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EliasLuiz/TCC | Leon3/designs/leon3-ahbfile/leon3mp.vhd | 1 | 6,398 | -- ahbfile demonstration design
-- Martin Aberg, 2015
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
library techmap;
use techmap.gencomp.all;
library gaisler;
use gaisler.leon3.all;
use gaisler.uart.all;
use gaisler.misc.all;
use work.config.all;
entity leon3mp is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW
);
port (
rstn : in std_ulogic;
clk : in std_ulogic
);
end;
architecture rtl of leon3mp is
constant nahbm : integer := CFG_NCPU*CFG_LEON3 + 1;
constant nahbs : integer := CFG_DSU*CFG_LEON3 + CFG_AHBRAMEN + 1;
signal apbi : apb_slv_in_type;
signal apbo : apb_slv_out_vector := (others => apb_none);
signal ahbsi : ahb_slv_in_type;
signal ahbso : ahb_slv_out_vector := (others => ahbs_none);
signal ahbmi : ahb_mst_in_type;
signal ahbmo : ahb_mst_out_vector := (others => ahbm_none);
signal u1i : uart_in_type;
signal u1o : uart_out_type;
signal irqi : irq_in_vector(0 to CFG_NCPU-1);
signal irqo : irq_out_vector(0 to CFG_NCPU-1);
signal dbgi : l3_debug_in_vector(0 to CFG_NCPU-1);
signal dbgo : l3_debug_out_vector(0 to CFG_NCPU-1);
signal dsui : dsu_in_type;
signal dsuo : dsu_out_type;
signal gpti : gptimer_in_type;
signal gpioi : gpio_in_type;
signal gpioo : gpio_out_type;
begin
ahb0 : ahbctrl
generic map (
defmast => CFG_DEFMST,
rrobin => CFG_RROBIN,
split => CFG_SPLIT,
fpnpen => CFG_FPNPEN,
ioaddr => CFG_AHBIO,
ioen => 1,
nahbm => nahbm,
nahbs => nahbs
)
port map (rstn, clk, ahbmi, ahbmo, ahbsi, ahbso);
l3 : if CFG_LEON3 = 1 generate
cpu : for i in 0 to CFG_NCPU-1 generate
u0 : leon3s
generic map (
i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU, CFG_V8, 0, CFG_MAC,
pclow, CFG_NOTAG, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE,
CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE,
CFG_DSETSZ, CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ,
CFG_ILRAMADDR, CFG_DLRAMEN, CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN,
CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP,
CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR, CFG_NCPU-1,
CFG_DFIXED, CFG_SCAN, CFG_MMU_PAGE, CFG_BP, CFG_NP_ASI, CFG_WRPSR
)
port map (
clk, rstn, ahbmi, ahbmo(i), ahbsi, ahbso, irqi(i), irqo(i), dbgi(i),
dbgo(i)
);
end generate;
-- errorn_pad : odpad generic map (tech => padtech) port map (errorn, dbgo(0).error);
dsugen : if CFG_DSU = 1 generate
dsu0 : dsu3
generic map (
hindex => 0,
haddr => 16#900#,
hmask => 16#F00#,
ncpu => CFG_NCPU,
tbits => 30,
tech => memtech,
irq => 0,
kbytes => CFG_ATBSZ
)
port map (
rstn, clk, ahbmi, ahbsi, ahbso(0), dbgo, dbgi, dsui, dsuo
);
dsui.enable <= '1';
dsui.break <= '0';
-- dsuen_pad : inpad generic map (tech => padtech) port map (dsuen, dsui.enable);
-- dsubre_pad : inpad generic map (tech => padtech) port map (dsubre, dsui.break);
-- dsuact_pad : outpad generic map (tech => padtech) port map (dsuact, dsuo.active);
end generate;
end generate;
nodsu : if CFG_DSU = 0 generate
dsuo.tstop <= '0';
dsuo.active <= '0';
end generate;
ahbfile0 : entity work.ahbfile
generic map (
hindex => nahbm-1
)
port map (
rstn,
clk,
ahbmi,
ahbmo(nahbm-1)
);
apb0 : apbctrl
generic map (
hindex => nahbs-1,
haddr => CFG_APBADDR
)
port map (rstn, clk, ahbsi, ahbso(nahbs-1), apbi, apbo);
ua1 : if CFG_UART1_ENABLE /= 0 generate
uart1 : apbuart
generic map (
pindex => 1,
paddr => 1,
pirq => 2,
console => dbguart,
fifosize => CFG_UART1_FIFO
)
port map (rstn, clk, apbi, apbo(1), u1i, u1o);
u1i.extclk <= '0';
u1i.ctsn <= '0';
u1i.rxd <= '1';
--txd1 <= u1o.txd;
end generate;
irqctrl : if CFG_IRQ3_ENABLE /= 0 generate
irqctrl0 : irqmp
generic map (
pindex => 2,
paddr => 2,
ncpu => CFG_NCPU
)
port map (rstn, clk, apbi, apbo(2), irqo, irqi);
end generate;
irq3 : if CFG_IRQ3_ENABLE = 0 generate
x : for i in 0 to CFG_NCPU-1 generate
irqi(i).irl <= "0000";
end generate;
end generate;
gpt : if CFG_GPT_ENABLE /= 0 generate
timer0 : gptimer
generic map (
pindex => 3,
paddr => 3,
pirq => CFG_GPT_IRQ,
sepirq => CFG_GPT_SEPIRQ,
sbits => CFG_GPT_SW,
ntimers => CFG_GPT_NTIM,
nbits => CFG_GPT_TW,
wdog => CFG_GPT_WDOG
)
port map (rstn, clk, apbi, apbo(3), gpti, open);
gpti <= gpti_dhalt_drive(dsuo.tstop);
end generate;
gpio0 : if CFG_GRGPIO_ENABLE /= 0 generate
grgpio0: grgpio
generic map (
pindex => 11,
paddr => 11,
imask => CFG_GRGPIO_IMASK,
nbits => CFG_GRGPIO_WIDTH
)
port map (rstn, clk, apbi, apbo(11), gpioi, gpioo);
-- pio_pads : for i in 0 to CFG_GRGPIO_WIDTH-1 generate
-- pio_pad : iopad
-- generic map (tech => padtech)
-- port map (gpio(i), gpioo.dout(i), gpioo.oen(i), gpioi.din(i));
-- end generate;
end generate;
ocram : if CFG_AHBRAMEN = 1 generate
ahbram0 : ahbram
generic map (
hindex => CFG_LEON3*CFG_DSU,
haddr => CFG_AHBRADDR,
tech => CFG_MEMTECH,
kbytes => CFG_AHBRSZ,
pipe => CFG_AHBRPIPE
)
port map (rstn, clk, ahbsi, ahbso(CFG_LEON3*CFG_DSU));
end generate;
-----------------------------------------------------------------------
--- Boot message ----------------------------------------------------
-----------------------------------------------------------------------
-- pragma translate_off
x : report_design
generic map (
msg1 => "LEON3 MP Demonstration design",
fabtech => tech_table(fabtech), memtech => tech_table(memtech),
mdel => 1
);
-- pragma translate_on
end;
| gpl-3.0 | a36e8a191cef72c9c45f34f422f176a5 | 0.559081 | 3.430563 | false | false | false | false |
EliasLuiz/TCC | Leon3/lib/techmap/maps/clkpad.vhd | 1 | 4,623 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: clkpad
-- File: clkpad.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: Clock pad with technology wrapper
------------------------------------------------------------------------------
library techmap;
library ieee;
use ieee.std_logic_1164.all;
use techmap.gencomp.all;
use techmap.allpads.all;
entity clkpad is
generic (tech : integer := 0; level : integer := 0;
voltage : integer := x33v; arch : integer := 0;
hf : integer := 0; filter : integer := 0);
port (pad : in std_ulogic; o : out std_ulogic; rstn : in std_ulogic := '1'; lock : out std_ulogic);
end;
architecture rtl of clkpad is
begin
gen0 : if has_pads(tech) = 0 generate
o <= to_X01(pad); lock <= '1';
end generate;
xcv2 : if (is_unisim(tech) = 1) generate
u0 : unisim_clkpad generic map (level, voltage, arch, hf, tech) port map (pad, o, rstn, lock);
end generate;
axc : if (tech = axcel) or (tech = axdsp) generate
u0 : axcel_clkpad generic map (level, voltage, arch) port map (pad, o); lock <= '1';
end generate;
pa : if (tech = proasic) or (tech = apa3) generate
u0 : apa3_clkpad generic map (level, voltage) port map (pad, o); lock <= '1';
end generate;
pa3e : if (tech = apa3e) generate
u0 : apa3e_clkpad generic map (level, voltage) port map (pad, o); lock <= '1';
end generate;
igl2 : if (tech = igloo2) or (tech = rtg4) generate
u0 : igloo2_clkpad port map (pad, o); lock <= '1';
end generate;
pa3l : if (tech = apa3l) generate
u0 : apa3l_clkpad generic map (level, voltage) port map (pad, o); lock <= '1';
end generate;
fus : if (tech = actfus) generate
u0 : fusion_clkpad generic map (level, voltage) port map (pad, o); lock <= '1';
end generate;
atc : if (tech = atc18s) generate
u0 : atc18_clkpad generic map (level, voltage) port map (pad, o); lock <= '1';
end generate;
atcrh : if (tech = atc18rha) generate
u0 : atc18rha_clkpad generic map (level, voltage) port map (pad, o); lock <= '1';
end generate;
um : if (tech = umc) generate
u0 : umc_inpad generic map (level, voltage) port map (pad, o); lock <= '1';
end generate;
rhu : if (tech = rhumc) generate
u0 : rhumc_inpad generic map (level, voltage, filter) port map (pad, o); lock <= '1';
end generate;
saed : if (tech = saed32) generate
u0 : saed32_inpad generic map (level, voltage) port map (pad, o); lock <= '1';
end generate;
rhs : if (tech = rhs65) generate
u0 : rhs65_inpad generic map (level, voltage) port map (pad, o); lock <= '1';
end generate;
dar : if (tech = dare) generate
u0 : dare_inpad generic map (level, voltage) port map (pad, o); lock <= '1';
end generate;
ihp : if (tech = ihp25) generate
u0 : ihp25_clkpad generic map (level, voltage) port map (pad, o); lock <= '1';
end generate;
rh18t : if (tech = rhlib18t) generate
u0 : rh_lib18t_inpad port map (pad, o); lock <= '1';
end generate;
ut025 : if (tech = ut25) generate
u0 : ut025crh_inpad port map (pad, o); lock <= '1';
end generate;
ut13 : if (tech = ut130) generate
u0 : ut130hbd_inpad generic map (level, voltage, filter)
port map (pad, o); lock <= '1';
end generate;
ut9 : if (tech = ut90) generate
u0 : ut90nhbd_inpad port map (pad, o); lock <= '1';
end generate;
pere : if (tech = peregrine) generate
u0 : peregrine_inpad port map (pad, o); lock <= '1';
end generate;
n2x : if (tech = easic45) generate
u0 : n2x_inpad generic map (level, voltage) port map (pad, o); lock <= '1';
end generate;
end;
| gpl-3.0 | e476e1decb8b23df5787200ad6612b0b | 0.617564 | 3.452577 | false | false | false | false |
pwsoft/fpga_examples | rtl/video/video_dither_mult.vhd | 1 | 3,124 | -- -----------------------------------------------------------------------
--
-- Syntiac VHDL support files.
--
-- -----------------------------------------------------------------------
-- Copyright 2005-2009 by Peter Wendrich ([email protected])
-- http://www.syntiac.com
--
-- This source file is free software: you can redistribute it and/or modify
-- it under the terms of the GNU Lesser General Public License as published
-- by the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This source file is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
-- -----------------------------------------------------------------------
--
-- Video dither block. Converts high precision video signal to
-- lower precision by dithering. The dither input can for example
-- come from the current X and Y coordinates or a pseudo random source.
--
-- Improved version of the video_dither.vhd using a multiplier and scaler
-- to have a more linear output range. The original has a tendency to clip
-- at higher output levels.
--
-- If bypass input is 1 the dither algorithm is disabled and the output
-- is equal to the input.
--
-- This component has a delay of one clock cycle.
--
-- -----------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.ALL;
-- -----------------------------------------------------------------------
entity video_dither is
generic (
dBits : integer := 8;
qBits : integer := 5;
ditherBits : integer := 4;
scaler_bits : integer := 9
);
port (
clk : in std_logic;
clkEna : in std_logic := '1';
bypass : in std_logic := '0';
dither : in unsigned(ditherBits-1 downto 0);
d : in unsigned(dBits-1 downto 0);
q : out unsigned(qBits-1 downto 0)
);
end entity;
-- -----------------------------------------------------------------------
architecture rtl of video_dither is
constant input_bits : integer := dBits + 1;
constant output_bits : integer := scaler_bits + input_bits;
constant scaler_const : integer := (2**(output_bits-1)-1) / ((2**dBits)+(2**ditherBits)-2);
signal q_reg : unsigned(q'range) := (others => '0');
begin
assert(dither'length <= d'length);
q <= q_reg;
process(clk)
variable input : unsigned(input_bits-1 downto 0);
variable scaler : unsigned(scaler_bits-1 downto 0);
variable output : unsigned(output_bits-1 downto 0);
begin
input := ("0" & d) + dither;
scaler := to_unsigned(scaler_const, scaler_bits);
output := input * scaler;
if rising_edge(clk) then
if clkEna = '1' then
q_reg <= output(output'high-1 downto output'high-q'length);
if bypass = '1' then
q_reg <= d(d'high downto (d'high-q'high));
end if;
end if;
end if;
end process;
end architecture;
| lgpl-2.1 | 833eb3580ef7d03adf9ec47edacaaeb0 | 0.59379 | 3.809756 | false | false | false | false |
ARC-Lab-UF/UAA | src/fifo_core.vhd | 1 | 12,482 | -- Copyright (c) 2015 University of Florida
--
-- This file is part of uaa.
--
-- uaa is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- uaa is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with uaa. If not, see <http://www.gnu.org/licenses/>.
-- Greg Stitt
-- University of Florida
-- Description:
-- This file implements the fifo_core entity, which defines the architecture the
-- fifo entity (see fifo.vhd).
--
-- The entity contains architectures for using flips (FF) or memory (MEMORY)
-- when synthesized.
-- Notes:
-- The fifo protects against invalid writes (i.e. when full) and invalid reads
-- (i.e. when empty)
--
-- use_bram = true and same_cycle_output = true is not supported by
-- all FPGAs.
--
-- All FIFO depths are currently rounded up to the nearest power of two.
-- Used entities:
-- ram (in BRAM architecture)
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.math_custom.all;
-------------------------------------------------------------------------------
-- Generics Description
-- width : the width of the FIFO in bits (required)
-- depth : the depth of the FIFO in words (required)
-- use_bram : uses bram when true, uses LUTs/FFs when false (required)
-- same_cycle_output : output appears in same cycle as read when true, one
-- cycle later when false (required)
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Port Description:
-- clk : clock input
-- rst : reset input (asynchronous)
-- rd : read input (active high)
-- wr : write input (active high)
-- empty : empty output (active high)
-- full : full output (active high)
-- input : fifo input
-- output : fifo output
-------------------------------------------------------------------------------
entity fifo_core is
generic(width : positive;
depth : positive;
use_bram : boolean;
same_cycle_output : boolean);
port(clk : in std_logic;
rst : in std_logic;
rd : in std_logic;
wr : in std_logic;
empty : out std_logic;
full : out std_logic;
input : in std_logic_vector(width-1 downto 0);
output : out std_logic_vector(width-1 downto 0));
end fifo_core;
-- FF architecture
-- This architecture implements the FIFO with flip-flops
architecture FF of fifo_core is
type reg_array is array (0 to depth-1) of std_logic_vector(width-1 downto 0);
signal regs : reg_array;
signal count, next_count : unsigned(bitsNeeded(depth)-1 downto 0);
signal valid_wr : std_logic;
signal valid_rd : std_logic;
signal empty_s : std_logic;
signal full_s : std_logic;
begin
-- create a shift register to act as the fifo
-- always writes to register 0
process(clk, rst)
begin
if (rst = '1') then
-- initialize all registers to 0 (unnessary, useful for debugging)
for i in 0 to depth-1 loop
regs(i) <= (others => '0');
end loop;
elsif (rising_edge(clk)) then
-- shift in input everytime there is a valid write
if (valid_wr = '1') then
regs(0) <= input;
for i in 0 to depth-2 loop
regs(i+1) <= regs(i);
end loop;
end if;
end if;
end process;
-- assign the 1-cycle delayed output if applicable
U_OUTPUT_NEXT_CYCLE : if same_cycle_output = false generate
process(clk, rst)
begin
if (rst = '1') then
output <= (others => '0');
elsif(rising_edge(clk)) then
-- count-1 is the front of the fifo
if (count = 0) then
-- special case when fifo is empty. One alternative is to
-- increase the fifo depth to be a power of two,
-- in which case this isn't necessary.
output <= regs(0);
else
output <= regs(to_integer(count-1));
end if;
end if;
end process;
end generate;
-- assign the output in the same cycle if applicable
U_OUTPUT_SAME_CYCLE : if same_cycle_output = true generate
process(regs, count)
begin
-- count-1 is the front of the fifo
if (count = 0) then
-- special case when fifo is empty. One alternative is to
-- require the fifo depth to be a power of two,
-- in which case this isn't necessary.
output <= regs(0);
else
output <= regs(to_integer(count-1));
end if;
end process;
end generate;
-- update empty flag
empty_s <= '1' when count = 0 else '0';
empty <= empty_s;
-- update full flag
full_s <= '0' when rd = '1' else
'1' when count = depth else '0';
full <= full_s;
-- determine valid write and read
valid_wr <= wr and not full_s;
valid_rd <= rd and not empty_s;
-- update count based on read and write signals
process(valid_rd, valid_wr, count)
variable count_v : unsigned(bitsNeeded(depth)-1 downto 0);
begin
count_v := count;
if (valid_rd = '1' and valid_wr = '0') then
count_v := count_v - 1;
elsif (valid_rd = '0' and valid_wr = '1') then
count_v := count_v + 1;
end if;
next_count <= count_v;
end process;
-- create count register
process(clk, rst)
begin
if (rst = '1') then
count <= to_unsigned(0, count'length);
elsif (clk'event and clk = '1') then
count <= next_count;
end if;
end process;
end FF;
architecture MEMORY of fifo_core is
signal rd_addr : unsigned(bitsNeeded(depth-1)-1 downto 0);
signal rd_addr_adjusted : unsigned(bitsNeeded(depth-1)-1 downto 0);
signal wr_addr : unsigned(bitsNeeded(depth-1)-1 downto 0);
signal ram_out : std_logic_vector(width-1 downto 0);
signal valid_wr : std_logic;
signal valid_rd : std_logic;
signal empty_s : std_logic;
signal full_s : std_logic;
begin
-- implement FIFO using BRAM
BRAM : if use_bram = true generate
SAME_CYCLE : if same_cycle_output = true generate
-- adjust the rd address to account for the one cycle delay in the
-- block ram. This ensures that the correct output remains until
-- the the next read. When a read does occur, this reads the next
-- location in memory to ensure that data is available on the next
-- cycle.
rd_addr_adjusted <= rd_addr when valid_rd = '0' else rd_addr+1;
-- use RAM with synchronous read during write. This is necessary to
-- ensure that an output is available 1 cycle after a write, which
-- is the same time that the empty flag is cleared.
U_RAM : entity work.ram(SYNC_READ_DURING_WRITE)
generic map (
word_width => width,
addr_width => bitsNeeded(depth-1),
num_words => 2**bitsNeeded(depth-1))
port map (
clk => clk,
wen => valid_wr,
waddr => std_logic_vector(wr_addr),
wdata => input,
raddr => std_logic_vector(rd_addr_adjusted),
rdata => ram_out);
-- avoid warning about unused signal
output <= ram_out;
end generate SAME_CYCLE;
NOT_SAME_CYCLE : if same_cycle_output = false generate
-- avoids warning about unused signal for these generics
rd_addr_adjusted <= rd_addr;
-- use RAM with synchronous reads
U_RAM : entity work.ram(SYNC_READ)
generic map (
word_width => width,
addr_width => bitsNeeded(depth-1),
num_words => 2**bitsNeeded(depth-1))
port map (
clk => clk,
wen => valid_wr,
waddr => std_logic_vector(wr_addr),
wdata => input,
raddr => std_logic_vector(rd_addr_adjusted),
rdata => ram_out);
-- avoid warning about unused signal
output <= ram_out;
end generate NOT_SAME_CYCLE;
end generate BRAM;
-- implement FIFO using distributed RAM, LUTs, or any RAM that supports
-- asynchronous reads
-- synthesis tools might convert this to another resource if FPGA memory
-- does not support asynchronous reads
DIST_RAM : if use_bram = false generate
SAME_CYCLE : if same_cycle_output = true generate
-- avoids warning about unused signal for these generics
rd_addr_adjusted <= rd_addr;
-- use RAM with asynchronous reads (not supported by all FPGAs)
U_RAM : entity work.ram(ASYNC_READ)
generic map (
word_width => width,
addr_width => bitsNeeded(depth-1),
num_words => 2**bitsNeeded(depth-1))
port map (
clk => clk,
wen => valid_wr,
waddr => std_logic_vector(wr_addr),
wdata => input,
raddr => std_logic_vector(rd_addr_adjusted),
rdata => ram_out);
-- avoids warning about unused signal for these generics
output <= ram_out;
end generate SAME_CYCLE;
NOT_SAME_CYCLE : if same_cycle_output = false generate
-- avoids warning about unused signal for these generics
rd_addr_adjusted <= rd_addr;
-- use RAM with asynchronous reads (not supported by all FPGAs)
U_RAM : entity work.ram(ASYNC_READ)
generic map (
word_width => width,
addr_width => bitsNeeded(depth-1),
num_words => 2**bitsNeeded(depth-1))
port map (
clk => clk,
wen => valid_wr,
waddr => std_logic_vector(wr_addr),
wdata => input,
raddr => std_logic_vector(rd_addr_adjusted),
rdata => ram_out);
-- add a register to delay the output by a cycle
process(clk, rst)
begin
if (rst = '1') then
output <= (others => '0');
elsif (rising_edge(clk)) then
output <= ram_out;
end if;
end process;
end generate NOT_SAME_CYCLE;
end generate DIST_RAM;
-- update empty flag
empty_s <= '1' when wr_addr = rd_addr else '0';
empty <= empty_s;
-- update full flag
full_s <= '0' when rd = '1' else
'1' when wr_addr + 1 = rd_addr else '0';
full <= full_s;
-- determine valid write and read
valid_wr <= wr and not full_s;
valid_rd <= rd and not empty_s;
-- update wr and rd addresses
process(clk, rst)
begin
if (rst = '1') then
wr_addr <= (others => '0');
rd_addr <= (others => '0');
elsif rising_edge(clk) then
if (valid_rd = '1') then
rd_addr <= rd_addr + 1;
end if;
if (valid_wr = '1') then
wr_addr <= wr_addr + 1;
end if;
end if;
end process;
end MEMORY;
| gpl-3.0 | dd824dad358597d99e6f69da17d3de9f | 0.518747 | 4.370448 | false | false | false | false |
EliasLuiz/TCC | Leon3/lib/gaisler/pci/grpci2/pcilib2.vhd | 1 | 14,216 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: pcilib2
-- File: pcilib2.vhd
-- Author: Nils-Johan Wessman - Aeroflex Gaisler
-- Description: Package with type declarations for PCI registers & constants
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
library gaisler;
use gaisler.pci.pci_in_type;
use gaisler.pci.pci_out_type;
package pcilib2 is
-- Constants for PCI commands
constant INT_ACK : std_logic_vector(3 downto 0) := "0000";
constant SPEC_CYCLE : std_logic_vector(3 downto 0) := "0001";
constant IO_READ : std_logic_vector(3 downto 0) := "0010";
constant IO_WRITE : std_logic_vector(3 downto 0) := "0011";
constant MEM_READ : std_logic_vector(3 downto 0) := "0110";
constant MEM_WRITE : std_logic_vector(3 downto 0) := "0111";
constant CONF_READ : std_logic_vector(3 downto 0) := "1010";
constant CONF_WRITE : std_logic_vector(3 downto 0) := "1011";
constant MEM_R_MULT : std_logic_vector(3 downto 0) := "1100";
constant DAC : std_logic_vector(3 downto 0) := "1101";
constant MEM_R_LINE : std_logic_vector(3 downto 0) := "1110";
constant MEM_W_INV : std_logic_vector(3 downto 0) := "1111";
type pci_config_command_type is record
ioen : std_logic; -- I/O access enable
memen : std_logic; -- Memory access enable
msten : std_logic; -- Master enable
-- spcen : std_logic; -- Special cycle enable
mwien : std_logic; -- Memory write and invalidate enable
-- vgaps : std_logic; -- VGA palette snooping enable
perren : std_logic; -- Parity error response enable
serren : std_logic; -- SERR error response enable
intdis : std_logic; -- Interrupt disable
-- wcc : std_logic; -- Address stepping enable
-- serre : std_logic; -- Enable SERR# driver
-- fbtbe : std_logic; -- Fast back-to-back enable
end record;
constant pci_config_command_none : pci_config_command_type := ('0','0','0','0','0','0','0');
type pci_config_status_type is record
intsta : std_logic; -- Interrupt status
-- c66mhz : std_logic; -- 66MHz capability
-- udf : std_logic; -- UDF supported
-- fbtbc : std_logic; -- Fast back-to-back capability
mdpe : std_logic; -- Master data parity error
-- dst : std_logic_vector(1 downto 0); -- DEVSEL timing
sta : std_logic; -- Signaled target abort
rta : std_logic; -- Received target abort
rma : std_logic; -- Received master abort
sse : std_logic; -- Signaled system error
dpe : std_logic; -- Detected parity error
end record;
constant pci_config_status_none : pci_config_status_type := ('0','0','0','0','0','0','0');
----type pci_config_type is record
---- conf_en : std_logic;
---- bus : std_logic_vector(7 downto 0);
---- dev : std_logic_vector(4 downto 0);
---- func : std_logic_vector(2 downto 0);
---- reg : std_logic_vector(5 downto 0);
---- data : std_logic_vector(31 downto 0);
----end record;
type pci_sigs_type is record
ad : std_logic_vector(31 downto 0);
cbe : std_logic_vector(3 downto 0);
frame : std_logic; -- Master frame
devsel : std_logic; -- PCI device select
trdy : std_logic; -- Target ready
irdy : std_logic; -- Master ready
stop : std_logic; -- Target stop request
par : std_logic; -- PCI bus parity
req : std_logic; -- Master bus request
perr : std_logic; -- Parity Error
serr : std_logic;
oe_par : std_logic;
oe_ad : std_logic;
oe_ctrl : std_logic;
oe_cbe : std_logic;
oe_frame : std_logic;
oe_irdy : std_logic;
oe_req : std_logic;
oe_perr : std_logic;
oe_serr : std_logic;
end record;
--type pci_target_state_type is (pt_idle, pt_b_busy, pt_s_data, pt_backoff, pt_turn_ar);
subtype pci_target_state_type is std_logic_vector(2 downto 0);
constant pt_idle : std_logic_vector(2 downto 0) := "000";
constant pt_b_busy : std_logic_vector(2 downto 0) := "001";
constant pt_s_data : std_logic_vector(2 downto 0) := "010";
constant pt_backoff : std_logic_vector(2 downto 0) := "011";
constant pt_turn_ar : std_logic_vector(2 downto 0) := "100";
--type pci_target_fifo_state_type is (ptf_idle, ptf_fifo, ptf_cwrite, ptf_write);
subtype pci_target_fifo_state_type is std_logic_vector(1 downto 0);
constant ptf_idle : std_logic_vector(1 downto 0) := "00";
constant ptf_fifo : std_logic_vector(1 downto 0) := "01";
constant ptf_cwrite : std_logic_vector(1 downto 0) := "10";
constant ptf_write : std_logic_vector(1 downto 0) := "11";
--type pci_master_state_type is (pm_idle, pm_addr, pm_m_data, pm_turn_ar, pm_s_tar, pm_dr_bus);
subtype pci_master_state_type is std_logic_vector(2 downto 0);
constant pm_idle : std_logic_vector(2 downto 0) := "000";
constant pm_addr : std_logic_vector(2 downto 0) := "001";
constant pm_m_data : std_logic_vector(2 downto 0) := "010";
constant pm_turn_ar : std_logic_vector(2 downto 0) := "011";
constant pm_s_tar : std_logic_vector(2 downto 0) := "100";
constant pm_dr_bus : std_logic_vector(2 downto 0) := "101";
--type pci_master_fifo_state_type is (pmf_idle, pmf_fifo, pmf_read);
subtype pci_master_fifo_state_type is std_logic_vector(1 downto 0);
constant pmf_idle : std_logic_vector(1 downto 0) := "00";
constant pmf_fifo : std_logic_vector(1 downto 0) := "01";
constant pmf_read : std_logic_vector(1 downto 0) := "10";
type pci_core_fifo_type is record
data : std_logic_vector(31 downto 0); -- 32 bit FIFO data
last : std_logic; -- Last word in FIFO
stlast: std_logic; -- Second to last word in FIFO
hold : std_logic;
valid : std_logic; -- Contains valid data
err : std_logic; -- signal target-abort
end record;
constant pci_core_fifo_none : pci_core_fifo_type := ((others => '0'), '0', '0', '0', '0', '0');
type pci_core_fifo_vector_type is array (0 to 2) of pci_core_fifo_type;
constant pci_core_fifo_vector_none : pci_core_fifo_vector_type := (others => pci_core_fifo_none);
type pci_reg_in_type is record
ad : std_logic_vector(31 downto 0); -- PCI address/data
cbe : std_logic_vector(3 downto 0); -- PCI command/byte enable
frame : std_logic; -- Master frame
devsel : std_logic; -- PCI device select
trdy : std_logic; -- Target ready
irdy : std_logic; -- Master ready
stop : std_logic; -- Target stop request
par : std_logic; -- PCI bus parity
perr : std_logic; -- Parity error
serr : std_logic; -- System error
gnt : std_logic; -- Master grant
idsel : std_logic; -- PCI configuration device select
end record;
type pci_reg_out_type is record
ad : std_logic_vector(31 downto 0); -- PCI address/data
aden : std_logic_vector(31 downto 0); -- PCI address/data [enable]
cbe : std_logic_vector(3 downto 0); -- PCI command/byte enable
cbeen : std_logic_vector(3 downto 0); -- PCI command/byte enable [enable]
frame : std_logic; -- Master frame
frameen : std_logic; -- Master frame [enable]
irdy : std_logic; -- Master ready
irdyen : std_logic; -- Master ready [enable]
trdy : std_logic; -- Target ready
trdyen : std_logic; -- Target ready [enable]
stop : std_logic; -- Target stop request
stopen : std_logic; -- Target stop request [enable]
devsel : std_logic; -- PCI device select
devselen: std_logic; -- PCI device select [enable]
par : std_logic; -- PCI bus parity
paren : std_logic; -- PCI bus parity [enable]
perr : std_logic; -- Parity error
perren : std_logic; -- Parity error [enable]
lock : std_logic; -- PCI lock
locken : std_logic; -- PCI lock [enable]
req : std_logic; -- Master request
reqen : std_logic; -- Master request [enable]
serren : std_logic; -- System error
inten : std_logic; -- PCI interrupt [enable]
vinten : std_logic_vector(3 downto 0); -- PCI interrupt [enable]
serr : std_logic; -- SERR value, constant 0 - included for iotest
end record;
type grpci2_phy_in_type is record
pcirstout : std_logic;
pciasyncrst : std_logic;
pcisoftrst : std_logic_vector(2 downto 0);
pciinten : std_logic_vector(3 downto 0);
m_request : std_logic;
m_mabort : std_logic;
pr_m_fstate : pci_master_fifo_state_type;
pr_m_cfifo : pci_core_fifo_vector_type;
pv_m_cfifo : pci_core_fifo_vector_type;
pr_m_addr : std_logic_vector(31 downto 0);
pr_m_cbe_data : std_logic_vector(3 downto 0);
pr_m_cbe_cmd : std_logic_vector(3 downto 0);
pr_m_first : std_logic_vector(1 downto 0);
pv_m_term : std_logic_vector(1 downto 0);
pr_m_ltimer : std_logic_vector(7 downto 0);
pr_m_burst : std_logic;
pr_m_abort : std_logic_vector(0 downto 0);
pr_m_perren : std_logic_vector(0 downto 0);
pr_m_done_fifo : std_logic;
t_abort : std_logic;
t_ready : std_logic;
t_retry : std_logic;
pr_t_state : pci_target_state_type;
pv_t_state : pci_target_state_type;
pr_t_fstate : pci_target_fifo_state_type;
pr_t_cfifo : pci_core_fifo_vector_type;
pv_t_diswithout : std_logic;
pr_t_stoped : std_logic;
pr_t_lcount : std_logic_vector(2 downto 0);
pr_t_first_word : std_logic;
pr_t_cur_acc_0_read : std_logic;
pv_t_hold_write : std_logic;
pv_t_hold_reset : std_logic;
pr_conf_comm_perren : std_logic;
pr_conf_comm_serren : std_logic;
testen : std_logic;
testoen : std_logic;
testrst : std_logic;
end record;
type grpci2_phy_out_type is record
pciv : pci_in_type;
pr_m_state : pci_master_state_type;
pr_m_last : std_logic_vector(1 downto 0);
pr_m_hold : std_logic_vector(1 downto 0);
pr_m_term : std_logic_vector(1 downto 0);
pr_t_hold : std_logic_vector(0 downto 0);
pr_t_stop : std_logic;
pr_t_abort : std_logic;
pr_t_diswithout : std_logic;
pr_t_addr_perr : std_logic;
pcirsto : std_logic_vector(0 downto 0);
pr_po : pci_reg_out_type;
pio : pci_in_type;
poo : pci_reg_out_type;
end record;
component grpci2_phy is
generic(
tech : integer := 0;
oepol : integer := 0;
bypass : integer range 0 to 1 := 1;
netlist : integer := 0;
scantest: integer := 0;
iotest : integer := 0
);
port(
pciclk : in std_logic;
pcii : in pci_in_type;
phyi : in grpci2_phy_in_type;
pcio : out pci_out_type;
phyo : out grpci2_phy_out_type;
iotmact : in std_ulogic;
iotmoe : in std_ulogic;
iotdout : in std_logic_vector(44 downto 0);
iotdin : out std_logic_vector(45 downto 0)
);
end component;
component grpci2_phy_wrapper is
generic(
tech : integer := 0;
oepol : integer := 0;
bypass : integer range 0 to 1 := 1;
netlist : integer := 0;
scantest: integer := 0;
iotest : integer := 0
);
port(
pciclk : in std_logic;
pcii : in pci_in_type;
phyi : in grpci2_phy_in_type;
pcio : out pci_out_type;
phyo : out grpci2_phy_out_type;
iotmact : in std_ulogic;
iotmoe : in std_ulogic;
iotdout : in std_logic_vector(44 downto 0);
iotdin : out std_logic_vector(45 downto 0)
);
end component;
component grpci2_ahbmst is
generic (
hindex : integer := 0;
hirq : integer := 0;
venid : integer := VENDOR_GAISLER;
devid : integer := 0;
version : integer := 0;
chprot : integer := 3;
incaddr : integer := 0);
port (
rst : in std_ulogic;
clk : in std_ulogic;
dmai : in ahb_dma_in_type;
dmao : out ahb_dma_out_type;
ahbi : in ahb_mst_in_type;
ahbo : out ahb_mst_out_type
);
end component;
type dma_ahb_in_type is record
req : std_ulogic;
write : std_ulogic;
addr : std_logic_vector(31 downto 0);
data : std_logic_vector(31 downto 0);
size : std_logic_vector(1 downto 0);
noreq : std_logic;
burst : std_logic;
end record;
constant dma_ahb_in_none : dma_ahb_in_type := ('0', '0', (others => '0'),
(others => '0'), (others => '0'), '0', '0');
type dma_ahb_out_type is record
grant : std_ulogic;
ready : std_ulogic;
error : std_ulogic;
retry : std_ulogic;
data : std_logic_vector(31 downto 0);
end record;
component grpci2_ahb_mst is
generic(
hindex : integer := 0;
venid : integer := VENDOR_GAISLER;
devid : integer := 0;
version : integer := 0
);
port(
rst : in std_ulogic;
clk : in std_ulogic;
ahbmi : in ahb_mst_in_type;
ahbmo : out ahb_mst_out_type;
dmai0 : in dma_ahb_in_type;
dmao0 : out dma_ahb_out_type;
dmai1 : in dma_ahb_in_type;
dmao1 : out dma_ahb_out_type
);
end component;
end ;
| gpl-3.0 | f95a00d530df2bf6fd9e8d1554e21a03 | 0.603053 | 3.180313 | false | false | false | false |
EliasLuiz/TCC | Leon3/lib/gaisler/leon3v3/proc3.vhd | 1 | 6,949 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: proc3
-- File: proc3.vhd
-- Author: Jiri Gaisler Gaisler Research
-- Description: LEON3 processor core with pipeline, mul/div & cache control
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
library techmap;
use techmap.gencomp.all;
library gaisler;
use gaisler.leon3.all;
use gaisler.libiu.all;
use gaisler.libcache.all;
use gaisler.arith.all;
use gaisler.libleon3.all;
use gaisler.libfpu.all;
entity proc3 is
generic (
hindex : integer := 0;
fabtech : integer range 0 to NTECH := 0;
memtech : integer := 0;
nwindows : integer range 2 to 32 := 8;
dsu : integer range 0 to 1 := 0;
fpu : integer range 0 to 15 := 0;
v8 : integer range 0 to 63 := 0;
cp : integer range 0 to 1 := 0;
mac : integer range 0 to 1 := 0;
pclow : integer range 0 to 2 := 2;
notag : integer range 0 to 1 := 0;
nwp : integer range 0 to 4 := 0;
icen : integer range 0 to 1 := 0;
irepl : integer range 0 to 3 := 2;
isets : integer range 1 to 4 := 1;
ilinesize : integer range 4 to 8 := 4;
isetsize : integer range 1 to 256 := 1;
isetlock : integer range 0 to 1 := 0;
dcen : integer range 0 to 1 := 0;
drepl : integer range 0 to 3 := 2;
dsets : integer range 1 to 4 := 1;
dlinesize : integer range 4 to 8 := 4;
dsetsize : integer range 1 to 256 := 1;
dsetlock : integer range 0 to 1 := 0;
dsnoop : integer range 0 to 7 := 0;
ilram : integer range 0 to 2 := 0;
ilramsize : integer range 1 to 512 := 1;
ilramstart : integer range 0 to 255 := 16#8e#;
dlram : integer range 0 to 2 := 0;
dlramsize : integer range 1 to 512 := 1;
dlramstart : integer range 0 to 255 := 16#8f#;
mmuen : integer range 0 to 1 := 0;
itlbnum : integer range 2 to 64 := 8;
dtlbnum : integer range 2 to 64 := 8;
tlb_type : integer range 0 to 3 := 1;
tlb_rep : integer range 0 to 1 := 0;
lddel : integer range 1 to 2 := 2;
disas : integer range 0 to 2 := 0;
tbuf : integer range 0 to 128 := 0;
pwd : integer range 0 to 2 := 0;
svt : integer range 0 to 1 := 0;
rstaddr : integer := 0;
smp : integer range 0 to 15 := 0;
cached : integer := 0;
clk2x : integer := 0;
scantest : integer := 0;
mmupgsz : integer range 0 to 5 := 0;
bp : integer := 1;
npasi : integer range 0 to 1 := 0;
pwrpsr : integer range 0 to 1 := 0;
rex : integer := 0;
altwin : integer range 0 to 1 := 0
);
port (
clk : in std_ulogic;
rstn : in std_ulogic;
holdn : out std_ulogic;
ahbi : in ahb_mst_in_type;
ahbo : out ahb_mst_out_type;
ahbsi : in ahb_slv_in_type;
ahbso : in ahb_slv_out_vector;
rfi : out iregfile_in_type;
rfo : in iregfile_out_type;
crami : out cram_in_type;
cramo : in cram_out_type;
tbi : out tracebuf_in_type;
tbo : in tracebuf_out_type;
tbi_2p : out tracebuf_2p_in_type;
tbo_2p : in tracebuf_2p_out_type;
fpi : out fpc_in_type;
fpo : in fpc_out_type;
cpi : out fpc_in_type;
cpo : in fpc_out_type;
irqi : in l3_irq_in_type;
irqo : out l3_irq_out_type;
dbgi : in l3_debug_in_type;
dbgo : out l3_debug_out_type;
hclk, sclk : in std_ulogic;
hclken : in std_ulogic
);
end;
architecture rtl of proc3 is
constant IRFWT : integer := 1;
signal ici : icache_in_type;
signal ico : icache_out_type;
signal dci : dcache_in_type;
signal dco : dcache_out_type;
signal holdnx, pholdn : std_logic;
signal muli : mul32_in_type;
signal mulo : mul32_out_type;
signal divi : div32_in_type;
signal divo : div32_out_type;
begin
holdnx <= ico.hold and dco.hold and fpo.holdn; holdn <= holdnx;
pholdn <= fpo.holdn;
-- integer unit
iu : iu3
generic map (nwindows, isets, dsets, fpu, v8, cp, mac, dsu, nwp, pclow*(1-rex),
notag, hindex, lddel, IRFWT, disas, tbuf, pwd, svt, rstaddr, smp, fabtech,
clk2x, bp, npasi, pwrpsr, rex, altwin)
port map (clk, rstn, holdnx, ici, ico, dci, dco, rfi, rfo, irqi, irqo,
dbgi, dbgo, muli, mulo, divi, divo, fpo, fpi, cpo, cpi, tbo, tbi, tbo_2p, tbi_2p, sclk);
-- multiply and divide units
mgen : if v8 /= 0 generate
mul0 : mul32 generic map (fabtech, v8/16, (v8 mod 4)/2, mac, (v8 mod 16)/4)
port map (rstn, clk, holdnx, muli, mulo);
div0 : div32 port map (rstn, clk, holdnx, divi, divo);
end generate;
nomgen : if v8 = 0 generate
divo <= ('0', '0', "0000", zero32);
mulo <= ('0', '0', "0000", zero32&zero32);
end generate;
-- cache controller
c0mmu : mmu_cache
generic map (
hindex, fabtech, memtech, dsu, icen, irepl, isets, ilinesize, isetsize,
isetlock, dcen, drepl, dsets, dlinesize, dsetsize, dsetlock,
dsnoop, ilram, ilramsize, ilramstart, dlram, dlramsize, dlramstart,
itlbnum, dtlbnum, tlb_type, tlb_rep, cached,
clk2x, scantest, mmupgsz, smp, mmuen)
port map (rstn, clk, ici, ico, dci, dco, ahbi, ahbo, ahbsi, ahbso,
crami, cramo, pholdn, hclk, sclk, hclken
);
end;
| gpl-3.0 | 975501451a88539229fb8aaaac257f49 | 0.542956 | 3.585655 | false | false | false | false |
yishinli/emc2 | src/hal/drivers/mesa-hostmot2/firmware/src/I22HostMot2.vhd | 1 | 11,919 | library IEEE;
use IEEE.std_logic_1164.all; -- defines std_logic types
use IEEE.std_logic_ARITH.ALL;
use IEEE.std_logic_UNSIGNED.ALL;
Library UNISIM;
use UNISIM.vcomponents.all;
--
-- Copyright (C) 2007, Peter C. Wallace, Mesa Electronics
-- http://www.mesanet.com
--
-- This program is is licensed under a disjunctive dual license giving you
-- the choice of one of the two following sets of free software/open source
-- licensing terms:
--
-- * GNU General Public License (GPL), version 2.0 or later
-- * 3-clause BSD License
--
--
-- The GNU GPL License:
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
--
--
-- The 3-clause BSD License:
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- * Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- * Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- * Neither the name of Mesa Electronics nor the names of its
-- contributors may be used to endorse or promote products
-- derived from this software without specific prior written
-- permission.
--
--
-- Disclaimer:
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
use work.IDROMParms.all;
use work.NumberOfModules.all;
use work.MaxPinsPerModule.all;
-- This template works for the 5i22, 5i23 and 4i68
entity HM2_${prefix} is
generic
(
-- Note: all pinout/module count information is derived
-- from the PinDesc and ModuleID which are inserted here
-- by the build system, using data from the .spec file
ThePinDesc: PinDescType := ${pin_desc};
TheModuleID: ModuleIDType := ${module_id};
PWMRefWidth: integer := 13; -- PWM resolution is PWMRefWidth-1 bits, MSB is for symmetrical mode
IDROMType: integer := 2;
SepClocks: boolean := true;
OneWS: boolean := true;
UseStepGenPrescaler : boolean := true;
UseIRQLogic: boolean := true;
UseWatchDog: boolean := true;
OffsetToModules: integer := 64;
OffsetToPinDesc: integer := 512;
ClockHigh: integer := ClockHigh22;
ClockLow: integer := ClockLow22;
BoardNameLow : std_Logic_Vector(31 downto 0) := BoardNameMESA;
BoardNameHigh : std_Logic_Vector(31 downto 0) := BoardName${board_name};
-- 5I22-1000 = 1000, 5I22-1500 = 1500, 5I23 or 4I68 = 400
FPGASize: integer := ${fpga_size};
-- 5I22 = 320, 5I23 or 4I68 = 208
FPGAPins: integer := ${fpga_pins};
-- 5I22 = 4, 5I23 or 4I68 = 3
IOPorts: integer := ${io_ports};
-- 5I22 = 96, 5I23 or 4I68 = 72
IOWidth: integer := ${io_pins};
PortWidth: integer := 24;
BusWidth: integer := 32;
AddrWidth: integer := 16;
InstStride0: integer := 4;
InstStride1: integer := 16;
RegStride0: integer := 256;
RegStride1: integer := 4;
-- 5I22 = 8, 5I23 = 2, 4I68 = 4
LEDCount: integer := ${led_count}
);
port
(
-- bus interface signals --
-- LRD: in std_logic;
-- LWR: in std_logic;
LW_R: in std_logic;
-- ALE: in std_logic;
ADS: in std_logic;
BLAST: in std_logic;
-- WAITOUT: in std_logic;
-- LOCKO: in std_logic;
-- CS0: in std_logic;
-- CS1: in std_logic;
READY: out std_logic;
BTERM: out std_logic;
INT: out std_logic;
HOLD: in std_logic;
HOLDA: inout std_logic;
CCS: out std_logic;
-- RESET: in std_logic;
DISABLECONF: out std_logic;
LAD: inout std_logic_vector (31 downto 0); -- data/address bus
-- LA: in std_logic_vector (8 downto 2); -- non-muxed address bus
-- LBE: in std_logic_vector (3 downto 0); -- byte enables
IOBITS: inout std_logic_vector (IOWidth -1 downto 0);
LCLK: in std_logic;
-- led bits
LEDS: out std_logic_vector(LEDCount -1 downto 0)
);
end HM2_${prefix};
architecture dataflow of HM2_${prefix} is
-- alias SYNCLK: std_logic is LCLK;
-- misc global signals --
signal D: std_logic_vector (BusWidth-1 downto 0); -- internal data bus
signal DPipe: std_logic_vector (BusWidth-1 downto 0); -- read pipeline reg
signal LADPipe: std_logic_vector (BusWidth-1 downto 0); -- write pipeline reg
signal LW_RPipe: std_logic;
signal A: std_logic_vector (15 downto 2);
signal Read: std_logic;
signal ReadTSEn: std_logic;
signal Write: std_logic;
signal Burst: std_logic;
signal NextA: std_logic_vector (15 downto 2);
signal ReadyFF: std_logic;
-- CLK multiplier DCM signals
signal fclk : std_logic;
signal clkfx: std_logic;
signal clk0: std_logic;
-- Extract the number of modules of each type from the ModuleID
constant StepGens: integer := NumberOfModules(TheModuleID,StepGenTag);
constant QCounters: integer := NumberOfModules(TheModuleID,QCountTag);
constant MuxedQCounters: integer := NumberOfModules(TheModuleID,MuxedQCountTag);
constant PWMGens : integer := NumberOfModules(TheModuleID,PWMTag);
constant SPIs: integer := NumberOfModules(TheModuleID,SPITag);
constant BSPIs: integer := NumberOfModules(TheModuleID,BSPITag);
constant SSIs: integer := NumberOfModules(TheModuleID,SSITag);
constant UARTs: integer := NumberOfModules(TheModuleID,UARTRTag);
-- extract the needed Stepgen table width from the max pin# used with a stepgen tag
constant StepGenTableWidth: integer := MaxPinsPerModule(ThePinDesc,StepGenTag);
-- extract how many BSPI CS pins are needed from the max pin# used with a BSPI tag skipping the first 4
constant BSPICSWidth: integer := MaxPinsPerModule(ThePinDesc,BSPITag)-4;
begin
ClockMult : DCM
generic map (
CLKDV_DIVIDE => 2.0,
CLKFX_DIVIDE => 2,
CLKFX_MULTIPLY => 4, -- 4 FOR 96 MHz, 5 for 120
CLKIN_DIVIDE_BY_2 => FALSE,
CLKIN_PERIOD => 20.0,
CLKOUT_PHASE_SHIFT => "NONE",
CLK_FEEDBACK => "1X",
DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS",
DFS_FREQUENCY_MODE => "LOW",
DLL_FREQUENCY_MODE => "LOW",
DUTY_CYCLE_CORRECTION => TRUE,
FACTORY_JF => X"C080",
PHASE_SHIFT => 0,
STARTUP_WAIT => FALSE)
port map (
CLK0 => clk0, --
CLKFB => clk0, -- DCM clock feedback
CLKFX => clkfx,
CLKIN => LCLK, -- Clock input (from IBUFG, BUFG or DCM)
PSCLK => '0', -- Dynamic phase adjust clock input
PSEN => '0', -- Dynamic phase adjust enable input
PSINCDEC => '0', -- Dynamic phase adjust increment/decrement
RST => '0' -- DCM asynchronous reset input
);
BUFG_inst : BUFG
port map (
O => FClk, -- Clock buffer output
I => clkfx -- Clock buffer input
);
-- End of DCM_inst instantiation
ahostmot2: entity HostMot2
generic map (
thepindesc => ThePinDesc,
themoduleid => TheModuleID,
stepgens => StepGens,
qcounters => QCounters,
muxedqcounters => MuxedQCounters,
pwmgens => PWMGens,
spis => SPIs,
bspis => BSPIs,
ssis => SSIs,
uarts => UARTs,
pwmrefwidth => PWMRefWidth,
stepgentablewidth => StepGenTableWidth,
bspicswidth => BSPICSWidth,
idromtype => IDROMType,
sepclocks => SepClocks,
onews => OneWS,
usestepgenprescaler => UseStepGenPrescaler,
useirqlogic => UseIRQLogic,
usewatchdog => UseWatchDog,
offsettomodules => OffsetToModules,
offsettopindesc => OffsetToPinDesc,
clockhigh => ClockHigh,
clocklow => ClockLow,
boardnamelow => BoardNameLow,
boardnamehigh => BoardNameHigh,
fpgasize => FPGASize,
fpgapins => FPGAPins,
ioports => IOPorts,
iowidth => IOWidth,
portwidth => PortWidth,
buswidth => BusWidth,
addrwidth => AddrWidth,
inststride0 => InstStride0,
inststride1 => InstStride1,
regstride0 => RegStride0,
regstride1 => RegStride1,
ledcount => LEDCount
)
port map (
ibus => LADPipe,
obus => D,
addr => NextA,
read => Read,
write => Write,
clklow => LCLK,
clkhigh => FClk,
int => INT,
iobits => IOBITS,
leds => LEDS
);
LADDrivers: process (DPipe,ReadTSEn,LCLK)
begin
if rising_edge(LCLK) then
DPipe <= D;
LADPipe <= LAD;
end if;
if ReadTSEn ='1' then
LAD <= DPipe;
else
LAD <= "ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ";
end if;
end process LADDrivers;
BusCycleGen: process (LCLK,ADS, LAD, ReadyFF, A, Burst, LW_RPipe) -- added 1 wait state (read/write)
begin
if rising_edge(LCLK) then
A <= NextA; -- always update our latched address
if ADS = '0' then -- if *ADS then latch address & indicate start of burst
Burst <= '1';
end if;
if BLAST = '0' and ReadyFF= '1' then -- end of burst
Burst <= '0';
end if;
if OneWS then
if Burst = '1' then
ReadyFF <= not ReadyFF; -- just one wait state so toggle ReadyFF
else
ReadyFF <= '0'; -- idle not ready
end if;
else
ReadyFF <= '1'; -- always ready if OneWS not used
end if;
LW_RPipe <= LW_R;
end if; -- lclk
if ADS = '0' then -- NextA is combinatorial next address
NextA <= LAD(15 downto 2); -- we need this for address lookahead for block RAM
else
if ReadyFF = '1' then
NextA <= A+1;
else
NextA <= A;
end if;
end if;
Write <= Burst and LW_RPipe and ReadyFF; -- A write is any time during burst when LW_R is high and ReadyFF is high
-- Note that write writes the data from the LADPipe register to the destination
ReadTSEn <= Burst and not LW_RPipe; -- ReadTSEn is any time during burst when LW_R is low = tri state enable on DPipe output
Read <= Burst and not LW_RPipe and not ReadyFF; -- A read is any time during burst when LW_R is low and ReadyFF is low = internal read data enable to DPipe input
READY <= not ReadyFF; -- note: target only!
end process BusCycleGen;
Not4I68: if BoardNameHigh /= BoardName4I68 generate
DoHandshake: process (HOLD)
begin
HOLDA <= HOLD;
CCS <= '1';
DISABLECONF <= '0';
BTERM <= '1';
end process DoHandShake;
end generate;
Is4I68: if BoardNameHigh = BoardName4I68 generate -- because the standard 4I68 does not have CCS connected
DoHandshake: process (HOLD)
begin
HOLDA <= HOLD;
DISABLECONF <= 'Z';
BTERM <= '1';
end process DoHandShake;
end generate;
end dataflow;
| lgpl-2.1 | 44d636a02c987da113ee2b7e06eccb04 | 0.662136 | 3.308077 | false | false | false | false |
hoglet67/CoPro6502 | src/LX9Co_CoPro6502.vhd | 1 | 9,815 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity LX9CoPro6502 is
generic (
UseT65Core : boolean := false;
UseJensCore : boolean := false;
UseAlanDCore : boolean := true
);
port (
-- GOP Signals
fastclk : in std_logic;
test : inout std_logic_vector(8 downto 1);
sw : in std_logic_vector(3 downto 0);
-- Tube signals
h_phi2 : in std_logic;
h_addr : in std_logic_vector(2 downto 0);
h_data : inout std_logic_vector(7 downto 0);
h_rdnw : in std_logic;
h_cs_b : in std_logic;
h_rst_b : in std_logic;
h_irq_b : inout std_logic;
-- Ram Signals
ram_ub_b : out std_logic;
ram_lb_b : out std_logic;
ram_cs : out std_logic;
ram_oe : out std_logic;
ram_wr : out std_logic;
ram_addr : out std_logic_vector (18 downto 0);
ram_data : inout std_logic_vector (7 downto 0)
);
end LX9CoPro6502;
architecture BEHAVIORAL of LX9CoPro6502 is
-------------------------------------------------
-- clock and reset signals
-------------------------------------------------
signal clk_16M00 : std_logic;
signal phi0 : std_logic;
signal phi1 : std_logic;
signal phi2 : std_logic;
signal phi3 : std_logic;
signal cpu_clken : std_logic;
signal bootmode : std_logic;
signal RSTn : std_logic;
signal RSTn_sync : std_logic;
signal clken_counter : std_logic_vector (1 downto 0);
signal reset_counter : std_logic_vector (8 downto 0);
-------------------------------------------------
-- parasite signals
-------------------------------------------------
signal p_cs_b : std_logic;
signal p_data_out : std_logic_vector (7 downto 0);
-------------------------------------------------
-- ram/rom signals
-------------------------------------------------
signal ram_cs_b : std_logic;
signal ram_oe_int : std_logic;
signal ram_wr_int : std_logic;
signal rom_cs_b : std_logic;
signal rom_data_out : std_logic_vector (7 downto 0);
-------------------------------------------------
-- cpu signals
-------------------------------------------------
signal debug_clk : std_logic;
signal cpu_R_W_n : std_logic;
signal cpu_addr : std_logic_vector (23 downto 0);
signal cpu_addr_us: unsigned (23 downto 0);
signal cpu_din : std_logic_vector (7 downto 0);
signal cpu_dout : std_logic_vector (7 downto 0);
signal cpu_dout_us: unsigned (7 downto 0);
signal cpu_IRQ_n : std_logic;
signal cpu_NMI_n : std_logic;
signal cpu_IRQ_n_sync : std_logic;
signal cpu_NMI_n_sync : std_logic;
signal sync : std_logic;
begin
---------------------------------------------------------------------
-- instantiated components
---------------------------------------------------------------------
inst_ICAP_config : entity work.ICAP_config port map (
fastclk => fastclk,
sw_in => sw,
sw_out => open,
h_addr => h_addr,
h_cs_b => h_cs_b,
h_data => h_data,
h_phi2 => h_phi2,
h_rdnw => h_rdnw,
h_rst_b => h_rst_b
);
inst_dcm_32_16 : entity work.dcm_32_16 port map (
CLKIN_IN => fastclk,
CLK0_OUT => clk_16M00,
CLK0_OUT1 => open,
CLK2X_OUT => open
);
inst_tuberom : entity work.tuberom_65c102 port map (
CLK => clk_16M00,
ADDR => cpu_addr(10 downto 0),
DATA => rom_data_out
);
GenT65Core: if UseT65Core generate
inst_T65 : entity work.T65 port map (
Mode => "01",
Abort_n => '1',
SO_n => '1',
Res_n => RSTn_sync,
Enable => cpu_clken,
Clk => clk_16M00,
Rdy => '1',
IRQ_n => cpu_IRQ_n_sync,
NMI_n => cpu_NMI_n_sync,
R_W_n => cpu_R_W_n,
Sync => sync,
A(23 downto 0) => cpu_addr,
DI(7 downto 0) => cpu_din,
DO(7 downto 0) => cpu_dout
);
-- For debugging only
debug_clk <= cpu_clken;
end generate;
GenJensCore: if UseJensCore generate
Inst_r65c02_tc: entity work.r65c02_tc PORT MAP(
clk_clk_i => phi0,
d_i => cpu_din,
irq_n_i => cpu_IRQ_n_sync,
nmi_n_i => cpu_NMI_n_sync,
rdy_i => '1',
rst_rst_n_i => RSTn_sync,
so_n_i => '1',
a_o => cpu_addr(15 downto 0),
d_o => cpu_dout,
rd_o => open,
sync_o => sync,
wr_n_o => cpu_R_W_n,
wr_o => open
);
-- For debugging only
debug_clk <= phi0;
end generate;
GenAlanDCore: if UseAlanDCore generate
inst_r65c02: entity work.r65c02 port map(
reset => RSTn_sync,
clk => clk_16M00,
enable => cpu_clken,
nmi_n => cpu_NMI_n_sync,
irq_n => cpu_IRQ_n_sync,
di => unsigned(cpu_din),
do => cpu_dout_us,
addr => cpu_addr_us(15 downto 0),
nwe => cpu_R_W_n,
sync => sync,
sync_irq => open
);
cpu_dout <= std_logic_vector(cpu_dout_us);
cpu_addr <= std_logic_vector(cpu_addr_us);
-- For debugging only
debug_clk <= cpu_clken;
end generate;
inst_tube: entity work.tube port map (
h_addr => h_addr,
h_cs_b => h_cs_b,
h_data => h_data,
h_phi2 => h_phi2,
h_rdnw => h_rdnw,
h_rst_b => h_rst_b,
h_irq_b => h_irq_b,
p_addr => cpu_addr(2 downto 0),
p_cs_b => not((not p_cs_b) and cpu_clken),
p_data_in => cpu_dout,
p_data_out => p_data_out,
p_rdnw => cpu_R_W_n,
p_phi2 => clk_16M00,
p_rst_b => RSTn,
p_nmi_b => cpu_NMI_n,
p_irq_b => cpu_IRQ_n
);
p_cs_b <= '0' when cpu_addr(15 downto 3) = "1111111011111" else '1';
rom_cs_b <= '0' when cpu_addr(15 downto 11) = "11111" and cpu_R_W_n = '1' and bootmode = '1' else '1';
ram_cs_b <= '0' when p_cs_b = '1' and rom_cs_b = '1' else '1';
cpu_din <=
p_data_out when p_cs_b = '0' else
rom_data_out when rom_cs_b = '0' else
ram_data when ram_cs_b = '0' else
x"f1";
ram_ub_b <= '0';
ram_lb_b <= '0';
ram_cs <= ram_cs_b;
ram_oe_int <= not ((not ram_cs_b) and cpu_R_W_n);
ram_oe <= ram_oe_int;
ram_wr_int <= not ((not ram_cs_b) and (not cpu_R_W_n) and phi1);
ram_wr <= ram_wr_int;
ram_addr <= "000" & cpu_addr(15 downto 0);
ram_data <= cpu_dout when cpu_R_W_n = '0' else "ZZZZZZZZ";
--------------------------------------------------------
-- test signals
--------------------------------------------------------
-- default to hi-impedence, to avoid conflicts with
-- a Raspberry Pi connected to the test connector
test <= (others => 'Z');
--------------------------------------------------------
-- boot mode generator
--------------------------------------------------------
boot_gen : process(clk_16M00, RSTn_sync)
begin
if RSTn_sync = '0' then
bootmode <= '1';
elsif rising_edge(clk_16M00) then
if p_cs_b = '0' then
bootmode <= '0';
end if;
end if;
end process;
--------------------------------------------------------
-- power up reset
--------------------------------------------------------
reset_gen : process(clk_16M00)
begin
if rising_edge(clk_16M00) then
if (reset_counter(8) = '0') then
reset_counter <= reset_counter + 1;
end if;
RSTn_sync <= RSTn AND reset_counter(8);
end if;
end process;
--------------------------------------------------------
-- interrupt synchronization
--------------------------------------------------------
sync_gen : process(clk_16M00, RSTn_sync)
begin
if RSTn_sync = '0' then
cpu_NMI_n_sync <= '1';
cpu_IRQ_n_sync <= '1';
elsif rising_edge(clk_16M00) then
if (cpu_clken = '1') then
cpu_NMI_n_sync <= cpu_NMI_n;
cpu_IRQ_n_sync <= cpu_IRQ_n;
end if;
end if;
end process;
--------------------------------------------------------
-- clock enable generator
-- 4MHz
-- cpu_clken active on cycle 0, 4, 8, 12
-- address/data changes on cycle 1, 5, 9, 13
-- phi0 active on cycle 1..2
-- phi1 active on cycle 2..3
-- phi2 active on cycle 3..0
-- phi3 active on cycle 0..1
--------------------------------------------------------
clk_gen : process(clk_16M00, RSTn)
begin
if rising_edge(clk_16M00) then
clken_counter <= clken_counter + 1;
cpu_clken <= clken_counter(0) and clken_counter(1);
phi0 <= not clken_counter(1);
phi1 <= phi0;
phi2 <= phi1;
phi3 <= phi2;
end if;
end process;
end BEHAVIORAL;
| gpl-3.0 | baf09e591a4690beda96fee8f43843cc | 0.422007 | 3.6191 | false | false | false | false |
18545/FPGA | old/camera_demo/camera_demo.srcs/sources_1/ip/blk_mem_gen_0/synth/blk_mem_gen_0.vhd | 1 | 14,454 | -- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:blk_mem_gen:8.2
-- IP Revision: 6
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY blk_mem_gen_v8_2;
USE blk_mem_gen_v8_2.blk_mem_gen_v8_2;
ENTITY blk_mem_gen_0 IS
PORT (
clka : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(18 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
clkb : IN STD_LOGIC;
addrb : IN STD_LOGIC_VECTOR(18 DOWNTO 0);
doutb : OUT STD_LOGIC_VECTOR(11 DOWNTO 0)
);
END blk_mem_gen_0;
ARCHITECTURE blk_mem_gen_0_arch OF blk_mem_gen_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF blk_mem_gen_0_arch: ARCHITECTURE IS "yes";
COMPONENT blk_mem_gen_v8_2 IS
GENERIC (
C_FAMILY : STRING;
C_XDEVICEFAMILY : STRING;
C_ELABORATION_DIR : STRING;
C_INTERFACE_TYPE : INTEGER;
C_AXI_TYPE : INTEGER;
C_AXI_SLAVE_TYPE : INTEGER;
C_USE_BRAM_BLOCK : INTEGER;
C_ENABLE_32BIT_ADDRESS : INTEGER;
C_CTRL_ECC_ALGO : STRING;
C_HAS_AXI_ID : INTEGER;
C_AXI_ID_WIDTH : INTEGER;
C_MEM_TYPE : INTEGER;
C_BYTE_SIZE : INTEGER;
C_ALGORITHM : INTEGER;
C_PRIM_TYPE : INTEGER;
C_LOAD_INIT_FILE : INTEGER;
C_INIT_FILE_NAME : STRING;
C_INIT_FILE : STRING;
C_USE_DEFAULT_DATA : INTEGER;
C_DEFAULT_DATA : STRING;
C_HAS_RSTA : INTEGER;
C_RST_PRIORITY_A : STRING;
C_RSTRAM_A : INTEGER;
C_INITA_VAL : STRING;
C_HAS_ENA : INTEGER;
C_HAS_REGCEA : INTEGER;
C_USE_BYTE_WEA : INTEGER;
C_WEA_WIDTH : INTEGER;
C_WRITE_MODE_A : STRING;
C_WRITE_WIDTH_A : INTEGER;
C_READ_WIDTH_A : INTEGER;
C_WRITE_DEPTH_A : INTEGER;
C_READ_DEPTH_A : INTEGER;
C_ADDRA_WIDTH : INTEGER;
C_HAS_RSTB : INTEGER;
C_RST_PRIORITY_B : STRING;
C_RSTRAM_B : INTEGER;
C_INITB_VAL : STRING;
C_HAS_ENB : INTEGER;
C_HAS_REGCEB : INTEGER;
C_USE_BYTE_WEB : INTEGER;
C_WEB_WIDTH : INTEGER;
C_WRITE_MODE_B : STRING;
C_WRITE_WIDTH_B : INTEGER;
C_READ_WIDTH_B : INTEGER;
C_WRITE_DEPTH_B : INTEGER;
C_READ_DEPTH_B : INTEGER;
C_ADDRB_WIDTH : INTEGER;
C_HAS_MEM_OUTPUT_REGS_A : INTEGER;
C_HAS_MEM_OUTPUT_REGS_B : INTEGER;
C_HAS_MUX_OUTPUT_REGS_A : INTEGER;
C_HAS_MUX_OUTPUT_REGS_B : INTEGER;
C_MUX_PIPELINE_STAGES : INTEGER;
C_HAS_SOFTECC_INPUT_REGS_A : INTEGER;
C_HAS_SOFTECC_OUTPUT_REGS_B : INTEGER;
C_USE_SOFTECC : INTEGER;
C_USE_ECC : INTEGER;
C_EN_ECC_PIPE : INTEGER;
C_HAS_INJECTERR : INTEGER;
C_SIM_COLLISION_CHECK : STRING;
C_COMMON_CLK : INTEGER;
C_DISABLE_WARN_BHV_COLL : INTEGER;
C_EN_SLEEP_PIN : INTEGER;
C_USE_URAM : INTEGER;
C_EN_RDADDRA_CHG : INTEGER;
C_EN_RDADDRB_CHG : INTEGER;
C_EN_DEEPSLEEP_PIN : INTEGER;
C_EN_SHUTDOWN_PIN : INTEGER;
C_DISABLE_WARN_BHV_RANGE : INTEGER;
C_COUNT_36K_BRAM : STRING;
C_COUNT_18K_BRAM : STRING;
C_EST_POWER_SUMMARY : STRING
);
PORT (
clka : IN STD_LOGIC;
rsta : IN STD_LOGIC;
ena : IN STD_LOGIC;
regcea : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(18 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
clkb : IN STD_LOGIC;
rstb : IN STD_LOGIC;
enb : IN STD_LOGIC;
regceb : IN STD_LOGIC;
web : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addrb : IN STD_LOGIC_VECTOR(18 DOWNTO 0);
dinb : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
doutb : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
injectsbiterr : IN STD_LOGIC;
injectdbiterr : IN STD_LOGIC;
eccpipece : IN STD_LOGIC;
sbiterr : OUT STD_LOGIC;
dbiterr : OUT STD_LOGIC;
rdaddrecc : OUT STD_LOGIC_VECTOR(18 DOWNTO 0);
sleep : IN STD_LOGIC;
deepsleep : IN STD_LOGIC;
shutdown : IN STD_LOGIC;
s_aclk : IN STD_LOGIC;
s_aresetn : IN STD_LOGIC;
s_axi_awid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awaddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_wlast : IN STD_LOGIC;
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_arid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_araddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_rdata : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rlast : OUT STD_LOGIC;
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
s_axi_injectsbiterr : IN STD_LOGIC;
s_axi_injectdbiterr : IN STD_LOGIC;
s_axi_sbiterr : OUT STD_LOGIC;
s_axi_dbiterr : OUT STD_LOGIC;
s_axi_rdaddrecc : OUT STD_LOGIC_VECTOR(18 DOWNTO 0)
);
END COMPONENT blk_mem_gen_v8_2;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF blk_mem_gen_0_arch: ARCHITECTURE IS "blk_mem_gen_v8_2,Vivado 2015.2";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF blk_mem_gen_0_arch : ARCHITECTURE IS "blk_mem_gen_0,blk_mem_gen_v8_2,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF blk_mem_gen_0_arch: ARCHITECTURE IS "blk_mem_gen_0,blk_mem_gen_v8_2,{x_ipProduct=Vivado 2015.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=blk_mem_gen,x_ipVersion=8.2,x_ipCoreRevision=6,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_FAMILY=zynq,C_XDEVICEFAMILY=zynq,C_ELABORATION_DIR=./,C_INTERFACE_TYPE=0,C_AXI_TYPE=1,C_AXI_SLAVE_TYPE=0,C_USE_BRAM_BLOCK=0,C_ENABLE_32BIT_ADDRESS=0,C_CTRL_ECC_ALGO=NONE,C_HAS_AXI_ID=0,C_AXI_ID_WIDTH=4,C_MEM_TYPE=1,C_BYTE_SIZE=9,C_ALGORITHM=1,C_PRIM_TYPE=1,C_LOAD_INIT_FILE=0,C_INIT_FILE_NAME=no_coe_file_loaded,C_INIT_FILE=blk_mem_gen_0.mem,C_USE_DEFAULT_DATA=0,C_DEFAULT_DATA=0,C_HAS_RSTA=0,C_RST_PRIORITY_A=CE,C_RSTRAM_A=0,C_INITA_VAL=0,C_HAS_ENA=0,C_HAS_REGCEA=0,C_USE_BYTE_WEA=0,C_WEA_WIDTH=1,C_WRITE_MODE_A=NO_CHANGE,C_WRITE_WIDTH_A=12,C_READ_WIDTH_A=12,C_WRITE_DEPTH_A=307200,C_READ_DEPTH_A=307200,C_ADDRA_WIDTH=19,C_HAS_RSTB=0,C_RST_PRIORITY_B=CE,C_RSTRAM_B=0,C_INITB_VAL=0,C_HAS_ENB=0,C_HAS_REGCEB=0,C_USE_BYTE_WEB=0,C_WEB_WIDTH=1,C_WRITE_MODE_B=WRITE_FIRST,C_WRITE_WIDTH_B=12,C_READ_WIDTH_B=12,C_WRITE_DEPTH_B=307200,C_READ_DEPTH_B=307200,C_ADDRB_WIDTH=19,C_HAS_MEM_OUTPUT_REGS_A=0,C_HAS_MEM_OUTPUT_REGS_B=1,C_HAS_MUX_OUTPUT_REGS_A=0,C_HAS_MUX_OUTPUT_REGS_B=0,C_MUX_PIPELINE_STAGES=0,C_HAS_SOFTECC_INPUT_REGS_A=0,C_HAS_SOFTECC_OUTPUT_REGS_B=0,C_USE_SOFTECC=0,C_USE_ECC=0,C_EN_ECC_PIPE=0,C_HAS_INJECTERR=0,C_SIM_COLLISION_CHECK=ALL,C_COMMON_CLK=0,C_DISABLE_WARN_BHV_COLL=0,C_EN_SLEEP_PIN=0,C_USE_URAM=0,C_EN_RDADDRA_CHG=0,C_EN_RDADDRB_CHG=0,C_EN_DEEPSLEEP_PIN=0,C_EN_SHUTDOWN_PIN=0,C_DISABLE_WARN_BHV_RANGE=0,C_COUNT_36K_BRAM=103,C_COUNT_18K_BRAM=1,C_EST_POWER_SUMMARY=Estimated Power for IP _ 16.887376 mW}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF clka: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK";
ATTRIBUTE X_INTERFACE_INFO OF wea: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA WE";
ATTRIBUTE X_INTERFACE_INFO OF addra: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR";
ATTRIBUTE X_INTERFACE_INFO OF dina: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA DIN";
ATTRIBUTE X_INTERFACE_INFO OF clkb: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB CLK";
ATTRIBUTE X_INTERFACE_INFO OF addrb: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB ADDR";
ATTRIBUTE X_INTERFACE_INFO OF doutb: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB DOUT";
BEGIN
U0 : blk_mem_gen_v8_2
GENERIC MAP (
C_FAMILY => "zynq",
C_XDEVICEFAMILY => "zynq",
C_ELABORATION_DIR => "./",
C_INTERFACE_TYPE => 0,
C_AXI_TYPE => 1,
C_AXI_SLAVE_TYPE => 0,
C_USE_BRAM_BLOCK => 0,
C_ENABLE_32BIT_ADDRESS => 0,
C_CTRL_ECC_ALGO => "NONE",
C_HAS_AXI_ID => 0,
C_AXI_ID_WIDTH => 4,
C_MEM_TYPE => 1,
C_BYTE_SIZE => 9,
C_ALGORITHM => 1,
C_PRIM_TYPE => 1,
C_LOAD_INIT_FILE => 0,
C_INIT_FILE_NAME => "no_coe_file_loaded",
C_INIT_FILE => "blk_mem_gen_0.mem",
C_USE_DEFAULT_DATA => 0,
C_DEFAULT_DATA => "0",
C_HAS_RSTA => 0,
C_RST_PRIORITY_A => "CE",
C_RSTRAM_A => 0,
C_INITA_VAL => "0",
C_HAS_ENA => 0,
C_HAS_REGCEA => 0,
C_USE_BYTE_WEA => 0,
C_WEA_WIDTH => 1,
C_WRITE_MODE_A => "NO_CHANGE",
C_WRITE_WIDTH_A => 12,
C_READ_WIDTH_A => 12,
C_WRITE_DEPTH_A => 307200,
C_READ_DEPTH_A => 307200,
C_ADDRA_WIDTH => 19,
C_HAS_RSTB => 0,
C_RST_PRIORITY_B => "CE",
C_RSTRAM_B => 0,
C_INITB_VAL => "0",
C_HAS_ENB => 0,
C_HAS_REGCEB => 0,
C_USE_BYTE_WEB => 0,
C_WEB_WIDTH => 1,
C_WRITE_MODE_B => "WRITE_FIRST",
C_WRITE_WIDTH_B => 12,
C_READ_WIDTH_B => 12,
C_WRITE_DEPTH_B => 307200,
C_READ_DEPTH_B => 307200,
C_ADDRB_WIDTH => 19,
C_HAS_MEM_OUTPUT_REGS_A => 0,
C_HAS_MEM_OUTPUT_REGS_B => 1,
C_HAS_MUX_OUTPUT_REGS_A => 0,
C_HAS_MUX_OUTPUT_REGS_B => 0,
C_MUX_PIPELINE_STAGES => 0,
C_HAS_SOFTECC_INPUT_REGS_A => 0,
C_HAS_SOFTECC_OUTPUT_REGS_B => 0,
C_USE_SOFTECC => 0,
C_USE_ECC => 0,
C_EN_ECC_PIPE => 0,
C_HAS_INJECTERR => 0,
C_SIM_COLLISION_CHECK => "ALL",
C_COMMON_CLK => 0,
C_DISABLE_WARN_BHV_COLL => 0,
C_EN_SLEEP_PIN => 0,
C_USE_URAM => 0,
C_EN_RDADDRA_CHG => 0,
C_EN_RDADDRB_CHG => 0,
C_EN_DEEPSLEEP_PIN => 0,
C_EN_SHUTDOWN_PIN => 0,
C_DISABLE_WARN_BHV_RANGE => 0,
C_COUNT_36K_BRAM => "103",
C_COUNT_18K_BRAM => "1",
C_EST_POWER_SUMMARY => "Estimated Power for IP : 16.887376 mW"
)
PORT MAP (
clka => clka,
rsta => '0',
ena => '0',
regcea => '0',
wea => wea,
addra => addra,
dina => dina,
clkb => clkb,
rstb => '0',
enb => '0',
regceb => '0',
web => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
addrb => addrb,
dinb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 12)),
doutb => doutb,
injectsbiterr => '0',
injectdbiterr => '0',
eccpipece => '0',
sleep => '0',
deepsleep => '0',
shutdown => '0',
s_aclk => '0',
s_aresetn => '0',
s_axi_awid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awaddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_awlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_awsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_awburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_awvalid => '0',
s_axi_wdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 12)),
s_axi_wstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_wlast => '0',
s_axi_wvalid => '0',
s_axi_bready => '0',
s_axi_arid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_araddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_arlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_arsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_arburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_arvalid => '0',
s_axi_rready => '0',
s_axi_injectsbiterr => '0',
s_axi_injectdbiterr => '0'
);
END blk_mem_gen_0_arch;
| mit | 9c4a710a47b8d65404fdd3d1f41c1eb8 | 0.628407 | 3.015019 | false | false | false | false |
EliasLuiz/TCC | Leon3/lib/gaisler/leon3v3/grfpwx.vhd | 1 | 4,601 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: grfpwx
-- File: grfpwx.vhd
-- Author: Edvin Catovic - Gaisler Research
-- Description: GRFPU/GRFPC wrapper and FP register file
------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
use techmap.netcomp.all;
library gaisler;
use gaisler.leon3.all;
use gaisler.libleon3.all;
use gaisler.libfpu.all;
entity grfpwx is
generic (fabtech : integer := 0;
memtech : integer := 0;
mul : integer range 0 to 3 := 0;
pclow : integer range 0 to 2 := 2;
dsu : integer range 0 to 1 := 0;
disas : integer range 0 to 2 := 0;
netlist : integer := 0;
index : integer := 0;
scantest : integer := 0);
port (
rst : in std_ulogic; -- Reset
clk : in std_ulogic;
holdn : in std_ulogic; -- pipeline hold
cpi : in fpc_in_type;
cpo : out fpc_out_type;
testin : in std_logic_vector(TESTIN_WIDTH-1 downto 0)
);
end;
architecture rtl of grfpwx is
signal rfi1, rfi2 : fp_rf_in_type;
signal rfo1, rfo2 : fp_rf_out_type;
signal rf1rd1, rf1rd2, rf2rd1, rf2rd2, rf1wd, rf2wd : std_logic_vector(38 downto 0);
begin
x1 : if true generate
grfpw0 : grfpw_net generic map (fabtech, pclow, dsu, disas)
port map (
rst ,
clk ,
holdn ,
cpi.flush ,
cpi.exack ,
cpi.a_rs1 ,
cpi.d.pc ,
cpi.d.inst ,
cpi.d.cnt ,
cpi.d.trap ,
cpi.d.annul ,
cpi.d.pv ,
cpi.a.pc ,
cpi.a.inst ,
cpi.a.cnt ,
cpi.a.trap ,
cpi.a.annul ,
cpi.a.pv ,
cpi.e.pc ,
cpi.e.inst ,
cpi.e.cnt ,
cpi.e.trap ,
cpi.e.annul ,
cpi.e.pv ,
cpi.m.pc ,
cpi.m.inst ,
cpi.m.cnt ,
cpi.m.trap ,
cpi.m.annul ,
cpi.m.pv ,
cpi.x.pc ,
cpi.x.inst ,
cpi.x.cnt ,
cpi.x.trap ,
cpi.x.annul ,
cpi.x.pv ,
cpi.lddata ,
cpi.dbg.enable ,
cpi.dbg.write ,
cpi.dbg.fsr ,
cpi.dbg.addr ,
cpi.dbg.data ,
cpo.data ,
cpo.exc ,
cpo.cc ,
cpo.ccv ,
cpo.ldlock ,
cpo.holdn ,
cpo.dbg.data ,
rfi1.rd1addr ,
rfi1.rd2addr ,
rfi1.wraddr ,
rfi1.wrdata ,
rfi1.ren1 ,
rfi1.ren2 ,
rfi1.wren ,
rfi2.rd1addr ,
rfi2.rd2addr ,
rfi2.wraddr ,
rfi2.wrdata ,
rfi2.ren1 ,
rfi2.ren2 ,
rfi2.wren ,
rfo1.data1 ,
rfo1.data2 ,
rfo2.data1 ,
rfo2.data2
);
end generate;
rf1 : regfile_3p_l3 generic map (memtech, 4, 32, 1, 16,
scantest
)
port map (clk, rfi1.wraddr, rfi1.wrdata, rfi1.wren, clk, rfi1.rd1addr,
rfi1.ren1, rfo1.data1, rfi1.rd2addr, rfi1.ren2, rfo1.data2,
testin
);
rf2 : regfile_3p_l3 generic map (memtech, 4, 32, 1, 16,
scantest
)
port map (clk, rfi2.wraddr, rfi2.wrdata, rfi2.wren, clk, rfi2.rd1addr,
rfi2.ren1, rfo2.data1, rfi2.rd2addr, rfi2.ren2, rfo2.data2,
testin
);
end;
| gpl-3.0 | 2667085f8165ce493af0b5b694e877ec | 0.501195 | 3.436146 | false | false | false | false |
pwsoft/fpga_examples | rtl/chameleon/chameleon_buttons.vhd | 1 | 9,853 | -- -----------------------------------------------------------------------
--
-- Turbo Chameleon
--
-- Multi purpose FPGA expansion for the Commodore 64 computer
--
-- -----------------------------------------------------------------------
-- Copyright 2005-2019 by Peter Wendrich ([email protected])
-- http://www.syntiac.com/chameleon.html
--
-- This source file is free software: you can redistribute it and/or modify
-- it under the terms of the GNU Lesser General Public License as published
-- by the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This source file is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
-- -----------------------------------------------------------------------
--
-- buttons
-- Decodes the action of the three buttons on the Chameleon cartridge.
-- Generates trigger signals depending on configuration and the duration a
-- button is pressed down.
--
-- -----------------------------------------------------------------------
-- shortpress_ms - Length of a short keypress in milliseconds
-- A button pressed shorter is ignored (debounce).
-- longpress_ms - Length of a long keypress in milliseconds
-- A button pressed longer is considered a long press.
-- -----------------------------------------------------------------------
-- clk - system clock input
-- ena_1khz - Enable must be high for one clk cycle each millisecond
-- menu_mode - High when menu mode is active
-- Most button functions are disabled inside the menu.
-- reset_last_button - Reset last_button output
-- last_button - Reports last pressed key
-- Allows menu-system to reuse the buttons by decoding in software
-- button_l - Left button input (for physical button)
-- button_m - Middle button input (for physical button)
-- button_r - Right button input (for physical button)
-- button_l_2 - Left button input (internal from PS/2 or CDTV remote)
-- button_m_2 - Middle button input (internal from PS/2 or CDTV remote)
-- button_r_2 - Right button input (internal from PS/2 or CDTV remote)
-- button_config - button configuration input
-- Refer to "The Programmers Manual" for available settings
--
-- reset - Reset output
-- boot - Request for reboot of the system (long reset)
-- freeze - cartridge freezer request
-- menu - menu freezer request
-- turbo_toggle - CPU turbo toggle request
-- disk8_next - select next disk image for emulated drive 8
-- disk8_first - select first disk image for emulated drive 8
-- disk9_next - select next disk image for emulated drive 9
-- disk9_first - select first disk image for emulated drive 9
-- cart_toggle - Toggle cartridge on/off (some cartridges have an on/off switch)
-- cart_prg - Switch cartridge in programming mode (expert cartridge)
-- -----------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.all;
-- -----------------------------------------------------------------------
entity chameleon_buttons is
generic (
shortpress_ms : integer := 50;
longpress_ms : integer := 1000
);
port (
clk : in std_logic;
ena_1khz : in std_logic;
menu_mode : in std_logic := '0';
reset_last_button : in std_logic := '0';
last_button : out unsigned(2 downto 0);
button_l : in std_logic;
button_m : in std_logic;
button_r : in std_logic;
button_l_2 : in std_logic := '0';
button_m_2 : in std_logic := '0';
button_r_2 : in std_logic := '0';
button_config : in unsigned(3 downto 0);
reset : out std_logic;
boot : out std_logic;
freeze : out std_logic;
menu : out std_logic;
turbo_toggle : out std_logic;
disk8_next : out std_logic;
disk8_first : out std_logic;
disk9_next : out std_logic;
disk9_first : out std_logic;
cart_toggle : out std_logic;
cart_prg : out std_logic
);
end entity;
-- -----------------------------------------------------------------------
architecture rtl of chameleon_buttons is
signal button_l_cnt : integer range 0 to longpress_ms := 0;
signal button_l_long : std_logic := '0';
signal button_l_short : std_logic := '0';
signal button_m_cnt : integer range 0 to longpress_ms := 0;
signal button_m_long : std_logic := '0';
signal button_m_short : std_logic := '0';
signal button_r_cnt : integer range 0 to longpress_ms := 0;
signal button_r_long : std_logic := '0';
signal button_r_short : std_logic := '0';
signal button_l_dly1 : std_logic := '0';
signal button_l_dly2 : std_logic := '0';
signal button_l_loc : std_logic := '0';
signal button_m_dly1 : std_logic := '0';
signal button_m_dly2 : std_logic := '0';
signal button_m_loc : std_logic := '0';
signal button_r_dly1 : std_logic := '0';
signal button_r_dly2 : std_logic := '0';
signal button_r_loc : std_logic := '0';
signal last_button_reg : unsigned(2 downto 0) := (others => '0');
signal reset_reg : std_logic := '0';
signal boot_reg : std_logic := '0';
signal freeze_reg : std_logic := '0';
signal menu_reg : std_logic := '0';
signal cart_toggle_reg : std_logic := '0';
signal cart_prg_reg : std_logic := '0';
signal turbo_reg : std_logic := '0';
signal disk8_next_reg : std_logic := '0';
signal disk8_first_reg : std_logic := '0';
signal disk9_next_reg : std_logic := '0';
signal disk9_first_reg : std_logic := '0';
begin
last_button <= last_button_reg;
reset <= reset_reg;
boot <= boot_reg;
freeze <= freeze_reg;
menu <= menu_reg;
turbo_toggle <= turbo_reg;
disk8_next <= disk8_next_reg;
disk8_first <= disk8_first_reg;
disk9_next <= disk9_next_reg;
disk9_first <= disk9_first_reg;
cart_toggle <= cart_toggle_reg;
cart_prg <= cart_prg_reg;
-- Syncronise buttons to clock (double registered for async inputs)
process(clk)
begin
if rising_edge(clk) then
button_l_dly1 <= button_l;
button_l_dly2 <= button_l_dly1;
button_l_loc <= button_l_dly2 or button_l_2;
button_m_dly1 <= button_m;
button_m_dly2 <= button_m_dly1;
button_m_loc <= button_m_dly2 or button_m_2;
button_r_dly1 <= button_r;
button_r_dly2 <= button_r_dly1;
button_r_loc <= button_r_dly2 or button_r_2;
end if;
end process;
process(clk)
begin
if rising_edge(clk) then
button_l_long <= '0';
button_l_short <= '0';
if button_l_loc = '1' then
if button_l_cnt /= longpress_ms then
if ena_1khz = '1' then
button_l_cnt <= button_l_cnt + 1;
end if;
if button_l_cnt > shortpress_ms then
button_l_short <= '1';
end if;
else
button_l_long <= '1';
end if;
else
button_l_cnt <= 0;
end if;
end if;
end process;
process(clk)
begin
if rising_edge(clk) then
button_m_long <= '0';
button_m_short <= '0';
if button_m_loc = '1' then
if button_m_cnt /= longpress_ms then
if ena_1khz = '1' then
button_m_cnt <= button_m_cnt + 1;
end if;
if button_m_cnt > shortpress_ms then
button_m_short <= '1';
end if;
else
button_m_long <= '1';
end if;
else
button_m_cnt <= 0;
end if;
end if;
end process;
process(clk)
begin
if rising_edge(clk) then
button_r_long <= '0';
button_r_short <= '0';
if button_r_loc = '1' then
if button_r_cnt /= longpress_ms then
if ena_1khz = '1' then
button_r_cnt <= button_r_cnt + 1;
end if;
if button_r_cnt > shortpress_ms then
button_r_short <= '1';
end if;
else
button_r_long <= '1';
end if;
else
button_r_cnt <= 0;
end if;
end if;
end process;
process(clk)
begin
if rising_edge(clk) then
reset_reg <= '0';
freeze_reg <= '0';
menu_reg <= '0';
boot_reg <= '0';
cart_toggle_reg <= '0';
cart_prg_reg <= '0';
turbo_reg <= '0';
disk8_next_reg <= '0';
disk8_first_reg <= '0';
disk9_next_reg <= '0';
disk9_first_reg <= '0';
if button_l_loc = '0' then
if menu_mode = '0' then
case button_config is
when "0000" =>
menu_reg <= button_l_short;
when "0001" =>
cart_toggle_reg <= button_l_short;
cart_prg_reg <= button_l_long;
when "0010" =>
turbo_reg <= button_l_short;
when "0100" =>
disk8_next_reg <= button_l_short;
disk8_first_reg <= button_l_long;
when "0101" =>
disk9_next_reg <= button_l_short;
disk9_first_reg <= button_l_long;
when others =>
null;
end case;
end if;
if button_l_short = '1' then
last_button_reg <= "010";
end if;
if button_l_long = '1' then
last_button_reg <= "011";
end if;
end if;
if button_m_loc = '0' then
if menu_mode = '0' then
freeze_reg <= button_m_short;
if button_m_long = '1' then
menu_reg <= '1';
end if;
end if;
if button_m_short = '1' then
last_button_reg <= "100";
end if;
if button_m_long = '1' then
last_button_reg <= "101";
end if;
end if;
if button_r_loc = '0' then
if menu_mode = '0' then
reset_reg <= button_r_short;
end if;
boot_reg <= button_r_long;
if button_r_short = '1' then
last_button_reg <= "110";
end if;
if button_r_long = '1' then
last_button_reg <= "111";
end if;
end if;
if reset_last_button = '1' then
last_button_reg <= (others => '0');
end if;
end if;
end process;
end architecture;
| lgpl-2.1 | a35e98f80be34da3f002d6a84c3d6512 | 0.578707 | 3.114096 | false | false | false | false |
EliasLuiz/TCC | Leon3/lib/gaisler/uart/dcom_uart.vhd | 1 | 11,471 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: dcom_uart
-- File: dcom_uart.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: Asynchronous UART with baud-rate detection.
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.config_types.all;
use grlib.config.all;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
library gaisler;
use gaisler.libdcom.all;
use gaisler.uart.all;
--pragma translate_off
use std.textio.all;
--pragma translate_on
entity dcom_uart is
generic (
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#fff#
);
port (
rst : in std_ulogic;
clk : in std_ulogic;
ui : in uart_in_type;
uo : out uart_out_type;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
uarti : in dcom_uart_in_type;
uarto : out dcom_uart_out_type
);
end;
architecture rtl of dcom_uart is
constant REVISION : integer := 0;
constant pconfig : apb_config_type := (
0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_AHBUART, 0, REVISION, 0),
1 => apb_iobar(paddr, pmask));
type rxfsmtype is (idle, startbit, data, stopbit);
type txfsmtype is (idle, data);
type uartregs is record
rxen : std_ulogic; -- receiver enabled
dready : std_ulogic; -- data ready
rsempty : std_ulogic; -- receiver shift register empty (internal)
tsempty : std_ulogic; -- transmitter shift register empty
thempty : std_ulogic; -- transmitter hold register empty
break : std_ulogic; -- break detected
ovf : std_ulogic; -- receiver overflow
frame : std_ulogic; -- framing error
rhold : std_logic_vector(7 downto 0);
rshift : std_logic_vector(7 downto 0);
tshift : std_logic_vector(9 downto 0);
thold : std_logic_vector(7 downto 0);
txstate : txfsmtype;
txclk : std_logic_vector(2 downto 0); -- tx clock divider
txtick : std_ulogic; -- tx clock (internal)
rxstate : rxfsmtype;
rxclk : std_logic_vector(2 downto 0); -- rx clock divider
rxdb : std_logic_vector(1 downto 0); -- rx data filtering buffer
rxtick : std_ulogic; -- rx clock (internal)
tick : std_ulogic; -- rx clock (internal)
scaler : std_logic_vector(17 downto 0);
brate : std_logic_vector(17 downto 0);
tcnt : std_logic_vector(1 downto 0); -- autobaud counter
rxf : std_logic_vector(4 downto 0); -- rx data filtering buffer
fedge : std_ulogic; -- rx falling edge
end record;
constant RESET_ALL : boolean := GRLIB_CONFIG_ARRAY(grlib_sync_reset_enable_all) = 1;
constant RES : uartregs := (
rxen => '0', dready => '0', rsempty => '1', tsempty => '1', thempty => '1',
break => '0', ovf => '0', frame => '0', rhold => (others => '0'),
rshift => (others => '0'), tshift => (others => '1'), thold => (others => '0'),
txstate => idle, txclk => (others => '0'), txtick => '0', rxstate => idle,
rxclk => (others => '0'), rxdb => (others => '0'), rxtick => '0', tick => '0',
scaler => "111111111111111011", brate => (others => '1'), tcnt => (others => '0'),
rxf => (others => '0'), fedge => '0');
signal r, rin : uartregs;
begin
uartop : process(rst, r, apbi, uarti, ui )
variable rdata : std_logic_vector(31 downto 0);
variable scaler : std_logic_vector(17 downto 0);
variable rxclk, txclk : std_logic_vector(2 downto 0);
variable irxd : std_ulogic;
variable v : uartregs;
begin
v := r;
v.txtick := '0'; v.rxtick := '0'; v.tick := '0'; rdata := (others => '0');
v.rxdb(1) := r.rxdb(0);
-- scaler
if r.tcnt = "11" then scaler := r.scaler - 1;
else scaler := r.scaler + 1; end if;
if r.tcnt /= "11" then
if (r.rxdb(1) and not r.rxdb(0)) = '1' then v.fedge := '1'; end if;
if (r.fedge) = '1' then
v.scaler := scaler;
if (v.scaler(17) and not r.scaler(16)) = '1' then
v.scaler := "111111111111111011";
v.fedge := '0'; v.tcnt := "00";
end if;
end if;
if (r.rxdb(1) and r.fedge and not r.rxdb(0)) = '1' then
if (r.brate(17 downto 4)> r.scaler(17 downto 4)) then
v.brate := r.scaler; v.tcnt := "00";
end if;
v.scaler := "111111111111111011";
if (r.brate(17 downto 4) = r.scaler(17 downto 4)) then
v.tcnt := r.tcnt + 1;
if r.tcnt = "10" then
v.brate := "0000" & r.scaler(17 downto 4);
v.scaler := v.brate; v.rxen := '1';
end if;
end if;
end if;
else
if (r.break and r.rxdb(1)) = '1' then
v.scaler := "111111111111111011";
v.brate := (others => '1'); v.tcnt := "00";
v.break := '0'; v.rxen := '0';
end if;
end if;
if r.rxen = '1' then
v.scaler := scaler;
v.tick := scaler(15) and not r.scaler(15);
if v.tick = '1' then v.scaler := r.brate; end if;
end if;
-- read/write registers
if uarti.read = '1' then v.dready := '0'; end if;
case apbi.paddr(3 downto 2) is
when "01" =>
rdata(9 downto 0) := r.tcnt & r.rxdb(0) & r.frame & '0' & r.ovf &
r.break & r.thempty & r.tsempty & r.dready;
when "10" =>
rdata(1 downto 0) := (r.tcnt(1) or r.tcnt(0)) & r.rxen;
when others =>
rdata(17 downto 0) := r.brate;
end case;
if (apbi.psel(pindex) and apbi.penable and apbi.pwrite) = '1' then
case apbi.paddr(3 downto 2) is
when "01" =>
v.frame := apbi.pwdata(6);
v.ovf := apbi.pwdata(4);
v.break := apbi.pwdata(3);
when "10" =>
v.tcnt := apbi.pwdata(1) & apbi.pwdata(1);
v.rxen := apbi.pwdata(0);
when "11" =>
v.brate := apbi.pwdata(17 downto 0);
v.scaler := apbi.pwdata(17 downto 0);
when others =>
end case;
end if;
-- tx clock
txclk := r.txclk + 1;
if r.tick = '1' then
v.txclk := txclk; v.txtick := r.txclk(2) and not txclk(2);
end if;
-- rx clock
rxclk := r.rxclk + 1;
if r.tick = '1' then
v.rxclk := rxclk; v.rxtick := r.rxclk(2) and not rxclk(2);
end if;
-- filter rx data
v.rxf(1 downto 0) := r.rxf(0) & ui.rxd; -- meta-stability filter
if ((r.tcnt /= "11") and (r.scaler(0 downto 0) = "1")) or
((r.tcnt = "11") and (r.tick = '1'))
then v.rxf(4 downto 2) := r.rxf(3 downto 1); end if;
v.rxdb(0) := (r.rxf(4) and r.rxf(3)) or (r.rxf(4) and r.rxf(2)) or
(r.rxf(3) and r.rxf(2));
irxd := r.rxdb(0);
-- transmitter operation
case r.txstate is
when idle => -- idle and stop bit state
if (r.txtick = '1') then v.tsempty := '1'; end if;
if (r.rxen and (not r.thempty) and r.txtick) = '1' then
v.tshift := '0' & r.thold & '0'; v.txstate := data;
v.thempty := '1';
v.tsempty := '0'; v.txclk := "00" & r.tick; v.txtick := '0';
end if;
when data => -- transmit data frame
if r.txtick = '1' then
v.tshift := '1' & r.tshift(9 downto 1);
if r.tshift(9 downto 1) = "111111110" then
v.tshift(0) := '1'; v.txstate := idle;
end if;
end if;
end case;
-- writing of tx data register must be done after tx fsm to get correct
-- operation of thempty flag
if uarti.write = '1' then
v.thold := uarti.data(7 downto 0); v.thempty := '0';
end if;
-- receiver operation
case r.rxstate is
when idle => -- wait for start bit
if ((not r.rsempty) and not r.dready) = '1' then
v.rhold := r.rshift; v.rsempty := '1'; v.dready := '1';
end if;
if (r.rxen and r.rxdb(1) and (not irxd)) = '1' then
v.rxstate := startbit; v.rshift := (others => '1'); v.rxclk := "100";
if v.rsempty = '0' then v.ovf := '1'; end if;
v.rsempty := '0'; v.rxtick := '0';
end if;
when startbit => -- check validity of start bit
if r.rxtick = '1' then
if irxd = '0' then
v.rshift := irxd & r.rshift(7 downto 1); v.rxstate := data;
else
v.rxstate := idle;
end if;
end if;
when data => -- receive data frame
if r.rxtick = '1' then
v.rshift := irxd & r.rshift(7 downto 1);
if r.rshift(0) = '0' then
v.rxstate := stopbit;
end if;
end if;
when stopbit => -- receive stop bit
if r.rxtick = '1' then
if irxd = '1' then
v.rsempty := '0';
if v.dready = '0' then
v.rhold := r.rshift; v.rsempty := '1'; v.dready := '1';
end if;
else
if r.rshift = "00000000" then
v.break := '1'; -- break
else
v.frame := '1'; -- framing error
end if;
v.rsempty := '1';
end if;
v.rxstate := idle;
end if;
when others =>
v.rxstate := idle;
end case;
-- reset operation
if not RESET_ALL and rst = '0' then
v.frame := RES.frame; v.rsempty := RES.rsempty;
v.ovf := RES.ovf; v.break := RES.break; v.thempty := RES.thempty;
v.tsempty := RES.tsempty; v.dready := RES.dready; v.fedge := RES.fedge;
v.txstate := RES.txstate; v.rxstate := RES.rxstate; v.tshift(0) := RES.tshift(0);
v.scaler := RES.scaler; v.brate := RES.brate;
v.rxen := RES.rxen; v.tcnt := RES.tcnt;
v.txclk := RES.txclk; v.rxclk := RES.rxclk;
end if;
-- update registers
rin <= v;
-- drive outputs
uo.txd <= r.tshift(0);
uo.scaler(31 downto 18) <= (others => '0');
uo.scaler(17 downto 0) <= r.brate;
uo.rtsn <= '0';
uo.rxen <= andv(r.tcnt);
uarto.dready <= r.dready;
uarto.tsempty <= r.tsempty;
uarto.thempty <= r.thempty;
uarto.lock <= r.tcnt(1) and r.tcnt(0);
uarto.enable <= r.rxen;
uarto.data <= r.rhold;
uo.txen <= '1'; uo.flow <= '0';
apbo.prdata <= rdata;
end process;
apbo.pirq <= (others => '0');
apbo.pconfig <= pconfig;
apbo.pindex <= pindex;
regs : process(clk)
begin
if rising_edge(clk) then
r <= rin;
if RESET_ALL and rst = '0' then
r <= RES;
-- Sync. registers not reset
r.rxf <= rin.rxf;
end if;
end if;
end process;
end;
| gpl-3.0 | 77b69bccb22538cd74de4b13eabda6bd | 0.539011 | 3.295317 | false | false | false | false |
EliasLuiz/TCC | Leon3/lib/gaisler/sim/ddr3ram.vhd | 1 | 30,863 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: ddr3ram
-- File: ddr3ram.vhd
-- Author: Magnus Hjorth, Aeroflex Gaisler
-- Description: Generic simulation model of DDR3 SDRAM (JESD79-3)
------------------------------------------------------------------------------
--pragma translate_off
use std.textio.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library grlib;
use grlib.stdio.hread;
use grlib.stdlib.all;
entity ddr3ram is
generic (
width: integer := 32;
abits: integer range 13 to 16 := 13;
colbits: integer range 9 to 12 := 10;
rowbits: integer range 1 to 16 := 13;
implbanks: integer range 1 to 8 := 1;
fname: string;
lddelay: time := (0 ns);
ldguard: integer range 0 to 1 := 0; -- 1: wait for doload input before
-- loading RAM
-- Speed bins: 0-1:800E-D, 2-4:1066G-E 5-8:1333J-F 9-12:1600K-G
speedbin: integer range 0 to 12 := 0;
density: integer range 2 to 6 := 3; -- 2:512M 3:1G 4:2G 5:4G 6:8G bits/chip
pagesize: integer range 1 to 2 := 1; -- 1K/2K page size (controls tRRD)
changeendian: integer range 0 to 32 := 0
);
port (
ck: in std_ulogic;
ckn: in std_ulogic;
cke: in std_ulogic;
csn: in std_ulogic;
odt: in std_ulogic;
rasn: in std_ulogic;
casn: in std_ulogic;
wen: in std_ulogic;
dm: in std_logic_vector(width/8-1 downto 0);
ba: in std_logic_vector(2 downto 0);
a: in std_logic_vector(abits-1 downto 0);
resetn: in std_ulogic;
dq: inout std_logic_vector(width-1 downto 0);
dqs: inout std_logic_vector(width/8-1 downto 0);
dqsn: inout std_logic_vector(width/8-1 downto 0);
doload: in std_ulogic := '1'
);
end;
architecture sim of ddr3ram is
type moderegs is record
-- Mode register (0)
ppd: std_ulogic;
wr: std_logic_vector(2 downto 0);
dllres: std_ulogic;
tm: std_ulogic;
rbt: std_ulogic;
caslat: std_logic_vector(3 downto 0);
blen: std_logic_vector(1 downto 0);
-- Extended mode register 1
qoff: std_ulogic;
tdqsen: std_ulogic;
level: std_ulogic;
al: std_logic_vector(1 downto 0);
rtt_nom: std_logic_vector(2 downto 0);
dic: std_logic_vector(1 downto 0);
dlldis: std_ulogic;
-- Extended mode register 2
rtt_wr: std_logic_vector(1 downto 0);
srt: std_ulogic;
asr: std_ulogic;
cwl: std_logic_vector(2 downto 0);
pasr: std_logic_vector(2 downto 0);
-- Extended mode register 3
mpr: std_ulogic;
mprloc: std_logic_vector(1 downto 0);
end record;
-- Mode registers as signal, useful for debugging
signal mr: moderegs;
-- Handshaking between command and DQ/DQS processes
signal read_en, write_en, dqscal_en: boolean := false;
signal read_data, write_data: std_logic_vector(2*width-1 downto 0);
signal write_mask: std_logic_vector(width/4-1 downto 0);
signal initdone: boolean := false;
-- Small delta-t to adjust calculations for jitter tol.
constant deltat: time := 50 ps;
-- Timing parameters
constant tWR: time := 15 ns;
constant tMRD_ck: integer := 4;
constant tRTP_ck: integer := 4;
constant tRTP_t: time := 7.5 ns;
function tRTP(tper: time) return time is
begin
if tRTP_ck*tper > tRTP_t then return tRTP_ck*tper; else return tRTP_t; end if;
end tRTP;
constant tMOD_ck: integer := 12;
constant tMOD_t: time := 15 ns;
type timetab is array (0 to 12) of time;
-- 800E 800D 1066G 1066H 1066E 1333J 1333H 1333G 1333F 1600K 1600J 1600H 1600G
constant tRAS : timetab :=
(37.5 ns, 37.5 ns, 37.5 ns, 37.5 ns, 37.5 ns, 36 ns, 36 ns, 36 ns, 36 ns, 35 ns, 35 ns, 35 ns, 35 ns);
constant tRP : timetab :=
(15 ns, 12.5 ns, 15 ns, 13.125 ns, 11.25 ns, 15 ns, 13.5 ns, 12 ns, 10.5 ns, 13.75 ns, 12.5 ns, 11.25 ns, 10 ns);
constant tRCD: timetab := tRP;
type timetab2 is array(2 to 6) of time;
constant tRFC: timetab2 := (90 ns, 110 ns, 160 ns, 300 ns, 350 ns);
function tRRD(tper: time; speedbin: integer range 0 to 12) return time is
variable t: time;
begin
case speedbin is
when 0 to 1 => t:=10 ns;
when 2 to 4 => if pagesize<2 then t:=7.5 ns; else t:=10 ns; end if;
when 5 to 12 => if pagesize<2 then t:=6 ns; else t:=7.5 ns; end if;
end case;
if t < 4*tper then t:=4*tper; end if;
return t;
end tRRD;
function pick(t,f: integer; b: boolean) return integer is
begin
if b then return t; else return f; end if;
end pick;
begin
-----------------------------------------------------------------------------
-- Init sequence checker
-----------------------------------------------------------------------------
initp: process
procedure checkcmd(crasn,ccasn,cwen: std_ulogic;
cba: std_logic_vector(2 downto 0);
ca: std_logic_vector(15 downto 0)) is
variable amatch: boolean;
begin
wait until rising_edge(ck);
while cke='1' and (csn='1' or (rasn='1' and casn='1' and wen='1')) loop
wait until rising_edge(ck);
end loop;
amatch := true;
for x in a'range loop
if ca(x)/='-' and ca(x)/=a(x) then amatch:=false; end if;
end loop;
assert cke='1' and csn='0' and rasn=crasn and casn=ccasn and wen=cwen and
(cba="---" or cba=ba) and amatch
report "Wrong command during init sequence" severity warning;
end checkcmd;
variable t,t2: time;
variable i: integer;
begin
initdone <= false;
-- Allow resetn to be X or U for a while during sim start
if resetn /= '0' then
wait until resetn='0' for 1 us;
end if;
assert resetn='0' report "RESETn not asserted on power-up" severity warning;
wait until resetn/='0' for 200 us;
assert resetn='0' report "RESETn raised with less than 200 us init delay" severity warning;
l0: loop
initdone <= false;
wait until resetn/='0';
assert cke='0' report "CKE not low when RESETn deasserted" severity warning;
wait until (resetn='0' or cke/='0') for 500 us;
if resetn='0' then next; end if;
assert cke='0' report "CKE raised with less than 500 us delay after RESETn deasserted" severity warning;
wait until (resetn='0' or cke/='0') and rising_edge(ck);
if resetn='0' then next; end if;
assert cke='1' and (csn='1' or (rasn='1' and casn='1' and wen='1'));
t := now;
t2 := t+tRFC(density)+(10 ns);
i := 0;
while i<5 and now<t2 loop
wait until (resetn='0' or rising_edge(ck));
if resetn='0' then next l0; end if;
assert cke='1' and (csn='1' or (rasn='1' and casn='1' and wen='1'));
i := i+1;
end loop;
-- EMRS EMR2
checkcmd('0','0','0',"010","----------------");
if resetn='0' then next; end if;
-- EMRS EMR3
checkcmd('0','0','0',"011","----------------");
if resetn='0' then next; end if;
-- EMRS EMR1 enable DLL
checkcmd('0','0','0',"001","---------------0");
if resetn='0' then next; end if;
-- EMRS EMR0 reset DLL
checkcmd('0','0','0',"000","-------1--------");
if resetn='0' then next; end if;
-- ZQCL
checkcmd('1','1','0',"---","-----1----------");
if resetn='0' then next; end if;
for x in 1 to 512 loop
wait until (resetn='0' or rising_edge(ck));
if resetn='0' then next l0; end if;
assert cke='1' and (csn='1' or (rasn='1' and casn='1' and wen='1'));
end loop;
initdone <= true;
wait until resetn='0';
end loop;
end process;
-----------------------------------------------------------------------------
-- Command state machine
-----------------------------------------------------------------------------
cmdp: process(ck)
-- Data split by bank to avoid exceeding 4G
constant b0size: integer := (2**(colbits+rowbits)) * ((width+15)/16);
constant b1size: integer := pick(b0size, 1, implbanks>1);
constant b2size: integer := pick(b0size, 1, implbanks>2);
constant b3size: integer := pick(b0size, 1, implbanks>3);
constant b4size: integer := pick(b0size, 1, implbanks>4);
constant b5size: integer := pick(b0size, 1, implbanks>5);
constant b6size: integer := pick(b0size, 1, implbanks>6);
constant b7size: integer := pick(b0size, 1, implbanks>7);
subtype coldata is std_logic_vector(width-1 downto 0);
subtype idata is integer range 0 to (2**20)-1; -- 16 data bits + 2x2 X/U state
type idata_arr is array(natural range <>) of idata;
variable memdata0: idata_arr(0 to b0size-1);
variable memdata1: idata_arr(0 to b1size-1);
variable memdata2: idata_arr(0 to b2size-1);
variable memdata3: idata_arr(0 to b3size-1);
variable memdata4: idata_arr(0 to b4size-1);
variable memdata5: idata_arr(0 to b5size-1);
variable memdata6: idata_arr(0 to b6size-1);
variable memdata7: idata_arr(0 to b7size-1);
function reversedata(data : std_logic_vector; step : integer)
return std_logic_vector is
variable rdata: std_logic_vector(data'length-1 downto 0);
begin
for i in 0 to (data'length/step-1) loop
rdata(i*step+step-1 downto i*step) := data(data'length-i*step-1 downto data'length-i*step-step);
end loop;
return rdata;
end function reversedata;
impure function memdata_get(bank,idx: integer) return coldata is
variable r: coldata;
variable x: idata;
variable p: std_logic_vector(19 downto 0);
variable iidx: integer;
begin
iidx := (idx*width)/16;
for q in 0 to (width+15)/16-1 loop
case bank is
when 0 => x := memdata0(iidx+q);
when 1 => x := memdata1(iidx+q);
when 2 => x := memdata2(iidx+q);
when 3 => x := memdata3(iidx+q);
when 4 => x := memdata4(iidx+q);
when 5 => x := memdata5(iidx+q);
when 6 => x := memdata6(iidx+q);
when others => x := memdata7(iidx+q);
end case;
p := std_logic_vector(to_unsigned(x,20));
if p(18)='0' then p(15 downto 8) := "UUUUUUUU";
elsif p(19)='1' then p(15 downto 8) := "XXXXXXXX"; end if;
if p(16)='0' then p(7 downto 0) := "UUUUUUUU";
elsif p(17)='1' then p(7 downto 0) := "XXXXXXXX"; end if;
if width < 16 then
r := p(7 downto 0);
else
r(width-16*q-1 downto width-16*q-16) := p(15 downto 0);
end if;
end loop;
if changeendian /= 0 then
r := reversedata(r, changeendian);
end if;
return r;
end memdata_get;
procedure memdata_set(bank,idx: integer; v: coldata) is
variable n: coldata;
variable x: idata;
variable p: std_logic_vector(19 downto 0);
variable iidx: integer;
begin
-- assert false
-- report ("memdata_set: bank " & tost(bank) & " idx " & tost(idx) & " data " & tost(v))
-- severity note;
n := v;
if changeendian /= 0 then
n := reversedata(n, changeendian);
end if;
iidx := (idx*width)/16;
for q in 0 to (width+15)/16-1 loop
p := "0101" & x"0000";
if width < 16 then
p(7 downto 0) := n;
else
p(15 downto 0) := n(width-16*q-1 downto width-16*q-16);
end if;
if p(15 downto 8)="UUUUUUUU" then p(18):='0'; p(15 downto 8):=x"00";
elsif is_x(p(15 downto 8)) then p(19):='1'; p(15 downto 8):=x"00"; end if;
if p(7 downto 0)="UUUUUUUU" then p(16):='0'; p(7 downto 0):=x"00";
elsif is_x(p(7 downto 0)) then p(17):='1'; p(7 downto 0):=x"00"; end if;
x := to_integer(unsigned(p));
case bank is
when 0 => memdata0(iidx+q) := x;
when 1 => memdata1(iidx+q) := x;
when 2 => memdata2(iidx+q) := x;
when 3 => memdata3(iidx+q) := x;
when 4 => memdata4(iidx+q) := x;
when 5 => memdata5(iidx+q) := x;
when 6 => memdata6(iidx+q) := x;
when others => memdata7(iidx+q) := x;
end case;
end loop;
end memdata_set;
procedure load_srec is
file TCF : text open read_mode is fname;
variable L1: line;
variable CH : character;
variable rectype : std_logic_vector(3 downto 0);
variable recaddr : std_logic_vector(31 downto 0);
variable reclen : std_logic_vector(7 downto 0);
variable recdata : std_logic_vector(0 to 16*8-1);
variable idx, coloffs, len: integer;
begin
L1:= new string'("");
while not endfile(TCF) loop
readline(TCF,L1);
if (L1'length /= 0) then
while (not (L1'length=0)) and (L1(L1'left) = ' ') loop
std.textio.read(L1,CH);
end loop;
if L1'length > 0 then
read(L1, ch);
if (ch = 'S') or (ch = 's') then
hread(L1, rectype);
hread(L1, reclen);
len := to_integer(unsigned(reclen))-1;
recaddr := (others => '0');
case rectype is
when "0001" => hread(L1, recaddr(15 downto 0)); len := len - 2;
when "0010" => hread(L1, recaddr(23 downto 0)); len := len - 3;
when "0011" => hread(L1, recaddr); len := len - 4;
when others => next;
end case;
hread(L1, recdata(0 to len*8-1));
if width < 16 then
idx := to_integer(unsigned(recaddr(rowbits+colbits-1 downto 0)));
while len > 1 loop
memdata0(idx) := 16#10000# + to_integer(unsigned(recdata(0 to 7)));
idx := idx+1;
len := len-1;
recdata(0 to recdata'length-8-1) := recdata(8 to recdata'length-1);
end loop;
else
assert recaddr(0)='0'; -- Assume 16-bit alignment on SREC entry
idx := to_integer(unsigned(recaddr(rowbits+colbits+log2(width/16) downto 1)));
while len > 1 loop
memdata0(idx) := 16#50000# + to_integer(unsigned(recdata(0 to 15)));
idx := idx+1;
len := len-2;
recdata(0 to recdata'length-16-1) := recdata(16 to recdata'length-1);
end loop;
if len > 0 then
memdata0(idx) := 16#40000# + to_integer(unsigned(recdata(0 to 15)));
end if;
end if;
end if;
end if;
end if;
end loop;
end load_srec;
variable vmr: moderegs;
type bankstate is record
openrow: integer;
opentime: time;
closetime: time;
writetime: time;
readtime: time;
autopch: integer;
pchpush: boolean;
end record;
type bankstate_arr is array(natural range <>) of bankstate;
variable banks: bankstate_arr(7 downto 0) := (others => (-1, 0 ns, 0 ns, 0 ns, 0 ns, -1, false));
type int_arr is array(natural range <>) of integer;
type dataacc is record
r,w: boolean;
col: int_arr(0 to 1);
bank: integer;
first,wchop: boolean;
end record;
type dataacc_arr is array(natural range <>) of dataacc;
variable accpipe: dataacc_arr(0 to 25);
variable cmd: std_logic_vector(2 downto 0);
variable bank: integer;
variable colv: unsigned(a'high-2 downto 0);
variable alow: unsigned(2 downto 0);
variable col: integer;
variable prev_re, re: time;
variable blen, wblen: integer;
variable lastref: time := 0 ns;
variable i, al, cl, cwl, wrap: integer;
variable b: boolean;
variable mrscount: integer := 100;
variable mrstime: time;
variable loaded: boolean := false;
variable cold: coldata;
procedure checktime(got, exp: time; gt: boolean; req: string) is
begin
assert (got + deltat > exp and gt) or (got-deltat < exp and not gt)
report (req & " violation, got: " & tost(got/(1 ps)) & " ps, exp: " & tost(exp/(1 ps)) & "ps")
severity warning;
end checktime;
begin
if rising_edge(ck) and resetn='1' then
-- Update pipe regs
prev_re := re;
re := now;
accpipe(1 to accpipe'high) := accpipe(0 to accpipe'high-1);
accpipe(0).r:=false; accpipe(0).w:=false; accpipe(0).first:=false;
-- Parse MR fields
cmd := rasn & casn & wen;
if is_x(vmr.caslat) then cl:=0; else cl:=to_integer(unsigned(vmr.caslat(3 downto 1)))+4; end if;
if cl<5 or cl>11 then cl:=0; end if;
case vmr.al is
when "00" => al:=0;
when "01" => al:=cl-1;
when "10" => al:=cl-2;
when others => al:=-1;
end case;
if is_x(vmr.cwl) then cwl:=0; else cwl:=to_integer(unsigned(vmr.cwl))+5; end if;
if cwl>8 then cwl:=0; end if;
if is_x(vmr.wr) then wrap:=0; else wrap:=to_integer(unsigned(vmr.wr))+4; end if;
if wrap<5 or wrap>12 then wrap:=0; end if;
-- Checks for all-bank commands
mrscount := mrscount+1;
assert (mrscount >= tMRD_ck) or (cke='1' and (csn='1' or cmd="111"))
report "tMRD violation!" severity warning;
assert (mrscount > tMOD_ck and now > mrstime+tMOD_t-deltat) or
(cke='1' and (csn='1' or cmd="111" or cmd="000"))
report "tMOD violation!" severity warning;
if cke='1' and csn='0' and cmd/="111" then
checktime(now-lastref, tRFC(density), true, "tRFC");
end if;
if vmr.mpr='1' then
assert cke='0' or csn='1' or cmd="111" or cmd="101"
report "Command other than read in MPR mode!" severity warning;
for x in 7 downto 0 loop
assert banks(x).openrow<0
report "Row opened in MPR mode!" severity warning;
end loop;
end if;
-- Main command handler
if cke='1' and csn='0' then
case cmd is
when "111" => -- NOP
when "011" => -- RAS
assert initdone report "Opening row before init sequence done!" severity warning;
bank := to_integer(unsigned(ba));
assert banks(bank).openrow < 0
report "Row already open" severity warning;
checktime(now-banks(bank).closetime, tRP(speedbin), true, "tRP");
for x in 0 to 7 loop
checktime(now-banks(x).opentime, tRRD(re-prev_re, speedbin), true, "tRRD");
end loop;
banks(bank).openrow := to_integer(unsigned(a(rowbits-1 downto 0)));
banks(bank).opentime := now;
when "101" | "100" => -- Read/Write
bank := to_integer(unsigned(ba));
assert banks(bank).openrow >= 0 or vmr.mpr='1'
report "Row not open" severity error;
checktime(now-banks(bank).opentime+al*(re-prev_re), tRCD(speedbin), true, "tRCD");
for x in 0 to 3 loop
assert not accpipe(x).r and not accpipe(x).w;
end loop;
if cmd(0)='1' then accpipe(3).r:=true; else accpipe(3).w:=true; end if;
colv := unsigned(std_logic_vector'(a(a'high downto 13) & a(11) & a(9 downto 0)));
wblen := 8;
case vmr.blen is
when "00" => blen := 8;
when "01" => if a(12)='1' then blen:=8; else blen:=4; end if;
when "11" => blen := 4; wblen:=4;
when others => assert false report "Invalid burst length setting in MR!" severity error;
end case;
alow := unsigned(a(2 downto 0));
if cmd(0)='0' then
alow(1 downto 0) := "00";
if blen=8 then alow(2):='0'; end if;
end if;
for x in 0 to blen-1 loop
accpipe(3-x/2).bank := bank;
if cmd(0)='1' then accpipe(3-x/2).r:=true; else accpipe(3-x/2).w:=true; end if;
if vmr.rbt='0' then -- Sequential
colv(log2(blen)-1 downto 0) := alow(log2(blen)-1 downto 0) + x;
else -- Interleaved
colv(log2(blen)-1 downto 0) := alow(log2(blen)-1 downto 0) xor to_unsigned(x,log2(blen));
end if;
col := banks(bank).openrow * (2**colbits) + to_integer(colv(colbits-1 downto 0));
accpipe(3-x/2).col(x mod 2) := col;
accpipe(3-x/2).wchop := (blen<wblen);
end loop;
accpipe(3).first := true;
-- Auto precharge
if a(10)='1' then
if cmd(0)='1' then
banks(bank).autopch := al+tRTP_ck;
else
banks(bank).autopch := al+cwl+wblen/2+wrap;
end if;
banks(bank).pchpush := true;
end if;
when "110" => -- ZQInit
for x in 0 to 7 loop
checktime(now-banks(x).closetime, tRP(speedbin), true, "tRP");
end loop;
for x in 3+cl+al downto 0 loop
assert not accpipe(x).r severity warning;
end loop;
for x in 4+cwl+al downto 0 loop
assert not accpipe(x).w severity warning;
end loop;
-- Currently does not check TZQCoper/TZQCs
when "010" => -- Precharge
if a(10)='0' then bank := to_integer(unsigned(ba)); else bank:=0; end if;
for x in 6+cwl+al downto 0 loop
assert ( (not ((accpipe(x).r and x<=3+al) or accpipe(x).w)) or
(a(10)='0' and accpipe(x).bank/=bank) )
report "Precharging bank with access in progress" severity warning;
end loop;
for x in 0 to 7 loop
if a(10)='1' or ba=std_logic_vector(to_unsigned(x,3)) then
assert banks(x).autopch<0
report "Precharging bank that is auto-precharged!" severity note;
assert a(10)='1' or banks(x).openrow >= 0
report "Precharging single bank that is in idle state!" severity note;
banks(x).autopch := 0; -- Handled below case statement
banks(x).pchpush := false;
end if;
end loop;
when "001" => -- Auto refresh
for x in 0 to 7 loop
assert banks(x).openrow < 0
report "Bank in wrong state for auto refresh!" severity warning;
checktime(now-banks(x).closetime, tRP(speedbin), true, "tRP");
end loop;
lastref := now;
when "000" => -- MRS
for x in 0 to 7 loop
checktime(now-banks(x).closetime, tRP(speedbin), true, "tRP");
end loop;
bank := to_integer(unsigned(ba));
case bank is
when 0 =>
vmr.ppd := a(12);
vmr.wr := a(11 downto 9);
vmr.dllres := a(8);
vmr.tm := a(7);
vmr.caslat := a(6 downto 4) & a(2);
vmr.rbt := a(3);
vmr.blen := a(1 downto 0);
when 1 =>
vmr.qoff := a(12);
vmr.tdqsen := a(11);
vmr.level := a(7);
vmr.al := a(4 downto 3);
vmr.rtt_nom := a(9) & a(6) & a(2);
vmr.dic := a(5) & a(1);
vmr.dlldis := a(0);
when 2 =>
vmr.rtt_wr := a(10 downto 9);
vmr.srt := a(7);
vmr.asr := a(6);
vmr.cwl := a(5 downto 3);
vmr.pasr := a(2 downto 0);
when 3 =>
vmr.mpr := a(2);
vmr.mprloc := a(1 downto 0);
when others =>
assert false report ("MRS to invalid bank addr: " & std_logic'image(ba(1)) & std_logic'image(ba(0))) severity warning;
end case;
mrscount := 0;
mrstime := now;
when others =>
assert false report ("Invalid command: " & std_logic'image(rasn) & std_logic'image(casn) & std_logic'image(wen)) severity warning;
end case;
end if;
-- Manual or auto precharge handling
for x in 0 to 7 loop
if banks(x).autopch=0 then
if banks(x).pchpush and
((now-banks(x).readtime-deltat) < tRTP_t or
(now-banks(x).opentime-deltat) < tRAS(speedbin)) then
-- Auto delay auto-precharge to satisfy tRTP_t
-- NOTE: According to Micron's datasheets, their DDR3 memories
-- automatically hold off the auto precharge so that also tRAS is satisfied,
-- and the MIG controller seems to depend on this. It is not clear in the
-- JEDEC standard (rev F) whether this is guaranteed behavior for all DDR3
-- RAMs, but we emulate that behavior here.
banks(x).autopch := banks(x).autopch+1;
else
checktime(now-banks(x).writetime, tWR, true, "tWR");
checktime(now-banks(x).opentime, tRAS(speedbin), true, "tRAS");
checktime(now-banks(x).readtime, tRTP(re-prev_re), true, "tRTP");
banks(x).openrow := -1;
banks(x).closetime := now;
end if;
end if;
if banks(x).autopch >= 0 then
banks(x).autopch := banks(x).autopch - 1;
end if;
end loop;
-- Read/write management
if not loaded and lddelay < now and (ldguard=0 or doload='1') then
load_srec;
loaded := true;
end if;
if accpipe(2+cl+al).r then
assert cl>1 report "Incorrect CL setting!" severity warning;
read_en <= true;
-- print("Reading from col " & tost(accpipe(2+i).col(0)) & " and " & tost(accpipe(2+i).col(1)));
-- col0 <= accpipe(2+i).col(0); col1 <= accpipe(2+i).col(1);
if vmr.mpr='1' then
assert vmr.mprloc="00" report "Read from undefined MPR!" severity warning;
read_data <= (others => '0');
for x in width/8-1 downto 0 loop
read_data(x*8) <= '1';
end loop;
else
read_data <= memdata_get(accpipe(2+cl+al).bank, accpipe(2+cl+al).col(0)) &
memdata_get(accpipe(2+cl+al).bank, accpipe(2+cl+al).col(1));
end if;
else
read_en <= false;
end if;
if accpipe(3+al).r and accpipe(3+al).first then
banks(accpipe(3+al).bank).readtime := now;
end if;
write_en <= accpipe(2+cwl+al).w or accpipe(3+cwl+al).w;
if accpipe(4+cwl+al).w then
assert not is_x(write_mask) report "Write error!";
for x in 0 to 1 loop
cold := memdata_get(accpipe(4+cwl+al).bank, accpipe(4+cwl+al).col(x));
for b in width/8-1 downto 0 loop
if write_mask((1-x)*width/8+b)='0' then
cold(8*b+7 downto 8*b) :=
write_data( (1-x)*width+b*8+7 downto (1-x)*width+b*8);
end if;
end loop;
memdata_set(accpipe(4+cwl+al).bank, accpipe(4+cwl+al).col(x), cold);
end loop;
banks(accpipe(4+cwl+al).bank).writetime := now;
end if;
if accpipe(6+cwl+al).w and accpipe(6+cwl+al).wchop then
banks(accpipe(6+cwl+al).bank).writetime := now;
end if;
dqscal_en <= (vmr.level='1');
elsif resetn='0' then
for x in banks'range loop
banks(x).openrow := -1;
end loop;
end if;
mr <= vmr;
end process;
-----------------------------------------------------------------------------
-- DQS/DQ handling and data sampling process
-----------------------------------------------------------------------------
dqproc: process
variable rdata: std_logic_vector(2*width-1 downto 0);
variable hdata: std_logic_vector(width-1 downto 0);
variable hmask: std_logic_vector(width/8-1 downto 0);
variable prevdqs: std_logic_vector(width/8-1 downto 0);
begin
dq <= (others => 'Z');
dqs <= (others => 'Z');
dqsn <= (others => 'Z');
wait until read_en or write_en or dqscal_en;
assert not (read_en and write_en);
if dqscal_en then
while dqscal_en loop
prevdqs := dqs;
wait on dqs,dqscal_en;
for x in dqs'range loop
if dqs(x)='1' and prevdqs(x)='0' then
dq(8*x+7 downto 8*x) <= "0000000" & ck;
end if;
end loop;
end loop;
elsif read_en then
dqs <= (others => '0');
dqsn <= (others => '1');
wait until falling_edge(ck);
while read_en loop
rdata := read_data;
wait until rising_edge(ck);
dqs <= (others => '1');
dqsn <= (others => '0');
dq <= rdata(2*width-1 downto width);
wait until falling_edge(ck);
dqs <= (others => '0');
dqsn <= (others => '1');
dq <= rdata(width-1 downto 0);
end loop;
wait until rising_edge(ck);
else
wait until falling_edge(ck);
while write_en loop
prevdqs := to_X01(dqs);
wait until to_X01(dqs) /= prevdqs or not write_en or rising_edge(ck);
if rising_edge(ck) then
write_data <= (others => 'X');
write_mask <= (others => 'X');
end if;
for x in dqs'range loop
if prevdqs(x)='0' and to_X01(dqs(x))='1' then
hdata(8*x+7 downto 8*x) := dq(8*x+7 downto 8*x);
hmask(x) := dm(x);
elsif prevdqs(x)='1' and to_X01(dqs(x))='0' then
write_data(width+8*x+7 downto width+8*x) <= hdata(8*x+7 downto 8*x);
write_data(8*x+7 downto 8*x) <= dq(8*x+7 downto 8*x);
write_mask(width/8+x) <= hmask(x);
write_mask(x) <= dm(x);
end if;
end loop;
end loop;
end if;
end process;
end;
-- pragma translate_on
| gpl-3.0 | f72157d8118081673608c28a9751c45d | 0.533908 | 3.594573 | false | false | false | false |
pwsoft/fpga_examples | quartus/chameleon2/chameleon2_gigatron/pll50.vhd | 1 | 19,642 | -- megafunction wizard: %ALTPLL%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altpll
-- ============================================================
-- File Name: pll50.vhd
-- Megafunction Name(s):
-- altpll
--
-- Simulation Library Files(s):
-- altera_mf
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 17.0.2 Build 602 07/19/2017 SJ Lite Edition
-- ************************************************************
--Copyright (C) 2017 Intel Corporation. All rights reserved.
--Your use of Intel Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Intel Program License
--Subscription Agreement, the Intel Quartus Prime License Agreement,
--the Intel MegaCore Function License Agreement, or other
--applicable license agreement, including, without limitation,
--that your use is for the sole purpose of programming logic
--devices manufactured by Intel and sold by Intel or its
--authorized distributors. Please refer to the applicable
--agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
ENTITY pll50 IS
PORT
(
inclk0 : IN STD_LOGIC := '0';
c0 : OUT STD_LOGIC ;
c1 : OUT STD_LOGIC ;
c2 : OUT STD_LOGIC ;
c3 : OUT STD_LOGIC ;
locked : OUT STD_LOGIC
);
END pll50;
ARCHITECTURE SYN OF pll50 IS
SIGNAL sub_wire0 : STD_LOGIC ;
SIGNAL sub_wire1 : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL sub_wire2_bv : BIT_VECTOR (0 DOWNTO 0);
SIGNAL sub_wire2 : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL sub_wire3 : STD_LOGIC_VECTOR (4 DOWNTO 0);
SIGNAL sub_wire4 : STD_LOGIC ;
SIGNAL sub_wire5 : STD_LOGIC ;
SIGNAL sub_wire6 : STD_LOGIC ;
SIGNAL sub_wire7 : STD_LOGIC ;
SIGNAL sub_wire8 : STD_LOGIC ;
COMPONENT altpll
GENERIC (
bandwidth_type : STRING;
clk0_divide_by : NATURAL;
clk0_duty_cycle : NATURAL;
clk0_multiply_by : NATURAL;
clk0_phase_shift : STRING;
clk1_divide_by : NATURAL;
clk1_duty_cycle : NATURAL;
clk1_multiply_by : NATURAL;
clk1_phase_shift : STRING;
clk2_divide_by : NATURAL;
clk2_duty_cycle : NATURAL;
clk2_multiply_by : NATURAL;
clk2_phase_shift : STRING;
clk3_divide_by : NATURAL;
clk3_duty_cycle : NATURAL;
clk3_multiply_by : NATURAL;
clk3_phase_shift : STRING;
compensate_clock : STRING;
inclk0_input_frequency : NATURAL;
intended_device_family : STRING;
lpm_hint : STRING;
lpm_type : STRING;
operation_mode : STRING;
pll_type : STRING;
port_activeclock : STRING;
port_areset : STRING;
port_clkbad0 : STRING;
port_clkbad1 : STRING;
port_clkloss : STRING;
port_clkswitch : STRING;
port_configupdate : STRING;
port_fbin : STRING;
port_inclk0 : STRING;
port_inclk1 : STRING;
port_locked : STRING;
port_pfdena : STRING;
port_phasecounterselect : STRING;
port_phasedone : STRING;
port_phasestep : STRING;
port_phaseupdown : STRING;
port_pllena : STRING;
port_scanaclr : STRING;
port_scanclk : STRING;
port_scanclkena : STRING;
port_scandata : STRING;
port_scandataout : STRING;
port_scandone : STRING;
port_scanread : STRING;
port_scanwrite : STRING;
port_clk0 : STRING;
port_clk1 : STRING;
port_clk2 : STRING;
port_clk3 : STRING;
port_clk4 : STRING;
port_clk5 : STRING;
port_clkena0 : STRING;
port_clkena1 : STRING;
port_clkena2 : STRING;
port_clkena3 : STRING;
port_clkena4 : STRING;
port_clkena5 : STRING;
port_extclk0 : STRING;
port_extclk1 : STRING;
port_extclk2 : STRING;
port_extclk3 : STRING;
self_reset_on_loss_lock : STRING;
width_clock : NATURAL
);
PORT (
inclk : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
clk : OUT STD_LOGIC_VECTOR (4 DOWNTO 0);
locked : OUT STD_LOGIC
);
END COMPONENT;
BEGIN
sub_wire2_bv(0 DOWNTO 0) <= "0";
sub_wire2 <= To_stdlogicvector(sub_wire2_bv);
sub_wire0 <= inclk0;
sub_wire1 <= sub_wire2(0 DOWNTO 0) & sub_wire0;
sub_wire7 <= sub_wire3(3);
sub_wire6 <= sub_wire3(2);
sub_wire5 <= sub_wire3(1);
sub_wire4 <= sub_wire3(0);
c0 <= sub_wire4;
c1 <= sub_wire5;
c2 <= sub_wire6;
c3 <= sub_wire7;
locked <= sub_wire8;
altpll_component : altpll
GENERIC MAP (
bandwidth_type => "AUTO",
clk0_divide_by => 1,
clk0_duty_cycle => 50,
clk0_multiply_by => 2,
clk0_phase_shift => "0",
clk1_divide_by => 1,
clk1_duty_cycle => 50,
clk1_multiply_by => 2,
clk1_phase_shift => "5000",
clk2_divide_by => 1,
clk2_duty_cycle => 50,
clk2_multiply_by => 3,
clk2_phase_shift => "0",
clk3_divide_by => 1,
clk3_duty_cycle => 50,
clk3_multiply_by => 3,
clk3_phase_shift => "4167",
compensate_clock => "CLK0",
inclk0_input_frequency => 20000,
intended_device_family => "Cyclone 10 LP",
lpm_hint => "CBX_MODULE_PREFIX=pll50",
lpm_type => "altpll",
operation_mode => "SOURCE_SYNCHRONOUS",
pll_type => "AUTO",
port_activeclock => "PORT_UNUSED",
port_areset => "PORT_UNUSED",
port_clkbad0 => "PORT_UNUSED",
port_clkbad1 => "PORT_UNUSED",
port_clkloss => "PORT_UNUSED",
port_clkswitch => "PORT_UNUSED",
port_configupdate => "PORT_UNUSED",
port_fbin => "PORT_UNUSED",
port_inclk0 => "PORT_USED",
port_inclk1 => "PORT_UNUSED",
port_locked => "PORT_USED",
port_pfdena => "PORT_UNUSED",
port_phasecounterselect => "PORT_UNUSED",
port_phasedone => "PORT_UNUSED",
port_phasestep => "PORT_UNUSED",
port_phaseupdown => "PORT_UNUSED",
port_pllena => "PORT_UNUSED",
port_scanaclr => "PORT_UNUSED",
port_scanclk => "PORT_UNUSED",
port_scanclkena => "PORT_UNUSED",
port_scandata => "PORT_UNUSED",
port_scandataout => "PORT_UNUSED",
port_scandone => "PORT_UNUSED",
port_scanread => "PORT_UNUSED",
port_scanwrite => "PORT_UNUSED",
port_clk0 => "PORT_USED",
port_clk1 => "PORT_USED",
port_clk2 => "PORT_USED",
port_clk3 => "PORT_USED",
port_clk4 => "PORT_UNUSED",
port_clk5 => "PORT_UNUSED",
port_clkena0 => "PORT_UNUSED",
port_clkena1 => "PORT_UNUSED",
port_clkena2 => "PORT_UNUSED",
port_clkena3 => "PORT_UNUSED",
port_clkena4 => "PORT_UNUSED",
port_clkena5 => "PORT_UNUSED",
port_extclk0 => "PORT_UNUSED",
port_extclk1 => "PORT_UNUSED",
port_extclk2 => "PORT_UNUSED",
port_extclk3 => "PORT_UNUSED",
self_reset_on_loss_lock => "OFF",
width_clock => 5
)
PORT MAP (
inclk => sub_wire1,
clk => sub_wire3,
locked => sub_wire8
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
-- Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
-- Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
-- Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
-- Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
-- Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
-- Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
-- Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
-- Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
-- Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
-- Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
-- Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
-- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
-- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
-- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "Any"
-- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1"
-- Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "1"
-- Retrieval info: PRIVATE: DIV_FACTOR2 NUMERIC "1"
-- Retrieval info: PRIVATE: DIV_FACTOR3 NUMERIC "1"
-- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
-- Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
-- Retrieval info: PRIVATE: DUTY_CYCLE2 STRING "50.00000000"
-- Retrieval info: PRIVATE: DUTY_CYCLE3 STRING "50.00000000"
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "100.000000"
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "100.000000"
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE2 STRING "150.000000"
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE3 STRING "150.000000"
-- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
-- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
-- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
-- Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
-- Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
-- Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
-- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "50.000"
-- Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone 10 LP"
-- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
-- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1"
-- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "deg"
-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT2 STRING "deg"
-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT3 STRING "deg"
-- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
-- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
-- Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0"
-- Retrieval info: PRIVATE: MIRROR_CLK2 STRING "0"
-- Retrieval info: PRIVATE: MIRROR_CLK3 STRING "0"
-- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "2"
-- Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "2"
-- Retrieval info: PRIVATE: MULT_FACTOR2 NUMERIC "3"
-- Retrieval info: PRIVATE: MULT_FACTOR3 NUMERIC "3"
-- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "0"
-- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "100.00000000"
-- Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "200.00000000"
-- Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "150.00000000"
-- Retrieval info: PRIVATE: OUTPUT_FREQ3 STRING "150.00000000"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "0"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE2 STRING "0"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE3 STRING "0"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT2 STRING "MHz"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT3 STRING "MHz"
-- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
-- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
-- Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "180.00000000"
-- Retrieval info: PRIVATE: PHASE_SHIFT2 STRING "0.00000000"
-- Retrieval info: PRIVATE: PHASE_SHIFT3 STRING "225.00000000"
-- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg"
-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT2 STRING "deg"
-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT3 STRING "deg"
-- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
-- Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
-- Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll50.mif"
-- Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
-- Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
-- Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
-- Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
-- Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
-- Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
-- Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
-- Retrieval info: PRIVATE: SPREAD_USE STRING "0"
-- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "1"
-- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
-- Retrieval info: PRIVATE: STICKY_CLK1 STRING "1"
-- Retrieval info: PRIVATE: STICKY_CLK2 STRING "1"
-- Retrieval info: PRIVATE: STICKY_CLK3 STRING "1"
-- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
-- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: USE_CLK0 STRING "1"
-- Retrieval info: PRIVATE: USE_CLK1 STRING "1"
-- Retrieval info: PRIVATE: USE_CLK2 STRING "1"
-- Retrieval info: PRIVATE: USE_CLK3 STRING "1"
-- Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
-- Retrieval info: PRIVATE: USE_CLKENA1 STRING "0"
-- Retrieval info: PRIVATE: USE_CLKENA2 STRING "0"
-- Retrieval info: PRIVATE: USE_CLKENA3 STRING "0"
-- Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
-- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
-- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "1"
-- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
-- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "2"
-- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
-- Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "1"
-- Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
-- Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "2"
-- Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "5000"
-- Retrieval info: CONSTANT: CLK2_DIVIDE_BY NUMERIC "1"
-- Retrieval info: CONSTANT: CLK2_DUTY_CYCLE NUMERIC "50"
-- Retrieval info: CONSTANT: CLK2_MULTIPLY_BY NUMERIC "3"
-- Retrieval info: CONSTANT: CLK2_PHASE_SHIFT STRING "0"
-- Retrieval info: CONSTANT: CLK3_DIVIDE_BY NUMERIC "1"
-- Retrieval info: CONSTANT: CLK3_DUTY_CYCLE NUMERIC "50"
-- Retrieval info: CONSTANT: CLK3_MULTIPLY_BY NUMERIC "3"
-- Retrieval info: CONSTANT: CLK3_PHASE_SHIFT STRING "4167"
-- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
-- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "20000"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone 10 LP"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
-- Retrieval info: CONSTANT: OPERATION_MODE STRING "SOURCE_SYNCHRONOUS"
-- Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
-- Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: SELF_RESET_ON_LOSS_LOCK STRING "OFF"
-- Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5"
-- Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
-- Retrieval info: USED_PORT: @inclk 0 0 2 0 INPUT_CLK_EXT VCC "@inclk[1..0]"
-- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
-- Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1"
-- Retrieval info: USED_PORT: c2 0 0 0 0 OUTPUT_CLK_EXT VCC "c2"
-- Retrieval info: USED_PORT: c3 0 0 0 0 OUTPUT_CLK_EXT VCC "c3"
-- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
-- Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked"
-- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
-- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
-- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
-- Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
-- Retrieval info: CONNECT: c2 0 0 0 0 @clk 0 0 1 2
-- Retrieval info: CONNECT: c3 0 0 0 0 @clk 0 0 1 3
-- Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL pll50.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL pll50.ppf TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL pll50.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL pll50.bsf FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL pll50_inst.vhd FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL pll50.cmp TRUE
-- Retrieval info: LIB_FILE: altera_mf
-- Retrieval info: CBX_MODULE_PREFIX: ON
| lgpl-2.1 | 22e85a01718c42cd96840e73d22c0d36 | 0.700947 | 3.270396 | false | false | false | false |
EliasLuiz/TCC | Leon3/designs/leon3-digilent-basys3/testbench.vhd | 1 | 4,107 | -----------------------------------------------------------------------------
-- LEON3 Demonstration design test bench
-- Copyright (C) 2016 Cobham Gaisler
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library gaisler;
use gaisler.libdcom.all;
use gaisler.sim.all;
library techmap;
use techmap.gencomp.all;
use work.debug.all;
use work.config.all;
entity testbench is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
clktech : integer := CFG_CLKTECH;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW
);
end;
architecture behav of testbench is
constant promfile : string := "prom.srec"; -- rom contents
constant lresp : boolean := false;
signal clk : std_ulogic := '0';
-- Switches
signal sw : std_logic_vector(15 downto 0);
-- LEDs
signal led : std_logic_vector(15 downto 0);
-- Buttons
signal btnc : std_ulogic;
signal btnu : std_ulogic;
signal btnl : std_ulogic;
signal btnr : std_ulogic;
signal btnd : std_ulogic;
-- VGA connector
signal vgared : std_logic_vector(3 downto 0);
signal vgablue : std_logic_vector(3 downto 0);
signal vgagreen : std_logic_vector(3 downto 0);
signal hsync : std_ulogic;
signal vsync : std_ulogic;
-- USB-RS232 interface
signal rstx : std_logic;
signal rsrx : std_logic;
-- SPI
signal spi_sim_sck : std_logic;
signal qspicsn : std_logic;
signal qspidb : std_logic_vector(3 downto 0);
begin
-- clock and reset
clk <= not clk after 5 ns;
btnc <= '1', '0' after 100 ns;
d3 : entity work.leon3mp
generic map (fabtech, memtech, padtech, clktech, disas, dbguart, pclow,
use_ahbram_sim => 1)
port map (
clk => clk, sw => sw, led => led,
btnc => btnc, btnu => btnu, btnl => btnl, btnr => btnr, btnd => btnd,
vgared => vgared, vgablue => vgablue, vgagreen => vgagreen,
hsync => hsync, vsync => vsync,
rstx => rstx, rsrx => rsrx,
spi_sim_sck => spi_sim_sck,
qspicsn => qspicsn, qspidb => qspidb);
spimem0: if CFG_SPIMCTRL = 1 generate
s0 : spi_flash generic map (ftype => 4, debug => 0, fname => promfile,
readcmd => CFG_SPIMCTRL_READCMD,
dummybyte => CFG_SPIMCTRL_DUMMYBYTE,
dualoutput => CFG_SPIMCTRL_DUALOUTPUT)
port map (spi_sim_sck, qspidb(0), qspidb(1), qspicsn);
end generate spimem0;
iuerr : process
begin
wait for 10 us;
assert (to_X01(led(3)) = '0')
report "*** IU in error mode, simulation halted ***"
severity failure;
end process;
end;
| gpl-3.0 | 2b98a841812694b0848546e945b351ca | 0.569028 | 4.070367 | false | false | false | false |
EliasLuiz/TCC | Leon3/designs/leon3mp/leon3mp.vhd | 1 | 36,052 | -----------------------------------------------------------------------------
-- LEON3 Demonstration design
-- Copyright (C) 2004 Jiri Gaisler, Gaisler Research
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
library techmap;
use techmap.gencomp.all;
library gaisler;
use gaisler.memctrl.all;
use gaisler.leon3.all;
use gaisler.uart.all;
use gaisler.misc.all;
use gaisler.can.all;
use gaisler.pci.all;
use gaisler.net.all;
use gaisler.jtag.all;
use gaisler.spacewire.all;
library esa;
use esa.memoryctrl.all;
use esa.pcicomp.all;
use work.config.all;
entity leon3mp is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
clktech : integer := CFG_CLKTECH;
ncpu : integer := CFG_NCPU;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW
);
port (
resetn : in std_ulogic;
clk : in std_ulogic;
pllref : in std_ulogic;
errorn : out std_ulogic;
address : out std_logic_vector(27 downto 0);
data : inout std_logic_vector(31 downto 0);
sa : out std_logic_vector(14 downto 0);
sd : inout std_logic_vector(63 downto 0);
sdclk : out std_ulogic;
sdcke : out std_logic_vector (1 downto 0); -- sdram clock enable
sdcsn : out std_logic_vector (1 downto 0); -- sdram chip select
sdwen : out std_ulogic; -- sdram write enable
sdrasn : out std_ulogic; -- sdram ras
sdcasn : out std_ulogic; -- sdram cas
sddqm : out std_logic_vector (7 downto 0); -- sdram dqm
dsutx : out std_ulogic; -- DSU tx data
dsurx : in std_ulogic; -- DSU rx data
dsuen : in std_ulogic;
dsubre : in std_ulogic;
dsuact : out std_ulogic;
txd1 : out std_ulogic; -- UART1 tx data
rxd1 : in std_ulogic; -- UART1 rx data
txd2 : out std_ulogic; -- UART2 tx data
rxd2 : in std_ulogic; -- UART2 rx data
ramsn : out std_logic_vector (4 downto 0);
ramoen : out std_logic_vector (4 downto 0);
rwen : out std_logic_vector (3 downto 0);
oen : out std_ulogic;
writen : out std_ulogic;
read : out std_ulogic;
iosn : out std_ulogic;
romsn : out std_logic_vector (1 downto 0);
gpio : inout std_logic_vector(CFG_GRGPIO_WIDTH-1 downto 0); -- I/O port
emdio : inout std_logic; -- ethernet PHY interface
etx_clk : in std_ulogic;
erx_clk : in std_ulogic;
erxd : in std_logic_vector(3 downto 0);
erx_dv : in std_ulogic;
erx_er : in std_ulogic;
erx_col : in std_ulogic;
erx_crs : in std_ulogic;
etxd : out std_logic_vector(3 downto 0);
etx_en : out std_ulogic;
etx_er : out std_ulogic;
emdc : out std_ulogic;
emddis : out std_logic;
epwrdwn : out std_ulogic;
ereset : out std_ulogic;
esleep : out std_ulogic;
epause : out std_ulogic;
pci_rst : inout std_logic; -- PCI bus
pci_clk : in std_ulogic;
pci_gnt : in std_ulogic;
pci_idsel : in std_ulogic;
pci_lock : inout std_ulogic;
pci_ad : inout std_logic_vector(31 downto 0);
pci_cbe : inout std_logic_vector(3 downto 0);
pci_frame : inout std_ulogic;
pci_irdy : inout std_ulogic;
pci_trdy : inout std_ulogic;
pci_devsel : inout std_ulogic;
pci_stop : inout std_ulogic;
pci_perr : inout std_ulogic;
pci_par : inout std_ulogic;
pci_req : inout std_ulogic;
pci_serr : inout std_ulogic;
pci_host : in std_ulogic;
pci_66 : in std_ulogic;
pci_arb_req : in std_logic_vector(0 to 3);
pci_arb_gnt : out std_logic_vector(0 to 3);
can_txd : out std_ulogic;
can_rxd : in std_ulogic;
can_stb : out std_ulogic;
spw_clk : in std_ulogic;
spw_rxd : in std_logic_vector(0 to 2);
spw_rxdn : in std_logic_vector(0 to 2);
spw_rxs : in std_logic_vector(0 to 2);
spw_rxsn : in std_logic_vector(0 to 2);
spw_txd : out std_logic_vector(0 to 2);
spw_txdn : out std_logic_vector(0 to 2);
spw_txs : out std_logic_vector(0 to 2);
spw_txsn : out std_logic_vector(0 to 2);
tck, tms, tdi : in std_ulogic;
tdo : out std_ulogic
);
end;
architecture rtl of leon3mp is
constant blength : integer := 12;
constant maxahbmsp : integer := NCPU+CFG_AHB_UART+
CFG_GRETH+CFG_AHB_JTAG+CFG_GRPCI2_TARGET+CFG_GRPCI2_DMA;
constant maxahbm : integer := (CFG_SPW_NUM*CFG_SPW_EN) + maxahbmsp;
signal vcc, gnd : std_logic_vector(4 downto 0);
signal memi : memory_in_type;
signal memo : memory_out_type;
signal wpo : wprot_out_type;
signal sdi : sdctrl_in_type;
signal sdo : sdram_out_type;
signal sdo2, sdo3 : sdctrl_out_type;
signal apbi : apb_slv_in_type;
signal apbo : apb_slv_out_vector := (others => apb_none);
signal ahbsi : ahb_slv_in_type;
signal ahbso : ahb_slv_out_vector := (others => ahbs_none);
signal ahbmi : ahb_mst_in_type;
signal ahbmo : ahb_mst_out_vector := (others => ahbm_none);
signal clkm, rstn, rstraw, pciclk, sdclkl, spw_lclk : std_ulogic;
signal cgi : clkgen_in_type;
signal cgo : clkgen_out_type;
signal u1i, u2i, dui : uart_in_type;
signal u1o, u2o, duo : uart_out_type;
signal irqi : irq_in_vector(0 to NCPU-1);
signal irqo : irq_out_vector(0 to NCPU-1);
signal dbgi : l3_debug_in_vector(0 to NCPU-1);
signal dbgo : l3_debug_out_vector(0 to NCPU-1);
signal dsui : dsu_in_type;
signal dsuo : dsu_out_type;
signal pcii : pci_in_type;
signal pcio : pci_out_type;
signal ethi, ethi1, ethi2 : eth_in_type;
signal etho, etho1, etho2 : eth_out_type;
signal gpti : gptimer_in_type;
signal gpioi : gpio_in_type;
signal gpioo : gpio_out_type;
signal can_lrx, can_ltx : std_ulogic;
signal lclk, pci_lclk : std_ulogic;
signal pci_arb_req_n, pci_arb_gnt_n : std_logic_vector(0 to 3);
signal pci_dirq : std_logic_vector(3 downto 0);
signal spwi : grspw_in_type_vector(0 to 2);
signal spwo : grspw_out_type_vector(0 to 2);
signal spw_rxclk : std_logic_vector(0 to CFG_SPW_NUM-1);
signal dtmp : std_logic_vector(0 to CFG_SPW_NUM-1);
signal stmp : std_logic_vector(0 to CFG_SPW_NUM-1);
signal spw_rxtxclk : std_ulogic;
signal spw_rxclkn : std_ulogic;
attribute sync_set_reset : string;
attribute sync_set_reset of rstn : signal is "true";
constant BOARD_FREQ : integer := 40000; -- Board frequency in KHz
constant CPU_FREQ : integer := BOARD_FREQ * CFG_CLKMUL / CFG_CLKDIV;
constant IOAEN : integer := CFG_SDCTRL + CFG_CAN + CFG_GRPCI2_MASTER;
constant CFG_SDEN : integer := CFG_SDCTRL + CFG_MCTRL_SDEN ;
constant sysfreq : integer := (CFG_CLKMUL/CFG_CLKDIV)*40000;
begin
----------------------------------------------------------------------
--- Reset and Clock generation -------------------------------------
----------------------------------------------------------------------
vcc <= (others => '1'); gnd <= (others => '0');
cgi.pllctrl <= "00"; cgi.pllrst <= rstraw;
pllref_pad : clkpad generic map (tech => padtech) port map (pllref, cgi.pllref);
clk_pad : clkpad generic map (tech => padtech) port map (clk, lclk);
pci_clk_pad : clkpad generic map (tech => padtech, level => pci33)
port map (pci_clk, pci_lclk);
clkgen0 : clkgen -- clock generator
generic map (clktech, CFG_CLKMUL, CFG_CLKDIV, CFG_SDEN,
CFG_CLK_NOFB, (CFG_GRPCI2_MASTER+CFG_GRPCI2_TARGET), CFG_PCIDLL, CFG_PCISYSCLK)
port map (lclk, pci_lclk, clkm, open, open, sdclkl, pciclk, cgi, cgo);
sdclk_pad : outpad generic map (tech => padtech, slew => 1, strength => 24)
port map (sdclk, sdclkl);
rst0 : rstgen -- reset generator
port map (resetn, clkm, cgo.clklock, rstn, rstraw);
----------------------------------------------------------------------
--- AHB CONTROLLER --------------------------------------------------
----------------------------------------------------------------------
ahb0 : ahbctrl -- AHB arbiter/multiplexer
generic map (defmast => CFG_DEFMST, split => CFG_SPLIT,
rrobin => CFG_RROBIN, ioaddr => CFG_AHBIO,
ioen => IOAEN, nahbm => maxahbm, nahbs => 8)
port map (rstn, clkm, ahbmi, ahbmo, ahbsi, ahbso);
----------------------------------------------------------------------
--- LEON3 processor and DSU -----------------------------------------
----------------------------------------------------------------------
l3 : if CFG_LEON3 = 1 generate
cpu : for i in 0 to NCPU-1 generate
u0 : leon3s -- LEON3 processor
generic map (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU, CFG_V8,
0, CFG_MAC, pclow, CFG_NOTAG, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE,
CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ,
CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN,
CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP,
CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR, NCPU-1, CFG_DFIXED,
CFG_SCAN, CFG_MMU_PAGE, CFG_BP, CFG_NP_ASI, CFG_WRPSR)
port map (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso,
irqi(i), irqo(i), dbgi(i), dbgo(i));
end generate;
errorn_pad : odpad generic map (tech => padtech) port map (errorn, dbgo(0).error);
dsugen : if CFG_DSU = 1 generate
dsu0 : dsu3 -- LEON3 Debug Support Unit
generic map (hindex => 2, haddr => 16#900#, hmask => 16#F00#,
ncpu => NCPU, tbits => 30, tech => memtech, irq => 0, kbytes => CFG_ATBSZ)
port map (rstn, clkm, ahbmi, ahbsi, ahbso(2), dbgo, dbgi, dsui, dsuo);
dsuen_pad : inpad generic map (tech => padtech) port map (dsuen, dsui.enable);
dsubre_pad : inpad generic map (tech => padtech) port map (dsubre, dsui.break);
dsuact_pad : outpad generic map (tech => padtech) port map (dsuact, dsuo.active);
end generate;
end generate;
nodsu : if CFG_DSU = 0 generate
ahbso(2) <= ahbs_none; dsuo.tstop <= '0'; dsuo.active <= '0';
end generate;
dcomgen : if CFG_AHB_UART = 1 generate
dcom0: ahbuart -- Debug UART
generic map (hindex => NCPU, pindex => 7, paddr => 7)
port map (rstn, clkm, dui, duo, apbi, apbo(7), ahbmi, ahbmo(NCPU));
dsurx_pad : inpad generic map (tech => padtech) port map (dsurx, dui.rxd);
dsutx_pad : outpad generic map (tech => padtech) port map (dsutx, duo.txd);
end generate;
nouah : if CFG_AHB_UART = 0 generate apbo(7) <= apb_none; end generate;
ahbjtaggen0 :if CFG_AHB_JTAG = 1 generate
ahbjtag0 : ahbjtag generic map(tech => fabtech, hindex => NCPU+CFG_AHB_UART)
port map(rstn, clkm, tck, tms, tdi, tdo, ahbmi, ahbmo(NCPU+CFG_AHB_UART),
open, open, open, open, open, open, open, gnd(0));
end generate;
----------------------------------------------------------------------
--- Memory controllers ----------------------------------------------
----------------------------------------------------------------------
src : if CFG_SRCTRL = 1 generate -- 32-bit PROM/SRAM controller
sr0 : srctrl generic map (hindex => 0, ramws => CFG_SRCTRL_RAMWS,
romws => CFG_SRCTRL_PROMWS, ramaddr => 16#400#,
prom8en => CFG_SRCTRL_8BIT, rmw => CFG_SRCTRL_RMW)
port map (rstn, clkm, ahbsi, ahbso(0), memi, memo, sdo3);
apbo(0) <= apb_none;
end generate;
sdc : if CFG_SDCTRL = 1 generate
sdc : sdctrl generic map (hindex => 3, haddr => 16#600#, hmask => 16#F00#,
ioaddr => 1, fast => 0, pwron => 0, invclk => CFG_SDCTRL_INVCLK,
sdbits => 32 + 32*CFG_SDCTRL_SD64, pageburst => CFG_SDCTRL_PAGE)
port map (rstn, clkm, ahbsi, ahbso(3), sdi, sdo2);
sa_pad : outpadv generic map (width => 15, tech => padtech)
port map (sa, sdo2.address);
sd_pad : iopadv generic map (width => 32, tech => padtech)
port map (sd(31 downto 0), sdo2.data(31 downto 0), sdo2.bdrive, sdi.data(31 downto 0));
sd2 : if CFG_SDCTRL_SD64 = 1 generate
sd_pad2 : iopadv generic map (width => 32)
port map (sd(63 downto 32), sdo2.data, sdo2.bdrive, sdi.data(63 downto 32));
end generate;
sdcke_pad : outpadv generic map (width =>2, tech => padtech)
port map (sdcke, sdo2.sdcke);
sdwen_pad : outpad generic map (tech => padtech)
port map (sdwen, sdo2.sdwen);
sdcsn_pad : outpadv generic map (width =>2, tech => padtech)
port map (sdcsn, sdo2.sdcsn);
sdras_pad : outpad generic map (tech => padtech)
port map (sdrasn, sdo2.rasn);
sdcas_pad : outpad generic map (tech => padtech)
port map (sdcasn, sdo2.casn);
sddqm_pad : outpadv generic map (width =>8, tech => padtech)
port map (sddqm, sdo2.dqm(7 downto 0));
end generate;
mg2 : if CFG_MCTRL_LEON2 = 1 generate -- LEON2 memory controller
sr1 : mctrl generic map (hindex => 0, pindex => 0, paddr => 0,
srbanks => 4+CFG_MCTRL_5CS, sden => CFG_MCTRL_SDEN,
ram8 => CFG_MCTRL_RAM8BIT, ram16 => CFG_MCTRL_RAM16BIT,
invclk => CFG_MCTRL_INVCLK, sepbus => CFG_MCTRL_SEPBUS,
sdbits => 32 + 32*CFG_MCTRL_SD64, pageburst => CFG_MCTRL_PAGE)
port map (rstn, clkm, memi, memo, ahbsi, ahbso(0), apbi, apbo(0), wpo, sdo);
sdpads : if CFG_MCTRL_SDEN = 1 generate -- SDRAM controller
sd2 : if CFG_MCTRL_SEPBUS = 1 generate
sa_pad : outpadv generic map (width => 15) port map (sa, memo.sa);
bdr : for i in 0 to 3 generate
sd_pad : iopadv generic map (tech => padtech, width => 8)
port map (sd(31-i*8 downto 24-i*8), memo.data(31-i*8 downto 24-i*8),
memo.bdrive(i), memi.sd(31-i*8 downto 24-i*8));
sd2 : if CFG_MCTRL_SD64 = 1 generate
sd_pad2 : iopadv generic map (tech => padtech, width => 8)
port map (sd(31-i*8+32 downto 24-i*8+32), memo.data(31-i*8 downto 24-i*8),
memo.bdrive(i), memi.sd(31-i*8+32 downto 24-i*8+32));
end generate;
end generate;
end generate;
sdwen_pad : outpad generic map (tech => padtech)
port map (sdwen, sdo.sdwen);
sdras_pad : outpad generic map (tech => padtech)
port map (sdrasn, sdo.rasn);
sdcas_pad : outpad generic map (tech => padtech)
port map (sdcasn, sdo.casn);
sddqm_pad : outpadv generic map (width =>8, tech => padtech)
port map (sddqm, sdo.dqm);
sdcke_pad : outpadv generic map (width =>2, tech => padtech)
port map (sdcke, sdo.sdcke);
sdcsn_pad : outpadv generic map (width =>2, tech => padtech)
port map (sdcsn, sdo.sdcsn);
end generate;
end generate;
nosd0 : if (CFG_MCTRL_SDEN = 0) and (CFG_SDCTRL = 0) generate -- no SDRAM controller
sdcke_pad : outpadv generic map (width =>2, tech => padtech)
port map (sdcke, vcc(1 downto 0));
sdcsn_pad : outpadv generic map (width =>2, tech => padtech)
port map (sdcsn, vcc(1 downto 0));
end generate;
memi.brdyn <= '1'; memi.bexcn <= '1';
memi.writen <= '1'; memi.wrn <= "1111"; memi.bwidth <= "10";
mgpads : if (CFG_SRCTRL = 1) or (CFG_MCTRL_LEON2 = 1) generate -- prom/sram pads
addr_pad : outpadv generic map (width => 28, tech => padtech)
port map (address, memo.address(27 downto 0));
rams_pad : outpadv generic map (width => 5, tech => padtech)
port map (ramsn, memo.ramsn(4 downto 0));
roms_pad : outpadv generic map (width => 2, tech => padtech)
port map (romsn, memo.romsn(1 downto 0));
oen_pad : outpad generic map (tech => padtech)
port map (oen, memo.oen);
rwen_pad : outpadv generic map (width => 4, tech => padtech)
port map (rwen, memo.wrn);
roen_pad : outpadv generic map (width => 5, tech => padtech)
port map (ramoen, memo.ramoen(4 downto 0));
wri_pad : outpad generic map (tech => padtech)
port map (writen, memo.writen);
read_pad : outpad generic map (tech => padtech)
port map (read, memo.read);
iosn_pad : outpad generic map (tech => padtech)
port map (iosn, memo.iosn);
bdr : for i in 0 to 3 generate
data_pad : iopadv generic map (tech => padtech, width => 8)
port map (data(31-i*8 downto 24-i*8), memo.data(31-i*8 downto 24-i*8),
memo.bdrive(i), memi.data(31-i*8 downto 24-i*8));
end generate;
end generate;
----------------------------------------------------------------------
--- APB Bridge and various periherals -------------------------------
----------------------------------------------------------------------
bpromgen : if CFG_AHBROMEN /= 0 generate
brom : entity work.ahbrom
generic map (hindex => 5, haddr => CFG_AHBRODDR, pipe => CFG_AHBROPIP)
port map ( rstn, clkm, ahbsi, ahbso(5));
end generate;
nobpromgen : if CFG_AHBROMEN = 0 generate
ahbso(5) <= ahbs_none;
end generate;
----------------------------------------------------------------------
--- APB Bridge and various periherals -------------------------------
----------------------------------------------------------------------
apb0 : apbctrl -- AHB/APB bridge
generic map (hindex => 1, haddr => CFG_APBADDR)
port map (rstn, clkm, ahbsi, ahbso(1), apbi, apbo );
ua1 : if CFG_UART1_ENABLE /= 0 generate
uart1 : apbuart -- UART 1
generic map (pindex => 1, paddr => 1, pirq => 2, console => dbguart,
fifosize => CFG_UART1_FIFO)
port map (rstn, clkm, apbi, apbo(1), u1i, u1o);
u1i.rxd <= rxd1; u1i.ctsn <= '0'; u1i.extclk <= '0'; txd1 <= u1o.txd;
end generate;
noua0 : if CFG_UART1_ENABLE = 0 generate apbo(1) <= apb_none; end generate;
ua2 : if CFG_UART2_ENABLE /= 0 generate
uart2 : apbuart -- UART 2
generic map (pindex => 9, paddr => 9, pirq => 3, fifosize => CFG_UART2_FIFO)
port map (rstn, clkm, apbi, apbo(9), u2i, u2o);
u2i.rxd <= rxd2; u2i.ctsn <= '0'; u2i.extclk <= '0'; txd2 <= u2o.txd;
end generate;
noua1 : if CFG_UART2_ENABLE = 0 generate apbo(9) <= apb_none; end generate;
irqctrl : if CFG_IRQ3_ENABLE /= 0 generate
irqctrl0 : irqmp -- interrupt controller
generic map (pindex => 2, paddr => 2, ncpu => NCPU)
port map (rstn, clkm, apbi, apbo(2), irqo, irqi);
end generate;
irq3 : if CFG_IRQ3_ENABLE = 0 generate
x : for i in 0 to NCPU-1 generate
irqi(i).irl <= "0000";
end generate;
apbo(2) <= apb_none;
end generate;
pci_dirq(3 downto 1) <= (others => '0');
pci_dirq(0) <= orv(irqi(0).irl);
gpt : if CFG_GPT_ENABLE /= 0 generate
timer0 : gptimer -- timer unit
generic map (pindex => 3, paddr => 3, pirq => CFG_GPT_IRQ,
sepirq => CFG_GPT_SEPIRQ, sbits => CFG_GPT_SW, ntimers => CFG_GPT_NTIM,
nbits => CFG_GPT_TW, wdog => CFG_GPT_WDOG)
port map (rstn, clkm, apbi, apbo(3), gpti, open);
gpti <= gpti_dhalt_drive(dsuo.tstop);
end generate;
notim : if CFG_GPT_ENABLE = 0 generate apbo(3) <= apb_none; end generate;
gpio0 : if CFG_GRGPIO_ENABLE /= 0 generate -- GR GPIO unit
grgpio0: grgpio
generic map( pindex => 11, paddr => 11, imask => CFG_GRGPIO_IMASK,
nbits => CFG_GRGPIO_WIDTH)
port map( rstn, clkm, apbi, apbo(11), gpioi, gpioo);
pio_pads : for i in 0 to CFG_GRGPIO_WIDTH-1 generate
pio_pad : iopad generic map (tech => padtech)
port map (gpio(i), gpioo.dout(i), gpioo.oen(i), gpioi.din(i));
end generate;
end generate;
-----------------------------------------------------------------------
--- PCI ------------------------------------------------------------
-----------------------------------------------------------------------
pp0 : if (CFG_GRPCI2_MASTER+CFG_GRPCI2_TARGET) /= 0 generate
grpci2xt : if (CFG_GRPCI2_TARGET) /= 0 and (CFG_GRPCI2_MASTER+CFG_GRPCI2_DMA) = 0 generate
pci0 : grpci2
generic map (
memtech => memtech,
hmindex => CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG,
hdmindex => CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+1,
hsindex => 4, haddr => 16#C00#, hmask => 16#E00#, ioaddr => 16#400#,
pindex => 4, paddr => 4, irq => 4, irqmode => 0,
master => CFG_GRPCI2_MASTER, target => CFG_GRPCI2_TARGET,
dma => CFG_GRPCI2_DMA, tracebuffer => CFG_GRPCI2_TRACE,
vendorid => CFG_GRPCI2_VID, deviceid => CFG_GRPCI2_DID,
classcode => CFG_GRPCI2_CLASS, revisionid => CFG_GRPCI2_RID,
cap_pointer => CFG_GRPCI2_CAP, ext_cap_pointer => CFG_GRPCI2_NCAP,
iobase => CFG_AHBIO, extcfg => CFG_GRPCI2_EXTCFG,
bar0 => CFG_GRPCI2_BAR0, bar1 => CFG_GRPCI2_BAR1,
bar2 => CFG_GRPCI2_BAR2, bar3 => CFG_GRPCI2_BAR3,
bar4 => CFG_GRPCI2_BAR4, bar5 => CFG_GRPCI2_BAR5,
fifo_depth => CFG_GRPCI2_FDEPTH, fifo_count => CFG_GRPCI2_FCOUNT,
conv_endian => CFG_GRPCI2_ENDIAN, deviceirq => CFG_GRPCI2_DEVINT,
deviceirqmask => CFG_GRPCI2_DEVINTMSK, hostirq => CFG_GRPCI2_HOSTINT,
hostirqmask => CFG_GRPCI2_HOSTINTMSK,
nsync => 2, hostrst => 1, bypass => CFG_GRPCI2_BYPASS,
debug => 0, tbapben => 0, tbpindex => 5, tbpaddr => 16#400#, tbpmask => 16#C00#
)
port map (
rstn, clkm, pciclk, pci_dirq, pcii, pcio, apbi, apbo(4), ahbsi, open, ahbmi,
ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG), ahbmi,
open, open, open, open, open);
end generate;
grpci2xmt : if (CFG_GRPCI2_MASTER+CFG_GRPCI2_TARGET) > 1 and (CFG_GRPCI2_DMA) = 0 generate
pci0 : grpci2
generic map (
memtech => memtech,
hmindex => CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG,
hdmindex => CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+1,
hsindex => 4, haddr => 16#C00#, hmask => 16#E00#, ioaddr => 16#400#,
pindex => 4, paddr => 4, irq => 4, irqmode => 0,
master => CFG_GRPCI2_MASTER, target => CFG_GRPCI2_TARGET,
dma => CFG_GRPCI2_DMA, tracebuffer => CFG_GRPCI2_TRACE,
vendorid => CFG_GRPCI2_VID, deviceid => CFG_GRPCI2_DID,
classcode => CFG_GRPCI2_CLASS, revisionid => CFG_GRPCI2_RID,
cap_pointer => CFG_GRPCI2_CAP, ext_cap_pointer => CFG_GRPCI2_NCAP,
iobase => CFG_AHBIO, extcfg => CFG_GRPCI2_EXTCFG,
bar0 => CFG_GRPCI2_BAR0, bar1 => CFG_GRPCI2_BAR1,
bar2 => CFG_GRPCI2_BAR2, bar3 => CFG_GRPCI2_BAR3,
bar4 => CFG_GRPCI2_BAR4, bar5 => CFG_GRPCI2_BAR5,
fifo_depth => CFG_GRPCI2_FDEPTH, fifo_count => CFG_GRPCI2_FCOUNT,
conv_endian => CFG_GRPCI2_ENDIAN, deviceirq => CFG_GRPCI2_DEVINT,
deviceirqmask => CFG_GRPCI2_DEVINTMSK, hostirq => CFG_GRPCI2_HOSTINT,
hostirqmask => CFG_GRPCI2_HOSTINTMSK,
nsync => 2, hostrst => 1, bypass => CFG_GRPCI2_BYPASS,
debug => 0, tbapben => 0, tbpindex => 5, tbpaddr => 16#400#, tbpmask => 16#C00#
)
port map (
rstn, clkm, pciclk, pci_dirq, pcii, pcio, apbi, apbo(4), ahbsi, ahbso(4), ahbmi,
ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG), ahbmi,
open, open, open, open, open);
end generate;
grpci2xd : if (CFG_GRPCI2_MASTER+CFG_GRPCI2_TARGET) /= 0 and CFG_GRPCI2_DMA /= 0 generate
pci0 : grpci2
generic map (
memtech => memtech,
hmindex => CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG,
hdmindex => CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+1,
hsindex => 4, haddr => 16#C00#, hmask => 16#E00#, ioaddr => 16#400#,
pindex => 4, paddr => 4, irq => 4, irqmode => 0,
master => CFG_GRPCI2_MASTER, target => CFG_GRPCI2_TARGET,
dma => CFG_GRPCI2_DMA, tracebuffer => CFG_GRPCI2_TRACE,
vendorid => CFG_GRPCI2_VID, deviceid => CFG_GRPCI2_DID,
classcode => CFG_GRPCI2_CLASS, revisionid => CFG_GRPCI2_RID,
cap_pointer => CFG_GRPCI2_CAP, ext_cap_pointer => CFG_GRPCI2_NCAP,
iobase => CFG_AHBIO, extcfg => CFG_GRPCI2_EXTCFG,
bar0 => CFG_GRPCI2_BAR0, bar1 => CFG_GRPCI2_BAR1,
bar2 => CFG_GRPCI2_BAR2, bar3 => CFG_GRPCI2_BAR3,
bar4 => CFG_GRPCI2_BAR4, bar5 => CFG_GRPCI2_BAR5,
fifo_depth => CFG_GRPCI2_FDEPTH, fifo_count => CFG_GRPCI2_FCOUNT,
conv_endian => CFG_GRPCI2_ENDIAN, deviceirq => CFG_GRPCI2_DEVINT,
deviceirqmask => CFG_GRPCI2_DEVINTMSK, hostirq => CFG_GRPCI2_HOSTINT,
hostirqmask => CFG_GRPCI2_HOSTINTMSK,
nsync => 2, hostrst => 1, bypass => CFG_GRPCI2_BYPASS,
debug => 0, tbapben => 0, tbpindex => 5, tbpaddr => 16#400#, tbpmask => 16#C00#
)
port map (
rstn, clkm, pciclk, pci_dirq, pcii, pcio, apbi, apbo(4), ahbsi, ahbso(4), ahbmi,
ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG), ahbmi,
ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+1),
open, open, open, open);
end generate;
pcia0 : if CFG_PCI_ARB = 1 generate -- PCI arbiter
pciarb0 : pciarb generic map (pindex => 10, paddr => 10,
apb_en => CFG_PCI_ARBAPB)
port map ( clk => pciclk, rst_n => pcii.rst,
req_n => pci_arb_req_n, frame_n => pcii.frame,
gnt_n => pci_arb_gnt_n, pclk => clkm,
prst_n => rstn, apbi => apbi, apbo => apbo(10)
);
pgnt_pad : outpadv generic map (tech => padtech, width => 4)
port map (pci_arb_gnt, pci_arb_gnt_n);
preq_pad : inpadv generic map (tech => padtech, width => 4)
port map (pci_arb_req, pci_arb_req_n);
end generate;
pcipads0 : pcipads generic map (padtech => padtech) -- PCI pads
port map ( pci_rst, pci_gnt, pci_idsel, pci_lock, pci_ad, pci_cbe,
pci_frame, pci_irdy, pci_trdy, pci_devsel, pci_stop, pci_perr,
pci_par, pci_req, pci_serr, pci_host, pci_66, pcii, pcio );
end generate;
nop1 : if CFG_GRPCI2_MASTER = 0 generate ahbso(4) <= ahbs_none; end generate;
nop2 : if CFG_GRPCI2_MASTER+CFG_GRPCI2_TARGET = 0 generate
apbo(4) <= apb_none; apbo(5) <= apb_none; end generate;
noarb : if CFG_PCI_ARB = 0 generate apbo(10) <= apb_none; end generate;
-----------------------------------------------------------------------
--- ETHERNET ---------------------------------------------------------
-----------------------------------------------------------------------
eth0 : if CFG_GRETH = 1 generate -- Gaisler ethernet MAC
e1 : greth generic map(hindex => NCPU+CFG_AHB_UART+CFG_GRPCI2_TARGET+CFG_GRPCI2_DMA+CFG_AHB_JTAG,
pindex => 15, paddr => 15, pirq => 7, memtech => memtech,
mdcscaler => CPU_FREQ/1000, enable_mdio => 1, fifosize => CFG_ETH_FIFO,
nsync => 1, edcl => CFG_DSU_ETH, edclbufsz => CFG_ETH_BUF,
macaddrh => CFG_ETH_ENM, macaddrl => CFG_ETH_ENL,
ipaddrh => CFG_ETH_IPM, ipaddrl => CFG_ETH_IPL)
port map( rst => rstn, clk => clkm, ahbmi => ahbmi,
ahbmo => ahbmo(NCPU+CFG_AHB_UART+CFG_GRPCI2_TARGET+CFG_GRPCI2_DMA+CFG_AHB_JTAG), apbi => apbi,
apbo => apbo(15), ethi => ethi, etho => etho);
emdio_pad : iopad generic map (tech => padtech)
port map (emdio, etho.mdio_o, etho.mdio_oe, ethi.mdio_i);
etxc_pad : clkpad generic map (tech => padtech, arch => 1)
port map (etx_clk, ethi.tx_clk);
erxc_pad : clkpad generic map (tech => padtech, arch => 1)
port map (erx_clk, ethi.rx_clk);
erxd_pad : inpadv generic map (tech => padtech, width => 4)
port map (erxd, ethi.rxd(3 downto 0));
erxdv_pad : inpad generic map (tech => padtech)
port map (erx_dv, ethi.rx_dv);
erxer_pad : inpad generic map (tech => padtech)
port map (erx_er, ethi.rx_er);
erxco_pad : inpad generic map (tech => padtech)
port map (erx_col, ethi.rx_col);
erxcr_pad : inpad generic map (tech => padtech)
port map (erx_crs, ethi.rx_crs);
etxd_pad : outpadv generic map (tech => padtech, width => 4)
port map (etxd, etho.txd(3 downto 0));
etxen_pad : outpad generic map (tech => padtech)
port map ( etx_en, etho.tx_en);
etxer_pad : outpad generic map (tech => padtech)
port map (etx_er, etho.tx_er);
emdc_pad : outpad generic map (tech => padtech)
port map (emdc, etho.mdc);
emdis_pad : outpad generic map (tech => padtech)
port map (emddis, vcc(0));
eepwrdwn_pad : outpad generic map (tech => padtech)
port map (epwrdwn, gnd(0));
esleep_pad : outpad generic map (tech => padtech)
port map (esleep, gnd(0));
epause_pad : outpad generic map (tech => padtech)
port map (epause, gnd(0));
ereset_pad : outpad generic map (tech => padtech)
port map (ereset, gnd(0));
end generate;
-----------------------------------------------------------------------
--- CAN --------------------------------------------------------------
-----------------------------------------------------------------------
can0 : if CFG_CAN = 1 generate
can0 : can_oc generic map (slvndx => 6, ioaddr => CFG_CANIO,
iomask => 16#FFF#, irq => CFG_CANIRQ, memtech => memtech)
port map (rstn, clkm, ahbsi, ahbso(6), can_lrx, can_ltx );
end generate;
ncan : if CFG_CAN = 0 generate ahbso(6) <= ahbs_none; end generate;
can_stb <= '0'; -- no standby
can_loopback : if CFG_CANLOOP = 1 generate
can_lrx <= can_ltx;
end generate;
can_pads : if CFG_CANLOOP = 0 generate
can_tx_pad : outpad generic map (tech => padtech)
port map (can_txd, can_ltx);
can_rx_pad : inpad generic map (tech => padtech)
port map (can_rxd, can_lrx);
end generate;
-----------------------------------------------------------------------
--- AHB RAM ----------------------------------------------------------
-----------------------------------------------------------------------
ocram : if CFG_AHBRAMEN = 1 generate
ahbram0 : ahbram generic map (hindex => 7, haddr => CFG_AHBRADDR,
tech => CFG_MEMTECH, kbytes => CFG_AHBRSZ, pipe => CFG_AHBRPIPE)
port map ( rstn, clkm, ahbsi, ahbso(7));
end generate;
nram : if CFG_AHBRAMEN = 0 generate ahbso(7) <= ahbs_none; end generate;
-----------------------------------------------------------------------
--- SPACEWIRE -------------------------------------------------------
-----------------------------------------------------------------------
spw : if CFG_SPW_EN > 0 generate
spw_clk_pad : clkpad generic map (tech => padtech) port map (spw_clk, spw_lclk);
spw_rxtxclk <= spw_lclk;
spw_rxclkn <= not spw_rxtxclk;
swloop : for i in 0 to CFG_SPW_NUM-1 generate
-- GRSPW2 PHY
spw2_input : if CFG_SPW_GRSPW = 2 generate
spw_phy0 : grspw2_phy
generic map(
scantest => 0,
tech => fabtech,
input_type => CFG_SPW_INPUT,
rxclkbuftype => 1)
port map(
rstn => rstn,
rxclki => spw_rxtxclk,
rxclkin => spw_rxclkn,
nrxclki => spw_rxtxclk,
di => dtmp(i),
si => stmp(i),
do => spwi(i).d(1 downto 0),
dov => spwi(i).dv(1 downto 0),
dconnect => spwi(i).dconnect(1 downto 0),
rxclko => spw_rxclk(i));
spwi(i).nd <= (others => '0'); -- Only used in GRSPW
spwi(i).dv(3 downto 2) <= "00"; -- For second port
end generate spw2_input;
-- GRSPW PHY
spw1_input: if CFG_SPW_GRSPW = 1 generate
spw_phy0 : grspw_phy
generic map(
tech => fabtech,
rxclkbuftype => 1,
scantest => 0)
port map(
rxrst => spwo(i).rxrst,
di => dtmp(i),
si => stmp(i),
rxclko => spw_rxclk(i),
do => spwi(i).d(0),
ndo => spwi(i).nd(4 downto 0),
dconnect => spwi(i).dconnect(1 downto 0));
spwi(i).d(1) <= '0';
spwi(i).dv <= (others => '0'); -- Only used in GRSPW2
spwi(i).nd(9 downto 5) <= "00000"; -- For second port
end generate spw1_input;
spwi(i).d(3 downto 2) <= "00"; -- For second port
spwi(i).dconnect(3 downto 2) <= "00"; -- For second port
spwi(i).s(1 downto 0) <= "00"; -- Only used in PHY
sw0 : grspwm generic map(tech => memtech, netlist => CFG_SPW_NETLIST,
hindex => maxahbmsp+i, pindex => 12+i, paddr => 12+i, pirq => 10+i,
sysfreq => sysfreq, nsync => 1, rmap => CFG_SPW_RMAP,
rmapcrc => CFG_SPW_RMAPCRC, rmapbufs => CFG_SPW_RMAPBUF,
ports => 1, dmachan => CFG_SPW_DMACHAN,
fifosize1 => CFG_SPW_AHBFIFO, fifosize2 => CFG_SPW_RXFIFO,
rxclkbuftype => 1, spwcore => CFG_SPW_GRSPW,
input_type => CFG_SPW_INPUT, output_type => CFG_SPW_OUTPUT,
rxtx_sameclk => CFG_SPW_RTSAME)
port map(resetn, clkm, spw_rxclk(i), spw_rxclk(i), spw_rxtxclk, spw_rxtxclk,
ahbmi, ahbmo(maxahbmsp+i),
apbi, apbo(12+i), spwi(i), spwo(i));
spwi(i).tickin <= '0'; spwi(i).rmapen <= '1';
spwi(i).clkdiv10 <= conv_std_logic_vector(sysfreq/10000-1, 8);
spwi(i).dcrstval <= (others => '0');
spwi(i).timerrstval <= (others => '0');
spw_rxd_pad : inpad_ds generic map (padtech, lvds, x25v)
port map (spw_rxd(i), spw_rxdn(i), dtmp(i));
spw_rxs_pad : inpad_ds generic map (padtech, lvds, x25v)
port map (spw_rxs(i), spw_rxsn(i), stmp(i));
spw_txd_pad : outpad_ds generic map (padtech, lvds, x25v)
port map (spw_txd(i), spw_txdn(i), spwo(i).d(0), gnd(0));
spw_txs_pad : outpad_ds generic map (padtech, lvds, x25v)
port map (spw_txs(i), spw_txsn(i), spwo(i).s(0), gnd(0));
end generate;
end generate;
-----------------------------------------------------------------------
--- Drive unused bus elements ---------------------------------------
-----------------------------------------------------------------------
-- nam1 : for i in maxahbm to NAHBMST-1 generate
-- ahbmo(i) <= ahbm_none;
-- end generate;
-- nam2 : if CFG_PCI > 1 generate
-- ahbmo(NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_PCI-1) <= ahbm_none;
-- end generate;
-- nap0 : for i in 12+(CFG_SPW_NUM*CFG_SPW_EN) to NAPBSLV-1 generate apbo(i) <= apb_none; end generate;
-- apbo(6) <= apb_none;
-- nah0 : for i in 9 to NAHBSLV-1 generate ahbso(i) <= ahbs_none; end generate;
-----------------------------------------------------------------------
--- Boot message ----------------------------------------------------
-----------------------------------------------------------------------
-- pragma translate_off
x : report_design
generic map (
msg1 => "LEON3 MP Demonstration design",
fabtech => tech_table(fabtech), memtech => tech_table(memtech),
mdel => 1
);
-- pragma translate_on
end;
| gpl-3.0 | 64bec536b3ac8629e31e009c8ed929c2 | 0.555087 | 3.482949 | false | false | false | false |
pwsoft/fpga_examples | rtl/ttl/ttl_pkg.vhd | 1 | 6,652 | -- -----------------------------------------------------------------------
--
-- Syntiac VHDL support files.
--
-- -----------------------------------------------------------------------
-- Copyright 2005-2018 by Peter Wendrich ([email protected])
-- http://www.syntiac.com
--
-- This source file is free software: you can redistribute it and/or modify
-- it under the terms of the GNU Lesser General Public License as published
-- by the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This source file is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
-- -----------------------------------------------------------------------
--
-- Support package to simulate various standard TTL and CMOS chips
-- from the 74xx and CD40xx series and be synthesized on a FPGA to
-- offer realtime emulation of circuits based on these chips.
-- The package offers a ttl_t type that has more states as just 0 and 1.
-- Most FPGAs are not capable of onchip tri-state busses (though could
-- possibly still be translated by the synthesis tool).
-- However real designs also use pullups and pulldowns, series
-- resistors and diode logic. This is more tricky to directly
-- translate to a std_logic based design.
--
-- So ttl_t supports next to logic ZERO and ONE also PULLDOWN, FLOAT and PULLUP
-- states. And as the handling of these states is abstracted in this package,
-- the ttl_t type can be extended with more voltage/current levels without
-- much change (often none) in the entities that implement the actual logic
-- of the chip emulation.
--
-- Operator overloading allows operators like "or", "nand" or "xor" to work
-- on ttl_t types. ttl2std and std2ttl allows interfacing with std_logic based
-- logic.
--
-- Busses can be build using the + operator. The signal with highest strength
-- will determine the result on the bus. If both ZERO and ONE are present
-- the result with be a SHORT that can be asserted or flagged.
--
-- The buffered routine converts weak signals (like a PULLUP) into a strong
-- ZERO or ONE.
--
-- is_low returns true if the ttl_t type represents a logic low.
-- is_high returns true if the ttl_t type represents a logic high.
-- -----------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package ttl_pkg is
type ttl_t is (
ZERO, -- Logic 0
PULLDOWN, -- Pulldown
FLOAT, -- Floating / Tristated
PULLUP, -- Pullup
ONE, -- Logic 1
SHORT -- Short
);
type ttl_list_t is array(integer range <>) of ttl_t;
constant GND : ttl_t := ZERO;
constant VCC : ttl_t := ONE;
function ttl2std(r : ttl_t) return std_logic;
function std2ttl(r : std_logic) return ttl_t;
function buffered(r : ttl_t) return ttl_t;
function is_low(r : ttl_t) return boolean;
function is_high(r : ttl_t) return boolean;
function "not"(r : ttl_t) return ttl_t;
function "and"(l,r : ttl_t) return ttl_t;
function "nand"(l,r : ttl_t) return ttl_t;
function "or"(l,r : ttl_t) return ttl_t;
function "xor"(l,r : ttl_t) return ttl_t;
function "+"(l,r : ttl_t) return ttl_t;
end package;
package body ttl_pkg is
function ttl2std(r : ttl_t) return std_logic is
variable result : std_logic := '1';
begin
result := '1';
if is_low(r) then
result := '0';
end if;
return result;
end function;
function std2ttl(r : std_logic) return ttl_t is
variable result : ttl_t := ONE;
begin
result := ONE;
if r = '0' then
result := ZERO;
end if;
return result;
end function;
function buffered(r : ttl_t) return ttl_t is
variable result : ttl_t := ONE;
begin
result := ONE;
if (is_low(r)) then
result := ZERO;
end if;
return result;
end function;
function is_low(r : ttl_t) return boolean is
begin
return (r = ZERO) or (r = PULLDOWN);
end function;
function is_high(r : ttl_t) return boolean is
begin
return (r = PULLUP) or (r = ONE);
end function;
function "not"(r : ttl_t) return ttl_t is
variable result : ttl_t := ONE;
begin
case r is
when ZERO | PULLDOWN | FLOAT => result := ONE;
when PULLUP | ONE => result := ZERO;
when SHORT => result := FLOAT;
end case;
return result;
end function;
function "and"(l,r : ttl_t) return ttl_t is
variable result : ttl_t := ONE;
begin
result := ONE;
if (l = ZERO) or (l = PULLDOWN) or (r = ZERO) or (r = PULLDOWN) then
result := ZERO;
end if;
return result;
end function;
function "nand"(l,r : ttl_t) return ttl_t is
variable result : ttl_t := ZERO;
begin
result := ZERO;
if (l = ZERO) or (l = PULLDOWN) or (r = ZERO) or (r = PULLDOWN) then
result := ONE;
end if;
return result;
end function;
function "or"(l,r : ttl_t) return ttl_t is
variable result : ttl_t := ZERO;
begin
result := ZERO;
if is_high(l) or is_high(r) then
result := ONE;
end if;
return result;
end function;
function "nor"(l,r : ttl_t) return ttl_t is
variable result : ttl_t := ONE;
begin
result := ONE;
if is_high(l) or is_high(r) then
result := ZERO;
end if;
return result;
end function;
function "xor"(l,r : ttl_t) return ttl_t is
variable result : ttl_t := ZERO;
begin
if (is_high(l) and is_low(r)) or (is_low(l) and is_high(r)) then
result := ONE;
end if;
return result;
end function;
function "+"(l,r : ttl_t) return ttl_t is
variable result : ttl_t := FLOAT;
begin
case l is
when ZERO =>
case r is
when ZERO | PULLDOWN | FLOAT | PULLUP => result := ZERO;
when ONE => result := SHORT;
when SHORT => result := SHORT;
end case;
when PULLDOWN =>
case r is
when ZERO => result := ZERO;
when PULLDOWN | FLOAT => result := PULLDOWN;
when PULLUP => result := FLOAT;
when ONE => result := ONE;
when SHORT => result := SHORT;
end case;
when FLOAT =>
result := r;
when PULLUP =>
case r is
when ZERO => result := ZERO;
when PULLDOWN => result := FLOAT;
when FLOAT | PULLUP => result := PULLUP;
when ONE => result := ONE;
when SHORT => result := SHORT;
end case;
when ONE =>
case r is
when ZERO => result := SHORT;
when PULLDOWN | FLOAT | PULLUP | ONE => result := ONE;
when SHORT => result := SHORT;
end case;
when SHORT =>
result := SHORT;
end case;
return result;
end function;
end package body; | lgpl-2.1 | dcd944a29621bf5bd33a094825f31b55 | 0.635147 | 3.326 | false | false | false | false |
hoglet67/CoPro6502 | src/T80/T16450.vhd | 2 | 13,027 | --
-- 16450 compatible UART with synchronous bus interface
-- RClk/BaudOut is XIn enable instead of actual clock
--
-- Version : 0249b
--
-- Copyright (c) 2002 Daniel Wallner ([email protected])
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
-- http://www.opencores.org/cvsweb.shtml/t80/
--
-- Limitations :
--
-- File history :
--
-- 0208 : First release
--
-- 0249 : Fixed interrupt and baud rate bugs found by Andy Dyer
-- Added modem status and break detection
-- Added support for 1.5 and 2 stop bits
--
-- 0249b : Fixed loopback break generation bugs found by Andy Dyer
--
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity T16450 is
port(
MR_n : in std_logic;
XIn : in std_logic;
RClk : in std_logic;
CS_n : in std_logic;
Rd_n : in std_logic;
Wr_n : in std_logic;
A : in std_logic_vector(2 downto 0);
D_In : in std_logic_vector(7 downto 0);
D_Out : out std_logic_vector(7 downto 0);
SIn : in std_logic;
CTS_n : in std_logic;
DSR_n : in std_logic;
RI_n : in std_logic;
DCD_n : in std_logic;
SOut : out std_logic;
RTS_n : out std_logic;
DTR_n : out std_logic;
OUT1_n : out std_logic;
OUT2_n : out std_logic;
BaudOut : out std_logic;
Intr : out std_logic
);
end T16450;
architecture rtl of T16450 is
signal RBR : std_logic_vector(7 downto 0); -- Reciever Buffer Register
signal THR : std_logic_vector(7 downto 0); -- Transmitter Holding Register
signal IER : std_logic_vector(7 downto 0); -- Interrupt Enable Register
signal IIR : std_logic_vector(7 downto 0); -- Interrupt Ident. Register
signal LCR : std_logic_vector(7 downto 0); -- Line Control Register
signal MCR : std_logic_vector(7 downto 0); -- MODEM Control Register
signal LSR : std_logic_vector(7 downto 0); -- Line Status Register
signal MSR : std_logic_vector(7 downto 0); -- MODEM Status Register
signal SCR : std_logic_vector(7 downto 0); -- Scratch Register
signal DLL : std_logic_vector(7 downto 0); -- Divisor Latch (LS)
signal DLM : std_logic_vector(7 downto 0); -- Divisor Latch (MS)
signal DM0 : std_logic_vector(7 downto 0);
signal DM1 : std_logic_vector(7 downto 0);
signal MSR_In : std_logic_vector(3 downto 0);
signal Bit_Phase : unsigned(3 downto 0);
signal Brk_Cnt : unsigned(3 downto 0);
signal RX_Filtered : std_logic;
signal RX_ShiftReg : std_logic_vector(7 downto 0);
signal RX_Bit_Cnt : integer range 0 to 11;
signal RX_Parity : std_logic;
signal RXD : std_logic;
signal TX_Tick : std_logic;
signal TX_ShiftReg : std_logic_vector(7 downto 0);
signal TX_Bit_Cnt : integer range 0 to 11;
signal TX_Parity : std_logic;
signal TX_Next_Is_Stop : std_logic;
signal TX_Stop_Bit : std_logic;
signal TXD : std_logic;
begin
DTR_n <= MCR(4) or not MCR(0);
RTS_n <= MCR(4) or not MCR(1);
OUT1_n <= MCR(4) or not MCR(2);
OUT2_n <= MCR(4) or not MCR(3);
SOut <= MCR(4) or (TXD and not LCR(6));
RXD <= SIn when MCR(4) = '0' else (TXD and not LCR(6));
Intr <= not IIR(0);
-- Registers
DM0 <= DLL when LCR(7) = '1' else RBR;
DM1 <= DLM when LCR(7) = '1' else IER;
with A select
D_Out <=
DM0 when "000",
DM1 when "001",
IIR when "010",
LCR when "011",
MCR when "100",
LSR when "101",
MSR when "110",
SCR when others;
process (MR_n, XIn)
begin
if MR_n = '0' then
THR <= "00000000";
IER <= "00000000";
LCR <= "00000000";
MCR <= "00000000";
MSR(3 downto 0) <= "0000";
SCR <= "00000000"; -- ??
DLL <= "00000000"; -- ??
DLM <= "00000000"; -- ??
elsif XIn'event and XIn = '1' then
if Wr_n = '0' and CS_n = '0' then
case A is
when "000" =>
if LCR(7) = '1' then
DLL <= D_In;
else
THR <= D_In;
end if;
when "001" =>
if LCR(7) = '1' then
DLM <= D_In;
else
IER(3 downto 0) <= D_In(3 downto 0);
end if;
when "011" =>
LCR <= D_In;
when "100" =>
MCR <= D_In;
when "111" =>
SCR <= D_In;
when others =>
end case;
end if;
if Rd_n = '0' and CS_n = '0' and A = "110" then
MSR(3 downto 0) <= "0000";
end if;
if MSR(4) /= MSR_In(0) then
MSR(0) <= '1';
end if;
if MSR(5) /= MSR_In(1) then
MSR(1) <= '1';
end if;
if MSR(6) = '0' and MSR_In(2) = '1' then
MSR(2) <= '1';
end if;
if MSR(7) /= MSR_In(3) then
MSR(3) <= '1';
end if;
end if;
end process;
process (XIn)
begin
if XIn'event and XIn = '1' then
if MCR(4) = '0' then
MSR(4) <= MSR_In(0);
MSR(5) <= MSR_In(1);
MSR(6) <= MSR_In(2);
MSR(7) <= MSR_In(3);
else
MSR(4) <= MCR(1);
MSR(5) <= MCR(0);
MSR(6) <= MCR(2);
MSR(7) <= MCR(3);
end if;
MSR_In(0) <= CTS_n;
MSR_In(1) <= DSR_n;
MSR_In(2) <= RI_n;
MSR_In(3) <= DCD_n;
end if;
end process;
IIR(7 downto 3) <= "00000";
IIR(2 downto 0) <=
"110" when IER(2) = '1' and LSR(4 downto 1) /= "0000" else
"100" when (IER(0) and LSR(0)) = '1' else
"010" when (IER(1) and LSR(5)) = '1' else
"000" when IER(3) = '1' and ((MCR(4) = '0' and MSR(3 downto 0) /= "0000") or
(MCR(4) = '1' and MCR(3 downto 0) /= "0000")) else
"001";
-- Baud x 16 clock generator
process (MR_n, XIn)
variable Baud_Cnt : unsigned(15 downto 0);
begin
if MR_n = '0' then
Baud_Cnt := "0000000000000000";
BaudOut <= '0';
elsif XIn'event and XIn = '1' then
if Baud_Cnt(15 downto 1) = "000000000000000" or (Wr_n = '0' and CS_n = '0' and A(2 downto 1) = "00" and LCR(7) = '1') then
Baud_Cnt(15 downto 8) := unsigned(DLM);
Baud_Cnt(7 downto 0) := unsigned(DLL);
BaudOut <= '1';
else
Baud_Cnt := Baud_Cnt - 1;
BaudOut <= '0';
end if;
end if;
end process;
-- Input filter
process (MR_n, XIn)
variable Samples : std_logic_vector(1 downto 0);
begin
if MR_n = '0' then
Samples := "11";
RX_Filtered <= '1';
elsif XIn'event and XIn = '1' then
if RClk = '1' then
Samples(1) := Samples(0);
Samples(0) := RXD;
end if;
if Samples = "00" then
RX_Filtered <= '0';
end if;
if Samples = "11" then
RX_Filtered <= '1';
end if;
end if;
end process;
-- Receive state machine
process (MR_n, XIn)
begin
if MR_n = '0' then
RBR <= "00000000";
LSR(4 downto 0) <= "00000";
Bit_Phase <= "0000";
Brk_Cnt <= "0000";
RX_ShiftReg(7 downto 0) <= "00000000";
RX_Bit_Cnt <= 0;
RX_Parity <= '0';
elsif XIn'event and XIn = '1' then
if A = "000" and LCR(7) = '0' and Rd_n = '0' and CS_n = '0' then
LSR(0) <= '0'; -- DR
end if;
if A = "101" and Rd_n = '0' and CS_n = '0' then
LSR(4) <= '0'; -- BI
LSR(3) <= '0'; -- FE
LSR(2) <= '0'; -- PE
LSR(1) <= '0'; -- OE
end if;
if RClk = '1' then
if RX_Bit_Cnt = 0 and (RX_Filtered = '1' or Bit_Phase = "0111") then
Bit_Phase <= "0000";
else
Bit_Phase <= Bit_Phase + 1;
end if;
if Bit_Phase = "1111" then
if RX_Filtered = '1' then
Brk_Cnt <= "0000";
else
Brk_Cnt <= Brk_Cnt + 1;
end if;
if Brk_Cnt = "1100" then
LSR(4) <= '1'; -- BI
end if;
end if;
if RX_Bit_Cnt = 0 then
if Bit_Phase = "0111" then
RX_Bit_Cnt <= RX_Bit_Cnt + 1;
RX_Parity <= not LCR(4); -- EPS
end if;
elsif Bit_Phase = "1111" then
RX_Bit_Cnt <= RX_Bit_Cnt + 1;
if RX_Bit_Cnt = 10 then -- Parity stop bit
RX_Bit_Cnt <= 0;
LSR(0) <= '1'; -- UART Receive complete
LSR(3) <= not RX_Filtered; -- Framing error
elsif (RX_Bit_Cnt = 9 and LCR(1 downto 0) = "11") or
(RX_Bit_Cnt = 8 and LCR(1 downto 0) = "10") or
(RX_Bit_Cnt = 7 and LCR(1 downto 0) = "01") or
(RX_Bit_Cnt = 6 and LCR(1 downto 0) = "00") then -- Stop bit/Parity
RX_Bit_Cnt <= 0;
if LCR(3) = '1' then -- PEN
RX_Bit_Cnt <= 10;
if LCR(5) = '1' then -- Stick parity
if RX_Filtered = LCR(4) then
LSR(2) <= '1';
end if;
else
if RX_Filtered /= RX_Parity then
LSR(2) <= '1';
end if;
end if;
else
LSR(0) <= '1'; -- UART Receive complete
LSR(3) <= not RX_Filtered; -- Framing error
end if;
RBR <= RX_ShiftReg(7 downto 0);
LSR(1) <= LSR(0);
if A = "101" and Rd_n = '0' and CS_n = '0' then
LSR(1) <= '0';
end if;
else
RX_ShiftReg(6 downto 0) <= RX_ShiftReg(7 downto 1);
RX_ShiftReg(7) <= RX_Filtered;
if LCR(1 downto 0) = "10" then
RX_ShiftReg(7) <= '0';
RX_ShiftReg(6) <= RX_Filtered;
end if;
if LCR(1 downto 0) = "01" then
RX_ShiftReg(7) <= '0';
RX_ShiftReg(6) <= '0';
RX_ShiftReg(5) <= RX_Filtered;
end if;
if LCR(1 downto 0) = "00" then
RX_ShiftReg(7) <= '0';
RX_ShiftReg(6) <= '0';
RX_ShiftReg(5) <= '0';
RX_ShiftReg(4) <= RX_Filtered;
end if;
RX_Parity <= RX_Filtered xor RX_Parity;
end if;
end if;
end if;
end if;
end process;
-- Transmit bit tick
process (MR_n, XIn)
variable TX_Cnt : unsigned(4 downto 0);
begin
if MR_n = '0' then
TX_Cnt := "00000";
TX_Tick <= '0';
elsif XIn'event and XIn = '1' then
TX_Tick <= '0';
if RClk = '1' then
TX_Cnt := TX_Cnt + 1;
if LCR(2) = '1' and TX_Stop_Bit = '1' then
if LCR(1 downto 0) = "00" then
if TX_Cnt = "10111" then
TX_Tick <= '1';
TX_Cnt(3 downto 0) := "0000";
end if;
else
if TX_Cnt = "11111" then
TX_Tick <= '1';
TX_Cnt(3 downto 0) := "0000";
end if;
end if;
else
TX_Cnt(4) := '1';
if TX_Cnt(3 downto 0) = "1111" then
TX_Tick <= '1';
end if;
end if;
end if;
end if;
end process;
-- Transmit state machine
process (MR_n, XIn)
begin
if MR_n = '0' then
LSR(7 downto 5) <= "011";
TX_Bit_Cnt <= 0;
TX_ShiftReg <= (others => '0');
TXD <= '1';
TX_Parity <= '0';
TX_Next_Is_Stop <= '0';
TX_Stop_Bit <= '0';
elsif XIn'event and XIn = '1' then
if TX_Tick = '1' then
TX_Next_Is_Stop <= '0';
TX_Stop_Bit <= TX_Next_Is_Stop;
case TX_Bit_Cnt is
when 0 =>
if LSR(5) <= '0' then -- THRE
TX_Bit_Cnt <= 1;
end if;
TXD <= '1';
when 1 => -- Start bit
TX_ShiftReg(7 downto 0) <= THR;
LSR(5) <= '1'; -- THRE
TXD <= '0';
TX_Parity <= not LCR(4); -- EPS
TX_Bit_Cnt <= TX_Bit_Cnt + 1;
when 10 => -- Parity bit
TXD <= TX_Parity;
if LCR(5) = '1' then -- Stick parity
TXD <= not LCR(4);
end if;
TX_Bit_Cnt <= 0;
TX_Next_Is_Stop <= '1';
when others =>
TX_Bit_Cnt <= TX_Bit_Cnt + 1;
if (TX_Bit_Cnt = 9 and LCR(1 downto 0) = "11") or
(TX_Bit_Cnt = 8 and LCR(1 downto 0) = "10") or
(TX_Bit_Cnt = 7 and LCR(1 downto 0) = "01") or
(TX_Bit_Cnt = 6 and LCR(1 downto 0) = "00") then
TX_Bit_Cnt <= 0;
if LCR(3) = '1' then -- PEN
TX_Bit_Cnt <= 10;
else
TX_Next_Is_Stop <= '1';
end if;
LSR(6) <= '1'; -- TEMT
end if;
TXD <= TX_ShiftReg(0);
TX_ShiftReg(6 downto 0) <= TX_ShiftReg(7 downto 1);
TX_Parity <= TX_ShiftReg(0) xor TX_Parity;
end case;
end if;
if Wr_n = '0' and CS_n = '0' and A = "000" and LCR(7) = '0' then
LSR(5) <= '0'; -- THRE
LSR(6) <= '0'; -- TEMT
end if;
end if;
end process;
end;
| gpl-3.0 | 3c6c618786f75fbd56aa688b5bb22cce | 0.566746 | 2.664553 | false | false | false | false |
GLADICOS/SPACEWIRESYSTEMC | rtl/RTL_VJ/SpaceWireCODECIPSynchronizeOnePulse.vhdl | 1 | 4,176 | ------------------------------------------------------------------------------
-- The MIT License (MIT)
--
-- Copyright (c) <2013> <Shimafuji Electric Inc., Osaka University, JAXA>
--
-- Permission is hereby granted, free of charge, to any person obtaining a copy
-- of this software and associated documentation files (the "Software"), to deal
-- in the Software without restriction, including without limitation the rights
-- to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-- copies of the Software, and to permit persons to whom the Software is
-- furnished to do so, subject to the following conditions:
--
-- The above copyright notice and this permission notice shall be included in
-- all copies or substantial portions of the Software.
--
-- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-- AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
-- OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
-- THE SOFTWARE.
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
entity SpaceWireCODECIPSynchronizeOnePulse is
port (
clock : in std_logic;
asynchronousClock : in std_logic;
reset : in std_logic;
asynchronousIn : in std_logic;
synchronizedOut : out std_logic
);
end SpaceWireCODECIPSynchronizeOnePulse;
architecture Behavioral of SpaceWireCODECIPSynchronizeOnePulse is
signal iLatchedAsynchronous : std_logic;
signal iSynchronousRegister : std_logic;
signal iSynchronousClear : std_logic;
signal iSynchronizedOut : std_logic;
begin
----------------------------------------------------------------------
-- Synchronize the asynchronous One Shot Pulse to Clock.
----------------------------------------------------------------------
synchronizedOut <= iSynchronizedOut;
----------------------------------------------------------------------
-- latch the rising edge of the input signal.
----------------------------------------------------------------------
process (asynchronousIn, reset, iSynchronousClear)
begin
if (reset = '1' or iSynchronousClear = '1') then
iLatchedAsynchronous <= '0';
elsif (asynchronousIn'event and asynchronousIn = '1') then
iLatchedAsynchronous <= '1';
end if;
end process;
----------------------------------------------------------------------
-- Synchronize a latch signal to Clock.
----------------------------------------------------------------------
process (clock, reset, iSynchronousClear)
begin
if (reset = '1' or iSynchronousClear = '1') then
iSynchronousRegister <= '0';
elsif (clock'event and clock = '1') then
if (iLatchedAsynchronous = '1') then
iSynchronousRegister <= '1';
end if;
end if;
end process;
----------------------------------------------------------------------
-- Output Clock synchronized One_Shot_Pulse and clear signal.
----------------------------------------------------------------------
process (clock, reset, iSynchronousRegister)
begin
if (reset = '1') then
iSynchronizedOut <= '0';
iSynchronousClear <= '0';
elsif (clock'event and clock = '1') then
if (iSynchronousRegister = '1' and iSynchronousClear = '0') then
iSynchronizedOut <= '1';
iSynchronousClear <= '1';
elsif (iSynchronousRegister = '1') then
iSynchronizedOut <= '0';
iSynchronousClear <= '0';
else
iSynchronizedOut <= '0';
iSynchronousClear <= '0';
end if;
end if;
end process;
end Behavioral;
| gpl-3.0 | 30a2c01a9772e11837fa5eb652532114 | 0.541427 | 5.092683 | false | false | false | false |
EliasLuiz/TCC | Leon3/lib/gaisler/misc/apbps2.vhd | 1 | 13,643 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: apbps2
-- File: apbps2.vhd
-- Author: Marcus Hellqvist, Jiri Gaisler
-- Modified by: Jan Andersson
-- Description: PS/2 keyboard interface
-----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.stdlib.all;
use grlib.amba.all;
use grlib.devices.all;
library gaisler;
use gaisler.misc.all;
entity apbps2 is
generic(
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#fff#;
pirq : integer := 0;
fKHz : integer := 50000;
fixed : integer := 0;
oepol : integer range 0 to 1 := 0
);
port(
rst : in std_ulogic; -- Global asynchronous reset
clk : in std_ulogic; -- Global clock
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
ps2i : in ps2_in_type;
ps2o : out ps2_out_type
);
end;
architecture rtl of apbps2 is
constant fifosize : integer := 16;
type rxstates is (idle,start,data,parity,stop);
type txstates is (idle,waitrequest,start,data,parity,stop,ack);
type fifotype is array(0 to fifosize-1) of std_logic_vector(7 downto 0);
type ps2_regs is record
-- status reg
data_ready : std_ulogic; -- data ready
parity_error : std_ulogic; -- parity carry out/ error bit
frame_error : std_ulogic; -- frame error when receiving
kb_inh : std_ulogic; -- keyboard inhibit
rbf : std_ulogic; -- receiver buffer full
tbf : std_ulogic; -- transmitter buffer full
rcnt : std_logic_vector(log2x(fifosize) downto 0); -- fifo counter
tcnt : std_logic_vector(log2x(fifosize) downto 0); -- fifo counter
-- control reg
rx_en : std_ulogic; -- receive enable
tx_en : std_ulogic; -- transmit enable
rx_irq_en : std_ulogic; -- keyboard interrupt enable
tx_irq_en : std_ulogic; -- transmit interrupt enable
-- others
tx_act : std_ulogic; -- tx active
rxdf : std_logic_vector(4 downto 0); -- rx data filter
rxcf : std_logic_vector(4 downto 0); -- rx clock filter
rx_irq : std_ulogic; -- keyboard interrupt
tx_irq : std_ulogic; -- transmit interrupt
rxfifo : fifotype; -- fifo with 16 bytes
rraddr : std_logic_vector(log2x(fifosize)-1 downto 0); -- fifo read address
rwaddr : std_logic_vector(log2x(fifosize)-1 downto 0); -- fifo write address
rxstate : rxstates;
txfifo : fifotype; -- fifo with 16 bytes
traddr : std_logic_vector(log2x(fifosize)-1 downto 0); -- fifo read address
twaddr : std_logic_vector(log2x(fifosize)-1 downto 0); -- fifo write address
txstate : txstates;
ps2_clk_syn : std_ulogic; -- ps2 clock synchronized
ps2_data_syn : std_ulogic; -- ps2 data synchronized
ps2_clk_fall : std_ulogic; -- ps2 clock falling edge detector
rshift : std_logic_vector(7 downto 0); -- shift register
rpar : std_ulogic; -- parity check bit
tshift : std_logic_vector(9 downto 0); -- shift register
tpar : std_ulogic; -- transmit parity bit
ps2clk : std_ulogic; -- ps2 clock
ps2data : std_ulogic; -- ps2 data
ps2clkoe : std_ulogic; -- ps2 clock output enable
ps2dataoe : std_ulogic; -- ps2 data output enable
timer : std_logic_vector(16 downto 0); -- timer
reload : std_logic_vector(16 downto 0); -- reload register
end record;
constant rcntzero : std_logic_vector(log2x(fifosize) downto 0) := (others => '0');
constant REVISION : integer := 2;
constant pconfig : apb_config_type := (
0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_APBPS2, 0, REVISION, pirq),
1 => apb_iobar(paddr, pmask));
constant OUTPUT : std_ulogic := conv_std_logic(oepol = 1);
constant INPUT : std_ulogic := conv_std_logic(oepol = 0);
signal r, rin : ps2_regs;
signal ps2_clk, ps2_data : std_ulogic;
begin
ps2_op : process(r, rst, ps2_clk, ps2_data,apbi)
variable v : ps2_regs;
variable rdata : std_logic_vector(31 downto 0);
variable irq : std_logic_vector(NAHBIRQ-1 downto 0);
begin
v := r;
rdata := (others => '0'); v.data_ready := '0'; irq := (others => '0'); irq(pirq) := r.rx_irq or r.tx_irq;
v.rx_irq := '0'; v.tx_irq := '0'; v.rbf := r.rcnt(log2x(fifosize)); v.tbf := r.tcnt(log2x(fifosize));
if r.rcnt /= rcntzero then v.data_ready := '1'; end if;
-- Synchronize and filter ps2 input
v.rxdf(0) := ps2_data; v.rxdf(4 downto 1) := r.rxdf(3 downto 0);
v.rxcf(0) := ps2_clk; v.rxcf(4 downto 1) := r.rxcf(3 downto 0);
if (r.rxdf(4) & r.rxdf(4) & r.rxdf(4) & r.rxdf(4)) = r.rxdf(3 downto 0) then
v.ps2_data_syn := r.rxdf(4);
end if;
if (r.rxcf(4) & r.rxcf(4) & r.rxcf(4) & r.rxcf(4)) = r.rxcf(3 downto 0) then
v.ps2_clk_syn := r.rxcf(4);
end if;
if (v.ps2_clk_syn /= r.ps2_clk_syn) and (v.ps2_clk_syn = '0') then
v.ps2_clk_fall := '1';
else
v.ps2_clk_fall := '0';
end if;
-- read registers
case apbi.paddr(3 downto 2) is
when "00" =>
rdata(7 downto 0) := r.rxfifo(conv_integer(r.rraddr));
if (apbi.psel(pindex) and apbi.penable and (not apbi.pwrite)) = '1' then
if r.rcnt /= rcntzero then
v.rxfifo(conv_integer(r.rraddr)) := (others => '0');
v.rraddr := r.rraddr + 1; v.rcnt := r.rcnt - 1;
end if;
end if;
when "01" =>
rdata(27 + log2x(fifosize) downto 27) := r.rcnt;
rdata(22 + log2x(fifosize) downto 22) := r.tcnt;
rdata(5 downto 0) := r.tbf & r.rbf & r.kb_inh & r.frame_error & r.parity_error & r.data_ready;
when "10" =>
rdata(3 downto 0) := r.tx_irq_en & r.rx_irq_en & r.tx_en & r.rx_en;
when others =>
if fixed = 0 then rdata(r.reload'range) := r.reload; end if;
end case;
-- write registers
if (apbi.psel(pindex) and apbi.penable and apbi.pwrite) = '1' then
case apbi.paddr(3 downto 2) is
when "00" =>
if r.tcnt(log2x(fifosize)) = '0' then
v.txfifo(conv_integer(r.twaddr)) := apbi.pwdata(7 downto 0);
v.twaddr := r.twaddr + 1; v.tcnt := r.tcnt + 1;
end if;
when "01" =>
v.kb_inh := apbi.pwdata(3);
v.frame_error := apbi.pwdata(2);
v.parity_error := apbi.pwdata(1);
when "10" =>
v.tx_irq_en := apbi.pwdata(3);
v.rx_irq_en := apbi.pwdata(2);
v.tx_en := apbi.pwdata(1);
v.rx_en := apbi.pwdata(0);
when "11" =>
if fixed = 0 then
v.reload := apbi.pwdata(r.reload'range);
end if;
when others =>
null;
end case;
end if;
case r.txstate is
when idle =>
if r.tx_en = '1' and r.tcnt /= rcntzero then
v.ps2clk := '0'; v.ps2clkoe := OUTPUT; v.tx_act := '1';
v.ps2data := '1'; v.ps2dataoe := OUTPUT; v.txstate := waitrequest;
if fixed = 1 then v.timer := conv_std_logic_vector(fKHz/10,r.timer'length);
else v.timer := r.reload; end if;
end if;
when waitrequest =>
v.timer := r.timer - 1;
if (v.timer(r.timer'left) and not r.timer(r.timer'left)) = '1' then
v.ps2data := '0'; v.txstate := start;
end if;
when start =>
v.ps2clkoe := INPUT; v.ps2clk := '1';
v.tshift := "10" & r.txfifo(conv_integer(r.traddr));
v.traddr := r.traddr + 1; v.tcnt := r.tcnt - 1;
v.tpar := '1';
v.txstate := data;
when data =>
if r.ps2_clk_fall = '1' then
v.ps2data := r.tshift(0);
v.tpar := r.tpar xor r.tshift(0);
v.tshift := '1' & r.tshift(9 downto 1);
if v.tshift = "1111111110" then v.txstate := parity; end if;
end if;
when parity =>
if r.ps2_clk_fall = '1' then
v.ps2data := r.tpar; v.txstate := stop;
end if;
when stop =>
if r.ps2_clk_fall = '1' then
v.ps2data := '1'; v.txstate := ack;
end if;
when ack =>
v.ps2dataoe := INPUT;
if r.ps2_clk_fall = '1' and r.ps2_data_syn = '0'then
v.ps2data := '1'; v.ps2dataoe := OUTPUT; v.tx_irq := r.tx_irq_en;
v.txstate := idle; v.tx_act := '0';
end if;
end case;
-- receiver state machine
case r.rxstate is
when idle =>
if (r.rx_en and not r.tx_act) = '1' then
v.rshift := (others => '1'); v.rxstate := start;
end if;
when start =>
if r.ps2_clk_fall = '1' then
if r.ps2_data_syn = '0' then
v.rshift := r.ps2_data_syn & r.rshift(7 downto 1);
v.rxstate := data; v.rpar := '0';
v.parity_error := '0'; v.frame_error := '0';
else v.rxstate := idle; end if;
end if;
when data =>
if r.ps2_clk_fall = '1' then
v.rshift := r.ps2_data_syn & r.rshift(7 downto 1);
v.rpar := r.rpar xor r.ps2_data_syn;
if r.rshift(0) = '0' then v.rxstate := parity; end if;
end if;
when parity =>
if r.ps2_clk_fall = '1' then
v.parity_error := r.rpar xor (not r.ps2_data_syn);
v.rxstate := stop;
end if;
when stop =>
if r.ps2_clk_fall = '1' then
if r.ps2_data_syn = '1' then
v.rx_irq := r.rx_irq_en; v.rxstate := idle;
if (r.rbf or r.parity_error) = '0' then
v.rxfifo(conv_integer(r.rwaddr)) := r.rshift(7 downto 0);
v.rwaddr := r.rwaddr + 1; v.rcnt := r.rcnt + 1;
end if;
else v.frame_error := '1'; v.rxstate := idle; end if;
end if;
end case;
-- keyboard inhibit / high impedance
if v.tx_act = '0' then
if r.rbf = '1' then
v.kb_inh := '1'; v.ps2clk := '0'; v.ps2data := '1';
v.ps2dataoe := OUTPUT; v.ps2clkoe := OUTPUT;
else
v.ps2clk := '1'; v.ps2data := '1'; v.ps2dataoe := INPUT;
v.ps2clkoe := INPUT;
end if;
end if;
if r.tx_act = '1' then
v.rxstate := idle;
end if;
-- reset operations
if rst = '0' then
v.data_ready := '0'; v.kb_inh := '0'; v.parity_error := '0';
v.frame_error := '0'; v.rx_en := '0'; v.tx_act := '0';
v.tx_en := '0'; v.rx_irq := '0'; v.tx_irq := '0';
v.ps2_clk_fall := '0'; v.ps2_clk_syn := '0'; v.ps2_data_syn := '0';
v.rshift := (others => '0'); v.rxstate := idle; v.txstate := idle;
v.rraddr := (others => '0'); v.rwaddr := (others => '0');
v.rcnt := (others => '0'); v.traddr := (others => '0');
v.twaddr := (others => '0'); v.tcnt := (others => '0');
v.tshift := (others => '0'); v.tpar := '0';
if fixed = 0 then
v.reload := conv_std_logic_vector(fKHz/10,r.reload'length);
end if;
end if;
if fixed = 1 then v.reload := (others => '0'); end if;
-- update registers
rin <= v;
-- drive outputs
apbo.prdata <= rdata;
apbo.pirq <= irq;
apbo.pindex <= pindex;
ps2o.ps2_clk_o <= r.ps2clk;
ps2o.ps2_clk_oe <= r.ps2clkoe;
ps2o.ps2_data_o <= r.ps2data;
ps2o.ps2_data_oe <= r.ps2dataoe;
end process;
apbo.pconfig <= pconfig;
regs : process(clk)
begin
if rising_edge(clk) then
r <= rin;
ps2_data <= to_x01(ps2i.ps2_data_i);
ps2_clk <= to_x01(ps2i.ps2_clk_i);
end if;
end process;
-- pragma translate_off
bootmsg : report_version
generic map ("apbps2_" & tost(pindex) & ": APB PS2 interface rev " &
tost(REVISION) & ", irq " & tost(pirq));
-- pragma translate_on
end;
| gpl-3.0 | 974f02c84fedc9d5b82399a189f6db34 | 0.510518 | 3.350442 | false | false | false | false |
pwsoft/fpga_examples | quartus/chameleon2/chameleon2_gigatron/chameleon2_gigatron.vhd | 1 | 11,432 | -- -----------------------------------------------------------------------
--
-- Turbo Chameleon
--
-- Multi purpose FPGA expansion for the Commodore 64 computer
--
-- -----------------------------------------------------------------------
-- Copyright 2005-2021 by Peter Wendrich ([email protected])
-- http://www.syntiac.com/chameleon.html
--
-- This source file is free software: you can redistribute it and/or modify
-- it under the terms of the GNU Lesser General Public License as published
-- by the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This source file is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
-- -----------------------------------------------------------------------
--
-- Part of the Gigatron emulator.
-- Toplevel for Chameleon V2 hardware.
--
-- -----------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-- -----------------------------------------------------------------------
architecture rtl of chameleon2 is
-- System settings
constant clk_ticks_per_usec : integer := 100;
constant resetCycles : integer := 255;
-- Clocks
signal sysclk : std_logic;
signal clk_150 : std_logic;
-- Clocks enables
signal ena_1mhz : std_logic;
signal ena_1khz : std_logic;
-- System control signals
signal reset : std_logic;
signal reset_trig : std_logic;
signal reboot_trig : std_logic;
-- SPI controller
signal spi_req : std_logic;
signal spi_ack : std_logic;
signal spi_d : unsigned(7 downto 0);
signal spi_q : unsigned(7 downto 0);
-- PHI 2
signal phi : std_logic;
signal phi_mode : std_logic;
signal phi_cnt : unsigned(7 downto 0);
signal end_of_phi_0 : std_logic;
signal end_of_phi_1 : std_logic;
signal phi_post_1 : std_logic;
signal phi_post_2 : std_logic;
signal phi_post_3 : std_logic;
signal phi_post_4 : std_logic;
-- LEDs
signal led_green : std_logic;
signal led_red : std_logic;
-- PS/2 Keyboard
signal ps2_keyboard_clk_in : std_logic;
signal ps2_keyboard_dat_in : std_logic;
signal ps2_keyboard_clk_out : std_logic;
signal ps2_keyboard_dat_out : std_logic;
-- PS/2 Mouse
signal ps2_mouse_clk_in: std_logic;
signal ps2_mouse_dat_in: std_logic;
signal ps2_mouse_clk_out: std_logic;
signal ps2_mouse_dat_out: std_logic;
-- USB debugging
signal usb_remote_reset : std_logic;
signal reconfig_request : std_logic;
signal reconfig_slot : unsigned(3 downto 0);
signal flashslot : unsigned(4 downto 0);
signal usb_req : std_logic;
signal usb_ack : std_logic;
signal usb_we : std_logic;
signal usb_a : unsigned(31 downto 0);
signal usb_d : unsigned(7 downto 0);
signal usb_q : unsigned(7 downto 0);
-- IEC bus
signal iec_clk_in : std_logic := '1';
signal iec_dat_in : std_logic := '1';
signal iec_atn_in : std_logic := '1';
signal iec_srq_in : std_logic := '1';
-- Docking station
signal docking_joystick1 : unsigned(6 downto 0);
signal docking_joystick2 : unsigned(6 downto 0);
signal docking_joystick3 : unsigned(6 downto 0);
signal docking_joystick4 : unsigned(6 downto 0);
signal docking_keys : unsigned(63 downto 0);
signal docking_restore_n : std_logic;
-- Audio output (sigma delta)
signal audio : std_logic;
-- Video pipeline
signal end_of_line : std_logic;
signal end_of_frame : std_logic;
type vid_stage_t is record
ena_pixel : std_logic;
hsync : std_logic;
vsync : std_logic;
x : unsigned(11 downto 0);
y : unsigned(11 downto 0);
r : unsigned(4 downto 0);
g : unsigned(4 downto 0);
b : unsigned(4 downto 0);
end record;
signal vga_master : vid_stage_t;
begin
-- -----------------------------------------------------------------------
-- Unused pins
-- -----------------------------------------------------------------------
clock_ior <= '1';
clock_iow <= '1';
iec_clk_out <= '0';
iec_atn_out <= '0';
iec_dat_out <= '0';
iec_srq_out <= '0';
irq_out <= '0';
nmi_out <= '0';
sigma_l <= audio;
sigma_r <= audio;
rtc_cs <= '0';
mmc_cs <= '1';
-- -----------------------------------------------------------------------
-- PLL
-- -----------------------------------------------------------------------
pll_blk : block
signal ram_clk_loc : std_logic;
begin
pll_inst : entity work.pll50
port map (
inclk0 => clk50m,
c0 => sysclk,
c1 => ram_clk,
c2 => open,
c3 => open,
locked => open
);
end block;
-- -----------------------------------------------------------------------
-- 1 Mhz and 1 Khz clocks
-- -----------------------------------------------------------------------
my1Mhz : entity work.chameleon_1mhz
generic map (
clk_ticks_per_usec => 100
)
port map (
clk => sysclk,
ena_1mhz => ena_1mhz,
ena_1mhz_2 => open
);
my1Khz : entity work.chameleon_1khz
port map (
clk => sysclk,
ena_1mhz => ena_1mhz,
ena_1khz => ena_1khz
);
-- -----------------------------------------------------------------------
-- Reset
-- -----------------------------------------------------------------------
reset_blk : block
signal reset_request : std_logic;
begin
reset_inst : entity work.gen_reset
generic map (
resetCycles => resetCycles
)
port map (
clk => sysclk,
enable => ena_1khz,
button => reset_request,
reset => reset
);
reset_request <= reset_trig or usb_remote_reset;
end block;
-- -----------------------------------------------------------------------
-- Gigatron entity
-- -----------------------------------------------------------------------
gigatron_top_blk : block
signal hsync : std_logic;
signal vsync : std_logic;
begin
gigatron_top_inst : entity work.gigatron_top
generic map (
clk_ticks_per_usec => clk_ticks_per_usec
)
port map (
clk => sysclk,
reset => reset,
flashslot => flashslot,
-- SPI interface
spi_cs_n => flash_cs,
spi_req => spi_req,
spi_ack => spi_ack,
spi_d => spi_d,
spi_q => spi_q,
-- SDRAM interface
ram_data => ram_d,
ram_addr => ram_a,
ram_ba => ram_ba,
ram_we => ram_we,
ram_ras => ram_ras,
ram_cas => ram_cas,
ram_ldqm => ram_ldqm,
ram_udqm => ram_udqm,
-- Keyboard and joystick
ps2_keyboard_clk_in => ps2_keyboard_clk_in,
ps2_keyboard_dat_in => ps2_keyboard_dat_in,
ps2_keyboard_clk_out => ps2_keyboard_clk_out,
ps2_keyboard_dat_out => ps2_keyboard_dat_out,
joystick => docking_joystick1,
-- LEDs
led_green => led_green,
led_red => led_red,
-- Audio
audio => audio,
-- Video
red => red,
grn => grn,
blu => blu,
hsync => hsync,
vsync => vsync
);
hsync_n <= not hsync;
vsync_n <= not vsync;
end block;
-- -----------------------------------------------------------------------
-- PS2IEC multiplexer
-- -----------------------------------------------------------------------
io_ps2iec_inst : entity work.chameleon2_io_ps2iec
port map (
clk => sysclk,
ps2iec_sel => ps2iec_sel,
ps2iec => ps2iec,
ps2_mouse_clk => ps2_mouse_clk_in,
ps2_mouse_dat => ps2_mouse_dat_in,
ps2_keyboard_clk => ps2_keyboard_clk_in,
ps2_keyboard_dat => ps2_keyboard_dat_in,
iec_clk => iec_clk_in,
iec_srq => iec_srq_in,
iec_atn => iec_atn_in,
iec_dat => iec_dat_in
);
-- -----------------------------------------------------------------------
-- Button debounce
-- -----------------------------------------------------------------------
chameleon_buttons_inst : entity work.chameleon_buttons
port map (
clk => sysclk,
ena_1khz => ena_1khz,
menu_mode => '0',
button_l => (not usart_cts),
button_m => (not freeze_btn),
button_r => (not reset_btn),
button_config => X"0",
reset => reset_trig,
boot => reboot_trig,
freeze => open,
menu => open
);
-- -----------------------------------------------------------------------
-- LED, PS2 and reset shiftregister
-- -----------------------------------------------------------------------
io_shiftreg_inst : entity work.chameleon2_io_shiftreg
port map (
clk => sysclk,
ser_out_clk => ser_out_clk,
ser_out_dat => ser_out_dat,
ser_out_rclk => ser_out_rclk,
reset_c64 => reset,
reset_iec => reset,
ps2_mouse_clk => ps2_mouse_clk_out,
ps2_mouse_dat => ps2_mouse_dat_out,
ps2_keyboard_clk => ps2_keyboard_clk_out,
ps2_keyboard_dat => ps2_keyboard_dat_out,
led_green => led_green,
led_red => led_red
);
-- -----------------------------------------------------------------------
-- SPI controller
-- -----------------------------------------------------------------------
chameleon2_spi_inst : entity work.chameleon2_spi
generic map (
clk_ticks_per_usec => clk_ticks_per_usec
)
port map (
clk => sysclk,
sclk => spi_clk,
miso => spi_miso,
mosi => spi_mosi,
req => spi_req,
ack => spi_ack,
speed => '1', -- select fast speed for flash access
d => spi_d,
q => spi_q
);
-- -----------------------------------------------------------------------
-- USB communication
-- -----------------------------------------------------------------------
usb_inst : entity work.chameleon_usb
generic map (
remote_reset_enabled => true
)
port map (
clk => sysclk,
req => usb_req,
ack => usb_ack,
we => usb_we,
a => usb_a,
d => usb_d,
q => usb_q,
reconfig => reboot_trig,
reconfig_slot => X"0",
flashslot => flashslot,
serial_clk => usart_clk,
serial_rxd => usart_tx,
serial_txd => usart_rx,
serial_cts_n => usart_rts,
remote_reset => usb_remote_reset
);
usb_ack <= usb_req;
-- -----------------------------------------------------------------------
-- Chameleon I/O
-- -----------------------------------------------------------------------
chameleon2_io_inst : entity work.chameleon2_io
generic map (
enable_docking_station => true,
enable_cdtv_remote => true,
enable_c64_joykeyb => true,
enable_c64_4player => false
)
port map (
-- Clocks
clk => sysclk,
ena_1mhz => ena_1mhz,
phi2_n => phi2_n,
dotclock_n => dotclk_n,
-- Control
reset => reset,
-- Toplevel signals
ir_data => ir_data,
ioef => ioef,
romlh => romlh,
dma_out => dma_out,
game_out => game_out,
exrom_out => exrom_out,
ba_in => ba_in,
rw_out => rw_out,
sa_dir => sa_dir,
sa_oe => sa_oe,
sa15_out => sa15_out,
low_a => low_a,
sd_dir => sd_dir,
sd_oe => sd_oe,
low_d => low_d,
-- C64 timing
phi_mode => phi_mode,
phi_out => phi,
phi_cnt => phi_cnt,
phi_end_0 => end_of_phi_0,
phi_end_1 => end_of_phi_1,
phi_post_1 => phi_post_1,
phi_post_2 => phi_post_2,
phi_post_3 => phi_post_3,
phi_post_4 => phi_post_4,
-- Joysticks
joystick1 => docking_joystick1,
joystick2 => docking_joystick2,
joystick3 => docking_joystick3,
joystick4 => docking_joystick4,
-- Keyboards
keys => docking_keys,
restore_key_n => docking_restore_n
-- amiga_reset_n => docking_amiga_reset_n,
-- amiga_trigger => docking_amiga_trigger,
-- amiga_scancode => docking_amiga_scancode,
);
end architecture;
| lgpl-2.1 | 78f667acac5dff66140fdb3d1ac98a17 | 0.518632 | 3.197762 | false | false | false | false |
EliasLuiz/TCC | Leon3/lib/techmap/maps/odpad.vhd | 1 | 5,766 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: odpad
-- File: odpad.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: tri-state output pad with technology wrapper
------------------------------------------------------------------------------
library techmap;
library ieee;
use ieee.std_logic_1164.all;
use techmap.gencomp.all;
use techmap.allpads.all;
entity odpad is
generic (tech : integer := 0; level : integer := 0; slew : integer := 0;
voltage : integer := x33v; strength : integer := 12;
oepol : integer := 0);
port (pad : out std_ulogic; i : in std_ulogic;
cfgi: in std_logic_vector(19 downto 0) := "00000000000000000000");
end;
architecture rtl of odpad is
signal gnd, oen, padx : std_ulogic;
begin
oen <= not i when oepol /= padoen_polarity(tech) else i;
gnd <= '0';
gen0 : if has_pads(tech) = 0 generate
pad <= gnd
-- pragma translate_off
after 2 ns
-- pragma translate_on
when oen = '0'
-- pragma translate_off
else 'X' after 2 ns when is_x(i)
-- pragma translate_on
else 'Z'
-- pragma translate_off
after 2 ns
-- pragma translate_on
;
end generate;
xcv : if (is_unisim(tech) = 1) generate
x0 : unisim_toutpad generic map (level, slew, voltage, strength)
port map (pad, gnd, oen);
end generate;
axc : if (tech = axcel) or (tech = axdsp) generate
x0 : axcel_toutpad generic map (level, slew, voltage, strength)
port map (pad, gnd, oen);
end generate;
pa3 : if (tech = proasic) or (tech = apa3) generate
x0 : apa3_toutpad generic map (level, slew, voltage, strength)
port map (pad, gnd, oen);
end generate;
pa3e : if (tech = apa3e) generate
x0 : apa3e_toutpad generic map (level, slew, voltage, strength)
port map (pad, gnd, oen);
end generate;
igl2 : if (tech = igloo2) or (tech = rtg4) generate
x0 : igloo2_toutpad port map (pad, gnd, oen);
end generate;
pa3l : if (tech = apa3l) generate
x0 : apa3l_toutpad generic map (level, slew, voltage, strength)
port map (pad, gnd, oen);
end generate;
fus : if (tech = actfus) generate
x0 : fusion_toutpad generic map (level, slew, voltage, strength)
port map (pad, gnd, oen);
end generate;
atc : if (tech = atc18s) generate
x0 : atc18_toutpad generic map (level, slew, voltage, strength)
port map (pad, gnd, oen);
end generate;
atcrh : if (tech = atc18rha) generate
x0 : atc18rha_toutpad generic map (level, slew, voltage, strength)
port map (pad, gnd, oen);
end generate;
um : if (tech = umc) generate
x0 : umc_toutpad generic map (level, slew, voltage, strength)
port map (pad, gnd, oen);
end generate;
rhu : if (tech = rhumc) generate
x0 : rhumc_toutpad generic map (level, slew, voltage, strength)
port map (pad, gnd, oen);
end generate;
ihp : if (tech = ihp25) generate
x0 : ihp25_toutpad generic map(level, slew, voltage, strength)
port map (pad, gnd, oen);
end generate;
rh18t : if (tech = rhlib18t) generate
x0 : rh_lib18t_iopad generic map (strength)
port map (padx, gnd, oen, open);
pad <= padx;
end generate;
ut025 : if (tech = ut25) generate
x0 : ut025crh_iopad generic map (level, slew, voltage, strength)
port map (padx, gnd, oen, open);
pad <= padx;
end generate;
ut13 : if (tech = ut130) generate
x0 : ut130hbd_iopad generic map (level, slew, voltage, strength)
port map (padx, gnd, oen, open);
pad <= padx;
end generate;
pere : if (tech = peregrine) generate
x0 : peregrine_iopad generic map (strength)
port map (padx, gnd, oen, open);
pad <= padx;
end generate;
nex : if (tech = easic90) generate
x0 : nextreme_toutpad generic map (level, slew, voltage, strength)
port map (pad, gnd, oen);
end generate;
n2x : if (tech = easic45) generate
x0 : n2x_toutpad generic map (level, slew, voltage, strength)
port map (pad, gnd, oen,cfgi(0), cfgi(1),
cfgi(19 downto 15), cfgi(14 downto 10),
cfgi(9 downto 6), cfgi(5 downto 2));
end generate;
end;
library techmap;
library ieee;
use ieee.std_logic_1164.all;
use techmap.gencomp.all;
entity odpadv is
generic (tech : integer := 0; level : integer := 0; slew : integer := 0;
voltage : integer := 0; strength : integer := 0; width : integer := 1;
oepol : integer := 0);
port (
pad : out std_logic_vector(width-1 downto 0);
i : in std_logic_vector(width-1 downto 0);
cfgi: in std_logic_vector(19 downto 0) := "00000000000000000000");
end;
architecture rtl of odpadv is
begin
v : for j in width-1 downto 0 generate
x0 : odpad generic map (tech, level, slew, voltage, strength, oepol)
port map (pad(j), i(j), cfgi);
end generate;
end;
| gpl-3.0 | e3ae3193cd1aea753d991032e1fbbcde | 0.633021 | 3.548308 | false | false | false | false |
EliasLuiz/TCC | Leon3/lib/testgrouppolito/pr/dprc.vhd | 1 | 15,634 | ------------------------------------------------------------------------------
-- Copyright (c) 2014, Pascal Trotta - Testgroup (Politecnico di Torino)
-- All rights reserved.
--
-- Redistribution and use in source and binary forms, with or without modification,
-- are permitted provided that the following conditions are met:
--
-- 1. Redistributions of source code must retain the above copyright notice, this
-- list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright notice, this
-- list of conditions and the following disclaimer in the documentation and/or other
-- materials provided with the distribution.
--
-- THIS SOURCE CODE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
-- MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
-- EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
-- GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
-- ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
-- OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
-----------------------------------------------------------------------------
-- Entity: dprc
-- File: dprc.vhd
-- Author: Pascal Trotta (TestGroup research group - Politecnico di Torino)
-- Contacts: [email protected] www.testgroup.polito.it
-- Description: Top entity of the dynamic partial reconfiguration controller for Xilinx FPGAs
-- (see the DPRC IP-core user manual for configuration and operations).
-- Last revision: 08/10/2014
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
library grlib;
use grlib.amba.all;
use grlib.devices.all;
use grlib.DMA2AHB_Package.all;
library techmap;
use techmap.gencomp.all;
library testgrouppolito;
use testgrouppolito.dprc_pkg.all;
library unisim;
use unisim.vcomponents.all;
--pragma translate_off
use std.textio.all;
use ieee.std_logic_textio.all;
use grlib.stdlib.report_version;
use grlib.stdlib.tost;
--pragma translate_on
entity dprc is
generic (
cfg_clkmul : integer := 2; -- clkraw multiplier
cfg_clkdiv : integer := 1; -- clkraw divisor
raw_freq : integer := 50000; -- Board frequency in KHz
clk_sel : integer := 0; -- Select between clkraw and clk100 for ICAP domain clk when configured in async or d2prc mode
hindex : integer := 2; -- AMBA AHB master index
vendorid : integer := VENDOR_CONTRIB; -- Vendor ID
deviceid : integer := CONTRIB_CORE1; -- Device ID
version : integer := 1; -- Device version
pindex : integer := 13; -- AMBA APB slave index
paddr : integer := 13; -- Address for APB I/O BAR
pmask : integer := 16#fff#; -- Mask for APB I/O BAR
pirq : integer := 0; -- Interrupt index
technology : integer := virtex4; -- FPGA target technology
crc_en : integer := 0; -- Enable bitstream verification (d2prc-crc mode)
edac_en : integer := 1; -- Enable bitstream EDAC (d2prc-edac mode)
words_block : integer := 10; -- Number of 32-bit words in a CRC-block
fifo_dcm_inst : integer := 0; -- Instantiate clock generator and fifo (async/sync mode)
fifo_depth : integer := 9); -- Number of addressing bits for the FIFO (true FIFO depth = 2**fifo_depth)
port (
rstn : in std_ulogic; -- Asynchronous Reset input (active low)
clkm : in std_ulogic; -- Clock input
clkraw : in std_ulogic; -- Raw Clock input
clk100 : in std_ulogic; -- 100 MHz Clock input
ahbmi : in ahb_mst_in_type; -- AHB master input
ahbmo : out ahb_mst_out_type; -- AHB master output
apbi : in apb_slv_in_type; -- APB slave input
apbo : out apb_slv_out_type; -- APB slave output
rm_reset : out std_logic_vector(31 downto 0)); -- Reconfigurable modules reset (1 bit for each different reconfigurable partition)
end dprc;
architecture dprc_rtl of dprc is
signal dma_in : DMA_In_Type;
signal dma_out : DMA_Out_Type;
signal icap_in, ricap_in : icap_in_type;
signal icap_out, ricap_out : icap_out_type;
signal clk_icap : std_ulogic;
signal icap_swapped : std_logic_vector(31 downto 0);
signal cgi : clkgen_in_type;
signal cgo : clkgen_out_type;
signal sysrstn : std_ulogic;
signal rego, reg_apbout : dprc_apbregout_type;
signal regi, reg_apbin : dprc_apbregin_type;
signal regcontrol, rregcontrol : dprc_apbcontrol_type;
signal wen_del : std_ulogic;
constant pconfig : apb_config_type := (0 => ahb_device_reg (vendorid, deviceid, 0, version, pirq), 1 => apb_iobar(paddr, pmask));
--pragma translate_off
file icap_file: TEXT open write_mode is "icap_data";
--pragma translate_on
begin
-- ahb interface
dma2ahb_inst: DMA2AHB
generic map(hindex => hindex, vendorid => vendorid, deviceid => deviceid, version => version)
port map(HCLK => clkm, HRESETn => sysrstn, DMAIn => dma_in, DMAOut => dma_out, AHBIn => ahbmi, AHBOut => ahbmo);
-- apb interface
apbo.pindex <= pindex;
apbo.pconfig <= pconfig;
comb : process(reg_apbout, reg_apbin, apbi, regcontrol, rregcontrol)
variable readdata : std_logic_vector(31 downto 0);
variable regvi : dprc_apbregin_type;
variable regvo : dprc_apbregout_type;
variable irq : std_logic_vector(NAHBIRQ-1 downto 0);
begin
-- assign register outputs to variables
regvi := reg_apbin;
regvo := reg_apbout;
-- read register
readdata := (others => '0');
case apbi.paddr(4 downto 2) is
when "000" =>
readdata := reg_apbin.control;
when "001" =>
readdata := reg_apbin.address;
when "010" =>
readdata := reg_apbout.status;
when "011" =>
readdata := reg_apbout.timer;
when "100" =>
readdata := reg_apbin.rm_reset;
when others =>
readdata := (others => '0');
end case;
-- write registers
if (apbi.psel(pindex) and apbi.penable and apbi.pwrite) = '1' then
case apbi.paddr(4 downto 2) is
when "000" =>
regvi.control := apbi.pwdata;
when "001" =>
regvi.address := apbi.pwdata;
when "100" =>
regvi.rm_reset := apbi.pwdata;
when others =>
end case;
end if;
-- timer
if regcontrol.timer_clear='1' then
regvo.timer := (others=>'0');
elsif regcontrol.timer_en='1' then
regvo.timer := regvo.timer+'1';
end if;
-- clear control registers
if regcontrol.control_clr='1' then
regvi.control(19 downto 0) := (others=>'0');
end if;
-- update status
if (regcontrol.status_clr='1') then
regvo.status := (others=>'0');
elsif regcontrol.status_en='1' then
regvo.status := regcontrol.status_value;
end if;
-- generate interrupt pulse after status register has been updated (if interrupts are enabled through control register bit 20)
irq := (others=>'0');
if (regcontrol.status_en='0') and (rregcontrol.status_en='1') and (reg_apbin.control(31)='1') then
irq(pirq) := '1';
end if;
apbo.pirq <= irq; -- drive interrupt on the bus
-- assign variables to register inputs
regi <= regvi;
rego <= regvo;
-- drive bus with read data
apbo.prdata <= readdata;
end process;
regs : process(clkm,sysrstn)
begin
if (sysrstn='0') then
reg_apbin.control <= (others => '0');
reg_apbin.address <= (others => '0');
reg_apbin.rm_reset <= (others => '0');
reg_apbout.status(31 downto 4) <= (others => '0');
reg_apbout.status(3 downto 0) <= (others => '1');
reg_apbout.timer <= (others => '0');
rregcontrol.status_en <= '0';
elsif rising_edge(clkm) then
reg_apbin <= regi;
reg_apbout <= rego;
rregcontrol.status_en <= regcontrol.status_en;
end if;
end process;
-- Register ICAP I/Os
regs_icap: process(clk_icap, sysrstn)
begin
if (sysrstn='0') then
ricap_out.odata<=(others=>'0');
ricap_out.busy<='0';
ricap_in.idata<=(others=>'0');
ricap_in.cen<='1';
ricap_in.wen<='1';
wen_del <= '1';
elsif rising_edge(clk_icap) then
ricap_out <= icap_out;
ricap_in <= icap_in;
wen_del <= ricap_in.wen;
end if;
end process;
-- operating mode selection
d2prc_crc_gen: if crc_en=1 generate
d2prc_inst : d2prc
generic map (technology => technology, crc_block => words_block, fifo_depth => fifo_depth)
port map (rstn => sysrstn, clkm => clkm, clk100 => clk_icap, dmai => dma_in, dmao => dma_out, icapi => icap_in, icapo => ricap_out, apbregi => reg_apbin, apbcontrol => regcontrol, rm_reset => rm_reset);
-- Boot message
-- pragma translate_off
bootmsg : report_version
generic map (
"dprc: ahb master " & tost(hindex) & ", apb slave " & tost(pindex) & ", Dynamic Partial Reconfiguration Controller, rev " &
tost(version) & ", irq " & tost(pirq) & ", mode D2PRC-CRC, fifo " & tost(2**fifo_depth) );
-- pragma translate_on
end generate;
d2prc_edac_gen: if edac_en=1 generate
d2prc_inst : d2prc_edac
generic map (technology => technology, fifo_depth => fifo_depth)
port map (rstn => sysrstn, clkm => clkm, clk100 => clk_icap, dmai => dma_in, dmao => dma_out, icapi => icap_in, icapo => ricap_out, apbregi => reg_apbin, apbcontrol => regcontrol, rm_reset => rm_reset);
-- Boot message
-- pragma translate_off
bootmsg : report_version
generic map (
"dprc: ahb master " & tost(hindex) & ", apb slave " & tost(pindex) & ", Dynamic Partial Reconfiguration Controller, rev " &
tost(version) & ", irq " & tost(pirq) & ", mode D2PRC-SECDED, fifo " & tost(2**fifo_depth) );
-- pragma translate_on
end generate;
asyncsync_gen: if (crc_en=0) and (edac_en=0) generate
async_gen: if fifo_dcm_inst=1 generate
async_dprc_inst : async_dprc
generic map(technology => technology, fifo_depth => fifo_depth)
port map(rstn => sysrstn, clkm => clkm, clk100 => clk_icap, dmai => dma_in, dmao => dma_out, icapi => icap_in, icapo => ricap_out, apbregi => reg_apbin, apbcontrol => regcontrol, rm_reset => rm_reset);
-- Boot message
-- pragma translate_off
bootmsg : report_version
generic map (
"dprc: ahb master " & tost(hindex) & ", apb slave " & tost(pindex) & ", Dynamic Partial Reconfiguration Controller, rev " &
tost(version) & ", irq " & tost(pirq) & ", mode DPRC-ASYNC, fifo " & tost(2**fifo_depth) );
-- pragma translate_on
end generate;
sync_gen: if fifo_dcm_inst=0 generate
sync_dprc_inst: sync_dprc
port map(rstn => sysrstn, clkm => clkm, dmai => dma_in, dmao => dma_out, icapi => icap_in, icapo => ricap_out, apbregi => reg_apbin, apbcontrol => regcontrol, rm_reset => rm_reset);
-- Boot message
-- pragma translate_off
bootmsg : report_version
generic map (
"dprc: ahb master " & tost(hindex) & ", apb slave " & tost(pindex) & ", Dynamic Partial Reconfiguration Controller, rev " &
tost(version) & ", irq " & tost(pirq) & ", mode DPRC-SYNC" );
-- pragma translate_on
end generate;
end generate;
-- clock generation (if necessary)
clock_gen: if (crc_en=1 or fifo_dcm_inst=1 or edac_en=1) generate
ext_clk_gen: if clk_sel=1 generate
clk_icap <= clk100; -- 100 MHz external clock
sysrstn <= rstn;
end generate;
int_clk_gen: if clk_sel=0 generate -- instantiate internal clock generator
cgi.pllctrl <= "00"; cgi.pllrst <= rstn;
clkgen_inst : clkgen
generic map (technology, cfg_clkmul, cfg_clkdiv, 0, 0, 0, 0, 0, raw_freq)
port map (clkin => clkraw, pciclkin => '0', clk => clk_icap, cgi => cgi, cgo => cgo);
sysrstn <= cgo.clklock;
end generate;
end generate;
noclock_gen: if (crc_en=0 and fifo_dcm_inst=0 and edac_en=0) generate
clk_icap <= clkm; -- system clock
sysrstn <= rstn;
end generate;
-- ICAP input data byte swapping (if necessary)
swap_gen: if (technology=virtex5 or technology=virtex6 or technology=virtex7 or technology=artix7 or technology=kintex7 or technology=zynq7000) generate
icapbyteswap(ricap_in.idata,icap_swapped);
end generate;
-- ICAP instantiation
icapv4_gen: if (technology=virtex4) generate
icap_virtex4_inst: ICAP_VIRTEX4
generic map (ICAP_WIDTH => "X32")
port map (BUSY => icap_out.busy, O => icap_out.odata, CE => ricap_in.cen, CLK => clk_icap, I => ricap_in.idata, WRITE => wen_del);
end generate;
icapv5_gen: if (technology=virtex5) generate
icap_virtex5_inst: ICAP_VIRTEX5
generic map (ICAP_WIDTH => "X32") -- 32 bit data width
port map (BUSY => icap_out.busy, O => icap_out.odata, CE => ricap_in.cen, CLK => clk_icap, I => icap_swapped, WRITE => wen_del);
end generate;
icapv6_gen: if (technology=virtex6) generate
icap_virtex6_inst: ICAP_VIRTEX6
generic map (DEVICE_ID => X"04244093", ICAP_WIDTH => "X32", SIM_CFG_FILE_NAME => "NONE")
port map (BUSY => icap_out.busy, O => icap_out.odata, CSB => ricap_in.cen, CLK => clk_icap, I => icap_swapped, RDWRB => wen_del);
end generate;
icap7_gen: if (technology=virtex7 or technology=artix7 or technology=kintex7 or technology=zynq7000) generate
icap_7series_inst: ICAPE2
generic map ( DEVICE_ID => X"03631093", ICAP_WIDTH => "X32", SIM_CFG_FILE_NAME => "NONE")
port map (O => icap_out.odata, CSIB => ricap_in.cen, CLK => clk_icap, I => icap_swapped, RDWRB => wen_del);
end generate;
--pragma translate_off
-- write ICAP data input to a file for verification purposes
wfile: process
variable l : line;
begin
while true loop
wait until rising_edge(clk_icap);
wait for 1 ns;
if ricap_in.cen='0' and wen_del='0' then
write(l, ricap_in.idata);
writeline(icap_file, l);
end if;
end loop;
end process;
--pragma translate_on
end dprc_rtl;
| gpl-3.0 | 527bc24b8d4b3b4f59435ede40d6f916 | 0.583984 | 4.00769 | false | false | false | false |
hoglet67/CoPro6502 | src/PDP2011/cpu.vhd | 1 | 236,365 |
--
-- Copyright (c) 2008-2015 Sytse van Slooten
--
-- Permission is hereby granted to any person obtaining a copy of these VHDL source files and
-- other language source files and associated documentation files ("the materials") to use
-- these materials solely for personal, non-commercial purposes.
-- You are also granted permission to make changes to the materials, on the condition that this
-- copyright notice is retained unchanged.
--
-- The materials are distributed in the hope that they will be useful, but WITHOUT ANY WARRANTY;
-- without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
--
-- $Revision: 1.424 $
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity pdp2011_cpu is
port(
addr_v : out std_logic_vector(15 downto 0); -- the virtual address that the cpu drives out to the bus for the current read or write
datain : in std_logic_vector(15 downto 0); -- when doing a read, the data input to the cpu
dataout : out std_logic_vector(15 downto 0); -- when doing a write, the data output from the cpu
wr : out std_logic; -- if '1', the cpu is doing a write to the bus and drives addr_v and dataout
rd : out std_logic; -- if '1', the cpu is doing a read from the bus, drives addr_v and reads datain
dw8 : out std_logic; -- if '1', the read or write initiated by the cpu is 8 bits wide
cp : out std_logic; -- if '1', the read or write should use the previous cpu mode
ifetch : out std_logic; -- if '1', this read is for an instruction fetch
id : out std_logic; -- if '1', the read or write should use data space
init : out std_logic; -- if '1', the devices on the bus should reset
iwait : out std_logic; -- if '1', the cpu is waiting for an interrupt
br7 : in std_logic; -- interrupt request, 7
bg7 : out std_logic; -- interrupt grant, 7
int_vector7 : in std_logic_vector(8 downto 0); -- interrupt vector, 7
br6 : in std_logic;
bg6 : out std_logic;
int_vector6 : in std_logic_vector(8 downto 0);
br5 : in std_logic;
bg5 : out std_logic;
int_vector5 : in std_logic_vector(8 downto 0);
bg4 : out std_logic; -- interrupt request, 4
br4 : in std_logic; -- interrupt grant, 4
int_vector4 : in std_logic_vector(8 downto 0); -- interrupt vector, 4
mmutrap : in std_logic; -- if '1', the mmu requests a trap to be serviced after the current instruction completes
ack_mmutrap : out std_logic; -- if '1', the mmu trap request is being acknowledged
mmuabort : in std_logic; -- if '1', the mmu requests that the current instruction is aborted because of a mmu fault
ack_mmuabort : out std_logic; -- if '1', the mmu abort request is being acknowledged
npr : in std_logic; -- non-processor request
npg : out std_logic; -- non-processor grant
nxmabort : in std_logic; -- nxm abort - a memory access cycle by the cpu refers to an address that does not exist
oddabort : in std_logic; -- odd abort - a memory access cycle by the cpu is for a full word, but uses an odd address
illhalt : out std_logic; -- a halt instruction was not executed because it was illegal in the current mode; for use in the cer cpu error register
ysv : out std_logic; -- a yellow stack trap is in progress - for use in the cer cpu error register
rsv : out std_logic; -- a red stack trap is in progress - for use in the cer cpu error register
cpu_stack_limit : in std_logic_vector(15 downto 0); -- the cpu stack limit control register value
cpu_kmillhalt : in std_logic; -- the control register setting for kernel mode illegal halt
sr0_ic : out std_logic; -- sr0/mmr0 instruction complete flag
sr1 : out std_logic_vector(15 downto 0); -- sr1/mmr1, address of the current instruction
sr2 : out std_logic_vector(15 downto 0); -- sr2, register autoincrement/autodecrement information for instruction restart
dstfreference : out std_logic; -- if '1', the destination reference is the final reference for this addressing mode
sr3csmenable : in std_logic; -- if '1', the enable csm instruction flag in sr3/mmr3 is set
psw_in : in std_logic_vector(15 downto 0); -- psw input from the control register address @ 177776
psw_in_we_even : in std_logic; -- psw input from the control register address @ 177776, write enable for the even address part
psw_in_we_odd : in std_logic; -- psw input from the control register address @ 177776, write enable for the odd address part
psw_out : out std_logic_vector(15 downto 0); -- psw output, current psw that the cpu uses
pir_in : in std_logic_vector(15 downto 0); -- pirq value input from the control register
modelcode : in integer range 0 to 255; -- cpu model code
have_fp : in integer range 0 to 2 := 2; -- floating point; 0=force disable; 1=force enable; 2=follow default for cpu model
have_fpa : in integer range 0 to 1 := 0; -- floating point accelerator present with J11 cpu
init_r7 : in std_logic_vector(15 downto 0) := x"f600"; -- start address after reset = o'173000' = m9312 hi rom
init_psw : in std_logic_vector(15 downto 0) := x"00e0"; -- initial psw for kernel mode, primary register set, priority 7
run : in std_logic := '0'; -- if '1', continue when the cpu is in halt state
clk : in std_logic; -- input clock
reset : in std_logic -- reset cpu, also causes init signal to devices on the bus to be asserted
);
end pdp2011_cpu;
architecture implementation of pdp2011_cpu is
component cpuregs is
port(
raddr : in std_logic_vector(5 downto 0);
waddr : in std_logic_vector(5 downto 0);
d : in std_logic_vector(15 downto 0);
o : out std_logic_vector(15 downto 0);
we : in std_logic;
clk : in std_logic
);
end component;
component fpuregs is
port(
raddr : in std_logic_vector(2 downto 0);
waddr : in std_logic_vector(2 downto 0);
d : in std_logic_vector(63 downto 0);
o : out std_logic_vector(63 downto 0);
fpmode : in std_logic;
we : in std_logic;
clk : in std_logic
);
end component;
type state_type is (
state_init, state_ifetch, state_idecode,
state_src0,
state_src1,
state_src2, state_src2w,
state_src3, state_src3a,
state_src4, state_src4w,
state_src5, state_src5a,
state_src6, state_src6a,
state_src7, state_src7a, state_src7b,
state_dst0,
state_dst1,
state_dst2,
state_dst3, state_dst3a,
state_dst4,
state_dst5, state_dst5a,
state_dst6, state_dst6a,
state_dst7, state_dst7a, state_dst7b,
state_sob,
state_jmp,
state_jsr, state_jsra, state_jsrb, state_jsrc,
state_rts, state_rtsa,
state_mark, state_marka, state_markb,
state_csm, state_csma, state_csmb, state_csmc, state_csmd, state_csme, state_csmf, state_csmg, state_csmh, state_csmi,
state_mfp, state_mfpa,
state_mtp, state_mtpa,
state_mtps,
state_dopr, state_dopra, state_doprb,
state_mul, state_mula, state_mulb,
state_div, state_diva, state_divb,
state_ash, state_ashb,
state_ashc, state_ashd, state_ashe,
state_xor,
state_ldfps,
state_stststore,
state_fptrap,
state_fpao,
state_fpso2,
state_fpwr, state_fpwr1, state_fpwr2,
state_fpd0,
state_fpir1, state_fpir2,
state_fpiwr, state_fpiww, state_fpiw1, state_fpiw2,
state_fpr1, state_fpr2, state_fpr3, state_fpr4,
state_fpww, state_fpw1, state_fpw2, state_fpw3, state_fpw4,
state_fprun,
state_fprunao,
state_tstset, state_wrtlck, state_wrtlcka,
state_rsv,
state_trap, state_trapa, state_trapb, state_trapc, state_trapw, state_trapd, state_trape, state_trapf,
state_rti, state_rtia, state_rtib,
state_illegalop,
state_mmuabort, state_mmutrap,
state_br7, state_br6, state_br5, state_br4,
state_store_alu_p, state_store_alu_w, state_store_alu_r,
state_npg
);
signal state : state_type := state_init;
signal pdststate : state_type := state_store_alu_r; -- initialize to a valid value, to enable optimizing
signal psrcstate : state_type := state_store_alu_r; -- initialize to a valid value, to enable optimizing
signal ir : std_logic_vector(15 downto 0);
signal ir_addr : std_logic_vector(15 downto 0);
signal ir_dop : std_logic;
signal ir_sop : std_logic;
signal ir_jmp : std_logic;
signal ir_jsr : std_logic;
signal ir_csm : std_logic;
signal ir_mfpi : std_logic;
signal ir_mfpd : std_logic;
signal ir_mf : std_logic;
signal ir_mtpi : std_logic;
signal ir_mtpd : std_logic;
signal ir_mt : std_logic;
signal ir_mtps : std_logic;
signal ir_mfps : std_logic;
signal ir_dopr : std_logic;
signal ir_fpsop1 : std_logic;
signal ir_fpsop2 : std_logic;
signal ir_fpao : std_logic;
signal ir_facdst : std_logic;
signal ir_facsrc : std_logic;
signal ir_facfdst : std_logic;
signal ir_facfsrc : std_logic;
signal ir_fpma48 : std_logic;
signal ir_fpmai : std_logic;
signal ir_fpmaf : std_logic;
signal ir_mpr : std_logic;
signal ir_rtt : std_logic;
signal ir_wait : std_logic;
signal ir_halt : std_logic;
signal ir_byte : std_logic;
signal ir_store : std_logic;
signal ir_srcr7 : std_logic;
signal ir_dstr7 : std_logic;
signal ir_dstm2r7 : std_logic;
signal temp_psw : std_logic_vector(15 downto 0);
signal trap_vector : std_logic_vector(8 downto 0);
signal trap_vectorp2 : std_logic_vector(8 downto 0);
-- addr
signal addr : std_logic_vector(15 downto 0);
-- psw
signal psw : std_logic_vector(15 downto 0) := init_psw;
signal pswmf : std_logic_vector(15 downto 8);
signal psw_delayedupdate : std_logic_vector(15 downto 0);
signal psw_delayedupdate_even : std_logic;
signal psw_delayedupdate_odd : std_logic;
-- pc
signal r7 : std_logic_vector(15 downto 0) := init_r7;
signal r7p2 : std_logic_vector(15 downto 0);
-- alu signals
signal alu_input : std_logic_vector(15 downto 0);
signal alus_input : std_logic_vector(15 downto 0);
signal alut_input : std_logic_vector(15 downto 0);
signal alu_output : std_logic_vector(15 downto 0);
signal alu_output_signext : std_logic_vector(15 downto 0);
signal alu_psw : std_logic_vector(3 downto 0);
-- register bus
signal rbus_raddr : std_logic_vector(5 downto 0);
signal rbus_waddr : std_logic_vector(5 downto 0);
signal rbus_d : std_logic_vector(15 downto 0);
signal rbus_o : std_logic_vector(15 downto 0);
signal rbus_we : std_logic;
signal rbus_ix : std_logic_vector(2 downto 0);
signal rbus_cpu_mode : std_logic_vector(1 downto 0);
signal rbus_data : std_logic_vector(15 downto 0);
signal rbus_data_m8 : std_logic_vector(15 downto 0);
signal rbus_data_m4 : std_logic_vector(15 downto 0);
signal rbus_data_m2 : std_logic_vector(15 downto 0);
signal rbus_data_m1 : std_logic_vector(15 downto 0);
signal rbus_data_p8 : std_logic_vector(15 downto 0);
signal rbus_data_p4 : std_logic_vector(15 downto 0);
signal rbus_data_p2 : std_logic_vector(15 downto 0);
signal rbus_data_p1 : std_logic_vector(15 downto 0);
signal rbus_data_mv : std_logic_vector(15 downto 0);
signal rbus_data_pv : std_logic_vector(15 downto 0);
-- sr1/mmr1
signal sr1_dst : std_logic_vector(7 downto 0);
signal sr1_src : std_logic_vector(7 downto 0);
signal sr1_dstd : std_logic_vector(4 downto 0);
signal sr1_srcd : std_logic_vector(4 downto 0);
signal sr1_p2 : std_logic_vector(4 downto 0);
signal sr1_pv : std_logic_vector(4 downto 0);
signal sr1_m2 : std_logic_vector(4 downto 0);
signal sr1_mv : std_logic_vector(4 downto 0);
-- current/previous mode flags
signal cp_req : std_logic;
signal cp_mf : std_logic;
signal cp_mt : std_logic;
-- id selector output based on state
signal id_select : std_logic;
-- rd output based on state
signal rd_select : std_logic;
signal rs_mt : std_logic;
signal rs_jj : std_logic;
-- address buffers
signal dest_addr : std_logic_vector(15 downto 0);
signal addr_indirect : std_logic_vector(15 downto 0);
signal finalreference : std_logic;
-- signals for eis operations (div, mul, ash, ashc)
signal eis_output : std_logic_vector(15 downto 0);
signal eis_output32 : std_logic_vector(15 downto 0);
signal eis_temp : std_logic_vector(15 downto 0);
signal eis_temp1 : std_logic_vector(31 downto 0);
signal eis_temp2 : std_logic_vector(31 downto 0);
signal eis_sequencer : std_logic_vector(4 downto 0);
signal eis_psw : std_logic_vector(3 downto 0);
signal eis_flag1 : std_logic;
signal eis_flag2 : std_logic;
-- counter for number of cycles to remain in init state
signal initcycles : integer range 0 to 7;
-- signals for yellow stack trap recognition
signal yellow_stack_trap : std_logic;
signal yellow_stack_trap_trigger : std_logic;
signal yellow_stack_trap_relevant_state : std_logic;
signal yellow_stack_trap_inhibit : std_logic;
-- signals for red stack trap recognition
signal red_stack_trap : std_logic;
signal red_stack_trap_trigger : std_logic;
signal red_stack_trap_relevant_state : std_logic;
-- floating point stuff
signal fps : std_logic_vector(15 downto 0);
signal fec : std_logic_vector(3 downto 0);
signal fea : std_logic_vector(15 downto 0);
-- floating point alu
signal falu_input : std_logic_vector(63 downto 0);
signal falus_input : std_logic_vector(63 downto 0);
signal falu_output : std_logic_vector(63 downto 0);
signal falu_output2 : std_logic_vector(63 downto 0);
signal falu_fps : std_logic_vector(3 downto 0);
signal falu_load : std_logic;
signal falu_done : std_logic;
signal falu_flag1 : std_logic;
type falu_fsm_type is (
falu_idle,
falu_align,
falu_mult,
falu_div,
falu_addsub,
falu_shift, falu_shift2, falu_shifte,
falu_norm,
falu_rt, falu_rtc,
falu_sep, falu_sep2, falu_sep3,
falu_zres,
falu_res
);
signal falu_fsm : falu_fsm_type := falu_idle;
signal falu_ccw : std_logic_vector(9 downto 0);
signal falu_state : integer range 0 to 163;
signal falu_work1 : std_logic_vector(58 downto 0);
signal falu_work2 : std_logic_vector(58 downto 0);
signal falu_pending_clear : std_logic;
signal falu_pending_fic : std_logic;
signal falu_pending_fiu : std_logic;
signal falu_pending_fiv : std_logic;
signal falu_pending_divz : std_logic;
-- floating point registers
signal fbus_raddr : std_logic_vector(2 downto 0);
signal fbus_waddr : std_logic_vector(2 downto 0);
signal fbus_d : std_logic_vector(63 downto 0);
signal fbus_o : std_logic_vector(63 downto 0);
signal fbus_we : std_logic;
signal fbus_fd : std_logic;
-- sob slowdown
signal sob_slowdown: integer range 0 to 255;
-- configuration stuff
signal have_sob_zkdjbug : integer range 0 to 1;
signal have_sob : integer range 0 to 1;
signal have_sxt : integer range 0 to 1;
signal have_rtt : integer range 0 to 1;
signal have_mark : integer range 0 to 1;
signal have_xor : integer range 0 to 1;
signal have_eis : integer range 0 to 1;
signal have_fpu_default : integer range 0 to 1;
signal have_fpu : integer range 0 to 1;
signal have_mtps : integer range 0 to 1;
signal have_mfp : integer range 0 to 1;
signal have_mpr : integer range 0 to 1;
signal have_spl : integer range 0 to 1;
signal have_csm : integer range 0 to 1;
signal have_red : integer range 0 to 1;
signal have_pswimmediateupdate : integer range 0 to 1;
signal have_mmuimmediateabort : integer range 0 to 1;
signal have_oddimmediateabort : integer range 0 to 1;
signal have_psw1512 : integer range 0 to 1;
signal have_psw11 : integer range 0 to 1;
signal have_psw8 : integer range 0 to 1;
begin
cpuregs0: cpuregs port map(
raddr => rbus_raddr,
waddr => rbus_waddr,
d => rbus_d,
o => rbus_o,
we => rbus_we,
clk => clk
);
fpuregs0: fpuregs port map(
raddr => fbus_raddr,
waddr => fbus_waddr,
d => fbus_d,
o => fbus_o,
fpmode => fbus_fd,
we => fbus_we,
clk => clk
);
r7p2 <= r7 + 2;
trap_vectorp2 <= trap_vector + 2;
alu_output_signext <= alu_output(7) & alu_output(7) & alu_output(7) & alu_output(7) & alu_output(7) & alu_output(7) & alu_output(7) & alu_output(7) & alu_output(7 downto 0);
-- generate bus stuff
iwait <= ir_wait;
-- finalreference : this bit signals states that access the final operand
-- this is needed for a) byte accesses; b) m[f|t]p[i|d]; so several other access types can be omitted here
with state select finalreference <=
'1' when state_dst1,
'1' when state_dst2,
'1' when state_dst3a,
'1' when state_dst4,
'1' when state_dst5a,
'1' when state_dst6a,
'1' when state_dst7b,
'1' when state_src1,
'1' when state_src2,
'1' when state_src3a,
'1' when state_src4,
'1' when state_src5a,
'1' when state_src6a,
'1' when state_src7b,
'1' when state_store_alu_w,
'0' when others;
-- dstfreference : this bit signals states that access the final operand in dest mode only
-- this is needed for maintenance mode in the mmu, and then most likely only to be able
-- to pass diagnostics without error messages
with state select dstfreference <=
'1' when state_dst1,
'1' when state_dst2,
'1' when state_dst3a,
'1' when state_dst4,
'1' when state_dst5a,
'1' when state_dst6a,
'1' when state_dst7b,
'1' when state_store_alu_w,
'0' when others;
-- generate signals for yellow stack trap
with state select yellow_stack_trap_relevant_state <=
'1' when state_dst4,
'1' when state_dst5a,
'1' when state_src4,
'1' when state_src5a,
'1' when state_trapc,
'1' when state_trapd,
'1' when state_csmc,
'1' when state_csme,
'1' when state_csmg,
'0' when others;
yellow_stack_trap_trigger <= '1'
when yellow_stack_trap_relevant_state = '1'
and rbus_ix = "110"
and psw(15 downto 14) = "00"
and yellow_stack_trap_inhibit = '0'
and red_stack_trap = '0'
and unsigned(cpu_stack_limit) > unsigned(rbus_data_m2)
else '0';
ysv <= yellow_stack_trap_trigger;
-- generate signals for red stack trap
with state select red_stack_trap_relevant_state <=
'1' when state_trapc,
'1' when state_trapd,
'0' when others;
red_stack_trap_trigger <= '1'
when red_stack_trap_relevant_state = '1'
-- and (mmuabort = '1' or oddabort = '1' or nxmabort = '1')
and (oddabort = '1' or nxmabort = '1')
else '0';
rsv <= red_stack_trap_trigger;
-- dw8 : data width 8, signals that a byte is accessed
dw8 <= '1' when (finalreference = '1' and ir_byte = '1') else '0';
-- cp : this address refers to current or previous mode
cp_mf <= '1' when finalreference = '1' and state /= state_store_alu_w and (ir_mfpi = '1' or ir_mfpd = '1') else '0';
cp_mt <= '1' when state = state_store_alu_w and (ir_mtpi = '1' or ir_mtpd = '1') else '0';
cp_req <= '1' when cp_mf = '1' or cp_mt = '1' else '0';
cp <= cp_req;
-- rd : cpu needs read transaction
with state select rd_select <=
'1' when state_idecode,
'1' when state_dst1,
'1' when state_dst2,
'1' when state_dst3 | state_dst3a,
'1' when state_dst4,
'1' when state_dst5 | state_dst5a,
'1' when state_dst6 | state_dst6a,
'1' when state_dst7 | state_dst7a | state_dst7b,
'1' when state_src1,
'1' when state_src2,
'1' when state_src3 | state_src3a,
'1' when state_src4,
'1' when state_src5 | state_src5a,
'1' when state_src6 | state_src6a,
'1' when state_src7 | state_src7a | state_src7b,
'1' when state_mfpa,
'1' when state_mtpa,
'1' when state_fpir1 | state_fpir2,
'1' when state_fpr1 | state_fpr2 | state_fpr3 | state_fpr4,
'1' when state_trapa | state_trapf,
'1' when state_csmi,
'1' when state_rtsa,
'1' when state_markb,
'1' when state_rtia | state_rtib,
'0' when others;
-- rs signals - read suppression for specific cases, because raising the read line would cause a wrong memory access - potentially a trap
rs_mt <= '1' when (ir_mtpi = '1' or ir_mtpd = '1') and finalreference = '1' and state /= state_store_alu_w else '0';
rs_jj <= '1' when (ir_jmp = '1' or ir_jsr = '1') and finalreference = '1' else '0';
rd <= '0' when rs_mt = '1' or rs_jj = '1' or ir_wait = '1' else rd_select;
-- wr : cpu needs write transaction
with state select wr <=
ir_store when state_store_alu_w,
'1' when state_stststore,
'1' when state_fpiw1 | state_fpiw2,
'1' when state_fpw1 | state_fpw2 | state_fpw3 | state_fpw4,
'1' when state_jsrb,
'1' when state_trapc | state_trapd,
'1' when state_csmc | state_csme | state_csmg,
'0' when others;
-- select data to write
with state select dataout <=
alu_output when state_store_alu_w,
fea when state_stststore,
falu_output(63 downto 48) when state_fpw1,
falu_output(47 downto 32) when state_fpw2,
falu_output(31 downto 16) when state_fpw3,
falu_output(15 downto 0) when state_fpw4,
falu_output(63 downto 48) when state_fpiw1,
falu_output(47 downto 32) when state_fpiw2,
rbus_data when state_jsrb,
temp_psw when state_trapc,
r7 when state_trapd,
temp_psw when state_csmc,
r7 when state_csme,
alu_output when state_csmg,
"0000000000000000" when others;
-- addr : select address to drive
with state select addr <=
r7 when state_ifetch, -- r7 is driven out during wait or halt states - only used for debugging, not to drive actual logic
r7 when state_idecode,
rbus_data when state_dst1,
rbus_data when state_dst2,
rbus_data when state_dst3,
addr_indirect when state_dst3a,
rbus_data_mv when state_dst4,
rbus_data_m2 when state_dst5,
addr_indirect when state_dst5a,
r7 when state_dst6,
addr_indirect when state_dst6a,
r7 when state_dst7,
addr_indirect when state_dst7a,
addr_indirect when state_dst7b,
rbus_data when state_src1,
rbus_data when state_src2,
rbus_data when state_src3,
addr_indirect when state_src3a,
rbus_data_mv when state_src4,
rbus_data_m2 when state_src5,
addr_indirect when state_src5a,
r7 when state_src6,
addr_indirect when state_src6a,
r7 when state_src7,
addr_indirect when state_src7a,
addr_indirect when state_src7b,
rbus_data_m2 when state_mfpa,
rbus_data when state_mtpa,
addr_indirect when state_fpir1,
addr_indirect when state_fpir2,
addr_indirect when state_fpr1,
addr_indirect when state_fpr2,
addr_indirect when state_fpr3,
addr_indirect when state_fpr4,
addr_indirect when state_fpiw1,
addr_indirect when state_fpiw2,
addr_indirect when state_fpw1,
addr_indirect when state_fpw2,
addr_indirect when state_fpw3,
addr_indirect when state_fpw4,
"0000000" & trap_vectorp2 when state_trapa,
"0000000" & trap_vector when state_trapb,
rbus_data_m2 when state_trapc,
rbus_data_m2 when state_trapd,
"0000000" & trap_vector when state_trapf,
addr_indirect when state_jsrb,
addr_indirect when state_rtsa,
rbus_data when state_markb,
rbus_data when state_rtia,
rbus_data when state_rtib,
rbus_data_m2 when state_csmc,
rbus_data_m2 when state_csme,
rbus_data_m2 when state_csmg,
"0000000" & trap_vector when state_csmi,
dest_addr when state_store_alu_w,
dest_addr when state_stststore,
"0000000000000000" when others;
addr_v <= addr;
-- id : map states onto instruction or data access
ir_dstm2r7 <= '0' when ir(5 downto 0) = "010111" else '1';
ir_srcr7 <= '0' when ir(8 downto 6) = "111" else '1';
ir_dstr7 <= '0' when ir(2 downto 0) = "111" else '1';
with state select id_select <=
'0' when state_idecode,
ir_dstr7 when state_dst1,
ir_dstr7 when state_dst2,
ir_dstr7 when state_dst3,
'1' when state_dst3a,
ir_dstr7 when state_dst4,
ir_dstr7 when state_dst5,
'1' when state_dst5a,
'0' when state_dst6,
'1' when state_dst6a,
'0' when state_dst7,
'1' when state_dst7a,
'1' when state_dst7b,
ir_srcr7 when state_src1,
ir_srcr7 when state_src2,
ir_srcr7 when state_src3,
'1' when state_src3a,
ir_srcr7 when state_src4,
ir_srcr7 when state_src5,
'1' when state_src5a,
'0' when state_src6,
'1' when state_src6a,
'0' when state_src7,
'1' when state_src7a,
'1' when state_src7b,
ir_dstm2r7 when state_fpir1,
'1' when state_fpir2,
ir_dstm2r7 when state_fpiw1,
'1' when state_fpiw2,
ir_dstm2r7 when state_fpr1,
'1' when state_fpr2 | state_fpr3 | state_fpr4,
ir_dstm2r7 when state_fpw1,
'1' when state_fpw2 | state_fpw3 | state_fpw4,
'1' when state_stststore, -- always in d-space, this is the second store - first is handled by store_alu_w
'1' when state_mfpa, -- move from previous, stack push is to current d-space
'1' when state_mtpa, -- move to previous, stack pop is from current d-space
'1' when state_trapa, -- d-mapping for loading the trap psw from kernel d-space
'1' when state_trapb, -- to enable debugging output via addr - d-mapping should be 1 to 1, i-mapping likely is not
'1' when state_trapc, -- stack is in d-space
'1' when state_trapd, -- stack is in d-space
'1' when state_trapf, -- d-mapping for loading the trap vector from kernel d-space
'1' when state_jsrb,
'1' when state_rtsa,
'0' when state_mark,
'0' when state_marka,
'1' when state_rtia, -- stack is in d-space
'1' when state_rtib, -- stack is in d-space
'1' when state_csmc | state_csme | state_csmg,
'0' when state_csmi, -- apparently; this at least is suggested by 0174_CKKTBD0_1144mmgmt.pdf
ir_dstm2r7 when state_store_alu_w,
'0' when others;
id <=
'1' when ir_mfpi = '1' and psw(15 downto 12) = "1111" and cp_req = '1'
else '0' when ir_mfpi = '1' and cp_req = '1'
else '1' when ir_mfpd = '1' and cp_req = '1'
else '0' when ir_mtpi = '1' and cp_req = '1'
else '1' when ir_mtpd = '1' and cp_req = '1'
else id_select;
-- psw that is output to the mmu
psw_out <= rbus_cpu_mode & pswmf(13 downto 8) & psw(7 downto 0);
-- psw filtered by cpu modelcode
pswmf(15 downto 12) <= psw(15 downto 12) when have_psw1512 = 1 else "0000";
pswmf(11) <= psw(11) when have_psw11 = 1 else '0';
pswmf(10 downto 9) <= "00";
pswmf(8) <= psw(8) when have_psw8 = 1 else '0';
-- pswmf(7 downto 0) <= psw(7 downto 0);
-- registers
rbus_raddr <= rbus_cpu_mode & pswmf(11) & rbus_ix;
with rbus_ix select rbus_data <=
r7 when "111",
rbus_o when others;
-- calculate amount of autoincrement or autodecrement
ir_fpma48 <= '1' when (fps(7) = '1' and ir(11 downto 8) /= "1111") or (fps(7) = '0' and ir(11 downto 8) = "1111") else '0';
rbus_data_m8 <= rbus_data - 8;
rbus_data_m4 <= rbus_data - 4;
rbus_data_m2 <= rbus_data - 2;
rbus_data_m1 <= rbus_data - 1;
rbus_data_p8 <= rbus_data + 8;
rbus_data_p4 <= rbus_data + 4;
rbus_data_p2 <= rbus_data + 2;
rbus_data_p1 <= rbus_data + 1;
rbus_data_mv <= rbus_data_m8 when (ir_fpmaf = '1' and ir_fpma48 = '1' and rbus_ix /= "111")
else rbus_data_m4 when (ir_fpmaf = '1' and ir_fpma48 = '0' and rbus_ix /= "111")
else rbus_data_m4 when (ir_fpmai = '1' and fps(6) = '1' and rbus_ix /= "111")
else rbus_data_m1 when (ir_byte = '1' and rbus_ix(2 downto 1) /= "11")
else rbus_data_m2;
rbus_data_pv <= rbus_data_p8 when (ir_fpmaf = '1' and ir_fpma48 = '1' and rbus_ix /= "111")
else rbus_data_p4 when (ir_fpmaf = '1' and ir_fpma48 = '0' and rbus_ix /= "111")
else rbus_data_p4 when (ir_fpmai = '1' and fps(6) = '1' and rbus_ix /= "111")
else rbus_data_p1 when (ir_byte = '1' and rbus_ix(2 downto 1) /= "11")
else rbus_data_p2;
-- sr1 cq. mmr1 construction
ir_mf <= '1' when ir_mfpi = '1' or ir_mfpd = '1' else '0';
ir_mt <= '1' when ir_mtpi = '1' or ir_mtpd = '1' else '0';
sr1_dst <= sr1_dstd & ir(2 downto 0) when sr1_dstd /= "00000" and ir(2 downto 0) /= "111"
else "00000000";
sr1_src <= sr1_srcd & "110" when (ir_mt = '1' or ir_mf = '1' or ir_jsr = '1') and sr1_srcd /= "00000"
else sr1_srcd & ir(8 downto 6) when sr1_srcd /= "00000" and ir(8 downto 6) /= "111" and ir_dop = '1'
else "00000000";
sr1 <= sr1_dst & sr1_src when (ir_dop = '1' or ir_jsr = '1') and sr1_srcd /= "00000"
else sr1_dst & sr1_src when sr1_dstd = "00000"
else sr1_src & sr1_dst;
-- sr1 <= sr1_src & sr1_dst when sr1_dstd /= "00000" and sr1_src(2 downto 0) /= sr1_dst(2 downto 0)
-- else "00000000" & (sr1_src(7 downto 3) + sr1_dst(7 downto 3)) & sr1_dst(2 downto 0) when sr1_src(2 downto 0) = sr1_dst(2 downto 0)
-- else "00000000" & sr1_src;
sr1_p2 <= "00010";
sr1_pv <= "01000" when (ir_fpmaf = '1' and ir_fpma48 = '1' and rbus_ix /= "111")
else "00100" when (ir_fpmaf = '1' and ir_fpma48 = '0' and rbus_ix /= "111")
else "00100" when (ir_fpmai = '1' and fps(6) = '1' and rbus_ix /= "111")
else "00001" when (ir_byte = '1' and rbus_ix(2 downto 1) /= "11")
else "00010";
sr1_m2 <= "11110";
sr1_mv <= "11000" when (ir_fpmaf = '1' and ir_fpma48 = '1' and rbus_ix /= "111")
else "11100" when (ir_fpmaf = '1' and ir_fpma48 = '0' and rbus_ix /= "111")
else "11100" when (ir_fpmai = '1' and fps(6) = '1' and rbus_ix /= "111")
else "11111" when (ir_byte = '1' and rbus_ix(2 downto 1) /= "11")
else "11110";
-- cpu model configuration
have_sob_zkdjbug <= 0; -- set flag to enable bugfix for zkdj maindec
with modelcode select have_sob <=
1 when 3,
1 when 23 | 24, -- kdf11
1 when 34,
1 when 35 | 40,
1 when 44,
1 when 45 | 50 | 55,
1 when 60,
1 when 70,
1 when 73 | 83 | 84 | 93 | 94, -- kdj11
0 when others;
with modelcode select have_sxt <=
1 when 3,
1 when 23 | 24, -- kdf11
1 when 34,
1 when 35 | 40,
1 when 44,
1 when 45 | 50 | 55,
1 when 60,
1 when 70,
1 when 73 | 83 | 84 | 93 | 94, -- kdj11
0 when others;
with modelcode select have_rtt <=
1 when 3,
1 when 23 | 24, -- kdf11
1 when 34,
1 when 35 | 40,
1 when 44,
1 when 45 | 50 | 55,
1 when 60,
1 when 70,
1 when 73 | 83 | 84 | 93 | 94, -- kdj11
0 when others;
with modelcode select have_mark <=
1 when 3,
1 when 23 | 24, -- kdf11
1 when 34,
1 when 35 | 40,
1 when 44,
1 when 45 | 50 | 55,
1 when 60,
1 when 70,
1 when 73 | 83 | 84 | 93 | 94, -- kdj11
0 when others;
with modelcode select have_xor <=
1 when 3,
1 when 23 | 24, -- kdf11
1 when 34,
1 when 35 | 40,
1 when 44,
1 when 45 | 50 | 55,
1 when 60,
1 when 70,
1 when 73 | 83 | 84 | 93 | 94, -- kdj11
0 when others;
with modelcode select have_eis <=
1 when 23 | 24, -- kdf11
1 when 34,
1 when 35 | 40,
1 when 44,
1 when 45 | 50 | 55,
1 when 60,
1 when 70,
1 when 73 | 83 | 84 | 93 | 94, -- kdj11
0 when others;
with modelcode select have_fpu_default <=
1 when 23 | 24, -- kdf11
1 when 34,
1 when 44,
1 when 45 | 50 | 55,
1 when 60,
1 when 70,
1 when 73 | 83 | 84 | 93 | 94, -- kdj11
0 when others;
have_fpu <= have_fpu_default when have_fp = 2 else have_fp;
with modelcode select have_mtps <=
1 when 3,
1 when 4,
1 when 23 | 24, -- kdf11
1 when 34 | 35 | 40, -- kt11d!
1 when 73 | 83 | 84 | 93 | 94, -- kdj11
0 when others;
with modelcode select have_mfp <=
1 when 23 | 24, -- kdf11
1 when 34 | 35 | 40, -- kt11d!
1 when 44,
1 when 45 | 50 | 55,
1 when 60,
1 when 70,
1 when 73 | 83 | 84 | 93 | 94, -- kdj11
0 when others;
with modelcode select have_mpr <=
1 when 73 | 83 | 84 | 93 | 94, -- kdj11
0 when others;
with modelcode select have_spl <=
1 when 44,
1 when 45 | 50 | 55,
1 when 70,
1 when 73 | 83 | 84 | 93 | 94, -- kdj11
0 when others;
with modelcode select have_csm <=
1 when 44,
1 when 73 | 83 | 84 | 93 | 94, -- kdj11
0 when others;
with modelcode select have_red <=
1 when 35 | 40,
1 when 45 | 50 | 55,
1 when 60,
1 when 70,
1 when 73 | 83 | 84 | 93 | 94, -- kdj11
0 when others;
with modelcode select have_pswimmediateupdate <=
0 when 44, -- observed behaviour, at least from kkab
0 when 4,
-- 0 when 5 | 10, FIXME FIXME FIXME
-- 0 when 15 | 20,
1 when others;
with modelcode select have_mmuimmediateabort <=
-- 1 when 73 | 83 | 84 | 93 | 94, -- kdj11 -- as understood from 2.11BSD, trap.c
0 when others;
with modelcode select have_oddimmediateabort <=
1 when others; -- found no evidence that this is not actually what all pdps do
with modelcode select have_psw1512 <= -- curr/prev mode bits
1 when 23 | 24, -- kdf11
1 when 34 | 35 | 40, -- kt11d!
1 when 44,
1 when 45 | 50 | 55,
1 when 60,
1 when 70,
1 when 73 | 83 | 84 | 93 | 94, -- kdj11
0 when others;
with modelcode select have_psw11 <= -- general purpose reg set bit
1 when 45 | 50 | 55,
1 when 70,
1 when 73 | 83 | 84 | 93 | 94, -- kdj11
0 when others;
with modelcode select have_psw8 <= -- FIXME, what is this? 11/44 handbook has this as CIS insn suspension
1 when 23 | 24, -- kdf11
1 when 44,
1 when 73 | 83 | 84 | 93 | 94, -- kdj11
0 when others;
-- state sequencer
process(clk)
variable v_sop : std_logic;
variable v_dop : std_logic;
variable v_jmp : std_logic;
variable v_jsr : std_logic;
variable v_csm : std_logic;
variable v_mfpi : std_logic;
variable v_mfpd : std_logic;
variable v_mtpi : std_logic;
variable v_mtpd : std_logic;
variable v_mtps : std_logic;
variable v_mfps : std_logic;
variable v_dopr : std_logic;
variable v_mpr : std_logic;
variable v_fpsop1 : std_logic;
variable v_fpsop2 : std_logic;
variable v_fpao : std_logic;
begin
if clk='1' and clk'event then
--
-- synchronous reset; setup some signals that must have a known value after a reset signal to the cpu
--
if reset='1' then
r7 <= init_r7; -- start address
psw <= init_psw; -- initial psw
rbus_cpu_mode <= "00"; -- initial rbus access for kernel mode sp
ir_rtt <= '0'; -- no rtt
ir_wait <= '0'; -- not in wait state
ir_halt <= '0'; -- not halted
bg7 <= '0'; -- no bg7 active
bg6 <= '0'; -- no bg6 active
bg5 <= '0'; -- no bg5 active
bg4 <= '0'; -- no bg4 active
npg <= '0'; -- not granting bus
if have_red = 1 then
red_stack_trap <= '0'; -- not doing a red stack trap
end if;
yellow_stack_trap <= '0'; -- not doing a yellow stack trap
fps <= x"0000"; -- initial fp11 status register
fea <= x"0000"; -- initial fp11 error address register
fec <= "0000"; -- initial fp11 error code register
falu_load <= '0'; -- not doing a load of the fp11 fpao alu
psw_delayedupdate_even <= '0'; -- not updating psw after the fact - even address byte part
psw_delayedupdate_odd <= '0'; -- not updating psw after the fact - odd address byte
state <= state_init; -- first state in the major state machine after reset
initcycles <= 7; -- setup to stay this many cycles in state_init
init <= '1'; -- send reset signal to outside
rbus_waddr <= "000000"; -- select r0 in set 0
rbus_d <= conv_std_logic_vector(modelcode, 16); -- set modelcode on rbus
rbus_we <= '1'; -- pulse write
else
--
-- main state machine; setup some default values for signals that are applicable in each state
--
rbus_we <= '0'; -- default is not writing to the register file
fbus_we <= '0'; -- default is not writing to the fp11 register file
ifetch <= '0'; -- default is not an instruction fetch
ack_mmuabort <= '0'; -- default not acknowledging an mmu abort
ack_mmutrap <= '0'; -- default not acknowledging an mmu trap
illhalt <= '0'; -- no illegal halt
falu_pending_clear <= '0'; -- not clearing any pending fp11 interrupt flags
if yellow_stack_trap_trigger = '1' then -- do we have a pending yellow stack trap?
yellow_stack_trap <= '1'; -- signal to deal with it on the next pass through state_ifetch
end if;
--
-- aborts; these conditions abort the execution of instructions, no matter in which state the state machine is
--
-- the ir_csm check in here is really a dirty hack - it's to prevent state_csmi from changing r7 when an abort occurs in
-- the final memory reference. It's needed to pass zkdk - but, probably a more generic case exists for anything that changes
-- r7. The problem lies in what happens if r7 is changed, and subsequently an abort occurs - then r7 will be pushed, but
-- with the changed value, which most likely is incorrect - because the memory access was aborted.
-- It may make more sense to generically enable have_mmuimmediateabort, but, then 2.11BSD will not run - it needs the
-- decrement of a stack push to be reflected in the r6, because otherwise it will not grow a stack. Re. the ls -als problem.
if have_red = 1 and red_stack_trap_trigger = '1' then -- if the conditions for a red stack trap have tripped
red_stack_trap <= '1'; -- set flag
state <= state_rsv; -- start red trap sequence
elsif mmuabort = '1' and (have_mmuimmediateabort = 1 or ir_csm = '1') then -- signal from mmu that an access caused an abort. dealing with the abort here suppresses any actions taken by the state itself, re. code at end of state machine
state <= state_mmuabort; -- precursor state for mmu abort
ack_mmuabort <= '1'; -- set acknowledge flag to mmu core
elsif oddabort = '1' and (have_oddimmediateabort = 1 or ir_csm = '1') then -- odd abort signal, and need to deal with it and suppress the state machine actions?
trap_vector <= o"004"; -- set vector
state <= state_trap; -- do trap
else
--
-- state_init; this is the first state after a reset, both the hardware signal as well as the insn. This state will
-- set the init signal towards the 'bus', and stretch it a bit, to give slower things on the bus a bit of extra time
-- to reset in their turn. Since there are not really 'slower' things on the bus, this may not be necessary, but at
-- some point it did help in debugging.
--
case state is
when state_init =>
if initcycles = 0 then
state <= state_ifetch;
init <= '0';
else
init <= '1';
initcycles <= initcycles - 1;
end if;
--
-- state_ifetch; all things that need to happen before starting to decode a new instruction. Actually, this state
-- just sets up the memory to produce a new instruction; besides however there is a lot of logic that deduces
-- whether other things, such as handling interrupts need to be serviced before a new instruction can start.
--
-- the if-elsif statement is a priority encoder that determines the relative priority of interrupts.
--
when state_ifetch =>
rbus_cpu_mode <= pswmf(15 downto 14); -- set rbus to the current cpu mode
ir_wait <= '0';
if have_red = 1 then
red_stack_trap <= '0';
end if;
yellow_stack_trap_inhibit <= '0';
if ir_halt = '1' then
if run = '1' then -- mostly just to allow passing a halt in a test program
state <= state_ifetch;
ir_halt <= '0';
end if;
elsif npr = '1' then -- bus master request
state <= state_npg;
npg <= '1';
elsif mmutrap = '1' then -- mmu trap vector = 250
state <= state_mmutrap;
ack_mmutrap <= '1';
elsif yellow_stack_trap = '1' then
yellow_stack_trap <= '0';
yellow_stack_trap_inhibit <= '1';
trap_vector <= o"004"; -- yellow stack trap, vector = 004
state <= state_trap;
elsif falu_pending_fic = '1' then -- pending fic trap from fp11
state <= state_fptrap;
elsif falu_pending_fiu = '1' then -- pending fiu trap from fp11
state <= state_fptrap;
elsif falu_pending_fiv = '1' then -- pending fiv trap from fp11
state <= state_fptrap;
elsif falu_pending_divz = '1' then -- pending div by zero trap from fp11
state <= state_fptrap;
elsif pir_in(15) = '1' and unsigned(psw(7 downto 5)) < unsigned'("111") then
trap_vector <= o"240"; -- pirq, vector = 240
state <= state_trap;
elsif br7 = '1' and unsigned(psw(7 downto 5)) < unsigned'("111") then
state <= state_br7; -- external, level 7, vector determined by device
bg7 <= '1';
elsif pir_in(14) = '1' and unsigned(psw(7 downto 5)) < unsigned'("110") then
trap_vector <= o"240"; -- pirq, vector = 240
state <= state_trap;
elsif br6 = '1' and unsigned(psw(7 downto 5)) < unsigned'("110") then
state <= state_br6; -- external, level 6, vector determined by device
bg6 <= '1';
elsif pir_in(13) = '1' and unsigned(psw(7 downto 5)) < unsigned'("101") then
trap_vector <= o"240"; -- pirq, vector = 240
state <= state_trap;
elsif br5 = '1' and unsigned(psw(7 downto 5)) < unsigned'("101") then
state <= state_br5; -- external, level 5, vector determined by device
bg5 <= '1';
elsif pir_in(12) = '1' and unsigned(psw(7 downto 5)) < unsigned'("100") then
trap_vector <= o"240"; -- pirq, vector = 240
state <= state_trap;
elsif br4 = '1' and unsigned(psw(7 downto 5)) < unsigned'("100") then
state <= state_br4; -- external, level 4, vector determined by device
bg4 <= '1';
elsif pir_in(11) = '1' and unsigned(psw(7 downto 5)) < unsigned'("011") then
trap_vector <= o"240"; -- pirq, vector = 240
state <= state_trap;
elsif pir_in(10) = '1' and unsigned(psw(7 downto 5)) < unsigned'("010") then
trap_vector <= o"240"; -- pirq, vector = 240
state <= state_trap;
elsif pir_in(9) = '1' and unsigned(psw(7 downto 5)) < unsigned'("001") then
trap_vector <= o"240"; -- pirq, vector = 240
state <= state_trap;
elsif psw(4) = '1' and ir_rtt = '0' then
trap_vector <= o"014"; -- trace bit, vector = 014
state <= state_trap;
else
if ir_wait = '0' then -- if not in wait mode
state <= state_idecode; -- go process an instruction
ifetch <= '1'; -- set ifetch flag to signal instruction fetch to the outside world
else
ir_wait <= '1'; -- go into wait mode
end if;
sr1_srcd <= "00000"; -- setup mmu sr1 source part
sr1_dstd <= "00000"; -- setup mmu sr1 destination part
sr0_ic <= '1'; -- set mmu sr0 instruction complete flag
if modelcode = 44 -- fairly sure about this list, see kktb. Seems likely that at least 70 and J11 would also do this variant. However, not sure about F11 or other models
or modelcode = 45 or modelcode = 50 or modelcode = 55 -- and least sure of all about 45... but gamble is on this variant, seems 70 is most likely similar
or modelcode = 70
or modelcode = 73
or modelcode = 83
or modelcode = 84
or modelcode = 93
or modelcode = 94
then
sr2 <= r7; -- store address of instruction for mmu, sr2/mmr2
end if;
end if;
if have_pswimmediateupdate = 0 then -- some cpu models only effectuate the result of updates to the psw after the insn fetch following the update
if psw_delayedupdate_even = '1' then
psw(7 downto 5) <= psw_delayedupdate(7 downto 5); -- T bit can only be set with RTI/RTT instruction
if modelcode = 04 -- except for 11/04 etc
or modelcode = 05 or modelcode = 10
or modelcode = 15 or modelcode = 20
then
psw(4) <= psw_delayedupdate(4);
end if;
psw(3 downto 0) <= psw_delayedupdate(3 downto 0);
end if;
if psw_delayedupdate_odd = '1' then
psw(15 downto 8) <= psw_delayedupdate(15 downto 8);
rbus_cpu_mode <= psw_delayedupdate(15 downto 14); -- set rbus to the current cpu mode
end if;
psw_delayedupdate_even <= '0';
psw_delayedupdate_odd <= '0';
end if;
--
-- state_idecode; decode the instruction word and determine which path through the states will have to be initiated
--
--
-- first, set defaults for several status flags
--
when state_idecode =>
r7 <= r7p2; -- increment pc after instruction fetch
ir <= datain; -- store instruction word
ir_addr <= r7; -- store address of instruction
sr0_ic <= '0'; -- set instruction not complete in our part of sr0/mmr0
if modelcode = 34
or modelcode = 23 or modelcode = 24 -- fixme, verify this, but how?
then
sr2 <= r7; -- store address of instruction for mmu, sr2/mmr2
end if;
ir_fpmaf <= '0'; -- not a fp 4- or 8-byte memory access
ir_fpmai <= '0'; -- not a fp integer mode memory access
ir_sop <= '0'; -- current instruction is not single operand
ir_dop <= '0'; -- current instruction is not dual operand
ir_jmp <= '0'; -- current instruction is not jmp
ir_jsr <= '0'; -- current instruction is not jsr
ir_csm <= '0'; -- current instruction is not csm
ir_mfpi <= '0'; -- current instruction is not mfpi
ir_mfpd <= '0'; -- current instruction is not mfpd
ir_mtpi <= '0'; -- current instruction is not mtpi
ir_mtpd <= '0'; -- current instruction is not mtpd
ir_mtps <= '0'; -- current instruction is not mtps
ir_mfps <= '0'; -- current instruction is not mfps
ir_dopr <= '0'; -- current instruction is not dual operand register
ir_fpsop1 <= '0'; -- current instruction is not an fp single operand group 1 insn
ir_fpsop2 <= '0'; -- current instruction is not an fp single operand group 2 insn
ir_fpao <= '0'; -- current instruction is not an fp accumulator and operand insn
ir_facdst <= '0'; -- current instruction is not an fp accumulator and operand insn in cpu dst format
ir_facsrc <= '0'; -- current instruction is not an fp accumulator and operand insn in cpu src format
ir_facfdst <= '0'; -- current instruction is not an fp accumulator and operand insn in fp11 dst format
ir_facfsrc <= '0'; -- current instruction is not an fp accumulator and operand insn in fp11 src format
ir_mpr <= '0'; -- current instruction is not a multiprocessor instruction
ir_rtt <= '0'; -- current instruction is not rtt and no trace trap is being suppressed
fbus_fd <= fps(7); -- start on the assumption that access to the fp register set follows the fps fd flag
falu_pending_clear <= '1'; -- clear any leftover pending interrupt flags
state <= state_illegalop; -- set catch value in case we don't decode an insn
--
-- setup variables to classify which of several instruction groups the current instruction is, to make the decode logic easier to follow
--
-- sop - single operand insn
if datain(14 downto 9) = "0000101" -- single operand, word or byte (x05xxx)
or datain(14 downto 8) = "00001100" -- single operand, word or byte (x06xxx), first half of range
or datain(15 downto 6) = "0000000011" -- swab
or (datain(15 downto 6) = "0000110111" and have_sxt = 1) -- sxt
then
v_sop := '1';
else
v_sop := '0';
end if;
-- dop - double operand insn
if datain(14 downto 12) /= "000" and datain(14 downto 12) /= "111" then -- dop
v_dop := '1';
else
v_dop := '0';
end if;
-- jmp
if datain(15 downto 6) = "0000000001" then -- jmp
v_jmp := '1';
else
v_jmp := '0';
end if;
-- jsr
if datain(15 downto 9) = "0000100" then -- jsr
v_jsr := '1';
else
v_jsr := '0';
end if;
-- csm
if have_csm = 1 and datain(15 downto 6) = "0000111000" then -- csm
v_csm := '1';
else
v_csm := '0';
end if;
-- mfpi/mfpd/mtpi/mtpd
if have_mfp = 1 and datain(15 downto 6) = "0000110101" then -- mfpi
v_mfpi := '1';
else
v_mfpi := '0';
end if;
if have_mfp = 1 and datain(15 downto 6) = "1000110101" then -- mfpd
v_mfpd := '1';
else
v_mfpd := '0';
end if;
if have_mfp = 1 and datain(15 downto 6) = "0000110110" then -- mtpi
v_mtpi := '1';
else
v_mtpi := '0';
end if;
if have_mfp = 1 and datain(15 downto 6) = "1000110110" then -- mtpd
v_mtpd := '1';
else
v_mtpd := '0';
end if;
-- mtps/mfps
if have_mtps = 1 and datain(15 downto 6) = "1000110100" then -- mtps
v_mtps := '1';
else
v_mtps := '0';
end if;
if have_mtps = 1 and datain(15 downto 6) = "1000110111" then -- mfps
v_mfps := '1';
else
v_mfps := '0';
end if;
-- double operand, register - eis/xor
if (have_eis = 1 and datain(15 downto 11) = "01110") -- mul, div, ash, ashc
or (have_xor = 1 and datain(15 downto 9) = "0111100") then -- xor
v_dopr := '1';
else
v_dopr := '0';
end if;
-- multiprocessor insns - mpr
if have_mpr = 1 and datain(15 downto 7) = "000011101" then -- tstset/wrtlck
v_mpr := '1';
else
v_mpr := '0';
end if;
-- floating point insns - fpu, single op group 1 - those that dont have an ac as operand
if datain(15 downto 8) = "11110000"
and datain(7 downto 6) /= "00"
and have_fpu = 1
then -- fp11 single operand group 1: ldfps, stfps, stst
v_fpsop1 := '1';
else
v_fpsop1 := '0';
end if;
-- floating point insns - fpu, single op group 2 - those that have an ac as operand
if datain(15 downto 8) = "11110001"
and have_fpu = 1
then -- fp11 single operand group 2: clr(f/d), tst(f/d), abs(f/d), neg(f/d)
v_fpsop2 := '1';
else
v_fpsop2 := '0';
end if;
-- floating point insns - fpu, ac and operand group
if datain(15 downto 12) = "1111"
and datain(11 downto 9) /= "000"
and have_fpu = 1
then -- fp11 ac and operand group
v_fpao := '1';
else
v_fpao := '0';
end if;
--
-- setup signal copies of the variables just set, to be used in other states following idecode
--
if v_sop = '1' then
ir_sop <= '1';
end if;
if v_dop = '1' then
ir_dop <= '1';
end if;
if v_jmp = '1' then
ir_jmp <= '1';
end if;
if v_jsr = '1' then
ir_jsr <= '1';
end if;
if v_csm = '1' then
ir_csm <= '1';
end if;
if v_mfpi = '1' then
ir_mfpi <= '1';
end if;
if v_mfpd = '1' then
ir_mfpd <= '1';
end if;
if v_mtpi = '1' then
ir_mtpi <= '1';
end if;
if v_mtpd = '1' then
ir_mtpd <= '1';
end if;
if v_mtps = '1' then
ir_mtps <= '1';
end if;
if v_mfps = '1' then
ir_mfps <= '1';
end if;
if v_dopr = '1' then
ir_dopr <= '1';
end if;
if v_mpr = '1' then
ir_mpr <= '1';
end if;
-- with the floating point insns, here we also set flags that determine whether 2 or 4 (integer), or 4 or 8 (float/double) byte memory access is needed
if v_fpsop1 = '1' then
ir_fpsop1 <= '1';
end if;
if v_fpsop2 = '1' then
ir_fpsop2 <= '1';
ir_fpmaf <= '1';
end if;
if v_fpao = '1' then
ir_fpao <= '1';
ir_facdst <= '0';
ir_facsrc <= '0';
ir_facfdst <= '0';
ir_facfsrc <= '0';
if datain(11 downto 9) = "101" then -- stexp, stc(f|d)(i|l)
ir_facdst <= '1';
if datain(8) = '1' then -- stc(f|d)(i|l)
ir_fpmai <= '1'; -- needs 2 or 4 byte memory access
end if;
elsif datain(11 downto 8) = "1101" then -- ldexp
ir_facsrc <= '1';
elsif datain(11 downto 8) = "1110" then -- ldc(i|l)(f|d)
ir_facsrc <= '1';
ir_fpmai <= '1'; -- needs 2 or 4 byte memory access
elsif datain(11 downto 8) = "1000" then -- st(f|d)
ir_facfdst <= '1';
ir_fpmaf <= '1'; -- needs 4 or 8 byte memory access
elsif datain(11 downto 8) = "1100" then -- stc(f|d)
ir_facfdst <= '1';
ir_fpmaf <= '1'; -- needs 4 or 8 byte memory access
else -- if not any of the other special cases,
ir_facfsrc <= '1'; -- then it should be an fsrc format insn
ir_fpmaf <= '1'; -- needs 4 or 8 byte memory access
end if;
end if;
-- instruction decoder proper
if
v_sop = '1'
or v_dop = '1'
or v_jmp = '1'
or v_jsr = '1'
or v_csm = '1'
or v_mfpi = '1'
or v_mfpd = '1'
or v_mtpi = '1'
or v_mtpd = '1'
or v_mtps = '1'
or v_mfps = '1'
or v_dopr = '1'
or v_mpr = '1'
or v_fpsop1 = '1'
or v_fpsop2 = '1'
or v_fpao = '1'
then
case datain(5 downto 3) is
when "000" =>
psrcstate <= state_dst0;
when "001" =>
psrcstate <= state_dst1;
when "010" =>
psrcstate <= state_dst2;
when "011" =>
psrcstate <= state_dst3;
when "100" =>
psrcstate <= state_dst4;
when "101" =>
psrcstate <= state_dst5;
when "110" =>
psrcstate <= state_dst6;
when "111" =>
psrcstate <= state_dst7;
when others =>
null;
end case;
if datain(5 downto 3) = "000" then
pdststate <= state_store_alu_r;
else
pdststate <= state_store_alu_p;
end if;
if v_dop = '1' then
case datain(11 downto 9) is
when "000" =>
rbus_ix <= datain(8 downto 6);
state <= state_src0;
when "001" =>
rbus_ix <= datain(8 downto 6);
state <= state_src1;
when "010" =>
rbus_ix <= datain(8 downto 6);
state <= state_src2;
when "011" =>
rbus_ix <= datain(8 downto 6);
state <= state_src3;
when "100" =>
rbus_ix <= datain(8 downto 6);
state <= state_src4;
when "101" =>
rbus_ix <= datain(8 downto 6);
state <= state_src5;
when "110" =>
rbus_ix <= datain(8 downto 6);
state <= state_src6;
when "111" =>
rbus_ix <= datain(8 downto 6);
state <= state_src7;
when others =>
null;
end case;
else
case datain(5 downto 3) is
when "000" =>
if v_jmp = '1' then
state <= state_illegalop; -- jmp with mode 0 is illegal
elsif v_jsr = '1' then
state <= state_illegalop; -- jsr with mode 0 is illegal
elsif have_mfp = 1 and (v_mfpi = '1' or v_mfpd = '1') then
if datain(2 downto 0) = "110" then
rbus_cpu_mode <= psw(13 downto 12);
end if;
rbus_ix <= datain(2 downto 0);
state <= state_dst0;
elsif have_mfp = 1 and (v_mtpi = '1' or v_mtpd = '1') then -- if mode is 0, it's not very interesting to try and read the register
rbus_ix <= "110";
state <= state_mtp;
elsif have_mpr = 1 and v_mpr = '1' then
state <= state_illegalop; -- tstset/wrtlck mode 0 are illegal
elsif have_fpu = 1 and v_fpao = '1' then
if datain(11 downto 9) /= "101" -- stexp, stc(f/d)(i/l)
and datain(11 downto 8) /= "1101" -- ldexp
and datain(11 downto 8) /= "1110" -- ldc(i/l)(f/d)
then
if datain(2 downto 1) = "11" then -- ac6 and ac7 do not exist
fec <= "0010";
state <= state_fptrap;
else
if datain(11) & datain(9 downto 8) = "100" then
fbus_raddr <= '0' & datain(7 downto 6); -- fdst insn, need ac
else
fbus_raddr <= datain(2 downto 0); -- fsrc insn, need mode 0 fsrc ac
end if;
state <= state_fpao;
end if;
else
fbus_raddr <= '0' & datain(7 downto 6); -- ldexp, ldc(i/l)(f/d), stexp, stc(f/d)(i/l) get ac
rbus_ix <= datain(2 downto 0);
state <= state_dst0;
end if;
elsif have_fpu = 1 and v_fpsop2 = '1' then
if datain(2 downto 1) = "11" then -- ac6 and ac7 do not exist
fec <= "0010";
state <= state_fptrap;
else
fbus_raddr <= datain(2 downto 0); -- fsrc insn, need mode 0 fsrc ac
state <= state_fpso2;
end if;
else
rbus_ix <= datain(2 downto 0);
state <= state_dst0;
end if;
when "001" =>
state <= state_dst1;
rbus_ix <= datain(2 downto 0);
when "010" =>
state <= state_dst2;
rbus_ix <= datain(2 downto 0);
when "011" =>
state <= state_dst3;
rbus_ix <= datain(2 downto 0);
when "100" =>
state <= state_dst4;
rbus_ix <= datain(2 downto 0);
when "101" =>
state <= state_dst5;
rbus_ix <= datain(2 downto 0);
when "110" =>
state <= state_dst6;
rbus_ix <= datain(2 downto 0);
when "111" =>
state <= state_dst7;
rbus_ix <= datain(2 downto 0);
when others =>
null;
end case;
if v_sop = '1' then
if datain(5 downto 3) = "000" then
pdststate <= state_store_alu_r;
else
pdststate <= state_store_alu_p;
end if;
elsif v_jmp = '1' then
pdststate <= state_jmp;
elsif v_jsr = '1' then
pdststate <= state_jsr;
elsif v_csm = '1' then
pdststate <= state_csm;
elsif v_mfpi = '1' or v_mfpd = '1' then
pdststate <= state_mfp;
elsif v_mtpi = '1' or v_mtpd = '1' then
rbus_ix <= "110";
state <= state_mtp;
elsif have_mtps = 1 and v_mtps = '1' then
pdststate <= state_mtps;
elsif have_mtps = 1 and v_mfps = '1' then
if datain(5 downto 3) = "000" then
pdststate <= state_store_alu_r;
else
pdststate <= state_store_alu_p;
end if;
elsif v_dopr = '1' then
pdststate <= state_dopr;
elsif v_mpr = '1' then
if datain(6) = '0' then
pdststate <= state_tstset;
else
pdststate <= state_wrtlck;
end if;
elsif have_fpu = 1 and v_fpsop1 = '1' then
case datain(7 downto 6) is
when "01" => -- ldfps
pdststate <= state_ldfps;
when "10" => -- stfps
if datain(5 downto 3) = "000" then
pdststate <= state_store_alu_r;
else
pdststate <= state_store_alu_p;
end if;
when "11" => -- stst
if datain(5 downto 3) = "000" then
pdststate <= state_store_alu_r;
else
pdststate <= state_store_alu_p;
end if;
when others =>
null;
end case;
elsif have_fpu = 1 and v_fpsop2 = '1' then
pdststate <= state_fpso2; -- clr(f|d),tst(f|d),abs(f|d),neg(f|d)
elsif have_fpu = 1 and v_fpao = '1' then
pdststate <= state_fpao;
if datain(11 downto 8) = "1101" -- ldexp
or datain(11 downto 8) = "1010" -- stexp
or datain(11) & datain(9 downto 8) = "100" -- st(f|d), stc(f|d)(d|f)
or datain(11 downto 8) = "1011" -- stc(f|d)(i|l)
then
fbus_raddr <= '0' & datain(7 downto 6); -- needed for st(f|d), stc(f|d)(d|f), ldexp, stexp
end if;
else
pdststate <= state_illegalop;
end if;
end if;
end if;
if datain(14 downto 11) = "0000" then -- pc and ps change, excl. jsr, emt, trap
if datain(15) = '0' and datain(10 downto 8) = "000" then -- halt group, jmp
-- halt is a complicated case - it is handled differently by most models - it traps either to 4, 10, or to the console, or plainly halts
-- don't have a console yet - so the last two are simple. Still, the mode bit for the J11 came as a surprise - thought I had seen all variants.
if datain(7 downto 0) = "00000000" then -- halt
if pswmf(15 downto 14) /= "00"
and (modelcode = 73 or modelcode = 44 or modelcode = 45 or modelcode = 50 or modelcode = 55 or modelcode = 70 or modelcode = 84 or modelcode = 83 or modelcode = 93 or modelcode = 94)
then
illhalt <= '1';
trap_vector <= o"004";
state <= state_trap;
elsif pswmf(15 downto 14) /= "00"
and (modelcode = 23 or modelcode = 24 or modelcode = 34 or modelcode = 35 or modelcode = 40 or modelcode = 60)
then
illhalt <= '1';
trap_vector <= o"010";
state <= state_trap;
elsif modelcode = 3 or modelcode = 21 or modelcode = 4 or modelcode = 5 or modelcode = 10 or modelcode = 15 or modelcode = 20
then
ir_halt <= '1';
state <= state_ifetch;
elsif pswmf(15 downto 14) = "00" and cpu_kmillhalt = '1'
then
illhalt <= '1';
trap_vector <= o"004";
state <= state_trap;
elsif pswmf(15 downto 14) = "00"
then
ir_halt <= '1';
state <= state_ifetch;
else -- the default, if we do not know the model of the cpu, is to follow the rule of J11
illhalt <= '1';
trap_vector <= o"004";
state <= state_trap;
end if;
end if;
if datain(7 downto 0) = "00000001" then -- wait
if pswmf(15 downto 14) = "00" then -- if not in kernel mode, this insn is a noop
ir_wait <= '1'; -- setting this flag will cause ifetch not to switch into idecode until an interrupt has occurred
end if;
state <= state_ifetch; -- next state is ifetch
end if;
if datain(7 downto 0) = "00000010" then -- rti
state <= state_rti;
rbus_ix <= "110";
if modelcode = 4 -- these models do not have rtt, but allow rti to set the t bit
or modelcode = 5 or modelcode = 10
or modelcode = 15 or modelcode = 20
then
if psw(4) = '0' then
ir_rtt <= '1';
end if;
end if;
end if;
if datain(7 downto 0) = "00000011" then -- bpt
trap_vector <= o"014"; -- bpt, vector = 014
state <= state_trap;
end if;
if datain(7 downto 0) = "00000100" then -- iot
trap_vector <= o"020"; -- iot, vector = 020
state <= state_trap;
end if;
if datain(7 downto 0) = "00000101" then -- reset
if pswmf(15 downto 14) = "00" then
initcycles <= 7; -- not as long as the original specs say, but just a bit more than a single cycle
state <= state_init;
else
state <= state_ifetch; -- reset is a no-op when not in kernel mode
end if;
end if;
if have_rtt = 1 and datain(7 downto 0) = "00000110" then -- rtt
state <= state_rti;
rbus_ix <= "110";
ir_rtt <= '1';
end if;
--
-- mfpt : the opcode 000007 is used by some diagnostics, including at least fkaa, 11/34 basic inst tst, to trigger an illegal instruction trap
-- also, obviously it should work differently for the appropriate models
--
if datain(7 downto 0) = "00000111" then -- mfpt
if modelcode = 21 then
state <= state_ifetch;
rbus_waddr <= pswmf(15 downto 14) & pswmf(11) & "000";
rbus_d <= '0' & o"00004"; -- 4 = T-11
rbus_we <= '1';
end if;
if modelcode = 23 or modelcode = 24 then
state <= state_ifetch;
rbus_waddr <= pswmf(15 downto 14) & pswmf(11) & "000";
rbus_d <= '0' & o"00003"; -- 3 = F-11
rbus_we <= '1';
end if;
if modelcode = 44 then
state <= state_ifetch;
rbus_waddr <= pswmf(15 downto 14) & pswmf(11) & "000";
rbus_d <= '0' & o"00001"; -- 1 = 11/44
rbus_we <= '1';
end if;
if modelcode = 73
or modelcode = 53
or modelcode = 83
or modelcode = 84
or modelcode = 93
or modelcode = 94
then
state <= state_ifetch;
rbus_waddr <= pswmf(15 downto 14) & pswmf(11) & "000";
rbus_d <= '0' & o"00005"; -- 5 = J11
rbus_we <= '1';
end if;
end if;
if datain(7 downto 3) = "10000" then -- rts
state <= state_rts;
rbus_ix <= "110";
end if;
if have_spl = 1 and datain(7 downto 3) = "10011" then -- spl
if pswmf(15 downto 14) = "00" then
psw(7 downto 5) <= datain(2 downto 0);
end if;
state <= state_ifetch;
end if;
if datain(7 downto 4) = "1010" then -- clear cc
psw(3 downto 0) <= psw(3 downto 0) and (not datain(3 downto 0));
state <= state_ifetch;
end if;
if datain(7 downto 4) = "1011" then -- set cc
psw(3 downto 0) <= psw(3 downto 0) or datain(3 downto 0);
state <= state_ifetch;
end if;
else -- branch group
-- the branch insns used to have a separate state to actually do the branch, including calculating the effective address
-- this variant, however notationally inelegant, uses less logic, and less cycles as well.
state <= state_ifetch;
case datain(15) & datain(10 downto 8) is
when "0001" => -- br
r7 <= r7p2 + (datain(7) & datain(7) & datain(7) & datain(7) & datain(7) & datain(7) & datain(7) & datain(7 downto 0) & '0');
when "0010" => -- bne
if psw(2) = '0' then
r7 <= r7p2 + (datain(7) & datain(7) & datain(7) & datain(7) & datain(7) & datain(7) & datain(7) & datain(7 downto 0) & '0');
end if;
when "0011" => -- beq
if psw(2) = '1' then
r7 <= r7p2 + (datain(7) & datain(7) & datain(7) & datain(7) & datain(7) & datain(7) & datain(7) & datain(7 downto 0) & '0');
end if;
when "0100" => -- bge
if psw(3) = psw(1) then
r7 <= r7p2 + (datain(7) & datain(7) & datain(7) & datain(7) & datain(7) & datain(7) & datain(7) & datain(7 downto 0) & '0');
end if;
when "0101" => -- blt
if psw(3) /= psw(1) then
r7 <= r7p2 + (datain(7) & datain(7) & datain(7) & datain(7) & datain(7) & datain(7) & datain(7) & datain(7 downto 0) & '0');
end if;
when "0110" => -- bgt
if psw(2) = '0' and psw(3) = psw(1) then
r7 <= r7p2 + (datain(7) & datain(7) & datain(7) & datain(7) & datain(7) & datain(7) & datain(7) & datain(7 downto 0) & '0');
end if;
when "0111" => -- ble
if psw(2) = '1' or psw(3) /= psw(1) then
r7 <= r7p2 + (datain(7) & datain(7) & datain(7) & datain(7) & datain(7) & datain(7) & datain(7) & datain(7 downto 0) & '0');
end if;
when "1000" => -- bpl
if psw(3) = '0' then
r7 <= r7p2 + (datain(7) & datain(7) & datain(7) & datain(7) & datain(7) & datain(7) & datain(7) & datain(7 downto 0) & '0');
end if;
when "1001" => -- bmi
if psw(3) = '1' then
r7 <= r7p2 + (datain(7) & datain(7) & datain(7) & datain(7) & datain(7) & datain(7) & datain(7) & datain(7 downto 0) & '0');
end if;
when "1010" => -- bhi
if psw(2) = '0' and psw(0) = '0' then
r7 <= r7p2 + (datain(7) & datain(7) & datain(7) & datain(7) & datain(7) & datain(7) & datain(7) & datain(7 downto 0) & '0');
end if;
when "1011" => -- blos
if psw(2) = '1' or psw(0) = '1' then
r7 <= r7p2 + (datain(7) & datain(7) & datain(7) & datain(7) & datain(7) & datain(7) & datain(7) & datain(7 downto 0) & '0');
end if;
when "1100" => -- bvc
if psw(1) = '0' then
r7 <= r7p2 + (datain(7) & datain(7) & datain(7) & datain(7) & datain(7) & datain(7) & datain(7) & datain(7 downto 0) & '0');
end if;
when "1101" => -- bvs
if psw(1) = '1' then
r7 <= r7p2 + (datain(7) & datain(7) & datain(7) & datain(7) & datain(7) & datain(7) & datain(7) & datain(7 downto 0) & '0');
end if;
when "1110" => -- bhis
if psw(0) = '0' then
r7 <= r7p2 + (datain(7) & datain(7) & datain(7) & datain(7) & datain(7) & datain(7) & datain(7) & datain(7 downto 0) & '0');
end if;
when "1111" => -- blo
if psw(0) = '1' then
r7 <= r7p2 + (datain(7) & datain(7) & datain(7) & datain(7) & datain(7) & datain(7) & datain(7) & datain(7 downto 0) & '0');
end if;
when others =>
null;
end case;
end if;
end if;
if datain(15 downto 9) = "1000100" then -- trap, emt etc
if datain(8) = '0' then
trap_vector <= o"030"; -- emt, vector = 030
else
trap_vector <= o"034"; -- trap, vector = 034
end if;
state <= state_trap;
end if;
if have_sob = 1 and datain(15 downto 9) = "0111111" then -- sob
rbus_ix <= datain(8 downto 6);
state <= state_sob;
if have_sob_zkdjbug = 1 and (modelcode = 73 or modelcode = 83 or modelcode = 84 or modelcode = 93 or modelcode = 94) then
sob_slowdown <= 255;
end if;
end if;
if have_mark = 1 and datain(15 downto 6) = "0000110100" then -- mark
rbus_waddr <= pswmf(15 downto 14) & "0110";
rbus_d <= unsigned(r7p2) + unsigned(datain(5 downto 0) & '0');
rbus_we <= '1';
rbus_ix <= "101";
state <= state_mark;
end if;
if have_fpu = 1 and datain(15 downto 6) = "1111000000" then -- fp11 operate group
case datain(5 downto 0) is
when "000000" => -- cfcc
psw(3 downto 0) <= fps(3 downto 0);
state <= state_ifetch;
when "000001" => -- setf
fps(7) <= '0';
state <= state_ifetch;
when "000010" => -- seti
fps(6) <= '0';
state <= state_ifetch;
when "001001" => -- setd
fps(7) <= '1';
state <= state_ifetch;
when "001010" => -- setl
fps(6) <= '1';
state <= state_ifetch;
when others =>
if modelcode = 45 or modelcode = 50 or modelcode = 55 or modelcode = 70 then
if datain(5 downto 3) = "000" then
state <= state_ifetch; -- allow 45/55/70 specific insns ldub, ldsc, stao, mrs, stq0 not to cause a trap
else
fec <= "0010"; -- unknown insn, start trap seq
state <= state_fptrap;
end if;
else
fec <= "0010"; -- unknown insn, start trap seq
state <= state_fptrap;
end if;
end case;
end if;
--
-- illegal op : used for both catching unknown opcodes and for illegal operands to jmp and jsr, also tstset/wrtlck
--
when state_illegalop =>
--
-- vector for illegal operand, register mode jmp or jsr
-- manuals seem to incorrectly list what vector should be used; systems use either 004 or 010.
-- for instance, EK-DCJ11-UG-PRE_J11ug_Oct83.pdf pg. C-7 item 5
-- however, diagnostics reveal the following:
-- 11/34 - 004, source AC-8045D-MC_CFKABD0-1134-Traps-Tst_Apr77.pdf
-- 11/44 - 010, confirmed by running kkab
-- 11/45 - 010, source PDP1145_Handbook_1973.pdf, pg. 230
-- J11 - 010, source 0095_CZKDJB0_KDJ11.pdf, seq 166/K13
--
if have_fpu = 1 and ir(15 downto 12) = "1111" then
fec <= "0010";
state <= state_fptrap;
elsif ir_jmp = '1' or ir_jsr = '1' then
if modelcode = 34
or modelcode = 4 -- verified 04 behaviour by running gkab
then
trap_vector <= o"004";
else
trap_vector <= o"010";
end if;
state <= state_trap;
else
trap_vector <= o"010"; -- illegal op, vector = 010
state <= state_trap;
end if;
--
-- jmp : move dest addr as computed into r7
--
when state_jmp =>
r7 <= dest_addr;
state <= state_ifetch;
--
-- npg : non-processor grant, ie. allow the bus to another bus master while the npr signal is active
--
when state_npg =>
if npr = '0' then
state <= state_ifetch;
npg <= '0';
else
npg <= '1';
end if;
--
-- mmuabort : the mmu requests an abort of the current instruction, potentially halfway trough an instruction
--
when state_mmuabort =>
if have_psw1512 = 1 and mmuabort = '0' then
ack_mmuabort <= '0';
trap_vector <= o"250"; -- mmu, vector = 250
state <= state_trap;
end if;
--
-- mmutrap : the mmu has requested a trap after the current instruction has finished; this trap will now be initiated
--
when state_mmutrap =>
if have_psw1512 = 1 and mmutrap = '0' then
ack_mmutrap <= '0';
trap_vector <= o"250"; -- mmu, vector = 250
state <= state_trap;
end if;
-- bus request aka interrupt, prio level 7; handle br7/bg7 signals and initiate trap
when state_br7 =>
if br7 = '0' then
bg7 <= '0';
trap_vector <= int_vector7;
state <= state_trap;
if modelcode = 45 or modelcode = 50 or modelcode = 55
or modelcode = 70 then
sr2 <= "0000000" & int_vector7; -- set trap vector in sr2
sr0_ic <= '0'; -- make sure to flag instruction not complete
end if;
end if;
-- bus request, prio level 6; handle br6/bg6 signals and initiate trap
when state_br6 =>
if br6 = '0' then
bg6 <= '0';
trap_vector <= int_vector6;
state <= state_trap;
if modelcode = 45 or modelcode = 50 or modelcode = 55
or modelcode = 70 then
sr2 <= "0000000" & int_vector6; -- set trap vector in sr2
sr0_ic <= '0'; -- make sure to flag instruction not complete
end if;
end if;
-- bus request, prio level 5; handle br5/bg5 signals and initiate trap
when state_br5 =>
if br5 = '0' then
bg5 <= '0';
trap_vector <= int_vector5;
state <= state_trap;
if modelcode = 45 or modelcode = 50 or modelcode = 55
or modelcode = 70 then
sr2 <= "0000000" & int_vector5; -- set trap vector in sr2
sr0_ic <= '0'; -- make sure to flag instruction not complete
end if;
end if;
-- bus request, prio level 4; handle br4/bg4 signals and initiate trap
when state_br4 =>
if br4 = '0' then
bg4 <= '0';
trap_vector <= int_vector4;
state <= state_trap;
if modelcode = 45 or modelcode = 50 or modelcode = 55
or modelcode = 70 then
sr2 <= "0000000" & int_vector4; -- set trap vector in sr2
sr0_ic <= '0'; -- make sure to flag instruction not complete
end if;
end if;
-- floating point error trap : precursor state handles fid bit in fps and contents of fea, and pending conditions signalled by the floating point alu
when state_fptrap =>
if falu_pending_fic = '1' then -- note the order... if more than one bit is set, the order of precedence is v, u, c
fec <= "0110";
end if;
if falu_pending_fiu = '1' then
fec <= "1010";
end if;
if falu_pending_fiv = '1' then
fec <= "1000";
end if;
if falu_pending_divz = '1' then
fec <= "0100";
end if;
fea <= ir_addr;
fps(15) <= '1';
if fps(14) = '0' then
trap_vector <= o"244"; -- floating point trap, vector = 244
state <= state_trap;
else -- wait for pending interrupt flags to clear before continuing
if falu_pending_fic = '0' and falu_pending_fiu = '0' and falu_pending_fiv = '0' and falu_pending_divz = '0' then
state <= state_ifetch;
end if;
end if;
falu_pending_clear <= '1';
--
-- rsv: red stack trap
-- implemented by setting the kernel sp to 4, and then starting a trap
-- the trap states will then decrement the sp, and save psw and r7 in
-- the right locations.
-- this approach is not necessarily correct, but passes czkdjb0
-- and it is also as described in EK-KDJ1B-UG_KDJ11-B_Nov86.pdf
-- in chapter 1.3.2, page 1-10
-- this takes some extra attention when sequencing through the
-- trap code to select kernel sp, though. Need to ignore whatever
-- is set in loc. 6
--
-- some extra explanation is probably needed for the copying of
-- psw from temp_psw. The reason is as follows: a red trap by
-- definition is a result from an earlier trap gone wrong. In the
-- first step of a normal trap, the psw is copied into temp_psw.
-- State_rsv restores that original psw into the real psw - then
-- starts a new trap.
--
when state_rsv =>
if have_red = 1 then
psw <= temp_psw;
rbus_waddr <= "00" & "0110";
rbus_d <= x"0004";
rbus_we <= '1';
trap_vector <= o"004"; -- red stack trap, vector = 004
state <= state_trap;
end if;
-- trap: start a trap sequence, trap through trapf
when state_trap =>
temp_psw <= psw;
psw(15 downto 14) <= "00"; -- initial, we'll load the real mode to select the correct stack by in the next step
psw(13 downto 12) <= pswmf(15 downto 14);
rbus_cpu_mode <= "00"; -- force rbus cpu mode to 00 - this is output to the mmu to select the par/pdr set
state <= state_trapa;
when state_trapa =>
rbus_ix <= "110";
if have_red = 1 and red_stack_trap = '1' then
rbus_cpu_mode <= "00";
else
rbus_cpu_mode <= datain(15 downto 14);
end if;
psw(15 downto 14) <= datain(15 downto 14);
psw(11 downto 0) <= datain(11 downto 0);
state <= state_trapb;
when state_trapb =>
state <= state_trapc;
when state_trapc =>
if have_red = 1 and red_stack_trap = '1' then
rbus_waddr <= "00" & "0110";
else
rbus_waddr <= pswmf(15 downto 14) & "0110";
end if;
rbus_d <= rbus_data_m2;
rbus_we <= '1';
state <= state_trapw;
when state_trapw =>
state <= state_trapd;
when state_trapd =>
if have_red = 1 and red_stack_trap = '1' then
rbus_waddr <= "00" & "0110";
else
rbus_waddr <= pswmf(15 downto 14) & "0110";
end if;
rbus_d <= rbus_data_m2;
rbus_we <= '1';
state <= state_trape;
when state_trape =>
rbus_cpu_mode <= "00"; -- force rbus cpu mode to 00 - this is output to the mmu to select the par/pdr set
state <= state_trapf;
when state_trapf =>
r7 <= datain;
state <= state_ifetch;
-- rti: start a rti sequence, rti through rtib
when state_rti =>
state <= state_rtia;
rbus_waddr <= pswmf(15 downto 14) & "0110";
rbus_d <= rbus_data_p2;
rbus_we <= '1';
when state_rtia =>
state <= state_rtib;
r7 <= datain;
when state_rtib =>
state <= state_ifetch;
rbus_waddr <= pswmf(15 downto 14) & "0110";
rbus_d <= rbus_data_p2;
rbus_we <= '1';
if modelcode = 4 then -- FIXME, probably other models as well - 5, 10, 15, 20? 04 behaviour tested with gkab
psw_delayedupdate <= datain;
psw_delayedupdate_even <= '1';
psw_delayedupdate_odd <= '1';
else
psw(4 downto 0) <= datain(4 downto 0);
if pswmf(15 downto 14) = "00" then
psw(7 downto 5) <= datain(7 downto 5);
end if;
psw(10 downto 8) <= datain(10 downto 8);
if pswmf(15 downto 14) = "00" then
psw(15 downto 11) <= datain(15 downto 11);
else
psw(15 downto 11) <= datain(15 downto 11) or pswmf(15 downto 11);
end if;
end if;
-- csm : process csm insn
when state_csm =>
if have_csm = 1 and sr3csmenable = '1' and psw(15 downto 14) /= "00" then
temp_psw(15 downto 4) <= psw(15 downto 4);
temp_psw(3 downto 0) <= "0000";
psw(15 downto 14) <= "01";
psw(13 downto 12) <= psw(15 downto 14);
psw(4) <= '0';
rbus_ix <= "110";
rbus_cpu_mode <= psw(15 downto 14);
state <= state_csma;
else
state <= state_illegalop;
end if;
when state_csma =>
rbus_waddr <= "01" & "0110"; -- address super sp
rbus_d <= rbus_data;
rbus_we <= '1';
state <= state_csmb;
when state_csmb =>
rbus_cpu_mode <= "01";
state <= state_csmc;
when state_csmc => -- push temp_psw
rbus_waddr <= "01" & "0110";
rbus_d <= rbus_data_m2;
rbus_we <= '1';
state <= state_csmd;
when state_csmd =>
state <= state_csme;
when state_csme => -- push pc
rbus_waddr <= "01" & "0110";
rbus_d <= rbus_data_m2;
rbus_we <= '1';
state <= state_csmf;
when state_csmf =>
state <= state_csmg;
when state_csmg => -- push alu_output
rbus_waddr <= "01" & "0110";
rbus_d <= rbus_data_m2;
rbus_we <= '1';
state <= state_csmh;
when state_csmh =>
trap_vector <= o"010"; -- csm loads r7 from vector = 010, but from supervisor I-space
state <= state_csmi;
when state_csmi =>
r7 <= datain;
state <= state_ifetch;
-- sob: deal with sob instruction
when state_sob =>
if have_sob_zkdjbug = 1 and (modelcode = 73 or modelcode = 83 or modelcode = 84 or modelcode = 93 or modelcode = 94) then
if sob_slowdown = 0 then
rbus_waddr <= pswmf(15 downto 14) & pswmf(11) & ir(8 downto 6);
rbus_d <= rbus_data_m1;
rbus_we <= '1';
if rbus_data_m1 = "0000000000000000" then
state <= state_ifetch;
else
r7 <= r7 - (ir(5 downto 0) & '0');
state <= state_ifetch;
end if;
else
sob_slowdown <= sob_slowdown - 1;
end if;
else
rbus_waddr <= pswmf(15 downto 14) & pswmf(11) & ir(8 downto 6);
rbus_d <= rbus_data_m1;
rbus_we <= '1';
if rbus_data_m1 = "0000000000000000" then
state <= state_ifetch;
else
r7 <= r7 - (ir(5 downto 0) & '0');
state <= state_ifetch;
end if;
end if;
-- move from previous i/d
when state_mfp =>
rbus_ix <= "110";
state <= state_mfpa;
when state_mfpa =>
dest_addr <= addr;
state <= state_store_alu_p;
sr1_srcd <= sr1_m2; -- it is the dest, actually - but that field is already used
rbus_waddr <= psw(15 downto 14) & '0' & "110";
rbus_d <= rbus_data_m2;
rbus_we <= '1';
-- move to previous i/d
when state_mtp =>
sr1_srcd <= sr1_p2;
rbus_waddr <= psw(15 downto 14) & '0' & "110";
rbus_d <= rbus_data_p2;
rbus_we <= '1';
state <= state_mtpa;
when state_mtpa =>
alus_input <= datain;
rbus_ix <= ir(2 downto 0);
state <= psrcstate;
-- mtps insn - move to ps
when state_mtps =>
if have_mtps = 1 then
if psw(15 downto 14) = "00" then
psw(7 downto 5) <= alu_output(7 downto 5);
psw(3 downto 0) <= alu_output(3 downto 0);
else
psw(3 downto 0) <= alu_output(3 downto 0);
end if;
state <= state_ifetch;
end if;
-- double operand,register instruction states dopr through doprb
-- these are for the EIS instruction set, ie mul, div, ash, ashc, xor
-- dopr is a precursor state, used to pick up the second operand from
-- the register file
when state_dopr =>
rbus_ix <= ir(8 downto 6);
state <= state_dopra;
-- dopra: setup the eis_sequencer to handle microstates for the eis alu
-- and dispatch to the states needed for each insn; also setup to read
-- ternary operand from the register file
when state_dopra =>
alus_input <= rbus_data;
rbus_ix <= ir(8 downto 7) & '1';
if ir(11 downto 9) = "000" then
eis_sequencer <= "11111";
state <= state_mul;
elsif ir(11 downto 9) = "010" then
eis_sequencer <= "11111";
state <= state_ash;
elsif ir(11 downto 9) = "100" then
state <= state_xor;
else
state <= state_doprb;
end if;
-- doprb: read ternary operand from the rbus, setup the
-- eis_sequencer for div and ashc
when state_doprb =>
alut_input <= rbus_data;
if ir (11 downto 9) = "001" then
if ir(6) = '1' then -- illegal, R must be even acc. EK-KDJ1B-UG_KDJ11-B_Nov86.pdf, pg. 9-31, and PDP1145_Handbook_1973.pdf, pg. 71
state <= state_ifetch; -- FIXME, does it make sense to go back to ifetch from here if the ir was illegal?
psw(3 downto 0) <= "0010"; -- not sure if this makes sense, but CZKDJB0 won't pass without
else
eis_sequencer <= "10000";
state <= state_div;
end if;
elsif ir(11 downto 9) = "011" then
eis_sequencer <= "11111";
state <= state_ashc;
else
state <= state_illegalop; -- should not be possible
end if;
-- mul through mulb: handle mul insn
when state_mul =>
if eis_sequencer = "00001" then
state <= state_mula;
end if;
eis_sequencer <= eis_sequencer + 1;
when state_mula =>
if ir(8 downto 6) /= "111" then
rbus_waddr <= pswmf(15 downto 14) & pswmf(11) & ir(8 downto 6);
rbus_d <= eis_output;
rbus_we <= '1';
else
r7 <= eis_output;
end if;
state <= state_mulb;
when state_mulb =>
if ir(8 downto 7) /= "11" then
rbus_waddr <= pswmf(15 downto 14) & pswmf(11) & ir(8 downto 7) & '1';
rbus_d <= eis_output32;
rbus_we <= '1';
else
r7 <= eis_output32;
end if;
psw(3 downto 0) <= eis_psw;
state <= state_ifetch;
-- div through divb: handle div insn
when state_div =>
if eis_sequencer = "11111" then
state <= state_diva;
end if;
eis_sequencer <= eis_sequencer - 1;
when state_diva =>
if eis_psw(1 downto 0) = "00" then
if ir(8 downto 6) /= "111" then
rbus_waddr <= pswmf(15 downto 14) & pswmf(11) & ir(8 downto 6);
rbus_d <= eis_output;
rbus_we <= '1';
else
r7 <= eis_output;
end if;
end if;
state <= state_divb;
when state_divb =>
if eis_psw(1 downto 0) = "00" then
if ir(8 downto 7) /= "11" then
rbus_waddr <= pswmf(15 downto 14) & pswmf(11) & ir(8 downto 7) & '1';
rbus_d <= eis_output32;
rbus_we <= '1';
else
r7 <= eis_output32;
end if;
end if;
psw(3 downto 0) <= eis_psw;
state <= state_ifetch;
-- ash through ashb: handle ash insn
when state_ash =>
if eis_sequencer = "11111" then
eis_sequencer <= eis_sequencer + 1;
else
if eis_flag2 = '1' then
state <= state_ashb;
end if;
end if;
when state_ashb =>
if ir(8 downto 6) /= "111" then
rbus_waddr <= pswmf(15 downto 14) & pswmf(11) & ir(8 downto 6);
rbus_d <= eis_output;
rbus_we <= '1';
else
r7 <= eis_output;
end if;
psw(3 downto 0) <= eis_psw;
state <= state_ifetch;
-- ashc through ashe: handle ashc insn
when state_ashc =>
if eis_sequencer = "11111" then
eis_sequencer <= eis_sequencer + 1;
else
if eis_flag2 = '1' then
state <= state_ashd;
end if;
end if;
when state_ashd =>
if ir(8 downto 6) /= "111" then
rbus_waddr <= pswmf(15 downto 14) & pswmf(11) & ir(8 downto 6);
rbus_d <= eis_output;
rbus_we <= '1';
else
r7 <= eis_output;
end if;
state <= state_ashe;
when state_ashe =>
if ir(8 downto 7) /= "11" then
rbus_waddr <= pswmf(15 downto 14) & pswmf(11) & ir(8 downto 7) & '1';
rbus_d <= eis_output32;
rbus_we <= '1';
else
r7 <= eis_output32;
end if;
psw(3 downto 0) <= eis_psw;
state <= state_ifetch;
-- xor: dispatch to state that stores result
when state_xor =>
if ir(5 downto 3) = "000" then
state <= state_store_alu_r;
else
state <= state_store_alu_p;
end if;
-- ldfps - load fpu state
when state_ldfps =>
fps <= alu_output;
state <= state_ifetch;
-- stst - store fpu fec and fea
when state_stststore =>
state <= state_ifetch;
-- dispatch insn in the fpso2 group - unless the insn is a clr(f|d), go into the
-- states that read an fp src operand
when state_fpso2 =>
addr_indirect <= dest_addr;
if ir(5 downto 3) /= "000" then
if ir(7 downto 6) = "00" then -- clr(f|d)
state <= state_fprun; -- don't need to read for clear
else
state <= state_fpr1;
end if;
else
falu_input <= fbus_o; -- fbus read already done in ifetch for mode 0
state <= state_fprun;
end if;
-- dispatch insn groups for the fp acc and operand format, in
-- all forms - fsrc, fsdt, src, dst, as signalled by the main
-- state machine - and cycle into the appropriate state to
-- handle the core accesses that are required to load the
-- operands, either in f|d, or i|l format.
when state_fpao =>
if ir(5 downto 3) /= "000" then
addr_indirect <= dest_addr;
if ir_facfsrc = '1' then
fbus_raddr <= '0' & ir(7 downto 6);
state <= state_fpr1;
elsif ir_facfdst = '1' then
falu_input <= fbus_o;
state <= state_fprun;
elsif ir_facdst = '1' then
falu_input <= fbus_o;
state <= state_fprun;
elsif ir_facsrc = '1' then
falu_input <= fbus_o;
state <= state_fpir1;
else
-- FIXME, go into some cpu error state?
end if;
else -- mode 0, so input from register!!!
if ir_facfsrc = '1' then
falu_input <= fbus_o;
fbus_raddr <= '0' & ir(7 downto 6);
state <= state_fprun;
elsif ir_facfdst = '1' then
falu_input <= fbus_o;
state <= state_fprun;
elsif ir_facdst = '1' then
falu_input <= fbus_o;
state <= state_fprun;
elsif ir_facsrc = '1' then
if ir(8) = '1' then -- ldexp
falu_input <= fbus_o;
falus_input(55 downto 40) <= rbus_data;
else -- ldc(i|l)(f|d)
falu_input(55 downto 40) <= "0000000000000000";
falu_input(39 downto 24) <= rbus_data;
falu_input(23 downto 0) <= "000000000000000000000000";
end if;
state <= state_fprun; -- FIXME, what about long data?
end if;
end if;
when state_fpir1 =>
if ir(8) = '1' then -- state is reachable only for ldexp and ldc(i|l)(f|d); ir(8) = 1 means ldexp
state <= state_fprun; -- ldexp
falus_input(55 downto 40) <= datain; -- FIXME, it does not really make sense to put the input value here?
else
falu_input(23 downto 0) <= "000000000000000000000000";
if fps(6) = '1' and ir(5 downto 0) /= "010111" then -- ldc(i|l)(f|d) mode 2, reg 7 : then only 1 word to be read
falu_input(55 downto 40) <= datain;
addr_indirect <= addr_indirect + 2;
state <= state_fpir2;
else
falu_input(55 downto 40) <= "0000000000000000";
falu_input(39 downto 24) <= datain;
state <= state_fprun;
end if;
end if;
when state_fpir2 =>
falu_input(39 downto 24) <= datain;
state <= state_fprun;
when state_fpr1 =>
if datain(15 downto 7) = "100000000" and fps(11) = '1' and fps(14) = '0' then -- do we need to trigger the fiuv trap for -0, undefined variable?
state <= state_fptrap; -- cause trap
fps(15) <= '1'; -- set error flag
fec <= "1100"; -- fiuv code
else
if datain(15 downto 7) = "100000000" and fps(11) = '1' then -- if interrupts are disabled, we still signal the error... FIXME, is this required at all?
fps(15) <= '1'; -- set error flag
fec <= "1100"; -- fiuv code
end if;
falu_input(63 downto 48) <= datain;
addr_indirect <= addr_indirect + 2;
if ir(5 downto 0) = "010111" then -- mode 2, reg 7 : then only 1 word to be loaded
falu_input(47 downto 0) <= "000000000000000000000000000000000000000000000000";
state <= state_fprun;
else
state <= state_fpr2;
end if;
end if;
when state_fpr2 =>
falu_input(47 downto 32) <= datain;
if fps(7) = '1' -- if mode is d
or (fps(7) = '0' and ir(11 downto 8) = "1111") -- or if mode is f, and the insn is ldcfd
then -- then we need to read the next two words
state <= state_fpr3;
addr_indirect <= addr_indirect + 2;
else
falu_input(31 downto 0) <= "00000000000000000000000000000000"; -- if mode is f, insn is not ldcfd, zero out the low 32 bits of the input
state <= state_fprun;
end if;
when state_fpr3 =>
falu_input(31 downto 16) <= datain;
addr_indirect <= addr_indirect + 2;
state <= state_fpr4;
when state_fpr4 =>
falu_input(15 downto 0) <= datain;
state <= state_fprun;
when state_fpwr =>
fbus_d <= falu_output;
fps(4) <= '0'; -- this appears to be needed to pass zkdl; always setting the bit to zero makes one of the other tests complain.
fps(3 downto 0) <= falu_fps;
fbus_waddr <= '0' & ir(7 downto 6);
fbus_we <= '1';
state <= state_ifetch;
if ir(11 downto 8) = "0011" and ir(6) = '0' then -- mod with even ac, need to store ac+1
state <= state_fpwr1;
end if;
when state_fpwr1 =>
state <= state_fpwr2;
when state_fpwr2 =>
fbus_d <= falu_output2;
fbus_waddr <= '0' & ir(7) & '1';
fbus_we <= '1';
state <= state_ifetch;
when state_fpd0 =>
fps(4) <= '0'; -- this appears to be needed to pass zkdl; always setting the bit to zero makes one of the other tests complain.
fps(3 downto 0) <= falu_fps;
if ir_fpsop2 = '1' and ir(7 downto 6) = "01" then -- tst(f/d)
state <= state_ifetch;
elsif ir(2 downto 1) /= "11" then
fbus_d <= falu_output;
fbus_waddr <= ir(2 downto 0);
fbus_we <= '1';
end if;
state <= state_ifetch;
when state_fpiwr =>
if ir(2 downto 0) /= "111" then
rbus_waddr <= pswmf(15 downto 14) & pswmf(11) & ir(2 downto 0);
rbus_d <= falu_output(63 downto 48);
rbus_we <= '1';
else
r7 <= falu_output(63 downto 48); -- FIXME, check what real pdp's do?
end if;
fps(4) <= '0'; -- this appears to be needed to pass zkdl; always setting the bit to zero makes one of the other tests complain.
fps(3 downto 0) <= falu_fps;
psw(3 downto 0) <= falu_fps;
state <= state_ifetch;
when state_fpiww =>
addr_indirect <= dest_addr;
fps(4) <= '0'; -- this appears to be needed to pass zkdl; always setting the bit to zero makes one of the other tests complain.
fps(3 downto 0) <= falu_fps;
psw(3 downto 0) <= falu_fps;
state <= state_fpiw1;
when state_fpiw1 =>
if ir(5 downto 0) = "010111" -- stc(f|d)(i|l) mode 2, reg 7 : then only 1 word to be written
or fps(6) = '0' -- stc(f|d)(i|l), short integer mode
or ir(11 downto 8) = "1010" -- stexp insn
then
state <= state_ifetch;
else
addr_indirect <= addr_indirect + 2;
state <= state_fpiw2;
end if;
when state_fpiw2 =>
state <= state_ifetch;
when state_fpww =>
addr_indirect <= dest_addr;
fps(4) <= '0'; -- this appears to be needed to pass zkdl; always setting the bit to zero makes one of the other tests complain.
fps(3 downto 0) <= falu_fps;
if ir_fpsop2 = '1' and ir(7 downto 6) = "01" then -- tst(f/d)
state <= state_ifetch;
else
state <= state_fpw1;
end if;
when state_fpw1 =>
if ir(5 downto 0) = "010111" then -- mode 2, reg 7 : then only 1 word to be written
state <= state_ifetch;
else
addr_indirect <= addr_indirect + 2;
state <= state_fpw2;
end if;
when state_fpw2 =>
if (fps(7) = '1' and ir(11 downto 8) /= "1100") -- reverse sense of fps D bit when insn is stc(f|d)(d|f)
or (fps(7) = '0' and ir(11 downto 8) = "1100")
then
state <= state_fpw3;
addr_indirect <= addr_indirect + 2;
else
state <= state_ifetch;
end if;
when state_fpw3 =>
addr_indirect <= addr_indirect + 2;
state <= state_fpw4;
when state_fpw4 =>
state <= state_ifetch;
when state_fprun =>
if ir_fpao = '1' then
if ir_facfsrc = '1' then
falus_input <= fbus_o;
end if;
state <= state_fprunao;
falu_load <= '1';
falu_state <= 0;
elsif ir_fpsop2 = '1' then
if ir(5 downto 3) = "000" then
state <= state_fpd0;
else
state <= state_fpww;
end if;
else
state <= state_ifetch; -- FIXME, needed?
end if;
when state_fprunao =>
falu_state <= falu_state + 1;
falu_load <= '0';
if falu_state > 160 then -- FIXME, this may prevent hangs. Why?
state <= state_ifetch; -- FIXME, error!
end if;
if falu_done = '1' then
falu_state <= 0;
case ir(11 downto 8) is
when "1000" => -- st(f|d)
if ir(5 downto 3) = "000" then
state <= state_fpd0;
else
state <= state_fpww;
end if;
when "1010" => -- stexp
if ir(5 downto 3) = "000" then
state <= state_fpiwr;
else
state <= state_fpiww;
end if;
when "1011" => -- stc(f|d)(i|l)
if ir(5 downto 3) = "000" then
state <= state_fpiwr;
else
state <= state_fpiww;
end if;
when "1100" => -- stc(f|d)(d|f)
fbus_fd <= '1'; -- enable full access to fp register bank
if ir(5 downto 3) = "000" then
state <= state_fpd0;
else
state <= state_fpww;
end if;
when "1111" => -- ldc(d|f)(f|d)
fbus_fd <= '1'; -- enable full access to fp register bank
state <= state_fpwr;
when others =>
state <= state_fpwr;
end case;
end if;
when state_tstset =>
rbus_waddr <= pswmf(15 downto 14) & pswmf(11) & "000";
rbus_d <= alu_input;
rbus_we <= '1';
state <= state_store_alu_p;
when state_wrtlck =>
rbus_ix <= "000";
state <= state_wrtlcka;
when state_wrtlcka =>
alu_input <= rbus_data;
state <= state_store_alu_p;
when state_mark =>
r7 <= rbus_data;
rbus_ix <= "110";
state <= state_marka;
when state_marka =>
rbus_waddr <= pswmf(15 downto 14) & pswmf(11) & "110";
rbus_d <= rbus_data_p2;
rbus_we <= '1';
state <= state_markb;
when state_markb =>
rbus_waddr <= pswmf(15 downto 14) & pswmf(11) & "101";
rbus_d <= datain;
rbus_we <= '1';
state <= state_ifetch;
when state_jsr =>
rbus_ix <= "110";
state <= state_jsra;
when state_jsra =>
addr_indirect <= rbus_data_m2;
rbus_waddr <= pswmf(15 downto 14) & "0110";
rbus_d <= rbus_data_m2;
rbus_we <= '1';
sr1_srcd <= sr1_m2;
rbus_ix <= ir(8 downto 6);
state <= state_jsrb;
when state_jsrb =>
state <= state_jsrc;
when state_jsrc =>
if ir(8 downto 6) /= "111" then
rbus_waddr <= pswmf(15 downto 14) & pswmf(11) & ir(8 downto 6);
rbus_d <= r7;
rbus_we <= '1';
end if;
r7 <= dest_addr;
state <= state_ifetch;
when state_rts =>
addr_indirect <= rbus_data;
if ir(2 downto 0) /= "110" then -- the r6 special case; it is not really necessary to increment sp here, since it will be loaded in the next step. Does not harm either.
rbus_waddr <= pswmf(15 downto 14) & "0110";
rbus_d <= rbus_data_p2;
rbus_we <= '1';
-- sr1_dstd <= sr1_p2; -- simh doesn't
end if;
rbus_ix <= ir(2 downto 0);
state <= state_rtsa;
when state_rtsa =>
if ir(2 downto 0) /= "111" then
r7 <= rbus_data;
rbus_waddr <= pswmf(15 downto 14) & pswmf(11) & ir(2 downto 0);
rbus_d <= datain;
rbus_we <= '1';
else
r7 <= datain;
end if;
state <= state_ifetch;
when state_dst0 =>
alu_input <= rbus_data;
state <= pdststate;
rbus_cpu_mode <= pswmf(15 downto 14); -- may have been set temporarily to handle mode 0 r6 for mfp(i|d)
when state_src0 =>
-- handle issue 3 in programming differences list
if ir_dop = '1' and ir(8 downto 6) = "111"
and (ir(5 downto 4) = "11")
and (
modelcode = 15 or modelcode = 20 or modelcode = 35 or modelcode = 40
or modelcode = 53
or modelcode = 73 or modelcode = 83 or modelcode = 84 or modelcode = 93 or modelcode = 94
)
then
alus_input <= rbus_data_p2;
state <= psrcstate;
rbus_ix <= ir(2 downto 0);
else
alus_input <= rbus_data;
state <= psrcstate;
rbus_ix <= ir(2 downto 0);
end if;
when state_dst1 =>
dest_addr <= addr;
alu_input <= datain;
state <= pdststate;
when state_src1 =>
alus_input <= datain;
state <= psrcstate;
rbus_ix <= ir(2 downto 0);
when state_dst2 =>
dest_addr <= addr;
alu_input <= datain;
state <= pdststate;
sr1_dstd <= sr1_pv;
if ir(2 downto 0) /= "111" then
rbus_waddr <= pswmf(15 downto 14) & pswmf(11) & ir(2 downto 0);
rbus_d <= rbus_data_pv;
rbus_we <= '1';
else
r7 <= rbus_data_p2;
end if;
when state_src2 =>
alus_input <= datain;
if ir_dop = '1' and ir(8 downto 6) = ir(2 downto 0) and ir(2 downto 0) /= "111" then
state <= state_src2w;
else
state <= psrcstate;
end if;
rbus_ix <= ir(2 downto 0);
sr1_srcd <= sr1_pv;
if ir(8 downto 6) /= "111" then
rbus_waddr <= pswmf(15 downto 14) & pswmf(11) & ir(8 downto 6);
rbus_d <= rbus_data_pv;
rbus_we <= '1';
else
r7 <= rbus_data_p2;
end if;
when state_src2w =>
state <= psrcstate;
when state_dst3 =>
addr_indirect <= datain;
sr1_dstd <= sr1_p2;
if ir(2 downto 0) /= "111" then
rbus_waddr <= pswmf(15 downto 14) & pswmf(11) & ir(2 downto 0);
rbus_d <= rbus_data_p2;
rbus_we <= '1';
else
r7 <= rbus_data_p2;
end if;
state <= state_dst3a;
when state_dst3a =>
dest_addr <= addr;
alu_input <= datain;
state <= pdststate;
when state_src3 =>
addr_indirect <= datain;
rbus_ix <= ir(2 downto 0);
sr1_srcd <= sr1_p2;
if ir(8 downto 6) /= "111" then
rbus_waddr <= pswmf(15 downto 14) & pswmf(11) & ir(8 downto 6);
rbus_d <= rbus_data_p2;
rbus_we <= '1';
else
r7 <= rbus_data_p2;
end if;
state <= state_src3a;
when state_src3a =>
alus_input <= datain;
state <= psrcstate;
when state_dst4 =>
dest_addr <= addr;
alu_input <= datain;
state <= pdststate;
sr1_dstd <= sr1_mv;
if ir(2 downto 0) /= "111" then
rbus_waddr <= pswmf(15 downto 14) & pswmf(11) & ir(2 downto 0);
rbus_d <= rbus_data_mv;
rbus_we <= '1';
else
r7 <= rbus_data_m2; -- FIXME, where does this even begin to make sense - it would effectively jump to the same insn?
end if;
when state_src4 =>
alus_input <= datain;
if ir_dop = '1' and ir(8 downto 6) = ir(2 downto 0) and ir(2 downto 0) /= "111" then
state <= state_src4w;
else
state <= psrcstate;
end if;
rbus_ix <= ir(2 downto 0);
sr1_srcd <= sr1_mv;
if ir(8 downto 6) /= "111" then
rbus_waddr <= pswmf(15 downto 14) & pswmf(11) & ir(8 downto 6);
rbus_d <= rbus_data_mv;
rbus_we <= '1';
else
r7 <= rbus_data_m2;
end if;
when state_src4w =>
state <= psrcstate;
when state_dst5 =>
addr_indirect <= datain;
sr1_dstd <= sr1_m2;
if ir(2 downto 0) /= "111" then
rbus_waddr <= pswmf(15 downto 14) & pswmf(11) & ir(2 downto 0);
rbus_d <= rbus_data_m2;
rbus_we <= '1';
else
r7 <= rbus_data_m2;
end if;
state <= state_dst5a;
when state_dst5a =>
dest_addr <= addr;
alu_input <= datain;
state <= pdststate;
when state_src5 =>
addr_indirect <= datain;
rbus_ix <= ir(2 downto 0);
sr1_srcd <= sr1_m2;
if ir(8 downto 6) /= "111" then
rbus_waddr <= pswmf(15 downto 14) & pswmf(11) & ir(8 downto 6);
rbus_d <= rbus_data_m2;
rbus_we <= '1';
else
r7 <= rbus_data_m2;
end if;
state <= state_src5a;
when state_src5a =>
alus_input <= datain;
state <= psrcstate;
when state_dst6 =>
r7 <= r7p2;
if ir(2 downto 0) = "111" then
addr_indirect <= unsigned(datain) + unsigned(rbus_data_p2);
else
addr_indirect <= unsigned(datain) + unsigned(rbus_data);
end if;
state <= state_dst6a;
when state_dst6a =>
dest_addr <= addr;
alu_input <= datain;
state <= pdststate;
when state_src6 =>
r7 <= r7p2;
if ir(8 downto 6) = "111" then
addr_indirect <= unsigned(datain) + unsigned(rbus_data_p2);
else
addr_indirect <= unsigned(datain) + unsigned(rbus_data);
end if;
state <= state_src6a;
when state_src6a =>
alus_input <= datain;
state <= psrcstate;
rbus_ix <= ir(2 downto 0);
when state_dst7 =>
r7 <= r7p2;
if ir(2 downto 0) = "111" then
addr_indirect <= unsigned(datain) + unsigned(rbus_data_p2);
else
addr_indirect <= unsigned(datain) + unsigned(rbus_data);
end if;
state <= state_dst7a;
when state_dst7a =>
addr_indirect <= datain;
state <= state_dst7b;
when state_dst7b =>
dest_addr <= addr;
alu_input <= datain;
state <= pdststate;
rbus_ix <= "110";
when state_src7 =>
r7 <= r7p2;
if ir(8 downto 6) = "111" then
addr_indirect <= unsigned(datain) + unsigned(rbus_data_p2);
else
addr_indirect <= unsigned(datain) + unsigned(rbus_data);
end if;
state <= state_src7a;
when state_src7a =>
addr_indirect <= datain;
state <= state_src7b;
when state_src7b =>
alus_input <= datain;
state <= psrcstate;
rbus_ix <= ir(2 downto 0);
when state_store_alu_p =>
state <= state_store_alu_w;
when state_store_alu_w =>
psw(3 downto 0) <= alu_psw;
if psw_in_we_even = '1' then -- direct write into 777776 overrides psw setting from alu
if have_pswimmediateupdate = 1 then
psw(7 downto 5) <= psw_in(7 downto 5); -- T bit can only be set with RTI/RTT instruction
psw(3 downto 0) <= psw_in(3 downto 0);
else
psw_delayedupdate_even <= '1';
psw_delayedupdate(7 downto 0) <= psw_in(7 downto 0);
end if;
end if;
if psw_in_we_odd = '1' then
if have_pswimmediateupdate = 1 then
psw(15 downto 8) <= psw_in(15 downto 8);
else
psw_delayedupdate_odd <= '1';
psw_delayedupdate(15 downto 8) <= psw_in(15 downto 8);
end if;
end if;
state <= state_ifetch;
if ir(15 downto 6) = "1111000011" then -- stst?
if ir(5 downto 0) /= "010111" then -- not if mode 2, r7 -- immediate
state <= state_stststore;
dest_addr <= dest_addr + 2;
end if;
end if;
when state_store_alu_r =>
if ir_store = '1' then
if ir(2 downto 0) /= "111" then
if ir_mtpi = '1' or ir_mtpd = '1' then
rbus_waddr <= pswmf(13 downto 12) & pswmf(11) & ir(2 downto 0);
else
rbus_waddr <= pswmf(15 downto 14) & pswmf(11) & ir(2 downto 0);
end if;
if ir(15 downto 12) = "1001" then -- movb? movb needs to sign extend if the result is moved to a register
rbus_d <= alu_output_signext;
elsif have_mtps = 1 and ir_mfps = '1' then -- mfps needs sign extend if the result is moved to a register
rbus_d <= alu_output_signext;
elsif ir_byte = '1' then
rbus_d <= alu_input(15 downto 8) & alu_output(7 downto 0);
else
rbus_d <= alu_output;
end if;
rbus_we <= '1';
else
r7 <= alu_output;
end if;
end if;
psw(3 downto 0) <= alu_psw;
state <= state_ifetch;
when others =>
null;
end case;
end if;
if nxmabort = '1' then
if modelcode = 34 -- FIXME, if this is disabled for these models, FKAB, KKAB will fail. However, if enabled for 45, unix v7 will fail during /etc/rc processing.
or modelcode = 44
or modelcode = 04
then
if state = state_src2 or state = state_src3 then
rbus_we <= '0';
sr1_srcd <= "00000";
end if;
if state = state_dst2 or state = state_dst3 then
rbus_we <= '0';
sr1_dstd <= "00000";
end if;
end if;
trap_vector <= o"004";
state <= state_trap;
end if;
if mmuabort = '1' and have_mmuimmediateabort = 0 then -- signal from mmu that an access caused an abort.
state <= state_mmuabort; -- precursor state for mmu abort
ack_mmuabort <= '1'; -- set acknowledge flag to mmu core
elsif oddabort = '1' and have_oddimmediateabort = 0 then -- odd abort signal
trap_vector <= o"004"; -- set vector
state <= state_trap; -- do trap
end if;
end if;
end if;
end process;
-- base instruction set alu
process(alu_input, alus_input, ir, psw(3 downto 0),
ir_sop, ir_dop, ir_mfpi, ir_csm, ir_mfpd, ir_mtpi, ir_mtpd, ir_mtps, ir_mfps, ir_dopr, ir_mpr, ir_fpsop1,
have_csm, have_mfp, have_mtps, have_xor, have_mpr, fps, fec,
modelcode)
variable result : std_logic_vector(15 downto 0);
variable result8 : std_logic_vector(7 downto 0);
begin
ir_byte <= '0';
ir_store <= '1';
if ir_sop = '1' then
case ir(15 downto 6) is
when "0000000011" => -- swab
result(15 downto 8) := alu_input(7 downto 0);
result(7 downto 0) := alu_input(15 downto 8);
alu_output <= result;
alu_psw(3) <= alu_input(15);
if alu_input(15 downto 8) = "00000000" then
alu_psw(2) <= '1';
else
alu_psw(2) <= '0';
end if;
if modelcode = 15 or modelcode = 20 then
alu_psw(1) <= psw(1);
else
alu_psw(1) <= '0';
end if;
alu_psw(0) <= '0';
when "0000101000" => -- clr
result := "0000000000000000";
alu_output <= result;
alu_psw(3 downto 0) <= "0100";
when "1000101000" => -- clrb
ir_byte <= '1';
result := "0000000000000000";
alu_output <= result;
alu_psw(3 downto 0) <= "0100";
when "0000101001" => -- com
result := not alu_input;
alu_output <= result;
alu_psw(3) <= not alu_input(15);
if not alu_input = "0000000000000000" then
alu_psw(2) <= '1';
else
alu_psw(2) <= '0';
end if;
alu_psw(1 downto 0) <= "01";
when "1000101001" => -- comb
ir_byte <= '1';
result := not alu_input;
alu_output <= result;
alu_psw(3) <= not alu_input(7);
if not alu_input(7 downto 0) = "00000000" then
alu_psw(2) <= '1';
else
alu_psw(2) <= '0';
end if;
alu_psw(1 downto 0) <= "01";
when "0000101010" => -- inc
result := alu_input + 1;
alu_output <= result;
alu_psw(3) <= result(15);
if result = "0000000000000000" then
alu_psw(2) <= '1';
else
alu_psw(2) <= '0';
end if;
if alu_input = "0111111111111111" then
alu_psw(1) <= '1';
else
alu_psw(1) <= '0';
end if;
alu_psw(0) <= psw(0);
when "1000101010" => -- incb
ir_byte <= '1';
result := alu_input + 1;
alu_output <= result;
alu_psw(3) <= result(7);
if result(7 downto 0) = "00000000" then
alu_psw(2) <= '1';
else
alu_psw(2) <= '0';
end if;
if alu_input(7 downto 0) = "01111111" then
alu_psw(1) <= '1';
else
alu_psw(1) <= '0';
end if;
alu_psw(0) <= psw(0);
when "0000101011" => -- dec
result := alu_input - 1;
alu_output <= result;
alu_psw(3) <= result(15);
if result = "0000000000000000" then
alu_psw(2) <= '1';
else
alu_psw(2) <= '0';
end if;
if alu_input = "1000000000000000" then
alu_psw(1) <= '1';
else
alu_psw(1) <= '0';
end if;
alu_psw(0) <= psw(0);
when "1000101011" => -- decb
ir_byte <= '1';
result := alu_input - 1;
alu_output <= result;
alu_psw(3) <= result(7);
if result(7 downto 0) = "00000000" then
alu_psw(2) <= '1';
else
alu_psw(2) <= '0';
end if;
if alu_input(7 downto 0) = "10000000" then
alu_psw(1) <= '1';
else
alu_psw(1) <= '0';
end if;
alu_psw(0) <= psw(0);
when "0000101100" => -- neg
result := (not alu_input) + 1;
alu_output <= result;
alu_psw(3) <= result(15);
if result = "0000000000000000" then
alu_psw(2) <= '1';
alu_psw(0) <= '0';
else
alu_psw(2) <= '0';
alu_psw(0) <= '1';
end if;
if result = "1000000000000000" then
alu_psw(1) <= '1';
else
alu_psw(1) <= '0';
end if;
when "1000101100" => -- negb
ir_byte <= '1';
result := (not alu_input) + 1;
alu_output <= result;
alu_psw(3) <= result(7);
if result(7 downto 0) = "00000000" then
alu_psw(2) <= '1';
alu_psw(0) <= '0';
else
alu_psw(2) <= '0';
alu_psw(0) <= '1';
end if;
if result(7 downto 0) = "10000000" then
alu_psw(1) <= '1';
else
alu_psw(1) <= '0';
end if;
when "0000101101" => -- adc
result := alu_input + psw(0);
alu_output <= result;
alu_psw(3) <= result(15);
if result = "0000000000000000" then
alu_psw(2) <= '1';
else
alu_psw(2) <= '0';
end if;
if alu_input = "0111111111111111" and psw(0) = '1' then
alu_psw(1) <= '1';
else
alu_psw(1) <= '0';
end if;
if alu_input = "1111111111111111" and psw(0) = '1' then
alu_psw(0) <= '1';
else
alu_psw(0) <= '0';
end if;
when "1000101101" => -- adcb
ir_byte <= '1';
result := alu_input + psw(0);
alu_output <= result;
alu_psw(3) <= result(7);
if result(7 downto 0) = "00000000" then
alu_psw(2) <= '1';
else
alu_psw(2) <= '0';
end if;
if alu_input(7 downto 0) = "01111111" and psw(0) = '1' then
alu_psw(1) <= '1';
else
alu_psw(1) <= '0';
end if;
if alu_input(7 downto 0) = "11111111" and psw(0) = '1' then
alu_psw(0) <= '1';
else
alu_psw(0) <= '0';
end if;
when "0000101110" => -- sbc
result := alu_input - psw(0);
alu_output <= result;
alu_psw(3) <= result(15);
if result = "0000000000000000" then
alu_psw(2) <= '1';
else
alu_psw(2) <= '0';
end if;
if alu_input = "1000000000000000" and psw(0) = '1' then
alu_psw(1) <= '1';
else
alu_psw(1) <= '0';
end if;
if alu_input = "0000000000000000" and psw(0) = '1' then
alu_psw(0) <= '1';
else
alu_psw(0) <= '0';
end if;
when "1000101110" => -- sbcb
ir_byte <= '1';
result := alu_input - psw(0);
alu_output <= result;
alu_psw(3) <= result(7);
if result(7 downto 0) = "00000000" then
alu_psw(2) <= '1';
else
alu_psw(2) <= '0';
end if;
if alu_input(7 downto 0) = "10000000" and psw(0) = '1' then
alu_psw(1) <= '1';
else
alu_psw(1) <= '0';
end if;
if alu_input(7 downto 0) = "00000000" and psw(0) = '1' then
alu_psw(0) <= '1';
else
alu_psw(0) <= '0';
end if;
when "0000101111" => -- tst
result := alu_input;
alu_output <= result;
ir_store <= '0';
alu_psw(3) <= result(15);
if result = "0000000000000000" then
alu_psw(2) <= '1';
else
alu_psw(2) <= '0';
end if;
alu_psw(1 downto 0) <= "00";
when "1000101111" => -- tstb
ir_byte <= '1';
result := alu_input;
alu_output <= result;
ir_store <= '0';
alu_psw(3) <= result(7);
if result(7 downto 0) = "00000000" then
alu_psw(2) <= '1';
else
alu_psw(2) <= '0';
end if;
alu_psw(1 downto 0) <= "00";
when "0000110000" => -- ror
result := psw(0) & alu_input(15 downto 1);
alu_output <= result;
alu_psw(3) <= result(15);
if result = "0000000000000000" then
alu_psw(2) <= '1';
else
alu_psw(2) <= '0';
end if;
alu_psw(1) <= alu_input(0) xor result(15);
alu_psw(0) <= alu_input(0);
when "1000110000" => -- rorb
ir_byte <= '1';
result8 := psw(0) & alu_input(7 downto 1);
alu_output(7 downto 0) <= result8;
alu_output(15 downto 8) <= "XXXXXXXX";
alu_psw(3) <= result8(7);
if result8 = "00000000" then
alu_psw(2) <= '1';
else
alu_psw(2) <= '0';
end if;
alu_psw(1) <= alu_input(0) xor result8(7);
alu_psw(0) <= alu_input(0);
when "0000110001" => -- rol
result := alu_input(14 downto 0) & psw(0);
alu_output <= result;
alu_psw(3) <= result(15);
if result = "0000000000000000" then
alu_psw(2) <= '1';
else
alu_psw(2) <= '0';
end if;
alu_psw(1) <= alu_input(15) xor result(15);
alu_psw(0) <= alu_input(15);
when "1000110001" => -- rolb
ir_byte <= '1';
result8 := alu_input(6 downto 0) & psw(0);
alu_output(7 downto 0) <= result8;
alu_output(15 downto 8) <= "XXXXXXXX";
alu_psw(3) <= result8(7);
if result8 = "00000000" then
alu_psw(2) <= '1';
else
alu_psw(2) <= '0';
end if;
alu_psw(1) <= alu_input(7) xor result8(7);
alu_psw(0) <= alu_input(7);
when "0000110010" => -- asr
result := alu_input(15) & alu_input(15 downto 1);
alu_output <= result;
alu_psw(3) <= result(15);
if result = "0000000000000000" then
alu_psw(2) <= '1';
else
alu_psw(2) <= '0';
end if;
alu_psw(1) <= alu_input(0) xor result(15);
alu_psw(0) <= alu_input(0);
when "1000110010" => -- asrb
ir_byte <= '1';
result8 := alu_input(7) & alu_input(7 downto 1);
alu_output(7 downto 0) <= result8;
alu_output(15 downto 8) <= "XXXXXXXX";
alu_psw(3) <= result8(7);
if result8 = "00000000" then
alu_psw(2) <= '1';
else
alu_psw(2) <= '0';
end if;
alu_psw(1) <= alu_input(0) xor result8(7);
alu_psw(0) <= alu_input(0);
when "0000110011" => -- asl
result := alu_input(14 downto 0) & '0';
alu_output <= result;
alu_psw(3) <= result(15);
if result = "0000000000000000" then
alu_psw(2) <= '1';
else
alu_psw(2) <= '0';
end if;
alu_psw(1) <= alu_input(15) xor result(15);
alu_psw(0) <= alu_input(15);
when "1000110011" => -- aslb
ir_byte <= '1';
result8 := alu_input(6 downto 0) & '0';
alu_output(7 downto 0) <= result8;
alu_output(15 downto 8) <= "XXXXXXXX";
alu_psw(3) <= result8(7);
if result8 = "00000000" then
alu_psw(2) <= '1';
else
alu_psw(2) <= '0';
end if;
alu_psw(1) <= alu_input(7) xor result8(7);
alu_psw(0) <= alu_input(7);
when "0000110111" => -- sxt
if psw(3) = '0' then
result := "0000000000000000";
alu_psw(2) <= '1';
else
result := "1111111111111111";
alu_psw(2) <= '0';
end if;
alu_output <= result;
alu_psw(3) <= psw(3);
alu_psw(1) <= '0';
alu_psw(0) <= psw(0);
when others =>
alu_output <= "XXXXXXXXXXXXXXXX";
alu_psw <= "XXXX";
end case;
elsif ir_dop = '1' then
case ir(15 downto 12) is
when "0001" => -- mov
result := alus_input;
alu_output <= result;
alu_psw(3) <= result(15);
if result = "0000000000000000" then
alu_psw(2) <= '1';
else
alu_psw(2) <= '0';
end if;
alu_psw(1) <= '0';
alu_psw(0) <= psw(0);
when "1001" => -- movb
ir_byte <= '1';
result := alus_input;
alu_output <= result;
alu_psw(3) <= result(7);
if result(7 downto 0) = "00000000" then
alu_psw(2) <= '1';
else
alu_psw(2) <= '0';
end if;
alu_psw(1) <= '0';
alu_psw(0) <= psw(0);
when "0010" => -- cmp
result := alus_input - alu_input;
alu_output <= alu_input;
ir_store <= '0';
alu_psw(3) <= result(15);
if result = "0000000000000000" then
alu_psw(2) <= '1';
else
alu_psw(2) <= '0';
end if;
if (alu_input(15) /= alus_input(15)) and (alus_input(15) /= result(15)) then
alu_psw(1) <= '1';
else
alu_psw(1) <= '0';
end if;
alu_psw(0) <= ((not alus_input(15)) and alu_input(15)) or ((not alus_input(15)) and result(15)) or (alu_input(15) and result(15));
when "1010" => -- cmpb
ir_byte <= '1';
result8 := alus_input(7 downto 0) - alu_input(7 downto 0);
alu_output <= alu_input;
ir_store <= '0';
alu_psw(3) <= result8(7);
if result8 = "00000000" then
alu_psw(2) <= '1';
else
alu_psw(2) <= '0';
end if;
if (alu_input(7) /= alus_input(7)) and (alus_input(7) /= result8(7)) then
alu_psw(1) <= '1';
else
alu_psw(1) <= '0';
end if;
alu_psw(0) <= ((not alus_input(7)) and alu_input(7)) or ((not alus_input(7)) and result8(7)) or (alu_input(7) and result8(7));
when "0011" => -- bit
result := alus_input and alu_input;
alu_output <= alu_input;
ir_store <= '0';
alu_psw(3) <= result(15);
if result = "0000000000000000" then
alu_psw(2) <= '1';
else
alu_psw(2) <= '0';
end if;
alu_psw(1) <= '0';
alu_psw(0) <= psw(0);
when "1011" => -- bitb
ir_byte <= '1';
result := alus_input and alu_input;
alu_output <= alu_input;
ir_store <= '0';
alu_psw(3) <= result(7);
if result(7 downto 0) = "00000000" then
alu_psw(2) <= '1';
else
alu_psw(2) <= '0';
end if;
alu_psw(1) <= '0';
alu_psw(0) <= psw(0);
when "0100" => -- bic
result := (not alus_input) and alu_input;
alu_output <= result;
alu_psw(3) <= result(15);
if result = "0000000000000000" then
alu_psw(2) <= '1';
else
alu_psw(2) <= '0';
end if;
alu_psw(1) <= '0';
alu_psw(0) <= psw(0);
when "1100" => -- bicb
ir_byte <= '1';
result := (not alus_input) and alu_input;
alu_output <= result;
alu_psw(3) <= result(7);
if result(7 downto 0) = "00000000" then
alu_psw(2) <= '1';
else
alu_psw(2) <= '0';
end if;
alu_psw(1) <= '0';
alu_psw(0) <= psw(0);
when "0101" => -- bis
result := alus_input or alu_input;
alu_output <= result;
alu_psw(3) <= result(15);
if result = "0000000000000000" then
alu_psw(2) <= '1';
else
alu_psw(2) <= '0';
end if;
alu_psw(1) <= '0';
alu_psw(0) <= psw(0);
when "1101" => -- bisb
ir_byte <= '1';
result := alus_input or alu_input;
alu_output <= result;
alu_psw(3) <= result(7);
if result(7 downto 0) = "00000000" then
alu_psw(2) <= '1';
else
alu_psw(2) <= '0';
end if;
alu_psw(1) <= '0';
alu_psw(0) <= psw(0);
when "0110" => -- add
result := alu_input + alus_input;
alu_output <= result;
alu_psw(3) <= result(15);
if result = "0000000000000000" then
alu_psw(2) <= '1';
else
alu_psw(2) <= '0';
end if;
if (alu_input(15) = alus_input(15)) and (alus_input(15) /= result(15)) then
alu_psw(1) <= '1';
else
alu_psw(1) <= '0';
end if;
alu_psw(0) <= (alu_input(15) and alus_input(15)) or (alu_input(15) and not result(15)) or (alus_input(15) and not result(15));
when "1110" => -- sub
result := alu_input - alus_input;
alu_output <= result;
alu_psw(3) <= result(15);
if result = "0000000000000000" then
alu_psw(2) <= '1';
else
alu_psw(2) <= '0';
end if;
if (alu_input(15) /= alus_input(15)) and (alu_input(15) /= result(15)) then
alu_psw(1) <= '1';
else
alu_psw(1) <= '0';
end if;
alu_psw(0) <= ((not alu_input(15)) and alus_input(15)) or ((not alu_input(15)) and result(15)) or (alus_input(15) and result(15));
when others =>
alu_output <= "XXXXXXXXXXXXXXXX";
alu_psw <= "XXXX";
end case;
-- misc insns
elsif have_csm = 1 and ir_csm = '1' then -- csm
alu_output <= alu_input;
alu_psw <= psw(3 downto 0);
elsif have_mfp = 1 and (ir_mfpi = '1' or ir_mfpd = '1') then -- mfpi, mfpd, mtpi, mtpd
alu_output <= alu_input;
alu_psw(3) <= alu_input(15);
if alu_input = "0000000000000000" then
alu_psw(2) <= '1';
else
alu_psw(2) <= '0';
end if;
alu_psw(1) <= '0';
alu_psw(0) <= psw(0);
elsif have_mfp = 1 and (ir_mtpi = '1' or ir_mtpd = '1') then -- mfpi, mfpd, mtpi, mtpd
alu_output <= alus_input;
alu_psw(3) <= alus_input(15);
if alus_input = "0000000000000000" then
alu_psw(2) <= '1';
else
alu_psw(2) <= '0';
end if;
alu_psw(1) <= '0';
alu_psw(0) <= psw(0);
elsif have_mtps = 1 and ir_mtps = '1' then -- mtps
ir_byte <= '1';
alu_output <= alu_input;
alu_psw <= psw(3 downto 0);
elsif have_mtps = 1 and ir_mfps = '1' then -- mfps
ir_byte <= '1';
alu_output <= psw;
alu_psw(3) <= psw(7);
if psw(7 downto 0) = "0000000" then
alu_psw(2) <= '1';
else
alu_psw(2) <= '0';
end if;
alu_psw(1) <= '0';
alu_psw(0) <= psw(0);
elsif have_xor = 1 and ir_dopr = '1' and ir(11 downto 9) = "100" then -- xor
result := alu_input xor alus_input; -- xor is handled here, not in the eis alu
alu_output <= result;
alu_psw(3) <= result(15);
if result = "0000000000000000" then
alu_psw(2) <= '1';
else
alu_psw(2) <= '0';
end if;
alu_psw(1) <= '0';
alu_psw(0) <= psw(0);
elsif have_mpr = 1 and ir_mpr = '1' then
case ir(6) is
when '0' => -- tstset
result := alu_input(15 downto 1) & '1';
alu_output <= result;
alu_psw(3) <= alu_input(15);
if alu_input = "0000000000000000" then
alu_psw(2) <= '1';
else
alu_psw(2) <= '0';
end if;
alu_psw(1) <= '0';
alu_psw(0) <= alu_input(0);
when '1' => -- wrtlck
result := alu_input;
alu_output <= result;
alu_psw(3) <= alu_input(15);
if alu_input = "0000000000000000" then
alu_psw(2) <= '1';
else
alu_psw(2) <= '0';
end if;
alu_psw(1) <= '0';
alu_psw(0) <= psw(0);
when others =>
null;
end case;
-- fp11 insns with simple integer result
elsif ir_fpsop1 = '1' then
alu_psw(3 downto 0) <= psw(3 downto 0);
case ir(7 downto 6) is
when "01" => -- ldfps
result := alu_input;
alu_output <= result;
when "10" => -- stfps
result(15 downto 14) := fps(15 downto 14);
result(13 downto 12) := "00"; -- set these unused bits to zero to stop the tests complaining
result(11 downto 0) := fps(11 downto 0);
alu_output <= result;
when "11" => -- stst
result := "000000000000" & fec;
alu_output <= result;
when others =>
alu_output <= "XXXXXXXXXXXXXXXX";
alu_psw <= "XXXX";
end case;
else
alu_output <= "XXXXXXXXXXXXXXXX";
alu_psw <= "XXXX";
end if;
end process;
--
-- eis alu: mul, div, ash, ashc insns
--
process(clk)
begin
if clk = '1' and clk'event then
if have_eis = 1 and ir_dopr = '1' and ir(11) = '0' then
case ir(10 downto 9) is
when "00" => -- mul
if eis_sequencer = "11111" then -- load seq. code
eis_temp1 <= signed(alu_input) * signed(alus_input); -- mul is easy, just use the hw multipliers
elsif eis_sequencer = "00000" then -- done seq. code
eis_output <= eis_temp1(31 downto 16); -- high part
eis_output32 <= eis_temp1(15 downto 0); -- low part
eis_psw(3) <= eis_temp1(31); -- set n
if eis_temp1 = "00000000000000000000000000000000" then -- set z
eis_psw(2) <= '1';
else
eis_psw(2) <= '0';
end if;
eis_psw(1) <= '0'; -- set v - always 0, 15bits*15bits into 31 cannot overflow
if (eis_temp1(31) = '1' and eis_temp1(30 downto 15) /= "1111111111111111")
or (eis_temp1(31) = '0' and eis_temp1(30 downto 15) /= "0000000000000000") then
eis_psw(0) <= '1';
else
eis_psw(0) <= '0';
end if;
end if;
when "01" => -- div
if eis_sequencer = "10000" then -- load seq. code
if alu_input(15) = '1' then -- if input negative
eis_temp1 <= '0' & ((not alu_input) + 1) & (14 downto 0 => '0'); -- take two's complement
eis_flag1 <= '1';
else
eis_temp1 <= '0' & alu_input & (14 downto 0 => '0');
eis_flag1 <= '0';
end if;
if alus_input(15) = '1' then
eis_temp2 <= (not (alus_input & alut_input)) + 1;
eis_flag2 <= '1';
else
eis_temp2 <= alus_input & alut_input;
eis_flag2 <= '0';
end if;
eis_psw <= "0000";
-- main div loop
elsif eis_sequencer(4) = '0' then
if unsigned(eis_temp1) <= unsigned(eis_temp2) then
if eis_sequencer(3 downto 0) = "1111" then
if unsigned(eis_temp1) <= unsigned(eis_temp2) then
eis_psw(1) <= '1';
end if;
end if;
eis_temp(conv_integer(eis_sequencer(3 downto 0))) <= '1';
eis_temp2 <= eis_temp2 - eis_temp1;
else
eis_temp(conv_integer(eis_sequencer(3 downto 0))) <= '0';
end if;
eis_temp1(30 downto 0) <= eis_temp1(31 downto 1);
else
-- post processing
-- setting the flags after the div instruction is the tricky part. A division by zero causes
-- the result not to be stored - which is handled by the state machine, results are only
-- stored if the v and c flags are 00. Still a very tricky thing considering all the
-- border cases. I believe the current model is correct - and also, it passes all the tests
-- I can find. Specifically, fkac, and zkdj - and the results make sense as well.
if eis_flag2 = '1' then -- if 2nd op was negative
eis_output32 <= (not eis_temp2(15 downto 0)) + 1; -- sign adjust remainder
else
eis_output32 <= eis_temp2(15 downto 0); -- or just the positive
end if;
if eis_flag1 /= eis_flag2 then -- if signs were different
eis_psw(3) <= '1'; -- set N
eis_output <= (not eis_temp) + 1; -- sign adjust result
else
eis_psw(3) <= '0'; -- clear n
eis_output <= eis_temp; -- copy result
end if;
-- special cases : result is zero
if eis_temp(14 downto 0) = (14 downto 0 => '0') then
if eis_temp(15) = '0' then
eis_psw(3) <= '0';
eis_psw(2) <= '1';
eis_output(15) <= '0';
else
eis_psw(2) <= '0';
end if;
if eis_temp(15) = '1' and eis_flag1 /= eis_flag2 then
eis_psw(1) <= '0'; -- special case: quotient is negative maxint - that isn't an overflow
end if;
else
eis_psw(2) <= '0';
end if;
-- set c and v if divisor was zero
if alu_input = (15 downto 0 => '0') then
if modelcode = 73 or modelcode = 83 or modelcode = 84 or modelcode = 93 or modelcode = 94 or modelcode = 53 then
eis_psw(2) <= psw(2); -- observed behaviour and needed to pass zkdj FIXME
end if;
eis_psw(1) <= '1';
eis_psw(0) <= '1';
end if;
end if;
when "10" => -- ash
if eis_sequencer = "11111" then
eis_output <= alus_input;
eis_flag2 <= '0';
eis_psw(1) <= '0';
eis_psw(0) <= '0';
eis_temp(15 downto 6) <= "0000000000"; -- for easier debugging
eis_flag1 <= alu_input(5);
if alu_input(4 downto 0) = "11111" then -- see EK-1184E-TM-001_Dec87.pdf, page B-17
if modelcode = 73
or modelcode = 53
or modelcode = 83
or modelcode = 84
or modelcode = 93
or modelcode = 94
then
if have_fpa = 0 then -- Speculative - see ashc case
eis_flag1 <= '1';
end if;
end if;
end if;
if alu_input(5) = '1' then
eis_temp(5 downto 0) <= (not alu_input(5 downto 0)) + 1;
else
eis_temp(5 downto 0) <= alu_input(5 downto 0);
end if;
else
if eis_temp(5 downto 0) /= "000000" then
if eis_flag1 = '1' then
eis_output <= eis_output(15) & eis_output(15 downto 1);
eis_psw(0) <= eis_output(0);
else
eis_output <= eis_output(14 downto 0) & '0';
if eis_output(15 downto 14) = "10" or eis_output(15 downto 14) = "01" then
eis_psw(1) <= '1';
end if;
eis_psw(0) <= eis_output(15);
end if;
eis_temp(5 downto 0) <= eis_temp(5 downto 0) - 1;
else
eis_flag2 <= '1';
eis_psw(3) <= eis_output(15);
if eis_output = "0000000000000000" then
eis_psw(2) <= '1';
else
eis_psw(2) <= '0';
end if;
end if;
end if;
when "11" => -- ashc
if eis_sequencer = "11111" then
eis_temp1 <= alus_input & alut_input;
eis_flag2 <= '0';
eis_psw(1) <= '0';
eis_psw(0) <= '0';
eis_temp(15 downto 6) <= "0000000000"; -- for easier debugging
eis_flag1 <= alu_input(5);
if alu_input(4 downto 0) = "11111" then -- see EK-1184E-TM-001_Dec87.pdf, page B-17
if modelcode = 73
or modelcode = 53
or modelcode = 83
or modelcode = 84
or modelcode = 93
or modelcode = 94
then
if have_fpa = 0 then -- As evidenced from the test code in RSTS V10.1L
eis_flag1 <= '1';
end if;
end if;
end if;
if alu_input(5) = '1' then
eis_temp(5 downto 0) <= ('0' & (not alu_input(4 downto 0))) + 1;
else
eis_temp(4 downto 0) <= alu_input(4 downto 0);
eis_temp(5) <= '0';
end if;
else
if eis_temp(5 downto 0) /= "000000" then
if eis_flag1 = '1' then
eis_temp1 <= eis_temp1(31) & eis_temp1(31 downto 1);
eis_psw(0) <= eis_temp1(0);
else
eis_temp1 <= eis_temp1(30 downto 0) & '0';
if eis_temp1(31 downto 30) = "10" or eis_temp1(31 downto 30) = "01" then
eis_psw(1) <= '1';
end if;
eis_psw(0) <= eis_temp1(31);
end if;
eis_temp(5 downto 0) <= eis_temp(5 downto 0) - 1;
else
eis_flag2 <= '1';
eis_output <= eis_temp1(31 downto 16);
eis_output32 <= eis_temp1(15 downto 0);
eis_psw(3) <= eis_temp1(31);
if eis_temp1 = "00000000000000000000000000000000" then
eis_psw(2) <= '1';
else
eis_psw(2) <= '0';
end if;
end if;
end if;
when others =>
null;
end case;
end if;
end if;
end process;
-- floating point alu
process(clk, reset, falu_pending_clear, ir_fpao, falu_load, falu_input, falus_input, ir_wait)
variable v_caseworkaround : std_logic_vector(3 downto 0);
begin
if clk = '1' and clk'event then
if have_fpu = 1 and reset = '1' then
falu_done <= '0';
falu_fsm <= falu_idle;
falu_fps <= "0000";
falu_flag1 <= '0';
falu_pending_fiu <= '0';
falu_pending_fiv <= '0';
falu_pending_fic <= '0';
falu_pending_divz <= '0';
elsif have_fpu = 1 and ir_wait = '0' then
if falu_pending_clear = '1' then
falu_pending_fiu <= '0';
falu_pending_fiv <= '0';
falu_pending_fic <= '0';
falu_pending_divz <= '0';
end if;
if ir_fpao = '1' then
-- if the falu_load bit is one, load the work registers and the initial state for the falu state machine.
-- both of which are dependent on exactly which instruction we need to process - the sequence in the
-- state machine needs to be started at a specific point, which is not the same for all insn - and
-- definitely all insn have their own initialization requirements and special cases.
--
-- also, the main cpu state machine includes
if falu_load = '1' then
falu_done <= '0';
falu_fps <= "0000";
case ir(11 downto 8) is
when "0010" | "0011" => -- mul(f|d), mod(f|d)
if falu_input(63) = falus_input(63) then -- set sign - positive if both operands are same sign, negative otherwise
falu_fps(3) <= '0';
else
falu_fps(3) <= '1';
end if;
falu_fps(2 downto 0) <= "000"; -- set default for fps bits
falu_fsm <= falu_mult;
falu_work1 <= (others => '0');
falu_work2 <= '0' & '1' & falus_input(54 downto 0) & '0' & '0';
if falu_input(62 downto 55) = "00000000" or falus_input(62 downto 55) = "00000000" then -- if either input exponent is zero, we don't need to multiply at all
falu_output <= (others => '0');
falu_output2 <= (others => '0');
falu_fps <= "0100";
falu_fsm <= falu_idle;
falu_done <= '1';
end if;
falu_ccw <= ("00" & falu_input(62 downto 55)) + ("00" & falus_input(62 downto 55)) - "0010000001";
when "0100" | "0110" => -- add(f|d), sub(f|d)
falu_fsm <= falu_align;
falu_work1 <= '0' & '1' & falu_input(54 downto 0) & '0' & '0';
falu_work2 <= '0' & '1' & falus_input(54 downto 0) & '0' & '0';
falu_fps(3 downto 0) <= "0000"; -- set default for fps bits
if falu_input(62 downto 55) = "00000000" then -- if the primary input exponent is zero, we don't need to add (or subtract) at all
falu_output <= falus_input;
falu_fps(3) <= falus_input(63);
if falus_input(62 downto 55) = "00000000" then
falu_fps(2) <= '1';
else
falu_fps(2) <= '0';
end if;
falu_fsm <= falu_idle;
falu_done <= '1';
elsif falus_input(62 downto 55) = "00000000" then -- if the secondary input exponent is zero, we don't need to add (or subtract) at all
falu_output(62 downto 0) <= falu_input(62 downto 0);
if ir(9) = '0' then
falu_fps(3) <= falu_input(63);
falu_output(63) <= falu_input(63);
else
falu_fps(3) <= not falu_input(63);
falu_output(63) <= not falu_input(63);
end if;
falu_fsm <= falu_idle;
falu_done <= '1';
elsif unsigned(falu_input(62 downto 55)) < unsigned(falus_input(62 downto 55)) then
falu_ccw <= "00" & (unsigned(falus_input(62 downto 55)) - unsigned(falu_input(62 downto 55)));
falu_flag1 <= '1';
elsif unsigned(falu_input(62 downto 55)) = unsigned(falus_input(62 downto 55)) then
falu_ccw <= (others => '0');
if unsigned(falu_input(54 downto 0)) < unsigned(falus_input(54 downto 0)) then
falu_flag1 <= '1';
else
falu_flag1 <= '0';
end if;
else
falu_ccw <= "00" & (unsigned(falu_input(62 downto 55)) - unsigned(falus_input(62 downto 55)));
falu_flag1 <= '0';
end if;
when "0101" => -- ld(f|d)
falu_output <= falu_input;
falu_fps(3) <= falu_input(63);
if falu_input(62 downto 55) = "00000000" then
falu_fps(2) <= '1';
else
falu_fps(2) <= '0';
end if;
falu_fps(1 downto 0) <= "00"; -- set default for fps bits
falu_fsm <= falu_idle;
falu_done <= '1';
when "0111" => -- cmp(f|d)
falu_output <= falus_input;
falu_fps(3 downto 0) <= "0000"; -- set default for fps bits
if falu_input(63) = '1' and falus_input(63) = '0' then
falu_fps(3) <= '1';
elsif falu_input(63) = '0' and falus_input(63) = '0' then
if unsigned(falu_input(62 downto 55)) < unsigned(falus_input(62 downto 55)) then
falu_fps(3) <= '1';
elsif unsigned(falu_input(62 downto 55)) = unsigned(falus_input(62 downto 55)) then
if unsigned(falu_input(54 downto 0)) < unsigned(falus_input(54 downto 0)) then
falu_fps(3) <= '1';
elsif unsigned(falu_input(54 downto 0)) = unsigned(falus_input(54 downto 0)) then
falu_fps(2) <= '1';
else
-- n=0, z=0
end if;
else
-- n=0, z=0
end if;
elsif falu_input(63) = '1' and falus_input(63) = '1' then
if unsigned(falus_input(62 downto 55)) < unsigned(falu_input(62 downto 55)) then
falu_fps(3) <= '1';
elsif unsigned(falus_input(62 downto 55)) = unsigned(falu_input(62 downto 55)) then
if unsigned(falus_input(54 downto 0)) < unsigned(falu_input(54 downto 0)) then
falu_fps(3) <= '1';
elsif unsigned(falus_input(54 downto 0)) = unsigned(falu_input(54 downto 0)) then
falu_fps(2) <= '1';
else
-- n=0, z=0
end if;
else
-- n=0, z=0
end if;
end if;
if falu_input(62 downto 55) = "00000000" and falus_input(62 downto 55) = "00000000" then
falu_fps <= "0100";
falu_output <= (others => '0');
end if;
falu_fsm <= falu_idle;
falu_done <= '1';
when "1000" => -- st(f|d)
falu_output <= falu_input;
falu_fps <= fps(3 downto 0);
falu_fsm <= falu_idle;
falu_done <= '1';
when "1001" => -- div(f|d)
if falu_input(63) = falus_input(63) then -- set sign - positive if both operands are same sign, negative otherwise
falu_fps(3) <= '0';
else
falu_fps(3) <= '1';
end if;
falu_fps(2 downto 0) <= "000"; -- set default for other fps bits
falu_fsm <= falu_div;
falu_work1 <= (others => '0');
falu_work2 <= '0' & '1' & falus_input(54 downto 0) & '0' & '0';
if falus_input(62 downto 55) = "00000000" then -- check ac operand first, then if fsrc is zero, those settings will take precedence over these
falu_output <= (others => '0');
falu_fps <= "0100";
falu_fsm <= falu_idle;
falu_done <= '1';
end if;
if falu_input(62 downto 55) = "00000000" then
falu_pending_divz <= '1';
falu_output <= falus_input;
falu_fps <= fps(3 downto 0); -- the doc is unspecific... but xxdp jfpa seems to expect no updates to fps
falu_fsm <= falu_idle;
falu_done <= '1';
end if;
falu_ccw <= "0000111010";
when "1010" => -- stexp
falu_output(55 downto 48) <= falu_input(62 downto 55) - "10000000";
if unsigned(falu_input(62 downto 55)) < unsigned'("10000000") then
falu_fps(3) <= '1';
falu_output(63 downto 56) <= (others => '1');
else
falu_fps(3) <= '0';
falu_output(63 downto 56) <= (others => '0');
end if;
if falu_input(62 downto 55) = "10000000" then
falu_fps(2) <= '1';
else
falu_fps(2) <= '0';
end if;
falu_fps(1) <= '0';
falu_fps(0) <= '0';
falu_fsm <= falu_idle;
falu_done <= '1';
when "1011" => -- stc(f|d)(i|l)
falu_fsm <= falu_shift;
falu_fps(3) <= falu_input(63); -- n is set from input
falu_fps(2 downto 0) <= "000"; -- set default for other fps bits
falu_work1 <= (others => '0'); -- the idea to use work1 here is that synthesis may reuse the shifter we already have for it
if fps(6) = '0' then -- if short integer mode
falu_work1(58 downto 43) <= '1' & falu_input(54 downto 40);
falu_ccw <= unsigned'("0010010000") - unsigned("00" & falu_input(62 downto 55)); -- exponent minus the bias
else
if fps(7) = '0' then -- if in long integer mode, we need to check if we're in float mode, because then we can only copy 23 bits of fraction
falu_work1(58 downto 35) <= '1' & falu_input(54 downto 32);
else
falu_work1(58 downto 26) <= '1' & falu_input(54 downto 23);
end if;
if ir(5 downto 3) = "000" or ir(5 downto 0) = "010111" then -- reg or mode 2, reg 7
falu_ccw <= unsigned'("0010010000") - unsigned("00" & falu_input(62 downto 55)); -- exponent minus the bias
else
falu_ccw <= unsigned'("0010100000") - unsigned("00" & falu_input(62 downto 55)); -- exponent minus the bias
end if;
end if;
if unsigned(falu_input(62 downto 55)) < unsigned'("10000001") then -- it is not entirely clear in the manuals, but if the input is less than 1, the output is zero, and only the Z flag is set. It is not a conversion error!
falu_output <= (others => '0');
falu_fps(3) <= '0';
falu_fps(2) <= '1';
falu_fps(1) <= '0';
falu_fps(0) <= '0';
falu_fsm <= falu_idle;
falu_done <= '1';
end if;
when "1100" | "1111" => -- stc(f|d)(d|f), ldc(d|f)(f|d)
falu_fps(3) <= falu_input(63); -- n bit is in most cases a direct copy of the input
falu_output(63 downto 55) <= falu_input(63 downto 55); -- right in most cases
falu_fps(2 downto 0) <= "000"; -- set default for other fps bits
if falu_input(62 downto 55) = "00000000" then -- if the input exponent is zero, then the z bit in fps must be set
falu_fps(2) <= '1';
falu_fps(3) <= '0'; -- negative zero exp is ignored
falu_output <= (others => '0');
else
falu_fps(2) <= '0';
if (fps(7) = '0' and ir(11 downto 8) = "1100") or (fps(7) = '1' and ir(11 downto 8) = "1111") then -- convert to a double, or to a float?
falu_output(54 downto 32) <= falu_input(54 downto 32); -- just copy the high part if converting f to d
falu_output(31 downto 0) <= "00000000000000000000000000000000"; -- and set the low part to zeroes
else
if fps(5) = '1' then -- on d to f conversion, if round/trunc is trunc
falu_output(54 downto 32) <= falu_input(54 downto 32); -- just copy the high part
falu_output(31 downto 0) <= "00000000000000000000000000000000"; -- and set the low part to zeroes
else
if falu_input(62 downto 31) = "11111111111111111111111111111111" then -- this bit pattern causes overflow to occur
falu_output(62 downto 32) <= "0000000000000000000000000000000"; -- result after overflow is zeroes
falu_fps(2) <= '1'; -- set z bit, because of zeroes we just set!
falu_fps(1) <= '1'; -- set v bit to signal overflow
if fps(9) = '1' then -- if fiv enabled
falu_pending_fiv <= '1'; -- then signal the pending interrupt
end if;
else
falu_output(62 downto 31) <= falu_input(62 downto 31) + "1"; -- normal case, round bit added. Note that I count on normal arithmetic to handle increasing the exponent, if that is necessary to handle an overflow of the fraction part
end if;
falu_output(31 downto 0) <= "00000000000000000000000000000000"; -- in all cases, the low part is cleared
end if;
end if;
end if;
falu_fsm <= falu_idle;
falu_done <= '1';
when "1101" => -- ldexp
falu_output(63) <= falu_input(63); -- setup sign, in all cases a copy of the input
falu_output(54 downto 0) <= falu_input(54 downto 0); -- fraction is in all cases same as input
falu_fps(3) <= falu_input(63); -- setup n bit
falu_fps(2 downto 0) <= "000"; -- set default for other fps bits
if falus_input(55) = '1' then -- sign bit on, ie. is this a negative 2-complement integer
if falus_input(54 downto 47) = "11111111" -- if yes, then the next 8 bits need to be ones too, else it is an overflow
and falus_input(47 downto 40) /= "10000000" then -- would produce an overflow as well - special case
falu_output(62 downto 55) <= falus_input(47 downto 40) + "10000000"; -- not an overflow --> assign the new exponent, biased w. 200 oct
else
if fps(10) = '1' then -- if fiu enabled
falu_output(62 downto 55) <= falus_input(47 downto 40) + "10000000";
if falus_input(47 downto 40) + "10000000" = "00000000" then
falu_fps(2) <= '1';
end if;
falu_pending_fiu <= '1';
else
falu_output <= (others => '0'); -- if fiu disabled, just set the output to zeroes
falu_fps(2) <= '1'; -- and dont forget to set the z bit either
falu_fps(3) <= '0'; -- and also dont forget zero is not negative
end if;
end if;
else -- positive exponent
if falus_input(54 downto 47) = "00000000" then -- for a positive exponent, the high 8 bits must be clear, otherwise it is an overflow
falu_output(62 downto 55) <= falus_input(47 downto 40) + "10000000"; -- not overflow - assign new exponent biased w. 200 oct
else
falu_fps(1) <= '1'; -- v bit is set only when exponent > 177
if fps(9) = '1' then -- if fiv is enabled
falu_output(62 downto 55) <= falus_input(47 downto 40) + "10000000";
if falus_input(47 downto 40) + "10000000" = "00000000" then
falu_fps(2) <= '1';
end if;
falu_pending_fiv <= '1';
else -- if fiv is disabled
falu_output <= (others => '0'); -- set the output to all zeroes
falu_fps(2) <= '1'; -- set z bit as well
falu_fps(3) <= '0';
end if;
end if;
end if;
falu_fsm <= falu_idle;
falu_done <= '1';
when "1110" => -- ldc(i|l)(f|d)
falu_fsm <= falu_norm;
falu_fps(2 downto 0) <= "000"; -- set default for fps bits
if fps(6) = '0'
or ir(5 downto 3) = "000"
or ir(5 downto 0) = "010111" -- mode 2, reg 7 only
then
if fps(6) = '1' then -- if fl is set ie long mode, mode must be 0 or mode 2, reg 7, and the strange exception to use the single 16bit word as the upper applies.
falu_ccw <= "0010011111"; -- 37(8) or 31(10), max number of shifts for long mode; special case
else
falu_ccw <= "0010001111"; -- 17(8) or 15(10), max number of shifts for integer mode
end if;
falu_work1 <= (others => '0');
if falu_input(39) = '1' then
falu_fps(3) <= '1';
falu_work1(58 downto 43) <= (not falu_input(39 downto 24)) + 1;
else
falu_fps(3) <= '0';
falu_work1(58 downto 43) <= falu_input(39 downto 24);
end if;
else
falu_ccw <= "0010011111"; -- 37(8) or 31(10), max number of shifts for long mode
falu_work1 <= (others => '0');
if falu_input(55) = '1' then
falu_fps(3) <= '1';
falu_work1(58 downto 27) <= (not falu_input(55 downto 24)) + 1;
else
falu_fps(3) <= '0';
falu_work1(58 downto 27) <= falu_input(55 downto 24);
end if;
end if;
when others =>
null;
end case;
else
case falu_fsm is
-- multiply, ie. shifting and adding
-- this does not deal with the fd bit - all mult operations are full precision, regardless of the bit. The core
-- would be significantly faster for single prec if we would deal with the fd bit. FIXME!
when falu_mult =>
if falu_work2(57 downto 2) /= "00000000000000000000000000000000000000000000000000000000" then
if falu_work2(2) = '1' then -- if lowest order bit is a one
falu_work1 <= ('0' & falu_work1(58 downto 1) + ('0' & '1' & falu_input(54 downto 0) & "00")); -- then shift right and add
else
falu_work1 <= '0' & falu_work1(58 downto 1); -- if not set, then only shift right
end if;
falu_work2 <= '0' & falu_work2(58 downto 1); -- shift right for next round
else
falu_fsm <= falu_norm; -- if all bits done, then go into normalize state
end if;
-- align the operands for addition or subtraction
-- flag1 has which one of the operands needs to be shifted - and also, check the fd bit to see what the maximum value of the shift should be
-- falu_ccw has the difference - if it is 0, or shift- and decrement to 0, the addition/subtraction state is next up
when falu_align =>
if falu_ccw /= "0000000000" then
if falu_flag1 = '1' then
falu_work1 <= '0' & falu_work1(58 downto 1);
else
falu_work2 <= '0' & falu_work2(58 downto 1);
end if;
if fps(7) = '1' and unsigned(falu_ccw) > unsigned'("0000111001") then -- > 57 ??
falu_ccw <= "0000000000";
if falu_flag1 = '1' then
falu_work1 <= (others => '0');
else
falu_work2 <= (others => '0');
end if;
falu_fsm <= falu_addsub;
elsif fps(7) = '0' and unsigned(falu_ccw) > unsigned'("0000011001") then -- > 25 ??
falu_ccw <= "0000000000";
if falu_flag1 = '1' then
falu_work1 <= (others => '0');
else
falu_work2 <= (others => '0');
end if;
falu_fsm <= falu_addsub;
else
falu_ccw <= falu_ccw - 1;
end if;
else
falu_fsm <= falu_addsub;
end if;
when falu_addsub =>
-- this statement:
-- case ir(9) & falu_input(63) & falus_input(63) & falu_flag1 is
-- would be a nice and elegant way to express what I would like
-- alas, ISE cannot translate it. See:
-- AR #22098 - 8.2i XST-"ERROR:HDLParsers:818 - Cannot determine the type of the selector &"
v_caseworkaround := ir(9) & falu_input(63) & falus_input(63) & falu_flag1;
case v_caseworkaround is
when "0000" | "0001" => -- add, +|+
falu_work1 <= falu_work1 + falu_work2;
falu_fps(3) <= '0';
when "0100" => -- add, !work1<work2, -|+
falu_work1 <= falu_work1 - falu_work2;
falu_fps(3) <= '1';
when "0101" => -- add, work1<work2, -|+
falu_work1 <= falu_work2 - falu_work1;
falu_fps(3) <= '0';
when "0010" => -- add, !work1<work2, +|-
falu_work1 <= falu_work1 - falu_work2;
falu_fps(3) <= '0';
when "0011" => -- add, work1<work2, +|-
falu_work1 <= falu_work2 - falu_work1;
falu_fps(3) <= '1';
when "0110" | "0111" => -- add, -|-
falu_work1 <= falu_work1 + falu_work2;
falu_fps(3) <= '1';
when "1000" => -- sub, !work1<work2, +|+
falu_work1 <= falu_work1 - falu_work2;
falu_fps(3) <= '1';
when "1001" => -- sub, work1<work2, +|+
falu_work1 <= falu_work2 - falu_work1;
falu_fps(3) <= '0';
when "1100" | "1101" => -- sub, -|+
falu_work1 <= falu_work2 + falu_work1;
falu_fps(3) <= '0';
when "1010" | "1011" => -- sub, +|-
falu_work1 <= falu_work2 + falu_work1;
falu_fps(3) <= '1';
when "1110" => -- sub, !work1<work2, -|-
falu_work1 <= falu_work1 - falu_work2;
falu_fps(3) <= '0';
when "1111" => -- sub, work1<work2, -|-
falu_work1 <= falu_work2 - falu_work1;
falu_fps(3) <= '1';
when others =>
null;
end case;
if falu_flag1 = '1' then
falu_ccw <= "00" & falus_input(62 downto 55);
else
falu_ccw <= "00" & falu_input(62 downto 55);
end if;
falu_fsm <= falu_norm;
when falu_div =>
if unsigned(falu_work2) >= unsigned('0' & '1' & falu_input(54 downto 0) & "00") then
falu_work1 <= falu_work1(57 downto 0) & '1';
falu_work2 <= unsigned(falu_work2(57 downto 0) & '0') - unsigned('1' & falu_input(54 downto 0) & "000");
else
falu_work1 <= falu_work1(57 downto 0) & '0';
falu_work2 <= falu_work2(57 downto 0) & '0';
end if;
if falu_ccw /= "0000000000" then
falu_ccw <= falu_ccw - 1;
else
falu_fsm <= falu_norm;
falu_ccw <= unsigned("00" & falus_input(62 downto 55)) - unsigned("00" & falu_input(62 downto 55)) + unsigned'("0010000000");
end if;
when falu_shift =>
if falu_ccw /= "0000000000" then
falu_work1 <= '0' & falu_work1(58 downto 1);
falu_ccw <= falu_ccw - 1;
else
falu_output <= (others => '0');
if falu_input(63) = '1' then
falu_output(63 downto 32) <= (not falu_work1(58 downto 27)) + 1;
else
falu_output(63 downto 32) <= falu_work1(58 downto 27);
end if;
falu_fsm <= falu_shift2;
end if;
if fps(6) = '0' then
if unsigned(falu_ccw) > unsigned'("0000001111") then
falu_fsm <= falu_shifte;
end if;
else
if unsigned(falu_ccw) > unsigned'("0000011111") then
falu_fsm <= falu_shifte;
end if;
end if;
when falu_shift2 =>
if falu_output(63 downto 48) = "0000000000000000" then
if fps(6) = '0' then
falu_fps(3) <= '0';
falu_fps(2) <= '1';
else
if falu_output(47 downto 32) = "0000000000000000" then
falu_fps(3) <= '0';
falu_fps(2) <= '1';
end if;
end if;
end if;
if falu_output(63) /= falu_input(63) then
falu_fsm <= falu_shifte;
else
falu_fsm <= falu_idle;
falu_done <= '1';
end if;
when falu_shifte =>
falu_fps(3) <= '0'; -- on error, result is not negative
falu_fps(2) <= '1';
falu_fps(1) <= '0'; -- V bit is not used
falu_fps(0) <= '1';
falu_output <= (others => '0');
if fps(8) = '1' then
falu_pending_fic <= '1';
end if;
falu_fsm <= falu_idle;
falu_done <= '1';
when falu_norm =>
if falu_work1(58 downto 57) = "01" then -- hidden bit in the right place, overflow bit clear?
if ir(11 downto 8) = "0011" then
falu_fsm <= falu_sep;
else
falu_fsm <= falu_rt;
end if;
elsif falu_work1(58) = '1' then -- is the overflow bit set?
falu_work1 <= '0' & falu_work1(58 downto 1); -- shift right
falu_ccw <= falu_ccw + 1; -- increase exponent
if ir(11 downto 8) = "0011" then
falu_fsm <= falu_sep;
else
falu_fsm <= falu_rt;
end if;
else
-- 76543210987654321098765432109876543210987654321098765432
if falu_work1(57 downto 2) /= "00000000000000000000000000000000000000000000000000000000" then
falu_work1 <= falu_work1(57 downto 0) & '0'; -- shift left
falu_ccw <= falu_ccw - 1; -- decrease exponent
else -- coming here, we have lost all ones from the fraction; the output is zero
falu_fps(3) <= '0'; -- make sure that the n bit is cleared
falu_fsm <= falu_zres; -- result is zero
end if;
end if;
when falu_sep =>
if signed(falu_ccw) <= signed'("0010000000") then
falu_output2 <= (others => '0');
falu_fsm <= falu_rt;
elsif (signed(falu_ccw) > signed'("0010011000") and fps(7) = '0') or (signed(falu_ccw) > signed'("0010111000") and fps(7) = '1') then
falu_fsm <= falu_sep3;
else
falu_output2(63) <= falu_fps(3);
falu_output2(62 downto 55) <= falu_ccw(7 downto 0);
falu_output2(54 downto 0) <= falu_work1(56 downto 2);
falu_fsm <= falu_sep2;
falu_work2 <= (others => '0');
falu_work2(58 downto 57) <= "10";
end if;
when falu_sep2 =>
if signed(falu_ccw) > signed'("0010000000") then
falu_work1 <= falu_work1(57 downto 0) & '0'; -- shift left
falu_work2 <= '1' & falu_work2(58 downto 1); -- shift right
falu_ccw <= falu_ccw - 1;
elsif falu_work1(57) /= '1' and falu_ccw /= "0000000000" then
falu_work1 <= falu_work1(57 downto 0) & '0'; -- shift left
falu_ccw <= falu_ccw - 1;
if falu_work1(57 downto 2) = "00000000000000000000000000000000000000000000000000000000" then
falu_ccw <= "0000000000";
end if;
else
falu_output2(54 downto 0) <= falu_output2(54 downto 0) and falu_work2(56 downto 2);
falu_fsm <= falu_res;
if falu_ccw = "0000000000" then
falu_fsm <= falu_zres; -- zero result handled directly, because res would wrongly raise an underflow
end if;
end if;
when falu_sep3 =>
falu_output <= (others => '0'); -- set fraction output to zero
falu_fps(3) <= '0'; -- if the fraction is zero, so is its sign
falu_fps(2) <= '1'; -- set z for fraction
falu_output2(63) <= falu_fps(3);
falu_output2(62 downto 55) <= falu_ccw(7 downto 0);
falu_output2(54 downto 0) <= falu_work1(56 downto 2);
if falu_ccw(8) = '1' and falu_ccw(9) /= '1' then -- overflow?
falu_fps(1) <= '1'; -- set the flag
if fps(9) = '1' then -- are overflow traps enabled?
falu_pending_fiv <= '1'; -- yes, set flag
else
falu_output2 <= (others => '0');
end if;
end if;
falu_done <= '1';
falu_fsm <= falu_idle;
when falu_rt =>
if fps(5) = '0' then
if fps(7) = '0' then
-- 87654321098765432109876543 210987654321098765432109876543210
falu_work1 <= (unsigned(falu_work1(58 downto 33)) + unsigned'("00000000000000000000000001")) & "000000000000000000000000000000000";
else
falu_work1 <= falu_work1 + "10";
end if;
end if;
falu_fsm <= falu_rtc;
when falu_rtc =>
if falu_work1(58) = '1' then
falu_work1 <= '0' & falu_work1(58 downto 1);
falu_ccw <= falu_ccw + 1;
end if;
falu_fsm <= falu_res;
when falu_res =>
falu_output(63) <= falu_fps(3);
falu_output(62 downto 55) <= falu_ccw(7 downto 0);
falu_output(54 downto 0) <= falu_work1(56 downto 2);
falu_done <= '1';
falu_fsm <= falu_idle;
if falu_ccw(7 downto 0) = "00000000" then
falu_fps(2) <= '1';
else
falu_fps(2) <= '0';
end if;
if falu_ccw(9) = '1' or falu_ccw(9 downto 0) = "0000000000" then
if fps(10) = '1' then -- are underflow traps enabled?
falu_pending_fiu <= '1'; -- yes, set flag
else
falu_fsm <= falu_zres; -- traps are not enabled, output is zero
end if;
elsif falu_ccw(8) = '1' then
falu_fps(1) <= '1'; -- set the flag
if fps(9) = '1' then -- are overflow traps enabled?
falu_pending_fiv <= '1'; -- yes, set flag
else
falu_fsm <= falu_zres; -- traps are not enabled, output is zero
end if;
end if;
when falu_zres =>
falu_output <= (others => '0');
falu_fps(3) <= '0';
falu_fps(2) <= '1';
falu_fps(0) <= '0';
falu_done <= '1';
falu_fsm <= falu_idle;
when falu_idle =>
falu_done <= '0';
falu_ccw <= (others => '0');
falu_work1 <= (others => '0');
falu_work2 <= (others => '0');
falu_flag1 <= '0';
when others =>
null;
end case;
end if;
elsif ir_fpsop2 = '1' then
case ir(7 downto 6) is
when "00" => -- clr(f/d)
falu_output <= (others => '0');
falu_fps(3 downto 0) <= "0100";
when "01" => -- tst(f/d)
falu_output <= falu_input;
if falu_input(62 downto 55) = "00000000" then
falu_fps(2) <= '1';
falu_output <= (others => '0');
else
falu_fps(2) <= '0';
end if;
falu_fps(3) <= falu_input(63);
falu_fps(1) <= '0';
falu_fps(0) <= '0';
when "10" => -- abs(f/d)
falu_output <= '0' & falu_input(62 downto 0);
if falu_input(62 downto 55) = "00000000" then
falu_fps(2) <= '1';
falu_output <= (others => '0');
else
falu_fps(2) <= '0';
end if;
falu_fps(3) <= '0';
falu_fps(1) <= '0';
falu_fps(0) <= '0';
when "11" => -- neg(f/d)
if falu_input(63) = '0' then
falu_output <= '1' & falu_input(62 downto 0);
falu_fps(3) <= '1';
else
falu_output <= '0' & falu_input(62 downto 0);
falu_fps(3) <= '0';
end if;
if falu_input(62 downto 55) = "00000000" then
falu_output <= (others => '0');
falu_fps(2) <= '1';
falu_fps(3) <= '0';
else
falu_fps(2) <= '0';
end if;
falu_fps(1) <= '0';
falu_fps(0) <= '0';
when others =>
falu_output <= (others => 'X');
falu_fps(3 downto 0) <= "XXXX";
end case;
falu_output2 <= (others => 'X');
else
falu_output <= (others => 'X');
falu_output2 <= (others => 'X');
falu_fps(3 downto 0) <= "XXXX";
end if;
end if;
end if;
end process;
end implementation;
| gpl-3.0 | 4e427fc8a8527d1bc59c3315b0d725df | 0.388911 | 4.512074 | false | false | false | false |
hoglet67/CoPro6502 | src/T80/SSRAM.vhd | 2 | 3,030 | --
-- Inferrable Synchronous SRAM for XST synthesis
--
-- Version : 0220
--
-- Copyright (c) 2002 Daniel Wallner ([email protected])
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
-- http://www.opencores.org/cvsweb.shtml/t51/
--
-- Limitations :
--
-- File history :
-- 0208 : Initial release
-- 0218 : Fixed data out at write
-- 0220 : Added support for XST
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity SSRAM is
generic(
AddrWidth : integer := 11;
DataWidth : integer := 8
);
port(
Clk : in std_logic;
CE_n : in std_logic;
WE_n : in std_logic;
A : in std_logic_vector(AddrWidth - 1 downto 0);
DIn : in std_logic_vector(DataWidth - 1 downto 0);
DOut : out std_logic_vector(DataWidth - 1 downto 0)
);
end SSRAM;
architecture behaviour of SSRAM is
type Memory_Image is array (natural range <>) of std_logic_vector(DataWidth - 1 downto 0);
signal RAM : Memory_Image(0 to 2 ** AddrWidth - 1);
signal A_r : std_logic_vector(AddrWidth - 1 downto 0);
begin
process (Clk)
begin
if Clk'event and Clk = '1' then
if (CE_n nor WE_n) = '1' then
RAM(to_integer(unsigned(A))) <= DIn;
end if;
A_r <= A;
end if;
end process;
DOut <= RAM(to_integer(unsigned(A_r)))
-- pragma translate_off
when not is_x(A_r) else (others => '-')
-- pragma translate_on
;
end;
| gpl-3.0 | 34fc66bf22e9e8138f7aadededc3f68f | 0.719802 | 3.677184 | false | false | false | false |
EliasLuiz/TCC | Leon3/lib/gaisler/ddr/ddr2spax_ddr.vhd | 1 | 53,332 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: ddr2spax
-- File: ddr2spax.vhd
-- Author: Magnus Hjorth - Aeroflex Gaisler
-- Description: DDR2 memory controller with asynch AHB interface
-- Based on ddr2sp(16/32/64)a, generalized and expanded
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library grlib;
use grlib.stdlib.all;
use grlib.amba.all;
use grlib.devices.all;
library gaisler;
use gaisler.ddrpkg.all;
use gaisler.ddrintpkg.all;
entity ddr2spax_ddr is
generic (
ddrbits : integer := 32;
burstlen : integer := 8;
MHz : integer := 100;
TRFC : integer := 130;
col : integer := 9;
Mbyte : integer := 8;
pwron : integer := 0;
oepol : integer := 0;
readdly : integer := 1;
odten : integer := 0;
octen : integer := 0;
-- dqsgating : integer := 0;
nosync : integer := 0;
dqsgating : integer := 0;
eightbanks : integer range 0 to 1 := 0; -- Set to 1 if 8 banks instead of 4
dqsse : integer range 0 to 1 := 0; -- single ended DQS
ddr_syncrst: integer range 0 to 1 := 0;
chkbits : integer := 0;
bigmem : integer range 0 to 1 := 0;
raspipe : integer range 0 to 1 := 0;
hwidthen : integer range 0 to 1 := 0;
phytech : integer := 0;
hasdqvalid : integer := 0;
rstdel : integer := 200;
phyptctrl : integer := 0;
scantest : integer := 0;
dis_caslat : integer := 0;
dis_init : integer := 0;
cke_rst : integer := 0
);
port (
ddr_rst : in std_ulogic;
clk_ddr : in std_ulogic;
request : in ddr_request_type;
start_tog: in std_logic;
response : out ddr_response_type;
sdi : in ddrctrl_in_type;
sdo : out ddrctrl_out_type;
wbraddr : out std_logic_vector(log2((16*burstlen)/ddrbits) downto 0);
wbrdata : in std_logic_vector(2*(ddrbits+chkbits)-1 downto 0);
rbwaddr : out std_logic_vector(log2((16*burstlen)/ddrbits)-1 downto 0);
rbwdata : out std_logic_vector(2*(ddrbits+chkbits)-1 downto 0);
rbwrite : out std_logic;
hwidth : in std_ulogic;
reqsel : in std_ulogic;
frequest : in ddr_request_type;
response2: out ddr_response_type;
testen : in std_ulogic;
testrst : in std_ulogic;
testoen : in std_ulogic
);
end ddr2spax_ddr;
architecture rtl of ddr2spax_ddr is
constant CMD_PRE : std_logic_vector(2 downto 0) := "010";
constant CMD_REF : std_logic_vector(2 downto 0) := "100";
constant CMD_LMR : std_logic_vector(2 downto 0) := "110";
constant CMD_EMR : std_logic_vector(2 downto 0) := "111";
function tosl(x: integer) return std_logic is
begin
if x /= 0 then return '1'; else return '0'; end if;
end tosl;
function zerov(w: integer) return std_logic_vector is
constant r: std_logic_vector(w-1 downto 0) := (others => '0');
begin
return r;
end zerov;
constant l2blen: integer := log2(burstlen)+log2(32);
constant l2ddrw: integer := log2(ddrbits*2);
constant oepols: std_logic := tosl(oepol);
-- Write buffer dimensions
-- Write buffer is addressable down to 32-bit level on write (AHB) side.
constant wbuf_rabits: integer := 1+l2blen-l2ddrw; -- log2((burstlen*32)/(2*ddrbits));
constant wbuf_rdbits: integer := 2*ddrbits;
-- Read buffer dimensions
constant rbuf_wabits: integer := l2blen-l2ddrw; -- log2((burstlen*32)/(2*ddrbits));
constant rbuf_wdbits: integer := 2*(ddrbits+chkbits);
-- sdram configuration register
type sdram_cfg_type is record
command : std_logic_vector(2 downto 0);
csize : std_logic_vector(1 downto 0);
bsize : std_logic_vector(3 downto 0);
trcd : std_logic_vector(2 downto 0); -- tRCD : 2-9 clock cycles
trfc : std_logic_vector(7 downto 0);
trp : std_logic_vector(2 downto 0); -- precharge to activate: 2-9 clock cycles
refresh : std_logic_vector(11 downto 0);
renable : std_ulogic;
dllrst : std_ulogic;
refon : std_ulogic;
cke : std_ulogic;
cal_en : std_logic_vector(7 downto 0);
cal_inc : std_logic_vector(7 downto 0);
cbcal_en : std_logic_vector(3 downto 0);
cbcal_inc : std_logic_vector(3 downto 0);
cal_pll : std_logic_vector(1 downto 0); -- *** ??? pll_reconf
cal_rst : std_logic;
readdly : std_logic_vector(3 downto 0);
twr : std_logic_vector(4 downto 0);
emr : std_logic_vector(1 downto 0); -- selects EM register
ocd : std_ulogic; -- enable/disable ocd
dqsctrl : std_logic_vector(7 downto 0);
eightbanks : std_ulogic;
caslat : std_logic_vector(1 downto 0); -- CAS latency 3-6
odten : std_logic_vector(1 downto 0);
tras : std_logic_vector(4 downto 0); -- RAS-to-Precharge minimum
trtp : std_ulogic;
regmem : std_ulogic; -- Registered memory (1 cycle extra latency)
strength : std_ulogic; -- Drive strength 1=reduced, 0=normal
end record;
constant ddr_burstlen: integer := (burstlen*32)/(2*ddrbits);
constant l2ddr_burstlen: integer := l2blen-l2ddrw;
type ddrstate is (dsidle,dsrascas,dscaslat,dsreaddly,dsdata,dsdone,dsagain,dsreg,dsrefresh,dspreall);
type ddrcmdstate is (dcrstdel,dcoff,dcinit1,dcinit2,dcinit3,dcinit4,dcinit5,dcinit6,dcinit7,dcinit8,dcon);
type ddr_reg_type is record
s : ddrstate;
cmds : ddrcmdstate;
response : ddr_response_type;
response1 : ddr_response_type;
response2 : ddr_response_type;
response_prev : ddr_response_type;
cfg : sdram_cfg_type;
rowsel : std_logic_vector(2 downto 0);
endaddr : std_logic_vector(l2blen-4 downto 2);
addrlo : std_logic_vector(l2ddrw-4 downto 0);
col : std_logic_vector(13 downto 0);
hwrite : std_logic;
hsize : std_logic_vector(2 downto 0);
ctr : std_logic_vector(7 downto 0);
casctr : std_logic_vector(l2ddr_burstlen-1 downto 0);
datacas : std_logic;
prectr : std_logic_vector(5 downto 0);
rastimer : std_logic_vector(4 downto 0);
tras_met : std_logic;
pchpend : std_logic;
refctr : std_logic_vector(16 downto 0);
refpend : std_logic;
pastlast : std_logic;
sdo_csn : std_logic_vector(1 downto 0);
sdo_wen : std_ulogic;
wen_prev : std_ulogic;
sdo_rasn : std_ulogic;
rasn_pre : std_ulogic;
sdo_casn : std_ulogic;
sdo_dqm : std_logic_vector(15 downto 0);
dqm_prev : std_logic_vector(15 downto 0);
twr_plus_cl : std_logic_vector(5 downto 0);
request_row : std_logic_vector(14 downto 0);
request_bank : std_logic_vector(2 downto 0);
request_cs : std_logic_vector(0 downto 0);
row : std_logic_vector(14 downto 0);
setrow : std_logic;
samerow : std_logic;
start_tog_prev: std_logic;
sdo_bdrive : std_ulogic;
sdo_qdrive : std_ulogic;
sdo_nbdrive : std_ulogic;
sdo_address : std_logic_vector(14 downto 0);
sdo_address_prev: std_logic_vector(14 downto 0);
sdo_ba : std_logic_vector(2 downto 0);
sdo_data : std_logic_vector(sdo.data'length-1 downto 0);
sdo_cb : std_logic_vector(sdo.cb'length-1 downto 0);
sdo_odt : std_logic;
sdo_oct : std_logic;
rbwrite : std_logic;
rbwdata : std_logic_vector(rbuf_wdbits-1 downto 0);
ramaddr : std_logic_vector(rbuf_wabits-1 downto 0);
ramaddr_prev : std_logic_vector(rbuf_wabits-1 downto 0);
mr_twr : std_logic_vector(2 downto 0);
mr_tcl : std_logic_vector(2 downto 0);
read_pend : std_logic_vector(15 downto 0);
req1,req2 : ddr_request_type;
start1,start2 : std_logic;
hwidth1 : std_logic;
hwidth : std_logic;
hwcas : std_logic;
hwctr : std_logic;
end record;
signal dr,ndr : ddr_reg_type;
signal muxsel2,muxsel1,muxsel0: std_ulogic;
signal muxin4: std_logic_vector(31 downto 0);
signal muxout4: std_logic_vector(3 downto 0);
signal start_tog_delta1,start_tog_delta2: std_logic;
signal arst: std_ulogic;
attribute syn_keep: boolean;
attribute syn_keep of muxsel2:signal is true;
attribute syn_keep of muxsel1:signal is true;
attribute syn_keep of muxsel0:signal is true;
begin
arst <= testrst when (scantest/=0 and ddr_syncrst=0) and testen='1' else ddr_rst;
start_tog_delta1 <= start_tog;
start_tog_delta2 <= start_tog_delta1;
muxsel2 <= dr.rowsel(2);
muxsel1 <= dr.rowsel(1);
muxsel0 <= dr.rowsel(0);
muxproc : process(muxin4,muxsel2,muxsel1,muxsel0)
begin
muxout4(3) <= genmux((muxsel2 & muxsel1 & muxsel0),muxin4(31 downto 24));
muxout4(2) <= genmux((muxsel2 & muxsel1 & muxsel0),muxin4(23 downto 16));
muxout4(1) <= genmux((muxsel2 & muxsel1 & muxsel0),muxin4(15 downto 8));
muxout4(0) <= genmux((muxsel2 & muxsel1 & muxsel0),muxin4(7 downto 0));
end process;
ddrcomb : process(ddr_rst,sdi,request,frequest,start_tog_delta2,dr,wbrdata,muxout4,hwidth,reqsel,testen,testoen)
constant plmemwrite: boolean := false;
constant plmemread: boolean := false;
variable dv: ddr_reg_type;
variable o: ddrctrl_out_type;
variable bdrive,qdrive: std_logic;
variable vreq,vreqf: ddr_request_type;
variable resp,resp2: ddr_response_type;
variable vstart: std_logic;
variable acsn: std_logic_vector(1 downto 0);
variable arow: std_logic_vector(14 downto 0);
variable acol: std_logic_vector(13 downto 0);
variable abank: std_logic_vector(2 downto 0);
variable aendaddr: std_logic_vector(l2blen-4 downto 2);
variable aloa: std_logic_vector(l2ddrw-4 downto 0);
variable rbw: std_logic;
variable rbwd: std_logic_vector(rbuf_wdbits-1 downto 0);
variable rbwa: std_logic_vector(rbuf_wabits-1 downto 0);
variable wbra: std_logic_vector(wbuf_rabits-1 downto 0);
variable regdata: std_logic_vector(31 downto 0);
variable regsd1 : std_logic_vector(31 downto 0); -- data from registers
variable regsd2 : std_logic_vector(31 downto 0); -- data from registers
variable regsd3 : std_logic_vector(31 downto 0); -- data from registers
variable regsd4 : std_logic_vector(31 downto 0); -- data from registers
variable regsd5 : std_logic_vector(31 downto 0); -- data from registers
variable mr : std_logic_vector(14 downto 0); -- DDR2 Mode register
variable mask: std_logic_vector(15 downto 0);
variable hio1: std_logic;
variable w5: std_logic;
variable precharge_next: std_logic;
variable precharge_notras: std_logic;
variable goto_caslat: std_logic;
variable block_precharge: std_logic;
variable regt0,regt1: std_logic_vector(ddrbits-1 downto 0);
variable addrtemp3,addrtemp2,addrtemp1,addrtemp0: std_logic_vector(7 downto 0);
variable expcsize: std_logic_vector(2 downto 0);
variable caslat_reg: std_logic_vector(2 downto 0);
variable addrlo32, endaddr32: std_logic_vector(3 downto 2);
variable endaddr43: std_logic_vector(4 downto 3);
variable endaddr42: std_logic_vector(4 downto 2);
variable inc_rctr: std_logic;
begin
dv := dr;
o := ddrctrl_out_none;
o.sdcke := (others => dr.cfg.cke);
o.sdcsn := dr.sdo_csn;
o.sdwen := dr.wen_prev;
o.rasn := dr.sdo_rasn and dr.rasn_pre;
o.casn := dr.sdo_casn and dr.datacas;
o.dqm := dr.dqm_prev;
o.bdrive := dr.sdo_bdrive;
o.qdrive := dr.sdo_qdrive;
o.nbdrive := dr.sdo_nbdrive;
o.address := dr.sdo_address;
o.data := dr.sdo_data;
o.ba := dr.sdo_ba;
o.cal_en := dr.cfg.cal_en;
o.cal_inc := dr.cfg.cal_inc;
o.cal_pll := dr.cfg.cal_pll;
o.cal_rst := dr.cfg.cal_rst;
o.odt := (others => dr.sdo_odt);
o.oct := dr.sdo_oct;
o.cb := dr.sdo_cb;
o.cbcal_en := dr.cfg.cbcal_en;
o.cbcal_inc := dr.cfg.cbcal_inc;
resp := ddr_response_none;
resp2 := ddr_response_none;
rbw := dr.rbwrite;
rbwd := dr.rbwdata;
rbwa := (others => '0');
w5 := '0';
wbra := dr.response.done_tog & dr.ramaddr;
dv.ramaddr_prev := dr.ramaddr;
dv.dqm_prev := dr.sdo_dqm;
dv.wen_prev := dr.sdo_wen;
dv.response_prev := dr.response;
dv.sdo_address_prev := dr.sdo_address;
dv.cfg.cal_en := (others => '0');
dv.cfg.cal_inc := (others => '0');
dv.cfg.cal_pll := (others => '0');
dv.cfg.cal_rst := '0';
dv.cfg.cbcal_en := (others => '0');
dv.cfg.cbcal_inc := (others => '0');
dv.sdo_data := (others => '0');
dv.sdo_data(2*ddrbits-1 downto ddrbits) := wbrdata(2*ddrbits+chkbits-1 downto ddrbits+chkbits);
dv.sdo_data(ddrbits-1 downto 0) := wbrdata(ddrbits-1 downto 0);
dv.sdo_cb := (others => '0');
if chkbits > 0 then
dv.sdo_cb(2*chkbits-1 downto chkbits) := wbrdata(2*ddrbits+2*chkbits-1 downto 2*ddrbits+chkbits);
dv.sdo_cb(chkbits-1 downto 0) := wbrdata(ddrbits+chkbits-1 downto ddrbits);
end if;
if hwidthen/=0 and dr.hwidth='1' and dr.hwctr='1' then
dv.sdo_data(ddrbits-1 downto 0) := dr.sdo_data(2*ddrbits-1 downto ddrbits);
if chkbits > 0 then
dv.sdo_cb(chkbits-1 downto 0) := dr.sdo_cb(2*chkbits-1 downto chkbits);
end if;
end if;
if not (hwidthen/=0 and hasdqvalid/=0 and sdi.datavalid='0') then
dv.rbwdata(2*ddrbits+chkbits-1 downto ddrbits+chkbits) := sdi.data(2*ddrbits-1 downto ddrbits);
dv.rbwdata(ddrbits-1 downto 0) := sdi.data(ddrbits-1 downto 0);
if chkbits > 0 then
dv.rbwdata(2*ddrbits+2*chkbits-1 downto 2*ddrbits+chkbits) := sdi.cb(2*chkbits-1 downto chkbits);
dv.rbwdata(ddrbits+chkbits-1 downto ddrbits) := sdi.cb(chkbits-1 downto 0);
end if;
-- Half-width input data muxing
if hwidthen/=0 and dr.hwidth='1' and dr.hwctr='1' then
dv.rbwdata(2*ddrbits+chkbits-1 downto 2*ddrbits+chkbits-ddrbits/2) :=
dr.rbwdata(2*ddrbits+chkbits-ddrbits/2-1 downto ddrbits+chkbits);
dv.rbwdata(2*ddrbits+chkbits-ddrbits/2-1 downto ddrbits+chkbits) :=
dr.rbwdata(ddrbits/2-1 downto 0);
dv.rbwdata(ddrbits-1 downto ddrbits/2) :=
sdi.data(ddrbits+ddrbits/2-1 downto ddrbits);
if chkbits > 0 then
dv.rbwdata(2*ddrbits+2*chkbits-1 downto 2*ddrbits+2*chkbits-chkbits/2) :=
dr.rbwdata(2*ddrbits+2*chkbits-chkbits/2-1 downto 2*ddrbits+chkbits);
dv.rbwdata(2*ddrbits+2*chkbits-chkbits/2-1 downto 2*ddrbits+chkbits) :=
dr.rbwdata(ddrbits+chkbits/2-1 downto ddrbits);
dv.rbwdata(ddrbits+chkbits-1 downto ddrbits+chkbits/2) :=
sdi.cb(chkbits+chkbits/2-1 downto chkbits);
end if;
end if;
end if;
-- hwidth input should be constant but sample it for robustness
-- then sample in one more stage to allow replication if necessary
dv.hwidth1 := hwidth;
dv.hwidth := dr.hwidth1;
if hwidthen=0 then dv.hwidth:='0'; end if;
-- Synchronize 1/2 stages
dv.req1 := request; dv.req2 := dr.req1;
dv.start1 := start_tog_delta2; dv.start2 := dr.start1;
vstart := dr.start2;
vreq := dr.req2;
vreqf := dr.req1;
if nosync /= 0 then vstart:=start_tog_delta2; vreq:=request; vreqf:=request; end if;
if nosync > 1 then vreqf:=frequest; end if;
dv.start_tog_prev := vstart;
regsd1 := (others => '0');
regsd1(31 downto 15) := dr.cfg.refon & dr.cfg.ocd & dr.cfg.emr & dr.cfg.bsize(3) & dr.cfg.trcd(0) &
dr.cfg.bsize(2 downto 0) & dr.cfg.csize & dr.cfg.command &
dr.cfg.dllrst & dr.cfg.renable & dr.cfg.cke;
regsd1(11 downto 0) := dr.cfg.refresh;
regsd2 := (others => '0');
regsd2(25 downto 18) := std_logic_vector(to_unsigned(phytech,8));
if bigmem /= 0 then regsd2(17):='1'; end if;
if chkbits > 0 then regsd2(16):='1'; end if;
regsd2(15 downto 0) := "1" &
std_logic_vector(to_unsigned(log2(ddrbits/8),3)) &
std_logic_vector(to_unsigned(MHz,12));
if dr.hwidth='1' then
regsd2(14 downto 12) := std_logic_vector(to_unsigned(log2((ddrbits/2)/8),3));
end if;
regsd3 := (others => '0');
regsd3(17 downto 16) := dr.cfg.readdly(1 downto 0);
regsd3(22 downto 18) := dr.cfg.trfc(4 downto 0);
regsd3(27 downto 23) := dr.cfg.twr;
regsd3(28) := dr.cfg.trp(0);
regsd4 := (others => '0');
regsd4(23 downto 22) := dr.cfg.readdly(3 downto 2);
regsd4(21) := dr.cfg.regmem;
regsd4(13 downto 0) := dr.cfg.trtp & "00" & dr.cfg.caslat &
dr.cfg.eightbanks & dr.cfg.dqsctrl;
regsd5 := (others => '0');
regsd5(30 downto 28) := dr.cfg.trp;
regsd5(25 downto 18) := dr.cfg.trfc;
regsd5(17 downto 16) := dr.cfg.odten;
regsd5(15) := dr.cfg.strength;
regsd5(10 downto 8) := dr.cfg.trcd;
regsd5(4 downto 0) := dr.cfg.tras;
case ddrbits is
when 16 => o.regwdata := dr.sdo_data(31 downto 0) & dr.sdo_data(31 downto 0);
when 32 => o.regwdata := dr.sdo_data(31 downto 0) & dr.sdo_data(63 downto 32);
when 64 => o.regwdata := dr.sdo_data(31 downto 0) & dr.sdo_data(63 downto 32);
when others => o.regwdata := dr.sdo_data(2*ddrbits-7*32-1 downto 2*ddrbits-8*32) &
dr.sdo_data(2*ddrbits-6*32-1 downto 2*ddrbits-7*32);
end case;
if dr.cfg.regmem='1' then
caslat_reg := std_logic_vector(unsigned('0' & dr.cfg.caslat)+1);
else
caslat_reg := '0' & dr.cfg.caslat;
end if;
-- Mode register
dv.mr_twr := std_logic_vector(unsigned(dr.cfg.twr(2 downto 0))-3);
if dv.mr_twr="110" or dv.mr_twr="111" or dv.mr_twr="000" then
dv.mr_twr := "101";
end if;
dv.mr_tcl := std_logic_vector(unsigned('0' & dr.cfg.caslat)+3);
mr := (others => '0');
mr(12) := '0'; -- Power down exit time
mr(11 downto 9) := dr.mr_twr; -- WR-1
mr(8) := dr.cfg.dllrst; -- DLL Reset
mr(7) := '0'; -- Test mode
mr(6 downto 4) := dr.mr_tcl; -- CL
mr(3) := '0'; -- Burst type, 0=seq 1=interl
mr(2 downto 0) := "010"; -- Burst len 010=4, 011=8
-- Calculate address parts from a2ds.haddr and a2ds.startword
expcsize := dr.hwidth & dr.cfg.csize;
case expcsize is
when "011" => arow := vreqf.startaddr(l2ddrw+22 downto l2ddrw+8);
when "111" | "010" => arow := vreqf.startaddr(l2ddrw+21 downto l2ddrw+7);
when "110" | "001" => arow := vreqf.startaddr(l2ddrw+20 downto l2ddrw+6);
when "101" | "000" => arow := vreqf.startaddr(l2ddrw+19 downto l2ddrw+5);
when others => arow := vreqf.startaddr(l2ddrw+18 downto l2ddrw+4);
end case;
dv.rowsel := dr.cfg.bsize(2 downto 0);
if bigmem /= 0 and dr.cfg.bsize(3 downto 1)="000" then
dv.rowsel := "010";
end if;
if bigmem = 0 and dr.cfg.bsize(3)='1' then
dv.rowsel := "111";
end if;
addrtemp3 := vreqf.startaddr(30 downto 23); --CS
addrtemp2 := vreqf.startaddr(29 downto 22); --BA2/1
addrtemp1 := vreqf.startaddr(28 downto 21); --BA1/0
addrtemp0 := vreqf.startaddr(27 downto 20); --BA0/-
if bigmem=1 then
addrtemp3(1 downto 0) := "0" & vreqf.startaddr(31);
addrtemp2(1 downto 0) := vreqf.startaddr(31 downto 30);
addrtemp1(1 downto 0) := vreqf.startaddr(30 downto 29);
addrtemp0(1 downto 0) := vreqf.startaddr(29 downto 28);
end if;
muxin4 <= addrtemp3 & addrtemp2 & addrtemp1 & addrtemp0;
abank := muxout4(2 downto 0);
if dr.cfg.eightbanks='0' then
abank := '0' & abank(2) & abank(1);
end if;
acol := vreqf.startaddr(log2(ddrbits/8)+13 downto log2(ddrbits/8));
if ddrbits=16 then acol(0):='0'; end if; -- Always align to at least 32 bits
acsn(0) := muxout4(3);
acsn(1) := not acsn(0);
dv.setrow := '0';
if dr.setrow='1' then
dv.row := dr.sdo_address_prev;
end if;
dv.samerow := '0';
if abank=dr.sdo_ba and acsn=dr.sdo_csn and arow=dr.row then
dv.samerow := '1';
end if;
dv.request_row := arow;
dv.request_cs := acsn(0 downto 0);
dv.request_bank := abank;
hio1 := vreqf.hio;
if raspipe /= 0 then
vstart := dr.start_tog_prev;
arow := dr.request_row;
acsn := (not dr.request_cs) & dr.request_cs;
abank := dr.request_bank;
hio1 := vreq.hio;
end if;
aendaddr := vreq.endaddr(log2(4*burstlen)-1 downto 2);
if vreq.hsize(1 downto 0)="11" and vreq.hio='0' then
aendaddr(2):='1';
end if;
if ahbdw > 64 and vreqf.hsize(2)='1' then
aendaddr(3 downto 2) := "11";
if ahbdw > 128 and vreqf.hsize(0)='1' then
aendaddr(4) := '1';
end if;
end if;
aloa(l2ddrw-4 downto 0) := vreq.startaddr(l2ddrw-4 downto 0);
if ddrbits > 32 then addrlo32 := dr.addrlo(3 downto 2);
elsif ddrbits > 16 then addrlo32 := '0' & dr.addrlo(2);
else addrlo32 := "00";
end if;
endaddr32 := dr.endaddr(3 downto 2);
endaddr43 := dr.endaddr(4 downto 3);
endaddr42 := dr.endaddr(4 downto 2);
-- Calculate data mask
mask := (others => dr.pastlast);
-- Set mask bits for <word access
if dr.hsize="000" then
if dr.addrlo(0)='1' then
mask := mask or "1010101010101010";
else
mask := mask or "0101010101010101";
end if;
end if;
if dr.hsize(2 downto 1)="00" then
if dr.addrlo(1)='1' then
mask := mask or "1100110011001100";
else
mask := mask or "0011001100110011";
end if;
end if;
-- First access
-- (this could be written in generic code instead)
if dr.ctr=zerov(dr.ctr'length) then
case ddrbits is
when 16 =>
null;
when 32 =>
if dr.addrlo(2)='1' then
mask(7 downto 0) := mask(7 downto 0) or x"F0";
end if;
when 64 =>
case addrlo32 is
when "00" => null;
when "01" => mask := mask or x"F000";
when "10" => mask := mask or x"FF00";
when others => mask := mask or x"FFF0";
end case;
when others => null;
end case;
end if;
-- Last access
if dr.ramaddr = dr.endaddr(log2(4*burstlen)-1 downto log2(2*ddrbits/8)) then
if hwidthen=0 or dr.hwidth='0' or dr.hwctr='1' then
dv.pastlast := '1';
end if;
case ddrbits is
when 16 => null;
when 32 =>
if dr.endaddr(2)='0' then
mask(7 downto 0) := mask(7 downto 0) or x"0F";
end if;
when 64 =>
case endaddr32 is
when "00" => mask := mask or x"0FFF";
when "01" => mask := mask or x"00FF";
when "10" => mask := mask or x"000F";
when others => null;
end case;
when others => null;
end case;
end if;
-- Before first
if dr.col(1)='1' and dr.ctr(0)='1' and dr.ctr(dr.ctr'high downto 1)=zerov(dr.ctr'length-1) then
mask := mask or x"FFFF";
end if;
dv.sdo_rasn := '1'; dv.sdo_casn := '1'; dv.sdo_wen := '1';
dv.sdo_odt := '0'; dv.sdo_oct := '0';
dv.rbwrite := '0';
dv.ctr := std_logic_vector(unsigned(dr.ctr)+1);
if hwidthen/=0 and dr.hwidth='1' and dr.s=dsdata then
dv.hwctr := not dr.hwctr;
if dr.hwctr='0' then dv.ctr := dr.ctr; end if;
end if;
dv.rastimer := std_logic_vector(unsigned(dr.rastimer)+1);
if dr.rastimer=dr.cfg.tras then dv.tras_met := '1'; end if;
-- Calculate whether we would precharge the next cycle if Tras=0
precharge_notras := '0';
if dr.casctr=zerov(dr.casctr'length) and dr.prectr="000000" and dr.pchpend='1' then
precharge_notras := '1';
end if;
-- Calculate whether we should precharge the next cycle
precharge_next := precharge_notras and dr.tras_met;
block_precharge := '0';
inc_rctr := '0';
goto_caslat := '0';
case dr.s is
when dsidle =>
dv.ctr := (others => '0');
dv.hwctr := '0';
dv.sdo_bdrive := not oepols;
dv.sdo_qdrive := not oepols;
dv.sdo_nbdrive := not oepols;
dv.col := acol;
dv.sdo_csn := (others => '1');
dv.rastimer := (others => '0');
dv.tras_met := '0';
dv.response.rctr_gray := "0000";
if dr.refpend='1' and dr.cfg.refon='1' then
-- Periodic refresh
dv.sdo_csn := (others => '0');
dv.sdo_rasn := '0';
dv.sdo_casn := '0';
dv.refpend := '0';
dv.s := dsrefresh;
elsif vstart /= dr.response.done_tog and (dr.cmds=dcon or (dr.cmds=dcoff and dr.cfg.renable='0')) then
-- R/W data
dv.sdo_rasn := '0' or hio1;
dv.sdo_csn := acsn;
dv.sdo_address := arow;
dv.sdo_ba := abank;
dv.s := dsrascas;
elsif dr.cfg.command /= "000" then
-- Command
dv.sdo_csn := (others => '0');
if dr.cfg.command(2 downto 1)="11" then
dv.sdo_wen:='0'; dv.sdo_casn:='0'; dv.sdo_rasn:='0';
dv.sdo_ba := "00" & dr.cfg.command(0);
if dr.cfg.command(0)='0' or dr.cfg.emr="00" then
dv.sdo_ba := "000";
dv.sdo_address := mr;
else
dv.sdo_ba := "0" & dr.cfg.emr;
if dr.cfg.emr="01" then
dv.sdo_address := "0000"&conv_std_logic(dqsse=1)&dr.cfg.ocd&dr.cfg.ocd&dr.cfg.ocd
& dr.cfg.odten(1)&"000"& dr.cfg.odten(0) & dr.cfg.strength & "0";
else
dv.sdo_address := (others => '0');
end if;
end if;
else
dv.sdo_wen := dr.cfg.command(2);
dv.sdo_casn := dr.cfg.command(1);
dv.sdo_rasn := dr.cfg.command(0);
dv.sdo_address(10) := '1';
-- print("X Command: " & tost(dr.cfg.command) & " -> casn:" & tost(dv.sdo_casn) & ",rasn:" & tost(dv.sdo_rasn) & ",wen:" & tost(dv.sdo_wen));
end if;
dv.cfg.command := "000";
if dr.cfg.command=CMD_REF then
dv.s := dsrefresh;
end if;
if dr.cfg.command=CMD_PRE then
dv.s := dspreall;
end if;
end if;
when dsrascas =>
if dr.ctr(2 downto 0)="000" then
-- pragma translate_off
assert dr.ctr="00000000" severity failure;
-- pragma translate_on
-- dv.row := dr.sdo_address;
dv.setrow := '1';
end if;
dv.hwrite := vreq.hwrite;
dv.hsize := vreq.hsize;
dv.endaddr := aendaddr;
dv.addrlo := aloa;
dv.sdo_address := dr.col(13 downto 10) & '0' & dr.col(9 downto 1) & '0';
if dr.hwidth='1' then
dv.sdo_address := dr.col(12 downto 9) & '0' & dr.col(8 downto 1) & "00";
end if;
if vreq.hio='1' and dr.ctr(0)='1' then
dv.s := dsreg;
dv.ctr := (others => '0');
dv.hwctr := '0';
elsif vreq.hio='0' and dr.ctr(2 downto 0)=dr.cfg.trcd then
goto_caslat := '1';
end if;
when dscaslat =>
dv.sdo_odt := dr.hwrite;
dv.sdo_oct := not dr.hwrite;
dv.pastlast := '0';
if (dis_caslat = 0 and dr.ctr(2 downto 0)=caslat_reg) or
(dis_caslat /= 0 and dr.hwrite='0' and dr.ctr(2 downto 0)="000" ) or
(dis_caslat /= 0 and dr.hwrite='1' and dr.ctr(2 downto 0)=std_logic_vector(unsigned(sdi.regrdata(2 downto 0)) -1)) then
if dr.hwrite='1' then
dv.s := dsdata;
else
dv.s := dsreaddly;
end if;
dv.ctr := (others => '0');
dv.hwctr := '0';
dv.sdo_qdrive := not (dr.hwrite xor oepols);
dv.sdo_nbdrive := not (dr.hwrite xor oepols);
end if;
when dsreaddly =>
dv.sdo_odt := dr.hwrite;
dv.sdo_oct := not dr.hwrite;
dv.pastlast := '0';
if dr.ctr(3 downto 0)=dr.cfg.readdly then
dv.s := dsdata;
dv.ctr := (others => '0');
dv.hwctr := '0';
end if;
when dsdata =>
inc_rctr := '0';
dv.sdo_odt := dr.hwrite;
dv.sdo_oct := not dr.hwrite;
dv.rbwrite := '1';
dv.sdo_dqm := mask;
dv.sdo_bdrive := not (dr.hwrite xor oepols);
dv.sdo_qdrive := not (dr.hwrite xor oepols);
dv.sdo_nbdrive := not (dr.hwrite xor oepols);
-- If-case to handle pausing for half-width mode
if hwidthen=0 or dr.hwidth='0' or dr.hwctr='1' then
inc_rctr := '1';
-- The first request may be on a 2-odd column to get the first data first
-- Make sure following requests are on even mult of 4xcolumns
if dr.ctr(0)='1' then
dv.col(1) := '0';
end if;
-- Make sure we don't advance read counter for the unwanted 3:rd/4:th
-- word in the burst in this case
if dr.ctr(0)='1' and dr.col(1)='1' then
inc_rctr := '0';
end if;
-- Toggle done and change state after completed burst
if dr.ctr(log2(ddr_burstlen)-1 downto 0)=(not zerov(l2ddr_burstlen)) then
dv.sdo_nbdrive := not oepols;
dv.s := dsdone;
dv.response.done_tog := not dr.response.done_tog;
end if;
end if;
-- Stall if not ready yet
if hasdqvalid/=0 and sdi.datavalid='0' and dr.hwrite='0' then
dv.ctr := dr.ctr;
dv.hwctr := dr.hwctr;
dv.response := dr.response;
dv.s := dsdata;
dv.col(1) := dr.col(1);
dv.rbwrite := '0';
inc_rctr := '0';
end if;
if inc_rctr='1' and dr.hwrite='0' then
dv.response.rctr_gray(l2ddr_burstlen-1 downto 0) :=
nextgray(dr.response.rctr_gray(l2ddr_burstlen-1 downto 0));
end if;
when dsdone =>
dv.response.rctr_gray := "0000";
dv.sdo_bdrive := not oepols;
if dr.ctr(0)='1' then
dv.sdo_qdrive := not oepols;
end if;
if dr.pchpend='0' and dr.prectr=zerov(dr.prectr'length) then
dv.s := dsidle;
end if;
-- Short circuit if request on same row and waiting for Tras to expire
if precharge_notras='1' and precharge_next='0' and
dr.start_tog_prev /= dr.response.done_tog and dr.samerow='1' and vreq.hio='0' then
dv.col := acol;
dv.endaddr := aendaddr;
dv.addrlo := aloa;
dv.hwrite := vreq.hwrite;
dv.hsize := vreq.hsize;
dv.s := dsagain;
dv.sdo_qdrive := not oepols;
end if;
when dsagain =>
block_precharge := '1';
dv.sdo_address := dr.col(13 downto 10) & '0' & dr.col(9 downto 1) & '0';
goto_caslat := '1';
when dsreg =>
-- This code assumes ddrbits>=16, needs to be changed slightly to support
-- smaller widths
dv.rbwrite := '1';
-- DDR2CFG1-5,PHYCFG read
regt0 := (others => '0'); regt1 := (others => '0');
case ddrbits is
when 16 =>
case endaddr42 is
when "000" => regt0 := regsd1(31 downto 16); regt1 := regsd1(15 downto 0);
when "001" => regt0 := regsd2(31 downto 16); regt1 := regsd2(15 downto 0);
when "010" => regt0 := regsd3(31 downto 16); regt1 := regsd3(15 downto 0);
when "011" => regt0 := regsd4(31 downto 16); regt1 := regsd4(15 downto 0);
when "100" | "101" => regt0 := regsd5(31 downto 16); regt1 := regsd5(15 downto 0);
when "110" => regt0 := sdi.regrdata(31 downto 16); regt1 := sdi.regrdata(15 downto 0);
when others => regt0 := sdi.regrdata(63 downto 48); regt1 := sdi.regrdata(47 downto 32);
end case;
when 32 =>
case endaddr43 is
when "00" => regt0 := regsd1; regt1 := regsd2;
when "01" => regt0 := regsd3; regt1 := regsd4;
when "10" => regt0 := regsd5; regt1 := regsd2;
when others => regt0 := sdi.regrdata(31 downto 0); regt1 := sdi.regrdata(63 downto 32);
end case;
when 64 =>
case dr.endaddr(4) is
when '0' => regt0 := regsd1 & regsd2; regt1 := regsd3 & regsd4;
when others => regt0 := regsd5 & regsd2; regt1 := sdi.regrdata(31 downto 0) & sdi.regrdata(63 downto 32);
end case;
when 128 =>
regt0 := regsd1 & regsd2 & regsd3 & regsd4;
regt1 := regsd5 & regsd2 & sdi.regrdata(31 downto 0) & sdi.regrdata(63 downto 32);
when others =>
regt0(ddrbits-1 downto ddrbits-255) := regsd1 & regsd2 & regsd3 & regsd4 &
regsd5 & x"00000000" & sdi.regrdata(31 downto 0) & sdi.regrdata(63 downto 32);
end case;
dv.rbwdata(ddrbits*2+chkbits-1 downto ddrbits+chkbits) := regt0;
dv.rbwdata(ddrbits-1 downto 0) := regt1;
-- Note write data is two cycles behind
regt0 := dr.sdo_data(ddrbits*2-1 downto ddrbits);
regt1 := dr.sdo_data(ddrbits-1 downto 0);
if dr.hwrite='1' and dr.ctr(2 downto 0)="010" then
w5 := '0';
case ddrbits is
when 16 =>
case endaddr42 is
when "000" => regsd1 := regt0 & regt1;
when "001" => regsd2 := regt0 & regt1;
when "010" => regsd3 := regt0 & regt1;
when "011" => regsd4 := regt0 & regt1;
when "100" => regsd5 := regt0 & regt1;
w5 := '1';
when "110" => o.regwrite(0) := '1';
when "111" => o.regwrite(1) := '1';
when others => null;
end case;
when 32 =>
case endaddr42 is
when "000" => regsd1 := regt0;
when "001" => regsd2 := regt1;
when "010" => regsd3 := regt0;
when "011" => regsd4 := regt1;
when "100" => regsd5 := regt0;
w5 := '1';
when "110" => o.regwrite(0) := '1';
when "111" => o.regwrite(1) := '1';
when others => null;
end case;
when 64 =>
case endaddr42 is
when "000" => regsd1 := regt0(63 downto 32);
when "001" => regsd2 := regt0(31 downto 0);
when "010" => regsd3 := regt1(63 downto 32);
when "011" => regsd4 := regt1(31 downto 0);
when "100" => regsd5 := regt0(63 downto 32);
w5 := '1';
when "110" => o.regwrite(0) := '1';
when "111" => o.regwrite(1) := '1';
when others => null;
end case;
when 128 =>
case endaddr42 is
when "000" => regsd1 := regt0(127 downto 96);
when "001" => regsd2 := regt0(95 downto 64);
when "010" => regsd3 := regt0(63 downto 32);
when "011" => regsd4 := regt0(31 downto 0);
when "100" => regsd5 := regt1(127 downto 96);
w5 := '1';
when "110" => o.regwrite(0) := '1';
when "111" => o.regwrite(1) := '1';
when others => null;
end case;
when others =>
case endaddr42 is
when "000" => regsd1 := regt0(ddrbits-1 downto ddrbits-32);
when "001" => regsd2 := regt0(ddrbits-33 downto ddrbits-64);
when "010" => regsd3 := regt0(ddrbits-65 downto ddrbits-96);
when "011" => regsd4 := regt0(ddrbits-97 downto ddrbits-128);
when "100" => regsd5 := regt0(ddrbits-129 downto ddrbits-160);
w5 := '1';
when "110" => o.regwrite(0) := '1';
when "111" => o.regwrite(1) := '1';
when others => null;
end case;
end case;
-- Update lsb aliases for expanded fields in ddr2cfg5
if w5='1' then
regsd3(28) := regsd5(28); -- TRP
regsd3(22 downto 18) := regsd5(22 downto 18); -- TRFC
regsd1(26) := regsd5(8); -- TRCD
end if;
end if;
if (dr.hwrite='1' and dr.ctr(2 downto 1)="11") or dr.hwrite='0' then
dv.s := dsidle;
dv.response.done_tog := not dr.response.done_tog;
end if;
dv.cfg := (refon => regsd1(31), ocd => regsd1(30), emr => regsd1(29 downto 28),
trcd => regsd5(10 downto 9) & regsd1(26),
bsize => regsd1(27) & regsd1(25 downto 23), csize => regsd1(22 downto 21),
command => regsd1(20 downto 18), dllrst => regsd1(17), renable => regsd1(16),
cke => regsd1(15), refresh => regsd1(11 downto 0),
cal_pll => regsd3(30 downto 29), cal_rst => regsd3(31),
trp => regsd5(30 downto 29) & regsd3(28),
twr => regsd3(27 downto 23),
trfc => regsd5(25 downto 23) & regsd3(22 downto 18),
readdly => regsd4(23 downto 22) & regsd3(17 downto 16), cal_inc => regsd3(15 downto 8),
cal_en => regsd3(7 downto 0),
eightbanks => regsd4(8), dqsctrl => regsd4(7 downto 0),
caslat => regsd4(10 downto 9),
odten => regsd5(17 downto 16), tras => regsd5(4 downto 0), strength => regsd5(15),
trtp => regsd4(13), cbcal_inc => regsd4(31 downto 28), cbcal_en => regsd4(27 downto 24),
regmem => regsd4(21)
);
when dsrefresh =>
if dr.ctr(7 downto 0)=dr.cfg.trfc then
dv.s := dsidle;
end if;
when dspreall =>
-- Wait for tRP (eightbanks=0) or tRP+1 (eightbanks=1)
if dr.ctr(3 downto 0)=std_logic_vector(("0" & unsigned(dr.cfg.trp)) + (2+eightbanks)) then
dv.s := dsidle;
end if;
end case;
if goto_caslat='1' then
dv.s := dscaslat;
-- Set counter to -4 for read and -1 for write to compensate
-- write-read diff and pipelining.
-- Only need lowest three bits so set highest 3 to '0' as usual
dv.ctr(5 downto 3) := "000";
dv.ctr(2 downto 0) := "100";
if vreq.hwrite='1' then
dv.ctr(2 downto 0) := "111";
end if;
dv.casctr := std_logic_vector(to_unsigned(ddr_burstlen/2, dv.casctr'length));
dv.hwcas := '0';
dv.pchpend := '1';
end if;
-- CAS and precharge handling
-- FSM above sets up casctr and pchpend
if dis_caslat /= 0 then
dv.twr_plus_cl := std_logic_vector(("0" & unsigned(dr.cfg.twr)) + ("000" & unsigned(sdi.regrdata(2 downto 0))) - 1); -- should be -2 instead of -1 but AFI might delay write data for an additional clock cycle, requiring an additional twr clock cycle
else
dv.twr_plus_cl := std_logic_vector(("0" & unsigned(dr.cfg.twr)) + ("0000" & unsigned(dr.cfg.caslat)));
end if;
if dr.prectr /= zerov(dr.prectr'length) then
dv.prectr := std_logic_vector(unsigned(dr.prectr)-1);
end if;
dv.read_pend := '0' & dr.read_pend(dr.read_pend'high downto 1);
dv.datacas := '1';
if dr.casctr /= zerov(dr.casctr'length) then
if dr.datacas='1' then
dv.datacas := '0';
-- dv.sdo_casn := '0';
dv.sdo_wen := not dr.hwrite;
if dr.hwrite='0' then
if dis_caslat /= 0 then
dv.read_pend(4 downto 3) := "11";
else
case dr.cfg.caslat is
when "00" => dv.read_pend(4 downto 3) := "11";
when "01" => dv.read_pend(5 downto 4) := "11";
when "10" => dv.read_pend(6 downto 5) := "11";
when others => dv.read_pend(7 downto 6) := "11";
end case;
end if;
end if;
elsif dr.hwidth='1' then
dv.hwcas := not dr.hwcas;
if dr.hwcas='1' then
dv.casctr := std_logic_vector(unsigned(dr.casctr)-1);
if l2blen-l2ddrw > 1 then
dv.sdo_address(l2blen-l2ddrw+1 downto 3) :=
std_logic_vector(unsigned(dr.sdo_address(l2blen-l2ddrw+1 downto 3)+1));
end if;
dv.sdo_address(2) := '0';
else
dv.sdo_address(2) := not dr.sdo_address(2);
end if;
else
dv.casctr := std_logic_vector(unsigned(dr.casctr)-1);
if l2blen-l2ddrw > 1 then
dv.sdo_address(l2blen-l2ddrw downto 2) :=
std_logic_vector(unsigned(dr.sdo_address(l2blen-l2ddrw downto 2)+1));
end if;
dv.sdo_address(1) := '0';
end if;
-- Set up precharge counter (will not run until casctr=0)
if dr.hwrite='0' then
dv.prectr := "00000" & dr.cfg.trtp;
else
dv.prectr := dr.twr_plus_cl;
end if;
end if;
o.read_pend := dv.read_pend(7 downto 0);
dv.rasn_pre := '1';
if precharge_next='1' and block_precharge='0' then
dv.pchpend := '0';
dv.sdo_wen := '0';
-- dv.sdo_rasn := '0';
dv.rasn_pre := '0';
dv.prectr := "000" & dr.cfg.trp;
end if;
-- Refresh and init handling
dv.refctr := std_logic_vector(unsigned(dr.refctr)+1);
case dr.cmds is
when dcrstdel =>
if dr.refctr=std_logic_vector(to_unsigned(MHz*rstdel, dr.refctr'length)) then
dv.cmds := dcoff;
end if;
-- Bypass reset delay by writing anything to regsd2
if dr.start_tog_prev='1' and
vreq.hio='1' and vreq.hwrite='1' and vreq.endaddr(4 downto 2)="001" then
dv.cmds := dcoff;
end if;
when dcoff =>
-- Wait for renable to be set high and phy to be locked
dv.refctr := (others => '0');
if dr.cfg.renable='1' then
dv.cfg.cke := '1';
dv.cfg.dllrst := '1';
dv.cfg.ocd := '0';
dv.cmds := dcinit1;
elsif dis_init /= 0 then
dv.cmds := dcon;
end if;
when dcinit1 =>
-- Wait >=400 ns
if dr.refctr=std_logic_vector(to_unsigned((MHz*4+9)/10, dr.refctr'length)) then
dv.cmds := dcinit2;
dv.cfg.command := CMD_PRE;
dv.cfg.emr := "00";
end if;
when dcinit2 =>
-- MR order 2,3,1,0
-- 2xcycles per command
if dr.cfg.command="000" then
dv.cfg.command := CMD_EMR;
dv.cfg.emr := (not dr.cfg.emr(0)) & dr.cfg.emr(1); -- 00->10->11->01->00
if dr.cfg.emr="01" then
dv.cmds := dcinit3;
dv.refctr := (others => '0');
end if;
end if;
when dcinit3 =>
if dr.cfg.command="000" then
dv.cfg.command := CMD_PRE;
dv.cmds := dcinit4;
end if;
when dcinit4 =>
if dr.cfg.command="000" then
dv.cfg.command := CMD_REF;
dv.cmds := dcinit5;
end if;
when dcinit5 =>
if dr.cfg.command="000" then
dv.cfg.command := CMD_REF;
dv.cmds := dcinit6;
end if;
when dcinit6 =>
if dr.cfg.command="000" then
dv.cfg.command := CMD_EMR;
dv.cfg.emr := "00";
dv.cfg.dllrst := '0';
dv.cmds := dcinit7;
dv.refctr := (others => '0');
end if;
when dcinit7 =>
if dr.refctr(7 downto 0)=std_logic_vector(to_unsigned(200,8)) then
dv.cfg.command := CMD_EMR;
dv.cfg.emr := "01";
dv.cfg.ocd := '1';
dv.cmds := dcinit8;
end if;
when dcinit8 =>
if dr.cfg.command="000" then
if dr.cfg.ocd='1' then
dv.cfg.ocd := '0';
dv.cfg.command := CMD_EMR;
else
dv.cmds := dcon;
dv.cfg.renable := '0';
end if;
end if;
dv.refctr := (others => '0');
when dcon =>
if dr.cfg.cke='0' then
dv.cmds := dcoff;
elsif dr.cfg.renable='1' then
dv.cmds := dcinit2;
dv.refctr := (others => '0');
elsif dr.refctr(11 downto 0)=dr.cfg.refresh then
dv.refpend := '1';
dv.refctr := (others => '0');
end if;
end case;
if dis_init /= 0 then
dv.cfg.renable := '0';
end if;
-- Calculate next address
dv.ramaddr(0) := dv.ctr(0) xor dv.col(1);
if rbuf_wabits > 1 then
dv.ramaddr(rbuf_wabits-1 downto 1) :=
std_logic_vector(unsigned(dr.col(rbuf_wabits downto 2)) +
unsigned(dv.ctr(rbuf_wabits-1 downto 1)));
end if;
-- print("col: " & tost(dr.col) & ", dv.ctr: " & tost(dv.ctr) & ", res: " & tost(dv.ramaddr));
if eightbanks=0 then dv.cfg.eightbanks:='0'; end if;
rbwd := dv.rbwdata;
rbwa := dr.ramaddr;
rbw := dv.rbwrite;
if plmemwrite then
rbwd := dr.rbwdata;
rbwa := dr.ramaddr_prev;
rbw := dr.rbwrite;
end if;
if not plmemread then
o.dqm := dr.sdo_dqm;
o.sdwen := dr.sdo_wen;
o.data := dv.sdo_data;
o.cb := dv.sdo_cb;
end if;
-- half-width output data muxing, placed after (potential) pipeline regs.
if hwidthen/=0 and dr.hwidth='1' then
if dr.hwctr='1' then
o.data(ddrbits/2-1 downto 0) := o.data(2*ddrbits-ddrbits/2-1 downto ddrbits);
o.data(2*ddrbits-ddrbits/2-1 downto ddrbits) := o.data(2*ddrbits-1 downto 2*ddrbits-ddrbits/2);
if chkbits > 0 then
o.cb(chkbits/2-1 downto 0) := o.cb(2*chkbits-chkbits/2-1 downto chkbits);
o.cb(2*chkbits-chkbits/2-1 downto chkbits) := o.cb(2*chkbits-1 downto 2*chkbits-chkbits/2);
end if;
o.dqm(ddrbits/16-1 downto 0) := o.dqm(ddrbits/4-ddrbits/16-1 downto ddrbits/8);
o.dqm(ddrbits/4-ddrbits/16-1 downto ddrbits/8) := o.dqm(ddrbits/4-1 downto ddrbits/4-ddrbits/16);
else
o.data(2*ddrbits-ddrbits/2-1 downto ddrbits) := o.data(ddrbits-1 downto ddrbits/2);
if chkbits > 0 then
o.cb(2*chkbits-chkbits/2-1 downto chkbits) := o.cb(chkbits-1 downto chkbits/2);
end if;
o.dqm(ddrbits/4-ddrbits/16-1 downto ddrbits/8) := o.dqm(ddrbits/8-1 downto ddrbits/16);
end if;
end if;
if ddr_rst='0' then
dv.s := dsidle;
dv.cmds := dcrstdel;
dv.response := ddr_response_none;
dv.casctr := (others => '0');
dv.refctr := (others => '0');
dv.pchpend := '0';
dv.refpend := '0';
dv.rbwrite := '0';
dv.ctr := (others => '0');
dv.hwctr := '0';
dv.sdo_nbdrive := not oepols;
dv.sdo_csn := (others => '1');
dv.rastimer := (others => '0');
dv.tras_met := '0';
dv.cfg.command := "000";
dv.cfg.emr := "00";
dv.cfg.csize := conv_std_logic_vector(col-9, 2);
dv.cfg.bsize := conv_std_logic_vector(log2(Mbyte/8), 4);
dv.cfg.refon := '0';
dv.cfg.trfc := conv_std_logic_vector(TRFC*MHz/1000-2, 8);
dv.cfg.refresh := conv_std_logic_vector(7800*MHz/1000, 12);
dv.cfg.twr := conv_std_logic_vector((15 * MHz + 999) / 1000 + 3, 5);
dv.sdo_dqm := (others => '1');
dv.cfg.dllrst := '0';
dv.cfg.cke := std_logic(to_unsigned(cke_rst, 1)(0));
dv.cfg.ocd := '0';
dv.cfg.readdly := conv_std_logic_vector(readdly, 4);
dv.cfg.eightbanks := conv_std_logic_vector(eightbanks, 1)(0);
dv.cfg.odten := std_logic_vector(to_unsigned(odten,2));
dv.cfg.dqsctrl := (others => '0');
dv.cfg.strength := '0';
if pwron = 1 and dis_init = 0 then dv.cfg.renable := '1'; else dv.cfg.renable:='0'; end if;
-- Default to min 15 ns tRCD, 15 ns tRP, min(7.5 ns,2*tCK) tRTP
-- Use CL=3 for DDR2-400/533, 4 for DDR2-667, 5 for DDR2-800
dv.cfg.trcd := "000";
dv.cfg.trp := "000";
dv.cfg.trtp := '0';
dv.cfg.caslat := "00";
dv.cfg.regmem := '0';
if MHz > 130 then
dv.cfg.trcd := "001";
dv.cfg.trp := "001";
end if;
if MHz > 200 then
-- Will work up to 600 MHz, then trcd/trp needs to be expanded
dv.cfg.trcd := std_logic_vector(to_unsigned((15 * MHz + 999) / 1000 - 2, 3));
dv.cfg.trp := std_logic_vector(to_unsigned((15 * MHz + 999) / 1000 - 2, 3));
end if;
if MHz > 267 then
-- Works up to 400 MHz, then trtp will need to be expanded
dv.cfg.trtp := '1';
dv.cfg.caslat := "01";
end if;
if MHz > 334 then
dv.cfg.caslat := "10";
end if;
dv.cfg.cal_rst := '1'; -- Reset input delays
dv.sdo_ba := (others => '0');
dv.sdo_address := (others => '0');
-- Default to min 45 ns tRAS
dv.cfg.tras := std_logic_vector(to_unsigned((45*MHz+999)/1000 - 2, 5));
dv.read_pend := (others => '0');
if ddr_syncrst /= 0 then
dv.sdo_bdrive := not oepols;
dv.sdo_qdrive := not oepols;
dv.sdo_odt := '0';
if phyptctrl /= 0 then
o.sdcke := "00";
o.bdrive := not oepols;
o.qdrive := not oepols;
o.odt := (others => '0');
end if;
end if;
end if;
if dr.cfg.odten="00" then
dv.sdo_odt := '0';
end if;
if octen=0 then
dv.sdo_oct := '0';
end if;
for x in 0 to chkbits/4-1 loop
o.cbdqm(x) := o.dqm(x*ddrbits/chkbits);
end loop;
if vreq.maskdata='1' then
o.dqm := (others => '1');
end if;
if vreq.maskcb='1' then
o.cbdqm := (others => '1');
end if;
if dr.cfg.command /= "000" then
-- print("Command: " & tost(dr.cfg.command) & " -> casn:" & tost(dv.sdo_casn) & ",rasn:" & tost(dv.sdo_rasn) & ",wen:" & tost(dv.sdo_wen));
end if;
-- Dynamic nosync handling (nosync=2)
if plmemwrite then
dv.response1 := dr.response;
dv.response2 := dr.response;
else
dv.response1 := dv.response;
dv.response2 := dv.response;
end if;
if reqsel='1' then dv.response1 := ddr_response_none; end if;
if reqsel='0' then dv.response2 := ddr_response_none; end if;
if nosync > 1 then
resp := dr.response1;
elsif plmemwrite then
resp := dr.response_prev;
else
resp := dr.response;
end if;
resp2 := dr.response2;
if scantest/=0 and phyptctrl/=0 then
if testen='1' then
o.bdrive := testoen;
o.qdrive := testoen;
end if;
end if;
rbwdata <= rbwd;
rbwaddr <= rbwa;
rbwrite <= rbw;
wbraddr <= wbra;
sdo <= o;
response <= resp;
response2 <= resp2;
ndr <= dv;
end process;
ddrregs: process(clk_ddr,arst)
begin
if rising_edge(clk_ddr) then
dr <= ndr;
end if;
if ddr_syncrst=0 and arst='0' then
dr.cfg.cke <= std_logic(to_unsigned(cke_rst, 1)(0));
dr.sdo_bdrive <= not oepols;
dr.sdo_qdrive <= not oepols;
dr.sdo_odt <= '0';
end if;
end process;
end;
| gpl-3.0 | db39a51de4cb271c828d6bdce3835886 | 0.536488 | 3.379293 | false | false | false | false |
EliasLuiz/TCC | Leon3/lib/gaisler/pci/ptf/pt_pkg.vhd | 1 | 29,067 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-------------------------------------------------------------------------------
-- Package: pt_pkg
-- File: pt_pkg.vhd
-- Author: Nils-Johan Wessman, Aeroflex Gaisler
-- Description: PCI Test Framework - Main package
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
--use grlib.amba.all;
--use grlib.testlib.all;
use grlib.stdlib.all;
package pt_pkg is
-----------------------------------------------------------------------------
-- Constants and PCI signal
-----------------------------------------------------------------------------
-- Constants for PCI commands
constant INT_ACK : std_logic_vector(3 downto 0) := "0000";
constant SPEC_CYCLE : std_logic_vector(3 downto 0) := "0001";
constant IO_READ : std_logic_vector(3 downto 0) := "0010";
constant IO_WRITE : std_logic_vector(3 downto 0) := "0011";
constant MEM_READ : std_logic_vector(3 downto 0) := "0110";
constant MEM_WRITE : std_logic_vector(3 downto 0) := "0111";
constant CONF_READ : std_logic_vector(3 downto 0) := "1010";
constant CONF_WRITE : std_logic_vector(3 downto 0) := "1011";
constant MEM_R_MULT : std_logic_vector(3 downto 0) := "1100";
constant DAC : std_logic_vector(3 downto 0) := "1101";
constant MEM_R_LINE : std_logic_vector(3 downto 0) := "1110";
constant MEM_W_INV : std_logic_vector(3 downto 0) := "1111";
type bar_type is array(0 to 5) of std_logic_vector(31 downto 0);
constant bar_init : bar_type := ((others => '0'),(others => '0'),(others => '0'),(others => '0'),(others => '0'),(others => '0'));
type config_header_type is record
devid : std_logic_vector(15 downto 0);
vendid : std_logic_vector(15 downto 0);
status : std_logic_vector(15 downto 0);
command : std_logic_vector(15 downto 0);
class_code : std_logic_vector(23 downto 0);
revid : std_logic_vector(7 downto 0);
bist : std_logic_vector(7 downto 0);
header_type : std_logic_vector(7 downto 0);
lat_timer : std_logic_vector(7 downto 0);
cache_lsize : std_logic_vector(7 downto 0);
bar : bar_type;
cis_p : std_logic_vector(31 downto 0);
subid : std_logic_vector(15 downto 0);
subvendid : std_logic_vector(15 downto 0);
exp_rom_ba : std_logic_vector(31 downto 0);
max_lat : std_logic_vector(7 downto 0);
min_gnt : std_logic_vector(7 downto 0);
int_pin : std_logic_vector(7 downto 0);
int_line : std_logic_vector(7 downto 0);
end record;
constant config_init : config_header_type := (
devid => conv_std_logic_vector(16#0BAD#,16),
vendid => conv_std_logic_vector(16#AFFE#,16),
status => (others => '0'),
command => (others => '0'),
class_code => conv_std_logic_vector(16#050000#,24),
revid => conv_std_logic_vector(16#01#,8),
bist => (others => '0'),
header_type => (others => '0'),
lat_timer => (others => '0'),
cache_lsize => (others => '0'),
bar => bar_init,
cis_p => (others => '0'),
subid => (others => '0'),
subvendid => (others => '0'),
exp_rom_ba => (others => '0'),
max_lat => (others => '0'),
min_gnt => (others => '0'),
int_pin => (others => '0'),
int_line => (others => '0'));
-- These types defines the TB PCI bus
type pci_ad_type is record
ad : std_logic_vector(31 downto 0);
cbe : std_logic_vector(3 downto 0);
par : std_logic;
end record;
constant ad_const : pci_ad_type := (
ad => (others => 'Z'),
cbe => (others => 'Z'),
par => 'Z');
type pci_ifc_type is record
frame : std_logic;
irdy : std_logic;
trdy : std_logic;
stop : std_logic;
devsel : std_logic;
idsel : std_logic_vector(20 downto 0);
lock : std_logic;
end record;
constant ifc_const : pci_ifc_type := (
frame => 'H',
irdy => 'H',
trdy => 'H',
stop => 'H',
lock => 'H',
idsel => (others => 'L'),
devsel => 'H');
type pci_err_type is record
perr : std_logic;
serr : std_logic;
end record;
constant err_const : pci_err_type := (
perr => 'H',
serr => 'H');
type pci_arb_type is record
req : std_logic_vector(20 downto 0);
gnt : std_logic_vector(20 downto 0);
end record;
constant arb_const : pci_arb_type := (
req => (others => 'H'),
gnt => (others => 'H'));
type pci_syst_type is record
clk : std_logic;
rst : std_logic;
end record;
constant syst_const : pci_syst_type := (
clk => 'H',
rst => 'H');
type pci_ext64_type is record
ad : std_logic_vector(63 downto 32);
cbe : std_logic_vector(7 downto 4);
par64 : std_logic;
req64 : std_logic;
ack64 : std_logic;
end record;
constant ext64_const : pci_ext64_type := (
ad => (others => 'Z'),
cbe => (others => 'Z'),
par64 => 'Z',
req64 => 'Z',
ack64 => 'Z');
--type pci_int_type is record
-- inta : std_logic;
-- intb : std_logic;
-- intc : std_logic;
-- intd : std_logic;
--end record;
--constant int_const : pci_int_type := (
-- inta => 'H',
-- intb => 'H',
-- intc => 'H',
-- intd => 'H');
constant int_const : std_logic_vector(3 downto 0) := "HHHH";
type pci_cache_type is record
sbo : std_logic;
sdone : std_logic;
end record;
constant cache_const : pci_cache_type := (
sbo => 'U',
sdone => 'U');
type pci_type is record
ad : pci_ad_type;
ifc : pci_ifc_type;
err : pci_err_type;
arb : pci_arb_type;
syst : pci_syst_type;
ext64 : pci_ext64_type;
--int : pci_int_type;
int : std_logic_vector(3 downto 0);
cache : pci_cache_type;
end record;
constant pci_idle : pci_type := ( ad_const, ifc_const, err_const, arb_const,
syst_const, ext64_const, int_const, cache_const);
-----------------------------------------------------------------------------
-- Types for PCI master
-----------------------------------------------------------------------------
type pt_pci_access_type is record
addr : std_logic_vector(31 downto 0);
cbe_cmd : std_logic_vector(3 downto 0);
data : std_logic_vector(31 downto 0);
cbe_data : std_logic_vector(3 downto 0);
ws : integer;
status : integer range 0 to 3;
id : integer;
debug : integer range 0 to 3;
last : boolean;
idle : boolean;
list_res : boolean;
valid : boolean;
parerr : integer range 0 to 2;
cod : integer range 0 to 2; -- Cancel on disconnect
end record;
type pt_pci_master_in_type is record
req : std_logic;
add : boolean;
remove : boolean;
rmall : boolean;
get_res : boolean;
add_res : boolean;
acc : pt_pci_access_type;
end record;
type pt_pci_master_out_type is record
ack : std_logic;
res_found : std_logic;
acc : pt_pci_access_type;
valid : boolean;
end record;
-----------------------------------------------------------------------------
-- PCI master procedures
-----------------------------------------------------------------------------
procedure pt_pci_master_sync_with_core(
signal dbgi : out pt_pci_master_in_type;
signal dbgo : in pt_pci_master_out_type);
procedure pt_add_acc_nb(
constant addr : std_logic_vector(31 downto 0);
constant cbe_cmd : std_logic_vector(3 downto 0);
constant data : std_logic_vector(31 downto 0);
constant cbe_data : std_logic_vector(3 downto 0);
constant waits : integer;
constant last : boolean;
constant id : integer;
constant debug : integer;
signal dbgi : out pt_pci_master_in_type;
signal dbgo : in pt_pci_master_out_type;
constant list_res : boolean := false);
procedure pt_add_acc_nb(
constant addr : std_logic_vector(31 downto 0);
constant cbe_cmd : std_logic_vector(3 downto 0);
constant data : std_logic_vector(31 downto 0);
constant cbe_data : std_logic_vector(3 downto 0);
constant waits : integer;
constant last : boolean;
constant parerr : integer;
constant id : integer;
constant debug : integer;
signal dbgi : out pt_pci_master_in_type;
signal dbgo : in pt_pci_master_out_type;
constant list_res : boolean := false);
procedure pt_add_acc_nb(
constant addr : std_logic_vector(31 downto 0);
constant cbe_cmd : std_logic_vector(3 downto 0);
constant data : std_logic_vector(31 downto 0);
constant cbe_data : std_logic_vector(3 downto 0);
constant waits : integer;
constant last : boolean;
constant parerr : integer;
constant cod : integer;
constant id : integer;
constant debug : integer;
signal dbgi : out pt_pci_master_in_type;
signal dbgo : in pt_pci_master_out_type;
constant list_res : boolean := false);
procedure pt_add_acc(
constant addr : std_logic_vector(31 downto 0);
constant cbe_cmd : std_logic_vector(3 downto 0);
constant data : std_logic_vector(31 downto 0);
constant cbe_data : std_logic_vector(3 downto 0);
constant waits : integer;
constant last : boolean;
constant id : integer;
constant debug : integer;
signal dbgi : out pt_pci_master_in_type;
signal dbgo : in pt_pci_master_out_type);
procedure pt_add_acc(
constant addr : std_logic_vector(31 downto 0);
constant cbe_cmd : std_logic_vector(3 downto 0);
constant data : std_logic_vector(31 downto 0);
constant cbe_data : std_logic_vector(3 downto 0);
constant waits : integer;
constant last : boolean;
constant parerr : integer;
constant id : integer;
constant debug : integer;
signal dbgi : out pt_pci_master_in_type;
signal dbgo : in pt_pci_master_out_type);
procedure pt_add_acc(
constant addr : std_logic_vector(31 downto 0);
constant cbe_cmd : std_logic_vector(3 downto 0);
constant data : std_logic_vector(31 downto 0);
constant cbe_data : std_logic_vector(3 downto 0);
constant waits : integer;
constant last : boolean;
constant parerr : integer;
constant cod : integer;
constant id : integer;
constant debug : integer;
signal dbgi : out pt_pci_master_in_type;
signal dbgo : in pt_pci_master_out_type);
procedure pt_add_idle_nb(
constant waits : integer;
constant id : integer;
constant debug : integer;
signal dbgi : out pt_pci_master_in_type;
signal dbgo : in pt_pci_master_out_type;
constant list_res : boolean := false);
procedure pt_add_idle(
constant waits : integer;
constant id : integer;
constant debug : integer;
signal dbgi : out pt_pci_master_in_type;
signal dbgo : in pt_pci_master_out_type);
-----------------------------------------------------------------------------
-- Types for PCI target
-----------------------------------------------------------------------------
type pt_pci_response_type is record
addr : std_logic_vector(31 downto 0);
retry : integer;
ws : integer;
diswithout : integer;
diswith : integer;
abort : integer;
parerr : integer;
debug : integer;
valid : boolean;
end record;
type pt_pci_target_in_type is record
req : std_logic;
insert: std_logic;
remove: std_logic;
rmall : std_logic;
addr : std_logic_vector(31 downto 0);
resp : pt_pci_response_type;
end record;
type pt_pci_target_out_type is record
ack : std_logic;
resp : pt_pci_response_type;
valid : std_logic;
end record;
-----------------------------------------------------------------------------
-- PCI target procedures
-----------------------------------------------------------------------------
procedure pt_pci_target_sync_with_core(
signal dbgi : out pt_pci_target_in_type;
signal dbgo : in pt_pci_target_out_type);
procedure pt_insert_resp(
constant addr : std_logic_vector(31 downto 0);
constant retry : integer;
constant waits : integer;
constant discon: integer;
constant parerr: integer;
constant abort : integer;
constant debug : integer;
signal dbgi : out pt_pci_target_in_type;
signal dbgo : in pt_pci_target_out_type);
procedure pt_remove_resp(
constant addr : std_logic_vector(31 downto 0);
constant rmall : boolean;
signal dbgi : out pt_pci_target_in_type;
signal dbgo : in pt_pci_target_out_type);
-----------------------------------------------------------------------------
-- Component declarations
-----------------------------------------------------------------------------
component pt_pci_master -- A PCI master that is accessed through a Testbench vector
generic (
slot : integer := 0; -- Slot number for this unit
tval : time := 7 ns); -- Output delay for signals that are driven by this unit
port (
pciin : in pci_type;
pciout : out pci_type;
dbgi : in pt_pci_master_in_type;
dbgo : out pt_pci_master_out_type
);
end component;
component pt_pci_target -- Represents a simple memory on the PCI bus
generic (
slot : integer := 0; -- Slot number for this unit
abits : integer := 10; -- Memory size. Size is 2^abits 32-bit words
bars : integer := 1; -- Number of bars for this target. Min 1, Max 6
resptime : integer := 2; -- The initial response time in clks for this target
latency : integer := 0; -- The latency in clks for every dataphase for a burst access
rbuf : integer := 8; -- The maximum no of words this target can transfer in a continuous burst
stopwd : boolean := true; -- Target disconnect type. true = disconnect WITH data, false = disconnect WITHOUT data
tval : time := 7 ns; -- Output delay for signals that are driven by this unit
conf : config_header_type := config_init; -- The reset condition of the configuration space of this target
dbglevel : integer := 1); -- Debug level. Higher value means more debug information
port (
pciin : in pci_type;
pciout : out pci_type;
dbgi : in pt_pci_target_in_type;
dbgo : out pt_pci_target_out_type
);
end component;
component pt_pci_arb
generic (
slots : integer := 5; -- The number of slots in the test system
tval : time := 7 ns); -- Output delay for signals that are driven by this unit
port (
systclk : in pci_syst_type;
ifcin : in pci_ifc_type;
arbin : in pci_arb_type;
arbout : out pci_arb_type);
end component;
--component pt_pci_monitor is
-- generic (dbglevel : integer := 1); -- Debug level. Higher value means more debug information
-- port (pciin : in pci_type);
--end component;
end package pt_pkg;
package body pt_pkg is
-----------------------------------------------------------------------------
-- PCI master procedures
-----------------------------------------------------------------------------
procedure pt_pci_master_sync_with_core(
signal dbgi : out pt_pci_master_in_type;
signal dbgo : in pt_pci_master_out_type) is
begin
dbgi.req <= '1';
wait until dbgo.ack = '1';
dbgi.req <= '0';
wait until dbgo.ack = '0';
end procedure pt_pci_master_sync_with_core;
procedure pt_add_acc_nb(
constant addr : std_logic_vector(31 downto 0);
constant cbe_cmd : std_logic_vector(3 downto 0);
constant data : std_logic_vector(31 downto 0);
constant cbe_data : std_logic_vector(3 downto 0);
constant waits : integer;
constant last : boolean;
constant id : integer;
constant debug : integer;
signal dbgi : out pt_pci_master_in_type;
signal dbgo : in pt_pci_master_out_type;
constant list_res : boolean := false) is
begin
dbgi.add <= true;
dbgi.remove <= false;
dbgi.get_res <= false;
dbgi.add_res <= false;
dbgi.acc.id <= id;
dbgi.acc.addr <= addr;
dbgi.acc.cbe_cmd <= cbe_cmd;
dbgi.acc.data <= data;
dbgi.acc.cbe_data <= cbe_data;
dbgi.acc.ws <= waits;
dbgi.acc.last <= last;
dbgi.acc.idle <= false;
dbgi.acc.list_res <= list_res;
dbgi.acc.valid <= true;
dbgi.acc.debug <= debug;
dbgi.acc.cod <= 0;
pt_pci_master_sync_with_core(dbgi, dbgo);
dbgi.add <= false;
dbgi.acc.valid <= false;
end procedure;
procedure pt_add_acc_nb(
constant addr : std_logic_vector(31 downto 0);
constant cbe_cmd : std_logic_vector(3 downto 0);
constant data : std_logic_vector(31 downto 0);
constant cbe_data : std_logic_vector(3 downto 0);
constant waits : integer;
constant last : boolean;
constant parerr : integer;
constant id : integer;
constant debug : integer;
signal dbgi : out pt_pci_master_in_type;
signal dbgo : in pt_pci_master_out_type;
constant list_res : boolean := false) is
begin
dbgi.add <= true;
dbgi.remove <= false;
dbgi.get_res <= false;
dbgi.add_res <= false;
dbgi.acc.id <= id;
dbgi.acc.addr <= addr;
dbgi.acc.cbe_cmd <= cbe_cmd;
dbgi.acc.data <= data;
dbgi.acc.cbe_data <= cbe_data;
dbgi.acc.ws <= waits;
dbgi.acc.last <= last;
dbgi.acc.parerr <= parerr;
dbgi.acc.idle <= false;
dbgi.acc.list_res <= list_res;
dbgi.acc.valid <= true;
dbgi.acc.debug <= debug;
dbgi.acc.cod <= 0;
pt_pci_master_sync_with_core(dbgi, dbgo);
dbgi.add <= false;
dbgi.acc.valid <= false;
end procedure;
procedure pt_add_acc_nb(
constant addr : std_logic_vector(31 downto 0);
constant cbe_cmd : std_logic_vector(3 downto 0);
constant data : std_logic_vector(31 downto 0);
constant cbe_data : std_logic_vector(3 downto 0);
constant waits : integer;
constant last : boolean;
constant parerr : integer;
constant cod : integer;
constant id : integer;
constant debug : integer;
signal dbgi : out pt_pci_master_in_type;
signal dbgo : in pt_pci_master_out_type;
constant list_res : boolean := false) is
begin
dbgi.add <= true;
dbgi.remove <= false;
dbgi.get_res <= false;
dbgi.add_res <= false;
dbgi.acc.id <= id;
dbgi.acc.addr <= addr;
dbgi.acc.cbe_cmd <= cbe_cmd;
dbgi.acc.data <= data;
dbgi.acc.cbe_data <= cbe_data;
dbgi.acc.ws <= waits;
dbgi.acc.last <= last;
dbgi.acc.parerr <= parerr;
dbgi.acc.idle <= false;
dbgi.acc.list_res <= list_res;
dbgi.acc.valid <= true;
dbgi.acc.debug <= debug;
dbgi.acc.cod <= cod;
pt_pci_master_sync_with_core(dbgi, dbgo);
dbgi.add <= false;
dbgi.acc.valid <= false;
end procedure;
procedure pt_add_acc(
constant addr : std_logic_vector(31 downto 0);
constant cbe_cmd : std_logic_vector(3 downto 0);
constant data : std_logic_vector(31 downto 0);
constant cbe_data : std_logic_vector(3 downto 0);
constant waits : integer;
constant last : boolean;
constant parerr : integer;
constant id : integer;
constant debug : integer;
signal dbgi : out pt_pci_master_in_type;
signal dbgo : in pt_pci_master_out_type) is
begin
pt_add_acc_nb(addr, cbe_cmd , data, cbe_data, waits, last, parerr, id, debug, dbgi, dbgo, true);
while true loop
dbgi.get_res <= true;
dbgi.add <= false;
dbgi.remove <= false;
dbgi.add_res <= false;
dbgi.acc.id <= id;
dbgi.acc.addr <= (others => '0');
dbgi.acc.cbe_cmd <= (others => '0');
dbgi.acc.data <= (others => '0');
dbgi.acc.cbe_data <= (others => '0');
dbgi.acc.ws <= 0;
dbgi.acc.idle <= false;
dbgi.acc.list_res <= false;
dbgi.acc.valid <= true;
dbgi.acc.debug <= debug;
dbgi.acc.cod <= 0;
pt_pci_master_sync_with_core(dbgi, dbgo);
dbgi.add <= false;
dbgi.get_res <= false;
dbgi.acc.valid <= false;
if dbgo.valid = false then
while dbgo.res_found /= '1' loop
wait until dbgo.res_found = '1';
end loop;
else
exit;
end if;
end loop;
end procedure;
procedure pt_add_acc(
constant addr : std_logic_vector(31 downto 0);
constant cbe_cmd : std_logic_vector(3 downto 0);
constant data : std_logic_vector(31 downto 0);
constant cbe_data : std_logic_vector(3 downto 0);
constant waits : integer;
constant last : boolean;
constant parerr : integer;
constant cod : integer;
constant id : integer;
constant debug : integer;
signal dbgi : out pt_pci_master_in_type;
signal dbgo : in pt_pci_master_out_type) is
begin
pt_add_acc_nb(addr, cbe_cmd , data, cbe_data, waits, last, parerr, cod, id, debug, dbgi, dbgo, true);
while true loop
dbgi.get_res <= true;
dbgi.add <= false;
dbgi.remove <= false;
dbgi.add_res <= false;
dbgi.acc.id <= id;
dbgi.acc.addr <= (others => '0');
dbgi.acc.cbe_cmd <= (others => '0');
dbgi.acc.data <= (others => '0');
dbgi.acc.cbe_data <= (others => '0');
dbgi.acc.ws <= 0;
dbgi.acc.idle <= false;
dbgi.acc.list_res <= false;
dbgi.acc.valid <= true;
dbgi.acc.debug <= debug;
dbgi.acc.cod <= 0;
pt_pci_master_sync_with_core(dbgi, dbgo);
dbgi.add <= false;
dbgi.get_res <= false;
dbgi.acc.valid <= false;
if dbgo.valid = false then
while dbgo.res_found /= '1' loop
wait until dbgo.res_found = '1';
end loop;
else
exit;
end if;
end loop;
end procedure;
procedure pt_add_acc(
constant addr : std_logic_vector(31 downto 0);
constant cbe_cmd : std_logic_vector(3 downto 0);
constant data : std_logic_vector(31 downto 0);
constant cbe_data : std_logic_vector(3 downto 0);
constant waits : integer;
constant last : boolean;
constant id : integer;
constant debug : integer;
signal dbgi : out pt_pci_master_in_type;
signal dbgo : in pt_pci_master_out_type) is
begin
pt_add_acc_nb(addr, cbe_cmd , data, cbe_data, waits, last, id, debug, dbgi, dbgo, true);
while true loop
dbgi.get_res <= true;
dbgi.add <= false;
dbgi.remove <= false;
dbgi.add_res <= false;
dbgi.acc.id <= id;
dbgi.acc.addr <= (others => '0');
dbgi.acc.cbe_cmd <= (others => '0');
dbgi.acc.data <= (others => '0');
dbgi.acc.cbe_data <= (others => '0');
dbgi.acc.ws <= 0;
dbgi.acc.idle <= false;
dbgi.acc.list_res <= false;
dbgi.acc.valid <= true;
dbgi.acc.debug <= debug;
dbgi.acc.cod <= 0;
pt_pci_master_sync_with_core(dbgi, dbgo);
dbgi.add <= false;
dbgi.get_res <= false;
dbgi.acc.valid <= false;
if dbgo.valid = false then
while dbgo.res_found /= '1' loop
wait until dbgo.res_found = '1';
end loop;
else
exit;
end if;
end loop;
end procedure;
procedure pt_add_idle_nb(
constant waits : integer;
constant id : integer;
constant debug : integer;
signal dbgi : out pt_pci_master_in_type;
signal dbgo : in pt_pci_master_out_type;
constant list_res : boolean := false) is
begin
dbgi.add <= true;
dbgi.remove <= false;
dbgi.get_res <= false;
dbgi.add_res <= false;
dbgi.acc.id <= id;
dbgi.acc.addr <= (others => '0');
dbgi.acc.cbe_cmd <= (others => '0');
dbgi.acc.data <= (others => '0');
dbgi.acc.cbe_data <= (others => '0');
dbgi.acc.ws <= waits;
dbgi.acc.idle <= true;
dbgi.acc.list_res <= list_res;
dbgi.acc.valid <= true;
dbgi.acc.debug <= debug;
dbgi.acc.cod <= 0;
pt_pci_master_sync_with_core(dbgi, dbgo);
dbgi.add <= false;
dbgi.acc.valid <= false;
end procedure;
procedure pt_add_idle(
constant waits : integer;
constant id : integer;
constant debug : integer;
signal dbgi : out pt_pci_master_in_type;
signal dbgo : in pt_pci_master_out_type) is
begin
-- Add acc
pt_add_idle_nb(waits, id, debug, dbgi, dbgo, true);
while true loop
dbgi.get_res <= true;
dbgi.add <= false;
dbgi.remove <= false;
dbgi.add_res <= false;
dbgi.acc.id <= id;
dbgi.acc.addr <= (others => '0');
dbgi.acc.cbe_cmd <= (others => '0');
dbgi.acc.data <= (others => '0');
dbgi.acc.cbe_data <= (others => '0');
dbgi.acc.ws <= 0;
dbgi.acc.idle <= false;
dbgi.acc.list_res <= false;
dbgi.acc.valid <= true;
dbgi.acc.debug <= debug;
dbgi.acc.cod <= 0;
pt_pci_master_sync_with_core(dbgi, dbgo);
dbgi.add <= false;
dbgi.get_res <= false;
dbgi.acc.valid <= false;
if dbgo.valid = false then
while dbgo.res_found /= '1' loop
wait until dbgo.res_found = '1';
end loop;
else
exit;
end if;
end loop;
end procedure;
-----------------------------------------------------------------------------
-- PCI target procedures
-----------------------------------------------------------------------------
procedure pt_pci_target_sync_with_core(
signal dbgi : out pt_pci_target_in_type;
signal dbgo : in pt_pci_target_out_type) is
begin
dbgi.req <= '1';
wait until dbgo.ack = '1';
dbgi.req <= '0';
wait until dbgo.ack = '0';
end procedure pt_pci_target_sync_with_core;
procedure pt_insert_resp(
constant addr : std_logic_vector(31 downto 0);
constant retry : integer;
constant waits : integer;
constant discon: integer;
constant parerr: integer;
constant abort : integer;
constant debug : integer;
signal dbgi : out pt_pci_target_in_type;
signal dbgo : in pt_pci_target_out_type) is
begin
dbgi.insert <= '1';
dbgi.remove <= '0';
dbgi.resp.addr <= addr;
dbgi.resp.retry <= retry;
dbgi.resp.ws <= waits;
dbgi.resp.parerr <= parerr;
dbgi.resp.abort <= abort;
dbgi.resp.debug <= debug;
if discon = 1 then
dbgi.resp.diswith <= 1;
elsif discon = 2 then
dbgi.resp.diswithout <= 1;
else
dbgi.resp.diswith <= 0;
dbgi.resp.diswithout <= 0;
end if;
pt_pci_target_sync_with_core(dbgi, dbgo);
dbgi.insert <= '0';
end procedure;
procedure pt_remove_resp(
constant addr : std_logic_vector(31 downto 0);
constant rmall : boolean;
signal dbgi : out pt_pci_target_in_type;
signal dbgo : in pt_pci_target_out_type) is
begin
dbgi.insert <= '0';
dbgi.remove <= '1';
if rmall = true then dbgi.rmall <= '1';
else dbgi.rmall <= '0'; end if;
dbgi.addr <= addr;
pt_pci_target_sync_with_core(dbgi, dbgo);
dbgi.remove <= '0';
dbgi.rmall <= '0';
end procedure;
end pt_pkg;
| gpl-3.0 | c126382ddbbf670a9f436413725bba28 | 0.547081 | 3.556031 | false | false | false | false |
ggaray/nicsim-vhd | statsgen.vhd | 1 | 99,199 | -- NICSim-vhd: A VHDL-based modelling and simulation of NIC's buffers
-- Copyright (C) 2013 Godofredo R. Garay <godofredo.garay (-at-) gmail.com>
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
use std.textio.all;
library ieee;
use ieee.math_real.all; -- for uniform
entity statsgen is
port (
pciclk : in bit;
ethclk : in bit;
pktreceived : in bit;
pktsize : in integer; --in bytes
transfer_start_req : in bit;
transfer_end : in bit;
buffer_fill_level_in_bytes : in integer;
buffer_fill_level_in_data_units : in integer;
max_buffer_fill_level : in integer;
dropped_packets_count : in integer;
nic_proc_latency_cycles_counter_out : in integer;
acq_latency_cycles_counter_out : in integer;
arb_latency_cycles_counter_out : in integer;
target_latency_cycles_counter_out : in integer;
burst_cycles_counter_out : in integer;
dma_cycles_counter_out : in integer;
clock_counter_out : out integer
);
end statsgen;
architecture V1 of statsgen is
--------------- Bus width configuration ---------------
--constant bus_width_in_bits : integer := 32; -- PCI 33/32
constant bus_width_in_bits : integer := 64; -- PCI 66/64, PCI-X 133/64
constant bus_width_in_bytes : integer := bus_width_in_bits/8;
-- ***To be removed
--constant bus_width_in_bytes : integer := 4; -- PCI bus
--constant bus_width_in_bytes : integer := 8; -- PCI-X bus
--constant preamble : integer := 7;
--constant sof : integer := 1;
--------------- Buffer configuration ---------------
--constant buffer_size : integer := 10000; -- Number of memory locations
--------------- Descriptor size configuration ---------------
constant descriptor_size_in_bytes : integer := 16; -- Descriptor size in bytes
constant descriptor_size_in_data_blocks : integer := descriptor_size_in_bytes/bus_width_in_bytes;
-- ******To be removed
--constant descriptor_size_in_data_blocks : integer := 2; -- Descriptor size in data blocks (PCI-X bus)
--constant descriptor_size_in_data_blocks : integer := 4; -- Descriptor size in data blocks (PCI bus)
--------------- Size of the Ethernet frame fields ---------------
constant preamble_in_bytes : integer := 7;
constant sof_in_bytes : integer := 1;
constant destination_address_in_bytes : integer := 6;
constant source_address_in_bytes : integer := 6;
constant length_in_bytes : integer := 2;
constant checksum_in_bytes : integer := 4;
-- Variables needed for printing out simulation statistics
shared variable nic_processing_latency_cycles_count : natural := 0;
shared variable nic_overhead_cycles_count : natural := 0;
shared variable arbitration_latency_cycles_count : natural := 0;
shared variable acquisition_latency_cycles_count : natural := 0;
shared variable target_latency_cycles_count : natural := 0;
shared variable max_nic_latency_cycles_count : natural := 0;
shared variable max_arbitration_latency_cycles_count : natural := 0;
shared variable max_acquisition_latency_cycles_count : natural := 0;
shared variable max_target_latency_cycles_count : natural := 0;
shared variable transmission_cycles_count : natural := 0;
shared variable number_of_packet_being_transferred : natural := 0;
shared variable number_of_last_transferred_packet : natural := 0;
shared variable nic_latency_cycles_count_per_packet : natural := 0;
shared variable max_nic_latency_cycles_count_per_packet : natural := 0;
shared variable arbitration_latency_cycles_count_per_packet : natural := 0;
shared variable max_arbitration_latency_cycles_count_per_packet : natural := 0;
shared variable acquisition_latency_cycles_count_per_packet : natural := 0;
shared variable max_acquisition_latency_cycles_count_per_packet : natural := 0;
shared variable target_latency_cycles_count_per_packet : natural := 0;
shared variable max_target_latency_cycles_count_per_packet : natural := 0;
shared variable processing_cycle_of_the_last_processed_packet_by_nic : natural := 0;
shared variable processing_cycle_of_the_last_processed_packet_by_arb : natural := 0;
shared variable processing_cycle_of_the_last_processed_packet_by_acq : natural := 0;
shared variable processing_cycle_of_the_last_processed_packet_by_memsub : natural := 0;
shared variable received_packets_counter : natural := 0;
shared variable transferred_packets_count : natural := 0;
shared variable clock_counter_value : integer := 1;
shared variable data_units_received_count : integer := 0;
--shared variable descriptor_size : integer := 0;
shared variable data_units_received_rate : real := 0.0;
shared variable nic_rate : real;
shared variable arbctrl_rate : real;
shared variable acqctrl_rate : real;
shared variable memsub_rate : real;
shared variable clock_counter_for_computing_data_units_received_rate : natural := 0;
shared variable data_unit_size : integer := 0;
shared variable buff_fill_level : integer := 0;
shared variable max_buff_fill_level : integer := 0;
shared variable max_received_data_unit_size_in_bytes : integer := 0;
shared variable size_of_received_data_unit_in_bytes : integer := 0;
-- Output values
signal sig_clock_counter_value : integer := 1;
begin
clock_counter_out <= sig_clock_counter_value;
statsgen_fsm : process
type statsgen_state is (idle,
incrementing_nic_latency_cycles,
incrementing_nic_overhead_cycles,
incrementing_arbitration_latency_cycles_for_payload_transfer,
incrementing_acquisition_latency_cycles_for_payload_transfer,
incrementing_target_latency_cycles_for_payload_transfer,
incrementing_transmission_cycles_for_payload_transfer,
incrementing_arbitration_latency_cycles_for_descriptor_transfer,
incrementing_acquisition_latency_cycles_for_descriptor_transfer,
incrementing_target_latency_cycles_for_descriptor_transfer,
incrementing_transmission_cycles_for_descriptor_transfer,
incrementing_arbitration_latency_cycles_for_aborted_payload_transfer,
incrementing_acquisition_latency_cycles_for_aborted_payload_transfer,
incrementing_target_latency_cycles_for_aborted_payload_transfer,
incrementing_transmission_cycles_for_resuming_aborted_payload_transfer,
incrementing_arbitration_latency_cycles_for_aborted_descriptor_transfer,
incrementing_acquisition_latency_cycles_for_aborted_descriptor_transfer,
incrementing_target_latency_cycles_for_aborted_descriptor_transfer,
incrementing_transmission_cycles_for_resuming_aborted_descriptor_transfer);
variable state : statsgen_state := idle; --Initial state
variable next_state : statsgen_state := idle;
-- return_to_this_state is a temporal variable is used within the state incrementing_nic_latency_cycles
-- in order to return to the current state of the call
variable return_to_this_state : statsgen_state;
begin
wait until pciclk'event and pciclk = '1';
case state is
when idle =>
if buffer_fill_level_in_bytes = 0
and nic_proc_latency_cycles_counter_out = 0
and arb_latency_cycles_counter_out = 0
and acq_latency_cycles_counter_out = 0
and target_latency_cycles_counter_out = 0
and burst_cycles_counter_out = 0
and dma_cycles_counter_out = 0
then next_state := idle;
elsif buffer_fill_level_in_bytes > 0
and nic_proc_latency_cycles_counter_out = 0
and arb_latency_cycles_counter_out = 0
and acq_latency_cycles_counter_out = 0
and target_latency_cycles_counter_out = 0
and burst_cycles_counter_out = 0
and dma_cycles_counter_out = 0
then nic_overhead_cycles_count := nic_overhead_cycles_count + 1;
nic_latency_cycles_count_per_packet :=
(nic_overhead_cycles_count + nic_processing_latency_cycles_count) -
processing_cycle_of_the_last_processed_packet_by_nic;
return_to_this_state := incrementing_nic_latency_cycles;
assert false
report "statsgen_fsm: incrementing_nic_overhead_cycles"
severity note;
next_state := incrementing_nic_overhead_cycles;
elsif buffer_fill_level_in_bytes > 0
and nic_proc_latency_cycles_counter_out > 0
and arb_latency_cycles_counter_out = 0
and acq_latency_cycles_counter_out = 0
and target_latency_cycles_counter_out = 0
and burst_cycles_counter_out = 0
and dma_cycles_counter_out = 0
then nic_processing_latency_cycles_count := nic_processing_latency_cycles_count + 1;
nic_latency_cycles_count_per_packet :=
(nic_overhead_cycles_count + nic_processing_latency_cycles_count)
- processing_cycle_of_the_last_processed_packet_by_nic;
assert false
report "statsgen_fsm: incrementing_nic_latency_cycles"
severity note;
next_state := incrementing_nic_latency_cycles;
end if;
when incrementing_nic_latency_cycles =>
if buffer_fill_level_in_bytes > 0
and nic_proc_latency_cycles_counter_out > 0
and arb_latency_cycles_counter_out = 0
and acq_latency_cycles_counter_out = 0
and target_latency_cycles_counter_out = 0
and burst_cycles_counter_out = 0
and dma_cycles_counter_out = 0
then nic_processing_latency_cycles_count := nic_processing_latency_cycles_count + 1;
nic_latency_cycles_count_per_packet :=
(nic_overhead_cycles_count + nic_processing_latency_cycles_count)
- processing_cycle_of_the_last_processed_packet_by_nic;
next_state := incrementing_nic_latency_cycles;
elsif buffer_fill_level_in_bytes > 0
and nic_proc_latency_cycles_counter_out = 0
and arb_latency_cycles_counter_out = 0
and acq_latency_cycles_counter_out = 0
and target_latency_cycles_counter_out = 0
and burst_cycles_counter_out = 0
and dma_cycles_counter_out = 0
then nic_overhead_cycles_count := nic_overhead_cycles_count + 1;
nic_latency_cycles_count_per_packet :=
(nic_overhead_cycles_count + nic_processing_latency_cycles_count) -
processing_cycle_of_the_last_processed_packet_by_nic;
return_to_this_state := incrementing_arbitration_latency_cycles_for_payload_transfer;
assert false
report "statsgen_fsm: incrementing_nic_overhead_cycles"
severity note;
next_state := incrementing_nic_overhead_cycles;
elsif buffer_fill_level_in_bytes > 0
and nic_proc_latency_cycles_counter_out = 0
and arb_latency_cycles_counter_out > 0
and acq_latency_cycles_counter_out = 0
and target_latency_cycles_counter_out = 0
and burst_cycles_counter_out = 0
and dma_cycles_counter_out = 0
then arbitration_latency_cycles_count := arbitration_latency_cycles_count + 1;
arbitration_latency_cycles_count_per_packet :=
arbitration_latency_cycles_count - processing_cycle_of_the_last_processed_packet_by_arb;
assert false
report "statsgen_fsm: incrementing_arbitration_latency_cycles_for_payload_transfer"
severity note;
next_state := incrementing_arbitration_latency_cycles_for_payload_transfer;
end if;
-- **************** INICIO de incrementing_nic_overhead_cycles
when incrementing_nic_overhead_cycles =>
if buffer_fill_level_in_bytes = 0
and transfer_end = '0' --We need to wait the falling edge of transfer_end
and nic_proc_latency_cycles_counter_out = 0
and arb_latency_cycles_counter_out = 0
and acq_latency_cycles_counter_out = 0
and target_latency_cycles_counter_out = 0
and burst_cycles_counter_out = 0
and dma_cycles_counter_out = 0
then assert false
report "statsgen_fsm: idle"
severity note;
next_state := idle;
elsif buffer_fill_level_in_bytes = 0
and transfer_end = '1' --We need to wait the falling edge of transfer_end
and nic_proc_latency_cycles_counter_out = 0
and arb_latency_cycles_counter_out = 0
and acq_latency_cycles_counter_out = 0
and target_latency_cycles_counter_out = 0
and burst_cycles_counter_out = 0
and dma_cycles_counter_out = 0
then nic_overhead_cycles_count := nic_overhead_cycles_count + 1;
nic_latency_cycles_count_per_packet :=
(nic_overhead_cycles_count + nic_processing_latency_cycles_count) -
processing_cycle_of_the_last_processed_packet_by_nic;
next_state := incrementing_nic_overhead_cycles;
elsif buffer_fill_level_in_bytes = 0
and transfer_end = '0'
then nic_overhead_cycles_count := nic_overhead_cycles_count + 1;
nic_latency_cycles_count_per_packet :=
(nic_overhead_cycles_count + nic_processing_latency_cycles_count) -
processing_cycle_of_the_last_processed_packet_by_nic;
next_state := incrementing_nic_overhead_cycles;
elsif buffer_fill_level_in_bytes = 0
and transfer_end = '1'
then assert false
report "statsgen_fsm: idle"
severity note;
next_state := idle;
elsif buffer_fill_level_in_bytes > 0
and nic_proc_latency_cycles_counter_out = 0
and arb_latency_cycles_counter_out = 0
and acq_latency_cycles_counter_out = 0
and target_latency_cycles_counter_out = 0
--and burst_cycles_counter_out = 0
and dma_cycles_counter_out = 0
then nic_overhead_cycles_count := nic_overhead_cycles_count + 1;
nic_latency_cycles_count_per_packet :=
(nic_overhead_cycles_count + nic_processing_latency_cycles_count) -
processing_cycle_of_the_last_processed_packet_by_nic;
next_state := incrementing_nic_overhead_cycles;
elsif buffer_fill_level_in_bytes > 0
and nic_proc_latency_cycles_counter_out > 0
and arb_latency_cycles_counter_out = 0
and acq_latency_cycles_counter_out = 0
and target_latency_cycles_counter_out = 0
--and burst_cycles_counter_out = 0
and dma_cycles_counter_out = 0
and return_to_this_state = incrementing_nic_latency_cycles
then nic_processing_latency_cycles_count := nic_processing_latency_cycles_count + 1;
nic_latency_cycles_count_per_packet :=
(nic_overhead_cycles_count + nic_processing_latency_cycles_count) -
processing_cycle_of_the_last_processed_packet_by_nic;
assert false
report "statsgen_fsm: incrementing_nic_latency_cycles"
severity note;
next_state := incrementing_nic_latency_cycles;
elsif buffer_fill_level_in_bytes > 0
and nic_proc_latency_cycles_counter_out = 0
and arb_latency_cycles_counter_out > 0
and acq_latency_cycles_counter_out = 0
and target_latency_cycles_counter_out = 0
--and burst_cycles_counter_out = 0
and dma_cycles_counter_out = 0
and return_to_this_state = incrementing_arbitration_latency_cycles_for_payload_transfer
then arbitration_latency_cycles_count := arbitration_latency_cycles_count + 1;
arbitration_latency_cycles_count_per_packet :=
arbitration_latency_cycles_count - processing_cycle_of_the_last_processed_packet_by_arb;
assert false
report "statsgen_fsm: incrementing_arbitration_latency_cycles_for_payload_transfer"
severity note;
next_state := incrementing_arbitration_latency_cycles_for_payload_transfer;
elsif buffer_fill_level_in_bytes > 0
and nic_proc_latency_cycles_counter_out = 0
and arb_latency_cycles_counter_out > 0
and acq_latency_cycles_counter_out = 0
and target_latency_cycles_counter_out = 0
--and burst_cycles_counter_out = 0
and dma_cycles_counter_out = 0
and return_to_this_state = incrementing_arbitration_latency_cycles_for_descriptor_transfer
then arbitration_latency_cycles_count := arbitration_latency_cycles_count + 1;
arbitration_latency_cycles_count_per_packet :=
arbitration_latency_cycles_count - processing_cycle_of_the_last_processed_packet_by_arb;
assert false
report "statsgen_fsm: incrementing_arbitration_latency_cycles_for_descriptor_transfer"
severity note;
next_state := incrementing_arbitration_latency_cycles_for_descriptor_transfer;
elsif buffer_fill_level_in_bytes > 0
and nic_proc_latency_cycles_counter_out = 0
and arb_latency_cycles_counter_out = 0
and acq_latency_cycles_counter_out > 0
and target_latency_cycles_counter_out = 0
--and burst_cycles_counter_out = 0
and dma_cycles_counter_out = 0
and return_to_this_state = incrementing_acquisition_latency_cycles_for_payload_transfer
then acquisition_latency_cycles_count := acquisition_latency_cycles_count + 1;
acquisition_latency_cycles_count_per_packet :=
acquisition_latency_cycles_count - processing_cycle_of_the_last_processed_packet_by_acq;
assert false
report "statsgen_fsm: incrementing_acquisition_latency_cycles_for_payload_transfer"
severity note;
next_state := incrementing_acquisition_latency_cycles_for_payload_transfer;
elsif buffer_fill_level_in_bytes > 0
and nic_proc_latency_cycles_counter_out = 0
and arb_latency_cycles_counter_out = 0
and acq_latency_cycles_counter_out > 0
and target_latency_cycles_counter_out = 0
--and burst_cycles_counter_out = 0
and dma_cycles_counter_out = 0
and return_to_this_state = incrementing_acquisition_latency_cycles_for_descriptor_transfer
then acquisition_latency_cycles_count := acquisition_latency_cycles_count + 1;
acquisition_latency_cycles_count_per_packet :=
acquisition_latency_cycles_count - processing_cycle_of_the_last_processed_packet_by_acq;
assert false
report "statsgen_fsm: incrementing_acquisition_latency_cycles_for_descriptor_transfer"
severity note;
next_state := incrementing_acquisition_latency_cycles_for_descriptor_transfer;
elsif buffer_fill_level_in_bytes > 0
and nic_proc_latency_cycles_counter_out = 0
and arb_latency_cycles_counter_out = 0
and acq_latency_cycles_counter_out = 0
and target_latency_cycles_counter_out > 0
--and burst_cycles_counter_out = 0
and dma_cycles_counter_out = 0
and return_to_this_state = incrementing_target_latency_cycles_for_payload_transfer
then target_latency_cycles_count := target_latency_cycles_count + 1;
target_latency_cycles_count_per_packet :=
target_latency_cycles_count - processing_cycle_of_the_last_processed_packet_by_memsub;
assert false
report "statsgen_fsm: incrementing_target_latency_cycles_for_payload_transfer"
severity note;
next_state := incrementing_target_latency_cycles_for_payload_transfer;
elsif buffer_fill_level_in_bytes > 0
and nic_proc_latency_cycles_counter_out = 0
and arb_latency_cycles_counter_out = 0
and acq_latency_cycles_counter_out = 0
and target_latency_cycles_counter_out > 0
--and burst_cycles_counter_out = 0
and dma_cycles_counter_out = 0
and return_to_this_state = incrementing_target_latency_cycles_for_descriptor_transfer
then target_latency_cycles_count := target_latency_cycles_count + 1;
target_latency_cycles_count_per_packet :=
target_latency_cycles_count - processing_cycle_of_the_last_processed_packet_by_memsub;
assert false
report "statsgen_fsm: incrementing_target_latency_cycles_for_descriptor_transfer"
severity note;
next_state := incrementing_target_latency_cycles_for_descriptor_transfer;
elsif buffer_fill_level_in_bytes > 0
and nic_proc_latency_cycles_counter_out = 0
and arb_latency_cycles_counter_out = 0
and acq_latency_cycles_counter_out = 0
and target_latency_cycles_counter_out = 0
and dma_cycles_counter_out > 0
and burst_cycles_counter_out > 0
and return_to_this_state = incrementing_transmission_cycles_for_payload_transfer
then transmission_cycles_count := transmission_cycles_count + 1;
assert false
report "statsgen_fsm: incrementing_transmission_cycles_for_payload_transfer"
severity note;
next_state := incrementing_transmission_cycles_for_payload_transfer;
elsif buffer_fill_level_in_bytes > 0
and nic_proc_latency_cycles_counter_out = 0
and arb_latency_cycles_counter_out = 0
and acq_latency_cycles_counter_out = 0
and target_latency_cycles_counter_out = 0
and dma_cycles_counter_out > 0
and burst_cycles_counter_out > 0
and return_to_this_state = incrementing_transmission_cycles_for_descriptor_transfer
then transmission_cycles_count := transmission_cycles_count + 1;
assert false
report "statsgen_fsm: incrementing_transmission_cycles_for_descriptor_transfer"
severity note;
next_state := incrementing_transmission_cycles_for_descriptor_transfer;
-- elsif buffer_fill_level_in_bytes > 0
-- and nic_proc_latency_cycles_counter_out = 0
-- and arb_latency_cycles_counter_out = 0
-- and acq_latency_cycles_counter_out = 0
-- and target_latency_cycles_counter_out > 0
-- and burst_cycles_counter_out = 0
-- and dma_cycles_counter_out = 0
-- and return_to_this_state = incrementing_target_latency_cycles_for_payload_transfer
-- then target_latency_cycles_count := target_latency_cycles_count + 1;
-- target_latency_cycles_count_per_packet :=
-- target_latency_cycles_count - processing_cycle_of_the_last_processed_packet_by_memsub;
-- assert false
-- report "statsgen_fsm: incrementing_target_latency_cycles_for_payload_transfer"
-- severity note;
-- next_state := incrementing_target_latency_cycles_for_payload_transfer;
------------------------------------------------
-- Aborted payload transfer scenario
------------------------------------------------
-- Case 1: Transitions from NIC overhead state to the arbitration, acquisition and target latencies ()
elsif buffer_fill_level_in_bytes > 0
and nic_proc_latency_cycles_counter_out = 0
and arb_latency_cycles_counter_out = 0
and acq_latency_cycles_counter_out = 0
and target_latency_cycles_counter_out = 0
and burst_cycles_counter_out = 0
and dma_cycles_counter_out > 0
then nic_overhead_cycles_count := nic_overhead_cycles_count + 1;
nic_latency_cycles_count_per_packet :=
(nic_overhead_cycles_count + nic_processing_latency_cycles_count) -
processing_cycle_of_the_last_processed_packet_by_nic;
next_state := incrementing_nic_overhead_cycles;
elsif buffer_fill_level_in_bytes > 0
and nic_proc_latency_cycles_counter_out = 0
and arb_latency_cycles_counter_out > 0
and acq_latency_cycles_counter_out = 0
and target_latency_cycles_counter_out = 0
and burst_cycles_counter_out = 0
and dma_cycles_counter_out > 0
and return_to_this_state = incrementing_arbitration_latency_cycles_for_aborted_payload_transfer
then arbitration_latency_cycles_count := arbitration_latency_cycles_count + 1;
arbitration_latency_cycles_count_per_packet :=
arbitration_latency_cycles_count - processing_cycle_of_the_last_processed_packet_by_arb;
assert false
report "statsgen_fsm: incrementing_arbitration_latency_cycles_for_aborted_payload_transfer"
severity note;
next_state := incrementing_arbitration_latency_cycles_for_aborted_payload_transfer;
elsif buffer_fill_level_in_bytes > 0
and nic_proc_latency_cycles_counter_out = 0
and arb_latency_cycles_counter_out = 0
and acq_latency_cycles_counter_out > 0
and target_latency_cycles_counter_out = 0
and burst_cycles_counter_out = 0
and dma_cycles_counter_out > 0
and return_to_this_state = incrementing_acquisition_latency_cycles_for_aborted_payload_transfer
then acquisition_latency_cycles_count := acquisition_latency_cycles_count + 1;
acquisition_latency_cycles_count_per_packet :=
acquisition_latency_cycles_count - processing_cycle_of_the_last_processed_packet_by_acq;
assert false
report "statsgen_fsm: incrementing_acquisition_latency_cycles_for_aborted_payload_transfer"
severity note;
next_state := incrementing_acquisition_latency_cycles_for_aborted_payload_transfer;
elsif buffer_fill_level_in_bytes > 0
and nic_proc_latency_cycles_counter_out = 0
and arb_latency_cycles_counter_out = 0
and acq_latency_cycles_counter_out = 0
and target_latency_cycles_counter_out > 0
and burst_cycles_counter_out = 0
and dma_cycles_counter_out > 0
and return_to_this_state = incrementing_target_latency_cycles_for_aborted_payload_transfer
then target_latency_cycles_count := target_latency_cycles_count + 1;
target_latency_cycles_count_per_packet :=
target_latency_cycles_count - processing_cycle_of_the_last_processed_packet_by_memsub;
assert false
report "statsgen_fsm: incrementing_target_latency_cycles_for_aborted_payload_transfer"
severity note;
next_state := incrementing_target_latency_cycles_for_aborted_payload_transfer;
elsif buffer_fill_level_in_bytes > 0
and nic_proc_latency_cycles_counter_out = 0
and arb_latency_cycles_counter_out = 0
and acq_latency_cycles_counter_out = 0
and target_latency_cycles_counter_out = 0
and burst_cycles_counter_out > 0
and dma_cycles_counter_out > 0
--and resume_aborted_payload_transfer = '0'
and return_to_this_state = incrementing_transmission_cycles_for_resuming_aborted_payload_transfer
then transmission_cycles_count := transmission_cycles_count + 1;
assert false
report "statsgen_fsm: incrementing_transmission_cycles_for_resuming_aborted_payload_transfer"
severity note;
next_state := incrementing_transmission_cycles_for_resuming_aborted_payload_transfer;
elsif buffer_fill_level_in_bytes > 0
and nic_proc_latency_cycles_counter_out = 0
and arb_latency_cycles_counter_out = 0
and acq_latency_cycles_counter_out = 0
and target_latency_cycles_counter_out = 0
and burst_cycles_counter_out = 0
and dma_cycles_counter_out > 0
and return_to_this_state = incrementing_arbitration_latency_cycles_for_aborted_descriptor_transfer
then arbitration_latency_cycles_count := arbitration_latency_cycles_count + 1;
arbitration_latency_cycles_count_per_packet :=
arbitration_latency_cycles_count - processing_cycle_of_the_last_processed_packet_by_arb;
assert false
report "statsgen_fsm: incrementing_arbitration_latency_cycles_for_aborted_descriptor_transfer"
severity note;
next_state := incrementing_arbitration_latency_cycles_for_aborted_descriptor_transfer;
elsif buffer_fill_level_in_bytes > 0
and nic_proc_latency_cycles_counter_out = 0
and arb_latency_cycles_counter_out = 0
and acq_latency_cycles_counter_out = 0
and target_latency_cycles_counter_out = 0
and burst_cycles_counter_out = 0
and dma_cycles_counter_out > 0
and return_to_this_state = incrementing_acquisition_latency_cycles_for_aborted_descriptor_transfer
then acquisition_latency_cycles_count := acquisition_latency_cycles_count + 1;
acquisition_latency_cycles_count_per_packet :=
acquisition_latency_cycles_count - processing_cycle_of_the_last_processed_packet_by_acq;
assert false
report "statsgen_fsm: incrementing_acquisition_latency_cycles_for_aborted_descriptor_transfer"
severity note;
next_state := incrementing_acquisition_latency_cycles_for_aborted_descriptor_transfer;
elsif buffer_fill_level_in_bytes > 0
and nic_proc_latency_cycles_counter_out = 0
and arb_latency_cycles_counter_out = 0
and acq_latency_cycles_counter_out = 0
and target_latency_cycles_counter_out = 0
and burst_cycles_counter_out = 0
and dma_cycles_counter_out > 0
and return_to_this_state = incrementing_target_latency_cycles_for_aborted_descriptor_transfer
then target_latency_cycles_count := target_latency_cycles_count + 1;
target_latency_cycles_count_per_packet :=
target_latency_cycles_count - processing_cycle_of_the_last_processed_packet_by_memsub;
assert false
report "statsgen_fsm: incrementing_target_latency_cycles_for_aborted_descriptor_transfer"
severity note;
next_state := incrementing_target_latency_cycles_for_aborted_descriptor_transfer;
elsif buffer_fill_level_in_bytes > 0
and nic_proc_latency_cycles_counter_out = 0
and arb_latency_cycles_counter_out = 0
and acq_latency_cycles_counter_out = 0
and target_latency_cycles_counter_out = 0
and burst_cycles_counter_out = 0
and dma_cycles_counter_out > 0
--and resume_aborted_descriptor_transfer = '0'
and return_to_this_state = incrementing_transmission_cycles_for_resuming_aborted_descriptor_transfer
then transmission_cycles_count := transmission_cycles_count + 1;
assert false
report "statsgen_fsm: incrementing_transmission_cycles_for_resuming_aborted_descriptor_transfer"
severity note;
next_state := incrementing_transmission_cycles_for_resuming_aborted_descriptor_transfer;
------------------------------------------------
-- Aborted descriptor transfer scenario
------------------------------------------------
end if;
-- ************** FIN de incrementing_nic_overhead_cycles
when incrementing_arbitration_latency_cycles_for_payload_transfer =>
if buffer_fill_level_in_bytes > 0
and nic_proc_latency_cycles_counter_out = 0
and arb_latency_cycles_counter_out > 0
and acq_latency_cycles_counter_out = 0
and target_latency_cycles_counter_out = 0
and dma_cycles_counter_out = 0
then arbitration_latency_cycles_count := arbitration_latency_cycles_count + 1;
arbitration_latency_cycles_count_per_packet :=
arbitration_latency_cycles_count - processing_cycle_of_the_last_processed_packet_by_arb;
next_state := incrementing_arbitration_latency_cycles_for_payload_transfer;
elsif buffer_fill_level_in_bytes > 0
and nic_proc_latency_cycles_counter_out = 0
and arb_latency_cycles_counter_out = 0
and acq_latency_cycles_counter_out = 0
and target_latency_cycles_counter_out = 0
and dma_cycles_counter_out = 0
then nic_overhead_cycles_count := nic_overhead_cycles_count + 1;
nic_latency_cycles_count_per_packet :=
(nic_overhead_cycles_count + nic_processing_latency_cycles_count) -
processing_cycle_of_the_last_processed_packet_by_nic;
return_to_this_state := incrementing_acquisition_latency_cycles_for_payload_transfer;
assert false
report "statsgen_fsm: incrementing_nic_overhead_cycles"
severity note;
next_state := incrementing_nic_overhead_cycles;
elsif buffer_fill_level_in_bytes > 0
and nic_proc_latency_cycles_counter_out = 0
and arb_latency_cycles_counter_out = 0
and acq_latency_cycles_counter_out > 0
and target_latency_cycles_counter_out = 0
and dma_cycles_counter_out = 0
then acquisition_latency_cycles_count := acquisition_latency_cycles_count + 1;
acquisition_latency_cycles_count_per_packet :=
acquisition_latency_cycles_count - processing_cycle_of_the_last_processed_packet_by_acq;
assert false
report "statsgen_fsm: incrementing_acquisition_latency_cycles_for_payload_transfer"
severity note;
next_state := incrementing_acquisition_latency_cycles_for_payload_transfer;
end if;
when incrementing_acquisition_latency_cycles_for_payload_transfer =>
if buffer_fill_level_in_bytes > 0
and nic_proc_latency_cycles_counter_out = 0
and arb_latency_cycles_counter_out = 0
and acq_latency_cycles_counter_out > 0
and target_latency_cycles_counter_out = 0
and dma_cycles_counter_out = 0
then acquisition_latency_cycles_count := acquisition_latency_cycles_count + 1;
acquisition_latency_cycles_count_per_packet :=
acquisition_latency_cycles_count - processing_cycle_of_the_last_processed_packet_by_acq;
next_state := incrementing_acquisition_latency_cycles_for_payload_transfer;
elsif buffer_fill_level_in_bytes > 0
and nic_proc_latency_cycles_counter_out = 0
and arb_latency_cycles_counter_out = 0
and acq_latency_cycles_counter_out = 0
and target_latency_cycles_counter_out = 0
and dma_cycles_counter_out = 0
then nic_overhead_cycles_count := nic_overhead_cycles_count + 1;
nic_latency_cycles_count_per_packet :=
(nic_overhead_cycles_count + nic_processing_latency_cycles_count) -
processing_cycle_of_the_last_processed_packet_by_nic;
return_to_this_state := incrementing_target_latency_cycles_for_payload_transfer;
assert false
report "statsgen_fsm: incrementing_nic_overhead_cycles"
severity note;
next_state := incrementing_nic_overhead_cycles;
elsif buffer_fill_level_in_bytes > 0
and nic_proc_latency_cycles_counter_out = 0
and arb_latency_cycles_counter_out = 0
and acq_latency_cycles_counter_out = 0
and target_latency_cycles_counter_out > 0
and dma_cycles_counter_out = 0
then target_latency_cycles_count := target_latency_cycles_count + 1;
target_latency_cycles_count_per_packet :=
target_latency_cycles_count - processing_cycle_of_the_last_processed_packet_by_memsub;
assert false
report "statsgen_fsm: incrementing_target_latency_cycles_for_payload_transfer"
severity note;
next_state := incrementing_target_latency_cycles_for_payload_transfer;
end if;
when incrementing_target_latency_cycles_for_payload_transfer =>
if buffer_fill_level_in_bytes > 0
and nic_proc_latency_cycles_counter_out = 0
and arb_latency_cycles_counter_out = 0
and acq_latency_cycles_counter_out = 0
and target_latency_cycles_counter_out > 0
and dma_cycles_counter_out = 0
and burst_cycles_counter_out = 0
then target_latency_cycles_count := target_latency_cycles_count + 1;
target_latency_cycles_count_per_packet :=
target_latency_cycles_count - processing_cycle_of_the_last_processed_packet_by_memsub;
next_state := incrementing_target_latency_cycles_for_payload_transfer;
elsif buffer_fill_level_in_bytes > 0
and nic_proc_latency_cycles_counter_out = 0
and arb_latency_cycles_counter_out = 0
and acq_latency_cycles_counter_out = 0
and target_latency_cycles_counter_out = 0
and dma_cycles_counter_out = 0
and burst_cycles_counter_out = 0
then nic_overhead_cycles_count := nic_overhead_cycles_count + 1;
nic_latency_cycles_count_per_packet :=
(nic_overhead_cycles_count + nic_processing_latency_cycles_count) -
processing_cycle_of_the_last_processed_packet_by_nic;
return_to_this_state := incrementing_transmission_cycles_for_payload_transfer;
assert false
report "statsgen_fsm: incrementing_nic_overhead_cycles"
severity note;
next_state := incrementing_nic_overhead_cycles;
elsif buffer_fill_level_in_bytes > 0
and nic_proc_latency_cycles_counter_out = 0
and arb_latency_cycles_counter_out = 0
and acq_latency_cycles_counter_out = 0
and target_latency_cycles_counter_out = 0
and dma_cycles_counter_out > 0
--and payload_transfer_req = '0'
then transmission_cycles_count := transmission_cycles_count + 1;
assert false
report "statsgen_fsm: incrementing_transmission_cycles_for_payload_transfer"
severity note;
next_state := incrementing_transmission_cycles_for_payload_transfer;
end if;
when incrementing_transmission_cycles_for_payload_transfer =>
if buffer_fill_level_in_bytes > 0
and nic_proc_latency_cycles_counter_out = 0
and arb_latency_cycles_counter_out = 0
and acq_latency_cycles_counter_out = 0
and target_latency_cycles_counter_out = 0
and burst_cycles_counter_out > 0 -- we keep incrementing transmission cycles count until burst counter reach zero
and dma_cycles_counter_out > 0
--and payload_transfer_req = '0' -- better, payload_transfer_aborted?
--and payload_transfer_aborted = '0'
then transmission_cycles_count := transmission_cycles_count + 1;
next_state := incrementing_transmission_cycles_for_payload_transfer;
elsif buffer_fill_level_in_bytes > 0
and nic_proc_latency_cycles_counter_out = 0
and arb_latency_cycles_counter_out > 0 -- In this case, no overhead happen after completing successfully dma transfer
and acq_latency_cycles_counter_out = 0
and target_latency_cycles_counter_out = 0
--and burst_cycles_counter_out > 0
and dma_cycles_counter_out = 0 -- Transfer is not aborted
--and payload_transfer_req = '0' -- better, payload_transfer_aborted?
--and payload_transfer_aborted = '0' -- Transfer is not aborted
then arbitration_latency_cycles_count := arbitration_latency_cycles_count + 1;
arbitration_latency_cycles_count_per_packet :=
arbitration_latency_cycles_count - processing_cycle_of_the_last_processed_packet_by_arb;
assert false
report "statsgen_fsm: incrementing_arbitration_latency_cycles_for_descriptor_transfer"
severity note;
next_state := incrementing_arbitration_latency_cycles_for_descriptor_transfer;
elsif buffer_fill_level_in_bytes > 0
and nic_proc_latency_cycles_counter_out = 0
and arb_latency_cycles_counter_out = 0
and acq_latency_cycles_counter_out = 0
and target_latency_cycles_counter_out = 0
--and burst_cycles_counter_out > 0
and dma_cycles_counter_out = 0 -- Transfer is not aborted
--and payload_transfer_aborted = '0' -- Transfer is not aborted
then nic_overhead_cycles_count := nic_overhead_cycles_count + 1;
nic_latency_cycles_count_per_packet :=
(nic_overhead_cycles_count + nic_processing_latency_cycles_count) -
processing_cycle_of_the_last_processed_packet_by_nic;
return_to_this_state := incrementing_arbitration_latency_cycles_for_descriptor_transfer;
assert false
report "statsgen_fsm: incrementing_nic_overhead_cycles"
severity note;
next_state := incrementing_nic_overhead_cycles;
elsif buffer_fill_level_in_bytes > 0
and nic_proc_latency_cycles_counter_out = 0
and arb_latency_cycles_counter_out = 0
and acq_latency_cycles_counter_out = 0
and target_latency_cycles_counter_out = 0
and burst_cycles_counter_out = 0 -- End of DMA transfer cycles
and dma_cycles_counter_out > 0 -- Transfer is aborted, dma counter is not equals to 0
--and payload_transfer_aborted = '1' -- Transfer is aborted, dma counter is not equals to 0
then nic_overhead_cycles_count := nic_overhead_cycles_count + 1;
nic_latency_cycles_count_per_packet :=
(nic_overhead_cycles_count + nic_processing_latency_cycles_count) -
processing_cycle_of_the_last_processed_packet_by_nic;
return_to_this_state := incrementing_arbitration_latency_cycles_for_aborted_payload_transfer;
assert false
report "statsgen_fsm: incrementing_nic_overhead_cycle"
severity note;
next_state := incrementing_nic_overhead_cycles;
end if;
when incrementing_arbitration_latency_cycles_for_descriptor_transfer =>
if buffer_fill_level_in_bytes > 0
and nic_proc_latency_cycles_counter_out = 0
and arb_latency_cycles_counter_out > 0
and acq_latency_cycles_counter_out = 0
and target_latency_cycles_counter_out = 0
and dma_cycles_counter_out = 0
then arbitration_latency_cycles_count := arbitration_latency_cycles_count + 1;
arbitration_latency_cycles_count_per_packet :=
arbitration_latency_cycles_count - processing_cycle_of_the_last_processed_packet_by_arb;
next_state := incrementing_arbitration_latency_cycles_for_descriptor_transfer;
elsif buffer_fill_level_in_bytes > 0
and nic_proc_latency_cycles_counter_out = 0
and arb_latency_cycles_counter_out = 0
and acq_latency_cycles_counter_out = 0
and target_latency_cycles_counter_out = 0
and dma_cycles_counter_out = 0
then nic_overhead_cycles_count := nic_overhead_cycles_count + 1;
nic_latency_cycles_count_per_packet :=
(nic_overhead_cycles_count + nic_processing_latency_cycles_count) -
processing_cycle_of_the_last_processed_packet_by_nic;
return_to_this_state := incrementing_acquisition_latency_cycles_for_descriptor_transfer;
assert false
report "statsgen_fsm: incrementing_nic_overhead_cycles"
severity note;
next_state := incrementing_nic_overhead_cycles;
elsif buffer_fill_level_in_bytes > 0
and nic_proc_latency_cycles_counter_out = 0
and arb_latency_cycles_counter_out = 0
and acq_latency_cycles_counter_out > 0
and target_latency_cycles_counter_out = 0
and dma_cycles_counter_out = 0
then acquisition_latency_cycles_count := acquisition_latency_cycles_count + 1;
acquisition_latency_cycles_count_per_packet :=
acquisition_latency_cycles_count - processing_cycle_of_the_last_processed_packet_by_acq;
assert false
report "statsgen_fsm: incrementing_acquisition_latency_cycles_for_descriptor_transfer"
severity note;
next_state := incrementing_acquisition_latency_cycles_for_descriptor_transfer;
end if;
when incrementing_acquisition_latency_cycles_for_descriptor_transfer =>
if buffer_fill_level_in_bytes > 0
and nic_proc_latency_cycles_counter_out = 0
and arb_latency_cycles_counter_out = 0
and acq_latency_cycles_counter_out > 0
and target_latency_cycles_counter_out = 0
and dma_cycles_counter_out = 0
then acquisition_latency_cycles_count := acquisition_latency_cycles_count + 1;
acquisition_latency_cycles_count_per_packet :=
acquisition_latency_cycles_count - processing_cycle_of_the_last_processed_packet_by_acq;
next_state := incrementing_acquisition_latency_cycles_for_descriptor_transfer;
elsif buffer_fill_level_in_bytes > 0
and nic_proc_latency_cycles_counter_out = 0
and arb_latency_cycles_counter_out = 0
and acq_latency_cycles_counter_out = 0
and target_latency_cycles_counter_out = 0
and dma_cycles_counter_out = 0
then nic_overhead_cycles_count := nic_overhead_cycles_count + 1;
nic_latency_cycles_count_per_packet :=
(nic_overhead_cycles_count + nic_processing_latency_cycles_count) -
processing_cycle_of_the_last_processed_packet_by_nic;
return_to_this_state := incrementing_target_latency_cycles_for_descriptor_transfer;
assert false
report "statsgen_fsm: incrementing_nic_overhead_cycles"
severity note;
next_state := incrementing_nic_overhead_cycles;
elsif buffer_fill_level_in_bytes > 0
and nic_proc_latency_cycles_counter_out = 0
and arb_latency_cycles_counter_out = 0
and acq_latency_cycles_counter_out = 0
and target_latency_cycles_counter_out > 0
and dma_cycles_counter_out = 0
then target_latency_cycles_count := target_latency_cycles_count + 1;
target_latency_cycles_count_per_packet :=
target_latency_cycles_count - processing_cycle_of_the_last_processed_packet_by_memsub;
assert false
report "statsgen_fsm: incrementing_target_latency_cycles_for_descriptor_transfer"
severity note;
next_state := incrementing_target_latency_cycles_for_descriptor_transfer;
end if;
when incrementing_target_latency_cycles_for_descriptor_transfer =>
if buffer_fill_level_in_bytes > 0
and nic_proc_latency_cycles_counter_out = 0
and arb_latency_cycles_counter_out = 0
and acq_latency_cycles_counter_out = 0
and target_latency_cycles_counter_out > 0
and dma_cycles_counter_out = 0
then target_latency_cycles_count := target_latency_cycles_count + 1;
target_latency_cycles_count_per_packet :=
target_latency_cycles_count - processing_cycle_of_the_last_processed_packet_by_memsub;
next_state := incrementing_target_latency_cycles_for_descriptor_transfer;
elsif buffer_fill_level_in_bytes > 0
and nic_proc_latency_cycles_counter_out = 0
and arb_latency_cycles_counter_out = 0
and acq_latency_cycles_counter_out = 0
and target_latency_cycles_counter_out = 0
and dma_cycles_counter_out = 0
then nic_overhead_cycles_count := nic_overhead_cycles_count + 1;
nic_latency_cycles_count_per_packet :=
(nic_overhead_cycles_count + nic_processing_latency_cycles_count) -
processing_cycle_of_the_last_processed_packet_by_nic;
return_to_this_state := incrementing_transmission_cycles_for_descriptor_transfer;
assert false
report "statsgen_fsm: incrementing_nic_overhead_cycles"
severity note;
next_state := incrementing_nic_overhead_cycles;
elsif buffer_fill_level_in_bytes > 0
and nic_proc_latency_cycles_counter_out = 0
and arb_latency_cycles_counter_out = 0
and acq_latency_cycles_counter_out = 0
and target_latency_cycles_counter_out = 0
and dma_cycles_counter_out > 0
--and descriptor_transfer_req = '0'
then transmission_cycles_count := transmission_cycles_count + 1;
assert false
report "statsgen_fsm: incrementing_transmission_cycles_for_descriptor_transfer"
severity note;
next_state := incrementing_transmission_cycles_for_descriptor_transfer;
end if;
when incrementing_transmission_cycles_for_descriptor_transfer =>
if buffer_fill_level_in_bytes > 0
and nic_proc_latency_cycles_counter_out = 0
and arb_latency_cycles_counter_out = 0
and acq_latency_cycles_counter_out = 0
and target_latency_cycles_counter_out = 0
and dma_cycles_counter_out > 0
--and descriptor_transfer_req = '0'
--and descriptor_transfer_aborted = '0'
then transmission_cycles_count := transmission_cycles_count + 1;
next_state := incrementing_transmission_cycles_for_descriptor_transfer;
elsif buffer_fill_level_in_bytes > 0
and nic_proc_latency_cycles_counter_out = 0
and arb_latency_cycles_counter_out = 0
and acq_latency_cycles_counter_out = 0
and target_latency_cycles_counter_out = 0
--and burst_cycles_counter_out = 0 -- End of DMA transfer cycles
and dma_cycles_counter_out = 0 -- Transfer is not aborted
--and descriptor_transfer_aborted = '0' -- Not aborted
then nic_overhead_cycles_count := nic_overhead_cycles_count + 1;
nic_latency_cycles_count_per_packet :=
(nic_overhead_cycles_count + nic_processing_latency_cycles_count) -
processing_cycle_of_the_last_processed_packet_by_nic;
return_to_this_state := incrementing_nic_latency_cycles;
assert false
report "statsgen_fsm: incrementing_nic_overhead_cycles"
severity note;
next_state := incrementing_nic_overhead_cycles;
elsif buffer_fill_level_in_bytes > 0
and nic_proc_latency_cycles_counter_out = 0
and arb_latency_cycles_counter_out = 0
and acq_latency_cycles_counter_out = 0
and target_latency_cycles_counter_out = 0
and burst_cycles_counter_out = 0 -- End of DMA transfer cycles
and dma_cycles_counter_out > 0 -- Transfer aborted !
--and descriptor_transfer_aborted = '0' -- Not aborted
then nic_overhead_cycles_count := nic_overhead_cycles_count + 1;
nic_latency_cycles_count_per_packet :=
(nic_overhead_cycles_count + nic_processing_latency_cycles_count) -
processing_cycle_of_the_last_processed_packet_by_nic;
return_to_this_state := incrementing_arbitration_latency_cycles_for_descriptor_transfer;
assert false
report "statsgen_fsm: incrementing_nic_overhead_cycles"
severity note;
next_state := incrementing_nic_overhead_cycles;
elsif buffer_fill_level_in_bytes > 0
and nic_proc_latency_cycles_counter_out = 0
and arb_latency_cycles_counter_out > 0
and acq_latency_cycles_counter_out = 0
and target_latency_cycles_counter_out = 0
and burst_cycles_counter_out = 0 -- End of DMA transfer cycles
and dma_cycles_counter_out > 0 -- Transfer aborted !
--and descriptor_transfer_aborted = '0' -- Not aborted
then assert false
report "statsgen_fsm: incrementing_nic_overhead_cycles"
severity note;
next_state := incrementing_nic_latency_cycles;
elsif buffer_fill_level_in_bytes > 0
and nic_proc_latency_cycles_counter_out > 0 -- Go directly to nic processing, no overhead cycles happen
and arb_latency_cycles_counter_out = 0
and acq_latency_cycles_counter_out = 0
and target_latency_cycles_counter_out = 0
and dma_cycles_counter_out = 0
then assert false
report "statsgen_fsm: incrementing_nic_latency_cycles"
severity note;
next_state := incrementing_nic_latency_cycles;
elsif buffer_fill_level_in_bytes = 0 -- Buffer empty !!
and nic_proc_latency_cycles_counter_out = 0
and arb_latency_cycles_counter_out = 0
and acq_latency_cycles_counter_out = 0
and target_latency_cycles_counter_out = 0
--and burst_cycles_counter_out = 0 -- End of DMA transfer cycles
and dma_cycles_counter_out = 0 -- Transfer is not aborted
--and descriptor_transfer_aborted = '0' -- Not aborted
then nic_overhead_cycles_count := nic_overhead_cycles_count + 1;
nic_latency_cycles_count_per_packet :=
(nic_overhead_cycles_count + nic_processing_latency_cycles_count) -
processing_cycle_of_the_last_processed_packet_by_nic;
return_to_this_state := idle;
assert false
report "statsgen_fsm: idle"
severity note;
next_state := idle;
elsif buffer_fill_level_in_bytes = 0 -- Buffer empty !!
and nic_proc_latency_cycles_counter_out > 0 -- Go directly to nic processing, no overhead cycles happen
and arb_latency_cycles_counter_out = 0
and acq_latency_cycles_counter_out = 0
and target_latency_cycles_counter_out = 0
--and burst_cycles_counter_out = 0 -- End of DMA transfer cycles
and dma_cycles_counter_out = 0 -- Transfer is not aborted
--and descriptor_transfer_aborted = '0' -- Not aborted
then assert false
report "statsgen_fsm: idle"
severity note;
next_state := incrementing_nic_latency_cycles;
end if;
when incrementing_arbitration_latency_cycles_for_aborted_payload_transfer =>
---------------------------------
-- Go to overhead state
---------------------------------
if buffer_fill_level_in_bytes > 0
and nic_proc_latency_cycles_counter_out = 0
and arb_latency_cycles_counter_out > 0
and acq_latency_cycles_counter_out = 0
and target_latency_cycles_counter_out = 0
and burst_cycles_counter_out = 0
and dma_cycles_counter_out > 0 -- Because of it is an aborted transfer, dma cycles counter is greater than 0
then arbitration_latency_cycles_count := arbitration_latency_cycles_count + 1;
arbitration_latency_cycles_count_per_packet :=
arbitration_latency_cycles_count - processing_cycle_of_the_last_processed_packet_by_arb;
next_state := incrementing_arbitration_latency_cycles_for_aborted_payload_transfer;
elsif buffer_fill_level_in_bytes > 0
and nic_proc_latency_cycles_counter_out = 0
and arb_latency_cycles_counter_out = 0
and acq_latency_cycles_counter_out = 0
and target_latency_cycles_counter_out = 0
and burst_cycles_counter_out = 0
and dma_cycles_counter_out > 0 -- Because of it is an aborted transfer, dma cycles counter is greater than 0
then nic_overhead_cycles_count := nic_overhead_cycles_count + 1;
nic_latency_cycles_count_per_packet :=
(nic_overhead_cycles_count + nic_processing_latency_cycles_count) -
processing_cycle_of_the_last_processed_packet_by_nic;
return_to_this_state := incrementing_acquisition_latency_cycles_for_aborted_payload_transfer;
assert false
report "statsgen_fsm: incrementing_nic_overhead_cycles"
severity note;
next_state := incrementing_nic_overhead_cycles;
---------------------------------------------------
-- Go to directly to the next state, no overhead
---------------------------------------------------
elsif buffer_fill_level_in_bytes > 0
and nic_proc_latency_cycles_counter_out = 0
and arb_latency_cycles_counter_out = 0
and acq_latency_cycles_counter_out > 0 --Go directly to incrementing acquisition latency cycles, no overhead happen
and target_latency_cycles_counter_out = 0
and burst_cycles_counter_out = 0
and dma_cycles_counter_out > 0 -- Because of it is an aborted transfer, dma cycles counter is greater than 0
then acquisition_latency_cycles_count := acquisition_latency_cycles_count + 1;
acquisition_latency_cycles_count_per_packet :=
acquisition_latency_cycles_count - processing_cycle_of_the_last_processed_packet_by_acq;
assert false
report "statsgen_fsm: incrementing_acquisition_latency_cycles_for_aborted_payload_transfer"
severity note;
next_state := incrementing_acquisition_latency_cycles_for_aborted_payload_transfer;
end if;
when incrementing_acquisition_latency_cycles_for_aborted_payload_transfer =>
---------------------------------
-- Go to overhead state
---------------------------------
if buffer_fill_level_in_bytes > 0
and nic_proc_latency_cycles_counter_out = 0
and arb_latency_cycles_counter_out = 0
and acq_latency_cycles_counter_out > 0
and target_latency_cycles_counter_out = 0
and burst_cycles_counter_out = 0
and dma_cycles_counter_out > 0 -- Because of it is an aborted transfer, dma cycles counter is greater than 0
then acquisition_latency_cycles_count := acquisition_latency_cycles_count + 1;
acquisition_latency_cycles_count_per_packet :=
acquisition_latency_cycles_count - processing_cycle_of_the_last_processed_packet_by_acq;
next_state := incrementing_acquisition_latency_cycles_for_aborted_payload_transfer;
elsif buffer_fill_level_in_bytes > 0
and nic_proc_latency_cycles_counter_out = 0
and arb_latency_cycles_counter_out = 0
and acq_latency_cycles_counter_out = 0
and target_latency_cycles_counter_out = 0
and burst_cycles_counter_out = 0
and dma_cycles_counter_out > 0 -- Because of it is an aborted transfer, dma cycles counter is greater than 0
then nic_overhead_cycles_count := nic_overhead_cycles_count + 1;
nic_latency_cycles_count_per_packet :=
(nic_overhead_cycles_count + nic_processing_latency_cycles_count) -
processing_cycle_of_the_last_processed_packet_by_nic;
return_to_this_state := incrementing_target_latency_cycles_for_aborted_payload_transfer;
assert false
report "statsgen_fsm: incrementing_nic_overhead_cycles"
severity note;
next_state := incrementing_nic_overhead_cycles;
---------------------------------
-- Go to directly to the next state, no overhead
---------------------------------
elsif buffer_fill_level_in_bytes > 0
and nic_proc_latency_cycles_counter_out = 0
and arb_latency_cycles_counter_out = 0
and acq_latency_cycles_counter_out = 0
and target_latency_cycles_counter_out > 0 --Go directly to incrementing target latency cycles, no overhead happen
and burst_cycles_counter_out = 0
and dma_cycles_counter_out > 0 -- Because of it is an aborted transfer, dma cycles counter is greater than 0
then target_latency_cycles_count := target_latency_cycles_count + 1;
target_latency_cycles_count_per_packet :=
target_latency_cycles_count - processing_cycle_of_the_last_processed_packet_by_memsub;
assert false
report "statsgen_fsm: incrementing_target_latency_cycles_for_aborted_payload_transfer"
severity note;
next_state := incrementing_target_latency_cycles_for_aborted_payload_transfer;
end if;
when incrementing_target_latency_cycles_for_aborted_payload_transfer =>
if buffer_fill_level_in_bytes > 0
and nic_proc_latency_cycles_counter_out = 0
and arb_latency_cycles_counter_out = 0
and acq_latency_cycles_counter_out = 0
and target_latency_cycles_counter_out > 0
and burst_cycles_counter_out = 0
and dma_cycles_counter_out > 0 -- Because of it is an aborted transfer, dma cycles counter is greater than 0
then target_latency_cycles_count := target_latency_cycles_count + 1;
target_latency_cycles_count_per_packet :=
target_latency_cycles_count - processing_cycle_of_the_last_processed_packet_by_memsub;
next_state := incrementing_target_latency_cycles_for_aborted_payload_transfer;
elsif buffer_fill_level_in_bytes > 0
and nic_proc_latency_cycles_counter_out = 0
and arb_latency_cycles_counter_out = 0
and acq_latency_cycles_counter_out = 0
and target_latency_cycles_counter_out = 0
and burst_cycles_counter_out = 0
and dma_cycles_counter_out > 0 -- Because of it is an aborted transfer, dma cycles counter is greater than 0
then nic_overhead_cycles_count := nic_overhead_cycles_count + 1;
nic_latency_cycles_count_per_packet :=
(nic_overhead_cycles_count + nic_processing_latency_cycles_count) -
processing_cycle_of_the_last_processed_packet_by_nic;
return_to_this_state := incrementing_transmission_cycles_for_resuming_aborted_payload_transfer;
assert false
report "statsgen_fsm: incrementing_nic_overhead_cycles"
severity note;
next_state := incrementing_nic_overhead_cycles;
elsif buffer_fill_level_in_bytes > 0
and nic_proc_latency_cycles_counter_out = 0
and arb_latency_cycles_counter_out = 0
and acq_latency_cycles_counter_out = 0
and target_latency_cycles_counter_out = 0
and burst_cycles_counter_out > 0 -- Go directly to incrementing transmission cycles, no overhead happen
and dma_cycles_counter_out > 0 -- Because of it is an aborted transfer, dma cycles counter is greater than 0
--and resume_aborted_payload_transfer = '0'
then transmission_cycles_count := transmission_cycles_count + 1;
assert false
report "statsgen_fsm: incrementing_transmission_cycles_for_resuming_aborted_payload_transfer"
severity note;
next_state := incrementing_transmission_cycles_for_resuming_aborted_payload_transfer;
end if;
when incrementing_transmission_cycles_for_resuming_aborted_payload_transfer =>
if buffer_fill_level_in_bytes > 0
and nic_proc_latency_cycles_counter_out = 0
and arb_latency_cycles_counter_out = 0
and acq_latency_cycles_counter_out = 0
and target_latency_cycles_counter_out = 0
and burst_cycles_counter_out > 0
and dma_cycles_counter_out > 0 -- Because of it is an aborted transfer, dma cycles counter is greater than 0
then transmission_cycles_count := transmission_cycles_count + 1;
next_state := incrementing_transmission_cycles_for_resuming_aborted_payload_transfer;
elsif buffer_fill_level_in_bytes > 0
and nic_proc_latency_cycles_counter_out = 0
and arb_latency_cycles_counter_out = 0
and acq_latency_cycles_counter_out = 0
and target_latency_cycles_counter_out = 0
and burst_cycles_counter_out = 0
and dma_cycles_counter_out > 0 -- Again, payload fragmentation
then nic_overhead_cycles_count := nic_overhead_cycles_count + 1;
nic_latency_cycles_count_per_packet :=
(nic_overhead_cycles_count + nic_processing_latency_cycles_count) -
processing_cycle_of_the_last_processed_packet_by_nic;
return_to_this_state := incrementing_arbitration_latency_cycles_for_aborted_payload_transfer;
assert false
report "statsgen_fsm: incrementing_nic_overhead_cycles"
severity note;
next_state := incrementing_nic_overhead_cycles;
elsif buffer_fill_level_in_bytes > 0
and nic_proc_latency_cycles_counter_out = 0
and arb_latency_cycles_counter_out = 0
and acq_latency_cycles_counter_out = 0
and target_latency_cycles_counter_out = 0
--and burst_cycles_counter_out = 0
and dma_cycles_counter_out = 0 -- Aborted transfer completed
then nic_overhead_cycles_count := nic_overhead_cycles_count + 1;
nic_latency_cycles_count_per_packet :=
(nic_overhead_cycles_count + nic_processing_latency_cycles_count) -
processing_cycle_of_the_last_processed_packet_by_nic;
return_to_this_state := incrementing_arbitration_latency_cycles_for_descriptor_transfer;
assert false
report "statsgen_fsm: incrementing_nic_overhead_cycles"
severity note;
next_state := incrementing_nic_overhead_cycles;
-- Quizas nunca ocurra esta transaccion, ir directo al otro estado sin pasar por ciclos de overhead
-- elsif buffer_fill_level_in_bytes > 0
-- and nic_proc_latency_cycles_counter_out = 0
-- and arb_latency_cycles_counter_out > 0
-- and acq_latency_cycles_counter_out = 0
-- and target_latency_cycles_counter_out = 0
-- and burst_cycles_counter_out = 0
-- and resume_aborted_payload_transfer = '0'
-- then arbitration_latency_cycles_count := arbitration_latency_cycles_count + 1;
-- arbitration_latency_cycles_count_per_packet :=
-- arbitration_latency_cycles_count - processing_cycle_of_the_last_processed_packet_by_arb;
-- assert false
-- report "statsgen_fsm: incrementing_arbitration_latency_cycles_for_descriptor_transfer"
-- severity note;
-- next_state := incrementing_arbitration_latency_cycles_for_descriptor_transfer;
-- Quizas nunca ocurra esta transaccion, ir directo al otro estado sin pasar por ciclos de overhead
-- elsif buffer_fill_level_in_bytes > 0
-- and nic_proc_latency_cycles_counter_out = 0
-- and arb_latency_cycles_counter_out > 0
-- and acq_latency_cycles_counter_out = 0
-- and target_latency_cycles_counter_out = 0
-- and burst_cycles_counter_out = 0
-- and resume_aborted_payload_transfer = '1'
-- then arbitration_latency_cycles_count := arbitration_latency_cycles_count + 1;
-- arbitration_latency_cycles_count_per_packet :=
-- arbitration_latency_cycles_count - processing_cycle_of_the_last_processed_packet_by_arb;
-- assert false
-- report "statsgen_fsm: incrementing_arbitration_latency_cycles_for_aborted_payload_transfer"
-- severity note;
-- next_state := incrementing_arbitration_latency_cycles_for_aborted_payload_transfer;
end if;
when incrementing_arbitration_latency_cycles_for_aborted_descriptor_transfer =>
if buffer_fill_level_in_bytes > 0
and nic_proc_latency_cycles_counter_out = 0
and arb_latency_cycles_counter_out > 0
and acq_latency_cycles_counter_out = 0
and target_latency_cycles_counter_out = 0
and burst_cycles_counter_out > 0
--and resume_aborted_descriptor_transfer = '0'
then arbitration_latency_cycles_count := arbitration_latency_cycles_count + 1;
arbitration_latency_cycles_count_per_packet :=
arbitration_latency_cycles_count - processing_cycle_of_the_last_processed_packet_by_arb;
next_state := incrementing_arbitration_latency_cycles_for_aborted_descriptor_transfer;
elsif buffer_fill_level_in_bytes > 0
and nic_proc_latency_cycles_counter_out = 0
and arb_latency_cycles_counter_out = 0
and acq_latency_cycles_counter_out = 0
and target_latency_cycles_counter_out = 0
and burst_cycles_counter_out > 0
then nic_overhead_cycles_count := nic_overhead_cycles_count + 1;
nic_latency_cycles_count_per_packet :=
(nic_overhead_cycles_count + nic_processing_latency_cycles_count) -
processing_cycle_of_the_last_processed_packet_by_nic;
return_to_this_state := incrementing_acquisition_latency_cycles_for_aborted_descriptor_transfer;
assert false
report "statsgen_fsm: incrementing_nic_overhead_cycles"
severity note;
next_state := incrementing_nic_overhead_cycles;
elsif buffer_fill_level_in_bytes > 0
and nic_proc_latency_cycles_counter_out = 0
and arb_latency_cycles_counter_out = 0
and acq_latency_cycles_counter_out > 0
and target_latency_cycles_counter_out = 0
and burst_cycles_counter_out > 0
then acquisition_latency_cycles_count := acquisition_latency_cycles_count + 1;
acquisition_latency_cycles_count_per_packet :=
acquisition_latency_cycles_count - processing_cycle_of_the_last_processed_packet_by_acq;
assert false
report "statsgen_fsm: incrementing_acquisition_latency_cycles_for_aborted_descriptor_transfer"
severity note;
next_state := incrementing_acquisition_latency_cycles_for_aborted_descriptor_transfer;
end if;
when incrementing_acquisition_latency_cycles_for_aborted_descriptor_transfer =>
if buffer_fill_level_in_bytes > 0
and nic_proc_latency_cycles_counter_out = 0
and arb_latency_cycles_counter_out = 0
and acq_latency_cycles_counter_out > 0
and target_latency_cycles_counter_out = 0
and burst_cycles_counter_out > 0
then acquisition_latency_cycles_count := acquisition_latency_cycles_count + 1;
acquisition_latency_cycles_count_per_packet :=
acquisition_latency_cycles_count - processing_cycle_of_the_last_processed_packet_by_acq;
assert false
report "statsgen_fsm: incrementing_acquisition_latency_cycles_for_aborted_descriptor_transfer"
severity note;
next_state := incrementing_acquisition_latency_cycles_for_aborted_descriptor_transfer;
elsif buffer_fill_level_in_bytes > 0
and nic_proc_latency_cycles_counter_out = 0
and arb_latency_cycles_counter_out = 0
and acq_latency_cycles_counter_out = 0
and target_latency_cycles_counter_out = 0
and burst_cycles_counter_out > 0
then nic_overhead_cycles_count := nic_overhead_cycles_count + 1;
nic_latency_cycles_count_per_packet :=
(nic_overhead_cycles_count + nic_processing_latency_cycles_count) -
processing_cycle_of_the_last_processed_packet_by_nic;
return_to_this_state := incrementing_target_latency_cycles_for_aborted_descriptor_transfer;
assert false
report "statsgen_fsm: incrementing_nic_overhead_cycles"
severity note;
next_state := incrementing_nic_overhead_cycles;
elsif buffer_fill_level_in_bytes > 0
and nic_proc_latency_cycles_counter_out = 0
and arb_latency_cycles_counter_out = 0
and acq_latency_cycles_counter_out = 0
and target_latency_cycles_counter_out > 0
and burst_cycles_counter_out > 0
then target_latency_cycles_count := target_latency_cycles_count + 1;
target_latency_cycles_count_per_packet :=
target_latency_cycles_count - processing_cycle_of_the_last_processed_packet_by_memsub;
assert false
report "statsgen_fsm: incrementing_target_latency_cycles_for_aborted_descriptor_transfer"
severity note;
next_state := incrementing_target_latency_cycles_for_aborted_descriptor_transfer;
end if;
when incrementing_target_latency_cycles_for_aborted_descriptor_transfer =>
if buffer_fill_level_in_bytes > 0
and nic_proc_latency_cycles_counter_out = 0
and arb_latency_cycles_counter_out = 0
and acq_latency_cycles_counter_out = 0
and target_latency_cycles_counter_out > 0
and burst_cycles_counter_out > 0
then target_latency_cycles_count := target_latency_cycles_count + 1;
target_latency_cycles_count_per_packet :=
target_latency_cycles_count - processing_cycle_of_the_last_processed_packet_by_memsub;
next_state := incrementing_target_latency_cycles_for_aborted_descriptor_transfer;
elsif buffer_fill_level_in_bytes > 0
and nic_proc_latency_cycles_counter_out = 0
and arb_latency_cycles_counter_out = 0
and acq_latency_cycles_counter_out = 0
and target_latency_cycles_counter_out = 0
and burst_cycles_counter_out > 0
then nic_overhead_cycles_count := nic_overhead_cycles_count + 1;
nic_latency_cycles_count_per_packet :=
(nic_overhead_cycles_count + nic_processing_latency_cycles_count) -
processing_cycle_of_the_last_processed_packet_by_nic;
return_to_this_state := incrementing_transmission_cycles_for_resuming_aborted_descriptor_transfer;
assert false
report "statsgen_fsm: incrementing_nic_overhead_cycles"
severity note;
next_state := incrementing_nic_overhead_cycles;
elsif buffer_fill_level_in_bytes > 0
and nic_proc_latency_cycles_counter_out = 0
and arb_latency_cycles_counter_out = 0
and acq_latency_cycles_counter_out = 0
and target_latency_cycles_counter_out = 0
and burst_cycles_counter_out > 0
--and resume_aborted_descriptor_transfer = '0'
then transmission_cycles_count := transmission_cycles_count + 1;
assert false
report "statsgen_fsm: incrementing_transmission_cycles_for_resuming_aborted_descriptor_transfer"
severity note;
next_state := incrementing_transmission_cycles_for_resuming_aborted_descriptor_transfer;
end if;
when incrementing_transmission_cycles_for_resuming_aborted_descriptor_transfer =>
if buffer_fill_level_in_bytes > 0
and nic_proc_latency_cycles_counter_out = 0
and arb_latency_cycles_counter_out = 0
and acq_latency_cycles_counter_out = 0
and target_latency_cycles_counter_out = 0
and burst_cycles_counter_out > 0
--and resume_aborted_descriptor_transfer = '0'
then transmission_cycles_count := transmission_cycles_count + 1;
next_state := incrementing_transmission_cycles_for_resuming_aborted_descriptor_transfer;
elsif buffer_fill_level_in_bytes > 0
and nic_proc_latency_cycles_counter_out = 0
and arb_latency_cycles_counter_out = 0
and acq_latency_cycles_counter_out = 0
and target_latency_cycles_counter_out = 0
and burst_cycles_counter_out = 0 -- Aborted descriptor transfer completed
then nic_overhead_cycles_count := nic_overhead_cycles_count + 1;
nic_latency_cycles_count_per_packet :=
(nic_overhead_cycles_count + nic_processing_latency_cycles_count) -
processing_cycle_of_the_last_processed_packet_by_nic;
return_to_this_state := incrementing_transmission_cycles_for_resuming_aborted_descriptor_transfer;
assert false
report "statsgen_fsm: incrementing_nic_overhead_cycles"
severity note;
next_state := incrementing_nic_overhead_cycles;
elsif buffer_fill_level_in_bytes = 0
then next_state := idle;
end if;
end case;
state := next_state;
end process statsgen_fsm;
transaction_in_progress_monitor: process
type statsgen_transaction_in_progress_monitor_fsm is (idle,
transaction_in_progress,
ending_transaction);
--updating_latency_per_packet);
variable state : statsgen_transaction_in_progress_monitor_fsm := idle; --Initial state
variable next_state : statsgen_transaction_in_progress_monitor_fsm := idle;
begin
wait until pciclk'event and pciclk = '0';
case state is
when idle =>
processing_cycle_of_the_last_processed_packet_by_nic := nic_overhead_cycles_count + nic_processing_latency_cycles_count;
processing_cycle_of_the_last_processed_packet_by_arb := arbitration_latency_cycles_count;
processing_cycle_of_the_last_processed_packet_by_acq := acquisition_latency_cycles_count;
processing_cycle_of_the_last_processed_packet_by_memsub := target_latency_cycles_count;
arbitration_latency_cycles_count_per_packet := 0;
acquisition_latency_cycles_count_per_packet := 0;
target_latency_cycles_count_per_packet := 0;
if transfer_start_req = '1'
and transfer_end = '0'
then next_state := idle;
elsif transfer_start_req = '0' --Start of transaction
and transfer_end = '0'
then assert false
report "statsgen_transaction_in_progress_monitor_fsm: transaction_in_progress"
severity note;
next_state := transaction_in_progress;
end if;
when transaction_in_progress =>
if transfer_start_req = '0' --Transaction in progress
and transfer_end = '0'
then next_state := transaction_in_progress;
elsif transfer_end = '1' --Transaction termination start
then transferred_packets_count := transferred_packets_count + 1;
assert false
report "statsgen_transaction_in_progress_monitor_fsm: ending_transaction"
severity note;
next_state := ending_transaction;
end if;
when ending_transaction =>
if transfer_end = '1' --Transaction termination in progress
then next_state := ending_transaction;
elsif transfer_end = '0' --End of transaction (transaction termination process completed)
then assert false
report "statsgen_transaction_in_progress_monitor_fsm: updating_latency_per_packet"
severity note;
next_state := idle;
end if;
-- when updating_latency_per_packet =>
-- processing_cycle_of_the_last_processed_packet_by_nic := nic_overhead_cycles_count + nic_processing_latency_cycles_count;
-- assert false
-- report "statsgen_transaction_in_progress_monitor_fsm: idle"
-- severity note;
-- next_state := idle;
end case;
state := next_state;
end process transaction_in_progress_monitor;
maximum_latency_monitor: process
begin
wait until pciclk'event and pciclk = '0';
if nic_latency_cycles_count_per_packet > max_nic_latency_cycles_count_per_packet
then max_nic_latency_cycles_count_per_packet := nic_latency_cycles_count_per_packet;
end if;
if arbitration_latency_cycles_count_per_packet > max_arbitration_latency_cycles_count_per_packet
then max_arbitration_latency_cycles_count_per_packet := arbitration_latency_cycles_count_per_packet;
end if;
if acquisition_latency_cycles_count_per_packet > max_acquisition_latency_cycles_count_per_packet
then max_acquisition_latency_cycles_count_per_packet := acquisition_latency_cycles_count_per_packet;
end if;
if target_latency_cycles_count_per_packet > max_target_latency_cycles_count_per_packet
then max_target_latency_cycles_count_per_packet := target_latency_cycles_count_per_packet;
end if;
end process maximum_latency_monitor;
max_buffer_fill_level_monitor: process
begin
wait until ethclk'event and ethclk = '1';
if buff_fill_level > max_buff_fill_level
then max_buff_fill_level := buff_fill_level;
end if;
end process max_buffer_fill_level_monitor;
max_data_unit_size_monitor: process
type max_data_unit_size_monitor_fsm is (idle,
comparing);
variable state : max_data_unit_size_monitor_fsm := idle; --Initial state
variable next_state : max_data_unit_size_monitor_fsm := idle;
begin
wait until ethclk'event and ethclk = '1';
case state is
when idle =>
if pktreceived = '0'
then next_state := idle;
elsif pktreceived = '1'
then size_of_received_data_unit_in_bytes := pktsize - (preamble_in_bytes + sof_in_bytes) + descriptor_size_in_bytes;
next_state := comparing;
end if;
when comparing =>
if size_of_received_data_unit_in_bytes > max_received_data_unit_size_in_bytes
then max_received_data_unit_size_in_bytes := size_of_received_data_unit_in_bytes;
end if;
size_of_received_data_unit_in_bytes := 0;
next_state := idle;
end case;
state := next_state;
end process max_data_unit_size_monitor;
inc_clock_counter: process
begin
wait until pciclk'event and pciclk = '1';
clock_counter_value := clock_counter_value + 1;
end process inc_clock_counter;
clock_counter_manager: process
begin
wait until pciclk'event and pciclk = '0';
sig_clock_counter_value <= clock_counter_value;
end process clock_counter_manager;
input_rate_computation_in_data_units_per_pci_cycles: process
type data_units_received_monitor_fsm is (idle,
fresh_packet_received,
waiting_packet_received_falling_edge,
waiting_for_a_fresh_packet);
variable state : data_units_received_monitor_fsm := idle; --Initial state
variable next_state : data_units_received_monitor_fsm := idle;
begin
wait until pciclk'event and pciclk = '1';
case state is
when idle =>
if pktreceived = '0'
then next_state := idle;
elsif pktreceived = '1'
then received_packets_counter := received_packets_counter + 1;
nic_overhead_cycles_count := nic_overhead_cycles_count + 1;
assert false
report "data_units_received_monitor_fsm: fresh_packet_received"
severity note;
next_state := fresh_packet_received;
end if;
when fresh_packet_received =>
--received_packets_counter := received_packets_counter + 1;
nic_overhead_cycles_count := nic_overhead_cycles_count + 1;
data_units_received_count :=
data_units_received_count + integer(ceil(real(pktsize - (preamble_in_bytes + sof_in_bytes))/real(bus_width_in_bytes)))
+ descriptor_size_in_data_blocks;
data_unit_size := integer(ceil(real(pktsize - (preamble_in_bytes + sof_in_bytes))/real(bus_width_in_bytes)))
+ descriptor_size_in_data_blocks;
--descriptor_size := descriptor_size_in_data_blocks;
clock_counter_for_computing_data_units_received_rate := clock_counter_for_computing_data_units_received_rate + 1;
data_units_received_rate :=
real(data_units_received_count)/real(clock_counter_for_computing_data_units_received_rate);
assert false
report "data_units_received_monitor_fsm: waiting_packet_received_falling_edge"
severity note;
next_state := waiting_packet_received_falling_edge;
when waiting_packet_received_falling_edge =>
if pktreceived = '1'
then clock_counter_for_computing_data_units_received_rate := clock_counter_for_computing_data_units_received_rate + 1;
data_units_received_rate :=
real(data_units_received_count)/real(clock_counter_for_computing_data_units_received_rate);
nic_overhead_cycles_count := nic_overhead_cycles_count + 1;
next_state := waiting_packet_received_falling_edge;
elsif pktreceived = '0'
then clock_counter_for_computing_data_units_received_rate := clock_counter_for_computing_data_units_received_rate + 1;
data_units_received_rate :=
real(data_units_received_count)/real(clock_counter_for_computing_data_units_received_rate);
--nic_overhead_cycles_count := nic_overhead_cycles_count + 1;
assert false
report "data_units_received_monitor_fsm: waiting_for_a_fresh_packet"
severity note;
next_state := waiting_for_a_fresh_packet;
end if;
when waiting_for_a_fresh_packet =>
if pktreceived = '0'
then clock_counter_for_computing_data_units_received_rate := clock_counter_for_computing_data_units_received_rate + 1;
data_units_received_rate :=
real(data_units_received_count)/real(clock_counter_for_computing_data_units_received_rate);
--nic_overhead_cycles_count := nic_overhead_cycles_count + 1;
next_state := waiting_for_a_fresh_packet;
elsif pktreceived = '1'
then received_packets_counter := received_packets_counter + 1;
clock_counter_for_computing_data_units_received_rate := clock_counter_for_computing_data_units_received_rate + 1;
data_units_received_rate :=
real(data_units_received_count)/real(clock_counter_for_computing_data_units_received_rate);
nic_overhead_cycles_count := nic_overhead_cycles_count + 1;
assert false
report "data_units_received_monitor_fsm: fresh_packet_received"
severity note;
next_state := fresh_packet_received;
end if;
end case;
state := next_state;
end process input_rate_computation_in_data_units_per_pci_cycles;
-- input_rate_computation_in_packets_per_second: process
-- type data_units_received_monitor_fsm is (idle,
-- fresh_packet_received,
-- waiting_packet_received_falling_edge,
-- waiting_for_a_fresh_packet);
-- variable state : data_units_received_monitor_fsm := idle; --Initial state
-- variable next_state : data_units_received_monitor_fsm := idle;
-- begin
-- wait until ethclk'event and ethclk = '1';
-- case state is
-- when idle =>
-- if pktreceived = '0'
-- then next_state := idle;
-- elsif pktreceived = '1'
-- then next_state := fresh_packet_received;
-- end if;
-- when fresh_packet_received =>
-- packets_received_counter := packets_received_counter + 1;
-- eth_clock_counter := eth_clock_counter + 1;
-- packets_received_rate :=
-- real(packets_received_counter)/real(clock_counter_for_computing_data_units_received_rate);
-- next_state := waiting_packet_received_falling_edge;
-- when waiting_packet_received_falling_edge =>
-- if pktreceived = '1'
-- then clock_counter_for_computing_data_units_received_rate := clock_counter_for_computing_data_units_received_rate + 1;
-- data_units_received_rate :=
-- real(data_units_received_count)/real(clock_counter_for_computing_data_units_received_rate);
-- next_state := waiting_packet_received_falling_edge;
-- elsif pktreceived = '0'
-- then clock_counter_for_computing_data_units_received_rate := clock_counter_for_computing_data_units_received_rate + 1;
-- data_units_received_rate :=
-- real(data_units_received_count)/real(clock_counter_for_computing_data_units_received_rate);
-- next_state := waiting_for_a_fresh_packet;
-- end if;
-- when waiting_for_a_fresh_packet =>
-- if pktreceived = '0'
-- then clock_counter_for_computing_data_units_received_rate := clock_counter_for_computing_data_units_received_rate + 1;
-- data_units_received_rate :=
-- real(data_units_received_count)/real(clock_counter_for_computing_data_units_received_rate);
-- next_state := waiting_for_a_fresh_packet;
-- elsif pktreceived = '1'
-- then clock_counter_for_computing_data_units_received_rate := clock_counter_for_computing_data_units_received_rate + 1;
-- data_units_received_rate :=
-- real(data_units_received_count)/real(clock_counter_for_computing_data_units_received_rate);
-- next_state := fresh_packet_received;
-- end if;
-- end case;
-- state := next_state;
-- end process input_rate_computation_in_packets_per_second;
current_packet_being_transferred_monitor: process
type packet_being_transferred_fsm_state is (waiting_transfer_start,
waiting_packet_reception,
transferring,
ending);
variable state : packet_being_transferred_fsm_state := waiting_packet_reception; --Initial state
variable next_state : packet_being_transferred_fsm_state := waiting_packet_reception;
begin
wait until pciclk'event and pciclk = '1';
case state is
when waiting_packet_reception =>
if pktreceived = '0'
then --number_of_packet_being_transferred := 0;
next_state := waiting_packet_reception;
elsif pktreceived = '1'
then number_of_packet_being_transferred := number_of_last_transferred_packet;
number_of_packet_being_transferred := number_of_packet_being_transferred + 1;
assert false
report "current_packet_being_transferred_monitor_fsm: waiting_transfer_start"
severity note;
next_state := waiting_transfer_start;
end if;
when waiting_transfer_start =>
if transfer_start_req = '1' and transfer_end = '0'
then --assert false
--report "current_packet_being_transferred_monitor_fsm: waiting_transfer_start"
--severity note;
next_state := waiting_transfer_start;
elsif transfer_start_req = '0' and transfer_end = '0'
then --number_of_packet_being_transferred := number_of_last_transferred_packet;
--number_of_packet_being_transferred := number_of_packet_being_transferred + 1;
assert false
report "current_packet_being_transferred_monitor_fsm: transferring"
severity note;
next_state := transferring;
end if;
when transferring =>
if transfer_start_req = '0' and transfer_end = '1'
then number_of_last_transferred_packet := number_of_packet_being_transferred;
number_of_packet_being_transferred := 0;
assert false
report "current_packet_being_transferred_monitor_fsm: ending"
severity note;
next_state := ending;
elsif transfer_start_req = '0' and transfer_end = '0'
then --assert false
--report "current_packet_being_transferred_monitor_fsm: transferring"
--severity note;
next_state := transferring;
end if;
when ending =>
if transfer_end = '1'
then next_state := ending;
elsif transfer_end = '0'
then --number_of_packet_being_transferred := 0;
--next_state := waiting_transfer_start;
assert false
report "current_packet_being_transferred_monitor_fsm: waiting_packet_reception"
severity note;
next_state := waiting_packet_reception;
end if;
end case;
state := next_state;
end process current_packet_being_transferred_monitor;
-------------------------------------------------------------------------------------------------------------
---------- Print out statistics -----------------------------------------------------------------------------
-------------------------------------------------------------------------------------------------------------
print_out_input_workload_statistics: process
file input_workload_statistics_file : text open write_mode is "input.out";
variable output_line : line;
variable clock_counter : natural := 1;
variable average : real;
begin
wait until pciclk'event and pciclk = '0';
write(output_line, string'("clock "));
write(output_line, clock_counter);
write(output_line, string'(": "));
write(output_line, string'("rcvd data units size (in data blocks) = "));
write(output_line, data_units_received_count);
write(output_line, string'(": "));
write(output_line, string'("cycles count = "));
write(output_line, clock_counter_for_computing_data_units_received_rate);
write(output_line, string'(": "));
write(output_line, string'("max. data unit size = "));
write(output_line, data_unit_size);
write(output_line, string'(": "));
write(output_line, string'("rate = "));
write(output_line, data_units_received_rate);
writeline(input_workload_statistics_file, output_line);
clock_counter := clock_counter + 1;
end process print_out_input_workload_statistics;
print_out_buffer_statistics: process
file buffer_statistics_output_file : text open write_mode is "buffer.out";
variable output_line : line;
variable clock_counter : integer := 1;
-- variable verbosity : integer := 1; **** Output verbosity management has not been implemented yet...
begin
--wait until pciclk'event and pciclk = '1';
wait until pciclk'event and pciclk = '0';
write(output_line, string'("clock "));
write(output_line, clock_counter);
write(output_line, string'(": "));
-- write(output_line, string'("FIFO size = "));
-- write(output_line, buffer_size);
-- write(output_line, string'(": "));
-- write(output_line, string'("occupancy = "));
-- write(output_line, occupancy);
-- write(output_line, string'("("));
-- write(output_line, real(occupancy)/real(buffer_size));
-- write(output_line, string'(" %) "));
-- write(output_line, string'(": "));
-- write(output_line, string'("fill level = "));
-- write(output_line, buff_fill_level);
-- write(output_line, string'(": "));
-- write(output_line, string'(": "));
write(output_line, string'("fill level (in bytes) = "));
write(output_line, buffer_fill_level_in_bytes);
write(output_line, string'(": "));
write(output_line, string'("max fill level = "));
write(output_line, max_buffer_fill_level);
write(output_line, string'(": "));
write(output_line, string'("received pkts = "));
write(output_line, received_packets_counter);
write(output_line, string'(": "));
write(output_line, string'("transferred = "));
write(output_line, transferred_packets_count);
write(output_line, string'(": "));
write(output_line, string'("dropped = "));
write(output_line, dropped_packets_count);
writeline(buffer_statistics_output_file, output_line);
clock_counter := clock_counter + 1;
end process print_out_buffer_statistics;
print_out_nic_statistics: process
file nic_output_file : text open write_mode is "nic.out";
variable output_line : line;
variable clock_counter : natural := 1;
begin
wait until pciclk'event and pciclk = '0';
write(output_line, string'("clock "));
write(output_line, clock_counter);
write(output_line, string'(": "));
write(output_line, string'("rcvd packets = "));
write(output_line, received_packets_counter);
write(output_line, string'(": "));
-- write(output_line, string'("transferring # "));
-- write(output_line, number_of_packet_being_transferred);
-- write(output_line, string'(": "));
--write(output_line, string'("lat. cycles = "));
--write(output_line, nic_processing_latency_cycles_count);
--write(output_line, string'(": "));
--write(output_line, string'("ovrh. cycles = "));
--write(output_line, nic_overhead_cycles_count);
-- write(output_line, string'(": "));
-- write(output_line, string'("lat. per pkt = "));
-- write(output_line, nic_latency_cycles_count_per_packet);
-- write(output_line, string'(": "));
-- write(output_line, string'("last processed pkt = "));
-- write(output_line, processing_cycle_of_the_last_processed_packet_by_nic);
-- write(output_line, string'(": "));
write(output_line, string'("non trans. cycles = "));
write(output_line, nic_overhead_cycles_count + nic_processing_latency_cycles_count);
write(output_line, string'(": "));
write(output_line, string'("trans. cycles = "));
write(output_line, transmission_cycles_count);
write(output_line, string'(": "));
write(output_line, string'("latency = "));
write(output_line, max_nic_latency_cycles_count_per_packet);
write(output_line, string'(": "));
write(output_line, string'("rate = "));
if (nic_overhead_cycles_count + nic_processing_latency_cycles_count) > 0
then write(output_line, real(transmission_cycles_count)/real(nic_overhead_cycles_count
+ nic_processing_latency_cycles_count + transmission_cycles_count));
else write(output_line, string'("0.0e0"));
end if;
writeline(nic_output_file, output_line);
clock_counter := clock_counter + 1;
end process print_out_nic_statistics;
print_out_bus_arbitration_statistics: process
file bus_arb_output_file : text open write_mode is "arb.out";
variable output_line : line;
variable clock_counter : natural := 1;
-- variable average : real;
begin
wait until pciclk'event and pciclk = '0';
write(output_line, string'("clock "));
write(output_line, clock_counter);
write(output_line, string'(": "));
-- write(output_line, received_packets_counter);
-- write(output_line, string'(" received pkts"));
-- write(output_line, string'(": "));
-- write(output_line, string'("transferring # "));
-- write(output_line, number_of_packet_being_transferred);
-- write(output_line, string'(": "));
write(output_line, string'("non trans. cycles = "));
write(output_line, arbitration_latency_cycles_count);
write(output_line, string'(": "));
write(output_line, string'("trans. cycles = "));
write(output_line, transmission_cycles_count);
write(output_line, string'(": "));
--write(output_line, string'("lat. per pkt = "));
--write(output_line, arbitration_latency_cycles_count_per_packet);
--write(output_line, string'(": "));
--write(output_line, string'("last processed pkt = "));
--write(output_line, processing_cycle_of_the_last_processed_packet_by_arb);
--write(output_line, string'(": "));
write(output_line, string'("latency = "));
write(output_line, max_arbitration_latency_cycles_count_per_packet);
write(output_line, string'(": "));
write(output_line, string'("rate = "));
if arbitration_latency_cycles_count > 0
then write(output_line, real(transmission_cycles_count)/real(arbitration_latency_cycles_count + transmission_cycles_count));
else write(output_line, string'("0.0e0"));
end if;
writeline(bus_arb_output_file, output_line);
clock_counter := clock_counter + 1;
end process print_out_bus_arbitration_statistics;
print_out_bus_acquisition_statistics: process
file bus_acq_output_file : text open write_mode is "acq.out";
variable output_line : line;
variable clock_counter : natural := 1;
-- variable average : real;
begin
wait until pciclk'event and pciclk = '0';
write(output_line, string'("clock "));
write(output_line, clock_counter);
write(output_line, string'(": "));
-- write(output_line, received_packets_counter);
-- write(output_line, string'(" received pkts"));
-- write(output_line, string'(": "));
-- write(output_line, string'("transferring # "));
-- write(output_line, number_of_packet_being_transferred);
-- write(output_line, string'(": "));
write(output_line, string'("non trans. cycles = "));
write(output_line, acquisition_latency_cycles_count);
write(output_line, string'(": "));
write(output_line, string'("trans. cycles = "));
write(output_line, transmission_cycles_count);
-- write(output_line, string'(": "));
-- write(output_line, string'("lat. per pkt = "));
-- write(output_line, acquisition_latency_cycles_count_per_packet);
-- write(output_line, string'(": "));
-- write(output_line, string'("last processed pkt = "));
-- write(output_line, processing_cycle_of_the_last_processed_packet_by_acq);
write(output_line, string'(": "));
write(output_line, string'("latency = "));
write(output_line, max_acquisition_latency_cycles_count_per_packet);
write(output_line, string'(": "));
write(output_line, string'("rate = "));
if acquisition_latency_cycles_count > 0
then write(output_line, real(transmission_cycles_count)/real(acquisition_latency_cycles_count + transmission_cycles_count));
else write(output_line, string'("0.0e0"));
end if;
writeline(bus_acq_output_file, output_line);
clock_counter := clock_counter + 1;
end process print_out_bus_acquisition_statistics;
print_out_target_latency_statistics: process
file target_latency_output_file : text open write_mode is "memsub.out";
variable output_line : line;
variable clock_counter : natural := 1;
-- variable average : real;
begin
wait until pciclk'event and pciclk = '0';
write(output_line, string'("clock "));
write(output_line, clock_counter);
write(output_line, string'(": "));
-- write(output_line, received_packets_counter);
-- write(output_line, string'(" received pkts"));
-- write(output_line, string'(": "));
-- write(output_line, string'("transferring # "));
-- write(output_line, number_of_packet_being_transferred);
-- write(output_line, string'(": "));
write(output_line, string'("non trans. cycles = "));
write(output_line, target_latency_cycles_count);
write(output_line, string'(": "));
write(output_line, string'("trans. cycles = "));
write(output_line, transmission_cycles_count);
write(output_line, string'(": "));
-- write(output_line, string'("lat. per pkt = "));
-- write(output_line, target_latency_cycles_count_per_packet);
-- write(output_line, string'(": "));
-- write(output_line, string'("last processed pkt = "));
-- write(output_line, processing_cycle_of_the_last_processed_packet_by_memsub);
-- write(output_line, string'(": "));
write(output_line, string'("latency = "));
write(output_line, max_target_latency_cycles_count_per_packet);
write(output_line, string'(": "));
write(output_line, string'("rate = "));
if target_latency_cycles_count > 0
then write(output_line, real(transmission_cycles_count)/real(target_latency_cycles_count + transmission_cycles_count));
else write(output_line, string'("0.0e0"));
end if;
writeline(target_latency_output_file, output_line);
clock_counter := clock_counter + 1;
end process print_out_target_latency_statistics;
end V1;
| gpl-3.0 | 8cb5f8c0dcf266a974b31c7658e07a8b | 0.677305 | 3.349507 | false | false | false | false |
freecores/cryptopan_core | rtl/subbytesshiftrows.vhd | 1 | 3,591 | --
-- This file is part of the Crypto-PAn core.
--
-- Copyright (c) 2007 The University of Waikato, Hamilton, New Zealand.
-- Authors: Anthony Blake ([email protected])
--
-- All rights reserved.
--
-- This code has been developed by the University of Waikato WAND
-- research group. For further information please see http://www.wand.net.nz/
--
-- This source file is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This source is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with libtrace; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
--
library ieee;
use ieee.std_logic_1164.all;
use work.cryptopan.all;
entity subbytesshiftrows is
port (
bytes_in : in s_vector;
bytes_out : out s_vector;
in_en : in std_logic;
out_en : out std_logic;
clk : in std_logic;
reset : in std_logic
);
end subbytesshiftrows;
architecture rtl of subbytesshiftrows is
component dual_bram_256x8
port (
addra : IN std_logic_VECTOR(7 downto 0);
addrb : IN std_logic_VECTOR(7 downto 0);
clka : IN std_logic;
clkb : IN std_logic;
douta : OUT std_logic_VECTOR(7 downto 0);
doutb : OUT std_logic_VECTOR(7 downto 0));
end component;
component sbox
port (
clk : in std_logic;
reset : in std_logic;
addra : in std_logic_vector(7 downto 0);
douta : out std_logic_vector(7 downto 0));
end component;
signal subbytes_out : s_vector;
signal in_en_int : std_logic;
begin -- rtl
out_en <= in_en_int;
CLKLOGIC : process (clk, reset)
begin
if reset = '1' then
in_en_int <= '0';
elsif clk'event and clk = '1' then
in_en_int <= in_en;
end if;
end process CLKLOGIC;
USE_BRAM_GEN : if use_bram = true generate
GEN_SBOX_BRAM : for i in 0 to 7 generate
SBOX_i: dual_bram_256x8
port map (
addra => bytes_in(i),
addrb => bytes_in(i+8),
clka => clk,
clkb => clk,
douta => subbytes_out(i),
doutb => subbytes_out(i+8));
end generate GEN_SBOX_BRAM;
end generate USE_BRAM_GEN;
NO_BRAM_GEN : if use_bram = false generate
GEN_SBOX_NOBRAM : for i in 0 to 15 generate
SBOX_i : sbox
port map (
clk => clk,
reset => reset,
addra => bytes_in(i),
douta => subbytes_out(i) );
end generate GEN_SBOX_NOBRAM;
end generate NO_BRAM_GEN;
bytes_out(0) <= subbytes_out(0);
bytes_out(1) <= subbytes_out(1);
bytes_out(2) <= subbytes_out(2);
bytes_out(3) <= subbytes_out(3);
bytes_out(4) <= subbytes_out(5);
bytes_out(5) <= subbytes_out(6);
bytes_out(6) <= subbytes_out(7);
bytes_out(7) <= subbytes_out(4);
bytes_out(8) <= subbytes_out(10);
bytes_out(9) <= subbytes_out(11);
bytes_out(10) <= subbytes_out(8);
bytes_out(11) <= subbytes_out(9);
bytes_out(12) <= subbytes_out(15);
bytes_out(13) <= subbytes_out(12);
bytes_out(14) <= subbytes_out(13);
bytes_out(15) <= subbytes_out(14);
end rtl;
| gpl-2.0 | 1405f4a917c1ab6a42320f4056feeb81 | 0.617098 | 3.240975 | false | false | false | false |
EliasLuiz/TCC | Leon3/lib/gaisler/misc/apbvga.vhd | 1 | 11,979 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: apbvga
-- File: vga.vhd
-- Author: Marcus Hellqvist
-- Description: VGA controller
-----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
library techmap;
use techmap.gencomp.all;
library gaisler;
use gaisler.misc.all;
use gaisler.charrom_package.all;
entity apbvga is
generic(
memtech : integer := DEFMEMTECH;
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#fff#
);
port( rst : in std_ulogic; -- Global asynchronous reset
clk : in std_ulogic; -- Global clock
vgaclk : in std_ulogic; -- VGA clock
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
vgao : out apbvga_out_type
);
end entity apbvga;
architecture rtl of apbvga is
type state_type is (s0,s1,s2);
constant RAM_DEPTH : integer := 12;
constant RAM_DATA_BITS : integer := 8;
constant MAX_FRAME : std_logic_vector((RAM_DEPTH-1) downto 0):= X"B90";
type ram_out_type is record
dataout2 : std_logic_vector((RAM_DATA_BITS -1) downto 0);
end record;
type vga_regs is record
video_out : std_logic_vector(23 downto 0);
hsync : std_ulogic;
vsync : std_ulogic;
csync : std_ulogic;
hcnt : std_logic_vector(9 downto 0);
vcnt : std_logic_vector(9 downto 0);
blank : std_ulogic;
linecnt : std_logic_vector(3 downto 0);
h_video_on : std_ulogic;
v_video_on : std_ulogic;
pixel : std_ulogic;
state : state_type;
rombit : std_logic_vector(2 downto 0);
romaddr : std_logic_vector(11 downto 0);
ramaddr2 : std_logic_vector((RAM_DEPTH -1) downto 0);
ramdatain2 : std_logic_vector((RAM_DATA_BITS -1) downto 0);
wstartaddr : std_logic_vector((RAM_DEPTH-1) downto 0);
raddr : std_logic_vector((RAM_DEPTH-1) downto 0);
tmp : std_logic_vector(RAM_DEPTH-1 downto 0);
end record;
type color_reg_type is record
bgcolor : std_logic_vector(23 downto 0);
txtcolor : std_logic_vector(23 downto 0);
end record;
type vmmu_reg_type is record
waddr : std_logic_vector((RAM_DEPTH-1) downto 0);
wstartaddr : std_logic_vector((RAM_DEPTH-1) downto 0);
ramaddr1 : std_logic_vector((RAM_DEPTH -1) downto 0);
ramdatain1 : std_logic_vector((RAM_DATA_BITS -1) downto 0);
ramenable1 : std_ulogic;
ramwrite1 : std_ulogic;
color : color_reg_type;
end record;
constant REVISION : amba_version_type := 0;
constant pconfig : apb_config_type := (
0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_VGACTRL, 0, REVISION, 0),
1 => apb_iobar(paddr, pmask));
constant hmax : integer:= 799;
constant vmax : integer:= 524;
constant hvideo : integer:= 639;
constant vvideo : integer:= 480;
constant hfporch : integer:= 19;
constant vfporch : integer:= 11;
constant hbporch : integer:= 45;
constant vbporch : integer:= 31;
constant hsyncpulse : integer:= 96;
constant vsyncpulse : integer:= 2;
constant char_height : std_logic_vector(3 downto 0):="1100";
signal p,pin : vmmu_reg_type;
signal ramo : ram_out_type;
signal r,rin : vga_regs;
signal romdata : std_logic_vector(7 downto 0);
signal gnd, vcc : std_ulogic;
begin
gnd <= '0'; vcc <= '1';
comb1: process(rst,r,p,romdata,ramo)
variable v : vga_regs;
begin
v:=r;
v.wstartaddr := p.wstartaddr;
-- horizontal counter
if r.hcnt < conv_std_logic_vector(hmax,10) then
v.hcnt := r.hcnt +1;
else
v.hcnt := (others => '0');
end if;
-- vertical counter
if (r.vcnt >= conv_std_logic_vector(vmax,10)) and (r.hcnt >= conv_std_logic_vector(hmax,10)) then
v.vcnt := (others => '0');
elsif r.hcnt = conv_std_logic_vector(hmax,10) then
v.vcnt := r.vcnt +1;
end if;
-- horizontal pixel out
if r.hcnt <= conv_std_logic_vector(hvideo,10) then
v.h_video_on := '1';
else
v.h_video_on := '0';
end if;
-- vertical pixel out
if r.vcnt <= conv_std_logic_vector(vvideo,10) then
v.v_video_on := '1';
else
v.v_video_on := '0';
end if;
-- generate hsync
if (r.hcnt <= conv_std_logic_vector((hvideo+hfporch+hsyncpulse),10)) and
(r.hcnt >= conv_std_logic_vector((hvideo+hfporch),10)) then
v.hsync := '0';
else
v.hsync := '1';
end if;
-- generate vsync
if (r.vcnt <= conv_std_logic_vector((vvideo+vfporch+vsyncpulse),10)) and
(r.vcnt >= conv_std_logic_vector((vvideo+vfporch),10)) then
v.vsync := '0';
else
v.vsync := '1';
end if;
--generate csync & blank
v.csync := not (v.hsync xor v.vsync);
v.blank := v.h_video_on and v.v_video_on;
-- count line of character
if v.hcnt = conv_std_logic_vector(hvideo,10) then
if (r.linecnt = char_height) or (v.vcnt = conv_std_logic_vector(vmax,10)) then
v.linecnt := (others => '0');
else
v.linecnt := r.linecnt +1;
end if;
end if;
if v.blank = '1' then
case r.state is
when s0 => v.ramaddr2 := r.raddr;
v.raddr := r.raddr +1;
v.state := s1;
when s1 => v.romaddr := v.linecnt & ramo.dataout2;
v.state := s2;
when s2 => if r.rombit = "011" then
v.ramaddr2 := r.raddr;
v.raddr := r.raddr +1;
elsif r.rombit = "010" then
v.state := s1;
end if;
end case;
v.rombit := r.rombit - 1;
v.pixel := romdata(conv_integer(r.rombit));
end if;
-- read from same address char_height times
if v.raddr = (r.tmp + X"050") then
if (v.linecnt < char_height) then
v.raddr := r.tmp;
elsif v.raddr(11 downto 4) = X"FF" then --check for end of allowed memory(80x51)
v.raddr := (others => '0');
v.tmp := (others => '0');
else
v.tmp := r.tmp + X"050";
end if;
end if;
if v.v_video_on = '0' then
v.raddr := r.wstartaddr;
v.tmp := r.wstartaddr;
v.state := s0;
end if;
-- define pixel color
if v.pixel = '1'and v.blank = '1' then
v.video_out := p.color.txtcolor;
else
v.video_out := p.color.bgcolor;
end if;
if rst = '0' then
v.hcnt := conv_std_logic_Vector(hmax,10);
v.vcnt := conv_std_logic_Vector(vmax,10);
v.v_video_on := '0';
v.h_video_on := '0';
v.hsync := '0';
v.vsync := '0';
v.csync := '0';
v.blank := '0';
v.linecnt := (others => '0');
v.state := s0;
v.rombit := "111";
v.pixel := '0';
v.video_out := (others => '0');
v.raddr := (others => '0');
v.tmp := (others => '0');
v.ramaddr2 := (others => '0');
v.ramdatain2 := (others => '0');
end if;
-- update register
rin <= v;
-- drive outputs
vgao.hsync <= r.hsync;
vgao.vsync <= r.vsync;
vgao.comp_sync <= r.csync;
vgao.blank <= r.blank;
vgao.video_out_r <= r.video_out(23 downto 16);
vgao.video_out_g <= r.video_out(15 downto 8);
vgao.video_out_b <= r.video_out(7 downto 0);
vgao.bitdepth <= "11"; -- All data is valid
end process;
comb2: process(rst,r,p,apbi,ramo)
variable v : vmmu_reg_type;
variable rdata : std_logic_vector(31 downto 0);
begin
v := p;
v.ramenable1 := '0'; v.ramwrite1 := '0';
rdata := (others => '0');
case apbi.paddr(3 downto 2) is
when "00" => if (apbi.psel(pindex) and apbi.penable and apbi.pwrite) = '1' then
v.waddr := apbi.pwdata(19 downto 8);
v.ramdatain1 := apbi.pwdata(7 downto 0);
v.ramenable1 := '1';
v.ramwrite1 := '1';
v.ramaddr1 := apbi.pwdata(19 downto 8);
end if;
when "01" => if (apbi.psel(pindex) and apbi.penable and apbi.pwrite) = '1' then
v.color.bgcolor := apbi.pwdata(23 downto 0);
end if;
when "10" => if (apbi.psel(pindex) and apbi.penable and apbi.pwrite) = '1' then
v.color.txtcolor := apbi.pwdata(23 downto 0);
end if;
when others => null;
end case;
if (p.waddr - p.wstartaddr) >= MAX_FRAME then
if p.wstartaddr(11 downto 4) = X"FA" then --last position of allowed memory
v.wstartaddr := X"000";
else
v.wstartaddr := p.wstartaddr + X"050";
end if;
end if;
if rst = '0' then
v.waddr := (others => '0');
v.wstartaddr := (others => '0');
v.color.bgcolor := (others => '0');
v.color.txtcolor := (others => '1');
end if;
--update registers
pin <= v;
--drive outputs
apbo.prdata <= rdata;
apbo.pindex <= pindex;
apbo.pirq <= (others => '0');
end process;
apbo.pconfig <= pconfig;
reg : process(clk)
begin
if clk'event and clk = '1' then
p <= pin;
end if;
end process;
reg2 : process(vgaclk)
begin
if vgaclk'event and vgaclk = '1' then
r <= rin;
end if;
end process;
rom0 : charrom port map(clk=>vgaclk, addr=>r.romaddr, data=>romdata);
ram0 : syncram_2p generic map (tech => memtech, abits => RAM_DEPTH,
dbits => RAM_DATA_BITS, sepclk => 1)
port map (
rclk => vgaclk, raddress => r.ramaddr2, dataout => ramo.dataout2, renable => vcc,
wclk => clk, waddress => p.ramaddr1, datain => p.ramdatain1, write => p.ramwrite1
);
-- ram0 : syncram_dp generic map (tech => memtech, abits => RAM_DEPTH, dbits => RAM_DATA_BITS)
-- port map ( clk1 => clk, address1 => p.ramaddr1, datain1 => p.ramdatain1,
-- dataout1 => open, enable1 => p.ramenable1, write1 => p.ramwrite1,
-- clk2 => vgaclk, address2 => r.ramaddr2, datain2 => r.ramdatain2,
-- dataout2 => ramo.dataout2, enable2 => gnd, write2 => gnd);
-- pragma translate_off
bootmsg : report_version
generic map ("apbvga" & tost(pindex) & ": APB VGA module rev 0");
-- pragma translate_on
end architecture;
| gpl-3.0 | a87c7b7215a42516c25a483c266999a4 | 0.531513 | 3.504681 | false | false | false | false |
GLADICOS/SPACEWIRESYSTEMC | altera_work/spw_jaxa/jaxa/jaxa_inst.vhd | 1 | 16,461 | component jaxa is
port (
autostart_external_connection_export : out std_logic; -- export
clk_clk : in std_logic := 'X'; -- clk
controlflagsin_external_connection_export : out std_logic_vector(1 downto 0); -- export
controlflagsout_external_connection_export : in std_logic_vector(1 downto 0) := (others => 'X'); -- export
creditcount_external_connection_export : in std_logic_vector(5 downto 0) := (others => 'X'); -- export
errorstatus_external_connection_export : in std_logic_vector(7 downto 0) := (others => 'X'); -- export
linkdisable_external_connection_export : out std_logic; -- export
linkstart_external_connection_export : out std_logic; -- export
linkstatus_external_connection_export : in std_logic_vector(15 downto 0) := (others => 'X'); -- export
memory_mem_a : out std_logic_vector(12 downto 0); -- mem_a
memory_mem_ba : out std_logic_vector(2 downto 0); -- mem_ba
memory_mem_ck : out std_logic; -- mem_ck
memory_mem_ck_n : out std_logic; -- mem_ck_n
memory_mem_cke : out std_logic; -- mem_cke
memory_mem_cs_n : out std_logic; -- mem_cs_n
memory_mem_ras_n : out std_logic; -- mem_ras_n
memory_mem_cas_n : out std_logic; -- mem_cas_n
memory_mem_we_n : out std_logic; -- mem_we_n
memory_mem_reset_n : out std_logic; -- mem_reset_n
memory_mem_dq : inout std_logic_vector(7 downto 0) := (others => 'X'); -- mem_dq
memory_mem_dqs : inout std_logic := 'X'; -- mem_dqs
memory_mem_dqs_n : inout std_logic := 'X'; -- mem_dqs_n
memory_mem_odt : out std_logic; -- mem_odt
memory_mem_dm : out std_logic; -- mem_dm
memory_oct_rzqin : in std_logic := 'X'; -- oct_rzqin
outstandingcount_external_connection_export : in std_logic_vector(5 downto 0) := (others => 'X'); -- export
pll_0_outclk0_clk : out std_logic; -- clk
receiveactivity_external_connection_export : in std_logic := 'X'; -- export
receiveclock_external_connection_export : out std_logic; -- export
receivefifodatacount_external_connection_export : in std_logic := 'X'; -- export
receivefifodataout_external_connection_export : in std_logic_vector(8 downto 0) := (others => 'X'); -- export
receivefifoempty_external_connection_export : in std_logic := 'X'; -- export
receivefifofull_external_connection_export : in std_logic := 'X'; -- export
receivefiforeadenable_external_connection_export : out std_logic; -- export
spacewiredatain_external_connection_export : out std_logic; -- export
spacewiredataout_external_connection_export : in std_logic := 'X'; -- export
spacewirestrobein_external_connection_export : out std_logic; -- export
spacewirestrobeout_external_connection_export : in std_logic := 'X'; -- export
statisticalinformation_0_external_connection_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
statisticalinformation_1_external_connection_export : out std_logic_vector(7 downto 0); -- export
statisticalinformationclear_external_connection_export : out std_logic; -- export
tickin_external_connection_export : out std_logic; -- export
tickout_external_connection_export : in std_logic := 'X'; -- export
timein_external_connection_export : out std_logic_vector(5 downto 0); -- export
timeout_external_connection_export : in std_logic_vector(5 downto 0) := (others => 'X'); -- export
transmitactivity_external_connection_export : in std_logic := 'X'; -- export
transmitclock_external_connection_export : out std_logic; -- export
transmitclockdividevalue_external_connection_export : out std_logic_vector(5 downto 0); -- export
transmitfifodatacount_external_connection_export : in std_logic_vector(5 downto 0) := (others => 'X'); -- export
transmitfifodatain_external_connection_export : out std_logic_vector(8 downto 0); -- export
transmitfifofull_external_connection_export : in std_logic := 'X'; -- export
transmitfifowriteenable_external_connection_export : out std_logic -- export
);
end component jaxa;
u0 : component jaxa
port map (
autostart_external_connection_export => CONNECTED_TO_autostart_external_connection_export, -- autostart_external_connection.export
clk_clk => CONNECTED_TO_clk_clk, -- clk.clk
controlflagsin_external_connection_export => CONNECTED_TO_controlflagsin_external_connection_export, -- controlflagsin_external_connection.export
controlflagsout_external_connection_export => CONNECTED_TO_controlflagsout_external_connection_export, -- controlflagsout_external_connection.export
creditcount_external_connection_export => CONNECTED_TO_creditcount_external_connection_export, -- creditcount_external_connection.export
errorstatus_external_connection_export => CONNECTED_TO_errorstatus_external_connection_export, -- errorstatus_external_connection.export
linkdisable_external_connection_export => CONNECTED_TO_linkdisable_external_connection_export, -- linkdisable_external_connection.export
linkstart_external_connection_export => CONNECTED_TO_linkstart_external_connection_export, -- linkstart_external_connection.export
linkstatus_external_connection_export => CONNECTED_TO_linkstatus_external_connection_export, -- linkstatus_external_connection.export
memory_mem_a => CONNECTED_TO_memory_mem_a, -- memory.mem_a
memory_mem_ba => CONNECTED_TO_memory_mem_ba, -- .mem_ba
memory_mem_ck => CONNECTED_TO_memory_mem_ck, -- .mem_ck
memory_mem_ck_n => CONNECTED_TO_memory_mem_ck_n, -- .mem_ck_n
memory_mem_cke => CONNECTED_TO_memory_mem_cke, -- .mem_cke
memory_mem_cs_n => CONNECTED_TO_memory_mem_cs_n, -- .mem_cs_n
memory_mem_ras_n => CONNECTED_TO_memory_mem_ras_n, -- .mem_ras_n
memory_mem_cas_n => CONNECTED_TO_memory_mem_cas_n, -- .mem_cas_n
memory_mem_we_n => CONNECTED_TO_memory_mem_we_n, -- .mem_we_n
memory_mem_reset_n => CONNECTED_TO_memory_mem_reset_n, -- .mem_reset_n
memory_mem_dq => CONNECTED_TO_memory_mem_dq, -- .mem_dq
memory_mem_dqs => CONNECTED_TO_memory_mem_dqs, -- .mem_dqs
memory_mem_dqs_n => CONNECTED_TO_memory_mem_dqs_n, -- .mem_dqs_n
memory_mem_odt => CONNECTED_TO_memory_mem_odt, -- .mem_odt
memory_mem_dm => CONNECTED_TO_memory_mem_dm, -- .mem_dm
memory_oct_rzqin => CONNECTED_TO_memory_oct_rzqin, -- .oct_rzqin
outstandingcount_external_connection_export => CONNECTED_TO_outstandingcount_external_connection_export, -- outstandingcount_external_connection.export
pll_0_outclk0_clk => CONNECTED_TO_pll_0_outclk0_clk, -- pll_0_outclk0.clk
receiveactivity_external_connection_export => CONNECTED_TO_receiveactivity_external_connection_export, -- receiveactivity_external_connection.export
receiveclock_external_connection_export => CONNECTED_TO_receiveclock_external_connection_export, -- receiveclock_external_connection.export
receivefifodatacount_external_connection_export => CONNECTED_TO_receivefifodatacount_external_connection_export, -- receivefifodatacount_external_connection.export
receivefifodataout_external_connection_export => CONNECTED_TO_receivefifodataout_external_connection_export, -- receivefifodataout_external_connection.export
receivefifoempty_external_connection_export => CONNECTED_TO_receivefifoempty_external_connection_export, -- receivefifoempty_external_connection.export
receivefifofull_external_connection_export => CONNECTED_TO_receivefifofull_external_connection_export, -- receivefifofull_external_connection.export
receivefiforeadenable_external_connection_export => CONNECTED_TO_receivefiforeadenable_external_connection_export, -- receivefiforeadenable_external_connection.export
spacewiredatain_external_connection_export => CONNECTED_TO_spacewiredatain_external_connection_export, -- spacewiredatain_external_connection.export
spacewiredataout_external_connection_export => CONNECTED_TO_spacewiredataout_external_connection_export, -- spacewiredataout_external_connection.export
spacewirestrobein_external_connection_export => CONNECTED_TO_spacewirestrobein_external_connection_export, -- spacewirestrobein_external_connection.export
spacewirestrobeout_external_connection_export => CONNECTED_TO_spacewirestrobeout_external_connection_export, -- spacewirestrobeout_external_connection.export
statisticalinformation_0_external_connection_export => CONNECTED_TO_statisticalinformation_0_external_connection_export, -- statisticalinformation_0_external_connection.export
statisticalinformation_1_external_connection_export => CONNECTED_TO_statisticalinformation_1_external_connection_export, -- statisticalinformation_1_external_connection.export
statisticalinformationclear_external_connection_export => CONNECTED_TO_statisticalinformationclear_external_connection_export, -- statisticalinformationclear_external_connection.export
tickin_external_connection_export => CONNECTED_TO_tickin_external_connection_export, -- tickin_external_connection.export
tickout_external_connection_export => CONNECTED_TO_tickout_external_connection_export, -- tickout_external_connection.export
timein_external_connection_export => CONNECTED_TO_timein_external_connection_export, -- timein_external_connection.export
timeout_external_connection_export => CONNECTED_TO_timeout_external_connection_export, -- timeout_external_connection.export
transmitactivity_external_connection_export => CONNECTED_TO_transmitactivity_external_connection_export, -- transmitactivity_external_connection.export
transmitclock_external_connection_export => CONNECTED_TO_transmitclock_external_connection_export, -- transmitclock_external_connection.export
transmitclockdividevalue_external_connection_export => CONNECTED_TO_transmitclockdividevalue_external_connection_export, -- transmitclockdividevalue_external_connection.export
transmitfifodatacount_external_connection_export => CONNECTED_TO_transmitfifodatacount_external_connection_export, -- transmitfifodatacount_external_connection.export
transmitfifodatain_external_connection_export => CONNECTED_TO_transmitfifodatain_external_connection_export, -- transmitfifodatain_external_connection.export
transmitfifofull_external_connection_export => CONNECTED_TO_transmitfifofull_external_connection_export, -- transmitfifofull_external_connection.export
transmitfifowriteenable_external_connection_export => CONNECTED_TO_transmitfifowriteenable_external_connection_export -- transmitfifowriteenable_external_connection.export
);
| gpl-3.0 | 8dd60e12b7ffe1228a0223e98b4f957d | 0.481441 | 5.140849 | false | false | false | false |
yishinli/emc2 | src/hal/drivers/mesa-hostmot2/firmware/src/pwmrefh.vhd | 1 | 5,885 | library IEEE;
use IEEE.std_logic_1164.ALL;
use IEEE.std_logic_ARITH.ALL;
use IEEE.std_logic_UNSIGNED.ALL;
--
-- Copyright (C) 2007, Peter C. Wallace, Mesa Electronics
-- http://www.mesanet.com
--
-- This program is is licensed under a disjunctive dual license giving you
-- the choice of one of the two following sets of free software/open source
-- licensing terms:
--
-- * GNU General Public License (GPL), version 2.0 or later
-- * 3-clause BSD License
--
--
-- The GNU GPL License:
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
--
--
-- The 3-clause BSD License:
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- * Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- * Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- * Neither the name of Mesa Electronics nor the names of its
-- contributors may be used to endorse or promote products
-- derived from this software without specific prior written
-- permission.
--
--
-- Disclaimer:
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
entity pwmrefh is
generic (
buswidth : integer;
refwidth : integer
);
Port (
clk: in std_logic;
hclk: in std_logic;
refcount: out std_logic_vector (refwidth-1 downto 0);
ibus: in std_logic_vector (buswidth -1 downto 0);
pdmrate: out std_logic;
pwmrateload: in std_logic;
pdmrateload: in std_logic
);
end pwmrefh;
architecture behavioral of pwmrefh is
signal count: std_logic_vector (refwidth -1 downto 0);
signal pwmrateacc: std_logic_vector (16 downto 0);
alias pwmratemsb: std_logic is pwmrateacc(16);
signal oldpwmratemsb: std_logic;
signal pwmratelatch: std_logic_vector (15 downto 0);
signal prepwmratelatch: std_logic_vector (15 downto 0);
signal pwmratelatchloadreq: std_logic;
signal oldpwmratelatchloadreq: std_logic;
signal olderpwmratelatchloadreq: std_logic;
signal pdmrateacc: std_logic_vector (16 downto 0);
alias pdmratemsb: std_logic is pdmrateacc(16);
signal oldpdmratemsb: std_logic;
signal pdmratelatch: std_logic_vector (15 downto 0);
signal prepdmratelatch: std_logic_vector (15 downto 0);
signal pdmratelatchloadreq: std_logic;
signal oldpdmratelatchloadreq: std_logic;
signal olderpdmratelatchloadreq: std_logic;
signal prate: std_logic;
begin
apwmref: process (clk,
olderpwmratelatchloadreq,
olderpdmratelatchloadreq,
prate,
hclk,
count,
ibus)
begin
if rising_edge(hclk) then -- 100 Mhz high speed clock
if oldpwmratelatchloadreq = '1' and olderpwmratelatchloadreq = '1' then
pwmratelatch <= prepwmratelatch;
end if;
oldpwmratelatchloadreq <= pwmratelatchloadreq;
olderpwmratelatchloadreq <= oldpwmratelatchloadreq;
pwmrateacc <= pwmrateacc + pwmratelatch;
oldpwmratemsb <= pwmratemsb;
if oldpwmratemsb /= pwmratemsb then
count <= count + 1;
end if; -- old /= new
if oldpdmratelatchloadreq = '1' and olderpdmratelatchloadreq = '1' then
pdmratelatch <= prepdmratelatch;
end if;
oldpdmratelatchloadreq <= pdmratelatchloadreq;
olderpdmratelatchloadreq <= oldpdmratelatchloadreq;
pdmrateacc <= pdmrateacc + pdmratelatch;
oldpdmratemsb <= pdmratemsb;
if oldpdmratemsb /= pdmratemsb then
prate <= '1';
else
prate <= '0';
end if; -- old /= new
end if; -- hclk
if rising_edge(clk) then -- 33/48/50 Mhz local bus clock
if pwmrateload = '1' then
prepwmratelatch <= ibus;
pwmratelatchloadreq <= '1';
end if;
if pdmrateload = '1' then
prepdmratelatch <= ibus;
pdmratelatchloadreq <= '1';
end if;
end if; -- clk
if olderpwmratelatchloadreq = '1' then -- asyncronous request clear
pwmratelatchloadreq <= '0';
end if;
if olderpdmratelatchloadreq = '1' then -- asyncronous request clear
pdmratelatchloadreq <= '0';
end if;
refcount <= count;
pdmrate <= prate;
end process;
end behavioral;
| lgpl-2.1 | ccf45134ba9553e0dc65a3c8cd21d1c0 | 0.693968 | 3.532413 | false | false | false | false |
EliasLuiz/TCC | Leon3/lib/gaisler/misc/ahbdpram.vhd | 1 | 5,311 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: ahdpbram
-- File: ahbdpram.vhd
-- Author: Jiri Gaisler - Gaisler Reserch
-- Description: AHB DP ram. 0-waitstate read, 0/1-waitstate write.
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
library techmap;
use techmap.gencomp.all;
entity ahbdpram is
generic (
hindex : integer := 0;
haddr : integer := 0;
hmask : integer := 16#fff#;
tech : integer := 2;
abits : integer range 8 to 19 := 8;
bytewrite : integer range 0 to 1 := 0
);
port (
rst : in std_ulogic;
clk : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
clkdp : in std_ulogic;
address : in std_logic_vector((abits -1) downto 0);
datain : in std_logic_vector(31 downto 0);
dataout : out std_logic_vector(31 downto 0);
enable : in std_ulogic; -- active high chip select
write : in std_logic_vector(0 to 3) -- active high byte write enable
); -- big-endian write: bwrite(0) => data(31:24)
end;
architecture rtl of ahbdpram is
--constant abits : integer := log2(kbytes) + 8;
constant kbytes : integer := 2**(abits - 8);
constant hconfig : ahb_config_type := (
0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_AHBDPRAM, 0, abits+2, 0),
4 => ahb_membar(haddr, '1', '1', hmask),
others => zero32);
type reg_type is record
hwrite : std_ulogic;
hready : std_ulogic;
hsel : std_ulogic;
addr : std_logic_vector(abits+1 downto 0);
size : std_logic_vector(1 downto 0);
end record;
signal r, c : reg_type;
signal ramsel : std_ulogic;
signal bwrite : std_logic_vector(3 downto 0);
signal ramaddr : std_logic_vector(abits-1 downto 0);
signal ramdata : std_logic_vector(31 downto 0);
signal hwdata : std_logic_vector(31 downto 0);
begin
comb : process (ahbsi, r, rst, ramdata)
variable bs : std_logic_vector(3 downto 0);
variable v : reg_type;
variable haddr : std_logic_vector(abits-1 downto 0);
begin
v := r; v.hready := '1'; bs := (others => '0');
if (r.hwrite or not r.hready) = '1' then haddr := r.addr(abits+1 downto 2);
else
haddr := ahbsi.haddr(abits+1 downto 2); bs := (others => '0');
end if;
if ahbsi.hready = '1' then
v.hsel := ahbsi.hsel(hindex) and ahbsi.htrans(1);
v.hwrite := ahbsi.hwrite and v.hsel;
v.addr := ahbsi.haddr(abits+1 downto 0);
v.size := ahbsi.hsize(1 downto 0);
end if;
if r.hwrite = '1' then
case r.size(1 downto 0) is
when "00" => bs (conv_integer(r.addr(1 downto 0))) := '1';
when "01" => bs := r.addr(1) & r.addr(1) & not (r.addr(1) & r.addr(1));
when others => bs := (others => '1');
end case;
v.hready := not (v.hsel and not ahbsi.hwrite);
v.hwrite := v.hwrite and v.hready;
end if;
if rst = '0' then v.hwrite := '0'; v.hready := '1'; end if;
bwrite <= bs; ramsel <= v.hsel or r.hwrite; ahbso.hready <= r.hready;
ramaddr <= haddr; c <= v; ahbso.hrdata <= ahbdrivedata(ramdata);
end process;
ahbso.hresp <= "00";
ahbso.hsplit <= (others => '0');
ahbso.hirq <= (others => '0');
ahbso.hconfig <= hconfig;
ahbso.hindex <= hindex;
hwdata <= ahbreadword(ahbsi.hwdata, r.addr(4 downto 2));
bw : if bytewrite = 1 generate
ra : for i in 0 to 3 generate
aram : syncram_dp generic map (tech, abits, 8) port map (
clk, ramaddr, hwdata(i*8+7 downto i*8),
ramdata(i*8+7 downto i*8), ramsel, bwrite(3-i),
clkdp, address, datain(i*8+7 downto i*8),
dataout(i*8+7 downto i*8), enable, write(3-i)
);
end generate;
end generate;
nobw : if bytewrite = 0 generate
aram : syncram_dp generic map (tech, abits, 32) port map (
clk, ramaddr, hwdata(31 downto 0), ramdata, ramsel, r.hwrite,
clkdp, address, datain, dataout, enable, write(0)
);
end generate;
reg : process (clk)
begin
if rising_edge(clk ) then r <= c; end if;
end process;
-- pragma translate_off
bootmsg : report_version
generic map ("ahbdpram" & tost(hindex) &
": AHB DP SRAM Module, " & tost(kbytes) & " kbytes");
-- pragma translate_on
end;
| gpl-3.0 | 0f07337bb561e43a2016d0309db99d80 | 0.606289 | 3.374206 | false | false | false | false |
hoglet67/CoPro6502 | src/CPU65C02/reg_pc.vhd | 1 | 8,529 | -- VHDL Entity r65c02_tc.reg_pc.symbol
--
-- Created:
-- by - eda.UNKNOWN (ENTW-7HPZ200)
-- at - 11:59:59 06.09.2018
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2016.2 (Build 5)
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
entity reg_pc is
port(
adr_i : in std_logic_vector (15 downto 0);
clk_clk_i : in std_logic;
ld_i : in std_logic_vector (1 downto 0);
ld_pc_i : in std_logic;
offset_i : in std_logic_vector (15 downto 0);
rst_rst_n_i : in std_logic;
sel_pc_in_i : in std_logic;
sel_pc_val_i : in std_logic_vector (1 downto 0);
adr_nxt_pc_o : out std_logic_vector (15 downto 0);
adr_pc_o : out std_logic_vector (15 downto 0)
);
-- Declarations
end reg_pc ;
-- (C) 2008 - 2018 Jens Gutschmidt
-- (email: [email protected])
--
-- Versions:
-- Revision 1.7 2013/07/21 11:11:00 jens
-- - Changing the title block and internal revision history
--
-- Revision 1.6 2009/01/04 10:20:47 eda
-- Changes for cosmetic issues only
--
-- Revision 1.5 2009/01/04 09:23:10 eda
-- - Delete unused nets and blocks (same as R6502_TC)
-- - Rename blocks
--
-- Revision 1.4 2009/01/03 16:53:02 eda
-- - Unused nets and blocks deleted
-- - Renamed blocks
--
-- Revision 1.3 2009/01/03 16:42:02 eda
-- - Unused nets and blocks deleted
-- - Renamed blocks
--
-- Revision 1.2 2008/12/31 19:31:24 eda
-- Production Release
--
--
--
-- VHDL Architecture r65c02_tc.reg_pc.struct
--
-- Created:
-- by - eda.UNKNOWN (ENTW-7HPZ200)
-- at - 11:59:59 06.09.2018
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2016.2 (Build 5)
--
-- COPYRIGHT (C) 2008 - 2018 by Jens Gutschmidt
--
-- This program is free software: you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation, either version 3 of the License, or any later version.
--
-- This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License along with this program. If not, see <http://www.gnu.org/licenses/>.
--
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
architecture struct of reg_pc is
-- Architecture declarations
-- Internal signal declarations
signal adr_pc_high_o_i : std_logic_vector(7 downto 0);
signal adr_pc_low_o_i : std_logic_vector(7 downto 0);
signal adr_pc_o_i : std_logic_vector(15 downto 0);
signal ci_o_i : std_logic;
signal cout_pc_o_i : std_logic;
signal load3_o_i : std_logic;
signal load_o_i : std_logic;
signal offset_high_o_i : std_logic_vector(7 downto 0);
signal offset_low_o_i : std_logic_vector(7 downto 0);
signal val_o_i : std_logic_vector(7 downto 0);
signal val_one : std_logic_vector(7 downto 0);
signal val_zero : std_logic_vector(7 downto 0);
-- Implicit buffer signal declarations
signal adr_nxt_pc_o_internal : std_logic_vector (15 downto 0);
signal adr_pc_o_internal : std_logic_vector (15 downto 0);
-- ModuleWare signal declarations(v1.12) for instance 'U_0' of 'adff'
signal mw_U_0reg_cval : std_logic_vector(7 downto 0);
-- ModuleWare signal declarations(v1.12) for instance 'U_4' of 'adff'
signal mw_U_4reg_cval : std_logic_vector(7 downto 0);
-- ModuleWare signal declarations(v1.12) for instance 'U_3' of 'split'
signal mw_U_3temp_din : std_logic_vector(15 downto 0);
-- ModuleWare signal declarations(v1.12) for instance 'U_5' of 'split'
signal mw_U_5temp_din : std_logic_vector(15 downto 0);
begin
-- ModuleWare code(v1.12) for instance 'U_2' of 'add'
u_2combo_proc: process (adr_pc_low_o_i, val_o_i)
variable temp_din0 : std_logic_vector(8 downto 0);
variable temp_din1 : std_logic_vector(8 downto 0);
variable temp_sum : unsigned(8 downto 0);
variable temp_carry : std_logic;
begin
temp_din0 := '0' & adr_pc_low_o_i;
temp_din1 := '0' & val_o_i;
temp_carry := '0';
temp_sum := unsigned(temp_din0) + unsigned(temp_din1) + temp_carry;
adr_nxt_pc_o_internal(7 DOWNTO 0) <= conv_std_logic_vector(temp_sum(7 downto 0),8);
cout_pc_o_i <= temp_sum(8) ;
end process u_2combo_proc;
-- ModuleWare code(v1.12) for instance 'U_11' of 'add'
u_11combo_proc: process (adr_pc_high_o_i, offset_high_o_i, ci_o_i)
variable temp_din0 : std_logic_vector(8 downto 0);
variable temp_din1 : std_logic_vector(8 downto 0);
variable temp_sum : unsigned(8 downto 0);
variable temp_carry : std_logic;
begin
temp_din0 := '0' & adr_pc_high_o_i;
temp_din1 := '0' & offset_high_o_i;
temp_carry := ci_o_i;
temp_sum := unsigned(temp_din0) + unsigned(temp_din1) + temp_carry;
adr_nxt_pc_o_internal(15 DOWNTO 8) <= conv_std_logic_vector(temp_sum(7 downto 0),8);
end process u_11combo_proc;
-- ModuleWare code(v1.12) for instance 'U_0' of 'adff'
adr_pc_o_internal(7 DOWNTO 0) <= mw_U_0reg_cval;
u_0seq_proc: process (clk_clk_i, rst_rst_n_i)
begin
if (rst_rst_n_i = '0') then
mw_U_0reg_cval <= "00000000";
elsif (clk_clk_i'event and clk_clk_i='1') then
if (load_o_i = '1') then
mw_U_0reg_cval <= adr_nxt_pc_o_internal(7 DOWNTO 0);
end if;
end if;
end process u_0seq_proc;
-- ModuleWare code(v1.12) for instance 'U_4' of 'adff'
adr_pc_o_internal(15 DOWNTO 8) <= mw_U_4reg_cval;
u_4seq_proc: process (clk_clk_i, rst_rst_n_i)
begin
if (rst_rst_n_i = '0') then
mw_U_4reg_cval <= "00000000";
elsif (clk_clk_i'event and clk_clk_i='1') then
if (load3_o_i = '1') then
mw_U_4reg_cval <= adr_nxt_pc_o_internal(15 DOWNTO 8);
end if;
end if;
end process u_4seq_proc;
-- ModuleWare code(v1.12) for instance 'U_6' of 'and'
load_o_i <= ld_pc_i and ld_i(0);
-- ModuleWare code(v1.12) for instance 'U_7' of 'and'
load3_o_i <= ld_pc_i and ld_i(1);
-- ModuleWare code(v1.12) for instance 'U_10' of 'and'
ci_o_i <= cout_pc_o_i and ld_pc_i;
-- ModuleWare code(v1.12) for instance 'U_1' of 'constval'
val_zero <= "00000000";
-- ModuleWare code(v1.12) for instance 'U_9' of 'constval'
val_one <= "00000001";
-- ModuleWare code(v1.12) for instance 'U_8' of 'mux'
u_8combo_proc: process(adr_pc_o_internal, adr_i, sel_pc_in_i)
begin
case sel_pc_in_i is
when '0' => adr_pc_o_i <= adr_pc_o_internal;
when '1' => adr_pc_o_i <= adr_i;
when others => adr_pc_o_i <= (others => 'X');
end case;
end process u_8combo_proc;
-- ModuleWare code(v1.12) for instance 'U_13' of 'mux'
u_13combo_proc: process(val_one, val_zero, offset_low_o_i,
sel_pc_val_i)
begin
case sel_pc_val_i is
when "00" => val_o_i <= val_one;
when "01" => val_o_i <= val_zero;
when "10" => val_o_i <= offset_low_o_i;
when "11" => val_o_i <= val_zero;
when others => val_o_i <= (others => 'X');
end case;
end process u_13combo_proc;
-- ModuleWare code(v1.12) for instance 'U_3' of 'split'
mw_U_3temp_din <= adr_pc_o_i;
u_3combo_proc: process (mw_U_3temp_din)
variable temp_din: std_logic_vector(15 downto 0);
begin
temp_din := mw_U_3temp_din(15 downto 0);
adr_pc_low_o_i <= temp_din(7 downto 0);
adr_pc_high_o_i <= temp_din(15 downto 8);
end process u_3combo_proc;
-- ModuleWare code(v1.12) for instance 'U_5' of 'split'
mw_U_5temp_din <= offset_i;
u_5combo_proc: process (mw_U_5temp_din)
variable temp_din: std_logic_vector(15 downto 0);
begin
temp_din := mw_U_5temp_din(15 downto 0);
offset_low_o_i <= temp_din(7 downto 0);
offset_high_o_i <= temp_din(15 downto 8);
end process u_5combo_proc;
-- Instance port mappings.
-- Implicit buffered output assignments
adr_nxt_pc_o <= adr_nxt_pc_o_internal;
adr_pc_o <= adr_pc_o_internal;
end struct;
| gpl-3.0 | 5156e7b208c2bbccf1f0e022bc6b41e2 | 0.600891 | 2.917893 | false | false | false | false |
EliasLuiz/TCC | Leon3/designs/leon3-xilinx-ml40x/config.vhd | 1 | 6,790 |
-----------------------------------------------------------------------------
-- LEON3 Demonstration design test bench configuration
-- Copyright (C) 2009 Aeroflex Gaisler
------------------------------------------------------------------------------
library techmap;
use techmap.gencomp.all;
package config is
-- Technology and synthesis options
constant CFG_FABTECH : integer := virtex4;
constant CFG_MEMTECH : integer := virtex4;
constant CFG_PADTECH : integer := virtex4;
constant CFG_TRANSTECH : integer := GTP0;
constant CFG_NOASYNC : integer := 0;
constant CFG_SCAN : integer := 0;
-- Clock generator
constant CFG_CLKTECH : integer := virtex4;
constant CFG_CLKMUL : integer := (13);
constant CFG_CLKDIV : integer := (20);
constant CFG_OCLKDIV : integer := 1;
constant CFG_OCLKBDIV : integer := 0;
constant CFG_OCLKCDIV : integer := 0;
constant CFG_PCIDLL : integer := 0;
constant CFG_PCISYSCLK: integer := 0;
constant CFG_CLK_NOFB : integer := 0;
-- LEON3 processor core
constant CFG_LEON3 : integer := 1;
constant CFG_NCPU : integer := (1);
constant CFG_NWIN : integer := (8);
constant CFG_V8 : integer := 16#32# + 4*0;
constant CFG_MAC : integer := 0;
constant CFG_BP : integer := 0;
constant CFG_SVT : integer := 1;
constant CFG_RSTADDR : integer := 16#00000#;
constant CFG_LDDEL : integer := (1);
constant CFG_NOTAG : integer := 0;
constant CFG_NWP : integer := (2);
constant CFG_PWD : integer := 1*2;
constant CFG_FPU : integer := 0 + 16*0 + 32*0;
constant CFG_GRFPUSH : integer := 0;
constant CFG_ICEN : integer := 1;
constant CFG_ISETS : integer := 2;
constant CFG_ISETSZ : integer := 8;
constant CFG_ILINE : integer := 8;
constant CFG_IREPL : integer := 0;
constant CFG_ILOCK : integer := 0;
constant CFG_ILRAMEN : integer := 0;
constant CFG_ILRAMADDR: integer := 16#8E#;
constant CFG_ILRAMSZ : integer := 1;
constant CFG_DCEN : integer := 1;
constant CFG_DSETS : integer := 2;
constant CFG_DSETSZ : integer := 4;
constant CFG_DLINE : integer := 4;
constant CFG_DREPL : integer := 0;
constant CFG_DLOCK : integer := 0;
constant CFG_DSNOOP : integer := 0 + 1*2 + 4*0;
constant CFG_DFIXED : integer := 16#0#;
constant CFG_DLRAMEN : integer := 0;
constant CFG_DLRAMADDR: integer := 16#8F#;
constant CFG_DLRAMSZ : integer := 1;
constant CFG_MMUEN : integer := 1;
constant CFG_ITLBNUM : integer := 8;
constant CFG_DTLBNUM : integer := 8;
constant CFG_TLB_TYPE : integer := 0 + 1*2;
constant CFG_TLB_REP : integer := 0;
constant CFG_MMU_PAGE : integer := 0;
constant CFG_DSU : integer := 1;
constant CFG_ITBSZ : integer := 2 + 64*0;
constant CFG_ATBSZ : integer := 2;
constant CFG_AHBPF : integer := 0;
constant CFG_LEON3FT_EN : integer := 0;
constant CFG_IUFT_EN : integer := 0;
constant CFG_FPUFT_EN : integer := 0;
constant CFG_RF_ERRINJ : integer := 0;
constant CFG_CACHE_FT_EN : integer := 0;
constant CFG_CACHE_ERRINJ : integer := 0;
constant CFG_LEON3_NETLIST: integer := 0;
constant CFG_DISAS : integer := 0 + 0;
constant CFG_PCLOW : integer := 2;
constant CFG_STAT_ENABLE : integer := 0;
constant CFG_STAT_CNT : integer := 1;
constant CFG_STAT_NMAX : integer := 0;
constant CFG_STAT_DSUEN : integer := 0;
constant CFG_NP_ASI : integer := 0;
constant CFG_WRPSR : integer := 0;
constant CFG_ALTWIN : integer := 0;
constant CFG_REX : integer := 0;
-- AMBA settings
constant CFG_DEFMST : integer := (0);
constant CFG_RROBIN : integer := 1;
constant CFG_SPLIT : integer := 1;
constant CFG_FPNPEN : integer := 0;
constant CFG_AHBIO : integer := 16#FFF#;
constant CFG_APBADDR : integer := 16#800#;
constant CFG_AHB_MON : integer := 0;
constant CFG_AHB_MONERR : integer := 0;
constant CFG_AHB_MONWAR : integer := 0;
constant CFG_AHB_DTRACE : integer := 0;
-- DSU UART
constant CFG_AHB_UART : integer := 0;
-- JTAG based DSU interface
constant CFG_AHB_JTAG : integer := 1;
-- Ethernet DSU
constant CFG_DSU_ETH : integer := 1 + 0 + 0;
constant CFG_ETH_BUF : integer := 2;
constant CFG_ETH_IPM : integer := 16#C0A8#;
constant CFG_ETH_IPL : integer := 16#0033#;
constant CFG_ETH_ENM : integer := 16#020000#;
constant CFG_ETH_ENL : integer := 16#00002F#;
-- LEON2 memory controller
constant CFG_MCTRL_LEON2 : integer := 1;
constant CFG_MCTRL_RAM8BIT : integer := 0;
constant CFG_MCTRL_RAM16BIT : integer := 0;
constant CFG_MCTRL_5CS : integer := 0;
constant CFG_MCTRL_SDEN : integer := 0;
constant CFG_MCTRL_SEPBUS : integer := 0;
constant CFG_MCTRL_INVCLK : integer := 0;
constant CFG_MCTRL_SD64 : integer := 0;
constant CFG_MCTRL_PAGE : integer := 0 + 0;
-- DDR controller
constant CFG_DDRSP : integer := 1;
constant CFG_DDRSP_INIT : integer := 1;
constant CFG_DDRSP_FREQ : integer := (100);
constant CFG_DDRSP_COL : integer := (9);
constant CFG_DDRSP_SIZE : integer := (64);
constant CFG_DDRSP_RSKEW : integer := (0);
-- SSRAM controller
constant CFG_SSCTRL : integer := 0;
constant CFG_SSCTRLP16 : integer := 0;
-- AHB status register
constant CFG_AHBSTAT : integer := 1;
constant CFG_AHBSTATN : integer := (1);
-- AHB ROM
constant CFG_AHBROMEN : integer := 0;
constant CFG_AHBROPIP : integer := 0;
constant CFG_AHBRODDR : integer := 16#000#;
constant CFG_ROMADDR : integer := 16#000#;
constant CFG_ROMMASK : integer := 16#E00# + 16#000#;
-- AHB RAM
constant CFG_AHBRAMEN : integer := 0;
constant CFG_AHBRSZ : integer := 1;
constant CFG_AHBRADDR : integer := 16#A00#;
constant CFG_AHBRPIPE : integer := 0;
-- Gaisler Ethernet core
constant CFG_GRETH : integer := 1;
constant CFG_GRETH1G : integer := 0;
constant CFG_ETH_FIFO : integer := 32;
-- UART 1
constant CFG_UART1_ENABLE : integer := 1;
constant CFG_UART1_FIFO : integer := 4;
-- LEON3 interrupt controller
constant CFG_IRQ3_ENABLE : integer := 1;
constant CFG_IRQ3_NSEC : integer := 0;
-- Modular timer
constant CFG_GPT_ENABLE : integer := 1;
constant CFG_GPT_NTIM : integer := (2);
constant CFG_GPT_SW : integer := (8);
constant CFG_GPT_TW : integer := (32);
constant CFG_GPT_IRQ : integer := (8);
constant CFG_GPT_SEPIRQ : integer := 1;
constant CFG_GPT_WDOGEN : integer := 0;
constant CFG_GPT_WDOG : integer := 16#0#;
-- GPIO port
constant CFG_GRGPIO_ENABLE : integer := 1;
constant CFG_GRGPIO_IMASK : integer := 16#0FFFE#;
constant CFG_GRGPIO_WIDTH : integer := (32);
-- I2C master
constant CFG_I2C_ENABLE : integer := 1;
-- VGA and PS2/ interface
constant CFG_KBD_ENABLE : integer := 0;
constant CFG_VGA_ENABLE : integer := 0;
constant CFG_SVGA_ENABLE : integer := 0;
-- AMBA System ACE Interface Controller
constant CFG_GRACECTRL : integer := 1;
-- GRLIB debugging
constant CFG_DUART : integer := 0;
end;
| gpl-3.0 | 8fbd66d501b9afa193c75beacc376d9a | 0.645803 | 3.607864 | false | false | false | false |
EliasLuiz/TCC | Leon3/lib/gaisler/pci/ptf/pt_pci_arb.vhd | 1 | 4,050 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: pt_pci_arb
-- File: pt_pci_arb.vhd
-- Author: Alf Vaerneus, Gaisler Research
-- Description: PCI arbiter
------------------------------------------------------------------------------
-- pragma translate_off
library ieee;
use ieee.std_logic_1164.all;
library gaisler;
use gaisler.pt_pkg.all;
entity pt_pci_arb is
generic (
slots : integer := 5;
tval : time := 7 ns);
port (
systclk : in pci_syst_type;
ifcin : in pci_ifc_type;
arbin : in pci_arb_type;
arbout : out pci_arb_type);
end pt_pci_arb;
architecture tb of pt_pci_arb is
type queue_type is array (0 to slots-1) of integer range 0 to slots;
signal queue : queue_type;
signal queue_nr : integer range 0 to slots;
signal wfbus : boolean;
begin
arb : process(systclk)
variable i, slotgnt : integer;
variable set : boolean;
variable bus_idle : boolean;
variable vqueue_nr : integer range 0 to slots;
variable gnt,req : std_logic_vector(slots-1 downto 0);
begin
set := false; vqueue_nr := queue_nr;
if (ifcin.frame and ifcin.irdy) = '1' then bus_idle := true; else bus_idle := false; end if;
gnt := to_x01(arbin.gnt(slots-1 downto 0));
req := to_x01(arbin.req(slots-1 downto 0));
if systclk.rst = '0' then
gnt := (others => '1');
wfbus <= false;
for i in 0 to slots-1 loop
queue(i) <= 0;
end loop;
queue_nr <= 0;
elsif rising_edge(systclk.clk) then
for i in 0 to slots-1 loop
if (gnt(i) or req(i)) = '0' then
if (bus_idle or wfbus) then
set := true;
end if;
end if;
end loop;
for i in 0 to slots-1 loop
if (gnt(i) and not req(i)) = '1' then
if queue(i) = 0 then
vqueue_nr := vqueue_nr+1;
queue(i) <= vqueue_nr;
elsif (queue(i) = 1 and set = false) then
gnt := (others => '1'); gnt(i) := '0';
queue(i) <= 0;
if not bus_idle then wfbus <= true; end if;
if vqueue_nr > 0 then vqueue_nr := vqueue_nr-1; end if;
elsif queue(i) >= 2 then
if (set = false or vqueue_nr <= 1) then
queue(i) <= queue(i)-1;
-- if vqueue_nr > 0 then vqueue_nr := vqueue_nr-1; end if;
end if;
end if;
elsif (req(i) and not gnt(i)) = '1' then
queue(i) <= 0; gnt(i) := '1';
-- if vqueue_nr > 0 then vqueue_nr := vqueue_nr-1; end if;
elsif (req(i) and gnt(i)) = '1' then
if (queue(i) > 0 and set = false) then
queue(i) <= queue(i)-1;
if (vqueue_nr > 0 and queue(i) = 1) then vqueue_nr := vqueue_nr-1; end if;
end if;
end if;
end loop;
end if;
if bus_idle then wfbus <= false; end if;
queue_nr <= vqueue_nr;
arbout.req <= (others => 'Z');
arbout.gnt <= (others => 'Z');
arbout.gnt(slots-1 downto 0) <= gnt;
end process;
end;
-- pragma translate_on
| gpl-3.0 | ddd3887108c966f0c6936d55f333c9c6 | 0.555062 | 3.497409 | false | false | false | false |
Gizeta/bjuedc | uart-fpga/uart.vhd | 1 | 5,248 | --------------------------------------------
-- 串口收发实验
-- Filename: uart
-- PIN_89--->P1.2
--------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity uart is -- 定义uart实体
port(
clkin, resetin : in std_logic; -- clkin 为50M
rxd : in std_logic; -- 串行输入数据
txd : out std_logic; -- 串行输出数据
wei : out std_logic_vector(3 downto 0); -- S0 ~ S3
duan : out std_logic_vector(7 downto 0)
);
end uart;
architecture arch of uart is
component gen_div is -- 分频元件调用声明
-- 326分频, 326 * 16 * (9600) = 50M
-- 波特率为9600
generic(div_param : integer := 163);
port(
clk_in : in std_logic;
clk_out : out std_logic;
reset : in std_logic
);
end component;
component uart_send is -- 串口发送元件调用声明
port(
bclk_t, reset_t, xmit_cmd_p : in std_logic;
tbuf : in std_logic_vector(7 downto 0);
txd : out std_logic;
t_done : out std_logic
);
end component;
component uart_recv is -- 串口接受元件调用声明
port(
bclk_r, reset_r, rxd : in std_logic;
r_ready : out std_logic;
rbuf : out std_logic_vector(7 downto 0)
);
end component;
component narr_sig is -- 信号窄化元件声明调用
port(
sig_in : in std_logic;
clk : in std_logic;
reset : in std_logic;
narr_prd : in std_logic_vector(7 downto 0);
narr_sig_out : out std_logic
);
end component;
signal clk_b : std_logic; -- 波特率时钟
signal clk1 : std_logic; -- 数码管时钟
signal xmit_p : std_logic; -- 新一轮发送启动信号
signal xbuf : std_logic_vector(7 downto 0); -- 待发送数据缓冲区
signal txd_done_iner : std_logic; -- 帧数据发送完标志
signal rev_buf : std_logic_vector(7 downto 0); -- 接收数据缓冲区
signal rev_ready : std_logic; -- 帧数据接受完标志
begin
---------------------------------
-- 分频模块例化
---------------------------------
uart_baud: gen_div
generic map(163)
port map(
clk_in => clkin,
reset => not resetin,
clk_out => clk_b
);
---------------------------------
-- 分频模块例化
---------------------------------
seg_clk: gen_div
generic map(10) -- 20分频
port map(
clk_in => clkin,
reset => not resetin,
clk_out => clk1
);
---------------------------------
-- 串口发送模块例化
---------------------------------
uart_transfer: uart_send
port map(
bclk_t => clk_b,
reset_t => not resetin,
xmit_cmd_p => xmit_p,
tbuf => xbuf,
txd => txd,
t_done => txd_done_iner
);
---------------------------------
-- 串口接收元件例化
---------------------------------
uart_receive: uart_recv
port map(
bclk_r => clk_b,
reset_r => not resetin,
rxd => rxd,
r_ready => rev_ready,
rbuf => rev_buf
);
---------------------------------
-- 信号窄化模块例化
---------------------------------
narr_rev_ready: narr_sig -- 窄化rev_ready信号后给xmit_p
port map(
sig_in => rev_ready, -- 输入需窄化信号
clk => clk_b,
reset => not resetin,
narr_prd => X"03", -- narr信号高电平持续的周期数(以clk为周期)
narr_sig_out => xmit_p -- 输出窄化后信号
);
process(rev_ready, resetin, rev_buf, clk_b)
begin
if rising_edge(rev_ready) then -- 接收完毕
xbuf <= rev_buf; -- 装载数据
end if;
end process;
display: process(clk1, rev_ready, rev_buf)
begin
if rising_edge(rev_ready) then -- 接收完毕
case rev_buf(7 downto 4) is -- 前四位为位选信息
when "0001" => wei <= "1000"; -- 1
when "0010" => wei <= "0100"; -- 2
when "0011" => wei <= "0010"; -- 3
when "0100" => wei <= "0001"; -- 4
when "1001" => wei <= "1000"; -- 1.
when "1010" => wei <= "0100"; -- 2.
when "1011" => wei <= "0010"; -- 3.
when "1100" => wei <= "0001"; -- 4.
when others => wei <= "0000";
end case;
case rev_buf(3 downto 0) is -- 后四位为位选信息
when "0000" => duan <= x"3f"; -- 0
when "0001" => duan <= x"06"; -- 1
when "0010" => duan <= x"5b"; -- 2
when "0011" => duan <= x"4f"; -- 3
when "0100" => duan <= x"66"; -- 4
when "0101" => duan <= x"6d"; -- 5
when "0110" => duan <= x"7d"; -- 6
when "0111" => duan <= x"07"; -- 7
when "1000" => duan <= x"7f"; -- 8
when "1001" => duan <= x"6f"; -- 9
when others => duan <= x"00";
end case;
if rev_buf(7) = '1' then
duan(7) <= '1';
end if;
end if;
end process;
end arch;
| mit | a99ddd74a69c5156f7d22543320066cd | 0.442851 | 2.822287 | false | false | false | false |
yishinli/emc2 | src/hal/drivers/mesa-hostmot2/firmware/src/IDParms.vhd | 1 | 202,741 |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_UNSIGNED.ALL;
use IEEE.std_logic_ARITH.ALL;
--
-- Copyright (C) 2007, Peter C. Wallace, Mesa Electronics
-- http://www.mesanet.com
--
-- This program is is licensed under a disjunctive dual license giving you
-- the choice of one of the two following sets of free software/open source
-- licensing terms:
--
-- * GNU General Public License (GPL), version 2.0 or later
-- * 3-clause BSD License
--
--
-- The GNU GPL License:
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
--
--
-- The 3-clause BSD License:
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- * Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- * Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- * Neither the name of Mesa Electronics nor the names of its
-- contributors may be used to endorse or promote products
-- derived from this software without specific prior written
-- permission.
--
--
-- Disclaimer:
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
package IDROMParms is
constant NullAddr : std_logic_vector(7 downto 0) := x"00";
constant ReadIDAddr : std_logic_vector(7 downto 0) := x"01";
constant LEDAddr : std_logic_vector(7 downto 0) := x"02";
constant LEDNumRegs : std_logic_vector(7 downto 0) := x"01";
constant LEDMPBitMask : std_logic_vector(31 downto 0) := x"00000000";
constant IDROMAddr : std_logic_vector(7 downto 0) := x"04";
constant Cookie : std_logic_vector(31 downto 0) := x"55AACAFE";
constant HostMotNameLow : std_logic_vector(31 downto 0) := x"54534F48"; -- HOST
constant HostMotNameHigh : std_logic_vector(31 downto 0) := x"32544F4D"; -- MOT2
constant BoardNameMesa : std_logic_vector(31 downto 0) := x"4153454D"; -- MESA
constant BoardName4I65 : std_logic_vector(31 downto 0) := x"35364934"; -- 4I65
constant BoardName4I68 : std_logic_vector(31 downto 0) := x"38364934"; -- 4I68
constant BoardName5I20 : std_logic_vector(31 downto 0) := x"30324935"; -- 5I20
constant BoardName5I22 : std_logic_vector(31 downto 0) := x"32324935"; -- 5I22
constant BoardName5I23 : std_logic_vector(31 downto 0) := x"33324935"; -- 5I23
constant BoardName7I43 : std_logic_vector(31 downto 0) := x"33344937"; -- 7I43
constant BoardName7I60 : std_logic_vector(31 downto 0) := x"30364937"; -- 7I60
constant IDROMOffset : std_logic_vector(31 downto 0) := x"0000"&IDROMAddr&x"00"; -- note need to change if pitch changed
constant IDROMWEnAddr : std_logic_vector(7 downto 0) := x"08";
constant IRQDivAddr : std_logic_vector(7 downto 0) := x"09";
constant IRQStatusAddr : std_logic_vector(7 downto 0) := x"0A";
constant ClearIRQAddr : std_logic_vector(7 downto 0) := x"0B";
constant IRQNumRegs : std_logic_vector(7 downto 0) := x"03";
constant IRQMPBitMask : std_logic_vector(31 downto 0) := x"00000000";
constant WatchdogTimeAddr : std_logic_vector(7 downto 0) := x"0C";
constant WatchDogStatusAddr : std_logic_vector(7 downto 0) := x"0D";
constant WatchDogCookieAddr : std_logic_vector(7 downto 0) := x"0E";
constant WatchDogNumRegs : std_logic_vector(7 downto 0) := x"03";
constant WatchDogMPBitMask : std_logic_vector(31 downto 0) := x"00000000";
constant PortAddr : std_logic_vector(7 downto 0) := x"10";
constant DDRAddr : std_logic_vector(7 downto 0) := x"11";
constant AltDataSrcAddr : std_logic_vector(7 downto 0) := x"12";
constant OpenDrainModeAddr : std_logic_vector(7 downto 0) := x"13";
constant OutputInvAddr : std_logic_vector(7 downto 0) := x"14";
constant IOPortNumRegs : std_logic_vector(7 downto 0) := x"05";
constant IOPortMPBitMask : std_logic_vector(31 downto 0) := x"0000001F";
constant StepGenRateAddr : std_logic_vector(7 downto 0) := x"20";
constant StepGenAccumAddr : std_logic_vector(7 downto 0) := x"21";
constant StepGenModeAddr : std_logic_vector(7 downto 0) := x"22";
constant StepGenDSUTimeAddr : std_logic_vector(7 downto 0) := x"23";
constant StepGenDHLDTimeAddr : std_logic_vector(7 downto 0) := x"24";
constant StepGenPulseATimeAddr : std_logic_vector(7 downto 0) := x"25";
constant StepGenPulseITimeAddr : std_logic_vector(7 downto 0) := x"26";
constant StepGenTableAddr : std_logic_vector(7 downto 0) := x"27";
constant StepGenTableMaxAddr : std_logic_vector(7 downto 0) := x"28";
constant StepGenBasicRateAddr : std_logic_vector(7 downto 0) := x"29";
constant StepGenNumRegs : std_logic_vector(7 downto 0) := x"0A";
constant StepGenMPBitMask : std_logic_vector(31 downto 0) := x"000001FF";
constant QCounterAddr : std_logic_vector(7 downto 0) := x"30";
constant QCounterCCRAddr : std_logic_vector(7 downto 0) := x"31";
constant TSDivAddr : std_logic_vector(7 downto 0) := x"32";
constant TSAddr : std_logic_vector(7 downto 0) := x"33";
constant QCRateAddr : std_logic_vector(7 downto 0) := x"34";
constant QCounterNumRegs : std_logic_vector(7 downto 0) := x"05";
constant QCounterMPBitMask : std_logic_vector(31 downto 0) := x"00000003";
constant MuxedQCounterAddr : std_logic_vector(7 downto 0) := x"35";
constant MuxedQCounterCCRAddr : std_logic_vector(7 downto 0) := x"36";
constant MuxedTSDivAddr : std_logic_vector(7 downto 0) := x"37";
constant MuxedTSAddr : std_logic_vector(7 downto 0) := x"38";
constant MuxedQCRateAddr : std_logic_vector(7 downto 0) := x"39";
constant MuxedQCounterNumRegs : std_logic_vector(7 downto 0) := x"05";
constant MuxedQCounterMPBitMask : std_logic_vector(31 downto 0) := x"00000003";
constant PWMValAddr : std_logic_vector(7 downto 0) := x"40";
constant PWMCRAddr : std_logic_vector(7 downto 0) := x"41";
constant PWMRateAddr : std_logic_vector(7 downto 0) := x"42";
constant PDMRateAddr : std_logic_vector(7 downto 0) := x"43";
constant PWMEnasAddr : std_logic_vector(7 downto 0) := x"44";
constant PWMNumRegs : std_logic_vector(7 downto 0) := x"05";
constant PWMMPBitMask : std_logic_vector(31 downto 0) := x"00000003";
constant SPIDataAddr : std_logic_vector(7 downto 0) := x"50";
constant SPIBitCountAddr : std_logic_vector(7 downto 0) := x"51";
constant SPIBitrateAddr : std_logic_vector(7 downto 0) := x"52";
constant SPINumRegs : std_logic_vector(7 downto 0) := x"03";
constant SPIMPBitMask : std_logic_vector(31 downto 0) := x"00000007";
constant BSPIDataAddr : std_logic_vector(7 downto 0) := x"54";
constant BSPIDescriptorAddr : std_logic_vector(7 downto 0) := x"55";
constant BSPIFIFOCountAddr : std_logic_vector(7 downto 0) := x"56";
constant BSPINumRegs : std_logic_vector(7 downto 0) := x"03";
constant BSPIMPBitMask : std_logic_vector(31 downto 0) := x"00000007";
constant UARTTDataAddr : std_logic_vector(7 downto 0) := x"60";
constant UARTTFIFOCountAddr : std_logic_vector(7 downto 0) := x"61";
constant UARTTBitrateAddr: std_logic_vector(7 downto 0) := x"62";
constant UARTTModeRegAddr : std_logic_vector(7 downto 0) := x"63";
constant UARTTNumRegs : std_logic_vector(7 downto 0) := x"04";
constant UARTTMPBitMask : std_logic_vector(31 downto 0) := x"0000000F";
constant UARTRDataAddr : std_logic_vector(7 downto 0) := x"70";
constant UARTRFIFOCountAddr : std_logic_vector(7 downto 0) := x"71";
constant UARTRBitrateAddr : std_logic_vector(7 downto 0) := x"72";
constant UARTRModeRegAddr : std_logic_vector(7 downto 0) := x"73";
constant UARTRNumRegs : std_logic_vector(7 downto 0) := x"04";
constant UARTRMPBitMask : std_logic_vector(31 downto 0) := x"0000000F";
constant TranslateRamAddr : std_logic_vector(7 downto 0) := x"78";
constant TranslateRegionAddr : std_logic_vector(7 downto 0) := x"7C";
constant TranslateNumRegs : std_logic_vector(7 downto 0) := x"04";
constant TranslateMPBitMask : std_logic_vector(31 downto 0) := x"00000000";
constant ClockLow20: integer := 33333333; -- 5I20/4I65 low speed clock
constant ClockLow22: integer := 48000000; -- 5I22/5I23 low speed clock
constant ClockLow43: integer := 50000000; -- 7I43 low speed clock
constant ClockLow43U: integer := 33333333; -- 7I43U low speed clock
constant ClockLow68: integer := 48000000; -- 4I68 low speed clock
constant ClockHigh20: integer := 100000000; -- 5I20/4I65 high speed clock
constant ClockHigh22: integer := 96000000; -- 5I22/5I23 high speed clock
constant ClockHigh43: integer := 100000000; -- 7I43 high speed clock
constant ClockHigh43U: integer := 100000000; -- 7I43U high speed clock
constant ClockHigh68: integer := 96000000; -- 4I68 high speed clock
constant ClockLowTag: std_logic_vector(7 downto 0) := x"01";
constant ClockHighTag: std_logic_vector(7 downto 0) := x"02";
constant NullTag : std_logic_vector(7 downto 0) := x"00";
constant NullPin : std_logic_vector(7 downto 0) := x"00";
constant IRQLogicTag : std_logic_vector(7 downto 0) := x"01";
constant WatchDogTag : std_logic_vector(7 downto 0) := x"02";
constant IOPortTag : std_logic_vector(7 downto 0) := x"03";
constant QCountTag : std_logic_vector(7 downto 0) := x"04";
constant QCountQAPin : std_logic_vector(7 downto 0) := x"01";
constant QCountQBPin : std_logic_vector(7 downto 0) := x"02";
constant QCountIdxPin : std_logic_vector(7 downto 0) := x"03";
constant QCountIdxMaskPin : std_logic_vector(7 downto 0) := x"04";
constant StepGenTag : std_logic_vector(7 downto 0) := x"05";
constant StepGenStepPin : std_logic_vector(7 downto 0) := x"81";
constant StepGenDirPin : std_logic_vector(7 downto 0) := x"82";
constant StepGenTable2Pin : std_logic_vector(7 downto 0) := x"83";
constant StepGenTable3Pin : std_logic_vector(7 downto 0) := x"84";
constant StepGenTable4Pin : std_logic_vector(7 downto 0) := x"85";
constant StepGenTable5Pin : std_logic_vector(7 downto 0) := x"86";
constant StepGenTable6Pin : std_logic_vector(7 downto 0) := x"87";
constant StepGenTable7Pin : std_logic_vector(7 downto 0) := x"88";
constant PWMTag : std_logic_vector(7 downto 0) := x"06";
constant PWMAOutPin : std_logic_vector(7 downto 0) := x"81";
constant PWMBDirPin : std_logic_vector(7 downto 0) := x"82";
constant PWMCEnaPin : std_logic_vector(7 downto 0) := x"83";
constant SPITag : std_logic_vector(7 downto 0) := x"07";
constant SPIFramePin : std_logic_vector(7 downto 0) := x"81";
constant SPIOutPin : std_logic_vector(7 downto 0) := x"82";
constant SPIClkPin : std_logic_vector(7 downto 0) := x"83";
constant SPIInPin : std_logic_vector(7 downto 0) := x"04";
constant SSITag : std_logic_vector(7 downto 0) := x"08";
constant UARTTTag : std_logic_vector(7 downto 0) := x"09";
constant UTDataPin : std_logic_vector(7 downto 0) := x"81";
constant UTDrvEnPin : std_logic_vector(7 downto 0) := x"82";
constant UARTRTag : std_logic_vector(7 downto 0) := x"0A";
constant URDataPin : std_logic_vector(7 downto 0) := x"01";
constant AddrXTag : std_logic_vector(7 downto 0) := x"0B";
constant MuxedQCountTag: std_logic_vector(7 downto 0) := x"0C";
constant MuxedQCountQAPin : std_logic_vector(7 downto 0) := x"01";
constant MuxedQCountQBPin : std_logic_vector(7 downto 0) := x"02";
constant MuxedQCountIdxPin : std_logic_vector(7 downto 0) := x"03";
constant MuxedQCountIdxMaskPin : std_logic_vector(7 downto 0) := x"04";
constant MuxedQCountSelTag: std_logic_vector(7 downto 0) := x"0D";
constant MuxedQCountSel0Pin : std_logic_vector(7 downto 0) := x"81";
constant MuxedQCountSel1Pin : std_logic_vector(7 downto 0) := x"82";
constant BSPITag : std_logic_vector(7 downto 0) := x"0E";
constant BSPIFramePin : std_logic_vector(7 downto 0) := x"81";
constant BSPIOutPin : std_logic_vector(7 downto 0) := x"82";
constant BSPIClkPin : std_logic_vector(7 downto 0) := x"83";
constant BSPIInPin : std_logic_vector(7 downto 0) := x"04";
constant BSPICS0Pin : std_logic_vector(7 downto 0) := x"85";
constant BSPICS1Pin : std_logic_vector(7 downto 0) := x"86";
constant BSPICS2Pin : std_logic_vector(7 downto 0) := x"87";
constant BSPICS3Pin : std_logic_vector(7 downto 0) := x"88";
constant BSPICS4Pin : std_logic_vector(7 downto 0) := x"89";
constant BSPICS5Pin : std_logic_vector(7 downto 0) := x"8A";
constant BSPICS6Pin : std_logic_vector(7 downto 0) := x"8B";
constant BSPICS7Pin : std_logic_vector(7 downto 0) := x"8C";
constant LEDTag : std_logic_vector(7 downto 0) := x"80";
constant emptypin : std_logic_vector(31 downto 0) := x"00000000";
constant empty : std_logic_vector(31 downto 0) := x"00000000";
constant PadT : std_logic_vector(7 downto 0) := x"00";
constant MaxModules : integer := 32; -- maximum number of module types
constant MaxPins : integer := 128; -- maximum number of I/O pins (may change to 144 with 3X20)
-- would be better to change all the pindescs to records
-- but that requires reversing the byte order of the constant
-- pindesc arrays, some other day...
type PinDescRecord is -- not used yet!
record
SecPin : std_logic_vector(7 downto 0);
SecFunc : std_logic_vector(7 downto 0);
SecInst : std_logic_vector(7 downto 0);
PriFunc : std_logic_vector(7 downto 0);
end record;
type PinDescType is array(0 to MaxPins -1) of std_logic_vector(31 downto 0);
type ModuleRecord is
record
GTag : std_logic_vector(7 downto 0);
Version : std_logic_vector(7 downto 0);
Clock : std_logic_vector(7 downto 0);
NumInstances : std_logic_vector(7 downto 0);
BaseAddr : std_logic_vector(15 downto 0);
NumRegisters : std_logic_vector(7 downto 0);
Strides : std_logic_vector(7 downto 0);
MultRegs : std_logic_vector(31 downto 0);
end record;
type ModuleIDType is array(0 to MaxModules-1) of ModuleRecord;
-- These messy constants must remain until I make a script
-- to generate them based on configuration parameters
-------------------------------------------------------------------------------------------------
-- first 2 connector pinouts (7I43)
-------------------------------------------------------------------------------------------------
constant ModuleID_SV8 : ModuleIDType :=(
(WatchDogTag, x"00", ClockLowTag, x"01", WatchDogTimeAddr&PadT, WatchDogNumRegs, x"00", WatchDogMPBitMask),
(IOPortTag, x"00", ClockLowTag, x"02", PortAddr&PadT, IOPortNumRegs, x"00", IOPortMPBitMask),
(QcountTag, x"02", ClockLowTag, x"08", QcounterAddr&PadT, QCounterNumRegs, x"00", QCounterMPBitMask),
(PWMTag, x"00", ClockHighTag, x"08", PWMValAddr&PadT, PWMNumRegs, x"00", PWMMPBitMask),
(AddrXTag, x"00", ClockLowTag, x"01", TranslateRAMAddr&PadT, TranslateNumRegs, x"00", TranslateMPBitMask),
(LEDTag, x"00", ClockLowTag, x"01", LEDAddr&PadT, LEDNumRegs, x"00", LEDMPBitMask),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000")
);
constant PinDesc_SV8 : PinDescType :=(
-- Base func sec unit sec func sec pin
IOPortTag & x"01" & QCountTag & x"02",
IOPortTag & x"01" & QCountTag & x"01",
IOPortTag & x"00" & QCountTag & x"02",
IOPortTag & x"00" & QCountTag & x"01",
IOPortTag & x"01" & QCountTag & x"03",
IOPortTag & x"00" & QCountTag & x"03",
IOPortTag & x"01" & PWMTag & x"81",
IOPortTag & x"00" & PWMTag & x"81",
IOPortTag & x"01" & PWMTag & x"82",
IOPortTag & x"00" & PWMTag & x"82",
IOPortTag & x"01" & PWMTag & x"83",
IOPortTag & x"00" & PWMTag & x"83",
IOPortTag & x"03" & QCountTag & x"02",
IOPortTag & x"03" & QCountTag & x"01",
IOPortTag & x"02" & QCountTag & x"02",
IOPortTag & x"02" & QCountTag & x"01",
IOPortTag & x"03" & QCountTag & x"03",
IOPortTag & x"02" & QCountTag & x"03",
IOPortTag & x"03" & PWMTag & x"81",
IOPortTag & x"02" & PWMTag & x"81",
IOPortTag & x"03" & PWMTag & x"82",
IOPortTag & x"02" & PWMTag & x"82",
IOPortTag & x"03" & PWMTag & x"83",
IOPortTag & x"02" & PWMTag & x"83",
IOPortTag & x"05" & QCountTag & x"02",
IOPortTag & x"05" & QCountTag & x"01",
IOPortTag & x"04" & QCountTag & x"02",
IOPortTag & x"04" & QCountTag & x"01",
IOPortTag & x"05" & QCountTag & x"03",
IOPortTag & x"04" & QCountTag & x"03",
IOPortTag & x"05" & PWMTag & x"81",
IOPortTag & x"04" & PWMTag & x"81",
IOPortTag & x"05" & PWMTag & x"82",
IOPortTag & x"04" & PWMTag & x"82",
IOPortTag & x"05" & PWMTag & x"83",
IOPortTag & x"04" & PWMTag & x"83",
IOPortTag & x"07" & QCountTag & x"02",
IOPortTag & x"07" & QCountTag & x"01",
IOPortTag & x"06" & QCountTag & x"02",
IOPortTag & x"06" & QCountTag & x"01",
IOPortTag & x"07" & QCountTag & x"03",
IOPortTag & x"06" & QCountTag & x"03",
IOPortTag & x"07" & PWMTag & x"81",
IOPortTag & x"06" & PWMTag & x"81",
IOPortTag & x"07" & PWMTag & x"82",
IOPortTag & x"06" & PWMTag & x"82",
IOPortTag & x"07" & PWMTag & x"83",
IOPortTag & x"06" & PWMTag & x"83",
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin);
constant ModuleID_SVST4_4 : ModuleIDType :=(
(WatchDogTag, x"00", ClockLowTag, x"01", WatchDogTimeAddr&PadT, WatchDogNumRegs, x"00", WatchDogMPBitMask),
(IOPortTag, x"00", ClockLowTag, x"02", PortAddr&PadT, IOPortNumRegs, x"00", IOPortMPBitMask),
(QcountTag, x"02", ClockLowTag, x"04", QcounterAddr&PadT, QCounterNumRegs, x"00", QCounterMPBitMask),
(PWMTag, x"00", ClockHighTag, x"04", PWMValAddr&PadT, PWMNumRegs, x"00", PWMMPBitMask),
(StepGenTag, x"01", ClockLowTag, x"04", StepGenRateAddr&PadT, StepGenNumRegs, x"00", StepGenMPBitMask),
(AddrXTag, x"00", ClockLowTag, x"01", TranslateRAMAddr&PadT, TranslateNumRegs, x"00", TranslateMPBitMask),
(LEDTag, x"00", ClockLowTag, x"01", LEDAddr&PadT, LEDNumRegs, x"00", LEDMPBitMask),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000")
);
constant PinDesc_SVST4_4 : PinDescType :=(
-- Base func sec unit sec func sec pin
IOPortTag & x"01" & QCountTag & x"02",
IOPortTag & x"01" & QCountTag & x"01",
IOPortTag & x"00" & QCountTag & x"02",
IOPortTag & x"00" & QCountTag & x"01",
IOPortTag & x"01" & QCountTag & x"03",
IOPortTag & x"00" & QCountTag & x"03",
IOPortTag & x"01" & PWMTag & x"81",
IOPortTag & x"00" & PWMTag & x"81",
IOPortTag & x"01" & PWMTag & x"82",
IOPortTag & x"00" & PWMTag & x"82",
IOPortTag & x"01" & PWMTag & x"83",
IOPortTag & x"00" & PWMTag & x"83",
IOPortTag & x"03" & QCountTag & x"02",
IOPortTag & x"03" & QCountTag & x"01",
IOPortTag & x"02" & QCountTag & x"02",
IOPortTag & x"02" & QCountTag & x"01",
IOPortTag & x"03" & QCountTag & x"03",
IOPortTag & x"02" & QCountTag & x"03",
IOPortTag & x"03" & PWMTag & x"81",
IOPortTag & x"02" & PWMTag & x"81",
IOPortTag & x"03" & PWMTag & x"82",
IOPortTag & x"02" & PWMTag & x"82",
IOPortTag & x"03" & PWMTag & x"83",
IOPortTag & x"02" & PWMTag & x"83",
IOPortTag & x"00" & StepGenTag & x"81",
IOPortTag & x"00" & StepGenTag & x"82",
IOPortTag & x"00" & StepGenTag & x"83",
IOPortTag & x"00" & StepGenTag & x"84",
IOPortTag & x"00" & StepGenTag & x"85",
IOPortTag & x"00" & StepGenTag & x"86",
IOPortTag & x"01" & StepGenTag & x"81",
IOPortTag & x"01" & StepGenTag & x"82",
IOPortTag & x"01" & StepGenTag & x"83",
IOPortTag & x"01" & StepGenTag & x"84",
IOPortTag & x"01" & StepGenTag & x"85",
IOPortTag & x"01" & StepGenTag & x"86",
IOPortTag & x"02" & StepGenTag & x"81",
IOPortTag & x"02" & StepGenTag & x"82",
IOPortTag & x"02" & StepGenTag & x"83",
IOPortTag & x"02" & StepGenTag & x"84",
IOPortTag & x"02" & StepGenTag & x"85",
IOPortTag & x"02" & StepGenTag & x"86",
IOPortTag & x"03" & StepGenTag & x"81",
IOPortTag & x"03" & StepGenTag & x"82",
IOPortTag & x"03" & StepGenTag & x"83",
IOPortTag & x"03" & StepGenTag & x"84",
IOPortTag & x"03" & StepGenTag & x"85",
IOPortTag & x"03" & StepGenTag & x"86",
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin);
constant ModuleID_SVST4_6 : ModuleIDType :=(
(WatchDogTag, x"00", ClockLowTag, x"01", WatchDogTimeAddr&PadT, WatchDogNumRegs, x"00", WatchDogMPBitMask),
(IOPortTag, x"00", ClockLowTag, x"02", PortAddr&PadT, IOPortNumRegs, x"00", IOPortMPBitMask),
(QcountTag, x"02", ClockLowTag, x"04", QcounterAddr&PadT, QCounterNumRegs, x"00", QCounterMPBitMask),
(PWMTag, x"00", ClockHighTag, x"04", PWMValAddr&PadT, PWMNumRegs, x"00", PWMMPBitMask),
(StepGenTag, x"01", ClockLowTag, x"06", StepGenRateAddr&PadT, StepGenNumRegs, x"00", StepGenMPBitMask),
(AddrXTag, x"00", ClockLowTag, x"01", TranslateRAMAddr&PadT, TranslateNumRegs, x"00", TranslateMPBitMask),
(LEDTag, x"00", ClockLowTag, x"01", LEDAddr&PadT, LEDNumRegs, x"00", LEDMPBitMask),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000")
);
constant PinDesc_SVST4_6 : PinDescType :=(
-- Base func sec unit sec func sec pin
IOPortTag & x"01" & QCountTag & x"02",
IOPortTag & x"01" & QCountTag & x"01",
IOPortTag & x"00" & QCountTag & x"02",
IOPortTag & x"00" & QCountTag & x"01",
IOPortTag & x"01" & QCountTag & x"03",
IOPortTag & x"00" & QCountTag & x"03",
IOPortTag & x"01" & PWMTag & x"81",
IOPortTag & x"00" & PWMTag & x"81",
IOPortTag & x"01" & PWMTag & x"82",
IOPortTag & x"00" & PWMTag & x"82",
IOPortTag & x"01" & PWMTag & x"83",
IOPortTag & x"00" & PWMTag & x"83",
IOPortTag & x"03" & QCountTag & x"02",
IOPortTag & x"03" & QCountTag & x"01",
IOPortTag & x"02" & QCountTag & x"02",
IOPortTag & x"02" & QCountTag & x"01",
IOPortTag & x"03" & QCountTag & x"03",
IOPortTag & x"02" & QCountTag & x"03",
IOPortTag & x"03" & PWMTag & x"81",
IOPortTag & x"02" & PWMTag & x"81",
IOPortTag & x"03" & PWMTag & x"82",
IOPortTag & x"02" & PWMTag & x"82",
IOPortTag & x"03" & PWMTag & x"83",
IOPortTag & x"02" & PWMTag & x"83",
IOPortTag & x"00" & StepGenTag & x"81",
IOPortTag & x"00" & StepGenTag & x"82",
IOPortTag & x"00" & StepGenTag & x"83",
IOPortTag & x"00" & StepGenTag & x"84",
IOPortTag & x"01" & StepGenTag & x"81",
IOPortTag & x"01" & StepGenTag & x"82",
IOPortTag & x"01" & StepGenTag & x"83",
IOPortTag & x"01" & StepGenTag & x"84",
IOPortTag & x"02" & StepGenTag & x"81",
IOPortTag & x"02" & StepGenTag & x"82",
IOPortTag & x"02" & StepGenTag & x"83",
IOPortTag & x"02" & StepGenTag & x"84",
IOPortTag & x"03" & StepGenTag & x"81",
IOPortTag & x"03" & StepGenTag & x"82",
IOPortTag & x"03" & StepGenTag & x"83",
IOPortTag & x"03" & StepGenTag & x"84",
IOPortTag & x"04" & StepGenTag & x"81",
IOPortTag & x"04" & StepGenTag & x"82",
IOPortTag & x"04" & StepGenTag & x"83",
IOPortTag & x"04" & StepGenTag & x"84",
IOPortTag & x"05" & StepGenTag & x"81",
IOPortTag & x"05" & StepGenTag & x"82",
IOPortTag & x"05" & StepGenTag & x"83",
IOPortTag & x"05" & StepGenTag & x"84",
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin);
constant ModuleID_SVST4_12 : ModuleIDType :=(
(WatchDogTag, x"00", ClockLowTag, x"01", WatchDogTimeAddr&PadT, WatchDogNumRegs, x"00", WatchDogMPBitMask),
(IOPortTag, x"00", ClockLowTag, x"02", PortAddr&PadT, IOPortNumRegs, x"00", IOPortMPBitMask),
(QcountTag, x"02", ClockLowTag, x"04", QcounterAddr&PadT, QCounterNumRegs, x"00", QCounterMPBitMask),
(PWMTag, x"00", ClockHighTag, x"04", PWMValAddr&PadT, PWMNumRegs, x"00", PWMMPBitMask),
(StepGenTag, x"01", ClockLowTag, x"0C", StepGenRateAddr&PadT, StepGenNumRegs, x"00", StepGenMPBitMask),
(AddrXTag, x"00", ClockLowTag, x"01", TranslateRAMAddr&PadT, TranslateNumRegs, x"00", TranslateMPBitMask),
(LEDTag, x"00", ClockLowTag, x"01", LEDAddr&PadT, LEDNumRegs, x"00", LEDMPBitMask),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000")
);
constant PinDesc_SVST4_12 : PinDescType :=(
-- Base func sec unit sec func sec pin
IOPortTag & x"01" & QCountTag & x"02",
IOPortTag & x"01" & QCountTag & x"01",
IOPortTag & x"00" & QCountTag & x"02",
IOPortTag & x"00" & QCountTag & x"01",
IOPortTag & x"01" & QCountTag & x"03",
IOPortTag & x"00" & QCountTag & x"03",
IOPortTag & x"01" & PWMTag & x"81",
IOPortTag & x"00" & PWMTag & x"81",
IOPortTag & x"01" & PWMTag & x"82",
IOPortTag & x"00" & PWMTag & x"82",
IOPortTag & x"01" & PWMTag & x"83",
IOPortTag & x"00" & PWMTag & x"83",
IOPortTag & x"03" & QCountTag & x"02",
IOPortTag & x"03" & QCountTag & x"01",
IOPortTag & x"02" & QCountTag & x"02",
IOPortTag & x"02" & QCountTag & x"01",
IOPortTag & x"03" & QCountTag & x"03",
IOPortTag & x"02" & QCountTag & x"03",
IOPortTag & x"03" & PWMTag & x"81",
IOPortTag & x"02" & PWMTag & x"81",
IOPortTag & x"03" & PWMTag & x"82",
IOPortTag & x"02" & PWMTag & x"82",
IOPortTag & x"03" & PWMTag & x"83",
IOPortTag & x"02" & PWMTag & x"83",
IOPortTag & x"00" & StepGenTag & x"81",
IOPortTag & x"00" & StepGenTag & x"82",
IOPortTag & x"01" & StepGenTag & x"81",
IOPortTag & x"01" & StepGenTag & x"82",
IOPortTag & x"02" & StepGenTag & x"81",
IOPortTag & x"02" & StepGenTag & x"82",
IOPortTag & x"03" & StepGenTag & x"81",
IOPortTag & x"03" & StepGenTag & x"82",
IOPortTag & x"04" & StepGenTag & x"81",
IOPortTag & x"04" & StepGenTag & x"82",
IOPortTag & x"05" & StepGenTag & x"81",
IOPortTag & x"05" & StepGenTag & x"82",
IOPortTag & x"06" & StepGenTag & x"81",
IOPortTag & x"06" & StepGenTag & x"82",
IOPortTag & x"07" & StepGenTag & x"81",
IOPortTag & x"07" & StepGenTag & x"82",
IOPortTag & x"08" & StepGenTag & x"81",
IOPortTag & x"08" & StepGenTag & x"82",
IOPortTag & x"09" & StepGenTag & x"81",
IOPortTag & x"09" & StepGenTag & x"82",
IOPortTag & x"0A" & StepGenTag & x"81",
IOPortTag & x"0A" & StepGenTag & x"82",
IOPortTag & x"0B" & StepGenTag & x"81",
IOPortTag & x"0B" & StepGenTag & x"82",
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin);
-------------------------------------------------------------------------------------------------
-- 7I43 USB configurations with no TRAM
-------------------------------------------------------------------------------------------------
constant ModuleID_SV8NA : ModuleIDType :=(
(WatchDogTag, x"00", ClockLowTag, x"01", WatchDogTimeAddr&PadT, WatchDogNumRegs, x"00", WatchDogMPBitMask),
(IOPortTag, x"00", ClockLowTag, x"02", PortAddr&PadT, IOPortNumRegs, x"00", IOPortMPBitMask),
(QcountTag, x"02", ClockLowTag, x"08", QcounterAddr&PadT, QCounterNumRegs, x"00", QCounterMPBitMask),
(PWMTag, x"00", ClockHighTag, x"08", PWMValAddr&PadT, PWMNumRegs, x"00", PWMMPBitMask),
(LEDTag, x"00", ClockLowTag, x"01", LEDAddr&PadT, LEDNumRegs, x"00", LEDMPBitMask),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000")
);
constant PinDesc_SV8NA : PinDescType :=(
-- Base func sec unit sec func sec pin
IOPortTag & x"01" & QCountTag & x"02",
IOPortTag & x"01" & QCountTag & x"01",
IOPortTag & x"00" & QCountTag & x"02",
IOPortTag & x"00" & QCountTag & x"01",
IOPortTag & x"01" & QCountTag & x"03",
IOPortTag & x"00" & QCountTag & x"03",
IOPortTag & x"01" & PWMTag & x"81",
IOPortTag & x"00" & PWMTag & x"81",
IOPortTag & x"01" & PWMTag & x"82",
IOPortTag & x"00" & PWMTag & x"82",
IOPortTag & x"01" & PWMTag & x"83",
IOPortTag & x"00" & PWMTag & x"83",
IOPortTag & x"03" & QCountTag & x"02",
IOPortTag & x"03" & QCountTag & x"01",
IOPortTag & x"02" & QCountTag & x"02",
IOPortTag & x"02" & QCountTag & x"01",
IOPortTag & x"03" & QCountTag & x"03",
IOPortTag & x"02" & QCountTag & x"03",
IOPortTag & x"03" & PWMTag & x"81",
IOPortTag & x"02" & PWMTag & x"81",
IOPortTag & x"03" & PWMTag & x"82",
IOPortTag & x"02" & PWMTag & x"82",
IOPortTag & x"03" & PWMTag & x"83",
IOPortTag & x"02" & PWMTag & x"83",
IOPortTag & x"05" & QCountTag & x"02",
IOPortTag & x"05" & QCountTag & x"01",
IOPortTag & x"04" & QCountTag & x"02",
IOPortTag & x"04" & QCountTag & x"01",
IOPortTag & x"05" & QCountTag & x"03",
IOPortTag & x"04" & QCountTag & x"03",
IOPortTag & x"05" & PWMTag & x"81",
IOPortTag & x"04" & PWMTag & x"81",
IOPortTag & x"05" & PWMTag & x"82",
IOPortTag & x"04" & PWMTag & x"82",
IOPortTag & x"05" & PWMTag & x"83",
IOPortTag & x"04" & PWMTag & x"83",
IOPortTag & x"07" & QCountTag & x"02",
IOPortTag & x"07" & QCountTag & x"01",
IOPortTag & x"06" & QCountTag & x"02",
IOPortTag & x"06" & QCountTag & x"01",
IOPortTag & x"07" & QCountTag & x"03",
IOPortTag & x"06" & QCountTag & x"03",
IOPortTag & x"07" & PWMTag & x"81",
IOPortTag & x"06" & PWMTag & x"81",
IOPortTag & x"07" & PWMTag & x"82",
IOPortTag & x"06" & PWMTag & x"82",
IOPortTag & x"07" & PWMTag & x"83",
IOPortTag & x"06" & PWMTag & x"83",
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin);
constant ModuleID_SVST4_4NA : ModuleIDType :=(
(WatchDogTag, x"00", ClockLowTag, x"01", WatchDogTimeAddr&PadT, WatchDogNumRegs, x"00", WatchDogMPBitMask),
(IOPortTag, x"00", ClockLowTag, x"02", PortAddr&PadT, IOPortNumRegs, x"00", IOPortMPBitMask),
(QcountTag, x"02", ClockLowTag, x"04", QcounterAddr&PadT, QCounterNumRegs, x"00", QCounterMPBitMask),
(PWMTag, x"00", ClockHighTag, x"04", PWMValAddr&PadT, PWMNumRegs, x"00", PWMMPBitMask),
(StepGenTag, x"01", ClockLowTag, x"04", StepGenRateAddr&PadT, StepGenNumRegs, x"00", StepGenMPBitMask),
(LEDTag, x"00", ClockLowTag, x"01", LEDAddr&PadT, LEDNumRegs, x"00", LEDMPBitMask),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000")
);
constant PinDesc_SVST4_4NA : PinDescType :=(
-- Base func sec unit sec func sec pin
IOPortTag & x"01" & QCountTag & x"02",
IOPortTag & x"01" & QCountTag & x"01",
IOPortTag & x"00" & QCountTag & x"02",
IOPortTag & x"00" & QCountTag & x"01",
IOPortTag & x"01" & QCountTag & x"03",
IOPortTag & x"00" & QCountTag & x"03",
IOPortTag & x"01" & PWMTag & x"81",
IOPortTag & x"00" & PWMTag & x"81",
IOPortTag & x"01" & PWMTag & x"82",
IOPortTag & x"00" & PWMTag & x"82",
IOPortTag & x"01" & PWMTag & x"83",
IOPortTag & x"00" & PWMTag & x"83",
IOPortTag & x"03" & QCountTag & x"02",
IOPortTag & x"03" & QCountTag & x"01",
IOPortTag & x"02" & QCountTag & x"02",
IOPortTag & x"02" & QCountTag & x"01",
IOPortTag & x"03" & QCountTag & x"03",
IOPortTag & x"02" & QCountTag & x"03",
IOPortTag & x"03" & PWMTag & x"81",
IOPortTag & x"02" & PWMTag & x"81",
IOPortTag & x"03" & PWMTag & x"82",
IOPortTag & x"02" & PWMTag & x"82",
IOPortTag & x"03" & PWMTag & x"83",
IOPortTag & x"02" & PWMTag & x"83",
IOPortTag & x"00" & StepGenTag & x"81",
IOPortTag & x"00" & StepGenTag & x"82",
IOPortTag & x"00" & StepGenTag & x"83",
IOPortTag & x"00" & StepGenTag & x"84",
IOPortTag & x"00" & StepGenTag & x"85",
IOPortTag & x"00" & StepGenTag & x"86",
IOPortTag & x"01" & StepGenTag & x"81",
IOPortTag & x"01" & StepGenTag & x"82",
IOPortTag & x"01" & StepGenTag & x"83",
IOPortTag & x"01" & StepGenTag & x"84",
IOPortTag & x"01" & StepGenTag & x"85",
IOPortTag & x"01" & StepGenTag & x"86",
IOPortTag & x"02" & StepGenTag & x"81",
IOPortTag & x"02" & StepGenTag & x"82",
IOPortTag & x"02" & StepGenTag & x"83",
IOPortTag & x"02" & StepGenTag & x"84",
IOPortTag & x"02" & StepGenTag & x"85",
IOPortTag & x"02" & StepGenTag & x"86",
IOPortTag & x"03" & StepGenTag & x"81",
IOPortTag & x"03" & StepGenTag & x"82",
IOPortTag & x"03" & StepGenTag & x"83",
IOPortTag & x"03" & StepGenTag & x"84",
IOPortTag & x"03" & StepGenTag & x"85",
IOPortTag & x"03" & StepGenTag & x"86",
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin);
constant ModuleID_SVST4_6NA : ModuleIDType :=(
(WatchDogTag, x"00", ClockLowTag, x"01", WatchDogTimeAddr&PadT, WatchDogNumRegs, x"00", WatchDogMPBitMask),
(IOPortTag, x"00", ClockLowTag, x"02", PortAddr&PadT, IOPortNumRegs, x"00", IOPortMPBitMask),
(QcountTag, x"02", ClockLowTag, x"04", QcounterAddr&PadT, QCounterNumRegs, x"00", QCounterMPBitMask),
(PWMTag, x"00", ClockHighTag, x"04", PWMValAddr&PadT, PWMNumRegs, x"00", PWMMPBitMask),
(StepGenTag, x"01", ClockLowTag, x"06", StepGenRateAddr&PadT, StepGenNumRegs, x"00", StepGenMPBitMask),
(LEDTag, x"00", ClockLowTag, x"01", LEDAddr&PadT, LEDNumRegs, x"00", LEDMPBitMask),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000")
);
constant PinDesc_SVST4_6NA : PinDescType :=(
-- Base func sec unit sec func sec pin
IOPortTag & x"01" & QCountTag & x"02",
IOPortTag & x"01" & QCountTag & x"01",
IOPortTag & x"00" & QCountTag & x"02",
IOPortTag & x"00" & QCountTag & x"01",
IOPortTag & x"01" & QCountTag & x"03",
IOPortTag & x"00" & QCountTag & x"03",
IOPortTag & x"01" & PWMTag & x"81",
IOPortTag & x"00" & PWMTag & x"81",
IOPortTag & x"01" & PWMTag & x"82",
IOPortTag & x"00" & PWMTag & x"82",
IOPortTag & x"01" & PWMTag & x"83",
IOPortTag & x"00" & PWMTag & x"83",
IOPortTag & x"03" & QCountTag & x"02",
IOPortTag & x"03" & QCountTag & x"01",
IOPortTag & x"02" & QCountTag & x"02",
IOPortTag & x"02" & QCountTag & x"01",
IOPortTag & x"03" & QCountTag & x"03",
IOPortTag & x"02" & QCountTag & x"03",
IOPortTag & x"03" & PWMTag & x"81",
IOPortTag & x"02" & PWMTag & x"81",
IOPortTag & x"03" & PWMTag & x"82",
IOPortTag & x"02" & PWMTag & x"82",
IOPortTag & x"03" & PWMTag & x"83",
IOPortTag & x"02" & PWMTag & x"83",
IOPortTag & x"00" & StepGenTag & x"81",
IOPortTag & x"00" & StepGenTag & x"82",
IOPortTag & x"00" & StepGenTag & x"83",
IOPortTag & x"00" & StepGenTag & x"84",
IOPortTag & x"01" & StepGenTag & x"81",
IOPortTag & x"01" & StepGenTag & x"82",
IOPortTag & x"01" & StepGenTag & x"83",
IOPortTag & x"01" & StepGenTag & x"84",
IOPortTag & x"02" & StepGenTag & x"81",
IOPortTag & x"02" & StepGenTag & x"82",
IOPortTag & x"02" & StepGenTag & x"83",
IOPortTag & x"02" & StepGenTag & x"84",
IOPortTag & x"03" & StepGenTag & x"81",
IOPortTag & x"03" & StepGenTag & x"82",
IOPortTag & x"03" & StepGenTag & x"83",
IOPortTag & x"03" & StepGenTag & x"84",
IOPortTag & x"04" & StepGenTag & x"81",
IOPortTag & x"04" & StepGenTag & x"82",
IOPortTag & x"04" & StepGenTag & x"83",
IOPortTag & x"04" & StepGenTag & x"84",
IOPortTag & x"05" & StepGenTag & x"81",
IOPortTag & x"05" & StepGenTag & x"82",
IOPortTag & x"05" & StepGenTag & x"83",
IOPortTag & x"05" & StepGenTag & x"84",
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin);
constant ModuleID_SVST4_12NA : ModuleIDType :=(
(WatchDogTag, x"00", ClockLowTag, x"01", WatchDogTimeAddr&PadT, WatchDogNumRegs, x"00", WatchDogMPBitMask),
(IOPortTag, x"00", ClockLowTag, x"02", PortAddr&PadT, IOPortNumRegs, x"00", IOPortMPBitMask),
(QcountTag, x"02", ClockLowTag, x"04", QcounterAddr&PadT, QCounterNumRegs, x"00", QCounterMPBitMask),
(PWMTag, x"00", ClockHighTag, x"04", PWMValAddr&PadT, PWMNumRegs, x"00", PWMMPBitMask),
(StepGenTag, x"01", ClockLowTag, x"0C", StepGenRateAddr&PadT, StepGenNumRegs, x"00", StepGenMPBitMask),
(LEDTag, x"00", ClockLowTag, x"01", LEDAddr&PadT, LEDNumRegs, x"00", LEDMPBitMask),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000")
);
constant PinDesc_SVST4_12NA : PinDescType :=(
-- Base func sec unit sec func sec pin
IOPortTag & x"01" & QCountTag & x"02",
IOPortTag & x"01" & QCountTag & x"01",
IOPortTag & x"00" & QCountTag & x"02",
IOPortTag & x"00" & QCountTag & x"01",
IOPortTag & x"01" & QCountTag & x"03",
IOPortTag & x"00" & QCountTag & x"03",
IOPortTag & x"01" & PWMTag & x"81",
IOPortTag & x"00" & PWMTag & x"81",
IOPortTag & x"01" & PWMTag & x"82",
IOPortTag & x"00" & PWMTag & x"82",
IOPortTag & x"01" & PWMTag & x"83",
IOPortTag & x"00" & PWMTag & x"83",
IOPortTag & x"03" & QCountTag & x"02",
IOPortTag & x"03" & QCountTag & x"01",
IOPortTag & x"02" & QCountTag & x"02",
IOPortTag & x"02" & QCountTag & x"01",
IOPortTag & x"03" & QCountTag & x"03",
IOPortTag & x"02" & QCountTag & x"03",
IOPortTag & x"03" & PWMTag & x"81",
IOPortTag & x"02" & PWMTag & x"81",
IOPortTag & x"03" & PWMTag & x"82",
IOPortTag & x"02" & PWMTag & x"82",
IOPortTag & x"03" & PWMTag & x"83",
IOPortTag & x"02" & PWMTag & x"83",
IOPortTag & x"00" & StepGenTag & x"81",
IOPortTag & x"00" & StepGenTag & x"82",
IOPortTag & x"01" & StepGenTag & x"81",
IOPortTag & x"01" & StepGenTag & x"82",
IOPortTag & x"02" & StepGenTag & x"81",
IOPortTag & x"02" & StepGenTag & x"82",
IOPortTag & x"03" & StepGenTag & x"81",
IOPortTag & x"03" & StepGenTag & x"82",
IOPortTag & x"04" & StepGenTag & x"81",
IOPortTag & x"04" & StepGenTag & x"82",
IOPortTag & x"05" & StepGenTag & x"81",
IOPortTag & x"05" & StepGenTag & x"82",
IOPortTag & x"06" & StepGenTag & x"81",
IOPortTag & x"06" & StepGenTag & x"82",
IOPortTag & x"07" & StepGenTag & x"81",
IOPortTag & x"07" & StepGenTag & x"82",
IOPortTag & x"08" & StepGenTag & x"81",
IOPortTag & x"08" & StepGenTag & x"82",
IOPortTag & x"09" & StepGenTag & x"81",
IOPortTag & x"09" & StepGenTag & x"82",
IOPortTag & x"0A" & StepGenTag & x"81",
IOPortTag & x"0A" & StepGenTag & x"82",
IOPortTag & x"0B" & StepGenTag & x"81",
IOPortTag & x"0B" & StepGenTag & x"82",
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin);
-------------------------------------------------------------------------------------------------
-- 3 connector pinouts (4I65,5I20,4I68,5I23)
-------------------------------------------------------------------------------------------------
constant ModuleID_3xi30 : ModuleIDType :=(
(WatchDogTag, x"00", ClockLowTag, x"01", WatchDogTimeAddr&PadT, WatchDogNumRegs, x"00", WatchDogMPBitMask),
(IOPortTag, x"00", ClockLowTag, x"03", PortAddr&PadT, IOPortNumRegs, x"00", IOPortMPBitMask),
(QcountTag, x"02", ClockLowTag, x"0C", QcounterAddr&PadT, QCounterNumRegs, x"00", QCounterMPBitMask),
(PWMTag, x"00", ClockHighTag, x"0C", PWMValAddr&PadT, PWMNumRegs, x"00", PWMMPBitMask),
(LEDTag, x"00", ClockLowTag, x"01", LEDAddr&PadT, LEDNumRegs, x"00", LEDMPBitMask),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000")
);
constant PinDesc_3xi30 : PinDescType :=(
-- Base func sec unit sec func sec pin
IOPortTag & x"01" & QCountTag & x"02",
IOPortTag & x"01" & QCountTag & x"01",
IOPortTag & x"00" & QCountTag & x"02",
IOPortTag & x"00" & QCountTag & x"01",
IOPortTag & x"01" & QCountTag & x"03",
IOPortTag & x"00" & QCountTag & x"03",
IOPortTag & x"01" & PWMTag & x"81",
IOPortTag & x"00" & PWMTag & x"81",
IOPortTag & x"01" & PWMTag & x"82",
IOPortTag & x"00" & PWMTag & x"82",
IOPortTag & x"01" & PWMTag & x"83",
IOPortTag & x"00" & PWMTag & x"83",
IOPortTag & x"03" & QCountTag & x"02",
IOPortTag & x"03" & QCountTag & x"01",
IOPortTag & x"02" & QCountTag & x"02",
IOPortTag & x"02" & QCountTag & x"01",
IOPortTag & x"03" & QCountTag & x"03",
IOPortTag & x"02" & QCountTag & x"03",
IOPortTag & x"03" & PWMTag & x"81",
IOPortTag & x"02" & PWMTag & x"81",
IOPortTag & x"03" & PWMTag & x"82",
IOPortTag & x"02" & PWMTag & x"82",
IOPortTag & x"03" & PWMTag & x"83",
IOPortTag & x"02" & PWMTag & x"83",
IOPortTag & x"05" & QCountTag & x"02",
IOPortTag & x"05" & QCountTag & x"01",
IOPortTag & x"04" & QCountTag & x"02",
IOPortTag & x"04" & QCountTag & x"01",
IOPortTag & x"05" & QCountTag & x"03",
IOPortTag & x"04" & QCountTag & x"03",
IOPortTag & x"05" & PWMTag & x"81",
IOPortTag & x"04" & PWMTag & x"81",
IOPortTag & x"05" & PWMTag & x"82",
IOPortTag & x"04" & PWMTag & x"82",
IOPortTag & x"05" & PWMTag & x"83",
IOPortTag & x"04" & PWMTag & x"83",
IOPortTag & x"07" & QCountTag & x"02",
IOPortTag & x"07" & QCountTag & x"01",
IOPortTag & x"06" & QCountTag & x"02",
IOPortTag & x"06" & QCountTag & x"01",
IOPortTag & x"07" & QCountTag & x"03",
IOPortTag & x"06" & QCountTag & x"03",
IOPortTag & x"07" & PWMTag & x"81",
IOPortTag & x"06" & PWMTag & x"81",
IOPortTag & x"07" & PWMTag & x"82",
IOPortTag & x"06" & PWMTag & x"82",
IOPortTag & x"07" & PWMTag & x"83",
IOPortTag & x"06" & PWMTag & x"83",
IOPortTag & x"09" & QCountTag & x"02",
IOPortTag & x"09" & QCountTag & x"01",
IOPortTag & x"08" & QCountTag & x"02",
IOPortTag & x"08" & QCountTag & x"01",
IOPortTag & x"09" & QCountTag & x"03",
IOPortTag & x"08" & QCountTag & x"03",
IOPortTag & x"09" & PWMTag & x"81",
IOPortTag & x"08" & PWMTag & x"81",
IOPortTag & x"09" & PWMTag & x"82",
IOPortTag & x"08" & PWMTag & x"82",
IOPortTag & x"09" & PWMTag & x"83",
IOPortTag & x"08" & PWMTag & x"83",
IOPortTag & x"0B" & QCountTag & x"02",
IOPortTag & x"0B" & QCountTag & x"01",
IOPortTag & x"0A" & QCountTag & x"02",
IOPortTag & x"0A" & QCountTag & x"01",
IOPortTag & x"0B" & QCountTag & x"03",
IOPortTag & x"0A" & QCountTag & x"03",
IOPortTag & x"0B" & PWMTag & x"81",
IOPortTag & x"0A" & PWMTag & x"81",
IOPortTag & x"0B" & PWMTag & x"82",
IOPortTag & x"0A" & PWMTag & x"82",
IOPortTag & x"0B" & PWMTag & x"83",
IOPortTag & x"0A" & PWMTag & x"83",
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin);
constant ModuleID_SVST8_4 : ModuleIDType :=(
(WatchDogTag, x"00", ClockLowTag, x"01", WatchDogTimeAddr&PadT, WatchDogNumRegs, x"00", WatchDogMPBitMask),
(IOPortTag, x"00", ClockLowTag, x"03", PortAddr&PadT, IOPortNumRegs, x"00", IOPortMPBitMask),
(QcountTag, x"02", ClockLowTag, x"08", QcounterAddr&PadT, QCounterNumRegs, x"00", QCounterMPBitMask),
(PWMTag, x"00", ClockHighTag, x"08", PWMValAddr&PadT, PWMNumRegs, x"00", PWMMPBitMask),
(StepGenTag, x"01", ClockLowTag, x"04", StepGenRateAddr&PadT, StepGenNumRegs, x"00", StepGenMPBitMask),
(LEDTag, x"00", ClockLowTag, x"01", LEDAddr&PadT, LEDNumRegs, x"00", LEDMPBitMask),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000")
);
constant PinDesc_SVST8_4 : PinDescType :=(
-- Base func sec unit sec func sec pin
IOPortTag & x"01" & QCountTag & x"02",
IOPortTag & x"01" & QCountTag & x"01",
IOPortTag & x"00" & QCountTag & x"02",
IOPortTag & x"00" & QCountTag & x"01",
IOPortTag & x"01" & QCountTag & x"03",
IOPortTag & x"00" & QCountTag & x"03",
IOPortTag & x"01" & PWMTag & x"81",
IOPortTag & x"00" & PWMTag & x"81",
IOPortTag & x"01" & PWMTag & x"82",
IOPortTag & x"00" & PWMTag & x"82",
IOPortTag & x"01" & PWMTag & x"83",
IOPortTag & x"00" & PWMTag & x"83",
IOPortTag & x"03" & QCountTag & x"02",
IOPortTag & x"03" & QCountTag & x"01",
IOPortTag & x"02" & QCountTag & x"02",
IOPortTag & x"02" & QCountTag & x"01",
IOPortTag & x"03" & QCountTag & x"03",
IOPortTag & x"02" & QCountTag & x"03",
IOPortTag & x"03" & PWMTag & x"81",
IOPortTag & x"02" & PWMTag & x"81",
IOPortTag & x"03" & PWMTag & x"82",
IOPortTag & x"02" & PWMTag & x"82",
IOPortTag & x"03" & PWMTag & x"83",
IOPortTag & x"02" & PWMTag & x"83",
IOPortTag & x"05" & QCountTag & x"02",
IOPortTag & x"05" & QCountTag & x"01",
IOPortTag & x"04" & QCountTag & x"02",
IOPortTag & x"04" & QCountTag & x"01",
IOPortTag & x"05" & QCountTag & x"03",
IOPortTag & x"04" & QCountTag & x"03",
IOPortTag & x"05" & PWMTag & x"81",
IOPortTag & x"04" & PWMTag & x"81",
IOPortTag & x"05" & PWMTag & x"82",
IOPortTag & x"04" & PWMTag & x"82",
IOPortTag & x"05" & PWMTag & x"83",
IOPortTag & x"04" & PWMTag & x"83",
IOPortTag & x"07" & QCountTag & x"02",
IOPortTag & x"07" & QCountTag & x"01",
IOPortTag & x"06" & QCountTag & x"02",
IOPortTag & x"06" & QCountTag & x"01",
IOPortTag & x"07" & QCountTag & x"03",
IOPortTag & x"06" & QCountTag & x"03",
IOPortTag & x"07" & PWMTag & x"81",
IOPortTag & x"06" & PWMTag & x"81",
IOPortTag & x"07" & PWMTag & x"82",
IOPortTag & x"06" & PWMTag & x"82",
IOPortTag & x"07" & PWMTag & x"83",
IOPortTag & x"06" & PWMTag & x"83",
IOPortTag & x"00" & StepGenTag & x"81",
IOPortTag & x"00" & StepGenTag & x"82",
IOPortTag & x"00" & StepGenTag & x"83",
IOPortTag & x"00" & StepGenTag & x"84",
IOPortTag & x"00" & StepGenTag & x"85",
IOPortTag & x"00" & StepGenTag & x"86",
IOPortTag & x"01" & StepGenTag & x"81",
IOPortTag & x"01" & StepGenTag & x"82",
IOPortTag & x"01" & StepGenTag & x"83",
IOPortTag & x"01" & StepGenTag & x"84",
IOPortTag & x"01" & StepGenTag & x"85",
IOPortTag & x"01" & StepGenTag & x"86",
IOPortTag & x"02" & StepGenTag & x"81",
IOPortTag & x"02" & StepGenTag & x"82",
IOPortTag & x"02" & StepGenTag & x"83",
IOPortTag & x"02" & StepGenTag & x"84",
IOPortTag & x"02" & StepGenTag & x"85",
IOPortTag & x"02" & StepGenTag & x"86",
IOPortTag & x"03" & StepGenTag & x"81",
IOPortTag & x"03" & StepGenTag & x"82",
IOPortTag & x"03" & StepGenTag & x"83",
IOPortTag & x"03" & StepGenTag & x"84",
IOPortTag & x"03" & StepGenTag & x"85",
IOPortTag & x"03" & StepGenTag & x"86",
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin);
constant ModuleID_24xQCtrOnly : ModuleIDType :=(
(WatchDogTag, x"00", ClockLowTag, x"01", WatchDogTimeAddr&PadT, WatchDogNumRegs, x"00", WatchDogMPBitMask),
(IOPortTag, x"00", ClockLowTag, x"03", PortAddr&PadT, IOPortNumRegs, x"00", IOPortMPBitMask),
(QcountTag, x"02", ClockLowTag, x"10", QcounterAddr&PadT, QCounterNumRegs, x"00", QCounterMPBitMask),
(LEDTag, x"00", ClockLowTag, x"01", LEDAddr&PadT, LEDNumRegs, x"00", LEDMPBitMask),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000")
);
constant PinDesc_24xQCtrOnly : PinDescType :=(
-- Base func sec unit sec func sec pin
IOPortTag & x"00" & QCountTag & x"01",
IOPortTag & x"00" & QCountTag & x"02",
IOPortTag & x"00" & QCountTag & x"03",
IOPortTag & x"01" & QCountTag & x"01",
IOPortTag & x"01" & QCountTag & x"02",
IOPortTag & x"01" & QCountTag & x"03",
IOPortTag & x"02" & QCountTag & x"01",
IOPortTag & x"02" & QCountTag & x"02",
IOPortTag & x"02" & QCountTag & x"03",
IOPortTag & x"03" & QCountTag & x"01",
IOPortTag & x"03" & QCountTag & x"02",
IOPortTag & x"03" & QCountTag & x"03",
IOPortTag & x"04" & QCountTag & x"01",
IOPortTag & x"04" & QCountTag & x"02",
IOPortTag & x"04" & QCountTag & x"03",
IOPortTag & x"05" & QCountTag & x"01",
IOPortTag & x"05" & QCountTag & x"02",
IOPortTag & x"05" & QCountTag & x"03",
IOPortTag & x"06" & QCountTag & x"01",
IOPortTag & x"06" & QCountTag & x"02",
IOPortTag & x"06" & QCountTag & x"03",
IOPortTag & x"07" & QCountTag & x"01",
IOPortTag & x"07" & QCountTag & x"02",
IOPortTag & x"07" & QCountTag & x"03",
IOPortTag & x"08" & QCountTag & x"01",
IOPortTag & x"08" & QCountTag & x"02",
IOPortTag & x"08" & QCountTag & x"03",
IOPortTag & x"09" & QCountTag & x"01",
IOPortTag & x"09" & QCountTag & x"02",
IOPortTag & x"09" & QCountTag & x"03",
IOPortTag & x"0A" & QCountTag & x"01",
IOPortTag & x"0A" & QCountTag & x"02",
IOPortTag & x"0A" & QCountTag & x"03",
IOPortTag & x"0B" & QCountTag & x"01",
IOPortTag & x"0B" & QCountTag & x"02",
IOPortTag & x"0B" & QCountTag & x"03",
IOPortTag & x"0C" & QCountTag & x"01",
IOPortTag & x"0C" & QCountTag & x"02",
IOPortTag & x"0C" & QCountTag & x"03",
IOPortTag & x"0D" & QCountTag & x"01",
IOPortTag & x"0D" & QCountTag & x"02",
IOPortTag & x"0D" & QCountTag & x"03",
IOPortTag & x"0E" & QCountTag & x"01",
IOPortTag & x"0E" & QCountTag & x"02",
IOPortTag & x"0E" & QCountTag & x"03",
IOPortTag & x"0F" & QCountTag & x"01",
IOPortTag & x"0F" & QCountTag & x"02",
IOPortTag & x"0F" & QCountTag & x"03",
IOPortTag & x"10" & QCountTag & x"01",
IOPortTag & x"10" & QCountTag & x"02",
IOPortTag & x"10" & QCountTag & x"03",
IOPortTag & x"11" & QCountTag & x"01",
IOPortTag & x"11" & QCountTag & x"02",
IOPortTag & x"11" & QCountTag & x"03",
IOPortTag & x"12" & QCountTag & x"01",
IOPortTag & x"12" & QCountTag & x"02",
IOPortTag & x"12" & QCountTag & x"03",
IOPortTag & x"13" & QCountTag & x"01",
IOPortTag & x"13" & QCountTag & x"02",
IOPortTag & x"13" & QCountTag & x"03",
IOPortTag & x"14" & QCountTag & x"01",
IOPortTag & x"14" & QCountTag & x"02",
IOPortTag & x"14" & QCountTag & x"03",
IOPortTag & x"15" & QCountTag & x"01",
IOPortTag & x"15" & QCountTag & x"02",
IOPortTag & x"15" & QCountTag & x"03",
IOPortTag & x"16" & QCountTag & x"01",
IOPortTag & x"16" & QCountTag & x"02",
IOPortTag & x"16" & QCountTag & x"03",
IOPortTag & x"17" & QCountTag & x"01",
IOPortTag & x"17" & QCountTag & x"02",
IOPortTag & x"17" & QCountTag & x"03",
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin);
constant ModuleID_SVST4_8 : ModuleIDType :=(
(WatchDogTag, x"00", ClockLowTag, x"01", WatchDogTimeAddr&PadT, WatchDogNumRegs, x"00", WatchDogMPBitMask),
(IOPortTag, x"00", ClockLowTag, x"03", PortAddr&PadT, IOPortNumRegs, x"00", IOPortMPBitMask),
(QcountTag, x"02", ClockLowTag, x"04", QcounterAddr&PadT, QCounterNumRegs, x"00", QCounterMPBitMask),
(PWMTag, x"00", ClockHighTag, x"04", PWMValAddr&PadT, PWMNumRegs, x"00", PWMMPBitMask),
(StepGenTag, x"01", ClockLowTag, x"08", StepGenRateAddr&PadT, StepGenNumRegs, x"00", StepGenMPBitMask),
(LEDTag, x"00", ClockLowTag, x"01", LEDAddr&PadT, LEDNumRegs, x"00", LEDMPBitMask),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000")
);
constant PinDesc_SVST4_8 : PinDescType :=(
-- Base func sec unit sec func sec pin
IOPortTag & x"01" & QCountTag & x"02",
IOPortTag & x"01" & QCountTag & x"01",
IOPortTag & x"00" & QCountTag & x"02",
IOPortTag & x"00" & QCountTag & x"01",
IOPortTag & x"01" & QCountTag & x"03",
IOPortTag & x"00" & QCountTag & x"03",
IOPortTag & x"01" & PWMTag & x"81",
IOPortTag & x"00" & PWMTag & x"81",
IOPortTag & x"01" & PWMTag & x"82",
IOPortTag & x"00" & PWMTag & x"82",
IOPortTag & x"01" & PWMTag & x"83",
IOPortTag & x"00" & PWMTag & x"83",
IOPortTag & x"03" & QCountTag & x"02",
IOPortTag & x"03" & QCountTag & x"01",
IOPortTag & x"02" & QCountTag & x"02",
IOPortTag & x"02" & QCountTag & x"01",
IOPortTag & x"03" & QCountTag & x"03",
IOPortTag & x"02" & QCountTag & x"03",
IOPortTag & x"03" & PWMTag & x"81",
IOPortTag & x"02" & PWMTag & x"81",
IOPortTag & x"03" & PWMTag & x"82",
IOPortTag & x"02" & PWMTag & x"82",
IOPortTag & x"03" & PWMTag & x"83",
IOPortTag & x"02" & PWMTag & x"83",
IOPortTag & x"00" & StepGenTag & x"81",
IOPortTag & x"00" & StepGenTag & x"82",
IOPortTag & x"00" & StepGenTag & x"83",
IOPortTag & x"00" & StepGenTag & x"84",
IOPortTag & x"00" & StepGenTag & x"85",
IOPortTag & x"00" & StepGenTag & x"86",
IOPortTag & x"01" & StepGenTag & x"81",
IOPortTag & x"01" & StepGenTag & x"82",
IOPortTag & x"01" & StepGenTag & x"83",
IOPortTag & x"01" & StepGenTag & x"84",
IOPortTag & x"01" & StepGenTag & x"85",
IOPortTag & x"01" & StepGenTag & x"86",
IOPortTag & x"02" & StepGenTag & x"81",
IOPortTag & x"02" & StepGenTag & x"82",
IOPortTag & x"02" & StepGenTag & x"83",
IOPortTag & x"02" & StepGenTag & x"84",
IOPortTag & x"02" & StepGenTag & x"85",
IOPortTag & x"02" & StepGenTag & x"86",
IOPortTag & x"03" & StepGenTag & x"81",
IOPortTag & x"03" & StepGenTag & x"82",
IOPortTag & x"03" & StepGenTag & x"83",
IOPortTag & x"03" & StepGenTag & x"84",
IOPortTag & x"03" & StepGenTag & x"85",
IOPortTag & x"03" & StepGenTag & x"86",
IOPortTag & x"04" & StepGenTag & x"81",
IOPortTag & x"04" & StepGenTag & x"82",
IOPortTag & x"04" & StepGenTag & x"83",
IOPortTag & x"04" & StepGenTag & x"84",
IOPortTag & x"04" & StepGenTag & x"85",
IOPortTag & x"04" & StepGenTag & x"86",
IOPortTag & x"05" & StepGenTag & x"81",
IOPortTag & x"05" & StepGenTag & x"82",
IOPortTag & x"05" & StepGenTag & x"83",
IOPortTag & x"05" & StepGenTag & x"84",
IOPortTag & x"05" & StepGenTag & x"85",
IOPortTag & x"05" & StepGenTag & x"86",
IOPortTag & x"06" & StepGenTag & x"81",
IOPortTag & x"06" & StepGenTag & x"82",
IOPortTag & x"06" & StepGenTag & x"83",
IOPortTag & x"06" & StepGenTag & x"84",
IOPortTag & x"06" & StepGenTag & x"85",
IOPortTag & x"06" & StepGenTag & x"86",
IOPortTag & x"07" & StepGenTag & x"81",
IOPortTag & x"07" & StepGenTag & x"82",
IOPortTag & x"07" & StepGenTag & x"83",
IOPortTag & x"07" & StepGenTag & x"84",
IOPortTag & x"07" & StepGenTag & x"85",
IOPortTag & x"07" & StepGenTag & x"86",
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin);
constant ModuleID_SVST2_8 : ModuleIDType :=(
(WatchDogTag, x"00", ClockLowTag, x"01", WatchDogTimeAddr&PadT, WatchDogNumRegs, x"00", WatchDogMPBitMask),
(IOPortTag, x"00", ClockLowTag, x"03", PortAddr&PadT, IOPortNumRegs, x"00", IOPortMPBitMask),
(QcountTag, x"02", ClockLowTag, x"02", QcounterAddr&PadT, QCounterNumRegs, x"00", QCounterMPBitMask),
(PWMTag, x"00", ClockHighTag, x"02", PWMValAddr&PadT, PWMNumRegs, x"00", PWMMPBitMask),
(StepGenTag, x"01", ClockLowTag, x"08", StepGenRateAddr&PadT, StepGenNumRegs, x"00", StepGenMPBitMask),
(LEDTag, x"00", ClockLowTag, x"01", LEDAddr&PadT, LEDNumRegs, x"00", LEDMPBitMask),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000")
);
constant PinDesc_SVST2_8 : PinDescType :=(
-- Base func sec unit sec func sec pin
IOPortTag & x"01" & QCountTag & x"02",
IOPortTag & x"01" & QCountTag & x"01",
IOPortTag & x"00" & QCountTag & x"02",
IOPortTag & x"00" & QCountTag & x"01",
IOPortTag & x"01" & QCountTag & x"03",
IOPortTag & x"00" & QCountTag & x"03",
IOPortTag & x"01" & PWMTag & x"81",
IOPortTag & x"00" & PWMTag & x"81",
IOPortTag & x"01" & PWMTag & x"82",
IOPortTag & x"00" & PWMTag & x"82",
IOPortTag & x"01" & PWMTag & x"83",
IOPortTag & x"00" & PWMTag & x"83",
IOPortTag & x"00" & NullTag & x"00",
IOPortTag & x"00" & NullTag & x"00",
IOPortTag & x"00" & NullTag & x"00",
IOPortTag & x"00" & NullTag & x"00",
IOPortTag & x"00" & NullTag & x"00",
IOPortTag & x"00" & NullTag & x"00",
IOPortTag & x"00" & NullTag & x"00",
IOPortTag & x"00" & NullTag & x"00",
IOPortTag & x"00" & NullTag & x"00",
IOPortTag & x"00" & NullTag & x"00",
IOPortTag & x"00" & NullTag & x"00",
IOPortTag & x"00" & NullTag & x"00",
IOPortTag & x"00" & StepGenTag & x"81",
IOPortTag & x"00" & StepGenTag & x"82",
IOPortTag & x"00" & StepGenTag & x"83",
IOPortTag & x"00" & StepGenTag & x"84",
IOPortTag & x"00" & StepGenTag & x"85",
IOPortTag & x"00" & StepGenTag & x"86",
IOPortTag & x"01" & StepGenTag & x"81",
IOPortTag & x"01" & StepGenTag & x"82",
IOPortTag & x"01" & StepGenTag & x"83",
IOPortTag & x"01" & StepGenTag & x"84",
IOPortTag & x"01" & StepGenTag & x"85",
IOPortTag & x"01" & StepGenTag & x"86",
IOPortTag & x"02" & StepGenTag & x"81",
IOPortTag & x"02" & StepGenTag & x"82",
IOPortTag & x"02" & StepGenTag & x"83",
IOPortTag & x"02" & StepGenTag & x"84",
IOPortTag & x"02" & StepGenTag & x"85",
IOPortTag & x"02" & StepGenTag & x"86",
IOPortTag & x"03" & StepGenTag & x"81",
IOPortTag & x"03" & StepGenTag & x"82",
IOPortTag & x"03" & StepGenTag & x"83",
IOPortTag & x"03" & StepGenTag & x"84",
IOPortTag & x"03" & StepGenTag & x"85",
IOPortTag & x"03" & StepGenTag & x"86",
IOPortTag & x"04" & StepGenTag & x"81",
IOPortTag & x"04" & StepGenTag & x"82",
IOPortTag & x"04" & StepGenTag & x"83",
IOPortTag & x"04" & StepGenTag & x"84",
IOPortTag & x"04" & StepGenTag & x"85",
IOPortTag & x"04" & StepGenTag & x"86",
IOPortTag & x"05" & StepGenTag & x"81",
IOPortTag & x"05" & StepGenTag & x"82",
IOPortTag & x"05" & StepGenTag & x"83",
IOPortTag & x"05" & StepGenTag & x"84",
IOPortTag & x"05" & StepGenTag & x"85",
IOPortTag & x"05" & StepGenTag & x"86",
IOPortTag & x"06" & StepGenTag & x"81",
IOPortTag & x"06" & StepGenTag & x"82",
IOPortTag & x"06" & StepGenTag & x"83",
IOPortTag & x"06" & StepGenTag & x"84",
IOPortTag & x"06" & StepGenTag & x"85",
IOPortTag & x"06" & StepGenTag & x"86",
IOPortTag & x"07" & StepGenTag & x"81",
IOPortTag & x"07" & StepGenTag & x"82",
IOPortTag & x"07" & StepGenTag & x"83",
IOPortTag & x"07" & StepGenTag & x"84",
IOPortTag & x"07" & StepGenTag & x"85",
IOPortTag & x"07" & StepGenTag & x"86",
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin);
constant ModuleID_ST12 : ModuleIDType :=(
(WatchDogTag, x"00", ClockLowTag, x"01", WatchDogTimeAddr&PadT, WatchDogNumRegs, x"00", WatchDogMPBitMask),
(IOPortTag, x"00", ClockLowTag, x"03", PortAddr&PadT, IOPortNumRegs, x"00", IOPortMPBitMask),
(StepGenTag, x"01", ClockLowTag, x"0C", StepGenRateAddr&PadT, StepGenNumRegs, x"00", StepGenMPBitMask),
(LEDTag, x"00", ClockLowTag, x"01", LEDAddr&PadT, LEDNumRegs, x"00", LEDMPBitMask),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000")
);
constant PinDesc_ST12 : PinDescType :=(
-- Base func sec unit sec func sec pin
IOPortTag & x"00" & StepGenTag & x"81",
IOPortTag & x"00" & StepGenTag & x"82",
IOPortTag & x"00" & StepGenTag & x"83",
IOPortTag & x"00" & StepGenTag & x"84",
IOPortTag & x"00" & StepGenTag & x"85",
IOPortTag & x"00" & StepGenTag & x"86",
IOPortTag & x"01" & StepGenTag & x"81",
IOPortTag & x"01" & StepGenTag & x"82",
IOPortTag & x"01" & StepGenTag & x"83",
IOPortTag & x"01" & StepGenTag & x"84",
IOPortTag & x"01" & StepGenTag & x"85",
IOPortTag & x"01" & StepGenTag & x"86",
IOPortTag & x"02" & StepGenTag & x"81",
IOPortTag & x"02" & StepGenTag & x"82",
IOPortTag & x"02" & StepGenTag & x"83",
IOPortTag & x"02" & StepGenTag & x"84",
IOPortTag & x"02" & StepGenTag & x"85",
IOPortTag & x"02" & StepGenTag & x"86",
IOPortTag & x"03" & StepGenTag & x"81",
IOPortTag & x"03" & StepGenTag & x"82",
IOPortTag & x"03" & StepGenTag & x"83",
IOPortTag & x"03" & StepGenTag & x"84",
IOPortTag & x"03" & StepGenTag & x"85",
IOPortTag & x"03" & StepGenTag & x"86",
IOPortTag & x"04" & StepGenTag & x"81",
IOPortTag & x"04" & StepGenTag & x"82",
IOPortTag & x"04" & StepGenTag & x"83",
IOPortTag & x"04" & StepGenTag & x"84",
IOPortTag & x"04" & StepGenTag & x"85",
IOPortTag & x"04" & StepGenTag & x"86",
IOPortTag & x"05" & StepGenTag & x"81",
IOPortTag & x"05" & StepGenTag & x"82",
IOPortTag & x"05" & StepGenTag & x"83",
IOPortTag & x"05" & StepGenTag & x"84",
IOPortTag & x"05" & StepGenTag & x"85",
IOPortTag & x"05" & StepGenTag & x"86",
IOPortTag & x"06" & StepGenTag & x"81",
IOPortTag & x"06" & StepGenTag & x"82",
IOPortTag & x"06" & StepGenTag & x"83",
IOPortTag & x"06" & StepGenTag & x"84",
IOPortTag & x"06" & StepGenTag & x"85",
IOPortTag & x"06" & StepGenTag & x"86",
IOPortTag & x"07" & StepGenTag & x"81",
IOPortTag & x"07" & StepGenTag & x"82",
IOPortTag & x"07" & StepGenTag & x"83",
IOPortTag & x"07" & StepGenTag & x"84",
IOPortTag & x"07" & StepGenTag & x"85",
IOPortTag & x"07" & StepGenTag & x"86",
IOPortTag & x"08" & StepGenTag & x"81",
IOPortTag & x"08" & StepGenTag & x"82",
IOPortTag & x"08" & StepGenTag & x"83",
IOPortTag & x"08" & StepGenTag & x"84",
IOPortTag & x"08" & StepGenTag & x"85",
IOPortTag & x"08" & StepGenTag & x"86",
IOPortTag & x"09" & StepGenTag & x"81",
IOPortTag & x"09" & StepGenTag & x"82",
IOPortTag & x"09" & StepGenTag & x"83",
IOPortTag & x"09" & StepGenTag & x"84",
IOPortTag & x"09" & StepGenTag & x"85",
IOPortTag & x"09" & StepGenTag & x"86",
IOPortTag & x"0A" & StepGenTag & x"81",
IOPortTag & x"0A" & StepGenTag & x"82",
IOPortTag & x"0A" & StepGenTag & x"83",
IOPortTag & x"0A" & StepGenTag & x"84",
IOPortTag & x"0A" & StepGenTag & x"85",
IOPortTag & x"0A" & StepGenTag & x"86",
IOPortTag & x"0B" & StepGenTag & x"81",
IOPortTag & x"0B" & StepGenTag & x"82",
IOPortTag & x"0B" & StepGenTag & x"83",
IOPortTag & x"0B" & StepGenTag & x"84",
IOPortTag & x"0B" & StepGenTag & x"85",
IOPortTag & x"0B" & StepGenTag & x"86",
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin);
constant ModuleID_DelftSV12 : ModuleIDType :=(
(WatchDogTag, x"00", ClockLowTag, x"01", WatchDogTimeAddr&PadT, WatchDogNumRegs, x"00", WatchDogMPBitMask),
(IOPortTag, x"00", ClockLowTag, x"03", PortAddr&PadT, IOPortNumRegs, x"00", IOPortMPBitMask),
(QcountTag, x"02", ClockLowTag, x"0C", QcounterAddr&PadT, QCounterNumRegs, x"00", QCounterMPBitMask),
(PWMTag, x"00", ClockHighTag, x"0C", PWMValAddr&PadT, PWMNumRegs, x"00", PWMMPBitMask),
(LEDTag, x"00", ClockLowTag, x"01", LEDAddr&PadT, LEDNumRegs, x"00", LEDMPBitMask),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000")
);
constant PinDesc_DelftSV12 : PinDescType :=(
-- Base func sec unit sec func sec pin
IOPortTag & x"00" & QCountTag & x"01",
IOPortTag & x"00" & QCountTag & x"02",
IOPortTag & x"00" & QCountTag & x"03",
IOPortTag & x"01" & QCountTag & x"01",
IOPortTag & x"01" & QCountTag & x"02",
IOPortTag & x"01" & QCountTag & x"03",
IOPortTag & x"02" & QCountTag & x"01",
IOPortTag & x"02" & QCountTag & x"02",
IOPortTag & x"02" & QCountTag & x"03",
IOPortTag & x"03" & QCountTag & x"01",
IOPortTag & x"03" & QCountTag & x"02",
IOPortTag & x"03" & QCountTag & x"03",
IOPortTag & x"04" & QCountTag & x"01",
IOPortTag & x"04" & QCountTag & x"02",
IOPortTag & x"04" & QCountTag & x"03",
IOPortTag & x"05" & QCountTag & x"01",
IOPortTag & x"05" & QCountTag & x"02",
IOPortTag & x"05" & QCountTag & x"03",
IOPortTag & x"00" & PWMTag & x"81",
IOPortTag & x"00" & PWMTag & x"82",
IOPortTag & x"00" & PWMTag & x"83",
IOPortTag & x"01" & PWMTag & x"81",
IOPortTag & x"01" & PWMTag & x"82",
IOPortTag & x"01" & PWMTag & x"83",
IOPortTag & x"06" & QCountTag & x"01",
IOPortTag & x"06" & QCountTag & x"02",
IOPortTag & x"06" & QCountTag & x"03",
IOPortTag & x"07" & QCountTag & x"01",
IOPortTag & x"07" & QCountTag & x"02",
IOPortTag & x"07" & QCountTag & x"03",
IOPortTag & x"08" & QCountTag & x"01",
IOPortTag & x"08" & QCountTag & x"02",
IOPortTag & x"08" & QCountTag & x"03",
IOPortTag & x"09" & QCountTag & x"01",
IOPortTag & x"09" & QCountTag & x"02",
IOPortTag & x"09" & QCountTag & x"03",
IOPortTag & x"0A" & QCountTag & x"01",
IOPortTag & x"0A" & QCountTag & x"02",
IOPortTag & x"0A" & QCountTag & x"03",
IOPortTag & x"0B" & QCountTag & x"01",
IOPortTag & x"0B" & QCountTag & x"02",
IOPortTag & x"0B" & QCountTag & x"03",
IOPortTag & x"06" & PWMTag & x"81",
IOPortTag & x"06" & PWMTag & x"82",
IOPortTag & x"06" & PWMTag & x"83",
IOPortTag & x"07" & PWMTag & x"81",
IOPortTag & x"07" & PWMTag & x"82",
IOPortTag & x"07" & PWMTag & x"83",
IOPortTag & x"02" & PWMTag & x"81",
IOPortTag & x"02" & PWMTag & x"82",
IOPortTag & x"02" & PWMTag & x"83",
IOPortTag & x"03" & PWMTag & x"81",
IOPortTag & x"03" & PWMTag & x"82",
IOPortTag & x"03" & PWMTag & x"83",
IOPortTag & x"04" & PWMTag & x"81",
IOPortTag & x"04" & PWMTag & x"82",
IOPortTag & x"04" & PWMTag & x"83",
IOPortTag & x"05" & PWMTag & x"81",
IOPortTag & x"05" & PWMTag & x"82",
IOPortTag & x"05" & PWMTag & x"83",
IOPortTag & x"08" & PWMTag & x"81",
IOPortTag & x"08" & PWMTag & x"82",
IOPortTag & x"08" & PWMTag & x"83",
IOPortTag & x"09" & PWMTag & x"81",
IOPortTag & x"09" & PWMTag & x"82",
IOPortTag & x"09" & PWMTag & x"83",
IOPortTag & x"0A" & PWMTag & x"81",
IOPortTag & x"0A" & PWMTag & x"82",
IOPortTag & x"0A" & PWMTag & x"83",
IOPortTag & x"0B" & PWMTag & x"81",
IOPortTag & x"0B" & PWMTag & x"82",
IOPortTag & x"0B" & PWMTag & x"83",
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin);
constant ModuleID_MShaver : ModuleIDType :=(
(WatchDogTag, x"00", ClockLowTag, x"01", WatchDogTimeAddr&PadT, WatchDogNumRegs, x"00", WatchDogMPBitMask),
(IOPortTag, x"00", ClockLowTag, x"03", PortAddr&PadT, IOPortNumRegs, x"00", IOPortMPBitMask),
(QcountTag, x"02", ClockLowTag, x"03", QcounterAddr&PadT, QCounterNumRegs, x"00", QCounterMPBitMask),
(PWMTag, x"00", ClockHighTag, x"01", PWMValAddr&PadT, PWMNumRegs, x"00", PWMMPBitMask),
(StepGenTag, x"00", ClockLowTag, x"03", StepGenRateAddr&PadT, StepGenNumRegs, x"00", StepGenMPBitMask),
(LEDTag, x"00", ClockLowTag, x"01", LEDAddr&PadT, LEDNumRegs, x"00", LEDMPBitMask),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000")
);
constant PinDesc_MShaver : PinDescType :=(
-- Base func sec unit sec func sec pin
IOPortTag & x"00" & QCountTag & QCountQAPin, -- I/O 00
IOPortTag & x"00" & QCountTag & QCountQBPin, -- I/O 01
IOPortTag & x"00" & QCountTag & QCountIDXPin, -- I/O 02
IOPortTag & x"01" & QCountTag & QCountQAPin, -- I/O 03
IOPortTag & x"00" & StepGenTag & StepGenStepPin, -- I/O 04
IOPortTag & x"00" & NullTag & x"00", -- I/O 05
IOPortTag & x"00" & StepGenTag & StepGenDirPin, -- I/O 06
IOPortTag & x"00" & NullTag & x"00", -- I/O 07
IOPortTag & x"01" & StepGenTag & StepGenStepPin, -- I/O 08
IOPortTag & x"00" & NullTag & x"00", -- I/O 09
IOPortTag & x"01" & StepGenTag & StepGenDirPin, -- I/O 10
IOPortTag & x"00" & NullTag & x"00", -- I/O 11
IOPortTag & x"01" & QCountTag & QCountQBPin, -- I/O 12
IOPortTag & x"02" & QCountTag & QCountQAPin, -- I/O 13
IOPortTag & x"02" & QCountTag & QCountQBPin, -- I/O 14
IOPortTag & x"00" & NullTag & x"00", -- I/O 15
IOPortTag & x"02" & StepGenTag & StepGenStepPin, -- I/O 16
IOPortTag & x"00" & NullTag & x"00", -- I/O 17
IOPortTag & x"02" & StepGenTag & StepGenDirPin, -- I/O 18
IOPortTag & x"00" & NullTag & x"00", -- I/O 19
IOPortTag & x"00" & PWMTag & PWMAOutPin, -- I/O 20
IOPortTag & x"00" & NullTag & x"00", -- I/O 21
IOPortTag & x"00" & NullTag & x"00", -- I/O 22
IOPortTag & x"00" & NullTag & x"00", -- I/O 23
IOPortTag & x"00" & NullTag & x"00", -- I/O 24
IOPortTag & x"00" & NullTag & x"00", -- I/O 25
IOPortTag & x"00" & NullTag & x"00", -- I/O 26
IOPortTag & x"00" & NullTag & x"00", -- I/O 27
IOPortTag & x"00" & NullTag & x"00", -- I/O 28
IOPortTag & x"00" & NullTag & x"00", -- I/O 29
IOPortTag & x"00" & NullTag & x"00", -- I/O 30
IOPortTag & x"00" & NullTag & x"00", -- I/O 31
IOPortTag & x"00" & NullTag & x"00", -- I/O 32
IOPortTag & x"00" & NullTag & x"00", -- I/O 33
IOPortTag & x"00" & NullTag & x"00", -- I/O 34
IOPortTag & x"00" & NullTag & x"00", -- I/O 35
IOPortTag & x"00" & NullTag & x"00", -- I/O 36
IOPortTag & x"00" & NullTag & x"00", -- I/O 37
IOPortTag & x"00" & NullTag & x"00", -- I/O 38
IOPortTag & x"00" & NullTag & x"00", -- I/O 39
IOPortTag & x"00" & NullTag & x"00", -- I/O 40
IOPortTag & x"00" & NullTag & x"00", -- I/O 41
IOPortTag & x"00" & NullTag & x"00", -- I/O 42
IOPortTag & x"00" & NullTag & x"00", -- I/O 43
IOPortTag & x"00" & NullTag & x"00", -- I/O 44
IOPortTag & x"00" & NullTag & x"00", -- I/O 45
IOPortTag & x"00" & NullTag & x"00", -- I/O 46
IOPortTag & x"00" & NullTag & x"00", -- I/O 47
IOPortTag & x"00" & NullTag & x"00", -- I/O 48
IOPortTag & x"00" & NullTag & x"00", -- I/O 49
IOPortTag & x"00" & NullTag & x"00", -- I/O 50
IOPortTag & x"00" & NullTag & x"00", -- I/O 51
IOPortTag & x"00" & NullTag & x"00", -- I/O 52
IOPortTag & x"00" & NullTag & x"00", -- I/O 53
IOPortTag & x"00" & NullTag & x"00", -- I/O 54
IOPortTag & x"00" & NullTag & x"00", -- I/O 55
IOPortTag & x"00" & NullTag & x"00", -- I/O 56
IOPortTag & x"00" & NullTag & x"00", -- I/O 57
IOPortTag & x"00" & NullTag & x"00", -- I/O 58
IOPortTag & x"00" & NullTag & x"00", -- I/O 59
IOPortTag & x"00" & NullTag & x"00", -- I/O 60
IOPortTag & x"00" & NullTag & x"00", -- I/O 61
IOPortTag & x"00" & NullTag & x"00", -- I/O 62
IOPortTag & x"00" & NullTag & x"00", -- I/O 63
IOPortTag & x"00" & NullTag & x"00", -- I/O 64
IOPortTag & x"00" & NullTag & x"00", -- I/O 65
IOPortTag & x"00" & NullTag & x"00", -- I/O 66
IOPortTag & x"00" & NullTag & x"00", -- I/O 67
IOPortTag & x"00" & NullTag & x"00", -- I/O 68
IOPortTag & x"00" & NullTag & x"00", -- I/O 69
IOPortTag & x"00" & NullTag & x"00", -- I/O 70
IOPortTag & x"00" & NullTag & x"00", -- I/O 71
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin);
constant ModuleID_72Pin_2x7I65 : ModuleIDType :=(
(WatchDogTag, x"00", ClockLowTag, x"01", WatchDogTimeAddr&PadT, WatchDogNumRegs, x"00", WatchDogMPBitMask),
(IOPortTag, x"00", ClockLowTag, x"03", PortAddr&PadT, IOPortNumRegs, x"00", IOPortMPBitMask),
(MuxedQcountTag, x"02", ClockLowTag, x"10", QcounterAddr&PadT, MuxedQCounterNumRegs, x"00", MuxedQCounterMPBitMask),
(MuxedQCountSelTag, x"00", ClockLowTag, x"01", NullAddr&PadT, x"00", x"00", x"00000000"),
(BSPITag, x"00", ClockLowTag, x"02", BSPIDataAddr&PadT, BSPINumRegs, x"00", BSPIMPBitMask),
(LEDTag, x"00", ClockLowTag, x"01", LEDAddr&PadT, LEDNumRegs, x"00", LEDMPBitMask),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000")
);
constant PinDesc_72Pin_2x7I65 : PinDescType :=(
-- Base func sec unit sec func sec pin
IOPortTag & x"00" & MuxedQCountTag & MuxedQCountQAPin, -- I/O 00
IOPortTag & x"00" & MuxedQCountTag & MuxedQCountQBPin, -- I/O 01
IOPortTag & x"00" & MuxedQCountTag & MuxedQCountIDXPin, -- I/O 02
IOPortTag & x"01" & MuxedQCountTag & MuxedQCountQAPin, -- I/O 03
IOPortTag & x"01" & MuxedQCountTag & MuxedQCountQBPin, -- I/O 04
IOPortTag & x"01" & MuxedQCountTag & MuxedQCountIDXPin, -- I/O 05
IOPortTag & x"02" & MuxedQCountTag & MuxedQCountQAPin, -- I/O 06
IOPortTag & x"02" & MuxedQCountTag & MuxedQCountQBPin, -- I/O 07
IOPortTag & x"02" & MuxedQCountTag & MuxedQCountIDXPin, -- I/O 08
IOPortTag & x"03" & MuxedQCountTag & MuxedQCountQAPin, -- I/O 09
IOPortTag & x"03" & MuxedQCountTag & MuxedQCountQBPin, -- I/O 10
IOPortTag & x"03" & MuxedQCountTag & MuxedQCountIDXPin, -- I/O 11
IOPortTag & x"00" & NullTag & x"00", -- I/O 12
IOPortTag & x"00" & MuxedQCountSelTag & MuxedQCountSel0Pin, -- I/O 37
IOPortTag & x"00" & BSPITag & BSPIFramePin, -- I/O 14
IOPortTag & x"00" & BSPITag & BSPIOutPin, -- I/O 15
IOPortTag & x"00" & BSPITag & BSPIClkPin, -- I/O 16
IOPortTag & x"00" & BSPITag & BSPIInPin, -- I/O 17
IOPortTag & x"00" & BSPITag & BSPICS2Pin, -- I/O 18
IOPortTag & x"00" & BSPITag & BSPICS1Pin, -- I/O 19
IOPortTag & x"00" & BSPITag & BSPICS0Pin, -- I/O 20
IOPortTag & x"00" & NullTag & x"00", -- I/O 21
IOPortTag & x"00" & NullTag & x"00", -- I/O 22
IOPortTag & x"00" & NullTag & x"00", -- I/O 23
IOPortTag & x"04" & MuxedQCountTag & MuxedQCountQAPin, -- I/O 24
IOPortTag & x"04" & MuxedQCountTag & MuxedQCountQBPin, -- I/O 25
IOPortTag & x"04" & MuxedQCountTag & MuxedQCountIDXPin, -- I/O 26
IOPortTag & x"05" & MuxedQCountTag & MuxedQCountQAPin, -- I/O 27
IOPortTag & x"05" & MuxedQCountTag & MuxedQCountQBPin, -- I/O 28
IOPortTag & x"05" & MuxedQCountTag & MuxedQCountIDXPin, -- I/O 29
IOPortTag & x"06" & MuxedQCountTag & MuxedQCountQAPin, -- I/O 30
IOPortTag & x"06" & MuxedQCountTag & MuxedQCountQBPin, -- I/O 31
IOPortTag & x"06" & MuxedQCountTag & MuxedQCountIDXPin, -- I/O 32
IOPortTag & x"07" & MuxedQCountTag & MuxedQCountQAPin, -- I/O 33
IOPortTag & x"07" & MuxedQCountTag & MuxedQCountQBPin, -- I/O 34
IOPortTag & x"07" & MuxedQCountTag & MuxedQCountIDXPin, -- I/O 35
IOPortTag & x"00" & NullTag & x"00", -- I/O 36
IOPortTag & x"00" & MuxedQCountSelTag & MuxedQCountSel0Pin, -- I/O 37
IOPortTag & x"01" & BSPITag & BSPIFramePin, -- I/O 38
IOPortTag & x"01" & BSPITag & BSPIOutPin, -- I/O 39
IOPortTag & x"01" & BSPITag & BSPIClkPin, -- I/O 40
IOPortTag & x"01" & BSPITag & BSPIInPin, -- I/O 41
IOPortTag & x"01" & BSPITag & BSPICS2Pin, -- I/O 42
IOPortTag & x"01" & BSPITag & BSPICS1Pin, -- I/O 43
IOPortTag & x"01" & BSPITag & BSPICS0Pin, -- I/O 44
IOPortTag & x"00" & NullTag & x"00", -- I/O 45
IOPortTag & x"00" & NullTag & x"00", -- I/O 46
IOPortTag & x"00" & NullTag & x"00", -- I/O 47
IOPortTag & x"00" & NullTag & x"00", -- I/O 48
IOPortTag & x"00" & NullTag & x"00", -- I/O 49
IOPortTag & x"00" & NullTag & x"00", -- I/O 50
IOPortTag & x"00" & NullTag & x"00", -- I/O 51
IOPortTag & x"00" & NullTag & x"00", -- I/O 52
IOPortTag & x"00" & NullTag & x"00", -- I/O 53
IOPortTag & x"00" & NullTag & x"00", -- I/O 54
IOPortTag & x"00" & NullTag & x"00", -- I/O 55
IOPortTag & x"00" & NullTag & x"00", -- I/O 56
IOPortTag & x"00" & NullTag & x"00", -- I/O 57
IOPortTag & x"00" & NullTag & x"00", -- I/O 58
IOPortTag & x"00" & NullTag & x"00", -- I/O 59
IOPortTag & x"00" & NullTag & x"00", -- I/O 60
IOPortTag & x"00" & NullTag & x"00", -- I/O 61
IOPortTag & x"00" & NullTag & x"00", -- I/O 62
IOPortTag & x"00" & NullTag & x"00", -- I/O 63
IOPortTag & x"00" & NullTag & x"00", -- I/O 64
IOPortTag & x"00" & NullTag & x"00", -- I/O 65
IOPortTag & x"00" & NullTag & x"00", -- I/O 66
IOPortTag & x"00" & NullTag & x"00", -- I/O 67
IOPortTag & x"00" & NullTag & x"00", -- I/O 68
IOPortTag & x"00" & NullTag & x"00", -- I/O 69
IOPortTag & x"00" & NullTag & x"00", -- I/O 70
IOPortTag & x"00" & NullTag & x"00", -- I/O 71
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin);
constant ModuleID_SVST8_4IM2 : ModuleIDType :=(
(WatchDogTag, x"00", ClockLowTag, x"01", WatchDogTimeAddr&PadT, WatchDogNumRegs, x"00", WatchDogMPBitMask),
(IOPortTag, x"00", ClockLowTag, x"03", PortAddr&PadT, IOPortNumRegs, x"00", IOPortMPBitMask),
(QcountTag, x"02", ClockLowTag, x"08", QcounterAddr&PadT, QCounterNumRegs, x"00", QCounterMPBitMask),
(PWMTag, x"00", ClockHighTag, x"08", PWMValAddr&PadT, PWMNumRegs, x"00", PWMMPBitMask),
(StepGenTag, x"01", ClockLowTag, x"04", StepGenRateAddr&PadT, StepGenNumRegs, x"00", StepGenMPBitMask),
(LEDTag, x"00", ClockLowTag, x"01", LEDAddr&PadT, LEDNumRegs, x"00", LEDMPBitMask),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000")
);
constant PinDesc_SVST8_4IM2 : PinDescType :=(
-- Base func sec unit sec func sec pin
IOPortTag & x"01" & QCountTag & QCountQBPin, -- I/O 00
IOPortTag & x"01" & QCountTag & QCountQAPin, -- I/O 01
IOPortTag & x"00" & QCountTag & QCountQBPin, -- I/O 02
IOPortTag & x"00" & QCountTag & QCountQAPin, -- I/O 03
IOPortTag & x"01" & QCountTag & QCountIDXPin, -- I/O 04
IOPortTag & x"00" & QCountTag & QCountIDXPin, -- I/O 05
IOPortTag & x"01" & PWMTag & PWMAOutPin, -- I/O 06
IOPortTag & x"00" & PWMTag & PWMAOutPin, -- I/O 07
IOPortTag & x"01" & PWMTag & PWMBDirPin, -- I/O 08
IOPortTag & x"00" & PWMTag & PWMBDirPin, -- I/O 09
IOPortTag & x"01" & PWMTag & PWMCEnaPin, -- I/O 10
IOPortTag & x"00" & PWMTag & PWMCEnaPin, -- I/O 11
IOPortTag & x"03" & QCountTag & QCountQBPin, -- I/O 12
IOPortTag & x"03" & QCountTag & QCountQAPin, -- I/O 37
IOPortTag & x"02" & QCountTag & QCountQBPin, -- I/O 14
IOPortTag & x"02" & QCountTag & QCountQAPin, -- I/O 15
IOPortTag & x"03" & QCountTag & QCountIDXPin, -- I/O 16
IOPortTag & x"02" & QCountTag & QCountIDXPin, -- I/O 17
IOPortTag & x"03" & PWMTag & PWMAOutPin, -- I/O 18
IOPortTag & x"02" & PWMTag & PWMAOutPin, -- I/O 19
IOPortTag & x"03" & PWMTag & PWMBDirPin, -- I/O 20
IOPortTag & x"02" & PWMTag & PWMBDirPin, -- I/O 21
IOPortTag & x"03" & PWMTag & PWMCEnaPin, -- I/O 22
IOPortTag & x"02" & PWMTag & PWMCenaPin, -- I/O 23
IOPortTag & x"05" & QCountTag & QCountQBPin, -- I/O 24
IOPortTag & x"05" & QCountTag & QCountQAPin, -- I/O 25
IOPortTag & x"04" & QCountTag & QCountQBPin, -- I/O 26
IOPortTag & x"04" & QCountTag & QCountQAPin, -- I/O 27
IOPortTag & x"05" & QCountTag & QCountIDXPin, -- I/O 28
IOPortTag & x"04" & QCountTag & QCountIDXPin, -- I/O 29
IOPortTag & x"05" & PWMTag & PWMAOutPin, -- I/O 30
IOPortTag & x"04" & PWMTag & PWMAOutPin, -- I/O 31
IOPortTag & x"05" & PWMTag & PWMBDirPin, -- I/O 32
IOPortTag & x"04" & PWMTag & PWMBDirPin, -- I/O 33
IOPortTag & x"05" & PWMTag & PWMCEnaPin, -- I/O 34
IOPortTag & x"04" & PWMTag & PWMCEnaPin, -- I/O 35
IOPortTag & x"07" & QCountTag & QCountQBPin, -- I/O 36
IOPortTag & x"07" & QCountTag & QCountQAPin, -- I/O 37
IOPortTag & x"06" & QCountTag & QCountQBPin, -- I/O 38
IOPortTag & x"06" & QCountTag & QCountQAPin, -- I/O 39
IOPortTag & x"07" & QCountTag & QCountIDXPin, -- I/O 40
IOPortTag & x"06" & QCountTag & QCountIDXPin, -- I/O 41
IOPortTag & x"07" & PWMTag & PWMAOutPin, -- I/O 42
IOPortTag & x"06" & PWMTag & PWMAOutPin, -- I/O 43
IOPortTag & x"07" & PWMTag & PWMBDirPin, -- I/O 44
IOPortTag & x"06" & PWMTag & PWMBDirPin, -- I/O 45
IOPortTag & x"07" & PWMTag & PWMCEnaPin, -- I/O 46
IOPortTag & x"06" & PWMTag & PWMCEnaPin, -- I/O 47
IOPortTag & x"00" & QCountTag & QCountIdxMaskPin, -- I/O 48
IOPortTag & x"01" & QCountTag & QCountIdxMaskPin, -- I/O 49
IOPortTag & x"02" & QCountTag & QCountIdxMaskPin, -- I/O 50
IOPortTag & x"03" & QCountTag & QCountIdxMaskPin, -- I/O 51
IOPortTag & x"04" & QCountTag & QCountIdxMaskPin, -- I/O 52
IOPortTag & x"05" & QCountTag & QCountIdxMaskPin, -- I/O 53
IOPortTag & x"06" & QCountTag & QCountIdxMaskPin, -- I/O 54
IOPortTag & x"07" & QCountTag & QCountIdxMaskPin, -- I/O 55
IOPortTag & x"00" & NullTag & x"00", -- I/O 56
IOPortTag & x"00" & NullTag & x"00", -- I/O 57
IOPortTag & x"00" & NullTag & x"00", -- I/O 58
IOPortTag & x"00" & NullTag & x"00", -- I/O 59
IOPortTag & x"00" & NullTag & x"00", -- I/O 60
IOPortTag & x"00" & NullTag & x"00", -- I/O 61
IOPortTag & x"00" & NullTag & x"00", -- I/O 62
IOPortTag & x"00" & NullTag & x"00", -- I/O 63
IOPortTag & x"00" & StepGenTag & StepGenStepPin, -- I/O 64
IOPortTag & x"00" & StepGenTag & StepGenDirPin, -- I/O 65
IOPortTag & x"01" & StepGenTag & StepGenStepPin, -- I/O 66
IOPortTag & x"01" & StepGenTag & StepGenDirPin, -- I/O 67
IOPortTag & x"02" & StepGenTag & StepGenStepPin, -- I/O 68
IOPortTag & x"02" & StepGenTag & StepGenDirPin, -- I/O 69
IOPortTag & x"03" & StepGenTag & StepGenStepPin, -- I/O 70
IOPortTag & x"03" & StepGenTag & StepGenDirPin, -- I/O 71
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin);
constant ModuleID_SVUA8_4 : ModuleIDType :=(
(WatchDogTag, x"00", ClockLowTag, x"01", WatchDogTimeAddr&PadT, WatchDogNumRegs, x"00", WatchDogMPBitMask),
(IOPortTag, x"00", ClockLowTag, x"03", PortAddr&PadT, IOPortNumRegs, x"00", IOPortMPBitMask),
(QcountTag, x"02", ClockLowTag, x"08", QcounterAddr&PadT, QCounterNumRegs, x"00", QCounterMPBitMask),
(PWMTag, x"00", ClockHighTag, x"08", PWMValAddr&PadT, PWMNumRegs, x"00", PWMMPBitMask),
(UARTTTag, x"00", ClockLowTag, x"04", UARTTDataAddr&PadT, UARTTNumRegs, x"00", UARTTMPBitMask),
(UARTRTag, x"00", ClockLowTag, x"04", UARTRDataAddr&PadT, UARTRNumRegs, x"00", UARTRMPBitMask),
(LEDTag, x"00", ClockLowTag, x"01", LEDAddr&PadT, LEDNumRegs, x"00", LEDMPBitMask),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000")
);
constant PinDesc_SVUA8_4 : PinDescType :=(
-- Base func sec unit sec func sec pin
IOPortTag & x"01" & QCountTag & QCountQBPin, -- I/O 00
IOPortTag & x"01" & QCountTag & QCountQAPin, -- I/O 01
IOPortTag & x"00" & QCountTag & QCountQBPin, -- I/O 02
IOPortTag & x"00" & QCountTag & QCountQAPin, -- I/O 03
IOPortTag & x"01" & QCountTag & QCountIDXPin, -- I/O 04
IOPortTag & x"00" & QCountTag & QCountIDXPin, -- I/O 05
IOPortTag & x"01" & PWMTag & PWMAOutPin, -- I/O 06
IOPortTag & x"00" & PWMTag & PWMAOutPin, -- I/O 07
IOPortTag & x"01" & PWMTag & PWMBDirPin, -- I/O 08
IOPortTag & x"00" & PWMTag & PWMBDirPin, -- I/O 09
IOPortTag & x"01" & PWMTag & PWMCEnaPin, -- I/O 10
IOPortTag & x"00" & PWMTag & PWMCEnaPin, -- I/O 11
IOPortTag & x"03" & QCountTag & QCountQBPin, -- I/O 12
IOPortTag & x"03" & QCountTag & QCountQAPin, -- I/O 37
IOPortTag & x"02" & QCountTag & QCountQBPin, -- I/O 14
IOPortTag & x"02" & QCountTag & QCountQAPin, -- I/O 15
IOPortTag & x"03" & QCountTag & QCountIDXPin, -- I/O 16
IOPortTag & x"02" & QCountTag & QCountIDXPin, -- I/O 17
IOPortTag & x"03" & PWMTag & PWMAOutPin, -- I/O 18
IOPortTag & x"02" & PWMTag & PWMAOutPin, -- I/O 19
IOPortTag & x"03" & PWMTag & PWMBDirPin, -- I/O 20
IOPortTag & x"02" & PWMTag & PWMBDirPin, -- I/O 21
IOPortTag & x"03" & PWMTag & PWMCEnaPin, -- I/O 22
IOPortTag & x"02" & PWMTag & PWMCenaPin, -- I/O 23
IOPortTag & x"05" & QCountTag & QCountQBPin, -- I/O 24
IOPortTag & x"05" & QCountTag & QCountQAPin, -- I/O 25
IOPortTag & x"04" & QCountTag & QCountQBPin, -- I/O 26
IOPortTag & x"04" & QCountTag & QCountQAPin, -- I/O 27
IOPortTag & x"05" & QCountTag & QCountIDXPin, -- I/O 28
IOPortTag & x"04" & QCountTag & QCountIDXPin, -- I/O 29
IOPortTag & x"05" & PWMTag & PWMAOutPin, -- I/O 30
IOPortTag & x"04" & PWMTag & PWMAOutPin, -- I/O 31
IOPortTag & x"05" & PWMTag & PWMBDirPin, -- I/O 32
IOPortTag & x"04" & PWMTag & PWMBDirPin, -- I/O 33
IOPortTag & x"05" & PWMTag & PWMCEnaPin, -- I/O 34
IOPortTag & x"04" & PWMTag & PWMCEnaPin, -- I/O 35
IOPortTag & x"07" & QCountTag & QCountQBPin, -- I/O 36
IOPortTag & x"07" & QCountTag & QCountQAPin, -- I/O 37
IOPortTag & x"06" & QCountTag & QCountQBPin, -- I/O 38
IOPortTag & x"06" & QCountTag & QCountQAPin, -- I/O 39
IOPortTag & x"07" & QCountTag & QCountIDXPin, -- I/O 40
IOPortTag & x"06" & QCountTag & QCountIDXPin, -- I/O 41
IOPortTag & x"07" & PWMTag & PWMAOutPin, -- I/O 42
IOPortTag & x"06" & PWMTag & PWMAOutPin, -- I/O 43
IOPortTag & x"07" & PWMTag & PWMBDirPin, -- I/O 44
IOPortTag & x"06" & PWMTag & PWMBDirPin, -- I/O 45
IOPortTag & x"07" & PWMTag & PWMCEnaPin, -- I/O 46
IOPortTag & x"06" & PWMTag & PWMCEnaPin, -- I/O 47
IOPortTag & x"00" & UARTRTag & URDataPin, -- I/O 48
IOPortTag & x"01" & UARTRTag & URDataPin, -- I/O 49
IOPortTag & x"02" & UARTRTag & URDataPin, -- I/O 50
IOPortTag & x"03" & UARTRTag & URDataPin, -- I/O 51
IOPortTag & x"00" & UARTTTag & UTDataPin, -- I/O 52
IOPortTag & x"00" & UARTTTag & UTDrvEnPin, -- I/O 53
IOPortTag & x"01" & UARTTTag & UTDataPin, -- I/O 54
IOPortTag & x"01" & UARTTTag & UTDrvEnPin, -- I/O 55
IOPortTag & x"02" & UARTTTag & UTDataPin, -- I/O 56
IOPortTag & x"02" & UARTTTag & UTDrvEnPin, -- I/O 57
IOPortTag & x"03" & UARTTTag & UTDataPin, -- I/O 58
IOPortTag & x"03" & UARTTTag & UTDrvEnPin, -- I/O 59
IOPortTag & x"00" & NullTag & x"00", -- I/O 60
IOPortTag & x"00" & NullTag & x"00", -- I/O 61
IOPortTag & x"00" & NullTag & x"00", -- I/O 62
IOPortTag & x"00" & NullTag & x"00", -- I/O 63
IOPortTag & x"00" & NullTag & x"00", -- I/O 64
IOPortTag & x"00" & NullTag & x"00", -- I/O 65
IOPortTag & x"00" & NullTag & x"00", -- I/O 66
IOPortTag & x"00" & NullTag & x"00", -- I/O 67
IOPortTag & x"00" & NullTag & x"00", -- I/O 68
IOPortTag & x"00" & NullTag & x"00", -- I/O 69
IOPortTag & x"00" & NullTag & x"00", -- I/O 70
IOPortTag & x"00" & NullTag & x"00", -- I/O 71
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin);
constant ModuleID_SVUA8_8 : ModuleIDType :=(
(WatchDogTag, x"00", ClockLowTag, x"01", WatchDogTimeAddr&PadT, WatchDogNumRegs, x"00", WatchDogMPBitMask),
(IOPortTag, x"00", ClockLowTag, x"03", PortAddr&PadT, IOPortNumRegs, x"00", IOPortMPBitMask),
(QcountTag, x"02", ClockLowTag, x"08", QcounterAddr&PadT, QCounterNumRegs, x"00", QCounterMPBitMask),
(PWMTag, x"00", ClockHighTag, x"08", PWMValAddr&PadT, PWMNumRegs, x"00", PWMMPBitMask),
(UARTTTag, x"00", ClockLowTag, x"08", UARTTDataAddr&PadT, UARTTNumRegs, x"00", UARTTMPBitMask),
(UARTRTag, x"00", ClockLowTag, x"08", UARTRDataAddr&PadT, UARTRNumRegs, x"00", UARTRMPBitMask),
(LEDTag, x"00", ClockLowTag, x"01", LEDAddr&PadT, LEDNumRegs, x"00", LEDMPBitMask),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000")
);
constant PinDesc_SVUA8_8 : PinDescType :=(
-- Base func sec unit sec func sec pin
IOPortTag & x"01" & QCountTag & QCountQBPin, -- I/O 00
IOPortTag & x"01" & QCountTag & QCountQAPin, -- I/O 01
IOPortTag & x"00" & QCountTag & QCountQBPin, -- I/O 02
IOPortTag & x"00" & QCountTag & QCountQAPin, -- I/O 03
IOPortTag & x"01" & QCountTag & QCountIDXPin, -- I/O 04
IOPortTag & x"00" & QCountTag & QCountIDXPin, -- I/O 05
IOPortTag & x"01" & PWMTag & PWMAOutPin, -- I/O 06
IOPortTag & x"00" & PWMTag & PWMAOutPin, -- I/O 07
IOPortTag & x"01" & PWMTag & PWMBDirPin, -- I/O 08
IOPortTag & x"00" & PWMTag & PWMBDirPin, -- I/O 09
IOPortTag & x"01" & PWMTag & PWMCEnaPin, -- I/O 10
IOPortTag & x"00" & PWMTag & PWMCEnaPin, -- I/O 11
IOPortTag & x"03" & QCountTag & QCountQBPin, -- I/O 12
IOPortTag & x"03" & QCountTag & QCountQAPin, -- I/O 37
IOPortTag & x"02" & QCountTag & QCountQBPin, -- I/O 14
IOPortTag & x"02" & QCountTag & QCountQAPin, -- I/O 15
IOPortTag & x"03" & QCountTag & QCountIDXPin, -- I/O 16
IOPortTag & x"02" & QCountTag & QCountIDXPin, -- I/O 17
IOPortTag & x"03" & PWMTag & PWMAOutPin, -- I/O 18
IOPortTag & x"02" & PWMTag & PWMAOutPin, -- I/O 19
IOPortTag & x"03" & PWMTag & PWMBDirPin, -- I/O 20
IOPortTag & x"02" & PWMTag & PWMBDirPin, -- I/O 21
IOPortTag & x"03" & PWMTag & PWMCEnaPin, -- I/O 22
IOPortTag & x"02" & PWMTag & PWMCenaPin, -- I/O 23
IOPortTag & x"05" & QCountTag & QCountQBPin, -- I/O 24
IOPortTag & x"05" & QCountTag & QCountQAPin, -- I/O 25
IOPortTag & x"04" & QCountTag & QCountQBPin, -- I/O 26
IOPortTag & x"04" & QCountTag & QCountQAPin, -- I/O 27
IOPortTag & x"05" & QCountTag & QCountIDXPin, -- I/O 28
IOPortTag & x"04" & QCountTag & QCountIDXPin, -- I/O 29
IOPortTag & x"05" & PWMTag & PWMAOutPin, -- I/O 30
IOPortTag & x"04" & PWMTag & PWMAOutPin, -- I/O 31
IOPortTag & x"05" & PWMTag & PWMBDirPin, -- I/O 32
IOPortTag & x"04" & PWMTag & PWMBDirPin, -- I/O 33
IOPortTag & x"05" & PWMTag & PWMCEnaPin, -- I/O 34
IOPortTag & x"04" & PWMTag & PWMCEnaPin, -- I/O 35
IOPortTag & x"07" & QCountTag & QCountQBPin, -- I/O 36
IOPortTag & x"07" & QCountTag & QCountQAPin, -- I/O 37
IOPortTag & x"06" & QCountTag & QCountQBPin, -- I/O 38
IOPortTag & x"06" & QCountTag & QCountQAPin, -- I/O 39
IOPortTag & x"07" & QCountTag & QCountIDXPin, -- I/O 40
IOPortTag & x"06" & QCountTag & QCountIDXPin, -- I/O 41
IOPortTag & x"07" & PWMTag & PWMAOutPin, -- I/O 42
IOPortTag & x"06" & PWMTag & PWMAOutPin, -- I/O 43
IOPortTag & x"07" & PWMTag & PWMBDirPin, -- I/O 44
IOPortTag & x"06" & PWMTag & PWMBDirPin, -- I/O 45
IOPortTag & x"07" & PWMTag & PWMCEnaPin, -- I/O 46
IOPortTag & x"06" & PWMTag & PWMCEnaPin, -- I/O 47
IOPortTag & x"00" & UARTRTag & URDataPin, -- I/O 48
IOPortTag & x"01" & UARTRTag & URDataPin, -- I/O 49
IOPortTag & x"02" & UARTRTag & URDataPin, -- I/O 50
IOPortTag & x"03" & UARTRTag & URDataPin, -- I/O 51
IOPortTag & x"00" & UARTTTag & UTDataPin, -- I/O 52
IOPortTag & x"00" & UARTTTag & UTDrvEnPin, -- I/O 53
IOPortTag & x"01" & UARTTTag & UTDataPin, -- I/O 54
IOPortTag & x"01" & UARTTTag & UTDrvEnPin, -- I/O 55
IOPortTag & x"02" & UARTTTag & UTDataPin, -- I/O 56
IOPortTag & x"02" & UARTTTag & UTDrvEnPin, -- I/O 57
IOPortTag & x"03" & UARTTTag & UTDataPin, -- I/O 58
IOPortTag & x"03" & UARTTTag & UTDrvEnPin, -- I/O 59
IOPortTag & x"04" & UARTRTag & URDataPin, -- I/O 60
IOPortTag & x"05" & UARTRTag & URDataPin, -- I/O 61
IOPortTag & x"06" & UARTRTag & URDataPin, -- I/O 62
IOPortTag & x"07" & UARTRTag & URDataPin, -- I/O 63
IOPortTag & x"04" & UARTTTag & UTDataPin, -- I/O 64
IOPortTag & x"04" & UARTTTag & UTDrvEnPin, -- I/O 65
IOPortTag & x"05" & UARTTTag & UTDataPin, -- I/O 66
IOPortTag & x"05" & UARTTTag & UTDrvEnPin, -- I/O 67
IOPortTag & x"06" & UARTTTag & UTDataPin, -- I/O 68
IOPortTag & x"06" & UARTTTag & UTDrvEnPin, -- I/O 69
IOPortTag & x"07" & UARTTTag & UTDataPin, -- I/O 70
IOPortTag & x"07" & UARTTTag & UTDrvEnPin, -- I/O 71
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin);
constant ModuleID_JDosa66 : ModuleIDType :=(
(WatchDogTag, x"00", ClockLowTag, x"01", WatchDogTimeAddr&PadT, WatchDogNumRegs, x"00", WatchDogMPBitMask),
(IOPortTag, x"00", ClockLowTag, x"03", PortAddr&PadT, IOPortNumRegs, x"00", IOPortMPBitMask),
(QcountTag, x"02", ClockLowTag, x"06", QcounterAddr&PadT, QCounterNumRegs, x"00", QCounterMPBitMask),
(StepGenTag, x"01", ClockLowTag, x"06", StepGenRateAddr&PadT, StepGenNumRegs, x"00", StepGenMPBitMask),
(LEDTag, x"00", ClockLowTag, x"01", LEDAddr&PadT, LEDNumRegs, x"00", LEDMPBitMask),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000")
);
constant PinDesc_JDosa66 : PinDescType :=(
-- Base func sec unit sec func sec pin
IOPortTag & x"00" & QCountTag & QCountQAPin, -- I/O 00
IOPortTag & x"00" & QCountTag & QCountQBPin, -- I/O 01
IOPortTag & x"00" & QCountTag & QCountIDXPin, -- I/O 02
IOPortTag & x"01" & QCountTag & QCountQAPin, -- I/O 03
IOPortTag & x"01" & QCountTag & QCountQBPin, -- I/O 04
IOPortTag & x"01" & QCountTag & QCountIDXPin, -- I/O 05
IOPortTag & x"02" & QCountTag & QCountQAPin, -- I/O 06
IOPortTag & x"02" & QCountTag & QCountQBPin, -- I/O 07
IOPortTag & x"02" & QCountTag & QCountIDXPin, -- I/O 08
IOPortTag & x"03" & QCountTag & QCountQAPin, -- I/O 09
IOPortTag & x"03" & QCountTag & QCountQBPin, -- I/O 10
IOPortTag & x"03" & QCountTag & QCountIDXPin, -- I/O 11
IOPortTag & x"04" & QCountTag & QCountQAPin, -- I/O 12
IOPortTag & x"04" & QCountTag & QCountQBPin, -- I/O 37
IOPortTag & x"04" & QCountTag & QCountIDXPin, -- I/O 14
IOPortTag & x"05" & QCountTag & QCountQAPin, -- I/O 15
IOPortTag & x"05" & QCountTag & QCountQBPin, -- I/O 16
IOPortTag & x"05" & QCountTag & QCountIDXPin, -- I/O 17
IOPortTag & x"00" & NullTag & x"00", -- I/O 18
IOPortTag & x"00" & NullTag & x"00", -- I/O 19
IOPortTag & x"00" & NullTag & x"00", -- I/O 20
IOPortTag & x"00" & NullTag & x"00", -- I/O 21
IOPortTag & x"00" & NullTag & x"00", -- I/O 22
IOPortTag & x"00" & NullTag & x"00", -- I/O 23
IOPortTag & x"00" & StepGenTag & StepGenStepPin, -- I/O 24
IOPortTag & x"00" & StepGenTag & StepGenDirPin, -- I/O 25
IOPortTag & x"01" & StepGenTag & StepGenStepPin, -- I/O 26
IOPortTag & x"01" & StepGenTag & StepGenDirPin, -- I/O 27
IOPortTag & x"02" & StepGenTag & StepGenStepPin, -- I/O 28
IOPortTag & x"02" & StepGenTag & StepGenDirPin, -- I/O 29
IOPortTag & x"03" & StepGenTag & StepGenStepPin, -- I/O 30
IOPortTag & x"03" & StepGenTag & StepGenDirPin, -- I/O 31
IOPortTag & x"04" & StepGenTag & StepGenStepPin, -- I/O 32
IOPortTag & x"04" & StepGenTag & StepGenDirPin, -- I/O 33
IOPortTag & x"05" & StepGenTag & StepGenStepPin, -- I/O 34
IOPortTag & x"05" & StepGenTag & StepGenDirPin, -- I/O 35
IOPortTag & x"00" & NullTag & x"00", -- I/O 36
IOPortTag & x"00" & NullTag & x"00", -- I/O 37
IOPortTag & x"00" & NullTag & x"00", -- I/O 38
IOPortTag & x"00" & NullTag & x"00", -- I/O 39
IOPortTag & x"00" & NullTag & x"00", -- I/O 40
IOPortTag & x"00" & NullTag & x"00", -- I/O 41
IOPortTag & x"00" & NullTag & x"00", -- I/O 42
IOPortTag & x"00" & NullTag & x"00", -- I/O 43
IOPortTag & x"00" & NullTag & x"00", -- I/O 44
IOPortTag & x"00" & NullTag & x"00", -- I/O 45
IOPortTag & x"00" & NullTag & x"00", -- I/O 46
IOPortTag & x"00" & NullTag & x"00", -- I/O 47
IOPortTag & x"00" & NullTag & x"00", -- I/O 48
IOPortTag & x"00" & NullTag & x"00", -- I/O 49
IOPortTag & x"00" & NullTag & x"00", -- I/O 50
IOPortTag & x"00" & NullTag & x"00", -- I/O 51
IOPortTag & x"00" & NullTag & x"00", -- I/O 52
IOPortTag & x"00" & NullTag & x"00", -- I/O 53
IOPortTag & x"00" & NullTag & x"00", -- I/O 54
IOPortTag & x"00" & NullTag & x"00", -- I/O 55
IOPortTag & x"00" & NullTag & x"00", -- I/O 56
IOPortTag & x"00" & NullTag & x"00", -- I/O 57
IOPortTag & x"00" & NullTag & x"00", -- I/O 58
IOPortTag & x"00" & NullTag & x"00", -- I/O 59
IOPortTag & x"00" & NullTag & x"00", -- I/O 60
IOPortTag & x"00" & NullTag & x"00", -- I/O 61
IOPortTag & x"00" & NullTag & x"00", -- I/O 62
IOPortTag & x"00" & NullTag & x"00", -- I/O 63
IOPortTag & x"00" & NullTag & x"00", -- I/O 64
IOPortTag & x"00" & NullTag & x"00", -- I/O 65
IOPortTag & x"00" & NullTag & x"00", -- I/O 66
IOPortTag & x"00" & NullTag & x"00", -- I/O 67
IOPortTag & x"00" & NullTag & x"00", -- I/O 68
IOPortTag & x"00" & NullTag & x"00", -- I/O 69
IOPortTag & x"00" & NullTag & x"00", -- I/O 70
IOPortTag & x"00" & NullTag & x"00", -- I/O 71
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin);
constant ModuleID_JDosa88 : ModuleIDType :=(
(WatchDogTag, x"00", ClockLowTag, x"01", WatchDogTimeAddr&PadT, WatchDogNumRegs, x"00", WatchDogMPBitMask),
(IOPortTag, x"00", ClockLowTag, x"03", PortAddr&PadT, IOPortNumRegs, x"00", IOPortMPBitMask),
(QcountTag, x"02", ClockLowTag, x"08", QcounterAddr&PadT, QCounterNumRegs, x"00", QCounterMPBitMask),
(StepGenTag, x"01", ClockLowTag, x"08", StepGenRateAddr&PadT, StepGenNumRegs, x"00", StepGenMPBitMask),
(LEDTag, x"00", ClockLowTag, x"01", LEDAddr&PadT, LEDNumRegs, x"00", LEDMPBitMask),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000")
);
constant PinDesc_JDosa88 : PinDescType :=(
-- Base func sec unit sec func sec pin
IOPortTag & x"00" & QCountTag & QCountQAPin, -- I/O 00
IOPortTag & x"00" & QCountTag & QCountQBPin, -- I/O 01
IOPortTag & x"00" & QCountTag & QCountIDXPin, -- I/O 02
IOPortTag & x"01" & QCountTag & QCountQAPin, -- I/O 03
IOPortTag & x"01" & QCountTag & QCountQBPin, -- I/O 04
IOPortTag & x"01" & QCountTag & QCountIDXPin, -- I/O 05
IOPortTag & x"02" & QCountTag & QCountQAPin, -- I/O 06
IOPortTag & x"02" & QCountTag & QCountQBPin, -- I/O 07
IOPortTag & x"02" & QCountTag & QCountIDXPin, -- I/O 08
IOPortTag & x"03" & QCountTag & QCountQAPin, -- I/O 09
IOPortTag & x"03" & QCountTag & QCountQBPin, -- I/O 10
IOPortTag & x"03" & QCountTag & QCountIDXPin, -- I/O 11
IOPortTag & x"04" & QCountTag & QCountQAPin, -- I/O 12
IOPortTag & x"04" & QCountTag & QCountQBPin, -- I/O 37
IOPortTag & x"04" & QCountTag & QCountIDXPin, -- I/O 14
IOPortTag & x"05" & QCountTag & QCountQAPin, -- I/O 15
IOPortTag & x"05" & QCountTag & QCountQBPin, -- I/O 16
IOPortTag & x"05" & QCountTag & QCountIDXPin, -- I/O 17
IOPortTag & x"06" & QCountTag & QCountQAPin, -- I/O 18
IOPortTag & x"06" & QCountTag & QCountQBPin, -- I/O 19
IOPortTag & x"06" & QCountTag & QCountIDXPin, -- I/O 20
IOPortTag & x"07" & QCountTag & QCountQAPin, -- I/O 21
IOPortTag & x"07" & QCountTag & QCountQBPin, -- I/O 22
IOPortTag & x"07" & QCountTag & QCountIDXPin, -- I/O 23
IOPortTag & x"00" & StepGenTag & StepGenStepPin, -- I/O 24
IOPortTag & x"00" & StepGenTag & StepGenDirPin, -- I/O 25
IOPortTag & x"01" & StepGenTag & StepGenStepPin, -- I/O 26
IOPortTag & x"01" & StepGenTag & StepGenDirPin, -- I/O 27
IOPortTag & x"02" & StepGenTag & StepGenStepPin, -- I/O 28
IOPortTag & x"02" & StepGenTag & StepGenDirPin, -- I/O 29
IOPortTag & x"03" & StepGenTag & StepGenStepPin, -- I/O 30
IOPortTag & x"03" & StepGenTag & StepGenDirPin, -- I/O 31
IOPortTag & x"04" & StepGenTag & StepGenStepPin, -- I/O 32
IOPortTag & x"04" & StepGenTag & StepGenDirPin, -- I/O 33
IOPortTag & x"05" & StepGenTag & StepGenStepPin, -- I/O 34
IOPortTag & x"05" & StepGenTag & StepGenDirPin, -- I/O 35
IOPortTag & x"06" & StepGenTag & StepGenStepPin, -- I/O 36
IOPortTag & x"06" & StepGenTag & StepGenDirPin, -- I/O 37
IOPortTag & x"07" & StepGenTag & StepGenStepPin, -- I/O 38
IOPortTag & x"07" & StepGenTag & StepGenDirPin, -- I/O 39
IOPortTag & x"00" & NullTag & x"00", -- I/O 40
IOPortTag & x"00" & NullTag & x"00", -- I/O 41
IOPortTag & x"00" & NullTag & x"00", -- I/O 42
IOPortTag & x"00" & NullTag & x"00", -- I/O 43
IOPortTag & x"00" & NullTag & x"00", -- I/O 44
IOPortTag & x"00" & NullTag & x"00", -- I/O 45
IOPortTag & x"00" & NullTag & x"00", -- I/O 46
IOPortTag & x"00" & NullTag & x"00", -- I/O 47
IOPortTag & x"00" & NullTag & x"00", -- I/O 48
IOPortTag & x"00" & NullTag & x"00", -- I/O 49
IOPortTag & x"00" & NullTag & x"00", -- I/O 50
IOPortTag & x"00" & NullTag & x"00", -- I/O 51
IOPortTag & x"00" & NullTag & x"00", -- I/O 52
IOPortTag & x"00" & NullTag & x"00", -- I/O 53
IOPortTag & x"00" & NullTag & x"00", -- I/O 54
IOPortTag & x"00" & NullTag & x"00", -- I/O 55
IOPortTag & x"00" & NullTag & x"00", -- I/O 56
IOPortTag & x"00" & NullTag & x"00", -- I/O 57
IOPortTag & x"00" & NullTag & x"00", -- I/O 58
IOPortTag & x"00" & NullTag & x"00", -- I/O 59
IOPortTag & x"00" & NullTag & x"00", -- I/O 60
IOPortTag & x"00" & NullTag & x"00", -- I/O 61
IOPortTag & x"00" & NullTag & x"00", -- I/O 62
IOPortTag & x"00" & NullTag & x"00", -- I/O 63
IOPortTag & x"00" & NullTag & x"00", -- I/O 64
IOPortTag & x"00" & NullTag & x"00", -- I/O 65
IOPortTag & x"00" & NullTag & x"00", -- I/O 66
IOPortTag & x"00" & NullTag & x"00", -- I/O 67
IOPortTag & x"00" & NullTag & x"00", -- I/O 68
IOPortTag & x"00" & NullTag & x"00", -- I/O 69
IOPortTag & x"00" & NullTag & x"00", -- I/O 70
IOPortTag & x"00" & NullTag & x"00", -- I/O 71
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin);
constant ModuleID_JDosa1212 : ModuleIDType :=(
(WatchDogTag, x"00", ClockLowTag, x"01", WatchDogTimeAddr&PadT, WatchDogNumRegs, x"00", WatchDogMPBitMask),
(IOPortTag, x"00", ClockLowTag, x"03", PortAddr&PadT, IOPortNumRegs, x"00", IOPortMPBitMask),
(QcountTag, x"02", ClockLowTag, x"0C", QcounterAddr&PadT, QCounterNumRegs, x"00", QCounterMPBitMask),
(StepGenTag, x"01", ClockLowTag, x"0C", StepGenRateAddr&PadT, StepGenNumRegs, x"00", StepGenMPBitMask),
(LEDTag, x"00", ClockLowTag, x"01", LEDAddr&PadT, LEDNumRegs, x"00", LEDMPBitMask),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000")
);
constant PinDesc_JDosa1212 : PinDescType :=(
-- Base func sec unit sec func sec pin
IOPortTag & x"00" & QCountTag & QCountQAPin, -- I/O 00
IOPortTag & x"00" & QCountTag & QCountQBPin, -- I/O 01
IOPortTag & x"00" & QCountTag & QCountIDXPin, -- I/O 02
IOPortTag & x"01" & QCountTag & QCountQAPin, -- I/O 03
IOPortTag & x"01" & QCountTag & QCountQBPin, -- I/O 04
IOPortTag & x"01" & QCountTag & QCountIDXPin, -- I/O 05
IOPortTag & x"02" & QCountTag & QCountQAPin, -- I/O 06
IOPortTag & x"02" & QCountTag & QCountQBPin, -- I/O 07
IOPortTag & x"02" & QCountTag & QCountIDXPin, -- I/O 08
IOPortTag & x"03" & QCountTag & QCountQAPin, -- I/O 09
IOPortTag & x"03" & QCountTag & QCountQBPin, -- I/O 10
IOPortTag & x"03" & QCountTag & QCountIDXPin, -- I/O 11
IOPortTag & x"04" & QCountTag & QCountQAPin, -- I/O 12
IOPortTag & x"04" & QCountTag & QCountQBPin, -- I/O 37
IOPortTag & x"04" & QCountTag & QCountIDXPin, -- I/O 14
IOPortTag & x"05" & QCountTag & QCountQAPin, -- I/O 15
IOPortTag & x"05" & QCountTag & QCountQBPin, -- I/O 16
IOPortTag & x"05" & QCountTag & QCountIDXPin, -- I/O 17
IOPortTag & x"06" & QCountTag & QCountQAPin, -- I/O 18
IOPortTag & x"06" & QCountTag & QCountQBPin, -- I/O 19
IOPortTag & x"06" & QCountTag & QCountIDXPin, -- I/O 20
IOPortTag & x"07" & QCountTag & QCountQAPin, -- I/O 21
IOPortTag & x"07" & QCountTag & QCountQBPin, -- I/O 22
IOPortTag & x"07" & QCountTag & QCountIDXPin, -- I/O 23
IOPortTag & x"00" & StepGenTag & StepGenStepPin, -- I/O 24
IOPortTag & x"00" & StepGenTag & StepGenDirPin, -- I/O 25
IOPortTag & x"01" & StepGenTag & StepGenStepPin, -- I/O 26
IOPortTag & x"01" & StepGenTag & StepGenDirPin, -- I/O 27
IOPortTag & x"02" & StepGenTag & StepGenStepPin, -- I/O 28
IOPortTag & x"02" & StepGenTag & StepGenDirPin, -- I/O 29
IOPortTag & x"03" & StepGenTag & StepGenStepPin, -- I/O 30
IOPortTag & x"03" & StepGenTag & StepGenDirPin, -- I/O 31
IOPortTag & x"04" & StepGenTag & StepGenStepPin, -- I/O 32
IOPortTag & x"04" & StepGenTag & StepGenDirPin, -- I/O 33
IOPortTag & x"05" & StepGenTag & StepGenStepPin, -- I/O 34
IOPortTag & x"05" & StepGenTag & StepGenDirPin, -- I/O 35
IOPortTag & x"06" & StepGenTag & StepGenStepPin, -- I/O 36
IOPortTag & x"06" & StepGenTag & StepGenDirPin, -- I/O 37
IOPortTag & x"07" & StepGenTag & StepGenStepPin, -- I/O 38
IOPortTag & x"07" & StepGenTag & StepGenDirPin, -- I/O 39
IOPortTag & x"08" & StepGenTag & StepGenStepPin, -- I/O 40
IOPortTag & x"08" & StepGenTag & StepGenDirPin, -- I/O 41
IOPortTag & x"09" & StepGenTag & StepGenStepPin, -- I/O 42
IOPortTag & x"09" & StepGenTag & StepGenDirPin, -- I/O 43
IOPortTag & x"0A" & StepGenTag & StepGenStepPin, -- I/O 44
IOPortTag & x"0A" & StepGenTag & StepGenDirPin, -- I/O 45
IOPortTag & x"0B" & StepGenTag & StepGenStepPin, -- I/O 46
IOPortTag & x"0B" & StepGenTag & StepGenDirPin, -- I/O 47
IOPortTag & x"08" & QCountTag & QCountQAPin, -- I/O 48
IOPortTag & x"08" & QCountTag & QCountQBPin, -- I/O 49
IOPortTag & x"08" & QCountTag & QCountIDXPin, -- I/O 50
IOPortTag & x"09" & QCountTag & QCountQAPin, -- I/O 51
IOPortTag & x"09" & QCountTag & QCountQBPin, -- I/O 52
IOPortTag & x"09" & QCountTag & QCountIDXPin, -- I/O 53
IOPortTag & x"0A" & QCountTag & QCountQAPin, -- I/O 54
IOPortTag & x"0A" & QCountTag & QCountQBPin, -- I/O 55
IOPortTag & x"0A" & QCountTag & QCountIDXPin, -- I/O 56
IOPortTag & x"0B" & QCountTag & QCountQAPin, -- I/O 57
IOPortTag & x"0B" & QCountTag & QCountQBPin, -- I/O 58
IOPortTag & x"0B" & QCountTag & QCountIDXPin, -- I/O 59
IOPortTag & x"00" & NullTag & x"00", -- I/O 60
IOPortTag & x"00" & NullTag & x"00", -- I/O 61
IOPortTag & x"00" & NullTag & x"00", -- I/O 62
IOPortTag & x"00" & NullTag & x"00", -- I/O 63
IOPortTag & x"00" & NullTag & x"00", -- I/O 64
IOPortTag & x"00" & NullTag & x"00", -- I/O 65
IOPortTag & x"00" & NullTag & x"00", -- I/O 66
IOPortTag & x"00" & NullTag & x"00", -- I/O 67
IOPortTag & x"00" & NullTag & x"00", -- I/O 68
IOPortTag & x"00" & NullTag & x"00", -- I/O 69
IOPortTag & x"00" & NullTag & x"00", -- I/O 70
IOPortTag & x"00" & NullTag & x"00", -- I/O 71
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin);
-------------------------------------------------------------------------------------------------
-- 4 connector pinouts (5I22)
-------------------------------------------------------------------------------------------------
constant ModuleID_4xi30 : ModuleIDType :=(
(WatchDogTag, x"00", ClockLowTag, x"01", WatchDogTimeAddr&PadT, WatchDogNumRegs, x"00", WatchDogMPBitMask),
(IOPortTag, x"00", ClockLowTag, x"04", PortAddr&PadT, IOPortNumRegs, x"00", IOPortMPBitMask),
(QcountTag, x"02", ClockLowTag, x"10", QcounterAddr&PadT, QCounterNumRegs, x"00", QCounterMPBitMask),
(PWMTag, x"00", ClockHighTag, x"10", PWMValAddr&PadT, PWMNumRegs, x"00", PWMMPBitMask),
(LEDTag, x"00", ClockLowTag, x"01", LEDAddr&PadT, LEDNumRegs, x"00", LEDMPBitMask),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000")
);
constant PinDesc_4xi30 : PinDescType :=(
-- Base func sec unit sec func sec pin
IOPortTag & x"01" & QCountTag & x"02",
IOPortTag & x"01" & QCountTag & x"01",
IOPortTag & x"00" & QCountTag & x"02",
IOPortTag & x"00" & QCountTag & x"01",
IOPortTag & x"01" & QCountTag & x"03",
IOPortTag & x"00" & QCountTag & x"03",
IOPortTag & x"01" & PWMTag & x"81",
IOPortTag & x"00" & PWMTag & x"81",
IOPortTag & x"01" & PWMTag & x"82",
IOPortTag & x"00" & PWMTag & x"82",
IOPortTag & x"01" & PWMTag & x"83",
IOPortTag & x"00" & PWMTag & x"83",
IOPortTag & x"03" & QCountTag & x"02",
IOPortTag & x"03" & QCountTag & x"01",
IOPortTag & x"02" & QCountTag & x"02",
IOPortTag & x"02" & QCountTag & x"01",
IOPortTag & x"03" & QCountTag & x"03",
IOPortTag & x"02" & QCountTag & x"03",
IOPortTag & x"03" & PWMTag & x"81",
IOPortTag & x"02" & PWMTag & x"81",
IOPortTag & x"03" & PWMTag & x"82",
IOPortTag & x"02" & PWMTag & x"82",
IOPortTag & x"03" & PWMTag & x"83",
IOPortTag & x"02" & PWMTag & x"83",
IOPortTag & x"05" & QCountTag & x"02",
IOPortTag & x"05" & QCountTag & x"01",
IOPortTag & x"04" & QCountTag & x"02",
IOPortTag & x"04" & QCountTag & x"01",
IOPortTag & x"05" & QCountTag & x"03",
IOPortTag & x"04" & QCountTag & x"03",
IOPortTag & x"05" & PWMTag & x"81",
IOPortTag & x"04" & PWMTag & x"81",
IOPortTag & x"05" & PWMTag & x"82",
IOPortTag & x"04" & PWMTag & x"82",
IOPortTag & x"05" & PWMTag & x"83",
IOPortTag & x"04" & PWMTag & x"83",
IOPortTag & x"07" & QCountTag & x"02",
IOPortTag & x"07" & QCountTag & x"01",
IOPortTag & x"06" & QCountTag & x"02",
IOPortTag & x"06" & QCountTag & x"01",
IOPortTag & x"07" & QCountTag & x"03",
IOPortTag & x"06" & QCountTag & x"03",
IOPortTag & x"07" & PWMTag & x"81",
IOPortTag & x"06" & PWMTag & x"81",
IOPortTag & x"07" & PWMTag & x"82",
IOPortTag & x"06" & PWMTag & x"82",
IOPortTag & x"07" & PWMTag & x"83",
IOPortTag & x"06" & PWMTag & x"83",
IOPortTag & x"09" & QCountTag & x"02",
IOPortTag & x"09" & QCountTag & x"01",
IOPortTag & x"08" & QCountTag & x"02",
IOPortTag & x"08" & QCountTag & x"01",
IOPortTag & x"09" & QCountTag & x"03",
IOPortTag & x"08" & QCountTag & x"03",
IOPortTag & x"09" & PWMTag & x"81",
IOPortTag & x"08" & PWMTag & x"81",
IOPortTag & x"09" & PWMTag & x"82",
IOPortTag & x"08" & PWMTag & x"82",
IOPortTag & x"09" & PWMTag & x"83",
IOPortTag & x"08" & PWMTag & x"83",
IOPortTag & x"0B" & QCountTag & x"02",
IOPortTag & x"0B" & QCountTag & x"01",
IOPortTag & x"0A" & QCountTag & x"02",
IOPortTag & x"0A" & QCountTag & x"01",
IOPortTag & x"0B" & QCountTag & x"03",
IOPortTag & x"0A" & QCountTag & x"03",
IOPortTag & x"0B" & PWMTag & x"81",
IOPortTag & x"0A" & PWMTag & x"81",
IOPortTag & x"0B" & PWMTag & x"82",
IOPortTag & x"0A" & PWMTag & x"82",
IOPortTag & x"0B" & PWMTag & x"83",
IOPortTag & x"0A" & PWMTag & x"83",
IOPortTag & x"0D" & QCountTag & x"02",
IOPortTag & x"0D" & QCountTag & x"01",
IOPortTag & x"0C" & QCountTag & x"02",
IOPortTag & x"0C" & QCountTag & x"01",
IOPortTag & x"0D" & QCountTag & x"03",
IOPortTag & x"0C" & QCountTag & x"03",
IOPortTag & x"0D" & PWMTag & x"81",
IOPortTag & x"0C" & PWMTag & x"81",
IOPortTag & x"0D" & PWMTag & x"82",
IOPortTag & x"0C" & PWMTag & x"82",
IOPortTag & x"0D" & PWMTag & x"83",
IOPortTag & x"0C" & PWMTag & x"83",
IOPortTag & x"0F" & QCountTag & x"02",
IOPortTag & x"0F" & QCountTag & x"01",
IOPortTag & x"0E" & QCountTag & x"02",
IOPortTag & x"0E" & QCountTag & x"01",
IOPortTag & x"0F" & QCountTag & x"03",
IOPortTag & x"0E" & QCountTag & x"03",
IOPortTag & x"0F" & PWMTag & x"81",
IOPortTag & x"0E" & PWMTag & x"81",
IOPortTag & x"0F" & PWMTag & x"82",
IOPortTag & x"0E" & PWMTag & x"82",
IOPortTag & x"0F" & PWMTag & x"83",
IOPortTag & x"0E" & PWMTag & x"83",
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin);
constant ModuleID_SVST8_8 : ModuleIDType :=(
(WatchDogTag, x"00", ClockLowTag, x"01", WatchDogTimeAddr&PadT, WatchDogNumRegs, x"00", WatchDogMPBitMask),
(IOPortTag, x"00", ClockLowTag, x"04", PortAddr&PadT, IOPortNumRegs, x"00", IOPortMPBitMask),
(QcountTag, x"02", ClockLowTag, x"08", QcounterAddr&PadT, QCounterNumRegs, x"00", QCounterMPBitMask),
(PWMTag, x"00", ClockHighTag, x"08", PWMValAddr&PadT, PWMNumRegs, x"00", PWMMPBitMask),
(StepGenTag, x"01", ClockLowTag, x"08", StepGenRateAddr&PadT, StepGenNumRegs, x"00", StepGenMPBitMask),
(LEDTag, x"00", ClockLowTag, x"01", LEDAddr&PadT, LEDNumRegs, x"00", LEDMPBitMask),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000")
);
constant PinDesc_SVST8_8 : PinDescType :=(
-- Base func sec unit sec func sec pin
IOPortTag & x"01" & QCountTag & x"02",
IOPortTag & x"01" & QCountTag & x"01",
IOPortTag & x"00" & QCountTag & x"02",
IOPortTag & x"00" & QCountTag & x"01",
IOPortTag & x"01" & QCountTag & x"03",
IOPortTag & x"00" & QCountTag & x"03",
IOPortTag & x"01" & PWMTag & x"81",
IOPortTag & x"00" & PWMTag & x"81",
IOPortTag & x"01" & PWMTag & x"82",
IOPortTag & x"00" & PWMTag & x"82",
IOPortTag & x"01" & PWMTag & x"83",
IOPortTag & x"00" & PWMTag & x"83",
IOPortTag & x"03" & QCountTag & x"02",
IOPortTag & x"03" & QCountTag & x"01",
IOPortTag & x"02" & QCountTag & x"02",
IOPortTag & x"02" & QCountTag & x"01",
IOPortTag & x"03" & QCountTag & x"03",
IOPortTag & x"02" & QCountTag & x"03",
IOPortTag & x"03" & PWMTag & x"81",
IOPortTag & x"02" & PWMTag & x"81",
IOPortTag & x"03" & PWMTag & x"82",
IOPortTag & x"02" & PWMTag & x"82",
IOPortTag & x"03" & PWMTag & x"83",
IOPortTag & x"02" & PWMTag & x"83",
IOPortTag & x"05" & QCountTag & x"02",
IOPortTag & x"05" & QCountTag & x"01",
IOPortTag & x"04" & QCountTag & x"02",
IOPortTag & x"04" & QCountTag & x"01",
IOPortTag & x"05" & QCountTag & x"03",
IOPortTag & x"04" & QCountTag & x"03",
IOPortTag & x"05" & PWMTag & x"81",
IOPortTag & x"04" & PWMTag & x"81",
IOPortTag & x"05" & PWMTag & x"82",
IOPortTag & x"04" & PWMTag & x"82",
IOPortTag & x"05" & PWMTag & x"83",
IOPortTag & x"04" & PWMTag & x"83",
IOPortTag & x"07" & QCountTag & x"02",
IOPortTag & x"07" & QCountTag & x"01",
IOPortTag & x"06" & QCountTag & x"02",
IOPortTag & x"06" & QCountTag & x"01",
IOPortTag & x"07" & QCountTag & x"03",
IOPortTag & x"06" & QCountTag & x"03",
IOPortTag & x"07" & PWMTag & x"81",
IOPortTag & x"06" & PWMTag & x"81",
IOPortTag & x"07" & PWMTag & x"82",
IOPortTag & x"06" & PWMTag & x"82",
IOPortTag & x"07" & PWMTag & x"83",
IOPortTag & x"06" & PWMTag & x"83",
IOPortTag & x"00" & StepGenTag & x"81",
IOPortTag & x"00" & StepGenTag & x"82",
IOPortTag & x"00" & StepGenTag & x"83",
IOPortTag & x"00" & StepGenTag & x"84",
IOPortTag & x"00" & StepGenTag & x"85",
IOPortTag & x"00" & StepGenTag & x"86",
IOPortTag & x"01" & StepGenTag & x"81",
IOPortTag & x"01" & StepGenTag & x"82",
IOPortTag & x"01" & StepGenTag & x"83",
IOPortTag & x"01" & StepGenTag & x"84",
IOPortTag & x"01" & StepGenTag & x"85",
IOPortTag & x"01" & StepGenTag & x"86",
IOPortTag & x"02" & StepGenTag & x"81",
IOPortTag & x"02" & StepGenTag & x"82",
IOPortTag & x"02" & StepGenTag & x"83",
IOPortTag & x"02" & StepGenTag & x"84",
IOPortTag & x"02" & StepGenTag & x"85",
IOPortTag & x"02" & StepGenTag & x"86",
IOPortTag & x"03" & StepGenTag & x"81",
IOPortTag & x"03" & StepGenTag & x"82",
IOPortTag & x"03" & StepGenTag & x"83",
IOPortTag & x"03" & StepGenTag & x"84",
IOPortTag & x"03" & StepGenTag & x"85",
IOPortTag & x"03" & StepGenTag & x"86",
IOPortTag & x"04" & StepGenTag & x"81",
IOPortTag & x"04" & StepGenTag & x"82",
IOPortTag & x"04" & StepGenTag & x"83",
IOPortTag & x"04" & StepGenTag & x"84",
IOPortTag & x"04" & StepGenTag & x"85",
IOPortTag & x"04" & StepGenTag & x"86",
IOPortTag & x"05" & StepGenTag & x"81",
IOPortTag & x"05" & StepGenTag & x"82",
IOPortTag & x"05" & StepGenTag & x"83",
IOPortTag & x"05" & StepGenTag & x"84",
IOPortTag & x"05" & StepGenTag & x"85",
IOPortTag & x"05" & StepGenTag & x"86",
IOPortTag & x"06" & StepGenTag & x"81",
IOPortTag & x"06" & StepGenTag & x"82",
IOPortTag & x"06" & StepGenTag & x"83",
IOPortTag & x"06" & StepGenTag & x"84",
IOPortTag & x"06" & StepGenTag & x"85",
IOPortTag & x"06" & StepGenTag & x"86",
IOPortTag & x"07" & StepGenTag & x"81",
IOPortTag & x"07" & StepGenTag & x"82",
IOPortTag & x"07" & StepGenTag & x"83",
IOPortTag & x"07" & StepGenTag & x"84",
IOPortTag & x"07" & StepGenTag & x"85",
IOPortTag & x"07" & StepGenTag & x"86",
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin);
constant ModuleID_SVST8_24 : ModuleIDType :=(
(WatchDogTag, x"00", ClockLowTag, x"01", WatchDogTimeAddr&PadT, WatchDogNumRegs, x"00", WatchDogMPBitMask),
(IOPortTag, x"00", ClockLowTag, x"04", PortAddr&PadT, IOPortNumRegs, x"00", IOPortMPBitMask),
(QcountTag, x"02", ClockLowTag, x"08", QcounterAddr&PadT, QCounterNumRegs, x"00", QCounterMPBitMask),
(PWMTag, x"00", ClockHighTag, x"08", PWMValAddr&PadT, PWMNumRegs, x"00", PWMMPBitMask),
(StepGenTag, x"01", ClockLowTag, x"18", StepGenRateAddr&PadT, StepGenNumRegs, x"00", StepGenMPBitMask),
(LEDTag, x"00", ClockLowTag, x"01", LEDAddr&PadT, LEDNumRegs, x"00", LEDMPBitMask),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000")
);
constant PinDesc_SVST8_24 : PinDescType :=(
-- Base func sec unit sec func sec pin
IOPortTag & x"01" & QCountTag & x"02",
IOPortTag & x"01" & QCountTag & x"01",
IOPortTag & x"00" & QCountTag & x"02",
IOPortTag & x"00" & QCountTag & x"01",
IOPortTag & x"01" & QCountTag & x"03",
IOPortTag & x"00" & QCountTag & x"03",
IOPortTag & x"01" & PWMTag & x"81",
IOPortTag & x"00" & PWMTag & x"81",
IOPortTag & x"01" & PWMTag & x"82",
IOPortTag & x"00" & PWMTag & x"82",
IOPortTag & x"01" & PWMTag & x"83",
IOPortTag & x"00" & PWMTag & x"83",
IOPortTag & x"03" & QCountTag & x"02",
IOPortTag & x"03" & QCountTag & x"01",
IOPortTag & x"02" & QCountTag & x"02",
IOPortTag & x"02" & QCountTag & x"01",
IOPortTag & x"03" & QCountTag & x"03",
IOPortTag & x"02" & QCountTag & x"03",
IOPortTag & x"03" & PWMTag & x"81",
IOPortTag & x"02" & PWMTag & x"81",
IOPortTag & x"03" & PWMTag & x"82",
IOPortTag & x"02" & PWMTag & x"82",
IOPortTag & x"03" & PWMTag & x"83",
IOPortTag & x"02" & PWMTag & x"83",
IOPortTag & x"05" & QCountTag & x"02",
IOPortTag & x"05" & QCountTag & x"01",
IOPortTag & x"04" & QCountTag & x"02",
IOPortTag & x"04" & QCountTag & x"01",
IOPortTag & x"05" & QCountTag & x"03",
IOPortTag & x"04" & QCountTag & x"03",
IOPortTag & x"05" & PWMTag & x"81",
IOPortTag & x"04" & PWMTag & x"81",
IOPortTag & x"05" & PWMTag & x"82",
IOPortTag & x"04" & PWMTag & x"82",
IOPortTag & x"05" & PWMTag & x"83",
IOPortTag & x"04" & PWMTag & x"83",
IOPortTag & x"07" & QCountTag & x"02",
IOPortTag & x"07" & QCountTag & x"01",
IOPortTag & x"06" & QCountTag & x"02",
IOPortTag & x"06" & QCountTag & x"01",
IOPortTag & x"07" & QCountTag & x"03",
IOPortTag & x"06" & QCountTag & x"03",
IOPortTag & x"07" & PWMTag & x"81",
IOPortTag & x"06" & PWMTag & x"81",
IOPortTag & x"07" & PWMTag & x"82",
IOPortTag & x"06" & PWMTag & x"82",
IOPortTag & x"07" & PWMTag & x"83",
IOPortTag & x"06" & PWMTag & x"83",
IOPortTag & x"00" & StepGenTag & x"81",
IOPortTag & x"00" & StepGenTag & x"82",
IOPortTag & x"01" & StepGenTag & x"81",
IOPortTag & x"01" & StepGenTag & x"82",
IOPortTag & x"02" & StepGenTag & x"81",
IOPortTag & x"02" & StepGenTag & x"82",
IOPortTag & x"03" & StepGenTag & x"81",
IOPortTag & x"03" & StepGenTag & x"82",
IOPortTag & x"04" & StepGenTag & x"81",
IOPortTag & x"04" & StepGenTag & x"82",
IOPortTag & x"05" & StepGenTag & x"81",
IOPortTag & x"05" & StepGenTag & x"82",
IOPortTag & x"06" & StepGenTag & x"81",
IOPortTag & x"06" & StepGenTag & x"82",
IOPortTag & x"07" & StepGenTag & x"81",
IOPortTag & x"07" & StepGenTag & x"82",
IOPortTag & x"08" & StepGenTag & x"81",
IOPortTag & x"08" & StepGenTag & x"82",
IOPortTag & x"09" & StepGenTag & x"81",
IOPortTag & x"09" & StepGenTag & x"82",
IOPortTag & x"0A" & StepGenTag & x"81",
IOPortTag & x"0A" & StepGenTag & x"82",
IOPortTag & x"0B" & StepGenTag & x"81",
IOPortTag & x"0B" & StepGenTag & x"82",
IOPortTag & x"0C" & StepGenTag & x"81",
IOPortTag & x"0C" & StepGenTag & x"82",
IOPortTag & x"0D" & StepGenTag & x"81",
IOPortTag & x"0D" & StepGenTag & x"82",
IOPortTag & x"0E" & StepGenTag & x"81",
IOPortTag & x"0E" & StepGenTag & x"82",
IOPortTag & x"0F" & StepGenTag & x"81",
IOPortTag & x"0F" & StepGenTag & x"82",
IOPortTag & x"10" & StepGenTag & x"81",
IOPortTag & x"10" & StepGenTag & x"82",
IOPortTag & x"11" & StepGenTag & x"81",
IOPortTag & x"11" & StepGenTag & x"82",
IOPortTag & x"12" & StepGenTag & x"81",
IOPortTag & x"12" & StepGenTag & x"82",
IOPortTag & x"13" & StepGenTag & x"81",
IOPortTag & x"13" & StepGenTag & x"82",
IOPortTag & x"14" & StepGenTag & x"81",
IOPortTag & x"14" & StepGenTag & x"82",
IOPortTag & x"15" & StepGenTag & x"81",
IOPortTag & x"15" & StepGenTag & x"82",
IOPortTag & x"16" & StepGenTag & x"81",
IOPortTag & x"16" & StepGenTag & x"82",
IOPortTag & x"17" & StepGenTag & x"81",
IOPortTag & x"17" & StepGenTag & x"82",
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin);
constant ModuleID_SVSTSP8_12_6 : ModuleIDType :=(
(WatchDogTag, x"00", ClockLowTag, x"01", WatchDogTimeAddr&PadT, WatchDogNumRegs, x"00", WatchDogMPBitMask),
(IOPortTag, x"00", ClockLowTag, x"04", PortAddr&PadT, IOPortNumRegs, x"00", IOPortMPBitMask),
(QcountTag, x"02", ClockLowTag, x"08", QcounterAddr&PadT, QCounterNumRegs, x"00", QCounterMPBitMask),
(PWMTag, x"00", ClockHighTag, x"08", PWMValAddr&PadT, PWMNumRegs, x"00", PWMMPBitMask),
(StepGenTag, x"01", ClockLowTag, x"0C", StepGenRateAddr&PadT, StepGenNumRegs, x"00", StepGenMPBitMask),
(SPITag, x"00", ClockLowTag, x"06", SPIDataAddr&PadT, SPINumRegs, x"00", SPIMPBitMask),
(LEDTag, x"00", ClockLowTag, x"01", LEDAddr&PadT, LEDNumRegs, x"00", LEDMPBitMask),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000")
);
constant PinDesc_SVSTSP8_12_6 : PinDescType :=(
-- Base func sec unit sec func sec pin
IOPortTag & x"01" & QCountTag & x"02",
IOPortTag & x"01" & QCountTag & x"01",
IOPortTag & x"00" & QCountTag & x"02",
IOPortTag & x"00" & QCountTag & x"01",
IOPortTag & x"01" & QCountTag & x"03",
IOPortTag & x"00" & QCountTag & x"03",
IOPortTag & x"01" & PWMTag & x"81",
IOPortTag & x"00" & PWMTag & x"81",
IOPortTag & x"01" & PWMTag & x"82",
IOPortTag & x"00" & PWMTag & x"82",
IOPortTag & x"01" & PWMTag & x"83",
IOPortTag & x"00" & PWMTag & x"83",
IOPortTag & x"03" & QCountTag & x"02",
IOPortTag & x"03" & QCountTag & x"01",
IOPortTag & x"02" & QCountTag & x"02",
IOPortTag & x"02" & QCountTag & x"01",
IOPortTag & x"03" & QCountTag & x"03",
IOPortTag & x"02" & QCountTag & x"03",
IOPortTag & x"03" & PWMTag & x"81",
IOPortTag & x"02" & PWMTag & x"81",
IOPortTag & x"03" & PWMTag & x"82",
IOPortTag & x"02" & PWMTag & x"82",
IOPortTag & x"03" & PWMTag & x"83",
IOPortTag & x"02" & PWMTag & x"83",
IOPortTag & x"05" & QCountTag & x"02",
IOPortTag & x"05" & QCountTag & x"01",
IOPortTag & x"04" & QCountTag & x"02",
IOPortTag & x"04" & QCountTag & x"01",
IOPortTag & x"05" & QCountTag & x"03",
IOPortTag & x"04" & QCountTag & x"03",
IOPortTag & x"05" & PWMTag & x"81",
IOPortTag & x"04" & PWMTag & x"81",
IOPortTag & x"05" & PWMTag & x"82",
IOPortTag & x"04" & PWMTag & x"82",
IOPortTag & x"05" & PWMTag & x"83",
IOPortTag & x"04" & PWMTag & x"83",
IOPortTag & x"07" & QCountTag & x"02",
IOPortTag & x"07" & QCountTag & x"01",
IOPortTag & x"06" & QCountTag & x"02",
IOPortTag & x"06" & QCountTag & x"01",
IOPortTag & x"07" & QCountTag & x"03",
IOPortTag & x"06" & QCountTag & x"03",
IOPortTag & x"07" & PWMTag & x"81",
IOPortTag & x"06" & PWMTag & x"81",
IOPortTag & x"07" & PWMTag & x"82",
IOPortTag & x"06" & PWMTag & x"82",
IOPortTag & x"07" & PWMTag & x"83",
IOPortTag & x"06" & PWMTag & x"83",
IOPortTag & x"00" & StepGenTag & x"81",
IOPortTag & x"00" & StepGenTag & x"82",
IOPortTag & x"01" & StepGenTag & x"81",
IOPortTag & x"01" & StepGenTag & x"82",
IOPortTag & x"02" & StepGenTag & x"81",
IOPortTag & x"02" & StepGenTag & x"82",
IOPortTag & x"03" & StepGenTag & x"81",
IOPortTag & x"03" & StepGenTag & x"82",
IOPortTag & x"04" & StepGenTag & x"81",
IOPortTag & x"04" & StepGenTag & x"82",
IOPortTag & x"05" & StepGenTag & x"81",
IOPortTag & x"05" & StepGenTag & x"82",
IOPortTag & x"06" & StepGenTag & x"81",
IOPortTag & x"06" & StepGenTag & x"82",
IOPortTag & x"07" & StepGenTag & x"81",
IOPortTag & x"07" & StepGenTag & x"82",
IOPortTag & x"08" & StepGenTag & x"81",
IOPortTag & x"08" & StepGenTag & x"82",
IOPortTag & x"09" & StepGenTag & x"81",
IOPortTag & x"09" & StepGenTag & x"82",
IOPortTag & x"0A" & StepGenTag & x"81",
IOPortTag & x"0A" & StepGenTag & x"82",
IOPortTag & x"0B" & StepGenTag & x"81",
IOPortTag & x"0B" & StepGenTag & x"82",
IOPortTag & x"00" & SPITag & x"81",
IOPortTag & x"00" & SPITag & x"82",
IOPortTag & x"00" & SPITag & x"83",
IOPortTag & x"00" & SPITag & x"04",
IOPortTag & x"01" & SPITag & x"81",
IOPortTag & x"01" & SPITag & x"82",
IOPortTag & x"01" & SPITag & x"83",
IOPortTag & x"01" & SPITag & x"04",
IOPortTag & x"02" & SPITag & x"81",
IOPortTag & x"02" & SPITag & x"82",
IOPortTag & x"02" & SPITag & x"83",
IOPortTag & x"02" & SPITag & x"04",
IOPortTag & x"03" & SPITag & x"81",
IOPortTag & x"03" & SPITag & x"82",
IOPortTag & x"03" & SPITag & x"83",
IOPortTag & x"03" & SPITag & x"04",
IOPortTag & x"04" & SPITag & x"81",
IOPortTag & x"04" & SPITag & x"82",
IOPortTag & x"04" & SPITag & x"83",
IOPortTag & x"04" & SPITag & x"04",
IOPortTag & x"05" & SPITag & x"81",
IOPortTag & x"05" & SPITag & x"82",
IOPortTag & x"05" & SPITag & x"83",
IOPortTag & x"05" & SPITag & x"04",
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin);
end package IDROMParms;
| lgpl-2.1 | 7aae25fa5e55cfde4d4d4223f1856265 | 0.590912 | 2.223427 | false | false | false | false |
EliasLuiz/TCC | Leon3/lib/gaisler/grdmac/grdmac_ahbmst.vhd | 1 | 6,128 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: grdmac_ahbmst
-- File: grdmac_ahbmst.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Modified: Andrea Gianarro - Aeroflex Gaisler AB
-- Description: Generic AHB master interface with enhanced burst support
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.config_types.all;
use grlib.config.all;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
library gaisler;
use gaisler.grdmac_pkg.all;
entity grdmac_ahbmst is
generic (
hindex : integer := 0;
hirq : integer := 0;
venid : integer := VENDOR_GAISLER;
devid : integer := 0;
version : integer := 0;
chprot : integer := 3;
incaddr : integer := 0);
port (
rst : in std_ulogic;
clk : in std_ulogic;
dmai : in grdmac_ahb_dma_in_type;
dmao : out grdmac_ahb_dma_out_type;
ahbi : in ahb_mst_in_type;
ahbo : out ahb_mst_out_type
);
end;
architecture rtl of grdmac_ahbmst is
constant hconfig : ahb_config_type := (
0 => ahb_device_reg ( venid, devid, 0, version, hirq),
others => zero32);
type reg_type is record
start : std_ulogic;
retry : std_ulogic;
grant : std_ulogic;
active : std_ulogic;
end record;
constant RESET_ALL : boolean := GRLIB_CONFIG_ARRAY(grlib_sync_reset_enable_all) = 1;
constant RES : reg_type := ('0', '0', '0', '0');
signal r, rin : reg_type;
begin
comb : process(ahbi, dmai, rst, r)
variable v : reg_type;
variable ready : std_ulogic;
variable retry : std_ulogic;
variable mexc : std_ulogic;
variable inc : std_logic_vector(5 downto 0); -- address increment
variable haddr : std_logic_vector(31 downto 0); -- AHB address
variable hwdata : std_logic_vector(AHBDW-1 downto 0); -- AHB write data
variable htrans : std_logic_vector(1 downto 0); -- transfer type
variable hwrite : std_ulogic; -- read/write
variable hburst : std_logic_vector(2 downto 0); -- burst type
variable newaddr : std_logic_vector(9 downto 0); -- next sequential address
variable hbusreq : std_ulogic; -- bus request
variable hprot : std_logic_vector(3 downto 0); -- transfer type
variable xhirq : std_logic_vector(NAHBIRQ-1 downto 0);
begin
v := r; ready := '0'; mexc := '0'; retry := '0'; inc := (others => '0');
hprot := conv_std_logic_vector(chprot, 4); -- non-cached supervisor data
xhirq := (others => '0'); xhirq(hirq) := dmai.irq;
haddr := dmai.address; hbusreq := dmai.start and not dmai.idle;
hwdata := dmai.wdata;
newaddr := dmai.address(9 downto 0);
if INCADDR > 0 then
inc(conv_integer(dmai.size)) := '1';
newaddr := haddr(9 downto 0) + inc;
end if;
if dmai.burst = '0' then hburst := HBURST_SINGLE;
else hburst := HBURST_INCR; end if;
if dmai.start = '1' then
if dmai.idle = '1' then
htrans := HTRANS_IDLE;
elsif(r.active and dmai.burst and not r.retry) = '1' then
haddr(9 downto 0) := newaddr;
if dmai.busy = '1' then htrans := HTRANS_BUSY;
else
if dmai.first_beat = '1' then htrans := HTRANS_NONSEQ;
else htrans := HTRANS_SEQ; end if;
end if;
hburst := HBURST_INCR;
else htrans := HTRANS_NONSEQ; end if;
else htrans := HTRANS_IDLE; end if;
if r.active = '1' then
if ahbi.hready = '1' then
case ahbi.hresp is
when HRESP_OKAY => ready := '1';
when HRESP_RETRY | HRESP_SPLIT=> retry := '1';
when others => ready := '1'; mexc := '1';
end case;
end if;
if ((ahbi.hresp = HRESP_RETRY) or (ahbi.hresp = HRESP_SPLIT)) then
v.retry := not ahbi.hready;
else v.retry := '0'; end if;
end if;
if r.retry = '1' then htrans := HTRANS_IDLE; end if;
v.start := '0';
if ahbi.hready = '1' then
v.grant := ahbi.hgrant(hindex);
if (htrans = HTRANS_NONSEQ) or (htrans = HTRANS_SEQ) or (htrans = HTRANS_BUSY) then
v.active := r.grant; v.start := r.grant;
else
v.active := '0';
end if;
end if;
if (not RESET_ALL) and (rst = '0') then
v.retry := RES.retry; v.active := RES.active;
end if;
rin <= v;
ahbo.haddr <= haddr;
ahbo.htrans <= htrans;
ahbo.hbusreq <= hbusreq;
ahbo.hwdata <= hwdata;
ahbo.hconfig <= hconfig;
ahbo.hlock <= '0';
ahbo.hwrite <= dmai.write;
ahbo.hsize <= dmai.size;
ahbo.hburst <= hburst;
ahbo.hprot <= hprot;
ahbo.hirq <= xhirq;
ahbo.hindex <= hindex;
dmao.start <= r.start;
dmao.active <= r.active;
dmao.ready <= ready;
dmao.mexc <= mexc;
dmao.retry <= retry;
dmao.haddr <= newaddr;
dmao.rdata <= ahbi.hrdata;
end process;
regs : process(clk)
begin
if rising_edge(clk) then
r <= rin;
if RESET_ALL and rst = '0' then
r <= RES;
end if;
end if;
end process;
end;
| gpl-3.0 | 5a2373aef6522a0e2a43eddb1b8ee72d | 0.585183 | 3.606828 | false | false | false | false |
pwsoft/fpga_examples | rtl/ttl/ttl_74151.vhd | 1 | 2,668 | -- -----------------------------------------------------------------------
--
-- Syntiac VHDL support files.
--
-- -----------------------------------------------------------------------
-- Copyright 2005-2018 by Peter Wendrich ([email protected])
-- http://www.syntiac.com
--
-- This source file is free software: you can redistribute it and/or modify
-- it under the terms of the GNU Lesser General Public License as published
-- by the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This source file is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
-- -----------------------------------------------------------------------
-- 8-input multiplexer
-- -----------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.ALL;
use work.ttl_pkg.all;
-- -----------------------------------------------------------------------
entity ttl_74151 is
generic (
latency : integer := 3
);
port (
emuclk : in std_logic;
p4 : in ttl_t; -- I0
p3 : in ttl_t; -- I1
p2 : in ttl_t; -- I2
p1 : in ttl_t; -- I3
p15 : in ttl_t; -- I4
p14 : in ttl_t; -- I5
p13 : in ttl_t; -- I6
p12 : in ttl_t; -- I7
p7 : in ttl_t; -- nEnable
p11 : in ttl_t; -- S0
p10 : in ttl_t; -- S1
p9 : in ttl_t; -- S2
p5 : out ttl_t; -- Y
p6 : out ttl_t -- nY
);
end entity;
architecture rtl of ttl_74151 is
signal p5_loc : ttl_t;
signal p6_loc : ttl_t;
begin
p5_latency_inst : entity work.ttl_latency
generic map (latency => latency)
port map (clk => emuclk, d => p5_loc, q => p5);
p6_latency_inst : entity work.ttl_latency
generic map (latency => latency)
port map (clk => emuclk, d => p6_loc, q => p6);
p5_loc <=
ZERO when is_high(p7) else
buffered(p4) when is_low(p9) and is_low(p10) and is_low(p11) else
buffered(p3) when is_low(p9) and is_low(p10) and is_high(p11) else
buffered(p2) when is_low(p9) and is_high(p10) and is_low(p11) else
buffered(p1) when is_low(p9) and is_high(p10) and is_high(p11) else
buffered(p15) when is_high(p9) and is_low(p10) and is_low(p11) else
buffered(p14) when is_high(p9) and is_low(p10) and is_high(p11) else
buffered(p13) when is_high(p9) and is_high(p10) and is_low(p11) else
buffered(p12);
p6_loc <= not(p5_loc);
end architecture;
| lgpl-2.1 | f4f771cf6a2cc621c3ed63789fb4003e | 0.570465 | 3.011287 | false | false | false | false |
EliasLuiz/TCC | Leon3/lib/techmap/maps/allclkgen.vhd | 1 | 21,578 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Package: allclkgen
-- File: allclkgen.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: Clock generator interface package
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
package allclkgen is
component clkgen_virtex2
generic (
clk_mul : integer := 1;
clk_div : integer := 1;
sdramen : integer := 0;
noclkfb : integer := 0;
pcien : integer := 0;
pcidll : integer := 0;
pcisysclk: integer := 0;
freq : integer := 25000;
clk2xen : integer := 0;
clksel : integer := 0); -- enable clock select
port (
clkin : in std_logic;
pciclkin: in std_logic;
clk : out std_logic; -- main clock
clkn : out std_logic; -- inverted main clock
clk2x : out std_logic; -- double clock
sdclk : out std_logic; -- SDRAM clock
pciclk : out std_logic; -- PCI clock
cgi : in clkgen_in_type;
cgo : out clkgen_out_type;
clk1xu : out std_ulogic; -- unscaled clock
clk2xu : out std_ulogic);
end component;
component clkgen_spartan3
generic (
clk_mul : integer := 1;
clk_div : integer := 1;
sdramen : integer := 0;
noclkfb : integer := 0;
pcien : integer := 0;
pcidll : integer := 0;
pcisysclk: integer := 0;
freq : integer := 25000;
clk2xen : integer := 0;
clksel : integer := 0); -- enable clock select
port (
clkin : in std_logic;
pciclkin: in std_logic;
clk : out std_logic; -- main clock
clkn : out std_logic; -- inverted main clock
clk2x : out std_logic; -- double clock
sdclk : out std_logic; -- SDRAM clock
pciclk : out std_logic; -- PCI clock
cgi : in clkgen_in_type;
cgo : out clkgen_out_type;
clk1xu : out std_ulogic; -- unscaled clock
clk2xu : out std_ulogic);
end component;
component clkgen_virtex5
generic (
clk_mul : integer := 1;
clk_div : integer := 1;
sdramen : integer := 0;
noclkfb : integer := 0;
pcien : integer := 0;
pcidll : integer := 0;
pcisysclk: integer := 0;
freq : integer := 25000;
clk2xen : integer := 0;
clksel : integer := 0); -- enable clock select
port (
clkin : in std_logic;
pciclkin: in std_logic;
clk : out std_logic; -- main clock
clkn : out std_logic; -- inverted main clock
clk2x : out std_logic; -- double clock
sdclk : out std_logic; -- SDRAM clock
pciclk : out std_logic; -- PCI clock
cgi : in clkgen_in_type;
cgo : out clkgen_out_type;
clk1xu : out std_ulogic; -- unscaled clock
clk2xu : out std_ulogic);
end component;
component clkgen_virtex7
generic (
clk_mul : integer := 1;
clk_div : integer := 1;
freq : integer := 25000);
port (
clkin : in std_logic;
clk : out std_logic; -- main clock
clk90 : out std_ulogic; -- main clock 90deg
clkio : out std_ulogic; -- IO ref clock
cgi : in clkgen_in_type;
cgo : out clkgen_out_type);
end component;
component clkgen_axcelerator
generic (
clk_mul : integer := 1;
clk_div : integer := 1;
sdramen : integer := 0;
sdinvclk : integer := 0;
pcien : integer := 0;
pcidll : integer := 0;
pcisysclk: integer := 0;
freq : integer := 25000);
port (
clkin : in std_logic;
pciclkin: in std_logic;
clk : out std_logic; -- main clock
clkn : out std_logic; -- inverted main clock
sdclk : out std_logic; -- SDRAM clock
pciclk : out std_logic; -- PCI clock
cgi : in clkgen_in_type;
cgo : out clkgen_out_type);
end component;
component clkgen_altera_mf
generic (
clk_mul : integer := 1;
clk_div : integer := 1;
sdramen : integer := 0;
sdinvclk : integer := 0;
pcien : integer := 0;
pcidll : integer := 0;
pcisysclk: integer := 0;
freq : integer := 25000;
clk2xen : integer := 0);
port (
clkin : in std_logic;
pciclkin: in std_logic;
clk : out std_logic; -- main clock
clkn : out std_logic; -- inverted main clock
clk2x : out std_logic; -- double clock
sdclk : out std_logic; -- SDRAM clock
pciclk : out std_logic; -- PCI clock
cgi : in clkgen_in_type;
cgo : out clkgen_out_type);
end component;
component clkgen_stratixii
generic (
clk_mul : integer := 1;
clk_div : integer := 1;
sdramen : integer := 0;
sdinvclk : integer := 0;
pcien : integer := 0;
pcidll : integer := 0;
pcisysclk: integer := 0;
freq : integer := 25000;
clk2xen : integer := 0);
port (
clkin : in std_logic;
pciclkin: in std_logic;
clk : out std_logic; -- main clock
clkn : out std_logic; -- inverted main clock
clk2x : out std_logic; -- double clock
sdclk : out std_logic; -- SDRAM clock
pciclk : out std_logic; -- PCI clock
cgi : in clkgen_in_type;
cgo : out clkgen_out_type);
end component;
component clkgen_cycloneiii
generic (
clk_mul : integer := 1;
clk_div : integer := 1;
sdramen : integer := 0;
sdinvclk : integer := 0;
pcien : integer := 0;
pcidll : integer := 0;
pcisysclk: integer := 0;
freq : integer := 25000;
clk2xen : integer := 0);
port (
clkin : in std_logic;
pciclkin: in std_logic;
clk : out std_logic; -- main clock
clkn : out std_logic; -- inverted main clock
clk2x : out std_logic; -- double clock
sdclk : out std_logic; -- SDRAM clock
pciclk : out std_logic; -- PCI clock
cgi : in clkgen_in_type;
cgo : out clkgen_out_type);
end component;
component clkgen_stratixiii
generic (
clk_mul : integer := 1;
clk_div : integer := 1;
sdramen : integer := 0;
sdinvclk : integer := 0;
pcien : integer := 0;
pcidll : integer := 0;
pcisysclk: integer := 0;
freq : integer := 25000;
clk2xen : integer := 0);
port (
clkin : in std_logic;
pciclkin: in std_logic;
clk : out std_logic; -- main clock
clkn : out std_logic; -- inverted main clock
clk2x : out std_logic; -- double clock
sdclk : out std_logic; -- SDRAM clock
pciclk : out std_logic; -- PCI clock
cgi : in clkgen_in_type;
cgo : out clkgen_out_type);
end component;
component clkgen_rh_lib18t
generic (
clk_mul : integer := 1;
clk_div : integer := 1);
port (
rst : in std_logic;
clkin : in std_logic;
clk : out std_logic;
sdclk : out std_logic; -- SDRAM clock
clk2x : out std_logic;
clk4x : out std_logic
);
end component;
component clkmul_virtex2
generic ( clk_mul : integer := 2 ; clk_div : integer := 2);
port (
resetin : in std_logic;
clkin : in std_logic;
clk : out std_logic;
resetout: out std_logic
);
end component;
component clkand_unisim
port(
i : in std_ulogic;
en : in std_ulogic;
o : out std_ulogic
);
end component;
component clkand_ut025crh
port(
i : in std_ulogic;
en : in std_ulogic;
o : out std_ulogic
);
end component;
component clkand_ut130hbd
port(
i : in std_ulogic;
en : in std_ulogic;
o : out std_ulogic;
tsten : in std_ulogic
);
end component;
component clkand_ut90nhbd
port(
i : in std_ulogic;
en : in std_ulogic;
o : out std_ulogic;
tsten : in std_ulogic
);
end component;
component clkrand_ut130hbd
port(
i : in std_ulogic;
en : in std_ulogic;
o : out std_ulogic
);
end component;
component clkand_rh_lib18t
port(
i : in std_ulogic;
en : in std_ulogic;
o : out std_ulogic;
tsten : in std_ulogic
);
end component;
component clkmux_unisim
port(
i0, i1 : in std_ulogic;
sel : in std_ulogic;
o : out std_ulogic
);
end component;
component clkmux_ut130hbd
port(
i0, i1 : in std_ulogic;
sel : in std_ulogic;
o : out std_ulogic
);
end component;
component clkmux_ut90nhbd
port(
i0, i1 : in std_ulogic;
sel : in std_ulogic;
o : out std_ulogic
);
end component;
component clkmux_fusion
port(
i0, i1 : in std_ulogic;
sel : in std_ulogic;
o : out std_ulogic
);
end component;
component altera_pll
generic (
clk_mul : integer := 1;
clk_div : integer := 1;
clk_freq : integer := 25000;
clk2xen : integer := 0;
sdramen : integer := 0
);
port (
inclk0 : in std_ulogic;
c0 : out std_ulogic;
c0_2x : out std_ulogic;
e0 : out std_ulogic;
locked : out std_ulogic);
end component;
component clkgen_proasic3
generic (
clk_mul : integer := 1;
clk_div : integer := 1;
clk_odiv : integer := 1; -- output divider
pcien : integer := 0;
pcisysclk: integer := 0;
freq : integer := 25000; -- clock frequency in KHz
clkb_odiv: integer := 0;
clkc_odiv: integer := 0);
port (
clkin : in std_ulogic;
pciclkin: in std_ulogic;
clk : out std_ulogic; -- main clock
sdclk : out std_ulogic; -- SDRAM clock
pciclk : out std_ulogic;
cgi : in clkgen_in_type;
cgo : out clkgen_out_type;
clkb : out std_logic;
clkc : out std_logic);
end component;
component clkgen_fusion
generic (
clk_mul : integer := 1;
clk_div : integer := 1;
clk_odiv : integer := 1; -- output divider
pcien : integer := 0;
pcisysclk: integer := 0;
freq : integer := 25000; -- clock frequency in KHz
clkb_odiv: integer := 0;
clkc_odiv: integer := 0);
port (
clkin : in std_ulogic;
pciclkin: in std_ulogic;
clk : out std_ulogic; -- main clock
sdclk : out std_ulogic; -- SDRAM clock
pciclk : out std_ulogic;
cgi : in clkgen_in_type;
cgo : out clkgen_out_type;
clkb : out std_logic;
clkc : out std_logic);
end component;
component clkgen_proasic3e
generic (
clk_mul : integer := 1;
clk_div : integer := 1;
clk_odiv : integer := 1; -- output divider
pcien : integer := 0;
pcisysclk: integer := 0;
freq : integer := 25000; -- clock frequency in KHz
clkb_odiv: integer := 0;
clkc_odiv: integer := 0);
port (
clkin : in std_ulogic;
pciclkin: in std_ulogic;
clk : out std_ulogic; -- main clock
sdclk : out std_ulogic; -- SDRAM clock
pciclk : out std_ulogic;
cgi : in clkgen_in_type;
cgo : out clkgen_out_type;
clkb : out std_logic;
clkc : out std_logic);
end component;
component clkgen_proasic3l
generic (
clk_mul : integer := 1;
clk_div : integer := 1;
clk_odiv : integer := 1; -- output divider
pcien : integer := 0;
pcisysclk: integer := 0;
freq : integer := 25000; -- clock frequency in KHz
clkb_odiv: integer := 0;
clkc_odiv: integer := 0);
port (
clkin : in std_ulogic;
pciclkin: in std_ulogic;
clk : out std_ulogic; -- main clock
sdclk : out std_ulogic; -- SDRAM clock
pciclk : out std_ulogic;
cgi : in clkgen_in_type;
cgo : out clkgen_out_type;
clkb : out std_logic;
clkc : out std_logic);
end component;
component cyclone3_pll is
generic (
clk_mul : integer := 1;
clk_div : integer := 1;
clk_freq : integer := 25000;
clk2xen : integer := 0;
sdramen : integer := 0
);
port (
inclk0 : in std_ulogic;
c0 : out std_ulogic;
c0_2x : out std_ulogic;
e0 : out std_ulogic;
locked : out std_ulogic);
end component;
component stratix3_pll
generic (
clk_mul : integer := 1;
clk_div : integer := 1;
clk_freq : integer := 25000;
clk2xen : integer := 0;
sdramen : integer := 0
);
port (
inclk0 : in std_ulogic;
c0 : out std_ulogic;
c0_2x : out std_ulogic;
e0 : out std_ulogic;
locked : out std_ulogic);
end component;
component clkgen_rhumc
port (
clkin : in std_logic;
clk : out std_logic; -- main clock
clk2x : out std_logic; -- 2x clock
sdclk : out std_logic; -- SDRAM clock
pciclk : out std_logic; -- PCI clock
cgi : in clkgen_in_type;
cgo : out clkgen_out_type;
clk4x : out std_logic; -- 4x clock
clk1xu : out std_logic; -- unscaled 1X clock
clk2xu : out std_logic -- unscaled 2X clock
);
end component;
component clkinv_saed32
port(
i : in std_ulogic;
o : out std_ulogic);
end component;
component clkand_saed32
port(
i : in std_ulogic;
en : in std_ulogic;
o : out std_ulogic;
tsten : in std_ulogic := '0'
);
end component;
component clkmux_saed32
port (
i0, i1 : in std_ulogic;
sel : in std_ulogic;
o : out std_ulogic);
end component;
component clkgen_saed32
port (
clkin : in std_logic;
clk : out std_logic; -- main clock
clk2x : out std_logic; -- 2x clock
sdclk : out std_logic; -- SDRAM clock
pciclk : out std_logic; -- PCI clock
cgi : in clkgen_in_type;
cgo : out clkgen_out_type;
clk4x : out std_logic; -- 4x clock
clk1xu : out std_logic; -- unscaled 1X clock
clk2xu : out std_logic -- unscaled 2X clock
);
end component;
component clkinv_rhs65
port(
i : in std_ulogic;
o : out std_ulogic);
end component;
component clkand_rhs65
port(
i : in std_ulogic;
en : in std_ulogic;
o : out std_ulogic;
tsten : in std_ulogic := '0'
);
end component;
component clkmux_rhs65
port (
i0, i1 : in std_ulogic;
sel : in std_ulogic;
o : out std_ulogic);
end component;
component clkgen_rhs65
port (
clkin : in std_logic;
clk : out std_logic; -- main clock
clk2x : out std_logic; -- 2x clock
sdclk : out std_logic; -- SDRAM clock
pciclk : out std_logic; -- PCI clock
cgi : in clkgen_in_type;
cgo : out clkgen_out_type;
clk4x : out std_logic; -- 4x clock
clk1xu : out std_logic; -- unscaled 1X clock
clk2xu : out std_logic -- unscaled 2X clock
);
end component;
component clkinv_dare
port(
i : in std_ulogic;
o : out std_ulogic);
end component;
component clkand_dare
port(
i : in std_ulogic;
en : in std_ulogic;
o : out std_ulogic;
tsten : in std_ulogic := '0'
);
end component;
component clkmux_rhumc
port (
i0, i1 : in std_ulogic;
sel : in std_ulogic;
o : out std_ulogic);
end component;
component clkgen_dare
generic (
noclkfb : integer := 1
);
port (
clkin : in std_logic;
clk : out std_logic; -- main clock
clk2x : out std_logic; -- 2x clock
sdclk : out std_logic; -- SDRAM clock
pciclk : out std_logic; -- PCI clock
cgi : in clkgen_in_type;
cgo : out clkgen_out_type;
clk4x : out std_logic; -- 4x clock
clk1xu : out std_logic; -- unscaled 1X clock
clk2xu : out std_logic; -- unscaled 2X clock
clk8x : out std_logic
);
end component;
component clkgen_easic90
generic (
clk_mul : integer;
clk_div : integer;
freq : integer;
pcisysclk : integer;
pcien : integer);
port (
clkin : in std_ulogic;
pciclkin : in std_ulogic;
clk : out std_ulogic;
clk2x : out std_ulogic;
clk4x : out std_ulogic;
clkn : out std_ulogic;
lock : out std_ulogic);
end component;
component clkmux_dare
port(
i0 : in std_ulogic;
i1 : in std_ulogic;
sel : in std_ulogic;
o : out std_ulogic);
end component;
component clkmux_rhlib18t
port(
i0 : in std_ulogic;
i1 : in std_ulogic;
sel : in std_ulogic;
o : out std_ulogic);
end component;
component clkand_n2x
port(
i : in std_ulogic;
en : in std_ulogic;
o : out std_ulogic;
tsten : in std_ulogic := '0'
);
end component;
component clkmux_n2x
port (
i0, i1 : in std_ulogic;
sel : in std_ulogic;
o : out std_ulogic);
end component;
component clkgen_n2x
generic (
clk_mul : integer := 1;
clk_div : integer := 1;
sdramen : integer := 0;
noclkfb : integer := 0;
pcien : integer := 0;
pcidll : integer := 0;
pcisysclk: integer := 0;
freq : integer := 25000; -- clock frequency in KHz
clk2xen : integer := 0;
clksel : integer := 0; -- enable clock select
clk270en : integer := 0);
port (
clkin : in std_ulogic;
pciclkin: in std_ulogic;
clk : out std_ulogic; -- main clock
clkn : out std_ulogic; -- inverted main clock
clk2x : out std_ulogic; -- double clock
sdclk : out std_ulogic; -- SDRAM clock
pciclk : out std_ulogic; -- PCI clock
cgi : in clkgen_in_type;
cgo : out clkgen_out_type;
clk1xu : out std_ulogic; -- unscaled clock
clk2xu : out std_ulogic; -- unscaled 2X clock
clk270 : out std_ulogic -- clk shifted 270 degrees
);
end component;
component clkgen_ut130hbd
generic (
clk_mul : integer := 1;
clk_div : integer := 1;
sdramen : integer := 0;
noclkfb : integer := 0;
pcien : integer := 0;
pcidll : integer := 0;
pcisysclk: integer := 0;
freq : integer := 25000; -- clock frequency in KHz
clk2xen : integer := 0;
clksel : integer := 0); -- enable clock select
port (
clkin : in std_ulogic;
pciclkin: in std_ulogic;
clk : out std_ulogic; -- main clock
clkn : out std_ulogic; -- inverted main clock
clk2x : out std_ulogic; -- double clock
clk4x : out std_ulogic;
clk8x : out std_ulogic;
sdclk : out std_ulogic; -- SDRAM clock
pciclk : out std_ulogic; -- PCI clock
cgi : in clkgen_in_type;
cgo : out clkgen_out_type;
clk1xu : out std_ulogic; -- unscaled clock
clk2xu : out std_ulogic -- unscaled 2X clock
);
end component;
component clkgen_ut90nhbd is
generic (
clk_mul : integer := 1;
clk_div : integer := 1;
sdramen : integer := 0;
noclkfb : integer := 0;
pcien : integer := 0;
pcidll : integer := 0;
pcisysclk: integer := 0;
freq : integer := 25000; -- clock frequency in KHz
clk2xen : integer := 0;
clksel : integer := 0); -- enable clock select
port (
clkin : in std_ulogic;
pciclkin: in std_ulogic;
clk : out std_ulogic; -- main clock
clkn : out std_ulogic; -- inverted main clock
clk2x : out std_ulogic; -- double clock
sdclk : out std_ulogic; -- SDRAM clock
pciclk : out std_ulogic; -- PCI clock
cgi : in clkgen_in_type;
cgo : out clkgen_out_type;
clk1xu : out std_ulogic; -- unscaled clock
clk2xu : out std_ulogic -- unscaled 2X clock
);
end component;
component sim_pll is
generic (
clkmul: integer := 1;
clkdiv1: integer := 1;
clkphase1: integer := 0;
clkdiv2: integer := 1;
clkphase2: integer := 0;
clkdiv3: integer := 1;
clkphase3: integer := 0;
clkdiv4: integer := 1;
clkphase4: integer := 0;
-- Frequency limits in kHz, for checking only
minfreq: integer := 0;
maxfreq: integer := 10000000
);
port (
i: in std_logic;
o1: out std_logic;
o2: out std_logic;
o3: out std_logic;
o4: out std_logic;
lock: out std_logic;
rst: in std_logic
);
end component;
end;
| gpl-3.0 | 5511b515e3fd433ef312dd5b70c4c119 | 0.550468 | 3.344908 | false | false | false | false |
EliasLuiz/TCC | Leon3/lib/techmap/maps/leon3_net.vhd | 1 | 44,481 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
use work.gencomp.all;
entity leon3_net is
generic (
hindex : integer := 0;
fabtech : integer range 0 to NTECH := DEFFABTECH;
memtech : integer range 0 to NTECH := DEFMEMTECH;
nwindows : integer range 2 to 32 := 8;
dsu : integer range 0 to 1 := 0;
fpu : integer range 0 to 31 := 0;
v8 : integer range 0 to 63 := 0;
cp : integer range 0 to 1 := 0;
mac : integer range 0 to 1 := 0;
pclow : integer range 0 to 2 := 2;
notag : integer range 0 to 1 := 0;
nwp : integer range 0 to 4 := 0;
icen : integer range 0 to 1 := 0;
irepl : integer range 0 to 2 := 2;
isets : integer range 1 to 4 := 1;
ilinesize : integer range 4 to 8 := 4;
isetsize : integer range 1 to 256 := 1;
isetlock : integer range 0 to 1 := 0;
dcen : integer range 0 to 1 := 0;
drepl : integer range 0 to 2 := 2;
dsets : integer range 1 to 4 := 1;
dlinesize : integer range 4 to 8 := 4;
dsetsize : integer range 1 to 256 := 1;
dsetlock : integer range 0 to 1 := 0;
dsnoop : integer range 0 to 6 := 0;
ilram : integer range 0 to 1 := 0;
ilramsize : integer range 1 to 512 := 1;
ilramstart : integer range 0 to 255 := 16#8e#;
dlram : integer range 0 to 1 := 0;
dlramsize : integer range 1 to 512 := 1;
dlramstart : integer range 0 to 255 := 16#8f#;
mmuen : integer range 0 to 1 := 0;
itlbnum : integer range 2 to 64 := 8;
dtlbnum : integer range 2 to 64 := 8;
tlb_type : integer range 0 to 3 := 1;
tlb_rep : integer range 0 to 1 := 0;
lddel : integer range 1 to 2 := 2;
disas : integer range 0 to 2 := 0;
tbuf : integer range 0 to 64 := 0;
pwd : integer range 0 to 2 := 2; -- power-down
svt : integer range 0 to 1 := 1; -- single vector trapping
rstaddr : integer := 0;
smp : integer range 0 to 15 := 0; -- support SMP systems
iuft : integer range 0 to 4 := 0;
fpft : integer range 0 to 4 := 0;
cmft : integer range 0 to 1 := 0;
cached : integer := 0;
clk2x : integer := 1;
scantest : integer := 0;
mmupgsz : integer range 0 to 5 := 0;
bp : integer := 1;
npasi : integer range 0 to 1 := 0;
pwrpsr : integer range 0 to 1 := 0;
rex : integer range 0 to 1 := 0;
altwin : integer range 0 to 1 := 0
);
port (
clk : in std_ulogic; -- free-running clock
gclk2 : in std_ulogic; -- gated 2x clock
gfclk2 : in std_ulogic; -- gated 2x FPU clock
clk2 : in std_ulogic; -- free-running 2x clock
rstn : in std_ulogic;
ahbi : in ahb_mst_in_type;
ahbo : out ahb_mst_out_type;
ahbsi : in ahb_slv_in_type;
-- ahbso : in ahb_slv_out_vector;
irqi_irl: in std_logic_vector(3 downto 0);
irqi_resume: in std_ulogic;
irqi_rstrun: in std_ulogic;
irqi_rstvec: in std_logic_vector(31 downto 12);
irqi_index: in std_logic_vector(3 downto 0);
irqi_pwdsetaddr: in std_ulogic;
irqi_pwdnewaddr: in std_logic_vector(31 downto 2);
irqi_forceerr: in std_ulogic;
irqo_intack: out std_ulogic;
irqo_irl: out std_logic_vector(3 downto 0);
irqo_pwd: out std_ulogic;
irqo_fpen: out std_ulogic;
irqo_err: out std_ulogic;
dbgi_dsuen : in std_ulogic; -- DSU enable
dbgi_denable : in std_ulogic; -- diagnostic register access enablee
dbgi_dbreak : in std_ulogic; -- debug break-in
dbgi_step : in std_ulogic; -- single step
dbgi_halt : in std_ulogic; -- halt processor
dbgi_reset : in std_ulogic; -- reset processor
dbgi_dwrite : in std_ulogic; -- read/write
dbgi_daddr : in std_logic_vector(23 downto 2); -- diagnostic address
dbgi_ddata : in std_logic_vector(31 downto 0); -- diagnostic data
dbgi_btrapa : in std_ulogic; -- break on IU trap
dbgi_btrape : in std_ulogic; -- break on IU trap
dbgi_berror : in std_ulogic; -- break on IU error mode
dbgi_bwatch : in std_ulogic; -- break on IU watchpoint
dbgi_bsoft : in std_ulogic; -- break on software breakpoint (TA 1)
dbgi_tenable : in std_ulogic;
dbgi_timer : in std_logic_vector(30 downto 0);
dbgo_data : out std_logic_vector(31 downto 0);
dbgo_crdy : out std_ulogic;
dbgo_dsu : out std_ulogic;
dbgo_dsumode : out std_ulogic;
dbgo_error : out std_ulogic;
dbgo_halt : out std_ulogic;
dbgo_pwd : out std_ulogic;
dbgo_idle : out std_ulogic;
dbgo_ipend : out std_ulogic;
dbgo_icnt : out std_ulogic;
dbgo_fcnt : out std_ulogic;
dbgo_optype : out std_logic_vector(5 downto 0); -- instruction type
dbgo_bpmiss : out std_ulogic; -- branch predict miss
dbgo_istat_cmiss : out std_ulogic;
dbgo_istat_tmiss : out std_ulogic;
dbgo_istat_chold : out std_ulogic;
dbgo_istat_mhold : out std_ulogic;
dbgo_dstat_cmiss : out std_ulogic;
dbgo_dstat_tmiss : out std_ulogic;
dbgo_dstat_chold : out std_ulogic;
dbgo_dstat_mhold : out std_ulogic;
dbgo_wbhold : out std_ulogic; -- write buffer hold
dbgo_su : out std_ulogic;
-- fpui : out grfpu_in_type;
-- fpuo : in grfpu_out_type;
clken : in std_ulogic
);
end ;
architecture rtl of leon3_net is
signal disasen : std_ulogic;
component leon3ft_cycloneiv
generic (
hindex : integer := 0;
fabtech : integer range 0 to NTECH := DEFFABTECH;
memtech : integer range 0 to NTECH := DEFMEMTECH;
nwindows : integer range 2 to 32 := 8;
dsu : integer range 0 to 1 := 0;
fpu : integer range 0 to 31 := 0;
v8 : integer range 0 to 63 := 0;
cp : integer range 0 to 1 := 0;
mac : integer range 0 to 1 := 0;
pclow : integer range 0 to 2 := 2;
notag : integer range 0 to 1 := 0;
nwp : integer range 0 to 4 := 0;
icen : integer range 0 to 1 := 0;
irepl : integer range 0 to 2 := 2;
isets : integer range 1 to 4 := 1;
ilinesize : integer range 4 to 8 := 4;
isetsize : integer range 1 to 256 := 1;
isetlock : integer range 0 to 1 := 0;
dcen : integer range 0 to 1 := 0;
drepl : integer range 0 to 2 := 2;
dsets : integer range 1 to 4 := 1;
dlinesize : integer range 4 to 8 := 4;
dsetsize : integer range 1 to 256 := 1;
dsetlock : integer range 0 to 1 := 0;
dsnoop : integer range 0 to 6 := 0;
ilram : integer range 0 to 1 := 0;
ilramsize : integer range 1 to 512 := 1;
ilramstart : integer range 0 to 255 := 16#8e#;
dlram : integer range 0 to 1 := 0;
dlramsize : integer range 1 to 512 := 1;
dlramstart : integer range 0 to 255 := 16#8f#;
mmuen : integer range 0 to 1 := 0;
itlbnum : integer range 2 to 64 := 8;
dtlbnum : integer range 2 to 64 := 8;
tlb_type : integer range 0 to 3 := 1;
tlb_rep : integer range 0 to 1 := 0;
lddel : integer range 1 to 2 := 2;
disas : integer range 0 to 2 := 0;
tbuf : integer range 0 to 64 := 0;
pwd : integer range 0 to 2 := 2; -- power-down
svt : integer range 0 to 1 := 1; -- single vector trapping
rstaddr : integer := 0;
smp : integer range 0 to 15 := 0; -- support SMP systems
iuft : integer range 0 to 4 := 0;
fpft : integer range 0 to 4 := 0;
cmft : integer range 0 to 1 := 0;
cached : integer := 0;
scantest : integer := 0;
mmupgsz : integer range 0 to 5 := 0;
bp : integer := 1;
npasi : integer range 0 to 1 := 0;
pwrpsr : integer range 0 to 1 := 0
);
port (
clk : in std_ulogic; -- free-running clock
gclk2 : in std_ulogic; -- gated 2x clock
gfclk2 : in std_ulogic; -- gated 2x FPU clock
clk2 : in std_ulogic; -- free-running 2x clock
rstn : in std_ulogic;
ahbi_hgrant: in std_logic_vector(0 to NAHBMST-1); -- bus grant
ahbi_hready: in std_ulogic; -- transfer done
ahbi_hresp: in std_logic_vector(1 downto 0); -- response type
ahbi_hrdata: in std_logic_vector(31 downto 0); -- read data bus
ahbi_hirq: in std_logic_vector(NAHBIRQ-1 downto 0); -- interrupt result bus
ahbi_testen: in std_ulogic;
ahbi_testrst: in std_ulogic;
ahbi_scanen: in std_ulogic;
ahbi_testoen: in std_ulogic;
ahbo_hbusreq: out std_ulogic; -- bus request
ahbo_hlock: out std_ulogic; -- lock request
ahbo_htrans: out std_logic_vector(1 downto 0); -- transfer type
ahbo_haddr: out std_logic_vector(31 downto 0); -- address bus (byte)
ahbo_hwrite: out std_ulogic; -- read/write
ahbo_hsize: out std_logic_vector(2 downto 0); -- transfer size
ahbo_hburst: out std_logic_vector(2 downto 0); -- burst type
ahbo_hprot: out std_logic_vector(3 downto 0); -- protection control
ahbo_hwdata: out std_logic_vector(31 downto 0); -- write data bus
ahbo_hirq: out std_logic_vector(NAHBIRQ-1 downto 0); -- interrupt bus
ahbsi_hsel: in std_logic_vector(0 to NAHBSLV-1); -- slave select
ahbsi_haddr: in std_logic_vector(31 downto 0); -- address bus (byte)
ahbsi_hwrite: in std_ulogic; -- read/write
ahbsi_htrans: in std_logic_vector(1 downto 0); -- transfer type
ahbsi_hsize: in std_logic_vector(2 downto 0); -- transfer size
ahbsi_hburst: in std_logic_vector(2 downto 0); -- burst type
ahbsi_hwdata: in std_logic_vector(31 downto 0); -- write data bus
ahbsi_hprot: in std_logic_vector(3 downto 0); -- protection control
ahbsi_hready: in std_ulogic; -- transfer done
ahbsi_hmaster: in std_logic_vector(3 downto 0); -- current master
ahbsi_hmastlock: in std_ulogic; -- locked access
ahbsi_hmbsel: in std_logic_vector(0 to NAHBAMR-1); -- memory bank select
ahbsi_hirq: in std_logic_vector(NAHBIRQ-1 downto 0); -- interrupt result bus
irqi_irl: in std_logic_vector(3 downto 0);
irqi_resume: in std_ulogic;
irqi_rstrun: in std_ulogic;
irqi_rstvec: in std_logic_vector(31 downto 12);
irqi_index: in std_logic_vector(3 downto 0);
irqi_pwdsetaddr: in std_ulogic;
irqi_pwdnewaddr: in std_logic_vector(31 downto 2);
irqi_forceerr: in std_ulogic;
irqo_intack: out std_ulogic;
irqo_irl: out std_logic_vector(3 downto 0);
irqo_pwd: out std_ulogic;
irqo_fpen: out std_ulogic;
irqo_err: out std_ulogic;
dbgi_dsuen : in std_ulogic; -- DSU enable
dbgi_denable : in std_ulogic; -- diagnostic register access enablee
dbgi_dbreak : in std_ulogic; -- debug break-in
dbgi_step : in std_ulogic; -- single step
dbgi_halt : in std_ulogic; -- halt processor
dbgi_reset : in std_ulogic; -- reset processor
dbgi_dwrite : in std_ulogic; -- read/write
dbgi_daddr : in std_logic_vector(23 downto 2); -- diagnostic address
dbgi_ddata : in std_logic_vector(31 downto 0); -- diagnostic data
dbgi_btrapa : in std_ulogic; -- break on IU trap
dbgi_btrape : in std_ulogic; -- break on IU trap
dbgi_berror : in std_ulogic; -- break on IU error mode
dbgi_bwatch : in std_ulogic; -- break on IU watchpoint
dbgi_bsoft : in std_ulogic; -- break on software breakpoint (TA 1)
dbgi_tenable : in std_ulogic;
dbgi_timer : in std_logic_vector(30 downto 0);
dbgo_data : out std_logic_vector(31 downto 0);
dbgo_crdy : out std_ulogic;
dbgo_dsu : out std_ulogic;
dbgo_dsumode : out std_ulogic;
dbgo_error : out std_ulogic;
dbgo_halt : out std_ulogic;
dbgo_pwd : out std_ulogic;
dbgo_idle : out std_ulogic;
dbgo_ipend : out std_ulogic;
dbgo_icnt : out std_ulogic;
dbgo_fcnt : out std_ulogic;
dbgo_optype : out std_logic_vector(5 downto 0); -- instruction type
dbgo_bpmiss : out std_ulogic; -- branch predict miss
dbgo_istat_cmiss : out std_ulogic;
dbgo_istat_tmiss : out std_ulogic;
dbgo_istat_chold : out std_ulogic;
dbgo_istat_mhold : out std_ulogic;
dbgo_dstat_cmiss : out std_ulogic;
dbgo_dstat_tmiss : out std_ulogic;
dbgo_dstat_chold : out std_ulogic;
dbgo_dstat_mhold : out std_ulogic;
dbgo_wbhold : out std_ulogic; -- write buffer hold
dbgo_su : out std_ulogic;
-- fpui : out grfpu_in_type;
-- fpuo : in grfpu_out_type;
clken : in std_ulogic);
end component;
signal ahbi_hgrant: std_logic_vector(0 to NAHBMST-1);
signal ahbi_hready: std_ulogic;
signal ahbi_hresp: std_logic_vector(1 downto 0);
signal ahbi_hrdata: std_logic_vector(31 downto 0);
signal ahbi_hirq: std_logic_vector(NAHBIRQ-1 downto 0);
signal ahbi_testen: std_ulogic;
signal ahbi_testrst: std_ulogic;
signal ahbi_scanen: std_ulogic;
signal ahbi_testoen: std_ulogic;
signal ahbo_hbusreq: std_ulogic;
signal ahbo_hlock: std_ulogic;
signal ahbo_htrans: std_logic_vector(1 downto 0);
signal ahbo_haddr: std_logic_vector(31 downto 0);
signal ahbo_hwrite: std_ulogic;
signal ahbo_hsize: std_logic_vector(2 downto 0);
signal ahbo_hburst: std_logic_vector(2 downto 0);
signal ahbo_hprot: std_logic_vector(3 downto 0);
signal ahbo_hwdata: std_logic_vector(31 downto 0);
signal ahbo_hirq: std_logic_vector(NAHBIRQ-1 downto 0);
signal ahbsi_hsel: std_logic_vector(0 to NAHBSLV-1);
signal ahbsi_haddr: std_logic_vector(31 downto 0);
signal ahbsi_hwrite: std_ulogic;
signal ahbsi_htrans: std_logic_vector(1 downto 0);
signal ahbsi_hsize: std_logic_vector(2 downto 0);
signal ahbsi_hburst: std_logic_vector(2 downto 0);
signal ahbsi_hwdata: std_logic_vector(31 downto 0);
signal ahbsi_hprot: std_logic_vector(3 downto 0);
signal ahbsi_hready: std_ulogic;
signal ahbsi_hmaster: std_logic_vector(3 downto 0);
signal ahbsi_hmastlock: std_ulogic;
signal ahbsi_hmbsel: std_logic_vector(0 to NAHBAMR-1);
signal ahbsi_hirq: std_logic_vector(NAHBIRQ-1 downto 0);
constant L3DI :integer := GAISLER_LEON3
;
constant hconfig : ahb_config_type := (
0 => ahb_device_reg (VENDOR_GAISLER, L3DI, 0, 3, 0),
others => zero32);
begin
disasen <= '1' when disas /= 0 else '0';
-- Plug&Play information
ahbo.hconfig <= hconfig;
ahbo.hindex <= hindex;
ax : if fabtech = axcel generate
-- pragma translate_off
assert false
report "LEON3 netlist: netlist for this technology is deprecated"
severity failure;
-- pragma translate_on
--wrp: leon3ft_axcelerator
--generic map (fpu => fpu, v8 => v8, mmuen => mmuen, isets => isets, isetsize => isetsize)
--port map(
-- clk => clk,
-- rstn => rstn,
-- ahbi_hgrant => ahbi_hgrant,
-- ahbi_hready => ahbi_hready,
-- ahbi_hresp => ahbi_hresp,
-- ahbi_hrdata => ahbi_hrdata,
-- ahbi_hirq => ahbi_hirq,
-- ahbo_hbusreq => ahbo_hbusreq,
-- ahbo_hlock => ahbo_hlock,
-- ahbo_htrans => ahbo_htrans,
-- ahbo_haddr => ahbo_haddr,
-- ahbo_hwrite => ahbo_hwrite,
-- ahbo_hsize => ahbo_hsize,
-- ahbo_hburst => ahbo_hburst,
-- ahbo_hprot => ahbo_hprot,
-- ahbo_hwdata => ahbo_hwdata,
-- ahbo_hirq => ahbo_hirq,
-- ahbsi_hsel => ahbsi_hsel,
-- ahbsi_haddr => ahbsi_haddr,
-- ahbsi_hwrite => ahbsi_hwrite,
-- ahbsi_htrans => ahbsi_htrans,
-- ahbsi_hsize => ahbsi_hsize,
-- ahbsi_hburst => ahbsi_hburst,
-- ahbsi_hwdata => ahbsi_hwdata,
-- ahbsi_hprot => ahbsi_hprot,
-- ahbsi_hready => ahbsi_hready,
-- ahbsi_hmaster => ahbsi_hmaster,
-- ahbsi_hmastlock => ahbsi_hmastlock,
-- ahbsi_hmbsel => ahbsi_hmbsel,
-- ahbsi_hirq => ahbsi_hirq,
-- irqi_irl => irqi_irl,
-- irqi_rst => irqi_rst,
-- irqi_run => irqi_run,
-- irqo_intack => irqo_intack,
-- irqo_irl => irqo_irl,
-- irqo_pwd => irqo_pwd,
-- dbgi_dsuen => dbgi_dsuen,
-- dbgi_denable => dbgi_denable,
-- dbgi_dbreak => dbgi_dbreak,
-- dbgi_step => dbgi_step,
-- dbgi_halt => dbgi_halt,
-- dbgi_reset => dbgi_reset,
-- dbgi_dwrite => dbgi_dwrite,
-- dbgi_daddr => dbgi_daddr,
-- dbgi_ddata => dbgi_ddata,
-- dbgi_btrapa => dbgi_btrapa,
-- dbgi_btrape => dbgi_btrape,
-- dbgi_berror => dbgi_berror,
-- dbgi_bwatch => dbgi_bwatch,
-- dbgi_bsoft => dbgi_bsoft,
-- dbgi_tenable => dbgi_tenable,
-- dbgi_timer => dbgi_timer,
-- dbgo_data => dbgo_data,
-- dbgo_crdy => dbgo_crdy,
-- dbgo_dsu => dbgo_dsu,
-- dbgo_dsumode => dbgo_dsumode,
-- dbgo_error => dbgo_error,
-- dbgo_halt => dbgo_halt,
-- dbgo_pwd => dbgo_pwd,
-- dbgo_idle => dbgo_idle,
-- dbgo_ipend => dbgo_ipend,
-- dbgo_icnt => dbgo_icnt,
-- disasen => disasen);
end generate;
pa3 : if (fabtech = apa3) generate
-- pragma translate_off
assert false
report "LEON3 netlist: netlist for this technology is deprecated"
severity failure;
-- pragma translate_on
--wrp: leon3ft_proasic3
-- generic map (fpu => fpu, v8 => v8, mmuen => mmuen, isets => isets, isetsize => isetsize)
-- port map(
-- clk => clk,
-- rstn => rstn,
-- ahbi_hgrant => ahbi_hgrant,
-- ahbi_hready => ahbi_hready,
-- ahbi_hresp => ahbi_hresp,
-- ahbi_hrdata => ahbi_hrdata,
-- ahbi_hirq => ahbi_hirq,
-- ahbo_hbusreq => ahbo_hbusreq,
-- ahbo_hlock => ahbo_hlock,
-- ahbo_htrans => ahbo_htrans,
-- ahbo_haddr => ahbo_haddr,
-- ahbo_hwrite => ahbo_hwrite,
-- ahbo_hsize => ahbo_hsize,
-- ahbo_hburst => ahbo_hburst,
-- ahbo_hprot => ahbo_hprot,
-- ahbo_hwdata => ahbo_hwdata,
-- ahbo_hirq => ahbo_hirq,
-- ahbsi_hsel => ahbsi_hsel,
-- ahbsi_haddr => ahbsi_haddr,
-- ahbsi_hwrite => ahbsi_hwrite,
-- ahbsi_htrans => ahbsi_htrans,
-- ahbsi_hsize => ahbsi_hsize,
-- ahbsi_hburst => ahbsi_hburst,
-- ahbsi_hwdata => ahbsi_hwdata,
-- ahbsi_hprot => ahbsi_hprot,
-- ahbsi_hready => ahbsi_hready,
-- ahbsi_hmaster => ahbsi_hmaster,
-- ahbsi_hmastlock => ahbsi_hmastlock,
-- ahbsi_hmbsel => ahbsi_hmbsel,
-- ahbsi_hirq => ahbsi_hirq,
-- irqi_irl => irqi_irl,
-- irqi_rst => irqi_rst,
-- irqi_run => irqi_run,
-- irqo_intack => irqo_intack,
-- irqo_irl => irqo_irl,
-- irqo_pwd => irqo_pwd,
-- dbgi_dsuen => dbgi_dsuen,
-- dbgi_denable => dbgi_denable,
-- dbgi_dbreak => dbgi_dbreak,
-- dbgi_step => dbgi_step,
-- dbgi_halt => dbgi_halt,
-- dbgi_reset => dbgi_reset,
-- dbgi_dwrite => dbgi_dwrite,
-- dbgi_daddr => dbgi_daddr,
-- dbgi_ddata => dbgi_ddata,
-- dbgi_btrapa => dbgi_btrapa,
-- dbgi_btrape => dbgi_btrape,
-- dbgi_berror => dbgi_berror,
-- dbgi_bwatch => dbgi_bwatch,
-- dbgi_bsoft => dbgi_bsoft,
-- dbgi_tenable => dbgi_tenable,
-- dbgi_timer => dbgi_timer,
-- dbgo_data => dbgo_data,
-- dbgo_crdy => dbgo_crdy,
-- dbgo_dsu => dbgo_dsu,
-- dbgo_dsumode => dbgo_dsumode,
-- dbgo_error => dbgo_error,
-- dbgo_halt => dbgo_halt,
-- dbgo_pwd => dbgo_pwd,
-- dbgo_idle => dbgo_idle,
-- dbgo_ipend => dbgo_ipend,
-- dbgo_icnt => dbgo_icnt,
-- disasen => disasen);
end generate;
pa3e : if (fabtech = apa3e) generate
-- pragma translate_off
assert false
report "LEON3 netlist: netlist for this technology is deprecated"
severity failure;
-- pragma translate_on
--wrp: leon3ft_proasic3e
-- generic map (fpu => fpu, v8 => v8, mmuen => mmuen, isets => isets, isetsize => isetsize)
-- port map(
-- clk => clk,
-- rstn => rstn,
-- ahbi_hgrant => ahbi_hgrant,
-- ahbi_hready => ahbi_hready,
-- ahbi_hresp => ahbi_hresp,
-- ahbi_hrdata => ahbi_hrdata,
-- ahbi_hirq => ahbi_hirq,
-- ahbo_hbusreq => ahbo_hbusreq,
-- ahbo_hlock => ahbo_hlock,
-- ahbo_htrans => ahbo_htrans,
-- ahbo_haddr => ahbo_haddr,
-- ahbo_hwrite => ahbo_hwrite,
-- ahbo_hsize => ahbo_hsize,
-- ahbo_hburst => ahbo_hburst,
-- ahbo_hprot => ahbo_hprot,
-- ahbo_hwdata => ahbo_hwdata,
-- ahbo_hirq => ahbo_hirq,
-- ahbsi_hsel => ahbsi_hsel,
-- ahbsi_haddr => ahbsi_haddr,
-- ahbsi_hwrite => ahbsi_hwrite,
-- ahbsi_htrans => ahbsi_htrans,
-- ahbsi_hsize => ahbsi_hsize,
-- ahbsi_hburst => ahbsi_hburst,
-- ahbsi_hwdata => ahbsi_hwdata,
-- ahbsi_hprot => ahbsi_hprot,
-- ahbsi_hready => ahbsi_hready,
-- ahbsi_hmaster => ahbsi_hmaster,
-- ahbsi_hmastlock => ahbsi_hmastlock,
-- ahbsi_hmbsel => ahbsi_hmbsel,
-- ahbsi_hirq => ahbsi_hirq,
-- irqi_irl => irqi_irl,
-- irqi_rst => irqi_rst,
-- irqi_run => irqi_run,
-- irqo_intack => irqo_intack,
-- irqo_irl => irqo_irl,
-- irqo_pwd => irqo_pwd,
-- dbgi_dsuen => dbgi_dsuen,
-- dbgi_denable => dbgi_denable,
-- dbgi_dbreak => dbgi_dbreak,
-- dbgi_step => dbgi_step,
-- dbgi_halt => dbgi_halt,
-- dbgi_reset => dbgi_reset,
-- dbgi_dwrite => dbgi_dwrite,
-- dbgi_daddr => dbgi_daddr,
-- dbgi_ddata => dbgi_ddata,
-- dbgi_btrapa => dbgi_btrapa,
-- dbgi_btrape => dbgi_btrape,
-- dbgi_berror => dbgi_berror,
-- dbgi_bwatch => dbgi_bwatch,
-- dbgi_bsoft => dbgi_bsoft,
-- dbgi_tenable => dbgi_tenable,
-- dbgi_timer => dbgi_timer,
-- dbgo_data => dbgo_data,
-- dbgo_crdy => dbgo_crdy,
-- dbgo_dsu => dbgo_dsu,
-- dbgo_dsumode => dbgo_dsumode,
-- dbgo_error => dbgo_error,
-- dbgo_halt => dbgo_halt,
-- dbgo_pwd => dbgo_pwd,
-- dbgo_idle => dbgo_idle,
-- dbgo_ipend => dbgo_ipend,
-- dbgo_icnt => dbgo_icnt,
-- disasen => disasen);
end generate;
pa3l : if (fabtech = apa3l) generate
-- pragma translate_off
assert false
report "LEON3 netlist: netlist for this technology is deprecated"
severity failure;
-- pragma translate_on
--wrp: leon3ft_proasic3l
-- generic map (fpu => fpu, v8 => v8, mmuen => mmuen, isets => isets, isetsize => isetsize)
-- port map(
-- clk => clk,
-- rstn => rstn,
-- ahbi_hgrant => ahbi_hgrant,
-- ahbi_hready => ahbi_hready,
-- ahbi_hresp => ahbi_hresp,
-- ahbi_hrdata => ahbi_hrdata,
-- ahbi_hirq => ahbi_hirq,
-- ahbo_hbusreq => ahbo_hbusreq,
-- ahbo_hlock => ahbo_hlock,
-- ahbo_htrans => ahbo_htrans,
-- ahbo_haddr => ahbo_haddr,
-- ahbo_hwrite => ahbo_hwrite,
-- ahbo_hsize => ahbo_hsize,
-- ahbo_hburst => ahbo_hburst,
-- ahbo_hprot => ahbo_hprot,
-- ahbo_hwdata => ahbo_hwdata,
-- ahbo_hirq => ahbo_hirq,
-- ahbsi_hsel => ahbsi_hsel,
-- ahbsi_haddr => ahbsi_haddr,
-- ahbsi_hwrite => ahbsi_hwrite,
-- ahbsi_htrans => ahbsi_htrans,
-- ahbsi_hsize => ahbsi_hsize,
-- ahbsi_hburst => ahbsi_hburst,
-- ahbsi_hwdata => ahbsi_hwdata,
-- ahbsi_hprot => ahbsi_hprot,
-- ahbsi_hready => ahbsi_hready,
-- ahbsi_hmaster => ahbsi_hmaster,
-- ahbsi_hmastlock => ahbsi_hmastlock,
-- ahbsi_hmbsel => ahbsi_hmbsel,
-- ahbsi_hirq => ahbsi_hirq,
-- irqi_irl => irqi_irl,
-- irqi_rst => irqi_rst,
-- irqi_run => irqi_run,
-- irqo_intack => irqo_intack,
-- irqo_irl => irqo_irl,
-- irqo_pwd => irqo_pwd,
-- dbgi_dsuen => dbgi_dsuen,
-- dbgi_denable => dbgi_denable,
-- dbgi_dbreak => dbgi_dbreak,
-- dbgi_step => dbgi_step,
-- dbgi_halt => dbgi_halt,
-- dbgi_reset => dbgi_reset,
-- dbgi_dwrite => dbgi_dwrite,
-- dbgi_daddr => dbgi_daddr,
-- dbgi_ddata => dbgi_ddata,
-- dbgi_btrapa => dbgi_btrapa,
-- dbgi_btrape => dbgi_btrape,
-- dbgi_berror => dbgi_berror,
-- dbgi_bwatch => dbgi_bwatch,
-- dbgi_bsoft => dbgi_bsoft,
-- dbgi_tenable => dbgi_tenable,
-- dbgi_timer => dbgi_timer,
-- dbgo_data => dbgo_data,
-- dbgo_crdy => dbgo_crdy,
-- dbgo_dsu => dbgo_dsu,
-- dbgo_dsumode => dbgo_dsumode,
-- dbgo_error => dbgo_error,
-- dbgo_halt => dbgo_halt,
-- dbgo_pwd => dbgo_pwd,
-- dbgo_idle => dbgo_idle,
-- dbgo_ipend => dbgo_ipend,
-- dbgo_icnt => dbgo_icnt,
-- disasen => disasen);
end generate;
xil : if (is_unisim(fabtech) = 1) generate
-- pragma translate_off
assert false
report "LEON3 netlist: netlist for this technology is deprecated"
severity failure;
-- pragma translate_on
--wrp: leon3ft_unisim
--generic map (fabtech => fabtech, fpu => fpu, v8 => v8, mmuen => mmuen, isets => isets, isetsize => isetsize)
--port map(
-- clk => clk,
-- rstn => rstn,
-- ahbi_hgrant => ahbi_hgrant,
-- ahbi_hready => ahbi_hready,
-- ahbi_hresp => ahbi_hresp,
-- ahbi_hrdata => ahbi_hrdata,
-- ahbi_hirq => ahbi_hirq,
-- ahbo_hbusreq => ahbo_hbusreq,
-- ahbo_hlock => ahbo_hlock,
-- ahbo_htrans => ahbo_htrans,
-- ahbo_haddr => ahbo_haddr,
-- ahbo_hwrite => ahbo_hwrite,
-- ahbo_hsize => ahbo_hsize,
-- ahbo_hburst => ahbo_hburst,
-- ahbo_hprot => ahbo_hprot,
-- ahbo_hwdata => ahbo_hwdata,
-- ahbo_hirq => ahbo_hirq,
-- ahbsi_hsel => ahbsi_hsel,
-- ahbsi_haddr => ahbsi_haddr,
-- ahbsi_hwrite => ahbsi_hwrite,
-- ahbsi_htrans => ahbsi_htrans,
-- ahbsi_hsize => ahbsi_hsize,
-- ahbsi_hburst => ahbsi_hburst,
-- ahbsi_hwdata => ahbsi_hwdata,
-- ahbsi_hprot => ahbsi_hprot,
-- ahbsi_hready => ahbsi_hready,
-- ahbsi_hmaster => ahbsi_hmaster,
-- ahbsi_hmastlock => ahbsi_hmastlock,
-- ahbsi_hmbsel => ahbsi_hmbsel,
-- ahbsi_hirq => ahbsi_hirq,
-- irqi_irl => irqi_irl,
-- irqi_rst => irqi_rst,
-- irqi_run => irqi_run,
-- irqo_intack => irqo_intack,
-- irqo_irl => irqo_irl,
-- irqo_pwd => irqo_pwd,
-- dbgi_dsuen => dbgi_dsuen,
-- dbgi_denable => dbgi_denable,
-- dbgi_dbreak => dbgi_dbreak,
-- dbgi_step => dbgi_step,
-- dbgi_halt => dbgi_halt,
-- dbgi_reset => dbgi_reset,
-- dbgi_dwrite => dbgi_dwrite,
-- dbgi_daddr => dbgi_daddr,
-- dbgi_ddata => dbgi_ddata,
-- dbgi_btrapa => dbgi_btrapa,
-- dbgi_btrape => dbgi_btrape,
-- dbgi_berror => dbgi_berror,
-- dbgi_bwatch => dbgi_bwatch,
-- dbgi_bsoft => dbgi_bsoft,
-- dbgi_tenable => dbgi_tenable,
-- dbgi_timer => dbgi_timer,
-- dbgo_data => dbgo_data,
-- dbgo_crdy => dbgo_crdy,
-- dbgo_dsu => dbgo_dsu,
-- dbgo_dsumode => dbgo_dsumode,
-- dbgo_error => dbgo_error,
-- dbgo_halt => dbgo_halt,
-- dbgo_pwd => dbgo_pwd,
-- dbgo_idle => dbgo_idle,
-- dbgo_ipend => dbgo_ipend,
-- dbgo_icnt => dbgo_icnt,
-- disasen => disasen);
end generate;
atc : if fabtech = atc18rha generate
-- pragma translate_off
assert false
report "LEON3 netlist: netlist for this technology is deprecated"
severity failure;
-- pragma translate_on
--wrp: leon3ft_atc18rha
--generic map (fpu => fpu, v8 => v8, mmuen => mmuen, isets => isets, isetsize => isetsize)
--port map(
-- clk => clk,
-- gclk => gclk2,
-- rstn => rstn,
-- ahbi_hgrant => ahbi_hgrant,
-- ahbi_hready => ahbi_hready,
-- ahbi_hresp => ahbi_hresp,
-- ahbi_hrdata => ahbi_hrdata,
-- ahbi_hirq => ahbi_hirq,
-- ahbi_testen => ahbi_testen,
-- ahbi_testrst => ahbi_testrst,
-- ahbi_scanen => ahbi_scanen,
-- ahbi_testoen => ahbi_testoen,
-- ahbo_hbusreq => ahbo_hbusreq,
-- ahbo_hlock => ahbo_hlock,
-- ahbo_htrans => ahbo_htrans,
-- ahbo_haddr => ahbo_haddr,
-- ahbo_hwrite => ahbo_hwrite,
-- ahbo_hsize => ahbo_hsize,
-- ahbo_hburst => ahbo_hburst,
-- ahbo_hprot => ahbo_hprot,
-- ahbo_hwdata => ahbo_hwdata,
-- ahbo_hirq => ahbo_hirq,
-- ahbsi_hsel => ahbsi_hsel,
-- ahbsi_haddr => ahbsi_haddr,
-- ahbsi_hwrite => ahbsi_hwrite,
-- ahbsi_htrans => ahbsi_htrans,
-- ahbsi_hsize => ahbsi_hsize,
-- ahbsi_hburst => ahbsi_hburst,
-- ahbsi_hwdata => ahbsi_hwdata,
-- ahbsi_hprot => ahbsi_hprot,
-- ahbsi_hready => ahbsi_hready,
-- ahbsi_hmaster => ahbsi_hmaster,
-- ahbsi_hmastlock => ahbsi_hmastlock,
-- ahbsi_hmbsel => ahbsi_hmbsel,
-- ahbsi_hirq => ahbsi_hirq,
-- irqi_irl => irqi_irl,
-- irqi_rst => irqi_rst,
-- irqi_run => irqi_run,
-- irqo_intack => irqo_intack,
-- irqo_irl => irqo_irl,
-- irqo_pwd => irqo_pwd,
-- dbgi_dsuen => dbgi_dsuen,
-- dbgi_denable => dbgi_denable,
-- dbgi_dbreak => dbgi_dbreak,
-- dbgi_step => dbgi_step,
-- dbgi_halt => dbgi_halt,
-- dbgi_reset => dbgi_reset,
-- dbgi_dwrite => dbgi_dwrite,
-- dbgi_daddr => dbgi_daddr,
-- dbgi_ddata => dbgi_ddata,
-- dbgi_btrapa => dbgi_btrapa,
-- dbgi_btrape => dbgi_btrape,
-- dbgi_berror => dbgi_berror,
-- dbgi_bwatch => dbgi_bwatch,
-- dbgi_bsoft => dbgi_bsoft,
-- dbgi_tenable => dbgi_tenable,
-- dbgi_timer => dbgi_timer,
-- dbgo_data => dbgo_data,
-- dbgo_crdy => dbgo_crdy,
-- dbgo_dsu => dbgo_dsu,
-- dbgo_dsumode => dbgo_dsumode,
-- dbgo_error => dbgo_error,
-- dbgo_halt => dbgo_halt,
-- dbgo_pwd => dbgo_pwd,
-- dbgo_idle => dbgo_idle,
-- dbgo_ipend => dbgo_ipend,
-- dbgo_icnt => dbgo_icnt,
-- disasen => disasen);
end generate;
cyciv : if fabtech = cyclone3 generate
wrp: leon3ft_cycloneiv
generic map (
hindex => hindex,
fabtech => fabtech,
memtech => memtech,
nwindows => nwindows,
dsu => dsu,
fpu => fpu,
v8 => v8,
cp => cp,
mac => mac,
pclow => pclow,
notag => notag,
nwp => nwp,
icen => icen,
irepl => irepl,
isets => isets,
ilinesize => ilinesize,
isetsize => isetsize,
isetlock => isetlock,
dcen => dcen,
drepl => drepl,
dsets => dsets,
dlinesize => dlinesize,
dsetsize => dsetsize,
dsetlock => dsetlock,
dsnoop => dsnoop,
ilram => ilram,
ilramsize => ilramsize,
ilramstart => ilramstart,
dlram => dlram,
dlramsize => dlramsize,
dlramstart => dlramstart,
mmuen => mmuen,
itlbnum => itlbnum,
dtlbnum => dtlbnum,
tlb_type => tlb_type,
tlb_rep => tlb_rep,
lddel => lddel,
disas => disas,
tbuf => tbuf,
pwd => pwd,
svt => svt,
rstaddr => rstaddr,
smp => smp,
iuft => iuft,
fpft => fpft,
cmft => cmft,
cached => cached,
scantest => scantest,
mmupgsz => mmupgsz,
bp => bp,
npasi => npasi,
pwrpsr => pwrpsr)
port map(
clk => clk,
gclk2 => gclk2,
gfclk2 => gfclk2,
clk2 => clk2,
rstn => rstn,
ahbi_hgrant => ahbi_hgrant,
ahbi_hready => ahbi_hready,
ahbi_hresp => ahbi_hresp,
ahbi_hrdata => ahbi_hrdata,
ahbi_hirq => ahbi_hirq,
ahbi_testen => ahbi_testen,
ahbi_testrst => ahbi_testrst,
ahbi_scanen => ahbi_scanen,
ahbi_testoen => ahbi_testoen,
ahbo_hbusreq => ahbo_hbusreq,
ahbo_hlock => ahbo_hlock,
ahbo_htrans => ahbo_htrans,
ahbo_haddr => ahbo_haddr,
ahbo_hwrite => ahbo_hwrite,
ahbo_hsize => ahbo_hsize,
ahbo_hburst => ahbo_hburst,
ahbo_hprot => ahbo_hprot,
ahbo_hwdata => ahbo_hwdata,
ahbo_hirq => ahbo_hirq,
ahbsi_hsel => ahbsi_hsel,
ahbsi_haddr => ahbsi_haddr,
ahbsi_hwrite => ahbsi_hwrite,
ahbsi_htrans => ahbsi_htrans,
ahbsi_hsize => ahbsi_hsize,
ahbsi_hburst => ahbsi_hburst,
ahbsi_hwdata => ahbsi_hwdata,
ahbsi_hprot => ahbsi_hprot,
ahbsi_hready => ahbsi_hready,
ahbsi_hmaster => ahbsi_hmaster,
ahbsi_hmastlock => ahbsi_hmastlock,
ahbsi_hmbsel => ahbsi_hmbsel,
ahbsi_hirq => ahbsi_hirq,
irqi_irl => irqi_irl,
irqi_resume => irqi_resume,
irqi_rstrun => irqi_rstrun,
irqi_rstvec => irqi_rstvec,
irqi_index => irqi_index,
irqi_pwdsetaddr => irqi_pwdsetaddr,
irqi_pwdnewaddr => irqi_pwdnewaddr,
irqi_forceerr => irqi_forceerr,
irqo_intack => irqo_intack,
irqo_irl => irqo_irl,
irqo_pwd => irqo_pwd,
irqo_fpen => irqo_fpen,
irqo_err => irqo_err,
dbgi_dsuen => dbgi_dsuen,
dbgi_denable => dbgi_denable,
dbgi_dbreak => dbgi_dbreak,
dbgi_step => dbgi_step,
dbgi_halt => dbgi_halt,
dbgi_reset => dbgi_reset,
dbgi_dwrite => dbgi_dwrite,
dbgi_daddr => dbgi_daddr,
dbgi_ddata => dbgi_ddata,
dbgi_btrapa => dbgi_btrapa,
dbgi_btrape => dbgi_btrape,
dbgi_berror => dbgi_berror,
dbgi_bwatch => dbgi_bwatch,
dbgi_bsoft => dbgi_bsoft,
dbgi_tenable => dbgi_tenable,
dbgi_timer => dbgi_timer,
dbgo_data => dbgo_data,
dbgo_crdy => dbgo_crdy,
dbgo_dsu => dbgo_dsu,
dbgo_dsumode => dbgo_dsumode,
dbgo_error => dbgo_error,
dbgo_halt => dbgo_halt,
dbgo_pwd => dbgo_pwd,
dbgo_idle => dbgo_idle,
dbgo_ipend => dbgo_ipend,
dbgo_icnt => dbgo_icnt,
dbgo_fcnt => dbgo_fcnt,
dbgo_optype => dbgo_optype,
dbgo_bpmiss => dbgo_bpmiss,
dbgo_istat_cmiss => dbgo_istat_cmiss,
dbgo_istat_tmiss => dbgo_istat_tmiss,
dbgo_istat_chold => dbgo_istat_chold,
dbgo_istat_mhold => dbgo_istat_mhold,
dbgo_dstat_cmiss => dbgo_dstat_cmiss,
dbgo_dstat_tmiss => dbgo_dstat_tmiss,
dbgo_dstat_chold => dbgo_dstat_chold,
dbgo_dstat_mhold => dbgo_dstat_mhold,
dbgo_wbhold => dbgo_wbhold,
dbgo_su => dbgo_su,
clken => clken);
end generate;
ahbi_hgrant(0) <= ahbi.hgrant(hindex);
ahbi_hgrant(1 to NAHBMST-1) <= (others => '0');
ahbi_hready <= ahbi.hready;
ahbi_hresp <= ahbi.hresp;
ahbi_hrdata <= ahbi.hrdata(31 downto 0);
ahbi_hirq <= ahbi.hirq;
ahbi_testen <= ahbi.testen;
ahbi_testrst <= ahbi.testrst;
ahbi_scanen <= ahbi.scanen;
ahbi_testoen <= ahbi.testoen;
ahbo.hbusreq <= ahbo_hbusreq;
ahbo.hlock <= ahbo_hlock;
ahbo.htrans <= ahbo_htrans;
ahbo.haddr <= ahbo_haddr;
ahbo.hwrite <= ahbo_hwrite;
ahbo.hsize <= '0' & ahbo_hsize(1 downto 0);
ahbo.hburst <= "00" & ahbo_hburst(0);
ahbo.hprot <= ahbo_hprot;
ahbo.hwdata(31 downto 0) <= ahbo_hwdata;
ahbo.hirq <= (others => '0'); --ahbo_hirq;
ahbsi_hsel <= ahbsi.hsel;
ahbsi_haddr <= ahbsi.haddr;
ahbsi_hwrite <= ahbsi.hwrite;
ahbsi_htrans <= ahbsi.htrans;
ahbsi_hsize <= ahbsi.hsize;
ahbsi_hburst <= ahbsi.hburst;
ahbsi_hwdata <= ahbsi.hwdata(31 downto 0);
ahbsi_hprot <= ahbsi.hprot;
ahbsi_hready <= ahbsi.hready;
ahbsi_hmaster <= ahbsi.hmaster;
ahbsi_hmastlock <= ahbsi.hmastlock;
ahbsi_hmbsel <= ahbsi.hmbsel;
ahbsi_hirq <= ahbsi.hirq;
-- pragma translate_off
assert NAHBSLV=16
report "LEON3 netlist: Only NAHBSLV=16 supported by wrapper"
severity Failure;
-- pragma translate_on
end architecture;
| gpl-3.0 | ae4cca56d150fa0fe896642efff3c3f3 | 0.477552 | 3.860193 | false | false | false | false |
hoglet67/CoPro6502 | src/T80/T80_MCode.vhd | 1 | 55,674 | -- ****
-- T80(b) core. In an effort to merge and maintain bug fixes ....
--
--
-- Ver 303 add undocumented DDCB and FDCB opcodes by TobiFlex 20.04.2010
-- Ver 302 fixed IO cycle timing, tested thanks to Alessandro.
-- Ver 300 started tidyup
-- MikeJ March 2005
-- Latest version from www.fpgaarcade.com (original www.opencores.org)
--
-- ****
--
-- Z80 compatible microprocessor core
--
-- Version : 0242
--
-- Copyright (c) 2001-2002 Daniel Wallner ([email protected])
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
-- http://www.opencores.org/cvsweb.shtml/t80/
--
-- Limitations :
--
-- File history :
--
-- 0208 : First complete release
--
-- 0211 : Fixed IM 1
--
-- 0214 : Fixed mostly flags, only the block instructions now fail the zex regression test
--
-- 0235 : Added IM 2 fix by Mike Johnson
--
-- 0238 : Added NoRead signal
--
-- 0238b: Fixed instruction timing for POP and DJNZ
--
-- 0240 : Added (IX/IY+d) states, removed op-codes from mode 2 and added all remaining mode 3 op-codes
-- 0240mj1 fix for HL inc/dec for INI, IND, INIR, INDR, OUTI, OUTD, OTIR, OTDR
--
-- 0242 : Fixed I/O instruction timing, cleanup
--
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.T80_Pack.all;
entity T80_MCode is
generic(
Mode : integer := 0;
Flag_C : integer := 0;
Flag_N : integer := 1;
Flag_P : integer := 2;
Flag_X : integer := 3;
Flag_H : integer := 4;
Flag_Y : integer := 5;
Flag_Z : integer := 6;
Flag_S : integer := 7
);
port(
IR : in std_logic_vector(7 downto 0);
ISet : in std_logic_vector(1 downto 0);
MCycle : in std_logic_vector(2 downto 0);
F : in std_logic_vector(7 downto 0);
NMICycle : in std_logic;
IntCycle : in std_logic;
XY_State : in std_logic_vector(1 downto 0);
MCycles : out std_logic_vector(2 downto 0);
TStates : out std_logic_vector(2 downto 0);
Prefix : out std_logic_vector(1 downto 0); -- None,CB,ED,DD/FD
Inc_PC : out std_logic;
Inc_WZ : out std_logic;
IncDec_16 : out std_logic_vector(3 downto 0); -- BC,DE,HL,SP 0 is inc
Read_To_Reg : out std_logic;
Read_To_Acc : out std_logic;
Set_BusA_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI/DB,A,SP(L),SP(M),0,F
Set_BusB_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI,A,SP(L),SP(M),1,F,PC(L),PC(M),0
ALU_Op : out std_logic_vector(3 downto 0);
-- ADD, ADC, SUB, SBC, AND, XOR, OR, CP, ROT, BIT, SET, RES, DAA, RLD, RRD, None
Save_ALU : out std_logic;
PreserveC : out std_logic;
Arith16 : out std_logic;
Set_Addr_To : out std_logic_vector(2 downto 0); -- aNone,aXY,aIOA,aSP,aBC,aDE,aZI
IORQ : out std_logic;
Jump : out std_logic;
JumpE : out std_logic;
JumpXY : out std_logic;
Call : out std_logic;
RstP : out std_logic;
LDZ : out std_logic;
LDW : out std_logic;
LDSPHL : out std_logic;
Special_LD : out std_logic_vector(2 downto 0); -- A,I;A,R;I,A;R,A;None
ExchangeDH : out std_logic;
ExchangeRp : out std_logic;
ExchangeAF : out std_logic;
ExchangeRS : out std_logic;
I_DJNZ : out std_logic;
I_CPL : out std_logic;
I_CCF : out std_logic;
I_SCF : out std_logic;
I_RETN : out std_logic;
I_BT : out std_logic;
I_BC : out std_logic;
I_BTR : out std_logic;
I_RLD : out std_logic;
I_RRD : out std_logic;
I_INRC : out std_logic;
SetDI : out std_logic;
SetEI : out std_logic;
IMode : out std_logic_vector(1 downto 0);
Halt : out std_logic;
NoRead : out std_logic;
Write : out std_logic;
XYbit_undoc : out std_logic
);
end T80_MCode;
architecture rtl of T80_MCode is
function is_cc_true(
F : std_logic_vector(7 downto 0);
cc : bit_vector(2 downto 0)
) return boolean is
begin
if Mode = 3 then
case cc is
when "000" => return F(7) = '0'; -- NZ
when "001" => return F(7) = '1'; -- Z
when "010" => return F(4) = '0'; -- NC
when "011" => return F(4) = '1'; -- C
when "100" => return false;
when "101" => return false;
when "110" => return false;
when "111" => return false;
end case;
else
case cc is
when "000" => return F(6) = '0'; -- NZ
when "001" => return F(6) = '1'; -- Z
when "010" => return F(0) = '0'; -- NC
when "011" => return F(0) = '1'; -- C
when "100" => return F(2) = '0'; -- PO
when "101" => return F(2) = '1'; -- PE
when "110" => return F(7) = '0'; -- P
when "111" => return F(7) = '1'; -- M
end case;
end if;
end;
begin
process (IR, ISet, MCycle, F, NMICycle, IntCycle)
variable DDD : std_logic_vector(2 downto 0);
variable SSS : std_logic_vector(2 downto 0);
variable DPair : std_logic_vector(1 downto 0);
variable IRB : bit_vector(7 downto 0);
begin
DDD := IR(5 downto 3);
SSS := IR(2 downto 0);
DPair := IR(5 downto 4);
IRB := to_bitvector(IR);
MCycles <= "001";
if MCycle = "001" then
TStates <= "100";
else
TStates <= "011";
end if;
Prefix <= "00";
Inc_PC <= '0';
Inc_WZ <= '0';
IncDec_16 <= "0000";
Read_To_Acc <= '0';
Read_To_Reg <= '0';
Set_BusB_To <= "0000";
Set_BusA_To <= "0000";
ALU_Op <= "0" & IR(5 downto 3);
Save_ALU <= '0';
PreserveC <= '0';
Arith16 <= '0';
IORQ <= '0';
Set_Addr_To <= aNone;
Jump <= '0';
JumpE <= '0';
JumpXY <= '0';
Call <= '0';
RstP <= '0';
LDZ <= '0';
LDW <= '0';
LDSPHL <= '0';
Special_LD <= "000";
ExchangeDH <= '0';
ExchangeRp <= '0';
ExchangeAF <= '0';
ExchangeRS <= '0';
I_DJNZ <= '0';
I_CPL <= '0';
I_CCF <= '0';
I_SCF <= '0';
I_RETN <= '0';
I_BT <= '0';
I_BC <= '0';
I_BTR <= '0';
I_RLD <= '0';
I_RRD <= '0';
I_INRC <= '0';
SetDI <= '0';
SetEI <= '0';
IMode <= "11";
Halt <= '0';
NoRead <= '0';
Write <= '0';
XYbit_undoc <= '0';
case ISet is
when "00" =>
------------------------------------------------------------------------------
--
-- Unprefixed instructions
--
------------------------------------------------------------------------------
case IRB is
-- 8 BIT LOAD GROUP
when "01000000"|"01000001"|"01000010"|"01000011"|"01000100"|"01000101"|"01000111"
|"01001000"|"01001001"|"01001010"|"01001011"|"01001100"|"01001101"|"01001111"
|"01010000"|"01010001"|"01010010"|"01010011"|"01010100"|"01010101"|"01010111"
|"01011000"|"01011001"|"01011010"|"01011011"|"01011100"|"01011101"|"01011111"
|"01100000"|"01100001"|"01100010"|"01100011"|"01100100"|"01100101"|"01100111"
|"01101000"|"01101001"|"01101010"|"01101011"|"01101100"|"01101101"|"01101111"
|"01111000"|"01111001"|"01111010"|"01111011"|"01111100"|"01111101"|"01111111" =>
-- LD r,r'
Set_BusB_To(2 downto 0) <= SSS;
ExchangeRp <= '1';
Set_BusA_To(2 downto 0) <= DDD;
Read_To_Reg <= '1';
when "00000110"|"00001110"|"00010110"|"00011110"|"00100110"|"00101110"|"00111110" =>
-- LD r,n
MCycles <= "010";
case to_integer(unsigned(MCycle)) is
when 2 =>
Inc_PC <= '1';
Set_BusA_To(2 downto 0) <= DDD;
Read_To_Reg <= '1';
when others => null;
end case;
when "01000110"|"01001110"|"01010110"|"01011110"|"01100110"|"01101110"|"01111110" =>
-- LD r,(HL)
MCycles <= "010";
case to_integer(unsigned(MCycle)) is
when 1 =>
Set_Addr_To <= aXY;
when 2 =>
Set_BusA_To(2 downto 0) <= DDD;
Read_To_Reg <= '1';
when others => null;
end case;
when "01110000"|"01110001"|"01110010"|"01110011"|"01110100"|"01110101"|"01110111" =>
-- LD (HL),r
MCycles <= "010";
case to_integer(unsigned(MCycle)) is
when 1 =>
Set_Addr_To <= aXY;
Set_BusB_To(2 downto 0) <= SSS;
Set_BusB_To(3) <= '0';
when 2 =>
Write <= '1';
when others => null;
end case;
when "00110110" =>
-- LD (HL),n
MCycles <= "011";
case to_integer(unsigned(MCycle)) is
when 2 =>
Inc_PC <= '1';
Set_Addr_To <= aXY;
Set_BusB_To(2 downto 0) <= SSS;
Set_BusB_To(3) <= '0';
when 3 =>
Write <= '1';
when others => null;
end case;
when "00001010" =>
-- LD A,(BC)
MCycles <= "010";
case to_integer(unsigned(MCycle)) is
when 1 =>
Set_Addr_To <= aBC;
when 2 =>
Read_To_Acc <= '1';
when others => null;
end case;
when "00011010" =>
-- LD A,(DE)
MCycles <= "010";
case to_integer(unsigned(MCycle)) is
when 1 =>
Set_Addr_To <= aDE;
when 2 =>
Read_To_Acc <= '1';
when others => null;
end case;
when "00111010" =>
if Mode = 3 then
-- LDD A,(HL)
MCycles <= "010";
case to_integer(unsigned(MCycle)) is
when 1 =>
Set_Addr_To <= aXY;
when 2 =>
Read_To_Acc <= '1';
IncDec_16 <= "1110";
when others => null;
end case;
else
-- LD A,(nn)
MCycles <= "100";
case to_integer(unsigned(MCycle)) is
when 2 =>
Inc_PC <= '1';
LDZ <= '1';
when 3 =>
Set_Addr_To <= aZI;
Inc_PC <= '1';
when 4 =>
Read_To_Acc <= '1';
when others => null;
end case;
end if;
when "00000010" =>
-- LD (BC),A
MCycles <= "010";
case to_integer(unsigned(MCycle)) is
when 1 =>
Set_Addr_To <= aBC;
Set_BusB_To <= "0111";
when 2 =>
Write <= '1';
when others => null;
end case;
when "00010010" =>
-- LD (DE),A
MCycles <= "010";
case to_integer(unsigned(MCycle)) is
when 1 =>
Set_Addr_To <= aDE;
Set_BusB_To <= "0111";
when 2 =>
Write <= '1';
when others => null;
end case;
when "00110010" =>
if Mode = 3 then
-- LDD (HL),A
MCycles <= "010";
case to_integer(unsigned(MCycle)) is
when 1 =>
Set_Addr_To <= aXY;
Set_BusB_To <= "0111";
when 2 =>
Write <= '1';
IncDec_16 <= "1110";
when others => null;
end case;
else
-- LD (nn),A
MCycles <= "100";
case to_integer(unsigned(MCycle)) is
when 2 =>
Inc_PC <= '1';
LDZ <= '1';
when 3 =>
Set_Addr_To <= aZI;
Inc_PC <= '1';
Set_BusB_To <= "0111";
when 4 =>
Write <= '1';
when others => null;
end case;
end if;
-- 16 BIT LOAD GROUP
when "00000001"|"00010001"|"00100001"|"00110001" =>
-- LD dd,nn
MCycles <= "011";
case to_integer(unsigned(MCycle)) is
when 2 =>
Inc_PC <= '1';
Read_To_Reg <= '1';
if DPAIR = "11" then
Set_BusA_To(3 downto 0) <= "1000";
else
Set_BusA_To(2 downto 1) <= DPAIR;
Set_BusA_To(0) <= '1';
end if;
when 3 =>
Inc_PC <= '1';
Read_To_Reg <= '1';
if DPAIR = "11" then
Set_BusA_To(3 downto 0) <= "1001";
else
Set_BusA_To(2 downto 1) <= DPAIR;
Set_BusA_To(0) <= '0';
end if;
when others => null;
end case;
when "00101010" =>
if Mode = 3 then
-- LDI A,(HL)
MCycles <= "010";
case to_integer(unsigned(MCycle)) is
when 1 =>
Set_Addr_To <= aXY;
when 2 =>
Read_To_Acc <= '1';
IncDec_16 <= "0110";
when others => null;
end case;
else
-- LD HL,(nn)
MCycles <= "101";
case to_integer(unsigned(MCycle)) is
when 2 =>
Inc_PC <= '1';
LDZ <= '1';
when 3 =>
Set_Addr_To <= aZI;
Inc_PC <= '1';
LDW <= '1';
when 4 =>
Set_BusA_To(2 downto 0) <= "101"; -- L
Read_To_Reg <= '1';
Inc_WZ <= '1';
Set_Addr_To <= aZI;
when 5 =>
Set_BusA_To(2 downto 0) <= "100"; -- H
Read_To_Reg <= '1';
when others => null;
end case;
end if;
when "00100010" =>
if Mode = 3 then
-- LDI (HL),A
MCycles <= "010";
case to_integer(unsigned(MCycle)) is
when 1 =>
Set_Addr_To <= aXY;
Set_BusB_To <= "0111";
when 2 =>
Write <= '1';
IncDec_16 <= "0110";
when others => null;
end case;
else
-- LD (nn),HL
MCycles <= "101";
case to_integer(unsigned(MCycle)) is
when 2 =>
Inc_PC <= '1';
LDZ <= '1';
when 3 =>
Set_Addr_To <= aZI;
Inc_PC <= '1';
LDW <= '1';
Set_BusB_To <= "0101"; -- L
when 4 =>
Inc_WZ <= '1';
Set_Addr_To <= aZI;
Write <= '1';
Set_BusB_To <= "0100"; -- H
when 5 =>
Write <= '1';
when others => null;
end case;
end if;
when "11111001" =>
-- LD SP,HL
TStates <= "110";
LDSPHL <= '1';
when "11000101"|"11010101"|"11100101"|"11110101" =>
-- PUSH qq
MCycles <= "011";
case to_integer(unsigned(MCycle)) is
when 1 =>
TStates <= "101";
IncDec_16 <= "1111";
Set_Addr_TO <= aSP;
if DPAIR = "11" then
Set_BusB_To <= "0111";
else
Set_BusB_To(2 downto 1) <= DPAIR;
Set_BusB_To(0) <= '0';
Set_BusB_To(3) <= '0';
end if;
when 2 =>
IncDec_16 <= "1111";
Set_Addr_To <= aSP;
if DPAIR = "11" then
Set_BusB_To <= "1011";
else
Set_BusB_To(2 downto 1) <= DPAIR;
Set_BusB_To(0) <= '1';
Set_BusB_To(3) <= '0';
end if;
Write <= '1';
when 3 =>
Write <= '1';
when others => null;
end case;
when "11000001"|"11010001"|"11100001"|"11110001" =>
-- POP qq
MCycles <= "011";
case to_integer(unsigned(MCycle)) is
when 1 =>
Set_Addr_To <= aSP;
when 2 =>
IncDec_16 <= "0111";
Set_Addr_To <= aSP;
Read_To_Reg <= '1';
if DPAIR = "11" then
Set_BusA_To(3 downto 0) <= "1011";
else
Set_BusA_To(2 downto 1) <= DPAIR;
Set_BusA_To(0) <= '1';
end if;
when 3 =>
IncDec_16 <= "0111";
Read_To_Reg <= '1';
if DPAIR = "11" then
Set_BusA_To(3 downto 0) <= "0111";
else
Set_BusA_To(2 downto 1) <= DPAIR;
Set_BusA_To(0) <= '0';
end if;
when others => null;
end case;
-- EXCHANGE, BLOCK TRANSFER AND SEARCH GROUP
when "11101011" =>
if Mode /= 3 then
-- EX DE,HL
ExchangeDH <= '1';
end if;
when "00001000" =>
if Mode = 3 then
-- LD (nn),SP
MCycles <= "101";
case to_integer(unsigned(MCycle)) is
when 2 =>
Inc_PC <= '1';
LDZ <= '1';
when 3 =>
Set_Addr_To <= aZI;
Inc_PC <= '1';
LDW <= '1';
Set_BusB_To <= "1000";
when 4 =>
Inc_WZ <= '1';
Set_Addr_To <= aZI;
Write <= '1';
Set_BusB_To <= "1001";
when 5 =>
Write <= '1';
when others => null;
end case;
elsif Mode < 2 then
-- EX AF,AF'
ExchangeAF <= '1';
end if;
when "11011001" =>
if Mode = 3 then
-- RETI
MCycles <= "011";
case to_integer(unsigned(MCycle)) is
when 1 =>
Set_Addr_TO <= aSP;
when 2 =>
IncDec_16 <= "0111";
Set_Addr_To <= aSP;
LDZ <= '1';
when 3 =>
Jump <= '1';
IncDec_16 <= "0111";
--I_RETN <= '1';
SetEI <= '1';
when others => null;
end case;
elsif Mode < 2 then
-- EXX
ExchangeRS <= '1';
end if;
when "11100011" =>
if Mode /= 3 then
-- EX (SP),HL
MCycles <= "101";
case to_integer(unsigned(MCycle)) is
when 1 =>
Set_Addr_To <= aSP;
when 2 =>
Read_To_Reg <= '1';
Set_BusA_To <= "0101";
Set_BusB_To <= "0101";
Set_Addr_To <= aSP;
when 3 =>
IncDec_16 <= "0111";
Set_Addr_To <= aSP;
TStates <= "100";
Write <= '1';
when 4 =>
Read_To_Reg <= '1';
Set_BusA_To <= "0100";
Set_BusB_To <= "0100";
Set_Addr_To <= aSP;
when 5 =>
IncDec_16 <= "1111";
TStates <= "101";
Write <= '1';
when others => null;
end case;
end if;
-- 8 BIT ARITHMETIC AND LOGICAL GROUP
when "10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000111"
|"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001111"
|"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010111"
|"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011111"
|"10100000"|"10100001"|"10100010"|"10100011"|"10100100"|"10100101"|"10100111"
|"10101000"|"10101001"|"10101010"|"10101011"|"10101100"|"10101101"|"10101111"
|"10110000"|"10110001"|"10110010"|"10110011"|"10110100"|"10110101"|"10110111"
|"10111000"|"10111001"|"10111010"|"10111011"|"10111100"|"10111101"|"10111111" =>
-- ADD A,r
-- ADC A,r
-- SUB A,r
-- SBC A,r
-- AND A,r
-- OR A,r
-- XOR A,r
-- CP A,r
Set_BusB_To(2 downto 0) <= SSS;
Set_BusA_To(2 downto 0) <= "111";
Read_To_Reg <= '1';
Save_ALU <= '1';
when "10000110"|"10001110"|"10010110"|"10011110"|"10100110"|"10101110"|"10110110"|"10111110" =>
-- ADD A,(HL)
-- ADC A,(HL)
-- SUB A,(HL)
-- SBC A,(HL)
-- AND A,(HL)
-- OR A,(HL)
-- XOR A,(HL)
-- CP A,(HL)
MCycles <= "010";
case to_integer(unsigned(MCycle)) is
when 1 =>
Set_Addr_To <= aXY;
when 2 =>
Read_To_Reg <= '1';
Save_ALU <= '1';
Set_BusB_To(2 downto 0) <= SSS;
Set_BusA_To(2 downto 0) <= "111";
when others => null;
end case;
when "11000110"|"11001110"|"11010110"|"11011110"|"11100110"|"11101110"|"11110110"|"11111110" =>
-- ADD A,n
-- ADC A,n
-- SUB A,n
-- SBC A,n
-- AND A,n
-- OR A,n
-- XOR A,n
-- CP A,n
MCycles <= "010";
if MCycle = "010" then
Inc_PC <= '1';
Read_To_Reg <= '1';
Save_ALU <= '1';
Set_BusB_To(2 downto 0) <= SSS;
Set_BusA_To(2 downto 0) <= "111";
end if;
when "00000100"|"00001100"|"00010100"|"00011100"|"00100100"|"00101100"|"00111100" =>
-- INC r
Set_BusB_To <= "1010";
Set_BusA_To(2 downto 0) <= DDD;
Read_To_Reg <= '1';
Save_ALU <= '1';
PreserveC <= '1';
ALU_Op <= "0000";
when "00110100" =>
-- INC (HL)
MCycles <= "011";
case to_integer(unsigned(MCycle)) is
when 1 =>
Set_Addr_To <= aXY;
when 2 =>
TStates <= "100";
Set_Addr_To <= aXY;
Read_To_Reg <= '1';
Save_ALU <= '1';
PreserveC <= '1';
ALU_Op <= "0000";
Set_BusB_To <= "1010";
Set_BusA_To(2 downto 0) <= DDD;
when 3 =>
Write <= '1';
when others => null;
end case;
when "00000101"|"00001101"|"00010101"|"00011101"|"00100101"|"00101101"|"00111101" =>
-- DEC r
Set_BusB_To <= "1010";
Set_BusA_To(2 downto 0) <= DDD;
Read_To_Reg <= '1';
Save_ALU <= '1';
PreserveC <= '1';
ALU_Op <= "0010";
when "00110101" =>
-- DEC (HL)
MCycles <= "011";
case to_integer(unsigned(MCycle)) is
when 1 =>
Set_Addr_To <= aXY;
when 2 =>
TStates <= "100";
Set_Addr_To <= aXY;
ALU_Op <= "0010";
Read_To_Reg <= '1';
Save_ALU <= '1';
PreserveC <= '1';
Set_BusB_To <= "1010";
Set_BusA_To(2 downto 0) <= DDD;
when 3 =>
Write <= '1';
when others => null;
end case;
-- GENERAL PURPOSE ARITHMETIC AND CPU CONTROL GROUPS
when "00100111" =>
-- DAA
Set_BusA_To(2 downto 0) <= "111";
Read_To_Reg <= '1';
ALU_Op <= "1100";
Save_ALU <= '1';
when "00101111" =>
-- CPL
I_CPL <= '1';
when "00111111" =>
-- CCF
I_CCF <= '1';
when "00110111" =>
-- SCF
I_SCF <= '1';
when "00000000" =>
if NMICycle = '1' then
-- NMI
MCycles <= "011";
case to_integer(unsigned(MCycle)) is
when 1 =>
TStates <= "101";
IncDec_16 <= "1111";
Set_Addr_To <= aSP;
Set_BusB_To <= "1101";
when 2 =>
TStates <= "100";
Write <= '1';
IncDec_16 <= "1111";
Set_Addr_To <= aSP;
Set_BusB_To <= "1100";
when 3 =>
TStates <= "100";
Write <= '1';
when others => null;
end case;
elsif IntCycle = '1' then
-- INT (IM 2)
if mode = 3 then
MCycles <= "011";
else
MCycles <= "101";
end if;
case to_integer(unsigned(MCycle)) is
when 1 =>
LDZ <= '1';
TStates <= "101";
IncDec_16 <= "1111";
Set_Addr_To <= aSP;
Set_BusB_To <= "1101";
when 2 =>
TStates <= "100";
Write <= '1';
IncDec_16 <= "1111";
Set_Addr_To <= aSP;
Set_BusB_To <= "1100";
when 3 =>
TStates <= "100";
Write <= '1';
when 4 =>
Inc_PC <= '1';
LDZ <= '1';
when 5 =>
Jump <= '1';
when others => null;
end case;
else
-- NOP
end if;
when "01110110" =>
-- HALT
Halt <= '1';
when "11110011" =>
-- DI
SetDI <= '1';
when "11111011" =>
-- EI
SetEI <= '1';
-- 16 BIT ARITHMETIC GROUP
when "00001001"|"00011001"|"00101001"|"00111001" =>
-- ADD HL,ss
MCycles <= "011";
case to_integer(unsigned(MCycle)) is
when 2 =>
NoRead <= '1';
ALU_Op <= "0000";
Read_To_Reg <= '1';
Save_ALU <= '1';
Set_BusA_To(2 downto 0) <= "101";
case to_integer(unsigned(IR(5 downto 4))) is
when 0|1|2 =>
Set_BusB_To(2 downto 1) <= IR(5 downto 4);
Set_BusB_To(0) <= '1';
when others =>
Set_BusB_To <= "1000";
end case;
TStates <= "100";
Arith16 <= '1';
when 3 =>
NoRead <= '1';
Read_To_Reg <= '1';
Save_ALU <= '1';
ALU_Op <= "0001";
Set_BusA_To(2 downto 0) <= "100";
case to_integer(unsigned(IR(5 downto 4))) is
when 0|1|2 =>
Set_BusB_To(2 downto 1) <= IR(5 downto 4);
when others =>
Set_BusB_To <= "1001";
end case;
Arith16 <= '1';
when others =>
end case;
when "00000011"|"00010011"|"00100011"|"00110011" =>
-- INC ss
TStates <= "110";
IncDec_16(3 downto 2) <= "01";
IncDec_16(1 downto 0) <= DPair;
when "00001011"|"00011011"|"00101011"|"00111011" =>
-- DEC ss
TStates <= "110";
IncDec_16(3 downto 2) <= "11";
IncDec_16(1 downto 0) <= DPair;
-- ROTATE AND SHIFT GROUP
when "00000111"
-- RLCA
|"00010111"
-- RLA
|"00001111"
-- RRCA
|"00011111" =>
-- RRA
Set_BusA_To(2 downto 0) <= "111";
ALU_Op <= "1000";
Read_To_Reg <= '1';
Save_ALU <= '1';
-- JUMP GROUP
when "11000011" =>
-- JP nn
MCycles <= "011";
case to_integer(unsigned(MCycle)) is
when 2 =>
Inc_PC <= '1';
LDZ <= '1';
when 3 =>
Inc_PC <= '1';
Jump <= '1';
when others => null;
end case;
when "11000010"|"11001010"|"11010010"|"11011010"|"11100010"|"11101010"|"11110010"|"11111010" =>
if IR(5) = '1' and Mode = 3 then
case IRB(4 downto 3) is
when "00" =>
-- LD ($FF00+C),A
MCycles <= "010";
case to_integer(unsigned(MCycle)) is
when 1 =>
Set_Addr_To <= aBC;
Set_BusB_To <= "0111";
when 2 =>
Write <= '1';
IORQ <= '1';
when others =>
end case;
when "01" =>
-- LD (nn),A
MCycles <= "100";
case to_integer(unsigned(MCycle)) is
when 2 =>
Inc_PC <= '1';
LDZ <= '1';
when 3 =>
Set_Addr_To <= aZI;
Inc_PC <= '1';
Set_BusB_To <= "0111";
when 4 =>
Write <= '1';
when others => null;
end case;
when "10" =>
-- LD A,($FF00+C)
MCycles <= "010";
case to_integer(unsigned(MCycle)) is
when 1 =>
Set_Addr_To <= aBC;
when 2 =>
Read_To_Acc <= '1';
IORQ <= '1';
when others =>
end case;
when "11" =>
-- LD A,(nn)
MCycles <= "100";
case to_integer(unsigned(MCycle)) is
when 2 =>
Inc_PC <= '1';
LDZ <= '1';
when 3 =>
Set_Addr_To <= aZI;
Inc_PC <= '1';
when 4 =>
Read_To_Acc <= '1';
when others => null;
end case;
end case;
else
-- JP cc,nn
MCycles <= "011";
case to_integer(unsigned(MCycle)) is
when 2 =>
Inc_PC <= '1';
LDZ <= '1';
when 3 =>
Inc_PC <= '1';
if is_cc_true(F, to_bitvector(IR(5 downto 3))) then
Jump <= '1';
end if;
when others => null;
end case;
end if;
when "00011000" =>
if Mode /= 2 then
-- JR e
MCycles <= "011";
case to_integer(unsigned(MCycle)) is
when 2 =>
Inc_PC <= '1';
when 3 =>
NoRead <= '1';
JumpE <= '1';
TStates <= "101";
when others => null;
end case;
end if;
when "00111000" =>
if Mode /= 2 then
-- JR C,e
MCycles <= "011";
case to_integer(unsigned(MCycle)) is
when 2 =>
Inc_PC <= '1';
if F(Flag_C) = '0' then
MCycles <= "010";
end if;
when 3 =>
NoRead <= '1';
JumpE <= '1';
TStates <= "101";
when others => null;
end case;
end if;
when "00110000" =>
if Mode /= 2 then
-- JR NC,e
MCycles <= "011";
case to_integer(unsigned(MCycle)) is
when 2 =>
Inc_PC <= '1';
if F(Flag_C) = '1' then
MCycles <= "010";
end if;
when 3 =>
NoRead <= '1';
JumpE <= '1';
TStates <= "101";
when others => null;
end case;
end if;
when "00101000" =>
if Mode /= 2 then
-- JR Z,e
MCycles <= "011";
case to_integer(unsigned(MCycle)) is
when 2 =>
Inc_PC <= '1';
if F(Flag_Z) = '0' then
MCycles <= "010";
end if;
when 3 =>
NoRead <= '1';
JumpE <= '1';
TStates <= "101";
when others => null;
end case;
end if;
when "00100000" =>
if Mode /= 2 then
-- JR NZ,e
MCycles <= "011";
case to_integer(unsigned(MCycle)) is
when 2 =>
Inc_PC <= '1';
if F(Flag_Z) = '1' then
MCycles <= "010";
end if;
when 3 =>
NoRead <= '1';
JumpE <= '1';
TStates <= "101";
when others => null;
end case;
end if;
when "11101001" =>
-- JP (HL)
JumpXY <= '1';
when "00010000" =>
if Mode = 3 then
I_DJNZ <= '1';
elsif Mode < 2 then
-- DJNZ,e
MCycles <= "011";
case to_integer(unsigned(MCycle)) is
when 1 =>
TStates <= "101";
I_DJNZ <= '1';
Set_BusB_To <= "1010";
Set_BusA_To(2 downto 0) <= "000";
Read_To_Reg <= '1';
Save_ALU <= '1';
ALU_Op <= "0010";
when 2 =>
I_DJNZ <= '1';
Inc_PC <= '1';
when 3 =>
NoRead <= '1';
JumpE <= '1';
TStates <= "101";
when others => null;
end case;
end if;
-- CALL AND RETURN GROUP
when "11001101" =>
-- CALL nn
MCycles <= "101";
case to_integer(unsigned(MCycle)) is
when 2 =>
Inc_PC <= '1';
LDZ <= '1';
when 3 =>
IncDec_16 <= "1111";
Inc_PC <= '1';
TStates <= "100";
Set_Addr_To <= aSP;
LDW <= '1';
Set_BusB_To <= "1101";
when 4 =>
Write <= '1';
IncDec_16 <= "1111";
Set_Addr_To <= aSP;
Set_BusB_To <= "1100";
when 5 =>
Write <= '1';
Call <= '1';
when others => null;
end case;
when "11000100"|"11001100"|"11010100"|"11011100"|"11100100"|"11101100"|"11110100"|"11111100" =>
if IR(5) = '0' or Mode /= 3 then
-- CALL cc,nn
MCycles <= "101";
case to_integer(unsigned(MCycle)) is
when 2 =>
Inc_PC <= '1';
LDZ <= '1';
when 3 =>
Inc_PC <= '1';
LDW <= '1';
if is_cc_true(F, to_bitvector(IR(5 downto 3))) then
IncDec_16 <= "1111";
Set_Addr_TO <= aSP;
TStates <= "100";
Set_BusB_To <= "1101";
else
MCycles <= "011";
end if;
when 4 =>
Write <= '1';
IncDec_16 <= "1111";
Set_Addr_To <= aSP;
Set_BusB_To <= "1100";
when 5 =>
Write <= '1';
Call <= '1';
when others => null;
end case;
end if;
when "11001001" =>
-- RET
MCycles <= "011";
case to_integer(unsigned(MCycle)) is
when 1 =>
Set_Addr_TO <= aSP;
when 2 =>
IncDec_16 <= "0111";
Set_Addr_To <= aSP;
LDZ <= '1';
when 3 =>
Jump <= '1';
IncDec_16 <= "0111";
when others => null;
end case;
when "11000000"|"11001000"|"11010000"|"11011000"|"11100000"|"11101000"|"11110000"|"11111000" =>
if IR(5) = '1' and Mode = 3 then
case IRB(4 downto 3) is
when "00" =>
-- LD ($FF00+nn),A
MCycles <= "011";
case to_integer(unsigned(MCycle)) is
when 2 =>
Inc_PC <= '1';
Set_Addr_To <= aIOA;
Set_BusB_To <= "0111";
when 3 =>
Write <= '1';
when others => null;
end case;
when "01" =>
-- ADD SP,n
MCycles <= "011";
case to_integer(unsigned(MCycle)) is
when 2 =>
ALU_Op <= "0000";
Inc_PC <= '1';
Read_To_Reg <= '1';
Save_ALU <= '1';
Set_BusA_To <= "1000";
Set_BusB_To <= "0110";
when 3 =>
NoRead <= '1';
Read_To_Reg <= '1';
Save_ALU <= '1';
ALU_Op <= "0001";
Set_BusA_To <= "1001";
Set_BusB_To <= "1110"; -- Incorrect unsigned !!!!!!!!!!!!!!!!!!!!!
when others =>
end case;
when "10" =>
-- LD A,($FF00+nn)
MCycles <= "011";
case to_integer(unsigned(MCycle)) is
when 2 =>
Inc_PC <= '1';
Set_Addr_To <= aIOA;
when 3 =>
Read_To_Acc <= '1';
when others => null;
end case;
when "11" =>
-- LD HL,SP+n -- Not correct !!!!!!!!!!!!!!!!!!!
MCycles <= "101";
case to_integer(unsigned(MCycle)) is
when 2 =>
Inc_PC <= '1';
LDZ <= '1';
when 3 =>
Set_Addr_To <= aZI;
Inc_PC <= '1';
LDW <= '1';
when 4 =>
Set_BusA_To(2 downto 0) <= "101"; -- L
Read_To_Reg <= '1';
Inc_WZ <= '1';
Set_Addr_To <= aZI;
when 5 =>
Set_BusA_To(2 downto 0) <= "100"; -- H
Read_To_Reg <= '1';
when others => null;
end case;
end case;
else
-- RET cc
MCycles <= "011";
case to_integer(unsigned(MCycle)) is
when 1 =>
if is_cc_true(F, to_bitvector(IR(5 downto 3))) then
Set_Addr_TO <= aSP;
else
MCycles <= "001";
end if;
TStates <= "101";
when 2 =>
IncDec_16 <= "0111";
Set_Addr_To <= aSP;
LDZ <= '1';
when 3 =>
Jump <= '1';
IncDec_16 <= "0111";
when others => null;
end case;
end if;
when "11000111"|"11001111"|"11010111"|"11011111"|"11100111"|"11101111"|"11110111"|"11111111" =>
-- RST p
MCycles <= "011";
case to_integer(unsigned(MCycle)) is
when 1 =>
TStates <= "101";
IncDec_16 <= "1111";
Set_Addr_To <= aSP;
Set_BusB_To <= "1101";
when 2 =>
Write <= '1';
IncDec_16 <= "1111";
Set_Addr_To <= aSP;
Set_BusB_To <= "1100";
when 3 =>
Write <= '1';
RstP <= '1';
when others => null;
end case;
-- INPUT AND OUTPUT GROUP
when "11011011" =>
if Mode /= 3 then
-- IN A,(n)
MCycles <= "011";
case to_integer(unsigned(MCycle)) is
when 2 =>
Inc_PC <= '1';
Set_Addr_To <= aIOA;
when 3 =>
Read_To_Acc <= '1';
IORQ <= '1';
TStates <= "100"; -- MIKEJ should be 4 for IO cycle
when others => null;
end case;
end if;
when "11010011" =>
if Mode /= 3 then
-- OUT (n),A
MCycles <= "011";
case to_integer(unsigned(MCycle)) is
when 2 =>
Inc_PC <= '1';
Set_Addr_To <= aIOA;
Set_BusB_To <= "0111";
when 3 =>
Write <= '1';
IORQ <= '1';
TStates <= "100"; -- MIKEJ should be 4 for IO cycle
when others => null;
end case;
end if;
------------------------------------------------------------------------------
------------------------------------------------------------------------------
-- MULTIBYTE INSTRUCTIONS
------------------------------------------------------------------------------
------------------------------------------------------------------------------
when "11001011" =>
if Mode /= 2 then
Prefix <= "01";
end if;
when "11101101" =>
if Mode < 2 then
Prefix <= "10";
end if;
when "11011101"|"11111101" =>
if Mode < 2 then
Prefix <= "11";
end if;
end case;
when "01" =>
------------------------------------------------------------------------------
--
-- CB prefixed instructions
--
------------------------------------------------------------------------------
Set_BusA_To(2 downto 0) <= IR(2 downto 0);
Set_BusB_To(2 downto 0) <= IR(2 downto 0);
case IRB is
when "00000000"|"00000001"|"00000010"|"00000011"|"00000100"|"00000101"|"00000111"
|"00010000"|"00010001"|"00010010"|"00010011"|"00010100"|"00010101"|"00010111"
|"00001000"|"00001001"|"00001010"|"00001011"|"00001100"|"00001101"|"00001111"
|"00011000"|"00011001"|"00011010"|"00011011"|"00011100"|"00011101"|"00011111"
|"00100000"|"00100001"|"00100010"|"00100011"|"00100100"|"00100101"|"00100111"
|"00101000"|"00101001"|"00101010"|"00101011"|"00101100"|"00101101"|"00101111"
|"00110000"|"00110001"|"00110010"|"00110011"|"00110100"|"00110101"|"00110111"
|"00111000"|"00111001"|"00111010"|"00111011"|"00111100"|"00111101"|"00111111" =>
-- RLC r
-- RL r
-- RRC r
-- RR r
-- SLA r
-- SRA r
-- SRL r
-- SLL r (Undocumented) / SWAP r
if XY_State="00" then
if MCycle = "001" then
ALU_Op <= "1000";
Read_To_Reg <= '1';
Save_ALU <= '1';
end if;
else
-- R/S (IX+d),Reg, undocumented
MCycles <= "011";
XYbit_undoc <= '1';
case to_integer(unsigned(MCycle)) is
when 1 | 7=>
Set_Addr_To <= aXY;
when 2 =>
ALU_Op <= "1000";
Read_To_Reg <= '1';
Save_ALU <= '1';
Set_Addr_To <= aXY;
TStates <= "100";
when 3 =>
Write <= '1';
when others => null;
end case;
end if;
when "00000110"|"00010110"|"00001110"|"00011110"|"00101110"|"00111110"|"00100110"|"00110110" =>
-- RLC (HL)
-- RL (HL)
-- RRC (HL)
-- RR (HL)
-- SRA (HL)
-- SRL (HL)
-- SLA (HL)
-- SLL (HL) (Undocumented) / SWAP (HL)
MCycles <= "011";
case to_integer(unsigned(MCycle)) is
when 1 | 7 =>
Set_Addr_To <= aXY;
when 2 =>
ALU_Op <= "1000";
Read_To_Reg <= '1';
Save_ALU <= '1';
Set_Addr_To <= aXY;
TStates <= "100";
when 3 =>
Write <= '1';
when others =>
end case;
when "01000000"|"01000001"|"01000010"|"01000011"|"01000100"|"01000101"|"01000111"
|"01001000"|"01001001"|"01001010"|"01001011"|"01001100"|"01001101"|"01001111"
|"01010000"|"01010001"|"01010010"|"01010011"|"01010100"|"01010101"|"01010111"
|"01011000"|"01011001"|"01011010"|"01011011"|"01011100"|"01011101"|"01011111"
|"01100000"|"01100001"|"01100010"|"01100011"|"01100100"|"01100101"|"01100111"
|"01101000"|"01101001"|"01101010"|"01101011"|"01101100"|"01101101"|"01101111"
|"01110000"|"01110001"|"01110010"|"01110011"|"01110100"|"01110101"|"01110111"
|"01111000"|"01111001"|"01111010"|"01111011"|"01111100"|"01111101"|"01111111" =>
-- BIT b,r
if XY_State="00" then
if MCycle = "001" then
Set_BusB_To(2 downto 0) <= IR(2 downto 0);
ALU_Op <= "1001";
end if;
else
-- BIT b,(IX+d), undocumented
MCycles <= "010";
XYbit_undoc <= '1';
case to_integer(unsigned(MCycle)) is
when 1 | 7=>
Set_Addr_To <= aXY;
when 2 =>
ALU_Op <= "1001";
TStates <= "100";
when others => null;
end case;
end if;
when "01000110"|"01001110"|"01010110"|"01011110"|"01100110"|"01101110"|"01110110"|"01111110" =>
-- BIT b,(HL)
MCycles <= "010";
case to_integer(unsigned(MCycle)) is
when 1 | 7=>
Set_Addr_To <= aXY;
when 2 =>
ALU_Op <= "1001";
TStates <= "100";
when others => null;
end case;
when "11000000"|"11000001"|"11000010"|"11000011"|"11000100"|"11000101"|"11000111"
|"11001000"|"11001001"|"11001010"|"11001011"|"11001100"|"11001101"|"11001111"
|"11010000"|"11010001"|"11010010"|"11010011"|"11010100"|"11010101"|"11010111"
|"11011000"|"11011001"|"11011010"|"11011011"|"11011100"|"11011101"|"11011111"
|"11100000"|"11100001"|"11100010"|"11100011"|"11100100"|"11100101"|"11100111"
|"11101000"|"11101001"|"11101010"|"11101011"|"11101100"|"11101101"|"11101111"
|"11110000"|"11110001"|"11110010"|"11110011"|"11110100"|"11110101"|"11110111"
|"11111000"|"11111001"|"11111010"|"11111011"|"11111100"|"11111101"|"11111111" =>
-- SET b,r
if XY_State="00" then
if MCycle = "001" then
ALU_Op <= "1010";
Read_To_Reg <= '1';
Save_ALU <= '1';
end if;
else
-- SET b,(IX+d),Reg, undocumented
MCycles <= "011";
XYbit_undoc <= '1';
case to_integer(unsigned(MCycle)) is
when 1 | 7=>
Set_Addr_To <= aXY;
when 2 =>
ALU_Op <= "1010";
Read_To_Reg <= '1';
Save_ALU <= '1';
Set_Addr_To <= aXY;
TStates <= "100";
when 3 =>
Write <= '1';
when others => null;
end case;
end if;
when "11000110"|"11001110"|"11010110"|"11011110"|"11100110"|"11101110"|"11110110"|"11111110" =>
-- SET b,(HL)
MCycles <= "011";
case to_integer(unsigned(MCycle)) is
when 1 | 7=>
Set_Addr_To <= aXY;
when 2 =>
ALU_Op <= "1010";
Read_To_Reg <= '1';
Save_ALU <= '1';
Set_Addr_To <= aXY;
TStates <= "100";
when 3 =>
Write <= '1';
when others => null;
end case;
when "10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000111"
|"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001111"
|"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010111"
|"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011111"
|"10100000"|"10100001"|"10100010"|"10100011"|"10100100"|"10100101"|"10100111"
|"10101000"|"10101001"|"10101010"|"10101011"|"10101100"|"10101101"|"10101111"
|"10110000"|"10110001"|"10110010"|"10110011"|"10110100"|"10110101"|"10110111"
|"10111000"|"10111001"|"10111010"|"10111011"|"10111100"|"10111101"|"10111111" =>
-- RES b,r
if XY_State="00" then
if MCycle = "001" then
ALU_Op <= "1011";
Read_To_Reg <= '1';
Save_ALU <= '1';
end if;
else
-- RES b,(IX+d),Reg, undocumented
MCycles <= "011";
XYbit_undoc <= '1';
case to_integer(unsigned(MCycle)) is
when 1 | 7=>
Set_Addr_To <= aXY;
when 2 =>
ALU_Op <= "1011";
Read_To_Reg <= '1';
Save_ALU <= '1';
Set_Addr_To <= aXY;
TStates <= "100";
when 3 =>
Write <= '1';
when others => null;
end case;
end if;
when "10000110"|"10001110"|"10010110"|"10011110"|"10100110"|"10101110"|"10110110"|"10111110" =>
-- RES b,(HL)
MCycles <= "011";
case to_integer(unsigned(MCycle)) is
when 1 | 7 =>
Set_Addr_To <= aXY;
when 2 =>
ALU_Op <= "1011";
Read_To_Reg <= '1';
Save_ALU <= '1';
Set_Addr_To <= aXY;
TStates <= "100";
when 3 =>
Write <= '1';
when others => null;
end case;
end case;
when others =>
------------------------------------------------------------------------------
--
-- ED prefixed instructions
--
------------------------------------------------------------------------------
case IRB is
when "00000000"|"00000001"|"00000010"|"00000011"|"00000100"|"00000101"|"00000110"|"00000111"
|"00001000"|"00001001"|"00001010"|"00001011"|"00001100"|"00001101"|"00001110"|"00001111"
|"00010000"|"00010001"|"00010010"|"00010011"|"00010100"|"00010101"|"00010110"|"00010111"
|"00011000"|"00011001"|"00011010"|"00011011"|"00011100"|"00011101"|"00011110"|"00011111"
|"00100000"|"00100001"|"00100010"|"00100011"|"00100100"|"00100101"|"00100110"|"00100111"
|"00101000"|"00101001"|"00101010"|"00101011"|"00101100"|"00101101"|"00101110"|"00101111"
|"00110000"|"00110001"|"00110010"|"00110011"|"00110100"|"00110101"|"00110110"|"00110111"
|"00111000"|"00111001"|"00111010"|"00111011"|"00111100"|"00111101"|"00111110"|"00111111"
|"10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000110"|"10000111"
|"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001110"|"10001111"
|"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010110"|"10010111"
|"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011110"|"10011111"
| "10100100"|"10100101"|"10100110"|"10100111"
| "10101100"|"10101101"|"10101110"|"10101111"
| "10110100"|"10110101"|"10110110"|"10110111"
| "10111100"|"10111101"|"10111110"|"10111111"
|"11000000"|"11000001"|"11000010"|"11000011"|"11000100"|"11000101"|"11000110"|"11000111"
|"11001000"|"11001001"|"11001010"|"11001011"|"11001100"|"11001101"|"11001110"|"11001111"
|"11010000"|"11010001"|"11010010"|"11010011"|"11010100"|"11010101"|"11010110"|"11010111"
|"11011000"|"11011001"|"11011010"|"11011011"|"11011100"|"11011101"|"11011110"|"11011111"
|"11100000"|"11100001"|"11100010"|"11100011"|"11100100"|"11100101"|"11100110"|"11100111"
|"11101000"|"11101001"|"11101010"|"11101011"|"11101100"|"11101101"|"11101110"|"11101111"
|"11110000"|"11110001"|"11110010"|"11110011"|"11110100"|"11110101"|"11110110"|"11110111"
|"11111000"|"11111001"|"11111010"|"11111011"|"11111100"|"11111101"|"11111110"|"11111111" =>
null; -- NOP, undocumented
when "01111110"|"01111111" =>
-- NOP, undocumented
null;
-- 8 BIT LOAD GROUP
when "01010111" =>
-- LD A,I
Special_LD <= "100";
TStates <= "101";
when "01011111" =>
-- LD A,R
Special_LD <= "101";
TStates <= "101";
when "01000111" =>
-- LD I,A
Special_LD <= "110";
TStates <= "101";
when "01001111" =>
-- LD R,A
Special_LD <= "111";
TStates <= "101";
-- 16 BIT LOAD GROUP
when "01001011"|"01011011"|"01101011"|"01111011" =>
-- LD dd,(nn)
MCycles <= "101";
case to_integer(unsigned(MCycle)) is
when 2 =>
Inc_PC <= '1';
LDZ <= '1';
when 3 =>
Set_Addr_To <= aZI;
Inc_PC <= '1';
LDW <= '1';
when 4 =>
Read_To_Reg <= '1';
if IR(5 downto 4) = "11" then
Set_BusA_To <= "1000";
else
Set_BusA_To(2 downto 1) <= IR(5 downto 4);
Set_BusA_To(0) <= '1';
end if;
Inc_WZ <= '1';
Set_Addr_To <= aZI;
when 5 =>
Read_To_Reg <= '1';
if IR(5 downto 4) = "11" then
Set_BusA_To <= "1001";
else
Set_BusA_To(2 downto 1) <= IR(5 downto 4);
Set_BusA_To(0) <= '0';
end if;
when others => null;
end case;
when "01000011"|"01010011"|"01100011"|"01110011" =>
-- LD (nn),dd
MCycles <= "101";
case to_integer(unsigned(MCycle)) is
when 2 =>
Inc_PC <= '1';
LDZ <= '1';
when 3 =>
Set_Addr_To <= aZI;
Inc_PC <= '1';
LDW <= '1';
if IR(5 downto 4) = "11" then
Set_BusB_To <= "1000";
else
Set_BusB_To(2 downto 1) <= IR(5 downto 4);
Set_BusB_To(0) <= '1';
Set_BusB_To(3) <= '0';
end if;
when 4 =>
Inc_WZ <= '1';
Set_Addr_To <= aZI;
Write <= '1';
if IR(5 downto 4) = "11" then
Set_BusB_To <= "1001";
else
Set_BusB_To(2 downto 1) <= IR(5 downto 4);
Set_BusB_To(0) <= '0';
Set_BusB_To(3) <= '0';
end if;
when 5 =>
Write <= '1';
when others => null;
end case;
when "10100000" | "10101000" | "10110000" | "10111000" =>
-- LDI, LDD, LDIR, LDDR
MCycles <= "100";
case to_integer(unsigned(MCycle)) is
when 1 =>
Set_Addr_To <= aXY;
IncDec_16 <= "1100"; -- BC
when 2 =>
Set_BusB_To <= "0110";
Set_BusA_To(2 downto 0) <= "111";
ALU_Op <= "0000";
Set_Addr_To <= aDE;
if IR(3) = '0' then
IncDec_16 <= "0110"; -- IX
else
IncDec_16 <= "1110";
end if;
when 3 =>
I_BT <= '1';
TStates <= "101";
Write <= '1';
if IR(3) = '0' then
IncDec_16 <= "0101"; -- DE
else
IncDec_16 <= "1101";
end if;
when 4 =>
NoRead <= '1';
TStates <= "101";
when others => null;
end case;
when "10100001" | "10101001" | "10110001" | "10111001" =>
-- CPI, CPD, CPIR, CPDR
MCycles <= "100";
case to_integer(unsigned(MCycle)) is
when 1 =>
Set_Addr_To <= aXY;
IncDec_16 <= "1100"; -- BC
when 2 =>
Set_BusB_To <= "0110";
Set_BusA_To(2 downto 0) <= "111";
ALU_Op <= "0111";
Save_ALU <= '1';
PreserveC <= '1';
if IR(3) = '0' then
IncDec_16 <= "0110";
else
IncDec_16 <= "1110";
end if;
when 3 =>
NoRead <= '1';
I_BC <= '1';
TStates <= "101";
when 4 =>
NoRead <= '1';
TStates <= "101";
when others => null;
end case;
when "01000100"|"01001100"|"01010100"|"01011100"|"01100100"|"01101100"|"01110100"|"01111100" =>
-- NEG
Alu_OP <= "0010";
Set_BusB_To <= "0111";
Set_BusA_To <= "1010";
Read_To_Acc <= '1';
Save_ALU <= '1';
when "01000110"|"01001110"|"01100110"|"01101110" =>
-- IM 0
IMode <= "00";
when "01010110"|"01110110" =>
-- IM 1
IMode <= "01";
when "01011110"|"01110111" =>
-- IM 2
IMode <= "10";
-- 16 bit arithmetic
when "01001010"|"01011010"|"01101010"|"01111010" =>
-- ADC HL,ss
MCycles <= "011";
case to_integer(unsigned(MCycle)) is
when 2 =>
NoRead <= '1';
ALU_Op <= "0001";
Read_To_Reg <= '1';
Save_ALU <= '1';
Set_BusA_To(2 downto 0) <= "101";
case to_integer(unsigned(IR(5 downto 4))) is
when 0|1|2 =>
Set_BusB_To(2 downto 1) <= IR(5 downto 4);
Set_BusB_To(0) <= '1';
when others =>
Set_BusB_To <= "1000";
end case;
TStates <= "100";
when 3 =>
NoRead <= '1';
Read_To_Reg <= '1';
Save_ALU <= '1';
ALU_Op <= "0001";
Set_BusA_To(2 downto 0) <= "100";
case to_integer(unsigned(IR(5 downto 4))) is
when 0|1|2 =>
Set_BusB_To(2 downto 1) <= IR(5 downto 4);
Set_BusB_To(0) <= '0';
when others =>
Set_BusB_To <= "1001";
end case;
when others =>
end case;
when "01000010"|"01010010"|"01100010"|"01110010" =>
-- SBC HL,ss
MCycles <= "011";
case to_integer(unsigned(MCycle)) is
when 2 =>
NoRead <= '1';
ALU_Op <= "0011";
Read_To_Reg <= '1';
Save_ALU <= '1';
Set_BusA_To(2 downto 0) <= "101";
case to_integer(unsigned(IR(5 downto 4))) is
when 0|1|2 =>
Set_BusB_To(2 downto 1) <= IR(5 downto 4);
Set_BusB_To(0) <= '1';
when others =>
Set_BusB_To <= "1000";
end case;
TStates <= "100";
when 3 =>
NoRead <= '1';
ALU_Op <= "0011";
Read_To_Reg <= '1';
Save_ALU <= '1';
Set_BusA_To(2 downto 0) <= "100";
case to_integer(unsigned(IR(5 downto 4))) is
when 0|1|2 =>
Set_BusB_To(2 downto 1) <= IR(5 downto 4);
when others =>
Set_BusB_To <= "1001";
end case;
when others =>
end case;
when "01101111" =>
-- RLD
MCycles <= "100";
case to_integer(unsigned(MCycle)) is
when 2 =>
NoRead <= '1';
Set_Addr_To <= aXY;
when 3 =>
Read_To_Reg <= '1';
Set_BusB_To(2 downto 0) <= "110";
Set_BusA_To(2 downto 0) <= "111";
ALU_Op <= "1101";
TStates <= "100";
Set_Addr_To <= aXY;
Save_ALU <= '1';
when 4 =>
I_RLD <= '1';
Write <= '1';
when others =>
end case;
when "01100111" =>
-- RRD
MCycles <= "100";
case to_integer(unsigned(MCycle)) is
when 2 =>
Set_Addr_To <= aXY;
when 3 =>
Read_To_Reg <= '1';
Set_BusB_To(2 downto 0) <= "110";
Set_BusA_To(2 downto 0) <= "111";
ALU_Op <= "1110";
TStates <= "100";
Set_Addr_To <= aXY;
Save_ALU <= '1';
when 4 =>
I_RRD <= '1';
Write <= '1';
when others =>
end case;
when "01000101"|"01001101"|"01010101"|"01011101"|"01100101"|"01101101"|"01110101"|"01111101" =>
-- RETI, RETN
MCycles <= "011";
case to_integer(unsigned(MCycle)) is
when 1 =>
Set_Addr_TO <= aSP;
when 2 =>
IncDec_16 <= "0111";
Set_Addr_To <= aSP;
LDZ <= '1';
when 3 =>
Jump <= '1';
IncDec_16 <= "0111";
I_RETN <= '1';
when others => null;
end case;
when "01000000"|"01001000"|"01010000"|"01011000"|"01100000"|"01101000"|"01110000"|"01111000" =>
-- IN r,(C)
MCycles <= "010";
case to_integer(unsigned(MCycle)) is
when 1 =>
Set_Addr_To <= aBC;
when 2 =>
TStates <= "100"; -- MIKEJ should be 4 for IO cycle
IORQ <= '1';
if IR(5 downto 3) /= "110" then
Read_To_Reg <= '1';
Set_BusA_To(2 downto 0) <= IR(5 downto 3);
end if;
I_INRC <= '1';
when others =>
end case;
when "01000001"|"01001001"|"01010001"|"01011001"|"01100001"|"01101001"|"01110001"|"01111001" =>
-- OUT (C),r
-- OUT (C),0
MCycles <= "010";
case to_integer(unsigned(MCycle)) is
when 1 =>
Set_Addr_To <= aBC;
Set_BusB_To(2 downto 0) <= IR(5 downto 3);
if IR(5 downto 3) = "110" then
Set_BusB_To(3) <= '1';
end if;
when 2 =>
TStates <= "100"; -- MIKEJ should be 4 for IO cycle
Write <= '1';
IORQ <= '1';
when others =>
end case;
when "10100010" | "10101010" | "10110010" | "10111010" =>
-- INI, IND, INIR, INDR
-- note B is decremented AFTER being put on the bus
MCycles <= "100";
case to_integer(unsigned(MCycle)) is
when 1 =>
Set_Addr_To <= aBC;
Set_BusB_To <= "1010";
Set_BusA_To <= "0000";
Read_To_Reg <= '1';
Save_ALU <= '1';
ALU_Op <= "0010";
when 2 =>
TStates <= "100"; -- MIKEJ should be 4 for IO cycle
IORQ <= '1';
Set_BusB_To <= "0110";
Set_Addr_To <= aXY;
when 3 =>
if IR(3) = '0' then
--IncDec_16 <= "0010";
IncDec_16 <= "0110";
else
--IncDec_16 <= "1010";
IncDec_16 <= "1110";
end if;
TStates <= "100";
Write <= '1';
I_BTR <= '1';
when 4 =>
NoRead <= '1';
TStates <= "101";
when others => null;
end case;
when "10100011" | "10101011" | "10110011" | "10111011" =>
-- OUTI, OUTD, OTIR, OTDR
-- note B is decremented BEFORE being put on the bus.
-- mikej fix for hl inc
MCycles <= "100";
case to_integer(unsigned(MCycle)) is
when 1 =>
TStates <= "101";
Set_Addr_To <= aXY;
Set_BusB_To <= "1010";
Set_BusA_To <= "0000";
Read_To_Reg <= '1';
Save_ALU <= '1';
ALU_Op <= "0010";
when 2 =>
Set_BusB_To <= "0110";
Set_Addr_To <= aBC;
when 3 =>
if IR(3) = '0' then
IncDec_16 <= "0110"; -- mikej
else
IncDec_16 <= "1110"; -- mikej
end if;
TStates <= "100"; -- MIKEJ should be 4 for IO cycle
IORQ <= '1';
Write <= '1';
I_BTR <= '1';
when 4 =>
NoRead <= '1';
TStates <= "101";
when others => null;
end case;
end case;
end case;
if Mode = 1 then
if MCycle = "001" then
-- TStates <= "100";
else
TStates <= "011";
end if;
end if;
if Mode = 3 then
if MCycle = "001" then
-- TStates <= "100";
else
TStates <= "100";
end if;
end if;
if Mode < 2 then
if MCycle = "110" then
Inc_PC <= '1';
if Mode = 1 then
Set_Addr_To <= aXY;
TStates <= "100";
Set_BusB_To(2 downto 0) <= SSS;
Set_BusB_To(3) <= '0';
end if;
if IRB = "00110110" or IRB = "11001011" then
Set_Addr_To <= aNone;
end if;
end if;
if MCycle = "111" then
if Mode = 0 then
TStates <= "101";
end if;
if ISet /= "01" then
Set_Addr_To <= aXY;
end if;
Set_BusB_To(2 downto 0) <= SSS;
Set_BusB_To(3) <= '0';
if IRB = "00110110" or ISet = "01" then
-- LD (HL),n
Inc_PC <= '1';
else
NoRead <= '1';
end if;
end if;
end if;
end process;
end;
| gpl-3.0 | 45fa3522b310df28d569780480823d81 | 0.4896 | 3.144891 | false | false | false | false |
EliasLuiz/TCC | Leon3/lib/techmap/maps/toutpad.vhd | 1 | 7,253 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: toutpad
-- File: toutpad.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: tri-state output pad with technology wrapper
------------------------------------------------------------------------------
library techmap;
library ieee;
use ieee.std_logic_1164.all;
use techmap.gencomp.all;
use techmap.allpads.all;
entity toutpad is
generic (tech : integer := 0; level : integer := 0; slew : integer := 0;
voltage : integer := x33v; strength : integer := 12;
oepol : integer := 0);
port (pad : out std_ulogic; i, en : in std_ulogic;
cfgi: in std_logic_vector(19 downto 0) := "00000000000000000000");
end;
architecture rtl of toutpad is
signal oen : std_ulogic;
signal padx, gnd : std_ulogic;
begin
gnd <= '0';
oen <= not en when oepol /= padoen_polarity(tech) else en;
gen0 : if has_pads(tech) = 0 generate
pad <= i
-- pragma translate_off
after 2 ns
-- pragma translate_on
when oen = '0'
-- pragma translate_off
else 'X' after 2 ns when is_x(en)
-- pragma translate_on
else 'Z'
-- pragma translate_off
after 2 ns
-- pragma translate_on
;
end generate;
xcv : if (is_unisim(tech) = 1) generate
u0 : unisim_toutpad generic map (level, slew, voltage, strength)
port map (pad, i, oen);
end generate;
axc : if (tech = axcel) or (tech = axdsp) generate
u0 : axcel_toutpad generic map (level, slew, voltage, strength)
port map (pad, i, oen);
end generate;
pa3 : if (tech = proasic) or (tech = apa3) generate
u0 : apa3_toutpad generic map (level, slew, voltage, strength)
port map (pad, i, oen);
end generate;
pa3e : if (tech = apa3e) generate
u0 : apa3e_toutpad generic map (level, slew, voltage, strength)
port map (pad, i, oen);
end generate;
igl2 : if (tech = igloo2) or (tech = rtg4) generate
u0 : igloo2_toutpad port map (pad, i, oen);
end generate;
pa3l : if (tech = apa3l) generate
u0 : apa3l_toutpad generic map (level, slew, voltage, strength)
port map (pad, i, oen);
end generate;
fus : if (tech = actfus) generate
u0 : fusion_toutpad generic map (level, slew, voltage, strength)
port map (pad, i, oen);
end generate;
atc : if (tech = atc18s) generate
u0 : atc18_toutpad generic map (level, slew, voltage, strength)
port map (pad, i, oen);
end generate;
atcrh : if (tech = atc18rha) generate
u0 : atc18rha_toutpad generic map (level, slew, voltage, strength)
port map (pad, i, oen);
end generate;
um : if (tech = umc) generate
u0 : umc_toutpad generic map (level, slew, voltage, strength)
port map (pad, i, oen);
end generate;
rhu : if (tech = rhumc) generate
u0 : rhumc_toutpad generic map (level, slew, voltage, strength)
port map (pad, i, oen);
end generate;
saed : if (tech = saed32) generate
u0 : saed32_toutpad generic map (level, slew, voltage, strength)
port map (pad, i, oen);
end generate;
rhs : if (tech = rhs65) generate
u0 : rhs65_toutpad generic map (level, slew, voltage, strength)
port map (pad, i, oen, cfgi(0), cfgi(2), cfgi(1));
end generate;
dar : if (tech = dare) generate
u0 : dare_toutpad generic map (level, slew, voltage, strength)
port map (pad, i, oen);
end generate;
ihp : if (tech = ihp25) generate
u0 : ihp25_toutpad generic map (level, slew, voltage, strength)
port map(pad, i, oen);
end generate;
ihprh : if (tech = ihp25rh) generate
u0 : ihp25rh_toutpad generic map (level, slew, voltage, strength)
port map(pad, i, oen);
end generate;
rh18t : if (tech = rhlib18t) generate
u0 : rh_lib18t_iopad generic map (strength) port map (padx, i, oen, open);
pad <= padx;
end generate;
ut025 : if (tech = ut25) generate
u0 : ut025crh_toutpad generic map (level, slew, voltage, strength)
port map(pad, i, oen);
end generate;
ut13 : if (tech = ut130) generate
u0 : ut130hbd_toutpad generic map (level, slew, voltage, strength)
port map(pad, i, oen);
end generate;
pere : if (tech = peregrine) generate
u0 : peregrine_toutpad generic map (level, slew, voltage, strength)
port map(pad, i, oen);
end generate;
nex : if (tech = easic90) generate
u0 : nextreme_toutpad generic map (level, slew, voltage, strength)
port map (pad, i, oen);
end generate;
n2x : if (tech = easic45) generate
u0 : n2x_toutpad generic map (level, slew, voltage, strength)
port map (pad, i, oen, cfgi(0), cfgi(1),
cfgi(19 downto 15), cfgi(14 downto 10), cfgi(9 downto 6), cfgi(5 downto 2));
end generate;
ut90nhbd : if (tech = ut90) generate
u0 : ut90nhbd_toutpad generic map (level, slew, voltage, strength)
port map(pad, i, oen, cfgi(0));
end generate;
end;
library techmap;
library ieee;
use ieee.std_logic_1164.all;
use techmap.gencomp.all;
entity toutpadv is
generic (tech : integer := 0; level : integer := 0; slew : integer := 0;
voltage : integer := x33v; strength : integer := 12; width : integer := 1;
oepol : integer := 0);
port (
pad : out std_logic_vector(width-1 downto 0);
i : in std_logic_vector(width-1 downto 0);
en : in std_ulogic;
cfgi: in std_logic_vector(19 downto 0) := "00000000000000000000"
);
end;
architecture rtl of toutpadv is
begin
v : for j in width-1 downto 0 generate
u0 : toutpad generic map (tech, level, slew, voltage, strength, oepol)
port map (pad(j), i(j), en, cfgi);
end generate;
end;
library techmap;
library ieee;
use ieee.std_logic_1164.all;
use techmap.gencomp.all;
entity toutpadvv is
generic (tech : integer := 0; level : integer := 0; slew : integer := 0;
voltage : integer := x33v; strength : integer := 12; width : integer := 1;
oepol : integer := 0);
port (
pad : out std_logic_vector(width-1 downto 0);
i : in std_logic_vector(width-1 downto 0);
en : in std_logic_vector(width-1 downto 0);
cfgi: in std_logic_vector(19 downto 0) := "00000000000000000000");
end;
architecture rtl of toutpadvv is
begin
v : for j in width-1 downto 0 generate
u0 : toutpad generic map (tech, level, slew, voltage, strength, oepol)
port map (pad(j), i(j), en(j), cfgi);
end generate;
end;
| gpl-3.0 | ab5746642773774aa8b6cc2909af29b0 | 0.640563 | 3.457102 | false | false | false | false |
EliasLuiz/TCC | Leon3/designs/leon3-digilent-nexys-video/config.vhd | 1 | 6,166 |
-----------------------------------------------------------------------------
-- LEON3 Demonstration design test bench configuration
-- Copyright (C) 2009 Aeroflex Gaisler
------------------------------------------------------------------------------
library techmap;
use techmap.gencomp.all;
package config is
-- Technology and synthesis options
constant CFG_FABTECH : integer := artix7;
constant CFG_MEMTECH : integer := artix7;
constant CFG_PADTECH : integer := artix7;
constant CFG_TRANSTECH : integer := GTP0;
constant CFG_NOASYNC : integer := 0;
constant CFG_SCAN : integer := 0;
-- Clock generator
constant CFG_CLKTECH : integer := artix7;
constant CFG_CLKMUL : integer := (14);
constant CFG_CLKDIV : integer := (20);
constant CFG_OCLKDIV : integer := 1;
constant CFG_OCLKBDIV : integer := 0;
constant CFG_OCLKCDIV : integer := 0;
constant CFG_PCIDLL : integer := 0;
constant CFG_PCISYSCLK: integer := 0;
constant CFG_CLK_NOFB : integer := 0;
-- LEON3 processor core
constant CFG_LEON3 : integer := 1;
constant CFG_NCPU : integer := (1);
constant CFG_NWIN : integer := (8);
constant CFG_V8 : integer := 2 + 4*0;
constant CFG_MAC : integer := 0;
constant CFG_BP : integer := 1;
constant CFG_SVT : integer := 0;
constant CFG_RSTADDR : integer := 16#00000#;
constant CFG_LDDEL : integer := (1);
constant CFG_NOTAG : integer := 0;
constant CFG_NWP : integer := (0);
constant CFG_PWD : integer := 0*2;
constant CFG_FPU : integer := 0 + 16*0 + 32*0;
constant CFG_GRFPUSH : integer := 0;
constant CFG_ICEN : integer := 1;
constant CFG_ISETS : integer := 4;
constant CFG_ISETSZ : integer := 4;
constant CFG_ILINE : integer := 8;
constant CFG_IREPL : integer := 2;
constant CFG_ILOCK : integer := 0;
constant CFG_ILRAMEN : integer := 0;
constant CFG_ILRAMADDR: integer := 16#8E#;
constant CFG_ILRAMSZ : integer := 1;
constant CFG_DCEN : integer := 1;
constant CFG_DSETS : integer := 4;
constant CFG_DSETSZ : integer := 4;
constant CFG_DLINE : integer := 8;
constant CFG_DREPL : integer := 2;
constant CFG_DLOCK : integer := 0;
constant CFG_DSNOOP : integer := 0 + 0*2 + 4*0;
constant CFG_DFIXED : integer := 16#0#;
constant CFG_DLRAMEN : integer := 0;
constant CFG_DLRAMADDR: integer := 16#8F#;
constant CFG_DLRAMSZ : integer := 1;
constant CFG_MMUEN : integer := 0;
constant CFG_ITLBNUM : integer := 2;
constant CFG_DTLBNUM : integer := 2;
constant CFG_TLB_TYPE : integer := 1 + 0*2;
constant CFG_TLB_REP : integer := 1;
constant CFG_MMU_PAGE : integer := 0;
constant CFG_DSU : integer := 1;
constant CFG_ITBSZ : integer := 1 + 64*0;
constant CFG_ATBSZ : integer := 1;
constant CFG_AHBPF : integer := 0;
constant CFG_LEON3FT_EN : integer := 0;
constant CFG_IUFT_EN : integer := 0;
constant CFG_FPUFT_EN : integer := 0;
constant CFG_RF_ERRINJ : integer := 0;
constant CFG_CACHE_FT_EN : integer := 0;
constant CFG_CACHE_ERRINJ : integer := 0;
constant CFG_LEON3_NETLIST: integer := 0;
constant CFG_DISAS : integer := 0 + 0;
constant CFG_PCLOW : integer := 2;
constant CFG_STAT_ENABLE : integer := 0;
constant CFG_STAT_CNT : integer := 1;
constant CFG_STAT_NMAX : integer := 0;
constant CFG_STAT_DSUEN : integer := 0;
constant CFG_NP_ASI : integer := 0;
constant CFG_WRPSR : integer := 0;
constant CFG_ALTWIN : integer := 0;
constant CFG_REX : integer := 0;
-- AMBA settings
constant CFG_DEFMST : integer := (0);
constant CFG_RROBIN : integer := 1;
constant CFG_SPLIT : integer := 0;
constant CFG_FPNPEN : integer := 1;
constant CFG_AHBIO : integer := 16#FFF#;
constant CFG_APBADDR : integer := 16#800#;
constant CFG_AHB_MON : integer := 0;
constant CFG_AHB_MONERR : integer := 0;
constant CFG_AHB_MONWAR : integer := 0;
constant CFG_AHB_DTRACE : integer := 0;
-- DSU UART
constant CFG_AHB_UART : integer := 1;
-- JTAG based DSU interface
constant CFG_AHB_JTAG : integer := 1;
-- Ethernet DSU
constant CFG_DSU_ETH : integer := 1 + 1 + 0;
constant CFG_ETH_BUF : integer := 2;
constant CFG_ETH_IPM : integer := 16#C0A8#;
constant CFG_ETH_IPL : integer := 16#0033#;
constant CFG_ETH_ENM : integer := 16#020000#;
constant CFG_ETH_ENL : integer := 16#000000#;
-- Xilinx MIG 7-Series
constant CFG_MIG_7SERIES : integer := 1;
constant CFG_MIG_7SERIES_MODEL : integer := 0;
-- AHB ROM
constant CFG_AHBROMEN : integer := 0;
constant CFG_AHBROPIP : integer := 0;
constant CFG_AHBRODDR : integer := 16#000#;
constant CFG_ROMADDR : integer := 16#000#;
constant CFG_ROMMASK : integer := 16#E00# + 16#000#;
-- AHB RAM
constant CFG_AHBRAMEN : integer := 0;
constant CFG_AHBRSZ : integer := 1;
constant CFG_AHBRADDR : integer := 16#A00#;
constant CFG_AHBRPIPE : integer := 0;
-- Gaisler Ethernet core
constant CFG_GRETH : integer := 1;
constant CFG_GRETH1G : integer := 0;
constant CFG_ETH_FIFO : integer := 8;
-- UART 1
constant CFG_UART1_ENABLE : integer := 1;
constant CFG_UART1_FIFO : integer := 1;
-- LEON3 interrupt controller
constant CFG_IRQ3_ENABLE : integer := 1;
constant CFG_IRQ3_NSEC : integer := 0;
-- Modular timer
constant CFG_GPT_ENABLE : integer := 1;
constant CFG_GPT_NTIM : integer := (2);
constant CFG_GPT_SW : integer := (8);
constant CFG_GPT_TW : integer := (32);
constant CFG_GPT_IRQ : integer := (8);
constant CFG_GPT_SEPIRQ : integer := 1;
constant CFG_GPT_WDOGEN : integer := 0;
constant CFG_GPT_WDOG : integer := 16#0#;
-- GPIO port
constant CFG_GRGPIO_ENABLE : integer := 1;
constant CFG_GRGPIO_IMASK : integer := 16#0000#;
constant CFG_GRGPIO_WIDTH : integer := (8);
-- SPI memory controller
constant CFG_SPIMCTRL : integer := 1;
constant CFG_SPIMCTRL_SDCARD : integer := 0;
constant CFG_SPIMCTRL_READCMD : integer := 16#0B#;
constant CFG_SPIMCTRL_DUMMYBYTE : integer := 0;
constant CFG_SPIMCTRL_DUALOUTPUT : integer := 0;
constant CFG_SPIMCTRL_SCALER : integer := (2);
constant CFG_SPIMCTRL_ASCALER : integer := (2);
constant CFG_SPIMCTRL_PWRUPCNT : integer := (0);
constant CFG_SPIMCTRL_OFFSET : integer := 16#0#;
-- GRLIB debugging
constant CFG_DUART : integer := 1;
end;
| gpl-3.0 | d6d5f0265e7601aa32b7ba113609723f | 0.644989 | 3.637758 | false | false | false | false |
EliasLuiz/TCC | Leon3/lib/techmap/atc18/pads_atc18.vhd | 1 | 10,146 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Package: atcpads_gen
-- File: atcpads_gen.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: Atmel ATC18 pad wrappers
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
package atcpads is
-- input pad
component pc33d00z port (pad : in std_logic; cin : out std_logic); end component;
-- input pad with pull-up
component pc33d00uz port (pad : in std_logic; cin : out std_logic); end component;
-- schmitt input pad
component pc33d20z port (pad : in std_logic; cin : out std_logic); end component;
-- schmitt input pad with pull-up
component pt33d20uz port (pad : inout std_logic; cin : out std_logic); end component;
-- output pads
component pt33o01z port (i : in std_logic; pad : out std_logic); end component;
component pt33o02z port (i : in std_logic; pad : out std_logic); end component;
component pt33o04z port (i : in std_logic; pad : out std_logic); end component;
component pt33o08z port (i : in std_logic; pad : out std_logic); end component;
-- tri-state output pads
component pt33t01z port (i, oen : in std_logic; pad : out std_logic); end component;
component pt33t02z port (i, oen : in std_logic; pad : out std_logic); end component;
component pt33t04z port (i, oen : in std_logic; pad : out std_logic); end component;
component pt33t08z port (i, oen : in std_logic; pad : out std_logic); end component;
-- tri-state output pads with pull-up
component pt33t01uz port (i, oen : in std_logic; pad : out std_logic); end component;
component pt33t02uz port (i, oen : in std_logic; pad : out std_logic); end component;
component pt33t04uz port (i, oen : in std_logic; pad : out std_logic); end component;
component pt33t08uz port (i, oen : in std_logic; pad : out std_logic); end component;
-- bidirectional pads
component pt33b01z
port (i, oen : in std_logic; cin : out std_logic; pad : inout std_logic);
end component;
component pt33b02z
port (i, oen : in std_logic; cin : out std_logic; pad : inout std_logic);
end component;
component pt33b08z
port (i, oen : in std_logic; cin : out std_logic; pad : inout std_logic);
end component;
component pt33b04z
port (i, oen : in std_logic; cin : out std_logic; pad : inout std_logic);
end component;
-- bidirectional pads with pull-up
component pt33b01uz
port (i, oen : in std_logic; cin : out std_logic; pad : inout std_logic);
end component;
component pt33b02uz
port (i, oen : in std_logic; cin : out std_logic; pad : inout std_logic);
end component;
component pt33b08uz
port (i, oen : in std_logic; cin : out std_logic; pad : inout std_logic);
end component;
component pt33b04uz
port (i, oen : in std_logic; cin : out std_logic; pad : inout std_logic);
end component;
--PCI pads
component pp33o01z
port (i : in std_logic; pad : out std_logic);
end component;
component pp33b01z
port ( i, oen : in std_logic; cin : out std_logic; pad : inout std_logic);
end component;
component pp33t01z
port (i, oen : in std_logic; pad : out std_logic);
end component;
end;
library ieee;
library techmap;
use ieee.std_logic_1164.all;
use techmap.gencomp.all;
-- pragma translate_off
library atc18;
use atc18.pc33d00z;
-- pragma translate_on
entity atc18_inpad is
generic (level : integer := 0; voltage : integer := 0);
port (pad : in std_logic; o : out std_logic);
end;
architecture rtl of atc18_inpad is
component pc33d00z port (pad : in std_logic; cin : out std_logic); end component;
begin
pci0 : if level = pci33 generate
ip : pc33d00z port map (pad => pad, cin => o);
end generate;
gen0 : if level /= pci33 generate
ip : pc33d00z port map (pad => pad, cin => o);
end generate;
end;
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
-- pragma translate_off
library atc18;
use atc18.pp33b01z;
use atc18.pt33b01z;
use atc18.pt33b02z;
use atc18.pt33b08z;
use atc18.pt33b04z;
-- pragma translate_on
entity atc18_iopad is
generic (level : integer := 0; slew : integer := 0;
voltage : integer := 0; strength : integer := 0);
port (pad : inout std_logic; i, en : in std_logic; o : out std_logic);
end ;
architecture rtl of atc18_iopad is
component pp33b01z
port ( i, oen : in std_logic; cin : out std_logic; pad : inout std_logic);
end component;
component pt33b01z
port (i, oen : in std_logic; cin : out std_logic; pad : inout std_logic);
end component;
component pt33b02z
port (i, oen : in std_logic; cin : out std_logic; pad : inout std_logic);
end component;
component pt33b08z
port (i, oen : in std_logic; cin : out std_logic; pad : inout std_logic);
end component;
component pt33b04z
port (i, oen : in std_logic; cin : out std_logic; pad : inout std_logic);
end component;
begin
pci0 : if level = pci33 generate
op : pp33b01z port map (i => i, oen => en, pad => pad, cin => o);
end generate;
gen0 : if level /= pci33 generate
f1 : if (strength <= 4) generate
op : pt33b01z port map (i => i, oen => en, pad => pad, cin => o);
end generate;
f2 : if (strength > 4) and (strength <= 8) generate
op : pt33b02z port map (i => i, oen => en, pad => pad, cin => o);
end generate;
f3 : if (strength > 8) and (strength <= 16) generate
op : pt33b04z port map (i => i, oen => en, pad => pad, cin => o);
end generate;
f4 : if (strength > 16) generate
op : pt33b08z port map (i => i, oen => en, pad => pad, cin => o);
end generate;
end generate;
end;
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
-- pragma translate_off
library atc18;
use atc18.pp33t01z;
use atc18.pt33o01z;
use atc18.pt33o02z;
use atc18.pt33o04z;
use atc18.pt33o08z;
-- pragma translate_on
entity atc18_outpad is
generic (level : integer := 0; slew : integer := 0;
voltage : integer := 0; strength : integer := 0);
port (pad : out std_logic; i : in std_logic);
end ;
architecture rtl of atc18_outpad is
component pp33t01z
port (i, oen : in std_logic; pad : out std_logic);
end component;
component pt33o01z port (i : in std_logic; pad : out std_logic); end component;
component pt33o02z port (i : in std_logic; pad : out std_logic); end component;
component pt33o04z port (i : in std_logic; pad : out std_logic); end component;
component pt33o08z port (i : in std_logic; pad : out std_logic); end component;
signal gnd : std_logic;
begin
gnd <= '0';
pci0 : if level = pci33 generate
op : pp33t01z port map (i => i, oen => gnd, pad => pad);
end generate;
gen0 : if level /= pci33 generate
f4 : if (strength <= 4) generate
op : pt33o01z port map (i => i, pad => pad);
end generate;
f8 : if (strength > 4) and (strength <= 8) generate
op : pt33o02z port map (i => i, pad => pad);
end generate;
f16 : if (strength > 8) and (strength <= 16) generate
op : pt33o04z port map (i => i, pad => pad);
end generate;
f32 : if (strength > 16) generate
op : pt33o08z port map (i => i, pad => pad);
end generate;
end generate;
end;
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
-- pragma translate_off
library atc18;
use atc18.pp33t01z;
use atc18.pt33t01z;
use atc18.pt33t02z;
use atc18.pt33t04z;
use atc18.pt33t08z;
-- pragma translate_on
entity atc18_toutpad is
generic (level : integer := 0; slew : integer := 0;
voltage : integer := 0; strength : integer := 0);
port (pad : out std_logic; i, en : in std_logic);
end ;
architecture rtl of atc18_toutpad is
component pp33t01z
port (i, oen : in std_logic; pad : out std_logic);
end component;
component pt33t01z port (i, oen : in std_logic; pad : out std_logic); end component;
component pt33t02z port (i, oen : in std_logic; pad : out std_logic); end component;
component pt33t04z port (i, oen : in std_logic; pad : out std_logic); end component;
component pt33t08z port (i, oen : in std_logic; pad : out std_logic); end component;
begin
pci0 : if level = pci33 generate
op : pp33t01z port map (i => i, oen => en, pad => pad);
end generate;
gen0 : if level /= pci33 generate
f4 : if (strength <= 4) generate
op : pt33t01z port map (i => i, oen => en, pad => pad);
end generate;
f8 : if (strength > 4) and (strength <= 8) generate
op : pt33t02z port map (i => i, oen => en, pad => pad);
end generate;
f16 : if (strength > 8) and (strength <= 16) generate
op : pt33t04z port map (i => i, oen => en, pad => pad);
end generate;
f32 : if (strength > 16) generate
op : pt33t08z port map (i => i, oen => en, pad => pad);
end generate;
end generate;
end;
library ieee;
use ieee.std_logic_1164.all;
entity atc18_clkpad is
generic (level : integer := 0; voltage : integer := 0);
port (pad : in std_logic; o : out std_logic);
end;
architecture rtl of atc18_clkpad is
begin
o <= pad;
end;
| gpl-3.0 | 0fd1bcad5816fd2c24a8dc654318e1da | 0.647053 | 3.211776 | false | false | false | false |
EliasLuiz/TCC | Leon3/lib/techmap/virtex5/serdes_unisim.vhd | 1 | 74,624 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: serdes_unisim
-- File: serdes_unisim.vhd
-- Author: Andrea Gianarro - Cobham Gaisler AB
-- Description: Xilinx Virtex 5 GTP and GTX-based SGMII Gigabit Ethernet Serdes
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.stdlib.all;
library techmap;
use techmap.gencomp.all;
library unisim;
--use unisim.BUFG;
use unisim.vcomponents.all;
-- pragma translate_off
-- pragma translate_on
entity serdes_unisim is
generic (
transtech : integer
);
port (
clk_125 : in std_logic;
rst_125 : in std_logic;
rx_in_p : in std_logic; -- SER IN
rx_in_n : in std_logic; -- SER IN
rx_out : out std_logic_vector(9 downto 0); -- PAR OUT
rx_clk : out std_logic;
rx_rstn : out std_logic;
rx_pll_clk : out std_logic;
rx_pll_rstn : out std_logic;
tx_pll_clk : out std_logic;
tx_pll_rstn : out std_logic;
tx_in : in std_logic_vector(9 downto 0) ; -- PAR IN
tx_out_p : out std_logic; -- SER OUT
tx_out_n : out std_logic; -- SER OUT
bitslip : in std_logic
);
end entity;
architecture rtl of serdes_unisim is
constant SIMULATION_P : integer := 1;
component BUFG
port ( O : out std_logic;
I : in std_logic );
end component;
-- signal rx_clk_int, rx_pll_clk_int, tx_pll_clk_int, rst_int, pll_areset_int, rx_locked_int, rx_rstn_int_0, tx_locked_int : std_logic;
-- signal rx_cda_reset_int, bitslip_int, rx_in_int, rx_rst_int, rx_divfwdclk_int, tx_out_int : std_logic_vector(0 downto 0) ;
-- signal rx_clk_rstn_int, rx_pll_rstn_int, tx_pll_rstn_int, rx_cda_reset_int_0 : std_logic;
-- signal rx_out_int, tx_in_int : std_logic_vector(9 downto 0) ;
signal ref_clk_int, ref_clk_lock_int, ref_clk_rstn_int, ref_clk_rst_int : std_logic;
signal ref_clk_buf_int, rx_usrclk_int, rx_usrclk2_int, tx_usrclk_int, tx_usrclk2_int : std_logic;
signal ref_clk_buf_rstn_int, rx_usrclk2_rstn_int, tx_usrclk2_rstn_int, tx_rst_int, rx_rst_int : std_logic;
signal rx_rec_clk_int, rx_rec_clk_buf_int : std_logic;
signal tx_out_clk_int, tx_out_clk_rstn_int, rst_done_int : std_logic;
signal tx_usrclk_lock_int, rx_usrclk_lock_int : std_logic;
signal rx_rec_clk0_int, rst_done0_int, rx_in0_n, rx_in0_p, tx_out0_n, tx_out0_p : std_logic;
signal rx_rec_clk1_int, rst_done1_int, rx_in1_n, rx_in1_p, tx_out1_n, tx_out1_p : std_logic;
signal r0, r1, r2 : std_logic_vector(4 downto 0);
signal clkdv_i, clk0_i, clkfb_i, reset_to_dcm : std_logic;
signal count_to_dcm_reset : std_logic_vector(1 downto 0);
signal clkfbout_i, clkout0_i, clkout1_i, pll_lk_out, pll_locked_out_r, time_elapsed : std_logic;
signal lock_wait_counter : std_logic_vector(15 downto 0);
-- ground and tied_to_vcc_i signals
signal tied_to_ground_i : std_logic;
signal tied_to_ground_vec_i : std_logic_vector(63 downto 0);
signal tied_to_vcc_i : std_logic;
signal tied_to_vcc_vec_i : std_logic_vector(63 downto 0);
-- RX Datapath signals
signal rxdata0_i : std_logic_vector(31 downto 0);
signal rxchariscomma0_float_i : std_logic;
signal rxcharisk0_float_i : std_logic;
signal rxdisperr0_float_i : std_logic;
signal rxnotintable0_float_i : std_logic;
signal rxrundisp0_float_i : std_logic;
signal rxdata0_out_i : std_logic_vector(9 downto 0);
signal rxcharisk0_i : std_logic_vector(3 downto 0);
signal rxdisperr0_i : std_logic_vector(3 downto 0);
-- TX Datapath signals
signal txdata0_i : std_logic_vector(31 downto 0);
signal txdata0_in_i : std_logic_vector(9 downto 0);
signal txchardispmode0_i : std_logic_vector(3 downto 0);
signal txchardispval0_i : std_logic_vector(3 downto 0);
signal txkerr0_float_i : std_logic;
signal txrundisp0_float_i : std_logic;
-- Electrical idle reset logic signals
signal rxelecidle0_i : std_logic;
signal rxelecidlereset0_i : std_logic;
-- RX Datapath signals
signal rxdata1_i : std_logic_vector(31 downto 0);
signal rxchariscomma1_float_i : std_logic;
signal rxcharisk1_float_i : std_logic;
signal rxdisperr1_float_i : std_logic;
signal rxnotintable1_float_i : std_logic;
signal rxrundisp1_float_i : std_logic;
signal rxdata1_out_i : std_logic_vector(9 downto 0);
signal rxcharisk1_i : std_logic_vector(3 downto 0);
signal rxdisperr1_i : std_logic_vector(3 downto 0);
-- TX Datapath signals
signal txdata1_i : std_logic_vector(31 downto 0);
signal txdata1_in_i : std_logic_vector(9 downto 0);
signal txchardispmode1_i : std_logic_vector(3 downto 0);
signal txchardispval1_i : std_logic_vector(3 downto 0);
signal txkerr1_float_i : std_logic;
signal txrundisp1_float_i : std_logic;
-- Electrical idle reset logic signals
signal rxelecidle1_i : std_logic;
signal resetdone1_i : std_logic;
signal rxelecidlereset1_i : std_logic;
-- Shared Electrical Idle Reset signal
signal rxenelecidleresetb_i : std_logic;
signal txelecidle_r : std_logic;
signal txelecidle0_r : std_logic;
signal txelecidle1_r : std_logic;
signal txpowerdown0_r : std_logic_vector(1 downto 0);
signal rxpowerdown0_r : std_logic_vector(1 downto 0);
signal txpowerdown1_r : std_logic_vector(1 downto 0);
signal rxpowerdown1_r : std_logic_vector(1 downto 0);
begin
-- output clocks
rx_clk <= rx_usrclk2_int;
rx_pll_clk <= ref_clk_buf_int;
tx_pll_clk <= tx_usrclk2_int;
-- output synchronized resets
rx_rstn <= rx_usrclk2_rstn_int;
rx_pll_rstn <= ref_clk_buf_rstn_int;
tx_pll_rstn <= tx_usrclk2_rstn_int;
ref_clk_rst_int <= not ref_clk_lock_int;
-- reset synchronizers
rst0 : process (ref_clk_buf_int, ref_clk_rst_int) begin
if rising_edge(ref_clk_buf_int) then
r0 <= r0(3 downto 0) & rst_done_int;
ref_clk_buf_rstn_int <= r0(4) and r0(3) and r0(2);
end if;
if (ref_clk_rst_int = '1') then r0 <= "00000"; ref_clk_buf_rstn_int <= '0'; end if;
end process;
rst1 : process (rx_usrclk2_int, rx_rst_int) begin
if rising_edge(rx_usrclk2_int) then
r1 <= r1(3 downto 0) & rst_done_int;
rx_usrclk2_rstn_int <= r1(4) and r1(3) and r1(2);
end if;
if (rx_rst_int = '1') then r1 <= "00000"; rx_usrclk2_rstn_int <= '0'; end if;
end process;
rst2 : process (tx_usrclk2_int, tx_rst_int) begin
if rising_edge(tx_usrclk2_int) then
r2 <= r2(3 downto 0) & rst_done_int;
tx_usrclk2_rstn_int <= r2(4) and r2(3) and r2(2);
end if;
if (tx_rst_int = '1') then r2 <= "00000"; tx_usrclk2_rstn_int <= '0'; end if;
end process;
-- Transceiver channel selection
ch0: if transtech = GTP0 or transtech = GTX0 generate
rx_rec_clk_int <= rx_rec_clk0_int;
rst_done_int <= rst_done0_int;
rx_in0_n <= rx_in_n;
rx_in0_p <= rx_in_p;
tx_out_n <= tx_out0_n;
tx_out_p <= tx_out0_p;
inv_tx: for i in 0 to 9 generate
txdata0_in_i(i) <= tx_in(9-i);
rx_out(i) <= rxdata0_out_i(9-i);
end generate ;
end generate;
ch1: if transtech = GTP1 or transtech = GTX1 generate
rx_rec_clk_int <= rx_rec_clk1_int;
rst_done_int <= rst_done1_int;
rx_in1_n <= rx_in_n;
rx_in1_p <= rx_in_p;
tx_out_n <= tx_out1_n;
tx_out_p <= tx_out1_p;
inv_tx: for i in 0 to 9 generate
txdata1_in_i(i) <= tx_in(9-i);
rx_out(i) <= rxdata1_out_i(9-i);
end generate ;
end generate;
--------------------------- Static signal Assignments ---------------------
tied_to_ground_i <= '0';
tied_to_ground_vec_i(63 downto 0) <= (others => '0');
tied_to_vcc_i <= '1';
tied_to_vcc_vec_i(63 downto 0) <= (others => '1');
------------------- GTP Datapath byte mapping -----------------
--The GTP deserializes the rightmost parallel bit (LSb) first
--The GTP serializes the rightmost parallel bit (LSb) first
--The GTP deserializes the rightmost parallel bit (LSb) first
--The GTP serializes the rightmost parallel bit (LSb) first
------------- GTP0 rxdata_out_i Assignments for 10 bit datapath -------
rxdata0_out_i <= (rxdisperr0_i(0) & rxcharisk0_i(0) & rxdata0_i(7 downto 0));
------------- GTP0 txdata_i Assignments for 10 bit datapath -------
txdata0_i <= (tied_to_ground_vec_i(23 downto 0) & txdata0_in_i(7 downto 0));
txchardispval0_i <= (tied_to_ground_vec_i(2 downto 0) & txdata0_in_i(8));
txchardispmode0_i <= (tied_to_ground_vec_i(2 downto 0) & txdata0_in_i(9));
------------- GTP1 rxdata_out_i Assignments for 10 bit datapath -------
rxdata1_out_i <= (rxdisperr1_i(0) & rxcharisk1_i(0) & rxdata1_i(7 downto 0));
------------- GTP1 txdata_i Assignments for 10 bit datapath -------
txdata1_i <= (tied_to_ground_vec_i(23 downto 0) & txdata1_in_i(7 downto 0));
txchardispval1_i <= (tied_to_ground_vec_i(2 downto 0) & txdata1_in_i(8));
txchardispmode1_i <= (tied_to_ground_vec_i(2 downto 0) & txdata1_in_i(9));
---- Clock buffers
ref_clk_buf0 : BUFG
port map
(
I => ref_clk_int,
O => ref_clk_buf_int
);
rx_rec_clk_buf0 : BUFG
port map
(
I => rx_rec_clk_int,
O => rx_rec_clk_buf_int
);
---- GTP_DUAL instantiation
inst_gtp0: if (transtech = GTP0) or (transtech = GTP1) generate
-- no need for extra clocks on GTP transtech
tx_usrclk_int <= ref_clk_buf_int;
tx_usrclk2_int <= ref_clk_buf_int;
tx_rst_int <= not ref_clk_lock_int;
rx_usrclk_int <= rx_rec_clk_buf_int;
rx_usrclk2_int <= rx_rec_clk_buf_int;
rx_rst_int <= not ref_clk_lock_int;
gtp_dual_i:GTP_DUAL
generic map (
--_______________________ Simulation-Only Attributes ___________________
SIM_RECEIVER_DETECT_PASS0 => TRUE,
SIM_RECEIVER_DETECT_PASS1 => TRUE,
SIM_MODE => "FAST",
SIM_GTPRESET_SPEEDUP => 0,
SIM_PLL_PERDIV2 => x"190",
--___________________________ Shared Attributes ________________________
-------------------------- Tile and PLL Attributes ---------------------
CLK25_DIVIDER => 5,
CLKINDC_B => TRUE,
OOB_CLK_DIVIDER => 4,
OVERSAMPLE_MODE => FALSE,
PLL_DIVSEL_FB => 2,
PLL_DIVSEL_REF => 1,
PLL_TXDIVSEL_COMM_OUT => 2,
TX_SYNC_FILTERB => 1,
--____________________ Transmit Interface Attributes ___________________
------------------- TX Buffering and Phase Alignment -------------------
TX_BUFFER_USE_0 => FALSE,
TX_XCLK_SEL_0 => "TXUSR",
TXRX_INVERT_0 => "00100",
TX_BUFFER_USE_1 => FALSE,
TX_XCLK_SEL_1 => "TXUSR",
TXRX_INVERT_1 => "00100",
--------------------- TX Serial Line Rate settings ---------------------
PLL_TXDIVSEL_OUT_0 => 1,
PLL_TXDIVSEL_OUT_1 => 1,
--------------------- TX Driver and OOB signalling --------------------
TX_DIFF_BOOST_0 => TRUE,
TX_DIFF_BOOST_1 => TRUE,
------------------ TX Pipe Control for PCI Express/SATA ---------------
COM_BURST_VAL_0 => "1111",
COM_BURST_VAL_1 => "1111",
--_______________________ Receive Interface Attributes ________________
------------ RX Driver,OOB signalling,Coupling and Eq,CDR -------------
AC_CAP_DIS_0 => TRUE,
OOBDETECT_THRESHOLD_0 => "001",
PMA_CDR_SCAN_0 => x"6c07640",
PMA_RX_CFG_0 => x"09f0088",
RCV_TERM_GND_0 => FALSE,
RCV_TERM_MID_0 => FALSE,
RCV_TERM_VTTRX_0 => FALSE,
TERMINATION_IMP_0 => 50,
AC_CAP_DIS_1 => TRUE,
OOBDETECT_THRESHOLD_1 => "001",
PMA_CDR_SCAN_1 => x"6c07640",
PMA_RX_CFG_1 => x"09f0088",
RCV_TERM_GND_1 => FALSE,
RCV_TERM_MID_1 => FALSE,
RCV_TERM_VTTRX_1 => FALSE,
TERMINATION_IMP_1 => 50,
PCS_COM_CFG => x"1680a0e",
TERMINATION_CTRL => "10100",
TERMINATION_OVRD => FALSE,
--------------------- RX Serial Line Rate Attributes ------------------
PLL_RXDIVSEL_OUT_0 => 2,
PLL_SATA_0 => FALSE,
PLL_RXDIVSEL_OUT_1 => 2,
PLL_SATA_1 => FALSE,
----------------------- PRBS Detection Attributes ---------------------
PRBS_ERR_THRESHOLD_0 => x"00000001",
PRBS_ERR_THRESHOLD_1 => x"00000001",
---------------- Comma Detection and Alignment Attributes -------------
ALIGN_COMMA_WORD_0 => 1,
COMMA_10B_ENABLE_0 => "1111111111",
COMMA_DOUBLE_0 => FALSE,
DEC_MCOMMA_DETECT_0 => FALSE,
DEC_PCOMMA_DETECT_0 => FALSE,
DEC_VALID_COMMA_ONLY_0 => FALSE,
MCOMMA_10B_VALUE_0 => "1010000011",
MCOMMA_DETECT_0 => FALSE,
PCOMMA_10B_VALUE_0 => "0101111100",
PCOMMA_DETECT_0 => FALSE,
RX_SLIDE_MODE_0 => "PCS",
ALIGN_COMMA_WORD_1 => 1,
COMMA_10B_ENABLE_1 => "1111111111",
COMMA_DOUBLE_1 => FALSE,
DEC_MCOMMA_DETECT_1 => FALSE,
DEC_PCOMMA_DETECT_1 => FALSE,
DEC_VALID_COMMA_ONLY_1 => FALSE,
MCOMMA_10B_VALUE_1 => "1010000011",
MCOMMA_DETECT_1 => FALSE,
PCOMMA_10B_VALUE_1 => "0101111100",
PCOMMA_DETECT_1 => FALSE,
RX_SLIDE_MODE_1 => "PCS",
------------------ RX Loss-of-sync State Machine Attributes -----------
RX_LOSS_OF_SYNC_FSM_0 => FALSE,
RX_LOS_INVALID_INCR_0 => 8,
RX_LOS_THRESHOLD_0 => 128,
RX_LOSS_OF_SYNC_FSM_1 => FALSE,
RX_LOS_INVALID_INCR_1 => 8,
RX_LOS_THRESHOLD_1 => 128,
-------------- RX Elastic Buffer and Phase alignment Attributes -------
RX_BUFFER_USE_0 => FALSE,
RX_XCLK_SEL_0 => "RXUSR",
RX_BUFFER_USE_1 => FALSE,
RX_XCLK_SEL_1 => "RXUSR",
------------------------ Clock Correction Attributes ------------------
CLK_CORRECT_USE_0 => FALSE,
CLK_COR_ADJ_LEN_0 => 1,
CLK_COR_DET_LEN_0 => 1,
CLK_COR_INSERT_IDLE_FLAG_0 => FALSE,
CLK_COR_KEEP_IDLE_0 => FALSE,
CLK_COR_MAX_LAT_0 => 18,
CLK_COR_MIN_LAT_0 => 16,
CLK_COR_PRECEDENCE_0 => TRUE,
CLK_COR_REPEAT_WAIT_0 => 0,
CLK_COR_SEQ_1_1_0 => "0000000000",
CLK_COR_SEQ_1_2_0 => "0000000000",
CLK_COR_SEQ_1_3_0 => "0000000000",
CLK_COR_SEQ_1_4_0 => "0000000000",
CLK_COR_SEQ_1_ENABLE_0 => "0000",
CLK_COR_SEQ_2_1_0 => "0000000000",
CLK_COR_SEQ_2_2_0 => "0000000000",
CLK_COR_SEQ_2_3_0 => "0000000000",
CLK_COR_SEQ_2_4_0 => "0000000000",
CLK_COR_SEQ_2_ENABLE_0 => "0000",
CLK_COR_SEQ_2_USE_0 => FALSE,
RX_DECODE_SEQ_MATCH_0 => FALSE,
CLK_CORRECT_USE_1 => FALSE,
CLK_COR_ADJ_LEN_1 => 1,
CLK_COR_DET_LEN_1 => 1,
CLK_COR_INSERT_IDLE_FLAG_1 => FALSE,
CLK_COR_KEEP_IDLE_1 => FALSE,
CLK_COR_MAX_LAT_1 => 18,
CLK_COR_MIN_LAT_1 => 16,
CLK_COR_PRECEDENCE_1 => TRUE,
CLK_COR_REPEAT_WAIT_1 => 0,
CLK_COR_SEQ_1_1_1 => "0000000000",
CLK_COR_SEQ_1_2_1 => "0000000000",
CLK_COR_SEQ_1_3_1 => "0000000000",
CLK_COR_SEQ_1_4_1 => "0000000000",
CLK_COR_SEQ_1_ENABLE_1 => "0000",
CLK_COR_SEQ_2_1_1 => "0000000000",
CLK_COR_SEQ_2_2_1 => "0000000000",
CLK_COR_SEQ_2_3_1 => "0000000000",
CLK_COR_SEQ_2_4_1 => "0000000000",
CLK_COR_SEQ_2_ENABLE_1 => "0000",
CLK_COR_SEQ_2_USE_1 => FALSE,
RX_DECODE_SEQ_MATCH_1 => FALSE,
------------------------ Channel Bonding Attributes -------------------
CHAN_BOND_1_MAX_SKEW_0 => 1,
CHAN_BOND_2_MAX_SKEW_0 => 1,
CHAN_BOND_LEVEL_0 => 0,
CHAN_BOND_MODE_0 => "OFF",
CHAN_BOND_SEQ_1_1_0 => "0000000000",
CHAN_BOND_SEQ_1_2_0 => "0000000000",
CHAN_BOND_SEQ_1_3_0 => "0000000000",
CHAN_BOND_SEQ_1_4_0 => "0000000000",
CHAN_BOND_SEQ_1_ENABLE_0 => "0001",
CHAN_BOND_SEQ_2_1_0 => "0000000000",
CHAN_BOND_SEQ_2_2_0 => "0000000000",
CHAN_BOND_SEQ_2_3_0 => "0000000000",
CHAN_BOND_SEQ_2_4_0 => "0000000000",
CHAN_BOND_SEQ_2_ENABLE_0 => "0000",
CHAN_BOND_SEQ_2_USE_0 => FALSE,
CHAN_BOND_SEQ_LEN_0 => 1,
PCI_EXPRESS_MODE_0 => FALSE,
CHAN_BOND_1_MAX_SKEW_1 => 1,
CHAN_BOND_2_MAX_SKEW_1 => 1,
CHAN_BOND_LEVEL_1 => 0,
CHAN_BOND_MODE_1 => "OFF",
CHAN_BOND_SEQ_1_1_1 => "0000000000",
CHAN_BOND_SEQ_1_2_1 => "0000000000",
CHAN_BOND_SEQ_1_3_1 => "0000000000",
CHAN_BOND_SEQ_1_4_1 => "0000000000",
CHAN_BOND_SEQ_1_ENABLE_1 => "0001",
CHAN_BOND_SEQ_2_1_1 => "0000000000",
CHAN_BOND_SEQ_2_2_1 => "0000000000",
CHAN_BOND_SEQ_2_3_1 => "0000000000",
CHAN_BOND_SEQ_2_4_1 => "0000000000",
CHAN_BOND_SEQ_2_ENABLE_1 => "0000",
CHAN_BOND_SEQ_2_USE_1 => FALSE,
CHAN_BOND_SEQ_LEN_1 => 1,
PCI_EXPRESS_MODE_1 => FALSE,
------------------ RX Attributes for PCI Express/SATA ---------------
RX_STATUS_FMT_0 => "PCIE",
SATA_BURST_VAL_0 => "100",
SATA_IDLE_VAL_0 => "100",
SATA_MAX_BURST_0 => 9,
SATA_MAX_INIT_0 => 27,
SATA_MAX_WAKE_0 => 9,
SATA_MIN_BURST_0 => 5,
SATA_MIN_INIT_0 => 15,
SATA_MIN_WAKE_0 => 5,
TRANS_TIME_FROM_P2_0 => x"003c",
TRANS_TIME_NON_P2_0 => x"0019",
TRANS_TIME_TO_P2_0 => x"0064",
RX_STATUS_FMT_1 => "PCIE",
SATA_BURST_VAL_1 => "100",
SATA_IDLE_VAL_1 => "100",
SATA_MAX_BURST_1 => 9,
SATA_MAX_INIT_1 => 27,
SATA_MAX_WAKE_1 => 9,
SATA_MIN_BURST_1 => 5,
SATA_MIN_INIT_1 => 15,
SATA_MIN_WAKE_1 => 5,
TRANS_TIME_FROM_P2_1 => x"003c",
TRANS_TIME_NON_P2_1 => x"0019",
TRANS_TIME_TO_P2_1 => x"0064"
)
port map (
------------------------ Loopback and Powerdown Ports ----------------------
LOOPBACK0 => tied_to_ground_vec_i(2 downto 0),
LOOPBACK1 => tied_to_ground_vec_i(2 downto 0),
RXPOWERDOWN0 => tied_to_ground_vec_i(1 downto 0),
RXPOWERDOWN1 => tied_to_ground_vec_i(1 downto 0),
TXPOWERDOWN0 => tied_to_ground_vec_i(1 downto 0),
TXPOWERDOWN1 => tied_to_ground_vec_i(1 downto 0),
----------------------- Receive Ports - 8b10b Decoder ----------------------
RXCHARISCOMMA0 => open,
RXCHARISCOMMA1 => open,
RXCHARISK0 => rxcharisk0_i(1 downto 0),
RXCHARISK1 => rxcharisk1_i(1 downto 0),
RXDEC8B10BUSE0 => tied_to_ground_i,
RXDEC8B10BUSE1 => tied_to_ground_i,
RXDISPERR0 => rxdisperr0_i(1 downto 0),
RXDISPERR1 => rxdisperr1_i(1 downto 0),
RXNOTINTABLE0 => open,
RXNOTINTABLE1 => open,
RXRUNDISP0 => open,
RXRUNDISP1 => open,
------------------- Receive Ports - Channel Bonding Ports ------------------
RXCHANBONDSEQ0 => open,
RXCHANBONDSEQ1 => open,
RXCHBONDI0 => tied_to_ground_vec_i(2 downto 0),
RXCHBONDI1 => tied_to_ground_vec_i(2 downto 0),
RXCHBONDO0 => open,
RXCHBONDO1 => open,
RXENCHANSYNC0 => tied_to_ground_i,
RXENCHANSYNC1 => tied_to_ground_i,
------------------- Receive Ports - Clock Correction Ports -----------------
RXCLKCORCNT0 => open,
RXCLKCORCNT1 => open,
--------------- Receive Ports - Comma Detection and Alignment --------------
RXBYTEISALIGNED0 => open,
RXBYTEISALIGNED1 => open,
RXBYTEREALIGN0 => open,
RXBYTEREALIGN1 => open,
RXCOMMADET0 => open,
RXCOMMADET1 => open,
RXCOMMADETUSE0 => tied_to_vcc_i,
RXCOMMADETUSE1 => tied_to_vcc_i,
RXENMCOMMAALIGN0 => tied_to_ground_i,
RXENMCOMMAALIGN1 => tied_to_ground_i,
RXENPCOMMAALIGN0 => tied_to_ground_i,
RXENPCOMMAALIGN1 => tied_to_ground_i,
RXSLIDE0 => bitslip,
RXSLIDE1 => bitslip,
----------------------- Receive Ports - PRBS Detection ---------------------
PRBSCNTRESET0 => tied_to_ground_i,
PRBSCNTRESET1 => tied_to_ground_i,
RXENPRBSTST0 => tied_to_ground_vec_i(1 downto 0),
RXENPRBSTST1 => tied_to_ground_vec_i(1 downto 0),
RXPRBSERR0 => open,
RXPRBSERR1 => open,
------------------- Receive Ports - RX Data Path interface -----------------
RXDATA0 => rxdata0_i(15 downto 0),
RXDATA1 => rxdata1_i(15 downto 0),
RXDATAWIDTH0 => tied_to_ground_i,
RXDATAWIDTH1 => tied_to_ground_i,
RXRECCLK0 => rx_rec_clk0_int,
RXRECCLK1 => rx_rec_clk1_int,
RXRESET0 => rx_rst_int,
RXRESET1 => rx_rst_int,
RXUSRCLK0 => rx_usrclk_int,
RXUSRCLK1 => rx_usrclk_int,
RXUSRCLK20 => rx_usrclk2_int,
RXUSRCLK21 => rx_usrclk2_int,
------- Receive Ports - RX Driver,OOB signalling,Coupling and Eq.,CDR ------
RXCDRRESET0 => tied_to_ground_i,
RXCDRRESET1 => tied_to_ground_i,
RXELECIDLE0 => rxelecidle0_i,
RXELECIDLE1 => rxelecidle1_i,
RXELECIDLERESET0 => tied_to_ground_i,
RXELECIDLERESET1 => tied_to_ground_i,
RXENEQB0 => tied_to_vcc_i,
RXENEQB1 => tied_to_vcc_i,
RXEQMIX0 => tied_to_ground_vec_i(1 downto 0),
RXEQMIX1 => tied_to_ground_vec_i(1 downto 0),
RXEQPOLE0 => tied_to_ground_vec_i(3 downto 0),
RXEQPOLE1 => tied_to_ground_vec_i(3 downto 0),
RXN0 => rx_in0_n,
RXN1 => rx_in1_n,
RXP0 => rx_in0_p,
RXP1 => rx_in1_p,
-------- Receive Ports - RX Elastic Buffer and Phase Alignment Ports -------
RXBUFRESET0 => tied_to_ground_i,
RXBUFRESET1 => tied_to_ground_i,
RXBUFSTATUS0 => open,
RXBUFSTATUS1 => open,
RXCHANISALIGNED0 => open,
RXCHANISALIGNED1 => open,
RXCHANREALIGN0 => open,
RXCHANREALIGN1 => open,
RXPMASETPHASE0 => tied_to_ground_i,
RXPMASETPHASE1 => tied_to_ground_i,
RXSTATUS0 => open,
RXSTATUS1 => open,
--------------- Receive Ports - RX Loss-of-sync State Machine --------------
RXLOSSOFSYNC0 => open,
RXLOSSOFSYNC1 => open,
---------------------- Receive Ports - RX Oversampling ---------------------
RXENSAMPLEALIGN0 => tied_to_ground_i,
RXENSAMPLEALIGN1 => tied_to_ground_i,
RXOVERSAMPLEERR0 => open,
RXOVERSAMPLEERR1 => open,
-------------- Receive Ports - RX Pipe Control for PCI Express -------------
PHYSTATUS0 => open,
PHYSTATUS1 => open,
RXVALID0 => open,
RXVALID1 => open,
----------------- Receive Ports - RX Polarity Control Ports ----------------
RXPOLARITY0 => tied_to_ground_i,
RXPOLARITY1 => tied_to_ground_i,
------------- Shared Ports - Dynamic Reconfiguration Port (DRP) ------------
DADDR => tied_to_ground_vec_i(6 downto 0),
DCLK => tied_to_ground_i,
DEN => tied_to_ground_i,
DI => tied_to_ground_vec_i(15 downto 0),
DO => open,
DRDY => open,
DWE => tied_to_ground_i,
--------------------- Shared Ports - Tile and PLL Ports --------------------
CLKIN => clk_125,
GTPRESET => rst_125,
GTPTEST => tied_to_ground_vec_i(3 downto 0),
INTDATAWIDTH => tied_to_vcc_i,
PLLLKDET => ref_clk_lock_int,
PLLLKDETEN => tied_to_vcc_i,
PLLPOWERDOWN => tied_to_ground_i,
REFCLKOUT => ref_clk_int,
REFCLKPWRDNB => tied_to_vcc_i,
RESETDONE0 => rst_done0_int,
RESETDONE1 => rst_done1_int,
RXENELECIDLERESETB => tied_to_vcc_i,
TXENPMAPHASEALIGN => tied_to_ground_i,
TXPMASETPHASE => tied_to_ground_i,
---------------- Transmit Ports - 8b10b Encoder Control Ports --------------
TXBYPASS8B10B0 => tied_to_ground_vec_i(1 downto 0),
TXBYPASS8B10B1 => tied_to_ground_vec_i(1 downto 0),
TXCHARDISPMODE0 => txchardispmode0_i(1 downto 0),
TXCHARDISPMODE1 => txchardispmode1_i(1 downto 0),
TXCHARDISPVAL0 => txchardispval0_i(1 downto 0),
TXCHARDISPVAL1 => txchardispval1_i(1 downto 0),
TXCHARISK0 => tied_to_ground_vec_i(1 downto 0),
TXCHARISK1 => tied_to_ground_vec_i(1 downto 0),
TXENC8B10BUSE0 => tied_to_ground_i,
TXENC8B10BUSE1 => tied_to_ground_i,
TXKERR0 => open,
TXKERR1 => open,
TXRUNDISP0 => open,
TXRUNDISP1 => open,
------------- Transmit Ports - TX Buffering and Phase Alignment ------------
TXBUFSTATUS0 => open,
TXBUFSTATUS1 => open,
------------------ Transmit Ports - TX Data Path interface -----------------
TXDATA0 => txdata0_i(15 downto 0),
TXDATA1 => txdata1_i(15 downto 0),
TXDATAWIDTH0 => tied_to_ground_i,
TXDATAWIDTH1 => tied_to_ground_i,
TXOUTCLK0 => open,
TXOUTCLK1 => open,
TXRESET0 => tx_rst_int,
TXRESET1 => tx_rst_int,
TXUSRCLK0 => tx_usrclk_int,
TXUSRCLK1 => tx_usrclk_int,
TXUSRCLK20 => tx_usrclk2_int,
TXUSRCLK21 => tx_usrclk2_int,
--------------- Transmit Ports - TX Driver and OOB signalling --------------
TXBUFDIFFCTRL0 => "000",
TXBUFDIFFCTRL1 => "000",
TXDIFFCTRL0 => "000",
TXDIFFCTRL1 => "000",
TXINHIBIT0 => tied_to_ground_i,
TXINHIBIT1 => tied_to_ground_i,
TXN0 => tx_out0_n,
TXN1 => tx_out1_n,
TXP0 => tx_out0_p,
TXP1 => tx_out1_p,
TXPREEMPHASIS0 => "000",
TXPREEMPHASIS1 => "000",
--------------------- Transmit Ports - TX PRBS Generator -------------------
TXENPRBSTST0 => tied_to_ground_vec_i(1 downto 0),
TXENPRBSTST1 => tied_to_ground_vec_i(1 downto 0),
-------------------- Transmit Ports - TX Polarity Control ------------------
TXPOLARITY0 => tied_to_ground_i,
TXPOLARITY1 => tied_to_ground_i,
----------------- Transmit Ports - TX Ports for PCI Express ----------------
TXDETECTRX0 => tied_to_ground_i,
TXDETECTRX1 => tied_to_ground_i,
TXELECIDLE0 => tied_to_ground_i,
TXELECIDLE1 => tied_to_ground_i,
--------------------- Transmit Ports - TX Ports for SATA -------------------
TXCOMSTART0 => tied_to_ground_i,
TXCOMSTART1 => tied_to_ground_i,
TXCOMTYPE0 => tied_to_ground_i,
TXCOMTYPE1 => tied_to_ground_i
);
end generate;
---- GTX_DUAL instantiation
inst_gtx0: if (transtech = GTX0) or (transtech = GTX1) generate
-- refclkout_dcm0: MGT_USRCLK_SOURCE
-- generic map
-- (
-- FREQUENCY_MODE => "LOW",
-- PERFORMANCE_MODE => "MAX_SPEED"
-- )
-- port map
-- (
-- DIV1_OUT => tx_usrclk2_int,
-- DIV2_OUT => tx_usrclk_int,
-- DCM_LOCKED_OUT => tx_usrclk_lock_int,
-- CLK_IN => ref_clk_buf_int,
-- DCM_RESET_IN => ref_clk_rst_int
-- );
-- Logic to apply DCM reset for 3 CLKIN cycles
process(ref_clk_buf_int, ref_clk_rst_int)
begin
if(ref_clk_rst_int='1') then
count_to_dcm_reset <= "00";
elsif(ref_clk_buf_int'event and ref_clk_buf_int='1') then
if(count_to_dcm_reset<"11") then
count_to_dcm_reset <= count_to_dcm_reset + '1';
else
count_to_dcm_reset <= count_to_dcm_reset;
end if;
end if;
end process;
reset_to_dcm <= '1' when (count_to_dcm_reset <"11") else
'0';
-- Instantiate a DCM module to divide the reference clock.
clock_divider_i : DCM_BASE
generic map
(
CLKDV_DIVIDE => 2.0,
DFS_FREQUENCY_MODE => "LOW",
DLL_FREQUENCY_MODE => "LOW",
DCM_PERFORMANCE_MODE => "MAX_SPEED"
)
port map
(
CLK0 => clk0_i,
CLK180 => open,
CLK270 => open,
CLK2X => open,
CLK2X180 => open,
CLK90 => open,
CLKDV => clkdv_i,
CLKFX => open,
CLKFX180 => open,
LOCKED => tx_usrclk_lock_int,
CLKFB => clkfb_i,
CLKIN => ref_clk_buf_int,
RST => reset_to_dcm
);
dcm_1x_bufg_i : BUFG
port map
(
I => clk0_i,
O => clkfb_i
);
tx_usrclk2_int <= clkfb_i;
dcm_div2_bufg_i : BUFG
port map
(
I => clkdv_i,
O => tx_usrclk_int
);
pll_adv_i : PLL_ADV
generic map
(
CLKFBOUT_MULT => 18,
DIVCLK_DIVIDE => 1,
CLKFBOUT_PHASE => 0.0,
CLKIN1_PERIOD => 16.0,
CLKIN2_PERIOD => 10.0, -- Not used
CLKOUT0_DIVIDE => 18,
CLKOUT0_PHASE => 0.0,
CLKOUT1_DIVIDE => 9,
CLKOUT1_PHASE => 0.0,
CLKOUT2_DIVIDE => 1,
CLKOUT2_PHASE => 0.0,
CLKOUT3_DIVIDE => 1,
CLKOUT3_PHASE => 0.0
)
port map
(
CLKIN1 => rx_rec_clk_buf_int,
CLKIN2 => tied_to_ground_i,
CLKINSEL => tied_to_vcc_i,
CLKFBIN => clkfbout_i,
CLKOUT0 => clkout0_i,
CLKOUT1 => clkout1_i,
CLKOUT2 => open,
CLKOUT3 => open,
CLKOUT4 => open,
CLKOUT5 => open,
CLKFBOUT => clkfbout_i,
CLKFBDCM => open,
CLKOUTDCM0 => open,
CLKOUTDCM1 => open,
CLKOUTDCM2 => open,
CLKOUTDCM3 => open,
CLKOUTDCM4 => open,
CLKOUTDCM5 => open,
DO => open,
DRDY => open,
DADDR => tied_to_ground_vec_i(4 downto 0),
DCLK => tied_to_ground_i,
DEN => tied_to_ground_i,
DI => tied_to_ground_vec_i(15 downto 0),
DWE => tied_to_ground_i,
REL => tied_to_ground_i,
LOCKED => pll_lk_out,
RST => ref_clk_rst_int
);
clkout0_bufg_i : BUFG
port map
(
O => rx_usrclk_int,
I => clkout0_i
);
clkout1_bufg_i : BUFG
port map
(
O => rx_usrclk2_int,
I => clkout1_i
);
--lockwait_count : if SIMULATION_P = 1 generate
--
-- -- lock not valid until 100us after PLL is released from reset
-- process(rx_rec_clk_buf_int, ref_clk_rst_int)
-- begin
-- if (ref_clk_rst_int = '1') then
-- lock_wait_counter <= "0000000000000000";
-- pll_locked_out_r <= '0';
-- time_elapsed <= '0';
-- elsif (rx_rec_clk_buf_int'event and rx_rec_clk_buf_int = '1') then
-- if (lock_wait_counter = "0001100001101010" or (time_elapsed = '1')) then
-- pll_locked_out_r <= pll_lk_out;
-- time_elapsed <= '1';
-- else
-- lock_wait_counter <= lock_wait_counter + 1;
-- end if;
-- end if;
-- end process;
--
-- rx_usrclk_lock_int <= pll_locked_out_r;
--
-- end generate lockwait_count; -- end SIMULATION_P=1 generate section
--
-- no_lockwait_count : if SIMULATION_P = 0 generate
rx_usrclk_lock_int <= pll_lk_out;
--end generate no_lockwait_count; -- End generate for SIMULATION_P
-- rxrecclk_pll1_i : MGT_USRCLK_SOURCE_PLL
-- generic map
-- (
-- MULT => 18,
-- DIVIDE => 1,
-- CLK_PERIOD => 16.0,
-- OUT0_DIVIDE => 18,
-- OUT1_DIVIDE => 9,
-- OUT2_DIVIDE => 1,
-- OUT3_DIVIDE => 1,
-- SIMULATION_P => 1,
-- LOCK_WAIT_COUNT => "0001100001101010"
-- )
-- port map
-- (
-- CLK0_OUT => rx_usrclk_int,
-- CLK1_OUT => rx_usrclk2_int,
-- CLK2_OUT => open,
-- CLK3_OUT => open,
-- CLK_IN => rx_rec_clk_buf_int,
-- PLL_LOCKED_OUT => rx_usrclk_lock_int,
-- PLL_RESET_IN => ref_clk_rst_int
-- );
tx_rst_int <= not tx_usrclk_lock_int;
rx_rst_int <= not rx_usrclk_lock_int;
gtx_dual_i: GTX_DUAL
generic map
(
--_______________________ Simulation-Only Attributes ___________________
SIM_RECEIVER_DETECT_PASS_0 => TRUE,
SIM_RECEIVER_DETECT_PASS_1 => TRUE,
SIM_MODE => "FAST",
SIM_GTXRESET_SPEEDUP => 0,
SIM_PLL_PERDIV2 => x"0c8",
--___________________________ Shared Attributes ________________________
-------------------------- Tile and PLL Attributes ---------------------
CLK25_DIVIDER => 5,
CLKINDC_B => TRUE,
CLKRCV_TRST => TRUE,
OOB_CLK_DIVIDER => 4,
OVERSAMPLE_MODE => FALSE,
PLL_COM_CFG => x"21680a",
PLL_CP_CFG => x"00",
PLL_DIVSEL_FB => 4,
PLL_DIVSEL_REF => 1,
PLL_FB_DCCEN => FALSE,
PLL_LKDET_CFG => "101",
PLL_TDCC_CFG => "000",
PMA_COM_CFG => x"000000000000000000",
--____________________ Transmit Interface Attributes ___________________
------------------- TX Buffering and Phase Alignment -------------------
TX_BUFFER_USE_0 => FALSE,
TX_XCLK_SEL_0 => "TXUSR",
TXRX_INVERT_0 => "111",
TX_BUFFER_USE_1 => FALSE,
TX_XCLK_SEL_1 => "TXUSR",
TXRX_INVERT_1 => "111",
--------------------- TX Gearbox Settings -----------------------------
GEARBOX_ENDEC_0 => "000",
TXGEARBOX_USE_0 => FALSE,
GEARBOX_ENDEC_1 => "000",
TXGEARBOX_USE_1 => FALSE,
--------------------- TX Serial Line Rate settings ---------------------
PLL_TXDIVSEL_OUT_0 => 4,
PLL_TXDIVSEL_OUT_1 => 4,
--------------------- TX Driver and OOB signalling --------------------
CM_TRIM_0 => "10",
PMA_TX_CFG_0 => x"80082",
TX_DETECT_RX_CFG_0 => x"1832",
TX_IDLE_DELAY_0 => "010",
CM_TRIM_1 => "10",
PMA_TX_CFG_1 => x"80082",
TX_DETECT_RX_CFG_1 => x"1832",
TX_IDLE_DELAY_1 => "010",
------------------ TX Pipe Control for PCI Express/SATA ---------------
COM_BURST_VAL_0 => "1111",
COM_BURST_VAL_1 => "1111",
--_______________________ Receive Interface Attributes ________________
------------ RX Driver,OOB signalling,Coupling and Eq,CDR -------------
AC_CAP_DIS_0 => TRUE,
OOBDETECT_THRESHOLD_0 => "111",
PMA_CDR_SCAN_0 => x"6404035",
PMA_RX_CFG_0 => x"0f44088",
RCV_TERM_GND_0 => FALSE,
RCV_TERM_VTTRX_0 => FALSE,
TERMINATION_IMP_0 => 50,
AC_CAP_DIS_1 => TRUE,
OOBDETECT_THRESHOLD_1 => "111",
PMA_CDR_SCAN_1 => x"6404035",
PMA_RX_CFG_1 => x"0f44088",
RCV_TERM_GND_1 => FALSE,
RCV_TERM_VTTRX_1 => FALSE,
TERMINATION_IMP_1 => 50,
TERMINATION_CTRL => "10100",
TERMINATION_OVRD => FALSE,
---------------- RX Decision Feedback Equalizer(DFE) ----------------
DFE_CFG_0 => "1001111011",
DFE_CFG_1 => "1001111011",
DFE_CAL_TIME => "00110",
--------------------- RX Serial Line Rate Attributes ------------------
PLL_RXDIVSEL_OUT_0 => 4,
PLL_SATA_0 => FALSE,
PLL_RXDIVSEL_OUT_1 => 4,
PLL_SATA_1 => FALSE,
----------------------- PRBS Detection Attributes ---------------------
PRBS_ERR_THRESHOLD_0 => x"00000001",
PRBS_ERR_THRESHOLD_1 => x"00000001",
---------------- Comma Detection and Alignment Attributes -------------
ALIGN_COMMA_WORD_0 => 1,
COMMA_10B_ENABLE_0 => "0001111111",
COMMA_DOUBLE_0 => FALSE,
DEC_MCOMMA_DETECT_0 => FALSE,
DEC_PCOMMA_DETECT_0 => FALSE,
DEC_VALID_COMMA_ONLY_0 => FALSE,
MCOMMA_10B_VALUE_0 => "1010000011",
MCOMMA_DETECT_0 => FALSE,
PCOMMA_10B_VALUE_0 => "0101111100",
PCOMMA_DETECT_0 => FALSE,
RX_SLIDE_MODE_0 => "PCS",
ALIGN_COMMA_WORD_1 => 1,
COMMA_10B_ENABLE_1 => "0001111111",
COMMA_DOUBLE_1 => FALSE,
DEC_MCOMMA_DETECT_1 => FALSE,
DEC_PCOMMA_DETECT_1 => FALSE,
DEC_VALID_COMMA_ONLY_1 => FALSE,
MCOMMA_10B_VALUE_1 => "1010000011",
MCOMMA_DETECT_1 => FALSE,
PCOMMA_10B_VALUE_1 => "0101111100",
PCOMMA_DETECT_1 => FALSE,
RX_SLIDE_MODE_1 => "PCS",
------------------ RX Loss-of-sync State Machine Attributes -----------
RX_LOSS_OF_SYNC_FSM_0 => FALSE,
RX_LOS_INVALID_INCR_0 => 8,
RX_LOS_THRESHOLD_0 => 128,
RX_LOSS_OF_SYNC_FSM_1 => FALSE,
RX_LOS_INVALID_INCR_1 => 8,
RX_LOS_THRESHOLD_1 => 128,
--------------------- RX Gearbox Settings -----------------------------
RXGEARBOX_USE_0 => FALSE,
RXGEARBOX_USE_1 => FALSE,
-------------- RX Elastic Buffer and Phase alignment Attributes -------
PMA_RXSYNC_CFG_0 => x"00",
RX_BUFFER_USE_0 => FALSE,
RX_XCLK_SEL_0 => "RXUSR",
PMA_RXSYNC_CFG_1 => x"00",
RX_BUFFER_USE_1 => FALSE,
RX_XCLK_SEL_1 => "RXUSR",
------------------------ Clock Correction Attributes ------------------
CLK_CORRECT_USE_0 => FALSE,
CLK_COR_ADJ_LEN_0 => 2,
CLK_COR_DET_LEN_0 => 2,
CLK_COR_INSERT_IDLE_FLAG_0 => FALSE,
CLK_COR_KEEP_IDLE_0 => FALSE,
CLK_COR_MAX_LAT_0 => 20,
CLK_COR_MIN_LAT_0 => 16,
CLK_COR_PRECEDENCE_0 => TRUE,
CLK_COR_REPEAT_WAIT_0 => 0,
CLK_COR_SEQ_1_1_0 => "0000000000",
CLK_COR_SEQ_1_2_0 => "0000000000",
CLK_COR_SEQ_1_3_0 => "0000000000",
CLK_COR_SEQ_1_4_0 => "0000000000",
CLK_COR_SEQ_1_ENABLE_0 => "0000",
CLK_COR_SEQ_2_1_0 => "0000000000",
CLK_COR_SEQ_2_2_0 => "0000000000",
CLK_COR_SEQ_2_3_0 => "0000000000",
CLK_COR_SEQ_2_4_0 => "0000000000",
CLK_COR_SEQ_2_ENABLE_0 => "0000",
CLK_COR_SEQ_2_USE_0 => FALSE,
RX_DECODE_SEQ_MATCH_0 => FALSE,
CLK_CORRECT_USE_1 => FALSE,
CLK_COR_ADJ_LEN_1 => 2,
CLK_COR_DET_LEN_1 => 2,
CLK_COR_INSERT_IDLE_FLAG_1 => FALSE,
CLK_COR_KEEP_IDLE_1 => FALSE,
CLK_COR_MAX_LAT_1 => 20,
CLK_COR_MIN_LAT_1 => 16,
CLK_COR_PRECEDENCE_1 => TRUE,
CLK_COR_REPEAT_WAIT_1 => 0,
CLK_COR_SEQ_1_1_1 => "0000000000",
CLK_COR_SEQ_1_2_1 => "0000000000",
CLK_COR_SEQ_1_3_1 => "0000000000",
CLK_COR_SEQ_1_4_1 => "0000000000",
CLK_COR_SEQ_1_ENABLE_1 => "0000",
CLK_COR_SEQ_2_1_1 => "0000000000",
CLK_COR_SEQ_2_2_1 => "0000000000",
CLK_COR_SEQ_2_3_1 => "0000000000",
CLK_COR_SEQ_2_4_1 => "0000000000",
CLK_COR_SEQ_2_ENABLE_1 => "0000",
CLK_COR_SEQ_2_USE_1 => FALSE,
RX_DECODE_SEQ_MATCH_1 => FALSE,
------------------------ Channel Bonding Attributes -------------------
CB2_INH_CC_PERIOD_0 => 8,
CHAN_BOND_1_MAX_SKEW_0 => 1,
CHAN_BOND_2_MAX_SKEW_0 => 1,
CHAN_BOND_KEEP_ALIGN_0 => FALSE,
CHAN_BOND_LEVEL_0 => 0,
CHAN_BOND_MODE_0 => "OFF",
CHAN_BOND_SEQ_1_1_0 => "0000000000",
CHAN_BOND_SEQ_1_2_0 => "0000000000",
CHAN_BOND_SEQ_1_3_0 => "0000000000",
CHAN_BOND_SEQ_1_4_0 => "0000000000",
CHAN_BOND_SEQ_1_ENABLE_0 => "0000",
CHAN_BOND_SEQ_2_1_0 => "0000000000",
CHAN_BOND_SEQ_2_2_0 => "0000000000",
CHAN_BOND_SEQ_2_3_0 => "0000000000",
CHAN_BOND_SEQ_2_4_0 => "0000000000",
CHAN_BOND_SEQ_2_ENABLE_0 => "0000",
CHAN_BOND_SEQ_2_USE_0 => FALSE,
CHAN_BOND_SEQ_LEN_0 => 1,
PCI_EXPRESS_MODE_0 => FALSE,
CB2_INH_CC_PERIOD_1 => 8,
CHAN_BOND_1_MAX_SKEW_1 => 1,
CHAN_BOND_2_MAX_SKEW_1 => 1,
CHAN_BOND_KEEP_ALIGN_1 => FALSE,
CHAN_BOND_LEVEL_1 => 0,
CHAN_BOND_MODE_1 => "OFF",
CHAN_BOND_SEQ_1_1_1 => "0000000000",
CHAN_BOND_SEQ_1_2_1 => "0000000000",
CHAN_BOND_SEQ_1_3_1 => "0000000000",
CHAN_BOND_SEQ_1_4_1 => "0000000000",
CHAN_BOND_SEQ_1_ENABLE_1 => "0000",
CHAN_BOND_SEQ_2_1_1 => "0000000000",
CHAN_BOND_SEQ_2_2_1 => "0000000000",
CHAN_BOND_SEQ_2_3_1 => "0000000000",
CHAN_BOND_SEQ_2_4_1 => "0000000000",
CHAN_BOND_SEQ_2_ENABLE_1 => "0000",
CHAN_BOND_SEQ_2_USE_1 => FALSE,
CHAN_BOND_SEQ_LEN_1 => 1,
PCI_EXPRESS_MODE_1 => FALSE,
-------- RX Attributes to Control Reset after Electrical Idle ------
RX_EN_IDLE_HOLD_DFE_0 => TRUE,
RX_EN_IDLE_RESET_BUF_0 => TRUE,
RX_IDLE_HI_CNT_0 => "1000",
RX_IDLE_LO_CNT_0 => "0000",
RX_EN_IDLE_HOLD_DFE_1 => TRUE,
RX_EN_IDLE_RESET_BUF_1 => TRUE,
RX_IDLE_HI_CNT_1 => "1000",
RX_IDLE_LO_CNT_1 => "0000",
CDR_PH_ADJ_TIME => "01010",
RX_EN_IDLE_RESET_FR => TRUE,
RX_EN_IDLE_HOLD_CDR => FALSE,
RX_EN_IDLE_RESET_PH => TRUE,
------------------ RX Attributes for PCI Express/SATA ---------------
RX_STATUS_FMT_0 => "PCIE",
SATA_BURST_VAL_0 => "100",
SATA_IDLE_VAL_0 => "100",
SATA_MAX_BURST_0 => 9,
SATA_MAX_INIT_0 => 27,
SATA_MAX_WAKE_0 => 9,
SATA_MIN_BURST_0 => 5,
SATA_MIN_INIT_0 => 15,
SATA_MIN_WAKE_0 => 5,
TRANS_TIME_FROM_P2_0 => x"003c",
TRANS_TIME_NON_P2_0 => x"0019",
TRANS_TIME_TO_P2_0 => x"0064",
RX_STATUS_FMT_1 => "PCIE",
SATA_BURST_VAL_1 => "100",
SATA_IDLE_VAL_1 => "100",
SATA_MAX_BURST_1 => 9,
SATA_MAX_INIT_1 => 27,
SATA_MAX_WAKE_1 => 9,
SATA_MIN_BURST_1 => 5,
SATA_MIN_INIT_1 => 15,
SATA_MIN_WAKE_1 => 5,
TRANS_TIME_FROM_P2_1 => x"003c",
TRANS_TIME_NON_P2_1 => x"0019",
TRANS_TIME_TO_P2_1 => x"0064"
)
port map
(
------------------------ Loopback and Powerdown Ports ----------------------
LOOPBACK0 => tied_to_ground_vec_i(2 downto 0),
LOOPBACK1 => tied_to_ground_vec_i(2 downto 0),
RXPOWERDOWN0 => tied_to_ground_vec_i(1 downto 0),
RXPOWERDOWN1 => tied_to_ground_vec_i(1 downto 0),
TXPOWERDOWN0 => tied_to_ground_vec_i(1 downto 0),
TXPOWERDOWN1 => tied_to_ground_vec_i(1 downto 0),
-------------- Receive Ports - 64b66b and 64b67b Gearbox Ports -------------
RXDATAVALID0 => open,
RXDATAVALID1 => open,
RXGEARBOXSLIP0 => tied_to_ground_i,
RXGEARBOXSLIP1 => tied_to_ground_i,
RXHEADER0 => open,
RXHEADER1 => open,
RXHEADERVALID0 => open,
RXHEADERVALID1 => open,
RXSTARTOFSEQ0 => open,
RXSTARTOFSEQ1 => open,
----------------------- Receive Ports - 8b10b Decoder ----------------------
RXCHARISCOMMA0 => open,
RXCHARISCOMMA1 => open,
RXCHARISK0 => rxcharisk0_i,
RXCHARISK1 => rxcharisk1_i,
RXDEC8B10BUSE0 => tied_to_ground_i,
RXDEC8B10BUSE1 => tied_to_ground_i,
RXDISPERR0 => rxdisperr0_i,
RXDISPERR1 => rxdisperr1_i,
RXNOTINTABLE0 => open,
RXNOTINTABLE1 => open,
RXRUNDISP0 => open,
RXRUNDISP1 => open,
------------------- Receive Ports - Channel Bonding Ports ------------------
RXCHANBONDSEQ0 => open,
RXCHANBONDSEQ1 => open,
RXCHBONDI0 => tied_to_ground_vec_i(3 downto 0),
RXCHBONDI1 => tied_to_ground_vec_i(3 downto 0),
RXCHBONDO0 => open,
RXCHBONDO1 => open,
RXENCHANSYNC0 => tied_to_ground_i,
RXENCHANSYNC1 => tied_to_ground_i,
------------------- Receive Ports - Clock Correction Ports -----------------
RXCLKCORCNT0 => open,
RXCLKCORCNT1 => open,
--------------- Receive Ports - Comma Detection and Alignment --------------
RXBYTEISALIGNED0 => open,
RXBYTEISALIGNED1 => open,
RXBYTEREALIGN0 => open,
RXBYTEREALIGN1 => open,
RXCOMMADET0 => open,
RXCOMMADET1 => open,
RXCOMMADETUSE0 => tied_to_vcc_i,
RXCOMMADETUSE1 => tied_to_vcc_i,
RXENMCOMMAALIGN0 => tied_to_ground_i,
RXENMCOMMAALIGN1 => tied_to_ground_i,
RXENPCOMMAALIGN0 => tied_to_ground_i,
RXENPCOMMAALIGN1 => tied_to_ground_i,
RXSLIDE0 => bitslip,
RXSLIDE1 => bitslip,
----------------------- Receive Ports - PRBS Detection ---------------------
PRBSCNTRESET0 => tied_to_ground_i,
PRBSCNTRESET1 => tied_to_ground_i,
RXENPRBSTST0 => tied_to_ground_vec_i(1 downto 0),
RXENPRBSTST1 => tied_to_ground_vec_i(1 downto 0),
RXPRBSERR0 => open,
RXPRBSERR1 => open,
------------------- Receive Ports - RX Data Path interface -----------------
RXDATA0 => rxdata0_i,
RXDATA1 => rxdata1_i,
RXDATAWIDTH0 => "00",
RXDATAWIDTH1 => "00",
RXRECCLK0 => rx_rec_clk0_int,
RXRECCLK1 => rx_rec_clk1_int,
RXRESET0 => rx_rst_int,
RXRESET1 => rx_rst_int,
RXUSRCLK0 => rx_usrclk_int,
RXUSRCLK1 => rx_usrclk_int,
RXUSRCLK20 => rx_usrclk2_int,
RXUSRCLK21 => rx_usrclk2_int,
------------ Receive Ports - RX Decision Feedback Equalizer(DFE) -----------
DFECLKDLYADJ0 => tied_to_ground_vec_i(5 downto 0),
DFECLKDLYADJ1 => tied_to_ground_vec_i(5 downto 0),
DFECLKDLYADJMONITOR0 => open,
DFECLKDLYADJMONITOR1 => open,
DFEEYEDACMONITOR0 => open,
DFEEYEDACMONITOR1 => open,
DFESENSCAL0 => open,
DFESENSCAL1 => open,
DFETAP10 => tied_to_ground_vec_i(4 downto 0),
DFETAP11 => tied_to_ground_vec_i(4 downto 0),
DFETAP1MONITOR0 => open,
DFETAP1MONITOR1 => open,
DFETAP20 => tied_to_ground_vec_i(4 downto 0),
DFETAP21 => tied_to_ground_vec_i(4 downto 0),
DFETAP2MONITOR0 => open,
DFETAP2MONITOR1 => open,
DFETAP30 => tied_to_ground_vec_i(3 downto 0),
DFETAP31 => tied_to_ground_vec_i(3 downto 0),
DFETAP3MONITOR0 => open,
DFETAP3MONITOR1 => open,
DFETAP40 => tied_to_ground_vec_i(3 downto 0),
DFETAP41 => tied_to_ground_vec_i(3 downto 0),
DFETAP4MONITOR0 => open,
DFETAP4MONITOR1 => open,
------- Receive Ports - RX Driver,OOB signalling,Coupling and Eq.,CDR ------
RXCDRRESET0 => tied_to_ground_i,
RXCDRRESET1 => tied_to_ground_i,
RXELECIDLE0 => open,
RXELECIDLE1 => open,
RXENEQB0 => tied_to_ground_i,
RXENEQB1 => tied_to_ground_i,
RXEQMIX0 => "11",
RXEQMIX1 => "11",
RXEQPOLE0 => "0000",
RXEQPOLE1 => "0000",
RXN0 => rx_in0_n,
RXN1 => rx_in1_n,
RXP0 => rx_in0_p,
RXP1 => rx_in1_p,
-------- Receive Ports - RX Elastic Buffer and Phase Alignment Ports -------
RXBUFRESET0 => tied_to_ground_i,
RXBUFRESET1 => tied_to_ground_i,
RXBUFSTATUS0 => open,
RXBUFSTATUS1 => open,
RXCHANISALIGNED0 => open,
RXCHANISALIGNED1 => open,
RXCHANREALIGN0 => open,
RXCHANREALIGN1 => open,
RXENPMAPHASEALIGN0 => tied_to_ground_i,
RXENPMAPHASEALIGN1 => tied_to_ground_i,
RXPMASETPHASE0 => tied_to_ground_i,
RXPMASETPHASE1 => tied_to_ground_i,
RXSTATUS0 => open,
RXSTATUS1 => open,
--------------- Receive Ports - RX Loss-of-sync State Machine --------------
RXLOSSOFSYNC0 => open,
RXLOSSOFSYNC1 => open,
---------------------- Receive Ports - RX Oversampling ---------------------
RXENSAMPLEALIGN0 => tied_to_ground_i,
RXENSAMPLEALIGN1 => tied_to_ground_i,
RXOVERSAMPLEERR0 => open,
RXOVERSAMPLEERR1 => open,
-------------- Receive Ports - RX Pipe Control for PCI Express -------------
PHYSTATUS0 => open,
PHYSTATUS1 => open,
RXVALID0 => open,
RXVALID1 => open,
----------------- Receive Ports - RX Polarity Control Ports ----------------
RXPOLARITY0 => tied_to_ground_i,
RXPOLARITY1 => tied_to_ground_i,
------------- Shared Ports - Dynamic Reconfiguration Port (DRP) ------------
DADDR => tied_to_ground_vec_i(6 downto 0),
DCLK => tied_to_ground_i,
DEN => tied_to_ground_i,
DI => tied_to_ground_vec_i(15 downto 0),
DO => open,
DRDY => open,
DWE => tied_to_ground_i,
--------------------- Shared Ports - Tile and PLL Ports --------------------
CLKIN => clk_125,
GTXRESET => rst_125,
GTXTEST => "10000000000000",
INTDATAWIDTH => tied_to_vcc_i,
PLLLKDET => ref_clk_lock_int,
PLLLKDETEN => tied_to_vcc_i,
PLLPOWERDOWN => tied_to_ground_i,
REFCLKOUT => ref_clk_int,
REFCLKPWRDNB => tied_to_vcc_i,
RESETDONE0 => rst_done0_int,
RESETDONE1 => rst_done1_int,
-------------- Transmit Ports - 64b66b and 64b67b Gearbox Ports ------------
TXGEARBOXREADY0 => open,
TXGEARBOXREADY1 => open,
TXHEADER0 => tied_to_ground_vec_i(2 downto 0),
TXHEADER1 => tied_to_ground_vec_i(2 downto 0),
TXSEQUENCE0 => tied_to_ground_vec_i(6 downto 0),
TXSEQUENCE1 => tied_to_ground_vec_i(6 downto 0),
TXSTARTSEQ0 => tied_to_ground_i,
TXSTARTSEQ1 => tied_to_ground_i,
---------------- Transmit Ports - 8b10b Encoder Control Ports --------------
TXBYPASS8B10B0 => tied_to_ground_vec_i(3 downto 0),
TXBYPASS8B10B1 => tied_to_ground_vec_i(3 downto 0),
TXCHARDISPMODE0 => txchardispmode0_i,
TXCHARDISPMODE1 => txchardispmode1_i,
TXCHARDISPVAL0 => txchardispval0_i,
TXCHARDISPVAL1 => txchardispval1_i,
TXCHARISK0 => tied_to_ground_vec_i(3 downto 0),
TXCHARISK1 => tied_to_ground_vec_i(3 downto 0),
TXENC8B10BUSE0 => tied_to_ground_i,
TXENC8B10BUSE1 => tied_to_ground_i,
TXKERR0 => open,
TXKERR1 => open,
TXRUNDISP0 => open,
TXRUNDISP1 => open,
------------- Transmit Ports - TX Buffering and Phase Alignment ------------
TXBUFSTATUS0 => open,
TXBUFSTATUS1 => open,
------------------ Transmit Ports - TX Data Path interface -----------------
TXDATA0 => txdata0_i,
TXDATA1 => txdata1_i,
TXDATAWIDTH0 => "00",
TXDATAWIDTH1 => "00",
TXOUTCLK0 => open,
TXOUTCLK1 => open,
TXRESET0 => tx_rst_int,
TXRESET1 => tx_rst_int,
TXUSRCLK0 => tx_usrclk_int,
TXUSRCLK1 => tx_usrclk_int,
TXUSRCLK20 => tx_usrclk2_int,
TXUSRCLK21 => tx_usrclk2_int,
--------------- Transmit Ports - TX Driver and OOB signalling --------------
TXBUFDIFFCTRL0 => "101",
TXBUFDIFFCTRL1 => "101",
TXDIFFCTRL0 => "000",
TXDIFFCTRL1 => "000",
TXINHIBIT0 => tied_to_ground_i,
TXINHIBIT1 => tied_to_ground_i,
TXN0 => tx_out0_n,
TXN1 => tx_out1_n,
TXP0 => tx_out0_p,
TXP1 => tx_out1_p,
TXPREEMPHASIS0 => "0000",
TXPREEMPHASIS1 => "0000",
-------- Transmit Ports - TX Elastic Buffer and Phase Alignment Ports ------
TXENPMAPHASEALIGN0 => tied_to_ground_i,
TXENPMAPHASEALIGN1 => tied_to_ground_i,
TXPMASETPHASE0 => tied_to_ground_i,
TXPMASETPHASE1 => tied_to_ground_i,
--------------------- Transmit Ports - TX PRBS Generator -------------------
TXENPRBSTST0 => tied_to_ground_vec_i(1 downto 0),
TXENPRBSTST1 => tied_to_ground_vec_i(1 downto 0),
-------------------- Transmit Ports - TX Polarity Control ------------------
TXPOLARITY0 => tied_to_ground_i,
TXPOLARITY1 => tied_to_ground_i,
----------------- Transmit Ports - TX Ports for PCI Express ----------------
TXDETECTRX0 => tied_to_ground_i,
TXDETECTRX1 => tied_to_ground_i,
TXELECIDLE0 => tied_to_ground_i,
TXELECIDLE1 => tied_to_ground_i,
--------------------- Transmit Ports - TX Ports for SATA -------------------
TXCOMSTART0 => tied_to_ground_i,
TXCOMSTART1 => tied_to_ground_i,
TXCOMTYPE0 => tied_to_ground_i,
TXCOMTYPE1 => tied_to_ground_i
);
end generate;
end architecture ;
| gpl-3.0 | d77994eea53fe39190291aad82b6602c | 0.376514 | 4.26984 | false | false | false | false |
EliasLuiz/TCC | Leon3/designs/leon3-altera-de2-ep2c35/config.vhd | 1 | 5,955 |
-----------------------------------------------------------------------------
-- LEON3 Demonstration design test bench configuration
-- Copyright (C) 2009 Aeroflex Gaisler
------------------------------------------------------------------------------
library techmap;
use techmap.gencomp.all;
package config is
-- Technology and synthesis options
constant CFG_FABTECH : integer := stratix2;
constant CFG_MEMTECH : integer := stratix2;
constant CFG_PADTECH : integer := stratix2;
constant CFG_TRANSTECH : integer := GTP0;
constant CFG_NOASYNC : integer := 0;
constant CFG_SCAN : integer := 0;
-- Clock generator
constant CFG_CLKTECH : integer := stratix2;
constant CFG_CLKMUL : integer := (5);
constant CFG_CLKDIV : integer := (5);
constant CFG_OCLKDIV : integer := 1;
constant CFG_OCLKBDIV : integer := 0;
constant CFG_OCLKCDIV : integer := 0;
constant CFG_PCIDLL : integer := 0;
constant CFG_PCISYSCLK: integer := 0;
constant CFG_CLK_NOFB : integer := 0;
-- LEON3 processor core
constant CFG_LEON3 : integer := 1;
constant CFG_NCPU : integer := (1);
constant CFG_NWIN : integer := (8);
constant CFG_V8 : integer := 16#32# + 4*0;
constant CFG_MAC : integer := 0;
constant CFG_BP : integer := 1;
constant CFG_SVT : integer := 1;
constant CFG_RSTADDR : integer := 16#00000#;
constant CFG_LDDEL : integer := (1);
constant CFG_NOTAG : integer := 0;
constant CFG_NWP : integer := (2);
constant CFG_PWD : integer := 1*2;
constant CFG_FPU : integer := 0 + 16*0 + 32*0;
constant CFG_GRFPUSH : integer := 0;
constant CFG_ICEN : integer := 1;
constant CFG_ISETS : integer := 2;
constant CFG_ISETSZ : integer := 4;
constant CFG_ILINE : integer := 8;
constant CFG_IREPL : integer := 2;
constant CFG_ILOCK : integer := 0;
constant CFG_ILRAMEN : integer := 0;
constant CFG_ILRAMADDR: integer := 16#8E#;
constant CFG_ILRAMSZ : integer := 1;
constant CFG_DCEN : integer := 1;
constant CFG_DSETS : integer := 1;
constant CFG_DSETSZ : integer := 4;
constant CFG_DLINE : integer := 4;
constant CFG_DREPL : integer := 0;
constant CFG_DLOCK : integer := 0;
constant CFG_DSNOOP : integer := 0 + 0*2 + 4*0;
constant CFG_DFIXED : integer := 16#0#;
constant CFG_DLRAMEN : integer := 0;
constant CFG_DLRAMADDR: integer := 16#8F#;
constant CFG_DLRAMSZ : integer := 1;
constant CFG_MMUEN : integer := 0;
constant CFG_ITLBNUM : integer := 2;
constant CFG_DTLBNUM : integer := 2;
constant CFG_TLB_TYPE : integer := 1 + 0*2;
constant CFG_TLB_REP : integer := 1;
constant CFG_MMU_PAGE : integer := 0;
constant CFG_DSU : integer := 1;
constant CFG_ITBSZ : integer := 2 + 64*0;
constant CFG_ATBSZ : integer := 2;
constant CFG_AHBPF : integer := 0;
constant CFG_LEON3FT_EN : integer := 0;
constant CFG_IUFT_EN : integer := 0;
constant CFG_FPUFT_EN : integer := 0;
constant CFG_RF_ERRINJ : integer := 0;
constant CFG_CACHE_FT_EN : integer := 0;
constant CFG_CACHE_ERRINJ : integer := 0;
constant CFG_LEON3_NETLIST: integer := 0;
constant CFG_DISAS : integer := 0 + 0;
constant CFG_PCLOW : integer := 2;
constant CFG_STAT_ENABLE : integer := 0;
constant CFG_STAT_CNT : integer := 1;
constant CFG_STAT_NMAX : integer := 0;
constant CFG_STAT_DSUEN : integer := 0;
constant CFG_NP_ASI : integer := 0;
constant CFG_WRPSR : integer := 0;
constant CFG_ALTWIN : integer := 0;
constant CFG_REX : integer := 0;
-- AMBA settings
constant CFG_DEFMST : integer := (0);
constant CFG_RROBIN : integer := 1;
constant CFG_SPLIT : integer := 0;
constant CFG_FPNPEN : integer := 0;
constant CFG_AHBIO : integer := 16#FFF#;
constant CFG_APBADDR : integer := 16#800#;
constant CFG_AHB_MON : integer := 0;
constant CFG_AHB_MONERR : integer := 0;
constant CFG_AHB_MONWAR : integer := 0;
constant CFG_AHB_DTRACE : integer := 0;
-- DSU UART
constant CFG_AHB_UART : integer := 1;
-- JTAG based DSU interface
constant CFG_AHB_JTAG : integer := 1;
-- SDRAM controller
constant CFG_SDCTRL : integer := 1;
constant CFG_SDCTRL_INVCLK : integer := 0;
constant CFG_SDCTRL_SD64 : integer := 0;
constant CFG_SDCTRL_PAGE : integer := 0 + 0;
-- LEON2 memory controller
constant CFG_MCTRL_LEON2 : integer := 1;
constant CFG_MCTRL_RAM8BIT : integer := 1;
constant CFG_MCTRL_RAM16BIT : integer := 0;
constant CFG_MCTRL_5CS : integer := 0;
constant CFG_MCTRL_SDEN : integer := 0;
constant CFG_MCTRL_SEPBUS : integer := 0;
constant CFG_MCTRL_INVCLK : integer := 0;
constant CFG_MCTRL_SD64 : integer := 0;
constant CFG_MCTRL_PAGE : integer := 0 + 0;
-- AHB status register
constant CFG_AHBSTAT : integer := 1;
constant CFG_AHBSTATN : integer := (1);
-- AHB RAM
constant CFG_AHBRAMEN : integer := 0;
constant CFG_AHBRSZ : integer := 1;
constant CFG_AHBRADDR : integer := 16#A00#;
constant CFG_AHBRPIPE : integer := 0;
-- UART 1
constant CFG_UART1_ENABLE : integer := 1;
constant CFG_UART1_FIFO : integer := 4;
-- LEON3 interrupt controller
constant CFG_IRQ3_ENABLE : integer := 1;
constant CFG_IRQ3_NSEC : integer := 0;
-- Modular timer
constant CFG_GPT_ENABLE : integer := 1;
constant CFG_GPT_NTIM : integer := (2);
constant CFG_GPT_SW : integer := (16);
constant CFG_GPT_TW : integer := (32);
constant CFG_GPT_IRQ : integer := (8);
constant CFG_GPT_SEPIRQ : integer := 1;
constant CFG_GPT_WDOGEN : integer := 0;
constant CFG_GPT_WDOG : integer := 16#0#;
-- GPIO port
constant CFG_GRGPIO_ENABLE : integer := 1;
constant CFG_GRGPIO_IMASK : integer := 16#fe#;
constant CFG_GRGPIO_WIDTH : integer := (32);
-- Second GPIO port
constant CFG_GRGPIO2_ENABLE : integer := 1;
constant CFG_GRGPIO2_IMASK : integer := 16#fe#;
constant CFG_GRGPIO2_WIDTH : integer := (32);
-- VGA and PS2/ interface
constant CFG_KBD_ENABLE : integer := 1;
constant CFG_VGA_ENABLE : integer := 0;
constant CFG_SVGA_ENABLE : integer := 1;
-- GRLIB debugging
constant CFG_DUART : integer := 0;
end;
| gpl-3.0 | 04a0bc9fb400140671d8700752f04b0e | 0.64534 | 3.633313 | false | false | false | false |
EliasLuiz/TCC | Leon3/lib/techmap/eclipsee/memory_eclipse.vhd | 1 | 4,714 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: various
-- File: memory_eclipse.vhd
-- Author: Jiri Gaisler Gaisler Research
-- Description: Memory generators for Quicklogic Eclipse rams
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
-- translate_off
library eclipsee;
use eclipsee.all;
-- translate_on
entity eclipse_syncram_2p is
generic ( abits : integer := 8; dbits : integer := 32);
port (
rclk : in std_ulogic;
rena : in std_ulogic;
raddr : in std_logic_vector (abits -1 downto 0);
dout : out std_logic_vector (dbits -1 downto 0);
wclk : in std_ulogic;
waddr : in std_logic_vector (abits -1 downto 0);
din : in std_logic_vector (dbits -1 downto 0);
write : in std_ulogic);
end;
architecture rtl of eclipse_syncram_2p is
component RAM128X18_25um is
port (WA, RA : in std_logic_vector (6 downto 0);
WD : in std_logic_vector (17 downto 0);
WE, RE, WCLK, RCLK, ASYNCRD : in std_logic;
RD : out std_logic_vector (17 downto 0) );
end component;
component RAM256X9_25um is
port (WA, RA : in std_logic_vector (7 downto 0);
WD : in std_logic_vector (8 downto 0);
WE, RE, WCLK, RCLK, ASYNCRD : in std_logic;
RD : out std_logic_vector (8 downto 0) );
end component;
component RAM512X4_25um
port (WA, RA : in std_logic_vector (8 downto 0);
WD : in std_logic_vector (3 downto 0);
WE, RE, WCLK, RCLK, ASYNCRD : in std_logic;
RD : out std_logic_vector (3 downto 0));
end component;
component RAM1024X2_25um is
port (WA, RA : in std_logic_vector (9 downto 0);
WD : in std_logic_vector (1 downto 0);
WE, RE, WCLK, RCLK, ASYNCRD : in std_logic;
RD : out std_logic_vector (1 downto 0) );
end component;
constant dlen : integer := dbits + 18;
signal di1, q2, gnd : std_logic_vector(dlen downto 0);
signal a1, a2 : std_logic_vector(12 downto 0);
begin
gnd <= (others => '0');
di1(dbits-1 downto 0) <= din; di1(dlen downto dbits) <= (others => '0');
a1(abits-1 downto 0) <= waddr; a1(12 downto abits) <= (others => '0');
a2(abits-1 downto 0) <= raddr; a2(12 downto abits) <= (others => '0');
dout <= q2(dbits-1 downto 0); q2(dlen downto dbits) <= (others => '0');
a7 : if (abits <= 7) generate
x : for i in 0 to (dbits-1)/18 generate
u0 : RAM128X18_25um port map (
a1(6 downto 0), a2(6 downto 0), di1(i*18+17 downto i*18),
write, rena, wclk, rclk, gnd(0), q2(i*18+17 downto i*18));
end generate;
end generate;
a8 : if (abits = 8) generate
x : for i in 0 to (dbits-1)/9 generate
u0 : RAM256X9_25um port map (
a1(7 downto 0), a2(7 downto 0), di1(i*9+8 downto i*9),
write, rena, wclk, rclk, gnd(0), q2(i*9+8 downto i*9));
end generate;
end generate;
a9 : if (abits = 9) generate
x : for i in 0 to (dbits-1)/4 generate
u0 : RAM512X4_25um port map (
a1(8 downto 0), a2(8 downto 0), di1(i*4+3 downto i*4),
write, rena, wclk, rclk, gnd(0), q2(i*4+3 downto i*4));
end generate;
end generate;
a10 : if (abits = 10) generate
x : for i in 0 to (dbits-1)/2 generate
u0 : RAM1024X2_25um port map (
a1(9 downto 0), a2(9 downto 0), di1(i*2+1 downto i*2),
write, rena, wclk, rclk, gnd(0), q2(i*2+1 downto i*2));
end generate;
end generate;
-- pragma translate_off
unsup : if abits > 10 generate
x : process
begin
assert false
report "Address depth larger than 10 is not supported for Eclipse rams"
severity failure;
wait;
end process;
end generate;
-- pragma translate_on
end;
| gpl-3.0 | b4da9125052d82dcf89bc860ddeae3cf | 0.606703 | 3.338527 | false | false | false | false |
EliasLuiz/TCC | Leon3/lib/gaisler/sim/ahbram_sim.vhd | 1 | 11,868 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: ahbram
-- File: ahbram.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Modified: Jan Andersson - Aeroflex Gaisler
-- Description: AHB ram. 0-waitstate read, 0/1-waitstate write.
-- Added Sx-Record read function
------------------------------------------------------------------------------
-- pragma translate_off
library ieee;
use ieee.std_logic_1164.all;
use std.textio.all;
use IEEE.Numeric_Std.all;
library grlib;
use grlib.config_types.all;
use grlib.config.all;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
use grlib.stdio.all;
library techmap;
use techmap.gencomp.all;
entity ahbram_sim is
generic (
hindex : integer := 0;
haddr : integer := 0;
hmask : integer := 16#fff#;
tech : integer := DEFMEMTECH;
kbytes : integer := 1;
pipe : integer := 0;
maccsz : integer := AHBDW;
fname : string := "ram.dat"
);
port (
rst : in std_ulogic;
clk : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type
);
end;
architecture rtl of ahbram_sim is
constant abits : integer := log2ext(kbytes) + 8 - maccsz/64;
constant dw : integer := maccsz;
constant hconfig : ahb_config_type := (
0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_AHBRAM, 0, abits+2+maccsz/64, 0),
4 => ahb_membar(haddr, '1', '1', hmask),
others => zero32);
type reg_type is record
hwrite : std_ulogic;
hready : std_ulogic;
hsel : std_ulogic;
addr : std_logic_vector(abits-1+log2(dw/8) downto 0);
size : std_logic_vector(2 downto 0);
prdata : std_logic_vector((dw-1)*pipe downto 0);
pwrite : std_ulogic;
pready : std_ulogic;
end record;
constant RESET_ALL : boolean := GRLIB_CONFIG_ARRAY(grlib_sync_reset_enable_all) = 1;
constant RES : reg_type :=
(hwrite => '0', hready => '1', hsel => '0', addr => (others => '0'),
size => (others => '0'), prdata => (others => '0'), pwrite => '0',
pready => '1');
signal r, c : reg_type;
signal ramsel : std_logic_vector(dw/8-1 downto 0);
signal write : std_logic_vector(dw/8-1 downto 0);
signal ramaddr : std_logic_vector(abits-1 downto 0);
signal ramdata : std_logic_vector(dw-1 downto 0);
signal hwdata : std_logic_vector(dw-1 downto 0);
type ram_type is array (0 to (2**ramaddr'length)-1) of std_logic_vector(ramdata'range);
signal ram : ram_type;
signal read_address : std_logic_vector(ramaddr'range);
begin
comb : process (ahbsi, r, rst, ramdata)
variable bs : std_logic_vector(dw/8-1 downto 0);
variable v : reg_type;
variable haddr : std_logic_vector(abits-1 downto 0);
variable hrdata : std_logic_vector(dw-1 downto 0);
variable seldata : std_logic_vector(dw-1 downto 0);
variable raddr : std_logic_vector(3 downto 2);
variable adsel : std_logic;
begin
v := r; v.hready := '1'; bs := (others => '0');
v.pready := r.hready;
if pipe=0 then
adsel := r.hwrite or not r.hready;
else
adsel := r.hwrite or r.pwrite;
v.hready := r.hready or not r.pwrite;
end if;
if adsel = '1' then
haddr := r.addr(abits-1+log2(dw/8) downto log2(dw/8));
else
haddr := ahbsi.haddr(abits-1+log2(dw/8) downto log2(dw/8));
bs := (others => '0');
end if;
raddr := (others => '0');
v.pwrite := '0';
if pipe/=0 and (r.hready='1' or r.pwrite='0') then
v.addr := ahbsi.haddr(abits-1+log2(dw/8) downto 0);
end if;
if ahbsi.hready = '1' then
if pipe=0 then
v.addr := ahbsi.haddr(abits-1+log2(dw/8) downto 0);
end if;
v.hsel := ahbsi.hsel(hindex) and ahbsi.htrans(1);
v.size := ahbsi.hsize(2 downto 0);
v.hwrite := ahbsi.hwrite and v.hsel;
if pipe = 1 and v.hsel = '1' and ahbsi.hwrite = '0' and (r.pready='1' or ahbsi.htrans(0)='0') then
v.hready := '0';
v.pwrite := r.hwrite;
end if;
end if;
if r.hwrite = '1' then
case r.size is
when HSIZE_BYTE =>
bs(bs'left-conv_integer(r.addr(log2(dw/16) downto 0))) := '1';
when HSIZE_HWORD =>
for i in 0 to dw/16-1 loop
if i = conv_integer(r.addr(log2(dw/16) downto 1)) then
bs(bs'left-i*2 downto bs'left-i*2-1) := (others => '1');
end if;
end loop; -- i
when HSIZE_WORD =>
if dw = 32 then bs := (others => '1');
else
for i in 0 to dw/32-1 loop
if i = conv_integer(r.addr(log2(dw/8)-1 downto 2)) then
bs(bs'left-i*4 downto bs'left-i*4-3) := (others => '1');
end if;
end loop; -- i
end if;
when HSIZE_DWORD =>
if dw = 32 then null;
elsif dw = 64 then bs := (others => '1');
else
for i in 0 to dw/64-1 loop
if i = conv_integer(r.addr(3)) then
bs(bs'left-i*8 downto bs'left-i*8-7) := (others => '1');
end if;
end loop; -- i
end if;
when HSIZE_4WORD =>
if dw < 128 then null;
elsif dw = 128 then bs := (others => '1');
else
for i in 0 to dw/64-1 loop
if i = conv_integer(r.addr(3)) then
bs(bs'left-i*8 downto bs'left-i*8-7) := (others => '1');
end if;
end loop; -- i
end if;
when others => --HSIZE_8WORD
if dw < 256 then null;
else bs := (others => '1'); end if;
end case;
v.hready := not (v.hsel and not ahbsi.hwrite);
v.hwrite := v.hwrite and v.hready;
end if;
-- Duplicate read data on word basis, unless CORE_ACDM is enabled
if CORE_ACDM = 0 then
if dw = 32 then
seldata := ramdata;
elsif dw = 64 then
if r.size = HSIZE_DWORD then seldata := ramdata; else
if r.addr(2) = '0' then
seldata(dw/2-1 downto 0) := ramdata(dw-1 downto dw/2);
else
seldata(dw/2-1 downto 0) := ramdata(dw/2-1 downto 0);
end if;
seldata(dw-1 downto dw/2) := seldata(dw/2-1 downto 0);
end if;
elsif dw = 128 then
if r.size = HSIZE_4WORD then
seldata := ramdata;
elsif r.size = HSIZE_DWORD then
if r.addr(3) = '0' then seldata(dw/2-1 downto 0) := ramdata(dw-1 downto dw/2);
else seldata(dw/2-1 downto 0) := ramdata(dw/2-1 downto 0); end if;
seldata(dw-1 downto dw/2) := seldata(dw/2-1 downto 0);
else
raddr := r.addr(3 downto 2);
case raddr is
when "00" => seldata(dw/4-1 downto 0) := ramdata(4*dw/4-1 downto 3*dw/4);
when "01" => seldata(dw/4-1 downto 0) := ramdata(3*dw/4-1 downto 2*dw/4);
when "10" => seldata(dw/4-1 downto 0) := ramdata(2*dw/4-1 downto 1*dw/4);
when others => seldata(dw/4-1 downto 0) := ramdata(dw/4-1 downto 0);
end case;
seldata(dw-1 downto dw/4) := seldata(dw/4-1 downto 0) &
seldata(dw/4-1 downto 0) &
seldata(dw/4-1 downto 0);
end if;
else
seldata := ahbselectdata(ramdata, r.addr(4 downto 2), r.size);
end if;
else
seldata := ramdata;
end if;
if pipe = 0 then
v.prdata := (others => '0');
hrdata := seldata;
else
v.prdata := seldata;
hrdata := r.prdata;
end if;
if (not RESET_ALL) and (rst = '0') then
v.hwrite := RES.hwrite; v.hready := RES.hready;
end if;
write <= bs; for i in 0 to dw/8-1 loop ramsel(i) <= v.hsel or r.hwrite; end loop;
ramaddr <= haddr; c <= v;
ahbso.hrdata <= ahbdrivedata(hrdata);
ahbso.hready <= r.hready;
end process;
ahbso.hresp <= "00";
ahbso.hsplit <= (others => '0');
ahbso.hirq <= (others => '0');
ahbso.hconfig <= hconfig;
ahbso.hindex <= hindex;
-- Select correct write data
hwdata <= ahbreaddata(ahbsi.hwdata, r.addr(4 downto 2),
conv_std_logic_vector(log2(dw/8), 3));
-- aram : syncrambw generic map (tech, abits, dw, scantest) port map (
-- clk, ramaddr, hwdata, ramdata, ramsel, write, ahbsi.testin);
RamProc: process(clk) is
variable L1 : line;
variable FIRST : boolean := true;
variable ADR : std_logic_vector(19 downto 0);
variable BUF : std_logic_vector(31 downto 0);
variable CH : character;
variable ai : integer := 0;
variable len : integer := 0;
file TCF : text open read_mode is fname;
variable rectype : std_logic_vector(3 downto 0);
variable recaddr : std_logic_vector(31 downto 0);
variable reclen : std_logic_vector(7 downto 0);
variable recdata : std_logic_vector(0 to 16*8-1);
begin
if rising_edge(clk) then
if conv_integer(write) > 0 then
for i in 0 to dw/8-1 loop
if (write(i) = '1') then
ram(to_integer(unsigned(ramaddr)))(i*8+7 downto i*8) <= hwdata(i*8+7 downto i*8);
end if;
end loop;
end if;
read_address <= ramaddr;
end if;
if (rst = '0') and (FIRST = true) then
ram <= (others => (others => '0'));
L1:= new string'("");
while not endfile(TCF) loop
readline(TCF,L1);
if (L1'length /= 0) then --'
while (not (L1'length=0)) and (L1(L1'left) = ' ') loop
std.textio.read(L1,CH);
end loop;
if L1'length > 0 then --'
read(L1, ch);
if (ch = 'S') or (ch = 's') then
hread(L1, rectype);
hread(L1, reclen);
len := conv_integer(reclen)-1;
recaddr := (others => '0');
case rectype is
when "0001" =>
hread(L1, recaddr(15 downto 0));
when "0010" =>
hread(L1, recaddr(23 downto 0));
when "0011" =>
hread(L1, recaddr);
when others => next;
end case;
hread(L1, recdata);
recaddr(31 downto abits+2) := (others => '0');
ai := conv_integer(recaddr)/4;
for i in 0 to 3 loop
ram(ai+i) <= recdata((i*32) to (i*32+31));
end loop;
if ai = 0 then
ai := 1;
end if;
end if;
end if;
end if;
end loop;
FIRST := false;
end if;
end process RamProc;
ramdata <= ram(to_integer(unsigned(read_address)));
reg : process (clk)
begin
if rising_edge(clk) then
r <= c;
if RESET_ALL and rst = '0' then
r <= RES;
end if;
end if;
end process;
bootmsg : report_version
generic map ("ahbram" & tost(hindex) &
": AHB SRAM Module rev 1, " & tost(kbytes) & " kbytes");
end;
-- pragma translate_on
| gpl-3.0 | 9cb5d0313c243522c6cb1eca65256a49 | 0.54331 | 3.425108 | false | false | false | false |
EliasLuiz/TCC | Leon3/designs/leon3-terasic-de2-115/leon3mp.vhd | 1 | 29,283 | -----------------------------------------------------------------------------
-- LEON3 Demonstration design
-- Copyright (C) 2004 Jiri Gaisler, Gaisler Research
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib, techmap;
use grlib.amba.all;
use grlib.stdlib.all;
use techmap.gencomp.all;
library gaisler;
use gaisler.memctrl.all;
use gaisler.leon3.all;
use gaisler.uart.all;
use gaisler.misc.all;
use gaisler.spi.all;
use gaisler.can.all;
use gaisler.net.all;
use gaisler.jtag.all;
use gaisler.gr1553b_pkg.all;
-- pragma translate_off
use gaisler.sim.all;
-- pragma translate_on
library esa;
use esa.memoryctrl.all;
use work.config.all;
entity leon3mp is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
clktech : integer := CFG_CLKTECH;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW
);
port (
resetn : in std_logic;
clock_50 : in std_logic;
sma_clkout : out std_ulogic;
errorn : out std_logic;
fl_addr : out std_logic_vector(22 downto 0);
fl_dq : inout std_logic_vector(7 downto 0);
dram_addr : out std_logic_vector(12 downto 0);
dram_ba : out std_logic_vector(1 downto 0);
dram_dq : inout std_logic_vector(31 downto 0);
dram_clk : out std_logic;
dram_cke : out std_logic;
dram_cs_n : out std_logic;
dram_we_n : out std_logic; -- sdram write enable
dram_ras_n : out std_logic; -- sdram ras
dram_cas_n : out std_logic; -- sdram cas
dram_dqm : out std_logic_vector (3 downto 0); -- sdram dqm
uart_txd : out std_logic; -- DSU tx data
uart_rxd : in std_logic; -- DSU rx data
dsubre : in std_logic;
dsuact : out std_logic;
fl_oe_n : out std_logic;
fl_we_n : out std_logic;
fl_rst_n : out std_logic;
fl_wp_n : out std_logic;
fl_ce_n : out std_logic;
-- gpio : inout std_logic_vector(CFG_GRGPIO_WIDTH-1 downto 0); -- I/O port
gpio : inout std_logic_vector(35 downto 0); -- I/O port
enet0_mdio : inout std_logic; -- ethernet PHY interface
enet0_gtx_clk : in std_logic;
enet0_rx_clk : in std_logic;
enet0_tx_clk : in std_logic;
enet0_rx_data: in std_logic_vector(3 downto 0);
enet0_rx_dv : in std_logic;
enet0_rx_er : in std_logic;
enet0_rx_col : in std_logic;
enet0_rx_crs : in std_logic;
enet0_int_n : in std_logic;
enet0_rst_n : out std_logic;
enet0_tx_data: out std_logic_vector(3 downto 0);
enet0_tx_en : out std_logic;
enet0_tx_er : out std_logic;
enet0_mdc : out std_logic;
can_txd : out std_logic_vector(0 to CFG_CAN_NUM-1);
can_rxd : in std_logic_vector(0 to CFG_CAN_NUM-1);
can_stb : out std_logic_vector(0 to CFG_CAN_NUM-1);
clk_1553 : in std_logic;
busainen : out std_logic;
busainp : in std_logic;
busainn : in std_logic;
busaoutin : out std_logic;
busaoutp : out std_logic;
busaoutn : out std_logic;
busbinen : out std_logic;
busbinp : in std_logic;
busbinn : in std_logic;
busboutin : out std_logic;
busboutp : out std_logic;
busboutn : out std_logic;
sw : in std_logic_vector(0 to 2) := "000"
);
end;
architecture rtl of leon3mp is
constant blength : integer := 12;
constant fifodepth : integer := 8;
signal vcc, gnd : std_logic_vector(4 downto 0);
signal memi : memory_in_type;
signal memo : memory_out_type;
signal wpo : wprot_out_type;
signal sdi : sdctrl_in_type;
signal sdo : sdram_out_type;
signal apbi : apb_slv_in_type;
signal apbo : apb_slv_out_vector := (others => apb_none);
signal ahbsi : ahb_slv_in_type;
signal ahbso : ahb_slv_out_vector := (others => ahbs_none);
signal ahbmi : ahb_mst_in_type;
signal ahbmo : ahb_mst_out_vector := (others => ahbm_none);
signal clkm, rstn, rstraw, pciclk, sdclkl : std_logic;
signal cgi, cgi2 : clkgen_in_type;
signal cgo, cgo2 : clkgen_out_type;
signal u1i, u2i, dui : uart_in_type;
signal u1o, u2o, duo : uart_out_type;
signal irqi : irq_in_vector(0 to CFG_NCPU-1);
signal irqo : irq_out_vector(0 to CFG_NCPU-1);
signal dbgi : l3_debug_in_vector(0 to CFG_NCPU-1);
signal dbgo : l3_debug_out_vector(0 to CFG_NCPU-1);
signal dsui : dsu_in_type;
signal dsuo : dsu_out_type;
signal spii, spislvi : spi_in_type;
signal spio, spislvo : spi_out_type;
signal slvsel : std_logic_vector(CFG_SPICTRL_SLVS-1 downto 0);
signal stati : ahbstat_in_type;
signal ethi, ethi1, ethi2 : eth_in_type;
signal etho, etho1, etho2 : eth_out_type;
signal ethclk, egtx_clk_fb : std_logic;
signal egtx_clk, legtx_clk, l2egtx_clk : std_logic;
signal gpti : gptimer_in_type;
signal gpto : gptimer_out_type;
signal gpioi : gpio_in_type;
signal gpioo : gpio_out_type;
signal clklock, elock : std_ulogic;
signal can_lrx, can_ltx : std_logic_vector(0 to 7);
signal dsubren : std_logic;
signal pci_arb_req_n, pci_arb_gnt_n : std_logic_vector(0 to 3);
signal clk1553 : Std_Logic;
type milout_array is array (0 to 0) of gr1553b_txout_type;
type milin_array is array (0 to 0) of gr1553b_rxin_type;
signal rst1553: std_ulogic;
signal milout: milout_array;
signal milin: milin_array;
signal tck, tms, tdi, tdo : std_logic;
signal fpi : grfpu_in_vector_type;
signal fpo : grfpu_out_vector_type;
constant BOARD_FREQ : integer := 50000; -- Board frequency in KHz
constant CPU_FREQ : integer := BOARD_FREQ * CFG_CLKMUL / CFG_CLKDIV; -- cpu frequency in KHz
constant IOAEN : integer := CFG_CAN;
constant CFG_SDEN : integer := CFG_MCTRL_SDEN;
constant CFG_INVCLK : integer := CFG_MCTRL_INVCLK;
constant OEPOL : integer := padoen_polarity(padtech);
attribute syn_keep : boolean;
attribute syn_preserve : boolean;
attribute keep : boolean;
begin
----------------------------------------------------------------------
--- Reset and Clock generation -------------------------------------
----------------------------------------------------------------------
vcc <= (others => '1'); gnd <= (others => '0');
cgi.pllctrl <= "00"; cgi.pllrst <= rstraw;
clkgen0 : clkgen -- clock generator using toplevel generic 'freq'
generic map (tech => CFG_CLKTECH, clk_mul => CFG_CLKMUL,
clk_div => CFG_CLKDIV, sdramen => CFG_MCTRL_SDEN,
noclkfb => CFG_CLK_NOFB, freq => BOARD_FREQ, clk2xen => 1)
port map (clkin => clock_50, pciclkin => gnd(0), clk => clkm, clkn => open,
clk2x => sma_clkout, sdclk => sdclkl, pciclk => open,
cgi => cgi, cgo => cgo);
sdclk_pad : outpad generic map (tech => padtech, slew => 1)
port map (dram_clk, sdclkl);
rst0 : rstgen -- reset generator
port map (resetn, clkm, clklock, rstn, rstraw);
clklock <= cgo.clklock and elock;
----------------------------------------------------------------------
--- AHB CONTROLLER --------------------------------------------------
----------------------------------------------------------------------
ahb0 : ahbctrl -- AHB arbiter/multiplexer
generic map (defmast => CFG_DEFMST, split => CFG_SPLIT,
rrobin => CFG_RROBIN, ioaddr => CFG_AHBIO, ioen => IOAEN,
nahbm => CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_SPI2AHB+CFG_GRETH+
CFG_GR1553B_ENABLE,
nahbs => 8)
port map (rstn, clkm, ahbmi, ahbmo, ahbsi, ahbso);
----------------------------------------------------------------------
--- LEON3 processor and DSU -----------------------------------------
----------------------------------------------------------------------
cpu : for i in 0 to CFG_NCPU-1 generate
leon3 : leon3x -- LEON3 processor
generic map (
hindex => i,
fabtech => fabtech,
memtech => memtech,
nwindows => CFG_NWIN,
dsu => CFG_DSU,
fpu => CFG_FPU + 32*CFG_GRFPUSH,
v8 => CFG_V8,
cp => 0,
mac => CFG_MAC,
pclow => pclow,
notag => CFG_NOTAG,
nwp => CFG_NWP,
icen => CFG_ICEN,
irepl => CFG_IREPL,
isets => CFG_ISETS,
ilinesize => CFG_ILINE,
isetsize => CFG_ISETSZ,
isetlock => CFG_ILOCK,
dcen => CFG_DCEN,
drepl => CFG_DREPL,
dsets => CFG_DSETS,
dlinesize => CFG_DLINE,
dsetsize => CFG_DSETSZ,
dsetlock => CFG_DLOCK,
dsnoop => CFG_DSNOOP,
ilram => CFG_ILRAMEN,
ilramsize => CFG_ILRAMSZ,
ilramstart => CFG_ILRAMADDR,
dlram => CFG_DLRAMEN,
dlramsize => CFG_DLRAMSZ,
dlramstart => CFG_DLRAMADDR,
mmuen => CFG_MMUEN,
itlbnum => CFG_ITLBNUM,
dtlbnum => CFG_DTLBNUM,
tlb_type => CFG_TLB_TYPE,
tlb_rep => CFG_TLB_REP,
lddel => CFG_LDDEL,
disas => disas,
tbuf => CFG_ITBSZ,
pwd => CFG_PWD,
svt => CFG_SVT,
rstaddr => CFG_RSTADDR,
smp => CFG_NCPU-1,
iuft => CFG_IUFT_EN,
fpft => CFG_FPUFT_EN,
cmft => CFG_CACHE_FT_EN,
iuinj => CFG_RF_ERRINJ,
ceinj => CFG_CACHE_ERRINJ,
cached => CFG_DFIXED,
clk2x => 0,
netlist => CFG_LEON3_NETLIST,
scantest => CFG_SCAN,
mmupgsz => CFG_MMU_PAGE,
bp => CFG_BP,
npasi => CFG_NP_ASI)
port map (
clk => clkm, gclk2 => clkm, gfclk2 => clkm, clk2 => clkm, rstn => rstn,
ahbi => ahbmi, ahbo => ahbmo(i), ahbsi => ahbsi, ahbso => ahbso,
irqi => irqi(i), irqo => irqo(i), dbgi => dbgi(i), dbgo => dbgo(i),
fpui => fpi(i), fpuo => fpo(i), clken => vcc(0));
end generate;
sh : if CFG_GRFPUSH /= 0 generate
grfpush0 : grfpushwx generic map ((CFG_FPU-1), CFG_NCPU, fabtech)
port map (clkm, rstn, fpi, fpo);
end generate;
nosh : if CFG_GRFPUSH = 0 generate
fpo <= (others => grfpu_out_none);
end generate;
errorn_pad : odpad generic map (tech => padtech) port map (errorn, dbgo(0).error);
dsugen : if CFG_DSU = 1 generate
dsu0 : dsu3 -- LEON3 Debug Support Unit
generic map (hindex => 2, haddr => 16#900#, hmask => 16#F00#,
ncpu => CFG_NCPU, tbits => 30, tech => memtech, irq => 0, kbytes => CFG_ATBSZ)
port map (rstn, clkm, ahbmi, ahbsi, ahbso(2), dbgo, dbgi, dsui, dsuo);
dsui.enable <= '1';
dsubre_pad : inpad generic map (tech => padtech) port map (dsubre, dsubren);
dsui.break <= not dsubren;
dsuact_pad : outpad generic map (tech => padtech) port map (dsuact, dsuo.active);
end generate;
nodsu : if CFG_DSU = 0 generate
ahbso(2) <= ahbs_none; dsuo.tstop <= '0'; dsuo.active <= '0';
end generate;
dcomgen : if CFG_AHB_UART = 1 generate
dcom0: ahbuart -- Debug UART
generic map (hindex => CFG_NCPU, pindex => 7, paddr => 7)
port map (rstn, clkm, dui, duo, apbi, apbo(7), ahbmi, ahbmo(CFG_NCPU));
-- dsurx_pad : inpad generic map (tech => padtech) port map (dsurx, dui.rxd);
dui.rxd <= uart_rxd when sw(0) = '0' else '1';
-- dsutx_pad : outpad generic map (tech => padtech) port map (dsutx, duo.txd);
end generate;
-- nouah : if CFG_AHB_UART = 0 generate apbo(7) <= apb_none; end generate;
ahbjtaggen0 :if CFG_AHB_JTAG = 1 generate
ahbjtag0 : ahbjtag generic map(tech => fabtech, hindex => CFG_NCPU+CFG_AHB_UART)
port map(rstn, clkm, tck, tms, tdi, tdo, ahbmi, ahbmo(CFG_NCPU+CFG_AHB_UART),
open, open, open, open, open, open, open, gnd(0));
end generate;
----------------------------------------------------------------------
--- Memory controllers ----------------------------------------------
----------------------------------------------------------------------
memi.edac <= '0'; memi.bwidth <= "00";
mctrl0 : if CFG_MCTRL_LEON2 = 1 generate -- LEON2 memory controller
sr1 : mctrl generic map (hindex => 0, pindex => 0, paddr => 0,
srbanks => 4, sden => CFG_MCTRL_SDEN, ram8 => CFG_MCTRL_RAM8BIT,
ram16 => CFG_MCTRL_RAM16BIT, invclk => CFG_MCTRL_INVCLK,
sepbus => CFG_MCTRL_SEPBUS, oepol => OEPOL, iomask => 0,
sdbits => 32 + 32*CFG_MCTRL_SD64, pageburst => CFG_MCTRL_PAGE)
port map (rstn, clkm, memi, memo, ahbsi, ahbso(0), apbi, apbo(0), wpo, sdo);
addr_pad : outpadv generic map (width => 23, tech => padtech)
port map (fl_addr, memo.address(22 downto 0));
roms_pad : outpad generic map (tech => padtech)
port map (fl_ce_n, memo.romsn(0));
oen_pad : outpad generic map (tech => padtech)
port map (fl_oe_n, memo.oen);
wri_pad : outpad generic map (tech => padtech)
port map (fl_we_n, memo.writen);
fl_rst_pad : outpad generic map (tech => padtech)
port map (fl_rst_n, rstn);
fl_wp_pad : outpad generic map (tech => padtech)
port map (fl_wp_n, vcc(0));
data_pad : iopadvv generic map (tech => padtech, width => 8, oepol => OEPOL)
port map (fl_dq, memo.data(31 downto 24), memo.vbdrive(31 downto 24), memi.data(31 downto 24));
memi.brdyn <= '1'; memi.bexcn <= '1';
memi.writen <= '1'; memi.wrn <= "1111";
sdpads : if CFG_MCTRL_SDEN = 1 generate -- SDRAM controller
sd2 : if CFG_MCTRL_SEPBUS = 1 generate
sa_pad : outpadv generic map (width => 13)
port map (dram_addr, memo.sa(12 downto 0));
ba_pad : outpadv generic map (width => 2)
port map (dram_ba, memo.sa(14 downto 13));
sd_pad : iopadvv generic map (tech => padtech, width => 32, oepol => OEPOL)
port map (dram_dq(31 downto 0), memo.sddata(31 downto 0),
memo.svbdrive(31 downto 0), memi.sd(31 downto 0));
end generate;
sdwen_pad : outpad generic map (tech => padtech)
port map (dram_we_n, sdo.sdwen);
sdras_pad : outpad generic map (tech => padtech)
port map (dram_ras_n, sdo.rasn);
sdcas_pad : outpad generic map (tech => padtech)
port map (dram_cas_n, sdo.casn);
sddqm_pad : outpadv generic map (width => 4, tech => padtech)
port map (dram_dqm, sdo.dqm(3 downto 0));
sdcke_pad : outpad generic map (tech => padtech)
port map (dram_cke, sdo.sdcke(0));
sdcsn_pad : outpad generic map (tech => padtech)
port map (dram_cs_n, sdo.sdcsn(0));
end generate;
end generate;
nosd0 : if (CFG_SDEN = 0) generate -- no SDRAM controller
sdcke_pad : outpad generic map (tech => padtech)
port map (dram_cke, vcc(0));
sdcsn_pad : outpad generic map (tech => padtech)
port map (dram_cs_n, vcc(0));
end generate;
mg0 : if CFG_MCTRL_LEON2 = 0 generate -- No PROM/SRAM controller
apbo(0) <= apb_none; ahbso(0) <= ahbs_none;
roms_pad : outpad generic map (tech => padtech)
port map (fl_ce_n, vcc(0));
end generate;
----------------------------------------------------------------------
--- APB Bridge and various periherals -------------------------------
----------------------------------------------------------------------
apb0 : apbctrl -- AHB/APB bridge
generic map (hindex => 1, haddr => CFG_APBADDR)
port map (rstn, clkm, ahbsi, ahbso(1), apbi, apbo );
ua1 : if CFG_UART1_ENABLE /= 0 generate
uart1 : apbuart -- UART 1
generic map (pindex => 1, paddr => 1, pirq => 2, console => dbguart,
fifosize => CFG_UART1_FIFO)
port map (rstn, clkm, apbi, apbo(1), u1i, u1o);
u1i.rxd <= '1' when sw(0) = '0' else uart_rxd; u1i.ctsn <= '0'; u1i.extclk <= '0';
end generate;
uart_txd <= u1o.txd when sw(0) = '1' else duo.txd;
noua0 : if CFG_UART1_ENABLE = 0 generate apbo(1) <= apb_none; end generate;
irqctrl : if CFG_IRQ3_ENABLE /= 0 generate
irqctrl0 : irqmp -- interrupt controller
generic map (pindex => 2, paddr => 2, ncpu => CFG_NCPU)
port map (rstn, clkm, apbi, apbo(2), irqo, irqi);
end generate;
irq3 : if CFG_IRQ3_ENABLE = 0 generate
x : for i in 0 to CFG_NCPU-1 generate
irqi(i).irl <= "0000";
end generate;
-- apbo(2) <= apb_none;
end generate;
gpt : if CFG_GPT_ENABLE /= 0 generate
timer0 : gptimer -- timer unit
generic map (pindex => 3, paddr => 3, pirq => CFG_GPT_IRQ,
sepirq => CFG_GPT_SEPIRQ, sbits => CFG_GPT_SW, ntimers => CFG_GPT_NTIM,
nbits => CFG_GPT_TW)
port map (rstn, clkm, apbi, apbo(3), gpti, open);
gpti <= gpti_dhalt_drive(dsuo.tstop);
end generate;
-- notim : if CFG_GPT_ENABLE = 0 generate apbo(3) <= apb_none; end generate;
gpio0 : if CFG_GRGPIO_ENABLE /= 0 generate -- GR GPIO unit
grgpio0: grgpio
generic map( pindex => 9, paddr => 9, imask => CFG_GRGPIO_IMASK,
nbits => CFG_GRGPIO_WIDTH)
port map( rstn, clkm, apbi, apbo(9), gpioi, gpioo);
pio_pads : for i in 0 to CFG_GRGPIO_WIDTH-1 generate
pio_pad : iopad generic map (tech => padtech)
port map (gpio(i), gpioo.dout(i), gpioo.oen(i), gpioi.din(i));
end generate;
end generate;
spic: if CFG_SPICTRL_ENABLE = 1 generate -- SPI controller
spi1 : spictrl
generic map (pindex => 10, paddr => 10, pmask => 16#fff#, pirq => 10,
fdepth => CFG_SPICTRL_FIFO, slvselen => CFG_SPICTRL_SLVREG,
slvselsz => CFG_SPICTRL_SLVS, odmode => 0, netlist => 0,
syncram => CFG_SPICTRL_SYNCRAM, ft => CFG_SPICTRL_FT)
port map (rstn, clkm, apbi, apbo(10), spii, spio, slvsel);
spii.spisel <= '1'; -- Master only
miso_pad : iopad generic map (tech => padtech)
port map (gpio(35), spio.miso, spio.misooen, spii.miso);
mosi_pad : iopad generic map (tech => padtech)
port map (gpio(34), spio.mosi, spio.mosioen, spii.mosi);
sck_pad : iopad generic map (tech => padtech)
port map (gpio(33), spio.sck, spio.sckoen, spii.sck);
slvsel_pad : iopad generic map (tech => padtech)
port map (gpio(32), slvsel(0), gnd(0), open);
end generate spic;
spibridge : if CFG_SPI2AHB /= 0 generate -- SPI to AHB bridge
withapb : if CFG_SPI2AHB_APB /= 0 generate
spi2ahb0 : spi2ahb_apb
generic map(hindex => CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG,
ahbaddrh => CFG_SPI2AHB_ADDRH, ahbaddrl => CFG_SPI2AHB_ADDRL,
ahbmaskh => CFG_SPI2AHB_MASKH, ahbmaskl => CFG_SPI2AHB_MASKL,
resen => CFG_SPI2AHB_RESEN, pindex => 11, paddr => 11, pmask => 16#fff#,
pirq => 11, filter => CFG_SPI2AHB_FILTER, cpol => CFG_SPI2AHB_CPOL,
cpha => CFG_SPI2AHB_CPHA)
port map (rstn, clkm, ahbmi, ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG),
apbi, apbo(11), spislvi, spislvo);
end generate;
woapb : if CFG_SPI2AHB_APB = 0 generate
spi2ahb0 : spi2ahb
generic map(hindex => CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG,
ahbaddrh => CFG_SPI2AHB_ADDRH, ahbaddrl => CFG_SPI2AHB_ADDRL,
ahbmaskh => CFG_SPI2AHB_MASKH, ahbmaskl => CFG_SPI2AHB_MASKL,
filter => CFG_SPI2AHB_FILTER,
cpol => CFG_SPI2AHB_CPOL, cpha => CFG_SPI2AHB_CPHA)
port map (rstn, clkm, ahbmi, ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG),
spislvi, spislvo);
end generate;
spislv_miso_pad : iopad generic map (tech => padtech)
port map (gpio(31), spislvo.miso, spislvo.misooen, spislvi.miso);
spislvl_mosi_pad : iopad generic map (tech => padtech)
port map (gpio(30), spislvo.mosi, spislvo.mosioen, spislvi.mosi);
spislv_sck_pad : iopad generic map (tech => padtech)
port map (gpio(29), spislvo.sck, spislvo.sckoen, spislvi.sck);
spislv_slvsel_pad : iopad generic map (tech => padtech)
port map (gpio(28), gnd(0), vcc(0), spislvi.spisel);
end generate;
nospibridge : if CFG_SPI2AHB = 0 or CFG_SPI2AHB_APB = 0 generate
apbo(11) <= apb_none;
end generate;
ahbs : if CFG_AHBSTAT = 1 generate -- AHB status register
stati.cerror(0) <= memo.ce;
ahbstat0 : ahbstat generic map (pindex => 15, paddr => 15, pirq => 1,
nftslv => CFG_AHBSTATN)
port map (rstn, clkm, ahbmi, ahbsi, stati, apbi, apbo(15));
end generate;
nop2 : if CFG_AHBSTAT = 0 generate apbo(15) <= apb_none; end generate;
-----------------------------------------------------------------------
--- ETHERNET ---------------------------------------------------------
-----------------------------------------------------------------------
eth1 : if CFG_GRETH = 1 generate -- Gaisler ethernet MAC
e1 : grethm generic map(
hindex => CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_SPI2AHB,
pindex => 14, paddr => 14, pirq => 12, memtech => memtech,
mdcscaler => CPU_FREQ/1000, enable_mdio => 1, fifosize => CFG_ETH_FIFO,
nsync => 1, edcl => CFG_DSU_ETH, edclbufsz => CFG_ETH_BUF,
macaddrh => CFG_ETH_ENM, macaddrl => CFG_ETH_ENL, phyrstadr => 16,
ipaddrh => CFG_ETH_IPM, ipaddrl => CFG_ETH_IPL, giga => CFG_GRETH1G,
enable_mdint => 1)
port map(
rst => rstn, clk => clkm, ahbmi => ahbmi,
ahbmo => ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_SPI2AHB),
apbi => apbi, apbo => apbo(14), ethi => ethi, etho => etho);
greth1g: if CFG_GRETH1G = 1 generate
eth_macclk_pad : clkpad
generic map (tech => padtech, arch => 3, hf => 1)
port map (enet0_gtx_clk, egtx_clk, cgo.clklock, elock);
end generate greth1g;
emdio_pad : iopad generic map (tech => padtech)
port map (enet0_mdio, etho.mdio_o, etho.mdio_oe, ethi.mdio_i);
etxc_pad : clkpad generic map (tech => padtech, arch => 2)
port map (enet0_tx_clk, ethi.tx_clk);
erxc_pad : clkpad generic map (tech => padtech, arch => 2)
port map (enet0_rx_clk, ethi.rx_clk);
erxd_pad : inpadv generic map (tech => padtech, width => 4)
port map (enet0_rx_data, ethi.rxd(3 downto 0));
erxdv_pad : inpad generic map (tech => padtech)
port map (enet0_rx_dv, ethi.rx_dv);
erxer_pad : inpad generic map (tech => padtech)
port map (enet0_rx_er, ethi.rx_er);
erxco_pad : inpad generic map (tech => padtech)
port map (enet0_rx_col, ethi.rx_col);
erxcr_pad : inpad generic map (tech => padtech)
port map (enet0_rx_crs, ethi.rx_crs);
emdintn_pad : inpad generic map (tech => padtech)
port map (enet0_int_n, ethi.mdint);
etxd_pad : outpadv generic map (tech => padtech, width => 4)
port map (enet0_tx_data, etho.txd(3 downto 0));
etxen_pad : outpad generic map (tech => padtech)
port map (enet0_tx_en, etho.tx_en);
etxer_pad : outpad generic map (tech => padtech)
port map (enet0_tx_er, etho.tx_er);
emdc_pad : outpad generic map (tech => padtech)
port map (enet0_mdc, etho.mdc);
eth0_rst_pad : odpad generic map (tech => padtech)
port map (enet0_rst_n, rstn);
-- emdis_pad : outpad generic map (tech => padtech)
-- port map (emddis, vcc(0));
-- eepwrdwn_pad : outpad generic map (tech => padtech)
-- port map (epwrdwn, gnd(0));
-- esleep_pad : outpad generic map (tech => padtech)
-- port map (esleep, gnd(0));
-- epause_pad : outpad generic map (tech => padtech)
-- port map (epause, gnd(0));
-- ereset_pad : outpad generic map (tech => padtech)
-- port map (ereset, gnd(0));
ethi.gtx_clk <= egtx_clk;
end generate;
noeth: if CFG_GRETH = 0 or CFG_GRETH1G = 0 generate
elock <= '1';
end generate noeth;
-----------------------------------------------------------------------
--- CAN --------------------------------------------------------------
-----------------------------------------------------------------------
can0 : if CFG_CAN = 1 generate
can0 : can_mc generic map (slvndx => 6, ioaddr => CFG_CANIO,
iomask => 16#FF0#, irq => CFG_CANIRQ, memtech => memtech,
ncores => CFG_CAN_NUM, sepirq => CFG_CANSEPIRQ)
port map (rstn, clkm, ahbsi, ahbso(6), can_lrx, can_ltx );
can_pads : for i in 0 to CFG_CAN_NUM-1 generate
can_tx_pad : outpad generic map (tech => padtech)
port map (can_txd(i), can_ltx(i));
can_rx_pad : inpad generic map (tech => padtech)
port map (can_rxd(i), can_lrx(i));
end generate;
end generate;
-- can_stb <= '0'; -- no standby
ncan : if CFG_CAN = 0 generate ahbso(6) <= ahbs_none; end generate;
-----------------------------------------------------------------------
--- MIL-STD-1553B
-----------------------------------------------------------------------
mil: if CFG_GR1553B_ENABLE /= 0 generate
--milclk_pad : clkpad generic map (tech => padtech) port map (clk_1553, clk1553);
milclk_pad : techbuf generic map(tech => padtech, buftype => 2)
port map(i => clk_1553, o => clk1553);
milrst: rstgen
port map (resetn, clk1553, vcc(0), rst1553, open);
gr1553b0: gr1553b_nlw
generic map (
tech => 0, -- inferred = rtl
hindex => CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_SPI2AHB+CFG_GRETH,
pindex => 13, paddr => 13, pirq => 13,
bc_enable => CFG_GR1553B_BCEN, rt_enable => CFG_GR1553B_RTEN,
bm_enable => CFG_GR1553B_BMEN,
bc_rtbusmask => 1)
port map (
clk => clkm, rst => rstn,
ahbmi => ahbmi, ahbmo => ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_SPI2AHB+CFG_GRETH),
apbsi => apbi, apbso => apbo(13),
auxin => gr1553b_auxin_zero, auxout => open,
codec_clk => clk1553, codec_rst => rst1553,
txout => milout(0), txout_fb => milout(0), rxin => milin(0)
);
end generate;
nmil: if CFG_GR1553B_ENABLE = 0 generate
clk1553 <= '0'; rst1553 <= '0';
milout(0) <= (others => '0');
end generate;
milpads: gr1553b_pads
generic map (padtech => padtech, outen_pol => 1)
port map (milout(0), milin(0),
busainen, busainp, busainn, busaoutin, busaoutp, busaoutn,
busbinen, busbinp, busbinn, busboutin, busboutp, busboutn);
-----------------------------------------------------------------------
--- AHB RAM ----------------------------------------------------------
-----------------------------------------------------------------------
-- ocram : if CFG_AHBRAMEN = 1 generate
-- ahbram0 : ftahbram generic map (hindex => 7, haddr => CFG_AHBRADDR,
-- tech => CFG_MEMTECH, kbytes => CFG_AHBRSZ, pindex => 6,
-- paddr => 6, edacen => CFG_AHBRAEDAC, autoscrub => CFG_AHBRASCRU,
-- errcnten => CFG_AHBRAECNT, cntbits => CFG_AHBRAEBIT)
-- port map ( rstn, clkm, ahbsi, ahbso(7), apbi, apbo(6), open);
-- end generate;
--
-- nram : if CFG_AHBRAMEN = 0 generate ahbso(7) <= ahbs_none; end generate;
-----------------------------------------------------------------------
--- Drive unused bus elements ---------------------------------------
-----------------------------------------------------------------------
-- nam1 : for i in (CFG_NCPU+CFG_AHB_UART+log2x(CFG_PCI)+CFG_AHB_JTAG) to NAHBMST-1 generate
-- ahbmo(i) <= ahbm_none;
-- end generate;
-- nam2 : if CFG_PCI > 1 generate
-- ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+log2x(CFG_PCI)-1) <= ahbm_none;
-- end generate;
-- nap0 : for i in 11 to NAPBSLV-1 generate apbo(i) <= apb_none; end generate;
-- apbo(6) <= apb_none;
-----------------------------------------------------------------------
--- Test report module ----------------------------------------------
-----------------------------------------------------------------------
-- pragma translate_off
test0 : ahbrep generic map (hindex => 7, haddr => 16#200#)
port map (rstn, clkm, ahbsi, ahbso(7));
-- pragma translate_on
-----------------------------------------------------------------------
--- Boot message ----------------------------------------------------
-----------------------------------------------------------------------
-- pragma translate_off
x : report_design
generic map (
msg1 => "LEON3 TerAsic DE2_115 Demonstration design",
fabtech => tech_table(fabtech), memtech => tech_table(memtech),
mdel => 1
);
-- pragma translate_on
end;
| gpl-3.0 | 21341c3ace932883f73d37fccb80ed7e | 0.554178 | 3.516633 | false | false | false | false |
EliasLuiz/TCC | Leon3/lib/gaisler/ambatest/ahbtbm.vhd | 1 | 14,288 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: ahbtbm
-- File: ahbtbm.vhd
-- Author: Nils-Johan Wessman - Gaisler Research
-- Description: AHB Testbench master
------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
use work.ahbtbp.all;
entity ahbtbm is
generic (
hindex : integer := 0;
hirq : integer := 0;
venid : integer := VENDOR_GAISLER;
devid : integer := 0;
version : integer := 0;
chprot : integer := 3;
incaddr : integer := 0);
port (
rst : in std_ulogic;
clk : in std_ulogic;
ctrli : in ahbtbm_ctrl_in_type;
ctrlo : out ahbtbm_ctrl_out_type;
ahbmi : in ahb_mst_in_type;
ahbmo : out ahb_mst_out_type
);
end;
architecture rtl of ahbtbm is
constant hconfig : ahb_config_type := (
0 => ahb_device_reg ( venid, devid, 0, version, 0),
others => zero32);
type reg_type is record
-- new /*
grant : std_logic;
grant2 : std_logic;
retry : std_logic_vector(1 downto 0);
read : std_logic; -- indicate
dbgl : integer;
use128 : integer;
hsize : std_logic_vector(2 downto 0);
ac : ahbtbm_access_array_type;
retryac : ahbtbm_access_type;
curac : ahbtbm_access_type;
haddr : std_logic_vector(31 downto 0); -- addr current access
hdata : std_logic_vector(31 downto 0); -- data currnet access
hdata128 : std_logic_vector(127 downto 0); -- data currnet access
hwrite : std_logic; -- write current access
hrdata : std_logic_vector(31 downto 0);
hrdata128 : std_logic_vector(127 downto 0);
status : ahbtbm_status_type;
dvalid : std_logic;
oldhtrans : std_logic_vector(1 downto 0);
-- new */
start : std_ulogic;
active : std_ulogic;
end record;
signal dmai : ahb_dma_in_type;
signal dmao : ahb_dma_out_type;
signal r, rin : reg_type;
begin
ctrlo.rst <= rst;
ctrlo.clk <= clk;
comb : process(ahbmi, ctrli, rst, r)
-- new /*
variable v : reg_type;
variable update : std_logic;
variable hbusreq : std_ulogic; -- bus request
variable kblimit : std_logic; -- 1 kB limit indicator
-- new */
variable ready : std_ulogic;
variable retry : std_ulogic;
variable mexc : std_ulogic;
variable inc : std_logic_vector(3 downto 0); -- address increment
variable haddr : std_logic_vector(31 downto 0); -- AHB address
variable hwdata : std_logic_vector(31 downto 0); -- AHB write data
variable htrans : std_logic_vector(1 downto 0); -- transfer type
variable hwrite : std_ulogic; -- read/write
variable hburst : std_logic_vector(2 downto 0); -- burst type
variable newaddr : std_logic_vector(10 downto 0); -- next sequential address
variable hprot : std_logic_vector(3 downto 0); -- transfer type
variable xhirq : std_logic_vector(NAHBIRQ-1 downto 0);
begin
-- new /*
v := r; update := '0'; hbusreq := '0';--v.retry := '0';
v.dvalid := '0'; xhirq := (others => '0');
hprot := "1110";
--v.hrdata := ahbmi.hrdata;
--v.hrdata128 := ahbmi.hrdata128;
v.hrdata := ahbmi.hrdata(31 downto 0);
v.hrdata128 := ahbread4word(ahbmi.hrdata);
-- pragma translate_off
if ahbmi.hready = '1' and ahbmi.hresp = HRESP_ERROR then
v.hrdata := (others => 'X');
v.hrdata128 := (others => 'X');
end if;
-- pragma translate_on
v.status.err := '0';
--v.oldhtrans := r.ac(1).htrans;
kblimit := '0';
-- Sample grant when hready
if ahbmi.hready = '1' then
v.grant := ahbmi.hgrant(hindex);
v.grant2 := r.grant;
v.oldhtrans := r.ac(1).htrans;
end if;
-- 1k limit
if (r.ac(0).htrans = HTRANS_SEQ
and (r.ac(0).haddr(10) xor r.ac(1).haddr(10)) = '1')
or (r.retryac.htrans = HTRANS_SEQ
and (r.retryac.haddr(10) xor r.ac(1).haddr(10)) = '1' and r.retry = "10") then
kblimit := '1';
end if;
-- Read in new access
--if ((ahbmi.hready = '1' and ahbmi.hresp = HRESP_OKAY and r.grant = '1')
-- or r.ac(1).htrans = HTRANS_IDLE) and r.retry = '0' then
--if ahbmi.hready = '1' and ((ahbmi.hresp = HRESP_OKAY and r.grant = '1')
-- or r.ac(1).htrans = HTRANS_IDLE) and r.retry = "00" then
if ahbmi.hready = '0' and (ahbmi.hresp = HRESP_RETRY or ahbmi.hresp = HRESP_SPLIT) and r.grant2 = '1' then
if r.retry = "00" then
v.retryac := r.ac(1);
v.ac(1) := r.curac;
v.ac(1).htrans := HTRANS_IDLE;
v.ac(1).hburst := "000";
v.retry := "01";
elsif r.retry = "10" then
v.ac(1) := r.retryac;
if kblimit = '1' then v.ac(1).htrans := HTRANS_NONSEQ; end if;
end if;
elsif ahbmi.hready = '1' and ( r.grant = '1'
or r.ac(1).htrans = HTRANS_IDLE) and r.retry = "00" then
-- elsif ahbmi.hready = '1' and (( r.grant = '1' and
-- (ahbmi.hresp = HRESP_OKAY or ahbmi.hresp = HRESP_ERROR))
-- or r.ac(1).htrans = HTRANS_IDLE) and r.retry = "00" then
v.ac(1) := r.ac(0); v.ac(0) := ctrli.ac;
v.curac := r.ac(1);
v.hdata := r.ac(1).hdata; v.haddr := r.ac(1).haddr;
v.hwrite := r.ac(1).hwrite; v.dbgl := r.ac(1).ctrl.dbgl;
v.use128 := r.ac(1).ctrl.use128;
if v.use128 = 0 then
v.hdata128 := r.ac(1).hdata & r.ac(1).hdata & r.ac(1).hdata & r.ac(1).hdata;
else
v.hdata128 := r.ac(1).hdata128;
end if;
v.hsize := r.ac(1).hsize;
v.read := (not r.ac(1).hwrite) and r.ac(1).htrans(1);
update := '1';
if kblimit = '1' then v.ac(1).htrans := HTRANS_NONSEQ; end if;
elsif ahbmi.hready = '0' and (ahbmi.hresp = HRESP_RETRY or ahbmi.hresp = HRESP_SPLIT) and r.grant2 = '1' then
if r.retry = "00" then
v.retryac := r.ac(1);
v.ac(1) := r.curac;
v.ac(1).htrans := HTRANS_IDLE;
v.ac(1).hburst := "000";
v.retry := "01";
elsif r.retry = "10" then
v.ac(1) := r.retryac;
if kblimit = '1' then v.ac(1).htrans := HTRANS_NONSEQ; end if;
end if;
elsif r.retry = "01" then
v.ac(1).htrans := HTRANS_NONSEQ;
v.ac(1).hburst := r.curac.hburst;
v.read := '0';
v.retry := "10";
elsif ahbmi.hready = '1' and r.grant = '1' and r.retry = "10" then
v.read := (not r.ac(1).hwrite) and r.ac(1).htrans(1);
--if ahbmi.hresp = HRESP_OKAY then
--if ahbmi.hresp = HRESP_OKAY or ahbmi.hresp = HRESP_ERROR then
v.ac(1) := r.retryac;
if kblimit = '1' then v.ac(1).htrans := HTRANS_NONSEQ; end if;
v.retry := "00";
--end if;
end if;
-- NONSEQ in retry
--if r.retry = '1' then v.ac(1).htrans := HTRANS_NONSEQ; end if;
-- NONSEQ if burst is interrupted
if r.grant = '0' and r.ac(1).htrans = HTRANS_SEQ then
v.ac(1).htrans := HTRANS_NONSEQ;
end if;
--if r.ac(1).htrans /= HTRANS_IDLE or r.ac(0).htrans /= HTRANS_IDLE then
-- hbusreq := '1';
--end if;
if r.ac(1).htrans = HTRANS_NONSEQ
or (r.ac(1).htrans = HTRANS_SEQ
and r.ac(0).htrans /= HTRANS_NONSEQ and kblimit = '0') then
hbusreq := '1';
end if;
--if r.grant = '0' then -- fix dvalid if grant deasserted *** ???
if r.grant = '0' and ahbmi.hready = '1' then
v.read := '0';
end if;
-- Check read data
if r.read = '1' and ahbmi.hresp = HRESP_OKAY and ahbmi.hready = '1' then
v.dvalid := '1';
if r.use128 = 0 then
--if r.hdata /= ahbmi.hrdata then
if r.hdata /= ahbmi.hrdata(31 downto 0) then
v.status.err := '1';
end if;
else
if r.hsize = "100" then
--if r.hdata128 /= ahbmi.hrdata128 then
if r.hdata128 /= ahbread4word(ahbmi.hrdata) then
v.status.err := '1';
end if;
else
--if r.hdata128(63 downto 0) /= ahbmi.hrdata128(63 downto 0) then
--if r.hdata128(63 downto 0) /= ahbmi.hrdata(63 downto 0) then
if r.hdata128(63 downto 0) /= ahbreaddword(ahbmi.hrdata) then
v.status.err := '1';
end if;
end if;
end if;
elsif r.read = '1' and ahbmi.hresp = HRESP_ERROR and ahbmi.hready = '1' then
v.status.err := '1';
end if;
-- new */
if rst = '0' then
v.ac(0).htrans := (others => '0');
v.ac(1).htrans := (others => '0');
v.retry := (others => '0');
v.read := '0';
v.ac(1).haddr := (others => '0');
v.ac(1).htrans := (others => '0');
v.ac(1).hwrite := '0';
v.ac(1).hsize := (others => '0');
v.ac(1).hburst := (others =>'0');
end if;
rin <= v;
ctrlo.update <= update;
ctrlo.status <= r.status;
ctrlo.hrdata <= r.hrdata;
ctrlo.hrdata128 <= r.hrdata128;
ctrlo.dvalid <= r.dvalid;
ahbmo.haddr <= r.ac(1).haddr;
ahbmo.htrans <= r.ac(1).htrans;
ahbmo.hbusreq <= hbusreq;
--ahbmo.hwdata <= r.hdata;
--ahbmo.hwdata128 <= r.hdata128;
ahbmo.hwdata <= ahbdrivedata(r.hdata128);
ahbmo.hconfig <= hconfig;
ahbmo.hlock <= '0';
ahbmo.hwrite <= r.ac(1).hwrite;
ahbmo.hsize <= r.ac(1).hsize;
ahbmo.hburst <= r.ac(1).hburst;
ahbmo.hprot <= r.ac(1).hprot;
ahbmo.hirq <= xhirq;
ahbmo.hindex <= hindex;
end process;
regs : process(clk)
begin
if rising_edge(clk) then
r <= rin;
-- pragma translate_off
if r.read = '1' and ahbmi.hready = '1' then --and r.oldhtrans /= HTRANS_IDLE then
if ahbmi.hresp = HRESP_OKAY then
if rin.status.err = '0' then
if r.dbgl >= 2 then
if r.use128 = 0 then print(ptime & "Read[" & tost(r.haddr) & "]: " & tost(ahbmi.hrdata(31 downto 0)));
else
if r.hsize = "100" then print(ptime & "Read[" & tost(r.haddr) & "]: " & tost(ahbmi.hrdata));
else print(ptime & "Read[" & tost(r.haddr) & "]: " & tost(ahbreaddword(ahbmi.hrdata))); end if;
end if;
end if;
else
if r.dbgl >= 1 then
if r.use128 = 0 then print(ptime & "Read[" & tost(r.haddr) & "]: " & tost(ahbmi.hrdata(31 downto 0))
& " != " & tost(r.hdata));
else
if r.hsize = "100" then print(ptime & "Read[" & tost(r.haddr) & "]: " & tost(ahbmi.hrdata)
& " != " & tost(r.hdata128));
else print(ptime & "Read[" & tost(r.haddr) & "]: " & tost(ahbreaddword(ahbmi.hrdata))
& " != " & tost(r.hdata128(63 downto 0)));
end if;
end if;
end if;
end if;
elsif ahbmi.hresp = HRESP_RETRY then
if r.dbgl >= 3 then
print(ptime & "Read[" & tost(r.haddr) & "]: [RETRY]");
end if;
elsif ahbmi.hresp = HRESP_SPLIT then
if r.dbgl >= 3 then
print(ptime & "Read[" & tost(r.haddr) & "]: [SPLIT]");
end if;
elsif ahbmi.hresp = HRESP_ERROR then
if r.dbgl >= 1 then
print(ptime & "Read[" & tost(r.haddr) & "]: [ERROR]");
end if;
end if;
end if;
if r.hwrite = '1' and ahbmi.hready = '1' and r.oldhtrans /= HTRANS_IDLE then
if ahbmi.hresp = HRESP_OKAY then
if r.dbgl >= 2 then
if r.use128 = 0 then print(ptime & "Write[" & tost(r.haddr) & "]: " & tost(r.hdata));
else
if r.hsize = "100" then print(ptime & "Write[" & tost(r.haddr) & "]: " & tost(r.hdata128));
else print(ptime & "Write[" & tost(r.haddr) & "]: " & tost(r.hdata128(63 downto 0))); end if;
end if;
end if;
elsif ahbmi.hresp = HRESP_RETRY then
if r.dbgl >= 3 then
if r.use128 = 0 then print(ptime & "Write[" & tost(r.haddr) & "]: " & tost(r.hdata) & " [RETRY]");
else
if r.hsize = "100" then print(ptime & "Write[" & tost(r.haddr) & "]: " & tost(r.hdata128) & " [RETRY]");
else print(ptime & "Write[" & tost(r.haddr) & "]: " & tost(r.hdata128(63 downto 0)) & " [RETRY]"); end if;
end if;
end if;
elsif ahbmi.hresp = HRESP_SPLIT then
if r.dbgl >= 3 then
print(ptime & "Write[" & tost(r.haddr) & "]: " & tost(r.hdata)
& " [SPLIT]");
end if;
elsif ahbmi.hresp = HRESP_SPLIT then
if r.dbgl >= 3 then
print(ptime & "Write[" & tost(r.haddr) & "]: " & tost(r.hdata)
& " [SPLIT]");
end if;
elsif ahbmi.hresp = HRESP_ERROR then
if r.dbgl >= 1 then
if r.use128 = 0 then print(ptime & "Write[" & tost(r.haddr) & "]: " & tost(r.hdata) & " [ERROR]");
else
if r.hsize = "100" then print(ptime & "Write[" & tost(r.haddr) & "]: " & tost(r.hdata128) & " [ERROR]");
else print(ptime & "Write[" & tost(r.haddr) & "]: " & tost(r.hdata128(63 downto 0)) & " [ERROR]"); end if;
end if;
end if;
end if;
end if;
-- pragma translate_on
end if;
end process;
end;
| gpl-3.0 | e5567ee56055b808c70aad97c5238179 | 0.534225 | 3.302057 | false | false | false | false |
tmeissner/vhdl_verification | osvvm_fsm_coverage/osvvm_fsm_coverage.vhd | 1 | 3,462 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library std;
use std.env.all;
library osvvm;
use osvvm.NamePkg.all ;
use osvvm.TranscriptPkg.all ;
use osvvm.OsvvmGlobalPkg.all ;
use osvvm.AlertLogPkg.all ;
use osvvm.RandomPkg.all ;
use osvvm.CoveragePkg.all ;
use osvvm.MemoryPkg.all ;
entity osvvm_fsm_coverage is
end entity osvvm_fsm_coverage;
architecture sim of osvvm_fsm_coverage is
type t_fsm_state is (IDLE, ADDR, DATA);
signal s_fsm_state : t_fsm_state;
signal s_clk : std_logic := '0';
signal s_reset_n : std_logic := '0';
shared variable sv_cover : CovPType;
procedure fsm_covadd_states (name : in string;
prev : in t_fsm_state;
curr : in t_fsm_state;
covdb : inout CovPType) is
begin
covdb.AddCross(name,
GenBin(t_fsm_state'pos(prev)),
GenBin(t_fsm_state'pos(curr)));
wait;
end procedure fsm_covadd_states;
procedure fsm_covadd_illegal (name : in string;
covdb : inout CovPType) is
begin
covdb.AddCross(ALL_ILLEGAL, ALL_ILLEGAL);
wait;
end procedure fsm_covadd_illegal;
procedure fsm_covcollect (signal reset : in std_logic;
signal clk : in std_logic;
signal state : in t_fsm_state;
covdb : inout CovPType) is
variable v_state : t_fsm_state := t_fsm_state'left;
begin
wait until reset = '1' and rising_edge(clk);
loop
v_state := state;
wait until rising_edge(s_clk);
covdb.ICover((t_fsm_state'pos(v_state), t_fsm_state'pos(state)));
end loop;
end procedure fsm_covcollect;
begin
s_clk <= not(s_clk) after 5 ns;
s_reset_n <= '1' after 20 ns;
FsmP : process (s_reset_n, s_clk) is
begin
if (s_reset_n = '0') then
s_fsm_state <= IDLE;
elsif (rising_edge(s_clk)) then
case s_fsm_state is
when IDLE => s_fsm_state <= ADDR;
when ADDR => s_fsm_state <= DATA;
when DATA => s_fsm_state <= IDLE;
when others =>
null;
end case;
end if;
end process FsmP;
fsm_covadd_states ("IDLE->ADDR", IDLE, ADDR, sv_cover);
fsm_covadd_states ("ADDR->DATA", ADDR, DATA, sv_cover);
fsm_covadd_states ("DATA->IDLE", DATA, IDLE, sv_cover);
fsm_covadd_illegal ("ILLEGAL", sv_cover);
fsm_covcollect (s_reset_n, s_clk, s_fsm_state, sv_cover);
FinishP : process is
begin
wait until s_clk'active;
if (sv_cover.IsCovered) then
Log("FSM full covered :)", ALWAYS);
sv_cover.SetName("FSM state coverage report");
sv_cover.WriteBin;
stop(0);
end if;
end process FinishP;
-- psl default clock is rising_edge(s_clk);
-- psl IDLE_ADDR : assert always (s_fsm_state = IDLE and s_reset_n = '1') -> next (s_fsm_state = ADDR) abort not(s_reset_n)
-- report "FSM error: IDLE should be followed by ADDR state";
-- psl ADDR_DATA : assert always (s_fsm_state = ADDR and s_reset_n = '1') -> next (s_fsm_state = DATA) abort not(s_reset_n);
-- report "FSM error: ADDR should be followed by DATA state";
-- psl DATA_IDLE : assert always (s_fsm_state = DATA and s_reset_n = '1') -> next (s_fsm_state = IDLE) abort not(s_reset_n);
-- report "FSM error: DATA should be followed by IDLE state";
end architecture sim;
| lgpl-3.0 | 0f26e4fc01b36a3a5c7f8855d43b0dac | 0.592432 | 3.287749 | false | false | false | false |
EliasLuiz/TCC | Leon3/lib/techmap/cycloneiii/cycloneiii_clkgen.vhd | 1 | 7,967 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
-- pragma translate_off
library altera_mf;
use altera_mf.altpll;
-- pragma translate_on
entity cyclone3_pll is
generic (
clk_mul : integer := 1;
clk_div : integer := 1;
clk_freq : integer := 25000;
clk2xen : integer := 0;
sdramen : integer := 0
);
port (
inclk0 : in std_ulogic;
c0 : out std_ulogic;
c0_2x : out std_ulogic;
e0 : out std_ulogic;
locked : out std_ulogic
);
end;
architecture rtl of cyclone3_pll is
component altpll
generic (
intended_device_family : string := "CycloneIII" ;
operation_mode : string := "NORMAL" ;
compensate_clock : string := "clock0";
inclk0_input_frequency : positive;
width_clock : positive := 6;
clk0_multiply_by : positive := 1;
clk0_divide_by : positive := 1;
clk1_multiply_by : positive := 1;
clk1_divide_by : positive := 1;
clk2_multiply_by : positive := 1;
clk2_divide_by : positive := 1;
port_clkena0 : string := "PORT_CONNECTIVITY";
port_clkena1 : string := "PORT_CONNECTIVITY";
port_clkena2 : string := "PORT_CONNECTIVITY";
port_clkena3 : string := "PORT_CONNECTIVITY";
port_clkena4 : string := "PORT_CONNECTIVITY";
port_clkena5 : string := "PORT_CONNECTIVITY"
);
port (
inclk : in std_logic_vector(1 downto 0);
clkena : in std_logic_vector(5 downto 0);
clk : out std_logic_vector(width_clock-1 downto 0);
locked : out std_logic
);
end component;
signal clkena : std_logic_vector (5 downto 0);
signal clkout : std_logic_vector (4 downto 0);
signal inclk : std_logic_vector (1 downto 0);
constant clk_period : integer := 1000000000/clk_freq;
constant CLK_MUL2X : integer := clk_mul * 2;
begin
clkena(5 downto 3) <= (others => '0');
clkena(0) <= '1';
clkena(1) <= '1' when sdramen = 1 else '0';
clkena(2) <= '1' when clk2xen = 1 else '0';
inclk <= '0' & inclk0;
c0 <= clkout(0); c0_2x <= clkout(2); e0 <= clkout(1);
sden : if sdramen = 1 generate
altpll0 : altpll
generic map (
intended_device_family => "Cyclone III",
operation_mode => "ZERO_DELAY_BUFFER", inclk0_input_frequency => clk_period,
width_clock => 5, compensate_clock => "CLK1",
port_clkena2 => "PORT_UNUSED", port_clkena3 => "PORT_UNUSED",
port_clkena4 => "PORT_UNUSED", port_clkena5 => "PORT_UNUSED",
clk0_multiply_by => clk_mul, clk0_divide_by => clk_div,
clk1_multiply_by => clk_mul, clk1_divide_by => clk_div,
clk2_multiply_by => CLK_MUL2X, clk2_divide_by => clk_div)
port map ( clkena => clkena, inclk => inclk,
clk => clkout, locked => locked);
end generate;
-- Must use operation_mode other than "ZERO_DELAY_BUFFER" due to
-- tool issues with ZERO_DELAY_BUFFER and non-existent output clock
nosd : if sdramen = 0 generate
altpll0 : altpll
generic map (
intended_device_family => "Cyclone III",
operation_mode => "NORMAL", inclk0_input_frequency => clk_period,
width_clock => 5,
port_clkena1 => "PORT_UNUSED",
port_clkena2 => "PORT_UNUSED", port_clkena3 => "PORT_UNUSED",
port_clkena4 => "PORT_UNUSED", port_clkena5 => "PORT_UNUSED",
clk0_multiply_by => clk_mul, clk0_divide_by => clk_div,
clk1_multiply_by => clk_mul, clk1_divide_by => clk_div,
clk2_multiply_by => CLK_MUL2X, clk2_divide_by => clk_div)
port map ( clkena => clkena, inclk => inclk,
clk => clkout, locked => locked);
end generate;
end;
library ieee;
use ieee.std_logic_1164.all;
-- pragma translate_off
library altera_mf;
library grlib;
use grlib.stdlib.all;
-- pragma translate_on
library techmap;
use techmap.gencomp.all;
entity clkgen_cycloneiii is
generic (
clk_mul : integer := 1;
clk_div : integer := 1;
sdramen : integer := 0;
sdinvclk : integer := 0;
pcien : integer := 0;
pcidll : integer := 0;
pcisysclk: integer := 0;
freq : integer := 25000;
clk2xen : integer := 0;
tech : integer := 0);
port (
clkin : in std_logic;
pciclkin: in std_logic;
clk : out std_logic; -- main clock
clkn : out std_logic; -- inverted main clock
clk2x : out std_logic; -- double clock
sdclk : out std_logic; -- SDRAM clock
pciclk : out std_logic; -- PCI clock
cgi : in clkgen_in_type;
cgo : out clkgen_out_type);
end;
architecture rtl of clkgen_cycloneiii is
constant VERSION : integer := 1;
constant CLKIN_PERIOD : integer := 20;
signal clk_i : std_logic;
signal clkint, pciclkint : std_logic;
signal pllclk, pllclkn : std_logic; -- generated clocks
signal s_clk : std_logic;
component cyclone3_pll
generic (
clk_mul : integer := 1;
clk_div : integer := 1;
clk_freq : integer := 25000;
clk2xen : integer := 0;
sdramen : integer := 0
);
port (
inclk0 : in std_ulogic;
c0 : out std_ulogic;
c0_2x : out std_ulogic;
e0 : out std_ulogic;
locked : out std_ulogic);
end component;
begin
cgo.pcilock <= '1';
-- c0 : if (PCISYSCLK = 0) generate
-- Clkint <= Clkin;
-- end generate;
-- c1 : if (PCISYSCLK = 1) generate
-- Clkint <= pciclkin;
-- end generate;
-- c2 : if (PCIEN = 1) generate
-- p0 : if (PCIDLL = 1) generate
-- pciclkint <= pciclkin;
-- pciclk <= pciclkint;
-- end generate;
-- p1 : if (PCIDLL = 0) generate
-- u0 : if (PCISYSCLK = 0) generate
-- pciclkint <= pciclkin;
-- end generate;
-- pciclk <= clk_i when (PCISYSCLK = 1) else pciclkint;
-- end generate;
-- end generate;
-- c3 : if (PCIEN = 0) generate
-- pciclk <= Clkint;
-- end generate;
c0: if (PCISYSCLK = 0) or (PCIEN = 0) generate
clkint <= clkin;
end generate c0;
c1: if PCIEN /= 0 generate
d0: if PCISYSCLK = 1 generate
clkint <= pciclkin;
end generate d0;
pciclk <= pciclkin;
end generate c1;
c2: if PCIEN = 0 generate
pciclk <= '0';
end generate c2;
sdclk_pll : cyclone3_pll
generic map (clk_mul, clk_div, freq, clk2xen, sdramen)
port map ( inclk0 => clkint, e0 => sdclk, c0 => s_clk, c0_2x => clk2x,
locked => cgo.clklock);
clk <= s_clk;
clkn <= not s_clk;
-- pragma translate_off
bootmsg : report_version
generic map (
"clkgen_cycloneiii" & ": altpll sdram/pci clock generator, version " & tost(VERSION),
"clkgen_cycloneiii" & ": Frequency " & tost(freq) & " KHz, PLL scaler " & tost(clk_mul) & "/" & tost(clk_div));
-- pragma translate_on
end;
| gpl-3.0 | d5104527d1c51661a166816e06e65f58 | 0.587423 | 3.518993 | false | false | false | false |
EliasLuiz/TCC | Leon3/designs/leon3-terasic-de4/config.vhd | 1 | 7,913 |
-----------------------------------------------------------------------------
-- LEON3 Demonstration design test bench configuration
-- Copyright (C) 2009 Aeroflex Gaisler
------------------------------------------------------------------------------
library techmap;
use techmap.gencomp.all;
package config is
-- Technology and synthesis options
constant CFG_FABTECH : integer := stratix4;
constant CFG_MEMTECH : integer := stratix4;
constant CFG_PADTECH : integer := stratix4;
constant CFG_TRANSTECH : integer := GTP0;
constant CFG_NOASYNC : integer := 0;
constant CFG_SCAN : integer := 0;
-- Clock generator
constant CFG_CLKTECH : integer := stratix4;
constant CFG_CLKMUL : integer := (5);
constant CFG_CLKDIV : integer := (5);
constant CFG_OCLKDIV : integer := 1;
constant CFG_OCLKBDIV : integer := 0;
constant CFG_OCLKCDIV : integer := 0;
constant CFG_PCIDLL : integer := 0;
constant CFG_PCISYSCLK: integer := 0;
constant CFG_CLK_NOFB : integer := 0;
-- LEON3 processor core
constant CFG_LEON3 : integer := 1;
constant CFG_NCPU : integer := (1);
constant CFG_NWIN : integer := (8);
constant CFG_V8 : integer := 16#32# + 4*0;
constant CFG_MAC : integer := 0;
constant CFG_BP : integer := 1;
constant CFG_SVT : integer := 1;
constant CFG_RSTADDR : integer := 16#00000#;
constant CFG_LDDEL : integer := (1);
constant CFG_NOTAG : integer := 0;
constant CFG_NWP : integer := (2);
constant CFG_PWD : integer := 1*2;
constant CFG_FPU : integer := 0 + 16*0 + 32*0;
constant CFG_GRFPUSH : integer := 0;
constant CFG_ICEN : integer := 1;
constant CFG_ISETS : integer := 4;
constant CFG_ISETSZ : integer := 4;
constant CFG_ILINE : integer := 8;
constant CFG_IREPL : integer := 0;
constant CFG_ILOCK : integer := 0;
constant CFG_ILRAMEN : integer := 0;
constant CFG_ILRAMADDR: integer := 16#8E#;
constant CFG_ILRAMSZ : integer := 1;
constant CFG_DCEN : integer := 1;
constant CFG_DSETS : integer := 4;
constant CFG_DSETSZ : integer := 4;
constant CFG_DLINE : integer := 4;
constant CFG_DREPL : integer := 0;
constant CFG_DLOCK : integer := 0;
constant CFG_DSNOOP : integer := 0 + 1*2 + 4*1;
constant CFG_DFIXED : integer := 16#0#;
constant CFG_DLRAMEN : integer := 0;
constant CFG_DLRAMADDR: integer := 16#8F#;
constant CFG_DLRAMSZ : integer := 1;
constant CFG_MMUEN : integer := 1;
constant CFG_ITLBNUM : integer := 8;
constant CFG_DTLBNUM : integer := 8;
constant CFG_TLB_TYPE : integer := 0 + 1*2;
constant CFG_TLB_REP : integer := 0;
constant CFG_MMU_PAGE : integer := 0;
constant CFG_DSU : integer := 1;
constant CFG_ITBSZ : integer := 2 + 64*0;
constant CFG_ATBSZ : integer := 2;
constant CFG_AHBPF : integer := 0;
constant CFG_LEON3FT_EN : integer := 0;
constant CFG_IUFT_EN : integer := 0;
constant CFG_FPUFT_EN : integer := 0;
constant CFG_RF_ERRINJ : integer := 0;
constant CFG_CACHE_FT_EN : integer := 0;
constant CFG_CACHE_ERRINJ : integer := 0;
constant CFG_LEON3_NETLIST: integer := 0;
constant CFG_DISAS : integer := 0 + 0;
constant CFG_PCLOW : integer := 2;
constant CFG_STAT_ENABLE : integer := 0;
constant CFG_STAT_CNT : integer := 1;
constant CFG_STAT_NMAX : integer := 0;
constant CFG_STAT_DSUEN : integer := 0;
constant CFG_NP_ASI : integer := 0;
constant CFG_WRPSR : integer := 0;
constant CFG_ALTWIN : integer := 0;
constant CFG_REX : integer := 0;
-- L2 Cache
constant CFG_L2_EN : integer := 0;
constant CFG_L2_SIZE : integer := 32;
constant CFG_L2_WAYS : integer := 4;
constant CFG_L2_HPROT : integer := 0;
constant CFG_L2_PEN : integer := 0;
constant CFG_L2_WT : integer := 0;
constant CFG_L2_RAN : integer := 0;
constant CFG_L2_SHARE : integer := 0;
constant CFG_L2_LSZ : integer := 64;
constant CFG_L2_MAP : integer := 16#00F0#;
constant CFG_L2_MTRR : integer := (8);
constant CFG_L2_EDAC : integer := 0;
-- AMBA settings
constant CFG_DEFMST : integer := (0);
constant CFG_RROBIN : integer := 1;
constant CFG_SPLIT : integer := 0;
constant CFG_FPNPEN : integer := 1;
constant CFG_AHBIO : integer := 16#FFF#;
constant CFG_APBADDR : integer := 16#800#;
constant CFG_AHB_MON : integer := 0;
constant CFG_AHB_MONERR : integer := 0;
constant CFG_AHB_MONWAR : integer := 0;
constant CFG_AHB_DTRACE : integer := 0;
-- DSU UART
constant CFG_AHB_UART : integer := 1;
-- JTAG based DSU interface
constant CFG_AHB_JTAG : integer := 1;
-- Ethernet DSU
constant CFG_DSU_ETH : integer := 1 + 1 + 1;
constant CFG_ETH_BUF : integer := 2;
constant CFG_ETH_IPM : integer := 16#C0A8#;
constant CFG_ETH_IPL : integer := 16#0033#;
constant CFG_ETH_ENM : integer := 16#020000#;
constant CFG_ETH_ENL : integer := 16#000009#;
-- LEON2 memory controller
constant CFG_MCTRL_LEON2 : integer := 1;
constant CFG_MCTRL_RAM8BIT : integer := 0;
constant CFG_MCTRL_RAM16BIT : integer := 1;
constant CFG_MCTRL_5CS : integer := 0;
constant CFG_MCTRL_SDEN : integer := 0;
constant CFG_MCTRL_SEPBUS : integer := 0;
constant CFG_MCTRL_INVCLK : integer := 0;
constant CFG_MCTRL_SD64 : integer := 0;
constant CFG_MCTRL_PAGE : integer := 0 + 0;
-- DDR controller
constant CFG_DDR2SP : integer := 1;
constant CFG_DDR2SP_INIT : integer := 0;
constant CFG_DDR2SP_FREQ : integer := (50);
constant CFG_DDR2SP_TRFC : integer := (128);
constant CFG_DDR2SP_DATAWIDTH : integer := (64);
constant CFG_DDR2SP_FTEN : integer := 0;
constant CFG_DDR2SP_FTWIDTH : integer := 0;
constant CFG_DDR2SP_COL : integer := 9;
constant CFG_DDR2SP_SIZE : integer := 8;
constant CFG_DDR2SP_DELAY0 : integer := (0);
constant CFG_DDR2SP_DELAY1 : integer := (0);
constant CFG_DDR2SP_DELAY2 : integer := (0);
constant CFG_DDR2SP_DELAY3 : integer := (0);
constant CFG_DDR2SP_DELAY4 : integer := (0);
constant CFG_DDR2SP_DELAY5 : integer := (0);
constant CFG_DDR2SP_DELAY6 : integer := (0);
constant CFG_DDR2SP_DELAY7 : integer := (0);
constant CFG_DDR2SP_NOSYNC : integer := 0;
-- AHB status register
constant CFG_AHBSTAT : integer := 1;
constant CFG_AHBSTATN : integer := (1);
-- AHB RAM
constant CFG_AHBRAMEN : integer := 0;
constant CFG_AHBRSZ : integer := 1;
constant CFG_AHBRADDR : integer := 16#A00#;
constant CFG_AHBRPIPE : integer := 0;
-- Gaisler Ethernet core
constant CFG_GRETH : integer := 1;
constant CFG_GRETH1G : integer := 0;
constant CFG_ETH_FIFO : integer := 8;
-- Gaisler Ethernet core
constant CFG_GRETH2 : integer := 1;
constant CFG_GRETH21G : integer := 0;
constant CFG_ETH2_FIFO : integer := 8;
-- SPI controller
constant CFG_SPICTRL_ENABLE : integer := 1;
constant CFG_SPICTRL_NUM : integer := (1);
constant CFG_SPICTRL_SLVS : integer := (2);
constant CFG_SPICTRL_FIFO : integer := (2);
constant CFG_SPICTRL_SLVREG : integer := 1;
constant CFG_SPICTRL_ODMODE : integer := 1;
constant CFG_SPICTRL_AM : integer := 0;
constant CFG_SPICTRL_ASEL : integer := 0;
constant CFG_SPICTRL_TWEN : integer := 1;
constant CFG_SPICTRL_MAXWLEN : integer := (0);
constant CFG_SPICTRL_SYNCRAM : integer := 1;
constant CFG_SPICTRL_FT : integer := 0;
-- UART 1
constant CFG_UART1_ENABLE : integer := 1;
constant CFG_UART1_FIFO : integer := 4;
-- LEON3 interrupt controller
constant CFG_IRQ3_ENABLE : integer := 1;
constant CFG_IRQ3_NSEC : integer := 0;
-- Modular timer
constant CFG_GPT_ENABLE : integer := 1;
constant CFG_GPT_NTIM : integer := (2);
constant CFG_GPT_SW : integer := (16);
constant CFG_GPT_TW : integer := (32);
constant CFG_GPT_IRQ : integer := (8);
constant CFG_GPT_SEPIRQ : integer := 1;
constant CFG_GPT_WDOGEN : integer := 0;
constant CFG_GPT_WDOG : integer := 16#0#;
-- GPIO port
constant CFG_GRGPIO_ENABLE : integer := 1;
constant CFG_GRGPIO_IMASK : integer := 16#fe#;
constant CFG_GRGPIO_WIDTH : integer := (32);
-- GRLIB debugging
constant CFG_DUART : integer := 0;
end;
| gpl-3.0 | 00d69d13ba824ec1eb145660c1a52bbb | 0.647795 | 3.499779 | false | false | false | false |
EliasLuiz/TCC | Leon3/lib/techmap/maps/syncram_2p.vhd | 1 | 15,962 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: syncram_2p
-- File: syncram_2p.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: syncronous 2-port ram with tech selection
------------------------------------------------------------------------------
library ieee;
library techmap;
use ieee.std_logic_1164.all;
use techmap.gencomp.all;
use work.allmem.all;
library grlib;
use grlib.config.all;
use grlib.config_types.all;
use grlib.stdlib.all;
entity syncram_2p is
generic (tech : integer := 0; abits : integer := 6; dbits : integer := 8;
sepclk : integer := 0; wrfst : integer := 0; testen : integer := 0;
words : integer := 0; custombits : integer := 1);
port (
rclk : in std_ulogic;
renable : in std_ulogic;
raddress : in std_logic_vector((abits -1) downto 0);
dataout : out std_logic_vector((dbits -1) downto 0);
wclk : in std_ulogic;
write : in std_ulogic;
waddress : in std_logic_vector((abits -1) downto 0);
datain : in std_logic_vector((dbits -1) downto 0);
testin : in std_logic_vector(TESTIN_WIDTH-1 downto 0) := testin_none
);
end;
architecture rtl of syncram_2p is
constant nctrl : integer := abits*2 + (TESTIN_WIDTH-2) + 2;
signal gnd : std_ulogic;
signal vgnd : std_logic_vector(dbits-1 downto 0);
signal dataoutx, dataoutxx : std_logic_vector((dbits -1) downto 0);
signal tmode: std_ulogic;
signal testdata : std_logic_vector((dbits -1) downto 0);
signal renable2 : std_ulogic;
constant SCANTESTBP : boolean := (testen = 1) and syncram_add_scan_bypass(tech)=1;
constant iwrfst : integer := (1-syncram_2p_write_through(tech)) * wrfst;
signal xrenable,xwrite : std_ulogic;
signal custominx,customoutx: std_logic_vector(syncram_customif_maxwidth downto 0);
signal customclkx: std_ulogic;
component memrwcol is
generic (
techwrfst : integer;
techrwcol : integer;
techrdhold : integer;
abits: integer;
dbits: integer;
sepclk: integer;
wrfst: integer
);
port (
clk1 : in std_ulogic;
clk2 : in std_ulogic;
uenable1 : in std_ulogic;
uwrite1 : in std_ulogic;
uaddress1: in std_logic_vector((abits-1) downto 0);
udatain1 : in std_logic_vector((dbits-1) downto 0);
udataout1: out std_logic_vector((dbits-1) downto 0);
uenable2 : in std_ulogic;
uwrite2 : in std_ulogic;
uaddress2: in std_logic_vector((abits-1) downto 0);
udatain2 : in std_logic_vector((dbits-1) downto 0);
udataout2: out std_logic_vector((dbits-1) downto 0);
menable1 : out std_ulogic;
menable2 : out std_ulogic;
mdataout1: in std_logic_vector((dbits-1) downto 0);
mdataout2: in std_logic_vector((dbits-1) downto 0);
testmode : in std_ulogic;
testdata : in std_logic_vector((dbits-1) downto 0)
);
end component;
begin
gnd <= '0'; vgnd <= (others => '0');
xrenable <= renable and not testin(TESTIN_WIDTH-2) when testen/=0 else renable;
xwrite <= write and not testin(TESTIN_WIDTH-2) when testen/=0 else write;
dataout <= dataoutxx;
rwcol0: memrwcol
generic map (
techwrfst => syncram_2p_write_through(tech),
techrwcol => syncram_2p_dest_rw_collision(tech),
techrdhold => syncram_2p_readhold(tech),
abits => abits,
dbits => dbits,
sepclk => sepclk,
wrfst => wrfst)
port map (
clk1 => rclk,
clk2 => wclk,
uenable1 => xrenable,
uwrite1 => '0',
uaddress1 => raddress,
udatain1 => vgnd,
udataout1 => dataoutxx,
uenable2 => '1',
uwrite2 => write,
uaddress2 => waddress,
udatain2 => datain,
udataout2 => open,
menable1 => renable2,
menable2 => open,
mdataout1 => dataoutx,
mdataout2 => vgnd,
testmode => tmode,
testdata => testdata
);
tmode <= testin(TESTIN_WIDTH-1) when SCANTESTBP else '0';
scanbp : if SCANTESTBP generate
comb : process (waddress, raddress, datain, renable, write, testin)
variable tmp : std_logic_vector((dbits -1) downto 0);
variable ctrlsigs : std_logic_vector((nctrl -1) downto 0);
begin
ctrlsigs := testin(TESTIN_WIDTH-3 downto 0) & write & renable & raddress & waddress;
tmp := datain;
for i in 0 to nctrl-1 loop
tmp(i mod dbits) := tmp(i mod dbits) xor ctrlsigs(i);
end loop;
testdata <= tmp;
end process;
end generate;
noscanbp : if not SCANTESTBP generate
testdata <= (others => '0');
end generate;
custominx <= (others => '0');
customclkx <= '0';
nocust: if syncram_has_customif(tech)=0 generate
customoutx <= (others => '0');
end generate;
inf : if tech = inferred generate
x0 : generic_syncram_2p generic map (abits, dbits, sepclk)
port map (rclk, wclk, raddress, waddress, datain, write, dataoutx);
end generate;
xcv : if tech = virtex generate
x0 : virtex_syncram_dp generic map (abits, dbits)
port map (wclk, waddress, datain, open, xwrite, xwrite,
rclk, raddress, vgnd, dataoutx, renable2, gnd);
end generate;
xc2v : if (is_unisim(tech) = 1) and (tech /= virtex)generate
x0 : unisim_syncram_2p generic map (abits, dbits, sepclk, iwrfst)
port map (rclk, renable2, raddress, dataoutx, wclk,
xwrite, waddress, datain);
end generate;
vir : if tech = memvirage generate
d39 : if dbits = 39 generate
x0 : virage_syncram_2p generic map (abits, dbits, sepclk)
port map (rclk, renable2, raddress, dataoutx,
wclk, xwrite, waddress, datain);
end generate;
d32 : if dbits <= 32 generate
x0 : virage_syncram_dp generic map (abits, dbits)
port map (wclk, waddress, datain, open, xwrite, xwrite,
rclk, raddress, vgnd, dataoutx, renable2, gnd);
end generate;
end generate;
atrh : if tech = atc18rha generate
x0 : atc18rha_syncram_2p generic map (abits, dbits, sepclk)
port map (rclk, renable2, raddress, dataoutx,
wclk, xwrite, waddress, datain, testin(TESTIN_WIDTH-1 downto TESTIN_WIDTH-4));
end generate;
axc : if (tech = axcel) or (tech = axdsp) generate
x0 : axcel_syncram_2p generic map (abits, dbits, sepclk)
port map (rclk, renable2, raddress, dataoutx,
wclk, waddress, datain, xwrite);
end generate;
proa : if tech = proasic generate
x0 : proasic_syncram_2p generic map (abits, dbits)
port map (rclk, renable2, raddress, dataoutx,
wclk, waddress, datain, xwrite);
end generate;
proa3 : if tech = apa3 generate
x0 : proasic3_syncram_2p generic map (abits, dbits, sepclk)
port map (rclk, renable2, raddress, dataoutx,
wclk, waddress, datain, xwrite);
end generate;
proa3e : if tech = apa3e generate
x0 : proasic3e_syncram_2p generic map (abits, dbits, sepclk)
port map (rclk, renable2, raddress, dataoutx,
wclk, waddress, datain, xwrite);
end generate;
proa3l : if tech = apa3l generate
x0 : proasic3l_syncram_2p generic map (abits, dbits, sepclk)
port map (rclk, renable2, raddress, dataoutx,
wclk, waddress, datain, xwrite);
end generate;
igl2 : if tech = igloo2 generate
x0 : igloo2_syncram_2p generic map (abits, dbits, sepclk)
port map (rclk, renable2, raddress, dataoutx,
wclk, waddress, datain, xwrite);
end generate;
rt4 : if tech = rtg4 generate
x0 : rtg4_syncram_2p generic map (abits, dbits, sepclk)
port map (rclk, renable2, raddress, dataoutx, open,
wclk, xwrite, waddress, datain, gnd);
end generate;
saed : if tech = saed32 generate
-- x0 : saed32_syncram_2p generic map (abits, dbits, sepclk)
-- port map (rclk, renable2, raddress, dataoutx,
-- wclk, waddress, datain, xwrite);
x0 : generic_syncram_2p generic map (abits, dbits, sepclk)
port map (rclk, wclk, raddress, waddress, datain, write, dataoutx);
end generate;
rhs : if tech = rhs65 generate
x0 : rhs65_syncram_2p generic map (abits, dbits, sepclk)
port map (rclk, renable, raddress, dataoutx,
wclk, waddress, datain, write,
testin(TESTIN_WIDTH-8),testin(TESTIN_WIDTH-3),
custominx(0),customoutx(0),
testin(TESTIN_WIDTH-4),testin(TESTIN_WIDTH-5),testin(TESTIN_WIDTH-6),
customclkx,
testin(TESTIN_WIDTH-7),'0',customoutx(1),
customoutx(7 downto 2));
customoutx(customoutx'high downto 8) <= (others => '0');
end generate;
dar : if tech = dare generate
x0 : dare_syncram_2p generic map (abits, dbits, sepclk)
port map (rclk, renable2, raddress, dataoutx,
wclk, waddress, datain, xwrite);
end generate;
rhu : if tech = rhumc generate
x0 : rhumc_syncram_2p generic map (abits, dbits, sepclk)
port map (rclk, renable2, raddress, dataoutx,
wclk, waddress, datain, xwrite);
end generate;
fus : if tech = actfus generate
x0 : fusion_syncram_2p generic map (abits, dbits)
port map (rclk, renable2, raddress, dataoutx,
wclk, waddress, datain, xwrite);
end generate;
ihp : if tech = ihp25 generate
x0 : generic_syncram_2p generic map (abits, dbits, sepclk)
port map (rclk, wclk, raddress, waddress, datain, xwrite, dataoutx);
end generate;
-- NOTE: port 1 on altsyncram must be a read port due to Cyclone II M4K write issue
alt : if (tech = altera) or (tech = stratix1) or (tech = stratix2) or
(tech = stratix3) or (tech = stratix4) or (tech = cyclone3) generate
x0 : altera_syncram_dp generic map (abits, dbits)
port map (rclk, raddress, vgnd, dataoutx, renable2, gnd,
wclk, waddress, datain, open, xwrite, xwrite);
end generate;
rh_lib18t0 : if tech = rhlib18t generate
x0 : rh_lib18t_syncram_2p generic map (abits, dbits, sepclk)
port map (rclk, renable2, raddress, dataoutx, wclk, xwrite, waddress, datain,
testin(TESTIN_WIDTH-1 downto TESTIN_WIDTH-4));
end generate;
lat : if tech = lattice generate
x0 : ec_syncram_dp generic map (abits, dbits)
port map (wclk, waddress, datain, open, xwrite, xwrite,
rclk, raddress, vgnd, dataoutx, renable2, gnd);
end generate;
ut025 : if tech = ut25 generate
x0 : ut025crh_syncram_2p generic map (abits, dbits)
port map (rclk, renable2, raddress, dataoutx,
wclk, waddress, datain, xwrite);
end generate;
ut09 : if tech = ut90 generate
x0 : ut90nhbd_syncram_2p generic map (abits, dbits)
port map (rclk, renable2, raddress, dataoutx,
wclk, xwrite, waddress, datain, testin(TESTIN_WIDTH-3));
end generate;
ut13 : if tech = ut130 generate
x0 : ut130hbd_syncram_2p generic map (abits, dbits, words)
port map (rclk, renable2, raddress, dataoutx,
wclk, xwrite, waddress, datain);
end generate;
arti : if tech = memartisan generate
x0 : artisan_syncram_2p generic map (abits, dbits)
port map (rclk, renable2, raddress, dataoutx,
wclk, xwrite, waddress, datain);
end generate;
cust1 : if tech = custom1 generate
x0 : custom1_syncram_2p generic map (abits, dbits)
port map (rclk, renable2, raddress, dataoutx,
wclk, xwrite, waddress, datain);
end generate;
ecl : if tech = eclipse generate
x0 : eclipse_syncram_2p generic map (abits, dbits)
port map (rclk, renable2, raddress, dataoutx,
wclk, waddress, datain, xwrite);
end generate;
vir90 : if tech = memvirage90 generate
x0 : virage90_syncram_dp generic map (abits, dbits)
port map (wclk, waddress, datain, open, xwrite, xwrite,
rclk, raddress, vgnd, dataoutx, renable2, gnd);
end generate;
nex : if tech = easic90 generate
x0 : nextreme_syncram_2p generic map (abits, dbits)
port map (rclk, renable2, raddress, dataoutx,
wclk, xwrite, waddress, datain);
end generate;
smic : if tech = smic013 generate
x0 : smic13_syncram_2p generic map (abits, dbits)
port map (rclk, renable2, raddress, dataoutx,
wclk, xwrite, waddress, datain);
end generate;
tm65gplu : if tech = tm65gplus generate
x0 : tm65gplus_syncram_2p generic map (abits, dbits)
port map (rclk, renable2, raddress, dataoutx,
wclk, xwrite, waddress, datain);
end generate;
cmos9sfx : if tech = cmos9sf generate
x0 : cmos9sf_syncram_2p generic map (abits, dbits)
port map (rclk, renable2, raddress, dataoutx,
wclk, xwrite, waddress, datain);
end generate;
n2x : if tech = easic45 generate
x0 : n2x_syncram_2p generic map (abits, dbits, sepclk, iwrfst)
port map (rclk, renable2, raddress, dataoutx, wclk,
xwrite, waddress, datain);
end generate;
rh_lib13t0 : if tech = rhlib13t generate
x0 : rh_lib13t_syncram_2p generic map (abits, dbits, sepclk)
port map (rclk, renable2, raddress, dataoutx, wclk, xwrite, waddress, datain,
testin(TESTIN_WIDTH-1 downto TESTIN_WIDTH-4));
end generate;
-- pragma translate_off
noram : if has_2pram(tech) = 0 generate
x : process
begin
assert false report "synram_2p: technology " & tech_table(tech) &
" not supported"
severity failure;
wait;
end process;
end generate;
dmsg : if GRLIB_CONFIG_ARRAY(grlib_debug_level) >= 2 generate
x : process
begin
assert false report "syncram_2p: " & tost(2**abits) & "x" & tost(dbits) &
" (" & tech_table(tech) & ")"
severity note;
wait;
end process;
end generate;
generic_check : process
begin
assert sepclk = 0 or wrfst = 0
report "syncram_2p: Write-first not supported for RAM with separate clocks"
severity failure;
wait;
end process;
chk : if GRLIB_CONFIG_ARRAY(grlib_syncram_selftest_enable) /= 0 generate
chkblk: block
signal refdo,pwdata: std_logic_vector(dbits-1 downto 0);
signal pren,bpen: std_ulogic;
signal praddr,pwaddr: std_logic_vector(abits-1 downto 0);
begin
refram : generic_syncram_2p generic map (abits, dbits, 1)
port map (rclk, wclk, raddress, waddress, datain, write, refdo);
p: process(rclk)
begin
if rising_edge(rclk) then
assert pren/='1' or (bpen='0' and refdo=dataoutxx) or
(bpen='1' and pwdata=dataoutxx) or is_x(refdo) or is_x(praddr)
report "Read mismatch addr=" & tost(praddr) & " impl=" & tost(dataoutxx) & " ref=" & tost(refdo)
severity error;
pren <= renable;
praddr <= raddress;
pwdata <= datain;
if wrfst/=0 and renable='1' and write='1' and raddress=waddress then
bpen <= '1';
else
bpen <= '0';
end if;
end if;
end process;
end block;
end generate;
-- pragma translate_on
end;
| gpl-3.0 | 2812b5a7c3a24c104156301402fc32da | 0.631124 | 3.693198 | false | true | false | false |
EliasLuiz/TCC | Leon3/designs/leon3-xilinx-ml50x/ahb2mig_ml50x.vhd | 2 | 23,819 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: ahb2mig
-- File: ahb2mig.vhd
-- Author: Jiri Gaisler, Gaisler Research
-- Description: AHB wrapper for Xilinx Virtex5 DDR2/3 MIG
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
package ml50x is
constant BANK_WIDTH : integer := 2; -- # of memory bank addr bits.
constant CKE_WIDTH : integer := 2; -- # of memory clock enable outputs.
constant CLK_WIDTH : integer := 2; -- # of clock outputs.
constant COL_WIDTH : integer := 10; -- # of memory column bits.
constant CS_NUM : integer := 1; --2; -- # of separate memory chip selects.
constant CS_WIDTH : integer := 1; --2; -- # of total memory chip selects.
constant CS_BITS : integer := 0; --1; -- set to log2(CS_NUM) (rounded up).
constant DM_WIDTH : integer := 8; -- # of data mask bits.
constant DQ_WIDTH : integer := 64; -- # of data width.
constant DQ_PER_DQS : integer := 8; -- # of DQ data bits per strobe.
constant DQS_WIDTH : integer := 8; -- # of DQS strobes.
constant DQ_BITS : integer := 6; -- set to log2(DQS_WIDTH*DQ_PER_DQS).
constant DQS_BITS : integer := 3; -- set to log2(DQS_WIDTH).
constant ODT_WIDTH : integer := 1; -- # of memory on-die term enables.
constant ROW_WIDTH : integer := 13; -- # of memory row and # of addr bits.
constant APPDATA_WIDTH : integer := 128; -- # of usr read/write data bus bits.
constant ADDR_WIDTH : integer := 31; -- # of memory row and # of addr bits.
constant MIGHMASK : integer := 16#F00#; -- AHB mask for 256 Mbyte memory
-- constant MIGHMASK : integer := 16#E00#; -- AHB mask for 512 Mbyte memory
-- constant MIGHMASK : integer := 16#C00#; -- AHB mask for 1024 Mbyte memory
type mig_app_in_type is record
app_wdf_wren : std_logic;
app_wdf_data : std_logic_vector(APPDATA_WIDTH-1 downto 0);
app_wdf_mask : std_logic_vector(APPDATA_WIDTH/8-1 downto 0);
app_addr : std_logic_vector(ADDR_WIDTH-1 downto 0);
app_cmd : std_logic_vector(2 downto 0);
app_en : std_logic;
end record;
type mig_app_out_type is record
app_af_afull : std_logic;
app_wdf_afull : std_logic;
app_rd_data : std_logic_vector(APPDATA_WIDTH-1 downto 0);
app_rd_data_valid : std_logic;
end record;
component mig_36_1
generic(
BANK_WIDTH : integer := 2;
-- # of memory bank addr bits.
CKE_WIDTH : integer := 1;
-- # of memory clock enable outputs.
CLK_WIDTH : integer := 2;
-- # of clock outputs.
COL_WIDTH : integer := 10;
-- # of memory column bits.
CS_NUM : integer := 1;
-- # of separate memory chip selects.
CS_WIDTH : integer := 1;
-- # of total memory chip selects.
CS_BITS : integer := 0;
-- set to log2(CS_NUM) (rounded up).
DM_WIDTH : integer := 8;
-- # of data mask bits.
DQ_WIDTH : integer := 64;
-- # of data width.
DQ_PER_DQS : integer := 8;
-- # of DQ data bits per strobe.
DQS_WIDTH : integer := 8;
-- # of DQS strobes.
DQ_BITS : integer := 6;
-- set to log2(DQS_WIDTH*DQ_PER_DQS).
DQS_BITS : integer := 3;
-- set to log2(DQS_WIDTH).
ODT_WIDTH : integer := 1;
-- # of memory on-die term enables.
ROW_WIDTH : integer := 13;
-- # of memory row and # of addr bits.
ADDITIVE_LAT : integer := 0;
-- additive write latency.
BURST_LEN : integer := 4;
-- burst length (in double words).
BURST_TYPE : integer := 0;
-- burst type (=0 seq; =1 interleaved).
CAS_LAT : integer := 3;
-- CAS latency.
ECC_ENABLE : integer := 0;
-- enable ECC (=1 enable).
APPDATA_WIDTH : integer := 128;
-- # of usr read/write data bus bits.
MULTI_BANK_EN : integer := 1;
-- Keeps multiple banks open. (= 1 enable).
TWO_T_TIME_EN : integer := 1;
-- 2t timing for unbuffered dimms.
ODT_TYPE : integer := 1;
-- ODT (=0(none),=1(75),=2(150),=3(50)).
REDUCE_DRV : integer := 0;
-- reduced strength mem I/O (=1 yes).
REG_ENABLE : integer := 0;
-- registered addr/ctrl (=1 yes).
TREFI_NS : integer := 7800;
-- auto refresh interval (ns).
TRAS : integer := 40000;
-- active->precharge delay.
TRCD : integer := 15000;
-- active->read/write delay.
TRFC : integer := 105000;
-- refresh->refresh, refresh->active delay.
TRP : integer := 15000;
-- precharge->command delay.
TRTP : integer := 7500;
-- read->precharge delay.
TWR : integer := 15000;
-- used to determine write->precharge.
TWTR : integer := 10000;
-- write->read delay.
HIGH_PERFORMANCE_MODE : boolean := TRUE;
-- # = TRUE, the IODELAY performance mode is set
-- to high.
-- # = FALSE, the IODELAY performance mode is set
-- to low.
SIM_ONLY : integer := 0;
-- = 1 to skip SDRAM power up delay.
DEBUG_EN : integer := 0;
-- Enable debug signals/controls.
-- When this parameter is changed from 0 to 1,
-- make sure to uncomment the coregen commands
-- in ise_flow.bat or create_ise.bat files in
-- par folder.
CLK_PERIOD : integer := 5000;
-- Core/Memory clock period (in ps).
DLL_FREQ_MODE : string := "HIGH";
-- DCM Frequency range.
CLK_TYPE : string := "SINGLE_ENDED";
-- # = "DIFFERENTIAL " ->; Differential input clocks ,
-- # = "SINGLE_ENDED" -> Single ended input clocks.
NOCLK200 : boolean := FALSE;
-- clk200 enable and disable
RST_ACT_LOW : integer := 1
-- =1 for active low reset, =0 for active high.
);
port(
ddr2_dq : inout std_logic_vector((DQ_WIDTH-1) downto 0);
ddr2_a : out std_logic_vector((ROW_WIDTH-1) downto 0);
ddr2_ba : out std_logic_vector((BANK_WIDTH-1) downto 0);
ddr2_ras_n : out std_logic;
ddr2_cas_n : out std_logic;
ddr2_we_n : out std_logic;
ddr2_cs_n : out std_logic_vector((CS_WIDTH-1) downto 0);
ddr2_odt : out std_logic_vector((ODT_WIDTH-1) downto 0);
ddr2_cke : out std_logic_vector((CKE_WIDTH-1) downto 0);
ddr2_dm : out std_logic_vector((DM_WIDTH-1) downto 0);
sys_clk : in std_logic;
idly_clk_200 : in std_logic;
sys_rst_n : in std_logic;
phy_init_done : out std_logic;
rst0_tb : out std_logic;
clk0_tb : out std_logic;
app_wdf_afull : out std_logic;
app_af_afull : out std_logic;
rd_data_valid : out std_logic;
app_wdf_wren : in std_logic;
app_af_wren : in std_logic;
app_af_addr : in std_logic_vector(30 downto 0);
app_af_cmd : in std_logic_vector(2 downto 0);
rd_data_fifo_out : out std_logic_vector((APPDATA_WIDTH-1) downto 0);
app_wdf_data : in std_logic_vector((APPDATA_WIDTH-1) downto 0);
app_wdf_mask_data : in std_logic_vector((APPDATA_WIDTH/8-1) downto 0);
ddr2_dqs : inout std_logic_vector((DQS_WIDTH-1) downto 0);
ddr2_dqs_n : inout std_logic_vector((DQS_WIDTH-1) downto 0);
ddr2_ck : out std_logic_vector((CLK_WIDTH-1) downto 0);
ddr2_ck_n : out std_logic_vector((CLK_WIDTH-1) downto 0)
);
end component ;
end package;
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
library gaisler;
use grlib.devices.all;
use gaisler.memctrl.all;
library techmap;
use techmap.gencomp.all;
use work.ml50x.all;
entity ahb2mig_ml50x is
generic (
memtech : integer := 0;
hindex : integer := 0;
haddr : integer := 0;
hmask : integer := 16#e00#;
MHz : integer := 100;
Mbyte : integer := 512;
nosync : integer := 0
);
port (
rst_ddr : in std_ulogic;
rst_ahb : in std_ulogic;
clk_ddr : in std_ulogic;
clk_ahb : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
migi : out mig_app_in_type;
migo : in mig_app_out_type
);
end;
architecture rtl of ahb2mig_ml50x is
constant REVISION : integer := 0;
constant hconfig : ahb_config_type := (
0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_MIGDDR2, 0, REVISION, 0),
4 => ahb_membar(haddr, '1', '1', hmask),
others => zero32);
type ahb_state_type is (midle, rhold, dread, dwrite, whold1, whold2);
type ddr_state_type is (midle, rhold, dread, dwrite, whold1, whold2);
constant abuf : integer := 6;
type access_param is record
haddr : std_logic_vector(31 downto 0);
size : std_logic_vector(2 downto 0);
hwrite : std_ulogic;
end record;
-- local registers
type mem is array(0 to 7) of std_logic_vector(31 downto 0);
type wrm is array(0 to 7) of std_logic_vector(3 downto 0);
type ahb_reg_type is record
hready : std_ulogic;
hsel : std_ulogic;
startsd : std_ulogic;
state : ahb_state_type;
haddr : std_logic_vector(31 downto 0);
hrdata : std_logic_vector(127 downto 0);
hwrite : std_ulogic;
htrans : std_logic_vector(1 downto 0);
hresp : std_logic_vector(1 downto 0);
raddr : std_logic_vector(abuf-1 downto 0);
size : std_logic_vector(2 downto 0);
acc : access_param;
sync : std_ulogic;
hwdata : mem;
write : wrm;
end record;
type ddr_reg_type is record
startsd : std_ulogic;
hrdata : std_logic_vector(255 downto 0);
sync : std_ulogic;
dstate : ahb_state_type;
end record;
signal vcc, clk_ahb1, clk_ahb2 : std_ulogic;
signal r, ri : ddr_reg_type;
signal ra, rai : ahb_reg_type;
signal rbdrive, ribdrive : std_logic_vector(31 downto 0);
signal hwdata, hwdatab : std_logic_vector(127 downto 0);
begin
vcc <= '1';
ahb_ctrl : process(rst_ahb, ahbsi, r, ra, migo, hwdata)
variable va : ahb_reg_type; -- local variables for registers
variable startsd : std_ulogic;
variable ready : std_logic;
variable tmp : std_logic_vector(3 downto 0);
variable waddr : integer;
variable rdata : std_logic_vector(127 downto 0);
begin
va := ra; va.hresp := HRESP_OKAY;
tmp := (others => '0');
case ra.raddr(2 downto 2) is
when "0" => rdata := r.hrdata(127 downto 0);
when others => rdata := r.hrdata(255 downto 128);
end case;
if AHBDW > 64 and ra.size = HSIZE_4WORD then
va.hrdata := rdata(63 downto 0) & rdata(127 downto 64);
elsif AHBDW > 32 and ra.size = HSIZE_DWORD then
if ra.raddr(1) = '1' then va.hrdata(63 downto 0) := rdata(127 downto 64);
else va.hrdata(63 downto 0) := rdata(63 downto 0); end if;
va.hrdata(127 downto 64) := va.hrdata(63 downto 0);
else
case ra.raddr(1 downto 0) is
when "00" => va.hrdata(31 downto 0) := rdata(63 downto 32);
when "01" => va.hrdata(31 downto 0) := rdata(31 downto 0);
when "10" => va.hrdata(31 downto 0) := rdata(127 downto 96);
when others => va.hrdata(31 downto 0) := rdata(95 downto 64);
end case;
va.hrdata(127 downto 32) := va.hrdata(31 downto 0) &
va.hrdata(31 downto 0) &
va.hrdata(31 downto 0);
end if;
if nosync = 0 then
va.sync := r.startsd;
if ra.startsd = ra.sync then ready := '1';
else ready := '0'; end if;
else
if ra.startsd = r.startsd then ready := '1';
else ready := '0'; end if;
end if;
if ((ahbsi.hready and ahbsi.hsel(hindex)) = '1') then
va.htrans := ahbsi.htrans; va.haddr := ahbsi.haddr;
va.size := ahbsi.hsize(2 downto 0); va.hwrite := ahbsi.hwrite;
if ahbsi.htrans(1) = '1' then
va.hsel := '1'; va.hready := '0';
end if;
end if;
if ahbsi.hready = '1' then va.hsel := ahbsi.hsel(hindex); end if;
case ra.state is
when midle =>
va.write := (others => "0000");
if ((va.hsel and va.htrans(1)) = '1') then
if va.hwrite = '0' then
va.state := rhold; va.startsd := not ra.startsd;
else
va.state := dwrite; va.hready := '1';
end if;
end if;
va.raddr := ra.haddr(7 downto 2);
if ((ahbsi.hready and ahbsi.hsel(hindex)) = '1') then
va.acc := (va.haddr, va.size, va.hwrite);
end if;
when rhold =>
va.raddr := ra.haddr(7 downto 2);
if ready = '1' then
va.state := dread; va.hready := '1';
if AHBDW > 64 and ra.size(2) = '1' then va.raddr := ra.raddr + 4;
elsif AHBDW > 32 and andv(ra.size(1 downto 0)) = '1' then va.raddr := ra.raddr + 2;
else va.raddr := ra.raddr + 1; end if;
end if;
when dread =>
va.hready := '1';
if AHBDW > 64 and ra.size(2) = '1' then va.raddr := ra.raddr + 4;
elsif AHBDW > 32 and andv(ra.size(1 downto 0)) = '1' then va.raddr := ra.raddr + 2;
else va.raddr := ra.raddr + 1; end if;
if ((va.hsel and va.htrans(1) and va.htrans(0)) = '0')
or (ra.raddr(2 downto 0) = "000") then
va.state := midle; va.hready := '0';
end if;
va.acc := (va.haddr, va.size, va.hwrite);
when dwrite =>
va.raddr := ra.haddr(7 downto 2); va.hready := '1';
if (((va.hsel and va.htrans(1) and va.htrans(0)) = '0')
or (ra.haddr(4 downto 2) = "111")
or (AHBDW > 32 and ra.haddr(5 downto 2) = "1110" and andv(ra.size(1 downto 0)) = '1')
or (AHBDW > 64 and ra.haddr(5 downto 2) = "1100" and ra.size(2) = '1')) then
va.startsd := not ra.startsd; va.state := whold1;
va.hready := '0';
end if;
tmp := decode(ra.haddr(1 downto 0));
waddr := conv_integer(ra.haddr(4 downto 2));
va.hwdata(waddr) := hwdata(31 downto 0);
case ra.size is
when "000" => va.write(waddr) := tmp(0) & tmp(1) & tmp(2) & tmp(3);
when "001" => va.write(waddr) := tmp(0) & tmp(0) & tmp(2) & tmp(2);
when "010" => va.write(waddr) := "1111";
when "011" => va.write(waddr) := "1111"; va.write(waddr+1) := "1111";
va.hwdata(waddr+1) := hwdata((63 mod AHBDW) downto (32 mod AHBDW));
when others => va.write(waddr) := "1111"; va.write(waddr+1) := "1111";
va.write(waddr+2) := "1111"; va.write(waddr+3) := "1111";
va.hwdata(waddr+1) := hwdata((63 mod AHBDW) downto (32 mod AHBDW));
va.hwdata(waddr+2) := hwdata((95 mod AHBDW) downto (64 mod AHBDW));
va.hwdata(waddr+3) := hwdata((127 mod AHBDW) downto (96 mod AHBDW));
end case;
when whold1 =>
va.state := whold2;
when whold2 =>
if ready = '1' then
va.state := midle; va.acc := (va.haddr, va.size, va.hwrite);
end if;
end case;
if (ahbsi.hready and ahbsi.hsel(hindex) ) = '1' then
if ahbsi.htrans(1) = '0' then va.hready := '1'; end if;
end if;
if rst_ahb = '0' then
va.hsel := '0';
va.hready := '1';
va.state := midle;
va.startsd := '0';
va.acc.hwrite := '0';
va.acc.haddr := (others => '0');
end if;
rai <= va;
end process;
ahbso.hready <= ra.hready;
ahbso.hresp <= ra.hresp;
ahbso.hrdata <= ahbdrivedata(ra.hrdata);
-- migi.app_addr <= '0' & ra.acc.haddr(28 downto 6) & "000";
migi.app_addr <= "00000" & ra.acc.haddr(28 downto 5) & "00";
ddr_ctrl : process(rst_ddr, r, ra, migo)
variable v : ddr_reg_type; -- local variables for registers
variable startsd : std_ulogic;
variable raddr : std_logic_vector(13 downto 0);
variable adec : std_ulogic;
variable haddr : std_logic_vector(31 downto 0);
variable hsize : std_logic_vector(1 downto 0);
variable hwrite : std_ulogic;
variable htrans : std_logic_vector(1 downto 0);
variable hready : std_ulogic;
variable app_en : std_ulogic;
variable app_cmd : std_logic_vector(2 downto 0);
variable app_wdf_mask : std_logic_vector(APPDATA_WIDTH/8-1 downto 0);
variable app_wdf_wren : std_ulogic;
variable app_wdf_data : std_logic_vector(APPDATA_WIDTH-1 downto 0);
begin
-- Variable default settings to avoid latches
v := r; app_en := '0'; app_cmd := "000"; app_wdf_wren := '0';
app_wdf_mask := (others => '0');
app_wdf_mask(15 downto 0) := ra.write(2) & ra.write(3) & ra.write(0) & ra.write(1);
app_wdf_data := (others => '0');
app_wdf_data(127 downto 0) := ra.hwdata(2) & ra.hwdata(3) & ra.hwdata(0) & ra.hwdata(1);
if ra.acc.hwrite = '0' then app_cmd(0) := '1'; else app_cmd(0) := '0'; end if;
v.sync := ra.startsd;
if nosync = 0 then
if r.startsd /= r.sync then startsd := '1';
else startsd := '0'; end if;
else
if ra.startsd /= r.startsd then startsd := '1';
else startsd := '0'; end if;
end if;
case r.dstate is
when midle =>
if (startsd = '1') and (migo.app_af_afull = '0') then
if ra.acc.hwrite = '0' then
v.dstate := dread; app_en := '1';
elsif migo.app_wdf_afull = '0' then
v.dstate := dwrite; app_en := '1'; app_wdf_wren := '1';
end if;
end if;
when dread =>
if migo.app_rd_data_valid = '1' then
v.hrdata(127 downto 0) := migo.app_rd_data(127 downto 0);
v.dstate := rhold;
end if;
when rhold =>
v.hrdata(255 downto 128) := migo.app_rd_data(127 downto 0);
v.dstate := midle;
v.startsd := not r.startsd;
when dwrite =>
app_wdf_wren := '1';
app_wdf_mask(15 downto 0) := ra.write(6) & ra.write(7) & ra.write(4) & ra.write(5);
app_wdf_data(127 downto 0) := ra.hwdata(6) & ra.hwdata(7) & ra.hwdata(4) & ra.hwdata(5);
v.startsd := not r.startsd;
v.dstate := midle;
when others =>
end case;
-- reset
if rst_ddr = '0' then
v.startsd := '0';
app_en := '0';
v.dstate := midle;
end if;
ri <= v;
migi.app_cmd <= app_cmd;
migi.app_en <= app_en;
migi.app_wdf_wren <= app_wdf_wren;
migi.app_wdf_mask <= not app_wdf_mask;
migi.app_wdf_data <= app_wdf_data;
end process;
ahbso.hconfig <= hconfig;
ahbso.hirq <= (others => '0');
ahbso.hindex <= hindex;
ahbso.hsplit <= (others => '0');
clk_ahb1 <= clk_ahb; clk_ahb2 <= clk_ahb1; -- sync clock deltas
ahbregs : process(clk_ahb2) begin
if rising_edge(clk_ahb2) then
ra <= rai;
end if;
end process;
ddrregs : process(clk_ddr) begin
if rising_edge(clk_ddr) then
r <= ri;
end if;
end process;
-- Write data selection.
AHB32: if AHBDW = 32 generate
hwdata <= ahbsi.hwdata(31 downto 0) & ahbsi.hwdata(31 downto 0) &
ahbsi.hwdata(31 downto 0) & ahbsi.hwdata(31 downto 0);
end generate AHB32;
AHB64: if AHBDW = 64 generate
-- With CORE_ACDM set to 0 hwdata will always be ahbsi.hwdata(63 downto 0)
-- otherwise the valid data slice will be selected, and possibly uplicated,
-- from ahbsi.hwdata.
hwdatab(63 downto 0) <= ahbreaddword(ahbsi.hwdata, ra.haddr(4 downto 2)) when (CORE_ACDM = 0 or ra.size(1 downto 0) = "11") else
(ahbreadword(ahbsi.hwdata, ra.haddr(4 downto 2)) &
ahbreadword(ahbsi.hwdata, ra.haddr(4 downto 2)));
hwdata <= hwdatab(31 downto 0) & hwdatab(63 downto 32) &
hwdatab(31 downto 0) & hwdatab(63 downto 32);
end generate AHB64;
AHBWIDE: if AHBDW > 64 generate
-- With CORE_ACDM set to 0 hwdata will always be ahbsi.hwdata(127 downto 0)
-- otherwise the valid data slice will be selected, and possibly uplicated,
-- from ahbsi.hwdata.
hwdatab <= ahbread4word(ahbsi.hwdata, ra.haddr(4 downto 2)) when (CORE_ACDM = 0 or ra.size(2) = '1') else
(ahbreaddword(ahbsi.hwdata, ra.haddr(4 downto 2)) &
ahbreaddword(ahbsi.hwdata, ra.haddr(4 downto 2))) when (ra.size = "011") else
(ahbreadword(ahbsi.hwdata, ra.haddr(4 downto 2)) &
ahbreadword(ahbsi.hwdata, ra.haddr(4 downto 2)) &
ahbreadword(ahbsi.hwdata, ra.haddr(4 downto 2)) &
ahbreadword(ahbsi.hwdata, ra.haddr(4 downto 2)));
hwdata <= hwdatab(31 downto 0) & hwdatab(63 downto 32) &
hwdatab(95 downto 64) & hwdatab(127 downto 96);
end generate AHBWIDE;
-- pragma translate_off
bootmsg : report_version
generic map (
msg1 => "ahb2mig" & tost(hindex) & ": 64-bit DDR2/3 controller rev " &
tost(REVISION) & ", " & tost(Mbyte) & " Mbyte, " & tost(MHz) &
" MHz DDR clock");
-- pragma translate_on
end;
| gpl-3.0 | 5747e7036d24eed9244a6bd2d733f1f3 | 0.524917 | 3.594778 | false | false | false | false |
hoglet67/CoPro6502 | src/DCM/dcm_32_72.vhd | 1 | 2,183 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library UNISIM;
use UNISIM.Vcomponents.all;
entity dcm_32_72 is
port (CLKIN_IN : in std_logic;
CLK0_OUT : out std_logic;
CLK0_OUT1 : out std_logic;
CLK2X_OUT : out std_logic);
end dcm_32_72;
architecture BEHAVIORAL of dcm_32_72 is
signal CLKFX_BUF : std_logic;
signal CLK2X_BUF : std_logic;
signal CLKIN_IBUFG : std_logic;
signal GND_BIT : std_logic;
begin
GND_BIT <= '0';
CLKFX_BUFG_INST : BUFG
port map (I => CLKFX_BUF, O => CLK0_OUT);
CLK2X_BUFG_INST : BUFG
port map (I => CLK2X_BUF, O => CLK2X_OUT);
DCM_INST : DCM
generic map(CLK_FEEDBACK => "NONE",
CLKDV_DIVIDE => 4.0, -- 72.00 = 32.000 * 9/4
CLKFX_MULTIPLY => 9,
CLKFX_DIVIDE => 4,
CLKIN_DIVIDE_BY_2 => false,
CLKIN_PERIOD => 31.25,
CLKOUT_PHASE_SHIFT => "NONE",
DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS",
DFS_FREQUENCY_MODE => "LOW",
DLL_FREQUENCY_MODE => "LOW",
DUTY_CYCLE_CORRECTION => true,
FACTORY_JF => x"C080",
PHASE_SHIFT => 0,
STARTUP_WAIT => false)
port map (CLKFB => GND_BIT,
CLKIN => CLKIN_IN,
DSSEN => GND_BIT,
PSCLK => GND_BIT,
PSEN => GND_BIT,
PSINCDEC => GND_BIT,
RST => GND_BIT,
CLKDV => open,
CLKFX => CLKFX_BUF,
CLKFX180 => open,
CLK0 => open,
CLK2X => CLK2X_BUF,
CLK2X180 => open,
CLK90 => open,
CLK180 => open,
CLK270 => open,
LOCKED => open,
PSDONE => open,
STATUS => open);
end BEHAVIORAL;
| gpl-3.0 | 89d3d37746b23fa6625e5368bd0cdd33 | 0.412735 | 4.080374 | false | false | false | false |
EliasLuiz/TCC | Leon3/lib/grlib/amba/apbctrl.vhd | 1 | 3,370 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: apbctrl
-- File: apbctrl.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: AMBA AHB/APB bridge with plug&play support
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.config_types.all;
use grlib.config.all;
use grlib.amba.all;
use grlib.stdlib.all;
entity apbctrl is
generic (
hindex : integer := 0;
haddr : integer := 0;
hmask : integer := 16#fff#;
nslaves : integer range 1 to NAPBSLV := NAPBSLV;
debug : integer range 0 to 2 := 2;
icheck : integer range 0 to 1 := 1;
enbusmon : integer range 0 to 1 := 0;
asserterr : integer range 0 to 1 := 0;
assertwarn : integer range 0 to 1 := 0;
pslvdisable : integer := 0;
mcheck : integer range 0 to 1 := 1;
ccheck : integer range 0 to 1 := 1
);
port (
rst : in std_ulogic;
clk : in std_ulogic;
ahbi : in ahb_slv_in_type;
ahbo : out ahb_slv_out_type;
apbi : out apb_slv_in_type;
apbo : in apb_slv_out_vector
);
end;
architecture struct of apbctrl is
signal lahbi : ahb_slv_in_vector_type(0 to 0);
signal lahbo : ahb_slv_out_vector_type(0 to 0);
signal lapbi : apb_slv_in_vector;
signal lwp : std_logic_vector(0 to 0);
signal lwpv : std_logic_vector(256-1 downto 0);
begin
lahbi(0) <= ahbi;
ahbo <= lahbo(0);
apbi <= lapbi(0);
lwp(0) <= '0';
lwpv <= (others => '0');
apbx : apbctrlx
generic map(
hindex0 => hindex,
haddr0 => haddr,
hmask0 => hmask,
hindex1 => 0,
haddr1 => 0,
hmask1 => 0,
nslaves => nslaves,
nports => 1,
wprot => 0,
debug => debug,
icheck => icheck,
enbusmon => enbusmon,
asserterr => asserterr,
assertwarn => assertwarn,
pslvdisable => pslvdisable,
mcheck => mcheck,
ccheck => ccheck)
port map(
rst => rst,
clk => clk,
ahbi => lahbi,
ahbo => lahbo,
apbi => lapbi,
apbo => apbo,
wp => lwp,
wpv => lwpv);
end;
| gpl-3.0 | f9dc5e980741c536fa03e93b6d656f7b | 0.542433 | 3.860252 | false | false | false | false |
EliasLuiz/TCC | Leon3/lib/gaisler/greth/adapters/rgmii.vhd | 1 | 33,798 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: rgmii
-- File: rgmii.vhd
-- Author: Fredrik Ringhage - Aeroflex Gaisler
-- Description: GMII to RGMII interface
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library gaisler;
use gaisler.net.all;
use gaisler.misc.all;
library grlib;
use grlib.config_types.all;
use grlib.config.all;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
library techmap;
use techmap.gencomp.all;
use techmap.allclkgen.all;
library eth;
use eth.grethpkg.all;
entity rgmii is
generic (
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#fff#;
tech : integer := 0;
gmii : integer := 0;
debugmem : integer := 0;
abits : integer := 8;
no_clk_mux : integer := 0;
pirq : integer := 0;
use90degtxclk : integer := 0;
mode100 : integer := 0
);
port (
rstn : in std_ulogic;
gmiii : out eth_in_type;
gmiio : in eth_out_type;
rgmiii : in eth_in_type;
rgmiio : out eth_out_type;
-- APB Status bus
apb_clk : in std_logic;
apb_rstn : in std_logic;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type
);
end ;
architecture rtl of rgmii is
constant REVISION : integer := 1;
constant pconfig : apb_config_type := (
0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_RGMII, 0, REVISION, pirq),
1 => apb_iobar(paddr, pmask));
type status_vector_type is array(1 downto 0) of std_logic_vector(15 downto 0);
type rgmiiregs is record
clk25_wrap : unsigned(5 downto 0);
clk25_first_edge : unsigned(5 downto 0);
clk25_second_edge : unsigned(5 downto 0);
clk2_5_wrap : unsigned(5 downto 0);
clk2_5_first_edge : unsigned(5 downto 0);
clk2_5_second_edge : unsigned(5 downto 0);
irq : std_logic_vector(15 downto 0); -- interrupt
mask : std_logic_vector(15 downto 0); -- interrupt enable
clkedge : std_logic_vector(23 downto 0);
rxctrl_q1_delay : std_logic_vector(1 downto 0);
rxctrl_q2_delay : std_logic_vector(1 downto 0);
rxctrl_q1_sel : std_logic;
rxctrl_delay : std_logic;
rxctrl_c_delay : std_logic;
status_vector : status_vector_type;
end record;
-- Global signal
signal vcc, gnd : std_ulogic;
signal tx_en, tx_ctl : std_ulogic;
signal txd : std_logic_vector(7 downto 0);
signal rxd, rxd_pre, rxd_int, rxd_int0, rxd_int1, rxd_int2,rxd_q1,rxd_q2 : std_logic_vector(7 downto 0);
signal rx_clk, nrx_clk : std_ulogic;
signal rx_dv, rx_dv_pre, rx_dv_int, rx_dv0 , rx_ctl, rx_ctl_pre, rx_ctl_int, rx_ctl0, rx_error : std_logic;
signal rx_dv_int0, rx_dv_int1, rx_dv_int2 : std_logic;
signal rx_ctl_int0, rx_ctl_int1, rx_ctl_int2 : std_logic;
signal clk50i, clk50d, clk25i, clk25ni, clk2_5i, clk2_5ni : std_ulogic;
signal txp, txn, txp_sync, txn_sync, tx_clk_ddr, tx_clk, tx_clki, ntx_clk : std_ulogic;
signal cnt2_5, cnt25 : unsigned(5 downto 0);
signal rsttxclkn,rsttxclk,rsttxclk90n,rsttxclk90 : std_logic;
-- RGMII Inband status signals
signal inbandopt,inbandreq : std_logic;
signal link_status : std_logic;
signal clock_speed : std_logic_vector(1 downto 0);
signal duplex_status : std_logic;
signal false_carrier_ind : std_logic;
signal carrier_ext : std_logic;
signal carrier_ext_error : std_logic;
signal carrier_sense : std_logic;
-- Status signals and Clock domain crossing
signal line_status_vector : std_logic_vector(3 downto 0);
signal status_vector : std_logic_vector(15 downto 0);
signal status_vector_sync : std_logic_vector(15 downto 0);
-- APB and RGMII control register
constant RESET_ALL : boolean := GRLIB_CONFIG_ARRAY(grlib_sync_reset_enable_all) = 1;
-- notech default settings
constant RES : rgmiiregs :=
( clk25_wrap => to_unsigned(4,6), clk25_first_edge => to_unsigned(1,6), clk25_second_edge => to_unsigned(2,6),
clk2_5_wrap => to_unsigned(49,6), clk2_5_first_edge => to_unsigned(23,6), clk2_5_second_edge => to_unsigned(24,6),
irq => (others => '0'), mask => (others => '0'), clkedge => "000000100011100000111000",
rxctrl_q1_delay => (others => '0'), rxctrl_q2_delay => (others => '0'), rxctrl_q1_sel => '0', rxctrl_delay => '0',
rxctrl_c_delay => '0', status_vector => (others => (others => '0')) );
-- Kintex7 settings for KC705 Dev Board
constant RES_kintex7 : rgmiiregs :=
( clk25_wrap => to_unsigned(4,6), clk25_first_edge => to_unsigned(1,6), clk25_second_edge => to_unsigned(2,6),
clk2_5_wrap => to_unsigned(49,6), clk2_5_first_edge => to_unsigned(23,6), clk2_5_second_edge => to_unsigned(24,6),
irq => (others => '0'), mask => (others => '0'), clkedge => "000000100011100000111000",
rxctrl_q1_delay => (others => '0'), rxctrl_q2_delay => (others => '0'), rxctrl_q1_sel => '1', rxctrl_delay => '0',
rxctrl_c_delay => '0', status_vector => (others => (others => '0')) );
-- Spartan6 settings for GR-XC6 Dev Board
constant RES_spartan6 : rgmiiregs :=
( clk25_wrap => to_unsigned(4,6), clk25_first_edge => to_unsigned(1,6), clk25_second_edge => to_unsigned(2,6),
clk2_5_wrap => to_unsigned(49,6), clk2_5_first_edge => to_unsigned(23,6), clk2_5_second_edge => to_unsigned(24,6),
irq => (others => '0'), mask => (others => '0'), clkedge => "000000100011100000111000",
rxctrl_q1_delay => (others => '0'), rxctrl_q2_delay => "01", rxctrl_q1_sel => '1', rxctrl_delay => '0',
rxctrl_c_delay => '0', status_vector => (others => (others => '0')) );
-- Artix7 settings for AC701 Dev Board
constant RES_artix7 : rgmiiregs :=
( clk25_wrap => to_unsigned(4,6), clk25_first_edge => to_unsigned(1,6), clk25_second_edge => to_unsigned(2,6),
clk2_5_wrap => to_unsigned(49,6), clk2_5_first_edge => to_unsigned(23,6), clk2_5_second_edge => to_unsigned(24,6),
irq => (others => '0'), mask => (others => '0'), clkedge => "000000100011100000111000",
rxctrl_q1_delay => (others => '0'), rxctrl_q2_delay => (others => '0'), rxctrl_q1_sel => '1', rxctrl_delay => '0',
rxctrl_c_delay => '1', status_vector => (others => (others => '0')) );
signal r, rin : rgmiiregs;
signal clk_tx_90_n : std_logic;
signal sync_gbit : std_logic;
signal sync_speed : std_logic;
signal cnt2_5_en, cnt25_en : std_logic;
signal clkedge_sync : std_logic_vector(23 downto 0);
signal sync_rxctrl_q1_delay : std_logic_vector(1 downto 0);
signal sync_rxctrl_q2_delay : std_logic_vector(1 downto 0);
signal sync_rxctrl_q1_sel : std_logic;
signal sync_rxctrl_delay : std_logic;
signal sync_rxctrl_c_delay : std_logic;
signal cnt_en : std_logic;
signal clk10_100 : std_logic;
signal clk25_wrap_sync : unsigned(5 downto 0);
signal clk25_first_edge_sync : unsigned(5 downto 0);
signal clk25_second_edge_sync : unsigned(5 downto 0);
signal clk2_5_wrap_sync : unsigned(5 downto 0);
signal clk2_5_first_edge_sync : unsigned(5 downto 0);
signal clk2_5_second_edge_sync : unsigned(5 downto 0);
-- debug signal
signal WMemRgmiioData : std_logic_vector(15 downto 0);
signal RMemRgmiioData : std_logic_vector(15 downto 0);
signal RMemRgmiioAddr : std_logic_vector(9 downto 0);
signal WMemRgmiioAddr : std_logic_vector(9 downto 0);
signal WMemRgmiioWrEn : std_logic;
signal WMemRgmiiiData : std_logic_vector(15 downto 0);
signal RMemRgmiiiData : std_logic_vector(15 downto 0);
signal RMemRgmiiiAddr : std_logic_vector(9 downto 0);
signal WMemRgmiiiAddr : std_logic_vector(9 downto 0);
signal WMemRgmiiiWrEn : std_logic;
signal RMemRgmiiiRead : std_logic;
signal RMemRgmiioRead : std_logic;
signal clk25i_del : std_logic;
signal clk2_5i_del : std_logic;
signal clk10_100_del : std_logic;
signal tx_clki_del : std_logic;
signal tx_clk_del : std_logic;
signal ntx_clk_del : std_logic;
begin -- rtl
vcc <= '1'; gnd <= '0';
---------------------------------------------------------------------------------------
-- MDIO path
---------------------------------------------------------------------------------------
gmiii.mdint <= rgmiii.mdint;
gmiii.mdio_i <= rgmiii.mdio_i;
rgmiio.mdio_o <= gmiio.mdio_o;
rgmiio.mdio_oe <= gmiio.mdio_oe;
rgmiio.mdc <= gmiio.mdc;
---------------------------------------------------------------------------------------
-- TX path
---------------------------------------------------------------------------------------
useclkmux0 : if no_clk_mux = 0 generate
usemode100 : if mode100 = 1 generate
process (apb_clk)
begin -- process
if rising_edge(apb_clk) then
clk50i <= not clk50i;
if apb_rstn = '0' then clk50i <= '0'; end if;
end if;
end process;
process (apb_clk)
begin -- process
if rising_edge(apb_clk) then
clk50d <= clk50i;
if (clk50d = '1' and clk50i = '0') then
clk25i_del <= not clk25i_del;
end if;
if (clk50d = '0' and clk50i = '1') then
clk25i <= not clk25i;
if cnt2_5 = "001001" then
cnt2_5 <= "000000"; clk2_5i_del <= not clk2_5i_del;
else
cnt2_5 <= cnt2_5 + 1;
end if;
if cnt2_5 = "000111" then
clk2_5i <= not clk2_5i;
end if;
end if;
if apb_rstn = '0' then clk50d <= '0'; clk25i <= '0'; clk2_5i <= '0'; cnt2_5 <= "000000"; clk25i_del <= '0'; clk2_5i_del <= '0'; end if;
end if;
end process;
end generate;
usemodeAPB : if mode100 = 0 generate
process (apb_clk)
begin -- process
if rising_edge(apb_clk) then
clk25i <= not clk25i;
if cnt2_5 = "001001" then cnt2_5 <= "000000"; clk2_5i <= not clk2_5i;
else cnt2_5 <= cnt2_5 + 1; end if;
if apb_rstn = '0' then clk25i <= '0'; clk2_5i <= '0'; cnt2_5 <= "000000"; end if;
end if;
end process;
end generate;
notecclkmux : if (has_clkmux(tech) = 0) generate
tx_clki <= rgmiii.gtx_clk when ((gmii = 1) and (gmiio.gbit = '1')) else
clk25i when gmiio.speed = '1' else clk2_5i;
end generate;
tecclkmux : if (has_clkmux(tech) = 1) generate
-- Select 2.5 or 25 Mhz clockL
clkmux10_100 : clkmux generic map (tech => tech) port map (clk2_5i,clk25i,gmiio.speed,clk10_100);
clkmux1000 : clkmux generic map (tech => tech) port map (clk10_100,rgmiii.gtx_clk,gmiio.gbit,tx_clki);
clkmux10_100d : clkmux generic map (tech => tech) port map (clk2_5i_del,clk25i_del,gmiio.speed,clk10_100_del);
clkmux1000d : clkmux generic map (tech => tech) port map (clk10_100_del,rgmiii.gtx_clk,gmiio.gbit,tx_clki_del);
end generate;
clkbuf0: techbuf generic map (buftype => 2, tech => tech)
port map (i => tx_clki, o => tx_clk);
clkbuf01: techbuf generic map (buftype => 2, tech => tech)
port map (i => tx_clki_del, o => tx_clk_del);
end generate;
noclkmux0 : if no_clk_mux = 1 generate
-- Generate transmit clocks.
tx_clk <= rgmiii.gtx_clk;
-- CDC
syncreg7 : syncreg port map (tx_clk, gmiio.gbit , sync_gbit );
syncreg8 : syncreg port map (tx_clk, gmiio.speed, sync_speed );
syncreg_clkedge : for i in 0 to r.clkedge'length-1 generate
syncreg9 : syncreg port map (tx_clk, r.clkedge(i), clkedge_sync(i));
end generate;
syncreg_clk25_wrap_sync : for i in 0 to r.clk25_wrap'length-1 generate
syncreg_clk25_wrap_sync : syncreg port map (tx_clk, r.clk25_wrap(i), clk25_wrap_sync(i));
end generate;
syncreg_clk25_first_edge : for i in 0 to r.clk25_first_edge'length-1 generate
syncreg_clk25_first_edge : syncreg port map (tx_clk, r.clk25_first_edge(i), clk25_first_edge_sync(i));
end generate;
syncreg_clk25_second_edge : for i in 0 to r.clk25_second_edge'length-1 generate
syncreg_clk25_second_edge : syncreg port map (tx_clk, r.clk25_second_edge(i), clk25_second_edge_sync(i));
end generate;
syncreg_clk2_5_wrap_sync : for i in 0 to r.clk2_5_wrap'length-1 generate
syncreg_clk2_5_wrap_sync : syncreg port map (tx_clk, r.clk2_5_wrap(i), clk2_5_wrap_sync(i));
end generate;
syncreg_clk2_5_first_edge : for i in 0 to r.clk2_5_first_edge'length-1 generate
syncreg_clk2_5_first_edge : syncreg port map (tx_clk, r.clk2_5_first_edge(i), clk2_5_first_edge_sync(i));
end generate;
syncreg_clk2_5_second_edge : for i in 0 to r.clk2_5_second_edge'length-1 generate
syncreg_clk2_5_second_edge : syncreg port map (tx_clk, r.clk2_5_second_edge(i), clk2_5_second_edge_sync(i));
end generate;
process (tx_clk)
begin -- process
if rising_edge(tx_clk) then
if cnt25 >= clk25_wrap_sync then
cnt25 <= to_unsigned(0,cnt25'length);
cnt25_en <= '1';
else
cnt25_en <= '0';
cnt25 <= cnt25 + 1;
end if;
if (cnt25 >= clk25_wrap_sync) then
clk25ni <= clkedge_sync(0);
clk25i <= clkedge_sync(1);
elsif (cnt25 = clk25_first_edge_sync) then
clk25ni <= clkedge_sync(2);
clk25i <= clkedge_sync(3);
elsif (cnt25 = clk25_second_edge_sync) then
clk25ni <= clkedge_sync(4);
clk25i <= clkedge_sync(5);
end if;
if cnt2_5 >= clk2_5_wrap_sync then
cnt2_5 <= to_unsigned(0,cnt2_5'length);
cnt2_5_en <= '1';
else
cnt2_5 <= cnt2_5 + 1;
cnt2_5_en <= '0';
end if;
if (cnt2_5 >= clk2_5_wrap_sync) then
clk2_5ni <= clkedge_sync(8);
clk2_5i <= clkedge_sync(9);
elsif (cnt25 = clk2_5_first_edge_sync) then
clk2_5ni <= clkedge_sync(10);
clk2_5i <= clkedge_sync(11);
elsif (cnt2_5 = clk2_5_second_edge_sync) then
clk2_5ni <= clkedge_sync(12);
clk2_5i <= clkedge_sync(13);
end if;
if rsttxclkn = '0' then
cnt2_5_en <= '0'; cnt25_en <= '0'; clk25i <= '0'; clk25ni <= '0';
clk2_5i <= '0'; clk2_5ni <= '0'; cnt2_5 <= to_unsigned(0,cnt2_5'length);
cnt25 <= to_unsigned(0,cnt25'length);
end if;
end if;
end process;
end generate;
ntx_clk <= not tx_clk;
ntx_clk_del <= not tx_clk_del;
gmiii.gtx_clk <= tx_clk;
gmiii.tx_clk <= tx_clk;
noclkmux1 : if no_clk_mux = 1 generate
cnt_en <= '1' when ((gmii = 1) and (sync_gbit = '1')) else
cnt25_en when sync_speed = '1' else cnt2_5_en;
end generate;
useclkmux1 : if no_clk_mux = 0 generate
cnt_en <= '1';
end generate;
gmiii.tx_dv <= cnt_en when gmiio.tx_en = '1' else '1';
-- Generate RGMII control signal and check data rate
process (tx_clk)
begin -- process
if rising_edge(tx_clk) then
if (gmii = 1) and (sync_gbit = '1') then
txd(7 downto 0) <= gmiio.txd(7 downto 0);
else
txd(3 downto 0) <= gmiio.txd(3 downto 0);
txd(7 downto 4) <= gmiio.txd(3 downto 0);
end if;
tx_en <= gmiio.tx_en;
tx_ctl <= gmiio.tx_en xor gmiio.tx_er;
end if;
if (gmii = 1) and (sync_gbit = '1') then
txp <= clkedge_sync(17);
txn <= clkedge_sync(16);
else
if sync_speed = '1' then
txp <= clk25ni;
txn <= clk25i;
else
txp <= clk2_5ni;
txn <= clk2_5i;
end if;
end if;
end process;
clk_tx_rst : rstgen
generic map(syncin => 1, syncrst => 1)
port map(rstn, tx_clk, vcc, rsttxclkn, open);
rsttxclk <= not rsttxclkn;
-- DDR outputs
rgmii_txd : for i in 0 to 3 generate
ddr_oreg0 : ddr_oreg generic map (tech, arch => 1)
port map (q => rgmiio.txd(i), c1 => tx_clk, c2 => ntx_clk, ce => vcc,
d1 => txd(i), d2 => txd(i+4), r => rsttxclk, s => gnd);
end generate;
rgmii_tx_ctl : ddr_oreg generic map (tech, arch => 1)
port map (q => rgmiio.tx_en, c1 => tx_clk, c2 => ntx_clk, ce => vcc,
d1 => tx_en, d2 => tx_ctl, r => rsttxclk, s => gnd);
no_clk_mux1 : if no_clk_mux = 1 generate
use90degtxclk1 : if use90degtxclk = 1 generate
clk_tx90_rst : rstgen
generic map(syncin => 1, syncrst => 1)
port map(rstn, rgmiii.tx_clk_90, vcc, rsttxclk90n, open);
rsttxclk90 <= not rsttxclk90n;
clk_tx_90_n <= not rgmiii.tx_clk_90;
syncreg_txp : syncreg port map (rgmiii.tx_clk_90, txp, txp_sync);
syncreg_txn : syncreg port map (rgmiii.tx_clk_90, txn, txn_sync);
rgmii_tx_clk : ddr_oreg generic map (tech, arch => 1)
port map (q => tx_clk_ddr, c1 => rgmiii.tx_clk_90, c2 => clk_tx_90_n, ce => vcc,
d1 => txp_sync, d2 => txn_sync, r => rsttxclk90, s => gnd);
end generate;
use90degtxclk0 : if use90degtxclk = 0 generate
rgmii_tx_clk : ddr_oreg generic map (tech, arch => 1)
port map (q => tx_clk_ddr, c1 => tx_clk, c2 => ntx_clk, ce => vcc,
d1 => txp, d2 => txn, r => rsttxclk, s => gnd);
end generate;
end generate;
no_clk_mux0 : if no_clk_mux = 0 generate
use90degtxclk00 : if mode100 = 1 generate
rgmii_tx_clk : ddr_oreg generic map (tech, arch => 1)
port map (q => tx_clk_ddr, c1 => tx_clk_del, c2 => ntx_clk_del, ce => vcc,
d1 => '1', d2 => '0', r => rsttxclk, s => gnd);
end generate;
use90degtxclk01 : if mode100 = 0 generate
rgmii_tx_clk : ddr_oreg generic map (tech, arch => 1)
port map (q => tx_clk_ddr, c1 => tx_clk, c2 => ntx_clk, ce => vcc,
d1 => '1', d2 => '0', r => rsttxclk, s => gnd);
end generate;
end generate;
rgmiio.tx_er <= '0';
rgmiio.tx_clk <= tx_clk_ddr;
rgmiio.reset <= rstn;
rgmiio.gbit <= gmiio.gbit;
rgmiio.speed <= gmiio.speed when (gmii = 1) else '0';
-- Not used in RGMII mode
rgmiio.txd(7 downto 4) <= (others => '0');
---------------------------------------------------------------------------------------
-- RX path
---------------------------------------------------------------------------------------
-- CDC (RX Control signal)
syncreg_q1_delay : for i in 0 to r.rxctrl_q1_delay'length-1 generate
syncreg0 : syncreg port map (rx_clk, r.rxctrl_q1_delay(i), sync_rxctrl_q1_delay(i));
end generate;
syncreg_q2_delay : for i in 0 to r.rxctrl_q2_delay'length-1 generate
syncreg1 : syncreg port map (rx_clk, r.rxctrl_q2_delay(i) , sync_rxctrl_q2_delay(i));
end generate;
syncreg_q1_sel : syncreg port map (rx_clk, r.rxctrl_q1_sel, sync_rxctrl_q1_sel);
syncreg_delay_sel : syncreg port map (rx_clk, r.rxctrl_delay, sync_rxctrl_delay);
syncreg_delay_c_sel : syncreg port map (rx_clk, r.rxctrl_c_delay, sync_rxctrl_c_delay);
-- Rx Clocks
rx_clk <= rgmiii.rx_clk;
nrx_clk <= not rgmiii.rx_clk;
-- DDR inputs
rgmii_rxd : for i in 0 to 3 generate
ddr_ireg0 : ddr_ireg generic map (tech, arch => 1)
port map (q1 => rxd_pre(i), q2 => rxd_pre(i+4), c1 => rx_clk, c2 => nrx_clk,
ce => vcc, d => rgmiii.rxd(i), r => gnd, s => gnd);
process (rx_clk)
begin
if rising_edge(rx_clk) then
rxd_int <= rxd_pre;
rxd_int0(i) <= rxd_int(i);
rxd_int0(i+4) <= rxd_int(i+4);
rxd_int1(i) <= rxd_int0(i);
rxd_int1(i+4) <= rxd_int0(i+4);
rxd_int2(i) <= rxd_int1(i);
rxd_int2(i+4) <= rxd_int1(i+4);
end if;
end process;
end generate;
rgmii_rxd0 : for i in 0 to 3 generate
process (rx_clk)
begin
if (sync_rxctrl_q1_delay = "00") then
if (sync_rxctrl_delay = '1') then
rxd_q1(i) <= rxd_int(i+4);
else
rxd_q1(i) <= rxd_int(i);
end if;
elsif (sync_rxctrl_q1_delay = "01") then
rxd_q1(i) <= rxd_int0(i);
elsif (sync_rxctrl_q1_delay = "10") then
rxd_q1(i) <= rxd_int1(i);
else
rxd_q1(i) <= rxd_int2(i);
end if;
end process;
end generate;
rgmii_rxd1 : for i in 4 to 7 generate
process (rx_clk)
begin
if (sync_rxctrl_q2_delay = "00") then
if (sync_rxctrl_delay = '1') then
rxd_q2(i) <= rxd_int0(i-4);
else
rxd_q2(i) <= rxd_int(i);
end if;
elsif (sync_rxctrl_q2_delay = "01") then
rxd_q2(i) <= rxd_int0(i);
elsif (sync_rxctrl_q2_delay = "10") then
rxd_q2(i) <= rxd_int1(i);
else
rxd_q2(i) <= rxd_int2(i);
end if;
end process;
end generate;
rxd(3 downto 0) <= rxd_q1(3 downto 0) when (sync_rxctrl_q1_sel = '0') else rxd_q2(7 downto 4);
rxd(7 downto 4) <= rxd_q2(7 downto 4) when (sync_rxctrl_q1_sel = '0') else rxd_q1(3 downto 0);
ddr_dv0 : ddr_ireg generic map (tech, arch => 1)
port map (q1 => rx_dv_pre, q2 => rx_ctl_pre, c1 => rx_clk, c2 => nrx_clk,
ce => vcc, d => rgmiii.rx_dv, r => gnd, s => gnd);
process (rx_clk)
begin
if rising_edge(rx_clk) then
rx_ctl_int <= rx_ctl_pre;
rx_dv_int <= rx_dv_pre;
rx_ctl_int0 <= rx_ctl_int;
rx_ctl_int1 <= rx_ctl_int0;
rx_ctl_int2 <= rx_ctl_int1;
rx_dv_int0 <= rx_dv_int;
rx_dv_int1 <= rx_dv_int0;
rx_dv_int2 <= rx_dv_int2;
end if;
end process;
process (rx_clk)
begin
if (sync_rxctrl_q1_delay = "00") then
--rx_dv0 <= rx_dv_int;
if (sync_rxctrl_c_delay = '1') then
rx_dv0 <= rx_ctl_int;
else
rx_dv0 <= rx_dv_int;
end if;
elsif (sync_rxctrl_q1_delay = "01") then
rx_dv0 <= rx_dv_int0;
elsif (sync_rxctrl_q1_delay = "10") then
rx_dv0 <= rx_dv_int1;
else
rx_dv0 <= rx_dv_int2;
end if;
if (sync_rxctrl_q2_delay = "00") then
--rx_ctl0 <= rx_ctl_int;
if (sync_rxctrl_c_delay = '1') then
rx_ctl0 <= rx_dv_int0;
else
rx_ctl0 <= rx_ctl_int;
end if;
elsif (sync_rxctrl_q2_delay = "01") then
rx_ctl0 <= rx_ctl_int0;
elsif (sync_rxctrl_q2_delay = "10") then
rx_ctl0 <= rx_ctl_int1;
else
rx_ctl0 <= rx_ctl_int2;
end if;
end process;
rx_dv <= rx_dv0 when (sync_rxctrl_q1_sel = '0') else rx_ctl0;
rx_ctl <= rx_ctl0 when (sync_rxctrl_q1_sel = '0') else rx_dv0;
-- Decode GMII error signal
rx_error <= rx_dv xor rx_ctl;
-- Enable inband status registers during Interframe Gap
inbandopt <= not ( rx_dv or rx_error );
inbandreq <= rx_error and not rx_dv;
-- Sample RGMII inband information
process (rx_clk)
begin
if rising_edge(rx_clk) then
if (inbandopt = '1') then
link_status <= rxd(0);
clock_speed <= rxd(2 downto 1);
duplex_status <= rxd(3);
end if;
if (inbandreq = '1') then
if (rxd = x"0E") then false_carrier_ind <= '1'; else false_carrier_ind <= '0'; end if;
if (rxd = x"0F") then carrier_ext <= '1'; else carrier_ext <= '0'; end if;
if (rxd = x"1F") then carrier_ext_error <= '1'; else carrier_ext_error <= '0'; end if;
if (rxd = x"FF") then carrier_sense <= '1'; else carrier_sense <= '0'; end if;
end if;
end if;
end process;
-- GMII output
gmiii.rxd <= rxd;
gmiii.rx_dv <= rx_dv;
gmiii.rx_er <= rx_error;
gmiii.rx_clk <= rx_clk;
gmiii.rx_col <= '0';
gmiii.rx_crs <= rx_dv;
gmiii.rmii_clk <= '0';
gmiii.rx_en <= '1';
-- GMII output controlled via generics
gmiii.edclsepahb <= '0';
gmiii.edcldisable <= '0';
gmiii.phyrstaddr <= (others => '0');
gmiii.edcladdr <= (others => '0');
---------------------------------------------------------------------------------------
-- APB Section
---------------------------------------------------------------------------------------
apbo.pindex <= pindex;
apbo.pconfig <= pconfig;
-- Status Register
status_vector_sync(15) <= '1' when (no_clk_mux = 1) else '0';
status_vector_sync(14) <= '1' when (debugmem = 1 ) else '0';
status_vector_sync(13) <= '1' when (gmii = 1 ) else '0';
status_vector_sync(12 downto 10) <= (others => '0');
status_vector_sync(9) <= gmiio.gbit;
status_vector_sync(8) <= gmiio.speed;
status_vector_sync(7) <= carrier_sense;
status_vector_sync(6) <= carrier_ext_error;
status_vector_sync(5) <= carrier_ext;
status_vector_sync(4) <= false_carrier_ind;
status_vector_sync(3) <= duplex_status;
status_vector_sync(2) <= clock_speed(1);
status_vector_sync(1) <= clock_speed(0);
status_vector_sync(0) <= link_status;
-- CDC clock domain crossing
syncreg_status : for i in 0 to status_vector'length-1 generate
syncreg3 : syncreg port map (tx_clk, status_vector_sync(i), status_vector(i));
end generate;
rgmiiapb : process(apb_rstn, r, apbi, RMemRgmiiiData, RMemRgmiiiRead, RMemRgmiioRead, status_vector )
variable rdata : std_logic_vector(31 downto 0);
variable paddress : std_logic_vector(7 downto 2);
variable v : rgmiiregs;
begin
v := r;
paddress := (others => '0');
paddress(abits-1 downto 2) := apbi.paddr(abits-1 downto 2);
rdata := (others => '0');
v.status_vector(1) := r.status_vector(0);
v.status_vector(0) := status_vector;
-- read/write registers
if (apbi.psel(pindex) and apbi.penable and (not apbi.pwrite)) = '1' then
case paddress(7 downto 2) is
when "000000" =>
rdata(15 downto 0) := r.status_vector(0);
when "000001" =>
rdata(15 downto 0) := r.irq;
v.irq := (others => '0'); -- Interrupt is clear on read
when "000010" =>
rdata(15 downto 0) := r.mask;
when "000011" =>
rdata(5 downto 0) := std_logic_vector(r.clk25_wrap);
when "000100" =>
rdata(5 downto 0) := std_logic_vector(r.clk25_first_edge);
when "000101" =>
rdata(5 downto 0) := std_logic_vector(r.clk25_second_edge);
when "000110" =>
rdata(5 downto 0) := std_logic_vector(r.clk2_5_wrap);
when "000111" =>
rdata(5 downto 0) := std_logic_vector(r.clk2_5_first_edge);
when "001000" =>
rdata(5 downto 0) := std_logic_vector(r.clk2_5_second_edge);
when "001001" =>
rdata(23 downto 0) := r.clkedge;
when "001010" =>
rdata(1 downto 0) := v.rxctrl_q2_delay;
when "001011" =>
rdata(1 downto 0) := v.rxctrl_q1_delay;
when "001100" =>
rdata(0) := v.rxctrl_q1_sel;
when "001101" =>
rdata(0) := v.rxctrl_delay;
when "001110" =>
rdata(0) := v.rxctrl_c_delay;
when others =>
null;
end case;
end if;
if (apbi.psel(pindex) and apbi.penable and apbi.pwrite) = '1' then
case paddress(7 downto 2) is
when "000000" =>
null;
when "000001" =>
null;
when "000010" =>
v.mask := apbi.pwdata(15 downto 0);
when "000011" =>
v.clk25_wrap := unsigned(apbi.pwdata(5 downto 0));
when "000100" =>
v.clk25_first_edge := unsigned(apbi.pwdata(5 downto 0));
when "000101" =>
v.clk25_second_edge := unsigned(apbi.pwdata(5 downto 0));
when "000110" =>
v.clk2_5_wrap := unsigned(apbi.pwdata(5 downto 0));
when "000111" =>
v.clk2_5_first_edge := unsigned(apbi.pwdata(5 downto 0));
when "001000" =>
v.clk2_5_second_edge := unsigned(apbi.pwdata(5 downto 0));
when "001001" =>
v.clkedge := apbi.pwdata(23 downto 0);
when "001010" =>
v.rxctrl_q2_delay := apbi.pwdata(1 downto 0);
when "001011" =>
v.rxctrl_q1_delay := apbi.pwdata(1 downto 0);
when "001100" =>
v.rxctrl_q1_sel := apbi.pwdata(0);
when "001101" =>
v.rxctrl_delay := apbi.pwdata(0);
when "001110" =>
v.rxctrl_c_delay := apbi.pwdata(0);
when others =>
null;
end case;
end if;
-- Check interrupts
for i in 0 to r.status_vector'length-1 loop
if ((r.status_vector(0)(i) xor r.status_vector(1)(i)) and r.mask(i)) = '1' then
v.irq(i) := '1';
end if;
end loop;
-- reset operation
if (not RESET_ALL) and (apb_rstn = '0') then
if (tech = kintex7) then
v := RES_kintex7;
elsif (tech = spartan6) then
v := RES_spartan6;
elsif (tech = artix7) then
v := RES_artix7;
else
v := RES;
end if;
end if;
-- update registers
rin <= v;
-- drive outputs
if apbi.psel(pindex) = '0' then
apbo.prdata <= (others => '0');
elsif RMemRgmiiiRead = '1' then
apbo.prdata(31 downto 16) <= (others => '0');
apbo.prdata(15 downto 0) <= RMemRgmiiiData;
elsif RMemRgmiioRead = '1' then
apbo.prdata(31 downto 16) <= (others => '0');
apbo.prdata(15 downto 0) <= RMemRgmiioData;
else
apbo.prdata <= rdata;
end if;
apbo.pirq <= (others => '0');
apbo.pirq(pirq) <= orv(v.irq);
end process;
regs : process(apb_clk)
begin
if rising_edge(apb_clk) then
r <= rin;
if RESET_ALL and apb_rstn = '0' then
if (tech = kintex7) then
r <= RES_kintex7;
elsif (tech = spartan6) then
r <= RES_spartan6;
else
r <= RES;
end if;
end if;
end if;
end process;
---------------------------------------------------------------------------------------
-- Debug Mem
---------------------------------------------------------------------------------------
debugmem1 : if (debugmem /= 0) generate
-- Write GMII IN data
process (tx_clk)
begin -- process
if rising_edge(tx_clk) then
WMemRgmiioData(15 downto 0) <= "000" & tx_en & "000" & tx_ctl & txd;
if (tx_en = '1') and ((WMemRgmiioAddr < "0111111110") or (WMemRgmiioAddr = "1111111111")) then
WMemRgmiioAddr <= WMemRgmiioAddr + 1;
WMemRgmiioWrEn <= '1';
else
if (tx_en = '0') then
WMemRgmiioAddr <= (others => '1');
else
WMemRgmiioAddr <= WMemRgmiioAddr;
end if;
WMemRgmiioWrEn <= '0';
end if;
end if;
end process;
-- Read
RMemRgmiioRead <= apbi.paddr(10) and apbi.psel(pindex);
RMemRgmiioAddr <= "00" & apbi.paddr(10-1 downto 2);
gmiii0 : syncram_2p generic map (tech, 10, 16, 1, 0, 0) port map(
apb_clk, RMemRgmiioRead, RMemRgmiioAddr, RMemRgmiioData,
tx_clk, WMemRgmiioWrEn, WMemRgmiioAddr(10-1 downto 0), WMemRgmiioData);
-- Write GMII IN data
process (rx_clk)
begin -- process
if rising_edge(rx_clk) then
WMemRgmiiiData(15 downto 0) <= "000" & rx_dv & "000" & rx_ctl & rxd(7 downto 4) & rxd(3 downto 0);
if ((rx_dv = '1') or (rx_ctl = '1')) and ((WMemRgmiiiAddr < "0111111110") or (WMemRgmiiiAddr = "1111111111")) then
WMemRgmiiiAddr <= WMemRgmiiiAddr + 1;
WMemRgmiiiWrEn <= '1';
else
if (rx_dv = '0') then
WMemRgmiiiAddr <= (others => '1');
else
WMemRgmiiiAddr <= WMemRgmiiiAddr;
end if;
WMemRgmiiiWrEn <= '0';
end if;
end if;
end process;
-- Read
RMemRgmiiiRead <= apbi.paddr(11) and apbi.psel(pindex);
RMemRgmiiiAddr <= "00" & apbi.paddr(10-1 downto 2);
rgmiii0 : syncram_2p generic map (tech, 10, 16, 1, 0, 0) port map(
apb_clk, RMemRgmiiiRead, RMemRgmiiiAddr, RMemRgmiiiData,
rx_clk, WMemRgmiiiWrEn, WMemRgmiiiAddr(10-1 downto 0), WMemRgmiiiData);
end generate;
-- pragma translate_off
bootmsg : report_version
generic map ("rgmii" & tost(pindex) &
": RGMII rev " & tost(REVISION) & ", irq " & tost(pirq));
-- pragma translate_on
end rtl;
| gpl-3.0 | c4ad1b56745ebd72ebefb5023197aecb | 0.546482 | 3.264561 | false | false | false | false |
EliasLuiz/TCC | Leon3/lib/gaisler/leon3v3/libleon3.vhd | 1 | 7,863 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Package: libleon3
-- File: libleon3.vhd
-- Author: Jiri Gaisler Gaisler Research
-- Description: LEON3 internal components
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
library techmap;
use techmap.gencomp.all;
library gaisler;
use gaisler.leon3.all;
use gaisler.libiu.all;
use gaisler.libcache.all;
use gaisler.libfpu.all;
use gaisler.mmuiface.all;
package libleon3 is
component proc3
generic (
hindex : integer := 0;
fabtech : integer range 0 to NTECH := 0;
memtech : integer := 0;
nwindows : integer range 2 to 32 := 8;
dsu : integer range 0 to 1 := 0;
fpu : integer range 0 to 15 := 0;
v8 : integer range 0 to 63 := 0;
cp : integer range 0 to 1 := 0;
mac : integer range 0 to 1 := 0;
pclow : integer range 0 to 2 := 2;
notag : integer range 0 to 1 := 0;
nwp : integer range 0 to 4 := 0;
icen : integer range 0 to 1 := 0;
irepl : integer range 0 to 3 := 2;
isets : integer range 1 to 4 := 1;
ilinesize : integer range 4 to 8 := 4;
isetsize : integer range 1 to 256 := 1;
isetlock : integer range 0 to 1 := 0;
dcen : integer range 0 to 1 := 0;
drepl : integer range 0 to 3 := 2;
dsets : integer range 1 to 4 := 1;
dlinesize : integer range 4 to 8 := 4;
dsetsize : integer range 1 to 256 := 1;
dsetlock : integer range 0 to 1 := 0;
dsnoop : integer range 0 to 7 := 0;
ilram : integer range 0 to 2 := 0;
ilramsize : integer range 1 to 512 := 1;
ilramstart : integer range 0 to 255 := 16#8e#;
dlram : integer range 0 to 2 := 0;
dlramsize : integer range 1 to 512 := 1;
dlramstart : integer range 0 to 255 := 16#8f#;
mmuen : integer range 0 to 1 := 0;
itlbnum : integer range 2 to 64 := 8;
dtlbnum : integer range 2 to 64 := 8;
tlb_type : integer range 0 to 3 := 1;
tlb_rep : integer range 0 to 1 := 0;
lddel : integer range 1 to 2 := 2;
disas : integer range 0 to 2 := 0;
tbuf : integer range 0 to 128 := 0;
pwd : integer range 0 to 2 := 0; -- power-down
svt : integer range 0 to 1 := 0; -- single-vector trapping
rstaddr : integer := 0;
smp : integer range 0 to 15 := 0; -- support SMP systems
cached : integer := 0;
clk2x : integer := 0;
scantest : integer := 0;
mmupgsz : integer range 0 to 5 := 0;
bp : integer := 1;
npasi : integer range 0 to 1 := 0;
pwrpsr : integer range 0 to 1 := 0;
rex : integer := 0;
altwin : integer range 0 to 1 := 0
);
port (
clk : in std_ulogic;
rstn : in std_ulogic;
holdn : out std_ulogic;
ahbi : in ahb_mst_in_type;
ahbo : out ahb_mst_out_type;
ahbsi : in ahb_slv_in_type;
ahbso : in ahb_slv_out_vector;
rfi : out iregfile_in_type;
rfo : in iregfile_out_type;
crami : out cram_in_type;
cramo : in cram_out_type;
tbi : out tracebuf_in_type;
tbo : in tracebuf_out_type;
tbi_2p : out tracebuf_2p_in_type;
tbo_2p : in tracebuf_2p_out_type;
fpi : out fpc_in_type;
fpo : in fpc_out_type;
cpi : out fpc_in_type;
cpo : in fpc_out_type;
irqi : in l3_irq_in_type;
irqo : out l3_irq_out_type;
dbgi : in l3_debug_in_type;
dbgo : out l3_debug_out_type;
hclk, sclk : in std_ulogic;
hclken : in std_ulogic
);
end component;
component grfpwx
generic (
fabtech : integer := 0;
memtech : integer := 0;
mul : integer range 0 to 3 := 0;
pclow : integer range 0 to 2 := 2;
dsu : integer range 0 to 1 := 0;
disas : integer range 0 to 2 := 0;
netlist : integer := 0;
index : integer := 0;
scantest: integer := 0);
port (
rst : in std_ulogic; -- Reset
clk : in std_ulogic;
holdn : in std_ulogic; -- pipeline hold
cpi : in fpc_in_type;
cpo : out fpc_out_type;
testin : in std_logic_vector(TESTIN_WIDTH-1 downto 0)
);
end component;
component grlfpwx
generic (
tech : integer := 0;
pclow : integer range 0 to 2 := 2;
dsu : integer range 0 to 1 := 0;
disas : integer range 0 to 2 := 0;
pipe : integer := 0;
netlist : integer := 0;
index : integer := 0;
scantest: integer := 0
);
port (
rst : in std_ulogic; -- Reset
clk : in std_ulogic;
holdn : in std_ulogic; -- pipeline hold
cpi : in fpc_in_type;
cpo : out fpc_out_type;
testin: in std_logic_vector(TESTIN_WIDTH-1 downto 0)
);
end component;
component regfile_3p_l3
generic (
tech : integer := 0;
abits : integer := 6;
dbits : integer := 8;
wrfst : integer := 0;
numregs : integer := 64;
testen : integer := 0);
port (
wclk : in std_ulogic;
waddr : in std_logic_vector((abits -1) downto 0);
wdata : in std_logic_vector((dbits -1) downto 0);
we : in std_ulogic;
rclk : in std_ulogic;
raddr1 : in std_logic_vector((abits -1) downto 0);
re1 : in std_ulogic;
rdata1 : out std_logic_vector((dbits -1) downto 0);
raddr2 : in std_logic_vector((abits -1) downto 0);
re2 : in std_ulogic;
rdata2 : out std_logic_vector((dbits -1) downto 0);
testin : in std_logic_vector(TESTIN_WIDTH-1 downto 0)
);
end component;
end;
| gpl-3.0 | 18361cd4c75dd8056a8cc2c91da2af7a | 0.477299 | 3.818844 | false | true | false | false |
EliasLuiz/TCC | Leon3/designs/leon3-xilinx-ml403/leon3mp.vhd | 1 | 26,088 | -----------------------------------------------------------------------------
-- LEON3 Demonstration design
-- Copyright (C) 2004 Jiri Gaisler, Gaisler Research
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib, techmap;
use grlib.amba.all;
use grlib.devices.all;
use grlib.stdlib.all;
use techmap.gencomp.all;
use techmap.allclkgen.all;
library gaisler;
use gaisler.memctrl.all;
use gaisler.ddrpkg.all;
use gaisler.leon3.all;
use gaisler.uart.all;
use gaisler.misc.all;
use gaisler.i2c.all;
use gaisler.net.all;
use gaisler.jtag.all;
use gaisler.spacewire.all;
library esa;
use esa.memoryctrl.all;
use work.config.all;
entity leon3mp is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
ncpu : integer := CFG_NCPU;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW
);
port (
sys_rst_in : in std_ulogic;
sys_clk : in std_ulogic; -- 100 MHz main clock
--pragma translate_off
plb_error : out std_logic; -- ERRORn
--pragma translate_on
opb_error : out std_logic; -- DSU active
sram_flash_addr : out std_logic_vector(20 downto 0);
sram_flash_data : inout std_logic_vector(31 downto 0);
sram_cen : out std_logic;
sram_bw : out std_logic_vector (0 to 3);
sram_flash_oe_n : out std_ulogic;
sram_flash_we_n : out std_ulogic;
flash_ce : out std_logic;
sram_clk : out std_ulogic;
sram_clk_fb : in std_ulogic;
sram_adv_ld_n : out std_ulogic;
--pragma translate_off
iosn : out std_ulogic;
--pragma translate_on
ddr_clk : out std_logic;
ddr_clkb : out std_logic;
ddr_clk_fb : in std_logic;
ddr_cke : out std_logic;
ddr_csb : out std_logic;
ddr_web : out std_ulogic; -- ddr write enable
ddr_rasb : out std_ulogic; -- ddr ras
ddr_casb : out std_ulogic; -- ddr cas
ddr_dm : out std_logic_vector (3 downto 0); -- ddr dm
ddr_dqs : inout std_logic_vector (3 downto 0); -- ddr dqs
ddr_ad : out std_logic_vector (12 downto 0); -- ddr address
ddr_ba : out std_logic_vector (1 downto 0); -- ddr bank address
ddr_dq : inout std_logic_vector (31 downto 0); -- ddr data
txd1 : out std_ulogic; -- UART1 tx data
rxd1 : in std_ulogic; -- UART1 rx data
gpio : inout std_logic_vector(13 downto 0); -- I/O port
phy_gtx_clk : out std_logic;
phy_mii_data : inout std_logic; -- ethernet PHY interface
phy_tx_clk : in std_ulogic;
phy_rx_clk : in std_ulogic;
phy_rx_data : in std_logic_vector(7 downto 0);
phy_dv : in std_ulogic;
phy_rx_er : in std_ulogic;
phy_col : in std_ulogic;
phy_crs : in std_ulogic;
phy_tx_data : out std_logic_vector(7 downto 0);
phy_tx_en : out std_ulogic;
phy_tx_er : out std_ulogic;
phy_mii_clk : out std_ulogic;
phy_rst_n : out std_ulogic;
ps2_keyb_clk : inout std_logic;
ps2_keyb_data : inout std_logic;
ps2_mouse_clk : inout std_logic;
ps2_mouse_data : inout std_logic;
tft_lcd_clk : out std_ulogic;
vid_hsync : out std_ulogic;
vid_vsync : out std_ulogic;
vid_r : out std_logic_vector(7 downto 3);
vid_g : out std_logic_vector(7 downto 3);
vid_b : out std_logic_vector(7 downto 3);
usb_csn : out std_logic;
iic_scl : inout std_ulogic;
iic_sda : inout std_ulogic
);
end;
architecture rtl of leon3mp is
constant blength : integer := 12;
constant fifodepth : integer := 8;
constant maxahbm : integer := NCPU+CFG_AHB_UART
+CFG_GRETH+CFG_AHB_JTAG+CFG_SVGA_ENABLE;
signal vcc, gnd : std_logic_vector(4 downto 0);
signal memi : memory_in_type;
signal memo : memory_out_type;
signal wpo : wprot_out_type;
signal sdi : sdctrl_in_type;
signal sdo : sdctrl_out_type;
signal sdo2 : sdctrl_out_type;
signal apbi : apb_slv_in_type;
signal apbo : apb_slv_out_vector := (others => apb_none);
signal ahbsi : ahb_slv_in_type;
signal ahbso : ahb_slv_out_vector := (others => ahbs_none);
signal ahbmi : ahb_mst_in_type;
signal ahbmo : ahb_mst_out_vector := (others => ahbm_none);
signal clkm, rstn, rstraw, srclkl : std_ulogic;
signal clkm_90, clkm_180, clkm_270 : std_ulogic;
signal cgi, cgi2 : clkgen_in_type;
signal cgo, cgo2 : clkgen_out_type;
signal u1i, u2i, dui : uart_in_type;
signal u1o, u2o, duo : uart_out_type;
signal irqi : irq_in_vector(0 to NCPU-1);
signal irqo : irq_out_vector(0 to NCPU-1);
signal dbgi : l3_debug_in_vector(0 to NCPU-1);
signal dbgo : l3_debug_out_vector(0 to NCPU-1);
signal dsui : dsu_in_type;
signal dsuo : dsu_out_type;
signal ethi, ethi1, ethi2 : eth_in_type;
signal etho, etho1, etho2 : eth_out_type;
signal gpti : gptimer_in_type;
signal gpioi : gpio_in_type;
signal gpioo : gpio_out_type;
signal clklock, lock, lclk, clkml, rst, ndsuact : std_ulogic;
signal tck, tckn, tms, tdi, tdo : std_ulogic;
signal ddrclk, ddrrst : std_ulogic;
signal ethclk, egtx_clk_fb : std_ulogic;
signal egtx_clk, legtx_clk, l2egtx_clk : std_ulogic;
signal kbdi : ps2_in_type;
signal kbdo : ps2_out_type;
signal moui : ps2_in_type;
signal mouo : ps2_out_type;
signal vgao : apbvga_out_type;
signal clk_sel : std_logic_vector(1 downto 0);
signal clkval : std_logic_vector(1 downto 0);
signal clkvga, clk1x, video_clk, dac_clk : std_ulogic;
signal i2ci : i2c_in_type;
signal i2co : i2c_out_type;
constant BOARD_FREQ : integer := 100000; -- input frequency in KHz
constant CPU_FREQ : integer := BOARD_FREQ * CFG_CLKMUL / CFG_CLKDIV; -- cpu frequency in KHz
constant I2C_FILTER : integer := (CPU_FREQ*5+50000)/100000+1;
constant IOAEN : integer := CFG_DDRSP;
signal stati : ahbstat_in_type;
signal ddrclkfb, ssrclkfb, ddr_clkl, ddr_clk90l, ddr_clknl, ddr_clk270l : std_ulogic;
signal ddr_clkv : std_logic_vector(2 downto 0);
signal ddr_clkbv : std_logic_vector(2 downto 0);
signal ddr_ckev : std_logic_vector(1 downto 0);
signal ddr_csbv : std_logic_vector(1 downto 0);
signal ddr_adl : std_logic_vector (13 downto 0);
attribute syn_keep : boolean;
attribute syn_preserve : boolean;
attribute syn_keep of clkml : signal is true;
attribute syn_preserve of clkml : signal is true;
attribute syn_keep of egtx_clk : signal is true;
attribute syn_preserve of egtx_clk : signal is true;
attribute keep : boolean;
attribute keep of lock : signal is true;
attribute keep of clkml : signal is true;
attribute keep of clkm : signal is true;
attribute keep of egtx_clk : signal is true;
signal romsn : std_ulogic;
constant SPW_LOOP_BACK : integer := 0;
begin
usb_csn <= '1';
----------------------------------------------------------------------
--- Reset and Clock generation -------------------------------------
----------------------------------------------------------------------
vcc <= (others => '1'); gnd <= (others => '0');
cgi.pllctrl <= "00"; cgi.pllrst <= rstraw; cgi.pllref <= ssrclkfb;
ssrref_pad : clkpad generic map (tech => padtech)
port map (sram_clk_fb, ssrclkfb);
clk_pad : clkpad generic map (tech => padtech, arch => 2)
port map (sys_clk, lclk);
srclk_pad : outpad generic map (tech => padtech, slew => 1, strength => 24)
port map (sram_clk, srclkl);
clkgen0 : clkgen -- system clock generator
generic map (CFG_FABTECH, CFG_CLKMUL, CFG_CLKDIV, 1, 0, 0, 0, 0, BOARD_FREQ, 0)
port map (lclk, gnd(0), clkm, open, open, srclkl, open, cgi, cgo, open, clk1x);
g1clk : if CFG_GRETH1G /= 0 generate
clkgen1 : clkgen -- Ethernet 1G PHY clock generator
generic map (CFG_FABTECH, 5, 4, 0, 0, 0, 0, 0, BOARD_FREQ, 0)
port map (lclk, gnd(0), egtx_clk, open, open, open, open, cgi2, cgo2);
cgi2.pllctrl <= "00"; cgi2.pllrst <= rstraw; --cgi2.pllref <= egtx_clk_fb;
egtx_clk_pad : outpad generic map (tech => padtech)
port map (phy_gtx_clk, egtx_clk);
clklock <= lock and cgo2.clklock;
end generate;
nog1clk : if CFG_GRETH1G = 0 generate
clklock <= lock;
end generate;
resetn_pad : inpad generic map (tech => padtech) port map (sys_rst_in, rst);
rst0 : rstgen -- reset generator
port map (rst, clkm, clklock, rstn, rstraw);
----------------------------------------------------------------------
--- AHB CONTROLLER --------------------------------------------------
----------------------------------------------------------------------
ahb0 : ahbctrl -- AHB arbiter/multiplexer
generic map (defmast => CFG_DEFMST, split => CFG_SPLIT,
rrobin => CFG_RROBIN, ioaddr => CFG_AHBIO, devid => XILINX_ML401,
ioen => IOAEN, nahbm => maxahbm, nahbs => 8)
port map (rstn, clkm, ahbmi, ahbmo, ahbsi, ahbso);
----------------------------------------------------------------------
--- LEON3 processor and DSU -----------------------------------------
----------------------------------------------------------------------
l3 : if CFG_LEON3 = 1 generate
cpu : for i in 0 to NCPU-1 generate
u0 : leon3s -- LEON3 processor
generic map (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU, CFG_V8,
0, CFG_MAC, pclow, CFG_NOTAG, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE,
CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ,
CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN,
CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP,
CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR, NCPU-1,
CFG_DFIXED, CFG_SCAN, CFG_MMU_PAGE, CFG_BP, CFG_NP_ASI, CFG_WRPSR)
port map (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso,
irqi(i), irqo(i), dbgi(i), dbgo(i));
end generate;
--pragma translate_off
errorn_pad : odpad generic map (tech => padtech) port map (plb_error, dbgo(0).error);
--pragma translate_on
dsugen : if CFG_DSU = 1 generate
dsu0 : dsu3 -- LEON3 Debug Support Unit
generic map (hindex => 2, haddr => 16#900#, hmask => 16#F00#,
ncpu => NCPU, tbits => 30, tech => memtech, irq => 0, kbytes => CFG_ATBSZ)
port map (rstn, clkm, ahbmi, ahbsi, ahbso(2), dbgo, dbgi, dsui, dsuo);
-- dsuen_pad : inpad generic map (tech => padtech) port map (dsuen, dsui.enable);
dsui.enable <= '1';
-- dsubre_pad : inpad generic map (tech => padtech) port map (dsubre, dsui.break);
dsui.break <= gpioo.val(11); -- South Button
-- dsuact_pad : outpad generic map (tech => padtech) port map (dsuact, ndsuact);
dsuact_pad : outpad generic map (tech => padtech) port map (opb_error, ndsuact);
ndsuact <= not dsuo.active;
end generate;
end generate;
nodsu : if CFG_DSU = 0 generate
dsuo.tstop <= '0'; dsuo.active <= '0';
end generate;
dcomgen : if CFG_AHB_UART = 1 generate
dcom0: ahbuart -- Debug UART
generic map (hindex => NCPU, pindex => 7, paddr => 7)
port map (rstn, clkm, dui, duo, apbi, apbo(7), ahbmi, ahbmo(NCPU));
-- dsurx_pad : inpad generic map (tech => padtech) port map (rxd1, dui.rxd);
-- dsutx_pad : outpad generic map (tech => padtech) port map (txd1, duo.txd);
dui.rxd <= rxd1 when gpioo.val(13) = '1' else '1';
end generate;
txd1 <= duo.txd when gpioo.val(13) = '1' else u1o.txd;
ahbjtaggen0 :if CFG_AHB_JTAG = 1 generate
ahbjtag0 : ahbjtag generic map(tech => fabtech, hindex => NCPU+CFG_AHB_UART)
port map(rstn, clkm, tck, tms, tdi, tdo, ahbmi, ahbmo(NCPU+CFG_AHB_UART),
open, open, open, open, open, open, open, gnd(0));
end generate;
----------------------------------------------------------------------
--- Memory controllers ----------------------------------------------
----------------------------------------------------------------------
memi.writen <= '1'; memi.wrn <= "1111"; memi.bwidth <= "10";
memi.brdyn <= '1'; memi.bexcn <= '1';
ssr0 : if CFG_SSCTRL = 1 generate
ssrctrl0 : ssrctrl generic map (hindex => 3, pindex => 0, ramaddr => 16#600#)
port map (rstn, clkm, ahbsi, ahbso(3), apbi, apbo(0), memi, memo);
end generate;
mctrl0 : if CFG_MCTRL_LEON2 = 1 generate
mctrl0 : mctrl generic map (hindex => 3, pindex => 0,
ramaddr => 16#C00#, rammask => 16#FF0#,
paddr => 0, srbanks => 1, ram8 => CFG_MCTRL_RAM8BIT,
ram16 => CFG_MCTRL_RAM16BIT, sden => CFG_MCTRL_SDEN,
invclk => CFG_MCTRL_INVCLK, sepbus => CFG_MCTRL_SEPBUS)
port map (rstn, clkm, memi, memo, ahbsi, ahbso(3), apbi, apbo(0), wpo, open);
end generate;
romsn <= not memo.romsn(0);
sram_adv_ld_n_pad : outpad generic map (tech => padtech)
port map (sram_adv_ld_n, gnd(0));
addr_pad : outpadv generic map (width => 21, tech => padtech)
port map (sram_flash_addr, memo.address(22 downto 2));
rams_pad : outpad generic map ( tech => padtech)
port map (sram_cen, memo.ramsn(0));
roms_pad : outpad generic map (tech => padtech)
port map (flash_ce, romsn);
oen_pad : outpad generic map (tech => padtech)
port map (sram_flash_oe_n, memo.oen);
--pragma translate_off
iosn_pad : outpad generic map (tech => padtech)
port map (iosn, memo.iosn);
--pragma translate_on
rwen_pad : outpadv generic map (width => 4, tech => padtech)
port map (sram_bw, memo.wrn);
wri_pad : outpad generic map (tech => padtech)
port map (sram_flash_we_n, memo.writen);
data_pads : iopadvv generic map (tech => padtech, width => 32)
port map (sram_flash_data, memo.data, memo.vbdrive, memi.data);
ddrsp0 : if (CFG_DDRSP /= 0) generate
ddrc0 : ddrspa generic map ( fabtech => CFG_FABTECH, memtech => memtech,
hindex => 0, haddr => 16#400#, hmask => 16#F00#, ioaddr => 1,
pwron => CFG_DDRSP_INIT, MHz => BOARD_FREQ/1000,
clkmul => CFG_DDRSP_FREQ/10, clkdiv => 10, ahbfreq => CPU_FREQ/1000,
col => CFG_DDRSP_COL, Mbyte => CFG_DDRSP_SIZE, ddrbits => 32,
phyiconf => 1)
port map (
rst, rstn, lclk, clkm, lock, clkml, clkml, ahbsi, ahbso(0),
ddr_clkv, ddr_clkbv, open, ddr_clk_fb,
ddr_ckev, ddr_csbv, ddr_web, ddr_rasb, ddr_casb,
ddr_dm, ddr_dqs, ddr_adl, ddr_ba, ddr_dq);
ddr_ad <= ddr_adl(12 downto 0);
ddr_clk <= ddr_clkv(0); ddr_clkb <= ddr_clkbv(0);
ddr_cke <= ddr_ckev(0); ddr_csb <= ddr_csbv(0);
end generate;
noddr : if (CFG_DDRSP = 0) generate lock <= '1'; end generate;
----------------------------------------------------------------------
--- APB Bridge and various periherals -------------------------------
----------------------------------------------------------------------
bpromgen : if CFG_AHBROMEN /= 0 generate
brom : entity work.ahbrom
generic map (hindex => 6, haddr => CFG_AHBRODDR, pipe => CFG_AHBROPIP)
port map ( rstn, clkm, ahbsi, ahbso(6));
end generate;
----------------------------------------------------------------------
--- APB Bridge and various periherals -------------------------------
----------------------------------------------------------------------
apb0 : apbctrl -- AHB/APB bridge
generic map (hindex => 1, haddr => CFG_APBADDR, nslaves => 16)
port map (rstn, clkm, ahbsi, ahbso(1), apbi, apbo );
ua1 : if CFG_UART1_ENABLE /= 0 generate
uart1 : apbuart -- UART 1
generic map (pindex => 1, paddr => 1, pirq => 2, console => dbguart,
fifosize => CFG_UART1_FIFO)
port map (rstn, clkm, apbi, apbo(1), u1i, u1o);
u1i.extclk <= '0'; u1i.ctsn <= '0';
u1i.rxd <= rxd1 when gpioo.val(13) = '0' else '1';
end generate;
irqctrl : if CFG_IRQ3_ENABLE /= 0 generate
irqctrl0 : irqmp -- interrupt controller
generic map (pindex => 2, paddr => 2, ncpu => NCPU)
port map (rstn, clkm, apbi, apbo(2), irqo, irqi);
end generate;
irq3 : if CFG_IRQ3_ENABLE = 0 generate
x : for i in 0 to NCPU-1 generate
irqi(i).irl <= "0000";
end generate;
apbo(2) <= apb_none;
end generate;
gpt : if CFG_GPT_ENABLE /= 0 generate
timer0 : gptimer -- timer unit
generic map (pindex => 3, paddr => 3, pirq => CFG_GPT_IRQ,
sepirq => CFG_GPT_SEPIRQ, sbits => CFG_GPT_SW, ntimers => CFG_GPT_NTIM,
nbits => CFG_GPT_TW)
port map (rstn, clkm, apbi, apbo(3), gpti, open);
gpti <= gpti_dhalt_drive(dsuo.tstop);
end generate;
nogpt : if CFG_GPT_ENABLE = 0 generate apbo(3) <= apb_none; end generate;
kbd : if CFG_KBD_ENABLE /= 0 generate
ps21 : apbps2 generic map(pindex => 4, paddr => 4, pirq => 4)
port map(rstn, clkm, apbi, apbo(4), moui, mouo);
ps20 : apbps2 generic map(pindex => 5, paddr => 5, pirq => 5)
port map(rstn, clkm, apbi, apbo(5), kbdi, kbdo);
end generate;
nokbd : if CFG_KBD_ENABLE = 0 generate apbo(5) <= apb_none; kbdo <= ps2o_none; end generate;
kbdclk_pad : iopad generic map (tech => padtech)
port map (ps2_keyb_clk,kbdo.ps2_clk_o, kbdo.ps2_clk_oe, kbdi.ps2_clk_i);
kbdata_pad : iopad generic map (tech => padtech)
port map (ps2_keyb_data, kbdo.ps2_data_o, kbdo.ps2_data_oe, kbdi.ps2_data_i);
mouclk_pad : iopad generic map (tech => padtech)
port map (ps2_mouse_clk, mouo.ps2_clk_o, mouo.ps2_clk_oe, moui.ps2_clk_i);
mouata_pad : iopad generic map (tech => padtech)
port map (ps2_mouse_data, mouo.ps2_data_o, mouo.ps2_data_oe, moui.ps2_data_i);
vga : if CFG_VGA_ENABLE /= 0 generate
vga0 : apbvga generic map(memtech => memtech, pindex => 6, paddr => 6)
port map(rstn, clkm, ethclk, apbi, apbo(6), vgao);
clk_sel <= "00";
end generate;
svga : if CFG_SVGA_ENABLE /= 0 generate
svga0 : svgactrl generic map(memtech => memtech, pindex => 6, paddr => 6,
hindex => CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG,
clk0 => 4*(1000000000/BOARD_FREQ), clk1 => 2*(1000000000/BOARD_FREQ),
clk2 => 1000000000/CPU_FREQ, burstlen => 6)
port map(rstn, clkm, clkvga, apbi, apbo(6), vgao, ahbmi,
ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG), clk_sel);
end generate;
vgadiv : if (CFG_VGA_ENABLE + CFG_SVGA_ENABLE) /= 0 generate
clkdiv : process(clk1x, rstn)
begin
if rstn = '0' then clkval <= "00";
elsif rising_edge(clk1x) then
clkval <= clkval + 1;
end if;
end process;
video_clk <= clkval(1) when clk_sel = "00" else clkval(0) when clk_sel = "01" else clkm;
b1 : techbuf generic map (2, CFG_FABTECH) port map (video_clk, clkvga);
dac_clk <= not clkvga;
end generate;
novga : if (CFG_VGA_ENABLE + CFG_SVGA_ENABLE) = 0 generate
apbo(6) <= apb_none; vgao <= vgao_none;
end generate;
vert_sync_pad : outpad generic map (tech => padtech)
port map (vid_vsync, vgao.vsync);
horiz_sync_pad : outpad generic map (tech => padtech)
port map (vid_hsync, vgao.hsync);
video_out_r_pad : outpadv generic map (width => 5, tech => padtech)
port map (vid_r(7 downto 3), vgao.video_out_r(7 downto 3));
video_out_g_pad : outpadv generic map (width => 5, tech => padtech)
port map (vid_g(7 downto 3), vgao.video_out_g(7 downto 3));
video_out_b_pad : outpadv generic map (width => 5, tech => padtech)
port map (vid_b(7 downto 3), vgao.video_out_b(7 downto 3));
video_clock_pad : outpad generic map ( tech => padtech)
port map (tft_lcd_clk, dac_clk);
gpio0 : if CFG_GRGPIO_ENABLE /= 0 generate -- GPIO unit
grgpio0: grgpio
generic map(pindex => 8, paddr => 8, imask => 16#00F0#, nbits => 14)
port map(rst => rstn, clk => clkm, apbi => apbi, apbo => apbo(8),
gpioi => gpioi, gpioo => gpioo);
gpio_pads : iopadvv generic map (tech => padtech, width => 14)
port map (gpio, gpioo.dout(13 downto 0), gpioo.oen(13 downto 0),
gpioi.din(13 downto 0));
end generate;
ahbs : if CFG_AHBSTAT = 1 generate -- AHB status register
stati <= ahbstat_in_none;
ahbstat0 : ahbstat generic map (pindex => 15, paddr => 15, pirq => 7,
nftslv => CFG_AHBSTATN)
port map (rstn, clkm, ahbmi, ahbsi, stati, apbi, apbo(15));
end generate;
i2cm: if CFG_I2C_ENABLE = 1 generate -- I2C master
i2c0 : i2cmst
generic map (pindex => 12, paddr => 12, pmask => 16#FFF#,
pirq => 11, filter => I2C_FILTER)
port map (rstn, clkm, apbi, apbo(12), i2ci, i2co);
i2c_scl_pad : iopad generic map (tech => padtech)
port map (iic_scl, i2co.scl, i2co.scloen, i2ci.scl);
i2c_sda_pad : iopad generic map (tech => padtech)
port map (iic_sda, i2co.sda, i2co.sdaoen, i2ci.sda);
end generate i2cm;
-----------------------------------------------------------------------
--- ETHERNET ---------------------------------------------------------
-----------------------------------------------------------------------
eth1 : if CFG_GRETH = 1 generate -- Gaisler ethernet MAC
e1 : grethm generic map(hindex => NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_SVGA_ENABLE,
pindex => 11, paddr => 11, pirq => 12, memtech => memtech,
mdcscaler => CPU_FREQ/1000, enable_mdio => 1, fifosize => CFG_ETH_FIFO,
nsync => 1, edcl => CFG_DSU_ETH, edclbufsz => CFG_ETH_BUF,
macaddrh => CFG_ETH_ENM, macaddrl => CFG_ETH_ENL,
ipaddrh => CFG_ETH_IPM, ipaddrl => CFG_ETH_IPL, giga => CFG_GRETH1G)
port map( rst => rstn, clk => clkm, ahbmi => ahbmi,
ahbmo => ahbmo(NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_SVGA_ENABLE),
apbi => apbi, apbo => apbo(11), ethi => ethi, etho => etho);
emdio_pad : iopad generic map (tech => padtech)
port map (phy_mii_data, etho.mdio_o, etho.mdio_oe, ethi.mdio_i);
etxc_pad : clkpad generic map (tech => padtech, arch => 2)
port map (phy_tx_clk, ethi.tx_clk);
erxc_pad : clkpad generic map (tech => padtech, arch => 2)
port map (phy_rx_clk, ethi.rx_clk);
erxd_pad : inpadv generic map (tech => padtech, width => 8)
port map (phy_rx_data, ethi.rxd(7 downto 0));
erxdv_pad : inpad generic map (tech => padtech)
port map (phy_dv, ethi.rx_dv);
erxer_pad : inpad generic map (tech => padtech)
port map (phy_rx_er, ethi.rx_er);
erxco_pad : inpad generic map (tech => padtech)
port map (phy_col, ethi.rx_col);
erxcr_pad : inpad generic map (tech => padtech)
port map (phy_crs, ethi.rx_crs);
etxd_pad : outpadv generic map (tech => padtech, width => 8)
port map (phy_tx_data, etho.txd(7 downto 0));
etxen_pad : outpad generic map (tech => padtech)
port map ( phy_tx_en, etho.tx_en);
etxer_pad : outpad generic map (tech => padtech)
port map (phy_tx_er, etho.tx_er);
emdc_pad : outpad generic map (tech => padtech)
port map (phy_mii_clk, etho.mdc);
erst_pad : outpad generic map (tech => padtech)
port map (phy_rst_n, rstn);
ethi.gtx_clk <= egtx_clk;
end generate;
-----------------------------------------------------------------------
--- AHB RAM ----------------------------------------------------------
-----------------------------------------------------------------------
ocram : if CFG_AHBRAMEN = 1 generate
ahbram0 : ahbram generic map (hindex => 7, haddr => CFG_AHBRADDR,
tech => CFG_MEMTECH, kbytes => CFG_AHBRSZ, pipe => CFG_AHBRPIPE)
port map ( rstn, clkm, ahbsi, ahbso(7));
end generate;
-----------------------------------------------------------------------
--- AHB DEBUG --------------------------------------------------------
-----------------------------------------------------------------------
-- dma0 : ahbdma
-- generic map (hindex => CFG_NCPU+CFG_AHB_UART+CFG_GRETH+CFG_AHB_JTAG,
-- pindex => 13, paddr => 13, dbuf => 6)
-- port map (rstn, clkm, apbi, apbo(13), ahbmi,
-- ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_GRETH+CFG_AHB_JTAG));
-- at0 : ahbtrace
-- generic map ( hindex => 7, ioaddr => 16#200#, iomask => 16#E00#,
-- tech => memtech, irq => 0, kbytes => 8)
-- port map ( rstn, clkm, ahbmi, ahbsi, ahbso(7));
-----------------------------------------------------------------------
--- Drive unused bus elements ---------------------------------------
-----------------------------------------------------------------------
-- nam1 : for i in (NCPU+CFG_AHB_UART+CFG_ETH+CFG_AHB_ETH+CFG_AHB_JTAG) to NAHBMST-1 generate
-- ahbmo(i) <= ahbm_none;
-- end generate;
-- nap0 : for i in 11 to NAPBSLV-1 generate apbo(i) <= apb_none; end generate;
-- nah0 : for i in 8 to NAHBSLV-1 generate ahbso(i) <= ahbs_none; end generate;
-----------------------------------------------------------------------
--- Boot message ----------------------------------------------------
-----------------------------------------------------------------------
-- pragma translate_off
x : report_design
generic map (
msg1 => "LEON3 Avnet ML401 (Virtex4 LX25) Demonstration design",
fabtech => tech_table(fabtech), memtech => tech_table(memtech),
mdel => 1
);
-- pragma translate_on
end;
| gpl-3.0 | f0598d8fb02b295925a7f8f9926316a8 | 0.57375 | 3.433987 | false | false | false | false |
EliasLuiz/TCC | Leon3/lib/techmap/stratixiii/serdes_stratixiii.vhd | 1 | 8,913 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: serdes_stratixiii
-- File: serdes_stratixiii.vhd
-- Author: Andrea Gianarro - Aeroflex Gaisler AB
-- Description: Stratix III and IV SGMII Gigabit Ethernet Serdes
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.stdlib.all;
library techmap;
use techmap.gencomp.all;
library altera_mf;
use altera_mf.altera_mf_components.all;
entity serdes_stratixiii is
port (
clk_125 : in std_logic;
rst_125 : in std_logic;
rx_in : in std_logic; -- SER IN
rx_out : out std_logic_vector(9 downto 0); -- PAR OUT
rx_clk : out std_logic;
rx_rstn : out std_logic;
rx_pll_clk : out std_logic;
rx_pll_rstn : out std_logic;
tx_pll_clk : out std_logic;
tx_pll_rstn : out std_logic;
tx_in : in std_logic_vector(9 downto 0) ; -- PAR IN
tx_out : out std_logic; -- SER OUT
bitslip : in std_logic
);
end entity;
architecture rtl of serdes_stratixiii is
signal rx_clk_int, rx_pll_clk_int, tx_pll_clk_int, rst_int, pll_areset_int, rx_locked_int, rx_rstn_int_0, tx_locked_int : std_logic;
signal rx_cda_reset_int, bitslip_int, rx_in_int, rx_rst_int, rx_divfwdclk_int, tx_out_int : std_logic_vector(0 downto 0) ;
signal rx_clk_rstn_int, rx_pll_rstn_int, tx_pll_rstn_int, rx_cda_reset_int_0 : std_logic;
signal rx_out_int, tx_in_int : std_logic_vector(9 downto 0) ;
signal r0, r1, r2 : std_logic_vector(4 downto 0);
signal r3 : std_logic_vector(5 downto 0);
signal r4 : std_logic_vector(1 downto 0);
begin
bitslip_int(0) <= bitslip;
rx_in_int(0) <= rx_in;
tx_in_int <= tx_in;
rx_out <= rx_out_int;
tx_out <= tx_out_int(0);
-- output clocks
rx_clk <= rx_clk_int;
rx_pll_clk <= rx_pll_clk_int;
tx_pll_clk <= tx_pll_clk_int;
-- output synchronized resets
rx_rstn <= rx_clk_rstn_int;
rx_pll_rstn <= rx_pll_rstn_int;
tx_pll_rstn <= tx_pll_rstn_int;
--rx_cda_reset_int(0) <= rx_cda_reset_int_0;
rx_rst_int(0) <= not rx_rstn_int_0;
rx_clk_int <= rx_divfwdclk_int(0);
-- reset synchronizers
rst0 : process (rx_clk_int, rst_125) begin
if rising_edge(rx_clk_int) then
r0 <= r0(3 downto 0) & rx_locked_int;
rx_clk_rstn_int <= r0(4) and r0(3) and r0(2);
end if;
if (rst_125 = '1') then r0 <= "00000"; rx_clk_rstn_int <= '0'; end if;
end process;
rst1 : process (rx_pll_clk_int, rx_clk_rstn_int) begin
if rising_edge(rx_pll_clk_int) then
r1 <= r1(3 downto 0) & rx_locked_int;
rx_pll_rstn_int <= r1(4) and r1(3) and r1(2);
end if;
if (rx_clk_rstn_int = '0') then r1 <= "00000"; rx_pll_rstn_int <= '0'; end if;
end process;
rst2 : process (tx_pll_clk_int, rx_clk_rstn_int) begin
if rising_edge(tx_pll_clk_int) then
r2 <= r2(3 downto 0) & tx_locked_int;
tx_pll_rstn_int <= r2(4) and r2(3) and r2(2);
end if;
if (rx_clk_rstn_int = '0') then r2 <= "00000"; tx_pll_rstn_int <= '0'; end if;
end process;
-- 6 stages reset synchronizer
rst3 : process (clk_125, rst_125) begin
if rising_edge(clk_125) then
r3 <= r3(4 downto 0) & rx_locked_int;
rx_rstn_int_0 <= r3(5) and r3(4) and r3(3);
end if;
if (rst_125 = '1') then r3 <= "000000"; rx_rstn_int_0 <= '0'; end if;
end process;
lvds_rx0: altlvds_rx
generic map (
buffer_implementation => "RAM",
cds_mode => "UNUSED",
--clk_src_is_pll => "off",
common_rx_tx_pll => "ON",
data_align_rollover => 10,
--data_rate => "1250.0 Mbps",
deserialization_factor => 10,
dpa_initial_phase_value => 0,
dpll_lock_count => 0,
dpll_lock_window => 0,
--enable_clock_pin_mode => "UNUSED",
enable_dpa_align_to_rising_edge_only => "OFF",
enable_dpa_calibration => "ON",
enable_dpa_fifo => "UNUSED",
enable_dpa_initial_phase_selection => "OFF",
enable_dpa_mode => "ON",
enable_dpa_pll_calibration => "OFF",
enable_soft_cdr_mode => "ON",
implement_in_les => "OFF",
inclock_boost => 0,
inclock_data_alignment => "EDGE_ALIGNED",
inclock_period => 8000,
inclock_phase_shift => 0,
input_data_rate => 1250,
intended_device_family => "Stratix IV",
lose_lock_on_one_change => "UNUSED",
lpm_hint => "UNUSED",
lpm_type => "altlvds_rx",
number_of_channels => 1,
outclock_resource => "AUTO",
pll_operation_mode => "UNUSED",
pll_self_reset_on_loss_lock => "UNUSED",
port_rx_channel_data_align => "PORT_USED",
port_rx_data_align => "PORT_UNUSED",
--refclk_frequency => "125.000000 MHz",
registered_data_align_input => "UNUSED",
registered_output => "ON",
reset_fifo_at_first_lock => "UNUSED",
rx_align_data_reg => "UNUSED",
sim_dpa_is_negative_ppm_drift => "OFF",
sim_dpa_net_ppm_variation => 0,
sim_dpa_output_clock_phase_shift => 0,
use_coreclock_input => "OFF",
use_dpll_rawperror => "OFF",
use_external_pll => "OFF",
use_no_phase_shift => "ON",
x_on_bitslip => "ON"
)
port map (
pll_areset => rst_125, --pll_areset_int,
rx_channel_data_align => bitslip_int,
rx_in => rx_in_int,
rx_inclock => clk_125,
rx_reset => rx_rst_int,
rx_divfwdclk => rx_divfwdclk_int,
rx_locked => rx_locked_int,
rx_out => rx_out_int,
rx_outclock => rx_pll_clk_int,
dpa_pll_cal_busy => open,
dpa_pll_recal => '0',
pll_phasecounterselect => open,
pll_phasedone => '1',
pll_phasestep => open,
pll_phaseupdown => open,
pll_scanclk => open,
rx_cda_max => open,
rx_cda_reset => (others => '0'),
rx_coreclk => (others => '1'),
rx_data_align => '0',
rx_data_align_reset => '0',
--rx_data_reset => '0',
rx_deskew => '0',
rx_dpa_lock_reset => (others => '0'),
rx_dpa_locked => open,
--rx_dpaclock => '0',
rx_dpll_enable => (others => '1'),
rx_dpll_hold => (others => '0'),
rx_dpll_reset => (others => '0'),
rx_enable => '1',
rx_fifo_reset => (others => '0'),
rx_pll_enable => '1',
rx_readclock => '0',
rx_syncclock => '0'
);
lvds_tx0: altlvds_tx
generic map (
center_align_msb => "UNUSED",
--clk_src_is_pll => "off",
common_rx_tx_pll => "ON",
coreclock_divide_by => 1,
--data_rate => "1250.0 Mbps",
deserialization_factor => 10,
differential_drive => 0,
implement_in_les => "OFF",
inclock_boost => 0,
inclock_data_alignment => "EDGE_ALIGNED",
inclock_period => 8000,
inclock_phase_shift => 0,
intended_device_family => "Stratix IV",
lpm_hint => "UNUSED",
lpm_type => "altlvds_tx",
multi_clock => "OFF",
number_of_channels => 1,
outclock_alignment => "EDGE_ALIGNED",
outclock_divide_by => 10,
outclock_duty_cycle => 50,
outclock_multiply_by => 1,
outclock_phase_shift => 0,
outclock_resource => "AUTO",
output_data_rate => 1250,
pll_self_reset_on_loss_lock => "OFF",
preemphasis_setting => 0,
--refclk_frequency => "125.00 MHz",
registered_input => "TX_CORECLK",
use_external_pll => "OFF",
use_no_phase_shift => "ON",
vod_setting => 0
)
port map (
pll_areset => rst_125, --pll_areset_int,
tx_in => tx_in_int,
tx_inclock => clk_125,
tx_out => tx_out_int,
tx_locked => tx_locked_int,
tx_coreclock => tx_pll_clk_int,
sync_inclock => '0',
--tx_data_reset => '0',
tx_enable => '1',
tx_outclock => open,
tx_pll_enable => '1',
tx_syncclock => '0'
);
end architecture ;
| gpl-3.0 | e253e22ddb3ca2539bddf77a82c927a8 | 0.566139 | 2.753475 | false | false | false | false |
EliasLuiz/TCC | Leon3/designs/leon3-xilinx-sp601/config.vhd | 1 | 8,132 |
-----------------------------------------------------------------------------
-- LEON3 Demonstration design test bench configuration
-- Copyright (C) 2009 Aeroflex Gaisler
------------------------------------------------------------------------------
library techmap;
use techmap.gencomp.all;
package config is
-- Technology and synthesis options
constant CFG_FABTECH : integer := spartan6;
constant CFG_MEMTECH : integer := spartan6;
constant CFG_PADTECH : integer := spartan6;
constant CFG_TRANSTECH : integer := GTP0;
constant CFG_NOASYNC : integer := 0;
constant CFG_SCAN : integer := 0;
-- Clock generator
constant CFG_CLKTECH : integer := spartan6;
constant CFG_CLKMUL : integer := (18);
constant CFG_CLKDIV : integer := (9);
constant CFG_OCLKDIV : integer := 1;
constant CFG_OCLKBDIV : integer := 0;
constant CFG_OCLKCDIV : integer := 0;
constant CFG_PCIDLL : integer := 0;
constant CFG_PCISYSCLK: integer := 0;
constant CFG_CLK_NOFB : integer := 0;
-- LEON3 processor core
constant CFG_LEON3 : integer := 1;
constant CFG_NCPU : integer := (1);
constant CFG_NWIN : integer := (8);
constant CFG_V8 : integer := 16#32# + 4*0;
constant CFG_MAC : integer := 0;
constant CFG_BP : integer := 1;
constant CFG_SVT : integer := 1;
constant CFG_RSTADDR : integer := 16#00000#;
constant CFG_LDDEL : integer := (1);
constant CFG_NOTAG : integer := 1;
constant CFG_NWP : integer := (0);
constant CFG_PWD : integer := 1*2;
constant CFG_FPU : integer := 0 + 16*0 + 32*0;
constant CFG_GRFPUSH : integer := 0;
constant CFG_ICEN : integer := 1;
constant CFG_ISETS : integer := 1;
constant CFG_ISETSZ : integer := 8;
constant CFG_ILINE : integer := 8;
constant CFG_IREPL : integer := 0;
constant CFG_ILOCK : integer := 0;
constant CFG_ILRAMEN : integer := 0;
constant CFG_ILRAMADDR: integer := 16#8E#;
constant CFG_ILRAMSZ : integer := 1;
constant CFG_DCEN : integer := 1;
constant CFG_DSETS : integer := 1;
constant CFG_DSETSZ : integer := 4;
constant CFG_DLINE : integer := 4;
constant CFG_DREPL : integer := 0;
constant CFG_DLOCK : integer := 0;
constant CFG_DSNOOP : integer := 0 + 0*2 + 4*0;
constant CFG_DFIXED : integer := 16#0#;
constant CFG_DLRAMEN : integer := 0;
constant CFG_DLRAMADDR: integer := 16#8F#;
constant CFG_DLRAMSZ : integer := 1;
constant CFG_MMUEN : integer := 1;
constant CFG_ITLBNUM : integer := 8;
constant CFG_DTLBNUM : integer := 8;
constant CFG_TLB_TYPE : integer := 0 + 1*2;
constant CFG_TLB_REP : integer := 0;
constant CFG_MMU_PAGE : integer := 0;
constant CFG_DSU : integer := 1;
constant CFG_ITBSZ : integer := 2 + 64*0;
constant CFG_ATBSZ : integer := 2;
constant CFG_AHBPF : integer := 0;
constant CFG_LEON3FT_EN : integer := 0;
constant CFG_IUFT_EN : integer := 0;
constant CFG_FPUFT_EN : integer := 0;
constant CFG_RF_ERRINJ : integer := 0;
constant CFG_CACHE_FT_EN : integer := 0;
constant CFG_CACHE_ERRINJ : integer := 0;
constant CFG_LEON3_NETLIST: integer := 0;
constant CFG_DISAS : integer := 0 + 0;
constant CFG_PCLOW : integer := 2;
constant CFG_STAT_ENABLE : integer := 0;
constant CFG_STAT_CNT : integer := 1;
constant CFG_STAT_NMAX : integer := 0;
constant CFG_STAT_DSUEN : integer := 0;
constant CFG_NP_ASI : integer := 0;
constant CFG_WRPSR : integer := 0;
constant CFG_ALTWIN : integer := 0;
constant CFG_REX : integer := 0;
-- AMBA settings
constant CFG_DEFMST : integer := (0);
constant CFG_RROBIN : integer := 1;
constant CFG_SPLIT : integer := 0;
constant CFG_FPNPEN : integer := 0;
constant CFG_AHBIO : integer := 16#FFF#;
constant CFG_APBADDR : integer := 16#800#;
constant CFG_AHB_MON : integer := 0;
constant CFG_AHB_MONERR : integer := 0;
constant CFG_AHB_MONWAR : integer := 0;
constant CFG_AHB_DTRACE : integer := 0;
-- DSU UART
constant CFG_AHB_UART : integer := 0;
-- JTAG based DSU interface
constant CFG_AHB_JTAG : integer := 1;
-- Ethernet DSU
constant CFG_DSU_ETH : integer := 0 + 0 + 0;
constant CFG_ETH_BUF : integer := 1;
constant CFG_ETH_IPM : integer := 16#C0A8#;
constant CFG_ETH_IPL : integer := 16#0033#;
constant CFG_ETH_ENM : integer := 16#020000#;
constant CFG_ETH_ENL : integer := 16#000009#;
-- LEON2 memory controller
constant CFG_MCTRL_LEON2 : integer := 1;
constant CFG_MCTRL_RAM8BIT : integer := 1;
constant CFG_MCTRL_RAM16BIT : integer := 0;
constant CFG_MCTRL_5CS : integer := 0;
constant CFG_MCTRL_SDEN : integer := 0;
constant CFG_MCTRL_SEPBUS : integer := 0;
constant CFG_MCTRL_INVCLK : integer := 0;
constant CFG_MCTRL_SD64 : integer := 0;
constant CFG_MCTRL_PAGE : integer := 0 + 0;
-- DDR controller
constant CFG_DDR2SP : integer := 0;
constant CFG_DDR2SP_INIT : integer := 0;
constant CFG_DDR2SP_FREQ : integer := 100;
constant CFG_DDR2SP_TRFC : integer := 130;
constant CFG_DDR2SP_DATAWIDTH : integer := 64;
constant CFG_DDR2SP_FTEN : integer := 0;
constant CFG_DDR2SP_FTWIDTH : integer := 0;
constant CFG_DDR2SP_COL : integer := 9;
constant CFG_DDR2SP_SIZE : integer := 8;
constant CFG_DDR2SP_DELAY0 : integer := 0;
constant CFG_DDR2SP_DELAY1 : integer := 0;
constant CFG_DDR2SP_DELAY2 : integer := 0;
constant CFG_DDR2SP_DELAY3 : integer := 0;
constant CFG_DDR2SP_DELAY4 : integer := 0;
constant CFG_DDR2SP_DELAY5 : integer := 0;
constant CFG_DDR2SP_DELAY6 : integer := 0;
constant CFG_DDR2SP_DELAY7 : integer := 0;
constant CFG_DDR2SP_NOSYNC : integer := 0;
-- Xilinx MIG
constant CFG_MIG_DDR2 : integer := 1;
constant CFG_MIG_RANKS : integer := (1);
constant CFG_MIG_COLBITS : integer := (10);
constant CFG_MIG_ROWBITS : integer := (13);
constant CFG_MIG_BANKBITS: integer := (2);
constant CFG_MIG_HMASK : integer := 16#F00#;
-- AHB ROM
constant CFG_AHBROMEN : integer := 0;
constant CFG_AHBROPIP : integer := 0;
constant CFG_AHBRODDR : integer := 16#000#;
constant CFG_ROMADDR : integer := 16#000#;
constant CFG_ROMMASK : integer := 16#E00# + 16#000#;
-- AHB RAM
constant CFG_AHBRAMEN : integer := 0;
constant CFG_AHBRSZ : integer := 1;
constant CFG_AHBRADDR : integer := 16#A00#;
constant CFG_AHBRPIPE : integer := 0;
-- Gaisler Ethernet core
constant CFG_GRETH : integer := 1;
constant CFG_GRETH1G : integer := 0;
constant CFG_ETH_FIFO : integer := 32;
-- UART 1
constant CFG_UART1_ENABLE : integer := 1;
constant CFG_UART1_FIFO : integer := 4;
-- LEON3 interrupt controller
constant CFG_IRQ3_ENABLE : integer := 1;
constant CFG_IRQ3_NSEC : integer := 0;
-- Modular timer
constant CFG_GPT_ENABLE : integer := 1;
constant CFG_GPT_NTIM : integer := (2);
constant CFG_GPT_SW : integer := (8);
constant CFG_GPT_TW : integer := (32);
constant CFG_GPT_IRQ : integer := (8);
constant CFG_GPT_SEPIRQ : integer := 1;
constant CFG_GPT_WDOGEN : integer := 0;
constant CFG_GPT_WDOG : integer := 16#0#;
-- GPIO port
constant CFG_GRGPIO_ENABLE : integer := 1;
constant CFG_GRGPIO_IMASK : integer := 16#0000#;
constant CFG_GRGPIO_WIDTH : integer := (8);
-- SPI memory controller
constant CFG_SPIMCTRL : integer := 0;
constant CFG_SPIMCTRL_SDCARD : integer := 0;
constant CFG_SPIMCTRL_READCMD : integer := 16#0#;
constant CFG_SPIMCTRL_DUMMYBYTE : integer := 0;
constant CFG_SPIMCTRL_DUALOUTPUT : integer := 0;
constant CFG_SPIMCTRL_SCALER : integer := 1;
constant CFG_SPIMCTRL_ASCALER : integer := 1;
constant CFG_SPIMCTRL_PWRUPCNT : integer := 0;
constant CFG_SPIMCTRL_OFFSET : integer := 16#0#;
-- SPI controller
constant CFG_SPICTRL_ENABLE : integer := 0;
constant CFG_SPICTRL_NUM : integer := 1;
constant CFG_SPICTRL_SLVS : integer := 1;
constant CFG_SPICTRL_FIFO : integer := 1;
constant CFG_SPICTRL_SLVREG : integer := 0;
constant CFG_SPICTRL_ODMODE : integer := 0;
constant CFG_SPICTRL_AM : integer := 0;
constant CFG_SPICTRL_ASEL : integer := 0;
constant CFG_SPICTRL_TWEN : integer := 0;
constant CFG_SPICTRL_MAXWLEN : integer := 0;
constant CFG_SPICTRL_SYNCRAM : integer := 0;
constant CFG_SPICTRL_FT : integer := 0;
-- GRLIB debugging
constant CFG_DUART : integer := 0;
end;
| gpl-3.0 | 209a9def52e802102c46de4149c67398 | 0.653837 | 3.571366 | false | false | false | false |
firecake/IRIS | FPGA/VHDL/ipcore_dir/RAM/example_design/RAM_exdes.vhd | 1 | 5,566 |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7.1 Core - Top-level core wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006-2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: RAM_exdes.vhd
--
-- Description:
-- This is the actual BMG core wrapper.
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: August 31, 2005 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY UNISIM;
USE UNISIM.VCOMPONENTS.ALL;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
ENTITY RAM_exdes IS
PORT (
--Inputs - Port A
WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
CLKA : IN STD_LOGIC;
--Inputs - Port B
WEB : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRB : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
DINB : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
DOUTB : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
CLKB : IN STD_LOGIC
);
END RAM_exdes;
ARCHITECTURE xilinx OF RAM_exdes IS
COMPONENT BUFG IS
PORT (
I : IN STD_ULOGIC;
O : OUT STD_ULOGIC
);
END COMPONENT;
COMPONENT RAM IS
PORT (
--Port A
WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
CLKA : IN STD_LOGIC;
--Port B
WEB : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRB : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
DINB : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
DOUTB : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
CLKB : IN STD_LOGIC
);
END COMPONENT;
SIGNAL CLKA_buf : STD_LOGIC;
SIGNAL CLKB_buf : STD_LOGIC;
SIGNAL S_ACLK_buf : STD_LOGIC;
BEGIN
bufg_A : BUFG
PORT MAP (
I => CLKA,
O => CLKA_buf
);
bufg_B : BUFG
PORT MAP (
I => CLKB,
O => CLKB_buf
);
bmg0 : RAM
PORT MAP (
--Port A
WEA => WEA,
ADDRA => ADDRA,
DINA => DINA,
DOUTA => DOUTA,
CLKA => CLKA_buf,
--Port B
WEB => WEB,
ADDRB => ADDRB,
DINB => DINB,
DOUTB => DOUTB,
CLKB => CLKB_buf
);
END xilinx;
| gpl-3.0 | 1717a703ecfd687821b9036d320fc681 | 0.529824 | 4.467095 | false | false | false | false |
EliasLuiz/TCC | Leon3/designs/leon3-gr-xc6s/testbench.vhd | 1 | 12,979 | ----------------------------------------------------------------------------
-- LEON3 Demonstration design test bench
-- Copyright (C) 2004 Jiri Gaisler, Gaisler Research
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library gaisler;
use gaisler.libdcom.all;
use gaisler.sim.all;
library techmap;
use techmap.gencomp.all;
use work.debug.all;
library grlib;
use grlib.stdlib.all;
use work.config.all; -- configuration
entity testbench is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
clktech : integer := CFG_CLKTECH;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW;
clkperiod : integer := 20; -- system clock period
romwidth : integer := 32; -- rom data width (8/32)
romdepth : integer := 16; -- rom address depth
sramwidth : integer := 32; -- ram data width (8/16/32)
sramdepth : integer := 18; -- ram address depth
srambanks : integer := 2 -- number of ram banks
);
end;
architecture behav of testbench is
constant promfile : string := "prom.srec"; -- rom contents
constant sramfile : string := "ram.srec"; -- ram contents
constant sdramfile : string := "ram.srec"; -- sdram contents
signal clk : std_logic := '0';
signal Rst : std_logic := '0'; -- Reset
constant ct : integer := clkperiod/2;
signal address : std_logic_vector(24 downto 0);
signal data : std_logic_vector(31 downto 24);
signal pio : std_logic_vector(17 downto 0);
signal genio : std_logic_vector(59 downto 0);
signal romsn : std_logic;
signal oen : std_ulogic;
signal writen : std_ulogic;
signal GND : std_ulogic := '0';
signal VCC : std_ulogic := '1';
signal NC : std_ulogic := 'Z';
signal wdogn,wdogn_local : std_logic;
signal txd1, rxd1 : std_logic;
signal txd2, rxd2 : std_logic;
signal ctsn1, rtsn1 : std_ulogic;
signal ctsn2, rtsn2 : std_ulogic;
signal erx_dv, erx_dv_d, etx_en: std_logic:='0';
signal erxd, erxd_d, etxd: std_logic_vector(7 downto 0):=(others=>'0');
signal emdc, emdio: std_logic; --dummy signal for the mdc,mdio in the phy which is not used
signal emdint : std_ulogic;
signal etx_clk : std_ulogic;
signal erx_clk : std_ulogic := '0';
signal ps2clk : std_logic_vector(1 downto 0);
signal ps2data : std_logic_vector(1 downto 0);
signal clk2 : std_ulogic := '0';
signal clk125 : std_ulogic := '0';
signal iic_scl : std_ulogic;
signal iic_sda : std_ulogic;
signal ddc_scl : std_ulogic;
signal ddc_sda : std_ulogic;
signal dvi_iic_scl : std_logic;
signal dvi_iic_sda : std_logic;
signal spw_clk : std_ulogic := '0';
signal spw_rxdp : std_logic_vector(0 to CFG_SPW_NUM-1) := (others => '0');
signal spw_rxdn : std_logic_vector(0 to CFG_SPW_NUM-1) := (others => '0');
signal spw_rxsp : std_logic_vector(0 to CFG_SPW_NUM-1) := (others => '0');
signal spw_rxsn : std_logic_vector(0 to CFG_SPW_NUM-1) := (others => '0');
signal spw_txdp : std_logic_vector(0 to CFG_SPW_NUM-1);
signal spw_txdn : std_logic_vector(0 to CFG_SPW_NUM-1);
signal spw_txsp : std_logic_vector(0 to CFG_SPW_NUM-1);
signal spw_txsn : std_logic_vector(0 to CFG_SPW_NUM-1);
signal tft_lcd_data : std_logic_vector(11 downto 0);
signal tft_lcd_clk_p : std_ulogic;
signal tft_lcd_clk_n : std_ulogic;
signal tft_lcd_hsync : std_ulogic;
signal tft_lcd_vsync : std_ulogic;
signal tft_lcd_de : std_ulogic;
signal tft_lcd_reset_b : std_ulogic;
-- DDR2 memory
signal ddr_clk : std_logic;
signal ddr_clkb : std_logic;
signal ddr_clk_fb : std_logic;
signal ddr_cke : std_logic;
signal ddr_csb : std_logic := '0';
signal ddr_we : std_ulogic; -- write enable
signal ddr_ras : std_ulogic; -- ras
signal ddr_cas : std_ulogic; -- cas
signal ddr_dm : std_logic_vector(1 downto 0); -- dm
signal ddr_dqs : std_logic_vector(1 downto 0); -- dqs
signal ddr_dqsn : std_logic_vector(1 downto 0); -- dqsn
signal ddr_ad : std_logic_vector(12 downto 0); -- address
signal ddr_ba : std_logic_vector(2 downto 0); -- bank address
signal ddr_dq : std_logic_vector(15 downto 0); -- data
signal ddr_dq2 : std_logic_vector(15 downto 0); -- data
signal ddr_odt : std_logic;
signal ddr_rzq : std_logic;
signal ddr_zio : std_logic;
-- SPI flash
signal spi_sel_n : std_ulogic;
signal spi_clk : std_ulogic;
signal spi_mosi : std_ulogic;
signal dsurst : std_ulogic;
signal errorn : std_logic;
signal switch : std_logic_vector(9 downto 0); -- I/O port
signal led : std_logic_vector(3 downto 0); -- I/O port
signal erx_er : std_logic := '0';
signal erx_col : std_logic := '0';
signal erx_crs : std_logic := '1';
signal etx_er : std_logic := '0';
constant lresp : boolean := false;
begin
-- clock and reset
clk <= not clk after ct * 1 ns;
clk125 <= not clk125 after 10 ns;
--erx_clk <= not erx_clk after 4 ns;
clk2 <= '0'; --not clk2 after 5 ns;
rst <= dsurst and wdogn_local;
rxd1 <= 'H'; ctsn1 <= '0';
rxd2 <= 'H'; ctsn2 <= '0';
ps2clk <= "HH"; ps2data <= "HH";
pio(4) <= pio(5); pio(1) <= pio(2); pio <= (others => 'H');
wdogn <= 'H';
wdogn_local <= 'H';
switch(7) <= '1';
switch(8) <= '0';
emdio <= 'H';
spw_rxdp <= spw_txdp; spw_rxdn <= spw_txdn;
spw_rxsp <= spw_txsp; spw_rxsn <= spw_txsn;
cpu : entity work.leon3mp
generic map ( fabtech, memtech, padtech, clktech,
disas, dbguart, pclow )
port map (rst, clk, clk2, clk125, wdogn, address(24 downto 0), data,
oen, writen, romsn,
ddr_clk, ddr_clkb, ddr_cke, ddr_odt, ddr_we, ddr_ras, ddr_csb ,ddr_cas, ddr_dm,
ddr_dqs, ddr_dqsn, ddr_ad, ddr_ba, ddr_dq, ddr_rzq, ddr_zio,
txd1, rxd1, ctsn1, rtsn1, txd2, rxd2, ctsn2, rtsn2, pio, genio,
switch, led, erx_clk, emdio, erxd(3 downto 0)'delayed(1 ns), erx_dv'delayed(1 ns), emdint,
etx_clk, etxd(3 downto 0), etx_en, emdc,
ps2clk, ps2data, iic_scl, iic_sda, ddc_scl, ddc_sda,
dvi_iic_scl, dvi_iic_sda,
tft_lcd_data, tft_lcd_clk_p, tft_lcd_clk_n, tft_lcd_hsync,
tft_lcd_vsync, tft_lcd_de, tft_lcd_reset_b,
spw_clk, spw_rxdp, spw_rxdn,
spw_rxsp, spw_rxsn, spw_txdp, spw_txdn, spw_txsp, spw_txsn,
spi_sel_n, spi_clk, spi_mosi
);
prom0 : sram generic map (index => 6, abits => romdepth, fname => promfile)
port map (address(romdepth-1 downto 0), data(31 downto 24), romsn,
writen, oen);
ddr2mem : if (CFG_MIG_DDR2 = 1) generate
u1: ddr2ram
generic map (width => 16, abits => 13, babits => 3,
colbits => 10, rowbits => 13, implbanks => 1,
fname => sdramfile, lddelay => (340 us),
speedbin => 1)
port map (ck => ddr_clk, ckn => ddr_clkb, cke => ddr_cke, csn => ddr_csb,
odt => ddr_odt, rasn => ddr_ras, casn => ddr_cas, wen => ddr_we,
dm => ddr_dm, ba => ddr_ba, a => ddr_ad,
dq => ddr_dq, dqs => ddr_dqs, dqsn => ddr_dqsn);
end generate;
ps2devs: for i in 0 to 1 generate
ps2_device(ps2clk(i), ps2data(i));
end generate ps2devs;
errorn <= led(1);
errorn <= 'H'; -- ERROR pull-up
phy0 : if (CFG_GRETH = 1) generate
emdio <= 'H';
p0: phy
generic map(
address => 1,
extended_regs => 1,
aneg => 1,
base100_t4 => 1,
base100_x_fd => 1,
base100_x_hd => 1,
fd_10 => 1,
hd_10 => 1,
base100_t2_fd => 1,
base100_t2_hd => 1,
base1000_x_fd => 1,
base1000_x_hd => 1,
base1000_t_fd => 1,
base1000_t_hd => 1,
rmii => 0,
rgmii => 1
)
port map(rst, emdio, open, erx_clk, erxd_d, erx_dv_d,
erx_er, erx_col, erx_crs, etxd, etx_en, etx_er, emdc, clk125);
end generate;
rcxclkp : process(erx_clk) is
begin
erxd <= erxd_d;
erx_dv <= erx_dv_d;
end process;
--wdognp : process
-- begin
-- wdogn_local <= 'H';
-- if wdogn = '0' then
-- wdogn_local <= '0';
-- wait for 1 ms;
-- end if;
-- wait for 20 ns;
-- end process;
data <= buskeep(data) after 5 ns;
dsucom : process
procedure dsucfg(signal dsurx : in std_ulogic; signal dsutx : out std_ulogic) is
variable w32 : std_logic_vector(31 downto 0);
variable c8 : std_logic_vector(7 downto 0);
constant txp : time := 320 * 1 ns;
begin
dsutx <= '1';
dsurst <= '0';
wait for 201 us;
wait for 2500 ns;
dsurst <= '1';
wait;
wait for 5000 ns;
txc(dsutx, 16#55#, txp); -- sync uart
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp);
txa(dsutx, 16#00#, 16#00#, 16#20#, 16#2e#, txp);
wait for 25000 ns;
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#01#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#40#, 16#00#, 16#24#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#0D#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#70#, 16#11#, 16#78#, txp);
txa(dsutx, 16#91#, 16#00#, 16#00#, 16#0D#, txp);
txa(dsutx, 16#90#, 16#40#, 16#00#, 16#44#, txp);
txa(dsutx, 16#00#, 16#00#, 16#20#, 16#00#, txp);
txc(dsutx, 16#80#, txp);
txa(dsutx, 16#90#, 16#40#, 16#00#, 16#44#, txp);
wait;
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#00#, 16#00#, 16#0a#, 16#aa#, txp);
txa(dsutx, 16#00#, 16#55#, 16#00#, 16#55#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#00#, 16#00#, 16#0a#, 16#a0#, txp);
txa(dsutx, 16#01#, 16#02#, 16#09#, 16#33#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#2e#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#91#, 16#00#, 16#00#, 16#00#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#2e#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#0f#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#00#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#80#, 16#00#, 16#02#, 16#10#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#0f#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#91#, 16#40#, 16#00#, 16#24#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#24#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#91#, 16#70#, 16#00#, 16#00#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#03#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
txa(dsutx, 16#00#, 16#00#, 16#ff#, 16#ff#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#40#, 16#00#, 16#48#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#12#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#40#, 16#00#, 16#60#, txp);
txa(dsutx, 16#00#, 16#00#, 16#12#, 16#10#, txp);
txc(dsutx, 16#80#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp);
rxi(dsurx, w32, txp, lresp);
txc(dsutx, 16#a0#, txp);
txa(dsutx, 16#40#, 16#00#, 16#00#, 16#00#, txp);
rxi(dsurx, w32, txp, lresp);
end;
begin
dsucfg(txd2, rxd2);
wait;
end process;
iuerr : process
begin
wait until dsurst = '1';
wait for 5000 ns;
if to_x01(errorn) = '1' then wait on errorn; end if;
assert (to_x01(errorn) = '1')
report "*** IU in error mode, simulation halted ***"
severity failure ;
end process;
end ;
| gpl-3.0 | 69d6c7a23a0f3f89ec4739c5cd2d85ba | 0.567917 | 2.992622 | false | false | false | false |
EliasLuiz/TCC | Leon3/lib/techmap/maps/syncreg.vhd | 1 | 2,517 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: syncreg
-- File: syncreg.vhd
-- Author: Aeroflex Gaisler AB
-- Description: Technology wrapper for sync registers
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
entity syncreg is
generic (
tech : integer := 0;
stages : integer range 1 to 5 := 2
);
port (
clk : in std_ulogic;
d : in std_ulogic;
q : out std_ulogic
);
end;
architecture tmap of syncreg is
begin
sync0 : if has_syncreg(tech) = 0 generate
--syncreg : block
-- signal c : std_logic_vector(stages-1 downto 0);
--begin
-- x0 : process(clk)
-- begin
-- if rising_edge(clk) then
-- for i in 0 to stages-1 loop
-- c(i) <= d;
-- if i /= 0 then c(i) = c(i-1); end if;
-- end loop;
-- end if;
-- end process;
-- q <= c(stages-1);
--end block syncreg;
syncreg : block
signal c : std_logic_vector(stages downto 0);
attribute keep : boolean;
attribute keep of c : signal is true;
begin
c(0) <= d;
syncregs : for i in 1 to stages generate
dff : grdff
generic map(tech => tech)
port map(clk => clk, d => c(i-1), q => c(i));
end generate;
q <= c(stages);
end block syncreg;
end generate;
end;
| gpl-3.0 | 2c252866758e45f561b792aab31f1dea | 0.556615 | 4.00159 | false | false | false | false |
EliasLuiz/TCC | Leon3/designs/leon3-altera-ep3c25-eek/leon3mp.vhd | 1 | 32,910 | ------------------------------------------------------------------------------
-- LEON3 Demonstration design
-- Copyright (C) 2008 Jiri Gaisler, Gaisler Research
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
library techmap;
use techmap.gencomp.all;
library gaisler;
use gaisler.memctrl.all;
use gaisler.ddrpkg.all;
use gaisler.leon3.all;
use gaisler.uart.all;
use gaisler.misc.all;
use gaisler.net.all;
use gaisler.jtag.all;
use gaisler.i2c.all;
use gaisler.spi.all;
library esa;
use esa.memoryctrl.all;
use work.config.all;
entity leon3mp is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
clktech : integer := CFG_CLKTECH;
ncpu : integer := CFG_NCPU;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW;
freq : integer := 50000 -- frequency of main clock (used for PLLs)
);
port (
resetn : in std_ulogic;
clk : in std_ulogic;
errorn : out std_ulogic;
-- flash/ssram bus
address : out std_logic_vector(25 downto 1);
data : inout std_logic_vector(31 downto 0);
romsn : out std_ulogic;
oen : out std_logic;
writen : out std_logic;
rstoutn : out std_ulogic;
ssram_cen : out std_logic;
ssram_wen : out std_logic;
ssram_bw : out std_logic_vector (0 to 3);
ssram_oen : out std_ulogic;
ssram_clk : out std_ulogic;
ssram_adscn : out std_ulogic;
-- ssram_adsp_n : out std_ulogic;
-- ssram_adv_n : out std_ulogic;
-- pragma translate_off
iosn : out std_ulogic;
-- pragma translate_on
-- DDR
ddr_clk : out std_logic;
ddr_clkn : out std_logic;
ddr_cke : out std_logic;
ddr_csb : out std_logic;
ddr_web : out std_ulogic; -- ddr write enable
ddr_rasb : out std_ulogic; -- ddr ras
ddr_casb : out std_ulogic; -- ddr cas
ddr_dm : out std_logic_vector (1 downto 0); -- ddr dm
ddr_dqs : inout std_logic_vector (1 downto 0); -- ddr dqs
ddr_ad : out std_logic_vector (12 downto 0); -- ddr address
ddr_ba : out std_logic_vector (1 downto 0); -- ddr bank address
ddr_dq : inout std_logic_vector (15 downto 0); -- ddr data
-- debug support unit
dsubren : in std_ulogic;
dsuact : out std_ulogic;
-- I/O port
gpio : in std_logic_vector(CFG_GRGPIO_WIDTH-3 downto 0);
-- Connections over HSMC connector
-- LCD touch panel display
hc_vd : out std_logic;
hc_hd : out std_logic;
hc_den : out std_logic;
hc_nclk : out std_logic;
hc_lcd_data : out std_logic_vector(7 downto 0);
hc_grest : out std_logic;
hc_scen : out std_logic;
hc_sda : inout std_logic;
hc_adc_penirq_n : in std_logic;
hc_adc_dout : in std_logic;
hc_adc_busy : in std_logic;
hc_adc_din : out std_logic;
hc_adc_dclk : out std_logic;
hc_adc_cs_n : out std_logic; -- Shared with video decoder
-- Shared by video decoder and audio codec
hc_i2c_sclk : out std_logic;
hc_i2c_sdat : inout std_logic;
-- Video decoder
hc_td_d : inout std_logic_vector(7 downto 0);
hc_td_hs : in std_logic;
hc_td_vs : in std_logic;
hc_td_27mhz : in std_logic;
hc_td_reset : out std_logic;
-- Audio codec
hc_aud_adclrck : out std_logic;
hc_aud_adcdat : in std_logic;
hc_aud_daclrck : out std_logic;
hc_aud_dacdat : out std_logic;
hc_aud_bclk : out std_logic;
hc_aud_xck : out std_logic;
-- SD card
hc_sd_dat : inout std_logic;
hc_sd_dat3 : inout std_logic;
hc_sd_cmd : inout std_logic;
hc_sd_clk : inout std_logic;
-- Ethernet PHY
hc_tx_d : out std_logic_vector(3 downto 0);
hc_rx_d : in std_logic_vector(3 downto 0);
hc_tx_clk : in std_logic;
hc_rx_clk : in std_logic;
hc_tx_en : out std_logic;
hc_rx_dv : in std_logic;
hc_rx_crs : in std_logic;
hc_rx_err : in std_logic;
hc_rx_col : in std_logic;
hc_mdio : inout std_logic;
hc_mdc : out std_logic;
hc_eth_reset_n : out std_logic;
-- RX232 (console/debug UART)
hc_uart_rxd : in std_logic;
hc_uart_txd : out std_logic;
-- PS/2
hc_ps2_dat : inout std_logic;
hc_ps2_clk : inout std_logic;
-- VGA/DAC
hc_vga_data : out std_logic_vector(9 downto 0);
hc_vga_clock : out std_ulogic;
hc_vga_hs : out std_ulogic;
hc_vga_vs : out std_ulogic;
hc_vga_blank : out std_ulogic;
hc_vga_sync : out std_ulogic;
-- I2C EEPROM
hc_id_i2cscl : out std_logic;
hc_id_i2cdat : inout std_logic
);
end;
architecture rtl of leon3mp is
component serializer
generic (
length : integer := 8 -- vector length
);
port (
clk : in std_ulogic;
sync : in std_ulogic;
ivec0 : in std_logic_vector((length-1) downto 0);
ivec1 : in std_logic_vector((length-1) downto 0);
ivec2 : in std_logic_vector((length-1) downto 0);
ovec : out std_logic_vector((length-1) downto 0)
);
end component;
component altera_eek_clkgen
generic (
clk0_mul : integer := 1;
clk0_div : integer := 1;
clk1_mul : integer := 1;
clk1_div : integer := 1;
clk_freq : integer := 25000);
port (
inclk0 : in std_ulogic;
clk0 : out std_ulogic;
clk0x3 : out std_ulogic;
clksel : in std_logic_vector(1 downto 0);
locked : out std_ulogic);
end component;
constant blength : integer := 12;
constant fifodepth : integer := 8;
constant maxahbm : integer := NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_LCD_ENABLE+
CFG_SVGA_ENABLE+CFG_GRETH;
signal vcc, gnd : std_logic_vector(7 downto 0);
signal memi, smemi : memory_in_type;
signal memo, smemo : memory_out_type;
signal wpo : wprot_out_type;
signal ddrclkfb, ssrclkfb, ddr_clkl, ddr_clk90l, ddr_clknl, ddr_clk270l : std_ulogic;
signal ddr_clkv : std_logic_vector(2 downto 0);
signal ddr_clkbv : std_logic_vector(2 downto 0);
signal ddr_ckev : std_logic_vector(1 downto 0);
signal ddr_csbv : std_logic_vector(1 downto 0);
signal ddr_adl : std_logic_vector (13 downto 0);
signal clklock, lock, clkml, rst, ndsuact : std_ulogic;
signal tck, tckn, tms, tdi, tdo : std_ulogic;
signal ddrclk, ddrrst : std_ulogic;
signal apbi : apb_slv_in_type;
signal apbo : apb_slv_out_vector := (others => apb_none);
signal ahbsi : ahb_slv_in_type;
signal ahbso : ahb_slv_out_vector := (others => ahbs_none);
signal ahbmi : ahb_mst_in_type;
signal ahbmo : ahb_mst_out_vector := (others => ahbm_none);
signal clkm, rstn, rawrstn, ssram_clkl : std_ulogic;
signal cgi : clkgen_in_type;
signal cgo : clkgen_out_type;
signal u1i, dui : uart_in_type;
signal u1o, duo : uart_out_type;
signal irqi : irq_in_vector(0 to NCPU-1);
signal irqo : irq_out_vector(0 to NCPU-1);
signal dbgi : l3_debug_in_vector(0 to NCPU-1);
signal dbgo : l3_debug_out_vector(0 to NCPU-1);
signal dsui : dsu_in_type;
signal dsuo : dsu_out_type;
signal gpti : gptimer_in_type;
signal gpioi : gpio_in_type;
signal gpioo : gpio_out_type;
signal ps2i : ps2_in_type;
signal ps2o : ps2_out_type;
signal i2ci : i2c_in_type;
signal i2co : i2c_out_type;
signal spii : spi_in_type;
signal spio : spi_out_type;
signal slvsel : std_logic_vector(CFG_SPICTRL_SLVS-1 downto 0);
signal ethi : eth_in_type;
signal etho : eth_out_type;
signal lcdo : apbvga_out_type;
signal lcd_data : std_logic_vector(7 downto 0);
signal lcd_den : std_ulogic;
signal lcd_grest : std_ulogic;
signal lcdspii : spi_in_type;
signal lcdspio : spi_out_type;
signal lcdslvsel : std_logic_vector(1 downto 0);
signal lcdclksel : std_logic_vector(1 downto 0);
signal lcdclk : std_ulogic;
signal lcdclk3x : std_ulogic;
signal lcdclklck : std_ulogic;
signal vgao : apbvga_out_type;
signal vga_data : std_logic_vector(9 downto 0);
signal vgaclksel : std_logic_vector(1 downto 0);
signal vgaclk : std_ulogic;
signal vgaclk3x : std_ulogic;
signal vgaclklck : std_ulogic;
constant IOAEN : integer := 1;
constant BOARD_FREQ : integer := 50000; -- input frequency in KHz
constant CPU_FREQ : integer := BOARD_FREQ * CFG_CLKMUL / CFG_CLKDIV; -- cpu frequency in KHz
constant I2C_FILTER : integer := (CPU_FREQ*5+50000)/100000+1;
signal lclk, lclkout : std_ulogic;
signal dsubre : std_ulogic;
attribute syn_keep : boolean;
attribute syn_keep of clkm : signal is true;
attribute syn_keep of clkml : signal is true;
attribute syn_keep of lcdclk : signal is true;
attribute syn_keep of lcdclk3x : signal is true;
attribute syn_keep of vgaclk : signal is true;
attribute syn_keep of vgaclk3x : signal is true;
begin
----------------------------------------------------------------------
--- Reset and Clock generation -------------------------------------
----------------------------------------------------------------------
vcc <= (others => '1'); gnd <= (others => '0');
cgi.pllctrl <= "00"; cgi.pllrst <= not resetn; cgi.pllref <= '0';
clklock <= cgo.clklock and lock and lcdclklck and vgaclklck;
clk_pad : clkpad generic map (tech => padtech) port map (clk, lclk);
clkgen0 : clkgen -- clock generator using toplevel generic 'freq'
generic map (tech => CFG_CLKTECH, clk_mul => CFG_CLKMUL,
clk_div => CFG_CLKDIV, sdramen => 1,
freq => freq)
port map (clkin => lclk, pciclkin => gnd(0), clk => clkm, clkn => open,
clk2x => open, sdclk => ssram_clkl, pciclk => open,
cgi => cgi, cgo => cgo);
ssrclk_pad : outpad generic map (tech => padtech, slew => 1, strength => 24)
port map (ssram_clk, ssram_clkl);
rst0 : rstgen -- reset generator
port map (resetn, clkm, clklock, rstn, rawrstn);
rstoutn <= resetn;
----------------------------------------------------------------------
--- AVOID BUS CONTENTION --------------------------------------------
----------------------------------------------------------------------
-- This design uses the ethernet PHY and we must therefore disable the
-- video decoder and stay away from the touch panel.
-- Video coder
hc_td_reset <= '0'; -- Video Decoder Reset
----------------------------------------------------------------------
--- AHB CONTROLLER --------------------------------------------------
----------------------------------------------------------------------
ahb0 : ahbctrl -- AHB arbiter/multiplexer
generic map (defmast => CFG_DEFMST, split => CFG_SPLIT,
rrobin => CFG_RROBIN, ioaddr => CFG_AHBIO,
ioen => IOAEN, nahbm => maxahbm, nahbs => 8)
port map (rstn, clkm, ahbmi, ahbmo, ahbsi, ahbso);
----------------------------------------------------------------------
--- LEON3 processor and DSU -----------------------------------------
----------------------------------------------------------------------
l3 : if CFG_LEON3 = 1 generate
cpu : for i in 0 to NCPU-1 generate
u0 : leon3s -- LEON3 processor
generic map (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU, CFG_V8,
0, CFG_MAC, pclow, CFG_NOTAG, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE,
CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ,
CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN,
CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP,
CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR, NCPU-1,
CFG_DFIXED, CFG_SCAN, CFG_MMU_PAGE, CFG_BP, CFG_NP_ASI, CFG_WRPSR)
port map (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso,
irqi(i), irqo(i), dbgi(i), dbgo(i));
end generate;
errorn_pad : outpad generic map (tech => padtech) port map (errorn, dbgo(0).error);
dsugen : if CFG_DSU = 1 generate
dsu0 : dsu3 -- LEON3 Debug Support Unit
generic map (hindex => 2, haddr => 16#900#, hmask => 16#F00#,
ncpu => NCPU, tbits => 30, tech => memtech, irq => 0, kbytes => CFG_ATBSZ)
port map (rstn, clkm, ahbmi, ahbsi, ahbso(2), dbgo, dbgi, dsui, dsuo);
dsui.enable <= '1';
dsubre_pad : inpad generic map (tech => padtech) port map (dsubre, dsui.break);
dsuact_pad : outpad generic map (tech => padtech) port map (dsuact, dsuo.active);
end generate;
end generate;
nodsu : if CFG_DSU = 0 generate
ahbso(2) <= ahbs_none; dsuo.tstop <= '0'; dsuo.active <= '0';
end generate;
dcomgen : if CFG_AHB_UART = 1 generate
dcom0 : ahbuart -- Debug UART
generic map (hindex => NCPU, pindex => 7, paddr => 7)
port map (rstn, clkm, dui, duo, apbi, apbo(7), ahbmi, ahbmo(NCPU));
dsurx_pad : inpad generic map (tech => padtech) port map (hc_uart_rxd, dui.rxd);
dsutx_pad : outpad generic map (tech => padtech) port map (hc_uart_txd, duo.txd);
end generate;
nouah : if CFG_AHB_UART = 0 generate apbo(7) <= apb_none; end generate;
ahbjtaggen0 :if CFG_AHB_JTAG = 1 generate
ahbjtag0 : ahbjtag generic map(tech => fabtech, hindex => NCPU+CFG_AHB_UART)
port map(rstn, clkm, tck, tms, tdi, tdo, ahbmi, ahbmo(NCPU+CFG_AHB_UART),
open, open, open, open, open, open, open, gnd(0));
end generate;
----------------------------------------------------------------------
--- Memory controllers ----------------------------------------------
----------------------------------------------------------------------
mg2 : if CFG_MCTRL_LEON2 = 1 generate -- LEON2 memory controller
sr1 :mctrl generic map (hindex => 0, pindex => 0, paddr => 0,
ramaddr => 16#400#+16#600#*CFG_DDRSP, rammask =>16#F00#, srbanks => 1,
sden => 0, ram16 => 1)
port map (rstn, clkm, memi, memo, ahbsi, ahbso(0), apbi, apbo(0), wpo);
end generate;
memi.brdyn <= '1'; memi.bexcn <= '1';
memi.writen <= '1'; memi.wrn <= "1111"; memi.bwidth <= "01";
ssr0 : if CFG_SSCTRL = 1 generate
ssrctrl0 : ssrctrl generic map (hindex => 0, pindex => 0,
iomask => 0, ramaddr => 16#400#+16#600#*CFG_DDRSP,
bus16 => CFG_SSCTRLP16)
port map (rstn, clkm, ahbsi, ahbso(0), apbi, apbo(0), memi, memo);
end generate;
mg0 : if (CFG_MCTRL_LEON2 + CFG_SSCTRL) = 0 generate -- no prom/sram pads
apbo(0) <= apb_none; ahbso(0) <= ahbs_none;
roms_pad : outpad generic map (tech => padtech) port map (romsn, vcc(0));
end generate;
mgpads : if (CFG_MCTRL_LEON2 + CFG_SSCTRL) /= 0 generate -- prom/sram pads
addr_pad : outpadv generic map (width => 25, tech => padtech)
port map (address, memo.address(25 downto 1));
roms_pad : outpad generic map (tech => padtech)
port map (romsn, memo.romsn(0));
oen_pad : outpad generic map (tech => padtech)
port map (oen, memo.oen);
wri_pad : outpad generic map (tech => padtech)
port map (writen, memo.writen);
-- pragma translate_off
iosn_pad : outpad generic map (tech => padtech)
port map (iosn, memo.iosn);
-- pragma translate_on
-- ssram_adv_n_pad : outpad generic map (tech => padtech)
-- port map (ssram_adv_n, vcc(0));
-- ssram_adsp_n_pad : outpad generic map (tech => padtech)
-- port map (ssram_adsp_n, gnd(0));
ssram_adscn_pad : outpad generic map (tech => padtech)
port map (ssram_adscn, gnd(0));
ssrams_pad : outpad generic map ( tech => padtech)
port map (ssram_cen, memo.ramsn(0));
ssram_oen_pad : outpad generic map (tech => padtech)
port map (ssram_oen, memo.oen);
ssram_rwen_pad : outpadv generic map (width => 4, tech => padtech)
port map (ssram_bw, memo.wrn);
ssram_wri_pad : outpad generic map (tech => padtech)
port map (ssram_wen, memo.writen);
data_pad : iopadvv generic map (tech => padtech, width => 32)
port map (data(31 downto 0), memo.data(31 downto 0),
memo.vbdrive, memi.data(31 downto 0));
end generate;
ddrsp0 : if (CFG_DDRSP /= 0) generate
ddrc0 : ddrspa generic map ( fabtech => fabtech, memtech => memtech,
hindex => 3, haddr => 16#400#, hmask => 16#F00#, ioaddr => 1,
pwron => CFG_DDRSP_INIT, MHz => BOARD_FREQ/1000, rskew => CFG_DDRSP_RSKEW,
clkmul => CFG_DDRSP_FREQ/5, clkdiv => 10, ahbfreq => CPU_FREQ/1000,
col => CFG_DDRSP_COL, Mbyte => CFG_DDRSP_SIZE, ddrbits => 16, regoutput => 1)
port map (
resetn, rstn, lclk, clkm, lock, clkml, clkml, ahbsi, ahbso(3),
ddr_clkv, ddr_clkbv, open, gnd(0),
ddr_ckev, ddr_csbv, ddr_web, ddr_rasb, ddr_casb,
ddr_dm, ddr_dqs, ddr_adl, ddr_ba, ddr_dq);
ddr_ad <= ddr_adl(12 downto 0);
ddr_clk <= ddr_clkv(0); ddr_clkn <= ddr_clkbv(0);
ddr_cke <= ddr_ckev(0); ddr_csb <= ddr_csbv(0);
end generate;
ddrsp1 : if (CFG_DDRSP = 0) generate
ddr_cke <= '0'; ddr_csb <= '1'; lock <= '1';
end generate;
----------------------------------------------------------------------
--- APB Bridge and various periherals -------------------------------
----------------------------------------------------------------------
apb0 : apbctrl -- AHB/APB bridge
generic map (hindex => 1, haddr => CFG_APBADDR)
port map (rstn, clkm, ahbsi, ahbso(1), apbi, apbo);
ua1 : if CFG_UART1_ENABLE /= 0 generate
uart1 : apbuart -- UART 1
generic map (pindex => 1, paddr => 1, pirq => 2, console => dbguart,
fifosize => CFG_UART1_FIFO)
port map (rstn, clkm, apbi, apbo(1), u1i, u1o);
u1i.ctsn <= '0'; u1i.extclk <= '0';
upads : if CFG_AHB_UART = 0 generate
u1i.rxd <= hc_uart_rxd; hc_uart_txd <= u1o.txd;
end generate;
end generate;
noua0 : if CFG_UART1_ENABLE = 0 generate apbo(1) <= apb_none; end generate;
irqctrl : if CFG_IRQ3_ENABLE /= 0 generate
irqctrl0 : irqmp -- interrupt controller
generic map (pindex => 2, paddr => 2, ncpu => NCPU)
port map (rstn, clkm, apbi, apbo(2), irqo, irqi);
end generate;
irq3 : if CFG_IRQ3_ENABLE = 0 generate
x : for i in 0 to NCPU-1 generate
irqi(i).irl <= "0000";
end generate;
apbo(2) <= apb_none;
end generate;
gpt : if CFG_GPT_ENABLE /= 0 generate
timer0 : gptimer -- Timer unit
generic map (pindex => 3, paddr => 3, pirq => CFG_GPT_IRQ,
sepirq => CFG_GPT_SEPIRQ, sbits => CFG_GPT_SW, ntimers => CFG_GPT_NTIM,
nbits => CFG_GPT_TW)
port map (rstn, clkm, apbi, apbo(3), gpti, open);
gpti <= gpti_dhalt_drive(dsuo.tstop);
end generate;
notim : if CFG_GPT_ENABLE = 0 generate apbo(3) <= apb_none; end generate;
gpio0 : if CFG_GRGPIO_ENABLE /= 0 generate -- GPIO unit
grgpio0: grgpio
generic map(pindex => 5, paddr => 5, imask => CFG_GRGPIO_IMASK, nbits => CFG_GRGPIO_WIDTH)
port map(rst => rstn, clk => clkm, apbi => apbi, apbo => apbo(5),
gpioi => gpioi, gpioo => gpioo);
pio_pads : for i in 0 to CFG_GRGPIO_WIDTH-3 generate
gpioi.din(i) <= gpio(i);
end generate;
gpioi.din(3) <= hc_adc_penirq_n;
gpioi.din(4) <= hc_adc_busy;
end generate;
ps2 : if CFG_PS2_ENABLE /= 0 generate -- PS/2 unit
ps20 : apbps2 generic map(pindex => 6, paddr => 6, pirq => 6)
port map(rstn, clkm, apbi, apbo(6), ps2i, ps2o);
end generate;
nops2 : if CFG_PS2_ENABLE = 0 generate
apbo(4) <= apb_none; ps2o <= ps2o_none;
end generate;
ps2clk_pad : iopad generic map (tech => padtech)
port map (hc_ps2_clk, ps2o.ps2_clk_o, ps2o.ps2_clk_oe, ps2i.ps2_clk_i);
ps2data_pad : iopad generic map (tech => padtech)
port map (hc_ps2_dat, ps2o.ps2_data_o, ps2o.ps2_data_oe, ps2i.ps2_data_i);
i2cm: if CFG_I2C_ENABLE = 1 generate -- I2C master
i2c0 : i2cmst
generic map (pindex => 8, paddr => 8, pmask => 16#FFF#,
pirq => 11, filter => I2C_FILTER)
port map (rstn, clkm, apbi, apbo(8), i2ci, i2co);
-- The EEK does not use a bi-directional line for the I2C clock
i2ci.scl <= i2co.scloen; -- No clock stretch possible
-- When SCL output enable is activated the line should go low
i2c_scl_pad : outpad generic map (tech => padtech)
port map (hc_id_i2cscl, i2co.scloen);
i2c_sda_pad : iopad generic map (tech => padtech)
port map (hc_id_i2cdat, i2co.sda, i2co.sdaoen, i2ci.sda);
end generate i2cm;
spic: if CFG_SPICTRL_ENABLE = 1 generate -- SPI controller
spi1 : spictrl
generic map (pindex => 9, paddr => 9, pmask => 16#fff#, pirq => 7,
fdepth => CFG_SPICTRL_FIFO, slvselen => CFG_SPICTRL_SLVREG,
slvselsz => CFG_SPICTRL_SLVS, odmode => 1,
syncram => CFG_SPICTRL_SYNCRAM, ft => CFG_SPICTRL_FT)
port map (rstn, clkm, apbi, apbo(9), spii, spio, slvsel);
miso_pad : iopad generic map (tech => padtech)
port map (hc_sd_dat, spio.miso, spio.misooen, spii.miso);
mosi_pad : iopad generic map (tech => padtech)
port map (hc_sd_cmd, spio.mosi, spio.mosioen, spii.mosi);
sck_pad : iopad generic map (tech => padtech)
port map (hc_sd_clk, spio.sck, spio.sckoen, spii.sck);
slvsel_pad : outpad generic map (tech => padtech)
port map (hc_sd_dat3, slvsel(0));
spii.spisel <= '1'; -- Master only
end generate spic;
-----------------------------------------------------------------------
-- LCD touch panel ---------------------------------------------------
-----------------------------------------------------------------------
lcd: if CFG_LCD_ENABLE /= 0 generate -- LCD
lcd0 : svgactrl generic map(memtech => memtech, pindex => 11, paddr => 11,
hindex => CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG,
clk0 => 30120, clk1 => 0, clk2 => 0, clk3 => 0, burstlen => 4)
port map(rstn, clkm, lcdclk, apbi, apbo(11), lcdo, ahbmi,
ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG), open);
lcdser0: serializer generic map (length => 8)
port map (lcdclk3x, lcdo.hsync, lcdo.video_out_b, lcdo.video_out_g,
lcdo.video_out_r, lcd_data);
lcdclksel <= "00";
lcdclkgen : altera_eek_clkgen
generic map (clk0_mul => 166, clk0_div => 250, clk1_mul => 9,
clk1_div => 50, clk_freq => BOARD_FREQ)
port map (lclk, lcdclk, lcdclk3x, lcdclksel, lcdclklck);
lcd_vert_sync_pad : outpad generic map (tech => padtech)
port map (hc_vd, lcdo.vsync);
lcd_horiz_sync_pad : outpad generic map (tech => padtech)
port map (hc_hd, lcdo.hsync);
lcd_video_out_pad : outpadv generic map (width => 8, tech => padtech)
port map (hc_lcd_data, lcd_data);
lcd_video_clock_pad : outpad generic map (tech => padtech)
port map (hc_nclk, lcdclk3x);
lcd_den <= lcdo.blank;
end generate;
nolcd : if CFG_LCD_ENABLE = 0 generate
apbo(11) <= apb_none; lcdo <= vgao_none;
lcd_den <= '0'; -- LCD RGB Data Enable
lcdclk <= '0'; lcdclk3x <= '0'; lcdclklck <= '1';
end generate;
lcd_den_pad : outpad generic map (tech => padtech)
port map (hc_den, lcd_den);
lcdsysreset: if CFG_LCD_ENABLE /= 0 or CFG_LCD3T_ENABLE /= 0 generate
lcd_grest <= rstn;
end generate;
lcdalwaysreset: if CFG_LCD_ENABLE = 0 and CFG_LCD3T_ENABLE = 0 generate
lcd_grest <= '0';
end generate lcdalwaysreset;
lcd_reset_pad : outpad generic map (tech => padtech) -- LCD Global Reset, active low
port map (hc_grest, lcd_grest);
touch3wire: if CFG_LCD3T_ENABLE /= 0 generate -- LCD 3-wire and touch panel interface
-- TODO:
-- Interrupt and busy signals not connected
touch3spi1 : spictrl
generic map (pindex => 12, paddr => 12, pmask => 16#fff#, pirq => 12,
fdepth => 2, slvselen => 1, slvselsz => 2, odmode => 0,
syncram => 0, ft => 0)
port map (rstn, clkm, apbi, apbo(12), lcdspii, lcdspio, lcdslvsel);
adc_miso_pad : inpad generic map (tech => padtech)
port map (hc_adc_dout, lcdspii.miso);
adc_mosi_pad : outpad generic map (tech => padtech)
port map (hc_adc_din, lcdspio.mosi);
lcd_adc_dclk_pad : outpad generic map (tech => padtech)
port map (hc_adc_dclk, lcdspio.sck);
hcd_sda_pad : iopad generic map (tech => padtech)
port map (hc_sda, lcdspio.mosi, lcdspio.mosioen, lcdspii.mosi);
lcdspii.spisel <= '1'; -- Master only
end generate;
notouch3wire: if CFG_LCD3T_ENABLE = 0 generate
lcdslvsel <= (others => '1');
apbo(12) <= apb_none;
end generate;
hc_adc_cs_n_pad : outpad generic map (tech => padtech)
port map (hc_adc_cs_n, lcdslvsel(0));
hc_scen_pad : outpad generic map (tech => padtech)
port map (hc_scen, lcdslvsel(1));
-----------------------------------------------------------------------
-- SVGA controller ----------------------------------------------------
-----------------------------------------------------------------------
svga : if CFG_SVGA_ENABLE /= 0 generate -- VGA DAC
svga0 : svgactrl generic map(memtech => memtech, pindex => 13, paddr => 13,
hindex => CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_LCD_ENABLE,
clk0 => 40000, clk1 => 25000, clk2 => 0, clk3 => 0, burstlen => 4)
port map(rstn, clkm, vgaclk, apbi, apbo(13), vgao, ahbmi,
ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_LCD_ENABLE),
vgaclksel);
svgaser0: serializer generic map (length => 8)
port map (vgaclk3x, vgao.hsync, vgao.video_out_b, vgao.video_out_g,
vgao.video_out_r, vga_data(9 downto 2));
vga_data(1 downto 0) <= (others => '0');
vgaclkgen : altera_eek_clkgen
generic map (clk0_mul => 1, clk0_div => 2, clk1_mul => 4,
clk1_div => 5, clk_freq => BOARD_FREQ)
port map (lclk, vgaclk, vgaclk3x, vgaclksel, vgaclklck);
vga_blank_pad : outpad generic map (tech => padtech)
port map (hc_vga_blank, vgao.blank);
vga_comp_sync_pad : outpad generic map (tech => padtech)
port map (hc_vga_sync, vgao.comp_sync);
vga_vert_sync_pad : outpad generic map (tech => padtech)
port map (hc_vga_vs, vgao.vsync);
vga_horiz_sync_pad : outpad generic map (tech => padtech)
port map (hc_vga_hs, vgao.hsync);
vga_video_out_pad : outpadv generic map (width => 10, tech => padtech)
port map (hc_vga_data, vga_data);
vga_video_clock_pad : outpad generic map (tech => padtech)
port map (hc_vga_clock, vgaclk3x);
end generate svga;
nosvga : if CFG_SVGA_ENABLE = 0 generate
apbo(13) <= apb_none; vgao <= vgao_none;
vgaclk <= '0'; vgaclk3x <= '0'; vgaclklck <= '1';
end generate;
-----------------------------------------------------------------------
--- ETHERNET ---------------------------------------------------------
-----------------------------------------------------------------------
eth0 : if CFG_GRETH /= 0 generate -- Gaisler ethernet MAC
e1 : grethm generic map(
hindex => CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_LCD_ENABLE+CFG_SVGA_ENABLE,
pindex => 10, paddr => 10, pirq => 10, memtech => memtech,
mdcscaler => CPU_FREQ/1000, enable_mdio => 1, fifosize => CFG_ETH_FIFO,
nsync => 1, edcl => CFG_DSU_ETH, edclbufsz => CFG_ETH_BUF,
macaddrh => CFG_ETH_ENM, macaddrl => CFG_ETH_ENL, phyrstadr => 1,
ipaddrh => CFG_ETH_IPM, ipaddrl => CFG_ETH_IPL, giga => CFG_GRETH1G)
port map( rst => rstn, clk => clkm, ahbmi => ahbmi,
ahbmo => ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_LCD_ENABLE+CFG_SVGA_ENABLE),
apbi => apbi, apbo => apbo(10), ethi => ethi, etho => etho);
emdio_pad : iopad generic map (tech => padtech)
port map (hc_mdio, etho.mdio_o, etho.mdio_oe, ethi.mdio_i);
etxc_pad : clkpad generic map (tech => padtech, arch => 2)
port map (hc_tx_clk, ethi.tx_clk);
erxc_pad : clkpad generic map (tech => padtech, arch => 2)
port map (hc_rx_clk, ethi.rx_clk);
erxd_pad : inpadv generic map (tech => padtech, width => 4)
port map (hc_rx_d, ethi.rxd(3 downto 0));
erxdv_pad : inpad generic map (tech => padtech)
port map (hc_rx_dv, ethi.rx_dv);
erxer_pad : inpad generic map (tech => padtech)
port map (hc_rx_err, ethi.rx_er);
erxco_pad : inpad generic map (tech => padtech)
port map (hc_rx_col, ethi.rx_col);
erxcr_pad : inpad generic map (tech => padtech)
port map (hc_rx_crs, ethi.rx_crs);
etxd_pad : outpadv generic map (tech => padtech, width => 4)
port map (hc_tx_d, etho.txd(3 downto 0));
etxen_pad : outpad generic map (tech => padtech)
port map (hc_tx_en, etho.tx_en);
emdc_pad : outpad generic map (tech => padtech)
port map (hc_mdc, etho.mdc);
erst_pad : outpad generic map (tech => padtech)
port map (hc_eth_reset_n, rawrstn);
end generate;
-----------------------------------------------------------------------
--- AHB ROM ----------------------------------------------------------
-----------------------------------------------------------------------
bpromgen : if CFG_AHBROMEN /= 0 generate
brom : entity work.ahbrom
generic map (hindex => 6, haddr => CFG_AHBRODDR, pipe => CFG_AHBROPIP)
port map ( rstn, clkm, ahbsi, ahbso(6));
end generate;
nobpromgen : if CFG_AHBROMEN = 0 generate
ahbso(6) <= ahbs_none;
end generate;
-----------------------------------------------------------------------
--- AHB RAM ----------------------------------------------------------
-----------------------------------------------------------------------
ahbramgen : if CFG_AHBRAMEN = 1 generate
ahbram0 : ahbram generic map (hindex => 7, haddr => CFG_AHBRADDR,
tech => CFG_MEMTECH, kbytes => CFG_AHBRSZ, pipe => CFG_AHBRPIPE)
port map (rstn, clkm, ahbsi, ahbso(7));
end generate;
nram : if CFG_AHBRAMEN = 0 generate ahbso(7) <= ahbs_none; end generate;
-----------------------------------------------------------------------
--- Drive unused bus elements ---------------------------------------
-----------------------------------------------------------------------
nam1 : for i in (CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_LCD_ENABLE+CFG_SVGA_ENABLE+CFG_GRETH) to NAHBMST-1 generate
ahbmo(i) <= ahbm_none;
end generate;
-- invert signal for input via a key
dsubre <= not dsubren;
-----------------------------------------------------------------------
--- Boot message ----------------------------------------------------
-----------------------------------------------------------------------
-- pragma translate_off
x : report_design
generic map (
msg1 => "LEON3 Altera Embedded Evaluation Kit Demonstration Design",
fabtech => tech_table(fabtech), memtech => tech_table(memtech),
mdel => 1
);
-- pragma translate_on
end;
| gpl-3.0 | ae42245a6e876d78fb7c2a158dc31f1d | 0.549985 | 3.588485 | false | false | false | false |
GLADICOS/SPACEWIRESYSTEMC | rtl/RTL_VJ/SpaceWireCODECIPFIFO9x64.vhdl | 1 | 11,385 | ------------------------------------------------------------------------------
-- The MIT License (MIT)
--
-- Copyright (c) <2013> <Shimafuji Electric Inc., Osaka University, JAXA>
--
-- Permission is hereby granted, free of charge, to any person obtaining a copy
-- of this software and associated documentation files (the "Software"), to deal
-- in the Software without restriction, including without limitation the rights
-- to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-- copies of the Software, and to permit persons to whom the Software is
-- furnished to do so, subject to the following conditions:
--
-- The above copyright notice and this permission notice shall be included in
-- all copies or substantial portions of the Software.
--
-- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-- AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
-- OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
-- THE SOFTWARE.
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
entity SpaceWireCODECIPFIFO9x64 is
port (
writeDataIn : in std_logic_vector(8 downto 0);
readClock : in std_logic;
readEnable : in std_logic;
reset : in std_logic;
writeClock : in std_logic;
writeEnable : in std_logic;
readDataOut : out std_logic_vector(8 downto 0);
empty : out std_logic;
full : out std_logic;
readDataCount : out std_logic_vector(5 downto 0);
writeDataCount : out std_logic_vector(5 downto 0)
);
end SpaceWireCODECIPFIFO9x64;
architecture RTL of SpaceWireCODECIPFIFO9x64 is
type turnMemory is array(0 to 63) of std_logic_vector(8 downto 0);
signal dpram : turnMemory;
type turnTable is array(0 to 63) of std_logic_vector(5 downto 0);
constant binaryToGray : turnTable := (
"000000", "000001", "000011", "000010",
"000110", "000111", "000101", "000100",
"001100", "001101", "001111", "001110",
"001010", "001011", "001001", "001000",
"011000", "011001", "011011", "011010",
"011110", "011111", "011101", "011100",
"010100", "010101", "010111", "010110",
"010010", "010011", "010001", "010000",
"110000", "110001", "110011", "110010",
"110110", "110111", "110101", "110100",
"111100", "111101", "111111", "111110",
"111010", "111011", "111001", "111000",
"101000", "101001", "101011", "101010",
"101110", "101111", "101101", "101100",
"100100", "100101", "100111", "100110",
"100010", "100011", "100001", "100000");
constant grayToBinary : turnTable := (
"000000", "000001", "000011", "000010",
"000111", "000110", "000100", "000101",
"001111", "001110", "001100", "001101",
"001000", "001001", "001011", "001010",
"011111", "011110", "011100", "011101",
"011000", "011001", "011011", "011010",
"010000", "010001", "010011", "010010",
"010111", "010110", "010100", "010101",
"111111", "111110", "111100", "111101",
"111000", "111001", "111011", "111010",
"110000", "110001", "110011", "110010",
"110111", "110110", "110100", "110101",
"100000", "100001", "100011", "100010",
"100111", "100110", "100100", "100101",
"101111", "101110", "101100", "101101",
"101000", "101001", "101011", "101010");
signal iWriteReset : std_logic;
signal iReadReset : std_logic;
signal iWriteResetTime : std_logic_vector(1 downto 0);
signal iReadResetTime : std_logic_vector(1 downto 0);
signal iWritePointer : std_logic_vector(5 downto 0);
signal iGrayWritePointer : std_logic_vector(5 downto 0);
signal iGrayWritePointer1 : std_logic_vector(5 downto 0);
signal iGrayWritePointer2 : std_logic_vector(5 downto 0);
signal iGrayWritePointer3 : std_logic_vector(5 downto 0);
signal iWritePointer4 : std_logic_vector(5 downto 0);
signal iReadPointer : std_logic_vector(5 downto 0);
signal iGrayReadPointer : std_logic_vector(5 downto 0);
signal iGrayReadPointer1 : std_logic_vector(5 downto 0);
signal iGrayReadPointer2 : std_logic_vector(5 downto 0);
signal iReadPointer3 : std_logic_vector(5 downto 0);
signal iWriteDataCount : std_logic_vector(5 downto 0);
signal iFull : std_logic;
signal iReadDataOut : std_logic_vector(8 downto 0);
signal iReadDataCount : std_logic_vector(5 downto 0);
signal iEmpty : std_logic;
begin
writeDataCount <= iWriteDataCount;
full <= iFull;
empty <= iEmpty;
readDataCount <= iReadDataCount;
readDataOut <= iReadDataOut;
----------------------------------------------------------------------
-- synchronized Reset.
----------------------------------------------------------------------
process(reset, writeClock)
begin
if (reset = '1') then
iWriteResetTime <= "11";
iWriteReset <= '1';
elsif (writeClock'event and writeClock = '1') then
iWriteResetTime <= iWriteResetTime(0) & reset;
iWriteReset <= iWriteResetTime(1);
end if;
end process;
----------------------------------------------------------------------
-- Write pointer of the buffer.
----------------------------------------------------------------------
process(iWriteReset, writeClock)
begin
if (writeClock'event and writeClock = '1') then
if (iWriteReset = '1') then
iWritePointer <= "000000";
elsif (writeEnable = '1') then
iWritePointer <= iWritePointer + '1';
end if;
end if;
end process;
iWriteDataCount <= iWritePointer - iReadPointer3;
----------------------------------------------------------------------
-- Writing to buffer.
----------------------------------------------------------------------
process(writeClock)
begin
if (writeClock'event and writeClock = '1') then
if (writeEnable = '1') then
dpram(conv_integer(iWritePointer)) <= writeDataIn;
end if;
end if;
end process;
----------------------------------------------------------------------
-- Change to Gray code.
----------------------------------------------------------------------
process(iWriteReset, writeClock)
begin
if (writeClock'event and writeClock = '1') then
if (iWriteReset = '1') then
iGrayWritePointer <= "000000";
else
iGrayWritePointer <= binaryToGray(conv_integer(iWritePointer));
end if;
end if;
end process;
iFull <= '1' when ((iWritePointer - iReadPointer3) > "111000") or iWriteReset = '1' else '0';
----------------------------------------------------------------------
-- Convert gray code Readpointer to binary Readpointer to calculate writeDataCount and full.
----------------------------------------------------------------------
process(iWriteReset, writeClock)
begin
if (writeClock'event and writeClock = '1') then
if (iWriteReset = '1') then
iGrayReadPointer1 <= "000000";
iGrayReadPointer2 <= "000000";
iReadPointer3 <= "000000";
else
iGrayReadPointer1 <= iGrayReadPointer;
iGrayReadPointer2 <= iGrayReadPointer1;
iReadPointer3 <= grayToBinary(conv_integer(iGrayReadPointer2));
end if;
end if;
end process;
----------------------------------------------------------------------
-- Convert gray code Writepointer to binary Writepointer to calculate readDataCount and empty.
----------------------------------------------------------------------
process(iReadReset, readClock)
begin
if (readClock'event and readClock = '1') then
if (iReadReset = '1') then
iGrayWritePointer1 <= "000000";
iGrayWritePointer2 <= "000000";
iGrayWritePointer3 <= "000000";
iWritePointer4 <= "000000";
else
iGrayWritePointer1 <= iGrayWritePointer;
iGrayWritePointer2 <= iGrayWritePointer1;
iGrayWritePointer3 <= iGrayWritePointer2;
iWritePointer4 <= grayToBinary(conv_integer(iGrayWritePointer3));
end if;
end if;
end process;
----------------------------------------------------------------------
-- Read from buffer.
----------------------------------------------------------------------
process(readClock)
begin
if (readClock'event and readClock = '1') then
if(iEmpty = '0')then
if (readEnable = '1') then
iReadDataOut <= dpram(conv_integer(iReadPointer));
end if;
end if;
end if;
end process;
iReadDataCount <= iWritePointer4 - iReadPointer;
----------------------------------------------------------------------
-- Read pointer of the buffer.
----------------------------------------------------------------------
process(iReadReset, readClock)
begin
if (readClock'event and readClock = '1') then
if (iReadReset = '1') then
iReadPointer <= "000000";
elsif(iEmpty = '0')then
if readEnable = '1' then
iReadPointer <= iReadPointer + '1';
end if;
end if;
end if;
end process;
----------------------------------------------------------------------
-- Change to Gray code.
----------------------------------------------------------------------
process(iReadReset, readClock)
begin
if (readClock'event and readClock = '1') then
if (iReadReset = '1') then
iGrayReadPointer <= "000000";
else
iGrayReadPointer <= binaryToGray(conv_integer(iReadPointer));
end if;
end if;
end process;
----------------------------------------------------------------------
-- Generate the EMPTY signal.
----------------------------------------------------------------------
iEmpty <= '1' when iWritePointer4 = iReadPointer or iReadReset = '1' else '0';
----------------------------------------------------------------------
-- synchronized Reset.
----------------------------------------------------------------------
process(reset, readClock)
begin
if (reset = '1') then
iReadResetTime <= "11";
iReadReset <= '1';
elsif (readClock'event and readClock = '1') then
iReadResetTime <= iReadResetTime(0) & reset;
iReadReset <= iReadResetTime(1);
end if;
end process;
end RTL;
| gpl-3.0 | c02f223c00e5828f7ff6d9af92b5843f | 0.502679 | 4.631814 | false | false | false | false |
EliasLuiz/TCC | Teste/DefTypes.vhd | 1 | 11,630 | library ieee;
use ieee.math_real.all;
use ieee.std_logic_1164.all;
use work.Constants.all;
package DefTypes is
-----------------------------TYPES-----------------------------
--Type used for easier access to the NPCTag table data
type MemoTableTNPCTagEntry is record
Valid: std_logic;
Tag: std_logic_vector(MemoTableTTagWidth-1 downto 0);
NPC: std_logic_vector(ArchitectureBitCount-1 downto 0);
end record;
--Type used for easier access to the LRUCounter table data
type MemoTableTLRUCounterEntry is record
LRUCounter: std_logic_vector(MemoTableTLRUCounterEntryWidth-1 downto 0);
end record;
--Auxiliary types for the input and output contexts
--Records a register's identifier number and value
type MemoTableTRegister is record
Identifier: std_logic_vector(ArchitectureBitCountAddress-1 downto 0); --Register number
Value: std_logic_vector(ArchitectureBitCount-1 downto 0); --Register value
end record;
--Array of registers
type MemoTableTRegisterArray is
array (natural range <>) --Number of registers
of MemoTableTRegister; --Register entry
--Type used for easier access to the Input table data
subtype MemoTableTInputEntry is
MemoTableTRegisterArray(0 to InputContextLenght-1);
--Type used for easier access to the Output table data
subtype MemoTableTOutputEntry is
MemoTableTRegisterArray(0 to OutputContextLenght-1);
--Type used for easier access to the full trace data
type MemoTableTTrace is record
Valid: std_logic;
NPC: std_logic_vector(ArchitectureBitCount-1 downto 0);
InputRegisters: MemoTableTInputEntry;
OutputRegisters: MemoTableTOutputEntry;
LRUCounter: std_logic_vector(MemoTableTLRUCounterEntryWidth-1 downto 0);
end record;
--Interface to the input / output of MemoTableTNPCTag
type MemoTableTNPCTagBus is
array(0 to MemoTableTAssociativity-1) of --Ways
MemoTableTNPCTagEntry; --Data
--std_logic_vector(MemoTableTNPCTagEntryWidth-1 downto 0); --Data
--Interface to the input / output of MemoTableTInput
type MemoTableTInputBus is
array(0 to MemoTableTAssociativity-1) of --Ways
MemoTableTInputEntry; --Data
--std_logic_vector(MemoTableTInputEntryWidth-1 downto 0); --Data
--Interface to the input / output of MemoTableTOutput
type MemoTableTOutputBus is
array(0 to MemoTableTAssociativity-1) of --Ways
MemoTableTOutputEntry; --Data
--std_logic_vector(MemoTableTOutputEntryWidth-1 downto 0); --Data
--Interface to the input / output of MemoTableTLRUCounter
type MemoTableTLRUCounterBus is
array(0 to MemoTableTAssociativity-1) of --Ways
MemoTableTLRUCounterEntry; --Data
--std_logic_vector(MemoTableTLRUCounterEntryWidth-1 downto 0); --Data
--Interface to the input / output of MemoTableT
type MemoTableTBus is
array(0 to MemoTableTAssociativity-1) of --Ways
MemoTableTTrace; --Data
--std_logic_vector(MemoTableTEntryWidth-1 downto 0); --Data
---------------------------------------------------------------
---------------------------FUNCTIONS---------------------------
function StdLogicToRegister(signal input : in std_logic_vector) return MemoTableTRegister;
function RegisterToStdLogic(signal input : in MemoTableTRegister) return std_logic_vector;
function LRUCounterStdLogicToRegister(signal input : in std_logic_vector) return MemoTableTRegister;
function RegisterToLRUCounterStdLogic(signal input : in MemoTableTRegister) return std_logic_vector;
function StdLogicToLRUCounter(signal input : in std_logic_vector) return MemoTableTLRUCounterEntry;
function LRUCounterToStdLogic(signal input : in MemoTableTLRUCounterEntry) return std_logic_vector;
function StdLogicToNPCTag(signal input : in std_logic_vector) return MemoTableTNPCTagEntry;
function NPCTagToStdLogic(signal input : in MemoTableTNPCTagEntry) return std_logic_vector;
function StdLogicToInput(signal input : in std_logic_vector) return MemoTableTInputEntry;
function InputToStdLogic(signal input : in MemoTableTInputEntry) return std_logic_vector;
function StdLogicToOutput(signal input : in std_logic_vector) return MemoTableTOutputEntry;
function OutputToStdLogic(signal input : in MemoTableTOutputEntry) return std_logic_vector;
---------------------------------------------------------------
end DefTypes;
package body DefTypes is
function StdLogicToRegister(signal input : in std_logic_vector) return MemoTableTRegister is
variable res: MemoTableTRegister;
begin
res.Value(ArchitectureBitCount-1 downto 0) :=
input(ArchitectureBitCount+ArchitectureBitCountAddress-1 downto ArchitectureBitCountAddress);
res.Identifier(ArchitectureBitCountAddress-1 downto 0) :=
input(ArchitectureBitCountAddress-1 downto 0);
return res;
end StdLogicToRegister;
function RegisterToStdLogic(signal input : in MemoTableTRegister) return std_logic_vector is
variable res: std_logic_vector(ArchitectureBitCountAddress+ArchitectureBitCount-1 downto 0);
begin
res(ArchitectureBitCount+ArchitectureBitCountAddress-1 downto ArchitectureBitCountAddress) :=
input.Value(ArchitectureBitCount-1 downto 0);
res(ArchitectureBitCountAddress-1 downto 0) :=
input.Identifier(ArchitectureBitCountAddress-1 downto 0);
return res;
end RegisterToStdLogic;
function LRUCounterStdLogicToRegister(signal input : in std_logic_vector) return MemoTableTRegister is
variable res: MemoTableTRegister;
begin
res.Value(ArchitectureBitCount-1 downto MemoTableTLRUCounterEntryWidth) :=
(OTHERS => '0');
res.Value(MemoTableTLRUCounterEntryWidth-1 downto 0) :=
input(MemoTableTLRUCounterEntryWidth+MemoTableTAssociativityAddress-1 downto MemoTableTAssociativityAddress);
res.Identifier(ArchitectureBitCountAddress-1 downto MemoTableTAssociativityAddress) :=
(OTHERS => '0');
res.Identifier(MemoTableTAssociativityAddress-1 downto 0) :=
input(MemoTableTAssociativityAddress-1 downto 0);
return res;
end LRUCounterStdLogicToRegister;
function RegisterToLRUCounterStdLogic(signal input : in MemoTableTRegister) return std_logic_vector is
variable res: std_logic_vector(ArchitectureBitCountAddress+ArchitectureBitCount-1 downto 0);
begin
res(ArchitectureBitCount+ArchitectureBitCountAddress-1 downto MemoTableTLRUCounterEntryWidth+ArchitectureBitCountAddress) :=
(OTHERS => '0');
res(MemoTableTLRUCounterEntryWidth+ArchitectureBitCountAddress-1 downto ArchitectureBitCountAddress) :=
input.Value(MemoTableTLRUCounterEntryWidth-1 downto 0);
res(ArchitectureBitCountAddress-1 downto MemoTableTAssociativityAddress) :=
(OTHERS => '0');
res(MemoTableTAssociativityAddress-1 downto 0) :=
input.Identifier(MemoTableTAssociativityAddress-1 downto 0);
return res;
end RegisterToLRUCounterStdLogic;
---------------------------FUNCTIONS---------------------------
-- Bit(s) Value
-- (MemoTableTNPCTagEntryWidth - 1) Valid bit
-- (MemoTableTTagWidth + ArchitectureBitCount - 1
-- downto ArchitectureBitCount) Tag field
-- (ArchitectureBitCount - 1 downto 0) NPC
function StdLogicToNPCTag(signal input : in std_logic_vector) return MemoTableTNPCTagEntry is
variable res: MemoTableTNPCTagEntry;
begin
res.Valid := input(MemoTableTNPCTagEntryWidth - 1);
res.Tag := input(MemoTableTTagWidth + ArchitectureBitCount - 1
downto ArchitectureBitCount);
res.NPC := input(ArchitectureBitCount - 1 downto 0);
return res;
end StdLogicToNPCTag;
function NPCTagToStdLogic(signal input : in MemoTableTNPCTagEntry) return std_logic_vector is
variable res: std_logic_vector(MemoTableTNPCTagEntryWidth - 1 downto 0);
begin
res(MemoTableTNPCTagEntryWidth - 1) := input.Valid;
res(MemoTableTTagWidth + ArchitectureBitCount - 1
downto ArchitectureBitCount) := input.Tag;
res(ArchitectureBitCount - 1 downto 0) := input.NPC;
return res;
end NPCTagToStdLogic;
-- Bit(s) Value
-- N*(ArchitectureBitCount+ArchitectureBitCountAddress)
-- downto N*ArchitectureBitCount+(N+1)*ArchitectureBitCountAddress)-1 Nth register identifier
-- N*ArchitectureBitCount+(N+1)*ArchitectureBitCountAddress)
-- downto (N+1)(ArchitectureBitCount+ArchitectureBitCountAddress)-1 Nth register value
function StdLogicToInput(signal input : in std_logic_vector) return MemoTableTInputEntry is
variable res: MemoTableTInputEntry;
begin
r: for i in 0 to InputContextLenght-1 loop
res(i).Identifier(ArchitectureBitCountAddress-1 downto 0) := input(
i*ArchitectureBitCount+(i+1)*ArchitectureBitCountAddress-1
downto i*ArchitectureBitCount+i*ArchitectureBitCountAddress);
res(i).Value(ArchitectureBitCount-1 downto 0) := input(
(i+1)*(ArchitectureBitCount+ArchitectureBitCountAddress)-1
downto i*ArchitectureBitCount+(i+1)*ArchitectureBitCountAddress);
end loop r;
return res;
end StdLogicToInput;
function InputToStdLogic(signal input : in MemoTableTInputEntry) return std_logic_vector is
variable res: std_logic_vector(MemoTableTInputEntryWidth - 1 downto 0);
begin
r: for i in 0 to InputContextLenght-1 loop
res(i*(ArchitectureBitCount+ArchitectureBitCountAddress)
downto i*ArchitectureBitCount+(i+1)*ArchitectureBitCountAddress-1) := input(i).Identifier;
res(i*ArchitectureBitCount+(i+1)*ArchitectureBitCountAddress
downto (i+1)*(ArchitectureBitCount+ArchitectureBitCountAddress)-1) := input(i).Value;
end loop r;
return res;
end InputToStdLogic;
-- Bit(s) Value
-- N*(ArchitectureBitCount+ArchitectureBitCountAddress)
-- downto N*ArchitectureBitCount+(N+1)*ArchitectureBitCountAddress)-1 Nth register identifier
-- N*ArchitectureBitCount+(N+1)*ArchitectureBitCountAddress)
-- downto (N+1)(ArchitectureBitCount+ArchitectureBitCountAddress)-1 Nth register value
function StdLogicToOutput(signal input : in std_logic_vector) return MemoTableTOutputEntry is
variable res: MemoTableTOutputEntry;
begin
r: for i in 0 to OutputContextLenght-1 loop
res(i).Identifier := input(i*ArchitectureBitCount+(i+1)*ArchitectureBitCountAddress-1
downto i*(ArchitectureBitCount+ArchitectureBitCountAddress));
res(i).Value := input((i+1)*(ArchitectureBitCount+ArchitectureBitCountAddress)-1
downto i*ArchitectureBitCount+(i+1)*ArchitectureBitCountAddress);
end loop r;
return res;
end StdLogicToOutput;
function OutputToStdLogic(signal input : in MemoTableTOutputEntry) return std_logic_vector is
variable res: std_logic_vector(MemoTableTOutputEntryWidth - 1 downto 0);
begin
r: for i in 0 to OutputContextLenght-1 loop
res(i*ArchitectureBitCount+(i+1)*ArchitectureBitCountAddress-1
downto i*(ArchitectureBitCount+ArchitectureBitCountAddress)) := input(i).Identifier;
res((i+1)*(ArchitectureBitCount+ArchitectureBitCountAddress)-1
downto i*ArchitectureBitCount+(i+1)*ArchitectureBitCountAddress) := input(i).Value;
end loop r;
return res;
end OutputToStdLogic;
-- Bit(s) Value
-- (MemoTableTLRUCounterEntryWidth - 1 downto 0) LRU Counter
function StdLogicToLRUCounter(signal input : in std_logic_vector) return MemoTableTLRUCounterEntry is
variable res: MemoTableTLRUCounterEntry;
begin
res.LRUCounter := input;
return res;
end StdLogicToLRUCounter;
function LRUCounterToStdLogic(signal input : in MemoTableTLRUCounterEntry) return std_logic_vector is
variable res: std_logic_vector(MemoTableTLRUCounterEntryWidth - 1 downto 0);
begin
res := input.LRUCounter;
return res;
end LRUCounterToStdLogic;
---------------------------------------------------------------
end package body;
| gpl-3.0 | 709837bbeaedd11ed0e1761b145defac | 0.753138 | 3.614046 | false | false | false | false |
EliasLuiz/TCC | Leon3/designs/leon3-xilinx-vc707/testbench.vhd | 1 | 18,296 | -----------------------------------------------------------------------------
-- LEON Demonstration design test bench
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library gaisler;
use gaisler.libdcom.all;
use gaisler.sim.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
library techmap;
use techmap.gencomp.all;
use work.debug.all;
use work.config.all;
entity testbench is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
clktech : integer := CFG_CLKTECH;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW;
USE_MIG_INTERFACE_MODEL : boolean := false
);
end;
architecture behav of testbench is
-- DDR3 Simulation parameters
constant SIM_BYPASS_INIT_CAL : string := "FAST";
-- # = "OFF" - Complete memory init &
-- calibration sequence
-- # = "SKIP" - Not supported
-- # = "FAST" - Complete memory init & use
-- abbreviated calib sequence
constant SIMULATION : string := "TRUE";
-- Should be TRUE during design simulations and
-- FALSE during implementations
constant promfile : string := "prom.srec"; -- rom contents
constant ramfile : string := "ram.srec"; -- ram contents
signal clk : std_logic := '0';
signal rst : std_logic := '0';
signal address : std_logic_vector(25 downto 0);
signal data : std_logic_vector(15 downto 0);
signal button : std_logic_vector(3 downto 0) := "0000";
signal genio : std_logic_vector(59 downto 0);
signal romsn : std_logic;
signal oen : std_ulogic;
signal writen : std_ulogic;
signal adv : std_logic;
signal GND : std_ulogic := '0';
signal VCC : std_ulogic := '1';
signal NC : std_ulogic := 'Z';
signal txd1 , rxd1 , dsurx : std_logic;
signal txd2 , rxd2 , dsutx : std_logic;
signal ctsn1 , rtsn1 , dsuctsn : std_ulogic;
signal ctsn2 , rtsn2 , dsurtsn : std_ulogic;
signal phy_mii_data : std_logic;
signal phy_tx_clk : std_ulogic;
signal phy_rx_clk : std_ulogic;
signal phy_rx_data : std_logic_vector(7 downto 0);
signal phy_dv : std_ulogic;
signal phy_rx_er : std_ulogic;
signal phy_col : std_ulogic;
signal phy_crs : std_ulogic;
signal phy_tx_data : std_logic_vector(7 downto 0);
signal phy_tx_en : std_ulogic;
signal phy_tx_er : std_ulogic;
signal phy_mii_clk : std_ulogic;
signal phy_rst_n : std_ulogic;
signal phy_gtx_clk : std_ulogic;
signal phy_mii_int_n : std_ulogic;
signal clk27 : std_ulogic := '0';
signal clk200p : std_ulogic := '0';
signal clk200n : std_ulogic := '1';
signal clk33 : std_ulogic := '0';
signal clkethp : std_ulogic := '0';
signal clkethn : std_ulogic := '1';
signal txp1 : std_logic;
signal txn : std_logic;
signal rxp : std_logic := '1';
signal rxn : std_logic := '0';
signal iic_scl : std_ulogic;
signal iic_sda : std_ulogic;
signal ddc_scl : std_ulogic;
signal ddc_sda : std_ulogic;
signal dvi_iic_scl : std_logic;
signal dvi_iic_sda : std_logic;
signal tft_lcd_data : std_logic_vector(11 downto 0);
signal tft_lcd_clk_p : std_ulogic;
signal tft_lcd_clk_n : std_ulogic;
signal tft_lcd_hsync : std_ulogic;
signal tft_lcd_vsync : std_ulogic;
signal tft_lcd_de : std_ulogic;
signal tft_lcd_reset_b : std_ulogic;
-- DDR3 memory
signal ddr3_dq : std_logic_vector(63 downto 0);
signal ddr3_dqs_p : std_logic_vector(7 downto 0);
signal ddr3_dqs_n : std_logic_vector(7 downto 0);
signal ddr3_addr : std_logic_vector(13 downto 0);
signal ddr3_ba : std_logic_vector(2 downto 0);
signal ddr3_ras_n : std_logic;
signal ddr3_cas_n : std_logic;
signal ddr3_we_n : std_logic;
signal ddr3_reset_n : std_logic;
signal ddr3_ck_p : std_logic_vector(0 downto 0);
signal ddr3_ck_n : std_logic_vector(0 downto 0);
signal ddr3_cke : std_logic_vector(0 downto 0);
signal ddr3_cs_n : std_logic_vector(0 downto 0);
signal ddr3_dm : std_logic_vector(7 downto 0);
signal ddr3_odt : std_logic_vector(0 downto 0);
-- SPI flash
signal spi_sel_n : std_ulogic;
signal spi_clk : std_ulogic;
signal spi_mosi : std_ulogic;
signal dsurst : std_ulogic;
signal errorn : std_logic;
signal switch : std_logic_vector(4 downto 0); -- I/O port
signal led : std_logic_vector(6 downto 0); -- I/O port
constant lresp : boolean := false;
signal tdqs_n : std_logic;
signal gmii_tx_clk : std_logic;
signal gmii_rx_clk : std_logic;
signal gmii_txd : std_logic_vector(7 downto 0);
signal gmii_tx_en : std_logic;
signal gmii_tx_er : std_logic;
signal gmii_rxd : std_logic_vector(7 downto 0);
signal gmii_rx_dv : std_logic;
signal gmii_rx_er : std_logic;
signal configuration_finished : boolean;
signal speed_is_10_100 : std_logic;
signal speed_is_100 : std_logic;
signal usb_clkout : std_logic := '0';
signal usb_d : std_logic_vector(7 downto 0);
signal usb_resetn : std_ulogic;
signal usb_nxt : std_ulogic;
signal usb_stp : std_ulogic;
signal usb_dir : std_ulogic;
-- GRUSB_DCL test signals
signal ddelay : std_ulogic := '0';
signal dstart : std_ulogic := '0';
signal drw : std_ulogic;
signal daddr : std_logic_vector(31 downto 0);
signal dlen : std_logic_vector(14 downto 0);
signal ddi : grusb_dcl_debug_data;
signal ddone : std_ulogic;
signal ddo : grusb_dcl_debug_data;
signal phy_mdio : std_logic;
signal phy_mdc : std_ulogic;
signal txp_eth, txn_eth : std_logic;
begin
-- clock and reset
clk200p <= not clk200p after 2.5 ns;
clk200n <= not clk200n after 2.5 ns;
clkethp <= not clkethp after 4 ns;
clkethn <= not clkethp after 4 ns;
rst <= not dsurst;
rxd1 <= 'H'; ctsn1 <= '0';
rxd2 <= 'H'; ctsn2 <= '0';
button <= "0000";
switch(3 downto 0) <= "0000";
cpu : entity work.leon3mp
generic map (
fabtech => fabtech,
memtech => memtech,
padtech => padtech,
clktech => clktech,
disas => disas,
dbguart => dbguart,
pclow => pclow,
SIM_BYPASS_INIT_CAL => SIM_BYPASS_INIT_CAL,
SIMULATION => SIMULATION,
USE_MIG_INTERFACE_MODEL => USE_MIG_INTERFACE_MODEL,
autonegotiation => 0
)
port map (
reset => rst,
clk200p => clk200p,
clk200n => clk200n,
address => address,
data => data,
oen => oen,
writen => writen,
romsn => romsn,
adv => adv,
ddr3_dq => ddr3_dq,
ddr3_dqs_p => ddr3_dqs_p,
ddr3_dqs_n => ddr3_dqs_n,
ddr3_addr => ddr3_addr,
ddr3_ba => ddr3_ba,
ddr3_ras_n => ddr3_ras_n,
ddr3_cas_n => ddr3_cas_n,
ddr3_we_n => ddr3_we_n,
ddr3_reset_n => ddr3_reset_n,
ddr3_ck_p => ddr3_ck_p,
ddr3_ck_n => ddr3_ck_n,
ddr3_cke => ddr3_cke,
ddr3_cs_n => ddr3_cs_n,
ddr3_dm => ddr3_dm,
ddr3_odt => ddr3_odt,
dsurx => dsurx,
dsutx => dsutx,
dsuctsn => dsuctsn,
dsurtsn => dsurtsn,
button => button,
switch => switch,
led => led,
iic_scl => iic_scl,
iic_sda => iic_sda,
usb_refclk_opt => '0',
usb_clkout => usb_clkout,
usb_d => usb_d,
usb_nxt => usb_nxt,
usb_stp => usb_stp,
usb_dir => usb_dir,
usb_resetn => usb_resetn,
gtrefclk_p => clkethp,
gtrefclk_n => clkethn,
txp => txp_eth,
txn => txn_eth,
rxp => txp_eth,
rxn => txn_eth,
emdio => phy_mdio,
emdc => phy_mdc,
eint => '0',
erst => OPEN,
can_txd => OPEN,
can_rxd => "0",
spi_data_out => '0',
spi_data_in => OPEN,
spi_data_cs_b => OPEN,
spi_clk => OPEN
);
phy0 : if (CFG_GRETH = 1) generate
phy_mdio <= 'H';
p0: phy
generic map (
address => 7,
extended_regs => 1,
aneg => 1,
base100_t4 => 1,
base100_x_fd => 1,
base100_x_hd => 1,
fd_10 => 1,
hd_10 => 1,
base100_t2_fd => 1,
base100_t2_hd => 1,
base1000_x_fd => 1,
base1000_x_hd => 1,
base1000_t_fd => 1,
base1000_t_hd => 1,
rmii => 0,
rgmii => 1
)
port map(dsurst, phy_mdio, OPEN , OPEN , OPEN ,
OPEN , OPEN , OPEN , OPEN , "00000000",
'0', '0', phy_mdc, clkethp);
end generate;
prom0 : for i in 0 to 1 generate
sr0 : sram generic map (index => i+4, abits => 26, fname => promfile)
port map (address(25 downto 0), data(15-i*8 downto 8-i*8), romsn,
writen, oen);
end generate;
-- Memory model instantiation
gen_mem_model : if (USE_MIG_INTERFACE_MODEL /= true) generate
ddr3mem : if (CFG_MIG_7SERIES = 1) generate
u1 : ddr3ram
generic map (
width => 64,
abits => 14,
colbits => 10,
rowbits => 10,
implbanks => 1,
fname => ramfile,
lddelay => (0 ns),
ldguard => 1,
speedbin => 9, --DDR3-1600K
density => 3,
pagesize => 1,
changeendian => 8)
port map (
ck => ddr3_ck_p(0),
ckn => ddr3_ck_n(0),
cke => ddr3_cke(0),
csn => ddr3_cs_n(0),
odt => ddr3_odt(0),
rasn => ddr3_ras_n,
casn => ddr3_cas_n,
wen => ddr3_we_n,
dm => ddr3_dm,
ba => ddr3_ba,
a => ddr3_addr,
resetn => ddr3_reset_n,
dq => ddr3_dq,
dqs => ddr3_dqs_p,
dqsn => ddr3_dqs_n,
doload => led(3)
);
end generate ddr3mem;
end generate gen_mem_model;
mig_mem_model : if (USE_MIG_INTERFACE_MODEL = true) generate
ddr3_dq <= (others => 'Z');
ddr3_dqs_p <= (others => 'Z');
ddr3_dqs_n <= (others => 'Z');
end generate mig_mem_model;
errorn <= led(1);
errorn <= 'H'; -- ERROR pull-up
usbtr: if (CFG_GRUSBHC = 1) generate
u0: ulpi
port map (usb_clkout, usb_d, usb_nxt, usb_stp, usb_dir, usb_resetn);
end generate usbtr;
usbdevsim: if (CFG_GRUSBDC = 1) generate
u0: grusbdcsim
generic map (functm => 0, keepclk => 1)
port map (usb_resetn, usb_clkout, usb_d, usb_nxt, usb_stp, usb_dir);
end generate usbdevsim;
usb_dclsim: if (CFG_GRUSB_DCL = 1) generate
u0: grusb_dclsim
generic map (functm => 0, keepclk => 1)
port map (usb_resetn, usb_clkout, usb_d, usb_nxt, usb_stp, usb_dir,
ddelay, dstart, drw, daddr, dlen, ddi, ddone, ddo);
usb_dcl_proc : process
begin
wait for 10 ns;
Print("GRUSB_DCL test started");
wait until rising_edge(ddone);
-- Write 128 bytes to memory
daddr <= X"40000000";
dlen <= conv_std_logic_vector(32,15);
for i in 0 to 127 loop
ddi(i) <= conv_std_logic_vector(i+8,8);
end loop; -- i
grusb_dcl_write(usb_clkout, drw, dstart, ddone);
-- Read back written data
grusb_dcl_read(usb_clkout, drw, dstart, ddone);
-- Compare data
for i in 0 to 127 loop
if ddo(i) /= ddi(i) then
Print("ERROR: Data mismatch using GRUSB_DCL");
end if;
end loop;
Print("GRUSB_DCL test finished");
wait;
end process;
end generate usb_dclsim;
iuerr : process
begin
wait for 210 us; -- This is for proper DDR3 behaviour durign init phase not needed durin simulation
if (USE_MIG_INTERFACE_MODEL /= true) then
wait on led(3); -- DDR3 Memory Init ready
end if;
wait for 5000 ns;
if to_x01(errorn) = '1' then
wait on errorn;
end if;
assert (to_x01(errorn) = '1')
report "*** IU in error mode, simulation halted ***"
severity failure ; -- this should be a failure
end process;
data <= buskeep(data) after 5 ns;
dsucom : process
procedure dsucfg(signal dsurx : in std_ulogic; signal dsutx : out std_ulogic) is
variable w32 : std_logic_vector(31 downto 0);
variable c8 : std_logic_vector(7 downto 0);
constant txp : time := 320 * 1 ns;
begin
dsutx <= '1';
dsurst <= '0';
switch(4) <= '0';
wait for 2500 ns;
if (USE_MIG_INTERFACE_MODEL /= true) then
wait for 210 us; -- This is for proper DDR3 behaviour durign init phase not needed durin simulation
end if;
dsurst <= '1';
switch(4) <= '1';
if (USE_MIG_INTERFACE_MODEL /= true) then
wait on led(3); -- Wait for DDR3 Memory Init ready
end if;
report "Start DSU transfer";
wait for 5000 ns;
txc(dsutx, 16#55#, txp); -- sync uart
-- Reads from memory and DSU register to mimic GRMON during simulation
l1 : loop
txc(dsutx, 16#80#, txp);
txa(dsutx, 16#40#, 16#00#, 16#00#, 16#04#, txp);
rxi(dsurx, w32, txp, lresp);
--report "DSU read memory " & tost(w32);
txc(dsutx, 16#80#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
rxi(dsurx, w32, txp, lresp);
--report "DSU Break and Single Step register" & tost(w32);
end loop l1;
wait;
-- ** This is only kept for reference --
-- do test read and writes to DDR3 to check status
-- Write
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#40#, 16#00#, 16#00#, 16#00#, txp);
txa(dsutx, 16#01#, 16#23#, 16#45#, 16#67#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#40#, 16#00#, 16#00#, 16#04#, txp);
txa(dsutx, 16#89#, 16#AB#, 16#CD#, 16#EF#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#40#, 16#00#, 16#00#, 16#08#, txp);
txa(dsutx, 16#08#, 16#19#, 16#2A#, 16#3B#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#40#, 16#00#, 16#00#, 16#0C#, txp);
txa(dsutx, 16#4C#, 16#5D#, 16#6E#, 16#7F#, txp);
txc(dsutx, 16#80#, txp);
txa(dsutx, 16#40#, 16#00#, 16#00#, 16#00#, txp);
rxi(dsurx, w32, txp, lresp);
txc(dsutx, 16#80#, txp);
txa(dsutx, 16#40#, 16#00#, 16#00#, 16#04#, txp);
rxi(dsurx, w32, txp, lresp);
report "* Read " & tost(w32);
txc(dsutx, 16#a0#, txp);
txa(dsutx, 16#40#, 16#00#, 16#00#, 16#08#, txp);
rxi(dsurx, w32, txp, lresp);
txc(dsutx, 16#a0#, txp);
txa(dsutx, 16#40#, 16#00#, 16#00#, 16#0C#, txp);
rxi(dsurx, w32, txp, lresp);
wait;
-- Register 0x90000000 (DSU Control Register)
-- Data 0x0000202e (b0010 0000 0010 1110)
-- [0] - Trace Enable
-- [1] - Break On Error
-- [2] - Break on IU watchpoint
-- [3] - Break on s/w break points
--
-- [4] - (Break on trap)
-- [5] - Break on error traps
-- [6] - Debug mode (Read mode only)
-- [7] - DSUEN (read mode)
--
-- [8] - DSUBRE (read mode)
-- [9] - Processor mode error (clears error)
-- [10] - processor halt (returns 1 if processor halted)
-- [11] - power down mode (return 1 if processor in power down mode)
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp);
txa(dsutx, 16#00#, 16#00#, 16#80#, 16#02#, txp);
wait;
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp);
txa(dsutx, 16#00#, 16#00#, 16#20#, 16#2e#, txp);
wait for 25000 ns;
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#01#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#40#, 16#00#, 16#24#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#0D#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#70#, 16#11#, 16#78#, txp);
txa(dsutx, 16#91#, 16#00#, 16#00#, 16#0D#, txp);
txa(dsutx, 16#90#, 16#40#, 16#00#, 16#44#, txp);
txa(dsutx, 16#00#, 16#00#, 16#20#, 16#00#, txp);
txc(dsutx, 16#80#, txp);
txa(dsutx, 16#90#, 16#40#, 16#00#, 16#44#, txp);
wait;
end;
begin
dsuctsn <= '0';
dsucfg(dsutx, dsurx);
wait;
end process;
end ;
| gpl-3.0 | df9be1d888fcee381cb25c96c72d33a7 | 0.530881 | 3.326545 | false | false | false | false |
EliasLuiz/TCC | Leon3/designs/leon3-xilinx-ml605/ahb2mig_ml605.vhd | 1 | 16,783 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: ahb2mig
-- File: ahb2mig.vhd
-- Author: Jiri Gaisler, Gaisler Research
-- Description: AHB wrapper for Xilinx Virtex6 DDR2/3 MIG
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
package ml605 is
constant nCS_PER_RANK : integer := 1;
constant BANK_WIDTH : integer := 3;
constant CK_WIDTH : integer := 1;
constant CKE_WIDTH : integer := 1;
constant COL_WIDTH : integer := 10;
constant CS_WIDTH : integer := 1;
constant DM_WIDTH : integer := 8;
constant DQ_WIDTH : integer := 64;
constant DQS_WIDTH : integer := 8;
constant ROW_WIDTH : integer := 13;
constant PAYLOAD_WIDTH : integer := 64;
constant ADDR_WIDTH : integer := 27;
type mig_app_in_type is record
app_wdf_wren : std_logic;
app_wdf_data : std_logic_vector((4*PAYLOAD_WIDTH)-1 downto 0);
app_wdf_mask : std_logic_vector((4*PAYLOAD_WIDTH)/8-1 downto 0);
app_wdf_end : std_logic;
app_addr : std_logic_vector(ADDR_WIDTH-1 downto 0);
app_cmd : std_logic_vector(2 downto 0);
app_en : std_logic;
end record;
type mig_app_out_type is record
app_rdy : std_logic;
app_wdf_rdy : std_logic;
app_rd_data : std_logic_vector((4*PAYLOAD_WIDTH)-1 downto 0);
app_rd_data_valid : std_logic;
end record;
component ahb2mig_ml605
generic (
memtech : integer := 0;
hindex : integer := 0;
haddr : integer := 0;
hmask : integer := 16#e00#;
MHz : integer := 100;
Mbyte : integer := 512;
nosync : integer := 0
);
port (
rst : in std_ulogic;
clk_ddr : in std_ulogic;
clk_ahb : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
migi : out mig_app_in_type;
migo : in mig_app_out_type
);
end component;
end package;
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
library gaisler;
use grlib.devices.all;
use gaisler.memctrl.all;
library techmap;
use techmap.gencomp.all;
use work.ml605.all;
entity ahb2mig_ml605 is
generic (
memtech : integer := 0;
hindex : integer := 0;
haddr : integer := 0;
hmask : integer := 16#e00#;
MHz : integer := 100;
Mbyte : integer := 512;
nosync : integer := 0
);
port (
rst : in std_ulogic;
clk_ddr : in std_ulogic;
clk_ahb : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
migi : out mig_app_in_type;
migo : in mig_app_out_type
);
end;
architecture rtl of ahb2mig_ml605 is
constant REVISION : integer := 0;
constant hconfig : ahb_config_type := (
0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_MIGDDR2, 0, REVISION, 0),
4 => ahb_membar(haddr, '1', '1', hmask),
others => zero32);
type ahb_state_type is (midle, rhold, dread, dwrite, whold1, whold2);
type ddr_state_type is (midle, rhold, dread, dwrite, whold1, whold2);
constant abuf : integer := 6;
type access_param is record
haddr : std_logic_vector(31 downto 0);
size : std_logic_vector(2 downto 0);
hwrite : std_ulogic;
end record;
-- local registers
type mem is array(0 to 15) of std_logic_vector(31 downto 0);
type wrm is array(0 to 15) of std_logic_vector(3 downto 0);
type ahb_reg_type is record
hready : std_ulogic;
hsel : std_ulogic;
startsd : std_ulogic;
state : ahb_state_type;
haddr : std_logic_vector(31 downto 0);
hrdata : std_logic_vector(127 downto 0);
hwrite : std_ulogic;
htrans : std_logic_vector(1 downto 0);
hresp : std_logic_vector(1 downto 0);
raddr : std_logic_vector(abuf-1 downto 0);
size : std_logic_vector(2 downto 0);
acc : access_param;
sync : std_ulogic;
hwdata : mem;
write : wrm;
end record;
type ddr_reg_type is record
startsd : std_ulogic;
hrdata : std_logic_vector(511 downto 0);
sync : std_ulogic;
dstate : ahb_state_type;
end record;
signal vcc, clk_ahb1, clk_ahb2 : std_ulogic;
signal r, ri : ddr_reg_type;
signal ra, rai : ahb_reg_type;
signal rbdrive, ribdrive : std_logic_vector(31 downto 0);
signal hwdata, hwdatab : std_logic_vector(127 downto 0);
begin
vcc <= '1';
ahb_ctrl : process(rst, ahbsi, r, ra, migo, hwdata)
variable va : ahb_reg_type; -- local variables for registers
variable startsd : std_ulogic;
variable ready : std_logic;
variable tmp : std_logic_vector(3 downto 0);
variable waddr : integer;
variable rdata : std_logic_vector(127 downto 0);
begin
va := ra; va.hresp := HRESP_OKAY;
tmp := (others => '0');
case ra.raddr(3 downto 2) is
when "00" => rdata := r.hrdata(127 downto 0);
when "01" => rdata := r.hrdata(255 downto 128);
when "10" => rdata := r.hrdata(383 downto 256);
when others => rdata := r.hrdata(511 downto 384);
end case;
if AHBDW > 64 and ra.size = HSIZE_4WORD then
va.hrdata := rdata(31 downto 0) & rdata(63 downto 32) & rdata(95 downto 64) & rdata(127 downto 96);
elsif AHBDW > 32 and ra.size = HSIZE_DWORD then
if ra.raddr(1) = '1' then va.hrdata(63 downto 0) := rdata(95 downto 64) & rdata(127 downto 96);
else va.hrdata(63 downto 0) := rdata(31 downto 0) & rdata(63 downto 32); end if;
va.hrdata(127 downto 64) := va.hrdata(63 downto 0);
else
case ra.raddr(1 downto 0) is
when "00" => va.hrdata(31 downto 0) := rdata(31 downto 0);
when "01" => va.hrdata(31 downto 0) := rdata(63 downto 32);
when "10" => va.hrdata(31 downto 0) := rdata(95 downto 64);
when others => va.hrdata(31 downto 0) := rdata(127 downto 96);
end case;
va.hrdata(127 downto 32) := va.hrdata(31 downto 0) &
va.hrdata(31 downto 0) &
va.hrdata(31 downto 0);
end if;
if nosync = 0 then
va.sync := r.startsd;
if ra.startsd = ra.sync then ready := '1';
else ready := '0'; end if;
else
if ra.startsd = r.startsd then ready := '1';
else ready := '0'; end if;
end if;
if ((ahbsi.hready and ahbsi.hsel(hindex)) = '1') then
va.htrans := ahbsi.htrans; va.haddr := ahbsi.haddr;
va.size := ahbsi.hsize(2 downto 0); va.hwrite := ahbsi.hwrite;
if ahbsi.htrans(1) = '1' then
va.hsel := '1'; va.hready := '0';
end if;
end if;
if ahbsi.hready = '1' then va.hsel := ahbsi.hsel(hindex); end if;
case ra.state is
when midle =>
va.write := (others => "0000");
if ((va.hsel and va.htrans(1)) = '1') then
if va.hwrite = '0' then
va.state := rhold; va.startsd := not ra.startsd;
else
va.state := dwrite; va.hready := '1';
end if;
end if;
va.raddr := ra.haddr(7 downto 2);
if ((ahbsi.hready and ahbsi.hsel(hindex)) = '1') then
va.acc := (va.haddr, va.size, va.hwrite);
end if;
when rhold =>
va.raddr := ra.haddr(7 downto 2);
if ready = '1' then
va.state := dread; va.hready := '1';
if AHBDW > 64 and ra.size(2) = '1' then va.raddr := ra.raddr + 4;
elsif AHBDW > 32 and andv(ra.size(1 downto 0)) = '1' then va.raddr := ra.raddr + 2;
else va.raddr := ra.raddr + 1; end if;
end if;
when dread =>
va.hready := '1';
if AHBDW > 64 and ra.size(2) = '1' then va.raddr := ra.raddr + 4;
elsif AHBDW > 32 and andv(ra.size(1 downto 0)) = '1' then va.raddr := ra.raddr + 2;
else va.raddr := ra.raddr + 1; end if;
if ((va.hsel and va.htrans(1) and va.htrans(0)) = '0')
or (ra.raddr(3 downto 0) = "0000") then
va.state := midle; va.hready := '0';
end if;
va.acc := (va.haddr, va.size, va.hwrite);
when dwrite =>
va.raddr := ra.haddr(7 downto 2); va.hready := '1';
if (((va.hsel and va.htrans(1) and va.htrans(0)) = '0')
or (ra.haddr(5 downto 2) = "1111")
or (AHBDW > 32 and ra.haddr(5 downto 2) = "1110" and andv(ra.size(1 downto 0)) = '1')
or (AHBDW > 64 and ra.haddr(5 downto 2) = "1100" and ra.size(2) = '1')) then
va.startsd := not ra.startsd; va.state := whold1;
va.hready := '0';
end if;
tmp := decode(ra.haddr(1 downto 0));
waddr := conv_integer(ra.haddr(5 downto 2));
va.hwdata(waddr) := hwdata(31 downto 0);
case ra.size is
when "000" => va.write(waddr) := tmp(0) & tmp(1) & tmp(2) & tmp(3);
when "001" => va.write(waddr) := tmp(0) & tmp(0) & tmp(2) & tmp(2);
when "010" => va.write(waddr) := "1111";
when "011" => va.write(waddr) := "1111"; va.write(waddr+1) := "1111";
va.hwdata(waddr+1) := hwdata((63 mod AHBDW) downto (32 mod AHBDW));
when others => va.write(waddr) := "1111"; va.write(waddr+1) := "1111";
va.write(waddr+2) := "1111"; va.write(waddr+3) := "1111";
va.hwdata(waddr+1) := hwdata((63 mod AHBDW) downto (32 mod AHBDW));
va.hwdata(waddr+2) := hwdata((95 mod AHBDW) downto (64 mod AHBDW));
va.hwdata(waddr+3) := hwdata((127 mod AHBDW) downto (96 mod AHBDW));
end case;
when whold1 =>
va.state := whold2;
when whold2 =>
if ready = '1' then
va.state := midle; va.acc := (va.haddr, va.size, va.hwrite);
end if;
end case;
if (ahbsi.hready and ahbsi.hsel(hindex) ) = '1' then
if ahbsi.htrans(1) = '0' then va.hready := '1'; end if;
end if;
if rst = '0' then
va.hsel := '0';
va.hready := '1';
va.state := midle;
va.startsd := '0';
va.acc.hwrite := '0';
va.acc.haddr := (others => '0');
end if;
rai <= va;
end process;
ahbso.hready <= ra.hready;
ahbso.hresp <= ra.hresp;
ahbso.hrdata <= ahbdrivedata(ra.hrdata);
migi.app_addr <= '0' & ra.acc.haddr(28 downto 6) & "000";
ddr_ctrl : process(rst, r, ra, migo)
variable v : ddr_reg_type; -- local variables for registers
variable startsd : std_ulogic;
variable raddr : std_logic_vector(13 downto 0);
variable adec : std_ulogic;
variable haddr : std_logic_vector(31 downto 0);
variable hsize : std_logic_vector(1 downto 0);
variable hwrite : std_ulogic;
variable htrans : std_logic_vector(1 downto 0);
variable hready : std_ulogic;
variable app_en : std_ulogic;
variable app_cmd : std_logic_vector(2 downto 0);
variable app_wdf_mask : std_logic_vector(31 downto 0);
variable app_wdf_wren : std_ulogic;
variable app_wdf_end : std_ulogic;
variable app_wdf_data : std_logic_vector(255 downto 0);
begin
-- Variable default settings to avoid latches
v := r; app_en := '0'; app_cmd := "000";
app_wdf_wren := '0'; app_wdf_mask := ra.write(7) & ra.write(6) & ra.write(5) &
ra.write(4) & ra.write(3) & ra.write(2) & ra.write(1) & ra.write(0);
app_wdf_data := ra.hwdata(7) & ra.hwdata(6) & ra.hwdata(5) & ra.hwdata(4) &
ra.hwdata(3) & ra.hwdata(2) & ra.hwdata(1) & ra.hwdata(0);
if ra.acc.hwrite = '0' then app_cmd(0) := '1'; else app_cmd(0) := '0'; end if;
app_wdf_end := '0'; v.sync := ra.startsd;
if nosync = 0 then
if r.startsd /= r.sync then startsd := '1';
else startsd := '0'; end if;
else
if ra.startsd /= r.startsd then startsd := '1';
else startsd := '0'; end if;
end if;
case r.dstate is
when midle =>
if startsd = '1' then app_en := '1'; end if;
if (migo.app_rdy and app_en) = '1' then
if ra.acc.hwrite = '0' then v.dstate := dread;
else v.dstate := dwrite; end if;
end if;
when dread =>
if migo.app_rd_data_valid = '1' then
v.hrdata(255 downto 0) := migo.app_rd_data;
v.dstate := rhold;
end if;
when rhold =>
v.hrdata(511 downto 256) := migo.app_rd_data;
v.dstate := midle;
v.startsd := not r.startsd;
when dwrite =>
app_wdf_wren := '1';
if migo.app_wdf_rdy = '1' then
v.dstate := whold1;
end if;
when whold1 =>
app_wdf_wren := '1'; app_wdf_end := '1';
app_wdf_mask := ra.write(15) & ra.write(14) & ra.write(13) &
ra.write(12) & ra.write(11) & ra.write(10) & ra.write(9) & ra.write(8);
app_wdf_data := ra.hwdata(15) & ra.hwdata(14) & ra.hwdata(13) & ra.hwdata(12) &
ra.hwdata(11) & ra.hwdata(10) & ra.hwdata(9) & ra.hwdata(8);
if migo.app_wdf_rdy = '1' then
v.startsd := not r.startsd;
v.dstate := midle;
end if;
when others =>
end case;
-- reset
if rst = '0' then
v.startsd := '0';
end if;
ri <= v;
migi.app_cmd <= app_cmd;
migi.app_en <= app_en;
migi.app_wdf_wren <= app_wdf_wren;
migi.app_wdf_end <= app_wdf_end;
migi.app_wdf_mask <= not app_wdf_mask;
migi.app_wdf_data <= app_wdf_data;
end process;
ahbso.hconfig <= hconfig;
ahbso.hirq <= (others => '0');
ahbso.hindex <= hindex;
ahbso.hsplit <= (others => '0');
clk_ahb1 <= clk_ahb; clk_ahb2 <= clk_ahb1; -- sync clock deltas
ahbregs : process(clk_ahb2) begin
if rising_edge(clk_ahb2) then
ra <= rai;
end if;
end process;
ddrregs : process(clk_ddr, rst) begin
if rising_edge(clk_ddr) then
r <= ri;
end if;
end process;
-- Write data selection.
AHB32: if AHBDW = 32 generate
hwdata <= ahbsi.hwdata(31 downto 0) & ahbsi.hwdata(31 downto 0) &
ahbsi.hwdata(31 downto 0) & ahbsi.hwdata(31 downto 0);
end generate AHB32;
AHB64: if AHBDW = 64 generate
-- With CORE_ACDM set to 0 hwdata will always be ahbsi.hwdata(63 downto 0)
-- otherwise the valid data slice will be selected, and possibly uplicated,
-- from ahbsi.hwdata.
hwdatab(63 downto 0) <= ahbreaddword(ahbsi.hwdata, ra.haddr(4 downto 2)) when (CORE_ACDM = 0 or ra.size(1 downto 0) = "11") else
(ahbreadword(ahbsi.hwdata, ra.haddr(4 downto 2)) &
ahbreadword(ahbsi.hwdata, ra.haddr(4 downto 2)));
hwdata <= hwdatab(31 downto 0) & hwdatab(63 downto 32) &
hwdatab(31 downto 0) & hwdatab(63 downto 32);
end generate AHB64;
AHBWIDE: if AHBDW > 64 generate
-- With CORE_ACDM set to 0 hwdata will always be ahbsi.hwdata(127 downto 0)
-- otherwise the valid data slice will be selected, and possibly uplicated,
-- from ahbsi.hwdata.
hwdatab <= ahbread4word(ahbsi.hwdata, ra.haddr(4 downto 2)) when (CORE_ACDM = 0 or ra.size(2) = '1') else
(ahbreaddword(ahbsi.hwdata, ra.haddr(4 downto 2)) &
ahbreaddword(ahbsi.hwdata, ra.haddr(4 downto 2))) when (ra.size = "011") else
(ahbreadword(ahbsi.hwdata, ra.haddr(4 downto 2)) &
ahbreadword(ahbsi.hwdata, ra.haddr(4 downto 2)) &
ahbreadword(ahbsi.hwdata, ra.haddr(4 downto 2)) &
ahbreadword(ahbsi.hwdata, ra.haddr(4 downto 2)));
hwdata <= hwdatab(31 downto 0) & hwdatab(63 downto 32) &
hwdatab(95 downto 64) & hwdatab(127 downto 96);
end generate AHBWIDE;
-- pragma translate_off
bootmsg : report_version
generic map (
msg1 => "mig2ahb" & tost(hindex) & ": 64-bit DDR2/3 controller rev " &
tost(REVISION) & ", " & tost(Mbyte) & " Mbyte, " & tost(MHz) &
" MHz DDR clock");
-- pragma translate_on
end;
| gpl-3.0 | 0bb67159817db7bbf2021886ca31b6c5 | 0.570458 | 3.279851 | false | false | false | false |
EliasLuiz/TCC | Leon3/lib/techmap/maps/spictrl_net.vhd | 1 | 6,371 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-------------------------------------------------------------------------------
-- Entity: spictrl_net
-- File: spictrl_net.vhd
-- Author: Jan Andersson - Aeroflex Gaisler
-- Description: Netlist wrapper for SPICTRL core
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
use techmap.gencomp.all;
entity spictrl_net is
generic (
tech : integer range 0 to NTECH := 0;
fdepth : integer range 1 to 7 := 1;
slvselen : integer range 0 to 1 := 0;
slvselsz : integer range 1 to 32 := 1;
oepol : integer range 0 to 1 := 0;
odmode : integer range 0 to 1 := 0;
automode : integer range 0 to 1 := 0;
acntbits : integer range 1 to 32 := 32;
aslvsel : integer range 0 to 1 := 0;
twen : integer range 0 to 1 := 1;
maxwlen : integer range 0 to 15 := 0;
automask0 : integer := 0;
automask1 : integer := 0;
automask2 : integer := 0;
automask3 : integer := 0
);
port (
rstn : in std_ulogic;
clk : in std_ulogic;
-- APB signals
apbi_psel : in std_ulogic;
apbi_penable : in std_ulogic;
apbi_paddr : in std_logic_vector(31 downto 0);
apbi_pwrite : in std_ulogic;
apbi_pwdata : in std_logic_vector(31 downto 0);
apbi_testen : in std_ulogic;
apbi_testrst : in std_ulogic;
apbi_scanen : in std_ulogic;
apbi_testoen : in std_ulogic;
apbo_prdata : out std_logic_vector(31 downto 0);
apbo_pirq : out std_ulogic;
-- SPI signals
spii_miso : in std_ulogic;
spii_mosi : in std_ulogic;
spii_sck : in std_ulogic;
spii_spisel : in std_ulogic;
spii_astart : in std_ulogic;
spii_cstart : in std_ulogic;
spio_miso : out std_ulogic;
spio_misooen : out std_ulogic;
spio_mosi : out std_ulogic;
spio_mosioen : out std_ulogic;
spio_sck : out std_ulogic;
spio_sckoen : out std_ulogic;
spio_enable : out std_ulogic;
spio_astart : out std_ulogic;
spio_aready : out std_ulogic;
slvsel : out std_logic_vector((slvselsz-1) downto 0)
);
end entity spictrl_net;
architecture rtl of spictrl_net is
component spictrl_unisim
generic (
slvselen : integer range 0 to 1 := 0;
slvselsz : integer range 1 to 32 := 1);
port (
rstn : in std_ulogic;
clk : in std_ulogic;
-- APB signals
apbi_psel : in std_ulogic;
apbi_penable : in std_ulogic;
apbi_paddr : in std_logic_vector(31 downto 0);
apbi_pwrite : in std_ulogic;
apbi_pwdata : in std_logic_vector(31 downto 0);
apbi_testen : in std_ulogic;
apbi_testrst : in std_ulogic;
apbi_scanen : in std_ulogic;
apbi_testoen : in std_ulogic;
apbo_prdata : out std_logic_vector(31 downto 0);
apbo_pirq : out std_ulogic;
-- SPI signals
spii_miso : in std_ulogic;
spii_mosi : in std_ulogic;
spii_sck : in std_ulogic;
spii_spisel : in std_ulogic;
spii_astart : in std_ulogic;
spii_cstart : in std_ulogic;
spio_miso : out std_ulogic;
spio_misooen : out std_ulogic;
spio_mosi : out std_ulogic;
spio_mosioen : out std_ulogic;
spio_sck : out std_ulogic;
spio_sckoen : out std_ulogic;
spio_enable : out std_ulogic;
spio_astart : out std_ulogic;
spio_aready : out std_ulogic;
slvsel : out std_logic_vector((slvselsz-1) downto 0));
end component;
begin
xil : if false generate --(is_unisim(tech) = 1) generate
xilctrl : spictrl_unisim
generic map (
slvselen => slvselen,
slvselsz => slvselsz)
port map (
rstn => rstn,
clk => clk,
-- APB signals
apbi_psel => apbi_psel,
apbi_penable => apbi_penable,
apbi_paddr => apbi_paddr,
apbi_pwrite => apbi_pwrite,
apbi_pwdata => apbi_pwdata,
apbi_testen => apbi_testen,
apbi_testrst => apbi_testrst,
apbi_scanen => apbi_scanen,
apbi_testoen => apbi_testoen,
apbo_prdata => apbo_prdata,
apbo_pirq => apbo_pirq,
-- SPI signals
spii_miso => spii_miso,
spii_mosi => spii_mosi,
spii_sck => spii_sck,
spii_spisel => spii_spisel,
spii_astart => spii_astart,
spii_cstart => spii_cstart,
spio_miso => spio_miso,
spio_misooen => spio_misooen,
spio_mosi => spio_mosi,
spio_mosioen => spio_mosioen,
spio_sck => spio_sck,
spio_sckoen => spio_sckoen,
spio_enable => spio_enable,
spio_astart => spio_astart,
spio_aready => spio_aready,
slvsel => slvsel);
end generate;
-- pragma translate_off
nonet : if true generate --not ((is_unisim(tech) = 1)) generate
err : process
begin
assert false report "ERROR : No SPICTRL netlist available for this process!"
severity failure;
wait;
end process;
end generate;
-- pragma translate_on
end architecture;
| gpl-3.0 | 9fc6ace81bffaa6c0807d514effe3008 | 0.563334 | 3.769822 | false | true | false | false |
EliasLuiz/TCC | Leon3/designs/leon3-digilent-nexys3/testbench.vhd | 1 | 8,167 | -----------------------------------------------------------------------------
-- LEON3 Demonstration design test bench
-- Copyright (C) 2004 Jiri Gaisler, Gaisler Research
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library gaisler;
use gaisler.libdcom.all;
use gaisler.sim.all;
library techmap;
use techmap.gencomp.all;
use work.debug.all;
use work.config.all;
entity testbench is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
clktech : integer := CFG_CLKTECH;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW;
clkperiod : integer := 37; -- system clock period
romwidth : integer := 16; -- rom data width (8/32)
romdepth : integer := 16 -- rom address depth
);
end;
architecture behav of testbench is
constant promfile : string := "prom.srec"; -- rom contents
constant sdramfile : string := "ram.srec"; -- sdram contents
constant lresp : boolean := false;
constant ct : integer := clkperiod/2;
signal clk : std_logic := '0';
signal clk200p : std_logic := '1';
signal clk200n : std_logic := '0';
signal rst : std_logic := '0';
signal rstn1 : std_logic;
signal rstn2 : std_logic;
signal error : std_logic;
-- PROM flash
signal address : std_logic_vector(26 downto 0):=(others =>'0');
signal data : std_logic_vector(31 downto 0);
signal RamCS : std_logic;
signal oen : std_ulogic;
signal writen : std_ulogic;
signal iosn : std_ulogic;
signal FlashCS : std_ulogic;
-- Debug support unit
signal dsubre : std_ulogic;
-- AHB Uart
signal dsurx : std_ulogic;
signal dsutx : std_ulogic;
-- APB Uart
signal urxd : std_ulogic;
signal utxd : std_ulogic;
-- Ethernet signals
signal etx_clk : std_ulogic;
signal erx_clk : std_ulogic;
signal erxdt : std_logic_vector(7 downto 0);
signal erx_dv : std_ulogic;
signal erx_er : std_ulogic;
signal erx_col : std_ulogic;
signal erx_crs : std_ulogic;
signal etxdt : std_logic_vector(7 downto 0);
signal etx_en : std_ulogic;
signal etx_er : std_ulogic;
signal emdc : std_ulogic;
signal emdio : std_logic;
-- SVGA signals
signal vid_hsync : std_ulogic;
signal vid_vsync : std_ulogic;
signal vid_r : std_logic_vector(3 downto 0);
signal vid_g : std_logic_vector(3 downto 0);
signal vid_b : std_logic_vector(3 downto 0);
-- Select signal for SPI flash
signal spi_sel_n : std_logic;
signal spi_clk : std_logic;
signal spi_mosi : std_logic;
-- Output signals for LEDs
signal led : std_logic_vector(7 downto 0);
signal brdyn : std_ulogic;
signal sw : std_logic_vector(7 downto 0):= (others =>'0');
signal btn : std_logic_vector(4 downto 0):= (others =>'0');
begin
-- clock and reset
clk <= not clk after ct * 1 ns;
rst <= '1', '0' after 100 ns;
dsubre <= '0';
urxd <= 'H';
spi_sel_n <= 'H';
spi_clk <= 'L';
d3 : entity work.leon3mp
generic map (fabtech, memtech, padtech, clktech, disas, dbguart, pclow)
port map (
clk => clk,
-- PROM
address => address(25 downto 0),
data => data(31 downto 16),
MemOE => oen,
MemWR => writen,
RamCS => RamCS,
--FlashRp => FlashRP
FlashCS => FlashCS,
-- AHB Uart
RsRx => dsurx,
RsTx => dsutx,
-- PHY
PhyTxClk => etx_clk,
PhyRxClk => erx_clk,
PhyRxd => erxdt(3 downto 0),
PhyRxDv => erx_dv,
PhyRxEr => erx_er,
PhyCol => erx_col,
PhyCrs => erx_crs,
PhyTxd => etxdt(3 downto 0),
PhyTxEn => etx_en,
PhyTxEr => etx_er,
PhyMdc => emdc,
PhyMdio => emdio,
-- Output signals for LEDs
led => led,
sw => sw,
btn => btn
);
btn(0) <= rst;
prom0 : for i in 0 to (romwidth/8)-1 generate
sr0 : sram generic map (index => 4+i, abits => romdepth, fname => promfile)--index => i
port map (address(romdepth-1 downto 0), data(31-i*8 downto 24-i*8), FlashCS,
writen, oen);
end generate;
sram0 : sram
generic map (index => 4, abits => 24, fname => sdramfile)
port map (address(23 downto 0), data(31 downto 24), RamCS, writen, oen);
sram1 : sram
generic map (index => 5, abits => 24, fname => sdramfile)
port map (address(23 downto 0), data(23 downto 16), RamCS, writen, oen);
phy0 : if (CFG_GRETH = 1) generate
emdio <= 'H';
p0: phy
generic map (address => 1)
port map(rstn1, emdio, etx_clk, erx_clk, erxdt, erx_dv, erx_er,
erx_col, erx_crs, etxdt, etx_en, etx_er, emdc, '0');
end generate;
spimem0: if CFG_SPIMCTRL = 1 generate
s0 : spi_flash generic map (ftype => 4, debug => 0, fname => promfile,
readcmd => CFG_SPIMCTRL_READCMD,
dummybyte => CFG_SPIMCTRL_DUMMYBYTE,
dualoutput => 0) -- Dual output is not supported in this design
port map (spi_clk, spi_mosi, data(24), spi_sel_n);
end generate spimem0;
led(3) <= 'L'; -- ERROR pull-down
error <= not led(3);
iuerr : process
begin
wait for 5 us;
assert (to_X01(error) = '1')
report "*** IU in error mode, simulation halted ***"
severity failure;
end process;
test0 : grtestmod
port map ( rst, clk, error, address(21 downto 2), data, iosn, oen, writen, brdyn);
data <= buskeep(data) after 5 ns;
dsucom : process
procedure dsucfg(signal dsurx : in std_ulogic; signal dsutx : out std_ulogic) is
variable w32 : std_logic_vector(31 downto 0);
variable c8 : std_logic_vector(7 downto 0);
constant txp : time := 160 * 1 ns;
begin
dsutx <= '1';
wait;
wait for 5000 ns;
txc(dsutx, 16#55#, txp); -- sync uart
txc(dsutx, 16#a0#, txp);
txa(dsutx, 16#40#, 16#00#, 16#00#, 16#00#, txp);
rxi(dsurx, w32, txp, lresp);
-- txc(dsutx, 16#c0#, txp);
-- txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp);
-- txa(dsutx, 16#00#, 16#00#, 16#00#, 16#ef#, txp);
--
-- txc(dsutx, 16#c0#, txp);
-- txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
-- txa(dsutx, 16#00#, 16#00#, 16#ff#, 16#ff#, txp);
--
-- txc(dsutx, 16#c0#, txp);
-- txa(dsutx, 16#90#, 16#40#, 16#00#, 16#48#, txp);
-- txa(dsutx, 16#00#, 16#00#, 16#00#, 16#12#, txp);
--
-- txc(dsutx, 16#c0#, txp);
-- txa(dsutx, 16#90#, 16#40#, 16#00#, 16#60#, txp);
-- txa(dsutx, 16#00#, 16#00#, 16#12#, 16#10#, txp);
--
-- txc(dsutx, 16#80#, txp);
-- txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp);
-- rxi(dsurx, w32, txp, lresp);
end;
begin
dsucfg(dsutx, dsurx);
wait;
end process;
end;
| gpl-3.0 | a25a0d1d3a3dee176e197522cd6be3b3 | 0.563855 | 3.526339 | false | false | false | false |
EliasLuiz/TCC | Leon3/designs/leon3-xilinx-xc3sd-1800/testbench.vhd | 1 | 10,755 | -----------------------------------------------------------------------------
-- LEON3 Demonstration design test bench
-- Copyright (C) 2004 Jiri Gaisler, Gaisler Research
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library gaisler;
use gaisler.libdcom.all;
use gaisler.sim.all;
library techmap;
use techmap.gencomp.all;
library micron;
use micron.components.all;
use work.debug.all;
use work.config.all;
entity testbench is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
clktech : integer := CFG_CLKTECH;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW;
clkperiod : integer := 8 -- system clock period
);
end;
architecture behav of testbench is
constant promfile : string := "prom.srec"; -- rom contents
constant sdramfile : string := "ram.srec"; -- sdram contents
constant lresp : boolean := false;
constant ct : integer := clkperiod/2;
signal clk : std_logic := '0';
signal clk_vga : std_logic := '0';
signal rst : std_logic := '0';
signal rstn1 : std_logic;
signal rstn2 : std_logic;
signal error : std_logic;
-- PROM flash
signal address : std_logic_vector(23 downto 0);
signal data : std_logic_vector(31 downto 0);
signal romsn : std_logic;
signal oen : std_ulogic;
signal writen : std_ulogic;
signal iosn : std_ulogic;
-- DDR2 memory
signal ddr_clk : std_logic_vector(1 downto 0);
signal ddr_clkb : std_logic_vector(1 downto 0);
signal ddr_clk_fb : std_logic;
signal ddr_cke : std_logic;
signal ddr_csb : std_logic;
signal ddr_we : std_ulogic; -- write enable
signal ddr_ras : std_ulogic; -- ras
signal ddr_cas : std_ulogic; -- cas
signal ddr_dm : std_logic_vector(3 downto 0); -- dm
signal ddr_dqs : std_logic_vector(3 downto 0); -- dqs
signal ddr_dqsn : std_logic_vector(3 downto 0); -- dqsn
signal ddr_ad : std_logic_vector(12 downto 0); -- address
signal ddr_ba : std_logic_vector(1 downto 0); -- bank address
signal ddr_dq : std_logic_vector(31 downto 0); -- data
signal ddr_dq2 : std_logic_vector(31 downto 0); -- data
signal ddr_odt : std_logic;
-- Debug support unit
signal dsubre : std_ulogic;
-- AHB Uart
signal dsurx : std_ulogic;
signal dsutx : std_ulogic;
-- APB Uart
signal urxd : std_ulogic;
signal utxd : std_ulogic;
-- Ethernet signals
signal etx_clk : std_ulogic;
signal erx_clk : std_ulogic;
signal erxdt : std_logic_vector(7 downto 0);
signal erx_dv : std_ulogic;
signal erx_er : std_ulogic;
signal erx_col : std_ulogic;
signal erx_crs : std_ulogic;
signal etxdt : std_logic_vector(7 downto 0);
signal etx_en : std_ulogic;
signal etx_er : std_ulogic;
signal emdc : std_ulogic;
signal emdio : std_logic;
-- SVGA signals
signal vid_hsync : std_ulogic;
signal vid_vsync : std_ulogic;
signal vid_r : std_logic_vector(3 downto 0);
signal vid_g : std_logic_vector(3 downto 0);
signal vid_b : std_logic_vector(3 downto 0);
-- Select signal for SPI flash
signal spi_sel_n : std_logic;
signal spi_clk : std_logic;
signal spi_mosi : std_logic;
-- Output signals for LEDs
signal led : std_logic_vector(2 downto 0);
signal brdyn : std_ulogic;
begin
-- clock and reset
clk <= not clk after ct * 1 ns;
clk_vga <= not clk_vga after 20 ns;
rst <= '1', '0' after 100 ns;
dsubre <= '0';
urxd <= 'H';
spi_sel_n <= 'H';
spi_clk <= 'L';
d3 : entity work.leon3mp
generic map (fabtech, memtech, padtech, clktech, disas, dbguart, pclow)
port map (
reset => rst,
reset_o1 => rstn1,
reset_o2 => rstn2,
clk_in => clk,
clk_vga => clk_vga,
errorn => error,
-- PROM
address => address(23 downto 0),
data => data(31 downto 24),
romsn => romsn,
oen => oen,
writen => writen,
iosn => iosn,
testdata => data(23 downto 0),
-- DDR2
ddr_clk => ddr_clk,
ddr_clkb => ddr_clkb,
ddr_clk_fb_out => ddr_clk_fb,
ddr_clk_fb => ddr_clk_fb,
ddr_cke => ddr_cke,
ddr_csb => ddr_csb,
ddr_we => ddr_we,
ddr_ras => ddr_ras,
ddr_cas => ddr_cas,
ddr_dm => ddr_dm,
ddr_dqs => ddr_dqs,
ddr_dqsn => ddr_dqsn,
ddr_ad => ddr_ad,
ddr_ba => ddr_ba,
ddr_dq => ddr_dq,
ddr_odt => ddr_odt,
-- Debug Unit
dsubre => dsubre,
-- AHB Uart
dsutx => dsutx,
dsurx => dsurx,
-- PHY
etx_clk => etx_clk,
erx_clk => erx_clk,
erxd => erxdt(3 downto 0),
erx_dv => erx_dv,
erx_er => erx_er,
erx_col => erx_col,
erx_crs => erx_crs,
etxd => etxdt(3 downto 0),
etx_en => etx_en,
etx_er => etx_er,
emdc => emdc,
emdio => emdio,
-- SVGA
vid_hsync => vid_hsync,
vid_vsync => vid_vsync,
vid_r => vid_r,
vid_g => vid_g,
vid_b => vid_b,
-- SPI flash select
spi_sel_n => spi_sel_n,
spi_clk => spi_clk,
spi_mosi => spi_mosi,
-- Output signals for LEDs
led => led
);
ddr2mem : if (CFG_DDR2SP /= 0) generate
-- ddr2mem0 : for i in 0 to 1 generate
-- u1 : HY5PS121621F
-- generic map (TimingCheckFlag => true, PUSCheckFlag => false,
-- index => 1-i, bbits => 32, fname => sdramfile)
-- port map (DQ => ddr_dq2(i*16+15 downto i*16),
-- LDQS => ddr_dqs(i*2), LDQSB => ddr_dqsn(i*2),
-- UDQS => ddr_dqs(i*2+1), UDQSB => ddr_dqsn(i*2+1),
-- LDM => ddr_dm(i*2), WEB => ddr_we, CASB => ddr_cas,
-- RASB => ddr_ras, CSB => ddr_csb, BA => ddr_ba,
-- ADDR => ddr_ad(12 downto 0), CKE => ddr_cke,
-- CLK => ddr_clk(i), CLKB => ddr_clkb(i), UDM => ddr_dm(i*2+1));
-- end generate;
ddr0 : ddr2ram
generic map(width => 32, abits => 13, babits =>2, colbits => 10, rowbits => 13,
implbanks => 1, fname => sdramfile, speedbin=>1, density => 2)
port map (ck => ddr_clk(0), ckn => ddr_clkb(0), cke => ddr_cke, csn => ddr_csb,
odt => ddr_odt, rasn => ddr_ras, casn => ddr_cas, wen => ddr_we,
dm => ddr_dm, ba => ddr_ba(1 downto 0), a => ddr_ad(12 downto 0), dq => ddr_dq2,
dqs => ddr_dqs);
ddr2delay0 : delay_wire
generic map(data_width => ddr_dq'length, delay_atob => 0.0, delay_btoa => 1.0)
port map(a => ddr_dq, b => ddr_dq2);
end generate;
prom0 : sram
generic map (index => 6, abits => 24, fname => promfile)
port map (address(23 downto 0), data(31 downto 24), romsn, writen, oen);
phy0 : if (CFG_GRETH = 1) generate
etxdt(7 downto 4) <= "0000";
emdio <= 'H';
p0: phy
generic map (address => 1)
port map(rstn1, emdio, etx_clk, erx_clk, erxdt, erx_dv, erx_er,
erx_col, erx_crs, etxdt, etx_en, etx_er, emdc, '0');
end generate;
spimem0: if CFG_SPIMCTRL = 1 generate
s0 : spi_flash generic map (ftype => 4, debug => 0, fname => promfile,
readcmd => CFG_SPIMCTRL_READCMD,
dummybyte => CFG_SPIMCTRL_DUMMYBYTE,
dualoutput => 0) -- Dual output is not supported in this design
port map (spi_clk, spi_mosi, data(24), spi_sel_n);
end generate spimem0;
error <= 'H'; -- ERROR pull-up
iuerr : process
begin
wait for 5 us;
assert (to_X01(error) = '1')
report "*** IU in error mode, simulation halted ***"
severity failure;
end process;
test0 : grtestmod
port map ( rst, clk, error, address(21 downto 2), data, iosn, oen, writen, brdyn);
data <= buskeep(data) after 5 ns;
dsucom : process
procedure dsucfg(signal dsurx : in std_ulogic; signal dsutx : out std_ulogic) is
variable w32 : std_logic_vector(31 downto 0);
variable c8 : std_logic_vector(7 downto 0);
constant txp : time := 160 * 1 ns;
begin
dsutx <= '1';
wait;
wait for 5000 ns;
txc(dsutx, 16#55#, txp); -- sync uart
txc(dsutx, 16#a0#, txp);
txa(dsutx, 16#40#, 16#00#, 16#00#, 16#00#, txp);
rxi(dsurx, w32, txp, lresp);
-- txc(dsutx, 16#c0#, txp);
-- txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp);
-- txa(dsutx, 16#00#, 16#00#, 16#00#, 16#ef#, txp);
--
-- txc(dsutx, 16#c0#, txp);
-- txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
-- txa(dsutx, 16#00#, 16#00#, 16#ff#, 16#ff#, txp);
--
-- txc(dsutx, 16#c0#, txp);
-- txa(dsutx, 16#90#, 16#40#, 16#00#, 16#48#, txp);
-- txa(dsutx, 16#00#, 16#00#, 16#00#, 16#12#, txp);
--
-- txc(dsutx, 16#c0#, txp);
-- txa(dsutx, 16#90#, 16#40#, 16#00#, 16#60#, txp);
-- txa(dsutx, 16#00#, 16#00#, 16#12#, 16#10#, txp);
--
-- txc(dsutx, 16#80#, txp);
-- txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp);
-- rxi(dsurx, w32, txp, lresp);
end;
begin
dsucfg(dsutx, dsurx);
wait;
end process;
end;
| gpl-3.0 | 9702351aabc11174639d07ebaa510075 | 0.536867 | 3.404558 | false | false | false | false |
tmeissner/vhdl_verification | psl_test_endpoint/psl_test_endpoint.vhd | 1 | 1,150 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library std;
use std.env.all;
entity psl_test_endpoint is
end entity psl_test_endpoint;
architecture test of psl_test_endpoint is
signal s_rst_n : std_logic := '0';
signal s_clk : std_logic := '0';
signal s_write : std_logic;
signal s_read : std_logic;
begin
s_rst_n <= '1' after 100 ns;
s_clk <= not s_clk after 10 ns;
TestP : process is
begin
report "RUNNING psl_test_endpoint test case";
report "==========================================";
s_write <= '0'; -- named assertion should hit
s_read <= '0';
wait until s_rst_n = '1' and rising_edge(s_clk);
s_write <= '1';
wait until rising_edge(s_clk);
s_read <= '1'; -- assertion should hit
wait until rising_edge(s_clk);
s_write <= '0';
s_read <= '0';
wait until rising_edge(s_clk);
stop(0);
wait;
end process TestP;
-- psl default clock is rising_edge(s_clk);
-- psl endpoint E_TEST0 is {not(s_write); s_write};
process is
begin
wait until E_TEST0;
report "HIT";
wait;
end process;
end architecture test;
| lgpl-3.0 | 475f836b66daef48f541c0733d7d1e0c | 0.589565 | 3.125 | false | true | false | false |
hoglet67/CoPro6502 | test/TestBenchZ80.vhd | 1 | 8,106 | --------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 20:24:00 10/29/2014
-- Design Name:
-- Module Name: /home/dmb/atom/CoPro6502/TestBench.vhd
-- Project Name: CoPro6502
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: CoPro6502
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE std.textio.all;
USE ieee.std_logic_textio.all;
use work.txt_util.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY TestBenchZ80 IS
END TestBenchZ80;
ARCHITECTURE behavior OF TestBenchZ80 IS
--task para_write;
-- input [2:0] addr;
-- input [7:0] data;
-- begin
-- @ (negedge HO2);
-- PA = addr;
-- PDIN = data;
-- PNWDS = 0;
-- PCS = 0;
-- @ (negedge HO2);
-- PCS = 1;
-- PA = "000;
-- PDIN = "00000000;
-- PNWDS = 1;
-- end
-- endtask
-- task para_read;
-- input [2:0] addr;
-- input [7:0] expected_mask;
-- input [7:0] expected_data;
-- begin
-- @ (negedge HO2);
-- PA = addr;
-- PNRDS = 0;
-- PCS = 0;
-- @ (posedge HO2);
-- if ((PDOUT & expected_mask) != expected_data)
-- $display("%0dns: para addr %0d data error detected; expected_mask = %b; expected_data = %b; actual_data = %b", $time, PA, expected_mask, expected_data, PDOUT);
-- @ (negedge HO2);
-- PCS = 1;
-- PA = "000;
-- PNRDS = 1;
-- end
-- endtask
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT CoProZ80
PORT(
fastclk : IN std_logic;
tp : OUT std_logic_vector(8 downto 2);
sw : IN std_logic_vector(2 downto 1);
fcs : OUT std_logic;
h_phi2 : IN std_logic;
h_addr : IN std_logic_vector(2 downto 0);
h_data : INOUT std_logic_vector(7 downto 0);
h_rdnw : IN std_logic;
h_cs_b : IN std_logic;
h_rst_b : IN std_logic;
h_irq_b : INOUT std_logic;
ram_cs : OUT std_logic;
ram_oe : OUT std_logic;
ram_wr : OUT std_logic;
ram_addr : OUT std_logic_vector(18 downto 0);
ram_data : INOUT std_logic_vector(7 downto 0)
);
END COMPONENT;
COMPONENT SRAM
PORT(
ADDR : in std_logic_vector(15 downto 0);
DATA : inout std_logic_vector(7 downto 0);
OE : in std_logic;
WE : in std_logic;
CS : in std_logic
);
END COMPONENT;
--Inputs
signal fastclk : std_logic := '0';
signal sw : std_logic_vector(2 downto 1) := (others => '0');
signal h_phi2 : std_logic := '0';
signal h_addr : std_logic_vector(2 downto 0) := (others => '0');
signal h_rdnw : std_logic := '1';
signal h_cs_b : std_logic := '1';
signal h_rst_b : std_logic := '1';
--BiDirs
signal h_data : std_logic_vector(7 downto 0);
signal h_irq_b : std_logic;
signal ram_data : std_logic_vector(7 downto 0);
--Outputs
signal tp : std_logic_vector(8 downto 2);
signal fcs : std_logic;
signal ram_cs : std_logic;
signal ram_oe : std_logic;
signal ram_wr : std_logic;
signal ram_addr : std_logic_vector(18 downto 0);
-- Clock period definitions
constant fastclk_period : time := 10 ns;
constant phi2_period : time := 250 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: CoProZ80 PORT MAP (
fastclk => fastclk,
tp => tp,
sw => sw,
fcs => fcs,
h_phi2 => h_phi2,
h_addr => h_addr,
h_data => h_data,
h_rdnw => h_rdnw,
h_cs_b => h_cs_b,
h_rst_b => h_rst_b,
h_irq_b => h_irq_b,
ram_cs => ram_cs,
ram_oe => ram_oe,
ram_wr => ram_wr,
ram_addr => ram_addr,
ram_data => ram_data
);
inst_sram: SRAM PORT MAP (
ADDR => ram_addr(15 downto 0),
DATA => ram_data,
OE => ram_oe,
WE => ram_wr,
CS => ram_cs
);
-- Clock process definitions
fastclk_process :process
begin
fastclk <= '0';
wait for fastclk_period/2;
fastclk <= '1';
wait for fastclk_period/2;
end process;
phi2_process :process
begin
h_phi2 <= '0';
wait for phi2_period/2;
h_phi2 <= '1';
wait for phi2_period/2;
end process;
-- Stimulus process
stim_proc: process
procedure host_write (
addr : in std_logic_vector(2 downto 0);
data : in std_logic_vector(7 downto 0)
) is
begin
wait until falling_edge(h_phi2);
h_addr <= addr;
h_data <= data;
h_rdnw <= '0';
h_cs_b <= '0';
wait until falling_edge(h_phi2);
h_cs_b <= '1';
h_addr <= "000";
h_data <= "ZZZZZZZZ";
h_rdnw <= '1';
end host_write;
procedure delay (
n : in integer
) is
begin
for i in 0 to n loop
wait until falling_edge(h_phi2);
end loop;
end delay;
procedure host_read (
addr : in std_logic_vector(2 downto 0);
expected_mask : in std_logic_vector(7 downto 0);
expected_data : in std_logic_vector(7 downto 0)
) is
begin
wait until falling_edge(h_phi2);
h_addr <= addr;
h_rdnw <= '1';
h_cs_b <= '0';
wait until falling_edge(h_phi2);
if ((h_data and expected_mask) /= expected_data) then
report " data error detected: host addr" & str(h_addr) severity note;
report " expected_mask = " & str(expected_mask) severity note;
report " expected_data = " & str(expected_data) severity note;
report " actual_data = " & str(h_data) severity note;
end if;
wait until falling_edge(h_phi2);
h_cs_b <= '1';
h_addr <= "000";
h_rdnw <= '1';
end host_read;
begin
-- hold reset state for 100 ns.
wait for 100 ns;
wait until falling_edge(h_phi2);
h_rst_b <= '0';
for i in 0 to 99 loop
wait until falling_edge(h_phi2);
end loop;
h_rst_b <= '1';
wait for 1 ms;
delay(10);
-- Take PRST high, low, high
host_write("000", "00100000");
host_write("000", "10100000");
host_write("000", "00100000");
host_read("000", "00000000", "00000000");
delay(10);
-- De-Assert soft reset (up until this point it will be X)
host_write("000", "01000000");
delay(10);
-- Assert soft reset for atleast 24 clocks to flush the 24 byte FIFO
host_write("000", "11000000");
delay(50);
-- De-Assert soft reset
host_write("000", "01000000");
delay(10);
-- Disable all interrupts
host_write("000", "00001111");
-- Set two byte mode for register 3
host_write("000", "00010000");
-- Enable NMI (M=1)
host_write("000", "10001000");
-- Check the control bits are as expected
host_read("000", "11111111", "01001000");
-- Read the junk byte out of register 3
-- para_read("100", "11000000", "00000000"); -- N=0 _F=0
-- host_read("101", "00000000", "00000000");
-- para_read("100", "11000000", "11000000"); -- N=1 _F=1
delay(10);
wait for 1000 ms;
end process;
END;
| gpl-3.0 | d3f2fa4a67aff39ab369c5a347b8e7a4 | 0.525783 | 3.434746 | false | false | false | false |
EliasLuiz/TCC | Leon3/lib/gaisler/srmmu/mmulrue.vhd | 1 | 3,786 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: mmulrue
-- File: mmulrue.vhd
-- Author: Konrad Eisele, Jiri Gaisler, Gaisler Research
-- Description: MMU LRU logic
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.config_types.all;
use grlib.config.all;
use grlib.amba.all;
use grlib.stdlib.all;
library gaisler;
use gaisler.mmuconfig.all;
use gaisler.mmuiface.all;
entity mmulrue is
generic (
position : integer;
entries : integer := 8 );
port (
rst : in std_logic;
clk : in std_logic;
lruei : in mmulrue_in_type;
lrueo : out mmulrue_out_type );
end mmulrue;
architecture rtl of mmulrue is
constant entries_log : integer := log2(entries);
type lru_rtype is record
pos : std_logic_vector(entries_log-1 downto 0);
movetop : std_logic;
end record;
constant RESET_ALL : boolean := GRLIB_CONFIG_ARRAY(grlib_sync_reset_enable_all) = 1;
constant ASYNC_RESET : boolean := GRLIB_CONFIG_ARRAY(grlib_async_reset_enable) = 1;
signal c,r : lru_rtype;
begin
p0: process (rst, r, lruei)
variable v : lru_rtype;
variable ov : mmulrue_out_type;
begin
v := r; ov := mmulrue_out_none;
-- #init
if (r.movetop) = '1' then
if (lruei.fromleft) = '0' then
v.pos := lruei.left(entries_log-1 downto 0);
v.movetop := '0';
end if;
elsif (lruei.fromright) = '1' then
v.pos := lruei.right(entries_log-1 downto 0);
v.movetop := not lruei.clear;
end if;
if (lruei.touch and not lruei.clear) = '1' then -- touch request
if (v.pos = lruei.pos(entries_log-1 downto 0)) then -- check
v.movetop := '1';
end if;
end if;
if ((not ASYNC_RESET) and (not RESET_ALL) and (rst = '0')) or (lruei.flush = '1') then
v.pos := conv_std_logic_vector(position, entries_log);
v.movetop := '0';
end if;
--# Drive signals
ov.pos(entries_log-1 downto 0) := r.pos;
ov.movetop := r.movetop;
lrueo <= ov;
c <= v;
end process p0;
syncrregs : if not ASYNC_RESET generate
p1: process (clk)
begin
if rising_edge(clk) then
r <= c;
if RESET_ALL and (rst = '0') then
r.pos <= conv_std_logic_vector(position, entries_log);
r.movetop <= '0';
end if;
end if;
end process p1;
end generate;
asyncrregs : if ASYNC_RESET generate
p1: process (clk, rst)
begin
if rst = '0' then
r.pos <= conv_std_logic_vector(position, entries_log);
r.movetop <= '0';
elsif rising_edge(clk) then
r <= c;
end if;
end process p1;
end generate;
end rtl;
| gpl-3.0 | 3a31ceebc0226776a88f3935e5c635d0 | 0.591125 | 3.629914 | false | false | false | false |
GLADICOS/SPACEWIRESYSTEMC | altera_work/spw_fifo_ulight/ulight_fifo/ulight_fifo_inst.vhd | 1 | 12,168 | component ulight_fifo is
port (
auto_start_external_connection_export : out std_logic; -- export
clk_clk : in std_logic := 'X'; -- clk
clock_sel_external_connection_export : out std_logic_vector(2 downto 0); -- export
counter_rx_fifo_external_connection_export : in std_logic_vector(5 downto 0) := (others => 'X'); -- export
counter_tx_fifo_external_connection_export : in std_logic_vector(5 downto 0) := (others => 'X'); -- export
data_flag_rx_external_connection_export : in std_logic_vector(8 downto 0) := (others => 'X'); -- export
data_info_external_connection_export : in std_logic_vector(13 downto 0) := (others => 'X'); -- export
data_read_en_rx_external_connection_export : out std_logic; -- export
fifo_empty_rx_status_external_connection_export : in std_logic := 'X'; -- export
fifo_empty_tx_status_external_connection_export : in std_logic := 'X'; -- export
fifo_full_rx_status_external_connection_export : in std_logic := 'X'; -- export
fifo_full_tx_status_external_connection_export : in std_logic := 'X'; -- export
fsm_info_external_connection_export : in std_logic_vector(5 downto 0) := (others => 'X'); -- export
led_pio_test_external_connection_export : out std_logic_vector(4 downto 0); -- export
link_disable_external_connection_export : out std_logic; -- export
link_start_external_connection_export : out std_logic; -- export
memory_mem_a : out std_logic_vector(12 downto 0); -- mem_a
memory_mem_ba : out std_logic_vector(2 downto 0); -- mem_ba
memory_mem_ck : out std_logic; -- mem_ck
memory_mem_ck_n : out std_logic; -- mem_ck_n
memory_mem_cke : out std_logic; -- mem_cke
memory_mem_cs_n : out std_logic; -- mem_cs_n
memory_mem_ras_n : out std_logic; -- mem_ras_n
memory_mem_cas_n : out std_logic; -- mem_cas_n
memory_mem_we_n : out std_logic; -- mem_we_n
memory_mem_reset_n : out std_logic; -- mem_reset_n
memory_mem_dq : inout std_logic_vector(7 downto 0) := (others => 'X'); -- mem_dq
memory_mem_dqs : inout std_logic := 'X'; -- mem_dqs
memory_mem_dqs_n : inout std_logic := 'X'; -- mem_dqs_n
memory_mem_odt : out std_logic; -- mem_odt
memory_mem_dm : out std_logic; -- mem_dm
memory_oct_rzqin : in std_logic := 'X'; -- oct_rzqin
pll_0_locked_export : out std_logic; -- export
pll_0_outclk0_clk : out std_logic; -- clk
reset_reset_n : in std_logic := 'X'; -- reset_n
timecode_ready_rx_external_connection_export : in std_logic := 'X'; -- export
timecode_rx_external_connection_export : in std_logic_vector(7 downto 0) := (others => 'X'); -- export
timecode_tx_data_external_connection_export : out std_logic_vector(7 downto 0); -- export
timecode_tx_enable_external_connection_export : out std_logic; -- export
timecode_tx_ready_external_connection_export : in std_logic := 'X'; -- export
write_data_fifo_tx_external_connection_export : out std_logic_vector(8 downto 0); -- export
write_en_tx_external_connection_export : out std_logic -- export
);
end component ulight_fifo;
u0 : component ulight_fifo
port map (
auto_start_external_connection_export => CONNECTED_TO_auto_start_external_connection_export, -- auto_start_external_connection.export
clk_clk => CONNECTED_TO_clk_clk, -- clk.clk
clock_sel_external_connection_export => CONNECTED_TO_clock_sel_external_connection_export, -- clock_sel_external_connection.export
counter_rx_fifo_external_connection_export => CONNECTED_TO_counter_rx_fifo_external_connection_export, -- counter_rx_fifo_external_connection.export
counter_tx_fifo_external_connection_export => CONNECTED_TO_counter_tx_fifo_external_connection_export, -- counter_tx_fifo_external_connection.export
data_flag_rx_external_connection_export => CONNECTED_TO_data_flag_rx_external_connection_export, -- data_flag_rx_external_connection.export
data_info_external_connection_export => CONNECTED_TO_data_info_external_connection_export, -- data_info_external_connection.export
data_read_en_rx_external_connection_export => CONNECTED_TO_data_read_en_rx_external_connection_export, -- data_read_en_rx_external_connection.export
fifo_empty_rx_status_external_connection_export => CONNECTED_TO_fifo_empty_rx_status_external_connection_export, -- fifo_empty_rx_status_external_connection.export
fifo_empty_tx_status_external_connection_export => CONNECTED_TO_fifo_empty_tx_status_external_connection_export, -- fifo_empty_tx_status_external_connection.export
fifo_full_rx_status_external_connection_export => CONNECTED_TO_fifo_full_rx_status_external_connection_export, -- fifo_full_rx_status_external_connection.export
fifo_full_tx_status_external_connection_export => CONNECTED_TO_fifo_full_tx_status_external_connection_export, -- fifo_full_tx_status_external_connection.export
fsm_info_external_connection_export => CONNECTED_TO_fsm_info_external_connection_export, -- fsm_info_external_connection.export
led_pio_test_external_connection_export => CONNECTED_TO_led_pio_test_external_connection_export, -- led_pio_test_external_connection.export
link_disable_external_connection_export => CONNECTED_TO_link_disable_external_connection_export, -- link_disable_external_connection.export
link_start_external_connection_export => CONNECTED_TO_link_start_external_connection_export, -- link_start_external_connection.export
memory_mem_a => CONNECTED_TO_memory_mem_a, -- memory.mem_a
memory_mem_ba => CONNECTED_TO_memory_mem_ba, -- .mem_ba
memory_mem_ck => CONNECTED_TO_memory_mem_ck, -- .mem_ck
memory_mem_ck_n => CONNECTED_TO_memory_mem_ck_n, -- .mem_ck_n
memory_mem_cke => CONNECTED_TO_memory_mem_cke, -- .mem_cke
memory_mem_cs_n => CONNECTED_TO_memory_mem_cs_n, -- .mem_cs_n
memory_mem_ras_n => CONNECTED_TO_memory_mem_ras_n, -- .mem_ras_n
memory_mem_cas_n => CONNECTED_TO_memory_mem_cas_n, -- .mem_cas_n
memory_mem_we_n => CONNECTED_TO_memory_mem_we_n, -- .mem_we_n
memory_mem_reset_n => CONNECTED_TO_memory_mem_reset_n, -- .mem_reset_n
memory_mem_dq => CONNECTED_TO_memory_mem_dq, -- .mem_dq
memory_mem_dqs => CONNECTED_TO_memory_mem_dqs, -- .mem_dqs
memory_mem_dqs_n => CONNECTED_TO_memory_mem_dqs_n, -- .mem_dqs_n
memory_mem_odt => CONNECTED_TO_memory_mem_odt, -- .mem_odt
memory_mem_dm => CONNECTED_TO_memory_mem_dm, -- .mem_dm
memory_oct_rzqin => CONNECTED_TO_memory_oct_rzqin, -- .oct_rzqin
pll_0_locked_export => CONNECTED_TO_pll_0_locked_export, -- pll_0_locked.export
pll_0_outclk0_clk => CONNECTED_TO_pll_0_outclk0_clk, -- pll_0_outclk0.clk
reset_reset_n => CONNECTED_TO_reset_reset_n, -- reset.reset_n
timecode_ready_rx_external_connection_export => CONNECTED_TO_timecode_ready_rx_external_connection_export, -- timecode_ready_rx_external_connection.export
timecode_rx_external_connection_export => CONNECTED_TO_timecode_rx_external_connection_export, -- timecode_rx_external_connection.export
timecode_tx_data_external_connection_export => CONNECTED_TO_timecode_tx_data_external_connection_export, -- timecode_tx_data_external_connection.export
timecode_tx_enable_external_connection_export => CONNECTED_TO_timecode_tx_enable_external_connection_export, -- timecode_tx_enable_external_connection.export
timecode_tx_ready_external_connection_export => CONNECTED_TO_timecode_tx_ready_external_connection_export, -- timecode_tx_ready_external_connection.export
write_data_fifo_tx_external_connection_export => CONNECTED_TO_write_data_fifo_tx_external_connection_export, -- write_data_fifo_tx_external_connection.export
write_en_tx_external_connection_export => CONNECTED_TO_write_en_tx_external_connection_export -- write_en_tx_external_connection.export
);
| gpl-3.0 | 4983e018ee1e31a18fd04bfb55dc4af5 | 0.45595 | 4.457143 | false | false | false | false |
EliasLuiz/TCC | Leon3/lib/grlib/util/util.vhd | 1 | 2,393 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Package: util
-- File: util.vhd
-- Author: Jiri Gaisler, Gaisler Research
-- Description: Misc utilities
------------------------------------------------------------------------------
-- pragma translate_off
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.stdlib.all;
entity report_version is
generic (msg1, msg2, msg3, msg4 : string := ""; mdel : integer := 4);
end;
architecture beh of report_version is
begin
x : process
begin
wait for mdel * 1 ns;
if (msg1 /= "") then print(msg1); end if;
if (msg2 /= "") then print(msg2); end if;
if (msg3 /= "") then print(msg3); end if;
if (msg4 /= "") then print(msg4); end if;
wait;
end process;
end;
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.stdlib.all;
entity report_design is
generic (msg1, fabtech, memtech : string := ""; mdel : integer := 4);
end;
architecture beh of report_design is
begin
x : report_version
generic map (
msg1 => msg1,
msg2 => "GRLIB Version " & tost(LIBVHDL_VERSION/1000) & "." & tost((LIBVHDL_VERSION mod 1000)/100)
& "." & tost(LIBVHDL_VERSION mod 100) & ", build " & tost(LIBVHDL_BUILD),
msg3 => "Target technology: " & fabtech & ", memory library: " & memtech,
mdel => mdel);
end;
-- pragma translate_on
| gpl-3.0 | 6d5081ee37104c70f37ef672de47ef16 | 0.608023 | 3.910131 | false | false | false | false |
pwsoft/fpga_examples | rtl/general/gen_counter_signed.vhd | 1 | 2,495 | -- -----------------------------------------------------------------------
--
-- Syntiac's generic VHDL support files.
--
-- -----------------------------------------------------------------------
-- Copyright 2005-2010 by Peter Wendrich ([email protected])
-- http://www.syntiac.com/fpga64.html
--
-- This source file is free software: you can redistribute it and/or modify
-- it under the terms of the GNU Lesser General Public License as published
-- by the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This source file is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
-- -----------------------------------------------------------------------
--
-- gen_counter.vhd
--
-- -----------------------------------------------------------------------
--
-- Loadable Up/Down Counter
--
-- -----------------------------------------------------------------------
-- clk - clock input
-- reset - reset counter to 0
-- load - Load counter from d input
-- up - Count up
-- down - Count down
-- d - input for load
-- q - counter output
-- -----------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.ALL;
-- -----------------------------------------------------------------------
entity gen_counter_signed is
generic (
width : integer := 8
);
port (
clk : in std_logic;
reset : in std_logic := '0';
load : in std_logic := '0';
up : in std_logic := '0';
down : in std_logic := '0';
d : in signed(width-1 downto 0) := (others => '0');
q : out signed(width-1 downto 0)
);
end entity;
-- -----------------------------------------------------------------------
architecture rtl of gen_counter_signed is
signal qReg : signed(d'range) := (others => '0');
begin
q <= qReg;
process(clk) is
begin
if rising_edge(clk) then
if reset = '1' then
qReg <= (others => '0');
elsif load = '1' then
qReg <= d;
elsif (up = '1') and (down = '0') then
qReg <= qReg + 1;
elsif (up = '0') and (down = '1') then
qReg <= qReg - 1;
end if;
end if;
end process;
end architecture;
| lgpl-2.1 | 31ca381c9aded02bcdf357386905a918 | 0.490581 | 3.960317 | false | false | false | false |
EliasLuiz/TCC | Leon3/designs/leon3-xilinx-ac701/config.vhd | 1 | 7,842 |
-----------------------------------------------------------------------------
-- LEON3 Demonstration design test bench configuration
-- Copyright (C) 2009 Aeroflex Gaisler
------------------------------------------------------------------------------
library techmap;
use techmap.gencomp.all;
package config is
-- Technology and synthesis options
constant CFG_FABTECH : integer := artix7;
constant CFG_MEMTECH : integer := artix7;
constant CFG_PADTECH : integer := artix7;
constant CFG_TRANSTECH : integer := GTP0;
constant CFG_NOASYNC : integer := 0;
constant CFG_SCAN : integer := 0;
-- Clock generator
constant CFG_CLKTECH : integer := artix7;
constant CFG_CLKMUL : integer := (4);
constant CFG_CLKDIV : integer := (8);
constant CFG_OCLKDIV : integer := 1;
constant CFG_OCLKBDIV : integer := 0;
constant CFG_OCLKCDIV : integer := 0;
constant CFG_PCIDLL : integer := 0;
constant CFG_PCISYSCLK: integer := 0;
constant CFG_CLK_NOFB : integer := 0;
-- LEON processor core
constant CFG_LEON : integer := 3;
constant CFG_NCPU : integer := (1);
constant CFG_NWIN : integer := (8);
constant CFG_V8 : integer := 16#32# + 4*0;
constant CFG_MAC : integer := 0;
constant CFG_SVT : integer := 1;
constant CFG_RSTADDR : integer := 16#00000#;
constant CFG_LDDEL : integer := (1);
constant CFG_NWP : integer := (2);
constant CFG_PWD : integer := 1*2;
constant CFG_FPU : integer := 0 + 16*0 + 32*0;
constant CFG_GRFPUSH : integer := 0;
constant CFG_ICEN : integer := 1;
constant CFG_ISETS : integer := 4;
constant CFG_ISETSZ : integer := 4;
constant CFG_ILINE : integer := 4;
constant CFG_IREPL : integer := 0;
constant CFG_ILOCK : integer := 0;
constant CFG_ILRAMEN : integer := 0;
constant CFG_ILRAMADDR: integer := 16#8E#;
constant CFG_ILRAMSZ : integer := 1;
constant CFG_DCEN : integer := 1;
constant CFG_DSETS : integer := 4;
constant CFG_DSETSZ : integer := 4;
constant CFG_DLINE : integer := 4;
constant CFG_DREPL : integer := 0;
constant CFG_DLOCK : integer := 0;
constant CFG_DSNOOP : integer := 1*2 + 4*1;
constant CFG_DFIXED : integer := 16#0#;
constant CFG_BWMASK : integer := 16#0#;
constant CFG_CACHEBW : integer := 128;
constant CFG_DLRAMEN : integer := 0;
constant CFG_DLRAMADDR: integer := 16#8F#;
constant CFG_DLRAMSZ : integer := 1;
constant CFG_MMUEN : integer := 1;
constant CFG_ITLBNUM : integer := 8;
constant CFG_DTLBNUM : integer := 8;
constant CFG_TLB_TYPE : integer := 0 + 1*2;
constant CFG_TLB_REP : integer := 0;
constant CFG_DSU : integer := 1;
constant CFG_ITBSZ : integer := 4 + 64*1;
constant CFG_ATBSZ : integer := 4;
constant CFG_AHBPF : integer := 2;
constant CFG_AHBWP : integer := 2;
constant CFG_LEONFT_EN : integer := 0 + 0*8;
constant CFG_LEON_NETLIST : integer := 0;
constant CFG_DISAS : integer := 0 + 0;
constant CFG_PCLOW : integer := 2;
constant CFG_STAT_ENABLE : integer := 1;
constant CFG_STAT_CNT : integer := (4);
constant CFG_STAT_NMAX : integer := (0);
constant CFG_STAT_DSUEN : integer := 1;
constant CFG_NP_ASI : integer := 1;
constant CFG_WRPSR : integer := 1;
constant CFG_ALTWIN : integer := 0;
constant CFG_REX : integer := 0;
-- L2 Cache
constant CFG_L2_EN : integer := 1;
constant CFG_L2_SIZE : integer := 64;
constant CFG_L2_WAYS : integer := 1;
constant CFG_L2_HPROT : integer := 0;
constant CFG_L2_PEN : integer := 0;
constant CFG_L2_WT : integer := 0;
constant CFG_L2_RAN : integer := 0;
constant CFG_L2_SHARE : integer := 0;
constant CFG_L2_LSZ : integer := 32;
constant CFG_L2_MAP : integer := 16#00F0#;
constant CFG_L2_MTRR : integer := (0);
constant CFG_L2_EDAC : integer := 0;
-- AMBA settings
constant CFG_DEFMST : integer := (0);
constant CFG_RROBIN : integer := 1;
constant CFG_SPLIT : integer := 0;
constant CFG_FPNPEN : integer := 1;
constant CFG_AHBIO : integer := 16#FFF#;
constant CFG_APBADDR : integer := 16#800#;
constant CFG_AHB_MON : integer := 0;
constant CFG_AHB_MONERR : integer := 0;
constant CFG_AHB_MONWAR : integer := 0;
constant CFG_AHB_DTRACE : integer := 0;
-- DSU UART
constant CFG_AHB_UART : integer := 0;
-- JTAG based DSU interface
constant CFG_AHB_JTAG : integer := 1;
-- Ethernet DSU
constant CFG_DSU_ETH : integer := 1 + 0 + 0;
constant CFG_ETH_BUF : integer := 2;
constant CFG_ETH_IPM : integer := 16#C0A8#;
constant CFG_ETH_IPL : integer := 16#0033#;
constant CFG_ETH_ENM : integer := 16#020000#;
constant CFG_ETH_ENL : integer := 16#000000#;
-- LEON2 memory controller
constant CFG_MCTRL_LEON2 : integer := 1;
constant CFG_MCTRL_RAM8BIT : integer := 1;
constant CFG_MCTRL_RAM16BIT : integer := 1;
constant CFG_MCTRL_5CS : integer := 0;
constant CFG_MCTRL_SDEN : integer := 0;
constant CFG_MCTRL_SEPBUS : integer := 0;
constant CFG_MCTRL_INVCLK : integer := 0;
constant CFG_MCTRL_SD64 : integer := 0;
constant CFG_MCTRL_PAGE : integer := 0 + 0;
-- Xilinx MIG 7-Series
constant CFG_MIG_7SERIES : integer := 1;
constant CFG_MIG_7SERIES_MODEL : integer := 0;
-- AHB status register
constant CFG_AHBSTAT : integer := 0;
constant CFG_AHBSTATN : integer := (1);
-- AHB ROM
constant CFG_AHBROMEN : integer := 1;
constant CFG_AHBROPIP : integer := 0;
constant CFG_AHBRODDR : integer := 16#000#;
constant CFG_ROMADDR : integer := 16#100#;
constant CFG_ROMMASK : integer := 16#E00# + 16#100#;
-- AHB RAM
constant CFG_AHBRAMEN : integer := 1;
constant CFG_AHBRSZ : integer := 4;
constant CFG_AHBRADDR : integer := 16#A00#;
constant CFG_AHBRPIPE : integer := 0;
-- Gaisler Ethernet core
constant CFG_GRETH : integer := 1;
constant CFG_GRETH1G : integer := 0;
constant CFG_ETH_FIFO : integer := 8;
constant CFG_GRETH_FT : integer := 0;
constant CFG_GRETH_EDCLFT : integer := 0;
-- UART 1
constant CFG_UART1_ENABLE : integer := 1;
constant CFG_UART1_FIFO : integer := 32;
-- LEON3 interrupt controller
constant CFG_IRQ3_ENABLE : integer := 1;
constant CFG_IRQ3_NSEC : integer := 0;
-- Modular timer
constant CFG_GPT_ENABLE : integer := 1;
constant CFG_GPT_NTIM : integer := (2);
constant CFG_GPT_SW : integer := (8);
constant CFG_GPT_TW : integer := (32);
constant CFG_GPT_IRQ : integer := (8);
constant CFG_GPT_SEPIRQ : integer := 1;
constant CFG_GPT_WDOGEN : integer := 0;
constant CFG_GPT_WDOG : integer := 16#0#;
-- GPIO port
constant CFG_GRGPIO_ENABLE : integer := 1;
constant CFG_GRGPIO_IMASK : integer := 16#0000#;
constant CFG_GRGPIO_WIDTH : integer := (7);
-- I2C master
constant CFG_I2C_ENABLE : integer := 1;
-- VGA and PS2/ interface
constant CFG_KBD_ENABLE : integer := 0;
constant CFG_VGA_ENABLE : integer := 0;
constant CFG_SVGA_ENABLE : integer := 0;
-- SPI memory controller
constant CFG_SPIMCTRL : integer := 1;
constant CFG_SPIMCTRL_SDCARD : integer := 0;
constant CFG_SPIMCTRL_READCMD : integer := 16#0B#;
constant CFG_SPIMCTRL_DUMMYBYTE : integer := 0;
constant CFG_SPIMCTRL_DUALOUTPUT : integer := 0;
constant CFG_SPIMCTRL_SCALER : integer := (8);
constant CFG_SPIMCTRL_ASCALER : integer := (8);
constant CFG_SPIMCTRL_PWRUPCNT : integer := (0);
constant CFG_SPIMCTRL_OFFSET : integer := 16#0#;
-- SPI controller
constant CFG_SPICTRL_ENABLE : integer := 1;
constant CFG_SPICTRL_NUM : integer := (1);
constant CFG_SPICTRL_SLVS : integer := (1);
constant CFG_SPICTRL_FIFO : integer := (1);
constant CFG_SPICTRL_SLVREG : integer := 1;
constant CFG_SPICTRL_ODMODE : integer := 0;
constant CFG_SPICTRL_AM : integer := 0;
constant CFG_SPICTRL_ASEL : integer := 0;
constant CFG_SPICTRL_TWEN : integer := 0;
constant CFG_SPICTRL_MAXWLEN : integer := (0);
constant CFG_SPICTRL_SYNCRAM : integer := 0;
constant CFG_SPICTRL_FT : integer := 0;
-- GRLIB debugging
constant CFG_DUART : integer := 0;
end;
| gpl-3.0 | dbe494c4daa63443ae6b950091b59932 | 0.648687 | 3.566166 | false | false | false | false |
EliasLuiz/TCC | Leon3/lib/gaisler/leon3v3/tbufmem.vhd | 1 | 3,523 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: tbufmem
-- File: tbufmem.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: 256-bit trace buffer memory (CPU/AHB)
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library gaisler;
use gaisler.leon3.all;
library techmap;
use techmap.gencomp.all;
library grlib;
use grlib.stdlib.all;
entity tbufmem is
generic (
tech : integer := 0;
tbuf : integer := 0; -- trace buf size in kB (0 - no trace buffer)
dwidth : integer := 32; -- AHB data width
testen : integer := 0
);
port (
clk : in std_ulogic;
di : in tracebuf_in_type;
do : out tracebuf_out_type;
testin : in std_logic_vector(TESTIN_WIDTH-1 downto 0)
);
end;
architecture rtl of tbufmem is
constant ADDRBITS : integer := 10 + log2(tbuf) - 4;
signal enable : std_logic_vector(1 downto 0);
begin
enable <= di.enable & di.enable;
mem32 : for i in 0 to 1 generate -- basic 128 buffer
ram0 : syncram64 generic map (tech => tech, abits => addrbits, testen => testen, custombits => memtest_vlen)
port map ( clk, di.addr(addrbits-1 downto 0), di.data(((i*64)+63) downto (i*64)),
do.data(((i*64)+63) downto (i*64)), enable ,di.write(i*2+1 downto i*2), testin
);
end generate;
mem64 : if dwidth > 32 generate -- extra data buffer for 64-bit bus
ram0 : syncram generic map (tech => tech, abits => addrbits, dbits => 32, testen => testen, custombits => memtest_vlen)
port map ( clk, di.addr(addrbits-1 downto 0), di.data((128+31) downto 128),
do.data((128+31) downto 128), di.enable, di.write(7), testin
);
end generate;
mem128 : if dwidth > 64 generate -- extra data buffer for 128-bit bus
ram0 : syncram64 generic map (tech => tech, abits => addrbits, testen => testen, custombits => memtest_vlen)
port map ( clk, di.addr(addrbits-1 downto 0), di.data((128+95) downto (128+32)),
do.data((128+95) downto (128+32)), enable ,di.write(6 downto 5), testin
);
end generate;
nomem64 : if dwidth < 64 generate -- no extra data buffer for 64-bit bus
do.data((128+31) downto 128) <= (others => '0');
end generate;
nomem128 : if dwidth < 128 generate -- no extra data buffer for 128-bit bus
do.data((128+95) downto (128+32)) <= (others => '0');
end generate;
do.data(255 downto 224) <= (others => '0');
end;
| gpl-3.0 | 945caed9498900a4f3a54d704be2bee4 | 0.612546 | 3.771949 | false | true | false | false |
EliasLuiz/TCC | Leon3/lib/gaisler/jtag/jtagcom.vhd | 1 | 7,865 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: jtagcom
-- File: jtagcom.vhd
-- Author: Edvin Catovic - Gaisler Research
-- Modified: J. Gaisler, K. Glembo, J. Andersson - Aeroflex Gaisler
-- Description: JTAG Debug Interface with AHB master interface
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
library techmap;
use techmap.gencomp.all;
library gaisler;
use gaisler.libjtagcom.all;
use gaisler.misc.all;
entity jtagcom is
generic (
isel : integer range 0 to 1 := 0;
nsync : integer range 1 to 2 := 2;
ainst : integer range 0 to 255 := 2;
dinst : integer range 0 to 255 := 3;
reread : integer range 0 to 1 := 0);
port (
rst : in std_ulogic;
clk : in std_ulogic;
tapo : in tap_out_type;
tapi : out tap_in_type;
dmao : in ahb_dma_out_type;
dmai : out ahb_dma_in_type;
tck : in std_ulogic;
trst : in std_ulogic
);
attribute sync_set_reset of rst : signal is "true";
end;
architecture rtl of jtagcom is
constant ADDBITS : integer := 10;
constant NOCMP : boolean := (isel /= 0);
type state_type is (shft, ahb, nxt_shft);
type reg_type is record
addr : std_logic_vector(34 downto 0);
data : std_logic_vector(32 downto 0);
state : state_type;
tcktog: std_logic_vector(nsync-1 downto 0);
tcktog2: std_ulogic;
tdishft: std_ulogic;
trst : std_logic_vector(nsync-1 downto 0);
tdi : std_logic_vector(nsync-1 downto 0);
shift : std_logic_vector(nsync-1 downto 0);
shift2: std_ulogic;
upd : std_logic_vector(nsync-1 downto 0);
upd2 : std_ulogic;
asel : std_logic_vector(nsync-1 downto 0);
dsel : std_logic_vector(nsync-1 downto 0);
seq : std_ulogic;
holdn : std_ulogic;
end record;
type tckreg_type is record
tcktog: std_ulogic;
tdi: std_ulogic;
tdor: std_ulogic;
end record;
signal nexttdo: std_ulogic;
signal r, rin : reg_type;
signal tr: tckreg_type;
begin
comb : process (rst, r, tapo, dmao, tr)
variable v : reg_type;
variable redge0 : std_ulogic;
variable vdmai : ahb_dma_in_type;
variable asel, dsel : std_ulogic;
variable vtapi : tap_in_type;
variable write, seq : std_ulogic;
variable vnexttdo: std_ulogic;
begin
v := r;
if NOCMP then
asel := tapo.asel; dsel := tapo.dsel;
else
if tapo.inst = conv_std_logic_vector(ainst, 8) then asel := '1'; else asel := '0'; end if;
if tapo.inst = conv_std_logic_vector(dinst, 8) then dsel := '1'; else dsel := '0'; end if;
end if;
vtapi.en := asel or dsel;
vnexttdo := '0';
if asel='1' then
if tapo.shift='1' then
vnexttdo := r.addr(1);
else
vnexttdo := r.addr(0);
end if;
else
if tapo.shift='1' then
vnexttdo := r.data(1);
else
vnexttdo := r.data(0);
end if;
if reread /= 0 then vnexttdo := vnexttdo and r.holdn; end if;
end if;
nexttdo <= vnexttdo;
vtapi.tdo := tr.tdor;
write := r.addr(34); seq := r.seq;
v.tcktog(0) := r.tcktog(nsync-1); v.tcktog(nsync-1) := tr.tcktog;
v.tcktog2 := r.tcktog(0); v.shift2 := r.shift(0);
v.trst(0) := r.trst(nsync-1); v.trst(nsync-1) := tapo.reset;
v.tdi(0) := r.tdi(nsync-1); v.tdi(nsync-1) := tr.tdi;
v.shift(0) := r.shift(nsync-1); v.shift(nsync-1) := tapo.shift;
v.upd(0) := r.upd(nsync-1); v.upd(nsync-1) := tapo.upd;
v.upd2 := r.upd(0);
v.asel(0) := r.asel(nsync-1); v.asel(nsync-1) := asel;
v.dsel(0) := r.dsel(nsync-1); v.dsel(nsync-1) := dsel;
redge0 := r.tcktog2 xor r.tcktog(0);
v.tdishft := '0';
vdmai.address := r.addr(31 downto 0); vdmai.wdata := ahbdrivedata(r.data(31 downto 0));
vdmai.start := '0'; vdmai.burst := '0'; vdmai.write := write;
vdmai.busy := '0'; vdmai.irq := '0'; vdmai.size := '0' & r.addr(33 downto 32);
case r.state is
when shft =>
if (r.asel(0) or r.dsel(0)) = '1' then
if r.shift2 = '1' then
if redge0 = '1' then
if r.asel(0) = '1' then v.addr(33 downto 0) := r.addr(34 downto 1); end if;
if r.dsel(0) = '1' then v.data(31 downto 0) := r.data(32 downto 1); end if;
v.tdishft := '1'; -- Shift in TDI next AHB cycle
end if;
elsif r.upd2 = '1' then
if reread /= 0 then
v.data(32) := '0'; -- Transfer not done
end if;
if (r.asel(0) and not write) = '1' then v.state := ahb; end if;
if (r.dsel(0) and (write or (not write and seq))) = '1' then -- data register
v.state := ahb;
if (seq and not write) = '1' then
v.addr(ADDBITS-1 downto 2) := r.addr(ADDBITS-1 downto 2) + 1;
end if;
end if;
end if;
end if;
if r.tdishft='1' then
if r.asel(0)='1' then v.addr(34):=r.tdi(0); end if;
if r.dsel(0)='1' then v.data(32):=r.tdi(0); v.seq:=r.tdi(0); end if;
end if;
if reread /= 0 then v.holdn := '1'; end if;
vdmai.size := "000";
when ahb =>
if reread /= 0 and r.shift2 = '1' then v.holdn := '0'; end if;
if dmao.active = '1' then
if dmao.ready = '1' then
v.data(31 downto 0) := ahbreadword(dmao.rdata);
v.state := nxt_shft;
if reread /= 0 then
v.data(32) := '1'; -- Transfer done
end if;
if (write and seq) = '1' then
v.addr(ADDBITS-1 downto 2) := r.addr(ADDBITS-1 downto 2) + 1;
end if;
end if;
else
vdmai.start := '1';
end if;
when nxt_shft =>
if reread /= 0 then
v.holdn := (r.holdn or r.upd2) and not r.shift2;
if r.upd2 = '0' and r.shift2 = '0' and r.holdn = '1' then v.state := shft; end if;
else
if r.upd2 = '0' then v.state := shft; end if;
end if;
when others =>
v.state := shft; v.addr := (others => '0'); v.seq := '0';
end case;
if (rst = '0') or (r.trst(0) = '1') then
v.state := shft; v.addr := (others => '0'); v.seq := '0';
end if;
if reread = 0 then v.holdn := '0'; end if;
rin <= v; dmai <= vdmai; tapi <= vtapi;
end process;
reg : process (clk)
begin
if rising_edge(clk) then r <= rin; end if;
end process;
tckreg: process (tck,trst)
begin
if rising_edge(tck) then
tr.tcktog <= not tr.tcktog;
tr.tdi <= tapo.tdi;
tr.tdor <= nexttdo;
end if;
if trst='0' then
tr.tcktog <= '0';
tr.tdi <= '0';
tr.tdor <= '0';
end if;
end process;
end;
| gpl-3.0 | af872ac669bc941c67358e016c98a54f | 0.546217 | 3.283925 | false | false | false | false |
GLADICOS/SPACEWIRESYSTEMC | rtl/RTL_SL/syncdff.vhd | 2 | 2,191 | --
-- Double flip-flop synchronizer.
--
-- This entity is used to safely capture asynchronous signals.
--
-- An implementation may assign additional constraints to this entity
-- in order to reduce the probability of meta-stability issues.
-- For example, an extra tight timing constraint could be placed on
-- the data path from syncdff_ff1 to syncdff_ff2 to ensure that
-- meta-stability of ff1 is resolved before ff2 captures the signal.
--
library ieee;
use ieee.std_logic_1164.all;
entity syncdff is
port (
clk: in std_logic; -- clock (destination domain)
rst: in std_logic; -- asynchronous reset, active-high
di: in std_logic; -- input data
do: out std_logic -- output data
);
-- Turn off register replication in XST.
attribute REGISTER_DUPLICATION: string;
attribute REGISTER_DUPLICATION of syncdff: entity is "NO";
end entity syncdff;
architecture syncdff_arch of syncdff is
-- flip-flops
signal syncdff_ff1: std_ulogic := '0';
signal syncdff_ff2: std_ulogic := '0';
-- Turn of shift-register extraction in XST.
attribute SHIFT_EXTRACT: string;
attribute SHIFT_EXTRACT of syncdff_ff1: signal is "NO";
attribute SHIFT_EXTRACT of syncdff_ff2: signal is "NO";
-- Tell XST to place both flip-flops in the same slice.
attribute RLOC: string;
attribute RLOC of syncdff_ff1: signal is "X0Y0";
attribute RLOC of syncdff_ff2: signal is "X0Y0";
-- Tell XST to keep the flip-flop net names to be used in timing constraints.
attribute KEEP: string;
attribute KEEP of syncdff_ff1: signal is "SOFT";
attribute KEEP of syncdff_ff2: signal is "SOFT";
begin
-- second flip-flop drives the output signal
do <= syncdff_ff2;
process (clk, rst) is
begin
if rst = '1' then
-- asynchronous reset
syncdff_ff1 <= '0';
syncdff_ff2 <= '0';
elsif rising_edge(clk) then
-- data synchronization
syncdff_ff1 <= di;
syncdff_ff2 <= syncdff_ff1;
end if;
end process;
end architecture syncdff_arch;
| gpl-3.0 | 6b909f60d13a7146f161ac0a8ed72ceb | 0.63989 | 3.857394 | false | false | false | false |
pedabraham/MDSM | crs/Diseño2v1.vhd | 1 | 3,675 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
entity MDled is
port(
sensores : IN STD_LOGIC_VECTOR(8 downto 0);
clk : IN STD_LOGIC;
resetAbsoluto: IN STD_LOGIC;
prueba: out std_logic_vector(3 downto 0);
p2: out std_logic;
abre : OUT STD_LOGIC
);
end MDled;
architecture Behavioral of MDled is
component BaseDeTiempo is
generic(
n : integer := 9
);
port(
NewWord : IN STD_LOGIC_VECTOR(n-1 downto 0);
CE : OUT STD_LOGIC
);
end component;
component BasedeTiempo2 is
port(
clk : in std_logic;
rst_in : in std_logic;
rst_out : out std_logic
);
end component;
component bitsToNumbers is
port(
cadenaOriginalDeBits: IN STD_LOGIC_VECTOR(8 downto 0);
numero : OUT STD_LOGIC_VECTOR(3 downto 0)
);
end component;
component ROM is
port(
Count : in STD_LOGIC_VECTOR(3 downto 0);
Valor : out STD_LOGIC_VECTOR(3 downto 0)
);
end component;
component comparador is
generic(
n:integer:=4
);
port(
A: in STD_LOGIC_VECTOR(n-1 downto 0);
B: in STD_LOGIC_VECTOR(n-1 downto 0);
CLK: in STD_LOGIC;
Clr : in STD_LOGIC;
Count : in STD_LOGIC_VECTOR(3 downto 0);
Bool: out STD_LOGIC
);
end component;
--component Verificador1 is
-- port(
-- bool : in STD_LOGIC;
-- Count : in STD_LOGIC_VECTOR(3 downto 0);
-- CLK : in STD_LOGIC;
-- Clr : in STD_LOGIC;
-- Salida : out STD_LOGIC
-- );
--end component;
component Contador is
generic(
n : INTEGER := 4
);
port(
clk : IN STD_LOGIC;
clr : IN STD_LOGIC;
CE : IN STD_LOGIC;
Count : OUT STD_LOGIC_VECTOR(n-1 downto 0) --Indica el turno en que se detecto un sensor.
);
end component;
component val1 is
generic(
n:integer:=9
);
port(
NewWord : IN STD_LOGIC_VECTOR(n-1 downto 0); --cadena recien hecha
Clk : IN STD_LOGIC;
rst : IN STD_LOGIC;
GoodWord : OUT STD_LOGIC_VECTOR(n-1 downto 0) --palabra que saldra si pasa los filtros
);
end component;
--SIGNALS--
signal CE,CE2,rst,rstComp,rstTB2 : STD_LOGIC;
signal numero,valor,count: STD_LOGIC_VECTOR(3 downto 0);
signal GoodWord: STD_LOGIC_VECTOR(8 downto 0);
begin
--port map--
TimeBasis: BaseDeTiempo port map(NewWord=>GoodWord,CE=>CE);--genera el clk para el val
TimeBasis2: BaseDeTiempo2 port map(CLK=>CLK,rst_in=>rstTB2,rst_out=>rstComp);
BTN: bitsToNumbers port map(cadenaOriginalDeBits=>sensores,numero=>numero);
Comp: comparador port map(A=>valor,B=>numero,CLK=>CLK,Clr=>rst,Count=>Count,Bool=>abre);
Cont: Contador port map(CLK=>CLK,CE=>CE,clr=>rst,count=>count);
Ro: ROM port map (Count=>count,valor=>valor);
Val: val1 port map(NewWord=>sensores,clk=>clk,rst=>rst,GoodWord=>GoodWord);--genera la palabra que el timeBasis va a procesar
--TimeBasis12:BaseDeTiempo port map(NewWord=>GoodWord,CE=>CE);--generea el clk del sistema
-- En las prubas con botones se encontraron pulsos inesperados y se espera que el val solucione estos problemas
comb : process( resetAbsoluto,rstComp,CE,count)
begin
if (ResetAbsoluto='1') then
rst <= ResetAbsoluto;
rstTB2 <= ResetAbsoluto;
else
rst <= rstComp;
rstTB2 <= CE;
end if ;
prueba <= count;
p2 <= CE;
end process ; -- comb
--Verifica: Verificador1 port map (bool=>bool,count=>count,CLK=>CE,clr=>rst,Salida=>abre);
--CE1 <= '0' when RTS = '0' else CE when rising_edge(CLK);
end Behavioral; | mit | cd81061ebee8869b60f00d129e4bbd53 | 0.622857 | 2.895981 | false | false | false | false |
kdgwill/VHDL_Framer_Example | VHDL_Framer_Example/Example1/ram.vhd | 2 | 2,769 | ---------------------------------------------------------------------------------
--RAM------------------------------------------------------------
--By Kyle Williams, 04/07/2011--------------------------------------------------
--PROJECT DESCRIPTION------------------------------------------------------------
--4--After 8 bytes have been written in the ram start reading the data from the ram
----------------Define Libraries to be used--------------------------------------
LIBRARY IEEE ;
USE IEEE.std_logic_1164.all ;
USE IEEE.std_logic_unsigned.all;
USE ieee.numeric_std.all;
-----------------ENTITY FOR RAM------------------------------------------
ENTITY ram is
GENERIC ( bits : INTEGER := 8; -- # of bits per word
words : INTEGER := 32 ); -- # of words in the memory
PORT ( wr_ena : IN STD_LOGIC; -- write enable
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
addr : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
ram_in : IN STD_LOGIC_VECTOR (bits - 1 DOWNTO 0);
ram_out : OUT STD_LOGIC_VECTOR (bits -1 DOWNTO 0)
);
END ram;
-----------------BEHAVIOR OF RAM-----------------------------------------
ARCHITECTURE ram of ram IS
--TYPE row IS ARRAY (7 downto 0) OF STD_LOGIC; -- 1D array
--TYPE matrix IS ARRAY (0 to 3) of row; -- 1Dx1D array
--TYPE matrix IS ARRAY (0 to 4) of STD_LOGIC_VECTOR (7 DOWNTO 0)--1Dx1D
--Example: 2D array
--The array below is truly two-dimensional. Notice that its construction is not based on vectors, but rather entirely on scalars
--TYPE matrix2D IS ARRAY (0 TO 3, 7 DOWNTO 0) of STD_LOGIC; --2D array
TYPE vector_array is ARRAY (0 to words -1) of STD_LOGIC_VECTOR (bits-1 DOWNTO 0);--32x8
signal memory : vector_array:=(others=> (others=>'0'));--matrix and set to 0 initially this is wrong but set for conceptual purposes
signal temp_addr: Integer;
-------------------PROCEDUREE------------------------------
BEGIN
--Design Question should it take 9 ram inputs before output begining output sequence
--Program works either way so it is up to the manufacturer
--temp_addr <= to_integer(unsigned(addr));--offset is 9 ctrl_out changes up here
PROCESS (clock, wr_ena)
BEGIN
IF(reset='0')THEN
memory <= (others=> (others=>'0'));
temp_addr <= 0; -- only enable if want offset of 1 instead of 9
ELSIF(rising_edge(clock)) THEN -- can also use clk'EVENT AND clk = '1'
temp_addr <= to_integer(unsigned(addr));--offset is 1 ctrl_out changes up here
IF (wr_ena = '1') THEN
memory(temp_addr) <= ram_in;
ELSE
ram_out <= memory(temp_addr);
END IF;
END IF;
END PROCESS;
--ram_out <= memory(temp_addr);--asynchronous
END ram;
| gpl-3.0 | e1382debb2538ea45c9678b3cc19d04c | 0.5316 | 4.132836 | false | false | false | false |
pwsoft/fpga_examples | rtl/ps2/io_ps2_mouse.vhd | 1 | 7,647 | -- -----------------------------------------------------------------------
--
-- Syntiac VHDL support files.
--
-- -----------------------------------------------------------------------
-- Copyright 2005-2009 by Peter Wendrich ([email protected])
-- http://www.syntiac.com
--
-- This source file is free software: you can redistribute it and/or modify
-- it under the terms of the GNU Lesser General Public License as published
-- by the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This source file is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
-- -----------------------------------------------------------------------
--
-- PS/2 mouse driver
--
-- Uses: io_ps2_com
--
-- -----------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.ALL;
-- -----------------------------------------------------------------------
entity io_ps2_mouse is
generic (
-- Enable support for intelli-mouse mode.
-- This allows the use of the scroll-wheel on mice that have them.
intelliMouseSupport : boolean := true;
-- Number of system-cycles used for PS/2 clock filtering
clockFilter : integer := 15;
-- Timer calibration
ticksPerUsec : integer := 33 -- 33 Mhz clock
);
port (
clk: in std_logic;
reset : in std_logic := '0';
ps2_clk_in: in std_logic;
ps2_dat_in: in std_logic;
ps2_clk_out: out std_logic;
ps2_dat_out: out std_logic;
mousePresent : out std_logic;
trigger : out std_logic;
leftButton : out std_logic;
middleButton : out std_logic;
rightButton : out std_logic;
deltaX : out signed(8 downto 0);
deltaY : out signed(8 downto 0);
deltaZ : out signed(3 downto 0)
);
end entity;
-- -----------------------------------------------------------------------
architecture rtl of io_ps2_mouse is
constant ticksPer100Usec : integer := ticksPerUsec * 100;
constant tickTimeout : integer := ticksPerUsec * 3500000;
type mainStateDef is (
stateInit, stateInitAA, stateInitID, stateReset, stateReset2, stateResetAck,
intelliKnock, intelliKnockAck, intelliCheckId,
stateSetDataReporting, stateSetDataReportingAck,
stateWaitByte1, stateWaitByte2, stateWaitByte3, stateWaitByte4);
signal masterState : mainStateDef := stateInit;
signal timeoutCount : integer range 0 to tickTimeout := 0;
signal resetCom : std_logic;
signal inIdle : std_logic;
signal recvTrigger : std_logic := '0';
signal sendTrigger : std_logic := '0';
signal sendBusy : std_logic;
signal sendByte : unsigned(7 downto 0);
signal recvByte : unsigned(10 downto 0);
signal intelliMouse : std_logic := '0';
signal intelliCnt : unsigned(2 downto 0) := "000";
begin
myPs2Com : entity work.io_ps2_com
generic map (
clockFilter => clockFilter,
ticksPerUsec => ticksPerUsec
)
port map (
clk => clk,
reset => resetCom,
ps2_clk_in => ps2_clk_in,
ps2_dat_in => ps2_dat_in,
ps2_clk_out => ps2_clk_out,
ps2_dat_out => ps2_dat_out,
inIdle => inIdle,
sendTrigger => sendTrigger,
sendByte => sendByte,
sendBusy => sendBusy,
recvTrigger => recvTrigger,
recvByte => recvByte
);
--
-- Mouse state machine
process(clk)
begin
if rising_edge(clk) then
resetCom <= '0';
mousePresent <= '0';
trigger <= '0';
sendTrigger <= '0';
if timeoutCount /= 0 then
timeoutCount <= timeoutCount - 1;
else
masterState <= stateReset;
end if;
case masterState is
--
-- Reset sequence states
--
when stateReset =>
resetCom <= '1';
timeoutCount <= tickTimeout;
masterState <= stateReset2;
when stateReset2 =>
-- Reset mouse
if sendBusy = '0' then
sendByte <= X"FF";
sendTrigger <= '1';
masterState <= stateResetAck;
end if;
when stateResetAck =>
if recvTrigger = '1' then
masterState <= stateInit;
end if;
--
-- Mouse BAT handling states (Basic assurance test)
--
when stateInit =>
-- Wait for mouse to perform self-test
timeoutCount <= tickTimeout;
masterState <= stateInitAA;
when stateInitAA =>
-- Receive selftest result. It should be AAh.
if recvTrigger = '1' then
if recvByte(8 downto 1) = X"AA" then
masterState <= stateInitID;
end if;
end if;
when stateInitID =>
-- Receive device ID (it isn't checked)
if recvTrigger = '1' then
timeoutCount <= tickTimeout;
masterState <= stateSetDataReporting;
intelliCnt <= (others => '0');
if intelliMouseSupport then
masterState <= intelliKnock;
end if;
end if;
--
-- Intelli Mouse knock sequence for wheel support
--
when intelliKnock =>
if sendBusy = '0' then
sendTrigger <= '1';
masterState <= intelliKnockAck;
intelliCnt <= intelliCnt + 1;
case intelliCnt is
when "000" => sendByte <= X"F3"; -- Set sample rate
when "001" => sendByte <= X"C8"; -- Rate 200
when "010" => sendByte <= X"F3"; -- Set sample rate
when "011" => sendByte <= X"64"; -- Rate 100
when "100" => sendByte <= X"F3"; -- Set sample rate
when "101" => sendByte <= X"50"; -- Rate 80
when "110" => sendByte <= X"F2"; -- Request ID
when others => sendByte <= (others => '-');
end case;
end if;
when intelliKnockAck =>
if recvTrigger = '1' then
masterState <= intelliKnock;
-- End of knock sequence, check the mouse ID
if intelliCnt = "111" then
masterState <= intelliCheckId;
end if;
end if;
when intelliCheckId =>
if recvTrigger = '1' then
masterState <= stateSetDataReporting;
intelliMouse <= '0';
if recvByte(8 downto 1) = X"03" then
intelliMouse <= '1';
end if;
end if;
--
-- Enable data reporting
--
when stateSetDataReporting =>
if sendBusy = '0' then
sendByte <= X"F4";
sendTrigger <= '1';
masterState <= stateSetDataReportingAck;
end if;
when stateSetDataReportingAck =>
if recvTrigger = '1' then
masterState <= stateWaitByte1;
end if;
--
-- Receive movement packet
--
when stateWaitByte1 =>
mousePresent <= '1';
if inIdle = '1' then
timeoutCount <= tickTimeout;
end if;
if recvTrigger = '1' then
leftButton <= recvByte(1);
rightButton <= recvByte(2);
middleButton <= recvByte(3);
deltaX(8) <= recvByte(5);
deltaY(8) <= recvByte(6);
masterState <= stateWaitByte2;
end if;
when stateWaitByte2 =>
mousePresent <= '1';
if recvTrigger = '1' then
deltaX(7 downto 0) <= signed(recvByte(8 downto 1));
masterState <= stateWaitByte3;
end if;
when stateWaitByte3 =>
mousePresent <= '1';
if recvTrigger = '1' then
deltaY(7 downto 0) <= signed(recvByte(8 downto 1));
if intelliMouse = '1' then
masterState <= stateWaitByte4;
else
deltaZ <= (others => '0');
trigger <= '1';
masterState <= stateWaitByte1;
end if;
end if;
when stateWaitByte4 =>
mousePresent <= '1';
if recvTrigger = '1' then
deltaZ <= signed(recvByte(4 downto 1));
trigger <= '1';
masterState <= stateWaitByte1;
end if;
end case;
if reset = '1' then
masterState <= stateReset;
end if;
end if;
end process;
end architecture;
| lgpl-2.1 | c6a66b2028a89787cfbc4b70843dd3bb | 0.601543 | 3.337844 | false | false | false | false |
EliasLuiz/TCC | Leon3/lib/eth/core/greth_tx.vhd | 1 | 17,548 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: greth_tx
-- File: greth_tx.vhd
-- Author: Marko Isomaki
-- Description: Ethernet transmitter
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.stdlib.all;
library eth;
use eth.grethpkg.all;
entity greth_tx is
generic(
ifg_gap : integer := 24;
attempt_limit : integer := 16;
backoff_limit : integer := 10;
nsync : integer range 1 to 2 := 2;
rmii : integer range 0 to 1 := 0;
gmiimode : integer range 0 to 1 := 0
);
port(
rst : in std_ulogic;
clk : in std_ulogic;
txi : in host_tx_type;
txo : out tx_host_type
);
attribute sync_set_reset of rst : signal is "true";
end entity;
architecture rtl of greth_tx is
function mirror2(din : in std_logic_vector(3 downto 0))
return std_logic_vector is
variable do : std_logic_vector(3 downto 0);
begin
do(3) := din(0); do(2) := din(1);
do(1) := din(2); do(0) := din(3);
return do;
end function;
function init_ifg(
ifg_gap : in integer;
rmii : in integer)
return integer is
begin
if rmii = 0 then
return log2(ifg_gap);
else
return log2(ifg_gap*20);
end if;
end function;
constant maxattempts : std_logic_vector(4 downto 0) :=
conv_std_logic_vector(attempt_limit, 5);
--transmitter constants
constant ifg_bits : integer := init_ifg(ifg_gap, rmii);
constant ifg_p1 : std_logic_vector(ifg_bits-1 downto 0) :=
conv_std_logic_vector((ifg_gap)/3, ifg_bits);
constant ifg_p2 : std_logic_vector(ifg_bits-1 downto 0) :=
conv_std_logic_vector((ifg_gap*2)/3, ifg_bits);
constant ifg_p1_r100 : std_logic_vector(ifg_bits-1 downto 0) :=
conv_std_logic_vector((ifg_gap*2)/3, ifg_bits);
constant ifg_p2_r100 : std_logic_vector(ifg_bits-1 downto 0) :=
conv_std_logic_vector(rmii*(ifg_gap*4)/3, ifg_bits);
constant ifg_p1_r10 : std_logic_vector(ifg_bits-1 downto 0) :=
conv_std_logic_vector(rmii*(ifg_gap*20)/3, ifg_bits);
constant ifg_p2_r10 : std_logic_vector(ifg_bits-1 downto 0) :=
conv_std_logic_vector(rmii*(ifg_gap*40)/3, ifg_bits);
function ifg_sel(
rmii : in integer;
p1 : in integer;
speed : in std_ulogic)
return std_logic_vector is
begin
if p1 = 1 then
if rmii = 0 then
return ifg_p1;
else
if speed = '1' then
return ifg_p1_r100;
else
return ifg_p1_r10;
end if;
end if;
else
if rmii = 0 then
return ifg_p2;
else
if speed = '1' then
return ifg_p2_r100;
else
return ifg_p2_r10;
end if;
end if;
end if;
end function;
--transmitter types
type tx_state_type is (idle, preamble, sfd, data1, data2, pad1, pad2, fcs,
fcs2, finish, calc_backoff, wait_backoff, send_jam, send_jam2,
check_attempts);
type def_state_type is (monitor, def_on, ifg1, ifg2, frame_waitingst);
type tx_reg_type is record
--deference process
def_state : def_state_type;
ifg_cycls : std_logic_vector(ifg_bits-1 downto 0);
deferring : std_ulogic;
was_transmitting : std_ulogic;
--tx process
main_state : tx_state_type;
transmitting : std_ulogic;
tx_en : std_ulogic;
txd : std_logic_vector(3 downto 0);
cnt : std_logic_vector(3 downto 0);
icnt : std_logic_vector(1 downto 0);
crc : std_logic_vector(31 downto 0);
crc_en : std_ulogic;
byte_count : std_logic_vector(10 downto 0);
slot_count : std_logic_vector(6 downto 0);
random : std_logic_vector(9 downto 0);
delay_val : std_logic_vector(9 downto 0);
retry_cnt : std_logic_vector(4 downto 0);
status : std_logic_vector(1 downto 0);
data : std_logic_vector(31 downto 0);
--synchronization
read : std_ulogic;
done : std_ulogic;
restart : std_ulogic;
start : std_logic_vector(nsync downto 0);
read_ack : std_logic_vector(nsync-1 downto 0);
crs : std_logic_vector(1 downto 0);
col : std_logic_vector(1 downto 0);
fullduplex : std_logic_vector(1 downto 0);
--rmii
crs_act : std_ulogic;
crs_prev : std_ulogic;
speed : std_logic_vector(1 downto 0);
rcnt : std_logic_vector(3 downto 0);
switch : std_ulogic;
txd_msb : std_logic_vector(1 downto 0);
zero : std_ulogic;
rmii_crc_en : std_ulogic;
end record;
--transmitter signals
signal r, rin : tx_reg_type;
signal txrst : std_ulogic;
signal vcc : std_ulogic;
--attribute sync_set_reset : string;
attribute sync_set_reset of txrst : signal is "true";
begin
vcc <= '1';
tx_rst : eth_rstgen
port map(rst, clk, vcc, txrst, open);
tx : process(txrst, r, txi) is
variable collision : std_ulogic;
variable frame_waiting : std_ulogic;
variable index : integer range 0 to 7;
variable start : std_ulogic;
variable read_ack : std_ulogic;
variable v : tx_reg_type;
variable crs : std_ulogic;
variable col : std_ulogic;
variable tx_done : std_ulogic;
begin
v := r; frame_waiting := '0'; tx_done := '0'; v.rmii_crc_en := '0';
--synchronization
v.col(1) := r.col(0); v.col(0) := txi.rx_col;
v.crs(1) := r.crs(0); v.crs(0) := txi.rx_crs;
v.fullduplex(0) := txi.full_duplex;
v.fullduplex(1) := r.fullduplex(0);
v.start(0) := txi.start;
v.read_ack(0) := txi.readack;
if nsync = 2 then
v.start(1) := r.start(0);
v.read_ack(1) := r.read_ack(0);
end if;
start := r.start(nsync) xor r.start(nsync-1);
read_ack := not (r.read xor r.read_ack(nsync-1));
--crc generation
if (r.crc_en = '1') and ((rmii = 0) or (r.rmii_crc_en = '1')) then
v.crc := calccrc(r.txd, r.crc);
end if;
--rmii
if rmii = 0 then
col := r.col(1); crs := r.crs(1);
tx_done := '1';
else
v.crs_prev := r.crs(1);
if (r.crs(0) and not r.crs_act) = '1' then
v.crs_act := '1';
end if;
if (r.crs(1) or r.crs(0)) = '0' then
v.crs_act := '0';
end if;
crs := r.crs(1) and not ((not r.crs_prev) and r.crs_act);
col := crs and r.tx_en;
v.speed(1) := r.speed(0); v.speed(0) := txi.speed;
if r.tx_en = '1' then
v.rcnt := r.rcnt - 1;
if r.speed(1) = '1' then
v.switch := not r.switch;
if r.switch = '1' then
tx_done := '1'; v.rmii_crc_en := '1';
end if;
if r.switch = '0' then
v.txd(1 downto 0) := r.txd_msb;
end if;
else
v.zero := '0';
if r.rcnt = "0001" then
v.zero := '1';
end if;
if r.zero = '1' then
v.switch := not r.switch;
v.rcnt := "1001";
if r.switch = '0' then
v.txd(1 downto 0) := r.txd_msb;
end if;
end if;
if (r.switch and r.zero) = '1' then
tx_done := '1'; v.rmii_crc_en := '1';
end if;
end if;
end if;
end if;
collision := col and not r.fullduplex(1);
--main fsm
case r.main_state is
when idle =>
v.transmitting := '0';
if rmii = 1 then
v.rcnt := "1001"; v.switch := '0';
end if;
if (start and not r.deferring) = '1' then
v.main_state := preamble; v.transmitting := '1'; v.tx_en := '1';
v.byte_count := (others => '1'); v.status := (others => '0');
v.read := not r.read; v.start(nsync) := r.start(nsync-1);
elsif start = '1' then
frame_waiting := '1';
end if;
v.txd := "0101"; v.cnt := "1110";
when preamble =>
if tx_done = '1' then
v.cnt := r.cnt - 1;
if r.cnt = "0000" then
v.txd := "1101"; v.main_state := sfd;
end if;
if collision = '1' then v.main_state := send_jam; end if;
end if;
when sfd =>
if tx_done = '1' then
v.main_state := data1; v.icnt := (others => '0'); v.crc_en := '1';
v.crc := (others => '1'); v.byte_count := (others => '0');
v.txd := txi.data(27 downto 24);
if (read_ack and txi.valid) = '0' then
v.status(0) := '1'; v.main_state := finish; v.tx_en := '0';
else
v.data := txi.data; v.read := not r.read;
end if;
if collision = '1' then v.main_state := send_jam; end if;
end if;
when data1 =>
index := conv_integer(r.icnt);
if tx_done = '1' then
v.byte_count := r.byte_count + 1;
v.main_state := data2; v.icnt := r.icnt + 1;
case index is
when 0 => v.txd := r.data(31 downto 28);
when 1 => v.txd := r.data(23 downto 20);
when 2 => v.txd := r.data(15 downto 12);
when 3 => v.txd := r.data(7 downto 4);
when others => null;
end case;
if v.byte_count = txi.len then
v.tx_en := '1';
if conv_integer(v.byte_count) >= 60 then
v.main_state := fcs; v.cnt := (others => '0');
else
v.main_state := pad1;
end if;
elsif index = 3 then
if (read_ack and txi.valid) = '0' then
v.status(0) := '1'; v.main_state := finish; v.tx_en := '0';
else
v.data := txi.data; v.read := not r.read;
end if;
end if;
if collision = '1' then v.main_state := send_jam; end if;
end if;
when data2 =>
index := conv_integer(r.icnt);
if tx_done = '1' then
v.main_state := data1;
case index is
when 0 => v.txd := r.data(27 downto 24);
when 1 => v.txd := r.data(19 downto 16);
when 2 => v.txd := r.data(11 downto 8);
when 3 => v.txd := r.data(3 downto 0);
when others => null;
end case;
if collision = '1' then v.main_state := send_jam; end if;
end if;
when pad1 =>
if tx_done = '1' then
v.main_state := pad2;
if collision = '1' then v.main_state := send_jam; end if;
end if;
when pad2 =>
if tx_done = '1' then
v.byte_count := r.byte_count + 1;
if conv_integer(v.byte_count) = 60 then
v.main_state := fcs; v.cnt := (others => '0');
else
v.main_state := pad1;
end if;
if collision = '1' then v.main_state := send_jam; end if;
end if;
when fcs =>
if tx_done = '1' then
v.cnt := r.cnt + 1; v.crc_en := '0'; index := conv_integer(r.cnt);
case index is
when 0 => v.txd := mirror2(not v.crc(31 downto 28));
when 1 => v.txd := mirror2(not r.crc(27 downto 24));
when 2 => v.txd := mirror2(not r.crc(23 downto 20));
when 3 => v.txd := mirror2(not r.crc(19 downto 16));
when 4 => v.txd := mirror2(not r.crc(15 downto 12));
when 5 => v.txd := mirror2(not r.crc(11 downto 8));
when 6 => v.txd := mirror2(not r.crc(7 downto 4));
when 7 => v.txd := mirror2(not r.crc(3 downto 0));
v.main_state := fcs2;
when others => null;
end case;
end if;
when fcs2 =>
if tx_done = '1' then
v.main_state := finish; v.tx_en := '0';
end if;
when finish =>
v.tx_en := '0'; v.transmitting := '0'; v.main_state := idle;
v.retry_cnt := (others => '0'); v.done := not r.done;
when send_jam =>
if tx_done = '1' then
v.cnt := "0110"; v.main_state := send_jam2; v.crc_en := '0';
end if;
when send_jam2 =>
if tx_done = '1' then
v.cnt := r.cnt - 1;
if r.cnt = "0000" then
v.main_state := check_attempts; v.retry_cnt := r.retry_cnt + 1;
v.tx_en := '0';
end if;
end if;
when check_attempts =>
v.transmitting := '0';
if r.retry_cnt = maxattempts then
v.main_state := finish; v.status(1) := '1';
else
v.main_state := calc_backoff; v.restart := not r.restart;
end if;
v.tx_en := '0';
when calc_backoff =>
v.delay_val := (others => '0');
for i in 1 to backoff_limit-1 loop
if i < conv_integer(r.retry_cnt)+1 then
v.delay_val(i) := r.random(i);
end if;
end loop;
v.main_state := wait_backoff; v.slot_count := (others => '1');
when wait_backoff =>
if conv_integer(r.delay_val) = 0 then
v.main_state := idle;
end if;
v.slot_count := r.slot_count - 1;
if conv_integer(r.slot_count) = 0 then
v.slot_count := (others => '1'); v.delay_val := r.delay_val - 1;
end if;
when others =>
v.main_state := idle;
end case;
--random values;
v.random := r.random(8 downto 0) & (not (r.random(2) xor r.random(9)));
--deference
case r.def_state is
when monitor =>
v.was_transmitting := '0';
if ( (crs and not r.fullduplex(1)) or
(r.transmitting and r.fullduplex(1)) ) = '1' then
v.deferring := '1'; v.def_state := def_on;
v.was_transmitting := r.transmitting;
end if;
when def_on =>
v.was_transmitting := r.was_transmitting or r.transmitting;
if r.fullduplex(1) = '1' then
if r.transmitting = '0' then v.def_state := ifg1; end if;
v.ifg_cycls := ifg_sel(rmii, 1, r.speed(1));
else
if (r.transmitting or crs) = '0' then
v.def_state := ifg1; v.ifg_cycls := ifg_sel(rmii, 1, r.speed(1));
end if;
end if;
when ifg1 =>
v.ifg_cycls := r.ifg_cycls - 1;
if r.ifg_cycls = zero32(ifg_bits-1 downto 0) then
v.def_state := ifg2;
v.ifg_cycls := ifg_sel(rmii, 0, r.speed(1));
elsif (crs and not r.fullduplex(1)) = '1' then
v.ifg_cycls := ifg_sel(rmii, 1, r.speed(1));
end if;
when ifg2 =>
v.ifg_cycls := r.ifg_cycls - 1;
if r.ifg_cycls = zero32(ifg_bits-1 downto 0) then
v.deferring := '0';
if (r.fullduplex(1) or not frame_waiting) = '1' then
v.def_state := monitor;
elsif frame_waiting = '1' then
v.def_state := frame_waitingst;
end if;
end if;
when frame_waitingst =>
if frame_waiting = '0' then v.def_state := monitor; end if;
when others => v.def_state := monitor;
end case;
if rmii = 1 then
v.txd_msb := v.txd(3 downto 2);
end if;
if txrst = '0' then
v.main_state := idle; v.random := (others => '0');
v.def_state := monitor; v.deferring := '0'; v.tx_en := '0';
v.done := '0'; v.restart := '0'; v.read := '0';
v.start := (others => '0'); v.read_ack := (others => '0');
v.icnt := (others => '0'); v.delay_val := (others => '0');
v.ifg_cycls := (others => '0');
v.crs_act := '0';
v.slot_count := (others => '1');
v.retry_cnt := (others => '0');
v.cnt := (others => '0');
end if;
rin <= v;
txo.tx_er <= '0';
txo.tx_en <= r.tx_en;
txo.txd <= r.txd;
txo.done <= r.done;
txo.read <= r.read;
txo.restart <= r.restart;
txo.status <= r.status;
end process;
gmiimode0 : if gmiimode = 0 generate
txregs0 : process(clk) is
begin
if rising_edge(clk) then
r <= rin;
if txrst = '0' then
r.icnt <= (others => '0'); r.delay_val <= (others => '0');
r.cnt <= (others => '0');
else
r.icnt <= rin.icnt; r.delay_val <= rin.delay_val;
r.cnt <= rin.cnt;
end if;
end if;
end process;
end generate;
gmiimode1 : if gmiimode = 1 generate
txregs0 : process(clk) is
begin
if rising_edge(clk) then
if (txi.datavalid = '1' or txrst = '0') then r <= rin; end if;
if txrst = '0' then
r.icnt <= (others => '0'); r.delay_val <= (others => '0');
r.cnt <= (others => '0');
else
if txi.datavalid = '1' then
r.icnt <= rin.icnt; r.delay_val <= rin.delay_val;
r.cnt <= rin.cnt;
end if;
end if;
end if;
end process;
end generate;
end architecture;
| gpl-3.0 | adb0be74786ef5764efd2a5f5daeba0b | 0.517153 | 3.204529 | false | false | false | false |
EliasLuiz/TCC | Leon3/lib/gaisler/leon3/leon3.in.vhd | 1 | 3,526 | -- LEON3 processor core
constant CFG_LEON3 : integer := CONFIG_LEON3;
constant CFG_NCPU : integer := CONFIG_PROC_NUM;
constant CFG_NWIN : integer := CONFIG_IU_NWINDOWS;
constant CFG_V8 : integer := CFG_IU_V8 + 4*CFG_IU_MUL_STRUCT;
constant CFG_MAC : integer := CONFIG_IU_MUL_MAC;
constant CFG_BP : integer := CONFIG_IU_BP;
constant CFG_SVT : integer := CONFIG_IU_SVT;
constant CFG_RSTADDR : integer := 16#CONFIG_IU_RSTADDR#;
constant CFG_LDDEL : integer := CONFIG_IU_LDELAY;
constant CFG_NOTAG : integer := CONFIG_NOTAG;
constant CFG_NWP : integer := CONFIG_IU_WATCHPOINTS;
constant CFG_PWD : integer := CONFIG_PWD*2;
constant CFG_FPU : integer := CONFIG_FPU + 16*CONFIG_FPU_NETLIST + 32*CONFIG_FPU_GRFPU_SHARED;
constant CFG_GRFPUSH : integer := CONFIG_FPU_GRFPU_SHARED;
constant CFG_ICEN : integer := CONFIG_ICACHE_ENABLE;
constant CFG_ISETS : integer := CFG_IU_ISETS;
constant CFG_ISETSZ : integer := CFG_ICACHE_SZ;
constant CFG_ILINE : integer := CFG_ILINE_SZ;
constant CFG_IREPL : integer := CFG_ICACHE_ALGORND;
constant CFG_ILOCK : integer := CONFIG_ICACHE_LOCK;
constant CFG_ILRAMEN : integer := CONFIG_ICACHE_LRAM;
constant CFG_ILRAMADDR: integer := 16#CONFIG_ICACHE_LRSTART#;
constant CFG_ILRAMSZ : integer := CFG_ILRAM_SIZE;
constant CFG_DCEN : integer := CONFIG_DCACHE_ENABLE;
constant CFG_DSETS : integer := CFG_IU_DSETS;
constant CFG_DSETSZ : integer := CFG_DCACHE_SZ;
constant CFG_DLINE : integer := CFG_DLINE_SZ;
constant CFG_DREPL : integer := CFG_DCACHE_ALGORND;
constant CFG_DLOCK : integer := CONFIG_DCACHE_LOCK;
constant CFG_DSNOOP : integer := CONFIG_DCACHE_SNOOP_SP + CONFIG_DCACHE_SNOOP*2 + 4*CONFIG_DCACHE_SNOOP_SEPTAG;
constant CFG_DFIXED : integer := 16#CONFIG_CACHE_FIXED#;
constant CFG_DLRAMEN : integer := CONFIG_DCACHE_LRAM;
constant CFG_DLRAMADDR: integer := 16#CONFIG_DCACHE_LRSTART#;
constant CFG_DLRAMSZ : integer := CFG_DLRAM_SIZE;
constant CFG_MMUEN : integer := CONFIG_MMUEN;
constant CFG_ITLBNUM : integer := CONFIG_ITLBNUM;
constant CFG_DTLBNUM : integer := CONFIG_DTLBNUM;
constant CFG_TLB_TYPE : integer := CONFIG_TLB_TYPE + CFG_MMU_FASTWB*2;
constant CFG_TLB_REP : integer := CONFIG_TLB_REP;
constant CFG_MMU_PAGE : integer := CONFIG_MMU_PAGE;
constant CFG_DSU : integer := CONFIG_DSU_ENABLE;
constant CFG_ITBSZ : integer := CFG_DSU_ITB + 64*CONFIG_DSU_ITRACE_2P;
constant CFG_ATBSZ : integer := CFG_DSU_ATB;
constant CFG_AHBPF : integer := CFG_DSU_AHBPF;
constant CFG_LEON3FT_EN : integer := CONFIG_LEON3FT_EN;
constant CFG_IUFT_EN : integer := CONFIG_IUFT_EN;
constant CFG_FPUFT_EN : integer := CONFIG_FPUFT;
constant CFG_RF_ERRINJ : integer := CONFIG_RF_ERRINJ;
constant CFG_CACHE_FT_EN : integer := CONFIG_CACHE_FT_EN;
constant CFG_CACHE_ERRINJ : integer := CONFIG_CACHE_ERRINJ;
constant CFG_LEON3_NETLIST: integer := CONFIG_LEON3_NETLIST;
constant CFG_DISAS : integer := CONFIG_IU_DISAS + CONFIG_IU_DISAS_NET;
constant CFG_PCLOW : integer := CFG_DEBUG_PC32;
constant CFG_STAT_ENABLE : integer := CONFIG_STAT_ENABLE;
constant CFG_STAT_CNT : integer := CONFIG_STAT_CNT;
constant CFG_STAT_NMAX : integer := CONFIG_STAT_NMAX;
constant CFG_STAT_DSUEN : integer := CONFIG_STAT_DSUEN;
constant CFG_NP_ASI : integer := CONFIG_NP_ASI;
constant CFG_WRPSR : integer := CONFIG_WRPSR;
constant CFG_ALTWIN : integer := CONFIG_ALTWIN;
constant CFG_REX : integer := CONFIG_REX;
| gpl-3.0 | eab787d9bba40779a84b771eb592f307 | 0.692853 | 3.295327 | false | true | false | false |
hoglet67/CoPro6502 | src/T80/T80a.vhd | 8 | 7,490 | -- ****
-- T80(b) core. In an effort to merge and maintain bug fixes ....
--
--
-- Ver 300 started tidyup
-- MikeJ March 2005
-- Latest version from www.fpgaarcade.com (original www.opencores.org)
--
-- ****
--
-- Z80 compatible microprocessor core, asynchronous top level
--
-- Version : 0247
--
-- Copyright (c) 2001-2002 Daniel Wallner ([email protected])
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
-- http://www.opencores.org/cvsweb.shtml/t80/
--
-- Limitations :
--
-- File history :
--
-- 0208 : First complete release
--
-- 0211 : Fixed interrupt cycle
--
-- 0235 : Updated for T80 interface change
--
-- 0238 : Updated for T80 interface change
--
-- 0240 : Updated for T80 interface change
--
-- 0242 : Updated for T80 interface change
--
-- 0247 : Fixed bus req/ack cycle
--
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.T80_Pack.all;
entity T80a is
generic(
Mode : integer := 0 -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB
);
port(
RESET_n : in std_logic;
CLK_n : in std_logic;
WAIT_n : in std_logic;
INT_n : in std_logic;
NMI_n : in std_logic;
BUSRQ_n : in std_logic;
M1_n : out std_logic;
MREQ_n : out std_logic;
IORQ_n : out std_logic;
RD_n : out std_logic;
WR_n : out std_logic;
RFSH_n : out std_logic;
HALT_n : out std_logic;
BUSAK_n : out std_logic;
A : out std_logic_vector(15 downto 0);
D : inout std_logic_vector(7 downto 0)
);
end T80a;
architecture rtl of T80a is
signal CEN : std_logic;
signal Reset_s : std_logic;
signal IntCycle_n : std_logic;
signal IORQ : std_logic;
signal NoRead : std_logic;
signal Write : std_logic;
signal MREQ : std_logic;
signal MReq_Inhibit : std_logic;
signal Req_Inhibit : std_logic;
signal RD : std_logic;
signal MREQ_n_i : std_logic;
signal IORQ_n_i : std_logic;
signal RD_n_i : std_logic;
signal WR_n_i : std_logic;
signal RFSH_n_i : std_logic;
signal BUSAK_n_i : std_logic;
signal A_i : std_logic_vector(15 downto 0);
signal DO : std_logic_vector(7 downto 0);
signal DI_Reg : std_logic_vector (7 downto 0); -- Input synchroniser
signal Wait_s : std_logic;
signal MCycle : std_logic_vector(2 downto 0);
signal TState : std_logic_vector(2 downto 0);
begin
CEN <= '1';
BUSAK_n <= BUSAK_n_i;
MREQ_n_i <= not MREQ or (Req_Inhibit and MReq_Inhibit);
RD_n_i <= not RD or Req_Inhibit;
MREQ_n <= MREQ_n_i when BUSAK_n_i = '1' else 'Z';
IORQ_n <= IORQ_n_i when BUSAK_n_i = '1' else 'Z';
RD_n <= RD_n_i when BUSAK_n_i = '1' else 'Z';
WR_n <= WR_n_i when BUSAK_n_i = '1' else 'Z';
RFSH_n <= RFSH_n_i when BUSAK_n_i = '1' else 'Z';
A <= A_i when BUSAK_n_i = '1' else (others => 'Z');
D <= DO when Write = '1' and BUSAK_n_i = '1' else (others => 'Z');
process (RESET_n, CLK_n)
begin
if RESET_n = '0' then
Reset_s <= '0';
elsif CLK_n'event and CLK_n = '1' then
Reset_s <= '1';
end if;
end process;
u0 : T80
generic map(
Mode => Mode,
IOWait => 1)
port map(
CEN => CEN,
M1_n => M1_n,
IORQ => IORQ,
NoRead => NoRead,
Write => Write,
RFSH_n => RFSH_n_i,
HALT_n => HALT_n,
WAIT_n => Wait_s,
INT_n => INT_n,
NMI_n => NMI_n,
RESET_n => Reset_s,
BUSRQ_n => BUSRQ_n,
BUSAK_n => BUSAK_n_i,
CLK_n => CLK_n,
A => A_i,
DInst => D,
DI => DI_Reg,
DO => DO,
MC => MCycle,
TS => TState,
IntCycle_n => IntCycle_n);
process (CLK_n)
begin
if CLK_n'event and CLK_n = '0' then
Wait_s <= WAIT_n;
if TState = "011" and BUSAK_n_i = '1' then
DI_Reg <= to_x01(D);
end if;
end if;
end process;
process (Reset_s,CLK_n)
begin
if Reset_s = '0' then
WR_n_i <= '1';
elsif CLK_n'event and CLK_n = '1' then
WR_n_i <= '1';
if TState = "001" then -- To short for IO writes !!!!!!!!!!!!!!!!!!!
WR_n_i <= not Write;
end if;
end if;
end process;
process (Reset_s,CLK_n)
begin
if Reset_s = '0' then
Req_Inhibit <= '0';
elsif CLK_n'event and CLK_n = '1' then
if MCycle = "001" and TState = "010" then
Req_Inhibit <= '1';
else
Req_Inhibit <= '0';
end if;
end if;
end process;
process (Reset_s,CLK_n)
begin
if Reset_s = '0' then
MReq_Inhibit <= '0';
elsif CLK_n'event and CLK_n = '0' then
if MCycle = "001" and TState = "010" then
MReq_Inhibit <= '1';
else
MReq_Inhibit <= '0';
end if;
end if;
end process;
process(Reset_s,CLK_n)
begin
if Reset_s = '0' then
RD <= '0';
IORQ_n_i <= '1';
MREQ <= '0';
elsif CLK_n'event and CLK_n = '0' then
if MCycle = "001" then
if TState = "001" then
RD <= IntCycle_n;
MREQ <= IntCycle_n;
IORQ_n_i <= IntCycle_n;
end if;
if TState = "011" then
RD <= '0';
IORQ_n_i <= '1';
MREQ <= '1';
end if;
if TState = "100" then
MREQ <= '0';
end if;
else
if TState = "001" and NoRead = '0' then
RD <= not Write;
IORQ_n_i <= not IORQ;
MREQ <= not IORQ;
end if;
if TState = "011" then
RD <= '0';
IORQ_n_i <= '1';
MREQ <= '0';
end if;
end if;
end if;
end process;
end;
| gpl-3.0 | afb93652da33814c48de0d34d179cd09 | 0.565421 | 3.055896 | false | false | false | false |
EliasLuiz/TCC | Leon3/designs/leon3-avnet-eval-xc4vlx60/ahb2mig_avnet_eval.vhd | 1 | 18,922 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: ahb2mig
-- File: ahb2mig.vhd
-- Author: Jiri Gaisler, Gaisler Research
-- Description: AHB wrapper for Xilinx Virtex5 DDR2/3 MIG
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
package avnet_eval is
constant APPDATA_WIDTH : integer := 32; -- # of usr read/write data bus bits.
constant ADDR_WIDTH : integer := 36; -- # of memory row and # of addr bits.
constant MIGHMASK : integer := 16#FE0#; -- AHB mask for 256 Mbyte memory
-- constant MIGHMASK : integer := 16#E00#; -- AHB mask for 512 Mbyte memory
-- constant MIGHMASK : integer := 16#C00#; -- AHB mask for 1024 Mbyte memory
type mig_app_in_type is record
app_wdf_wren : std_logic;
app_wdf_data : std_logic_vector(APPDATA_WIDTH-1 downto 0);
app_wdf_mask : std_logic_vector(APPDATA_WIDTH/8-1 downto 0);
app_addr : std_logic_vector(ADDR_WIDTH-1 downto 0);
app_en : std_logic;
mig_rst : std_logic;
end record;
type mig_app_out_type is record
app_af_afull : std_logic;
app_wdf_afull : std_logic;
app_rd_data : std_logic_vector(APPDATA_WIDTH-1 downto 0);
app_rd_data_valid : std_logic;
end record;
end package;
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
library gaisler;
use grlib.devices.all;
use gaisler.memctrl.all;
library techmap;
use techmap.gencomp.all;
use work.avnet_eval.all;
entity ahb2mig_avnet_eval is
generic (
memtech : integer := 0;
hindex : integer := 0;
haddr : integer := 0;
hmask : integer := 16#e00#;
MHz : integer := 100;
Mbyte : integer := 512;
nosync : integer := 0
);
port (
rst_ddr : in std_ulogic;
rst_ahb : in std_ulogic;
rst_50 : in std_ulogic;
clk_ddr : in std_ulogic;
clk_ahb : in std_ulogic;
clk_50 : in std_ulogic;
init_done : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
migi : out mig_app_in_type;
migo : in mig_app_out_type
);
end;
architecture rtl of ahb2mig_avnet_eval is
constant REVISION : integer := 0;
constant hconfig : ahb_config_type := (
0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_MIGDDR2, 0, REVISION, 0),
4 => ahb_membar(haddr, '1', '1', hmask),
others => zero32);
type ahb_state_type is (midle, rhold, dread, dwrite, whold1, whold2);
type ddr_state_type is (midle, rhold1, rhold2, rhold3, rhold4, rhold5, rhold6, rhold7, dread,
whold1, whold2, whold3, whold4, whold5, whold6, whold7);
constant abuf : integer := 6;
type access_param is record
haddr : std_logic_vector(31 downto 0);
size : std_logic_vector(2 downto 0);
hwrite : std_ulogic;
end record;
-- local registers
type mem is array(0 to 7) of std_logic_vector(31 downto 0);
type wrm is array(0 to 7) of std_logic_vector(3 downto 0);
type ahb_reg_type is record
hready : std_ulogic;
hsel : std_ulogic;
startsd : std_ulogic;
state : ahb_state_type;
haddr : std_logic_vector(31 downto 0);
hrdata : std_logic_vector(127 downto 0);
hwrite : std_ulogic;
htrans : std_logic_vector(1 downto 0);
hresp : std_logic_vector(1 downto 0);
raddr : std_logic_vector(abuf-1 downto 0);
size : std_logic_vector(2 downto 0);
acc : access_param;
sync : std_ulogic;
hwdata : mem;
write : wrm;
end record;
type ddr_reg_type is record
startsd : std_ulogic;
hrdata : std_logic_vector(255 downto 0);
sync : std_ulogic;
dstate : ddr_state_type;
addr : std_logic_vector(2 downto 0);
end record;
signal vcc, clk_ahb1, clk_ahb2 : std_ulogic;
signal r, ri : ddr_reg_type;
signal ra, rai : ahb_reg_type;
signal rbdrive, ribdrive : std_logic_vector(31 downto 0);
signal hwdata, hwdatab : std_logic_vector(127 downto 0);
signal rdel : std_logic_vector(25 downto 0);
begin
vcc <= '1';
ahb_ctrl : process(rst_ahb, ahbsi, r, ra, migo, hwdata)
variable va : ahb_reg_type; -- local variables for registers
variable startsd : std_ulogic;
variable ready : std_logic;
variable tmp : std_logic_vector(3 downto 0);
variable waddr : integer;
variable rdata : std_logic_vector(127 downto 0);
begin
va := ra; va.hresp := HRESP_OKAY;
tmp := (others => '0');
case ra.raddr(2 downto 2) is
when "0" => rdata := r.hrdata(127 downto 0);
when others => rdata := r.hrdata(255 downto 128);
end case;
if AHBDW > 64 and ra.size = HSIZE_4WORD then
va.hrdata := rdata(127 downto 0);
elsif AHBDW > 32 and ra.size = HSIZE_DWORD then
if ra.raddr(1) = '1' then va.hrdata(63 downto 0) := rdata(127 downto 64);
else va.hrdata(63 downto 0) := rdata(63 downto 0); end if;
va.hrdata(127 downto 64) := va.hrdata(63 downto 0);
else
case ra.raddr(1 downto 0) is
when "00" => va.hrdata(31 downto 0) := rdata(31 downto 0);
when "01" => va.hrdata(31 downto 0) := rdata(63 downto 32);
when "10" => va.hrdata(31 downto 0) := rdata(95 downto 64);
when others => va.hrdata(31 downto 0) := rdata(127 downto 96);
end case;
va.hrdata(127 downto 32) := va.hrdata(31 downto 0) &
va.hrdata(31 downto 0) &
va.hrdata(31 downto 0);
end if;
if nosync = 0 then
va.sync := r.startsd;
if ra.startsd = ra.sync then ready := '1';
else ready := '0'; end if;
else
if ra.startsd = r.startsd then ready := '1';
else ready := '0'; end if;
end if;
if ((ahbsi.hready and ahbsi.hsel(hindex)) = '1') then
va.htrans := ahbsi.htrans; va.haddr := ahbsi.haddr;
va.size := ahbsi.hsize(2 downto 0); va.hwrite := ahbsi.hwrite;
if ahbsi.htrans(1) = '1' then
va.hsel := '1'; va.hready := '0';
end if;
end if;
if ahbsi.hready = '1' then va.hsel := ahbsi.hsel(hindex); end if;
case ra.state is
when midle =>
va.write := (others => "0000");
if ((va.hsel and va.htrans(1)) = '1') then
if va.hwrite = '0' then
va.state := rhold; va.startsd := not ra.startsd;
else
va.state := dwrite; va.hready := '1';
end if;
end if;
va.raddr := ra.haddr(7 downto 2);
if ((ahbsi.hready and ahbsi.hsel(hindex)) = '1') then
va.acc := (va.haddr, va.size, va.hwrite);
end if;
when rhold =>
va.raddr := ra.haddr(7 downto 2);
if ready = '1' then
va.state := dread; va.hready := '1';
if AHBDW > 64 and ra.size(2) = '1' then va.raddr := ra.raddr + 4;
elsif AHBDW > 32 and andv(ra.size(1 downto 0)) = '1' then va.raddr := ra.raddr + 2;
else va.raddr := ra.raddr + 1; end if;
end if;
when dread =>
va.hready := '1';
if AHBDW > 64 and ra.size(2) = '1' then va.raddr := ra.raddr + 4;
elsif AHBDW > 32 and andv(ra.size(1 downto 0)) = '1' then va.raddr := ra.raddr + 2;
else va.raddr := ra.raddr + 1; end if;
if ((va.hsel and va.htrans(1) and va.htrans(0)) = '0')
or (ra.raddr(2 downto 0) = "000") then
va.state := midle; va.hready := '0';
end if;
va.acc := (va.haddr, va.size, va.hwrite);
when dwrite =>
va.raddr := ra.haddr(7 downto 2); va.hready := '1';
if (((va.hsel and va.htrans(1) and va.htrans(0)) = '0')
or (ra.haddr(4 downto 2) = "111")
or (AHBDW > 32 and ra.haddr(5 downto 2) = "1110" and andv(ra.size(1 downto 0)) = '1')
or (AHBDW > 64 and ra.haddr(5 downto 2) = "1100" and ra.size(2) = '1')) then
va.startsd := not ra.startsd; va.state := whold1;
va.hready := '0';
end if;
tmp := decode(ra.haddr(1 downto 0));
waddr := conv_integer(ra.haddr(4 downto 2));
va.hwdata(waddr) := hwdata(31 downto 0);
case ra.size is
when "000" => va.write(waddr) := tmp(0) & tmp(1) & tmp(2) & tmp(3);
when "001" => va.write(waddr) := tmp(0) & tmp(0) & tmp(2) & tmp(2);
when "010" => va.write(waddr) := "1111";
when "011" => va.write(waddr) := "1111"; va.write(waddr+1) := "1111";
va.hwdata(waddr+1) := hwdata((63 mod AHBDW) downto (32 mod AHBDW));
when others => va.write(waddr) := "1111"; va.write(waddr+1) := "1111";
va.write(waddr+2) := "1111"; va.write(waddr+3) := "1111";
va.hwdata(waddr+1) := hwdata((63 mod AHBDW) downto (32 mod AHBDW));
va.hwdata(waddr+2) := hwdata((95 mod AHBDW) downto (64 mod AHBDW));
va.hwdata(waddr+3) := hwdata((127 mod AHBDW) downto (96 mod AHBDW));
end case;
when whold1 =>
va.state := whold2;
when whold2 =>
if ready = '1' then
va.state := midle; va.acc := (va.haddr, va.size, va.hwrite);
end if;
end case;
if (ahbsi.hready and ahbsi.hsel(hindex) ) = '1' then
if ahbsi.htrans(1) = '0' then va.hready := '1'; end if;
end if;
if rst_ahb = '0' then
va.hsel := '0';
va.hready := '1';
va.state := midle;
va.startsd := '0';
va.acc.hwrite := '0';
va.acc.haddr := (others => '0');
end if;
rai <= va;
end process;
ahbso.hready <= ra.hready;
ahbso.hresp <= ra.hresp;
ahbso.hrdata <= ahbdrivedata(ra.hrdata);
-- delayed reset for the MIG, will not work otherwise ...
rstp : process(clk_50)
begin
if rising_edge(clk_50) then
if rdel(25) = '0' then rdel <= rdel + 1; end if;
if rst_50 = '0' then
rdel <= (others => '0');
-- pragma translate_off
rdel <= (25 => '0', 2 => '0', others => '1');
-- pragma translate_on
end if;
end if;
end process;
ddr_ctrl : process(rst_ddr, r, ra, migo, init_done, rdel)
variable v : ddr_reg_type; -- local variables for registers
variable startsd : std_ulogic;
variable raddr : std_logic_vector(13 downto 0);
variable adec : std_ulogic;
variable haddr : std_logic_vector(31 downto 0);
variable hsize : std_logic_vector(1 downto 0);
variable hwrite : std_ulogic;
variable htrans : std_logic_vector(1 downto 0);
variable hready : std_ulogic;
variable app_en : std_ulogic;
variable app_cmd : std_logic_vector(2 downto 0);
variable app_wdf_mask : std_logic_vector(APPDATA_WIDTH/8-1 downto 0);
variable app_wdf_wren : std_ulogic;
variable app_wdf_data : std_logic_vector(APPDATA_WIDTH-1 downto 0);
variable app_addr : std_logic_vector(ADDR_WIDTH-1 downto 0);
begin
-- Variable default settings to avoid latches
v := r; app_en := '0'; app_cmd := "100"; app_wdf_wren := '0';
app_wdf_mask := (others => '0');
app_wdf_mask := ra.write(0);
app_wdf_data := (others => '0');
app_wdf_data(31 downto 0) := ra.hwdata(0);
if ra.acc.hwrite = '0' then app_cmd(0) := '1'; else app_cmd(0) := '0'; end if;
app_addr := '0' & app_cmd & "00000" & ra.acc.haddr(27 downto 5) & r.addr(0) & "000";
v.sync := ra.startsd;
if nosync = 0 then
if r.startsd /= r.sync then startsd := '1';
else startsd := '0'; end if;
else
if ra.startsd /= r.startsd then startsd := '1';
else startsd := '0'; end if;
end if;
case r.dstate is
when midle =>
v.addr := "00" & ra.acc.haddr(4); app_addr(3) := ra.acc.haddr(4);
if (startsd = '1') and (migo.app_af_afull = '0') and (init_done = '1') then
if ra.acc.hwrite = '0' then
if ra.acc.haddr(4) = '0' then
v.dstate := dread; v.addr := r.addr + 1;
else v.dstate := rhold4; end if;
app_en := '1';
elsif migo.app_wdf_afull = '0' then
if ra.acc.haddr(4) = '0' then
v.dstate := whold1; v.addr := r.addr + 1;
else
v.dstate := whold5;
app_wdf_mask(3 downto 0) := ra.write(4);
app_wdf_data(31 downto 0) := ra.hwdata(4);
end if;
app_en := '1'; app_wdf_wren := '1';
end if;
end if;
when dread =>
if r.addr(0) = '1' then
v.addr := r.addr + 1; app_en := '1';
end if;
if migo.app_rd_data_valid = '1' then
v.hrdata(31 downto 0) := migo.app_rd_data(31 downto 0);
v.dstate := rhold1;
end if;
when rhold1 =>
if migo.app_rd_data_valid = '1' then
v.hrdata(63 downto 32) := migo.app_rd_data(31 downto 0);
v.dstate := rhold2;
end if;
when rhold2 =>
if migo.app_rd_data_valid = '1' then
v.hrdata(95 downto 64) := migo.app_rd_data(31 downto 0);
v.dstate := rhold3;
end if;
when rhold3 =>
if migo.app_rd_data_valid = '1' then
v.hrdata(127 downto 96) := migo.app_rd_data(31 downto 0);
v.dstate := rhold4;
end if;
when rhold4 =>
if migo.app_rd_data_valid = '1' then
v.hrdata(159 downto 128) := migo.app_rd_data(31 downto 0);
v.dstate := rhold5;
end if;
when rhold5 =>
if migo.app_rd_data_valid = '1' then
v.hrdata(191 downto 160) := migo.app_rd_data(31 downto 0);
v.dstate := rhold6;
end if;
when rhold6 =>
if migo.app_rd_data_valid = '1' then
v.hrdata(223 downto 192) := migo.app_rd_data(31 downto 0);
v.dstate := rhold7;
end if;
when rhold7 =>
if migo.app_rd_data_valid = '1' then
v.hrdata(255 downto 224) := migo.app_rd_data(31 downto 0);
v.dstate := midle;
v.startsd := not r.startsd;
end if;
when whold1 =>
app_wdf_wren := '1';
app_wdf_mask(3 downto 0) := ra.write(1);
app_wdf_data(31 downto 0) := ra.hwdata(1);
v.dstate := whold2;
when whold2 =>
app_wdf_wren := '1';
app_wdf_mask(3 downto 0) := ra.write(2);
app_wdf_data(31 downto 0) := ra.hwdata(2);
v.dstate := whold3;
when whold3 =>
app_wdf_wren := '1';
app_wdf_mask(3 downto 0) := ra.write(3);
app_wdf_data(31 downto 0) := ra.hwdata(3);
if (ra.write(4) = "0000") and (ra.write(5) = "0000") and (ra.write(6) = "0000") and
(ra.write(7) = "0000")
then v.startsd := not r.startsd; v.dstate := midle;
elsif migo.app_wdf_afull = '0' then v.dstate := whold4; app_en := '1'; end if;
when whold4 =>
app_wdf_wren := '1';
app_wdf_mask(3 downto 0) := ra.write(4);
app_wdf_data(31 downto 0) := ra.hwdata(4);
v.dstate := whold5;
when whold5 =>
app_wdf_wren := '1';
app_wdf_mask(3 downto 0) := ra.write(5);
app_wdf_data(31 downto 0) := ra.hwdata(5);
v.dstate := whold6;
when whold6 =>
app_wdf_wren := '1';
app_wdf_mask(3 downto 0) := ra.write(6);
app_wdf_data(31 downto 0) := ra.hwdata(6);
v.dstate := whold7;
when whold7 =>
app_wdf_wren := '1';
app_wdf_mask(3 downto 0) := ra.write(7);
app_wdf_data(31 downto 0) := ra.hwdata(7);
v.startsd := not r.startsd;
v.dstate := midle;
when others =>
end case;
-- reset
if rst_ddr = '0' then
v.startsd := '0';
app_en := '0';
v.dstate := midle;
v.addr := "000";
end if;
ri <= v;
migi.app_addr <= app_addr;
migi.app_en <= app_en;
migi.app_wdf_wren <= app_wdf_wren;
migi.app_wdf_mask <= not app_wdf_mask;
migi.app_wdf_data <= app_wdf_data;
migi.mig_rst <= rdel(25);
end process;
ahbso.hconfig <= hconfig;
ahbso.hirq <= (others => '0');
ahbso.hindex <= hindex;
ahbso.hsplit <= (others => '0');
clk_ahb1 <= clk_ahb; clk_ahb2 <= clk_ahb1; -- sync clock deltas
ahbregs : process(clk_ahb2) begin
if rising_edge(clk_ahb2) then
ra <= rai;
end if;
end process;
ddrregs : process(clk_ddr) begin
if rising_edge(clk_ddr) then
r <= ri;
end if;
end process;
-- Write data selection.
AHB32: if AHBDW = 32 generate
hwdata <= ahbsi.hwdata(31 downto 0) & ahbsi.hwdata(31 downto 0) &
ahbsi.hwdata(31 downto 0) & ahbsi.hwdata(31 downto 0);
end generate AHB32;
AHB64: if AHBDW = 64 generate
-- With CORE_ACDM set to 0 hwdata will always be ahbsi.hwdata(63 downto 0)
-- otherwise the valid data slice will be selected, and possibly uplicated,
-- from ahbsi.hwdata.
hwdatab(63 downto 0) <= ahbreaddword(ahbsi.hwdata, ra.haddr(4 downto 2)) when (CORE_ACDM = 0 or ra.size(1 downto 0) = "11") else
(ahbreadword(ahbsi.hwdata, ra.haddr(4 downto 2)) &
ahbreadword(ahbsi.hwdata, ra.haddr(4 downto 2)));
hwdata <= hwdatab(31 downto 0) & hwdatab(63 downto 32) &
hwdatab(31 downto 0) & hwdatab(63 downto 32);
end generate AHB64;
AHBWIDE: if AHBDW > 64 generate
-- With CORE_ACDM set to 0 hwdata will always be ahbsi.hwdata(127 downto 0)
-- otherwise the valid data slice will be selected, and possibly uplicated,
-- from ahbsi.hwdata.
hwdatab <= ahbread4word(ahbsi.hwdata, ra.haddr(4 downto 2)) when (CORE_ACDM = 0 or ra.size(2) = '1') else
(ahbreaddword(ahbsi.hwdata, ra.haddr(4 downto 2)) &
ahbreaddword(ahbsi.hwdata, ra.haddr(4 downto 2))) when (ra.size = "011") else
(ahbreadword(ahbsi.hwdata, ra.haddr(4 downto 2)) &
ahbreadword(ahbsi.hwdata, ra.haddr(4 downto 2)) &
ahbreadword(ahbsi.hwdata, ra.haddr(4 downto 2)) &
ahbreadword(ahbsi.hwdata, ra.haddr(4 downto 2)));
hwdata <= hwdatab(31 downto 0) & hwdatab(63 downto 32) &
hwdatab(95 downto 64) & hwdatab(127 downto 96);
end generate AHBWIDE;
-- pragma translate_off
bootmsg : report_version
generic map (
msg1 => "ahb2mig" & tost(hindex) & ": 32-bit DDR controller rev " &
tost(REVISION) & ", " & tost(Mbyte) & " Mbyte, " & tost(MHz) &
" MHz DDR clock");
-- pragma translate_on
end;
| gpl-3.0 | 7dc2aa3eba54abdc42d2a64df92c687a | 0.57309 | 3.179634 | false | false | false | false |
pwsoft/fpga_examples | rtl/ttl/ttl_74573.vhd | 1 | 4,117 | -- -----------------------------------------------------------------------
--
-- Syntiac VHDL support files.
--
-- -----------------------------------------------------------------------
-- Copyright 2005-2018 by Peter Wendrich ([email protected])
-- http://www.syntiac.com
--
-- This source file is free software: you can redistribute it and/or modify
-- it under the terms of the GNU Lesser General Public License as published
-- by the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This source file is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
-- -----------------------------------------------------------------------
-- Octal D-type transparent latch; 3-state
-- -----------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.ALL;
use work.ttl_pkg.all;
-- -----------------------------------------------------------------------
entity ttl_74573 is
generic (
latency : integer := 2
);
port (
emuclk : in std_logic;
p1 : in ttl_t; -- OEn
p2 : in ttl_t; -- D0
p3 : in ttl_t; -- D1
p4 : in ttl_t; -- D2
p5 : in ttl_t; -- D3
p6 : in ttl_t; -- D4
p7 : in ttl_t; -- D5
p8 : in ttl_t; -- D6
p9 : in ttl_t; -- D7
p11 : in ttl_t; -- LE
p12 : out ttl_t; -- Q7
p13 : out ttl_t; -- Q6
p14 : out ttl_t; -- Q5
p15 : out ttl_t; -- Q4
p16 : out ttl_t; -- Q3
p17 : out ttl_t; -- Q2
p18 : out ttl_t; -- Q1
p19 : out ttl_t -- Q0
);
end entity;
architecture rtl of ttl_74573 is
signal p12_loc : ttl_t;
signal p13_loc : ttl_t;
signal p14_loc : ttl_t;
signal p15_loc : ttl_t;
signal p16_loc : ttl_t;
signal p17_loc : ttl_t;
signal p18_loc : ttl_t;
signal p19_loc : ttl_t;
signal latch_reg : unsigned(7 downto 0) := (others => '0');
begin
p12_latency_inst : entity work.ttl_latency
generic map (latency => latency)
port map (clk => emuclk, d => p12_loc, q => p12);
p13_latency_inst : entity work.ttl_latency
generic map (latency => latency)
port map (clk => emuclk, d => p13_loc, q => p13);
p14_latency_inst : entity work.ttl_latency
generic map (latency => latency)
port map (clk => emuclk, d => p14_loc, q => p14);
p15_latency_inst : entity work.ttl_latency
generic map (latency => latency)
port map (clk => emuclk, d => p15_loc, q => p15);
p16_latency_inst : entity work.ttl_latency
generic map (latency => latency)
port map (clk => emuclk, d => p16_loc, q => p16);
p17_latency_inst : entity work.ttl_latency
generic map (latency => latency)
port map (clk => emuclk, d => p17_loc, q => p17);
p18_latency_inst : entity work.ttl_latency
generic map (latency => latency)
port map (clk => emuclk, d => p18_loc, q => p18);
p19_latency_inst : entity work.ttl_latency
generic map (latency => latency)
port map (clk => emuclk, d => p19_loc, q => p19);
p12_loc <= FLOAT when is_high(p1) else std2ttl(latch_reg(7));
p13_loc <= FLOAT when is_high(p1) else std2ttl(latch_reg(6));
p14_loc <= FLOAT when is_high(p1) else std2ttl(latch_reg(5));
p15_loc <= FLOAT when is_high(p1) else std2ttl(latch_reg(4));
p16_loc <= FLOAT when is_high(p1) else std2ttl(latch_reg(3));
p17_loc <= FLOAT when is_high(p1) else std2ttl(latch_reg(2));
p18_loc <= FLOAT when is_high(p1) else std2ttl(latch_reg(1));
p19_loc <= FLOAT when is_high(p1) else std2ttl(latch_reg(0));
process(emuclk)
begin
if rising_edge(emuclk) then
if is_high(p11) then
latch_reg(0) <= ttl2std(p2);
latch_reg(1) <= ttl2std(p3);
latch_reg(2) <= ttl2std(p4);
latch_reg(3) <= ttl2std(p5);
latch_reg(4) <= ttl2std(p6);
latch_reg(5) <= ttl2std(p7);
latch_reg(6) <= ttl2std(p8);
latch_reg(7) <= ttl2std(p9);
end if;
end if;
end process;
end architecture;
| lgpl-2.1 | 5d03731945f79d7292ce3b9bf3b72171 | 0.584649 | 2.855062 | false | false | false | false |
EliasLuiz/TCC | Leon3/designs/leon3-altera-ep2s60-ddr/leon3mp.vhd | 1 | 21,068 | -----------------------------------------------------------------------------
-- LEON3 Demonstration design
-- Copyright (C) 2004 Jiri Gaisler, Gaisler Research
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
library techmap;
use techmap.gencomp.all;
library gaisler;
use gaisler.memctrl.all;
use gaisler.ddrpkg.all;
use gaisler.leon3.all;
use gaisler.uart.all;
use gaisler.misc.all;
use gaisler.jtag.all;
library esa;
use esa.memoryctrl.all;
use work.config.all;
entity leon3mp is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
clktech : integer := CFG_CLKTECH;
ncpu : integer := CFG_NCPU;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW;
freq : integer := 50000 -- frequency of main clock (used for PLLs)
);
port (
resetn : in std_ulogic;
clk : in std_ulogic;
errorn : out std_ulogic;
-- flash/ethernet bus
address : out std_logic_vector(23 downto 0);
data : inout std_logic_vector(31 downto 0);
romsn : out std_ulogic;
oen : out std_logic;
writen : out std_logic;
byten : out std_logic;
wpn : out std_logic;
-- SSRAM
ssram_ce1n : out std_logic;
ssram_ce2 : out std_logic;
ssram_ce3n : out std_logic;
ssram_wen : out std_logic;
ssram_bw : out std_logic_vector (0 to 3);
ssram_oen : out std_ulogic;
ssaddr : out std_logic_vector(20 downto 2);
ssdata : inout std_logic_vector(31 downto 0);
ssram_clk : out std_ulogic;
ssram_adscn : out std_ulogic;
ssram_adsp_n : out std_ulogic;
ssram_adv_n : out std_ulogic;
-- pragma translate_off
iosn : out std_ulogic;
-- pragma translate_on
ddr_clkin : in std_logic;
ddr_clk : out std_logic;
ddr_clkn : out std_logic;
ddr_cke : out std_logic;
ddr_csb : out std_logic;
ddr_web : out std_ulogic; -- ddr write enable
ddr_rasb : out std_ulogic; -- ddr ras
ddr_casb : out std_ulogic; -- ddr cas
ddr_dm : out std_logic_vector (1 downto 0); -- ddr dm
ddr_dqs : inout std_logic_vector (1 downto 0); -- ddr dqs
ddr_ad : out std_logic_vector (12 downto 0); -- ddr address
ddr_ba : out std_logic_vector (1 downto 0); -- ddr bank address
ddr_dq : inout std_logic_vector (15 downto 0); -- ddr data
-- debug support unit
dsubren : in std_ulogic;
dsuact : out std_ulogic;
-- console/debug UART
rxd1 : in std_logic;
txd1 : out std_logic;
-- for smsc lan chip
eth_aen : out std_logic;
eth_readn : out std_logic;
eth_writen: out std_logic;
eth_nbe : out std_logic_vector(3 downto 0);
eth_lclk : out std_ulogic;
eth_nads : out std_logic;
eth_ncycle : out std_logic;
eth_wnr : out std_logic;
eth_nvlbus : out std_logic;
eth_nrdyrtn : out std_logic;
eth_ndatacs : out std_logic;
gpio : inout std_logic_vector(CFG_GRGPIO_WIDTH-1 downto 0) -- I/O port
);
end;
architecture rtl of leon3mp is
constant blength : integer := 12;
constant fifodepth : integer := 8;
constant maxahbm : integer := NCPU+CFG_AHB_UART+CFG_AHB_JTAG;
signal vcc, gnd : std_logic_vector(7 downto 0);
signal memi, smemi : memory_in_type;
signal memo, smemo : memory_out_type;
signal wpo : wprot_out_type;
signal ddrclkfb, ssrclkfb, ddr_clkl, ddr_clk90l, ddr_clknl, ddr_clk270l : std_ulogic;
signal ddr_clkv : std_logic_vector(2 downto 0);
signal ddr_clkbv : std_logic_vector(2 downto 0);
signal ddr_ckev : std_logic_vector(1 downto 0);
signal ddr_csbv : std_logic_vector(1 downto 0);
signal ddr_adl : std_logic_vector (13 downto 0);
signal clklock, lock, clkml, rst, ndsuact : std_ulogic;
signal tck, tckn, tms, tdi, tdo : std_ulogic;
signal ddrclk, ddrrst : std_ulogic;
-- attribute syn_keep : boolean;
-- attribute syn_preserve : boolean;
-- attribute syn_keep of clkml : signal is true;
-- attribute syn_preserve of clkml : signal is true;
--for smc lan chip
signal s_eth_aen : std_logic;
signal s_eth_readn : std_logic;
signal s_eth_writen: std_logic;
signal s_eth_nbe : std_logic_vector(3 downto 0);
signal ssd, prd : std_logic_vector(31 downto 0);
signal apbi : apb_slv_in_type;
signal apbo : apb_slv_out_vector := (others => apb_none);
signal ahbsi : ahb_slv_in_type;
signal ahbso : ahb_slv_out_vector := (others => ahbs_none);
signal ahbmi : ahb_mst_in_type;
signal ahbmo : ahb_mst_out_vector;
signal clkm, rstn, ssram_clkl : std_ulogic;
signal cgi : clkgen_in_type;
signal cgo : clkgen_out_type;
signal u1i, dui : uart_in_type;
signal u1o, duo : uart_out_type;
signal irqi : irq_in_vector(0 to NCPU-1);
signal irqo : irq_out_vector(0 to NCPU-1);
signal dbgi : l3_debug_in_vector(0 to NCPU-1);
signal dbgo : l3_debug_out_vector(0 to NCPU-1);
signal dsui : dsu_in_type;
signal dsuo : dsu_out_type;
signal gpti : gptimer_in_type;
signal gpioi : gpio_in_type;
signal gpioo : gpio_out_type;
constant IOAEN : integer := 1;
constant BOARD_FREQ : integer := 50000; -- input frequency in KHz
constant CPU_FREQ : integer := BOARD_FREQ * CFG_CLKMUL / CFG_CLKDIV; -- cpu frequency in KHz
signal dsubre : std_ulogic;
component smc_mctrl
generic (
hindex : integer := 0;
pindex : integer := 0;
romaddr : integer := 16#000#;
rommask : integer := 16#E00#;
ioaddr : integer := 16#200#;
iomask : integer := 16#E00#;
ramaddr : integer := 16#400#;
rammask : integer := 16#C00#;
paddr : integer := 0;
pmask : integer := 16#fff#;
wprot : integer := 0;
invclk : integer := 0;
fast : integer := 0;
romasel : integer := 28;
sdrasel : integer := 29;
srbanks : integer := 4;
ram8 : integer := 0;
ram16 : integer := 0;
sden : integer := 0;
sepbus : integer := 0;
sdbits : integer := 32;
sdlsb : integer := 2;
oepol : integer := 0;
syncrst : integer := 0
);
port (
rst : in std_ulogic;
clk : in std_ulogic;
memi : in memory_in_type;
memo : out memory_out_type;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
wpo : in wprot_out_type;
sdo : out sdram_out_type;
eth_aen : out std_ulogic; -- for smsc lan chip
eth_readn : out std_ulogic; -- for smsc lan chip
eth_writen: out std_ulogic; -- for smsc lan chip
eth_nbe : out std_logic_vector(3 downto 0) -- for smsc lan chip
);
end component;
begin
----------------------------------------------------------------------
--- Reset and Clock generation -------------------------------------
----------------------------------------------------------------------
vcc <= (others => '1'); gnd <= (others => '0');
cgi.pllctrl <= "00"; cgi.pllrst <= not resetn; cgi.pllref <= '0';
clklock <= cgo.clklock and lock;
clkgen0 : clkgen -- clock generator using toplevel generic 'freq'
generic map (tech => CFG_CLKTECH, clk_mul => CFG_CLKMUL,
clk_div => CFG_CLKDIV, sdramen => CFG_MCTRL_SDEN,
freq => freq)
port map (clkin => clk, pciclkin => gnd(0), clk => clkm, clkn => open,
clk2x => open, sdclk => ssram_clkl, pciclk => open,
cgi => cgi, cgo => cgo);
ssrclk_pad : outpad generic map (tech => padtech, slew => 1, strength => 24)
port map (ssram_clk, ssram_clkl);
rst0 : rstgen -- reset generator
port map (resetn, clkm, clklock, rstn);
----------------------------------------------------------------------
--- AHB CONTROLLER --------------------------------------------------
----------------------------------------------------------------------
ahb0 : ahbctrl -- AHB arbiter/multiplexer
generic map (defmast => CFG_DEFMST, split => CFG_SPLIT,
rrobin => CFG_RROBIN, ioaddr => CFG_AHBIO,
ioen => IOAEN, nahbm => maxahbm, nahbs => 8)
port map (rstn, clkm, ahbmi, ahbmo, ahbsi, ahbso);
----------------------------------------------------------------------
--- LEON3 processor and DSU -----------------------------------------
----------------------------------------------------------------------
l3 : if CFG_LEON3 = 1 generate
cpu : for i in 0 to NCPU-1 generate
u0 : leon3s -- LEON3 processor
generic map (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU, CFG_V8,
0, CFG_MAC, pclow, CFG_NOTAG, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE,
CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ,
CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN,
CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP,
CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR, NCPU-1, 0, 0,
CFG_MMU_PAGE, CFG_BP, CFG_NP_ASI, CFG_WRPSR)
port map (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso,
irqi(i), irqo(i), dbgi(i), dbgo(i));
end generate;
errorn_pad : odpad generic map (tech => padtech) port map (errorn, dbgo(0).error);
dsugen : if CFG_DSU = 1 generate
dsu0 : dsu3 -- LEON3 Debug Support Unit
generic map (hindex => 2, haddr => 16#900#, hmask => 16#F00#,
ncpu => NCPU, tbits => 30, tech => memtech, irq => 0, kbytes => CFG_ATBSZ)
port map (rstn, clkm, ahbmi, ahbsi, ahbso(2), dbgo, dbgi, dsui, dsuo);
dsui.enable <= '1';
dsubre_pad : inpad generic map (tech => padtech) port map (dsubre, dsui.break);
dsuact_pad : outpad generic map (tech => padtech) port map (dsuact, dsuo.active);
end generate;
end generate;
nodsu : if CFG_DSU = 0 generate
ahbso(2) <= ahbs_none; dsuo.tstop <= '0'; dsuo.active <= '0';
end generate;
dcomgen : if CFG_AHB_UART = 1 generate
dcom0 : ahbuart -- Debug UART
generic map (hindex => NCPU, pindex => 4, paddr => 7)
port map (rstn, clkm, dui, duo, apbi, apbo(4), ahbmi, ahbmo(NCPU));
dsurx_pad : inpad generic map (tech => padtech) port map (rxd1, dui.rxd);
dsutx_pad : outpad generic map (tech => padtech) port map (txd1, duo.txd);
end generate;
nouah : if CFG_AHB_UART = 0 generate apbo(4) <= apb_none; end generate;
ahbjtaggen0 :if CFG_AHB_JTAG = 1 generate
ahbjtag0 : ahbjtag generic map(tech => fabtech, hindex => NCPU+CFG_AHB_UART)
port map(rstn, clkm, tck, tms, tdi, tdo, ahbmi, ahbmo(NCPU+CFG_AHB_UART),
open, open, open, open, open, open, open, gnd(0));
end generate;
----------------------------------------------------------------------
--- Memory controllers ----------------------------------------------
----------------------------------------------------------------------
mg2 : if CFG_MCTRL_LEON2 = 1 generate -- LEON2 memory controller
sr1 : smc_mctrl generic map (hindex => 0, pindex => 0, paddr => 0,
ramaddr => 16#400#+16#600#*CFG_DDRSP, rammask =>16#F00#, srbanks => 1,
sden => 0, ram8 => 1)
port map (rstn, clkm, memi, memo, ahbsi, ahbso(0), apbi, apbo(0), wpo, open,
s_eth_aen, s_eth_readn, s_eth_writen, s_eth_nbe);
end generate;
wpn <= '1'; byten <= '0';
memi.brdyn <= '1'; memi.bexcn <= '1';
memi.writen <= '1'; memi.wrn <= "1111"; memi.bwidth <= "00";
mg0 : if CFG_MCTRL_LEON2 = 0 generate -- no prom/sram pads
apbo(0) <= apb_none; ahbso(0) <= ahbs_none;
roms_pad : outpad generic map (tech => padtech)
port map (romsn, vcc(0));
end generate;
mgpads : if CFG_MCTRL_LEON2 = 1 generate -- prom/sram pads
addr_pad : outpadv generic map (width => 24, tech => padtech)
port map (address, memo.address(23 downto 0));
roms_pad : outpad generic map (tech => padtech)
port map (romsn, memo.romsn(0));
oen_pad : outpad generic map (tech => padtech)
port map (oen, memo.oen);
wri_pad : outpad generic map (tech => padtech)
port map (writen, memo.writen);
-- pragma translate_off
iosn_pad : outpad generic map (tech => padtech)
port map (iosn, memo.iosn);
-- pragma translate_on
ssram_adv_n_pad : outpad generic map (tech => padtech)
port map (ssram_adv_n, vcc(0));
ssram_adsp_n_pad : outpad generic map (tech => padtech)
port map (ssram_adsp_n, gnd(0));
ssaddr_pad : outpadv generic map (width => 19, tech => padtech)
port map (ssaddr, memo.address(20 downto 2));
ssram_adscn_pad : outpad generic map (tech => padtech)
port map (ssram_adscn, vcc(0));
ssram_ce1n_pad : outpad generic map (tech => padtech)
port map (ssram_ce1n, gnd(0));
ssram_ce2_pad : outpad generic map (tech => padtech)
port map (ssram_ce2, vcc(0));
ssrams_pad : outpad generic map ( tech => padtech)
port map (ssram_ce3n, memo.ramsn(0));
ssram_oen_pad : outpad generic map (tech => padtech)
port map (ssram_oen, memo.oen);
ssram_rwen_pad : outpadv generic map (width => 4, tech => padtech)
port map (ssram_bw, memo.wrn);
ssram_wri_pad : outpad generic map (tech => padtech)
port map (ssram_wen, memo.writen);
ssram_data_pads : iopadvv generic map (tech => padtech, width => 32)
port map (ssdata, memo.data, memo.vbdrive, ssd);
memi.data(31 downto 0) <= ssd when memo.ramsn(0) = '0' else prd;
-- for smc lan chip
eth_aen_pad : outpad generic map (tech => padtech)
port map (eth_aen, s_eth_aen);
eth_readn_pad : outpad generic map (tech => padtech)
port map (eth_readn, s_eth_readn);
eth_writen_pad : outpad generic map (tech => padtech)
port map (eth_writen, s_eth_writen);
eth_nbe_pad : outpadv generic map (width => 4, tech => padtech)
port map (eth_nbe, s_eth_nbe);
data_pad : iopadvv generic map (tech => padtech, width => 32)
port map (data(31 downto 0), memo.data(31 downto 0),
memo.vbdrive, prd);
end generate;
ddrsp0 : if (CFG_DDRSP /= 0) generate
ddrc0 : ddrspa generic map ( fabtech => fabtech, memtech => memtech,
hindex => 3, haddr => 16#400#, hmask => 16#F00#, ioaddr => 1,
pwron => CFG_DDRSP_INIT, MHz => BOARD_FREQ/1000,
clkmul => CFG_DDRSP_FREQ/5, clkdiv => 10, ahbfreq => CPU_FREQ/1000,
col => CFG_DDRSP_COL, Mbyte => CFG_DDRSP_SIZE, ddrbits => 16)
port map (
resetn, rstn, ddr_clkin, clkm, lock, clkml, clkml, ahbsi, ahbso(3),
ddr_clkv, ddr_clkbv, open, gnd(0),
ddr_ckev, ddr_csbv, ddr_web, ddr_rasb, ddr_casb,
ddr_dm, ddr_dqs, ddr_adl, ddr_ba, ddr_dq);
ddr_ad <= ddr_adl(12 downto 0);
ddr_clk <= ddr_clkv(0); ddr_clkn <= ddr_clkbv(0);
ddr_cke <= ddr_ckev(0); ddr_csb <= ddr_csbv(0);
end generate;
ddrsp1 : if (CFG_DDRSP = 0) generate
ddr_cke <= '0'; ddr_csb <= '1'; lock <= '1';
end generate;
----------------------------------------------------------------------
--- APB Bridge and various periherals -------------------------------
----------------------------------------------------------------------
apb0 : apbctrl -- AHB/APB bridge
generic map (hindex => 1, haddr => CFG_APBADDR)
port map (rstn, clkm, ahbsi, ahbso(1), apbi, apbo);
ua1 : if CFG_UART1_ENABLE /= 0 generate
uart1 : apbuart -- UART 1
generic map (pindex => 1, paddr => 1, pirq => 2, console => dbguart,
fifosize => CFG_UART1_FIFO)
port map (rstn, clkm, apbi, apbo(1), u1i, u1o);
u1i.ctsn <= '0'; u1i.extclk <= '0';
upads : if CFG_AHB_UART = 0 generate
u1i.rxd <= rxd1; txd1 <= u1o.txd;
end generate;
end generate;
noua0 : if CFG_UART1_ENABLE = 0 generate apbo(1) <= apb_none; end generate;
irqctrl : if CFG_IRQ3_ENABLE /= 0 generate
irqctrl0 : irqmp -- interrupt controller
generic map (pindex => 2, paddr => 2, ncpu => NCPU)
port map (rstn, clkm, apbi, apbo(2), irqo, irqi);
end generate;
irq3 : if CFG_IRQ3_ENABLE = 0 generate
x : for i in 0 to NCPU-1 generate
irqi(i).irl <= "0000";
end generate;
apbo(2) <= apb_none;
end generate;
gpt : if CFG_GPT_ENABLE /= 0 generate
timer0 : gptimer -- timer unit
generic map (pindex => 3, paddr => 3, pirq => CFG_GPT_IRQ,
sepirq => CFG_GPT_SEPIRQ, sbits => CFG_GPT_SW, ntimers => CFG_GPT_NTIM,
nbits => CFG_GPT_TW)
port map (rstn, clkm, apbi, apbo(3), gpti, open);
gpti <= gpti_dhalt_drive(dsuo.tstop);
end generate;
notim : if CFG_GPT_ENABLE = 0 generate apbo(3) <= apb_none; end generate;
gpio0 : if CFG_GRGPIO_ENABLE /= 0 generate -- GPIO unit
grgpio0: grgpio
generic map(pindex => 5, paddr => 5, imask => CFG_GRGPIO_IMASK, nbits => CFG_GRGPIO_WIDTH)
port map(rst => rstn, clk => clkm, apbi => apbi, apbo => apbo(5),
gpioi => gpioi, gpioo => gpioo);
pio_pads : for i in 0 to CFG_GRGPIO_WIDTH-1 generate
pio_pad : iopad generic map (tech => padtech)
port map (gpio(i), gpioo.dout(i), gpioo.oen(i), gpioi.din(i));
end generate;
end generate;
-----------------------------------------------------------------------
--- AHB ROM ----------------------------------------------------------
-----------------------------------------------------------------------
bpromgen : if CFG_AHBROMEN /= 0 generate
brom : entity work.ahbrom
generic map (hindex => 6, haddr => CFG_AHBRODDR, pipe => CFG_AHBROPIP)
port map ( rstn, clkm, ahbsi, ahbso(6));
end generate;
nobpromgen : if CFG_AHBROMEN = 0 generate
ahbso(6) <= ahbs_none;
end generate;
-----------------------------------------------------------------------
--- AHB RAM ----------------------------------------------------------
-----------------------------------------------------------------------
ahbramgen : if CFG_AHBRAMEN = 1 generate
ahbram0 : ahbram generic map (hindex => 7, haddr => CFG_AHBRADDR,
tech => CFG_MEMTECH, kbytes => CFG_AHBRSZ, pipe => CFG_AHBRPIPE)
port map (rstn, clkm, ahbsi, ahbso(7));
end generate;
nram : if CFG_AHBRAMEN = 0 generate ahbso(7) <= ahbs_none; end generate;
-----------------------------------------------------------------------
--- Drive unused bus elements ---------------------------------------
-----------------------------------------------------------------------
nam1 : for i in (NCPU+CFG_AHB_UART+CFG_AHB_JTAG) to NAHBMST-1 generate
ahbmo(i) <= ahbm_none;
end generate;
nap0 : for i in 6 to NAPBSLV-1 generate apbo(i) <= apb_none; end generate;
nah0 : for i in 8 to NAHBSLV-1 generate ahbso(i) <= ahbs_none; end generate;
-- invert signal for input via a key
dsubre <= not dsubren;
-- for smc lan chip
eth_lclk <= vcc(0);
eth_nads <= gnd(0);
eth_ncycle <= vcc(0);
eth_wnr <= vcc(0);
eth_nvlbus <= vcc(0);
eth_nrdyrtn <= vcc(0);
eth_ndatacs <= vcc(0);
-----------------------------------------------------------------------
--- Boot message ----------------------------------------------------
-----------------------------------------------------------------------
-- pragma translate_off
x : report_design
generic map (
msg1 => "LEON3 Altera EP2C60 SSRAM/DDR Demonstration design",
fabtech => tech_table(fabtech), memtech => tech_table(memtech),
mdel => 1
);
-- pragma translate_on
end;
| gpl-3.0 | a79e3efb3b540f5fb13d93b18b50cae2 | 0.546326 | 3.660181 | false | false | false | false |
richjyoung/lfsr-package | test/LFSR_TB/main_tb.vhd | 1 | 6,122 | library IEEE, JUNIT_TB, LFSR, LFSR_TB, STD;
use IEEE.std_logic_1164.all;
use JUNIT_TB.junit.all;
use LFSR.lfsr_components.all;
use LFSR.lfsr.all;
use LFSR_TB.lfsr_tb_components.all;
use LFSR_TB.main_tb_pkg.all;
use STD.textio.all;
--------------------------------------------------------------------------------
entity main_tb is
end main_tb;
--------------------------------------------------------------------------------
architecture tb of main_tb is
----------------------------------------------------------------------------
-- Test Definitions
----------------------------------------------------------------------------
constant TESTSUITE : T_TESTSUITE := (
0 => (
NAME => "3 bit max period ",
L_NAME => 16,
BITS => 3,
PERIOD => lfsr_maximum(3),
EXPECTED => 70 ns
),
1 => (
NAME => "3 bit period 2 ",
L_NAME => 14,
BITS => 3,
PERIOD => 2,
EXPECTED => 20 ns
),
2 => (
NAME => "3 bit max-1 period ",
L_NAME => 18,
BITS => 3,
PERIOD => lfsr_maximum(3)-1,
EXPECTED => 60 ns
),
3 => (
NAME => "4 bit max period ",
L_NAME => 16,
BITS => 4,
PERIOD => lfsr_maximum(4),
EXPECTED => 150 ns
),
4 => (
NAME => "4 bit period 2 ",
L_NAME => 14,
BITS => 4,
PERIOD => 2,
EXPECTED => 20 ns
),
5 => (
NAME => "4 bit max-1 period ",
L_NAME => 18,
BITS => 4,
PERIOD => lfsr_maximum(4)-1,
EXPECTED => 140 ns
)
);
constant C_PERIOD : time := 10 ns;
signal RESULTS : T_TESTRESULTS;
signal CLK : std_logic;
signal RESET : std_logic := '1';
signal FINISHED : std_logic;
signal GO : std_logic := '0';
begin
FINISHED <= done(RESULTS);
----------------------------------------------------------------------------
-- Test Process
----------------------------------------------------------------------------
stim_proc: process
file JFILE : text open write_mode is "main_tb_junit.xml";
variable JLINE : line;
variable V_STARTED : time;
variable V_FINISHED : time;
begin
------------------------------------------------------------------------
-- Initial Setup
------------------------------------------------------------------------
RESET <= '1';
GO <= '0';
wait until rising_edge(CLK);
wait until rising_edge(CLK);
wait until rising_edge(CLK);
wait until rising_edge(CLK);
wait until rising_edge(CLK);
RESET <= '0';
------------------------------------------------------------------------
-- Run Tests
------------------------------------------------------------------------
wait until rising_edge(CLK);
GO <= '1';
V_STARTED := now;
wait until FINISHED = '1';
V_FINISHED := now;
------------------------------------------------------------------------
-- Output Test Results
------------------------------------------------------------------------
junit_xml_declaration(JFILE);
junit_start_testsuites(JFILE, "main", "Main", C_TESTCASES,
failures(RESULTS), (V_FINISHED-V_STARTED));
junit_start_testsuite(JFILE, "main_tb", "Main TB", C_TESTCASES,
failures(RESULTS), (V_FINISHED-V_STARTED));
for I in TESTSUITE'range loop
junit_start_testcase(JFILE, integer'image(I),
TESTSUITE(I).NAME(1 to TESTSUITE(I).L_NAME),
RESULTS(I).RUNTIME);
if RESULTS(I).PASS_nFAIL = '0' then
junit_failure(JFILE, "period_error", time'image(RESULTS(I).RUNTIME));
end if;
junit_end_testcase(JFILE);
end loop;
junit_end_testsuite(JFILE);
junit_end_testsuites(JFILE);
------------------------------------------------------------------------
-- End Simulation
------------------------------------------------------------------------
wait for C_PERIOD * 10;
assert false report "SIMULATION FINISHED" severity failure;
wait;
end process stim_proc;
----------------------------------------------------------------------------
-- Instantiate testers for each test case
----------------------------------------------------------------------------
G_UUT: for I in 0 to C_TESTCASES-1 generate
U_UUT: pulse_tester
generic map (
G_lfsr_width => TESTSUITE(I).BITS,
G_period => TESTSUITE(I).PERIOD,
G_expected => TESTSUITE(I).EXPECTED
)
port map (
CLK => CLK,
RESET => RESET,
GO => GO,
DONE => RESULTS(I).DONE,
PASS_nFAIL => RESULTS(I).PASS_nFAIL,
RUNTIME => RESULTS(I).RUNTIME
);
end generate;
------------------------------------------------------------------------
-- Simulation Clock
------------------------------------------------------------------------
clk_proc: process
begin
CLK <= '0';
wait for C_PERIOD / 2;
CLK <= '1';
wait for C_PERIOD / 2;
end process clk_proc;
end tb; | mit | 7d428d26f058f582cc7c4ee516bab774 | 0.327997 | 5.219096 | false | true | false | false |
kdgwill/VHDL_Framer_Example | VHDL_Framer_Example/Example1/blockDiagram/ramController.vhd | 1 | 3,067 | ---------------------------------------------------------------------------------
--RamController---------------------------------------------------------------------
--By Kyle Williams, 04/07/2011--------------------------------------------------
--CLASS DESCRIPTION------------------------------------------------------------
-----3-After frame detect take every 8 bits and store them in a ram----------------
-----4-After 8 bytes have been written in the ram start reading the data from the ram
----------------Define Libraries to be used--------------------------------------
LIBRARY IEEE ;
USE IEEE.std_logic_1164.all ;
USE IEEE.std_logic_unsigned.all;
USE ieee.numeric_std.all;
-----------------ENTITY FOR RAM CONTROLLER------------------------------------------
ENTITY ramController is
GENERIC ( bits : INTEGER := 8;
words : INTEGER := 32); -- # of bits per word
PORT ( reset : IN STD_Logic;
clock : IN STD_LOGIC;
enable : IN STD_LOGIC;
ctrl_in : IN STD_LOGIC_VECTOR (bits - 1 DOWNTO 0);
addr : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
wr_ena : OUT STD_LOGIC; -- write enable
ctrl_out : OUT STD_LOGIC_VECTOR (bits -1 DOWNTO 0)
);
END ramController;
-----------------BEHAVIOR OF RAM CONTROLLER-----------------------------------------
ARCHITECTURE ramController of ramController IS
Signal temp_addr : INTEGER:=0;
--///CHECK FOR CHANGE IN IMPUT AND ADJUST ACCORDINGLY
--/SHOULD ALSO BE DOING WORK OF RETRIEVING
-------------------PROCEDUREE------------------------------
BEGIN
Process(clock,reset)
Variable S_wr_ena : STD_LOGIC:='0';
BEGIN
IF(reset='0') THEN
S_wr_ena:='0';
temp_addr <= 0;
ELSIF(rising_edge(clock) AND enable = '1') THEN
--you can't increment std_logic directly,
--you need to convert it to unsigned and the result
--back to std_logic_vector using the numeric_std package.
--temp_addr <= to_integer(unsigned(S_addr));
IF(S_wr_ena='1')THEN
--READ FROM RAM-------------------------------
--position pointer to end of list if location is 0 to locate the previous address
S_wr_ena:='0';
ELSE
--WRITE TO RAM--------------------------------
--RESET pointer if pointing to location greater than memory else increase address
IF(temp_addr <= words-2)THEN--for some reason compare with 32 instead of 31 look into this
temp_addr <= temp_addr+1;
ELSE
temp_addr <= 0;
END IF;
S_wr_ena:='1';
END IF;
END IF;
wr_ena<=S_wr_ena;
END PROCESS;
ADDR_CHECK:PROCESS(clock, reset)
Variable S_addr : STD_LOGIC_VECTOR(5 DOWNTO 0):="000000";--local variable
BEGIN
IF (reset = '0')THEN
addr <= (others => '0');
s_addr := (others => '0');
ELSIF rising_edge (clock)THEN
s_addr:=std_logic_vector(to_unsigned(temp_addr,6) );
END IF;
addr<=s_addr;
ctrl_out<=ctrl_in;
END PROCESS;
END ramController; | gpl-3.0 | 28d4972ee2f7b3f54754eda99a5c0102 | 0.499511 | 4.301543 | false | false | false | false |
EliasLuiz/TCC | Leon3/lib/techmap/maps/nandtree.vhd | 1 | 2,469 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: nandtree
-- File: nandtree.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: Nand-tree with tech mapping
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
entity nandtree is
generic(
tech : integer := inferred;
width : integer := 2;
imp : integer := 0 );
port( i : in std_logic_vector(width-1 downto 0);
o : out std_ulogic;
en : in std_ulogic
);
end entity;
architecture rtl of nandtree is
component rh_lib18t_nand_tree
generic (npins : integer := 2);
port(
-- Input Signlas: --
TEST_MODE : in std_logic;
IN_PINS_BUS : in std_logic_vector(npins-1 downto 0);
NAND_TREE_OUT : out std_logic
);
end component;
function fnandtree(v : std_logic_vector) return std_ulogic is
variable a : std_logic_vector(v'length-1 downto 0);
variable b : std_logic_vector(v'length downto 0);
begin
a := v; b(0) := '1';
for i in 0 to v'length-1 loop
b(i+1) := a(i) nand b(i);
end loop;
return b(v'length);
end;
begin
behav : if tech /= rhlib18t generate
o <= fnandtree(i);
end generate;
rhlib : if tech = rhlib18t generate
rhnand : rh_lib18t_nand_tree generic map (width)
port map (en, i, o);
end generate;
end;
| gpl-3.0 | 9cfb5e4300c23d9cae24193be657d6cd | 0.599838 | 3.746586 | false | false | false | false |
EliasLuiz/TCC | Leon3/designs/leon3-ztex-ufm-115/ahb2mig_ztex.vhd | 1 | 15,846 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-------------------------------------------------------------------------------
-- Entity: ahb2mig_ztex
-- File: ahb2mig_ztex.vhd
-- Author: Jiri Gaisler - Aeroflex Gaisler AB
--
-- This is a AHB-2.0 interface for the Xilinx Spartan-6 MIG.
-- One bidir 32-bit port is used for the main AHB bus.
-------------------------------------------------------------------------------
-- Patched for ZTEX: Oleg Belousov <[email protected]>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
entity ahb2mig_ztex is
generic(
hindex : integer := 0;
haddr : integer := 0;
hmask : integer := 16#f00#;
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#fff#;
MEMCLK_PERIOD : integer := 5000
);
port(
mcb3_dram_dq : inout std_logic_vector(15 downto 0);
mcb3_dram_udqs : inout std_logic;
mcb3_dram_udqs_n : inout std_logic;
mcb3_dram_dqs : inout std_logic;
mcb3_dram_dqs_n : inout std_logic;
mcb3_dram_a : out std_logic_vector(12 downto 0);
mcb3_dram_ba : out std_logic_vector(2 downto 0);
mcb3_dram_cke : out std_logic;
mcb3_dram_ras_n : out std_logic;
mcb3_dram_cas_n : out std_logic;
mcb3_dram_we_n : out std_logic;
mcb3_dram_dm : out std_logic;
mcb3_dram_udm : out std_logic;
mcb3_dram_ck : out std_logic;
mcb3_dram_ck_n : out std_logic;
mcb3_rzq : inout std_logic;
mcb3_zio : inout std_logic;
ahbso : out ahb_slv_out_type;
ahbsi : in ahb_slv_in_type;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
calib_done : out std_logic;
test_error : out std_logic;
rst_n_syn : in std_logic;
rst_n_async : in std_logic;
clk_amba : in std_logic;
clk_mem : in std_logic
);
end ;
architecture rtl of ahb2mig_ztex is
component mig_37
generic(
C3_P0_MASK_SIZE : integer := 4;
C3_P0_DATA_PORT_SIZE : integer := 32;
C3_P1_MASK_SIZE : integer := 4;
C3_P1_DATA_PORT_SIZE : integer := 32;
C3_MEMCLK_PERIOD : integer := 5000;
C3_RST_ACT_LOW : integer := 0;
C3_INPUT_CLK_TYPE : string := "SINGLE_ENDED";
C3_CALIB_SOFT_IP : string := "TRUE";
C3_SIMULATION : string := "FALSE";
DEBUG_EN : integer := 0;
C3_MEM_ADDR_ORDER : string := "ROW_BANK_COLUMN";
C3_NUM_DQ_PINS : integer := 16;
C3_MEM_ADDR_WIDTH : integer := 13;
C3_MEM_BANKADDR_WIDTH : integer := 3
);
port (
mcb3_dram_dq : inout std_logic_vector(C3_NUM_DQ_PINS-1 downto 0);
mcb3_dram_a : out std_logic_vector(C3_MEM_ADDR_WIDTH-1 downto 0);
mcb3_dram_ba : out std_logic_vector(C3_MEM_BANKADDR_WIDTH-1 downto 0);
mcb3_dram_cke : out std_logic;
mcb3_dram_ras_n : out std_logic;
mcb3_dram_cas_n : out std_logic;
mcb3_dram_we_n : out std_logic;
mcb3_dram_dm : out std_logic;
mcb3_dram_udqs : inout std_logic;
mcb3_dram_udqs_n : inout std_logic;
mcb3_rzq : inout std_logic;
mcb3_zio : inout std_logic;
mcb3_dram_udm : out std_logic;
c3_sys_clk : in std_logic;
c3_sys_rst_n : in std_logic;
c3_calib_done : out std_logic;
c3_clk0 : out std_logic;
c3_rst0 : out std_logic;
mcb3_dram_dqs : inout std_logic;
mcb3_dram_dqs_n : inout std_logic;
mcb3_dram_ck : out std_logic;
mcb3_dram_ck_n : out std_logic;
c3_p0_cmd_clk : in std_logic;
c3_p0_cmd_en : in std_logic;
c3_p0_cmd_instr : in std_logic_vector(2 downto 0);
c3_p0_cmd_bl : in std_logic_vector(5 downto 0);
c3_p0_cmd_byte_addr : in std_logic_vector(29 downto 0);
c3_p0_cmd_empty : out std_logic;
c3_p0_cmd_full : out std_logic;
c3_p0_wr_clk : in std_logic;
c3_p0_wr_en : in std_logic;
c3_p0_wr_mask : in std_logic_vector(C3_P0_MASK_SIZE - 1 downto 0);
c3_p0_wr_data : in std_logic_vector(C3_P0_DATA_PORT_SIZE - 1 downto 0);
c3_p0_wr_full : out std_logic;
c3_p0_wr_empty : out std_logic;
c3_p0_wr_count : out std_logic_vector(6 downto 0);
c3_p0_wr_underrun : out std_logic;
c3_p0_wr_error : out std_logic;
c3_p0_rd_clk : in std_logic;
c3_p0_rd_en : in std_logic;
c3_p0_rd_data : out std_logic_vector(C3_P0_DATA_PORT_SIZE - 1 downto 0);
c3_p0_rd_full : out std_logic;
c3_p0_rd_empty : out std_logic;
c3_p0_rd_count : out std_logic_vector(6 downto 0);
c3_p0_rd_overflow : out std_logic;
c3_p0_rd_error : out std_logic
);
end component;
type bstate_type is (idle, start, read1);
constant hconfig : ahb_config_type := (
0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_MIGDDR2, 0, 0, 0),
4 => ahb_membar(haddr, '1', '1', hmask),
-- 5 => ahb_iobar(ioaddr, iomask),
others => zero32);
constant pconfig : apb_config_type := (
0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_MIGDDR2, 0, 0, 0),
1 => apb_iobar(paddr, pmask));
type reg_type is record
bstate : bstate_type;
cmd_bl : std_logic_vector(5 downto 0);
wr_count : std_logic_vector(6 downto 0);
rd_cnt : std_logic_vector(5 downto 0);
hready : std_logic;
hsel : std_logic;
hwrite : std_logic;
htrans : std_logic_vector(1 downto 0);
hburst : std_logic_vector(2 downto 0);
hsize : std_logic_vector(2 downto 0);
hrdata : std_logic_vector(31 downto 0);
haddr : std_logic_vector(31 downto 0);
hmaster : std_logic_vector(3 downto 0);
end record;
type mcb_type is record
cmd_en : std_logic;
cmd_instr : std_logic_vector(2 downto 0);
cmd_empty : std_logic;
cmd_full : std_logic;
cmd_bl : std_logic_vector(5 downto 0);
cmd_byte_addr : std_logic_vector(29 downto 0);
wr_full : std_logic;
wr_empty : std_logic;
wr_underrun : std_logic;
wr_error : std_logic;
wr_mask : std_logic_vector(3 downto 0);
wr_en : std_logic;
wr_data : std_logic_vector(31 downto 0);
wr_count : std_logic_vector(6 downto 0);
rd_data : std_logic_vector(31 downto 0);
rd_full : std_logic;
rd_empty : std_logic;
rd_count : std_logic_vector(6 downto 0);
rd_overflow : std_logic;
rd_error : std_logic;
rd_en : std_logic;
end record;
signal r, rin : reg_type;
signal i : mcb_type;
begin
comb: process( rst_n_syn, r, ahbsi, i )
variable v : reg_type;
variable wmask : std_logic_vector(3 downto 0);
variable wr_en : std_logic;
variable cmd_en : std_logic;
variable cmd_instr : std_logic_vector(2 downto 0);
variable rd_en : std_logic;
variable cmd_bl : std_logic_vector(5 downto 0);
variable hwdata : std_logic_vector(31 downto 0);
variable readdata : std_logic_vector(31 downto 0);
begin
v := r; wr_en := '0'; cmd_en := '0'; cmd_instr := "000";
rd_en := '0';
if (ahbsi.hready = '1') then
if (ahbsi.hsel(hindex) and ahbsi.htrans(1)) = '1' then
v.hsel := '1'; v.hburst := ahbsi.hburst;
v.hwrite := ahbsi.hwrite; v.hsize := ahbsi.hsize;
v.hmaster := ahbsi.hmaster;
v.hready := '0';
if ahbsi.htrans(0) = '0' then v.haddr := ahbsi.haddr; end if;
else
v.hsel := '0'; v.hready := '1';
end if;
v.htrans := ahbsi.htrans;
end if;
hwdata := ahbsi.hwdata(15 downto 0) & ahbsi.hwdata(31 downto 16);
case r.hsize(1 downto 0) is
when "00" => wmask := not decode(r.haddr(1 downto 0));
case r.haddr(1 downto 0) is
when "00" => wmask := "1101";
when "01" => wmask := "1110";
when "10" => wmask := "0111";
when others => wmask := "1011";
end case;
when "01" => wmask := not decode(r.haddr(1 downto 0));
wmask(3) := wmask(2); wmask(1) := wmask(0);
when others => wmask := "0000";
end case;
i.wr_mask <= wmask;
cmd_bl := r.cmd_bl;
case r.bstate is
when idle =>
if v.hsel = '1' then
v.bstate := start;
v.hready := ahbsi.hwrite and not i.cmd_full and not i.wr_full;
v.haddr := ahbsi.haddr;
end if;
v.cmd_bl := (others => '0');
when start =>
if r.hwrite = '1' then
v.haddr := r.haddr;
if r.hready = '1' then
v.cmd_bl := r.cmd_bl + 1; v.hready := '1'; wr_en := '1';
if (ahbsi.htrans /= "11") then
if v.hsel = '1' then
if (ahbsi.hwrite = '0') or (i.wr_count >= "0000100") then
v.hready := '0';
else v.hready := '1'; end if;
else v.bstate := idle; end if;
v.cmd_bl := (others => '0'); v.haddr := ahbsi.haddr;
cmd_en := '1';
elsif (i.cmd_full = '1') then
v.hready := '0';
elsif (i.wr_count >= "0101111") then
v.hready := '0'; cmd_en := '1';
v.cmd_bl := (others => '0'); v.haddr := ahbsi.haddr;
end if;
else
if (i.cmd_full = '0') and (i.wr_count <= "0001111") then
v.hready := '1';
end if;
end if;
else
if i.cmd_full = '0' then
cmd_en := '1'; cmd_instr(0) := '1';
v.cmd_bl := "000" & not r.haddr(4 downto 2);
cmd_bl := v.cmd_bl;
v.bstate := read1;
end if;
end if;
when read1 =>
v.hready := '0';
if (r.rd_cnt = "000000") then -- flush data from previous line
if (i.rd_empty = '0') or ((r.hready = '1') and (ahbsi.htrans /= "11")) then
v.hrdata(31 downto 0) := i.rd_data(15 downto 0) & i.rd_data(31 downto 16);
v.hready := '1';
if (i.rd_empty = '0') then v.cmd_bl := r.cmd_bl - 1; rd_en := '1'; end if;
if (r.cmd_bl = "000000") or (ahbsi.htrans /= "11") then
if (ahbsi.hsel(hindex) = '1') and (ahbsi.htrans = "10") and (r.hready = '1') then
v.bstate := start; v.hready := ahbsi.hwrite and not i.cmd_full and not i.wr_full;
v.cmd_bl := (others => '0');
else
v.bstate := idle;
end if;
if (i.rd_empty = '1') then v.rd_cnt := r.cmd_bl + 1;
else v.rd_cnt := r.cmd_bl; end if;
end if;
end if;
end if;
when others =>
end case;
readdata := (others => '0');
-- case apbi.paddr(5 downto 2) is
-- when "0000" => readdata(nbits-1 downto 0) := r.din2;
-- when "0001" => readdata(nbits-1 downto 0) := r.dout;
-- when others =>
-- end case;
readdata(20 downto 0) :=
i.rd_error & i.rd_overflow & i.wr_error & i.wr_underrun &
i.cmd_full & i.rd_full & i.rd_empty & i.wr_full & i.wr_empty &
r.rd_cnt & r.cmd_bl;
if (r.rd_cnt /= "000000") and (i.rd_empty = '0') then
rd_en := '1'; v.rd_cnt := r.rd_cnt - 1;
end if;
if rst_n_syn = '0' then
v.rd_cnt := "000000"; v.bstate := idle; v.hready := '1';
end if;
rin <= v;
apbo.prdata <= readdata;
i.rd_en <= rd_en;
i.wr_en <= wr_en;
i.cmd_bl <= cmd_bl;
i.cmd_en <= cmd_en;
i.cmd_instr <= cmd_instr;
i.wr_data <= hwdata;
end process;
i.cmd_byte_addr <= r.haddr(29 downto 2) & "00";
ahbso.hready <= r.hready;
ahbso.hresp <= "00"; --r.hresp;
ahbso.hrdata <= r.hrdata;
ahbso.hconfig <= hconfig;
ahbso.hirq <= (others => '0');
ahbso.hindex <= hindex;
ahbso.hsplit <= (others => '0');
apbo.pirq <= (others => '0');
apbo.pindex <= pindex;
apbo.pconfig <= pconfig;
regs : process(clk_amba)
begin
if rising_edge(clk_amba) then
r <= rin;
end if;
end process;
MCB_inst : entity work.mig_37 generic map(
C3_RST_ACT_LOW => 1,
-- pragma translate_off
C3_SIMULATION => "TRUE",
-- pragma translate_on
C3_MEM_ADDR_ORDER => "BANK_ROW_COLUMN",
C3_MEMCLK_PERIOD => MEMCLK_PERIOD
)
port map (
mcb3_dram_dq => mcb3_dram_dq,
mcb3_rzq => mcb3_rzq,
mcb3_zio => mcb3_zio,
mcb3_dram_udqs => mcb3_dram_udqs,
mcb3_dram_udqs_n => mcb3_dram_udqs_n,
mcb3_dram_dqs => mcb3_dram_dqs,
mcb3_dram_dqs_n => mcb3_dram_dqs_n,
mcb3_dram_a => mcb3_dram_a,
mcb3_dram_ba => mcb3_dram_ba,
mcb3_dram_cke => mcb3_dram_cke,
mcb3_dram_ras_n => mcb3_dram_ras_n,
mcb3_dram_cas_n => mcb3_dram_cas_n,
mcb3_dram_we_n => mcb3_dram_we_n,
mcb3_dram_dm => mcb3_dram_dm,
mcb3_dram_udm => mcb3_dram_udm,
mcb3_dram_ck => mcb3_dram_ck,
mcb3_dram_ck_n => mcb3_dram_ck_n,
c3_sys_clk => clk_mem,
c3_sys_rst_n => rst_n_async,
c3_calib_done => calib_done,
c3_clk0 => open,
c3_rst0 => open,
c3_p0_cmd_clk => clk_amba,
c3_p0_cmd_en => i.cmd_en,
c3_p0_cmd_instr => i.cmd_instr,
c3_p0_cmd_bl => i.cmd_bl,
c3_p0_cmd_byte_addr => i.cmd_byte_addr,
c3_p0_cmd_empty => i.cmd_empty,
c3_p0_cmd_full => i.cmd_full,
c3_p0_wr_clk => clk_amba,
c3_p0_wr_en => i.wr_en,
c3_p0_wr_mask => i.wr_mask,
c3_p0_wr_data => i.wr_data,
c3_p0_wr_full => i.wr_full,
c3_p0_wr_empty => i.wr_empty,
c3_p0_wr_count => i.wr_count,
c3_p0_wr_underrun => i.wr_underrun,
c3_p0_wr_error => i.wr_error,
c3_p0_rd_clk => clk_amba,
c3_p0_rd_en => i.rd_en,
c3_p0_rd_data => i.rd_data,
c3_p0_rd_full => i.rd_full,
c3_p0_rd_empty => i.rd_empty,
c3_p0_rd_count => i.rd_count,
c3_p0_rd_overflow => i.rd_overflow,
c3_p0_rd_error => i.rd_error
);
end;
| gpl-3.0 | 197ce2631c28fd2e269c81716b45d2e2 | 0.506752 | 3.053179 | false | false | false | false |
EliasLuiz/TCC | Leon3/lib/gaisler/greth/adapters/sgmii.vhd | 1 | 7,987 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: sgmii
-- File: sgmii.vhd
-- Author: Andrea Gianarro - Aeroflex Gaisler AB
-- Description: SGMII to GMII Ethernet bridge
-- Provide a valid MDC clock input for proper functioning
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library gaisler;
use gaisler.net.all;
use gaisler.misc.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
library techmap;
use techmap.gencomp.all;
library opencores;
use opencores.ge_1000baseX_comp.all;
entity sgmii is
generic (
fabtech : integer := 0;
memtech : integer := 0;
transtech : integer := 0;
phy_addr : integer := 0;
mode : integer := 0 -- unused
);
port (
clk_125 : in std_logic;
rst_125 : in std_logic;
ser_rx_p : in std_logic;
ser_rx_n : in std_logic;
ser_tx_p : out std_logic;
ser_tx_n : out std_logic;
txd : in std_logic_vector(7 downto 0);
tx_en : in std_logic;
tx_er : in std_logic;
tx_clk : out std_logic;
tx_rstn : out std_logic;
rxd : out std_logic_vector(7 downto 0);
rx_dv : out std_logic;
rx_er : out std_logic;
rx_col : out std_logic;
rx_crs : out std_logic;
rx_clk : out std_logic;
rx_rstn : out std_logic;
-- optional MDIO interface to PCS
mdc : in std_logic; -- must be provided
mdio_o : in std_logic := '0';
mdio_oe : in std_logic := '1';
mdio_i : out std_logic;
-- added for igloo2_serdes
apbin : in apb_in_serdes := apb_in_serdes_none;
apbout : out apb_out_serdes;
m2gl_padin : in pad_in_serdes := pad_in_serdes_none;
m2gl_padout : out pad_out_serdes;
serdes_clk125 : out std_logic;
rx_aligned : out std_logic
) ;
end entity ;
architecture rtl of sgmii is
signal tx_in_int_reversed, rx_out_int_reversed, tx_in_int, rx_out_int, rx_out_pll_int : std_logic_vector(9 downto 0);
signal rx_clk_int, rx_pll_clk_int, tx_pll_clk_int, rx_rstn_int, rx_rst_int, rx_pll_rstn_int, rx_pll_rst_int, tx_pll_rst_int, tx_pll_rstn_int, startup_enable_int : std_logic;
signal mdio_int, bitslip_int : std_logic;
signal rx_int_clk : std_logic_vector(0 downto 0) ;
signal debug_int : std_logic_vector(31 downto 0) ;
signal ready_sig : std_logic;
signal mdc_rst, mdc_rstn : std_logic;
begin
rx_rst_int <= not rx_rstn_int;
rx_pll_rst_int <= not rx_pll_rstn_int;
tx_pll_rst_int <= not tx_pll_rstn_int;
pma0: serdes
generic map (
fabtech => fabtech,
transtech => transtech
)
port map (
clk_125 => clk_125,
rst_125 => rst_125,
rx_in_p => ser_rx_p,
rx_in_n => ser_rx_n,
rx_out => rx_out_int,
rx_clk => rx_clk_int,
rx_rstn => rx_rstn_int,
rx_pll_clk => rx_pll_clk_int,
rx_pll_rstn => rx_pll_rstn_int,
tx_pll_clk => tx_pll_clk_int,
tx_pll_rstn => tx_pll_rstn_int,
tx_in => tx_in_int,
tx_out_p => ser_tx_p,
tx_out_n => ser_tx_n,
bitslip => bitslip_int,
apbin => apbin,
apbout => apbout,
m2gl_padin => m2gl_padin,
m2gl_padout => m2gl_padout,
serdes_clk125 => serdes_clk125,
serdes_ready => ready_sig
);
str0: if (fabtech = stratix3) or (fabtech = stratix4) or (is_unisim(fabtech) = 1) generate
-- COMMA DETECTOR WITH BITSLIP LOGIC
cd0: comma_detect
generic map (
bsbreak => 16,
bswait => 63
)
port map (
clk => rx_clk_int,
rstn => rx_rstn_int,
indata => rx_out_int,
bitslip => bitslip_int
);
-- ELASTIC BUFFER WITH INTERNAL FIFO
eb0: elastic_buffer
generic map (
tech => memtech,
abits => 7
)
port map (
wr_clk => rx_clk_int,
wr_rst => rx_rst_int,
wr_data => rx_out_int,
rd_clk => rx_pll_clk_int,
rd_rst => rx_pll_rst_int,
rd_data => rx_out_pll_int
);
pcs0 : ge_1000baseX
generic map (
PHY_ADDR => phy_addr,
BASEX_AN_MODE => mode
)
port map(
rx_ck => rx_pll_clk_int,
tx_ck => tx_pll_clk_int,
rx_reset => rx_pll_rst_int,
tx_reset => tx_pll_rst_int,
startup_enable => startup_enable_int,
tbi_rxd => rx_out_pll_int, -- abcdefghij
tbi_txd => tx_in_int, -- abcdefghij
gmii_rxd => rxd,
gmii_rx_dv => rx_dv,
gmii_rx_er => rx_er,
gmii_col => rx_col,
gmii_cs => rx_crs,
gmii_txd => txd,
gmii_tx_en => tx_en,
gmii_tx_er => tx_er,
repeater_mode => '0',
mdc_reset => rst_125,
mdio_i => mdio_int,
mdio_o => mdio_i,
mdc => mdc,
debug => debug_int
);
end generate;
igl2 : if (fabtech = igloo2) or (fabtech = rtg4) generate
-- comma detector and word aligner
wa0: word_aligner
port map (
clk => rx_clk_int,
rstn => rx_rstn_int,
rx_in => rx_out_int,
rx_out => rx_out_pll_int);
rst0 : rstgen -- reset synchronizer for MDC clock domain in ge_1000baseX
generic map (syncrst => 1, acthigh => 1)
port map (rx_pll_rst_int, mdc, '1', mdc_rstn, open);
mdc_rst <= not(mdc_rstn);
pcs0 : ge_1000baseX
generic map (
PHY_ADDR => phy_addr,
BASEX_AN_MODE => mode
)
port map(
rx_ck => rx_pll_clk_int,
tx_ck => tx_pll_clk_int,
rx_reset => rx_pll_rst_int,
tx_reset => tx_pll_rst_int,
startup_enable => startup_enable_int,
tbi_rxd => rx_out_pll_int, -- abcdefghij
tbi_txd => tx_in_int, -- abcdefghij
gmii_rxd => rxd,
gmii_rx_dv => rx_dv,
gmii_rx_er => rx_er,
gmii_col => rx_col,
gmii_cs => rx_crs,
gmii_txd => txd,
gmii_tx_en => tx_en,
gmii_tx_er => tx_er,
repeater_mode => '0',
mdc_reset => mdc_rst,
mdio_i => mdio_int,
mdio_o => mdio_i,
mdc => mdc,
debug => debug_int
);
end generate;
mdio_int <= mdio_o when mdio_oe = '0' else
'0';
startup_enable_int <= (not rst_125) and ready_sig;
rx_clk <= rx_pll_clk_int; --rx_clk_int;
rx_rstn <= rx_pll_rstn_int;
tx_clk <= tx_pll_clk_int; --clk_125;
tx_rstn <= tx_pll_rstn_int;
rx_aligned <= ready_sig;
end architecture ; -- rtl
| gpl-3.0 | 5e840d2b683003c2cbf660c343014b11 | 0.517591 | 3.322379 | false | false | false | false |
EliasLuiz/TCC | Leon3/lib/grlib/amba/devices.vhd | 1 | 46,526 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: devices
-- File: devices.vhd
-- Author: Cobham Gaisler AB
-- Description: Vendor and devices IDs for AMBA plug&play
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
-- pragma translate_off
use std.textio.all;
-- pragma translate_on
package devices is
-- Vendor codes
constant VENDOR_RESERVED : amba_vendor_type := 16#00#; -- Do not use!
constant VENDOR_GAISLER : amba_vendor_type := 16#01#;
constant VENDOR_PENDER : amba_vendor_type := 16#02#;
constant VENDOR_ESA : amba_vendor_type := 16#04#;
constant VENDOR_ASTRIUM : amba_vendor_type := 16#06#;
constant VENDOR_OPENCHIP : amba_vendor_type := 16#07#;
constant VENDOR_OPENCORES : amba_vendor_type := 16#08#;
constant VENDOR_CONTRIB : amba_vendor_type := 16#09#;
constant VENDOR_DLR : amba_vendor_type := 16#0A#;
constant VENDOR_EONIC : amba_vendor_type := 16#0B#;
constant VENDOR_TELECOMPT : amba_vendor_type := 16#0C#;
constant VENDOR_DTU : amba_vendor_type := 16#0D#;
constant VENDOR_BSC : amba_vendor_type := 16#0E#;
constant VENDOR_RADIONOR : amba_vendor_type := 16#0F#;
constant VENDOR_GLEICHMANN : amba_vendor_type := 16#10#;
constant VENDOR_MENTA : amba_vendor_type := 16#11#;
constant VENDOR_SUN : amba_vendor_type := 16#13#;
constant VENDOR_MOVIDIA : amba_vendor_type := 16#14#;
constant VENDOR_ORBITA : amba_vendor_type := 16#17#;
constant VENDOR_SYNOPSYS : amba_vendor_type := 16#21#;
constant VENDOR_NASA : amba_vendor_type := 16#22#;
constant VENDOR_S3 : amba_vendor_type := 16#31#;
constant VENDOR_ACTEL : amba_vendor_type := 16#AC#;
constant VENDOR_APPLECORE : amba_vendor_type := 16#AE#;
constant VENDOR_C3E : amba_vendor_type := 16#C3#;
constant VENDOR_CBKPAN : amba_vendor_type := 16#C8#;
constant VENDOR_CAL : amba_vendor_type := 16#CA#;
constant VENDOR_CETON : amba_vendor_type := 16#CB#;
constant VENDOR_EMBEDDIT : amba_vendor_type := 16#EA#;
constant VENDOR_NASA_GSFC : amba_vendor_type := 16#FC#;
-- Cobham Gaisler device ids
constant GAISLER_LEON2DSU : amba_device_type := 16#002#;
constant GAISLER_LEON3 : amba_device_type := 16#003#;
constant GAISLER_LEON3DSU : amba_device_type := 16#004#;
constant GAISLER_ETHAHB : amba_device_type := 16#005#;
constant GAISLER_APBMST : amba_device_type := 16#006#;
constant GAISLER_AHBUART : amba_device_type := 16#007#;
constant GAISLER_SRCTRL : amba_device_type := 16#008#;
constant GAISLER_SDCTRL : amba_device_type := 16#009#;
constant GAISLER_SSRCTRL : amba_device_type := 16#00A#;
constant GAISLER_I2C2AHB : amba_device_type := 16#00B#;
constant GAISLER_APBUART : amba_device_type := 16#00C#;
constant GAISLER_IRQMP : amba_device_type := 16#00D#;
constant GAISLER_AHBRAM : amba_device_type := 16#00E#;
constant GAISLER_AHBDPRAM : amba_device_type := 16#00F#;
constant GAISLER_GRIOMMU2 : amba_device_type := 16#010#;
constant GAISLER_GPTIMER : amba_device_type := 16#011#;
constant GAISLER_PCITRG : amba_device_type := 16#012#;
constant GAISLER_PCISBRG : amba_device_type := 16#013#;
constant GAISLER_PCIFBRG : amba_device_type := 16#014#;
constant GAISLER_PCITRACE : amba_device_type := 16#015#;
constant GAISLER_DMACTRL : amba_device_type := 16#016#;
constant GAISLER_AHBTRACE : amba_device_type := 16#017#;
constant GAISLER_DSUCTRL : amba_device_type := 16#018#;
constant GAISLER_CANAHB : amba_device_type := 16#019#;
constant GAISLER_GPIO : amba_device_type := 16#01A#;
constant GAISLER_AHBROM : amba_device_type := 16#01B#;
constant GAISLER_AHBJTAG : amba_device_type := 16#01C#;
constant GAISLER_ETHMAC : amba_device_type := 16#01D#;
constant GAISLER_SWNODE : amba_device_type := 16#01E#;
constant GAISLER_SPW : amba_device_type := 16#01F#;
constant GAISLER_AHB2AHB : amba_device_type := 16#020#;
constant GAISLER_USBDC : amba_device_type := 16#021#;
constant GAISLER_USB_DCL : amba_device_type := 16#022#;
constant GAISLER_DDRMP : amba_device_type := 16#023#;
constant GAISLER_ATACTRL : amba_device_type := 16#024#;
constant GAISLER_DDRSP : amba_device_type := 16#025#;
constant GAISLER_EHCI : amba_device_type := 16#026#;
constant GAISLER_UHCI : amba_device_type := 16#027#;
constant GAISLER_I2CMST : amba_device_type := 16#028#;
constant GAISLER_SPW2 : amba_device_type := 16#029#;
constant GAISLER_AHBDMA : amba_device_type := 16#02A#;
constant GAISLER_NUHOSP3 : amba_device_type := 16#02B#;
constant GAISLER_CLKGATE : amba_device_type := 16#02C#;
constant GAISLER_SPICTRL : amba_device_type := 16#02D#;
constant GAISLER_DDR2SP : amba_device_type := 16#02E#;
constant GAISLER_SLINK : amba_device_type := 16#02F#;
constant GAISLER_GRTM : amba_device_type := 16#030#;
constant GAISLER_GRTC : amba_device_type := 16#031#;
constant GAISLER_GRPW : amba_device_type := 16#032#;
constant GAISLER_GRCTM : amba_device_type := 16#033#;
constant GAISLER_GRHCAN : amba_device_type := 16#034#;
constant GAISLER_GRFIFO : amba_device_type := 16#035#;
constant GAISLER_GRADCDAC : amba_device_type := 16#036#;
constant GAISLER_GRPULSE : amba_device_type := 16#037#;
constant GAISLER_GRTIMER : amba_device_type := 16#038#;
constant GAISLER_AHB2PP : amba_device_type := 16#039#;
constant GAISLER_GRVERSION : amba_device_type := 16#03A#;
constant GAISLER_APB2PW : amba_device_type := 16#03B#;
constant GAISLER_PW2APB : amba_device_type := 16#03C#;
constant GAISLER_GRCAN : amba_device_type := 16#03D#;
constant GAISLER_I2CSLV : amba_device_type := 16#03E#;
constant GAISLER_U16550 : amba_device_type := 16#03F#;
constant GAISLER_AHBMST_EM : amba_device_type := 16#040#;
constant GAISLER_AHBSLV_EM : amba_device_type := 16#041#;
constant GAISLER_GRTESTMOD : amba_device_type := 16#042#;
constant GAISLER_ASCS : amba_device_type := 16#043#;
constant GAISLER_IPMVBCTRL : amba_device_type := 16#044#;
constant GAISLER_SPIMCTRL : amba_device_type := 16#045#;
constant GAISLER_L4STAT : amba_device_type := 16#047#;
constant GAISLER_LEON4 : amba_device_type := 16#048#;
constant GAISLER_LEON4DSU : amba_device_type := 16#049#;
constant GAISLER_PWM : amba_device_type := 16#04A#;
constant GAISLER_L2CACHE : amba_device_type := 16#04B#;
constant GAISLER_SDCTRL64 : amba_device_type := 16#04C#;
constant GAISLER_GR1553B : amba_device_type := 16#04D#;
constant GAISLER_1553TST : amba_device_type := 16#04E#;
constant GAISLER_GRIOMMU : amba_device_type := 16#04F#;
constant GAISLER_FTAHBRAM : amba_device_type := 16#050#;
constant GAISLER_FTSRCTRL : amba_device_type := 16#051#;
constant GAISLER_AHBSTAT : amba_device_type := 16#052#;
constant GAISLER_LEON3FT : amba_device_type := 16#053#;
constant GAISLER_FTMCTRL : amba_device_type := 16#054#;
constant GAISLER_FTSDCTRL : amba_device_type := 16#055#;
constant GAISLER_FTSRCTRL8 : amba_device_type := 16#056#;
constant GAISLER_MEMSCRUB : amba_device_type := 16#057#;
constant GAISLER_FTSDCTRL64: amba_device_type := 16#058#;
constant GAISLER_NANDFCTRL : amba_device_type := 16#059#;
constant GAISLER_N2DLLCTRL : amba_device_type := 16#05A#;
constant GAISLER_N2PLLCTRL : amba_device_type := 16#05B#;
constant GAISLER_SPI2AHB : amba_device_type := 16#05C#;
constant GAISLER_DDRSDMUX : amba_device_type := 16#05D#;
constant GAISLER_AHBFROM : amba_device_type := 16#05E#;
constant GAISLER_PCIEXP : amba_device_type := 16#05F#;
constant GAISLER_APBPS2 : amba_device_type := 16#060#;
constant GAISLER_VGACTRL : amba_device_type := 16#061#;
constant GAISLER_LOGAN : amba_device_type := 16#062#;
constant GAISLER_SVGACTRL : amba_device_type := 16#063#;
constant GAISLER_T1AHB : amba_device_type := 16#064#;
constant GAISLER_MP7WRAP : amba_device_type := 16#065#;
constant GAISLER_GRSYSMON : amba_device_type := 16#066#;
constant GAISLER_GRACECTRL : amba_device_type := 16#067#;
constant GAISLER_ATAHBSLV : amba_device_type := 16#068#;
constant GAISLER_ATAHBMST : amba_device_type := 16#069#;
constant GAISLER_ATAPBSLV : amba_device_type := 16#06A#;
constant GAISLER_MIGDDR2 : amba_device_type := 16#06B#;
constant GAISLER_LCDCTRL : amba_device_type := 16#06C#;
constant GAISLER_SWITCHOVER: amba_device_type := 16#06D#;
constant GAISLER_FIFOUART : amba_device_type := 16#06E#;
constant GAISLER_MUXCTRL : amba_device_type := 16#06F#;
constant GAISLER_B1553BC : amba_device_type := 16#070#;
constant GAISLER_B1553RT : amba_device_type := 16#071#;
constant GAISLER_B1553BRM : amba_device_type := 16#072#;
constant GAISLER_AES : amba_device_type := 16#073#;
constant GAISLER_ECC : amba_device_type := 16#074#;
constant GAISLER_PCIF : amba_device_type := 16#075#;
constant GAISLER_CLKMOD : amba_device_type := 16#076#;
constant GAISLER_HAPSTRAK : amba_device_type := 16#077#;
constant GAISLER_TEST_1X2 : amba_device_type := 16#078#;
constant GAISLER_WILD2AHB : amba_device_type := 16#079#;
constant GAISLER_BIO1 : amba_device_type := 16#07A#;
constant GAISLER_AESDMA : amba_device_type := 16#07B#;
constant GAISLER_GRPCI2 : amba_device_type := 16#07C#;
constant GAISLER_GRPCI2_DMA: amba_device_type := 16#07D#;
constant GAISLER_GRPCI2_TB : amba_device_type := 16#07E#;
constant GAISLER_MMA : amba_device_type := 16#07F#;
constant GAISLER_SATCAN : amba_device_type := 16#080#;
constant GAISLER_CANMUX : amba_device_type := 16#081#;
constant GAISLER_GRTMRX : amba_device_type := 16#082#;
constant GAISLER_GRTCTX : amba_device_type := 16#083#;
constant GAISLER_GRTMDESC : amba_device_type := 16#084#;
constant GAISLER_GRTMVC : amba_device_type := 16#085#;
constant GAISLER_GEFFE : amba_device_type := 16#086#;
constant GAISLER_GPREG : amba_device_type := 16#087#;
constant GAISLER_GRTMPAHB : amba_device_type := 16#088#;
constant GAISLER_SPWCUC : amba_device_type := 16#089#;
constant GAISLER_SPW2_DMA : amba_device_type := 16#08A#;
constant GAISLER_SPWROUTER : amba_device_type := 16#08B#;
constant GAISLER_EDCLMST : amba_device_type := 16#08C#;
constant GAISLER_GRPWTX : amba_device_type := 16#08D#;
constant GAISLER_GRPWRX : amba_device_type := 16#08E#;
constant GAISLER_GPREGBANK : amba_device_type := 16#08F#;
constant GAISLER_MIG_7SERIES : amba_device_type := 16#090#;
constant GAISLER_GRSPW2_SIST : amba_device_type := 16#091#;
constant GAISLER_SGMII : amba_device_type := 16#092#;
constant GAISLER_RGMII : amba_device_type := 16#093#;
constant GAISLER_IRQGEN : amba_device_type := 16#094#;
constant GAISLER_GRDMAC : amba_device_type := 16#095#;
constant GAISLER_AHB2AVLA : amba_device_type := 16#096#;
constant GAISLER_SPWTDP : amba_device_type := 16#097#;
constant GAISLER_L3STAT : amba_device_type := 16#098#;
constant GAISLER_GR740THS : amba_device_type := 16#099#;
constant GAISLER_GRRM : amba_device_type := 16#09A#;
constant GAISLER_CMAP : amba_device_type := 16#09B#;
constant GAISLER_CPGEN : amba_device_type := 16#09C#;
constant GAISLER_AMBAPROT : amba_device_type := 16#09D#;
constant GAISLER_IGLOO2_BRIDGE : amba_device_type := 16#09E#;
constant GAISLER_AHB2AXI : amba_device_type := 16#09F#;
constant GAISLER_AXI2AHB : amba_device_type := 16#0A0#;
constant GAISLER_FDIR_RSTCTRL : amba_device_type := 16#0A1#;
constant GAISLER_APB3MST : amba_device_type := 16#0A2#;
constant GAISLER_LRAM : amba_device_type := 16#0A3#;
constant GAISLER_BOOTSEQ : amba_device_type := 16#0A4#;
-- Sun Microsystems
constant SUN_T1 : amba_device_type := 16#001#;
constant SUN_S1 : amba_device_type := 16#011#;
-- Caltech
constant CAL_DDRCTRL : amba_device_type := 16#188#;
-- CBK PAN
constant CBKPAN_FTNANDCTRL : amba_device_type := 16#001#;
constant CBKPAN_FTEEPROMCTRL : amba_device_type := 16#002#;
constant CBKPAN_FTSDCTRL16 : amba_device_type := 16#003#;
constant CBKPAN_STIXCTRL : amba_device_type := 16#300#;
-- European Space Agency device ids
constant ESA_LEON2 : amba_device_type := 16#002#;
constant ESA_LEON2APB : amba_device_type := 16#003#;
constant ESA_IRQ : amba_device_type := 16#005#;
constant ESA_TIMER : amba_device_type := 16#006#;
constant ESA_UART : amba_device_type := 16#007#;
constant ESA_CFG : amba_device_type := 16#008#;
constant ESA_IO : amba_device_type := 16#009#;
constant ESA_MCTRL : amba_device_type := 16#00F#;
constant ESA_PCIARB : amba_device_type := 16#010#;
constant ESA_HURRICANE : amba_device_type := 16#011#;
constant ESA_SPW_RMAP : amba_device_type := 16#012#;
constant ESA_AHBUART : amba_device_type := 16#013#;
constant ESA_SPWA : amba_device_type := 16#014#;
constant ESA_BOSCHCAN : amba_device_type := 16#015#;
constant ESA_IRQ2 : amba_device_type := 16#016#;
constant ESA_AHBSTAT : amba_device_type := 16#017#;
constant ESA_WPROT : amba_device_type := 16#018#;
constant ESA_WPROT2 : amba_device_type := 16#019#;
constant ESA_PDEC3AMBA : amba_device_type := 16#020#;
constant ESA_PTME3AMBA : amba_device_type := 16#021#;
-- OpenChip IDs
constant OPENCHIP_APBGPIO : amba_device_type := 16#001#;
constant OPENCHIP_APBI2C : amba_device_type := 16#002#;
constant OPENCHIP_APBSPI : amba_device_type := 16#003#;
constant OPENCHIP_APBCHARLCD : amba_device_type := 16#004#;
constant OPENCHIP_APBPWM : amba_device_type := 16#005#;
constant OPENCHIP_APBPS2 : amba_device_type := 16#006#;
constant OPENCHIP_APBMMCSD : amba_device_type := 16#007#;
constant OPENCHIP_APBNAND : amba_device_type := 16#008#;
constant OPENCHIP_APBLPC : amba_device_type := 16#009#;
constant OPENCHIP_APBCF : amba_device_type := 16#00A#;
constant OPENCHIP_APBSYSACE : amba_device_type := 16#00B#;
constant OPENCHIP_APB1WIRE : amba_device_type := 16#00C#;
constant OPENCHIP_APBJTAG : amba_device_type := 16#00D#;
constant OPENCHIP_APBSUI : amba_device_type := 16#00E#;
-- Gleichmann's device ids
constant GLEICHMANN_CUSTOM : amba_device_type := 16#001#;
constant GLEICHMANN_GEOLCD01 : amba_device_type := 16#002#;
constant GLEICHMANN_DAC : amba_device_type := 16#003#;
constant GLEICHMANN_HPI : amba_device_type := 16#004#;
constant GLEICHMANN_SPI : amba_device_type := 16#005#;
constant GLEICHMANN_HIFC : amba_device_type := 16#006#;
constant GLEICHMANN_ADCDAC : amba_device_type := 16#007#;
constant GLEICHMANN_SPIOC : amba_device_type := 16#008#;
constant GLEICHMANN_AC97 : amba_device_type := 16#009#;
-- MENTA device ids
constant MENTA_EFPGA_IP : amba_device_type := 16#002#;
-- DTU device ids
constant DTU_IV : amba_device_type := 16#001#;
constant DTU_RBMMTRANS : amba_device_type := 16#002#;
constant DTU_FTMCTRL : amba_device_type := 16#054#;
-- BSC device ids
constant BSC_CORE1 : amba_device_type := 16#001#;
constant BSC_CORE2 : amba_device_type := 16#002#;
-- Orbita device ids
constant ORBITA_1553B : amba_device_type := 16#001#;
constant ORBITA_429 : amba_device_type := 16#002#;
constant ORBITA_SPI : amba_device_type := 16#003#;
constant ORBITA_I2C : amba_device_type := 16#004#;
constant ORBITA_SMARTCARD : amba_device_type := 16#064#;
constant ORBITA_SDCARD : amba_device_type := 16#065#;
constant ORBITA_UART16550 : amba_device_type := 16#066#;
constant ORBITA_CRYPTO : amba_device_type := 16#067#;
constant ORBITA_SYSIF : amba_device_type := 16#068#;
constant ORBITA_PIO : amba_device_type := 16#069#;
constant ORBITA_RTC : amba_device_type := 16#0C8#;
constant ORBITA_COLORLCD : amba_device_type := 16#12C#;
constant ORBITA_PCI : amba_device_type := 16#190#;
constant ORBITA_DSP : amba_device_type := 16#1F4#;
constant ORBITA_USBHOST : amba_device_type := 16#258#;
constant ORBITA_USBDEV : amba_device_type := 16#2BC#;
-- Actel device ids
constant ACTEL_COREMP7 : amba_device_type := 16#001#;
-- NASA device ids
constant NASA_EP32 : amba_device_type := 16#001#;
-- AppleCore device ids
constant APPLECORE_UTLEON3 : amba_device_type := 16#001#;
constant APPLECORE_UTLEON3DSU : amba_device_type := 16#002#;
constant APPLECORE_APBPERFCNT : amba_device_type := 16#003#;
-- Contribution library IDs
constant CONTRIB_CORE1 : amba_device_type := 16#001#;
constant CONTRIB_CORE2 : amba_device_type := 16#002#;
-- grlib system device ids
subtype system_device_type is integer range 0 to 16#ffff#;
constant LEON3_ACT_FUSION : system_device_type := 16#0105#;
constant LEON3_RTAX_CID1 : system_device_type := 16#0201#;
constant LEON3_RTAX_CID2 : system_device_type := 16#0202#;
constant LEON3_RTAX_CID3 : system_device_type := 16#0203#;
constant LEON3_RTAX_CID4 : system_device_type := 16#0204#;
constant LEON3_RTAX_CID5 : system_device_type := 16#0205#;
constant LEON3_RTAX_CID6 : system_device_type := 16#0206#;
constant LEON3_RTAX_CID7 : system_device_type := 16#0207#;
constant LEON3_RTAX_CID8 : system_device_type := 16#0208#;
constant LEON3_PROXIMA : system_device_type := 16#0252#;
constant ALTERA_DE2 : system_device_type := 16#0302#;
constant ALTERA_DE4 : system_device_type := 16#0303#;
constant XILINX_ML401 : system_device_type := 16#0401#;
constant LEON3FT_GRXC4V : system_device_type := 16#0453#;
constant XILINX_ML501 : system_device_type := 16#0501#;
constant XILINX_ML505 : system_device_type := 16#0505#;
constant XILINX_ML506 : system_device_type := 16#0506#;
constant XILINX_ML507 : system_device_type := 16#0507#;
constant XILINX_ML509 : system_device_type := 16#0509#;
constant XILINX_ML510 : system_device_type := 16#0510#;
constant MICROSEMI_M2GL_EVAL : system_device_type := 16#0560#;
constant XILINX_SP601 : system_device_type := 16#0601#;
constant XILINX_ML605 : system_device_type := 16#0605#;
constant XILINX_AC701 : system_device_type := 16#A701#;
constant XILINX_KC705 : system_device_type := 16#A705#;
constant XILINX_VC707 : system_device_type := 16#A707#;
constant ESA_SSDP : system_device_type := 16#ADA2#;
-- pragma translate_off
constant GAISLER_DESC : vendor_description := "Cobham Gaisler ";
constant gaisler_device_table : device_table_type := (
GAISLER_LEON2DSU => "LEON2 Debug Support Unit ",
GAISLER_LEON3 => "LEON3 SPARC V8 Processor ",
GAISLER_LEON3DSU => "LEON3 Debug Support Unit ",
GAISLER_ETHAHB => "OC ethernet AHB interface ",
GAISLER_AHBRAM => "Single-port AHB SRAM module ",
GAISLER_AHBDPRAM => "Dual-port AHB SRAM module ",
GAISLER_APBMST => "AHB/APB Bridge ",
GAISLER_AHBUART => "AHB Debug UART ",
GAISLER_SRCTRL => "Simple SRAM Controller ",
GAISLER_SDCTRL => "PC133 SDRAM Controller ",
GAISLER_SSRCTRL => "Synchronous SRAM Controller ",
GAISLER_APBUART => "Generic UART ",
GAISLER_IRQMP => "Multi-processor Interrupt Ctrl.",
GAISLER_GPTIMER => "Modular Timer Unit ",
GAISLER_PCITRG => "Simple 32-bit PCI Target ",
GAISLER_PCISBRG => "Simple 32-bit PCI Bridge ",
GAISLER_PCIFBRG => "Fast 32-bit PCI Bridge ",
GAISLER_PCITRACE => "32-bit PCI Trace Buffer ",
GAISLER_DMACTRL => "PCI/AHB DMA controller ",
GAISLER_AHBTRACE => "AMBA Trace Buffer ",
GAISLER_DSUCTRL => "DSU/ETH controller ",
GAISLER_GRTM => "CCSDS Telemetry Encoder ",
GAISLER_GRTC => "CCSDS Telecommand Decoder ",
GAISLER_GRPW => "PacketWire to AMBA AHB I/F ",
GAISLER_GRCTM => "CCSDS Time Manager ",
GAISLER_GRHCAN => "ESA HurriCANe CAN with DMA ",
GAISLER_GRFIFO => "FIFO Controller ",
GAISLER_GRADCDAC => "ADC / DAC Interface ",
GAISLER_GRPULSE => "General Purpose I/O with Pulses",
GAISLER_GRTIMER => "Timer Unit with Latches ",
GAISLER_AHB2PP => "AMBA AHB to Packet Parallel I/F",
GAISLER_GRVERSION => "Version and Revision Register ",
GAISLER_APB2PW => "PacketWire Transmit Interface ",
GAISLER_PW2APB => "PacketWire Receive Interface ",
GAISLER_GRCAN => "CAN Controller with DMA ",
GAISLER_AHBMST_EM => "AMBA Master Emulator ",
GAISLER_AHBSLV_EM => "AMBA Slave Emulator ",
GAISLER_CANAHB => "OC CAN AHB interface ",
GAISLER_GPIO => "General Purpose I/O port ",
GAISLER_AHBROM => "Generic AHB ROM ",
GAISLER_AHB2AHB => "AHB-to-AHB Bridge ",
GAISLER_AHBDMA => "Simple AHB DMA controller ",
GAISLER_NUHOSP3 => "Nuhorizons Spartan3 IO I/F ",
GAISLER_CLKGATE => "Clock gating unit ",
GAISLER_FTAHBRAM => "Generic FT AHB SRAM module ",
GAISLER_FTSRCTRL => "Simple FT SRAM Controller ",
GAISLER_LEON3FT => "LEON3-FT SPARC V8 Processor ",
GAISLER_FTMCTRL => "Memory controller with EDAC ",
GAISLER_FTSDCTRL => "FT PC133 SDRAM Controller ",
GAISLER_FTSRCTRL8 => "FT 8-bit SRAM/16-bit IO Ctrl ",
GAISLER_FTSDCTRL64=> "64-bit FT SDRAM Controller ",
GAISLER_AHBSTAT => "AHB Status Register ",
GAISLER_AHBJTAG => "JTAG Debug Link ",
GAISLER_ETHMAC => "GR Ethernet MAC ",
GAISLER_SWNODE => "SpaceWire Node Interface ",
GAISLER_SPW => "SpaceWire Serial Link ",
GAISLER_VGACTRL => "VGA controller ",
GAISLER_APBPS2 => "PS2 interface ",
GAISLER_LOGAN => "On chip Logic Analyzer ",
GAISLER_SVGACTRL => "SVGA frame buffer ",
GAISLER_T1AHB => "Niagara T1 PCX/AHB bridge ",
GAISLER_B1553BC => "AMBA Wrapper for Core1553BBC ",
GAISLER_B1553RT => "AMBA Wrapper for Core1553BRT ",
GAISLER_B1553BRM => "AMBA Wrapper for Core1553BRM ",
GAISLER_SATCAN => "SatCAN controller ",
GAISLER_CANMUX => "CAN Bus multiplexer ",
GAISLER_GRTMRX => "CCSDS Telemetry Receiver ",
GAISLER_GRTCTX => "CCSDS Telecommand Transmitter ",
GAISLER_GRTMDESC => "CCSDS Telemetry Descriptor ",
GAISLER_GRTMVC => "CCSDS Telemetry VC Generator ",
GAISLER_GRTMPAHB => "CCSDS Telemetry VC AHB Input ",
GAISLER_GEFFE => "Geffe Generator ",
GAISLER_SPWCUC => "CCSDS CUC / SpaceWire I/F ",
GAISLER_GPREG => "General Purpose Register ",
GAISLER_AES => "Advanced Encryption Standard ",
GAISLER_AESDMA => "AES 256 DMA ",
GAISLER_GRPCI2 => "GRPCI2 PCI/AHB bridge ",
GAISLER_GRPCI2_DMA=> "GRPCI2 DMA interface ",
GAISLER_GRPCI2_TB => "GRPCI2 Trace buffer ",
GAISLER_MMA => "Memory Mapped AMBA ",
GAISLER_ECC => "Elliptic Curve Cryptography ",
GAISLER_PCIF => "AMBA Wrapper for CorePCIF ",
GAISLER_USBDC => "GR USB 2.0 Device Controller ",
GAISLER_USB_DCL => "USB Debug Communication Link ",
GAISLER_DDRMP => "Multi-port DDR controller ",
GAISLER_ATACTRL => "ATA controller ",
GAISLER_DDRSP => "Single-port DDR266 controller ",
GAISLER_EHCI => "USB Enhanced Host Controller ",
GAISLER_UHCI => "USB Universal Host Controller ",
GAISLER_I2CMST => "AMBA Wrapper for OC I2C-master ",
GAISLER_I2CSLV => "I2C Slave ",
GAISLER_U16550 => "Simple 16550 UART ",
GAISLER_SPICTRL => "SPI Controller ",
GAISLER_DDR2SP => "Single-port DDR2 controller ",
GAISLER_GRTESTMOD => "Test report module ",
GAISLER_CLKMOD => "CPU Clock Switching Ctrl module",
GAISLER_SLINK => "SLINK Master ",
GAISLER_HAPSTRAK => "HAPS HapsTrak I/O Port ",
GAISLER_TEST_1X2 => "HAPS TEST_1x2 interface ",
GAISLER_WILD2AHB => "WildCard CardBus interface ",
GAISLER_BIO1 => "Basic I/O board BIO1 ",
GAISLER_ASCS => "ASCS Master ",
GAISLER_SPW2 => "GRSPW2 SpaceWire Serial Link ",
GAISLER_IPMVBCTRL => "IPM-bus/MVBC memory controller ",
GAISLER_SPIMCTRL => "SPI Memory Controller ",
GAISLER_L4STAT => "LEON4 Statistics Unit ",
GAISLER_LEON4 => "LEON4 SPARC V8 Processor ",
GAISLER_LEON4DSU => "LEON4 Debug Support Unit ",
GAISLER_PWM => "PWM generator ",
GAISLER_L2CACHE => "L2-Cache Controller ",
GAISLER_SDCTRL64 => "64-bit PC133 SDRAM Controller ",
GAISLER_MP7WRAP => "CoreMP7 wrapper ",
GAISLER_GRSYSMON => "AMBA wrapper for System Monitor",
GAISLER_GRACECTRL => "System ACE I/F Controller ",
GAISLER_ATAHBSLV => "AMBA Test Framework AHB Slave ",
GAISLER_ATAHBMST => "AMBA Test Framework AHB Master ",
GAISLER_ATAPBSLV => "AMBA Test Framework APB Slave ",
GAISLER_MIGDDR2 => "Xilinx MIG DDR2 Controller ",
GAISLER_LCDCTRL => "LCD Controller ",
GAISLER_SWITCHOVER=> "Switchover Logic ",
GAISLER_FIFOUART => "UART with large FIFO ",
GAISLER_MUXCTRL => "Analogue multiplexer control ",
GAISLER_GR1553B => "MIL-STD-1553B Interface ",
GAISLER_1553TST => "MIL-STD-1553B Test Device ",
GAISLER_MEMSCRUB => "AHB Memory Scrubber ",
GAISLER_GRIOMMU => "IO Memory Management Unit ",
GAISLER_SPW2_DMA => "GRSPW Router DMA interface ",
GAISLER_SPWROUTER => "GRSPW Router ",
GAISLER_EDCLMST => "EDCL master interface ",
GAISLER_GRPWTX => "PacketWire Transmitter with DMA",
GAISLER_GRPWRX => "PacketWire Receiver with DMA ",
GAISLER_GRIOMMU2 => "IOMMU secondary master i/f ",
GAISLER_I2C2AHB => "I2C to AHB Bridge ",
GAISLER_NANDFCTRL => "NAND Flash Controller ",
GAISLER_N2PLLCTRL => "N2X PLL Dynamic Config. i/f ",
GAISLER_N2DLLCTRL => "N2X DLL Dynamic Config. i/f ",
GAISLER_GPREGBANK => "General Purpose Register Bank ",
GAISLER_SPI2AHB => "SPI to AHB Bridge ",
GAISLER_DDRSDMUX => "Muxed FT DDR/SDRAM controller ",
GAISLER_AHBFROM => "Flash ROM Memory ",
GAISLER_PCIEXP => "Xilinx PCI EXPRESS Wrapper ",
GAISLER_MIG_7SERIES => "Xilinx MIG DDR3 Controller ",
GAISLER_GRSPW2_SIST => "GRSPW Router SIST ",
GAISLER_SGMII => "XILINX SGMII Interface ",
GAISLER_RGMII => "Gaisler RGMII Interface ",
GAISLER_IRQGEN => "Interrupt generator ",
GAISLER_GRDMAC => "GRDMAC DMA Controller ",
GAISLER_AHB2AVLA => "Avalon-MM memory controller ",
GAISLER_SPWTDP => "CCSDS TDP / SpaceWire I/F ",
GAISLER_L3STAT => "LEON3 Statistics Unit ",
GAISLER_GR740THS => "Temperature sensor ",
GAISLER_GRRM => "Reconfiguration Module ",
GAISLER_CMAP => "CCSDS Memory Access Protocol ",
GAISLER_CPGEN => "Discrete Command Pulse Gen ",
GAISLER_AMBAPROT => "AMBA Protection Unit ",
GAISLER_IGLOO2_BRIDGE => "Microsemi SF2/IGLOO2 MSS/HPMS ",
GAISLER_AHB2AXI => "AMBA AHB/AXI Bridge ",
GAISLER_AXI2AHB => "AMBA AXI/AHB Bridge ",
GAISLER_FDIR_RSTCTRL => "FDIR Reset Controller ",
GAISLER_APB3MST => "AHB/APB3 Bridge ",
GAISLER_LRAM => "Dual-port AHB(/CPU) On-Chip RAM",
GAISLER_BOOTSEQ => "Custom AHB sequencer ",
others => "Unknown Device ");
constant gaisler_lib : vendor_library_type := (
vendorid => VENDOR_GAISLER,
vendordesc => GAISLER_DESC,
device_table => gaisler_device_table
);
constant ESA_DESC : vendor_description := "European Space Agency ";
constant esa_device_table : device_table_type := (
ESA_LEON2 => "LEON2 SPARC V8 Processor ",
ESA_LEON2APB => "LEON2 Peripheral Bus ",
ESA_IRQ => "LEON2 Interrupt Controller ",
ESA_TIMER => "LEON2 Timer ",
ESA_UART => "LEON2 UART ",
ESA_CFG => "LEON2 Configuration Register ",
ESA_IO => "LEON2 Input/Output ",
ESA_MCTRL => "LEON2 Memory Controller ",
ESA_PCIARB => "PCI Arbiter ",
ESA_HURRICANE => "HurriCANe/HurryAMBA CAN Ctrl ",
ESA_SPW_RMAP => "UoD/Saab SpaceWire/RMAP link ",
ESA_AHBUART => "LEON2 AHB Debug UART ",
ESA_SPWA => "ESA/ASTRIUM SpaceWire link ",
ESA_BOSCHCAN => "SSC/BOSCH CAN Ctrl ",
ESA_IRQ2 => "LEON2 Secondary Irq Controller ",
ESA_AHBSTAT => "LEON2 AHB Status Register ",
ESA_WPROT => "LEON2 Write Protection ",
ESA_WPROT2 => "LEON2 Extended Write Protection",
ESA_PDEC3AMBA => "ESA CCSDS PDEC3AMBA TC Decoder ",
ESA_PTME3AMBA => "ESA CCSDS PTME3AMBA TM Encoder ",
others => "Unknown Device ");
constant esa_lib : vendor_library_type := (
vendorid => VENDOR_ESA,
vendordesc => ESA_DESC,
device_table => esa_device_table
);
constant OPENCHIP_DESC : vendor_description := "OpenChip ";
constant openchip_device_table : device_table_type := (
OPENCHIP_APBGPIO => "APB General Purpose IO ",
OPENCHIP_APBI2C => "APB I2C Interface ",
OPENCHIP_APBSPI => "APB SPI Interface ",
OPENCHIP_APBCHARLCD => "APB Character LCD ",
OPENCHIP_APBPWM => "APB PWM ",
OPENCHIP_APBPS2 => "APB PS/2 Interface ",
OPENCHIP_APBMMCSD => "APB MMC/SD Card Interface ",
OPENCHIP_APBNAND => "APB NAND(SmartMedia) Interface ",
OPENCHIP_APBLPC => "APB LPC Interface ",
OPENCHIP_APBCF => "APB CompactFlash (IDE) ",
OPENCHIP_APBSYSACE => "APB SystemACE Interface ",
OPENCHIP_APB1WIRE => "APB 1-Wire Interface ",
OPENCHIP_APBJTAG => "APB JTAG TAP Master ",
OPENCHIP_APBSUI => "APB Simple User Interface ",
others => "Unknown Device ");
constant openchip_lib : vendor_library_type := (
vendorid => VENDOR_OPENCHIP,
vendordesc => OPENCHIP_DESC,
device_table => openchip_device_table
);
constant GLEICHMANN_DESC : vendor_description := "Gleichmann Electronics ";
constant gleichmann_device_table : device_table_type := (
GLEICHMANN_CUSTOM => "Custom device ",
GLEICHMANN_GEOLCD01 => "GEOLCD01 graphics system ",
GLEICHMANN_DAC => "Sigma delta DAC ",
GLEICHMANN_HPI => "AHB-to-HPI bridge ",
GLEICHMANN_SPI => "SPI master ",
GLEICHMANN_HIFC => "Human interface controller ",
GLEICHMANN_ADCDAC => "Sigma delta ADC/DAC ",
GLEICHMANN_SPIOC => "SPI master for SDCard IF ",
GLEICHMANN_AC97 => "AC97 Controller ",
others => "Unknown Device ");
constant gleichmann_lib : vendor_library_type := (
vendorid => VENDOR_GLEICHMANN,
vendordesc => GLEICHMANN_DESC,
device_table => gleichmann_device_table
);
constant CONTRIB_DESC : vendor_description := "Various contributions ";
constant contrib_device_table : device_table_type := (
CONTRIB_CORE1 => "Contributed core 1 ",
CONTRIB_CORE2 => "Contributed core 2 ",
others => "Unknown Device ");
constant contrib_lib : vendor_library_type := (
vendorid => VENDOR_CONTRIB,
vendordesc => CONTRIB_DESC,
device_table => contrib_device_table
);
constant MENTA_DESC : vendor_description := "Menta ";
constant menta_device_table : device_table_type := (
MENTA_EFPGA_IP => "eFPGA Core IP ",
others => "Unknown Device ");
constant menta_lib : vendor_library_type := (
vendorid => VENDOR_MENTA,
vendordesc => MENTA_DESC,
device_table => menta_device_table
);
constant SUN_DESC : vendor_description := "Sun Microsystems ";
constant sun_device_table : device_table_type := (
SUN_T1 => "Niagara T1 SPARC V9 Processor ",
SUN_S1 => "Niagara S1 SPARC V9 Processor ",
others => "Unknown Device ");
constant sun_lib : vendor_library_type := (
vendorid => VENDOR_SUN,
vendordesc => SUN_DESC,
device_table => sun_device_table
);
constant OPENCORES_DESC : vendor_description := "OpenCores ";
constant opencores_device_table : device_table_type := (
others => "Unknown Device ");
constant opencores_lib : vendor_library_type := (
vendorid => VENDOR_OPENCORES,
vendordesc => OPENCORES_DESC,
device_table => opencores_device_table
);
constant CBKPAN_DESC : vendor_description := "CBK PAN ";
constant cbkpan_device_table : device_table_type := (
CBKPAN_FTNANDCTRL => "NAND FLASH controller w/DMA ",
CBKPAN_FTEEPROMCTRL => "Fault Toler. EEPROM Controller ",
CBKPAN_FTSDCTRL16 => "Fault Toler. 16-bit SDRAM Ctrl.",
CBKPAN_STIXCTRL => "SolO/STIX IDPU dedicated ctrl. ",
others => "Unknown Device ");
constant cbkpan_lib : vendor_library_type := (
vendorid => VENDOR_CBKPAN,
vendordesc => CBKPAN_DESC,
device_table => cbkpan_device_table
);
constant CETON_DESC : vendor_description := "Ceton Corporation ";
constant ceton_device_table : device_table_type := (
others => "Unknown Device ");
constant ceton_lib : vendor_library_type := (
vendorid => VENDOR_CETON,
vendordesc => CETON_DESC,
device_table => ceton_device_table
);
constant SYNOPSYS_DESC : vendor_description := "Synopsys Inc. ";
constant synopsys_device_table : device_table_type := (
others => "Unknown Device ");
constant synopsys_lib : vendor_library_type := (
vendorid => VENDOR_SYNOPSYS,
vendordesc => SYNOPSYS_DESC,
device_table => synopsys_device_table
);
constant EMBEDDIT_DESC : vendor_description := "Embedd.it ";
constant embeddit_device_table : device_table_type := (
others => "Unknown Device ");
constant embeddit_lib : vendor_library_type := (
vendorid => VENDOR_EMBEDDIT,
vendordesc => EMBEDDIT_DESC,
device_table => embeddit_device_table
);
constant dlr_device_table : device_table_type := (
others => "Unknown Device ");
constant DLR_DESC : vendor_description := "German Aerospace Center ";
constant dlr_lib : vendor_library_type := (
vendorid => VENDOR_DLR,
vendordesc => DLR_DESC,
device_table => dlr_device_table
);
constant eonic_device_table : device_table_type := (
others => "Unknown Device ");
constant EONIC_DESC : vendor_description := "Eonic BV ";
constant eonic_lib : vendor_library_type := (
vendorid => VENDOR_EONIC,
vendordesc => EONIC_DESC,
device_table => eonic_device_table
);
constant telecompt_device_table : device_table_type := (
others => "Unknown Device ");
constant TELECOMPT_DESC : vendor_description := "Telecom ParisTech ";
constant telecompt_lib : vendor_library_type := (
vendorid => VENDOR_TELECOMPT,
vendordesc => TELECOMPT_DESC,
device_table => telecompt_device_table
);
constant radionor_device_table : device_table_type := (
others => "Unknown Device ");
constant RADIONOR_DESC : vendor_description := "Radionor Communications ";
constant radionor_lib : vendor_library_type := (
vendorid => VENDOR_RADIONOR,
vendordesc => RADIONOR_DESC,
device_table => radionor_device_table
);
constant bsc_device_table : device_table_type := (
BSC_CORE1 => "Core 1 ",
BSC_CORE2 => "Core 2 ",
others => "Unknown Device ");
constant BSC_DESC : vendor_description := "BSC ";
constant bsc_lib : vendor_library_type := (
vendorid => VENDOR_BSC,
vendordesc => BSC_DESC,
device_table => bsc_device_table
);
constant dtu_device_table : device_table_type := (
DTU_IV => "Instrument Virtualizer ",
DTU_RBMMTRANS => "RB/MM Transfer ",
DTU_FTMCTRL => "Memory controller with 8CS ",
others => "Unknown Device ");
constant DTU_DESC : vendor_description := "DTU Space ";
constant dtu_lib : vendor_library_type := (
vendorid => VENDOR_DTU,
vendordesc => DTU_DESC,
device_table => dtu_device_table
);
constant orbita_device_table : device_table_type := (
ORBITA_1553B => "MIL-STD-1553B Controller ",
ORBITA_429 => "429 Interface ",
ORBITA_SPI => "SPI Interface ",
ORBITA_I2C => "I2C Interface ",
ORBITA_SMARTCARD => "Smart Card Reader ",
ORBITA_SDCARD => "SD Card Reader ",
ORBITA_UART16550 => "16550 UART ",
ORBITA_CRYPTO => "Crypto Engine ",
ORBITA_SYSIF => "System Interface ",
ORBITA_PIO => "Programmable IO module ",
ORBITA_RTC => "Real-Time Clock ",
ORBITA_COLORLCD => "Color LCD Controller ",
ORBITA_PCI => "PCI Module ",
ORBITA_DSP => "DPS Co-Processor ",
ORBITA_USBHOST => "USB Host ",
ORBITA_USBDEV => "USB Device ",
others => "Unknown Device ");
constant ORBITA_DESC : vendor_description := "Orbita ";
constant orbita_lib : vendor_library_type := (
vendorid => VENDOR_ORBITA,
vendordesc => ORBITA_DESC,
device_table => orbita_device_table
);
constant ACTEL_DESC : vendor_description := "Actel Corporation ";
constant actel_device_table : device_table_type := (
ACTEL_COREMP7 => "CoreMP7 Processor ",
others => "Unknown Device ");
constant actel_lib : vendor_library_type := (
vendorid => VENDOR_ACTEL,
vendordesc => ACTEL_DESC,
device_table => actel_device_table
);
constant NASA_DESC : vendor_description := "NASA ";
constant nasa_device_table : device_table_type := (
NASA_EP32 => "EP32 Forth processor ",
others => "Unknown Device ");
constant nasa_lib : vendor_library_type := (
vendorid => VENDOR_NASA,
vendordesc => NASA_DESC,
device_table => nasa_device_table
);
constant NASA_GSFC_DESC : vendor_description := "NASA GSFC ";
constant nasa_gsfc_device_table : device_table_type := (
others => "Unknown Device ");
constant nasa_gsfc_lib : vendor_library_type := (
vendorid => VENDOR_NASA_GSFC,
vendordesc => NASA_GSFC_DESC,
device_table => nasa_gsfc_device_table
);
constant S3_DESC : vendor_description := "S3 Group ";
constant s3_device_table : device_table_type := (
others => "Unknown Device ");
constant s3_lib : vendor_library_type := (
vendorid => VENDOR_S3,
vendordesc => S3_DESC,
device_table => s3_device_table
);
constant APPLECORE_DESC : vendor_description := "AppleCore ";
constant applecore_device_table : device_table_type := (
APPLECORE_UTLEON3 => "AppleCore uT-LEON3 Processor ",
APPLECORE_UTLEON3DSU => "AppleCore uT-LEON3 DSU ",
others => "Unknown Device ");
constant applecore_lib : vendor_library_type := (
vendorid => VENDOR_APPLECORE,
vendordesc => APPLECORE_DESC,
device_table => applecore_device_table
);
constant C3E_DESC : vendor_description := "TU Braunschweig C3E ";
constant c3e_device_table : device_table_type := (
others => "Unknown Device ");
constant c3e_lib : vendor_library_type := (
vendorid => VENDOR_C3E,
vendordesc => C3E_DESC,
device_table => c3e_device_table
);
constant UNKNOWN_DESC : vendor_description := "Unknown vendor ";
constant unknown_device_table : device_table_type := (
others => "Unknown Device ");
constant unknown_lib : vendor_library_type := (
vendorid => 0,
vendordesc => UNKNOWN_DESC,
device_table => unknown_device_table
);
constant iptable : device_array := (
VENDOR_GAISLER => gaisler_lib,
VENDOR_ESA => esa_lib,
VENDOR_OPENCHIP => openchip_lib,
VENDOR_OPENCORES => opencores_lib,
VENDOR_CONTRIB => contrib_lib,
VENDOR_DLR => dlr_lib,
VENDOR_EONIC => eonic_lib,
VENDOR_TELECOMPT => telecompt_lib,
VENDOR_GLEICHMANN => gleichmann_lib,
VENDOR_MENTA => menta_lib,
VENDOR_EMBEDDIT => embeddit_lib,
VENDOR_SUN => sun_lib,
VENDOR_RADIONOR => radionor_lib,
VENDOR_ORBITA => orbita_lib,
VENDOR_SYNOPSYS => synopsys_lib,
VENDOR_CETON => ceton_lib,
VENDOR_ACTEL => actel_lib,
VENDOR_NASA => nasa_lib,
VENDOR_NASA_GSFC => nasa_gsfc_lib,
VENDOR_S3 => s3_lib,
others => unknown_lib);
type system_table_type is array (0 to 65535) of device_description;
constant system_table : system_table_type := (
LEON3_ACT_FUSION => "LEON3 Actel Fusion Dev. board ",
LEON3_RTAX_CID2 => "LEON3FT RTAX Configuration 2 ",
LEON3_RTAX_CID5 => "LEON3FT RTAX Configuration 5 ",
LEON3_RTAX_CID6 => "LEON3FT RTAX Configuration 6 ",
LEON3_RTAX_CID7 => "LEON3FT RTAX Configuration 7 ",
LEON3_RTAX_CID8 => "LEON3FT RTAX Configuration 8 ",
LEON3_PROXIMA => "LEON3 PROXIMA FPGA design ",
ALTERA_DE2 => "Altera DE2 Development board ",
ALTERA_DE4 => "TerASIC DE4 Development board ",
XILINX_ML401 => "Xilinx ML401 Development board ",
XILINX_ML501 => "Xilinx ML501 Development board ",
XILINX_ML505 => "Xilinx ML505 Development board ",
XILINX_ML506 => "Xilinx ML506 Development board ",
XILINX_ML507 => "Xilinx ML507 Development board ",
XILINX_ML509 => "Xilinx ML509 Development board ",
XILINX_ML510 => "Xilinx ML510 Development board ",
XILINX_AC701 => "Xilinx AC701 Development board ",
XILINX_KC705 => "Xilinx KC705 Development board ",
XILINX_VC707 => "Xilinx VC707 Development board ",
MICROSEMI_M2GL_EVAL=> "Microsemi IGLOO2 Evaluation kit",
XILINX_SP601 => "Xilinx SP601 Development board ",
XILINX_ML605 => "Xilinx ML605 Development board ",
others => "Unknown system ");
-- pragma translate_on
end;
| gpl-3.0 | 6c1ec0e48249225fe106491af719a393 | 0.593582 | 3.691368 | false | false | false | false |
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