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emogenet/ghdl | testsuite/gna/bug071/atod.vhdl | 1 | 1,241 | entity atod is
end atod;
architecture behav of atod is
type real_array is array (natural range <>) of real;
constant csts : real_array :=
(1.0,
0.0,
-- Corner cases from
-- http://www.exploringbinary.com/
-- decimal-to-realing-point-needs-arbitrary-precision/
7.8459735791271921e65,
-- In binary:
-- 1.11011100 11010000 00001000 10011100 00010011 00010100 1110 e218
-- 1. d c d 0 0 8 9 c 1 3 1 4 e
3.571e266,
-- 1.01100010 01100100 01001100 01100001 11010100 00011010 1010 e885
-- 1. 6 2 6 4 4 c 6 1 d 4 1 a a
3.08984926168550152811E-32,
-- 1.01000000 11011110 01001000 01100111 01100110 01010011 1011 e-105
-- 1. 4 0 d e 4 8 6 7 6 6 5 3 b
7.4505805969238281e-09
);
begin
process
variable v : real;
begin
for i in csts'range loop
report to_string (csts (i), "%a") severity note;
end loop;
v := csts (2);
assert to_string (v, "%a") = "0x1.dcd0089c1314ep+218" severity failure;
v := csts (3);
assert to_string (v, "%a") = "0x1.62644c61d41aap+885" severity failure;
wait;
end process;
end behav;
| gpl-2.0 | 4b722dd7aa09fa86a98eb9b65bd29093 | 0.570508 | 2.947743 | false | false | false | false |
hacklabmikkeli/rough-boy | common.vhdl | 2 | 5,638 | --
-- Knobs Galore - a free phase distortion synthesizer
-- Copyright (C) 2015 Ilmo Euro
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
library ieee;
library std;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
use std.textio.all;
package common is
constant ctl_bits : natural := 8;
constant ctl_max : natural := 2**ctl_bits;
constant ctl_hi : natural := ctl_max - 1;
subtype ctl_signal is unsigned(ctl_bits - 1 downto 0);
constant time_bits : natural := 17;
constant time_max : natural := 2**time_bits;
constant time_hi : natural := time_max - 1;
subtype time_signal is unsigned(time_bits - 1 downto 0);
constant voice_bits : natural := 13;
constant voice_max : natural := 2**voice_bits;
constant voice_hi : natural := voice_max - 1;
subtype voice_signal is unsigned(voice_bits - 1 downto 0);
constant audio_bits : natural := 16;
constant audio_max : natural := 2**audio_bits;
constant audio_hi : natural := audio_max - 1;
subtype audio_signal is unsigned(audio_bits - 1 downto 0);
constant keys_bits : natural := 6;
constant keys_max : natural := 2**keys_bits;
constant keys_hi : natural := keys_max - 1;
subtype keys_signal is unsigned(keys_bits - 1 downto 0);
subtype adsr_stage is std_logic_vector(1 downto 0);
constant adsr_attack: adsr_stage := "00";
constant adsr_decay: adsr_stage := "01";
constant adsr_sustain: adsr_stage := "10";
constant adsr_rel: adsr_stage := "11";
subtype waveform_t is std_logic;
constant waveform_saw: waveform_t := '0';
constant waveform_sq: waveform_t := '1';
subtype mode_t is unsigned(2 downto 0);
constant mode_saw: mode_t := "000";
constant mode_sq: mode_t := "001";
constant mode_saw_res: mode_t := "010";
constant mode_sq_res: mode_t := "011";
constant mode_saw_fat: mode_t := "100";
constant mode_sq_fat: mode_t := "101";
constant mode_saw_sync: mode_t := "110";
constant mode_mix: mode_t := "111";
subtype voice_transform_t is unsigned(1 downto 0);
constant voice_transform_none: voice_transform_t := "00";
constant voice_transform_oct: voice_transform_t := "01";
constant voice_transform_sub: voice_transform_t := "10";
subtype key_event_t is std_logic_vector(1 downto 0);
constant key_event_idle: key_event_t := "00";
constant key_event_make: key_event_t := "01";
constant key_event_break: key_event_t := "10";
type state_vector_t is
record
sv_phase: time_signal;
sv_gain: time_signal;
sv_gain_stage: adsr_stage;
sv_gain_prev_gate: std_logic;
sv_cutoff: time_signal;
sv_cutoff_stage: adsr_stage;
sv_cutoff_prev_gate: std_logic;
end record;
type synthesis_params is
record
sp_mode: mode_t;
sp_transform: voice_transform_t;
sp_cutoff_base: ctl_signal;
sp_cutoff_env: ctl_signal;
sp_cutoff_attack: ctl_signal;
sp_cutoff_decay: ctl_signal;
sp_cutoff_sustain: ctl_signal;
sp_cutoff_rel: ctl_signal;
sp_gain_attack: ctl_signal;
sp_gain_decay: ctl_signal;
sp_gain_sustain: ctl_signal;
sp_gain_rel: ctl_signal;
end record;
constant voices_bits: natural := 3;
constant num_voices: natural := 2**voices_bits;
constant empty_state_vector : state_vector_t :=
((others => '0')
,(others => '0')
,adsr_rel
,'0'
,(others => '0')
,adsr_rel
,'0'
);
constant empty_synthesis_params : synthesis_params :=
(mode_saw
,voice_transform_none
,x"FF"
,x"00"
,x"FF"
,x"FF"
,x"FF"
,x"FF"
,x"FF"
,x"FF"
,x"FF"
,x"FF"
);
-- TODO: make the array larger after optimizing
type ctl_lut_t is array(0 to 255, 0 to 16) of ctl_signal;
function to_ctl(input: time_signal)
return ctl_signal;
function to_audio_msb(input: ctl_signal)
return audio_signal;
function to_audio_lsb(input: ctl_signal)
return audio_signal;
end common;
package body common is
function to_ctl(input: time_signal)
return ctl_signal is
begin
return input(input'high downto input'high - ctl_bits + 1);
end function;
function to_audio_msb(input: ctl_signal)
return audio_signal is
variable retval: audio_signal := (others => '0');
begin
retval(retval'high downto retval'high - ctl_bits + 1) := input;
return retval;
end function;
function to_audio_lsb(input: ctl_signal)
return audio_signal is
variable retval: audio_signal := (others => '0');
begin
retval(ctl_bits - 1 downto 0) := input;
return retval;
end function;
end common;
| gpl-3.0 | cf8f7ffa9f7a3ff5e2e5f132014c7d6e | 0.604824 | 3.539234 | false | false | false | false |
emogenet/ghdl | testsuite/vests/vhdl-93/ashenden/compliant/ch_21_fg_21_02.vhd | 4 | 4,483 |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_21_fg_21_02.vhd,v 1.2 2001-10-26 16:29:37 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
library ieee; use ieee.std_logic_1164.all;
package project_util is
-- code from book (in text)
function "<" ( bv1, bv2 : bit_vector ) return boolean;
subtype word is std_logic_vector(31 downto 0);
-- end code from book
end package project_util;
package body project_util is
function "<" ( bv1, bv2 : bit_vector ) return boolean is
variable tmp1 : bit_vector(bv1'range) := bv1;
variable tmp2 : bit_vector(bv2'range) := bv2;
begin
assert bv1'length = bv2'length
report "vectors are of different length in ""<"" comparison"
severity failure;
tmp1(tmp1'left) := not tmp1(tmp1'left);
tmp2(tmp2'left) := not tmp2(tmp2'left);
return std.standard."<" ( tmp1, tmp2 );
end function "<";
end package body project_util;
-- code from book
library ieee; use ieee.std_logic_1164.all;
use work.project_util.all;
entity limit_checker is
port ( input, lower_bound, upper_bound : in word;
out_of_bounds : out std_logic );
end entity limit_checker;
--------------------------------------------------
architecture behavioral of limit_checker is
subtype bv_word is bit_vector(31 downto 0);
function word_to_bitvector ( w : in word ) return bv_word is
begin
return To_bitvector ( w, xmap => '0' );
end function word_to_bitvector;
begin
algorithm : process (input, lower_bound, upper_bound) is
begin
if "<" ( bv1 => word_to_bitvector(input),
bv2 => word_to_bitvector(lower_bound) )
or "<" ( bv1 => word_to_bitvector(upper_bound),
bv2 => word_to_bitvector(input) ) then
out_of_bounds <= '1';
else
out_of_bounds <= '0';
end if;
end process algorithm;
end architecture behavioral;
-- end code from book
library ieee; use ieee.std_logic_1164.all;
use work.project_util.all;
entity fg_21_02 is
end entity fg_21_02;
architecture test of fg_21_02 is
signal input : word;
signal out_of_bounds : std_logic;
begin
dut : entity work.limit_checker(behavioral)
port map ( input => input,
lower_bound => X"FFFFFFF0", upper_bound => X"00000010",
out_of_bounds => out_of_bounds );
stimulus : input <= X"00000000",
X"00000008" after 10 ns,
X"00000010" after 20 ns,
X"00000018" after 30 ns,
X"FFFFFFF8" after 40 ns,
X"FFFFFFF0" after 50 ns,
X"FFFFFF00" after 60 ns;
end architecture test;
| gpl-2.0 | 9c8b6618a9d2fc2e6e233df94059d365 | 0.479813 | 4.82043 | false | false | false | false |
emogenet/ghdl | libraries/ieee2008/numeric_std_unsigned-body.vhdl | 4 | 18,848 | -- --------------------------------------------------------------------
--
-- Copyright © 2008 by IEEE. All rights reserved.
--
-- This source file is an essential part of IEEE Std 1076-2008,
-- IEEE Standard VHDL Language Reference Manual. This source file may not be
-- copied, sold, or included with software that is sold without written
-- permission from the IEEE Standards Department. This source file may be
-- copied for individual use between licensed users. This source file is
-- provided on an AS IS basis. The IEEE disclaims ANY WARRANTY EXPRESS OR
-- IMPLIED INCLUDING ANY WARRANTY OF MERCHANTABILITY AND FITNESS FOR USE
-- FOR A PARTICULAR PURPOSE. The user of the source file shall indemnify
-- and hold IEEE harmless from any damages or liability arising out of the
-- use thereof.
--
-- Title : Standard VHDL Synthesis Packages
-- : (NUMERIC_STD_UNSIGNED package body)
-- :
-- Library : This package shall be compiled into a library
-- : symbolically named IEEE.
-- :
-- Developers: Accellera VHDL-TC, and IEEE P1076 Working Group
-- :
-- Purpose : This package defines numeric types and arithmetic functions
-- : for use with synthesis tools. Values of type STD_ULOGIC_VECTOR
-- : are interpreted as unsigned numbers in vector form.
-- : The leftmost bit is treated as the most significant bit.
-- : This package contains overloaded arithmetic operators on
-- : the STD_ULOGIC_VECTOR type. The package also contains
-- : useful type conversions functions, clock detection
-- : functions, and other utility functions.
-- :
-- : If any argument to a function is a null array, a null array
-- : is returned (exceptions, if any, are noted individually).
--
-- Note : This package may be modified to include additional data
-- : required by tools, but it must in no way change the
-- : external interfaces or simulation behavior of the
-- : description. It is permissible to add comments and/or
-- : attributes to the package declarations, but not to change
-- : or delete any original lines of the package declaration.
-- : The package body may be changed only in accordance with
-- : the terms of Clause 16 of this standard.
-- :
-- --------------------------------------------------------------------
-- $Revision: 1220 $
-- $Date: 2008-04-10 17:16:09 +0930 (Thu, 10 Apr 2008) $
-- --------------------------------------------------------------------
library ieee;
use ieee.numeric_std.all;
package body NUMERIC_STD_UNSIGNED is
-- Id: A.3
function "+" (L, R : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is
begin
return STD_ULOGIC_VECTOR (UNSIGNED(L) + UNSIGNED(R));
end function "+";
-- Id: A.3R
function "+"(L : STD_ULOGIC_VECTOR; R : STD_ULOGIC) return STD_ULOGIC_VECTOR is
begin
return STD_ULOGIC_VECTOR (UNSIGNED(L) + R);
end function "+";
-- Id: A.3L
function "+"(L : STD_ULOGIC; R : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is
begin
return STD_ULOGIC_VECTOR (L + UNSIGNED(R));
end function "+";
-- Id: A.5
function "+" (L : STD_ULOGIC_VECTOR; R : NATURAL) return STD_ULOGIC_VECTOR is
begin
return STD_ULOGIC_VECTOR (UNSIGNED(L) + R);
end function "+";
-- Id: A.6
function "+" (L : NATURAL; R : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is
begin
return STD_ULOGIC_VECTOR (L + UNSIGNED(R));
end function "+";
--============================================================================
-- Id: A.9
function "-" (L, R : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is
begin
return STD_ULOGIC_VECTOR (UNSIGNED(L) - UNSIGNED(R));
end function "-";
-- Id: A.9R
function "-"(L : STD_ULOGIC_VECTOR; R : STD_ULOGIC) return STD_ULOGIC_VECTOR is
begin
return STD_ULOGIC_VECTOR (UNSIGNED(L) - R);
end function "-";
-- Id: A.9L
function "-"(L : STD_ULOGIC; R : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is
begin
return STD_ULOGIC_VECTOR (L - UNSIGNED(R));
end function "-";
-- Id: A.11
function "-" (L : STD_ULOGIC_VECTOR; R : NATURAL) return STD_ULOGIC_VECTOR is
begin
return STD_ULOGIC_VECTOR (UNSIGNED(L) - R);
end function "-";
-- Id: A.12
function "-" (L : NATURAL; R : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is
begin
return STD_ULOGIC_VECTOR (L - UNSIGNED(R));
end function "-";
--============================================================================
-- Id: A.15
function "*" (L, R : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is
begin
return STD_ULOGIC_VECTOR (UNSIGNED(L) * UNSIGNED(R));
end function "*";
-- Id: A.17
function "*" (L : STD_ULOGIC_VECTOR; R : NATURAL) return STD_ULOGIC_VECTOR is
begin
return STD_ULOGIC_VECTOR (UNSIGNED(L) * R);
end function "*";
-- Id: A.18
function "*" (L : NATURAL; R : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is
begin
return STD_ULOGIC_VECTOR (L * UNSIGNED(R));
end function "*";
--============================================================================
-- Id: A.21
function "/" (L, R : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is
begin
return STD_ULOGIC_VECTOR (UNSIGNED(L) / UNSIGNED(R));
end function "/";
-- Id: A.23
function "/" (L : STD_ULOGIC_VECTOR; R : NATURAL) return STD_ULOGIC_VECTOR is
begin
return STD_ULOGIC_VECTOR (UNSIGNED(L) / R);
end function "/";
-- Id: A.24
function "/" (L : NATURAL; R : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is
begin
return STD_ULOGIC_VECTOR (L / UNSIGNED(R));
end function "/";
--============================================================================
-- Id: A.27
function "rem" (L, R : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is
begin
return STD_ULOGIC_VECTOR (UNSIGNED(L) rem UNSIGNED(R));
end function "rem";
-- Id: A.29
function "rem" (L : STD_ULOGIC_VECTOR; R : NATURAL) return STD_ULOGIC_VECTOR is
begin
return STD_ULOGIC_VECTOR (UNSIGNED(L) rem R);
end function "rem";
-- Id: A.30
function "rem" (L : NATURAL; R : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is
begin
return STD_ULOGIC_VECTOR (L rem UNSIGNED(R));
end function "rem";
--============================================================================
-- Id: A.33
function "mod" (L, R : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is
begin
return STD_ULOGIC_VECTOR (UNSIGNED(L) mod UNSIGNED(R));
end function "mod";
-- Id: A.35
function "mod" (L : STD_ULOGIC_VECTOR; R : NATURAL) return STD_ULOGIC_VECTOR is
begin
return STD_ULOGIC_VECTOR (UNSIGNED(L) mod R);
end function "mod";
-- Id: A.36
function "mod" (L : NATURAL; R : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is
begin
return STD_ULOGIC_VECTOR (L mod UNSIGNED(R));
end function "mod";
--============================================================================
-- Id: A.39
function find_leftmost (ARG: STD_ULOGIC_VECTOR; Y: STD_ULOGIC) return INTEGER is
begin
return find_leftmost(UNSIGNED(ARG), Y);
end function find_leftmost;
-- Id: A.41
function find_rightmost (ARG: STD_ULOGIC_VECTOR; Y: STD_ULOGIC) return INTEGER is
begin
return find_rightmost(UNSIGNED(ARG), Y);
end function find_rightmost;
--============================================================================
-- Id: C.1
function ">" (L, R : STD_ULOGIC_VECTOR) return BOOLEAN is
begin
return UNSIGNED(L) > UNSIGNED(R);
end function ">";
-- Id: C.3
function ">" (L : NATURAL; R : STD_ULOGIC_VECTOR) return BOOLEAN is
begin
return L > UNSIGNED(R);
end function ">";
-- Id: C.5
function ">" (L : STD_ULOGIC_VECTOR; R : NATURAL) return BOOLEAN is
begin
return UNSIGNED(L) > R;
end function ">";
--============================================================================
-- Id: C.7
function "<" (L, R : STD_ULOGIC_VECTOR) return BOOLEAN is
begin
return UNSIGNED(L) < UNSIGNED(R);
end function "<";
-- Id: C.9
function "<" (L : NATURAL; R : STD_ULOGIC_VECTOR) return BOOLEAN is
begin
return L < UNSIGNED(R);
end function "<";
-- Id: C.11
function "<" (L : STD_ULOGIC_VECTOR; R : NATURAL) return BOOLEAN is
begin
return UNSIGNED(L) < R;
end function "<";
--============================================================================
-- Id: C.13
function "<=" (L, R : STD_ULOGIC_VECTOR) return BOOLEAN is
begin
return UNSIGNED(L) <= UNSIGNED(R);
end function "<=";
-- Id: C.15
function "<=" (L : NATURAL; R : STD_ULOGIC_VECTOR) return BOOLEAN is
begin
return L <= UNSIGNED(R);
end function "<=";
-- Id: C.17
function "<=" (L : STD_ULOGIC_VECTOR; R : NATURAL) return BOOLEAN is
begin
return UNSIGNED(L) <= R;
end function "<=";
--============================================================================
-- Id: C.19
function ">=" (L, R : STD_ULOGIC_VECTOR) return BOOLEAN is
begin
return UNSIGNED(L) >= UNSIGNED(R);
end function ">=";
-- Id: C.21
function ">=" (L : NATURAL; R : STD_ULOGIC_VECTOR) return BOOLEAN is
begin
return L >= UNSIGNED(R);
end function ">=";
-- Id: C.23
function ">=" (L : STD_ULOGIC_VECTOR; R : NATURAL) return BOOLEAN is
begin
return UNSIGNED(L) >= R;
end function ">=";
--============================================================================
-- Id: C.25
function "=" (L, R : STD_ULOGIC_VECTOR) return BOOLEAN is
begin
return UNSIGNED(L) = UNSIGNED(R);
end function "=";
-- Id: C.27
function "=" (L : NATURAL; R : STD_ULOGIC_VECTOR) return BOOLEAN is
begin
return L = UNSIGNED(R);
end function "=";
-- Id: C.29
function "=" (L : STD_ULOGIC_VECTOR; R : NATURAL) return BOOLEAN is
begin
return UNSIGNED(L) = R;
end function "=";
--============================================================================
-- Id: C.31
function "/=" (L, R : STD_ULOGIC_VECTOR) return BOOLEAN is
begin
return UNSIGNED(L) /= UNSIGNED(R);
end function "/=";
-- Id: C.33
function "/=" (L : NATURAL; R : STD_ULOGIC_VECTOR) return BOOLEAN is
begin
return L /= UNSIGNED(R);
end function "/=";
-- Id: C.35
function "/=" (L : STD_ULOGIC_VECTOR; R : NATURAL) return BOOLEAN is
begin
return UNSIGNED(L) /= R;
end function "/=";
--============================================================================
-- Id: C.37
function MINIMUM (L, R: STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is
begin
return STD_ULOGIC_VECTOR (MINIMUM(UNSIGNED(L), UNSIGNED(R)));
end function MINIMUM;
-- Id: C.39
function MINIMUM (L: NATURAL; R: STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is
begin
return STD_ULOGIC_VECTOR (MINIMUM(L, UNSIGNED(R)));
end function MINIMUM;
-- Id: C.41
function MINIMUM (L: STD_ULOGIC_VECTOR; R: NATURAL) return STD_ULOGIC_VECTOR is
begin
return STD_ULOGIC_VECTOR (MINIMUM(UNSIGNED(L), R));
end function MINIMUM;
--============================================================================
-- Id: C.43
function MAXIMUM (L, R: STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is
begin
return STD_ULOGIC_VECTOR (MAXIMUM(UNSIGNED(L), UNSIGNED(R)));
end function MAXIMUM;
-- Id: C.45
function MAXIMUM (L: NATURAL; R: STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is
begin
return STD_ULOGIC_VECTOR (MAXIMUM(L, UNSIGNED(R)));
end function MAXIMUM;
-- Id: C.47
function MAXIMUM (L: STD_ULOGIC_VECTOR; R: NATURAL) return STD_ULOGIC_VECTOR is
begin
return STD_ULOGIC_VECTOR (MAXIMUM(UNSIGNED(L), R));
end function MAXIMUM;
--============================================================================
-- Id: C.49
function "?>" (L, R: STD_ULOGIC_VECTOR) return STD_ULOGIC is
begin
return UNSIGNED(L) ?> UNSIGNED(R);
end function "?>";
-- Id: C.51
function "?>" (L: NATURAL; R: STD_ULOGIC_VECTOR) return STD_ULOGIC is
begin
return L ?> UNSIGNED(R);
end function "?>";
-- Id: C.53
function "?>" (L: STD_ULOGIC_VECTOR; R: NATURAL) return STD_ULOGIC is
begin
return UNSIGNED(L) ?> R;
end function "?>";
--============================================================================
-- Id: C.55
function "?<" (L, R: STD_ULOGIC_VECTOR) return STD_ULOGIC is
begin
return UNSIGNED(L) ?< UNSIGNED(R);
end function "?<";
-- Id: C.57
function "?<" (L: NATURAL; R: STD_ULOGIC_VECTOR) return STD_ULOGIC is
begin
return L ?< UNSIGNED(R);
end function "?<";
-- Id: C.59
function "?<" (L: STD_ULOGIC_VECTOR; R: NATURAL) return STD_ULOGIC is
begin
return UNSIGNED(L) ?< R;
end function "?<";
--============================================================================
-- Id: C.61
function "?<=" (L, R: STD_ULOGIC_VECTOR) return STD_ULOGIC is
begin
return UNSIGNED(L) ?<= UNSIGNED(R);
end function "?<=";
-- Id: C.63
function "?<=" (L: NATURAL; R: STD_ULOGIC_VECTOR) return STD_ULOGIC is
begin
return L ?<= UNSIGNED(R);
end function "?<=";
-- Id: C.65
function "?<=" (L: STD_ULOGIC_VECTOR; R: NATURAL) return STD_ULOGIC is
begin
return UNSIGNED(L) ?<= R;
end function "?<=";
--============================================================================
-- Id: C.67
function "?>=" (L, R: STD_ULOGIC_VECTOR) return STD_ULOGIC is
begin
return UNSIGNED(L) ?>= UNSIGNED(R);
end function "?>=";
-- Id: C.69
function "?>=" (L: NATURAL; R: STD_ULOGIC_VECTOR) return STD_ULOGIC is
begin
return L ?>= UNSIGNED(R);
end function "?>=";
-- Id: C.71
function "?>=" (L: STD_ULOGIC_VECTOR; R: NATURAL) return STD_ULOGIC is
begin
return UNSIGNED(L) ?>= R;
end function "?>=";
--============================================================================
-- Id: C.73
function "?=" (L, R: STD_ULOGIC_VECTOR) return STD_ULOGIC is
begin
return UNSIGNED(L) ?= UNSIGNED(R);
end function "?=";
-- Id: C.75
function "?=" (L: NATURAL; R: STD_ULOGIC_VECTOR) return STD_ULOGIC is
begin
return L ?= UNSIGNED(R);
end function "?=";
-- Id: C.77
function "?=" (L: STD_ULOGIC_VECTOR; R: NATURAL) return STD_ULOGIC is
begin
return UNSIGNED(L) ?= R;
end function "?=";
--============================================================================
-- Id: C.79
function "?/=" (L, R: STD_ULOGIC_VECTOR) return STD_ULOGIC is
begin
return UNSIGNED(L) ?/= UNSIGNED(R);
end function "?/=";
-- Id: C.81
function "?/=" (L: NATURAL; R: STD_ULOGIC_VECTOR) return STD_ULOGIC is
begin
return L ?/= UNSIGNED(R);
end function "?/=";
-- Id: C.83
function "?/=" (L: STD_ULOGIC_VECTOR; R: NATURAL) return STD_ULOGIC is
begin
return UNSIGNED(L) ?/= R;
end function "?/=";
--============================================================================
-- Id: S.1
function SHIFT_LEFT (ARG : STD_ULOGIC_VECTOR; COUNT : NATURAL)
return STD_ULOGIC_VECTOR is
begin
return std_logic_vector (SHIFT_LEFT(unsigned(ARG), COUNT));
end function SHIFT_LEFT;
-- Id: S.2
function SHIFT_RIGHT (ARG : STD_ULOGIC_VECTOR; COUNT : NATURAL)
return STD_ULOGIC_VECTOR is
begin
return std_logic_vector (SHIFT_RIGHT(unsigned(ARG), COUNT));
end function SHIFT_RIGHT;
--============================================================================
-- Id: S.5
function ROTATE_LEFT (ARG : STD_ULOGIC_VECTOR; COUNT : NATURAL)
return STD_ULOGIC_VECTOR is
begin
return std_logic_vector (ROTATE_LEFT(unsigned(ARG), COUNT));
end function ROTATE_LEFT;
-- Id: S.6
function ROTATE_RIGHT (ARG : STD_ULOGIC_VECTOR; COUNT : NATURAL)
return STD_ULOGIC_VECTOR is
begin
return std_logic_vector (ROTATE_RIGHT(unsigned(ARG), COUNT));
end function ROTATE_RIGHT;
--============================================================================
-- Id: S.17
function "sla" (ARG: STD_ULOGIC_VECTOR; COUNT: INTEGER)
return STD_ULOGIC_VECTOR is
begin
return STD_ULOGIC_VECTOR (UNSIGNED(ARG) sla COUNT);
end function "sla";
-- Id: S.19
function "sra" (ARG: STD_ULOGIC_VECTOR; COUNT: INTEGER)
return STD_ULOGIC_VECTOR is
begin
return STD_ULOGIC_VECTOR (UNSIGNED(ARG) sra COUNT);
end function "sra";
--============================================================================
-- Id: R.2
function RESIZE (ARG : STD_ULOGIC_VECTOR; NEW_SIZE : NATURAL)
return STD_ULOGIC_VECTOR is
begin
return STD_ULOGIC_VECTOR (
RESIZE (ARG => UNSIGNED(ARG),
NEW_SIZE => NEW_SIZE));
end function RESIZE;
function RESIZE (ARG, SIZE_RES : STD_ULOGIC_VECTOR)
return STD_ULOGIC_VECTOR is
begin
return STD_ULOGIC_VECTOR (
RESIZE (ARG => UNSIGNED(ARG),
NEW_SIZE => SIZE_RES'length));
end function RESIZE;
--============================================================================
-- Id: D.1
function TO_INTEGER (ARG : STD_ULOGIC_VECTOR) return NATURAL is
begin
return TO_INTEGER(UNSIGNED(ARG));
end function TO_INTEGER;
-- Id: D.3
function To_StdLogicVector (ARG, SIZE : NATURAL) return STD_LOGIC_VECTOR is
begin
return STD_LOGIC_VECTOR (TO_UNSIGNED(ARG => ARG,
SIZE => SIZE));
end function To_StdLogicVector;
-- Id: D.5
function To_StdULogicVector (ARG, SIZE : NATURAL) return STD_ULOGIC_VECTOR is
begin
return STD_ULOGIC_VECTOR (TO_UNSIGNED(ARG => ARG,
SIZE => SIZE));
end function To_StdULogicVector;
function To_StdLogicVector (ARG : NATURAL; SIZE_RES : STD_ULOGIC_VECTOR)
return STD_LOGIC_VECTOR is
begin
return STD_LOGIC_VECTOR (TO_UNSIGNED (ARG => ARG,
SIZE => SIZE_RES'length));
end function To_StdLogicVector;
function To_StdULogicVector (ARG : NATURAL; SIZE_RES : STD_ULOGIC_VECTOR)
return STD_ULOGIC_VECTOR is
begin
return STD_ULOGIC_VECTOR (TO_UNSIGNED (ARG => ARG,
SIZE => SIZE_RES'length));
end function To_StdULogicVector;
end package body NUMERIC_STD_UNSIGNED;
| gpl-2.0 | 52112e446a4687878bc3141a4564b12c | 0.533691 | 4.170834 | false | false | false | false |
emogenet/ghdl | testsuite/vests/vhdl-93/ashenden/non_compliant/ch_17_fg_17_16.vhd | 4 | 3,886 |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_17_fg_17_16.vhd,v 1.2 2001-10-26 16:29:37 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
package body «element_type_simple_name»_ordered_collection_adt is
function new_ordered_collection return ordered_collection is
variable result : ordered_collection := new ordered_collection_object;
begin
result.next_element := result;
result.prev_element := result;
return result;
end function new_ordered_collection;
procedure insert ( c : inout ordered_collection; e : in element_type ) is
variable current_element : ordered_collection := c.next_element;
variable new_element : ordered_collection;
begin
while current_element /= c
and key_of(current_element.element) < key_of(e) loop
current_element := current_element.next_element;
end loop;
-- insert new element before current_element
new_element := new ordered_collection_object'(
element => e,
next_element => current_element,
prev_element => current_element.prev_element );
new_element.next_element.prev_element := new_element;
new_element.prev_element.next_element := new_element;
end procedure insert;
procedure get_element ( variable p : in position; e : out element_type ) is
begin
e := p.current_element.element;
end procedure get_element;
procedure test_null_position ( variable p : in position; is_null : out boolean ) is
begin
is_null := p.current_element = p.the_collection;
end procedure test_null_position;
procedure search ( variable c : in ordered_collection; k : in key_type;
p : out position ) is
variable current_element : ordered_collection := c.next_element;
begin
while current_element /= c
and key_of(current_element.element) < k loop
current_element := current_element.next_element;
end loop;
if current_element = c or k < key_of(current_element.element) then
p := new position_object'(c, c); -- null position
else
p := new position_object'(c, current_element);
end if;
end procedure search;
procedure find_first ( variable c : in ordered_collection; p : out position ) is
begin
p := new position_object'(c, c.next_element);
end procedure find_first;
procedure advance ( p : inout position ) is
variable is_null : boolean;
begin
test_null_position(p, is_null);
if not is_null then
p.current_element := p.current_element.next_element;
end if;
end procedure advance;
procedure delete ( p : inout position ) is
variable is_null : boolean;
begin
test_null_position(p, is_null);
if not is_null then
p.current_element.next_element.prev_element
:= p.current_element.prev_element;
p.current_element.prev_element.next_element
:= p.current_element.next_element;
p.current_element := p.current_element.next_element;
end if;
end procedure delete;
end package body «element_type_simple_name»_ordered_collection_adt;
| gpl-2.0 | fc42a7d283096795dc51d8ba9d78780d | 0.671127 | 3.937183 | false | false | false | false |
emogenet/ghdl | testsuite/vests/vhdl-ams/ashenden/compliant/sequential-statements/SR_flipflop.vhd | 4 | 1,221 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
entity SR_flipflop is
port ( S, R : in bit; Q : out bit );
end entity SR_flipflop;
--------------------------------------------------
architecture checking of SR_flipflop is
begin
set_reset : process (S, R) is
begin
assert S = '1' nand R = '1';
if S = '1' then
Q <= '1';
end if;
if R = '1' then
Q <= '0';
end if;
end process set_reset;
end architecture checking;
| gpl-2.0 | 520a13943ebdf5868211c808b77f1440 | 0.650287 | 4.003279 | false | false | false | false |
emogenet/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc156.vhd | 4 | 2,366 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc156.vhd,v 1.2 2001-10-26 16:30:11 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c04s03b02x02p17n01i00156ent IS
PORT ( ii: INOUT integer);
PROCEDURE addup (i1,i2,i3:IN INTEGER;add:IN BOOLEAN;VARIABLE i4:OUT INTEGER) IS
BEGIN
IF add THEN
i4 := (i1+i2+i3);
ELSE
i4 := (i1-i2)-i3;
END IF;
END;
END c04s03b02x02p17n01i00156ent;
ARCHITECTURE c04s03b02x02p17n01i00156arch OF c04s03b02x02p17n01i00156ent IS
BEGIN
TESTING: PROCESS
VARIABLE a1 : INTEGER := 57;
VARIABLE a2 : INTEGER := 68;
VARIABLE a3 : INTEGER := 77;
VARIABLE b1 : BIT := '1';
VARIABLE b2 : BIT := '0';
FUNCTION convb (inp:IN INTEGER) RETURN BOOLEAN IS
BEGIN
IF (inp > 0) THEN
RETURN (TRUE);
ELSE
RETURN (FALSE);
END IF;
END;
FUNCTION conv1 (inp:IN BIT) RETURN INTEGER IS
BEGIN
IF (inp = '1') THEN
RETURN (22);
ELSE
RETURN (23);
END IF;
END;
BEGIN
WAIT FOR 1 ns;
addup(i2=>conv1(b1),add=>conv1(a2),i1=>conv1(b2),i3=>a1,i4=>a1);
WAIT FOR 1 ns;
assert FALSE
report "***FAILED TEST: c04s03b02x02p17n01i00156 - Type coversion return wrong type."
severity ERROR;
wait;
END PROCESS TESTING;
END c04s03b02x02p17n01i00156arch;
| gpl-2.0 | d313f03ba308e521e978bfcba2e2ca39 | 0.629332 | 3.474302 | false | true | false | false |
ambrosef/HLx_Examples | Acceleration/memcached/regressionSims/sources/kvs_tbDriverHDLNode.vhdl | 1 | 4,846 | -------------------------------------------------------------------------------
--
-- Title : local_link_source.vhd - part of the Groucher simulation environment
--
-- Description : This code models the behavior of a local link source device
-- to drive a Grouch module with optional status and length interfaces
--
-- Files: reads from a file data and control inputs
-- if a line starts with capital W then the following number if interpreted
-- as an integer, and the program waits for this integer * cycles
-- if a line starts with a captial D then the rest is interpreted as follows:
-- data bus '' ctl signals( * - DONE - EMPTY -ALMOST)
-- the bit size of the values must be at least the size of the bus rounded to the next 4
-- and is always interpreted as hex.
-- Organization is MSB to LSB
-- length and status are optional
-- if their widths (generics S_WIDTH and L_WIDTH) are set to 0, then
-- we won't parse for them in the file
-- Interface: the processing starts after rst de-asserts
-- drives a standard tx interface (local link + len + sts)
-- Parameters: data width
-- bpr_sensitive
-- pkt_filename
--
-- ----------------------------------------------------------------------------
-- DONE is ignored....
-- DONE is ignored....
-- ----------------------------------------------------------------------------
-- Changelog:
-- 2 Control Flow Bugs fixed.
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.std_logic_arith.ALL;
USE IEEE.std_logic_unsigned.ALL;
USE IEEE.STD_LOGIC_TEXTIO.all;
LIBRARY STD;
USE STD.TEXTIO.ALL;
entity kvs_tbDriverHDLNode is
generic (
D_WIDTH : integer := 64;
BPR_SENSITIVE : Boolean := true; -- decides whether we react to backpressure or not
--PKT_FILENAME : string := "/home/kimonk/vc709sim/pkt.in.2.txt"
PKT_FILENAME : string := "pkt.in.txt"
);
port (
clk : in std_logic;
rst : in std_logic;
udp_out_ready : in std_logic;
udp_out_valid : out std_logic;
udp_out_keep : out std_logic_vector(7 downto 0);
udp_out_user : out std_logic_vector(111 downto 0);
udp_out_last : out std_logic;
udp_out_data : out std_logic_vector (63 downto 0)
);
end kvs_tbDriverHDLNode;
architecture rtl of kvs_tbDriverHDLNode is
-- read width from file- roudns each value up to the next multiple of 4
constant FD_WIDTH : integer := ((D_WIDTH-1) / 4)*4 + 4;
--signal item_consumed : std_logic;
begin
read_file_p : process
FILE data_file : TEXT OPEN READ_MODE IS PKT_FILENAME;
variable c : character;
variable wait_period : integer;
variable l : line;
variable read_dat : std_logic_vector(63 downto 0);
variable read_keep : std_logic_vector(7 downto 0);
variable read_ctl : std_logic_vector(3 downto 0);
variable item_consumed : std_logic;
variable cntCorrection : integer;
variable firstRun : integer;
--variable read_ctl_buf : std_logic_Vector(3 downto 0) := (others => '1');
begin
if (D_WIDTH=0) then
assert false report "D_WIDTH and R_WIDTH must be greater than 0" severity failure;
end if;
-- assign defaults for rest
udp_out_valid <= '0';
udp_out_last <= '0';
udp_out_data <=(others => '0');
udp_out_keep <=(others => '0');
udp_out_user <=(others => '0');
item_consumed := '0';
firstRun := 0;
wait_period := 1;
wait until CLK'event and CLK='1';
while (not endfile(data_file)) loop
READLINE(data_file, l);
READ(l, c);
case c is
when 'W' => -- wait
READ(l,wait_period);
cntCorrection := 1;
for i in 0 to wait_period -1 loop
udp_out_valid <= '0';
wait until CLK'event and CLK='1';
end loop;
when others =>
-- parse data line
HREAD(l,read_dat);
READ(l,c);--blank
HREAD(l,read_keep);
READ(l,c);--blank
HREAD(l,read_ctl);
udp_out_data <= read_dat;
udp_out_keep <= read_keep;
if (read_ctl = 1) then
udp_out_last <= '1';
else
udp_out_last <= '0';
end if;
udp_out_valid <= '1';
wait until udp_out_ready = '1' and CLK'event and CLK='1';
end case;
--wait until CLK'event and CLK='1';
end loop;
wait until CLK'event and CLK='1';
-- following delay is to ensure the last bit of data
-- is through the simulation
wait for 1000 * 1000 ns;
-- then terminate the simulation
--if (endfile(data_file)) then
-- assert false report "End of simulation." severity failure;
--end if;
end process;
end rtl; | bsd-3-clause | b0250c422f17423cdefa1cf66df3df59 | 0.563764 | 3.563235 | false | false | false | false |
emogenet/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/simulator_failure/tc78.vhd | 4 | 1,708 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc78.vhd,v 1.2 2001-10-26 16:30:30 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c04s03b01x02p10n04i00078ent IS
END c04s03b01x02p10n04i00078ent;
ARCHITECTURE c04s03b01x02p10n04i00078arch OF c04s03b01x02p10n04i00078ent IS
type int_array is array(1 to 1) of integer;
signal s : int_array := (others => 0);
BEGIN
s <= (others => 1);
s <= (others => 2);
TEST: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST:c04s03b01x02p10n04i00078 - Signal has multiple sources but is not a resolved signal."
severity ERROR;
wait;
END PROCESS TEST;
END c04s03b01x02p10n04i00078arch;
| gpl-2.0 | 6882fb1eb8f703de973c47c92fb79352 | 0.66452 | 3.721133 | false | true | false | false |
emogenet/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc154.vhd | 4 | 2,361 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc154.vhd,v 1.2 2001-10-26 16:29:41 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
package c04s03b02x02p16n01i00154pkg is
procedure P1 (a : in integer; b: inout integer);
function F1 (I1 : in integer) return real;
function F2 (I2 : in real) return integer;
end c04s03b02x02p16n01i00154pkg;
package body c04s03b02x02p16n01i00154pkg is
procedure P1 (a : in integer; b: inout integer) is
begin
b := a;
end P1;
function F1 (I1 : in integer) return real is
begin
return 10.0;
end F1;
function F2 (I2 : in real) return integer is
begin
return 10;
end F2;
end c04s03b02x02p16n01i00154pkg;
use work.c04s03b02x02p16n01i00154pkg.all;
ENTITY c04s03b02x02p16n01i00154ent IS
END c04s03b02x02p16n01i00154ent;
ARCHITECTURE c04s03b02x02p16n01i00154arch OF c04s03b02x02p16n01i00154ent IS
BEGIN
TESTING: PROCESS
variable x : real := 1.0;
BEGIN
P1 (10, F1(b) => F2(x)); -- No_failure_here
assert NOT(F2(x) = 10)
report "***PASSED TEST: c04s03b02x02p16n01i00154"
severity NOTE;
assert (F2(x) = 10)
report "***FAILED TEST: c04s03b02x02p16n01i00154 - Types of the actuals match those of the formals test failed.."
severity ERROR;
wait;
END PROCESS TESTING;
END c04s03b02x02p16n01i00154arch;
| gpl-2.0 | 89cdb3f44242fc35b483562b88fbe464 | 0.676832 | 3.22101 | false | true | false | false |
gmsanchez/OrgComp | TP_02/TB_Cont32bSinc.vhd | 1 | 2,972 | -- Ejercicio 3(a), contador síncrono
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE work.txt_util.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY TB_Cont32bSinc IS
END TB_Cont32bSinc;
ARCHITECTURE behavior OF TB_Cont32bSinc IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT Cont32bSinc
PORT(
CLK : IN std_logic;
RST : IN std_logic;
LOAD : IN std_logic;
CE : IN std_logic;
UND : IN std_logic;
DIN : IN std_logic_vector(31 downto 0);
Q : BUFFER std_logic_vector(31 downto 0)
);
END COMPONENT;
--Inputs
signal CLK : std_logic := '0';
signal RST : std_logic := '0';
signal LOAD : std_logic := '0';
signal CE : std_logic := '0';
signal UND : std_logic := '0';
signal DIN : std_logic_vector(31 downto 0) := (others => '0');
--Outputs
signal Q : std_logic_vector(31 downto 0);
-- Clock period definitions
constant CLK_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: Cont32bSinc PORT MAP (
CLK => CLK,
RST => RST,
LOAD => LOAD,
CE => CE,
UND => UND,
DIN => DIN,
Q => Q
);
-- Clock process definitions
CLK_process :process
begin
CLK <= '0';
wait for CLK_period/2;
CLK <= '1';
wait for CLK_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
-- check initial states
wait for 12 ns;
DIN<=x"00000000";
RST<='1';
LOAD<='0';
UND<='0';
CE <= '0';
wait for 10 ns;
RST <= '0';
wait for 40 ns; -- debe mantenerse sin contar
DIN <= x"0000005A";
CE<='1';
wait for 20 ns;
LOAD <= '1';
wait for 10 ns;
LOAD <= '0';
wait for 100 ns;
UND <= '1';
wait;
end process;
corr_proc: process(CLK)
variable theTime : time;
begin
theTime := now;
if theTime=20000 ps then
assert (Q=x"00000000")
report "Resultado erroneo a los " & time'image(theTime) & " Q=" & str(Q)
severity ERROR;
end if;
if theTime=70000 ps then
assert (Q=x"fffffffc")
report "Resultado erroneo a los " & time'image(theTime) & " Q=" & str(Q)
severity ERROR;
end if;
if theTime=80000 ps then
assert (Q=x"fffffff8")
report "Resultado erroneo a los " & time'image(theTime) & " Q=" & str(Q)
severity ERROR;
end if;
if theTime=90000 ps then
assert (Q=x"0000005a")
report "Resultado erroneo a los " & time'image(theTime) & " Q=" & str(Q)
severity ERROR;
end if;
if theTime=120000 ps then
assert (Q=x"0000004e")
report "Resultado erroneo a los " & time'image(theTime) & " Q=" & str(Q)
severity ERROR;
end if;
if theTime=210000 ps then
assert (Q=x"0000003a")
report "Resultado erroneo a los " & time'image(theTime) & " Q=" & str(Q)
severity ERROR;
end if;
end process;
END;
| gpl-2.0 | ce6c62fa569aefa12b0ab9d8edd9b03e | 0.593739 | 3.078756 | false | false | false | false |
emogenet/ghdl | testsuite/vests/vhdl-ams/ashenden/compliant/frequency-modeling/opamp_2pole.vhd | 4 | 2,331 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
library ieee; use ieee.math_real.all;
library ieee_proposed; use ieee_proposed.electrical_systems.all;
entity opamp_2pole is
port ( terminal in_pos, in_neg, output : electrical );
end entity opamp_2pole;
----------------------------------------------------------------
architecture dot of opamp_2pole is
constant A : real := 1.0e6; -- open loop gain
constant fp1 : real := 5.0; -- first pole
constant fp2 : real := 9.0e5; -- second pole
constant tp1 : real := 1.0 / (fp1 * math_2_pi); -- first time constant
constant tp2 : real := 1.0 / (fp2 * math_2_pi); -- second time constant
quantity v_in across in_pos to in_neg;
quantity v_out across i_out through output;
begin
v_in == (tp1 * tp2) * v_out'dot'dot / A
+ (tp1 + tp2) * v_out'dot / A + v_out / A;
end architecture dot;
----------------------------------------------------------------
architecture ltf of opamp_2pole is
constant A : real := 1.0e6; -- open loop gain
constant fp1 : real := 5.0; -- first pole (Hz)
constant fp2 : real := 9.0e5; -- second pole (Hz)
constant wp1 : real := fp1 * math_2_pi; -- first pole (rad/s)
constant wp2 : real := fp2 * math_2_pi; -- second pole (rad/s)
constant num : real_vector := (0 => wp1 * wp2 * A);
constant den : real_vector := (wp1 * wp2, wp1 + wp2, 1.0);
quantity v_in across in_pos to in_neg;
quantity v_out across i_out through output;
begin
v_out == v_in'ltf(num, den);
end architecture ltf;
| gpl-2.0 | b3f73e35a0f4e564dbcd0b3d2690fd24 | 0.616903 | 3.542553 | false | false | false | false |
emogenet/ghdl | testsuite/gna/perf02/tb.vhd | 2 | 11,154 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library std;
use std.textio.all;
entity tb is
end tb;
architecture augh of tb is
constant simu_max_cycles : natural := 100000;
constant simu_disp_cycles : std_logic := '1';
constant simu_err_end_in : std_logic := '0';
constant reset_cycles : natural := 4;
component top is
port (
clock : in std_logic;
reset : in std_logic;
start : in std_logic;
stdin_rdy : out std_logic;
stdin_ack : in std_logic;
stdout_data : out std_logic_vector(31 downto 0);
stdout_rdy : out std_logic;
stdout_ack : in std_logic;
stdin_data : in std_logic_vector(31 downto 0)
);
end component;
signal clock : std_logic := '0';
signal reset : std_logic := '0';
signal start : std_logic := '0';
signal clock_next : std_logic := '0';
-- Access 'clock' model 'clock'
-- Access 'reset' model 'reset'
-- Access 'start' model 'start'
-- Access 'stdin' model 'fifo_in'
signal stdin_data : std_logic_vector(31 downto 0) := (others => '0');
signal stdin_rdy : std_logic := '0';
signal stdin_ack : std_logic := '0';
signal stdin_vector_idx : natural := 0;
signal stdin_vector : std_logic_vector(31 downto 0) := (others => '0');
-- Test vectors
constant stdin_vectors_nb : natural := 100;
type stdin_vec_type is array (0 to stdin_vectors_nb-1) of std_logic_vector(31 downto 0);
constant stdin_vectors : stdin_vec_type := (
X"00000044", X"00000044", X"00000044", X"00000044", X"00000044", X"00000044", X"00000044", X"00000044",
X"00000044", X"00000044", X"00000044", X"00000044", X"00000044", X"00000044", X"00000044", X"00000044",
X"00000044", X"00000043", X"00000043", X"00000043", X"00000043", X"00000043", X"00000043", X"00000043",
X"00000042", X"00000042", X"00000042", X"00000042", X"00000042", X"00000042", X"00000041", X"00000041",
X"00000041", X"00000041", X"00000041", X"00000040", X"00000040", X"00000040", X"00000040", X"00000040",
X"00000040", X"00000040", X"00000040", X"0000003f", X"0000003f", X"0000003f", X"0000003f", X"0000003f",
X"0000003e", X"0000003e", X"0000003e", X"0000003e", X"0000003e", X"0000003e", X"0000003d", X"0000003d",
X"0000003d", X"0000003d", X"0000003d", X"0000003d", X"0000003c", X"0000003c", X"0000003c", X"0000003c",
X"0000003c", X"0000003c", X"0000003c", X"0000003c", X"0000003c", X"0000003b", X"0000003b", X"0000003b",
X"0000003b", X"0000003b", X"0000003b", X"0000003b", X"0000003b", X"0000003b", X"0000003b", X"0000003b",
X"0000003b", X"0000003b", X"0000003b", X"0000003b", X"0000003b", X"0000003b", X"0000003b", X"0000003b",
X"0000003b", X"0000003b", X"0000003b", X"0000003b", X"0000003c", X"0000003c", X"0000003c", X"0000003c",
X"0000003c", X"0000003c", X"0000003c", X"0000003c"
);
-- Access 'stdout' model 'fifo_out'
signal stdout_data : std_logic_vector(31 downto 0) := (others => '0');
signal stdout_rdy : std_logic := '0';
signal stdout_ack : std_logic := '0';
signal stdout_vector_idx : natural := 0;
signal stdout_vector : std_logic_vector(31 downto 0) := (others => '0');
-- Test vectors
constant stdout_vectors_nb : natural := 150;
type stdout_vec_type is array (0 to stdout_vectors_nb-1) of std_logic_vector(31 downto 0);
constant stdout_vectors : stdout_vec_type := (
X"000000fd", X"000000de", X"00000077", X"000000ba", X"000000f4", X"00000092", X"00000020", X"000000a0",
X"000000ec", X"000000ed", X"000000ee", X"000000f0", X"000000f1", X"000000f1", X"000000f2", X"000000f3",
X"000000f4", X"000000f4", X"000000f3", X"000000f5", X"000000f5", X"000000f5", X"000000f6", X"000000f6",
X"000000f6", X"000000f7", X"000000f8", X"000000f6", X"000000f7", X"000000f8", X"000000f7", X"000000f8",
X"000000f8", X"000000f6", X"000000f8", X"000000f8", X"000000f7", X"000000f9", X"000000f9", X"000000f8",
X"000000f8", X"000000f8", X"000000f7", X"000000fa", X"000000fb", X"000000fb", X"000000fa", X"000000fb",
X"000000fb", X"000000fb", X"00000000", X"00000000", X"00000000", X"00000000", X"ffffffff", X"00000000",
X"00000000", X"ffffffff", X"00000000", X"00000000", X"ffffffff", X"ffffffff", X"00000000", X"00000000",
X"ffffffff", X"fffffffd", X"fffffffe", X"fffffffd", X"ffffffff", X"fffffffc", X"00000000", X"ffffffff",
X"ffffffff", X"fffffffb", X"00000000", X"00000000", X"ffffffff", X"00000004", X"0000000b", X"00000009",
X"0000000b", X"0000000d", X"00000011", X"00000010", X"00000014", X"00000013", X"00000016", X"00000013",
X"00000016", X"00000017", X"0000001a", X"0000001a", X"0000001d", X"0000001e", X"00000021", X"0000001f",
X"0000001e", X"0000001a", X"0000001e", X"00000020", X"00000026", X"00000025", X"00000026", X"00000023",
X"00000025", X"00000024", X"00000027", X"00000025", X"00000028", X"00000028", X"0000002b", X"00000029",
X"0000002d", X"0000002e", X"0000002f", X"00000028", X"00000027", X"00000027", X"0000002d", X"0000002f",
X"00000031", X"0000002d", X"0000002d", X"0000002c", X"00000031", X"00000030", X"0000002f", X"00000028",
X"0000002a", X"0000002d", X"00000033", X"00000030", X"0000002e", X"00000029", X"0000002d", X"00000030",
X"00000037", X"00000035", X"00000035", X"00000030", X"00000030", X"0000002e", X"00000031", X"0000002e",
X"0000002f", X"0000002c", X"00000031", X"00000034", X"0000003a", X"0000003a"
);
signal clock_counter : natural := 0;
signal clock_counter_stop : natural := 0;
signal errors_nb : natural := 0;
-- Defined in VHDL 2008, not handled by GHDL
function to_string(sv: std_logic_vector) return string is
variable bv: bit_vector(sv'range) := to_bitvector(sv);
variable lp: line;
begin
write(lp, bv);
return lp.all;
end;
begin
-- Instantiation of the main component
top_i : top port map (
-- Access 'clock' model 'clock'
clock => clock,
-- Access 'reset' model 'reset'
reset => reset,
-- Access 'start' model 'start'
start => start,
-- Access 'stdin' model 'fifo_in'
stdin_data => stdin_data,
stdin_rdy => stdin_rdy,
stdin_ack => stdin_ack,
-- Access 'stdout' model 'fifo_out'
stdout_data => stdout_data,
stdout_rdy => stdout_rdy,
stdout_ack => stdout_ack
);
-- Functionality for top-level access 'clock' model 'clock'
-- Generation of clock: 100MHz (note: arbitrary value)
clock <= clock_next after 5 ns;
clock_next <= not clock when clock_counter_stop = 0 or clock_counter <= clock_counter_stop else '0';
-- Clock counter and global messages
process (clock)
-- To print simulation messages
variable l : line;
begin
-- Increment clock counter
if rising_edge(clock) then
clock_counter <= clock_counter + 1;
if false and simu_disp_cycles = '1' then
-- Write simulation message
write(l, string'("INFO clock cycle "));
write(l, clock_counter);
writeline(output, l);
end if;
end if;
-- Messages
if falling_edge(clock) then
if clock_counter > simu_max_cycles then
report "ERROR Too many cycles simulated. Stopping simulation." severity failure;
end if;
if clock_counter < reset_cycles then
report "INFO Reset" severity note;
end if;
if clock_counter = reset_cycles then
report "INFO Start" severity note;
end if;
end if;
end process;
-- Functionality for top-level access 'reset' model 'reset'
-- Generation of reset
reset <= '1' when clock_counter < reset_cycles else '0';
-- Functionality for top-level access 'start' model 'start'
-- Generation of start
start <= '1';
-- Functionality for top-level access 'stdin' model 'fifo_in'
-- FIFO stdin
-- Sending inputs
stdin_vector <= stdin_vectors(stdin_vector_idx) when stdin_vector_idx < stdin_vectors_nb else (others => '0');
stdin_data <= stdin_vector(31 downto 0);
stdin_ack <= '1' when reset = '0' and stdin_vector_idx < stdin_vectors_nb else '0';
process (clock)
-- To print simulation messages
variable l : line;
begin
if rising_edge(clock) then
if stdin_vector_idx < stdin_vectors_nb then
if stdin_rdy = '1' and stdin_ack = '1' and reset = '0' then
-- Write simulation message
write(l, string'("INFO Input vector "));
write(l, stdin_vector_idx);
write(l, string'(" at cycle "));
write(l, clock_counter);
writeline(output, l);
if stdin_vector_idx = 0 then
write(l, string'("INFO First input vector sent at clock cycle "));
write(l, clock_counter);
writeline(output, l);
end if;
if stdin_vector_idx = stdin_vectors_nb - 1 then
write(l, string'("INFO Last input vector sent at clock cycle "));
write(l, clock_counter);
writeline(output, l);
end if;
-- Increase vector index
stdin_vector_idx <= stdin_vector_idx + 1;
end if; -- Handshake
else
if stdin_rdy = '1' and reset = '0' then
if simu_err_end_in = '1' then
report "ERROR Out of input vectors. Stopping simulation." severity failure;
end if;
end if; -- Handshake
end if;
end if;
end process;
-- Functionality for top-level access 'stdout' model 'fifo_out'
-- FIFO stdout
-- Checking outputs
-- Always enable output FIFO
stdout_ack <= '1' when stdout_vector_idx < stdout_vectors_nb and reset = '0' else '0';
stdout_vector <= stdout_vectors(stdout_vector_idx) when stdout_vector_idx < stdout_vectors_nb else (others => '0');
-- Check outputs
process (clock)
variable l : line;
begin
if rising_edge(clock) then
if stdout_vector_idx < stdout_vectors_nb then
if stdout_rdy = '1' and stdout_ack = '1' and reset = '0' then
if stdout_data = stdout_vector(31 downto 0) then
-- The vector is verified
write(l, string'("INFO Output nb "));
write(l, stdout_vector_idx);
write(l, string'(" at cycle "));
write(l, clock_counter);
write(l, string'(" (check OK)"));
write(l, string'(" Obtained "));
write(l, to_string(stdout_data));
writeline(output, l);
else
-- An error is detected
write(l, string'("ERROR Output nb "));
write(l, stdout_vector_idx);
write(l, string'(" at cycle "));
write(l, clock_counter);
writeline(output, l);
write(l, string'(" Obtained "));
write(l, to_string(stdout_data));
writeline(output, l);
write(l, string'(" Expected "));
write(l, to_string(stdout_vector(31 downto 0)));
writeline(output, l);
errors_nb <= errors_nb + 1;
--report "ERROR A simulation error was found." severity failure;
end if;
if stdout_vector_idx = stdout_vectors_nb - 1 then
write(l, string'("INFO Last output vector read at cycle "));
write(l, clock_counter);
writeline(output, l);
report "INFO Stopping simulation." severity note;
clock_counter_stop <= clock_counter + 3;
end if;
-- Increase vector index
stdout_vector_idx <= stdout_vector_idx + 1;
end if; -- FIFO handshake
else
-- All vectors have been read
if errors_nb > 0 then
write(l, string'("ERROR Number of errors found : "));
write(l, errors_nb);
writeline(output, l);
report "ERROR Simulation errors were found." severity failure;
end if;
end if; -- Check all vectors read
end if; -- Clock
end process;
end augh;
| gpl-2.0 | 4e3c0ead2d6c7c84825ca49baf03e724 | 0.651784 | 3.035102 | false | false | false | false |
hacklabmikkeli/rough-boy | phase_gen.vhdl | 2 | 1,411 | --
-- Knobs Galore - a free phase distortion synthesizer
-- Copyright (C) 2015 Ilmo Euro
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.common.all;
entity phase_gen is
port (EN: in std_logic
;CLK: in std_logic
;PHASE_IN: in time_signal
;PHASE_OUT: out time_signal
)
;
end entity;
architecture phase_gen_impl of phase_gen is
signal s1_phase_out_buf: time_signal := (others => '0');
begin
process(CLK)
begin
if EN = '1' and rising_edge(CLK) then
s1_phase_out_buf <= PHASE_IN + 1;
end if;
end process;
PHASE_OUT <= s1_phase_out_buf;
end architecture;
| gpl-3.0 | 6e569045935dc4c170b7a04c8a9e821a | 0.639263 | 3.703412 | false | false | false | false |
emogenet/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc746.vhd | 4 | 9,354 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc746.vhd,v 1.2 2001-10-26 16:29:59 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
package c01s01b01x01p05n02i00746pkg is
type boolean_vector is array (natural range <>) of boolean;
type severity_level_vector is array (natural range <>) of severity_level;
type integer_vector is array (natural range <>) of integer;
type real_vector is array (natural range <>) of real;
type time_vector is array (natural range <>) of time;
type natural_vector is array (natural range <>) of natural;
type positive_vector is array (natural range <>) of positive;
type record_std_package is record
a:boolean;
b:bit;
c:character;
d:severity_level;
e:integer;
f:real;
g:time;
h:natural;
i:positive;
j:string(1 to 7);
k:bit_vector(0 to 3);
end record;
type array_rec_std is array (integer range <>) of record_std_package;
function F1(inp : boolean_vector(0 to 15)) return boolean ;
function F2(inp : bit_vector(0 to 3)) return bit ;
function F3(inp : string(1 to 7)) return character ;
function F4(inp : severity_level_vector(0 to 15)) return severity_level ;
function F5(inp : integer_vector(0 to 15)) return integer ;
function F6(inp : real_vector(0 to 15)) return real ;
function F7(inp : time_vector(0 to 15)) return time ;
function F8(inp : natural_vector(0 to 15)) return natural ;
function F9(inp : positive_vector(0 to 15)) return positive ;
function F10(inp: array_rec_std(0 to 7)) return record_std_package ;
end c01s01b01x01p05n02i00746pkg;
package body c01s01b01x01p05n02i00746pkg is
function F1(inp : boolean_vector(0 to 15)) return boolean is
begin
for i in 0 to 15 loop
assert(inp(i) = true) report"wrong initialization of S1" severity error;
end loop;
return false;
end F1;
function F2(inp : bit_vector(0 to 3)) return bit is
begin
for i in 0 to 3 loop
assert(inp(i) = '0') report"wrong initialization of S2" severity error;
end loop;
return '0';
end F2;
function F3(inp : string(1 to 7)) return character is
begin
for i in 1 to 7 loop
assert(inp(i) = 's') report"wrong initialization of S3" severity error;
end loop;
return 'h';
end F3;
function F4(inp : severity_level_vector(0 to 15)) return severity_level is
begin
for i in 0 to 15 loop
assert(inp(i) = note) report"wrong initialization of S4" severity error;
end loop;
return error;
end F4;
function F5(inp : integer_vector(0 to 15)) return integer is
begin
for i in 0 to 15 loop
assert(inp(i) = 3) report"wrong initialization of S5" severity error;
end loop;
return 6;
end F5;
function F6(inp : real_vector(0 to 15)) return real is
begin
for i in 0 to 15 loop
assert(inp(i) = 3.0) report"wrong initialization of S6" severity error;
end loop;
return 6.0;
end F6;
function F7(inp : time_vector(0 to 15)) return time is
begin
for i in 0 to 15 loop
assert(inp(i) = 3 ns) report"wrong initialization of S7" severity error;
end loop;
return 6 ns;
end F7;
function F8(inp : natural_vector(0 to 15)) return natural is
begin
for i in 0 to 15 loop
assert(inp(i) = 1) report"wrong initialization of S8" severity error;
end loop;
return 6;
end F8;
function F9(inp : positive_vector(0 to 15)) return positive is
begin
for i in 0 to 15 loop
assert(inp(i) = 1) report"wrong initialization of S9" severity error;
end loop;
return 6;
end F9;
function F10(inp : array_rec_std(0 to 7)) return record_std_package is
begin
for i in 0 to 7 loop
assert(inp(i) = (true,'1','s',note,3,3.0,3 ns, 1,1,"sssssss","0000")) report"wrong initialization of S10" severity error;
end loop;
return (false,'0','s',error,5,5.0,5 ns,5,5,"metrics","1100");
end F10;
end c01s01b01x01p05n02i00746pkg;
use work.c01s01b01x01p05n02i00746pkg.all;
ENTITY c01s01b01x01p05n02i00746ent IS
generic(
zero : integer := 0;
one : integer := 1;
two : integer := 2;
three: integer := 3;
four : integer := 4;
five : integer := 5;
six : integer := 6;
seven: integer := 7;
eight: integer := 8;
nine : integer := 9;
fifteen:integer:= 15;
C1 : boolean := true;
C2 : bit := '1';
C3 : character := 's';
C4 : severity_level:= note;
C5 : integer := 3;
C6 : real := 3.0;
C7 : time := 3 ns;
C8 : natural := 1;
C9 : positive := 1;
C10 : string := "sssssss";
C11 : bit_vector := B"0000";
C48 : record_std_package := (true,'1','s',note,3,3.0,3 ns,1,1,"sssssss","0000")
);
port(
S1 : boolean_vector(zero to fifteen) := (others => C1);
S2 : severity_level_vector(zero to fifteen) := (others => C4);
S3 : integer_vector(zero to fifteen) := (others => C5);
S4 : real_vector(zero to fifteen) := (others => C6);
S5 : time_vector (zero to fifteen) := (others => C7);
S6 : natural_vector(zero to fifteen) := (others => C8);
S7 : positive_vector(zero to fifteen) := (others => C9);
S8 : string(one to seven) := C10;
S9 : bit_vector(zero to three) := C11;
S48: array_rec_std(zero to seven) := (others => C48)
);
END c01s01b01x01p05n02i00746ent;
ARCHITECTURE c01s01b01x01p05n02i00746arch OF c01s01b01x01p05n02i00746ent IS
BEGIN
TESTING: PROCESS
variable var1 : boolean;
variable var4 : severity_level;
variable var5 : integer;
variable var6 : real;
variable var7 : time;
variable var8 : natural;
variable var9 : positive;
variable var2 : bit;
variable var3 : character;
variable var48: record_std_package;
BEGIN
var1 := F1(S1);
var2 := F2(S9);
var3 := F3(S8);
var4 := F4(S2);
var5 := F5(S3);
var6 := F6(S4);
var7 := F7(S5);
var8 := F8(S6);
var9 := F9(S7);
var48 := F10(S48);
wait for 1 ns;
assert(var1 = false) report "wrong assignment in the function F1" severity error;
assert(var2 = '0') report "wrong assignment in the function F2" severity error;
assert(var3 = 'h') report "wrong assignment in the function F3" severity error;
assert(var4 = error) report "wrong assignment in the function F4" severity error;
assert(var5 = 6) report "wrong assignment in the function F5" severity error;
assert(var6 = 6.0) report "wrong assignment in the function F6" severity error;
assert(var7 = 6 ns) report "wrong assignment in the function F7" severity error;
assert(var8 = 6) report "wrong assignment in the function F8" severity error;
assert(var9 = 6) report "wrong assignment in the function F9" severity error;
assert(var48 = (false,'0','s',error,5,5.0,5 ns,5,5,"metrics","1100")) report "wrong assignment in the function F10" severity error;
assert NOT( var1 = F1(S1) and
var2 = F2(S9) and
var3 = F3(S8) and
var4 = F4(S2) and
var5 = F5(S3) and
var6 = F6(S4) and
var7 = F7(S5) and
var8 = F8(S6) and
var9 = F9(S7) and
var48 = F10(S48) )
report "***PASSED TEST: c01s01b01x01p05n02i00746"
severity NOTE;
assert ( var1 = F1(S1) and
var2 = F2(S9) and
var3 = F3(S8) and
var4 = F4(S2) and
var5 = F5(S3) and
var6 = F6(S4) and
var7 = F7(S5) and
var8 = F8(S6) and
var9 = F9(S7) and
var48 = F10(S48) )
report "***FAILED TEST: c01s01b01x01p05n02i00746 - Generic can be used to specify the size of ports."
severity ERROR;
wait;
END PROCESS TESTING;
END c01s01b01x01p05n02i00746arch;
| gpl-2.0 | 59cf327c1ba47571eea0d54d3a07a556 | 0.587342 | 3.38913 | false | false | false | false |
emogenet/ghdl | testsuite/gna/bug040/shr_212.vhd | 2 | 1,108 | library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity shr_212 is
port (
output : out std_logic_vector(31 downto 0);
input : in std_logic_vector(31 downto 0);
shift : in std_logic_vector(5 downto 0);
padding : in std_logic
);
end shr_212;
architecture augh of shr_212 is
signal tmp_padding : std_logic;
signal tmp_result : std_logic_vector(32 downto 0);
-- Little utility functions to make VHDL syntactically correct
-- with the syntax to_integer(unsigned(vector)) when 'vector' is a std_logic.
-- This happens when accessing arrays with <= 2 cells, for example.
function to_integer(B: std_logic) return integer is
variable V: std_logic_vector(0 to 0);
begin
V(0) := B;
return to_integer(unsigned(V));
end;
function to_integer(V: std_logic_vector) return integer is
begin
return to_integer(unsigned(V));
end;
begin
-- Temporary signals
tmp_padding <= padding;
tmp_result <= std_logic_vector(shift_right( unsigned(padding & input), to_integer(shift) ));
-- The output
output <= tmp_result(31 downto 0);
end architecture;
| gpl-2.0 | ffa4e8069c004d3a93d698d3d04ca978 | 0.704874 | 3.086351 | false | false | false | false |
emogenet/ghdl | libraries/ieee2008/math_complex.vhdl | 4 | 34,169 | -- --------------------------------------------------------------------
--
-- Copyright © 2008 by IEEE. All rights reserved.
--
-- This source file is an essential part of IEEE Std 1076-2008,
-- IEEE Standard VHDL Language Reference Manual. This source file may not be
-- copied, sold, or included with software that is sold without written
-- permission from the IEEE Standards Department. This source file may be
-- copied for individual use between licensed users. This source file is
-- provided on an AS IS basis. The IEEE disclaims ANY WARRANTY EXPRESS OR
-- IMPLIED INCLUDING ANY WARRANTY OF MERCHANTABILITY AND FITNESS FOR USE
-- FOR A PARTICULAR PURPOSE. The user of the source file shall indemnify
-- and hold IEEE harmless from any damages or liability arising out of the
-- use thereof.
--
-- Title : Standard VHDL Mathematical Packages
-- : (MATH_COMPLEX package declaration)
-- :
-- Library : This package shall be compiled into a library
-- : symbolically named IEEE.
-- :
-- Developers: IEEE DASC VHDL Mathematical Packages Working Group
-- :
-- Purpose : This package defines a standard for designers to use in
-- : describing VHDL models that make use of common COMPLEX
-- : constants and common COMPLEX mathematical functions and
-- : operators.
-- :
-- Limitation: The values generated by the functions in this package
-- : may vary from platform to platform, and the precision
-- : of results is only guaranteed to be the minimum required
-- : by IEEE Std 1076-2008.
-- :
-- Note : This package may be modified to include additional data
-- : required by tools, but it must in no way change the
-- : external interfaces or simulation behavior of the
-- : description. It is permissible to add comments and/or
-- : attributes to the package declarations, but not to change
-- : or delete any original lines of the package declaration.
-- : The package body may be changed only in accordance with
-- : the terms of Clause 16 of this standard.
-- :
-- --------------------------------------------------------------------
-- $Revision: 1220 $
-- $Date: 2008-04-10 17:16:09 +0930 (Thu, 10 Apr 2008) $
-- --------------------------------------------------------------------
use WORK.MATH_REAL.all;
package MATH_COMPLEX is
constant CopyRightNotice : STRING
:= "Copyright 2008 IEEE. All rights reserved.";
--
-- Type Definitions
--
type COMPLEX is
record
RE : REAL; -- Real part
IM : REAL; -- Imaginary part
end record;
subtype POSITIVE_REAL is REAL range 0.0 to REAL'high;
subtype PRINCIPAL_VALUE is REAL range -MATH_PI to MATH_PI;
type COMPLEX_POLAR is
record
MAG : POSITIVE_REAL; -- Magnitude
ARG : PRINCIPAL_VALUE; -- Angle in radians; -MATH_PI is illegal
end record;
--
-- Constant Definitions
--
constant MATH_CBASE_1 : COMPLEX := COMPLEX'(1.0, 0.0);
constant MATH_CBASE_J : COMPLEX := COMPLEX'(0.0, 1.0);
constant MATH_CZERO : COMPLEX := COMPLEX'(0.0, 0.0);
--
-- Overloaded equality and inequality operators for COMPLEX_POLAR
-- (equality and inequality operators for COMPLEX are predefined)
--
function "=" (L : in COMPLEX_POLAR; R : in COMPLEX_POLAR) return BOOLEAN;
-- Purpose:
-- Returns TRUE if L is equal to R and returns FALSE otherwise
-- Special values:
-- COMPLEX_POLAR'(0.0, X) = COMPLEX_POLAR'(0.0, Y) returns TRUE
-- regardless of the value of X and Y.
-- Domain:
-- L in COMPLEX_POLAR and L.ARG /= -MATH_PI
-- R in COMPLEX_POLAR and R.ARG /= -MATH_PI
-- Error conditions:
-- Error if L.ARG = -MATH_PI
-- Error if R.ARG = -MATH_PI
-- Range:
-- "="(L,R) is either TRUE or FALSE
-- Notes:
-- None
function "/=" (L : in COMPLEX_POLAR; R : in COMPLEX_POLAR) return BOOLEAN;
-- Purpose:
-- Returns TRUE if L is not equal to R and returns FALSE
-- otherwise
-- Special values:
-- COMPLEX_POLAR'(0.0, X) /= COMPLEX_POLAR'(0.0, Y) returns
-- FALSE regardless of the value of X and Y.
-- Domain:
-- L in COMPLEX_POLAR and L.ARG /= -MATH_PI
-- R in COMPLEX_POLAR and R.ARG /= -MATH_PI
-- Error conditions:
-- Error if L.ARG = -MATH_PI
-- Error if R.ARG = -MATH_PI
-- Range:
-- "/="(L,R) is either TRUE or FALSE
-- Notes:
-- None
--
-- Function Declarations
--
function CMPLX(X : in REAL; Y : in REAL := 0.0) return COMPLEX;
-- Purpose:
-- Returns COMPLEX number X + iY
-- Special values:
-- None
-- Domain:
-- X in REAL
-- Y in REAL
-- Error conditions:
-- None
-- Range:
-- CMPLX(X,Y) is mathematically unbounded
-- Notes:
-- None
function GET_PRINCIPAL_VALUE(X : in REAL) return PRINCIPAL_VALUE;
-- Purpose:
-- Returns principal value of angle X; X in radians
-- Special values:
-- None
-- Domain:
-- X in REAL
-- Error conditions:
-- None
-- Range:
-- -MATH_PI < GET_PRINCIPAL_VALUE(X) <= MATH_PI
-- Notes:
-- None
function COMPLEX_TO_POLAR(Z : in COMPLEX) return COMPLEX_POLAR;
-- Purpose:
-- Returns principal value COMPLEX_POLAR of Z
-- Special values:
-- COMPLEX_TO_POLAR(MATH_CZERO) = COMPLEX_POLAR'(0.0, 0.0)
-- COMPLEX_TO_POLAR(Z) = COMPLEX_POLAR'(ABS(Z.IM),
-- SIGN(Z.IM)*MATH_PI_OVER_2) if Z.RE = 0.0
-- Domain:
-- Z in COMPLEX
-- Error conditions:
-- None
-- Range:
-- result.MAG >= 0.0
-- -MATH_PI < result.ARG <= MATH_PI
-- Notes:
-- None
function POLAR_TO_COMPLEX(Z : in COMPLEX_POLAR) return COMPLEX;
-- Purpose:
-- Returns COMPLEX value of Z
-- Special values:
-- None
-- Domain:
-- Z in COMPLEX_POLAR and Z.ARG /= -MATH_PI
-- Error conditions:
-- Error if Z.ARG = -MATH_PI
-- Range:
-- POLAR_TO_COMPLEX(Z) is mathematically unbounded
-- Notes:
-- None
function "ABS"(Z : in COMPLEX) return POSITIVE_REAL;
-- Purpose:
-- Returns absolute value (magnitude) of Z
-- Special values:
-- None
-- Domain:
-- Z in COMPLEX
-- Error conditions:
-- None
-- Range:
-- ABS(Z) is mathematically unbounded
-- Notes:
-- ABS(Z) = SQRT(Z.RE*Z.RE + Z.IM*Z.IM)
function "ABS"(Z : in COMPLEX_POLAR) return POSITIVE_REAL;
-- Purpose:
-- Returns absolute value (magnitude) of Z
-- Special values:
-- None
-- Domain:
-- Z in COMPLEX_POLAR and Z.ARG /= -MATH_PI
-- Error conditions:
-- Error if Z.ARG = -MATH_PI
-- Range:
-- ABS(Z) >= 0.0
-- Notes:
-- ABS(Z) = Z.MAG
function ARG(Z : in COMPLEX) return PRINCIPAL_VALUE;
-- Purpose:
-- Returns argument (angle) in radians of the principal
-- value of Z
-- Special values:
-- ARG(Z) = 0.0 if Z.RE >= 0.0 and Z.IM = 0.0
-- ARG(Z) = SIGN(Z.IM)*MATH_PI_OVER_2 if Z.RE = 0.0
-- ARG(Z) = MATH_PI if Z.RE < 0.0 and Z.IM = 0.0
-- Domain:
-- Z in COMPLEX
-- Error conditions:
-- None
-- Range:
-- -MATH_PI < ARG(Z) <= MATH_PI
-- Notes:
-- ARG(Z) = ARCTAN(Z.IM, Z.RE)
function ARG(Z : in COMPLEX_POLAR) return PRINCIPAL_VALUE;
-- Purpose:
-- Returns argument (angle) in radians of the principal
-- value of Z
-- Special values:
-- None
-- Domain:
-- Z in COMPLEX_POLAR and Z.ARG /= -MATH_PI
-- Error conditions:
-- Error if Z.ARG = -MATH_PI
-- Range:
-- -MATH_PI < ARG(Z) <= MATH_PI
-- Notes:
-- ARG(Z) = Z.ARG
function "-" (Z : in COMPLEX) return COMPLEX;
-- Purpose:
-- Returns unary minus of Z
-- Special values:
-- None
-- Domain:
-- Z in COMPLEX
-- Error conditions:
-- None
-- Range:
-- "-"(Z) is mathematically unbounded
-- Notes:
-- Returns -x -jy for Z= x + jy
function "-" (Z : in COMPLEX_POLAR) return COMPLEX_POLAR;
-- Purpose:
-- Returns principal value of unary minus of Z
-- Special values:
-- "-"(Z) = COMPLEX_POLAR'(Z.MAG, MATH_PI) if Z.ARG = 0.0
-- Domain:
-- Z in COMPLEX_POLAR and Z.ARG /= -MATH_PI
-- Error conditions:
-- Error if Z.ARG = -MATH_PI
-- Range:
-- result.MAG >= 0.0
-- -MATH_PI < result.ARG <= MATH_PI
-- Notes:
-- Returns COMPLEX_POLAR'(Z.MAG, Z.ARG - SIGN(Z.ARG)*MATH_PI) if
-- Z.ARG /= 0.0
function CONJ (Z : in COMPLEX) return COMPLEX;
-- Purpose:
-- Returns complex conjugate of Z
-- Special values:
-- None
-- Domain:
-- Z in COMPLEX
-- Error conditions:
-- None
-- Range:
-- CONJ(Z) is mathematically unbounded
-- Notes:
-- Returns x -jy for Z= x + jy
function CONJ (Z : in COMPLEX_POLAR) return COMPLEX_POLAR;
-- Purpose:
-- Returns principal value of complex conjugate of Z
-- Special values:
-- CONJ(Z) = COMPLEX_POLAR'(Z.MAG, MATH_PI) if Z.ARG = MATH_PI
-- Domain:
-- Z in COMPLEX_POLAR and Z.ARG /= -MATH_PI
-- Error conditions:
-- Error if Z.ARG = -MATH_PI
-- Range:
-- result.MAG >= 0.0
-- -MATH_PI < result.ARG <= MATH_PI
-- Notes:
-- Returns COMPLEX_POLAR'(Z.MAG, -Z.ARG) if Z.ARG /= MATH_PI
function SQRT(Z : in COMPLEX) return COMPLEX;
-- Purpose:
-- Returns square root of Z with positive real part
-- or, if the real part is zero, the one with nonnegative
-- imaginary part
-- Special values:
-- SQRT(MATH_CZERO) = MATH_CZERO
-- Domain:
-- Z in COMPLEX
-- Error conditions:
-- None
-- Range:
-- SQRT(Z) is mathematically unbounded
-- Notes:
-- None
function SQRT(Z : in COMPLEX_POLAR) return COMPLEX_POLAR;
-- Purpose:
-- Returns square root of Z with positive real part
-- or, if the real part is zero, the one with nonnegative
-- imaginary part
-- Special values:
-- SQRT(Z) = COMPLEX_POLAR'(0.0, 0.0) if Z.MAG = 0.0
-- Domain:
-- Z in COMPLEX_POLAR and Z.ARG /= -MATH_PI
-- Error conditions:
-- Error if Z.ARG = -MATH_PI
-- Range:
-- result.MAG >= 0.0
-- -MATH_PI < result.ARG <= MATH_PI
-- Notes:
-- None
function EXP(Z : in COMPLEX) return COMPLEX;
-- Purpose:
-- Returns exponential of Z
-- Special values:
-- EXP(MATH_CZERO) = MATH_CBASE_1
-- EXP(Z) = -MATH_CBASE_1 if Z.RE = 0.0 and ABS(Z.IM) = MATH_PI
-- EXP(Z) = SIGN(Z.IM)*MATH_CBASE_J if Z.RE = 0.0 and
-- ABS(Z.IM) = MATH_PI_OVER_2
-- Domain:
-- Z in COMPLEX
-- Error conditions:
-- None
-- Range:
-- EXP(Z) is mathematically unbounded
-- Notes:
-- None
function EXP(Z : in COMPLEX_POLAR) return COMPLEX_POLAR;
-- Purpose:
-- Returns principal value of exponential of Z
-- Special values:
-- EXP(Z) = COMPLEX_POLAR'(1.0, 0.0) if Z.MAG =0.0 and
-- Z.ARG = 0.0
-- EXP(Z) = COMPLEX_POLAR'(1.0, MATH_PI) if Z.MAG = MATH_PI and
-- ABS(Z.ARG) = MATH_PI_OVER_2
-- EXP(Z) = COMPLEX_POLAR'(1.0, MATH_PI_OVER_2) if
-- Z.MAG = MATH_PI_OVER_2 and
-- Z.ARG = MATH_PI_OVER_2
-- EXP(Z) = COMPLEX_POLAR'(1.0, -MATH_PI_OVER_2) if
-- Z.MAG = MATH_PI_OVER_2 and
-- Z.ARG = -MATH_PI_OVER_2
-- Domain:
-- Z in COMPLEX_POLAR and Z.ARG /= -MATH_PI
-- Error conditions:
-- Error if Z.ARG = -MATH_PI
-- Range:
-- result.MAG >= 0.0
-- -MATH_PI < result.ARG <= MATH_PI
-- Notes:
-- None
function LOG(Z : in COMPLEX) return COMPLEX;
-- Purpose:
-- Returns natural logarithm of Z
-- Special values:
-- LOG(MATH_CBASE_1) = MATH_CZERO
-- LOG(-MATH_CBASE_1) = COMPLEX'(0.0, MATH_PI)
-- LOG(MATH_CBASE_J) = COMPLEX'(0.0, MATH_PI_OVER_2)
-- LOG(-MATH_CBASE_J) = COMPLEX'(0.0, -MATH_PI_OVER_2)
-- LOG(Z) = MATH_CBASE_1 if Z = COMPLEX'(MATH_E, 0.0)
-- Domain:
-- Z in COMPLEX and ABS(Z) /= 0.0
-- Error conditions:
-- Error if ABS(Z) = 0.0
-- Range:
-- LOG(Z) is mathematically unbounded
-- Notes:
-- None
function LOG2(Z : in COMPLEX) return COMPLEX;
-- Purpose:
-- Returns logarithm base 2 of Z
-- Special values:
-- LOG2(MATH_CBASE_1) = MATH_CZERO
-- LOG2(Z) = MATH_CBASE_1 if Z = COMPLEX'(2.0, 0.0)
-- Domain:
-- Z in COMPLEX and ABS(Z) /= 0.0
-- Error conditions:
-- Error if ABS(Z) = 0.0
-- Range:
-- LOG2(Z) is mathematically unbounded
-- Notes:
-- None
function LOG10(Z : in COMPLEX) return COMPLEX;
-- Purpose:
-- Returns logarithm base 10 of Z
-- Special values:
-- LOG10(MATH_CBASE_1) = MATH_CZERO
-- LOG10(Z) = MATH_CBASE_1 if Z = COMPLEX'(10.0, 0.0)
-- Domain:
-- Z in COMPLEX and ABS(Z) /= 0.0
-- Error conditions:
-- Error if ABS(Z) = 0.0
-- Range:
-- LOG10(Z) is mathematically unbounded
-- Notes:
-- None
function LOG(Z : in COMPLEX_POLAR) return COMPLEX_POLAR;
-- Purpose:
-- Returns principal value of natural logarithm of Z
-- Special values:
-- LOG(Z) = COMPLEX_POLAR'(0.0, 0.0) if Z.MAG = 1.0 and
-- Z.ARG = 0.0
-- LOG(Z) = COMPLEX_POLAR'(MATH_PI, MATH_PI_OVER_2) if
-- Z.MAG = 1.0 and Z.ARG = MATH_PI
-- LOG(Z) = COMPLEX_POLAR'(MATH_PI_OVER_2, MATH_PI_OVER_2) if
-- Z.MAG = 1.0 and Z.ARG = MATH_PI_OVER_2
-- LOG(Z) = COMPLEX_POLAR'(MATH_PI_OVER_2, -MATH_PI_OVER_2) if
-- Z.MAG = 1.0 and Z.ARG = -MATH_PI_OVER_2
-- LOG(Z) = COMPLEX_POLAR'(1.0, 0.0) if Z.MAG = MATH_E and
-- Z.ARG = 0.0
-- Domain:
-- Z in COMPLEX_POLAR and Z.ARG /= -MATH_PI
-- Z.MAG /= 0.0
-- Error conditions:
-- Error if Z.ARG = -MATH_PI
-- Error if Z.MAG = 0.0
-- Range:
-- result.MAG >= 0.0
-- -MATH_PI < result.ARG <= MATH_PI
-- Notes:
-- None
function LOG2(Z : in COMPLEX_POLAR) return COMPLEX_POLAR;
-- Purpose:
-- Returns principal value of logarithm base 2 of Z
-- Special values:
-- LOG2(Z) = COMPLEX_POLAR'(0.0, 0.0) if Z.MAG = 1.0 and
-- Z.ARG = 0.0
-- LOG2(Z) = COMPLEX_POLAR'(1.0, 0.0) if Z.MAG = 2.0 and
-- Z.ARG = 0.0
-- Domain:
-- Z in COMPLEX_POLAR and Z.ARG /= -MATH_PI
-- Z.MAG /= 0.0
-- Error conditions:
-- Error if Z.ARG = -MATH_PI
-- Error if Z.MAG = 0.0
-- Range:
-- result.MAG >= 0.0
-- -MATH_PI < result.ARG <= MATH_PI
-- Notes:
-- None
function LOG10(Z : in COMPLEX_POLAR) return COMPLEX_POLAR;
-- Purpose:
-- Returns principal value of logarithm base 10 of Z
-- Special values:
-- LOG10(Z) = COMPLEX_POLAR'(0.0, 0.0) if Z.MAG = 1.0 and
-- Z.ARG = 0.0
-- LOG10(Z) = COMPLEX_POLAR'(1.0, 0.0) if Z.MAG = 10.0 and
-- Z.ARG = 0.0
-- Domain:
-- Z in COMPLEX_POLAR and Z.ARG /= -MATH_PI
-- Z.MAG /= 0.0
-- Error conditions:
-- Error if Z.ARG = -MATH_PI
-- Error if Z.MAG = 0.0
-- Range:
-- result.MAG >= 0.0
-- -MATH_PI < result.ARG <= MATH_PI
-- Notes:
-- None
function LOG(Z : in COMPLEX; BASE : in REAL) return COMPLEX;
-- Purpose:
-- Returns logarithm base BASE of Z
-- Special values:
-- LOG(MATH_CBASE_1, BASE) = MATH_CZERO
-- LOG(Z,BASE) = MATH_CBASE_1 if Z = COMPLEX'(BASE, 0.0)
-- Domain:
-- Z in COMPLEX and ABS(Z) /= 0.0
-- BASE > 0.0
-- BASE /= 1.0
-- Error conditions:
-- Error if ABS(Z) = 0.0
-- Error if BASE <= 0.0
-- Error if BASE = 1.0
-- Range:
-- LOG(Z,BASE) is mathematically unbounded
-- Notes:
-- None
function LOG(Z : in COMPLEX_POLAR; BASE : in REAL) return COMPLEX_POLAR;
-- Purpose:
-- Returns principal value of logarithm base BASE of Z
-- Special values:
-- LOG(Z, BASE) = COMPLEX_POLAR'(0.0, 0.0) if Z.MAG = 1.0 and
-- Z.ARG = 0.0
-- LOG(Z, BASE) = COMPLEX_POLAR'(1.0, 0.0) if Z.MAG = BASE and
-- Z.ARG = 0.0
-- Domain:
-- Z in COMPLEX_POLAR and Z.ARG /= -MATH_PI
-- Z.MAG /= 0.0
-- BASE > 0.0
-- BASE /= 1.0
-- Error conditions:
-- Error if Z.ARG = -MATH_PI
-- Error if Z.MAG = 0.0
-- Error if BASE <= 0.0
-- Error if BASE = 1.0
-- Range:
-- result.MAG >= 0.0
-- -MATH_PI < result.ARG <= MATH_PI
-- Notes:
-- None
function SIN (Z : in COMPLEX) return COMPLEX;
-- Purpose:
-- Returns sine of Z
-- Special values:
-- SIN(MATH_CZERO) = MATH_CZERO
-- SIN(Z) = MATH_CZERO if Z = COMPLEX'(MATH_PI, 0.0)
-- Domain:
-- Z in COMPLEX
-- Error conditions:
-- None
-- Range:
-- ABS(SIN(Z)) <= SQRT(SIN(Z.RE)*SIN(Z.RE) +
-- SINH(Z.IM)*SINH(Z.IM))
-- Notes:
-- None
function SIN (Z : in COMPLEX_POLAR) return COMPLEX_POLAR;
-- Purpose:
-- Returns principal value of sine of Z
-- Special values:
-- SIN(Z) = COMPLEX_POLAR'(0.0, 0.0) if Z.MAG = 0.0 and
-- Z.ARG = 0.0
-- SIN(Z) = COMPLEX_POLAR'(0.0, 0.0) if Z.MAG = MATH_PI and
-- Z.ARG = 0.0
-- Domain:
-- Z in COMPLEX_POLAR and Z.ARG /= -MATH_PI
-- Error conditions:
-- Error if Z.ARG = -MATH_PI
-- Range:
-- result.MAG >= 0.0
-- -MATH_PI < result.ARG <= MATH_PI
-- Notes:
-- None
function COS (Z : in COMPLEX) return COMPLEX;
-- Purpose:
-- Returns cosine of Z
-- Special values:
-- COS(Z) = MATH_CZERO if Z = COMPLEX'(MATH_PI_OVER_2, 0.0)
-- COS(Z) = MATH_CZERO if Z = COMPLEX'(-MATH_PI_OVER_2, 0.0)
-- Domain:
-- Z in COMPLEX
-- Error conditions:
-- None
-- Range:
-- ABS(COS(Z)) <= SQRT(COS(Z.RE)*COS(Z.RE) +
-- SINH(Z.IM)*SINH(Z.IM))
-- Notes:
-- None
function COS (Z : in COMPLEX_POLAR) return COMPLEX_POLAR;
-- Purpose:
-- Returns principal value of cosine of Z
-- Special values:
-- COS(Z) = COMPLEX_POLAR'(0.0, 0.0) if Z.MAG = MATH_PI_OVER_2
-- and Z.ARG = 0.0
-- COS(Z) = COMPLEX_POLAR'(0.0, 0.0) if Z.MAG = MATH_PI_OVER_2
-- and Z.ARG = MATH_PI
-- Domain:
-- Z in COMPLEX_POLAR and Z.ARG /= -MATH_PI
-- Error conditions:
-- Error if Z.ARG = -MATH_PI
-- Range:
-- result.MAG >= 0.0
-- -MATH_PI < result.ARG <= MATH_PI
-- Notes:
-- None
function SINH (Z : in COMPLEX) return COMPLEX;
-- Purpose:
-- Returns hyperbolic sine of Z
-- Special values:
-- SINH(MATH_CZERO) = MATH_CZERO
-- SINH(Z) = MATH_CZERO if Z.RE = 0.0 and Z.IM = MATH_PI
-- SINH(Z) = MATH_CBASE_J if Z.RE = 0.0 and
-- Z.IM = MATH_PI_OVER_2
-- SINH(Z) = -MATH_CBASE_J if Z.RE = 0.0 and
-- Z.IM = -MATH_PI_OVER_2
-- Domain:
-- Z in COMPLEX
-- Error conditions:
-- None
-- Range:
-- ABS(SINH(Z)) <= SQRT(SINH(Z.RE)*SINH(Z.RE) +
-- SIN(Z.IM)*SIN(Z.IM))
-- Notes:
-- None
function SINH (Z : in COMPLEX_POLAR) return COMPLEX_POLAR;
-- Purpose:
-- Returns principal value of hyperbolic sine of Z
-- Special values:
-- SINH(Z) = COMPLEX_POLAR'(0.0, 0.0) if Z.MAG = 0.0 and
-- Z.ARG = 0.0
-- SINH(Z) = COMPLEX_POLAR'(0.0, 0.0) if Z.MAG = MATH_PI and
-- Z.ARG = MATH_PI_OVER_2
-- SINH(Z) = COMPLEX_POLAR'(1.0, MATH_PI_OVER_2) if Z.MAG =
-- MATH_PI_OVER_2 and Z.ARG = MATH_PI_OVER_2
-- SINH(Z) = COMPLEX_POLAR'(1.0, -MATH_PI_OVER_2) if Z.MAG =
-- MATH_PI_OVER_2 and Z.ARG = -MATH_PI_OVER_2
-- Domain:
-- Z in COMPLEX_POLAR and Z.ARG /= -MATH_PI
-- Error conditions:
-- Error if Z.ARG = -MATH_PI
-- Range:
-- result.MAG >= 0.0
-- -MATH_PI < result.ARG <= MATH_PI
-- Notes:
-- None
function COSH (Z : in COMPLEX) return COMPLEX;
-- Purpose:
-- Returns hyperbolic cosine of Z
-- Special values:
-- COSH(MATH_CZERO) = MATH_CBASE_1
-- COSH(Z) = -MATH_CBASE_1 if Z.RE = 0.0 and Z.IM = MATH_PI
-- COSH(Z) = MATH_CZERO if Z.RE = 0.0 and Z.IM = MATH_PI_OVER_2
-- COSH(Z) = MATH_CZERO if Z.RE = 0.0 and Z.IM = -MATH_PI_OVER_2
-- Domain:
-- Z in COMPLEX
-- Error conditions:
-- None
-- Range:
-- ABS(COSH(Z)) <= SQRT(SINH(Z.RE)*SINH(Z.RE) +
-- COS(Z.IM)*COS(Z.IM))
-- Notes:
-- None
function COSH (Z : in COMPLEX_POLAR) return COMPLEX_POLAR;
-- Purpose:
-- Returns principal value of hyperbolic cosine of Z
-- Special values:
-- COSH(Z) = COMPLEX_POLAR'(1.0, 0.0) if Z.MAG = 0.0 and
-- Z.ARG = 0.0
-- COSH(Z) = COMPLEX_POLAR'(1.0, MATH_PI) if Z.MAG = MATH_PI and
-- Z.ARG = MATH_PI_OVER_2
-- COSH(Z) = COMPLEX_POLAR'(0.0, 0.0) if Z.MAG =
-- MATH_PI_OVER_2 and Z.ARG = MATH_PI_OVER_2
-- COSH(Z) = COMPLEX_POLAR'(0.0, 0.0) if Z.MAG =
-- MATH_PI_OVER_2 and Z.ARG = -MATH_PI_OVER_2
-- Domain:
-- Z in COMPLEX_POLAR and Z.ARG /= -MATH_PI
-- Error conditions:
-- Error if Z.ARG = -MATH_PI
-- Range:
-- result.MAG >= 0.0
-- -MATH_PI < result.ARG <= MATH_PI
-- Notes:
-- None
--
-- Arithmetic Operators
--
function "+" (L : in COMPLEX; R : in COMPLEX) return COMPLEX;
-- Purpose:
-- Returns arithmetic addition of L and R
-- Special values:
-- None
-- Domain:
-- L in COMPLEX
-- R in COMPLEX
-- Error conditions:
-- None
-- Range:
-- "+"(Z) is mathematically unbounded
-- Notes:
-- None
function "+" (L : in REAL; R : in COMPLEX) return COMPLEX;
-- Purpose:
-- Returns arithmetic addition of L and R
-- Special values:
-- None
-- Domain:
-- L in REAL
-- R in COMPLEX
-- Error conditions:
-- None
-- Range:
-- "+"(Z) is mathematically unbounded
-- Notes:
-- None
function "+" (L : in COMPLEX; R : in REAL) return COMPLEX;
-- Purpose:
-- Returns arithmetic addition of L and R
-- Special values:
-- None
-- Domain:
-- L in COMPLEX
-- R in REAL
-- Error conditions:
-- None
-- Range:
-- "+"(Z) is mathematically unbounded
-- Notes:
-- None
function "+" (L : in COMPLEX_POLAR; R : in COMPLEX_POLAR)
return COMPLEX_POLAR;
-- Purpose:
-- Returns arithmetic addition of L and R
-- Special values:
-- None
-- Domain:
-- L in COMPLEX_POLAR and L.ARG /= -MATH_PI
-- R in COMPLEX_POLAR and R.ARG /= -MATH_PI
-- Error conditions:
-- Error if L.ARG = -MATH_PI
-- Error if R.ARG = -MATH_PI
-- Range:
-- result.MAG >= 0.0
-- -MATH_PI < result.ARG <= MATH_PI
-- Notes:
-- None
function "+" (L : in REAL; R : in COMPLEX_POLAR) return COMPLEX_POLAR;
-- Purpose:
-- Returns arithmetic addition of L and R
-- Special values:
-- None
-- Domain:
-- L in REAL
-- R in COMPLEX_POLAR and R.ARG /= -MATH_PI
-- Error conditions:
-- Error if R.ARG = -MATH_PI
-- Range:
-- result.MAG >= 0.0
-- -MATH_PI < result.ARG <= MATH_PI
-- Notes:
-- None
function "+" (L : in COMPLEX_POLAR; R : in REAL) return COMPLEX_POLAR;
-- Purpose:
-- Returns arithmetic addition of L and R
-- Special values:
-- None
-- Domain:
-- L in COMPLEX_POLAR and L.ARG /= -MATH_PI
-- R in REAL
-- Error conditions:
-- Error if L.ARG = -MATH_PI
-- Range:
-- result.MAG >= 0.0
-- -MATH_PI < result.ARG <= MATH_PI
-- Notes:
-- None
function "-" (L : in COMPLEX; R : in COMPLEX) return COMPLEX;
-- Purpose:
-- Returns arithmetic subtraction of L minus R
-- Special values:
-- None
-- Domain:
-- L in COMPLEX
-- R in COMPLEX
-- Error conditions:
-- None
-- Range:
-- "-"(Z) is mathematically unbounded
-- Notes:
-- None
function "-" (L : in REAL; R : in COMPLEX) return COMPLEX;
-- Purpose:
-- Returns arithmetic subtraction of L minus R
-- Special values:
-- None
-- Domain:
-- L in REAL
-- R in COMPLEX
-- Error conditions:
-- None
-- Range:
-- "-"(Z) is mathematically unbounded
-- Notes:
-- None
function "-" (L : in COMPLEX; R : in REAL) return COMPLEX;
-- Purpose:
-- Returns arithmetic subtraction of L minus R
-- Special values:
-- None
-- Domain:
-- L in COMPLEX
-- R in REAL
-- Error conditions:
-- None
-- Range:
-- "-"(Z) is mathematically unbounded
-- Notes:
-- None
function "-" (L : in COMPLEX_POLAR; R : in COMPLEX_POLAR)
return COMPLEX_POLAR;
-- Purpose:
-- Returns arithmetic subtraction of L minus R
-- Special values:
-- None
-- Domain:
-- L in COMPLEX_POLAR and L.ARG /= -MATH_PI
-- R in COMPLEX_POLAR and R.ARG /= -MATH_PI
-- Error conditions:
-- Error if L.ARG = -MATH_PI
-- Error if R.ARG = -MATH_PI
-- Range:
-- result.MAG >= 0.0
-- -MATH_PI < result.ARG <= MATH_PI
-- Notes:
-- None
function "-" (L : in REAL; R : in COMPLEX_POLAR) return COMPLEX_POLAR;
-- Purpose:
-- Returns arithmetic subtraction of L minus R
-- Special values:
-- None
-- Domain:
-- L in REAL
-- R in COMPLEX_POLAR and R.ARG /= -MATH_PI
-- Error conditions:
-- Error if R.ARG = -MATH_PI
-- Range:
-- result.MAG >= 0.0
-- -MATH_PI < result.ARG <= MATH_PI
-- Notes:
-- None
function "-" (L : in COMPLEX_POLAR; R : in REAL) return COMPLEX_POLAR;
-- Purpose:
-- Returns arithmetic subtraction of L minus R
-- Special values:
-- None
-- Domain:
-- L in COMPLEX_POLAR and L.ARG /= -MATH_PI
-- R in REAL
-- Error conditions:
-- Error if L.ARG = -MATH_PI
-- Range:
-- result.MAG >= 0.0
-- -MATH_PI < result.ARG <= MATH_PI
-- Notes:
-- None
function "*" (L : in COMPLEX; R : in COMPLEX) return COMPLEX;
-- Purpose:
-- Returns arithmetic multiplication of L and R
-- Special values:
-- None
-- Domain:
-- L in COMPLEX
-- R in COMPLEX
-- Error conditions:
-- None
-- Range:
-- "*"(Z) is mathematically unbounded
-- Notes:
-- None
function "*" (L : in REAL; R : in COMPLEX) return COMPLEX;
-- Purpose:
-- Returns arithmetic multiplication of L and R
-- Special values:
-- None
-- Domain:
-- L in REAL
-- R in COMPLEX
-- Error conditions:
-- None
-- Range:
-- "*"(Z) is mathematically unbounded
-- Notes:
-- None
function "*" (L : in COMPLEX; R : in REAL) return COMPLEX;
-- Purpose:
-- Returns arithmetic multiplication of L and R
-- Special values:
-- None
-- Domain:
-- L in COMPLEX
-- R in REAL
-- Error conditions:
-- None
-- Range:
-- "*"(Z) is mathematically unbounded
-- Notes:
-- None
function "*" (L : in COMPLEX_POLAR; R : in COMPLEX_POLAR)
return COMPLEX_POLAR;
-- Purpose:
-- Returns arithmetic multiplication of L and R
-- Special values:
-- None
-- Domain:
-- L in COMPLEX_POLAR and L.ARG /= -MATH_PI
-- R in COMPLEX_POLAR and R.ARG /= -MATH_PI
-- Error conditions:
-- Error if L.ARG = -MATH_PI
-- Error if R.ARG = -MATH_PI
-- Range:
-- result.MAG >= 0.0
-- -MATH_PI < result.ARG <= MATH_PI
-- Notes:
-- None
function "*" (L : in REAL; R : in COMPLEX_POLAR) return COMPLEX_POLAR;
-- Purpose:
-- Returns arithmetic multiplication of L and R
-- Special values:
-- None
-- Domain:
-- L in REAL
-- R in COMPLEX_POLAR and R.ARG /= -MATH_PI
-- Error conditions:
-- Error if R.ARG = -MATH_PI
-- Range:
-- result.MAG >= 0.0
-- -MATH_PI < result.ARG <= MATH_PI
-- Notes:
-- None
function "*" (L : in COMPLEX_POLAR; R : in REAL) return COMPLEX_POLAR;
-- Purpose:
-- Returns arithmetic multiplication of L and R
-- Special values:
-- None
-- Domain:
-- L in COMPLEX_POLAR and L.ARG /= -MATH_PI
-- R in REAL
-- Error conditions:
-- Error if L.ARG = -MATH_PI
-- Range:
-- result.MAG >= 0.0
-- -MATH_PI < result.ARG <= MATH_PI
-- Notes:
-- None
function "/" (L : in COMPLEX; R : in COMPLEX) return COMPLEX;
-- Purpose:
-- Returns arithmetic division of L by R
-- Special values:
-- None
-- Domain:
-- L in COMPLEX
-- R in COMPLEX and R /= MATH_CZERO
-- Error conditions:
-- Error if R = MATH_CZERO
-- Range:
-- "/"(Z) is mathematically unbounded
-- Notes:
-- None
function "/" (L : in REAL; R : in COMPLEX) return COMPLEX;
-- Purpose:
-- Returns arithmetic division of L by R
-- Special values:
-- None
-- Domain:
-- L in REAL
-- R in COMPLEX and R /= MATH_CZERO
-- Error conditions:
-- Error if R = MATH_CZERO
-- Range:
-- "/"(Z) is mathematically unbounded
-- Notes:
-- None
function "/" (L : in COMPLEX; R : in REAL) return COMPLEX;
-- Purpose:
-- Returns arithmetic division of L by R
-- Special values:
-- None
-- Domain:
-- L in COMPLEX
-- R in REAL and R /= 0.0
-- Error conditions:
-- Error if R = 0.0
-- Range:
-- "/"(Z) is mathematically unbounded
-- Notes:
-- None
function "/" (L : in COMPLEX_POLAR; R : in COMPLEX_POLAR)
return COMPLEX_POLAR;
-- Purpose:
-- Returns arithmetic division of L by R
-- Special values:
-- None
-- Domain:
-- L in COMPLEX_POLAR and L.ARG /= -MATH_PI
-- R in COMPLEX_POLAR and R.ARG /= -MATH_PI
-- R.MAG > 0.0
-- Error conditions:
-- Error if R.MAG <= 0.0
-- Error if L.ARG = -MATH_PI
-- Error if R.ARG = -MATH_PI
-- Range:
-- result.MAG >= 0.0
-- -MATH_PI < result.ARG <= MATH_PI
-- Notes:
-- None
function "/" (L : in REAL; R : in COMPLEX_POLAR) return COMPLEX_POLAR;
-- Purpose:
-- Returns arithmetic division of L by R
-- Special values:
-- None
-- Domain:
-- L in REAL
-- R in COMPLEX_POLAR and R.ARG /= -MATH_PI
-- R.MAG > 0.0
-- Error conditions:
-- Error if R.MAG <= 0.0
-- Error if R.ARG = -MATH_PI
-- Range:
-- result.MAG >= 0.0
-- -MATH_PI < result.ARG <= MATH_PI
-- Notes:
-- None
function "/" (L : in COMPLEX_POLAR; R : in REAL) return COMPLEX_POLAR;
-- Purpose:
-- Returns arithmetic division of L by R
-- Special values:
-- None
-- Domain:
-- L in COMPLEX_POLAR and L.ARG /= -MATH_PI
-- R /= 0.0
-- Error conditions:
-- Error if L.ARG = -MATH_PI
-- Error if R = 0.0
-- Range:
-- result.MAG >= 0.0
-- -MATH_PI < result.ARG <= MATH_PI
-- Notes:
-- None
end package MATH_COMPLEX;
| gpl-2.0 | a8986099c3754ef154c176da82d18db7 | 0.494717 | 3.606227 | false | false | false | false |
emogenet/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc1451.vhd | 4 | 1,815 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1451.vhd,v 1.2 2001-10-26 16:29:41 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s07b00x00p01n01i01451ent IS
END c08s07b00x00p01n01i01451ent;
ARCHITECTURE c08s07b00x00p01n01i01451arch OF c08s07b00x00p01n01i01451ent IS
begin
t: process
type some2 is (alpha,beta);
variable j : some2 := alpha;
variable k : integer := 0;
begin
if j = alpha then
k := 1;
end if;
assert (k = 0)
report "***PASSED TEST: c08s07b00x00p01n01i01451"
severity NOTE;
assert NOT(k = 0)
report "***FAILED TEST: c08s07b00x00p01n01i01451 - BOOLEAN expression of IF statement using enumerated types"
severity ERROR;
wait;
end process;
END c08s07b00x00p01n01i01451arch;
| gpl-2.0 | af6b5ee1c3a954d3db34e2961bd4c5ae | 0.660055 | 3.637275 | false | true | false | false |
emogenet/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc747.vhd | 4 | 9,235 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc747.vhd,v 1.2 2001-10-26 16:29:59 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
package c01s01b01x01p05n02i00747pkg is
type boolean_vector is array (natural range <>) of boolean;
type severity_level_vector is array (natural range <>) of severity_level;
type integer_vector is array (natural range <>) of integer;
type real_vector is array (natural range <>) of real;
type time_vector is array (natural range <>) of time;
type natural_vector is array (natural range <>) of natural;
type positive_vector is array (natural range <>) of positive;
type record_std_package is record
a:boolean;
b:bit;
c:character;
d:severity_level;
e:integer;
f:real;
g:time;
h:natural;
i:positive;
j:string(1 to 7);
k:bit_vector(0 to 3);
end record;
type array_rec_std is array (integer range <>) of record_std_package;
procedure P1(inp : boolean_vector;ot:out boolean) ;
procedure P2(inp : bit_vector;ot:out bit) ;
procedure P3(inp : string; ot:out character);
procedure P4(inp : severity_level_vector;ot:out severity_level);
procedure P5(inp : integer_vector; ot:out integer) ;
procedure P6(inp : real_vector; ot:out real) ;
procedure P7(inp : time_vector; ot:out time) ;
procedure P8(inp : natural_vector;ot:out natural) ;
procedure P9(inp : positive_vector;ot:out positive) ;
procedure P10(inp : array_rec_std;ot:out record_std_package) ;
end c01s01b01x01p05n02i00747pkg;
package body c01s01b01x01p05n02i00747pkg is
procedure P1(inp : boolean_vector;ot:out boolean) is
begin
for i in 0 to 15 loop
assert(inp(i) = true) report"wrong initialization of S1" severity error;
end loop;
ot := false;
end P1;
procedure P2(inp : bit_vector;ot:out bit) is
begin
for i in 0 to 3 loop
assert(inp(i) = '0') report"wrong initialization of S2" severity error;
end loop;
ot := '0';
end P2;
procedure P3(inp : string; ot:out character) is
begin
for i in 1 to 7 loop
assert(inp(i) = 's') report"wrong initialization of S3" severity error;
end loop;
ot := 'h';
end P3;
procedure P4(inp : severity_level_vector;ot:out severity_level) is
begin
for i in 0 to 15 loop
assert(inp(i) = note) report"wrong initialization of S4" severity error;
end loop;
ot := error;
end P4;
procedure P5(inp : integer_vector; ot:out integer) is
begin
for i in 0 to 15 loop
assert(inp(i) = 3) report"wrong initialization of S5" severity error;
end loop;
ot := 6;
end P5;
procedure P6(inp : real_vector; ot:out real) is
begin
for i in 0 to 15 loop
assert(inp(i) = 3.0) report"wrong initialization of S6" severity error;
end loop;
ot := 6.0;
end P6;
procedure P7(inp : time_vector; ot:out time) is
begin
for i in 0 to 15 loop
assert(inp(i) = 3 ns) report"wrong initialization of S7" severity error;
end loop;
ot := 6 ns;
end P7;
procedure P8(inp : natural_vector;ot:out natural) is
begin
for i in 0 to 15 loop
assert(inp(i) = 1) report"wrong initialization of S8" severity error;
end loop;
ot := 6;
end P8;
procedure P9(inp : positive_vector;ot:out positive) is
begin
for i in 0 to 15 loop
assert(inp(i) = 1) report"wrong initialization of S9" severity error;
end loop;
ot := 6;
end P9;
procedure P10(inp : array_rec_std;ot:out record_std_package) is
begin
for i in 0 to 7 loop
assert(inp(i) = (true,'1','s',note,3,3.0,3 ns, 1,1,"sssssss","0000")) report"wrong initialization of S10" severity error;
end loop;
ot := (false,'0','s',error,5,5.0,5 ns,5,5,"metrics","1100");
end P10;
end c01s01b01x01p05n02i00747pkg;
use work.c01s01b01x01p05n02i00747pkg.all;
ENTITY c01s01b01x01p05n02i00747ent IS
generic(
zero : integer := 0;
one : integer := 1;
two : integer := 2;
three: integer := 3;
four : integer := 4;
five : integer := 5;
six : integer := 6;
seven: integer := 7;
eight: integer := 8;
nine : integer := 9;
fifteen:integer:= 15;
C1 : boolean := true;
C2 : bit := '1';
C3 : character := 's';
C4 : severity_level:= note;
C5 : integer := 3;
C6 : real := 3.0;
C7 : time := 3 ns;
C8 : natural := 1;
C9 : positive := 1;
C10 : string := "sssssss";
C11 : bit_vector := B"0000";
C48 : record_std_package := (true,'1','s',note,3,3.0,3 ns,1,1,"sssssss","0000")
);
port(
S1 : boolean_vector(zero to fifteen) := (others => C1);
S2 : severity_level_vector(zero to fifteen) := (others => C4);
S3 : integer_vector(zero to fifteen) := (others => C5);
S4 : real_vector(zero to fifteen) := (others => C6);
S5 : time_vector (zero to fifteen) := (others => C7);
S6 : natural_vector(zero to fifteen) := (others => C8);
S7 : positive_vector(zero to fifteen) := (others => C9);
S8 : string(one to seven) := C10;
S9 : bit_vector(zero to three) := C11;
S48: array_rec_std(zero to seven) := (others => C48)
);
END c01s01b01x01p05n02i00747ent;
ARCHITECTURE c01s01b01x01p05n02i00747arch OF c01s01b01x01p05n02i00747ent IS
BEGIN
TESTING: PROCESS
variable var1 : boolean;
variable var4 : severity_level;
variable var5 : integer;
variable var6 : real;
variable var7 : time;
variable var8 : natural;
variable var9 : positive;
variable var2 : bit;
variable var3 : character;
variable var48: record_std_package;
BEGIN
P1(S1,var1);
P2(S9,var2);
P3(S8,var3);
P4(S2,var4);
P5(S3,var5);
P6(S4,var6);
P7(S5,var7);
P8(S6,var8);
P9(S7,var9);
P10(S48,var48);
wait for 1 ns;
assert(var1 = false) report "wrong assignment in the function F1" severity error;
assert(var2 = '0') report "wrong assignment in the function F2" severity error;
assert(var3 = 'h') report "wrong assignment in the function F3" severity error;
assert(var4 = error) report "wrong assignment in the function F4" severity error;
assert(var5 = 6) report "wrong assignment in the function F5" severity error;
assert(var6 = 6.0) report "wrong assignment in the function F6" severity error;
assert(var7 = 6 ns) report "wrong assignment in the function F7" severity error;
assert(var8 = 6) report "wrong assignment in the function F8" severity error;
assert(var9 = 6) report "wrong assignment in the function F9" severity error;
assert(var48 = (false,'0','s',error,5,5.0,5 ns,5,5,"metrics","1100")) report "wrong assignment in the function F10" severity error;
assert NOT( var1 = false and
var2 = '0' and
var3 = 'h' and
var4 = error and
var5 = 6 and
var6 = 6.0 and
var7 = 6 ns and
var8 = 6 and
var9 = 6 and
var48 = (false,'0','s',error,5,5.0,5 ns,5,5,"metrics","1100") )
report "***PASSED TEST: c01s01b01x01p05n02i00747"
severity NOTE;
assert ( var1 = false and
var2 = '0' and
var3 = 'h' and
var4 = error and
var5 = 6 and
var6 = 6.0 and
var7 = 6 ns and
var8 = 6 and
var9 = 6 and
var48 = (false,'0','s',error,5,5.0,5 ns,5,5,"metrics","1100") )
report "***FAILED TEST: c01s01b01x01p05n02i00747 - Generic can be used to specify the size of ports."
severity ERROR;
wait;
END PROCESS TESTING;
END c01s01b01x01p05n02i00747arch;
| gpl-2.0 | bde128a15668793976494080a55ba174 | 0.58235 | 3.401473 | false | false | false | false |
hacklabmikkeli/rough-boy | delta_sigma_dac.vhdl | 2 | 1,671 | --
-- Knobs Galore - a free phase distortion synthesizer
-- Copyright (C) 2015 Ilmo Euro
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
use work.common.all;
entity delta_sigma_dac is
port (EN: in std_logic
;CLK: in std_logic
;Zin: in audio_signal
;Vout: out std_logic
)
;
end entity;
architecture delta_sigma_dac_impl of delta_sigma_dac is
subtype sigma_t is signed(audio_signal'high + 1 downto 0);
signal sigma : sigma_t := (others => '0');
begin
process (CLK)
variable delta : sigma_t;
variable zin_s : sigma_t;
begin
if EN = '1' and rising_edge(CLK) then
zin_s := signed("0" & Zin);
delta := ('0', others => not sigma(sigma'left));
sigma <= (sigma + zin_s) - delta;
end if;
end process;
Vout <= not sigma(sigma'left);
end architecture;
| gpl-3.0 | ecc88da00cf2136586803d259c5645dd | 0.619988 | 3.746637 | false | false | false | false |
gmsanchez/OrgComp | TP_02/TB_SN54AS169A.vhd | 1 | 4,454 | --------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 15:10:32 10/01/2014
-- Design Name:
-- Module Name: E:/2014/Academico/OC/2014/tp2/TB_SN54AS169A.vhd
-- Project Name: tp2
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: SN54AS169A
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY TB_SN54AS169A IS
END TB_SN54AS169A;
ARCHITECTURE Behavioral OF TB_SN54AS169A IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT SN54AS169A
PORT(
CLK : IN std_logic;
UND : IN std_logic;
NLOAD : IN std_logic;
NENT : IN std_logic;
NENP : IN std_logic;
DIN : IN std_logic_vector(3 downto 0);
NRCO : OUT std_logic;
DOUT : OUT std_logic_vector(3 downto 0)
);
END COMPONENT;
--Inputs
signal CLK : std_logic := '0';
signal UND : std_logic := '0';
signal NLOAD : std_logic := '0';
signal NENT : std_logic := '0';
signal NENP : std_logic := '0';
signal DIN : std_logic_vector(3 downto 0) := (others => '0');
--Outputs
signal NRCO : std_logic;
signal DOUT : std_logic_vector(3 downto 0);
-- Clock period definitions
constant CLK_period : time := 10 ns;
-- variable whatsTheTime : time;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: SN54AS169A PORT MAP (
CLK => CLK,
UND => UND,
NLOAD => NLOAD,
NENT => NENT,
NENP => NENP,
DIN => DIN,
NRCO => NRCO,
DOUT => DOUT
);
-- Clock process definitions
CLK_process :process
begin
CLK <= '0';
wait for CLK_period/2;
CLK <= '1';
wait for CLK_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
wait for 20 ns;
-- insert stimulus here
DIN<="1101";
NLOAD<='1';
UND<='0';
NENT<='1';
NENP<='1';
wait for 5 ns;
NLOAD<='0';
UND<='1';
NENT<='0';
NENP<='0';
wait for 5 ns;
NLOAD<='1';
wait for 40 ns;
NENP<='1';
NENT<='1';
wait for 5 ns;
UND<='0';
wait for 25 ns;
NENP<='0';
NENT<='0';
wait;
end process;
corr_proc: process(CLK)
variable theTime : time;
begin
theTime := now;
if theTime=30000 ps then
report time'image(theTime);
assert (dout="1101" and nrco='1')
report("Salidas erroneas.")
severity ERROR;
end if;
if theTime=40000 ps then
report time'image(theTime);
assert (dout="1110" and nrco='1')
report("Salidas erroneas.")
severity ERROR;
end if;
if theTime=50000 ps then
report time'image(theTime);
assert (dout="1111" and nrco='0')
report("Salidas erroneas.")
severity ERROR;
end if;
if theTime=60000 ps then
report time'image(theTime);
assert (dout="0000" and nrco='1')
report("Salidas erroneas.")
severity ERROR;
end if;
if theTime=70000 ps then
report time'image(theTime);
assert (dout="0001" and nrco='1')
report("Salidas erroneas.")
severity ERROR;
end if;
if theTime=110000 ps then
report time'image(theTime);
assert (dout="0000" and nrco='0')
report("Salidas erroneas.")
severity ERROR;
end if;
if theTime=120000 ps then
report time'image(theTime);
assert (dout="1111" and nrco='1')
report("Salidas erroneas.")
severity ERROR;
end if;
if theTime=130000 ps then
report time'image(theTime);
assert (dout="1110" and nrco='1')
report("Salidas erroneas.")
severity ERROR;
end if;
end process;
END;
| gpl-2.0 | 408286e0775d3ccd19eaf8880d842999 | 0.572519 | 3.33633 | false | false | false | false |
rafa-jfet/OFM | ARCHIVOS VHDL/intlv_completo.vhd | 1 | 3,236 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 20:47:25 07/01/2015
-- Design Name:
-- Module Name: intlv_completo - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity intlv_completo is
Port ( clk : in STD_LOGIC;
reset : in STD_LOGIC;
button : in STD_LOGIC;
modulation : in STD_LOGIC_VECTOR (2 downto 0);
bit_in : in STD_LOGIC;
ok_bit_in : in STD_LOGIC;
bit_out : out STD_LOGIC_VECTOR (0 downto 0);
ok_bit_out : out STD_LOGIC);
end intlv_completo;
architecture Behavioral of intlv_completo is
-- señales de salida del interleaver, entrada a la memoria
signal write_intlv_mem, bit_out_intlv_mem : STD_LOGIC_VECTOR (0 downto 0);
signal dir_bit_intlv_mem : STD_LOGIC_VECTOR (8 downto 0);
component intlv is
Generic ( bits_BPSK : integer := 96;
bits_QPSK : integer := 192;
bits_8PSK : integer := 288;
col_BPSK : integer := 12;
col_QPSK : integer := 12;
col_8PSK : integer := 18;
fil_BPSK : integer := 8;
fil_QPSK : integer := 16;
fil_8PSK : integer := 16);
Port ( clk : in STD_LOGIC;
reset : in STD_LOGIC;
button : in STD_LOGIC;
modulation : in STD_LOGIC_VECTOR (2 downto 0);
bit_in : in STD_LOGIC;
ok_bit_in : in STD_LOGIC;
bit_out : out STD_LOGIC_VECTOR (0 downto 0);
dir_bit : out STD_LOGIC_VECTOR (8 downto 0);
write_mem : out STD_LOGIC_VECTOR (0 downto 0);
ok_bit_out : out STD_LOGIC
);
end component;
component intlv_mem is
PORT (
clka : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
);
END component;
begin
interleaver : intlv
Generic map ( bits_BPSK => 96,
bits_QPSK => 192,
bits_8PSK => 288,
col_BPSK => 12,
col_QPSK => 12,
col_8PSK => 18,
fil_BPSK => 8,
fil_QPSK => 16,
fil_8PSK => 16)
Port map ( clk => clk,
reset => reset,
button => button,
modulation => modulation,
bit_in => bit_in,
ok_bit_in => ok_bit_in,
bit_out => bit_out_intlv_mem, --
dir_bit => dir_bit_intlv_mem, --
write_mem => write_intlv_mem, --
ok_bit_out => ok_bit_out
);
interleaver_memory : intlv_mem
PORT map (
clka => clk,
wea => write_intlv_mem,
addra => dir_bit_intlv_mem,
dina => bit_out_intlv_mem,
douta => bit_out
);
end Behavioral;
| gpl-3.0 | 608c72a8a5f1bef448a3509cff91e64f | 0.555315 | 3.367326 | false | false | false | false |
emogenet/ghdl | testsuite/vests/vhdl-ams/ashenden/compliant/components-and-configs/intermediate.vhd | 4 | 1,886 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- analyze into resource library chips
entity XYZ3000_cpu is
port ( clock : in bit; addr_data : inout bit_vector(31 downto 0);
other_port : in bit := '0' );
end entity XYZ3000_cpu;
architecture full_function of XYZ3000_cpu is
begin
end architecture full_function;
-- analyze into work library
entity memory_array is
port ( addr : in bit_vector(25 downto 0); other_port : in bit := '0' );
end entity memory_array;
architecture behavioral of memory_array is
begin
end architecture behavioral;
-- code from book
library chips;
configuration intermediate of single_board_computer is
for structural
for cpu : processor
use entity chips.XYZ3000_cpu(full_function)
port map ( clock => clk, addr_data => a_d, -- . . . );
-- not in book
other_port => open );
-- end not in book
end for;
for main_memory : memory
use entity work.memory_array(behavioral);
end for;
for all : serial_interface
use open;
end for;
-- . . .
end for;
end configuration intermediate;
-- end code from book
| gpl-2.0 | 846aed2ed62e9f6905133eb34221d6ec | 0.69088 | 3.987315 | false | false | false | false |
rafa-jfet/OFM | ARCHIVOS VHDL/scrambler.vhd | 1 | 3,022 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 17:51:47 04/23/2015
-- Design Name:
-- Module Name: scrambler - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity scrambler is
Generic ( SAT_ESPERA : integer := 7);
Port ( clk : in STD_LOGIC;
reset : in STD_LOGIC;
button : in STD_LOGIC;
first_in : in STD_LOGIC;
second_in : in STD_LOGIC;
fin_rx : in STD_LOGIC;
ok_bit_in : in STD_LOGIC;
bit_out : out STD_LOGIC;
ok_bit_out : out STD_LOGIC);
end scrambler;
architecture Behavioral of scrambler is
type estado is ( reposo,
inicio,
first_input,
second_input);
signal estado_actual, estado_nuevo : estado;
--signal estado_nuevo : estado;
signal reg, p_reg : STD_LOGIC_VECTOR (6 downto 0);
signal cont, p_cont : integer range 0 to SAT_ESPERA;
signal p_ok_bit_out : STD_LOGIC;
begin
comb : process (estado_actual, first_in, second_in, ok_bit_in, fin_rx, reg, button, cont)
begin
p_reg <= reg;
p_cont <= cont -1;
p_ok_bit_out <= '0';
bit_out <= reg(0) xor second_in;
estado_nuevo <= estado_actual;
case estado_actual is
when reposo => -- estado inicial de reposo y reset de señales
bit_out <= '0';
if ( button = '1' ) then
p_reg <= (others => '1');
estado_nuevo <= inicio;
end if;
when inicio =>
if ( fin_rx = '1' ) then -- fin de recepcion de datos
estado_nuevo <= reposo;
elsif ( ok_bit_in = '1' ) then
estado_nuevo <= first_input;
p_reg(6 downto 1) <= reg(5 downto 0);
p_reg(0) <= reg(6) xor reg(3);
p_ok_bit_out <= '1';
p_cont <= SAT_ESPERA;
end if;
when first_input => --mantiene la salida con first_in SAT_ESPERA ciclos
bit_out <= reg(0) xor first_in;
if ( cont = 0 ) then
estado_nuevo <= second_input;
p_reg(6 downto 1) <= reg(5 downto 0);
p_reg(0) <= reg(6) xor reg(3);
p_ok_bit_out <= '1';
end if;
when second_input =>
bit_out <= reg(0) xor second_in;
estado_nuevo <= inicio;
end case;
end process;
sinc : process (clk, reset)
begin
if ( reset = '1' ) then
reg <= (others => '1');
estado_actual <= reposo;
ok_bit_out <= '0';
cont <= SAT_ESPERA;
elsif ( rising_edge(clk) ) then
reg <= p_reg;
cont <= p_cont;
ok_bit_out <= p_ok_bit_out;
estado_actual <= estado_nuevo;
end if;
end process;
end Behavioral;
| gpl-3.0 | 912d91567f34c7b043e32d32de116122 | 0.575116 | 3.012961 | false | false | false | false |
rafa-jfet/OFM | ARCHIVOS VHDL/FSM.vhd | 1 | 5,508 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 19:21:00 03/23/2015
-- Design Name:
-- Module Name: FSM - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_logic_arith.ALL;
use IEEE.std_logic_unsigned.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity FSM is
Generic (ancho_bus_dir:integer:=9;
VAL_SAT_CONT:integer:=5208;
ANCHO_CONTADOR:integer:=13;
ULT_DIR_TX : integer := 420);
Port ( clk : in STD_LOGIC;
reset : in STD_LOGIC;
button : in STD_LOGIC;
data_in : in STD_LOGIC_VECTOR(31 downto 0);
direcc : out STD_LOGIC_VECTOR (ancho_bus_dir -1 downto 0);
TX : out STD_LOGIC);
end FSM;
architecture Behavioral of FSM is
type estado is (reposo,
inicio,
test_data,
b_start,
b_0,
b_1,
b_2,
b_3,
b_4,
b_5,
b_6,
b_7,
b_paridad,
b_stop,
espera,
fin);
signal estado_actual: estado;
signal estado_nuevo: estado;
signal dir, p_dir: std_logic_vector (ancho_bus_dir -1 downto 0);
signal cont, p_cont: std_logic_vector (ANCHO_CONTADOR -1 downto 0);
signal byte_tx, p_byte_tx : std_logic_vector (1 downto 0);
signal data, p_data : std_logic_vector (7 downto 0);
begin
direcc <= dir;
maq_estados:process(estado_actual, button, data, cont, dir, byte_tx, data_in)
begin
p_dir <= dir;
p_cont <= cont;
p_byte_tx <= byte_tx;
p_data <= data;
TX <= '1';
case estado_actual is
when reposo =>
TX <= '1';
p_dir <= (others => '0');
p_cont <= (others => '0');
p_byte_tx <= "00";
if button = '1' then
estado_nuevo <= inicio;
else
estado_nuevo <= reposo;
end if;
when inicio =>
TX <= '1';
estado_nuevo <= test_data;
case byte_tx is
when "00" =>
p_data <= data_in (31 downto 24);
when "01" =>
p_data <= data_in (23 downto 16);
when "10" =>
p_data <= data_in (15 downto 8);
when OTHERS =>
p_data <= data_in (7 downto 0);
end case;
when test_data =>
TX <= '1';
if dir = ULT_DIR_TX then
estado_nuevo <= fin;
else
estado_nuevo <= b_start;
end if;
when b_start =>
TX <= '0';
p_cont <= cont +1;
if cont = VAL_SAT_CONT then
p_cont <= (others => '0');
estado_nuevo <= b_0;
else
estado_nuevo <= b_start;
end if;
when b_0 =>
TX <= data(0);
p_cont <= cont +1;
if cont = VAL_SAT_CONT then
p_cont <= (others => '0');
estado_nuevo <= b_1;
else
estado_nuevo <= b_0;
end if;
when b_1 =>
TX <= data(1);
p_cont <= cont +1;
if cont = VAL_SAT_CONT then
p_cont <= (others => '0');
estado_nuevo <= b_2;
else
estado_nuevo <= b_1;
end if;
when b_2 =>
TX <= data(2);
p_cont <= cont +1;
if cont = VAL_SAT_CONT then
p_cont <= (others => '0');
estado_nuevo <= b_3;
else
estado_nuevo <= b_2;
end if;
when b_3 =>
TX <= data(3);
p_cont <= cont +1;
if cont = VAL_SAT_CONT then
p_cont <= (others => '0');
estado_nuevo <= b_4;
else
estado_nuevo <= b_3;
end if;
when b_4 =>
TX <= data(4);
p_cont <= cont +1;
if cont = VAL_SAT_CONT then
p_cont <= (others => '0');
estado_nuevo <= b_5;
else
estado_nuevo <= b_4;
end if;
when b_5 =>
TX <= data(5);
p_cont <= cont +1;
if cont = VAL_SAT_CONT then
p_cont <= (others => '0');
estado_nuevo <= b_6;
else
estado_nuevo <= b_5;
end if;
when b_6 =>
TX <= data(6);
p_cont <= cont +1;
if cont = VAL_SAT_CONT then
p_cont <= (others => '0');
estado_nuevo <= b_7;
else
estado_nuevo <= b_6;
end if;
when b_7 =>
TX <= data(7);
p_cont <= cont +1;
if cont = VAL_SAT_CONT then
p_cont <= (others => '0');
estado_nuevo <= b_paridad;
else
estado_nuevo <= b_7;
end if;
when b_paridad =>
TX <= data(0) xor data(1) xor data(2) xor data(3) xor data(4) xor data(5) xor data(6) xor data(7);
p_cont <= cont + 1;
if cont = VAL_SAT_CONT then
p_cont <= (others => '0');
estado_nuevo <= b_stop;
else
estado_nuevo <= b_paridad;
end if;
when b_stop =>
TX <= '1';
p_cont <= cont + 1;
if cont = VAL_SAT_CONT then
p_cont <= (others => '0');
estado_nuevo <= espera;
else
estado_nuevo <= b_stop;
end if;
when espera =>
p_byte_tx <= byte_tx +1;
if (byte_tx = "11") then
p_dir <= dir +1;
end if;
estado_nuevo <= inicio;
when fin =>
end case;
end process;
sinc:process(reset, clk)
begin
if reset = '1' then
cont <= (others => '0');
estado_actual <= reposo;
dir <= (others => '0');
byte_tx <= (others => '0');
data <= (others => '0');
elsif rising_edge(clk) then
cont <= p_cont;
estado_actual <= estado_nuevo;
dir <= p_dir;
byte_tx <= p_byte_tx;
data <= p_data;
end if;
end process;
end Behavioral;
| gpl-3.0 | bcd695bea70a136a2b228cc0054550df | 0.527052 | 2.741663 | false | false | false | false |
hacklabmikkeli/rough-boy | waveshaper.vhdl | 2 | 3,404 | --
-- Knobs Galore - a free phase distortion synthesiaudio_outer
-- Copyright (C) 2015 Ilmo Euro
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
use work.common.all;
entity waveshaper is
port (EN: in std_logic
;CLK: in std_logic
;THETA: in ctl_signal
;AUDIO_OUT: out voice_signal
;GAIN_IN: in ctl_signal
;GAIN_THRU: out ctl_signal
)
;
end entity;
architecture waveshaper_sin of waveshaper is
type lut_t is array(0 to (ctl_max/4) - 1) of voice_signal;
function init_sin_lut return lut_t is
constant N : real := real(ctl_max);
variable theta, audio_out : real;
variable audio_out_int : integer;
variable retval : lut_t;
begin
for k in lut_t'low to lut_t'high loop
theta := (real(k) / N) * 2.0 * MATH_PI;
audio_out := (sin(theta) * 0.5) + 0.5;
audio_out_int := integer(audio_out * real(voice_max));
if audio_out_int < 0 then
audio_out_int := 0;
elsif audio_out_int > (voice_max - 1) then
audio_out_int := (voice_max - 1);
end if;
retval(k) := to_unsigned(audio_out_int, voice_bits);
end loop;
return retval;
end function init_sin_lut;
constant sin_lut : lut_t := init_sin_lut;
function lookup(theta: ctl_signal; lut: lut_t)
return voice_signal is
constant phase_max : integer := ctl_max / 4;
variable quadrant : unsigned(1 downto 0);
variable phase : integer;
begin
quadrant := theta(ctl_bits-1 downto ctl_bits-2);
phase := to_integer(theta(ctl_bits-3 downto 0));
case theta(ctl_bits-1 downto ctl_bits-2) is
when "00" =>
return lut(phase);
when "01" =>
return lut(phase_max - 1 - phase);
when "10" =>
return not (lut(phase)); -- negate
when others =>
return not (lut(phase_max - 1 - phase)); -- negate
end case;
end function;
signal rom: lut_t := sin_lut;
attribute ram_style: string;
attribute ram_style of rom: signal is "block";
signal s1_audio_out_buf: voice_signal := (others => '0');
signal s1_gain_thru_buf: ctl_signal := (others => '0');
begin
process (CLK)
begin
if EN = '1' and rising_edge(CLK) then
s1_audio_out_buf <= lookup(THETA, rom);
s1_gain_thru_buf <= GAIN_IN;
end if;
end process;
AUDIO_OUT <= s1_audio_out_buf;
GAIN_THRU <= s1_gain_thru_buf;
end architecture;
| gpl-3.0 | 96828afccc60ceab37ec8e5c1bd317bf | 0.577556 | 3.617428 | false | false | false | false |
makestuff/spi-master | vhdl/spi_master.vhdl | 1 | 8,958 | --
-- Copyright (C) 2011, 2013 Chris McClelland
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU Lesser General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU Lesser General Public License for more details.
--
-- You should have received a copy of the GNU Lesser General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity spi_master is
generic (
FAST_COUNT : unsigned(5 downto 0) := "000000"; -- maxcount for fast mode: defaults to sysClk/2 (24MHz @48MHz)
SLOW_COUNT : unsigned(5 downto 0) := "111011"; -- maxcount for slow mode: defaults to sysClk/120 (400kHz @48MHz)
BIT_ORDER : std_logic := '0' -- '0' for LSB first, '1' for MSB first
);
port(
reset_in : in std_logic;
clk_in : in std_logic;
-- Client interface
sendData_in : in std_logic_vector(7 downto 0);
turbo_in : in std_logic;
suppress_in : in std_logic;
sendValid_in : in std_logic;
sendReady_out : out std_logic;
recvData_out : out std_logic_vector(7 downto 0);
recvValid_out : out std_logic;
recvReady_in : in std_logic;
-- SPI interface
spiClk_out : out std_logic;
spiData_out : out std_logic;
spiData_in : in std_logic
);
end entity;
architecture rtl of spi_master is
-- SPI master FSM
type StateType is (
S_IDLE,
S_RECV_COUNT,
S_RECV_NOCOUNT,
S_SCLK_LOW, -- drive LSB on spiData whilst holding spiClk low
S_SCLK_HIGH -- drive LSB on spiData whilst holding spiClk high
);
signal state, state_next : StateType := S_IDLE;
signal shiftOut, shiftOut_next : std_logic_vector(7 downto 0) := (others => '0'); -- outbound shift reg
signal shiftIn, shiftIn_next : std_logic_vector(6 downto 0) := (others => '0'); -- inbound shift reg
signal recvData, recvData_next : std_logic_vector(7 downto 0) := (others => '0'); -- receive side dbl.buf
signal cycleCount, cycleCount_next : unsigned(5 downto 0) := (others => '0'); -- num cycles per 1/2 bit
signal initCeiling, contCeiling : unsigned(5 downto 0) := SLOW_COUNT; -- count init values
signal turbo, turbo_next : std_logic := '0'; -- fast or slow?
signal bitCount, bitCount_next : unsigned(2 downto 0) := (others => '0'); -- num bits remaining
signal suppress, suppress_next : std_logic := '0'; -- suppress output?
begin
-- Infer registers
process(clk_in)
begin
if ( rising_edge(clk_in) ) then
if ( reset_in = '1' ) then
state <= S_IDLE;
shiftOut <= (others => '0');
shiftIn <= (others => '0');
recvData <= (others => '0');
bitCount <= "000";
cycleCount <= (others => '0');
turbo <= '0';
suppress <= '0';
else
state <= state_next;
shiftOut <= shiftOut_next;
shiftIn <= shiftIn_next;
recvData <= recvData_next;
bitCount <= bitCount_next;
cycleCount <= cycleCount_next;
turbo <= turbo_next;
suppress <= suppress_next;
end if;
end if;
end process;
initCeiling <=
FAST_COUNT when turbo_in = '1' else
SLOW_COUNT;
contCeiling <=
FAST_COUNT when turbo = '1' else
SLOW_COUNT;
-- Next state logic
process(
state, sendData_in, suppress_in, sendValid_in, recvData, recvReady_in,
shiftOut, shiftIn, spiData_in, suppress, turbo, turbo_in,
initCeiling, contCeiling, cycleCount, bitCount)
begin
state_next <= state;
shiftOut_next <= shiftOut;
shiftIn_next <= shiftIn;
recvData_next <= recvData;
recvValid_out <= '0';
cycleCount_next <= cycleCount;
bitCount_next <= bitCount;
turbo_next <= turbo;
suppress_next <= suppress;
if ( BIT_ORDER = '1' ) then
spiData_out <= shiftOut(7); -- always drive the MSB on spiData_out
else
spiData_out <= shiftOut(0); -- always drive the LSB on spiData_out
end if;
sendReady_out <= '0'; -- not ready for data
case state is
-- Wait for data on the send pipe for us to clock out
when S_IDLE =>
spiClk_out <= '1';
sendReady_out <= '1'; -- ready for data
if ( sendValid_in = '1' ) then
-- we've got some data to send...prepare to clock it out
state_next <= S_SCLK_LOW; -- spiClk going low
turbo_next <= turbo_in;
suppress_next <= suppress_in;
shiftOut_next <= sendData_in; -- get send byte from FIFO
bitCount_next <= "111"; -- need eight bits for a full byte
cycleCount_next <= initCeiling; -- initialise the delay counter
end if;
-- Drive bit on spiData, and hold spiClk low for cycleCount+1 cycles
when S_SCLK_LOW =>
spiClk_out <= '0';
cycleCount_next <= cycleCount - 1;
if ( cycleCount = 0 ) then
-- Time to move on to S_SCLK_HIGH - prepare to sample input data
state_next <= S_SCLK_HIGH;
if ( BIT_ORDER = '1' ) then
shiftIn_next <= shiftIn(5 downto 0) & spiData_in;
else
shiftIn_next <= spiData_in & shiftIn(6 downto 1);
end if;
cycleCount_next <= contCeiling;
if ( bitCount = 0 ) then
-- Update the recvData register
if ( BIT_ORDER = '1' ) then
recvData_next <= shiftIn(6 downto 0) & spiData_in;
else
recvData_next <= spiData_in & shiftIn(6 downto 0);
end if;
if ( suppress = '0' ) then
state_next <= S_RECV_COUNT;
else
state_next <= S_SCLK_HIGH;
end if;
end if;
end if;
-- Wait for consumption of received byte whilst counting down
when S_RECV_COUNT =>
spiClk_out <= '1';
recvValid_out <= '1';
cycleCount_next <= cycleCount - 1;
if ( cycleCount = 0 ) then
state_next <= S_RECV_NOCOUNT;
end if;
if ( recvReady_in = '1' ) then
if ( cycleCount = 0 ) then
-- Received byte will be consumed, but we're out of time - time to begin new byte if necessary
sendReady_out <= '1';
if ( sendValid_in = '1' ) then
-- There's a new byte to send
state_next <= S_SCLK_LOW;
turbo_next <= turbo_in;
suppress_next <= suppress_in;
shiftOut_next <= sendData_in;
bitCount_next <= "111";
cycleCount_next <= initCeiling;
else
-- Nothing to do, go idle
state_next <= S_IDLE;
end if;
else
-- Received byte will be consumed - go to HIGH state for remainder of count
state_next <= S_SCLK_HIGH;
end if;
else
if ( cycleCount = 0 ) then
-- Received byte will not be consumed yet, and we're out of time - wait in NOCOUNT
state_next <= S_RECV_NOCOUNT;
else
-- Received byte will not be consumed yet, but we're not yet out of time - wait here
end if;
end if;
-- Wait for consumption of received byte; no countdown
when S_RECV_NOCOUNT =>
spiClk_out <= '1';
recvValid_out <= '1';
if ( recvReady_in = '1' ) then
-- Received byte will be consumed - time to begin new byte if necessary
sendReady_out <= '1';
if ( sendValid_in = '1' ) then
-- There's a new byte to send
state_next <= S_SCLK_LOW;
turbo_next <= turbo_in;
suppress_next <= suppress_in;
shiftOut_next <= sendData_in;
bitCount_next <= "111";
cycleCount_next <= initCeiling;
else
-- Nothing to do, go idle
state_next <= S_IDLE;
end if;
end if;
-- Carry on driving bit on spiData, hold spiClk high for four cycles
when S_SCLK_HIGH =>
spiClk_out <= '1';
cycleCount_next <= cycleCount - 1;
if ( cycleCount = 0 ) then
-- Time to move back to S_SCLK_LOW or S_IDLE - shift next bit out on next clock edge
if ( BIT_ORDER = '1' ) then
shiftOut_next <= shiftOut(6 downto 0) & "0";
else
shiftOut_next <= "0" & shiftOut(7 downto 1);
end if;
bitCount_next <= bitCount - 1;
cycleCount_next <= contCeiling;
if ( bitCount = 0 ) then
-- This was the last bit...see if there's another byte to send or go back to idle state
sendReady_out <= '1';
if ( sendValid_in = '1' ) then
-- There's a new byte to send
state_next <= S_SCLK_LOW;
turbo_next <= turbo_in;
suppress_next <= suppress_in;
shiftOut_next <= sendData_in;
bitCount_next <= "111";
cycleCount_next <= initCeiling;
else
-- Nothing to do, go idle
state_next <= S_IDLE;
end if;
else
-- This was not the last bit...do another clock
state_next <= S_SCLK_LOW;
end if;
end if;
end case;
end process;
recvData_out <= recvData;
end architecture;
| gpl-3.0 | feddecba686de6ab672f705e257e003b | 0.60672 | 3.365139 | false | false | false | false |
pmh92/Proyecto-OFDM | test/datawrite.vhd | 1 | 6,090 | -------------------------------------------------------------------------------
--! @file
--! @author Hipolito Guzman-Miranda
--! @brief Writes circuit output to file
-------------------------------------------------------------------------------
--! Use IEEE standard definitions library
library ieee;
--! Use std_logic* signal types
use ieee.std_logic_1164.all;
--! Allows use of arithmetical operations between integers and vectors
use ieee.std_logic_arith.all;
-- Allows writing strings to lines and lines to files
use STD.textio.all;
-- Allows converting std_logic_vector(s) to strings (BIN, HEX, OCT)
use work.image_pkg.all;
-- Allows writing std_logic_vector(s) to line(s) in BIN, HEX, OCT and reading BIN, HEX, OCT vector(s) from line(s)
use ieee.std_logic_textio.all;
-- For print() function
use work.txt_util.all;
--! @brief Writes circuit output data to file
--!
--! @detailed Creates (overwriting if it exists) a file at \c OUTPUT_FILE,
--! writing \c OUTPUT_NIBBLES chars in each line. Data will be written in hex
--! format: 4 bits per character (nibble). Reads \c DATA_WIDTH - bit input \c data
--! and internally reorders it to form complete lines. \c data is only sampled
--! when \c valid is active.
entity datawrite is
generic(
SIMULATION_LABEL : string := "datawrite"; --! Allow to separate messages from different instances in SIMULATION
VERBOSE : boolean := false; --! Print more internal details
DEBUG : boolean := false; --! Print debug info (developers only)
OUTPUT_FILE : string := "./output/datawrite_test.txt"; --! File where data will be stored
OUTPUT_NIBBLES : integer := 2; --! Hex chars on each output line
DATA_WIDTH : integer := 8 --! Width of input data
);
port(
clk : in std_logic; --! Will sample input on rising_edge of this clock
data : in std_logic_vector (DATA_WIDTH-1 downto 0); --! Data to write to file
valid : in std_logic; --! Active high, indicates data is valid
endsim : in std_logic --! Active high, tells the process to close its open files
);
end datawrite;
--! @brief Architecture accumulates input data in a vector which will be written to the output file
architecture pack_lines_and_write of datawrite is
constant NUM_CHUNKS : integer := 4*OUTPUT_NIBBLES / DATA_WIDTH; --! Each line in output file equals to NUM_CHUNKS data of DATA_WIDTH
signal received_data : integer := 0;
begin
assert OUTPUT_NIBBLES > 0
report "datawrite(" & SIMULATION_LABEL & "): OUTPUT_NIBBLES must be a positive non-zero integer"
severity failure;
assert DATA_WIDTH > 0
report "datawrite(" & SIMULATION_LABEL & "): DATA_WIDTH must be a positive non-zero integer"
severity failure;
assert 4*OUTPUT_NIBBLES >= DATA_WIDTH
report "datawrite(" & SIMULATION_LABEL & "): DATA_WIDTH (" & image(DATA_WIDTH) & ") bits must fit into OUTPUT_NIBBLES nibbles (4*" & image(OUTPUT_NIBBLES) & ") bits"
severity failure;
assert (4*OUTPUT_NIBBLES) mod DATA_WIDTH = 0
report "datawrite(" & SIMULATION_LABEL & "): An exact multiple of DATA_WIDTH (" & image(DATA_WIDTH) & ") must fit into OUTPUT_NIBBLES nibbles (4*" & image(OUTPUT_NIBBLES) & ") bits."
severity failure;
--! @brief Accumulates data to form a line, when line is complete it gets written to the output file
--!
--! @detailed Also reports errors and checks for unexpected conditions
datawrite_read : process
file file_pointer : text;
variable current_line : line;
variable expected_data : std_logic_vector (OUTPUT_NIBBLES*4-1 downto 0); -- Data read from file
variable current_data : std_logic_vector (OUTPUT_NIBBLES*4-1 downto 0); -- Data read from input
variable chunk_idx : integer range 0 to NUM_CHUNKS := 0; -- Points to current data chunk in line
variable error_count : integer := 0; -- Store differences between received and expected data
variable correct_count : integer := 0; -- Store number of correct data
begin
print ("datawrite(" & SIMULATION_LABEL & "): NUM_CHUNKS: " & image(NUM_CHUNKS));
print ("datawrite(" & SIMULATION_LABEL & "): opening output file " & OUTPUT_FILE);
file_open(file_pointer, OUTPUT_FILE, WRITE_MODE);
while (endsim /= '1') loop
print (DEBUG, "datawrite(" & SIMULATION_LABEL & "): composing line");
while (chunk_idx < NUM_CHUNKS and endsim /= '1') loop
wait until (rising_edge(clk) or endsim = '1');
if (valid = '1') then
print (DEBUG, "datawrite(" & SIMULATION_LABEL & "): chunk_idx: " & image(chunk_idx));
current_data(DATA_WIDTH*(chunk_idx+1)-1 downto DATA_WIDTH*chunk_idx) := data; -- Put input data in the correct chunk
chunk_idx := chunk_idx + 1;
received_data <= received_data + 1;
end if;
end loop;
if (chunk_idx /= NUM_CHUNKS and chunk_idx /= 0) then
print ("datawrite(" & SIMULATION_LABEL & "): warning: endsim received whilst line not completed. (chunk_idx = " & image(chunk_idx) & ")" );
end if;
-- Avoid writing twice the last line
if (endsim /= '1') then
print ("datawrite(" & SIMULATION_LABEL & "): writing line");
hwrite(current_line, current_data);
writeline(file_pointer, current_line);
end if;
current_data := (others => 'U');
chunk_idx := 0;
end loop;
print (VERBOSE, "datawrite(" & SIMULATION_LABEL & "): " & image(received_data) & " data received");
print (VERBOSE, "datawrite(" & SIMULATION_LABEL & "): Closing output file");
file_close(file_pointer);
wait;
end process datawrite_read;
end pack_lines_and_write;
| gpl-2.0 | f5b626daeebbc692f4c1045c14db7ec3 | 0.598194 | 4.142857 | false | false | false | false |
emogenet/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc873.vhd | 3 | 12,117 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc873.vhd,v 1.2 2001-10-26 16:30:01 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
package c01s03b01x00p12n01i00873pkg is
constant low_number : integer := 0;
constant hi_number : integer := 3;
subtype hi_to_low_range is integer range low_number to hi_number;
type boolean_vector is array (natural range <>) of boolean;
type severity_level_vector is array (natural range <>) of severity_level;
type integer_vector is array (natural range <>) of integer;
type real_vector is array (natural range <>) of real;
type time_vector is array (natural range <>) of time;
type natural_vector is array (natural range <>) of natural;
type positive_vector is array (natural range <>) of positive;
type record_std_package is record
a: boolean;
b: bit;
c:character;
d:severity_level;
e:integer;
f:real;
g:time;
h:natural;
i:positive;
end record;
type array_rec_std is array (natural range <>) of record_std_package;
type four_value is ('Z','0','1','X');
--enumerated type
constant C1 : boolean := true;
constant C2 : bit := '1';
constant C3 : character := 's';
constant C4 : severity_level := note;
constant C5 : integer := 3;
constant C6 : real := 3.0;
constant C7 : time := 3 ns;
constant C8 : natural := 1;
constant C9 : positive := 1;
signal Sin1 : bit_vector(0 to 5) ;
signal Sin2 : boolean_vector(0 to 5) ;
signal Sin4 : severity_level_vector(0 to 5) ;
signal Sin5 : integer_vector(0 to 5) ;
signal Sin6 : real_vector(0 to 5) ;
signal Sin7 : time_vector(0 to 5) ;
signal Sin8 : natural_vector(0 to 5) ;
signal Sin9 : positive_vector(0 to 5) ;
signal Sin10: array_rec_std(0 to 5) ;
end c01s03b01x00p12n01i00873pkg;
use work.c01s03b01x00p12n01i00873pkg.all;
entity c01s03b01x00p12n01i00873ent_a is
port(
sigin1 : in boolean ;
sigout1 : out boolean ;
sigin2 : in bit ;
sigout2 : out bit ;
sigin4 : in severity_level ;
sigout4 : out severity_level ;
sigin5 : in integer ;
sigout5 : out integer ;
sigin6 : in real ;
sigout6 : out real ;
sigin7 : in time ;
sigout7 : out time ;
sigin8 : in natural ;
sigout8 : out natural ;
sigin9 : in positive ;
sigout9 : out positive ;
sigin10 : in record_std_package ;
sigout10 : out record_std_package
);
end;
architecture c01s03b01x00p12n01i00873ent_a of c01s03b01x00p12n01i00873ent_a is
begin
sigout1 <= sigin1;
sigout2 <= sigin2;
sigout4 <= sigin4;
sigout5 <= sigin5;
sigout6 <= sigin6;
sigout7 <= sigin7;
sigout8 <= sigin8;
sigout9 <= sigin9;
sigout10 <= sigin10;
end;
configuration c01s03b01x00p12n01i00873ent_abench of c01s03b01x00p12n01i00873ent_a is
for c01s03b01x00p12n01i00873ent_a
end for;
end;
use work.c01s03b01x00p12n01i00873pkg.all;
entity c01s03b01x00p12n01i00873ent_a1 is
port(
sigin1 : in boolean ;
sigout1 : out boolean ;
sigin2 : in bit ;
sigout2 : out bit ;
sigin4 : in severity_level ;
sigout4 : out severity_level ;
sigin5 : in integer ;
sigout5 : out integer ;
sigin6 : in real ;
sigout6 : out real ;
sigin7 : in time ;
sigout7 : out time ;
sigin8 : in natural ;
sigout8 : out natural ;
sigin9 : in positive ;
sigout9 : out positive ;
sigin10 : in record_std_package ;
sigout10 : out record_std_package
);
end;
architecture c01s03b01x00p12n01i00873ent_a1 of c01s03b01x00p12n01i00873ent_a1 is
begin
sigout1 <= false;
sigout2 <= '0';
sigout4 <= error;
sigout5 <= 6;
sigout6 <= 6.0;
sigout7 <= 6 ns;
sigout8 <= 6;
sigout9 <= 6;
sigout10 <= (false,'0','h',error,6,6.0,6 ns,6,6);
end;
configuration c01s03b01x00p12n01i00873ent_a1bench of c01s03b01x00p12n01i00873ent_a1 is
for c01s03b01x00p12n01i00873ent_a1
end for;
end;
use work.c01s03b01x00p12n01i00873pkg.all;
ENTITY c01s03b01x00p12n01i00873ent IS
generic(
zero : integer := 0;
one : integer := 1;
two : integer := 2;
three: integer := 3;
four : integer := 4;
five : integer := 5;
six : integer := 6;
seven: integer := 7;
eight: integer := 8;
nine : integer := 9;
fifteen:integer:= 15);
port(
dumy : inout bit_vector(zero to three));
END c01s03b01x00p12n01i00873ent;
ARCHITECTURE c01s03b01x00p12n01i00873arch OF c01s03b01x00p12n01i00873ent IS
component c01s03b01x00p12n01i00873ent_a
port(
sigin1 : in boolean ;
sigout1 : out boolean ;
sigin2 : in bit ;
sigout2 : out bit ;
sigin4 : in severity_level ;
sigout4 : out severity_level ;
sigin5 : in integer ;
sigout5 : out integer ;
sigin6 : in real ;
sigout6 : out real ;
sigin7 : in time ;
sigout7 : out time ;
sigin8 : in natural ;
sigout8 : out natural ;
sigin9 : in positive ;
sigout9 : out positive ;
sigin10 : in record_std_package ;
sigout10 : out record_std_package
);
end component;
begin
Sin1(zero) <='1';
Sin2(zero) <= true;
Sin4(zero) <= note;
Sin5(zero) <= 3;
Sin6(zero) <= 3.0;
Sin7(zero) <= 3 ns;
Sin8(zero) <= 1;
Sin9(zero) <= 1;
Sin10(zero) <= (C1,C2,C3,C4,C5,C6,C7,C8,C9);
K:block
BEGIN
T5 : c01s03b01x00p12n01i00873ent_a
port map
(
Sin2(4),Sin2(5),
Sin1(4),Sin1(5),
Sin4(4),Sin4(5),
Sin5(4),Sin5(5),
Sin6(4),Sin6(5),
Sin7(4),Sin7(5),
Sin8(4),Sin8(5),
Sin9(4),Sin9(5),
Sin10(4),Sin10(5)
);
G: for i in zero to three generate
T1:c01s03b01x00p12n01i00873ent_a
port map
(
Sin2(i),Sin2(i+1),
Sin1(i),Sin1(i+1),
Sin4(i),Sin4(i+1),
Sin5(i),Sin5(i+1),
Sin6(i),Sin6(i+1),
Sin7(i),Sin7(i+1),
Sin8(i),Sin8(i+1),
Sin9(i),Sin9(i+1),
Sin10(i),Sin10(i+1)
);
end generate;
end block;
TESTING: PROCESS
variable dumb : bit_vector(zero to three);
BEGIN
wait for 1 ns;
assert Sin1(0) = Sin1(4) report "assignment of Sin1(0) to Sin1(4) is invalid through entity port" severity failure;
assert Sin2(0) = Sin2(4) report "assignment of Sin2(0) to Sin2(4) is invalid through entity port" severity failure;
assert Sin4(0) = Sin4(4) report "assignment of Sin4(0) to Sin4(4) is invalid through entity port" severity failure;
assert Sin5(0) = Sin5(4) report "assignment of Sin5(0) to Sin5(4) is invalid through entity port" severity failure;
assert Sin6(0) = Sin6(4) report "assignment of Sin6(0) to Sin6(4) is invalid through entity port" severity failure;
assert Sin7(0) = Sin7(4) report "assignment of Sin7(0) to Sin7(4) is invalid through entity port" severity failure;
assert Sin8(0) = Sin8(4) report "assignment of Sin8(0) to Sin8(4) is invalid through entity port" severity failure;
assert Sin9(0) = Sin9(4) report "assignment of Sin9(0) to Sin9(4) is invalid through entity port" severity failure;
assert Sin10(0) = Sin10(4) report "assignment of Sin10(0) to Sin10(4) is invalid through entity port" severity failure;
assert Sin1(5) = '0' report "assignment of Sin1(5) to Sin1(4) is invalid through entity port" severity failure;
assert Sin2(5) = false report "assignment of Sin2(5) to Sin2(4) is invalid through entity port" severity failure;
assert Sin4(5) = error report "assignment of Sin4(5) to Sin4(4) is invalid through entity port" severity failure;
assert Sin5(5) = 6 report "assignment of Sin5(5) to Sin5(4) is invalid through entity port" severity failure;
assert Sin6(5) = 6.0 report "assignment of Sin6(5) to Sin6(4) is invalid through entity port" severity failure;
assert Sin7(5) = 6 ns report "assignment of Sin7(5) to Sin7(4) is invalid through entity port" severity failure;
assert Sin8(5) = 6 report "assignment of Sin8(5) to Sin8(4) is invalid through entity port" severity failure;
assert Sin9(5) = 6 report "assignment of Sin9(5) to Sin9(4) is invalid through entity port" severity failure;
assert Sin10(5) = (false,'0','h',error,6,6.0,6 ns,6,6) report "assignment of Sin15(5) to Sin15(4) is invalid through entity port" severity failure;
assert NOT( Sin1(0) = sin1(4) and
Sin2(0) = Sin2(4) and
Sin4(0) = Sin4(4) and
Sin5(0) = Sin5(4) and
Sin6(0) = Sin6(4) and
Sin7(0) = Sin7(4) and
Sin8(0) = Sin8(4) and
Sin9(0) = Sin9(4) and
Sin10(0)= Sin10(4) and
Sin1(5) = '0' and
Sin2(5) = FALSE and
Sin4(5) = error and
Sin5(5) = 6 and
Sin6(5) = 6.0 and
Sin7(5) = 6 ns and
Sin8(5) = 6 and
Sin9(5) = 6 and
Sin10(5)=(False,'0','h',error,6,6.0,6 ns,6,6))
report "***PASSED TEST: c01s03b01x00p12n01i00873"
severity NOTE;
assert ( Sin1(0) = sin1(4) and
Sin2(0) = Sin2(4) and
Sin4(0) = Sin4(4) and
Sin5(0) = Sin5(4) and
Sin6(0) = Sin6(4) and
Sin7(0) = Sin7(4) and
Sin8(0) = Sin8(4) and
Sin9(0) = Sin9(4) and
Sin10(0)= Sin10(4) and
Sin1(5) = '0' and
Sin2(5) = FALSE and
Sin4(5) = error and
Sin5(5) = 6 and
Sin6(5) = 6.0 and
Sin7(5) = 6 ns and
Sin8(5) = 6 and
Sin9(5) = 6 and
Sin10(5)=(False,'0','h',error,6,6.0,6 ns,6,6))
report "***FAILED TEST: c01s03b01x00p12n01i00873 - If such a block configuration contains an index specification that is a discrete range, then the block configuration applies to those implicit block statements that are generated for the specified range of values of the corresponding generate index."
severity ERROR;
wait;
END PROCESS TESTING;
END c01s03b01x00p12n01i00873arch;
configuration c01s03b01x00p12n01i00873cfg of c01s03b01x00p12n01i00873ent is
for c01s03b01x00p12n01i00873arch
for K
for others:c01s03b01x00p12n01i00873ent_a use configuration work.c01s03b01x00p12n01i00873ent_a1bench;
end for;
for G(0 to 3)
for T1 :c01s03b01x00p12n01i00873ent_a
use configuration work.c01s03b01x00p12n01i00873ent_abench;
end for;
end for;
end for;
end for;
end;
| gpl-2.0 | e758a3e5bd051957f96b6f4d7f316533 | 0.590328 | 3.181985 | false | false | false | false |
rafa-jfet/OFM | ARCHIVOS VHDL/mapper_completo.vhd | 1 | 3,566 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 17:26:24 07/04/2015
-- Design Name:
-- Module Name: mapper_completo - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity mapper_completo is
Port ( clk : in STD_LOGIC;
reset : in STD_LOGIC;
bit_in : in STD_LOGIC_VECTOR (0 downto 0);
ok_bit_in : in STD_LOGIC;
modulation : in STD_LOGIC_VECTOR (2 downto 0);
dir_data : out STD_LOGIC_VECTOR (6 downto 0);
write_data : out STD_LOGIC_VECTOR (0 downto 0);
data_out : out STD_LOGIC_VECTOR (15 downto 0);
ok_data : out STD_LOGIC);
end mapper_completo;
architecture Behavioral of mapper_completo is
-- señales de salida del gray2angleinc, entrada al mapper
signal ang_inc : STD_LOGIC_VECTOR (2 downto 0);
signal ok_ang_inc : STD_LOGIC;
component gray2angleinc is
Port ( clk : in STD_LOGIC;
reset : in STD_LOGIC;
bit_in : in STD_LOGIC_VECTOR (0 downto 0);
ok_bit_in : in STD_LOGIC;
modulation : in STD_LOGIC_VECTOR (2 downto 0);
anginc_out : out STD_LOGIC_VECTOR (2 downto 0);
ok_anginc_out : out STD_LOGIC);
end component;
component mapper is
Generic ( DIR_INICIAL : STD_LOGIC_VECTOR (6 downto 0) := "0010000"; -- 16
DIR_FINAL : INTEGER := 112;
pos_A2 : STD_LOGIC_VECTOR (7 downto 0) := "01100100"; -- 100
pos_A1 : STD_LOGIC_VECTOR (7 downto 0) := "01000111"; -- 71
A0 : STD_LOGIC_VECTOR (7 downto 0) := "00000000"; -- 0
neg_A1 : STD_LOGIC_VECTOR (7 downto 0) := "10111001"; -- -71
neg_A2 : STD_LOGIC_VECTOR (7 downto 0) := "10011100"); -- -100
Port ( clk : in STD_LOGIC;
reset : in STD_LOGIC;
anginc : in STD_LOGIC_VECTOR (2 downto 0);
ok_anginc : in STD_LOGIC;
dir_data : out STD_LOGIC_VECTOR (6 downto 0);
write_data : out STD_LOGIC_VECTOR (0 downto 0);
Q_data : out STD_LOGIC_VECTOR (7 downto 0) := A0;
I_data : out STD_LOGIC_VECTOR (7 downto 0) := neg_A2;
ok_data : out STD_LOGIC);
end component;
begin
conv_gray_to_ang : gray2angleinc
Port map ( clk => clk,
reset => reset,
bit_in => bit_in,
ok_bit_in => ok_bit_in,
modulation => modulation,
anginc_out => ang_inc, --
ok_anginc_out => ok_ang_inc); --
mapp : mapper
Generic map( DIR_INICIAL => "0010000", -- 16
DIR_FINAL => 112,
pos_A2 => "01100100", -- 100
pos_A1 => "01000111", -- 71
A0 => "00000000", -- 0
neg_A1 => "10111001", -- -71
neg_A2 => "10011100") -- -100
Port map ( clk => clk,
reset => reset,
anginc => ang_inc, --
ok_anginc => ok_ang_inc, --
dir_data => dir_data,
write_data => write_data,
Q_data => data_out(7 downto 0),
I_data => data_out(15 downto 8),
ok_data => ok_data);
end Behavioral;
| gpl-3.0 | d2e73c254ab2b289e41eea7124586d8f | 0.554683 | 3.380095 | false | false | false | false |
emogenet/ghdl | libraries/ieee/math_complex.vhdl | 4 | 40,109 | ------------------------------------------------------------------------
--
-- Copyright 1996 by IEEE. All rights reserved.
--
-- This source file is an essential part of IEEE Std 1076.2-1996, IEEE Standard
-- VHDL Mathematical Packages. This source file may not be copied, sold, or
-- included with software that is sold without written permission from the IEEE
-- Standards Department. This source file may be used to implement this standard
-- and may be distributed in compiled form in any manner so long as the
-- compiled form does not allow direct decompilation of the original source file.
-- This source file may be copied for individual use between licensed users.
-- This source file is provided on an AS IS basis. The IEEE disclaims ANY
-- WARRANTY EXPRESS OR IMPLIED INCLUDING ANY WARRANTY OF MERCHANTABILITY
-- AND FITNESS FOR USE FOR A PARTICULAR PURPOSE. The user of the source
-- file shall indemnify and hold IEEE harmless from any damages or liability
-- arising out of the use thereof.
--
-- Title: Standard VHDL Mathematical Packages (IEEE Std 1076.2-1996,
-- MATH_COMPLEX)
--
-- Library: This package shall be compiled into a library
-- symbolically named IEEE.
--
-- Developers: IEEE DASC VHDL Mathematical Packages Working Group
--
-- Purpose: This package defines a standard for designers to use in
-- describing VHDL models that make use of common COMPLEX
-- constants and common COMPLEX mathematical functions and
-- operators.
--
-- Limitation: The values generated by the functions in this package may
-- vary from platform to platform, and the precision of results
-- is only guaranteed to be the minimum required by IEEE Std 1076-
-- 1993.
--
-- Notes:
-- No declarations or definitions shall be included in, or
-- excluded from, this package.
-- The "package declaration" defines the types, subtypes, and
-- declarations of MATH_COMPLEX.
-- The standard mathematical definition and conventional meaning
-- of the mathematical functions that are part of this standard
-- represent the formal semantics of the implementation of the
-- MATH_COMPLEX package declaration. The purpose of the
-- MATH_COMPLEX package body is to provide a guideline for
-- implementations to verify their implementation of MATH_COMPLEX.
-- Tool developers may choose to implement the package body in
-- the most efficient manner available to them.
--
-- -----------------------------------------------------------------------------
-- Version : 1.5
-- Date : 24 July 1996
-- -----------------------------------------------------------------------------
use WORK.MATH_REAL.all;
package MATH_COMPLEX is
constant CopyRightNotice: STRING
:= "Copyright 1996 IEEE. All rights reserved.";
--
-- Type Definitions
--
type COMPLEX is
record
RE: REAL; -- Real part
IM: REAL; -- Imaginary part
end record;
subtype POSITIVE_REAL is REAL range 0.0 to REAL'HIGH;
subtype PRINCIPAL_VALUE is REAL range -MATH_PI to MATH_PI;
type COMPLEX_POLAR is
record
MAG: POSITIVE_REAL; -- Magnitude
ARG: PRINCIPAL_VALUE; -- Angle in radians; -MATH_PI is illegal
end record;
--
-- Constant Definitions
--
constant MATH_CBASE_1: COMPLEX := COMPLEX'(1.0, 0.0);
constant MATH_CBASE_J: COMPLEX := COMPLEX'(0.0, 1.0);
constant MATH_CZERO: COMPLEX := COMPLEX'(0.0, 0.0);
--
-- Overloaded equality and inequality operators for COMPLEX_POLAR
-- (equality and inequality operators for COMPLEX are predefined)
--
function "=" ( L: in COMPLEX_POLAR; R: in COMPLEX_POLAR ) return BOOLEAN;
-- Purpose:
-- Returns TRUE if L is equal to R and returns FALSE otherwise
-- Special values:
-- COMPLEX_POLAR'(0.0, X) = COMPLEX_POLAR'(0.0, Y) returns TRUE
-- regardless of the value of X and Y.
-- Domain:
-- L in COMPLEX_POLAR and L.ARG /= -MATH_PI
-- R in COMPLEX_POLAR and R.ARG /= -MATH_PI
-- Error conditions:
-- Error if L.ARG = -MATH_PI
-- Error if R.ARG = -MATH_PI
-- Range:
-- "="(L,R) is either TRUE or FALSE
-- Notes:
-- None
function "/=" ( L: in COMPLEX_POLAR; R: in COMPLEX_POLAR ) return BOOLEAN;
-- Purpose:
-- Returns TRUE if L is not equal to R and returns FALSE
-- otherwise
-- Special values:
-- COMPLEX_POLAR'(0.0, X) /= COMPLEX_POLAR'(0.0, Y) returns
-- FALSE regardless of the value of X and Y.
-- Domain:
-- L in COMPLEX_POLAR and L.ARG /= -MATH_PI
-- R in COMPLEX_POLAR and R.ARG /= -MATH_PI
-- Error conditions:
-- Error if L.ARG = -MATH_PI
-- Error if R.ARG = -MATH_PI
-- Range:
-- "/="(L,R) is either TRUE or FALSE
-- Notes:
-- None
--
-- Function Declarations
--
function CMPLX(X: in REAL; Y: in REAL:= 0.0 ) return COMPLEX;
-- Purpose:
-- Returns COMPLEX number X + iY
-- Special values:
-- None
-- Domain:
-- X in REAL
-- Y in REAL
-- Error conditions:
-- None
-- Range:
-- CMPLX(X,Y) is mathematically unbounded
-- Notes:
-- None
function GET_PRINCIPAL_VALUE(X: in REAL ) return PRINCIPAL_VALUE;
-- Purpose:
-- Returns principal value of angle X; X in radians
-- Special values:
-- None
-- Domain:
-- X in REAL
-- Error conditions:
-- None
-- Range:
-- -MATH_PI < GET_PRINCIPAL_VALUE(X) <= MATH_PI
-- Notes:
-- None
function COMPLEX_TO_POLAR(Z: in COMPLEX ) return COMPLEX_POLAR;
-- Purpose:
-- Returns principal value COMPLEX_POLAR of Z
-- Special values:
-- COMPLEX_TO_POLAR(MATH_CZERO) = COMPLEX_POLAR'(0.0, 0.0)
-- COMPLEX_TO_POLAR(Z) = COMPLEX_POLAR'(ABS(Z.IM),
-- SIGN(Z.IM)*MATH_PI_OVER_2) if Z.RE = 0.0
-- Domain:
-- Z in COMPLEX
-- Error conditions:
-- None
-- Range:
-- result.MAG >= 0.0
-- -MATH_PI < result.ARG <= MATH_PI
-- Notes:
-- None
function POLAR_TO_COMPLEX(Z: in COMPLEX_POLAR ) return COMPLEX;
-- Purpose:
-- Returns COMPLEX value of Z
-- Special values:
-- None
-- Domain:
-- Z in COMPLEX_POLAR and Z.ARG /= -MATH_PI
-- Error conditions:
-- Error if Z.ARG = -MATH_PI
-- Range:
-- POLAR_TO_COMPLEX(Z) is mathematically unbounded
-- Notes:
-- None
function "ABS"(Z: in COMPLEX ) return POSITIVE_REAL;
-- Purpose:
-- Returns absolute value (magnitude) of Z
-- Special values:
-- None
-- Domain:
-- Z in COMPLEX
-- Error conditions:
-- None
-- Range:
-- ABS(Z) is mathematically unbounded
-- Notes:
-- ABS(Z) = SQRT(Z.RE*Z.RE + Z.IM*Z.IM)
function "ABS"(Z: in COMPLEX_POLAR ) return POSITIVE_REAL;
-- Purpose:
-- Returns absolute value (magnitude) of Z
-- Special values:
-- None
-- Domain:
-- Z in COMPLEX_POLAR and Z.ARG /= -MATH_PI
-- Error conditions:
-- Error if Z.ARG = -MATH_PI
-- Range:
-- ABS(Z) >= 0.0
-- Notes:
-- ABS(Z) = Z.MAG
function ARG(Z: in COMPLEX ) return PRINCIPAL_VALUE;
-- Purpose:
-- Returns argument (angle) in radians of the principal
-- value of Z
-- Special values:
-- ARG(Z) = 0.0 if Z.RE >= 0.0 and Z.IM = 0.0
-- ARG(Z) = SIGN(Z.IM)*MATH_PI_OVER_2 if Z.RE = 0.0
-- ARG(Z) = MATH_PI if Z.RE < 0.0 and Z.IM = 0.0
-- Domain:
-- Z in COMPLEX
-- Error conditions:
-- None
-- Range:
-- -MATH_PI < ARG(Z) <= MATH_PI
-- Notes:
-- ARG(Z) = ARCTAN(Z.IM, Z.RE)
function ARG(Z: in COMPLEX_POLAR ) return PRINCIPAL_VALUE;
-- Purpose:
-- Returns argument (angle) in radians of the principal
-- value of Z
-- Special values:
-- None
-- Domain:
-- Z in COMPLEX_POLAR and Z.ARG /= -MATH_PI
-- Error conditions:
-- Error if Z.ARG = -MATH_PI
-- Range:
-- -MATH_PI < ARG(Z) <= MATH_PI
-- Notes:
-- ARG(Z) = Z.ARG
function "-" (Z: in COMPLEX ) return COMPLEX;
-- Purpose:
-- Returns unary minus of Z
-- Special values:
-- None
-- Domain:
-- Z in COMPLEX
-- Error conditions:
-- None
-- Range:
-- "-"(Z) is mathematically unbounded
-- Notes:
-- Returns -x -jy for Z= x + jy
function "-" (Z: in COMPLEX_POLAR ) return COMPLEX_POLAR;
-- Purpose:
-- Returns principal value of unary minus of Z
-- Special values:
-- "-"(Z) = COMPLEX_POLAR'(Z.MAG, MATH_PI) if Z.ARG = 0.0
-- Domain:
-- Z in COMPLEX_POLAR and Z.ARG /= -MATH_PI
-- Error conditions:
-- Error if Z.ARG = -MATH_PI
-- Range:
-- result.MAG >= 0.0
-- -MATH_PI < result.ARG <= MATH_PI
-- Notes:
-- Returns COMPLEX_POLAR'(Z.MAG, Z.ARG - SIGN(Z.ARG)*MATH_PI) if
-- Z.ARG /= 0.0
function CONJ (Z: in COMPLEX) return COMPLEX;
-- Purpose:
-- Returns complex conjugate of Z
-- Special values:
-- None
-- Domain:
-- Z in COMPLEX
-- Error conditions:
-- None
-- Range:
-- CONJ(Z) is mathematically unbounded
-- Notes:
-- Returns x -jy for Z= x + jy
function CONJ (Z: in COMPLEX_POLAR) return COMPLEX_POLAR;
-- Purpose:
-- Returns principal value of complex conjugate of Z
-- Special values:
-- CONJ(Z) = COMPLEX_POLAR'(Z.MAG, MATH_PI) if Z.ARG = MATH_PI
-- Domain:
-- Z in COMPLEX_POLAR and Z.ARG /= -MATH_PI
-- Error conditions:
-- Error if Z.ARG = -MATH_PI
-- Range:
-- result.MAG >= 0.0
-- -MATH_PI < result.ARG <= MATH_PI
-- Notes:
-- Returns COMPLEX_POLAR'(Z.MAG, -Z.ARG) if Z.ARG /= MATH_PI
function SQRT(Z: in COMPLEX ) return COMPLEX;
-- Purpose:
-- Returns square root of Z with positive real part
-- or, if the real part is zero, the one with nonnegative
-- imaginary part
-- Special values:
-- SQRT(MATH_CZERO) = MATH_CZERO
-- Domain:
-- Z in COMPLEX
-- Error conditions:
-- None
-- Range:
-- SQRT(Z) is mathematically unbounded
-- Notes:
-- None
function SQRT(Z: in COMPLEX_POLAR ) return COMPLEX_POLAR;
-- Purpose:
-- Returns square root of Z with positive real part
-- or, if the real part is zero, the one with nonnegative
-- imaginary part
-- Special values:
-- SQRT(Z) = COMPLEX_POLAR'(0.0, 0.0) if Z.MAG = 0.0
-- Domain:
-- Z in COMPLEX_POLAR and Z.ARG /= -MATH_PI
-- Error conditions:
-- Error if Z.ARG = -MATH_PI
-- Range:
-- result.MAG >= 0.0
-- -MATH_PI < result.ARG <= MATH_PI
-- Notes:
-- None
function EXP(Z: in COMPLEX ) return COMPLEX;
-- Purpose:
-- Returns exponential of Z
-- Special values:
-- EXP(MATH_CZERO) = MATH_CBASE_1
-- EXP(Z) = -MATH_CBASE_1 if Z.RE = 0.0 and ABS(Z.IM) = MATH_PI
-- EXP(Z) = SIGN(Z.IM)*MATH_CBASE_J if Z.RE = 0.0 and
-- ABS(Z.IM) = MATH_PI_OVER_2
-- Domain:
-- Z in COMPLEX
-- Error conditions:
-- None
-- Range:
-- EXP(Z) is mathematically unbounded
-- Notes:
-- None
function EXP(Z: in COMPLEX_POLAR ) return COMPLEX_POLAR;
-- Purpose:
-- Returns principal value of exponential of Z
-- Special values:
-- EXP(Z) = COMPLEX_POLAR'(1.0, 0.0) if Z.MAG =0.0 and
-- Z.ARG = 0.0
-- EXP(Z) = COMPLEX_POLAR'(1.0, MATH_PI) if Z.MAG = MATH_PI and
-- ABS(Z.ARG) = MATH_PI_OVER_2
-- EXP(Z) = COMPLEX_POLAR'(1.0, MATH_PI_OVER_2) if
-- Z.MAG = MATH_PI_OVER_2 and
-- Z.ARG = MATH_PI_OVER_2
-- EXP(Z) = COMPLEX_POLAR'(1.0, -MATH_PI_OVER_2) if
-- Z.MAG = MATH_PI_OVER_2 and
-- Z.ARG = -MATH_PI_OVER_2
-- Domain:
-- Z in COMPLEX_POLAR and Z.ARG /= -MATH_PI
-- Error conditions:
-- Error if Z.ARG = -MATH_PI
-- Range:
-- result.MAG >= 0.0
-- -MATH_PI < result.ARG <= MATH_PI
-- Notes:
-- None
function LOG(Z: in COMPLEX ) return COMPLEX;
-- Purpose:
-- Returns natural logarithm of Z
-- Special values:
-- LOG(MATH_CBASE_1) = MATH_CZERO
-- LOG(-MATH_CBASE_1) = COMPLEX'(0.0, MATH_PI)
-- LOG(MATH_CBASE_J) = COMPLEX'(0.0, MATH_PI_OVER_2)
-- LOG(-MATH_CBASE_J) = COMPLEX'(0.0, -MATH_PI_OVER_2)
-- LOG(Z) = MATH_CBASE_1 if Z = COMPLEX'(MATH_E, 0.0)
-- Domain:
-- Z in COMPLEX and ABS(Z) /= 0.0
-- Error conditions:
-- Error if ABS(Z) = 0.0
-- Range:
-- LOG(Z) is mathematically unbounded
-- Notes:
-- None
function LOG2(Z: in COMPLEX ) return COMPLEX;
-- Purpose:
-- Returns logarithm base 2 of Z
-- Special values:
-- LOG2(MATH_CBASE_1) = MATH_CZERO
-- LOG2(Z) = MATH_CBASE_1 if Z = COMPLEX'(2.0, 0.0)
-- Domain:
-- Z in COMPLEX and ABS(Z) /= 0.0
-- Error conditions:
-- Error if ABS(Z) = 0.0
-- Range:
-- LOG2(Z) is mathematically unbounded
-- Notes:
-- None
function LOG10(Z: in COMPLEX ) return COMPLEX;
-- Purpose:
-- Returns logarithm base 10 of Z
-- Special values:
-- LOG10(MATH_CBASE_1) = MATH_CZERO
-- LOG10(Z) = MATH_CBASE_1 if Z = COMPLEX'(10.0, 0.0)
-- Domain:
-- Z in COMPLEX and ABS(Z) /= 0.0
-- Error conditions:
-- Error if ABS(Z) = 0.0
-- Range:
-- LOG10(Z) is mathematically unbounded
-- Notes:
-- None
function LOG(Z: in COMPLEX_POLAR ) return COMPLEX_POLAR;
-- Purpose:
-- Returns principal value of natural logarithm of Z
-- Special values:
-- LOG(Z) = COMPLEX_POLAR'(0.0, 0.0) if Z.MAG = 1.0 and
-- Z.ARG = 0.0
-- LOG(Z) = COMPLEX_POLAR'(MATH_PI, MATH_PI_OVER_2) if
-- Z.MAG = 1.0 and Z.ARG = MATH_PI
-- LOG(Z) = COMPLEX_POLAR'(MATH_PI_OVER_2, MATH_PI_OVER_2) if
-- Z.MAG = 1.0 and Z.ARG = MATH_PI_OVER_2
-- LOG(Z) = COMPLEX_POLAR'(MATH_PI_OVER_2, -MATH_PI_OVER_2) if
-- Z.MAG = 1.0 and Z.ARG = -MATH_PI_OVER_2
-- LOG(Z) = COMPLEX_POLAR'(1.0, 0.0) if Z.MAG = MATH_E and
-- Z.ARG = 0.0
-- Domain:
-- Z in COMPLEX_POLAR and Z.ARG /= -MATH_PI
-- Z.MAG /= 0.0
-- Error conditions:
-- Error if Z.ARG = -MATH_PI
-- Error if Z.MAG = 0.0
-- Range:
-- result.MAG >= 0.0
-- -MATH_PI < result.ARG <= MATH_PI
-- Notes:
-- None
function LOG2(Z: in COMPLEX_POLAR ) return COMPLEX_POLAR;
-- Purpose:
-- Returns principal value of logarithm base 2 of Z
-- Special values:
-- LOG2(Z) = COMPLEX_POLAR'(0.0, 0.0) if Z.MAG = 1.0 and
-- Z.ARG = 0.0
-- LOG2(Z) = COMPLEX_POLAR'(1.0, 0.0) if Z.MAG = 2.0 and
-- Z.ARG = 0.0
-- Domain:
-- Z in COMPLEX_POLAR and Z.ARG /= -MATH_PI
-- Z.MAG /= 0.0
-- Error conditions:
-- Error if Z.ARG = -MATH_PI
-- Error if Z.MAG = 0.0
-- Range:
-- result.MAG >= 0.0
-- -MATH_PI < result.ARG <= MATH_PI
-- Notes:
-- None
function LOG10(Z: in COMPLEX_POLAR ) return COMPLEX_POLAR;
-- Purpose:
-- Returns principal value of logarithm base 10 of Z
-- Special values:
-- LOG10(Z) = COMPLEX_POLAR'(0.0, 0.0) if Z.MAG = 1.0 and
-- Z.ARG = 0.0
-- LOG10(Z) = COMPLEX_POLAR'(1.0, 0.0) if Z.MAG = 10.0 and
-- Z.ARG = 0.0
-- Domain:
-- Z in COMPLEX_POLAR and Z.ARG /= -MATH_PI
-- Z.MAG /= 0.0
-- Error conditions:
-- Error if Z.ARG = -MATH_PI
-- Error if Z.MAG = 0.0
-- Range:
-- result.MAG >= 0.0
-- -MATH_PI < result.ARG <= MATH_PI
-- Notes:
-- None
function LOG(Z: in COMPLEX; BASE: in REAL) return COMPLEX;
-- Purpose:
-- Returns logarithm base BASE of Z
-- Special values:
-- LOG(MATH_CBASE_1, BASE) = MATH_CZERO
-- LOG(Z,BASE) = MATH_CBASE_1 if Z = COMPLEX'(BASE, 0.0)
-- Domain:
-- Z in COMPLEX and ABS(Z) /= 0.0
-- BASE > 0.0
-- BASE /= 1.0
-- Error conditions:
-- Error if ABS(Z) = 0.0
-- Error if BASE <= 0.0
-- Error if BASE = 1.0
-- Range:
-- LOG(Z,BASE) is mathematically unbounded
-- Notes:
-- None
function LOG(Z: in COMPLEX_POLAR; BASE: in REAL ) return COMPLEX_POLAR;
-- Purpose:
-- Returns principal value of logarithm base BASE of Z
-- Special values:
-- LOG(Z, BASE) = COMPLEX_POLAR'(0.0, 0.0) if Z.MAG = 1.0 and
-- Z.ARG = 0.0
-- LOG(Z, BASE) = COMPLEX_POLAR'(1.0, 0.0) if Z.MAG = BASE and
-- Z.ARG = 0.0
-- Domain:
-- Z in COMPLEX_POLAR and Z.ARG /= -MATH_PI
-- Z.MAG /= 0.0
-- BASE > 0.0
-- BASE /= 1.0
-- Error conditions:
-- Error if Z.ARG = -MATH_PI
-- Error if Z.MAG = 0.0
-- Error if BASE <= 0.0
-- Error if BASE = 1.0
-- Range:
-- result.MAG >= 0.0
-- -MATH_PI < result.ARG <= MATH_PI
-- Notes:
-- None
function SIN (Z : in COMPLEX ) return COMPLEX;
-- Purpose:
-- Returns sine of Z
-- Special values:
-- SIN(MATH_CZERO) = MATH_CZERO
-- SIN(Z) = MATH_CZERO if Z = COMPLEX'(MATH_PI, 0.0)
-- Domain:
-- Z in COMPLEX
-- Error conditions:
-- None
-- Range:
-- ABS(SIN(Z)) <= SQRT(SIN(Z.RE)*SIN(Z.RE) +
-- SINH(Z.IM)*SINH(Z.IM))
-- Notes:
-- None
function SIN (Z : in COMPLEX_POLAR ) return COMPLEX_POLAR;
-- Purpose:
-- Returns principal value of sine of Z
-- Special values:
-- SIN(Z) = COMPLEX_POLAR'(0.0, 0.0) if Z.MAG = 0.0 and
-- Z.ARG = 0.0
-- SIN(Z) = COMPLEX_POLAR'(0.0, 0.0) if Z.MAG = MATH_PI and
-- Z.ARG = 0.0
-- Domain:
-- Z in COMPLEX_POLAR and Z.ARG /= -MATH_PI
-- Error conditions:
-- Error if Z.ARG = -MATH_PI
-- Range:
-- result.MAG >= 0.0
-- -MATH_PI < result.ARG <= MATH_PI
-- Notes:
-- None
function COS (Z : in COMPLEX ) return COMPLEX;
-- Purpose:
-- Returns cosine of Z
-- Special values:
-- COS(Z) = MATH_CZERO if Z = COMPLEX'(MATH_PI_OVER_2, 0.0)
-- COS(Z) = MATH_CZERO if Z = COMPLEX'(-MATH_PI_OVER_2, 0.0)
-- Domain:
-- Z in COMPLEX
-- Error conditions:
-- None
-- Range:
-- ABS(COS(Z)) <= SQRT(COS(Z.RE)*COS(Z.RE) +
-- SINH(Z.IM)*SINH(Z.IM))
-- Notes:
-- None
function COS (Z : in COMPLEX_POLAR ) return COMPLEX_POLAR;
-- Purpose:
-- Returns principal value of cosine of Z
-- Special values:
-- COS(Z) = COMPLEX_POLAR'(0.0, 0.0) if Z.MAG = MATH_PI_OVER_2
-- and Z.ARG = 0.0
-- COS(Z) = COMPLEX_POLAR'(0.0, 0.0) if Z.MAG = MATH_PI_OVER_2
-- and Z.ARG = MATH_PI
-- Domain:
-- Z in COMPLEX_POLAR and Z.ARG /= -MATH_PI
-- Error conditions:
-- Error if Z.ARG = -MATH_PI
-- Range:
-- result.MAG >= 0.0
-- -MATH_PI < result.ARG <= MATH_PI
-- Notes:
-- None
function SINH (Z : in COMPLEX ) return COMPLEX;
-- Purpose:
-- Returns hyperbolic sine of Z
-- Special values:
-- SINH(MATH_CZERO) = MATH_CZERO
-- SINH(Z) = MATH_CZERO if Z.RE = 0.0 and Z.IM = MATH_PI
-- SINH(Z) = MATH_CBASE_J if Z.RE = 0.0 and
-- Z.IM = MATH_PI_OVER_2
-- SINH(Z) = -MATH_CBASE_J if Z.RE = 0.0 and
-- Z.IM = -MATH_PI_OVER_2
-- Domain:
-- Z in COMPLEX
-- Error conditions:
-- None
-- Range:
-- ABS(SINH(Z)) <= SQRT(SINH(Z.RE)*SINH(Z.RE) +
-- SIN(Z.IM)*SIN(Z.IM))
-- Notes:
-- None
function SINH (Z : in COMPLEX_POLAR ) return COMPLEX_POLAR;
-- Purpose:
-- Returns principal value of hyperbolic sine of Z
-- Special values:
-- SINH(Z) = COMPLEX_POLAR'(0.0, 0.0) if Z.MAG = 0.0 and
-- Z.ARG = 0.0
-- SINH(Z) = COMPLEX_POLAR'(0.0, 0.0) if Z.MAG = MATH_PI and
-- Z.ARG = MATH_PI_OVER_2
-- SINH(Z) = COMPLEX_POLAR'(1.0, MATH_PI_OVER_2) if Z.MAG =
-- MATH_PI_OVER_2 and Z.ARG = MATH_PI_OVER_2
-- SINH(Z) = COMPLEX_POLAR'(1.0, -MATH_PI_OVER_2) if Z.MAG =
-- MATH_PI_OVER_2 and Z.ARG = -MATH_PI_OVER_2
-- Domain:
-- Z in COMPLEX_POLAR and Z.ARG /= -MATH_PI
-- Error conditions:
-- Error if Z.ARG = -MATH_PI
-- Range:
-- result.MAG >= 0.0
-- -MATH_PI < result.ARG <= MATH_PI
-- Notes:
-- None
function COSH (Z : in COMPLEX ) return COMPLEX;
-- Purpose:
-- Returns hyperbolic cosine of Z
-- Special values:
-- COSH(MATH_CZERO) = MATH_CBASE_1
-- COSH(Z) = -MATH_CBASE_1 if Z.RE = 0.0 and Z.IM = MATH_PI
-- COSH(Z) = MATH_CZERO if Z.RE = 0.0 and Z.IM = MATH_PI_OVER_2
-- COSH(Z) = MATH_CZERO if Z.RE = 0.0 and Z.IM = -MATH_PI_OVER_2
-- Domain:
-- Z in COMPLEX
-- Error conditions:
-- None
-- Range:
-- ABS(COSH(Z)) <= SQRT(SINH(Z.RE)*SINH(Z.RE) +
-- COS(Z.IM)*COS(Z.IM))
-- Notes:
-- None
function COSH (Z : in COMPLEX_POLAR ) return COMPLEX_POLAR;
-- Purpose:
-- Returns principal value of hyperbolic cosine of Z
-- Special values:
-- COSH(Z) = COMPLEX_POLAR'(1.0, 0.0) if Z.MAG = 0.0 and
-- Z.ARG = 0.0
-- COSH(Z) = COMPLEX_POLAR'(1.0, MATH_PI) if Z.MAG = MATH_PI and
-- Z.ARG = MATH_PI_OVER_2
-- COSH(Z) = COMPLEX_POLAR'(0.0, 0.0) if Z.MAG =
-- MATH_PI_OVER_2 and Z.ARG = MATH_PI_OVER_2
-- COSH(Z) = COMPLEX_POLAR'(0.0, 0.0) if Z.MAG =
-- MATH_PI_OVER_2 and Z.ARG = -MATH_PI_OVER_2
-- Domain:
-- Z in COMPLEX_POLAR and Z.ARG /= -MATH_PI
-- Error conditions:
-- Error if Z.ARG = -MATH_PI
-- Range:
-- result.MAG >= 0.0
-- -MATH_PI < result.ARG <= MATH_PI
-- Notes:
-- None
--
-- Arithmetic Operators
--
function "+" ( L: in COMPLEX; R: in COMPLEX ) return COMPLEX;
-- Purpose:
-- Returns arithmetic addition of L and R
-- Special values:
-- None
-- Domain:
-- L in COMPLEX
-- R in COMPLEX
-- Error conditions:
-- None
-- Range:
-- "+"(Z) is mathematically unbounded
-- Notes:
-- None
function "+" ( L: in REAL; R: in COMPLEX ) return COMPLEX;
-- Purpose:
-- Returns arithmetic addition of L and R
-- Special values:
-- None
-- Domain:
-- L in REAL
-- R in COMPLEX
-- Error conditions:
-- None
-- Range:
-- "+"(Z) is mathematically unbounded
-- Notes:
-- None
function "+" ( L: in COMPLEX; R: in REAL ) return COMPLEX;
-- Purpose:
-- Returns arithmetic addition of L and R
-- Special values:
-- None
-- Domain:
-- L in COMPLEX
-- R in REAL
-- Error conditions:
-- None
-- Range:
-- "+"(Z) is mathematically unbounded
-- Notes:
-- None
function "+" ( L: in COMPLEX_POLAR; R: in COMPLEX_POLAR)
return COMPLEX_POLAR;
-- Purpose:
-- Returns arithmetic addition of L and R
-- Special values:
-- None
-- Domain:
-- L in COMPLEX_POLAR and L.ARG /= -MATH_PI
-- R in COMPLEX_POLAR and R.ARG /= -MATH_PI
-- Error conditions:
-- Error if L.ARG = -MATH_PI
-- Error if R.ARG = -MATH_PI
-- Range:
-- result.MAG >= 0.0
-- -MATH_PI < result.ARG <= MATH_PI
-- Notes:
-- None
function "+" ( L: in REAL; R: in COMPLEX_POLAR) return COMPLEX_POLAR;
-- Purpose:
-- Returns arithmetic addition of L and R
-- Special values:
-- None
-- Domain:
-- L in REAL
-- R in COMPLEX_POLAR and R.ARG /= -MATH_PI
-- Error conditions:
-- Error if R.ARG = -MATH_PI
-- Range:
-- result.MAG >= 0.0
-- -MATH_PI < result.ARG <= MATH_PI
-- Notes:
-- None
function "+" ( L: in COMPLEX_POLAR; R: in REAL) return COMPLEX_POLAR;
-- Purpose:
-- Returns arithmetic addition of L and R
-- Special values:
-- None
-- Domain:
-- L in COMPLEX_POLAR and L.ARG /= -MATH_PI
-- R in REAL
-- Error conditions:
-- Error if L.ARG = -MATH_PI
-- Range:
-- result.MAG >= 0.0
-- -MATH_PI < result.ARG <= MATH_PI
-- Notes:
-- None
function "-" ( L: in COMPLEX; R: in COMPLEX ) return COMPLEX;
-- Purpose:
-- Returns arithmetic subtraction of L minus R
-- Special values:
-- None
-- Domain:
-- L in COMPLEX
-- R in COMPLEX
-- Error conditions:
-- None
-- Range:
-- "-"(Z) is mathematically unbounded
-- Notes:
-- None
function "-" ( L: in REAL; R: in COMPLEX ) return COMPLEX;
-- Purpose:
-- Returns arithmetic subtraction of L minus R
-- Special values:
-- None
-- Domain:
-- L in REAL
-- R in COMPLEX
-- Error conditions:
-- None
-- Range:
-- "-"(Z) is mathematically unbounded
-- Notes:
-- None
function "-" ( L: in COMPLEX; R: in REAL ) return COMPLEX;
-- Purpose:
-- Returns arithmetic subtraction of L minus R
-- Special values:
-- None
-- Domain:
-- L in COMPLEX
-- R in REAL
-- Error conditions:
-- None
-- Range:
-- "-"(Z) is mathematically unbounded
-- Notes:
-- None
function "-" ( L: in COMPLEX_POLAR; R: in COMPLEX_POLAR)
return COMPLEX_POLAR;
-- Purpose:
-- Returns arithmetic subtraction of L minus R
-- Special values:
-- None
-- Domain:
-- L in COMPLEX_POLAR and L.ARG /= -MATH_PI
-- R in COMPLEX_POLAR and R.ARG /= -MATH_PI
-- Error conditions:
-- Error if L.ARG = -MATH_PI
-- Error if R.ARG = -MATH_PI
-- Range:
-- result.MAG >= 0.0
-- -MATH_PI < result.ARG <= MATH_PI
-- Notes:
-- None
function "-" ( L: in REAL; R: in COMPLEX_POLAR) return COMPLEX_POLAR;
-- Purpose:
-- Returns arithmetic subtraction of L minus R
-- Special values:
-- None
-- Domain:
-- L in REAL
-- R in COMPLEX_POLAR and R.ARG /= -MATH_PI
-- Error conditions:
-- Error if R.ARG = -MATH_PI
-- Range:
-- result.MAG >= 0.0
-- -MATH_PI < result.ARG <= MATH_PI
-- Notes:
-- None
function "-" ( L: in COMPLEX_POLAR; R: in REAL) return COMPLEX_POLAR;
-- Purpose:
-- Returns arithmetic subtraction of L minus R
-- Special values:
-- None
-- Domain:
-- L in COMPLEX_POLAR and L.ARG /= -MATH_PI
-- R in REAL
-- Error conditions:
-- Error if L.ARG = -MATH_PI
-- Range:
-- result.MAG >= 0.0
-- -MATH_PI < result.ARG <= MATH_PI
-- Notes:
-- None
function "*" ( L: in COMPLEX; R: in COMPLEX ) return COMPLEX;
-- Purpose:
-- Returns arithmetic multiplication of L and R
-- Special values:
-- None
-- Domain:
-- L in COMPLEX
-- R in COMPLEX
-- Error conditions:
-- None
-- Range:
-- "*"(Z) is mathematically unbounded
-- Notes:
-- None
function "*" ( L: in REAL; R: in COMPLEX ) return COMPLEX;
-- Purpose:
-- Returns arithmetic multiplication of L and R
-- Special values:
-- None
-- Domain:
-- L in REAL
-- R in COMPLEX
-- Error conditions:
-- None
-- Range:
-- "*"(Z) is mathematically unbounded
-- Notes:
-- None
function "*" ( L: in COMPLEX; R: in REAL ) return COMPLEX;
-- Purpose:
-- Returns arithmetic multiplication of L and R
-- Special values:
-- None
-- Domain:
-- L in COMPLEX
-- R in REAL
-- Error conditions:
-- None
-- Range:
-- "*"(Z) is mathematically unbounded
-- Notes:
-- None
function "*" ( L: in COMPLEX_POLAR; R: in COMPLEX_POLAR)
return COMPLEX_POLAR;
-- Purpose:
-- Returns arithmetic multiplication of L and R
-- Special values:
-- None
-- Domain:
-- L in COMPLEX_POLAR and L.ARG /= -MATH_PI
-- R in COMPLEX_POLAR and R.ARG /= -MATH_PI
-- Error conditions:
-- Error if L.ARG = -MATH_PI
-- Error if R.ARG = -MATH_PI
-- Range:
-- result.MAG >= 0.0
-- -MATH_PI < result.ARG <= MATH_PI
-- Notes:
-- None
function "*" ( L: in REAL; R: in COMPLEX_POLAR) return COMPLEX_POLAR;
-- Purpose:
-- Returns arithmetic multiplication of L and R
-- Special values:
-- None
-- Domain:
-- L in REAL
-- R in COMPLEX_POLAR and R.ARG /= -MATH_PI
-- Error conditions:
-- Error if R.ARG = -MATH_PI
-- Range:
-- result.MAG >= 0.0
-- -MATH_PI < result.ARG <= MATH_PI
-- Notes:
-- None
function "*" ( L: in COMPLEX_POLAR; R: in REAL) return COMPLEX_POLAR;
-- Purpose:
-- Returns arithmetic multiplication of L and R
-- Special values:
-- None
-- Domain:
-- L in COMPLEX_POLAR and L.ARG /= -MATH_PI
-- R in REAL
-- Error conditions:
-- Error if L.ARG = -MATH_PI
-- Range:
-- result.MAG >= 0.0
-- -MATH_PI < result.ARG <= MATH_PI
-- Notes:
-- None
function "/" ( L: in COMPLEX; R: in COMPLEX ) return COMPLEX;
-- Purpose:
-- Returns arithmetic division of L by R
-- Special values:
-- None
-- Domain:
-- L in COMPLEX
-- R in COMPLEX and R /= MATH_CZERO
-- Error conditions:
-- Error if R = MATH_CZERO
-- Range:
-- "/"(Z) is mathematically unbounded
-- Notes:
-- None
function "/" ( L: in REAL; R: in COMPLEX ) return COMPLEX;
-- Purpose:
-- Returns arithmetic division of L by R
-- Special values:
-- None
-- Domain:
-- L in REAL
-- R in COMPLEX and R /= MATH_CZERO
-- Error conditions:
-- Error if R = MATH_CZERO
-- Range:
-- "/"(Z) is mathematically unbounded
-- Notes:
-- None
function "/" ( L: in COMPLEX; R: in REAL ) return COMPLEX;
-- Purpose:
-- Returns arithmetic division of L by R
-- Special values:
-- None
-- Domain:
-- L in COMPLEX
-- R in REAL and R /= 0.0
-- Error conditions:
-- Error if R = 0.0
-- Range:
-- "/"(Z) is mathematically unbounded
-- Notes:
-- None
function "/" ( L: in COMPLEX_POLAR; R: in COMPLEX_POLAR)
return COMPLEX_POLAR;
-- Purpose:
-- Returns arithmetic division of L by R
-- Special values:
-- None
-- Domain:
-- L in COMPLEX_POLAR and L.ARG /= -MATH_PI
-- R in COMPLEX_POLAR and R.ARG /= -MATH_PI
-- R.MAG > 0.0
-- Error conditions:
-- Error if R.MAG <= 0.0
-- Error if L.ARG = -MATH_PI
-- Error if R.ARG = -MATH_PI
-- Range:
-- result.MAG >= 0.0
-- -MATH_PI < result.ARG <= MATH_PI
-- Notes:
-- None
function "/" ( L: in REAL; R: in COMPLEX_POLAR) return COMPLEX_POLAR;
-- Purpose:
-- Returns arithmetic division of L by R
-- Special values:
-- None
-- Domain:
-- L in REAL
-- R in COMPLEX_POLAR and R.ARG /= -MATH_PI
-- R.MAG > 0.0
-- Error conditions:
-- Error if R.MAG <= 0.0
-- Error if R.ARG = -MATH_PI
-- Range:
-- result.MAG >= 0.0
-- -MATH_PI < result.ARG <= MATH_PI
-- Notes:
-- None
function "/" ( L: in COMPLEX_POLAR; R: in REAL) return COMPLEX_POLAR;
-- Purpose:
-- Returns arithmetic division of L by R
-- Special values:
-- None
-- Domain:
-- L in COMPLEX_POLAR and L.ARG /= -MATH_PI
-- R /= 0.0
-- Error conditions:
-- Error if L.ARG = -MATH_PI
-- Error if R = 0.0
-- Range:
-- result.MAG >= 0.0
-- -MATH_PI < result.ARG <= MATH_PI
-- Notes:
-- None
end MATH_COMPLEX;
| gpl-2.0 | e609158ccac19ef9fffcf772a83f4dc4 | 0.429355 | 4.204738 | false | false | false | false |
pmh92/Proyecto-OFDM | ipcore_dir/DPRAM_10.vhd | 1 | 5,782 | --------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used solely --
-- for design, simulation, implementation and creation of design files --
-- limited to Xilinx devices or technologies. Use with non-Xilinx --
-- devices or technologies is expressly prohibited and immediately --
-- terminates your license. --
-- --
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY --
-- FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY --
-- PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE --
-- IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS --
-- MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY --
-- CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY --
-- RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY --
-- DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A --
-- PARTICULAR PURPOSE. --
-- --
-- Xilinx products are not intended for use in life support appliances, --
-- devices, or systems. Use in such applications are expressly --
-- prohibited. --
-- --
-- (c) Copyright 1995-2015 Xilinx, Inc. --
-- All rights reserved. --
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- You must compile the wrapper file DPRAM_10.vhd when simulating
-- the core, DPRAM_10. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Help".
-- The synthesis directives "translate_off/translate_on" specified
-- below are supported by Xilinx, Mentor Graphics and Synplicity
-- synthesis tools. Ensure they are correct for your synthesis tool(s).
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- synthesis translate_off
LIBRARY XilinxCoreLib;
-- synthesis translate_on
ENTITY DPRAM_10 IS
PORT (
clka : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(10 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(19 DOWNTO 0);
clkb : IN STD_LOGIC;
addrb : IN STD_LOGIC_VECTOR(10 DOWNTO 0);
doutb : OUT STD_LOGIC_VECTOR(19 DOWNTO 0)
);
END DPRAM_10;
ARCHITECTURE DPRAM_10_a OF DPRAM_10 IS
-- synthesis translate_off
COMPONENT wrapped_DPRAM_10
PORT (
clka : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(10 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(19 DOWNTO 0);
clkb : IN STD_LOGIC;
addrb : IN STD_LOGIC_VECTOR(10 DOWNTO 0);
doutb : OUT STD_LOGIC_VECTOR(19 DOWNTO 0)
);
END COMPONENT;
-- Configuration specification
FOR ALL : wrapped_DPRAM_10 USE ENTITY XilinxCoreLib.blk_mem_gen_v7_3(behavioral)
GENERIC MAP (
c_addra_width => 11,
c_addrb_width => 11,
c_algorithm => 1,
c_axi_id_width => 4,
c_axi_slave_type => 0,
c_axi_type => 1,
c_byte_size => 9,
c_common_clk => 0,
c_default_data => "0",
c_disable_warn_bhv_coll => 0,
c_disable_warn_bhv_range => 0,
c_enable_32bit_address => 0,
c_family => "spartan6",
c_has_axi_id => 0,
c_has_ena => 0,
c_has_enb => 0,
c_has_injecterr => 0,
c_has_mem_output_regs_a => 0,
c_has_mem_output_regs_b => 0,
c_has_mux_output_regs_a => 0,
c_has_mux_output_regs_b => 0,
c_has_regcea => 0,
c_has_regceb => 0,
c_has_rsta => 0,
c_has_rstb => 0,
c_has_softecc_input_regs_a => 0,
c_has_softecc_output_regs_b => 0,
c_init_file => "BlankString",
c_init_file_name => "DPRAM_10.mif",
c_inita_val => "0",
c_initb_val => "0",
c_interface_type => 0,
c_load_init_file => 1,
c_mem_type => 1,
c_mux_pipeline_stages => 0,
c_prim_type => 1,
c_read_depth_a => 2048,
c_read_depth_b => 2048,
c_read_width_a => 20,
c_read_width_b => 20,
c_rst_priority_a => "CE",
c_rst_priority_b => "CE",
c_rst_type => "SYNC",
c_rstram_a => 0,
c_rstram_b => 0,
c_sim_collision_check => "ALL",
c_use_bram_block => 0,
c_use_byte_wea => 0,
c_use_byte_web => 0,
c_use_default_data => 0,
c_use_ecc => 0,
c_use_softecc => 0,
c_wea_width => 1,
c_web_width => 1,
c_write_depth_a => 2048,
c_write_depth_b => 2048,
c_write_mode_a => "WRITE_FIRST",
c_write_mode_b => "WRITE_FIRST",
c_write_width_a => 20,
c_write_width_b => 20,
c_xdevicefamily => "spartan6"
);
-- synthesis translate_on
BEGIN
-- synthesis translate_off
U0 : wrapped_DPRAM_10
PORT MAP (
clka => clka,
wea => wea,
addra => addra,
dina => dina,
clkb => clkb,
addrb => addrb,
doutb => doutb
);
-- synthesis translate_on
END DPRAM_10_a;
| gpl-2.0 | e998e832841be03a43f2bf8b029fec62 | 0.533207 | 3.922659 | false | false | false | false |
ambrosef/HLx_Examples | Acceleration/tcp_ip/rtl/arpServerWrapper.vhd | 2 | 8,949 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity arpServerWrapper is
generic ( keyLength : integer := 32;
valueLength : integer := 48);
Port ( aclk : in STD_LOGIC;
aresetn : in STD_LOGIC;
myMacAddress : in std_logic_vector(47 downto 0);
myIpAddress : in std_logic_vector(31 downto 0);
axi_arp_to_arp_slice_tvalid : out std_logic;
axi_arp_to_arp_slice_tready : in std_logic;
axi_arp_to_arp_slice_tdata : out std_logic_vector(63 downto 0);
axi_arp_to_arp_slice_tkeep : out std_logic_vector(7 downto 0);
axi_arp_to_arp_slice_tlast : out std_logic;
axis_arp_lookup_reply_TVALID : out std_logic;
axis_arp_lookup_reply_TREADY : in std_logic;
axis_arp_lookup_reply_TDATA : out std_logic_vector(55 downto 0);
axi_arp_slice_to_arp_tvalid : in std_logic;
axi_arp_slice_to_arp_tready : out std_logic;
axi_arp_slice_to_arp_tdata : in std_logic_vector(63 downto 0);
axi_arp_slice_to_arp_tkeep : in std_logic_vector(7 downto 0);
axi_arp_slice_to_arp_tlast : in std_logic;
axis_arp_lookup_request_TVALID : in std_logic;
axis_arp_lookup_request_TREADY : out std_logic;
axis_arp_lookup_request_TDATA : in std_logic_vector(keyLength - 1 downto 0));
end arpServerWrapper;
architecture Structural of arpServerWrapper is
COMPONENT arp_server_ip
PORT(regIpAddress_V : IN std_logic_vector(31 downto 0);
myMacAddress_V : in std_logic_vector(47 downto 0);
aresetn : IN std_logic;
aclk : IN std_logic;
macUpdate_resp_TDATA : IN std_logic_vector(55 downto 0);
macUpdate_resp_TREADY : OUT std_logic;
macUpdate_resp_TVALID : IN std_logic;
macUpdate_req_TDATA : OUT std_logic_vector(87 downto 0);
macUpdate_req_TREADY : IN std_logic;
macUpdate_req_TVALID : OUT std_logic;
macLookup_resp_TDATA : IN std_logic_vector(55 downto 0);
macLookup_resp_TREADY : OUT std_logic;
macLookup_resp_TVALID : IN std_logic;
macLookup_req_TDATA : OUT std_logic_vector(39 downto 0);
macLookup_req_TREADY : IN std_logic;
macLookup_req_TVALID : OUT std_logic;
macIpEncode_rsp_TDATA : OUT std_logic_vector(55 downto 0);
macIpEncode_rsp_TREADY : IN std_logic;
macIpEncode_rsp_TVALID : OUT std_logic;
arpDataOut_TLAST : OUT std_logic;
arpDataOut_TKEEP : OUT std_logic_vector(7 downto 0);
arpDataOut_TDATA : OUT std_logic_vector(63 downto 0);
arpDataOut_TREADY : IN std_logic;
arpDataOut_TVALID : OUT std_logic;
macIpEncode_req_TDATA : IN std_logic_vector(31 downto 0);
macIpEncode_req_TREADY : OUT std_logic;
macIpEncode_req_TVALID : IN std_logic;
arpDataIn_TLAST : IN std_logic;
arpDataIn_TKEEP : IN std_logic_vector(7 downto 0);
arpDataIn_TDATA : IN std_logic_vector(63 downto 0);
arpDataIn_TREADY : OUT std_logic;
arpDataIn_TVALID : IN std_logic);
END COMPONENT;
signal invertedReset : std_logic;
signal lup_req_TVALID : std_logic;
signal lup_req_TREADY : std_logic;
signal lup_req_TDATA : std_logic_vector(39 downto 0);
signal lup_req_TDATA_im: std_logic_vector(keyLength downto 0);
signal lup_rsp_TVALID : std_logic;
signal lup_rsp_TREADY : std_logic;
signal lup_rsp_TDATA : std_logic_vector(55 downto 0);
signal lup_rsp_TDATA_im: std_logic_vector(valueLength downto 0);
signal upd_req_TVALID : std_logic;
signal upd_req_TREADY : std_logic;
signal upd_req_TDATA : std_logic_vector(87 downto 0);
signal upd_req_TDATA_im: std_logic_vector((keyLength + valueLength) + 1 downto 0);
signal upd_rsp_TVALID : std_logic;
signal upd_rsp_TREADY : std_logic;
signal upd_rsp_TDATA : std_logic_vector(55 downto 0);
signal upd_rsp_TDATA_im: std_logic_vector(valueLength + 1 downto 0);
begin
lup_req_TDATA_im <= lup_req_TDATA(32 downto 0);
lup_rsp_TDATA <= "0000000" & lup_rsp_TDATA_im;
upd_req_TDATA_im <= upd_req_TDATA((keyLength + valueLength) + 1 downto 0);
upd_rsp_TDATA <= "000000" & upd_rsp_TDATA_im;
invertedReset <= NOT aresetn;
-- SmartCam Wrapper
SmartCamCtl_inst: entity work.SmartCamCtlArp--(behavior)
port map(clk => aclk,
rst => invertedReset,
led0 => open,
led1 => open,
cam_ready => open,
lup_req_valid => lup_req_TVALID,
lup_req_ready => lup_req_TREADY,
lup_req_din => lup_req_TDATA_im,
lup_rsp_valid => lup_rsp_TVALID,
lup_rsp_ready => lup_rsp_TREADY,
lup_rsp_dout => lup_rsp_TDATA_im,
upd_req_valid => upd_req_TVALID,
upd_req_ready => upd_req_TREADY,
upd_req_din => upd_req_TDATA_im,
upd_rsp_valid => upd_rsp_TVALID,
upd_rsp_ready => upd_rsp_TREADY,
upd_rsp_dout => upd_rsp_TDATA_im,
debug => open);
-- ARP Server
arp_server_inst: arp_server_ip
port map (regIpAddress_V => myIpAddress,
myMacAddress_V => myMacAddress,
arpDataIn_TVALID => axi_arp_slice_to_arp_tvalid,
arpDataIn_TREADY => axi_arp_slice_to_arp_tready,
arpDataIn_TDATA => axi_arp_slice_to_arp_tdata,
arpDataIn_TKEEP => axi_arp_slice_to_arp_tkeep,
arpDataIn_TLAST => axi_arp_slice_to_arp_tlast,
macIpEncode_req_TVALID => axis_arp_lookup_request_TVALID,
macIpEncode_req_TREADY => axis_arp_lookup_request_TREADY,
macIpEncode_req_TDATA => axis_arp_lookup_request_TDATA,
arpDataOut_TVALID => axi_arp_to_arp_slice_tvalid,
arpDataOut_TREADY => axi_arp_to_arp_slice_tready,
arpDataOut_TDATA => axi_arp_to_arp_slice_tdata,
arpDataOut_TKEEP => axi_arp_to_arp_slice_tkeep,
arpDataOut_TLAST => axi_arp_to_arp_slice_tlast,
macIpEncode_rsp_TVALID => axis_arp_lookup_reply_TVALID,
macIpEncode_rsp_TREADY => axis_arp_lookup_reply_TREADY,
macIpEncode_rsp_TDATA => axis_arp_lookup_reply_TDATA,
macLookup_req_TVALID => lup_req_TVALID,
macLookup_req_TREADY => lup_req_TREADY,
macLookup_req_TDATA => lup_req_TDATA,
macLookup_resp_TVALID => lup_rsp_TVALID,
macLookup_resp_TREADY => lup_rsp_TREADY,
macLookup_resp_TDATA => lup_rsp_TDATA,
macUpdate_req_TVALID => upd_req_TVALID,
macUpdate_req_TREADY => upd_req_TREADY,
macUpdate_req_TDATA => upd_req_TDATA,
macUpdate_resp_TVALID => upd_rsp_TVALID,
macUpdate_resp_TREADY => upd_rsp_TREADY,
macUpdate_resp_TDATA => upd_rsp_TDATA,
aclk => aclk,
aresetn => aresetn);
end Structural; | bsd-3-clause | 57700f2ac7a1c87dc4797be52ca14876 | 0.476366 | 3.916411 | false | false | false | false |
rafa-jfet/OFM | ARCHIVOS VHDL/guardaifft.vhd | 1 | 2,526 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 12:49:53 06/29/2015
-- Design Name:
-- Module Name: guardaifft - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity guardaifft is
Port ( reset : in STD_LOGIC;
clk : in STD_LOGIC;
dv : in STD_LOGIC;
cpv : in STD_LOGIC;
edone : in STD_LOGIC;
xk_index : in STD_LOGIC_VECTOR(6 downto 0);
we : out STD_LOGIC;
xk_re : in STD_LOGIC_VECTOR (15 downto 0);
xk_im : in STD_LOGIC_VECTOR (15 downto 0);
EnableTxserie : out STD_LOGIC;
dato_out : out STD_LOGIC_VECTOR (31 downto 0);
addresout : out STD_LOGIC_VECTOR (8 downto 0));
end guardaifft;
architecture Behavioral of guardaifft is
type estado is ( reposo,
inicio,
fin);
signal estado_actual, estado_nuevo : estado;
signal dir_actual, dir_nueva: STD_LOGIC_VECTOR(8 downto 0);
begin
sinc : process(reset, clk)
begin
if(reset='1') then
estado_actual <= reposo;
dir_actual <= (others => '0');
elsif (clk='1' and clk'event) then
dir_actual <= dir_nueva;
estado_actual <= estado_nuevo;
end if;
end process;
addresout <= dir_actual;
dato_out <= xk_re & xk_im;
comb : process (estado_actual, dir_actual, dv, cpv, xk_index, edone)
begin
we <= dv;
dir_nueva <= dir_actual;
EnableTxserie <= '0';
case estado_actual is
when reposo =>
if ( dv='1') then
estado_nuevo <= inicio;
dir_nueva <=dir_actual+1;
else
estado_nuevo <= reposo;
end if;
when inicio =>
if (dv='1') then
dir_nueva <= dir_actual+1;
estado_nuevo <=inicio;
else
estado_nuevo<= fin;
end if;
when fin =>
EnableTXserie<='1';
estado_nuevo <=reposo;
end case;
end process;
end Behavioral;
| gpl-3.0 | e07699da95258e4cdc0bcbf52022bc5b | 0.5673 | 3.377005 | false | false | false | false |
emogenet/ghdl | testsuite/gna/perf02/test_data.vhd | 3 | 1,540 | library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity test_data is
port (
clk : in std_logic;
ra0_data : out std_logic_vector(31 downto 0);
wa0_addr : in std_logic_vector(6 downto 0);
wa0_en : in std_logic;
ra0_addr : in std_logic_vector(6 downto 0);
wa0_data : in std_logic_vector(31 downto 0);
ra1_data : out std_logic_vector(31 downto 0);
ra1_addr : in std_logic_vector(6 downto 0)
);
end test_data;
architecture augh of test_data is
-- Embedded RAM
type ram_type is array (0 to 127) of std_logic_vector(31 downto 0);
signal ram : ram_type := (others => (others => '0'));
-- Little utility functions to make VHDL syntactically correct
-- with the syntax to_integer(unsigned(vector)) when 'vector' is a std_logic.
-- This happens when accessing arrays with <= 2 cells, for example.
function to_integer(B: std_logic) return integer is
variable V: std_logic_vector(0 to 0);
begin
V(0) := B;
return to_integer(unsigned(V));
end;
function to_integer(V: std_logic_vector) return integer is
begin
return to_integer(unsigned(V));
end;
begin
-- Sequential process
-- It handles the Writes
process (clk)
begin
if rising_edge(clk) then
-- Write to the RAM
-- Note: there should be only one port.
if wa0_en = '1' then
ram( to_integer(wa0_addr) ) <= wa0_data;
end if;
end if;
end process;
-- The Read side (the outputs)
ra0_data <= ram( to_integer(ra0_addr) );
ra1_data <= ram( to_integer(ra1_addr) );
end architecture;
| gpl-2.0 | a4836c5429d0c116c71469e27185ee72 | 0.670779 | 2.84658 | false | false | false | false |
emogenet/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc36.vhd | 4 | 2,773 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc36.vhd,v 1.2 2001-10-26 16:29:53 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c04s03b01x01p02n01i00036ent IS
END c04s03b01x01p02n01i00036ent;
ARCHITECTURE c04s03b01x01p02n01i00036arch OF c04s03b01x01p02n01i00036ent IS
constant a : positive := 1; -- No_failure_here
constant b : natural := 1; -- No_failure_here
constant a1 : positive := a + 1; -- No_failure_here
constant a2 : positive := a + a; -- No_failure_here
constant a3 : positive := a * (a/a + 1); -- No_failure_here
constant b1 : natural := b + 1; -- No_failure_here
constant b2 : natural := b + b; -- No_failure_here
constant b3 : natural := b * (b/b + 1); -- No_failure_here
constant b4 : natural := b - b; -- No_failure_here
BEGIN
TESTING: PROCESS
BEGIN
assert NOT( a = 1 and
b = 1 and
a1 = 2 and
a2 = 2 and
a3 = 2 and
b1 = 2 and
b2 = 2 and
b3 = 2 and
b4 = 0 )
report "***PASSED TEST: c04s03b01x01p02n01i00036"
severity NOTE;
assert ( a = 1 and
b = 1 and
a1 = 2 and
a2 = 2 and
a3 = 2 and
b1 = 2 and
b2 = 2 and
b3 = 2 and
b4 = 0 )
report "***FAILED TEST: c04s03b01x01p02n01i00036 - Constant declaration syntactic format test failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c04s03b01x01p02n01i00036arch;
| gpl-2.0 | 2ab32da745e205f0a34dd87f4f433e16 | 0.545979 | 3.6875 | false | true | false | false |
rafa-jfet/OFM | ARCHIVOS VHDL/top_controlycoreifft.vhd | 1 | 4,289 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 25.06.2015 15:54:30
-- Design Name:
-- Module Name: IFFT_completa - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity IFFT_completa is
Port (
clk: in STD_LOGIC;
data_in : in STD_LOGIC_VECTOR (15 downto 0);
address_read : out STD_LOGIC_VECTOR(6 downto 0);
IfftEnable: in STD_LOGIC;
reset: in STD_LOGIC;
address_write :out STD_LOGIC_VECTOR(8 downto 0);
EnableTxserie :out STD_LOGIC;
datos_salida :out STD_LOGIC_VECTOR(31 downto 0);
we :out STD_LOGIC );
end IFFT_completa;
architecture Behavioral of IFFT_completa is
signal s_start, s_cp_len_we, s_unload,s_fwd_inv, s_fwd_inv_we, s_rfd, s_cpv,s_dv,s_edone: STD_LOGIC;
signal s_cp_len,s_xk_index : STD_LOGIC_VECTOR (6 DOWNTO 0);
signal s_xk_re, s_xk_im : STD_LOGIC_VECTOR (15 downto 0);
COMPONENT ifft is
PORT (
clk : IN STD_LOGIC;
sclr : IN STD_LOGIC;
start : IN STD_LOGIC;
unload : IN STD_LOGIC;
cp_len : IN STD_LOGIC_VECTOR(6 DOWNTO 0);
cp_len_we : IN STD_LOGIC;
xn_re : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
xn_im : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
fwd_inv : IN STD_LOGIC;
fwd_inv_we : IN STD_LOGIC;
rfd : OUT STD_LOGIC;
xn_index : OUT STD_LOGIC_VECTOR(6 DOWNTO 0);
busy : OUT STD_LOGIC;
edone : OUT STD_LOGIC;
done : OUT STD_LOGIC;
dv : OUT STD_LOGIC;
xk_index : OUT STD_LOGIC_VECTOR(6 DOWNTO 0);
cpv : OUT STD_LOGIC;
xk_re : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
xk_im : OUT STD_LOGIC_VECTOR(15 DOWNTO 0)
);
END COMPONENT;
COMPONENT ifftcontrol is
GENERIC (
CARRIERS : INTEGER :=128 );
PORT (
reset : in STD_LOGIC;
clk : in STD_LOGIC;
IfftEnable: in STD_LOGIC;
start : out STD_LOGIC;
cp_len : out STD_LOGIC_VECTOR(6 DOWNTO 0);
cp_len_we: out STD_LOGIC;
fwd_inv : out STD_LOGIC;
fwd_inv_we : out STD_LOGIC;
unload : out STD_LOGIC;
rfd : in STD_LOGIC
);
END COMPONENT;
COMPONENT guardaifft is
PORT (
reset : IN std_logic;
clk : IN std_logic;
dv : IN std_logic;
edone: in STD_LOGIC;
cpv : IN std_logic;
xk_index : IN std_logic_vector(6 downto 0);
xk_re : IN std_logic_vector(15 downto 0);
xk_im : IN std_logic_vector(15 downto 0);
we : OUT std_logic;
EnableTxserie : OUT std_logic;
dato_out : OUT std_logic_vector(31 downto 0);
addresout : OUT std_logic_vector(8 downto 0)
);
END COMPONENT;
begin
core1 : ifft
PORT MAP (
clk => clk,
sclr => reset,
start => s_start,
unload => s_unload,
cp_len => s_cp_len,
cp_len_we => s_cp_len_we,
xn_re => data_in (15 downto 8),
xn_im => data_in (7 downto 0),
fwd_inv => s_fwd_inv,
fwd_inv_we => s_fwd_inv_we,
rfd => s_rfd ,
xn_index => address_read,
busy => open,
edone => open,
done => s_edone,
dv => s_dv,
xk_index => s_xk_index ,
cpv => s_cpv,
xk_re => s_xk_re,
xk_im => s_xk_im
);
control: IfftControl
PORT MAP (
reset => reset,
clk => clk,
IfftEnable => IfftEnable,
start =>s_start,
cp_len => s_cp_len ,
cp_len_we => s_cp_len_we,
fwd_inv => s_fwd_inv,
fwd_inv_we=> s_fwd_inv_we ,
unload => s_unload,
rfd =>s_rfd
);
Inst_guardaifft : guardaifft
PORT MAP(
reset => reset ,
clk => clk ,
dv => s_dv,
edone => s_edone,
cpv =>s_cpv,
xk_index => s_xk_index,
we => we ,
xk_re => s_xk_re,
xk_im => s_xk_im,
EnableTxserie => EnableTxserie,
dato_out => datos_salida,
addresout => address_write
);
end Behavioral;
| gpl-3.0 | eb92a4cf70b186aff4c1977c2844a025 | 0.573793 | 2.919673 | false | false | false | false |
emogenet/ghdl | testsuite/vests/vhdl-93/ashenden/compliant/ch_03_fg_03_05.vhd | 4 | 1,567 |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_03_fg_03_05.vhd,v 1.3 2001-10-26 16:29:33 paw Exp $
-- $Revision: 1.3 $
--
-- ---------------------------------------------------------------------
entity cos is
port ( theta : in real; result : out real );
end entity cos;
architecture series of cos is
begin
summation : process (theta) is
variable sum, term : real;
variable n : natural;
begin
sum := 1.0;
term := 1.0;
n := 0;
while abs term > abs (sum / 1.0E6) loop
n := n + 2;
term := (-term) * theta**2 / real(((n-1) * n));
sum := sum + term;
end loop;
result <= sum;
end process summation;
end architecture series;
| gpl-2.0 | 7859f51c22ab8bfc1cc9f19a6593b1f4 | 0.582004 | 4.07013 | false | false | false | false |
pmh92/Proyecto-OFDM | ipcore_dir/DPRAM_12.vhd | 1 | 5,780 | --------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used solely --
-- for design, simulation, implementation and creation of design files --
-- limited to Xilinx devices or technologies. Use with non-Xilinx --
-- devices or technologies is expressly prohibited and immediately --
-- terminates your license. --
-- --
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY --
-- FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY --
-- PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE --
-- IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS --
-- MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY --
-- CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY --
-- RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY --
-- DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A --
-- PARTICULAR PURPOSE. --
-- --
-- Xilinx products are not intended for use in life support appliances, --
-- devices, or systems. Use in such applications are expressly --
-- prohibited. --
-- --
-- (c) Copyright 1995-2015 Xilinx, Inc. --
-- All rights reserved. --
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- You must compile the wrapper file DPRAM_12.vhd when simulating
-- the core, DPRAM_12. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Help".
-- The synthesis directives "translate_off/translate_on" specified
-- below are supported by Xilinx, Mentor Graphics and Synplicity
-- synthesis tools. Ensure they are correct for your synthesis tool(s).
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- synthesis translate_off
LIBRARY XilinxCoreLib;
-- synthesis translate_on
ENTITY DPRAM_12 IS
PORT (
clka : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(10 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
clkb : IN STD_LOGIC;
addrb : IN STD_LOGIC_VECTOR(10 DOWNTO 0);
doutb : OUT STD_LOGIC_VECTOR(23 DOWNTO 0)
);
END DPRAM_12;
ARCHITECTURE DPRAM_12_a OF DPRAM_12 IS
-- synthesis translate_off
COMPONENT wrapped_DPRAM_12
PORT (
clka : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(10 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
clkb : IN STD_LOGIC;
addrb : IN STD_LOGIC_VECTOR(10 DOWNTO 0);
doutb : OUT STD_LOGIC_VECTOR(23 DOWNTO 0)
);
END COMPONENT;
-- Configuration specification
FOR ALL : wrapped_DPRAM_12 USE ENTITY XilinxCoreLib.blk_mem_gen_v7_3(behavioral)
GENERIC MAP (
c_addra_width => 11,
c_addrb_width => 11,
c_algorithm => 1,
c_axi_id_width => 4,
c_axi_slave_type => 0,
c_axi_type => 1,
c_byte_size => 9,
c_common_clk => 1,
c_default_data => "0",
c_disable_warn_bhv_coll => 0,
c_disable_warn_bhv_range => 0,
c_enable_32bit_address => 0,
c_family => "spartan6",
c_has_axi_id => 0,
c_has_ena => 0,
c_has_enb => 0,
c_has_injecterr => 0,
c_has_mem_output_regs_a => 0,
c_has_mem_output_regs_b => 0,
c_has_mux_output_regs_a => 0,
c_has_mux_output_regs_b => 0,
c_has_regcea => 0,
c_has_regceb => 0,
c_has_rsta => 0,
c_has_rstb => 0,
c_has_softecc_input_regs_a => 0,
c_has_softecc_output_regs_b => 0,
c_init_file => "BlankString",
c_init_file_name => "DPRAM_12.mif",
c_inita_val => "0",
c_initb_val => "0",
c_interface_type => 0,
c_load_init_file => 1,
c_mem_type => 1,
c_mux_pipeline_stages => 0,
c_prim_type => 1,
c_read_depth_a => 2048,
c_read_depth_b => 2048,
c_read_width_a => 24,
c_read_width_b => 24,
c_rst_priority_a => "CE",
c_rst_priority_b => "CE",
c_rst_type => "SYNC",
c_rstram_a => 0,
c_rstram_b => 0,
c_sim_collision_check => "ALL",
c_use_bram_block => 0,
c_use_byte_wea => 0,
c_use_byte_web => 0,
c_use_default_data => 0,
c_use_ecc => 0,
c_use_softecc => 0,
c_wea_width => 1,
c_web_width => 1,
c_write_depth_a => 2048,
c_write_depth_b => 2048,
c_write_mode_a => "READ_FIRST",
c_write_mode_b => "READ_FIRST",
c_write_width_a => 24,
c_write_width_b => 24,
c_xdevicefamily => "spartan6"
);
-- synthesis translate_on
BEGIN
-- synthesis translate_off
U0 : wrapped_DPRAM_12
PORT MAP (
clka => clka,
wea => wea,
addra => addra,
dina => dina,
clkb => clkb,
addrb => addrb,
doutb => doutb
);
-- synthesis translate_on
END DPRAM_12_a;
| gpl-2.0 | 7d6cf9a740a81bcc71db29a64c020be9 | 0.533045 | 3.921303 | false | false | false | false |
ambrosef/HLx_Examples | Acceleration/memcached/regressionSims/sources/prototypeWrapper.vhd | 1 | 15,775 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity prototypeWrapper is
Generic (DRAM_WIDTH : integer := 512;
FLASH_WIDTH : integer := 64;
DRAM_CMD_WIDTH : integer := 40;
FLASH_CMD_WIDTH : integer := 48);
Port ( clk : in STD_LOGIC;
rst : in STD_LOGIC);
end prototypeWrapper;
architecture Structural of prototypeWrapper is
signal input_to_mcd_tvalid : std_logic;
signal input_to_mcd_tready : std_logic;
signal input_to_mcd_tdata : std_logic_vector(63 downto 0);
signal input_to_mcd_tuser : std_logic_vector(111 downto 0);
signal input_to_mcd_tkeep : std_logic_vector(7 downto 0);
signal input_to_mcd_tlast : std_logic;
signal mcd_to_output_tvalid : std_logic;
signal mcd_to_output_tready : std_logic;
signal mcd_to_output_tdata : std_logic_vector(63 downto 0);
signal mcd_to_output_tuser : std_logic_vector(111 downto 0);
signal mcd_to_output_tkeep : std_logic_vector(7 downto 0);
signal mcd_to_output_tlast : std_logic;
-- DRAM model connections
signal ht_dramRdData_data : std_logic_vector(DRAM_WIDTH-1 downto 0);
signal ht_dramRdData_valid : std_logic;
signal ht_dramRdData_ready : std_logic;
-- ht_cmd_dramRdData: Push Output, 16b
signal ht_cmd_dramRdData_data : std_logic_vector(DRAM_CMD_WIDTH-1 downto 0);
signal ht_cmd_dramRdData_valid : std_logic;
signal ht_cmd_dramRdData_ready : std_logic;
-- ht_dramWrData: Push Output, 512b
signal ht_dramWrData_data : std_logic_vector(DRAM_WIDTH-1 downto 0);
signal ht_dramWrData_valid : std_logic;
signal ht_dramWrData_ready : std_logic;
-- ht_cmd_dramWrData: Push Output, 16b
signal ht_cmd_dramWrData_data : std_logic_vector(DRAM_CMD_WIDTH-1 downto 0);
signal ht_cmd_dramWrData_valid : std_logic;
signal ht_cmd_dramWrData_ready : std_logic;
-- Update DRAM Connection
-- upd_dramRdData: Pull Input, 512b
signal upd_dramRdData_data : std_logic_vector(DRAM_WIDTH-1 downto 0);
signal upd_dramRdData_valid : std_logic;
signal upd_dramRdData_ready : std_logic;
-- upd_cmd_dramRdData: Push Output, 16b
signal upd_cmd_dramRdData_data : std_logic_vector(DRAM_CMD_WIDTH-1 downto 0);
signal upd_cmd_dramRdData_valid : std_logic;
signal upd_cmd_dramRdData_ready : std_logic;
-- upd_dramWrData: Push Output, 512b
signal upd_dramWrData_data : std_logic_vector(DRAM_WIDTH-1 downto 0);
signal upd_dramWrData_valid : std_logic;
signal upd_dramWrData_ready : std_logic;
-- upd_cmd_dramWrData: Push Output, 16b
signal upd_cmd_dramWrData_data : std_logic_vector(DRAM_CMD_WIDTH-1 downto 0);
signal upd_cmd_dramWrData_valid : std_logic;
signal upd_cmd_dramWrData_ready : std_logic;
-- Update Flash Connection
-- upd_flashRdData: Pull Input, 64b
signal upd_flashRdData_data : std_logic_vector(FLASH_WIDTH-1 downto 0);
signal upd_flashRdData_valid : std_logic;
signal upd_flashRdData_ready : std_logic;
-- upd_cmd_flashRdData: Push Output, 48b
signal upd_cmd_flashRdData_data : std_logic_vector(FLASH_CMD_WIDTH-1 downto 0);
signal upd_cmd_flashRdData_valid : std_logic;
signal upd_cmd_flashRdData_ready : std_logic;
-- upd_flashWrData: Push Output, 64b
signal upd_flashWrData_data : std_logic_vector(FLASH_WIDTH-1 downto 0);
signal upd_flashWrData_valid : std_logic;
signal upd_flashWrData_ready : std_logic;
-- upd_cmd_flashWrData: Push Output, 48b
signal upd_cmd_flashWrData_data : std_logic_vector(FLASH_CMD_WIDTH-1 downto 0);
signal upd_cmd_flashWrData_valid : std_logic;
signal upd_cmd_flashWrData_ready : std_logic;
--signal udp_out_ready_inv : std_logic;
signal aresetn : std_logic;
--------------------------------------------------------------------------------------
signal statsIn2monitor_data : std_logic_vector(63 downto 0);
signal statsIn2monitor_ready : std_logic;
signal statsIn2monitor_valid : std_logic;
signal statsOut2monitor_data : std_logic_vector(63 downto 0);
signal statsOut2monitor_ready : std_logic;
signal statsOut2monitor_valid : std_logic;
--------------------------------------------------------------------------------------
signal statsCollector2monitor_data : std_logic_vector(183 downto 0);
signal statsCollector2monitor_valid : std_logic;
signal statsCollector2monitor_ready : std_logic;
signal driver2statsCollector_data : std_logic_vector(173 downto 0);
signal driver2statsCollector_data_im : std_logic_vector(183 downto 0);
signal driver2statsCollector_valid : std_logic;
signal driver2statsCollector_ready : std_logic;
------------------Memory Allocation Signals-------------------------------------------
signal memcached2memAllocation_data : std_logic_vector(31 downto 0); -- Address reclamation
signal memcached2memAllocation_valid : std_logic;
signal memcached2memAllocation_ready : std_logic;
signal memAllocation2memcached_dram_data : std_logic_vector(31 downto 0); -- Address assignment for DRAM
signal memAllocation2memcached_dram_valid : std_logic;
signal memAllocation2memcached_dram_ready : std_logic;
signal memAllocation2memcached_flash_data : std_logic_vector(31 downto 0); -- Address assignment for SSD
signal memAllocation2memcached_flash_valid : std_logic;
signal memAllocation2memcached_flash_ready : std_logic;
signal flushReq : std_logic;
signal flushAck : std_logic;
signal flushDone : std_logic;
begin
aresetn <= NOT rst;
myReader: entity work.kvs_tbDriverHDLNode(rtl)
port map(clk => clk,
rst => rst,
udp_out_ready => input_to_mcd_tready,
udp_out_valid => input_to_mcd_tvalid,
udp_out_keep => input_to_mcd_tkeep,
udp_out_last => input_to_mcd_tlast,
udp_out_user => input_to_mcd_tuser,
udp_out_data => input_to_mcd_tdata);
myMonitor: entity work.kvs_tbMonitorHDLNode(structural)
generic map(D_WIDTH => 64,
PKT_FILENAME => "pkt.out.txt")
port map(clk => clk,
rst => rst,
udp_in_ready => mcd_to_output_tready,
udp_in_valid => mcd_to_output_tvalid,
udp_in_keep => mcd_to_output_tkeep,
udp_in_user => mcd_to_output_tuser,
udp_in_last => mcd_to_output_tlast,
udp_in_data => mcd_to_output_tdata);
-- Hash Table DRAM model instantiation
dramHash: entity work.dramModel
port map(ap_clk => clk,
ap_rst_n => aresetn,
-- ht_dramRdData: Pull Input, 512b
rdDataOut_V_V_TVALID => ht_dramRdData_valid,
rdDataOut_V_V_TREADY => ht_dramRdData_ready,
rdDataOut_V_V_TDATA => ht_dramRdData_data,
-- ht_cmd_dramRdData: Push Output, 10b
rdCmdIn_V_TDATA => ht_cmd_dramRdData_data,
rdCmdIn_V_TVALID => ht_cmd_dramRdData_valid,
rdCmdIn_V_TREADY => ht_cmd_dramRdData_ready,
-- ht_dramWrData: Push Output, 512b
wrDataIn_V_V_TDATA => ht_dramWrData_data,
wrDataIn_V_V_TVALID => ht_dramWrData_valid,
wrDataIn_V_V_TREADY => ht_dramWrData_ready,
-- ht_cmd_dramWrData: Push Output, 10b
wrCmdIn_V_TDATA => ht_cmd_dramWrData_data,
wrCmdIn_V_TVALID => ht_cmd_dramWrData_valid,
wrCmdIn_V_TREADY => ht_cmd_dramWrData_ready);
-- Update Table DRAM model instantiation
dramUpd: entity work.dramModel
port map(ap_clk => clk,
ap_rst_n => aresetn,
-- ht_dramRdData: Pull Input, 512b
rdDataOut_V_V_TVALID => upd_dramRdData_valid,
rdDataOut_V_V_TREADY => upd_dramRdData_ready,
rdDataOut_V_V_TDATA => upd_dramRdData_data,
-- ht_cmd_dramRdData: Push Output, 10b
rdCmdIn_V_TDATA => upd_cmd_dramRdData_data,
rdCmdIn_V_TVALID => upd_cmd_dramRdData_valid,
rdCmdIn_V_TREADY => upd_cmd_dramRdData_ready,
-- ht_dramWrData: Push Output, 512b
wrDataIn_V_V_TDATA => upd_dramWrData_data,
wrDataIn_V_V_TVALID => upd_dramWrData_valid,
wrDataIn_V_V_TREADY => upd_dramWrData_ready,
-- ht_cmd_dramWrData: Push Output, 10b
wrCmdIn_V_TDATA => upd_cmd_dramWrData_data,
wrCmdIn_V_TVALID => upd_cmd_dramWrData_valid,
wrCmdIn_V_TREADY => upd_cmd_dramWrData_ready);
--udp_in_data_im <= "0000000000" & udp_in_data;
--udp_in_data_im <= "000" & udp_in_data;
flashUpd: entity work.flashModel
port map(ap_clk => clk,
ap_rst_n => aresetn,
-- ht_dramRdData: Pull Input, 64b
rdDataOut_V_V_TVALID => upd_flashRdData_valid,
rdDataOut_V_V_TREADY => upd_flashRdData_ready,
rdDataOut_V_V_TDATA => upd_flashRdData_data,
-- ht_cmd_dramRdData: Push Output, 48b
rdCmdIn_V_TDATA => upd_cmd_flashRdData_data,
rdCmdIn_V_TVALID => upd_cmd_flashRdData_valid,
rdCmdIn_V_TREADY => upd_cmd_flashRdData_ready,
-- ht_dramWrData: Push Output, 64b
wrDataIn_V_V_TDATA => upd_flashWrData_data,
wrDataIn_V_V_TVALID => upd_flashWrData_valid,
wrDataIn_V_V_TREADY => upd_flashWrData_ready,
-- ht_cmd_dramWrData: Push Output, 48b
wrCmdIn_V_TDATA => upd_cmd_flashWrData_data,
wrCmdIn_V_TVALID => upd_cmd_flashWrData_valid,
wrCmdIn_V_TREADY => upd_cmd_flashWrData_ready);
-- Dummy PCIe memory allocation module
memAllocator: entity work.dummypciejoint_top
port map(inData_V_V_TVALID => memcached2memAllocation_valid,
inData_V_V_TREADY => memcached2memAllocation_ready,
inData_V_V_TDATA => memcached2memAllocation_data,
outDataDram_V_V_TVALID => memAllocation2memcached_dram_valid,
outDataDram_V_V_TREADY => memAllocation2memcached_dram_ready,
outDataDram_V_V_TDATA => memAllocation2memcached_dram_data,
outDataFlash_V_V_TVALID => memAllocation2memcached_flash_valid,
outDataFlash_V_V_TREADY => memAllocation2memcached_flash_ready,
outDataFlash_V_V_TDATA => memAllocation2memcached_flash_data,
flushReq_V => flushReq,
flushAck_V => flushAck,
flushDone_V => flushDone,
aresetn => aresetn,
aclk => clk);
-- memcached Pipeline Instantiation
myMemcachedPipeline: entity work.memcachedpipeline
port map (hashTableMemRdCmd_V_TVALID => ht_cmd_dramRdData_valid,
hashTableMemRdCmd_V_TREADY => ht_cmd_dramRdData_ready,
hashTableMemRdCmd_V_TDATA => ht_cmd_dramRdData_data,
hashTableMemRdData_V_V_TVALID => ht_dramRdData_valid,
hashTableMemRdData_V_V_TREADY => ht_dramRdData_ready,
hashTableMemRdData_V_V_TDATA => ht_dramRdData_data,
hashTableMemWrCmd_V_TVALID => ht_cmd_dramWrData_valid,
hashTableMemWrCmd_V_TREADY => ht_cmd_dramWrData_ready,
hashTableMemWrCmd_V_TDATA => ht_cmd_dramWrData_data,
hashTableMemWrData_V_V_TVALID => ht_dramWrData_valid,
hashTableMemWrData_V_V_TREADY => ht_dramWrData_ready,
hashTableMemWrData_V_V_TDATA => ht_dramWrData_data,
inData_TVALID => input_to_mcd_tvalid,
inData_TREADY => input_to_mcd_tready,
inData_TDATA => input_to_mcd_tdata,
inData_TKEEP => input_to_mcd_tkeep,
inData_TLAST => input_to_mcd_tlast,
inData_TUSER => input_to_mcd_tuser,
outData_TVALID => mcd_to_output_tvalid,
outData_TREADY => mcd_to_output_tready,
outData_TDATA => mcd_to_output_tdata,
outData_TUSER => mcd_to_output_tuser,
outData_TKEEP => mcd_to_output_tkeep,
outData_TLAST => mcd_to_output_tlast,
dramValueStoreMemRdCmd_V_TVALID => upd_cmd_dramRdData_valid,
dramValueStoreMemRdCmd_V_TREADY => upd_cmd_dramRdData_ready,
dramValueStoreMemRdCmd_V_TDATA => upd_cmd_dramRdData_data,
dramValueStoreMemRdData_V_V_TVALID => upd_dramRdData_valid,
dramValueStoreMemRdData_V_V_TREADY => upd_dramRdData_ready,
dramValueStoreMemRdData_V_V_TDATA => upd_dramRdData_data,
dramValueStoreMemWrCmd_V_TVALID => upd_cmd_dramWrData_valid,
dramValueStoreMemWrCmd_V_TREADY => upd_cmd_dramWrData_ready,
dramValueStoreMemWrCmd_V_TDATA => upd_cmd_dramWrData_data,
dramValueStoreMemWrData_V_V_TVALID => upd_dramWrData_valid,
dramValueStoreMemWrData_V_V_TREADY => upd_dramWrData_ready,
dramValueStoreMemWrData_V_V_TDATA => upd_dramWrData_data,
flashValueStoreMemRdCmd_V_TVALID => upd_cmd_flashRdData_valid,
flashValueStoreMemRdCmd_V_TREADY => upd_cmd_flashRdData_ready,
flashValueStoreMemRdCmd_V_TDATA => upd_cmd_flashRdData_data,
flashValueStoreMemRdData_V_V_TVALID => upd_flashRdData_valid,
flashValueStoreMemRdData_V_V_TREADY => upd_flashRdData_ready,
flashValueStoreMemRdData_V_V_TDATA => upd_flashRdData_data,
flashValueStoreMemWrCmd_V_TVALID => upd_cmd_flashWrData_valid,
flashValueStoreMemWrCmd_V_TREADY => upd_cmd_flashWrData_ready,
flashValueStoreMemWrCmd_V_TDATA => upd_cmd_flashWrData_data,
flashValueStoreMemWrData_V_V_TVALID => upd_flashWrData_valid,
flashValueStoreMemWrData_V_V_TREADY => upd_flashWrData_ready,
flashValueStoreMemWrData_V_V_TDATA => upd_flashWrData_data,
addressReturnOut_V_V_TDATA => memcached2memAllocation_data,
addressReturnOut_V_V_TVALID => memcached2memAllocation_valid,
addressReturnOut_V_V_TREADY => memcached2memAllocation_ready,
addressAssignDramIn_V_V_TDATA => memAllocation2memcached_dram_data,
addressAssignDramIn_V_V_TVALID => memAllocation2memcached_dram_valid,
addressAssignDramIn_V_V_TREADY => memAllocation2memcached_dram_ready,
addressAssignFlashIn_V_V_TDATA => memAllocation2memcached_flash_data,
addressAssignFlashIn_V_V_TVALID => memAllocation2memcached_flash_valid,
addressAssignFlashIn_V_V_TREADY => memAllocation2memcached_flash_ready,
ap_rst_n => aresetn,
ap_clk => clk,
flushReq_V => flushReq,
flushAck_V => flushAck,
flushDone_V => flushDone);
end Structural;
| bsd-3-clause | 0f66b37a8f7175bd24380fcc0a541b00 | 0.609192 | 3.427857 | false | false | false | false |
hacklabmikkeli/rough-boy | env_gen.vhdl | 2 | 3,975 | --
-- Knobs Galore - a free phase distortion synthesizer
-- Copyright (C) 2015 Ilmo Euro
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.common.all;
entity env_gen is
port (EN: in std_logic
;CLK: in std_logic
;GATE: in std_logic
;MIN: in ctl_signal
;MAX: in ctl_signal
;A_RATE: in ctl_signal
;D_RATE: in ctl_signal
;S_LVL: in ctl_signal
;R_RATE: in ctl_signal
;ENV_IN: in time_signal
;ENV_OUT: out time_signal
;STAGE_IN: in adsr_stage
;STAGE_OUT: out adsr_stage
;PREV_GATE_IN: in std_logic
;PREV_GATE_OUT: out std_logic
)
;
end entity;
architecture env_gen_impl of env_gen is
constant zero_f : time_signal := (others => '0');
constant zero_c : ctl_signal := (others => '0');
constant time_max_val : time_signal := to_unsigned(time_max - 1, time_bits);
constant bit_diff : natural := time_bits - ctl_bits - 1;
constant zero_f_min_c : unsigned(bit_diff downto 0) := (others => '0');
signal env_out_buf: time_signal := (others => '0');
signal stage_out_buf: adsr_stage := adsr_rel;
signal prev_gate_out_buf: std_logic := '0';
begin
process(CLK)
variable next_env_out: time_signal;
variable next_stage_out: adsr_stage;
begin
if EN = '1' and rising_edge(CLK) then
next_env_out := ENV_IN;
next_stage_out := STAGE_IN;
case next_stage_out is
when adsr_attack =>
if ENV_IN >= (MAX & zero_f_min_c) - A_RATE then
next_env_out := MAX & zero_f_min_c;
next_stage_out := adsr_decay;
else
next_env_out := ENV_IN + A_RATE;
end if;
when adsr_decay =>
if ENV_IN < (S_LVL & zero_f_min_c) + D_RATE then
next_env_out := S_LVL & zero_f_min_c;
next_stage_out := adsr_sustain;
else
next_env_out := ENV_IN - D_RATE;
end if;
when adsr_sustain =>
next_env_out := ENV_IN;
when adsr_rel =>
if ENV_IN < (MIN & zero_f_min_c) + R_RATE then
next_env_out := MIN & zero_f_min_c;
else
next_env_out := ENV_IN - R_RATE;
end if;
when others => -- non-binary values
null;
end case;
if PREV_GATE_IN = '0' and GATE = '1' then
next_stage_out := adsr_attack;
elsif PREV_GATE_IN = '1' and GATE = '0' then
next_stage_out := adsr_rel;
end if;
env_out_buf <= next_env_out;
stage_out_buf <= next_stage_out;
prev_gate_out_buf <= GATE;
end if;
end process;
ENV_OUT <= env_out_buf;
STAGE_OUT <= stage_out_buf;
PREV_GATE_OUT <= prev_gate_out_buf;
end architecture;
| gpl-3.0 | b045e9f145cfd8e866c325bf3ec7a557 | 0.504151 | 3.718428 | false | false | false | false |
hacklabmikkeli/rough-boy | mixer.vhdl | 2 | 1,907 | --
-- Knobs Galore - a free phase distortion synthesizer
-- Copyright (C) 2015 Ilmo Euro
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.common.all;
entity mixer is
port (EN: in std_logic
;CLK: in std_logic
;MUXED_IN: in voice_signal
;AUDIO_OUT: out audio_signal
);
end entity;
architecture mixer_impl of mixer is
signal accumulator: audio_signal := (others => '0');
signal audio_out_buf: audio_signal := (others => '0');
signal counter: unsigned(voices_bits - 1 downto 0) := (others=>'0');
begin
process(CLK)
variable zero: unsigned(voices_bits - 1 downto 0) := (others=>'0');
begin
if EN = '1' and rising_edge(CLK) then
if counter = zero then
audio_out_buf <= accumulator;
accumulator(voice_bits - 1 downto 0) <= MUXED_IN;
accumulator(audio_bits - 1 downto voice_bits) <= (others=>'0');
else
accumulator <= accumulator + MUXED_IN;
end if;
counter <= counter + 1;
end if;
end process;
AUDIO_OUT <= audio_out_buf;
end architecture;
| gpl-3.0 | 3268f05c2fb35bc776410eb843de6c08 | 0.611956 | 3.972917 | false | false | false | false |
makestuff/spi-master | vhdl/tb_lsbfirst/spi_master_tb.vhdl | 1 | 5,405 | --
-- Copyright (C) 2011, 2013 Chris McClelland
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU Lesser General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU Lesser General Public License for more details.
--
-- You should have received a copy of the GNU Lesser General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_textio.all;
use std.textio.all;
use work.hex_util.all;
entity spi_master_tb is
end entity;
architecture behavioural of spi_master_tb is
-- Clocks, etc
signal sysClk : std_logic; -- main system clock
signal dispClk : std_logic; -- display version of sysClk, which transitions 4ns before it
signal reset : std_logic;
-- Client interface
signal sendData : std_logic_vector(7 downto 0); -- data to send
signal sendValid : std_logic;
signal sendReady : std_logic;
signal recvData : std_logic_vector(7 downto 0); -- data we receive
signal recvValid : std_logic;
signal recvReady : std_logic;
-- External interface
signal spiClk : std_logic; -- serial clock
signal spiDataOut : std_logic; -- send serial data
signal spiDataIn : std_logic; -- receive serial data
begin
-- Instantiate the unit under test
uut: entity work.spi_master
generic map(
--FAST_COUNT => "000011"
FAST_COUNT => "000000",
BIT_ORDER => '0'
)
port map(
reset_in => reset,
clk_in => sysClk,
turbo_in => '1',
suppress_in => '0',
sendData_in => sendData,
sendValid_in => sendValid,
sendReady_out => sendReady,
recvData_out => recvData,
recvValid_out => recvValid,
recvReady_in => recvReady,
spiClk_out => spiClk,
spiData_out => spiDataOut,
spiData_in => spiDataIn
);
-- Drive the clocks. In simulation, sysClk lags 4ns behind dispClk, to give a visual hold time
-- for signals in GTKWave.
process
begin
sysClk <= '0';
dispClk <= '0';
wait for 16 ns;
loop
dispClk <= not(dispClk); -- first dispClk transitions
wait for 4 ns;
sysClk <= not(sysClk); -- then sysClk transitions, 4ns later
wait for 6 ns;
end loop;
end process;
-- Deassert the synchronous reset a couple of cycles after startup.
--
process
begin
reset <= '1';
wait until rising_edge(sysClk);
wait until rising_edge(sysClk);
reset <= '0';
wait;
end process;
-- Drive the unit under test. Read stimulus from stimulus.sim and write results to results.sim
process
variable inLine : line;
variable outLine : line;
file inFile : text open read_mode is "stimulus/send.sim";
file outFile : text open write_mode is "results/recv.sim";
begin
sendData <= (others => 'X');
sendValid <= '0';
wait until falling_edge(reset);
wait until rising_edge(sysClk);
while ( not endfile(inFile) ) loop
readline(inFile, inLine);
while ( inLine.all'length = 0 or inLine.all(1) = '#' or inLine.all(1) = ht or inLine.all(1) = ' ' ) loop
readline(inFile, inLine);
end loop;
sendData <= to_4(inLine.all(1)) & to_4(inLine.all(2));
sendValid <= to_1(inLine.all(4));
recvReady <= to_1(inLine.all(6));
wait for 10 ns;
write(outLine, from_4(sendData(7 downto 4)) & from_4(sendData(3 downto 0)));
write(outLine, ' ');
write(outLine, sendValid);
write(outLine, ' ');
write(outLine, sendReady);
writeline(outFile, outLine);
wait for 10 ns;
end loop;
sendData <= (others => 'X');
sendValid <= '0';
wait;
end process;
-- Mock the serial interface's interlocutor: send from s/recv.sim and receive into r/send.sim
process
variable inLine, outLine : line;
variable inData, outData : std_logic_vector(7 downto 0);
file inFile : text open read_mode is "stimulus/recv.sim";
file outFile : text open write_mode is "results/send.sim";
begin
spiDataIn <= 'X';
loop
exit when endfile(inFile);
readline(inFile, inLine);
read(inLine, inData);
wait until spiClk = '0';
spiDataIn <= inData(0);
wait until spiClk = '1';
outData(0) := spiDataOut;
wait until spiClk = '0';
spiDataIn <= inData(1);
wait until spiClk = '1';
outData(1) := spiDataOut;
wait until spiClk = '0';
spiDataIn <= inData(2);
wait until spiClk = '1';
outData(2) := spiDataOut;
wait until spiClk = '0';
spiDataIn <= inData(3);
wait until spiClk = '1';
outData(3) := spiDataOut;
wait until spiClk = '0';
spiDataIn <= inData(4);
wait until spiClk = '1';
outData(4) := spiDataOut;
wait until spiClk = '0';
spiDataIn <= inData(5);
wait until spiClk = '1';
outData(5) := spiDataOut;
wait until spiClk = '0';
spiDataIn <= inData(6);
wait until spiClk = '1';
outData(6) := spiDataOut;
wait until spiClk = '0';
spiDataIn <= inData(7);
wait until spiClk = '1';
outData(7) := spiDataOut;
write(outLine, outData);
writeline(outFile, outLine);
end loop;
wait for 10 ns;
spiDataIn <= 'X';
wait;
end process;
end architecture;
| gpl-3.0 | d832769fac9e8ddef644a2ae7b0b7d78 | 0.655319 | 3.291717 | false | false | false | false |
rafa-jfet/OFM | ARCHIVOS VHDL/mem_read.vhd | 1 | 4,632 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 19:23:11 04/14/2015
-- Design Name:
-- Module Name: mem_read - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--cambio lsosososo
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_logic_arith.ALL;
use IEEE.std_logic_unsigned.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity mem_read is
Generic ( ancho_bus_direcc : integer := 4;
TAM_BYTE : integer := 8;
bit_DBPSK : integer := 48;
bit_DQPSK : integer := 96;
bit_D8PSK : integer := 144);
Port ( clk : in STD_LOGIC;
reset : in STD_LOGIC;
button : in STD_LOGIC;
data : in STD_LOGIC_VECTOR (7 downto 0);
modulation : in STD_LOGIC_VECTOR (2 downto 0);
sat : in STD_LOGIC;
direcc : out STD_LOGIC_VECTOR (ancho_bus_direcc -1 downto 0);
bit_out : out STD_LOGIC;
ok_bit_out : out STD_LOGIC;
fin : out STD_LOGIC);
end mem_read;
architecture Behavioral of mem_read is
type estado is ( reposo,
inicio,
test_data,
b_0,
b_1,
b_2,
b_3,
b_4,
b_5,
b_6,
b_7,
-- dir_estable,
rellena);
signal estado_actual : estado;
signal estado_nuevo : estado;
signal dir, p_dir : STD_LOGIC_VECTOR ( ancho_bus_direcc -1 downto 0);
signal cont_bit, p_cont_bit : integer range 0 to bit_D8PSK;
signal p_ok_bit_out : STD_LOGIC;
begin
direcc <= dir;
comb : process (estado_actual, button, modulation, data, cont_bit, dir, sat)
begin
p_dir <= dir;
p_cont_bit <= cont_bit;
bit_out <= '0';
p_ok_bit_out <= '0';
fin <= '0';
estado_nuevo <= estado_actual;
case estado_actual is
when reposo => -- espera hasta que se activa "button"
if ( button = '1' ) then
estado_nuevo <= inicio;
end if;
when inicio =>
estado_nuevo <= test_data;
if ( cont_bit = 0 ) then
case modulation is
when "100" =>
p_cont_bit <= bit_DBPSK;
when "010" =>
p_cont_bit <= bit_DQPSK;
when OTHERS =>
p_cont_bit <= bit_D8PSK;
end case;
end if;
when test_data =>
if ( data = "00000000" ) then
estado_nuevo <= rellena;
else
estado_nuevo <= b_0;
p_ok_bit_out <= '1';
end if;
when rellena => --añade los ceros necesarios para completar un simbolo
estado_nuevo <= rellena;
if ( cont_bit -6 = 0 ) then
estado_nuevo <= reposo;
fin <= '1';
elsif ( sat = '1' ) then
p_cont_bit <= cont_bit -1;
p_ok_bit_out <= '1';
end if;
when b_0 =>
bit_out <= data(7);
if ( sat = '1' ) then
estado_nuevo <= b_1;
p_ok_bit_out <= '1';
end if;
when b_1 =>
bit_out <= data(6);
if ( sat = '1' ) then
estado_nuevo <= b_2;
p_ok_bit_out <= '1';
end if;
when b_2 =>
bit_out <= data(5);
if ( sat = '1' ) then
estado_nuevo <= b_3;
p_ok_bit_out <= '1';
end if;
when b_3 =>
bit_out <= data(4);
if ( sat = '1' ) then
estado_nuevo <= b_4;
p_ok_bit_out <= '1';
end if;
when b_4 =>
bit_out <= data(3);
if ( sat = '1' ) then
estado_nuevo <= b_5;
p_ok_bit_out <= '1';
end if;
when b_5 =>
bit_out <= data(2);
if ( sat = '1' ) then
estado_nuevo <= b_6;
p_ok_bit_out <= '1';
end if;
when b_6 =>
bit_out <= data(1);
if ( sat = '1' ) then
estado_nuevo <= b_7;
p_ok_bit_out <= '1';
end if;
when b_7 =>
bit_out <= data(0);
if ( sat = '1' ) then
estado_nuevo <= inicio;
p_dir <= dir +1;
p_cont_bit <= cont_bit -TAM_BYTE;
end if;
-- when dir_estable =>
-- estado_nuevo <= inicio;
end case;
end process;
sinc : process ( reset, clk)
begin
if ( reset = '1' ) then
cont_bit <= 0;
dir <= (others => '0');
ok_bit_out <= '0';
estado_actual <= reposo;
elsif ( rising_edge(clk) ) then
ok_bit_out <= p_ok_bit_out;
cont_bit <= p_cont_bit;
dir <= p_dir;
estado_actual <= estado_nuevo;
end if;
end process;
end Behavioral;
| gpl-3.0 | 7e314f9560face07918068590c559e42 | 0.523316 | 2.838235 | false | false | false | false |
gmsanchez/OrgComp | TP_02/TB_RegSHL_32b.vhd | 1 | 3,090 | -- Ejercicio 1(b)
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE work.txt_util.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY TB_RegSHL_32b IS
END TB_RegSHL_32b;
ARCHITECTURE behavior OF TB_RegSHL_32b IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT RegSHL_32b
PORT(
D : IN std_logic_vector(31 downto 0);
LOAD : in STD_LOGIC;
SHL : in STD_LOGIC;
SLI : in STD_LOGIC;
CLK : in STD_LOGIC;
RST : in STD_LOGIC;
O : BUFFER std_logic_vector(31 downto 0)
);
END COMPONENT;
--Inputs
signal D : std_logic_vector(31 downto 0) := (others => '0');
signal LOAD : std_logic := '0';
signal SHL : std_logic := '0';
signal SLI : std_logic := '0';
signal CLK : std_logic := '0';
signal RST : std_logic := '0';
--Outputs
signal O : std_logic_vector(31 downto 0);
-- Clock period definitions
constant CLK_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: RegSHL_32b PORT MAP (
D => D,
LOAD => LOAD,
SHL => SHL,
SLI => SLI,
CLK => CLK,
RST => RST,
O => O
);
-- Clock process definitions
CLK_process :process
begin
CLK <= '0';
wait for CLK_period/2;
CLK <= '1';
wait for CLK_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
-- check initial status
wait for 6 ns;
-- hold reset state for 5 ns.
SLI <= '0';
RST <= '1';
LOAD <= '0';
SHL <= '0';
D <= x"FAFAFAFA";
wait for 5 ns;
RST <= '0';
wait for 15 ns;
LOAD <= '1';
SHL <= '1';
wait for 20 ns;
D <= x"00000040"; -- Cargo un 64
wait for 15 ns;
LOAD <= '0';
SHL <= '0';
wait for 10 ns;
-- Hasta acá es igual al el otro registro. Empecemos los shift.
LOAD <= '0';
SHL <= '1';
wait for 60 ns;
wait;
end process;
corr_proc: process(CLK)
variable theTime : time;
begin
theTime := now;
-- report time'image(theTime);
if theTime=10000 ps then
assert (O=x"00000000")
report "Resultado erroneo a los " & time'image(theTime) & " O=" & str(O)
severity ERROR;
end if;
if theTime=40000 ps then
assert (O=x"FAFAFAFA")
report "Resultado erroneo a los " & time'image(theTime) & " O=" & str(O)
severity ERROR;
end if;
if theTime=60000 ps then
assert (O=x"00000040")
report "Resultado erroneo a los " & time'image(theTime) & " O=" & str(O)
severity ERROR;
end if;
if theTime=70000 ps then
assert (O=x"00000040")
report "Resultado erroneo a los " & time'image(theTime) & " O=" & str(O)
severity ERROR;
end if;
if theTime=100000 ps then
assert (O=x"00000200")
report "Resultado erroneo a los " & time'image(theTime) & " O=" & str(O)
severity ERROR;
end if;
if theTime=120000 ps then
assert (O=x"00000800")
report "Resultado erroneo a los " & time'image(theTime) & " O=" & str(O)
severity ERROR;
end if;
end process;
END;
| gpl-2.0 | b8ded0141c1eed930b0f3d25c0756cec | 0.590806 | 3.010721 | false | false | false | false |
rafa-jfet/OFM | ARCHIVOS VHDL/IfftControl.vhd | 1 | 2,473 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 15:54:31 06/24/2015
-- Design Name:
-- Module Name: asd - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity IfftControl is
generic(
CARRIERS : INTEGER :=128 --
);
Port (
reset : in STD_LOGIC;
clk : in STD_LOGIC;
IfftEnable: in STD_LOGIC;
start : out STD_LOGIC;
cp_len : out STD_LOGIC_VECTOR(6 DOWNTO 0);
cp_len_we : out STD_LOGIC;
unload : out STD_LOGIC;
fwd_inv : out STD_LOGIC;
fwd_inv_we : out STD_LOGIC;
rfd : in STD_LOGIC);
end IfftControl;
architecture Behavioral of IfftControl is
--declaracion de estados
type estado is (reposo,
-- leyendo,
inicio,
activo);
--señales
signal estado_actual, estado_nuevo: estado;
-- signal datoIn : STD_LOGIC_VECTOR (15 downto 0);
-- signal outReal, outImag : STD_LOGIC_VECTOR (7 downto 0);
-- signal dire_actual, dire_nuevo: STD_LOGIC_VECTOR(6 downto 0);
-- signal addra, p_addra : INTEGER RANGE 0 to CARRIERS; -- deberia ser carriers -1 pero sino no detectamos que es mayor por que desborda
begin
cp_len<="0001100"; --configuracion prefijo ciclico
fwd_inv <='0'; -- inversa ifft
--proceso sincrono
sinc: process(reset, clk)
begin
if(reset='1') then
estado_actual <= reposo;
elsif (clk='1' and clk'event) then
estado_actual <= estado_nuevo;
end if;
end process;
comb: process (estado_actual, ifftEnable, rfd)
begin
estado_nuevo<= estado_actual;
start <='0';
cp_len_we <='0';
unload <='1';
fwd_inv_we<='0';
case estado_actual is
when reposo =>
if ifftEnable='1' then
estado_nuevo<= inicio;
else
estado_nuevo <=reposo;
end if;
when inicio =>
--Conexiones con el core de FFT
start <='1';
cp_len_we <='1';
fwd_inv_we<='1';
--saltamos a otro estado
estado_nuevo<= activo;
when activo =>
start <='0';
--saltamos a otro estado
if rfd='1' then
estado_nuevo<= activo;
else
estado_nuevo <= reposo;
end if;
end case;
end process;
end Behavioral;
| gpl-3.0 | e7f1c738e0a8228c3ac5216c59bf68ce | 0.577032 | 3.178663 | false | false | false | false |
emogenet/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc1474.vhd | 4 | 1,826 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1474.vhd,v 1.2 2001-10-26 16:29:41 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s08b00x00p04n01i01474ent IS
END c08s08b00x00p04n01i01474ent;
ARCHITECTURE c08s08b00x00p04n01i01474arch OF c08s08b00x00p04n01i01474ent IS
BEGIN
TESTING: PROCESS
variable k : integer := 0;
variable i : BIT := '0';
BEGIN
case i is
when '0' => k := 5;
when '1' => NULL;
when others => NULL;
end case;
assert NOT( k = 5 )
report "***PASSED TEST: c08s08b00x00p04n01i01474"
severity NOTE;
assert ( k = 5 )
report "***FAILED TEST: c08s08b00x00p04n01i01474 - expression of enumeration type"
severity ERROR;
wait;
END PROCESS TESTING;
END c08s08b00x00p04n01i01474arch;
| gpl-2.0 | a062603020ffa2ccae080117eaa8ffe4 | 0.650055 | 3.63745 | false | true | false | false |
emogenet/ghdl | libraries/ieee/math_real-body.vhdl | 4 | 65,450 | ------------------------------------------------------------------------
--
-- Copyright 1996 by IEEE. All rights reserved.
-- This source file is an informative part of IEEE Std 1076.2-1996, IEEE Standard
-- VHDL Mathematical Packages. This source file may not be copied, sold, or
-- included with software that is sold without written permission from the IEEE
-- Standards Department. This source file may be used to implement this standard
-- and may be distributed in compiled form in any manner so long as the
-- compiled form does not allow direct decompilation of the original source file.
-- This source file may be copied for individual use between licensed users.
-- This source file is provided on an AS IS basis. The IEEE disclaims ANY
-- WARRANTY EXPRESS OR IMPLIED INCLUDING ANY WARRANTY OF MERCHANTABILITY
-- AND FITNESS FOR USE FOR A PARTICULAR PURPOSE. The user of the source
-- file shall indemnify and hold IEEE harmless from any damages or liability
-- arising out of the use thereof.
--
-- Title: Standard VHDL Mathematical Packages (IEEE Std 1076.2-1996,
-- MATH_REAL)
--
-- Library: This package shall be compiled into a library
-- symbolically named IEEE.
--
-- Developers: IEEE DASC VHDL Mathematical Packages Working Group
--
-- Purpose: This package body is a nonnormative implementation of the
-- functionality defined in the MATH_REAL package declaration.
--
-- Limitation: The values generated by the functions in this package may
-- vary from platform to platform, and the precision of results
-- is only guaranteed to be the minimum required by IEEE Std 1076
-- -1993.
--
-- Notes:
-- The "package declaration" defines the types, subtypes, and
-- declarations of MATH_REAL.
-- The standard mathematical definition and conventional meaning
-- of the mathematical functions that are part of this standard
-- represent the formal semantics of the implementation of the
-- MATH_REAL package declaration. The purpose of the MATH_REAL
-- package body is to clarify such semantics and provide a
-- guideline for implementations to verify their implementation
-- of MATH_REAL. Tool developers may choose to implement
-- the package body in the most efficient manner available to them.
--
-- -----------------------------------------------------------------------------
-- Version : 1.5
-- Date : 24 July 1996
-- -----------------------------------------------------------------------------
package body MATH_REAL is
--
-- Local Constants for Use in the Package Body Only
--
constant MATH_E_P2 : REAL := 7.38905_60989_30650; -- e**2
constant MATH_E_P10 : REAL := 22026.46579_48067_17; -- e**10
constant MATH_EIGHT_PI : REAL := 25.13274_12287_18345_90770_115; --8*pi
constant MAX_ITER: INTEGER := 27; -- Maximum precision factor for cordic
constant MAX_COUNT: INTEGER := 150; -- Maximum count for number of tries
constant BASE_EPS: REAL := 0.00001; -- Factor for convergence criteria
constant KC : REAL := 6.0725293500888142e-01; -- Constant for cordic
--
-- Local Type Declarations for Cordic Operations
--
type REAL_VECTOR is array (NATURAL range <>) of REAL;
type NATURAL_VECTOR is array (NATURAL range <>) of NATURAL;
subtype REAL_VECTOR_N is REAL_VECTOR (0 to MAX_ITER);
subtype REAL_ARR_2 is REAL_VECTOR (0 to 1);
subtype REAL_ARR_3 is REAL_VECTOR (0 to 2);
subtype QUADRANT is INTEGER range 0 to 3;
type CORDIC_MODE_TYPE is (ROTATION, VECTORING);
--
-- Auxiliary Functions for Cordic Algorithms
--
function POWER_OF_2_SERIES (D : in NATURAL_VECTOR; INITIAL_VALUE : in REAL;
NUMBER_OF_VALUES : in NATURAL) return REAL_VECTOR is
-- Description:
-- Returns power of two for a vector of values
-- Notes:
-- None
--
variable V : REAL_VECTOR (0 to NUMBER_OF_VALUES);
variable TEMP : REAL := INITIAL_VALUE;
variable FLAG : BOOLEAN := TRUE;
begin
for I in 0 to NUMBER_OF_VALUES loop
V(I) := TEMP;
for P in D'RANGE loop
if I = D(P) then
FLAG := FALSE;
exit;
end if;
end loop;
if FLAG then
TEMP := TEMP/2.0;
end if;
FLAG := TRUE;
end loop;
return V;
end POWER_OF_2_SERIES;
constant TWO_AT_MINUS : REAL_VECTOR := POWER_OF_2_SERIES(
NATURAL_VECTOR'(100, 90),1.0,
MAX_ITER);
constant EPSILON : REAL_VECTOR_N := (
7.8539816339744827e-01,
4.6364760900080606e-01,
2.4497866312686413e-01,
1.2435499454676144e-01,
6.2418809995957351e-02,
3.1239833430268277e-02,
1.5623728620476830e-02,
7.8123410601011116e-03,
3.9062301319669717e-03,
1.9531225164788189e-03,
9.7656218955931937e-04,
4.8828121119489829e-04,
2.4414062014936175e-04,
1.2207031189367021e-04,
6.1035156174208768e-05,
3.0517578115526093e-05,
1.5258789061315760e-05,
7.6293945311019699e-06,
3.8146972656064960e-06,
1.9073486328101870e-06,
9.5367431640596080e-07,
4.7683715820308876e-07,
2.3841857910155801e-07,
1.1920928955078067e-07,
5.9604644775390553e-08,
2.9802322387695303e-08,
1.4901161193847654e-08,
7.4505805969238281e-09
);
function CORDIC ( X0 : in REAL;
Y0 : in REAL;
Z0 : in REAL;
N : in NATURAL; -- Precision factor
CORDIC_MODE : in CORDIC_MODE_TYPE -- Rotation (Z -> 0)
-- or vectoring (Y -> 0)
) return REAL_ARR_3 is
-- Description:
-- Compute cordic values
-- Notes:
-- None
variable X : REAL := X0;
variable Y : REAL := Y0;
variable Z : REAL := Z0;
variable X_TEMP : REAL;
begin
if CORDIC_MODE = ROTATION then
for K in 0 to N loop
X_TEMP := X;
if ( Z >= 0.0) then
X := X - Y * TWO_AT_MINUS(K);
Y := Y + X_TEMP * TWO_AT_MINUS(K);
Z := Z - EPSILON(K);
else
X := X + Y * TWO_AT_MINUS(K);
Y := Y - X_TEMP * TWO_AT_MINUS(K);
Z := Z + EPSILON(K);
end if;
end loop;
else
for K in 0 to N loop
X_TEMP := X;
if ( Y < 0.0) then
X := X - Y * TWO_AT_MINUS(K);
Y := Y + X_TEMP * TWO_AT_MINUS(K);
Z := Z - EPSILON(K);
else
X := X + Y * TWO_AT_MINUS(K);
Y := Y - X_TEMP * TWO_AT_MINUS(K);
Z := Z + EPSILON(K);
end if;
end loop;
end if;
return REAL_ARR_3'(X, Y, Z);
end CORDIC;
--
-- Bodies for Global Mathematical Functions Start Here
--
function SIGN (X: in REAL ) return REAL is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- None
begin
if ( X > 0.0 ) then
return 1.0;
elsif ( X < 0.0 ) then
return -1.0;
else
return 0.0;
end if;
end SIGN;
function CEIL (X : in REAL ) return REAL is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) No conversion to an INTEGER type is expected, so truncate
-- cannot overflow for large arguments
-- b) The domain supported by this function is X <= LARGE
-- c) Returns X if ABS(X) >= LARGE
constant LARGE: REAL := REAL(INTEGER'HIGH);
variable RD: REAL;
begin
if ABS(X) >= LARGE then
return X;
end if;
RD := REAL ( INTEGER(X));
if RD = X then
return X;
end if;
if X > 0.0 then
if RD >= X then
return RD;
else
return RD + 1.0;
end if;
elsif X = 0.0 then
return 0.0;
else
if RD <= X then
return RD + 1.0;
else
return RD;
end if;
end if;
end CEIL;
function FLOOR (X : in REAL ) return REAL is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) No conversion to an INTEGER type is expected, so truncate
-- cannot overflow for large arguments
-- b) The domain supported by this function is ABS(X) <= LARGE
-- c) Returns X if ABS(X) >= LARGE
constant LARGE: REAL := REAL(INTEGER'HIGH);
variable RD: REAL;
begin
if ABS( X ) >= LARGE then
return X;
end if;
RD := REAL ( INTEGER(X));
if RD = X then
return X;
end if;
if X > 0.0 then
if RD <= X then
return RD;
else
return RD - 1.0;
end if;
elsif X = 0.0 then
return 0.0;
else
if RD >= X then
return RD - 1.0;
else
return RD;
end if;
end if;
end FLOOR;
function ROUND (X : in REAL ) return REAL is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns 0.0 if X = 0.0
-- b) Returns FLOOR(X + 0.5) if X > 0
-- c) Returns CEIL(X - 0.5) if X < 0
begin
if X > 0.0 then
return FLOOR(X + 0.5);
elsif X < 0.0 then
return CEIL( X - 0.5);
else
return 0.0;
end if;
end ROUND;
function TRUNC (X : in REAL ) return REAL is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns 0.0 if X = 0.0
-- b) Returns FLOOR(X) if X > 0
-- c) Returns CEIL(X) if X < 0
begin
if X > 0.0 then
return FLOOR(X);
elsif X < 0.0 then
return CEIL( X);
else
return 0.0;
end if;
end TRUNC;
function "MOD" (X, Y: in REAL ) return REAL is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns 0.0 on error
variable XNEGATIVE : BOOLEAN := X < 0.0;
variable YNEGATIVE : BOOLEAN := Y < 0.0;
variable VALUE : REAL;
begin
-- Check validity of input arguments
if (Y = 0.0) then
assert FALSE
report "MOD(X, 0.0) is undefined"
severity ERROR;
return 0.0;
end if;
-- Compute value
if ( XNEGATIVE ) then
if ( YNEGATIVE ) then
VALUE := X + (FLOOR(ABS(X)/ABS(Y)))*ABS(Y);
else
VALUE := X + (CEIL(ABS(X)/ABS(Y)))*ABS(Y);
end if;
else
if ( YNEGATIVE ) then
VALUE := X - (CEIL(ABS(X)/ABS(Y)))*ABS(Y);
else
VALUE := X - (FLOOR(ABS(X)/ABS(Y)))*ABS(Y);
end if;
end if;
return VALUE;
end "MOD";
function REALMAX (X, Y : in REAL ) return REAL is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) REALMAX(X,Y) = X when X = Y
--
begin
if X >= Y then
return X;
else
return Y;
end if;
end REALMAX;
function REALMIN (X, Y : in REAL ) return REAL is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) REALMIN(X,Y) = X when X = Y
--
begin
if X <= Y then
return X;
else
return Y;
end if;
end REALMIN;
procedure UNIFORM(variable SEED1,SEED2:inout POSITIVE;variable X:out REAL)
is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns 0.0 on error
--
variable Z, K: INTEGER;
variable TSEED1 : INTEGER := INTEGER'(SEED1);
variable TSEED2 : INTEGER := INTEGER'(SEED2);
begin
-- Check validity of arguments
if SEED1 > 2147483562 then
assert FALSE
report "SEED1 > 2147483562 in UNIFORM"
severity ERROR;
X := 0.0;
return;
end if;
if SEED2 > 2147483398 then
assert FALSE
report "SEED2 > 2147483398 in UNIFORM"
severity ERROR;
X := 0.0;
return;
end if;
-- Compute new seed values and pseudo-random number
K := TSEED1/53668;
TSEED1 := 40014 * (TSEED1 - K * 53668) - K * 12211;
if TSEED1 < 0 then
TSEED1 := TSEED1 + 2147483563;
end if;
K := TSEED2/52774;
TSEED2 := 40692 * (TSEED2 - K * 52774) - K * 3791;
if TSEED2 < 0 then
TSEED2 := TSEED2 + 2147483399;
end if;
Z := TSEED1 - TSEED2;
if Z < 1 then
Z := Z + 2147483562;
end if;
-- Get output values
SEED1 := POSITIVE'(TSEED1);
SEED2 := POSITIVE'(TSEED2);
X := REAL(Z)*4.656613e-10;
end UNIFORM;
function SQRT (X : in REAL ) return REAL is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Uses the Newton-Raphson approximation:
-- F(n+1) = 0.5*[F(n) + x/F(n)]
-- b) Returns 0.0 on error
--
constant EPS : REAL := BASE_EPS*BASE_EPS; -- Convergence factor
variable INIVAL: REAL;
variable OLDVAL : REAL ;
variable NEWVAL : REAL ;
variable COUNT : INTEGER := 1;
begin
-- Check validity of argument
if ( X < 0.0 ) then
assert FALSE
report "X < 0.0 in SQRT(X)"
severity ERROR;
return 0.0;
end if;
-- Get the square root for special cases
if X = 0.0 then
return 0.0;
else
if ( X = 1.0 ) then
return 1.0;
end if;
end if;
-- Get the square root for general cases
INIVAL := EXP(LOG(X)*(0.5)); -- Mathematically correct but imprecise
OLDVAL := INIVAL;
NEWVAL := (X/OLDVAL + OLDVAL)*0.5;
-- Check for relative and absolute error and max count
while ( ( (ABS((NEWVAL -OLDVAL)/NEWVAL) > EPS) OR
(ABS(NEWVAL - OLDVAL) > EPS) ) AND
(COUNT < MAX_COUNT) ) loop
OLDVAL := NEWVAL;
NEWVAL := (X/OLDVAL + OLDVAL)*0.5;
COUNT := COUNT + 1;
end loop;
return NEWVAL;
end SQRT;
function CBRT (X : in REAL ) return REAL is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Uses the Newton-Raphson approximation:
-- F(n+1) = (1/3)*[2*F(n) + x/F(n)**2];
--
constant EPS : REAL := BASE_EPS*BASE_EPS;
variable INIVAL: REAL;
variable XLOCAL : REAL := X;
variable NEGATIVE : BOOLEAN := X < 0.0;
variable OLDVAL : REAL ;
variable NEWVAL : REAL ;
variable COUNT : INTEGER := 1;
begin
-- Compute root for special cases
if X = 0.0 then
return 0.0;
elsif ( X = 1.0 ) then
return 1.0;
else
if X = -1.0 then
return -1.0;
end if;
end if;
-- Compute root for general cases
if NEGATIVE then
XLOCAL := -X;
end if;
INIVAL := EXP(LOG(XLOCAL)/(3.0)); -- Mathematically correct but
-- imprecise
OLDVAL := INIVAL;
NEWVAL := (XLOCAL/(OLDVAL*OLDVAL) + 2.0*OLDVAL)/3.0;
-- Check for relative and absolute errors and max count
while ( ( (ABS((NEWVAL -OLDVAL)/NEWVAL) > EPS ) OR
(ABS(NEWVAL - OLDVAL) > EPS ) ) AND
( COUNT < MAX_COUNT ) ) loop
OLDVAL := NEWVAL;
NEWVAL :=(XLOCAL/(OLDVAL*OLDVAL) + 2.0*OLDVAL)/3.0;
COUNT := COUNT + 1;
end loop;
if NEGATIVE then
NEWVAL := -NEWVAL;
end if;
return NEWVAL;
end CBRT;
function "**" (X : in INTEGER; Y : in REAL) return REAL is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns 0.0 on error condition
begin
-- Check validity of argument
if ( ( X < 0 ) and ( Y /= 0.0 ) ) then
assert FALSE
report "X < 0 and Y /= 0.0 in X**Y"
severity ERROR;
return 0.0;
end if;
if ( ( X = 0 ) and ( Y <= 0.0 ) ) then
assert FALSE
report "X = 0 and Y <= 0.0 in X**Y"
severity ERROR;
return 0.0;
end if;
-- Get value for special cases
if ( X = 0 and Y > 0.0 ) then
return 0.0;
end if;
if ( X = 1 ) then
return 1.0;
end if;
if ( Y = 0.0 and X /= 0 ) then
return 1.0;
end if;
if ( Y = 1.0) then
return (REAL(X));
end if;
-- Get value for general case
return EXP (Y * LOG (REAL(X)));
end "**";
function "**" (X : in REAL; Y : in REAL) return REAL is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns 0.0 on error condition
begin
-- Check validity of argument
if ( ( X < 0.0 ) and ( Y /= 0.0 ) ) then
assert FALSE
report "X < 0.0 and Y /= 0.0 in X**Y"
severity ERROR;
return 0.0;
end if;
if ( ( X = 0.0 ) and ( Y <= 0.0 ) ) then
assert FALSE
report "X = 0.0 and Y <= 0.0 in X**Y"
severity ERROR;
return 0.0;
end if;
-- Get value for special cases
if ( X = 0.0 and Y > 0.0 ) then
return 0.0;
end if;
if ( X = 1.0 ) then
return 1.0;
end if;
if ( Y = 0.0 and X /= 0.0 ) then
return 1.0;
end if;
if ( Y = 1.0) then
return (X);
end if;
-- Get value for general case
return EXP (Y * LOG (X));
end "**";
function EXP (X : in REAL ) return REAL is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) This function computes the exponential using the following
-- series:
-- exp(x) = 1 + x + x**2/2! + x**3/3! + ... ; |x| < 1.0
-- and reduces argument X to take advantage of exp(x+y) =
-- exp(x)*exp(y)
--
-- b) This implementation limits X to be less than LOG(REAL'HIGH)
-- to avoid overflow. Returns REAL'HIGH when X reaches that
-- limit
--
constant EPS : REAL := BASE_EPS*BASE_EPS*BASE_EPS;-- Precision criteria
variable RECIPROCAL: BOOLEAN := X < 0.0;-- Check sign of argument
variable XLOCAL : REAL := ABS(X); -- Use positive value
variable OLDVAL: REAL ;
variable COUNT: INTEGER ;
variable NEWVAL: REAL ;
variable LAST_TERM: REAL ;
variable FACTOR : REAL := 1.0;
begin
-- Compute value for special cases
if X = 0.0 then
return 1.0;
end if;
if XLOCAL = 1.0 then
if RECIPROCAL then
return MATH_1_OVER_E;
else
return MATH_E;
end if;
end if;
if XLOCAL = 2.0 then
if RECIPROCAL then
return 1.0/MATH_E_P2;
else
return MATH_E_P2;
end if;
end if;
if XLOCAL = 10.0 then
if RECIPROCAL then
return 1.0/MATH_E_P10;
else
return MATH_E_P10;
end if;
end if;
if XLOCAL > LOG(REAL'HIGH) then
if RECIPROCAL then
return 0.0;
else
assert FALSE
report "X > LOG(REAL'HIGH) in EXP(X)"
severity NOTE;
return REAL'HIGH;
end if;
end if;
-- Reduce argument to ABS(X) < 1.0
while XLOCAL > 10.0 loop
XLOCAL := XLOCAL - 10.0;
FACTOR := FACTOR*MATH_E_P10;
end loop;
while XLOCAL > 1.0 loop
XLOCAL := XLOCAL - 1.0;
FACTOR := FACTOR*MATH_E;
end loop;
-- Compute value for case 0 < XLOCAL < 1
OLDVAL := 1.0;
LAST_TERM := XLOCAL;
NEWVAL:= OLDVAL + LAST_TERM;
COUNT := 2;
-- Check for relative and absolute errors and max count
while ( ( (ABS((NEWVAL - OLDVAL)/NEWVAL) > EPS) OR
(ABS(NEWVAL - OLDVAL) > EPS) ) AND
(COUNT < MAX_COUNT ) ) loop
OLDVAL := NEWVAL;
LAST_TERM := LAST_TERM*(XLOCAL / (REAL(COUNT)));
NEWVAL := OLDVAL + LAST_TERM;
COUNT := COUNT + 1;
end loop;
-- Compute final value using exp(x+y) = exp(x)*exp(y)
NEWVAL := NEWVAL*FACTOR;
if RECIPROCAL then
NEWVAL := 1.0/NEWVAL;
end if;
return NEWVAL;
end EXP;
--
-- Auxiliary Functions to Compute LOG
--
function ILOGB(X: in REAL) return INTEGER IS
-- Description:
-- Returns n such that -1 <= ABS(X)/2^n < 2
-- Notes:
-- None
variable N: INTEGER := 0;
variable Y: REAL := ABS(X);
begin
if(Y = 1.0 or Y = 0.0) then
return 0;
end if;
if( Y > 1.0) then
while Y >= 2.0 loop
Y := Y/2.0;
N := N+1;
end loop;
return N;
end if;
-- O < Y < 1
while Y < 1.0 loop
Y := Y*2.0;
N := N -1;
end loop;
return N;
end ILOGB;
function LDEXP(X: in REAL; N: in INTEGER) RETURN REAL IS
-- Description:
-- Returns X*2^n
-- Notes:
-- None
begin
return X*(2.0 ** N);
end LDEXP;
function LOG (X : in REAL ) return REAL IS
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
--
-- Notes:
-- a) Returns REAL'LOW on error
--
-- Copyright (c) 1992 Regents of the University of California.
-- All rights reserved.
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
-- 3. All advertising materials mentioning features or use of this
-- software must display the following acknowledgement:
-- This product includes software developed by the University of
-- California, Berkeley and its contributors.
-- 4. Neither the name of the University nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS''
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR
-- CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
-- EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
-- PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
-- PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
-- OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
-- USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
-- DAMAGE.
--
-- NOTE: This VHDL version was generated using the C version of the
-- original function by the IEEE VHDL Mathematical Package
-- Working Group (CS/JT)
constant N: INTEGER := 128;
-- Table of log(Fj) = logF_head[j] + logF_tail[j], for Fj = 1+j/128.
-- Used for generation of extend precision logarithms.
-- The constant 35184372088832 is 2^45, so the divide is exact.
-- It ensures correct reading of logF_head, even for inaccurate
-- decimal-to-binary conversion routines. (Everybody gets the
-- right answer for INTEGERs less than 2^53.)
-- Values for LOG(F) were generated using error < 10^-57 absolute
-- with the bc -l package.
type REAL_VECTOR is array (NATURAL range <>) of REAL;
constant A1:REAL := 0.08333333333333178827;
constant A2:REAL := 0.01250000000377174923;
constant A3:REAL := 0.002232139987919447809;
constant A4:REAL := 0.0004348877777076145742;
constant LOGF_HEAD: REAL_VECTOR(0 TO N) := (
0.0,
0.007782140442060381246,
0.015504186535963526694,
0.023167059281547608406,
0.030771658666765233647,
0.038318864302141264488,
0.045809536031242714670,
0.053244514518837604555,
0.060624621816486978786,
0.067950661908525944454,
0.075223421237524235039,
0.082443669210988446138,
0.089612158689760690322,
0.096729626458454731618,
0.103796793681567578460,
0.110814366340264314203,
0.117783035656430001836,
0.124703478501032805070,
0.131576357788617315236,
0.138402322859292326029,
0.145182009844575077295,
0.151916042025732167530,
0.158605030176659056451,
0.165249572895390883786,
0.171850256926518341060,
0.178407657472689606947,
0.184922338493834104156,
0.191394852999565046047,
0.197825743329758552135,
0.204215541428766300668,
0.210564769107350002741,
0.216873938300523150246,
0.223143551314024080056,
0.229374101064877322642,
0.235566071312860003672,
0.241719936886966024758,
0.247836163904594286577,
0.253915209980732470285,
0.259957524436686071567,
0.265963548496984003577,
0.271933715484010463114,
0.277868451003087102435,
0.283768173130738432519,
0.289633292582948342896,
0.295464212893421063199,
0.301261330578199704177,
0.307025035294827830512,
0.312755710004239517729,
0.318453731118097493890,
0.324119468654316733591,
0.329753286372579168528,
0.335355541920762334484,
0.340926586970454081892,
0.346466767346100823488,
0.351976423156884266063,
0.357455888922231679316,
0.362905493689140712376,
0.368325561158599157352,
0.373716409793814818840,
0.379078352934811846353,
0.384411698910298582632,
0.389716751140440464951,
0.394993808240542421117,
0.400243164127459749579,
0.405465108107819105498,
0.410659924985338875558,
0.415827895143593195825,
0.420969294644237379543,
0.426084395310681429691,
0.431173464818130014464,
0.436236766774527495726,
0.441274560805140936281,
0.446287102628048160113,
0.451274644139630254358,
0.456237433481874177232,
0.461175715122408291790,
0.466089729924533457960,
0.470979715219073113985,
0.475845904869856894947,
0.480688529345570714212,
0.485507815781602403149,
0.490303988045525329653,
0.495077266798034543171,
0.499827869556611403822,
0.504556010751912253908,
0.509261901790523552335,
0.513945751101346104405,
0.518607764208354637958,
0.523248143765158602036,
0.527867089620485785417,
0.532464798869114019908,
0.537041465897345915436,
0.541597282432121573947,
0.546132437597407260909,
0.550647117952394182793,
0.555141507540611200965,
0.559615787935399566777,
0.564070138285387656651,
0.568504735352689749561,
0.572919753562018740922,
0.577315365035246941260,
0.581691739635061821900,
0.586049045003164792433,
0.590387446602107957005,
0.594707107746216934174,
0.599008189645246602594,
0.603290851438941899687,
0.607555250224322662688,
0.611801541106615331955,
0.616029877215623855590,
0.620240409751204424537,
0.624433288012369303032,
0.628608659422752680256,
0.632766669570628437213,
0.636907462236194987781,
0.641031179420679109171,
0.645137961373620782978,
0.649227946625615004450,
0.653301272011958644725,
0.657358072709030238911,
0.661398482245203922502,
0.665422632544505177065,
0.669430653942981734871,
0.673422675212350441142,
0.677398823590920073911,
0.681359224807238206267,
0.685304003098281100392,
0.689233281238557538017,
0.693147180560117703862);
constant LOGF_TAIL: REAL_VECTOR(0 TO N) := (
0.0,
-0.00000000000000543229938420049,
0.00000000000000172745674997061,
-0.00000000000001323017818229233,
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variable M, J:INTEGER;
variable F1, F2, G, Q, U, U2, V: REAL;
variable ZERO: REAL := 0.0;--Made variable so no constant folding occurs
variable ONE: REAL := 1.0; --Made variable so no constant folding occurs
-- double logb(), ldexp();
variable U1:REAL;
begin
-- Check validity of argument
if ( X <= 0.0 ) then
assert FALSE
report "X <= 0.0 in LOG(X)"
severity ERROR;
return(REAL'LOW);
end if;
-- Compute value for special cases
if ( X = 1.0 ) then
return 0.0;
end if;
if ( X = MATH_E ) then
return 1.0;
end if;
-- Argument reduction: 1 <= g < 2; x/2^m = g;
-- y = F*(1 + f/F) for |f| <= 2^-8
M := ILOGB(X);
G := LDEXP(X, -M);
J := INTEGER(REAL(N)*(G-1.0)); -- C code adds 0.5 for rounding
F1 := (1.0/REAL(N)) * REAL(J) + 1.0; --F1*128 is an INTEGER in [128,512]
F2 := G - F1;
-- Approximate expansion for log(1+f2/F1) ~= u + q
G := 1.0/(2.0*F1+F2);
U := 2.0*F2*G;
V := U*U;
Q := U*V*(A1 + V*(A2 + V*(A3 + V*A4)));
-- Case 1: u1 = u rounded to 2^-43 absolute. Since u < 2^-8,
-- u1 has at most 35 bits, and F1*u1 is exact, as F1 has < 8 bits.
-- It also adds exactly to |m*log2_hi + log_F_head[j] | < 750.
--
if ( J /= 0 or M /= 0) then
U1 := U + 513.0;
U1 := U1 - 513.0;
-- Case 2: |1-x| < 1/256. The m- and j- dependent terms are zero
-- u1 = u to 24 bits.
--
else
U1 := U;
--TRUNC(U1); --In c this is u1 = (double) (float) (u1)
end if;
U2 := (2.0*(F2 - F1*U1) - U1*F2) * G;
-- u1 + u2 = 2f/(2F+f) to extra precision.
-- log(x) = log(2^m*F1*(1+f2/F1)) =
-- (m*log2_hi+LOGF_HEAD(j)+u1) + (m*log2_lo+LOGF_TAIL(j)+q);
-- (exact) + (tiny)
U1 := U1 + REAL(M)*LOGF_HEAD(N) + LOGF_HEAD(J); -- Exact
U2 := (U2 + LOGF_TAIL(J)) + Q; -- Tiny
U2 := U2 + LOGF_TAIL(N)*REAL(M);
return (U1 + U2);
end LOG;
function LOG2 (X: in REAL) return REAL is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns REAL'LOW on error
begin
-- Check validity of arguments
if ( X <= 0.0 ) then
assert FALSE
report "X <= 0.0 in LOG2(X)"
severity ERROR;
return(REAL'LOW);
end if;
-- Compute value for special cases
if ( X = 1.0 ) then
return 0.0;
end if;
if ( X = 2.0 ) then
return 1.0;
end if;
-- Compute value for general case
return ( MATH_LOG2_OF_E*LOG(X) );
end LOG2;
function LOG10 (X: in REAL) return REAL is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns REAL'LOW on error
begin
-- Check validity of arguments
if ( X <= 0.0 ) then
assert FALSE
report "X <= 0.0 in LOG10(X)"
severity ERROR;
return(REAL'LOW);
end if;
-- Compute value for special cases
if ( X = 1.0 ) then
return 0.0;
end if;
if ( X = 10.0 ) then
return 1.0;
end if;
-- Compute value for general case
return ( MATH_LOG10_OF_E*LOG(X) );
end LOG10;
function LOG (X: in REAL; BASE: in REAL) return REAL is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns REAL'LOW on error
begin
-- Check validity of arguments
if ( X <= 0.0 ) then
assert FALSE
report "X <= 0.0 in LOG(X, BASE)"
severity ERROR;
return(REAL'LOW);
end if;
if ( BASE <= 0.0 or BASE = 1.0 ) then
assert FALSE
report "BASE <= 0.0 or BASE = 1.0 in LOG(X, BASE)"
severity ERROR;
return(REAL'LOW);
end if;
-- Compute value for special cases
if ( X = 1.0 ) then
return 0.0;
end if;
if ( X = BASE ) then
return 1.0;
end if;
-- Compute value for general case
return ( LOG(X)/LOG(BASE));
end LOG;
function SIN (X : in REAL ) return REAL is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) SIN(-X) = -SIN(X)
-- b) SIN(X) = X if ABS(X) < EPS
-- c) SIN(X) = X - X**3/3! if EPS < ABS(X) < BASE_EPS
-- d) SIN(MATH_PI_OVER_2 - X) = COS(X)
-- e) COS(X) = 1.0 - 0.5*X**2 if ABS(X) < EPS
-- f) COS(X) = 1.0 - 0.5*X**2 + (X**4)/4! if
-- EPS< ABS(X) <BASE_EPS
constant EPS : REAL := BASE_EPS*BASE_EPS; -- Convergence criteria
variable N : INTEGER;
variable NEGATIVE : BOOLEAN := X < 0.0;
variable XLOCAL : REAL := ABS(X) ;
variable VALUE: REAL;
variable TEMP : REAL;
begin
-- Make XLOCAL < MATH_2_PI
if XLOCAL > MATH_2_PI then
TEMP := FLOOR(XLOCAL/MATH_2_PI);
XLOCAL := XLOCAL - TEMP*MATH_2_PI;
end if;
if XLOCAL < 0.0 then
assert FALSE
report "XLOCAL <= 0.0 after reduction in SIN(X)"
severity ERROR;
XLOCAL := -XLOCAL;
end if;
-- Compute value for special cases
if XLOCAL = 0.0 or XLOCAL = MATH_2_PI or XLOCAL = MATH_PI then
return 0.0;
end if;
if XLOCAL = MATH_PI_OVER_2 then
if NEGATIVE then
return -1.0;
else
return 1.0;
end if;
end if;
if XLOCAL = MATH_3_PI_OVER_2 then
if NEGATIVE then
return 1.0;
else
return -1.0;
end if;
end if;
if XLOCAL < EPS then
if NEGATIVE then
return -XLOCAL;
else
return XLOCAL;
end if;
else
if XLOCAL < BASE_EPS then
TEMP := XLOCAL - (XLOCAL*XLOCAL*XLOCAL)/6.0;
if NEGATIVE then
return -TEMP;
else
return TEMP;
end if;
end if;
end if;
TEMP := MATH_PI - XLOCAL;
if ABS(TEMP) < EPS then
if NEGATIVE then
return -TEMP;
else
return TEMP;
end if;
else
if ABS(TEMP) < BASE_EPS then
TEMP := TEMP - (TEMP*TEMP*TEMP)/6.0;
if NEGATIVE then
return -TEMP;
else
return TEMP;
end if;
end if;
end if;
TEMP := MATH_2_PI - XLOCAL;
if ABS(TEMP) < EPS then
if NEGATIVE then
return TEMP;
else
return -TEMP;
end if;
else
if ABS(TEMP) < BASE_EPS then
TEMP := TEMP - (TEMP*TEMP*TEMP)/6.0;
if NEGATIVE then
return TEMP;
else
return -TEMP;
end if;
end if;
end if;
TEMP := ABS(MATH_PI_OVER_2 - XLOCAL);
if TEMP < EPS then
TEMP := 1.0 - TEMP*TEMP*0.5;
if NEGATIVE then
return -TEMP;
else
return TEMP;
end if;
else
if TEMP < BASE_EPS then
TEMP := 1.0 -TEMP*TEMP*0.5 + TEMP*TEMP*TEMP*TEMP/24.0;
if NEGATIVE then
return -TEMP;
else
return TEMP;
end if;
end if;
end if;
TEMP := ABS(MATH_3_PI_OVER_2 - XLOCAL);
if TEMP < EPS then
TEMP := 1.0 - TEMP*TEMP*0.5;
if NEGATIVE then
return TEMP;
else
return -TEMP;
end if;
else
if TEMP < BASE_EPS then
TEMP := 1.0 -TEMP*TEMP*0.5 + TEMP*TEMP*TEMP*TEMP/24.0;
if NEGATIVE then
return TEMP;
else
return -TEMP;
end if;
end if;
end if;
-- Compute value for general cases
if ((XLOCAL < MATH_PI_OVER_2 ) and (XLOCAL > 0.0)) then
VALUE:= CORDIC( KC, 0.0, x, 27, ROTATION)(1);
end if;
N := INTEGER ( FLOOR(XLOCAL/MATH_PI_OVER_2));
case QUADRANT( N mod 4) is
when 0 =>
VALUE := CORDIC( KC, 0.0, XLOCAL, 27, ROTATION)(1);
when 1 =>
VALUE := CORDIC( KC, 0.0, XLOCAL - MATH_PI_OVER_2, 27,
ROTATION)(0);
when 2 =>
VALUE := -CORDIC( KC, 0.0, XLOCAL - MATH_PI, 27, ROTATION)(1);
when 3 =>
VALUE := -CORDIC( KC, 0.0, XLOCAL - MATH_3_PI_OVER_2, 27,
ROTATION)(0);
end case;
if NEGATIVE then
return -VALUE;
else
return VALUE;
end if;
end SIN;
function COS (X : in REAL) return REAL is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) COS(-X) = COS(X)
-- b) COS(X) = SIN(MATH_PI_OVER_2 - X)
-- c) COS(MATH_PI + X) = -COS(X)
-- d) COS(X) = 1.0 - X*X/2.0 if ABS(X) < EPS
-- e) COS(X) = 1.0 - 0.5*X**2 + (X**4)/4! if
-- EPS< ABS(X) <BASE_EPS
--
constant EPS : REAL := BASE_EPS*BASE_EPS;
variable XLOCAL : REAL := ABS(X);
variable VALUE: REAL;
variable TEMP : REAL;
begin
-- Make XLOCAL < MATH_2_PI
if XLOCAL > MATH_2_PI then
TEMP := FLOOR(XLOCAL/MATH_2_PI);
XLOCAL := XLOCAL - TEMP*MATH_2_PI;
end if;
if XLOCAL < 0.0 then
assert FALSE
report "XLOCAL <= 0.0 after reduction in COS(X)"
severity ERROR;
XLOCAL := -XLOCAL;
end if;
-- Compute value for special cases
if XLOCAL = 0.0 or XLOCAL = MATH_2_PI then
return 1.0;
end if;
if XLOCAL = MATH_PI then
return -1.0;
end if;
if XLOCAL = MATH_PI_OVER_2 or XLOCAL = MATH_3_PI_OVER_2 then
return 0.0;
end if;
TEMP := ABS(XLOCAL);
if ( TEMP < EPS) then
return (1.0 - 0.5*TEMP*TEMP);
else
if (TEMP < BASE_EPS) then
return (1.0 -0.5*TEMP*TEMP + TEMP*TEMP*TEMP*TEMP/24.0);
end if;
end if;
TEMP := ABS(XLOCAL -MATH_2_PI);
if ( TEMP < EPS) then
return (1.0 - 0.5*TEMP*TEMP);
else
if (TEMP < BASE_EPS) then
return (1.0 -0.5*TEMP*TEMP + TEMP*TEMP*TEMP*TEMP/24.0);
end if;
end if;
TEMP := ABS (XLOCAL - MATH_PI);
if TEMP < EPS then
return (-1.0 + 0.5*TEMP*TEMP);
else
if (TEMP < BASE_EPS) then
return (-1.0 +0.5*TEMP*TEMP - TEMP*TEMP*TEMP*TEMP/24.0);
end if;
end if;
-- Compute value for general cases
return SIN(MATH_PI_OVER_2 - XLOCAL);
end COS;
function TAN (X : in REAL) return REAL is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) TAN(0.0) = 0.0
-- b) TAN(-X) = -TAN(X)
-- c) Returns REAL'LOW on error if X < 0.0
-- d) Returns REAL'HIGH on error if X > 0.0
variable NEGATIVE : BOOLEAN := X < 0.0;
variable XLOCAL : REAL := ABS(X) ;
variable VALUE: REAL;
variable TEMP : REAL;
begin
-- Make 0.0 <= XLOCAL <= MATH_2_PI
if XLOCAL > MATH_2_PI then
TEMP := FLOOR(XLOCAL/MATH_2_PI);
XLOCAL := XLOCAL - TEMP*MATH_2_PI;
end if;
if XLOCAL < 0.0 then
assert FALSE
report "XLOCAL <= 0.0 after reduction in TAN(X)"
severity ERROR;
XLOCAL := -XLOCAL;
end if;
-- Check validity of argument
if XLOCAL = MATH_PI_OVER_2 then
assert FALSE
report "X is a multiple of MATH_PI_OVER_2 in TAN(X)"
severity ERROR;
if NEGATIVE then
return(REAL'LOW);
else
return(REAL'HIGH);
end if;
end if;
if XLOCAL = MATH_3_PI_OVER_2 then
assert FALSE
report "X is a multiple of MATH_3_PI_OVER_2 in TAN(X)"
severity ERROR;
if NEGATIVE then
return(REAL'HIGH);
else
return(REAL'LOW);
end if;
end if;
-- Compute value for special cases
if XLOCAL = 0.0 or XLOCAL = MATH_PI then
return 0.0;
end if;
-- Compute value for general cases
VALUE := SIN(XLOCAL)/COS(XLOCAL);
if NEGATIVE then
return -VALUE;
else
return VALUE;
end if;
end TAN;
function ARCSIN (X : in REAL ) return REAL is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) ARCSIN(-X) = -ARCSIN(X)
-- b) Returns X on error
variable NEGATIVE : BOOLEAN := X < 0.0;
variable XLOCAL : REAL := ABS(X);
variable VALUE : REAL;
begin
-- Check validity of arguments
if XLOCAL > 1.0 then
assert FALSE
report "ABS(X) > 1.0 in ARCSIN(X)"
severity ERROR;
return X;
end if;
-- Compute value for special cases
if XLOCAL = 0.0 then
return 0.0;
elsif XLOCAL = 1.0 then
if NEGATIVE then
return -MATH_PI_OVER_2;
else
return MATH_PI_OVER_2;
end if;
end if;
-- Compute value for general cases
if XLOCAL < 0.9 then
VALUE := ARCTAN(XLOCAL/(SQRT(1.0 - XLOCAL*XLOCAL)));
else
VALUE := MATH_PI_OVER_2 - ARCTAN(SQRT(1.0 - XLOCAL*XLOCAL)/XLOCAL);
end if;
if NEGATIVE then
VALUE := -VALUE;
end if;
return VALUE;
end ARCSIN;
function ARCCOS (X : in REAL) return REAL is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) ARCCOS(-X) = MATH_PI - ARCCOS(X)
-- b) Returns X on error
variable NEGATIVE : BOOLEAN := X < 0.0;
variable XLOCAL : REAL := ABS(X);
variable VALUE : REAL;
begin
-- Check validity of argument
if XLOCAL > 1.0 then
assert FALSE
report "ABS(X) > 1.0 in ARCCOS(X)"
severity ERROR;
return X;
end if;
-- Compute value for special cases
if X = 1.0 then
return 0.0;
elsif X = 0.0 then
return MATH_PI_OVER_2;
elsif X = -1.0 then
return MATH_PI;
end if;
-- Compute value for general cases
if XLOCAL > 0.9 then
VALUE := ARCTAN(SQRT(1.0 - XLOCAL*XLOCAL)/XLOCAL);
else
VALUE := MATH_PI_OVER_2 - ARCTAN(XLOCAL/SQRT(1.0 - XLOCAL*XLOCAL));
end if;
if NEGATIVE then
VALUE := MATH_PI - VALUE;
end if;
return VALUE;
end ARCCOS;
function ARCTAN (Y : in REAL) return REAL is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) ARCTAN(-Y) = -ARCTAN(Y)
-- b) ARCTAN(Y) = -ARCTAN(1.0/Y) + MATH_PI_OVER_2 for |Y| > 1.0
-- c) ARCTAN(Y) = Y for |Y| < EPS
constant EPS : REAL := BASE_EPS*BASE_EPS*BASE_EPS;
variable NEGATIVE : BOOLEAN := Y < 0.0;
variable RECIPROCAL : BOOLEAN;
variable YLOCAL : REAL := ABS(Y);
variable VALUE : REAL;
begin
-- Make argument |Y| <=1.0
if YLOCAL > 1.0 then
YLOCAL := 1.0/YLOCAL;
RECIPROCAL := TRUE;
else
RECIPROCAL := FALSE;
end if;
-- Compute value for special cases
if YLOCAL = 0.0 then
if RECIPROCAL then
if NEGATIVE then
return (-MATH_PI_OVER_2);
else
return (MATH_PI_OVER_2);
end if;
else
return 0.0;
end if;
end if;
if YLOCAL < EPS then
if NEGATIVE then
if RECIPROCAL then
return (-MATH_PI_OVER_2 + YLOCAL);
else
return -YLOCAL;
end if;
else
if RECIPROCAL then
return (MATH_PI_OVER_2 - YLOCAL);
else
return YLOCAL;
end if;
end if;
end if;
-- Compute value for general cases
VALUE := CORDIC( 1.0, YLOCAL, 0.0, 27, VECTORING )(2);
if RECIPROCAL then
VALUE := MATH_PI_OVER_2 - VALUE;
end if;
if NEGATIVE then
VALUE := -VALUE;
end if;
return VALUE;
end ARCTAN;
function ARCTAN (Y : in REAL; X : in REAL) return REAL is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns 0.0 on error
variable YLOCAL : REAL;
variable VALUE : REAL;
begin
-- Check validity of arguments
if (Y = 0.0 and X = 0.0 ) then
assert FALSE report
"ARCTAN(0.0, 0.0) is undetermined"
severity ERROR;
return 0.0;
end if;
-- Compute value for special cases
if Y = 0.0 then
if X > 0.0 then
return 0.0;
else
return MATH_PI;
end if;
end if;
if X = 0.0 then
if Y > 0.0 then
return MATH_PI_OVER_2;
else
return -MATH_PI_OVER_2;
end if;
end if;
-- Compute value for general cases
YLOCAL := ABS(Y/X);
VALUE := ARCTAN(YLOCAL);
if X < 0.0 then
VALUE := MATH_PI - VALUE;
end if;
if Y < 0.0 then
VALUE := -VALUE;
end if;
return VALUE;
end ARCTAN;
function SINH (X : in REAL) return REAL is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns (EXP(X) - EXP(-X))/2.0
-- b) SINH(-X) = SINH(X)
variable NEGATIVE : BOOLEAN := X < 0.0;
variable XLOCAL : REAL := ABS(X);
variable TEMP : REAL;
variable VALUE : REAL;
begin
-- Compute value for special cases
if XLOCAL = 0.0 then
return 0.0;
end if;
-- Compute value for general cases
TEMP := EXP(XLOCAL);
VALUE := (TEMP - 1.0/TEMP)*0.5;
if NEGATIVE then
VALUE := -VALUE;
end if;
return VALUE;
end SINH;
function COSH (X : in REAL) return REAL is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns (EXP(X) + EXP(-X))/2.0
-- b) COSH(-X) = COSH(X)
variable XLOCAL : REAL := ABS(X);
variable TEMP : REAL;
variable VALUE : REAL;
begin
-- Compute value for special cases
if XLOCAL = 0.0 then
return 1.0;
end if;
-- Compute value for general cases
TEMP := EXP(XLOCAL);
VALUE := (TEMP + 1.0/TEMP)*0.5;
return VALUE;
end COSH;
function TANH (X : in REAL) return REAL is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns (EXP(X) - EXP(-X))/(EXP(X) + EXP(-X))
-- b) TANH(-X) = -TANH(X)
variable NEGATIVE : BOOLEAN := X < 0.0;
variable XLOCAL : REAL := ABS(X);
variable TEMP : REAL;
variable VALUE : REAL;
begin
-- Compute value for special cases
if XLOCAL = 0.0 then
return 0.0;
end if;
-- Compute value for general cases
TEMP := EXP(XLOCAL);
VALUE := (TEMP - 1.0/TEMP)/(TEMP + 1.0/TEMP);
if NEGATIVE then
return -VALUE;
else
return VALUE;
end if;
end TANH;
function ARCSINH (X : in REAL) return REAL is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns LOG( X + SQRT( X*X + 1.0))
begin
-- Compute value for special cases
if X = 0.0 then
return 0.0;
end if;
-- Compute value for general cases
return ( LOG( X + SQRT( X*X + 1.0)) );
end ARCSINH;
function ARCCOSH (X : in REAL) return REAL is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns LOG( X + SQRT( X*X - 1.0)); X >= 1.0
-- b) Returns X on error
begin
-- Check validity of arguments
if X < 1.0 then
assert FALSE
report "X < 1.0 in ARCCOSH(X)"
severity ERROR;
return X;
end if;
-- Compute value for special cases
if X = 1.0 then
return 0.0;
end if;
-- Compute value for general cases
return ( LOG( X + SQRT( X*X - 1.0)));
end ARCCOSH;
function ARCTANH (X : in REAL) return REAL is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns (LOG( (1.0 + X)/(1.0 - X)))/2.0 ; | X | < 1.0
-- b) Returns X on error
begin
-- Check validity of arguments
if ABS(X) >= 1.0 then
assert FALSE
report "ABS(X) >= 1.0 in ARCTANH(X)"
severity ERROR;
return X;
end if;
-- Compute value for special cases
if X = 0.0 then
return 0.0;
end if;
-- Compute value for general cases
return( 0.5*LOG( (1.0+X)/(1.0-X) ) );
end ARCTANH;
end MATH_REAL;
| gpl-2.0 | 725f9888a80ecd0c1a8ec6a12e4a7487 | 0.467914 | 4.340474 | false | false | false | false |
emogenet/ghdl | testsuite/gna/issue241/arr.vhdl | 2 | 339 | entity arr is
end;
architecture behav of arr is
type arr_type is array (natural range <>) of natural;
constant a : arr_type (2 downto 1) := (1 | 2 => 3);
constant b : boolean := a (1) = a (2);
begin
process
begin
case true is
when b => null;
when false => null;
end case;
wait;
end process;
end behav;
| gpl-2.0 | 4d07e1db4494c1d46d2914c864c7c7c5 | 0.59587 | 3.39 | false | false | false | false |
pmh92/Proyecto-OFDM | test/txt_util.vhd | 1 | 14,987 | -------------------------------------------------------------------
--! @file
--! @author Stephan Doll
--! @brief Package for VHDL text output, from Stephan Doll's VHDL verification course.
-------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use std.textio.all;
--! @brief Allows for text output in simulation
package txt_util is
--! prints a message to the screen
procedure print(text: string);
--! @brief prints the message when active
--
-- useful for debug switches
procedure print(active: boolean; text: string);
--! converts std_logic into a character
function chr(sl: std_logic) return character;
--! converts std_logic into a string (1 to 1)
function str(sl: std_logic) return string;
--! converts std_logic_vector into a string (binary base)
function str(slv: std_logic_vector) return string;
--! converts boolean into a string
function str(b: boolean) return string;
--! @brief converts an integer into a single character
--
-- (can also be used for hex conversion and other bases)
function chr(int: integer) return character;
--! converts integer into string using specified base
function str(int: integer; base: integer) return string;
--! converts integer to string, using base 10
function str(int: integer) return string;
--! convert std_logic_vector into a string in hex format
function hstr(slv: std_logic_vector) return string;
-- functions to manipulate strings
-----------------------------------
--! convert a character to upper case
function to_upper(c: character) return character;
--! convert a character to lower case
function to_lower(c: character) return character;
--! convert a string to upper case
function to_upper(s: string) return string;
--! convert a string to lower case
function to_lower(s: string) return string;
-- functions to convert strings into other formats
--------------------------------------------------
--! converts a character into std_logic
function to_std_logic(c: character) return std_logic;
--! converts a string into std_logic_vector
function to_std_logic_vector(s: string) return std_logic_vector;
-- file I/O
-----------
--! read variable length string from input file
procedure str_read(file in_file: TEXT;
res_string: out string);
--! print string to a file and start new line
procedure print(file out_file: TEXT;
new_string: in string);
--! print character to a file and start new line
procedure print(file out_file: TEXT;
char: in character);
end txt_util;
package body txt_util is
--! prints text to the screen
procedure print(text: string) is
variable msg_line: line;
begin
write(msg_line, text);
writeline(output, msg_line);
end print;
--! prints text to the screen when active
procedure print(active: boolean; text: string) is
begin
if active then
print(text);
end if;
end print;
--! converts std_logic into a character
function chr(sl: std_logic) return character is
variable c: character;
begin
case sl is
when 'U' => c:= 'U';
when 'X' => c:= 'X';
when '0' => c:= '0';
when '1' => c:= '1';
when 'Z' => c:= 'Z';
when 'W' => c:= 'W';
when 'L' => c:= 'L';
when 'H' => c:= 'H';
when '-' => c:= '-';
end case;
return c;
end chr;
--! converts std_logic into a string (1 to 1)
function str(sl: std_logic) return string is
variable s: string(1 to 1);
begin
s(1) := chr(sl);
return s;
end str;
--! @brief converts std_logic_vector into a string (binary base)
--
-- @detailed (this also takes care of the fact that the range of
-- a string is natural while a std_logic_vector may
-- have an integer range)
function str(slv: std_logic_vector) return string is
variable result : string (1 to slv'length);
variable r : integer;
begin
r := 1;
for i in slv'range loop
result(r) := chr(slv(i));
r := r + 1;
end loop;
return result;
end str;
--! @brief converts boolean into a string
function str(b: boolean) return string is
begin
if b then
return "true";
else
return "false";
end if;
end str;
--! @brief converts an integer into a character
--
-- @detailed for 0 to 9 the obvious mapping is used, higher
-- values are mapped to the characters A-Z
-- (this is usefull for systems with base > 10)
-- (adapted from Steve Vogwell's posting in comp.lang.vhdl)
function chr(int: integer) return character is
variable c: character;
begin
case int is
when 0 => c := '0';
when 1 => c := '1';
when 2 => c := '2';
when 3 => c := '3';
when 4 => c := '4';
when 5 => c := '5';
when 6 => c := '6';
when 7 => c := '7';
when 8 => c := '8';
when 9 => c := '9';
when 10 => c := 'A';
when 11 => c := 'B';
when 12 => c := 'C';
when 13 => c := 'D';
when 14 => c := 'E';
when 15 => c := 'F';
when 16 => c := 'G';
when 17 => c := 'H';
when 18 => c := 'I';
when 19 => c := 'J';
when 20 => c := 'K';
when 21 => c := 'L';
when 22 => c := 'M';
when 23 => c := 'N';
when 24 => c := 'O';
when 25 => c := 'P';
when 26 => c := 'Q';
when 27 => c := 'R';
when 28 => c := 'S';
when 29 => c := 'T';
when 30 => c := 'U';
when 31 => c := 'V';
when 32 => c := 'W';
when 33 => c := 'X';
when 34 => c := 'Y';
when 35 => c := 'Z';
when others => c := '?';
end case;
return c;
end chr;
--! @brief convert integer to string using specified base
--
-- @detailed (adapted from Steve Vogwell's posting in comp.lang.vhdl)
function str(int: integer; base: integer) return string is
variable temp: string(1 to 10);
variable num: integer;
variable abs_int: integer;
variable len: integer := 1;
variable power: integer := 1;
begin
-- bug fix for negative numbers
abs_int := abs(int);
num := abs_int;
while num >= base loop -- Determine how many
len := len + 1; -- characters required
num := num / base; -- to represent the
end loop ; -- number.
for i in len downto 1 loop -- Convert the number to
temp(i) := chr(abs_int/power mod base); -- a string starting
power := power * base; -- with the right hand
end loop ; -- side.
-- return result and add sign if required
if int < 0 then
return '-'& temp(1 to len);
else
return temp(1 to len);
end if;
end str;
--! convert integer to string, using base 10
function str(int: integer) return string is
begin
return str(int, 10) ;
end str;
--! converts a std_logic_vector into a hex string.
function hstr(slv: std_logic_vector) return string is
variable hexlen: integer;
variable longslv : std_logic_vector(67 downto 0) := (others => '0');
variable hex : string(1 to 16);
variable fourbit : std_logic_vector(3 downto 0);
begin
hexlen := (slv'left+1)/4;
if (slv'left+1) mod 4 /= 0 then
hexlen := hexlen + 1;
end if;
longslv(slv'left downto 0) := slv;
for i in (hexlen -1) downto 0 loop
fourbit := longslv(((i*4)+3) downto (i*4));
case fourbit is
when "0000" => hex(hexlen -I) := '0';
when "0001" => hex(hexlen -I) := '1';
when "0010" => hex(hexlen -I) := '2';
when "0011" => hex(hexlen -I) := '3';
when "0100" => hex(hexlen -I) := '4';
when "0101" => hex(hexlen -I) := '5';
when "0110" => hex(hexlen -I) := '6';
when "0111" => hex(hexlen -I) := '7';
when "1000" => hex(hexlen -I) := '8';
when "1001" => hex(hexlen -I) := '9';
when "1010" => hex(hexlen -I) := 'A';
when "1011" => hex(hexlen -I) := 'B';
when "1100" => hex(hexlen -I) := 'C';
when "1101" => hex(hexlen -I) := 'D';
when "1110" => hex(hexlen -I) := 'E';
when "1111" => hex(hexlen -I) := 'F';
when "ZZZZ" => hex(hexlen -I) := 'z';
when "UUUU" => hex(hexlen -I) := 'u';
when "XXXX" => hex(hexlen -I) := 'x';
when others => hex(hexlen -I) := '?';
end case;
end loop;
return hex(1 to hexlen);
end hstr;
-- functions to manipulate strings
-----------------------------------
--! convert a character to upper case
function to_upper(c: character) return character is
variable u: character;
begin
case c is
when 'a' => u := 'A';
when 'b' => u := 'B';
when 'c' => u := 'C';
when 'd' => u := 'D';
when 'e' => u := 'E';
when 'f' => u := 'F';
when 'g' => u := 'G';
when 'h' => u := 'H';
when 'i' => u := 'I';
when 'j' => u := 'J';
when 'k' => u := 'K';
when 'l' => u := 'L';
when 'm' => u := 'M';
when 'n' => u := 'N';
when 'o' => u := 'O';
when 'p' => u := 'P';
when 'q' => u := 'Q';
when 'r' => u := 'R';
when 's' => u := 'S';
when 't' => u := 'T';
when 'u' => u := 'U';
when 'v' => u := 'V';
when 'w' => u := 'W';
when 'x' => u := 'X';
when 'y' => u := 'Y';
when 'z' => u := 'Z';
when others => u := c;
end case;
return u;
end to_upper;
--! convert a character to lower case
function to_lower(c: character) return character is
variable l: character;
begin
case c is
when 'A' => l := 'a';
when 'B' => l := 'b';
when 'C' => l := 'c';
when 'D' => l := 'd';
when 'E' => l := 'e';
when 'F' => l := 'f';
when 'G' => l := 'g';
when 'H' => l := 'h';
when 'I' => l := 'i';
when 'J' => l := 'j';
when 'K' => l := 'k';
when 'L' => l := 'l';
when 'M' => l := 'm';
when 'N' => l := 'n';
when 'O' => l := 'o';
when 'P' => l := 'p';
when 'Q' => l := 'q';
when 'R' => l := 'r';
when 'S' => l := 's';
when 'T' => l := 't';
when 'U' => l := 'u';
when 'V' => l := 'v';
when 'W' => l := 'w';
when 'X' => l := 'x';
when 'Y' => l := 'y';
when 'Z' => l := 'z';
when others => l := c;
end case;
return l;
end to_lower;
--! convert a string to upper case
function to_upper(s: string) return string is
variable uppercase: string (s'range);
begin
for i in s'range loop
uppercase(i):= to_upper(s(i));
end loop;
return uppercase;
end to_upper;
--! convert a string to lower case
function to_lower(s: string) return string is
variable lowercase: string (s'range);
begin
for i in s'range loop
lowercase(i):= to_lower(s(i));
end loop;
return lowercase;
end to_lower;
-- functions to convert strings into other types
--! converts a character into a std_logic
function to_std_logic(c: character) return std_logic is
variable sl: std_logic;
begin
case c is
when 'U' =>
sl := 'U';
when 'X' =>
sl := 'X';
when '0' =>
sl := '0';
when '1' =>
sl := '1';
when 'Z' =>
sl := 'Z';
when 'W' =>
sl := 'W';
when 'L' =>
sl := 'L';
when 'H' =>
sl := 'H';
when '-' =>
sl := '-';
when others =>
sl := 'X';
end case;
return sl;
end to_std_logic;
--! converts a string into std_logic_vector
function to_std_logic_vector(s: string) return std_logic_vector is
variable slv: std_logic_vector(s'high-s'low downto 0);
variable k: integer;
begin
k := s'high-s'low;
for i in s'range loop
slv(k) := to_std_logic(s(i));
k := k - 1;
end loop;
return slv;
end to_std_logic_vector;
----------------
-- file I/O --
----------------
--! read variable length string from input file
procedure str_read(file in_file: TEXT;
res_string: out string) is
variable l: line;
variable c: character;
variable is_string: boolean;
begin
readline(in_file, l);
-- clear the contents of the result string
for i in res_string'range loop
res_string(i) := ' ';
end loop;
-- read all characters of the line, up to the length
-- of the results string
for i in res_string'range loop
read(l, c, is_string);
res_string(i) := c;
if not is_string then -- found end of line
exit;
end if;
end loop;
end str_read;
--! print string to a file
procedure print(file out_file: TEXT;
new_string: in string) is
variable l: line;
begin
write(l, new_string);
writeline(out_file, l);
end print;
--! print character to a file and start new line
procedure print(file out_file: TEXT;
char: in character) is
variable l: line;
begin
write(l, char);
writeline(out_file, l);
end print;
--! @brief appends contents of a string to a file until line feed occurs
--
-- @detailed (LF is considered to be the end of the string)
procedure str_write(file out_file: TEXT;
new_string: in string) is
begin
for i in new_string'range loop
print(out_file, new_string(i));
if new_string(i) = LF then -- end of string
exit;
end if;
end loop;
end str_write;
end txt_util;
| gpl-2.0 | 08eb4d5b4c9f8decd8798c242f16d906 | 0.472476 | 3.856665 | false | false | false | false |
rafa-jfet/OFM | ARCHIVOS VHDL/gray2angleinc.vhd | 1 | 3,389 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 01:15:11 05/08/2015
-- Design Name:
-- Module Name: gray2angleinc - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity gray2angleinc is
Port ( clk : in STD_LOGIC;
reset : in STD_LOGIC;
bit_in : in STD_LOGIC_VECTOR (0 downto 0);
ok_bit_in : in STD_LOGIC;
modulation : in STD_LOGIC_VECTOR (2 downto 0);
anginc_out : out STD_LOGIC_VECTOR (2 downto 0);
ok_anginc_out : out STD_LOGIC);
end gray2angleinc;
architecture Behavioral of gray2angleinc is
type estado is ( bit_0,
bit_1,
bit_2,
salida_valida );
signal estado_actual : estado;
signal estado_nuevo : estado;
signal anginc_int, p_anginc_int : STD_LOGIC_VECTOR ( 2 downto 0 );
begin
anginc_out <= anginc_int;
comb : process ( estado_actual, bit_in, ok_bit_in, anginc_int, modulation)
begin
p_anginc_int <= anginc_int;
ok_anginc_out <= '0';
estado_nuevo <= estado_actual;
case estado_actual is
when bit_0 =>
if ok_bit_in = '1' then
p_anginc_int(2) <= bit_in(0);
if modulation = "100" then
-- gray a decimal multiplicado por 4 (desplazamiento bits izq *2)
-- p_anginc_int(2) <= bit_in; --(gray a decimal) *2
p_anginc_int ( 1 downto 0 ) <= "00";
estado_nuevo <= salida_valida;
else
-- p_anginc_int(0) <= bit_in;
estado_nuevo <= bit_1;
end if;
end if;
when bit_1 =>
if ok_bit_in = '1' then
p_anginc_int(1) <= anginc_int(2) xor bit_in(0);
if modulation = "010" then
-- gray a decimal multiplicado por 2 (desplazamiento bits izq)
---- p_anginc_int(2) <= anginc_int(0);
-- p_anginc_int(1) <= anginc_int(0) xor bit_in;
p_anginc_int(0) <= '0';
estado_nuevo <= salida_valida;
else
-- p_anginc_int(1) <= bit_in;
estado_nuevo <= bit_2;
end if;
end if;
when bit_2 =>
p_anginc_int(0) <= anginc_int(1) xor bit_in(0);
if ok_bit_in = '1' then
-- gray a decimal
-- p_anginc_int(2) <= bit_in; --bin2 = gray2
-- p_anginc_int(1) <= anginc_int(1) xor bit_in; --bin1 = gray1 xor bin2(=gray2)
-- p_anginc_int(0) <= anginc_int(0) xor anginc_int(1) xor bit_in; --bin0 = gray0 xor bin1(=gray1 xor bin2)
estado_nuevo <= salida_valida;
end if;
when salida_valida =>
ok_anginc_out <= '1';
estado_nuevo <= bit_0;
end case;
end process;
sinc : process ( reset, clk )
begin
if ( reset = '1' ) then
anginc_int <= "000";
estado_actual <= bit_0;
elsif ( rising_edge(clk) ) then
anginc_int <= p_anginc_int;
estado_actual <= estado_nuevo;
end if;
end process;
end Behavioral;
| gpl-3.0 | f297d4d0f7921d984b9f18fe5b98ae4a | 0.562998 | 2.967601 | false | false | false | false |
hacklabmikkeli/rough-boy | amplifier.vhdl | 2 | 2,539 | --
-- Knobs Galore - a free phase distortion synthesizer
-- Copyright (C) 2015 Ilmo Euro
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
library ieee;
library work;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
use work.common.all;
entity amplifier is
port (EN: in std_logic
;CLK_EVEN: in std_logic
;CLK_ODD: in std_logic
;GAIN: in ctl_signal
;AUDIO_IN: in voice_signal
;AUDIO_OUT: out voice_signal
)
;
end entity;
architecture amplifier_impl of amplifier is
-- AUDIO_OUT =
-- (GAIN * AUDIO_IN) / CTL_MAX +
-- ((CTL_MAX - GAIN) * BIAS) / CTL_MAX
constant bias: voice_signal := ('1', others => '0');
signal s1_GX_N: voice_signal := (others => '0');
signal s1_N_Gb_N: voice_signal := (others => '0');
signal s2_audio_out_buf: voice_signal := (others => '0');
signal s3_audio_out_buf: voice_signal := (others => '0');
begin
process (CLK_EVEN)
variable GX: unsigned(ctl_bits + voice_bits - 1 downto 0);
variable N_Gb: unsigned(ctl_bits + voice_bits - 1 downto 0);
begin
if EN = '1' and rising_edge(CLK_EVEN) then
GX := GAIN * AUDIO_IN;
s1_GX_N <= GX(ctl_bits + voice_bits - 1 downto ctl_bits);
N_Gb := (not GAIN) * bias;
s1_N_Gb_N <= N_Gb(ctl_bits + voice_bits - 1 downto ctl_bits);
end if;
end process;
process (CLK_ODD)
begin
if EN = '1' and rising_edge(CLK_ODD) then
s2_audio_out_buf <= s1_GX_N + s1_N_Gb_N;
end if;
end process;
process (CLK_EVEN)
begin
if EN = '1' and rising_edge(CLK_ODD) then
s3_audio_out_buf <= s2_audio_out_buf;
end if;
end process;
AUDIO_OUT <= s3_audio_out_buf;
end architecture;
| gpl-3.0 | 25a9e56309edf0f93968e9b303e3e96a | 0.587633 | 3.389853 | false | false | false | false |
emogenet/ghdl | testsuite/gna/perf02/top.vhd | 3 | 307,015 | library ieee;
use ieee.std_logic_1164.all;
entity top is
port (
clock : in std_logic;
reset : in std_logic;
start : in std_logic;
stdin_rdy : out std_logic;
stdin_ack : in std_logic;
stdout_data : out std_logic_vector(31 downto 0);
stdout_rdy : out std_logic;
stdout_ack : in std_logic;
stdin_data : in std_logic_vector(31 downto 0)
);
end top;
architecture augh of top is
-- Declaration of components
component sub_147 is
port (
output : out std_logic_vector(63 downto 0);
sign : in std_logic;
ge : out std_logic;
in_a : in std_logic_vector(63 downto 0);
in_b : in std_logic_vector(63 downto 0)
);
end component;
component qq4_code4_table is
port (
clk : in std_logic;
ra0_data : out std_logic_vector(31 downto 0);
ra0_addr : in std_logic_vector(3 downto 0)
);
end component;
component qq6_code6_table is
port (
clk : in std_logic;
ra0_data : out std_logic_vector(31 downto 0);
ra0_addr : in std_logic_vector(5 downto 0)
);
end component;
component wl_code_table is
port (
clk : in std_logic;
ra0_data : out std_logic_vector(31 downto 0);
ra0_addr : in std_logic_vector(3 downto 0)
);
end component;
component ilb_table is
port (
clk : in std_logic;
ra0_data : out std_logic_vector(31 downto 0);
ra0_addr : in std_logic_vector(4 downto 0)
);
end component;
component decis_levl is
port (
clk : in std_logic;
ra0_data : out std_logic_vector(31 downto 0);
ra0_addr : in std_logic_vector(4 downto 0)
);
end component;
component quant26bt_pos is
port (
clk : in std_logic;
ra0_data : out std_logic_vector(31 downto 0);
ra0_addr : in std_logic_vector(4 downto 0)
);
end component;
component quant26bt_neg is
port (
clk : in std_logic;
ra0_data : out std_logic_vector(31 downto 0);
ra0_addr : in std_logic_vector(4 downto 0)
);
end component;
component qq2_code2_table is
port (
clk : in std_logic;
ra0_data : out std_logic_vector(31 downto 0);
ra0_addr : in std_logic_vector(1 downto 0)
);
end component;
component wh_code_table is
port (
clk : in std_logic;
ra0_data : out std_logic_vector(31 downto 0);
ra0_addr : in std_logic_vector(1 downto 0)
);
end component;
component cmp_694 is
port (
in1 : in std_logic_vector(31 downto 0);
in0 : in std_logic_vector(31 downto 0);
eq : out std_logic
);
end component;
component cmp_700 is
port (
in1 : in std_logic_vector(31 downto 0);
in0 : in std_logic_vector(31 downto 0);
eq : out std_logic
);
end component;
component sub_144 is
port (
output : out std_logic_vector(63 downto 0);
le : out std_logic;
sign : in std_logic;
ge : out std_logic;
in_a : in std_logic_vector(63 downto 0);
in_b : in std_logic_vector(63 downto 0)
);
end component;
component mul_145 is
port (
output : out std_logic_vector(63 downto 0);
in_a : in std_logic_vector(63 downto 0);
in_b : in std_logic_vector(31 downto 0)
);
end component;
component mul_146 is
port (
output : out std_logic_vector(63 downto 0);
in_a : in std_logic_vector(63 downto 0);
in_b : in std_logic_vector(31 downto 0)
);
end component;
component sub_143 is
port (
output : out std_logic_vector(63 downto 0);
lt : out std_logic;
le : out std_logic;
sign : in std_logic;
gt : out std_logic;
in_a : in std_logic_vector(63 downto 0);
in_b : in std_logic_vector(63 downto 0)
);
end component;
component add_142 is
port (
output : out std_logic_vector(63 downto 0);
in_a : in std_logic_vector(63 downto 0);
in_b : in std_logic_vector(63 downto 0)
);
end component;
component test_data is
port (
clk : in std_logic;
ra0_data : out std_logic_vector(31 downto 0);
wa0_addr : in std_logic_vector(6 downto 0);
wa0_en : in std_logic;
ra0_addr : in std_logic_vector(6 downto 0);
wa0_data : in std_logic_vector(31 downto 0);
ra1_data : out std_logic_vector(31 downto 0);
ra1_addr : in std_logic_vector(6 downto 0)
);
end component;
component shr_141 is
port (
output : out std_logic_vector(31 downto 0);
input : in std_logic_vector(31 downto 0);
shift : in std_logic_vector(5 downto 0);
padding : in std_logic
);
end component;
component compressed is
port (
clk : in std_logic;
ra0_data : out std_logic_vector(31 downto 0);
wa0_addr : in std_logic_vector(6 downto 0);
wa0_en : in std_logic;
ra0_addr : in std_logic_vector(6 downto 0);
wa0_data : in std_logic_vector(31 downto 0)
);
end component;
component result is
port (
clk : in std_logic;
ra0_data : out std_logic_vector(31 downto 0);
wa0_addr : in std_logic_vector(6 downto 0);
wa0_en : in std_logic;
ra0_addr : in std_logic_vector(6 downto 0);
wa0_data : in std_logic_vector(31 downto 0)
);
end component;
component cmp_662 is
port (
in1 : in std_logic_vector(31 downto 0);
in0 : in std_logic_vector(31 downto 0);
eq : out std_logic
);
end component;
component cmp_673 is
port (
in1 : in std_logic_vector(31 downto 0);
in0 : in std_logic_vector(31 downto 0);
eq : out std_logic
);
end component;
component mul_148 is
port (
output : out std_logic_vector(63 downto 0);
in_a : in std_logic_vector(32 downto 0);
in_b : in std_logic_vector(31 downto 0)
);
end component;
component mul_149 is
port (
output : out std_logic_vector(63 downto 0);
in_a : in std_logic_vector(32 downto 0);
in_b : in std_logic_vector(31 downto 0)
);
end component;
component add_153 is
port (
output : out std_logic_vector(63 downto 0);
in_a : in std_logic_vector(63 downto 0);
in_b : in std_logic_vector(63 downto 0)
);
end component;
component add_154 is
port (
output : out std_logic_vector(63 downto 0);
in_a : in std_logic_vector(63 downto 0);
in_b : in std_logic_vector(63 downto 0)
);
end component;
component add_155 is
port (
output : out std_logic_vector(63 downto 0);
in_a : in std_logic_vector(63 downto 0);
in_b : in std_logic_vector(63 downto 0)
);
end component;
component mul_156 is
port (
output : out std_logic_vector(63 downto 0);
in_a : in std_logic_vector(32 downto 0);
in_b : in std_logic_vector(31 downto 0)
);
end component;
component add_159 is
port (
output : out std_logic_vector(31 downto 0);
in_a : in std_logic_vector(31 downto 0);
in_b : in std_logic_vector(31 downto 0)
);
end component;
component sub_160 is
port (
output : out std_logic_vector(63 downto 0);
lt : out std_logic;
le : out std_logic;
sign : in std_logic;
ge : out std_logic;
in_a : in std_logic_vector(63 downto 0);
in_b : in std_logic_vector(63 downto 0)
);
end component;
component mul_161 is
port (
output : out std_logic_vector(63 downto 0);
in_a : in std_logic_vector(32 downto 0);
in_b : in std_logic_vector(31 downto 0)
);
end component;
component fsm_163 is
port (
clock : in std_logic;
reset : in std_logic;
out91 : out std_logic;
out92 : out std_logic;
out93 : out std_logic;
in7 : in std_logic;
out94 : out std_logic;
out95 : out std_logic;
out98 : out std_logic;
out100 : out std_logic;
out101 : out std_logic;
out102 : out std_logic;
out104 : out std_logic;
out105 : out std_logic;
out106 : out std_logic;
out107 : out std_logic;
out108 : out std_logic;
out109 : out std_logic;
out111 : out std_logic;
out114 : out std_logic;
out116 : out std_logic;
out118 : out std_logic;
out119 : out std_logic;
out120 : out std_logic;
out128 : out std_logic;
out130 : out std_logic;
out131 : out std_logic;
out132 : out std_logic;
out137 : out std_logic;
in8 : in std_logic;
out152 : out std_logic;
out155 : out std_logic;
out156 : out std_logic;
out31 : out std_logic;
in2 : in std_logic;
out28 : out std_logic;
out29 : out std_logic;
out30 : out std_logic;
out26 : out std_logic;
out27 : out std_logic;
out24 : out std_logic;
out25 : out std_logic;
out77 : out std_logic;
out79 : out std_logic;
out80 : out std_logic;
out82 : out std_logic;
out34 : out std_logic;
out35 : out std_logic;
out36 : out std_logic;
out32 : out std_logic;
out33 : out std_logic;
out40 : out std_logic;
out41 : out std_logic;
out88 : out std_logic;
out89 : out std_logic;
out21 : out std_logic;
out22 : out std_logic;
out23 : out std_logic;
out73 : out std_logic;
out76 : out std_logic;
in6 : in std_logic;
out70 : out std_logic;
out12 : out std_logic;
out13 : out std_logic;
out14 : out std_logic;
out17 : out std_logic;
out18 : out std_logic;
out19 : out std_logic;
out20 : out std_logic;
out9 : out std_logic;
out11 : out std_logic;
out8 : out std_logic;
out2 : out std_logic;
out4 : out std_logic;
out5 : out std_logic;
in1 : in std_logic;
out6 : out std_logic;
out7 : out std_logic;
out0 : out std_logic;
out1 : out std_logic;
out37 : out std_logic;
out38 : out std_logic;
out39 : out std_logic;
out1222 : out std_logic;
out1223 : out std_logic;
out1224 : out std_logic;
out1225 : out std_logic;
out1226 : out std_logic;
out1228 : out std_logic;
out1230 : out std_logic;
in0 : in std_logic;
out67 : out std_logic;
out68 : out std_logic;
out65 : out std_logic;
out66 : out std_logic;
in5 : in std_logic;
out62 : out std_logic;
out58 : out std_logic;
out56 : out std_logic;
in4 : in std_logic;
out57 : out std_logic;
out54 : out std_logic;
out55 : out std_logic;
out51 : out std_logic;
out52 : out std_logic;
out53 : out std_logic;
in3 : in std_logic;
out46 : out std_logic;
out47 : out std_logic;
out48 : out std_logic;
out49 : out std_logic;
out50 : out std_logic;
out42 : out std_logic;
out43 : out std_logic;
out44 : out std_logic;
out45 : out std_logic;
in9 : in std_logic;
in10 : in std_logic;
out171 : out std_logic;
in11 : in std_logic;
out191 : out std_logic;
out207 : out std_logic;
out208 : out std_logic;
out209 : out std_logic;
out212 : out std_logic;
out213 : out std_logic;
out216 : out std_logic;
out220 : out std_logic;
out221 : out std_logic;
out223 : out std_logic;
out224 : out std_logic;
out226 : out std_logic;
out227 : out std_logic;
out228 : out std_logic;
out229 : out std_logic;
out230 : out std_logic;
out233 : out std_logic;
out235 : out std_logic;
out236 : out std_logic;
out237 : out std_logic;
out238 : out std_logic;
out239 : out std_logic;
out241 : out std_logic;
out250 : out std_logic;
out258 : out std_logic;
out259 : out std_logic;
out261 : out std_logic;
out270 : out std_logic;
out276 : out std_logic;
out277 : out std_logic;
out283 : out std_logic;
out285 : out std_logic;
out287 : out std_logic;
out290 : out std_logic;
out291 : out std_logic;
out293 : out std_logic;
out301 : out std_logic;
out303 : out std_logic;
out304 : out std_logic;
out315 : out std_logic;
out319 : out std_logic;
out321 : out std_logic;
out330 : out std_logic;
out335 : out std_logic;
out338 : out std_logic;
out341 : out std_logic;
out342 : out std_logic;
out344 : out std_logic;
out347 : out std_logic;
out351 : out std_logic;
out354 : out std_logic;
out355 : out std_logic;
out356 : out std_logic;
out357 : out std_logic;
out358 : out std_logic;
out360 : out std_logic;
out361 : out std_logic;
out362 : out std_logic;
out365 : out std_logic;
out367 : out std_logic;
out368 : out std_logic;
out370 : out std_logic;
out375 : out std_logic;
out376 : out std_logic;
out378 : out std_logic;
out381 : out std_logic;
out382 : out std_logic;
out386 : out std_logic;
out387 : out std_logic;
out388 : out std_logic;
out390 : out std_logic;
out392 : out std_logic;
out393 : out std_logic;
out394 : out std_logic;
out397 : out std_logic;
out403 : out std_logic;
out404 : out std_logic;
out408 : out std_logic;
out409 : out std_logic;
out410 : out std_logic;
out412 : out std_logic;
out416 : out std_logic;
out417 : out std_logic;
out418 : out std_logic;
out419 : out std_logic;
out420 : out std_logic;
out421 : out std_logic;
out424 : out std_logic;
out425 : out std_logic;
out430 : out std_logic;
out431 : out std_logic;
out434 : out std_logic;
out436 : out std_logic;
out438 : out std_logic;
out439 : out std_logic;
out440 : out std_logic;
out441 : out std_logic;
out442 : out std_logic;
out443 : out std_logic;
out444 : out std_logic;
out445 : out std_logic;
out446 : out std_logic;
out447 : out std_logic;
out448 : out std_logic;
out450 : out std_logic;
out451 : out std_logic;
out454 : out std_logic;
out457 : out std_logic;
out460 : out std_logic;
out463 : out std_logic;
out465 : out std_logic;
out466 : out std_logic;
out472 : out std_logic;
out473 : out std_logic;
out475 : out std_logic;
out476 : out std_logic;
out479 : out std_logic;
out480 : out std_logic;
out481 : out std_logic;
out482 : out std_logic;
out484 : out std_logic;
out485 : out std_logic;
out489 : out std_logic;
out491 : out std_logic;
out494 : out std_logic;
out497 : out std_logic;
out500 : out std_logic;
out503 : out std_logic;
out504 : out std_logic;
out505 : out std_logic;
out508 : out std_logic;
out509 : out std_logic;
out513 : out std_logic;
out514 : out std_logic;
out516 : out std_logic;
out521 : out std_logic;
out523 : out std_logic;
out524 : out std_logic;
out525 : out std_logic;
out530 : out std_logic;
out532 : out std_logic;
out533 : out std_logic;
out535 : out std_logic;
out536 : out std_logic;
out539 : out std_logic;
out541 : out std_logic;
out543 : out std_logic;
out545 : out std_logic;
out547 : out std_logic;
out549 : out std_logic;
out550 : out std_logic;
out552 : out std_logic;
out558 : out std_logic;
out559 : out std_logic;
out563 : out std_logic;
out566 : out std_logic;
out572 : out std_logic;
out573 : out std_logic;
out576 : out std_logic;
out577 : out std_logic;
out581 : out std_logic;
out582 : out std_logic;
out590 : out std_logic;
out591 : out std_logic;
out592 : out std_logic;
out593 : out std_logic;
out595 : out std_logic;
out611 : out std_logic;
out619 : out std_logic;
out638 : out std_logic;
out643 : out std_logic;
out644 : out std_logic;
out645 : out std_logic;
out646 : out std_logic;
out648 : out std_logic;
out650 : out std_logic;
out652 : out std_logic;
out657 : out std_logic;
out659 : out std_logic;
out662 : out std_logic;
out677 : out std_logic;
out678 : out std_logic;
out679 : out std_logic;
out680 : out std_logic;
out682 : out std_logic;
out686 : out std_logic;
out692 : out std_logic;
out1218 : out std_logic;
out1219 : out std_logic;
out1220 : out std_logic;
out1221 : out std_logic;
out695 : out std_logic;
out697 : out std_logic;
out706 : out std_logic;
out719 : out std_logic;
out729 : out std_logic;
out744 : out std_logic;
out746 : out std_logic;
out748 : out std_logic;
out833 : out std_logic;
out834 : out std_logic;
out836 : out std_logic;
out837 : out std_logic;
out839 : out std_logic;
out840 : out std_logic;
out841 : out std_logic;
out844 : out std_logic;
out845 : out std_logic;
out846 : out std_logic;
out848 : out std_logic;
out850 : out std_logic;
out852 : out std_logic;
out854 : out std_logic;
out856 : out std_logic;
out858 : out std_logic;
out860 : out std_logic;
out863 : out std_logic;
out865 : out std_logic;
out866 : out std_logic;
out873 : out std_logic;
out877 : out std_logic;
out888 : out std_logic;
out891 : out std_logic;
out893 : out std_logic;
out895 : out std_logic;
out898 : out std_logic;
out900 : out std_logic;
out902 : out std_logic;
out903 : out std_logic;
out904 : out std_logic;
out905 : out std_logic;
out906 : out std_logic;
out907 : out std_logic;
out908 : out std_logic;
out909 : out std_logic;
out910 : out std_logic;
out912 : out std_logic;
out913 : out std_logic;
out914 : out std_logic;
out915 : out std_logic;
out917 : out std_logic;
out920 : out std_logic;
out921 : out std_logic;
out924 : out std_logic;
out934 : out std_logic;
out935 : out std_logic;
out937 : out std_logic;
out938 : out std_logic;
out940 : out std_logic;
out943 : out std_logic;
out945 : out std_logic;
out957 : out std_logic;
out958 : out std_logic;
out962 : out std_logic;
out968 : out std_logic;
out972 : out std_logic;
out973 : out std_logic;
out974 : out std_logic;
out975 : out std_logic;
out976 : out std_logic;
out980 : out std_logic;
out986 : out std_logic;
out988 : out std_logic;
out989 : out std_logic;
out990 : out std_logic;
out1004 : out std_logic;
out1008 : out std_logic;
out999 : out std_logic;
out1000 : out std_logic;
out1002 : out std_logic;
out1003 : out std_logic;
out1050 : out std_logic;
out1052 : out std_logic;
out1053 : out std_logic;
out1055 : out std_logic;
out1056 : out std_logic;
out1057 : out std_logic;
out1059 : out std_logic;
out1015 : out std_logic;
out1025 : out std_logic;
out1026 : out std_logic;
out1038 : out std_logic;
out1039 : out std_logic;
out1042 : out std_logic;
out1043 : out std_logic;
out1046 : out std_logic;
out1048 : out std_logic;
out1061 : out std_logic;
out1063 : out std_logic;
out1064 : out std_logic;
out1067 : out std_logic;
out1068 : out std_logic;
out1069 : out std_logic;
out1071 : out std_logic;
out1073 : out std_logic;
out1076 : out std_logic;
out1077 : out std_logic;
out1078 : out std_logic;
out1080 : out std_logic;
out1081 : out std_logic;
out1083 : out std_logic;
out1085 : out std_logic;
out1087 : out std_logic;
out1089 : out std_logic;
out1092 : out std_logic;
out1096 : out std_logic;
out1100 : out std_logic;
out1103 : out std_logic;
out1115 : out std_logic;
out1122 : out std_logic;
out1123 : out std_logic;
out1127 : out std_logic;
out1130 : out std_logic;
out1133 : out std_logic;
out1138 : out std_logic;
out1139 : out std_logic;
out1140 : out std_logic;
out1141 : out std_logic;
out1142 : out std_logic;
out1143 : out std_logic;
out1144 : out std_logic;
out1145 : out std_logic;
out1146 : out std_logic;
out1147 : out std_logic;
out1148 : out std_logic;
out1149 : out std_logic;
out1150 : out std_logic;
out1151 : out std_logic;
out1152 : out std_logic;
out1153 : out std_logic;
out1154 : out std_logic;
out1155 : out std_logic;
out1156 : out std_logic;
out1157 : out std_logic;
out1158 : out std_logic;
out1159 : out std_logic;
out1160 : out std_logic;
out1161 : out std_logic;
out1162 : out std_logic;
out1163 : out std_logic;
out1164 : out std_logic;
out1165 : out std_logic;
out1166 : out std_logic;
out1167 : out std_logic;
out1168 : out std_logic;
out1169 : out std_logic;
out1170 : out std_logic;
out1171 : out std_logic;
out1172 : out std_logic;
out1173 : out std_logic;
out1174 : out std_logic;
out1175 : out std_logic;
out1176 : out std_logic;
out1177 : out std_logic;
out1178 : out std_logic;
out1179 : out std_logic;
out1180 : out std_logic;
out1181 : out std_logic;
out1182 : out std_logic;
out1183 : out std_logic;
out1184 : out std_logic;
out1185 : out std_logic;
out1186 : out std_logic;
out1187 : out std_logic;
out1188 : out std_logic;
out1189 : out std_logic;
out1190 : out std_logic;
out1191 : out std_logic;
out1192 : out std_logic;
out1193 : out std_logic;
out1194 : out std_logic;
out1195 : out std_logic;
out1196 : out std_logic;
out1197 : out std_logic;
out1198 : out std_logic;
out1199 : out std_logic;
out1200 : out std_logic;
out1201 : out std_logic;
out1202 : out std_logic;
out1203 : out std_logic;
out1204 : out std_logic;
out1205 : out std_logic;
out1206 : out std_logic;
out1207 : out std_logic;
out1208 : out std_logic;
out1209 : out std_logic;
out1210 : out std_logic;
out1211 : out std_logic;
out1212 : out std_logic;
out1213 : out std_logic;
out1214 : out std_logic;
out1215 : out std_logic;
out1216 : out std_logic;
out1217 : out std_logic
);
end component;
-- Declaration of signals
signal sig_clock : std_logic;
signal sig_reset : std_logic;
signal augh_test_23 : std_logic;
signal augh_test_24 : std_logic;
signal augh_test_78 : std_logic;
signal augh_test_92 : std_logic;
signal sig_start : std_logic;
signal augh_test_113 : std_logic;
signal augh_test_124 : std_logic;
signal augh_test_135 : std_logic;
signal augh_test_137 : std_logic;
signal augh_test_138 : std_logic;
signal sig_782 : std_logic;
signal sig_783 : std_logic;
signal sig_784 : std_logic;
signal sig_785 : std_logic;
signal sig_786 : std_logic;
signal sig_787 : std_logic;
signal sig_788 : std_logic;
signal sig_789 : std_logic;
signal sig_790 : std_logic;
signal sig_791 : std_logic;
signal sig_792 : std_logic;
signal sig_793 : std_logic;
signal sig_794 : std_logic;
signal sig_795 : std_logic;
signal sig_796 : std_logic;
signal sig_797 : std_logic;
signal sig_798 : std_logic;
signal sig_799 : std_logic;
signal sig_800 : std_logic;
signal sig_801 : std_logic;
signal sig_802 : std_logic;
signal sig_803 : std_logic;
signal sig_804 : std_logic;
signal sig_805 : std_logic;
signal sig_806 : std_logic;
signal sig_807 : std_logic;
signal sig_808 : std_logic;
signal sig_809 : std_logic;
signal sig_810 : std_logic;
signal sig_811 : std_logic;
signal sig_812 : std_logic;
signal sig_813 : std_logic;
signal sig_814 : std_logic;
signal sig_815 : std_logic;
signal sig_816 : std_logic;
signal sig_817 : std_logic;
signal sig_818 : std_logic;
signal sig_819 : std_logic;
signal sig_820 : std_logic;
signal sig_821 : std_logic;
signal sig_822 : std_logic;
signal sig_823 : std_logic;
signal sig_824 : std_logic;
signal sig_825 : std_logic;
signal sig_826 : std_logic;
signal sig_827 : std_logic;
signal sig_828 : std_logic;
signal sig_829 : std_logic;
signal sig_830 : std_logic;
signal sig_831 : std_logic;
signal sig_832 : std_logic;
signal sig_833 : std_logic;
signal sig_834 : std_logic;
signal sig_835 : std_logic;
signal sig_836 : std_logic;
signal sig_837 : std_logic;
signal sig_838 : std_logic;
signal sig_839 : std_logic;
signal sig_840 : std_logic;
signal sig_841 : std_logic;
signal sig_842 : std_logic;
signal sig_843 : std_logic;
signal sig_844 : std_logic;
signal sig_845 : std_logic;
signal sig_846 : std_logic;
signal sig_847 : std_logic;
signal sig_848 : std_logic;
signal sig_849 : std_logic;
signal sig_850 : std_logic;
signal sig_851 : std_logic;
signal sig_852 : std_logic;
signal sig_853 : std_logic;
signal sig_854 : std_logic;
signal sig_855 : std_logic;
signal sig_856 : std_logic;
signal sig_857 : std_logic;
signal sig_858 : std_logic;
signal sig_859 : std_logic;
signal sig_860 : std_logic;
signal sig_861 : std_logic;
signal sig_862 : std_logic;
signal sig_863 : std_logic;
signal sig_864 : std_logic;
signal sig_865 : std_logic;
signal sig_866 : std_logic;
signal sig_867 : std_logic;
signal sig_868 : std_logic;
signal sig_869 : std_logic;
signal sig_870 : std_logic;
signal sig_871 : std_logic;
signal sig_872 : std_logic;
signal sig_873 : std_logic;
signal sig_874 : std_logic;
signal sig_875 : std_logic;
signal sig_876 : std_logic;
signal sig_877 : std_logic;
signal sig_878 : std_logic;
signal sig_879 : std_logic;
signal sig_880 : std_logic;
signal sig_881 : std_logic;
signal sig_882 : std_logic;
signal sig_883 : std_logic;
signal sig_884 : std_logic;
signal sig_885 : std_logic;
signal sig_886 : std_logic;
signal sig_887 : std_logic;
signal sig_888 : std_logic;
signal sig_889 : std_logic;
signal sig_890 : std_logic;
signal sig_891 : std_logic;
signal sig_892 : std_logic;
signal sig_893 : std_logic;
signal sig_894 : std_logic;
signal sig_895 : std_logic;
signal sig_896 : std_logic;
signal sig_897 : std_logic;
signal sig_898 : std_logic;
signal sig_899 : std_logic;
signal sig_900 : std_logic;
signal sig_901 : std_logic;
signal sig_902 : std_logic;
signal sig_903 : std_logic;
signal sig_904 : std_logic;
signal sig_905 : std_logic;
signal sig_906 : std_logic;
signal sig_907 : std_logic;
signal sig_908 : std_logic;
signal sig_909 : std_logic;
signal sig_910 : std_logic;
signal sig_911 : std_logic;
signal sig_912 : std_logic;
signal sig_913 : std_logic;
signal sig_914 : std_logic;
signal sig_915 : std_logic;
signal sig_916 : std_logic;
signal sig_917 : std_logic;
signal sig_918 : std_logic;
signal sig_919 : std_logic;
signal sig_920 : std_logic;
signal sig_921 : std_logic;
signal sig_922 : std_logic;
signal sig_923 : std_logic;
signal sig_924 : std_logic;
signal sig_925 : std_logic;
signal sig_926 : std_logic;
signal sig_927 : std_logic;
signal sig_928 : std_logic;
signal sig_929 : std_logic;
signal sig_930 : std_logic;
signal sig_931 : std_logic;
signal sig_932 : std_logic;
signal sig_933 : std_logic;
signal sig_934 : std_logic;
signal sig_935 : std_logic;
signal sig_936 : std_logic;
signal sig_937 : std_logic;
signal sig_938 : std_logic;
signal sig_939 : std_logic;
signal sig_940 : std_logic;
signal sig_941 : std_logic;
signal sig_942 : std_logic;
signal sig_943 : std_logic;
signal sig_944 : std_logic;
signal sig_945 : std_logic;
signal sig_946 : std_logic;
signal sig_947 : std_logic;
signal sig_948 : std_logic;
signal sig_949 : std_logic;
signal sig_950 : std_logic;
signal sig_951 : std_logic;
signal sig_952 : std_logic;
signal sig_953 : std_logic;
signal sig_954 : std_logic;
signal sig_955 : std_logic;
signal sig_956 : std_logic;
signal sig_957 : std_logic;
signal sig_958 : std_logic;
signal sig_959 : std_logic;
signal sig_960 : std_logic;
signal sig_961 : std_logic;
signal sig_962 : std_logic;
signal sig_963 : std_logic;
signal sig_964 : std_logic;
signal sig_965 : std_logic;
signal sig_966 : std_logic;
signal sig_967 : std_logic;
signal sig_968 : std_logic;
signal sig_969 : std_logic;
signal sig_970 : std_logic;
signal sig_971 : std_logic;
signal sig_972 : std_logic;
signal sig_973 : std_logic;
signal sig_974 : std_logic;
signal sig_975 : std_logic;
signal sig_976 : std_logic;
signal sig_977 : std_logic;
signal sig_978 : std_logic;
signal sig_979 : std_logic;
signal sig_980 : std_logic;
signal sig_981 : std_logic;
signal sig_982 : std_logic;
signal sig_983 : std_logic;
signal sig_984 : std_logic;
signal sig_985 : std_logic;
signal sig_986 : std_logic;
signal sig_987 : std_logic;
signal sig_988 : std_logic;
signal sig_989 : std_logic;
signal sig_990 : std_logic;
signal sig_991 : std_logic;
signal sig_992 : std_logic;
signal sig_993 : std_logic;
signal sig_994 : std_logic;
signal sig_995 : std_logic;
signal sig_996 : std_logic;
signal sig_997 : std_logic;
signal sig_998 : std_logic;
signal sig_999 : std_logic;
signal sig_1000 : std_logic;
signal sig_1001 : std_logic;
signal sig_1002 : std_logic;
signal sig_1003 : std_logic;
signal sig_1004 : std_logic;
signal sig_1005 : std_logic;
signal sig_1006 : std_logic;
signal sig_1007 : std_logic;
signal sig_1008 : std_logic;
signal sig_1009 : std_logic;
signal sig_1010 : std_logic;
signal sig_1011 : std_logic;
signal sig_1012 : std_logic;
signal sig_1013 : std_logic;
signal sig_1014 : std_logic;
signal sig_1015 : std_logic;
signal sig_1016 : std_logic;
signal sig_1017 : std_logic;
signal sig_1018 : std_logic;
signal sig_1019 : std_logic;
signal sig_1020 : std_logic;
signal sig_1021 : std_logic;
signal sig_1022 : std_logic;
signal sig_1023 : std_logic;
signal sig_1024 : std_logic;
signal sig_1025 : std_logic;
signal sig_1026 : std_logic;
signal sig_1027 : std_logic;
signal sig_1028 : std_logic;
signal sig_1029 : std_logic;
signal sig_1030 : std_logic;
signal sig_1031 : std_logic;
signal sig_1032 : std_logic;
signal sig_1033 : std_logic;
signal sig_1034 : std_logic;
signal sig_1035 : std_logic;
signal sig_1036 : std_logic;
signal sig_1037 : std_logic;
signal sig_1038 : std_logic;
signal sig_1039 : std_logic;
signal sig_1040 : std_logic;
signal sig_1041 : std_logic;
signal sig_1042 : std_logic;
signal sig_1043 : std_logic;
signal sig_1044 : std_logic;
signal sig_1045 : std_logic;
signal sig_1046 : std_logic;
signal sig_1047 : std_logic;
signal sig_1048 : std_logic;
signal sig_1049 : std_logic;
signal sig_1050 : std_logic;
signal sig_1051 : std_logic;
signal sig_1052 : std_logic;
signal sig_1053 : std_logic;
signal sig_1054 : std_logic;
signal sig_1055 : std_logic;
signal sig_1056 : std_logic;
signal sig_1057 : std_logic;
signal sig_1058 : std_logic;
signal sig_1059 : std_logic;
signal sig_1060 : std_logic;
signal sig_1061 : std_logic;
signal sig_1062 : std_logic;
signal sig_1063 : std_logic;
signal sig_1064 : std_logic;
signal sig_1065 : std_logic;
signal sig_1066 : std_logic;
signal sig_1067 : std_logic;
signal sig_1068 : std_logic;
signal sig_1069 : std_logic;
signal sig_1070 : std_logic;
signal sig_1071 : std_logic;
signal sig_1072 : std_logic;
signal sig_1073 : std_logic;
signal sig_1074 : std_logic;
signal sig_1075 : std_logic;
signal sig_1076 : std_logic;
signal sig_1077 : std_logic;
signal sig_1078 : std_logic;
signal sig_1079 : std_logic;
signal sig_1080 : std_logic;
signal sig_1081 : std_logic;
signal sig_1082 : std_logic;
signal sig_1083 : std_logic;
signal sig_1084 : std_logic;
signal sig_1085 : std_logic;
signal sig_1086 : std_logic;
signal sig_1087 : std_logic;
signal sig_1088 : std_logic;
signal sig_1089 : std_logic;
signal sig_1090 : std_logic;
signal sig_1091 : std_logic;
signal sig_1092 : std_logic;
signal sig_1093 : std_logic;
signal sig_1094 : std_logic;
signal sig_1095 : std_logic;
signal sig_1096 : std_logic;
signal sig_1097 : std_logic;
signal sig_1098 : std_logic;
signal sig_1099 : std_logic;
signal sig_1100 : std_logic;
signal sig_1101 : std_logic;
signal sig_1102 : std_logic;
signal sig_1103 : std_logic;
signal sig_1104 : std_logic;
signal sig_1105 : std_logic;
signal sig_1106 : std_logic;
signal sig_1107 : std_logic;
signal sig_1108 : std_logic;
signal sig_1109 : std_logic;
signal sig_1110 : std_logic;
signal sig_1111 : std_logic;
signal sig_1112 : std_logic;
signal sig_1113 : std_logic;
signal sig_1114 : std_logic;
signal sig_1115 : std_logic;
signal sig_1116 : std_logic;
signal sig_1117 : std_logic;
signal sig_1118 : std_logic;
signal sig_1119 : std_logic;
signal sig_1120 : std_logic;
signal sig_1121 : std_logic;
signal sig_1122 : std_logic;
signal sig_1123 : std_logic;
signal sig_1124 : std_logic;
signal sig_1125 : std_logic;
signal sig_1126 : std_logic;
signal sig_1127 : std_logic;
signal sig_1128 : std_logic;
signal sig_1129 : std_logic;
signal sig_1130 : std_logic;
signal sig_1131 : std_logic;
signal sig_1132 : std_logic;
signal sig_1133 : std_logic;
signal sig_1134 : std_logic;
signal sig_1135 : std_logic;
signal sig_1136 : std_logic;
signal sig_1137 : std_logic;
signal sig_1138 : std_logic;
signal sig_1139 : std_logic;
signal sig_1140 : std_logic;
signal sig_1141 : std_logic;
signal sig_1142 : std_logic;
signal sig_1143 : std_logic;
signal sig_1144 : std_logic;
signal sig_1145 : std_logic;
signal sig_1146 : std_logic;
signal sig_1147 : std_logic;
signal sig_1148 : std_logic;
signal sig_1149 : std_logic;
signal sig_1150 : std_logic;
signal sig_1151 : std_logic;
signal sig_1152 : std_logic;
signal sig_1153 : std_logic;
signal sig_1154 : std_logic;
signal sig_1155 : std_logic;
signal sig_1156 : std_logic;
signal sig_1157 : std_logic;
signal sig_1158 : std_logic;
signal sig_1159 : std_logic;
signal sig_1160 : std_logic;
signal sig_1161 : std_logic;
signal sig_1162 : std_logic;
signal sig_1163 : std_logic;
signal sig_1164 : std_logic;
signal sig_1165 : std_logic;
signal sig_1166 : std_logic;
signal sig_1167 : std_logic;
signal sig_1168 : std_logic;
signal sig_1169 : std_logic;
signal sig_1170 : std_logic;
signal sig_1171 : std_logic;
signal sig_1172 : std_logic;
signal sig_1173 : std_logic;
signal sig_1174 : std_logic;
signal sig_1175 : std_logic;
signal sig_1176 : std_logic;
signal sig_1177 : std_logic;
signal sig_1178 : std_logic;
signal sig_1179 : std_logic;
signal sig_1180 : std_logic;
signal sig_1181 : std_logic;
signal sig_1182 : std_logic;
signal sig_1183 : std_logic;
signal sig_1184 : std_logic;
signal sig_1185 : std_logic;
signal sig_1186 : std_logic;
signal sig_1187 : std_logic;
signal sig_1188 : std_logic;
signal sig_1189 : std_logic;
signal sig_1190 : std_logic;
signal sig_1191 : std_logic;
signal sig_1192 : std_logic;
signal sig_1193 : std_logic;
signal sig_1194 : std_logic;
signal sig_1195 : std_logic;
signal sig_1196 : std_logic;
signal sig_1197 : std_logic;
signal sig_1198 : std_logic;
signal sig_1199 : std_logic;
signal sig_1200 : std_logic;
signal sig_1201 : std_logic;
signal sig_1202 : std_logic;
signal sig_1203 : std_logic;
signal sig_1204 : std_logic;
signal sig_1205 : std_logic;
signal sig_1206 : std_logic;
signal sig_1207 : std_logic;
signal sig_1208 : std_logic;
signal sig_1209 : std_logic;
signal sig_1210 : std_logic;
signal sig_1211 : std_logic;
signal sig_1212 : std_logic;
signal sig_1213 : std_logic;
signal sig_1214 : std_logic;
signal sig_1215 : std_logic;
signal sig_1216 : std_logic;
signal sig_1217 : std_logic;
signal sig_1218 : std_logic;
signal sig_1219 : std_logic;
signal sig_1220 : std_logic;
signal sig_1221 : std_logic;
signal sig_1222 : std_logic;
signal sig_1223 : std_logic;
signal sig_1224 : std_logic;
signal sig_1225 : std_logic;
signal sig_1226 : std_logic;
signal sig_1227 : std_logic;
signal sig_1228 : std_logic;
signal sig_1229 : std_logic;
signal sig_1230 : std_logic;
signal sig_1231 : std_logic;
signal sig_1232 : std_logic;
signal sig_1233 : std_logic;
signal sig_1234 : std_logic;
signal sig_1235 : std_logic;
signal sig_1236 : std_logic;
signal sig_1237 : std_logic;
signal sig_1238 : std_logic;
signal sig_1239 : std_logic;
signal sig_1240 : std_logic;
signal sig_1241 : std_logic;
signal sig_1242 : std_logic;
signal sig_1243 : std_logic;
signal sig_1244 : std_logic;
signal sig_1245 : std_logic;
signal sig_1246 : std_logic;
signal sig_1247 : std_logic;
signal sig_1248 : std_logic;
signal sig_1249 : std_logic;
signal sig_1250 : std_logic;
signal sig_1251 : std_logic;
signal sig_1252 : std_logic;
signal sig_1253 : std_logic;
signal sig_1254 : std_logic;
signal sig_1255 : std_logic;
signal sig_1256 : std_logic;
signal sig_1257 : std_logic;
signal sig_1258 : std_logic;
signal sig_1259 : std_logic;
signal sig_1260 : std_logic;
signal sig_1261 : std_logic;
signal sig_1262 : std_logic;
signal sig_1263 : std_logic;
signal sig_1264 : std_logic;
signal sig_1265 : std_logic;
signal sig_1266 : std_logic;
signal sig_1267 : std_logic;
signal sig_1268 : std_logic;
signal sig_1269 : std_logic;
signal sig_1270 : std_logic;
signal sig_1271 : std_logic;
signal sig_1272 : std_logic;
signal sig_1273 : std_logic;
signal sig_1274 : std_logic;
signal sig_1275 : std_logic;
signal sig_1276 : std_logic;
signal sig_1277 : std_logic;
signal sig_1278 : std_logic;
signal sig_1279 : std_logic;
signal sig_1280 : std_logic;
signal sig_1281 : std_logic_vector(63 downto 0);
signal sig_1282 : std_logic;
signal sig_1283 : std_logic;
signal sig_1284 : std_logic;
signal sig_1285 : std_logic_vector(63 downto 0);
signal sig_1286 : std_logic_vector(31 downto 0);
signal sig_1287 : std_logic_vector(63 downto 0);
signal sig_1288 : std_logic_vector(63 downto 0);
signal sig_1289 : std_logic_vector(63 downto 0);
signal sig_1290 : std_logic_vector(63 downto 0);
signal sig_1291 : std_logic_vector(63 downto 0);
signal sig_1292 : std_logic_vector(63 downto 0);
signal sig_1293 : std_logic_vector(31 downto 0);
signal sig_1294 : std_logic_vector(31 downto 0);
signal sig_1295 : std_logic_vector(31 downto 0);
signal sig_1296 : std_logic_vector(31 downto 0);
signal sig_1297 : std_logic_vector(31 downto 0);
signal sig_1298 : std_logic_vector(63 downto 0);
signal sig_1299 : std_logic;
signal sig_1300 : std_logic;
signal sig_1301 : std_logic;
signal sig_1302 : std_logic_vector(63 downto 0);
signal sig_1303 : std_logic_vector(63 downto 0);
signal sig_1304 : std_logic_vector(63 downto 0);
signal sig_1305 : std_logic;
signal sig_1306 : std_logic;
signal sig_1307 : std_logic_vector(63 downto 0);
signal sig_1308 : std_logic_vector(31 downto 0);
signal sig_1309 : std_logic_vector(31 downto 0);
signal sig_1310 : std_logic_vector(31 downto 0);
signal sig_1311 : std_logic_vector(31 downto 0);
signal sig_1312 : std_logic_vector(31 downto 0);
signal sig_1313 : std_logic_vector(31 downto 0);
signal sig_1314 : std_logic_vector(31 downto 0);
signal sig_1315 : std_logic_vector(31 downto 0);
signal sig_1316 : std_logic_vector(31 downto 0);
signal sig_1317 : std_logic;
signal sig_1318 : std_logic_vector(63 downto 0);
signal sig_1319 : std_logic_vector(63 downto 0);
-- Other inlined components
signal and_757 : std_logic_vector(31 downto 0);
signal or_758 : std_logic_vector(31 downto 0);
signal and_760 : std_logic_vector(31 downto 0);
signal or_761 : std_logic_vector(7 downto 0);
signal not_762 : std_logic;
signal not_764 : std_logic;
signal not_766 : std_logic;
signal or_767 : std_logic_vector(7 downto 0);
signal mux_490 : std_logic_vector(30 downto 0);
signal and_744 : std_logic_vector(31 downto 0);
signal not_746 : std_logic;
signal or_747 : std_logic_vector(31 downto 0);
signal and_748 : std_logic_vector(31 downto 0);
signal not_751 : std_logic;
signal or_752 : std_logic_vector(31 downto 0);
signal and_753 : std_logic_vector(31 downto 0);
signal or_755 : std_logic_vector(31 downto 0);
signal tqmf_reg0 : std_logic_vector(31 downto 0) := (others => '0');
signal tqmf_reg1 : std_logic_vector(31 downto 0) := (others => '0');
signal tqmf_reg2 : std_logic_vector(31 downto 0) := (others => '0');
signal tqmf_reg3 : std_logic_vector(31 downto 0) := (others => '0');
signal tqmf_reg4 : std_logic_vector(31 downto 0) := (others => '0');
signal tqmf_reg5 : std_logic_vector(31 downto 0) := (others => '0');
signal tqmf_reg6 : std_logic_vector(31 downto 0) := (others => '0');
signal tqmf_reg7 : std_logic_vector(31 downto 0) := (others => '0');
signal read32_buf_0 : std_logic_vector(31 downto 0) := (others => '0');
signal write32_val_1 : std_logic_vector(31 downto 0) := (others => '0');
signal filtez_zl : std_logic_vector(63 downto 0) := (others => '0');
signal upzero_wd3 : std_logic_vector(31 downto 0) := (others => '0');
signal upzero_wd2 : std_logic_vector(31 downto 0) := (others => '0');
signal xh : std_logic_vector(31 downto 0) := (others => '0');
signal or_714 : std_logic_vector(31 downto 0);
signal and_715 : std_logic_vector(31 downto 0);
signal and_723 : std_logic_vector(31 downto 0);
signal and_727 : std_logic_vector(31 downto 0);
signal not_728 : std_logic;
signal and_735 : std_logic_vector(31 downto 0);
signal or_742 : std_logic_vector(31 downto 0);
signal and_743 : std_logic_vector(31 downto 0);
signal xl : std_logic_vector(31 downto 0) := (others => '0');
signal xd : std_logic_vector(31 downto 0) := (others => '0');
signal xs : std_logic_vector(31 downto 0) := (others => '0');
signal el : std_logic_vector(31 downto 0) := (others => '0');
signal mux_484 : std_logic_vector(31 downto 0);
signal mux_486 : std_logic_vector(31 downto 0);
signal sl : std_logic_vector(31 downto 0) := (others => '0');
signal mux_488 : std_logic_vector(30 downto 0);
signal szl : std_logic_vector(31 downto 0) := (others => '0');
signal il : std_logic_vector(5 downto 0) := (others => '0');
signal mux_480 : std_logic_vector(31 downto 0);
signal mux_476 : std_logic_vector(31 downto 0);
signal mux_472 : std_logic_vector(30 downto 0);
signal mux_474 : std_logic_vector(30 downto 0);
signal mux_470 : std_logic_vector(31 downto 0);
signal mux_468 : std_logic_vector(31 downto 0);
signal mux_460 : std_logic_vector(31 downto 0);
signal mux_462 : std_logic_vector(31 downto 0);
signal nbl : std_logic_vector(31 downto 0) := (others => '0');
signal mux_456 : std_logic_vector(63 downto 0);
signal al2 : std_logic_vector(31 downto 0) := (others => '0');
signal mux_458 : std_logic_vector(31 downto 0);
signal al1 : std_logic_vector(31 downto 0) := (others => '0');
signal plt2 : std_logic_vector(31 downto 0) := (others => '0');
signal mux_448 : std_logic_vector(31 downto 0);
signal plt1 : std_logic_vector(31 downto 0) := (others => '0');
signal plt : std_logic_vector(31 downto 0) := (others => '0');
signal dlt : std_logic_vector(31 downto 0) := (others => '0');
signal mux_434 : std_logic_vector(31 downto 0);
signal rlt2 : std_logic_vector(30 downto 0) := (others => '0');
signal mux_438 : std_logic_vector(31 downto 0);
signal rlt1 : std_logic_vector(30 downto 0) := (others => '0');
signal mux_440 : std_logic_vector(31 downto 0);
signal rlt : std_logic_vector(30 downto 0) := (others => '0');
signal mux_430 : std_logic_vector(31 downto 0);
signal mux_432 : std_logic_vector(31 downto 0);
signal detl : std_logic_vector(31 downto 0) := (others => '0');
signal mux_424 : std_logic_vector(31 downto 0);
signal mux_426 : std_logic_vector(31 downto 0);
signal mux_422 : std_logic_vector(31 downto 0);
signal deth : std_logic_vector(31 downto 0) := (others => '0');
signal mux_416 : std_logic_vector(63 downto 0);
signal sh : std_logic_vector(31 downto 0) := (others => '0');
signal mux_414 : std_logic_vector(63 downto 0);
signal eh : std_logic_vector(31 downto 0) := (others => '0');
signal mux_406 : std_logic_vector(63 downto 0);
signal mux_400 : std_logic_vector(31 downto 0);
signal mux_402 : std_logic_vector(63 downto 0);
signal ih : std_logic_vector(31 downto 0) := (others => '0');
signal mux_403 : std_logic_vector(63 downto 0);
signal mux_404 : std_logic_vector(63 downto 0);
signal dh : std_logic_vector(31 downto 0) := (others => '0');
signal mux_395 : std_logic_vector(63 downto 0);
signal mux_396 : std_logic_vector(63 downto 0);
signal mux_397 : std_logic_vector(63 downto 0);
signal mux_398 : std_logic_vector(31 downto 0);
signal mux_399 : std_logic_vector(63 downto 0);
signal nbh : std_logic_vector(31 downto 0) := (others => '0');
signal mux_383 : std_logic_vector(5 downto 0);
signal rh : std_logic_vector(31 downto 0) := (others => '0');
signal mux_385 : std_logic_vector(6 downto 0);
signal yh : std_logic_vector(30 downto 0) := (others => '0');
signal mux_390 : std_logic_vector(63 downto 0);
signal ph : std_logic_vector(31 downto 0) := (others => '0');
signal mux_391 : std_logic_vector(63 downto 0);
signal mux_376 : std_logic_vector(6 downto 0);
signal mux_377 : std_logic_vector(31 downto 0);
signal mux_372 : std_logic_vector(31 downto 0);
signal ah2 : std_logic_vector(31 downto 0) := (others => '0');
signal mux_374 : std_logic_vector(6 downto 0);
signal ah1 : std_logic_vector(31 downto 0) := (others => '0');
signal mux_364 : std_logic_vector(31 downto 0);
signal mux_365 : std_logic_vector(32 downto 0);
signal mux_366 : std_logic_vector(31 downto 0);
signal ph2 : std_logic_vector(31 downto 0) := (others => '0');
signal ph1 : std_logic_vector(31 downto 0) := (others => '0');
signal rh2 : std_logic_vector(30 downto 0) := (others => '0');
signal mux_363 : std_logic_vector(32 downto 0);
signal rh1 : std_logic_vector(30 downto 0) := (others => '0');
signal mux_352 : std_logic_vector(63 downto 0);
signal mux_353 : std_logic_vector(63 downto 0);
signal mux_354 : std_logic_vector(63 downto 0);
signal rl : std_logic_vector(31 downto 0) := (others => '0');
signal mux_355 : std_logic_vector(63 downto 0);
signal mux_356 : std_logic_vector(63 downto 0);
signal dec_dlt : std_logic_vector(31 downto 0) := (others => '0');
signal dec_detl : std_logic_vector(31 downto 0) := (others => '0');
signal mux_349 : std_logic_vector(32 downto 0);
signal mux_350 : std_logic_vector(31 downto 0);
signal mux_351 : std_logic_vector(63 downto 0);
signal dec_deth : std_logic_vector(31 downto 0) := (others => '0');
signal mux_341 : std_logic_vector(63 downto 0);
signal mux_342 : std_logic_vector(63 downto 0);
signal mux_338 : std_logic_vector(31 downto 0);
signal dec_plt2 : std_logic_vector(31 downto 0) := (others => '0');
signal dec_plt1 : std_logic_vector(31 downto 0) := (others => '0');
signal mux_336 : std_logic_vector(31 downto 0);
signal dec_plt : std_logic_vector(31 downto 0) := (others => '0');
signal mux_320 : std_logic_vector(31 downto 0);
signal dec_sl : std_logic_vector(31 downto 0) := (others => '0');
signal mux_322 : std_logic_vector(31 downto 0);
signal mux_324 : std_logic_vector(31 downto 0);
signal mux_326 : std_logic_vector(31 downto 0);
signal mux_310 : std_logic_vector(31 downto 0);
signal dec_rlt : std_logic_vector(30 downto 0) := (others => '0');
signal mux_314 : std_logic_vector(32 downto 0);
signal mux_315 : std_logic_vector(31 downto 0);
signal dec_rlt2 : std_logic_vector(30 downto 0) := (others => '0');
signal mux_316 : std_logic_vector(31 downto 0);
signal mux_318 : std_logic_vector(31 downto 0);
signal dec_rlt1 : std_logic_vector(30 downto 0) := (others => '0');
signal dec_al2 : std_logic_vector(31 downto 0) := (others => '0');
signal mux_308 : std_logic_vector(31 downto 0);
signal dec_al1 : std_logic_vector(31 downto 0) := (others => '0');
signal dl : std_logic_vector(31 downto 0) := (others => '0');
signal mux_292 : std_logic_vector(31 downto 0);
signal mux_294 : std_logic_vector(31 downto 0);
signal dec_nbh : std_logic_vector(31 downto 0) := (others => '0');
signal mux_296 : std_logic_vector(31 downto 0);
signal dec_dh : std_logic_vector(31 downto 0) := (others => '0');
signal mux_298 : std_logic_vector(31 downto 0);
signal dec_nbl : std_logic_vector(31 downto 0) := (others => '0');
signal mux_290 : std_logic_vector(31 downto 0);
signal mux_286 : std_logic_vector(31 downto 0);
signal mux_288 : std_logic_vector(31 downto 0);
signal mux_284 : std_logic_vector(31 downto 0);
signal mux_278 : std_logic_vector(31 downto 0);
signal dec_rh2 : std_logic_vector(30 downto 0) := (others => '0');
signal mux_280 : std_logic_vector(31 downto 0);
signal mux_282 : std_logic_vector(31 downto 0);
signal dec_rh1 : std_logic_vector(30 downto 0) := (others => '0');
signal mux_272 : std_logic_vector(31 downto 0);
signal dec_ah2 : std_logic_vector(31 downto 0) := (others => '0');
signal mux_274 : std_logic_vector(31 downto 0);
signal mux_276 : std_logic_vector(31 downto 0);
signal dec_ah1 : std_logic_vector(31 downto 0) := (others => '0');
signal dec_ph : std_logic_vector(31 downto 0) := (others => '0');
signal mux_262 : std_logic_vector(31 downto 0);
signal dec_sh : std_logic_vector(31 downto 0) := (others => '0');
signal dec_ph2 : std_logic_vector(31 downto 0) := (others => '0');
signal mux_260 : std_logic_vector(31 downto 0);
signal dec_ph1 : std_logic_vector(31 downto 0) := (others => '0');
signal mux_250 : std_logic_vector(31 downto 0);
signal abs_m_3 : std_logic_vector(31 downto 0) := (others => '0');
signal mux_248 : std_logic_vector(31 downto 0);
signal mux_244 : std_logic_vector(31 downto 0);
signal mux_246 : std_logic_vector(31 downto 0);
signal mux_242 : std_logic_vector(31 downto 0);
signal mux_238 : std_logic_vector(31 downto 0);
signal mux_240 : std_logic_vector(31 downto 0);
signal filtep_pl_14 : std_logic_vector(63 downto 0) := (others => '0');
signal mux_236 : std_logic_vector(31 downto 0);
signal quantl_el_16 : std_logic := '0';
signal mux_232 : std_logic_vector(31 downto 0);
signal mux_234 : std_logic_vector(31 downto 0);
signal quantl_detl_17 : std_logic_vector(31 downto 0) := (others => '0');
signal mux_230 : std_logic_vector(31 downto 0);
signal quantl_ril_18 : std_logic_vector(31 downto 0) := (others => '0');
signal mux_226 : std_logic_vector(31 downto 0);
signal mux_228 : std_logic_vector(31 downto 0);
signal quantl_mil_19 : std_logic_vector(31 downto 0) := (others => '0');
signal mux_224 : std_logic_vector(31 downto 0);
signal quantl_wd_20 : std_logic_vector(63 downto 0) := (others => '0');
signal mux_220 : std_logic_vector(31 downto 0);
signal mux_222 : std_logic_vector(31 downto 0);
signal quantl_decis_21 : std_logic_vector(31 downto 0) := (others => '0');
signal mux_218 : std_logic_vector(31 downto 0);
signal logscl_nbl_27 : std_logic_vector(31 downto 0) := (others => '0');
signal mux_214 : std_logic_vector(31 downto 0);
signal mux_216 : std_logic_vector(31 downto 0);
signal logscl_wd_28 : std_logic_vector(31 downto 0) := (others => '0');
signal mux_212 : std_logic_vector(31 downto 0);
signal mux_208 : std_logic_vector(31 downto 0);
signal mux_210 : std_logic_vector(31 downto 0);
signal mux_206 : std_logic_vector(31 downto 0);
signal mux_202 : std_logic_vector(31 downto 0);
signal mux_204 : std_logic_vector(31 downto 0);
signal scalel_wd3_35 : std_logic_vector(28 downto 0) := (others => '0');
signal mux_200 : std_logic_vector(31 downto 0);
signal mux_196 : std_logic_vector(31 downto 0);
signal mux_198 : std_logic_vector(31 downto 0);
signal mux_194 : std_logic_vector(31 downto 0);
signal mux_190 : std_logic_vector(31 downto 0);
signal mux_192 : std_logic_vector(31 downto 0);
signal mux_188 : std_logic_vector(31 downto 0);
signal mux_184 : std_logic_vector(31 downto 0);
signal mux_186 : std_logic_vector(31 downto 0);
signal uppol2_wd4_42 : std_logic_vector(31 downto 0) := (others => '0');
signal mux_182 : std_logic_vector(31 downto 0);
signal uppol2_apl2_43 : std_logic_vector(31 downto 0) := (others => '0');
signal mux_178 : std_logic_vector(31 downto 0);
signal mux_180 : std_logic_vector(31 downto 0);
signal mux_176 : std_logic_vector(31 downto 0);
signal mux_172 : std_logic_vector(31 downto 0);
signal mux_174 : std_logic_vector(31 downto 0);
signal mux_170 : std_logic_vector(31 downto 0);
signal uppol1_wd2_51 : std_logic_vector(31 downto 0) := (others => '0');
signal mux_166 : std_logic_vector(31 downto 0);
signal mux_168 : std_logic_vector(31 downto 0);
signal uppol1_wd3_52 : std_logic_vector(31 downto 0) := (others => '0');
signal mux_164 : std_logic_vector(31 downto 0);
signal uppol1_apl1_53 : std_logic_vector(31 downto 0) := (others => '0');
signal logsch_nbh_57 : std_logic_vector(31 downto 0) := (others => '0');
signal logsch_wd_58 : std_logic_vector(31 downto 0) := (others => '0');
signal encode_xin1_61 : std_logic_vector(31 downto 0) := (others => '0');
signal encode_xin2_62 : std_logic_vector(31 downto 0) := (others => '0');
signal encode_xa_67 : std_logic_vector(63 downto 0) := (others => '0');
signal encode_xb_68 : std_logic_vector(63 downto 0) := (others => '0');
signal encode_decis_69 : std_logic_vector(31 downto 0) := (others => '0');
signal not_709 : std_logic;
signal or_710 : std_logic_vector(31 downto 0);
signal decode_input_98 : std_logic_vector(29 downto 0) := (others => '0');
signal decode_xa1_100 : std_logic_vector(63 downto 0) := (others => '0');
signal decode_xa2_101 : std_logic_vector(63 downto 0) := (others => '0');
signal or_692 : std_logic_vector(7 downto 0);
signal not_693 : std_logic;
signal augh_main_i_132 : std_logic_vector(31 downto 0) := (others => '0');
signal encode_ret0_136 : std_logic_vector(31 downto 0) := (others => '0');
signal not_768 : std_logic;
signal or_769 : std_logic_vector(31 downto 0);
signal and_770 : std_logic_vector(31 downto 0);
signal and_771 : std_logic_vector(31 downto 0);
signal or_619 : std_logic_vector(7 downto 0);
signal not_620 : std_logic;
signal or_621 : std_logic_vector(7 downto 0);
signal not_622 : std_logic;
signal or_623 : std_logic_vector(7 downto 0);
signal not_624 : std_logic;
signal or_625 : std_logic_vector(7 downto 0);
signal not_626 : std_logic;
signal or_627 : std_logic_vector(7 downto 0);
signal and_633 : std_logic_vector(31 downto 0);
signal not_628 : std_logic;
signal or_629 : std_logic_vector(7 downto 0);
signal not_630 : std_logic;
signal dec_del_dhx_reg0 : std_logic_vector(31 downto 0) := (others => '0');
signal dec_del_dhx_reg1 : std_logic_vector(31 downto 0) := (others => '0');
signal or_631 : std_logic_vector(31 downto 0);
signal or_634 : std_logic_vector(7 downto 0);
signal not_635 : std_logic;
signal or_636 : std_logic_vector(7 downto 0);
signal not_637 : std_logic;
signal dec_del_bph_reg0 : std_logic_vector(31 downto 0) := (others => '0');
signal dec_del_bph_reg1 : std_logic_vector(31 downto 0) := (others => '0');
signal dec_del_bph_reg2 : std_logic_vector(31 downto 0) := (others => '0');
signal dec_del_bph_reg3 : std_logic_vector(31 downto 0) := (others => '0');
signal dec_del_bph_reg4 : std_logic_vector(31 downto 0) := (others => '0');
signal dec_del_bph_reg5 : std_logic_vector(31 downto 0) := (others => '0');
signal and_632 : std_logic_vector(31 downto 0);
signal or_641 : std_logic_vector(31 downto 0);
signal and_640 : std_logic_vector(31 downto 0);
signal and_645 : std_logic_vector(31 downto 0);
signal and_639 : std_logic_vector(31 downto 0);
signal and_643 : std_logic_vector(31 downto 0);
signal and_650 : std_logic_vector(31 downto 0);
signal or_651 : std_logic_vector(31 downto 0);
signal or_644 : std_logic_vector(31 downto 0);
signal and_649 : std_logic_vector(31 downto 0);
signal dec_del_dltx_reg0 : std_logic_vector(31 downto 0) := (others => '0');
signal dec_del_dltx_reg1 : std_logic_vector(31 downto 0) := (others => '0');
signal mux_498 : std_logic_vector(31 downto 0);
signal mux_500 : std_logic_vector(31 downto 0);
signal mux_502 : std_logic_vector(31 downto 0);
signal mux_504 : std_logic_vector(31 downto 0);
signal and_652 : std_logic_vector(31 downto 0);
signal and_653 : std_logic_vector(31 downto 0);
signal or_654 : std_logic_vector(31 downto 0);
signal and_655 : std_logic_vector(31 downto 0);
signal and_656 : std_logic_vector(31 downto 0);
signal or_657 : std_logic_vector(31 downto 0);
signal and_658 : std_logic_vector(31 downto 0);
signal and_659 : std_logic_vector(31 downto 0);
signal dec_del_bpl_reg0 : std_logic_vector(31 downto 0) := (others => '0');
signal dec_del_bpl_reg1 : std_logic_vector(31 downto 0) := (others => '0');
signal dec_del_bpl_reg2 : std_logic_vector(31 downto 0) := (others => '0');
signal dec_del_bpl_reg3 : std_logic_vector(31 downto 0) := (others => '0');
signal dec_del_bpl_reg4 : std_logic_vector(31 downto 0) := (others => '0');
signal dec_del_bpl_reg5 : std_logic_vector(31 downto 0) := (others => '0');
signal mux_510 : std_logic_vector(30 downto 0);
signal mux_512 : std_logic_vector(30 downto 0);
signal not_661 : std_logic;
signal and_665 : std_logic_vector(31 downto 0);
signal or_666 : std_logic_vector(31 downto 0);
signal delay_bph_reg0 : std_logic_vector(31 downto 0) := (others => '0');
signal delay_bph_reg1 : std_logic_vector(31 downto 0) := (others => '0');
signal delay_bph_reg2 : std_logic_vector(31 downto 0) := (others => '0');
signal delay_bph_reg3 : std_logic_vector(31 downto 0) := (others => '0');
signal delay_bph_reg4 : std_logic_vector(31 downto 0) := (others => '0');
signal delay_bph_reg5 : std_logic_vector(31 downto 0) := (others => '0');
signal mux_514 : std_logic_vector(31 downto 0);
signal mux_516 : std_logic_vector(31 downto 0);
signal mux_518 : std_logic_vector(31 downto 0);
signal mux_520 : std_logic_vector(31 downto 0);
signal and_647 : std_logic_vector(31 downto 0);
signal and_664 : std_logic_vector(31 downto 0);
signal and_667 : std_logic_vector(31 downto 0);
signal and_670 : std_logic_vector(31 downto 0);
signal and_672 : std_logic_vector(31 downto 0);
signal or_674 : std_logic_vector(31 downto 0);
signal delay_dhx_reg0 : std_logic_vector(31 downto 0) := (others => '0');
signal delay_dhx_reg1 : std_logic_vector(31 downto 0) := (others => '0');
signal mux_528 : std_logic_vector(31 downto 0);
signal or_638 : std_logic_vector(31 downto 0);
signal and_642 : std_logic_vector(31 downto 0);
signal or_648 : std_logic_vector(31 downto 0);
signal or_669 : std_logic_vector(31 downto 0);
signal and_676 : std_logic_vector(31 downto 0);
signal delay_dltx_reg0 : std_logic_vector(31 downto 0) := (others => '0');
signal delay_dltx_reg1 : std_logic_vector(31 downto 0) := (others => '0');
signal mux_532 : std_logic_vector(31 downto 0);
signal mux_534 : std_logic_vector(1 downto 0);
signal mux_535 : std_logic_vector(1 downto 0);
signal or_663 : std_logic_vector(31 downto 0);
signal and_668 : std_logic_vector(31 downto 0);
signal or_679 : std_logic_vector(7 downto 0);
signal not_680 : std_logic;
signal not_682 : std_logic;
signal or_683 : std_logic_vector(7 downto 0);
signal and_686 : std_logic_vector(31 downto 0);
signal and_689 : std_logic_vector(31 downto 0);
signal delay_bpl_reg0 : std_logic_vector(31 downto 0) := (others => '0');
signal delay_bpl_reg1 : std_logic_vector(31 downto 0) := (others => '0');
signal delay_bpl_reg2 : std_logic_vector(31 downto 0) := (others => '0');
signal delay_bpl_reg3 : std_logic_vector(31 downto 0) := (others => '0');
signal delay_bpl_reg4 : std_logic_vector(31 downto 0) := (others => '0');
signal delay_bpl_reg5 : std_logic_vector(31 downto 0) := (others => '0');
signal mux_540 : std_logic_vector(31 downto 0);
signal mux_544 : std_logic_vector(31 downto 0);
signal or_660 : std_logic_vector(7 downto 0);
signal or_677 : std_logic_vector(7 downto 0);
signal not_678 : std_logic;
signal not_684 : std_logic;
signal or_685 : std_logic_vector(31 downto 0);
signal or_688 : std_logic_vector(31 downto 0);
signal or_695 : std_logic_vector(7 downto 0);
signal accumc_reg0 : std_logic_vector(31 downto 0) := (others => '0');
signal accumc_reg1 : std_logic_vector(31 downto 0) := (others => '0');
signal accumc_reg2 : std_logic_vector(31 downto 0) := (others => '0');
signal accumc_reg3 : std_logic_vector(31 downto 0) := (others => '0');
signal accumc_reg4 : std_logic_vector(31 downto 0) := (others => '0');
signal accumc_reg5 : std_logic_vector(31 downto 0) := (others => '0');
signal accumc_reg6 : std_logic_vector(31 downto 0) := (others => '0');
signal accumc_reg7 : std_logic_vector(31 downto 0) := (others => '0');
signal accumc_reg8 : std_logic_vector(31 downto 0) := (others => '0');
signal accumc_reg9 : std_logic_vector(31 downto 0) := (others => '0');
signal accumc_reg10 : std_logic_vector(31 downto 0) := (others => '0');
signal not_671 : std_logic;
signal not_696 : std_logic;
signal or_697 : std_logic_vector(7 downto 0);
signal not_698 : std_logic;
signal or_699 : std_logic_vector(25 downto 0);
signal not_703 : std_logic;
signal accumd_reg0 : std_logic_vector(31 downto 0) := (others => '0');
signal accumd_reg1 : std_logic_vector(31 downto 0) := (others => '0');
signal accumd_reg2 : std_logic_vector(31 downto 0) := (others => '0');
signal accumd_reg3 : std_logic_vector(31 downto 0) := (others => '0');
signal accumd_reg4 : std_logic_vector(31 downto 0) := (others => '0');
signal accumd_reg5 : std_logic_vector(31 downto 0) := (others => '0');
signal accumd_reg6 : std_logic_vector(31 downto 0) := (others => '0');
signal accumd_reg7 : std_logic_vector(31 downto 0) := (others => '0');
signal accumd_reg8 : std_logic_vector(31 downto 0) := (others => '0');
signal accumd_reg9 : std_logic_vector(31 downto 0) := (others => '0');
signal accumd_reg10 : std_logic_vector(31 downto 0) := (others => '0');
signal mux_563 : std_logic_vector(31 downto 0);
signal mux_549 : std_logic_vector(30 downto 0);
signal mux_551 : std_logic_vector(30 downto 0);
signal mux_557 : std_logic_vector(31 downto 0);
signal mux_559 : std_logic_vector(31 downto 0);
signal mux_561 : std_logic_vector(31 downto 0);
signal not_646 : std_logic;
signal and_675 : std_logic_vector(31 downto 0);
signal and_681 : std_logic_vector(31 downto 0);
signal not_690 : std_logic;
signal and_691 : std_logic_vector(31 downto 0);
signal and_702 : std_logic_vector(31 downto 0);
signal or_705 : std_logic_vector(31 downto 0);
signal not_712 : std_logic;
signal or_717 : std_logic_vector(31 downto 0);
signal not_722 : std_logic;
signal tqmf_reg8 : std_logic_vector(31 downto 0) := (others => '0');
signal tqmf_reg9 : std_logic_vector(31 downto 0) := (others => '0');
signal tqmf_reg10 : std_logic_vector(31 downto 0) := (others => '0');
signal tqmf_reg11 : std_logic_vector(31 downto 0) := (others => '0');
signal tqmf_reg12 : std_logic_vector(31 downto 0) := (others => '0');
signal tqmf_reg13 : std_logic_vector(31 downto 0) := (others => '0');
signal tqmf_reg14 : std_logic_vector(31 downto 0) := (others => '0');
signal tqmf_reg15 : std_logic_vector(31 downto 0) := (others => '0');
signal tqmf_reg16 : std_logic_vector(31 downto 0) := (others => '0');
signal tqmf_reg17 : std_logic_vector(31 downto 0) := (others => '0');
signal tqmf_reg18 : std_logic_vector(31 downto 0) := (others => '0');
signal tqmf_reg19 : std_logic_vector(31 downto 0) := (others => '0');
signal tqmf_reg20 : std_logic_vector(31 downto 0) := (others => '0');
signal tqmf_reg21 : std_logic_vector(31 downto 0) := (others => '0');
signal mux_565 : std_logic_vector(31 downto 0);
signal mux_567 : std_logic_vector(4 downto 0);
signal mux_568 : std_logic_vector(3 downto 0);
signal mux_570 : std_logic_vector(3 downto 0);
signal and_687 : std_logic_vector(31 downto 0);
signal and_704 : std_logic_vector(31 downto 0);
signal and_707 : std_logic_vector(31 downto 0);
signal and_716 : std_logic_vector(31 downto 0);
signal or_720 : std_logic_vector(31 downto 0);
signal and_721 : std_logic_vector(31 downto 0);
signal and_724 : std_logic_vector(31 downto 0);
signal or_730 : std_logic_vector(7 downto 0);
signal not_731 : std_logic;
signal or_732 : std_logic_vector(7 downto 0);
signal not_733 : std_logic;
signal or_734 : std_logic_vector(31 downto 0);
signal or_740 : std_logic_vector(7 downto 0);
signal not_741 : std_logic;
signal and_706 : std_logic_vector(31 downto 0);
signal and_713 : std_logic_vector(31 downto 0);
signal and_718 : std_logic_vector(31 downto 0);
signal and_719 : std_logic_vector(31 downto 0);
signal not_725 : std_logic;
signal or_726 : std_logic_vector(31 downto 0);
signal tqmf_reg22 : std_logic_vector(31 downto 0) := (others => '0');
signal tqmf_reg23 : std_logic_vector(31 downto 0) := (others => '0');
signal mux_587 : std_logic_vector(31 downto 0);
signal mux_589 : std_logic_vector(31 downto 0);
signal mux_591 : std_logic_vector(63 downto 0);
signal mux_593 : std_logic_vector(31 downto 0);
signal mux_597 : std_logic_vector(31 downto 0);
signal mux_599 : std_logic_vector(31 downto 0);
signal mux_601 : std_logic_vector(31 downto 0);
signal mux_603 : std_logic_vector(31 downto 0);
signal mux_605 : std_logic_vector(31 downto 0);
signal mux_607 : std_logic_vector(31 downto 0);
signal mux_609 : std_logic_vector(31 downto 0);
signal mux_611 : std_logic_vector(31 downto 0);
signal or_701 : std_logic_vector(31 downto 0);
signal or_708 : std_logic_vector(7 downto 0);
signal and_711 : std_logic_vector(31 downto 0);
signal and_729 : std_logic_vector(31 downto 0);
signal and_736 : std_logic_vector(31 downto 0);
signal or_737 : std_logic_vector(31 downto 0);
signal and_738 : std_logic_vector(31 downto 0);
signal and_739 : std_logic_vector(31 downto 0);
signal or_745 : std_logic_vector(7 downto 0);
signal and_749 : std_logic_vector(31 downto 0);
signal and_750 : std_logic_vector(31 downto 0);
signal and_754 : std_logic_vector(31 downto 0);
signal and_756 : std_logic_vector(31 downto 0);
signal and_759 : std_logic_vector(31 downto 0);
signal and_763 : std_logic_vector(31 downto 0);
signal or_765 : std_logic_vector(7 downto 0);
signal or_772 : std_logic_vector(7 downto 0);
signal not_773 : std_logic;
signal or_774 : std_logic_vector(7 downto 0);
signal not_775 : std_logic;
signal or_776 : std_logic_vector(7 downto 0);
signal not_777 : std_logic;
signal or_778 : std_logic_vector(7 downto 0);
signal not_779 : std_logic;
signal or_780 : std_logic_vector(7 downto 0);
signal not_781 : std_logic;
-- This utility function is used for inlining MUX behaviour
-- Little utility function to ease concatenation of an std_logic
-- and explicitely return an std_logic_vector
function repeat(N: natural; B: std_logic) return std_logic_vector is
variable result: std_logic_vector(N-1 downto 0);
begin
result := (others => B);
return result;
end;
begin
-- Instantiation of components
sub_147_i : sub_147 port map (
output => sig_1318,
sign => '1',
ge => sig_1317,
in_a => sig_1319,
in_b => "1111111111111111111111111111111111111111111111111101000000000000"
);
qq4_code4_table_i : qq4_code4_table port map (
clk => sig_clock,
ra0_data => sig_1316,
ra0_addr => mux_570
);
qq6_code6_table_i : qq6_code6_table port map (
clk => sig_clock,
ra0_data => sig_1315,
ra0_addr => il
);
wl_code_table_i : wl_code_table port map (
clk => sig_clock,
ra0_data => sig_1314,
ra0_addr => mux_568
);
ilb_table_i : ilb_table port map (
clk => sig_clock,
ra0_data => sig_1313,
ra0_addr => mux_567
);
decis_levl_i : decis_levl port map (
clk => sig_clock,
ra0_data => sig_1312,
ra0_addr => quantl_mil_19(4 downto 0)
);
quant26bt_pos_i : quant26bt_pos port map (
clk => sig_clock,
ra0_data => sig_1311,
ra0_addr => quantl_mil_19(4 downto 0)
);
quant26bt_neg_i : quant26bt_neg port map (
clk => sig_clock,
ra0_data => sig_1310,
ra0_addr => quantl_mil_19(4 downto 0)
);
qq2_code2_table_i : qq2_code2_table port map (
clk => sig_clock,
ra0_data => sig_1309,
ra0_addr => mux_535
);
wh_code_table_i : wh_code_table port map (
clk => sig_clock,
ra0_data => sig_1308,
ra0_addr => mux_534
);
cmp_694_i : cmp_694 port map (
in1 => dlt,
in0 => "00000000000000000000000000000000",
eq => augh_test_78
);
cmp_700_i : cmp_700 port map (
in1 => dec_dh,
in0 => "00000000000000000000000000000000",
eq => augh_test_124
);
sub_144_i : sub_144 port map (
output => sig_1307,
le => sig_1306,
sign => '1',
ge => sig_1305,
in_a => mux_402,
in_b => mux_403
);
mul_145_i : mul_145 port map (
output => sig_1304,
in_a => mux_399,
in_b => mux_400
);
mul_146_i : mul_146 port map (
output => sig_1303,
in_a => mux_397,
in_b => mux_398
);
sub_143_i : sub_143 port map (
output => sig_1302,
lt => sig_1301,
le => sig_1300,
sign => '1',
gt => sig_1299,
in_a => mux_395,
in_b => mux_396
);
add_142_i : add_142 port map (
output => sig_1298,
in_a => mux_390,
in_b => mux_391
);
test_data_i : test_data port map (
clk => sig_clock,
ra0_data => sig_1297,
wa0_addr => mux_385,
wa0_en => sig_1213,
ra0_addr => sig_1298(6 downto 0),
wa0_data => read32_buf_0,
ra1_data => sig_1296,
ra1_addr => augh_main_i_132(6 downto 0)
);
shr_141_i : shr_141 port map (
output => sig_1295,
input => sig_1313,
shift => mux_383,
padding => sig_1313(31)
);
compressed_i : compressed port map (
clk => sig_clock,
ra0_data => sig_1294,
wa0_addr => augh_main_i_132(7 downto 1),
wa0_en => sig_1020,
ra0_addr => augh_main_i_132(7 downto 1),
wa0_data => encode_ret0_136
);
result_i : result port map (
clk => sig_clock,
ra0_data => sig_1293,
wa0_addr => mux_374,
wa0_en => sig_1088,
ra0_addr => mux_376,
wa0_data => mux_377
);
cmp_662_i : cmp_662 port map (
in1 => dec_dlt,
in0 => "00000000000000000000000000000000",
eq => augh_test_113
);
cmp_673_i : cmp_673 port map (
in1 => dh,
in0 => "00000000000000000000000000000000",
eq => augh_test_92
);
mul_148_i : mul_148 port map (
output => sig_1292,
in_a => mux_365,
in_b => mux_366
);
mul_149_i : mul_149 port map (
output => sig_1291,
in_a => mux_363,
in_b => mux_364
);
add_153_i : add_153 port map (
output => sig_1290,
in_a => mux_355,
in_b => mux_356
);
add_154_i : add_154 port map (
output => sig_1289,
in_a => mux_353,
in_b => mux_354
);
add_155_i : add_155 port map (
output => sig_1288,
in_a => mux_351,
in_b => mux_352
);
mul_156_i : mul_156 port map (
output => sig_1287,
in_a => mux_349,
in_b => mux_350
);
add_159_i : add_159 port map (
output => sig_1286,
in_a => uppol2_wd4_42,
in_b => sig_1281(38 downto 7)
);
sub_160_i : sub_160 port map (
output => sig_1285,
lt => sig_1284,
le => sig_1283,
sign => '1',
ge => sig_1282,
in_a => mux_341,
in_b => mux_342
);
mul_161_i : mul_161 port map (
output => sig_1281,
in_a => mux_314,
in_b => mux_315
);
fsm_163_i : fsm_163 port map (
clock => sig_clock,
reset => sig_reset,
out91 => sig_1280,
out92 => sig_1279,
out93 => sig_1278,
in7 => augh_test_138,
out94 => sig_1277,
out95 => sig_1276,
out98 => sig_1275,
out100 => sig_1274,
out101 => sig_1273,
out102 => sig_1272,
out104 => sig_1271,
out105 => sig_1270,
out106 => sig_1269,
out107 => sig_1268,
out108 => sig_1267,
out109 => sig_1266,
out111 => sig_1265,
out114 => sig_1264,
out116 => sig_1263,
out118 => sig_1262,
out119 => sig_1261,
out120 => sig_1260,
out128 => sig_1259,
out130 => sig_1258,
out131 => sig_1257,
out132 => sig_1256,
out137 => sig_1255,
in8 => augh_test_137,
out152 => sig_1254,
out155 => sig_1253,
out156 => sig_1252,
out31 => sig_1251,
in2 => sig_start,
out28 => sig_1250,
out29 => sig_1249,
out30 => sig_1248,
out26 => sig_1247,
out27 => sig_1246,
out24 => sig_1245,
out25 => sig_1244,
out77 => sig_1243,
out79 => sig_1242,
out80 => sig_1241,
out82 => sig_1240,
out34 => sig_1239,
out35 => sig_1238,
out36 => sig_1237,
out32 => sig_1236,
out33 => sig_1235,
out40 => sig_1234,
out41 => sig_1233,
out88 => sig_1232,
out89 => sig_1231,
out21 => sig_1230,
out22 => sig_1229,
out23 => sig_1228,
out73 => sig_1227,
out76 => sig_1226,
in6 => augh_test_124,
out70 => sig_1225,
out12 => sig_1224,
out13 => sig_1223,
out14 => sig_1222,
out17 => sig_1221,
out18 => sig_1220,
out19 => sig_1219,
out20 => sig_1218,
out9 => sig_1217,
out11 => stdout_rdy,
out8 => sig_1216,
out2 => sig_1215,
out4 => sig_1214,
out5 => sig_1213,
in1 => stdin_ack,
out6 => sig_1212,
out7 => sig_1211,
out0 => sig_1210,
out1 => sig_1209,
out37 => sig_1208,
out38 => sig_1207,
out39 => sig_1206,
out1222 => sig_1205,
out1223 => sig_1204,
out1224 => sig_1203,
out1225 => sig_1202,
out1226 => sig_1201,
out1228 => sig_1200,
out1230 => sig_1199,
in0 => stdout_ack,
out67 => sig_1198,
out68 => sig_1197,
out65 => sig_1196,
out66 => sig_1195,
in5 => augh_test_78,
out62 => sig_1194,
out58 => sig_1193,
out56 => sig_1192,
in4 => augh_test_92,
out57 => sig_1191,
out54 => sig_1190,
out55 => sig_1189,
out51 => sig_1188,
out52 => sig_1187,
out53 => sig_1186,
in3 => augh_test_113,
out46 => sig_1185,
out47 => sig_1184,
out48 => sig_1183,
out49 => sig_1182,
out50 => sig_1181,
out42 => sig_1180,
out43 => sig_1179,
out44 => sig_1178,
out45 => sig_1177,
in9 => augh_test_23,
in10 => augh_test_24,
out171 => sig_1176,
in11 => augh_test_135,
out191 => sig_1175,
out207 => sig_1174,
out208 => sig_1173,
out209 => sig_1172,
out212 => sig_1171,
out213 => sig_1170,
out216 => sig_1169,
out220 => sig_1168,
out221 => sig_1167,
out223 => sig_1166,
out224 => sig_1165,
out226 => sig_1164,
out227 => sig_1163,
out228 => sig_1162,
out229 => sig_1161,
out230 => sig_1160,
out233 => sig_1159,
out235 => sig_1158,
out236 => sig_1157,
out237 => sig_1156,
out238 => sig_1155,
out239 => sig_1154,
out241 => sig_1153,
out250 => sig_1152,
out258 => sig_1151,
out259 => sig_1150,
out261 => sig_1149,
out270 => sig_1148,
out276 => sig_1147,
out277 => sig_1146,
out283 => sig_1145,
out285 => sig_1144,
out287 => sig_1143,
out290 => sig_1142,
out291 => sig_1141,
out293 => sig_1140,
out301 => sig_1139,
out303 => sig_1138,
out304 => sig_1137,
out315 => sig_1136,
out319 => sig_1135,
out321 => sig_1134,
out330 => sig_1133,
out335 => sig_1132,
out338 => sig_1131,
out341 => sig_1130,
out342 => sig_1129,
out344 => sig_1128,
out347 => sig_1127,
out351 => sig_1126,
out354 => sig_1125,
out355 => sig_1124,
out356 => sig_1123,
out357 => sig_1122,
out358 => sig_1121,
out360 => sig_1120,
out361 => sig_1119,
out362 => sig_1118,
out365 => sig_1117,
out367 => sig_1116,
out368 => sig_1115,
out370 => sig_1114,
out375 => sig_1113,
out376 => sig_1112,
out378 => sig_1111,
out381 => sig_1110,
out382 => sig_1109,
out386 => sig_1108,
out387 => sig_1107,
out388 => sig_1106,
out390 => sig_1105,
out392 => sig_1104,
out393 => sig_1103,
out394 => sig_1102,
out397 => sig_1101,
out403 => sig_1100,
out404 => sig_1099,
out408 => sig_1098,
out409 => sig_1097,
out410 => sig_1096,
out412 => sig_1095,
out416 => sig_1094,
out417 => sig_1093,
out418 => sig_1092,
out419 => sig_1091,
out420 => sig_1090,
out421 => sig_1089,
out424 => sig_1088,
out425 => sig_1087,
out430 => sig_1086,
out431 => sig_1085,
out434 => sig_1084,
out436 => sig_1083,
out438 => sig_1082,
out439 => sig_1081,
out440 => sig_1080,
out441 => sig_1079,
out442 => sig_1078,
out443 => sig_1077,
out444 => sig_1076,
out445 => sig_1075,
out446 => sig_1074,
out447 => sig_1073,
out448 => sig_1072,
out450 => sig_1071,
out451 => sig_1070,
out454 => sig_1069,
out457 => sig_1068,
out460 => sig_1067,
out463 => sig_1066,
out465 => sig_1065,
out466 => sig_1064,
out472 => sig_1063,
out473 => sig_1062,
out475 => sig_1061,
out476 => sig_1060,
out479 => sig_1059,
out480 => sig_1058,
out481 => sig_1057,
out482 => sig_1056,
out484 => sig_1055,
out485 => sig_1054,
out489 => sig_1053,
out491 => sig_1052,
out494 => sig_1051,
out497 => sig_1050,
out500 => sig_1049,
out503 => sig_1048,
out504 => sig_1047,
out505 => sig_1046,
out508 => sig_1045,
out509 => sig_1044,
out513 => sig_1043,
out514 => sig_1042,
out516 => sig_1041,
out521 => sig_1040,
out523 => sig_1039,
out524 => sig_1038,
out525 => sig_1037,
out530 => sig_1036,
out532 => sig_1035,
out533 => sig_1034,
out535 => sig_1033,
out536 => sig_1032,
out539 => sig_1031,
out541 => sig_1030,
out543 => sig_1029,
out545 => sig_1028,
out547 => sig_1027,
out549 => sig_1026,
out550 => sig_1025,
out552 => sig_1024,
out558 => sig_1023,
out559 => sig_1022,
out563 => sig_1021,
out566 => sig_1020,
out572 => sig_1019,
out573 => sig_1018,
out576 => sig_1017,
out577 => sig_1016,
out581 => sig_1015,
out582 => sig_1014,
out590 => sig_1013,
out591 => sig_1012,
out592 => sig_1011,
out593 => sig_1010,
out595 => sig_1009,
out611 => sig_1008,
out619 => sig_1007,
out638 => sig_1006,
out643 => sig_1005,
out644 => sig_1004,
out645 => sig_1003,
out646 => sig_1002,
out648 => sig_1001,
out650 => sig_1000,
out652 => sig_999,
out657 => sig_998,
out659 => sig_997,
out662 => sig_996,
out677 => sig_995,
out678 => sig_994,
out679 => sig_993,
out680 => sig_992,
out682 => sig_991,
out686 => sig_990,
out692 => sig_989,
out1218 => sig_988,
out1219 => sig_987,
out1220 => sig_986,
out1221 => sig_985,
out695 => sig_984,
out697 => sig_983,
out706 => sig_982,
out719 => sig_981,
out729 => sig_980,
out744 => sig_979,
out746 => sig_978,
out748 => sig_977,
out833 => sig_976,
out834 => sig_975,
out836 => sig_974,
out837 => sig_973,
out839 => sig_972,
out840 => sig_971,
out841 => sig_970,
out844 => sig_969,
out845 => sig_968,
out846 => sig_967,
out848 => sig_966,
out850 => sig_965,
out852 => sig_964,
out854 => sig_963,
out856 => sig_962,
out858 => sig_961,
out860 => sig_960,
out863 => sig_959,
out865 => sig_958,
out866 => sig_957,
out873 => sig_956,
out877 => sig_955,
out888 => sig_954,
out891 => sig_953,
out893 => sig_952,
out895 => sig_951,
out898 => sig_950,
out900 => sig_949,
out902 => sig_948,
out903 => sig_947,
out904 => sig_946,
out905 => sig_945,
out906 => sig_944,
out907 => sig_943,
out908 => sig_942,
out909 => sig_941,
out910 => sig_940,
out912 => sig_939,
out913 => sig_938,
out914 => sig_937,
out915 => sig_936,
out917 => sig_935,
out920 => sig_934,
out921 => sig_933,
out924 => sig_932,
out934 => sig_931,
out935 => sig_930,
out937 => sig_929,
out938 => sig_928,
out940 => sig_927,
out943 => sig_926,
out945 => sig_925,
out957 => sig_924,
out958 => sig_923,
out962 => sig_922,
out968 => sig_921,
out972 => sig_920,
out973 => sig_919,
out974 => sig_918,
out975 => sig_917,
out976 => sig_916,
out980 => sig_915,
out986 => sig_914,
out988 => sig_913,
out989 => sig_912,
out990 => sig_911,
out1004 => sig_910,
out1008 => sig_909,
out999 => sig_908,
out1000 => sig_907,
out1002 => sig_906,
out1003 => sig_905,
out1050 => sig_904,
out1052 => sig_903,
out1053 => sig_902,
out1055 => sig_901,
out1056 => sig_900,
out1057 => sig_899,
out1059 => sig_898,
out1015 => sig_897,
out1025 => sig_896,
out1026 => sig_895,
out1038 => sig_894,
out1039 => sig_893,
out1042 => sig_892,
out1043 => sig_891,
out1046 => sig_890,
out1048 => sig_889,
out1061 => sig_888,
out1063 => sig_887,
out1064 => sig_886,
out1067 => sig_885,
out1068 => sig_884,
out1069 => sig_883,
out1071 => sig_882,
out1073 => sig_881,
out1076 => sig_880,
out1077 => sig_879,
out1078 => sig_878,
out1080 => sig_877,
out1081 => sig_876,
out1083 => sig_875,
out1085 => sig_874,
out1087 => sig_873,
out1089 => sig_872,
out1092 => sig_871,
out1096 => sig_870,
out1100 => sig_869,
out1103 => sig_868,
out1115 => sig_867,
out1122 => sig_866,
out1123 => sig_865,
out1127 => sig_864,
out1130 => sig_863,
out1133 => sig_862,
out1138 => sig_861,
out1139 => sig_860,
out1140 => sig_859,
out1141 => sig_858,
out1142 => sig_857,
out1143 => sig_856,
out1144 => sig_855,
out1145 => sig_854,
out1146 => sig_853,
out1147 => sig_852,
out1148 => sig_851,
out1149 => sig_850,
out1150 => sig_849,
out1151 => sig_848,
out1152 => sig_847,
out1153 => sig_846,
out1154 => sig_845,
out1155 => sig_844,
out1156 => sig_843,
out1157 => sig_842,
out1158 => sig_841,
out1159 => sig_840,
out1160 => sig_839,
out1161 => sig_838,
out1162 => sig_837,
out1163 => sig_836,
out1164 => sig_835,
out1165 => sig_834,
out1166 => sig_833,
out1167 => sig_832,
out1168 => sig_831,
out1169 => sig_830,
out1170 => sig_829,
out1171 => sig_828,
out1172 => sig_827,
out1173 => sig_826,
out1174 => sig_825,
out1175 => sig_824,
out1176 => sig_823,
out1177 => sig_822,
out1178 => sig_821,
out1179 => sig_820,
out1180 => sig_819,
out1181 => sig_818,
out1182 => sig_817,
out1183 => sig_816,
out1184 => sig_815,
out1185 => sig_814,
out1186 => sig_813,
out1187 => sig_812,
out1188 => sig_811,
out1189 => sig_810,
out1190 => sig_809,
out1191 => sig_808,
out1192 => sig_807,
out1193 => sig_806,
out1194 => sig_805,
out1195 => sig_804,
out1196 => sig_803,
out1197 => sig_802,
out1198 => sig_801,
out1199 => sig_800,
out1200 => sig_799,
out1201 => sig_798,
out1202 => sig_797,
out1203 => sig_796,
out1204 => sig_795,
out1205 => sig_794,
out1206 => sig_793,
out1207 => sig_792,
out1208 => sig_791,
out1209 => sig_790,
out1210 => sig_789,
out1211 => sig_788,
out1212 => sig_787,
out1213 => sig_786,
out1214 => sig_785,
out1215 => sig_784,
out1216 => sig_783,
out1217 => sig_782
);
-- Behaviour of component 'and_757' model 'and'
and_757 <=
uppol1_apl1_53 and
sig_1306 & sig_1306 & sig_1306 & sig_1306 & sig_1306 & sig_1306 & sig_1306 & sig_1306 & sig_1306 & sig_1306 & sig_1306 & sig_1306 & sig_1306 & sig_1306 & sig_1306 & sig_1306 & sig_1306 & sig_1306 & sig_1306 & sig_1306 & sig_1306 & sig_1306 & sig_1306 & sig_1306 & sig_1306 & sig_1306 & sig_1306 & sig_1306 & sig_1306 & sig_1306 & sig_1306 & sig_1306;
-- Behaviour of component 'or_758' model 'or'
or_758 <=
and_760 or
and_759;
-- Behaviour of component 'and_760' model 'and'
and_760 <=
uppol2_apl2_43 and
sig_1305 & sig_1305 & sig_1305 & sig_1305 & sig_1305 & sig_1305 & sig_1305 & sig_1305 & sig_1305 & sig_1305 & sig_1305 & sig_1305 & sig_1305 & sig_1305 & sig_1305 & sig_1305 & sig_1305 & sig_1305 & sig_1305 & sig_1305 & sig_1305 & sig_1305 & sig_1305 & sig_1305 & sig_1305 & sig_1305 & sig_1305 & sig_1305 & sig_1305 & sig_1305 & sig_1305 & sig_1305;
-- Behaviour of component 'or_761' model 'or'
or_761 <=
sig_1304(31) & "0000000" or
not_762 & "0000000";
-- Behaviour of component 'not_762' model 'not'
not_762 <= not (
sig_1304(31)
);
-- Behaviour of component 'not_764' model 'not'
not_764 <= not (
logsch_nbh_57(31)
);
-- Behaviour of component 'not_766' model 'not'
not_766 <= not (
sig_1304(31)
);
-- Behaviour of component 'or_767' model 'or'
or_767 <=
sig_1303(31) & "0000000" or
not_768 & "0000000";
-- Behaviour of component 'mux_490' model 'mux'
mux_490 <=
(repeat(31, sig_895) and dec_rlt1);
-- Behaviour of component 'and_744' model 'and'
and_744 <=
uppol1_apl1_53 and
sig_1282 & sig_1282 & sig_1282 & sig_1282 & sig_1282 & sig_1282 & sig_1282 & sig_1282 & sig_1282 & sig_1282 & sig_1282 & sig_1282 & sig_1282 & sig_1282 & sig_1282 & sig_1282 & sig_1282 & sig_1282 & sig_1282 & sig_1282 & sig_1282 & sig_1282 & sig_1282 & sig_1282 & sig_1282 & sig_1282 & sig_1282 & sig_1282 & sig_1282 & sig_1282 & sig_1282 & sig_1282;
-- Behaviour of component 'not_746' model 'not'
not_746 <= not (
sig_1303(31)
);
-- Behaviour of component 'or_747' model 'or'
or_747 <=
and_749 or
and_748;
-- Behaviour of component 'and_748' model 'and'
and_748 <=
"00000000000000000011000000000000" and
sig_1299 & sig_1299 & sig_1299 & sig_1299 & sig_1299 & sig_1299 & sig_1299 & sig_1299 & sig_1299 & sig_1299 & sig_1299 & sig_1299 & sig_1299 & sig_1299 & sig_1299 & sig_1299 & sig_1299 & sig_1299 & sig_1299 & sig_1299 & sig_1299 & sig_1299 & sig_1299 & sig_1299 & sig_1299 & sig_1299 & sig_1299 & sig_1299 & sig_1299 & sig_1299 & sig_1299 & sig_1299;
-- Behaviour of component 'not_751' model 'not'
not_751 <= not (
logsch_nbh_57(31)
);
-- Behaviour of component 'or_752' model 'or'
or_752 <=
and_754 or
and_753;
-- Behaviour of component 'and_753' model 'and'
and_753 <=
sig_1307(31 downto 0) and
sig_1301 & sig_1301 & sig_1301 & sig_1301 & sig_1301 & sig_1301 & sig_1301 & sig_1301 & sig_1301 & sig_1301 & sig_1301 & sig_1301 & sig_1301 & sig_1301 & sig_1301 & sig_1301 & sig_1301 & sig_1301 & sig_1301 & sig_1301 & sig_1301 & sig_1301 & sig_1301 & sig_1301 & sig_1301 & sig_1301 & sig_1301 & sig_1301 & sig_1301 & sig_1301 & sig_1301 & sig_1301;
-- Behaviour of component 'or_755' model 'or'
or_755 <=
and_757 or
and_756;
-- Behaviour of component 'or_714' model 'or'
or_714 <=
and_716 or
and_715;
-- Behaviour of component 'and_715' model 'and'
and_715 <=
"11111111111111111101000000000000" and
sig_1301 & sig_1301 & sig_1301 & sig_1301 & sig_1301 & sig_1301 & sig_1301 & sig_1301 & sig_1301 & sig_1301 & sig_1301 & sig_1301 & sig_1301 & sig_1301 & sig_1301 & sig_1301 & sig_1301 & sig_1301 & sig_1301 & sig_1301 & sig_1301 & sig_1301 & sig_1301 & sig_1301 & sig_1301 & sig_1301 & sig_1301 & sig_1301 & sig_1301 & sig_1301 & sig_1301 & sig_1301;
-- Behaviour of component 'and_723' model 'and'
and_723 <=
sig_1302(31 downto 0) and
sig_1303(31) & sig_1303(31) & sig_1303(31) & sig_1303(31) & sig_1303(31) & sig_1303(31) & sig_1303(31) & sig_1303(31) & sig_1303(31) & sig_1303(31) & sig_1303(31) & sig_1303(31) & sig_1303(31) & sig_1303(31) & sig_1303(31) & sig_1303(31) & sig_1303(31) & sig_1303(31) & sig_1303(31) & sig_1303(31) & sig_1303(31) & sig_1303(31) & sig_1303(31) & sig_1303(31) & sig_1303(31) & sig_1303(31) & sig_1303(31) & sig_1303(31) & sig_1303(31) & sig_1303(31) & sig_1303(31) & sig_1303(31);
-- Behaviour of component 'and_727' model 'and'
and_727 <=
sig_1290(25 downto 0) & uppol1_wd2_51(5 downto 0) and
not_728 & not_728 & not_728 & not_728 & not_728 & not_728 & not_728 & not_728 & not_728 & not_728 & not_728 & not_728 & not_728 & not_728 & not_728 & not_728 & not_728 & not_728 & not_728 & not_728 & not_728 & not_728 & not_728 & not_728 & not_728 & not_728 & not_728 & not_728 & not_728 & not_728 & not_728 & not_728;
-- Behaviour of component 'not_728' model 'not'
not_728 <= not (
sig_1281(31)
);
-- Behaviour of component 'and_735' model 'and'
and_735 <=
uppol1_wd3_52 and
sig_1299 & sig_1299 & sig_1299 & sig_1299 & sig_1299 & sig_1299 & sig_1299 & sig_1299 & sig_1299 & sig_1299 & sig_1299 & sig_1299 & sig_1299 & sig_1299 & sig_1299 & sig_1299 & sig_1299 & sig_1299 & sig_1299 & sig_1299 & sig_1299 & sig_1299 & sig_1299 & sig_1299 & sig_1299 & sig_1299 & sig_1299 & sig_1299 & sig_1299 & sig_1299 & sig_1299 & sig_1299;
-- Behaviour of component 'or_742' model 'or'
or_742 <=
and_744 or
and_743;
-- Behaviour of component 'and_743' model 'and'
and_743 <=
sig_1307(31 downto 0) and
sig_1301 & sig_1301 & sig_1301 & sig_1301 & sig_1301 & sig_1301 & sig_1301 & sig_1301 & sig_1301 & sig_1301 & sig_1301 & sig_1301 & sig_1301 & sig_1301 & sig_1301 & sig_1301 & sig_1301 & sig_1301 & sig_1301 & sig_1301 & sig_1301 & sig_1301 & sig_1301 & sig_1301 & sig_1301 & sig_1301 & sig_1301 & sig_1301 & sig_1301 & sig_1301 & sig_1301 & sig_1301;
-- Behaviour of component 'mux_484' model 'mux'
mux_484 <=
(repeat(32, sig_993) and uppol1_apl1_53);
-- Behaviour of component 'mux_486' model 'mux'
mux_486 <=
(repeat(32, sig_1015) and uppol2_apl2_43);
-- Behaviour of component 'mux_488' model 'mux'
mux_488 <=
(repeat(31, sig_1133) and dec_rlt);
-- Behaviour of component 'mux_480' model 'mux'
mux_480 <=
(repeat(32, sig_1015) and logsch_nbh_57);
-- Behaviour of component 'mux_476' model 'mux'
mux_476 <=
(repeat(32, sig_1033) and logscl_nbl_27);
-- Behaviour of component 'mux_472' model 'mux'
mux_472 <=
(repeat(31, sig_954) and rh(30 downto 0));
-- Behaviour of component 'mux_474' model 'mux'
mux_474 <=
(repeat(31, sig_1257) and dec_rh1);
-- Behaviour of component 'mux_470' model 'mux'
mux_470 <=
(repeat(32, sig_1027) and uppol2_apl2_43);
-- Behaviour of component 'mux_468' model 'mux'
mux_468 <=
(repeat(32, sig_1059) and uppol1_apl1_53);
-- Behaviour of component 'mux_460' model 'mux'
mux_460 <=
(repeat(32, sig_954) and dec_ph);
-- Behaviour of component 'mux_462' model 'mux'
mux_462 <=
(repeat(32, sig_1257) and dec_ph1);
-- Behaviour of component 'mux_456' model 'mux'
mux_456 <=
(repeat(64, sig_1133) and sig_1298) or
(repeat(64, sig_1154) and sig_1303) or
(repeat(64, sig_1241) and sig_1290) or
(repeat(64, sig_868) and sig_1281) or
(repeat(64, sig_895) and sig_1287) or
(repeat(64, sig_926) and sig_1289);
-- Behaviour of component 'mux_458' model 'mux'
mux_458 <=
(repeat(32, sig_966) and or_710) or
(repeat(32, sig_976) and or_705);
-- Behaviour of component 'mux_448' model 'mux'
mux_448 <=
(repeat(32, sig_901) and sig_1298(31 downto 0));
-- Behaviour of component 'mux_434' model 'mux'
mux_434 <=
(repeat(32, sig_997) and sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & or_697) or
(repeat(32, sig_1153) and sig_1292(31) & sig_1292(31) & sig_1292(31) & sig_1292(31) & sig_1292(31) & sig_1292(31) & sig_1292(31) & sig_1292(31) & sig_1292(31) & sig_1292(31) & sig_1292(31) & sig_1292(31) & sig_1292(31) & sig_1292(31) & sig_1292(31) & sig_1292(31) & sig_1292(31) & sig_1292(31) & sig_1292(31) & sig_1292(31) & sig_1292(31) & sig_1292(31) & sig_1292(31) & sig_1292(31) & or_636) or
(repeat(32, sig_1257) and sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & or_627) or
(repeat(32, sig_895) and sig_1303(31) & sig_1303(31) & sig_1303(31) & sig_1303(31) & sig_1303(31) & sig_1303(31) & sig_1303(31) & sig_1303(31) & sig_1303(31) & sig_1303(31) & sig_1303(31) & sig_1303(31) & sig_1303(31) & sig_1303(31) & sig_1303(31) & sig_1303(31) & sig_1303(31) & sig_1303(31) & sig_1303(31) & sig_1303(31) & sig_1303(31) & sig_1303(31) & sig_1303(31) & sig_1303(31) & or_740);
-- Behaviour of component 'mux_438' model 'mux'
mux_438 <=
(repeat(32, sig_911) and sig_1291(31) & sig_1291(31) & sig_1291(31) & sig_1291(31) & sig_1291(31) & sig_1291(31) & sig_1291(31) & sig_1291(31 downto 7)) or
(repeat(32, sig_1061) and sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31 downto 7));
-- Behaviour of component 'mux_440' model 'mux'
mux_440 <=
(repeat(32, sig_1038) and and_681) or
(repeat(32, sig_1099) and sig_1298(31 downto 0)) or
(repeat(32, sig_1107) and or_648) or
(repeat(32, sig_935) and and_724) or
(repeat(32, sig_1034) and or_685);
-- Behaviour of component 'mux_430' model 'mux'
mux_430 <=
(repeat(32, sig_1149) and sig_1281(31) & sig_1281(31) & sig_1281(31) & sig_1281(31) & sig_1281(31) & sig_1281(31) & sig_1281(31) & sig_1281(31) & sig_1281(31 downto 8)) or
(repeat(32, sig_1256) and sig_1303(31) & sig_1303(31) & sig_1303(31) & sig_1303(31) & sig_1303(31) & sig_1303(31) & sig_1303(31) & sig_1303(31) & sig_1303(31 downto 8));
-- Behaviour of component 'mux_432' model 'mux'
mux_432 <=
(repeat(32, sig_927) and sig_1288(31 downto 0)) or
(repeat(32, sig_908) and or_737) or
(repeat(32, sig_1133) and sig_1286) or
(repeat(32, sig_955) and or_717) or
(repeat(32, sig_1142) and or_641) or
(repeat(32, sig_1166) and or_631) or
(repeat(32, sig_961) and or_714) or
(repeat(32, sig_1022) and sig_1298(31 downto 0)) or
(repeat(32, sig_1091) and or_657) or
(repeat(32, sig_904) and or_747) or
(repeat(32, sig_879) and or_758);
-- Behaviour of component 'mux_424' model 'mux'
mux_424 <=
(repeat(32, sig_1072) and or_666) or
(repeat(32, sig_1133) and sig_1289(31 downto 0)) or
(repeat(32, sig_1142) and or_638) or
(repeat(32, sig_869) and sig_1298(31 downto 0)) or
(repeat(32, sig_874) and and_763) or
(repeat(32, sig_904) and and_750);
-- Behaviour of component 'mux_426' model 'mux'
mux_426 <=
(repeat(32, sig_916) and or_734) or
(repeat(32, sig_893) and or_742) or
(repeat(32, sig_1093) and or_654) or
(repeat(32, sig_927) and or_726) or
(repeat(32, sig_1101) and or_651) or
(repeat(32, sig_1133) and or_644) or
(repeat(32, sig_954) and or_720) or
(repeat(32, sig_1023) and or_688) or
(repeat(32, sig_1082) and or_663) or
(repeat(32, sig_885) and or_752) or
(repeat(32, sig_882) and or_755) or
(repeat(32, sig_865) and or_769);
-- Behaviour of component 'mux_422' model 'mux'
mux_422 <=
(repeat(32, sig_895) and sig_1292(31) & sig_1292(31) & sig_1292(31) & sig_1292(31) & sig_1292(31) & sig_1292(31) & sig_1292(31) & sig_1292(31 downto 7)) or
(repeat(32, sig_1153) and sig_1287(31) & sig_1287(31) & sig_1287(31) & sig_1287(31) & sig_1287(31) & sig_1287(31) & sig_1287(31) & sig_1287(31 downto 7));
-- Behaviour of component 'mux_416' model 'mux'
mux_416 <=
(repeat(64, sig_868) and sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31 downto 0)) or
(repeat(64, sig_1260) and sig_1298) or
(repeat(64, sig_1198) and sig_1289);
-- Behaviour of component 'mux_414' model 'mux'
mux_414 <=
(repeat(64, sig_868) and sig_1303(31) & sig_1303(31) & sig_1303(31) & sig_1303(31) & sig_1303(31) & sig_1303(31) & sig_1303(31) & sig_1303(31) & sig_1303(31) & sig_1303(31) & sig_1303(31) & sig_1303(31) & sig_1303(31) & sig_1303(31) & sig_1303(31) & sig_1303(31) & sig_1303(31) & sig_1303(31) & sig_1303(31) & sig_1303(31) & sig_1303(31) & sig_1303(31) & sig_1303(31) & sig_1303(31) & sig_1303(31) & sig_1303(31) & sig_1303(31) & sig_1303(31) & sig_1303(31) & sig_1303(31) & sig_1303(31) & sig_1303(31) & sig_1303(31 downto 0)) or
(repeat(64, sig_1260) and sig_1289) or
(repeat(64, sig_1198) and sig_1298);
-- Behaviour of component 'mux_406' model 'mux'
mux_406 <=
(repeat(64, sig_955) and sig_1303(31) & sig_1303(31) & sig_1303(31) & sig_1303(31) & sig_1303(31) & sig_1303(31) & sig_1303(31) & sig_1303(31) & sig_1303(31) & sig_1303(31) & sig_1303(31) & sig_1303(31) & sig_1303(31) & sig_1303(31) & sig_1303(31) & sig_1303(31) & sig_1303(31) & sig_1303(31) & sig_1303(31) & sig_1303(31) & sig_1303(31) & sig_1303(31) & sig_1303(31) & sig_1303(31) & sig_1303(31) & sig_1303(31) & sig_1303(31) & sig_1303(31) & sig_1303(31) & sig_1303(31) & sig_1303(31) & sig_1303(31) & sig_1303(31 downto 0)) or
(repeat(64, sig_1066) and sig_1289) or
(repeat(64, sig_1145) and sig_1298);
-- Behaviour of component 'mux_400' model 'mux'
mux_400 <=
(repeat(32, sig_1252) and "00000000000000000000000000001100") or
(repeat(32, sig_1172) and "00000000000000000000000000000000") or
(repeat(32, sig_1278) and "00000000000000000000000011111111") or
(repeat(32, sig_1254) and "00000000000000000011110010010000") or
(repeat(32, sig_1243) and "00000000000000000000000011010100") or
(repeat(32, sig_1196) and "00000000000000000000010110101000") or
(repeat(32, sig_1257) and dec_ph2) or
(repeat(32, sig_1262) and dec_del_dltx_reg1) or
(repeat(32, sig_1273) and delay_dhx_reg0) or
(repeat(32, sig_1163) and "00000000000000000000000000000000") or
(repeat(32, sig_1159) and quantl_detl_17) or
(repeat(32, sig_1147) and "11111111111111111111110110010000") or
(repeat(32, sig_1142) and "00000000000000000000000000000000") or
(repeat(32, sig_1133) and dec_ah2) or
(repeat(32, sig_1119) and "11111111111111111111001101101100") or
(repeat(32, sig_1101) and "00000000000000000000000000000000") or
(repeat(32, sig_1099) and sig_1316) or
(repeat(32, sig_1065) and "00000000000000000000111011011100") or
(repeat(32, sig_1062) and "00000000000000000000000001111111") or
(repeat(32, sig_1049) and "11111111111111111111110010111000") or
(repeat(32, sig_1042) and "00000000000000000000000000000000") or
(repeat(32, sig_1040) and "00000000000000000000000000000000") or
(repeat(32, sig_1038) and "00000000000000000000000000000000") or
(repeat(32, sig_1034) and "00000000000000000000000000000000") or
(repeat(32, sig_1033) and "00000000000000000000000000000000") or
(repeat(32, sig_1009) and "11111111111111111111111111010100") or
(repeat(32, sig_1003) and "00000000000000000000000000000000") or
(repeat(32, sig_997) and ph2) or
(repeat(32, sig_970) and "00000000000000000000000000110000") or
(repeat(32, sig_930) and "00000000000000000000000010000000") or
(repeat(32, sig_928) and delay_dhx_reg1) or
(repeat(32, sig_923) and delay_dltx_reg1) or
(repeat(32, sig_922) and delay_dltx_reg0) or
(repeat(32, sig_912) and dec_del_dltx_reg0) or
(repeat(32, sig_909) and sig_1309) or
(repeat(32, sig_889) and "00000000000000000000000000000000") or
(repeat(32, sig_883) and "00000000000000000000000000000000") or
(repeat(32, sig_879) and "00000000000000000000000000000000") or
(repeat(32, sig_1200) and dec_del_dhx_reg0);
-- Behaviour of component 'mux_402' model 'mux'
mux_402 <=
(repeat(64, sig_1031) and "0000000000000000000000000000000000000000000000000000000000001000") or
(repeat(64, sig_1015) and logsch_nbh_57(16) & logsch_nbh_57(16) & logsch_nbh_57(16) & logsch_nbh_57(16) & logsch_nbh_57(16) & logsch_nbh_57(16) & logsch_nbh_57(16) & logsch_nbh_57(16) & logsch_nbh_57(16) & logsch_nbh_57(16) & logsch_nbh_57(16) & logsch_nbh_57(16) & logsch_nbh_57(16) & logsch_nbh_57(16) & logsch_nbh_57(16) & logsch_nbh_57(16) & logsch_nbh_57(16) & logsch_nbh_57(16) & logsch_nbh_57(16) & logsch_nbh_57(16) & logsch_nbh_57(16) & logsch_nbh_57(16) & logsch_nbh_57(16) & logsch_nbh_57(16) & logsch_nbh_57(16) & logsch_nbh_57(16) & logsch_nbh_57(16) & logsch_nbh_57(16) & logsch_nbh_57(16) & logsch_nbh_57(16) & logsch_nbh_57(16) & logsch_nbh_57(16) & logsch_nbh_57(16) & logsch_nbh_57(16) & logsch_nbh_57(16) & logsch_nbh_57(16) & logsch_nbh_57(16) & logsch_nbh_57(16) & logsch_nbh_57(16) & logsch_nbh_57(16) & logsch_nbh_57(16) & logsch_nbh_57(16) & logsch_nbh_57(16) & logsch_nbh_57(16) & logsch_nbh_57(16) & logsch_nbh_57(16) & logsch_nbh_57(16) & logsch_nbh_57(16) & logsch_nbh_57(16) & logsch_nbh_57(16) & logsch_nbh_57(16) & logsch_nbh_57(16) & logsch_nbh_57(16) & logsch_nbh_57(16) & logsch_nbh_57(16) & logsch_nbh_57(16) & logsch_nbh_57(16) & logsch_nbh_57(16) & logsch_nbh_57(16 downto 11)) or
(repeat(64, sig_1108) and logscl_nbl_27(31) & logscl_nbl_27(31) & logscl_nbl_27(31) & logscl_nbl_27(31) & logscl_nbl_27(31) & logscl_nbl_27(31) & logscl_nbl_27(31) & logscl_nbl_27(31) & logscl_nbl_27(31) & logscl_nbl_27(31) & logscl_nbl_27(31) & logscl_nbl_27(31) & logscl_nbl_27(31) & logscl_nbl_27(31) & logscl_nbl_27(31) & logscl_nbl_27(31) & logscl_nbl_27(31) & logscl_nbl_27(31) & logscl_nbl_27(31) & logscl_nbl_27(31) & logscl_nbl_27(31) & logscl_nbl_27(31) & logscl_nbl_27(31) & logscl_nbl_27(31) & logscl_nbl_27(31) & logscl_nbl_27(31) & logscl_nbl_27(31) & logscl_nbl_27(31) & logscl_nbl_27(31) & logscl_nbl_27(31) & logscl_nbl_27(31) & logscl_nbl_27(31) & logscl_nbl_27) or
(repeat(64, sig_1045) and ih(31) & ih(31) & ih(31) & ih(31) & ih(31) & ih(31) & ih(31) & ih(31) & ih(31) & ih(31) & ih(31) & ih(31) & ih(31) & ih(31) & ih(31) & ih(31) & ih(31) & ih(31) & ih(31) & ih(31) & ih(31) & ih(31) & ih(31) & ih(31) & ih(31) & ih(31) & ih(31) & ih(31) & ih(31) & ih(31) & ih(31) & ih(31) & ih) or
(repeat(64, sig_1143) and logsch_nbh_57(31) & logsch_nbh_57(31) & logsch_nbh_57(31) & logsch_nbh_57(31) & logsch_nbh_57(31) & logsch_nbh_57(31) & logsch_nbh_57(31) & logsch_nbh_57(31) & logsch_nbh_57(31) & logsch_nbh_57(31) & logsch_nbh_57(31) & logsch_nbh_57(31) & logsch_nbh_57(31) & logsch_nbh_57(31) & logsch_nbh_57(31) & logsch_nbh_57(31) & logsch_nbh_57(31) & logsch_nbh_57(31) & logsch_nbh_57(31) & logsch_nbh_57(31) & logsch_nbh_57(31) & logsch_nbh_57(31) & logsch_nbh_57(31) & logsch_nbh_57(31) & logsch_nbh_57(31) & logsch_nbh_57(31) & logsch_nbh_57(31) & logsch_nbh_57(31) & logsch_nbh_57(31) & logsch_nbh_57(31) & logsch_nbh_57(31) & logsch_nbh_57(31) & logsch_nbh_57) or
(repeat(64, sig_1168) and uppol2_apl2_43(31) & uppol2_apl2_43(31) & uppol2_apl2_43(31) & uppol2_apl2_43(31) & uppol2_apl2_43(31) & uppol2_apl2_43(31) & uppol2_apl2_43(31) & uppol2_apl2_43(31) & uppol2_apl2_43(31) & uppol2_apl2_43(31) & uppol2_apl2_43(31) & uppol2_apl2_43(31) & uppol2_apl2_43(31) & uppol2_apl2_43(31) & uppol2_apl2_43(31) & uppol2_apl2_43(31) & uppol2_apl2_43(31) & uppol2_apl2_43(31) & uppol2_apl2_43(31) & uppol2_apl2_43(31) & uppol2_apl2_43(31) & uppol2_apl2_43(31) & uppol2_apl2_43(31) & uppol2_apl2_43(31) & uppol2_apl2_43(31) & uppol2_apl2_43(31) & uppol2_apl2_43(31) & uppol2_apl2_43(31) & uppol2_apl2_43(31) & uppol2_apl2_43(31) & uppol2_apl2_43(31) & uppol2_apl2_43(31) & uppol2_apl2_43) or
(repeat(64, sig_1069) and "0000000000000000000000000000000000000000000000000000000000001010") or
(repeat(64, sig_1102) and uppol1_apl1_53(31) & uppol1_apl1_53(31) & uppol1_apl1_53(31) & uppol1_apl1_53(31) & uppol1_apl1_53(31) & uppol1_apl1_53(31) & uppol1_apl1_53(31) & uppol1_apl1_53(31) & uppol1_apl1_53(31) & uppol1_apl1_53(31) & uppol1_apl1_53(31) & uppol1_apl1_53(31) & uppol1_apl1_53(31) & uppol1_apl1_53(31) & uppol1_apl1_53(31) & uppol1_apl1_53(31) & uppol1_apl1_53(31) & uppol1_apl1_53(31) & uppol1_apl1_53(31) & uppol1_apl1_53(31) & uppol1_apl1_53(31) & uppol1_apl1_53(31) & uppol1_apl1_53(31) & uppol1_apl1_53(31) & uppol1_apl1_53(31) & uppol1_apl1_53(31) & uppol1_apl1_53(31) & uppol1_apl1_53(31) & uppol1_apl1_53(31) & uppol1_apl1_53(31) & uppol1_apl1_53(31) & uppol1_apl1_53(31) & uppol1_apl1_53) or
(repeat(64, sig_954) and rl(31) & rl(31) & rl(31) & rl(31) & rl(31) & rl(31) & rl(31) & rl(31) & rl(31) & rl(31) & rl(31) & rl(31) & rl(31) & rl(31) & rl(31) & rl(31) & rl(31) & rl(31) & rl(31) & rl(31) & rl(31) & rl(31) & rl(31) & rl(31) & rl(31) & rl(31) & rl(31) & rl(31) & rl(31) & rl(31) & rl(31) & rl(31) & rl);
-- Behaviour of component 'mux_403' model 'mux'
mux_403 <=
(repeat(64, sig_954) and rh(31) & rh(31) & rh(31) & rh(31) & rh(31) & rh(31) & rh(31) & rh(31) & rh(31) & rh(31) & rh(31) & rh(31) & rh(31) & rh(31) & rh(31) & rh(31) & rh(31) & rh(31) & rh(31) & rh(31) & rh(31) & rh(31) & rh(31) & rh(31) & rh(31) & rh(31) & rh(31) & rh(31) & rh(31) & rh(31) & rh(31) & rh(31) & rh) or
(repeat(64, sig_1108) and "0000000000000000000000000000000000000000000000000100100000000000") or
(repeat(64, sig_962) and "1111111111111111111111111111111111111111111111111101000000000000") or
(repeat(64, sig_1143) and "0000000000000000000000000000000000000000000000000101100000000000") or
(repeat(64, sig_1167) and "0000000000000000000000000000000000000000000000000011000000000000") or
(repeat(64, sig_1044) and "0000000000000000000000000000000000000000000000000000000000000001") or
(repeat(64, sig_1068) and sig_1302(5) & sig_1302(5) & sig_1302(5) & sig_1302(5) & sig_1302(5) & sig_1302(5) & sig_1302(5) & sig_1302(5) & sig_1302(5) & sig_1302(5) & sig_1302(5) & sig_1302(5) & sig_1302(5) & sig_1302(5) & sig_1302(5) & sig_1302(5) & sig_1302(5) & sig_1302(5) & sig_1302(5) & sig_1302(5) & sig_1302(5) & sig_1302(5) & sig_1302(5) & sig_1302(5) & sig_1302(5) & sig_1302(5) & sig_1302(5) & sig_1302(5) & sig_1302(5) & sig_1302(5) & sig_1302(5) & sig_1302(5) & sig_1302(5) & sig_1302(5) & sig_1302(5) & sig_1302(5) & sig_1302(5) & sig_1302(5) & sig_1302(5) & sig_1302(5) & sig_1302(5) & sig_1302(5) & sig_1302(5) & sig_1302(5) & sig_1302(5) & sig_1302(5) & sig_1302(5) & sig_1302(5) & sig_1302(5) & sig_1302(5) & sig_1302(5) & sig_1302(5) & sig_1302(5) & sig_1302(5) & sig_1302(5) & sig_1302(5) & sig_1302(5) & sig_1302(5) & sig_1302(5 downto 0)) or
(repeat(64, sig_1103) and uppol1_wd3_52(31) & uppol1_wd3_52(31) & uppol1_wd3_52(31) & uppol1_wd3_52(31) & uppol1_wd3_52(31) & uppol1_wd3_52(31) & uppol1_wd3_52(31) & uppol1_wd3_52(31) & uppol1_wd3_52(31) & uppol1_wd3_52(31) & uppol1_wd3_52(31) & uppol1_wd3_52(31) & uppol1_wd3_52(31) & uppol1_wd3_52(31) & uppol1_wd3_52(31) & uppol1_wd3_52(31) & uppol1_wd3_52(31) & uppol1_wd3_52(31) & uppol1_wd3_52(31) & uppol1_wd3_52(31) & uppol1_wd3_52(31) & uppol1_wd3_52(31) & uppol1_wd3_52(31) & uppol1_wd3_52(31) & uppol1_wd3_52(31) & uppol1_wd3_52(31) & uppol1_wd3_52(31) & uppol1_wd3_52(31) & uppol1_wd3_52(31) & uppol1_wd3_52(31) & uppol1_wd3_52(31) & uppol1_wd3_52(31) & uppol1_wd3_52);
-- Behaviour of component 'mux_404' model 'mux'
mux_404 <=
(repeat(64, sig_955) and sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31 downto 0)) or
(repeat(64, sig_1066) and sig_1298) or
(repeat(64, sig_1145) and sig_1289);
-- Behaviour of component 'mux_395' model 'mux'
mux_395 <=
(repeat(64, sig_1031) and logscl_nbl_27(16) & logscl_nbl_27(16) & logscl_nbl_27(16) & logscl_nbl_27(16) & logscl_nbl_27(16) & logscl_nbl_27(16) & logscl_nbl_27(16) & logscl_nbl_27(16) & logscl_nbl_27(16) & logscl_nbl_27(16) & logscl_nbl_27(16) & logscl_nbl_27(16) & logscl_nbl_27(16) & logscl_nbl_27(16) & logscl_nbl_27(16) & logscl_nbl_27(16) & logscl_nbl_27(16) & logscl_nbl_27(16) & logscl_nbl_27(16) & logscl_nbl_27(16) & logscl_nbl_27(16) & logscl_nbl_27(16) & logscl_nbl_27(16) & logscl_nbl_27(16) & logscl_nbl_27(16) & logscl_nbl_27(16) & logscl_nbl_27(16) & logscl_nbl_27(16) & logscl_nbl_27(16) & logscl_nbl_27(16) & logscl_nbl_27(16) & logscl_nbl_27(16) & logscl_nbl_27(16) & logscl_nbl_27(16) & logscl_nbl_27(16) & logscl_nbl_27(16) & logscl_nbl_27(16) & logscl_nbl_27(16) & logscl_nbl_27(16) & logscl_nbl_27(16) & logscl_nbl_27(16) & logscl_nbl_27(16) & logscl_nbl_27(16) & logscl_nbl_27(16) & logscl_nbl_27(16) & logscl_nbl_27(16) & logscl_nbl_27(16) & logscl_nbl_27(16) & logscl_nbl_27(16) & logscl_nbl_27(16) & logscl_nbl_27(16) & logscl_nbl_27(16) & logscl_nbl_27(16) & logscl_nbl_27(16) & logscl_nbl_27(16) & logscl_nbl_27(16) & logscl_nbl_27(16) & logscl_nbl_27(16) & logscl_nbl_27(16 downto 11)) or
(repeat(64, sig_1029) and "0000000000000000000000000000000000000000000000000011110000000000") or
(repeat(64, sig_1135) and uppol1_wd2_51(31) & uppol1_wd2_51(31) & uppol1_wd2_51(31) & uppol1_wd2_51(31) & uppol1_wd2_51(31) & uppol1_wd2_51(31) & uppol1_wd2_51(31) & uppol1_wd2_51(31) & uppol1_wd2_51(31) & uppol1_wd2_51(31) & uppol1_wd2_51(31) & uppol1_wd2_51(31) & uppol1_wd2_51(31) & uppol1_wd2_51(31) & uppol1_wd2_51(31) & uppol1_wd2_51(31) & uppol1_wd2_51(31) & uppol1_wd2_51(31) & uppol1_wd2_51(31) & uppol1_wd2_51(31) & uppol1_wd2_51(31) & uppol1_wd2_51(31) & uppol1_wd2_51(31) & uppol1_wd2_51(31) & uppol1_wd2_51(31) & uppol1_wd2_51(31) & uppol1_wd2_51(31) & uppol1_wd2_51(31) & uppol1_wd2_51(31) & uppol1_wd2_51(31) & uppol1_wd2_51(31) & uppol1_wd2_51(31) & uppol1_wd2_51) or
(repeat(64, sig_1045) and abs_m_3(31) & abs_m_3(31) & abs_m_3(31) & abs_m_3(31) & abs_m_3(31) & abs_m_3(31) & abs_m_3(31) & abs_m_3(31) & abs_m_3(31) & abs_m_3(31) & abs_m_3(31) & abs_m_3(31) & abs_m_3(31) & abs_m_3(31) & abs_m_3(31) & abs_m_3(31) & abs_m_3(31) & abs_m_3(31) & abs_m_3(31) & abs_m_3(31) & abs_m_3(31) & abs_m_3(31) & abs_m_3(31) & abs_m_3(31) & abs_m_3(31) & abs_m_3(31) & abs_m_3(31) & abs_m_3(31) & abs_m_3(31) & abs_m_3(31) & abs_m_3(31) & abs_m_3(31) & abs_m_3) or
(repeat(64, sig_1143) and logsch_nbh_57(31) & logsch_nbh_57(31) & logsch_nbh_57(31) & logsch_nbh_57(31) & logsch_nbh_57(31) & logsch_nbh_57(31) & logsch_nbh_57(31) & logsch_nbh_57(31) & logsch_nbh_57(31) & logsch_nbh_57(31) & logsch_nbh_57(31) & logsch_nbh_57(31) & logsch_nbh_57(31) & logsch_nbh_57(31) & logsch_nbh_57(31) & logsch_nbh_57(31) & logsch_nbh_57(31) & logsch_nbh_57(31) & logsch_nbh_57(31) & logsch_nbh_57(31) & logsch_nbh_57(31) & logsch_nbh_57(31) & logsch_nbh_57(31) & logsch_nbh_57(31) & logsch_nbh_57(31) & logsch_nbh_57(31) & logsch_nbh_57(31) & logsch_nbh_57(31) & logsch_nbh_57(31) & logsch_nbh_57(31) & logsch_nbh_57(31) & logsch_nbh_57(31) & logsch_nbh_57) or
(repeat(64, sig_1168) and uppol2_apl2_43(31) & uppol2_apl2_43(31) & uppol2_apl2_43(31) & uppol2_apl2_43(31) & uppol2_apl2_43(31) & uppol2_apl2_43(31) & uppol2_apl2_43(31) & uppol2_apl2_43(31) & uppol2_apl2_43(31) & uppol2_apl2_43(31) & uppol2_apl2_43(31) & uppol2_apl2_43(31) & uppol2_apl2_43(31) & uppol2_apl2_43(31) & uppol2_apl2_43(31) & uppol2_apl2_43(31) & uppol2_apl2_43(31) & uppol2_apl2_43(31) & uppol2_apl2_43(31) & uppol2_apl2_43(31) & uppol2_apl2_43(31) & uppol2_apl2_43(31) & uppol2_apl2_43(31) & uppol2_apl2_43(31) & uppol2_apl2_43(31) & uppol2_apl2_43(31) & uppol2_apl2_43(31) & uppol2_apl2_43(31) & uppol2_apl2_43(31) & uppol2_apl2_43(31) & uppol2_apl2_43(31) & uppol2_apl2_43(31) & uppol2_apl2_43) or
(repeat(64, sig_1069) and logsch_nbh_57(16) & logsch_nbh_57(16) & logsch_nbh_57(16) & logsch_nbh_57(16) & logsch_nbh_57(16) & logsch_nbh_57(16) & logsch_nbh_57(16) & logsch_nbh_57(16) & logsch_nbh_57(16) & logsch_nbh_57(16) & logsch_nbh_57(16) & logsch_nbh_57(16) & logsch_nbh_57(16) & logsch_nbh_57(16) & logsch_nbh_57(16) & logsch_nbh_57(16) & logsch_nbh_57(16) & logsch_nbh_57(16) & logsch_nbh_57(16) & logsch_nbh_57(16) & logsch_nbh_57(16) & logsch_nbh_57(16) & logsch_nbh_57(16) & logsch_nbh_57(16) & logsch_nbh_57(16) & logsch_nbh_57(16) & logsch_nbh_57(16) & logsch_nbh_57(16) & logsch_nbh_57(16) & logsch_nbh_57(16) & logsch_nbh_57(16) & logsch_nbh_57(16) & logsch_nbh_57(16) & logsch_nbh_57(16) & logsch_nbh_57(16) & logsch_nbh_57(16) & logsch_nbh_57(16) & logsch_nbh_57(16) & logsch_nbh_57(16) & logsch_nbh_57(16) & logsch_nbh_57(16) & logsch_nbh_57(16) & logsch_nbh_57(16) & logsch_nbh_57(16) & logsch_nbh_57(16) & logsch_nbh_57(16) & logsch_nbh_57(16) & logsch_nbh_57(16) & logsch_nbh_57(16) & logsch_nbh_57(16) & logsch_nbh_57(16) & logsch_nbh_57(16) & logsch_nbh_57(16) & logsch_nbh_57(16) & logsch_nbh_57(16) & logsch_nbh_57(16) & logsch_nbh_57(16) & logsch_nbh_57(16) & logsch_nbh_57(16 downto 11)) or
(repeat(64, sig_1103) and uppol1_apl1_53(31) & uppol1_apl1_53(31) & uppol1_apl1_53(31) & uppol1_apl1_53(31) & uppol1_apl1_53(31) & uppol1_apl1_53(31) & uppol1_apl1_53(31) & uppol1_apl1_53(31) & uppol1_apl1_53(31) & uppol1_apl1_53(31) & uppol1_apl1_53(31) & uppol1_apl1_53(31) & uppol1_apl1_53(31) & uppol1_apl1_53(31) & uppol1_apl1_53(31) & uppol1_apl1_53(31) & uppol1_apl1_53(31) & uppol1_apl1_53(31) & uppol1_apl1_53(31) & uppol1_apl1_53(31) & uppol1_apl1_53(31) & uppol1_apl1_53(31) & uppol1_apl1_53(31) & uppol1_apl1_53(31) & uppol1_apl1_53(31) & uppol1_apl1_53(31) & uppol1_apl1_53(31) & uppol1_apl1_53(31) & uppol1_apl1_53(31) & uppol1_apl1_53(31) & uppol1_apl1_53(31) & uppol1_apl1_53(31) & uppol1_apl1_53) or
(repeat(64, sig_1108) and logscl_nbl_27(31) & logscl_nbl_27(31) & logscl_nbl_27(31) & logscl_nbl_27(31) & logscl_nbl_27(31) & logscl_nbl_27(31) & logscl_nbl_27(31) & logscl_nbl_27(31) & logscl_nbl_27(31) & logscl_nbl_27(31) & logscl_nbl_27(31) & logscl_nbl_27(31) & logscl_nbl_27(31) & logscl_nbl_27(31) & logscl_nbl_27(31) & logscl_nbl_27(31) & logscl_nbl_27(31) & logscl_nbl_27(31) & logscl_nbl_27(31) & logscl_nbl_27(31) & logscl_nbl_27(31) & logscl_nbl_27(31) & logscl_nbl_27(31) & logscl_nbl_27(31) & logscl_nbl_27(31) & logscl_nbl_27(31) & logscl_nbl_27(31) & logscl_nbl_27(31) & logscl_nbl_27(31) & logscl_nbl_27(31) & logscl_nbl_27(31) & logscl_nbl_27(31) & logscl_nbl_27) or
(repeat(64, sig_964) and xh(31) & xh(31) & xh(31) & xh(31) & xh(31) & xh(31) & xh(31) & xh(31) & xh(31) & xh(31) & xh(31) & xh(31) & xh(31) & xh(31) & xh(31) & xh(31) & xh(31) & xh(31) & xh(31) & xh(31) & xh(31) & xh(31) & xh(31) & xh(31) & xh(31) & xh(31) & xh(31) & xh(31) & xh(31) & xh(31) & xh(31) & xh(31) & xh) or
(repeat(64, sig_959) and xl(31) & xl(31) & xl(31) & xl(31) & xl(31) & xl(31) & xl(31) & xl(31) & xl(31) & xl(31) & xl(31) & xl(31) & xl(31) & xl(31) & xl(31) & xl(31) & xl(31) & xl(31) & xl(31) & xl(31) & xl(31) & xl(31) & xl(31) & xl(31) & xl(31) & xl(31) & xl(31) & xl(31) & xl(31) & xl(31) & xl(31) & xl(31) & xl) or
(repeat(64, sig_957) and encode_xa_67(46) & encode_xa_67(46) & encode_xa_67(46) & encode_xa_67(46) & encode_xa_67(46) & encode_xa_67(46) & encode_xa_67(46) & encode_xa_67(46) & encode_xa_67(46) & encode_xa_67(46) & encode_xa_67(46) & encode_xa_67(46) & encode_xa_67(46) & encode_xa_67(46) & encode_xa_67(46) & encode_xa_67(46) & encode_xa_67(46) & encode_xa_67(46 downto 0)) or
(repeat(64, sig_951) and augh_main_i_132(31) & augh_main_i_132(31) & augh_main_i_132(31) & augh_main_i_132(31) & augh_main_i_132(31) & augh_main_i_132(31) & augh_main_i_132(31) & augh_main_i_132(31) & augh_main_i_132(31) & augh_main_i_132(31) & augh_main_i_132(31) & augh_main_i_132(31) & augh_main_i_132(31) & augh_main_i_132(31) & augh_main_i_132(31) & augh_main_i_132(31) & augh_main_i_132(31) & augh_main_i_132(31) & augh_main_i_132(31) & augh_main_i_132(31) & augh_main_i_132(31) & augh_main_i_132(31) & augh_main_i_132(31) & augh_main_i_132(31) & augh_main_i_132(31) & augh_main_i_132(31) & augh_main_i_132(31) & augh_main_i_132(31) & augh_main_i_132(31) & augh_main_i_132(31) & augh_main_i_132(31) & augh_main_i_132(31) & augh_main_i_132) or
(repeat(64, sig_898) and quantl_mil_19(31) & quantl_mil_19(31) & quantl_mil_19(31) & quantl_mil_19(31) & quantl_mil_19(31) & quantl_mil_19(31) & quantl_mil_19(31) & quantl_mil_19(31) & quantl_mil_19(31) & quantl_mil_19(31) & quantl_mil_19(31) & quantl_mil_19(31) & quantl_mil_19(31) & quantl_mil_19(31) & quantl_mil_19(31) & quantl_mil_19(31) & quantl_mil_19(31) & quantl_mil_19(31) & quantl_mil_19(31) & quantl_mil_19(31) & quantl_mil_19(31) & quantl_mil_19(31) & quantl_mil_19(31) & quantl_mil_19(31) & quantl_mil_19(31) & quantl_mil_19(31) & quantl_mil_19(31) & quantl_mil_19(31) & quantl_mil_19(31) & quantl_mil_19(31) & quantl_mil_19(31) & quantl_mil_19(31) & quantl_mil_19) or
(repeat(64, sig_881) and quantl_wd_20);
-- Behaviour of component 'mux_396' model 'mux'
mux_396 <=
(repeat(64, sig_1045) and encode_decis_69(31) & encode_decis_69(31) & encode_decis_69(31) & encode_decis_69(31) & encode_decis_69(31) & encode_decis_69(31) & encode_decis_69(31) & encode_decis_69(31) & encode_decis_69(31) & encode_decis_69(31) & encode_decis_69(31) & encode_decis_69(31) & encode_decis_69(31) & encode_decis_69(31) & encode_decis_69(31) & encode_decis_69(31) & encode_decis_69(31) & encode_decis_69(31) & encode_decis_69(31) & encode_decis_69(31) & encode_decis_69(31) & encode_decis_69(31) & encode_decis_69(31) & encode_decis_69(31) & encode_decis_69(31) & encode_decis_69(31) & encode_decis_69(31) & encode_decis_69(31) & encode_decis_69(31) & encode_decis_69(31) & encode_decis_69(31) & encode_decis_69(31) & encode_decis_69) or
(repeat(64, sig_1029) and uppol2_apl2_43(31) & uppol2_apl2_43(31) & uppol2_apl2_43(31) & uppol2_apl2_43(31) & uppol2_apl2_43(31) & uppol2_apl2_43(31) & uppol2_apl2_43(31) & uppol2_apl2_43(31) & uppol2_apl2_43(31) & uppol2_apl2_43(31) & uppol2_apl2_43(31) & uppol2_apl2_43(31) & uppol2_apl2_43(31) & uppol2_apl2_43(31) & uppol2_apl2_43(31) & uppol2_apl2_43(31) & uppol2_apl2_43(31) & uppol2_apl2_43(31) & uppol2_apl2_43(31) & uppol2_apl2_43(31) & uppol2_apl2_43(31) & uppol2_apl2_43(31) & uppol2_apl2_43(31) & uppol2_apl2_43(31) & uppol2_apl2_43(31) & uppol2_apl2_43(31) & uppol2_apl2_43(31) & uppol2_apl2_43(31) & uppol2_apl2_43(31) & uppol2_apl2_43(31) & uppol2_apl2_43(31) & uppol2_apl2_43(31) & uppol2_apl2_43) or
(repeat(64, sig_1135) and "0000000000000000000000000000000000000000000000000000000011000000") or
(repeat(64, sig_1068) and "0000000000000000000000000000000000000000000000000000000000000001") or
(repeat(64, sig_1143) and "0000000000000000000000000000000000000000000000000101100000000000") or
(repeat(64, sig_1167) and "0000000000000000000000000000000000000000000000000011000000000000") or
(repeat(64, sig_1094) and sig_1307(31) & sig_1307(31) & sig_1307(31) & sig_1307(31) & sig_1307(31) & sig_1307(31) & sig_1307(31) & sig_1307(31) & sig_1307(31) & sig_1307(31) & sig_1307(31) & sig_1307(31) & sig_1307(31) & sig_1307(31) & sig_1307(31) & sig_1307(31) & sig_1307(31) & sig_1307(31) & sig_1307(31) & sig_1307(31) & sig_1307(31) & sig_1307(31) & sig_1307(31) & sig_1307(31) & sig_1307(31) & sig_1307(31) & sig_1307(31) & sig_1307(31) & sig_1307(31) & sig_1307(31) & sig_1307(31) & sig_1307(31) & sig_1307(31 downto 0)) or
(repeat(64, sig_1102) and uppol1_wd3_52(31) & uppol1_wd3_52(31) & uppol1_wd3_52(31) & uppol1_wd3_52(31) & uppol1_wd3_52(31) & uppol1_wd3_52(31) & uppol1_wd3_52(31) & uppol1_wd3_52(31) & uppol1_wd3_52(31) & uppol1_wd3_52(31) & uppol1_wd3_52(31) & uppol1_wd3_52(31) & uppol1_wd3_52(31) & uppol1_wd3_52(31) & uppol1_wd3_52(31) & uppol1_wd3_52(31) & uppol1_wd3_52(31) & uppol1_wd3_52(31) & uppol1_wd3_52(31) & uppol1_wd3_52(31) & uppol1_wd3_52(31) & uppol1_wd3_52(31) & uppol1_wd3_52(31) & uppol1_wd3_52(31) & uppol1_wd3_52(31) & uppol1_wd3_52(31) & uppol1_wd3_52(31) & uppol1_wd3_52(31) & uppol1_wd3_52(31) & uppol1_wd3_52(31) & uppol1_wd3_52(31) & uppol1_wd3_52(31) & uppol1_wd3_52) or
(repeat(64, sig_1108) and "0000000000000000000000000000000000000000000000000100100000000000") or
(repeat(64, sig_976) and eh(31) & eh(31) & eh(31) & eh(31) & eh(31) & eh(31) & eh(31) & eh(31) & eh(31) & eh(31) & eh(31) & eh(31) & eh(31) & eh(31) & eh(31) & eh(31) & eh(31) & eh(31) & eh(31) & eh(31) & eh(31) & eh(31) & eh(31) & eh(31) & eh(31) & eh(31) & eh(31) & eh(31) & eh(31) & eh(31) & eh(31) & eh(31) & eh) or
(repeat(64, sig_966) and el(31) & el(31) & el(31) & el(31) & el(31) & el(31) & el(31) & el(31) & el(31) & el(31) & el(31) & el(31) & el(31) & el(31) & el(31) & el(31) & el(31) & el(31) & el(31) & el(31) & el(31) & el(31) & el(31) & el(31) & el(31) & el(31) & el(31) & el(31) & el(31) & el(31) & el(31) & el(31) & el) or
(repeat(64, sig_964) and sh(31) & sh(31) & sh(31) & sh(31) & sh(31) & sh(31) & sh(31) & sh(31) & sh(31) & sh(31) & sh(31) & sh(31) & sh(31) & sh(31) & sh(31) & sh(31) & sh(31) & sh(31) & sh(31) & sh(31) & sh(31) & sh(31) & sh(31) & sh(31) & sh(31) & sh(31) & sh(31) & sh(31) & sh(31) & sh(31) & sh(31) & sh(31) & sh) or
(repeat(64, sig_962) and "1111111111111111111111111111111111111111111111111101000000000000") or
(repeat(64, sig_959) and sl(31) & sl(31) & sl(31) & sl(31) & sl(31) & sl(31) & sl(31) & sl(31) & sl(31) & sl(31) & sl(31) & sl(31) & sl(31) & sl(31) & sl(31) & sl(31) & sl(31) & sl(31) & sl(31) & sl(31) & sl(31) & sl(31) & sl(31) & sl(31) & sl(31) & sl(31) & sl(31) & sl(31) & sl(31) & sl(31) & sl(31) & sl(31) & sl) or
(repeat(64, sig_957) and encode_xb_68(46) & encode_xb_68(46) & encode_xb_68(46) & encode_xb_68(46) & encode_xb_68(46) & encode_xb_68(46) & encode_xb_68(46) & encode_xb_68(46) & encode_xb_68(46) & encode_xb_68(46) & encode_xb_68(46) & encode_xb_68(46) & encode_xb_68(46) & encode_xb_68(46) & encode_xb_68(46) & encode_xb_68(46) & encode_xb_68(46) & encode_xb_68(46 downto 0)) or
(repeat(64, sig_951) and "0000000000000000000000000000000000000000000000000000000001100011") or
(repeat(64, sig_898) and "0000000000000000000000000000000000000000000000000000000000011101") or
(repeat(64, sig_881) and "00000000000000000000000000000000" & quantl_decis_21);
-- Behaviour of component 'mux_397' model 'mux'
mux_397 <=
(repeat(64, sig_1257) and dec_ah1(31) & dec_ah1(31) & dec_ah1(31) & dec_ah1(31) & dec_ah1(31) & dec_ah1(31) & dec_ah1(31) & dec_ah1(31) & dec_ah1(31) & dec_ah1(31) & dec_ah1(31) & dec_ah1(31) & dec_ah1(31) & dec_ah1(31) & dec_ah1(31) & dec_ah1(31) & dec_ah1(31) & dec_ah1(31) & dec_ah1(31) & dec_ah1(31) & dec_ah1(31) & dec_ah1(31) & dec_ah1(31) & dec_ah1(31) & dec_ah1(31) & dec_ah1(31) & dec_ah1(31) & dec_ah1(31) & dec_ah1(31) & dec_ah1(31) & dec_ah1(31) & dec_ah1(31) & dec_ah1) or
(repeat(64, sig_1253) and tqmf_reg10(31) & tqmf_reg10(31) & tqmf_reg10(31) & tqmf_reg10(31) & tqmf_reg10(31) & tqmf_reg10(31) & tqmf_reg10(31) & tqmf_reg10(31) & tqmf_reg10(31) & tqmf_reg10(31) & tqmf_reg10(31) & tqmf_reg10(31) & tqmf_reg10(31) & tqmf_reg10(31) & tqmf_reg10(31) & tqmf_reg10(31) & tqmf_reg10(31) & tqmf_reg10(31) & tqmf_reg10(31) & tqmf_reg10(31) & tqmf_reg10(31) & tqmf_reg10(31) & tqmf_reg10(31) & tqmf_reg10(31) & tqmf_reg10(31) & tqmf_reg10(31) & tqmf_reg10(31) & tqmf_reg10(31) & tqmf_reg10(31) & tqmf_reg10(31) & tqmf_reg10(31) & tqmf_reg10(31) & tqmf_reg10) or
(repeat(64, sig_1275) and dh(31) & dh(31) & dh(31) & dh(31) & dh(31) & dh(31) & dh(31) & dh(31) & dh(31) & dh(31) & dh(31) & dh(31) & dh(31) & dh(31) & dh(31) & dh(31) & dh(31) & dh(31) & dh(31) & dh(31) & dh(31) & dh(31) & dh(31) & dh(31) & dh(31) & dh(31) & dh(31) & dh(31) & dh(31) & dh(31) & dh(31) & dh(31) & dh) or
(repeat(64, sig_1261) and tqmf_reg21(31) & tqmf_reg21(31) & tqmf_reg21(31) & tqmf_reg21(31) & tqmf_reg21(31) & tqmf_reg21(31) & tqmf_reg21(31) & tqmf_reg21(31) & tqmf_reg21(31) & tqmf_reg21(31) & tqmf_reg21(31) & tqmf_reg21(31) & tqmf_reg21(31) & tqmf_reg21(31) & tqmf_reg21(31) & tqmf_reg21(31) & tqmf_reg21(31) & tqmf_reg21(31) & tqmf_reg21(31) & tqmf_reg21(31) & tqmf_reg21(31) & tqmf_reg21(31) & tqmf_reg21(31) & tqmf_reg21(31) & tqmf_reg21(31) & tqmf_reg21(31) & tqmf_reg21(31) & tqmf_reg21(31) & tqmf_reg21(31) & tqmf_reg21(31) & tqmf_reg21(31) & tqmf_reg21(31) & tqmf_reg21) or
(repeat(64, sig_1241) and tqmf_reg2(31) & tqmf_reg2(31) & tqmf_reg2(31) & tqmf_reg2(31) & tqmf_reg2(31) & tqmf_reg2(31) & tqmf_reg2(31) & tqmf_reg2(31) & tqmf_reg2(31) & tqmf_reg2(31) & tqmf_reg2(31) & tqmf_reg2(31) & tqmf_reg2(31) & tqmf_reg2(31) & tqmf_reg2(31) & tqmf_reg2(31) & tqmf_reg2(31) & tqmf_reg2(31) & tqmf_reg2(31) & tqmf_reg2(31) & tqmf_reg2(31) & tqmf_reg2(31) & tqmf_reg2(31) & tqmf_reg2(31) & tqmf_reg2(31) & tqmf_reg2(31) & tqmf_reg2(31) & tqmf_reg2(31) & tqmf_reg2(31) & tqmf_reg2(31) & tqmf_reg2(31) & tqmf_reg2(31) & tqmf_reg2) or
(repeat(64, sig_1195) and tqmf_reg6(31) & tqmf_reg6(31) & tqmf_reg6(31) & tqmf_reg6(31) & tqmf_reg6(31) & tqmf_reg6(31) & tqmf_reg6(31) & tqmf_reg6(31) & tqmf_reg6(31) & tqmf_reg6(31) & tqmf_reg6(31) & tqmf_reg6(31) & tqmf_reg6(31) & tqmf_reg6(31) & tqmf_reg6(31) & tqmf_reg6(31) & tqmf_reg6(31) & tqmf_reg6(31) & tqmf_reg6(31) & tqmf_reg6(31) & tqmf_reg6(31) & tqmf_reg6(31) & tqmf_reg6(31) & tqmf_reg6(31) & tqmf_reg6(31) & tqmf_reg6(31) & tqmf_reg6(31) & tqmf_reg6(31) & tqmf_reg6(31) & tqmf_reg6(31) & tqmf_reg6(31) & tqmf_reg6(31) & tqmf_reg6) or
(repeat(64, sig_1262) and dec_del_bpl_reg1(31) & dec_del_bpl_reg1(31) & dec_del_bpl_reg1(31) & dec_del_bpl_reg1(31) & dec_del_bpl_reg1(31) & dec_del_bpl_reg1(31) & dec_del_bpl_reg1(31) & dec_del_bpl_reg1(31) & dec_del_bpl_reg1(31) & dec_del_bpl_reg1(31) & dec_del_bpl_reg1(31) & dec_del_bpl_reg1(31) & dec_del_bpl_reg1(31) & dec_del_bpl_reg1(31) & dec_del_bpl_reg1(31) & dec_del_bpl_reg1(31) & dec_del_bpl_reg1(31) & dec_del_bpl_reg1(31) & dec_del_bpl_reg1(31) & dec_del_bpl_reg1(31) & dec_del_bpl_reg1(31) & dec_del_bpl_reg1(31) & dec_del_bpl_reg1(31) & dec_del_bpl_reg1(31) & dec_del_bpl_reg1(31) & dec_del_bpl_reg1(31) & dec_del_bpl_reg1(31) & dec_del_bpl_reg1(31) & dec_del_bpl_reg1(31) & dec_del_bpl_reg1(31) & dec_del_bpl_reg1(31) & dec_del_bpl_reg1(31) & dec_del_bpl_reg1) or
(repeat(64, sig_1265) and dec_dlt(31) & dec_dlt(31) & dec_dlt(31) & dec_dlt(31) & dec_dlt(31) & dec_dlt(31) & dec_dlt(31) & dec_dlt(31) & dec_dlt(31) & dec_dlt(31) & dec_dlt(31) & dec_dlt(31) & dec_dlt(31) & dec_dlt(31) & dec_dlt(31) & dec_dlt(31) & dec_dlt(31) & dec_dlt(31) & dec_dlt(31) & dec_dlt(31) & dec_dlt(31) & dec_dlt(31) & dec_dlt(31) & dec_dlt(31) & dec_dlt(31) & dec_dlt(31) & dec_dlt(31) & dec_dlt(31) & dec_dlt(31) & dec_dlt(31) & dec_dlt(31) & dec_dlt(31) & dec_dlt) or
(repeat(64, sig_1270) and delay_bph_reg0(31) & delay_bph_reg0(31) & delay_bph_reg0(31) & delay_bph_reg0(31) & delay_bph_reg0(31) & delay_bph_reg0(31) & delay_bph_reg0(31) & delay_bph_reg0(31) & delay_bph_reg0(31) & delay_bph_reg0(31) & delay_bph_reg0(31) & delay_bph_reg0(31) & delay_bph_reg0(31) & delay_bph_reg0(31) & delay_bph_reg0(31) & delay_bph_reg0(31) & delay_bph_reg0(31) & delay_bph_reg0(31) & delay_bph_reg0(31) & delay_bph_reg0(31) & delay_bph_reg0(31) & delay_bph_reg0(31) & delay_bph_reg0(31) & delay_bph_reg0(31) & delay_bph_reg0(31) & delay_bph_reg0(31) & delay_bph_reg0(31) & delay_bph_reg0(31) & delay_bph_reg0(31) & delay_bph_reg0(31) & delay_bph_reg0(31) & delay_bph_reg0(31) & delay_bph_reg0) or
(repeat(64, sig_1175) and tqmf_reg22(31) & tqmf_reg22(31) & tqmf_reg22(31) & tqmf_reg22(31) & tqmf_reg22(31) & tqmf_reg22(31) & tqmf_reg22(31) & tqmf_reg22(31) & tqmf_reg22(31) & tqmf_reg22(31) & tqmf_reg22(31) & tqmf_reg22(31) & tqmf_reg22(31) & tqmf_reg22(31) & tqmf_reg22(31) & tqmf_reg22(31) & tqmf_reg22(31) & tqmf_reg22(31) & tqmf_reg22(31) & tqmf_reg22(31) & tqmf_reg22(31) & tqmf_reg22(31) & tqmf_reg22(31) & tqmf_reg22(31) & tqmf_reg22(31) & tqmf_reg22(31) & tqmf_reg22(31) & tqmf_reg22(31) & tqmf_reg22(31) & tqmf_reg22(31) & tqmf_reg22(31) & tqmf_reg22(31) & tqmf_reg22) or
(repeat(64, sig_1174) and dec_del_bpl_reg5(31) & dec_del_bpl_reg5(31) & dec_del_bpl_reg5(31) & dec_del_bpl_reg5(31) & dec_del_bpl_reg5(31) & dec_del_bpl_reg5(31) & dec_del_bpl_reg5(31) & dec_del_bpl_reg5(31) & dec_del_bpl_reg5(31) & dec_del_bpl_reg5(31) & dec_del_bpl_reg5(31) & dec_del_bpl_reg5(31) & dec_del_bpl_reg5(31) & dec_del_bpl_reg5(31) & dec_del_bpl_reg5(31) & dec_del_bpl_reg5(31) & dec_del_bpl_reg5(31) & dec_del_bpl_reg5(31) & dec_del_bpl_reg5(31) & dec_del_bpl_reg5(31) & dec_del_bpl_reg5(31) & dec_del_bpl_reg5(31) & dec_del_bpl_reg5(31) & dec_del_bpl_reg5(31) & dec_del_bpl_reg5(31) & dec_del_bpl_reg5(31) & dec_del_bpl_reg5(31) & dec_del_bpl_reg5(31) & dec_del_bpl_reg5(31) & dec_del_bpl_reg5(31) & dec_del_bpl_reg5(31) & dec_del_bpl_reg5(31) & dec_del_bpl_reg5) or
(repeat(64, sig_1160) and dec_del_bph_reg4(31) & dec_del_bph_reg4(31) & dec_del_bph_reg4(31) & dec_del_bph_reg4(31) & dec_del_bph_reg4(31) & dec_del_bph_reg4(31) & dec_del_bph_reg4(31) & dec_del_bph_reg4(31) & dec_del_bph_reg4(31) & dec_del_bph_reg4(31) & dec_del_bph_reg4(31) & dec_del_bph_reg4(31) & dec_del_bph_reg4(31) & dec_del_bph_reg4(31) & dec_del_bph_reg4(31) & dec_del_bph_reg4(31) & dec_del_bph_reg4(31) & dec_del_bph_reg4(31) & dec_del_bph_reg4(31) & dec_del_bph_reg4(31) & dec_del_bph_reg4(31) & dec_del_bph_reg4(31) & dec_del_bph_reg4(31) & dec_del_bph_reg4(31) & dec_del_bph_reg4(31) & dec_del_bph_reg4(31) & dec_del_bph_reg4(31) & dec_del_bph_reg4(31) & dec_del_bph_reg4(31) & dec_del_bph_reg4(31) & dec_del_bph_reg4(31) & dec_del_bph_reg4(31) & dec_del_bph_reg4) or
(repeat(64, sig_1153) and rh1(30) & rh1(30) & rh1(30) & rh1(30) & rh1(30) & rh1(30) & rh1(30) & rh1(30) & rh1(30) & rh1(30) & rh1(30) & rh1(30) & rh1(30) & rh1(30) & rh1(30) & rh1(30) & rh1(30) & rh1(30) & rh1(30) & rh1(30) & rh1(30) & rh1(30) & rh1(30) & rh1(30) & rh1(30) & rh1(30) & rh1(30) & rh1(30) & rh1(30) & rh1(30) & rh1(30) & rh1(30) & rh1 & '0') or
(repeat(64, sig_1146) and accumd_reg8(31) & accumd_reg8(31) & accumd_reg8(31) & accumd_reg8(31) & accumd_reg8(31) & accumd_reg8(31) & accumd_reg8(31) & accumd_reg8(31) & accumd_reg8(31) & accumd_reg8(31) & accumd_reg8(31) & accumd_reg8(31) & accumd_reg8(31) & accumd_reg8(31) & accumd_reg8(31) & accumd_reg8(31) & accumd_reg8(31) & accumd_reg8(31) & accumd_reg8(31) & accumd_reg8(31) & accumd_reg8(31) & accumd_reg8(31) & accumd_reg8(31) & accumd_reg8(31) & accumd_reg8(31) & accumd_reg8(31) & accumd_reg8(31) & accumd_reg8(31) & accumd_reg8(31) & accumd_reg8(31) & accumd_reg8(31) & accumd_reg8(31) & accumd_reg8) or
(repeat(64, sig_1136) and dec_plt(31) & dec_plt(31) & dec_plt(31) & dec_plt(31) & dec_plt(31) & dec_plt(31) & dec_plt(31) & dec_plt(31) & dec_plt(31) & dec_plt(31) & dec_plt(31) & dec_plt(31) & dec_plt(31) & dec_plt(31) & dec_plt(31) & dec_plt(31) & dec_plt(31) & dec_plt(31) & dec_plt(31) & dec_plt(31) & dec_plt(31) & dec_plt(31) & dec_plt(31) & dec_plt(31) & dec_plt(31) & dec_plt(31) & dec_plt(31) & dec_plt(31) & dec_plt(31) & dec_plt(31) & dec_plt(31) & dec_plt(31) & dec_plt) or
(repeat(64, sig_1125) and delay_bpl_reg5(31) & delay_bpl_reg5(31) & delay_bpl_reg5(31) & delay_bpl_reg5(31) & delay_bpl_reg5(31) & delay_bpl_reg5(31) & delay_bpl_reg5(31) & delay_bpl_reg5(31) & delay_bpl_reg5(31) & delay_bpl_reg5(31) & delay_bpl_reg5(31) & delay_bpl_reg5(31) & delay_bpl_reg5(31) & delay_bpl_reg5(31) & delay_bpl_reg5(31) & delay_bpl_reg5(31) & delay_bpl_reg5(31) & delay_bpl_reg5(31) & delay_bpl_reg5(31) & delay_bpl_reg5(31) & delay_bpl_reg5(31) & delay_bpl_reg5(31) & delay_bpl_reg5(31) & delay_bpl_reg5(31) & delay_bpl_reg5(31) & delay_bpl_reg5(31) & delay_bpl_reg5(31) & delay_bpl_reg5(31) & delay_bpl_reg5(31) & delay_bpl_reg5(31) & delay_bpl_reg5(31) & delay_bpl_reg5(31) & delay_bpl_reg5) or
(repeat(64, sig_1118) and accumd_reg6(31) & accumd_reg6(31) & accumd_reg6(31) & accumd_reg6(31) & accumd_reg6(31) & accumd_reg6(31) & accumd_reg6(31) & accumd_reg6(31) & accumd_reg6(31) & accumd_reg6(31) & accumd_reg6(31) & accumd_reg6(31) & accumd_reg6(31) & accumd_reg6(31) & accumd_reg6(31) & accumd_reg6(31) & accumd_reg6(31) & accumd_reg6(31) & accumd_reg6(31) & accumd_reg6(31) & accumd_reg6(31) & accumd_reg6(31) & accumd_reg6(31) & accumd_reg6(31) & accumd_reg6(31) & accumd_reg6(31) & accumd_reg6(31) & accumd_reg6(31) & accumd_reg6(31) & accumd_reg6(31) & accumd_reg6(31) & accumd_reg6(31) & accumd_reg6) or
(repeat(64, sig_1115) and delay_bph_reg5(31) & delay_bph_reg5(31) & delay_bph_reg5(31) & delay_bph_reg5(31) & delay_bph_reg5(31) & delay_bph_reg5(31) & delay_bph_reg5(31) & delay_bph_reg5(31) & delay_bph_reg5(31) & delay_bph_reg5(31) & delay_bph_reg5(31) & delay_bph_reg5(31) & delay_bph_reg5(31) & delay_bph_reg5(31) & delay_bph_reg5(31) & delay_bph_reg5(31) & delay_bph_reg5(31) & delay_bph_reg5(31) & delay_bph_reg5(31) & delay_bph_reg5(31) & delay_bph_reg5(31) & delay_bph_reg5(31) & delay_bph_reg5(31) & delay_bph_reg5(31) & delay_bph_reg5(31) & delay_bph_reg5(31) & delay_bph_reg5(31) & delay_bph_reg5(31) & delay_bph_reg5(31) & delay_bph_reg5(31) & delay_bph_reg5(31) & delay_bph_reg5(31) & delay_bph_reg5) or
(repeat(64, sig_1085) and dlt(31) & dlt(31) & dlt(31) & dlt(31) & dlt(31) & dlt(31) & dlt(31) & dlt(31) & dlt(31) & dlt(31) & dlt(31) & dlt(31) & dlt(31) & dlt(31) & dlt(31) & dlt(31) & dlt(31) & dlt(31) & dlt(31) & dlt(31) & dlt(31) & dlt(31) & dlt(31) & dlt(31) & dlt(31) & dlt(31) & dlt(31) & dlt(31) & dlt(31) & dlt(31) & dlt(31) & dlt(31) & dlt) or
(repeat(64, sig_1064) and accumc_reg5(31) & accumc_reg5(31) & accumc_reg5(31) & accumc_reg5(31) & accumc_reg5(31) & accumc_reg5(31) & accumc_reg5(31) & accumc_reg5(31) & accumc_reg5(31) & accumc_reg5(31) & accumc_reg5(31) & accumc_reg5(31) & accumc_reg5(31) & accumc_reg5(31) & accumc_reg5(31) & accumc_reg5(31) & accumc_reg5(31) & accumc_reg5(31) & accumc_reg5(31) & accumc_reg5(31) & accumc_reg5(31) & accumc_reg5(31) & accumc_reg5(31) & accumc_reg5(31) & accumc_reg5(31) & accumc_reg5(31) & accumc_reg5(31) & accumc_reg5(31) & accumc_reg5(31) & accumc_reg5(31) & accumc_reg5(31) & accumc_reg5(31) & accumc_reg5) or
(repeat(64, sig_1059) and accumd_reg4(31) & accumd_reg4(31) & accumd_reg4(31) & accumd_reg4(31) & accumd_reg4(31) & accumd_reg4(31) & accumd_reg4(31) & accumd_reg4(31) & accumd_reg4(31) & accumd_reg4(31) & accumd_reg4(31) & accumd_reg4(31) & accumd_reg4(31) & accumd_reg4(31) & accumd_reg4(31) & accumd_reg4(31) & accumd_reg4(31) & accumd_reg4(31) & accumd_reg4(31) & accumd_reg4(31) & accumd_reg4(31) & accumd_reg4(31) & accumd_reg4(31) & accumd_reg4(31) & accumd_reg4(31) & accumd_reg4(31) & accumd_reg4(31) & accumd_reg4(31) & accumd_reg4(31) & accumd_reg4(31) & accumd_reg4(31) & accumd_reg4(31) & accumd_reg4) or
(repeat(64, sig_1053) and dec_del_bpl_reg4(31) & dec_del_bpl_reg4(31) & dec_del_bpl_reg4(31) & dec_del_bpl_reg4(31) & dec_del_bpl_reg4(31) & dec_del_bpl_reg4(31) & dec_del_bpl_reg4(31) & dec_del_bpl_reg4(31) & dec_del_bpl_reg4(31) & dec_del_bpl_reg4(31) & dec_del_bpl_reg4(31) & dec_del_bpl_reg4(31) & dec_del_bpl_reg4(31) & dec_del_bpl_reg4(31) & dec_del_bpl_reg4(31) & dec_del_bpl_reg4(31) & dec_del_bpl_reg4(31) & dec_del_bpl_reg4(31) & dec_del_bpl_reg4(31) & dec_del_bpl_reg4(31) & dec_del_bpl_reg4(31) & dec_del_bpl_reg4(31) & dec_del_bpl_reg4(31) & dec_del_bpl_reg4(31) & dec_del_bpl_reg4(31) & dec_del_bpl_reg4(31) & dec_del_bpl_reg4(31) & dec_del_bpl_reg4(31) & dec_del_bpl_reg4(31) & dec_del_bpl_reg4(31) & dec_del_bpl_reg4(31) & dec_del_bpl_reg4(31) & dec_del_bpl_reg4) or
(repeat(64, sig_1048) and tqmf_reg14(31) & tqmf_reg14(31) & tqmf_reg14(31) & tqmf_reg14(31) & tqmf_reg14(31) & tqmf_reg14(31) & tqmf_reg14(31) & tqmf_reg14(31) & tqmf_reg14(31) & tqmf_reg14(31) & tqmf_reg14(31) & tqmf_reg14(31) & tqmf_reg14(31) & tqmf_reg14(31) & tqmf_reg14(31) & tqmf_reg14(31) & tqmf_reg14(31) & tqmf_reg14(31) & tqmf_reg14(31) & tqmf_reg14(31) & tqmf_reg14(31) & tqmf_reg14(31) & tqmf_reg14(31) & tqmf_reg14(31) & tqmf_reg14(31) & tqmf_reg14(31) & tqmf_reg14(31) & tqmf_reg14(31) & tqmf_reg14(31) & tqmf_reg14(31) & tqmf_reg14(31) & tqmf_reg14(31) & tqmf_reg14) or
(repeat(64, sig_1042) and delay_bpl_reg2(31) & delay_bpl_reg2(31) & delay_bpl_reg2(31) & delay_bpl_reg2(31) & delay_bpl_reg2(31) & delay_bpl_reg2(31) & delay_bpl_reg2(31) & delay_bpl_reg2(31) & delay_bpl_reg2(31) & delay_bpl_reg2(31) & delay_bpl_reg2(31) & delay_bpl_reg2(31) & delay_bpl_reg2(31) & delay_bpl_reg2(31) & delay_bpl_reg2(31) & delay_bpl_reg2(31) & delay_bpl_reg2(31) & delay_bpl_reg2(31) & delay_bpl_reg2(31) & delay_bpl_reg2(31) & delay_bpl_reg2(31) & delay_bpl_reg2(31) & delay_bpl_reg2(31) & delay_bpl_reg2(31) & delay_bpl_reg2(31) & delay_bpl_reg2(31) & delay_bpl_reg2(31) & delay_bpl_reg2(31) & delay_bpl_reg2(31) & delay_bpl_reg2(31) & delay_bpl_reg2(31) & delay_bpl_reg2(31) & delay_bpl_reg2) or
(repeat(64, sig_1040) and delay_bpl_reg3(31) & delay_bpl_reg3(31) & delay_bpl_reg3(31) & delay_bpl_reg3(31) & delay_bpl_reg3(31) & delay_bpl_reg3(31) & delay_bpl_reg3(31) & delay_bpl_reg3(31) & delay_bpl_reg3(31) & delay_bpl_reg3(31) & delay_bpl_reg3(31) & delay_bpl_reg3(31) & delay_bpl_reg3(31) & delay_bpl_reg3(31) & delay_bpl_reg3(31) & delay_bpl_reg3(31) & delay_bpl_reg3(31) & delay_bpl_reg3(31) & delay_bpl_reg3(31) & delay_bpl_reg3(31) & delay_bpl_reg3(31) & delay_bpl_reg3(31) & delay_bpl_reg3(31) & delay_bpl_reg3(31) & delay_bpl_reg3(31) & delay_bpl_reg3(31) & delay_bpl_reg3(31) & delay_bpl_reg3(31) & delay_bpl_reg3(31) & delay_bpl_reg3(31) & delay_bpl_reg3(31) & delay_bpl_reg3(31) & delay_bpl_reg3) or
(repeat(64, sig_1035) and tqmf_reg17(31) & tqmf_reg17(31) & tqmf_reg17(31) & tqmf_reg17(31) & tqmf_reg17(31) & tqmf_reg17(31) & tqmf_reg17(31) & tqmf_reg17(31) & tqmf_reg17(31) & tqmf_reg17(31) & tqmf_reg17(31) & tqmf_reg17(31) & tqmf_reg17(31) & tqmf_reg17(31) & tqmf_reg17(31) & tqmf_reg17(31) & tqmf_reg17(31) & tqmf_reg17(31) & tqmf_reg17(31) & tqmf_reg17(31) & tqmf_reg17(31) & tqmf_reg17(31) & tqmf_reg17(31) & tqmf_reg17(31) & tqmf_reg17(31) & tqmf_reg17(31) & tqmf_reg17(31) & tqmf_reg17(31) & tqmf_reg17(31) & tqmf_reg17(31) & tqmf_reg17(31) & tqmf_reg17(31) & tqmf_reg17) or
(repeat(64, sig_1027) and accumc_reg1(31) & accumc_reg1(31) & accumc_reg1(31) & accumc_reg1(31) & accumc_reg1(31) & accumc_reg1(31) & accumc_reg1(31) & accumc_reg1(31) & accumc_reg1(31) & accumc_reg1(31) & accumc_reg1(31) & accumc_reg1(31) & accumc_reg1(31) & accumc_reg1(31) & accumc_reg1(31) & accumc_reg1(31) & accumc_reg1(31) & accumc_reg1(31) & accumc_reg1(31) & accumc_reg1(31) & accumc_reg1(31) & accumc_reg1(31) & accumc_reg1(31) & accumc_reg1(31) & accumc_reg1(31) & accumc_reg1(31) & accumc_reg1(31) & accumc_reg1(31) & accumc_reg1(31) & accumc_reg1(31) & accumc_reg1(31) & accumc_reg1(31) & accumc_reg1) or
(repeat(64, sig_1023) and ph(31) & ph(31) & ph(31) & ph(31) & ph(31) & ph(31) & ph(31) & ph(31) & ph(31) & ph(31) & ph(31) & ph(31) & ph(31) & ph(31) & ph(31) & ph(31) & ph(31) & ph(31) & ph(31) & ph(31) & ph(31) & ph(31) & ph(31) & ph(31) & ph(31) & ph(31) & ph(31) & ph(31) & ph(31) & ph(31) & ph(31) & ph(31) & ph) or
(repeat(64, sig_1016) and tqmf_reg9(31) & tqmf_reg9(31) & tqmf_reg9(31) & tqmf_reg9(31) & tqmf_reg9(31) & tqmf_reg9(31) & tqmf_reg9(31) & tqmf_reg9(31) & tqmf_reg9(31) & tqmf_reg9(31) & tqmf_reg9(31) & tqmf_reg9(31) & tqmf_reg9(31) & tqmf_reg9(31) & tqmf_reg9(31) & tqmf_reg9(31) & tqmf_reg9(31) & tqmf_reg9(31) & tqmf_reg9(31) & tqmf_reg9(31) & tqmf_reg9(31) & tqmf_reg9(31) & tqmf_reg9(31) & tqmf_reg9(31) & tqmf_reg9(31) & tqmf_reg9(31) & tqmf_reg9(31) & tqmf_reg9(31) & tqmf_reg9(31) & tqmf_reg9(31) & tqmf_reg9(31) & tqmf_reg9(31) & tqmf_reg9) or
(repeat(64, sig_1008) and accumd_reg10(31) & accumd_reg10(31) & accumd_reg10(31) & accumd_reg10(31) & accumd_reg10(31) & accumd_reg10(31) & accumd_reg10(31) & accumd_reg10(31) & accumd_reg10(31) & accumd_reg10(31) & accumd_reg10(31) & accumd_reg10(31) & accumd_reg10(31) & accumd_reg10(31) & accumd_reg10(31) & accumd_reg10(31) & accumd_reg10(31) & accumd_reg10(31) & accumd_reg10(31) & accumd_reg10(31) & accumd_reg10(31) & accumd_reg10(31) & accumd_reg10(31) & accumd_reg10(31) & accumd_reg10(31) & accumd_reg10(31) & accumd_reg10(31) & accumd_reg10(31) & accumd_reg10(31) & accumd_reg10(31) & accumd_reg10(31) & accumd_reg10(31) & accumd_reg10) or
(repeat(64, sig_997) and ah1(31) & ah1(31) & ah1(31) & ah1(31) & ah1(31) & ah1(31) & ah1(31) & ah1(31) & ah1(31) & ah1(31) & ah1(31) & ah1(31) & ah1(31) & ah1(31) & ah1(31) & ah1(31) & ah1(31) & ah1(31) & ah1(31) & ah1(31) & ah1(31) & ah1(31) & ah1(31) & ah1(31) & ah1(31) & ah1(31) & ah1(31) & ah1(31) & ah1(31) & ah1(31) & ah1(31) & ah1(31) & ah1) or
(repeat(64, sig_973) and dec_dh(31) & dec_dh(31) & dec_dh(31) & dec_dh(31) & dec_dh(31) & dec_dh(31) & dec_dh(31) & dec_dh(31) & dec_dh(31) & dec_dh(31) & dec_dh(31) & dec_dh(31) & dec_dh(31) & dec_dh(31) & dec_dh(31) & dec_dh(31) & dec_dh(31) & dec_dh(31) & dec_dh(31) & dec_dh(31) & dec_dh(31) & dec_dh(31) & dec_dh(31) & dec_dh(31) & dec_dh(31) & dec_dh(31) & dec_dh(31) & dec_dh(31) & dec_dh(31) & dec_dh(31) & dec_dh(31) & dec_dh(31) & dec_dh) or
(repeat(64, sig_969) and tqmf_reg18(31) & tqmf_reg18(31) & tqmf_reg18(31) & tqmf_reg18(31) & tqmf_reg18(31) & tqmf_reg18(31) & tqmf_reg18(31) & tqmf_reg18(31) & tqmf_reg18(31) & tqmf_reg18(31) & tqmf_reg18(31) & tqmf_reg18(31) & tqmf_reg18(31) & tqmf_reg18(31) & tqmf_reg18(31) & tqmf_reg18(31) & tqmf_reg18(31) & tqmf_reg18(31) & tqmf_reg18(31) & tqmf_reg18(31) & tqmf_reg18(31) & tqmf_reg18(31) & tqmf_reg18(31) & tqmf_reg18(31) & tqmf_reg18(31) & tqmf_reg18(31) & tqmf_reg18(31) & tqmf_reg18(31) & tqmf_reg18(31) & tqmf_reg18(31) & tqmf_reg18(31) & tqmf_reg18(31) & tqmf_reg18) or
(repeat(64, sig_961) and accumd_reg0(31) & accumd_reg0(31) & accumd_reg0(31) & accumd_reg0(31) & accumd_reg0(31) & accumd_reg0(31) & accumd_reg0(31) & accumd_reg0(31) & accumd_reg0(31) & accumd_reg0(31) & accumd_reg0(31) & accumd_reg0(31) & accumd_reg0(31) & accumd_reg0(31) & accumd_reg0(31) & accumd_reg0(31) & accumd_reg0(31) & accumd_reg0(31) & accumd_reg0(31) & accumd_reg0(31) & accumd_reg0(31) & accumd_reg0(31) & accumd_reg0(31) & accumd_reg0(31) & accumd_reg0(31) & accumd_reg0(31) & accumd_reg0(31) & accumd_reg0(31) & accumd_reg0(31) & accumd_reg0(31) & accumd_reg0(31) & accumd_reg0(31) & accumd_reg0) or
(repeat(64, sig_955) and xd(31) & xd(31) & xd(31) & xd(31) & xd(31) & xd(31) & xd(31) & xd(31) & xd(31) & xd(31) & xd(31) & xd(31) & xd(31) & xd(31) & xd(31) & xd(31) & xd(31) & xd(31) & xd(31) & xd(31) & xd(31) & xd(31) & xd(31) & xd(31) & xd(31) & xd(31) & xd(31) & xd(31) & xd(31) & xd(31) & xd(31) & xd(31) & xd) or
(repeat(64, sig_954) and dec_ph(31) & dec_ph(31) & dec_ph(31) & dec_ph(31) & dec_ph(31) & dec_ph(31) & dec_ph(31) & dec_ph(31) & dec_ph(31) & dec_ph(31) & dec_ph(31) & dec_ph(31) & dec_ph(31) & dec_ph(31) & dec_ph(31) & dec_ph(31) & dec_ph(31) & dec_ph(31) & dec_ph(31) & dec_ph(31) & dec_ph(31) & dec_ph(31) & dec_ph(31) & dec_ph(31) & dec_ph(31) & dec_ph(31) & dec_ph(31) & dec_ph(31) & dec_ph(31) & dec_ph(31) & dec_ph(31) & dec_ph(31) & dec_ph) or
(repeat(64, sig_931) and accumc_reg7(31) & accumc_reg7(31) & accumc_reg7(31) & accumc_reg7(31) & accumc_reg7(31) & accumc_reg7(31) & accumc_reg7(31) & accumc_reg7(31) & accumc_reg7(31) & accumc_reg7(31) & accumc_reg7(31) & accumc_reg7(31) & accumc_reg7(31) & accumc_reg7(31) & accumc_reg7(31) & accumc_reg7(31) & accumc_reg7(31) & accumc_reg7(31) & accumc_reg7(31) & accumc_reg7(31) & accumc_reg7(31) & accumc_reg7(31) & accumc_reg7(31) & accumc_reg7(31) & accumc_reg7(31) & accumc_reg7(31) & accumc_reg7(31) & accumc_reg7(31) & accumc_reg7(31) & accumc_reg7(31) & accumc_reg7(31) & accumc_reg7(31) & accumc_reg7) or
(repeat(64, sig_927) and rh2(30) & rh2(30) & rh2(30) & rh2(30) & rh2(30) & rh2(30) & rh2(30) & rh2(30) & rh2(30) & rh2(30) & rh2(30) & rh2(30) & rh2(30) & rh2(30) & rh2(30) & rh2(30) & rh2(30) & rh2(30) & rh2(30) & rh2(30) & rh2(30) & rh2(30) & rh2(30) & rh2(30) & rh2(30) & rh2(30) & rh2(30) & rh2(30) & rh2(30) & rh2(30) & rh2(30) & rh2(30) & rh2 & '0') or
(repeat(64, sig_923) and delay_bpl_reg1(31) & delay_bpl_reg1(31) & delay_bpl_reg1(31) & delay_bpl_reg1(31) & delay_bpl_reg1(31) & delay_bpl_reg1(31) & delay_bpl_reg1(31) & delay_bpl_reg1(31) & delay_bpl_reg1(31) & delay_bpl_reg1(31) & delay_bpl_reg1(31) & delay_bpl_reg1(31) & delay_bpl_reg1(31) & delay_bpl_reg1(31) & delay_bpl_reg1(31) & delay_bpl_reg1(31) & delay_bpl_reg1(31) & delay_bpl_reg1(31) & delay_bpl_reg1(31) & delay_bpl_reg1(31) & delay_bpl_reg1(31) & delay_bpl_reg1(31) & delay_bpl_reg1(31) & delay_bpl_reg1(31) & delay_bpl_reg1(31) & delay_bpl_reg1(31) & delay_bpl_reg1(31) & delay_bpl_reg1(31) & delay_bpl_reg1(31) & delay_bpl_reg1(31) & delay_bpl_reg1(31) & delay_bpl_reg1(31) & delay_bpl_reg1) or
(repeat(64, sig_922) and delay_bpl_reg0(31) & delay_bpl_reg0(31) & delay_bpl_reg0(31) & delay_bpl_reg0(31) & delay_bpl_reg0(31) & delay_bpl_reg0(31) & delay_bpl_reg0(31) & delay_bpl_reg0(31) & delay_bpl_reg0(31) & delay_bpl_reg0(31) & delay_bpl_reg0(31) & delay_bpl_reg0(31) & delay_bpl_reg0(31) & delay_bpl_reg0(31) & delay_bpl_reg0(31) & delay_bpl_reg0(31) & delay_bpl_reg0(31) & delay_bpl_reg0(31) & delay_bpl_reg0(31) & delay_bpl_reg0(31) & delay_bpl_reg0(31) & delay_bpl_reg0(31) & delay_bpl_reg0(31) & delay_bpl_reg0(31) & delay_bpl_reg0(31) & delay_bpl_reg0(31) & delay_bpl_reg0(31) & delay_bpl_reg0(31) & delay_bpl_reg0(31) & delay_bpl_reg0(31) & delay_bpl_reg0(31) & delay_bpl_reg0(31) & delay_bpl_reg0) or
(repeat(64, sig_921) and tqmf_reg13(31) & tqmf_reg13(31) & tqmf_reg13(31) & tqmf_reg13(31) & tqmf_reg13(31) & tqmf_reg13(31) & tqmf_reg13(31) & tqmf_reg13(31) & tqmf_reg13(31) & tqmf_reg13(31) & tqmf_reg13(31) & tqmf_reg13(31) & tqmf_reg13(31) & tqmf_reg13(31) & tqmf_reg13(31) & tqmf_reg13(31) & tqmf_reg13(31) & tqmf_reg13(31) & tqmf_reg13(31) & tqmf_reg13(31) & tqmf_reg13(31) & tqmf_reg13(31) & tqmf_reg13(31) & tqmf_reg13(31) & tqmf_reg13(31) & tqmf_reg13(31) & tqmf_reg13(31) & tqmf_reg13(31) & tqmf_reg13(31) & tqmf_reg13(31) & tqmf_reg13(31) & tqmf_reg13(31) & tqmf_reg13) or
(repeat(64, sig_914) and dec_rlt2(30) & dec_rlt2(30) & dec_rlt2(30) & dec_rlt2(30) & dec_rlt2(30) & dec_rlt2(30) & dec_rlt2(30) & dec_rlt2(30) & dec_rlt2(30) & dec_rlt2(30) & dec_rlt2(30) & dec_rlt2(30) & dec_rlt2(30) & dec_rlt2(30) & dec_rlt2(30) & dec_rlt2(30) & dec_rlt2(30) & dec_rlt2(30) & dec_rlt2(30) & dec_rlt2(30) & dec_rlt2(30) & dec_rlt2(30) & dec_rlt2(30) & dec_rlt2(30) & dec_rlt2(30) & dec_rlt2(30) & dec_rlt2(30) & dec_rlt2(30) & dec_rlt2(30) & dec_rlt2(30) & dec_rlt2(30) & dec_rlt2(30) & dec_rlt2 & '0') or
(repeat(64, sig_911) and dec_rlt1(30) & dec_rlt1(30) & dec_rlt1(30) & dec_rlt1(30) & dec_rlt1(30) & dec_rlt1(30) & dec_rlt1(30) & dec_rlt1(30) & dec_rlt1(30) & dec_rlt1(30) & dec_rlt1(30) & dec_rlt1(30) & dec_rlt1(30) & dec_rlt1(30) & dec_rlt1(30) & dec_rlt1(30) & dec_rlt1(30) & dec_rlt1(30) & dec_rlt1(30) & dec_rlt1(30) & dec_rlt1(30) & dec_rlt1(30) & dec_rlt1(30) & dec_rlt1(30) & dec_rlt1(30) & dec_rlt1(30) & dec_rlt1(30) & dec_rlt1(30) & dec_rlt1(30) & dec_rlt1(30) & dec_rlt1(30) & dec_rlt1(30) & dec_rlt1 & '0') or
(repeat(64, sig_887) and accumc_reg9(31) & accumc_reg9(31) & accumc_reg9(31) & accumc_reg9(31) & accumc_reg9(31) & accumc_reg9(31) & accumc_reg9(31) & accumc_reg9(31) & accumc_reg9(31) & accumc_reg9(31) & accumc_reg9(31) & accumc_reg9(31) & accumc_reg9(31) & accumc_reg9(31) & accumc_reg9(31) & accumc_reg9(31) & accumc_reg9(31) & accumc_reg9(31) & accumc_reg9(31) & accumc_reg9(31) & accumc_reg9(31) & accumc_reg9(31) & accumc_reg9(31) & accumc_reg9(31) & accumc_reg9(31) & accumc_reg9(31) & accumc_reg9(31) & accumc_reg9(31) & accumc_reg9(31) & accumc_reg9(31) & accumc_reg9(31) & accumc_reg9(31) & accumc_reg9) or
(repeat(64, sig_885) and accumc_reg3(31) & accumc_reg3(31) & accumc_reg3(31) & accumc_reg3(31) & accumc_reg3(31) & accumc_reg3(31) & accumc_reg3(31) & accumc_reg3(31) & accumc_reg3(31) & accumc_reg3(31) & accumc_reg3(31) & accumc_reg3(31) & accumc_reg3(31) & accumc_reg3(31) & accumc_reg3(31) & accumc_reg3(31) & accumc_reg3(31) & accumc_reg3(31) & accumc_reg3(31) & accumc_reg3(31) & accumc_reg3(31) & accumc_reg3(31) & accumc_reg3(31) & accumc_reg3(31) & accumc_reg3(31) & accumc_reg3(31) & accumc_reg3(31) & accumc_reg3(31) & accumc_reg3(31) & accumc_reg3(31) & accumc_reg3(31) & accumc_reg3(31) & accumc_reg3) or
(repeat(64, sig_872) and dec_del_bpl_reg0(31) & dec_del_bpl_reg0(31) & dec_del_bpl_reg0(31) & dec_del_bpl_reg0(31) & dec_del_bpl_reg0(31) & dec_del_bpl_reg0(31) & dec_del_bpl_reg0(31) & dec_del_bpl_reg0(31) & dec_del_bpl_reg0(31) & dec_del_bpl_reg0(31) & dec_del_bpl_reg0(31) & dec_del_bpl_reg0(31) & dec_del_bpl_reg0(31) & dec_del_bpl_reg0(31) & dec_del_bpl_reg0(31) & dec_del_bpl_reg0(31) & dec_del_bpl_reg0(31) & dec_del_bpl_reg0(31) & dec_del_bpl_reg0(31) & dec_del_bpl_reg0(31) & dec_del_bpl_reg0(31) & dec_del_bpl_reg0(31) & dec_del_bpl_reg0(31) & dec_del_bpl_reg0(31) & dec_del_bpl_reg0(31) & dec_del_bpl_reg0(31) & dec_del_bpl_reg0(31) & dec_del_bpl_reg0(31) & dec_del_bpl_reg0(31) & dec_del_bpl_reg0(31) & dec_del_bpl_reg0(31) & dec_del_bpl_reg0(31) & dec_del_bpl_reg0) or
(repeat(64, sig_868) and tqmf_reg1(31) & tqmf_reg1(31) & tqmf_reg1(31) & tqmf_reg1(31) & tqmf_reg1(31) & tqmf_reg1(31) & tqmf_reg1(31) & tqmf_reg1(31) & tqmf_reg1(31) & tqmf_reg1(31) & tqmf_reg1(31) & tqmf_reg1(31) & tqmf_reg1(31) & tqmf_reg1(31) & tqmf_reg1(31) & tqmf_reg1(31) & tqmf_reg1(31) & tqmf_reg1(31) & tqmf_reg1(31) & tqmf_reg1(31) & tqmf_reg1(31) & tqmf_reg1(31) & tqmf_reg1(31) & tqmf_reg1(31) & tqmf_reg1(31) & tqmf_reg1(31) & tqmf_reg1(31) & tqmf_reg1(31) & tqmf_reg1(31) & tqmf_reg1(31) & tqmf_reg1(31) & tqmf_reg1(31) & tqmf_reg1) or
(repeat(64, sig_866) and tqmf_reg5(31) & tqmf_reg5(31) & tqmf_reg5(31) & tqmf_reg5(31) & tqmf_reg5(31) & tqmf_reg5(31) & tqmf_reg5(31) & tqmf_reg5(31) & tqmf_reg5(31) & tqmf_reg5(31) & tqmf_reg5(31) & tqmf_reg5(31) & tqmf_reg5(31) & tqmf_reg5(31) & tqmf_reg5(31) & tqmf_reg5(31) & tqmf_reg5(31) & tqmf_reg5(31) & tqmf_reg5(31) & tqmf_reg5(31) & tqmf_reg5(31) & tqmf_reg5(31) & tqmf_reg5(31) & tqmf_reg5(31) & tqmf_reg5(31) & tqmf_reg5(31) & tqmf_reg5(31) & tqmf_reg5(31) & tqmf_reg5(31) & tqmf_reg5(31) & tqmf_reg5(31) & tqmf_reg5(31) & tqmf_reg5) or
(repeat(64, sig_865) and accumd_reg2(31) & accumd_reg2(31) & accumd_reg2(31) & accumd_reg2(31) & accumd_reg2(31) & accumd_reg2(31) & accumd_reg2(31) & accumd_reg2(31) & accumd_reg2(31) & accumd_reg2(31) & accumd_reg2(31) & accumd_reg2(31) & accumd_reg2(31) & accumd_reg2(31) & accumd_reg2(31) & accumd_reg2(31) & accumd_reg2(31) & accumd_reg2(31) & accumd_reg2(31) & accumd_reg2(31) & accumd_reg2(31) & accumd_reg2(31) & accumd_reg2(31) & accumd_reg2(31) & accumd_reg2(31) & accumd_reg2(31) & accumd_reg2(31) & accumd_reg2(31) & accumd_reg2(31) & accumd_reg2(31) & accumd_reg2(31) & accumd_reg2(31) & accumd_reg2) or
(repeat(64, sig_864) and delay_bph_reg1(31) & delay_bph_reg1(31) & delay_bph_reg1(31) & delay_bph_reg1(31) & delay_bph_reg1(31) & delay_bph_reg1(31) & delay_bph_reg1(31) & delay_bph_reg1(31) & delay_bph_reg1(31) & delay_bph_reg1(31) & delay_bph_reg1(31) & delay_bph_reg1(31) & delay_bph_reg1(31) & delay_bph_reg1(31) & delay_bph_reg1(31) & delay_bph_reg1(31) & delay_bph_reg1(31) & delay_bph_reg1(31) & delay_bph_reg1(31) & delay_bph_reg1(31) & delay_bph_reg1(31) & delay_bph_reg1(31) & delay_bph_reg1(31) & delay_bph_reg1(31) & delay_bph_reg1(31) & delay_bph_reg1(31) & delay_bph_reg1(31) & delay_bph_reg1(31) & delay_bph_reg1(31) & delay_bph_reg1(31) & delay_bph_reg1(31) & delay_bph_reg1(31) & delay_bph_reg1) or
(repeat(64, sig_861) and dec_del_bph_reg2(31) & dec_del_bph_reg2(31) & dec_del_bph_reg2(31) & dec_del_bph_reg2(31) & dec_del_bph_reg2(31) & dec_del_bph_reg2(31) & dec_del_bph_reg2(31) & dec_del_bph_reg2(31) & dec_del_bph_reg2(31) & dec_del_bph_reg2(31) & dec_del_bph_reg2(31) & dec_del_bph_reg2(31) & dec_del_bph_reg2(31) & dec_del_bph_reg2(31) & dec_del_bph_reg2(31) & dec_del_bph_reg2(31) & dec_del_bph_reg2(31) & dec_del_bph_reg2(31) & dec_del_bph_reg2(31) & dec_del_bph_reg2(31) & dec_del_bph_reg2(31) & dec_del_bph_reg2(31) & dec_del_bph_reg2(31) & dec_del_bph_reg2(31) & dec_del_bph_reg2(31) & dec_del_bph_reg2(31) & dec_del_bph_reg2(31) & dec_del_bph_reg2(31) & dec_del_bph_reg2(31) & dec_del_bph_reg2(31) & dec_del_bph_reg2(31) & dec_del_bph_reg2(31) & dec_del_bph_reg2) or
(repeat(64, sig_1200) and dec_del_bph_reg0(31) & dec_del_bph_reg0(31) & dec_del_bph_reg0(31) & dec_del_bph_reg0(31) & dec_del_bph_reg0(31) & dec_del_bph_reg0(31) & dec_del_bph_reg0(31) & dec_del_bph_reg0(31) & dec_del_bph_reg0(31) & dec_del_bph_reg0(31) & dec_del_bph_reg0(31) & dec_del_bph_reg0(31) & dec_del_bph_reg0(31) & dec_del_bph_reg0(31) & dec_del_bph_reg0(31) & dec_del_bph_reg0(31) & dec_del_bph_reg0(31) & dec_del_bph_reg0(31) & dec_del_bph_reg0(31) & dec_del_bph_reg0(31) & dec_del_bph_reg0(31) & dec_del_bph_reg0(31) & dec_del_bph_reg0(31) & dec_del_bph_reg0(31) & dec_del_bph_reg0(31) & dec_del_bph_reg0(31) & dec_del_bph_reg0(31) & dec_del_bph_reg0(31) & dec_del_bph_reg0(31) & dec_del_bph_reg0(31) & dec_del_bph_reg0(31) & dec_del_bph_reg0(31) & dec_del_bph_reg0);
-- Behaviour of component 'mux_398' model 'mux'
mux_398 <=
(repeat(32, sig_1147) and "00000000000000000000000000110000") or
(repeat(32, sig_1133) and dec_plt1) or
(repeat(32, sig_1153) and ah1) or
(repeat(32, sig_1242) and "11111111111111111111111111010100") or
(repeat(32, sig_1196) and "00000000000000000000000010000000") or
(repeat(32, sig_1254) and "00000000000000000000111011011100") or
(repeat(32, sig_1268) and "00000000000000000000000000000000") or
(repeat(32, sig_1271) and "00000000000000000000000011111111") or
(repeat(32, sig_1119) and "11111111111111111111110010111000") or
(repeat(32, sig_1086) and "00000000000000000000000000000000") or
(repeat(32, sig_1065) and "00000000000000000011110010010000") or
(repeat(32, sig_1049) and "11111111111111111111001101101100") or
(repeat(32, sig_1036) and "00000000000000000000000000000000") or
(repeat(32, sig_1023) and ph1) or
(repeat(32, sig_1017) and "00000000000000000000000000000000") or
(repeat(32, sig_1007) and "00000000000000000000000000001100") or
(repeat(32, sig_1000) and "00000000000000000000000000000000") or
(repeat(32, sig_974) and "00000000000000000000000000000000") or
(repeat(32, sig_970) and "11111111111111111111110110010000") or
(repeat(32, sig_960) and "00000000000000000000000011010100") or
(repeat(32, sig_954) and dec_ph1) or
(repeat(32, sig_930) and "00000000000000000000010110101000") or
(repeat(32, sig_927) and ah2) or
(repeat(32, sig_914) and dec_al2) or
(repeat(32, sig_911) and dec_al1) or
(repeat(32, sig_895) and dec_plt2) or
(repeat(32, sig_890) and "00000000000000000000000000000000") or
(repeat(32, sig_871) and "00000000000000000000000000000000") or
(repeat(32, sig_863) and "00000000000000000000000000000000") or
(repeat(32, sig_862) and dec_del_dhx_reg1);
-- Behaviour of component 'mux_399' model 'mux'
mux_399 <=
(repeat(64, sig_1257) and dec_ph(31) & dec_ph(31) & dec_ph(31) & dec_ph(31) & dec_ph(31) & dec_ph(31) & dec_ph(31) & dec_ph(31) & dec_ph(31) & dec_ph(31) & dec_ph(31) & dec_ph(31) & dec_ph(31) & dec_ph(31) & dec_ph(31) & dec_ph(31) & dec_ph(31) & dec_ph(31) & dec_ph(31) & dec_ph(31) & dec_ph(31) & dec_ph(31) & dec_ph(31) & dec_ph(31) & dec_ph(31) & dec_ph(31) & dec_ph(31) & dec_ph(31) & dec_ph(31) & dec_ph(31) & dec_ph(31) & dec_ph(31) & dec_ph) or
(repeat(64, sig_1253) and tqmf_reg11(31) & tqmf_reg11(31) & tqmf_reg11(31) & tqmf_reg11(31) & tqmf_reg11(31) & tqmf_reg11(31) & tqmf_reg11(31) & tqmf_reg11(31) & tqmf_reg11(31) & tqmf_reg11(31) & tqmf_reg11(31) & tqmf_reg11(31) & tqmf_reg11(31) & tqmf_reg11(31) & tqmf_reg11(31) & tqmf_reg11(31) & tqmf_reg11(31) & tqmf_reg11(31) & tqmf_reg11(31) & tqmf_reg11(31) & tqmf_reg11(31) & tqmf_reg11(31) & tqmf_reg11(31) & tqmf_reg11(31) & tqmf_reg11(31) & tqmf_reg11(31) & tqmf_reg11(31) & tqmf_reg11(31) & tqmf_reg11(31) & tqmf_reg11(31) & tqmf_reg11(31) & tqmf_reg11(31) & tqmf_reg11) or
(repeat(64, sig_1277) and delay_bph_reg2(31) & delay_bph_reg2(31) & delay_bph_reg2(31) & delay_bph_reg2(31) & delay_bph_reg2(31) & delay_bph_reg2(31) & delay_bph_reg2(31) & delay_bph_reg2(31) & delay_bph_reg2(31) & delay_bph_reg2(31) & delay_bph_reg2(31) & delay_bph_reg2(31) & delay_bph_reg2(31) & delay_bph_reg2(31) & delay_bph_reg2(31) & delay_bph_reg2(31) & delay_bph_reg2(31) & delay_bph_reg2(31) & delay_bph_reg2(31) & delay_bph_reg2(31) & delay_bph_reg2(31) & delay_bph_reg2(31) & delay_bph_reg2(31) & delay_bph_reg2(31) & delay_bph_reg2(31) & delay_bph_reg2(31) & delay_bph_reg2(31) & delay_bph_reg2(31) & delay_bph_reg2(31) & delay_bph_reg2(31) & delay_bph_reg2(31) & delay_bph_reg2(31) & delay_bph_reg2) or
(repeat(64, sig_1261) and tqmf_reg20(31) & tqmf_reg20(31) & tqmf_reg20(31) & tqmf_reg20(31) & tqmf_reg20(31) & tqmf_reg20(31) & tqmf_reg20(31) & tqmf_reg20(31) & tqmf_reg20(31) & tqmf_reg20(31) & tqmf_reg20(31) & tqmf_reg20(31) & tqmf_reg20(31) & tqmf_reg20(31) & tqmf_reg20(31) & tqmf_reg20(31) & tqmf_reg20(31) & tqmf_reg20(31) & tqmf_reg20(31) & tqmf_reg20(31) & tqmf_reg20(31) & tqmf_reg20(31) & tqmf_reg20(31) & tqmf_reg20(31) & tqmf_reg20(31) & tqmf_reg20(31) & tqmf_reg20(31) & tqmf_reg20(31) & tqmf_reg20(31) & tqmf_reg20(31) & tqmf_reg20(31) & tqmf_reg20(31) & tqmf_reg20) or
(repeat(64, sig_1241) and tqmf_reg3(31) & tqmf_reg3(31) & tqmf_reg3(31) & tqmf_reg3(31) & tqmf_reg3(31) & tqmf_reg3(31) & tqmf_reg3(31) & tqmf_reg3(31) & tqmf_reg3(31) & tqmf_reg3(31) & tqmf_reg3(31) & tqmf_reg3(31) & tqmf_reg3(31) & tqmf_reg3(31) & tqmf_reg3(31) & tqmf_reg3(31) & tqmf_reg3(31) & tqmf_reg3(31) & tqmf_reg3(31) & tqmf_reg3(31) & tqmf_reg3(31) & tqmf_reg3(31) & tqmf_reg3(31) & tqmf_reg3(31) & tqmf_reg3(31) & tqmf_reg3(31) & tqmf_reg3(31) & tqmf_reg3(31) & tqmf_reg3(31) & tqmf_reg3(31) & tqmf_reg3(31) & tqmf_reg3(31) & tqmf_reg3) or
(repeat(64, sig_1195) and tqmf_reg7(31) & tqmf_reg7(31) & tqmf_reg7(31) & tqmf_reg7(31) & tqmf_reg7(31) & tqmf_reg7(31) & tqmf_reg7(31) & tqmf_reg7(31) & tqmf_reg7(31) & tqmf_reg7(31) & tqmf_reg7(31) & tqmf_reg7(31) & tqmf_reg7(31) & tqmf_reg7(31) & tqmf_reg7(31) & tqmf_reg7(31) & tqmf_reg7(31) & tqmf_reg7(31) & tqmf_reg7(31) & tqmf_reg7(31) & tqmf_reg7(31) & tqmf_reg7(31) & tqmf_reg7(31) & tqmf_reg7(31) & tqmf_reg7(31) & tqmf_reg7(31) & tqmf_reg7(31) & tqmf_reg7(31) & tqmf_reg7(31) & tqmf_reg7(31) & tqmf_reg7(31) & tqmf_reg7(31) & tqmf_reg7) or
(repeat(64, sig_1263) and dec_dlt(31) & dec_dlt(31) & dec_dlt(31) & dec_dlt(31) & dec_dlt(31) & dec_dlt(31) & dec_dlt(31) & dec_dlt(31) & dec_dlt(31) & dec_dlt(31) & dec_dlt(31) & dec_dlt(31) & dec_dlt(31) & dec_dlt(31) & dec_dlt(31) & dec_dlt(31) & dec_dlt(31) & dec_dlt(31) & dec_dlt(31) & dec_dlt(31) & dec_dlt(31) & dec_dlt(31) & dec_dlt(31) & dec_dlt(31) & dec_dlt(31) & dec_dlt(31) & dec_dlt(31) & dec_dlt(31) & dec_dlt(31) & dec_dlt(31) & dec_dlt(31) & dec_dlt(31) & dec_dlt) or
(repeat(64, sig_1266) and dec_del_bpl_reg3(31) & dec_del_bpl_reg3(31) & dec_del_bpl_reg3(31) & dec_del_bpl_reg3(31) & dec_del_bpl_reg3(31) & dec_del_bpl_reg3(31) & dec_del_bpl_reg3(31) & dec_del_bpl_reg3(31) & dec_del_bpl_reg3(31) & dec_del_bpl_reg3(31) & dec_del_bpl_reg3(31) & dec_del_bpl_reg3(31) & dec_del_bpl_reg3(31) & dec_del_bpl_reg3(31) & dec_del_bpl_reg3(31) & dec_del_bpl_reg3(31) & dec_del_bpl_reg3(31) & dec_del_bpl_reg3(31) & dec_del_bpl_reg3(31) & dec_del_bpl_reg3(31) & dec_del_bpl_reg3(31) & dec_del_bpl_reg3(31) & dec_del_bpl_reg3(31) & dec_del_bpl_reg3(31) & dec_del_bpl_reg3(31) & dec_del_bpl_reg3(31) & dec_del_bpl_reg3(31) & dec_del_bpl_reg3(31) & dec_del_bpl_reg3(31) & dec_del_bpl_reg3(31) & dec_del_bpl_reg3(31) & dec_del_bpl_reg3(31) & dec_del_bpl_reg3) or
(repeat(64, sig_1272) and dh(31) & dh(31) & dh(31) & dh(31) & dh(31) & dh(31) & dh(31) & dh(31) & dh(31) & dh(31) & dh(31) & dh(31) & dh(31) & dh(31) & dh(31) & dh(31) & dh(31) & dh(31) & dh(31) & dh(31) & dh(31) & dh(31) & dh(31) & dh(31) & dh(31) & dh(31) & dh(31) & dh(31) & dh(31) & dh(31) & dh(31) & dh(31) & dh) or
(repeat(64, sig_1175) and tqmf_reg23(31) & tqmf_reg23(31) & tqmf_reg23(31) & tqmf_reg23(31) & tqmf_reg23(31) & tqmf_reg23(31) & tqmf_reg23(31) & tqmf_reg23(31) & tqmf_reg23(31) & tqmf_reg23(31) & tqmf_reg23(31) & tqmf_reg23(31) & tqmf_reg23(31) & tqmf_reg23(31) & tqmf_reg23(31) & tqmf_reg23(31) & tqmf_reg23(31) & tqmf_reg23(31) & tqmf_reg23(31) & tqmf_reg23(31) & tqmf_reg23(31) & tqmf_reg23(31) & tqmf_reg23(31) & tqmf_reg23(31) & tqmf_reg23(31) & tqmf_reg23(31) & tqmf_reg23(31) & tqmf_reg23(31) & tqmf_reg23(31) & tqmf_reg23(31) & tqmf_reg23(31) & tqmf_reg23(31) & tqmf_reg23) or
(repeat(64, sig_1162) and dec_dh(31) & dec_dh(31) & dec_dh(31) & dec_dh(31) & dec_dh(31) & dec_dh(31) & dec_dh(31) & dec_dh(31) & dec_dh(31) & dec_dh(31) & dec_dh(31) & dec_dh(31) & dec_dh(31) & dec_dh(31) & dec_dh(31) & dec_dh(31) & dec_dh(31) & dec_dh(31) & dec_dh(31) & dec_dh(31) & dec_dh(31) & dec_dh(31) & dec_dh(31) & dec_dh(31) & dec_dh(31) & dec_dh(31) & dec_dh(31) & dec_dh(31) & dec_dh(31) & dec_dh(31) & dec_dh(31) & dec_dh(31) & dec_dh) or
(repeat(64, sig_1159) and sig_1312(31) & sig_1312(31) & sig_1312(31) & sig_1312(31) & sig_1312(31) & sig_1312(31) & sig_1312(31) & sig_1312(31) & sig_1312(31) & sig_1312(31) & sig_1312(31) & sig_1312(31) & sig_1312(31) & sig_1312(31) & sig_1312(31) & sig_1312(31) & sig_1312(31) & sig_1312(31) & sig_1312(31) & sig_1312(31) & sig_1312(31) & sig_1312(31) & sig_1312(31) & sig_1312(31) & sig_1312(31) & sig_1312(31) & sig_1312(31) & sig_1312(31) & sig_1312(31) & sig_1312(31) & sig_1312(31) & sig_1312(31) & sig_1312) or
(repeat(64, sig_1155) and delay_bph_reg0(31) & delay_bph_reg0(31) & delay_bph_reg0(31) & delay_bph_reg0(31) & delay_bph_reg0(31) & delay_bph_reg0(31) & delay_bph_reg0(31) & delay_bph_reg0(31) & delay_bph_reg0(31) & delay_bph_reg0(31) & delay_bph_reg0(31) & delay_bph_reg0(31) & delay_bph_reg0(31) & delay_bph_reg0(31) & delay_bph_reg0(31) & delay_bph_reg0(31) & delay_bph_reg0(31) & delay_bph_reg0(31) & delay_bph_reg0(31) & delay_bph_reg0(31) & delay_bph_reg0(31) & delay_bph_reg0(31) & delay_bph_reg0(31) & delay_bph_reg0(31) & delay_bph_reg0(31) & delay_bph_reg0(31) & delay_bph_reg0(31) & delay_bph_reg0(31) & delay_bph_reg0(31) & delay_bph_reg0(31) & delay_bph_reg0(31) & delay_bph_reg0(31) & delay_bph_reg0) or
(repeat(64, sig_1146) and accumc_reg8(31) & accumc_reg8(31) & accumc_reg8(31) & accumc_reg8(31) & accumc_reg8(31) & accumc_reg8(31) & accumc_reg8(31) & accumc_reg8(31) & accumc_reg8(31) & accumc_reg8(31) & accumc_reg8(31) & accumc_reg8(31) & accumc_reg8(31) & accumc_reg8(31) & accumc_reg8(31) & accumc_reg8(31) & accumc_reg8(31) & accumc_reg8(31) & accumc_reg8(31) & accumc_reg8(31) & accumc_reg8(31) & accumc_reg8(31) & accumc_reg8(31) & accumc_reg8(31) & accumc_reg8(31) & accumc_reg8(31) & accumc_reg8(31) & accumc_reg8(31) & accumc_reg8(31) & accumc_reg8(31) & accumc_reg8(31) & accumc_reg8(31) & accumc_reg8) or
(repeat(64, sig_1140) and dec_del_bph_reg3(31) & dec_del_bph_reg3(31) & dec_del_bph_reg3(31) & dec_del_bph_reg3(31) & dec_del_bph_reg3(31) & dec_del_bph_reg3(31) & dec_del_bph_reg3(31) & dec_del_bph_reg3(31) & dec_del_bph_reg3(31) & dec_del_bph_reg3(31) & dec_del_bph_reg3(31) & dec_del_bph_reg3(31) & dec_del_bph_reg3(31) & dec_del_bph_reg3(31) & dec_del_bph_reg3(31) & dec_del_bph_reg3(31) & dec_del_bph_reg3(31) & dec_del_bph_reg3(31) & dec_del_bph_reg3(31) & dec_del_bph_reg3(31) & dec_del_bph_reg3(31) & dec_del_bph_reg3(31) & dec_del_bph_reg3(31) & dec_del_bph_reg3(31) & dec_del_bph_reg3(31) & dec_del_bph_reg3(31) & dec_del_bph_reg3(31) & dec_del_bph_reg3(31) & dec_del_bph_reg3(31) & dec_del_bph_reg3(31) & dec_del_bph_reg3(31) & dec_del_bph_reg3(31) & dec_del_bph_reg3) or
(repeat(64, sig_1133) and dec_rh2(30) & dec_rh2(30) & dec_rh2(30) & dec_rh2(30) & dec_rh2(30) & dec_rh2(30) & dec_rh2(30) & dec_rh2(30) & dec_rh2(30) & dec_rh2(30) & dec_rh2(30) & dec_rh2(30) & dec_rh2(30) & dec_rh2(30) & dec_rh2(30) & dec_rh2(30) & dec_rh2(30) & dec_rh2(30) & dec_rh2(30) & dec_rh2(30) & dec_rh2(30) & dec_rh2(30) & dec_rh2(30) & dec_rh2(30) & dec_rh2(30) & dec_rh2(30) & dec_rh2(30) & dec_rh2(30) & dec_rh2(30) & dec_rh2(30) & dec_rh2(30) & dec_rh2(30) & dec_rh2 & '0') or
(repeat(64, sig_1125) and delay_bpl_reg0(31) & delay_bpl_reg0(31) & delay_bpl_reg0(31) & delay_bpl_reg0(31) & delay_bpl_reg0(31) & delay_bpl_reg0(31) & delay_bpl_reg0(31) & delay_bpl_reg0(31) & delay_bpl_reg0(31) & delay_bpl_reg0(31) & delay_bpl_reg0(31) & delay_bpl_reg0(31) & delay_bpl_reg0(31) & delay_bpl_reg0(31) & delay_bpl_reg0(31) & delay_bpl_reg0(31) & delay_bpl_reg0(31) & delay_bpl_reg0(31) & delay_bpl_reg0(31) & delay_bpl_reg0(31) & delay_bpl_reg0(31) & delay_bpl_reg0(31) & delay_bpl_reg0(31) & delay_bpl_reg0(31) & delay_bpl_reg0(31) & delay_bpl_reg0(31) & delay_bpl_reg0(31) & delay_bpl_reg0(31) & delay_bpl_reg0(31) & delay_bpl_reg0(31) & delay_bpl_reg0(31) & delay_bpl_reg0(31) & delay_bpl_reg0) or
(repeat(64, sig_1122) and dec_del_bpl_reg5(31) & dec_del_bpl_reg5(31) & dec_del_bpl_reg5(31) & dec_del_bpl_reg5(31) & dec_del_bpl_reg5(31) & dec_del_bpl_reg5(31) & dec_del_bpl_reg5(31) & dec_del_bpl_reg5(31) & dec_del_bpl_reg5(31) & dec_del_bpl_reg5(31) & dec_del_bpl_reg5(31) & dec_del_bpl_reg5(31) & dec_del_bpl_reg5(31) & dec_del_bpl_reg5(31) & dec_del_bpl_reg5(31) & dec_del_bpl_reg5(31) & dec_del_bpl_reg5(31) & dec_del_bpl_reg5(31) & dec_del_bpl_reg5(31) & dec_del_bpl_reg5(31) & dec_del_bpl_reg5(31) & dec_del_bpl_reg5(31) & dec_del_bpl_reg5(31) & dec_del_bpl_reg5(31) & dec_del_bpl_reg5(31) & dec_del_bpl_reg5(31) & dec_del_bpl_reg5(31) & dec_del_bpl_reg5(31) & dec_del_bpl_reg5(31) & dec_del_bpl_reg5(31) & dec_del_bpl_reg5(31) & dec_del_bpl_reg5(31) & dec_del_bpl_reg5) or
(repeat(64, sig_1118) and accumc_reg6(31) & accumc_reg6(31) & accumc_reg6(31) & accumc_reg6(31) & accumc_reg6(31) & accumc_reg6(31) & accumc_reg6(31) & accumc_reg6(31) & accumc_reg6(31) & accumc_reg6(31) & accumc_reg6(31) & accumc_reg6(31) & accumc_reg6(31) & accumc_reg6(31) & accumc_reg6(31) & accumc_reg6(31) & accumc_reg6(31) & accumc_reg6(31) & accumc_reg6(31) & accumc_reg6(31) & accumc_reg6(31) & accumc_reg6(31) & accumc_reg6(31) & accumc_reg6(31) & accumc_reg6(31) & accumc_reg6(31) & accumc_reg6(31) & accumc_reg6(31) & accumc_reg6(31) & accumc_reg6(31) & accumc_reg6(31) & accumc_reg6(31) & accumc_reg6) or
(repeat(64, sig_1104) and dec_del_bph_reg5(31) & dec_del_bph_reg5(31) & dec_del_bph_reg5(31) & dec_del_bph_reg5(31) & dec_del_bph_reg5(31) & dec_del_bph_reg5(31) & dec_del_bph_reg5(31) & dec_del_bph_reg5(31) & dec_del_bph_reg5(31) & dec_del_bph_reg5(31) & dec_del_bph_reg5(31) & dec_del_bph_reg5(31) & dec_del_bph_reg5(31) & dec_del_bph_reg5(31) & dec_del_bph_reg5(31) & dec_del_bph_reg5(31) & dec_del_bph_reg5(31) & dec_del_bph_reg5(31) & dec_del_bph_reg5(31) & dec_del_bph_reg5(31) & dec_del_bph_reg5(31) & dec_del_bph_reg5(31) & dec_del_bph_reg5(31) & dec_del_bph_reg5(31) & dec_del_bph_reg5(31) & dec_del_bph_reg5(31) & dec_del_bph_reg5(31) & dec_del_bph_reg5(31) & dec_del_bph_reg5(31) & dec_del_bph_reg5(31) & dec_del_bph_reg5(31) & dec_del_bph_reg5(31) & dec_del_bph_reg5) or
(repeat(64, sig_1100) and detl(31) & detl(31) & detl(31) & detl(31) & detl(31) & detl(31) & detl(31) & detl(31) & detl(31) & detl(31) & detl(31) & detl(31) & detl(31) & detl(31) & detl(31) & detl(31) & detl(31) & detl(31) & detl(31) & detl(31) & detl(31) & detl(31) & detl(31) & detl(31) & detl(31) & detl(31) & detl(31) & detl(31) & detl(31) & detl(31) & detl(31) & detl(31) & detl) or
(repeat(64, sig_1086) and delay_bpl_reg5(31) & delay_bpl_reg5(31) & delay_bpl_reg5(31) & delay_bpl_reg5(31) & delay_bpl_reg5(31) & delay_bpl_reg5(31) & delay_bpl_reg5(31) & delay_bpl_reg5(31) & delay_bpl_reg5(31) & delay_bpl_reg5(31) & delay_bpl_reg5(31) & delay_bpl_reg5(31) & delay_bpl_reg5(31) & delay_bpl_reg5(31) & delay_bpl_reg5(31) & delay_bpl_reg5(31) & delay_bpl_reg5(31) & delay_bpl_reg5(31) & delay_bpl_reg5(31) & delay_bpl_reg5(31) & delay_bpl_reg5(31) & delay_bpl_reg5(31) & delay_bpl_reg5(31) & delay_bpl_reg5(31) & delay_bpl_reg5(31) & delay_bpl_reg5(31) & delay_bpl_reg5(31) & delay_bpl_reg5(31) & delay_bpl_reg5(31) & delay_bpl_reg5(31) & delay_bpl_reg5(31) & delay_bpl_reg5(31) & delay_bpl_reg5) or
(repeat(64, sig_1064) and accumd_reg5(31) & accumd_reg5(31) & accumd_reg5(31) & accumd_reg5(31) & accumd_reg5(31) & accumd_reg5(31) & accumd_reg5(31) & accumd_reg5(31) & accumd_reg5(31) & accumd_reg5(31) & accumd_reg5(31) & accumd_reg5(31) & accumd_reg5(31) & accumd_reg5(31) & accumd_reg5(31) & accumd_reg5(31) & accumd_reg5(31) & accumd_reg5(31) & accumd_reg5(31) & accumd_reg5(31) & accumd_reg5(31) & accumd_reg5(31) & accumd_reg5(31) & accumd_reg5(31) & accumd_reg5(31) & accumd_reg5(31) & accumd_reg5(31) & accumd_reg5(31) & accumd_reg5(31) & accumd_reg5(31) & accumd_reg5(31) & accumd_reg5(31) & accumd_reg5) or
(repeat(64, sig_1061) and nbl(31) & nbl(31) & nbl(31) & nbl(31) & nbl(31) & nbl(31) & nbl(31) & nbl(31) & nbl(31) & nbl(31) & nbl(31) & nbl(31) & nbl(31) & nbl(31) & nbl(31) & nbl(31) & nbl(31) & nbl(31) & nbl(31) & nbl(31) & nbl(31) & nbl(31) & nbl(31) & nbl(31) & nbl(31) & nbl(31) & nbl(31) & nbl(31) & nbl(31) & nbl(31) & nbl(31) & nbl(31) & nbl) or
(repeat(64, sig_1059) and accumc_reg4(31) & accumc_reg4(31) & accumc_reg4(31) & accumc_reg4(31) & accumc_reg4(31) & accumc_reg4(31) & accumc_reg4(31) & accumc_reg4(31) & accumc_reg4(31) & accumc_reg4(31) & accumc_reg4(31) & accumc_reg4(31) & accumc_reg4(31) & accumc_reg4(31) & accumc_reg4(31) & accumc_reg4(31) & accumc_reg4(31) & accumc_reg4(31) & accumc_reg4(31) & accumc_reg4(31) & accumc_reg4(31) & accumc_reg4(31) & accumc_reg4(31) & accumc_reg4(31) & accumc_reg4(31) & accumc_reg4(31) & accumc_reg4(31) & accumc_reg4(31) & accumc_reg4(31) & accumc_reg4(31) & accumc_reg4(31) & accumc_reg4(31) & accumc_reg4) or
(repeat(64, sig_1054) and dec_del_bpl_reg0(31) & dec_del_bpl_reg0(31) & dec_del_bpl_reg0(31) & dec_del_bpl_reg0(31) & dec_del_bpl_reg0(31) & dec_del_bpl_reg0(31) & dec_del_bpl_reg0(31) & dec_del_bpl_reg0(31) & dec_del_bpl_reg0(31) & dec_del_bpl_reg0(31) & dec_del_bpl_reg0(31) & dec_del_bpl_reg0(31) & dec_del_bpl_reg0(31) & dec_del_bpl_reg0(31) & dec_del_bpl_reg0(31) & dec_del_bpl_reg0(31) & dec_del_bpl_reg0(31) & dec_del_bpl_reg0(31) & dec_del_bpl_reg0(31) & dec_del_bpl_reg0(31) & dec_del_bpl_reg0(31) & dec_del_bpl_reg0(31) & dec_del_bpl_reg0(31) & dec_del_bpl_reg0(31) & dec_del_bpl_reg0(31) & dec_del_bpl_reg0(31) & dec_del_bpl_reg0(31) & dec_del_bpl_reg0(31) & dec_del_bpl_reg0(31) & dec_del_bpl_reg0(31) & dec_del_bpl_reg0(31) & dec_del_bpl_reg0(31) & dec_del_bpl_reg0) or
(repeat(64, sig_1048) and tqmf_reg15(31) & tqmf_reg15(31) & tqmf_reg15(31) & tqmf_reg15(31) & tqmf_reg15(31) & tqmf_reg15(31) & tqmf_reg15(31) & tqmf_reg15(31) & tqmf_reg15(31) & tqmf_reg15(31) & tqmf_reg15(31) & tqmf_reg15(31) & tqmf_reg15(31) & tqmf_reg15(31) & tqmf_reg15(31) & tqmf_reg15(31) & tqmf_reg15(31) & tqmf_reg15(31) & tqmf_reg15(31) & tqmf_reg15(31) & tqmf_reg15(31) & tqmf_reg15(31) & tqmf_reg15(31) & tqmf_reg15(31) & tqmf_reg15(31) & tqmf_reg15(31) & tqmf_reg15(31) & tqmf_reg15(31) & tqmf_reg15(31) & tqmf_reg15(31) & tqmf_reg15(31) & tqmf_reg15(31) & tqmf_reg15) or
(repeat(64, sig_1041) and dlt(31) & dlt(31) & dlt(31) & dlt(31) & dlt(31) & dlt(31) & dlt(31) & dlt(31) & dlt(31) & dlt(31) & dlt(31) & dlt(31) & dlt(31) & dlt(31) & dlt(31) & dlt(31) & dlt(31) & dlt(31) & dlt(31) & dlt(31) & dlt(31) & dlt(31) & dlt(31) & dlt(31) & dlt(31) & dlt(31) & dlt(31) & dlt(31) & dlt(31) & dlt(31) & dlt(31) & dlt(31) & dlt) or
(repeat(64, sig_1037) and dec_del_bpl_reg2(31) & dec_del_bpl_reg2(31) & dec_del_bpl_reg2(31) & dec_del_bpl_reg2(31) & dec_del_bpl_reg2(31) & dec_del_bpl_reg2(31) & dec_del_bpl_reg2(31) & dec_del_bpl_reg2(31) & dec_del_bpl_reg2(31) & dec_del_bpl_reg2(31) & dec_del_bpl_reg2(31) & dec_del_bpl_reg2(31) & dec_del_bpl_reg2(31) & dec_del_bpl_reg2(31) & dec_del_bpl_reg2(31) & dec_del_bpl_reg2(31) & dec_del_bpl_reg2(31) & dec_del_bpl_reg2(31) & dec_del_bpl_reg2(31) & dec_del_bpl_reg2(31) & dec_del_bpl_reg2(31) & dec_del_bpl_reg2(31) & dec_del_bpl_reg2(31) & dec_del_bpl_reg2(31) & dec_del_bpl_reg2(31) & dec_del_bpl_reg2(31) & dec_del_bpl_reg2(31) & dec_del_bpl_reg2(31) & dec_del_bpl_reg2(31) & dec_del_bpl_reg2(31) & dec_del_bpl_reg2(31) & dec_del_bpl_reg2(31) & dec_del_bpl_reg2) or
(repeat(64, sig_1036) and delay_bpl_reg4(31) & delay_bpl_reg4(31) & delay_bpl_reg4(31) & delay_bpl_reg4(31) & delay_bpl_reg4(31) & delay_bpl_reg4(31) & delay_bpl_reg4(31) & delay_bpl_reg4(31) & delay_bpl_reg4(31) & delay_bpl_reg4(31) & delay_bpl_reg4(31) & delay_bpl_reg4(31) & delay_bpl_reg4(31) & delay_bpl_reg4(31) & delay_bpl_reg4(31) & delay_bpl_reg4(31) & delay_bpl_reg4(31) & delay_bpl_reg4(31) & delay_bpl_reg4(31) & delay_bpl_reg4(31) & delay_bpl_reg4(31) & delay_bpl_reg4(31) & delay_bpl_reg4(31) & delay_bpl_reg4(31) & delay_bpl_reg4(31) & delay_bpl_reg4(31) & delay_bpl_reg4(31) & delay_bpl_reg4(31) & delay_bpl_reg4(31) & delay_bpl_reg4(31) & delay_bpl_reg4(31) & delay_bpl_reg4(31) & delay_bpl_reg4) or
(repeat(64, sig_1035) and tqmf_reg16(31) & tqmf_reg16(31) & tqmf_reg16(31) & tqmf_reg16(31) & tqmf_reg16(31) & tqmf_reg16(31) & tqmf_reg16(31) & tqmf_reg16(31) & tqmf_reg16(31) & tqmf_reg16(31) & tqmf_reg16(31) & tqmf_reg16(31) & tqmf_reg16(31) & tqmf_reg16(31) & tqmf_reg16(31) & tqmf_reg16(31) & tqmf_reg16(31) & tqmf_reg16(31) & tqmf_reg16(31) & tqmf_reg16(31) & tqmf_reg16(31) & tqmf_reg16(31) & tqmf_reg16(31) & tqmf_reg16(31) & tqmf_reg16(31) & tqmf_reg16(31) & tqmf_reg16(31) & tqmf_reg16(31) & tqmf_reg16(31) & tqmf_reg16(31) & tqmf_reg16(31) & tqmf_reg16(31) & tqmf_reg16) or
(repeat(64, sig_1032) and dec_del_bpl_reg4(31) & dec_del_bpl_reg4(31) & dec_del_bpl_reg4(31) & dec_del_bpl_reg4(31) & dec_del_bpl_reg4(31) & dec_del_bpl_reg4(31) & dec_del_bpl_reg4(31) & dec_del_bpl_reg4(31) & dec_del_bpl_reg4(31) & dec_del_bpl_reg4(31) & dec_del_bpl_reg4(31) & dec_del_bpl_reg4(31) & dec_del_bpl_reg4(31) & dec_del_bpl_reg4(31) & dec_del_bpl_reg4(31) & dec_del_bpl_reg4(31) & dec_del_bpl_reg4(31) & dec_del_bpl_reg4(31) & dec_del_bpl_reg4(31) & dec_del_bpl_reg4(31) & dec_del_bpl_reg4(31) & dec_del_bpl_reg4(31) & dec_del_bpl_reg4(31) & dec_del_bpl_reg4(31) & dec_del_bpl_reg4(31) & dec_del_bpl_reg4(31) & dec_del_bpl_reg4(31) & dec_del_bpl_reg4(31) & dec_del_bpl_reg4(31) & dec_del_bpl_reg4(31) & dec_del_bpl_reg4(31) & dec_del_bpl_reg4(31) & dec_del_bpl_reg4) or
(repeat(64, sig_1027) and accumd_reg1(31) & accumd_reg1(31) & accumd_reg1(31) & accumd_reg1(31) & accumd_reg1(31) & accumd_reg1(31) & accumd_reg1(31) & accumd_reg1(31) & accumd_reg1(31) & accumd_reg1(31) & accumd_reg1(31) & accumd_reg1(31) & accumd_reg1(31) & accumd_reg1(31) & accumd_reg1(31) & accumd_reg1(31) & accumd_reg1(31) & accumd_reg1(31) & accumd_reg1(31) & accumd_reg1(31) & accumd_reg1(31) & accumd_reg1(31) & accumd_reg1(31) & accumd_reg1(31) & accumd_reg1(31) & accumd_reg1(31) & accumd_reg1(31) & accumd_reg1(31) & accumd_reg1(31) & accumd_reg1(31) & accumd_reg1(31) & accumd_reg1(31) & accumd_reg1) or
(repeat(64, sig_1023) and ah2(31) & ah2(31) & ah2(31) & ah2(31) & ah2(31) & ah2(31) & ah2(31) & ah2(31) & ah2(31) & ah2(31) & ah2(31) & ah2(31) & ah2(31) & ah2(31) & ah2(31) & ah2(31) & ah2(31) & ah2(31) & ah2(31) & ah2(31) & ah2(31) & ah2(31) & ah2(31) & ah2(31) & ah2(31) & ah2(31) & ah2(31) & ah2(31) & ah2(31) & ah2(31) & ah2(31) & ah2(31) & ah2) or
(repeat(64, sig_1016) and tqmf_reg8(31) & tqmf_reg8(31) & tqmf_reg8(31) & tqmf_reg8(31) & tqmf_reg8(31) & tqmf_reg8(31) & tqmf_reg8(31) & tqmf_reg8(31) & tqmf_reg8(31) & tqmf_reg8(31) & tqmf_reg8(31) & tqmf_reg8(31) & tqmf_reg8(31) & tqmf_reg8(31) & tqmf_reg8(31) & tqmf_reg8(31) & tqmf_reg8(31) & tqmf_reg8(31) & tqmf_reg8(31) & tqmf_reg8(31) & tqmf_reg8(31) & tqmf_reg8(31) & tqmf_reg8(31) & tqmf_reg8(31) & tqmf_reg8(31) & tqmf_reg8(31) & tqmf_reg8(31) & tqmf_reg8(31) & tqmf_reg8(31) & tqmf_reg8(31) & tqmf_reg8(31) & tqmf_reg8(31) & tqmf_reg8) or
(repeat(64, sig_1015) and dec_del_bph_reg4(31) & dec_del_bph_reg4(31) & dec_del_bph_reg4(31) & dec_del_bph_reg4(31) & dec_del_bph_reg4(31) & dec_del_bph_reg4(31) & dec_del_bph_reg4(31) & dec_del_bph_reg4(31) & dec_del_bph_reg4(31) & dec_del_bph_reg4(31) & dec_del_bph_reg4(31) & dec_del_bph_reg4(31) & dec_del_bph_reg4(31) & dec_del_bph_reg4(31) & dec_del_bph_reg4(31) & dec_del_bph_reg4(31) & dec_del_bph_reg4(31) & dec_del_bph_reg4(31) & dec_del_bph_reg4(31) & dec_del_bph_reg4(31) & dec_del_bph_reg4(31) & dec_del_bph_reg4(31) & dec_del_bph_reg4(31) & dec_del_bph_reg4(31) & dec_del_bph_reg4(31) & dec_del_bph_reg4(31) & dec_del_bph_reg4(31) & dec_del_bph_reg4(31) & dec_del_bph_reg4(31) & dec_del_bph_reg4(31) & dec_del_bph_reg4(31) & dec_del_bph_reg4(31) & dec_del_bph_reg4) or
(repeat(64, sig_1008) and accumc_reg10(31) & accumc_reg10(31) & accumc_reg10(31) & accumc_reg10(31) & accumc_reg10(31) & accumc_reg10(31) & accumc_reg10(31) & accumc_reg10(31) & accumc_reg10(31) & accumc_reg10(31) & accumc_reg10(31) & accumc_reg10(31) & accumc_reg10(31) & accumc_reg10(31) & accumc_reg10(31) & accumc_reg10(31) & accumc_reg10(31) & accumc_reg10(31) & accumc_reg10(31) & accumc_reg10(31) & accumc_reg10(31) & accumc_reg10(31) & accumc_reg10(31) & accumc_reg10(31) & accumc_reg10(31) & accumc_reg10(31) & accumc_reg10(31) & accumc_reg10(31) & accumc_reg10(31) & accumc_reg10(31) & accumc_reg10(31) & accumc_reg10(31) & accumc_reg10) or
(repeat(64, sig_1002) and delay_bph_reg4(31) & delay_bph_reg4(31) & delay_bph_reg4(31) & delay_bph_reg4(31) & delay_bph_reg4(31) & delay_bph_reg4(31) & delay_bph_reg4(31) & delay_bph_reg4(31) & delay_bph_reg4(31) & delay_bph_reg4(31) & delay_bph_reg4(31) & delay_bph_reg4(31) & delay_bph_reg4(31) & delay_bph_reg4(31) & delay_bph_reg4(31) & delay_bph_reg4(31) & delay_bph_reg4(31) & delay_bph_reg4(31) & delay_bph_reg4(31) & delay_bph_reg4(31) & delay_bph_reg4(31) & delay_bph_reg4(31) & delay_bph_reg4(31) & delay_bph_reg4(31) & delay_bph_reg4(31) & delay_bph_reg4(31) & delay_bph_reg4(31) & delay_bph_reg4(31) & delay_bph_reg4(31) & delay_bph_reg4(31) & delay_bph_reg4(31) & delay_bph_reg4(31) & delay_bph_reg4) or
(repeat(64, sig_997) and ph(31) & ph(31) & ph(31) & ph(31) & ph(31) & ph(31) & ph(31) & ph(31) & ph(31) & ph(31) & ph(31) & ph(31) & ph(31) & ph(31) & ph(31) & ph(31) & ph(31) & ph(31) & ph(31) & ph(31) & ph(31) & ph(31) & ph(31) & ph(31) & ph(31) & ph(31) & ph(31) & ph(31) & ph(31) & ph(31) & ph(31) & ph(31) & ph) or
(repeat(64, sig_969) and tqmf_reg19(31) & tqmf_reg19(31) & tqmf_reg19(31) & tqmf_reg19(31) & tqmf_reg19(31) & tqmf_reg19(31) & tqmf_reg19(31) & tqmf_reg19(31) & tqmf_reg19(31) & tqmf_reg19(31) & tqmf_reg19(31) & tqmf_reg19(31) & tqmf_reg19(31) & tqmf_reg19(31) & tqmf_reg19(31) & tqmf_reg19(31) & tqmf_reg19(31) & tqmf_reg19(31) & tqmf_reg19(31) & tqmf_reg19(31) & tqmf_reg19(31) & tqmf_reg19(31) & tqmf_reg19(31) & tqmf_reg19(31) & tqmf_reg19(31) & tqmf_reg19(31) & tqmf_reg19(31) & tqmf_reg19(31) & tqmf_reg19(31) & tqmf_reg19(31) & tqmf_reg19(31) & tqmf_reg19(31) & tqmf_reg19) or
(repeat(64, sig_961) and accumc_reg0(31) & accumc_reg0(31) & accumc_reg0(31) & accumc_reg0(31) & accumc_reg0(31) & accumc_reg0(31) & accumc_reg0(31) & accumc_reg0(31) & accumc_reg0(31) & accumc_reg0(31) & accumc_reg0(31) & accumc_reg0(31) & accumc_reg0(31) & accumc_reg0(31) & accumc_reg0(31) & accumc_reg0(31) & accumc_reg0(31) & accumc_reg0(31) & accumc_reg0(31) & accumc_reg0(31) & accumc_reg0(31) & accumc_reg0(31) & accumc_reg0(31) & accumc_reg0(31) & accumc_reg0(31) & accumc_reg0(31) & accumc_reg0(31) & accumc_reg0(31) & accumc_reg0(31) & accumc_reg0(31) & accumc_reg0(31) & accumc_reg0(31) & accumc_reg0) or
(repeat(64, sig_955) and xs(31) & xs(31) & xs(31) & xs(31) & xs(31) & xs(31) & xs(31) & xs(31) & xs(31) & xs(31) & xs(31) & xs(31) & xs(31) & xs(31) & xs(31) & xs(31) & xs(31) & xs(31) & xs(31) & xs(31) & xs(31) & xs(31) & xs(31) & xs(31) & xs(31) & xs(31) & xs(31) & xs(31) & xs(31) & xs(31) & xs(31) & xs(31) & xs) or
(repeat(64, sig_954) and dec_ah2(31) & dec_ah2(31) & dec_ah2(31) & dec_ah2(31) & dec_ah2(31) & dec_ah2(31) & dec_ah2(31) & dec_ah2(31) & dec_ah2(31) & dec_ah2(31) & dec_ah2(31) & dec_ah2(31) & dec_ah2(31) & dec_ah2(31) & dec_ah2(31) & dec_ah2(31) & dec_ah2(31) & dec_ah2(31) & dec_ah2(31) & dec_ah2(31) & dec_ah2(31) & dec_ah2(31) & dec_ah2(31) & dec_ah2(31) & dec_ah2(31) & dec_ah2(31) & dec_ah2(31) & dec_ah2(31) & dec_ah2(31) & dec_ah2(31) & dec_ah2(31) & dec_ah2(31) & dec_ah2) or
(repeat(64, sig_932) and dec_del_bph_reg0(31) & dec_del_bph_reg0(31) & dec_del_bph_reg0(31) & dec_del_bph_reg0(31) & dec_del_bph_reg0(31) & dec_del_bph_reg0(31) & dec_del_bph_reg0(31) & dec_del_bph_reg0(31) & dec_del_bph_reg0(31) & dec_del_bph_reg0(31) & dec_del_bph_reg0(31) & dec_del_bph_reg0(31) & dec_del_bph_reg0(31) & dec_del_bph_reg0(31) & dec_del_bph_reg0(31) & dec_del_bph_reg0(31) & dec_del_bph_reg0(31) & dec_del_bph_reg0(31) & dec_del_bph_reg0(31) & dec_del_bph_reg0(31) & dec_del_bph_reg0(31) & dec_del_bph_reg0(31) & dec_del_bph_reg0(31) & dec_del_bph_reg0(31) & dec_del_bph_reg0(31) & dec_del_bph_reg0(31) & dec_del_bph_reg0(31) & dec_del_bph_reg0(31) & dec_del_bph_reg0(31) & dec_del_bph_reg0(31) & dec_del_bph_reg0(31) & dec_del_bph_reg0(31) & dec_del_bph_reg0) or
(repeat(64, sig_931) and accumd_reg7(31) & accumd_reg7(31) & accumd_reg7(31) & accumd_reg7(31) & accumd_reg7(31) & accumd_reg7(31) & accumd_reg7(31) & accumd_reg7(31) & accumd_reg7(31) & accumd_reg7(31) & accumd_reg7(31) & accumd_reg7(31) & accumd_reg7(31) & accumd_reg7(31) & accumd_reg7(31) & accumd_reg7(31) & accumd_reg7(31) & accumd_reg7(31) & accumd_reg7(31) & accumd_reg7(31) & accumd_reg7(31) & accumd_reg7(31) & accumd_reg7(31) & accumd_reg7(31) & accumd_reg7(31) & accumd_reg7(31) & accumd_reg7(31) & accumd_reg7(31) & accumd_reg7(31) & accumd_reg7(31) & accumd_reg7(31) & accumd_reg7(31) & accumd_reg7) or
(repeat(64, sig_927) and delay_bph_reg1(31) & delay_bph_reg1(31) & delay_bph_reg1(31) & delay_bph_reg1(31) & delay_bph_reg1(31) & delay_bph_reg1(31) & delay_bph_reg1(31) & delay_bph_reg1(31) & delay_bph_reg1(31) & delay_bph_reg1(31) & delay_bph_reg1(31) & delay_bph_reg1(31) & delay_bph_reg1(31) & delay_bph_reg1(31) & delay_bph_reg1(31) & delay_bph_reg1(31) & delay_bph_reg1(31) & delay_bph_reg1(31) & delay_bph_reg1(31) & delay_bph_reg1(31) & delay_bph_reg1(31) & delay_bph_reg1(31) & delay_bph_reg1(31) & delay_bph_reg1(31) & delay_bph_reg1(31) & delay_bph_reg1(31) & delay_bph_reg1(31) & delay_bph_reg1(31) & delay_bph_reg1(31) & delay_bph_reg1(31) & delay_bph_reg1(31) & delay_bph_reg1(31) & delay_bph_reg1) or
(repeat(64, sig_921) and tqmf_reg12(31) & tqmf_reg12(31) & tqmf_reg12(31) & tqmf_reg12(31) & tqmf_reg12(31) & tqmf_reg12(31) & tqmf_reg12(31) & tqmf_reg12(31) & tqmf_reg12(31) & tqmf_reg12(31) & tqmf_reg12(31) & tqmf_reg12(31) & tqmf_reg12(31) & tqmf_reg12(31) & tqmf_reg12(31) & tqmf_reg12(31) & tqmf_reg12(31) & tqmf_reg12(31) & tqmf_reg12(31) & tqmf_reg12(31) & tqmf_reg12(31) & tqmf_reg12(31) & tqmf_reg12(31) & tqmf_reg12(31) & tqmf_reg12(31) & tqmf_reg12(31) & tqmf_reg12(31) & tqmf_reg12(31) & tqmf_reg12(31) & tqmf_reg12(31) & tqmf_reg12(31) & tqmf_reg12(31) & tqmf_reg12) or
(repeat(64, sig_914) and dec_detl(31) & dec_detl(31) & dec_detl(31) & dec_detl(31) & dec_detl(31) & dec_detl(31) & dec_detl(31) & dec_detl(31) & dec_detl(31) & dec_detl(31) & dec_detl(31) & dec_detl(31) & dec_detl(31) & dec_detl(31) & dec_detl(31) & dec_detl(31) & dec_detl(31) & dec_detl(31) & dec_detl(31) & dec_detl(31) & dec_detl(31) & dec_detl(31) & dec_detl(31) & dec_detl(31) & dec_detl(31) & dec_detl(31) & dec_detl(31) & dec_detl(31) & dec_detl(31) & dec_detl(31) & dec_detl(31) & dec_detl(31) & dec_detl) or
(repeat(64, sig_895) and dec_deth(31) & dec_deth(31) & dec_deth(31) & dec_deth(31) & dec_deth(31) & dec_deth(31) & dec_deth(31) & dec_deth(31) & dec_deth(31) & dec_deth(31) & dec_deth(31) & dec_deth(31) & dec_deth(31) & dec_deth(31) & dec_deth(31) & dec_deth(31) & dec_deth(31) & dec_deth(31) & dec_deth(31) & dec_deth(31) & dec_deth(31) & dec_deth(31) & dec_deth(31) & dec_deth(31) & dec_deth(31) & dec_deth(31) & dec_deth(31) & dec_deth(31) & dec_deth(31) & dec_deth(31) & dec_deth(31) & dec_deth(31) & dec_deth) or
(repeat(64, sig_904) and dec_del_bph_reg2(31) & dec_del_bph_reg2(31) & dec_del_bph_reg2(31) & dec_del_bph_reg2(31) & dec_del_bph_reg2(31) & dec_del_bph_reg2(31) & dec_del_bph_reg2(31) & dec_del_bph_reg2(31) & dec_del_bph_reg2(31) & dec_del_bph_reg2(31) & dec_del_bph_reg2(31) & dec_del_bph_reg2(31) & dec_del_bph_reg2(31) & dec_del_bph_reg2(31) & dec_del_bph_reg2(31) & dec_del_bph_reg2(31) & dec_del_bph_reg2(31) & dec_del_bph_reg2(31) & dec_del_bph_reg2(31) & dec_del_bph_reg2(31) & dec_del_bph_reg2(31) & dec_del_bph_reg2(31) & dec_del_bph_reg2(31) & dec_del_bph_reg2(31) & dec_del_bph_reg2(31) & dec_del_bph_reg2(31) & dec_del_bph_reg2(31) & dec_del_bph_reg2(31) & dec_del_bph_reg2(31) & dec_del_bph_reg2(31) & dec_del_bph_reg2(31) & dec_del_bph_reg2(31) & dec_del_bph_reg2) or
(repeat(64, sig_887) and accumd_reg9(31) & accumd_reg9(31) & accumd_reg9(31) & accumd_reg9(31) & accumd_reg9(31) & accumd_reg9(31) & accumd_reg9(31) & accumd_reg9(31) & accumd_reg9(31) & accumd_reg9(31) & accumd_reg9(31) & accumd_reg9(31) & accumd_reg9(31) & accumd_reg9(31) & accumd_reg9(31) & accumd_reg9(31) & accumd_reg9(31) & accumd_reg9(31) & accumd_reg9(31) & accumd_reg9(31) & accumd_reg9(31) & accumd_reg9(31) & accumd_reg9(31) & accumd_reg9(31) & accumd_reg9(31) & accumd_reg9(31) & accumd_reg9(31) & accumd_reg9(31) & accumd_reg9(31) & accumd_reg9(31) & accumd_reg9(31) & accumd_reg9(31) & accumd_reg9) or
(repeat(64, sig_885) and accumd_reg3(31) & accumd_reg3(31) & accumd_reg3(31) & accumd_reg3(31) & accumd_reg3(31) & accumd_reg3(31) & accumd_reg3(31) & accumd_reg3(31) & accumd_reg3(31) & accumd_reg3(31) & accumd_reg3(31) & accumd_reg3(31) & accumd_reg3(31) & accumd_reg3(31) & accumd_reg3(31) & accumd_reg3(31) & accumd_reg3(31) & accumd_reg3(31) & accumd_reg3(31) & accumd_reg3(31) & accumd_reg3(31) & accumd_reg3(31) & accumd_reg3(31) & accumd_reg3(31) & accumd_reg3(31) & accumd_reg3(31) & accumd_reg3(31) & accumd_reg3(31) & accumd_reg3(31) & accumd_reg3(31) & accumd_reg3(31) & accumd_reg3(31) & accumd_reg3) or
(repeat(64, sig_882) and delay_bph_reg5(31) & delay_bph_reg5(31) & delay_bph_reg5(31) & delay_bph_reg5(31) & delay_bph_reg5(31) & delay_bph_reg5(31) & delay_bph_reg5(31) & delay_bph_reg5(31) & delay_bph_reg5(31) & delay_bph_reg5(31) & delay_bph_reg5(31) & delay_bph_reg5(31) & delay_bph_reg5(31) & delay_bph_reg5(31) & delay_bph_reg5(31) & delay_bph_reg5(31) & delay_bph_reg5(31) & delay_bph_reg5(31) & delay_bph_reg5(31) & delay_bph_reg5(31) & delay_bph_reg5(31) & delay_bph_reg5(31) & delay_bph_reg5(31) & delay_bph_reg5(31) & delay_bph_reg5(31) & delay_bph_reg5(31) & delay_bph_reg5(31) & delay_bph_reg5(31) & delay_bph_reg5(31) & delay_bph_reg5(31) & delay_bph_reg5(31) & delay_bph_reg5(31) & delay_bph_reg5) or
(repeat(64, sig_880) and delay_bph_reg3(31) & delay_bph_reg3(31) & delay_bph_reg3(31) & delay_bph_reg3(31) & delay_bph_reg3(31) & delay_bph_reg3(31) & delay_bph_reg3(31) & delay_bph_reg3(31) & delay_bph_reg3(31) & delay_bph_reg3(31) & delay_bph_reg3(31) & delay_bph_reg3(31) & delay_bph_reg3(31) & delay_bph_reg3(31) & delay_bph_reg3(31) & delay_bph_reg3(31) & delay_bph_reg3(31) & delay_bph_reg3(31) & delay_bph_reg3(31) & delay_bph_reg3(31) & delay_bph_reg3(31) & delay_bph_reg3(31) & delay_bph_reg3(31) & delay_bph_reg3(31) & delay_bph_reg3(31) & delay_bph_reg3(31) & delay_bph_reg3(31) & delay_bph_reg3(31) & delay_bph_reg3(31) & delay_bph_reg3(31) & delay_bph_reg3(31) & delay_bph_reg3(31) & delay_bph_reg3) or
(repeat(64, sig_869) and deth(31) & deth(31) & deth(31) & deth(31) & deth(31) & deth(31) & deth(31) & deth(31) & deth(31) & deth(31) & deth(31) & deth(31) & deth(31) & deth(31) & deth(31) & deth(31) & deth(31) & deth(31) & deth(31) & deth(31) & deth(31) & deth(31) & deth(31) & deth(31) & deth(31) & deth(31) & deth(31) & deth(31) & deth(31) & deth(31) & deth(31) & deth(31) & deth) or
(repeat(64, sig_868) and tqmf_reg0(31) & tqmf_reg0(31) & tqmf_reg0(31) & tqmf_reg0(31) & tqmf_reg0(31) & tqmf_reg0(31) & tqmf_reg0(31) & tqmf_reg0(31) & tqmf_reg0(31) & tqmf_reg0(31) & tqmf_reg0(31) & tqmf_reg0(31) & tqmf_reg0(31) & tqmf_reg0(31) & tqmf_reg0(31) & tqmf_reg0(31) & tqmf_reg0(31) & tqmf_reg0(31) & tqmf_reg0(31) & tqmf_reg0(31) & tqmf_reg0(31) & tqmf_reg0(31) & tqmf_reg0(31) & tqmf_reg0(31) & tqmf_reg0(31) & tqmf_reg0(31) & tqmf_reg0(31) & tqmf_reg0(31) & tqmf_reg0(31) & tqmf_reg0(31) & tqmf_reg0(31) & tqmf_reg0(31) & tqmf_reg0) or
(repeat(64, sig_866) and tqmf_reg4(31) & tqmf_reg4(31) & tqmf_reg4(31) & tqmf_reg4(31) & tqmf_reg4(31) & tqmf_reg4(31) & tqmf_reg4(31) & tqmf_reg4(31) & tqmf_reg4(31) & tqmf_reg4(31) & tqmf_reg4(31) & tqmf_reg4(31) & tqmf_reg4(31) & tqmf_reg4(31) & tqmf_reg4(31) & tqmf_reg4(31) & tqmf_reg4(31) & tqmf_reg4(31) & tqmf_reg4(31) & tqmf_reg4(31) & tqmf_reg4(31) & tqmf_reg4(31) & tqmf_reg4(31) & tqmf_reg4(31) & tqmf_reg4(31) & tqmf_reg4(31) & tqmf_reg4(31) & tqmf_reg4(31) & tqmf_reg4(31) & tqmf_reg4(31) & tqmf_reg4(31) & tqmf_reg4(31) & tqmf_reg4) or
(repeat(64, sig_865) and accumc_reg2(31) & accumc_reg2(31) & accumc_reg2(31) & accumc_reg2(31) & accumc_reg2(31) & accumc_reg2(31) & accumc_reg2(31) & accumc_reg2(31) & accumc_reg2(31) & accumc_reg2(31) & accumc_reg2(31) & accumc_reg2(31) & accumc_reg2(31) & accumc_reg2(31) & accumc_reg2(31) & accumc_reg2(31) & accumc_reg2(31) & accumc_reg2(31) & accumc_reg2(31) & accumc_reg2(31) & accumc_reg2(31) & accumc_reg2(31) & accumc_reg2(31) & accumc_reg2(31) & accumc_reg2(31) & accumc_reg2(31) & accumc_reg2(31) & accumc_reg2(31) & accumc_reg2(31) & accumc_reg2(31) & accumc_reg2(31) & accumc_reg2(31) & accumc_reg2) or
(repeat(64, sig_862) and dec_del_bph_reg1(31) & dec_del_bph_reg1(31) & dec_del_bph_reg1(31) & dec_del_bph_reg1(31) & dec_del_bph_reg1(31) & dec_del_bph_reg1(31) & dec_del_bph_reg1(31) & dec_del_bph_reg1(31) & dec_del_bph_reg1(31) & dec_del_bph_reg1(31) & dec_del_bph_reg1(31) & dec_del_bph_reg1(31) & dec_del_bph_reg1(31) & dec_del_bph_reg1(31) & dec_del_bph_reg1(31) & dec_del_bph_reg1(31) & dec_del_bph_reg1(31) & dec_del_bph_reg1(31) & dec_del_bph_reg1(31) & dec_del_bph_reg1(31) & dec_del_bph_reg1(31) & dec_del_bph_reg1(31) & dec_del_bph_reg1(31) & dec_del_bph_reg1(31) & dec_del_bph_reg1(31) & dec_del_bph_reg1(31) & dec_del_bph_reg1(31) & dec_del_bph_reg1(31) & dec_del_bph_reg1(31) & dec_del_bph_reg1(31) & dec_del_bph_reg1(31) & dec_del_bph_reg1(31) & dec_del_bph_reg1);
-- Behaviour of component 'mux_383' model 'mux'
mux_383 <=
(repeat(6, sig_1015) and sig_1285(5 downto 0)) or
(repeat(6, sig_1068) and sig_1307(5 downto 0));
-- Behaviour of component 'mux_385' model 'mux'
mux_385 <=
(repeat(7, sig_1139) and "1100011") or
(repeat(7, sig_1047) and "0000110") or
(repeat(7, sig_1182) and "0000101") or
(repeat(7, sig_1183) and "0001000") or
(repeat(7, sig_1214) and "0001010") or
(repeat(7, sig_1192) and "0000010") or
(repeat(7, sig_1189) and "0000011") or
(repeat(7, sig_1187) and "0000111") or
(repeat(7, sig_1025) and "0001001") or
(repeat(7, sig_1019) and "0000001") or
(repeat(7, sig_999) and "0000100") or
(repeat(7, sig_860) and "1100010") or
(repeat(7, sig_859) and "1100001") or
(repeat(7, sig_858) and "1100000") or
(repeat(7, sig_857) and "1011111") or
(repeat(7, sig_856) and "1011110") or
(repeat(7, sig_855) and "1011101") or
(repeat(7, sig_854) and "1011100") or
(repeat(7, sig_853) and "1011011") or
(repeat(7, sig_852) and "1011010") or
(repeat(7, sig_851) and "1011001") or
(repeat(7, sig_850) and "1011000") or
(repeat(7, sig_849) and "1010111") or
(repeat(7, sig_848) and "1010110") or
(repeat(7, sig_847) and "1010101") or
(repeat(7, sig_846) and "1010100") or
(repeat(7, sig_845) and "1010011") or
(repeat(7, sig_844) and "1010010") or
(repeat(7, sig_843) and "1010001") or
(repeat(7, sig_842) and "1010000") or
(repeat(7, sig_841) and "1001111") or
(repeat(7, sig_840) and "1001110") or
(repeat(7, sig_839) and "1001101") or
(repeat(7, sig_838) and "1001100") or
(repeat(7, sig_837) and "1001011") or
(repeat(7, sig_836) and "1001010") or
(repeat(7, sig_835) and "1001001") or
(repeat(7, sig_834) and "1001000") or
(repeat(7, sig_833) and "1000111") or
(repeat(7, sig_832) and "1000110") or
(repeat(7, sig_831) and "1000101") or
(repeat(7, sig_830) and "1000100") or
(repeat(7, sig_829) and "1000011") or
(repeat(7, sig_828) and "1000010") or
(repeat(7, sig_827) and "1000001") or
(repeat(7, sig_826) and "1000000") or
(repeat(7, sig_825) and "0111111") or
(repeat(7, sig_824) and "0111110") or
(repeat(7, sig_823) and "0111101") or
(repeat(7, sig_822) and "0111100") or
(repeat(7, sig_821) and "0111011") or
(repeat(7, sig_820) and "0111010") or
(repeat(7, sig_819) and "0111001") or
(repeat(7, sig_818) and "0111000") or
(repeat(7, sig_817) and "0110111") or
(repeat(7, sig_816) and "0110110") or
(repeat(7, sig_815) and "0110101") or
(repeat(7, sig_814) and "0110100") or
(repeat(7, sig_813) and "0110011") or
(repeat(7, sig_812) and "0110010") or
(repeat(7, sig_811) and "0110001") or
(repeat(7, sig_810) and "0110000") or
(repeat(7, sig_809) and "0101111") or
(repeat(7, sig_808) and "0101110") or
(repeat(7, sig_807) and "0101101") or
(repeat(7, sig_806) and "0101100") or
(repeat(7, sig_805) and "0101011") or
(repeat(7, sig_804) and "0101010") or
(repeat(7, sig_803) and "0101001") or
(repeat(7, sig_802) and "0101000") or
(repeat(7, sig_801) and "0100111") or
(repeat(7, sig_800) and "0100110") or
(repeat(7, sig_799) and "0100101") or
(repeat(7, sig_798) and "0100100") or
(repeat(7, sig_797) and "0100011") or
(repeat(7, sig_796) and "0100010") or
(repeat(7, sig_795) and "0100001") or
(repeat(7, sig_794) and "0100000") or
(repeat(7, sig_793) and "0011111") or
(repeat(7, sig_792) and "0011110") or
(repeat(7, sig_791) and "0011101") or
(repeat(7, sig_790) and "0011100") or
(repeat(7, sig_789) and "0011011") or
(repeat(7, sig_788) and "0011010") or
(repeat(7, sig_787) and "0011001") or
(repeat(7, sig_786) and "0011000") or
(repeat(7, sig_785) and "0010111") or
(repeat(7, sig_784) and "0010110") or
(repeat(7, sig_783) and "0010101") or
(repeat(7, sig_782) and "0010100") or
(repeat(7, sig_988) and "0010011") or
(repeat(7, sig_987) and "0010010") or
(repeat(7, sig_986) and "0010001") or
(repeat(7, sig_985) and "0010000") or
(repeat(7, sig_1205) and "0001111") or
(repeat(7, sig_1204) and "0001110") or
(repeat(7, sig_1203) and "0001101") or
(repeat(7, sig_1202) and "0001100") or
(repeat(7, sig_1201) and "0001011");
-- Behaviour of component 'mux_390' model 'mux'
mux_390 <=
(repeat(64, sig_1133) and filtep_pl_14) or
(repeat(64, sig_1099) and logscl_wd_28(31) & logscl_wd_28(31) & logscl_wd_28(31) & logscl_wd_28(31) & logscl_wd_28(31) & logscl_wd_28(31) & logscl_wd_28(31) & logscl_wd_28(31) & logscl_wd_28(31) & logscl_wd_28(31) & logscl_wd_28(31) & logscl_wd_28(31) & logscl_wd_28(31) & logscl_wd_28(31) & logscl_wd_28(31) & logscl_wd_28(31) & logscl_wd_28(31) & logscl_wd_28(31) & logscl_wd_28(31) & logscl_wd_28(31) & logscl_wd_28(31) & logscl_wd_28(31) & logscl_wd_28(31) & logscl_wd_28(31) & logscl_wd_28(31) & logscl_wd_28(31) & logscl_wd_28(31) & logscl_wd_28(31) & logscl_wd_28(31) & logscl_wd_28(31) & logscl_wd_28(31) & logscl_wd_28(31) & logscl_wd_28) or
(repeat(64, sig_1260) and encode_xa_67) or
(repeat(64, sig_1145) and decode_xa1_100) or
(repeat(64, sig_1231) and upzero_wd2(31) & upzero_wd2(31) & upzero_wd2(31) & upzero_wd2(31) & upzero_wd2(31) & upzero_wd2(31) & upzero_wd2(31) & upzero_wd2(31) & upzero_wd2(31) & upzero_wd2(31) & upzero_wd2(31) & upzero_wd2(31) & upzero_wd2(31) & upzero_wd2(31) & upzero_wd2(31) & upzero_wd2(31) & upzero_wd2(31) & upzero_wd2(31) & upzero_wd2(31) & upzero_wd2(31) & upzero_wd2(31) & upzero_wd2(31) & upzero_wd2(31) & upzero_wd2(31) & upzero_wd2(31) & upzero_wd2(31) & upzero_wd2(31) & upzero_wd2(31) & upzero_wd2(31) & upzero_wd2(31) & upzero_wd2(31) & upzero_wd2(31) & upzero_wd2) or
(repeat(64, sig_1198) and encode_xb_68) or
(repeat(64, sig_1153) and sl(31) & sl(31) & sl(31) & sl(31) & sl(31) & sl(31) & sl(31) & sl(31) & sl(31) & sl(31) & sl(31) & sl(31) & sl(31) & sl(31) & sl(31) & sl(31) & sl(31) & sl(31) & sl(31) & sl(31) & sl(31) & sl(31) & sl(31) & sl(31) & sl(31) & sl(31) & sl(31) & sl(31) & sl(31) & sl(31) & sl(31) & sl(31) & sl) or
(repeat(64, sig_1169) and filtez_zl) or
(repeat(64, sig_1257) and dec_sh(31) & dec_sh(31) & dec_sh(31) & dec_sh(31) & dec_sh(31) & dec_sh(31) & dec_sh(31) & dec_sh(31) & dec_sh(31) & dec_sh(31) & dec_sh(31) & dec_sh(31) & dec_sh(31) & dec_sh(31) & dec_sh(31) & dec_sh(31) & dec_sh(31) & dec_sh(31) & dec_sh(31) & dec_sh(31) & dec_sh(31) & dec_sh(31) & dec_sh(31) & dec_sh(31) & dec_sh(31) & dec_sh(31) & dec_sh(31) & dec_sh(31) & dec_sh(31) & dec_sh(31) & dec_sh(31) & dec_sh(31) & dec_sh) or
(repeat(64, sig_1097) and filtep_pl_14(46) & filtep_pl_14(46) & filtep_pl_14(46) & filtep_pl_14(46) & filtep_pl_14(46) & filtep_pl_14(46) & filtep_pl_14(46) & filtep_pl_14(46) & filtep_pl_14(46) & filtep_pl_14(46) & filtep_pl_14(46) & filtep_pl_14(46) & filtep_pl_14(46) & filtep_pl_14(46) & filtep_pl_14(46) & filtep_pl_14(46) & filtep_pl_14(46) & filtep_pl_14(46) & filtep_pl_14(46) & filtep_pl_14(46) & filtep_pl_14(46) & filtep_pl_14(46) & filtep_pl_14(46) & filtep_pl_14(46) & filtep_pl_14(46) & filtep_pl_14(46) & filtep_pl_14(46) & filtep_pl_14(46) & filtep_pl_14(46) & filtep_pl_14(46) & filtep_pl_14(46) & filtep_pl_14(46) & filtep_pl_14(46 downto 15)) or
(repeat(64, sig_1090) and augh_main_i_132(6) & augh_main_i_132(6) & augh_main_i_132(6) & augh_main_i_132(6) & augh_main_i_132(6) & augh_main_i_132(6) & augh_main_i_132(6) & augh_main_i_132(6) & augh_main_i_132(6) & augh_main_i_132(6) & augh_main_i_132(6) & augh_main_i_132(6) & augh_main_i_132(6) & augh_main_i_132(6) & augh_main_i_132(6) & augh_main_i_132(6) & augh_main_i_132(6) & augh_main_i_132(6) & augh_main_i_132(6) & augh_main_i_132(6) & augh_main_i_132(6) & augh_main_i_132(6) & augh_main_i_132(6) & augh_main_i_132(6) & augh_main_i_132(6) & augh_main_i_132(6) & augh_main_i_132(6) & augh_main_i_132(6) & augh_main_i_132(6) & augh_main_i_132(6) & augh_main_i_132(6) & augh_main_i_132(6) & augh_main_i_132(6) & augh_main_i_132(6) & augh_main_i_132(6) & augh_main_i_132(6) & augh_main_i_132(6) & augh_main_i_132(6) & augh_main_i_132(6) & augh_main_i_132(6) & augh_main_i_132(6) & augh_main_i_132(6) & augh_main_i_132(6) & augh_main_i_132(6) & augh_main_i_132(6) & augh_main_i_132(6) & augh_main_i_132(6) & augh_main_i_132(6) & augh_main_i_132(6) & augh_main_i_132(6) & augh_main_i_132(6) & augh_main_i_132(6) & augh_main_i_132(6) & augh_main_i_132(6) & augh_main_i_132(6) & augh_main_i_132(6) & augh_main_i_132(6) & augh_main_i_132(6 downto 0)) or
(repeat(64, sig_1084) and dl(31) & dl(31) & dl(31) & dl(31) & dl(31) & dl(31) & dl(31) & dl(31) & dl(31) & dl(31) & dl(31) & dl(31) & dl(31) & dl(31) & dl(31) & dl(31) & dl(31) & dl(31) & dl(31) & dl(31) & dl(31) & dl(31) & dl(31) & dl(31) & dl(31) & dl(31) & dl(31) & dl(31) & dl(31) & dl(31) & dl(31) & dl(31) & dl) or
(repeat(64, sig_1066) and decode_xa2_101) or
(repeat(64, sig_1022) and uppol2_wd4_42(31) & uppol2_wd4_42(31) & uppol2_wd4_42(31) & uppol2_wd4_42(31) & uppol2_wd4_42(31) & uppol2_wd4_42(31) & uppol2_wd4_42(31) & uppol2_wd4_42(31) & uppol2_wd4_42(31) & uppol2_wd4_42(31) & uppol2_wd4_42(31) & uppol2_wd4_42(31) & uppol2_wd4_42(31) & uppol2_wd4_42(31) & uppol2_wd4_42(31) & uppol2_wd4_42(31) & uppol2_wd4_42(31) & uppol2_wd4_42(31) & uppol2_wd4_42(31) & uppol2_wd4_42(31) & uppol2_wd4_42(31) & uppol2_wd4_42(31) & uppol2_wd4_42(31) & uppol2_wd4_42(31) & uppol2_wd4_42(31) & uppol2_wd4_42(31) & uppol2_wd4_42(31) & uppol2_wd4_42(31) & uppol2_wd4_42(31) & uppol2_wd4_42(31) & uppol2_wd4_42(31) & uppol2_wd4_42(31) & uppol2_wd4_42) or
(repeat(64, sig_997) and sh(31) & sh(31) & sh(31) & sh(31) & sh(31) & sh(31) & sh(31) & sh(31) & sh(31) & sh(31) & sh(31) & sh(31) & sh(31) & sh(31) & sh(31) & sh(31) & sh(31) & sh(31) & sh(31) & sh(31) & sh(31) & sh(31) & sh(31) & sh(31) & sh(31) & sh(31) & sh(31) & sh(31) & sh(31) & sh(31) & sh(31) & sh(31) & sh) or
(repeat(64, sig_957) and encode_xa_67(46) & encode_xa_67(46) & encode_xa_67(46) & encode_xa_67(46) & encode_xa_67(46) & encode_xa_67(46) & encode_xa_67(46) & encode_xa_67(46) & encode_xa_67(46) & encode_xa_67(46) & encode_xa_67(46) & encode_xa_67(46) & encode_xa_67(46) & encode_xa_67(46) & encode_xa_67(46) & encode_xa_67(46) & encode_xa_67(46) & encode_xa_67(46 downto 0)) or
(repeat(64, sig_950) and augh_main_i_132(31) & augh_main_i_132(31) & augh_main_i_132(31) & augh_main_i_132(31) & augh_main_i_132(31) & augh_main_i_132(31) & augh_main_i_132(31) & augh_main_i_132(31) & augh_main_i_132(31) & augh_main_i_132(31) & augh_main_i_132(31) & augh_main_i_132(31) & augh_main_i_132(31) & augh_main_i_132(31) & augh_main_i_132(31) & augh_main_i_132(31) & augh_main_i_132(31) & augh_main_i_132(31) & augh_main_i_132(31) & augh_main_i_132(31) & augh_main_i_132(31) & augh_main_i_132(31) & augh_main_i_132(31) & augh_main_i_132(31) & augh_main_i_132(31) & augh_main_i_132(31) & augh_main_i_132(31) & augh_main_i_132(31) & augh_main_i_132(31) & augh_main_i_132(31) & augh_main_i_132(31) & augh_main_i_132(31) & augh_main_i_132(31) & augh_main_i_132(31 downto 1)) or
(repeat(64, sig_935) and dlt(31) & dlt(31) & dlt(31) & dlt(31) & dlt(31) & dlt(31) & dlt(31) & dlt(31) & dlt(31) & dlt(31) & dlt(31) & dlt(31) & dlt(31) & dlt(31) & dlt(31) & dlt(31) & dlt(31) & dlt(31) & dlt(31) & dlt(31) & dlt(31) & dlt(31) & dlt(31) & dlt(31) & dlt(31) & dlt(31) & dlt(31) & dlt(31) & dlt(31) & dlt(31) & dlt(31) & dlt(31) & dlt) or
(repeat(64, sig_895) and dec_sl(31) & dec_sl(31) & dec_sl(31) & dec_sl(31) & dec_sl(31) & dec_sl(31) & dec_sl(31) & dec_sl(31) & dec_sl(31) & dec_sl(31) & dec_sl(31) & dec_sl(31) & dec_sl(31) & dec_sl(31) & dec_sl(31) & dec_sl(31) & dec_sl(31) & dec_sl(31) & dec_sl(31) & dec_sl(31) & dec_sl(31) & dec_sl(31) & dec_sl(31) & dec_sl(31) & dec_sl(31) & dec_sl(31) & dec_sl(31) & dec_sl(31) & dec_sl(31) & dec_sl(31) & dec_sl(31) & dec_sl(31) & dec_sl) or
(repeat(64, sig_893) and dec_dh(31) & dec_dh(31) & dec_dh(31) & dec_dh(31) & dec_dh(31) & dec_dh(31) & dec_dh(31) & dec_dh(31) & dec_dh(31) & dec_dh(31) & dec_dh(31) & dec_dh(31) & dec_dh(31) & dec_dh(31) & dec_dh(31) & dec_dh(31) & dec_dh(31) & dec_dh(31) & dec_dh(31) & dec_dh(31) & dec_dh(31) & dec_dh(31) & dec_dh(31) & dec_dh(31) & dec_dh(31) & dec_dh(31) & dec_dh(31) & dec_dh(31) & dec_dh(31) & dec_dh(31) & dec_dh(31) & dec_dh(31) & dec_dh) or
(repeat(64, sig_901) and quantl_mil_19(31) & quantl_mil_19(31) & quantl_mil_19(31) & quantl_mil_19(31) & quantl_mil_19(31) & quantl_mil_19(31) & quantl_mil_19(31) & quantl_mil_19(31) & quantl_mil_19(31) & quantl_mil_19(31) & quantl_mil_19(31) & quantl_mil_19(31) & quantl_mil_19(31) & quantl_mil_19(31) & quantl_mil_19(31) & quantl_mil_19(31) & quantl_mil_19(31) & quantl_mil_19(31) & quantl_mil_19(31) & quantl_mil_19(31) & quantl_mil_19(31) & quantl_mil_19(31) & quantl_mil_19(31) & quantl_mil_19(31) & quantl_mil_19(31) & quantl_mil_19(31) & quantl_mil_19(31) & quantl_mil_19(31) & quantl_mil_19(31) & quantl_mil_19(31) & quantl_mil_19(31) & quantl_mil_19(31) & quantl_mil_19) or
(repeat(64, sig_874) and dh(31) & dh(31) & dh(31) & dh(31) & dh(31) & dh(31) & dh(31) & dh(31) & dh(31) & dh(31) & dh(31) & dh(31) & dh(31) & dh(31) & dh(31) & dh(31) & dh(31) & dh(31) & dh(31) & dh(31) & dh(31) & dh(31) & dh(31) & dh(31) & dh(31) & dh(31) & dh(31) & dh(31) & dh(31) & dh(31) & dh(31) & dh(31) & dh) or
(repeat(64, sig_869) and logsch_wd_58(31) & logsch_wd_58(31) & logsch_wd_58(31) & logsch_wd_58(31) & logsch_wd_58(31) & logsch_wd_58(31) & logsch_wd_58(31) & logsch_wd_58(31) & logsch_wd_58(31) & logsch_wd_58(31) & logsch_wd_58(31) & logsch_wd_58(31) & logsch_wd_58(31) & logsch_wd_58(31) & logsch_wd_58(31) & logsch_wd_58(31) & logsch_wd_58(31) & logsch_wd_58(31) & logsch_wd_58(31) & logsch_wd_58(31) & logsch_wd_58(31) & logsch_wd_58(31) & logsch_wd_58(31) & logsch_wd_58(31) & logsch_wd_58(31) & logsch_wd_58(31) & logsch_wd_58(31) & logsch_wd_58(31) & logsch_wd_58(31) & logsch_wd_58(31) & logsch_wd_58(31) & logsch_wd_58(31) & logsch_wd_58);
-- Behaviour of component 'mux_391' model 'mux'
mux_391 <=
(repeat(64, sig_1089) and "0000000000000000000000000000000000000000000000000000000000000001") or
(repeat(64, sig_1084) and dec_sl(31) & dec_sl(31) & dec_sl(31) & dec_sl(31) & dec_sl(31) & dec_sl(31) & dec_sl(31) & dec_sl(31) & dec_sl(31) & dec_sl(31) & dec_sl(31) & dec_sl(31) & dec_sl(31) & dec_sl(31) & dec_sl(31) & dec_sl(31) & dec_sl(31) & dec_sl(31) & dec_sl(31) & dec_sl(31) & dec_sl(31) & dec_sl(31) & dec_sl(31) & dec_sl(31) & dec_sl(31) & dec_sl(31) & dec_sl(31) & dec_sl(31) & dec_sl(31) & dec_sl(31) & dec_sl(31) & dec_sl(31) & dec_sl) or
(repeat(64, sig_1257) and dec_dh(31) & dec_dh(31) & dec_dh(31) & dec_dh(31) & dec_dh(31) & dec_dh(31) & dec_dh(31) & dec_dh(31) & dec_dh(31) & dec_dh(31) & dec_dh(31) & dec_dh(31) & dec_dh(31) & dec_dh(31) & dec_dh(31) & dec_dh(31) & dec_dh(31) & dec_dh(31) & dec_dh(31) & dec_dh(31) & dec_dh(31) & dec_dh(31) & dec_dh(31) & dec_dh(31) & dec_dh(31) & dec_dh(31) & dec_dh(31) & dec_dh(31) & dec_dh(31) & dec_dh(31) & dec_dh(31) & dec_dh(31) & dec_dh) or
(repeat(64, sig_1096) and filtez_zl(45) & filtez_zl(45) & filtez_zl(45) & filtez_zl(45) & filtez_zl(45) & filtez_zl(45) & filtez_zl(45) & filtez_zl(45) & filtez_zl(45) & filtez_zl(45) & filtez_zl(45) & filtez_zl(45) & filtez_zl(45) & filtez_zl(45) & filtez_zl(45) & filtez_zl(45) & filtez_zl(45) & filtez_zl(45) & filtez_zl(45) & filtez_zl(45) & filtez_zl(45) & filtez_zl(45) & filtez_zl(45) & filtez_zl(45) & filtez_zl(45) & filtez_zl(45) & filtez_zl(45) & filtez_zl(45) & filtez_zl(45) & filtez_zl(45) & filtez_zl(45) & filtez_zl(45) & filtez_zl(45 downto 14)) or
(repeat(64, sig_1231) and upzero_wd3(31) & upzero_wd3(31) & upzero_wd3(31) & upzero_wd3(31) & upzero_wd3(31) & upzero_wd3(31) & upzero_wd3(31) & upzero_wd3(31) & upzero_wd3(31) & upzero_wd3(31) & upzero_wd3(31) & upzero_wd3(31) & upzero_wd3(31) & upzero_wd3(31) & upzero_wd3(31) & upzero_wd3(31) & upzero_wd3(31) & upzero_wd3(31) & upzero_wd3(31) & upzero_wd3(31) & upzero_wd3(31) & upzero_wd3(31) & upzero_wd3(31) & upzero_wd3(31) & upzero_wd3(31) & upzero_wd3(31) & upzero_wd3(31) & upzero_wd3(31) & upzero_wd3(31) & upzero_wd3(31) & upzero_wd3(31) & upzero_wd3(31) & upzero_wd3) or
(repeat(64, sig_1194) and sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31 downto 0)) or
(repeat(64, sig_1099) and sig_1314(31) & sig_1314(31) & sig_1314(31) & sig_1314(31) & sig_1314(31) & sig_1314(31) & sig_1314(31) & sig_1314(31) & sig_1314(31) & sig_1314(31) & sig_1314(31) & sig_1314(31) & sig_1314(31) & sig_1314(31) & sig_1314(31) & sig_1314(31) & sig_1314(31) & sig_1314(31) & sig_1314(31) & sig_1314(31) & sig_1314(31) & sig_1314(31) & sig_1314(31) & sig_1314(31) & sig_1314(31) & sig_1314(31) & sig_1314(31) & sig_1314(31) & sig_1314(31) & sig_1314(31) & sig_1314(31) & sig_1314(31) & sig_1314) or
(repeat(64, sig_1133) and sig_1304) or
(repeat(64, sig_1153) and dlt(31) & dlt(31) & dlt(31) & dlt(31) & dlt(31) & dlt(31) & dlt(31) & dlt(31) & dlt(31) & dlt(31) & dlt(31) & dlt(31) & dlt(31) & dlt(31) & dlt(31) & dlt(31) & dlt(31) & dlt(31) & dlt(31) & dlt(31) & dlt(31) & dlt(31) & dlt(31) & dlt(31) & dlt(31) & dlt(31) & dlt(31) & dlt(31) & dlt(31) & dlt(31) & dlt(31) & dlt(31) & dlt) or
(repeat(64, sig_1022) and sig_1304(38) & sig_1304(38) & sig_1304(38) & sig_1304(38) & sig_1304(38) & sig_1304(38) & sig_1304(38) & sig_1304(38) & sig_1304(38) & sig_1304(38) & sig_1304(38) & sig_1304(38) & sig_1304(38) & sig_1304(38) & sig_1304(38) & sig_1304(38) & sig_1304(38) & sig_1304(38) & sig_1304(38) & sig_1304(38) & sig_1304(38) & sig_1304(38) & sig_1304(38) & sig_1304(38) & sig_1304(38) & sig_1304(38) & sig_1304(38) & sig_1304(38) & sig_1304(38) & sig_1304(38) & sig_1304(38) & sig_1304(38) & sig_1304(38 downto 7)) or
(repeat(64, sig_997) and dh(31) & dh(31) & dh(31) & dh(31) & dh(31) & dh(31) & dh(31) & dh(31) & dh(31) & dh(31) & dh(31) & dh(31) & dh(31) & dh(31) & dh(31) & dh(31) & dh(31) & dh(31) & dh(31) & dh(31) & dh(31) & dh(31) & dh(31) & dh(31) & dh(31) & dh(31) & dh(31) & dh(31) & dh(31) & dh(31) & dh(31) & dh(31) & dh) or
(repeat(64, sig_957) and encode_xb_68(46) & encode_xb_68(46) & encode_xb_68(46) & encode_xb_68(46) & encode_xb_68(46) & encode_xb_68(46) & encode_xb_68(46) & encode_xb_68(46) & encode_xb_68(46) & encode_xb_68(46) & encode_xb_68(46) & encode_xb_68(46) & encode_xb_68(46) & encode_xb_68(46) & encode_xb_68(46) & encode_xb_68(46) & encode_xb_68(46) & encode_xb_68(46 downto 0)) or
(repeat(64, sig_935) and szl(31) & szl(31) & szl(31) & szl(31) & szl(31) & szl(31) & szl(31) & szl(31) & szl(31) & szl(31) & szl(31) & szl(31) & szl(31) & szl(31) & szl(31) & szl(31) & szl(31) & szl(31) & szl(31) & szl(31) & szl(31) & szl(31) & szl(31) & szl(31) & szl(31) & szl(31) & szl(31) & szl(31) & szl(31) & szl(31) & szl(31) & szl(31) & szl) or
(repeat(64, sig_895) and dec_dlt(31) & dec_dlt(31) & dec_dlt(31) & dec_dlt(31) & dec_dlt(31) & dec_dlt(31) & dec_dlt(31) & dec_dlt(31) & dec_dlt(31) & dec_dlt(31) & dec_dlt(31) & dec_dlt(31) & dec_dlt(31) & dec_dlt(31) & dec_dlt(31) & dec_dlt(31) & dec_dlt(31) & dec_dlt(31) & dec_dlt(31) & dec_dlt(31) & dec_dlt(31) & dec_dlt(31) & dec_dlt(31) & dec_dlt(31) & dec_dlt(31) & dec_dlt(31) & dec_dlt(31) & dec_dlt(31) & dec_dlt(31) & dec_dlt(31) & dec_dlt(31) & dec_dlt(31) & dec_dlt) or
(repeat(64, sig_869) and sig_1308(31) & sig_1308(31) & sig_1308(31) & sig_1308(31) & sig_1308(31) & sig_1308(31) & sig_1308(31) & sig_1308(31) & sig_1308(31) & sig_1308(31) & sig_1308(31) & sig_1308(31) & sig_1308(31) & sig_1308(31) & sig_1308(31) & sig_1308(31) & sig_1308(31) & sig_1308(31) & sig_1308(31) & sig_1308(31) & sig_1308(31) & sig_1308(31) & sig_1308(31) & sig_1308(31) & sig_1308(31) & sig_1308(31) & sig_1308(31) & sig_1308(31) & sig_1308(31) & sig_1308(31) & sig_1308(31) & sig_1308(31) & sig_1308);
-- Behaviour of component 'mux_376' model 'mux'
mux_376 <=
(repeat(7, sig_1222) and "1001111") or
(repeat(7, sig_1220) and "1000001") or
(repeat(7, sig_1211) and "0100110") or
(repeat(7, sig_1223) and "1010000") or
(repeat(7, sig_1212) and "1000110") or
(repeat(7, sig_1210) and "0000111") or
(repeat(7, sig_1224) and "0011111") or
(repeat(7, sig_1217) and "0000100") or
(repeat(7, sig_1216) and "0001100") or
(repeat(7, sig_1219) and "0111000") or
(repeat(7, sig_1218) and "1001001") or
(repeat(7, sig_1230) and "1000000") or
(repeat(7, sig_1229) and "0100001") or
(repeat(7, sig_1228) and "1011000") or
(repeat(7, sig_1245) and "1000111") or
(repeat(7, sig_1244) and "1010111") or
(repeat(7, sig_1247) and "0101001") or
(repeat(7, sig_1246) and "0010101") or
(repeat(7, sig_1250) and "0000011") or
(repeat(7, sig_1249) and "0010110") or
(repeat(7, sig_1248) and "0010111") or
(repeat(7, sig_1251) and "0001110") or
(repeat(7, sig_1236) and "0001011") or
(repeat(7, sig_1235) and "1010001") or
(repeat(7, sig_1239) and "0011000") or
(repeat(7, sig_1238) and "1010010") or
(repeat(7, sig_1237) and "1011010") or
(repeat(7, sig_1208) and "1011011") or
(repeat(7, sig_1207) and "1011001") or
(repeat(7, sig_1206) and "0010010") or
(repeat(7, sig_1234) and "1001000") or
(repeat(7, sig_1233) and "1010100") or
(repeat(7, sig_1180) and "1001011") or
(repeat(7, sig_1179) and "0101011") or
(repeat(7, sig_1178) and "1001101") or
(repeat(7, sig_1177) and "1000101") or
(repeat(7, sig_1185) and "1000100") or
(repeat(7, sig_1184) and "0110101") or
(repeat(7, sig_1181) and "0001000") or
(repeat(7, sig_1188) and "0100100") or
(repeat(7, sig_1186) and "0100000") or
(repeat(7, sig_1190) and "0110000") or
(repeat(7, sig_1191) and "0011001") or
(repeat(7, sig_1193) and "0000110") or
(repeat(7, sig_1157) and "0010001") or
(repeat(7, sig_1156) and "0001111") or
(repeat(7, sig_1137) and "1010101") or
(repeat(7, sig_1123) and "1010110") or
(repeat(7, sig_1120) and "0110011") or
(repeat(7, sig_1117) and "0111110") or
(repeat(7, sig_1109) and "0000101") or
(repeat(7, sig_1080) and "1100011") or
(repeat(7, sig_1079) and "1100010") or
(repeat(7, sig_1078) and "1100001") or
(repeat(7, sig_1077) and "1100000") or
(repeat(7, sig_1076) and "1011111") or
(repeat(7, sig_1075) and "1011110") or
(repeat(7, sig_1074) and "1011101") or
(repeat(7, sig_1073) and "1011100") or
(repeat(7, sig_1055) and "0100111") or
(repeat(7, sig_1046) and "0110010") or
(repeat(7, sig_1039) and "0011101") or
(repeat(7, sig_1018) and "1000010") or
(repeat(7, sig_1013) and "0011110") or
(repeat(7, sig_1012) and "0110111") or
(repeat(7, sig_991) and "0000001") or
(repeat(7, sig_972) and "0100011") or
(repeat(7, sig_971) and "0011010") or
(repeat(7, sig_968) and "0111100") or
(repeat(7, sig_967) and "0110110") or
(repeat(7, sig_952) and "0101000") or
(repeat(7, sig_948) and "0111011") or
(repeat(7, sig_947) and "1000011") or
(repeat(7, sig_946) and "0111111") or
(repeat(7, sig_945) and "0111001") or
(repeat(7, sig_944) and "1001010") or
(repeat(7, sig_943) and "1001100") or
(repeat(7, sig_942) and "0101101") or
(repeat(7, sig_941) and "1010011") or
(repeat(7, sig_940) and "0101110") or
(repeat(7, sig_939) and "0110100") or
(repeat(7, sig_938) and "0100010") or
(repeat(7, sig_937) and "0010100") or
(repeat(7, sig_933) and "0101111") or
(repeat(7, sig_929) and "0010011") or
(repeat(7, sig_924) and "0101100") or
(repeat(7, sig_919) and "0000010") or
(repeat(7, sig_918) and "0011100") or
(repeat(7, sig_917) and "0001010") or
(repeat(7, sig_907) and "0010000") or
(repeat(7, sig_892) and "0111010") or
(repeat(7, sig_902) and "0100101") or
(repeat(7, sig_899) and "0001101") or
(repeat(7, sig_888) and "0110001") or
(repeat(7, sig_886) and "0011011") or
(repeat(7, sig_884) and "1001110") or
(repeat(7, sig_878) and "0111101") or
(repeat(7, sig_877) and "0101010") or
(repeat(7, sig_876) and "0001001");
-- Behaviour of component 'mux_377' model 'mux'
mux_377 <=
(repeat(32, sig_903) and decode_xa1_100(45 downto 14)) or
(repeat(32, sig_1087) and decode_xa2_101(45 downto 14));
-- Behaviour of component 'mux_372' model 'mux'
mux_372 <=
(repeat(32, sig_1081) and "00000000000000000000000001100100") or
(repeat(32, sig_1087) and sig_1289(30 downto 0) & augh_main_i_132(0)) or
(repeat(32, sig_950) and sig_1298(30 downto 0) & augh_main_i_132(0)) or
(repeat(32, sig_1023) and sig_1288(30 downto 0) & augh_main_i_132(0));
-- Behaviour of component 'mux_374' model 'mux'
mux_374 <=
(repeat(7, sig_903) and augh_main_i_132(6 downto 0)) or
(repeat(7, sig_1087) and sig_1298(6 downto 0));
-- Behaviour of component 'mux_364' model 'mux'
mux_364 <=
(repeat(32, sig_925) and "00000000000000000000000001111111") or
(repeat(32, sig_914) and dec_del_dltx_reg1) or
(repeat(32, sig_1253) and "00000000000000000000000000000000") or
(repeat(32, sig_1016) and "00000000000000000000000000000000") or
(repeat(32, sig_1241) and delay_dltx_reg1) or
(repeat(32, sig_1195) and "00000000000000000000000000000000") or
(repeat(32, sig_1129) and "00000000000000000000000011111111") or
(repeat(32, sig_1133) and dec_del_dhx_reg1) or
(repeat(32, sig_1153) and "00000000000000000000001000110100") or
(repeat(32, sig_895) and dec_del_dhx_reg0) or
(repeat(32, sig_868) and delay_dltx_reg0);
-- Behaviour of component 'mux_365' model 'mux'
mux_365 <=
(repeat(33, sig_1112) and delay_bph_reg2(31) & delay_bph_reg2) or
(repeat(33, sig_1125) and delay_bpl_reg2(31) & delay_bpl_reg2) or
(repeat(33, sig_1153) and plt(31) & plt) or
(repeat(33, sig_895) and dec_nbh(31) & dec_nbh) or
(repeat(33, sig_932) and dec_del_bph_reg5(31) & dec_del_bph_reg5) or
(repeat(33, sig_1053) and dec_del_bpl_reg5(31) & dec_del_bpl_reg5);
-- Behaviour of component 'mux_366' model 'mux'
mux_366 <=
(repeat(32, sig_895) and "00000000000000000000000001111111") or
(repeat(32, sig_1129) and "00000000000000000000000011111111") or
(repeat(32, sig_1153) and plt2);
-- Behaviour of component 'mux_363' model 'mux'
mux_363 <=
(repeat(33, sig_1016) and delay_bpl_reg4(31) & delay_bpl_reg4) or
(repeat(33, sig_932) and dec_del_bph_reg3(31) & dec_del_bph_reg3) or
(repeat(33, sig_1253) and delay_bpl_reg5(31) & delay_bpl_reg5) or
(repeat(33, sig_1053) and dec_del_bpl_reg3(31) & dec_del_bpl_reg3) or
(repeat(33, sig_1240) and delay_bpl_reg1(31) & delay_bpl_reg1) or
(repeat(33, sig_1195) and delay_bpl_reg3(31) & delay_bpl_reg3) or
(repeat(33, sig_1112) and delay_bph_reg1(31) & delay_bph_reg1) or
(repeat(33, sig_1133) and dec_del_bph_reg1(31) & dec_del_bph_reg1) or
(repeat(33, sig_1153) and deth(31) & deth) or
(repeat(33, sig_927) and al2(31) & al2) or
(repeat(33, sig_914) and dec_del_bpl_reg1(31) & dec_del_bpl_reg1) or
(repeat(33, sig_911) and dec_nbl(31) & dec_nbl) or
(repeat(33, sig_895) and dec_del_bph_reg0(31) & dec_del_bph_reg0) or
(repeat(33, sig_868) and delay_bpl_reg0(31) & delay_bpl_reg0) or
(repeat(33, sig_866) and delay_bpl_reg2(31) & delay_bpl_reg2);
-- Behaviour of component 'mux_352' model 'mux'
mux_352 <=
(repeat(64, sig_1023) and "0000000000000000000000000000000000000000000000000000000000000001") or
(repeat(64, sig_1133) and "0000000000000000000000000000000000000000000000000000000000000011") or
(repeat(64, sig_1227) and sig_1291(31) & sig_1291(31) & sig_1291(31) & sig_1291(31) & sig_1291(31) & sig_1291(31) & sig_1291(31) & sig_1291(31) & sig_1291(31) & sig_1291(31) & sig_1291(31) & sig_1291(31) & sig_1291(31) & sig_1291(31) & sig_1291(31) & sig_1291(31) & sig_1291(31) & sig_1291(31) & sig_1291(31) & sig_1291(31) & sig_1291(31) & sig_1291(31) & sig_1291(31) & sig_1291(31) & sig_1291(31) & sig_1291(31) & sig_1291(31) & sig_1291(31) & sig_1291(31) & sig_1291(31) & sig_1291(31) & sig_1291(31) & sig_1291(31 downto 0)) or
(repeat(64, sig_921) and filtez_zl(45) & filtez_zl(45) & filtez_zl(45) & filtez_zl(45) & filtez_zl(45) & filtez_zl(45) & filtez_zl(45) & filtez_zl(45) & filtez_zl(45) & filtez_zl(45) & filtez_zl(45) & filtez_zl(45) & filtez_zl(45) & filtez_zl(45) & filtez_zl(45) & filtez_zl(45) & filtez_zl(45) & filtez_zl(45) & filtez_zl(45) & filtez_zl(45) & filtez_zl(45) & filtez_zl(45) & filtez_zl(45) & filtez_zl(45) & filtez_zl(45) & filtez_zl(45) & filtez_zl(45) & filtez_zl(45) & filtez_zl(45) & filtez_zl(45) & filtez_zl(45) & filtez_zl(45) & filtez_zl(45 downto 14)) or
(repeat(64, sig_927) and sig_1291(38) & sig_1291(38) & sig_1291(38) & sig_1291(38) & sig_1291(38) & sig_1291(38) & sig_1291(38) & sig_1291(38) & sig_1291(38) & sig_1291(38) & sig_1291(38) & sig_1291(38) & sig_1291(38) & sig_1291(38) & sig_1291(38) & sig_1291(38) & sig_1291(38) & sig_1291(38) & sig_1291(38) & sig_1291(38) & sig_1291(38) & sig_1291(38) & sig_1291(38) & sig_1291(38) & sig_1291(38) & sig_1291(38) & sig_1291(38) & sig_1291(38) & sig_1291(38) & sig_1291(38) & sig_1291(38) & sig_1291(38) & sig_1291(38 downto 7)) or
(repeat(64, sig_954) and rh(31) & rh(31) & rh(31) & rh(31) & rh(31) & rh(31) & rh(31) & rh(31) & rh(31) & rh(31) & rh(31) & rh(31) & rh(31) & rh(31) & rh(31) & rh(31) & rh(31) & rh(31) & rh(31) & rh(31) & rh(31) & rh(31) & rh(31) & rh(31) & rh(31) & rh(31) & rh(31) & rh(31) & rh(31) & rh(31) & rh(31) & rh(31) & rh);
-- Behaviour of component 'mux_353' model 'mux'
mux_353 <=
(repeat(64, sig_926) and filtep_pl_14) or
(repeat(64, sig_905) and dec_dlt(31) & dec_dlt(31) & dec_dlt(31) & dec_dlt(31) & dec_dlt(31) & dec_dlt(31) & dec_dlt(31) & dec_dlt(31) & dec_dlt(31) & dec_dlt(31) & dec_dlt(31) & dec_dlt(31) & dec_dlt(31) & dec_dlt(31) & dec_dlt(31) & dec_dlt(31) & dec_dlt(31) & dec_dlt(31) & dec_dlt(31) & dec_dlt(31) & dec_dlt(31) & dec_dlt(31) & dec_dlt(31) & dec_dlt(31) & dec_dlt(31) & dec_dlt(31) & dec_dlt(31) & dec_dlt(31) & dec_dlt(31) & dec_dlt(31) & dec_dlt(31) & dec_dlt(31) & dec_dlt) or
(repeat(64, sig_1145) and decode_xa2_101) or
(repeat(64, sig_1022) and uppol1_wd2_51(31) & uppol1_wd2_51(31) & uppol1_wd2_51(31) & uppol1_wd2_51(31) & uppol1_wd2_51(31) & uppol1_wd2_51(31) & uppol1_wd2_51(31) & uppol1_wd2_51(31) & uppol1_wd2_51(31) & uppol1_wd2_51(31) & uppol1_wd2_51(31) & uppol1_wd2_51(31) & uppol1_wd2_51(31) & uppol1_wd2_51(31) & uppol1_wd2_51(31) & uppol1_wd2_51(31) & uppol1_wd2_51(31) & uppol1_wd2_51(31) & uppol1_wd2_51(31) & uppol1_wd2_51(31) & uppol1_wd2_51(31) & uppol1_wd2_51(31) & uppol1_wd2_51(31) & uppol1_wd2_51(31) & uppol1_wd2_51(31) & uppol1_wd2_51(31) & uppol1_wd2_51(31) & uppol1_wd2_51(31) & uppol1_wd2_51(31) & uppol1_wd2_51(31) & uppol1_wd2_51(31) & uppol1_wd2_51(31) & uppol1_wd2_51(31) & uppol1_wd2_51(31) & uppol1_wd2_51(31) & uppol1_wd2_51(31) & uppol1_wd2_51(31) & uppol1_wd2_51(31) & uppol1_wd2_51(31 downto 6)) or
(repeat(64, sig_1260) and encode_xb_68) or
(repeat(64, sig_1198) and encode_xa_67) or
(repeat(64, sig_1066) and decode_xa1_100) or
(repeat(64, sig_1087) and augh_main_i_132(31) & augh_main_i_132(31) & augh_main_i_132(31) & augh_main_i_132(31) & augh_main_i_132(31) & augh_main_i_132(31) & augh_main_i_132(31) & augh_main_i_132(31) & augh_main_i_132(31) & augh_main_i_132(31) & augh_main_i_132(31) & augh_main_i_132(31) & augh_main_i_132(31) & augh_main_i_132(31) & augh_main_i_132(31) & augh_main_i_132(31) & augh_main_i_132(31) & augh_main_i_132(31) & augh_main_i_132(31) & augh_main_i_132(31) & augh_main_i_132(31) & augh_main_i_132(31) & augh_main_i_132(31) & augh_main_i_132(31) & augh_main_i_132(31) & augh_main_i_132(31) & augh_main_i_132(31) & augh_main_i_132(31) & augh_main_i_132(31) & augh_main_i_132(31) & augh_main_i_132(31) & augh_main_i_132(31) & augh_main_i_132(31) & augh_main_i_132(31 downto 1)) or
(repeat(64, sig_1133) and logsch_wd_58(31) & logsch_wd_58(31) & logsch_wd_58(31) & logsch_wd_58(31) & logsch_wd_58(31) & logsch_wd_58(31) & logsch_wd_58(31) & logsch_wd_58(31) & logsch_wd_58(31) & logsch_wd_58(31) & logsch_wd_58(31) & logsch_wd_58(31) & logsch_wd_58(31) & logsch_wd_58(31) & logsch_wd_58(31) & logsch_wd_58(31) & logsch_wd_58(31) & logsch_wd_58(31) & logsch_wd_58(31) & logsch_wd_58(31) & logsch_wd_58(31) & logsch_wd_58(31) & logsch_wd_58(31) & logsch_wd_58(31) & logsch_wd_58(31) & logsch_wd_58(31) & logsch_wd_58(31) & logsch_wd_58(31) & logsch_wd_58(31) & logsch_wd_58(31) & logsch_wd_58(31) & logsch_wd_58(31) & logsch_wd_58) or
(repeat(64, sig_893) and filtep_pl_14(46) & filtep_pl_14(46) & filtep_pl_14(46) & filtep_pl_14(46) & filtep_pl_14(46) & filtep_pl_14(46) & filtep_pl_14(46) & filtep_pl_14(46) & filtep_pl_14(46) & filtep_pl_14(46) & filtep_pl_14(46) & filtep_pl_14(46) & filtep_pl_14(46) & filtep_pl_14(46) & filtep_pl_14(46) & filtep_pl_14(46) & filtep_pl_14(46) & filtep_pl_14(46) & filtep_pl_14(46) & filtep_pl_14(46) & filtep_pl_14(46) & filtep_pl_14(46) & filtep_pl_14(46) & filtep_pl_14(46) & filtep_pl_14(46) & filtep_pl_14(46) & filtep_pl_14(46) & filtep_pl_14(46) & filtep_pl_14(46) & filtep_pl_14(46) & filtep_pl_14(46) & filtep_pl_14(46) & filtep_pl_14(46 downto 15));
-- Behaviour of component 'mux_354' model 'mux'
mux_354 <=
(repeat(64, sig_1087) and "0000000000000000000000000000000000000000000000000000000000000001") or
(repeat(64, sig_1133) and sig_1308(31) & sig_1308(31) & sig_1308(31) & sig_1308(31) & sig_1308(31) & sig_1308(31) & sig_1308(31) & sig_1308(31) & sig_1308(31) & sig_1308(31) & sig_1308(31) & sig_1308(31) & sig_1308(31) & sig_1308(31) & sig_1308(31) & sig_1308(31) & sig_1308(31) & sig_1308(31) & sig_1308(31) & sig_1308(31) & sig_1308(31) & sig_1308(31) & sig_1308(31) & sig_1308(31) & sig_1308(31) & sig_1308(31) & sig_1308(31) & sig_1308(31) & sig_1308(31) & sig_1308(31) & sig_1308(31) & sig_1308(31) & sig_1308) or
(repeat(64, sig_1197) and sig_1303(31) & sig_1303(31) & sig_1303(31) & sig_1303(31) & sig_1303(31) & sig_1303(31) & sig_1303(31) & sig_1303(31) & sig_1303(31) & sig_1303(31) & sig_1303(31) & sig_1303(31) & sig_1303(31) & sig_1303(31) & sig_1303(31) & sig_1303(31) & sig_1303(31) & sig_1303(31) & sig_1303(31) & sig_1303(31) & sig_1303(31) & sig_1303(31) & sig_1303(31) & sig_1303(31) & sig_1303(31) & sig_1303(31) & sig_1303(31) & sig_1303(31) & sig_1303(31) & sig_1303(31) & sig_1303(31) & sig_1303(31) & sig_1303(31 downto 0)) or
(repeat(64, sig_910) and filtez_zl(45) & filtez_zl(45) & filtez_zl(45) & filtez_zl(45) & filtez_zl(45) & filtez_zl(45) & filtez_zl(45) & filtez_zl(45) & filtez_zl(45) & filtez_zl(45) & filtez_zl(45) & filtez_zl(45) & filtez_zl(45) & filtez_zl(45) & filtez_zl(45) & filtez_zl(45) & filtez_zl(45) & filtez_zl(45) & filtez_zl(45) & filtez_zl(45) & filtez_zl(45) & filtez_zl(45) & filtez_zl(45) & filtez_zl(45) & filtez_zl(45) & filtez_zl(45) & filtez_zl(45) & filtez_zl(45) & filtez_zl(45) & filtez_zl(45) & filtez_zl(45) & filtez_zl(45) & filtez_zl(45 downto 14)) or
(repeat(64, sig_926) and sig_1303) or
(repeat(64, sig_1022) and "0000000000000000000000000000000000000000000000000000000000000011");
-- Behaviour of component 'mux_355' model 'mux'
mux_355 <=
(repeat(64, sig_927) and uppol1_wd2_51(31) & uppol1_wd2_51(31) & uppol1_wd2_51(31) & uppol1_wd2_51(31) & uppol1_wd2_51(31) & uppol1_wd2_51(31) & uppol1_wd2_51(31) & uppol1_wd2_51(31) & uppol1_wd2_51(31) & uppol1_wd2_51(31) & uppol1_wd2_51(31) & uppol1_wd2_51(31) & uppol1_wd2_51(31) & uppol1_wd2_51(31) & uppol1_wd2_51(31) & uppol1_wd2_51(31) & uppol1_wd2_51(31) & uppol1_wd2_51(31) & uppol1_wd2_51(31) & uppol1_wd2_51(31) & uppol1_wd2_51(31) & uppol1_wd2_51(31) & uppol1_wd2_51(31) & uppol1_wd2_51(31) & uppol1_wd2_51(31) & uppol1_wd2_51(31) & uppol1_wd2_51(31) & uppol1_wd2_51(31) & uppol1_wd2_51(31) & uppol1_wd2_51(31) & uppol1_wd2_51(31) & uppol1_wd2_51(31) & uppol1_wd2_51(31) & uppol1_wd2_51(31) & uppol1_wd2_51(31) & uppol1_wd2_51(31) & uppol1_wd2_51(31) & uppol1_wd2_51(31) & uppol1_wd2_51(31 downto 6)) or
(repeat(64, sig_1133) and filtez_zl) or
(repeat(64, sig_1241) and filtep_pl_14);
-- Behaviour of component 'mux_356' model 'mux'
mux_356 <=
(repeat(64, sig_927) and "0000000000000000000000000000000000000000000000000000000000000011") or
(repeat(64, sig_1133) and sig_1291(31) & sig_1291(31) & sig_1291(31) & sig_1291(31) & sig_1291(31) & sig_1291(31) & sig_1291(31) & sig_1291(31) & sig_1291(31) & sig_1291(31) & sig_1291(31) & sig_1291(31) & sig_1291(31) & sig_1291(31) & sig_1291(31) & sig_1291(31) & sig_1291(31) & sig_1291(31) & sig_1291(31) & sig_1291(31) & sig_1291(31) & sig_1291(31) & sig_1291(31) & sig_1291(31) & sig_1291(31) & sig_1291(31) & sig_1291(31) & sig_1291(31) & sig_1291(31) & sig_1291(31) & sig_1291(31) & sig_1291(31) & sig_1291(31 downto 0)) or
(repeat(64, sig_1241) and sig_1281);
-- Behaviour of component 'mux_349' model 'mux'
mux_349 <=
(repeat(33, sig_1112) and delay_bph_reg3(31) & delay_bph_reg3) or
(repeat(33, sig_1125) and delay_bpl_reg3(31) & delay_bpl_reg3) or
(repeat(33, sig_1153) and nbh(31) & nbh) or
(repeat(33, sig_895) and dec_rh1(30) & dec_rh1 & '0') or
(repeat(33, sig_932) and dec_del_bph_reg2(31) & dec_del_bph_reg2) or
(repeat(33, sig_1053) and dec_del_bpl_reg2(31) & dec_del_bpl_reg2);
-- Behaviour of component 'mux_350' model 'mux'
mux_350 <=
(repeat(32, sig_895) and dec_ah1) or
(repeat(32, sig_1129) and "00000000000000000000000011111111") or
(repeat(32, sig_1153) and "00000000000000000000000001111111");
-- Behaviour of component 'mux_351' model 'mux'
mux_351 <=
(repeat(64, sig_1023) and augh_main_i_132(31) & augh_main_i_132(31) & augh_main_i_132(31) & augh_main_i_132(31) & augh_main_i_132(31) & augh_main_i_132(31) & augh_main_i_132(31) & augh_main_i_132(31) & augh_main_i_132(31) & augh_main_i_132(31) & augh_main_i_132(31) & augh_main_i_132(31) & augh_main_i_132(31) & augh_main_i_132(31) & augh_main_i_132(31) & augh_main_i_132(31) & augh_main_i_132(31) & augh_main_i_132(31) & augh_main_i_132(31) & augh_main_i_132(31) & augh_main_i_132(31) & augh_main_i_132(31) & augh_main_i_132(31) & augh_main_i_132(31) & augh_main_i_132(31) & augh_main_i_132(31) & augh_main_i_132(31) & augh_main_i_132(31) & augh_main_i_132(31) & augh_main_i_132(31) & augh_main_i_132(31) & augh_main_i_132(31) & augh_main_i_132(31) & augh_main_i_132(31 downto 1)) or
(repeat(64, sig_1133) and uppol1_wd2_51(31) & uppol1_wd2_51(31) & uppol1_wd2_51(31) & uppol1_wd2_51(31) & uppol1_wd2_51(31) & uppol1_wd2_51(31) & uppol1_wd2_51(31) & uppol1_wd2_51(31) & uppol1_wd2_51(31) & uppol1_wd2_51(31) & uppol1_wd2_51(31) & uppol1_wd2_51(31) & uppol1_wd2_51(31) & uppol1_wd2_51(31) & uppol1_wd2_51(31) & uppol1_wd2_51(31) & uppol1_wd2_51(31) & uppol1_wd2_51(31) & uppol1_wd2_51(31) & uppol1_wd2_51(31) & uppol1_wd2_51(31) & uppol1_wd2_51(31) & uppol1_wd2_51(31) & uppol1_wd2_51(31) & uppol1_wd2_51(31) & uppol1_wd2_51(31) & uppol1_wd2_51(31) & uppol1_wd2_51(31) & uppol1_wd2_51(31) & uppol1_wd2_51(31) & uppol1_wd2_51(31) & uppol1_wd2_51(31) & uppol1_wd2_51(31) & uppol1_wd2_51(31) & uppol1_wd2_51(31) & uppol1_wd2_51(31) & uppol1_wd2_51(31) & uppol1_wd2_51(31) & uppol1_wd2_51(31 downto 6)) or
(repeat(64, sig_1227) and filtez_zl) or
(repeat(64, sig_921) and filtep_pl_14(46) & filtep_pl_14(46) & filtep_pl_14(46) & filtep_pl_14(46) & filtep_pl_14(46) & filtep_pl_14(46) & filtep_pl_14(46) & filtep_pl_14(46) & filtep_pl_14(46) & filtep_pl_14(46) & filtep_pl_14(46) & filtep_pl_14(46) & filtep_pl_14(46) & filtep_pl_14(46) & filtep_pl_14(46) & filtep_pl_14(46) & filtep_pl_14(46) & filtep_pl_14(46) & filtep_pl_14(46) & filtep_pl_14(46) & filtep_pl_14(46) & filtep_pl_14(46) & filtep_pl_14(46) & filtep_pl_14(46) & filtep_pl_14(46) & filtep_pl_14(46) & filtep_pl_14(46) & filtep_pl_14(46) & filtep_pl_14(46) & filtep_pl_14(46) & filtep_pl_14(46) & filtep_pl_14(46) & filtep_pl_14(46 downto 15)) or
(repeat(64, sig_927) and uppol2_wd4_42(31) & uppol2_wd4_42(31) & uppol2_wd4_42(31) & uppol2_wd4_42(31) & uppol2_wd4_42(31) & uppol2_wd4_42(31) & uppol2_wd4_42(31) & uppol2_wd4_42(31) & uppol2_wd4_42(31) & uppol2_wd4_42(31) & uppol2_wd4_42(31) & uppol2_wd4_42(31) & uppol2_wd4_42(31) & uppol2_wd4_42(31) & uppol2_wd4_42(31) & uppol2_wd4_42(31) & uppol2_wd4_42(31) & uppol2_wd4_42(31) & uppol2_wd4_42(31) & uppol2_wd4_42(31) & uppol2_wd4_42(31) & uppol2_wd4_42(31) & uppol2_wd4_42(31) & uppol2_wd4_42(31) & uppol2_wd4_42(31) & uppol2_wd4_42(31) & uppol2_wd4_42(31) & uppol2_wd4_42(31) & uppol2_wd4_42(31) & uppol2_wd4_42(31) & uppol2_wd4_42(31) & uppol2_wd4_42(31) & uppol2_wd4_42) or
(repeat(64, sig_954) and rl(31) & rl(31) & rl(31) & rl(31) & rl(31) & rl(31) & rl(31) & rl(31) & rl(31) & rl(31) & rl(31) & rl(31) & rl(31) & rl(31) & rl(31) & rl(31) & rl(31) & rl(31) & rl(31) & rl(31) & rl(31) & rl(31) & rl(31) & rl(31) & rl(31) & rl(31) & rl(31) & rl(31) & rl(31) & rl(31) & rl(31) & rl(31) & rl);
-- Behaviour of component 'mux_341' model 'mux'
mux_341 <=
(repeat(64, sig_1045) and abs_m_3(31) & abs_m_3(31) & abs_m_3(31) & abs_m_3(31) & abs_m_3(31) & abs_m_3(31) & abs_m_3(31) & abs_m_3(31) & abs_m_3(31) & abs_m_3(31) & abs_m_3(31) & abs_m_3(31) & abs_m_3(31) & abs_m_3(31) & abs_m_3(31) & abs_m_3(31) & abs_m_3(31) & abs_m_3(31) & abs_m_3(31) & abs_m_3(31) & abs_m_3(31) & abs_m_3(31) & abs_m_3(31) & abs_m_3(31) & abs_m_3(31) & abs_m_3(31) & abs_m_3(31) & abs_m_3(31) & abs_m_3(31) & abs_m_3(31) & abs_m_3(31) & abs_m_3(31) & abs_m_3) or
(repeat(64, sig_1094) and uppol1_apl1_53(31) & uppol1_apl1_53(31) & uppol1_apl1_53(31) & uppol1_apl1_53(31) & uppol1_apl1_53(31) & uppol1_apl1_53(31) & uppol1_apl1_53(31) & uppol1_apl1_53(31) & uppol1_apl1_53(31) & uppol1_apl1_53(31) & uppol1_apl1_53(31) & uppol1_apl1_53(31) & uppol1_apl1_53(31) & uppol1_apl1_53(31) & uppol1_apl1_53(31) & uppol1_apl1_53(31) & uppol1_apl1_53(31) & uppol1_apl1_53(31) & uppol1_apl1_53(31) & uppol1_apl1_53(31) & uppol1_apl1_53(31) & uppol1_apl1_53(31) & uppol1_apl1_53(31) & uppol1_apl1_53(31) & uppol1_apl1_53(31) & uppol1_apl1_53(31) & uppol1_apl1_53(31) & uppol1_apl1_53(31) & uppol1_apl1_53(31) & uppol1_apl1_53(31) & uppol1_apl1_53(31) & uppol1_apl1_53(31) & uppol1_apl1_53) or
(repeat(64, sig_1142) and uppol2_apl2_43(31) & uppol2_apl2_43(31) & uppol2_apl2_43(31) & uppol2_apl2_43(31) & uppol2_apl2_43(31) & uppol2_apl2_43(31) & uppol2_apl2_43(31) & uppol2_apl2_43(31) & uppol2_apl2_43(31) & uppol2_apl2_43(31) & uppol2_apl2_43(31) & uppol2_apl2_43(31) & uppol2_apl2_43(31) & uppol2_apl2_43(31) & uppol2_apl2_43(31) & uppol2_apl2_43(31) & uppol2_apl2_43(31) & uppol2_apl2_43(31) & uppol2_apl2_43(31) & uppol2_apl2_43(31) & uppol2_apl2_43(31) & uppol2_apl2_43(31) & uppol2_apl2_43(31) & uppol2_apl2_43(31) & uppol2_apl2_43(31) & uppol2_apl2_43(31) & uppol2_apl2_43(31) & uppol2_apl2_43(31) & uppol2_apl2_43(31) & uppol2_apl2_43(31) & uppol2_apl2_43(31) & uppol2_apl2_43(31) & uppol2_apl2_43) or
(repeat(64, sig_1015) and "0000000000000000000000000000000000000000000000000000000000001010");
-- Behaviour of component 'mux_342' model 'mux'
mux_342 <=
(repeat(64, sig_1045) and encode_decis_69(31) & encode_decis_69(31) & encode_decis_69(31) & encode_decis_69(31) & encode_decis_69(31) & encode_decis_69(31) & encode_decis_69(31) & encode_decis_69(31) & encode_decis_69(31) & encode_decis_69(31) & encode_decis_69(31) & encode_decis_69(31) & encode_decis_69(31) & encode_decis_69(31) & encode_decis_69(31) & encode_decis_69(31) & encode_decis_69(31) & encode_decis_69(31) & encode_decis_69(31) & encode_decis_69(31) & encode_decis_69(31) & encode_decis_69(31) & encode_decis_69(31) & encode_decis_69(31) & encode_decis_69(31) & encode_decis_69(31) & encode_decis_69(31) & encode_decis_69(31) & encode_decis_69(31) & encode_decis_69(31) & encode_decis_69(31) & encode_decis_69(31) & encode_decis_69) or
(repeat(64, sig_1094) and sig_1307(31) & sig_1307(31) & sig_1307(31) & sig_1307(31) & sig_1307(31) & sig_1307(31) & sig_1307(31) & sig_1307(31) & sig_1307(31) & sig_1307(31) & sig_1307(31) & sig_1307(31) & sig_1307(31) & sig_1307(31) & sig_1307(31) & sig_1307(31) & sig_1307(31) & sig_1307(31) & sig_1307(31) & sig_1307(31) & sig_1307(31) & sig_1307(31) & sig_1307(31) & sig_1307(31) & sig_1307(31) & sig_1307(31) & sig_1307(31) & sig_1307(31) & sig_1307(31) & sig_1307(31) & sig_1307(31) & sig_1307(31) & sig_1307(31 downto 0)) or
(repeat(64, sig_1142) and "1111111111111111111111111111111111111111111111111101000000000000") or
(repeat(64, sig_1015) and sig_1307(5) & sig_1307(5) & sig_1307(5) & sig_1307(5) & sig_1307(5) & sig_1307(5) & sig_1307(5) & sig_1307(5) & sig_1307(5) & sig_1307(5) & sig_1307(5) & sig_1307(5) & sig_1307(5) & sig_1307(5) & sig_1307(5) & sig_1307(5) & sig_1307(5) & sig_1307(5) & sig_1307(5) & sig_1307(5) & sig_1307(5) & sig_1307(5) & sig_1307(5) & sig_1307(5) & sig_1307(5) & sig_1307(5) & sig_1307(5) & sig_1307(5) & sig_1307(5) & sig_1307(5) & sig_1307(5) & sig_1307(5) & sig_1307(5) & sig_1307(5) & sig_1307(5) & sig_1307(5) & sig_1307(5) & sig_1307(5) & sig_1307(5) & sig_1307(5) & sig_1307(5) & sig_1307(5) & sig_1307(5) & sig_1307(5) & sig_1307(5) & sig_1307(5) & sig_1307(5) & sig_1307(5) & sig_1307(5) & sig_1307(5) & sig_1307(5) & sig_1307(5) & sig_1307(5) & sig_1307(5) & sig_1307(5) & sig_1307(5) & sig_1307(5) & sig_1307(5) & sig_1307(5 downto 0));
-- Behaviour of component 'mux_338' model 'mux'
mux_338 <=
(repeat(32, sig_1257) and dec_dh);
-- Behaviour of component 'mux_336' model 'mux'
mux_336 <=
(repeat(32, sig_1257) and dec_del_dhx_reg0);
-- Behaviour of component 'mux_320' model 'mux'
mux_320 <=
(repeat(32, sig_932) and sig_1291(31) & sig_1291(31) & sig_1291(31) & sig_1291(31) & sig_1291(31) & sig_1291(31) & sig_1291(31) & sig_1291(31) & sig_1291(31 downto 8)) or
(repeat(32, sig_1161) and sig_1298(31 downto 0));
-- Behaviour of component 'mux_322' model 'mux'
mux_322 <=
(repeat(32, sig_932) and sig_1287(31) & sig_1287(31) & sig_1287(31) & sig_1287(31) & sig_1287(31) & sig_1287(31) & sig_1287(31) & sig_1287(31) & sig_1287(31 downto 8)) or
(repeat(32, sig_974) and sig_1298(31 downto 0));
-- Behaviour of component 'mux_324' model 'mux'
mux_324 <=
(repeat(32, sig_861) and sig_1298(31 downto 0)) or
(repeat(32, sig_932) and sig_1281(31) & sig_1281(31) & sig_1281(31) & sig_1281(31) & sig_1281(31) & sig_1281(31) & sig_1281(31) & sig_1281(31) & sig_1281(31 downto 8));
-- Behaviour of component 'mux_326' model 'mux'
mux_326 <=
(repeat(32, sig_862) and sig_1298(31 downto 0)) or
(repeat(32, sig_932) and sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31 downto 8));
-- Behaviour of component 'mux_310' model 'mux'
mux_310 <=
(repeat(32, sig_895) and dec_dlt);
-- Behaviour of component 'mux_314' model 'mux'
mux_314 <=
(repeat(33, sig_927) and plt(31) & plt) or
(repeat(33, sig_911) and dec_detl(31) & dec_detl) or
(repeat(33, sig_1133) and dec_al2(31) & dec_al2) or
(repeat(33, sig_932) and dec_del_bph_reg1(31) & dec_del_bph_reg1) or
(repeat(33, sig_1153) and al1(31) & al1) or
(repeat(33, sig_1241) and rlt2(30) & rlt2 & '0') or
(repeat(33, sig_1053) and dec_del_bpl_reg1(31) & dec_del_bpl_reg1) or
(repeat(33, sig_1112) and delay_bph_reg4(31) & delay_bph_reg4) or
(repeat(33, sig_1125) and delay_bpl_reg4(31) & delay_bpl_reg4) or
(repeat(33, sig_895) and dec_al1(31) & dec_al1) or
(repeat(33, sig_868) and rlt1(30) & rlt1 & '0');
-- Behaviour of component 'mux_315' model 'mux'
mux_315 <=
(repeat(32, sig_1133) and "00000000000000000000000001111111") or
(repeat(32, sig_1150) and "00000000000000000000000011111111") or
(repeat(32, sig_1241) and al2) or
(repeat(32, sig_868) and al1) or
(repeat(32, sig_911) and sig_1315) or
(repeat(32, sig_927) and plt1);
-- Behaviour of component 'mux_316' model 'mux'
mux_316 <=
(repeat(32, sig_932) and sig_1292(31) & sig_1292(31) & sig_1292(31) & sig_1292(31) & sig_1292(31) & sig_1292(31) & sig_1292(31) & sig_1292(31) & sig_1292(31 downto 8)) or
(repeat(32, sig_1171) and sig_1298(31 downto 0));
-- Behaviour of component 'mux_318' model 'mux'
mux_318 <=
(repeat(32, sig_890) and sig_1298(31 downto 0)) or
(repeat(32, sig_932) and sig_1303(31) & sig_1303(31) & sig_1303(31) & sig_1303(31) & sig_1303(31) & sig_1303(31) & sig_1303(31) & sig_1303(31) & sig_1303(31 downto 8));
-- Behaviour of component 'mux_308' model 'mux'
mux_308 <=
(repeat(32, sig_895) and dec_del_dltx_reg0);
-- Behaviour of component 'mux_292' model 'mux'
mux_292 <=
(repeat(32, sig_1017) and sig_1298(31 downto 0)) or
(repeat(32, sig_1053) and sig_1291(31) & sig_1291(31) & sig_1291(31) & sig_1291(31) & sig_1291(31) & sig_1291(31) & sig_1291(31) & sig_1291(31) & sig_1291(31 downto 8));
-- Behaviour of component 'mux_294' model 'mux'
mux_294 <=
(repeat(32, sig_1053) and sig_1287(31) & sig_1287(31) & sig_1287(31) & sig_1287(31) & sig_1287(31) & sig_1287(31) & sig_1287(31) & sig_1287(31) & sig_1287(31 downto 8)) or
(repeat(32, sig_1268) and sig_1298(31 downto 0));
-- Behaviour of component 'mux_296' model 'mux'
mux_296 <=
(repeat(32, sig_871) and sig_1298(31 downto 0)) or
(repeat(32, sig_1053) and sig_1281(31) & sig_1281(31) & sig_1281(31) & sig_1281(31) & sig_1281(31) & sig_1281(31) & sig_1281(31) & sig_1281(31) & sig_1281(31 downto 8));
-- Behaviour of component 'mux_298' model 'mux'
mux_298 <=
(repeat(32, sig_1053) and sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31 downto 8)) or
(repeat(32, sig_1262) and sig_1298(31 downto 0));
-- Behaviour of component 'mux_290' model 'mux'
mux_290 <=
(repeat(32, sig_1053) and sig_1303(31) & sig_1303(31) & sig_1303(31) & sig_1303(31) & sig_1303(31) & sig_1303(31) & sig_1303(31) & sig_1303(31) & sig_1303(31 downto 8)) or
(repeat(32, sig_1174) and sig_1298(31 downto 0));
-- Behaviour of component 'mux_286' model 'mux'
mux_286 <=
(repeat(32, sig_864) and sig_1298(31 downto 0)) or
(repeat(32, sig_1112) and sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31 downto 8));
-- Behaviour of component 'mux_288' model 'mux'
mux_288 <=
(repeat(32, sig_936) and sig_1298(31 downto 0)) or
(repeat(32, sig_1053) and sig_1292(31) & sig_1292(31) & sig_1292(31) & sig_1292(31) & sig_1292(31) & sig_1292(31) & sig_1292(31) & sig_1292(31) & sig_1292(31 downto 8));
-- Behaviour of component 'mux_284' model 'mux'
mux_284 <=
(repeat(32, sig_1112) and sig_1291(31) & sig_1291(31) & sig_1291(31) & sig_1291(31) & sig_1291(31) & sig_1291(31) & sig_1291(31) & sig_1291(31) & sig_1291(31 downto 8)) or
(repeat(32, sig_1280) and sig_1298(31 downto 0));
-- Behaviour of component 'mux_278' model 'mux'
mux_278 <=
(repeat(32, sig_875) and sig_1298(31 downto 0)) or
(repeat(32, sig_1112) and sig_1281(31) & sig_1281(31) & sig_1281(31) & sig_1281(31) & sig_1281(31) & sig_1281(31) & sig_1281(31) & sig_1281(31) & sig_1281(31 downto 8));
-- Behaviour of component 'mux_280' model 'mux'
mux_280 <=
(repeat(32, sig_1000) and sig_1298(31 downto 0)) or
(repeat(32, sig_1112) and sig_1287(31) & sig_1287(31) & sig_1287(31) & sig_1287(31) & sig_1287(31) & sig_1287(31) & sig_1287(31) & sig_1287(31) & sig_1287(31 downto 8));
-- Behaviour of component 'mux_282' model 'mux'
mux_282 <=
(repeat(32, sig_863) and sig_1298(31 downto 0)) or
(repeat(32, sig_1112) and sig_1292(31) & sig_1292(31) & sig_1292(31) & sig_1292(31) & sig_1292(31) & sig_1292(31) & sig_1292(31) & sig_1292(31) & sig_1292(31 downto 8));
-- Behaviour of component 'mux_272' model 'mux'
mux_272 <=
(repeat(32, sig_997) and delay_dhx_reg0);
-- Behaviour of component 'mux_274' model 'mux'
mux_274 <=
(repeat(32, sig_997) and dh);
-- Behaviour of component 'mux_276' model 'mux'
mux_276 <=
(repeat(32, sig_1092) and sig_1298(31 downto 0)) or
(repeat(32, sig_1112) and sig_1303(31) & sig_1303(31) & sig_1303(31) & sig_1303(31) & sig_1303(31) & sig_1303(31) & sig_1303(31) & sig_1303(31) & sig_1303(31 downto 8));
-- Behaviour of component 'mux_262' model 'mux'
mux_262 <=
(repeat(32, sig_1153) and dlt);
-- Behaviour of component 'mux_260' model 'mux'
mux_260 <=
(repeat(32, sig_1153) and delay_dltx_reg0);
-- Behaviour of component 'mux_250' model 'mux'
mux_250 <=
(repeat(32, sig_923) and sig_1298(31 downto 0)) or
(repeat(32, sig_1125) and sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31 downto 8));
-- Behaviour of component 'mux_248' model 'mux'
mux_248 <=
(repeat(32, sig_1042) and sig_1298(31 downto 0)) or
(repeat(32, sig_1125) and sig_1291(31) & sig_1291(31) & sig_1291(31) & sig_1291(31) & sig_1291(31) & sig_1291(31) & sig_1291(31) & sig_1291(31) & sig_1291(31 downto 8));
-- Behaviour of component 'mux_244' model 'mux'
mux_244 <=
(repeat(32, sig_1036) and sig_1298(31 downto 0)) or
(repeat(32, sig_1125) and sig_1287(31) & sig_1287(31) & sig_1287(31) & sig_1287(31) & sig_1287(31) & sig_1287(31) & sig_1287(31) & sig_1287(31) & sig_1287(31 downto 8));
-- Behaviour of component 'mux_246' model 'mux'
mux_246 <=
(repeat(32, sig_1040) and sig_1298(31 downto 0)) or
(repeat(32, sig_1125) and sig_1292(31) & sig_1292(31) & sig_1292(31) & sig_1292(31) & sig_1292(31) & sig_1292(31) & sig_1292(31) & sig_1292(31) & sig_1292(31 downto 8));
-- Behaviour of component 'mux_242' model 'mux'
mux_242 <=
(repeat(32, sig_1086) and sig_1298(31 downto 0)) or
(repeat(32, sig_1125) and sig_1281(31) & sig_1281(31) & sig_1281(31) & sig_1281(31) & sig_1281(31) & sig_1281(31) & sig_1281(31) & sig_1281(31) & sig_1281(31 downto 8));
-- Behaviour of component 'mux_238' model 'mux'
mux_238 <=
(repeat(32, sig_1008) and xd);
-- Behaviour of component 'mux_240' model 'mux'
mux_240 <=
(repeat(32, sig_1199) and sig_1298(31 downto 0)) or
(repeat(32, sig_1125) and sig_1303(31) & sig_1303(31) & sig_1303(31) & sig_1303(31) & sig_1303(31) & sig_1303(31) & sig_1303(31) & sig_1303(31) & sig_1303(31 downto 8));
-- Behaviour of component 'mux_236' model 'mux'
mux_236 <=
(repeat(32, sig_1008) and accumc_reg0);
-- Behaviour of component 'mux_232' model 'mux'
mux_232 <=
(repeat(32, sig_1008) and accumc_reg2);
-- Behaviour of component 'mux_234' model 'mux'
mux_234 <=
(repeat(32, sig_1008) and accumc_reg1);
-- Behaviour of component 'mux_230' model 'mux'
mux_230 <=
(repeat(32, sig_1008) and accumc_reg3);
-- Behaviour of component 'mux_226' model 'mux'
mux_226 <=
(repeat(32, sig_1008) and accumc_reg5);
-- Behaviour of component 'mux_228' model 'mux'
mux_228 <=
(repeat(32, sig_1008) and accumc_reg4);
-- Behaviour of component 'mux_224' model 'mux'
mux_224 <=
(repeat(32, sig_1008) and accumc_reg6);
-- Behaviour of component 'mux_220' model 'mux'
mux_220 <=
(repeat(32, sig_1008) and accumc_reg8);
-- Behaviour of component 'mux_222' model 'mux'
mux_222 <=
(repeat(32, sig_1008) and accumc_reg7);
-- Behaviour of component 'mux_218' model 'mux'
mux_218 <=
(repeat(32, sig_1008) and accumc_reg9);
-- Behaviour of component 'mux_214' model 'mux'
mux_214 <=
(repeat(32, sig_1008) and accumd_reg0);
-- Behaviour of component 'mux_216' model 'mux'
mux_216 <=
(repeat(32, sig_1008) and xs);
-- Behaviour of component 'mux_212' model 'mux'
mux_212 <=
(repeat(32, sig_1008) and accumd_reg1);
-- Behaviour of component 'mux_208' model 'mux'
mux_208 <=
(repeat(32, sig_1008) and accumd_reg3);
-- Behaviour of component 'mux_210' model 'mux'
mux_210 <=
(repeat(32, sig_1008) and accumd_reg2);
-- Behaviour of component 'mux_206' model 'mux'
mux_206 <=
(repeat(32, sig_1008) and accumd_reg4);
-- Behaviour of component 'mux_202' model 'mux'
mux_202 <=
(repeat(32, sig_1008) and accumd_reg6);
-- Behaviour of component 'mux_204' model 'mux'
mux_204 <=
(repeat(32, sig_1008) and accumd_reg5);
-- Behaviour of component 'mux_200' model 'mux'
mux_200 <=
(repeat(32, sig_1008) and accumd_reg7);
-- Behaviour of component 'mux_196' model 'mux'
mux_196 <=
(repeat(32, sig_1008) and accumd_reg9);
-- Behaviour of component 'mux_198' model 'mux'
mux_198 <=
(repeat(32, sig_1008) and accumd_reg8);
-- Behaviour of component 'mux_194' model 'mux'
mux_194 <=
(repeat(32, sig_1175) and tqmf_reg6);
-- Behaviour of component 'mux_190' model 'mux'
mux_190 <=
(repeat(32, sig_1175) and tqmf_reg8);
-- Behaviour of component 'mux_192' model 'mux'
mux_192 <=
(repeat(32, sig_1175) and tqmf_reg7);
-- Behaviour of component 'mux_188' model 'mux'
mux_188 <=
(repeat(32, sig_1175) and tqmf_reg9);
-- Behaviour of component 'mux_184' model 'mux'
mux_184 <=
(repeat(32, sig_1175) and tqmf_reg11);
-- Behaviour of component 'mux_186' model 'mux'
mux_186 <=
(repeat(32, sig_1175) and tqmf_reg10);
-- Behaviour of component 'mux_182' model 'mux'
mux_182 <=
(repeat(32, sig_1175) and tqmf_reg12);
-- Behaviour of component 'mux_178' model 'mux'
mux_178 <=
(repeat(32, sig_1175) and tqmf_reg14);
-- Behaviour of component 'mux_180' model 'mux'
mux_180 <=
(repeat(32, sig_1175) and tqmf_reg13);
-- Behaviour of component 'mux_176' model 'mux'
mux_176 <=
(repeat(32, sig_1175) and tqmf_reg15);
-- Behaviour of component 'mux_172' model 'mux'
mux_172 <=
(repeat(32, sig_1175) and tqmf_reg17);
-- Behaviour of component 'mux_174' model 'mux'
mux_174 <=
(repeat(32, sig_1175) and tqmf_reg16);
-- Behaviour of component 'mux_170' model 'mux'
mux_170 <=
(repeat(32, sig_1175) and tqmf_reg18);
-- Behaviour of component 'mux_166' model 'mux'
mux_166 <=
(repeat(32, sig_1175) and tqmf_reg20);
-- Behaviour of component 'mux_168' model 'mux'
mux_168 <=
(repeat(32, sig_1175) and tqmf_reg19);
-- Behaviour of component 'mux_164' model 'mux'
mux_164 <=
(repeat(32, sig_1175) and tqmf_reg21);
-- Behaviour of component 'not_709' model 'not'
not_709 <= not (
sig_1303(31)
);
-- Behaviour of component 'or_710' model 'or'
or_710 <=
and_713 or
and_711;
-- Behaviour of component 'or_692' model 'or'
or_692 <=
sig_1303(31) & "0000000" or
not_693 & "0000000";
-- Behaviour of component 'not_693' model 'not'
not_693 <= not (
sig_1303(31)
);
-- Behaviour of component 'not_768' model 'not'
not_768 <= not (
sig_1303(31)
);
-- Behaviour of component 'or_769' model 'or'
or_769 <=
and_771 or
and_770;
-- Behaviour of component 'and_770' model 'and'
and_770 <=
uppol1_wd3_52 and
sig_1299 & sig_1299 & sig_1299 & sig_1299 & sig_1299 & sig_1299 & sig_1299 & sig_1299 & sig_1299 & sig_1299 & sig_1299 & sig_1299 & sig_1299 & sig_1299 & sig_1299 & sig_1299 & sig_1299 & sig_1299 & sig_1299 & sig_1299 & sig_1299 & sig_1299 & sig_1299 & sig_1299 & sig_1299 & sig_1299 & sig_1299 & sig_1299 & sig_1299 & sig_1299 & sig_1299 & sig_1299;
-- Behaviour of component 'and_771' model 'and'
and_771 <=
uppol1_apl1_53 and
sig_1306 & sig_1306 & sig_1306 & sig_1306 & sig_1306 & sig_1306 & sig_1306 & sig_1306 & sig_1306 & sig_1306 & sig_1306 & sig_1306 & sig_1306 & sig_1306 & sig_1306 & sig_1306 & sig_1306 & sig_1306 & sig_1306 & sig_1306 & sig_1306 & sig_1306 & sig_1306 & sig_1306 & sig_1306 & sig_1306 & sig_1306 & sig_1306 & sig_1306 & sig_1306 & sig_1306 & sig_1306;
-- Behaviour of component 'or_619' model 'or'
or_619 <=
sig_1303(31) & "0000000" or
not_620 & "0000000";
-- Behaviour of component 'not_620' model 'not'
not_620 <= not (
sig_1303(31)
);
-- Behaviour of component 'or_621' model 'or'
or_621 <=
sig_1304(31) & "0000000" or
not_622 & "0000000";
-- Behaviour of component 'not_622' model 'not'
not_622 <= not (
sig_1304(31)
);
-- Behaviour of component 'or_623' model 'or'
or_623 <=
sig_1303(31) & "0000000" or
not_624 & "0000000";
-- Behaviour of component 'not_624' model 'not'
not_624 <= not (
sig_1303(31)
);
-- Behaviour of component 'or_625' model 'or'
or_625 <=
sig_1304(31) & "0000000" or
not_626 & "0000000";
-- Behaviour of component 'not_626' model 'not'
not_626 <= not (
sig_1304(31)
);
-- Behaviour of component 'or_627' model 'or'
or_627 <=
sig_1304(31) & "0000000" or
not_628 & "0000000";
-- Behaviour of component 'and_633' model 'and'
and_633 <=
uppol2_apl2_43 and
sig_1306 & sig_1306 & sig_1306 & sig_1306 & sig_1306 & sig_1306 & sig_1306 & sig_1306 & sig_1306 & sig_1306 & sig_1306 & sig_1306 & sig_1306 & sig_1306 & sig_1306 & sig_1306 & sig_1306 & sig_1306 & sig_1306 & sig_1306 & sig_1306 & sig_1306 & sig_1306 & sig_1306 & sig_1306 & sig_1306 & sig_1306 & sig_1306 & sig_1306 & sig_1306 & sig_1306 & sig_1306;
-- Behaviour of component 'not_628' model 'not'
not_628 <= not (
sig_1304(31)
);
-- Behaviour of component 'or_629' model 'or'
or_629 <=
sig_1304(31) & "0000000" or
not_630 & "0000000";
-- Behaviour of component 'not_630' model 'not'
not_630 <= not (
sig_1304(31)
);
-- Behaviour of component 'or_631' model 'or'
or_631 <=
and_633 or
and_632;
-- Behaviour of component 'or_634' model 'or'
or_634 <=
sig_1304(31) & "0000000" or
not_635 & "0000000";
-- Behaviour of component 'not_635' model 'not'
not_635 <= not (
sig_1304(31)
);
-- Behaviour of component 'or_636' model 'or'
or_636 <=
sig_1292(31) & "0000000" or
not_637 & "0000000";
-- Behaviour of component 'not_637' model 'not'
not_637 <= not (
sig_1292(31)
);
-- Behaviour of component 'and_632' model 'and'
and_632 <=
"00000000000000000011000000000000" and
sig_1299 & sig_1299 & sig_1299 & sig_1299 & sig_1299 & sig_1299 & sig_1299 & sig_1299 & sig_1299 & sig_1299 & sig_1299 & sig_1299 & sig_1299 & sig_1299 & sig_1299 & sig_1299 & sig_1299 & sig_1299 & sig_1299 & sig_1299 & sig_1299 & sig_1299 & sig_1299 & sig_1299 & sig_1299 & sig_1299 & sig_1299 & sig_1299 & sig_1299 & sig_1299 & sig_1299 & sig_1299;
-- Behaviour of component 'or_641' model 'or'
or_641 <=
and_643 or
and_642;
-- Behaviour of component 'and_640' model 'and'
and_640 <=
logsch_nbh_57 and
sig_1306 & sig_1306 & sig_1306 & sig_1306 & sig_1306 & sig_1306 & sig_1306 & sig_1306 & sig_1306 & sig_1306 & sig_1306 & sig_1306 & sig_1306 & sig_1306 & sig_1306 & sig_1306 & sig_1306 & sig_1306 & sig_1306 & sig_1306 & sig_1306 & sig_1306 & sig_1306 & sig_1306 & sig_1306 & sig_1306 & sig_1306 & sig_1306 & sig_1306 & sig_1306 & sig_1306 & sig_1306;
-- Behaviour of component 'and_645' model 'and'
and_645 <=
sig_1288(25 downto 0) & uppol1_wd2_51(5 downto 0) and
not_646 & not_646 & not_646 & not_646 & not_646 & not_646 & not_646 & not_646 & not_646 & not_646 & not_646 & not_646 & not_646 & not_646 & not_646 & not_646 & not_646 & not_646 & not_646 & not_646 & not_646 & not_646 & not_646 & not_646 & not_646 & not_646 & not_646 & not_646 & not_646 & not_646 & not_646 & not_646;
-- Behaviour of component 'and_639' model 'and'
and_639 <=
"00000000000000000101100000000000" and
sig_1299 & sig_1299 & sig_1299 & sig_1299 & sig_1299 & sig_1299 & sig_1299 & sig_1299 & sig_1299 & sig_1299 & sig_1299 & sig_1299 & sig_1299 & sig_1299 & sig_1299 & sig_1299 & sig_1299 & sig_1299 & sig_1299 & sig_1299 & sig_1299 & sig_1299 & sig_1299 & sig_1299 & sig_1299 & sig_1299 & sig_1299 & sig_1299 & sig_1299 & sig_1299 & sig_1299 & sig_1299;
-- Behaviour of component 'and_643' model 'and'
and_643 <=
uppol2_apl2_43 and
sig_1317 & sig_1317 & sig_1317 & sig_1317 & sig_1317 & sig_1317 & sig_1317 & sig_1317 & sig_1317 & sig_1317 & sig_1317 & sig_1317 & sig_1317 & sig_1317 & sig_1317 & sig_1317 & sig_1317 & sig_1317 & sig_1317 & sig_1317 & sig_1317 & sig_1317 & sig_1317 & sig_1317 & sig_1317 & sig_1317 & sig_1317 & sig_1317 & sig_1317 & sig_1317 & sig_1317 & sig_1317;
-- Behaviour of component 'and_650' model 'and'
and_650 <=
logscl_nbl_27 and
sig_1306 & sig_1306 & sig_1306 & sig_1306 & sig_1306 & sig_1306 & sig_1306 & sig_1306 & sig_1306 & sig_1306 & sig_1306 & sig_1306 & sig_1306 & sig_1306 & sig_1306 & sig_1306 & sig_1306 & sig_1306 & sig_1306 & sig_1306 & sig_1306 & sig_1306 & sig_1306 & sig_1306 & sig_1306 & sig_1306 & sig_1306 & sig_1306 & sig_1306 & sig_1306 & sig_1306 & sig_1306;
-- Behaviour of component 'or_651' model 'or'
or_651 <=
and_653 or
and_652;
-- Behaviour of component 'or_644' model 'or'
or_644 <=
and_647 or
and_645;
-- Behaviour of component 'and_649' model 'and'
and_649 <=
"00000000000000000100100000000000" and
sig_1299 & sig_1299 & sig_1299 & sig_1299 & sig_1299 & sig_1299 & sig_1299 & sig_1299 & sig_1299 & sig_1299 & sig_1299 & sig_1299 & sig_1299 & sig_1299 & sig_1299 & sig_1299 & sig_1299 & sig_1299 & sig_1299 & sig_1299 & sig_1299 & sig_1299 & sig_1299 & sig_1299 & sig_1299 & sig_1299 & sig_1299 & sig_1299 & sig_1299 & sig_1299 & sig_1299 & sig_1299;
-- Behaviour of component 'mux_498' model 'mux'
mux_498 <=
(repeat(32, sig_1133) and dec_plt);
-- Behaviour of component 'mux_500' model 'mux'
mux_500 <=
(repeat(32, sig_895) and dec_plt1);
-- Behaviour of component 'mux_502' model 'mux'
mux_502 <=
(repeat(32, sig_990) and "00000000000000000000000000001000") or
(repeat(32, sig_1101) and scalel_wd3_35 & "000");
-- Behaviour of component 'mux_504' model 'mux'
mux_504 <=
(repeat(32, sig_990) and "00000000000000000000000000100000") or
(repeat(32, sig_1122) and scalel_wd3_35 & "000");
-- Behaviour of component 'and_652' model 'and'
and_652 <=
uppol1_wd3_52 and
sig_1299 & sig_1299 & sig_1299 & sig_1299 & sig_1299 & sig_1299 & sig_1299 & sig_1299 & sig_1299 & sig_1299 & sig_1299 & sig_1299 & sig_1299 & sig_1299 & sig_1299 & sig_1299 & sig_1299 & sig_1299 & sig_1299 & sig_1299 & sig_1299 & sig_1299 & sig_1299 & sig_1299 & sig_1299 & sig_1299 & sig_1299 & sig_1299 & sig_1299 & sig_1299 & sig_1299 & sig_1299;
-- Behaviour of component 'and_653' model 'and'
and_653 <=
uppol1_apl1_53 and
sig_1306 & sig_1306 & sig_1306 & sig_1306 & sig_1306 & sig_1306 & sig_1306 & sig_1306 & sig_1306 & sig_1306 & sig_1306 & sig_1306 & sig_1306 & sig_1306 & sig_1306 & sig_1306 & sig_1306 & sig_1306 & sig_1306 & sig_1306 & sig_1306 & sig_1306 & sig_1306 & sig_1306 & sig_1306 & sig_1306 & sig_1306 & sig_1306 & sig_1306 & sig_1306 & sig_1306 & sig_1306;
-- Behaviour of component 'or_654' model 'or'
or_654 <=
and_656 or
and_655;
-- Behaviour of component 'and_655' model 'and'
and_655 <=
sig_1307(31 downto 0) and
sig_1301 & sig_1301 & sig_1301 & sig_1301 & sig_1301 & sig_1301 & sig_1301 & sig_1301 & sig_1301 & sig_1301 & sig_1301 & sig_1301 & sig_1301 & sig_1301 & sig_1301 & sig_1301 & sig_1301 & sig_1301 & sig_1301 & sig_1301 & sig_1301 & sig_1301 & sig_1301 & sig_1301 & sig_1301 & sig_1301 & sig_1301 & sig_1301 & sig_1301 & sig_1301 & sig_1301 & sig_1301;
-- Behaviour of component 'and_656' model 'and'
and_656 <=
uppol1_apl1_53 and
sig_1282 & sig_1282 & sig_1282 & sig_1282 & sig_1282 & sig_1282 & sig_1282 & sig_1282 & sig_1282 & sig_1282 & sig_1282 & sig_1282 & sig_1282 & sig_1282 & sig_1282 & sig_1282 & sig_1282 & sig_1282 & sig_1282 & sig_1282 & sig_1282 & sig_1282 & sig_1282 & sig_1282 & sig_1282 & sig_1282 & sig_1282 & sig_1282 & sig_1282 & sig_1282 & sig_1282 & sig_1282;
-- Behaviour of component 'or_657' model 'or'
or_657 <=
and_659 or
and_658;
-- Behaviour of component 'and_658' model 'and'
and_658 <=
"00000000000000000011000000000000" and
sig_1299 & sig_1299 & sig_1299 & sig_1299 & sig_1299 & sig_1299 & sig_1299 & sig_1299 & sig_1299 & sig_1299 & sig_1299 & sig_1299 & sig_1299 & sig_1299 & sig_1299 & sig_1299 & sig_1299 & sig_1299 & sig_1299 & sig_1299 & sig_1299 & sig_1299 & sig_1299 & sig_1299 & sig_1299 & sig_1299 & sig_1299 & sig_1299 & sig_1299 & sig_1299 & sig_1299 & sig_1299;
-- Behaviour of component 'and_659' model 'and'
and_659 <=
uppol2_apl2_43 and
sig_1306 & sig_1306 & sig_1306 & sig_1306 & sig_1306 & sig_1306 & sig_1306 & sig_1306 & sig_1306 & sig_1306 & sig_1306 & sig_1306 & sig_1306 & sig_1306 & sig_1306 & sig_1306 & sig_1306 & sig_1306 & sig_1306 & sig_1306 & sig_1306 & sig_1306 & sig_1306 & sig_1306 & sig_1306 & sig_1306 & sig_1306 & sig_1306 & sig_1306 & sig_1306 & sig_1306 & sig_1306;
-- Behaviour of component 'mux_510' model 'mux'
mux_510 <=
(repeat(31, sig_1023) and yh);
-- Behaviour of component 'mux_512' model 'mux'
mux_512 <=
(repeat(31, sig_997) and rh1);
-- Behaviour of component 'not_661' model 'not'
not_661 <= not (
sig_1303(31)
);
-- Behaviour of component 'and_665' model 'and'
and_665 <=
uppol1_apl1_53 and
sig_1282 & sig_1282 & sig_1282 & sig_1282 & sig_1282 & sig_1282 & sig_1282 & sig_1282 & sig_1282 & sig_1282 & sig_1282 & sig_1282 & sig_1282 & sig_1282 & sig_1282 & sig_1282 & sig_1282 & sig_1282 & sig_1282 & sig_1282 & sig_1282 & sig_1282 & sig_1282 & sig_1282 & sig_1282 & sig_1282 & sig_1282 & sig_1282 & sig_1282 & sig_1282 & sig_1282 & sig_1282;
-- Behaviour of component 'or_666' model 'or'
or_666 <=
and_668 or
and_667;
-- Behaviour of component 'mux_514' model 'mux'
mux_514 <=
(repeat(32, sig_1023) and ph);
-- Behaviour of component 'mux_516' model 'mux'
mux_516 <=
(repeat(32, sig_997) and ph1);
-- Behaviour of component 'mux_518' model 'mux'
mux_518 <=
(repeat(32, sig_995) and uppol1_apl1_53);
-- Behaviour of component 'mux_520' model 'mux'
mux_520 <=
(repeat(32, sig_1005) and uppol2_apl2_43);
-- Behaviour of component 'and_647' model 'and'
and_647 <=
sig_1302(31 downto 0) and
sig_1303(31) & sig_1303(31) & sig_1303(31) & sig_1303(31) & sig_1303(31) & sig_1303(31) & sig_1303(31) & sig_1303(31) & sig_1303(31) & sig_1303(31) & sig_1303(31) & sig_1303(31) & sig_1303(31) & sig_1303(31) & sig_1303(31) & sig_1303(31) & sig_1303(31) & sig_1303(31) & sig_1303(31) & sig_1303(31) & sig_1303(31) & sig_1303(31) & sig_1303(31) & sig_1303(31) & sig_1303(31) & sig_1303(31) & sig_1303(31) & sig_1303(31) & sig_1303(31) & sig_1303(31) & sig_1303(31) & sig_1303(31);
-- Behaviour of component 'and_664' model 'and'
and_664 <=
sig_1307(31 downto 0) and
sig_1301 & sig_1301 & sig_1301 & sig_1301 & sig_1301 & sig_1301 & sig_1301 & sig_1301 & sig_1301 & sig_1301 & sig_1301 & sig_1301 & sig_1301 & sig_1301 & sig_1301 & sig_1301 & sig_1301 & sig_1301 & sig_1301 & sig_1301 & sig_1301 & sig_1301 & sig_1301 & sig_1301 & sig_1301 & sig_1301 & sig_1301 & sig_1301 & sig_1301 & sig_1301 & sig_1301 & sig_1301;
-- Behaviour of component 'and_667' model 'and'
and_667 <=
"00000000000000000101100000000000" and
sig_1299 & sig_1299 & sig_1299 & sig_1299 & sig_1299 & sig_1299 & sig_1299 & sig_1299 & sig_1299 & sig_1299 & sig_1299 & sig_1299 & sig_1299 & sig_1299 & sig_1299 & sig_1299 & sig_1299 & sig_1299 & sig_1299 & sig_1299 & sig_1299 & sig_1299 & sig_1299 & sig_1299 & sig_1299 & sig_1299 & sig_1299 & sig_1299 & sig_1299 & sig_1299 & sig_1299 & sig_1299;
-- Behaviour of component 'and_670' model 'and'
and_670 <=
sig_1311 and
not_671 & not_671 & not_671 & not_671 & not_671 & not_671 & not_671 & not_671 & not_671 & not_671 & not_671 & not_671 & not_671 & not_671 & not_671 & not_671 & not_671 & not_671 & not_671 & not_671 & not_671 & not_671 & not_671 & not_671 & not_671 & not_671 & not_671 & not_671 & not_671 & not_671 & not_671 & not_671;
-- Behaviour of component 'and_672' model 'and'
and_672 <=
sig_1310 and
quantl_el_16 & quantl_el_16 & quantl_el_16 & quantl_el_16 & quantl_el_16 & quantl_el_16 & quantl_el_16 & quantl_el_16 & quantl_el_16 & quantl_el_16 & quantl_el_16 & quantl_el_16 & quantl_el_16 & quantl_el_16 & quantl_el_16 & quantl_el_16 & quantl_el_16 & quantl_el_16 & quantl_el_16 & quantl_el_16 & quantl_el_16 & quantl_el_16 & quantl_el_16 & quantl_el_16 & quantl_el_16 & quantl_el_16 & quantl_el_16 & quantl_el_16 & quantl_el_16 & quantl_el_16 & quantl_el_16 & quantl_el_16;
-- Behaviour of component 'or_674' model 'or'
or_674 <=
and_676 or
and_675;
-- Behaviour of component 'mux_528' model 'mux'
mux_528 <=
(repeat(32, sig_1069) and logsch_nbh_57);
-- Behaviour of component 'or_638' model 'or'
or_638 <=
and_640 or
and_639;
-- Behaviour of component 'and_642' model 'and'
and_642 <=
"11111111111111111101000000000000" and
sig_1284 & sig_1284 & sig_1284 & sig_1284 & sig_1284 & sig_1284 & sig_1284 & sig_1284 & sig_1284 & sig_1284 & sig_1284 & sig_1284 & sig_1284 & sig_1284 & sig_1284 & sig_1284 & sig_1284 & sig_1284 & sig_1284 & sig_1284 & sig_1284 & sig_1284 & sig_1284 & sig_1284 & sig_1284 & sig_1284 & sig_1284 & sig_1284 & sig_1284 & sig_1284 & sig_1284 & sig_1284;
-- Behaviour of component 'or_648' model 'or'
or_648 <=
and_650 or
and_649;
-- Behaviour of component 'or_669' model 'or'
or_669 <=
and_672 or
and_670;
-- Behaviour of component 'and_676' model 'and'
and_676 <=
ih and
sig_1283 & sig_1283 & sig_1283 & sig_1283 & sig_1283 & sig_1283 & sig_1283 & sig_1283 & sig_1283 & sig_1283 & sig_1283 & sig_1283 & sig_1283 & sig_1283 & sig_1283 & sig_1283 & sig_1283 & sig_1283 & sig_1283 & sig_1283 & sig_1283 & sig_1283 & sig_1283 & sig_1283 & sig_1283 & sig_1283 & sig_1283 & sig_1283 & sig_1283 & sig_1283 & sig_1283 & sig_1283;
-- Behaviour of component 'mux_532' model 'mux'
mux_532 <=
(repeat(32, sig_914) and decode_input_98(29) & decode_input_98(29) & decode_input_98(29) & decode_input_98(29) & decode_input_98(29) & decode_input_98(29) & decode_input_98(29 downto 4)) or
(repeat(32, sig_976) and or_701) or
(repeat(32, sig_1045) and or_674);
-- Behaviour of component 'mux_534' model 'mux'
mux_534 <=
(repeat(2, sig_869) and ih(1 downto 0)) or
(repeat(2, sig_1133) and decode_input_98(5 downto 4));
-- Behaviour of component 'mux_535' model 'mux'
mux_535 <=
(repeat(2, sig_869) and ih(1 downto 0)) or
(repeat(2, sig_895) and decode_input_98(5 downto 4));
-- Behaviour of component 'or_663' model 'or'
or_663 <=
and_665 or
and_664;
-- Behaviour of component 'and_668' model 'and'
and_668 <=
logsch_nbh_57 and
sig_1306 & sig_1306 & sig_1306 & sig_1306 & sig_1306 & sig_1306 & sig_1306 & sig_1306 & sig_1306 & sig_1306 & sig_1306 & sig_1306 & sig_1306 & sig_1306 & sig_1306 & sig_1306 & sig_1306 & sig_1306 & sig_1306 & sig_1306 & sig_1306 & sig_1306 & sig_1306 & sig_1306 & sig_1306 & sig_1306 & sig_1306 & sig_1306 & sig_1306 & sig_1306 & sig_1306 & sig_1306;
-- Behaviour of component 'or_679' model 'or'
or_679 <=
sig_1304(31) & "0000000" or
not_680 & "0000000";
-- Behaviour of component 'not_680' model 'not'
not_680 <= not (
sig_1304(31)
);
-- Behaviour of component 'not_682' model 'not'
not_682 <= not (
logscl_nbl_27(31)
);
-- Behaviour of component 'or_683' model 'or'
or_683 <=
sig_1303(31) & "0000000" or
not_684 & "0000000";
-- Behaviour of component 'and_686' model 'and'
and_686 <=
"00000000000000000100100000000000" and
sig_1299 & sig_1299 & sig_1299 & sig_1299 & sig_1299 & sig_1299 & sig_1299 & sig_1299 & sig_1299 & sig_1299 & sig_1299 & sig_1299 & sig_1299 & sig_1299 & sig_1299 & sig_1299 & sig_1299 & sig_1299 & sig_1299 & sig_1299 & sig_1299 & sig_1299 & sig_1299 & sig_1299 & sig_1299 & sig_1299 & sig_1299 & sig_1299 & sig_1299 & sig_1299 & sig_1299 & sig_1299;
-- Behaviour of component 'and_689' model 'and'
and_689 <=
sig_1289(25 downto 0) & uppol1_wd2_51(5 downto 0) and
not_690 & not_690 & not_690 & not_690 & not_690 & not_690 & not_690 & not_690 & not_690 & not_690 & not_690 & not_690 & not_690 & not_690 & not_690 & not_690 & not_690 & not_690 & not_690 & not_690 & not_690 & not_690 & not_690 & not_690 & not_690 & not_690 & not_690 & not_690 & not_690 & not_690 & not_690 & not_690;
-- Behaviour of component 'mux_540' model 'mux'
mux_540 <=
(repeat(32, sig_990) and "00000000000000000000000000001000") or
(repeat(32, sig_1057) and scalel_wd3_35 & "000");
-- Behaviour of component 'mux_544' model 'mux'
mux_544 <=
(repeat(32, sig_990) and "00000000000000000000000000100000") or
(repeat(32, sig_1011) and scalel_wd3_35 & "000");
-- Behaviour of component 'or_660' model 'or'
or_660 <=
sig_1303(31) & "0000000" or
not_661 & "0000000";
-- Behaviour of component 'or_677' model 'or'
or_677 <=
sig_1304(31) & "0000000" or
not_678 & "0000000";
-- Behaviour of component 'not_678' model 'not'
not_678 <= not (
sig_1304(31)
);
-- Behaviour of component 'not_684' model 'not'
not_684 <= not (
sig_1303(31)
);
-- Behaviour of component 'or_685' model 'or'
or_685 <=
and_687 or
and_686;
-- Behaviour of component 'or_688' model 'or'
or_688 <=
and_691 or
and_689;
-- Behaviour of component 'or_695' model 'or'
or_695 <=
sig_1303(31) & "0000000" or
not_696 & "0000000";
-- Behaviour of component 'not_671' model 'not'
not_671 <= not (
quantl_el_16
);
-- Behaviour of component 'not_696' model 'not'
not_696 <= not (
sig_1303(31)
);
-- Behaviour of component 'or_697' model 'or'
or_697 <=
sig_1304(31) & "0000000" or
not_698 & "0000000";
-- Behaviour of component 'not_698' model 'not'
not_698 <= not (
sig_1304(31)
);
-- Behaviour of component 'or_699' model 'or'
or_699 <=
ih(25 downto 0) or
quantl_ril_18(31 downto 6);
-- Behaviour of component 'not_703' model 'not'
not_703 <= not (
eh(31)
);
-- Behaviour of component 'mux_563' model 'mux'
mux_563 <=
(repeat(32, sig_1003) and uppol2_apl2_43);
-- Behaviour of component 'mux_549' model 'mux'
mux_549 <=
(repeat(31, sig_927) and rlt);
-- Behaviour of component 'mux_551' model 'mux'
mux_551 <=
(repeat(31, sig_1153) and rlt1);
-- Behaviour of component 'mux_557' model 'mux'
mux_557 <=
(repeat(32, sig_927) and plt);
-- Behaviour of component 'mux_559' model 'mux'
mux_559 <=
(repeat(32, sig_1153) and plt1);
-- Behaviour of component 'mux_561' model 'mux'
mux_561 <=
(repeat(32, sig_964) and uppol1_apl1_53);
-- Behaviour of component 'not_646' model 'not'
not_646 <= not (
sig_1303(31)
);
-- Behaviour of component 'and_675' model 'and'
and_675 <=
sig_1307(31 downto 0) and
sig_1299 & sig_1299 & sig_1299 & sig_1299 & sig_1299 & sig_1299 & sig_1299 & sig_1299 & sig_1299 & sig_1299 & sig_1299 & sig_1299 & sig_1299 & sig_1299 & sig_1299 & sig_1299 & sig_1299 & sig_1299 & sig_1299 & sig_1299 & sig_1299 & sig_1299 & sig_1299 & sig_1299 & sig_1299 & sig_1299 & sig_1299 & sig_1299 & sig_1299 & sig_1299 & sig_1299 & sig_1299;
-- Behaviour of component 'and_681' model 'and'
and_681 <=
logscl_nbl_27 and
not_682 & not_682 & not_682 & not_682 & not_682 & not_682 & not_682 & not_682 & not_682 & not_682 & not_682 & not_682 & not_682 & not_682 & not_682 & not_682 & not_682 & not_682 & not_682 & not_682 & not_682 & not_682 & not_682 & not_682 & not_682 & not_682 & not_682 & not_682 & not_682 & not_682 & not_682 & not_682;
-- Behaviour of component 'not_690' model 'not'
not_690 <= not (
sig_1303(31)
);
-- Behaviour of component 'and_691' model 'and'
and_691 <=
sig_1302(31 downto 0) and
sig_1303(31) & sig_1303(31) & sig_1303(31) & sig_1303(31) & sig_1303(31) & sig_1303(31) & sig_1303(31) & sig_1303(31) & sig_1303(31) & sig_1303(31) & sig_1303(31) & sig_1303(31) & sig_1303(31) & sig_1303(31) & sig_1303(31) & sig_1303(31) & sig_1303(31) & sig_1303(31) & sig_1303(31) & sig_1303(31) & sig_1303(31) & sig_1303(31) & sig_1303(31) & sig_1303(31) & sig_1303(31) & sig_1303(31) & sig_1303(31) & sig_1303(31) & sig_1303(31) & sig_1303(31) & sig_1303(31) & sig_1303(31);
-- Behaviour of component 'and_702' model 'and'
and_702 <=
"00000000000000000000000000000011" and
not_703 & not_703 & not_703 & not_703 & not_703 & not_703 & not_703 & not_703 & not_703 & not_703 & not_703 & not_703 & not_703 & not_703 & not_703 & not_703 & not_703 & not_703 & not_703 & not_703 & not_703 & not_703 & not_703 & not_703 & not_703 & not_703 & not_703 & not_703 & not_703 & not_703 & not_703 & not_703;
-- Behaviour of component 'or_705' model 'or'
or_705 <=
and_707 or
and_706;
-- Behaviour of component 'not_712' model 'not'
not_712 <= not (
el(31)
);
-- Behaviour of component 'or_717' model 'or'
or_717 <=
and_719 or
and_718;
-- Behaviour of component 'not_722' model 'not'
not_722 <= not (
sig_1303(31)
);
-- Behaviour of component 'mux_565' model 'mux'
mux_565 <=
(repeat(32, sig_891) and logscl_nbl_27);
-- Behaviour of component 'mux_567' model 'mux'
mux_567 <=
(repeat(5, sig_1031) and logscl_nbl_27(10 downto 6)) or
(repeat(5, sig_1070) and logsch_nbh_57(10 downto 6));
-- Behaviour of component 'mux_568' model 'mux'
mux_568 <=
(repeat(4, sig_914) and decode_input_98(3 downto 0)) or
(repeat(4, sig_1100) and quantl_ril_18(5 downto 2));
-- Behaviour of component 'mux_570' model 'mux'
mux_570 <=
(repeat(4, sig_914) and decode_input_98(3 downto 0)) or
(repeat(4, sig_1100) and quantl_ril_18(5 downto 2));
-- Behaviour of component 'and_687' model 'and'
and_687 <=
logscl_nbl_27 and
sig_1306 & sig_1306 & sig_1306 & sig_1306 & sig_1306 & sig_1306 & sig_1306 & sig_1306 & sig_1306 & sig_1306 & sig_1306 & sig_1306 & sig_1306 & sig_1306 & sig_1306 & sig_1306 & sig_1306 & sig_1306 & sig_1306 & sig_1306 & sig_1306 & sig_1306 & sig_1306 & sig_1306 & sig_1306 & sig_1306 & sig_1306 & sig_1306 & sig_1306 & sig_1306 & sig_1306 & sig_1306;
-- Behaviour of component 'and_704' model 'and'
and_704 <=
"00000000000000000000000000000001" and
eh(31) & eh(31) & eh(31) & eh(31) & eh(31) & eh(31) & eh(31) & eh(31) & eh(31) & eh(31) & eh(31) & eh(31) & eh(31) & eh(31) & eh(31) & eh(31) & eh(31) & eh(31) & eh(31) & eh(31) & eh(31) & eh(31) & eh(31) & eh(31) & eh(31) & eh(31) & eh(31) & eh(31) & eh(31) & eh(31) & eh(31) & eh(31);
-- Behaviour of component 'and_707' model 'and'
and_707 <=
sig_1302(31 downto 0) and
eh(31) & eh(31) & eh(31) & eh(31) & eh(31) & eh(31) & eh(31) & eh(31) & eh(31) & eh(31) & eh(31) & eh(31) & eh(31) & eh(31) & eh(31) & eh(31) & eh(31) & eh(31) & eh(31) & eh(31) & eh(31) & eh(31) & eh(31) & eh(31) & eh(31) & eh(31) & eh(31) & eh(31) & eh(31) & eh(31) & eh(31) & eh(31);
-- Behaviour of component 'and_716' model 'and'
and_716 <=
uppol2_apl2_43 and
sig_1305 & sig_1305 & sig_1305 & sig_1305 & sig_1305 & sig_1305 & sig_1305 & sig_1305 & sig_1305 & sig_1305 & sig_1305 & sig_1305 & sig_1305 & sig_1305 & sig_1305 & sig_1305 & sig_1305 & sig_1305 & sig_1305 & sig_1305 & sig_1305 & sig_1305 & sig_1305 & sig_1305 & sig_1305 & sig_1305 & sig_1305 & sig_1305 & sig_1305 & sig_1305 & sig_1305 & sig_1305;
-- Behaviour of component 'or_720' model 'or'
or_720 <=
and_723 or
and_721;
-- Behaviour of component 'and_721' model 'and'
and_721 <=
sig_1289(25 downto 0) & uppol1_wd2_51(5 downto 0) and
not_722 & not_722 & not_722 & not_722 & not_722 & not_722 & not_722 & not_722 & not_722 & not_722 & not_722 & not_722 & not_722 & not_722 & not_722 & not_722 & not_722 & not_722 & not_722 & not_722 & not_722 & not_722 & not_722 & not_722 & not_722 & not_722 & not_722 & not_722 & not_722 & not_722 & not_722 & not_722;
-- Behaviour of component 'and_724' model 'and'
and_724 <=
logscl_nbl_27 and
not_725 & not_725 & not_725 & not_725 & not_725 & not_725 & not_725 & not_725 & not_725 & not_725 & not_725 & not_725 & not_725 & not_725 & not_725 & not_725 & not_725 & not_725 & not_725 & not_725 & not_725 & not_725 & not_725 & not_725 & not_725 & not_725 & not_725 & not_725 & not_725 & not_725 & not_725 & not_725;
-- Behaviour of component 'or_730' model 'or'
or_730 <=
sig_1304(31) & "0000000" or
not_731 & "0000000";
-- Behaviour of component 'not_731' model 'not'
not_731 <= not (
sig_1304(31)
);
-- Behaviour of component 'or_732' model 'or'
or_732 <=
sig_1304(31) & "0000000" or
not_733 & "0000000";
-- Behaviour of component 'not_733' model 'not'
not_733 <= not (
sig_1304(31)
);
-- Behaviour of component 'or_734' model 'or'
or_734 <=
and_736 or
and_735;
-- Behaviour of component 'or_740' model 'or'
or_740 <=
sig_1303(31) & "0000000" or
not_741 & "0000000";
-- Behaviour of component 'not_741' model 'not'
not_741 <= not (
sig_1303(31)
);
-- Behaviour of component 'and_706' model 'and'
and_706 <=
eh and
not_703 & not_703 & not_703 & not_703 & not_703 & not_703 & not_703 & not_703 & not_703 & not_703 & not_703 & not_703 & not_703 & not_703 & not_703 & not_703 & not_703 & not_703 & not_703 & not_703 & not_703 & not_703 & not_703 & not_703 & not_703 & not_703 & not_703 & not_703 & not_703 & not_703 & not_703 & not_703;
-- Behaviour of component 'and_713' model 'and'
and_713 <=
sig_1302(31 downto 0) and
el(31) & el(31) & el(31) & el(31) & el(31) & el(31) & el(31) & el(31) & el(31) & el(31) & el(31) & el(31) & el(31) & el(31) & el(31) & el(31) & el(31) & el(31) & el(31) & el(31) & el(31) & el(31) & el(31) & el(31) & el(31) & el(31) & el(31) & el(31) & el(31) & el(31) & el(31) & el(31);
-- Behaviour of component 'and_718' model 'and'
and_718 <=
"00000000000000000011000000000000" and
sig_1299 & sig_1299 & sig_1299 & sig_1299 & sig_1299 & sig_1299 & sig_1299 & sig_1299 & sig_1299 & sig_1299 & sig_1299 & sig_1299 & sig_1299 & sig_1299 & sig_1299 & sig_1299 & sig_1299 & sig_1299 & sig_1299 & sig_1299 & sig_1299 & sig_1299 & sig_1299 & sig_1299 & sig_1299 & sig_1299 & sig_1299 & sig_1299 & sig_1299 & sig_1299 & sig_1299 & sig_1299;
-- Behaviour of component 'and_719' model 'and'
and_719 <=
uppol2_apl2_43 and
sig_1306 & sig_1306 & sig_1306 & sig_1306 & sig_1306 & sig_1306 & sig_1306 & sig_1306 & sig_1306 & sig_1306 & sig_1306 & sig_1306 & sig_1306 & sig_1306 & sig_1306 & sig_1306 & sig_1306 & sig_1306 & sig_1306 & sig_1306 & sig_1306 & sig_1306 & sig_1306 & sig_1306 & sig_1306 & sig_1306 & sig_1306 & sig_1306 & sig_1306 & sig_1306 & sig_1306 & sig_1306;
-- Behaviour of component 'not_725' model 'not'
not_725 <= not (
logscl_nbl_27(31)
);
-- Behaviour of component 'or_726' model 'or'
or_726 <=
and_729 or
and_727;
-- Behaviour of component 'mux_587' model 'mux'
mux_587 <=
(repeat(32, sig_1042) and sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & or_677) or
(repeat(32, sig_1040) and sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & or_679) or
(repeat(32, sig_1268) and sig_1303(31) & sig_1303(31) & sig_1303(31) & sig_1303(31) & sig_1303(31) & sig_1303(31) & sig_1303(31) & sig_1303(31) & sig_1303(31) & sig_1303(31) & sig_1303(31) & sig_1303(31) & sig_1303(31) & sig_1303(31) & sig_1303(31) & sig_1303(31) & sig_1303(31) & sig_1303(31) & sig_1303(31) & sig_1303(31) & sig_1303(31) & sig_1303(31) & sig_1303(31) & sig_1303(31) & or_623) or
(repeat(32, sig_1086) and sig_1303(31) & sig_1303(31) & sig_1303(31) & sig_1303(31) & sig_1303(31) & sig_1303(31) & sig_1303(31) & sig_1303(31) & sig_1303(31) & sig_1303(31) & sig_1303(31) & sig_1303(31) & sig_1303(31) & sig_1303(31) & sig_1303(31) & sig_1303(31) & sig_1303(31) & sig_1303(31) & sig_1303(31) & sig_1303(31) & sig_1303(31) & sig_1303(31) & sig_1303(31) & sig_1303(31) & or_660) or
(repeat(32, sig_1270) and sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & or_621) or
(repeat(32, sig_1280) and sig_1303(31) & sig_1303(31) & sig_1303(31) & sig_1303(31) & sig_1303(31) & sig_1303(31) & sig_1303(31) & sig_1303(31) & sig_1303(31) & sig_1303(31) & sig_1303(31) & sig_1303(31) & sig_1303(31) & sig_1303(31) & sig_1303(31) & sig_1303(31) & sig_1303(31) & sig_1303(31) & sig_1303(31) & sig_1303(31) & sig_1303(31) & sig_1303(31) & sig_1303(31) & sig_1303(31) & or_619) or
(repeat(32, sig_1161) and sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & or_634) or
(repeat(32, sig_1174) and sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & or_629) or
(repeat(32, sig_1262) and sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & or_625) or
(repeat(32, sig_1036) and sig_1303(31) & sig_1303(31) & sig_1303(31) & sig_1303(31) & sig_1303(31) & sig_1303(31) & sig_1303(31) & sig_1303(31) & sig_1303(31) & sig_1303(31) & sig_1303(31) & sig_1303(31) & sig_1303(31) & sig_1303(31) & sig_1303(31) & sig_1303(31) & sig_1303(31) & sig_1303(31) & sig_1303(31) & sig_1303(31) & sig_1303(31) & sig_1303(31) & sig_1303(31) & sig_1303(31) & or_683) or
(repeat(32, sig_1017) and sig_1303(31) & sig_1303(31) & sig_1303(31) & sig_1303(31) & sig_1303(31) & sig_1303(31) & sig_1303(31) & sig_1303(31) & sig_1303(31) & sig_1303(31) & sig_1303(31) & sig_1303(31) & sig_1303(31) & sig_1303(31) & sig_1303(31) & sig_1303(31) & sig_1303(31) & sig_1303(31) & sig_1303(31) & sig_1303(31) & sig_1303(31) & sig_1303(31) & sig_1303(31) & sig_1303(31) & or_692) or
(repeat(32, sig_1000) and sig_1303(31) & sig_1303(31) & sig_1303(31) & sig_1303(31) & sig_1303(31) & sig_1303(31) & sig_1303(31) & sig_1303(31) & sig_1303(31) & sig_1303(31) & sig_1303(31) & sig_1303(31) & sig_1303(31) & sig_1303(31) & sig_1303(31) & sig_1303(31) & sig_1303(31) & sig_1303(31) & sig_1303(31) & sig_1303(31) & sig_1303(31) & sig_1303(31) & sig_1303(31) & sig_1303(31) & or_695) or
(repeat(32, sig_974) and sig_1303(31) & sig_1303(31) & sig_1303(31) & sig_1303(31) & sig_1303(31) & sig_1303(31) & sig_1303(31) & sig_1303(31) & sig_1303(31) & sig_1303(31) & sig_1303(31) & sig_1303(31) & sig_1303(31) & sig_1303(31) & sig_1303(31) & sig_1303(31) & sig_1303(31) & sig_1303(31) & sig_1303(31) & sig_1303(31) & sig_1303(31) & sig_1303(31) & sig_1303(31) & sig_1303(31) & or_708) or
(repeat(32, sig_923) and sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & or_730) or
(repeat(32, sig_922) and sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & or_732) or
(repeat(32, sig_890) and sig_1303(31) & sig_1303(31) & sig_1303(31) & sig_1303(31) & sig_1303(31) & sig_1303(31) & sig_1303(31) & sig_1303(31) & sig_1303(31) & sig_1303(31) & sig_1303(31) & sig_1303(31) & sig_1303(31) & sig_1303(31) & sig_1303(31) & sig_1303(31) & sig_1303(31) & sig_1303(31) & sig_1303(31) & sig_1303(31) & sig_1303(31) & sig_1303(31) & sig_1303(31) & sig_1303(31) & or_745) or
(repeat(32, sig_875) and sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & or_761) or
(repeat(32, sig_872) and sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & or_765) or
(repeat(32, sig_871) and sig_1303(31) & sig_1303(31) & sig_1303(31) & sig_1303(31) & sig_1303(31) & sig_1303(31) & sig_1303(31) & sig_1303(31) & sig_1303(31) & sig_1303(31) & sig_1303(31) & sig_1303(31) & sig_1303(31) & sig_1303(31) & sig_1303(31) & sig_1303(31) & sig_1303(31) & sig_1303(31) & sig_1303(31) & sig_1303(31) & sig_1303(31) & sig_1303(31) & sig_1303(31) & sig_1303(31) & or_767) or
(repeat(32, sig_864) and sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & or_772) or
(repeat(32, sig_863) and sig_1303(31) & sig_1303(31) & sig_1303(31) & sig_1303(31) & sig_1303(31) & sig_1303(31) & sig_1303(31) & sig_1303(31) & sig_1303(31) & sig_1303(31) & sig_1303(31) & sig_1303(31) & sig_1303(31) & sig_1303(31) & sig_1303(31) & sig_1303(31) & sig_1303(31) & sig_1303(31) & sig_1303(31) & sig_1303(31) & sig_1303(31) & sig_1303(31) & sig_1303(31) & sig_1303(31) & or_774) or
(repeat(32, sig_862) and sig_1303(31) & sig_1303(31) & sig_1303(31) & sig_1303(31) & sig_1303(31) & sig_1303(31) & sig_1303(31) & sig_1303(31) & sig_1303(31) & sig_1303(31) & sig_1303(31) & sig_1303(31) & sig_1303(31) & sig_1303(31) & sig_1303(31) & sig_1303(31) & sig_1303(31) & sig_1303(31) & sig_1303(31) & sig_1303(31) & sig_1303(31) & sig_1303(31) & sig_1303(31) & sig_1303(31) & or_776) or
(repeat(32, sig_861) and sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & or_778) or
(repeat(32, sig_1200) and sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & or_780);
-- Behaviour of component 'mux_589' model 'mux'
mux_589 <=
(repeat(32, sig_1269) and sig_1303(31) & sig_1303(31) & sig_1303(31) & sig_1303(31) & sig_1303(31) & sig_1303(31) & sig_1303(31) & sig_1303(31) & sig_1303(31 downto 8)) or
(repeat(32, sig_1276) and sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31 downto 8));
-- Behaviour of component 'mux_591' model 'mux'
mux_591 <=
(repeat(64, sig_1154) and sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31 downto 0)) or
(repeat(64, sig_1169) and sig_1298) or
(repeat(64, sig_1227) and sig_1288) or
(repeat(64, sig_896) and sig_1291(31) & sig_1291(31) & sig_1291(31) & sig_1291(31) & sig_1291(31) & sig_1291(31) & sig_1291(31) & sig_1291(31) & sig_1291(31) & sig_1291(31) & sig_1291(31) & sig_1291(31) & sig_1291(31) & sig_1291(31) & sig_1291(31) & sig_1291(31) & sig_1291(31) & sig_1291(31) & sig_1291(31) & sig_1291(31) & sig_1291(31) & sig_1291(31) & sig_1291(31) & sig_1291(31) & sig_1291(31) & sig_1291(31) & sig_1291(31) & sig_1291(31) & sig_1291(31) & sig_1291(31) & sig_1291(31) & sig_1291(31) & sig_1291(31 downto 0)) or
(repeat(64, sig_1133) and sig_1290);
-- Behaviour of component 'mux_593' model 'mux'
mux_593 <=
(repeat(32, sig_949) and sig_1294) or
(repeat(32, sig_1209) and sig_1293);
-- Behaviour of component 'mux_597' model 'mux'
mux_597 <=
(repeat(32, sig_1175) and tqmf_reg5);
-- Behaviour of component 'mux_599' model 'mux'
mux_599 <=
(repeat(32, sig_1175) and tqmf_reg4);
-- Behaviour of component 'mux_601' model 'mux'
mux_601 <=
(repeat(32, sig_1175) and tqmf_reg3);
-- Behaviour of component 'mux_603' model 'mux'
mux_603 <=
(repeat(32, sig_1175) and tqmf_reg2);
-- Behaviour of component 'mux_605' model 'mux'
mux_605 <=
(repeat(32, sig_1175) and tqmf_reg1);
-- Behaviour of component 'mux_607' model 'mux'
mux_607 <=
(repeat(32, sig_1175) and tqmf_reg0);
-- Behaviour of component 'mux_609' model 'mux'
mux_609 <=
(repeat(32, sig_1175) and encode_xin1_61);
-- Behaviour of component 'mux_611' model 'mux'
mux_611 <=
(repeat(32, sig_1175) and encode_xin2_62);
-- Behaviour of component 'or_701' model 'or'
or_701 <=
and_704 or
and_702;
-- Behaviour of component 'or_708' model 'or'
or_708 <=
sig_1303(31) & "0000000" or
not_709 & "0000000";
-- Behaviour of component 'and_711' model 'and'
and_711 <=
el and
not_712 & not_712 & not_712 & not_712 & not_712 & not_712 & not_712 & not_712 & not_712 & not_712 & not_712 & not_712 & not_712 & not_712 & not_712 & not_712 & not_712 & not_712 & not_712 & not_712 & not_712 & not_712 & not_712 & not_712 & not_712 & not_712 & not_712 & not_712 & not_712 & not_712 & not_712 & not_712;
-- Behaviour of component 'and_729' model 'and'
and_729 <=
sig_1302(31 downto 0) and
sig_1281(31) & sig_1281(31) & sig_1281(31) & sig_1281(31) & sig_1281(31) & sig_1281(31) & sig_1281(31) & sig_1281(31) & sig_1281(31) & sig_1281(31) & sig_1281(31) & sig_1281(31) & sig_1281(31) & sig_1281(31) & sig_1281(31) & sig_1281(31) & sig_1281(31) & sig_1281(31) & sig_1281(31) & sig_1281(31) & sig_1281(31) & sig_1281(31) & sig_1281(31) & sig_1281(31) & sig_1281(31) & sig_1281(31) & sig_1281(31) & sig_1281(31) & sig_1281(31) & sig_1281(31) & sig_1281(31) & sig_1281(31);
-- Behaviour of component 'and_736' model 'and'
and_736 <=
uppol1_apl1_53 and
sig_1306 & sig_1306 & sig_1306 & sig_1306 & sig_1306 & sig_1306 & sig_1306 & sig_1306 & sig_1306 & sig_1306 & sig_1306 & sig_1306 & sig_1306 & sig_1306 & sig_1306 & sig_1306 & sig_1306 & sig_1306 & sig_1306 & sig_1306 & sig_1306 & sig_1306 & sig_1306 & sig_1306 & sig_1306 & sig_1306 & sig_1306 & sig_1306 & sig_1306 & sig_1306 & sig_1306 & sig_1306;
-- Behaviour of component 'or_737' model 'or'
or_737 <=
and_739 or
and_738;
-- Behaviour of component 'and_738' model 'and'
and_738 <=
"11111111111111111101000000000000" and
sig_1301 & sig_1301 & sig_1301 & sig_1301 & sig_1301 & sig_1301 & sig_1301 & sig_1301 & sig_1301 & sig_1301 & sig_1301 & sig_1301 & sig_1301 & sig_1301 & sig_1301 & sig_1301 & sig_1301 & sig_1301 & sig_1301 & sig_1301 & sig_1301 & sig_1301 & sig_1301 & sig_1301 & sig_1301 & sig_1301 & sig_1301 & sig_1301 & sig_1301 & sig_1301 & sig_1301 & sig_1301;
-- Behaviour of component 'and_739' model 'and'
and_739 <=
uppol2_apl2_43 and
sig_1305 & sig_1305 & sig_1305 & sig_1305 & sig_1305 & sig_1305 & sig_1305 & sig_1305 & sig_1305 & sig_1305 & sig_1305 & sig_1305 & sig_1305 & sig_1305 & sig_1305 & sig_1305 & sig_1305 & sig_1305 & sig_1305 & sig_1305 & sig_1305 & sig_1305 & sig_1305 & sig_1305 & sig_1305 & sig_1305 & sig_1305 & sig_1305 & sig_1305 & sig_1305 & sig_1305 & sig_1305;
-- Behaviour of component 'or_745' model 'or'
or_745 <=
sig_1303(31) & "0000000" or
not_746 & "0000000";
-- Behaviour of component 'and_749' model 'and'
and_749 <=
uppol2_apl2_43 and
sig_1306 & sig_1306 & sig_1306 & sig_1306 & sig_1306 & sig_1306 & sig_1306 & sig_1306 & sig_1306 & sig_1306 & sig_1306 & sig_1306 & sig_1306 & sig_1306 & sig_1306 & sig_1306 & sig_1306 & sig_1306 & sig_1306 & sig_1306 & sig_1306 & sig_1306 & sig_1306 & sig_1306 & sig_1306 & sig_1306 & sig_1306 & sig_1306 & sig_1306 & sig_1306 & sig_1306 & sig_1306;
-- Behaviour of component 'and_750' model 'and'
and_750 <=
logsch_nbh_57 and
not_751 & not_751 & not_751 & not_751 & not_751 & not_751 & not_751 & not_751 & not_751 & not_751 & not_751 & not_751 & not_751 & not_751 & not_751 & not_751 & not_751 & not_751 & not_751 & not_751 & not_751 & not_751 & not_751 & not_751 & not_751 & not_751 & not_751 & not_751 & not_751 & not_751 & not_751 & not_751;
-- Behaviour of component 'and_754' model 'and'
and_754 <=
uppol1_apl1_53 and
sig_1282 & sig_1282 & sig_1282 & sig_1282 & sig_1282 & sig_1282 & sig_1282 & sig_1282 & sig_1282 & sig_1282 & sig_1282 & sig_1282 & sig_1282 & sig_1282 & sig_1282 & sig_1282 & sig_1282 & sig_1282 & sig_1282 & sig_1282 & sig_1282 & sig_1282 & sig_1282 & sig_1282 & sig_1282 & sig_1282 & sig_1282 & sig_1282 & sig_1282 & sig_1282 & sig_1282 & sig_1282;
-- Behaviour of component 'and_756' model 'and'
and_756 <=
uppol1_wd3_52 and
sig_1299 & sig_1299 & sig_1299 & sig_1299 & sig_1299 & sig_1299 & sig_1299 & sig_1299 & sig_1299 & sig_1299 & sig_1299 & sig_1299 & sig_1299 & sig_1299 & sig_1299 & sig_1299 & sig_1299 & sig_1299 & sig_1299 & sig_1299 & sig_1299 & sig_1299 & sig_1299 & sig_1299 & sig_1299 & sig_1299 & sig_1299 & sig_1299 & sig_1299 & sig_1299 & sig_1299 & sig_1299;
-- Behaviour of component 'and_759' model 'and'
and_759 <=
"11111111111111111101000000000000" and
sig_1301 & sig_1301 & sig_1301 & sig_1301 & sig_1301 & sig_1301 & sig_1301 & sig_1301 & sig_1301 & sig_1301 & sig_1301 & sig_1301 & sig_1301 & sig_1301 & sig_1301 & sig_1301 & sig_1301 & sig_1301 & sig_1301 & sig_1301 & sig_1301 & sig_1301 & sig_1301 & sig_1301 & sig_1301 & sig_1301 & sig_1301 & sig_1301 & sig_1301 & sig_1301 & sig_1301 & sig_1301;
-- Behaviour of component 'and_763' model 'and'
and_763 <=
logsch_nbh_57 and
not_764 & not_764 & not_764 & not_764 & not_764 & not_764 & not_764 & not_764 & not_764 & not_764 & not_764 & not_764 & not_764 & not_764 & not_764 & not_764 & not_764 & not_764 & not_764 & not_764 & not_764 & not_764 & not_764 & not_764 & not_764 & not_764 & not_764 & not_764 & not_764 & not_764 & not_764 & not_764;
-- Behaviour of component 'or_765' model 'or'
or_765 <=
sig_1304(31) & "0000000" or
not_766 & "0000000";
-- Behaviour of component 'or_772' model 'or'
or_772 <=
sig_1304(31) & "0000000" or
not_773 & "0000000";
-- Behaviour of component 'not_773' model 'not'
not_773 <= not (
sig_1304(31)
);
-- Behaviour of component 'or_774' model 'or'
or_774 <=
sig_1303(31) & "0000000" or
not_775 & "0000000";
-- Behaviour of component 'not_775' model 'not'
not_775 <= not (
sig_1303(31)
);
-- Behaviour of component 'or_776' model 'or'
or_776 <=
sig_1303(31) & "0000000" or
not_777 & "0000000";
-- Behaviour of component 'not_777' model 'not'
not_777 <= not (
sig_1303(31)
);
-- Behaviour of component 'or_778' model 'or'
or_778 <=
sig_1304(31) & "0000000" or
not_779 & "0000000";
-- Behaviour of component 'not_779' model 'not'
not_779 <= not (
sig_1304(31)
);
-- Behaviour of component 'or_780' model 'or'
or_780 <=
sig_1304(31) & "0000000" or
not_781 & "0000000";
-- Behaviour of component 'not_781' model 'not'
not_781 <= not (
sig_1304(31)
);
-- Behaviour of all components of model 'reg'
-- Registers with clock = sig_clock and no reset
process(sig_clock)
begin
if rising_edge(sig_clock) then
if sig_1176 = '1' then
tqmf_reg0 <= mux_611;
end if;
if sig_1176 = '1' then
tqmf_reg1 <= mux_609;
end if;
if sig_1176 = '1' then
tqmf_reg2 <= mux_607;
end if;
if sig_1176 = '1' then
tqmf_reg3 <= mux_605;
end if;
if sig_1176 = '1' then
tqmf_reg4 <= mux_603;
end if;
if sig_1176 = '1' then
tqmf_reg5 <= mux_601;
end if;
if sig_1176 = '1' then
tqmf_reg6 <= mux_599;
end if;
if sig_1176 = '1' then
tqmf_reg7 <= mux_597;
end if;
if sig_1221 = '1' then
read32_buf_0 <= stdin_data;
end if;
if sig_1215 = '1' then
write32_val_1 <= mux_593;
end if;
if sig_1226 = '1' then
filtez_zl <= mux_591;
end if;
if sig_1274 = '1' then
upzero_wd3 <= mux_589;
end if;
if sig_1274 = '1' then
upzero_wd2 <= mux_587;
end if;
if sig_956 = '1' then
xh <= sig_1302(46 downto 15);
end if;
if sig_956 = '1' then
xl <= sig_1298(46 downto 15);
end if;
if sig_953 = '1' then
xd <= sig_1307(31 downto 0);
end if;
if sig_953 = '1' then
xs <= sig_1288(31 downto 0);
end if;
if sig_958 = '1' then
el <= sig_1302(31 downto 0);
end if;
if sig_920 = '1' then
sl <= sig_1288(31 downto 0);
end if;
if sig_920 = '1' then
szl <= filtez_zl(45 downto 14);
end if;
if sig_1098 = '1' then
il <= quantl_ril_18(5 downto 0);
end if;
if sig_983 = '1' then
nbl <= mux_565;
end if;
if sig_1001 = '1' then
al2 <= mux_563;
end if;
if sig_984 = '1' then
al1 <= mux_561;
end if;
if sig_1151 = '1' then
plt2 <= mux_559;
end if;
if sig_989 = '1' then
plt1 <= mux_557;
end if;
if sig_934 = '1' then
plt <= sig_1298(31 downto 0);
end if;
if sig_1098 = '1' then
dlt <= sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31 downto 15);
end if;
if sig_1151 = '1' then
rlt2 <= mux_551;
end if;
if sig_989 = '1' then
rlt1 <= mux_549;
end if;
if sig_1152 = '1' then
rlt <= sig_1298(30 downto 0);
end if;
if sig_1010 = '1' then
detl <= mux_544;
end if;
if sig_1056 = '1' then
deth <= mux_540;
end if;
if sig_1095 = '1' then
sh <= sig_1298(31 downto 0);
end if;
if sig_963 = '1' then
eh <= sig_1302(31 downto 0);
end if;
if sig_1043 = '1' then
ih <= mux_532;
end if;
if sig_870 = '1' then
dh <= sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31 downto 15);
end if;
if sig_1071 = '1' then
nbh <= mux_528;
end if;
if sig_1255 = '1' then
rh <= sig_1298(31 downto 0);
end if;
if sig_996 = '1' then
yh <= sig_1298(30 downto 0);
end if;
if sig_873 = '1' then
ph <= sig_1298(31 downto 0);
end if;
if sig_1004 = '1' then
ah2 <= mux_520;
end if;
if sig_994 = '1' then
ah1 <= mux_518;
end if;
if sig_998 = '1' then
ph2 <= mux_516;
end if;
if sig_1021 = '1' then
ph1 <= mux_514;
end if;
if sig_998 = '1' then
rh2 <= mux_512;
end if;
if sig_1021 = '1' then
rh1 <= mux_510;
end if;
if sig_1083 = '1' then
rl <= sig_1298(31 downto 0);
end if;
if sig_915 = '1' then
dec_dlt <= sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31 downto 15);
end if;
if sig_1121 = '1' then
dec_detl <= mux_504;
end if;
if sig_1105 = '1' then
dec_deth <= mux_502;
end if;
if sig_982 = '1' then
dec_plt2 <= mux_500;
end if;
if sig_1132 = '1' then
dec_plt1 <= mux_498;
end if;
if sig_906 = '1' then
dec_plt <= sig_1289(31 downto 0);
end if;
if sig_906 = '1' then
dec_sl <= sig_1298(31 downto 0);
end if;
if sig_897 = '1' then
dec_rlt <= sig_1298(30 downto 0);
end if;
if sig_982 = '1' then
dec_rlt2 <= mux_490;
end if;
if sig_1132 = '1' then
dec_rlt1 <= mux_488;
end if;
if sig_1014 = '1' then
dec_al2 <= mux_486;
end if;
if sig_992 = '1' then
dec_al1 <= mux_484;
end if;
if sig_913 = '1' then
dl <= sig_1281(31) & sig_1281(31) & sig_1281(31) & sig_1281(31) & sig_1281(31) & sig_1281(31) & sig_1281(31) & sig_1281(31) & sig_1281(31) & sig_1281(31) & sig_1281(31) & sig_1281(31) & sig_1281(31) & sig_1281(31) & sig_1281(31) & sig_1281(31 downto 15);
end if;
if sig_1014 = '1' then
dec_nbh <= mux_480;
end if;
if sig_897 = '1' then
dec_dh <= sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31 downto 15);
end if;
if sig_1030 = '1' then
dec_nbl <= mux_476;
end if;
if sig_1258 = '1' then
dec_rh2 <= mux_474;
end if;
if sig_981 = '1' then
dec_rh1 <= mux_472;
end if;
if sig_1026 = '1' then
dec_ah2 <= mux_470;
end if;
if sig_1058 = '1' then
dec_ah1 <= mux_468;
end if;
if sig_894 = '1' then
dec_ph <= sig_1298(31 downto 0);
end if;
if sig_894 = '1' then
dec_sh <= sig_1289(31 downto 0);
end if;
if sig_1258 = '1' then
dec_ph2 <= mux_462;
end if;
if sig_981 = '1' then
dec_ph1 <= mux_460;
end if;
if sig_975 = '1' then
abs_m_3 <= mux_458;
end if;
if sig_1232 = '1' then
filtep_pl_14 <= mux_456;
end if;
if sig_965 = '1' then
quantl_el_16 <= el(31);
end if;
if sig_867 = '1' then
quantl_detl_17 <= detl;
end if;
if sig_1063 = '1' then
quantl_ril_18 <= or_669;
end if;
if sig_900 = '1' then
quantl_mil_19 <= mux_448;
end if;
if sig_1024 = '1' then
quantl_wd_20 <= abs_m_3(31) & abs_m_3(31) & abs_m_3(31) & abs_m_3(31) & abs_m_3(31) & abs_m_3(31) & abs_m_3(31) & abs_m_3(31) & abs_m_3(31) & abs_m_3(31) & abs_m_3(31) & abs_m_3(31) & abs_m_3(31) & abs_m_3(31) & abs_m_3(31) & abs_m_3(31) & abs_m_3(31) & abs_m_3(31) & abs_m_3(31) & abs_m_3(31) & abs_m_3(31) & abs_m_3(31) & abs_m_3(31) & abs_m_3(31) & abs_m_3(31) & abs_m_3(31) & abs_m_3(31) & abs_m_3(31) & abs_m_3(31) & abs_m_3(31) & abs_m_3(31) & abs_m_3(31) & abs_m_3;
end if;
if sig_1158 = '1' then
quantl_decis_21 <= sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31) & sig_1304(31 downto 15);
end if;
if sig_1106 = '1' then
logscl_nbl_27 <= mux_440;
end if;
if sig_1060 = '1' then
logscl_wd_28 <= mux_438;
end if;
if sig_1067 = '1' then
scalel_wd3_35 <= sig_1295(28 downto 0);
end if;
if sig_1259 = '1' then
uppol2_wd4_42 <= mux_434;
end if;
if sig_1165 = '1' then
uppol2_apl2_43 <= mux_432;
end if;
if sig_1259 = '1' then
uppol1_wd2_51 <= mux_430;
end if;
if sig_1028 = '1' then
uppol1_wd3_52 <= sig_1302(31 downto 0);
end if;
if sig_1134 = '1' then
uppol1_apl1_53 <= mux_426;
end if;
if sig_1141 = '1' then
logsch_nbh_57 <= mux_424;
end if;
if sig_1148 = '1' then
logsch_wd_58 <= mux_422;
end if;
if sig_867 = '1' then
encode_xin1_61 <= sig_1296;
end if;
if sig_867 = '1' then
encode_xin2_62 <= sig_1297;
end if;
if sig_1225 = '1' then
encode_xa_67 <= mux_416;
end if;
if sig_1225 = '1' then
encode_xb_68 <= mux_414;
end if;
if sig_1152 = '1' then
encode_decis_69 <= sig_1291(31) & sig_1291(31) & sig_1291(31) & sig_1291(31) & sig_1291(31) & sig_1291(31) & sig_1291(31) & sig_1291(31) & sig_1291(31) & sig_1291(31) & sig_1291(31) & sig_1291(31) & sig_1291(31 downto 12);
end if;
if sig_913 = '1' then
decode_input_98 <= sig_1294(31 downto 2);
end if;
if sig_1144 = '1' then
decode_xa1_100 <= mux_406;
end if;
if sig_1144 = '1' then
decode_xa2_101 <= mux_404;
end if;
if sig_1138 = '1' then
augh_main_i_132 <= mux_372;
end if;
if sig_996 = '1' then
encode_ret0_136 <= or_699 & quantl_ril_18(5 downto 0);
end if;
if sig_1258 = '1' then
dec_del_dhx_reg0 <= mux_338;
end if;
if sig_1258 = '1' then
dec_del_dhx_reg1 <= mux_336;
end if;
if sig_980 = '1' then
dec_del_bph_reg0 <= mux_326;
end if;
if sig_979 = '1' then
dec_del_bph_reg1 <= mux_324;
end if;
if sig_977 = '1' then
dec_del_bph_reg2 <= mux_322;
end if;
if sig_1164 = '1' then
dec_del_bph_reg3 <= mux_320;
end if;
if sig_978 = '1' then
dec_del_bph_reg4 <= mux_318;
end if;
if sig_1170 = '1' then
dec_del_bph_reg5 <= mux_316;
end if;
if sig_982 = '1' then
dec_del_dltx_reg0 <= mux_310;
end if;
if sig_982 = '1' then
dec_del_dltx_reg1 <= mux_308;
end if;
if sig_1264 = '1' then
dec_del_bpl_reg0 <= mux_298;
end if;
if sig_1051 = '1' then
dec_del_bpl_reg1 <= mux_296;
end if;
if sig_1267 = '1' then
dec_del_bpl_reg2 <= mux_294;
end if;
if sig_1052 = '1' then
dec_del_bpl_reg3 <= mux_292;
end if;
if sig_1173 = '1' then
dec_del_bpl_reg4 <= mux_290;
end if;
if sig_1050 = '1' then
dec_del_bpl_reg5 <= mux_288;
end if;
if sig_1116 = '1' then
delay_bph_reg0 <= mux_286;
end if;
if sig_1279 = '1' then
delay_bph_reg1 <= mux_284;
end if;
if sig_1111 = '1' then
delay_bph_reg2 <= mux_282;
end if;
if sig_1110 = '1' then
delay_bph_reg3 <= mux_280;
end if;
if sig_1113 = '1' then
delay_bph_reg4 <= mux_278;
end if;
if sig_1114 = '1' then
delay_bph_reg5 <= mux_276;
end if;
if sig_998 = '1' then
delay_dhx_reg0 <= mux_274;
end if;
if sig_998 = '1' then
delay_dhx_reg1 <= mux_272;
end if;
if sig_1151 = '1' then
delay_dltx_reg0 <= mux_262;
end if;
if sig_1151 = '1' then
delay_dltx_reg1 <= mux_260;
end if;
if sig_1131 = '1' then
delay_bpl_reg0 <= mux_250;
end if;
if sig_1128 = '1' then
delay_bpl_reg1 <= mux_248;
end if;
if sig_1126 = '1' then
delay_bpl_reg2 <= mux_246;
end if;
if sig_1124 = '1' then
delay_bpl_reg3 <= mux_244;
end if;
if sig_1127 = '1' then
delay_bpl_reg4 <= mux_242;
end if;
if sig_1130 = '1' then
delay_bpl_reg5 <= mux_240;
end if;
if sig_1006 = '1' then
accumc_reg0 <= mux_238;
end if;
if sig_1006 = '1' then
accumc_reg1 <= mux_236;
end if;
if sig_1006 = '1' then
accumc_reg2 <= mux_234;
end if;
if sig_1006 = '1' then
accumc_reg3 <= mux_232;
end if;
if sig_1006 = '1' then
accumc_reg4 <= mux_230;
end if;
if sig_1006 = '1' then
accumc_reg5 <= mux_228;
end if;
if sig_1006 = '1' then
accumc_reg6 <= mux_226;
end if;
if sig_1006 = '1' then
accumc_reg7 <= mux_224;
end if;
if sig_1006 = '1' then
accumc_reg8 <= mux_222;
end if;
if sig_1006 = '1' then
accumc_reg9 <= mux_220;
end if;
if sig_1006 = '1' then
accumc_reg10 <= mux_218;
end if;
if sig_1006 = '1' then
accumd_reg0 <= mux_216;
end if;
if sig_1006 = '1' then
accumd_reg1 <= mux_214;
end if;
if sig_1006 = '1' then
accumd_reg2 <= mux_212;
end if;
if sig_1006 = '1' then
accumd_reg3 <= mux_210;
end if;
if sig_1006 = '1' then
accumd_reg4 <= mux_208;
end if;
if sig_1006 = '1' then
accumd_reg5 <= mux_206;
end if;
if sig_1006 = '1' then
accumd_reg6 <= mux_204;
end if;
if sig_1006 = '1' then
accumd_reg7 <= mux_202;
end if;
if sig_1006 = '1' then
accumd_reg8 <= mux_200;
end if;
if sig_1006 = '1' then
accumd_reg9 <= mux_198;
end if;
if sig_1006 = '1' then
accumd_reg10 <= mux_196;
end if;
if sig_1176 = '1' then
tqmf_reg8 <= mux_194;
end if;
if sig_1176 = '1' then
tqmf_reg9 <= mux_192;
end if;
if sig_1176 = '1' then
tqmf_reg10 <= mux_190;
end if;
if sig_1176 = '1' then
tqmf_reg11 <= mux_188;
end if;
if sig_1176 = '1' then
tqmf_reg12 <= mux_186;
end if;
if sig_1176 = '1' then
tqmf_reg13 <= mux_184;
end if;
if sig_1176 = '1' then
tqmf_reg14 <= mux_182;
end if;
if sig_1176 = '1' then
tqmf_reg15 <= mux_180;
end if;
if sig_1176 = '1' then
tqmf_reg16 <= mux_178;
end if;
if sig_1176 = '1' then
tqmf_reg17 <= mux_176;
end if;
if sig_1176 = '1' then
tqmf_reg18 <= mux_174;
end if;
if sig_1176 = '1' then
tqmf_reg19 <= mux_172;
end if;
if sig_1176 = '1' then
tqmf_reg20 <= mux_170;
end if;
if sig_1176 = '1' then
tqmf_reg21 <= mux_168;
end if;
if sig_1176 = '1' then
tqmf_reg22 <= mux_166;
end if;
if sig_1176 = '1' then
tqmf_reg23 <= mux_164;
end if;
end if;
end process;
-- Remaining signal assignments
-- Those who are not assigned by component instantiation
sig_clock <= clock;
sig_reset <= reset;
augh_test_23 <= sig_1300;
augh_test_24 <= sig_1300;
sig_start <= start;
augh_test_135 <= sig_1300;
augh_test_137 <= sig_1300;
augh_test_138 <= sig_1300;
sig_1319 <= uppol2_apl2_43(31) & uppol2_apl2_43(31) & uppol2_apl2_43(31) & uppol2_apl2_43(31) & uppol2_apl2_43(31) & uppol2_apl2_43(31) & uppol2_apl2_43(31) & uppol2_apl2_43(31) & uppol2_apl2_43(31) & uppol2_apl2_43(31) & uppol2_apl2_43(31) & uppol2_apl2_43(31) & uppol2_apl2_43(31) & uppol2_apl2_43(31) & uppol2_apl2_43(31) & uppol2_apl2_43(31) & uppol2_apl2_43(31) & uppol2_apl2_43(31) & uppol2_apl2_43(31) & uppol2_apl2_43(31) & uppol2_apl2_43(31) & uppol2_apl2_43(31) & uppol2_apl2_43(31) & uppol2_apl2_43(31) & uppol2_apl2_43(31) & uppol2_apl2_43(31) & uppol2_apl2_43(31) & uppol2_apl2_43(31) & uppol2_apl2_43(31) & uppol2_apl2_43(31) & uppol2_apl2_43(31) & uppol2_apl2_43(31) & uppol2_apl2_43;
-- Remaining top-level ports assignments
-- Those who are not assigned by component instantiation
stdin_rdy <= sig_1221;
stdout_data <= write32_val_1;
end architecture;
| gpl-2.0 | 353a752f4dcc412ecd3f619f3b15a281 | 0.63308 | 2.269864 | false | false | false | false |
ambrosef/HLx_Examples | Acceleration/memcached/regressionSims/sources/kvs_tbStatsMonitorHDLNode.vhdl | 1 | 4,021 | -------------------------------------------------------------------------------
--
-- Title : local_link_sink.vhd - part of the Groucher simulation environment
--
-- Description : This code models the behavior of a local link sink device
--
-- Files: writes the received data and control into a data file
-- every clock cycle
-- The characters in the text file are interpreted as hex
-- Organization is MSB to LSB
-- padded with 0s on the MSBs to multiples of 4
-- data bus ' ' ctl signals(valid, done)
-- takes the flow ctl signal either through the parameters
-- or from a file. this is determined through the
-- generic BPR_PARA
-- Interface: the processing starts after rst de-asserts
-- the data and control signals are plainly recorded
-- the backpressure is driven either from file input
-- or throught the parameters
-- Parameters: data width
-- length width
-- rem width
-- l_present: indicates whether the length inetrface exists or not
-- bpr_para: when true then DST_RDY_N is driven through
-- the following paramters:
-- bpr_delay: waits for bpr_Delay*clock ticks before
-- commencing assertion
-- bpr_period: indicates how often backpressure is asserted
-- in clock ticks
-- bpr_duration: inidcates for how long backpressure is
-- asserted within one period.
-- DURATION < PERIOD!
-- BPR_FILENAME : file name of input backpressure file
-- PKT_FILENAME : filename of output data file
--
--
-- ----------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_TEXTIO.all;
LIBRARY STD;
USE STD.TEXTIO.ALL;
entity kvs_tbStatsMonitorHDLNode is
generic (
D_WIDTH : integer := 64;
PKT_FILENAME : string := "pkt.out.txt"
);
port (
clk : in std_logic;
rst : in std_logic;
udp_in_ready : out std_logic;
udp_in_valid : in std_logic;
udp_in_data : in std_logic_vector (D_WIDTH-1 downto 0)
);
end kvs_tbStatsMonitorHDLNode;
architecture structural of kvs_tbStatsMonitorHDLNode is
constant FD_WIDTH : integer := ((D_WIDTH-1) / 4)*4 + 4;
begin
udp_in_ready <= '1';
-- write process for the received packet
write_pktfile_p : process
FILE pkt_file : TEXT OPEN WRITE_MODE IS PKT_FILENAME;
variable l : line;
variable d : character := 'D';
variable blank : character := ' ';
variable dat_vector : std_logic_vector(FD_WIDTH-1 downto 0);
variable ctl_vector : std_logic_vector(3 downto 0);
variable eop : std_logic;
variable modulus : std_logic_vector(2 downto 0);
begin
if (D_WIDTH=0) then
assert false report "D_WIDTH and R_WIDTH must be greater than 0" severity failure;
end if;
wait until rst='0';
while TRUE loop
-- write each cycle
wait until CLK'event and CLK='1';
-- padding
dat_vector(D_WIDTH-1 downto 0) := udp_in_data(D_WIDTH-1 downto 0);
dat_vector(FD_WIDTH-1 downto D_WIDTH) := (others => '0');
ctl_vector(3 downto 0) := '0' & '0' & udp_in_valid & '0'; -- udp_in_done is deprecated
-- compose output line and mas modulus.
write(l,d);
hwrite(l, dat_vector(FD_WIDTH-1 downto 64));
hwrite(l, dat_vector(63 downto 0));
write(l,blank);
hwrite(l, ctl_vector);
-- writing
writeline(pkt_file, l);
end loop;
end process;
end structural;
| bsd-3-clause | ba569973b920ffa33b17a30d941f2337 | 0.544641 | 4.008973 | false | false | false | false |
emogenet/ghdl | testsuite/vests/vhdl-93/ashenden/compliant/ch_07_fg_07_06.vhd | 4 | 2,197 |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_07_fg_07_06.vhd,v 1.2 2001-10-26 16:29:34 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
entity fg_07_06 is
end entity fg_07_06;
architecture test of fg_07_06 is
type func_code is (add, subtract);
signal op1 : integer := 10;
signal op2 : integer := 3;
signal dest : integer := 0;
signal func : func_code := add;
signal Z_flag : boolean := false;
constant Tpd : delay_length := 3 ns;
begin
stimulus : process is
-- code from book
procedure do_arith_op ( op : in func_code ) is
variable result : integer;
begin
case op is
when add =>
result := op1 + op2;
when subtract =>
result := op1 - op2;
end case;
dest <= result after Tpd;
Z_flag <= result = 0 after Tpd;
end procedure do_arith_op;
-- end code from book
begin
wait for 10 ns;
-- code from book (in text)
do_arith_op ( add );
-- end code from book
wait for 10 ns;
-- code from book (in text)
do_arith_op ( func );
-- end code from book
wait for 10 ns;
do_arith_op ( subtract );
wait for 10 ns;
op2 <= 10;
wait for 10 ns;
do_arith_op ( subtract );
wait;
end process stimulus;
end architecture test;
| gpl-2.0 | 705b99bf02770bb4aaf28e933676552c | 0.589895 | 3.909253 | false | false | false | false |
pmh92/Proyecto-OFDM | test/image_pkg.vhd | 1 | 9,647 | -----------------------------------------------------------------
--! @file
--! @author Ben Cohen
--! @brief Conversions from different datatypes to string, by Ben Cohen
--
-- Copyright (c) 1997 Ben Cohen. All rights reserved.
-- This model can be used in conjunction with the Kluwer Academic books
-- "VHDL Coding Styles and Methodologies", ISBN: 0-7923-9598-0
-- "VHDL Answers to Frequently Asked Questions", Kluwer Academic
-- by Ben Cohen. email: [email protected]
--
-- This source file for the Image Package
-- may be used and distributed without restriction provided
-- that this copyright statement is not removed from the file
-- and that any derivative work contains this copyright notice.
---------------------------------------------------------------
library IEEE;
use IEEE.Std_Logic_1164.all;
use IEEE.Std_Logic_TextIO.all;
use IEEE.Std_Logic_Arith.all;
library Std;
use STD.TextIO.all;
--! @brief Allows conversion from different datatypes to string
package image_pkg is
function Image(In_Image : Time) return String;
function Image(In_Image : Bit) return String;
function Image(In_Image : Bit_Vector) return String;
function Image(In_Image : Integer) return String;
function Image(In_Image : Real) return String;
function Image(In_Image : Std_uLogic) return String;
function Image(In_Image : Std_uLogic_Vector) return String;
function Image(In_Image : Std_Logic_Vector) return String;
function Image(In_Image : Signed) return String;
function Image(In_Image : UnSigned) return String;
function HexImage(InStrg : String) return String;
function HexImage(In_Image : Bit_Vector) return String;
function HexImage(In_Image : Std_uLogic_Vector) return String;
function HexImage(In_Image : Std_Logic_Vector) return String;
function HexImage(In_Image : Signed) return String;
function HexImage(In_Image : UnSigned) return String;
function DecImage(In_Image : Bit_Vector) return String;
function DecImage(In_Image : Std_uLogic_Vector) return String;
function DecImage(In_Image : Std_Logic_Vector) return String;
function DecImage(In_Image : Signed) return String;
function DecImage(In_Image : UnSigned) return String;
end image_pkg;
package body image_pkg is
function Image(In_Image : Time) return String is
variable L : Line; -- access type
variable W : String(1 to 25) := (others => ' ');
-- Long enough to hold a time string
begin
-- the WRITE procedure creates an object with "NEW".
-- L is passed as an output of the procedure.
Std.TextIO.WRITE(L, in_image);
-- Copy L.all onto W
W(L.all'range) := L.all;
Deallocate(L);
return W;
end Image;
function Image(In_Image : Bit) return String is
variable L : Line; -- access type
variable W : String(1 to 3) := (others => ' ');
begin
Std.TextIO.WRITE(L, in_image);
W(L.all'range) := L.all;
Deallocate(L);
return W;
end Image;
function Image(In_Image : Bit_Vector) return String is
variable L : Line; -- access type
variable W : String(1 to In_Image'length) := (others => ' ');
begin
Std.TextIO.WRITE(L, in_image);
W(L.all'range) := L.all;
Deallocate(L);
return W;
end Image;
function Image(In_Image : Integer) return String is
variable L : Line; -- access type
variable W : String(1 to 32) := (others => ' ');
-- Long enough to hold a time string
begin
Std.TextIO.WRITE(L, in_image);
W(L.all'range) := L.all;
Deallocate(L);
return W;
end Image;
function Image(In_Image : Real) return String is
variable L : Line; -- access type
variable W : String(1 to 32) := (others => ' ');
-- Long enough to hold a time string
begin
Std.TextIO.WRITE(L, in_image);
W(L.all'range) := L.all;
Deallocate(L);
return W;
end Image;
function Image(In_Image : Std_uLogic) return String is
variable L : Line; -- access type
variable W : String(1 to 3) := (others => ' ');
begin
IEEE.Std_Logic_Textio.WRITE(L, in_image);
W(L.all'range) := L.all;
Deallocate(L);
return W;
end Image;
function Image(In_Image : Std_uLogic_Vector) return String is
variable L : Line; -- access type
variable W : String(1 to In_Image'length) := (others => ' ');
begin
IEEE.Std_Logic_Textio.WRITE(L, in_image);
W(L.all'range) := L.all;
Deallocate(L);
return W;
end Image;
function Image(In_Image : Std_Logic_Vector) return String is
variable L : Line; -- access type
variable W : String(1 to In_Image'length) := (others => ' ');
begin
IEEE.Std_Logic_TextIO.WRITE(L, In_Image);
W(L.all'range) := L.all;
Deallocate(L);
return W;
end Image;
function Image(In_Image : Signed) return String is
begin
return Image(Std_Logic_Vector(In_Image));
end Image;
function Image(In_Image : UnSigned) return String is
begin
return Image(Std_Logic_Vector(In_Image));
end Image;
function HexImage(InStrg : String) return String is
subtype Int03_Typ is Integer range 0 to 3;
variable Result : string(1 to ((InStrg'length - 1)/4)+1) :=
(others => '0');
variable StrTo4 : string(1 to Result'length * 4) :=
(others => '0');
variable MTspace : Int03_Typ; -- Empty space to fill in
variable Str4 : String(1 to 4);
variable Group_v : Natural := 0;
begin
MTspace := Result'length * 4 - InStrg'length;
StrTo4(MTspace + 1 to StrTo4'length) := InStrg; -- padded with '0'
Cnvrt_Lbl : for I in Result'range loop
Group_v := Group_v + 4; -- identifies end of bit # in a group of 4
Str4 := StrTo4(Group_v - 3 to Group_v); -- get next 4 characters
case Str4 is
when "0000" => Result(I) := '0';
when "0001" => Result(I) := '1';
when "0010" => Result(I) := '2';
when "0011" => Result(I) := '3';
when "0100" => Result(I) := '4';
when "0101" => Result(I) := '5';
when "0110" => Result(I) := '6';
when "0111" => Result(I) := '7';
when "1000" => Result(I) := '8';
when "1001" => Result(I) := '9';
when "1010" => Result(I) := 'A';
when "1011" => Result(I) := 'B';
when "1100" => Result(I) := 'C';
when "1101" => Result(I) := 'D';
when "1110" => Result(I) := 'E';
when "1111" => Result(I) := 'F';
when others => Result(I) := 'X';
end case; -- Str4
end loop Cnvrt_Lbl;
return Result;
end HexImage;
function HexImage(In_Image : Bit_Vector) return String is
begin
return HexImage(Image(In_Image));
end HexImage;
function HexImage(In_Image : Std_uLogic_Vector) return String is
begin
return HexImage(Image(In_Image));
end HexImage;
function HexImage(In_Image : Std_Logic_Vector) return String is
begin
return HexImage(Image(In_Image));
end HexImage;
function HexImage(In_Image : Signed) return String is
begin
return HexImage(Image(In_Image));
end HexImage;
function HexImage(In_Image : UnSigned) return String is
begin
return HexImage(Image(In_Image));
end HexImage;
function DecImage(In_Image : Bit_Vector) return String is
variable In_Image_v : Bit_Vector(In_Image'length downto 1) := In_Image;
begin
if In_Image'length > 31 then
assert False
report "Number too large for Integer, clipping to 31 bits"
severity Warning;
return Image(Conv_Integer
(Unsigned(To_StdLogicVector
(In_Image_v(31 downto 1)))));
else
return Image(Conv_Integer(Unsigned(To_StdLogicVector(In_Image))));
end if;
end DecImage;
function DecImage(In_Image : Std_uLogic_Vector) return String is
variable In_Image_v : Std_uLogic_Vector(In_Image'length downto 1)
:= In_Image;
begin
if In_Image'length > 31 then
assert False
report "Number too large for Integer, clipping to 31 bits"
severity Warning;
return Image(Conv_Integer(Unsigned(In_Image_v(31 downto 1))));
else
return Image(Conv_Integer(Unsigned(In_Image)));
end if;
end DecImage;
function DecImage(In_Image : Std_Logic_Vector) return String is
variable In_Image_v : Std_Logic_Vector(In_Image'length downto 1)
:= In_Image;
begin
if In_Image'length > 31 then
assert False
report "Number too large for Integer, clipping to 31 bits"
severity Warning;
return Image(Conv_Integer(Unsigned(In_Image_v(31 downto 1))));
else
return Image(Conv_Integer(Unsigned(In_Image)));
end if;
end DecImage;
function DecImage(In_Image : Signed) return String is
variable In_Image_v : Signed(In_Image'length downto 1) := In_Image;
begin
if In_Image'length > 31 then
assert False
report "Number too large for Integer, clipping to 31 bits"
severity Warning;
return Image(Conv_Integer(In_Image_v(31 downto 1)));
else
return Image(Conv_Integer(In_Image));
end if;
end DecImage;
function DecImage(In_Image : UnSigned) return String is
variable In_Image_v : UnSigned(In_Image'length downto 1) := In_Image;
begin
if In_Image'length > 31 then
assert False
report "Number too large for Integer, clipping to 31 bits"
severity Warning;
return Image(Conv_Integer(In_Image_v(31 downto 1)));
else
return Image(Conv_Integer(In_Image));
end if;
end DecImage;
end image_pkg;
| gpl-2.0 | 28f00df93b64857fe5e9835487f60827 | 0.620504 | 3.570318 | false | false | false | false |
rafa-jfet/OFM | ARCHIVOS VHDL/div_frec.vhd | 1 | 2,330 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 18:34:40 03/09/2015
-- Design Name:
-- Module Name: DIV_FREC - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_logic_arith.ALL;
use IEEE.std_logic_unsigned.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity div_frec is
Generic ( SAT_BPSK : integer := 650;
SAT_QPSK : integer := 650;
SAT_8PSK : integer := 650 );
Port ( clk : in STD_LOGIC;
reset : in STD_LOGIC;
button : in STD_LOGIC;
modulation : in STD_LOGIC_VECTOR (2 downto 0);
sat : out STD_LOGIC);
end div_frec;
architecture Behavioral of div_frec is
type estado is ( reposo,
inicio,
activo );
signal estado_actual : estado;
signal estado_nuevo : estado;
signal cuenta, p_cuenta : integer ;--range 0 to SAT_BPSK;
begin
comb : process ( cuenta, estado_actual, button, modulation )
begin
sat <= '0';
p_cuenta <= cuenta;
estado_nuevo <= estado_actual;
case estado_actual is
when reposo =>
if ( button = '1' ) then
estado_nuevo <= inicio;
end if;
when inicio =>
case modulation is
when "100" =>
p_cuenta <= SAT_BPSK;
when "010" =>
p_cuenta <= SAT_QPSK;
when OTHERS =>
p_cuenta <= SAT_8PSK;
end case;
estado_nuevo <= activo;
when activo =>
if ( cuenta = 0 ) then
estado_nuevo <= inicio;
sat <= '1';
else
p_cuenta <= cuenta -1;
end if;
end case;
end process;
sinc : process(clk, reset)
begin
if ( reset = '1' ) then
cuenta <= 0;
estado_actual <= reposo;
elsif ( rising_edge(clk) ) then
cuenta <= p_cuenta;
estado_actual <= estado_nuevo;
end if;
end process;
end Behavioral; | gpl-3.0 | df9cd81d918b04e0daca062d2821cdf8 | 0.570815 | 3.426471 | false | false | false | false |
emogenet/ghdl | libraries/ieee2008/float_generic_pkg.vhdl | 4 | 51,341 | -- --------------------------------------------------------------------
--
-- Copyright © 2008 by IEEE. All rights reserved.
--
-- This source file is an essential part of IEEE Std 1076-2008,
-- IEEE Standard VHDL Language Reference Manual. This source file may not be
-- copied, sold, or included with software that is sold without written
-- permission from the IEEE Standards Department. This source file may be
-- copied for individual use between licensed users. This source file is
-- provided on an AS IS basis. The IEEE disclaims ANY WARRANTY EXPRESS OR
-- IMPLIED INCLUDING ANY WARRANTY OF MERCHANTABILITY AND FITNESS FOR USE
-- FOR A PARTICULAR PURPOSE. The user of the source file shall indemnify
-- and hold IEEE harmless from any damages or liability arising out of the
-- use thereof.
--
-- Title : Floating-point package (Generic package declaration)
-- :
-- Library : This package shall be compiled into a library
-- : symbolically named IEEE.
-- :
-- Developers: Accellera VHDL-TC and IEEE P1076 Working Group
-- :
-- Purpose : This packages defines basic binary floating point
-- : arithmetic functions
-- :
-- Note : This package may be modified to include additional data
-- : required by tools, but it must in no way change the
-- : external interfaces or simulation behavior of the
-- : description. It is permissible to add comments and/or
-- : attributes to the package declarations, but not to change
-- : or delete any original lines of the package declaration.
-- : The package body may be changed only in accordance with
-- : the terms of Clause 16 of this standard.
-- :
-- --------------------------------------------------------------------
-- $Revision: 1220 $
-- $Date: 2008-04-10 17:16:09 +0930 (Thu, 10 Apr 2008) $
-- --------------------------------------------------------------------
use STD.TEXTIO.all;
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
use IEEE.fixed_float_types.all;
package float_generic_pkg is
generic (
-- Defaults for sizing routines, when you do a "to_float" this will be
-- the default size. Example float32 would be 8 and 23 (8 downto -23)
float_exponent_width : NATURAL := 8;
float_fraction_width : NATURAL := 23;
-- Rounding algorithm, "round_nearest" is default, other valid values
-- are "round_zero" (truncation), "round_inf" (round up), and
-- "round_neginf" (round down)
float_round_style : round_type := round_nearest;
-- Denormal numbers (very small numbers near zero) true or false
float_denormalize : BOOLEAN := true;
-- Turns on NAN processing (invalid numbers and overflow) true of false
float_check_error : BOOLEAN := true;
-- Guard bits are added to the bottom of every operation for rounding.
-- any natural number (including 0) are valid.
float_guard_bits : NATURAL := 3;
-- If TRUE, then turn off warnings on "X" propagation
no_warning : BOOLEAN := false;
package fixed_pkg is new IEEE.fixed_generic_pkg
generic map (<>) );
-- Author David Bishop ([email protected])
constant CopyRightNotice : STRING :=
"Copyright 2008 by IEEE. All rights reserved.";
use fixed_pkg.all;
-- Note that this is "INTEGER range <>", thus if you use a literal, then the
-- default range will be (INTEGER'low to INTEGER'low + X)
type UNRESOLVED_float is array (INTEGER range <>) of STD_ULOGIC; -- main type
alias U_float is UNRESOLVED_float;
subtype float is (resolved) UNRESOLVED_float;
-----------------------------------------------------------------------------
-- Use the float type to define your own floating point numbers.
-- There must be a negative index or the packages will error out.
-- Minimum supported is "subtype float7 is float (3 downto -3);"
-- "subtype float16 is float (6 downto -9);" is probably the smallest
-- practical one to use.
-----------------------------------------------------------------------------
-- IEEE 754 single precision
subtype UNRESOLVED_float32 is UNRESOLVED_float (8 downto -23);
alias U_float32 is UNRESOLVED_float32;
subtype float32 is float (8 downto -23);
-----------------------------------------------------------------------------
-- IEEE-754 single precision floating point. This is a "float"
-- in C, and a FLOAT in Fortran. The exponent is 8 bits wide, and
-- the fraction is 23 bits wide. This format can hold roughly 7 decimal
-- digits. Infinity is 2**127 = 1.7E38 in this number system.
-- The bit representation is as follows:
-- 1 09876543 21098765432109876543210
-- 8 76543210 12345678901234567890123
-- 0 00000000 00000000000000000000000
-- 8 7 0 -1 -23
-- +/- exp. fraction
-----------------------------------------------------------------------------
-- IEEE 754 double precision
subtype UNRESOLVED_float64 is UNRESOLVED_float (11 downto -52);
alias U_float64 is UNRESOLVED_float64;
subtype float64 is float (11 downto -52);
-----------------------------------------------------------------------------
-- IEEE-754 double precision floating point. This is a "double float"
-- in C, and a FLOAT*8 in Fortran. The exponent is 11 bits wide, and
-- the fraction is 52 bits wide. This format can hold roughly 15 decimal
-- digits. Infinity is 2**2047 in this number system.
-- The bit representation is as follows:
-- 3 21098765432 1098765432109876543210987654321098765432109876543210
-- 1 09876543210 1234567890123456789012345678901234567890123456789012
-- S EEEEEEEEEEE FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF
-- 11 10 0 -1 -52
-- +/- exponent fraction
-----------------------------------------------------------------------------
-- IEEE 854 & C extended precision
subtype UNRESOLVED_float128 is UNRESOLVED_float (15 downto -112);
alias U_float128 is UNRESOLVED_float128;
subtype float128 is float (15 downto -112);
-----------------------------------------------------------------------------
-- The 128 bit floating point number is "long double" in C (on
-- some systems this is a 70 bit floating point number) and FLOAT*32
-- in Fortran. The exponent is 15 bits wide and the fraction is 112
-- bits wide. This number can handle approximately 33 decimal digits.
-- Infinity is 2**32,767 in this number system.
-----------------------------------------------------------------------------
-- purpose: Checks for a valid floating point number
type valid_fpstate is (nan, -- Signaling NaN (C FP_NAN)
quiet_nan, -- Quiet NaN (C FP_NAN)
neg_inf, -- Negative infinity (C FP_INFINITE)
neg_normal, -- negative normalized nonzero
neg_denormal, -- negative denormalized (FP_SUBNORMAL)
neg_zero, -- -0 (C FP_ZERO)
pos_zero, -- +0 (C FP_ZERO)
pos_denormal, -- Positive denormalized (FP_SUBNORMAL)
pos_normal, -- positive normalized nonzero
pos_inf, -- positive infinity
isx); -- at least one input is unknown
-- This deferred constant will tell you if the package body is synthesizable
-- or implemented as real numbers.
constant fphdlsynth_or_real : BOOLEAN; -- deferred constant
-- Returns the class which X falls into
function Classfp (
x : UNRESOLVED_float; -- floating point input
check_error : BOOLEAN := float_check_error) -- check for errors
return valid_fpstate;
-- Arithmetic functions, these operators do not require parameters.
function "abs" (arg : UNRESOLVED_float) return UNRESOLVED_float;
function "-" (arg : UNRESOLVED_float) return UNRESOLVED_float;
-- These allows the base math functions to use the default values
-- of their parameters. Thus they do full IEEE floating point.
function "+" (l, r : UNRESOLVED_float) return UNRESOLVED_float;
function "-" (l, r : UNRESOLVED_float) return UNRESOLVED_float;
function "*" (l, r : UNRESOLVED_float) return UNRESOLVED_float;
function "/" (l, r : UNRESOLVED_float) return UNRESOLVED_float;
function "rem" (l, r : UNRESOLVED_float) return UNRESOLVED_float;
function "mod" (l, r : UNRESOLVED_float) return UNRESOLVED_float;
-- Basic parameter list
-- round_style - Selects the rounding algorithm to use
-- guard - extra bits added to the end if the operation to add precision
-- check_error - When "false" turns off NAN and overflow checks
-- denormalize - When "false" turns off denormal number processing
function add (
l, r : UNRESOLVED_float; -- floating point input
constant round_style : round_type := float_round_style; -- rounding option
constant guard : NATURAL := float_guard_bits; -- number of guard bits
constant check_error : BOOLEAN := float_check_error; -- check for errors
constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP
return UNRESOLVED_float;
function subtract (
l, r : UNRESOLVED_float; -- floating point input
constant round_style : round_type := float_round_style; -- rounding option
constant guard : NATURAL := float_guard_bits; -- number of guard bits
constant check_error : BOOLEAN := float_check_error; -- check for errors
constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP
return UNRESOLVED_float;
function multiply (
l, r : UNRESOLVED_float; -- floating point input
constant round_style : round_type := float_round_style; -- rounding option
constant guard : NATURAL := float_guard_bits; -- number of guard bits
constant check_error : BOOLEAN := float_check_error; -- check for errors
constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP
return UNRESOLVED_float;
function divide (
l, r : UNRESOLVED_float; -- floating point input
constant round_style : round_type := float_round_style; -- rounding option
constant guard : NATURAL := float_guard_bits; -- number of guard bits
constant check_error : BOOLEAN := float_check_error; -- check for errors
constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP
return UNRESOLVED_float;
function remainder (
l, r : UNRESOLVED_float; -- floating point input
constant round_style : round_type := float_round_style; -- rounding option
constant guard : NATURAL := float_guard_bits; -- number of guard bits
constant check_error : BOOLEAN := float_check_error; -- check for errors
constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP
return UNRESOLVED_float;
function modulo (
l, r : UNRESOLVED_float; -- floating point input
constant round_style : round_type := float_round_style; -- rounding option
constant guard : NATURAL := float_guard_bits; -- number of guard bits
constant check_error : BOOLEAN := float_check_error; -- check for errors
constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP
return UNRESOLVED_float;
-- reciprocal
function reciprocal (
arg : UNRESOLVED_float; -- floating point input
constant round_style : round_type := float_round_style; -- rounding option
constant guard : NATURAL := float_guard_bits; -- number of guard bits
constant check_error : BOOLEAN := float_check_error; -- check for errors
constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP
return UNRESOLVED_float;
function dividebyp2 (
l, r : UNRESOLVED_float; -- floating point input
constant round_style : round_type := float_round_style; -- rounding option
constant guard : NATURAL := float_guard_bits; -- number of guard bits
constant check_error : BOOLEAN := float_check_error; -- check for errors
constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP
return UNRESOLVED_float;
-- Multiply accumulate result = l*r + c
function mac (
l, r, c : UNRESOLVED_float; -- floating point input
constant round_style : round_type := float_round_style; -- rounding option
constant guard : NATURAL := float_guard_bits; -- number of guard bits
constant check_error : BOOLEAN := float_check_error; -- check for errors
constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP
return UNRESOLVED_float;
-- Square root (all 754 based implementations need this)
function sqrt (
arg : UNRESOLVED_float; -- floating point input
constant round_style : round_type := float_round_style;
constant guard : NATURAL := float_guard_bits;
constant check_error : BOOLEAN := float_check_error;
constant denormalize : BOOLEAN := float_denormalize)
return UNRESOLVED_float;
function Is_Negative (arg : UNRESOLVED_float) return BOOLEAN;
-----------------------------------------------------------------------------
-- compare functions
-- =, /=, >=, <=, <, >, maximum, minimum
function eq ( -- equal =
l, r : UNRESOLVED_float; -- floating point input
constant check_error : BOOLEAN := float_check_error;
constant denormalize : BOOLEAN := float_denormalize)
return BOOLEAN;
function ne ( -- not equal /=
l, r : UNRESOLVED_float; -- floating point input
constant check_error : BOOLEAN := float_check_error;
constant denormalize : BOOLEAN := float_denormalize)
return BOOLEAN;
function lt ( -- less than <
l, r : UNRESOLVED_float; -- floating point input
constant check_error : BOOLEAN := float_check_error;
constant denormalize : BOOLEAN := float_denormalize)
return BOOLEAN;
function gt ( -- greater than >
l, r : UNRESOLVED_float; -- floating point input
constant check_error : BOOLEAN := float_check_error;
constant denormalize : BOOLEAN := float_denormalize)
return BOOLEAN;
function le ( -- less than or equal to <=
l, r : UNRESOLVED_float; -- floating point input
constant check_error : BOOLEAN := float_check_error;
constant denormalize : BOOLEAN := float_denormalize)
return BOOLEAN;
function ge ( -- greater than or equal to >=
l, r : UNRESOLVED_float; -- floating point input
constant check_error : BOOLEAN := float_check_error;
constant denormalize : BOOLEAN := float_denormalize)
return BOOLEAN;
-- Need to overload the default versions of these
function "=" (l, r : UNRESOLVED_float) return BOOLEAN;
function "/=" (l, r : UNRESOLVED_float) return BOOLEAN;
function ">=" (l, r : UNRESOLVED_float) return BOOLEAN;
function "<=" (l, r : UNRESOLVED_float) return BOOLEAN;
function ">" (l, r : UNRESOLVED_float) return BOOLEAN;
function "<" (l, r : UNRESOLVED_float) return BOOLEAN;
function "?=" (l, r : UNRESOLVED_float) return STD_ULOGIC;
function "?/=" (l, r : UNRESOLVED_float) return STD_ULOGIC;
function "?>" (l, r : UNRESOLVED_float) return STD_ULOGIC;
function "?>=" (l, r : UNRESOLVED_float) return STD_ULOGIC;
function "?<" (l, r : UNRESOLVED_float) return STD_ULOGIC;
function "?<=" (l, r : UNRESOLVED_float) return STD_ULOGIC;
function std_match (l, r : UNRESOLVED_float) return BOOLEAN;
function find_rightmost (arg : UNRESOLVED_float; y : STD_ULOGIC)
return INTEGER;
function find_leftmost (arg : UNRESOLVED_float; y : STD_ULOGIC)
return INTEGER;
function maximum (l, r : UNRESOLVED_float) return UNRESOLVED_float;
function minimum (l, r : UNRESOLVED_float) return UNRESOLVED_float;
-- conversion functions
-- Converts one floating point number into another.
function resize (
arg : UNRESOLVED_float; -- Floating point input
constant exponent_width : NATURAL := float_exponent_width; -- length of FP output exponent
constant fraction_width : NATURAL := float_fraction_width; -- length of FP output fraction
constant round_style : round_type := float_round_style; -- rounding option
constant check_error : BOOLEAN := float_check_error;
constant denormalize_in : BOOLEAN := float_denormalize; -- Use IEEE extended FP
constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP
return UNRESOLVED_float;
function resize (
arg : UNRESOLVED_float; -- Floating point input
size_res : UNRESOLVED_float;
constant round_style : round_type := float_round_style; -- rounding option
constant check_error : BOOLEAN := float_check_error;
constant denormalize_in : BOOLEAN := float_denormalize; -- Use IEEE extended FP
constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP
return UNRESOLVED_float;
function to_float32 (
arg : UNRESOLVED_float;
constant round_style : round_type := float_round_style; -- rounding option
constant check_error : BOOLEAN := float_check_error;
constant denormalize_in : BOOLEAN := float_denormalize; -- Use IEEE extended FP
constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP
return UNRESOLVED_float32;
function to_float64 (
arg : UNRESOLVED_float;
constant round_style : round_type := float_round_style; -- rounding option
constant check_error : BOOLEAN := float_check_error;
constant denormalize_in : BOOLEAN := float_denormalize; -- Use IEEE extended FP
constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP
return UNRESOLVED_float64;
function to_float128 (
arg : UNRESOLVED_float;
constant round_style : round_type := float_round_style; -- rounding option
constant check_error : BOOLEAN := float_check_error;
constant denormalize_in : BOOLEAN := float_denormalize; -- Use IEEE extended FP
constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP
return UNRESOLVED_float128;
-- Converts an fp into an SLV (needed for synthesis)
function to_slv (arg : UNRESOLVED_float) return STD_LOGIC_VECTOR;
alias to_StdLogicVector is to_slv [UNRESOLVED_float return STD_LOGIC_VECTOR];
alias to_Std_Logic_Vector is to_slv [UNRESOLVED_float return STD_LOGIC_VECTOR];
-- Converts an fp into an std_ulogic_vector (sulv)
function to_sulv (arg : UNRESOLVED_float) return STD_ULOGIC_VECTOR;
alias to_StdULogicVector is to_sulv [UNRESOLVED_float return STD_ULOGIC_VECTOR];
alias to_Std_ULogic_Vector is to_sulv [UNRESOLVED_float return STD_ULOGIC_VECTOR];
-- std_ulogic_vector to float
function to_float (
arg : STD_ULOGIC_VECTOR;
constant exponent_width : NATURAL := float_exponent_width; -- length of FP output exponent
constant fraction_width : NATURAL := float_fraction_width) -- length of FP output fraction
return UNRESOLVED_float;
-- Integer to float
function to_float (
arg : INTEGER;
constant exponent_width : NATURAL := float_exponent_width; -- length of FP output exponent
constant fraction_width : NATURAL := float_fraction_width; -- length of FP output fraction
constant round_style : round_type := float_round_style) -- rounding option
return UNRESOLVED_float;
-- real to float
function to_float (
arg : REAL;
constant exponent_width : NATURAL := float_exponent_width; -- length of FP output exponent
constant fraction_width : NATURAL := float_fraction_width; -- length of FP output fraction
constant round_style : round_type := float_round_style; -- rounding option
constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP
return UNRESOLVED_float;
-- unsigned to float
function to_float (
arg : UNRESOLVED_UNSIGNED;
constant exponent_width : NATURAL := float_exponent_width; -- length of FP output exponent
constant fraction_width : NATURAL := float_fraction_width; -- length of FP output fraction
constant round_style : round_type := float_round_style) -- rounding option
return UNRESOLVED_float;
-- signed to float
function to_float (
arg : UNRESOLVED_SIGNED;
constant exponent_width : NATURAL := float_exponent_width; -- length of FP output exponent
constant fraction_width : NATURAL := float_fraction_width; -- length of FP output fraction
constant round_style : round_type := float_round_style) -- rounding option
return UNRESOLVED_float;
-- unsigned fixed point to float
function to_float (
arg : UNRESOLVED_ufixed; -- unsigned fixed point input
constant exponent_width : NATURAL := float_exponent_width; -- width of exponent
constant fraction_width : NATURAL := float_fraction_width; -- width of fraction
constant round_style : round_type := float_round_style; -- rounding
constant denormalize : BOOLEAN := float_denormalize) -- use ieee extensions
return UNRESOLVED_float;
-- signed fixed point to float
function to_float (
arg : UNRESOLVED_sfixed;
constant exponent_width : NATURAL := float_exponent_width; -- length of FP output exponent
constant fraction_width : NATURAL := float_fraction_width; -- length of FP output fraction
constant round_style : round_type := float_round_style; -- rounding
constant denormalize : BOOLEAN := float_denormalize) -- rounding option
return UNRESOLVED_float;
-- size_res functions
-- Integer to float
function to_float (
arg : INTEGER;
size_res : UNRESOLVED_float;
constant round_style : round_type := float_round_style) -- rounding option
return UNRESOLVED_float;
-- real to float
function to_float (
arg : REAL;
size_res : UNRESOLVED_float;
constant round_style : round_type := float_round_style; -- rounding option
constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP
return UNRESOLVED_float;
-- unsigned to float
function to_float (
arg : UNRESOLVED_UNSIGNED;
size_res : UNRESOLVED_float;
constant round_style : round_type := float_round_style) -- rounding option
return UNRESOLVED_float;
-- signed to float
function to_float (
arg : UNRESOLVED_SIGNED;
size_res : UNRESOLVED_float;
constant round_style : round_type := float_round_style) -- rounding option
return UNRESOLVED_float;
-- sulv to float
function to_float (
arg : STD_ULOGIC_VECTOR;
size_res : UNRESOLVED_float)
return UNRESOLVED_float;
-- unsigned fixed point to float
function to_float (
arg : UNRESOLVED_ufixed; -- unsigned fixed point input
size_res : UNRESOLVED_float;
constant round_style : round_type := float_round_style; -- rounding
constant denormalize : BOOLEAN := float_denormalize) -- use ieee extensions
return UNRESOLVED_float;
-- signed fixed point to float
function to_float (
arg : UNRESOLVED_sfixed;
size_res : UNRESOLVED_float;
constant round_style : round_type := float_round_style; -- rounding
constant denormalize : BOOLEAN := float_denormalize) -- rounding option
return UNRESOLVED_float;
-- float to unsigned
function to_unsigned (
arg : UNRESOLVED_float; -- floating point input
constant size : NATURAL; -- length of output
constant round_style : round_type := float_round_style; -- rounding option
constant check_error : BOOLEAN := float_check_error) -- check for errors
return UNRESOLVED_UNSIGNED;
-- float to signed
function to_signed (
arg : UNRESOLVED_float; -- floating point input
constant size : NATURAL; -- length of output
constant round_style : round_type := float_round_style; -- rounding option
constant check_error : BOOLEAN := float_check_error) -- check for errors
return UNRESOLVED_SIGNED;
-- purpose: Converts a float to unsigned fixed point
function to_ufixed (
arg : UNRESOLVED_float; -- fp input
constant left_index : INTEGER; -- integer part
constant right_index : INTEGER; -- fraction part
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style; -- saturate
constant round_style : fixed_round_style_type := fixed_round_style; -- rounding
constant check_error : BOOLEAN := float_check_error; -- check for errors
constant denormalize : BOOLEAN := float_denormalize)
return UNRESOLVED_ufixed;
-- float to signed fixed point
function to_sfixed (
arg : UNRESOLVED_float; -- fp input
constant left_index : INTEGER; -- integer part
constant right_index : INTEGER; -- fraction part
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style; -- saturate
constant round_style : fixed_round_style_type := fixed_round_style; -- rounding
constant check_error : BOOLEAN := float_check_error; -- check for errors
constant denormalize : BOOLEAN := float_denormalize)
return UNRESOLVED_sfixed;
-- size_res versions
-- float to unsigned
function to_unsigned (
arg : UNRESOLVED_float; -- floating point input
size_res : UNRESOLVED_UNSIGNED;
constant round_style : round_type := float_round_style; -- rounding option
constant check_error : BOOLEAN := float_check_error) -- check for errors
return UNRESOLVED_UNSIGNED;
-- float to signed
function to_signed (
arg : UNRESOLVED_float; -- floating point input
size_res : UNRESOLVED_SIGNED;
constant round_style : round_type := float_round_style; -- rounding option
constant check_error : BOOLEAN := float_check_error) -- check for errors
return UNRESOLVED_SIGNED;
-- purpose: Converts a float to unsigned fixed point
function to_ufixed (
arg : UNRESOLVED_float; -- fp input
size_res : UNRESOLVED_ufixed;
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style; -- saturate
constant round_style : fixed_round_style_type := fixed_round_style; -- rounding
constant check_error : BOOLEAN := float_check_error; -- check for errors
constant denormalize : BOOLEAN := float_denormalize)
return UNRESOLVED_ufixed;
-- float to signed fixed point
function to_sfixed (
arg : UNRESOLVED_float; -- fp input
size_res : UNRESOLVED_sfixed;
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style; -- saturate
constant round_style : fixed_round_style_type := fixed_round_style; -- rounding
constant check_error : BOOLEAN := float_check_error; -- check for errors
constant denormalize : BOOLEAN := float_denormalize)
return UNRESOLVED_sfixed;
-- float to real
function to_real (
arg : UNRESOLVED_float; -- floating point input
constant check_error : BOOLEAN := float_check_error; -- check for errors
constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP
return REAL;
-- float to integer
function to_integer (
arg : UNRESOLVED_float; -- floating point input
constant round_style : round_type := float_round_style; -- rounding option
constant check_error : BOOLEAN := float_check_error) -- check for errors
return INTEGER;
-- For Verilog compatability
function realtobits (arg : REAL) return STD_ULOGIC_VECTOR;
function bitstoreal (arg : STD_ULOGIC_VECTOR) return REAL;
-- Maps metalogical values
function to_01 (
arg : UNRESOLVED_float; -- floating point input
XMAP : STD_LOGIC := '0')
return UNRESOLVED_float;
function Is_X (arg : UNRESOLVED_float) return BOOLEAN;
function to_X01 (arg : UNRESOLVED_float) return UNRESOLVED_float;
function to_X01Z (arg : UNRESOLVED_float) return UNRESOLVED_float;
function to_UX01 (arg : UNRESOLVED_float) return UNRESOLVED_float;
-- These two procedures were copied out of the body because they proved
-- very useful for vendor specific algorithm development
-- Break_number converts a floating point number into it's parts
-- Exponent is biased by -1
procedure break_number (
arg : in UNRESOLVED_float;
denormalize : in BOOLEAN := float_denormalize;
check_error : in BOOLEAN := float_check_error;
fract : out UNRESOLVED_UNSIGNED;
expon : out UNRESOLVED_SIGNED; -- NOTE: Add 1 to get the real exponent!
sign : out STD_ULOGIC);
procedure break_number (
arg : in UNRESOLVED_float;
denormalize : in BOOLEAN := float_denormalize;
check_error : in BOOLEAN := float_check_error;
fract : out UNRESOLVED_ufixed; -- a number between 1.0 and 2.0
expon : out UNRESOLVED_SIGNED; -- NOTE: Add 1 to get the real exponent!
sign : out STD_ULOGIC);
-- Normalize takes a fraction and and exponent and converts them into
-- a floating point number. Does the shifting and the rounding.
-- Exponent is assumed to be biased by -1
function normalize (
fract : UNRESOLVED_UNSIGNED; -- fraction, unnormalized
expon : UNRESOLVED_SIGNED; -- exponent - 1, normalized
sign : STD_ULOGIC; -- sign bit
sticky : STD_ULOGIC := '0'; -- Sticky bit (rounding)
constant exponent_width : NATURAL := float_exponent_width; -- size of output exponent
constant fraction_width : NATURAL := float_fraction_width; -- size of output fraction
constant round_style : round_type := float_round_style; -- rounding option
constant denormalize : BOOLEAN := float_denormalize; -- Use IEEE extended FP
constant nguard : NATURAL := float_guard_bits) -- guard bits
return UNRESOLVED_float;
-- Exponent is assumed to be biased by -1
function normalize (
fract : UNRESOLVED_ufixed; -- unsigned fixed point
expon : UNRESOLVED_SIGNED; -- exponent - 1, normalized
sign : STD_ULOGIC; -- sign bit
sticky : STD_ULOGIC := '0'; -- Sticky bit (rounding)
constant exponent_width : NATURAL := float_exponent_width; -- size of output exponent
constant fraction_width : NATURAL := float_fraction_width; -- size of output fraction
constant round_style : round_type := float_round_style; -- rounding option
constant denormalize : BOOLEAN := float_denormalize; -- Use IEEE extended FP
constant nguard : NATURAL := float_guard_bits) -- guard bits
return UNRESOLVED_float;
function normalize (
fract : UNRESOLVED_UNSIGNED; -- unsigned
expon : UNRESOLVED_SIGNED; -- exponent - 1, normalized
sign : STD_ULOGIC; -- sign bit
sticky : STD_ULOGIC := '0'; -- Sticky bit (rounding)
size_res : UNRESOLVED_float; -- used for sizing only
constant round_style : round_type := float_round_style; -- rounding option
constant denormalize : BOOLEAN := float_denormalize; -- Use IEEE extended FP
constant nguard : NATURAL := float_guard_bits) -- guard bits
return UNRESOLVED_float;
-- Exponent is assumed to be biased by -1
function normalize (
fract : UNRESOLVED_ufixed; -- unsigned fixed point
expon : UNRESOLVED_SIGNED; -- exponent - 1, normalized
sign : STD_ULOGIC; -- sign bit
sticky : STD_ULOGIC := '0'; -- Sticky bit (rounding)
size_res : UNRESOLVED_float; -- used for sizing only
constant round_style : round_type := float_round_style; -- rounding option
constant denormalize : BOOLEAN := float_denormalize; -- Use IEEE extended FP
constant nguard : NATURAL := float_guard_bits) -- guard bits
return UNRESOLVED_float;
-- overloaded versions
function "+" (l : UNRESOLVED_float; r : REAL) return UNRESOLVED_float;
function "+" (l : REAL; r : UNRESOLVED_float) return UNRESOLVED_float;
function "+" (l : UNRESOLVED_float; r : INTEGER) return UNRESOLVED_float;
function "+" (l : INTEGER; r : UNRESOLVED_float) return UNRESOLVED_float;
function "-" (l : UNRESOLVED_float; r : REAL) return UNRESOLVED_float;
function "-" (l : REAL; r : UNRESOLVED_float) return UNRESOLVED_float;
function "-" (l : UNRESOLVED_float; r : INTEGER) return UNRESOLVED_float;
function "-" (l : INTEGER; r : UNRESOLVED_float) return UNRESOLVED_float;
function "*" (l : UNRESOLVED_float; r : REAL) return UNRESOLVED_float;
function "*" (l : REAL; r : UNRESOLVED_float) return UNRESOLVED_float;
function "*" (l : UNRESOLVED_float; r : INTEGER) return UNRESOLVED_float;
function "*" (l : INTEGER; r : UNRESOLVED_float) return UNRESOLVED_float;
function "/" (l : UNRESOLVED_float; r : REAL) return UNRESOLVED_float;
function "/" (l : REAL; r : UNRESOLVED_float) return UNRESOLVED_float;
function "/" (l : UNRESOLVED_float; r : INTEGER) return UNRESOLVED_float;
function "/" (l : INTEGER; r : UNRESOLVED_float) return UNRESOLVED_float;
function "rem" (l : UNRESOLVED_float; r : REAL) return UNRESOLVED_float;
function "rem" (l : REAL; r : UNRESOLVED_float) return UNRESOLVED_float;
function "rem" (l : UNRESOLVED_float; r : INTEGER) return UNRESOLVED_float;
function "rem" (l : INTEGER; r : UNRESOLVED_float) return UNRESOLVED_float;
function "mod" (l : UNRESOLVED_float; r : REAL) return UNRESOLVED_float;
function "mod" (l : REAL; r : UNRESOLVED_float) return UNRESOLVED_float;
function "mod" (l : UNRESOLVED_float; r : INTEGER) return UNRESOLVED_float;
function "mod" (l : INTEGER; r : UNRESOLVED_float) return UNRESOLVED_float;
-- overloaded compare functions
function "=" (l : UNRESOLVED_float; r : REAL) return BOOLEAN;
function "/=" (l : UNRESOLVED_float; r : REAL) return BOOLEAN;
function ">=" (l : UNRESOLVED_float; r : REAL) return BOOLEAN;
function "<=" (l : UNRESOLVED_float; r : REAL) return BOOLEAN;
function ">" (l : UNRESOLVED_float; r : REAL) return BOOLEAN;
function "<" (l : UNRESOLVED_float; r : REAL) return BOOLEAN;
function "=" (l : REAL; r : UNRESOLVED_float) return BOOLEAN;
function "/=" (l : REAL; r : UNRESOLVED_float) return BOOLEAN;
function ">=" (l : REAL; r : UNRESOLVED_float) return BOOLEAN;
function "<=" (l : REAL; r : UNRESOLVED_float) return BOOLEAN;
function ">" (l : REAL; r : UNRESOLVED_float) return BOOLEAN;
function "<" (l : REAL; r : UNRESOLVED_float) return BOOLEAN;
function "=" (l : UNRESOLVED_float; r : INTEGER) return BOOLEAN;
function "/=" (l : UNRESOLVED_float; r : INTEGER) return BOOLEAN;
function ">=" (l : UNRESOLVED_float; r : INTEGER) return BOOLEAN;
function "<=" (l : UNRESOLVED_float; r : INTEGER) return BOOLEAN;
function ">" (l : UNRESOLVED_float; r : INTEGER) return BOOLEAN;
function "<" (l : UNRESOLVED_float; r : INTEGER) return BOOLEAN;
function "=" (l : INTEGER; r : UNRESOLVED_float) return BOOLEAN;
function "/=" (l : INTEGER; r : UNRESOLVED_float) return BOOLEAN;
function ">=" (l : INTEGER; r : UNRESOLVED_float) return BOOLEAN;
function "<=" (l : INTEGER; r : UNRESOLVED_float) return BOOLEAN;
function ">" (l : INTEGER; r : UNRESOLVED_float) return BOOLEAN;
function "<" (l : INTEGER; r : UNRESOLVED_float) return BOOLEAN;
function "?=" (l : UNRESOLVED_float; r : REAL) return STD_ULOGIC;
function "?/=" (l : UNRESOLVED_float; r : REAL) return STD_ULOGIC;
function "?>" (l : UNRESOLVED_float; r : REAL) return STD_ULOGIC;
function "?>=" (l : UNRESOLVED_float; r : REAL) return STD_ULOGIC;
function "?<" (l : UNRESOLVED_float; r : REAL) return STD_ULOGIC;
function "?<=" (l : UNRESOLVED_float; r : REAL) return STD_ULOGIC;
function "?=" (l : REAL; r : UNRESOLVED_float) return STD_ULOGIC;
function "?/=" (l : REAL; r : UNRESOLVED_float) return STD_ULOGIC;
function "?>" (l : REAL; r : UNRESOLVED_float) return STD_ULOGIC;
function "?>=" (l : REAL; r : UNRESOLVED_float) return STD_ULOGIC;
function "?<" (l : REAL; r : UNRESOLVED_float) return STD_ULOGIC;
function "?<=" (l : REAL; r : UNRESOLVED_float) return STD_ULOGIC;
function "?=" (l : UNRESOLVED_float; r : INTEGER) return STD_ULOGIC;
function "?/=" (l : UNRESOLVED_float; r : INTEGER) return STD_ULOGIC;
function "?>" (l : UNRESOLVED_float; r : INTEGER) return STD_ULOGIC;
function "?>=" (l : UNRESOLVED_float; r : INTEGER) return STD_ULOGIC;
function "?<" (l : UNRESOLVED_float; r : INTEGER) return STD_ULOGIC;
function "?<=" (l : UNRESOLVED_float; r : INTEGER) return STD_ULOGIC;
function "?=" (l : INTEGER; r : UNRESOLVED_float) return STD_ULOGIC;
function "?/=" (l : INTEGER; r : UNRESOLVED_float) return STD_ULOGIC;
function "?>" (l : INTEGER; r : UNRESOLVED_float) return STD_ULOGIC;
function "?>=" (l : INTEGER; r : UNRESOLVED_float) return STD_ULOGIC;
function "?<" (l : INTEGER; r : UNRESOLVED_float) return STD_ULOGIC;
function "?<=" (l : INTEGER; r : UNRESOLVED_float) return STD_ULOGIC;
-- minimum and maximum overloads
function maximum (l : UNRESOLVED_float; r : REAL) return UNRESOLVED_float;
function minimum (l : UNRESOLVED_float; r : REAL) return UNRESOLVED_float;
function maximum (l : REAL; r : UNRESOLVED_float) return UNRESOLVED_float;
function minimum (l : REAL; r : UNRESOLVED_float) return UNRESOLVED_float;
function maximum (l : UNRESOLVED_float; r : INTEGER) return UNRESOLVED_float;
function minimum (l : UNRESOLVED_float; r : INTEGER) return UNRESOLVED_float;
function maximum (l : INTEGER; r : UNRESOLVED_float) return UNRESOLVED_float;
function minimum (l : INTEGER; r : UNRESOLVED_float) return UNRESOLVED_float;
----------------------------------------------------------------------------
-- logical functions
----------------------------------------------------------------------------
function "not" (l : UNRESOLVED_float) return UNRESOLVED_float;
function "and" (l, r : UNRESOLVED_float) return UNRESOLVED_float;
function "or" (l, r : UNRESOLVED_float) return UNRESOLVED_float;
function "nand" (l, r : UNRESOLVED_float) return UNRESOLVED_float;
function "nor" (l, r : UNRESOLVED_float) return UNRESOLVED_float;
function "xor" (l, r : UNRESOLVED_float) return UNRESOLVED_float;
function "xnor" (l, r : UNRESOLVED_float) return UNRESOLVED_float;
-- Vector and std_ulogic functions, same as functions in numeric_std
function "and" (l : STD_ULOGIC; r : UNRESOLVED_float)
return UNRESOLVED_float;
function "and" (l : UNRESOLVED_float; r : STD_ULOGIC)
return UNRESOLVED_float;
function "or" (l : STD_ULOGIC; r : UNRESOLVED_float)
return UNRESOLVED_float;
function "or" (l : UNRESOLVED_float; r : STD_ULOGIC)
return UNRESOLVED_float;
function "nand" (l : STD_ULOGIC; r : UNRESOLVED_float)
return UNRESOLVED_float;
function "nand" (l : UNRESOLVED_float; r : STD_ULOGIC)
return UNRESOLVED_float;
function "nor" (l : STD_ULOGIC; r : UNRESOLVED_float)
return UNRESOLVED_float;
function "nor" (l : UNRESOLVED_float; r : STD_ULOGIC)
return UNRESOLVED_float;
function "xor" (l : STD_ULOGIC; r : UNRESOLVED_float)
return UNRESOLVED_float;
function "xor" (l : UNRESOLVED_float; r : STD_ULOGIC)
return UNRESOLVED_float;
function "xnor" (l : STD_ULOGIC; r : UNRESOLVED_float)
return UNRESOLVED_float;
function "xnor" (l : UNRESOLVED_float; r : STD_ULOGIC)
return UNRESOLVED_float;
-- Reduction operators, same as numeric_std functions
function "and" (l : UNRESOLVED_float) return STD_ULOGIC;
function "nand" (l : UNRESOLVED_float) return STD_ULOGIC;
function "or" (l : UNRESOLVED_float) return STD_ULOGIC;
function "nor" (l : UNRESOLVED_float) return STD_ULOGIC;
function "xor" (l : UNRESOLVED_float) return STD_ULOGIC;
function "xnor" (l : UNRESOLVED_float) return STD_ULOGIC;
-- Note: "sla", "sra", "sll", "slr", "rol" and "ror" not implemented.
-----------------------------------------------------------------------------
-- Recommended Functions from the IEEE 754 Appendix
-----------------------------------------------------------------------------
-- returns x with the sign of y.
function Copysign (x, y : UNRESOLVED_float) return UNRESOLVED_float;
-- Returns y * 2**n for integral values of N without computing 2**n
function Scalb (
y : UNRESOLVED_float; -- floating point input
N : INTEGER; -- exponent to add
constant round_style : round_type := float_round_style; -- rounding option
constant check_error : BOOLEAN := float_check_error; -- check for errors
constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP
return UNRESOLVED_float;
-- Returns y * 2**n for integral values of N without computing 2**n
function Scalb (
y : UNRESOLVED_float; -- floating point input
N : UNRESOLVED_SIGNED; -- exponent to add
constant round_style : round_type := float_round_style; -- rounding option
constant check_error : BOOLEAN := float_check_error; -- check for errors
constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP
return UNRESOLVED_float;
-- returns the unbiased exponent of x
function Logb (x : UNRESOLVED_float) return INTEGER;
function Logb (x : UNRESOLVED_float) return UNRESOLVED_SIGNED;
-- returns the next representable neighbor of x in the direction toward y
function Nextafter (
x, y : UNRESOLVED_float; -- floating point input
constant check_error : BOOLEAN := float_check_error; -- check for errors
constant denormalize : BOOLEAN := float_denormalize)
return UNRESOLVED_float;
-- Returns TRUE if X is unordered with Y.
function Unordered (x, y : UNRESOLVED_float) return BOOLEAN;
function Finite (x : UNRESOLVED_float) return BOOLEAN;
function Isnan (x : UNRESOLVED_float) return BOOLEAN;
-- Function to return constants.
function zerofp (
constant exponent_width : NATURAL := float_exponent_width; -- exponent
constant fraction_width : NATURAL := float_fraction_width) -- fraction
return UNRESOLVED_float;
function nanfp (
constant exponent_width : NATURAL := float_exponent_width; -- exponent
constant fraction_width : NATURAL := float_fraction_width) -- fraction
return UNRESOLVED_float;
function qnanfp (
constant exponent_width : NATURAL := float_exponent_width; -- exponent
constant fraction_width : NATURAL := float_fraction_width) -- fraction
return UNRESOLVED_float;
function pos_inffp (
constant exponent_width : NATURAL := float_exponent_width; -- exponent
constant fraction_width : NATURAL := float_fraction_width) -- fraction
return UNRESOLVED_float;
function neg_inffp (
constant exponent_width : NATURAL := float_exponent_width; -- exponent
constant fraction_width : NATURAL := float_fraction_width) -- fraction
return UNRESOLVED_float;
function neg_zerofp (
constant exponent_width : NATURAL := float_exponent_width; -- exponent
constant fraction_width : NATURAL := float_fraction_width) -- fraction
return UNRESOLVED_float;
-- size_res versions
function zerofp (
size_res : UNRESOLVED_float) -- variable is only use for sizing
return UNRESOLVED_float;
function nanfp (
size_res : UNRESOLVED_float) -- variable is only use for sizing
return UNRESOLVED_float;
function qnanfp (
size_res : UNRESOLVED_float) -- variable is only use for sizing
return UNRESOLVED_float;
function pos_inffp (
size_res : UNRESOLVED_float) -- variable is only use for sizing
return UNRESOLVED_float;
function neg_inffp (
size_res : UNRESOLVED_float) -- variable is only use for sizing
return UNRESOLVED_float;
function neg_zerofp (
size_res : UNRESOLVED_float) -- variable is only use for sizing
return UNRESOLVED_float;
--===========================================================================
-- string and textio Functions
--===========================================================================
-- writes S:EEEE:FFFFFFFF
procedure WRITE (
L : inout LINE; -- access type (pointer)
VALUE : in UNRESOLVED_float; -- value to write
JUSTIFIED : in SIDE := right; -- which side to justify text
FIELD : in WIDTH := 0); -- width of field
-- Reads SEEEEFFFFFFFF, "." and ":" are ignored
procedure READ (L : inout LINE; VALUE : out UNRESOLVED_float);
procedure READ (L : inout LINE; VALUE : out UNRESOLVED_float;
GOOD : out BOOLEAN);
alias BREAD is READ [LINE, UNRESOLVED_float, BOOLEAN];
alias BREAD is READ [LINE, UNRESOLVED_float];
alias BWRITE is WRITE [LINE, UNRESOLVED_float, SIDE, WIDTH];
alias BINARY_READ is READ [LINE, UNRESOLVED_FLOAT, BOOLEAN];
alias BINARY_READ is READ [LINE, UNRESOLVED_FLOAT];
alias BINARY_WRITE is WRITE [LINE, UNRESOLVED_float, SIDE, WIDTH];
procedure OWRITE (
L : inout LINE; -- access type (pointer)
VALUE : in UNRESOLVED_float; -- value to write
JUSTIFIED : in SIDE := right; -- which side to justify text
FIELD : in WIDTH := 0); -- width of field
-- Octal read with padding, no separators used
procedure OREAD (L : inout LINE; VALUE : out UNRESOLVED_float);
procedure OREAD (L : inout LINE; VALUE : out UNRESOLVED_float;
GOOD : out BOOLEAN);
alias OCTAL_READ is OREAD [LINE, UNRESOLVED_FLOAT, BOOLEAN];
alias OCTAL_READ is OREAD [LINE, UNRESOLVED_FLOAT];
alias OCTAL_WRITE is OWRITE [LINE, UNRESOLVED_FLOAT, SIDE, WIDTH];
-- Hex write with padding, no separators
procedure HWRITE (
L : inout LINE; -- access type (pointer)
VALUE : in UNRESOLVED_float; -- value to write
JUSTIFIED : in SIDE := right; -- which side to justify text
FIELD : in WIDTH := 0); -- width of field
-- Hex read with padding, no separators used
procedure HREAD (L : inout LINE; VALUE : out UNRESOLVED_float);
procedure HREAD (L : inout LINE; VALUE : out UNRESOLVED_float;
GOOD : out BOOLEAN);
alias HEX_READ is HREAD [LINE, UNRESOLVED_FLOAT, BOOLEAN];
alias HEX_READ is HREAD [LINE, UNRESOLVED_FLOAT];
alias HEX_WRITE is HWRITE [LINE, UNRESOLVED_FLOAT, SIDE, WIDTH];
-- returns "S:EEEE:FFFFFFFF"
function to_string (value : UNRESOLVED_float) return STRING;
alias TO_BSTRING is TO_STRING [UNRESOLVED_FLOAT return STRING];
alias TO_BINARY_STRING is TO_STRING [UNRESOLVED_FLOAT return STRING];
-- Returns a HEX string, with padding
function to_hstring (value : UNRESOLVED_float) return STRING;
alias TO_HEX_STRING is TO_HSTRING [UNRESOLVED_FLOAT return STRING];
-- Returns and octal string, with padding
function to_ostring (value : UNRESOLVED_float) return STRING;
alias TO_OCTAL_STRING is TO_OSTRING [UNRESOLVED_FLOAT return STRING];
function from_string (
bstring : STRING; -- binary string
constant exponent_width : NATURAL := float_exponent_width;
constant fraction_width : NATURAL := float_fraction_width)
return UNRESOLVED_float;
alias from_bstring is from_string [STRING, NATURAL, NATURAL
return UNRESOLVED_float];
alias from_binary_string is from_string [STRING, NATURAL, NATURAL
return UNRESOLVED_float];
function from_ostring (
ostring : STRING; -- Octal string
constant exponent_width : NATURAL := float_exponent_width;
constant fraction_width : NATURAL := float_fraction_width)
return UNRESOLVED_float;
alias from_octal_string is from_ostring [STRING, NATURAL, NATURAL
return UNRESOLVED_float];
function from_hstring (
hstring : STRING; -- hex string
constant exponent_width : NATURAL := float_exponent_width;
constant fraction_width : NATURAL := float_fraction_width)
return UNRESOLVED_float;
alias from_hex_string is from_hstring [STRING, NATURAL, NATURAL
return UNRESOLVED_float];
function from_string (
bstring : STRING; -- binary string
size_res : UNRESOLVED_float) -- used for sizing only
return UNRESOLVED_float;
alias from_bstring is from_string [STRING, UNRESOLVED_float
return UNRESOLVED_float];
alias from_binary_string is from_string [STRING, UNRESOLVED_float
return UNRESOLVED_float];
function from_ostring (
ostring : STRING; -- Octal string
size_res : UNRESOLVED_float) -- used for sizing only
return UNRESOLVED_float;
alias from_octal_string is from_ostring [STRING, UNRESOLVED_float
return UNRESOLVED_float];
function from_hstring (
hstring : STRING; -- hex string
size_res : UNRESOLVED_float) -- used for sizing only
return UNRESOLVED_float;
alias from_hex_string is from_hstring [STRING, UNRESOLVED_float
return UNRESOLVED_float];
end package float_generic_pkg;
| gpl-2.0 | 9e1c631b0e17d4ad6baeda9609c2bdac | 0.627452 | 4.414152 | false | false | false | false |
emogenet/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc449.vhd | 4 | 5,080 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc449.vhd,v 1.2 2001-10-26 16:29:54 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY model IS
PORT
(
F1: OUT integer := 3;
F2: INOUT integer := 3;
F3: IN integer
);
END model;
architecture model of model is
begin
process
begin
wait for 1 ns;
assert F3= 3
report"wrong initialization of F3 through type conversion" severity failure;
assert F2 = 3
report"wrong initialization of F2 through type conversion" severity failure;
wait;
end process;
end;
ENTITY c03s02b01x01p19n01i00449ent IS
END c03s02b01x01p19n01i00449ent;
ARCHITECTURE c03s02b01x01p19n01i00449arch OF c03s02b01x01p19n01i00449ent IS
type boolean_vector is array (natural range <>) of boolean;
type severity_level_vector is array (natural range <>) of severity_level;
type integer_vector is array (natural range <>) of integer;
type real_vector is array (natural range <>) of real;
type time_vector is array (natural range <>) of time;
type natural_vector is array (natural range <>) of natural;
type positive_vector is array (natural range <>) of positive;
subtype boolean_vector_st is boolean_vector(0 to 15);
subtype severity_level_vector_st is severity_level_vector(0 to 15);
subtype integer_vector_st is integer_vector(0 to 15);
subtype real_vector_st is real_vector(0 to 15);
subtype time_vector_st is time_vector(0 to 15);
subtype natural_vector_st is natural_vector(0 to 15);
subtype positive_vector_st is positive_vector(0 to 15);
type record_array_st is record
a:boolean_vector_st;
b:severity_level_vector_st;
c:integer_vector_st;
d:real_vector_st;
e:time_vector_st;
f:natural_vector_st;
g:positive_vector_st;
end record;
constant C1 : boolean := true;
constant C2 : bit := '1';
constant C3 : character := 's';
constant C4 : severity_level := note;
constant C5 : integer := 3;
constant C6 : real := 3.0;
constant C7 : time := 3 ns;
constant C8 : natural := 1;
constant C9 : positive := 1;
constant C70 : boolean_vector_st :=(others => C1);
constant C71 : severity_level_vector_st :=(others => C4);
constant C72 : integer_vector_st :=(others => C5);
constant C73 : real_vector_st :=(others => C6);
constant C74 : time_vector_st :=(others => C7);
constant C75 : natural_vector_st :=(others => C8);
constant C76 : positive_vector_st :=(others => C9);
constant C77 : record_array_st := (C70,C71,C72,C73,C74,C75,C76);
function complex_scalar(s : record_array_st) return integer is
begin
return 3;
end complex_scalar;
function scalar_complex(s : integer) return record_array_st is
begin
return C77;
end scalar_complex;
component model1
PORT
(
F1: OUT integer;
F2: INOUT integer;
F3: IN integer
);
end component;
for T1 : model1 use entity work.model(model);
signal S1 : record_array_st;
signal S2 : record_array_st;
signal S3 : record_array_st := C77;
BEGIN
T1: model1
port map (
scalar_complex(F1) => S1,
scalar_complex(F2) => complex_scalar(S2),
F3 => complex_scalar(S3)
);
TESTING: PROCESS
BEGIN
wait for 1 ns;
assert NOT((S1 = C77) and (S2 = C77))
report "***PASSED TEST: c03s02b01x01p19n01i00449"
severity NOTE;
assert ((S1 = C77) and (S2 = C77))
report "***FAILED TEST: c03s02b01x01p19n01i00449 - For an interface object of mode out, buffer, inout, or linkage, if the formal part includes a type conversion function, then the parameter subtype of that function must be a constrained array subtype."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s02b01x01p19n01i00449arch;
| gpl-2.0 | f6bb43b9811ac6955f186b32d35e4777 | 0.625984 | 3.649425 | false | false | false | false |
pmh92/Proyecto-OFDM | test/PRBS_tb.vhd | 1 | 1,211 | LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY prbs_tb IS
END prbs_tb;
ARCHITECTURE behavior OF prbs_tb IS
-- Component Declaration
COMPONENT PRBS
PORT ( clk : in STD_LOGIC;
rst : in STD_LOGIC;
enable : in STD_LOGIC;
output : out STD_LOGIC);
END COMPONENT;
SIGNAL clk : std_logic;
SIGNAL rst : std_logic;
SIGNAL enable : std_logic;
SIGNAL output : STD_LOGIC;
CONSTANT clk_period: TIME := 10 ns;
BEGIN
-- Component Instantiation
uut: PRBS PORT MAP(
clk => clk,
rst => rst,
enable => enable,
output => output
);
-- Generar los estimulos
stim_process : PROCESS
BEGIN
rst <= '1';
enable <= '0';
wait for 100 ns;
rst <= '0';
wait until rising_edge(clk);
FOR i IN 1 TO 25 LOOP
enable <= '1';
wait for clk_period;
enable <= '0';
wait for 3*clk_period;
END LOOP;
END PROCESS stim_process;
-- Generar el reloj
clk_process : PROCESS
BEGIN
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
END PROCESS clk_process;
END;
| gpl-2.0 | 25f1d72f33e6ffc8ed27b6b3e29cc5db | 0.538398 | 3.636637 | false | false | false | false |
emogenet/ghdl | testsuite/vests/vhdl-93/ashenden/compliant/ch_10_bvat-b.vhd | 4 | 31,770 |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_10_bvat-b.vhd,v 1.3 2001-10-26 16:29:35 paw Exp $
-- $Revision: 1.3 $
--
-- ---------------------------------------------------------------------
library bv_utilities;
use std.textio.all, bv_utilities.bv_arithmetic.all;
architecture bench of bv_test is
begin
process is
variable L : line;
variable byte : bit_vector(0 to 7);
variable word : bit_vector(1 to 32);
variable half_byte : bit_vector(1 to 4);
variable overflow, div_by_zero, result : boolean;
begin
wait for 1 ns;
----------------------------------------------------------------
----------------------------------------------------------------
-- test bit_vector to numeric conversions
----------------------------------------------------------------
----------------------------------------------------------------
write(L, string'("Testing bv_to_natural:"));
writeline(output, L);
write(L, string'(" bv_to_natural(X""02"") = "));
write(L, bv_to_natural(X"02"));
writeline(output, L);
assert bv_to_natural(X"02") = 2;
write(L, string'(" bv_to_natural(X""FE"") = "));
write(L, bv_to_natural(X"FE"));
writeline(output, L);
assert bv_to_natural(X"FE") = 254;
----------------------------------------------------------------
write(L, string'("Testing natural_to_bv:"));
writeline(output, L);
write(L, string'(" natural_to_bv(2) = "));
write(L, natural_to_bv(2, 8));
writeline(output, L);
assert natural_to_bv(2, 8) = X"02";
write(L, string'(" natural_to_bv(254) = "));
write(L, natural_to_bv(254, 8));
writeline(output, L);
assert natural_to_bv(254, 8) = X"FE";
----------------------------------------------------------------
write(L, string'("Testing bv_to_integer:"));
writeline(output, L);
write(L, string'(" bv_to_integer(X""02"") = "));
write(L, bv_to_integer(X"02"));
writeline(output, L);
assert bv_to_integer(X"02") = 2;
write(L, string'(" bv_to_integer(X""FE"") = "));
write(L, bv_to_integer(X"FE"));
writeline(output, L);
assert bv_to_integer(X"FE") = -2;
----------------------------------------------------------------
write(L, string'("Testing integer_to_bv:"));
writeline(output, L);
write(L, string'(" integer_to_bv(2) = "));
write(L, integer_to_bv(2, 8));
writeline(output, L);
assert integer_to_bv(2, 8) = X"02";
write(L, string'(" integer_to_bv(-2) = "));
write(L, integer_to_bv(-2, 8));
writeline(output, L);
assert integer_to_bv(-2, 8) = X"FE";
----------------------------------------------------------------
----------------------------------------------------------------
-- Arithmetic operations
----------------------------------------------------------------
----------------------------------------------------------------
----------------------------------------------------------------
-- bv_add: Signed addition with overflow detection
----------------------------------------------------------------
writeline(output, L);
write(L, string'("Testing bv_add with overflow:"));
writeline(output, L);
write(L, string'(" 2+2 = "));
bv_add(X"02", X"02", byte, overflow);
write(L, byte);
write(L, string'(", overflow = ")); write(L, overflow);
writeline(output, L);
assert byte = X"04" and not overflow;
write(L, string'(" 2+(-3) = "));
bv_add(X"02", X"FD", byte, overflow);
write(L, byte);
write(L, string'(", overflow = ")); write(L, overflow);
writeline(output, L);
assert byte = X"FF" and not overflow;
write(L, string'(" 64+64 = "));
bv_add(X"40", X"40", byte, overflow);
write(L, byte);
write(L, string'(", overflow = ")); write(L, overflow);
writeline(output, L);
assert byte = X"80" and overflow;
write(L, string'(" -64+(-64) = "));
bv_add(X"C0", X"C0", byte, overflow);
write(L, byte);
write(L, string'(", overflow = ")); write(L, overflow);
writeline(output, L);
assert byte = X"80" and not overflow;
----------------------------------------------------------------
-- "+": Signed addition without overflow detection
----------------------------------------------------------------
writeline(output, L);
write(L, string'("Testing ""+"" without overflow:"));
writeline(output, L);
write(L, string'(" 2+2 = "));
byte := X"02" + X"02";
write(L, byte);
writeline(output, L);
assert byte = X"04";
write(L, string'(" 2+(-3) = "));
byte := X"02" + X"FD";
write(L, byte);
writeline(output, L);
assert byte = X"FF";
write(L, string'(" 64+64 = "));
byte := X"40" + X"40";
write(L, byte);
writeline(output, L);
assert byte = X"80";
write(L, string'(" -64+(-64) = "));
byte := X"C0" + X"C0";
write(L, byte);
writeline(output, L);
assert byte = X"80";
----------------------------------------------------------------
-- bv_sub: Signed subtraction with overflow detection
----------------------------------------------------------------
writeline(output, L);
write(L, string'("Testing bv_sub with overflow:"));
writeline(output, L);
write(L, string'(" 2-2 = "));
bv_sub(X"02", X"02", byte, overflow);
write(L, byte);
write(L, string'(", overflow = ")); write(L, overflow);
writeline(output, L);
assert byte = X"00" and not overflow;
write(L, string'(" 2-(-3) = "));
bv_sub(X"02", X"FD", byte, overflow);
write(L, byte);
write(L, string'(", overflow = ")); write(L, overflow);
writeline(output, L);
assert byte = X"05" and not overflow;
write(L, string'(" 64-(-64) = "));
bv_sub(X"40", X"C0", byte, overflow);
write(L, byte);
write(L, string'(", overflow = ")); write(L, overflow);
writeline(output, L);
assert byte = X"80" and overflow;
write(L, string'(" -64-64 = "));
bv_sub(X"C0", X"40", byte, overflow);
write(L, byte);
write(L, string'(", overflow = ")); write(L, overflow);
writeline(output, L);
assert byte = X"80" and not overflow;
----------------------------------------------------------------
-- "-": Signed subtraction without overflow detection
----------------------------------------------------------------
writeline(output, L);
write(L, string'("Testing ""-"" without overflow:"));
writeline(output, L);
write(L, string'(" 2-2 = "));
byte := X"02" - X"02";
write(L, byte);
writeline(output, L);
assert byte = X"00";
write(L, string'(" 2-(-3) = "));
byte := X"02" - X"FD";
write(L, byte);
writeline(output, L);
assert byte = X"05";
write(L, string'(" 64-(-64) = "));
byte := X"40" - X"C0";
write(L, byte);
writeline(output, L);
assert byte = X"80";
write(L, string'(" -64-64 = "));
byte := X"C0" - X"40";
write(L, byte);
writeline(output, L);
assert byte = X"80";
----------------------------------------------------------------
-- bv_addu: Unsigned addition with overflow detection
----------------------------------------------------------------
writeline(output, L);
write(L, string'("Testing bv_addu with overflow:"));
writeline(output, L);
write(L, string'(" 2+2 = "));
bv_addu(X"02", X"02", byte, overflow);
write(L, byte);
write(L, string'(", overflow = ")); write(L, overflow);
writeline(output, L);
assert byte = X"04" and not overflow;
write(L, string'(" 64+64 = "));
bv_addu(X"40", X"40", byte, overflow);
write(L, byte);
write(L, string'(", overflow = ")); write(L, overflow);
writeline(output, L);
assert byte = X"80" and not overflow;
write(L, string'(" 128+128 = "));
bv_addu(X"80", X"80", byte, overflow);
write(L, byte);
write(L, string'(", overflow = ")); write(L, overflow);
writeline(output, L);
assert byte = X"00" and overflow;
----------------------------------------------------------------
-- bv_addu: Unsigned addition without overflow detection
----------------------------------------------------------------
writeline(output, L);
write(L, string'("Testing bv_addu without overflow:"));
writeline(output, L);
write(L, string'(" 2+2 = "));
byte := bv_addu(X"02", X"02");
write(L, byte);
writeline(output, L);
assert byte = X"04";
write(L, string'(" 64+64 = "));
byte := bv_addu(X"40", X"40");
write(L, byte);
writeline(output, L);
assert byte = X"80";
write(L, string'(" 128+128 = "));
byte := bv_addu(X"80", X"80");
write(L, byte);
writeline(output, L);
assert byte = X"00";
----------------------------------------------------------------
-- bv_subu: Unsigned subtraction with overflow detection
----------------------------------------------------------------
writeline(output, L);
write(L, string'("Testing bv_subu with overflow:"));
writeline(output, L);
write(L, string'(" 3-2 = "));
bv_subu(X"03", X"02", byte, overflow);
write(L, byte);
write(L, string'(", overflow = ")); write(L, overflow);
writeline(output, L);
assert byte = X"01" and not overflow;
write(L, string'(" 64-64 = "));
bv_subu(X"40", X"40", byte, overflow);
write(L, byte);
write(L, string'(", overflow = ")); write(L, overflow);
writeline(output, L);
assert byte = X"00" and not overflow;
write(L, string'(" 64-128 = "));
bv_subu(X"40", X"80", byte, overflow);
write(L, byte);
write(L, string'(", overflow = ")); write(L, overflow);
writeline(output, L);
assert byte = X"C0" and overflow;
----------------------------------------------------------------
-- bv_subu: Unsigned subtraction without overflow detection
----------------------------------------------------------------
writeline(output, L);
write(L, string'("Testing bv_subu without overflow:"));
writeline(output, L);
write(L, string'(" 3-2 = "));
byte := bv_subu(X"03", X"02");
write(L, byte);
writeline(output, L);
assert byte = X"01";
write(L, string'(" 64-64 = "));
byte := bv_subu(X"40", X"40");
write(L, byte);
writeline(output, L);
assert byte = X"00";
write(L, string'(" 64-128 = "));
byte := bv_subu(X"40", X"80");
write(L, byte);
writeline(output, L);
assert byte = X"C0";
----------------------------------------------------------------
-- bv_neg: Signed negation with overflow detection
----------------------------------------------------------------
writeline(output, L);
write(L, string'("Testing bv_neg with overflow:"));
writeline(output, L);
write(L, string'(" -(3) = "));
bv_neg(X"03", byte, overflow);
write(L, byte);
write(L, string'(", overflow = ")); write(L, overflow);
writeline(output, L);
assert byte = X"FD" and not overflow;
write(L, string'(" -(-3) = "));
bv_neg(X"FD", byte, overflow);
write(L, byte);
write(L, string'(", overflow = ")); write(L, overflow);
writeline(output, L);
assert byte = X"03" and not overflow;
write(L, string'(" -(127) = "));
bv_neg(X"7F", byte, overflow);
write(L, byte);
write(L, string'(", overflow = ")); write(L, overflow);
writeline(output, L);
assert byte = X"81" and not overflow;
write(L, string'(" -(-128) = "));
bv_neg(X"80", byte, overflow);
write(L, byte);
write(L, string'(", overflow = ")); write(L, overflow);
writeline(output, L);
assert byte = X"80" and overflow;
----------------------------------------------------------------
-- "-": Signed negation without overflow detection
----------------------------------------------------------------
writeline(output, L);
write(L, string'("Testing ""-"" without overflow:"));
writeline(output, L);
write(L, string'(" -(3) = "));
byte := - X"03";
write(L, byte);
writeline(output, L);
assert byte = X"FD";
write(L, string'(" -(-3) = "));
byte := - X"FD";
write(L, byte);
writeline(output, L);
assert byte = X"03";
write(L, string'(" -(127) = "));
byte := - X"7F";
write(L, byte);
writeline(output, L);
assert byte = X"81";
write(L, string'(" -(-128) = "));
byte := - X"80";
write(L, byte);
writeline(output, L);
assert byte = X"80";
----------------------------------------------------------------
-- bv_mult: Signed multiplication with overflow detection
----------------------------------------------------------------
writeline(output, L);
write(L, string'("Testing bv_mult with overflow:"));
writeline(output, L);
write(L, string'(" 5*(-3) = "));
bv_mult(X"05", X"FD", byte, overflow);
write(L, byte);
write(L, string'(", overflow = ")); write(L, overflow);
writeline(output, L);
assert byte = X"F1" and not overflow;
write(L, string'(" (-5)*(-3) = "));
bv_mult(X"FB", X"FD", byte, overflow);
write(L, byte);
write(L, string'(", overflow = ")); write(L, overflow);
writeline(output, L);
assert byte = X"0F" and not overflow;
write(L, string'(" 16*8 = "));
bv_mult(X"10", X"08", byte, overflow);
write(L, byte);
write(L, string'(", overflow = ")); write(L, overflow);
writeline(output, L);
assert byte = X"80" and overflow;
write(L, string'(" 16*16 = "));
bv_mult(X"10", X"10", byte, overflow);
write(L, byte);
write(L, string'(", overflow = ")); write(L, overflow);
writeline(output, L);
assert byte = X"00" and overflow;
write(L, string'(" 16*(-8) = "));
bv_mult(X"10", X"F8", byte, overflow);
write(L, byte);
write(L, string'(", overflow = ")); write(L, overflow);
writeline(output, L);
assert byte = X"80" and not overflow;
write(L, string'(" 16*(-16) = "));
bv_mult(X"10", X"F0", byte, overflow);
write(L, byte);
write(L, string'(", overflow = ")); write(L, overflow);
writeline(output, L);
assert byte = X"00" and overflow;
----------------------------------------------------------------
-- "*": Signed multiplication without overflow detection
----------------------------------------------------------------
writeline(output, L);
write(L, string'("Testing ""*"" without overflow:"));
writeline(output, L);
write(L, string'(" 5*(-3) = "));
byte := X"05" * X"FD";
write(L, byte);
writeline(output, L);
assert byte = X"F1";
write(L, string'(" (-5)*(-3) = "));
byte := X"FB" * X"FD";
write(L, byte);
writeline(output, L);
assert byte = X"0F";
write(L, string'(" 16*8 = "));
byte := X"10" * X"08";
write(L, byte);
writeline(output, L);
assert byte = X"80";
write(L, string'(" 16*16 = "));
byte := X"10" * X"10";
write(L, byte);
writeline(output, L);
assert byte = X"00";
write(L, string'(" 16*(-8) = "));
byte := X"10" * X"F8";
write(L, byte);
writeline(output, L);
assert byte = X"80";
write(L, string'(" 16*(-16) = "));
byte := X"10" * X"F0";
write(L, byte);
writeline(output, L);
assert byte = X"00";
----------------------------------------------------------------
-- bv_multu: Unsigned multiplication with overflow detection
----------------------------------------------------------------
writeline(output, L);
write(L, string'("Testing bv_multu with overflow:"));
writeline(output, L);
write(L, string'(" 5*7 = "));
bv_multu(X"05", X"07", byte, overflow);
write(L, byte);
write(L, string'(", overflow = ")); write(L, overflow);
writeline(output, L);
assert byte = X"23" and not overflow;
write(L, string'(" 16*8 = "));
bv_multu(X"10", X"08", byte, overflow);
write(L, byte);
write(L, string'(", overflow = ")); write(L, overflow);
writeline(output, L);
assert byte = X"80" and not overflow;
write(L, string'(" 16*16 = "));
bv_multu(X"10", X"10", byte, overflow);
write(L, byte);
write(L, string'(", overflow = ")); write(L, overflow);
writeline(output, L);
assert byte = X"00" and overflow;
----------------------------------------------------------------
-- bv_multu: Unsigned multiplication without overflow detection
----------------------------------------------------------------
writeline(output, L);
write(L, string'("Testing bv_multu without overflow:"));
writeline(output, L);
write(L, string'(" 5*7 = "));
byte := bv_multu(X"05", X"07");
write(L, byte);
writeline(output, L);
assert byte = X"23";
write(L, string'(" 16*8 = "));
byte := bv_multu(X"10", X"08");
write(L, byte);
writeline(output, L);
assert byte = X"80";
write(L, string'(" 16*16 = "));
byte := bv_multu(X"10", X"10");
write(L, byte);
writeline(output, L);
assert byte = X"00";
----------------------------------------------------------------
-- bv_div: Signed division with divide by zero and overflow detection
----------------------------------------------------------------
writeline(output, L);
write(L, string'("Testing bv_div with flags:"));
writeline(output, L);
write(L, string'(" 7/2 = "));
bv_div(X"07", X"02", byte, div_by_zero, overflow);
write(L, byte);
write(L, string'(", div_by_zero = ")); write(L, div_by_zero);
write(L, string'(", overflow = ")); write(L, overflow);
writeline(output, L);
assert byte = X"03" and not div_by_zero and not overflow;
write(L, string'(" -7/2 = "));
bv_div(X"F9", X"02", byte, div_by_zero, overflow);
write(L, byte);
write(L, string'(", div_by_zero = ")); write(L, div_by_zero);
write(L, string'(", overflow = ")); write(L, overflow);
writeline(output, L);
assert byte = X"FD" and not div_by_zero and not overflow;
write(L, string'(" 7/-2 = "));
bv_div(X"07", X"FE", byte, div_by_zero, overflow);
write(L, byte);
write(L, string'(", div_by_zero = ")); write(L, div_by_zero);
write(L, string'(", overflow = ")); write(L, overflow);
writeline(output, L);
assert byte = X"FD" and not div_by_zero and not overflow;
write(L, string'(" -7/-2 = "));
bv_div(X"F9", X"FE", byte, div_by_zero, overflow);
write(L, byte);
write(L, string'(", div_by_zero = ")); write(L, div_by_zero);
write(L, string'(", overflow = ")); write(L, overflow);
writeline(output, L);
assert byte = X"03" and not div_by_zero and not overflow;
write(L, string'(" -128/1 = "));
bv_div(X"80", X"01", byte, div_by_zero, overflow);
write(L, byte);
write(L, string'(", div_by_zero = ")); write(L, div_by_zero);
write(L, string'(", overflow = ")); write(L, overflow);
writeline(output, L);
assert byte = X"80" and not div_by_zero and not overflow;
write(L, string'(" -128/-1 = "));
bv_div(X"80", X"FF", byte, div_by_zero, overflow);
write(L, byte);
write(L, string'(", div_by_zero = ")); write(L, div_by_zero);
write(L, string'(", overflow = ")); write(L, overflow);
writeline(output, L);
assert byte = X"80" and not div_by_zero and overflow;
write(L, string'(" -16/0 = "));
bv_div(X"F0", X"00", byte, div_by_zero, overflow);
write(L, byte);
write(L, string'(", div_by_zero = ")); write(L, div_by_zero);
write(L, string'(", overflow = ")); write(L, overflow);
writeline(output, L);
assert byte = X"00" and div_by_zero and not overflow;
----------------------------------------------------------------
-- "/": Signed division without divide by zero and overflow detection
----------------------------------------------------------------
writeline(output, L);
write(L, string'("Testing ""/"" without flags:"));
writeline(output, L);
write(L, string'(" 7/2 = "));
byte := X"07" / X"02";
write(L, byte);
writeline(output, L);
assert byte = X"03";
write(L, string'(" -7/2 = "));
byte := X"F9" / X"02";
write(L, byte);
writeline(output, L);
assert byte = X"FD";
write(L, string'(" 7/-2 = "));
byte := X"07" / X"FE";
write(L, byte);
writeline(output, L);
assert byte = X"FD";
write(L, string'(" -7/-2 = "));
byte := X"F9" / X"FE";
write(L, byte);
writeline(output, L);
assert byte = X"03";
write(L, string'(" -128/1 = "));
byte := X"80" / X"01";
write(L, byte);
writeline(output, L);
assert byte = X"80";
write(L, string'(" -128/-1 = "));
byte := X"80" / X"FF";
write(L, byte);
writeline(output, L);
assert byte = X"80";
write(L, string'(" -16/0 = "));
byte := X"F0" / X"00";
write(L, byte);
writeline(output, L);
assert byte = X"00";
----------------------------------------------------------------
-- bv_divu: Unsigned division with divide by zero detection
----------------------------------------------------------------
writeline(output, L);
write(L, string'("Testing bv_divu with flag:"));
writeline(output, L);
write(L, string'(" 7/2 = "));
bv_divu(X"07", X"02", byte, div_by_zero);
write(L, byte);
write(L, string'(", div_by_zero = ")); write(L, div_by_zero);
writeline(output, L);
assert byte = X"03" and not div_by_zero;
write(L, string'(" 14/7 = "));
bv_divu(X"0E", X"07", byte, div_by_zero);
write(L, byte);
write(L, string'(", div_by_zero = ")); write(L, div_by_zero);
writeline(output, L);
assert byte = X"02" and not div_by_zero;
write(L, string'(" 16/1 = "));
bv_divu(X"10", X"01", byte, div_by_zero);
write(L, byte);
write(L, string'(", div_by_zero = ")); write(L, div_by_zero);
writeline(output, L);
assert byte = X"10" and not div_by_zero;
write(L, string'(" 16/0 = "));
bv_divu(X"10", X"00", byte, div_by_zero);
write(L, byte);
write(L, string'(", div_by_zero = ")); write(L, div_by_zero);
writeline(output, L);
assert byte = X"10" and div_by_zero;
write(L, string'(" 16/16 = "));
bv_divu(X"10", X"10", byte, div_by_zero);
write(L, byte);
write(L, string'(", div_by_zero = ")); write(L, div_by_zero);
writeline(output, L);
assert byte = X"01" and not div_by_zero;
write(L, string'(" 1/16 = "));
bv_divu(X"01", X"10", byte, div_by_zero);
write(L, byte);
write(L, string'(", div_by_zero = ")); write(L, div_by_zero);
writeline(output, L);
assert byte = X"00" and not div_by_zero;
write(L, string'(" 255/1 = "));
bv_divu(X"FF", X"01", byte, div_by_zero);
write(L, byte);
write(L, string'(", div_by_zero = ")); write(L, div_by_zero);
writeline(output, L);
assert byte = X"FF" and not div_by_zero;
----------------------------------------------------------------
-- bv_divu: Unsigned division without divide by zero detection
----------------------------------------------------------------
writeline(output, L);
write(L, string'("Testing bv_divu without flag:"));
writeline(output, L);
write(L, string'(" 7/2 = "));
byte := bv_divu(X"07", X"02");
write(L, byte);
writeline(output, L);
assert byte = X"03";
write(L, string'(" 14/7 = "));
byte := bv_divu(X"0E", X"07");
write(L, byte);
writeline(output, L);
assert byte = X"02";
write(L, string'(" 16/1 = "));
byte := bv_divu(X"10", X"01");
write(L, byte);
writeline(output, L);
assert byte = X"10";
write(L, string'(" 16/0 = "));
byte := bv_divu(X"10", X"00");
write(L, byte);
writeline(output, L);
assert byte = X"00";
write(L, string'(" 16/16 = "));
byte := bv_divu(X"10", X"10");
write(L, byte);
writeline(output, L);
assert byte = X"01";
write(L, string'(" 1/16 = "));
byte := bv_divu(X"01", X"10");
write(L, byte);
writeline(output, L);
assert byte = X"00";
write(L, string'(" 255/1 = "));
byte := bv_divu(X"FF", X"01");
write(L, byte);
writeline(output, L);
assert byte = X"FF";
----------------------------------------------------------------
----------------------------------------------------------------
-- Arithmetic comparison operators.
----------------------------------------------------------------
----------------------------------------------------------------
----------------------------------------------------------------
-- bv_lt: Signed less than comparison
----------------------------------------------------------------
writeline(output, L);
write(L, string'("Testing bv_lt:"));
writeline(output, L);
write(L, string'(" 2 < 2 = "));
result := bv_lt(X"02", X"02");
write(L, result);
writeline(output, L);
assert NOT result;
write(L, string'(" 2 < 3 = "));
result := bv_lt(X"02", X"03");
write(L, result);
writeline(output, L);
assert result;
write(L, string'(" -2 < 2 = "));
result := bv_lt(X"FE", X"02");
write(L, result);
writeline(output, L);
assert result;
write(L, string'(" 2 < -3 = "));
result := bv_lt(X"02", X"FD");
write(L, result);
writeline(output, L);
assert NOT result;
----------------------------------------------------------------
-- bv_le: Signed less than or equal comparison
----------------------------------------------------------------
writeline(output, L);
write(L, string'("Testing bv_le:"));
writeline(output, L);
write(L, string'(" 2 <= 2 = "));
result := bv_le(X"02", X"02");
write(L, result);
writeline(output, L);
assert result;
write(L, string'(" 2 <= 3 = "));
result := bv_le(X"02", X"03");
write(L, result);
writeline(output, L);
assert result;
write(L, string'(" -2 <= 2 = "));
result := bv_le(X"FE", X"02");
write(L, result);
writeline(output, L);
assert result;
write(L, string'(" 2 <= -3 = "));
result := bv_le(X"02", X"FD");
write(L, result);
writeline(output, L);
assert NOT result;
----------------------------------------------------------------
-- bv_gt: Signed greater than comparison
----------------------------------------------------------------
writeline(output, L);
write(L, string'("Testing bv_gt:"));
writeline(output, L);
write(L, string'(" 2 > 2 = "));
result := bv_gt(X"02", X"02");
write(L, result);
writeline(output, L);
assert NOT result;
write(L, string'(" 3 > 2 = "));
result := bv_gt(X"03", X"02");
write(L, result);
writeline(output, L);
assert result;
write(L, string'(" 2 > -2 = "));
result := bv_gt(X"02", X"FE");
write(L, result);
writeline(output, L);
assert result;
write(L, string'(" -3 > 2 = "));
result := bv_gt(X"FD", X"02");
write(L, result);
writeline(output, L);
assert NOT result;
----------------------------------------------------------------
-- bv_ge: Signed greater than or equal comparison
----------------------------------------------------------------
writeline(output, L);
write(L, string'("Testing bv_ge:"));
writeline(output, L);
write(L, string'(" 2 >= 2 = "));
result := bv_ge(X"02", X"02");
write(L, result);
writeline(output, L);
assert result;
write(L, string'(" 3 >= 2 = "));
result := bv_ge(X"03", X"02");
write(L, result);
writeline(output, L);
assert result;
write(L, string'(" 2 >= -2 = "));
result := bv_ge(X"02", X"FE");
write(L, result);
writeline(output, L);
assert result;
write(L, string'(" -3 >= 2 = "));
result := bv_ge(X"FD", X"02");
write(L, result);
writeline(output, L);
assert NOT result;
----------------------------------------------------------------
----------------------------------------------------------------
-- Extension operators - convert a bit vector to a longer one
----------------------------------------------------------------
----------------------------------------------------------------
----------------------------------------------------------------
-- bv_sext: Sign extension
----------------------------------------------------------------
writeline(output, L);
write(L, string'("Testing bv_sext:"));
writeline(output, L);
write(L, string'(" sext(X""02"", 32) = "));
word := bv_sext(X"02", 32);
write(L, word);
writeline(output, L);
assert word = X"00000002";
write(L, string'(" sext(X""FE"", 32) = "));
word := bv_sext(X"FE", 32);
write(L, word);
writeline(output, L);
assert word = X"FFFFFFFE";
write(L, string'(" sext(X""02"", 8) = "));
byte := bv_sext(X"02", 8);
write(L, byte);
writeline(output, L);
assert byte = X"02";
write(L, string'(" sext(X""FE"", 8) = "));
byte := bv_sext(X"FE", 8);
write(L, byte);
writeline(output, L);
assert byte = X"FE";
write(L, string'(" sext(X""02"", 4) = "));
half_byte := bv_sext(X"02", 4);
write(L, half_byte);
writeline(output, L);
assert half_byte = X"2";
write(L, string'(" sext(X""FE"", 4) = "));
half_byte := bv_sext(X"FE", 4);
write(L, half_byte);
writeline(output, L);
assert half_byte = X"E";
----------------------------------------------------------------
-- bv_zext" Zero extension
----------------------------------------------------------------
writeline(output, L);
write(L, string'("Testing bv_zext:"));
writeline(output, L);
write(L, string'(" zext(X""02"", 32) = "));
word := bv_zext(X"02", 32);
write(L, word);
writeline(output, L);
assert word = X"00000002";
write(L, string'(" zext(X""FE"", 32) = "));
word := bv_zext(X"FE", 32);
write(L, word);
writeline(output, L);
assert word = X"000000FE";
write(L, string'(" zext(X""02"", 8) = "));
byte := bv_zext(X"02", 8);
write(L, byte);
writeline(output, L);
assert byte = X"02";
write(L, string'(" zext(X""FE"", 8) = "));
byte := bv_zext(X"FE", 8);
write(L, byte);
writeline(output, L);
assert byte = X"FE";
write(L, string'(" zext(X""02"", 4) = "));
half_byte := bv_zext(X"02", 4);
write(L, half_byte);
writeline(output, L);
assert half_byte = X"2";
write(L, string'(" zext(X""FE"", 4) = "));
half_byte := bv_zext(X"FE", 4);
write(L, half_byte);
writeline(output, L);
assert half_byte = X"E";
wait;
end process;
end architecture bench;
| gpl-2.0 | 4a6841767b115448b23ef72a289f5203 | 0.465722 | 3.609817 | false | false | false | false |
makestuff/spi-master | vhdl/tb_msbfirst/spi_master_tb.vhdl | 1 | 5,405 | --
-- Copyright (C) 2011, 2013 Chris McClelland
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU Lesser General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU Lesser General Public License for more details.
--
-- You should have received a copy of the GNU Lesser General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_textio.all;
use std.textio.all;
use work.hex_util.all;
entity spi_master_tb is
end entity;
architecture behavioural of spi_master_tb is
-- Clocks, etc
signal sysClk : std_logic; -- main system clock
signal dispClk : std_logic; -- display version of sysClk, which transitions 4ns before it
signal reset : std_logic;
-- Client interface
signal sendData : std_logic_vector(7 downto 0); -- data to send
signal sendValid : std_logic;
signal sendReady : std_logic;
signal recvData : std_logic_vector(7 downto 0); -- data we receive
signal recvValid : std_logic;
signal recvReady : std_logic;
-- External interface
signal spiClk : std_logic; -- serial clock
signal spiDataOut : std_logic; -- send serial data
signal spiDataIn : std_logic; -- receive serial data
begin
-- Instantiate the unit under test
uut: entity work.spi_master
generic map(
--FAST_COUNT => "000011"
FAST_COUNT => "000000",
BIT_ORDER => '1'
)
port map(
reset_in => reset,
clk_in => sysClk,
turbo_in => '1',
suppress_in => '0',
sendData_in => sendData,
sendValid_in => sendValid,
sendReady_out => sendReady,
recvData_out => recvData,
recvValid_out => recvValid,
recvReady_in => recvReady,
spiClk_out => spiClk,
spiData_out => spiDataOut,
spiData_in => spiDataIn
);
-- Drive the clocks. In simulation, sysClk lags 4ns behind dispClk, to give a visual hold time
-- for signals in GTKWave.
process
begin
sysClk <= '0';
dispClk <= '0';
wait for 16 ns;
loop
dispClk <= not(dispClk); -- first dispClk transitions
wait for 4 ns;
sysClk <= not(sysClk); -- then sysClk transitions, 4ns later
wait for 6 ns;
end loop;
end process;
-- Deassert the synchronous reset a couple of cycles after startup.
--
process
begin
reset <= '1';
wait until rising_edge(sysClk);
wait until rising_edge(sysClk);
reset <= '0';
wait;
end process;
-- Drive the unit under test. Read stimulus from stimulus.sim and write results to results.sim
process
variable inLine : line;
variable outLine : line;
file inFile : text open read_mode is "stimulus/send.sim";
file outFile : text open write_mode is "results/recv.sim";
begin
sendData <= (others => 'X');
sendValid <= '0';
wait until falling_edge(reset);
wait until rising_edge(sysClk);
while ( not endfile(inFile) ) loop
readline(inFile, inLine);
while ( inLine.all'length = 0 or inLine.all(1) = '#' or inLine.all(1) = ht or inLine.all(1) = ' ' ) loop
readline(inFile, inLine);
end loop;
sendData <= to_4(inLine.all(1)) & to_4(inLine.all(2));
sendValid <= to_1(inLine.all(4));
recvReady <= to_1(inLine.all(6));
wait for 10 ns;
write(outLine, from_4(sendData(7 downto 4)) & from_4(sendData(3 downto 0)));
write(outLine, ' ');
write(outLine, sendValid);
write(outLine, ' ');
write(outLine, sendReady);
writeline(outFile, outLine);
wait for 10 ns;
end loop;
sendData <= (others => 'X');
sendValid <= '0';
wait;
end process;
-- Mock the serial interface's interlocutor: send from s/recv.sim and receive into r/send.sim
process
variable inLine, outLine : line;
variable inData, outData : std_logic_vector(7 downto 0);
file inFile : text open read_mode is "stimulus/recv.sim";
file outFile : text open write_mode is "results/send.sim";
begin
spiDataIn <= 'X';
loop
exit when endfile(inFile);
readline(inFile, inLine);
read(inLine, inData);
wait until spiClk = '0';
spiDataIn <= inData(7);
wait until spiClk = '1';
outData(7) := spiDataOut;
wait until spiClk = '0';
spiDataIn <= inData(6);
wait until spiClk = '1';
outData(6) := spiDataOut;
wait until spiClk = '0';
spiDataIn <= inData(5);
wait until spiClk = '1';
outData(5) := spiDataOut;
wait until spiClk = '0';
spiDataIn <= inData(4);
wait until spiClk = '1';
outData(4) := spiDataOut;
wait until spiClk = '0';
spiDataIn <= inData(3);
wait until spiClk = '1';
outData(3) := spiDataOut;
wait until spiClk = '0';
spiDataIn <= inData(2);
wait until spiClk = '1';
outData(2) := spiDataOut;
wait until spiClk = '0';
spiDataIn <= inData(1);
wait until spiClk = '1';
outData(1) := spiDataOut;
wait until spiClk = '0';
spiDataIn <= inData(0);
wait until spiClk = '1';
outData(0) := spiDataOut;
write(outLine, outData);
writeline(outFile, outLine);
end loop;
wait for 10 ns;
spiDataIn <= 'X';
wait;
end process;
end architecture;
| gpl-3.0 | 4eeca7ad5af756a43e9c0fda5a181b29 | 0.655319 | 3.291717 | false | false | false | false |
emogenet/ghdl | libraries/ieee2008/numeric_std_unsigned.vhdl | 4 | 26,652 | -- --------------------------------------------------------------------
--
-- Copyright © 2008 by IEEE. All rights reserved.
--
-- This source file is an essential part of IEEE Std 1076-2008,
-- IEEE Standard VHDL Language Reference Manual. This source file may not be
-- copied, sold, or included with software that is sold without written
-- permission from the IEEE Standards Department. This source file may be
-- copied for individual use between licensed users. This source file is
-- provided on an AS IS basis. The IEEE disclaims ANY WARRANTY EXPRESS OR
-- IMPLIED INCLUDING ANY WARRANTY OF MERCHANTABILITY AND FITNESS FOR USE
-- FOR A PARTICULAR PURPOSE. The user of the source file shall indemnify
-- and hold IEEE harmless from any damages or liability arising out of the
-- use thereof.
--
-- Title : Standard VHDL Synthesis Packages
-- : (NUMERIC_STD_UNSIGNED package declaration)
-- :
-- Library : This package shall be compiled into a library
-- : symbolically named IEEE.
-- :
-- Developers: Accellera VHDL-TC, and IEEE P1076 Working Group
-- :
-- Purpose : This package defines numeric types and arithmetic functions
-- : for use with synthesis tools. Values of type STD_ULOGIC_VECTOR
-- : are interpreted as unsigned numbers in vector form.
-- : The leftmost bit is treated as the most significant bit.
-- : This package contains overloaded arithmetic operators on
-- : the STD_ULOGIC_VECTOR type. The package also contains
-- : useful type conversions functions, clock detection
-- : functions, and other utility functions.
-- :
-- : If any argument to a function is a null array, a null array
-- : is returned (exceptions, if any, are noted individually).
--
-- Note : This package may be modified to include additional data
-- : required by tools, but it must in no way change the
-- : external interfaces or simulation behavior of the
-- : description. It is permissible to add comments and/or
-- : attributes to the package declarations, but not to change
-- : or delete any original lines of the package declaration.
-- : The package body may be changed only in accordance with
-- : the terms of Clause 16 of this standard.
-- :
-- --------------------------------------------------------------------
-- $Revision: 1220 $
-- $Date: 2008-04-10 17:16:09 +0930 (Thu, 10 Apr 2008) $
-- --------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
package NUMERIC_STD_UNSIGNED is
constant CopyRightNotice : STRING :=
"Copyright 2008 IEEE. All rights reserved.";
-- Id: A.3
function "+" (L, R : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;
-- Result subtype: STD_ULOGIC_VECTOR(MAXIMUM(L'LENGTH, R'LENGTH)-1 downto 0).
-- Result: Adds two UNSIGNED vectors that may be of different lengths.
-- Id: A.3R
function "+"(L : STD_ULOGIC_VECTOR; R : STD_ULOGIC) return STD_ULOGIC_VECTOR;
-- Result subtype: STD_ULOGIC_VECTOR(L'LENGTH-1 downto 0)
-- Result: Similar to A.3 where R is a one bit STD_ULOGIC_VECTOR
-- Id: A.3L
function "+"(L : STD_ULOGIC; R : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;
-- Result subtype: STD_ULOGIC_VECTOR(R'LENGTH-1 downto 0)
-- Result: Similar to A.3 where L is a one bit UNSIGNED
-- Id: A.5
function "+" (L : STD_ULOGIC_VECTOR; R : NATURAL) return STD_ULOGIC_VECTOR;
-- Result subtype: STD_ULOGIC_VECTOR(L'LENGTH-1 downto 0).
-- Result: Adds an UNSIGNED vector, L, with a non-negative INTEGER, R.
-- Id: A.6
function "+" (L : NATURAL; R : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;
-- Result subtype: STD_ULOGIC_VECTOR(R'LENGTH-1 downto 0).
-- Result: Adds a non-negative INTEGER, L, with an UNSIGNED vector, R.
--============================================================================
-- Id: A.9
function "-" (L, R : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;
-- Result subtype: UNSIGNED(MAXIMUM(L'LENGTH, R'LENGTH)-1 downto 0).
-- Result: Subtracts two UNSIGNED vectors that may be of different lengths.
-- Id: A.9R
function "-"(L : STD_ULOGIC_VECTOR; R : STD_ULOGIC) return STD_ULOGIC_VECTOR;
-- Result subtype: STD_ULOGIC_VECTOR(L'LENGTH-1 downto 0)
-- Result: Similar to A.9 where R is a one bit UNSIGNED
-- Id: A.9L
function "-"(L : STD_ULOGIC; R : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;
-- Result subtype: STD_ULOGIC_VECTOR(R'LENGTH-1 downto 0)
-- Result: Similar to A.9 where L is a one bit UNSIGNED
-- Id: A.11
function "-" (L : STD_ULOGIC_VECTOR; R : NATURAL) return STD_ULOGIC_VECTOR;
-- Result subtype: STD_ULOGIC_VECTOR(L'LENGTH-1 downto 0).
-- Result: Subtracts a non-negative INTEGER, R, from an UNSIGNED vector, L.
-- Id: A.12
function "-" (L : NATURAL; R : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;
-- Result subtype: STD_ULOGIC_VECTOR(R'LENGTH-1 downto 0).
-- Result: Subtracts an UNSIGNED vector, R, from a non-negative INTEGER, L.
--============================================================================
-- Id: A.15
function "*" (L, R : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;
-- Result subtype: STD_ULOGIC_VECTOR((L'LENGTH+R'LENGTH-1) downto 0).
-- Result: Performs the multiplication operation on two UNSIGNED vectors
-- that may possibly be of different lengths.
-- Id: A.17
function "*" (L : STD_ULOGIC_VECTOR; R : NATURAL) return STD_ULOGIC_VECTOR;
-- Result subtype: STD_ULOGIC_VECTOR((L'LENGTH+L'LENGTH-1) downto 0).
-- Result: Multiplies an UNSIGNED vector, L, with a non-negative
-- INTEGER, R. R is converted to an UNSIGNED vector of
-- SIZE L'LENGTH before multiplication.
-- Id: A.18
function "*" (L : NATURAL; R : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;
-- Result subtype: STD_ULOGIC_VECTOR((R'LENGTH+R'LENGTH-1) downto 0).
-- Result: Multiplies an UNSIGNED vector, R, with a non-negative
-- INTEGER, L. L is converted to an UNSIGNED vector of
-- SIZE R'LENGTH before multiplication.
--============================================================================
--
-- NOTE: If second argument is zero for "/" operator, a severity level
-- of ERROR is issued.
-- Id: A.21
function "/" (L, R : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;
-- Result subtype: STD_ULOGIC_VECTOR(L'LENGTH-1 downto 0)
-- Result: Divides an UNSIGNED vector, L, by another UNSIGNED vector, R.
-- Id: A.23
function "/" (L : STD_ULOGIC_VECTOR; R : NATURAL) return STD_ULOGIC_VECTOR;
-- Result subtype: STD_ULOGIC_VECTOR(L'LENGTH-1 downto 0)
-- Result: Divides an UNSIGNED vector, L, by a non-negative INTEGER, R.
-- If NO_OF_BITS(R) > L'LENGTH, result is truncated to L'LENGTH.
-- Id: A.24
function "/" (L : NATURAL; R : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;
-- Result subtype: STD_ULOGIC_VECTOR(R'LENGTH-1 downto 0)
-- Result: Divides a non-negative INTEGER, L, by an UNSIGNED vector, R.
-- If NO_OF_BITS(L) > R'LENGTH, result is truncated to R'LENGTH.
--============================================================================
--
-- NOTE: If second argument is zero for "rem" operator, a severity level
-- of ERROR is issued.
-- Id: A.27
function "rem" (L, R : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;
-- Result subtype: STD_ULOGIC_VECTOR(R'LENGTH-1 downto 0)
-- Result: Computes "L rem R" where L and R are UNSIGNED vectors.
-- Id: A.29
function "rem" (L : STD_ULOGIC_VECTOR; R : NATURAL) return STD_ULOGIC_VECTOR;
-- Result subtype: STD_ULOGIC_VECTOR(L'LENGTH-1 downto 0)
-- Result: Computes "L rem R" where L is an UNSIGNED vector and R is a
-- non-negative INTEGER.
-- If NO_OF_BITS(R) > L'LENGTH, result is truncated to L'LENGTH.
-- Id: A.30
function "rem" (L : NATURAL; R : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;
-- Result subtype: STD_ULOGIC_VECTOR(R'LENGTH-1 downto 0)
-- Result: Computes "L rem R" where R is an UNSIGNED vector and L is a
-- non-negative INTEGER.
-- If NO_OF_BITS(L) > R'LENGTH, result is truncated to R'LENGTH.
--============================================================================
--
-- NOTE: If second argument is zero for "mod" operator, a severity level
-- of ERROR is issued.
-- Id: A.33
function "mod" (L, R : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;
-- Result subtype: STD_ULOGIC_VECTOR(R'LENGTH-1 downto 0)
-- Result: Computes "L mod R" where L and R are UNSIGNED vectors.
-- Id: A.35
function "mod" (L : STD_ULOGIC_VECTOR; R : NATURAL) return STD_ULOGIC_VECTOR;
-- Result subtype: STD_ULOGIC_VECTOR(L'LENGTH-1 downto 0)
-- Result: Computes "L mod R" where L is an UNSIGNED vector and R
-- is a non-negative INTEGER.
-- If NO_OF_BITS(R) > L'LENGTH, result is truncated to L'LENGTH.
-- Id: A.36
function "mod" (L : NATURAL; R : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;
-- Result subtype: STD_ULOGIC_VECTOR(R'LENGTH-1 downto 0)
-- Result: Computes "L mod R" where R is an UNSIGNED vector and L
-- is a non-negative INTEGER.
-- If NO_OF_BITS(L) > R'LENGTH, result is truncated to R'LENGTH.
--============================================================================
-- Id: A.39
function find_leftmost (ARG : STD_ULOGIC_VECTOR; Y : STD_ULOGIC) return INTEGER;
-- Result subtype: INTEGER
-- Result: Finds the leftmost occurrence of the value of Y in ARG.
-- Returns the index of the occurrence if it exists, or -1 otherwise.
-- Id: A.41
function find_rightmost (ARG : STD_ULOGIC_VECTOR; Y : STD_ULOGIC) return INTEGER;
-- Result subtype: INTEGER
-- Result: Finds the leftmost occurrence of the value of Y in ARG.
-- Returns the index of the occurrence if it exists, or -1 otherwise.
--============================================================================
-- Comparison Operators
--============================================================================
-- Id: C.1
function ">" (L, R : STD_ULOGIC_VECTOR) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L > R" where L and R are UNSIGNED vectors possibly
-- of different lengths.
-- Id: C.3
function ">" (L : NATURAL; R : STD_ULOGIC_VECTOR) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L > R" where L is a non-negative INTEGER and
-- R is an UNSIGNED vector.
-- Id: C.5
function ">" (L : STD_ULOGIC_VECTOR; R : NATURAL) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L > R" where L is an UNSIGNED vector and
-- R is a non-negative INTEGER.
--============================================================================
-- Id: C.7
function "<" (L, R : STD_ULOGIC_VECTOR) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L < R" where L and R are UNSIGNED vectors possibly
-- of different lengths.
-- Id: C.9
function "<" (L : NATURAL; R : STD_ULOGIC_VECTOR) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L < R" where L is a non-negative INTEGER and
-- R is an UNSIGNED vector.
-- Id: C.11
function "<" (L : STD_ULOGIC_VECTOR; R : NATURAL) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L < R" where L is an UNSIGNED vector and
-- R is a non-negative INTEGER.
--============================================================================
-- Id: C.13
function "<=" (L, R : STD_ULOGIC_VECTOR) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L <= R" where L and R are UNSIGNED vectors possibly
-- of different lengths.
-- Id: C.15
function "<=" (L : NATURAL; R : STD_ULOGIC_VECTOR) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L <= R" where L is a non-negative INTEGER and
-- R is an UNSIGNED vector.
-- Id: C.17
function "<=" (L : STD_ULOGIC_VECTOR; R : NATURAL) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L <= R" where L is an UNSIGNED vector and
-- R is a non-negative INTEGER.
--============================================================================
-- Id: C.19
function ">=" (L, R : STD_ULOGIC_VECTOR) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L >= R" where L and R are UNSIGNED vectors possibly
-- of different lengths.
-- Id: C.21
function ">=" (L : NATURAL; R : STD_ULOGIC_VECTOR) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L >= R" where L is a non-negative INTEGER and
-- R is an UNSIGNED vector.
-- Id: C.23
function ">=" (L : STD_ULOGIC_VECTOR; R : NATURAL) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L >= R" where L is an UNSIGNED vector and
-- R is a non-negative INTEGER.
--============================================================================
-- Id: C.25
function "=" (L, R : STD_ULOGIC_VECTOR) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L = R" where L and R are UNSIGNED vectors possibly
-- of different lengths.
-- Id: C.27
function "=" (L : NATURAL; R : STD_ULOGIC_VECTOR) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L = R" where L is a non-negative INTEGER and
-- R is an UNSIGNED vector.
-- Id: C.29
function "=" (L : STD_ULOGIC_VECTOR; R : NATURAL) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L = R" where L is an UNSIGNED vector and
-- R is a non-negative INTEGER.
--============================================================================
-- Id: C.31
function "/=" (L, R : STD_ULOGIC_VECTOR) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L /= R" where L and R are UNSIGNED vectors possibly
-- of different lengths.
-- Id: C.33
function "/=" (L : NATURAL; R : STD_ULOGIC_VECTOR) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L /= R" where L is a non-negative INTEGER and
-- R is an UNSIGNED vector.
-- Id: C.35
function "/=" (L : STD_ULOGIC_VECTOR; R : NATURAL) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L /= R" where L is an UNSIGNED vector and
-- R is a non-negative INTEGER.
--============================================================================
-- Id: C.37
function MINIMUM (L, R : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;
-- Result subtype: STD_ULOGIC_VECTOR
-- Result: Returns the lesser of two UNSIGNED vectors that may be
-- of different lengths.
-- Id: C.39
function MINIMUM (L : NATURAL; R : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;
-- Result subtype: STD_ULOGIC_VECTOR
-- Result: Returns the lesser of a nonnegative INTEGER, L, and
-- an UNSIGNED vector, R.
-- Id: C.41
function MINIMUM (L : STD_ULOGIC_VECTOR; R : NATURAL) return STD_ULOGIC_VECTOR;
-- Result subtype: STD_ULOGIC_VECTOR
-- Result: Returns the lesser of an UNSIGNED vector, L, and
-- a nonnegative INTEGER, R.
--============================================================================
-- Id: C.43
function MAXIMUM (L, R : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;
-- Result subtype: STD_ULOGIC_VECTOR
-- Result: Returns the greater of two UNSIGNED vectors that may be
-- of different lengths.
-- Id: C.45
function MAXIMUM (L : NATURAL; R : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;
-- Result subtype: STD_ULOGIC_VECTOR
-- Result: Returns the greater of a nonnegative INTEGER, L, and
-- an UNSIGNED vector, R.
-- Id: C.47
function MAXIMUM (L : STD_ULOGIC_VECTOR; R : NATURAL) return STD_ULOGIC_VECTOR;
-- Result subtype: STD_ULOGIC_VECTOR
-- Result: Returns the greater of an UNSIGNED vector, L, and
-- a nonnegative INTEGER, R.
--============================================================================
-- Id: C.49
function "?>" (L, R : STD_ULOGIC_VECTOR) return STD_ULOGIC;
-- Result subtype: STD_ULOGIC
-- Result: Computes "L > R" where L and R are UNSIGNED vectors possibly
-- of different lengths.
-- Id: C.51
function "?>" (L : NATURAL; R : STD_ULOGIC_VECTOR) return STD_ULOGIC;
-- Result subtype: STD_ULOGIC
-- Result: Computes "L > R" where L is a nonnegative INTEGER and
-- R is an UNSIGNED vector.
-- Id: C.53
function "?>" (L : STD_ULOGIC_VECTOR; R : NATURAL) return STD_ULOGIC;
-- Result subtype: STD_ULOGIC
-- Result: Computes "L > R" where L is an UNSIGNED vector and
-- R is a nonnegative INTEGER.
--============================================================================
-- Id: C.55
function "?<" (L, R : STD_ULOGIC_VECTOR) return STD_ULOGIC;
-- Result subtype: STD_ULOGIC
-- Result: Computes "L < R" where L and R are UNSIGNED vectors possibly
-- of different lengths.
-- Id: C.57
function "?<" (L : NATURAL; R : STD_ULOGIC_VECTOR) return STD_ULOGIC;
-- Result subtype: STD_ULOGIC
-- Result: Computes "L < R" where L is a nonnegative INTEGER and
-- R is an UNSIGNED vector.
-- Id: C.59
function "?<" (L : STD_ULOGIC_VECTOR; R : NATURAL) return STD_ULOGIC;
-- Result subtype: STD_ULOGIC
-- Result: Computes "L < R" where L is an UNSIGNED vector and
-- R is a nonnegative INTEGER.
--============================================================================
-- Id: C.61
function "?<=" (L, R : STD_ULOGIC_VECTOR) return STD_ULOGIC;
-- Result subtype: STD_ULOGIC
-- Result: Computes "L <= R" where L and R are UNSIGNED vectors possibly
-- of different lengths.
-- Id: C.63
function "?<=" (L : NATURAL; R : STD_ULOGIC_VECTOR) return STD_ULOGIC;
-- Result subtype: STD_ULOGIC
-- Result: Computes "L <= R" where L is a nonnegative INTEGER and
-- R is an UNSIGNED vector.
-- Id: C.65
function "?<=" (L : STD_ULOGIC_VECTOR; R : NATURAL) return STD_ULOGIC;
-- Result subtype: STD_ULOGIC
-- Result: Computes "L <= R" where L is an UNSIGNED vector and
-- R is a nonnegative INTEGER.
--============================================================================
-- Id: C.67
function "?>=" (L, R : STD_ULOGIC_VECTOR) return STD_ULOGIC;
-- Result subtype: STD_ULOGIC
-- Result: Computes "L >= R" where L and R are UNSIGNED vectors possibly
-- of different lengths.
-- Id: C.69
function "?>=" (L : NATURAL; R : STD_ULOGIC_VECTOR) return STD_ULOGIC;
-- Result subtype: STD_ULOGIC
-- Result: Computes "L >= R" where L is a nonnegative INTEGER and
-- R is an UNSIGNED vector.
-- Id: C.71
function "?>=" (L : STD_ULOGIC_VECTOR; R : NATURAL) return STD_ULOGIC;
-- Result subtype: STD_ULOGIC
-- Result: Computes "L >= R" where L is an UNSIGNED vector and
-- R is a nonnegative INTEGER.
--============================================================================
-- Id: C.73
function "?=" (L, R : STD_ULOGIC_VECTOR) return STD_ULOGIC;
-- Result subtype: STD_ULOGIC
-- Result: Computes "L = R" where L and R are UNSIGNED vectors possibly
-- of different lengths.
-- Id: C.75
function "?=" (L : NATURAL; R : STD_ULOGIC_VECTOR) return STD_ULOGIC;
-- Result subtype: STD_ULOGIC
-- Result: Computes "L = R" where L is a nonnegative INTEGER and
-- R is an UNSIGNED vector.
-- Id: C.77
function "?=" (L : STD_ULOGIC_VECTOR; R : NATURAL) return STD_ULOGIC;
-- Result subtype: STD_ULOGIC
-- Result: Computes "L = R" where L is an UNSIGNED vector and
-- R is a nonnegative INTEGER.
--============================================================================
-- Id: C.79
function "?/=" (L, R : STD_ULOGIC_VECTOR) return STD_ULOGIC;
-- Result subtype: STD_ULOGIC
-- Result: Computes "L /= R" where L and R are UNSIGNED vectors possibly
-- of different lengths.
-- Id: C.81
function "?/=" (L : NATURAL; R : STD_ULOGIC_VECTOR) return STD_ULOGIC;
-- Result subtype: STD_ULOGIC
-- Result: Computes "L /= R" where L is a nonnegative INTEGER and
-- R is an UNSIGNED vector.
-- Id: C.83
function "?/=" (L : STD_ULOGIC_VECTOR; R : NATURAL) return STD_ULOGIC;
-- Result subtype: STD_ULOGIC
-- Result: Computes "L /= R" where L is an UNSIGNED vector and
-- R is a nonnegative INTEGER.
--============================================================================
-- Shift and Rotate Functions
--============================================================================
-- Id: S.1
function SHIFT_LEFT (ARG : STD_ULOGIC_VECTOR; COUNT : NATURAL)
return STD_ULOGIC_VECTOR;
-- Result subtype: STD_ULOGIC_VECTOR(ARG'LENGTH-1 downto 0)
-- Result: Performs a shift-left on an UNSIGNED vector COUNT times.
-- The vacated positions are filled with '0'.
-- The COUNT leftmost elements are lost.
-- Id: S.2
function SHIFT_RIGHT (ARG : STD_ULOGIC_VECTOR; COUNT : NATURAL)
return STD_ULOGIC_VECTOR;
-- Result subtype: UNSIGNED(ARG'LENGTH-1 downto 0)
-- Result: Performs a shift-right on an UNSIGNED vector COUNT times.
-- The vacated positions are filled with '0'.
-- The COUNT rightmost elements are lost.
--============================================================================
-- Id: S.5
function ROTATE_LEFT (ARG : STD_ULOGIC_VECTOR; COUNT : NATURAL)
return STD_ULOGIC_VECTOR;
-- Result subtype: STD_ULOGIC_VECTOR(ARG'LENGTH-1 downto 0)
-- Result: Performs a rotate-left of an UNSIGNED vector COUNT times.
-- Id: S.6
function ROTATE_RIGHT (ARG : STD_ULOGIC_VECTOR; COUNT : NATURAL)
return STD_ULOGIC_VECTOR;
-- Result subtype: STD_ULOGIC_VECTOR(ARG'LENGTH-1 downto 0)
-- Result: Performs a rotate-right of an UNSIGNED vector COUNT times.
--============================================================================
------------------------------------------------------------------------------
-- Note: Function S.17 is not compatible with IEEE Std 1076-1987. Comment
-- out the function (declaration and body) for IEEE Std 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.17
function "sla" (ARG : STD_ULOGIC_VECTOR; COUNT : INTEGER) return STD_ULOGIC_VECTOR;
-- Result subtype: STD_ULOGIC_VECTOR(ARG'LENGTH-1 downto 0)
-- Result: SHIFT_LEFT(ARG, COUNT)
------------------------------------------------------------------------------
-- Note: Function S.19 is not compatible with IEEE Std 1076-1987. Comment
-- out the function (declaration and body) for IEEE Std 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.19
function "sra" (ARG : STD_ULOGIC_VECTOR; COUNT : INTEGER) return STD_ULOGIC_VECTOR;
-- Result subtype: STD_ULOGIC_VECTOR(ARG'LENGTH-1 downto 0)
-- Result: SHIFT_RIGHT(ARG, COUNT)
--============================================================================
-- RESIZE Functions
--============================================================================
-- Id: R.2
function RESIZE (ARG : STD_ULOGIC_VECTOR; NEW_SIZE : NATURAL)
return STD_ULOGIC_VECTOR;
-- Result subtype: STD_ULOGIC_VECTOR(NEW_SIZE-1 downto 0)
-- Result: Resizes the UNSIGNED vector ARG to the specified size.
-- To create a larger vector, the new [leftmost] bit positions
-- are filled with '0'. When truncating, the leftmost bits
-- are dropped.
function RESIZE (ARG, SIZE_RES : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;
-- Result subtype: STD_ULOGIC_VECTOR (SIZE_RES'length-1 downto 0)
--============================================================================
-- Conversion Functions
--============================================================================
-- Id: D.1
function TO_INTEGER (ARG : STD_ULOGIC_VECTOR) return NATURAL;
-- Result subtype: NATURAL. Value cannot be negative since parameter is an
-- UNSIGNED vector.
-- Result: Converts the UNSIGNED vector to an INTEGER.
-- Id: D.3
function To_StdLogicVector (ARG, SIZE : NATURAL) return STD_LOGIC_VECTOR;
-- Result subtype: STD_LOGIC_VECTOR(SIZE-1 downto 0)
-- Result: Converts a non-negative INTEGER to an UNSIGNED vector with
-- the specified SIZE.
function To_StdLogicVector (ARG : NATURAL; SIZE_RES : STD_ULOGIC_VECTOR)
return STD_LOGIC_VECTOR;
-- Result subtype: STD_LOGIC_VECTOR(SIZE_RES'length-1 downto 0)
alias To_Std_Logic_Vector is
To_StdLogicVector[NATURAL, NATURAL return STD_LOGIC_VECTOR];
alias To_SLV is
To_StdLogicVector[NATURAL, NATURAL return STD_LOGIC_VECTOR];
alias To_Std_Logic_Vector is
To_StdLogicVector[NATURAL, STD_ULOGIC_VECTOR return STD_LOGIC_VECTOR];
alias To_SLV is
To_StdLogicVector[NATURAL, STD_ULOGIC_VECTOR return STD_LOGIC_VECTOR];
-- Id: D.5
function To_StdULogicVector (ARG, SIZE : NATURAL) return STD_ULOGIC_VECTOR;
-- Result subtype: STD_ULOGIC_VECTOR(SIZE-1 downto 0)
-- Result: Converts a non-negative INTEGER to an UNSIGNED vector with
-- the specified SIZE.
function To_StdULogicVector (ARG : NATURAL; SIZE_RES : STD_ULOGIC_VECTOR)
return STD_ULOGIC_VECTOR;
-- Result subtype: STD_LOGIC_VECTOR(SIZE_RES'length-1 downto 0)
alias To_Std_ULogic_Vector is
To_StdULogicVector[NATURAL, NATURAL return STD_ULOGIC_VECTOR];
alias To_SULV is
To_StdULogicVector[NATURAL, NATURAL return STD_ULOGIC_VECTOR];
alias To_Std_ULogic_Vector is
To_StdULogicVector[NATURAL, STD_ULOGIC_VECTOR return STD_ULOGIC_VECTOR];
alias To_SULV is
To_StdULogicVector[NATURAL, STD_ULOGIC_VECTOR return STD_ULOGIC_VECTOR];
end package NUMERIC_STD_UNSIGNED;
| gpl-2.0 | 95b4ebdd64fff2177e0a1f7d36306439 | 0.568663 | 4.177429 | false | false | false | false |
emogenet/ghdl | libraries/synopsys/std_logic_arith.vhdl | 5 | 70,211 | --------------------------------------------------------------------------
-- --
-- Copyright (c) 1990,1991,1992 by Synopsys, Inc. All rights reserved. --
-- --
-- This source file may be used and distributed without restriction --
-- provided that this copyright statement is not removed from the file --
-- and that any derivative work contains this copyright notice. --
-- --
-- Package name: STD_LOGIC_ARITH --
-- --
-- Purpose: --
-- A set of arithemtic, conversion, and comparison functions --
-- for SIGNED, UNSIGNED, SMALL_INT, INTEGER, --
-- STD_ULOGIC, STD_LOGIC, and STD_LOGIC_VECTOR. --
-- --
--------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
package std_logic_arith is
type UNSIGNED is array (NATURAL range <>) of STD_LOGIC;
type SIGNED is array (NATURAL range <>) of STD_LOGIC;
subtype SMALL_INT is INTEGER range 0 to 1;
function "+"(L: UNSIGNED; R: UNSIGNED) return UNSIGNED;
function "+"(L: SIGNED; R: SIGNED) return SIGNED;
function "+"(L: UNSIGNED; R: SIGNED) return SIGNED;
function "+"(L: SIGNED; R: UNSIGNED) return SIGNED;
function "+"(L: UNSIGNED; R: INTEGER) return UNSIGNED;
function "+"(L: INTEGER; R: UNSIGNED) return UNSIGNED;
function "+"(L: SIGNED; R: INTEGER) return SIGNED;
function "+"(L: INTEGER; R: SIGNED) return SIGNED;
function "+"(L: UNSIGNED; R: STD_ULOGIC) return UNSIGNED;
function "+"(L: STD_ULOGIC; R: UNSIGNED) return UNSIGNED;
function "+"(L: SIGNED; R: STD_ULOGIC) return SIGNED;
function "+"(L: STD_ULOGIC; R: SIGNED) return SIGNED;
function "+"(L: UNSIGNED; R: UNSIGNED) return STD_LOGIC_VECTOR;
function "+"(L: SIGNED; R: SIGNED) return STD_LOGIC_VECTOR;
function "+"(L: UNSIGNED; R: SIGNED) return STD_LOGIC_VECTOR;
function "+"(L: SIGNED; R: UNSIGNED) return STD_LOGIC_VECTOR;
function "+"(L: UNSIGNED; R: INTEGER) return STD_LOGIC_VECTOR;
function "+"(L: INTEGER; R: UNSIGNED) return STD_LOGIC_VECTOR;
function "+"(L: SIGNED; R: INTEGER) return STD_LOGIC_VECTOR;
function "+"(L: INTEGER; R: SIGNED) return STD_LOGIC_VECTOR;
function "+"(L: UNSIGNED; R: STD_ULOGIC) return STD_LOGIC_VECTOR;
function "+"(L: STD_ULOGIC; R: UNSIGNED) return STD_LOGIC_VECTOR;
function "+"(L: SIGNED; R: STD_ULOGIC) return STD_LOGIC_VECTOR;
function "+"(L: STD_ULOGIC; R: SIGNED) return STD_LOGIC_VECTOR;
function "-"(L: UNSIGNED; R: UNSIGNED) return UNSIGNED;
function "-"(L: SIGNED; R: SIGNED) return SIGNED;
function "-"(L: UNSIGNED; R: SIGNED) return SIGNED;
function "-"(L: SIGNED; R: UNSIGNED) return SIGNED;
function "-"(L: UNSIGNED; R: INTEGER) return UNSIGNED;
function "-"(L: INTEGER; R: UNSIGNED) return UNSIGNED;
function "-"(L: SIGNED; R: INTEGER) return SIGNED;
function "-"(L: INTEGER; R: SIGNED) return SIGNED;
function "-"(L: UNSIGNED; R: STD_ULOGIC) return UNSIGNED;
function "-"(L: STD_ULOGIC; R: UNSIGNED) return UNSIGNED;
function "-"(L: SIGNED; R: STD_ULOGIC) return SIGNED;
function "-"(L: STD_ULOGIC; R: SIGNED) return SIGNED;
function "-"(L: UNSIGNED; R: UNSIGNED) return STD_LOGIC_VECTOR;
function "-"(L: SIGNED; R: SIGNED) return STD_LOGIC_VECTOR;
function "-"(L: UNSIGNED; R: SIGNED) return STD_LOGIC_VECTOR;
function "-"(L: SIGNED; R: UNSIGNED) return STD_LOGIC_VECTOR;
function "-"(L: UNSIGNED; R: INTEGER) return STD_LOGIC_VECTOR;
function "-"(L: INTEGER; R: UNSIGNED) return STD_LOGIC_VECTOR;
function "-"(L: SIGNED; R: INTEGER) return STD_LOGIC_VECTOR;
function "-"(L: INTEGER; R: SIGNED) return STD_LOGIC_VECTOR;
function "-"(L: UNSIGNED; R: STD_ULOGIC) return STD_LOGIC_VECTOR;
function "-"(L: STD_ULOGIC; R: UNSIGNED) return STD_LOGIC_VECTOR;
function "-"(L: SIGNED; R: STD_ULOGIC) return STD_LOGIC_VECTOR;
function "-"(L: STD_ULOGIC; R: SIGNED) return STD_LOGIC_VECTOR;
function "+"(L: UNSIGNED) return UNSIGNED;
function "+"(L: SIGNED) return SIGNED;
function "-"(L: SIGNED) return SIGNED;
function "ABS"(L: SIGNED) return SIGNED;
function "+"(L: UNSIGNED) return STD_LOGIC_VECTOR;
function "+"(L: SIGNED) return STD_LOGIC_VECTOR;
function "-"(L: SIGNED) return STD_LOGIC_VECTOR;
function "ABS"(L: SIGNED) return STD_LOGIC_VECTOR;
function "*"(L: UNSIGNED; R: UNSIGNED) return UNSIGNED;
function "*"(L: SIGNED; R: SIGNED) return SIGNED;
function "*"(L: SIGNED; R: UNSIGNED) return SIGNED;
function "*"(L: UNSIGNED; R: SIGNED) return SIGNED;
function "*"(L: UNSIGNED; R: UNSIGNED) return STD_LOGIC_VECTOR;
function "*"(L: SIGNED; R: SIGNED) return STD_LOGIC_VECTOR;
function "*"(L: SIGNED; R: UNSIGNED) return STD_LOGIC_VECTOR;
function "*"(L: UNSIGNED; R: SIGNED) return STD_LOGIC_VECTOR;
function "<"(L: UNSIGNED; R: UNSIGNED) return BOOLEAN;
function "<"(L: SIGNED; R: SIGNED) return BOOLEAN;
function "<"(L: UNSIGNED; R: SIGNED) return BOOLEAN;
function "<"(L: SIGNED; R: UNSIGNED) return BOOLEAN;
function "<"(L: UNSIGNED; R: INTEGER) return BOOLEAN;
function "<"(L: INTEGER; R: UNSIGNED) return BOOLEAN;
function "<"(L: SIGNED; R: INTEGER) return BOOLEAN;
function "<"(L: INTEGER; R: SIGNED) return BOOLEAN;
function "<="(L: UNSIGNED; R: UNSIGNED) return BOOLEAN;
function "<="(L: SIGNED; R: SIGNED) return BOOLEAN;
function "<="(L: UNSIGNED; R: SIGNED) return BOOLEAN;
function "<="(L: SIGNED; R: UNSIGNED) return BOOLEAN;
function "<="(L: UNSIGNED; R: INTEGER) return BOOLEAN;
function "<="(L: INTEGER; R: UNSIGNED) return BOOLEAN;
function "<="(L: SIGNED; R: INTEGER) return BOOLEAN;
function "<="(L: INTEGER; R: SIGNED) return BOOLEAN;
function ">"(L: UNSIGNED; R: UNSIGNED) return BOOLEAN;
function ">"(L: SIGNED; R: SIGNED) return BOOLEAN;
function ">"(L: UNSIGNED; R: SIGNED) return BOOLEAN;
function ">"(L: SIGNED; R: UNSIGNED) return BOOLEAN;
function ">"(L: UNSIGNED; R: INTEGER) return BOOLEAN;
function ">"(L: INTEGER; R: UNSIGNED) return BOOLEAN;
function ">"(L: SIGNED; R: INTEGER) return BOOLEAN;
function ">"(L: INTEGER; R: SIGNED) return BOOLEAN;
function ">="(L: UNSIGNED; R: UNSIGNED) return BOOLEAN;
function ">="(L: SIGNED; R: SIGNED) return BOOLEAN;
function ">="(L: UNSIGNED; R: SIGNED) return BOOLEAN;
function ">="(L: SIGNED; R: UNSIGNED) return BOOLEAN;
function ">="(L: UNSIGNED; R: INTEGER) return BOOLEAN;
function ">="(L: INTEGER; R: UNSIGNED) return BOOLEAN;
function ">="(L: SIGNED; R: INTEGER) return BOOLEAN;
function ">="(L: INTEGER; R: SIGNED) return BOOLEAN;
function "="(L: UNSIGNED; R: UNSIGNED) return BOOLEAN;
function "="(L: SIGNED; R: SIGNED) return BOOLEAN;
function "="(L: UNSIGNED; R: SIGNED) return BOOLEAN;
function "="(L: SIGNED; R: UNSIGNED) return BOOLEAN;
function "="(L: UNSIGNED; R: INTEGER) return BOOLEAN;
function "="(L: INTEGER; R: UNSIGNED) return BOOLEAN;
function "="(L: SIGNED; R: INTEGER) return BOOLEAN;
function "="(L: INTEGER; R: SIGNED) return BOOLEAN;
function "/="(L: UNSIGNED; R: UNSIGNED) return BOOLEAN;
function "/="(L: SIGNED; R: SIGNED) return BOOLEAN;
function "/="(L: UNSIGNED; R: SIGNED) return BOOLEAN;
function "/="(L: SIGNED; R: UNSIGNED) return BOOLEAN;
function "/="(L: UNSIGNED; R: INTEGER) return BOOLEAN;
function "/="(L: INTEGER; R: UNSIGNED) return BOOLEAN;
function "/="(L: SIGNED; R: INTEGER) return BOOLEAN;
function "/="(L: INTEGER; R: SIGNED) return BOOLEAN;
function SHL(ARG: UNSIGNED; COUNT: UNSIGNED) return UNSIGNED;
function SHL(ARG: SIGNED; COUNT: UNSIGNED) return SIGNED;
function SHR(ARG: UNSIGNED; COUNT: UNSIGNED) return UNSIGNED;
function SHR(ARG: SIGNED; COUNT: UNSIGNED) return SIGNED;
function CONV_INTEGER(ARG: INTEGER) return INTEGER;
function CONV_INTEGER(ARG: UNSIGNED) return INTEGER;
function CONV_INTEGER(ARG: SIGNED) return INTEGER;
function CONV_INTEGER(ARG: STD_ULOGIC) return SMALL_INT;
function CONV_UNSIGNED(ARG: INTEGER; SIZE: INTEGER) return UNSIGNED;
function CONV_UNSIGNED(ARG: UNSIGNED; SIZE: INTEGER) return UNSIGNED;
function CONV_UNSIGNED(ARG: SIGNED; SIZE: INTEGER) return UNSIGNED;
function CONV_UNSIGNED(ARG: STD_ULOGIC; SIZE: INTEGER) return UNSIGNED;
function CONV_SIGNED(ARG: INTEGER; SIZE: INTEGER) return SIGNED;
function CONV_SIGNED(ARG: UNSIGNED; SIZE: INTEGER) return SIGNED;
function CONV_SIGNED(ARG: SIGNED; SIZE: INTEGER) return SIGNED;
function CONV_SIGNED(ARG: STD_ULOGIC; SIZE: INTEGER) return SIGNED;
function CONV_STD_LOGIC_VECTOR(ARG: INTEGER; SIZE: INTEGER)
return STD_LOGIC_VECTOR;
function CONV_STD_LOGIC_VECTOR(ARG: UNSIGNED; SIZE: INTEGER)
return STD_LOGIC_VECTOR;
function CONV_STD_LOGIC_VECTOR(ARG: SIGNED; SIZE: INTEGER)
return STD_LOGIC_VECTOR;
function CONV_STD_LOGIC_VECTOR(ARG: STD_ULOGIC; SIZE: INTEGER)
return STD_LOGIC_VECTOR;
-- zero extend STD_LOGIC_VECTOR (ARG) to SIZE,
-- SIZE < 0 is same as SIZE = 0
-- returns STD_LOGIC_VECTOR(SIZE-1 downto 0)
function EXT(ARG: STD_LOGIC_VECTOR; SIZE: INTEGER) return STD_LOGIC_VECTOR;
-- sign extend STD_LOGIC_VECTOR (ARG) to SIZE,
-- SIZE < 0 is same as SIZE = 0
-- return STD_LOGIC_VECTOR(SIZE-1 downto 0)
function SXT(ARG: STD_LOGIC_VECTOR; SIZE: INTEGER) return STD_LOGIC_VECTOR;
end Std_logic_arith;
library IEEE;
use IEEE.std_logic_1164.all;
package body std_logic_arith is
function max(L, R: INTEGER) return INTEGER is
begin
if L > R then
return L;
else
return R;
end if;
end;
function min(L, R: INTEGER) return INTEGER is
begin
if L < R then
return L;
else
return R;
end if;
end;
-- synopsys synthesis_off
type tbl_type is array (STD_ULOGIC) of STD_ULOGIC;
constant tbl_BINARY : tbl_type :=
('X', 'X', '0', '1', 'X', 'X', '0', '1', 'X');
-- synopsys synthesis_on
-- synopsys synthesis_off
type tbl_mvl9_boolean is array (STD_ULOGIC) of boolean;
constant IS_X : tbl_mvl9_boolean :=
(true, true, false, false, true, true, false, false, true);
-- synopsys synthesis_on
function MAKE_BINARY(A : STD_ULOGIC) return STD_ULOGIC is
-- synopsys built_in SYN_FEED_THRU
begin
-- synopsys synthesis_off
if (IS_X(A)) then
assert false
report "There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es)."
severity warning;
return ('X');
end if;
return tbl_BINARY(A);
-- synopsys synthesis_on
end;
function MAKE_BINARY(A : UNSIGNED) return UNSIGNED is
-- synopsys built_in SYN_FEED_THRU
variable one_bit : STD_ULOGIC;
variable result : UNSIGNED (A'range);
begin
-- synopsys synthesis_off
for i in A'range loop
if (IS_X(A(i))) then
assert false
report "There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es)."
severity warning;
result := (others => 'X');
return result;
end if;
result(i) := tbl_BINARY(A(i));
end loop;
return result;
-- synopsys synthesis_on
end;
function MAKE_BINARY(A : UNSIGNED) return SIGNED is
-- synopsys built_in SYN_FEED_THRU
variable one_bit : STD_ULOGIC;
variable result : SIGNED (A'range);
begin
-- synopsys synthesis_off
for i in A'range loop
if (IS_X(A(i))) then
assert false
report "There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es)."
severity warning;
result := (others => 'X');
return result;
end if;
result(i) := tbl_BINARY(A(i));
end loop;
return result;
-- synopsys synthesis_on
end;
function MAKE_BINARY(A : SIGNED) return UNSIGNED is
-- synopsys built_in SYN_FEED_THRU
variable one_bit : STD_ULOGIC;
variable result : UNSIGNED (A'range);
begin
-- synopsys synthesis_off
for i in A'range loop
if (IS_X(A(i))) then
assert false
report "There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es)."
severity warning;
result := (others => 'X');
return result;
end if;
result(i) := tbl_BINARY(A(i));
end loop;
return result;
-- synopsys synthesis_on
end;
function MAKE_BINARY(A : SIGNED) return SIGNED is
-- synopsys built_in SYN_FEED_THRU
variable one_bit : STD_ULOGIC;
variable result : SIGNED (A'range);
begin
-- synopsys synthesis_off
for i in A'range loop
if (IS_X(A(i))) then
assert false
report "There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es)."
severity warning;
result := (others => 'X');
return result;
end if;
result(i) := tbl_BINARY(A(i));
end loop;
return result;
-- synopsys synthesis_on
end;
function MAKE_BINARY(A : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
-- synopsys built_in SYN_FEED_THRU
variable one_bit : STD_ULOGIC;
variable result : STD_LOGIC_VECTOR (A'range);
begin
-- synopsys synthesis_off
for i in A'range loop
if (IS_X(A(i))) then
assert false
report "There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es)."
severity warning;
result := (others => 'X');
return result;
end if;
result(i) := tbl_BINARY(A(i));
end loop;
return result;
-- synopsys synthesis_on
end;
function MAKE_BINARY(A : UNSIGNED) return STD_LOGIC_VECTOR is
-- synopsys built_in SYN_FEED_THRU
variable one_bit : STD_ULOGIC;
variable result : STD_LOGIC_VECTOR (A'range);
begin
-- synopsys synthesis_off
for i in A'range loop
if (IS_X(A(i))) then
assert false
report "There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es)."
severity warning;
result := (others => 'X');
return result;
end if;
result(i) := tbl_BINARY(A(i));
end loop;
return result;
-- synopsys synthesis_on
end;
function MAKE_BINARY(A : SIGNED) return STD_LOGIC_VECTOR is
-- synopsys built_in SYN_FEED_THRU
variable one_bit : STD_ULOGIC;
variable result : STD_LOGIC_VECTOR (A'range);
begin
-- synopsys synthesis_off
for i in A'range loop
if (IS_X(A(i))) then
assert false
report "There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es)."
severity warning;
result := (others => 'X');
return result;
end if;
result(i) := tbl_BINARY(A(i));
end loop;
return result;
-- synopsys synthesis_on
end;
-- Type propagation function which returns a signed type with the
-- size of the left arg.
function LEFT_SIGNED_ARG(A,B: SIGNED) return SIGNED is
variable Z: SIGNED (A'left downto 0);
-- pragma return_port_name Z
begin
return(Z);
end;
-- Type propagation function which returns an unsigned type with the
-- size of the left arg.
function LEFT_UNSIGNED_ARG(A,B: UNSIGNED) return UNSIGNED is
variable Z: UNSIGNED (A'left downto 0);
-- pragma return_port_name Z
begin
return(Z);
end;
-- Type propagation function which returns a signed type with the
-- size of the result of a signed multiplication
function MULT_SIGNED_ARG(A,B: SIGNED) return SIGNED is
variable Z: SIGNED ((A'length+B'length-1) downto 0);
-- pragma return_port_name Z
begin
return(Z);
end;
-- Type propagation function which returns an unsigned type with the
-- size of the result of a unsigned multiplication
function MULT_UNSIGNED_ARG(A,B: UNSIGNED) return UNSIGNED is
variable Z: UNSIGNED ((A'length+B'length-1) downto 0);
-- pragma return_port_name Z
begin
return(Z);
end;
function mult(A,B: SIGNED) return SIGNED is
variable BA: SIGNED((A'length+B'length-1) downto 0);
variable PA: SIGNED((A'length+B'length-1) downto 0);
variable AA: SIGNED(A'length downto 0);
variable neg: STD_ULOGIC;
constant one : UNSIGNED(1 downto 0) := "01";
-- pragma map_to_operator MULT_TC_OP
-- pragma type_function MULT_SIGNED_ARG
-- pragma return_port_name Z
begin
if (A(A'left) = 'X' or B(B'left) = 'X') then
PA := (others => 'X');
return(PA);
end if;
PA := (others => '0');
neg := B(B'left) xor A(A'left);
BA := CONV_SIGNED(('0' & ABS(B)),(A'length+B'length));
AA := '0' & ABS(A);
for i in integer range 0 to A'length-1 loop
if AA(i) = '1' then
PA := PA+BA;
end if;
BA := SHL(BA,one);
end loop;
if (neg= '1') then
return(-PA);
else
return(PA);
end if;
end;
function mult(A,B: UNSIGNED) return UNSIGNED is
variable BA: UNSIGNED((A'length+B'length-1) downto 0);
variable PA: UNSIGNED((A'length+B'length-1) downto 0);
constant one : UNSIGNED(1 downto 0) := "01";
-- pragma map_to_operator MULT_UNS_OP
-- pragma type_function MULT_UNSIGNED_ARG
-- pragma return_port_name Z
begin
if (A(A'left) = 'X' or B(B'left) = 'X') then
PA := (others => 'X');
return(PA);
end if;
PA := (others => '0');
BA := CONV_UNSIGNED(B,(A'length+B'length));
for i in integer range 0 to A'length-1 loop
if A(i) = '1' then
PA := PA+BA;
end if;
BA := SHL(BA,one);
end loop;
return(PA);
end;
-- subtract two signed numbers of the same length
-- both arrays must have range (msb downto 0)
function minus(A, B: SIGNED) return SIGNED is
variable carry: STD_ULOGIC;
variable BV: STD_ULOGIC_VECTOR (A'left downto 0);
variable sum: SIGNED (A'left downto 0);
-- pragma map_to_operator SUB_TC_OP
-- pragma type_function LEFT_SIGNED_ARG
-- pragma return_port_name Z
begin
if (A(A'left) = 'X' or B(B'left) = 'X') then
sum := (others => 'X');
return(sum);
end if;
carry := '1';
BV := not STD_ULOGIC_VECTOR(B);
for i in 0 to A'left loop
sum(i) := A(i) xor BV(i) xor carry;
carry := (A(i) and BV(i)) or
(A(i) and carry) or
(carry and BV(i));
end loop;
return sum;
end;
-- add two signed numbers of the same length
-- both arrays must have range (msb downto 0)
function plus(A, B: SIGNED) return SIGNED is
variable carry: STD_ULOGIC;
variable BV, sum: SIGNED (A'left downto 0);
-- pragma map_to_operator ADD_TC_OP
-- pragma type_function LEFT_SIGNED_ARG
-- pragma return_port_name Z
begin
if (A(A'left) = 'X' or B(B'left) = 'X') then
sum := (others => 'X');
return(sum);
end if;
carry := '0';
BV := B;
for i in 0 to A'left loop
sum(i) := A(i) xor BV(i) xor carry;
carry := (A(i) and BV(i)) or
(A(i) and carry) or
(carry and BV(i));
end loop;
return sum;
end;
-- subtract two unsigned numbers of the same length
-- both arrays must have range (msb downto 0)
function unsigned_minus(A, B: UNSIGNED) return UNSIGNED is
variable carry: STD_ULOGIC;
variable BV: STD_ULOGIC_VECTOR (A'left downto 0);
variable sum: UNSIGNED (A'left downto 0);
-- pragma map_to_operator SUB_UNS_OP
-- pragma type_function LEFT_UNSIGNED_ARG
-- pragma return_port_name Z
begin
if (A(A'left) = 'X' or B(B'left) = 'X') then
sum := (others => 'X');
return(sum);
end if;
carry := '1';
BV := not STD_ULOGIC_VECTOR(B);
for i in 0 to A'left loop
sum(i) := A(i) xor BV(i) xor carry;
carry := (A(i) and BV(i)) or
(A(i) and carry) or
(carry and BV(i));
end loop;
return sum;
end;
-- add two unsigned numbers of the same length
-- both arrays must have range (msb downto 0)
function unsigned_plus(A, B: UNSIGNED) return UNSIGNED is
variable carry: STD_ULOGIC;
variable BV, sum: UNSIGNED (A'left downto 0);
-- pragma map_to_operator ADD_UNS_OP
-- pragma type_function LEFT_UNSIGNED_ARG
-- pragma return_port_name Z
begin
if (A(A'left) = 'X' or B(B'left) = 'X') then
sum := (others => 'X');
return(sum);
end if;
carry := '0';
BV := B;
for i in 0 to A'left loop
sum(i) := A(i) xor BV(i) xor carry;
carry := (A(i) and BV(i)) or
(A(i) and carry) or
(carry and BV(i));
end loop;
return sum;
end;
function "*"(L: SIGNED; R: SIGNED) return SIGNED is
-- pragma label_applies_to mult
-- synopsys subpgm_id 296
begin
return mult(CONV_SIGNED(L, L'length),
CONV_SIGNED(R, R'length)); -- pragma label mult
end;
function "*"(L: UNSIGNED; R: UNSIGNED) return UNSIGNED is
-- pragma label_applies_to mult
-- synopsys subpgm_id 295
begin
return mult(CONV_UNSIGNED(L, L'length),
CONV_UNSIGNED(R, R'length)); -- pragma label mult
end;
function "*"(L: UNSIGNED; R: SIGNED) return SIGNED is
-- pragma label_applies_to mult
-- synopsys subpgm_id 297
begin
return mult(CONV_SIGNED(L, L'length+1),
CONV_SIGNED(R, R'length)); -- pragma label mult
end;
function "*"(L: SIGNED; R: UNSIGNED) return SIGNED is
-- pragma label_applies_to mult
-- synopsys subpgm_id 298
begin
return mult(CONV_SIGNED(L, L'length),
CONV_SIGNED(R, R'length+1)); -- pragma label mult
end;
function "*"(L: SIGNED; R: SIGNED) return STD_LOGIC_VECTOR is
-- pragma label_applies_to mult
-- synopsys subpgm_id 301
begin
return STD_LOGIC_VECTOR (
mult(-- pragma label mult
CONV_SIGNED(L, L'length), CONV_SIGNED(R, R'length)));
end;
function "*"(L: UNSIGNED; R: UNSIGNED) return STD_LOGIC_VECTOR is
-- pragma label_applies_to mult
-- synopsys subpgm_id 300
begin
return STD_LOGIC_VECTOR (
mult(-- pragma label mult
CONV_UNSIGNED(L, L'length), CONV_UNSIGNED(R, R'length)));
end;
function "*"(L: UNSIGNED; R: SIGNED) return STD_LOGIC_VECTOR is
-- pragma label_applies_to mult
-- synopsys subpgm_id 302
begin
return STD_LOGIC_VECTOR (
mult(-- pragma label mult
CONV_SIGNED(L, L'length+1), CONV_SIGNED(R, R'length)));
end;
function "*"(L: SIGNED; R: UNSIGNED) return STD_LOGIC_VECTOR is
-- pragma label_applies_to mult
-- synopsys subpgm_id 303
begin
return STD_LOGIC_VECTOR (
mult(-- pragma label mult
CONV_SIGNED(L, L'length), CONV_SIGNED(R, R'length+1)));
end;
function "+"(L: UNSIGNED; R: UNSIGNED) return UNSIGNED is
-- pragma label_applies_to plus
-- synopsys subpgm_id 236
constant length: INTEGER := max(L'length, R'length);
begin
return unsigned_plus(CONV_UNSIGNED(L, length),
CONV_UNSIGNED(R, length)); -- pragma label plus
end;
function "+"(L: SIGNED; R: SIGNED) return SIGNED is
-- pragma label_applies_to plus
-- synopsys subpgm_id 237
constant length: INTEGER := max(L'length, R'length);
begin
return plus(CONV_SIGNED(L, length),
CONV_SIGNED(R, length)); -- pragma label plus
end;
function "+"(L: UNSIGNED; R: SIGNED) return SIGNED is
-- pragma label_applies_to plus
-- synopsys subpgm_id 238
constant length: INTEGER := max(L'length + 1, R'length);
begin
return plus(CONV_SIGNED(L, length),
CONV_SIGNED(R, length)); -- pragma label plus
end;
function "+"(L: SIGNED; R: UNSIGNED) return SIGNED is
-- pragma label_applies_to plus
-- synopsys subpgm_id 239
constant length: INTEGER := max(L'length, R'length + 1);
begin
return plus(CONV_SIGNED(L, length),
CONV_SIGNED(R, length)); -- pragma label plus
end;
function "+"(L: UNSIGNED; R: INTEGER) return UNSIGNED is
-- pragma label_applies_to plus
-- synopsys subpgm_id 240
constant length: INTEGER := L'length + 1;
begin
return CONV_UNSIGNED(
plus( -- pragma label plus
CONV_SIGNED(L, length), CONV_SIGNED(R, length)), length-1);
end;
function "+"(L: INTEGER; R: UNSIGNED) return UNSIGNED is
-- pragma label_applies_to plus
-- synopsys subpgm_id 241
constant length: INTEGER := R'length + 1;
begin
return CONV_UNSIGNED(
plus( -- pragma label plus
CONV_SIGNED(L, length), CONV_SIGNED(R, length)), length-1);
end;
function "+"(L: SIGNED; R: INTEGER) return SIGNED is
-- pragma label_applies_to plus
-- synopsys subpgm_id 242
constant length: INTEGER := L'length;
begin
return plus(CONV_SIGNED(L, length),
CONV_SIGNED(R, length)); -- pragma label plus
end;
function "+"(L: INTEGER; R: SIGNED) return SIGNED is
-- pragma label_applies_to plus
-- synopsys subpgm_id 243
constant length: INTEGER := R'length;
begin
return plus(CONV_SIGNED(L, length),
CONV_SIGNED(R, length)); -- pragma label plus
end;
function "+"(L: UNSIGNED; R: STD_ULOGIC) return UNSIGNED is
-- pragma label_applies_to plus
-- synopsys subpgm_id 244
constant length: INTEGER := L'length;
begin
return unsigned_plus(CONV_UNSIGNED(L, length),
CONV_UNSIGNED(R, length)) ; -- pragma label plus
end;
function "+"(L: STD_ULOGIC; R: UNSIGNED) return UNSIGNED is
-- pragma label_applies_to plus
-- synopsys subpgm_id 245
constant length: INTEGER := R'length;
begin
return unsigned_plus(CONV_UNSIGNED(L, length),
CONV_UNSIGNED(R, length)); -- pragma label plus
end;
function "+"(L: SIGNED; R: STD_ULOGIC) return SIGNED is
-- pragma label_applies_to plus
-- synopsys subpgm_id 246
constant length: INTEGER := L'length;
begin
return plus(CONV_SIGNED(L, length),
CONV_SIGNED(R, length)); -- pragma label plus
end;
function "+"(L: STD_ULOGIC; R: SIGNED) return SIGNED is
-- pragma label_applies_to plus
-- synopsys subpgm_id 247
constant length: INTEGER := R'length;
begin
return plus(CONV_SIGNED(L, length),
CONV_SIGNED(R, length)); -- pragma label plus
end;
function "+"(L: UNSIGNED; R: UNSIGNED) return STD_LOGIC_VECTOR is
-- pragma label_applies_to plus
-- synopsys subpgm_id 260
constant length: INTEGER := max(L'length, R'length);
begin
return STD_LOGIC_VECTOR (
unsigned_plus(-- pragma label plus
CONV_UNSIGNED(L, length), CONV_UNSIGNED(R, length)));
end;
function "+"(L: SIGNED; R: SIGNED) return STD_LOGIC_VECTOR is
-- pragma label_applies_to plus
-- synopsys subpgm_id 261
constant length: INTEGER := max(L'length, R'length);
begin
return STD_LOGIC_VECTOR (
plus(-- pragma label plus
CONV_SIGNED(L, length), CONV_SIGNED(R, length)));
end;
function "+"(L: UNSIGNED; R: SIGNED) return STD_LOGIC_VECTOR is
-- pragma label_applies_to plus
-- synopsys subpgm_id 262
constant length: INTEGER := max(L'length + 1, R'length);
begin
return STD_LOGIC_VECTOR (
plus(-- pragma label plus
CONV_SIGNED(L, length), CONV_SIGNED(R, length)));
end;
function "+"(L: SIGNED; R: UNSIGNED) return STD_LOGIC_VECTOR is
-- pragma label_applies_to plus
-- synopsys subpgm_id 263
constant length: INTEGER := max(L'length, R'length + 1);
begin
return STD_LOGIC_VECTOR (
plus(-- pragma label plus
CONV_SIGNED(L, length), CONV_SIGNED(R, length)));
end;
function "+"(L: UNSIGNED; R: INTEGER) return STD_LOGIC_VECTOR is
-- pragma label_applies_to plus
-- synopsys subpgm_id 264
constant length: INTEGER := L'length + 1;
begin
return STD_LOGIC_VECTOR (CONV_UNSIGNED(
plus( -- pragma label plus
CONV_SIGNED(L, length), CONV_SIGNED(R, length)), length-1));
end;
function "+"(L: INTEGER; R: UNSIGNED) return STD_LOGIC_VECTOR is
-- pragma label_applies_to plus
-- synopsys subpgm_id 265
constant length: INTEGER := R'length + 1;
begin
return STD_LOGIC_VECTOR (CONV_UNSIGNED(
plus( -- pragma label plus
CONV_SIGNED(L, length), CONV_SIGNED(R, length)), length-1));
end;
function "+"(L: SIGNED; R: INTEGER) return STD_LOGIC_VECTOR is
-- pragma label_applies_to plus
-- synopsys subpgm_id 266
constant length: INTEGER := L'length;
begin
return STD_LOGIC_VECTOR (
plus(-- pragma label plus
CONV_SIGNED(L, length), CONV_SIGNED(R, length)));
end;
function "+"(L: INTEGER; R: SIGNED) return STD_LOGIC_VECTOR is
-- pragma label_applies_to plus
-- synopsys subpgm_id 267
constant length: INTEGER := R'length;
begin
return STD_LOGIC_VECTOR (
plus(-- pragma label plus
CONV_SIGNED(L, length), CONV_SIGNED(R, length)));
end;
function "+"(L: UNSIGNED; R: STD_ULOGIC) return STD_LOGIC_VECTOR is
-- pragma label_applies_to plus
-- synopsys subpgm_id 268
constant length: INTEGER := L'length;
begin
return STD_LOGIC_VECTOR (
unsigned_plus(-- pragma label plus
CONV_UNSIGNED(L, length), CONV_UNSIGNED(R, length))) ;
end;
function "+"(L: STD_ULOGIC; R: UNSIGNED) return STD_LOGIC_VECTOR is
-- pragma label_applies_to plus
-- synopsys subpgm_id 269
constant length: INTEGER := R'length;
begin
return STD_LOGIC_VECTOR (
unsigned_plus(-- pragma label plus
CONV_UNSIGNED(L, length), CONV_UNSIGNED(R, length)));
end;
function "+"(L: SIGNED; R: STD_ULOGIC) return STD_LOGIC_VECTOR is
-- pragma label_applies_to plus
-- synopsys subpgm_id 270
constant length: INTEGER := L'length;
begin
return STD_LOGIC_VECTOR (
plus(-- pragma label plus
CONV_SIGNED(L, length), CONV_SIGNED(R, length)));
end;
function "+"(L: STD_ULOGIC; R: SIGNED) return STD_LOGIC_VECTOR is
-- pragma label_applies_to plus
-- synopsys subpgm_id 271
constant length: INTEGER := R'length;
begin
return STD_LOGIC_VECTOR (
plus(-- pragma label plus
CONV_SIGNED(L, length), CONV_SIGNED(R, length)));
end;
function "-"(L: UNSIGNED; R: UNSIGNED) return UNSIGNED is
-- pragma label_applies_to minus
-- synopsys subpgm_id 248
constant length: INTEGER := max(L'length, R'length);
begin
return unsigned_minus(CONV_UNSIGNED(L, length),
CONV_UNSIGNED(R, length)); -- pragma label minus
end;
function "-"(L: SIGNED; R: SIGNED) return SIGNED is
-- pragma label_applies_to minus
-- synopsys subpgm_id 249
constant length: INTEGER := max(L'length, R'length);
begin
return minus(CONV_SIGNED(L, length),
CONV_SIGNED(R, length)); -- pragma label minus
end;
function "-"(L: UNSIGNED; R: SIGNED) return SIGNED is
-- pragma label_applies_to minus
-- synopsys subpgm_id 250
constant length: INTEGER := max(L'length + 1, R'length);
begin
return minus(CONV_SIGNED(L, length),
CONV_SIGNED(R, length)); -- pragma label minus
end;
function "-"(L: SIGNED; R: UNSIGNED) return SIGNED is
-- pragma label_applies_to minus
-- synopsys subpgm_id 251
constant length: INTEGER := max(L'length, R'length + 1);
begin
return minus(CONV_SIGNED(L, length),
CONV_SIGNED(R, length)); -- pragma label minus
end;
function "-"(L: UNSIGNED; R: INTEGER) return UNSIGNED is
-- pragma label_applies_to minus
-- synopsys subpgm_id 252
constant length: INTEGER := L'length + 1;
begin
return CONV_UNSIGNED(
minus( -- pragma label minus
CONV_SIGNED(L, length), CONV_SIGNED(R, length)), length-1);
end;
function "-"(L: INTEGER; R: UNSIGNED) return UNSIGNED is
-- pragma label_applies_to minus
-- synopsys subpgm_id 253
constant length: INTEGER := R'length + 1;
begin
return CONV_UNSIGNED(
minus( -- pragma label minus
CONV_SIGNED(L, length), CONV_SIGNED(R, length)), length-1);
end;
function "-"(L: SIGNED; R: INTEGER) return SIGNED is
-- pragma label_applies_to minus
-- synopsys subpgm_id 254
constant length: INTEGER := L'length;
begin
return minus(CONV_SIGNED(L, length),
CONV_SIGNED(R, length)); -- pragma label minus
end;
function "-"(L: INTEGER; R: SIGNED) return SIGNED is
-- pragma label_applies_to minus
-- synopsys subpgm_id 255
constant length: INTEGER := R'length;
begin
return minus(CONV_SIGNED(L, length),
CONV_SIGNED(R, length)); -- pragma label minus
end;
function "-"(L: UNSIGNED; R: STD_ULOGIC) return UNSIGNED is
-- pragma label_applies_to minus
-- synopsys subpgm_id 256
constant length: INTEGER := L'length + 1;
begin
return CONV_UNSIGNED(
minus( -- pragma label minus
CONV_SIGNED(L, length), CONV_SIGNED(R, length)), length-1);
end;
function "-"(L: STD_ULOGIC; R: UNSIGNED) return UNSIGNED is
-- pragma label_applies_to minus
-- synopsys subpgm_id 257
constant length: INTEGER := R'length + 1;
begin
return CONV_UNSIGNED(
minus( -- pragma label minus
CONV_SIGNED(L, length), CONV_SIGNED(R, length)), length-1);
end;
function "-"(L: SIGNED; R: STD_ULOGIC) return SIGNED is
-- pragma label_applies_to minus
-- synopsys subpgm_id 258
constant length: INTEGER := L'length;
begin
return minus(CONV_SIGNED(L, length),
CONV_SIGNED(R, length)); -- pragma label minus
end;
function "-"(L: STD_ULOGIC; R: SIGNED) return SIGNED is
-- pragma label_applies_to minus
-- synopsys subpgm_id 259
constant length: INTEGER := R'length;
begin
return minus(CONV_SIGNED(L, length),
CONV_SIGNED(R, length)); -- pragma label minus
end;
function "-"(L: UNSIGNED; R: UNSIGNED) return STD_LOGIC_VECTOR is
-- pragma label_applies_to minus
-- synopsys subpgm_id 272
constant length: INTEGER := max(L'length, R'length);
begin
return STD_LOGIC_VECTOR (
unsigned_minus(-- pragma label minus
CONV_UNSIGNED(L, length), CONV_UNSIGNED(R, length)));
end;
function "-"(L: SIGNED; R: SIGNED) return STD_LOGIC_VECTOR is
-- pragma label_applies_to minus
-- synopsys subpgm_id 273
constant length: INTEGER := max(L'length, R'length);
begin
return STD_LOGIC_VECTOR (
minus(-- pragma label minus
CONV_SIGNED(L, length), CONV_SIGNED(R, length)));
end;
function "-"(L: UNSIGNED; R: SIGNED) return STD_LOGIC_VECTOR is
-- pragma label_applies_to minus
-- synopsys subpgm_id 274
constant length: INTEGER := max(L'length + 1, R'length);
begin
return STD_LOGIC_VECTOR (
minus(-- pragma label minus
CONV_SIGNED(L, length), CONV_SIGNED(R, length)));
end;
function "-"(L: SIGNED; R: UNSIGNED) return STD_LOGIC_VECTOR is
-- pragma label_applies_to minus
-- synopsys subpgm_id 275
constant length: INTEGER := max(L'length, R'length + 1);
begin
return STD_LOGIC_VECTOR (
minus(-- pragma label minus
CONV_SIGNED(L, length), CONV_SIGNED(R, length)));
end;
function "-"(L: UNSIGNED; R: INTEGER) return STD_LOGIC_VECTOR is
-- pragma label_applies_to minus
-- synopsys subpgm_id 276
constant length: INTEGER := L'length + 1;
begin
return STD_LOGIC_VECTOR (CONV_UNSIGNED(
minus( -- pragma label minus
CONV_SIGNED(L, length), CONV_SIGNED(R, length)), length-1));
end;
function "-"(L: INTEGER; R: UNSIGNED) return STD_LOGIC_VECTOR is
-- pragma label_applies_to minus
-- synopsys subpgm_id 277
constant length: INTEGER := R'length + 1;
begin
return STD_LOGIC_VECTOR (CONV_UNSIGNED(
minus( -- pragma label minus
CONV_SIGNED(L, length), CONV_SIGNED(R, length)), length-1));
end;
function "-"(L: SIGNED; R: INTEGER) return STD_LOGIC_VECTOR is
-- pragma label_applies_to minus
-- synopsys subpgm_id 278
constant length: INTEGER := L'length;
begin
return STD_LOGIC_VECTOR (
minus(-- pragma label minus
CONV_SIGNED(L, length), CONV_SIGNED(R, length)));
end;
function "-"(L: INTEGER; R: SIGNED) return STD_LOGIC_VECTOR is
-- pragma label_applies_to minus
-- synopsys subpgm_id 279
constant length: INTEGER := R'length;
begin
return STD_LOGIC_VECTOR (
minus(-- pragma label minus
CONV_SIGNED(L, length), CONV_SIGNED(R, length)));
end;
function "-"(L: UNSIGNED; R: STD_ULOGIC) return STD_LOGIC_VECTOR is
-- pragma label_applies_to minus
-- synopsys subpgm_id 280
constant length: INTEGER := L'length + 1;
begin
return STD_LOGIC_VECTOR (CONV_UNSIGNED(
minus( -- pragma label minus
CONV_SIGNED(L, length), CONV_SIGNED(R, length)), length-1));
end;
function "-"(L: STD_ULOGIC; R: UNSIGNED) return STD_LOGIC_VECTOR is
-- pragma label_applies_to minus
-- synopsys subpgm_id 281
constant length: INTEGER := R'length + 1;
begin
return STD_LOGIC_VECTOR (CONV_UNSIGNED(
minus( -- pragma label minus
CONV_SIGNED(L, length), CONV_SIGNED(R, length)), length-1));
end;
function "-"(L: SIGNED; R: STD_ULOGIC) return STD_LOGIC_VECTOR is
-- pragma label_applies_to minus
-- synopsys subpgm_id 282
constant length: INTEGER := L'length;
begin
return STD_LOGIC_VECTOR (
minus(-- pragma label minus
CONV_SIGNED(L, length), CONV_SIGNED(R, length)));
end;
function "-"(L: STD_ULOGIC; R: SIGNED) return STD_LOGIC_VECTOR is
-- pragma label_applies_to minus
-- synopsys subpgm_id 283
constant length: INTEGER := R'length;
begin
return STD_LOGIC_VECTOR (
minus(-- pragma label minus
CONV_SIGNED(L, length), CONV_SIGNED(R, length)));
end;
function "+"(L: UNSIGNED) return UNSIGNED is
-- synopsys subpgm_id 284
begin
return L;
end;
function "+"(L: SIGNED) return SIGNED is
-- synopsys subpgm_id 285
begin
return L;
end;
function "-"(L: SIGNED) return SIGNED is
-- pragma label_applies_to minus
-- synopsys subpgm_id 286
begin
return 0 - L; -- pragma label minus
end;
function "ABS"(L: SIGNED) return SIGNED is
-- synopsys subpgm_id 287
begin
if (L(L'left) = '0' or L(L'left) = 'L') then
return L;
else
return 0 - L;
end if;
end;
function "+"(L: UNSIGNED) return STD_LOGIC_VECTOR is
-- synopsys subpgm_id 289
begin
return STD_LOGIC_VECTOR (L);
end;
function "+"(L: SIGNED) return STD_LOGIC_VECTOR is
-- synopsys subpgm_id 290
begin
return STD_LOGIC_VECTOR (L);
end;
function "-"(L: SIGNED) return STD_LOGIC_VECTOR is
-- pragma label_applies_to minus
-- synopsys subpgm_id 292
variable tmp: SIGNED(L'length-1 downto 0);
begin
tmp := 0 - L; -- pragma label minus
return STD_LOGIC_VECTOR (tmp);
end;
function "ABS"(L: SIGNED) return STD_LOGIC_VECTOR is
-- synopsys subpgm_id 294
variable tmp: SIGNED(L'length-1 downto 0);
begin
if (L(L'left) = '0' or L(L'left) = 'L') then
return STD_LOGIC_VECTOR (L);
else
tmp := 0 - L;
return STD_LOGIC_VECTOR (tmp);
end if;
end;
-- Type propagation function which returns the type BOOLEAN
function UNSIGNED_RETURN_BOOLEAN(A,B: UNSIGNED) return BOOLEAN is
variable Z: BOOLEAN;
-- pragma return_port_name Z
begin
return(Z);
end;
-- Type propagation function which returns the type BOOLEAN
function SIGNED_RETURN_BOOLEAN(A,B: SIGNED) return BOOLEAN is
variable Z: BOOLEAN;
-- pragma return_port_name Z
begin
return(Z);
end;
-- compare two signed numbers of the same length
-- both arrays must have range (msb downto 0)
function is_less(A, B: SIGNED) return BOOLEAN is
constant sign: INTEGER := A'left;
variable a_is_0, b_is_1, result : boolean;
-- pragma map_to_operator LT_TC_OP
-- pragma type_function SIGNED_RETURN_BOOLEAN
-- pragma return_port_name Z
begin
if A(sign) /= B(sign) then
result := A(sign) = '1';
else
result := FALSE;
for i in 0 to sign-1 loop
a_is_0 := A(i) = '0';
b_is_1 := B(i) = '1';
result := (a_is_0 and b_is_1) or
(a_is_0 and result) or
(b_is_1 and result);
end loop;
end if;
return result;
end;
-- compare two signed numbers of the same length
-- both arrays must have range (msb downto 0)
function is_less_or_equal(A, B: SIGNED) return BOOLEAN is
constant sign: INTEGER := A'left;
variable a_is_0, b_is_1, result : boolean;
-- pragma map_to_operator LEQ_TC_OP
-- pragma type_function SIGNED_RETURN_BOOLEAN
-- pragma return_port_name Z
begin
if A(sign) /= B(sign) then
result := A(sign) = '1';
else
result := TRUE;
for i in 0 to sign-1 loop
a_is_0 := A(i) = '0';
b_is_1 := B(i) = '1';
result := (a_is_0 and b_is_1) or
(a_is_0 and result) or
(b_is_1 and result);
end loop;
end if;
return result;
end;
-- compare two unsigned numbers of the same length
-- both arrays must have range (msb downto 0)
function unsigned_is_less(A, B: UNSIGNED) return BOOLEAN is
constant sign: INTEGER := A'left;
variable a_is_0, b_is_1, result : boolean;
-- pragma map_to_operator LT_UNS_OP
-- pragma type_function UNSIGNED_RETURN_BOOLEAN
-- pragma return_port_name Z
begin
result := FALSE;
for i in 0 to sign loop
a_is_0 := A(i) = '0';
b_is_1 := B(i) = '1';
result := (a_is_0 and b_is_1) or
(a_is_0 and result) or
(b_is_1 and result);
end loop;
return result;
end;
-- compare two unsigned numbers of the same length
-- both arrays must have range (msb downto 0)
function unsigned_is_less_or_equal(A, B: UNSIGNED) return BOOLEAN is
constant sign: INTEGER := A'left;
variable a_is_0, b_is_1, result : boolean;
-- pragma map_to_operator LEQ_UNS_OP
-- pragma type_function UNSIGNED_RETURN_BOOLEAN
-- pragma return_port_name Z
begin
result := TRUE;
for i in 0 to sign loop
a_is_0 := A(i) = '0';
b_is_1 := B(i) = '1';
result := (a_is_0 and b_is_1) or
(a_is_0 and result) or
(b_is_1 and result);
end loop;
return result;
end;
function "<"(L: UNSIGNED; R: UNSIGNED) return BOOLEAN is
-- pragma label_applies_to lt
-- synopsys subpgm_id 305
constant length: INTEGER := max(L'length, R'length);
begin
return unsigned_is_less(CONV_UNSIGNED(L, length),
CONV_UNSIGNED(R, length)); -- pragma label lt
end;
function "<"(L: SIGNED; R: SIGNED) return BOOLEAN is
-- pragma label_applies_to lt
-- synopsys subpgm_id 306
constant length: INTEGER := max(L'length, R'length);
begin
return is_less(CONV_SIGNED(L, length),
CONV_SIGNED(R, length)); -- pragma label lt
end;
function "<"(L: UNSIGNED; R: SIGNED) return BOOLEAN is
-- pragma label_applies_to lt
-- synopsys subpgm_id 307
constant length: INTEGER := max(L'length + 1, R'length);
begin
return is_less(CONV_SIGNED(L, length),
CONV_SIGNED(R, length)); -- pragma label lt
end;
function "<"(L: SIGNED; R: UNSIGNED) return BOOLEAN is
-- pragma label_applies_to lt
-- synopsys subpgm_id 308
constant length: INTEGER := max(L'length, R'length + 1);
begin
return is_less(CONV_SIGNED(L, length),
CONV_SIGNED(R, length)); -- pragma label lt
end;
function "<"(L: UNSIGNED; R: INTEGER) return BOOLEAN is
-- pragma label_applies_to lt
-- synopsys subpgm_id 309
constant length: INTEGER := L'length + 1;
begin
return is_less(CONV_SIGNED(L, length),
CONV_SIGNED(R, length)); -- pragma label lt
end;
function "<"(L: INTEGER; R: UNSIGNED) return BOOLEAN is
-- pragma label_applies_to lt
-- synopsys subpgm_id 310
constant length: INTEGER := R'length + 1;
begin
return is_less(CONV_SIGNED(L, length),
CONV_SIGNED(R, length)); -- pragma label lt
end;
function "<"(L: SIGNED; R: INTEGER) return BOOLEAN is
-- pragma label_applies_to lt
-- synopsys subpgm_id 311
constant length: INTEGER := L'length;
begin
return is_less(CONV_SIGNED(L, length),
CONV_SIGNED(R, length)); -- pragma label lt
end;
function "<"(L: INTEGER; R: SIGNED) return BOOLEAN is
-- pragma label_applies_to lt
-- synopsys subpgm_id 312
constant length: INTEGER := R'length;
begin
return is_less(CONV_SIGNED(L, length),
CONV_SIGNED(R, length)); -- pragma label lt
end;
function "<="(L: UNSIGNED; R: UNSIGNED) return BOOLEAN is
-- pragma label_applies_to leq
-- synopsys subpgm_id 314
constant length: INTEGER := max(L'length, R'length);
begin
return unsigned_is_less_or_equal(CONV_UNSIGNED(L, length),
CONV_UNSIGNED(R, length)); -- pragma label leq
end;
function "<="(L: SIGNED; R: SIGNED) return BOOLEAN is
-- pragma label_applies_to leq
-- synopsys subpgm_id 315
constant length: INTEGER := max(L'length, R'length);
begin
return is_less_or_equal(CONV_SIGNED(L, length),
CONV_SIGNED(R, length)); -- pragma label leq
end;
function "<="(L: UNSIGNED; R: SIGNED) return BOOLEAN is
-- pragma label_applies_to leq
-- synopsys subpgm_id 316
constant length: INTEGER := max(L'length + 1, R'length);
begin
return is_less_or_equal(CONV_SIGNED(L, length),
CONV_SIGNED(R, length)); -- pragma label leq
end;
function "<="(L: SIGNED; R: UNSIGNED) return BOOLEAN is
-- pragma label_applies_to leq
-- synopsys subpgm_id 317
constant length: INTEGER := max(L'length, R'length + 1);
begin
return is_less_or_equal(CONV_SIGNED(L, length),
CONV_SIGNED(R, length)); -- pragma label leq
end;
function "<="(L: UNSIGNED; R: INTEGER) return BOOLEAN is
-- pragma label_applies_to leq
-- synopsys subpgm_id 318
constant length: INTEGER := L'length + 1;
begin
return is_less_or_equal(CONV_SIGNED(L, length),
CONV_SIGNED(R, length)); -- pragma label leq
end;
function "<="(L: INTEGER; R: UNSIGNED) return BOOLEAN is
-- pragma label_applies_to leq
-- synopsys subpgm_id 319
constant length: INTEGER := R'length + 1;
begin
return is_less_or_equal(CONV_SIGNED(L, length),
CONV_SIGNED(R, length)); -- pragma label leq
end;
function "<="(L: SIGNED; R: INTEGER) return BOOLEAN is
-- pragma label_applies_to leq
-- synopsys subpgm_id 320
constant length: INTEGER := L'length;
begin
return is_less_or_equal(CONV_SIGNED(L, length),
CONV_SIGNED(R, length)); -- pragma label leq
end;
function "<="(L: INTEGER; R: SIGNED) return BOOLEAN is
-- pragma label_applies_to leq
-- synopsys subpgm_id 321
constant length: INTEGER := R'length;
begin
return is_less_or_equal(CONV_SIGNED(L, length),
CONV_SIGNED(R, length)); -- pragma label leq
end;
function ">"(L: UNSIGNED; R: UNSIGNED) return BOOLEAN is
-- pragma label_applies_to gt
-- synopsys subpgm_id 323
constant length: INTEGER := max(L'length, R'length);
begin
return unsigned_is_less(CONV_UNSIGNED(R, length),
CONV_UNSIGNED(L, length)); -- pragma label gt
end;
function ">"(L: SIGNED; R: SIGNED) return BOOLEAN is
-- pragma label_applies_to gt
-- synopsys subpgm_id 324
constant length: INTEGER := max(L'length, R'length);
begin
return is_less(CONV_SIGNED(R, length),
CONV_SIGNED(L, length)); -- pragma label gt
end;
function ">"(L: UNSIGNED; R: SIGNED) return BOOLEAN is
-- pragma label_applies_to gt
-- synopsys subpgm_id 325
constant length: INTEGER := max(L'length + 1, R'length);
begin
return is_less(CONV_SIGNED(R, length),
CONV_SIGNED(L, length)); -- pragma label gt
end;
function ">"(L: SIGNED; R: UNSIGNED) return BOOLEAN is
-- pragma label_applies_to gt
-- synopsys subpgm_id 326
constant length: INTEGER := max(L'length, R'length + 1);
begin
return is_less(CONV_SIGNED(R, length),
CONV_SIGNED(L, length)); -- pragma label gt
end;
function ">"(L: UNSIGNED; R: INTEGER) return BOOLEAN is
-- pragma label_applies_to gt
-- synopsys subpgm_id 327
constant length: INTEGER := L'length + 1;
begin
return is_less(CONV_SIGNED(R, length),
CONV_SIGNED(L, length)); -- pragma label gt
end;
function ">"(L: INTEGER; R: UNSIGNED) return BOOLEAN is
-- pragma label_applies_to gt
-- synopsys subpgm_id 328
constant length: INTEGER := R'length + 1;
begin
return is_less(CONV_SIGNED(R, length),
CONV_SIGNED(L, length)); -- pragma label gt
end;
function ">"(L: SIGNED; R: INTEGER) return BOOLEAN is
-- pragma label_applies_to gt
-- synopsys subpgm_id 329
constant length: INTEGER := L'length;
begin
return is_less(CONV_SIGNED(R, length),
CONV_SIGNED(L, length)); -- pragma label gt
end;
function ">"(L: INTEGER; R: SIGNED) return BOOLEAN is
-- pragma label_applies_to gt
-- synopsys subpgm_id 330
constant length: INTEGER := R'length;
begin
return is_less(CONV_SIGNED(R, length),
CONV_SIGNED(L, length)); -- pragma label gt
end;
function ">="(L: UNSIGNED; R: UNSIGNED) return BOOLEAN is
-- pragma label_applies_to geq
-- synopsys subpgm_id 332
constant length: INTEGER := max(L'length, R'length);
begin
return unsigned_is_less_or_equal(CONV_UNSIGNED(R, length),
CONV_UNSIGNED(L, length)); -- pragma label geq
end;
function ">="(L: SIGNED; R: SIGNED) return BOOLEAN is
-- pragma label_applies_to geq
-- synopsys subpgm_id 333
constant length: INTEGER := max(L'length, R'length);
begin
return is_less_or_equal(CONV_SIGNED(R, length),
CONV_SIGNED(L, length)); -- pragma label geq
end;
function ">="(L: UNSIGNED; R: SIGNED) return BOOLEAN is
-- pragma label_applies_to geq
-- synopsys subpgm_id 334
constant length: INTEGER := max(L'length + 1, R'length);
begin
return is_less_or_equal(CONV_SIGNED(R, length),
CONV_SIGNED(L, length)); -- pragma label geq
end;
function ">="(L: SIGNED; R: UNSIGNED) return BOOLEAN is
-- pragma label_applies_to geq
-- synopsys subpgm_id 335
constant length: INTEGER := max(L'length, R'length + 1);
begin
return is_less_or_equal(CONV_SIGNED(R, length),
CONV_SIGNED(L, length)); -- pragma label geq
end;
function ">="(L: UNSIGNED; R: INTEGER) return BOOLEAN is
-- pragma label_applies_to geq
-- synopsys subpgm_id 336
constant length: INTEGER := L'length + 1;
begin
return is_less_or_equal(CONV_SIGNED(R, length),
CONV_SIGNED(L, length)); -- pragma label geq
end;
function ">="(L: INTEGER; R: UNSIGNED) return BOOLEAN is
-- pragma label_applies_to geq
-- synopsys subpgm_id 337
constant length: INTEGER := R'length + 1;
begin
return is_less_or_equal(CONV_SIGNED(R, length),
CONV_SIGNED(L, length)); -- pragma label geq
end;
function ">="(L: SIGNED; R: INTEGER) return BOOLEAN is
-- pragma label_applies_to geq
-- synopsys subpgm_id 338
constant length: INTEGER := L'length;
begin
return is_less_or_equal(CONV_SIGNED(R, length),
CONV_SIGNED(L, length)); -- pragma label geq
end;
function ">="(L: INTEGER; R: SIGNED) return BOOLEAN is
-- pragma label_applies_to geq
-- synopsys subpgm_id 339
constant length: INTEGER := R'length;
begin
return is_less_or_equal(CONV_SIGNED(R, length),
CONV_SIGNED(L, length)); -- pragma label geq
end;
-- for internal use only. Assumes SIGNED arguments of equal length.
function bitwise_eql(L: STD_ULOGIC_VECTOR; R: STD_ULOGIC_VECTOR)
return BOOLEAN is
-- pragma built_in SYN_EQL
begin
for i in L'range loop
if L(i) /= R(i) then
return FALSE;
end if;
end loop;
return TRUE;
end;
-- for internal use only. Assumes SIGNED arguments of equal length.
function bitwise_neq(L: STD_ULOGIC_VECTOR; R: STD_ULOGIC_VECTOR)
return BOOLEAN is
-- pragma built_in SYN_NEQ
begin
for i in L'range loop
if L(i) /= R(i) then
return TRUE;
end if;
end loop;
return FALSE;
end;
function "="(L: UNSIGNED; R: UNSIGNED) return BOOLEAN is
-- synopsys subpgm_id 341
constant length: INTEGER := max(L'length, R'length);
begin
return bitwise_eql( STD_ULOGIC_VECTOR( CONV_UNSIGNED(L, length) ),
STD_ULOGIC_VECTOR( CONV_UNSIGNED(R, length) ) );
end;
function "="(L: SIGNED; R: SIGNED) return BOOLEAN is
-- synopsys subpgm_id 342
constant length: INTEGER := max(L'length, R'length);
begin
return bitwise_eql( STD_ULOGIC_VECTOR( CONV_SIGNED(L, length) ),
STD_ULOGIC_VECTOR( CONV_SIGNED(R, length) ) );
end;
function "="(L: UNSIGNED; R: SIGNED) return BOOLEAN is
-- synopsys subpgm_id 343
constant length: INTEGER := max(L'length + 1, R'length);
begin
return bitwise_eql( STD_ULOGIC_VECTOR( CONV_SIGNED(L, length) ),
STD_ULOGIC_VECTOR( CONV_SIGNED(R, length) ) );
end;
function "="(L: SIGNED; R: UNSIGNED) return BOOLEAN is
-- synopsys subpgm_id 344
constant length: INTEGER := max(L'length, R'length + 1);
begin
return bitwise_eql( STD_ULOGIC_VECTOR( CONV_SIGNED(L, length) ),
STD_ULOGIC_VECTOR( CONV_SIGNED(R, length) ) );
end;
function "="(L: UNSIGNED; R: INTEGER) return BOOLEAN is
-- synopsys subpgm_id 345
constant length: INTEGER := L'length + 1;
begin
return bitwise_eql( STD_ULOGIC_VECTOR( CONV_SIGNED(L, length) ),
STD_ULOGIC_VECTOR( CONV_SIGNED(R, length) ) );
end;
function "="(L: INTEGER; R: UNSIGNED) return BOOLEAN is
-- synopsys subpgm_id 346
constant length: INTEGER := R'length + 1;
begin
return bitwise_eql( STD_ULOGIC_VECTOR( CONV_SIGNED(L, length) ),
STD_ULOGIC_VECTOR( CONV_SIGNED(R, length) ) );
end;
function "="(L: SIGNED; R: INTEGER) return BOOLEAN is
-- synopsys subpgm_id 347
constant length: INTEGER := L'length;
begin
return bitwise_eql( STD_ULOGIC_VECTOR( CONV_SIGNED(L, length) ),
STD_ULOGIC_VECTOR( CONV_SIGNED(R, length) ) );
end;
function "="(L: INTEGER; R: SIGNED) return BOOLEAN is
-- synopsys subpgm_id 348
constant length: INTEGER := R'length;
begin
return bitwise_eql( STD_ULOGIC_VECTOR( CONV_SIGNED(L, length) ),
STD_ULOGIC_VECTOR( CONV_SIGNED(R, length) ) );
end;
function "/="(L: UNSIGNED; R: UNSIGNED) return BOOLEAN is
-- synopsys subpgm_id 350
constant length: INTEGER := max(L'length, R'length);
begin
return bitwise_neq( STD_ULOGIC_VECTOR( CONV_UNSIGNED(L, length) ),
STD_ULOGIC_VECTOR( CONV_UNSIGNED(R, length) ) );
end;
function "/="(L: SIGNED; R: SIGNED) return BOOLEAN is
-- synopsys subpgm_id 351
constant length: INTEGER := max(L'length, R'length);
begin
return bitwise_neq( STD_ULOGIC_VECTOR( CONV_SIGNED(L, length) ),
STD_ULOGIC_VECTOR( CONV_SIGNED(R, length) ) );
end;
function "/="(L: UNSIGNED; R: SIGNED) return BOOLEAN is
-- synopsys subpgm_id 352
constant length: INTEGER := max(L'length + 1, R'length);
begin
return bitwise_neq( STD_ULOGIC_VECTOR( CONV_SIGNED(L, length) ),
STD_ULOGIC_VECTOR( CONV_SIGNED(R, length) ) );
end;
function "/="(L: SIGNED; R: UNSIGNED) return BOOLEAN is
-- synopsys subpgm_id 353
constant length: INTEGER := max(L'length, R'length + 1);
begin
return bitwise_neq( STD_ULOGIC_VECTOR( CONV_SIGNED(L, length) ),
STD_ULOGIC_VECTOR( CONV_SIGNED(R, length) ) );
end;
function "/="(L: UNSIGNED; R: INTEGER) return BOOLEAN is
-- synopsys subpgm_id 354
constant length: INTEGER := L'length + 1;
begin
return bitwise_neq( STD_ULOGIC_VECTOR( CONV_SIGNED(L, length) ),
STD_ULOGIC_VECTOR( CONV_SIGNED(R, length) ) );
end;
function "/="(L: INTEGER; R: UNSIGNED) return BOOLEAN is
-- synopsys subpgm_id 355
constant length: INTEGER := R'length + 1;
begin
return bitwise_neq( STD_ULOGIC_VECTOR( CONV_SIGNED(L, length) ),
STD_ULOGIC_VECTOR( CONV_SIGNED(R, length) ) );
end;
function "/="(L: SIGNED; R: INTEGER) return BOOLEAN is
-- synopsys subpgm_id 356
constant length: INTEGER := L'length;
begin
return bitwise_neq( STD_ULOGIC_VECTOR( CONV_SIGNED(L, length) ),
STD_ULOGIC_VECTOR( CONV_SIGNED(R, length) ) );
end;
function "/="(L: INTEGER; R: SIGNED) return BOOLEAN is
-- synopsys subpgm_id 357
constant length: INTEGER := R'length;
begin
return bitwise_neq( STD_ULOGIC_VECTOR( CONV_SIGNED(L, length) ),
STD_ULOGIC_VECTOR( CONV_SIGNED(R, length) ) );
end;
function SHL(ARG: UNSIGNED; COUNT: UNSIGNED) return UNSIGNED is
-- synopsys subpgm_id 358
constant control_msb: INTEGER := COUNT'length - 1;
variable control: UNSIGNED (control_msb downto 0);
constant result_msb: INTEGER := ARG'length-1;
subtype rtype is UNSIGNED (result_msb downto 0);
variable result, temp: rtype;
begin
control := MAKE_BINARY(COUNT);
-- synopsys synthesis_off
if (control(0) = 'X') then
result := rtype'(others => 'X');
return result;
end if;
-- synopsys synthesis_on
result := ARG;
for i in 0 to control_msb loop
if control(i) = '1' then
temp := rtype'(others => '0');
if 2**i <= result_msb then
temp(result_msb downto 2**i) :=
result(result_msb - 2**i downto 0);
end if;
result := temp;
end if;
end loop;
return result;
end;
function SHL(ARG: SIGNED; COUNT: UNSIGNED) return SIGNED is
-- synopsys subpgm_id 359
constant control_msb: INTEGER := COUNT'length - 1;
variable control: UNSIGNED (control_msb downto 0);
constant result_msb: INTEGER := ARG'length-1;
subtype rtype is SIGNED (result_msb downto 0);
variable result, temp: rtype;
begin
control := MAKE_BINARY(COUNT);
-- synopsys synthesis_off
if (control(0) = 'X') then
result := rtype'(others => 'X');
return result;
end if;
-- synopsys synthesis_on
result := ARG;
for i in 0 to control_msb loop
if control(i) = '1' then
temp := rtype'(others => '0');
if 2**i <= result_msb then
temp(result_msb downto 2**i) :=
result(result_msb - 2**i downto 0);
end if;
result := temp;
end if;
end loop;
return result;
end;
function SHR(ARG: UNSIGNED; COUNT: UNSIGNED) return UNSIGNED is
-- synopsys subpgm_id 360
constant control_msb: INTEGER := COUNT'length - 1;
variable control: UNSIGNED (control_msb downto 0);
constant result_msb: INTEGER := ARG'length-1;
subtype rtype is UNSIGNED (result_msb downto 0);
variable result, temp: rtype;
begin
control := MAKE_BINARY(COUNT);
-- synopsys synthesis_off
if (control(0) = 'X') then
result := rtype'(others => 'X');
return result;
end if;
-- synopsys synthesis_on
result := ARG;
for i in 0 to control_msb loop
if control(i) = '1' then
temp := rtype'(others => '0');
if 2**i <= result_msb then
temp(result_msb - 2**i downto 0) :=
result(result_msb downto 2**i);
end if;
result := temp;
end if;
end loop;
return result;
end;
function SHR(ARG: SIGNED; COUNT: UNSIGNED) return SIGNED is
-- synopsys subpgm_id 361
constant control_msb: INTEGER := COUNT'length - 1;
variable control: UNSIGNED (control_msb downto 0);
constant result_msb: INTEGER := ARG'length-1;
subtype rtype is SIGNED (result_msb downto 0);
variable result, temp: rtype;
variable sign_bit: STD_ULOGIC;
begin
control := MAKE_BINARY(COUNT);
-- synopsys synthesis_off
if (control(0) = 'X') then
result := rtype'(others => 'X');
return result;
end if;
-- synopsys synthesis_on
result := ARG;
sign_bit := ARG(ARG'left);
for i in 0 to control_msb loop
if control(i) = '1' then
temp := rtype'(others => sign_bit);
if 2**i <= result_msb then
temp(result_msb - 2**i downto 0) :=
result(result_msb downto 2**i);
end if;
result := temp;
end if;
end loop;
return result;
end;
function CONV_INTEGER(ARG: INTEGER) return INTEGER is
-- synopsys subpgm_id 365
begin
return ARG;
end;
function CONV_INTEGER(ARG: UNSIGNED) return INTEGER is
variable result: INTEGER;
variable tmp: STD_ULOGIC;
-- synopsys built_in SYN_UNSIGNED_TO_INTEGER
-- synopsys subpgm_id 366
begin
-- synopsys synthesis_off
assert ARG'length <= 31
report "ARG is too large in CONV_INTEGER"
severity FAILURE;
result := 0;
for i in ARG'range loop
result := result * 2;
tmp := tbl_BINARY(ARG(i));
if tmp = '1' then
result := result + 1;
elsif tmp = 'X' then
assert false
report "CONV_INTEGER: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, and it has been converted to 0."
severity WARNING;
end if;
end loop;
return result;
-- synopsys synthesis_on
end;
function CONV_INTEGER(ARG: SIGNED) return INTEGER is
variable result: INTEGER;
variable tmp: STD_ULOGIC;
-- synopsys built_in SYN_SIGNED_TO_INTEGER
-- synopsys subpgm_id 367
begin
-- synopsys synthesis_off
assert ARG'length <= 32
report "ARG is too large in CONV_INTEGER"
severity FAILURE;
result := 0;
for i in ARG'range loop
if i /= ARG'left then
result := result * 2;
tmp := tbl_BINARY(ARG(i));
if tmp = '1' then
result := result + 1;
elsif tmp = 'X' then
assert false
report "CONV_INTEGER: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, and it has been converted to 0."
severity WARNING;
end if;
end if;
end loop;
tmp := MAKE_BINARY(ARG(ARG'left));
if tmp = '1' then
if ARG'length = 32 then
result := (result - 2**30) - 2**30;
else
result := result - (2 ** (ARG'length-1));
end if;
end if;
return result;
-- synopsys synthesis_on
end;
function CONV_INTEGER(ARG: STD_ULOGIC) return SMALL_INT is
variable tmp: STD_ULOGIC;
-- synopsys built_in SYN_FEED_THRU
-- synopsys subpgm_id 370
begin
-- synopsys synthesis_off
tmp := tbl_BINARY(ARG);
if tmp = '1' then
return 1;
elsif tmp = 'X' then
assert false
report "CONV_INTEGER: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, and it has been converted to 0."
severity WARNING;
return 0;
else
return 0;
end if;
-- synopsys synthesis_on
end;
-- convert an integer to a unsigned STD_ULOGIC_VECTOR
function CONV_UNSIGNED(ARG: INTEGER; SIZE: INTEGER) return UNSIGNED is
variable result: UNSIGNED(SIZE-1 downto 0);
variable temp: integer;
-- synopsys built_in SYN_INTEGER_TO_UNSIGNED
-- synopsys subpgm_id 371
begin
-- synopsys synthesis_off
temp := ARG;
for i in 0 to SIZE-1 loop
if (temp mod 2) = 1 then
result(i) := '1';
else
result(i) := '0';
end if;
if temp > 0 then
temp := temp / 2;
else
temp := (temp - 1) / 2; -- simulate ASR
end if;
end loop;
return result;
-- synopsys synthesis_on
end;
function CONV_UNSIGNED(ARG: UNSIGNED; SIZE: INTEGER) return UNSIGNED is
constant msb: INTEGER := min(ARG'length, SIZE) - 1;
subtype rtype is UNSIGNED (SIZE-1 downto 0);
variable new_bounds: UNSIGNED (ARG'length-1 downto 0);
variable result: rtype;
-- synopsys built_in SYN_ZERO_EXTEND
-- synopsys subpgm_id 372
begin
-- synopsys synthesis_off
new_bounds := MAKE_BINARY(ARG);
if (new_bounds(0) = 'X') then
result := rtype'(others => 'X');
return result;
end if;
result := rtype'(others => '0');
result(msb downto 0) := new_bounds(msb downto 0);
return result;
-- synopsys synthesis_on
end;
function CONV_UNSIGNED(ARG: SIGNED; SIZE: INTEGER) return UNSIGNED is
constant msb: INTEGER := min(ARG'length, SIZE) - 1;
subtype rtype is UNSIGNED (SIZE-1 downto 0);
variable new_bounds: UNSIGNED (ARG'length-1 downto 0);
variable result: rtype;
-- synopsys built_in SYN_SIGN_EXTEND
-- synopsys subpgm_id 373
begin
-- synopsys synthesis_off
new_bounds := MAKE_BINARY(ARG);
if (new_bounds(0) = 'X') then
result := rtype'(others => 'X');
return result;
end if;
result := rtype'(others => new_bounds(new_bounds'left));
result(msb downto 0) := new_bounds(msb downto 0);
return result;
-- synopsys synthesis_on
end;
function CONV_UNSIGNED(ARG: STD_ULOGIC; SIZE: INTEGER) return UNSIGNED is
subtype rtype is UNSIGNED (SIZE-1 downto 0);
variable result: rtype;
-- synopsys built_in SYN_ZERO_EXTEND
-- synopsys subpgm_id 375
begin
-- synopsys synthesis_off
result := rtype'(others => '0');
result(0) := MAKE_BINARY(ARG);
if (result(0) = 'X') then
result := rtype'(others => 'X');
end if;
return result;
-- synopsys synthesis_on
end;
-- convert an integer to a 2's complement STD_ULOGIC_VECTOR
function CONV_SIGNED(ARG: INTEGER; SIZE: INTEGER) return SIGNED is
variable result: SIGNED (SIZE-1 downto 0);
variable temp: integer;
-- synopsys built_in SYN_INTEGER_TO_SIGNED
-- synopsys subpgm_id 376
begin
-- synopsys synthesis_off
temp := ARG;
for i in 0 to SIZE-1 loop
if (temp mod 2) = 1 then
result(i) := '1';
else
result(i) := '0';
end if;
if temp > 0 then
temp := temp / 2;
elsif (temp > integer'low) then
temp := (temp - 1) / 2; -- simulate ASR
else
temp := temp / 2; -- simulate ASR
end if;
end loop;
return result;
-- synopsys synthesis_on
end;
function CONV_SIGNED(ARG: UNSIGNED; SIZE: INTEGER) return SIGNED is
constant msb: INTEGER := min(ARG'length, SIZE) - 1;
subtype rtype is SIGNED (SIZE-1 downto 0);
variable new_bounds : SIGNED (ARG'length-1 downto 0);
variable result: rtype;
-- synopsys built_in SYN_ZERO_EXTEND
-- synopsys subpgm_id 377
begin
-- synopsys synthesis_off
new_bounds := MAKE_BINARY(ARG);
if (new_bounds(0) = 'X') then
result := rtype'(others => 'X');
return result;
end if;
result := rtype'(others => '0');
result(msb downto 0) := new_bounds(msb downto 0);
return result;
-- synopsys synthesis_on
end;
function CONV_SIGNED(ARG: SIGNED; SIZE: INTEGER) return SIGNED is
constant msb: INTEGER := min(ARG'length, SIZE) - 1;
subtype rtype is SIGNED (SIZE-1 downto 0);
variable new_bounds : SIGNED (ARG'length-1 downto 0);
variable result: rtype;
-- synopsys built_in SYN_SIGN_EXTEND
-- synopsys subpgm_id 378
begin
-- synopsys synthesis_off
new_bounds := MAKE_BINARY(ARG);
if (new_bounds(0) = 'X') then
result := rtype'(others => 'X');
return result;
end if;
result := rtype'(others => new_bounds(new_bounds'left));
result(msb downto 0) := new_bounds(msb downto 0);
return result;
-- synopsys synthesis_on
end;
function CONV_SIGNED(ARG: STD_ULOGIC; SIZE: INTEGER) return SIGNED is
subtype rtype is SIGNED (SIZE-1 downto 0);
variable result: rtype;
-- synopsys built_in SYN_ZERO_EXTEND
-- synopsys subpgm_id 380
begin
-- synopsys synthesis_off
result := rtype'(others => '0');
result(0) := MAKE_BINARY(ARG);
if (result(0) = 'X') then
result := rtype'(others => 'X');
end if;
return result;
-- synopsys synthesis_on
end;
-- convert an integer to an STD_LOGIC_VECTOR
function CONV_STD_LOGIC_VECTOR(ARG: INTEGER; SIZE: INTEGER) return STD_LOGIC_VECTOR is
variable result: STD_LOGIC_VECTOR (SIZE-1 downto 0);
variable temp: integer;
-- synopsys built_in SYN_INTEGER_TO_SIGNED
-- synopsys subpgm_id 381
begin
-- synopsys synthesis_off
temp := ARG;
for i in 0 to SIZE-1 loop
if (temp mod 2) = 1 then
result(i) := '1';
else
result(i) := '0';
end if;
if temp > 0 then
temp := temp / 2;
elsif (temp > integer'low) then
temp := (temp - 1) / 2; -- simulate ASR
else
temp := temp / 2; -- simulate ASR
end if;
end loop;
return result;
-- synopsys synthesis_on
end;
function CONV_STD_LOGIC_VECTOR(ARG: UNSIGNED; SIZE: INTEGER) return STD_LOGIC_VECTOR is
constant msb: INTEGER := min(ARG'length, SIZE) - 1;
subtype rtype is STD_LOGIC_VECTOR (SIZE-1 downto 0);
variable new_bounds : STD_LOGIC_VECTOR (ARG'length-1 downto 0);
variable result: rtype;
-- synopsys built_in SYN_ZERO_EXTEND
-- synopsys subpgm_id 382
begin
-- synopsys synthesis_off
new_bounds := MAKE_BINARY(ARG);
if (new_bounds(0) = 'X') then
result := rtype'(others => 'X');
return result;
end if;
result := rtype'(others => '0');
result(msb downto 0) := new_bounds(msb downto 0);
return result;
-- synopsys synthesis_on
end;
function CONV_STD_LOGIC_VECTOR(ARG: SIGNED; SIZE: INTEGER) return STD_LOGIC_VECTOR is
constant msb: INTEGER := min(ARG'length, SIZE) - 1;
subtype rtype is STD_LOGIC_VECTOR (SIZE-1 downto 0);
variable new_bounds : STD_LOGIC_VECTOR (ARG'length-1 downto 0);
variable result: rtype;
-- synopsys built_in SYN_SIGN_EXTEND
-- synopsys subpgm_id 383
begin
-- synopsys synthesis_off
new_bounds := MAKE_BINARY(ARG);
if (new_bounds(0) = 'X') then
result := rtype'(others => 'X');
return result;
end if;
result := rtype'(others => new_bounds(new_bounds'left));
result(msb downto 0) := new_bounds(msb downto 0);
return result;
-- synopsys synthesis_on
end;
function CONV_STD_LOGIC_VECTOR(ARG: STD_ULOGIC; SIZE: INTEGER) return STD_LOGIC_VECTOR is
subtype rtype is STD_LOGIC_VECTOR (SIZE-1 downto 0);
variable result: rtype;
-- synopsys built_in SYN_ZERO_EXTEND
-- synopsys subpgm_id 384
begin
-- synopsys synthesis_off
result := rtype'(others => '0');
result(0) := MAKE_BINARY(ARG);
if (result(0) = 'X') then
result := rtype'(others => 'X');
end if;
return result;
-- synopsys synthesis_on
end;
function EXT(ARG: STD_LOGIC_VECTOR; SIZE: INTEGER)
return STD_LOGIC_VECTOR is
constant msb: INTEGER := min(ARG'length, SIZE) - 1;
subtype rtype is STD_LOGIC_VECTOR (SIZE-1 downto 0);
variable new_bounds: STD_LOGIC_VECTOR (ARG'length-1 downto 0);
variable result: rtype;
-- synopsys built_in SYN_ZERO_EXTEND
-- synopsys subpgm_id 385
begin
-- synopsys synthesis_off
new_bounds := MAKE_BINARY(ARG);
if (new_bounds(0) = 'X') then
result := rtype'(others => 'X');
return result;
end if;
result := rtype'(others => '0');
result(msb downto 0) := new_bounds(msb downto 0);
return result;
-- synopsys synthesis_on
end;
function SXT(ARG: STD_LOGIC_VECTOR; SIZE: INTEGER) return STD_LOGIC_VECTOR is
constant msb: INTEGER := min(ARG'length, SIZE) - 1;
subtype rtype is STD_LOGIC_VECTOR (SIZE-1 downto 0);
variable new_bounds : STD_LOGIC_VECTOR (ARG'length-1 downto 0);
variable result: rtype;
-- synopsys built_in SYN_SIGN_EXTEND
-- synopsys subpgm_id 386
begin
-- synopsys synthesis_off
new_bounds := MAKE_BINARY(ARG);
if (new_bounds(0) = 'X') then
result := rtype'(others => 'X');
return result;
end if;
result := rtype'(others => new_bounds(new_bounds'left));
result(msb downto 0) := new_bounds(msb downto 0);
return result;
-- synopsys synthesis_on
end;
end std_logic_arith;
| gpl-2.0 | 5fbe13d901b50aeaac993e7f342a10f5 | 0.63933 | 3.441716 | false | false | false | false |
gmsanchez/OrgComp | TP_02/TB_Reg_32b.vhd | 1 | 2,394 | -- Ejercicio 1(a)
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
use work.txt_util.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY TB_Reg_32b IS
END TB_Reg_32b;
ARCHITECTURE behavior OF TB_Reg_32b IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT Reg_32b
PORT(
D : IN std_logic_vector(31 downto 0);
CLK : IN std_logic;
LOAD : IN std_logic;
RST : IN std_logic;
O : BUFFER std_logic_vector(31 downto 0)
);
END COMPONENT;
--Inputs
signal D : std_logic_vector(31 downto 0) := (others => '0');
signal CLK : std_logic := '0';
signal LOAD : std_logic := '0';
signal RST : std_logic := '0';
--Outputs
signal O : std_logic_vector(31 downto 0);
-- Clock period definitions
constant CLK_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: Reg_32b PORT MAP (
D => D,
CLK => CLK,
LOAD => LOAD,
RST => RST,
O => O
);
-- Clock process definitions
CLK_process :process
begin
CLK <= '0';
wait for CLK_period/2;
CLK <= '1';
wait for CLK_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
-- check initial status
wait for 6 ns;
-- hold reset state for 5 ns.
RST <= '1';
LOAD <= '0';
D <= x"FAFAFAFA";
wait for 5 ns;
RST <= '0';
wait for 15 ns;
LOAD <= '1';
wait for 20 ns;
D <= x"51617181";
wait for 15 ns;
LOAD <= '0';
wait;
end process;
corr_proc: process(CLK)
variable theTime : time;
begin
theTime := now;
-- report time'image(theTime);
if theTime=10000 ps then
assert (O=x"00000000")
report "Resultado erroneo a los " & time'image(theTime) & " O=" & str(O)
severity ERROR;
end if;
if theTime=40000 ps then
assert (O=x"FAFAFAFA")
report "Resultado erroneo a los " & time'image(theTime) & " O=" & str(O)
severity ERROR;
end if;
if theTime=60000 ps then
assert (O=x"51617181")
report "Resultado erroneo a los " & time'image(theTime) & " O=" & str(O)
severity ERROR;
end if;
if theTime=75000 ps then
assert (O=x"51617181")
report "Resultado erroneo a los " & time'image(theTime) & " O=" & str(O)
severity ERROR;
end if;
end process;
END;
| gpl-2.0 | 6ee60fdadbf86b49b31746895848b32b | 0.596491 | 3.085052 | false | false | false | false |
gmsanchez/OrgComp | TP_02/tb_Cont32bAsync.vhd | 1 | 3,042 | -- Ejercicio 3, contador Asíncrono
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE work.txt_util.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY tb_Cont32bAsync IS
END tb_Cont32bAsync;
ARCHITECTURE behavior OF tb_Cont32bAsync IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT Cont32bAsync
PORT(
CLK : IN std_logic;
RST : IN std_logic;
LOAD : IN std_logic;
CE : IN std_logic;
UND : IN std_logic;
DIN : IN std_logic_vector(31 downto 0);
Q : BUFFER std_logic_vector(31 downto 0)
);
END COMPONENT;
--Inputs
signal CLK : std_logic := '0';
signal RST : std_logic := '0';
signal LOAD : std_logic := '0';
signal CE : std_logic := '0';
signal UND : std_logic := '0';
signal DIN : std_logic_vector(31 downto 0) := (others => '0');
--Outputs
signal Q : std_logic_vector(31 downto 0);
-- Clock period definitions
constant CLK_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: Cont32bAsync PORT MAP (
CLK => CLK,
RST => RST,
LOAD => LOAD,
CE => CE,
UND => UND,
DIN => DIN,
Q => Q
);
-- Clock process definitions
CLK_process :process
begin
CLK <= '0';
wait for CLK_period/2;
CLK <= '1';
wait for CLK_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
-- check initial states
wait for 6 ns;
DIN<=x"00000000";
RST<='1';
LOAD<='0';
UND<='0';
CE <= '0';
wait for 10 ns;
RST <= '0';
wait for 40 ns; -- debe mantenerse sin contar
DIN <= x"0000005A";
CE<='1';
wait for 20 ns;
LOAD <= '1';
wait for 10 ns;
LOAD <= '0';
wait for 100 ns;
UND <= '1';
wait;
end process;
corr_proc: process(CLK)
variable theTime : time;
begin
theTime := now;
if theTime=10000 ps then
assert (Q=x"00000000")
report "Resultado erroneo a los " & time'image(theTime) & " Q=" & str(Q)
severity ERROR;
end if;
if theTime=70000 ps then
assert (Q=x"ffffffff")
report "Resultado erroneo a los " & time'image(theTime) & " Q=" & str(Q)
severity ERROR;
end if;
if theTime=80000 ps then
assert (Q=x"fffffffe")
report "Resultado erroneo a los " & time'image(theTime) & " Q=" & str(Q)
severity ERROR;
end if;
if theTime=90000 ps then
assert (Q=x"0000005a")
report "Resultado erroneo a los " & time'image(theTime) & " Q=" & str(Q)
severity ERROR;
end if;
if theTime=120000 ps then
assert (Q=x"00000057")
report "Resultado erroneo a los " & time'image(theTime) & " Q=" & str(Q)
severity ERROR;
end if;
if theTime=210000 ps then
assert (Q=x"00000052")
report "Resultado erroneo a los " & time'image(theTime) & " Q=" & str(Q)
severity ERROR;
end if;
end process;
END;
| gpl-2.0 | 9740c2af0dacb811c6393bfa768ba00e | 0.581388 | 3.164412 | false | false | false | false |
pmh92/Proyecto-OFDM | vhdl_verification.vhd | 2 | 3,597 | -------------------------------------------------------------------------------
--! @file
--! @author Hipolito Guzman-Miranda
--! @brief Common datatypes and component declarations
-------------------------------------------------------------------------------
--! Use IEEE standard definitions library
library IEEE;
--! Use std_logic* signal types
use IEEE.STD_LOGIC_1164.all;
--! @brief Common datatypes and component declarations
--!
--!
package vhdl_verification is
--! @brief Output of datagen when \c valid='0'
--!
--! @detailed This data type has the same possible values that a \c std_logic
--! can take, but adding the value
--! \c keep, which means "maintain last valid value"
type datagen_invalid_data is (
keep, -- Keep previous valid value
uninitialized, -- 'U'
unknown, -- 'X'
zero, -- '0'
one, -- '1'
high_impedance, -- 'Z'
weak_unknown, -- 'W'
weak_zero, -- 'L'
weak_one, -- 'H'
dont_care); -- '-'
COMPONENT clkmanager
generic (
CLK_PERIOD : time := 10 ns;
RST_ACTIVE_VALUE : std_logic := '0';
RST_CYCLES : integer := 10
);
port (
endsim : in std_logic;
clk : out std_logic;
rst : out std_logic
);
END COMPONENT;
COMPONENT datawrite
generic (
SIMULATION_LABEL : string := "datawrite";
VERBOSE : boolean := false;
DEBUG : boolean := false;
OUTPUT_FILE : string := "./out/datawrite_test.txt";
OUTPUT_NIBBLES : integer := 2;
DATA_WIDTH : integer := 8
);
port (
clk : in std_logic;
data : in std_logic_vector (DATA_WIDTH-1 downto 0);
valid : in std_logic;
endsim : in std_logic
);
END COMPONENT;
COMPONENT datacompare
generic (
SIMULATION_LABEL : string := "datacompare";
VERBOSE : boolean := false;
DEBUG : boolean := false;
GOLD_OUTPUT_FILE : string := "../test/datagen_test.txt";
GOLD_OUTPUT_NIBBLES : integer := 2;
DATA_WIDTH : integer := 8
);
port (
clk : in std_logic;
data : in std_logic_vector (DATA_WIDTH-1 downto 0);
valid : in std_logic;
endsim : in std_logic
);
END COMPONENT;
COMPONENT datagen
generic (
VERBOSE : boolean := false;
STIMULI_FILE : string := "../test/datagen_test.txt";
STIMULI_NIBBLES : integer := 2;
DATA_WIDTH : integer := 8;
THROUGHPUT : integer := 0;
INVALID_DATA : datagen_invalid_data := unknown;
CYCLES_AFTER_LAST_VECTOR : integer := 10
);
port (
clk : in std_logic;
can_write : in std_logic;
data : out std_logic_vector (DATA_WIDTH-1 downto 0);
valid : out std_logic;
endsim : out std_logic
);
END COMPONENT;
COMPONENT throughputchecker
generic (
SIMULATION_LABEL : string := "throughputchecker";
DEBUG : boolean := false;
THROUGHPUT : integer := 0
);
PORT (
clk : IN std_logic;
valid : IN std_logic;
endsim : IN std_logic
);
END COMPONENT;
end vhdl_verification;
--! @brief Package body is empty since there are no function definitions here
package body vhdl_verification is
end vhdl_verification;
| gpl-2.0 | 6465e8693b5178c44c69d28c3c74a13d | 0.501251 | 4.134483 | false | false | false | false |
EliasLuiz/TCC | Leon3/lib/gaisler/misc/grsysmon.vhd | 1 | 16,897 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-------------------------------------------------------------------------------
-- Entity: grsysmon
-- File: grsysmon.vhd
-- Author: Jan Andersson - Gaisler Research AB
-- Description: Provides GRLIB AMBA AHB slave interface to Xilinx SYSMON
library ieee;
use ieee.std_logic_1164.all;
library grlib, gaisler;
use grlib.amba.all;
use grlib.devices.all;
use grlib.stdlib.all;
use gaisler.misc.all;
library techmap;
use techmap.gencomp.all;
entity grsysmon is
generic (
-- GRLIB generics
tech : integer := DEFFABTECH;
hindex : integer := 0; -- AHB slave index
hirq : integer := 0; -- Interrupt line
caddr : integer := 16#000#; -- Base address for configuration area
cmask : integer := 16#fff#; -- Area mask
saddr : integer := 16#001#; -- Base address for sysmon register area
smask : integer := 16#fff#; -- Area mask
split : integer := 0; -- Enable AMBA SPLIT support
extconvst : integer := 0; -- Use external CONVST signal
wrdalign : integer := 0; -- Word align System Monitor registers
-- Virtex 5 SYSMON generics
INIT_40 : bit_vector := X"0000";
INIT_41 : bit_vector := X"0000";
INIT_42 : bit_vector := X"0800";
INIT_43 : bit_vector := X"0000";
INIT_44 : bit_vector := X"0000";
INIT_45 : bit_vector := X"0000";
INIT_46 : bit_vector := X"0000";
INIT_47 : bit_vector := X"0000";
INIT_48 : bit_vector := X"0000";
INIT_49 : bit_vector := X"0000";
INIT_4A : bit_vector := X"0000";
INIT_4B : bit_vector := X"0000";
INIT_4C : bit_vector := X"0000";
INIT_4D : bit_vector := X"0000";
INIT_4E : bit_vector := X"0000";
INIT_4F : bit_vector := X"0000";
INIT_50 : bit_vector := X"0000";
INIT_51 : bit_vector := X"0000";
INIT_52 : bit_vector := X"0000";
INIT_53 : bit_vector := X"0000";
INIT_54 : bit_vector := X"0000";
INIT_55 : bit_vector := X"0000";
INIT_56 : bit_vector := X"0000";
INIT_57 : bit_vector := X"0000";
SIM_MONITOR_FILE : string := "sysmon.txt");
port (
rstn : in std_ulogic;
clk : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
sysmoni : in grsysmon_in_type;
sysmono : out grsysmon_out_type
);
end grsysmon;
architecture rtl of grsysmon is
-----------------------------------------------------------------------------
-- Constants
-----------------------------------------------------------------------------
constant REVISION : amba_version_type := 0;
constant HCONFIG : ahb_config_type := (
0 => ahb_device_reg(VENDOR_GAISLER, GAISLER_GRSYSMON, 0, REVISION, hirq),
4 => ahb_iobar(caddr, cmask), 5 => ahb_iobar(saddr, smask),
others => zero32);
-- BANKs
constant CONF_BANK : integer := 0;
constant SYSMON_BANK : integer := 1;
-- Registers
constant CONF_REG_OFF : std_ulogic := '0';
constant STAT_REG_OFF : std_ulogic := '1';
-----------------------------------------------------------------------------
-- Types
-----------------------------------------------------------------------------
type sysmon_out_type is record
alm : std_logic_vector(2 downto 0);
busy : std_ulogic;
channel : std_logic_vector(4 downto 0);
do : std_logic_vector(15 downto 0);
drdy : std_ulogic;
eoc : std_ulogic;
eos : std_ulogic;
jtagbusy : std_ulogic;
jtaglocked : std_ulogic;
jtagmodified : std_ulogic;
ot : std_ulogic;
end record;
type sysmon_in_type is record
daddr : std_logic_vector(6 downto 0);
den : std_ulogic;
di : std_logic_vector(15 downto 0);
dwe : std_ulogic;
end record;
type grsysmon_conf_reg_type is record
ot_ien : std_ulogic;
alm_ien : std_logic_vector(2 downto 0);
convst : std_ulogic;
eos_ien : std_ulogic;
eoc_ien : std_ulogic;
busy_ien : std_ulogic;
jb_ien : std_ulogic;
jl_ien : std_ulogic;
jm_ien : std_ulogic;
end record;
type grsysmon_reg_type is record
cfgreg : grsysmon_conf_reg_type;
-- SYSMON
den : std_ulogic; -- System monitor data enable
sma : std_ulogic; -- System monitor access
smr : std_ulogic; -- System monitor access ready
-- AHB
insplit : std_ulogic; -- SPLIT response issued
unsplit : std_ulogic; -- SPLIT complete not issued
irq : std_ulogic; -- Interrupt request
hwrite : std_ulogic;
hsel : std_ulogic;
hmbsel : std_logic_vector(0 to 1);
haddr : std_logic_vector(6 downto 0);
hready : std_ulogic;
srdata : std_logic_vector(15 downto 0); -- SYSMON response data
rrdata : std_logic_vector(12 downto 0); -- Register response data
hresp : std_logic_vector(1 downto 0);
splmst : std_logic_vector(log2(NAHBMST)-1 downto 0); -- SPLIT:ed master
hsplit : std_logic_vector(NAHBMST-1 downto 0); -- Other SPLIT:ed masters
ahbcancel : std_ulogic; -- Locked access cancels ongoing SPLIT
-- response
end record;
-----------------------------------------------------------------------------
-- Signals
-----------------------------------------------------------------------------
signal r, rin : grsysmon_reg_type;
signal syso : sysmon_out_type;
signal sysi : sysmon_in_type;
signal sysmon_rst : std_ulogic;
signal lconvst : std_ulogic;
begin -- rtl
sysmon_rst <= not rstn;
convstint: if extconvst = 0 generate
lconvst <= r.cfgreg.convst;
end generate convstint;
convstext: if extconvst /= 0 generate
lconvst <= sysmoni.convst;
end generate convstext;
-----------------------------------------------------------------------------
-- System monitor
-----------------------------------------------------------------------------
macro0 : system_monitor
generic map (tech => tech,
INIT_40 => INIT_40, INIT_41 => INIT_41, INIT_42 => INIT_42,
INIT_43 => INIT_43, INIT_44 => INIT_44, INIT_45 => INIT_45,
INIT_46 => INIT_46, INIT_47 => INIT_47, INIT_48 => INIT_48,
INIT_49 => INIT_49, INIT_4A => INIT_4A, INIT_4B => INIT_4B,
INIT_4C => INIT_4C, INIT_4D => INIT_4D, INIT_4E => INIT_4E,
INIT_4F => INIT_4F, INIT_50 => INIT_50, INIT_51 => INIT_51,
INIT_52 => INIT_52, INIT_53 => INIT_53, INIT_54 => INIT_54,
INIT_55 => INIT_55, INIT_56 => INIT_56, INIT_57 => INIT_57,
SIM_MONITOR_FILE => SIM_MONITOR_FILE)
port map (alm => syso.alm, busy => syso.busy, channel => syso.channel,
do => syso.do, drdy => syso.drdy, eoc => syso.eoc,
eos => syso.eos, jtagbusy => syso.jtagbusy,
jtaglocked => syso.jtaglocked, jtagmodified => syso.jtagmodified,
ot => syso.ot, convst => lconvst, convstclk => sysmoni.convstclk,
daddr => sysi.daddr, dclk => clk, den => sysi.den,
di => sysi.di, dwe => sysi.dwe, reset => sysmon_rst,
vauxn => sysmoni.vauxn, vauxp => sysmoni.vauxp,
vn => sysmoni.vn, vp => sysmoni.vp);
-----------------------------------------------------------------------------
-- AMBA and control i/f
-----------------------------------------------------------------------------
comb: process (r, rstn, ahbsi, syso)
variable v : grsysmon_reg_type;
variable irq : std_logic_vector((NAHBIRQ-1) downto 0);
variable addr : std_logic_vector(7 downto 0);
variable hsplit : std_logic_vector(NAHBMST-1 downto 0);
variable regaddr : std_ulogic;
variable hrdata : std_logic_vector(31 downto 0);
variable hwdata : std_logic_vector(31 downto 0);
begin -- process comb
v := r; v.irq := '0'; irq := (others => '0'); irq(hirq) := r.irq;
v.hresp := HRESP_OKAY; v.hready := '1'; v.den := '0';
regaddr := r.haddr(1-wrdalign); hsplit := (others => '0');
v.cfgreg.convst := '0';
hwdata := ahbreadword(ahbsi.hwdata, r.haddr(4 downto 2));
-- AHB communication
if ahbsi.hready = '1' then
if (ahbsi.hsel(hindex) and ahbsi.htrans(1)) = '1' then
v.hmbsel := ahbsi.hmbsel(r.hmbsel'range);
if split = 0 or (not r.sma or ahbsi.hmbsel(CONF_BANK) or
ahbsi.hmastlock) = '1' then
v.hready := ahbsi.hmbsel(CONF_BANK) and ahbsi.hwrite;
v.hwrite := ahbsi.hwrite;
v.haddr := ahbsi.haddr((7+wrdalign) downto (1+wrdalign));
v.hsel := '1';
if ahbsi.hmbsel(SYSMON_BANK) = '1' then
v.den := not r.insplit; v.sma := '1';
if split /= 0 then
if ahbsi.hmastlock = '0' then
v.hresp := HRESP_SPLIT;
v.splmst := ahbsi.hmaster;
v.unsplit := '1';
else
v.ahbcancel := r.insplit;
end if;
v.insplit := not ahbsi.hmastlock;
end if;
end if;
else
-- Core is busy, transfer is not locked and access was to sysmon
-- registers. Respond with SPLIT or insert wait states
v.hready := '0';
if split /= 0 then
v.hresp := HRESP_SPLIT;
v.hsplit(conv_integer(ahbsi.hmaster)) := '1';
end if;
end if;
else
v.hsel := '0';
end if;
end if;
if (r.hready = '0') then
if (r.hresp = HRESP_OKAY) then v.hready := '0';
else v.hresp := r.hresp; end if;
end if;
-- Read access to conf registers
if (r.hsel and r.hmbsel(CONF_BANK)) = '1' then
v.rrdata := (others => '0');
if r.hwrite = '0' then
v.hready := '1';
v.hsel := '0';
end if;
case regaddr is
when CONF_REG_OFF =>
v.rrdata(12) := r.cfgreg.ot_ien;
v.rrdata(11 downto 9) := r.cfgreg.alm_ien;
if extconvst = 0 then
v.rrdata(6) := r.cfgreg.convst;
end if;
v.rrdata(5) := r.cfgreg.eos_ien;
v.rrdata(4) := r.cfgreg.eoc_ien;
v.rrdata(3) := r.cfgreg.busy_ien;
v.rrdata(2) := r.cfgreg.jb_ien;
v.rrdata(1) := r.cfgreg.jl_ien;
v.rrdata(0) := r.cfgreg.jm_ien;
if r.hwrite = '1' then
v.cfgreg.ot_ien := hwdata(12);
v.cfgreg.alm_ien := hwdata(11 downto 9);
if extconvst = 0 then
v.cfgreg.convst := hwdata(6);
end if;
v.cfgreg.eos_ien := hwdata(5);
v.cfgreg.eoc_ien := hwdata(4);
v.cfgreg.busy_ien := hwdata(3);
v.cfgreg.jb_ien := hwdata(2);
v.cfgreg.jl_ien := hwdata(1);
v.cfgreg.jm_ien := hwdata(0);
end if;
when STAT_REG_OFF =>
v.rrdata(12) := syso.ot;
v.rrdata(11 downto 9) := syso.alm;
v.rrdata(8 downto 4) := syso.channel;
v.rrdata(3) := syso.busy;
v.rrdata(2) := syso.jtagbusy;
v.rrdata(1) := syso.jtaglocked;
v.rrdata(0) := syso.jtagmodified;
when others => null;
end case;
end if;
-- SYSMON access finished
if syso.drdy = '1' then
v.srdata := syso.do;
v.smr := '1';
end if;
if (syso.drdy or r.smr) = '1' then
if split /= 0 and r.unsplit = '1' then
hsplit(conv_integer(r.splmst)) := '1';
v.unsplit := '0';
end if;
if ((split = 0 or v.ahbcancel = '0') and
(split = 0 or ahbsi.hmaster = r.splmst or r.insplit = '0') and
-- (((split = 0 or r.insplit = '0') and r.hmbsel(SYSMON_BANK) = '1') or
-- (split = 1 and ahbsi.hmbsel(SYSMON_BANK) = '1')) and
(((ahbsi.hsel(hindex) and ahbsi.hready and ahbsi.htrans(1)) = '1') or
((split = 0 or r.insplit = '0') and r.hready = '0' and r.hresp = HRESP_OKAY))) then
v.hresp := HRESP_OKAY;
if split /= 0 then
v.insplit := '0';
v.hsplit := r.hsplit;
end if;
v.hready := '1';
v.hsel := '0';
v.smr := '0';
v.sma := '0';
elsif split /= 0 and v.ahbcancel = '1' then
v.den := '1'; v.smr := '0';
v.ahbcancel := '0';
end if;
end if;
-- Interrupts
if (syso.ot and v.cfgreg.ot_ien) = '1' then
v.irq := '1';
v.cfgreg.ot_ien := '0';
end if;
for i in r.cfgreg.alm_ien'range loop
if (syso.alm(i) and r.cfgreg.alm_ien(i)) = '1' then
v.irq := '1';
v.cfgreg.alm_ien(i) := '0';
end if;
end loop; -- i
if (syso.eos and v.cfgreg.eos_ien) = '1' then
v.irq := '1';
v.cfgreg.eos_ien := '0';
end if;
if (syso.eoc and v.cfgreg.eoc_ien) = '1' then
v.irq := '1';
v.cfgreg.eoc_ien := '0';
end if;
if (syso.busy and v.cfgreg.busy_ien) = '1' then
v.irq := '1';
v.cfgreg.busy_ien := '0';
end if;
if (syso.jtagbusy and v.cfgreg.jb_ien) = '1' then
v.irq := '1';
v.cfgreg.jb_ien := '0';
end if;
if (syso.jtaglocked and v.cfgreg.jl_ien) = '1' then
v.irq := '1';
v.cfgreg.jl_ien := '0';
end if;
if (syso.jtagmodified and v.cfgreg.jm_ien) = '1' then
v.irq := '1';
v.cfgreg.jm_ien := '0';
end if;
-- Reset
if rstn = '0' then
v.cfgreg.ot_ien := '0';
v.cfgreg.alm_ien := (others => '0');
v.cfgreg.eos_ien := '0';
v.cfgreg.eoc_ien := '0';
v.cfgreg.busy_ien := '0';
v.cfgreg.jb_ien := '0';
v.cfgreg.jl_ien := '0';
v.cfgreg.jm_ien := '0';
v.sma := '0';
v.smr := '0';
v.insplit := '0';
v.unsplit := '0';
v.hready := '1';
v.hwrite := '0';
v.hsel := '0';
v.hmbsel := (others => '0');
v.ahbcancel := '0';
end if;
if split = 0 then
v.insplit := '0';
v.unsplit := '0';
v.splmst := (others => '0');
v.hsplit := (others => '0');
v.ahbcancel := '0';
end if;
-- Update registers
rin <= v;
-- AHB slave output
ahbso.hready <= r.hready;
ahbso.hresp <= r.hresp;
if r.hmbsel(CONF_BANK) = '1' then
if wrdalign = 0 then hrdata := zero32(31 downto 13) & r.rrdata;
else hrdata := '1' & zero32(30 downto 13) & r.rrdata; end if;
else
if wrdalign = 0 then hrdata := r.srdata & r.srdata;
else hrdata := zero32(31 downto 16) & r.srdata;
end if;
end if;
ahbso.hrdata <= ahbdrivedata(hrdata);
ahbso.hconfig <= HCONFIG;
ahbso.hirq <= irq;
ahbso.hindex <= hindex;
ahbso.hsplit <= hsplit;
-- Signals to system monitor
sysi.daddr <= r.haddr;
sysi.den <= r.den;
sysi.dwe <= r.hwrite;
if wrdalign = 0 then
if r.haddr(0) = '0' then sysi.di <= hwdata(31 downto 16);
else sysi.di <= hwdata(15 downto 0); end if;
else
sysi.di <= hwdata(15 downto 0);
end if;
-- Signals from system monitor to core outputs
sysmono.alm <= syso.alm;
sysmono.ot <= syso.ot;
sysmono.eoc <= syso.eoc;
sysmono.eos <= syso.eos;
sysmono.channel <= syso.channel;
end process comb;
reg: process (clk)
begin -- process reg
if rising_edge(clk) then
r <= rin;
end if;
end process reg;
-- Boot message
-- pragma translate_off
bootmsg : report_version
generic map (
"grsysmon" & tost(hindex) & ": AMBA wrapper for System Monitor, rev " &
tost(REVISION) & ", irq " & tost(hirq));
-- pragma translate_on
end rtl;
| gpl-3.0 | 2344553416165c7cfa9418eaced4dec6 | 0.506776 | 3.598935 | false | false | false | false |
GLADICOS/SPACEWIRESYSTEMC | rtl/RTL_VJ/SpaceWireCODECIPReceiverSynchronize.vhdl | 1 | 19,819 | ------------------------------------------------------------------------------
-- The MIT License (MIT)
--
-- Copyright (c) <2013> <Shimafuji Electric Inc., Osaka University, JAXA>
--
-- Permission is hereby granted, free of charge, to any person obtaining a copy
-- of this software and associated documentation files (the "Software"), to deal
-- in the Software without restriction, including without limitation the rights
-- to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-- copies of the Software, and to permit persons to whom the Software is
-- furnished to do so, subject to the following conditions:
--
-- The above copyright notice and this permission notice shall be included in
-- all copies or substantial portions of the Software.
--
-- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-- AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
-- OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
-- THE SOFTWARE.
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
entity SpaceWireCODECIPReceiverSynchronize is
generic (
gDisconnectCountValue : integer := 141
);
port (
spaceWireStrobeIn : in std_logic;
spaceWireDataIn : in std_logic;
receiveDataOut : out std_logic_vector (8 downto 0);
receiveDataValidOut : out std_logic;
receiveTimeCodeOut : out std_logic_vector (7 downto 0);
receiveTimeCodeValidOut : out std_logic;
receiveNCharacterOut : out std_logic;
receiveFCTOut : out std_logic;
receiveNullOut : out std_logic;
receiveEEPOut : out std_logic;
receiveEOPOut : out std_logic;
receiveOffOut : out std_logic;
receiverErrorOut : out std_logic;
parityErrorOut : out std_logic;
escapeErrorOut : out std_logic;
disconnectErrorOut : out std_logic;
spaceWireReset : in std_logic;
receiveFIFOWriteEnable : out std_logic;
enableReceive : in std_logic;
receiveClock : in std_logic
);
end SpaceWireCODECIPReceiverSynchronize;
architecture RTL of SpaceWireCODECIPReceiverSynchronize is
signal iDataRegister : std_logic_vector(7 downto 0);
signal iParity : std_logic;
signal iESCFlag : std_logic;
signal iSpaceWireSynchronize : std_logic_vector(1 downto 0);
signal iBitCount : std_logic_vector(3 downto 0);
signal iLinkTimeOutCounter : std_logic_vector (7 downto 0);
signal iDisconnectErrorOut : std_logic;
signal iParityErrorOut : std_logic;
signal iEscapeErrorOut : std_logic;
signal iCommandFlag, iDataFlag : std_logic;
type spaceWireStateMachine is (
spaceWireIdel,
spaceWireOff,
spaceWireEven0,
spaceWireEven1,
spaceWireWaitEven,
spaceWireOdd0,
spaceWireOdd1,
spaceWireWaitOdd
);
signal spaceWireState : spaceWireStateMachine;
signal iReceiverEOPOut : std_logic;
signal iReceiverEEPOut : std_logic;
signal iReceiverDataValidOut : std_logic;
signal iReceiveDataOut : std_logic_vector (8 downto 0) := (others => '0');
signal iReceiveTimeCodeOut : std_logic_vector (7 downto 0);
signal iReceiveTimeCodeValidOut : std_logic;
signal iReceiveNCharacterOut : std_logic;
signal iReceiveFCTOut : std_logic;
signal iReceiveNullOut : std_logic;
signal iReceiveOffOut : std_logic;
signal iReceiverErrorOut : std_logic;
signal iReceiveFIFOWriteEnable : std_logic;
begin
receiveDataOut <= iReceiveDataOut;
receiveTimeCodeOut <= iReceiveTimeCodeOut;
receiveTimeCodeValidOut <= iReceiveTimeCodeValidOut;
receiveNCharacterOut <= iReceiveNCharacterOut;
receiveFCTOut <= iReceiveFCTOut;
receiveNullOut <= iReceiveNullOut;
receiveOffOut <= iReceiveOffOut;
receiverErrorOut <= iReceiverErrorOut;
receiveFIFOWriteEnable <= iReceiveFIFOWriteEnable;
----------------------------------------------------------------------
-- ECSS-E-ST-50-12C 8.4.4 Receiver.
----------------------------------------------------------------------
----------------------------------------------------------------------
-- synchronize DS signal to the receiveClock.
----------------------------------------------------------------------
process (receiveClock)
begin
if (receiveClock'event and receiveClock = '1') then
iSpaceWireSynchronize <= spaceWireStrobeIn & spaceWireDataIn;
end if;
end process;
----------------------------------------------------------------------
-- Detect a change of the DS signal.
----------------------------------------------------------------------
process (receiveClock, spaceWireReset, iDisconnectErrorOut)
begin
if (spaceWireReset = '1' or iDisconnectErrorOut = '1') then
spaceWireState <= spaceWireIdel;
elsif (receiveClock'event and receiveClock = '1') then
if(enableReceive = '1')then
if (spaceWireState = spaceWireIdel) then
if (iSpaceWireSynchronize = "00") then
spaceWireState <= spaceWireOff;
end if;
elsif (spaceWireState = spaceWireOff) then
if (iSpaceWireSynchronize = "10") then
spaceWireState <= spaceWireOdd0;
end if;
elsif (spaceWireState = spaceWireEven1 or spaceWireState = spaceWireEven0 or spaceWireState = spaceWireWaitOdd) then
if (iSpaceWireSynchronize = "10") then
spaceWireState <= spaceWireOdd0;
elsif (iSpaceWireSynchronize = "01") then
spaceWireState <= spaceWireOdd1;
else
spaceWireState <= spaceWireWaitOdd;
end if;
elsif (spaceWireState = spaceWireOdd1 or spaceWireState = spaceWireOdd0 or spaceWireState = spaceWireWaitEven) then
if (iSpaceWireSynchronize = "00") then
spaceWireState <= spaceWireEven0;
elsif (iSpaceWireSynchronize = "11") then
spaceWireState <= spaceWireEven1;
else
spaceWireState <= spaceWireWaitEven;
end if;
else
spaceWireState <= spaceWireIdel;
end if;
end if;
end if;
end process;
process (receiveClock)
begin
if (receiveClock'event and receiveClock = '1') then
----------------------------------------------------------------------
-- Take the data into the shift register on the State transition of spaceWireState.
----------------------------------------------------------------------
if(enableReceive = '1')then
if (spaceWireState = spaceWireOff) then
iDataRegister <= (others => '0');
elsif (spaceWireState = spaceWireOdd1 or spaceWireState = spaceWireEven1) then
iDataRegister <= '1' & iDataRegister(7 downto 1);
elsif (spaceWireState = spaceWireOdd0 or spaceWireState = spaceWireEven0) then
iDataRegister <= '0' & iDataRegister(7 downto 1);
end if;
else
iDataRegister <= (others => '0');
end if;
----------------------------------------------------------------------
-- ECSS-E-ST-50-12C 7.4 Parity for error detection.
-- Odd Parity.
----------------------------------------------------------------------
if(enableReceive = '1' and iEscapeErrorOut = '0' and iDisconnectErrorOut = '0')then
if (spaceWireState = spaceWireOff) then
iParity <= '0';
elsif (iBitCount = 0 and spaceWireState = spaceWireEven1) then
if (iParity = '1') then
iParityErrorOut <= '1';
iParity <= '0';
end if;
elsif (iBitCount = 0 and spaceWireState = spaceWireEven0) then
if iParity = '0' then
iParityErrorOut <= '1';
else
iParity <= '0';
end if;
elsif (spaceWireState = spaceWireOdd1 or spaceWireState = spaceWireEven1) then
iParity <= not iParity;
end if;
else
iParityErrorOut <= '0';
end if;
----------------------------------------------------------------------
-- ECSS-E-ST-50-12C 8.5.3.7.2 Disconnect error.
-- Disconnect error is an error condition asserted
-- when the length of time since the last transition on
-- the D or S lines was longer than 850 ns nominal.
----------------------------------------------------------------------
if(enableReceive = '1' and iEscapeErrorOut = '0' and iParityErrorOut = '0')then
if (spaceWireState = spaceWireWaitOdd or spaceWireState = spaceWireWaitEven) then
if (iLinkTimeOutCounter < gDisconnectCountValue) then
iLinkTimeOutCounter <= iLinkTimeOutCounter + 1;
else
iDisconnectErrorOut <= '1';
end if;
elsif (spaceWireState = spaceWireIdel) then
iLinkTimeOutCounter <= X"00";
elsif (spaceWireState = spaceWireOdd1 or spaceWireState = spaceWireEven1 or spaceWireState = spaceWireOdd0 or spaceWireState = spaceWireEven0) then
iLinkTimeOutCounter <= X"00";
end if;
else
iDisconnectErrorOut <= '0';
iLinkTimeOutCounter <= X"00";
end if;
----------------------------------------------------------------------
-- ECSS-E-ST-50-12C 4.4 Character level
-- ECSS-E-ST-50-12C 7.2 Data characters
-- Discriminate the data character or the the control character by the Data
-- Control Flag.
----------------------------------------------------------------------
if(enableReceive = '1')then
if (spaceWireState = spaceWireIdel) then
iCommandFlag <= '0'; iDataFlag <= '0';
elsif (iBitCount = 0 and spaceWireState = spaceWireEven0) then
iCommandFlag <= '0'; iDataFlag <= '1';
elsif (iBitCount = 0 and spaceWireState = spaceWireEven1) then
iCommandFlag <= '1'; iDataFlag <= '0';
end if;
else
iCommandFlag <= '0'; iDataFlag <= '0';
end if;
----------------------------------------------------------------------
-- Increment bit of character corresponding by state transition of
-- spaceWireState.
----------------------------------------------------------------------
if(enableReceive = '1' and iEscapeErrorOut = '0' and iDisconnectErrorOut = '0')then
if (spaceWireState = spaceWireIdel or spaceWireState = spaceWireOff) then
iBitCount <= X"0";
elsif (spaceWireState = spaceWireEven1 or spaceWireState = spaceWireEven0) then
if (iBitCount = 1 and iCommandFlag = '1') then
iBitCount <= X"0";
elsif (iBitCount = 4 and iCommandFlag = '0') then
iBitCount <= X"0";
else
iBitCount <= iBitCount + 1;
end if;
end if;
else
iBitCount <= X"0";
end if;
----------------------------------------------------------------------
-- ECSS-E-ST-50-12C 7.3 Control characters and control codes.
-- Discriminate Data character, Control code and Time corde, and write to
-- Receive buffer
----------------------------------------------------------------------
if(enableReceive = '1')then
if (iBitCount = 0 and (spaceWireState = spaceWireOdd0 or spaceWireState = spaceWireOdd1)) then
if (iDataFlag = '1') then
if (iESCFlag = '1') then
--Time Code Receive.
iReceiveTimeCodeOut <= iDataRegister;
else
--Data Receive.
iReceiveDataOut <= '0' & iDataRegister;
iReceiveFIFOWriteEnable <= '1';
end if;
elsif (iCommandFlag = '1') then
if (iDataRegister (7 downto 6) = "10") then --EOP
iReceiveDataOut <= '1' & "00000000";
elsif (iDataRegister (7 downto 6) = "01") then --EEP
iReceiveDataOut <= '1' & "00000001";
end if;
if ((iESCFlag /= '1') and (iDataRegister (7 downto 6) = "10" or iDataRegister (7 downto 6) = "01")) then
--EOP EEP Receive.
iReceiveFIFOWriteEnable <= '1';
end if;
end if;
else
iReceiveFIFOWriteEnable <= '0';
end if;
end if;
----------------------------------------------------------------------
-- ECSS-E-ST-50-12C 7.3 Control characters and control codes.
-- ECSS-E-ST-50-12C 8.5.3.7.4 Escape error.
-- Receive DataCharacter, ControlCode and TimeCode.
----------------------------------------------------------------------
if(enableReceive = '1' and iDisconnectErrorOut = '0' and iParityErrorOut = '0')then
if (iBitCount = 0 and (spaceWireState = spaceWireOdd0 or spaceWireState = spaceWireOdd1)) then
if (iCommandFlag = '1') then
case iDataRegister(7 downto 6) is
----------------------------------------------------------------------
-- ECSS-E-ST-50-12C 8.5.3.2 gotNULL.
-- ECSS-E-ST-50-12C 8.5.3.3 gotFCT.
----------------------------------------------------------------------
when "00" => -- FCT Receive or Null Receive.
if (iESCFlag = '1') then
iReceiveNullOut <= '1';
iESCFlag <= '0';
else
iReceiveFCTOut <= '1';
end if;
when "11" => -- ESC Receive.
if (iESCFlag = '1') then
iEscapeErrorOut <= '1';
else
iESCFlag <= '1';
end if;
when "10" => -- EOP Receive.
if (iESCFlag = '1') then
iEscapeErrorOut <= '1';
else
iReceiverEOPOut <= '1';
end if;
when "01" => -- EEP Receive.
if (iESCFlag = '1') then
iEscapeErrorOut <= '1';
else
iReceiverEEPOut <= '1';
end if;
when others => null;
end case;
----------------------------------------------------------------------
-- ECSS-E-ST-50-12C 8.5.3.5 gotTime-Code.
-- ECSS-E-ST-50-12C 8.5.3.4 gotN-Char.
----------------------------------------------------------------------
elsif (iDataFlag = '1') then
if (iESCFlag = '1') then --TimeCode_Receive.
iReceiveTimeCodeValidOut <= '1';
iESCFlag <= '0';
else --N-Char_Receive.
iReceiverDataValidOut <= '1';
end if;
end if;
----------------------------------------------------------------------
-- Clear the previous Receive flag before receiving data.
----------------------------------------------------------------------
elsif (iBitCount = 1 and (spaceWireState = spaceWireOdd0 or spaceWireState = spaceWireOdd1)) then
iReceiverDataValidOut <= '0';
iReceiveTimeCodeValidOut <= '0';
iReceiveNullOut <= '0';
iReceiveFCTOut <= '0';
iReceiverEOPOut <= '0';
iReceiverEEPOut <= '0';
elsif spaceWireState = spaceWireIdel then
iReceiverDataValidOut <= '0';
iReceiveTimeCodeValidOut <= '0';
iReceiveNullOut <= '0';
iReceiveFCTOut <= '0';
iReceiverEOPOut <= '0';
iReceiverEEPOut <= '0';
iEscapeErrorOut <= '0';
iESCFlag <= '0';
end if;
else
iReceiverDataValidOut <= '0';
iReceiveTimeCodeValidOut <= '0';
iReceiveNullOut <= '0';
iReceiveFCTOut <= '0';
iReceiverEOPOut <= '0';
iReceiverEEPOut <= '0';
iEscapeErrorOut <= '0';
iESCFlag <= '0';
end if;
end if;
end process;
iReceiveOffOut <= '1' when spaceWireState = spaceWireOff else '0';
iReceiverErrorOut <= '1' when iDisconnectErrorOut = '1' or iParityErrorOut = '1' or iEscapeErrorOut = '1' else '0';
iReceiveNCharacterOut <= '1' when iReceiverEOPOut = '1' or iReceiverEEPOut = '1' or iReceiverDataValidOut = '1' else '0';
receiveDataValidOut <= iReceiverDataValidOut;
receiveEOPOut <= iReceiverEOPOut;
receiveEEPOut <= iReceiverEEPOut;
parityErrorOut <= iParityErrorOut;
escapeErrorOut <= iEscapeErrorOut;
disconnectErrorOut <= iDisconnectErrorOut;
end RTL;
| gpl-3.0 | 83db667b02cc4115bf60e4c47c14be81 | 0.451183 | 5.126487 | false | false | false | false |
EliasLuiz/TCC | Leon3/designs/leon3-gr-cpci-xc4v/config.vhd | 1 | 9,639 |
-----------------------------------------------------------------------------
-- LEON3 Demonstration design test bench configuration
-- Copyright (C) 2009 Aeroflex Gaisler
------------------------------------------------------------------------------
library techmap;
use techmap.gencomp.all;
package config is
-- Technology and synthesis options
constant CFG_FABTECH : integer := virtex4;
constant CFG_MEMTECH : integer := virtex4;
constant CFG_PADTECH : integer := virtex4;
constant CFG_TRANSTECH : integer := GTP0;
constant CFG_NOASYNC : integer := 0;
constant CFG_SCAN : integer := 0;
-- Clock generator
constant CFG_CLKTECH : integer := virtex4;
constant CFG_CLKMUL : integer := (6);
constant CFG_CLKDIV : integer := (5);
constant CFG_OCLKDIV : integer := 1;
constant CFG_OCLKBDIV : integer := 0;
constant CFG_OCLKCDIV : integer := 0;
constant CFG_PCIDLL : integer := 0;
constant CFG_PCISYSCLK: integer := 0;
constant CFG_CLK_NOFB : integer := 0;
-- LEON processor core
constant CFG_LEON : integer := 3;
constant CFG_NCPU : integer := (1);
constant CFG_NWIN : integer := (8);
constant CFG_V8 : integer := 2 + 4*0;
constant CFG_MAC : integer := 0;
constant CFG_SVT : integer := 1;
constant CFG_RSTADDR : integer := 16#00000#;
constant CFG_LDDEL : integer := (1);
constant CFG_NWP : integer := (4);
constant CFG_PWD : integer := 1*2;
constant CFG_FPU : integer := 0 + 16*0 + 32*0;
constant CFG_GRFPUSH : integer := 0;
constant CFG_ICEN : integer := 1;
constant CFG_ISETS : integer := 2;
constant CFG_ISETSZ : integer := 16;
constant CFG_ILINE : integer := 8;
constant CFG_IREPL : integer := 2;
constant CFG_ILOCK : integer := 0;
constant CFG_ILRAMEN : integer := 0;
constant CFG_ILRAMADDR: integer := 16#8E#;
constant CFG_ILRAMSZ : integer := 1;
constant CFG_DCEN : integer := 1;
constant CFG_DSETS : integer := 2;
constant CFG_DSETSZ : integer := 4;
constant CFG_DLINE : integer := 8;
constant CFG_DREPL : integer := 2;
constant CFG_DLOCK : integer := 0;
constant CFG_DSNOOP : integer := 1*2 + 4*0;
constant CFG_DFIXED : integer := 16#0#;
constant CFG_BWMASK : integer := 16#0#;
constant CFG_CACHEBW : integer := 128;
constant CFG_DLRAMEN : integer := 0;
constant CFG_DLRAMADDR: integer := 16#8F#;
constant CFG_DLRAMSZ : integer := 1;
constant CFG_MMUEN : integer := 1;
constant CFG_ITLBNUM : integer := 8;
constant CFG_DTLBNUM : integer := 8;
constant CFG_TLB_TYPE : integer := 0 + 1*2;
constant CFG_TLB_REP : integer := 0;
constant CFG_DSU : integer := 1;
constant CFG_ITBSZ : integer := 2 + 64*0;
constant CFG_ATBSZ : integer := 2;
constant CFG_AHBPF : integer := 0;
constant CFG_AHBWP : integer := 2;
constant CFG_LEONFT_EN : integer := 0 + 0*8;
constant CFG_LEON_NETLIST : integer := 0;
constant CFG_DISAS : integer := 0 + 0;
constant CFG_PCLOW : integer := 0;
constant CFG_STAT_ENABLE : integer := 0;
constant CFG_STAT_CNT : integer := 1;
constant CFG_STAT_NMAX : integer := 0;
constant CFG_STAT_DSUEN : integer := 0;
constant CFG_NP_ASI : integer := 0;
constant CFG_WRPSR : integer := 0;
constant CFG_ALTWIN : integer := 0;
constant CFG_REX : integer := 0;
-- AMBA settings
constant CFG_DEFMST : integer := (0);
constant CFG_RROBIN : integer := 1;
constant CFG_SPLIT : integer := 0;
constant CFG_FPNPEN : integer := 0;
constant CFG_AHBIO : integer := 16#FFF#;
constant CFG_APBADDR : integer := 16#800#;
constant CFG_AHB_MON : integer := 0;
constant CFG_AHB_MONERR : integer := 0;
constant CFG_AHB_MONWAR : integer := 0;
constant CFG_AHB_DTRACE : integer := 0;
-- DSU UART
constant CFG_AHB_UART : integer := 1;
-- JTAG based DSU interface
constant CFG_AHB_JTAG : integer := 1;
-- Ethernet DSU
constant CFG_DSU_ETH : integer := 1 + 0 + 0;
constant CFG_ETH_BUF : integer := 2;
constant CFG_ETH_IPM : integer := 16#C0A8#;
constant CFG_ETH_IPL : integer := 16#0059#;
constant CFG_ETH_ENM : integer := 16#020000#;
constant CFG_ETH_ENL : integer := 16#000059#;
-- LEON2 memory controller
constant CFG_MCTRL_LEON2 : integer := 1;
constant CFG_MCTRL_RAM8BIT : integer := 1;
constant CFG_MCTRL_RAM16BIT : integer := 0;
constant CFG_MCTRL_5CS : integer := 0;
constant CFG_MCTRL_SDEN : integer := 1;
constant CFG_MCTRL_SEPBUS : integer := 1;
constant CFG_MCTRL_INVCLK : integer := 0;
constant CFG_MCTRL_SD64 : integer := 1;
constant CFG_MCTRL_PAGE : integer := 0 + 0;
-- FTMCTRL memory controller
constant CFG_MCTRLFT : integer := 0;
constant CFG_MCTRLFT_RAM8BIT : integer := 0;
constant CFG_MCTRLFT_RAM16BIT : integer := 0;
constant CFG_MCTRLFT_5CS : integer := 0;
constant CFG_MCTRLFT_SDEN : integer := 0;
constant CFG_MCTRLFT_SEPBUS : integer := 0;
constant CFG_MCTRLFT_INVCLK : integer := 0;
constant CFG_MCTRLFT_SD64 : integer := 0;
constant CFG_MCTRLFT_EDAC : integer := 0 + 0 + 0;
constant CFG_MCTRLFT_PAGE : integer := 0 + 0;
constant CFG_MCTRLFT_ROMASEL : integer := 0;
constant CFG_MCTRLFT_WFB : integer := 0;
constant CFG_MCTRLFT_NET : integer := 0;
-- SDRAM controller
constant CFG_SDCTRL : integer := 0;
constant CFG_SDCTRL_INVCLK : integer := 0;
constant CFG_SDCTRL_SD64 : integer := 0;
constant CFG_SDCTRL_PAGE : integer := 0 + 0;
-- AHB status register
constant CFG_AHBSTAT : integer := 1;
constant CFG_AHBSTATN : integer := (1);
-- AHB RAM
constant CFG_AHBRAMEN : integer := 0;
constant CFG_AHBRSZ : integer := 4;
constant CFG_AHBRADDR : integer := 16#A00#;
constant CFG_AHBRPIPE : integer := 0;
-- Gaisler Ethernet core
constant CFG_GRETH : integer := 1;
constant CFG_GRETH1G : integer := 0;
constant CFG_ETH_FIFO : integer := 32;
constant CFG_GRETH_FT : integer := 0;
constant CFG_GRETH_EDCLFT : integer := 0;
-- CAN 2.0 interface
constant CFG_CAN : integer := 0;
constant CFG_CAN_NUM : integer := (1);
constant CFG_CANIO : integer := 16#C00#;
constant CFG_CANIRQ : integer := (13);
constant CFG_CANSEPIRQ: integer := 0;
constant CFG_CAN_SYNCRST : integer := 0;
constant CFG_CANFT : integer := 0;
-- Spacewire interface
constant CFG_SPW_EN : integer := 0;
constant CFG_SPW_NUM : integer := (1);
constant CFG_SPW_AHBFIFO : integer := 16;
constant CFG_SPW_RXFIFO : integer := 16;
constant CFG_SPW_RMAP : integer := 0;
constant CFG_SPW_RMAPBUF : integer := 4;
constant CFG_SPW_RMAPCRC : integer := 0;
constant CFG_SPW_NETLIST : integer := 0;
constant CFG_SPW_FT : integer := 0;
constant CFG_SPW_GRSPW : integer := 2;
constant CFG_SPW_RXUNAL : integer := 0;
constant CFG_SPW_DMACHAN : integer := (1);
constant CFG_SPW_PORTS : integer := (1);
constant CFG_SPW_INPUT : integer := 3;
constant CFG_SPW_OUTPUT : integer := 0;
constant CFG_SPW_RTSAME : integer := 0;
-- PCI interface
constant CFG_PCI : integer := 0;
constant CFG_PCIVID : integer := 16#1AC8#;
constant CFG_PCIDID : integer := 16#0054#;
constant CFG_PCIDEPTH : integer := 8;
constant CFG_PCI_MTF : integer := 1;
-- GRPCI2 interface
constant CFG_GRPCI2_MASTER : integer := 1;
constant CFG_GRPCI2_TARGET : integer := 1;
constant CFG_GRPCI2_DMA : integer := 0;
constant CFG_GRPCI2_VID : integer := 16#1AC8#;
constant CFG_GRPCI2_DID : integer := 16#0054#;
constant CFG_GRPCI2_CLASS : integer := 16#000000#;
constant CFG_GRPCI2_RID : integer := 16#00#;
constant CFG_GRPCI2_CAP : integer := 16#40#;
constant CFG_GRPCI2_NCAP : integer := 16#00#;
constant CFG_GRPCI2_BAR0 : integer := (26);
constant CFG_GRPCI2_BAR1 : integer := (0);
constant CFG_GRPCI2_BAR2 : integer := (0);
constant CFG_GRPCI2_BAR3 : integer := (0);
constant CFG_GRPCI2_BAR4 : integer := (0);
constant CFG_GRPCI2_BAR5 : integer := (0);
constant CFG_GRPCI2_FDEPTH : integer := 3;
constant CFG_GRPCI2_FCOUNT : integer := 2;
constant CFG_GRPCI2_ENDIAN : integer := 0;
constant CFG_GRPCI2_DEVINT : integer := 1;
constant CFG_GRPCI2_DEVINTMSK : integer := 16#0#;
constant CFG_GRPCI2_HOSTINT : integer := 1;
constant CFG_GRPCI2_HOSTINTMSK: integer := 16#0#;
constant CFG_GRPCI2_TRACE : integer := 1024;
constant CFG_GRPCI2_TRACEAPB : integer := 0;
constant CFG_GRPCI2_BYPASS : integer := 0;
constant CFG_GRPCI2_EXTCFG : integer := (0);
-- PCI arbiter
constant CFG_PCI_ARB : integer := 1;
constant CFG_PCI_ARBAPB : integer := 1;
constant CFG_PCI_ARB_NGNT : integer := (4);
-- PCI trace buffer
constant CFG_PCITBUFEN: integer := 0;
constant CFG_PCITBUF : integer := 256;
-- UART 1
constant CFG_UART1_ENABLE : integer := 1;
constant CFG_UART1_FIFO : integer := 8;
-- UART 2
constant CFG_UART2_ENABLE : integer := 1;
constant CFG_UART2_FIFO : integer := 8;
-- LEON3 interrupt controller
constant CFG_IRQ3_ENABLE : integer := 1;
constant CFG_IRQ3_NSEC : integer := 0;
-- Modular timer
constant CFG_GPT_ENABLE : integer := 1;
constant CFG_GPT_NTIM : integer := (3);
constant CFG_GPT_SW : integer := (8);
constant CFG_GPT_TW : integer := (32);
constant CFG_GPT_IRQ : integer := (8);
constant CFG_GPT_SEPIRQ : integer := 1;
constant CFG_GPT_WDOGEN : integer := 1;
constant CFG_GPT_WDOG : integer := 16#FFFFFF#;
-- GPIO port
constant CFG_GRGPIO_ENABLE : integer := 1;
constant CFG_GRGPIO_IMASK : integer := 16#FE#;
constant CFG_GRGPIO_WIDTH : integer := (8);
-- Dynamic Partial Reconfiguration
constant CFG_PRC : integer := 0;
constant CFG_CRC_EN : integer := 0;
constant CFG_EDAC_EN : integer := 0;
constant CFG_WORDS_BLOCK : integer := 100;
constant CFG_DCM_FIFO : integer := 0;
constant CFG_DPR_FIFO : integer := 9;
-- GRLIB debugging
constant CFG_DUART : integer := 0;
end;
| gpl-3.0 | bdccb774616d970ffcf32018cf380114 | 0.653284 | 3.526894 | false | false | false | false |
pwsoft/fpga_examples | rtl/chameleon/chameleon2_io_shiftreg.vhd | 1 | 3,733 | -- -----------------------------------------------------------------------
--
-- Turbo Chameleon 64
--
-- Multi purpose FPGA expansion for the Commodore 64 computer
--
-- -----------------------------------------------------------------------
-- Copyright 2005-2018 by Peter Wendrich ([email protected])
-- http://www.syntiac.com
--
-- This source file is free software: you can redistribute it and/or modify
-- it under the terms of the GNU Lesser General Public License as published
-- by the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This source file is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
-- -----------------------------------------------------------------------
-- I/O controller entity for the shiftregister controlling PS/2,
-- LEDs and reset signals on Turbo Chameleon 64 second edition.
--
-- -----------------------------------------------------------------------
-- clk - System clock
--
-- ser_out_clk - Serial clock, connect on toplevel to port with same name
-- ser_out_dat - Serial data, connect on toplevel to port with same name
-- ser_out_rclk - Serial strobe, connect on toplevel to port with same name
--
-- reset_c64 - Active high, pulls reset on the cartridge port
-- reset_iec - Active high, pulls reset on teh IEC connector
-- ps2_mouse_clk - Open drain output for PS/2 mouse clock (active low)
-- ps2_mouse_dat - Open drain output for PS/2 mouse data (active low)
-- ps2_keybard_clk - Open drain output for PS/2 keyboard clock (active low)
-- ps2_keybard_dat - Open drain output for PS/2 keyboard data (active low)
-- led_green - Active high, enable the green LED
-- led_red - Active high, enable the red LED
-- -----------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-- -----------------------------------------------------------------------
entity chameleon2_io_shiftreg is
port (
clk : in std_logic;
ser_out_clk : out std_logic;
ser_out_dat : out std_logic;
ser_out_rclk : out std_logic;
reset_c64 : in std_logic;
reset_iec : in std_logic;
ps2_mouse_clk : in std_logic;
ps2_mouse_dat : in std_logic;
ps2_keyboard_clk : in std_logic;
ps2_keyboard_dat : in std_logic;
led_green : in std_logic;
led_red : in std_logic
);
end entity;
architecture rtl of chameleon2_io_shiftreg is
signal state_reg : unsigned(6 downto 0) := (others => '0');
signal clk_reg : std_logic := '0';
signal dat_reg : std_logic := '0';
signal rclk_reg : std_logic := '1';
begin
ser_out_clk <= clk_reg;
ser_out_dat <= dat_reg;
ser_out_rclk <= rclk_reg;
process(clk)
begin
if rising_edge(clk) then
state_reg <= state_reg + 1;
clk_reg <= state_reg(2) and (not state_reg(6));
rclk_reg <= state_reg(2) and state_reg(6);
case state_reg(6 downto 3) is
when "0000" => dat_reg <= reset_c64;
when "0001" => dat_reg <= reset_iec;
when "0010" => dat_reg <= not ps2_mouse_clk;
when "0011" => dat_reg <= not ps2_mouse_dat;
when "0100" => dat_reg <= not ps2_keyboard_clk;
when "0101" => dat_reg <= not ps2_keyboard_dat;
when "0110" => dat_reg <= not led_green;
when "0111" => dat_reg <= not led_red;
when "1000" => null;
when others => state_reg <= (others => '0');
end case;
end if;
end process;
end architecture;
| lgpl-2.1 | b8a36a8e04bac56b74774b3e137adfa0 | 0.593089 | 3.511759 | false | false | false | false |
GLADICOS/SPACEWIRESYSTEMC | rtl/RTL_VJ/SpaceWireCODECIPLinkInterface.vhdl | 1 | 22,367 | ------------------------------------------------------------------------------
-- The MIT License (MIT)
--
-- Copyright (c) <2013> <Shimafuji Electric Inc., Osaka University, JAXA>
--
-- Permission is hereby granted, free of charge, to any person obtaining a copy
-- of this software and associated documentation files (the "Software"), to deal
-- in the Software without restriction, including without limitation the rights
-- to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-- copies of the Software, and to permit persons to whom the Software is
-- furnished to do so, subject to the following conditions:
--
-- The above copyright notice and this permission notice shall be included in
-- all copies or substantial portions of the Software.
--
-- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-- AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
-- OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
-- THE SOFTWARE.
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
library work;
use work.SpaceWireCODECIPPackage.all;
entity SpaceWireCODECIPLinkInterface is
generic (
gDisconnectCountValue : integer := 141;
gTimer6p4usValue : integer := 640;
gTimer12p8usValue : integer := 1280;
gTransmitClockDivideValue : std_logic_vector (5 downto 0) := "001001"
);
port (
clock : in std_logic;
reset : in std_logic;
-- state machine.
transmitClock : in std_logic;
linkStart : in std_logic;
linkDisable : in std_logic;
autoStart : in std_logic;
linkStatus : out std_logic_vector (15 downto 0);
errorStatus : out std_logic_vector (7 downto 0);
spaceWireResetOut : out std_logic;
FIFOAvailable : in std_logic;
-- transmitter.
tickIn : in std_logic;
timeIn : in std_logic_vector (5 downto 0);
controlFlagsIn : in std_logic_vector (1 downto 0);
transmitDataEnable : in std_logic;
transmitData : in std_logic_vector (7 downto 0);
transmitDataControlFlag : in std_logic;
transmitReady : out std_logic;
transmitClockDivideValue : in std_logic_vector(5 downto 0);
creditCount : out std_logic_vector (5 downto 0);
outstndingCount : out std_logic_vector (5 downto 0);
-- receiver.
receiveClock : in std_logic;
tickOut : out std_logic;
timeOut : out std_logic_vector (5 downto 0);
controlFlagsOut : out std_logic_vector (1 downto 0);
receiveFIFOWriteEnable1 : out std_logic;
receiveData : out std_logic_vector (7 downto 0);
receiveDataControlFlag : out std_logic;
receiveFIFOCount : in std_logic_vector(5 downto 0);
-- serial i/o.
spaceWireDataOut : out std_logic;
spaceWireStrobeOut : out std_logic;
spaceWireDataIn : in std_logic;
spaceWireStrobeIn : in std_logic;
statisticalInformationClear : in std_logic;
statisticalInformation : out bit32X8Array
);
end SpaceWireCODECIPLinkInterface;
architecture Behavioral of SpaceWireCODECIPLinkInterface is
component SpaceWireCODECIPReceiverSynchronize is
generic (
gDisconnectCountValue : integer := 141
);
port (
spaceWireStrobeIn : in std_logic;
spaceWireDataIn : in std_logic;
receiveDataOut : out std_logic_vector (8 downto 0);
receiveDataValidOut : out std_logic;
receiveTimeCodeOut : out std_logic_vector (7 downto 0);
receiveTimeCodeValidOut : out std_logic;
receiveNCharacterOut : out std_logic;
receiveFCTOut : out std_logic;
receiveNullOut : out std_logic;
receiveEEPOut : out std_logic;
receiveEOPOut : out std_logic;
receiveOffOut : out std_logic;
receiverErrorOut : out std_logic;
parityErrorOut : out std_logic;
escapeErrorOut : out std_logic;
disconnectErrorOut : out std_logic;
receiveFIFOWriteEnable : out std_logic;
enableReceive : in std_logic;
spaceWireReset : in std_logic;
receiveClock : in std_logic
);
end component;
component SpaceWireCODECIPTransmitter
generic (
gInitializeTransmitClockDivideValue : std_logic_vector (5 downto 0) := "001001"
);
port (
transmitClock : in std_logic;
clock : in std_logic;
receiveClock : in std_logic;
reset : in std_logic;
spaceWireDataOut : out std_logic;
spaceWireStrobeOut : out std_logic;
tickIn : in std_logic;
timeIn : in std_logic_vector (5 downto 0);
controlFlagsIn : in std_logic_vector (1 downto 0);
transmitDataEnable : in std_logic;
transmitData : in std_logic_vector (7 downto 0);
transmitDataControlFlag : in std_logic;
transmitReady : out std_logic;
enableTransmit : in std_logic;
sendNulls : in std_logic;
sendFCTs : in std_logic;
sendNCharacters : in std_logic;
sendTimeCodes : in std_logic;
gotFCT : in std_logic;
gotNCharacter : in std_logic;
receiveFIFOCount : in std_logic_vector(5 downto 0);
creditError : out std_logic;
transmitClockDivide : in std_logic_vector(5 downto 0);
creditCountOut : out std_logic_vector (5 downto 0);
outstandingCountOut : out std_logic_vector (5 downto 0);
spaceWireResetOut : in std_logic;
transmitEEPAsynchronous : out std_logic;
transmitEOPAsynchronous : out std_logic;
transmitByteAsynchronous : out std_logic
);
end component;
component SpaceWireCODECIPStateMachine
port (
clock : in std_logic;
receiveClock : in std_logic;
reset : in std_logic;
after12p8us : in std_logic;
after6p4us : in std_logic;
linkStart : in std_logic;
linkDisable : in std_logic;
autoStart : in std_logic;
enableTransmit : out std_logic;
sendNulls : out std_logic;
sendFCTs : out std_logic;
sendNCharacter : out std_logic;
sendTimeCodes : out std_logic;
gotTimeCode : in std_logic;
gotFCT : in std_logic;
gotNCharacter : in std_logic;
gotNull : in std_logic;
gotBit : in std_logic;
creditError : in std_logic;
receiveError : in std_logic;
enableReceive : out std_logic;
characterSequenceError : out std_logic;
spaceWireResetOut : out std_logic;
FIFOAvailable : in std_logic;
timer6p4usReset : out std_logic;
timer12p8usStart : out std_logic;
linkUpTransitionSynchronize : out std_logic;
linkDownTransitionSynchronize : out std_logic;
linkUpEnable : out std_logic;
nullSynchronize : out std_logic;
fctSynchronize : out std_logic
);
end component;
component SpaceWireCODECIPTimer is
generic (
gTimer6p4usValue : integer := 640;
gTimer12p8usValue : integer := 1280
);
port (
clock : in std_logic;
reset : in std_logic;
timer6p4usReset : in std_logic;
timer12p8usStart : in std_logic;
after6p4us : out std_logic;
after12p8us : out std_logic
);
end component;
component SpaceWireCODECIPStatisticalInformationCount is
port (
clock : in std_logic;
reset : in std_logic;
transmitClock : in std_logic;
receiveClock : in std_logic;
receiveEEPAsynchronous : in std_logic;
receiveEOPAsynchronous : in std_logic;
receiveByteAsynchronous : in std_logic;
transmitEEPAsynchronous : in std_logic;
transmitEOPAsynchronous : in std_logic;
transmitByteAsynchronous : in std_logic;
linkUpTransition : in std_logic;
linkDownTransition : in std_logic;
linkUpEnable : in std_logic;
nullSynchronous : in std_logic;
fctSynchronous : in std_logic;
statisticalInformationClear : in std_logic;
statisticalInformation : out bit32X8Array;
characterMonitor : out std_logic_vector(6 downto 0)
);
end component;
component SpaceWireCODECIPTimeCodeControl is
port (
clock : in std_logic;
reset : in std_logic;
receiveClock : in std_logic;
gotTimeCode : in std_logic;
receiveTimeCodeOut : in std_logic_vector(7 downto 0);
timeOut : out std_logic_vector(5 downto 0);
controlFlagsOut : out std_logic_vector(1 downto 0);
tickOut : out std_logic
);
end component;
signal gotFCT : std_logic;
signal gotTimeCode : std_logic;
signal gotNCharacter : std_logic;
signal gotNull : std_logic;
signal iGotBit : std_logic;
signal iCreditError : std_logic;
signal parityError : std_logic;
signal escapeError : std_logic;
signal disconnectError : std_logic;
signal receiveError : std_logic;
signal enableReceive : std_logic;
signal sendNCharactors : std_logic;
signal sendTimeCode : std_logic;
signal after12p8us : std_logic;
signal after6p4us : std_logic;
signal enableTransmit : std_logic;
signal sendNulls : std_logic;
signal sendFCTs : std_logic;
signal spaceWireResetOutSignal : std_logic;
signal characterSequenceError : std_logic;
signal timer6p4usReset : std_logic;
signal timer12p8usStart : std_logic;
signal receiveFIFOWriteEnable0 : std_logic;
signal iReceiveFIFOWriteEnable1 : std_logic;
signal receiveOff : std_logic;
signal receiveTimeCodeOut : std_logic_vector(7 downto 0) := x"00";
signal linkUpTransitionSynchronize : std_logic;
signal linkDownTransitionSynchronize : std_logic;
signal linkUpEnable : std_logic;
signal nullSynchronize : std_logic;
signal fctSynchronize : std_logic;
signal receiveEEPAsynchronous : std_logic;
signal receiveEOPAsynchronous : std_logic;
signal receiveByteAsynchronous : std_logic;
signal transmitEEPAsynchronous : std_logic;
signal transmitEOPAsynchronous : std_logic;
signal transmitByteAsynchronous : std_logic;
signal characterMonitor : std_logic_vector(6 downto 0);
begin
spaceWireReceiver : SpaceWireCODECIPReceiverSynchronize
generic map (
gDisconnectCountValue => gDisconnectCountValue
)
port map (
receiveClock => receiveClock,
spaceWireDataIn => spaceWireDataIn,
spaceWireStrobeIn => spaceWireStrobeIn,
receiveDataOut(7 downto 0) => receiveData,
receiveDataOut(8) => receiveDataControlFlag,
receiveDataValidOut => receiveByteAsynchronous,
receiveTimeCodeOut => receiveTimeCodeOut,
receiveFIFOWriteEnable => receiveFIFOWriteEnable0,
receiveFCTOut => gotFCT,
receiveTimeCodeValidOut => gotTimeCode,
receiveNCharacterOut => gotNCharacter,
receiveNullOut => gotNull,
receiveEEPOut => receiveEEPAsynchronous,
receiveEOPOut => receiveEOPAsynchronous,
receiveOffOut => receiveOff,
receiverErrorOut => receiveError,
parityErrorOut => parityError,
escapeErrorOut => escapeError,
disconnectErrorOut => disconnectError,
enableReceive => enableReceive,
spaceWireReset => spaceWireResetOutSignal
);
spaceWireTransmitter : SpaceWireCODECIPTransmitter
generic map (
gInitializeTransmitClockDivideValue => gTransmitClockDivideValue
)
port map (
transmitClock => transmitClock,
clock => clock,
receiveClock => receiveClock,
reset => reset,
spaceWireDataOut => spaceWireDataOut,
spaceWireStrobeOut => spaceWireStrobeOut,
tickIn => tickIn,
timeIn => timeIn,
controlFlagsIn => controlFlagsIn,
transmitDataEnable => transmitDataEnable,
transmitData => transmitData,
transmitDataControlFlag => transmitDataControlFlag,
transmitReady => transmitReady,
enableTransmit => enableTransmit,
--autoStart.
sendNulls => sendNulls,
sendFCTs => sendFCTs,
sendNCharacters => sendNCharactors,
sendTimeCodes => sendTimeCode,
--tx_fct.
gotFCT => gotFCT,
gotNCharacter => gotNCharacter,
receiveFIFOCount => receiveFIFOCount,
creditError => iCreditError,
transmitClockDivide => transmitClockDivideValue,
creditCountOut => creditCount,
outstandingCountOut => outstndingCount,
spaceWireResetOut => spaceWireResetOutSignal,
transmitEEPAsynchronous => transmitEEPAsynchronous,
transmitEOPAsynchronous => transmitEOPAsynchronous,
transmitByteAsynchronous => transmitByteAsynchronous
);
spaceWireStateMachine : SpaceWireCODECIPStateMachine
port map (
clock => clock,
receiveClock => receiveClock,
reset => reset,
after12p8us => after12p8us,
after6p4us => after6p4us,
linkStart => linkStart,
linkDisable => linkDisable,
autoStart => autoStart,
enableTransmit => enableTransmit,
sendNulls => sendNulls,
sendFCTs => sendFCTs,
sendNCharacter => sendNCharactors,
sendTimeCodes => sendTimeCode,
gotFCT => gotFCT,
gotTimeCode => gotTimeCode,
gotNCharacter => gotNCharacter,
gotNull => gotNull,
gotBit => iGotBit,
creditError => iCreditError,
receiveError => receiveError,
enableReceive => enableReceive,
characterSequenceError => characterSequenceError,
spaceWireResetOut => spaceWireResetOutSignal,
FIFOAvailable => FIFOAvailable,
timer6p4usReset => timer6p4usReset,
timer12p8usStart => timer12p8usStart,
linkUpTransitionSynchronize => linkUpTransitionSynchronize,
linkDownTransitionSynchronize => linkDownTransitionSynchronize,
linkUpEnable => linkUpEnable,
nullSynchronize => nullSynchronize,
fctSynchronize => fctSynchronize
);
spaceWireTimer : SpaceWireCODECIPTimer
generic map (
gTimer6p4usValue => gTimer6p4usValue,
gTimer12p8usValue => gTimer12p8usValue
)
port map (
clock => clock,
reset => reset,
timer6p4usReset => timer6p4usReset,
timer12p8usStart => timer12p8usStart,
after6p4us => after6p4us,
after12p8us => after12p8us
);
spaceWireStatisticalInformationCount : SpaceWireCODECIPStatisticalInformationCount
port map (
clock => clock,
reset => reset,
statisticalInformationClear => statisticalInformationClear,
transmitClock => transmitClock,
receiveClock => receiveClock,
receiveEEPAsynchronous => receiveEEPAsynchronous,
receiveEOPAsynchronous => receiveEOPAsynchronous,
receiveByteASynchronous => receiveByteAsynchronous,
transmitEEPAsynchronous => transmitEEPAsynchronous,
transmitEOPAsynchronous => transmitEOPAsynchronous,
transmitByteAsynchronous => transmitByteAsynchronous,
linkUpTransition => linkUpTransitionSynchronize,
linkDownTransition => linkDownTransitionSynchronize,
linkUpEnable => linkUpEnable,
nullSynchronous => nullSynchronize,
fctSynchronous => fctSynchronize,
statisticalInformation => statisticalInformation,
characterMonitor => characterMonitor
);
SpaceWireTimeCodeControl : SpaceWireCODECIPTimeCodeControl
port map (
clock => clock,
reset => reset,
receiveClock => receiveClock,
gotTimeCode => gotTimeCode,
receiveTimeCodeOut => receiveTimeCodeOut,
timeOut => timeOut,
controlFlagsOut => controlFlagsOut,
tickOut => tickOut
);
receiveFIFOWriteEnable1 <= iReceiveFIFOWriteEnable1;
iReceiveFIFOWriteEnable1 <= (receiveFIFOWriteEnable0 and sendNCharactors);
iGotBit <= not receiveOff;
spaceWireResetOut <= spaceWireResetOutSignal;
----------------------------------------------------------------------
-- Define status signal as LinkStatus or ErrorStatus.
----------------------------------------------------------------------
linkStatus (0) <= enableTransmit;
linkStatus (1) <= enableReceive;
linkStatus (2) <= sendNulls;
linkStatus (3) <= sendFCTs;
linkStatus (4) <= sendNCharactors;
linkStatus (5) <= sendTimeCode;
linkStatus (6) <= '0';
linkStatus (7) <= spaceWireResetOutSignal;
linkStatus (15 downto 8) <= "0" & characterMonitor;
errorStatus (0) <= characterSequenceError; --sequence.
errorStatus (1) <= iCreditError; --credit.
errorStatus (2) <= receiveError; --receiveError(=parity, discon or escape error)
errorStatus (3) <= '0';
errorStatus (4) <= parityError; -- parity.
errorStatus (5) <= disconnectError; -- disconnect.
errorStatus (6) <= escapeError; -- escape.
errorStatus (7) <= '0';
end Behavioral;
| gpl-3.0 | 7e0cd953083dd719c96c98def6983859 | 0.508964 | 4.967133 | false | false | false | false |
EliasLuiz/TCC | Leon3/lib/gaisler/arith/mul32.vhd | 1 | 15,135 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: mul
-- File: mul.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: This unit implements signed/unsigned 32-bit multiply module,
-- producing a 64-bit result.
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.config_types.all;
use grlib.config.all;
use grlib.stdlib.all;
use grlib.multlib.all;
library gaisler;
use gaisler.arith.all;
library techmap;
use techmap.gencomp.all;
entity mul32 is
generic (
tech : integer := 0;
multype : integer range 0 to 3 := 0;
pipe : integer range 0 to 1 := 0;
mac : integer range 0 to 1 := 0;
arch : integer range 0 to 3 := 0;
scantest: integer := 0
);
port (
rst : in std_ulogic;
clk : in std_ulogic;
holdn : in std_ulogic;
muli : in mul32_in_type;
mulo : out mul32_out_type;
testen : in std_ulogic := '0';
testrst : in std_ulogic := '1'
);
end;
architecture rtl of mul32 is
--attribute sync_set_reset : string;
--attribute sync_set_reset of rst : signal is "true";
constant m16x16 : integer := 0;
constant m32x8 : integer := 1;
constant m32x16 : integer := 2;
constant m32x32 : integer := 3;
constant MULTIPLIER : integer := multype;
constant MULPIPE : boolean := ((multype = 0) or (multype = 3)) and (pipe = 1);
constant MACEN : boolean := (multype = 0) and (mac = 1);
type mul_regtype is record
acc : std_logic_vector(63 downto 0);
state : std_logic_vector(1 downto 0);
start : std_logic;
ready : std_logic;
nready : std_logic;
end record;
type mac_regtype is record
mmac, xmac : std_logic;
msigned, xsigned : std_logic;
end record;
constant RESET_ALL : boolean := GRLIB_CONFIG_ARRAY(grlib_sync_reset_enable_all) = 1;
constant ASYNC_RESET : boolean := GRLIB_CONFIG_ARRAY(grlib_async_reset_enable) = 1;
constant MULRES : mul_regtype := (
acc => (others => '0'),
state => (others => '0'),
start => '0',
ready => '0',
nready => '0');
constant MACRES : mac_regtype := (
mmac => '0',
xmac => '0',
msigned => '0',
xsigned => '0');
signal arst : std_ulogic;
signal rm, rmin : mul_regtype;
signal mm, mmin : mac_regtype;
signal ma, mb : std_logic_vector(32 downto 0);
signal prod : std_logic_vector(65 downto 0);
signal mreg : std_logic_vector(49 downto 0);
signal vcc : std_logic;
begin
vcc <= '1';
arst <= testrst when (ASYNC_RESET and scantest/=0 and testen/='0') else
rst when ASYNC_RESET else
'1';
mulcomb : process(rst, rm, muli, mreg, prod, mm)
variable mop1, mop2 : std_logic_vector(32 downto 0);
variable acc, acc1, acc2 : std_logic_vector(48 downto 0);
variable zero, rsigned, rmac : std_logic;
variable v : mul_regtype;
variable w : mac_regtype;
constant CZero: std_logic_vector(47 downto 0) := "000000000000000000000000000000000000000000000000";
begin
v := rm; w := mm; v.start := muli.start; v.ready := '0'; v.nready := '0';
mop1 := muli.op1; mop2 := muli.op2;
acc1 := (others => '0'); acc2 := (others => '0'); zero := '0';
w.mmac := muli.mac; w.xmac := mm.mmac;
w.msigned := muli.signed; w.xsigned := mm.msigned;
if MULPIPE then rsigned := mm.xsigned; rmac := mm.xmac;
else rsigned := mm.msigned; rmac := mm.mmac; end if;
-- select input 2 to accumulator
case MULTIPLIER is
when m16x16 =>
acc2(32 downto 0) := mreg(32 downto 0);
when m32x8 =>
acc2(40 downto 0) := mreg(40 downto 0);
when m32x16 =>
acc2(48 downto 0) := mreg(48 downto 0);
when others => null;
end case;
-- state machine + inputs to multiplier and accumulator input 1
case rm.state is
when "00" =>
case MULTIPLIER is
when m16x16 =>
mop1(16 downto 0) := '0' & muli.op1(15 downto 0);
mop2(16 downto 0) := '0' & muli.op2(15 downto 0);
if MULPIPE and (rm.ready = '1' ) then
acc1(32 downto 0) := rm.acc(48 downto 16);
else acc1(32 downto 0) := '0' & rm.acc(63 downto 32); end if;
when m32x8 =>
mop1 := muli.op1;
mop2(8 downto 0) := '0' & muli.op2(7 downto 0);
acc1(40 downto 0) := '0' & rm.acc(63 downto 24);
when m32x16 =>
mop1 := muli.op1;
mop2(16 downto 0) := '0' & muli.op2(15 downto 0);
acc1(48 downto 0) := '0' & rm.acc(63 downto 16);
when others => null;
end case;
if (rm.start = '1') then v.state := "01"; end if;
when "01" =>
case MULTIPLIER is
when m16x16 =>
mop1(16 downto 0) := muli.op1(32 downto 16);
mop2(16 downto 0) := '0' & muli.op2(15 downto 0);
if MULPIPE then acc1(32 downto 0) := '0' & rm.acc(63 downto 32); end if;
v.state := "10";
when m32x8 =>
mop1 := muli.op1; mop2(8 downto 0) := '0' & muli.op2(15 downto 8);
v.state := "10";
when m32x16 =>
mop1 := muli.op1; mop2(16 downto 0) := muli.op2(32 downto 16);
v.state := "00";
when others => null;
end case;
when "10" =>
case MULTIPLIER is
when m16x16 =>
mop1(16 downto 0) := '0' & muli.op1(15 downto 0);
mop2(16 downto 0) := muli.op2(32 downto 16);
if MULPIPE then acc1 := (others => '0'); acc2 := (others => '0');
else acc1(32 downto 0) := rm.acc(48 downto 16); end if;
v.state := "11";
when m32x8 =>
mop1 := muli.op1; mop2(8 downto 0) := '0' & muli.op2(23 downto 16);
acc1(40 downto 0) := rm.acc(48 downto 8);
v.state := "11";
when others => null;
end case;
when others =>
case MULTIPLIER is
when m16x16 =>
mop1(16 downto 0) := muli.op1(32 downto 16);
mop2(16 downto 0) := muli.op2(32 downto 16);
if MULPIPE then acc1(32 downto 0) := rm.acc(48 downto 16);
else acc1(32 downto 0) := rm.acc(48 downto 16); end if;
v.state := "00";
when m32x8 =>
mop1 := muli.op1; mop2(8 downto 0) := muli.op2(32 downto 24);
acc1(40 downto 0) := rm.acc(56 downto 16);
v.state := "00";
when others => null;
end case;
end case;
-- optional UMAC/SMAC support
if MACEN then
if ((muli.mac and muli.signed) = '1') then
mop1(16) := muli.op1(15); mop2(16) := muli.op2(15);
end if;
if rmac = '1' then
acc1(32 downto 0) := muli.acc(32 downto 0);--muli.y(0) & muli.asr18;
if rsigned = '1' then acc2(39 downto 32) := (others => mreg(31));
else acc2(39 downto 32) := (others => '0'); end if;
end if;
acc1(39 downto 33) := muli.acc(39 downto 33);--muli.y(7 downto 1);
end if;
-- accumulator for iterative multiplication (and MAC)
-- pragma translate_off
if not (is_x(acc1 & acc2)) then
-- pragma translate_on
case MULTIPLIER is
when m16x16 =>
if MACEN then
acc(39 downto 0) := acc1(39 downto 0) + acc2(39 downto 0);
else
acc(32 downto 0) := acc1(32 downto 0) + acc2(32 downto 0);
end if;
when m32x8 =>
acc(40 downto 0) := acc1(40 downto 0) + acc2(40 downto 0);
when m32x16 =>
acc(48 downto 0) := acc1(48 downto 0) + acc2(48 downto 0);
when m32x32 =>
v.acc(31 downto 0) := prod(63 downto 32);
when others => null;
end case;
-- pragma translate_off
end if;
-- pragma translate_on
-- save intermediate result to accumulator
case rm.state is
when "00" =>
case MULTIPLIER is
when m16x16 =>
if MULPIPE and (rm.ready = '1' ) then
v.acc(48 downto 16) := acc(32 downto 0);
if rsigned = '1' then
v.acc(63 downto 49) := (others => acc(32));
end if;
else
v.acc(63 downto 32) := acc(31 downto 0);
end if;
when m32x8 => v.acc(63 downto 24) := acc(39 downto 0);
when m32x16 => v.acc(63 downto 16) := acc(47 downto 0);
when others => null;
end case;
when "01" =>
case MULTIPLIER is
when m16x16 =>
if MULPIPE then v.acc := (others => '0');
else v.acc := CZero(31 downto 0) & mreg(31 downto 0); end if;
when m32x8 =>
v.acc := CZero(23 downto 0) & mreg(39 downto 0);
if muli.signed = '1' then v.acc(48 downto 40) := (others => acc(40)); end if;
when m32x16 =>
v.acc := CZero(15 downto 0) & mreg(47 downto 0); v.ready := '1';
if muli.signed = '1' then v.acc(63 downto 48) := (others => acc(48)); end if;
when others => null;
end case;
v.nready := '1';
when "10" =>
case MULTIPLIER is
when m16x16 =>
if MULPIPE then
v.acc := CZero(31 downto 0) & mreg(31 downto 0);
else
v.acc(48 downto 16) := acc(32 downto 0);
end if;
when m32x8 => v.acc(48 downto 8) := acc(40 downto 0);
if muli.signed = '1' then v.acc(56 downto 49) := (others => acc(40)); end if;
when others => null;
end case;
when others =>
case MULTIPLIER is
when m16x16 =>
if MULPIPE then
v.acc(48 downto 16) := acc(32 downto 0);
else
v.acc(48 downto 16) := acc(32 downto 0);
if rsigned = '1' then
v.acc(63 downto 49) := (others => acc(32));
end if;
end if;
v.ready := '1';
when m32x8 => v.acc(56 downto 16) := acc(40 downto 0); v.ready := '1';
if muli.signed = '1' then v.acc(63 downto 57) := (others => acc(40)); end if;
when others => null;
end case;
end case;
-- drive result and condition codes
if (muli.flush = '1') then v.state := "00"; v.start := '0'; end if;
if (not ASYNC_RESET) and (not RESET_ALL) and (rst = '0') then
v.nready := MULRES.nready; v.ready := MULRES.ready;
v.state := MULRES.state; v.start := MULRES.start;
end if;
rmin <= v; ma <= mop1; mb <= mop2; mmin <= w;
if MULPIPE then mulo.ready <= rm.ready; mulo.nready <= rm.nready;
else mulo.ready <= v.ready; mulo.nready <= v.nready; end if;
case MULTIPLIER is
when m16x16 =>
if rm.acc(31 downto 0) = CZero(31 downto 0) then zero := '1'; end if;
if MACEN and (rmac = '1') then
mulo.result(39 downto 0) <= acc(39 downto 0);
if rsigned = '1' then
mulo.result(63 downto 40) <= (others => acc(39));
else
mulo.result(63 downto 40) <= (others => '0');
end if;
else
mulo.result(39 downto 0) <= v.acc(39 downto 32) & rm.acc(31 downto 0);
mulo.result(63 downto 40) <= v.acc(63 downto 40);
end if;
mulo.icc <= rm.acc(31) & zero & "00";
when m32x8 =>
if (rm.acc(23 downto 0) = CZero(23 downto 0)) and
(v.acc(31 downto 24) = CZero(7 downto 0))
then zero := '1'; end if;
mulo.result <= v.acc(63 downto 24) & rm.acc(23 downto 0);
mulo.icc <= v.acc(31) & zero & "00";
when m32x16 =>
if (rm.acc(15 downto 0) = CZero(15 downto 0)) and
(v.acc(31 downto 16) = CZero(15 downto 0))
then zero := '1'; end if;
mulo.result <= v.acc(63 downto 16) & rm.acc(15 downto 0);
mulo.icc <= v.acc(31) & zero & "00";
when m32x32 =>
-- mulo.result <= rm.acc(31 downto 0) & prod(31 downto 0);
mulo.result <= prod(63 downto 0);
mulo.icc(1 downto 0) <= "00";
if prod(31 downto 0) = zero32 then mulo.icc(2) <= '1' ;
else mulo.icc(2) <= '0'; end if;
mulo.icc(3) <= prod(31);
when others => null;
mulo.result <= (others => '-');
mulo.icc <= (others => '-');
end case;
end process;
xm1616 : if MULTIPLIER = m16x16 generate
m1616 : techmult generic map (tech, arch, 17, 17, pipe+1, pipe)
port map (ma(16 downto 0), mb(16 downto 0), clk, holdn, vcc, prod(33 downto 0));
syncrregs : if not ASYNC_RESET generate
reg : process(clk)
begin
if rising_edge(clk) then
if (holdn = '1') then
mm <= mmin;
mreg(33 downto 0) <= prod(33 downto 0);
end if;
if RESET_ALL and (rst = '0') then
mm <= MACRES;
mreg(33 downto 0) <= (others => '0');
end if;
end if;
end process;
end generate syncrregs;
asyncrregs : if ASYNC_RESET generate
reg : process(clk, arst)
begin
if (arst = '0') then
mm <= MACRES;
mreg(33 downto 0) <= (others => '0');
elsif rising_edge(clk) then
if (holdn = '1') then
mm <= mmin;
mreg(33 downto 0) <= prod(33 downto 0);
end if;
end if;
end process;
end generate asyncrregs;
mreg(49 downto 34) <= (others => '0');
prod(65 downto 34) <= (others => '0');
end generate;
xm3208 : if MULTIPLIER = m32x8 generate
m3208 : techmult generic map (tech, arch, 33, 8, 2, 1)
port map (ma(32 downto 0), mb(8 downto 0), clk, holdn, vcc, mreg(41 downto 0));
mm <= ('0', '0', '0', '0');
mreg(49 downto 42) <= (others => '0');
prod <= (others => '0');
end generate;
xm3216 : if MULTIPLIER = m32x16 generate
m3216 : techmult generic map (tech, arch, 33, 17, 2, 1)
port map (ma(32 downto 0), mb(16 downto 0), clk, holdn, vcc, mreg(49 downto 0));
mm <= ('0', '0', '0', '0');
prod <= (others => '0');
end generate;
xm3232 : if MULTIPLIER = m32x32 generate
m3232 : techmult generic map (tech, arch, 33, 33, pipe+1, pipe)
port map (ma(32 downto 0), mb(32 downto 0), clk, holdn, vcc, prod(65 downto 0));
mm <= ('0', '0', '0', '0');
mreg <= (others => '0');
end generate;
syncrregs : if not ASYNC_RESET generate
reg : process(clk)
begin
if rising_edge(clk) then
if (holdn = '1') then rm <= rmin; end if;
if (rst = '0') then
if RESET_ALL then
rm <= MULRES;
else
rm.nready <= MULRES.nready; rm.ready <= MULRES.ready;
rm.state <= MULRES.state; rm.start <= MULRES.start;
end if;
end if;
end if;
end process;
end generate syncrregs;
asyncrregs : if ASYNC_RESET generate
reg : process(clk, arst)
begin
if (arst = '0') then
rm <= MULRES;
elsif rising_edge(clk) then
if (holdn = '1') then rm <= rmin; end if;
end if;
end process;
end generate asyncrregs;
end;
| gpl-3.0 | 7ae8d340e7a27b961974fb30d6588cd2 | 0.564718 | 3.227767 | false | false | false | false |
pwsoft/fpga_examples | rtl/designs/gigatron/gigatron_logic.vhd | 1 | 5,974 | -- -----------------------------------------------------------------------
--
-- Turbo Chameleon
--
-- Multi purpose FPGA expansion for the Commodore 64 computer
--
-- -----------------------------------------------------------------------
-- Copyright 2005-2021 by Peter Wendrich ([email protected])
-- http://www.syntiac.com/chameleon.html
--
-- This source file is free software: you can redistribute it and/or modify
-- it under the terms of the GNU Lesser General Public License as published
-- by the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This source file is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
-- -----------------------------------------------------------------------
--
-- Part of the Gigatron emulator.
-- TTL logic emulation.
--
-- -----------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-- -----------------------------------------------------------------------
entity gigatron_logic is
port (
clk : in std_logic;
reset : in std_logic;
tick : in std_logic;
rom_req : out std_logic;
rom_a : out unsigned(15 downto 0);
rom_q : in unsigned(15 downto 0);
sram_we : out std_logic;
sram_a : out unsigned(15 downto 0);
sram_d : out unsigned(7 downto 0);
sram_q : in unsigned(7 downto 0);
inport : in unsigned(7 downto 0);
outport : out unsigned(7 downto 0);
xoutport : out unsigned(7 downto 0)
);
end entity;
-- -----------------------------------------------------------------------
architecture rtl of gigatron_logic is
signal rom_req_reg : std_logic := '0';
signal sram_we_reg : std_logic := '0';
signal sram_a_reg : unsigned(sram_a'range) := (others => '0');
signal sram_d_reg : unsigned(sram_d'range) := (others => '0');
signal pc_reg : unsigned(15 downto 0) := (others => '0');
signal accu_reg : unsigned(7 downto 0) := (others => '0');
signal ir_reg : unsigned(7 downto 0) := (others => '0');
signal d_reg : unsigned(7 downto 0) := (others => '0');
signal x_reg : unsigned(7 downto 0) := (others => '0');
signal y_reg : unsigned(7 downto 0) := (others => '0');
signal out_reg : unsigned(7 downto 0) := (others => '0');
signal xout_reg : unsigned(7 downto 0) := (others => '0');
signal b_bus_reg : unsigned(7 downto 0) := (others => '0');
signal alu_reg : unsigned(7 downto 0) := (others => '0');
signal in_reg : unsigned(7 downto 0) := (others => '1');
signal flags_reg : unsigned(2 downto 0) := (others => '0');
begin
rom_req <= rom_req_reg;
rom_a <= pc_reg;
sram_we <= sram_we_reg;
sram_a <= sram_a_reg;
sram_d <= sram_d_reg;
outport <= out_reg;
xoutport <= xout_reg;
process(clk)
begin
if rising_edge(clk) then
in_reg <= inport;
end if;
end process;
process(clk)
begin
if rising_edge(clk) then
sram_we_reg <= '0';
if tick = '1' then
rom_req_reg <= not rom_req_reg;
ir_reg <= rom_q(7 downto 0);
d_reg <= rom_q(15 downto 8);
if ir_reg(7 downto 5) = "110" then
-- RAM write
sram_we_reg <= '1';
end if;
pc_reg <= pc_reg + 1;
if ir_reg(7 downto 5) = "111" then
-- Jump instruction
if ir_reg(4 downto 2) = 0 then
pc_reg <= y_reg & b_bus_reg;
elsif (ir_reg(4 downto 2) and flags_reg) /= 0 then
pc_reg(7 downto 0) <= b_bus_reg;
end if;
else
-- Only update registers when not a jump instruction
case ir_reg(4 downto 2) is
when "100" =>
x_reg <= alu_reg;
when "101" =>
y_reg <= alu_reg;
when "110" =>
if ir_reg(7 downto 5) /= "110" then
out_reg <= alu_reg;
if (out_reg(6) = '0') and (alu_reg(6) = '1') then
-- Rising edge on hsync, latch xout from accumulator
xout_reg <= accu_reg;
end if;
end if;
when "111" =>
if ir_reg(7 downto 5) /= "110" then
out_reg <= alu_reg;
if (out_reg(6) = '0') and (alu_reg(6) = '1') then
-- Rising edge on hsync, latch xout from accumulator
xout_reg <= accu_reg;
end if;
end if;
x_reg <= x_reg + 1;
when others =>
if ir_reg(7 downto 5) /= "110" then
accu_reg <= alu_reg;
end if;
end case;
end if;
end if;
case ir_reg(1 downto 0) is
when "00" => b_bus_reg <= d_reg;
when "01" => b_bus_reg <= sram_q;
when "10" => b_bus_reg <= accu_reg;
when others => b_bus_reg <= in_reg;
end case;
sram_a_reg <= X"00" & d_reg;
if ir_reg(7 downto 5) /= "111" then
case ir_reg(4 downto 2) is
when "001" => sram_a_reg(7 downto 0) <= x_reg;
when "010" => sram_a_reg(15 downto 8) <= y_reg;
when "011" => sram_a_reg <= y_reg & x_reg;
when "111" => sram_a_reg <= y_reg & x_reg;
when others => null;
end case;
end if;
sram_d_reg <= b_bus_reg;
alu_reg <= b_bus_reg;
case ir_reg(7 downto 5) is
when "001" => alu_reg <= accu_reg and b_bus_reg;
when "010" => alu_reg <= accu_reg or b_bus_reg;
when "011" => alu_reg <= accu_reg xor b_bus_reg;
when "100" => alu_reg <= accu_reg + b_bus_reg;
when "101" => alu_reg <= accu_reg - b_bus_reg;
when "110" => alu_reg <= accu_reg;
when "111" => alu_reg <= 0 - accu_reg;
when others => null;
end case;
-- Determine condition codes for branch instructions.
-- Not really implemented as condition "flags" as such as it directly uses the accumulator status.
if accu_reg = 0 then
flags_reg <= "100";
else
flags_reg <= "0" & accu_reg(7) & (not accu_reg(7));
end if;
if reset = '1' then
pc_reg <= (others => '0');
end if;
end if;
end process;
end architecture;
| lgpl-2.1 | 1e58f48bb6ec250b9cc96812f9faa452 | 0.55072 | 3.023279 | false | false | false | false |
EliasLuiz/TCC | Leon3/lib/techmap/umc18/pads_umc18.vhd | 1 | 8,560 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Package: umcpads_gen
-- File: umcpads_gen.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: UMC pad wrappers
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
package umcpads is
-- input pad
component ICMT3V port( A : in std_logic; Z : out std_logic); end component;
-- input pad with pull-up
component ICMT3VPU port( A : in std_logic; Z : out std_logic); end component;
-- input pad with pull-down
component ICMT3VPD port( A : in std_logic; Z : out std_logic); end component;
-- schmitt input pad
component ISTRT3V port( A : in std_logic; Z : out std_logic); end component;
-- output pads
component OCM3V4 port( Z : out std_logic; A : in std_logic); end component;
component OCM3V12 port( Z : out std_logic; A : in std_logic); end component;
component OCM3V24 port( Z : out std_logic; A : in std_logic); end component;
-- tri-state output pads
component OCMTR4 port( EN : in std_logic; A : in std_logic; Z : out std_logic); end component;
component OCMTR12 port( EN : in std_logic; A : in std_logic; Z : out std_logic); end component;
component OCMTR24 port( EN : in std_logic; A : in std_logic; Z : out std_logic); end component;
-- bidirectional pads
component BICM3V4 port( IO : inout std_logic; EN : in std_logic; A : in std_logic; Z : out std_logic); end component;
component BICM3V12 port( IO : inout std_logic; EN : in std_logic; A : in std_logic; Z : out std_logic); end component;
component BICM3V24 port( IO : inout std_logic; EN : in std_logic; A : in std_logic; Z : out std_logic); end component;
end;
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
-- pragma translate_off
library umc18;
use umc18.ICMT3V;
use umc18.ICMT3VPU;
use umc18.ICMT3VPD;
use umc18.ISTRT3V;
-- pragma translate_on
entity umc_inpad is
generic (level : integer := 0; voltage : integer := 0; filter : integer := 0);
port (pad : in std_logic; o : out std_logic);
end;
architecture rtl of umc_inpad is
component ICMT3V port( A : in std_logic; Z : out std_logic); end component;
component ICMT3VPU port( A : in std_logic; Z : out std_logic); end component;
component ICMT3VPD port( A : in std_logic; Z : out std_logic); end component;
component ISTRT3V port( A : in std_logic; Z : out std_logic); end component;
begin
norm : if filter = 0 generate
ip : ICMT3V port map (a => pad, z => o);
end generate;
pu : if filter = pullup generate
ip : ICMT3VPU port map (a => pad, z => o);
end generate;
pd : if filter = pulldown generate
ip : ICMT3VPD port map (a => pad, z => o);
end generate;
sch : if filter = schmitt generate
ip : ISTRT3V port map (a => pad, z => o);
end generate;
end;
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
-- pragma translate_off
library umc18;
use umc18.BICM3V4;
use umc18.BICM3V12;
use umc18.BICM3V24;
-- pragma translate_on
entity umc_iopad is
generic (level : integer := 0; slew : integer := 0;
voltage : integer := 0; strength : integer := 0);
port (pad : inout std_logic; i, en : in std_logic; o : out std_logic);
end ;
architecture rtl of umc_iopad is
component BICM3V4 port( IO : inout std_logic; EN : in std_logic; A : in std_logic; Z : out std_logic); end component;
component BICM3V12 port( IO : inout std_logic; EN : in std_logic; A : in std_logic; Z : out std_logic); end component;
component BICM3V24 port( IO : inout std_logic; EN : in std_logic; A : in std_logic; Z : out std_logic); end component;
begin
f4 : if (strength <= 4) generate
op : BICM3V4 port map (a => i, en => en, io => pad, z => o);
end generate;
f12 : if (strength > 4) and (strength <= 12) generate
op : BICM3V12 port map (a => i, en => en, io => pad, z => o);
end generate;
f24 : if (strength > 16) generate
op : BICM3V24 port map (a => i, en => en, io => pad, z => o);
end generate;
end;
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
-- pragma translate_off
library umc18;
use umc18.OCM3V4;
use umc18.OCM3V12;
use umc18.OCM3V24;
-- pragma translate_on
entity umc_outpad is
generic (level : integer := 0; slew : integer := 0;
voltage : integer := 0; strength : integer := 0);
port (pad : out std_logic; i : in std_logic);
end ;
architecture rtl of umc_outpad is
component OCM3V4 port( Z : out std_logic; A : in std_logic); end component;
component OCM3V12 port( Z : out std_logic; A : in std_logic); end component;
component OCM3V24 port( Z : out std_logic; A : in std_logic); end component;
begin
f4 : if (strength <= 4) generate
op : OCM3V4 port map (a => i, z => pad);
end generate;
f12 : if (strength > 4) and (strength <= 12) generate
op : OCM3V12 port map (a => i, z => pad);
end generate;
f24 : if (strength > 12) generate
op : OCM3V24 port map (a => i, z => pad);
end generate;
end;
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
-- pragma translate_off
library umc18;
use umc18.OCMTR4;
use umc18.OCMTR12;
use umc18.OCMTR24;
-- pragma translate_on
entity umc_toutpad is
generic (level : integer := 0; slew : integer := 0;
voltage : integer := 0; strength : integer := 0);
port (pad : out std_logic; i, en : in std_logic);
end ;
architecture rtl of umc_toutpad is
component OCMTR4 port( EN : in std_logic; A : in std_logic; Z : out std_logic); end component;
component OCMTR12 port( EN : in std_logic; A : in std_logic; Z : out std_logic); end component;
component OCMTR24 port( EN : in std_logic; A : in std_logic; Z : out std_logic); end component;
begin
f4 : if (strength <= 4) generate
op : OCMTR4 port map (a => i, en => en, z => pad);
end generate;
f12 : if (strength > 4) and (strength <= 12) generate
op : OCMTR12 port map (a => i, en => en, z => pad);
end generate;
f24 : if (strength > 12) generate
op : OCMTR24 port map (a => i, en => en, z => pad);
end generate;
end;
library umc18;
-- pragma translate_off
use umc18.LVDS_Driver;
use umc18.LVDS_Receiver;
use umc18.LVDS_Biasmodule;
-- pragma translate_on
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
entity umc_lvds_combo is
generic (voltage : integer := 0; width : integer := 1);
port (odpadp, odpadn, ospadp, ospadn : out std_logic_vector(0 to width-1);
odval, osval, en : in std_logic_vector(0 to width-1);
idpadp, idpadn, ispadp, ispadn : in std_logic_vector(0 to width-1);
idval, isval : out std_logic_vector(0 to width-1);
lvdsref : in std_logic);
end ;
architecture rtl of umc_lvds_combo is
component LVDS_Driver port ( A, Vref, HI : in std_logic; Z, ZN : out std_logic); end component;
component LVDS_Receiver port ( A, AN : in std_logic; Z : out std_logic); end component;
component LVDS_Biasmodule port ( RefR : in std_logic; Vref, HI : out std_logic); end component;
signal vref, hi : std_logic;
begin
lvds_bias: LVDS_Biasmodule port map (lvdsref, vref, hi);
swloop : for i in 0 to width-1 generate
spw_rxd_pad : LVDS_Receiver port map (idpadp(i), idpadn(i), idval(i));
spw_rxs_pad : LVDS_Receiver port map (ispadp(i), ispadn(i), isval(i));
spw_txd_pad : LVDS_Driver port map (odval(i), vref, hi, odpadp(i), odpadn(i));
spw_txs_pad : LVDS_Driver port map (osval(i), vref, hi, ospadp(i), ospadn(i));
end generate;
end;
| gpl-3.0 | 4e0142e5a410f901cb7a31a9c89da722 | 0.653621 | 3.254753 | false | false | false | false |
GLADICOS/SPACEWIRESYSTEMC | altera_work/spw_light/spw_light/spw_light_inst.vhd | 1 | 11,712 | component spw_light is
port (
autostart_external_connection_export : out std_logic; -- export
clk_clk : in std_logic := 'X'; -- clk
connecting_external_connection_export : in std_logic := 'X'; -- export
ctrl_in_external_connection_export : out std_logic_vector(1 downto 0); -- export
ctrl_out_external_connection_export : in std_logic_vector(1 downto 0) := (others => 'X'); -- export
errcred_external_connection_export : in std_logic := 'X'; -- export
errdisc_external_connection_export : in std_logic := 'X'; -- export
erresc_external_connection_export : in std_logic := 'X'; -- export
errpar_external_connection_export : in std_logic := 'X'; -- export
linkdis_external_connection_export : out std_logic; -- export
linkstart_external_connection_export : out std_logic; -- export
memory_mem_a : out std_logic_vector(12 downto 0); -- mem_a
memory_mem_ba : out std_logic_vector(2 downto 0); -- mem_ba
memory_mem_ck : out std_logic; -- mem_ck
memory_mem_ck_n : out std_logic; -- mem_ck_n
memory_mem_cke : out std_logic; -- mem_cke
memory_mem_cs_n : out std_logic; -- mem_cs_n
memory_mem_ras_n : out std_logic; -- mem_ras_n
memory_mem_cas_n : out std_logic; -- mem_cas_n
memory_mem_we_n : out std_logic; -- mem_we_n
memory_mem_reset_n : out std_logic; -- mem_reset_n
memory_mem_dq : inout std_logic_vector(7 downto 0) := (others => 'X'); -- mem_dq
memory_mem_dqs : inout std_logic := 'X'; -- mem_dqs
memory_mem_dqs_n : inout std_logic := 'X'; -- mem_dqs_n
memory_mem_odt : out std_logic; -- mem_odt
memory_mem_dm : out std_logic; -- mem_dm
memory_oct_rzqin : in std_logic := 'X'; -- oct_rzqin
pll_0_locked_export : out std_logic; -- export
pll_0_outclk0_clk : out std_logic; -- clk
reset_reset_n : in std_logic := 'X'; -- reset_n
running_external_connection_export : in std_logic := 'X'; -- export
rxdata_external_connection_export : in std_logic_vector(7 downto 0) := (others => 'X'); -- export
rxflag_external_connection_export : in std_logic := 'X'; -- export
rxhalff_external_connection_export : in std_logic := 'X'; -- export
rxread_external_connection_export : out std_logic; -- export
rxvalid_external_connection_export : in std_logic := 'X'; -- export
started_external_connection_export : in std_logic := 'X'; -- export
tick_in_external_connection_export : out std_logic; -- export
tick_out_external_connection_export : in std_logic := 'X'; -- export
time_in_external_connection_export : out std_logic_vector(5 downto 0); -- export
time_out_external_connection_export : in std_logic_vector(5 downto 0) := (others => 'X'); -- export
txdata_external_connection_export : out std_logic_vector(7 downto 0); -- export
txdivcnt_external_connection_export : out std_logic_vector(7 downto 0); -- export
txflag_external_connection_export : out std_logic; -- export
txhalff_external_connection_export : in std_logic := 'X'; -- export
txrdy_external_connection_export : in std_logic := 'X'; -- export
txwrite_external_connection_export : out std_logic -- export
);
end component spw_light;
u0 : component spw_light
port map (
autostart_external_connection_export => CONNECTED_TO_autostart_external_connection_export, -- autostart_external_connection.export
clk_clk => CONNECTED_TO_clk_clk, -- clk.clk
connecting_external_connection_export => CONNECTED_TO_connecting_external_connection_export, -- connecting_external_connection.export
ctrl_in_external_connection_export => CONNECTED_TO_ctrl_in_external_connection_export, -- ctrl_in_external_connection.export
ctrl_out_external_connection_export => CONNECTED_TO_ctrl_out_external_connection_export, -- ctrl_out_external_connection.export
errcred_external_connection_export => CONNECTED_TO_errcred_external_connection_export, -- errcred_external_connection.export
errdisc_external_connection_export => CONNECTED_TO_errdisc_external_connection_export, -- errdisc_external_connection.export
erresc_external_connection_export => CONNECTED_TO_erresc_external_connection_export, -- erresc_external_connection.export
errpar_external_connection_export => CONNECTED_TO_errpar_external_connection_export, -- errpar_external_connection.export
linkdis_external_connection_export => CONNECTED_TO_linkdis_external_connection_export, -- linkdis_external_connection.export
linkstart_external_connection_export => CONNECTED_TO_linkstart_external_connection_export, -- linkstart_external_connection.export
memory_mem_a => CONNECTED_TO_memory_mem_a, -- memory.mem_a
memory_mem_ba => CONNECTED_TO_memory_mem_ba, -- .mem_ba
memory_mem_ck => CONNECTED_TO_memory_mem_ck, -- .mem_ck
memory_mem_ck_n => CONNECTED_TO_memory_mem_ck_n, -- .mem_ck_n
memory_mem_cke => CONNECTED_TO_memory_mem_cke, -- .mem_cke
memory_mem_cs_n => CONNECTED_TO_memory_mem_cs_n, -- .mem_cs_n
memory_mem_ras_n => CONNECTED_TO_memory_mem_ras_n, -- .mem_ras_n
memory_mem_cas_n => CONNECTED_TO_memory_mem_cas_n, -- .mem_cas_n
memory_mem_we_n => CONNECTED_TO_memory_mem_we_n, -- .mem_we_n
memory_mem_reset_n => CONNECTED_TO_memory_mem_reset_n, -- .mem_reset_n
memory_mem_dq => CONNECTED_TO_memory_mem_dq, -- .mem_dq
memory_mem_dqs => CONNECTED_TO_memory_mem_dqs, -- .mem_dqs
memory_mem_dqs_n => CONNECTED_TO_memory_mem_dqs_n, -- .mem_dqs_n
memory_mem_odt => CONNECTED_TO_memory_mem_odt, -- .mem_odt
memory_mem_dm => CONNECTED_TO_memory_mem_dm, -- .mem_dm
memory_oct_rzqin => CONNECTED_TO_memory_oct_rzqin, -- .oct_rzqin
pll_0_locked_export => CONNECTED_TO_pll_0_locked_export, -- pll_0_locked.export
pll_0_outclk0_clk => CONNECTED_TO_pll_0_outclk0_clk, -- pll_0_outclk0.clk
reset_reset_n => CONNECTED_TO_reset_reset_n, -- reset.reset_n
running_external_connection_export => CONNECTED_TO_running_external_connection_export, -- running_external_connection.export
rxdata_external_connection_export => CONNECTED_TO_rxdata_external_connection_export, -- rxdata_external_connection.export
rxflag_external_connection_export => CONNECTED_TO_rxflag_external_connection_export, -- rxflag_external_connection.export
rxhalff_external_connection_export => CONNECTED_TO_rxhalff_external_connection_export, -- rxhalff_external_connection.export
rxread_external_connection_export => CONNECTED_TO_rxread_external_connection_export, -- rxread_external_connection.export
rxvalid_external_connection_export => CONNECTED_TO_rxvalid_external_connection_export, -- rxvalid_external_connection.export
started_external_connection_export => CONNECTED_TO_started_external_connection_export, -- started_external_connection.export
tick_in_external_connection_export => CONNECTED_TO_tick_in_external_connection_export, -- tick_in_external_connection.export
tick_out_external_connection_export => CONNECTED_TO_tick_out_external_connection_export, -- tick_out_external_connection.export
time_in_external_connection_export => CONNECTED_TO_time_in_external_connection_export, -- time_in_external_connection.export
time_out_external_connection_export => CONNECTED_TO_time_out_external_connection_export, -- time_out_external_connection.export
txdata_external_connection_export => CONNECTED_TO_txdata_external_connection_export, -- txdata_external_connection.export
txdivcnt_external_connection_export => CONNECTED_TO_txdivcnt_external_connection_export, -- txdivcnt_external_connection.export
txflag_external_connection_export => CONNECTED_TO_txflag_external_connection_export, -- txflag_external_connection.export
txhalff_external_connection_export => CONNECTED_TO_txhalff_external_connection_export, -- txhalff_external_connection.export
txrdy_external_connection_export => CONNECTED_TO_txrdy_external_connection_export, -- txrdy_external_connection.export
txwrite_external_connection_export => CONNECTED_TO_txwrite_external_connection_export -- txwrite_external_connection.export
);
| gpl-3.0 | 7cc8c9e4360e018acdc3d49df0cdcf76 | 0.491889 | 4.285401 | false | false | false | false |
EliasLuiz/TCC | Leon3/lib/gaisler/spi/spimctrl.vhd | 1 | 39,273 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-------------------------------------------------------------------------------
-- Entity: spimctrl
-- File: spimctrl.vhd
-- Author: Jan Andersson - Aeroflex Gaisler AB
-- [email protected]
--
-- Description: SPI flash memory controller. Supports a wide range of SPI
-- memory devices with the data read instruction configurable via
-- generics. Also has limited support for initializing and reading
-- SD Cards in SPI mode.
--
-- The controller has two memory areas. The flash area where the flash memory
-- is directly mapped and the I/O area where core registers are mapped.
--
-- Revision 1 added support for burst reads when sdcard = 0
--
-- Post revision 1: Remove support for SD card by commenting out code
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.devices.all;
use grlib.stdlib.all;
library gaisler;
use gaisler.spi.all;
entity spimctrl is
generic (
hindex : integer := 0; -- AHB slave index
hirq : integer := 0; -- Interrupt line
faddr : integer := 16#000#; -- Flash map base address
fmask : integer := 16#fff#; -- Flash area mask
ioaddr : integer := 16#000#; -- I/O base address
iomask : integer := 16#fff#; -- I/O mask
spliten : integer := 0; -- AMBA SPLIT support
oepol : integer := 0; -- Output enable polarity
sdcard : integer range 0 to 0 := 0; -- Unused
readcmd : integer range 0 to 255 := 16#0B#; -- Mem. dev. READ command
dummybyte : integer range 0 to 1 := 1; -- Dummy byte after cmd
dualoutput : integer range 0 to 1 := 0; -- Enable dual output
scaler : integer range 1 to 512 := 1; -- SCK scaler
altscaler : integer range 1 to 512 := 1; -- Alternate SCK scaler
pwrupcnt : integer := 0; -- System clock cycles to init
maxahbaccsz : integer range 0 to 256 := AHBDW; -- Max AHB access size
offset : integer := 0
);
port (
rstn : in std_ulogic;
clk : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
spii : in spimctrl_in_type;
spio : out spimctrl_out_type
);
end spimctrl;
architecture rtl of spimctrl is
constant REVISION : amba_version_type := 1;
constant HCONFIG : ahb_config_type := (
0 => ahb_device_reg(VENDOR_GAISLER, GAISLER_SPIMCTRL, 0, REVISION, hirq),
4 => ahb_iobar(ioaddr, iomask),
5 => ahb_membar(faddr, '1', '1', fmask),
others => zero32);
-- BANKs
constant CTRL_BANK : integer := 0;
constant FLASH_BANK : integer := 1;
constant MAXDW : integer := maxahbaccsz;
-----------------------------------------------------------------------------
-- SD card constants
-----------------------------------------------------------------------------
-- constant SD_BLEN : integer := 4;
-- constant SD_CRC_BYTE : std_logic_vector(7 downto 0) := X"95";
-- constant SD_BLOCKLEN : std_logic_vector(31 downto 0) :=
-- conv_std_logic_vector(SD_BLEN, 32);
-- -- Commands
-- constant SD_CMD0 : std_logic_vector(5 downto 0) := "000000";
-- constant SD_CMD16 : std_logic_vector(5 downto 0) := "010000";
-- constant SD_CMD17 : std_logic_vector(5 downto 0) := "010001";
-- constant SD_CMD55 : std_logic_vector(5 downto 0) := "110111";
-- constant SD_ACMD41 : std_logic_vector(5 downto 0) := "101001";
-- -- Command timeout
-- constant SD_CMD_TIMEOUT : integer := 100;
-- -- Data token timeout
-- constant SD_DATATOK_TIMEOUT : integer := 312500;
-----------------------------------------------------------------------------
-- SPI device constants
-----------------------------------------------------------------------------
-- Length of read instruction argument-1
constant SPI_ARG_LEN : integer := 2 + dummybyte;
-----------------------------------------------------------------------------
-- Core constants
-----------------------------------------------------------------------------
-- OEN
constant OUTPUT : std_ulogic := conv_std_logic(oepol = 1); -- Enable outputs
constant INPUT : std_ulogic := not OUTPUT; -- Tri-state outputs
-- Register offsets
constant CONF_REG_OFF : std_logic_vector(7 downto 2) := "000000";
constant CTRL_REG_OFF : std_logic_vector(7 downto 2) := "000001";
constant STAT_REG_OFF : std_logic_vector(7 downto 2) := "000010";
constant RX_REG_OFF : std_logic_vector(7 downto 2) := "000011";
constant TX_REG_OFF : std_logic_vector(7 downto 2) := "000100";
-----------------------------------------------------------------------------
-- Subprograms
-----------------------------------------------------------------------------
-- Description: Determines required size of timer used for clock scaling
function timer_size
return integer is
begin -- timer_size
if altscaler > scaler then
return altscaler;
end if;
return scaler;
end timer_size;
-- Description: Returns the number of bits required for the haddr vector to
-- be able to save the Flash area address.
function req_addr_bits
return integer is
begin -- req_addr_bits
case fmask is
when 16#fff# => return 20;
when 16#ffe# => return 21;
when 16#ffc# => return 22;
when 16#ff8# => return 23;
when 16#ff0# => return 24;
when 16#fe0# => return 25;
when 16#fc0# => return 26;
when 16#f80# => return 27;
when 16#f00# => return 28;
when 16#e00# => return 29;
when 16#c00# => return 30;
when others => return 31;
end case;
end req_addr_bits;
-- Description: Returns true if SCK clock should transition
function sck_toggle (
curr : std_logic_vector((timer_size-1) downto 0);
last : std_logic_vector((timer_size-1) downto 0);
usealtscaler : boolean)
return boolean is
begin -- sck_toggle
if usealtscaler then
return (curr(altscaler-1) xor last(altscaler-1)) = '1';
end if;
return (curr(scaler-1) xor last(scaler-1)) = '1';
end sck_toggle;
-- Description: Short for conv_std_logic_vector, avoiding an alias
function cslv (
i : integer;
w : integer)
return std_logic_vector is
begin -- cslv
return conv_std_logic_vector(i,w);
end cslv;
-- Description: Calculates value for spi.cnt based on AMBA HSIZE
function calc_spi_cnt (
hsize : std_logic_vector(2 downto 0))
return std_logic_vector is
variable cnt : std_logic_vector(4 downto 0) := (others => '0');
begin -- calc_spi_cnt
for i in 0 to 4 loop
if i < conv_integer(hsize) then
cnt(i) := '1';
end if;
end loop; -- i
return cnt;
end calc_spi_cnt;
-----------------------------------------------------------------------------
-- States
-----------------------------------------------------------------------------
-- Main FSM states
type spimstate_type is (IDLE, AHB_RESPOND, USER_SPI, BUSY);
-- SPI device FSM states
type spistate_type is (SPI_PWRUP, SPI_READY, SPI_READ, SPI_ADDR, SPI_DATA);
-- SD FSM states
type sdstate_type is (SD_CHECK_PRES, SD_PWRUP0, SD_PWRUP1, SD_INIT_IDLE,
SD_ISS_ACMD41, SD_CHECK_CMD16, SD_READY,
SD_CHECK_CMD17, SD_CHECK_TOKEN, SD_HANDLE_DATA,
SD_SEND_CMD, SD_GET_RESP);
-----------------------------------------------------------------------------
-- Types
-----------------------------------------------------------------------------
type spim_ctrl_reg_type is record -- Control register
eas : std_ulogic; -- Enable alternate scaler
ien : std_ulogic; -- Interrupt enable
usrc : std_ulogic; -- User mode
end record;
type spim_stat_reg_type is record -- Status register
busy : std_ulogic; -- Core busy
done : std_ulogic; -- User operation done
end record;
type spim_regif_type is record -- Register bank
ctrl : spim_ctrl_reg_type; -- Control register
stat : spim_stat_reg_type; -- Status register
end record;
-- type sdcard_type is record -- Present when SD card
-- state : sdstate_type; -- SD state
-- tcnt : std_logic_vector(2 downto 0); -- Transmit count
-- rcnt : std_logic_vector(3 downto 0); -- Receive count
-- cmd : std_logic_vector(5 downto 0); -- SD command
-- rstate : sdstate_type; -- Return state
-- htb : std_ulogic; -- Handle trailing byte
-- vresp : std_ulogic; -- Valid response
-- cd : std_ulogic; -- Synchronized card detect
-- timeout : std_ulogic; -- Timeout status bit
-- dtocnt : std_logic_vector(18 downto 0); -- Data token timeout counter
-- ctocnt : std_logic_vector(6 downto 0); -- CMD resp. timeout counter
-- end record;
type spiflash_type is record -- Present when !SD card
state : spistate_type; -- Mem. device comm. state
cnt : std_logic_vector(4 downto 0); -- Generic counter
hsize : std_logic_vector(2 downto 0); -- Size of access
hburst : std_logic_vector(0 downto 0); -- Incremental burst
end record;
type spimctrl_in_array is array (1 downto 0) of spimctrl_in_type;
type spim_reg_type is record
-- Common
spimstate : spimstate_type; -- Main FSM
rst : std_ulogic; -- Reset
reg : spim_regif_type; -- Register bank
timer : std_logic_vector((timer_size-1) downto 0);
sample : std_logic_vector(1 downto 0); -- Sample data line
bd : std_ulogic;
sreg : std_logic_vector(7 downto 0); -- Shiftreg
bcnt : std_logic_vector(2 downto 0); -- Bit counter
go : std_ulogic; -- SPI comm. active
stop : std_ulogic; -- Stop SPI comm.
ar : std_logic_vector(MAXDW-1 downto 0); -- argument/response
hold : std_ulogic; -- Do not shift ar
insplit : std_ulogic; -- SPLIT response issued
unsplit : std_ulogic; -- SPLIT complete not issued
-- SPI flash device
spi : spiflash_type; -- Used when !SD card
-- SD
-- sd : sdcard_type; -- Used when SD card
-- AHB
irq : std_ulogic; -- Interrupt request
hsize : std_logic_vector(2 downto 0);
hwrite : std_ulogic;
hsel : std_ulogic;
hmbsel : std_logic_vector(0 to 1);
haddr : std_logic_vector((req_addr_bits-1) downto 0);
hready : std_ulogic;
frdata : std_logic_vector(MAXDW-1 downto 0); -- Flash response data
rrdata : std_logic_vector(7 downto 0); -- Register response data
hresp : std_logic_vector(1 downto 0);
splmst : std_logic_vector(log2(NAHBMST)-1 downto 0); -- SPLIT:ed master
hsplit : std_logic_vector(NAHBMST-1 downto 0); -- Other SPLIT:ed masters
ahbcancel : std_ulogic; -- Locked access cancels ongoing SPLIT
-- response
hburst : std_logic_vector(0 downto 0);
seq : std_ulogic; -- Sequential burst
-- Inputs and outputs
spii : spimctrl_in_array;
spio : spimctrl_out_type;
end record;
-----------------------------------------------------------------------------
-- Signals
-----------------------------------------------------------------------------
signal r, rin : spim_reg_type;
begin -- rtl
comb: process (r, rstn, ahbsi, spii)
variable v : spim_reg_type;
variable change : std_ulogic;
variable regaddr : std_logic_vector(7 downto 2);
variable hsplit : std_logic_vector(NAHBMST-1 downto 0);
variable ahbirq : std_logic_vector((NAHBIRQ-1) downto 0);
variable lastbit : std_ulogic;
variable enable_altscaler : boolean;
variable disable_flash : boolean;
variable read_flash : boolean;
variable hrdata : std_logic_vector(MAXDW-1 downto 0);
variable hwdatax : std_logic_vector(31 downto 0);
variable hwdata : std_logic_vector(7 downto 0);
begin -- process comb
v := r; v.spii := r.spii(0) & spii; v.sample := r.sample(0) & '0';
change := '0'; v.irq := '0'; v.hresp := HRESP_OKAY; v.hready := '1';
regaddr := r.haddr(7 downto 2); hsplit := (others => '0');
hwdatax := ahbreadword(ahbsi.hwdata, r.haddr(4 downto 2));
hwdata := hwdatax(7 downto 0);
ahbirq := (others => '0'); ahbirq(hirq) := r.irq;
-- if sdcard = 1 then v.sd.cd := r.spii(0).cd; else v.sd.cd := '0'; end if;
read_flash := false;
enable_altscaler := (not r.spio.initialized or r.reg.ctrl.eas) = '1';
-- disable_flash := (r.spio.errorn = '0' or r.reg.ctrl.usrc = '1' or
disable_flash := (r.reg.ctrl.usrc = '1' or
r.spio.initialized = '0' or r.spimstate = USER_SPI);
if dualoutput = 1 and sdcard = 0 then
lastbit := andv(r.bcnt(1 downto 0)) and
((r.spio.mosioen xnor INPUT) or r.bcnt(2));
else
lastbit := andv(r.bcnt);
end if;
v.bd := lastbit and r.sample(0);
---------------------------------------------------------------------------
-- AHB communication
---------------------------------------------------------------------------
if ahbsi.hready = '1' then
if (ahbsi.hsel(hindex) and ahbsi.htrans(1)) = '1' then
v.hmbsel := ahbsi.hmbsel(r.hmbsel'range);
if (spliten = 0 or r.spimstate /= AHB_RESPOND or
ahbsi.hmbsel(CTRL_BANK) = '1' or ahbsi.hmastlock = '1') then
-- Writes to register space have no wait state
v.hready := ahbsi.hmbsel(CTRL_BANK) and ahbsi.hwrite;
v.hsize := ahbsi.hsize;
v.hwrite := ahbsi.hwrite;
v.haddr := ahbsi.haddr(r.haddr'range);
v.hsel := '1';
if ahbsi.hmbsel(FLASH_BANK) = '1' then
if sdcard = 0 then
v.hburst(r.hburst'range) := ahbsi.hburst(r.hburst'range);
v.seq := ahbsi.htrans(0);
end if;
if ahbsi.hwrite = '1' or disable_flash then
v.hresp := HRESP_ERROR;
v.hsel := '0';
else
if spliten /= 0 then
if ahbsi.hmastlock = '0' then
v.hresp := HRESP_SPLIT;
v.splmst := ahbsi.hmaster;
v.unsplit := '1';
else
v.ahbcancel := r.insplit;
end if;
v.insplit := not ahbsi.hmastlock;
end if;
end if;
end if;
else
-- Core is busy, transfer is not locked and access was to flash
-- area. Respond with SPLIT or insert wait states
v.hready := '0';
if spliten /= 0 then
v.hresp := HRESP_SPLIT;
v.hsplit(conv_integer(ahbsi.hmaster)) := '1';
end if;
end if;
else
v.hsel := '0';
end if;
end if;
if (r.hready = '0') then
if (r.hresp = HRESP_OKAY) then v.hready := '0';
else v.hresp := r.hresp; end if;
end if;
-- Read access to core registers
if (r.hsel and r.hmbsel(CTRL_BANK) and not r.hwrite) = '1' then
v.rrdata := (others => '0');
v.hready := '1';
v.hsel := '0';
case regaddr is
when CONF_REG_OFF =>
-- if sdcard = 1 then
-- v.rrdata := (others => '0');
-- else
v.rrdata := cslv(readcmd, 8);
-- end if;
when CTRL_REG_OFF =>
v.rrdata(3) := r.spio.csn;
v.rrdata(2) := r.reg.ctrl.eas;
v.rrdata(1) := r.reg.ctrl.ien;
v.rrdata(0) := r.reg.ctrl.usrc;
when STAT_REG_OFF =>
-- v.rrdata(5) := r.sd.cd;
-- v.rrdata(4) := r.sd.timeout;
-- v.rrdata(3) := not r.spio.errorn;
v.rrdata(2) := r.spio.initialized;
v.rrdata(1) := r.reg.stat.busy;
v.rrdata(0) := r.reg.stat.done;
when RX_REG_OFF => v.rrdata := r.ar(7 downto 0);
when others => null;
end case;
end if;
-- Write access to core registers
if (r.hsel and r.hmbsel(CTRL_BANK) and r.hwrite) = '1' then
case regaddr is
when CTRL_REG_OFF =>
v.rst := hwdata(4);
if (r.reg.ctrl.usrc and not hwdata(0)) = '1' then
v.spio.csn := '1';
elsif hwdata(0) = '1' then
v.spio.csn := hwdata(3);
end if;
v.reg.ctrl.eas := hwdata(2);
v.reg.ctrl.ien := hwdata(1);
v.reg.ctrl.usrc := hwdata(0);
when STAT_REG_OFF =>
-- v.spio.errorn := r.spio.errorn or hwdata(3);
v.reg.stat.done := r.reg.stat.done and not hwdata(0);
when RX_REG_OFF => null;
when TX_REG_OFF =>
if r.reg.ctrl.usrc = '1' then
v.sreg := hwdata(7 downto 0);
end if;
when others => null;
end case;
end if;
---------------------------------------------------------------------------
-- SPIMCTRL control FSM
---------------------------------------------------------------------------
v.reg.stat.busy := '1';
case r.spimstate is
when BUSY =>
-- Wait for core to finish user mode access
if (r.go or r.spio.sck) = '0' then
v.spimstate := IDLE;
v.reg.stat.done:= '1';
v.irq := r.reg.ctrl.ien;
end if;
when AHB_RESPOND =>
if r.spio.ready = '1' then
if spliten /= 0 and r.unsplit = '1' then
hsplit(conv_integer(r.splmst)) := '1';
v.unsplit := '0';
end if;
if ((spliten = 0 or v.ahbcancel = '0') and
(spliten = 0 or ahbsi.hmaster = r.splmst or r.insplit = '0') and
(((ahbsi.hsel(hindex) and ahbsi.hready and ahbsi.htrans(1)) = '1') or
((spliten = 0 or r.insplit = '0') and r.hready = '0' and r.hresp = HRESP_OKAY))) then
v.spimstate := IDLE;
v.hresp := HRESP_OKAY;
if spliten /= 0 then
v.insplit := '0';
v.hsplit := r.hsplit;
end if;
v.hready := '1';
v.hsel := '0';
-- if r.spio.errorn = '0' then
-- v.hready := '0';
-- v.hresp := HRESP_ERROR;
-- end if;
elsif spliten /= 0 and v.ahbcancel = '1' then
v.spimstate := IDLE;
v.ahbcancel := '0';
end if;
end if;
when USER_SPI =>
if r.bd = '1' then
v.spimstate := BUSY;
v.hold := '1';
end if;
when others => -- IDLE
if spliten /= 0 and r.hresp /= HRESP_SPLIT then
hsplit := r.hsplit;
v.hsplit := (others => '0');
end if;
v.reg.stat.busy := '0';
if r.hsel = '1' then
if r.hmbsel(FLASH_BANK) = '1' then
-- Access to memory mapped flash area
v.spimstate := AHB_RESPOND;
read_flash := true;
elsif regaddr = TX_REG_OFF and (r.hwrite and r.reg.ctrl.usrc) = '1' then
-- Access to core transmit register
v.spimstate := USER_SPI;
v.go := '1';
v.stop := '1';
change := '1';
v.hold := '0';
if sdcard = 0 and dualoutput = 1 then
v.spio.mosioen := OUTPUT;
end if;
end if;
end if;
end case;
---------------------------------------------------------------------------
-- SD Card specific code
---------------------------------------------------------------------------
-- SD card initialization sequence:
-- * Check if card is present
-- * Perform power-up initialization sequence
-- * Issue CMD0 GO_IDLE_STATE
-- * Issue CMD55 APP_CMD
-- * Issue ACMD41 SEND_OP_COND
-- * Issue CMD16 SET_BLOCKLEN
-- if sdcard = 1 then
-- case r.sd.state is
-- when SD_PWRUP0 =>
-- v.go := '1';
-- v.sd.vresp := '1';
-- v.sd.state := SD_GET_RESP;
-- v.sd.rstate := SD_PWRUP1;
-- v.sd.rcnt := cslv(2, r.sd.rcnt'length);
-- when SD_PWRUP1 =>
-- v.sd.state := SD_SEND_CMD;
-- v.sd.rstate := SD_INIT_IDLE;
-- v.sd.cmd := SD_CMD0;
-- v.sd.rcnt := (others => '0');
-- v.ar := (others => '0');
-- when SD_INIT_IDLE =>
-- v.sd.state := SD_SEND_CMD;
-- v.sd.rcnt := (others => '0');
-- if r.ar(0) = '0' and r.sd.cmd /= SD_CMD0 then
-- v.sd.cmd := SD_CMD16;
-- v.ar := SD_BLOCKLEN;
-- v.sd.rstate := SD_CHECK_CMD16;
-- else
-- v.sd.cmd := SD_CMD55;
-- v.ar := (others => '0');
-- v.sd.rstate := SD_ISS_ACMD41;
-- end if;
-- when SD_ISS_ACMD41 =>
-- v.sd.state := SD_SEND_CMD;
-- v.sd.cmd := SD_ACMD41;
-- v.sd.rcnt := (others => '0');
-- v.ar := (others => '0');
-- v.sd.rstate := SD_INIT_IDLE;
-- when SD_CHECK_CMD16 =>
-- if r.ar(7 downto 0) /= zero32(7 downto 0) then
-- v.spio.errorn := '0';
-- else
-- v.spio.errorn := '1';
-- v.spio.initialized := '1';
-- v.sd.timeout := '0';
-- end if;
-- v.sd.state := SD_READY;
-- when SD_READY =>
-- v.spio.ready := '1';
-- v.sd.cmd := SD_CMD17;
-- v.sd.rstate := SD_CHECK_CMD17;
-- if read_flash then
-- v.sd.state := SD_SEND_CMD;
-- v.spio.ready := '0';
-- v.ar := (others => '0');
-- v.ar(r.haddr'left downto 2) := r.haddr(r.haddr'left downto 2);
-- end if;
-- when SD_CHECK_CMD17 =>
-- if r.ar(7 downto 0) /= X"00" then
-- v.sd.state := SD_READY;
-- v.spio.errorn := '0';
-- else
-- v.sd.rstate := SD_CHECK_TOKEN;
-- v.spio.csn := '0';
-- v.go := '1';
-- change := '1';
-- end if;
-- v.sd.dtocnt := cslv(SD_DATATOK_TIMEOUT, r.sd.dtocnt'length);
-- v.sd.state := SD_GET_RESP;
-- v.sd.vresp := '1';
-- v.hold := '0';
-- when SD_CHECK_TOKEN =>
-- if (r.ar(7 downto 5) = "111" and
-- r.sd.dtocnt /= zero32(r.sd.dtocnt'range)) then
-- v.sd.dtocnt := r.sd.dtocnt - 1;
-- v.sd.state := SD_GET_RESP;
-- if r.ar(0) = '0' then
-- v.sd.rstate := SD_HANDLE_DATA;
-- v.sd.rcnt := cslv(SD_BLEN-1, r.sd.rcnt'length);
-- end if;
-- v.spio.csn := '0';
-- v.go := '1';
-- change := '1';
-- else
-- v.spio.errorn := '0';
-- v.sd.state := SD_READY;
-- end if;
-- v.sd.timeout := not orv(r.sd.dtocnt);
-- v.sd.ctocnt := cslv(SD_CMD_TIMEOUT, r.sd.ctocnt'length);
-- v.hold := '0';
-- when SD_HANDLE_DATA =>
-- v.frdata := r.ar;
-- -- Receive and discard CRC
-- v.sd.state := SD_GET_RESP;
-- v.sd.rstate := SD_READY;
-- v.sd.htb := '1';
-- v.spio.csn := '0';
-- v.go := '1';
-- change := '1';
-- v.sd.vresp := '1';
-- v.spio.errorn := '1';
-- when SD_SEND_CMD =>
-- v.sd.htb := '1';
-- v.sd.vresp := '0';
-- v.spio.csn := '0';
-- v.sd.ctocnt := cslv(SD_CMD_TIMEOUT, r.sd.ctocnt'length);
-- if (v.bd or not r.go) = '1'then
-- v.hold := '0';
-- case r.sd.tcnt is
-- when "000" => v.sreg := "01" & r.sd.cmd;
-- v.hold := '1'; change := '1';
-- when "001" => v.sreg := r.ar(31 downto 24);
-- when "010" => v.sreg := r.ar(30 downto 23);
-- when "011" => v.sreg := r.ar(30 downto 23);
-- when "100" => v.sreg := r.ar(30 downto 23);
-- when "101" => v.sreg := SD_CRC_BYTE;
-- when others => v.sd.state := SD_GET_RESP;
-- end case;
-- v.go := '1';
-- v.sd.tcnt := r.sd.tcnt + 1;
-- end if;
-- when SD_GET_RESP =>
-- if v.bd = '1' then
-- if r.sd.vresp = '1' or r.sd.ctocnt = zero32(r.sd.ctocnt'range) then
-- if r.sd.rcnt = zero32(r.sd.rcnt'range) then
-- if r.sd.htb = '0' then
-- v.spio.csn := '1';
-- end if;
-- v.sd.htb := '0';
-- v.hold := '1';
-- else
-- v.sd.rcnt := r.sd.rcnt - 1;
-- end if;
-- else
-- v.sd.ctocnt := r.sd.ctocnt - 1;
-- end if;
-- end if;
-- if lastbit = '1' then
-- v.sd.vresp := r.sd.vresp or not r.ar(6);
-- if r.sd.rcnt = zero32(r.sd.rcnt'range) then
-- v.stop := r.sd.vresp and r.go and not r.sd.htb;
-- end if;
-- end if;
-- if r.sd.ctocnt = zero32(r.sd.ctocnt'range) then
-- v.stop := r.go;
-- end if;
-- if (r.go or r.spio.sck) = '0' then
-- v.sd.state := r.sd.rstate;
-- if r.sd.ctocnt = zero32(r.sd.ctocnt'range) then
-- if r.spio.initialized = '1' then
-- v.sd.state := SD_READY;
-- else
-- -- Try to initialize again
-- v.sd.state := SD_CHECK_PRES;
-- end if;
-- v.spio.errorn := '0';
-- v.sd.timeout := '1';
-- end if;
-- v.spio.csn := '1';
-- end if;
-- v.sd.tcnt := (others => '0');
-- when others => -- SD_CHECK_PRES
-- if r.sd.cd = '1' then
-- v.go := '1';
-- v.spio.csn := '0';
-- v.sd.state := SD_GET_RESP;
-- v.spio.cdcsnoen := OUTPUT;
-- end if;
-- v.sd.htb := '0';
-- v.sd.vresp := '1';
-- v.sd.rstate := SD_PWRUP0;
-- v.sd.rcnt := cslv(10, r.sd.rcnt'length);
-- v.sd.ctocnt := cslv(SD_CMD_TIMEOUT, r.sd.ctocnt'length);
-- end case;
-- end if;
---------------------------------------------------------------------------
-- SPI Flash (non SD) specific code
---------------------------------------------------------------------------
if sdcard = 0 then
case r.spi.state is
when SPI_READ =>
if r.go = '0' then
v.go := '1';
change := '1';
end if;
v.spi.cnt := cslv(SPI_ARG_LEN, r.spi.cnt'length);
if v.bd = '1' then
v.sreg := r.ar(23 downto 16);
end if;
if r.bd = '1' then
v.hold := '0';
v.spi.state := SPI_ADDR;
end if;
when SPI_ADDR =>
if v.bd = '1' then
v.sreg := r.ar(22 downto 15);
if dualoutput = 1 then
if r.spi.cnt = zero32(r.spi.cnt'range) then
v.spio.mosioen := INPUT;
end if;
end if;
end if;
if r.bd = '1' then
if r.spi.cnt = zero32(r.spi.cnt'range) then
v.spi.state := SPI_DATA;
v.spi.cnt := calc_spi_cnt(r.spi.hsize);
else
v.spi.cnt := r.spi.cnt - 1;
end if;
end if;
when SPI_DATA =>
if v.bd = '1' then
v.spi.cnt := r.spi.cnt - 1;
end if;
if lastbit = '1' and r.spi.cnt = zero32(r.spi.cnt'range) then
v.stop := r.go;
end if;
if (r.go or r.spio.sck) = '0' then
if r.spi.hburst(0) = '0' then -- not an incrementing burst
v.spi.state := SPI_PWRUP; -- CSN wait
v.spio.csn := '1';
v.go := '1';
v.stop := '1';
v.seq := '1'; -- Make right choice in SPI_PWRUP
v.bcnt := "110";
else
v.spi.state := SPI_READY;
end if;
v.hold := '1';
end if;
when SPI_READY =>
v.spio.ready := '1';
if read_flash then
v.go := '1';
if dualoutput = 1 then
v.bcnt(2) := '0';
end if;
if r.spio.csn = '1' then
-- New access, command and address
v.go := '0';
v.spio.csn := '0';
v.spi.state := SPI_READ;
elsif r.seq = '1' then
-- Continuation of burst
v.spi.state := SPI_DATA;
v.hold := '0';
else
-- Burst ended and new access
v.stop := '1';
v.spio.csn := '1';
v.spi.state := SPI_PWRUP;
v.bcnt := "011";
end if;
v.ar := (others => '0');
if offset /= 0 then
v.ar(r.haddr'range) := r.haddr + cslv(offset, req_addr_bits);
else
v.ar(r.haddr'range) := r.haddr;
end if;
v.spio.ready := '0';
v.sreg := cslv(readcmd, 8);
end if;
if r.spio.ready = '0' then
case r.spi.hsize is
when HSIZE_BYTE =>
for i in 0 to (MAXDW/8-1) loop
v.frdata(7+8*i downto 8*i):= r.ar(7 downto 0);
end loop; -- i
when HSIZE_HWORD =>
for i in 0 to (MAXDW/16-1) loop
v.frdata(15+16*i downto 16*i) := r.ar(15 downto 0);
end loop; -- i
when HSIZE_WORD =>
for i in 0 to (MAXDW/32-1) loop
v.frdata(31+32*i downto 32*i) := r.ar(31 downto 0);
end loop; -- i
when HSIZE_DWORD =>
if MAXDW > 32 and AHBDW > 32 then
for i in 0 to (MAXDW/64-1) loop
if MAXDW = 64 then
v.frdata(MAXDW-1+MAXDW*i downto MAXDW*i) :=
r.ar(MAXDW-1 downto 0);
elsif MAXDW = 128 then
v.frdata(MAXDW/2-1+MAXDW/2*i downto MAXDW/2*i) :=
r.ar(MAXDW/2-1 downto 0);
else
v.frdata(MAXDW/4-1+MAXDW/4*i downto MAXDW/4*i) :=
r.ar(MAXDW/4-1 downto 0);
end if;
end loop; -- i
else
null;
end if;
when HSIZE_4WORD =>
if MAXDW > 64 and AHBDW > 64 then
for i in 0 to (MAXDW/128-1) loop
if MAXDW = 128 then
v.frdata(MAXDW-1+MAXDW*i downto MAXDW*i) :=
r.ar(MAXDW-1 downto 0);
else
v.frdata(MAXDW/2-1+MAXDW/2*i downto MAXDW/2*i) :=
r.ar(MAXDW/2-1 downto 0);
end if;
end loop; -- i
else
null;
end if;
when others =>
if MAXDW > 128 and AHBDW > 128 then
v.frdata := r.ar;
else
null;
end if;
end case;
end if;
v.spi.hsize := r.hsize;
v.spi.hburst(0) := r.hburst(0);
v.spi.cnt := calc_spi_cnt(r.spi.hsize);
when others => -- SPI_PWRUP
v.hold := '1';
if r.spio.initialized = '1' then
-- Chip select wait
if (r.go or r.spio.sck) = '0' then
if r.seq = '1' then
v.spi.state := SPI_READY;
else
v.spi.state := SPI_READ;
v.spio.csn := '0';
end if;
if dualoutput = 1 then
v.spio.mosioen := OUTPUT;
v.bcnt(2) := '0';
end if;
end if;
else
-- Power up wait
if pwrupcnt /= 0 then
v.frdata := r.frdata - 1;
if r.frdata = zahbdw(r.frdata'range) then
v.spio.initialized := '1';
v.spi.state := SPI_READY;
end if;
else
v.spio.initialized := '1';
v.spi.state := SPI_READY;
end if;
end if;
end case;
end if;
---------------------------------------------------------------------------
-- SPI communication
---------------------------------------------------------------------------
-- Clock generation
if (r.go or r.spio.sck) = '1' then
v.timer := r.timer - 1;
if sck_toggle(v.timer, r.timer, enable_altscaler) then
v.spio.sck := not r.spio.sck;
v.sample(0) := not r.spio.sck;
change := r.spio.sck and r.go;
if (v.stop and lastbit and not r.spio.sck) = '1' then
v.go := '0';
v.stop := '0';
end if;
end if;
else
v.timer := (others => '1');
end if;
if r.sample(0) = '1' then
v.bcnt := r.bcnt + 1;
end if;
if r.sample(1-sdcard) = '1' then
if r.hold = '0' then
if sdcard = 0 and dualoutput = 1 and r.spio.mosioen = INPUT then
v.ar := r.ar(r.ar'left-2 downto 0) & r.spii(1-sdcard).miso & r.spii(1-sdcard).mosi;
else
v.ar := r.ar(r.ar'left-1 downto 0) & r.spii(1-sdcard).miso;
end if;
end if;
end if;
if change = '1' then
v.spio.mosi := v.sreg(7);
if sdcard = 1 or r.spi.state /= SPI_PWRUP then
v.sreg(7 downto 0) := v.sreg(6 downto 0) & '1';
end if;
end if;
---------------------------------------------------------------------------
-- System and core reset
---------------------------------------------------------------------------
if (not rstn or r.rst) = '1' then
-- if sdcard = 1 then
-- v.sd.state := SD_CHECK_PRES;
-- v.spio.cdcsnoen := INPUT;
-- v.sd.timeout := '0';
-- else
v.spi.state := SPI_PWRUP;
v.frdata := cslv(pwrupcnt, r.frdata'length);
v.spio.cdcsnoen := OUTPUT;
-- end if;
v.spimstate := IDLE;
v.rst := '0';
--
v.reg.ctrl := ('0', '0', '0');
v.reg.stat.done := '0';
--
v.sample := (others => '0');
v.sreg := (others => '1');
v.bcnt := (others => '0');
v.go := '0';
v.stop := '0';
v.hold := '0';
v.unsplit := '0';
--
v.hready := '1';
v.hwrite := '0';
v.hsel := '0';
v.hmbsel := (others => '0');
v.ahbcancel := '0';
--
v.spio.sck := '0';
v.spio.mosi := '1';
v.spio.mosioen := OUTPUT;
v.spio.csn := '1';
-- v.spio.errorn := '1';
v.spio.initialized := '0';
v.spio.ready := '0';
end if;
---------------------------------------------------------------------------
-- Drive unused signals
---------------------------------------------------------------------------
-- if sdcard = 1 then
-- v.spi.state := SPI_PWRUP;
-- v.spi.cnt := (others => '0');
-- v.spi.hsize := (others => '0');
-- v.spi.hburst := (others => '0');
-- v.hburst := (others => '0');
-- v.seq := '0';
-- else
-- v.sd.state := SD_CHECK_PRES;
-- v.sd.tcnt := (others => '0');
-- v.sd.rcnt := (others => '0');
-- v.sd.cmd := (others => '0');
-- v.sd.rstate := SD_CHECK_PRES;
-- v.sd.htb := '0';
-- v.sd.vresp := '0';
-- v.sd.timeout := '0';
-- v.sd.dtocnt := (others => '0');
-- v.sd.ctocnt := (others => '0');
-- end if;
if spliten = 0 then
v.insplit := '0';
v.unsplit := '0';
v.splmst := (others => '0');
v.hsplit := (others => '0');
v.ahbcancel := '0';
end if;
---------------------------------------------------------------------------
-- Signal assignments
---------------------------------------------------------------------------
-- Core registers
rin <= v;
-- AHB slave output
ahbso.hready <= r.hready;
ahbso.hresp <= r.hresp;
if r.hmbsel(CTRL_BANK) = '1' then
for i in 0 to (MAXDW/32-1) loop
hrdata(31 + 32*i downto 32*i) := zero32(31 downto 8) & r.rrdata;
end loop;
else
hrdata := r.frdata;
end if;
ahbso.hrdata <= ahbdrivedata(hrdata);
ahbso.hconfig <= HCONFIG;
ahbso.hirq <= ahbirq;
ahbso.hindex <= hindex;
ahbso.hsplit <= hsplit;
-- SPI signals
spio <= r.spio;
end process comb;
reg: process (clk)
begin -- process reg
if rising_edge(clk) then
r <= rin;
end if;
end process reg;
-- Boot message
-- pragma translate_off
bootmsg : report_version
generic map (
"spimctrl" & tost(hindex) & ": SPI memory controller rev " &
tost(REVISION) & ", irq " & tost(hirq));
-- pragma translate_on
end rtl;
| gpl-3.0 | bb463ed2246e5aa1ac3988c4d8953bd7 | 0.443689 | 3.719386 | false | false | false | false |
EliasLuiz/TCC | Leon3/lib/gaisler/misc/logan.vhd | 1 | 16,989 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: logan
-- File: logan.vhd
-- Author: Kristoffer Carlsson, Gaisler Research
-- Description: On-chip logic analyzer IP core
-----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
library techmap;
use techmap.gencomp.all;
entity logan is
generic (
dbits : integer range 0 to 256 := 32; -- Number of traced signals
depth : integer range 256 to 16384 := 1024; -- Depth of trace buffer
trigl : integer range 1 to 63 := 1; -- Number of trigger levels
usereg : integer range 0 to 1 := 1; -- Use input register
usequal : integer range 0 to 1 := 0; -- Use qualifer bit
usediv : integer range 0 to 1 := 1; -- Enable/disable div counter
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#F00#;
memtech : integer := DEFMEMTECH);
port (
rstn : in std_logic; -- Synchronous reset
clk : in std_logic; -- System clock
tclk : in std_logic; -- Trace clock
apbi : in apb_slv_in_type; -- APB in record
apbo : out apb_slv_out_type; -- APB out record
signals : in std_logic_vector(dbits - 1 downto 0)); -- Traced signals
end logan;
architecture rtl of logan is
constant REVISION : amba_version_type := 0;
constant pconfig : apb_config_type := (
0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_LOGAN, 0, REVISION, 0),
1 => apb_iobar(paddr, pmask));
constant abits: integer := 8 + log2x(depth/256 - 1);
constant az : std_logic_vector(abits-1 downto 0) := (others => '0');
constant dz : std_logic_vector(dbits-1 downto 0) := (others => '0');
type trig_cfg_type is record
pattern : std_logic_vector(dbits-1 downto 0); -- Pattern to trig on
mask : std_logic_vector(dbits-1 downto 0); -- trigger mask
count : std_logic_vector(5 downto 0); -- match counter
eq : std_ulogic; -- Trig on match or no match?
end record;
type trig_cfg_arr is array (0 to trigl-1) of trig_cfg_type;
type reg_type is record
armed : std_ulogic;
trig_demet : std_ulogic;
trigged : std_ulogic;
fin_demet : std_ulogic;
finished : std_ulogic;
qualifier : std_logic_vector(7 downto 0);
qual_val : std_ulogic;
divcount : std_logic_vector(15 downto 0);
counter : std_logic_vector(abits-1 downto 0);
page : std_logic_vector(3 downto 0);
trig_conf : trig_cfg_arr;
end record;
type trace_reg_type is record
armed : std_ulogic;
arm_demet : std_ulogic;
trigged : std_ulogic;
finished : std_ulogic;
sample : std_ulogic;
divcounter : std_logic_vector(15 downto 0);
match_count : std_logic_vector(5 downto 0);
counter : std_logic_vector(abits-1 downto 0);
curr_tl : integer range 0 to trigl-1;
w_addr : std_logic_vector(abits-1 downto 0);
end record;
signal r_addr : std_logic_vector(13 downto 0);
signal bufout : std_logic_vector(255 downto 0);
signal r_en : std_ulogic;
signal r, rin : reg_type;
signal tr, trin : trace_reg_type;
signal sigreg : std_logic_vector(dbits-1 downto 0);
signal sigold : std_logic_vector(dbits-1 downto 0);
begin
bufout(255 downto dbits) <= (others => '0');
-- Combinatorial process for AMBA clock domain
comb1: process(rstn, apbi, r, tr, bufout)
variable v : reg_type;
variable rdata : std_logic_vector(31 downto 0);
variable tl : integer range 0 to trigl-1;
variable pattern, mask : std_logic_vector(255 downto 0);
begin
v := r;
rdata := (others => '0'); tl := 0;
pattern := (others => '0'); mask := (others => '0');
-- Two stage synch
v.trig_demet := tr.trigged;
v.trigged := r.trig_demet;
v.fin_demet := tr.finished;
v.finished := r.fin_demet;
if r.finished = '1' then
v.armed := '0';
end if;
r_en <= '0';
-- Read/Write --
if apbi.psel(pindex) = '1' then
-- Write
if apbi.pwrite = '1' and apbi.penable = '1' then
-- Only conf area writeable
if apbi.paddr(15) = '0' then
-- pattern/mask
if apbi.paddr(14 downto 13) = "11" then
tl := conv_integer(apbi.paddr(11 downto 6));
pattern(dbits-1 downto 0) := v.trig_conf(tl).pattern;
mask(dbits-1 downto 0) := v.trig_conf(tl).mask;
case apbi.paddr(5 downto 2) is
when "0000" => pattern(31 downto 0) := apbi.pwdata;
when "0001" => pattern(63 downto 32) := apbi.pwdata;
when "0010" => pattern(95 downto 64) := apbi.pwdata;
when "0011" => pattern(127 downto 96) := apbi.pwdata;
when "0100" => pattern(159 downto 128) := apbi.pwdata;
when "0101" => pattern(191 downto 160) := apbi.pwdata;
when "0110" => pattern(223 downto 192) := apbi.pwdata;
when "0111" => pattern(255 downto 224) := apbi.pwdata;
when "1000" => mask(31 downto 0) := apbi.pwdata;
when "1001" => mask(63 downto 32) := apbi.pwdata;
when "1010" => mask(95 downto 64) := apbi.pwdata;
when "1011" => mask(127 downto 96) := apbi.pwdata;
when "1100" => mask(159 downto 128) := apbi.pwdata;
when "1101" => mask(191 downto 160) := apbi.pwdata;
when "1110" => mask(223 downto 192) := apbi.pwdata;
when "1111" => mask(255 downto 224) := apbi.pwdata;
when others => null;
end case;
-- write back updated pattern/mask
v.trig_conf(tl).pattern := pattern(dbits-1 downto 0);
v.trig_conf(tl).mask := mask(dbits-1 downto 0);
-- count/eq
elsif apbi.paddr(14 downto 13) = "01" then
tl := conv_integer(apbi.paddr(7 downto 2));
v.trig_conf(tl).count := apbi.pwdata(6 downto 1);
v.trig_conf(tl).eq := apbi.pwdata(0);
-- arm/reset
elsif apbi.paddr(14 downto 13)&apbi.paddr(4 downto 2) = "00000" then
v.armed := apbi.pwdata(0);
-- Page reg
elsif apbi.paddr(14 downto 13)&apbi.paddr(4 downto 2) = "00010" then
v.page := apbi.pwdata(3 downto 0);
-- Trigger counter
elsif apbi.paddr(14 downto 13)&apbi.paddr(4 downto 2) = "00011" then
v.counter := apbi.pwdata(abits-1 downto 0);
-- div count
elsif apbi.paddr(14 downto 13)&apbi.paddr(4 downto 2) = "00100" then
v.divcount := apbi.pwdata(15 downto 0);
-- qualifier bit
elsif apbi.paddr(14 downto 13)&apbi.paddr(4 downto 2) = "00101" then
v.qualifier := apbi.pwdata(7 downto 0);
v.qual_val := apbi.pwdata(8);
end if;
end if;
-- end write
-- Read
else
-- Read config/status area
if apbi.paddr(15) = '0' then
-- pattern/mask
if apbi.paddr(14 downto 13) = "11" then
tl := conv_integer(apbi.paddr(11 downto 6));
pattern(dbits-1 downto 0) := v.trig_conf(tl).pattern;
mask(dbits-1 downto 0) := v.trig_conf(tl).mask;
case apbi.paddr(5 downto 2) is
when "0000" => rdata := pattern(31 downto 0);
when "0001" => rdata := pattern(63 downto 32);
when "0010" => rdata := pattern(95 downto 64);
when "0011" => rdata := pattern(127 downto 96);
when "0100" => rdata := pattern(159 downto 128);
when "0101" => rdata := pattern(191 downto 160);
when "0110" => rdata := pattern(223 downto 192);
when "0111" => rdata := pattern(255 downto 224);
when "1000" => rdata := mask(31 downto 0);
when "1001" => rdata := mask(63 downto 32);
when "1010" => rdata := mask(95 downto 64);
when "1011" => rdata := mask(127 downto 96);
when "1100" => rdata := mask(159 downto 128);
when "1101" => rdata := mask(191 downto 160);
when "1110" => rdata := mask(223 downto 192);
when "1111" => rdata := mask(255 downto 224);
when others => rdata := (others => '0');
end case;
-- count/eq
elsif apbi.paddr(14 downto 13) = "01" then
tl := conv_integer(apbi.paddr(7 downto 2));
rdata(6 downto 1) := v.trig_conf(tl).count;
rdata(0) := v.trig_conf(tl).eq;
-- status
elsif apbi.paddr(14 downto 13)&apbi.paddr(4 downto 2) = "00000" then
rdata := conv_std_logic_vector(usereg,1) & conv_std_logic_vector(usequal,1) &
r.armed & r.trigged &
conv_std_logic_vector(dbits,8)&
conv_std_logic_vector(depth-1,14)&
conv_std_logic_vector(trigl,6);
-- trace buffer index
elsif apbi.paddr(14 downto 13)&apbi.paddr(4 downto 2) = "00001" then
rdata(abits-1 downto 0) := tr.w_addr(abits-1 downto 0);
-- page reg
elsif apbi.paddr(14 downto 13)&apbi.paddr(4 downto 2) = "00010" then
rdata(3 downto 0) := r.page;
-- trigger counter
elsif apbi.paddr(14 downto 13)&apbi.paddr(4 downto 2) = "00011" then
rdata(abits-1 downto 0) := r.counter;
-- divcount
elsif apbi.paddr(14 downto 13)&apbi.paddr(4 downto 2) = "00100" then
rdata(15 downto 0) := r.divcount;
-- qualifier
elsif apbi.paddr(14 downto 13)&apbi.paddr(4 downto 2) = "00101" then
rdata(7 downto 0) := r.qualifier;
rdata(8) := r.qual_val;
end if;
-- Read from trace buffer
else
-- address always r.page & apbi.paddr(14 downto 5)
r_en <= '1';
-- Select word from pattern
case apbi.paddr(4 downto 2) is
when "000" => rdata := bufout(31 downto 0);
when "001" => rdata := bufout(63 downto 32);
when "010" => rdata := bufout(95 downto 64);
when "011" => rdata := bufout(127 downto 96);
when "100" => rdata := bufout(159 downto 128);
when "101" => rdata := bufout(191 downto 160);
when "110" => rdata := bufout(223 downto 192);
when "111" => rdata := bufout(255 downto 224);
when others => rdata := (others => '0');
end case;
end if;
end if; -- end read
end if;
if rstn = '0' then
v.armed := '0'; v.trigged := '0'; v.finished := '0'; v.trig_demet := '0'; v.fin_demet := '0';
v.counter := (others => '0');
v.divcount := X"0001";
v.qualifier := (others => '0');
v.qual_val := '0';
v.page := (others => '0');
end if;
apbo.prdata <= rdata;
rin <= v;
end process;
-- Combinatorial process for trace clock domain
comb2 : process (rstn, tr, r, sigreg)
variable v : trace_reg_type;
begin
v := tr;
v.sample := '0';
if tr.armed = '0' then
v.trigged := '0'; v.counter := (others => '0'); v.curr_tl := 0; v.match_count := (others => '0');
end if;
-- Synch arm signal
v.arm_demet := r.armed;
v.armed := tr.arm_demet;
if tr.finished = '1' then
v.finished := tr.armed;
end if;
-- Trigger --
if tr.armed = '1' and tr.finished = '0' then
if usediv = 1 then
if tr.divcounter = X"0000" then
v.divcounter := r.divcount-1;
if usequal = 0 or sigreg(conv_integer(r.qualifier)) = r.qual_val then
v.sample := '1';
end if;
else
v.divcounter := v.divcounter - 1;
end if;
else
v.sample := '1';
end if;
if tr.sample = '1' then v.w_addr := tr.w_addr + 1; end if;
if tr.trigged = '1' and tr.sample = '1' then
if tr.counter = r.counter then
v.trigged := '0';
v.sample := '0';
v.finished := '1';
v.counter := (others => '0');
else v.counter := tr.counter + 1; end if;
else
-- match?
if ((sigreg xor r.trig_conf(tr.curr_tl).pattern) and r.trig_conf(tr.curr_tl).mask) = dz then
-- trig on equal
if r.trig_conf(tr.curr_tl).eq = '1' then
if tr.match_count /= r.trig_conf(tr.curr_tl).count then
v.match_count := tr.match_count + 1;
else
-- final match?
if tr.curr_tl = trigl-1 then
v.trigged := '1';
else
v.curr_tl := tr.curr_tl + 1;
end if;
end if;
end if;
else -- not a match
-- trig on inequal
if r.trig_conf(tr.curr_tl).eq = '0' then
if tr.match_count /= r.trig_conf(tr.curr_tl).count then
v.match_count := tr.match_count + 1;
else
-- final match?
if tr.curr_tl = trigl-1 then
v.trigged := '1';
else
v.curr_tl := tr.curr_tl + 1;
end if;
end if;
end if;
end if;
end if;
end if;
-- end trigger
if rstn = '0' then
v.armed := '0'; v.trigged := '0'; v.sample := '0'; v.finished := '0'; v.arm_demet := '0';
v.curr_tl := 0;
v.counter := (others => '0');
v.divcounter := (others => '0');
v.match_count := (others => '0');
v.w_addr := (others => '0');
end if;
trin <= v;
end process;
-- clk traced signals through register to minimize fan out
inreg: if usereg = 1 generate
process (tclk)
begin
if rising_edge(tclk) then
sigold <= sigreg;
sigreg <= signals;
end if;
end process;
end generate;
noinreg: if usereg = 0 generate
sigreg <= signals;
sigold <= signals;
end generate;
-- Update registers
reg: process(clk)
begin
if rising_edge(clk) then r <= rin; end if;
end process;
treg: process(tclk)
begin
if rising_edge(tclk) then tr <= trin; end if;
end process;
r_addr <= r.page & apbi.paddr(14 downto 5);
trace_buf : syncram_2p
generic map (tech => memtech, abits => abits, dbits => dbits)
port map (clk, r_en, r_addr(abits-1 downto 0), bufout(dbits-1 downto 0), -- read
tclk, tr.sample, tr.w_addr, sigold); -- write
apbo.pconfig <= pconfig;
apbo.pindex <= pindex;
apbo.pirq <= (others => '0');
end architecture;
| gpl-3.0 | 7525422c59238ab7b17a495d6e61f1d1 | 0.497852 | 3.861136 | false | false | false | false |
ARC-Lab-UF/UAA | src/fcbt.vhd | 1 | 22,565 | -- Copyright (c) 2015 University of Florida
--
-- This file is part of uaa.
--
-- uaa is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- uaa is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with uaa. If not, see <http://www.gnu.org/licenses/>.
-- David Wilson
-- University of Florida
-- Description:
-- The fcbt entity implements the fully compacted binary tree design similar to the
-- architecture described in the paper "High-Performance Reduction Circuits Using Deeply
-- Pipelined Operators on FPGAs" by Ling Zhuo, G.R. Morris and V.K. Prasanna (2007)
-- Used entities:
-- fifo2, delay, add_wrapper
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
use work.math_custom.all;
use work.flt_pkg.all;
-------------------------------------------------------------------------------
-- Generics Description
-- width : The width of the input and output in bits
-- add_core_name : A string representing different optimizations for the
-- actual adder core. See add_flt.vhd and flt_pkg.vhd for
-- more information.
-- use_bram : uses bram when true, uses LUTs or FFs when false
-- FCBT_max_inputs : This positive indicates the maximum amount of inputs
-- per input group. Buffer size scales with the log of
-- of this generic.
-- FCBT_obuf_size : Specifies the size of the output buffer for the
-- FCBT architecture.
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Port Description:
-- clk : clock input
-- rst : reset input (asynchronous, active high)
-- hold_output : When asserted, this signal prevents the entity from
-- continuing past a valid output. When not asserted, the
-- output is valid for only a single cycle. This signal
-- makes it possible to stall the fcbt if downstream
-- components cannot receive another input (active high)
-- ready : when asserted, the fcbt is ready to accept new inputs. If not
-- asserted, external components must hold the current input or
-- it will be lost (active high)
-- end_of_group : should be asserted on the same cycle as the last input in a
-- group (active high)
-- input : fcbt input
-- output : fcbt output
-- valid_in : assert when the input to the fcbt is valid and ready is
-- asserted (active high)
-- valid_out : asserted when the output from the fcbt is valid. Unless
-- hold_output is asserted, valid_out is only asserted for
-- one cycle. (active high)
-------------------------------------------------------------------------------
entity fcbt is
generic (
width : positive := 32;
add_core_name : string := "speed";
use_bram : boolean := true;
FCBT_max_inputs : positive := 128;
FCBT_obuf_size : positive := 14
);
port (
clk : in std_logic;
rst : in std_logic;
hold_output : in std_logic; -- '1' keeps outputs from disappearing
ready : out std_logic; -- '1' when fcbt can accept input
end_of_group : in std_logic; -- specifies last input in group
input : in std_logic_vector(width-1 downto 0);
output : out std_logic_vector(width-1 downto 0);
valid_in : in std_logic;
valid_out : out std_logic
);
end fcbt;
architecture STR of fcbt is
-- fcbt should be used when the max number of inputs per group is more than 4
function set_max_inputs return positive is
begin
if FCBT_max_inputs < 5 then
return 5;
else
return FCBT_max_inputs;
end if;
end function set_max_inputs;
function set_obuf_size return positive is
begin
if FCBT_obuf_size < 1 then
return 1;
else
return FCBT_obuf_size;
end if;
end function set_obuf_size;
constant ADD_LATENCY : natural := add_flt_latency(add_core_name);
constant BUFFER_DEPTH : integer := 6;
constant MAX_INPUTS : positive := set_max_inputs;
constant TREE_LEVELS : integer := clog2(MAX_INPUTS);
constant TREE_LEVELS_BITS : integer := clog2(TREE_LEVELS);
constant MAX_GROUP : integer := set_obuf_size;
constant MAX_GROUP_BITS : integer := clog2(MAX_GROUP);
constant TAGGING_BITS : integer := MAX_GROUP_BITS+2;
type data_array is array (natural range<>) of std_logic_vector(width-1 downto 0);
type obuf_out_array is array (natural range<>) of std_logic_vector(width downto 0);
type buf_count_array is array (natural range<>) of std_logic_vector(clog2(BUFFER_DEPTH+1)-1 downto 0);
type buf_group_num_array is array (natural range<>) of std_logic_vector(MAX_GROUP_BITS-1 downto 0);
type buf_array is array (natural range<>) of std_logic_vector(width+TAGGING_BITS-1 downto 0);
type add_group_labels_array is array (natural range<>) of std_logic_vector(TAGGING_BITS-1 downto 0);
-- input tagging signals
signal start_of_group : std_logic;
signal group_num : std_logic_vector(MAX_GROUP_BITS-1 downto 0);
-- adder signals
signal add_in1 : data_array(1 downto 0);
signal add_in2 : data_array(1 downto 0);
signal add_out : data_array(1 downto 0);
signal add_valid_in : std_logic_vector(1 downto 0);
signal add_valid_out : std_logic_vector(1 downto 0);
signal add_zero : std_logic_vector(1 downto 0);
signal add_group_tags_in : add_group_labels_array(1 downto 0);
signal add_group_tags_out : add_group_labels_array(1 downto 0);
signal add_group_num_in : buf_group_num_array(1 downto 0);
signal add_group_num_out : buf_group_num_array(1 downto 0);
signal add_end_of_group_in : std_logic_vector(1 downto 0);
signal add_end_of_group_out : std_logic_vector(1 downto 0);
signal add_start_of_group_in : std_logic_vector(1 downto 0);
signal add_start_of_group_out : std_logic_vector(1 downto 0);
signal add_last_element : std_logic_vector(1 downto 0);
-- buf signals
signal buf_in : buf_array(TREE_LEVELS-1 downto 0);
signal buf_out0 : data_array(TREE_LEVELS-1 downto 0);
signal buf_out1 : data_array(TREE_LEVELS-1 downto 0);
signal buf_out0_temp : buf_array(TREE_LEVELS-1 downto 0);
signal buf_out1_temp : buf_array(TREE_LEVELS-1 downto 0);
signal buf_rd : std_logic_vector(TREE_LEVELS-1 downto 0);
signal buf_rd_single : std_logic_vector(TREE_LEVELS-1 downto 0);
signal buf_wr : std_logic_vector(TREE_LEVELS-1 downto 0);
signal buf_start_of_group : std_logic_vector(TREE_LEVELS-1 downto 0);
signal buf_start_of_group_zero : std_logic_vector(TREE_LEVELS-1 downto 0);
signal buf_end_of_group : std_logic_vector(TREE_LEVELS-1 downto 0);
signal buf_end_of_group_zero : std_logic_vector(TREE_LEVELS-1 downto 0);
signal buf_group_num : buf_group_num_array(TREE_LEVELS-1 downto 0);
signal buf_count : buf_count_array(TREE_LEVELS-1 downto 0);
signal buf_empty : std_logic_vector(TREE_LEVELS-1 downto 0);
-- obuf signals
signal obuf_out : obuf_out_array(MAX_GROUP-1 downto 0);
signal output_ptn : unsigned(MAX_GROUP_BITS-1 downto 0);
signal valid_out_int : std_logic;
-- ctrl signals
signal ctrl_en : std_logic;
signal ctrl_count : unsigned(TREE_LEVELS-2 downto 0);
signal ctrl_buf_sel : unsigned(TREE_LEVELS_BITS-1 downto 0);
signal ctrl_next_buf_in : std_logic_vector(TREE_LEVELS_BITS-1 downto 0);
signal ctrl_next_buf_out : std_logic_vector(TREE_LEVELS_BITS-1 downto 0);
signal ready_max_groups : std_logic;
begin
-- the FCBT deasserts ready when fcbt holds the max number of groups
ctrl_en <= '1';
ready <= ready_max_groups;
---------------------------------------------------------------
-- Input Tagging
-- assign group number for incoming inputs. Group numbers will correspond to index in
-- output buffer and will ensure in-order outputs from the buffer.
process(clk, rst)
begin
if (rst = '1') then
-- group numbers start at 0
group_num <= std_logic_vector(to_unsigned(0, MAX_GROUP_BITS));
elsif (rising_edge(clk)) then
if (ready_max_groups = '1') then
-- get next group number after receiving the current group's last element
if (valid_in = '1' and end_of_group = '1') then
if (to_integer(unsigned(group_num)) = MAX_GROUP-1) then
group_num <= std_logic_vector(to_unsigned(0, MAX_GROUP_BITS));
else
group_num <= std_logic_vector(unsigned(group_num)+1);
end if;
end if;
end if;
end if;
end process;
ready_max_groups <= '0' when output_ptn = to_unsigned(to_integer(unsigned(group_num)+1) mod MAX_GROUP, MAX_GROUP_BITS) else '1';
-- keep track of which input is the first element of a group. This will be the first
-- received element or the next valid element following the last element of a
-- previous group.
process(clk, rst)
begin
if (rst = '1') then
-- First received element will be the start of the first group
start_of_group <= '1';
elsif (rising_edge(clk)) then
if (ready_max_groups = '1') then
-- the element following the end of one group will be the start of the
-- next group
if (end_of_group = '1' and valid_in = '1') then
start_of_group <= '1';
-- any other element is not the start of the next group
elsif (valid_in = '1') then
start_of_group <= '0';
end if;
end if;
end if;
end process;
---------------------------------------------------------------
-- BUF
-- attach tagging information to the input to identify the last element and its place in the
-- output buffer. The last element will have both end_of_group and start_of_group asserted.
-- Group_num will act as an index into the output buffer to handle out of order outputs
buf_in(0) <= group_num & end_of_group & start_of_group & input;
-- write to the first buffer any time there is valid input and the architecture isn't stalling
buf_wr(0) <= '1' when valid_in = '1' and ready_max_groups = '1' else
'0';
-- carry along data with tagging information
buf_in(1) <= add_group_num_out(0) & add_end_of_group_out(0) & add_start_of_group_out(0) & add_out(0);
-- write to the second buffer any time there is valid output from the first adder that isn't the final
-- sum of the group and when the architecture isn't stalling
buf_wr(1) <= '1' when add_valid_out(0) = '1' and add_last_element(0) = '0' else
'0';
U_BUFF_WR : for i in 2 to TREE_LEVELS-1 generate
-- carry along data with tagging information
buf_in(i) <= add_group_num_out(1) & add_end_of_group_out(1) & add_start_of_group_out(1) & add_out(1);
-- write to the other buffers any time there is valid output from the second adder that isn't the
-- final sum of the group and is the sum of elements on the buffer level below it
buf_wr(i) <= '1' when add_valid_out(1) = '1' and add_last_element(1) = '0' and
ctrl_next_buf_out = std_logic_vector(to_unsigned(i, TREE_LEVELS_BITS)) else
'0';
end generate U_BUFF_WR;
U_BUFFERS : for i in 0 to TREE_LEVELS-1 generate
U_BUFF : entity work.fifo2
generic map(
width => width+TAGGING_BITS,
depth => BUFFER_DEPTH,
use_bram => use_bram,
same_cycle_output => true)
port map(
clk => clk,
rst => rst,
rd => buf_rd(i),
wr => buf_wr(i),
single => buf_rd_single(i),
empty => buf_empty(i),
full => open,
overflow => open,
underflow => open,
input => buf_in(i),
output0 => buf_out0_temp(i),
output1 => buf_out1_temp(i),
count => buf_count(i)
);
-- break up buf outputs into group_num data, end_of_group flag, start_of_group flag, and data to add
-- Note: these may be uninitialized until the first rising clock edge when using block RAM
buf_group_num(i) <= buf_out0_temp(i)(width+2+MAX_GROUP_BITS-1 downto width+2);
buf_end_of_group(i) <= buf_out0_temp(i)(width+1) or buf_out1_temp(i)(width+1);
buf_end_of_group_zero(i) <= buf_out0_temp(i)(width+1);
buf_start_of_group(i) <= buf_out0_temp(i)(width) or buf_out1_temp(i)(width);
buf_start_of_group_zero(i) <= buf_out0_temp(i)(width);
buf_out0(i) <= buf_out0_temp(i)(width-1 downto 0);
buf_out1(i) <= buf_out1_temp(i)(width-1 downto 0);
end generate U_BUFFERS;
process(ctrl_count, buf_count, buf_out0_temp)
begin
-- default values
buf_rd_single <= (others => '0');
buf_rd <= (others => '0');
add_zero <= (others => '0');
add_valid_in <= (others => '0');
ctrl_buf_sel <= (others => '0');
-- perform singleton addition with 1st adder if the next element in buffer 0
-- is the last element of a group
if(buf_count(0) > std_logic_vector(to_unsigned(0, buf_count(0)'length)) and
buf_out0_temp(0)(width+1) = '1') then
buf_rd(0) <= '1';
buf_rd_single(0) <= '1';
add_zero(0) <= '1';
add_valid_in(0) <= '1';
-- perform normal addition with 1st adder when there's two or more elements
-- in buffer 0
elsif(buf_count(0) > std_logic_vector(to_unsigned(1, buf_count(0)'length))) then
buf_rd(0) <= '1';
add_valid_in(0) <= '1';
end if;
for i in 1 to TREE_LEVELS-1 loop
-- 2nd adder uses inputs from buffer i (i>=1) every 2^i cycles
if (ctrl_count(i-1 downto 0) = to_unsigned(2**(i-1)-1, i)) then
ctrl_buf_sel <= to_unsigned(i, ctrl_buf_sel'length);
-- perform singleton addition if the next element in buffer i is the last
-- element of a group
if(buf_count(i) > std_logic_vector(to_unsigned(0, buf_count(i)'length)) and
buf_out0_temp(i)(width+1) = '1') then
buf_rd(i) <= '1';
buf_rd_single(i) <= '1';
add_zero(1) <= '1';
add_valid_in(1) <= '1';
-- perform normal addition when there's two or more elements in buffer i
elsif(buf_count(i) > std_logic_vector(to_unsigned(1, buf_count(i)'length))) then
buf_rd(i) <= '1';
add_valid_in(1) <= '1';
end if;
end if;
end loop;
end process;
---------------------------------------------------------------
-- Adders
-- 1st adder inputs. Second input is zeroed for singleton addition
add_in1(0) <= buf_out0(0);
add_in2(0) <= buf_out1(0) when add_zero(0) = '0' else (others => '0');
-- 2nd adder inputs. Second input is zeroed for singleton addition
add_in1(1) <= buf_out0(to_integer(ctrl_buf_sel));
add_in2(1) <= buf_out1(to_integer(ctrl_buf_sel)) when add_zero(1) = '0' else (others => '0');
-- adder end_of_group bits. Value only considers first element in singleton add.
add_end_of_group_in(0) <= buf_end_of_group(0) when add_zero(0) = '0' else
buf_end_of_group_zero(0);
add_end_of_group_in(1) <= buf_end_of_group(to_integer(ctrl_buf_sel)) when add_zero(1) = '0' else
buf_end_of_group_zero(to_integer(ctrl_buf_sel));
-- adder start_of_group bits. Value only considers first element in singleton add.
add_start_of_group_in(0) <= buf_start_of_group(0) when add_zero(0) = '0' else
buf_start_of_group_zero(0);
add_start_of_group_in(1) <= buf_start_of_group(to_integer(ctrl_buf_sel)) when add_zero(1) = '0' else
buf_start_of_group_zero(to_integer(ctrl_buf_sel));
-- adder group_num bits
add_group_num_in(0) <= buf_group_num(0);
add_group_num_in(1) <= buf_group_num(to_integer(ctrl_buf_sel));
U_ADDERS : for i in 0 to 1 generate
U_ADDER : entity work.add_wrapper
generic map(
core_name => add_core_name,
width => width)
port map(
clk => clk,
rst => rst,
en => ctrl_en,
input1 => add_in1(i),
input2 => add_in2(i),
output => add_out(i),
valid_in => add_valid_in(i),
valid_out => add_valid_out(i),
count => open
);
U_GROUP_TAGS : entity work.delay
generic map(
cycles => ADD_LATENCY,
width => TAGGING_BITS,
init => std_logic_vector(to_unsigned(0, TAGGING_BITS)))
port map(
clk => clk,
rst => rst,
en => ctrl_en,
input => add_group_tags_in(i),
output => add_group_tags_out(i)
);
-- carry along tagging information while sum is in adder
add_group_tags_in(i) <= add_group_num_in(i) &
add_end_of_group_in(i) &
add_start_of_group_in(i);
-- break up tagging signal into end_of_group flag, start_of_group flag, and group_num data
add_end_of_group_out(i) <= add_group_tags_out(i)(1);
add_start_of_group_out(i) <= add_group_tags_out(i)(0);
add_group_num_out(i) <= add_group_tags_out(i)(TAGGING_BITS-1 downto 2);
-- an adder output with both end_of_group and start_of_group bits asserted is
-- the last element in the group
add_last_element(i) <= '1' when add_end_of_group_out(i) = '1' and
add_start_of_group_out(i) = '1' else
'0';
end generate;
U_NEXT_BUF : entity work.delay
generic map(
cycles => ADD_LATENCY,
width => TREE_LEVELS_BITS,
init => std_logic_vector(to_unsigned(0, TREE_LEVELS_BITS)))
port map(
clk => clk,
rst => rst,
en => ctrl_en,
input => ctrl_next_buf_in,
output => ctrl_next_buf_out
);
-- if the adder is using inputs from buffer i, the sum should be written to
-- buffer i+1 or obuf if final sum.
ctrl_next_buf_in <= std_logic_vector(ctrl_buf_sel+1);
---------------------------------------------------------------
-- OBUF
-- create obufs, and handle output and valid_out logic
process(clk, rst)
variable obuf_index : integer;
begin
if (rst = '1') then
for i in 0 to MAX_GROUP-1 loop
obuf_out(i) <= (others => '0');
end loop;
output_ptn <= to_unsigned(0, output_ptn'length);
valid_out_int <= '0';
output <= (others => '0');
elsif (rising_edge(clk)) then
for i in 0 to 1 loop
-- write adder output to obuf at its group number index if valid and last element of group
-- obuf has additional bit acting as a ready bit
if (add_valid_out(i) = '1' and add_last_element(i) = '1') then
obuf_out(to_integer(unsigned(add_group_num_out(i)))) <= '1' & add_out(i);
end if;
end loop;
if (hold_output = '0') then
-- clear valid_out flag if it was set before
valid_out_int <= '0';
-- outputs data at output_ptn if the ready bit is asserted and either hold_output isn't asserted
-- or valid_out isn't asserted.
if (obuf_out(to_integer(output_ptn))(width) = '1' and (hold_output = '0' or valid_out_int = '0')) then
output <= obuf_out(to_integer(output_ptn))(width-1 downto 0);
valid_out_int <= '1';
-- Data at output_ptn index is cleared and output_ptn gets next possible index.
obuf_out(to_integer(output_ptn)) <= (others => '0');
if (to_integer(output_ptn) = MAX_GROUP-1) then
output_ptn <= to_unsigned(0, MAX_GROUP_BITS);
else
output_ptn <= output_ptn+1;
end if;
end if;
end if;
end if;
end process;
valid_out <= valid_out_int;
---------------------------------------------------------------
-- Scheduling Counter
-- Counter bits used for scheduling 2nd adder additions
process(clk, rst)
begin
if (rst = '1') then
ctrl_count <= (others => '0');
elsif (rising_edge(clk)) then
ctrl_count <= unsigned(ctrl_count)+1;
end if;
end process;
end STR;
| gpl-3.0 | 69571532f1c1589a9383bec659ed2600 | 0.543186 | 3.707081 | false | false | false | false |
EliasLuiz/TCC | Leon3/designs/leon3-xilinx-ml510/config.vhd | 1 | 10,243 |
-----------------------------------------------------------------------------
-- LEON3 Demonstration design test bench configuration
-- Copyright (C) 2009 Aeroflex Gaisler
------------------------------------------------------------------------------
library techmap;
use techmap.gencomp.all;
package config is
-- Technology and synthesis options
constant CFG_FABTECH : integer := virtex5;
constant CFG_MEMTECH : integer := virtex5;
constant CFG_PADTECH : integer := virtex5;
constant CFG_TRANSTECH : integer := GTX1;
constant CFG_NOASYNC : integer := 0;
constant CFG_SCAN : integer := 0;
-- Clock generator
constant CFG_CLKTECH : integer := virtex5;
constant CFG_CLKMUL : integer := (8);
constant CFG_CLKDIV : integer := (10);
constant CFG_OCLKDIV : integer := 1;
constant CFG_OCLKBDIV : integer := 0;
constant CFG_OCLKCDIV : integer := 0;
constant CFG_PCIDLL : integer := 0;
constant CFG_PCISYSCLK: integer := 0;
constant CFG_CLK_NOFB : integer := 1;
-- LEON processor core
constant CFG_LEON : integer := 3;
constant CFG_NCPU : integer := (2);
constant CFG_NWIN : integer := (8);
constant CFG_V8 : integer := 16#32# + 4*0;
constant CFG_MAC : integer := 0;
constant CFG_SVT : integer := 1;
constant CFG_RSTADDR : integer := 16#00000#;
constant CFG_LDDEL : integer := (1);
constant CFG_NWP : integer := (2);
constant CFG_PWD : integer := 1*2;
constant CFG_FPU : integer := 0 + 16*0 + 32*0;
constant CFG_GRFPUSH : integer := 0;
constant CFG_ICEN : integer := 1;
constant CFG_ISETS : integer := 4;
constant CFG_ISETSZ : integer := 4;
constant CFG_ILINE : integer := 8;
constant CFG_IREPL : integer := 0;
constant CFG_ILOCK : integer := 0;
constant CFG_ILRAMEN : integer := 0;
constant CFG_ILRAMADDR: integer := 16#8E#;
constant CFG_ILRAMSZ : integer := 1;
constant CFG_DCEN : integer := 1;
constant CFG_DSETS : integer := 4;
constant CFG_DSETSZ : integer := 4;
constant CFG_DLINE : integer := 4;
constant CFG_DREPL : integer := 0;
constant CFG_DLOCK : integer := 0;
constant CFG_DSNOOP : integer := 1*2 + 4*1;
constant CFG_DFIXED : integer := 16#0#;
constant CFG_BWMASK : integer := 16#0#;
constant CFG_CACHEBW : integer := 128;
constant CFG_DLRAMEN : integer := 0;
constant CFG_DLRAMADDR: integer := 16#8F#;
constant CFG_DLRAMSZ : integer := 1;
constant CFG_MMUEN : integer := 1;
constant CFG_ITLBNUM : integer := 8;
constant CFG_DTLBNUM : integer := 8;
constant CFG_TLB_TYPE : integer := 0 + 0*2;
constant CFG_TLB_REP : integer := 1;
constant CFG_DSU : integer := 1;
constant CFG_ITBSZ : integer := 2 + 64*1;
constant CFG_ATBSZ : integer := 2;
constant CFG_AHBPF : integer := 2;
constant CFG_AHBWP : integer := 1;
constant CFG_LEONFT_EN : integer := 0 + 0*8;
constant CFG_LEON_NETLIST : integer := 0;
constant CFG_DISAS : integer := 0 + 0;
constant CFG_PCLOW : integer := 2;
constant CFG_STAT_ENABLE : integer := 1;
constant CFG_STAT_CNT : integer := (4);
constant CFG_STAT_NMAX : integer := (0);
constant CFG_STAT_DSUEN : integer := 1;
constant CFG_NP_ASI : integer := 1;
constant CFG_WRPSR : integer := 1;
constant CFG_ALTWIN : integer := 0;
constant CFG_REX : integer := 0;
-- L2 Cache
constant CFG_L2_EN : integer := 0;
constant CFG_L2_SIZE : integer := 64;
constant CFG_L2_WAYS : integer := 1;
constant CFG_L2_HPROT : integer := 0;
constant CFG_L2_PEN : integer := 0;
constant CFG_L2_WT : integer := 0;
constant CFG_L2_RAN : integer := 0;
constant CFG_L2_SHARE : integer := 0;
constant CFG_L2_LSZ : integer := 32;
constant CFG_L2_MAP : integer := 16#00F0#;
constant CFG_L2_MTRR : integer := (0);
constant CFG_L2_EDAC : integer := 0;
-- AMBA settings
constant CFG_DEFMST : integer := (0);
constant CFG_RROBIN : integer := 1;
constant CFG_SPLIT : integer := 1;
constant CFG_FPNPEN : integer := 0;
constant CFG_AHBIO : integer := 16#FFF#;
constant CFG_APBADDR : integer := 16#C00#;
constant CFG_AHB_MON : integer := 1;
constant CFG_AHB_MONERR : integer := 1;
constant CFG_AHB_MONWAR : integer := 1;
constant CFG_AHB_DTRACE : integer := 0;
-- DSU UART
constant CFG_AHB_UART : integer := 1;
-- JTAG based DSU interface
constant CFG_AHB_JTAG : integer := 1;
-- Ethernet DSU
constant CFG_DSU_ETH : integer := 1 + 0 + 0;
constant CFG_ETH_BUF : integer := 2;
constant CFG_ETH_IPM : integer := 16#C0A8#;
constant CFG_ETH_IPL : integer := 16#0034#;
constant CFG_ETH_ENM : integer := 16#020000#;
constant CFG_ETH_ENL : integer := 16#000035#;
-- LEON2 memory controller
constant CFG_MCTRL_LEON2 : integer := 1;
constant CFG_MCTRL_RAM8BIT : integer := 0;
constant CFG_MCTRL_RAM16BIT : integer := 1;
constant CFG_MCTRL_5CS : integer := 0;
constant CFG_MCTRL_SDEN : integer := 0;
constant CFG_MCTRL_SEPBUS : integer := 0;
constant CFG_MCTRL_INVCLK : integer := 0;
constant CFG_MCTRL_SD64 : integer := 0;
constant CFG_MCTRL_PAGE : integer := 0 + 0;
-- FTMCTRL memory controller
constant CFG_MCTRLFT : integer := 0;
constant CFG_MCTRLFT_RAM8BIT : integer := 0;
constant CFG_MCTRLFT_RAM16BIT : integer := 0;
constant CFG_MCTRLFT_5CS : integer := 0;
constant CFG_MCTRLFT_SDEN : integer := 0;
constant CFG_MCTRLFT_SEPBUS : integer := 0;
constant CFG_MCTRLFT_INVCLK : integer := 0;
constant CFG_MCTRLFT_SD64 : integer := 0;
constant CFG_MCTRLFT_EDAC : integer := 0 + 0 + 0;
constant CFG_MCTRLFT_PAGE : integer := 0 + 0;
constant CFG_MCTRLFT_ROMASEL : integer := 0;
constant CFG_MCTRLFT_WFB : integer := 0;
constant CFG_MCTRLFT_NET : integer := 0;
-- DDR controller
constant CFG_DDR2SP : integer := 1;
constant CFG_DDR2SP_INIT : integer := 1;
constant CFG_DDR2SP_FREQ : integer := 100;
constant CFG_DDR2SP_TRFC : integer := (130);
constant CFG_DDR2SP_DATAWIDTH : integer := (64);
constant CFG_DDR2SP_FTEN : integer := 0;
constant CFG_DDR2SP_FTWIDTH : integer := 0;
constant CFG_DDR2SP_COL : integer := (10);
constant CFG_DDR2SP_SIZE : integer := (512);
constant CFG_DDR2SP_DELAY0 : integer := (8);
constant CFG_DDR2SP_DELAY1 : integer := (8);
constant CFG_DDR2SP_DELAY2 : integer := (8);
constant CFG_DDR2SP_DELAY3 : integer := (8);
constant CFG_DDR2SP_DELAY4 : integer := (8);
constant CFG_DDR2SP_DELAY5 : integer := (8);
constant CFG_DDR2SP_DELAY6 : integer := (8);
constant CFG_DDR2SP_DELAY7 : integer := (8);
constant CFG_DDR2SP_NOSYNC : integer := 1;
-- AHB status register
constant CFG_AHBSTAT : integer := 1;
constant CFG_AHBSTATN : integer := (1);
-- AHB ROM
constant CFG_AHBROMEN : integer := 0;
constant CFG_AHBROPIP : integer := 0;
constant CFG_AHBRODDR : integer := 16#000#;
constant CFG_ROMADDR : integer := 16#000#;
constant CFG_ROMMASK : integer := 16#E00# + 16#000#;
-- AHB RAM
constant CFG_AHBRAMEN : integer := 0;
constant CFG_AHBRSZ : integer := 4;
constant CFG_AHBRADDR : integer := 16#A00#;
constant CFG_AHBRPIPE : integer := 0;
-- Gaisler Ethernet core
constant CFG_GRETH : integer := 1;
constant CFG_GRETH1G : integer := 0;
constant CFG_ETH_FIFO : integer := 64;
-- Gaisler Ethernet core
constant CFG_GRETH2 : integer := 1;
constant CFG_GRETH21G : integer := 0;
constant CFG_ETH2_FIFO : integer := 64;
-- UART 1
constant CFG_UART1_ENABLE : integer := 1;
constant CFG_UART1_FIFO : integer := 4;
-- LEON3 interrupt controller
constant CFG_IRQ3_ENABLE : integer := 1;
constant CFG_IRQ3_NSEC : integer := 0;
-- Modular timer
constant CFG_GPT_ENABLE : integer := 1;
constant CFG_GPT_NTIM : integer := (2);
constant CFG_GPT_SW : integer := (8);
constant CFG_GPT_TW : integer := (32);
constant CFG_GPT_IRQ : integer := (8);
constant CFG_GPT_SEPIRQ : integer := 1;
constant CFG_GPT_WDOGEN : integer := 0;
constant CFG_GPT_WDOG : integer := 16#0#;
-- GPIO port
constant CFG_GRGPIO_ENABLE : integer := 1;
constant CFG_GRGPIO_IMASK : integer := 16#0060#;
constant CFG_GRGPIO_WIDTH : integer := (12);
-- I2C master
constant CFG_I2C_ENABLE : integer := 1;
-- SPI controller
constant CFG_SPICTRL_ENABLE : integer := 1;
constant CFG_SPICTRL_NUM : integer := (1);
constant CFG_SPICTRL_SLVS : integer := (1);
constant CFG_SPICTRL_FIFO : integer := (2);
constant CFG_SPICTRL_SLVREG : integer := 1;
constant CFG_SPICTRL_ODMODE : integer := 0;
constant CFG_SPICTRL_AM : integer := 0;
constant CFG_SPICTRL_ASEL : integer := 0;
constant CFG_SPICTRL_TWEN : integer := 0;
constant CFG_SPICTRL_MAXWLEN : integer := (0);
constant CFG_SPICTRL_SYNCRAM : integer := 0;
constant CFG_SPICTRL_FT : integer := 0;
-- GRPCI2 interface
constant CFG_GRPCI2_MASTER : integer := 1;
constant CFG_GRPCI2_TARGET : integer := 1;
constant CFG_GRPCI2_DMA : integer := 1;
constant CFG_GRPCI2_VID : integer := 16#1AC8#;
constant CFG_GRPCI2_DID : integer := 16#0054#;
constant CFG_GRPCI2_CLASS : integer := 16#000000#;
constant CFG_GRPCI2_RID : integer := 16#00#;
constant CFG_GRPCI2_CAP : integer := 16#40#;
constant CFG_GRPCI2_NCAP : integer := 16#00#;
constant CFG_GRPCI2_BAR0 : integer := (26);
constant CFG_GRPCI2_BAR1 : integer := (0);
constant CFG_GRPCI2_BAR2 : integer := (0);
constant CFG_GRPCI2_BAR3 : integer := (0);
constant CFG_GRPCI2_BAR4 : integer := (0);
constant CFG_GRPCI2_BAR5 : integer := (0);
constant CFG_GRPCI2_FDEPTH : integer := 3;
constant CFG_GRPCI2_FCOUNT : integer := 2;
constant CFG_GRPCI2_ENDIAN : integer := 0;
constant CFG_GRPCI2_DEVINT : integer := 1;
constant CFG_GRPCI2_DEVINTMSK : integer := 16#0#;
constant CFG_GRPCI2_HOSTINT : integer := 1;
constant CFG_GRPCI2_HOSTINTMSK: integer := 16#0#;
constant CFG_GRPCI2_TRACE : integer := 1024;
constant CFG_GRPCI2_TRACEAPB : integer := 0;
constant CFG_GRPCI2_BYPASS : integer := 0;
constant CFG_GRPCI2_EXTCFG : integer := (0);
-- PCI arbiter
constant CFG_PCI_ARB : integer := 1;
constant CFG_PCI_ARBAPB : integer := 1;
constant CFG_PCI_ARB_NGNT : integer := (8);
-- SVGA controller
constant CFG_SVGA_ENABLE : integer := 0;
-- AMBA System ACE Interface Controller
constant CFG_GRACECTRL : integer := 1;
-- AMBA Wrapper for Xilinx System Monitor
constant CFG_GRSYSMON : integer := 0;
-- GRLIB debugging
constant CFG_DUART : integer := 0;
end;
| gpl-3.0 | 5d202519f1e2aae265867f294893bc15 | 0.654496 | 3.468676 | false | false | false | false |
pwsoft/fpga_examples | rtl/ttl/ttl_74138.vhd | 1 | 4,010 | -- -----------------------------------------------------------------------
--
-- Syntiac VHDL support files.
--
-- -----------------------------------------------------------------------
-- Copyright 2005-2018 by Peter Wendrich ([email protected])
-- http://www.syntiac.com
--
-- This source file is free software: you can redistribute it and/or modify
-- it under the terms of the GNU Lesser General Public License as published
-- by the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This source file is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
-- -----------------------------------------------------------------------
-- 3 to 8 line demultiplexer
-- -----------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.ALL;
use work.ttl_pkg.all;
-- -----------------------------------------------------------------------
entity ttl_74138 is
generic (
latency : integer := 2
);
port (
emuclk : in std_logic;
p1 : in ttl_t; -- S0
p2 : in ttl_t; -- S1
p3 : in ttl_t; -- S2
p4 : in ttl_t; -- nE1
p5 : in ttl_t; -- nE2
p6 : in ttl_t; -- E3
p15 : out ttl_t; -- nY0
p14 : out ttl_t; -- nY1
p13 : out ttl_t; -- nY2
p12 : out ttl_t; -- nY3
p11 : out ttl_t; -- nY4
p10 : out ttl_t; -- nY5
p9 : out ttl_t; -- nY6
p7 : out ttl_t -- nY7
);
end entity;
architecture rtl of ttl_74138 is
signal p7_loc : ttl_t;
signal p9_loc : ttl_t;
signal p10_loc : ttl_t;
signal p11_loc : ttl_t;
signal p12_loc : ttl_t;
signal p13_loc : ttl_t;
signal p14_loc : ttl_t;
signal p15_loc : ttl_t;
begin
p7_latency_inst : entity work.ttl_latency
generic map (latency => latency)
port map (clk => emuclk, d => p7_loc, q => p7);
p9_latency_inst : entity work.ttl_latency
generic map (latency => latency)
port map (clk => emuclk, d => p9_loc, q => p9);
p10_latency_inst : entity work.ttl_latency
generic map (latency => latency)
port map (clk => emuclk, d => p10_loc, q => p10);
p11_latency_inst : entity work.ttl_latency
generic map (latency => latency)
port map (clk => emuclk, d => p11_loc, q => p11);
p12_latency_inst : entity work.ttl_latency
generic map (latency => latency)
port map (clk => emuclk, d => p12_loc, q => p12);
p13_latency_inst : entity work.ttl_latency
generic map (latency => latency)
port map (clk => emuclk, d => p13_loc, q => p13);
p14_latency_inst : entity work.ttl_latency
generic map (latency => latency)
port map (clk => emuclk, d => p14_loc, q => p14);
p15_latency_inst : entity work.ttl_latency
generic map (latency => latency)
port map (clk => emuclk, d => p15_loc, q => p15);
p7_loc <= ZERO when is_high(p1) and is_high(p2) and is_high(p3) and is_low(p4) and is_low(p5) and is_high(p6) else ONE;
p9_loc <= ZERO when is_low(p1) and is_high(p2) and is_high(p3) and is_low(p4) and is_low(p5) and is_high(p6) else ONE;
p10_loc <= ZERO when is_high(p1) and is_low(p2) and is_high(p3) and is_low(p4) and is_low(p5) and is_high(p6) else ONE;
p11_loc <= ZERO when is_low(p1) and is_low(p2) and is_high(p3) and is_low(p4) and is_low(p5) and is_high(p6) else ONE;
p12_loc <= ZERO when is_high(p1) and is_high(p2) and is_low(p3) and is_low(p4) and is_low(p5) and is_high(p6) else ONE;
p13_loc <= ZERO when is_low(p1) and is_high(p2) and is_low(p3) and is_low(p4) and is_low(p5) and is_high(p6) else ONE;
p14_loc <= ZERO when is_high(p1) and is_low(p2) and is_low(p3) and is_low(p4) and is_low(p5) and is_high(p6) else ONE;
p15_loc <= ZERO when is_low(p1) and is_low(p2) and is_low(p3) and is_low(p4) and is_low(p5) and is_high(p6) else ONE;
end architecture;
| lgpl-2.1 | a1cf0a3b01bf35c0181392b7d0bd0472 | 0.597506 | 2.767426 | false | false | false | false |
EliasLuiz/TCC | Leon3/lib/gaisler/pci/ptf/pt_pci_master.vhd | 1 | 19,332 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: pt_pci_master
-- File: pt_pci_master.vhd
-- Author: Nils Johan Wessman, Aeroflex Gaisler
-- Description: PCI Testbench Master
------------------------------------------------------------------------------
-- pragma translate_off
library ieee;
use ieee.std_logic_1164.all;
library grlib;
library gaisler;
use gaisler.pt_pkg.all;
library grlib;
use grlib.stdlib.xorv;
use grlib.stdlib.tost;
use grlib.testlib.print;
entity pt_pci_master is
generic (
slot : integer := 0;
tval : time := 7 ns);
port (
-- PCI signals
pciin : in pci_type;
pciout : out pci_type;
-- Debug interface signals
dbgi : in pt_pci_master_in_type;
dbgo : out pt_pci_master_out_type
);
end pt_pci_master;
architecture behav of pt_pci_master is
-- NEW =>
type access_element_type;
type access_element_ptr is access access_element_type;
type access_element_type is record
acc : pt_pci_access_type;
nxt : access_element_ptr;
end record;
constant idle_acc : pt_pci_access_type := ((others => '0'), (others => '0'), (others => '0'), (others => '0'),
0, 0, 0, 0, false, false, false, false, 0, 0);
signal pci_core : pt_pci_master_in_type;
signal core_pci : pt_pci_master_out_type;
-- Description: Insert a access at the "tail" of the linked list of accesses
procedure add_acc (
variable acc_head : inout access_element_ptr;
variable acc_tail : inout access_element_ptr;
signal acc : in pt_pci_access_type) is
variable elem : access_element_ptr;
begin -- insert_access
elem := acc_tail;
if elem /= NULL then
elem.nxt := new access_element_type'(acc, NULL);
acc_tail := elem.nxt;
else
acc_head := new access_element_type'(acc, NULL);
acc_tail := acc_head;
end if;
end add_acc;
-- Description: Get the access at the "head" of the linked list of accesses
-- and remove if from the list
procedure pop_acc (
variable acc_head : inout access_element_ptr;
variable acc_tail : inout access_element_ptr;
signal acc : out pt_pci_access_type;
variable found : out boolean) is
variable elem : access_element_ptr;
begin -- pop_access
elem := acc_head;
if elem /= NULL then
found := true;
acc <= elem.acc;
if elem = acc_tail then
acc_head := NULL;
acc_tail := NULL;
else
acc_head := elem.nxt;
end if;
deallocate(elem);
else
found := false;
acc <= idle_acc;
end if;
end pop_acc;
-- Description: Searches the list for a result to a particular id.
procedure get_res (
variable res_head : inout access_element_ptr;
variable res_tail : inout access_element_ptr;
signal accin : in pt_pci_access_type;
signal acc : out pt_pci_access_type;
variable found : out boolean) is
variable elem, prev : access_element_ptr;
variable lfound : boolean := false;
begin -- get_result
prev := res_head;
elem := res_head;
while elem /= NULL and not lfound loop
-- Check if result is a match for id
if accin.id = elem.acc.id then
acc <= elem.acc;
lfound := true;
if prev = res_head then
res_head := elem.nxt;
else
prev.nxt := elem.nxt;
end if;
if elem = res_tail then
res_tail := NULL;
end if;
deallocate(elem);
end if;
if not lfound then
prev := elem;
elem := elem.nxt;
end if;
end loop;
if lfound then found := true;
else found := false; acc <= idle_acc; end if;
end get_res;
-- Description:
procedure rm_acc (
variable acc_head : inout access_element_ptr;
variable acc_tail : inout access_element_ptr;
signal acc : in pt_pci_access_type;
constant rmall : in boolean )is
variable elem, prev : access_element_ptr;
variable lfound : boolean := false;
begin -- rm_access
prev := acc_head;
elem := acc_head;
while elem /= NULL and not lfound loop
if rmall = true then
prev := elem;
elem := elem.nxt;
deallocate(prev);
else
if acc.addr = elem.acc.addr then
if prev = acc_head then
acc_head := elem.nxt;
else
prev.nxt := elem.nxt;
end if;
if elem = acc_tail then
acc_tail := NULL;
end if;
deallocate(elem);
lfound := true;
else
prev := elem;
elem := elem.nxt;
end if;
end if;
end loop;
if rmall = true then
acc_head := NULL;
acc_tail := NULL;
end if;
end rm_acc;
-- <= NEW
type state_type is(idle, addr, data, turn, active, done);
type reg_type is record
state : state_type;
pcien : std_logic_vector(3 downto 0);
perren : std_logic_vector(1 downto 0);
read : std_logic;
grant : std_logic;
perr_ad : std_logic_vector(31 downto 0);
perr_cbe : std_logic_vector(3 downto 0);
devsel_timeout : integer range 0 to 3;
pci : pci_type;
acc : pt_pci_access_type;
parerr : std_logic;
end record;
signal r,rin : reg_type;
begin
-- NEW =>
core_acc : process
variable acc_head : access_element_ptr := NULL;
variable acc_tail : access_element_ptr := NULL;
variable res_head : access_element_ptr := NULL;
variable res_tail : access_element_ptr := NULL;
variable res_to_find : pt_pci_access_type := idle_acc;
variable found : boolean;
begin
if pci_core.req /= '1' and dbgi.req /= '1' then
wait until pci_core.req = '1' or dbgi.req = '1';
end if;
if dbgi.req = '1' then
dbgo.res_found <= '0';
if dbgi.add = true then
add_acc(acc_head, acc_tail, dbgi.acc);
elsif dbgi.remove = true then
rm_acc(acc_head, acc_tail, dbgi.acc, dbgi.rmall);
elsif dbgi.get_res = true then
dbgo.valid <= false;
get_res(res_head, res_tail, dbgi.acc, dbgo.acc, found);
if found = true then dbgo.valid <= true; res_to_find := idle_acc;
else res_to_find := dbgi.acc; end if;
else
dbgo.valid <= false;
pop_acc(acc_head, acc_tail, dbgo.acc, found);
if found = true then dbgo.valid <= true; end if;
end if;
dbgo.ack <= '1';
wait until dbgi.req = '0';
dbgo.ack <= '0';
end if;
if pci_core.req = '1' then
if pci_core.add = true then
add_acc(acc_head, acc_tail, pci_core.acc);
elsif pci_core.add_res = true then
add_acc(res_head, res_tail, pci_core.acc);
if res_to_find.valid = true and pci_core.acc.id = res_to_find.id then
dbgo.res_found <= '1';
end if;
else
core_pci.valid <= false;
pop_acc(acc_head, acc_tail, core_pci.acc, found);
if found = true then core_pci.valid <= true; end if;
end if;
core_pci.ack <= '1';
wait until pci_core.req = '0';
core_pci.ack <= '0';
end if;
end process;
-- <= NEW
pt_pci_core : process
procedure sync_with_core is
begin
pci_core.req <= '1';
wait until core_pci.ack = '1';
pci_core.req <= '0';
wait until core_pci.ack = '0';
end sync_with_core;
function check_data(
constant pci_data : std_logic_vector(31 downto 0);
constant comp_data : std_logic_vector(31 downto 0);
constant cbe : std_logic_vector(3 downto 0))
return boolean is
variable res : boolean := true;
variable data : std_logic_vector(31 downto 0);
begin
data := comp_data;
if cbe(0) = '1' then data(7 downto 0) := (others => '-'); end if;
if cbe(1) = '1' then data(15 downto 8) := (others => '-'); end if;
if cbe(2) = '1' then data(23 downto 16) := (others => '-'); end if;
if cbe(3) = '1' then data(31 downto 24) := (others => '-'); end if;
for i in 0 to 31 loop
if pci_data(i) /= data(i) and data(i) /= '-' then res := false; end if;
end loop;
return res;
end check_data;
variable v : reg_type;
variable vpciin : pci_type;
begin
if to_x01(pciin.syst.rst) = '0' then
v.state := idle;
v.pcien := (others => '0');
v.pci := pci_idle;
v.pci.ifc.frame := '1';
v.pci.ifc.irdy := '1';
v.read := '0';
v.perren := (others => '0');
v.parerr := '0';
elsif rising_edge(pciin.syst.clk) then
v := r;
vpciin := pciin;
v.grant := to_x01(vpciin.ifc.frame) and to_x01(vpciin.ifc.irdy) and not r.pci.arb.req(slot) and not to_x01(vpciin.arb.gnt(slot));
v.pcien(1) := r.pcien(0); v.pcien(2) := r.pcien(1);
v.pci.ad.par := xorv(r.pci.ad.ad & r.pci.ad.cbe & r.parerr);
v.perr_ad := vpciin.ad.ad; v.perr_cbe := vpciin.ad.cbe;
v.pci.err.perr := (not xorv(r.perr_ad & r.perr_cbe & to_x01(vpciin.ad.par))) or not r.read;
v.perren(1) := r.perren(0);
case r.state is
when idle =>
if core_pci.valid = true then
if r.acc.idle = false then
v.pci.arb.req(slot) := '0';
if v.grant = '1' then
v.pcien(0) := '1';
v.pci.ifc.frame := '0';
v.pci.ad.ad := core_pci.acc.addr;
v.pci.ad.cbe := core_pci.acc.cbe_cmd;
if core_pci.acc.parerr = 2 then v.parerr := '1'; else v.parerr := '0'; end if;
v.state := addr;
v.read := '0';
v.perren := (others => '0');
end if;
else -- Idle cycle
if r.acc.ws <= 0 then
if r.acc.list_res = true then -- store result
pci_core.acc <= r.acc;
pci_core.add_res <= true; pci_core.add <= false; pci_core.remove <= false; sync_with_core;
wait for 1 ps;
end if;
pci_core.add_res <= false; pci_core.add <= false; pci_core.remove <= false; sync_with_core;
v.acc := core_pci.acc;
else
v.acc.ws := r.acc.ws - 1;
end if;
end if;
else
pci_core.add_res <= false; pci_core.add <= false; pci_core.remove <= false; sync_with_core;
v.acc := core_pci.acc;
end if;
when addr =>
if r.acc.last = true and r.acc.ws <= 0 then v.pci.ifc.frame := '1'; v.pci.arb.req(slot) := '1'; end if;
if (r.acc.cbe_cmd = MEM_READ or r.acc.cbe_cmd = MEM_R_MULT or r.acc.cbe_cmd = MEM_R_LINE
or r.acc.cbe_cmd = IO_READ or r.acc.cbe_cmd = CONF_READ) then
v.read := '1';
end if;
if r.acc.ws <= 0 then v.pci.ifc.irdy := '0'; v.pci.ad.ad := r.acc.data;
else v.acc.ws := r.acc.ws - 1; v.pci.ad.ad := (others => '-'); end if;
v.pci.ad.cbe := r.acc.cbe_data;
if core_pci.acc.parerr = 1 then v.parerr := '1'; else v.parerr := '0'; end if;
v.state := data;
v.devsel_timeout := 0;
when data =>
if r.pci.ifc.irdy = '1' and r.acc.ws /= 0 then
v.acc.ws := r.acc.ws - 1;
else
v.pci.ifc.irdy := '0';
v.pci.ad.ad := r.acc.data;
if r.acc.last = true or to_x01(vpciin.ifc.stop) = '0' then v.pci.ifc.frame := '1'; v.pci.arb.req(slot) := '1'; end if;
end if;
if to_x01(vpciin.ifc.devsel) = '1' then
if r.devsel_timeout < 3 then
v.devsel_timeout := r.devsel_timeout + 1;
else
v.pci.ifc.frame := '1';
v.pci.ifc.irdy := '1';
if r.pci.ifc.frame = '1' then
v.pcien(0) := '0';
v.state := idle;
if r.acc.list_res = true then -- store result
pci_core.acc <= r.acc; -- should set Master abort status in this response
pci_core.add_res <= true; pci_core.add <= false; pci_core.remove <= false; sync_with_core;
wait for 1 ps;
end if;
pci_core.add_res <= false; pci_core.add <= false; pci_core.remove <= false; sync_with_core;
v.acc := core_pci.acc;
if r.acc.debug >= 1 then
if r.read = '1' then
print("ERROR: PCITBM Read[" & tost(r.acc.addr) & "]: MASTER ABORT");
else
print("ERROR: PCITBM WRITE[" & tost(r.acc.addr) & "]: MASTER ABORT");
end if;
end if;
end if;
end if;
end if;
--if to_x01(vpciin.ifc.trdy) = '0' and r.pci.ifc.irdy = '0' then
if (to_x01(vpciin.ifc.trdy) = '0' or (r.acc.cod = 1 and to_x01(vpciin.ifc.stop) = '0')) and r.pci.ifc.irdy = '0' then
if r.read = '1' then v.perren(0) := '1'; end if; -- only drive perr from read
if r.pci.ifc.frame = '1' then -- done
v.pcien(0) := '0'; v.pci.ifc.irdy := '1';
if r.acc.list_res = true then -- store result
pci_core.acc <= r.acc;
if r.read = '1' then pci_core.acc.data <= vpciin.ad.ad; end if;
pci_core.add_res <= true; pci_core.add <= false; pci_core.remove <= false; sync_with_core;
wait for 1 ps;
end if;
pci_core.add_res <= false; pci_core.add <= false; pci_core.remove <= false; sync_with_core;
v.acc := core_pci.acc;
v.state := idle;
else
if r.acc.list_res = true then -- store result
pci_core.acc <= r.acc;
if r.read = '1' then pci_core.acc.data <= vpciin.ad.ad; end if;
pci_core.add_res <= true; pci_core.add <= false; pci_core.remove <= false; sync_with_core;
wait for 1 ps;
end if;
pci_core.add_res <= false; pci_core.add <= false; pci_core.remove <= false; sync_with_core;
v.acc := core_pci.acc;
if core_pci.valid = true then
v.pci.ad.cbe := v.acc.cbe_data;
if core_pci.acc.parerr = 1 then v.parerr := '1'; else v.parerr := '0'; end if;
if v.acc.ws <= 0 then
v.pci.ad.ad := v.acc.data;
if v.acc.last = true or to_x01(vpciin.ifc.stop) = '0' then v.pci.ifc.frame := '1'; v.pci.arb.req(slot) := '1'; end if;
else
v.pci.ad.ad := (others => '-');
if v.pci.ifc.frame = '0' then v.pci.ifc.irdy := '1'; end if; -- If frame => '1', do not add waitstates (irdey => '1')
v.acc.ws := v.acc.ws - 1;
end if;
else
assert false
report "No valid acces in list, access required! (no access is marked LAST)"
severity FAILURE;
end if;
end if;
if r.acc.debug >= 1 then
if r.acc.cod = 1 and to_x01(vpciin.ifc.stop) = '0' and to_x01(vpciin.ifc.trdy) = '1' then
if r.read = '1' then
print("PCITBM Read[" & tost(r.acc.addr) & "]: CANCELED ON DISCONNECT");
else
print("PCITBM WRITE[" & tost(r.acc.addr) & "]: CANCELED ON DISCONNECT");
end if;
else
if r.read = '1' then
if check_data(vpciin.ad.ad, r.pci.ad.ad, r.pci.ad.cbe) = false then
print("ERROR: PCITBM Read[" & tost(r.acc.addr) & "]: " & tost(vpciin.ad.ad) & " != " & tost(r.pci.ad.ad));
elsif r.acc.debug >= 2 then
print("PCITBM Read[" & tost(r.acc.addr) & "]: " & tost(vpciin.ad.ad));
end if;
else
if r.acc.debug >= 2 then
print("PCITBM Write[" & tost(r.acc.addr) & "]: " & tost(vpciin.ad.ad));
end if;
end if;
end if;
end if;
elsif to_x01(vpciin.ifc.stop) = '0' and r.pci.ifc.frame = '1' then -- Disconnect
v.pcien(0) := '0';
v.pci.ifc.irdy := '1';
v.state := idle;
if to_x01(vpciin.ifc.devsel) = '1' then
if r.acc.list_res = true then -- store result
pci_core.acc <= r.acc; -- should set Master abort status in this response
pci_core.add_res <= true; pci_core.add <= false; pci_core.remove <= false; sync_with_core;
wait for 1 ps;
end if;
pci_core.add_res <= false; pci_core.add <= false; pci_core.remove <= false; sync_with_core;
v.acc := core_pci.acc;
if r.acc.debug >= 1 then
if r.read = '1' then
print("ERROR: PCITBM Read[" & tost(r.acc.addr) & "]: TARGET ABORT");
else
print("ERROR: PCITBM WRITE[" & tost(r.acc.addr) & "]: TARGET ABORT");
end if;
end if;
end if;
end if;
when turn =>
when active =>
when done =>
when others =>
end case;
end if;
r <= v;
wait on pciin.syst.clk, pciin.syst.rst;
end process;
pciout.ad.ad <= r.pci.ad.ad after tval when (r.pcien(0) and not r.read) = '1' else (others => 'Z') after tval;
pciout.ad.cbe <= r.pci.ad.cbe after tval when r.pcien(0) = '1' else (others => 'Z') after tval;
pciout.ad.par <= r.pci.ad.par after tval when (r.pcien(1) = '1' and (r.read = '0' or r.pcien(3 downto 0) = "0011")) else 'Z' after tval;
pciout.ifc.frame <= r.pci.ifc.frame after tval when r.pcien(0) = '1' else 'Z' after tval;
pciout.ifc.irdy <= r.pci.ifc.irdy after tval when r.pcien(1) = '1' else 'Z' after tval;
pciout.err.perr <= r.pci.err.perr after tval when (r.pcien(2) and r.perren(1)) = '1' else 'Z' after tval;
pciout.err.serr <= r.pci.err.serr after tval when r.pcien(2) = '1' else 'Z' after tval;
-- Unused signals
pciout.arb <= arb_const;
pciout.arb.req(slot) <= r.pci.arb.req(slot) after tval;
-- Unused signals
pciout.ifc.trdy <= 'Z';
pciout.ifc.stop <= 'Z';
pciout.ifc.devsel <= 'Z';
pciout.ifc.lock <= 'Z';
pciout.ifc.idsel <= (others => 'Z');
pciout.err.serr <= 'Z';
pciout.syst <= syst_const;
pciout.ext64 <= ext64_const;
pciout.cache <= cache_const;
pciout.int <= (others => 'Z');
end;
-- pragma translate_on
| gpl-3.0 | f45c3b83f1515f153097b07c3b86225e | 0.529226 | 3.349272 | false | false | false | false |
EliasLuiz/TCC | Leon3/designs/leon3-asic/bschain.vhd | 1 | 11,953 | -----------------------------------------------------------------------------
-- LEON3 Demonstration design
-- Copyright (C) 2013, Aeroflex Gaisler AB
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library gaisler;
use gaisler.jtag.all;
use work.config.all;
entity bschain is
generic (tech: integer := CFG_FABTECH;
enable: integer range 0 to 1 := CFG_BOUNDSCAN_EN;
hzsup: integer range 0 to 1 := 1);
port (
-- Chain control signals
chain_tck : in std_ulogic;
chain_tckn : in std_ulogic;
chain_tdi : in std_ulogic;
chain_tdo : out std_ulogic;
bsshft : in std_ulogic;
bscapt : in std_ulogic;
bsupdi : in std_ulogic;
bsupdo : in std_ulogic;
bsdrive : in std_ulogic;
bshighz : in std_ulogic;
-- Pad-side signals
Presetn : in std_ulogic;
Pclksel : in std_logic_vector (1 downto 0);
Pclk : in std_ulogic;
Perrorn : out std_ulogic;
Paddress : out std_logic_vector(27 downto 0);
Pdatain : in std_logic_vector(31 downto 0);
Pdataout : out std_logic_vector(31 downto 0);
Pdataen : out std_logic_vector(31 downto 0);
Pcbin : in std_logic_vector(7 downto 0);
Pcbout : out std_logic_vector(7 downto 0);
Pcben : out std_logic_vector(7 downto 0);
Psdclk : out std_ulogic;
Psdcsn : out std_logic_vector (1 downto 0); -- sdram chip select
Psdwen : out std_ulogic; -- sdram write enable
Psdrasn : out std_ulogic; -- sdram ras
Psdcasn : out std_ulogic; -- sdram cas
Psddqm : out std_logic_vector (3 downto 0); -- sdram dqm
Pdsutx : out std_ulogic; -- DSU tx data
Pdsurx : in std_ulogic; -- DSU rx data
Pdsuen : in std_ulogic;
Pdsubre : in std_ulogic;
Pdsuact : out std_ulogic;
Ptxd1 : out std_ulogic; -- UART1 tx data
Prxd1 : in std_ulogic; -- UART1 rx data
Ptxd2 : out std_ulogic; -- UART2 tx data
Prxd2 : in std_ulogic; -- UART2 rx data
Pramsn : out std_logic_vector (4 downto 0);
Pramoen : out std_logic_vector (4 downto 0);
Prwen : out std_logic_vector (3 downto 0);
Poen : out std_ulogic;
Pwriten : out std_ulogic;
Pread : out std_ulogic;
Piosn : out std_ulogic;
Promsn : out std_logic_vector (1 downto 0);
Pbrdyn : in std_ulogic;
Pbexcn : in std_ulogic;
Pwdogn : out std_ulogic;
Pgpioin : in std_logic_vector(CFG_GRGPIO_WIDTH-1 downto 0); -- I/O port
Pgpioout : out std_logic_vector(CFG_GRGPIO_WIDTH-1 downto 0); -- I/O port
Pgpioen : out std_logic_vector(CFG_GRGPIO_WIDTH-1 downto 0); -- I/O port
Pprom32 : in std_ulogic;
Ppromedac : in std_ulogic;
Pspw_clksel : in std_logic_vector (1 downto 0);
Pspw_clk : in std_ulogic;
Pspw_rxd : in std_logic_vector(0 to CFG_SPW_NUM-1);
Pspw_rxs : in std_logic_vector(0 to CFG_SPW_NUM-1);
Pspw_txd : out std_logic_vector(0 to CFG_SPW_NUM-1);
Pspw_txs : out std_logic_vector(0 to CFG_SPW_NUM-1);
Pspw_ten : out std_logic_vector(0 to CFG_SPW_NUM-1);
Plclk2x : in std_ulogic;
Plclk4x : in std_ulogic;
Plclkdis : out std_ulogic;
Plclklock : in std_ulogic;
Plock : out std_ulogic;
Proen : in std_ulogic;
Proout : out std_ulogic;
-- Core-side signals
Cresetn : out std_ulogic;
Cclksel : out std_logic_vector (1 downto 0);
Cclk : out std_ulogic;
Cerrorn : in std_ulogic;
Caddress : in std_logic_vector(27 downto 0);
Cdatain : out std_logic_vector(31 downto 0);
Cdataout : in std_logic_vector(31 downto 0);
Cdataen : in std_logic_vector(31 downto 0);
Ccbin : out std_logic_vector(7 downto 0);
Ccbout : in std_logic_vector(7 downto 0);
Ccben : in std_logic_vector(7 downto 0);
Csdclk : in std_ulogic;
Csdcsn : in std_logic_vector (1 downto 0); -- sdram chip select
Csdwen : in std_ulogic; -- sdram write enable
Csdrasn : in std_ulogic; -- sdram ras
Csdcasn : in std_ulogic; -- sdram cas
Csddqm : in std_logic_vector (3 downto 0); -- sdram dqm
Cdsutx : in std_ulogic; -- DSU tx data
Cdsurx : out std_ulogic; -- DSU rx data
Cdsuen : out std_ulogic;
Cdsubre : out std_ulogic;
Cdsuact : in std_ulogic;
Ctxd1 : in std_ulogic; -- UART1 tx data
Crxd1 : out std_ulogic; -- UART1 rx data
Ctxd2 : in std_ulogic; -- UART2 tx data
Crxd2 : out std_ulogic; -- UART2 rx data
Cramsn : in std_logic_vector (4 downto 0);
Cramoen : in std_logic_vector (4 downto 0);
Crwen : in std_logic_vector (3 downto 0);
Coen : in std_ulogic;
Cwriten : in std_ulogic;
Cread : in std_ulogic;
Ciosn : in std_ulogic;
Cromsn : in std_logic_vector (1 downto 0);
Cbrdyn : out std_ulogic;
Cbexcn : out std_ulogic;
Cwdogn : in std_ulogic;
Cgpioin : out std_logic_vector(CFG_GRGPIO_WIDTH-1 downto 0); -- I/O port
Cgpioout : in std_logic_vector(CFG_GRGPIO_WIDTH-1 downto 0); -- I/O port
Cgpioen : in std_logic_vector(CFG_GRGPIO_WIDTH-1 downto 0); -- I/O port
Cprom32 : out std_ulogic;
Cpromedac : out std_ulogic;
Cspw_clksel : out std_logic_vector (1 downto 0);
Cspw_clk : out std_ulogic;
Cspw_rxd : out std_logic_vector(0 to CFG_SPW_NUM-1);
Cspw_rxs : out std_logic_vector(0 to CFG_SPW_NUM-1);
Cspw_txd : in std_logic_vector(0 to CFG_SPW_NUM-1);
Cspw_txs : in std_logic_vector(0 to CFG_SPW_NUM-1);
Cspw_ten : in std_logic_vector(0 to CFG_SPW_NUM-1);
Clclk2x : out std_ulogic;
Clclk4x : out std_ulogic;
Clclkdis : in std_ulogic;
Clclklock : out std_ulogic;
Clock : in std_ulogic;
Croen : out std_ulogic;
Croout : in std_ulogic
);
end;
architecture rtl of bschain is
signal sr1_tdi, sr1a_tdi, sr2a_tdi, sr2_tdi, sr3a_tdi, sr3_tdi, sr4_tdi: std_ulogic;
signal sr1i, sr1o: std_logic_vector(4 downto 0);
signal sr3i, sr3o: std_logic_vector(41 downto 0);
signal sr5i, sr5o: std_logic_vector(11+5*CFG_SPW_NUM downto 0);
begin
-----------------------------------------------------------------------------
-- Scan chain registers (note: adjust order to match pad ring)
sr1a: bscanregs
generic map (tech => tech, nsigs => sr1i'length, dirmask => 2#00001#, enable => enable)
port map (sr1i, sr1o, chain_tck, chain_tckn, sr1a_tdi, chain_tdo,
bsshft, bscapt, bsupdi, bsupdo, bsdrive, bshighz);
sr1i <= Presetn & Pclksel & Pclk & Cerrorn;
Cresetn <= sr1o(4); Cclksel <= sr1o(3 downto 2);
Cclk <= sr1o(1); Perrorn <= sr1o(0);
sr1b: bscanregs
generic map (tech => tech, nsigs => Paddress'length, dirmask => 16#3FFFFFFF#, enable => enable)
port map (Caddress, Paddress, chain_tck, chain_tckn, sr1_tdi, sr1a_tdi,
bsshft, bscapt, bsupdi, bsupdo, bsdrive, bshighz);
sr2a: bscanregsbd
generic map (tech => tech, nsigs => Pdataout'length, enable => enable, hzsup => hzsup)
port map (Pdataout, Pdataen, Pdatain, Cdataout, Cdataen, Cdatain,
chain_tck, chain_tckn, sr2a_tdi, sr1_tdi,
bsshft, bscapt, bsupdi, bsupdo, bsdrive, bshighz);
sr2b: bscanregsbd
generic map (tech => tech, nsigs => Pcbout'length, enable => enable, hzsup => hzsup)
port map (Pcbout, Pcben, Pcbin, Ccbout, Ccben, Ccbin,
chain_tck, chain_tckn, sr2_tdi, sr2a_tdi,
bsshft, bscapt, bsupdi, bsupdo, bsdrive, bshighz);
sr3a: bscanregs
generic map (tech => tech, nsigs => sr3i'length-30, dirmask => 2#11_11111111_10#, enable => enable)
port map (sr3i(sr3i'high downto 30), sr3o(sr3i'high downto 30), chain_tck, chain_tckn, sr3a_tdi, sr2_tdi,
bsshft, bscapt, bsupdi, bsupdo, bsdrive, bshighz);
sr3b: bscanregs
generic map (tech => tech, nsigs => 30, dirmask => 2#001101_01111111_11111111_11111001#, enable => enable)
port map (sr3i(29 downto 0), sr3o(29 downto 0), chain_tck, chain_tckn, sr3_tdi, sr3a_tdi,
bsshft, bscapt, bsupdi, bsupdo, bsdrive, bshighz);
sr3i(41 downto 30) <= Csdclk & Csdcsn & Csdwen & Csdrasn & Csdcasn &
Csddqm & Cdsutx & Pdsurx;
sr3i(29 downto 23) <= Pdsuen & Pdsubre & Cdsuact & Ctxd1 & Prxd1 & Ctxd2 & Prxd2;
sr3i(22 downto 9) <= Cramsn & Cramoen & Crwen;
sr3i(8 downto 0) <= Coen & Cwriten & Cread & Ciosn & Cromsn(1 downto 0) & Pbrdyn & Pbexcn & Cwdogn;
Psdclk <= sr3o(41); Psdcsn <= sr3o(40 downto 39); Psdwen <= sr3o(38);
Psdrasn <= sr3o(37); Psdcasn <= sr3o(36); Psddqm <= sr3o(35 downto 32);
Pdsutx <= sr3o(31); Cdsurx <= sr3o(30); Cdsuen <= sr3o(29);
Cdsubre <= sr3o(28); Pdsuact <= sr3o(27); Ptxd1 <= sr3o(26);
Crxd1 <= sr3o(25); Ptxd2 <= sr3o(24); Crxd2 <= sr3o(23);
Pramsn <= sr3o(22 downto 18); Pramoen <= sr3o(17 downto 13); Prwen <= sr3o(12 downto 9);
Poen <= sr3o(8); Pwriten <= sr3o(7); Pread <= sr3o(6);
Piosn <= sr3o(5); Promsn <= sr3o(4 downto 3); Cbrdyn <= sr3o(2);
Cbexcn <= sr3o(1); Pwdogn <= sr3o(0);
sr4: bscanregsbd
generic map (tech => tech, nsigs => Pgpioin'length, enable => enable, hzsup => hzsup)
port map (Pgpioout, Pgpioen, Pgpioin, Cgpioout, Cgpioen, Cgpioin,
chain_tck, chain_tckn, sr4_tdi, sr3_tdi,
bsshft, bscapt, bsupdi, bsupdo, bsdrive, bshighz);
sr5: bscanregs
generic map (tech => tech, nsigs => sr5i'length, dirmask => 2#00000011_10010101#, enable => enable)
port map (sr5i, sr5o, chain_tck, chain_tckn, chain_tdi, sr4_tdi,
bsshft, bscapt, bsupdi, bsupdo, bsdrive, bshighz);
sr5i <= Pprom32 & Ppromedac & Pspw_clksel & Pspw_clk & Pspw_rxd & Pspw_rxs &
Cspw_txd & Cspw_txs & Cspw_ten & Plclk2x & Plclk4x &
Clclkdis & Plclklock & Clock & Proen & Croout;
Cprom32 <= sr5o(11+5*CFG_SPW_NUM);
Cpromedac <= sr5o(10+5*CFG_SPW_NUM);
Cspw_clksel <= sr5o(9+5*CFG_SPW_NUM downto 8+5*CFG_SPW_NUM);
Cspw_clk <= sr5o(7+5*CFG_SPW_NUM);
Cspw_rxd <= sr5o(6+5*CFG_SPW_NUM downto 7+4*CFG_SPW_NUM);
Cspw_rxs <= sr5o(6+4*CFG_SPW_NUM downto 7+3*CFG_SPW_NUM);
Pspw_txd <= sr5o(6+3*CFG_SPW_NUM downto 7+2*CFG_SPW_NUM);
Pspw_txs <= sr5o(6+2*CFG_SPW_NUM downto 7+CFG_SPW_NUM);
Pspw_ten <= sr5o(6+CFG_SPW_NUM downto 7);
Clclk2x <= sr5o(6);
Clclk4x <= sr5o(5);
Plclkdis <= sr5o(4);
Clclklock <= sr5o(3);
Plock <= sr5o(2);
Croen <= sr5o(1);
Proout <= sr5o(0);
end;
| gpl-3.0 | 3c4fb25a72269b73c361da3d4c078415 | 0.585794 | 3.04768 | false | false | false | false |
EliasLuiz/TCC | Leon3/lib/gaisler/sim/sram16.vhd | 1 | 2,410 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: sram16
-- File: sram16.vhd
-- Author: Jiri Gaisler Gaisler Research
-- Description: Simulation model of generic 16-bit async SRAM
------------------------------------------------------------------------------
-- pragma translate_off
library ieee;
use ieee.std_logic_1164.all;
use std.textio.all;
library gaisler;
use gaisler.sim.all;
library grlib;
use grlib.stdlib.all;
entity sram16 is
generic (
index : integer := 0; -- Byte lane (0 - 3)
abits: Positive := 10; -- Default 10 address bits (1 Kbyte)
echk : integer := 0; -- Generate EDAC checksum
tacc : integer := 10; -- access time (ns)
fname : string := "ram.dat"; -- File to read from
clear : integer := 0); -- clear memory
port (
a : in std_logic_vector(abits-1 downto 0);
d : inout std_logic_vector(15 downto 0);
lb : in std_logic;
ub : in std_logic;
ce : in std_logic;
we : in std_ulogic;
oe : in std_ulogic);
end;
architecture sim of sram16 is
signal cex : std_logic_vector(0 to 1);
begin
cex(0) <= ce or lb; cex(1) <= ce or ub;
sr0 : sram generic map (index+1, abits, tacc, fname, clear)
port map (a, d(7 downto 0), cex(0), we, oe);
sr1 : sram generic map (index, abits, tacc, fname, clear)
port map (a, d(15 downto 8), cex(1), we, oe);
end sim;
-- pragma translate_on
| gpl-3.0 | 75bc4b2976a7a88b056c9dca9c9af715 | 0.607054 | 3.724884 | false | false | false | false |
EliasLuiz/TCC | Leon3/lib/gaisler/srmmu/mmu.vhd | 1 | 21,306 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: MMU
-- File: mmu.vhd
-- Author: Konrad Eisele, Jiri Gaisler, Gaisler Research
-- Description: Leon3 MMU top level entity
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.config_types.all;
use grlib.config.all;
use grlib.stdlib.all;
library techmap;
use techmap.gencomp.all;
library gaisler;
use gaisler.mmuconfig.all;
use gaisler.mmuiface.all;
use gaisler.libmmu.all;
entity mmu is
generic (
tech : integer range 0 to NTECH := 0;
itlbnum : integer range 2 to 64 := 8;
dtlbnum : integer range 2 to 64 := 8;
tlb_type : integer range 0 to 3 := 1;
tlb_rep : integer range 0 to 1 := 0;
mmupgsz : integer range 0 to 5 := 0;
scantest : integer := 0;
ramcbits : integer := 1
);
port (
rst : in std_logic;
clk : in std_logic;
mmudci : in mmudc_in_type;
mmudco : out mmudc_out_type;
mmuici : in mmuic_in_type;
mmuico : out mmuic_out_type;
mcmmo : in memory_mm_out_type;
mcmmi : out memory_mm_in_type;
testin : in std_logic_vector(TESTIN_WIDTH-1 downto 0)
);
end mmu;
architecture rtl of mmu is
constant MMUCTX_BITS : integer := M_CTX_SZ;
constant M_TLB_TYPE : integer range 0 to 1 := conv_integer(conv_std_logic_vector(tlb_type,2) and conv_std_logic_vector(1,2)); -- eather split or combined
constant M_TLB_FASTWRITE : integer range 0 to 3 := conv_integer(conv_std_logic_vector(tlb_type,2) and conv_std_logic_vector(2,2)); -- fast writebuffer
constant M_ENT_I : integer range 2 to 64 := itlbnum; -- icache tlb entries: number
constant M_ENT_ILOG : integer := log2(M_ENT_I); -- icache tlb entries: address bits
constant M_ENT_D : integer range 2 to 64 := dtlbnum; -- dcache tlb entries: number
constant M_ENT_DLOG : integer := log2(M_ENT_D); -- dcache tlb entries: address bits
constant M_ENT_C : integer range 2 to 64 := M_ENT_I; -- i/dcache tlb entries: number
constant M_ENT_CLOG : integer := M_ENT_ILOG; -- i/dcache tlb entries: address bits
type mmu_op is record
trans_op : std_logic;
flush_op : std_logic;
diag_op : std_logic;
end record;
constant mmu_op_none : mmu_op := ('0', '0', '0');
type mmu_cmbpctrl is record
tlbowner : mmu_idcache;
tlbactive : std_logic;
op : mmu_op;
end record;
constant mmu_cmbpctrl_none : mmu_cmbpctrl := (id_icache, '0', mmu_op_none);
type mmu_rtype is record
cmb_s1 : mmu_cmbpctrl;
cmb_s2 : mmu_cmbpctrl;
splt_is1 : mmu_cmbpctrl;
splt_is2 : mmu_cmbpctrl;
splt_ds1 : mmu_cmbpctrl;
splt_ds2 : mmu_cmbpctrl;
twactive : std_logic; -- split tlb
twowner : mmu_idcache; -- split tlb
flush : std_logic;
mmctrl2 : mmctrl_type2;
end record;
constant RESET_ALL : boolean := GRLIB_CONFIG_ARRAY(grlib_sync_reset_enable_all) = 1;
constant ASYNC_RESET : boolean := GRLIB_CONFIG_ARRAY(grlib_async_reset_enable) = 1;
constant RRES : mmu_rtype := (
cmb_s1 => mmu_cmbpctrl_none,
cmb_s2 => mmu_cmbpctrl_none,
splt_is1 => mmu_cmbpctrl_none,
splt_is2 => mmu_cmbpctrl_none,
splt_ds1 => mmu_cmbpctrl_none,
splt_ds2 => mmu_cmbpctrl_none,
twactive => '0',
twowner => id_icache,
flush => '0',
mmctrl2 => mmctrl2_zero);
signal r, c : mmu_rtype;
-- tlb
component mmutlb
generic (
tech : integer range 0 to NTECH := 0;
entries : integer range 2 to 64 := 8;
tlb_type : integer range 0 to 3 := 1;
tlb_rep : integer range 0 to 1 := 0;
mmupgsz : integer range 0 to 5 := 0;
scantest : integer := 0;
ramcbits : integer := 1
);
port (
rst : in std_logic;
clk : in std_logic;
tlbi : in mmutlb_in_type;
tlbo : out mmutlb_out_type;
two : in mmutw_out_type;
twi : out mmutw_in_type;
testin : in std_logic_vector(TESTIN_WIDTH-1 downto 0)
);
end component;
signal tlbi_a0 : mmutlb_in_type;
signal tlbi_a1 : mmutlb_in_type;
signal tlbo_a0 : mmutlb_out_type;
signal tlbo_a1 : mmutlb_out_type;
signal twi_a : mmutwi_a(1 downto 0);
signal two_a : mmutwo_a(1 downto 0);
-- table walk
component mmutw
generic (
mmupgsz : integer range 0 to 5 := 0
);
port (
rst : in std_logic;
clk : in std_logic;
mmctrl1 : in mmctrl_type1;
twi : in mmutw_in_type;
two : out mmutw_out_type;
mcmmo : in memory_mm_out_type;
mcmmi : out memory_mm_in_type
);
end component;
signal twi : mmutw_in_type;
signal two : mmutw_out_type;
signal mmctrl1 : mmctrl_type1;
begin
syncrregs : if not ASYNC_RESET generate
p1: process (clk)
begin
if rising_edge(clk) then
r <= c;
if RESET_ALL and (rst = '0') then
r <= RRES;
end if;
end if;
end process p1;
end generate;
asyncrregs : if ASYNC_RESET generate
p1: process (clk, rst)
begin
if rst = '0' then
r <= RRES;
elsif rising_edge(clk) then
r <= c;
end if;
end process p1;
end generate;
p0: process (rst, r, mmudci, mmuici, mcmmo, tlbo_a0, tlbo_a1, tlbi_a0, tlbi_a1, two_a, twi_a, two)
variable cmbtlbin : mmuidc_data_in_type;
variable cmbtlbout : mmutlb_out_type;
variable spltitlbin : mmuidc_data_in_type;
variable spltdtlbin : mmuidc_data_in_type;
variable spltitlbout : mmutlb_out_type;
variable spltdtlbout : mmutlb_out_type;
variable mmuico_transdata : mmuidc_data_out_type;
variable mmudco_transdata : mmuidc_data_out_type;
variable mmuico_grant : std_logic;
variable mmudco_grant : std_logic;
variable v : mmu_rtype;
variable twiv : mmutw_in_type;
variable twod, twoi : mmutw_out_type;
variable fault : mmutlbfault_out_type;
variable wbtransdata : mmuidc_data_out_type;
variable fs : mmctrl_fs_type;
variable fa : std_logic_vector(VA_I_SZ-1 downto 0);
begin
v := r;
wbtransdata.finish := '0';
wbtransdata.data := (others => '0');
wbtransdata.cache := '0';
wbtransdata.accexc := '0';
if (M_TLB_TYPE = 0) and (M_TLB_FASTWRITE /= 0) then
wbtransdata := tlbo_a1.wbtransdata;
end if;
cmbtlbin.data := (others => '0');
cmbtlbin.su := '0';
cmbtlbin.read := '0';
cmbtlbin.isid := id_dcache;
cmbtlbout.transdata.finish := '0';
cmbtlbout.transdata.data := (others => '0');
cmbtlbout.transdata.cache := '0';
cmbtlbout.transdata.accexc := '0';
cmbtlbout.fault.fault_pro := '0';
cmbtlbout.fault.fault_pri := '0';
cmbtlbout.fault.fault_access := '0';
cmbtlbout.fault.fault_mexc := '0';
cmbtlbout.fault.fault_trans := '0';
cmbtlbout.fault.fault_inv := '0';
cmbtlbout.fault.fault_lvl := (others => '0');
cmbtlbout.fault.fault_su := '0';
cmbtlbout.fault.fault_read := '0';
cmbtlbout.fault.fault_isid := id_dcache;
cmbtlbout.fault.fault_addr := (others => '0');
cmbtlbout.nexttrans := '0';
cmbtlbout.s1finished := '0';
mmuico_transdata.finish := '0';
mmuico_transdata.data := (others => '0');
mmuico_transdata.cache := '0';
mmuico_transdata.accexc := '0';
mmudco_transdata.finish := '0';
mmudco_transdata.data := (others => '0');
mmudco_transdata.cache := '0';
mmudco_transdata.accexc := '0';
mmuico_grant := '0';
mmudco_grant := '0';
twiv.walk_op_ur := '0';
twiv.areq_ur := '0';
twiv.data := (others => '0');
twiv.adata := (others => '0');
twiv.aaddr := (others => '0');
twod.finish := '0';
twod.data := (others => '0');
twod.addr := (others => '0');
twod.lvl := (others => '0');
twod.fault_mexc := '0';
twod.fault_trans := '0';
twod.fault_inv := '0';
twod.fault_lvl := (others => '0');
twoi.finish := '0';
twoi.data := (others => '0');
twoi.addr := (others => '0');
twoi.lvl := (others => '0');
twoi.fault_mexc := '0';
twoi.fault_trans := '0';
twoi.fault_inv := '0';
twoi.fault_lvl := (others => '0');
fault.fault_pro := '0';
fault.fault_pri := '0';
fault.fault_access := '0';
fault.fault_mexc := '0';
fault.fault_trans := '0';
fault.fault_inv := '0';
fault.fault_lvl := (others => '0');
fault.fault_su := '0';
fault.fault_read := '0';
fault.fault_isid := id_dcache;
fault.fault_addr := (others => '0');
fs.ow := '0';
fs.fav := '0';
fs.ft := (others => '0');
fs.at_ls := '0';
fs.at_id := '0';
fs.at_su := '0';
fs.l := (others => '0');
fs.ebe := (others => '0');
fa := (others => '0');
if M_TLB_TYPE = 0 then
spltitlbout := tlbo_a0;
spltdtlbout := tlbo_a1;
twod := two; twoi := two;
twod.finish := '0'; twoi.finish := '0';
spltdtlbin := mmudci.transdata;
spltitlbin := mmuici.transdata;
mmudco_transdata := spltdtlbout.transdata;
mmuico_transdata := spltitlbout.transdata;
-- d-tlb
if ((not r.splt_ds1.tlbactive) or spltdtlbout.s1finished) = '1' then
v.splt_ds1.tlbactive := '0';
v.splt_ds1.op.trans_op := '0';
v.splt_ds1.op.flush_op := '0';
if mmudci.trans_op = '1' then
mmudco_grant := '1';
v.splt_ds1.tlbactive := '1';
v.splt_ds1.op.trans_op := '1';
elsif mmudci.flush_op = '1' then
v.flush := '1';
mmudco_grant := '1';
v.splt_ds1.tlbactive := '1';
v.splt_ds1.op.flush_op := '1';
end if;
end if;
-- i-tlb
if ((not r.splt_is1.tlbactive) or spltitlbout.s1finished) = '1' then
v.splt_is1.tlbactive := '0';
v.splt_is1.op.trans_op := '0';
v.splt_is1.op.flush_op := '0';
if v.flush = '1' then
v.flush := '0';
v.splt_is1.tlbactive := '1';
v.splt_is1.op.flush_op := '1';
elsif mmuici.trans_op = '1' then
mmuico_grant := '1';
v.splt_is1.tlbactive := '1';
v.splt_is1.op.trans_op := '1';
end if;
end if;
if spltitlbout.transdata.finish = '1' and (r.splt_is2.op.flush_op = '0') then
fault := spltitlbout.fault;
end if;
if spltdtlbout.transdata.finish = '1' and (r.splt_is2.op.flush_op = '0') then
if (spltdtlbout.fault.fault_mexc or
spltdtlbout.fault.fault_trans or
spltdtlbout.fault.fault_inv or
spltdtlbout.fault.fault_pro or
spltdtlbout.fault.fault_pri or
spltdtlbout.fault.fault_access) = '1' then
fault := spltdtlbout.fault; -- overwrite icache fault
end if;
end if;
if spltitlbout.s1finished = '1' then
v.splt_is2 := r.splt_is1;
end if;
if spltdtlbout.s1finished = '1' then
v.splt_ds2 := r.splt_ds1;
end if;
if ( r.splt_is2.op.flush_op ) = '1' then
mmuico_transdata.finish := '0';
end if;
-- share tw
if two.finish = '1' then
v.twactive := '0';
end if;
if r.twowner = id_icache then
twiv := twi_a(0);
twoi.finish := two.finish;
else
twiv := twi_a(1);
twod.finish := two.finish;
end if;
if (v.twactive) = '0' then
if (twi_a(1).areq_ur or twi_a(1).walk_op_ur) = '1' then
v.twactive := '1';
v.twowner := id_dcache;
elsif (twi_a(0).areq_ur or twi_a(0).walk_op_ur) = '1' then
v.twactive := '1';
v.twowner := id_icache;
end if;
end if;
else
--# combined i/d cache: 1 tlb, 1 tw
-- share one tlb among i and d cache
cmbtlbout := tlbo_a0;
mmuico_grant := '0'; mmudco_grant := '0';
mmuico_transdata.finish := '0'; mmudco_transdata.finish := '0';
twiv := twi_a(0);
twod := two; twoi := two;
twod.finish := '0'; twoi.finish := '0';
-- twod.finish := two.finish;
twoi.finish := two.finish;
if ((not v.cmb_s1.tlbactive) or cmbtlbout.s1finished) = '1' then
v.cmb_s1.tlbactive := '0';
v.cmb_s1.op.trans_op := '0';
v.cmb_s1.op.flush_op := '0';
if (mmudci.trans_op or mmudci.flush_op or mmuici.trans_op) = '1' then
v.cmb_s1.tlbactive := '1';
end if;
if mmuici.trans_op = '1' then
mmuico_grant := '1';
v.cmb_s1.tlbowner := id_icache;
v.cmb_s1.op.trans_op := '1';
elsif mmudci.trans_op = '1' then
mmudco_grant := '1';
v.cmb_s1.tlbowner := id_dcache;
v.cmb_s1.op.trans_op := '1';
elsif mmudci.flush_op = '1' then
mmudco_grant := '1';
v.cmb_s1.tlbowner := id_dcache;
v.cmb_s1.op.flush_op := '1';
end if;
end if;
if (r.cmb_s1.tlbactive and not r.cmb_s2.tlbactive) = '1' then
end if;
if cmbtlbout.s1finished = '1' then
v.cmb_s2 := r.cmb_s1;
end if;
if r.cmb_s1.tlbowner = id_dcache then
cmbtlbin := mmudci.transdata;
else
cmbtlbin := mmuici.transdata;
end if;
if r.cmb_s2.tlbowner = id_dcache then
mmudco_transdata := cmbtlbout.transdata;
else
mmuico_transdata := cmbtlbout.transdata;
end if;
if cmbtlbout.transdata.finish = '1' and (r.cmb_s2.op.flush_op = '0') then
fault := cmbtlbout.fault;
end if;
end if;
-- # fault status register
if (mmudci.fsread) = '1' then
v.mmctrl2.valid := '0'; v.mmctrl2.fs.fav := '0';
end if;
-- SRMMU Fault Priorities
-- Pri Error
-------------------------
-- 1 Internal error
-- 2 Translation error
-- 3 Invalid address error
-- 4 Privilege violation error
-- 5 Protection error
-- 6 Access bus error
if (fault.fault_mexc) = '1' then
fs.ft := FS_FT_TRANS;
elsif (fault.fault_trans) = '1' then
fs.ft := FS_FT_TRANS;
elsif (fault.fault_inv) = '1' then
fs.ft := FS_FT_INV;
elsif (fault.fault_pri) = '1' then
fs.ft := FS_FT_PRI;
elsif (fault.fault_pro) = '1' then
fs.ft := FS_FT_PRO;
elsif (fault.fault_access) = '1' then
fs.ft := FS_FT_BUS;
else
fs.ft := FS_FT_NONE;
end if;
fs.ow := '0';
fs.l := fault.fault_lvl;
if fault.fault_isid = id_dcache then
fs.at_id := '0';
else
fs.at_id := '1';
end if;
fs.at_su := fault.fault_su;
fs.at_ls := not fault.fault_read;
fs.fav := '1';
fs.ebe := (others => '0');
fa := fault.fault_addr(VA_I_U downto VA_I_D);
if (fault.fault_mexc or
fault.fault_trans or
fault.fault_inv or
fault.fault_pro or
fault.fault_pri or
fault.fault_access) = '1' then
--# priority
--
if v.mmctrl2.valid = '1'then
if (fault.fault_mexc) = '1' then
v.mmctrl2.fs := fs;
v.mmctrl2.fa := fa;
else
-- An instruction or data access fault may not overwrite a
-- translation table access fault.
if (r.mmctrl2.fs.ft /= FS_FT_TRANS) then
if fault.fault_isid = id_dcache then
-- dcache, overwrite bit is cleared
v.mmctrl2.fs := fs;
v.mmctrl2.fa := fa;
else
-- icache
-- an inst access fault may not overwrite a data access fault:
if (not r.mmctrl2.fs.at_id) = '0' then
fs.ow := '1';
v.mmctrl2.fs := fs;
v.mmctrl2.fa := fa;
end if;
end if;
end if;
end if;
else
v.mmctrl2.fs := fs;
v.mmctrl2.fa := fa;
v.mmctrl2.valid := '1';
end if;
if (fault.fault_isid) = id_dcache then
mmudco_transdata.accexc := '1';
else
mmuico_transdata.accexc := '1';
end if;
end if;
-- # reset
if (not ASYNC_RESET) and ( not RESET_ALL ) and ( rst = '0' ) then
if M_TLB_TYPE = 0 then
v.splt_is1.tlbactive := RRES.splt_is1.tlbactive;
v.splt_is2.tlbactive := RRES.splt_is2.tlbactive;
v.splt_ds1.tlbactive := RRES.splt_ds1.tlbactive;
v.splt_ds2.tlbactive := RRES.splt_ds2.tlbactive;
v.splt_is1.op.trans_op := RRES.splt_is1.op.trans_op;
v.splt_is2.op.trans_op := RRES.splt_is2.op.trans_op;
v.splt_ds1.op.trans_op := RRES.splt_ds1.op.trans_op;
v.splt_ds2.op.trans_op := RRES.splt_ds2.op.trans_op;
v.splt_is1.op.flush_op := RRES.splt_is1.op.flush_op;
v.splt_is2.op.flush_op := RRES.splt_is2.op.flush_op;
v.splt_ds1.op.flush_op := RRES.splt_ds1.op.flush_op;
v.splt_ds2.op.flush_op := RRES.splt_ds2.op.flush_op;
else
v.cmb_s1.tlbactive := RRES.cmb_s1.tlbactive;
v.cmb_s2.tlbactive := RRES.cmb_s2.tlbactive;
v.cmb_s1.op.trans_op := RRES.cmb_s1.op.trans_op;
v.cmb_s2.op.trans_op := RRES.cmb_s2.op.trans_op;
v.cmb_s1.op.flush_op := RRES.cmb_s1.op.flush_op;
v.cmb_s2.op.flush_op := RRES.cmb_s2.op.flush_op;
end if;
v.flush := RRES.flush;
v.mmctrl2.valid := RRES.mmctrl2.valid;
v.twactive := RRES.twactive;
v.twowner := RRES.twowner;
end if;
-- drive signals
if M_TLB_TYPE = 0 then
tlbi_a0.trans_op <= r.splt_is1.op.trans_op;
tlbi_a0.flush_op <= r.splt_is1.op.flush_op;
tlbi_a0.transdata <= spltitlbin;
tlbi_a0.s2valid <= r.splt_is2.tlbactive;
tlbi_a0.mmctrl1 <= mmudci.mmctrl1;
tlbi_a0.wb_op <= '0';
tlbi_a1.trans_op <= r.splt_ds1.op.trans_op;
tlbi_a1.flush_op <= r.splt_ds1.op.flush_op;
tlbi_a1.transdata <= spltdtlbin;
tlbi_a1.s2valid <= r.splt_ds2.tlbactive;
tlbi_a1.mmctrl1 <= mmudci.mmctrl1;
tlbi_a1.wb_op <= mmudci.wb_op;
else
tlbi_a0.trans_op <= r.cmb_s1.op.trans_op;
tlbi_a0.flush_op <= r.cmb_s1.op.flush_op;
tlbi_a0.transdata <= cmbtlbin;
tlbi_a0.s2valid <= r.cmb_s2.tlbactive;
tlbi_a0.mmctrl1 <= mmudci.mmctrl1;
tlbi_a0.wb_op <= '0';
end if;
mmudco.transdata <= mmudco_transdata;
mmuico.transdata <= mmuico_transdata;
mmudco.grant <= mmudco_grant;
mmuico.grant <= mmuico_grant;
mmuico.tlbmiss <= twi_a(0).tlbmiss;
mmudco.mmctrl2 <= r.mmctrl2;
mmudco.wbtransdata <= wbtransdata;
twi <= twiv;
two_a(0) <= twoi;
two_a(1) <= twod;
mmctrl1 <= mmudci.mmctrl1;
c <= v;
end process p0;
tlbcomb0: if M_TLB_TYPE = 1 generate
-- i/d tlb
ctlb0 : mmutlb
generic map ( tech, M_ENT_C, 0, tlb_rep, mmupgsz, scantest, ramcbits )
port map (rst, clk, tlbi_a0, tlbo_a0, two_a(0), twi_a(0), testin
);
mmudco.tlbmiss <= twi_a(0).tlbmiss;
end generate tlbcomb0;
tlbsplit0: if M_TLB_TYPE = 0 generate
-- i tlb
itlb0 : mmutlb
generic map ( tech, M_ENT_I, 0, tlb_rep, mmupgsz, scantest, ramcbits )
port map (rst, clk, tlbi_a0, tlbo_a0, two_a(0), twi_a(0), testin
);
-- d tlb
dtlb0 : mmutlb
generic map ( tech, M_ENT_D, tlb_type, tlb_rep, mmupgsz, scantest, ramcbits )
port map (rst, clk, tlbi_a1, tlbo_a1, two_a(1), twi_a(1), testin
);
mmudco.tlbmiss <= twi_a(1).tlbmiss;
end generate tlbsplit0;
-- table walk component
tw0 : mmutw
generic map ( mmupgsz )
port map (rst, clk, mmctrl1, twi, two, mcmmo, mcmmi);
-- pragma translate_off
chk : process
begin
assert not ((M_TLB_TYPE = 1) and (M_TLB_FASTWRITE /= 0)) report
"Fast writebuffer only supported for combined cache"
severity failure;
wait;
end process;
-- pragma translate_on
end rtl;
| gpl-3.0 | 7e9ec4359afd6c2c38f53eb1708cb552 | 0.547733 | 3.230139 | false | false | false | false |
EliasLuiz/TCC | Leon3/designs/leon3-xilinx-ac701/testbench.vhd | 1 | 18,784 | -----------------------------------------------------------------------------
-- LEON3 Demonstration design test bench
-- Copyright (C) 2013 Gaisler Research
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library gaisler;
use gaisler.libdcom.all;
use gaisler.sim.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
library techmap;
use techmap.gencomp.all;
use work.debug.all;
use work.config.all;
entity testbench is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
clktech : integer := CFG_CLKTECH;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW;
USE_MIG_INTERFACE_MODEL : boolean := false
);
end;
architecture behav of testbench is
-- DDR3 Simulation parameters
constant SIM_BYPASS_INIT_CAL : string := "FAST";
-- # = "OFF" - Complete memory init &
-- calibration sequence
-- # = "SKIP" - Not supported
-- # = "FAST" - Complete memory init & use
-- abbreviated calib sequence
constant SIMULATION : string := "TRUE";
-- Should be TRUE during design simulations and
-- FALSE during implementations
constant promfile : string := "prom.srec"; -- rom contents
constant ramfile : string := "ram.srec"; -- ram contents
signal clk : std_logic := '0';
signal Rst : std_logic := '0';
signal GND : std_ulogic := '0';
signal VCC : std_ulogic := '1';
signal NC : std_ulogic := 'Z';
signal txd1 , rxd1 , dsurx : std_logic;
signal txd2 , rxd2 , dsutx : std_logic;
signal ctsn1 , rtsn1 , dsuctsn : std_ulogic;
signal ctsn2 , rtsn2 , dsurtsn : std_ulogic;
signal phy_gtxclk : std_logic := '0';
signal phy_txer : std_ulogic;
signal phy_txd : std_logic_vector(7 downto 0);
signal phy_txctl_txen : std_ulogic;
signal phy_txclk : std_ulogic;
signal phy_rxer : std_ulogic;
signal phy_rxd : std_logic_vector(7 downto 0);
signal phy_rxctl_rxdv : std_ulogic;
signal phy_rxclk : std_ulogic;
signal phy_reset : std_ulogic;
signal phy_mdio : std_logic;
signal phy_mdc : std_ulogic;
signal phy_crs : std_ulogic;
signal phy_col : std_ulogic;
signal phy_int : std_ulogic;
signal phy_rxdl : std_logic_vector(7 downto 0);
signal phy_txdl : std_logic_vector(7 downto 0);
signal clk27 : std_ulogic := '0';
signal clk200p : std_ulogic := '0';
signal clk200n : std_ulogic := '1';
signal clk33 : std_ulogic := '0';
signal clkethp : std_ulogic := '0';
signal clkethn : std_ulogic := '1';
signal txp1 : std_logic;
signal txn : std_logic;
signal rxp : std_logic := '1';
signal rxn : std_logic := '0';
signal iic_scl : std_ulogic;
signal iic_sda : std_ulogic;
signal ddc_scl : std_ulogic;
signal ddc_sda : std_ulogic;
signal dvi_iic_scl : std_logic;
signal dvi_iic_sda : std_logic;
signal tft_lcd_data : std_logic_vector(11 downto 0);
signal tft_lcd_clk_p : std_ulogic;
signal tft_lcd_clk_n : std_ulogic;
signal tft_lcd_hsync : std_ulogic;
signal tft_lcd_vsync : std_ulogic;
signal tft_lcd_de : std_ulogic;
signal tft_lcd_reset_b : std_ulogic;
-- DDR3 memory
signal ddr3_dq : std_logic_vector(63 downto 0);
signal ddr3_dqs_p : std_logic_vector(7 downto 0);
signal ddr3_dqs_n : std_logic_vector(7 downto 0);
signal ddr3_addr : std_logic_vector(13 downto 0);
signal ddr3_ba : std_logic_vector(2 downto 0);
signal ddr3_ras_n : std_logic;
signal ddr3_cas_n : std_logic;
signal ddr3_we_n : std_logic;
signal ddr3_reset_n : std_logic;
signal ddr3_ck_p : std_logic_vector(0 downto 0);
signal ddr3_ck_n : std_logic_vector(0 downto 0);
signal ddr3_cke : std_logic_vector(0 downto 0);
signal ddr3_cs_n : std_logic_vector(0 downto 0);
signal ddr3_dm : std_logic_vector(7 downto 0);
signal ddr3_odt : std_logic_vector(0 downto 0);
-- SPI flash
signal spi_sel_n : std_logic;
signal spi_clk : std_logic;
signal spi_miso : std_logic := '0';
signal spi_mosi : std_logic;
signal dsurst : std_ulogic;
signal errorn : std_logic;
signal switch : std_logic_vector(3 downto 0); -- I/O port
signal button : std_logic_vector(3 downto 0); -- I/O port
signal led : std_logic_vector(3 downto 0); -- I/O port
constant lresp : boolean := false;
signal tdqs_n : std_logic;
signal gmii_tx_clk : std_logic;
signal gmii_rx_clk : std_logic;
signal gmii_txd : std_logic_vector(7 downto 0);
signal gmii_tx_en : std_logic;
signal gmii_tx_er : std_logic;
signal gmii_rxd : std_logic_vector(7 downto 0);
signal gmii_rx_dv : std_logic;
signal gmii_rx_er : std_logic;
component leon3mp is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
clktech : integer := CFG_CLKTECH;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW;
SIM_BYPASS_INIT_CAL : string := "OFF";
SIMULATION : string := "FALSE";
USE_MIG_INTERFACE_MODEL : boolean := false
);
port (
reset : in std_ulogic;
clk200p : in std_ulogic; -- 200 MHz clock
clk200n : in std_ulogic; -- 200 MHz clock
spi_sel_n : inout std_ulogic;
spi_clk : out std_ulogic;
spi_miso : in std_ulogic;
spi_mosi : out std_ulogic;
ddr3_dq : inout std_logic_vector(63 downto 0);
ddr3_dqs_p : inout std_logic_vector(7 downto 0);
ddr3_dqs_n : inout std_logic_vector(7 downto 0);
ddr3_addr : out std_logic_vector(13 downto 0);
ddr3_ba : out std_logic_vector(2 downto 0);
ddr3_ras_n : out std_logic;
ddr3_cas_n : out std_logic;
ddr3_we_n : out std_logic;
ddr3_reset_n : out std_logic;
ddr3_ck_p : out std_logic_vector(0 downto 0);
ddr3_ck_n : out std_logic_vector(0 downto 0);
ddr3_cke : out std_logic_vector(0 downto 0);
ddr3_cs_n : out std_logic_vector(0 downto 0);
ddr3_dm : out std_logic_vector(7 downto 0);
ddr3_odt : out std_logic_vector(0 downto 0);
dsurx : in std_ulogic;
dsutx : out std_ulogic;
dsuctsn : in std_ulogic;
dsurtsn : out std_ulogic;
button : in std_logic_vector(3 downto 0);
switch : inout std_logic_vector(3 downto 0);
led : out std_logic_vector(3 downto 0);
iic_scl : inout std_ulogic;
iic_sda : inout std_ulogic;
gtrefclk_p : in std_logic;
gtrefclk_n : in std_logic;
phy_txclk : out std_logic;
phy_txd : out std_logic_vector(3 downto 0);
phy_txctl_txen : out std_ulogic;
phy_rxd : in std_logic_vector(3 downto 0);
phy_rxctl_rxdv : in std_ulogic;
phy_rxclk : in std_ulogic;
phy_reset : out std_ulogic;
phy_mdio : inout std_logic;
phy_mdc : out std_ulogic;
sfp_clock_mux : out std_logic_vector(1 downto 0);
sdcard_spi_miso : in std_logic;
sdcard_spi_mosi : out std_logic;
sdcard_spi_cs_b : out std_logic;
sdcard_spi_clk : out std_logic
);
end component;
begin
-- clock and reset
clk200p <= not clk200p after 2.5 ns;
clk200n <= not clk200n after 2.5 ns;
clkethp <= not clkethp after 4 ns;
clkethn <= not clkethp after 4 ns;
rst <= not dsurst;
rxd1 <= 'H'; ctsn1 <= '0';
rxd2 <= 'H'; ctsn2 <= '0';
button <= "0000";
switch(2 downto 0) <= "000";
cpu : leon3mp
generic map (
fabtech => fabtech,
memtech => memtech,
padtech => padtech,
clktech => clktech,
disas => disas,
dbguart => dbguart,
pclow => pclow,
SIM_BYPASS_INIT_CAL => SIM_BYPASS_INIT_CAL,
SIMULATION => SIMULATION,
USE_MIG_INTERFACE_MODEL => USE_MIG_INTERFACE_MODEL
)
port map (
reset => rst,
clk200p => clk200p,
clk200n => clk200n,
spi_sel_n => spi_sel_n,
spi_clk => spi_clk,
spi_miso => spi_miso,
spi_mosi => spi_mosi,
ddr3_dq => ddr3_dq,
ddr3_dqs_p => ddr3_dqs_p,
ddr3_dqs_n => ddr3_dqs_n,
ddr3_addr => ddr3_addr,
ddr3_ba => ddr3_ba,
ddr3_ras_n => ddr3_ras_n,
ddr3_cas_n => ddr3_cas_n,
ddr3_we_n => ddr3_we_n,
ddr3_reset_n => ddr3_reset_n,
ddr3_ck_p => ddr3_ck_p,
ddr3_ck_n => ddr3_ck_n,
ddr3_cke => ddr3_cke,
ddr3_cs_n => ddr3_cs_n,
ddr3_dm => ddr3_dm,
ddr3_odt => ddr3_odt,
dsurx => dsurx,
dsutx => dsutx,
dsuctsn => dsuctsn,
dsurtsn => dsurtsn,
button => button,
switch => switch,
led => led,
iic_scl => iic_scl,
iic_sda => iic_sda,
gtrefclk_p => clkethp,
gtrefclk_n => clkethn,
phy_txclk => phy_gtxclk,
phy_txd => phy_txd(3 downto 0),
phy_txctl_txen => phy_txctl_txen,
phy_rxd => phy_rxd(3 downto 0)'delayed(0 ns),
phy_rxctl_rxdv => phy_rxctl_rxdv'delayed(0 ns),
phy_rxclk => phy_rxclk'delayed(0 ns),
phy_reset => phy_reset,
phy_mdio => phy_mdio,
phy_mdc => phy_mdc,
sfp_clock_mux => OPEN ,
sdcard_spi_miso => '1',
sdcard_spi_mosi => OPEN ,
sdcard_spi_cs_b => OPEN ,
sdcard_spi_clk => OPEN
);
-- SPI memory model
spi_gen_model : if (CFG_SPIMCTRL = 1) generate
spi0 : spi_flash
generic map (
ftype => 3,
debug => 0,
readcmd => 16#0B#,
dummybyte => 0,
dualoutput => 0)
port map (
sck => spi_clk,
di => spi_mosi,
do => spi_miso,
csn => spi_sel_n,
sd_cmd_timeout => '0',
sd_data_timeout => '0');
end generate;
-- Memory Models instantiations
gen_mem_model : if (USE_MIG_INTERFACE_MODEL /= true) generate
ddr3mem : if (CFG_MIG_7SERIES = 1) generate
u1 : ddr3ram
generic map (
width => 64,
abits => 14,
colbits => 10,
rowbits => 10,
implbanks => 1,
fname => ramfile,
lddelay => (0 ns),
ldguard => 1,
speedbin => 9, --DDR3-1600K
density => 3,
pagesize => 1,
changeendian => 8)
port map (
ck => ddr3_ck_p(0),
ckn => ddr3_ck_n(0),
cke => ddr3_cke(0),
csn => ddr3_cs_n(0),
odt => ddr3_odt(0),
rasn => ddr3_ras_n,
casn => ddr3_cas_n,
wen => ddr3_we_n,
dm => ddr3_dm,
ba => ddr3_ba,
a => ddr3_addr,
resetn => ddr3_reset_n,
dq => ddr3_dq,
dqs => ddr3_dqs_p,
dqsn => ddr3_dqs_n,
doload => led(3)
);
end generate ddr3mem;
end generate gen_mem_model;
mig_mem_model : if (USE_MIG_INTERFACE_MODEL = true) generate
ddr3_dq <= (others => 'Z');
ddr3_dqs_p <= (others => 'Z');
ddr3_dqs_n <= (others => 'Z');
end generate mig_mem_model;
errorn <= led(1);
errorn <= 'H'; -- ERROR pull-up
phy0 : if (CFG_GRETH = 1) generate
phy_mdio <= 'H';
phy_int <= '0';
p0: phy
generic map (
address => 7,
extended_regs => 1,
aneg => 1,
base100_t4 => 1,
base100_x_fd => 1,
base100_x_hd => 1,
fd_10 => 1,
hd_10 => 1,
base100_t2_fd => 1,
base100_t2_hd => 1,
base1000_x_fd => 1,
base1000_x_hd => 1,
base1000_t_fd => 1,
base1000_t_hd => 1,
rmii => 0,
rgmii => 1
)
port map(phy_reset, phy_mdio, phy_txclk, phy_rxclk, phy_rxd,
phy_rxctl_rxdv, phy_rxer, phy_col, phy_crs, phy_txd,
phy_txctl_txen, phy_txer, phy_mdc, phy_gtxclk);
end generate;
iuerr : process
begin
wait for 210 us; -- This is for proper DDR3 behaviour durign init phase not needed durin simulation
if (USE_MIG_INTERFACE_MODEL /= true) then
wait on led(3); -- DDR3 Memory Init ready
end if;
wait for 5000 ns;
wait for 100 us;
if to_x01(errorn) = '1' then wait on errorn; end if;
assert (to_x01(errorn) = '1')
report "*** IU in error mode, simulation halted ***"
severity failure ; -- this should be a failure
end process;
--data <= buskeep(data) after 5 ns;
dsucom : process
procedure dsucfg(signal dsurx : in std_ulogic; signal dsutx : out std_ulogic) is
variable w32 : std_logic_vector(31 downto 0);
variable c8 : std_logic_vector(7 downto 0);
constant txp : time := 320 * 1 ns;
begin
dsutx <= '1';
dsurst <= '0';
switch(3) <= '0';
wait for 2500 ns;
wait for 210 us; -- This is for proper DDR3 behaviour durign init phase not needed durin simulation
dsurst <= '1';
switch(3) <= '1';
if (USE_MIG_INTERFACE_MODEL /= true) then
wait on led(3); -- Wait for DDR3 Memory Init ready
end if;
report "Start DSU transfer";
wait for 5000 ns;
txc(dsutx, 16#55#, txp); -- sync uart
-- Reads from memory and DSU register to mimic GRMON during simulation
l1 : loop
txc(dsutx, 16#80#, txp);
txa(dsutx, 16#40#, 16#00#, 16#00#, 16#04#, txp);
rxi(dsurx, w32, txp, lresp);
--report "DSU read memory " & tost(w32);
txc(dsutx, 16#80#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
rxi(dsurx, w32, txp, lresp);
--report "DSU Break and Single Step register" & tost(w32);
end loop l1;
wait;
-- ** This is only kept for reference --
-- do test read and writes to DDR3 to check status
-- Write
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#40#, 16#00#, 16#00#, 16#00#, txp);
txa(dsutx, 16#01#, 16#23#, 16#45#, 16#67#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#40#, 16#00#, 16#00#, 16#04#, txp);
txa(dsutx, 16#89#, 16#AB#, 16#CD#, 16#EF#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#40#, 16#00#, 16#00#, 16#08#, txp);
txa(dsutx, 16#08#, 16#19#, 16#2A#, 16#3B#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#40#, 16#00#, 16#00#, 16#0C#, txp);
txa(dsutx, 16#4C#, 16#5D#, 16#6E#, 16#7F#, txp);
txc(dsutx, 16#80#, txp);
txa(dsutx, 16#40#, 16#00#, 16#00#, 16#00#, txp);
rxi(dsurx, w32, txp, lresp);
txc(dsutx, 16#80#, txp);
txa(dsutx, 16#40#, 16#00#, 16#00#, 16#04#, txp);
rxi(dsurx, w32, txp, lresp);
report "* Read " & tost(w32);
txc(dsutx, 16#a0#, txp);
txa(dsutx, 16#40#, 16#00#, 16#00#, 16#08#, txp);
rxi(dsurx, w32, txp, lresp);
txc(dsutx, 16#a0#, txp);
txa(dsutx, 16#40#, 16#00#, 16#00#, 16#0C#, txp);
rxi(dsurx, w32, txp, lresp);
wait;
-- Register 0x90000000 (DSU Control Register)
-- Data 0x0000202e (b0010 0000 0010 1110)
-- [0] - Trace Enable
-- [1] - Break On Error
-- [2] - Break on IU watchpoint
-- [3] - Break on s/w break points
--
-- [4] - (Break on trap)
-- [5] - Break on error traps
-- [6] - Debug mode (Read mode only)
-- [7] - DSUEN (read mode)
--
-- [8] - DSUBRE (read mode)
-- [9] - Processor mode error (clears error)
-- [10] - processor halt (returns 1 if processor halted)
-- [11] - power down mode (return 1 if processor in power down mode)
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp);
txa(dsutx, 16#00#, 16#00#, 16#80#, 16#02#, txp);
wait;
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp);
txa(dsutx, 16#00#, 16#00#, 16#20#, 16#2e#, txp);
wait for 25000 ns;
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#01#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#40#, 16#00#, 16#24#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#0D#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#70#, 16#11#, 16#78#, txp);
txa(dsutx, 16#91#, 16#00#, 16#00#, 16#0D#, txp);
txa(dsutx, 16#90#, 16#40#, 16#00#, 16#44#, txp);
txa(dsutx, 16#00#, 16#00#, 16#20#, 16#00#, txp);
txc(dsutx, 16#80#, txp);
txa(dsutx, 16#90#, 16#40#, 16#00#, 16#44#, txp);
wait;
end;
begin
dsuctsn <= '0';
dsucfg(dsutx, dsurx);
wait;
end process;
end ;
| gpl-3.0 | 9dcb8b7f279efde29cb4924f381caa12 | 0.527896 | 3.30646 | false | false | false | false |
EliasLuiz/TCC | Leon3/designs/leon3-digilent-xup/config.vhd | 1 | 5,944 |
-----------------------------------------------------------------------------
-- LEON3 Demonstration design test bench configuration
-- Copyright (C) 2009 Aeroflex Gaisler
------------------------------------------------------------------------------
library techmap;
use techmap.gencomp.all;
package config is
-- Technology and synthesis options
constant CFG_FABTECH : integer := virtex2;
constant CFG_MEMTECH : integer := virtex2;
constant CFG_PADTECH : integer := virtex2;
constant CFG_TRANSTECH : integer := GTP0;
constant CFG_NOASYNC : integer := 0;
constant CFG_SCAN : integer := 0;
-- Clock generator
constant CFG_CLKTECH : integer := virtex2;
constant CFG_CLKMUL : integer := (13);
constant CFG_CLKDIV : integer := (20);
constant CFG_OCLKDIV : integer := 1;
constant CFG_OCLKBDIV : integer := 0;
constant CFG_OCLKCDIV : integer := 0;
constant CFG_PCIDLL : integer := 0;
constant CFG_PCISYSCLK: integer := 0;
constant CFG_CLK_NOFB : integer := 1;
-- LEON3 processor core
constant CFG_LEON3 : integer := 1;
constant CFG_NCPU : integer := (1);
constant CFG_NWIN : integer := (8);
constant CFG_V8 : integer := 2 + 4*0;
constant CFG_MAC : integer := 0;
constant CFG_BP : integer := 0;
constant CFG_SVT : integer := 1;
constant CFG_RSTADDR : integer := 16#00000#;
constant CFG_LDDEL : integer := (1);
constant CFG_NOTAG : integer := 0;
constant CFG_NWP : integer := (2);
constant CFG_PWD : integer := 0*2;
constant CFG_FPU : integer := 0 + 16*0 + 32*0;
constant CFG_GRFPUSH : integer := 0;
constant CFG_ICEN : integer := 1;
constant CFG_ISETS : integer := 2;
constant CFG_ISETSZ : integer := 8;
constant CFG_ILINE : integer := 8;
constant CFG_IREPL : integer := 0;
constant CFG_ILOCK : integer := 0;
constant CFG_ILRAMEN : integer := 0;
constant CFG_ILRAMADDR: integer := 16#8E#;
constant CFG_ILRAMSZ : integer := 1;
constant CFG_DCEN : integer := 1;
constant CFG_DSETS : integer := 2;
constant CFG_DSETSZ : integer := 4;
constant CFG_DLINE : integer := 8;
constant CFG_DREPL : integer := 0;
constant CFG_DLOCK : integer := 0;
constant CFG_DSNOOP : integer := 0 + 1*2 + 4*0;
constant CFG_DFIXED : integer := 16#0#;
constant CFG_DLRAMEN : integer := 0;
constant CFG_DLRAMADDR: integer := 16#8F#;
constant CFG_DLRAMSZ : integer := 1;
constant CFG_MMUEN : integer := 1;
constant CFG_ITLBNUM : integer := 8;
constant CFG_DTLBNUM : integer := 8;
constant CFG_TLB_TYPE : integer := 0 + 1*2;
constant CFG_TLB_REP : integer := 0;
constant CFG_MMU_PAGE : integer := 0;
constant CFG_DSU : integer := 1;
constant CFG_ITBSZ : integer := 2 + 64*0;
constant CFG_ATBSZ : integer := 2;
constant CFG_AHBPF : integer := 0;
constant CFG_LEON3FT_EN : integer := 0;
constant CFG_IUFT_EN : integer := 0;
constant CFG_FPUFT_EN : integer := 0;
constant CFG_RF_ERRINJ : integer := 0;
constant CFG_CACHE_FT_EN : integer := 0;
constant CFG_CACHE_ERRINJ : integer := 0;
constant CFG_LEON3_NETLIST: integer := 0;
constant CFG_DISAS : integer := 0 + 0;
constant CFG_PCLOW : integer := 2;
constant CFG_STAT_ENABLE : integer := 0;
constant CFG_STAT_CNT : integer := 1;
constant CFG_STAT_NMAX : integer := 0;
constant CFG_STAT_DSUEN : integer := 0;
constant CFG_NP_ASI : integer := 0;
constant CFG_WRPSR : integer := 0;
constant CFG_ALTWIN : integer := 0;
constant CFG_REX : integer := 0;
-- AMBA settings
constant CFG_DEFMST : integer := (0);
constant CFG_RROBIN : integer := 1;
constant CFG_SPLIT : integer := 1;
constant CFG_FPNPEN : integer := 0;
constant CFG_AHBIO : integer := 16#FFF#;
constant CFG_APBADDR : integer := 16#800#;
constant CFG_AHB_MON : integer := 0;
constant CFG_AHB_MONERR : integer := 0;
constant CFG_AHB_MONWAR : integer := 0;
constant CFG_AHB_DTRACE : integer := 0;
-- DSU UART
constant CFG_AHB_UART : integer := 1;
-- JTAG based DSU interface
constant CFG_AHB_JTAG : integer := 1;
-- Ethernet DSU
constant CFG_DSU_ETH : integer := 1 + 0 + 0;
constant CFG_ETH_BUF : integer := 2;
constant CFG_ETH_IPM : integer := 16#C0A8#;
constant CFG_ETH_IPL : integer := 16#0033#;
constant CFG_ETH_ENM : integer := 16#020000#;
constant CFG_ETH_ENL : integer := 16#000019#;
-- DDR controller
constant CFG_DDRSP : integer := 1;
constant CFG_DDRSP_INIT : integer := 1;
constant CFG_DDRSP_FREQ : integer := (90);
constant CFG_DDRSP_COL : integer := (9);
constant CFG_DDRSP_SIZE : integer := (256);
constant CFG_DDRSP_RSKEW : integer := (0);
-- AHB ROM
constant CFG_AHBROMEN : integer := 1;
constant CFG_AHBROPIP : integer := 1;
constant CFG_AHBRODDR : integer := 16#000#;
constant CFG_ROMADDR : integer := 16#100#;
constant CFG_ROMMASK : integer := 16#E00# + 16#100#;
-- AHB RAM
constant CFG_AHBRAMEN : integer := 0;
constant CFG_AHBRSZ : integer := 1;
constant CFG_AHBRADDR : integer := 16#A00#;
constant CFG_AHBRPIPE : integer := 0;
-- Gaisler Ethernet core
constant CFG_GRETH : integer := 1;
constant CFG_GRETH1G : integer := 0;
constant CFG_ETH_FIFO : integer := 32;
-- UART 1
constant CFG_UART1_ENABLE : integer := 1;
constant CFG_UART1_FIFO : integer := 8;
-- LEON3 interrupt controller
constant CFG_IRQ3_ENABLE : integer := 1;
constant CFG_IRQ3_NSEC : integer := 0;
-- Modular timer
constant CFG_GPT_ENABLE : integer := 1;
constant CFG_GPT_NTIM : integer := (2);
constant CFG_GPT_SW : integer := (8);
constant CFG_GPT_TW : integer := (32);
constant CFG_GPT_IRQ : integer := (8);
constant CFG_GPT_SEPIRQ : integer := 1;
constant CFG_GPT_WDOGEN : integer := 0;
constant CFG_GPT_WDOG : integer := 16#0#;
-- VGA and PS2/ interface
constant CFG_KBD_ENABLE : integer := 1;
constant CFG_VGA_ENABLE : integer := 0;
constant CFG_SVGA_ENABLE : integer := 1;
-- AMBA System ACE Interface Controller
constant CFG_GRACECTRL : integer := 1;
-- GRLIB debugging
constant CFG_DUART : integer := 0;
end;
| gpl-3.0 | c495403b6171b3dce76de7370762038c | 0.641992 | 3.631032 | false | false | false | false |
firecake/IRIS | FPGA/VHDL/ipcore_dir/Reset.vhd | 1 | 2,764 | --------------------------------------------------------------------------------
-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
--------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version : 14.7
-- \ \ Application : xaw2vhdl
-- / / Filename : Reset.vhd
-- /___/ /\ Timestamp : 05/27/2015 22:23:07
-- \ \ / \
-- \___\/\___\
--
--Command: xaw2vhdl-st C:\IRIS\ipcore_dir\.\Reset.xaw C:\IRIS\ipcore_dir\.\Reset
--Design Name: Reset
--Device: xc3s200a-4vq100
--
-- Module Reset
-- Generated by Xilinx Architecture Wizard
-- Written for synthesis tool: XST
library ieee;
use ieee.std_logic_1164.ALL;
use ieee.numeric_std.ALL;
library UNISIM;
use UNISIM.Vcomponents.ALL;
entity Reset is
port ( CLKIN_IN : in std_logic;
CLKIN_IBUFG_OUT : out std_logic;
CLK0_OUT : out std_logic;
LOCKED_OUT : out std_logic);
end Reset;
architecture BEHAVIORAL of Reset is
signal CLKFB_IN : std_logic;
signal CLKIN_IBUFG : std_logic;
signal CLK0_BUF : std_logic;
signal GND_BIT : std_logic;
begin
GND_BIT <= '0';
CLKIN_IBUFG_OUT <= CLKIN_IBUFG;
CLK0_OUT <= CLKFB_IN;
CLKIN_IBUFG_INST : IBUFG
port map (I=>CLKIN_IN,
O=>CLKIN_IBUFG);
CLK0_BUFG_INST : BUFG
port map (I=>CLK0_BUF,
O=>CLKFB_IN);
DCM_SP_INST : DCM_SP
generic map( CLK_FEEDBACK => "1X",
CLKDV_DIVIDE => 2.0,
CLKFX_DIVIDE => 1,
CLKFX_MULTIPLY => 4,
CLKIN_DIVIDE_BY_2 => FALSE,
CLKIN_PERIOD => 25.000,
CLKOUT_PHASE_SHIFT => "NONE",
DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS",
DFS_FREQUENCY_MODE => "LOW",
DLL_FREQUENCY_MODE => "LOW",
DUTY_CYCLE_CORRECTION => TRUE,
FACTORY_JF => x"C080",
PHASE_SHIFT => 0,
STARTUP_WAIT => FALSE)
port map (CLKFB=>CLKFB_IN,
CLKIN=>CLKIN_IBUFG,
DSSEN=>GND_BIT,
PSCLK=>GND_BIT,
PSEN=>GND_BIT,
PSINCDEC=>GND_BIT,
RST=>GND_BIT,
CLKDV=>open,
CLKFX=>open,
CLKFX180=>open,
CLK0=>CLK0_BUF,
CLK2X=>open,
CLK2X180=>open,
CLK90=>open,
CLK180=>open,
CLK270=>open,
LOCKED=>LOCKED_OUT,
PSDONE=>open,
STATUS=>open);
end BEHAVIORAL;
| gpl-3.0 | 46c92aa0f33c28d56b251937d6396fff | 0.442113 | 3.849582 | false | false | false | false |
EliasLuiz/TCC | Leon3/lib/grlib/sparc/sparc.vhd | 1 | 11,248 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- package: opcodes
-- File: opcodes.vhd
-- Author: Jiri Gaisler
-- Description: Instruction definitions according to the SPARC V8 manual.
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
package sparc is
-- op decoding (inst(31 downto 30))
subtype op_type is std_logic_vector(1 downto 0);
constant FMT2 : op_type := "00";
constant CALL : op_type := "01";
constant FMT3 : op_type := "10";
constant LDST : op_type := "11";
-- op2 decoding (inst(24 downto 22))
subtype op2_type is std_logic_vector(2 downto 0);
constant UNIMP : op2_type := "000";
constant BICC : op2_type := "010";
constant SETHI : op2_type := "100";
constant FBFCC : op2_type := "110";
constant CBCCC : op2_type := "111";
-- op3 decoding (inst(24 downto 19))
subtype op3_type is std_logic_vector(5 downto 0);
constant IADD : op3_type := "000000";
constant IAND : op3_type := "000001";
constant IOR : op3_type := "000010";
constant IXOR : op3_type := "000011";
constant ISUB : op3_type := "000100";
constant ANDN : op3_type := "000101";
constant ORN : op3_type := "000110";
constant IXNOR : op3_type := "000111";
constant ADDX : op3_type := "001000";
constant UMUL : op3_type := "001010";
constant SMUL : op3_type := "001011";
constant SUBX : op3_type := "001100";
constant UDIV : op3_type := "001110";
constant SDIV : op3_type := "001111";
constant ADDCC : op3_type := "010000";
constant ANDCC : op3_type := "010001";
constant ORCC : op3_type := "010010";
constant XORCC : op3_type := "010011";
constant SUBCC : op3_type := "010100";
constant ANDNCC : op3_type := "010101";
constant ORNCC : op3_type := "010110";
constant XNORCC : op3_type := "010111";
constant ADDXCC : op3_type := "011000";
constant UMULCC : op3_type := "011010";
constant SMULCC : op3_type := "011011";
constant SUBXCC : op3_type := "011100";
constant UDIVCC : op3_type := "011110";
constant SDIVCC : op3_type := "011111";
constant TADDCC : op3_type := "100000";
constant TSUBCC : op3_type := "100001";
constant TADDCCTV : op3_type := "100010";
constant TSUBCCTV : op3_type := "100011";
constant MULSCC : op3_type := "100100";
constant ISLL : op3_type := "100101";
constant ISRL : op3_type := "100110";
constant ISRA : op3_type := "100111";
constant RDY : op3_type := "101000";
constant RDPSR : op3_type := "101001";
constant RDWIM : op3_type := "101010";
constant RDTBR : op3_type := "101011";
constant WRY : op3_type := "110000";
constant WRPSR : op3_type := "110001";
constant WRWIM : op3_type := "110010";
constant WRTBR : op3_type := "110011";
constant FPOP1 : op3_type := "110100";
constant FPOP2 : op3_type := "110101";
constant CPOP1 : op3_type := "110110";
constant CPOP2 : op3_type := "110111";
constant JMPL : op3_type := "111000";
constant TICC : op3_type := "111010";
constant FLUSH : op3_type := "111011";
constant RETT : op3_type := "111001";
constant SAVE : op3_type := "111100";
constant RESTORE : op3_type := "111101";
constant UMAC : op3_type := "111110";
constant SMAC : op3_type := "111111";
constant LD : op3_type := "000000";
constant LDUB : op3_type := "000001";
constant LDUH : op3_type := "000010";
constant LDD : op3_type := "000011";
constant LDSB : op3_type := "001001";
constant LDSH : op3_type := "001010";
constant LDSTUB : op3_type := "001101";
constant SWAP : op3_type := "001111";
constant LDA : op3_type := "010000";
constant LDUBA : op3_type := "010001";
constant LDUHA : op3_type := "010010";
constant LDDA : op3_type := "010011";
constant LDSBA : op3_type := "011001";
constant LDSHA : op3_type := "011010";
constant LDSTUBA : op3_type := "011101";
constant SWAPA : op3_type := "011111";
constant LDF : op3_type := "100000";
constant LDFSR : op3_type := "100001";
constant LDDF : op3_type := "100011";
constant LDC : op3_type := "110000";
constant LDCSR : op3_type := "110001";
constant LDDC : op3_type := "110011";
constant ST : op3_type := "000100";
constant STB : op3_type := "000101";
constant STH : op3_type := "000110";
constant ISTD : op3_type := "000111";
constant STA : op3_type := "010100";
constant STBA : op3_type := "010101";
constant STHA : op3_type := "010110";
constant STDA : op3_type := "010111";
constant STF : op3_type := "100100";
constant STFSR : op3_type := "100101";
constant STDFQ : op3_type := "100110";
constant STDF : op3_type := "100111";
constant STC : op3_type := "110100";
constant STCSR : op3_type := "110101";
constant STDCQ : op3_type := "110110";
constant STDC : op3_type := "110111";
constant CASA : op3_type := "111100";
-- bicc decoding (inst(27 downto 25))
constant BA : std_logic_vector(3 downto 0) := "1000";
-- fpop1 decoding
subtype fpop_type is std_logic_vector(8 downto 0);
constant FITOS : fpop_type := "011000100";
constant FITOD : fpop_type := "011001000";
constant FITOQ : fpop_type := "011001100";
constant FSTOI : fpop_type := "011010001";
constant FDTOI : fpop_type := "011010010";
constant FQTOI : fpop_type := "011010011";
constant FSTOD : fpop_type := "011001001";
constant FSTOQ : fpop_type := "011001101";
constant FDTOS : fpop_type := "011000110";
constant FDTOQ : fpop_type := "011001110";
constant FQTOS : fpop_type := "011000111";
constant FQTOD : fpop_type := "011001011";
constant FMOVS : fpop_type := "000000001";
constant FNEGS : fpop_type := "000000101";
constant FABSS : fpop_type := "000001001";
constant FSQRTS : fpop_type := "000101001";
constant FSQRTD : fpop_type := "000101010";
constant FSQRTQ : fpop_type := "000101011";
constant FADDS : fpop_type := "001000001";
constant FADDD : fpop_type := "001000010";
constant FADDQ : fpop_type := "001000011";
constant FSUBS : fpop_type := "001000101";
constant FSUBD : fpop_type := "001000110";
constant FSUBQ : fpop_type := "001000111";
constant FMULS : fpop_type := "001001001";
constant FMULD : fpop_type := "001001010";
constant FMULQ : fpop_type := "001001011";
constant FSMULD : fpop_type := "001101001";
constant FDMULQ : fpop_type := "001101110";
constant FDIVS : fpop_type := "001001101";
constant FDIVD : fpop_type := "001001110";
constant FDIVQ : fpop_type := "001001111";
-- fpop2 decoding
constant FCMPS : fpop_type := "001010001";
constant FCMPD : fpop_type := "001010010";
constant FCMPQ : fpop_type := "001010011";
constant FCMPES : fpop_type := "001010101";
constant FCMPED : fpop_type := "001010110";
constant FCMPEQ : fpop_type := "001010111";
-- trap type decoding
subtype trap_type is std_logic_vector(5 downto 0);
constant TT_IAEX : trap_type := "000001";
constant TT_IINST : trap_type := "000010";
constant TT_PRIV : trap_type := "000011";
constant TT_FPDIS : trap_type := "000100";
constant TT_WINOF : trap_type := "000101";
constant TT_WINUF : trap_type := "000110";
constant TT_UNALA : trap_type := "000111";
constant TT_FPEXC : trap_type := "001000";
constant TT_DAEX : trap_type := "001001";
constant TT_TAG : trap_type := "001010";
constant TT_WATCH : trap_type := "001011";
constant TT_DSU : trap_type := "010000";
constant TT_PWD : trap_type := "010001";
constant TT_RFERR : trap_type := "100000";
constant TT_IAERR : trap_type := "100001";
constant TT_CPDIS : trap_type := "100100";
constant TT_CPEXC : trap_type := "101000";
constant TT_DIV : trap_type := "101010";
constant TT_DSEX : trap_type := "101011";
constant TT_TICC : trap_type := "111111";
-- Alternate address space identifiers
subtype asi_type is std_logic_vector(4 downto 0);
constant ASI_SYSR : asi_type := "00010"; -- 0x02
constant ASI_UINST : asi_type := "01000"; -- 0x08
constant ASI_SINST : asi_type := "01001"; -- 0x09
constant ASI_UDATA : asi_type := "01010"; -- 0x0A
constant ASI_SDATA : asi_type := "01011"; -- 0x0B
constant ASI_ITAG : asi_type := "01100"; -- 0x0C
constant ASI_IDATA : asi_type := "01101"; -- 0x0D
constant ASI_DTAG : asi_type := "01110"; -- 0x0E
constant ASI_DDATA : asi_type := "01111"; -- 0x0F
constant ASI_IFLUSH : asi_type := "10000"; -- 0x10
constant ASI_DFLUSH : asi_type := "10001"; -- 0x11
constant ASI_FLUSH_PAGE : std_logic_vector(4 downto 0) := "10000"; -- 0x10 i/dcache flush page
constant ASI_FLUSH_CTX : std_logic_vector(4 downto 0) := "10011"; -- 0x13 i/dcache flush ctx
constant ASI_DCTX : std_logic_vector(4 downto 0) := "10100"; -- 0x14 dcache ctx
constant ASI_ICTX : std_logic_vector(4 downto 0) := "10101"; -- 0x15 icache ctx
-- ASIs traditionally used by LEON for SRMMU
constant ASI_MMUFLUSHPROBE : std_logic_vector(4 downto 0) := "11000"; -- 0x18 i/dtlb flush/(probe)
constant ASI_MMUREGS : std_logic_vector(4 downto 0) := "11001"; -- 0x19 mmu regs access
constant ASI_MMU_BP : std_logic_vector(4 downto 0) := "11100"; -- 0x1c mmu Bypass
constant ASI_MMU_DIAG : std_logic_vector(4 downto 0) := "11101"; -- 0x1d mmu diagnostic
constant ASI_MMUSNOOP_DTAG : std_logic_vector(4 downto 0) := "11110"; -- 0x1e mmusnoop physical dtag
--constant ASI_MMU_DSU : std_logic_vector(4 downto 0) := "11111"; -- 0x1f mmu diagnostic
-- ASIs recommended in V8 specification, appendix I
constant ASI_MMUFLUSHPROBE_V8 : std_logic_vector(4 downto 0) := "00011"; -- 0x03 i/dtlb flush/(probe)
constant ASI_MMUREGS_V8 : std_logic_vector(4 downto 0) := "00100"; -- 0x04 mmu regs access
--constant ASI_MMU_BP_V8 : std_logic_vector(4 downto 0) := "11100"; -- 0x1c mmu Bypass
--constant ASI_MMU_DIAG_V8 : std_logic_vector(4 downto 0) := "11101"; -- 0x1d mmu diagnostic
-- ftt decoding
subtype ftt_type is std_logic_vector(2 downto 0);
constant FPIEEE_ERR : ftt_type := "001";
constant FPUNIMP_ERR : ftt_type := "011";
constant FPSEQ_ERR : ftt_type := "100";
constant FPHW_ERR : ftt_type := "101";
end;
| gpl-3.0 | 28667d9f26371acaee77066525c542e0 | 0.628289 | 3.288889 | false | false | false | false |
freecores/cryptopan_core | tb/cryptopan_unit_tb.vhd | 1 | 5,203 | --
-- This file is part of the Crypto-PAn core (www.opencores.org).
--
-- Copyright (c) 2007 The University of Waikato, Hamilton, New Zealand.
-- Authors: Anthony Blake ([email protected])
--
-- All rights reserved.
--
-- This code has been developed by the University of Waikato WAND
-- research group. For further information please see http://www.wand.net.nz/
--
-- This source file is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This source is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with libtrace; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
entity cryptopan_unit_tb is
end cryptopan_unit_tb;
architecture tb of cryptopan_unit_tb is
component cryptopan_unit
port (
clk : in std_logic;
reset : in std_logic;
ready : out std_logic;
key : in std_logic_vector(255 downto 0);
key_wren : in std_logic;
ip_in : in std_logic_vector(31 downto 0);
ip_wren : in std_logic;
ip_out : out std_logic_vector(31 downto 0);
ip_dv : out std_logic);
end component;
signal clk : std_logic;
signal reset : std_logic;
signal key : std_logic_vector(255 downto 0);
signal key_wren : std_logic;
signal ready : std_logic;
signal ip_in, ip_out : std_logic_vector(31 downto 0);
signal ip_wren, ip_dv : std_logic;
type char_file is file of character;
file bin_file_raw : char_file is in "sim/trace_bin_raw";
file bin_file_anon : char_file is in "sim/trace_bin_anon";
signal ip_in_int : std_logic_vector(31 downto 0);
signal ip_out_int : std_logic_vector(31 downto 0);
begin
CLKGEN : process
begin
clk <= '1';
wait for 5 ns;
clk <= '0';
wait for 5 ns;
end process CLKGEN;
DUT : cryptopan_unit
port map (
clk => clk,
reset => reset,
ready => ready,
key => key,
key_wren => key_wren,
ip_in => ip_in,
ip_wren => ip_wren,
ip_out => ip_out,
ip_dv => ip_dv);
GEN_IPS : process
variable my_char : character;
begin -- process GEN_IPS
-- file_open(bin_file_raw, "sim/trace_bin_raw", read_mode);
ip_in_int <= (others => '0');
ip_wren <= '0';
wait until ready = '1';
wait for 50 ns;
while not endfile(bin_file_raw) loop
read(bin_file_raw, my_char);
ip_in_int(31 downto 24) <= conv_std_logic_vector(character'pos(my_char), 8);
read(bin_file_raw, my_char);
ip_in_int(23 downto 16) <= conv_std_logic_vector(character'pos(my_char), 8);
read(bin_file_raw, my_char);
ip_in_int(15 downto 8) <= conv_std_logic_vector(character'pos(my_char), 8);
read(bin_file_raw, my_char);
ip_in_int(7 downto 0) <= conv_std_logic_vector(character'pos(my_char), 8);
wait for 10 ns;
ip_wren <= '1';
wait for 10 ns;
ip_wren <= '0';
wait until ready = '1';
end loop;
report "TEST COMPLETED" severity note;
end process GEN_IPS;
IP_OUT_INT_LOGIC : process
variable my_char : character;
begin -- process IP_OUT_INT_LOGIC
--ip_out_int <= (others => '0');
wait until ip_dv = '1';
read(bin_file_anon, my_char);
ip_out_int(31 downto 24) <= conv_std_logic_vector(character'pos(my_char), 8);
read(bin_file_anon, my_char);
ip_out_int(23 downto 16) <= conv_std_logic_vector(character'pos(my_char), 8);
read(bin_file_anon, my_char);
ip_out_int(15 downto 8) <= conv_std_logic_vector(character'pos(my_char), 8);
read(bin_file_anon, my_char);
ip_out_int(7 downto 0) <= conv_std_logic_vector(character'pos(my_char), 8);
end process IP_OUT_INT_LOGIC;
DV_LOGIC : process(clk)
variable my_char : character;
begin -- process DV_LOGIC
if clk'event and clk = '1' then
if ip_dv = '1' then
assert ip_out_int = ip_out report "TEST FAILED" severity error;
end if;
end if;
end process DV_LOGIC;
ip_in <= ip_in_int;
TESTBENCH : process
begin
reset <= '1';
-- ip_in <= (others => '0');
key <= (others => '0');
-- ip_wren <= '0';
key_wren <= '0';
wait for 50 ns;
reset <= '0';
wait for 20 ns;
key <= X"d8988f837979652762574c2d2a8422021522178d33a4cf80130a5b1649907d10";
key_wren <= '1';
wait for 10 ns;
key_wren <= '0';
-- wait until ready='1';
-- wait for 40 ns;
-- ip_in <= X"18050050";
-- ip_wren <= '1';
-- wait for 10 ns;
-- ip_wren <= '0';
-- wait until ready='1';
wait;
end process TESTBENCH;
end tb;
| gpl-2.0 | 3bdb489f6598f7495cc36d7c7be44b59 | 0.612531 | 3.124925 | false | false | false | false |
hoglet67/CoPro6502 | src/AlanD/R65Cx2.vhd | 1 | 62,018 | -- -----------------------------------------------------------------------
--
-- This is a table driven 65Cx2 core by A.Daly
-- This is a derivative of the excellent FPGA64 core see below
--
-- -----------------------------------------------------------------------
-- Copyright 2005-2008 by Peter Wendrich ([email protected])
-- http://www.syntiac.com/fpga64.html
-- -----------------------------------------------------------------------
library IEEE;
use ieee.std_logic_1164.ALL;
use ieee.numeric_std.ALL;
entity R65C02 is
port (
reset : in std_logic;
clk : in std_logic;
enable : in std_logic;
nmi_n : in std_logic;
irq_n : in std_logic;
di : in unsigned(7 downto 0);
do : out unsigned(7 downto 0);
do_next : out unsigned(7 downto 0);
addr : out unsigned(15 downto 0);
addr_next : out unsigned(15 downto 0);
nwe : out std_logic;
nwe_next : out std_logic;
sync : out std_logic;
sync_irq : out std_logic
);
end R65C02;
-- Store Zp (3) => fetch, cycle2, cycleEnd
-- Store Zp,x (4) => fetch, cycle2, preWrite, cycleEnd
-- Read Zp,x (4) => fetch, cycle2, cycleRead, cycleRead2
-- Rmw Zp,x (6) => fetch, cycle2, cycleRead, cycleRead2, cycleRmw, cycleEnd
-- Store Abs (4) => fetch, cycle2, cycle3, cycleEnd
-- Store Abs,x (5) => fetch, cycle2, cycle3, preWrite, cycleEnd
-- Rts (6) => fetch, cycle2, cycle3, cycleRead, cycleJump, cycleIncrEnd
-- Rti (6) => fetch, cycle2, stack1, stack2, stack3, cycleJump
-- Jsr (6) => fetch, cycle2, .. cycle5, cycle6, cycleJump
-- Jmp abs (-) => fetch, cycle2, .., cycleJump
-- Jmp (ind) (-) => fetch, cycle2, .., cycleJump
-- Brk / irq (6) => fetch, cycle2, stack2, stack3, stack4
-- -----------------------------------------------------------------------
architecture Behavioral of R65C02 is
-- signal counter : unsigned(27 downto 0);
-- signal mask_irq : std_logic;
-- signal mask_enable : std_logic;
-- Statemachine
type cpuCycles is (
opcodeFetch, -- New opcode is read and registers updated
cycle2,
cycle3,
cyclePreIndirect,
cycleIndirect,
cycleBranchTaken,
cycleBranchPage,
cyclePreRead, -- Cycle before read while doing zeropage indexed addressing.
cycleRead, -- Read cycle
cycleRead2, -- Second read cycle after page-boundary crossing.
cycleRmw, -- Calculate ALU output for read-modify-write instr.
cyclePreWrite, -- Cycle before write when doing indexed addressing.
cycleWrite, -- Write cycle for zeropage or absolute addressing.
cycleStack1,
cycleStack2,
cycleStack3,
cycleStack4,
cycleJump, -- Last cycle of Jsr, Jmp. Next fetch address is target addr.
cycleEnd
);
signal theCpuCycle : cpuCycles;
signal nextCpuCycle : cpuCycles;
signal updateRegisters : boolean;
signal processIrq : std_logic;
signal nmiReg: std_logic;
signal nmiEdge: std_logic;
signal irqReg : std_logic; -- Delay IRQ input with one clock cycle.
signal soReg : std_logic; -- SO pin edge detection
-- Opcode decoding
constant opcUpdateA : integer := 0;
constant opcUpdateX : integer := 1;
constant opcUpdateY : integer := 2;
constant opcUpdateS : integer := 3;
constant opcUpdateN : integer := 4;
constant opcUpdateV : integer := 5;
constant opcUpdateD : integer := 6;
constant opcUpdateI : integer := 7;
constant opcUpdateZ : integer := 8;
constant opcUpdateC : integer := 9;
constant opcSecondByte : integer := 10;
constant opcAbsolute : integer := 11;
constant opcZeroPage : integer := 12;
constant opcIndirect : integer := 13;
constant opcStackAddr : integer := 14; -- Push/Pop address
constant opcStackData : integer := 15; -- Push/Pop status/data
constant opcJump : integer := 16;
constant opcBranch : integer := 17;
constant indexX : integer := 18;
constant indexY : integer := 19;
constant opcStackUp : integer := 20;
constant opcWrite : integer := 21;
constant opcRmw : integer := 22;
constant opcIncrAfter : integer := 23; -- Insert extra cycle to increment PC (RTS)
constant opcRti : integer := 24;
constant opcIRQ : integer := 25;
constant opcInA : integer := 26;
constant opcInBrk : integer := 27;
constant opcInX : integer := 28;
constant opcInY : integer := 29;
constant opcInS : integer := 30;
constant opcInT : integer := 31;
constant opcInH : integer := 32;
constant opcInClear : integer := 33;
constant aluMode1From : integer := 34;
--
constant aluMode1To : integer := 37;
constant aluMode2From : integer := 38;
--
constant aluMode2To : integer := 40;
--
constant opcInCmp : integer := 41;
constant opcInCpx : integer := 42;
constant opcInCpy : integer := 43;
subtype addrDef is unsigned(0 to 15);
--
-- is Interrupt -----------------+
-- instruction is RTI ----------------+|
-- PC++ on last cycle (RTS) ---------------+||
-- RMW --------------+|||
-- Write -------------+||||
-- Pop/Stack up -------------+|||||
-- Branch ---------+ ||||||
-- Jump ----------+| ||||||
-- Push or Pop data -------+|| ||||||
-- Push or Pop addr ------+||| ||||||
-- Indirect -----+|||| ||||||
-- ZeroPage ----+||||| ||||||
-- Absolute ---+|||||| ||||||
-- PC++ on cycle2 --+||||||| ||||||
-- |AZI||JBXY|WM|||
constant immediate : addrDef := "1000000000000000";
constant implied : addrDef := "0000000000000000";
-- Zero page
constant readZp : addrDef := "1010000000000000";
constant writeZp : addrDef := "1010000000010000";
constant rmwZp : addrDef := "1010000000001000";
-- Zero page indexed
constant readZpX : addrDef := "1010000010000000";
constant writeZpX : addrDef := "1010000010010000";
constant rmwZpX : addrDef := "1010000010001000";
constant readZpY : addrDef := "1010000001000000";
constant writeZpY : addrDef := "1010000001010000";
constant rmwZpY : addrDef := "1010000001001000";
-- Zero page indirect
constant readIndX : addrDef := "1001000010000000";
constant writeIndX : addrDef := "1001000010010000";
constant rmwIndX : addrDef := "1001000010001000";
constant readIndY : addrDef := "1001000001000000";
constant writeIndY : addrDef := "1001000001010000";
constant rmwIndY : addrDef := "1001000001001000";
constant rmwInd : addrDef := "1001000000001000";
constant readInd : addrDef := "1001000000000000";
constant writeInd : addrDef := "1001000000010000";
-- |AZI||JBXY|WM||
-- Absolute
constant readAbs : addrDef := "1100000000000000";
constant writeAbs : addrDef := "1100000000010000";
constant rmwAbs : addrDef := "1100000000001000";
constant readAbsX : addrDef := "1100000010000000";
constant writeAbsX : addrDef := "1100000010010000";
constant rmwAbsX : addrDef := "1100000010001000";
constant readAbsY : addrDef := "1100000001000000";
constant writeAbsY : addrDef := "1100000001010000";
constant rmwAbsY : addrDef := "1100000001001000";
-- PHA PHP
constant push : addrDef := "0000010000000000";
-- PLA PLP
constant pop : addrDef := "0000010000100000";
-- Jumps
constant jsr : addrDef := "1000101000000000";
constant jumpAbs : addrDef := "1000001000000000";
constant jumpInd : addrDef := "1100001000000000";
constant jumpIndX : addrDef := "1100001010000000";
constant relative : addrDef := "1000000100000000";
-- Specials
constant rts : addrDef := "0000101000100100";
constant rti : addrDef := "0000111000100010";
constant brk : addrDef := "1000111000000001";
-- constant irq : addrDef := "0000111000000001";
-- constant : unsigned(0 to 0) := "0";
constant xxxxxxxx : addrDef := "----------0---00";
-- A = accu
-- X = index X
-- Y = index Y
-- S = Stack pointer
-- H = indexH
--
-- AEXYSTHc
constant aluInA : unsigned(0 to 7) := "10000000";
constant aluInBrk : unsigned(0 to 7) := "01000000";
constant aluInX : unsigned(0 to 7) := "00100000";
constant aluInY : unsigned(0 to 7) := "00010000";
constant aluInS : unsigned(0 to 7) := "00001000";
constant aluInT : unsigned(0 to 7) := "00000100";
constant aluInClr : unsigned(0 to 7) := "00000001";
constant aluInSet : unsigned(0 to 7) := "00000000";
constant aluInXXX : unsigned(0 to 7) := "--------";
-- Most of the aluModes are just like the opcodes.
-- aluModeInp -> input is output. calculate N and Z
-- aluModeCmp -> Compare for CMP, CPX, CPY
-- aluModeFlg -> input to flags needed for PLP, RTI and CLC, SEC, CLV
-- aluModeInc -> for INC but also INX, INY
-- aluModeDec -> for DEC but also DEX, DEY
subtype aluMode1 is unsigned(0 to 3);
subtype aluMode2 is unsigned(0 to 2);
subtype aluMode is unsigned(0 to 9);
-- Logic/Shift ALU
constant aluModeInp : aluMode1 := "0000";
constant aluModeP : aluMode1 := "0001";
constant aluModeInc : aluMode1 := "0010";
constant aluModeDec : aluMode1 := "0011";
constant aluModeFlg : aluMode1 := "0100";
constant aluModeBit : aluMode1 := "0101";
-- 0110
-- 0111
constant aluModeLsr : aluMode1 := "1000";
constant aluModeRor : aluMode1 := "1001";
constant aluModeAsl : aluMode1 := "1010";
constant aluModeRol : aluMode1 := "1011";
constant aluModeTSB : aluMode1 := "1100";
constant aluModeTRB : aluMode1 := "1101";
-- 1110
-- 1111;
-- Arithmetic ALU
constant aluModePss : aluMode2 := "000";
constant aluModeCmp : aluMode2 := "001";
constant aluModeAdc : aluMode2 := "010";
constant aluModeSbc : aluMode2 := "011";
constant aluModeAnd : aluMode2 := "100";
constant aluModeOra : aluMode2 := "101";
constant aluModeEor : aluMode2 := "110";
constant aluModeNoF : aluMode2 := "111";
--aluModeBRK
--constant aluBrk : aluMode := aluModeBRK & aluModePss & "---";
--constant aluFix : aluMode := aluModeInp & aluModeNoF & "---";
constant aluInp : aluMode := aluModeInp & aluModePss & "---";
constant aluP : aluMode := aluModeP & aluModePss & "---";
constant aluInc : aluMode := aluModeInc & aluModePss & "---";
constant aluDec : aluMode := aluModeDec & aluModePss & "---";
constant aluFlg : aluMode := aluModeFlg & aluModePss & "---";
constant aluBit : aluMode := aluModeBit & aluModeAnd & "---";
constant aluRor : aluMode := aluModeRor & aluModePss & "---";
constant aluLsr : aluMode := aluModeLsr & aluModePss & "---";
constant aluRol : aluMode := aluModeRol & aluModePss & "---";
constant aluAsl : aluMode := aluModeAsl & aluModePss & "---";
constant aluTSB : aluMode := aluModeTSB & aluModePss & "---";
constant aluTRB : aluMode := aluModeTRB & aluModePss & "---";
constant aluCmp : aluMode := aluModeInp & aluModeCmp & "100";
constant aluCpx : aluMode := aluModeInp & aluModeCmp & "010";
constant aluCpy : aluMode := aluModeInp & aluModeCmp & "001";
constant aluAdc : aluMode := aluModeInp & aluModeAdc & "---";
constant aluSbc : aluMode := aluModeInp & aluModeSbc & "---";
constant aluAnd : aluMode := aluModeInp & aluModeAnd & "---";
constant aluOra : aluMode := aluModeInp & aluModeOra & "---";
constant aluEor : aluMode := aluModeInp & aluModeEor & "---";
constant aluXXX : aluMode := (others => '-');
-- Stack operations. Push/Pop/None
constant stackInc : unsigned(0 to 0) := "0";
constant stackDec : unsigned(0 to 0) := "1";
constant stackXXX : unsigned(0 to 0) := "-";
subtype decodedBitsDef is unsigned(0 to 43);
type opcodeInfoTableDef is array(0 to 255) of decodedBitsDef;
constant opcodeInfoTable : opcodeInfoTableDef := (
-- +------- Update register A
-- |+------ Update register X
-- ||+----- Update register Y
-- |||+---- Update register S
-- |||| +-- Update Flags
-- |||| |
-- |||| _|__
-- |||| / \
-- AXYS NVDIZC addressing aluInput aluMode
-- AXYS NVDIZC addressing aluInput aluMode
"0000" & "001100" & brk & aluInBrk & aluP, -- 00 BRK
"1000" & "100010" & readIndX & aluInT & aluOra, -- 01 ORA (zp,x)
"0000" & "000000" & immediate & aluInXXX & aluXXX, -- 02 NOP ------- 65C02
"0000" & "000000" & implied & aluInXXX & aluXXX, -- 03 NOP ------- 65C02
"0000" & "000010" & rmwZp & aluInT & aluTSB, -- 04 TSB zp ----------- 65C02
"1000" & "100010" & readZp & aluInT & aluOra, -- 05 ORA zp
"0000" & "100011" & rmwZp & aluInT & aluAsl, -- 06 ASL zp
"0000" & "000000" & implied & aluInXXX & aluXXX, -- 07 NOP ------- 65C02
"0000" & "000000" & push & aluInXXX & aluP, -- 08 PHP
"1000" & "100010" & immediate & aluInT & aluOra, -- 09 ORA imm
"1000" & "100011" & implied & aluInA & aluAsl, -- 0A ASL accu
"0000" & "000000" & implied & aluInXXX & aluXXX, -- 0B NOP ------- 65C02
"0000" & "000010" & rmwAbs & aluInT & aluTSB, -- 0C TSB abs ---------- 65C02
"1000" & "100010" & readAbs & aluInT & aluOra, -- 0D ORA abs
"0000" & "100011" & rmwAbs & aluInT & aluAsl, -- 0E ASL abs
"0000" & "000000" & implied & aluInXXX & aluXXX, -- 0F NOP ------- 65C02
"0000" & "000000" & relative & aluInXXX & aluXXX, -- 10 BPL
"1000" & "100010" & readIndY & aluInT & aluOra, -- 11 ORA (zp),y
"1000" & "100010" & readInd & aluInT & aluOra, -- 12 ORA (zp) --------- 65C02
"0000" & "000000" & implied & aluInXXX & aluXXX, -- 13 NOP ------- 65C02
"0000" & "000010" & rmwZp & aluInT & aluTRB, -- 14 TRB zp ~---------- 65C02
"1000" & "100010" & readZpX & aluInT & aluOra, -- 15 ORA zp,x
"0000" & "100011" & rmwZpX & aluInT & aluAsl, -- 16 ASL zp,x
"0000" & "000000" & implied & aluInXXX & aluXXX, -- 17 NOP ------- 65C02
"0000" & "000001" & implied & aluInClr & aluFlg, -- 18 CLC
"1000" & "100010" & readAbsY & aluInT & aluOra, -- 19 ORA abs,y
"1000" & "100010" & implied & aluInA & aluInc, -- 1A INC accu --------- 65C02
"0000" & "000000" & implied & aluInXXX & aluXXX, -- 1B NOP ------- 65C02
"0000" & "000010" & rmwAbs & aluInT & aluTRB, -- 1C TRB abs ~----- --- 65C02
"1000" & "100010" & readAbsX & aluInT & aluOra, -- 1D ORA abs,x
"0000" & "100011" & rmwAbsX & aluInT & aluAsl, -- 1E ASL abs,x
"0000" & "000000" & implied & aluInXXX & aluXXX, -- 1F NOP ------- 65C02
-- AXYS NVDIZC addressing aluInput aluMode
"0000" & "000000" & jsr & aluInXXX & aluXXX, -- 20 JSR
"1000" & "100010" & readIndX & aluInT & aluAnd, -- 21 AND (zp,x)
"0000" & "000000" & immediate & aluInXXX & aluXXX, -- 22 NOP ------- 65C02
"0000" & "000000" & implied & aluInXXX & aluXXX, -- 23 NOP ------- 65C02
"0000" & "110010" & readZp & aluInT & aluBit, -- 24 BIT zp
"1000" & "100010" & readZp & aluInT & aluAnd, -- 25 AND zp
"0000" & "100011" & rmwZp & aluInT & aluRol, -- 26 ROL zp
"0000" & "000000" & implied & aluInXXX & aluXXX, -- 27 NOP ------- 65C02
"0000" & "111111" & pop & aluInT & aluFlg, -- 28 PLP
"1000" & "100010" & immediate & aluInT & aluAnd, -- 29 AND imm
"1000" & "100011" & implied & aluInA & aluRol, -- 2A ROL accu
"0000" & "000000" & implied & aluInXXX & aluXXX, -- 2B NOP ------- 65C02
"0000" & "110010" & readAbs & aluInT & aluBit, -- 2C BIT abs
"1000" & "100010" & readAbs & aluInT & aluAnd, -- 2D AND abs
"0000" & "100011" & rmwAbs & aluInT & aluRol, -- 2E ROL abs
"0000" & "000000" & implied & aluInXXX & aluXXX, -- 2F NOP ------- 65C02
"0000" & "000000" & relative & aluInXXX & aluXXX, -- 30 BMI
"1000" & "100010" & readIndY & aluInT & aluAnd, -- 31 AND (zp),y
"1000" & "100010" & readInd & aluInT & aluAnd, -- 32 AND (zp) -------- 65C02
"0000" & "000000" & implied & aluInXXX & aluXXX, -- 33 NOP ------- 65C02
"0000" & "110010" & readZpX & aluInT & aluBit, -- 34 BIT zp,x -------- 65C02
"1000" & "100010" & readZpX & aluInT & aluAnd, -- 35 AND zp,x
"0000" & "100011" & rmwZpX & aluInT & aluRol, -- 36 ROL zp,x
"0000" & "000000" & implied & aluInXXX & aluXXX, -- 37 NOP ------- 65C02
"0000" & "000001" & implied & aluInSet & aluFlg, -- 38 SEC
"1000" & "100010" & readAbsY & aluInT & aluAnd, -- 39 AND abs,y
"1000" & "100010" & implied & aluInA & aluDec, -- 3A DEC accu -------- 65C12
"0000" & "000000" & implied & aluInXXX & aluXXX, -- 3B NOP ------- 65C02
"0000" & "110010" & readAbsX & aluInT & aluBit, -- 3C BIT abs,x ------- 65C02
"1000" & "100010" & readAbsX & aluInT & aluAnd, -- 3D AND abs,x
"0000" & "100011" & rmwAbsX & aluInT & aluRol, -- 3E ROL abs,x
"0000" & "000000" & implied & aluInXXX & aluXXX, -- 3F NOP ------- 65C02
-- AXYS NVDIZC addressing aluInput aluMode
"0000" & "111111" & rti & aluInT & aluFlg, -- 40 RTI
"1000" & "100010" & readIndX & aluInT & aluEor, -- 41 EOR (zp,x)
"0000" & "000000" & immediate & aluInXXX & aluXXX, -- 42 NOP ------- 65C02
"0000" & "000000" & implied & aluInXXX & aluXXX, -- 43 NOP ------- 65C02
"0000" & "000000" & immediate & aluInXXX & aluXXX, -- 44 NOP ------- 65C02
"1000" & "100010" & readZp & aluInT & aluEor, -- 45 EOR zp
"0000" & "100011" & rmwZp & aluInT & aluLsr, -- 46 LSR zp
"0000" & "000000" & implied & aluInXXX & aluXXX, -- 47 NOP ------- 65C02
"0000" & "000000" & push & aluInA & aluInp, -- 48 PHA
"1000" & "100010" & immediate & aluInT & aluEor, -- 49 EOR imm
"1000" & "100011" & implied & aluInA & aluLsr, -- 4A LSR accu -------- 65C02
"0000" & "000000" & implied & aluInXXX & aluXXX, -- 4B NOP ------- 65C02
"0000" & "000000" & jumpAbs & aluInXXX & aluXXX, -- 4C JMP abs
"1000" & "100010" & readAbs & aluInT & aluEor, -- 4D EOR abs
"0000" & "100011" & rmwAbs & aluInT & aluLsr, -- 4E LSR abs
"0000" & "000000" & implied & aluInXXX & aluXXX, -- 4F NOP ------- 65C02
"0000" & "000000" & relative & aluInXXX & aluXXX, -- 50 BVC
"1000" & "100010" & readIndY & aluInT & aluEor, -- 51 EOR (zp),y
"1000" & "100010" & readInd & aluInT & aluEor, -- 52 EOR (zp) -------- 65C02
"0000" & "000000" & implied & aluInXXX & aluXXX, -- 53 NOP ------- 65C02
"0000" & "000000" & immediate & aluInXXX & aluXXX, -- 54 NOP ------- 65C02
"1000" & "100010" & readZpX & aluInT & aluEor, -- 55 EOR zp,x
"0000" & "100011" & rmwZpX & aluInT & aluLsr, -- 56 LSR zp,x
"0000" & "000000" & implied & aluInXXX & aluXXX, -- 57 NOP ------- 65C02
"0000" & "000100" & implied & aluInClr & aluXXX, -- 58 CLI
"1000" & "100010" & readAbsY & aluInT & aluEor, -- 59 EOR abs,y
"0000" & "000000" & push & aluInY & aluInp, -- 5A PHY ------------- 65C02
"0000" & "000000" & implied & aluInXXX & aluXXX, -- 5B NOP ------- 65C02
"0000" & "000000" & readAbs & aluInXXX & aluXXX, -- 5C NOP ------- 65C02
"1000" & "100010" & readAbsX & aluInT & aluEor, -- 5D EOR abs,x
"0000" & "100011" & rmwAbsX & aluInT & aluLsr, -- 5E LSR abs,x
"0000" & "000000" & implied & aluInXXX & aluXXX, -- 5F NOP ------- 65C02
-- AXYS NVDIZC addressing aluInput aluMode
"0000" & "000000" & rts & aluInXXX & aluXXX, -- 60 RTS
"1000" & "110011" & readIndX & aluInT & aluAdc, -- 61 ADC (zp,x)
"0000" & "000000" & immediate & aluInXXX & aluXXX, -- 62 NOP ------- 65C02
"0000" & "000000" & implied & aluInXXX & aluXXX, -- 63 NOP ------- 65C02
"0000" & "000000" & writeZp & aluInClr & aluInp, -- 64 STZ zp ---------- 65C02
"1000" & "110011" & readZp & aluInT & aluAdc, -- 65 ADC zp
"0000" & "100011" & rmwZp & aluInT & aluRor, -- 66 ROR zp
"0000" & "000000" & implied & aluInXXX & aluXXX, -- 67 NOP ------- 65C02
"1000" & "100010" & pop & aluInT & aluInp, -- 68 PLA
"1000" & "110011" & immediate & aluInT & aluAdc, -- 69 ADC imm
"1000" & "100011" & implied & aluInA & aluRor, -- 6A ROR accu
"0000" & "000000" & implied & aluInXXX & aluXXX, -- 6B NOP ------ 65C02
"0000" & "000000" & jumpInd & aluInXXX & aluXXX, -- 6C JMP indirect
"1000" & "110011" & readAbs & aluInT & aluAdc, -- 6D ADC abs
"0000" & "100011" & rmwAbs & aluInT & aluRor, -- 6E ROR abs
"0000" & "000000" & implied & aluInXXX & aluXXX, -- 6F NOP ------ 65C02
"0000" & "000000" & relative & aluInXXX & aluXXX, -- 70 BVS
"1000" & "110011" & readIndY & aluInT & aluAdc, -- 71 ADC (zp),y
"1000" & "110011" & readInd & aluInT & aluAdc, -- 72 ADC (zp) -------- 65C02
"0000" & "000000" & implied & aluInXXX & aluXXX, -- 73 NOP ------ 65C02
"0000" & "000000" & writeZpX & aluInClr & aluInp, -- 74 STZ zp,x -------- 65C02
"1000" & "110011" & readZpX & aluInT & aluAdc, -- 75 ADC zp,x
"0000" & "100011" & rmwZpX & aluInT & aluRor, -- 76 ROR zp,x
"0000" & "000000" & implied & aluInXXX & aluXXX, -- 77 NOP ----- 65C02
"0000" & "000100" & implied & aluInSet & aluXXX, -- 78 SEI
"1000" & "110011" & readAbsY & aluInT & aluAdc, -- 79 ADC abs,y
"0010" & "100010" & pop & aluInT & aluInp, -- 7A PLY ------------- 65C02
"0000" & "000000" & implied & aluInXXX & aluXXX, -- 7B NOP ----- 65C02
"0000" & "000000" & jumpIndX & aluInXXX & aluXXX, -- 7C JMP indirect,x -- 65C02
--"0000" & "000000" & jumpInd & aluInXXX & aluXXX, -- 6C JMP indirect
"1000" & "110011" & readAbsX & aluInT & aluAdc, -- 7D ADC abs,x
"0000" & "100011" & rmwAbsX & aluInT & aluRor, -- 7E ROR abs,x
"0000" & "000000" & implied & aluInXXX & aluXXX, -- 7F NOP ----- 65C02
-- AXYS NVDIZC addressing aluInput aluMode
"0000" & "000000" & relative & aluInXXX & aluXXX, -- 80 BRA ----------- 65C02
"0000" & "000000" & writeIndX & aluInA & aluInp, -- 81 STA (zp,x)
"0000" & "000000" & immediate & aluInXXX & aluXXX, -- 82 NOP ----- 65C02
"0000" & "000000" & implied & aluInXXX & aluXXX, -- 83 NOP ----- 65C02
"0000" & "000000" & writeZp & aluInY & aluInp, -- 84 STY zp
"0000" & "000000" & writeZp & aluInA & aluInp, -- 85 STA zp
"0000" & "000000" & writeZp & aluInX & aluInp, -- 86 STX zp
"0000" & "000000" & implied & aluInXXX & aluXXX, -- 87 NOP ----- 65C02
"0010" & "100010" & implied & aluInY & aluDec, -- 88 DEY
"0000" & "000010" & immediate & aluInT & aluBit, -- 89 BIT imm ------- 65C02
"1000" & "100010" & implied & aluInX & aluInp, -- 8A TXA
"0000" & "000000" & implied & aluInXXX & aluXXX, -- 8B NOP ----- 65C02
"0000" & "000000" & writeAbs & aluInY & aluInp, -- 8C STY abs ------- 65C02
"0000" & "000000" & writeAbs & aluInA & aluInp, -- 8D STA abs
"0000" & "000000" & writeAbs & aluInX & aluInp, -- 8E STX abs
"0000" & "000000" & implied & aluInXXX & aluXXX, -- 8F NOP ----- 65C02
"0000" & "000000" & relative & aluInXXX & aluXXX, -- 90 BCC
"0000" & "000000" & writeIndY & aluInA & aluInp, -- 91 STA (zp),y
"0000" & "000000" & writeInd & aluInA & aluInp, -- 92 STA (zp) ------ 65C02
"0000" & "000000" & implied & aluInXXX & aluXXX, -- 93 NOP ----- 65C02
"0000" & "000000" & writeZpX & aluInY & aluInp, -- 94 STY zp,x
"0000" & "000000" & writeZpX & aluInA & aluInp, -- 95 STA zp,x
"0000" & "000000" & writeZpY & aluInX & aluInp, -- 96 STX zp,y
"0000" & "000000" & implied & aluInXXX & aluXXX, -- 97 NOP ----- 65C02
"1000" & "100010" & implied & aluInY & aluInp, -- 98 TYA
"0000" & "000000" & writeAbsY & aluInA & aluInp, -- 99 STA abs,y
"0001" & "000000" & implied & aluInX & aluInp, -- 9A TXS
"0000" & "000000" & implied & aluInXXX & aluXXX, -- 9B NOP ----- 65C02
"0000" & "000000" & writeAbs & aluInClr & aluInp, -- 9C STZ Abs ------- 65C02
"0000" & "000000" & writeAbsX & aluInA & aluInp, -- 9D STA abs,x
"0000" & "000000" & writeAbsX & aluInClr & aluInp, -- 9C STZ Abs,x ----- 65C02
"0000" & "000000" & implied & aluInXXX & aluXXX, -- 9F NOP ----- 65C02
-- AXYS NVDIZC addressing aluInput aluMode
"0010" & "100010" & immediate & aluInT & aluInp, -- A0 LDY imm
"1000" & "100010" & readIndX & aluInT & aluInp, -- A1 LDA (zp,x)
"0100" & "100010" & immediate & aluInT & aluInp, -- A2 LDX imm
"0000" & "000000" & implied & aluInXXX & aluXXX, -- A3 NOP ----- 65C02
"0010" & "100010" & readZp & aluInT & aluInp, -- A4 LDY zp
"1000" & "100010" & readZp & aluInT & aluInp, -- A5 LDA zp
"0100" & "100010" & readZp & aluInT & aluInp, -- A6 LDX zp
"0000" & "000000" & implied & aluInXXX & aluXXX, -- A7 NOP ----- 65C02
"0010" & "100010" & implied & aluInA & aluInp, -- A8 TAY
"1000" & "100010" & immediate & aluInT & aluInp, -- A9 LDA imm
"0100" & "100010" & implied & aluInA & aluInp, -- AA TAX
"0000" & "000000" & implied & aluInXXX & aluXXX, -- AB NOP ----- 65C02
"0010" & "100010" & readAbs & aluInT & aluInp, -- AC LDY abs
"1000" & "100010" & readAbs & aluInT & aluInp, -- AD LDA abs
"0100" & "100010" & readAbs & aluInT & aluInp, -- AE LDX abs
"0000" & "000000" & implied & aluInXXX & aluXXX, -- AF NOP ----- 65C02
"0000" & "000000" & relative & aluInXXX & aluXXX, -- B0 BCS
"1000" & "100010" & readIndY & aluInT & aluInp, -- B1 LDA (zp),y
"1000" & "100010" & readInd & aluInT & aluInp, -- B2 LDA (zp) ------ 65C02
"0000" & "000000" & implied & aluInXXX & aluXXX, -- B3 NOP ----- 65C02
"0010" & "100010" & readZpX & aluInT & aluInp, -- B4 LDY zp,x
"1000" & "100010" & readZpX & aluInT & aluInp, -- B5 LDA zp,x
"0100" & "100010" & readZpY & aluInT & aluInp, -- B6 LDX zp,y
"0000" & "000000" & implied & aluInXXX & aluXXX, -- B7 NOP ----- 65C02
"0000" & "010000" & implied & aluInClr & aluFlg, -- B8 CLV
"1000" & "100010" & readAbsY & aluInT & aluInp, -- B9 LDA abs,y
"0100" & "100010" & implied & aluInS & aluInp, -- BA TSX
"0000" & "000000" & implied & aluInXXX & aluXXX, -- BB NOP ----- 65C02
"0010" & "100010" & readAbsX & aluInT & aluInp, -- BC LDY abs,x
"1000" & "100010" & readAbsX & aluInT & aluInp, -- BD LDA abs,x
"0100" & "100010" & readAbsY & aluInT & aluInp, -- BE LDX abs,y
"0000" & "000000" & implied & aluInXXX & aluXXX, -- BF NOP ----- 65C02
-- AXYS NVDIZC addressing aluInput aluMode
"0000" & "100011" & immediate & aluInT & aluCpy, -- C0 CPY imm
"0000" & "100011" & readIndX & aluInT & aluCmp, -- C1 CMP (zp,x)
"0000" & "000000" & immediate & aluInXXX & aluXXX, -- C2 NOP ----- 65C02
"0000" & "000000" & implied & aluInXXX & aluXXX, -- C3 NOP ----- 65C02
"0000" & "100011" & readZp & aluInT & aluCpy, -- C4 CPY zp
"0000" & "100011" & readZp & aluInT & aluCmp, -- C5 CMP zp
"0000" & "100010" & rmwZp & aluInT & aluDec, -- C6 DEC zp
"0000" & "000000" & implied & aluInXXX & aluXXX, -- C7 NOP ----- 65C02
"0010" & "100010" & implied & aluInY & aluInc, -- C8 INY
"0000" & "100011" & immediate & aluInT & aluCmp, -- C9 CMP imm
"0100" & "100010" & implied & aluInX & aluDec, -- CA DEX
"0000" & "000000" & implied & aluInXXX & aluXXX, -- CB NOP ----- 65C02
"0000" & "100011" & readAbs & aluInT & aluCpy, -- CC CPY abs
"0000" & "100011" & readAbs & aluInT & aluCmp, -- CD CMP abs
"0000" & "100010" & rmwAbs & aluInT & aluDec, -- CE DEC abs
"0000" & "000000" & implied & aluInXXX & aluXXX, -- CF NOP ----- 65C02
"0000" & "000000" & relative & aluInXXX & aluXXX, -- D0 BNE
"0000" & "100011" & readIndY & aluInT & aluCmp, -- D1 CMP (zp),y
"0000" & "100011" & readInd & aluInT & aluCmp, -- D2 CMP (zp) ------ 65C02
"0000" & "000000" & implied & aluInXXX & aluXXX, -- D3 NOP ----- 65C02
"0000" & "000000" & immediate & aluInXXX & aluXXX, -- D4 NOP ----- 65C02
"0000" & "100011" & readZpX & aluInT & aluCmp, -- D5 CMP zp,x
"0000" & "100010" & rmwZpX & aluInT & aluDec, -- D6 DEC zp,x
"0000" & "000000" & implied & aluInXXX & aluXXX, -- D7 NOP ----- 65C02
"0000" & "001000" & implied & aluInClr & aluXXX, -- D8 CLD
"0000" & "100011" & readAbsY & aluInT & aluCmp, -- D9 CMP abs,y
"0000" & "000000" & push & aluInX & aluInp, -- DA PHX ----------- 65C02
"0000" & "000000" & implied & aluInXXX & aluXXX, -- DB NOP ----- 65C02
"0000" & "000000" & readAbs & aluInXXX & aluXXX, -- DC NOP ----- 65C02
"0000" & "100011" & readAbsX & aluInT & aluCmp, -- DD CMP abs,x
"0000" & "100010" & rmwAbsX & aluInT & aluDec, -- DE DEC abs,x
"0000" & "000000" & implied & aluInXXX & aluXXX, -- DF NOP ----- 65C02
-- AXYS NVDIZC addressing aluInput aluMode
"0000" & "100011" & immediate & aluInT & aluCpx, -- E0 CPX imm
"1000" & "110011" & readIndX & aluInT & aluSbc, -- E1 SBC (zp,x)
"0000" & "000000" & immediate & aluInXXX & aluXXX, -- E2 NOP ----- 65C02
"0000" & "000000" & implied & aluInXXX & aluXXX, -- E3 NOP ----- 65C02
"0000" & "100011" & readZp & aluInT & aluCpx, -- E4 CPX zp
"1000" & "110011" & readZp & aluInT & aluSbc, -- E5 SBC zp
"0000" & "100010" & rmwZp & aluInT & aluInc, -- E6 INC zp
"0000" & "000000" & implied & aluInXXX & aluXXX, -- E7 NOP ----- 65C02
"0100" & "100010" & implied & aluInX & aluInc, -- E8 INX
"1000" & "110011" & immediate & aluInT & aluSbc, -- E9 SBC imm
"0000" & "000000" & implied & aluInXXX & aluXXX, -- EA NOP
"0000" & "000000" & implied & aluInXXX & aluXXX, -- EB NOP ----- 65C02
"0000" & "100011" & readAbs & aluInT & aluCpx, -- EC CPX abs
"1000" & "110011" & readAbs & aluInT & aluSbc, -- ED SBC abs
"0000" & "100010" & rmwAbs & aluInT & aluInc, -- EE INC abs
"0000" & "000000" & implied & aluInXXX & aluXXX, -- EF NOP ----- 65C02
"0000" & "000000" & relative & aluInXXX & aluXXX, -- F0 BEQ
"1000" & "110011" & readIndY & aluInT & aluSbc, -- F1 SBC (zp),y
"1000" & "110011" & readInd & aluInT & aluSbc, -- F2 SBC (zp) ------ 65C02
"0000" & "000000" & implied & aluInXXX & aluXXX, -- F3 NOP ----- 65C02
"0000" & "000000" & immediate & aluInXXX & aluXXX, -- F4 NOP ----- 65C02
"1000" & "110011" & readZpX & aluInT & aluSbc, -- F5 SBC zp,x
"0000" & "100010" & rmwZpX & aluInT & aluInc, -- F6 INC zp,x
"0000" & "000000" & implied & aluInXXX & aluXXX, -- F7 NOP ---- 65C02
"0000" & "001000" & implied & aluInSet & aluXXX, -- F8 SED
"1000" & "110011" & readAbsY & aluInT & aluSbc, -- F9 SBC abs,y
"0100" & "100010" & pop & aluInT & aluInp, -- FA PLX ----------- 65C02
"0000" & "000000" & implied & aluInXXX & aluXXX, -- FB NOP ----- 65C02
"0000" & "000000" & readAbs & aluInXXX & aluXXX, -- FC NOP ----- 65C02
"1000" & "110011" & readAbsX & aluInT & aluSbc, -- FD SBC abs,x
"0000" & "100010" & rmwAbsX & aluInT & aluInc, -- FE INC abs,x
"0000" & "000000" & implied & aluInXXX & aluXXX -- FF NOP ----- 65C02
);
signal opcInfo : decodedBitsDef;
signal nextOpcInfo : decodedBitsDef; -- Next opcode (decoded)
signal theOpcode : unsigned(7 downto 0);
signal nextOpcode : unsigned(7 downto 0);
-- Program counter
signal PC : unsigned(15 downto 0); -- Program counter
-- Address generation
type nextAddrDef is (
nextAddrHold,
nextAddrIncr,
nextAddrIncrL, -- Increment low bits only (zeropage accesses)
nextAddrIncrH, -- Increment high bits only (page-boundary)
nextAddrDecrH, -- Decrement high bits (branch backwards)
nextAddrPc,
nextAddrIrq,
nextAddrReset,
nextAddrAbs,
nextAddrAbsIndexed,
nextAddrZeroPage,
nextAddrZPIndexed,
nextAddrStack,
nextAddrRelative
);
signal nextAddr : nextAddrDef;
signal myAddrNext : unsigned(15 downto 0); -- DMB Lookahead output
signal myAddr : unsigned(15 downto 0);
signal myAddrIncr : unsigned(15 downto 0);
signal myAddrIncrH : unsigned(7 downto 0);
signal myAddrDecrH : unsigned(7 downto 0);
signal theWeNext : std_logic; -- DMB Lookahead output
signal theWe : std_logic;
signal irqActive : std_logic;
-- Output register
signal doNext : unsigned(7 downto 0); -- DMB Lookahead output
signal doReg : unsigned(7 downto 0);
-- Buffer register
signal T : unsigned(7 downto 0);
-- General registers
signal A: unsigned(7 downto 0); -- Accumulator
signal X: unsigned(7 downto 0); -- Index X
signal Y: unsigned(7 downto 0); -- Index Y
signal S: unsigned(7 downto 0); -- stack pointer
-- Status register
signal C: std_logic; -- Carry
signal Z: std_logic; -- Zero flag
signal I: std_logic; -- Interrupt flag
signal D: std_logic; -- Decimal mode
signal B: std_logic; -- Break software interrupt
signal R: std_logic; -- always 1
signal V: std_logic; -- Overflow
signal N: std_logic; -- Negative
-- ALU
-- ALU input
signal aluInput : unsigned(7 downto 0);
signal aluCmpInput : unsigned(7 downto 0);
-- ALU output
signal aluRegisterOut : unsigned(7 downto 0);
signal aluRmwOut : unsigned(7 downto 0);
signal aluC : std_logic;
signal aluZ : std_logic;
signal aluV : std_logic;
signal aluN : std_logic;
-- Indexing
signal indexOut : unsigned(8 downto 0);
signal realbrk : std_logic;
begin
processAluInput: process(clk, opcInfo, A, X, Y, T, S)
variable temp : unsigned(7 downto 0);
begin
temp := (others => '1');
if opcInfo(opcInA) = '1' then
temp := temp and A;
end if;
if opcInfo(opcInX) = '1' then
temp := temp and X;
end if;
if opcInfo(opcInY) = '1' then
temp := temp and Y;
end if;
if opcInfo(opcInS) = '1' then
temp := temp and S;
end if;
if opcInfo(opcInT) = '1' then
temp := temp and T;
end if;
if opcInfo(opcInBrk) = '1' then
temp := temp and "11100111"; -- also DMB clear D (bit 3)
end if;
if opcInfo(opcInClear) = '1' then
temp := (others => '0');
end if;
aluInput <= temp;
end process;
processCmpInput: process(clk, opcInfo, A, X, Y)
variable temp : unsigned(7 downto 0);
begin
temp := (others => '1');
if opcInfo(opcInCmp) = '1' then
temp := temp and A;
end if;
if opcInfo(opcInCpx) = '1' then
temp := temp and X;
end if;
if opcInfo(opcInCpy) = '1' then
temp := temp and Y;
end if;
aluCmpInput <= temp;
end process;
-- ALU consists of two parts
-- Read-Modify-Write or index instructions: INC/DEC/ASL/LSR/ROR/ROL
-- Accumulator instructions: ADC, SBC, EOR, AND, EOR, ORA
-- Some instructions are both RMW and accumulator so for most
-- instructions the rmw results are routed through accu alu too.
-- The B flag
------------
--No actual "B" flag exists inside the 6502's processor status register. The B
--flag only exists in the status flag byte pushed to the stack. Naturally,
--when the flags are restored (via PLP or RTI), the B bit is discarded.
--
--Depending on the means, the B status flag will be pushed to the stack as
--either 0 or 1.
--
--software instructions BRK & PHP will push the B flag as being 1.
--hardware interrupts IRQ & NMI will push the B flag as being 0.
processAlu: process(clk, opcInfo, aluInput, aluCmpInput, A, T, irqActive, N, V, R, D, I, Z, C)
variable lowBits: unsigned(5 downto 0);
variable nineBits: unsigned(8 downto 0);
variable rmwBits: unsigned(8 downto 0);
variable tsxBits: unsigned(8 downto 0);
variable varC : std_logic;
variable varZ : std_logic;
variable varV : std_logic;
variable varN : std_logic;
begin
lowBits := (others => '-');
nineBits := (others => '-');
rmwBits := (others => '-');
tsxBits := (others => '-');
R <= '1';
-- Shift unit
case opcInfo(aluMode1From to aluMode1To) is
when aluModeInp => rmwBits := C & aluInput;
when aluModeP => rmwBits := C & N & V & R & (not irqActive) & D & I & Z & C; -- irqActive
when aluModeInc => rmwBits := C & (aluInput + 1);
when aluModeDec => rmwBits := C & (aluInput - 1);
when aluModeAsl => rmwBits := aluInput & "0";
when aluModeTSB => rmwBits := "0" & (aluInput(7 downto 0) or A); -- added by alan for 65c02
tsxBits := "0" & (aluInput(7 downto 0) and A);
when aluModeTRB => rmwBits := "0" & (aluInput(7 downto 0) and (not A)); -- added by alan for 65c02
tsxBits := "0" & (aluInput(7 downto 0) and A);
when aluModeFlg => rmwBits := aluInput(0) & aluInput;
when aluModeLsr => rmwBits := aluInput(0) & "0" & aluInput(7 downto 1);
when aluModeRol => rmwBits := aluInput & C;
when aluModeRoR => rmwBits := aluInput(0) & C & aluInput(7 downto 1);
when others => rmwBits := C & aluInput;
end case;
-- ALU
case opcInfo(aluMode2From to aluMode2To) is
when aluModeAdc => lowBits := ("0" & A(3 downto 0) & rmwBits(8)) + ("0" & rmwBits(3 downto 0) & "1");
ninebits := ("0" & A) + ("0" & rmwBits(7 downto 0)) + (B"00000000" & rmwBits(8));
when aluModeSbc => lowBits := ("0" & A(3 downto 0) & rmwBits(8)) + ("0" & (not rmwBits(3 downto 0)) & "1");
ninebits := ("0" & A) + ("0" & (not rmwBits(7 downto 0))) + (B"00000000" & rmwBits(8));
when aluModeCmp => ninebits := ("0" & aluCmpInput) + ("0" & (not rmwBits(7 downto 0))) + "000000001";
when aluModeAnd => ninebits := rmwBits(8) & (A and rmwBits(7 downto 0));
when aluModeEor => ninebits := rmwBits(8) & (A xor rmwBits(7 downto 0));
when aluModeOra => ninebits := rmwBits(8) & (A or rmwBits(7 downto 0));
when aluModeNoF => ninebits := "000110000";
when others => ninebits := rmwBits;
end case;
varV := aluInput(6); -- Default for BIT / PLP / RTI
if (opcInfo(aluMode1From to aluMode1To) = aluModeFlg) then
varZ := rmwBits(1);
elsif (opcInfo(aluMode1From to aluMode1To) = aluModeTSB) or (opcInfo(aluMode1From to aluMode1To) = aluModeTRB) then
if tsxBits(7 downto 0) = X"00" then
varZ := '1';
else
varZ := '0';
end if;
elsif ninebits(7 downto 0) = X"00" then
varZ := '1';
else
varZ := '0';
end if;
if (opcInfo(aluMode1From to aluMode1To) = aluModeBit) or (opcInfo(aluMode1From to aluMode1To) = aluModeFlg) then
varN := rmwBits(7);
else
varN := nineBits(7);
end if;
varC := ninebits(8);
case opcInfo(aluMode2From to aluMode2To) is
-- Flags Affected: n v — — — — z c
-- n Set if most significant bit of result is set; else cleared.
-- v Set if signed overflow; cleared if valid signed result.
-- z Set if result is zero; else cleared.
-- c Set if unsigned overflow; cleared if valid unsigned result
when aluModeAdc =>
-- decimal mode low bits correction, is done after setting Z flag.
if D = '1' then
if lowBits(5 downto 1) > 9 then
ninebits(3 downto 0) := ninebits(3 downto 0) + 6;
if lowBits(5) = '0' then
ninebits(8 downto 4) := ninebits(8 downto 4) + 1;
end if;
end if;
end if;
when others => null;
end case;
case opcInfo(aluMode2From to aluMode2To) is
when aluModeAdc =>
-- decimal mode high bits correction, is done after setting Z and N flags
varV := (A(7) xor ninebits(7)) and (rmwBits(7) xor ninebits(7));
if D = '1' then
if ninebits(8 downto 4) > 9 then
ninebits(8 downto 4) := ninebits(8 downto 4) + 6;
varC := '1';
end if;
end if;
when aluModeSbc =>
varV := (A(7) xor ninebits(7)) and ((not rmwBits(7)) xor ninebits(7));
if D = '1' then
-- Check for borrow (lower 4 bits)
if lowBits(5) = '0' then
ninebits(7 downto 0) := ninebits(7 downto 0) - 6;
end if;
-- Check for borrow (upper 4 bits)
if ninebits(8) = '0' then
ninebits(8 downto 4) := ninebits(8 downto 4) - 6;
end if;
end if;
when others => null;
end case;
-- fix n and z flag for 65c02 adc sbc instructions in decimal mode
case opcInfo(aluMode2From to aluMode2To) is
when aluModeAdc =>
if D = '1' then
if ninebits(7 downto 0) = X"00" then
varZ := '1';
else
varZ := '0';
end if;
varN := ninebits(7);
end if;
when aluModeSbc =>
if D = '1' then
if ninebits(7 downto 0) = X"00" then
varZ := '1';
else
varZ := '0';
end if;
varN := ninebits(7);
end if;
when others => null;
end case;
-- DMB Remove Pipelining
-- if rising_edge(clk) then
aluRmwOut <= rmwBits(7 downto 0);
aluRegisterOut <= ninebits(7 downto 0);
aluC <= varC;
aluZ <= varZ;
aluV <= varV;
aluN <= varN;
-- end if;
end process;
calcInterrupt: process(clk)
begin
if rising_edge(clk) then
if enable = '1' then
if theCpuCycle = cycleStack4 or reset = '0' then
nmiReg <= '1';
end if;
if nextCpuCycle /= cycleBranchTaken and nextCpuCycle /= opcodeFetch then
irqReg <= irq_n;
nmiEdge <= nmi_n;
if (nmiEdge = '1') and (nmi_n = '0') then
nmiReg <= '0';
end if;
end if;
-- The 'or opcInfo(opcSetI)' prevents NMI immediately after BRK or IRQ.
-- Presumably this is done in the real 6502/6510 to prevent a double IRQ.
processIrq <= not ((nmiReg and (irqReg or I)) or opcInfo(opcIRQ));
end if;
end if;
end process;
--pipeirq: process(clk)
-- begin
-- if rising_edge(clk) then
-- if enable = '1' then
-- if (reset = '0') or (theCpuCycle = opcodeFetch) then
-- -- The 'or opcInfo(opcSetI)' prevents NMI immediately after BRK or IRQ.
-- -- Presumably this is done in the real 6502/6510 to prevent a double IRQ.
-- processIrq <= not ((nmiReg and (irqReg or I)) or opcInfo(opcIRQ));
-- end if;
-- end if;
-- end if;
-- end process;
calcNextOpcode: process(clk, di, reset, processIrq)
variable myNextOpcode : unsigned(7 downto 0);
begin
-- Next opcode is read from input unless a reset or IRQ is pending.
myNextOpcode := di;
if reset = '0' then
myNextOpcode := X"4C";
elsif processIrq = '1' then
myNextOpcode := X"00";
end if;
nextOpcode <= myNextOpcode;
end process;
nextOpcInfo <= opcodeInfoTable(to_integer(nextOpcode));
-- Read bits and flags from opcodeInfoTable and store in opcInfo.
-- This info is used to control the execution of the opcode.
calcOpcInfo: process(clk)
begin
if rising_edge(clk) then
if enable = '1' then
if (reset = '0') or (theCpuCycle = opcodeFetch) then
opcInfo <= nextOpcInfo;
end if;
end if;
end if;
end process;
calcTheOpcode: process(clk)
begin
if rising_edge(clk) then
if enable = '1' then
if theCpuCycle = opcodeFetch then
irqActive <= '0';
if processIrq = '1' then
irqActive <= '1';
end if;
-- Fetch opcode
theOpcode <= nextOpcode;
end if;
end if;
end if;
end process;
-- -----------------------------------------------------------------------
-- State machine
-- -----------------------------------------------------------------------
process(enable, theCpuCycle, opcInfo)
begin
updateRegisters <= false;
if enable = '1' then
if opcInfo(opcRti) = '1' then
if theCpuCycle = cycleRead then
updateRegisters <= true;
end if;
elsif theCpuCycle = opcodeFetch then
updateRegisters <= true;
end if;
end if;
end process;
process(clk)
begin
if rising_edge(clk) then
if enable = '1' then
theCpuCycle <= nextCpuCycle;
end if;
if reset = '0' then
theCpuCycle <= cycle2;
end if;
end if;
end process;
-- Determine the next cpu cycle. After the last cycle we always
-- go to opcodeFetch to get the next opcode.
calcNextCpuCycle: process(theCpuCycle, opcInfo, theOpcode, indexOut, T, N, V, C, Z)
begin
nextCpuCycle <= opcodeFetch;
case theCpuCycle is
when opcodeFetch => nextCpuCycle <= cycle2;
when cycle2 => if opcInfo(opcBranch) = '1' then
if (N = theOpcode(5) and theOpcode(7 downto 6) = "00")
or (V = theOpcode(5) and theOpcode(7 downto 6) = "01")
or (C = theOpcode(5) and theOpcode(7 downto 6) = "10")
or (Z = theOpcode(5) and theOpcode(7 downto 6) = "11")
or (theOpcode(7 downto 0) = x"80") then -- Branch condition is true
nextCpuCycle <= cycleBranchTaken;
end if;
elsif (opcInfo(opcStackUp) = '1') then
nextCpuCycle <= cycleStack1;
elsif opcInfo(opcStackAddr) = '1' and opcInfo(opcStackData) = '1' then
nextCpuCycle <= cycleStack2;
elsif opcInfo(opcStackAddr) = '1' then
nextCpuCycle <= cycleStack1;
elsif opcInfo(opcStackData) = '1' then
nextCpuCycle <= cycleWrite;
elsif opcInfo(opcAbsolute) = '1' then
nextCpuCycle <= cycle3;
elsif opcInfo(opcIndirect) = '1' then
if opcInfo(indexX) = '1' then
nextCpuCycle <= cyclePreIndirect;
else
nextCpuCycle <= cycleIndirect;
end if;
elsif opcInfo(opcZeroPage) = '1' then
if opcInfo(opcWrite) = '1' then
if (opcInfo(indexX) = '1') or (opcInfo(indexY) = '1') then
nextCpuCycle <= cyclePreWrite;
else
nextCpuCycle <= cycleWrite;
end if;
else
if (opcInfo(indexX) = '1') or (opcInfo(indexY) = '1') then
nextCpuCycle <= cyclePreRead;
else
nextCpuCycle <= cycleRead2;
end if;
end if;
elsif opcInfo(opcJump) = '1' then
nextCpuCycle <= cycleJump;
end if;
when cycle3 => nextCpuCycle <= cycleRead;
if opcInfo(opcWrite) = '1' then
if (opcInfo(indexX) = '1') or (opcInfo(indexY) = '1') then
nextCpuCycle <= cyclePreWrite;
else
nextCpuCycle <= cycleWrite;
end if;
end if;
if (opcInfo(opcIndirect) = '1') and (opcInfo(indexX) = '1') then
if opcInfo(opcWrite) = '1' then
nextCpuCycle <= cycleWrite;
else
nextCpuCycle <= cycleRead2;
end if;
end if;
when cyclePreIndirect => nextCpuCycle <= cycleIndirect;
when cycleIndirect => nextCpuCycle <= cycle3;
when cycleBranchTaken => if indexOut(8) /= T(7) then
nextCpuCycle <= cycleBranchPage;
end if;
when cyclePreRead => if opcInfo(opcZeroPage) = '1' then
nextCpuCycle <= cycleRead2;
end if;
when cycleRead =>
if opcInfo(opcJump) = '1' then
nextCpuCycle <= cycleJump;
elsif indexOut(8) = '1' then
nextCpuCycle <= cycleRead2;
elsif opcInfo(opcRmw) = '1' then
nextCpuCycle <= cycleRmw;
if opcInfo(indexX) = '1' or opcInfo(indexY) = '1' then
nextCpuCycle <= cycleRead2;
end if;
end if;
when cycleRead2 => if opcInfo(opcRmw) = '1' then
nextCpuCycle <= cycleRmw;
end if;
when cycleRmw => nextCpuCycle <= cycleWrite;
when cyclePreWrite => nextCpuCycle <= cycleWrite;
when cycleStack1 => nextCpuCycle <= cycleRead;
if opcInfo(opcStackAddr) = '1' then
nextCpuCycle <= cycleStack2;
end if;
when cycleStack2 => nextCpuCycle <= cycleStack3;
if opcInfo(opcRti) = '1' then
nextCpuCycle <= cycleRead;
end if;
if opcInfo(opcStackData) = '0' and opcInfo(opcStackUp) = '1' then
nextCpuCycle <= cycleJump;
end if;
when cycleStack3 => nextCpuCycle <= cycleRead;
if opcInfo(opcStackData) = '0' or opcInfo(opcStackUp) = '1' then
nextCpuCycle <= cycleJump;
elsif opcInfo(opcStackAddr) = '1' then
nextCpuCycle <= cycleStack4;
end if;
when cycleStack4 => nextCpuCycle <= cycleRead;
when cycleJump => if opcInfo(opcIncrAfter) = '1' then
nextCpuCycle <= cycleEnd;
end if;
when others => null;
end case;
end process;
-- -----------------------------------------------------------------------
-- T register
-- -----------------------------------------------------------------------
calcT: process(clk)
begin
if rising_edge(clk) then
if enable = '1' then
case theCpuCycle is
when cycle2 => T <= di;
when cycleStack1 | cycleStack2 =>
if opcInfo(opcStackUp) = '1' then
if theOpcode = x"28" or theOpcode = x"40" then -- plp or rti pulling the flags off the stack
T <= (di or "00110000"); -- Read from stack
else
T <= di;
end if;
end if;
when cycleIndirect | cycleRead | cycleRead2 => T <= di;
when others => null;
end case;
end if;
end if;
end process;
-- -----------------------------------------------------------------------
-- A register
-- -----------------------------------------------------------------------
process(clk)
begin
if rising_edge(clk) then
if updateRegisters then
if opcInfo(opcUpdateA) = '1' then
A <= aluRegisterOut;
end if;
end if;
end if;
end process;
-- -----------------------------------------------------------------------
-- X register
-- -----------------------------------------------------------------------
process(clk)
begin
if rising_edge(clk) then
if updateRegisters then
if opcInfo(opcUpdateX) = '1' then
X <= aluRegisterOut;
end if;
end if;
end if;
end process;
-- -----------------------------------------------------------------------
-- Y register
-- -----------------------------------------------------------------------
process(clk)
begin
if rising_edge(clk) then
if updateRegisters then
if opcInfo(opcUpdateY) = '1' then
Y <= aluRegisterOut;
end if;
end if;
end if;
end process;
-- -----------------------------------------------------------------------
-- C flag
-- -----------------------------------------------------------------------
process(clk)
begin
if rising_edge(clk) then
if updateRegisters then
if opcInfo(opcUpdateC) = '1' then
C <= aluC;
end if;
end if;
end if;
end process;
-- -----------------------------------------------------------------------
-- Z flag
-- -----------------------------------------------------------------------
process(clk)
begin
if rising_edge(clk) then
if updateRegisters then
if opcInfo(opcUpdateZ) = '1' then
Z <= aluZ;
end if;
end if;
end if;
end process;
-- -----------------------------------------------------------------------
-- I flag interupt flag
-- -----------------------------------------------------------------------
process(clk, reset)
begin
if reset = '0' then
I <= '1';
elsif rising_edge(clk) then
if updateRegisters then
if opcInfo(opcUpdateI) = '1' then
I <= aluInput(2);
end if;
end if;
end if;
end process;
-- -----------------------------------------------------------------------
-- D flag
-- -----------------------------------------------------------------------
process(clk, reset)
begin
if reset = '0' then
D <= '0';
elsif rising_edge(clk) then
if updateRegisters then
if opcInfo(opcUpdateD) = '1' then
D <= aluInput(3);
end if;
end if;
end if;
end process;
-- -----------------------------------------------------------------------
-- V flag
-- -----------------------------------------------------------------------
process(clk)
begin
if rising_edge(clk) then
if updateRegisters then
if opcInfo(opcUpdateV) = '1' then
V <= aluV;
end if;
end if;
end if;
end process;
-- -----------------------------------------------------------------------
-- N flag
-- -----------------------------------------------------------------------
process(clk)
begin
if rising_edge(clk) then
if updateRegisters then
if opcInfo(opcUpdateN) = '1' then
N <= aluN;
end if;
end if;
end if;
end process;
-- -----------------------------------------------------------------------
-- Stack pointer
-- -----------------------------------------------------------------------
process(clk)
variable sIncDec : unsigned(7 downto 0);
variable updateFlag : boolean;
begin
if rising_edge(clk) then
if opcInfo(opcStackUp) = '1' then
sIncDec := S + 1;
else
sIncDec := S - 1;
end if;
if enable = '1' then
updateFlag := false;
case nextCpuCycle is
when cycleStack1 =>
if (opcInfo(opcStackUp) = '1') or (opcInfo(opcStackData) = '1') then
updateFlag := true;
end if;
when cycleStack2 => updateFlag := true;
when cycleStack3 => updateFlag := true;
when cycleStack4 => updateFlag := true;
when cycleRead => if opcInfo(opcRti) = '1' then
updateFlag := true;
end if;
when cycleWrite => if opcInfo(opcStackData) = '1' then
updateFlag := true;
end if;
when others => null;
end case;
if updateFlag then
S <= sIncDec;
end if;
end if;
if updateRegisters then
if opcInfo(opcUpdateS) = '1' then
S <= aluRegisterOut;
end if;
end if;
end if;
end process;
-- -----------------------------------------------------------------------
-- Data out
-- -----------------------------------------------------------------------
calcDoComb: process(nextCpuCycle, aluRmwOut, opcInfo(opcIRQ), irqActive, myAddrIncr, PC, di)
begin
doNext <= aluRmwOut;
case nextCpuCycle is
when cycleStack2 => if opcInfo(opcIRQ) = '1' and irqActive = '0' then
doNext <= myAddrIncr(15 downto 8);
else
doNext <= PC(15 downto 8);
end if;
when cycleStack3 => doNext <= PC(7 downto 0);
when cycleRmw => doNext <= di; -- Read-modify-write write old value first.
when others => null;
end case;
end process;
-- DMB Lookahead data output
do_next <= doNext when enable = '1' else DoReg;
calcDoReg: process(clk)
begin
if rising_edge(clk) then
if enable = '1' then
doReg <= doNext;
end if;
end if;
end process;
-- DMB Registered data output
do <= doReg;
-- -----------------------------------------------------------------------
-- Write enable
-- -----------------------------------------------------------------------
calcWeComb: process(nextCpuCycle, opcInfo(opcStackUp), opcInfo(opcStackAddr), opcInfo(opcStackData))
begin
theWeNext <= '1';
case nextCpuCycle is
when cycleStack1 =>
if opcInfo(opcStackUp) = '0' and ((opcInfo(opcStackAddr) = '0') or (opcInfo(opcStackData) = '1')) then
theWeNext <= '0';
end if;
when cycleStack2 | cycleStack3 | cycleStack4 =>
if opcInfo(opcStackUp) = '0' then
theWeNext <= '0';
end if;
when cycleRmw => theWeNext <= '0';
when cycleWrite => theWeNext <= '0';
when others => null;
end case;
end process;
-- DMB Lookahead we output
nwe_next <= theWeNext when enable = '1' else theWe;
calcWeReg: process(clk)
begin
if rising_edge(clk) then
if enable = '1' then
theWe <= theWeNext;
end if;
end if;
end process;
-- DMB Registered we output
nwe <= theWe;
-- -----------------------------------------------------------------------
-- Program counter
-- -----------------------------------------------------------------------
calcPC: process(clk)
begin
if rising_edge(clk) then
if enable = '1' then
case theCpuCycle is
when opcodeFetch => PC <= myAddr;
when cycle2 => if irqActive = '0' then
if opcInfo(opcSecondByte) = '1' then
PC <= myAddrIncr;
else
PC <= myAddr;
end if;
end if;
when cycle3 => if opcInfo(opcAbsolute) = '1' then
PC <= myAddrIncr;
end if;
when others => null;
end case;
end if;
end if;
end process;
-- -----------------------------------------------------------------------
-- Address generation
-- -----------------------------------------------------------------------
calcNextAddr: process(theCpuCycle, opcInfo, indexOut, T, reset)
begin
nextAddr <= nextAddrIncr;
case theCpuCycle is
when cycle2 => if opcInfo(opcStackAddr) = '1' or opcInfo(opcStackData) = '1' then
nextAddr <= nextAddrStack;
elsif opcInfo(opcAbsolute) = '1' then
nextAddr <= nextAddrIncr;
elsif opcInfo(opcZeroPage) = '1' then
nextAddr <= nextAddrZeroPage;
elsif opcInfo(opcIndirect) = '1' then
nextAddr <= nextAddrZeroPage;
elsif opcInfo(opcSecondByte) = '1' then
nextAddr <= nextAddrIncr;
else
nextAddr <= nextAddrHold;
end if;
when cycle3 => if (opcInfo(opcIndirect) = '1') and (opcInfo(indexX) = '1') then
nextAddr <= nextAddrAbs;
else
nextAddr <= nextAddrAbsIndexed;
end if;
when cyclePreIndirect => nextAddr <= nextAddrZPIndexed;
when cycleIndirect => nextAddr <= nextAddrIncrL;
when cycleBranchTaken => nextAddr <= nextAddrRelative;
when cycleBranchPage => if T(7) = '0' then
nextAddr <= nextAddrIncrH;
else
nextAddr <= nextAddrDecrH;
end if;
when cyclePreRead => nextAddr <= nextAddrZPIndexed;
when cycleRead => nextAddr <= nextAddrPc;
if opcInfo(opcJump) = '1' then
-- Emulate 6510 bug, jmp(xxFF) fetches from same page.
-- Replace with nextAddrIncr if emulating 65C02 or later cpu.
nextAddr <= nextAddrIncr;
--nextAddr <= nextAddrIncrL;
elsif indexOut(8) = '1' then
nextAddr <= nextAddrIncrH;
elsif opcInfo(opcRmw) = '1' then
nextAddr <= nextAddrHold;
end if;
when cycleRead2 => nextAddr <= nextAddrPc;
if opcInfo(opcRmw) = '1' then
nextAddr <= nextAddrHold;
end if;
when cycleRmw => nextAddr <= nextAddrHold;
when cyclePreWrite => nextAddr <= nextAddrHold;
if opcInfo(opcZeroPage) = '1' then
nextAddr <= nextAddrZPIndexed;
elsif indexOut(8) = '1' then
nextAddr <= nextAddrIncrH;
end if;
when cycleWrite => nextAddr <= nextAddrPc;
when cycleStack1 => nextAddr <= nextAddrStack;
when cycleStack2 => nextAddr <= nextAddrStack;
when cycleStack3 => nextAddr <= nextAddrStack;
if opcInfo(opcStackData) = '0' then
nextAddr <= nextAddrPc;
end if;
when cycleStack4 => nextAddr <= nextAddrIrq;
when cycleJump => nextAddr <= nextAddrAbs;
when others => null;
end case;
if reset = '0' then
nextAddr <= nextAddrReset;
end if;
end process;
indexAlu: process(opcInfo, myAddr, T, X, Y)
begin
if opcInfo(indexX) = '1' then
indexOut <= (B"0" & T) + (B"0" & X);
elsif opcInfo(indexY) = '1' then
indexOut <= (B"0" & T) + (B"0" & Y);
elsif opcInfo(opcBranch) = '1' then
indexOut <= (B"0" & T) + (B"0" & myAddr(7 downto 0));
else
indexOut <= B"0" & T;
end if;
end process;
calcAddrComb: process(myAddr, nextAddr, myAddrIncr, myAddrIncrH, myAddrDecrH, PC, nmiReg, di, theOpcode, indexOut, S, T, X)
begin
myAddrNext <= myAddr;
case nextAddr is
when nextAddrIncr => myAddrNext <= myAddrIncr;
when nextAddrIncrL => myAddrNext(7 downto 0) <= myAddrIncr(7 downto 0);
when nextAddrIncrH => myAddrNext(15 downto 8) <= myAddrIncrH;
when nextAddrDecrH => myAddrNext(15 downto 8) <= myAddrDecrH;
when nextAddrPc => myAddrNext <= PC;
when nextAddrIrq =>myAddrNext <= X"FFFE";
if nmiReg = '0' then
myAddrNext <= X"FFFA";
end if;
when nextAddrReset => myAddrNext <= X"FFFC";
when nextAddrAbs => myAddrNext <= di & T;
when nextAddrAbsIndexed =>--myAddrNext <= di & indexOut(7 downto 0);
if theOpcode = x"7C" then
myAddrNext <= (di & T) + (x"00"& X);
else
myAddrNext <= di & indexOut(7 downto 0);
end if;
when nextAddrZeroPage => myAddrNext <= "00000000" & di;
when nextAddrZPIndexed => myAddrNext <= "00000000" & indexOut(7 downto 0);
when nextAddrStack => myAddrNext <= "00000001" & S;
when nextAddrRelative => myAddrNext(7 downto 0) <= indexOut(7 downto 0);
when others => null;
end case;
end process;
-- DMB Lookahead address output
addr_next <= myAddrNext when enable = '1' else myAddr;
calcAddrReg: process(clk)
begin
if rising_edge(clk) then
if enable = '1' then
myAddr <= myAddrNext;
end if;
end if;
end process;
myAddrIncr <= myAddr + 1;
myAddrIncrH <= myAddr(15 downto 8) + 1;
myAddrDecrH <= myAddr(15 downto 8) - 1;
-- DMB Registered address output
addr <= myAddr;
-- DMB This looked plain broken and inferred a latch
--
-- calcsync: process(clk)
-- begin
--
-- if enable = '1' then
-- case theCpuCycle is
-- when opcodeFetch => sync <= '1';
-- when others => sync <= '0';
-- end case;
-- end if;
-- end process;
sync <= '1' when theCpuCycle = opcodeFetch else '0';
sync_irq <= irqActive;
end architecture;
| gpl-3.0 | 9dda837d8ab69053c1cfe5761fa503fb | 0.55175 | 3.468509 | false | false | false | false |
Gizeta/bjuedc | uart-fpga/gen_div.vhd | 1 | 1,032 | --------------------------------------------
-- 通用偶数分频器
--------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity gen_div is
-- 分频因子, 分频为2*div_param, 默认2分频
generic(div_param : integer := 1);
port(
clk_in : in std_logic; -- 输入时钟
clk_out : out std_logic; -- 分频输出
reset : in std_logic -- 复位信号
);
end gen_div;
architecture arch of gen_div is
signal tmp : std_logic; -- 输出暂存寄存器
signal cnt : integer range 0 to div_param := 0; -- 计数寄存器
begin
process(clk_in, reset)
begin
if reset = '1' then -- reset有效时, output始终是0
cnt <= 0;
tmp <= '0';
elsif rising_edge(clk_in) then
cnt <= cnt + 1;
if cnt = div_param - 1 then
tmp <= not tmp; -- 取反信号
cnt <= 0;
end if;
end if;
end process;
clk_out <= tmp; -- 输出
end arch;
| mit | 83f412c079217a8b07bcf047e2416bab | 0.515152 | 2.709677 | false | false | false | false |
EliasLuiz/TCC | Leon3/lib/techmap/maps/cpu_disas_net.vhd | 1 | 4,563 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Package: cpu_disas_net
-- File: cpu_disas_net.vhd
-- Author: Jiri Gaisler, Gaisler Research
-- Description: SPARC disassembler according to SPARC V8 manual
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
-- pragma translate_off
library grlib;
use grlib.stdlib.all;
use grlib.sparc.all;
use grlib.sparc_disas.all;
-- pragma translate_on
entity cpu_disas_net is
port (
clk : in std_ulogic;
rstn : in std_ulogic;
dummy : out std_ulogic;
inst : in std_logic_vector(31 downto 0);
pc : in std_logic_vector(31 downto 2);
result: in std_logic_vector(31 downto 0);
index : in std_logic_vector(3 downto 0);
wreg : in std_ulogic;
annul : in std_ulogic;
holdn : in std_ulogic;
pv : in std_ulogic;
trap : in std_ulogic;
disas : in std_ulogic);
end;
architecture behav of cpu_disas_net is
begin
dummy <= '1';
-- pragma translate_off
trc : process(clk)
variable valid : boolean;
variable op : std_logic_vector(1 downto 0);
variable op3 : std_logic_vector(5 downto 0);
variable fpins, fpld : boolean;
variable iindex : integer;
begin
iindex := conv_integer(index);
op := inst(31 downto 30); op3 := inst(24 downto 19);
fpins := (op = FMT3) and ((op3 = FPOP1) or (op3 = FPOP2));
fpld := (op = LDST) and ((op3 = LDF) or (op3 = LDDF) or (op3 = LDFSR));
valid := (((not annul) and pv) = '1') and (not ((fpins or fpld) and (trap = '0')));
valid := valid and (holdn = '1');
if rising_edge(clk) and (rstn = '1') and (disas = '1') then
print_insn (iindex, pc(31 downto 2) & "00", inst,
result, valid, trap = '1', wreg = '1'
);
end if;
end process;
-- pragma translate_on
end;
library ieee;
use ieee.std_logic_1164.all;
-- pragma translate_off
library grlib;
use grlib.stdlib.all;
use grlib.sparc.all;
use grlib.sparc_disas.all;
-- pragma translate_on
entity fpu_disas_net is
port (
clk : in std_ulogic;
rstn : in std_ulogic;
dummy : out std_ulogic;
wr2inst : in std_logic_vector(31 downto 0);
wr2pc : in std_logic_vector(31 downto 2);
divinst : in std_logic_vector(31 downto 0);
divpc : in std_logic_vector(31 downto 2);
dbg_wrdata: in std_logic_vector(63 downto 0);
index : in std_logic_vector(3 downto 0);
dbg_wren : in std_logic_vector(1 downto 0);
resv : in std_ulogic;
ld : in std_ulogic;
rdwr : in std_ulogic;
ccwr : in std_ulogic;
rdd : in std_ulogic;
div_valid : in std_ulogic;
holdn : in std_ulogic;
disas : in std_ulogic);
end;
architecture behav of fpu_disas_net is
begin
dummy <= '1';
-- pragma translate_off
trc : process(clk)
variable valid : boolean;
variable op : std_logic_vector(1 downto 0);
variable op3 : std_logic_vector(5 downto 0);
variable fpins, fpld : boolean;
variable iindex : integer;
begin
iindex := conv_integer(index);
if rising_edge(clk) and (rstn = '1') and (disas /= '0') then
valid := ((((rdwr and not ld) or ccwr or (ld and resv)) and holdn) = '1');
print_fpinsn(0, wr2pc(31 downto 2) & "00", wr2inst, dbg_wrdata,
(rdd = '1'), valid, false, (dbg_wren /= "00"));
print_fpinsn(0, divpc(31 downto 2) & "00", divinst, dbg_wrdata,
(rdd = '1'), (div_valid and holdn) = '1', false, (dbg_wren /= "00"));
end if;
end process;
-- pragma translate_on
end;
| gpl-3.0 | 1f1b61a5dc0281589050685b52305f1a | 0.605961 | 3.443774 | false | false | false | false |
yishinli/emc2 | src/hal/drivers/m5i20/hostmot5_src/indexreg.vhd | 1 | 869 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity indexreg is
port (
clk: in STD_LOGIC;
ibus: in STD_LOGIC_VECTOR (15 downto 0);
obus: out STD_LOGIC_VECTOR (15 downto 0);
loadindex: in STD_LOGIC;
readindex: in STD_LOGIC;
index: out STD_LOGIC_VECTOR (7 downto 0)
);
end indexreg;
architecture behavioral of indexreg is
signal indexreg: STD_LOGIC_VECTOR (7 downto 0);
begin
aindexreg: process(clk,
ibus,
loadindex,
readindex,
indexreg
)
begin
if clk'event and clk = '1' then
if loadindex = '1' then
indexreg <= ibus(7 downto 0);
end if;
end if;
if readindex = '1' then
obus(7 downto 0) <= indexreg;
obus(15 downto 8) <= "ZZZZZZZZ";
else
obus <= "ZZZZZZZZZZZZZZZZ";
end if;
index <= indexreg;
end process;
end behavioral;
| lgpl-2.1 | 3ea2387ef559b08e720ccc1bb2c6be8d | 0.60069 | 3.038462 | false | false | false | false |
EliasLuiz/TCC | Leon3/designs/leon3-arrow-bemicro-sdk/testbench.vhd | 1 | 7,311 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
-- LEON3 BeMicro SDK design testbench
-- Copyright (C) 2011 - 2013 Aeroflex Gaisler
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library gaisler;
use gaisler.sim.all;
library techmap;
use techmap.gencomp.all;
use work.config.all; -- configuration
entity testbench is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
clktech : integer := CFG_CLKTECH;
ncpu : integer := CFG_NCPU;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW;
clkperiod : integer := 20 -- system clock period
);
end;
architecture behav of testbench is
constant promfile : string := "prom.srec"; -- rom contents
constant sramfile : string := "ram.srec"; -- ram contents
constant sdramfile : string := "ram.srec"; -- sdram contents
constant ct : integer := clkperiod/2;
signal cpu_rst_n : std_ulogic := '0';
signal clk_fpga_50m : std_ulogic := '0';
-- DDR SDRAM
signal ram_a : std_logic_vector (13 downto 0); -- ddr address
signal ram_ck_p : std_logic;
signal ram_ck_n : std_logic;
signal ram_cke : std_logic;
signal ram_cs_n : std_logic;
signal ram_ws_n : std_ulogic; -- ddr write enable
signal ram_ras_n : std_ulogic; -- ddr ras
signal ram_cas_n : std_ulogic; -- ddr cas
signal ram_dm : std_logic_vector(1 downto 0); -- ram_udm & ram_ldm
signal ram_dqs : std_logic_vector (1 downto 0); -- ram_udqs & ram_lqds
signal ram_ba : std_logic_vector (1 downto 0); -- ddr bank address
signal ram_d : std_logic_vector (15 downto 0); -- ddr data
-- Ethernet PHY
signal txd : std_logic_vector(3 downto 0);
signal rxd : std_logic_vector(3 downto 0);
signal tx_clk : std_logic;
signal rx_clk : std_logic;
signal tx_en : std_logic;
signal rx_dv : std_logic;
signal eth_crs : std_logic;
signal rx_er : std_logic;
signal eth_col : std_logic;
signal mdio : std_logic;
signal mdc : std_logic;
signal eth_reset_n : std_logic;
-- Temperature sensor
signal temp_sc : std_logic;
signal temp_cs_n : std_logic;
signal temp_sio : std_logic;
-- LEDs
signal f_led : std_logic_vector(7 downto 0);
-- User push-button
signal pbsw_n : std_logic;
-- Reconfig SW1 and SW2
signal reconfig_sw : std_logic_vector(2 downto 1);
-- SD card interface
signal sd_dat0 : std_logic;
signal sd_dat1 : std_logic;
signal sd_dat2 : std_logic;
signal sd_dat3 : std_logic;
signal sd_cmd : std_logic;
signal sd_clk : std_logic;
-- Ethernet PHY sim model
signal phy_tx_er : std_ulogic;
signal phy_gtx_clk : std_ulogic;
signal txdt : std_logic_vector(7 downto 0) := (others => '0');
signal rxdt : std_logic_vector(7 downto 0) := (others => '0');
-- EPCS
signal epcs_data : std_ulogic;
signal epcs_dclk : std_ulogic;
signal epcs_csn : std_logic;
signal epcs_asdi : std_logic;
begin
-- clock and reset
clk_fpga_50m <= not clk_fpga_50m after ct * 1 ns;
cpu_rst_n <= '0', '1' after 200 ns;
-- Push button, connected to DSU break, kept high
pbsw_n <= 'H';
reconfig_sw <= (others => 'H');
-- LEON3 SoC
d3 : entity work.leon3mp
generic map (fabtech, memtech, padtech, clktech, ncpu, disas, dbguart, pclow)
port map (
cpu_rst_n, clk_fpga_50m,
-- DDR SDRAM
ram_a, ram_ck_p, ram_ck_n, ram_cke, ram_cs_n, ram_ws_n,
ram_ras_n, ram_cas_n, ram_dm, ram_dqs, ram_ba, ram_d,
-- Ethernet PHY
txd, rxd, tx_clk, rx_clk, tx_en, rx_dv, eth_crs, rx_er,
eth_col, mdio, mdc, eth_reset_n,
-- Temperature sensor
temp_sc, temp_cs_n, temp_sio,
-- LEDs
f_led,
-- User push-button
pbsw_n,
-- Reconfig SW1 and SW2
reconfig_sw,
-- SD card interface
sd_dat0, sd_dat1, sd_dat2, sd_dat3, sd_cmd, sd_clk,
-- EPCS
epcs_data, epcs_dclk, epcs_csn, epcs_asdi
);
-- SD card signals
spiflashmod0 : spi_flash
generic map (ftype => 3, debug => 0, dummybyte => 0)
port map (sck => sd_clk, di => sd_cmd, do => sd_dat0, csn => sd_dat3);
sd_dat0 <= 'Z'; sd_cmd <= 'Z';
-- EPCS
spi0: spi_flash
generic map (
ftype => 4, debug => 0, fname => promfile, readcmd => CFG_SPIMCTRL_READCMD,
dummybyte => CFG_SPIMCTRL_DUMMYBYTE, dualoutput => CFG_SPIMCTRL_DUALOUTPUT,
memoffset => CFG_SPIMCTRL_OFFSET)
port map (sck => epcs_dclk, di => epcs_asdi, do => epcs_data,
csn => epcs_csn, sd_cmd_timeout => open,
sd_data_timeout => open);
-- On the BeMicro the temp_* signals are connected to a temperature sensor
temp_sc <= 'H'; temp_sio <= 'H';
-- DDR memory
ddr0 : ddrram
generic map(width => 16, abits => 14, colbits => 10, rowbits => 13,
implbanks => 1, fname => sdramfile, density => 2)
port map (ck => ram_ck_p, cke => ram_cke, csn => ram_cs_n,
rasn => ram_ras_n, casn => ram_cas_n, wen => ram_ws_n,
dm => ram_dm, ba => ram_ba, a => ram_a, dq => ram_d,
dqs => ram_dqs);
-- Ethernet PHY
mdio <= 'H'; phy_tx_er <= '0'; phy_gtx_clk <= '0';
txdt(3 downto 0) <= txd; rxd <= rxdt(3 downto 0);
p0: phy
generic map(base1000_t_fd => 0, base1000_t_hd => 0, address => 1)
port map(eth_reset_n, mdio, tx_clk, rx_clk, rxdt, rx_dv,
rx_er, eth_col, eth_crs, txdt, tx_en, phy_tx_er, mdc,
phy_gtx_clk);
-- LEDs
f_led <= (others => 'H');
-- Processor error mode indicator is connected to led(6).
iuerr : process
begin
wait for 2500 ns;
if to_x01(f_led(6)) = '1' then wait on f_led(6); end if;
assert (to_x01(f_led(6)) = '1')
report "*** IU in error mode, simulation halted ***"
severity failure ;
end process;
end ;
| gpl-3.0 | b1d8c54509f3d678be7ea8d299027574 | 0.572699 | 3.421151 | false | false | false | false |
EliasLuiz/TCC | Leon3/designs/leon3-altera-ep2s60-sdr/testbench.vhd | 1 | 9,511 | ------------------------------------------------------------------------------
-- LEON3 Demonstration design test bench
-- Copyright (C) 2004 Jiri Gaisler, Gaisler Research
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library gaisler;
use gaisler.libdcom.all;
use gaisler.sim.all;
library techmap;
use techmap.gencomp.all;
library micron;
use micron.components.all;
use work.debug.all;
use work.config.all; -- configuration
entity testbench is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
clktech : integer := CFG_CLKTECH;
ncpu : integer := CFG_NCPU;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW;
clkperiod : integer := 20; -- system clock period
romwidth : integer := 8; -- rom data width (8/32)
romdepth : integer := 23; -- rom address depth
sramwidth : integer := 32; -- ram data width (8/16/32)
sramdepth : integer := 20; -- ram address depth
srambanks : integer := 1 -- number of ram banks
);
end;
architecture behav of testbench is
constant promfile : string := "prom.srec"; -- rom contents
constant sramfile : string := "ram.srec"; -- ram contents
constant sdramfile : string := "ram.srec"; -- sdram contents
signal clk : std_logic := '0';
signal clkout, pllref : std_ulogic;
signal Rst : std_logic := '0'; -- Reset
constant ct : integer := clkperiod/2;
signal address : std_logic_vector(23 downto 0);
signal data : std_logic_vector(31 downto 0);
signal ramsn : std_ulogic;
signal ramoen : std_ulogic;
signal rwen : std_ulogic;
signal mben : std_logic_vector(3 downto 0);
--signal rwenx : std_logic_vector(3 downto 0);
signal romsn : std_ulogic;
signal iosn : std_ulogic;
signal oen : std_ulogic;
--signal read : std_ulogic;
signal writen : std_ulogic;
signal brdyn : std_ulogic;
signal bexcn : std_ulogic;
signal wdog : std_ulogic;
signal dsuen, dsutx, dsurx, dsubren, dsuact : std_ulogic;
signal dsurst : std_ulogic;
signal test : std_ulogic;
signal error : std_logic;
signal gpio : std_logic_vector(CFG_GRGPIO_WIDTH-1 downto 0);
signal GND : std_ulogic := '0';
signal VCC : std_ulogic := '1';
signal NC : std_ulogic := 'Z';
signal clk2 : std_ulogic := '1';
signal sdcke : std_ulogic; -- clk en
signal sdcsn : std_ulogic; -- chip sel
signal sdwen : std_ulogic; -- write en
signal sdrasn : std_ulogic; -- row addr stb
signal sdcasn : std_ulogic; -- col addr stb
signal sddqm : std_logic_vector (3 downto 0); -- data i/o mask
signal sdclk : std_ulogic;
signal sdba : std_logic_vector(1 downto 0);
signal plllock : std_ulogic;
signal txd1, rxd1 : std_ulogic;
--signal txd2, rxd2 : std_ulogic;
-- for smc lan chip
signal eth_aen : std_ulogic; -- for smsc eth
signal eth_readn : std_ulogic; -- for smsc eth
signal eth_writen : std_ulogic; -- for smsc eth
signal eth_nbe : std_logic_vector(3 downto 0); -- for smsc eth
signal eth_datacsn : std_ulogic;
constant lresp : boolean := false;
signal sa : std_logic_vector(14 downto 0);
signal sd : std_logic_vector(31 downto 0);
begin
-- clock and reset
clk <= not clk after ct * 1 ns;
rst <= dsurst;
dsubren <= '1'; rxd1 <= '1';
d3 : entity work.leon3mp generic map (fabtech, memtech, padtech, clktech,
ncpu, disas, dbguart, pclow )
port map (rst, clk, error, address, data, ramsn, ramoen, rwen, mben, iosn,
romsn, oen, writen, open, open, sa(11 downto 0), sd, sdclk, sdcke,
sdcsn, sdwen, sdrasn, sdcasn, sddqm, sdba, dsutx, dsurx, dsubren,
dsuact, rxd1, txd1, eth_aen, eth_readn,
eth_writen, eth_nbe);
sd1 : if (CFG_MCTRL_SDEN = 1) and (CFG_MCTRL_SEPBUS = 1) generate
u0: mt48lc16m16a2 generic map (index => 0, fname => sdramfile)
PORT MAP(
Dq => sd(31 downto 16), Addr => sa(12 downto 0),
Ba => sdba, Clk => sdclk, Cke => sdcke,
Cs_n => sdcsn, Ras_n => sdrasn, Cas_n => sdcasn, We_n => sdwen,
Dqm => sddqm(3 downto 2));
u1: mt48lc16m16a2 generic map (index => 16, fname => sdramfile)
PORT MAP(
Dq => sd(15 downto 0), Addr => sa(12 downto 0),
Ba => sdba, Clk => sdclk, Cke => sdcke,
Cs_n => sdcsn, Ras_n => sdrasn, Cas_n => sdcasn, We_n => sdwen,
Dqm => sddqm(1 downto 0));
end generate;
-- 8 bit prom
prom0 : sram generic map (index => 6, abits => romdepth, fname => promfile)
port map (address(romdepth-1 downto 0), data(31 downto 24),
romsn, rwen, oen);
sram0 : for i in 0 to (sramwidth/8)-1 generate
sr0 : sram generic map (index => i, abits => sramdepth, fname => sramfile)
port map (address(sramdepth+1 downto 2), data(31-i*8 downto 24-i*8), ramsn,
rwen, ramoen);
end generate;
error <= 'H'; -- ERROR pull-up
iuerr : process
begin
wait for 2500 ns;
if to_x01(error) = '1' then wait on error; end if;
assert (to_x01(error) = '1')
report "*** IU in error mode, simulation halted ***"
severity failure ;
end process;
data <= buskeep(data), (others => 'H') after 250 ns;
sd <= buskeep(sd), (others => 'H') after 250 ns;
test0 : grtestmod
port map ( rst, clk, error, address(21 downto 2), data,
iosn, oen, writen, brdyn);
dsucom : process
procedure dsucfg(signal dsurx : in std_ulogic; signal dsutx : out std_ulogic) is
variable w32 : std_logic_vector(31 downto 0);
variable c8 : std_logic_vector(7 downto 0);
constant txp : time := 160 * 1 ns;
begin
dsutx <= '1';
dsurst <= '0';
wait for 500 ns;
dsurst <= '1';
wait;
wait for 5000 ns;
txc(dsutx, 16#55#, txp); -- sync uart
-- txc(dsutx, 16#c0#, txp);
-- txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp);
-- txa(dsutx, 16#00#, 16#00#, 16#02#, 16#ae#, txp);
-- txc(dsutx, 16#c0#, txp);
-- txa(dsutx, 16#91#, 16#00#, 16#00#, 16#00#, txp);
-- txa(dsutx, 16#00#, 16#00#, 16#06#, 16#ae#, txp);
-- txc(dsutx, 16#c0#, txp);
-- txa(dsutx, 16#90#, 16#00#, 16#00#, 16#24#, txp);
-- txa(dsutx, 16#00#, 16#00#, 16#06#, 16#03#, txp);
-- txc(dsutx, 16#c0#, txp);
-- txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
-- txa(dsutx, 16#00#, 16#00#, 16#06#, 16#fc#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#2f#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#91#, 16#00#, 16#00#, 16#00#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#6f#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#11#, 16#00#, 16#00#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#00#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#40#, 16#00#, 16#04#, txp);
txa(dsutx, 16#00#, 16#02#, 16#20#, 16#01#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#02#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#0f#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#40#, 16#00#, 16#43#, 16#10#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#0f#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#91#, 16#40#, 16#00#, 16#24#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#24#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#91#, 16#70#, 16#00#, 16#00#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#03#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
txa(dsutx, 16#00#, 16#00#, 16#ff#, 16#ff#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#40#, 16#00#, 16#48#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#12#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#40#, 16#00#, 16#60#, txp);
txa(dsutx, 16#00#, 16#00#, 16#12#, 16#10#, txp);
txc(dsutx, 16#80#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp);
rxi(dsurx, w32, txp, lresp);
txc(dsutx, 16#a0#, txp);
txa(dsutx, 16#40#, 16#00#, 16#00#, 16#00#, txp);
rxi(dsurx, w32, txp, lresp);
end;
begin
dsucfg(dsutx, dsurx);
wait;
end process;
end ;
| gpl-3.0 | 83fd377217167288af0bf6857040a8e6 | 0.582273 | 3.13998 | false | false | false | false |
hoglet67/CoPro6502 | src/T6502/T65.vhd | 1 | 21,852 | -- ****
-- T65(b) core. In an effort to merge and maintain bug fixes ....
--
-- Ver 303 ost(ML) July 2014
-- (Sorry for some scratchpad comments that may make little sense)
-- Mods and some 6502 undocumented instructions.
--
-- Not correct opcodes acc. to Lorenz tests (incomplete list):
-- NOPN (nop)
-- NOPZX (nop + byte 172)
-- NOPAX (nop + word da ... da: byte 0)
-- ASOZ (byte $07 + byte 172)
--
-- Wolfgang April 2014
-- Ver 303 Bugfixes for NMI from foft
-- Ver 302 Bugfix for BRK command
-- Wolfgang January 2014
-- Ver 301 more merging
-- Ver 300 Bugfixes by ehenciak added, started tidyup *bust*
-- MikeJ March 2005
-- Latest version from www.fpgaarcade.com (original www.opencores.org)
--
-- ****
--
-- 65xx compatible microprocessor core
--
-- Version : 0246
--
-- Copyright (c) 2002 Daniel Wallner ([email protected])
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
-- http://www.opencores.org/cvsweb.shtml/t65/
--
-- Limitations :
--
-- 65C02 and 65C816 modes are incomplete
-- Undocumented instructions are not supported
-- Some interface signals behaves incorrect
--
-- File history :
--
-- 0246 : First release
--
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.T65_Pack.all;
-- ehenciak 2-23-2005 : Added the enable signal so that one doesn't have to use
-- the ready signal to limit the CPU.
entity T65 is
port(
Mode : in std_logic_vector(1 downto 0); -- "00" => 6502, "01" => 65C02, "10" => 65C816
Res_n : in std_logic;
Enable : in std_logic;
Clk : in std_logic;
Rdy : in std_logic;
Abort_n : in std_logic;
IRQ_n : in std_logic;
NMI_n : in std_logic;
SO_n : in std_logic;
R_W_n : out std_logic;
Sync : out std_logic;
EF : out std_logic;
MF : out std_logic;
XF : out std_logic;
ML_n : out std_logic;
VP_n : out std_logic;
VDA : out std_logic;
VPA : out std_logic;
A : out std_logic_vector(23 downto 0);
DI : in std_logic_vector(7 downto 0);--NOTE:Make sure DI equals DO when writing. This is important for DCP/DCM undoc instruction. TODO:convert to inout
DO : out std_logic_vector(7 downto 0)
);
end T65;
architecture rtl of T65 is
-- Registers
signal ABC, X, Y, D : std_logic_vector(15 downto 0);
signal P, AD, DL : std_logic_vector(7 downto 0) := x"00";
signal PwithB : std_logic_vector(7 downto 0);--ML:New way to push P with correct B state to stack
signal BAH : std_logic_vector(7 downto 0);
signal BAL : std_logic_vector(8 downto 0);
signal PBR : std_logic_vector(7 downto 0);
signal DBR : std_logic_vector(7 downto 0);
signal PC : unsigned(15 downto 0);
signal S : unsigned(15 downto 0);
signal EF_i : std_logic;
signal MF_i : std_logic;
signal XF_i : std_logic;
signal IR : std_logic_vector(7 downto 0);
signal MCycle : std_logic_vector(2 downto 0);
signal Mode_r : std_logic_vector(1 downto 0);
signal ALU_Op_r : T_ALU_Op;
signal Write_Data_r : T_Write_Data;
signal Set_Addr_To_r : T_Set_Addr_To;
signal PCAdder : unsigned(8 downto 0);
signal RstCycle : std_logic;
signal IRQCycle : std_logic;
signal NMICycle : std_logic;
signal SO_n_o : std_logic;
signal IRQ_n_o : std_logic;
signal NMI_n_o : std_logic;
signal NMIAct : std_logic;
signal Break : std_logic;
-- ALU signals
signal BusA : std_logic_vector(7 downto 0);
signal BusA_r : std_logic_vector(7 downto 0);
signal BusB : std_logic_vector(7 downto 0);
signal ALU_Q : std_logic_vector(7 downto 0);
signal P_Out : std_logic_vector(7 downto 0);
-- Micro code outputs
signal LCycle : std_logic_vector(2 downto 0);
signal ALU_Op : T_ALU_Op;
signal Set_BusA_To : T_Set_BusA_To;
signal Set_Addr_To : T_Set_Addr_To;
signal Write_Data : T_Write_Data;
signal Jump : std_logic_vector(1 downto 0);
signal BAAdd : std_logic_vector(1 downto 0);
signal BreakAtNA : std_logic;
signal ADAdd : std_logic;
signal AddY : std_logic;
signal PCAdd : std_logic;
signal Inc_S : std_logic;
signal Dec_S : std_logic;
signal LDA : std_logic;
signal LDP : std_logic;
signal LDX : std_logic;
signal LDY : std_logic;
signal LDS : std_logic;
signal LDDI : std_logic;
signal LDALU : std_logic;
signal LDAD : std_logic;
signal LDBAL : std_logic;
signal LDBAH : std_logic;
signal SaveP : std_logic;
signal Write : std_logic;
signal ALUmore : std_logic;
signal really_rdy : std_logic;
signal R_W_n_i : std_logic;
signal R_W_n_i_d : std_logic;
signal NMIActClear : std_logic; -- MWW hack
begin
-- workaround for ready-handling
-- ehenciak : Drive R_W_n_i off chip.
R_W_n <= R_W_n_i;
-- ehenciak : gate Rdy with read/write to make an "OK, it's
-- really OK to stop the processor now if Rdy is
-- deasserted" signal
really_rdy <= Rdy or not(R_W_n_i);
----
Sync <= '1' when MCycle = "000" else '0';
EF <= EF_i;
MF <= MF_i;
XF <= XF_i;
ML_n <= '0' when IR(7 downto 6) /= "10" and IR(2 downto 1) = "11" and MCycle(2 downto 1) /= "00" else '1';
VP_n <= '0' when IRQCycle = '1' and (MCycle = "101" or MCycle = "110") else '1';
VDA <= '1' when Set_Addr_To_r /= Set_Addr_To_PBR else '0'; -- Incorrect !!!!!!!!!!!!
VPA <= '1' when Jump(1) = '0' else '0'; -- Incorrect !!!!!!!!!!!!
mcode : T65_MCode
port map(
--inputs
Mode => Mode_r,
IR => IR,
MCycle => MCycle,
P => P,
--outputs
LCycle => LCycle,
ALU_Op => ALU_Op,
Set_BusA_To => Set_BusA_To,
Set_Addr_To => Set_Addr_To,
Write_Data => Write_Data,
Jump => Jump,
BAAdd => BAAdd,
BreakAtNA => BreakAtNA,
ADAdd => ADAdd,
AddY => AddY,
PCAdd => PCAdd,
Inc_S => Inc_S,
Dec_S => Dec_S,
LDA => LDA,
LDP => LDP,
LDX => LDX,
LDY => LDY,
LDS => LDS,
LDDI => LDDI,
LDALU => LDALU,
LDAD => LDAD,
LDBAL => LDBAL,
LDBAH => LDBAH,
SaveP => SaveP,
ALUmore => ALUmore,
Write => Write
);
alu : T65_ALU
port map(
Mode => Mode_r,
Op => ALU_Op_r,
BusA => BusA_r,
BusB => BusB,
P_In => P,
P_Out => P_Out,
Q => ALU_Q
);
process (Res_n, Clk)
begin
if Res_n = '0' then
PC <= (others => '0'); -- Program Counter
IR <= "00000000";
S <= (others => '0'); -- Dummy !!!!!!!!!!!!!!!!!!!!!
D <= (others => '0');
PBR <= (others => '0');
DBR <= (others => '0');
Mode_r <= (others => '0');
ALU_Op_r <= ALU_OP_BIT;
Write_Data_r <= Write_Data_DL;
Set_Addr_To_r <= Set_Addr_To_PBR;
R_W_n_i <= '1';
EF_i <= '1';
MF_i <= '1';
XF_i <= '1';
elsif Clk'event and Clk = '1' then
if (Enable = '1') then
if (really_rdy = '1') then
R_W_n_i <= not Write or RstCycle;
D <= (others => '1'); -- Dummy
PBR <= (others => '1'); -- Dummy
DBR <= (others => '1'); -- Dummy
EF_i <= '0'; -- Dummy
MF_i <= '0'; -- Dummy
XF_i <= '0'; -- Dummy
if MCycle = "000" then
Mode_r <= Mode;
if IRQCycle = '0' and NMICycle = '0' then
PC <= PC + 1;
end if;
if IRQCycle = '1' or NMICycle = '1' then
IR <= "00000000";
else
IR <= DI;
end if;
end if;
ALU_Op_r <= ALU_Op;
Write_Data_r <= Write_Data;
if Break = '1' then
Set_Addr_To_r <= Set_Addr_To_PBR;
else
Set_Addr_To_r <= Set_Addr_To;
end if;
if Inc_S = '1' then
S <= S + 1;
end if;
if Dec_S = '1' and RstCycle = '0' then
S <= S - 1;
end if;
if LDS = '1' then
S(7 downto 0) <= unsigned(ALU_Q);
end if;
if IR = "00000000" and MCycle = "001" and IRQCycle = '0' and NMICycle = '0' then
PC <= PC + 1;
end if;
--
-- jump control logic
--
case Jump is
when "01" =>
PC <= PC + 1;
when "10" =>
PC <= unsigned(DI & DL);
when "11" =>
if PCAdder(8) = '1' then
if DL(7) = '0' then
PC(15 downto 8) <= PC(15 downto 8) + 1;
else
PC(15 downto 8) <= PC(15 downto 8) - 1;
end if;
end if;
PC(7 downto 0) <= PCAdder(7 downto 0);
when others => null;
end case;
end if;
end if;
end if;
end process;
PCAdder <= resize(PC(7 downto 0),9) + resize(unsigned(DL(7) & DL),9) when PCAdd = '1'
else "0" & PC(7 downto 0);
process (Res_n, Clk)
variable tmpP:std_logic_vector(7 downto 0);--ML:Lets try to handle loading P at mcycle=0 and set/clk flags at same cycle
begin
if Res_n = '0' then
P <= x"00"; -- ensure we have nothing set on reset (e.g. B flag!)
elsif Clk'event and Clk = '1' then
tmpP:=P;
if (Enable = '1') then
if (really_rdy = '1') then
if MCycle = "000" then
if LDA = '1' then
ABC(7 downto 0) <= ALU_Q;
end if;
if LDX = '1' then
X(7 downto 0) <= ALU_Q;
end if;
if LDY = '1' then
Y(7 downto 0) <= ALU_Q;
end if;
if (LDA or LDX or LDY) = '1' then
-- P <= P_Out;-- Replaced with:
tmpP:=P_Out;
end if;
end if;
if SaveP = '1' then
-- P <= P_Out;-- Replaced with:
tmpP:=P_Out;
end if;
if LDP = '1' then
-- P <= ALU_Q;-- Replaced with: --ML:no need anymore: AND x"EF"; -- NEVER set B on RTI and PLP
tmpP:=ALU_Q;
end if;
if IR(4 downto 0) = "11000" then
case IR(7 downto 5) is
when "000" =>--0x18(clc)
-- P(Flag_C) <= '0';-- Replaced with:
tmpP(Flag_C) := '0';
when "001" =>--0x38(sec)
-- P(Flag_C) <= '1';
tmpP(Flag_C) := '1';
when "010" =>--0x58(cli)
-- P(Flag_I) <= '0';
tmpP(Flag_I) := '0';
when "011" =>--0x78(sei)
-- P(Flag_I) <= '1';
tmpP(Flag_I) := '1';
when "101" =>--0xb8(clv)
-- P(Flag_V) <= '0';
tmpP(Flag_V) := '0';
when "110" =>--0xd8(cld)
-- P(Flag_D) <= '0';
tmpP(Flag_D) := '0';
when "111" =>--0xf8(sed)
-- P(Flag_D) <= '1';
tmpP(Flag_D) := '1';
when others =>
end case;
end if;
--ML:Removed change of B flag, its constant '1' in P
--ML:The B flag appears to be locked to '1', but when pushed to stack, the SR data on the stack has the B flag cleared on interrupts, set on BRK instr.
--ML:The state of the B flag on warm reset apparently is unchanged (not confirmed, please do if you know)
--ML:The state of the B flag on cold reset is uncertain, but my guess would be set, unless it can be used to detect cold from warm reset.
--Since we cant (well, won't) simulate B=0 on cold reset, we just behave as if it was constant 1.
-- P(Flag_B) <= '1';
tmpP(Flag_B) := '1';
-- if IR = "00000000" and MCycle = "011" and RstCycle = '0' and NMICycle = '0' and IRQCycle = '0' then -- BRK
-- P(Flag_B) <= '1';
-- elsif IR = "00001000" then -- PHP
-- P(Flag_B) <= '1';
-- else
-- P(Flag_B) <= '0'; --> not the best way, but we keep B zero except for BRK and PHP opcodes
-- end if;
if IR = "00000000" and MCycle = "100" and RstCycle = '0' then --and (NMICycle = '1' or IRQCycle = '1') then
--This should happen after P has been pushed to stack
-- P(Flag_I) <= '1';
tmpP(Flag_I) := '1';
end if;
if SO_n_o = '1' and SO_n = '0' then
-- P(Flag_V) <= '1';
tmpP(Flag_V) := '1';
end if;
if RstCycle = '1' then
-- P(Flag_I) <= '0';
-- P(Flag_D) <= '0';
tmpP(Flag_I) := '0';
tmpP(Flag_D) := '0';
end if;
-- P(Flag_1) <= '1';
tmpP(Flag_1) := '1';
P<=tmpP;--new way
SO_n_o <= SO_n;
IRQ_n_o <= IRQ_n;
end if;
NMI_n_o <= NMI_n; -- MWW: detect nmi even if not rdy
end if;
end if;
end process;
---------------------------------------------------------------------------
--
-- Buses
--
---------------------------------------------------------------------------
process (Res_n, Clk)
begin
if Res_n = '0' then
BusA_r <= (others => '0');
BusB <= (others => '0');
AD <= (others => '0');
BAL <= (others => '0');
BAH <= (others => '0');
DL <= (others => '0');
elsif Clk'event and Clk = '1' then
if (Enable = '1') then
if (really_rdy = '1') then
--if (Rdy = '1') then
BusA_r <= BusA;
if ALUmore='1' then
BusB <= ALU_Q;
else
BusB <= DI;
end if;
case BAAdd is
when "01" =>
-- BA Inc
AD <= std_logic_vector(unsigned(AD) + 1);
BAL <= std_logic_vector(unsigned(BAL) + 1);
when "10" =>
-- BA Add
BAL <= std_logic_vector(resize(unsigned(BAL(7 downto 0)),9) + resize(unsigned(BusA),9));
when "11" =>
-- BA Adj
if BAL(8) = '1' then
BAH <= std_logic_vector(unsigned(BAH) + 1);
end if;
when others =>
end case;
-- ehenciak : modified to use Y register as well (bugfix)
if ADAdd = '1' then
if (AddY = '1') then
AD <= std_logic_vector(unsigned(AD) + unsigned(Y(7 downto 0)));
else
AD <= std_logic_vector(unsigned(AD) + unsigned(X(7 downto 0)));
end if;
end if;
NMIActClear <= '0';
if IR = "00000000" then
BAL <= (others => '1');
BAH <= (others => '1');
if RstCycle = '1' then
BAL(2 downto 0) <= "100";
elsif NMICycle = '1' then
BAL(2 downto 0) <= "010";
elsif NMIAct = '1' then -- MWW, force this to be changed by NMI, even if in midstream IRQ/brk
BAL(2 downto 0) <= "010";
NMIActClear <= '1';
else
BAL(2 downto 0) <= "110";
end if;
if Set_addr_To_r = Set_Addr_To_BA then
BAL(0) <= '1';
end if;
end if;
if LDDI = '1' then
DL <= DI;
end if;
if LDALU = '1' then
DL <= ALU_Q;
end if;
if LDAD = '1' then
AD <= DI;
end if;
if LDBAL = '1' then
BAL(7 downto 0) <= DI;
end if;
if LDBAH = '1' then
BAH <= DI;
end if;
end if;
end if;
end if;
end process;
Break <= (BreakAtNA and not BAL(8)) or (PCAdd and not PCAdder(8));
with Set_BusA_To select
BusA <=
DI when Set_BusA_To_DI,
ABC(7 downto 0) when Set_BusA_To_ABC,
X(7 downto 0) when Set_BusA_To_X,
Y(7 downto 0) when Set_BusA_To_Y,
std_logic_vector(S(7 downto 0)) when Set_BusA_To_S,
P when Set_BusA_To_P,
(others => '-') when Set_BusA_To_DONTCARE;--Can probably remove this
with Set_Addr_To_r select
A <=
"0000000000000001" & std_logic_vector(S(7 downto 0)) when Set_Addr_To_S,
DBR & "00000000" & AD when Set_Addr_To_AD,
"00000000" & BAH & BAL(7 downto 0) when Set_Addr_To_BA,
PBR & std_logic_vector(PC(15 downto 8)) & std_logic_vector(PCAdder(7 downto 0)) when Set_Addr_To_PBR;
--ML:This is the P that gets pushed on stack with correct B flag. I'm not sure if NMI also clears B, but I guess it does.
PwithB<=(P and x"ef") when (IRQCycle='1' or NMICycle='1') else P;
with Write_Data_r select
DO <=
DL when Write_Data_DL,
ABC(7 downto 0) when Write_Data_ABC,
X(7 downto 0) when Write_Data_X,
Y(7 downto 0) when Write_Data_Y,
std_logic_vector(S(7 downto 0)) when Write_Data_S,
PwithB when Write_Data_P,
std_logic_vector(PC(7 downto 0)) when Write_Data_PCL,
std_logic_vector(PC(15 downto 8)) when Write_Data_PCH,
(others=>'-') when Write_Data_DONTCARE;--Can probably remove this
-------------------------------------------------------------------------
--
-- Main state machine
--
-------------------------------------------------------------------------
process (Res_n, Clk)
begin
if Res_n = '0' then
MCycle <= "001";
RstCycle <= '1';
IRQCycle <= '0';
NMICycle <= '0';
NMIAct <= '0';
elsif Clk'event and Clk = '1' then
if (Enable = '1') then
if (really_rdy = '1') then
if (NMIActClear = '1') then
NMIAct <= '0';
end if;
if MCycle = LCycle or Break = '1' then
MCycle <= "000";
RstCycle <= '0';
IRQCycle <= '0';
NMICycle <= '0';
if NMIAct = '1' then
NMICycle <= '1';
elsif IRQ_n_o = '0' and P(Flag_I) = '0' then
IRQCycle <= '1';
end if;
else
MCycle <= std_logic_vector(unsigned(MCycle) + 1);
end if;
if NMICycle = '1' then
NMIAct <= '0';
end if;
end if;
if NMI_n_o = '1' and NMI_n = '0' then -- MWW: detect nmi even if not rdy
NMIAct <= '1';
end if;
end if;
end if;
end process;
end;
| gpl-3.0 | c085c66dca4b85aa2e4ef148a33d1754 | 0.46307 | 3.636545 | false | false | false | false |
EliasLuiz/TCC | Leon3/designs/leon3-digilent-xc3s1600e/leon3mp.vhd | 1 | 23,353 | ------------------------------------------------------------------------------
-- LEON3 Demonstration design
-- Copyright (C) 2006 Jiri Gaisler, Gaisler Research
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
library techmap;
use techmap.gencomp.all;
use techmap.allclkgen.all;
library gaisler;
use gaisler.memctrl.all;
use gaisler.ddrpkg.all;
use gaisler.leon3.all;
use gaisler.uart.all;
use gaisler.misc.all;
use gaisler.net.all;
use gaisler.jtag.all;
library esa;
use esa.memoryctrl.all;
use work.config.all;
entity leon3mp is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
clktech : integer := CFG_CLKTECH;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW;
ddrfreq : integer := 100000 -- frequency of ddr clock in kHz
);
port (
reset : in std_ulogic;
-- resoutn : out std_logic;
clk_50mhz : in std_ulogic;
errorn : out std_ulogic;
-- prom interface
address : out std_logic_vector(23 downto 0);
data : inout std_logic_vector(15 downto 0);
romsn : out std_ulogic;
oen : out std_ulogic;
writen : out std_ulogic;
byten : out std_ulogic;
-- pragma translate_off
iosn : out std_ulogic;
testdata : inout std_logic_vector(15 downto 0);
-- pragma translate_on
-- ddr memory
ddr_clk0 : out std_logic;
ddr_clk0b : out std_logic;
-- ddr_clk_fb_out : out std_logic;
ddr_clk_fb : in std_logic;
ddr_cke0 : out std_logic;
ddr_cs0b : out std_logic;
ddr_web : out std_ulogic; -- ddr write enable
ddr_rasb : out std_ulogic; -- ddr ras
ddr_casb : out std_ulogic; -- ddr cas
ddr_dm : out std_logic_vector (1 downto 0); -- ddr dm
ddr_dqs : inout std_logic_vector (1 downto 0); -- ddr dqs
ddr_ad : out std_logic_vector (12 downto 0); -- ddr address
ddr_ba : out std_logic_vector (1 downto 0); -- ddr bank address
ddr_dq : inout std_logic_vector (15 downto 0); -- ddr data
-- debug support unit
dsuen : in std_ulogic;
dsubre : in std_ulogic;
-- dsuact : out std_ulogic;
dsurx : in std_ulogic;
dsutx : out std_ulogic;
-- UART for serial console I/O
urxd1 : in std_ulogic;
utxd1 : out std_ulogic;
-- ethernet signals
emdio : inout std_logic; -- ethernet PHY interface
etx_clk : in std_ulogic;
erx_clk : in std_ulogic;
erxd : in std_logic_vector(3 downto 0);
erx_dv : in std_ulogic;
erx_er : in std_ulogic;
erx_col : in std_ulogic;
erx_crs : in std_ulogic;
etxd : out std_logic_vector(3 downto 0);
etx_en : out std_ulogic;
etx_er : out std_ulogic;
emdc : out std_ulogic;
spi : out std_ulogic;
led : out std_logic_vector(5 downto 0);
ps2clk : inout std_logic;
ps2data : inout std_logic;
vid_hsync : out std_ulogic;
vid_vsync : out std_ulogic;
vid_r : out std_logic;
vid_g : out std_logic;
vid_b : out std_logic
);
end;
architecture rtl of leon3mp is
constant blength : integer := 12;
constant fifodepth : integer := 8;
signal vcc, gnd : std_logic_vector(4 downto 0);
signal memi : memory_in_type;
signal memo : memory_out_type;
signal wpo : wprot_out_type;
signal sdi : sdctrl_in_type;
signal sdo : sdctrl_out_type;
signal gpioi : gpio_in_type;
signal gpioo : gpio_out_type;
signal apbi : apb_slv_in_type;
signal apbo : apb_slv_out_vector := (others => apb_none);
signal ahbsi : ahb_slv_in_type;
signal ahbso : ahb_slv_out_vector := (others => ahbs_none);
signal ahbmi : ahb_mst_in_type;
signal ahbmo : ahb_mst_out_vector := (others => ahbm_none);
signal lclk : std_ulogic;
signal ddrclk, ddrrst, ddrclkfb : std_ulogic;
signal clkm, rstn, clkml, clk2x : std_ulogic;
signal cgi : clkgen_in_type;
signal cgo : clkgen_out_type;
signal u1i, dui : uart_in_type;
signal u1o, duo : uart_out_type;
signal irqi : irq_in_vector(0 to CFG_NCPU-1);
signal irqo : irq_out_vector(0 to CFG_NCPU-1);
signal dbgi : l3_debug_in_vector(0 to CFG_NCPU-1);
signal dbgo : l3_debug_out_vector(0 to CFG_NCPU-1);
signal dsui : dsu_in_type;
signal dsuo : dsu_out_type;
signal ethi, ethi1, ethi2 : eth_in_type;
signal etho, etho1, etho2 : eth_out_type;
signal gpti : gptimer_in_type;
signal tck, tms, tdi, tdo : std_ulogic;
signal kbdi : ps2_in_type;
signal kbdo : ps2_out_type;
signal vgao : apbvga_out_type;
signal ldsubre : std_logic;
signal duart, ldsuen : std_logic;
signal rsertx, rserrx, rdsuen : std_logic;
signal rstraw : std_logic;
signal rstneg : std_logic;
signal rxd1, rxd2 : std_logic;
signal txd1 : std_logic;
signal lock : std_logic;
signal ddr_clk : std_logic_vector(2 downto 0);
signal ddr_clkb : std_logic_vector(2 downto 0);
signal ddr_cke : std_logic_vector(1 downto 0);
signal ddr_csb : std_logic_vector(1 downto 0);
signal ddr_adl : std_logic_vector(13 downto 0); -- ddr address
attribute keep : boolean;
attribute syn_keep : boolean;
attribute syn_preserve : boolean;
attribute syn_keep of lock : signal is true;
attribute syn_keep of clkml : signal is true;
attribute syn_preserve of clkml : signal is true;
attribute keep of lock : signal is true;
attribute keep of clkml : signal is true;
attribute keep of clkm : signal is true;
constant BOARD_FREQ : integer := 50000; -- input frequency in KHz
constant CPU_FREQ : integer := BOARD_FREQ * CFG_CLKMUL / CFG_CLKDIV; -- cpu frequency in KHz
begin
----------------------------------------------------------------------
--- Reset and Clock generation -------------------------------------
----------------------------------------------------------------------
vcc <= (others => '1'); gnd <= (others => '0');
cgi.pllctrl <= "00"; cgi.pllrst <= rstraw;
rstneg <= not reset; spi <= '1';
rst0 : rstgen port map (rstneg, clkm, lock, rstn, rstraw);
led(5) <= lock;
clk_pad : clkpad generic map (tech => padtech) port map (clk_50mhz, lclk);
clkgen0 : clkgen -- clock generator
generic map (fabtech, CFG_CLKMUL, CFG_CLKDIV, 0, 0, 0, 0, 0, BOARD_FREQ, 0)
port map (lclk, gnd(0), clkm, open, open, open, open, cgi, cgo, open, open, clk2x);
-- cgo.clklock <= '1';
----------------------------------------------------------------------
--- AHB CONTROLLER --------------------------------------------------
----------------------------------------------------------------------
ahb0 : ahbctrl -- AHB arbiter/multiplexer
generic map (defmast => CFG_DEFMST, split => CFG_SPLIT,
rrobin => CFG_RROBIN, ioaddr => CFG_AHBIO, ioen => 1,
nahbm => CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_GRETH+CFG_SVGA_ENABLE,
nahbs => 8)
port map (rstn, clkm, ahbmi, ahbmo, ahbsi, ahbso);
----------------------------------------------------------------------
--- LEON3 processor and DSU -----------------------------------------
----------------------------------------------------------------------
leon3gen : if CFG_LEON3 = 1 generate
cpu : for i in 0 to CFG_NCPU-1 generate
u0 : leon3s -- LEON3 processor
generic map (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU, CFG_V8,
0, CFG_MAC, pclow, CFG_NOTAG, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE,
CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ,
CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN,
CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP,
CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR,
CFG_NCPU-1, CFG_DFIXED, CFG_SCAN, CFG_MMU_PAGE, CFG_BP, CFG_NP_ASI, CFG_WRPSR)
port map (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso,
irqi(i), irqo(i), dbgi(i), dbgo(i));
end generate;
error_pad : odpad generic map (tech => padtech) port map (errorn, dbgo(0).error);
dsugen : if CFG_DSU = 1 generate
dsu0 : dsu3 -- LEON3 Debug Support Unit
generic map (hindex => 2, haddr => 16#900#, hmask => 16#F00#,
ncpu => CFG_NCPU, tbits => 30, tech => memtech, irq => 0, kbytes => CFG_ATBSZ)
port map (rstn, clkm, ahbmi, ahbsi, ahbso(2), dbgo, dbgi, dsui, dsuo);
dsui.enable <= '1';
dsubre_pad : inpad generic map (tech => padtech) port map (dsubre, ldsubre);
dsui.break <= ldsubre;
-- dsuact_pad : outpad generic map (tech => padtech) port map (dsuact, dsuo.active);
led(4) <= dsuo.active;
end generate;
end generate;
nodsu : if CFG_DSU = 0 generate
ahbso(2) <= ahbs_none; dsuo.tstop <= '0'; dsuo.active <= '0';
end generate;
dcomgen : if CFG_AHB_UART = 1 generate
dcom0 : ahbuart -- Debug UART
generic map (hindex => CFG_NCPU, pindex => 4, paddr => 7)
port map (rstn, clkm, dui, duo, apbi, apbo(4), ahbmi, ahbmo(CFG_NCPU));
dsurx_pad : inpad generic map (tech => padtech) port map (dsurx, rxd2);
dui.rxd <= rxd2;
dsutx_pad : outpad generic map (tech => padtech) port map (dsutx, duo.txd);
led(2) <= not rxd2; led(3) <= not duo.txd;
end generate;
nouah : if CFG_AHB_UART = 0 generate apbo(4) <= apb_none; end generate;
ahbjtaggen0 :if CFG_AHB_JTAG = 1 generate
ahbjtag0 : ahbjtag generic map(tech => fabtech, hindex => CFG_NCPU+CFG_AHB_UART)
port map(rstn, clkm, tck, tms, tdi, tdo, ahbmi, ahbmo(CFG_NCPU+CFG_AHB_UART),
open, open, open, open, open, open, open, gnd(0));
end generate;
----------------------------------------------------------------------
--- Memory controllers ----------------------------------------------
----------------------------------------------------------------------
mg2 : if CFG_MCTRL_LEON2 = 1 generate -- LEON2 memory controller
sr1 : mctrl generic map (hindex => 5, pindex => 0,
paddr => 0, srbanks => 1, ramaddr => 16#600#, rammask => 16#F00#, ram16 => 1 )
port map (rstn, clkm, memi, memo, ahbsi, ahbso(5), apbi, apbo(0), wpo, open);
end generate;
byten <= '1'; -- 16-bit flash
memi.brdyn <= '1'; memi.bexcn <= '1';
memi.writen <= '1'; memi.wrn <= "1111"; memi.bwidth <= "01";
mg0 : if (CFG_MCTRL_LEON2 = 0) generate
apbo(0) <= apb_none; ahbso(0) <= ahbs_none;
roms_pad : outpad generic map (tech => padtech)
port map (romsn, vcc(0));
end generate;
mgpads : if (CFG_MCTRL_LEON2 /= 0) generate
addr_pad : outpadv generic map (width => 24, tech => padtech)
port map (address, memo.address(23 downto 0));
roms_pad : outpad generic map (tech => padtech)
port map (romsn, memo.romsn(0));
oen_pad : outpad generic map (tech => padtech)
port map (oen, memo.oen);
wri_pad : outpad generic map (tech => padtech)
port map (writen, memo.writen);
-- pragma translate_off
iosn_pad : outpad generic map (tech => padtech)
port map (iosn, memo.iosn);
tbdr : for i in 0 to 1 generate
data_pad : iopadv generic map (tech => padtech, width => 8)
port map (testdata(15-i*8 downto 8-i*8), memo.data(15-i*8 downto 8-i*8),
memo.bdrive(i+2), memi.data(15-i*8 downto 8-i*8));
end generate;
-- pragma translate_on
bdr : for i in 0 to 1 generate
data_pad : iopadv generic map (tech => padtech, width => 8)
port map (data(15-i*8 downto 8-i*8), memo.data(31-i*8 downto 24-i*8),
memo.bdrive(i), memi.data(31-i*8 downto 24-i*8));
end generate;
end generate;
----------------------------------------------------------------------
--- DDR memory controller -------------------------------------------
----------------------------------------------------------------------
ddrsp0 : if (CFG_DDRSP /= 0) generate
ddrc : ddrspa generic map ( fabtech => spartan3e, memtech => memtech,
hindex => 4, haddr => 16#400#, hmask => 16#F00#, ioaddr => 1,
pwron => CFG_DDRSP_INIT, MHz => 2*BOARD_FREQ/1000, rskew => CFG_DDRSP_RSKEW,
clkmul => CFG_DDRSP_FREQ/10, clkdiv => 2*5, col => CFG_DDRSP_COL,
Mbyte => CFG_DDRSP_SIZE, ahbfreq => CPU_FREQ/1000, ddrbits => 16)
port map (
cgo.clklock, rstn, clk2x, clkm, lock, clkml, clkml, ahbsi, ahbso(4),
ddr_clk, ddr_clkb, open, ddr_clk_fb,
ddr_cke, ddr_csb, ddr_web, ddr_rasb, ddr_casb,
ddr_dm, ddr_dqs, ddr_adl, ddr_ba, ddr_dq);
ddr_clk0 <= ddr_clk(0); ddr_clk0b <= ddr_clkb(0);
ddr_cke0 <= ddr_cke(0); ddr_cs0b <= ddr_csb(0);
ddr_ad <= ddr_adl(12 downto 0);
end generate;
noddr : if (CFG_DDRSP = 0) generate lock <= '1'; end generate;
----------------------------------------------------------------------
--- APB Bridge and various periherals -------------------------------
----------------------------------------------------------------------
apb0 : apbctrl -- AHB/APB bridge
generic map (hindex => 1, haddr => CFG_APBADDR)
port map (rstn, clkm, ahbsi, ahbso(1), apbi, apbo);
ua1 : if CFG_UART1_ENABLE /= 0 generate
uart1 : apbuart -- UART 1
generic map (pindex => 1, paddr => 1, pirq => 2, console => dbguart,
fifosize => CFG_UART1_FIFO)
port map (rstn, clkm, apbi, apbo(1), u1i, u1o);
u1i.rxd <= rxd1; u1i.ctsn <= '0'; u1i.extclk <= '0'; txd1 <= u1o.txd;
serrx_pad : inpad generic map (tech => padtech) port map (urxd1, rxd1);
sertx_pad : outpad generic map (tech => padtech) port map (utxd1, txd1);
led(0) <= not rxd1; led(1) <= not txd1;
end generate;
noua0 : if CFG_UART1_ENABLE = 0 generate apbo(1) <= apb_none; end generate;
irqctrl : if CFG_IRQ3_ENABLE /= 0 generate
irqctrl0 : irqmp -- interrupt controller
generic map (pindex => 2, paddr => 2, ncpu => CFG_NCPU)
port map (rstn, clkm, apbi, apbo(2), irqo, irqi);
end generate;
irq3 : if CFG_IRQ3_ENABLE = 0 generate
x : for i in 0 to CFG_NCPU-1 generate
irqi(i).irl <= "0000";
end generate;
apbo(2) <= apb_none;
end generate;
gpt : if CFG_GPT_ENABLE /= 0 generate
timer0 : gptimer -- timer unit
generic map (pindex => 3, paddr => 3, pirq => CFG_GPT_IRQ,
sepirq => CFG_GPT_SEPIRQ, sbits => CFG_GPT_SW, ntimers => CFG_GPT_NTIM,
nbits => CFG_GPT_TW)
port map (rstn, clkm, apbi, apbo(3), gpti, open);
gpti <= gpti_dhalt_drive(dsuo.tstop);
end generate;
notim : if CFG_GPT_ENABLE = 0 generate apbo(3) <= apb_none; end generate;
gpio0 : if CFG_GRGPIO_ENABLE /= 0 generate -- GR GPIO unit
grgpio0: grgpio
generic map( pindex => 11, paddr => 11, imask => CFG_GRGPIO_IMASK,
nbits => 12 --CFG_GRGPIO_WIDTH
)
port map( rstn, clkm, apbi, apbo(11), gpioi, gpioo);
end generate;
kbd : if CFG_KBD_ENABLE /= 0 generate
ps20 : apbps2 generic map(pindex => 5, paddr => 5, pirq => 5)
port map(rstn, clkm, apbi, apbo(5), kbdi, kbdo);
kbdclk_pad : iopad generic map (tech => padtech)
port map (ps2clk,kbdo.ps2_clk_o, kbdo.ps2_clk_oe, kbdi.ps2_clk_i);
kbdata_pad : iopad generic map (tech => padtech)
port map (ps2data, kbdo.ps2_data_o, kbdo.ps2_data_oe, kbdi.ps2_data_i);
end generate;
nokbd : if CFG_KBD_ENABLE = 0 generate
apbo(5) <= apb_none; kbdo <= ps2o_none;
end generate;
-- vga : if CFG_VGA_ENABLE /= 0 generate
-- vga0 : apbvga generic map(memtech => memtech, pindex => 6, paddr => 6)
-- port map(rstn, clkm, ethclk, apbi, apbo(6), vgao);
-- video_clock_pad : outpad generic map ( tech => padtech)
-- port map (vid_clock, dac_clk);
-- dac_clk <= not clkm;
-- end generate;
svga : if CFG_SVGA_ENABLE /= 0 generate
svga0 : svgactrl generic map(memtech => memtech, pindex => 6, paddr => 6,
hindex => CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG,
clk0 => 1000000000/((BOARD_FREQ * CFG_CLKMUL)/CFG_CLKDIV),
clk1 => 0, clk2 => 0, burstlen => 5)
port map(rstn, clkm, clkm, apbi, apbo(6), vgao, ahbmi,
ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG), open);
end generate;
-- blank_pad : outpad generic map (tech => padtech)
-- port map (vid_blankn, vgao.blank);
-- comp_sync_pad : outpad generic map (tech => padtech)
-- port map (vid_syncn, vgao.comp_sync);
vert_sync_pad : outpad generic map (tech => padtech)
port map (vid_vsync, vgao.vsync);
horiz_sync_pad : outpad generic map (tech => padtech)
port map (vid_hsync, vgao.hsync);
video_out_r_pad : outpad generic map (tech => padtech)
port map (vid_r, vgao.video_out_r(7));
video_out_g_pad : outpad generic map (tech => padtech)
port map (vid_g, vgao.video_out_g(7));
video_out_b_pad : outpad generic map (tech => padtech)
port map (vid_b, vgao.video_out_b(7));
-----------------------------------------------------------------------
--- ETHERNET ---------------------------------------------------------
-----------------------------------------------------------------------
eth0 : if CFG_GRETH = 1 generate -- Gaisler ethernet MAC
e1 : grethm generic map(hindex => CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_SVGA_ENABLE,
pindex => 15, paddr => 15, pirq => 12, memtech => memtech,
mdcscaler => CPU_FREQ/1000, enable_mdio => 1, fifosize => CFG_ETH_FIFO,
nsync => 1, edcl => CFG_DSU_ETH, edclbufsz => CFG_ETH_BUF,
macaddrh => CFG_ETH_ENM, macaddrl => CFG_ETH_ENL,
ipaddrh => CFG_ETH_IPM, ipaddrl => CFG_ETH_IPL,
phyrstadr => 31, giga => CFG_GRETH1G)
port map( rst => rstn, clk => clkm, ahbmi => ahbmi,
ahbmo => ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_SVGA_ENABLE),
apbi => apbi, apbo => apbo(15), ethi => ethi, etho => etho);
emdio_pad : iopad generic map (tech => padtech)
port map (emdio, etho.mdio_o, etho.mdio_oe, ethi.mdio_i);
etxc_pad : inpad generic map (tech => padtech)
port map (etx_clk, ethi.tx_clk);
erxc_pad : inpad generic map (tech => padtech)
port map (erx_clk, ethi.rx_clk);
erxd_pad : inpadv generic map (tech => padtech, width => 4)
port map (erxd, ethi.rxd(3 downto 0));
erxdv_pad : inpad generic map (tech => padtech)
port map (erx_dv, ethi.rx_dv);
erxer_pad : inpad generic map (tech => padtech)
port map (erx_er, ethi.rx_er);
erxco_pad : inpad generic map (tech => padtech)
port map (erx_col, ethi.rx_col);
erxcr_pad : inpad generic map (tech => padtech)
port map (erx_crs, ethi.rx_crs);
etxd_pad : outpadv generic map (tech => padtech, width => 4)
port map (etxd, etho.txd(3 downto 0));
etxen_pad : outpad generic map (tech => padtech)
port map (etx_en, etho.tx_en);
etxer_pad : outpad generic map (tech => padtech)
port map (etx_er, etho.tx_er);
emdc_pad : outpad generic map (tech => padtech)
port map (emdc, etho.mdc);
end generate;
-----------------------------------------------------------------------
--- AHB DMA ----------------------------------------------------------
-----------------------------------------------------------------------
-- dma0 : ahbdma
-- generic map (hindex => CFG_NCPU+CFG_AHB_UART+CFG_GRETH,
-- pindex => 12, paddr => 12, dbuf => 32)
-- port map (rstn, clkm, apbi, apbo(12), ahbmi,
-- ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_GRETH));
--
-- at0 : ahbtrace
-- generic map ( hindex => 7, ioaddr => 16#200#, iomask => 16#E00#,
-- tech => memtech, irq => 0, kbytes => 8)
-- port map ( rstn, clkm, ahbmi, ahbsi, ahbso(7));
-----------------------------------------------------------------------
--- AHB ROM ----------------------------------------------------------
-----------------------------------------------------------------------
bpromgen : if CFG_AHBROMEN /= 0 generate
brom : entity work.ahbrom
generic map (hindex => 6, haddr => CFG_AHBRODDR, pipe => CFG_AHBROPIP)
port map ( rstn, clkm, ahbsi, ahbso(6));
end generate;
nobpromgen : if CFG_AHBROMEN = 0 generate
ahbso(6) <= ahbs_none;
end generate;
-----------------------------------------------------------------------
--- AHB RAM ----------------------------------------------------------
-----------------------------------------------------------------------
ahbramgen : if CFG_AHBRAMEN = 1 generate
ahbram0 : ahbram generic map (hindex => 3, haddr => CFG_AHBRADDR,
tech => CFG_MEMTECH, kbytes => CFG_AHBRSZ,
pipe => CFG_AHBRPIPE)
port map (rstn, clkm, ahbsi, ahbso(3));
end generate;
nram : if CFG_AHBRAMEN = 0 generate ahbso(3) <= ahbs_none; end generate;
-----------------------------------------------------------------------
--- Drive unused bus elements ---------------------------------------
-----------------------------------------------------------------------
nam1 : for i in (CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_GRETH+CFG_SVGA_ENABLE+1) to NAHBMST-1 generate
ahbmo(i) <= ahbm_none;
end generate;
-- nap0 : for i in 9 to NAPBSLV-1-CFG_GRETH generate apbo(i) <= apb_none; end generate;
-- nah0 : for i in 8 to NAHBSLV-1 generate ahbso(i) <= ahbs_none; end generate;
-- resoutn <= rstn;
-----------------------------------------------------------------------
--- Boot message ----------------------------------------------------
-----------------------------------------------------------------------
-- pragma translate_off
x : report_design
generic map (
msg1 => "LEON3 Demonstration design for Digilent Spartan3E Eval board",
fabtech => tech_table(fabtech), memtech => tech_table(memtech),
mdel => 1
);
-- pragma translate_on
end rtl;
| gpl-3.0 | 4df5fb9f2d158a730fbe30cf7f4eecab | 0.542029 | 3.654617 | false | false | false | false |
EliasLuiz/TCC | Leon3/designs/leon3-digilent-xc7z020/leon3mp.vhd | 1 | 24,053 | -----------------------------------------------------------------------------
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- LEON3 Zedboard Demonstration design
-- Copyright (C) 2012 Fredrik Ringhage, Aeroflex Gaisler
-- Modifed by Jiri Gaisler to provide working AXI interface, 2014-04-05
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib, techmap;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.config.all;
use techmap.gencomp.all;
library gaisler;
use gaisler.leon3.all;
use gaisler.uart.all;
use gaisler.misc.all;
use gaisler.jtag.all;
-- pragma translate_off
use gaisler.sim.all;
-- pragma translate_on
use work.config.all;
entity leon3mp is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
clktech : integer := CFG_CLKTECH;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW;
testahb : boolean := false
);
port (
processing_system7_0_MIO : inout std_logic_vector(53 downto 0);
processing_system7_0_PS_SRSTB : inout std_logic;
processing_system7_0_PS_CLK : inout std_logic;
processing_system7_0_PS_PORB : inout std_logic;
processing_system7_0_DDR_Clk : inout std_logic;
processing_system7_0_DDR_Clk_n : inout std_logic;
processing_system7_0_DDR_CKE : inout std_logic;
processing_system7_0_DDR_CS_n : inout std_logic;
processing_system7_0_DDR_RAS_n : inout std_logic;
processing_system7_0_DDR_CAS_n : inout std_logic;
processing_system7_0_DDR_WEB_pin : inout std_logic;
processing_system7_0_DDR_BankAddr : inout std_logic_vector(2 downto 0);
processing_system7_0_DDR_Addr : inout std_logic_vector(14 downto 0);
processing_system7_0_DDR_ODT : inout std_logic;
processing_system7_0_DDR_DRSTB : inout std_logic;
processing_system7_0_DDR_DQ : inout std_logic_vector(31 downto 0);
processing_system7_0_DDR_DM : inout std_logic_vector(3 downto 0);
processing_system7_0_DDR_DQS : inout std_logic_vector(3 downto 0);
processing_system7_0_DDR_DQS_n : inout std_logic_vector(3 downto 0);
processing_system7_0_DDR_VRN : inout std_logic;
processing_system7_0_DDR_VRP : inout std_logic;
button : in std_logic_vector(3 downto 0);
switch : inout std_logic_vector(7 downto 0);
led : out std_logic_vector(7 downto 0)
);
end;
architecture rtl of leon3mp is
component leon3_zedboard_stub
port (
DDR_addr : inout STD_LOGIC_VECTOR ( 14 downto 0 );
DDR_ba : inout STD_LOGIC_VECTOR ( 2 downto 0 );
DDR_cas_n : inout STD_LOGIC;
DDR_ck_n : inout STD_LOGIC;
DDR_ck_p : inout STD_LOGIC;
DDR_cke : inout STD_LOGIC;
DDR_cs_n : inout STD_LOGIC;
DDR_dm : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_dq : inout STD_LOGIC_VECTOR ( 31 downto 0 );
DDR_dqs_n : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_dqs_p : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_odt : inout STD_LOGIC;
DDR_ras_n : inout STD_LOGIC;
DDR_reset_n : inout STD_LOGIC;
DDR_we_n : inout STD_LOGIC;
FCLK_CLK0 : out STD_LOGIC;
FCLK_CLK1 : out STD_LOGIC;
FCLK_RESET0_N : out STD_LOGIC;
FIXED_IO_ddr_vrn : inout STD_LOGIC;
FIXED_IO_ddr_vrp : inout STD_LOGIC;
FIXED_IO_mio : inout STD_LOGIC_VECTOR ( 53 downto 0 );
FIXED_IO_ps_clk : inout STD_LOGIC;
FIXED_IO_ps_porb : inout STD_LOGIC;
FIXED_IO_ps_srstb : inout STD_LOGIC;
S_AXI_GP0_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_GP0_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_GP0_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP0_arid : in STD_LOGIC_VECTOR ( 5 downto 0 ); --
S_AXI_GP0_arlen : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP0_arlock : in STD_LOGIC_VECTOR ( 1 downto 0 ); --
S_AXI_GP0_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_GP0_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 ); --
S_AXI_GP0_arready : out STD_LOGIC;
S_AXI_GP0_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_GP0_arvalid : in STD_LOGIC;
S_AXI_GP0_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_GP0_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_GP0_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP0_awid : in STD_LOGIC_VECTOR ( 5 downto 0 ); --
S_AXI_GP0_awlen : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP0_awlock : in STD_LOGIC_VECTOR ( 1 downto 0 ); --
S_AXI_GP0_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_GP0_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 ); --
S_AXI_GP0_awready : out STD_LOGIC;
S_AXI_GP0_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_GP0_awvalid : in STD_LOGIC;
S_AXI_GP0_bid : out STD_LOGIC_VECTOR ( 5 downto 0 ); --
S_AXI_GP0_bready : in STD_LOGIC;
S_AXI_GP0_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_GP0_bvalid : out STD_LOGIC;
S_AXI_GP0_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_GP0_rid : out STD_LOGIC_VECTOR ( 5 downto 0 ); --
S_AXI_GP0_rlast : out STD_LOGIC;
S_AXI_GP0_rready : in STD_LOGIC;
S_AXI_GP0_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_GP0_rvalid : out STD_LOGIC;
S_AXI_GP0_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_GP0_wid : in STD_LOGIC_VECTOR ( 5 downto 0 ); --
S_AXI_GP0_wlast : in STD_LOGIC;
S_AXI_GP0_wready : out STD_LOGIC;
S_AXI_GP0_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP0_wvalid : in STD_LOGIC
);
end component;
constant maxahbm : integer := (CFG_LEON3*CFG_NCPU)+CFG_AHB_JTAG;
constant maxahbs : integer := 8;
constant maxapbs : integer := 16;
signal vcc, gnd : std_logic;
signal apbi : apb_slv_in_type;
signal apbo : apb_slv_out_vector := (others => apb_none);
signal ahbsi : ahb_slv_in_type;
signal ahbso : ahb_slv_out_vector := (others => ahbs_none);
signal ahbmi : ahb_mst_in_type;
signal ahbmo : ahb_mst_out_vector := (others => ahbm_none);
signal clkm, rstn, rsti, rst : std_ulogic;
signal u1i, dui : uart_in_type;
signal u1o, duo : uart_out_type;
signal irqi : irq_in_vector(0 to CFG_NCPU-1);
signal irqo : irq_out_vector(0 to CFG_NCPU-1);
signal dbgi : l3_debug_in_vector(0 to CFG_NCPU-1);
signal dbgo : l3_debug_out_vector(0 to CFG_NCPU-1);
signal dsui : dsu_in_type;
signal dsuo : dsu_out_type;
signal rxd1 : std_logic;
signal txd1 : std_logic;
signal gpti : gptimer_in_type;
signal gpto : gptimer_out_type;
signal gpioi : gpio_in_type;
signal gpioo : gpio_out_type;
signal tck, tckn, tms, tdi, tdo : std_ulogic;
constant BOARD_FREQ : integer := 83333; -- CLK0 frequency in KHz
constant CPU_FREQ : integer := BOARD_FREQ;
signal stati : ahbstat_in_type;
constant CIDSZ : integer := 6;
constant CLENSZ : integer := 4;
signal S_AXI_GP0_araddr : STD_LOGIC_VECTOR ( 31 downto 0 );
signal S_AXI_GP0_arburst : STD_LOGIC_VECTOR ( 1 downto 0 );
signal S_AXI_GP0_arcache : STD_LOGIC_VECTOR ( 3 downto 0 );
signal S_AXI_GP0_arid : STD_LOGIC_VECTOR ( CIDSZ-1 downto 0 );
signal S_AXI_GP0_arlen : STD_LOGIC_VECTOR ( CLENSZ-1 downto 0 );
signal S_AXI_GP0_arlock : STD_LOGIC_VECTOR ( 1 downto 0 ); --
signal S_AXI_GP0_arprot : STD_LOGIC_VECTOR ( 2 downto 0 );
signal S_AXI_GP0_arqos : STD_LOGIC_VECTOR ( 3 downto 0 ); --
signal S_AXI_GP0_awqos : STD_LOGIC_VECTOR ( 3 downto 0 ); --
signal S_AXI_GP0_arready : STD_LOGIC;
signal S_AXI_GP0_arsize : STD_LOGIC_VECTOR ( 2 downto 0 );
signal S_AXI_GP0_arvalid : STD_LOGIC;
signal S_AXI_GP0_awaddr : STD_LOGIC_VECTOR ( 31 downto 0 );
signal S_AXI_GP0_awburst : STD_LOGIC_VECTOR ( 1 downto 0 );
signal S_AXI_GP0_awcache : STD_LOGIC_VECTOR ( 3 downto 0 );
signal S_AXI_GP0_awid : STD_LOGIC_VECTOR ( CIDSZ-1 downto 0 );
signal S_AXI_GP0_awlen : STD_LOGIC_VECTOR ( CLENSZ-1 downto 0 );
signal S_AXI_GP0_awlock : STD_LOGIC_VECTOR ( 1 downto 0 ); --
signal S_AXI_GP0_awprot : STD_LOGIC_VECTOR ( 2 downto 0 );
signal S_AXI_GP0_awready : STD_LOGIC;
signal S_AXI_GP0_awsize : STD_LOGIC_VECTOR ( 2 downto 0 );
signal S_AXI_GP0_awvalid : STD_LOGIC;
signal S_AXI_GP0_bid : STD_LOGIC_VECTOR ( CIDSZ-1 downto 0 );
signal S_AXI_GP0_bready : STD_LOGIC;
signal S_AXI_GP0_bresp : STD_LOGIC_VECTOR ( 1 downto 0 );
signal S_AXI_GP0_bvalid : STD_LOGIC;
signal S_AXI_GP0_rdata : STD_LOGIC_VECTOR ( 31 downto 0 );
signal S_AXI_GP0_rid : STD_LOGIC_VECTOR ( CIDSZ-1 downto 0 );
signal S_AXI_GP0_rlast : STD_LOGIC;
signal S_AXI_GP0_rready : STD_LOGIC;
signal S_AXI_GP0_rresp : STD_LOGIC_VECTOR ( 1 downto 0 );
signal S_AXI_GP0_rvalid : STD_LOGIC;
signal S_AXI_GP0_wdata : STD_LOGIC_VECTOR ( 31 downto 0 );
signal S_AXI_GP0_wlast : STD_LOGIC;
signal S_AXI_GP0_wready : STD_LOGIC;
signal S_AXI_GP0_wstrb : STD_LOGIC_VECTOR ( 3 downto 0 );
signal S_AXI_GP0_wvalid : STD_LOGIC;
signal S_AXI_GP0_wid : STD_LOGIC_VECTOR ( 5 downto 0 ); --
begin
----------------------------------------------------------------------
--- Reset and Clock generation -------------------------------------
----------------------------------------------------------------------
vcc <= '1'; gnd <= '0';
reset_pad : inpad generic map (level => cmos, voltage => x18v, tech => padtech)
port map (button(0), rsti);
rstn <= rst and not rsti;
----------------------------------------------------------------------
--- AHB CONTROLLER --------------------------------------------------
----------------------------------------------------------------------
ahb0 : ahbctrl -- AHB arbiter/multiplexer
generic map (defmast => CFG_DEFMST, split => CFG_SPLIT,
rrobin => CFG_RROBIN, ioaddr => CFG_AHBIO, fpnpen => CFG_FPNPEN,
nahbm => maxahbm, nahbs => maxahbs)
port map (rstn, clkm, ahbmi, ahbmo, ahbsi, ahbso);
----------------------------------------------------------------------
--- LEON3 processor and DSU -----------------------------------------
----------------------------------------------------------------------
leon3_0 : if CFG_LEON3 = 1 generate
cpu : for i in 0 to CFG_NCPU-1 generate
u0 : leon3s -- LEON3 processor
generic map (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU*(1-CFG_GRFPUSH), CFG_V8,
0, CFG_MAC, pclow, CFG_NOTAG, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE,
CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ,
CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN,
CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP,
CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR, CFG_NCPU-1,
CFG_DFIXED, CFG_SCAN, CFG_MMU_PAGE, CFG_BP, CFG_NP_ASI, CFG_WRPSR)
port map (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso,
irqi(i), irqo(i), dbgi(i), dbgo(i));
end generate;
end generate;
nocpu : if CFG_LEON3 = 0 generate dbgo(0) <= dbgo_none; end generate;
led1_pad : outpad generic map (tech => padtech, level => cmos, voltage => x33v) port map (led(1), dbgo(0).error);
dsugen : if CFG_DSU = 1 generate
dsu0 : dsu3 -- LEON3 Debug Support Unit
generic map (hindex => 2, haddr => 16#900#, hmask => 16#F00#,
ncpu => CFG_NCPU, tbits => 30, tech => memtech, irq => 0, kbytes => CFG_ATBSZ)
port map (rstn, clkm, ahbmi, ahbsi, ahbso(2), dbgo, dbgi, dsui, dsuo);
dsui.enable <= '1';
dsui.break <= gpioi.val(0);
end generate;
dsuact_pad : outpad generic map (tech => padtech, level => cmos, voltage => x33v) port map (led(0), dsuo.active);
nodsu : if CFG_DSU = 0 generate
dsuo.tstop <= '0'; dsuo.active <= '0'; ahbso(2) <= ahbs_none;
end generate;
ahbjtaggen0 :if CFG_AHB_JTAG = 1 generate
ahbjtag0 : ahbjtag generic map(tech => fabtech, hindex => CFG_LEON3*CFG_NCPU)
port map(rstn, clkm, tck, tms, tdi, tdo, ahbmi, ahbmo(CFG_LEON3*CFG_NCPU),
open, open, open, open, open, open, open, gnd);
end generate;
leon3_zedboard_stub_i : leon3_zedboard_stub
port map (
DDR_ck_p => processing_system7_0_DDR_Clk,
DDR_ck_n => processing_system7_0_DDR_Clk_n,
DDR_cke => processing_system7_0_DDR_CKE,
DDR_cs_n => processing_system7_0_DDR_CS_n,
DDR_ras_n => processing_system7_0_DDR_RAS_n,
DDR_cas_n => processing_system7_0_DDR_CAS_n,
DDR_we_n => processing_system7_0_DDR_WEB_pin,
DDR_ba => processing_system7_0_DDR_BankAddr,
DDR_addr => processing_system7_0_DDR_Addr,
DDR_odt => processing_system7_0_DDR_ODT,
DDR_reset_n => processing_system7_0_DDR_DRSTB,
DDR_dq => processing_system7_0_DDR_DQ,
DDR_dm => processing_system7_0_DDR_DM,
DDR_dqs_p => processing_system7_0_DDR_DQS,
DDR_dqs_n => processing_system7_0_DDR_DQS_n,
FCLK_CLK0 => clkm,
FCLK_RESET0_N => rst,
FIXED_IO_mio => processing_system7_0_MIO,
FIXED_IO_ps_srstb => processing_system7_0_PS_SRSTB,
FIXED_IO_ps_clk => processing_system7_0_PS_CLK,
FIXED_IO_ps_porb => processing_system7_0_PS_PORB,
FIXED_IO_ddr_vrn => processing_system7_0_DDR_VRN,
FIXED_IO_ddr_vrp => processing_system7_0_DDR_VRP,
S_AXI_GP0_araddr => S_AXI_GP0_araddr,
S_AXI_GP0_arburst(1 downto 0) => S_AXI_GP0_arburst(1 downto 0),
S_AXI_GP0_arcache(3 downto 0) => S_AXI_GP0_arcache(3 downto 0),
S_AXI_GP0_arid => S_AXI_GP0_arid,
S_AXI_GP0_arlen => S_AXI_GP0_arlen,
S_AXI_GP0_arlock => S_AXI_GP0_arlock,
S_AXI_GP0_arprot(2 downto 0) => S_AXI_GP0_arprot(2 downto 0),
S_AXI_GP0_arqos => S_AXI_GP0_arqos,
S_AXI_GP0_awqos => S_AXI_GP0_awqos,
S_AXI_GP0_arready => S_AXI_GP0_arready,
S_AXI_GP0_arsize(2 downto 0) => S_AXI_GP0_arsize(2 downto 0),
S_AXI_GP0_arvalid => S_AXI_GP0_arvalid,
S_AXI_GP0_awaddr => S_AXI_GP0_awaddr,
S_AXI_GP0_awburst(1 downto 0) => S_AXI_GP0_awburst(1 downto 0),
S_AXI_GP0_awcache(3 downto 0) => S_AXI_GP0_awcache(3 downto 0),
S_AXI_GP0_awid => S_AXI_GP0_awid,
S_AXI_GP0_awlen => S_AXI_GP0_awlen,
S_AXI_GP0_awlock => S_AXI_GP0_awlock,
S_AXI_GP0_awprot(2 downto 0) => S_AXI_GP0_awprot(2 downto 0),
S_AXI_GP0_awready => S_AXI_GP0_awready,
S_AXI_GP0_awsize(2 downto 0) => S_AXI_GP0_awsize(2 downto 0),
S_AXI_GP0_awvalid => S_AXI_GP0_awvalid,
S_AXI_GP0_bid => S_AXI_GP0_bid,
S_AXI_GP0_bready => S_AXI_GP0_bready,
S_AXI_GP0_bresp(1 downto 0) => S_AXI_GP0_bresp(1 downto 0),
S_AXI_GP0_bvalid => S_AXI_GP0_bvalid,
S_AXI_GP0_rdata(31 downto 0) => S_AXI_GP0_rdata(31 downto 0),
S_AXI_GP0_rid => S_AXI_GP0_rid,
S_AXI_GP0_rlast => S_AXI_GP0_rlast,
S_AXI_GP0_rready => S_AXI_GP0_rready,
S_AXI_GP0_rresp(1 downto 0) => S_AXI_GP0_rresp(1 downto 0),
S_AXI_GP0_rvalid => S_AXI_GP0_rvalid,
S_AXI_GP0_wdata(31 downto 0) => S_AXI_GP0_wdata(31 downto 0),
S_AXI_GP0_wid => S_AXI_GP0_wid,
S_AXI_GP0_wlast => S_AXI_GP0_wlast,
S_AXI_GP0_wready => S_AXI_GP0_wready,
S_AXI_GP0_wstrb(3 downto 0) => S_AXI_GP0_wstrb(3 downto 0),
S_AXI_GP0_wvalid => S_AXI_GP0_wvalid
);
ahb2axi0 : entity work.ahb2axi
generic map(
hindex => 3, haddr => 16#400#, hmask => 16#F00#,
pindex => 0, paddr => 0, cidsz => CIDSZ, clensz => CLENSZ)
port map(
rstn => rstn,
clk => clkm,
ahbsi => ahbsi,
ahbso => ahbso(3),
apbi => apbi,
apbo => apbo(0),
M_AXI_araddr => S_AXI_GP0_araddr,
M_AXI_arburst(1 downto 0) => S_AXI_GP0_arburst(1 downto 0),
M_AXI_arcache(3 downto 0) => S_AXI_GP0_arcache(3 downto 0),
M_AXI_arid => S_AXI_GP0_arid,
M_AXI_arlen => S_AXI_GP0_arlen,
M_AXI_arlock => S_AXI_GP0_arlock,
M_AXI_arprot(2 downto 0) => S_AXI_GP0_arprot(2 downto 0),
M_AXI_arqos => S_AXI_GP0_arqos,
M_AXI_arready => S_AXI_GP0_arready,
M_AXI_arsize(2 downto 0) => S_AXI_GP0_arsize(2 downto 0),
M_AXI_arvalid => S_AXI_GP0_arvalid,
M_AXI_awaddr => S_AXI_GP0_awaddr,
M_AXI_awburst(1 downto 0) => S_AXI_GP0_awburst(1 downto 0),
M_AXI_awcache(3 downto 0) => S_AXI_GP0_awcache(3 downto 0),
M_AXI_awid => S_AXI_GP0_awid,
M_AXI_awlen => S_AXI_GP0_awlen,
M_AXI_awlock => S_AXI_GP0_awlock,
M_AXI_awprot(2 downto 0) => S_AXI_GP0_awprot(2 downto 0),
M_AXI_awqos => S_AXI_GP0_awqos,
M_AXI_awready => S_AXI_GP0_awready,
M_AXI_awsize(2 downto 0) => S_AXI_GP0_awsize(2 downto 0),
M_AXI_awvalid => S_AXI_GP0_awvalid,
M_AXI_bid => S_AXI_GP0_bid,
M_AXI_bready => S_AXI_GP0_bready,
M_AXI_bresp(1 downto 0) => S_AXI_GP0_bresp(1 downto 0),
M_AXI_bvalid => S_AXI_GP0_bvalid,
M_AXI_rdata(31 downto 0) => S_AXI_GP0_rdata(31 downto 0),
M_AXI_rid => S_AXI_GP0_rid,
M_AXI_rlast => S_AXI_GP0_rlast,
M_AXI_rready => S_AXI_GP0_rready,
M_AXI_rresp(1 downto 0) => S_AXI_GP0_rresp(1 downto 0),
M_AXI_rvalid => S_AXI_GP0_rvalid,
M_AXI_wdata(31 downto 0) => S_AXI_GP0_wdata(31 downto 0),
M_AXI_wlast => S_AXI_GP0_wlast,
M_AXI_wready => S_AXI_GP0_wready,
M_AXI_wstrb(3 downto 0) => S_AXI_GP0_wstrb(3 downto 0),
M_AXI_wvalid => S_AXI_GP0_wvalid
);
----------------------------------------------------------------------
--- APB Bridge and various periherals -------------------------------
----------------------------------------------------------------------
apb0 : apbctrl -- AHB/APB bridge
generic map (hindex => 1, haddr => CFG_APBADDR, nslaves => 16)
port map (rstn, clkm, ahbsi, ahbso(1), apbi, apbo );
irqgen : if CFG_LEON3 = 1 generate
irqctrl : if CFG_IRQ3_ENABLE /= 0 generate
irqctrl0 : irqmp -- interrupt controller
generic map (pindex => 2, paddr => 2, ncpu => CFG_NCPU)
port map (rstn, clkm, apbi, apbo(2), irqo, irqi);
end generate;
end generate;
irqctrl : if (CFG_IRQ3_ENABLE + CFG_LEON3) /= 2 generate
x : for i in 0 to CFG_NCPU-1 generate
irqi(i).irl <= "0000";
end generate;
apbo(2) <= apb_none;
end generate;
gpt : if CFG_GPT_ENABLE /= 0 generate
timer0 : gptimer -- timer unit
generic map (pindex => 3, paddr => 3, pirq => CFG_GPT_IRQ,
sepirq => CFG_GPT_SEPIRQ, sbits => CFG_GPT_SW, ntimers => CFG_GPT_NTIM,
nbits => CFG_GPT_TW, wdog => 0)
port map (rstn, clkm, apbi, apbo(3), gpti, gpto);
gpti <= gpti_dhalt_drive(dsuo.tstop);
end generate;
nogpt : if CFG_GPT_ENABLE = 0 generate apbo(3) <= apb_none; end generate;
gpio0 : if CFG_GRGPIO_ENABLE /= 0 generate -- GPIO unit
grgpio0: grgpio
generic map(pindex => 8, paddr => 8, imask => CFG_GRGPIO_IMASK, nbits => CFG_GRGPIO_WIDTH)
port map(rst => rstn, clk => clkm, apbi => apbi, apbo => apbo(8),
gpioi => gpioi, gpioo => gpioo);
pio_pad_0 : inpad generic map (tech => padtech)
port map (switch(0), gpioi.din(0)) -- Do not let SW modify BREAK input
pio_pads : for i in 1 to 7 generate
pio_pad : iopad generic map (tech => padtech, level => cmos, voltage => x18v)
port map (switch(i), gpioo.dout(i), gpioo.oen(i), gpioi.din(i));
end generate;
pio_pads2 : for i in 8 to 10 generate
pio_pad : inpad generic map (tech => padtech, level => cmos, voltage => x18v)
port map (button(i-8+1), gpioi.din(i));
end generate;
pio_pads3 : for i in 11 to 14 generate
pio_pad : outpad generic map (tech => padtech, level => cmos, voltage => x33v)
port map (led(i-11+4), gpioo.dout(i));
end generate;
end generate;
ua1 : if CFG_UART1_ENABLE /= 0 generate
uart1 : apbuart -- UART 1
generic map (pindex => 1, paddr => 1, pirq => 2, console => dbguart,
fifosize => CFG_UART1_FIFO)
port map (rstn, clkm, apbi, apbo(1), u1i, u1o);
u1i.rxd <= rxd1;
u1i.ctsn <= '0';
u1i.extclk <= '0';
txd1 <= u1o.txd;
end generate;
noua0 : if CFG_UART1_ENABLE = 0 generate apbo(1) <= apb_none; end generate;
hready_pad : outpad generic map (level => cmos, voltage => x33v, tech => padtech)
port map (led(2), ahbmi.hready);
rsti_pad : outpad generic map (level => cmos, voltage => x33v, tech => padtech)
port map (led(3), rsti);
ahbs : if CFG_AHBSTAT = 1 generate -- AHB status register
stati <= ahbstat_in_none;
ahbstat0 : ahbstat generic map (pindex => 15, paddr => 15, pirq => 7,
nftslv => CFG_AHBSTATN)
port map (rstn, clkm, ahbmi, ahbsi, stati, apbi, apbo(15));
end generate;
-----------------------------------------------------------------------
--- AHB ROM ----------------------------------------------------------
-----------------------------------------------------------------------
bpromgen : if CFG_AHBROMEN /= 0 generate
brom : entity work.ahbrom
generic map (hindex => 0, haddr => CFG_AHBRODDR, pipe => CFG_AHBROPIP)
port map ( rstn, clkm, ahbsi, ahbso(0));
end generate;
-----------------------------------------------------------------------
--- AHB RAM ----------------------------------------------------------
-----------------------------------------------------------------------
ocram : if CFG_AHBRAMEN = 1 generate
ahbram0 : ahbram generic map (hindex => 5, haddr => CFG_AHBRADDR,
tech => CFG_MEMTECH, kbytes => CFG_AHBRSZ, pipe => CFG_AHBRPIPE)
port map ( rstn, clkm, ahbsi, ahbso(5));
end generate;
-----------------------------------------------------------------------
--- Test report module ----------------------------------------------
-----------------------------------------------------------------------
-- pragma translate_off
test0_gen : if (testahb = true) generate
test0 : ahbrep generic map (hindex => 6, haddr => 16#200#)
port map (rstn, clkm, ahbsi, ahbso(6));
end generate;
-- pragma translate_on
-----------------------------------------------------------------------
--- Drive unused bus elements ---------------------------------------
-----------------------------------------------------------------------
nam1 : for i in (maxahbs+1) to NAHBMST-1 generate
ahbmo(i) <= ahbm_none;
end generate;
-----------------------------------------------------------------------
--- Boot message ----------------------------------------------------
-----------------------------------------------------------------------
-- pragma translate_off
x : report_design
generic map (
msg1 => "LEON3 Xilinx Zedboard Demonstration design",
fabtech => tech_table(fabtech), memtech => tech_table(memtech),
mdel => 1
);
-- pragma translate_on
end;
| gpl-3.0 | fb94fb2385dc903d83c29041645efcff | 0.570573 | 3.245581 | false | false | false | false |
EliasLuiz/TCC | Leon3/designs/leon3-digilent-nexys-video/leon3mp.vhd | 1 | 27,309 | ------------------------------------------------------------------------------
-- LEON3 Demonstration design
-- Copyright (C) 2016 Cobham Gaisler
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
library techmap;
use techmap.gencomp.all;
use techmap.allclkgen.all;
library gaisler;
use gaisler.memctrl.all;
use gaisler.leon3.all;
use gaisler.uart.all;
use gaisler.misc.all;
use gaisler.spi.all;
use gaisler.net.all;
use gaisler.jtag.all;
use gaisler.ddrpkg.all;
--pragma translate_off
use gaisler.sim.all;
library unisim;
use unisim.all;
--pragma translate_on
library esa;
use esa.memoryctrl.all;
use work.config.all;
entity leon3mp is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
clktech : integer := CFG_CLKTECH;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW;
SIM_BYPASS_INIT_CAL : string := "OFF";
SIMULATION : string := "FALSE";
USE_MIG_INTERFACE_MODEL : boolean := false
);
port (
sysclk : in std_ulogic;
-- LEDs
led : out std_logic_vector(7 downto 0);
-- Buttons
btnc : in std_ulogic;
btnd : in std_ulogic;
btnl : in std_ulogic;
btnr : in std_ulogic;
cpu_resetn : in std_ulogic;
-- Switches
sw : in std_logic_vector(7 downto 0);
-- USB-RS232 interface
uart_tx_in : in std_logic;
uart_rx_out : out std_logic;
-- DDR3
ddr3_dq : inout std_logic_vector(15 downto 0);
ddr3_dqs_p : inout std_logic_vector(1 downto 0);
ddr3_dqs_n : inout std_logic_vector(1 downto 0);
ddr3_addr : out std_logic_vector(14 downto 0);
ddr3_ba : out std_logic_vector(2 downto 0);
ddr3_ras_n : out std_logic;
ddr3_cas_n : out std_logic;
ddr3_we_n : out std_logic;
ddr3_reset_n : out std_logic;
ddr3_ck_p : out std_logic_vector(0 downto 0);
ddr3_ck_n : out std_logic_vector(0 downto 0);
ddr3_cke : out std_logic_vector(0 downto 0);
ddr3_dm : out std_logic_vector(1 downto 0);
ddr3_odt : out std_logic_vector(0 downto 0);
-- Ethernet
--eth_int_b : in std_logic;
--eth_mdc : out std_logic;
--eth_mdio : inout std_logic;
--eth_pme_b : out std_ulogic;
--eth_rst_b : out std_logic;
--eth_rxck : in std_logic;
--eth_rxctl : in std_logic;
--eth_rxd : in std_logic_vector(3 downto 0);
--eth_txck : in std_logic;
--eth_txctl : out std_logic;
--eth_txd : out std_logic_vector(3 downto 0);
phy_txclk : out std_logic;
phy_txd : out std_logic_vector(3 downto 0);
phy_txctl_txen : out std_ulogic;
phy_rxd : in std_logic_vector(3 downto 0);
phy_rxctl_rxdv : in std_ulogic;
phy_rxclk : in std_ulogic;
phy_reset : out std_ulogic;
phy_mdio : inout std_logic;
phy_mdc : out std_ulogic;
phy_int : in std_ulogic;
-- Fan PWM
fan_pwm : out std_ulogic;
-- SPI
qspi_cs : out std_ulogic;
qspi_dq : inout std_logic_vector(3 downto 0);
scl : out std_ulogic
);
end;
architecture rtl of leon3mp is
component IDELAYCTRL
port (
RDY : out std_ulogic;
REFCLK : in std_ulogic;
RST : in std_ulogic
);
end component;
component IODELAYE1
generic (
DELAY_SRC : string := "I";
IDELAY_TYPE : string := "DEFAULT";
IDELAY_VALUE : integer := 0;
ODELAY_VALUE : integer := 0
);
port (
CNTVALUEOUT : out std_logic_vector(4 downto 0);
DATAOUT : out std_ulogic;
C : in std_ulogic;
CE : in std_ulogic;
CINVCTRL : in std_ulogic;
CLKIN : in std_ulogic;
CNTVALUEIN : in std_logic_vector(4 downto 0);
DATAIN : in std_ulogic;
IDATAIN : in std_ulogic;
INC : in std_ulogic;
ODATAIN : in std_ulogic;
RST : in std_ulogic;
T : in std_ulogic
);
end component;
component ODELAYE2
generic (
ODELAY_VALUE : integer := 0
);
port (
C : in std_ulogic;
REGRST : in std_ulogic;
LD : in std_ulogic;
CE : in std_ulogic;
INC : in std_ulogic;
CINVCTRL : in std_ulogic;
CNTVALUEIN : in std_logic_vector(4 downto 0);
CLKIN : in std_ulogic;
ODATAIN : in std_ulogic;
LDPIPEEN : in std_ulogic;
DATAOUT : out std_ulogic;
CNTVALUEOUT : out std_logic_vector(4 downto 0)
);
end component;
signal vcc : std_logic;
signal gnd : std_logic;
signal gpioi : gpio_in_type;
signal gpioo : gpio_out_type;
signal apbi : apb_slv_in_type;
signal apbo : apb_slv_out_vector := (others => apb_none);
signal ahbsi : ahb_slv_in_type;
signal ahbso : ahb_slv_out_vector := (others => ahbs_none);
signal ahbmi : ahb_mst_in_type;
signal ahbmo : ahb_mst_out_vector := (others => ahbm_none);
signal cgi : clkgen_in_type;
signal cgo, cgo1 : clkgen_out_type;
signal cgi2 : clkgen_in_type;
signal cgo2 : clkgen_out_type;
signal u1i, dui : uart_in_type;
signal u1o, duo : uart_out_type;
signal irqi : irq_in_vector(0 to CFG_NCPU-1);
signal irqo : irq_out_vector(0 to CFG_NCPU-1);
signal dbgi : l3_debug_in_vector(0 to CFG_NCPU-1);
signal dbgo : l3_debug_out_vector(0 to CFG_NCPU-1);
signal dsui : dsu_in_type;
signal dsuo : dsu_out_type;
signal ndsuact : std_ulogic;
signal ethi : eth_in_type;
signal etho : eth_out_type;
signal gpti : gptimer_in_type;
signal spmi : spimctrl_in_type;
signal spmo : spimctrl_out_type;
signal clkm : std_ulogic
-- pragma translate_off
:= '0'
-- pragma translate_on
;
signal clkm2x, rstn : std_ulogic;
signal tck, tms, tdi, tdo : std_ulogic;
signal rstraw : std_logic;
signal lcpu_resetn : std_logic;
signal lock : std_logic;
signal clkinmig : std_logic;
signal clkref, calib_done, migrstn : std_logic;
signal gmiii : eth_in_type;
signal gmiio : eth_out_type;
signal rgmiii,rgmiii_buf : eth_in_type;
signal rgmiio : eth_out_type;
signal ethernet_phy_int : std_logic;
signal rxd1 : std_logic;
signal txd1 : std_logic;
--signal ethi : eth_in_type;
--signal etho : eth_out_type;
signal gtx_clk,gtx_clk_nobuf,gtx_clk90 : std_ulogic;
signal rstgtxn : std_logic;
signal idelay_reset_cnt : std_logic_vector(3 downto 0);
signal idelayctrl_reset : std_logic;
signal io_ref : std_logic;
signal phy_txclk_delay : std_logic;
attribute keep : boolean;
attribute syn_keep : boolean;
attribute syn_preserve : boolean;
attribute syn_keep of lock : signal is true;
attribute syn_keep of clkm : signal is true;
attribute syn_preserve of clkm : signal is true;
attribute keep of lock : signal is true;
attribute keep of clkm : signal is true;
constant BOARD_FREQ : integer := 100000; -- CLK input frequency in KHz
constant CPU_FREQ : integer := BOARD_FREQ * CFG_CLKMUL / CFG_CLKDIV; -- cpu frequency in KHz
begin
vcc <= '1'; gnd <= '0';
----------------------------------------------------------------------
--- Reset and Clock generation -------------------------------------
----------------------------------------------------------------------
cgi.pllctrl <= "00";
cgi.pllrst <= rstraw;
rst_pad : inpad generic map (tech => padtech, level => cmos, voltage => x15v)
port map (cpu_resetn, lcpu_resetn);
rst0 : rstgen
port map (lcpu_resetn, clkm, lock, rstn, rstraw);
lock <= calib_done when CFG_MIG_7SERIES = 1 else cgo.clklock;
rst1 : rstgen -- reset generator
port map (lcpu_resetn, clkm, vcc, migrstn, open);
-- clock generator
clkgen_gen: if (CFG_MIG_7SERIES = 0) generate
clkgen0 : clkgen
generic map (fabtech, CFG_CLKMUL, CFG_CLKDIV, 0, 0, 0, 0, 0, BOARD_FREQ, 0)
port map (sysclk, gnd, clkm, open, clkm2x, open, open, cgi, cgo, open, open, open);
end generate;
led(7) <= lcpu_resetn;
led(6) <= calib_done;
led(5) <= rstn;
led(4) <= lock; -- Used in TB
----------------------------------------------------------------------
--- AHB CONTROLLER --------------------------------------------------
----------------------------------------------------------------------
ahb0 : ahbctrl
generic map (defmast => CFG_DEFMST, split => CFG_SPLIT,
rrobin => CFG_RROBIN, ioaddr => CFG_AHBIO, ioen => 1,
nahbm => CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_GRETH,
nahbs => 8)
port map (rstn, clkm, ahbmi, ahbmo, ahbsi, ahbso);
----------------------------------------------------------------------
--- LEON3 processor and DSU -----------------------------------------
----------------------------------------------------------------------
-- LEON3 processor
leon3gen : if CFG_LEON3 = 1 generate
cpu : for i in 0 to CFG_NCPU-1 generate
u0 : leon3s
generic map (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU, CFG_V8,
0, CFG_MAC, pclow, CFG_NOTAG, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE,
CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ,
CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN,
CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP,
CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR,
CFG_NCPU-1, CFG_DFIXED, CFG_SCAN, CFG_MMU_PAGE, CFG_BP, CFG_NP_ASI, CFG_WRPSR,
CFG_REX, CFG_ALTWIN)
port map (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso, irqi(i), irqo(i), dbgi(i), dbgo(i));
end generate;
led(3) <= not dbgo(0).error;
led(2) <= not dsuo.active;
-- LEON3 Debug Support Unit
dsugen : if CFG_DSU = 1 generate
dsu0 : dsu3
generic map (hindex => 2, haddr => 16#900#, hmask => 16#F00#, ahbpf => CFG_AHBPF,
ncpu => CFG_NCPU, tbits => 30, tech => memtech, irq => 0, kbytes => CFG_ATBSZ)
port map (rstn, clkm, ahbmi, ahbsi, ahbso(2), dbgo, dbgi, dsui, dsuo);
--dsubre_pad : inpad generic map (tech => padtech) port map (dsubre, dsui.break);
dsui.enable <= '1';
end generate;
end generate;
nodsu : if CFG_DSU = 0 generate
ahbso(2) <= ahbs_none; dsuo.tstop <= '0'; dsuo.active <= '0';
end generate;
-- Debug UART
dcomgen : if CFG_AHB_UART = 1 generate
dcom0 : ahbuart
generic map (hindex => CFG_NCPU, pindex => 4, paddr => 7)
port map (rstn, clkm, dui, duo, apbi, apbo(4), ahbmi, ahbmo(CFG_NCPU));
dsurx_pad : inpad generic map (tech => padtech) port map (uart_tx_in, dui.rxd);
dsutx_pad : outpad generic map (tech => padtech) port map (uart_rx_out, duo.txd);
led(0) <= not dui.rxd;
led(1) <= not duo.txd;
end generate;
nouah : if CFG_AHB_UART = 0 generate apbo(4) <= apb_none; end generate;
ahbjtaggen0 :if CFG_AHB_JTAG = 1 generate
ahbjtag0 : ahbjtag generic map(tech => fabtech, hindex => CFG_NCPU+CFG_AHB_UART)
port map(rstn, clkm, tck, tms, tdi, tdo, ahbmi, ahbmo(CFG_NCPU+CFG_AHB_UART),
open, open, open, open, open, open, open, gnd);
end generate;
----------------------------------------------------------------------
--- DDR3 Memory controller ------------------------------------------
----------------------------------------------------------------------
-- nomig : if (CFG_MIG_7SERIES = 0) generate end generate;
mig_gen : if (CFG_MIG_7SERIES = 1) generate
gen_mig : if (USE_MIG_INTERFACE_MODEL /= true) generate
ddrc : ahb2mig_7series_ddr3_dq16_ad15_ba3 generic map(
hindex => 5, haddr => 16#400#, hmask => 16#F00#, pindex => 5, paddr => 5,
SIM_BYPASS_INIT_CAL => SIM_BYPASS_INIT_CAL, SIMULATION => SIMULATION,
USE_MIG_INTERFACE_MODEL => USE_MIG_INTERFACE_MODEL)
port map(
ddr3_dq => ddr3_dq,
ddr3_dqs_p => ddr3_dqs_p,
ddr3_dqs_n => ddr3_dqs_n,
ddr3_addr => ddr3_addr,
ddr3_ba => ddr3_ba,
ddr3_ras_n => ddr3_ras_n,
ddr3_cas_n => ddr3_cas_n,
ddr3_we_n => ddr3_we_n,
ddr3_reset_n => ddr3_reset_n,
ddr3_ck_p => ddr3_ck_p,
ddr3_ck_n => ddr3_ck_n,
ddr3_cke => ddr3_cke,
ddr3_dm => ddr3_dm,
ddr3_odt => ddr3_odt,
ahbsi => ahbsi,
ahbso => ahbso(5),
apbi => apbi,
apbo => apbo(5),
calib_done => calib_done,
rst_n_syn => migrstn,
rst_n_async => cgo1.clklock,--rstraw,
clk_amba => clkm,
sys_clk_i => clkinmig,
-- clk_ref_i => clkref,
ui_clk => clkm, -- 100 MHz clk , DDR at 400 MHz
ui_clk_sync_rst => open);
clkgenmigin : clkgen
generic map (clktech, 8, 4, 0, CFG_CLK_NOFB, 0, 0, 0, 100000)
port map (sysclk, sysclk, clkinmig, open, open, open, open, cgi, cgo1, open, open, open);
end generate gen_mig;
gen_mig_model : if (USE_MIG_INTERFACE_MODEL = true) generate
-- pragma translate_off
mig_ahbram : ahbram_sim
generic map (
hindex => 5,
haddr => 16#400#,
hmask => 16#F80#,
tech => 0,
kbytes => 1000,
pipe => 0,
maccsz => AHBDW,
fname => "ram.srec"
)
port map(
rst => rstn,
clk => clkm,
ahbsi => ahbsi,
ahbso => ahbso(5)
);
ddr3_dq <= (others => 'Z');
ddr3_dqs_p <= (others => 'Z');
ddr3_dqs_n <= (others => 'Z');
ddr3_addr <= (others => '0');
ddr3_ba <= (others => '0');
ddr3_ras_n <= '0';
ddr3_cas_n <= '0';
ddr3_we_n <= '0';
ddr3_ck_p <= (others => '0');
ddr3_ck_n <= (others => '0');
ddr3_cke <= (others => '0');
ddr3_dm <= (others => '0');
ddr3_odt <= (others => '0');
--calib_done : out std_logic;
calib_done <= '1';
--ui_clk : out std_logic;
clkm <= not clkm after 10.0 ns;
--ui_clk_sync_rst : out std_logic
-- n/a
-- pragma translate_on
end generate gen_mig_model; end generate;
----------------------------------------------------------------------
--- SPI Memory controller -------------------------------------------
----------------------------------------------------------------------
spi_gen: if CFG_SPIMCTRL = 1 generate
-- OPTIONALY set the offset generic (only affect reads).
-- The first 4MB are used for loading the FPGA.
-- For dual ouptut: readcmd => 16#3B#, dualoutput => 1
spimctrl1 : spimctrl
generic map (hindex => 7, hirq => 7, faddr => 16#000#, fmask => 16#ff0#,
ioaddr => 16#700#, iomask => 16#fff#, spliten => CFG_SPLIT,
sdcard => CFG_SPIMCTRL_SDCARD, readcmd => CFG_SPIMCTRL_READCMD,
dummybyte => CFG_SPIMCTRL_DUMMYBYTE,
dualoutput => CFG_SPIMCTRL_DUALOUTPUT, scaler => CFG_SPIMCTRL_SCALER,
altscaler => CFG_SPIMCTRL_ASCALER)
port map (rstn, clkm, ahbsi, ahbso(7), spmi, spmo);
qspi_dq(3) <= '1'; qspi_dq(2) <= '1';
spi_mosi_pad : outpad generic map (tech => padtech)
port map (qspi_dq(0), spmo.mosi);
spi_miso_pad : inpad generic map (tech => padtech)
port map (qspi_dq(1), spmi.miso);
spi_slvsel0_pad : outpad generic map (tech => padtech)
port map (qspi_cs, spmo.csn);
spi_sck_pad : outpad generic map (tech => padtech)
port map (scl, spmo.sck);
end generate;
nospi: if CFG_SPIMCTRL = 0 generate
ahbso(7) <= ahbs_none;
end generate;
----------------------------------------------------------------------
--- APB Bridge and various periherals -------------------------------
----------------------------------------------------------------------
-- APB Bridge
apb0 : apbctrl
generic map (hindex => 1, haddr => CFG_APBADDR)
port map (rstn, clkm, ahbsi, ahbso(1), apbi, apbo);
-- Interrupt controller
irqctrl : if CFG_IRQ3_ENABLE /= 0 generate
irqctrl0 : irqmp
generic map (pindex => 2, paddr => 2, ncpu => CFG_NCPU)
port map (rstn, clkm, apbi, apbo(2), irqo, irqi);
end generate;
irq3 : if CFG_IRQ3_ENABLE = 0 generate
x : for i in 0 to CFG_NCPU-1 generate
irqi(i).irl <= "0000";
end generate;
apbo(2) <= apb_none;
end generate;
-- Timer Unit
gpt : if CFG_GPT_ENABLE /= 0 generate
timer0 : gptimer
generic map (pindex => 3, paddr => 3, pirq => CFG_GPT_IRQ,
sepirq => CFG_GPT_SEPIRQ, sbits => CFG_GPT_SW,
ntimers => CFG_GPT_NTIM, nbits => CFG_GPT_TW)
port map (rstn, clkm, apbi, apbo(3), gpti, open);
gpti <= gpti_dhalt_drive(dsuo.tstop);
end generate;
notim : if CFG_GPT_ENABLE = 0 generate apbo(3) <= apb_none; end generate;
ua1 : if CFG_UART1_ENABLE /= 0 generate
uart1 : apbuart -- UART 1
generic map (pindex => 1, paddr => 1, pirq => 2, console => dbguart, fifosize => CFG_UART1_FIFO)
port map (rstn, clkm, apbi, apbo(1), u1i, u1o);
u1i.rxd <= rxd1;
u1i.ctsn <= '0';
u1i.extclk <= '0';
txd1 <= u1o.txd;
end generate;
noua0 : if CFG_UART1_ENABLE = 0 generate apbo(1) <= apb_none; end generate;
-----------------------------------------------------------------------
--- ETHERNET ---------------------------------------------------------
-----------------------------------------------------------------------
eth0 : if CFG_GRETH = 1 generate -- Gaisler ethernet MAC
e1 : grethm
generic map(
hindex => CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG,
pindex => 15, paddr => 15, pirq => 12, memtech => memtech,
mdcscaler => CPU_FREQ/1000, rmii => 0, enable_mdio => 1, fifosize => CFG_ETH_FIFO,
nsync => 2, edcl => CFG_DSU_ETH, edclbufsz => CFG_ETH_BUF, phyrstadr => 1,
macaddrh => CFG_ETH_ENM, macaddrl => CFG_ETH_ENL, enable_mdint => 1,
ipaddrh => CFG_ETH_IPM, ipaddrl => CFG_ETH_IPL,
giga => CFG_GRETH1G, ramdebug => 0, gmiimode => 1)
port map( rst => rstn, clk => clkm, ahbmi => ahbmi,
ahbmo => ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG),
apbi => apbi, apbo => apbo(15), ethi => ethi, etho => etho);
-----------------------------------------------------------------------------
-- An IDELAYCTRL primitive needs to be instantiated for the Fixed Tap Delay
-- mode of the IDELAY.
-- All IDELAYs in Fixed Tap Delay mode and the IDELAYCTRL primitives have
-- to be LOC'ed in the UCF file.
-----------------------------------------------------------------------------
dlyctrl0 : IDELAYCTRL port map (
RDY => OPEN,
REFCLK => sysclk,
RST => idelayctrl_reset
);
delay_rgmii_rx_ctl0 : IODELAYE1 generic map(
DELAY_SRC => "I",
IDELAY_TYPE => "FIXED",
IDELAY_VALUE => 20,
ODELAY_VALUE => 20
)
port map(
IDATAIN => rgmiii_buf.rx_dv,
ODATAIN => '0',
DATAOUT => rgmiii.rx_dv,
DATAIN => '0',
C => '0',
T => '1',
CE => '0',
INC => '0',
CINVCTRL => '0',
CLKIN => '0',
CNTVALUEIN => "00000",
CNTVALUEOUT => OPEN,
RST => '0'
);
rgmii_rxd : for i in 0 to 3 generate
delay_rgmii_rxd0 : IODELAYE1 generic map(
DELAY_SRC => "I",
IDELAY_TYPE => "FIXED",
IDELAY_VALUE => 20,
ODELAY_VALUE => 20
)
port map(
IDATAIN => rgmiii_buf.rxd(i),
ODATAIN => '0',
DATAOUT => rgmiii.rxd(i),
DATAIN => '0',
C => '0',
T => '1',
CE => '0',
INC => '0',
CINVCTRL => '0',
CLKIN => '0',
CNTVALUEIN => "00000",
CNTVALUEOUT => OPEN,
RST => '0'
);
end generate;
phy_txclk_delay <= rgmiio.tx_clk;
-- Generate a synchron delayed reset for Xilinx IO delay
rst1 : rstgen
generic map (acthigh => 1)
port map (lcpu_resetn, sysclk, lock, rstgtxn, OPEN);
process (sysclk,rstgtxn)
begin
if (rstgtxn = '0') then
idelay_reset_cnt <= (others => '0');
idelayctrl_reset <= '1';
elsif rising_edge(sysclk) then
if (idelay_reset_cnt > "1110") then
idelay_reset_cnt <= (others => '1');
idelayctrl_reset <= '0';
else
idelay_reset_cnt <= idelay_reset_cnt + 1;
idelayctrl_reset <= '1';
end if;
end if;
end process;
-- RGMII Interface
rgmii0 : rgmii generic map (pindex => 11, paddr => 16#010#, pmask => 16#ff0#, tech => fabtech,
gmii => CFG_GRETH1G, debugmem => 1, abits => 8, no_clk_mux => 0,
pirq => 11, use90degtxclk => 0, mode100 => 1)
port map (rstn, ethi, etho, rgmiii, rgmiio, clkm, rstn, apbi, apbo(11));
egtxc_pad : outpad generic map (tech => padtech, level => cmos, voltage => x25v, slew => 1)
port map (phy_txclk, phy_txclk_delay);
erxc_pad : clkpad generic map (tech => padtech, level => cmos, voltage => x25v, arch => 1)
port map (phy_rxclk, rgmiii.rx_clk);
erxd_pad : inpadv generic map (tech => padtech, level => cmos, voltage => x25v, width => 4)
port map (phy_rxd, rgmiii_buf.rxd(3 downto 0));
erxdv_pad : inpad generic map (tech => padtech, level => cmos, voltage => x25v)
port map (phy_rxctl_rxdv, rgmiii_buf.rx_dv);
etxd_pad : outpadv generic map (tech => padtech, level => cmos, voltage => x25v, slew => 1, width => 4)
port map (phy_txd, rgmiio.txd(3 downto 0));
etxen_pad : outpad generic map (tech => padtech, level => cmos, voltage => x25v, slew => 1)
port map (phy_txctl_txen, rgmiio.tx_en);
emdio_pad : iopad generic map (tech => padtech, level => cmos, voltage => x25v)
port map (phy_mdio, rgmiio.mdio_o, rgmiio.mdio_oe, rgmiii.mdio_i);
emdc_pad : outpad generic map (tech => padtech, level => cmos, voltage => x25v)
port map (phy_mdc, rgmiio.mdc);
eint_pad : inpad generic map (tech => padtech, level => cmos, voltage => x25v)
port map (phy_int, rgmiii.mdint);
erst_pad : outpad generic map (tech => padtech, level => cmos, voltage => x25v)
port map (phy_reset, rgmiio.reset);
-- Use system clock for RGMII interface
rgmiii.gtx_clk <= clkm;
end generate;
noeth0 : if CFG_GRETH = 0 generate
-- TODO:
end generate;
-----------------------------------------------------------------------
--- AHB ROM ----------------------------------------------------------
-----------------------------------------------------------------------
bpromgen : if CFG_AHBROMEN /= 0 generate
brom : entity work.ahbrom
generic map (hindex => 6, haddr => CFG_AHBRODDR, pipe => CFG_AHBROPIP)
port map ( rstn, clkm, ahbsi, ahbso(6));
end generate;
nobpromgen : if CFG_AHBROMEN = 0 generate
ahbso(6) <= ahbs_none;
end generate;
-----------------------------------------------------------------------
--- AHB RAM ----------------------------------------------------------
-----------------------------------------------------------------------
ahbramgen : if CFG_AHBRAMEN = 1 generate
ahbram0 : ahbram
generic map (hindex => 3, haddr => CFG_AHBRADDR, tech => CFG_MEMTECH,
kbytes => CFG_AHBRSZ, pipe => CFG_AHBRPIPE)
port map (rstn, clkm, ahbsi, ahbso(3));
end generate;
nram : if CFG_AHBRAMEN = 0 generate ahbso(3) <= ahbs_none; end generate;
-----------------------------------------------------------------------
-- Test report module, only used for simulation ----------------------
-----------------------------------------------------------------------
--pragma translate_off
test0 : ahbrep generic map (hindex => 4, haddr => 16#200#)
port map (rstn, clkm, ahbsi, ahbso(4));
--pragma translate_on
-----------------------------------------------------------------------
--- Drive unused bus elements ---------------------------------------
-----------------------------------------------------------------------
nam1 : for i in (CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_GRETH+1) to NAHBMST-1 generate
ahbmo(i) <= ahbm_none;
end generate;
-----------------------------------------------------------------------
--- Boot message ----------------------------------------------------
-----------------------------------------------------------------------
-- pragma translate_off
x : report_design
generic map (
msg1 => "LEON3 Demonstration design for Digilent Nexys Video board",
fabtech => tech_table(fabtech), memtech => tech_table(memtech),
mdel => 1
);
-- pragma translate_on
end rtl;
| gpl-3.0 | 011e8866865fd07f7bd9c9ce5a230cec | 0.500348 | 3.84309 | false | false | false | false |
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