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michaelfivez/ascon_hardware_implementation | ascon128128_unrolled2/Kernel/Ascon_block_datapath.vhd | 1 | 6,204 | -------------------------------------------------------------------------------
--! @project Unrolled (factor 2) hardware implementation of Asconv128128
--! @author Michael Fivez
--! @license This project is released under the GNU Public License.
--! The license and distribution terms for this file may be
--! found in the file LICENSE in this distribution or at
--! http://www.gnu.org/licenses/gpl-3.0.txt
--! @note This is an hardware implementation made for my graduation thesis
--! at the KULeuven, in the COSIC department (year 2015-2016)
--! The thesis is titled 'Energy efficient hardware implementations of CAESAR submissions',
--! and can be found on the COSIC website (www.esat.kuleuven.be/cosic/publications)
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity Ascon_StateUpdate_datapath is
port(
Clk : in std_logic; -- Clock
Reset : in std_logic; -- Reset (synchronous)
-- Control signals
RoundNr : in std_logic_vector(2 downto 0);
sel1,sel2,sel3,sel4 : in std_logic_vector(1 downto 0);
sel0 : in std_logic_vector(2 downto 0);
selout : in std_logic;
Reg0En,Reg1En,Reg2En,Reg3En,Reg4En,RegOutEn : in std_logic;
ActivateGen : in std_logic;
GenSize : in std_logic_vector(3 downto 0);
-- Data signals
IV : in std_logic_vector(127 downto 0);
Key : in std_logic_vector(127 downto 0);
DataIn : in std_logic_vector(127 downto 0);
DataOut : out std_logic_vector(127 downto 0)
);
end entity Ascon_StateUpdate_datapath;
architecture structural of Ascon_StateUpdate_datapath is
-- constants
constant EXTRAIV : std_logic_vector(63 downto 0) := x"80800c0800000000"; -- used in the initialization
constant SEPCONSTANT : std_logic_vector(63 downto 0) := x"0000000000000001";
constant ADCONSTANT : std_logic_vector(63 downto 0) := x"8000000000000000";
-- Register signals
signal Reg0In,Reg1In,Reg2In,Reg3In,Reg4In : std_logic_vector(63 downto 0);
signal Reg0Out,Reg1Out,Reg2Out,Reg3Out,Reg4Out : std_logic_vector(63 downto 0);
signal RegOutIn,RegOutOut : std_logic_vector(127 downto 0);
-- Internal signals on datapath
signal SboxOut0,SboxOut1,SboxOut2,SboxOut3,SboxOut4 : std_logic_vector(63 downto 0);
signal DiffOut0,DiffOut1,DiffOut2,DiffOut3,DiffOut4 : std_logic_vector(63 downto 0);
signal XorReg01,XorReg02,XorReg11,XorReg12 : std_logic_vector(63 downto 0);
signal XorReg2,XorReg31,XorReg32,XorReg4 : std_logic_vector(63 downto 0);
signal OutSig0,OutSig1 : std_logic_vector(127 downto 0);
begin
-- declare and connect all sub entities
rounds: entity work.Fullrounds port map(Reg0Out,Reg1Out,Reg2Out,Reg3Out,Reg4Out,RoundNr,DiffOut0,DiffOut1,DiffOut2,DiffOut3,DiffOut4);
outpgen: entity work.OutputGenerator port map(Reg0Out,Reg1Out,DataIn,GenSize,ActivateGen,XorReg01,XorReg11,OutSig0); -- ActivateGen is a bit that indicates decryption or not
---------------------------------------------
------ Combinatorial logic for a round ------
---------------------------------------------
datapath: process(IV,Key,DataIn,Reg0Out,Reg1Out,Reg2Out,Reg3Out,Reg4Out,RegOutOut, -- inputs blocks and registers
SboxOut0,SboxOut1,SboxOut2,SboxOut3,SboxOut4,DiffOut0,DiffOut1,DiffOut2,DiffOut3,DiffOut4, -- internal signals
XorReg01,XorReg02,XorReg11,XorReg12,XorReg2,XorReg31,XorReg32,XorReg4,OutSig0,OutSig1, -- internal signals
RoundNr,sel0,sel1,sel2,sel3,sel4,ActivateGen,selout,GenSize) is -- control signals
begin
-- Set correct inputs in registers
if sel0 = "000" then
Reg0In <= DiffOut0;
elsif sel0 = "001" then
Reg0In <= EXTRAIV;
elsif sel0 = "010" then
Reg0In <= XorReg01;
elsif sel0 = "011" then
Reg0In <= XorReg02;
else
Reg0In <= Reg0Out xor ADCONSTANT;
end if;
if sel1 = "00" then
Reg1In <= DiffOut1;
elsif sel1 = "01" then
Reg1In <= Key(127 downto 64);
elsif sel1 = "10" then
Reg1In <= XorReg11;
else
Reg1In <= XorReg12;
end if;
if sel2 = "00" then
Reg2In <= DiffOut2;
elsif sel2 = "01" then
Reg2In <= Key(63 downto 0);
else
Reg2In <= XorReg2;
end if;
if sel3 = "00" then
Reg3In <= DiffOut3;
elsif sel3 = "01" then
Reg3In <= IV(127 downto 64);
elsif sel3 = "10" then
Reg3In <= XorReg31;
else
Reg3In <= XorReg32;
end if;
if sel4 = "00" then
Reg4In <= DiffOut4;
elsif sel4 = "01" then
Reg4In <= IV(63 downto 0);
elsif sel4 = "10" then
Reg4In <= XorReg4;
else
Reg4In <= Reg4Out xor SEPCONSTANT;
end if;
XorReg02 <= Reg0Out xor Key(127 downto 64);
XorReg12 <= Reg1Out xor Key(63 downto 0);
XorReg2 <= Reg2Out xor Key(127 downto 64);
XorReg31 <= Reg3Out xor Key(127 downto 64);
XorReg32 <= Reg3Out xor Key(63 downto 0);
XorReg4 <= Reg4Out xor Key(63 downto 0);
-- Set output
OutSig1(127 downto 64) <= XorReg31;
OutSig1(63 downto 0) <= XorReg4;
if selout = '0' then
RegOutIn <= OutSig0;
else
RegOutIn <= OutSig1;
end if;
DataOut <= RegOutOut;
end process datapath;
---------------------------------------------
------ The registers in the datapath --------
---------------------------------------------
registerdatapath : process(Clk,Reset) is
begin
if(Clk = '1' and Clk'event) then
if Reset = '1' then -- synchronous reset
Reg0Out <= (others => '0');
Reg1Out <= (others => '0');
Reg2Out <= (others => '0');
Reg3Out <= (others => '0');
Reg4Out <= (others => '0');
RegOutOut <= (others => '0');
else
-- update registers with enable
if Reg0En = '1' then
Reg0Out <= Reg0In;
end if;
if Reg1En = '1' then
Reg1Out <= Reg1In;
end if;
if Reg2En = '1' then
Reg2Out <= Reg2In;
end if;
if Reg3En = '1' then
Reg3Out <= Reg3In;
end if;
if Reg4En = '1' then
Reg4Out <= Reg4In;
end if;
if RegOutEn = '1' then
RegOutOut <= RegOutIn;
end if;
end if;
end if;
end process registerdatapath;
end architecture structural;
| gpl-3.0 | d410e87998f597b4eae48350982feede | 0.624919 | 3.056158 | false | false | false | false |
SteffenReith/J1Sc | vprj/vhdl/J1Sc/J1Sc/J1Sc.srcs/sources_1/imports/J1Sc/src/main/vhdl/arch/Nexys4DDR/Board_Nexys4DDR.vhd | 2 | 3,813 | --------------------------------------------------------------------------------
--
-- Creation Date: Fri Apr 7 16:00:52 GMT+2 2017
-- Creator: Steffen Reith
-- Module Name: Board_Nexys4DDR - Behavioral
-- Project Name: J1Sc - A simple J1 implementation in Scala using Spinal HDL
--
-- Remark: The pmod pins are renumberd as follows 1 -> 0, 2 -> 1, 3 -> 2,
-- 4 -> 3, 7 -> 4, 8 -> 5, 9 -> 6, 10 -> 7
--
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity Board_Nexys4DDR is
port (nreset : in std_logic;
clk100Mhz : in std_logic;
extInt : in std_logic_vector(0 downto 0);
leds : out std_logic_vector(15 downto 0);
rgbLeds : out std_logic_vector(5 downto 0);
segments_a : out std_logic;
segments_b : out std_logic;
segments_c : out std_logic;
segments_d : out std_logic;
segments_e : out std_logic;
segments_f : out std_logic;
segments_g : out std_logic;
dot : out std_logic;
selector : out std_logic_vector(7 downto 0);
pmodA : inout std_logic_vector(7 downto 0);
sSwitches : in std_logic_vector(15 downto 0);
pButtons : in std_logic_vector(4 downto 0);
tck : in std_logic;
tms : in std_logic;
tdi : in std_logic;
tdo : out std_logic;
rx : in std_logic;
tx : out std_logic);
end Board_Nexys4DDR;
architecture Structural of Board_Nexys4DDR is
-- Positive reset signal
signal reset : std_logic;
-- Signals related to the board clk
signal boardClk : std_logic;
signal boardClkLocked : std_logic;
-- Interface for PModA
signal pmodA_read : std_logic_vector(7 downto 0);
signal pmodA_write : std_logic_vector(7 downto 0);
signal pmodA_writeEnable : std_logic_vector(7 downto 0);
begin
-- Instantiate a PLL/MMCM (makes a 80Mhz clock)
makeClk : entity work.PLL(Structural)
port map (clkIn => clk100Mhz,
clkOut => boardClk,
isLocked => boardClkLocked);
-- Make the reset positive
reset <= not nreset;
-- Instantiate the J1SoC core created by Spinal
core : entity work.J1Nexys4X
port map (reset => reset,
boardClk => boardClk,
boardClkLocked => boardClkLocked,
extInt => extInt,
leds => leds,
rgbLeds => rgbLeds,
segments_a => segments_a,
segments_b => segments_b,
segments_c => segments_c,
segments_d => segments_d,
segments_e => segments_e,
segments_f => segments_f,
segments_g => segments_g,
dot => dot,
selector => selector,
pmodA_read => pmodA_read,
pmodA_write => pmodA_write,
pmodA_writeEnable => pmodA_writeEnable,
sSwitches => sSwitches,
pButtons => pButtons,
tck => tck,
tms => tms,
tdi => tdi,
tdo => tdo,
rx => rx,
tx => tx);
-- Connect the pmodA read port
pmodA_read <= pmodA;
-- generate the write port and equip it with tristate functionality
pmodAGen : for i in pmodA'range generate
pmodA(i) <= pmodA_write(i) when pmodA_writeEnable(i) = '1' else 'Z';
end generate;
end architecture;
| bsd-3-clause | 9b7438cc8544cfbad8ebfec63d77be34 | 0.485707 | 4.047771 | false | false | false | false |
impedimentToProgress/UCI-BlueChip | AttackFiles/Attacks/privEsc/lib/eth/wrapper/greth_gen.vhd | 2 | 10,341 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: greth_gen
-- File: greth_gen.vhd
-- Author: Marko Isomaki
-- Description: Generic Ethernet MAC
------------------------------------------------------------------------------
library ieee;
library grlib;
use ieee.std_logic_1164.all;
use grlib.stdlib.all;
library techmap;
use techmap.gencomp.all;
library eth;
use eth.ethcomp.all;
entity greth_gen is
generic(
memtech : integer := 0;
ifg_gap : integer := 24;
attempt_limit : integer := 16;
backoff_limit : integer := 10;
mdcscaler : integer range 0 to 255 := 25;
enable_mdio : integer range 0 to 1 := 0;
fifosize : integer range 4 to 64 := 8;
nsync : integer range 1 to 2 := 2;
edcl : integer range 0 to 1 := 0;
edclbufsz : integer range 1 to 64 := 1;
macaddrh : integer := 16#00005E#;
macaddrl : integer := 16#000000#;
ipaddrh : integer := 16#c0a8#;
ipaddrl : integer := 16#0035#;
phyrstadr : integer range 0 to 31 := 0;
rmii : integer range 0 to 1 := 0;
oepol : integer range 0 to 1 := 0;
scanen : integer range 0 to 1 := 0);
port(
rst : in std_ulogic;
clk : in std_ulogic;
--ahb mst in
hgrant : in std_ulogic;
hready : in std_ulogic;
hresp : in std_logic_vector(1 downto 0);
hrdata : in std_logic_vector(31 downto 0);
--ahb mst out
hbusreq : out std_ulogic;
hlock : out std_ulogic;
htrans : out std_logic_vector(1 downto 0);
haddr : out std_logic_vector(31 downto 0);
hwrite : out std_ulogic;
hsize : out std_logic_vector(2 downto 0);
hburst : out std_logic_vector(2 downto 0);
hprot : out std_logic_vector(3 downto 0);
hwdata : out std_logic_vector(31 downto 0);
--apb slv in
psel : in std_ulogic;
penable : in std_ulogic;
paddr : in std_logic_vector(31 downto 0);
pwrite : in std_ulogic;
pwdata : in std_logic_vector(31 downto 0);
--apb slv out
prdata : out std_logic_vector(31 downto 0);
--irq
irq : out std_logic;
--ethernet input signals
rmii_clk : in std_ulogic;
tx_clk : in std_ulogic;
rx_clk : in std_ulogic;
rxd : in std_logic_vector(3 downto 0);
rx_dv : in std_ulogic;
rx_er : in std_ulogic;
rx_col : in std_ulogic;
rx_crs : in std_ulogic;
mdio_i : in std_ulogic;
phyrstaddr : in std_logic_vector(4 downto 0);
--ethernet output signals
reset : out std_ulogic;
txd : out std_logic_vector(3 downto 0);
tx_en : out std_ulogic;
tx_er : out std_ulogic;
mdc : out std_ulogic;
mdio_o : out std_ulogic;
mdio_oe : out std_ulogic;
--scantest
testrst : in std_ulogic;
testen : in std_ulogic
);
end entity;
architecture rtl of greth_gen is
function getfifosize(edcl, fifosize, ebufsize : in integer) return integer is
begin
if (edcl = 1) then
return ebufsize;
else
return fifosize;
end if;
end function;
constant fabits : integer := log2(fifosize);
type szvct is array (0 to 6) of integer;
constant ebuf : szvct := (64, 128, 128, 256, 256, 256, 256);
constant eabits : integer := log2(edclbufsz) + 8;
constant bufsize : std_logic_vector(2 downto 0) :=
conv_std_logic_vector(log2(edclbufsz), 3);
constant ebufsize : integer := ebuf(log2(edclbufsz));
constant txfifosize : integer := getfifosize(edcl, fifosize, ebufsize);
constant txfabits : integer := log2(txfifosize);
--rx ahb fifo
signal rxrenable : std_ulogic;
signal rxraddress : std_logic_vector(10 downto 0);
signal rxwrite : std_ulogic;
signal rxwdata : std_logic_vector(31 downto 0);
signal rxwaddress : std_logic_vector(10 downto 0);
signal rxrdata : std_logic_vector(31 downto 0);
--tx ahb fifo
signal txrenable : std_ulogic;
signal txraddress : std_logic_vector(10 downto 0);
signal txwrite : std_ulogic;
signal txwdata : std_logic_vector(31 downto 0);
signal txwaddress : std_logic_vector(10 downto 0);
signal txrdata : std_logic_vector(31 downto 0);
--edcl buf
signal erenable : std_ulogic;
signal eraddress : std_logic_vector(15 downto 0);
signal ewritem : std_ulogic;
signal ewritel : std_ulogic;
signal ewaddressm : std_logic_vector(15 downto 0);
signal ewaddressl : std_logic_vector(15 downto 0);
signal ewdata : std_logic_vector(31 downto 0);
signal erdata : std_logic_vector(31 downto 0);
begin
ethc0: grethc
generic map(
ifg_gap => ifg_gap,
attempt_limit => attempt_limit,
backoff_limit => backoff_limit,
mdcscaler => mdcscaler,
enable_mdio => enable_mdio,
fifosize => fifosize,
nsync => nsync,
edcl => edcl,
edclbufsz => edclbufsz,
macaddrh => macaddrh,
macaddrl => macaddrl,
ipaddrh => ipaddrh,
ipaddrl => ipaddrl,
phyrstadr => phyrstadr,
rmii => rmii,
oepol => oepol,
scanen => scanen)
port map(
rst => rst,
clk => clk,
--ahb mst in
hgrant => hgrant,
hready => hready,
hresp => hresp,
hrdata => hrdata,
--ahb mst out
hbusreq => hbusreq,
hlock => hlock,
htrans => htrans,
haddr => haddr,
hwrite => hwrite,
hsize => hsize,
hburst => hburst,
hprot => hprot,
hwdata => hwdata,
--apb slv in
psel => psel,
penable => penable,
paddr => paddr,
pwrite => pwrite,
pwdata => pwdata,
--apb slv out
prdata => prdata,
--irq
irq => irq,
--rx ahb fifo
rxrenable => rxrenable,
rxraddress => rxraddress,
rxwrite => rxwrite,
rxwdata => rxwdata,
rxwaddress => rxwaddress,
rxrdata => rxrdata,
--tx ahb fifo
txrenable => txrenable,
txraddress => txraddress,
txwrite => txwrite,
txwdata => txwdata,
txwaddress => txwaddress,
txrdata => txrdata,
--edcl buf
erenable => erenable,
eraddress => eraddress,
ewritem => ewritem,
ewritel => ewritel,
ewaddressm => ewaddressm,
ewaddressl => ewaddressl,
ewdata => ewdata,
erdata => erdata,
--ethernet input signals
rmii_clk => rmii_clk,
tx_clk => tx_clk,
rx_clk => rx_clk,
rxd => rxd(3 downto 0),
rx_dv => rx_dv,
rx_er => rx_er,
rx_col => rx_col,
rx_crs => rx_crs,
mdio_i => mdio_i,
phyrstaddr => phyrstaddr,
--ethernet output signals
reset => reset,
txd => txd(3 downto 0),
tx_en => tx_en,
tx_er => tx_er,
mdc => mdc,
mdio_o => mdio_o,
mdio_oe => mdio_oe,
--scantest
testrst => testrst,
testen => testen);
-------------------------------------------------------------------------------
-- FIFOS ----------------------------------------------------------------------
-------------------------------------------------------------------------------
tx_fifo0 : syncram_2p generic map(tech => memtech, abits => txfabits,
dbits => 32, sepclk => 0)
port map(clk, txrenable, txraddress(txfabits-1 downto 0), txrdata, clk,
txwrite, txwaddress(txfabits-1 downto 0), txwdata);
rx_fifo0 : syncram_2p generic map(tech => memtech, abits => fabits,
dbits => 32, sepclk => 0)
port map(clk, rxrenable, rxraddress(fabits-1 downto 0), rxrdata, clk,
rxwrite, rxwaddress(fabits-1 downto 0), rxwdata);
-------------------------------------------------------------------------------
-- EDCL buffer ram ------------------------------------------------------------
-------------------------------------------------------------------------------
edclram : if (edcl = 1) generate
rloopm : for i in 0 to 1 generate
r0 : syncram_2p generic map (memtech, eabits, 8) port map(
clk, erenable, eraddress(eabits-1 downto 0), erdata(i*8+23 downto i*8+16), clk,
ewritem, ewaddressm(eabits-1 downto 0), ewdata(i*8+23 downto i*8+16));
end generate;
rloopl : for i in 0 to 1 generate
r0 : syncram_2p generic map (memtech, eabits, 8) port map(
clk, erenable, eraddress(eabits-1 downto 0), erdata(i*8+7 downto i*8), clk,
ewritel, ewaddressl(eabits-1 downto 0), ewdata(i*8+7 downto i*8));
end generate;
end generate;
end architecture;
| mit | d4a4b1ce2c48af856b377bf0df4d9849 | 0.509525 | 4.158022 | false | false | false | false |
impedimentToProgress/UCI-BlueChip | AttackFiles/Attacks/privEsc/lib/techmap/apa/memory_apa.vhd | 2 | 6,545 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: various
-- File: mem_apa_gen.vhd
-- Author: Jiri Gaisler Gaisler Research
-- Description: Memory generators for Actel Proasic rams
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.stdlib.all;
-- pragma translate_off
library apa;
use apa.RAM256x9SST;
-- pragma translate_on
entity proasic_syncram_2p is
generic ( abits : integer := 8; dbits : integer := 32);
port (
rclk : in std_ulogic;
rena : in std_ulogic;
raddr : in std_logic_vector (abits -1 downto 0);
dout : out std_logic_vector (dbits -1 downto 0);
wclk : in std_ulogic;
waddr : in std_logic_vector (abits -1 downto 0);
din : in std_logic_vector (dbits -1 downto 0);
write : in std_ulogic);
end;
architecture rtl of proasic_syncram_2p is
component RAM256x9SST port(
DO8, DO7, DO6, DO5, DO4, DO3, DO2, DO1, DO0 : out std_logic;
WPE, RPE, DOS : out std_logic;
WADDR7, WADDR6, WADDR5, WADDR4, WADDR3, WADDR2, WADDR1, WADDR0 : in std_logic;
RADDR7, RADDR6, RADDR5, RADDR4, RADDR3, RADDR2, RADDR1, RADDR0 : in std_logic;
WCLKS, RCLKS : in std_logic;
DI8, DI7, DI6, DI5, DI4, DI3, DI2, DI1, DI0 : in std_logic;
WRB, RDB, WBLKB, RBLKB, PARODD, DIS : in std_logic);
end component;
type powarr is array (1 to 19) of integer;
constant ntbl : powarr := (1, 1, 1, 1, 1, 1, 1, 1, 2, 4, 8, 16, 32, others => 64);
constant dw : integer := dbits + 8;
subtype dword is std_logic_vector(dw downto 0);
type qarr is array (0 to 63) of dword;
signal gnd, wen, ren : std_ulogic;
signal q : qarr;
signal d : dword;
signal rra : std_logic_vector (20 downto 0);
signal ra, wa : std_logic_vector (63 downto 0);
signal wenv : std_logic_vector (63 downto 0);
signal renv : std_logic_vector (63 downto 0);
begin
gnd <= '0';
wa(63 downto abits) <= (others => '0'); wa(abits-1 downto 0) <= waddr;
ra(63 downto abits) <= (others => '0'); ra(abits-1 downto 0) <= raddr;
d(dw downto dbits) <= (others => '0'); d(dbits-1 downto 0) <= din;
wen <= not write; ren <= not rena;
x0 : if abits < 15 generate
b0 : for j in 0 to ntbl(abits)-1 generate
g0 : for i in 0 to (dbits-1)/9 generate
u0 : RAM256x9SST port map (
DO0 => q(j)(i*9+0), DO1 => q(j)(i*9+1), DO2 => q(j)(i*9+2),
DO3 => q(j)(i*9+3), DO4 => q(j)(i*9+4), DO5 => q(j)(i*9+5),
DO6 => q(j)(i*9+6), DO7 => q(j)(i*9+7), DO8 => q(j)(i*9+8),
DOS => open, RPE => open, WPE => open,
WADDR0 => wa(0), WADDR1 => wa(1), WADDR2 => wa(2),
WADDR3 => wa(3), WADDR4 => wa(4), WADDR5 => wa(5),
WADDR6 => wa(6), WADDR7 => wa(7),
RADDR0 => ra(0), RADDR1 => ra(1), RADDR2 => ra(2),
RADDR3 => ra(3), RADDR4 => ra(4), RADDR5 => ra(5),
RADDR6 => ra(6), RADDR7 => ra(7),
WCLKS => wclk, RCLKS => rclk,
DI0 => d(i*9+0), DI1 => d(i*9+1), DI2 => d(i*9+2),
DI3 => d(i*9+3), DI4 => d(i*9+4), DI5 => d(i*9+5),
DI6 => d(i*9+6), DI7 => d(i*9+7), DI8 => d(i*9+8),
RDB => ren, WRB => wen, RBLKB => renv(j), WBLKB => wenv(j),
PARODD => gnd, DIS => gnd
);
end generate;
end generate;
rra(20 downto abits) <= (others => '0');
reg : process(rclk)
begin
if rising_edge(rclk) then
rra(abits-1 downto 0) <= raddr(abits-1 downto 0);
rra(7 downto 0) <= (others => '0');
end if;
end process;
ctrl : process(write, waddr, q, rra, rena, raddr)
variable we,z,re : std_logic_vector(63 downto 0);
variable wea,rea : std_logic_vector(63 downto 0);
begin
we := (others => '0'); z := (others => '0'); re := (others => '0');
wea := (others => '0'); rea := (others => '0');
wea(abits-1 downto 0) := waddr(abits-1 downto 0); wea(7 downto 0) := (others => '0');
rea(abits-1 downto 0) := raddr(abits-1 downto 0); wea(7 downto 0) := (others => '0');
z(dbits-1 downto 0) :=
q(conv_integer(rra(19 downto 8)))(dbits-1 downto 0);
we (conv_integer(wea(19 downto 8))) := write;
re (conv_integer(rea(19 downto 8))) := rena;
wenv <= not we; renv <= not re; dout <= z(dbits-1 downto 0);
end process;
end generate;
-- pragma translate_off
unsup : if abits > 14 generate
x : process
begin
assert false
report "Address depth larger than 14 not supported for ProAsic rams"
severity failure;
wait;
end process;
end generate;
-- pragma translate_on
end;
library ieee;
use ieee.std_logic_1164.all;
entity proasic_syncram is
generic ( abits : integer := 10; dbits : integer := 8 );
port (
clk : in std_ulogic;
address : in std_logic_vector((abits -1) downto 0);
datain : in std_logic_vector((dbits -1) downto 0);
dataout : out std_logic_vector((dbits -1) downto 0);
enable : in std_ulogic;
write : in std_ulogic
);
end;
architecture rtl of proasic_syncram is
component proasic_syncram_2p
generic ( abits : integer := 8; dbits : integer := 32);
port (
rclk : in std_ulogic;
rena : in std_ulogic;
raddr : in std_logic_vector (abits -1 downto 0);
dout : out std_logic_vector (dbits -1 downto 0);
wclk : in std_ulogic;
waddr : in std_logic_vector (abits -1 downto 0);
din : in std_logic_vector (dbits -1 downto 0);
write : in std_ulogic);
end component;
begin
u0 : proasic_syncram_2p generic map (abits, dbits)
port map (clk, enable, address, dataout, clk, address, datain, write);
end;
| mit | 609b2f5558ec82928e2531ba5989423f | 0.579374 | 3.154217 | false | false | false | false |
cafe-alpha/wascafe | v13/r07c_de10_20201014_abus4/wasca/synthesis/submodules/Altera_UP_SD_Card_Response_Receiver.vhd | 7 | 11,537 | -- (C) 2001-2015 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
-------------------------------------------------------------------------------------
-- This module looks at the data on the CMD line and waits to receive a response.
-- It begins examining the data lines when the i_begin signal is asserted. It then
-- waits for a first '0'. It then proceeds to store as many bits as are required by
-- the response packet. Each message bit passes through the CRC7 circuit so that
-- the CRC check sum can be verified at the end of transmission. The circuit then produces
-- the o_data and o_CRC_passed outputs to indicate the message received and if the CRC
-- check passed.
--
-- If for some reason the requested response does not arrive within 56 clock cycles
-- then the circuit will produce a '1' on the o_timeout output. In such a case the
-- o_data should be ignored.
--
-- In case of a response that is not 001, 010, 011 or 110, the circuit expects
-- no response.
--
-- A signal o_done is asserted when the circuit has completed response retrieval. In
-- a case when a response is not expected, just wait for the CD Card to process the
-- command. This is done by waiting 8 (=PROCESSING_DELAY) clock cycles.
--
-- NOTES/REVISIONS:
-------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity Altera_UP_SD_Card_Response_Receiver is
generic (
TIMEOUT : std_logic_vector(7 downto 0) := "00111000";
BUSY_WAIT : std_logic_vector(7 downto 0) := "00110000";
PROCESSING_DELAY : std_logic_vector(7 downto 0) := "00001000"
);
port
(
i_clock : in std_logic;
i_reset_n : in std_logic;
i_begin : in std_logic;
i_scan_pulse : in std_logic;
i_datain : in std_logic;
i_wait_cmd_busy : in std_logic;
i_response_type : in std_logic_vector(2 downto 0);
o_data : out std_logic_vector(127 downto 0);
o_CRC_passed : out std_logic;
o_timeout : out std_logic;
o_done : out std_logic
);
end entity;
architecture rtl of Altera_UP_SD_Card_Response_Receiver is
component Altera_UP_SD_CRC7_Generator
port
(
i_clock : in std_logic;
i_enable : in std_logic;
i_reset_n : in std_logic;
i_shift : in std_logic;
i_datain : in std_logic;
o_dataout : out std_logic;
o_crcout : out std_logic_vector(6 downto 0)
);
end component;
-- Build an enumerated type for the state machine. On reset always reset the DE2 and read the state
-- of the switches.
type state_type is (s_WAIT_BEGIN, s_WAIT_END, s_WAIT_PROCESSING_DELAY, s_WAIT_BUSY, s_WAIT_BUSY_END, s_WAIT_BEGIN_DEASSERT);
-- Register to hold the current state
signal current_state : state_type;
signal next_state : state_type;
-- Local wires
-- REGISTERED
signal registered_data_input : std_logic_vector(127 downto 0);
signal response_incoming : std_logic;
signal counter, timeout_counter : std_logic_vector(7 downto 0);
signal crc_shift, keep_reading_bits, shift_crc_bits : std_logic;
-- UNREGISTERED
signal limit, limit_minus_1 : std_logic_vector(7 downto 0);
signal check_crc : std_logic;
signal CRC_bits : std_logic_vector(6 downto 0);
signal start_reading_bits, operation_complete, enable_crc_unit : std_logic;
begin
-- Control FSM. Begin operation when i_begin is raised, then wait for the operation to end and i_begin to be deasserted.
state_regs: process(i_clock, i_reset_n)
begin
if (i_reset_n = '0') then
current_state <= s_WAIT_BEGIN;
elsif (rising_edge(i_clock)) then
current_state <= next_state;
end if;
end process;
state_transitions: process(current_state, i_begin, operation_complete, timeout_counter, i_wait_cmd_busy, i_scan_pulse, i_datain)
begin
case current_state is
when s_WAIT_BEGIN =>
if (i_begin = '1') then
next_state <= s_WAIT_END;
else
next_state <= s_WAIT_BEGIN;
end if;
when s_WAIT_END =>
if (operation_complete = '1') then
if (timeout_counter = TIMEOUT) then
next_state <= s_WAIT_BEGIN_DEASSERT;
else
next_state <= s_WAIT_PROCESSING_DELAY;
end if;
else
next_state <= s_WAIT_END;
end if;
when s_WAIT_PROCESSING_DELAY =>
if (timeout_counter = PROCESSING_DELAY) then
if (i_wait_cmd_busy = '1') then
next_state <= s_WAIT_BUSY;
else
next_state <= s_WAIT_BEGIN_DEASSERT;
end if;
else
next_state <= s_WAIT_PROCESSING_DELAY;
end if;
when s_WAIT_BUSY =>
if ((i_scan_pulse = '1') and (i_datain = '0')) then
next_state <= s_WAIT_BUSY_END;
else
if (timeout_counter = BUSY_WAIT) then
-- If the card did not become busy, then it would not have raised the optional busy signal.
-- In such a case, proceeed further as the command has finished correctly.
next_state <= s_WAIT_BEGIN_DEASSERT;
else
next_state <= s_WAIT_BUSY;
end if;
end if;
when s_WAIT_BUSY_END =>
if ((i_scan_pulse = '1') and (i_datain = '1')) then
next_state <= s_WAIT_BEGIN_DEASSERT;
else
next_state <= s_WAIT_BUSY_END;
end if;
when s_WAIT_BEGIN_DEASSERT =>
if (i_begin = '1') then
next_state <= s_WAIT_BEGIN_DEASSERT;
else
next_state <= s_WAIT_BEGIN;
end if;
when others =>
next_state <= s_WAIT_BEGIN;
end case;
end process;
-- Store the response as it appears on the i_datain line.
received_data_buffer: process (i_clock, i_reset_n)
begin
if (i_reset_n = '0') then
registered_data_input <= (OTHERS=>'0');
elsif (rising_edge(i_clock)) then
-- Only read new data and update the counter value when the scan pulse is high.
if (i_scan_pulse = '1') then
if ((start_reading_bits = '1') or (keep_reading_bits = '1')) then
registered_data_input(127 downto 1) <= registered_data_input(126 downto 0);
registered_data_input(0) <= i_datain;
end if;
end if;
end if;
end process;
-- Counter received bits
data_read_counter: process (i_clock, i_reset_n)
begin
if (i_reset_n = '0') then
counter <= (OTHERS=>'0');
elsif (rising_edge(i_clock)) then
-- Reset he counter every time you being reading the response.
if (current_state = s_WAIT_BEGIN) then
counter <= (OTHERS => '0');
end if;
-- Update the counter value when the scan pulse is high.
if (i_scan_pulse = '1') then
if ((start_reading_bits = '1') or (keep_reading_bits = '1')) then
counter <= counter + '1';
end if;
end if;
end if;
end process;
operation_complete <= '1' when (((counter = limit) and (not (limit = "00000000"))) or
(timeout_counter = TIMEOUT) or
((timeout_counter = PROCESSING_DELAY) and (limit = "00000000"))) else '0';
-- Count the number of scan pulses before the response is received. If the counter
-- exceeds TIMEOUT value, then an error must have occured when the SD card received a message.
timeout_counter_control: process (i_clock, i_reset_n)
begin
if (i_reset_n = '0') then
timeout_counter <= (OTHERS=>'0');
elsif (rising_edge(i_clock)) then
-- Reset the counter every time you begin reading the response.
if ((current_state = s_WAIT_BEGIN) or ((current_state = s_WAIT_END) and (operation_complete = '1') and (not (timeout_counter = TIMEOUT)))) then
timeout_counter <= (OTHERS => '0');
end if;
-- Update the counter value when the scan pulse is high.
if (i_scan_pulse = '1') then
if (((start_reading_bits = '0') and (keep_reading_bits = '0') and (current_state = s_WAIT_END) and (not (timeout_counter = TIMEOUT))) or
(current_state = s_WAIT_PROCESSING_DELAY) or (current_state = s_WAIT_BUSY)) then
timeout_counter <= timeout_counter + '1';
end if;
end if;
end if;
end process;
-- Enable data storing only after you see the first 0.
read_enable_logic: process (i_clock, i_reset_n)
begin
if (i_reset_n = '0') then
keep_reading_bits <= '0';
elsif (rising_edge(i_clock)) then
if (i_scan_pulse = '1') then
if ((start_reading_bits = '1') or ((keep_reading_bits = '1') and (not (counter = limit_minus_1)))) then
keep_reading_bits <= '1';
else
keep_reading_bits <= '0';
end if;
end if;
end if;
end process;
start_reading_bits <= '1' when ((current_state = s_WAIT_END) and (i_datain = '0') and
(counter = "00000000") and (not (limit = "00000000"))) else '0';
-- CRC7 checker.
crc_checker: Altera_UP_SD_CRC7_Generator PORT MAP
(
i_clock => i_clock,
i_reset_n => i_reset_n,
i_enable => enable_crc_unit,
i_shift => shift_crc_bits,
i_datain => registered_data_input(7),
o_crcout => CRC_bits
);
enable_crc_unit <= '1' when ((i_scan_pulse = '1') and (current_state = s_WAIT_END)) else '0';
-- Clear CRC7 registers before processing the response bits
crc_control_register: process (i_clock, i_reset_n)
begin
if (i_reset_n = '0') then
shift_crc_bits <= '1';
elsif (rising_edge(i_clock)) then
-- Reset he counter every time you being reading the response.
if (current_state = s_WAIT_BEGIN) then
-- clear the CRC7 contents before you process the next message.
shift_crc_bits <= '1';
end if;
-- Only read new data and update the counter value when the scan pulse is high.
if (i_scan_pulse = '1') then
if ((start_reading_bits = '1') or (keep_reading_bits = '1')) then
if (counter = "00000111") then
-- Once the 7-bits of the CRC checker have been cleared you can process the message and
-- compute its CRC bits to verify the validity of the transmission.
shift_crc_bits <= '0';
end if;
end if;
end if;
end if;
end process;
-- Indicate the number of bits to expect in the response packet.
limit <= "00110000" when ((i_response_type = "001") or
(i_response_type = "011") or
(i_response_type = "110")) else
"10001000" when (i_response_type = "010") else
"00000000"; -- No response
limit_minus_1 <=
"00101111" when ((i_response_type = "001") or
(i_response_type = "011") or
(i_response_type = "110")) else
"10000111" when (i_response_type = "010") else
"00000000"; -- No response
check_crc <= '1' when ((i_response_type = "001") or (i_response_type = "110")) else '0';
-- Generate Circuit outputs
o_data <= (registered_data_input(127 downto 1) & '1') when (i_response_type = "010") else
(CONV_STD_LOGIC_VECTOR(0, 96) & registered_data_input(39 downto 8));
o_CRC_passed <= '1' when ((check_crc = '0') or
((registered_data_input(0) = '1') and (CRC_bits = registered_data_input(7 downto 1)))) else '0';
o_timeout <= '1' when (timeout_counter = TIMEOUT) else '0';
o_done <= '1' when (current_state = s_WAIT_BEGIN_DEASSERT) else '0';
end rtl; | gpl-2.0 | e5fe12f475081aecefd7c6a9d7f2acc7 | 0.644795 | 3.173865 | false | false | false | false |
michaelfivez/ascon_hardware_implementation | ascon128128_iterated/Kernel/Sbox.vhd | 1 | 3,929 | -------------------------------------------------------------------------------
--! @project Iterate hardware implementation of Asconv128128
--! @author Michael Fivez
--! @license This project is released under the GNU Public License.
--! The license and distribution terms for this file may be
--! found in the file LICENSE in this distribution or at
--! http://www.gnu.org/licenses/gpl-3.0.txt
--! @note This is an hardware implementation made for my graduation thesis
--! at the KULeuven, in the COSIC department (year 2015-2016)
--! The thesis is titled 'Energy efficient hardware implementations of CAESAR submissions',
--! and can be found on the COSIC website (www.esat.kuleuven.be/cosic/publications)
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity Sbox is
port(
X0In : in std_logic_vector(63 downto 0);
X1In : in std_logic_vector(63 downto 0);
X2In : in std_logic_vector(63 downto 0);
X3In : in std_logic_vector(63 downto 0);
X4In : in std_logic_vector(63 downto 0);
RoundNr : in std_logic_vector(3 downto 0);
X0Out : out std_logic_vector(63 downto 0);
X1Out : out std_logic_vector(63 downto 0);
X2Out : out std_logic_vector(63 downto 0);
X3Out : out std_logic_vector(63 downto 0);
X4Out : out std_logic_vector(63 downto 0));
end entity Sbox;
architecture structural of Sbox is
begin
Sbox: process(X0In,X1In,X2In,X3In,X4In,RoundNr) is
-- Procedure for 5-bit Sbox
procedure doSboxPart (
variable SboxPartIn : in std_logic_vector(4 downto 0);
variable SboxPartOut : out std_logic_vector(4 downto 0)) is
-- Temp variable
variable SboxPartTemp : std_logic_vector(17 downto 0);
begin
-- Sbox Interconnections
SboxPartTemp(0) := SboxPartIn(0) xor SboxPartIn(4);
SboxPartTemp(1) := SboxPartIn(2) xor SboxPartIn(1);
SboxPartTemp(2) := SboxPartIn(4) xor SboxPartIn(3);
SboxPartTemp(3) := not SboxPartTemp(0);
SboxPartTemp(4) := not SboxPartIn(1);
SboxPartTemp(5) := not SboxPartTemp(1);
SboxPartTemp(6) := not SboxPartIn(3);
SboxPartTemp(7) := not SboxPartTemp(2);
SboxPartTemp(8) := SboxPartIn(1) and SboxPartTemp(3);
SboxPartTemp(9) := SboxPartTemp(1) and SboxPartTemp(4);
SboxPartTemp(10) := SboxPartIn(3) and SboxPartTemp(5);
SboxPartTemp(11) := SboxPartTemp(2) and SboxPartTemp(6);
SboxPartTemp(12) := SboxPartTemp(0) and SboxPartTemp(7);
SboxPartTemp(13) := SboxPartTemp(0) xor SboxPartTemp(9);
SboxPartTemp(14) := SboxPartIn(1) xor SboxPartTemp(10);
SboxPartTemp(15) := SboxPartTemp(1) xor SboxPartTemp(11);
SboxPartTemp(16) := SboxPartIn(3) xor SboxPartTemp(12);
SboxPartTemp(17) := SboxPartTemp(2) xor SboxPartTemp(8);
SboxPartOut(0) := SboxPartTemp(13) xor SboxPartTemp(17);
SboxPartOut(1) := SboxPartTemp(13) xor SboxPartTemp(14);
SboxPartOut(2) := not SboxPartTemp(15);
SboxPartOut(3) := SboxPartTemp(15) xor SboxPartTemp(16);
SboxPartOut(4) := SboxPartTemp(17);
end procedure doSboxPart;
variable X2TempIn : std_logic_vector(63 downto 0);
variable TempIn,TempOut : std_logic_vector(4 downto 0);
begin
-- Xor with round constants
X2TempIn(3 downto 0) := X2In(3 downto 0) xor RoundNr;
X2TempIn(7 downto 4) := X2In(7 downto 4) xnor RoundNr;
X2TempIn(63 downto 8) := X2In(63 downto 8);
-- Apply 5-bit Sbox 64 times
for i in X0In'range loop
TempIn(0) := X0In(i);
TempIn(1) := X1In(i);
TempIn(2) := X2TempIn(i);
TempIn(3) := X3In(i);
TempIn(4) := X4In(i);
doSboxPart(TempIn,TempOut);
X0Out(i) <= TempOut(0);
X1Out(i) <= TempOut(1);
X2Out(i) <= TempOut(2);
X3Out(i) <= TempOut(3);
X4Out(i) <= TempOut(4);
end loop;
end process Sbox;
end architecture structural;
| gpl-3.0 | 2f4fc7910e3315bc2cca65438aa29623 | 0.640367 | 2.92772 | false | false | false | false |
impedimentToProgress/UCI-BlueChip | AttackFiles/Attacks/privEsc/lib/techmap/umc18/memory_umc18.vhd | 2 | 9,369 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: various
-- File: mem_umc_gen.vhd
-- Author: Jiri Gaisler Gaisler Research
-- Description: Memory generators for UMC rams
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
-- pragma translate_off
library umc18;
use umc18.SRAM_2048wx32b;
use umc18.SRAM_1024wx32b;
use umc18.SRAM_512wx32b;
use umc18.SRAM_256wx32b;
use umc18.SRAM_128wx32b;
use umc18.SRAM_64wx32b;
use umc18.SRAM_32wx32b;
use umc18.SRAM_2048wx40b;
use umc18.SRAM_1024wx40b;
use umc18.SRAM_512wx40b;
use umc18.SRAM_256wx40b;
use umc18.SRAM_128wx40b;
use umc18.SRAM_64wx40b;
use umc18.SRAM_32wx40b;
-- pragma translate_on
entity umc_syncram is
generic ( abits : integer := 10; dbits : integer := 8 );
port (
clk : in std_ulogic;
address : in std_logic_vector(abits -1 downto 0);
datain : in std_logic_vector(dbits -1 downto 0);
dataout : out std_logic_vector(dbits -1 downto 0);
enable : in std_ulogic;
write : in std_ulogic
);
end;
architecture rtl of umc_syncram is
component SRAM_2048wx32b is
port (
a : in std_logic_vector(10 downto 0);
data : in std_logic_vector(31 downto 0);
csn : in std_logic;
wen : in std_logic;
oen : in std_logic;
q : out std_logic_vector(31 downto 0);
clk : in std_logic
);
end component;
component SRAM_1024wx32b is
port (
a : in std_logic_vector(9 downto 0);
data : in std_logic_vector(31 downto 0);
csn : in std_logic;
wen : in std_logic;
oen : in std_logic;
q : out std_logic_vector(31 downto 0);
clk : in std_logic
);
end component;
component SRAM_512wx32b is
port (
a : in std_logic_vector(8 downto 0);
data : in std_logic_vector(31 downto 0);
csn : in std_logic;
wen : in std_logic;
oen : in std_logic;
q : out std_logic_vector(31 downto 0);
clk : in std_logic
);
end component;
component SRAM_256wx32b is
port (
a : in std_logic_vector(7 downto 0);
data : in std_logic_vector(31 downto 0);
csn : in std_logic;
wen : in std_logic;
oen : in std_logic;
q : out std_logic_vector(31 downto 0);
clk : in std_logic
);
end component;
component SRAM_128wx32b is
port (
a : in std_logic_vector(6 downto 0);
data : in std_logic_vector(31 downto 0);
csn : in std_logic;
wen : in std_logic;
oen : in std_logic;
q : out std_logic_vector(31 downto 0);
clk : in std_logic
);
end component;
component SRAM_64wx32b is
port (
a : in std_logic_vector(5 downto 0);
data : in std_logic_vector(31 downto 0);
csn : in std_logic;
wen : in std_logic;
oen : in std_logic;
q : out std_logic_vector(31 downto 0);
clk : in std_logic
);
end component;
component SRAM_32wx32b is
port (
a : in std_logic_vector(4 downto 0);
data : in std_logic_vector(31 downto 0);
csn : in std_logic;
wen : in std_logic;
oen : in std_logic;
q : out std_logic_vector(31 downto 0);
clk : in std_logic
);
end component;
component SRAM_2048wx40b is
port (
a : in std_logic_vector(10 downto 0);
data : in std_logic_vector(39 downto 0);
csn : in std_logic;
wen : in std_logic;
oen : in std_logic;
q : out std_logic_vector(39 downto 0);
clk : in std_logic
);
end component;
component SRAM_1024wx40b is
port (
a : in std_logic_vector(9 downto 0);
data : in std_logic_vector(39 downto 0);
csn : in std_logic;
wen : in std_logic;
oen : in std_logic;
q : out std_logic_vector(39 downto 0);
clk : in std_logic
);
end component;
component SRAM_512wx40b is
port (
a : in std_logic_vector(8 downto 0);
data : in std_logic_vector(39 downto 0);
csn : in std_logic;
wen : in std_logic;
oen : in std_logic;
q : out std_logic_vector(39 downto 0);
clk : in std_logic
);
end component;
component SRAM_256wx40b is
port (
a : in std_logic_vector(7 downto 0);
data : in std_logic_vector(39 downto 0);
csn : in std_logic;
wen : in std_logic;
oen : in std_logic;
q : out std_logic_vector(39 downto 0);
clk : in std_logic
);
end component;
component SRAM_128wx40b is
port (
a : in std_logic_vector(6 downto 0);
data : in std_logic_vector(39 downto 0);
csn : in std_logic;
wen : in std_logic;
oen : in std_logic;
q : out std_logic_vector(39 downto 0);
clk : in std_logic
);
end component;
component SRAM_64wx40b is
port (
a : in std_logic_vector(5 downto 0);
data : in std_logic_vector(39 downto 0);
csn : in std_logic;
wen : in std_logic;
oen : in std_logic;
q : out std_logic_vector(39 downto 0);
clk : in std_logic
);
end component;
component SRAM_32wx40b is
port (
a : in std_logic_vector(4 downto 0);
data : in std_logic_vector(39 downto 0);
csn : in std_logic;
wen : in std_logic;
oen : in std_logic;
q : out std_logic_vector(39 downto 0);
clk : in std_logic
);
end component;
signal d, q, gnd : std_logic_vector(41 downto 0);
signal a : std_logic_vector(17 downto 0);
signal vcc, csn, wen : std_ulogic;
constant synopsys_bug : std_logic_vector(41 downto 0) := (others => '0');
begin
csn <= not enable; wen <= not write;
gnd <= (others => '0'); vcc <= '1';
a(abits -1 downto 0) <= address;
d(dbits -1 downto 0) <= datain(dbits -1 downto 0);
a(17 downto abits) <= synopsys_bug(17 downto abits);
d(41 downto dbits) <= synopsys_bug(41 downto dbits);
dataout <= q(dbits -1 downto 0);
-- q(41 downto dbits) <= synopsys_bug(41 downto dbits);
d32 : if (dbits <= 32) generate
a5d32 : if (abits <= 5) generate
id0 : SRAM_32wx32b port map (a(4 downto 0), d(31 downto 0), csn,
wen, gnd(0), q(31 downto 0), clk);
end generate;
a6d32 : if (abits = 6) generate
id0 : SRAM_64wx32b port map (a(5 downto 0), d(31 downto 0), csn,
wen, gnd(0), q(31 downto 0), clk);
end generate;
a7d32 : if (abits = 7) generate
id0 : SRAM_128wx32b port map (a(6 downto 0), d(31 downto 0), csn,
wen, gnd(0), q(31 downto 0), clk);
end generate;
a8d32 : if (abits = 8) generate
id0 : SRAM_256wx32b port map (a(7 downto 0), d(31 downto 0), csn,
wen, gnd(0), q(31 downto 0), clk);
end generate;
a9d32 : if (abits = 9) generate
id0 : SRAM_512wx32b port map (a(8 downto 0), d(31 downto 0), csn,
wen, gnd(0), q(31 downto 0), clk);
end generate;
a10d32 : if (abits = 10) generate
id0 : SRAM_1024wx32b port map (a(9 downto 0), d(31 downto 0), csn,
wen, gnd(0), q(31 downto 0), clk);
end generate;
a11d32 : if (abits = 11) generate
id0 : SRAM_2048wx32b port map (a(10 downto 0), d(31 downto 0), csn,
wen, gnd(0), q(31 downto 0), clk);
end generate;
end generate;
d40 : if (dbits > 32) and (dbits <= 40) generate
a5d40 : if (abits <= 5) generate
id0 : SRAM_32wx40b port map (a(4 downto 0), d(39 downto 0), csn,
wen, gnd(0), q(39 downto 0), clk);
end generate;
a6d40 : if (abits = 6) generate
id0 : SRAM_64wx40b port map (a(5 downto 0), d(39 downto 0), csn,
wen, gnd(0), q(39 downto 0), clk);
end generate;
a7d40 : if (abits = 7) generate
id0 : SRAM_128wx40b port map (a(6 downto 0), d(39 downto 0), csn,
wen, gnd(0), q(39 downto 0), clk);
end generate;
a8d40 : if (abits = 8) generate
id0 : SRAM_256wx40b port map (a(7 downto 0), d(39 downto 0), csn,
wen, gnd(0), q(39 downto 0), clk);
end generate;
a9d40 : if (abits = 9) generate
id0 : SRAM_512wx40b port map (a(8 downto 0), d(39 downto 0), csn,
wen, gnd(0), q(39 downto 0), clk);
end generate;
a10d40 : if (abits = 10) generate
id0 : SRAM_1024wx40b port map (a(9 downto 0), d(39 downto 0), csn,
wen, gnd(0), q(39 downto 0), clk);
end generate;
a11d40 : if (abits = 11) generate
id0 : SRAM_2048wx40b port map (a(10 downto 0), d(39 downto 0), csn,
wen, gnd(0), q(39 downto 0), clk);
end generate;
end generate;
-- pragma translate_off
a_to_high : if (abits > 12) or (dbits > 40) generate
x : process
begin
assert false
report "Unsupported memory size (umc18)"
severity failure;
wait;
end process;
end generate;
-- pragma translate_on
end;
| mit | 685fc42cef2fb7ace1124d5a5e926785 | 0.605934 | 2.906017 | false | false | false | false |
michaelfivez/ascon_hardware_implementation | ascon12864_unrolled6/Kernel/DiffusionLayer.vhd | 1 | 1,687 | -------------------------------------------------------------------------------
--! @project Unrolled (6) hardware implementation of Asconv1286
--! @author Michael Fivez
--! @license This project is released under the GNU Public License.
--! The license and distribution terms for this file may be
--! found in the file LICENSE in this distribution or at
--! http://www.gnu.org/licenses/gpl-3.0.txt
--! @note This is an hardware implementation made for my graduation thesis
--! at the KULeuven, in the COSIC department (year 2015-2016)
--! The thesis is titled 'Energy efficient hardware implementations of CAESAR submissions',
--! and can be found on the COSIC website (www.esat.kuleuven.be/cosic/publications)
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity DiffusionLayer is
generic( SHIFT1 : integer range 0 to 63;
SHIFT2 : integer range 0 to 63);
port( Input : in std_logic_vector(63 downto 0);
Output : out std_logic_vector(63 downto 0));
end entity DiffusionLayer;
architecture structural of DiffusionLayer is
begin
DiffLayer: process(Input) is
variable Temp0,Temp1 : std_logic_vector(63 downto 0);
begin
Temp0(63 downto 64-SHIFT1) := Input(SHIFT1-1 downto 0);
Temp0(63-SHIFT1 downto 0) := Input(63 downto SHIFT1);
Temp1(63 downto 64-SHIFT2) := Input(SHIFT2-1 downto 0);
Temp1(63-SHIFT2 downto 0) := Input(63 downto SHIFT2);
Output <= Temp0 xor Temp1 xor Input;
end process DiffLayer;
end architecture structural;
| gpl-3.0 | 58c4c43e2b7ca899edbf6e6a6599fcee | 0.616479 | 3.740576 | false | false | false | false |
mgiacomini/mips-monocycle | MAIN_CTTRL.vhd | 1 | 10,086 | -- +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-- Complete implementation of Patterson and Hennessy single cycle MIPS processor
-- Copyright (C) 2015 Darci Luiz Tomasi Junior
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, version 3.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
-- Engineer: Darci Luiz Tomasi Junior
-- E-mail: [email protected]
-- Date : 01/07/2015 - 22:08
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;
ENTITY MAIN_PROCESSOR IS
PORT(
CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC
);
END MAIN_PROCESSOR;
ARCHITECTURE ARC_MAIN_PROCESSOR OF MAIN_PROCESSOR IS
COMPONENT ADD_PC IS
PORT(
IN_A : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
OUT_A : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END COMPONENT;
COMPONENT ADD IS
PORT(
IN_A : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
IN_B : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
OUT_A : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END COMPONENT;
COMPONENT AND_1 IS
PORT(
Branch : IN STD_LOGIC;
IN_A : IN STD_LOGIC;
OUT_A : OUT STD_LOGIC
);
END COMPONENT;
COMPONENT CONCAT IS
PORT(
IN_A : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
IN_B : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
OUT_A : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END COMPONENT;
COMPONENT CTRL IS
PORT(
OPCode : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
RegDst : OUT STD_LOGIC;
Jump : OUT STD_LOGIC;
Branch : OUT STD_LOGIC;
MemRead : OUT STD_LOGIC;
MemtoReg : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
ALUOp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
MemWrite : OUT STD_LOGIC;
ALUSrc : OUT STD_LOGIC;
RegWrite : OUT STD_LOGIC
);
END COMPONENT;
COMPONENT EXTEND_SIGNAL IS
PORT(
IN_A : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
OUT_A : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END COMPONENT;
COMPONENT INST IS
PORT(
IN_A : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
OUT_A : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END COMPONENT;
COMPONENT MEM IS
PORT(
CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
MemWrite : IN STD_LOGIC;
MemRead : IN STD_LOGIC;
IN_A : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
IN_B : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
OUT_A : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END COMPONENT;
COMPONENT MX_1 IS
PORT(
RegDst : IN STD_LOGIC;
IN_A : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
IN_B : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
OUT_A : OUT STD_LOGIC_VECTOR(4 DOWNTO 0)
);
END COMPONENT;
COMPONENT MX_2 IS
PORT(
AluSrc : IN STD_LOGIC;
IN_A : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
IN_B : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
OUT_A : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END COMPONENT;
COMPONENT MX_3 IS
PORT(
IN_A : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
IN_B : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
IN_C : IN STD_LOGIC;
OUT_A : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END COMPONENT;
COMPONENT MX_4 IS
PORT(
Jump : IN STD_LOGIC;
IN_A : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
IN_B : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
OUT_A : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END COMPONENT;
COMPONENT MX_5 IS
PORT(
MemtoReg : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
IN_A : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
IN_B : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
IN_C : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
OUT_A : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END COMPONENT;
COMPONENT PC IS
PORT(
CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
IN_A : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
OUT_A : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END COMPONENT;
COMPONENT REG IS
PORT(
CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
RegWrite : IN STD_LOGIC;
IN_A : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
IN_B : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
IN_C : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
IN_D : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
OUT_A : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
OUT_B : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END COMPONENT;
COMPONENT SL_1 IS
PORT(
IN_A : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
OUT_A : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END COMPONENT;
COMPONENT SL_2 IS
PORT(
IN_A : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
OUT_A : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END COMPONENT;
COMPONENT SL_16 IS
PORT(
IN_A : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
OUT_A : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END COMPONENT;
COMPONENT ULA_CTRL IS
PORT (
ALUOp : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
IN_A : IN STD_LOGIC_VECTOR (5 DOWNTO 0);
OUT_A : OUT STD_LOGIC_VECTOR (2 DOWNTO 0)
);
END COMPONENT;
COMPONENT ULA IS
PORT(
IN_A : IN STD_LOGIC_VECTOR (31 downto 0); --RS
IN_B : IN STD_LOGIC_VECTOR (31 downto 0); --RT
IN_C : IN STD_LOGIC_VECTOR (2 downto 0);
OUT_A : OUT STD_LOGIC_VECTOR (31 downto 0);
ZERO : OUT STD_LOGIC
);
END COMPONENT;
--ADD_PC
SIGNAL S_ADD_PC_OUT_A : STD_LOGIC_VECTOR(31 DOWNTO 0);
--ADD
SIGNAL S_ADD_OUT_A : STD_LOGIC_VECTOR(31 DOWNTO 0);
--AND_1
SIGNAL S_AND_1_OUT_A : STD_LOGIC;
--CONCAT
SIGNAL S_CONCAT_OUT_A : STD_LOGIC_VECTOR(31 DOWNTO 0);
--CTRL
SIGNAL S_CTRL_RegDst : STD_LOGIC;
SIGNAL S_CTRL_Jump : STD_LOGIC;
SIGNAL S_CTRL_Branch : STD_LOGIC;
SIGNAL S_CTRL_MemRead : STD_LOGIC;
SIGNAL S_CTRL_MemtoReg : STD_LOGIC_VECTOR(1 DOWNTO 0);
SIGNAL S_CTRL_ALUOp : STD_LOGIC_VECTOR(1 DOWNTO 0);
SIGNAL S_CTRL_MemWrite : STD_LOGIC;
SIGNAL S_CTRL_ALUSrc : STD_LOGIC;
SIGNAL S_CTRL_RegWrite : STD_LOGIC;
--INST
SIGNAL S_INST_OUT_A : STD_LOGIC_VECTOR(31 DOWNTO 0);
--EXTEND_SIGNAL
SIGNAL S_EXTEND_SIGNAL_OUT_A :STD_LOGIC_VECTOR (31 DOWNTO 0);
--MEM
SIGNAL S_MEM_OUT_A : STD_LOGIC_VECTOR(31 DOWNTO 0);
--MX_1
SIGNAL S_MX_1_OUT_A : STD_LOGIC_VECTOR(4 DOWNTO 0);
--MX_2
SIGNAL S_MX_2_OUT_A : STD_LOGIC_VECTOR(31 DOWNTO 0);
--MX_3
SIGNAL S_MX_3_OUT_A : STD_LOGIC_VECTOR(31 DOWNTO 0);
--MX_4
SIGNAL S_MX_4_OUT_A : STD_LOGIC_VECTOR(31 DOWNTO 0);
--MX_5
SIGNAL S_MX_5_OUT_A : STD_LOGIC_VECTOR(31 DOWNTO 0);
--PC
SIGNAL S_PC_OUT_A : STD_LOGIC_VECTOR(31 DOWNTO 0);
--REG
SIGNAL S_REG_OUT_A : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL S_REG_OUT_B : STD_LOGIC_VECTOR(31 DOWNTO 0);
--SL_1
SIGNAL S_SL_1_OUT_A : STD_LOGIC_VECTOR (31 DOWNTO 0);
--SL_2
SIGNAL S_SL_2_OUT_A : STD_LOGIC_VECTOR (31 DOWNTO 0);
--SL_16
SIGNAL S_SL_16_OUT_A : STD_LOGIC_VECTOR (31 DOWNTO 0);
--ULA_CTRL
SIGNAL S_ULA_CTRL_OUT_A : STD_LOGIC_VECTOR (2 DOWNTO 0);
--ULA
SIGNAL S_ULA_OUT_A : STD_LOGIC_VECTOR (31 downto 0);
SIGNAL S_ULA_ZERO : STD_LOGIC;
--DEMAIS SINAIS
SIGNAL S_GERAL_OPCode : STD_LOGIC_VECTOR(5 DOWNTO 0);
SIGNAL S_GERAL_RS : STD_LOGIC_VECTOR(4 DOWNTO 0);
SIGNAL S_GERAL_RT : STD_LOGIC_VECTOR(4 DOWNTO 0);
SIGNAL S_GERAL_RD : STD_LOGIC_VECTOR(4 DOWNTO 0);
SIGNAL S_GERAL_I_TYPE : STD_LOGIC_VECTOR(15 DOWNTO 0);
SIGNAL S_GERAL_FUNCT : STD_LOGIC_VECTOR(5 DOWNTO 0);
SIGNAL S_GERAL_JUMP : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL S_GERAL_PC_4 : STD_LOGIC_VECTOR(31 DOWNTO 0);
BEGIN
S_GERAL_OPCode <= S_INST_OUT_A(31 DOWNTO 26);
S_GERAL_RS <= S_INST_OUT_A(25 DOWNTO 21);
S_GERAL_RT <= S_INST_OUT_A(20 DOWNTO 16);
S_GERAL_RD <= S_INST_OUT_A(15 DOWNTO 11);
S_GERAL_I_TYPE <= S_INST_OUT_A(15 DOWNTO 0);
S_GERAL_FUNCT <= S_INST_OUT_A(5 DOWNTO 0);
S_GERAL_JUMP <= S_INST_OUT_A(31 DOWNTO 0);
S_GERAL_PC_4 <= S_ADD_PC_OUT_A(31 DOWNTO 0);
C_PC : PC PORT MAP(CLK, RESET, S_MX_4_OUT_A, S_PC_OUT_A);
C_ADD_PC : ADD_PC PORT MAP(S_PC_OUT_A, S_ADD_PC_OUT_A);
C_INST : INST PORT MAP(S_PC_OUT_A, S_INST_OUT_A);
C_SL_1 : SL_1 PORT MAP(S_GERAL_JUMP, S_SL_1_OUT_A);
C_CTRL : CTRL PORT MAP(S_GERAL_OPCode, S_CTRL_RegDst, S_CTRL_Jump, S_CTRL_Branch, S_CTRL_MemRead, S_CTRL_MemtoReg, S_CTRL_ALUOp, S_CTRL_MemWrite, S_CTRL_ALUSrc, S_CTRL_RegWrite);
C_CONCAT : CONCAT PORT MAP(S_SL_1_OUT_A, S_GERAL_PC_4, S_CONCAT_OUT_A);
C_MX_1 : MX_1 PORT MAP(S_CTRL_RegDst, S_GERAL_RT, S_GERAL_RD, S_MX_1_OUT_A);
C_SL_2 : SL_2 PORT MAP(S_EXTEND_SIGNAL_OUT_A, S_SL_2_OUT_A);
C_SL_16 : SL_16 PORT MAP(S_EXTEND_SIGNAL_OUT_A, S_SL_16_OUT_A);
C_REG : REG PORT MAP(CLK, RESET, S_CTRL_RegWrite, S_GERAL_RS, S_GERAL_RT, S_MX_1_OUT_A, S_MX_5_OUT_A, S_REG_OUT_A, S_REG_OUT_B);
C_EXTEND_SIGNAL : EXTEND_SIGNAL PORT MAP(S_GERAL_I_TYPE, S_EXTEND_SIGNAL_OUT_A);
C_ADD : ADD PORT MAP(S_ADD_PC_OUT_A, S_SL_2_OUT_A, S_ADD_OUT_A);
C_ULA : ULA PORT MAP(S_REG_OUT_A, S_MX_2_OUT_A, S_ULA_CTRL_OUT_A, S_ULA_OUT_A, S_ULA_ZERO);
C_MX_2 : MX_2 PORT MAP(S_CTRL_ALUSrc, S_REG_OUT_B, S_EXTEND_SIGNAL_OUT_A, S_MX_2_OUT_A);
C_ULA_CTRL : ULA_CTRL PORT MAP(S_CTRL_ALUOp, S_GERAL_FUNCT, S_ULA_CTRL_OUT_A);
C_MX_3 : MX_3 PORT MAP(S_ADD_PC_OUT_A, S_ADD_OUT_A, S_AND_1_OUT_A, S_MX_3_OUT_A);
C_AND_1 : AND_1 PORT MAP(S_CTRL_Branch, S_ULA_ZERO, S_AND_1_OUT_A);
C_MEM : MEM PORT MAP(CLK, RESET, S_CTRL_MemWrite, S_CTRL_MemRead, S_ULA_OUT_A, S_REG_OUT_B, S_MEM_OUT_A);
C_MX_4 : MX_4 PORT MAP(S_CTRL_Jump, S_CONCAT_OUT_A, S_MX_3_OUT_A, S_MX_4_OUT_A);
C_MX_5 : MX_5 PORT MAP(S_CTRL_MemtoReg, S_MEM_OUT_A, S_ULA_OUT_A, S_SL_16_OUT_A, S_MX_5_OUT_A);
END ARC_MAIN_PROCESSOR;
| gpl-3.0 | 86018e00f5f61ab967dbe51a13ed8ee6 | 0.607377 | 2.40716 | false | false | false | false |
impedimentToProgress/UCI-BlueChip | AttackFiles/Attacks/privEsc/lib/gaisler/pci/pcipads.vhd | 2 | 6,990 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: pcipads
-- File: pcipads.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: PCI pads module
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
use work.pci.all;
library grlib;
use grlib.stdlib.all;
entity pcipads is
generic (
padtech : integer := 0;
noreset : integer := 0;
oepol : integer := 0;
host : integer := 1;
int : integer := 0
);
port (
pci_rst : in std_ulogic;
pci_gnt : in std_ulogic;
pci_idsel : in std_ulogic;
pci_lock : inout std_ulogic;
pci_ad : inout std_logic_vector(31 downto 0);
pci_cbe : inout std_logic_vector(3 downto 0);
pci_frame : inout std_ulogic;
pci_irdy : inout std_ulogic;
pci_trdy : inout std_ulogic;
pci_devsel : inout std_ulogic;
pci_stop : inout std_ulogic;
pci_perr : inout std_ulogic;
pci_par : inout std_ulogic;
pci_req : inout std_ulogic; -- tristate pad but never read
pci_serr : inout std_ulogic; -- open drain output
pci_host : in std_ulogic;
pci_66 : in std_ulogic;
pcii : out pci_in_type;
pcio : in pci_out_type;
pci_int : inout std_logic_vector(3 downto 0) := conv_std_logic_vector(16#F#, 4) -- Disable int by default
--pci_int : inout std_logic_vector(3 downto 0) :=
-- conv_std_logic_vector(16#F# - (16#F# * oepol), 4) -- Disable int by default
);
end;
architecture rtl of pcipads is
signal vcc : std_ulogic;
begin
vcc <= '1';
norst : if noreset = 0 generate
pad_pci_rst : inpad generic map (padtech, pci33, 0) port map (pci_rst, pcii.rst);
end generate;
dorst : if noreset = 1 generate
pcii.rst <= pci_rst;
end generate;
pad_pci_gnt : inpad generic map (padtech, pci33, 0) port map (pci_gnt, pcii.gnt);
pad_pci_idsel : inpad generic map (padtech, pci33, 0) port map (pci_idsel, pcii.idsel);
dohost : if host = 1 generate
pad_pci_host : inpad generic map (padtech, pci33, 0) port map (pci_host, pcii.host);
end generate;
nohost : if host = 0 generate
pcii.host <= '1'; -- disable pci host functionality
end generate;
pad_pci_66 : inpad generic map (padtech, pci33, 0) port map (pci_66, pcii.pci66);
pad_pci_lock : iopad generic map (tech => padtech, level => pci33, oepol => oepol)
port map (pci_lock, pcio.lock, pcio.locken, pcii.lock);
pad_pci_ad : iopadvv generic map (tech => padtech, level => pci33, width => 32,
oepol => oepol)
port map (pci_ad, pcio.ad, pcio.vaden, pcii.ad);
pad_pci_cbe0 : iopad generic map (tech => padtech, level => pci33, oepol => oepol)
port map (pci_cbe(0), pcio.cbe(0), pcio.cbeen(0), pcii.cbe(0));
pad_pci_cbe1 : iopad generic map (tech => padtech, level => pci33, oepol => oepol)
port map (pci_cbe(1), pcio.cbe(1), pcio.cbeen(1), pcii.cbe(1));
pad_pci_cbe2 : iopad generic map (tech => padtech, level => pci33, oepol => oepol)
port map (pci_cbe(2), pcio.cbe(2), pcio.cbeen(2), pcii.cbe(2));
pad_pci_cbe3 : iopad generic map (tech => padtech, level => pci33, oepol => oepol)
port map (pci_cbe(3), pcio.cbe(3), pcio.cbeen(3), pcii.cbe(3));
pad_pci_frame : iopad generic map (tech => padtech, level => pci33, oepol => oepol)
port map (pci_frame, pcio.frame, pcio.frameen, pcii.frame);
pad_pci_trdy : iopad generic map (tech => padtech, level => pci33, oepol => oepol)
port map (pci_trdy, pcio.trdy, pcio.trdyen, pcii.trdy);
pad_pci_irdy : iopad generic map (tech => padtech, level => pci33, oepol => oepol)
port map (pci_irdy, pcio.irdy, pcio.irdyen, pcii.irdy);
pad_pci_devsel: iopad generic map (tech => padtech, level => pci33, oepol => oepol)
port map (pci_devsel, pcio.devsel, pcio.devselen, pcii.devsel);
pad_pci_stop : iopad generic map (tech => padtech, level => pci33, oepol => oepol)
port map (pci_stop, pcio.stop, pcio.stopen, pcii.stop);
pad_pci_perr : iopad generic map (tech => padtech, level => pci33, oepol => oepol)
port map (pci_perr, pcio.perr, pcio.perren, pcii.perr);
pad_pci_par : iopad generic map (tech => padtech, level => pci33, oepol => oepol)
port map (pci_par, pcio.par, pcio.paren, pcii.par);
pad_pci_req : toutpad generic map (tech => padtech, level => pci33, oepol => oepol)
port map (pci_req, pcio.req, pcio.reqen);
pad_pci_serr : iopad generic map (tech => padtech, level => pci33, oepol => oepol)
port map (pci_serr, pcio.serr, pcio.serren, pcii.serr);
-- PCI interrupt pads
-- int = 0 => no interrupt
-- int = 1 => PCI_INT[A] = out, PCI_INT[B,C,D] = Not connected
-- int = 2 => PCI_INT[B] = out, PCI_INT[A,C,D] = Not connected
-- int = 3 => PCI_INT[C] = out, PCI_INT[A,B,D] = Not connected
-- int = 4 => PCI_INT[D] = out, PCI_INT[A,B,C] = Not connected
-- int = 10 => PCI_INT[A] = inout, PCI_INT[B,C,D] = in
-- int = 11 => PCI_INT[B] = inout, PCI_INT[A,C,D] = in
-- int = 12 => PCI_INT[C] = inout, PCI_INT[A,B,D] = in
-- int = 13 => PCI_INT[D] = inout, PCI_INT[A,B,C] = in
-- int > 13 => PCI_INT[A,B,C,D] = in
interrupt : if int /= 0 generate
x : for i in 0 to 3 generate
xo : if i = int - 1 and int < 10 generate
pad_pci_int : odpad generic map (tech => padtech, level => pci33, oepol => oepol)
port map (pci_int(i), pcio.inten);
end generate;
xio : if i = (int - 10) and int >= 10 generate
pad_pci_int : iodpad generic map (tech => padtech, level => pci33, oepol => oepol)
port map (pci_int(i), pcio.inten, pcii.int(i));
end generate;
xi : if i /= (int - 10) and int >= 10 generate
pad_pci_int : inpad generic map (tech => padtech, level => pci33)
port map (pci_int(i), pcii.int(i));
end generate;
end generate;
end generate;
end;
| mit | b9f571fbc49df50e3916362a4d3903be | 0.595136 | 3.322243 | false | false | false | false |
impedimentToProgress/UCI-BlueChip | AttackFiles/Attacks/privEsc/lib/gaisler/ata/ata.vhd | 2 | 2,889 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: ata
-- File: ata.vhd
-- Authors: Nils-Johan Wessman, Jiri Gaisler - Gaisler Research
-- Description: ATA controller package
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
package ata is
type ata_in_type is record
ddi : std_logic_vector(15 downto 0);
iordy : std_logic;
intrq : std_logic;
dmarq : std_logic;
end record;
type ata_out_type is record
rstn : std_logic;
ddo : std_logic_vector(15 downto 0);
oen : std_logic;
da : std_logic_vector(2 downto 0);
cs0 : std_logic;
cs1 : std_logic;
dior : std_logic;
diow : std_logic;
dmack : std_logic;
end record;
type cf_out_type is record
power : std_logic;
atasel : std_logic;
we : std_logic;
csel : std_logic;
da : std_logic_vector(10 downto 3);
end record;
component atactrl is
generic (
tech : integer := 0;
fdepth : integer := 8;
mhindex : integer := 0;
shindex : integer := 0;
haddr : integer := 0;
hmask : integer := 16#ff0#;
pirq : integer := 0;
mwdma : integer := 0;
TWIDTH : natural := 8; -- counter width
-- PIO mode 0 settings (@100MHz clock)
PIO_mode0_T1 : natural := 6; -- 70ns
PIO_mode0_T2 : natural := 28; -- 290ns
PIO_mode0_T4 : natural := 2; -- 30ns
PIO_mode0_Teoc : natural := 23 -- 240ns ==> T0 - T1 - T2 = 600 - 70 - 290 = 240
);
port (
rst : in std_ulogic;
arst : in std_ulogic;
clk : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
ahbmi : in ahb_mst_in_type;
ahbmo : out ahb_mst_out_type;
cfo : out cf_out_type;
atai : in ata_in_type;
atao : out ata_out_type
);
end component;
end;
| mit | 943f34eb35b0ead8f2aff3099e4fe7d5 | 0.563171 | 3.557882 | false | false | false | false |
impedimentToProgress/UCI-BlueChip | AttackFiles/Attacks/privEsc/lib/opencores/ata/atahost_pio_actrl.vhd | 2 | 9,568 | ---------------------------------------------------------------------
---- ----
---- OpenCores IDE Controller ----
---- PIO Access Controller (common for OCIDEC 2 and above) ----
---- ----
---- Author: Richard Herveille ----
---- [email protected] ----
---- www.asics.ws ----
---- ----
---------------------------------------------------------------------
---- ----
---- Copyright (C) 2001, 2002 Richard Herveille ----
---- [email protected] ---
---- ----
---- This source file may be used and distributed without ----
---- restriction provided that this copyright statement is not ----
---- removed from the file and that any derivative work contains ----
---- the original copyright notice and the associated disclaimer.----
---- ----
---- THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ----
---- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ----
---- TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ----
---- FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ----
---- OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ----
---- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ----
---- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ----
---- GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ----
---- BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ----
---- LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ----
---- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ----
---- OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ----
---- POSSIBILITY OF SUCH DAMAGE. ----
---- ----
---------------------------------------------------------------------
-- rev.: 1.0 march 9th, 2001
-- rev.: 1.0a april 12th, 2001 Removed references to records.vhd
--
--
-- CVS Log
--
-- $Id: atahost_pio_actrl.vhd,v 1.1 2002/02/18 14:32:12 rherveille Exp $
--
-- $Date: 2002/02/18 14:32:12 $
-- $Revision: 1.1 $
-- $Author: rherveille $
-- $Locker: $
-- $State: Exp $
--
-- Change History:
-- $Log: atahost_pio_actrl.vhd,v $
-- Revision 1.1 2002/02/18 14:32:12 rherveille
-- renamed all files to 'atahost_***.vhd'
-- broke-up 'counter.vhd' into 'ud_cnt.vhd' and 'ro_cnt.vhd'
-- changed resD input to generic RESD in ud_cnt.vhd
-- changed ID input to generic ID in ro_cnt.vhd
-- changed core to reflect changes in ro_cnt.vhd
-- removed references to 'count' library
-- changed IO names
-- added disclaimer
-- added CVS log
-- moved registers and wishbone signals into 'atahost_wb_slave.vhd'
--
--
---------------------------
-- PIO Access controller --
---------------------------
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity atahost_pio_actrl is
generic(
TWIDTH : natural := 8; -- counter width
-- PIO mode 0 settings (@100MHz clock)
PIO_mode0_T1 : natural := 6; -- 70ns
PIO_mode0_T2 : natural := 28; -- 290ns
PIO_mode0_T4 : natural := 2; -- 30ns
PIO_mode0_Teoc : natural := 23 -- 240ns ==> T0 - T1 - T2 = 600 - 70 - 290 = 240
);
port(
clk : in std_logic; -- master clock
nReset : in std_logic; -- asynchronous active low reset
rst : in std_logic; -- synchronous active high reset
IDEctrl_FATR0,
IDEctrl_FATR1 : in std_logic;
cmdport_T1,
cmdport_T2,
cmdport_T4,
cmdport_Teoc : in std_logic_vector(7 downto 0);
cmdport_IORDYen : in std_logic; -- PIO command port / non-fast timing
dport0_T1,
dport0_T2,
dport0_T4,
dport0_Teoc : in std_logic_vector(7 downto 0);
dport0_IORDYen : in std_logic; -- PIO mode data-port / fast timing device 0
dport1_T1,
dport1_T2,
dport1_T4,
dport1_Teoc : in std_logic_vector(7 downto 0);
dport1_IORDYen : in std_logic; -- PIO mode data-port / fast timing device 1
SelDev : in std_logic; -- Selected device
go : in std_logic; -- Start transfer sequence
done : out std_logic; -- Transfer sequence done
dir : in std_logic; -- Transfer direction '1'=write, '0'=read
a : in std_logic_vector(3 downto 0):="0000"; -- PIO transfer address
q : out std_logic_vector(15 downto 0); -- Data read from ATA devices
DDi : in std_logic_vector(15 downto 0); -- Data from ATA DD bus
oe : out std_logic; -- DDbus output-enable signal
DIOR,
DIOW : out std_logic;
IORDY : in std_logic
);
end entity atahost_pio_actrl;
architecture structural of atahost_pio_actrl is
--
-- Component declarations
--
component atahost_pio_tctrl is
generic(
TWIDTH : natural := 8; -- counter width
-- PIO mode 0 settings (@100MHz clock)
PIO_mode0_T1 : natural := 6; -- 70ns
PIO_mode0_T2 : natural := 28; -- 290ns
PIO_mode0_T4 : natural := 2; -- 30ns
PIO_mode0_Teoc : natural := 23 -- 240ns ==> T0 - T1 - T2 = 600 - 70 - 290 = 240
);
port(
clk : in std_logic; -- master clock
nReset : in std_logic; -- asynchronous active low reset
rst : in std_logic; -- synchronous active high reset
-- timing/control register settings
IORDY_en : in std_logic; -- use IORDY (or not)
T1 : in std_logic_vector(TWIDTH -1 downto 0); -- T1 time (in clk-ticks)
T2 : in std_logic_vector(TWIDTH -1 downto 0); -- T2 time (in clk-ticks)
T4 : in std_logic_vector(TWIDTH -1 downto 0); -- T4 time (in clk-ticks)
Teoc : in std_logic_vector(TWIDTH -1 downto 0); -- end of cycle time
-- control signals
go : in std_logic; -- PIO controller selected (strobe signal)
we : in std_logic; -- write enable signal. '0'=read from device, '1'=write to device
-- return signals
oe : out std_logic; -- output enable signal
done : out std_logic; -- finished cycle
dstrb : out std_logic; -- data strobe, latch data (during read)
-- ATA signals
DIOR, -- IOread signal, active high
DIOW : out std_logic; -- IOwrite signal, active high
IORDY : in std_logic -- IORDY signal
);
end component atahost_pio_tctrl;
signal dstrb : std_logic;
signal T1, T2, T4, Teoc : std_logic_vector(TWIDTH -1 downto 0);
signal IORDYen : std_logic;
begin
--
--------------------------
-- PIO transfer control --
--------------------------
--
-- capture ATA data for PIO access
gen_PIOq: process(clk)
begin
if (clk'event and clk = '1') then
if (dstrb = '1') then
q <= DDi;
end if;
end if;
end process gen_PIOq;
--
-- PIO timing controllers
--
-- select timing settings for the addressed port
sel_port_t: process(clk)
variable Asel : std_logic; -- address selected
variable iT1, iT2, iT4, iTeoc : std_logic_vector(TWIDTH -1 downto 0);
variable iIORDYen : std_logic;
begin
if (clk'event and clk = '1') then
-- initially set timing registers to compatible timing
iT1 := cmdport_T1;
iT2 := cmdport_T2;
iT4 := cmdport_T4;
iTeoc := cmdport_Teoc;
iIORDYen := cmdport_IORDYen;
-- detect data-port access
Asel := not a(3) and not a(2) and not a(1) and not a(0); -- data port
if (Asel = '1') then -- data port selected, 16bit transfers
if ((SelDev = '1') and (IDEctrl_FATR1 = '1')) then -- data port1 selected and enabled ?
iT1 := dport1_T1;
iT2 := dport1_T2;
iT4 := dport1_T4;
iTeoc := dport1_Teoc;
iIORDYen := dport1_IORDYen;
elsif((SelDev = '0') and (IDEctrl_FATR0 = '1')) then -- data port0 selected and enabled ?
iT1 := dport0_T1;
iT2 := dport0_T2;
iT4 := dport0_T4;
iTeoc := dport0_Teoc;
iIORDYen := dport0_IORDYen;
end if;
end if;
T1 <= iT1;
T2 <= iT2;
T4 <= iT4;
Teoc <= iTeoc;
IORDYen <= iIORDYen;
end if;
end process sel_port_t;
--
-- hookup timing controller
--
PIO_timing_controller: atahost_pio_tctrl
generic map (
TWIDTH => TWIDTH,
PIO_mode0_T1 => PIO_mode0_T1,
PIO_mode0_T2 => PIO_mode0_T2,
PIO_mode0_T4 => PIO_mode0_T4,
PIO_mode0_Teoc => PIO_mode0_Teoc
)
port map (
clk => clk,
nReset => nReset,
rst => rst,
IORDY_en => IORDYen,
T1 => T1,
T2 => T2,
T4 => T4,
Teoc => Teoc,
go => go,
we => dir,
oe => oe,
done => done,
dstrb => dstrb,
DIOR => dior,
DIOW => diow,
IORDY => IORDY
);
end architecture structural;
| mit | d98b7ae9b15b4d8e63eca0f0be52dd37 | 0.507734 | 3.493246 | false | false | false | false |
impedimentToProgress/UCI-BlueChip | AttackFiles/Attacks/privEsc/lib/tech/stratixii/simprims/stratixii_components.vhd | 2 | 48,922 | -- Copyright (C) 1991-2006 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions
-- and other software and tools, and its AMPP partner logic
-- functions, and any output files any of the foregoing
-- (including device programming or simulation files), and any
-- associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License
-- Subscription Agreement, Altera MegaCore Function License
-- Agreement, or other applicable license agreement, including,
-- without limitation, that your use is for the sole purpose of
-- programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the
-- applicable agreement for further details.
-- Quartus II 6.0 Build 178 04/27/2006
LIBRARY IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.VITAL_Timing.all;
use work.stratixii_atom_pack.all;
package STRATIXII_COMPONENTS is
--
-- STRATIXII_LCELL_FF
--
component stratixii_lcell_ff
generic (
x_on_violation : string := "on";
lpm_type : string := "stratixii_lcell_ff";
tsetup_datain_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_adatasdata_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_sclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_datain_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_adatasdata_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_sclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_clk_regout_posedge : VitalDelayType01 := DefPropDelay01;
tpd_aclr_regout_posedge : VitalDelayType01 := DefPropDelay01;
tpd_aload_regout_posedge : VitalDelayType01 := DefPropDelay01;
tpd_adatasdata_regout: VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_datain : VitalDelayType01 := DefPropDelay01;
tipd_adatasdata : VitalDelayType01 := DefPropDelay01;
tipd_sclr : VitalDelayType01 := DefPropDelay01;
tipd_sload : VitalDelayType01 := DefPropDelay01;
tipd_aclr : VitalDelayType01 := DefPropDelay01;
tipd_aload : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks;
InstancePath: STRING := "*"
);
port (
datain : in std_logic := '0';
clk : in std_logic := '0';
aclr : in std_logic := '0';
aload : in std_logic := '0';
sclr : in std_logic := '0';
sload : in std_logic := '0';
ena : in std_logic := '1';
adatasdata : in std_logic := '0';
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
regout : out std_logic
);
end component;
--
-- STRATIXII_LCELL_COMB
--
component stratixii_lcell_comb
generic (
lut_mask : std_logic_vector(63 downto 0) := (OTHERS => '1');
shared_arith : string := "off";
extended_lut : string := "off";
lpm_type : string := "stratixii_lcell_comb";
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks;
InstancePath: STRING := "*";
tpd_dataa_combout : VitalDelayType01 := DefPropDelay01;
tpd_datab_combout : VitalDelayType01 := DefPropDelay01;
tpd_datac_combout : VitalDelayType01 := DefPropDelay01;
tpd_datad_combout : VitalDelayType01 := DefPropDelay01;
tpd_datae_combout : VitalDelayType01 := DefPropDelay01;
tpd_dataf_combout : VitalDelayType01 := DefPropDelay01;
tpd_datag_combout : VitalDelayType01 := DefPropDelay01;
tpd_dataa_sumout : VitalDelayType01 := DefPropDelay01;
tpd_datab_sumout : VitalDelayType01 := DefPropDelay01;
tpd_datac_sumout : VitalDelayType01 := DefPropDelay01;
tpd_datad_sumout : VitalDelayType01 := DefPropDelay01;
tpd_dataf_sumout : VitalDelayType01 := DefPropDelay01;
tpd_cin_sumout : VitalDelayType01 := DefPropDelay01;
tpd_sharein_sumout : VitalDelayType01 := DefPropDelay01;
tpd_dataa_cout : VitalDelayType01 := DefPropDelay01;
tpd_datab_cout : VitalDelayType01 := DefPropDelay01;
tpd_datac_cout : VitalDelayType01 := DefPropDelay01;
tpd_datad_cout : VitalDelayType01 := DefPropDelay01;
tpd_dataf_cout : VitalDelayType01 := DefPropDelay01;
tpd_cin_cout : VitalDelayType01 := DefPropDelay01;
tpd_sharein_cout : VitalDelayType01 := DefPropDelay01;
tpd_dataa_shareout : VitalDelayType01 := DefPropDelay01;
tpd_datab_shareout : VitalDelayType01 := DefPropDelay01;
tpd_datac_shareout : VitalDelayType01 := DefPropDelay01;
tpd_datad_shareout : VitalDelayType01 := DefPropDelay01;
tipd_dataa : VitalDelayType01 := DefPropDelay01;
tipd_datab : VitalDelayType01 := DefPropDelay01;
tipd_datac : VitalDelayType01 := DefPropDelay01;
tipd_datad : VitalDelayType01 := DefPropDelay01;
tipd_datae : VitalDelayType01 := DefPropDelay01;
tipd_dataf : VitalDelayType01 := DefPropDelay01;
tipd_datag : VitalDelayType01 := DefPropDelay01;
tipd_cin : VitalDelayType01 := DefPropDelay01;
tipd_sharein : VitalDelayType01 := DefPropDelay01
);
port (
dataa : in std_logic := '0';
datab : in std_logic := '0';
datac : in std_logic := '0';
datad : in std_logic := '0';
datae : in std_logic := '0';
dataf : in std_logic := '0';
datag : in std_logic := '0';
cin : in std_logic := '0';
sharein : in std_logic := '0';
combout : out std_logic;
sumout : out std_logic;
cout : out std_logic;
shareout : out std_logic
);
end component;
--
-- STRATIXII_IO
--
component stratixii_io
generic (
operation_mode : string := "input";
ddio_mode : string := "none";
open_drain_output : string := "false";
bus_hold : string := "false";
output_register_mode : string := "none";
output_async_reset : string := "none";
output_power_up : string := "low";
output_sync_reset : string := "none";
tie_off_output_clock_enable : string := "false";
oe_register_mode : string := "none";
oe_async_reset : string := "none";
oe_power_up : string := "low";
oe_sync_reset : string := "none";
tie_off_oe_clock_enable : string := "false";
input_register_mode : string := "none";
input_async_reset : string := "none";
input_power_up : string := "low";
input_sync_reset : string := "none";
extend_oe_disable : string := "false";
dqs_input_frequency : string := "10000 ps";
dqs_out_mode : string := "none";
dqs_delay_buffer_mode : string := "low";
dqs_phase_shift : integer := 0;
inclk_input : string := "normal";
ddioinclk_input : string := "negated_inclk";
dqs_offsetctrl_enable : string := "false";
dqs_ctrl_latches_enable : string := "false";
dqs_edge_detect_enable : string := "false";
gated_dqs : string := "false";
sim_dqs_intrinsic_delay : integer := 0;
sim_dqs_delay_increment : integer := 0;
sim_dqs_offset_increment : integer := 0;
lpm_type : string := "stratixii_io"
);
port (
datain : in std_logic := '0';
ddiodatain : in std_logic := '0';
oe : in std_logic := '1';
outclk : in std_logic := '0';
outclkena : in std_logic := '1';
inclk : in std_logic := '0';
inclkena : in std_logic := '1';
areset : in std_logic := '0';
sreset : in std_logic := '0';
ddioinclk : in std_logic := '0';
delayctrlin : in std_logic_vector(5 downto 0) := "000000";
offsetctrlin : in std_logic_vector(5 downto 0) := "000000";
dqsupdateen : in std_logic := '0';
linkin : in std_logic := '0';
terminationcontrol : in std_logic_vector(13 downto 0) := "00000000000000";
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
devoe : in std_logic := '0';
padio : inout std_logic;
combout : out std_logic;
regout : out std_logic;
ddioregout : out std_logic;
dqsbusout : out std_logic;
linkout : out std_logic
);
end component;
--
-- STRATIXII_CLKCTRL
--
component stratixii_clkctrl
generic (
clock_type : STRING := "Auto";
lpm_type : STRING := "stratixii_clkctrl";
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : STRING := "*";
tipd_inclk : VitalDelayArrayType01(3 downto 0) := (OTHERS => DefPropDelay01);
tipd_clkselect : VitalDelayArrayType01(1 downto 0) := (OTHERS => DefPropDelay01);
tipd_ena : VitalDelayType01 := DefPropDelay01
);
port (
inclk : in std_logic_vector(3 downto 0) := "0000";
clkselect : in std_logic_vector(1 downto 0) := "00";
ena : in std_logic := '1';
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
outclk : out std_logic
);
end component;
--
-- STRATIXII_MAC_MULT
--
component stratixii_mac_mult
generic
(
dataa_width : integer := 18;
datab_width : integer := 18;
dataa_clock : string := "none";
datab_clock : string := "none";
signa_clock : string := "none";
signb_clock : string := "none";
round_clock : string := "none";
saturate_clock : string := "none";
output_clock : string := "none";
dataa_clear : string := "none";
datab_clear : string := "none";
signa_clear : string := "none";
signb_clear : string := "none";
round_clear : string := "none";
saturate_clear : string := "none";
output_clear : string := "none";
bypass_multiplier : string := "no";
mode_clock : string := "none";
zeroacc_clock : string := "none";
mode_clear : string := "none";
zeroacc_clear : string := "none";
signa_internally_grounded : string := "false";
signb_internally_grounded : string := "false";
lpm_hint : string := "true";
dynamic_mode : string := "no";
lpm_type : string := "stratixii_mac_mult"
);
port
(
dataa : IN std_logic_vector(dataa_width-1 DOWNTO 0) := (others => '0');
datab : IN std_logic_vector(datab_width-1 DOWNTO 0) := (others => '0');
scanina : IN std_logic_vector(dataa_width-1 DOWNTO 0) := (others => '0');
scaninb : IN std_logic_vector(datab_width-1 DOWNTO 0) := (others => '0');
sourcea : IN std_logic := '0';
sourceb : IN std_logic := '0';
signa : IN std_logic := '0';
signb : IN std_logic := '0';
round : IN std_logic := '0';
saturate : IN std_logic := '0';
clk : IN std_logic_vector(3 DOWNTO 0) := (others => '0');
aclr : IN std_logic_vector(3 DOWNTO 0) := (others => '0');
ena : IN std_logic_vector(3 DOWNTO 0) := (others => '0');
mode : IN std_logic := '0';
zeroacc : IN std_logic := '0';
dataout : OUT std_logic_vector((dataa_width+datab_width)-1 DOWNTO 0);
scanouta : OUT std_logic_vector(dataa_width-1 DOWNTO 0);
scanoutb : OUT std_logic_vector(datab_width-1 DOWNTO 0);
devclrn : in std_logic := '1';
devpor : in std_logic := '1'
);
end component;
--
-- STRATIXII_MAC_OUT
--
component stratixii_mac_out
generic
(
operation_mode : string := "output_only";
dataa_width : integer := 1;
datab_width : integer := 1;
datac_width : integer := 1;
datad_width : integer := 1;
dataout_width : integer := 144;
addnsub0_clock : string := "none";
addnsub1_clock : string := "none";
zeroacc_clock : string := "none";
round0_clock : string := "none";
round1_clock : string := "none";
saturate_clock : string := "none";
multabsaturate_clock : string := "none";
multcdsaturate_clock : string := "none";
signa_clock : string := "none";
signb_clock : string := "none";
output_clock : string := "none";
addnsub0_clear : string := "none";
addnsub1_clear : string := "none";
zeroacc_clear : string := "none";
round0_clear : string := "none";
round1_clear : string := "none";
saturate_clear : string := "none";
multabsaturate_clear : string := "none";
multcdsaturate_clear : string := "none";
signa_clear : string := "none";
signb_clear : string := "none";
output_clear : string := "none";
addnsub0_pipeline_clock : string := "none";
addnsub1_pipeline_clock : string := "none";
round0_pipeline_clock : string := "none";
round1_pipeline_clock : string := "none";
saturate_pipeline_clock : string := "none";
multabsaturate_pipeline_clock : string := "none";
multcdsaturate_pipeline_clock : string := "none";
zeroacc_pipeline_clock : string := "none";
signa_pipeline_clock : string := "none";
signb_pipeline_clock : string := "none";
addnsub0_pipeline_clear : string := "none";
addnsub1_pipeline_clear : string := "none";
round0_pipeline_clear : string := "none";
round1_pipeline_clear : string := "none";
saturate_pipeline_clear : string := "none";
multabsaturate_pipeline_clear : string := "none";
multcdsaturate_pipeline_clear : string := "none";
zeroacc_pipeline_clear : string := "none";
signa_pipeline_clear : string := "none";
signb_pipeline_clear : string := "none";
mode0_clock : string := "none";
mode1_clock : string := "none";
zeroacc1_clock : string := "none";
saturate1_clock : string := "none";
output1_clock : string := "none";
output2_clock : string := "none";
output3_clock : string := "none";
output4_clock : string := "none";
output5_clock : string := "none";
output6_clock : string := "none";
output7_clock : string := "none";
mode0_clear : string := "none";
mode1_clear : string := "none";
zeroacc1_clear : string := "none";
saturate1_clear : string := "none";
output1_clear : string := "none";
output2_clear : string := "none";
output3_clear : string := "none";
output4_clear : string := "none";
output5_clear : string := "none";
output6_clear : string := "none";
output7_clear : string := "none";
mode0_pipeline_clock : string := "none";
mode1_pipeline_clock : string := "none";
zeroacc1_pipeline_clock : string := "none";
saturate1_pipeline_clock : string := "none";
mode0_pipeline_clear : string := "none";
mode1_pipeline_clear : string := "none";
zeroacc1_pipeline_clear : string := "none";
saturate1_pipeline_clear : string := "none";
dataa_forced_to_zero : string := "no";
datac_forced_to_zero : string := "no";
lpm_hint : string := "true";
lpm_type : string := "stratixii_mac_out"
);
port
(
dataa : in std_logic_vector (dataa_width - 1 downto 0) := (others => '0');
datab : in std_logic_vector (datab_width - 1 downto 0) := (others => '0');
datac : in std_logic_vector (datac_width - 1 downto 0) := (others => '0');
datad : in std_logic_vector (datad_width - 1 downto 0) := (others => '0');
zeroacc : in std_logic := '0';
addnsub0 : in std_logic := '1';
addnsub1 : in std_logic := '1';
round0 : in std_logic := '0';
round1 : in std_logic := '0';
saturate : in std_logic := '0';
multabsaturate : in std_logic := '0';
multcdsaturate : in std_logic := '0';
signa : in std_logic := '1';
signb : in std_logic := '1';
clk : in std_logic_vector (3 downto 0) := "0000";
aclr : in std_logic_vector (3 downto 0) := "0000";
ena : in std_logic_vector (3 downto 0) := "1111";
mode0 : in std_logic := '0';
mode1 : in std_logic := '0';
zeroacc1 : in std_logic := '0';
saturate1 : in std_logic := '0';
dataout : out std_logic_vector (dataout_width -1 downto 0);
accoverflow : out std_logic;
devclrn : in std_logic := '1';
devpor : in std_logic := '1'
);
end component;
--
-- STRATIXII_PLL
--
COMPONENT stratixii_pll
GENERIC (operation_mode : string := "normal";
pll_type : string := "auto";
compensate_clock : string := "clk0";
feedback_source : string := "e0";
qualify_conf_done : string := "off";
test_input_comp_delay : integer := 0;
test_feedback_comp_delay : integer := 0;
inclk0_input_frequency : integer := 10000;
inclk1_input_frequency : integer := 10000;
gate_lock_signal : string := "yes";
gate_lock_counter : integer := 1;
self_reset_on_gated_loss_lock : string := "off";
valid_lock_multiplier : integer := 1;
invalid_lock_multiplier : integer := 5;
switch_over_type : string := "auto";
switch_over_on_lossclk : string := "off";
switch_over_on_gated_lock : string := "off";
switch_over_counter : integer := 1;
enable_switch_over_counter : string := "off";
bandwidth : integer := 0;
bandwidth_type : string := "auto";
down_spread : string := "0 %";
spread_frequency : integer := 0;
clk0_output_frequency : integer := 0;
clk0_multiply_by : integer := 1;
clk0_divide_by : integer := 1;
clk0_phase_shift : string := "0";
clk0_duty_cycle : integer := 50;
clk1_output_frequency : integer := 0;
clk1_multiply_by : integer := 1;
clk1_divide_by : integer := 1;
clk1_phase_shift : string := "0";
clk1_duty_cycle : integer := 50;
clk2_output_frequency : integer := 0;
clk2_multiply_by : integer := 1;
clk2_divide_by : integer := 1;
clk2_phase_shift : string := "0";
clk2_duty_cycle : integer := 50;
clk3_output_frequency : integer := 0;
clk3_multiply_by : integer := 1;
clk3_divide_by : integer := 1;
clk3_phase_shift : string := "0";
clk3_duty_cycle : integer := 50;
clk4_output_frequency : integer := 0;
clk4_multiply_by : integer := 1;
clk4_divide_by : integer := 1;
clk4_phase_shift : string := "0";
clk4_duty_cycle : integer := 50;
clk5_output_frequency : integer := 0;
clk5_multiply_by : integer := 1;
clk5_divide_by : integer := 1;
clk5_phase_shift : string := "0";
clk5_duty_cycle : integer := 50;
pfd_min : integer := 0;
pfd_max : integer := 0;
vco_min : integer := 0;
vco_max : integer := 0;
vco_center : integer := 0;
-- ADVANCED USE PARAMETERS
m_initial : integer := 1;
m : integer := 1;
n : integer := 1;
m2 : integer := 1;
n2 : integer := 1;
ss : integer := 0;
c0_high : integer := 1;
c0_low : integer := 1;
c0_initial : integer := 1;
c0_mode : string := "bypass";
c0_ph : integer := 0;
c1_high : integer := 1;
c1_low : integer := 1;
c1_initial : integer := 1;
c1_mode : string := "bypass";
c1_ph : integer := 0;
c2_high : integer := 1;
c2_low : integer := 1;
c2_initial : integer := 1;
c2_mode : string := "bypass";
c2_ph : integer := 0;
c3_high : integer := 1;
c3_low : integer := 1;
c3_initial : integer := 1;
c3_mode : string := "bypass";
c3_ph : integer := 0;
c4_high : integer := 1;
c4_low : integer := 1;
c4_initial : integer := 1;
c4_mode : string := "bypass";
c4_ph : integer := 0;
c5_high : integer := 1;
c5_low : integer := 1;
c5_initial : integer := 1;
c5_mode : string := "bypass";
c5_ph : integer := 0;
m_ph : integer := 0;
clk0_counter : string := "c0";
clk1_counter : string := "c1";
clk2_counter : string := "c2";
clk3_counter : string := "c3";
clk4_counter : string := "c4";
clk5_counter : string := "c5";
c1_use_casc_in : string := "off";
c2_use_casc_in : string := "off";
c3_use_casc_in : string := "off";
c4_use_casc_in : string := "off";
c5_use_casc_in : string := "off";
m_test_source : integer := 5;
c0_test_source : integer := 5;
c1_test_source : integer := 5;
c2_test_source : integer := 5;
c3_test_source : integer := 5;
c4_test_source : integer := 5;
c5_test_source : integer := 5;
enable0_counter : string := "c0";
enable1_counter : string := "c1";
sclkout0_phase_shift : string := "0";
sclkout1_phase_shift : string := "0";
charge_pump_current : integer := 0;
loop_filter_c : integer := 1;
loop_filter_r : string := "1.0" ;
common_rx_tx : string := "off";
rx_outclock_resource : string := "auto";
use_vco_bypass : string := "false";
use_dc_coupling : string := "false";
pll_compensation_delay : integer := 0;
simulation_type : string := "functional";
lpm_type : string := "stratixii_pll";
clk0_use_even_counter_mode : string := "off";
clk1_use_even_counter_mode : string := "off";
clk2_use_even_counter_mode : string := "off";
clk3_use_even_counter_mode : string := "off";
clk4_use_even_counter_mode : string := "off";
clk5_use_even_counter_mode : string := "off";
clk0_use_even_counter_value : string := "off";
clk1_use_even_counter_value : string := "off";
clk2_use_even_counter_value : string := "off";
clk3_use_even_counter_value : string := "off";
clk4_use_even_counter_value : string := "off";
clk5_use_even_counter_value : string := "off";
vco_multiply_by : integer := 0;
vco_divide_by : integer := 0;
vco_post_scale : integer := 1;
XOn : Boolean := DefGlitchXOn;
MsgOn : Boolean := DefGlitchMsgOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
TimingChecksOn : Boolean := true;
InstancePath : STRING := "*";
tipd_inclk : VitalDelayArrayType01(1 downto 0) := (OTHERS => DefPropDelay01);
tipd_ena : VitalDelayType01 := DefPropDelay01;
tipd_pfdena : VitalDelayType01 := DefPropDelay01;
tipd_areset : VitalDelayType01 := DefPropDelay01;
tipd_fbin : VitalDelayType01 := DefPropDelay01;
tipd_scanclk : VitalDelayType01 := DefPropDelay01;
tipd_scanread : VitalDelayType01 := DefPropDelay01;
tipd_scanwrite : VitalDelayType01 := DefPropDelay01;
tipd_scandata : VitalDelayType01 := DefPropDelay01;
tipd_clkswitch : VitalDelayType01 := DefPropDelay01;
tsetup_scandata_scanclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_scandata_scanclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_scanread_scanclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_scanread_scanclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_scanwrite_scanclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_scanwrite_scanclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst
);
PORT (inclk : IN std_logic_vector(1 downto 0);
fbin : IN std_logic := '0';
ena : IN std_logic := '1';
clkswitch : IN std_logic := '0';
areset : IN std_logic := '0';
pfdena : IN std_logic := '1';
scanread : IN std_logic := '0';
scanwrite : IN std_logic := '0';
scandata : IN std_logic := '0';
scanclk : IN std_logic := '0';
testin : IN std_logic_vector(3 downto 0) := "0000";
clk : OUT std_logic_vector(5 downto 0);
clkbad : OUT std_logic_vector(1 downto 0);
activeclock : OUT std_logic;
locked : OUT std_logic;
clkloss : OUT std_logic;
scandataout : OUT std_logic;
scandone : OUT std_logic;
testupout : OUT std_logic;
testdownout : OUT std_logic;
-- lvds specific ports
enable0 : OUT std_logic;
enable1 : OUT std_logic;
sclkout : OUT std_logic_vector(1 downto 0)
);
END COMPONENT;
--
-- STRATIXII_LVDS_TRANSMITTER
--
COMPONENT stratixii_lvds_transmitter
GENERIC ( channel_width : integer := 10;
bypass_serializer : String := "false";
invert_clock : String := "false";
use_falling_clock_edge : String := "false";
use_serial_data_input : String := "false";
use_post_dpa_serial_data_input : String := "false";
preemphasis_setting : integer := 0;
vod_setting : integer := 0;
differential_drive : integer := 0;
lpm_type : String := "stratixii_lvds_transmitter";
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*";
tpd_clk0_dataout_posedge : VitalDelayType01 := DefPropDelay01;
tpd_clk0_dataout_negedge : VitalDelayType01 := DefPropDelay01;
tpd_serialdatain_dataout : VitalDelayType01 := DefPropDelay01;
tpd_postdpaserialdatain_dataout : VitalDelayType01 := DefPropDelay01;
tipd_clk0 : VitalDelayType01 := DefpropDelay01;
tipd_enable0 : VitalDelayType01 := DefpropDelay01;
tipd_datain : VitalDelayArrayType01(9 downto 0) := (OTHERS => DefpropDelay01);
tipd_serialdatain : VitalDelayType01 := DefpropDelay01;
tipd_postdpaserialdatain : VitalDelayType01 := DefpropDelay01
);
PORT ( clk0 : in std_logic;
enable0 : in std_logic := '0';
datain : in std_logic_vector(channel_width - 1 downto 0) := (OTHERS => '0');
serialdatain : in std_logic := '0';
postdpaserialdatain : in std_logic := '0';
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
dataout : out std_logic;
serialfdbkout : out std_logic
);
END COMPONENT;
--
-- STRATIXII_LVDS_RECEIVER
--
COMPONENT stratixii_lvds_receiver
GENERIC ( channel_width : integer := 10;
data_align_rollover : integer := 2;
enable_dpa : string := "off";
lose_lock_on_one_change : string := "off";
reset_fifo_at_first_lock : string := "on";
align_to_rising_edge_only : string := "on";
use_serial_feedback_input : string := "off";
dpa_debug : string := "off";
x_on_bitslip : string := "on";
lpm_type : string := "stratixii_lvds_receiver";
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*";
tipd_clk0 : VitalDelayType01 := DefpropDelay01;
tipd_datain : VitalDelayType01 := DefpropDelay01;
tipd_enable0 : VitalDelayType01 := DefpropDelay01;
tipd_dpareset : VitalDelayType01 := DefpropDelay01;
tipd_dpahold : VitalDelayType01 := DefpropDelay01;
tipd_dpaswitch : VitalDelayType01 := DefpropDelay01;
tipd_fiforeset : VitalDelayType01 := DefpropDelay01;
tipd_bitslip : VitalDelayType01 := DefpropDelay01;
tipd_bitslipreset : VitalDelayType01 := DefpropDelay01;
tipd_serialfbk : VitalDelayType01 := DefpropDelay01;
tpd_clk0_dpalock_posedge : VitalDelayType01 := DefPropDelay01
);
PORT ( clk0 : IN std_logic;
datain : IN std_logic := '0';
enable0 : IN std_logic := '0';
dpareset : IN std_logic := '0';
dpahold : IN std_logic := '0';
dpaswitch : IN std_logic := '0';
fiforeset : IN std_logic := '0';
bitslip : IN std_logic := '0';
bitslipreset : IN std_logic := '0';
serialfbk : IN std_logic := '0';
dataout : OUT std_logic_vector(channel_width - 1 DOWNTO 0);
dpalock : OUT std_logic;
bitslipmax : OUT std_logic;
serialdataout : OUT std_logic;
postdpaserialdataout : OUT std_logic;
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1'
);
END COMPONENT;
--
-- STRATIXII_DLL_COMPONENT
--
COMPONENT stratixii_dll
GENERIC (
input_frequency : string := "10000 ps";
delay_chain_length : integer := 16;
delay_buffer_mode : string := "low";
delayctrlout_mode : string := "normal";
static_delay_ctrl : integer := 0;
offsetctrlout_mode : string := "static";
static_offset : string := "0";
jitter_reduction : string := "false";
use_upndnin : string := "false";
use_upndninclkena : string := "false";
sim_valid_lock : integer := 1;
sim_loop_intrinsic_delay : integer := 1000;
sim_loop_delay_increment : integer := 100;
sim_valid_lockcount : integer := 90; -- 10000 = 1000 + 100*dllcounter
lpm_type : string := "stratixii_dll";
tipd_clk : VitalDelayType01 := DefpropDelay01;
tipd_aload : VitalDelayType01 := DefpropDelay01;
tipd_offset : VitalDelayArrayType01(5 downto 0) := (OTHERS => DefPropDelay01);
tipd_upndnin : VitalDelayType01 := DefpropDelay01;
tipd_upndninclkena : VitalDelayType01 := DefpropDelay01;
tipd_addnsub : VitalDelayType01 := DefpropDelay01;
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*";
tpd_offset_delayctrlout : VitalDelayType01 := DefPropDelay01;
tpd_clk_upndnout_posedge : VitalDelayType01 := DefPropDelay01;
tsetup_offset_clk_noedge_posedge : VitalDelayArrayType(5 downto 0) := (OTHERS => DefSetupHoldCnst);
thold_offset_clk_noedge_posedge : VitalDelayArrayType(5 downto 0) := (OTHERS => DefSetupHoldCnst);
tsetup_upndnin_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_upndnin_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_upndninclkena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_upndninclkena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_addnsub_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_addnsub_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_clk_delayctrlout_posedge : VitalDelayArrayType01(5 downto 0) := (OTHERS => DefPropDelay01)
);
PORT ( clk : IN std_logic := '0';
aload : IN std_logic := '0';
offset : IN std_logic_vector(5 DOWNTO 0) := "000000";
upndnin : IN std_logic := '0';
upndninclkena : IN std_logic := '1';
addnsub : IN std_logic := '0';
delayctrlout : OUT std_logic_vector(5 DOWNTO 0);
offsetctrlout : OUT std_logic_vector(5 DOWNTO 0);
dqsupdate : OUT std_logic;
upndnout : OUT std_logic;
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1'
);
END COMPONENT;
--
--
-- STRATIXII_RUBLOCK
--
--
component stratixii_rublock
generic
(
operation_mode : string := "remote";
sim_init_config : string := "factory";
sim_init_watchdog_value : integer := 0;
sim_init_page_select : integer := 0;
sim_init_status : integer := 0;
lpm_type : string := "stratixii_rublock"
);
port
(
clk : in std_logic;
shiftnld : in std_logic;
captnupdt : in std_logic;
regin : in std_logic;
rsttimer : in std_logic;
rconfig : in std_logic;
regout : out std_logic;
pgmout : out std_logic_vector(2 downto 0)
);
end component;
--
-- STRATIXII_TERMINATION_COMPONENT
--
COMPONENT stratixii_termination
GENERIC (
runtime_control : string := "false";
use_core_control : string := "false";
pullup_control_to_core : string := "true";
use_high_voltage_compare : string := "true";
use_both_compares : string := "false";
pullup_adder : integer := 0;
pulldown_adder : integer := 0;
half_rate_clock : string := "false";
power_down : string := "true";
left_shift : string := "false";
test_mode : string := "false";
lpm_type : string := "stratixii_termination";
tipd_rup : VitalDelayType01 := DefpropDelay01;
tipd_rdn : VitalDelayType01 := DefpropDelay01;
tipd_terminationclock : VitalDelayType01 := DefpropDelay01;
tipd_terminationclear : VitalDelayType01 := DefpropDelay01;
tipd_terminationenable : VitalDelayType01 := DefpropDelay01;
tipd_terminationpullup : VitalDelayArrayType01(6 downto 0) := (OTHERS => DefPropDelay01);
tipd_terminationpulldown : VitalDelayArrayType01(6 downto 0) := (OTHERS => DefPropDelay01);
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*";
tpd_terminationclock_terminationcontrol_posedge : VitalDelayArrayType01(13 downto 0) := (OTHERS => DefPropDelay01);
tpd_terminationclock_terminationcontrolprobe_posedge : VitalDelayArrayType01(6 downto 0) := (OTHERS => DefPropDelay01)
);
PORT (
rup : IN std_logic := '0';
rdn : IN std_logic := '0';
terminationclock : IN std_logic := '0';
terminationclear : IN std_logic := '0';
terminationenable : IN std_logic := '1';
terminationpullup : IN std_logic_vector(6 DOWNTO 0) := "0000000";
terminationpulldown : IN std_logic_vector(6 DOWNTO 0) := "0000000";
devclrn : IN std_logic := '1';
devpor : IN std_logic := '0';
incrup : OUT std_logic;
incrdn : OUT std_logic;
terminationcontrol : OUT std_logic_vector(13 DOWNTO 0);
terminationcontrolprobe : OUT std_logic_vector(6 DOWNTO 0)
);
END COMPONENT;
--
-- STRATIXII_ROUTING_WIRE
--
component stratixii_routing_wire
generic (
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
tpd_datain_dataout : VitalDelayType01 := DefPropDelay01;
tpd_datainglitch_dataout : VitalDelayType01 := DefPropDelay01;
tipd_datain : VitalDelayType01 := DefPropDelay01
);
PORT (
datain : in std_logic;
dataout : out std_logic
);
end component;
--
-- STRATIXII_JTAG
--
component stratixii_jtag
generic (
lpm_type : string := "stratixii_jtag"
);
port (
tms : in std_logic := '0';
tck : in std_logic := '0';
tdi : in std_logic := '0';
ntrst : in std_logic := '0';
tdoutap : in std_logic := '0';
tdouser : in std_logic := '0';
tdo: out std_logic;
tmsutap: out std_logic;
tckutap: out std_logic;
tdiutap: out std_logic;
shiftuser: out std_logic;
clkdruser: out std_logic;
updateuser: out std_logic;
runidleuser: out std_logic;
usr1user: out std_logic
);
end component;
--
--
-- STRATIXII_CRCBLOCK
--
--
component stratixii_crcblock
generic (
oscillator_divider : integer := 1;
lpm_type : string := "stratixii_crcblock"
);
port (
clk : in std_logic := '0';
shiftnld : in std_logic := '0';
ldsrc : in std_logic := '0';
crcerror : out std_logic;
regout : out std_logic
);
end component;
--
-- STRATIXII_ASMIBLOCK
--
component stratixii_asmiblock
generic (
lpm_type : string := "stratixii_asmiblock"
);
port (
dclkin : in std_logic;
scein : in std_logic;
sdoin : in std_logic;
oe : in std_logic;
data0out: out std_logic
);
end component;
--
-- STRATIXII_RAM_BLOCK
--
component stratixii_ram_block
generic
(
operation_mode : string := "single_port";
mixed_port_feed_through_mode : string := "dont_care";
ram_block_type : string := "auto";
logical_ram_name : string := "ram_name";
init_file : string := "init_file.hex";
init_file_layout : string := "none";
data_interleave_width_in_bits : integer := 1;
data_interleave_offset_in_bits : integer := 1;
port_a_logical_ram_depth : integer := 0;
port_a_logical_ram_width : integer := 0;
port_a_data_in_clear : string := "none";
port_a_address_clear : string := "none";
port_a_write_enable_clear : string := "none";
port_a_data_out_clock : string := "none";
port_a_data_out_clear : string := "none";
port_a_first_address : integer := 0;
port_a_last_address : integer := 0;
port_a_first_bit_number : integer := 0;
port_a_data_width : integer := 1;
port_a_byte_enable_clear : string := "none";
port_a_data_in_clock : string := "clock0";
port_a_address_clock : string := "clock0";
port_a_write_enable_clock : string := "clock0";
port_a_byte_enable_clock : string := "clock0";
port_b_logical_ram_depth : integer := 0;
port_b_logical_ram_width : integer := 0;
port_b_data_in_clock : string := "none";
port_b_data_in_clear : string := "none";
port_b_address_clock : string := "none";
port_b_address_clear : string := "none";
port_b_read_enable_write_enable_clock : string := "none";
port_b_read_enable_write_enable_clear : string := "none";
port_b_data_out_clock : string := "none";
port_b_data_out_clear : string := "none";
port_b_first_address : integer := 0;
port_b_last_address : integer := 0;
port_b_first_bit_number : integer := 0;
port_b_data_width : integer := 1;
port_b_byte_enable_clear : string := "none";
port_b_byte_enable_clock : string := "none";
port_a_address_width : integer := 1;
port_b_address_width : integer := 1;
port_a_byte_enable_mask_width : integer := 1;
port_b_byte_enable_mask_width : integer := 1;
power_up_uninitialized : string := "false";
port_a_byte_size : integer := 0;
port_a_disable_ce_on_input_registers : string := "off";
port_a_disable_ce_on_output_registers : string := "off";
port_b_byte_size : integer := 0;
port_b_disable_ce_on_input_registers : string := "off";
port_b_disable_ce_on_output_registers : string := "off";
lpm_type : string := "stratixii_ram_block";
lpm_hint : string := "true";
connectivity_checking : string := "off";
mem_init0 : bit_vector := X"0";
mem_init1 : bit_vector := X"0"
);
port
(
portawe : in std_logic := '0';
portabyteenamasks : in std_logic_vector (port_a_byte_enable_mask_width - 1 DOWNTO 0) := (others => '1');
portbbyteenamasks : in std_logic_vector (port_b_byte_enable_mask_width - 1 DOWNTO 0) := (others => '1');
portbrewe : in std_logic := '0';
clr0 : in std_logic := '0';
clr1 : in std_logic := '0';
clk0 : in std_logic := '0';
clk1 : in std_logic := '0';
ena0 : in std_logic := '1';
ena1 : in std_logic := '1';
portadatain : in std_logic_vector (port_a_data_width - 1 DOWNTO 0) := (others => '0');
portbdatain : in std_logic_vector (port_b_data_width - 1 DOWNTO 0) := (others => '0');
portaaddr : in std_logic_vector (port_a_address_width - 1 DOWNTO 0) := (others => '0');
portbaddr : in std_logic_vector (port_b_address_width - 1 DOWNTO 0) := (others => '0');
portaaddrstall : in std_logic := '0';
portbaddrstall : in std_logic := '0';
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
portadataout : out std_logic_vector (port_a_data_width - 1 DOWNTO 0);
portbdataout : out std_logic_vector (port_b_data_width - 1 DOWNTO 0)
);
end component;
end stratixii_components;
| mit | f16a088c7a9f6fe4833791137f11d18d | 0.49536 | 4.174588 | false | false | false | false |
impedimentToProgress/UCI-BlueChip | AttackFiles/Attacks/privEsc/lib/tech/unisim/vcomponents/xilinx_vcomponents.vhd | 2 | 125,241 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Package: vcomponents
-- File: vcomponents.vhd
-- Author: Jiri Gaisler, Gaisler Research
-- Description: Component declartions of some XILINX primitives
-----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
package vcomponents is
component ramb4_s16 port (
do : out std_logic_vector (15 downto 0);
addr : in std_logic_vector (7 downto 0);
clk : in std_ulogic;
di : in std_logic_vector (15 downto 0);
en, rst, we : in std_ulogic);
end component;
component RAMB4_S8
port (do : out std_logic_vector (7 downto 0);
addr : in std_logic_vector (8 downto 0);
clk : in std_ulogic;
di : in std_logic_vector (7 downto 0);
en, rst, we : in std_ulogic);
end component;
component RAMB4_S4
port (do : out std_logic_vector (3 downto 0);
addr : in std_logic_vector (9 downto 0);
clk : in std_ulogic;
di : in std_logic_vector (3 downto 0);
en, rst, we : in std_ulogic);
end component;
component RAMB4_S2
port (do : out std_logic_vector (1 downto 0);
addr : in std_logic_vector (10 downto 0);
clk : in std_ulogic;
di : in std_logic_vector (1 downto 0);
en, rst, we : in std_ulogic);
end component;
component RAMB4_S1
port (do : out std_logic_vector (0 downto 0);
addr : in std_logic_vector (11 downto 0);
clk : in std_ulogic;
di : in std_logic_vector (0 downto 0);
en, rst, we : in std_ulogic);
end component;
component RAMB4_S1_S1
port (
doa : out std_logic_vector (0 downto 0);
dob : out std_logic_vector (0 downto 0);
addra : in std_logic_vector (11 downto 0);
addrb : in std_logic_vector (11 downto 0);
clka : in std_ulogic;
clkb : in std_ulogic;
dia : in std_logic_vector (0 downto 0);
dib : in std_logic_vector (0 downto 0);
ena : in std_ulogic;
enb : in std_ulogic;
rsta : in std_ulogic;
rstb : in std_ulogic;
wea : in std_ulogic;
web : in std_ulogic
);
end component;
component RAMB4_S2_S2
port (
doa : out std_logic_vector (1 downto 0);
dob : out std_logic_vector (1 downto 0);
addra : in std_logic_vector (10 downto 0);
addrb : in std_logic_vector (10 downto 0);
clka : in std_ulogic;
clkb : in std_ulogic;
dia : in std_logic_vector (1 downto 0);
dib : in std_logic_vector (1 downto 0);
ena : in std_ulogic;
enb : in std_ulogic;
rsta : in std_ulogic;
rstb : in std_ulogic;
wea : in std_ulogic;
web : in std_ulogic
);
end component;
component RAMB4_S4_S4
port (
doa : out std_logic_vector (3 downto 0);
dob : out std_logic_vector (3 downto 0);
addra : in std_logic_vector (9 downto 0);
addrb : in std_logic_vector (9 downto 0);
clka : in std_ulogic;
clkb : in std_ulogic;
dia : in std_logic_vector (3 downto 0);
dib : in std_logic_vector (3 downto 0);
ena : in std_ulogic;
enb : in std_ulogic;
rsta : in std_ulogic;
rstb : in std_ulogic;
wea : in std_ulogic;
web : in std_ulogic
);
end component;
component RAMB4_S8_S8
port (
doa : out std_logic_vector (7 downto 0);
dob : out std_logic_vector (7 downto 0);
addra : in std_logic_vector (8 downto 0);
addrb : in std_logic_vector (8 downto 0);
clka : in std_ulogic;
clkb : in std_ulogic;
dia : in std_logic_vector (7 downto 0);
dib : in std_logic_vector (7 downto 0);
ena : in std_ulogic;
enb : in std_ulogic;
rsta : in std_ulogic;
rstb : in std_ulogic;
wea : in std_ulogic;
web : in std_ulogic
);
end component;
component RAMB4_S16_S16
port (
doa : out std_logic_vector (15 downto 0);
dob : out std_logic_vector (15 downto 0);
addra : in std_logic_vector (7 downto 0);
addrb : in std_logic_vector (7 downto 0);
clka : in std_ulogic;
clkb : in std_ulogic;
dia : in std_logic_vector (15 downto 0);
dib : in std_logic_vector (15 downto 0);
ena : in std_ulogic;
enb : in std_ulogic;
rsta : in std_ulogic;
rstb : in std_ulogic;
wea : in std_ulogic;
web : in std_ulogic
);
end component;
component RAMB16_S1
-- pragma translate_off
generic
(
INIT : bit_vector := X"0";
SRVAL : bit_vector := X"0";
WRITE_MODE : string := "WRITE_FIRST";
INIT_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_08 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_09 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_10 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_11 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_12 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_13 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_14 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_15 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_16 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_17 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_18 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_19 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_20 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_21 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_22 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_23 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_24 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_25 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_26 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_27 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_28 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_29 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_30 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_31 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_32 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_33 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_34 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_35 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_36 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_37 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_38 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_39 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"
);
-- pragma translate_on
port (
DO : out std_logic_vector (0 downto 0);
ADDR : in std_logic_vector (13 downto 0);
CLK : in std_ulogic;
DI : in std_logic_vector (0 downto 0);
EN : in std_ulogic;
SSR : in std_ulogic;
WE : in std_ulogic
);
end component;
component RAMB16_S2
-- pragma translate_off
generic
(
INIT : bit_vector := X"0";
SRVAL : bit_vector := X"0";
WRITE_MODE : string := "WRITE_FIRST";
INIT_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_08 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_09 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_10 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_11 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_12 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_13 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_14 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_15 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_16 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_17 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_18 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_19 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_20 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_21 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_22 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_23 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_24 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_25 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_26 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_27 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_28 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_29 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_30 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_31 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_32 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_33 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_34 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_35 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_36 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_37 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_38 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_39 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"
);
-- pragma translate_on
port (
DO : out std_logic_vector (1 downto 0);
ADDR : in std_logic_vector (12 downto 0);
CLK : in std_ulogic;
DI : in std_logic_vector (1 downto 0);
EN : in std_ulogic;
SSR : in std_ulogic;
WE : in std_ulogic
);
end component;
component RAMB16_S4
-- pragma translate_off
generic
(
INIT : bit_vector := X"0";
SRVAL : bit_vector := X"0";
WRITE_MODE : string := "WRITE_FIRST";
INIT_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_08 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_09 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_10 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_11 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_12 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_13 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_14 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_15 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_16 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_17 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_18 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_19 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_20 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_21 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_22 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_23 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_24 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_25 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_26 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_27 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_28 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_29 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_30 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_31 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_32 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_33 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_34 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_35 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_36 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_37 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_38 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_39 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"
);
-- pragma translate_on
port (
DO : out std_logic_vector (3 downto 0);
ADDR : in std_logic_vector (11 downto 0);
CLK : in std_ulogic;
DI : in std_logic_vector (3 downto 0);
EN : in std_ulogic;
SSR : in std_ulogic;
WE : in std_ulogic
);
end component;
component RAMB16_S9
-- pragma translate_off
generic
(
INIT : bit_vector := X"000";
SRVAL : bit_vector := X"000";
WRITE_MODE : string := "WRITE_FIRST";
INIT_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_08 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_09 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_10 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_11 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_12 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_13 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_14 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_15 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_16 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_17 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_18 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_19 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_20 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_21 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_22 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_23 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_24 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_25 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_26 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_27 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_28 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_29 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_30 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_31 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_32 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_33 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_34 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_35 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_36 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_37 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_38 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_39 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"
);
-- pragma translate_on
port (
DO : out std_logic_vector (7 downto 0);
DOP : out std_logic_vector (0 downto 0);
ADDR : in std_logic_vector (10 downto 0);
CLK : in std_ulogic;
DI : in std_logic_vector (7 downto 0);
DIP : in std_logic_vector (0 downto 0);
EN : in std_ulogic;
SSR : in std_ulogic;
WE : in std_ulogic
);
end component;
component RAMB16_S18
-- pragma translate_off
generic
(
INIT : bit_vector := X"00000";
SRVAL : bit_vector := X"00000";
write_mode : string := "WRITE_FIRST";
INITP_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_08 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_09 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_10 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_11 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_12 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_13 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_14 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_15 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_16 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_17 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_18 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_19 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_20 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_21 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_22 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_23 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_24 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_25 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_26 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_27 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_28 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_29 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_30 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_31 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_32 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_33 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_34 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_35 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_36 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_37 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_38 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_39 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"
);
-- pragma translate_on
port (
DO : out std_logic_vector (15 downto 0);
DOP : out std_logic_vector (1 downto 0);
ADDR : in std_logic_vector (9 downto 0);
CLK : in std_ulogic;
DI : in std_logic_vector (15 downto 0);
DIP : in std_logic_vector (1 downto 0);
EN : in std_ulogic;
SSR : in std_ulogic;
WE : in std_ulogic
);
end component;
component RAMB16_S36
-- pragma translate_off
generic
(
INIT : bit_vector := X"000000000";
SRVAL : bit_vector := X"000000000";
WRITE_MODE : string := "WRITE_FIRST";
INITP_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_08 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_09 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_10 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_11 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_12 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_13 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_14 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_15 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_16 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_17 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_18 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_19 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_20 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_21 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_22 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_23 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_24 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_25 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_26 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_27 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_28 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_29 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_30 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_31 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_32 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_33 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_34 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_35 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_36 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_37 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_38 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_39 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"
);
-- pragma translate_on
port (
DO : out std_logic_vector (31 downto 0);
DOP : out std_logic_vector (3 downto 0);
ADDR : in std_logic_vector (8 downto 0);
CLK : in std_ulogic;
DI : in std_logic_vector (31 downto 0);
DIP : in std_logic_vector (3 downto 0);
EN : in std_ulogic;
SSR : in std_ulogic;
WE : in std_ulogic
);
end component;
component RAMB16_S4_S4
-- pragma translate_off
generic
(
INIT_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_08 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_09 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_10 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_11 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_12 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_13 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_14 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_15 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_16 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_17 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_18 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_19 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_20 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_21 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_22 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_23 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_24 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_25 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_26 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_27 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_28 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_29 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_30 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_31 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_32 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_33 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_34 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_35 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_36 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_37 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_38 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_39 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_A : bit_vector := X"0";
INIT_B : bit_vector := X"0";
SIM_COLLISION_CHECK : string := "ALL";
SRVAL_A : bit_vector := X"0";
SRVAL_B : bit_vector := X"0";
WRITE_MODE_A : string := "WRITE_FIRST";
WRITE_MODE_B : string := "WRITE_FIRST"
);
-- pragma translate_on
port (
DOA : out std_logic_vector (3 downto 0);
DOB : out std_logic_vector (3 downto 0);
ADDRA : in std_logic_vector (11 downto 0);
ADDRB : in std_logic_vector (11 downto 0);
CLKA : in std_ulogic;
CLKB : in std_ulogic;
DIA : in std_logic_vector (3 downto 0);
DIB : in std_logic_vector (3 downto 0);
ENA : in std_ulogic;
ENB : in std_ulogic;
SSRA : in std_ulogic;
SSRB : in std_ulogic;
WEA : in std_ulogic;
WEB : in std_ulogic
);
end component;
component RAMB16_S1_S1
-- pragma translate_off
generic
(
INIT_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_08 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_09 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_10 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_11 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_12 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_13 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_14 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_15 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_16 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_17 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_18 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_19 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_20 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_21 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_22 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_23 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_24 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_25 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_26 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_27 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_28 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_29 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_30 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_31 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_32 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_33 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_34 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_35 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_36 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_37 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_38 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_39 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_A : bit_vector := X"0";
INIT_B : bit_vector := X"0";
SIM_COLLISION_CHECK : string := "ALL";
SRVAL_A : bit_vector := X"0";
SRVAL_B : bit_vector := X"0";
WRITE_MODE_A : string := "WRITE_FIRST";
WRITE_MODE_B : string := "WRITE_FIRST"
);
-- pragma translate_on
port (
DOA : out std_logic_vector (0 downto 0);
DOB : out std_logic_vector (0 downto 0);
ADDRA : in std_logic_vector (13 downto 0);
ADDRB : in std_logic_vector (13 downto 0);
CLKA : in std_ulogic;
CLKB : in std_ulogic;
DIA : in std_logic_vector (0 downto 0);
DIB : in std_logic_vector (0 downto 0);
ENA : in std_ulogic;
ENB : in std_ulogic;
SSRA : in std_ulogic;
SSRB : in std_ulogic;
WEA : in std_ulogic;
WEB : in std_ulogic
);
end component;
component RAMB16_S2_S2
-- pragma translate_off
generic
(
INIT_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_08 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_09 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_10 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_11 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_12 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_13 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_14 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_15 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_16 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_17 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_18 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_19 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_20 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_21 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_22 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_23 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_24 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_25 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_26 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_27 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_28 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_29 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_30 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_31 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_32 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_33 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_34 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_35 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_36 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_37 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_38 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_39 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_A : bit_vector := X"0";
INIT_B : bit_vector := X"0";
SIM_COLLISION_CHECK : string := "ALL";
SRVAL_A : bit_vector := X"0";
SRVAL_B : bit_vector := X"0";
WRITE_MODE_A : string := "WRITE_FIRST";
WRITE_MODE_B : string := "WRITE_FIRST"
);
-- pragma translate_on
port (
DOA : out std_logic_vector (1 downto 0);
DOB : out std_logic_vector (1 downto 0);
ADDRA : in std_logic_vector (12 downto 0);
ADDRB : in std_logic_vector (12 downto 0);
CLKA : in std_ulogic;
CLKB : in std_ulogic;
DIA : in std_logic_vector (1 downto 0);
DIB : in std_logic_vector (1 downto 0);
ENA : in std_ulogic;
ENB : in std_ulogic;
SSRA : in std_ulogic;
SSRB : in std_ulogic;
WEA : in std_ulogic;
WEB : in std_ulogic
);
end component;
component RAMB16_S9_S9
-- pragma translate_off
generic
(
INIT_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_08 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_09 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_10 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_11 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_12 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_13 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_14 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_15 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_16 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_17 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_18 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_19 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_20 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_21 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_22 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_23 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_24 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_25 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_26 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_27 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_28 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_29 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_30 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_31 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_32 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_33 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_34 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_35 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_36 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_37 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_38 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_39 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_A : bit_vector := X"000";
INIT_B : bit_vector := X"000";
SIM_COLLISION_CHECK : string := "ALL";
SRVAL_A : bit_vector := X"000";
SRVAL_B : bit_vector := X"000";
WRITE_MODE_A : string := "WRITE_FIRST";
WRITE_MODE_B : string := "WRITE_FIRST"
);
-- pragma translate_on
port (
DOA : out std_logic_vector (7 downto 0);
DOB : out std_logic_vector (7 downto 0);
DOPA : out std_logic_vector (0 downto 0);
DOPB : out std_logic_vector (0 downto 0);
ADDRA : in std_logic_vector (10 downto 0);
ADDRB : in std_logic_vector (10 downto 0);
CLKA : in std_ulogic;
CLKB : in std_ulogic;
DIA : in std_logic_vector (7 downto 0);
DIB : in std_logic_vector (7 downto 0);
DIPA : in std_logic_vector (0 downto 0);
DIPB : in std_logic_vector (0 downto 0);
ENA : in std_ulogic;
ENB : in std_ulogic;
SSRA : in std_ulogic;
SSRB : in std_ulogic;
WEA : in std_ulogic;
WEB : in std_ulogic
);
end component;
component RAMB16_S18_S18
-- pragma translate_off
generic
(
INIT_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_08 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_09 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_10 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_11 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_12 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_13 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_14 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_15 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_16 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_17 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_18 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_19 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_20 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_21 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_22 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_23 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_24 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_25 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_26 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_27 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_28 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_29 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_30 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_31 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_32 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_33 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_34 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_35 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_36 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_37 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_38 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_39 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_A : bit_vector := X"00000";
INIT_B : bit_vector := X"00000";
SIM_COLLISION_CHECK : string := "ALL";
SRVAL_A : bit_vector := X"00000";
SRVAL_B : bit_vector := X"00000";
WRITE_MODE_A : string := "WRITE_FIRST";
WRITE_MODE_B : string := "WRITE_FIRST"
);
-- pragma translate_on
port (
DOA : out std_logic_vector (15 downto 0);
DOB : out std_logic_vector (15 downto 0);
DOPA : out std_logic_vector (1 downto 0);
DOPB : out std_logic_vector (1 downto 0);
ADDRA : in std_logic_vector (9 downto 0);
ADDRB : in std_logic_vector (9 downto 0);
CLKA : in std_ulogic;
CLKB : in std_ulogic;
DIA : in std_logic_vector (15 downto 0);
DIB : in std_logic_vector (15 downto 0);
DIPA : in std_logic_vector (1 downto 0);
DIPB : in std_logic_vector (1 downto 0);
ENA : in std_ulogic;
ENB : in std_ulogic;
SSRA : in std_ulogic;
SSRB : in std_ulogic;
WEA : in std_ulogic;
WEB : in std_ulogic);
end component;
component RAMB16_S36_S36
-- pragma translate_off
generic
(
INIT_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_08 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_09 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_10 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_11 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_12 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_13 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_14 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_15 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_16 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_17 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_18 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_19 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_20 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_21 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_22 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_23 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_24 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_25 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_26 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_27 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_28 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_29 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_30 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_31 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_32 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_33 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_34 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_35 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_36 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_37 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_38 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_39 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_A : bit_vector := X"000000000";
INIT_B : bit_vector := X"000000000";
SIM_COLLISION_CHECK : string := "ALL";
SRVAL_A : bit_vector := X"000000000";
SRVAL_B : bit_vector := X"000000000";
WRITE_MODE_A : string := "WRITE_FIRST";
WRITE_MODE_B : string := "WRITE_FIRST"
);
-- pragma translate_on
port (
DOA : out std_logic_vector (31 downto 0);
DOB : out std_logic_vector (31 downto 0);
DOPA : out std_logic_vector (3 downto 0);
DOPB : out std_logic_vector (3 downto 0);
ADDRA : in std_logic_vector (8 downto 0);
ADDRB : in std_logic_vector (8 downto 0);
CLKA : in std_ulogic;
CLKB : in std_ulogic;
DIA : in std_logic_vector (31 downto 0);
DIB : in std_logic_vector (31 downto 0);
DIPA : in std_logic_vector (3 downto 0);
DIPB : in std_logic_vector (3 downto 0);
ENA : in std_ulogic;
ENB : in std_ulogic;
SSRA : in std_ulogic;
SSRB : in std_ulogic;
WEA : in std_ulogic;
WEB : in std_ulogic);
end component;
component DCM
generic (
CLKDV_DIVIDE : real := 2.0;
CLKFX_DIVIDE : integer := 1;
CLKFX_MULTIPLY : integer := 4;
CLKIN_DIVIDE_BY_2 : boolean := false;
CLKIN_PERIOD : real := 10.0;
CLKOUT_PHASE_SHIFT : string := "NONE";
CLK_FEEDBACK : string := "1X";
DESKEW_ADJUST : string := "SYSTEM_SYNCHRONOUS";
DFS_FREQUENCY_MODE : string := "LOW";
DLL_FREQUENCY_MODE : string := "LOW";
DSS_MODE : string := "NONE";
DUTY_CYCLE_CORRECTION : boolean := true;
FACTORY_JF : bit_vector := X"C080";
PHASE_SHIFT : integer := 0;
STARTUP_WAIT : boolean := false
);
port (
CLKFB : in std_logic;
CLKIN : in std_logic;
DSSEN : in std_logic;
PSCLK : in std_logic;
PSEN : in std_logic;
PSINCDEC : in std_logic;
RST : in std_logic;
CLK0 : out std_logic;
CLK90 : out std_logic;
CLK180 : out std_logic;
CLK270 : out std_logic;
CLK2X : out std_logic;
CLK2X180 : out std_logic;
CLKDV : out std_logic;
CLKFX : out std_logic;
CLKFX180 : out std_logic;
LOCKED : out std_logic;
PSDONE : out std_logic;
STATUS : out std_logic_vector (7 downto 0));
end component;
component DCM_SP
generic (
TimingChecksOn : boolean := true;
InstancePath : string := "*";
Xon : boolean := true;
MsgOn : boolean := false;
CLKDV_DIVIDE : real := 2.0;
CLKFX_DIVIDE : integer := 1;
CLKFX_MULTIPLY : integer := 4;
CLKIN_DIVIDE_BY_2 : boolean := false;
CLKIN_PERIOD : real := 10.0; --non-simulatable
CLKOUT_PHASE_SHIFT : string := "NONE";
CLK_FEEDBACK : string := "1X";
DESKEW_ADJUST : string := "SYSTEM_SYNCHRONOUS"; --non-simulatable
DFS_FREQUENCY_MODE : string := "LOW";
DLL_FREQUENCY_MODE : string := "LOW";
DSS_MODE : string := "NONE"; --non-simulatable
DUTY_CYCLE_CORRECTION : boolean := true;
FACTORY_JF : bit_vector := X"C080"; --non-simulatable
PHASE_SHIFT : integer := 0;
STARTUP_WAIT : boolean := false --non-simulatable
);
port (
CLK0 : out std_ulogic := '0';
CLK180 : out std_ulogic := '0';
CLK270 : out std_ulogic := '0';
CLK2X : out std_ulogic := '0';
CLK2X180 : out std_ulogic := '0';
CLK90 : out std_ulogic := '0';
CLKDV : out std_ulogic := '0';
CLKFX : out std_ulogic := '0';
CLKFX180 : out std_ulogic := '0';
LOCKED : out std_ulogic := '0';
PSDONE : out std_ulogic := '0';
STATUS : out std_logic_vector(7 downto 0) := "00000000";
CLKFB : in std_ulogic := '0';
CLKIN : in std_ulogic := '0';
DSSEN : in std_ulogic := '0';
PSCLK : in std_ulogic := '0';
PSEN : in std_ulogic := '0';
PSINCDEC : in std_ulogic := '0';
RST : in std_ulogic := '0'
);
end component;
component BUFGMUX port (O : out std_logic; I0, I1, S : in std_logic); end component;
component BUFG port (O : out std_logic; I : in std_logic); end component;
component BUFGP port (O : out std_logic; I : in std_logic); end component;
component BUFGDLL port (O : out std_logic; I : in std_logic); end component;
component IBUFG generic(
CAPACITANCE : string := "DONT_CARE"; IOSTANDARD : string := "LVCMOS25");
port (O : out std_logic; I : in std_logic); end component;
component IBUF generic(
CAPACITANCE : string := "DONT_CARE"; IOSTANDARD : string := "LVCMOS25");
port (O : out std_ulogic; I : in std_ulogic); end component;
component IOBUF generic (
CAPACITANCE : string := "DONT_CARE"; DRIVE : integer := 12;
IOSTANDARD : string := "LVCMOS25"; SLEW : string := "SLOW");
port (O : out std_ulogic; IO : inout std_logic; I, T : in std_ulogic); end component;
component OBUF generic (
CAPACITANCE : string := "DONT_CARE"; DRIVE : integer := 12;
IOSTANDARD : string := "LVCMOS25"; SLEW : string := "SLOW");
port (O : out std_ulogic; I : in std_ulogic); end component;
component OBUFT generic (
CAPACITANCE : string := "DONT_CARE"; DRIVE : integer := 12;
IOSTANDARD : string := "LVCMOS25"; SLEW : string := "SLOW");
port (O : out std_ulogic; I, T : in std_ulogic); end component;
component CLKDLL
port (
CLK0 : out std_ulogic;
CLK180 : out std_ulogic;
CLK270 : out std_ulogic;
CLK2X : out std_ulogic;
CLK90 : out std_ulogic;
CLKDV : out std_ulogic;
LOCKED : out std_ulogic;
CLKFB : in std_ulogic;
CLKIN : in std_ulogic;
RST : in std_ulogic);
end component;
component CLKDLLHF
port (
CLK0 : out std_ulogic := '0';
CLK180 : out std_ulogic := '0';
CLKDV : out std_ulogic := '0';
LOCKED : out std_ulogic := '0';
CLKFB : in std_ulogic := '0';
CLKIN : in std_ulogic := '0';
RST : in std_ulogic := '0');
end component;
component BSCAN_VIRTEX
port (CAPTURE : out STD_ULOGIC;
DRCK1 : out STD_ULOGIC;
DRCK2 : out STD_ULOGIC;
RESET : out STD_ULOGIC;
SEL1 : out STD_ULOGIC;
SEL2 : out STD_ULOGIC;
SHIFT : out STD_ULOGIC;
TDI : out STD_ULOGIC;
UPDATE : out STD_ULOGIC;
TDO1 : in STD_ULOGIC;
TDO2 : in STD_ULOGIC);
end component;
component BSCAN_VIRTEX2
port (CAPTURE : out STD_ULOGIC;
DRCK1 : out STD_ULOGIC;
DRCK2 : out STD_ULOGIC;
RESET : out STD_ULOGIC;
SEL1 : out STD_ULOGIC;
SEL2 : out STD_ULOGIC;
SHIFT : out STD_ULOGIC;
TDI : out STD_ULOGIC;
UPDATE : out STD_ULOGIC;
TDO1 : in STD_ULOGIC;
TDO2 : in STD_ULOGIC);
end component;
component BSCAN_SPARTAN3
port (CAPTURE : out STD_ULOGIC;
DRCK1 : out STD_ULOGIC;
DRCK2 : out STD_ULOGIC;
RESET : out STD_ULOGIC;
SEL1 : out STD_ULOGIC;
SEL2 : out STD_ULOGIC;
SHIFT : out STD_ULOGIC;
TDI : out STD_ULOGIC;
UPDATE : out STD_ULOGIC;
TDO1 : in STD_ULOGIC;
TDO2 : in STD_ULOGIC);
end component;
component BSCAN_VIRTEX4 generic ( JTAG_CHAIN : integer := 1);
port ( CAPTURE : out std_ulogic;
DRCK : out std_ulogic;
RESET : out std_ulogic;
SEL : out std_ulogic;
SHIFT : out std_ulogic;
TDI : out std_ulogic;
UPDATE : out std_ulogic;
TDO : in std_ulogic);
end component;
component BSCAN_VIRTEX5 generic ( JTAG_CHAIN : integer := 1);
port ( CAPTURE : out std_ulogic;
DRCK : out std_ulogic;
RESET : out std_ulogic;
SEL : out std_ulogic;
SHIFT : out std_ulogic;
TDI : out std_ulogic;
UPDATE : out std_ulogic;
TDO : in std_ulogic);
end component;
component IBUFDS
generic (
CAPACITANCE : string := "DONT_CARE";
DIFF_TERM : boolean := FALSE;
IBUF_DELAY_VALUE : string := "0";
IFD_DELAY_VALUE : string := "AUTO";
IOSTANDARD : string := "DEFAULT");
port (
O : out std_ulogic;
I : in std_ulogic;
IB : in std_ulogic
);
end component;
component IBUFDS_LVDS_25
port ( O : out std_ulogic;
I : in std_ulogic;
IB : in std_ulogic);
end component;
component IBUFGDS_LVDS_25
port ( O : out std_ulogic;
I : in std_ulogic;
IB : in std_ulogic);
end component;
component IOBUFDS
generic(
CAPACITANCE : string := "DONT_CARE";
IBUF_DELAY_VALUE : string := "0";
IFD_DELAY_VALUE : string := "AUTO";
IOSTANDARD : string := "DEFAULT");
port (
O : out std_ulogic;
IO : inout std_ulogic;
IOB : inout std_ulogic;
I : in std_ulogic;
T : in std_ulogic
);
end component;
component OBUFDS
generic(
CAPACITANCE : string := "DONT_CARE";
IOSTANDARD : string := "DEFAULT"
);
port(
O : out std_ulogic;
OB : out std_ulogic;
I : in std_ulogic
);
end component;
component OBUFDS_LVDS_25
port ( O : out std_ulogic;
OB : out std_ulogic;
I : in std_ulogic);
end component;
component OBUFTDS_LVDS_25
port ( O : out std_ulogic;
OB : out std_ulogic;
I : in std_ulogic;
T : in std_ulogic);
end component;
component IBUFGDS is
generic( CAPACITANCE : string := "DONT_CARE";
DIFF_TERM : boolean := FALSE; IBUF_DELAY_VALUE : string := "0";
IOSTANDARD : string := "DEFAULT");
port (O : out std_logic; I, IB : in std_logic);
end component;
component IBUFDS_LVDS_33
port ( O : out std_ulogic;
I : in std_ulogic;
IB : in std_ulogic);
end component;
component IBUFGDS_LVDS_33
port ( O : out std_ulogic;
I : in std_ulogic;
IB : in std_ulogic);
end component;
component OBUFDS_LVDS_33
port ( O : out std_ulogic;
OB : out std_ulogic;
I : in std_ulogic);
end component;
component OBUFTDS_LVDS_33
port ( O : out std_ulogic;
OB : out std_ulogic;
I : in std_ulogic;
T : in std_ulogic);
end component;
component FDCPE
generic ( INIT : bit := '0');
port (
Q : out std_ulogic;
C : in std_ulogic;
CE : in std_ulogic;
CLR : in std_ulogic;
D : in std_ulogic;
PRE : in std_ulogic);
end component;
component IDDR
generic (
DDR_CLK_EDGE : string := "OPPOSITE_EDGE";
INIT_Q1 : bit := '0';
INIT_Q2 : bit := '0';
SRTYPE : string := "SYNC");
port
(
Q1 : out std_ulogic;
Q2 : out std_ulogic;
C : in std_ulogic;
CE : in std_ulogic;
D : in std_ulogic;
R : in std_ulogic;
S : in std_ulogic);
end component;
component ODDR
generic (
DDR_CLK_EDGE : string := "OPPOSITE_EDGE";
INIT : bit := '0';
SRTYPE : string := "SYNC");
port (
Q : out std_ulogic;
C : in std_ulogic;
CE : in std_ulogic;
D1 : in std_ulogic;
D2 : in std_ulogic;
R : in std_ulogic;
S : in std_ulogic);
end component;
component IFDDRRSE
port (
Q0 : out std_ulogic;
Q1 : out std_ulogic;
C0 : in std_ulogic;
C1 : in std_ulogic;
CE : in std_ulogic;
D : in std_ulogic;
R : in std_ulogic;
S : in std_ulogic);
end component;
component OFDDRRSE
port (
Q : out std_ulogic;
C0 : in std_ulogic;
C1 : in std_ulogic;
CE : in std_ulogic;
D0 : in std_ulogic;
D1 : in std_ulogic;
R : in std_ulogic;
S : in std_ulogic);
end component;
component FDDRRSE
generic ( INIT : bit := '0');
port ( Q : out std_ulogic;
C0 : in std_ulogic;
C1 : in std_ulogic;
CE : in std_ulogic;
D0 : in std_ulogic;
D1 : in std_ulogic;
R : in std_ulogic;
S : in std_ulogic);
end component;
component IDELAY
generic ( IOBDELAY_TYPE : string := "DEFAULT";
IOBDELAY_VALUE : integer := 0);
port ( O : out std_ulogic;
C : in std_ulogic;
CE : in std_ulogic;
I : in std_ulogic;
INC : in std_ulogic;
RST : in std_ulogic);
end component;
component IDELAYCTRL
port ( RDY : out std_ulogic;
REFCLK : in std_ulogic;
RST : in std_ulogic);
end component;
component BUFIO
port ( O : out std_ulogic;
I : in std_ulogic);
end component;
component BUFR
generic ( BUFR_DIVIDE : string := "BYPASS";
SIM_DEVICE : string := "VIRTEX4");
port ( O : out std_ulogic;
CE : in std_ulogic;
CLR : in std_ulogic;
I : in std_ulogic);
end component;
component ODDR2
generic
(
DDR_ALIGNMENT : string := "NONE";
INIT : bit := '0';
SRTYPE : string := "SYNC"
);
port
(
Q : out std_ulogic;
C0 : in std_ulogic;
C1 : in std_ulogic;
CE : in std_ulogic;
D0 : in std_ulogic;
D1 : in std_ulogic;
R : in std_ulogic;
S : in std_ulogic
);
end component;
component IDDR2
generic
(
DDR_ALIGNMENT : string := "NONE";
INIT_Q0 : bit := '0';
INIT_Q1 : bit := '0';
SRTYPE : string := "SYNC"
);
port
(
Q0 : out std_ulogic;
Q1 : out std_ulogic;
C0 : in std_ulogic;
C1 : in std_ulogic;
CE : in std_ulogic;
D : in std_ulogic;
R : in std_ulogic;
S : in std_ulogic
);
end component;
component SYSMON
generic
(
INIT_40 : bit_vector := X"0000";
INIT_41 : bit_vector := X"0000";
INIT_42 : bit_vector := X"0800";
INIT_43 : bit_vector := X"0000";
INIT_44 : bit_vector := X"0000";
INIT_45 : bit_vector := X"0000";
INIT_46 : bit_vector := X"0000";
INIT_47 : bit_vector := X"0000";
INIT_48 : bit_vector := X"0000";
INIT_49 : bit_vector := X"0000";
INIT_4A : bit_vector := X"0000";
INIT_4B : bit_vector := X"0000";
INIT_4C : bit_vector := X"0000";
INIT_4D : bit_vector := X"0000";
INIT_4E : bit_vector := X"0000";
INIT_4F : bit_vector := X"0000";
INIT_50 : bit_vector := X"0000";
INIT_51 : bit_vector := X"0000";
INIT_52 : bit_vector := X"0000";
INIT_53 : bit_vector := X"0000";
INIT_54 : bit_vector := X"0000";
INIT_55 : bit_vector := X"0000";
INIT_56 : bit_vector := X"0000";
INIT_57 : bit_vector := X"0000";
SIM_MONITOR_FILE : string := "design.txt"
);
port
(
ALM : out std_logic_vector(2 downto 0);
BUSY : out std_ulogic;
CHANNEL : out std_logic_vector(4 downto 0);
DO : out std_logic_vector(15 downto 0);
DRDY : out std_ulogic;
EOC : out std_ulogic;
EOS : out std_ulogic;
JTAGBUSY : out std_ulogic;
JTAGLOCKED : out std_ulogic;
JTAGMODIFIED : out std_ulogic;
OT : out std_ulogic;
CONVST : in std_ulogic;
CONVSTCLK : in std_ulogic;
DADDR : in std_logic_vector(6 downto 0);
DCLK : in std_ulogic;
DEN : in std_ulogic;
DI : in std_logic_vector(15 downto 0);
DWE : in std_ulogic;
RESET : in std_ulogic;
VAUXN : in std_logic_vector(15 downto 0);
VAUXP : in std_logic_vector(15 downto 0);
VN : in std_ulogic;
VP : in std_ulogic
);
end component;
component FDRSE
generic ( INIT : bit := '0');
port ( Q : out std_ulogic;
C : in std_ulogic;
CE : in std_ulogic;
D : in std_ulogic;
R : in std_ulogic;
S : in std_ulogic);
end component;
component FDR
generic ( INIT : bit := '0');
port ( Q : out std_ulogic;
C : in std_ulogic;
D : in std_ulogic;
R : in std_ulogic);
end component;
component FDRE
generic ( INIT : bit := '0');
port ( Q : out std_ulogic;
C : in std_ulogic;
CE : in std_ulogic;
D : in std_ulogic;
R : in std_ulogic);
end component;
component FD
generic ( INIT : bit := '0');
port ( Q : out std_ulogic;
C : in std_ulogic;
D : in std_ulogic);
end component;
component FDRS
generic ( INIT : bit := '0');
port ( Q : out std_ulogic;
C : in std_ulogic;
D : in std_ulogic;
R : in std_ulogic;
S : in std_ulogic);
end component;
component FDE
generic ( INIT : bit := '0');
port ( Q : out std_ulogic;
C : in std_ulogic;
CE : in std_ulogic;
D : in std_ulogic);
end component;
component MUXF5
port ( O : out std_ulogic;
I0 : in std_ulogic;
I1 : in std_ulogic;
S : in std_ulogic);
end component;
component VCC
port ( P : out std_ulogic := '1');
end component;
component GND
port ( G : out std_ulogic := '0');
end component;
component INV
port
(
O : out std_ulogic;
I : in std_ulogic
);
end component;
component LUT2_L
generic
(
INIT : bit_vector := X"0"
);
port
(
LO : out std_ulogic;
I0 : in std_ulogic;
I1 : in std_ulogic
);
end component;
component LUT4
generic
(
INIT : bit_vector := X"0000"
);
port
(
O : out std_ulogic;
I0 : in std_ulogic;
I1 : in std_ulogic;
I2 : in std_ulogic;
I3 : in std_ulogic
);
end component;
component LUT3
generic
(
INIT : bit_vector := X"00"
);
port
(
O : out std_ulogic;
I0 : in std_ulogic;
I1 : in std_ulogic;
I2 : in std_ulogic
);
end component;
component LUT2
generic
(
INIT : bit_vector := X"0"
);
port
(
O : out std_ulogic;
I0 : in std_ulogic;
I1 : in std_ulogic
);
end component;
component FDC
generic
(
INIT : bit := '0'
);
port
(
Q : out std_ulogic;
C : in std_ulogic;
CLR : in std_ulogic;
D : in std_ulogic
);
end component;
component LUT3_L
generic
(
INIT : bit_vector := X"00"
);
port
(
LO : out std_ulogic;
I0 : in std_ulogic;
I1 : in std_ulogic;
I2 : in std_ulogic
);
end component;
component LUT1
generic
(
INIT : bit_vector := X"0"
);
port
(
O : out std_ulogic;
I0 : in std_ulogic
);
end component;
component LUT4_L
generic
(
INIT : bit_vector := X"0000"
);
port
(
LO : out std_ulogic;
I0 : in std_ulogic;
I1 : in std_ulogic;
I2 : in std_ulogic;
I3 : in std_ulogic
);
end component;
component FDCE
generic
(
INIT : bit := '0'
);
port
(
Q : out std_ulogic;
C : in std_ulogic;
CE : in std_ulogic;
CLR : in std_ulogic;
D : in std_ulogic
);
end component;
component FDC_1
generic
(
INIT : bit := '0'
);
port
(
Q : out std_ulogic;
C : in std_ulogic;
CLR : in std_ulogic;
D : in std_ulogic
);
end component;
component FDP
generic
(
INIT : bit := '1'
);
port
(
Q : out std_ulogic;
C : in std_ulogic;
D : in std_ulogic;
PRE : in std_ulogic
);
end component;
component FDS
generic
(
INIT : bit := '1'
);
port
(
Q : out std_ulogic;
C : in std_ulogic;
D : in std_ulogic;
S : in std_ulogic
);
end component;
component MUXCY
port
(
O : out std_ulogic;
CI : in std_ulogic;
DI : in std_ulogic;
S : in std_ulogic
);
end component;
component LUT1_L
generic
(
INIT : bit_vector := X"0"
);
port
(
LO : out std_ulogic;
I0 : in std_ulogic
);
end component;
component MUXF6
port
(
O : out std_ulogic;
I0 : in std_ulogic;
I1 : in std_ulogic;
S : in std_ulogic
);
end component;
component MUXF5_D
port
(
LO : out std_ulogic;
O : out std_ulogic;
I0 : in std_ulogic;
I1 : in std_ulogic;
S : in std_ulogic
);
end component;
component XORCY
port
(
O : out std_ulogic;
CI : in std_ulogic;
LI : in std_ulogic
);
end component;
component MUXCY_L
port
(
LO : out std_ulogic;
CI : in std_ulogic;
DI : in std_ulogic;
S : in std_ulogic
);
end component;
component FDSE
generic
(
INIT : bit := '1'
);
port
(
Q : out std_ulogic;
C : in std_ulogic;
CE : in std_ulogic;
D : in std_ulogic;
S : in std_ulogic
);
end component;
component MULT_AND
port
(
LO : out std_ulogic;
I0 : in std_ulogic;
I1 : in std_ulogic
);
end component;
component SRL16E
generic
(
INIT : bit_vector := X"0000"
);
port
(
Q : out STD_ULOGIC;
A0 : in STD_ULOGIC;
A1 : in STD_ULOGIC;
A2 : in STD_ULOGIC;
A3 : in STD_ULOGIC;
CE : in STD_ULOGIC;
CLK : in STD_ULOGIC;
D : in STD_ULOGIC
);
end component;
component ROM256X1
generic
(
INIT : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"
);
port
(
O : out std_ulogic;
A0 : in std_ulogic;
A1 : in std_ulogic;
A2 : in std_ulogic;
A3 : in std_ulogic;
A4 : in std_ulogic;
A5 : in std_ulogic;
A6 : in std_ulogic;
A7 : in std_ulogic
);
end component;
component FDPE
generic
(
INIT : bit := '1'
);
port
(
Q : out std_ulogic;
C : in std_ulogic;
CE : in std_ulogic;
D : in std_ulogic;
PRE : in std_ulogic
);
end component;
component MULT18X18
port
(
P : out std_logic_vector (35 downto 0);
A : in std_logic_vector (17 downto 0);
B : in std_logic_vector (17 downto 0)
);
end component;
component MULT18X18S
port
(
P : out std_logic_vector (35 downto 0);
A : in std_logic_vector (17 downto 0);
B : in std_logic_vector (17 downto 0);
C : in std_ulogic;
CE : in std_ulogic;
R : in std_ulogic
);
end component;
component MUXF7
port
(
O : out std_ulogic;
I0 : in std_ulogic;
I1 : in std_ulogic;
S : in std_ulogic
);
end component;
component IODELAY
generic
(
DELAY_SRC : string := "I";
HIGH_PERFORMANCE_MODE : boolean := true;
IDELAY_TYPE : string := "DEFAULT";
IDELAY_VALUE : integer := 0;
ODELAY_VALUE : integer := 0;
REFCLK_FREQUENCY : real := 200.0;
SIGNAL_PATTERN : string := "DATA"
);
port
(
DATAOUT : out std_ulogic;
C : in std_ulogic;
CE : in std_ulogic;
DATAIN : in std_ulogic;
IDATAIN : in std_ulogic;
INC : in std_ulogic;
ODATAIN : in std_ulogic;
RST : in std_ulogic;
T : in std_ulogic
);
end component;
component ISERDES
generic
(
BITSLIP_ENABLE : boolean := false;
DATA_RATE : string := "DDR";
DATA_WIDTH : integer := 4;
INIT_Q1 : bit := '0';
INIT_Q2 : bit := '0';
INIT_Q3 : bit := '0';
INIT_Q4 : bit := '0';
INTERFACE_TYPE : string := "MEMORY";
IOBDELAY : string := "NONE";
IOBDELAY_TYPE : string := "DEFAULT";
IOBDELAY_VALUE : integer := 0;
NUM_CE : integer := 2;
SERDES_MODE : string := "MASTER";
SRVAL_Q1 : bit := '0';
SRVAL_Q2 : bit := '0';
SRVAL_Q3 : bit := '0';
SRVAL_Q4 : bit := '0'
);
port
(
O : out std_ulogic;
Q1 : out std_ulogic;
Q2 : out std_ulogic;
Q3 : out std_ulogic;
Q4 : out std_ulogic;
Q5 : out std_ulogic;
Q6 : out std_ulogic;
SHIFTOUT1 : out std_ulogic;
SHIFTOUT2 : out std_ulogic;
BITSLIP : in std_ulogic;
CE1 : in std_ulogic;
CE2 : in std_ulogic;
CLK : in std_ulogic;
CLKDIV : in std_ulogic;
D : in std_ulogic;
DLYCE : in std_ulogic;
DLYINC : in std_ulogic;
DLYRST : in std_ulogic;
OCLK : in std_ulogic;
REV : in std_ulogic;
SHIFTIN1 : in std_ulogic;
SHIFTIN2 : in std_ulogic;
SR : in std_ulogic
);
end component;
component RAM16X1S
generic
(
INIT : bit_vector(15 downto 0) := X"0000"
);
port
(
O : out std_ulogic;
A0 : in std_ulogic;
A1 : in std_ulogic;
A2 : in std_ulogic;
A3 : in std_ulogic;
D : in std_ulogic;
WCLK : in std_ulogic;
WE : in std_ulogic
);
end component;
component RAM16X1D
generic
(
INIT : bit_vector(15 downto 0) := X"0000"
);
port
(
DPO : out std_ulogic;
SPO : out std_ulogic;
A0 : in std_ulogic;
A1 : in std_ulogic;
A2 : in std_ulogic;
A3 : in std_ulogic;
D : in std_ulogic;
DPRA0 : in std_ulogic;
DPRA1 : in std_ulogic;
DPRA2 : in std_ulogic;
DPRA3 : in std_ulogic;
WCLK : in std_ulogic;
WE : in std_ulogic
);
end component;
component ROM32X1
generic
(
INIT : bit_vector := X"00000000"
);
port
(
O : out std_ulogic;
A0 : in std_ulogic;
A1 : in std_ulogic;
A2 : in std_ulogic;
A3 : in std_ulogic;
A4 : in std_ulogic
);
end component;
component DSP48
generic
(
AREG : integer := 1;
B_INPUT : string := "DIRECT";
BREG : integer := 1;
CARRYINREG : integer := 1;
CARRYINSELREG : integer := 1;
CREG : integer := 1;
LEGACY_MODE : string := "MULT18X18S";
MREG : integer := 1;
OPMODEREG : integer := 1;
PREG : integer := 1;
SUBTRACTREG : integer := 1
);
port
(
BCOUT : out std_logic_vector(17 downto 0);
P : out std_logic_vector(47 downto 0);
PCOUT : out std_logic_vector(47 downto 0);
A : in std_logic_vector(17 downto 0);
B : in std_logic_vector(17 downto 0);
BCIN : in std_logic_vector(17 downto 0);
C : in std_logic_vector(47 downto 0);
CARRYIN : in std_ulogic;
CARRYINSEL : in std_logic_vector(1 downto 0);
CEA : in std_ulogic;
CEB : in std_ulogic;
CEC : in std_ulogic;
CECARRYIN : in std_ulogic;
CECINSUB : in std_ulogic;
CECTRL : in std_ulogic;
CEM : in std_ulogic;
CEP : in std_ulogic;
CLK : in std_ulogic;
OPMODE : in std_logic_vector(6 downto 0);
PCIN : in std_logic_vector(47 downto 0);
RSTA : in std_ulogic;
RSTB : in std_ulogic;
RSTC : in std_ulogic;
RSTCARRYIN : in std_ulogic;
RSTCTRL : in std_ulogic;
RSTM : in std_ulogic;
RSTP : in std_ulogic;
SUBTRACT : in std_ulogic
);
end component;
component RAMB16
generic
(
DOA_REG : integer := 0;
DOB_REG : integer := 0;
INIT_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_08 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_09 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_10 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_11 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_12 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_13 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_14 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_15 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_16 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_17 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_18 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_19 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_20 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_21 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_22 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_23 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_24 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_25 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_26 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_27 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_28 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_29 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_30 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_31 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_32 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_33 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_34 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_35 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_36 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_37 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_38 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_39 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_A : bit_vector := X"000000000";
INIT_B : bit_vector := X"000000000";
INITP_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INVERT_CLK_DOA_REG : boolean := false;
INVERT_CLK_DOB_REG : boolean := false;
RAM_EXTENSION_A : string := "NONE";
RAM_EXTENSION_B : string := "NONE";
READ_WIDTH_A : integer := 0;
READ_WIDTH_B : integer := 0;
SIM_COLLISION_CHECK : string := "ALL";
SRVAL_A : bit_vector := X"000000000";
SRVAL_B : bit_vector := X"000000000";
WRITE_MODE_A : string := "WRITE_FIRST";
WRITE_MODE_B : string := "WRITE_FIRST";
WRITE_WIDTH_A : integer := 0;
WRITE_WIDTH_B : integer := 0
);
port
(
CASCADEOUTA : out std_ulogic;
CASCADEOUTB : out std_ulogic;
DOA : out std_logic_vector (31 downto 0);
DOB : out std_logic_vector (31 downto 0);
DOPA : out std_logic_vector (3 downto 0);
DOPB : out std_logic_vector (3 downto 0);
ADDRA : in std_logic_vector (14 downto 0);
ADDRB : in std_logic_vector (14 downto 0);
CASCADEINA : in std_ulogic;
CASCADEINB : in std_ulogic;
CLKA : in std_ulogic;
CLKB : in std_ulogic;
DIA : in std_logic_vector (31 downto 0);
DIB : in std_logic_vector (31 downto 0);
DIPA : in std_logic_vector (3 downto 0);
DIPB : in std_logic_vector (3 downto 0);
ENA : in std_ulogic;
ENB : in std_ulogic;
REGCEA : in std_ulogic;
REGCEB : in std_ulogic;
SSRA : in std_ulogic;
SSRB : in std_ulogic;
WEA : in std_logic_vector (3 downto 0);
WEB : in std_logic_vector (3 downto 0)
);
end component;
component MUXF8
port
(
O : out std_ulogic;
I0 : in std_ulogic;
I1 : in std_ulogic;
S : in std_ulogic
);
end component;
component RAM64X1D
generic ( INIT : bit_vector(63 downto 0) := X"0000000000000000");
port
(
DPO : out std_ulogic;
SPO : out std_ulogic;
A0 : in std_ulogic;
A1 : in std_ulogic;
A2 : in std_ulogic;
A3 : in std_ulogic;
A4 : in std_ulogic;
A5 : in std_ulogic;
D : in std_ulogic;
DPRA0 : in std_ulogic;
DPRA1 : in std_ulogic;
DPRA2 : in std_ulogic;
DPRA3 : in std_ulogic;
DPRA4 : in std_ulogic;
DPRA5 : in std_ulogic;
WCLK : in std_ulogic;
WE : in std_ulogic
);
end component;
component BUF
port
(
O : out std_ulogic;
I : in std_ulogic
);
end component;
component LUT5
generic
(
INIT : bit_vector := X"00000000"
);
port
(
O : out std_ulogic;
I0 : in std_ulogic;
I1 : in std_ulogic;
I2 : in std_ulogic;
I3 : in std_ulogic;
I4 : in std_ulogic
);
end component;
component LUT5_L
generic
(
INIT : bit_vector := X"00000000"
);
port
(
LO : out std_ulogic;
I0 : in std_ulogic;
I1 : in std_ulogic;
I2 : in std_ulogic;
I3 : in std_ulogic;
I4 : in std_ulogic
);
end component;
component LUT6
generic
(
INIT : bit_vector := X"0000000000000000"
);
port
(
O : out std_ulogic;
I0 : in std_ulogic;
I1 : in std_ulogic;
I2 : in std_ulogic;
I3 : in std_ulogic;
I4 : in std_ulogic;
I5 : in std_ulogic
);
end component;
component LUT6_L
generic
(
INIT : bit_vector := X"0000000000000000"
);
port
(
LO : out std_ulogic;
I0 : in std_ulogic;
I1 : in std_ulogic;
I2 : in std_ulogic;
I3 : in std_ulogic;
I4 : in std_ulogic;
I5 : in std_ulogic
);
end component;
component RAM128X1S
generic (
INIT : bit_vector(127 downto 0) := X"00000000000000000000000000000000"
);
port (
O : out std_ulogic;
A0 : in std_ulogic;
A1 : in std_ulogic;
A2 : in std_ulogic;
A3 : in std_ulogic;
A4 : in std_ulogic;
A5 : in std_ulogic;
A6 : in std_ulogic;
D : in std_ulogic;
WCLK : in std_ulogic;
WE : in std_ulogic
);
end component;
end;
| mit | dd184e4374d316f8d6b71c8173982828 | 0.76229 | 4.683833 | false | false | false | false |
michaelfivez/ascon_hardware_implementation | ascon128128_unrolled2/API_plus_CipherCore/CypherCore.vhd | 1 | 14,264 | -------------------------------------------------------------------------------
--! @project Unrolled (factor 2) hardware implementation of Asconv128128
--! @author Michael Fivez
--! @license This project is released under the GNU Public License.
--! The license and distribution terms for this file may be
--! found in the file LICENSE in this distribution or at
--! http://www.gnu.org/licenses/gpl-3.0.txt
--! @note This is an hardware implementation made for my graduation thesis
--! at the KULeuven, in the COSIC department (year 2015-2016)
--! The thesis is titled 'Energy efficient hardware implementations of CAESAR submissions',
--! and can be found on the COSIC website (www.esat.kuleuven.be/cosic/publications)
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.ALL;
use ieee.numeric_std.all;
entity CipherCore is
generic (
G_NPUB_SIZE : integer := 128; --! Npub size (bits)
G_NSEC_SIZE : integer := 128; --! Nsec size (bits)
G_DBLK_SIZE : integer := 128; --! Data Block size (bits)
G_KEY_SIZE : integer := 128; --! Key size (bits)
G_RDKEY_SIZE : integer := 128; --! Round Key size (bits)
G_TAG_SIZE : integer := 128; --! Tag size (bits)
G_BS_BYTES : integer := 4; --! The number of bits required to hold block size expressed in bytes = log2_ceil(max(G_ABLK_SIZE,G_DBLK_SIZE)/8)
G_CTR_AD_SIZE : integer := 64; --! Maximum size for the counter that keeps track of authenticated data
G_CTR_D_SIZE : integer := 64 --! Maximum size for the counter that keeps track of data
);
port (
clk : in std_logic;
rst : in std_logic;
npub : in std_logic_vector(G_NPUB_SIZE -1 downto 0);
nsec : in std_logic_vector(G_NSEC_SIZE -1 downto 0);
key : in std_logic_vector(G_KEY_SIZE -1 downto 0);
rdkey : in std_logic_vector(G_RDKEY_SIZE -1 downto 0);
bdi : in std_logic_vector(G_DBLK_SIZE -1 downto 0);
exp_tag : in std_logic_vector(G_TAG_SIZE -1 downto 0);
len_a : in std_logic_vector(G_CTR_AD_SIZE -1 downto 0);
len_d : in std_logic_vector(G_CTR_D_SIZE -1 downto 0);
key_ready : in std_logic;
key_updated : out std_logic;
key_needs_update : in std_logic;
rdkey_ready : in std_logic;
rdkey_read : out std_logic;
npub_ready : in std_logic;
npub_read : out std_logic;
nsec_ready : in std_logic;
nsec_read : out std_logic;
bdi_ready : in std_logic;
bdi_proc : in std_logic;
bdi_ad : in std_logic;
bdi_nsec : in std_logic;
bdi_pad : in std_logic;
bdi_decrypt : in std_logic;
bdi_eot : in std_logic;
bdi_eoi : in std_logic;
bdi_read : out std_logic;
bdi_size : in std_logic_vector(G_BS_BYTES -1 downto 0);
bdi_valid_bytes : in std_logic_vector(G_DBLK_SIZE/8 -1 downto 0);
bdi_pad_loc : in std_logic_vector(G_DBLK_SIZE/8 -1 downto 0);
bdi_nodata : in std_logic;
exp_tag_ready : in std_logic;
bdo_ready : in std_logic;
bdo_write : out std_logic;
bdo : out std_logic_vector(G_DBLK_SIZE -1 downto 0);
bdo_size : out std_logic_vector(G_BS_BYTES+1 -1 downto 0);
bdo_nsec : out std_logic;
tag_ready : in std_logic;
tag_write : out std_logic;
tag : out std_logic_vector(G_TAG_SIZE -1 downto 0);
msg_auth_done : out std_logic;
msg_auth_valid : out std_logic
);
end entity CipherCore;
architecture structure of CipherCore is
-- Registers
signal keyreg,npubreg : std_logic_vector(127 downto 0);
-- Control signals AsconCore
signal AsconStart : std_logic;
signal AsconMode : std_logic_vector(3 downto 0);
signal AsconBusy : std_logic;
signal AsconSize : std_logic_vector(3 downto 0);
signal AsconInput : std_logic_vector(127 downto 0);
-- Internal Datapath signals
signal AsconOutput : std_logic_vector(127 downto 0);
begin
-- Morus_core entity
AsconCore : entity work.Ascon_StateUpdate port map(clk,rst,AsconStart,AsconMode,AsconSize,npubreg,keyreg,AsconInput,AsconBusy,AsconOutput);
----------------------------------------
------ DataPath for CipherCore ---------
----------------------------------------
datapath: process(AsconOutput,exp_tag,bdi,AsconInput) is
begin
-- Connect signals to the MorusCore
AsconInput <= bdi;
tag <= AsconOutput;
bdo <= AsconOutput;
if AsconOutput = exp_tag then
msg_auth_valid <= '1';
else
msg_auth_valid <= '0';
end if;
end process datapath;
----------------------------------------
------ ControlPath for CipherCore ------
----------------------------------------
fsm: process(clk, rst) is
type state_type is (IDLE,INIT_1,INIT_2,PROCESSING,RUN_CIPHER_1,RUN_CIPHER_2,RUN_CIPHER_3,RUN_CIPHER_4,TAG_1,TAG_2);
variable CurrState : state_type := IDLE;
variable firstblock : std_logic;
variable lastblock : std_logic_vector(1 downto 0);
variable afterRunning : std_logic_vector(2 downto 0);
begin
if(clk = '1' and clk'event) then
if rst = '1' then -- synchornous reset
key_updated <= '0';
CurrState := IDLE;
firstblock := '0';
keyreg <= (others => '0');
npubreg <= (others => '0');
AsconMode <= (others => '0'); -- the mode is a register
afterRunning := (others => '0');
else
-- registers above in reset are used
-- Standard values of the control signals are zero
AsconStart <= '0';
bdi_read <= '0';
msg_auth_done <= '0';
bdo_write <= '0';
bdo_size <= "10000";
tag_write <= '0';
npub_read <= '0';
AsconSize <= (others => '0');
FsmLogic: case CurrState is
when IDLE =>
-- if key_needs_update = '1' then -- Key needs updating
-- if key_ready = '1' then
-- key_updated <= '1';
-- keyreg <= key;
-- CurrState := IDLE;
-- else
-- CurrState := IDLE;
-- end if;
if key_needs_update = '1' and key_ready = '1' then -- Key needs updating
key_updated <= '1';
keyreg <= key;
CurrState := IDLE;
elsif bdi_proc = '1' and npub_ready = '1' then -- start of processing
CurrState := INIT_1;
npubreg <= npub;
npub_read <= '1';
AsconMode <= "0010"; -- Mode: initialization
AsconStart <= '1';
else
CurrState := IDLE;
end if;
when INIT_1 =>
if AsconBusy = '1' then
CurrState := INIT_2; -- to INIT_2
else
AsconStart <= '1';
CurrState := INIT_1; -- to INIT_1
end if;
when INIT_2 =>
if AsconBusy = '0' then
CurrState := PROCESSING; -- to PROCESSING
firstblock := '1';
lastblock := "00";
else
CurrState := INIT_2; -- to INIT_2
end if;
-- EVEN SIMPLIFY THIS AFTER YOU SEE IF WORKS
when PROCESSING =>
if lastblock(1) = '1' then -- Generate the Tag
AsconMode <= "0001";
AsconStart <= '1';
CurrState := TAG_1;
elsif bdi_ready = '1' then
if firstblock = '1' and bdi_ad = '0' then -- No associative data (and return in function)
-- SEP_CONST
AsconMode <= "0011";
AsconStart <= '1';
CurrState := PROCESSING;
elsif bdi_ad = '1' then
if bdi_eot = '0' then
-- AD_PROCESS
AsconMode <= "0000";
AsconStart <= '1';
afterRunning := "000";
CurrState := RUN_CIPHER_1;
elsif bdi_eoi = '0' then
if bdi_size = "0000" then
-- AD_PROCESS + case2 + SEP_CONST
AsconMode <= "0000";
AsconStart <= '1';
afterRunning := "001";
CurrState := RUN_CIPHER_1;
else
-- AD_PROCESS + SEP_CONST
AsconMode <= "0000";
AsconStart <= '1';
afterRunning := "010";
CurrState := RUN_CIPHER_1;
end if;
else
if bdi_size = "0000" then
-- AD_PROCESS + case2 + SEP_CONST + case1
AsconMode <= "0000";
AsconStart <= '1';
afterRunning := "101";
CurrState := RUN_CIPHER_1;
else
-- AD_PROCESS + SEP_CONST + case1
AsconMode <= "0000";
AsconStart <= '1';
afterRunning := "110";
CurrState := RUN_CIPHER_1;
end if;
end if;
else
if bdi_decrypt = '0' then
if bdi_eot = '0' then
-- ENCRYPT
AsconMode <= "0110";
AsconStart <= '1';
afterRunning := "011";
CurrState := RUN_CIPHER_1;
elsif bdi_size = "0000" then
-- ENCRYPT + case1
AsconMode <= "0110";
AsconStart <= '1';
afterRunning := "100";
CurrState := RUN_CIPHER_1;
else
-- LAST_BLOCK_ENCRYPT
bdi_read <= '1';
AsconMode <= "0111";
AsconStart <= '1';
afterRunning := "011";
CurrState := RUN_CIPHER_4;
end if;
else
if bdi_eot = '0' then
-- DECRYPT
AsconMode <= "0100";
AsconStart <= '1';
afterRunning := "011";
CurrState := RUN_CIPHER_1;
elsif bdi_size = "0000" then
-- DECRYPT + case1
AsconMode <= "0100";
AsconStart <= '1';
afterRunning := "100";
CurrState := RUN_CIPHER_1;
else
-- LAST_BLOCK_DECRYPT
bdi_read <= '1';
AsconMode <= "0101";
AsconStart <= '1';
AsconSize <= bdi_size;
afterRunning := "011";
CurrState := RUN_CIPHER_4;
end if;
end if;
end if;
-- check if tag after (eoi, with special case when no associative data:
-- This is needed, because if no associative data, it will do it's thing and then still the message block is
-- left to be processed
if firstblock = '1' and bdi_ad = '0' then -- lastblock will be set next return in the function
lastblock := "00";
elsif bdi_eoi = '1' and bdi_decrypt = '0' then -- the one after is tag encryption
lastblock := "10";
elsif bdi_eoi = '1' then -- the one after is tag decryption
lastblock := "11";
end if;
-- not firstblock anymore :
firstblock := '0';
end if;
when RUN_CIPHER_1 =>
if AsconBusy = '1' then
CurrState := RUN_CIPHER_2;
bdi_read <= '1';
else
AsconStart <= '1';
CurrState := RUN_CIPHER_1;
end if;
when RUN_CIPHER_3 =>
if AsconBusy = '1' then
CurrState := RUN_CIPHER_2;
else
AsconStart <= '1';
CurrState := RUN_CIPHER_3;
end if;
when RUN_CIPHER_4 =>
if AsconBusy = '1' then
CurrState := RUN_CIPHER_2;
else
CurrState := RUN_CIPHER_4;
end if;
when RUN_CIPHER_2 =>
if AsconBusy = '0' then
-- logic here:
-- a simple variable is used for the cases where after the cipher something special has to be done:
-- activating authregister after associative data = 1
-- resetting of blocknumber after last associative data = 2 (so also do 1's job)
-- giving of output after encryption/decryption = 3 for encryption, 4 for decryption
-- activating checksum after decription of message = 4
-- special giving of output after padded encryption/decryption = 5 and 6 (determines output_sel), also wait with bdi_read
AfterRunLogic: case afterRunning is
when "000" => -- return to IDLE
CurrState := PROCESSING;
when "001" => -- case2 and sep_cont after
AsconMode <= "1001";
AsconStart <= '1';
CurrState := RUN_CIPHER_3;
afterRunning := "010";
when "010" => -- SEPCONSTANT and return to IDLE
AsconMode <= "0011";
AsconStart <= '1';
CurrState := PROCESSING;
when "011" => -- GIVE OUTPUT and return to IDLE
if bdo_ready = '1' then
bdo_write <= '1';
CurrState := PROCESSING;
else
CurrState := RUN_CIPHER_2;
end if;
when "100" => -- GIVE OUTPUT & case1 and return to IDLE
if bdo_ready = '1' then
bdo_write <= '1';
CurrState := PROCESSING;
AsconMode <= "1000";
AsconStart <= '1';
else
CurrState := RUN_CIPHER_2;
end if;
when "101" => -- case2 and case1 and sep_cont after
AsconMode <= "1001";
AsconStart <= '1';
CurrState := RUN_CIPHER_3;
afterRunning := "110";
when "110" => -- case1 and sep_cont after
AsconMode <= "1000";
AsconStart <= '1';
CurrState := RUN_CIPHER_2;
afterRunning := "010";
when others =>
end case AfterRunLogic;
else
CurrState := RUN_CIPHER_2;
end if;
when TAG_1 =>
if AsconBusy = '1' then
CurrState := TAG_2;
else
AsconStart <= '1';
CurrState := TAG_1;
end if;
when TAG_2 =>
if AsconBusy = '0' and lastblock(0) = '0' then -- Generate Tag
if tag_ready = '1' then
tag_write <= '1';
key_updated <= '0';
CurrState := IDLE;
else
CurrState := TAG_2;
end if;
elsif AsconBusy = '0' then -- Compare Tag
if exp_tag_ready = '1' then
msg_auth_done <= '1';
key_updated <= '0';
CurrState := IDLE;
else
CurrState := TAG_2;
end if;
else
CurrState := TAG_2;
end if;
when others =>
end case FsmLogic;
end if;
end if;
end process fsm;
end architecture structure;
| gpl-3.0 | 549a256a273ed876f5710d78778a12eb | 0.5197 | 3.39054 | false | false | false | false |
impedimentToProgress/UCI-BlueChip | AttackFiles/Attacks/privEsc/lib/gaisler/pci/dmactrl.vhd | 2 | 16,792 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: dmactrl
-- File: dmactrl.vhd
-- Author: Alf Vaerneus - Gaisler Research
-- Modified: Nils-Johan Wessman - Gaisler Research
-- Description: Simple DMA controller
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
library gaisler;
use gaisler.misc.all;
use gaisler.pci.all;
entity dmactrl is
generic (
hindex : integer := 0;
slvindex : integer := 0;
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#fff#;
blength : integer := 4
);
port (
rst : in std_logic;
clk : in std_logic;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
ahbmi : in ahb_mst_in_type;
ahbmo : out ahb_mst_out_type;
ahbsi0 : in ahb_slv_in_type;
ahbso0 : out ahb_slv_out_type;
ahbsi1 : out ahb_slv_in_type;
ahbso1 : in ahb_slv_out_type
);
end;
architecture rtl of dmactrl is
constant BURST_LENGTH : integer := blength;
constant REVISION : integer := 0;
constant pconfig : apb_config_type := (
0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_DMACTRL, 0, REVISION, 0),
1 => apb_iobar(paddr, pmask));
type state_type is(idle, read1, read2, read3, read4, read5, write1, write2, writeb, write3, write4, turn);
type rbuf_type is array (0 to 2) of std_logic_vector(31 downto 0);
type dmactrl_reg_type is record
state : state_type;
addr0 : std_logic_vector(31 downto 2);
addr1 : std_logic_vector(31 downto 2);
hmbsel : std_logic_vector(0 to NAHBAMR-1);
htrans : std_logic_vector(1 downto 0);
rbuf : rbuf_type;
write : std_logic;
start_req : std_logic;
start : std_logic;
ready : std_logic;
err : std_logic;
first0 : std_logic;
first1 : std_logic;
no_ws : std_logic; -- no wait states
blimit : std_logic; -- 1k limit
dmao_start: std_logic;
two_in_buf: std_logic; -- two words in rbuf to be stored
burstl_p : std_logic_vector(BURST_LENGTH - 1 downto 0); -- pci access counter
burstl_a : std_logic_vector(BURST_LENGTH - 1 downto 0); -- amba access counter
ahb0_htrans : std_logic_vector(1 downto 0);
ahb0_hready : std_logic;
ahb0_retry : std_logic;
ahb0_hsel : std_logic;
start_del : std_logic;
end record;
signal r,rin : dmactrl_reg_type;
signal dmai : ahb_dma_in_type;
signal dmao : ahb_dma_out_type;
begin
comb : process(rst,r,dmao,apbi,ahbsi0,ahbso1)
variable v : dmactrl_reg_type;
variable vdmai : ahb_dma_in_type;
variable pdata : std_logic_vector(31 downto 0);
variable slvbusy : ahb_slv_out_type;
variable dma_done, pci_done : std_logic;
variable bufloc : integer range 0 to 2;
begin
slvbusy := ahbso1; v := r;
vdmai.burst := '1'; vdmai.address := r.addr0 & "00";
vdmai.write := not r.write; vdmai.start := '0'; vdmai.size := "10";
vdmai.wdata := r.rbuf(0); pdata := (others => '0');
vdmai.busy := '0'; vdmai.irq := '0';
bufloc := 0;
v.start_del := r.start;
slvbusy.hready := '1'; slvbusy.hindex := hindex; --slvbusy.hresp := "00";
v.ahb0_htrans := ahbsi0.htrans; v.ahb0_retry := '0';
v.ahb0_hsel := ahbsi0.hsel(slvindex); v.ahb0_hready := ahbsi0.hready;
-- AMBA busy response when dma is running
if r.ahb0_retry = '1' then slvbusy.hresp := "10";
else slvbusy.hresp := "00"; end if;
if r.ahb0_htrans = "10" and (r.start = '1') and r.ahb0_hsel = '1' and r.ahb0_hready = '1' then
slvbusy.hready := '0';
slvbusy.hresp := "10";
v.ahb0_retry := '1';
end if;
-- Done signals
if (r.burstl_a(BURST_LENGTH - 1 downto 1) = zero32(BURST_LENGTH - 1 downto 1)) then -- AMBA access done
dma_done := '1'; else dma_done := '0'; end if;
if (r.burstl_p(BURST_LENGTH - 1 downto 1) = zero32(BURST_LENGTH - 1 downto 1)) then -- PCI access done
pci_done := '1'; else pci_done := '0'; end if;
-- APB interface
if (apbi.psel(pindex) and apbi.penable) = '1' then
case apbi.paddr(4 downto 2) is
when "000" =>
if apbi.pwrite = '1' then
v.start_req := apbi.pwdata(0);
v.write := apbi.pwdata(1);
v.ready := r.ready and not apbi.pwdata(2);
v.err := r.err and not apbi.pwdata(3);
v.hmbsel := apbi.pwdata(7 downto 4);
end if;
pdata := zero32(31 downto 8) & r.hmbsel & r.err & r.ready & r.write & r.start_req;
when "001" =>
if apbi.pwrite = '1' then v.addr0 := apbi.pwdata(31 downto 2); end if;
pdata := r.addr0 & "00";
when "010" =>
if apbi.pwrite = '1' then v.addr1 := apbi.pwdata(31 downto 2); end if;
pdata := r.addr1 & "00";
when "011" =>
if apbi.pwrite = '1' then
v.burstl_p := apbi.pwdata(BURST_LENGTH - 1 downto 0);
v.burstl_a := apbi.pwdata(BURST_LENGTH - 1 downto 0);
end if;
pdata := zero32(31 downto BURST_LENGTH) & r.burstl_p;
when others =>
end case;
end if;
-- can't start dma until AMBA slave is idle
if r.start_req = '1' and (ahbsi0.hready = '1' and (ahbsi0.htrans = "00" or ahbsi0.hsel(slvindex) = '0')) then
v.start := '1';
end if;
case r.state is
when idle =>
v.htrans := "00";
v.first0 := '1'; v.first1 := '1';
v.no_ws := '0'; v.dmao_start := '0'; v.blimit := '0';
if r.start = '1' then
if r.write = '0' then v.state := read1;
else v.state := write1; end if;
end if;
when read1 => -- Start PCI read
bufloc := 0;
v.htrans := "10";
if ahbso1.hready = '1' and ahbso1.hresp = HRESP_OKAY then
if r.htrans(1) = '1' then
if pci_done = '1' then
v.htrans := "00";
v.state := read5;
else
v.htrans := "11";
v.state := read2;
end if;
end if;
elsif ahbso1.hready = '0' then
v.htrans := "11";
else
v.htrans := "00";
end if;
when read2 => -- fill rbuf (3 words)
if r.first1 = '1' then bufloc := 1; -- store 3 words
else bufloc := 2; end if;
if ahbso1.hready = '1' and ahbso1.hresp = HRESP_OKAY then
if r.htrans = "11" then
v.first1 := '0';
if pci_done = '1' then
v.htrans := "00";
v.state := read5;
elsif r.first1 = '0' then
v.htrans := "01";
v.state := read3;
v.first0 := '1';
end if;
end if;
end if;
when read3 => -- write to AMBA and read from PCI
vdmai.start := '1';
bufloc := 1;
if (dmao.ready and dmao.start) = '1' then bufloc := 1; v.no_ws := '1'; -- no wait state on AMBA ?
else
bufloc := 2;
if dmao.active = '1' then v.no_ws := '0'; end if;
end if;
if dmao.active = '0' then v.blimit := '1';
else v.blimit := '0'; end if;
if dmao.ready = '1' then
v.first0 := '0';
v.htrans := "11";
else
v.htrans := "01";
end if;
if r.htrans(1) = '1' and ahbso1.hready = '1' and ahbso1.hresp = HRESP_OKAY and pci_done = '1' then
v.state := read5;
v.htrans := "00";
elsif r.htrans(1) = '1' and ahbso1.hready = '0' and ahbso1.hresp = HRESP_RETRY then
if dmao.active = '0' then v.two_in_buf := '1'; end if; -- two words in rbuf to store
v.state := read4;
v.htrans := "01";
end if;
when read4 => -- PCI retry
bufloc := 1;
if dmao.ready = '1' then v.two_in_buf := '0'; end if;
if dmao.start = '1' and r.two_in_buf = '0' then v.dmao_start := '1'; end if;
if r.no_ws = '1' and r.dmao_start = '1' then vdmai.start := '0';
elsif dmao.start = '1' and r.two_in_buf = '0' then v.no_ws := '1'; vdmai.start := '0';
else vdmai.start := '1'; end if;
--if dmao.ready = '1' and r.no_ws = '1' and r.two_in_buf = '0' then -- handle change of waitstates (sdram refresh)
if (dmao.ready = '1' or (dmao.active = '0' and r.dmao_start = '1')) and r.no_ws = '1' and r.two_in_buf = '0' then
v.first0 := '1';
v.first1 := '1';
v.no_ws := '0';
v.dmao_start := '0';
v.state := read1;
end if;
when read5 => -- PCI read done
if dmao.start = '1' then v.first0 := '0'; -- first amba access
elsif dmao.active = '0' then v.first0 := '1'; end if; -- 1k limit
if dma_done = '0' or (r.first0 = '1' and dmao.start = '0') then vdmai.start := '1'; end if;
if (dmao.ready and dmao.start) = '1' then bufloc := 1; v.no_ws := '1'; -- no wait state on AMBA ?
else bufloc := 2; end if;
if dmao.ready = '1' and dma_done = '1' then
v.state := turn;
end if;
when write1 => -- Read first from AMBA
bufloc := 0;
v.first1 := '1'; v.no_ws := '0';
if dmao.start = '1' then v.first0 := '0'; -- first amba access
elsif dmao.active = '0' then v.first0 := '1'; end if; -- 1k limit
if dma_done = '1' and (r.first0 = '0' or dmao.start = '1') then vdmai.start := '0';
else vdmai.start := '1'; end if;
if dmao.ready = '1' then
if dma_done = '1' then v.state := write4;
else v.state := write2; end if;
v.htrans := "10"; -- start access to PCI
end if;
when write2 => -- Read from AMBA and write to PCI
bufloc := 0;
if (dmao.ready and dmao.start) = '1' then v.no_ws := '1'; end if; -- no wait state on AMBA ?
if dmao.start = '1' then v.first0 := '0'; -- first amba access
elsif dmao.active = '0' then v.first0 := '1'; end if; -- 1k limit
if dmao.ready = '1' then -- Data ready write to PCI
v.htrans := "11";
if dma_done = '1' then
v.state := write4;
end if;
else v.htrans := "01"; end if;
if ahbso1.hready = '0' then
vdmai.start := '0';
if v.no_ws = '1' then bufloc := 1; end if;
if dmao.active = '0' then v.state := writeb; -- AMBA 1k limit
else v.state := write3; end if;
elsif dma_done = '0' or (r.first0 = '1' and dmao.start = '0') then
vdmai.start := '1';
end if;
when writeb => -- AMBA 1k limit and PCI retry
bufloc := 1;
if dmao.active = '1' then vdmai.start := '0';
else vdmai.start := '1'; end if;
if dmao.ready = '1' then v.state := write3; end if;
when write3 => -- Retry from PCI
bufloc := 1;
--if ahbso1.hready = '1' then v.htrans := "10"; -- wait for AMBA access to be done before retry
if (ahbso1.hready and (dmao.ready or not dmao.active)) = '1' then v.htrans := "10";
else v.htrans := "01"; end if;
if r.htrans(1) = '1' and ahbso1.hready = '1' and ahbso1.hresp = HRESP_OKAY then
if pci_done = '1' then
v.htrans := "00";
v.state := turn;
elsif dma_done = '1' and r.burstl_a(0) = '0' then
v.htrans := "01";
v.state := write4;
else
v.htrans := "11";
v.first0 := '1';
v.state := write2;
end if;
end if;
when write4 => -- Done read AMBA
v.htrans := "11";
if pci_done = '1' and ahbso1.hready = '1' and r.htrans(1) = '1' then
v.htrans := "00";
v.state := turn;
elsif ahbso1.hready = '0' then
v.state := write3;
v.htrans := "01";
end if;
when turn =>
v.htrans := "00";
-- can't switch off dma until AMBA slave is idle
if (ahbsi0.hsel(slvindex) = '0' and r.ahb0_retry = '0' and ahbsi0.hready = '1')
or (ahbsi0.htrans = "00" and ahbsi0.hready = '1') or r.ahb0_retry = '1' then
v.ready := '1'; v.first1 := '1'; v.start_req := '0';
v.start := '0'; v.state := idle;
end if;
end case;
if ((r.htrans(1) and ahbso1.hready) = '1' and ahbso1.hresp = HRESP_OKAY) then -- PCI access done
v.burstl_p := r.burstl_p - '1'; -- dec counter
v.addr1 := r.addr1 + '1'; -- inc address (PCI)
if (r.write = '0' or r.state = write4 or r.state = write3) then
if r.state /= read1 and r.state /= read2 and (v.no_ws = '1' or r.state = write3) and v.blimit = '0' then
v.rbuf(0) := r.rbuf(1); -- dont update if wait states
v.rbuf(1) := r.rbuf(2); --
end if;
if r.write = '0' then v.rbuf(bufloc) := ahbso1.hrdata; end if; -- PCI to AMBA
end if; -- if wait states store in buf(2) else
end if; -- in buf(1). Frist word in buf(0)
if dmao.ready = '1' then -- AMBA access done
v.burstl_a := r.burstl_a - '1'; -- dec counter
v.addr0 := r.addr0 + 1; -- inc address (AMBA master)
if r.write = '1' then
if r.state /= write3 and bufloc = 0 then -- dont update if retry from PCI
v.rbuf(0) := r.rbuf(1);
v.rbuf(1) := r.rbuf(2);
end if;
v.rbuf(bufloc) := dmao.rdata; -- AMBA to PCI
elsif r.write = '0' and (r.first0 = '1' or v.state = read4 or r.state = read5 or (v.no_ws = '0' or r.blimit = '1')) then
v.rbuf(0) := r.rbuf(1); -- update when data is written if wait states or PCI retry or PCI done
v.rbuf(1) := r.rbuf(2);
end if;
end if;
if (ahbso1.hresp = HRESP_ERROR or (dmao.mexc or dmao.retry) = '1') then
v.err := '1'; v.state := turn; v.htrans := HTRANS_IDLE;
end if;
--cancel dma
if r.start = '1' and r.start_req = '0' then
v.state := turn;
end if;
if rst = '0' then
v.state := idle;
v.start := '0';
v.start_req := '0';
v.write := '0';
v.err := '0';
v.ready := '0';
v.first1 := '1';
v.two_in_buf := '0';
v.hmbsel := (others => '0');
v.addr1 := (others => '0');
end if;
if r.start = '1' then -- new *** ???
ahbsi1.hsel <= (others => '1');
ahbsi1.hmbsel(0 to 3) <= r.hmbsel;
ahbsi1.hsize <= "010";
ahbsi1.hwrite <= r.write;
ahbsi1.htrans <= v.htrans;
-- ahbsi1.haddr <= r.addr1 & "00";
ahbsi1.haddr <= v.addr1 & "00";
ahbsi1.hburst <= "001";
ahbsi1.hwdata <= r.rbuf(0);
ahbsi1.hready <= ahbso1.hready;
ahbsi1.hmaster <= conv_std_logic_vector(hindex,4);
ahbso0 <= slvbusy;
else
ahbsi1.hsel <= ahbsi0.hsel;
ahbsi1.hmbsel(0 to 3) <= ahbsi0.hmbsel(0 to 3);
ahbsi1.hsize <= ahbsi0.hsize;
ahbsi1.hwrite <= ahbsi0.hwrite;
ahbsi1.htrans <= ahbsi0.htrans;
ahbsi1.haddr <= ahbsi0.haddr;
ahbsi1.hburst <= ahbsi0.hburst;
ahbsi1.hwdata <= ahbsi0.hwdata;
ahbsi1.hready <= ahbsi0.hready;
ahbsi1.hmaster <= ahbsi0.hmaster;
ahbso0 <= ahbso1;
v.state := idle;
end if;
dmai <= vdmai;
rin <= v;
apbo.pconfig <= pconfig;
apbo.prdata <= pdata;
apbo.pirq <= (others => '0');
apbo.pindex <= pindex;
ahbsi1.hirq <= (others => '0');
ahbsi1.hprot <= (others => '0');
ahbsi1.hmastlock <= '0';
ahbsi1.hcache <= '0';
end process;
cpur : process (clk)
begin
if rising_edge (clk) then
r <= rin;
end if;
end process;
ahbmst0 : pciahbmst generic map (hindex => hindex, devid => GAISLER_DMACTRL, incaddr => 1)
port map (rst, clk, dmai, dmao, ahbmi, ahbmo);
-- pragma translate_off
bootmsg : report_version
generic map ("dmactrl" & tost(pindex) &
": 32-bit DMA controller & AHB/AHB bridge rev " & tost(REVISION));
-- pragma translate_on
end;
| mit | 15ee766677342b8a4ffe3672a95d8e5e | 0.531086 | 3.217475 | false | false | false | false |
impedimentToProgress/UCI-BlueChip | AttackFiles/Attacks/privEsc/lib/gaisler/jtag/jtag.vhd | 2 | 3,199 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- package: jtag
-- File: jtag.vhd
-- Author: Edvin Catovic - Gaisler Research
-- Description: JTAG components
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
library techmap;
use techmap.gencomp.all;
package jtag is
constant JTAG_MANF_ID_GR : integer range 0 to 2047 := 804;
constant JTAG_IHP25RH1 : integer range 0 to 65535 := 16#251#;
constant JTAG_UT699RH : integer range 0 to 65535 := 16#699#;
component ahbjtag
generic (
tech : integer range 0 to NTECH := 0;
hindex : integer := 0;
nsync : integer range 1 to 2 := 1;
idcode : integer range 0 to 255 := 9;
manf : integer range 0 to 2047 := 804;
part : integer range 0 to 65535 := 0;
ver : integer range 0 to 15 := 0;
ainst : integer range 0 to 255 := 2;
dinst : integer range 0 to 255 := 3;
scantest : integer := 0);
port (
rst : in std_ulogic;
clk : in std_ulogic;
tck : in std_ulogic;
tms : in std_ulogic;
tdi : in std_ulogic;
tdo : out std_ulogic;
ahbi : in ahb_mst_in_type;
ahbo : out ahb_mst_out_type;
tapo_tck : out std_ulogic;
tapo_tdi : out std_ulogic;
tapo_inst : out std_logic_vector(7 downto 0);
tapo_rst : out std_ulogic;
tapo_capt : out std_ulogic;
tapo_shft : out std_ulogic;
tapo_upd : out std_ulogic;
tapi_tdo : in std_ulogic;
trst : in std_ulogic := '1';
tdoen : out std_ulogic
);
end component;
component ahbjtag_bsd
generic (
tech : integer range 0 to NTECH := 0;
hindex : integer := 0;
nsync : integer range 1 to 2 := 1;
ainst : integer range 0 to 255 := 2;
dinst : integer range 0 to 255 := 3);
port (
rst : in std_ulogic;
clk : in std_ulogic;
ahbi : in ahb_mst_in_type;
ahbo : out ahb_mst_out_type;
asel : in std_ulogic;
dsel : in std_ulogic;
tck : in std_ulogic;
regi : in std_ulogic;
shift : in std_ulogic;
rego : out std_ulogic
);
end component;
end;
| mit | e101558580a5704a6a5185be2f0c5037 | 0.568303 | 3.750293 | false | false | false | false |
impedimentToProgress/UCI-BlueChip | AttackFiles/Attacks/privEsc/lib/gaisler/ata/atactrl.vhd | 2 | 3,134 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: atactrl
-- File: atactrl.vhd
-- Author: Jiri Gaisler, Gaisler Research
-- Description: ATA controller
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
library gaisler;
use gaisler.ata.all;
entity atactrl is
generic (
tech : integer := 0;
fdepth : integer := 8;
mhindex : integer := 0;
shindex : integer := 0;
haddr : integer := 0;
hmask : integer := 16#ff0#;
pirq : integer := 0;
mwdma : integer := 0;
TWIDTH : natural := 8; -- counter width
-- PIO mode 0 settings (@100MHz clock)
PIO_mode0_T1 : natural := 6; -- 70ns
PIO_mode0_T2 : natural := 28; -- 290ns
PIO_mode0_T4 : natural := 2; -- 30ns
PIO_mode0_Teoc : natural := 23 -- 240ns ==> T0 - T1 - T2 = 600 - 70 - 290 = 240
);
port (
rst : in std_ulogic;
arst : in std_ulogic;
clk : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
ahbmi : in ahb_mst_in_type;
ahbmo : out ahb_mst_out_type;
cfo : out cf_out_type;
atai : in ata_in_type;
atao : out ata_out_type
);
end;
architecture rtl of atactrl is
begin
dmaen : if mwdma = 1 generate
x0 : entity work.atactrl_dma generic map (tech, fdepth, mhindex, shindex, haddr, hmask,
pirq, TWIDTH, PIO_mode0_T1, PIO_mode0_T2, PIO_mode0_T4, PIO_mode0_Teoc)
port map (rst, arst, clk, ahbsi, ahbso, ahbmi, ahbmo, cfo,
atai.ddi, atai.iordy, atai.intrq, atao.rstn, atao.ddo, atao.oen,
atao.da, atao.cs0, atao.cs1, atao.dior, atao.diow, atao.dmack, atai.dmarq);
end generate;
nodma : if mwdma /= 1 generate
x0 : entity work.atactrl_nodma generic map (shindex, haddr, hmask,
pirq, TWIDTH, PIO_mode0_T1, PIO_mode0_T2, PIO_mode0_T4, PIO_mode0_Teoc)
port map (rst, arst, clk, ahbsi, ahbso, cfo,
atai.ddi, atai.iordy, atai.intrq, atao.rstn, atao.ddo, atao.oen,
atao.da, atao.cs0, atao.cs1, atao.dior, atao.diow, atao.dmack);
ahbmo <= ahbm_none;
end generate;
end;
| mit | 60a9f01f114bdab6fa35f3550589daa4 | 0.589343 | 3.285115 | false | false | false | false |
impedimentToProgress/UCI-BlueChip | AttackFiles/Attacks/privEsc/lib/techmap/maps/syncfifo.vhd | 2 | 2,931 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: syncfifo
-- File: syncfifo.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: syncronous fifo using syncram_2p
------------------------------------------------------------------------------
library ieee;
library techmap;
use ieee.std_logic_1164.all;
use techmap.gencomp.all;
library grlib;
use grlib.stdlib.all;
entity syncfifo is
generic (tech : integer := 0; abits : integer := 6; dbits : integer := 8;
sepclk : integer := 0; wrfst : integer := 0);
port (
rst : in std_ulogic;
rclk : in std_ulogic;
renable : in std_ulogic;
dataout : out std_logic_vector((dbits -1) downto 0);
wclk : in std_ulogic;
write : in std_ulogic;
datain : in std_logic_vector((dbits -1) downto 0);
full : out std_ulogic;
empty : out std_ulogic
);
end;
architecture rtl of syncfifo is
type reg_type is record
raddr, waddr : std_logic_vector(abits downto 0);
full, empty, notempty : std_ulogic;
end record;
signal r, rin : reg_type;
begin
comb : process (rst, write, renable, r)
variable v : reg_type;
begin
v := r;
if renable = '1' then v.raddr := r.raddr + 1; end if;
if write = '1' then v.waddr := r.waddr + 1; end if;
if (v.raddr(abits-1) = v.waddr(abits-1)) then
if (v.raddr(abits) = v.waddr(abits)) then
v.full := '0'; v.empty := '1';
else v.full := '1'; v.empty := '0'; end if;
else v.full := '0'; v.empty := '0'; end if;
if rst = '0' then
v.raddr := (others => '0'); v.waddr := (others => '0');
v.full := '0'; v.empty := '1';
end if;
rin <= v;
end process;
full <= r.full; empty <= r.empty;
regs : process (rclk)
begin
if rising_edge(rclk) then
r <= rin;
end if;
end process;
x0 : syncram_2p generic map (tech, abits, dbits, sepclk)
port map (rclk, renable, r.raddr(abits-1 downto 0), dataout,
wclk, write, r.waddr(abits-1 downto 0), datain);
end;
| mit | d566705d951d73c40def9cf5b388c746 | 0.584783 | 3.578755 | false | false | false | false |
michaelfivez/ascon_hardware_implementation | ascon12864_unrolled6/Kernel/Fullround.vhd | 1 | 4,893 | -------------------------------------------------------------------------------
--! @project Unrolled (6) hardware implementation of Asconv1286
--! @author Michael Fivez
--! @license This project is released under the GNU Public License.
--! The license and distribution terms for this file may be
--! found in the file LICENSE in this distribution or at
--! http://www.gnu.org/licenses/gpl-3.0.txt
--! @note This is an hardware implementation made for my graduation thesis
--! at the KULeuven, in the COSIC department (year 2015-2016)
--! The thesis is titled 'Energy efficient hardware implementations of CAESAR submissions',
--! and can be found on the COSIC website (www.esat.kuleuven.be/cosic/publications)
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity Fullrounds is
port(
Reg0Out,Reg1Out,Reg2Out,Reg3Out,Reg4Out : in std_logic_vector(63 downto 0);
RoundNr : in std_logic;
RoundOut0,RoundOut1,RoundOut2,RoundOut3,RoundOut4 : out std_logic_vector(63 downto 0));
end entity Fullrounds;
architecture structural of Fullrounds is
signal RoundNr_0, RoundNr_1, RoundNr_2, RoundNr_3, RoundNr_4, RoundNr_5 : std_logic_vector(3 downto 0);
signal SboxOut0_0,SboxOut0_1,SboxOut0_2,SboxOut0_3,SboxOut0_4 : std_logic_vector(63 downto 0);
signal SboxOut1_0,SboxOut1_1,SboxOut1_2,SboxOut1_3,SboxOut1_4 : std_logic_vector(63 downto 0);
signal SboxOut2_0,SboxOut2_1,SboxOut2_2,SboxOut2_3,SboxOut2_4 : std_logic_vector(63 downto 0);
signal SboxOut3_0,SboxOut3_1,SboxOut3_2,SboxOut3_3,SboxOut3_4 : std_logic_vector(63 downto 0);
signal SboxOut4_0,SboxOut4_1,SboxOut4_2,SboxOut4_3,SboxOut4_4 : std_logic_vector(63 downto 0);
signal SboxOut5_0,SboxOut5_1,SboxOut5_2,SboxOut5_3,SboxOut5_4 : std_logic_vector(63 downto 0);
signal DiffOut0_0,DiffOut0_1,DiffOut0_2,DiffOut0_3,DiffOut0_4 : std_logic_vector(63 downto 0);
signal DiffOut1_0,DiffOut1_1,DiffOut1_2,DiffOut1_3,DiffOut1_4 : std_logic_vector(63 downto 0);
signal DiffOut2_0,DiffOut2_1,DiffOut2_2,DiffOut2_3,DiffOut2_4 : std_logic_vector(63 downto 0);
signal DiffOut3_0,DiffOut3_1,DiffOut3_2,DiffOut3_3,DiffOut3_4 : std_logic_vector(63 downto 0);
signal DiffOut4_0,DiffOut4_1,DiffOut4_2,DiffOut4_3,DiffOut4_4 : std_logic_vector(63 downto 0);
begin
-- declare and connect all sub entities
sbox1: entity work.Sbox port map(Reg0Out,Reg1Out,Reg2Out,Reg3Out,Reg4Out,RoundNr_0,
SboxOut0_0,SboxOut0_1,SboxOut0_2,SboxOut0_3,SboxOut0_4);
difflayer1: entity work.FullDiffusionLayer port map(SboxOut0_0,SboxOut0_1,SboxOut0_2,SboxOut0_3,SboxOut0_4,
DiffOut0_0,DiffOut0_1,DiffOut0_2,DiffOut0_3,DiffOut0_4);
sbox2: entity work.Sbox port map(DiffOut0_0,DiffOut0_1,DiffOut0_2,DiffOut0_3,DiffOut0_4,RoundNr_1,
SboxOut1_0,SboxOut1_1,SboxOut1_2,SboxOut1_3,SboxOut1_4);
difflayer2: entity work.FullDiffusionLayer port map(SboxOut1_0,SboxOut1_1,SboxOut1_2,SboxOut1_3,SboxOut1_4,
DiffOut1_0,DiffOut1_1,DiffOut1_2,DiffOut1_3,DiffOut1_4);
sbox3: entity work.Sbox port map(DiffOut1_0,DiffOut1_1,DiffOut1_2,DiffOut1_3,DiffOut1_4,RoundNr_2,
SboxOut2_0,SboxOut2_1,SboxOut2_2,SboxOut2_3,SboxOut2_4);
difflayer3: entity work.FullDiffusionLayer port map(SboxOut2_0,SboxOut2_1,SboxOut2_2,SboxOut2_3,SboxOut2_4,
DiffOut2_0,DiffOut2_1,DiffOut2_2,DiffOut2_3,DiffOut2_4);
sbox4: entity work.Sbox port map(DiffOut2_0,DiffOut2_1,DiffOut2_2,DiffOut2_3,DiffOut2_4,RoundNr_3,
SboxOut3_0,SboxOut3_1,SboxOut3_2,SboxOut3_3,SboxOut3_4);
difflayer4: entity work.FullDiffusionLayer port map(SboxOut3_0,SboxOut3_1,SboxOut3_2,SboxOut3_3,SboxOut3_4,
DiffOut3_0,DiffOut3_1,DiffOut3_2,DiffOut3_3,DiffOut3_4);
sbox5: entity work.Sbox port map(DiffOut3_0,DiffOut3_1,DiffOut3_2,DiffOut3_3,DiffOut3_4,RoundNr_4,
SboxOut4_0,SboxOut4_1,SboxOut4_2,SboxOut4_3,SboxOut4_4);
difflayer5: entity work.FullDiffusionLayer port map(SboxOut4_0,SboxOut4_1,SboxOut4_2,SboxOut4_3,SboxOut4_4,
DiffOut4_0,DiffOut4_1,DiffOut4_2,DiffOut4_3,DiffOut4_4);
sbox6: entity work.Sbox port map(DiffOut4_0,DiffOut4_1,DiffOut4_2,DiffOut4_3,DiffOut4_4,RoundNr_5,
SboxOut5_0,SboxOut5_1,SboxOut5_2,SboxOut5_3,SboxOut5_4);
difflayer6: entity work.FullDiffusionLayer port map(SboxOut5_0,SboxOut5_1,SboxOut5_2,SboxOut5_3,SboxOut5_4,
RoundOut0,RoundOut1,RoundOut2,RoundOut3,RoundOut4);
roundnrgen: process(RoundNr) is
begin
if RoundNr = '0' then
RoundNr_0 <= "0000";
RoundNr_1 <= "0001";
RoundNr_2 <= "0010";
RoundNr_3 <= "0011";
RoundNr_4 <= "0100";
RoundNr_5 <= "0101";
else
RoundNr_0 <= "0110";
RoundNr_1 <= "0111";
RoundNr_2 <= "1000";
RoundNr_3 <= "1001";
RoundNr_4 <= "1010";
RoundNr_5 <= "1011";
end if;
end process;
end architecture structural;
| gpl-3.0 | d9604f5f7f2b20f012556ea6c7e6a0ee | 0.707337 | 2.404423 | false | false | false | false |
impedimentToProgress/UCI-BlueChip | AttackFiles/Attacks/privEsc/lib/gaisler/usb/usbdcl.vhd | 2 | 3,839 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: usbdcl
-- File: usbdcl.vhd
-- Author: Andreas Hansen
-- Modified: Marko Isomaki
-- Description: USB Debug Communication Link
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.stdlib.all;
use grlib.amba.all;
use grlib.devices.all;
library gaisler;
use gaisler.misc.all;
use gaisler.usb.all;
library techmap;
use techmap.gencomp.all;
entity usbdcl is
generic (
hindex : integer := 0;
memtech : integer := DEFMEMTECH
);
port (
uclk : in std_ulogic;
usbi : in usb_in_type;
usbo : out usb_out_type;
hclk : in std_ulogic;
hrst : in std_ulogic;
ahbi : in ahb_mst_in_type;
ahbo : out ahb_mst_out_type
);
end;
architecture bhv of usbdcl is
constant REVISION : amba_version_type := 0;
constant memibits : integer := 11;
constant memobits : integer := 11;
signal iri : usb_memi_in_type;
signal ori : usb_memo_in_type;
signal oraddr : std_logic_vector(memobits-1 downto 0);
signal iraddr : std_logic_vector(memibits-1 downto 0);
signal ordata : std_logic_vector(31 downto 0);
signal irdata : std_logic_vector(31 downto 0);
signal vcc : std_ulogic;
signal dmai : ahb_dma_in_type;
signal dmao : ahb_dma_out_type;
component usbdclc is
port (
uclk : in std_ulogic;
usbi : in usb_in_type;
usbo : out usb_out_type;
hclk : in std_ulogic;
hrst : in std_ulogic;
iri : out usb_memi_in_type;
ori : out usb_memo_in_type;
dmai : out ahb_dma_in_type;
dmao : in ahb_dma_out_type;
oraddr : out std_logic_vector(10 downto 0);
iraddr : out std_logic_vector(10 downto 0);
ordata : in std_logic_vector(31 downto 0);
irdata : in std_logic_vector(31 downto 0)
);
end component;
begin
vcc <= '1';
u0 : usbdclc
port map ( uclk, usbi, usbo, hclk, hrst, iri,
ori, dmai, dmao, oraddr, iraddr, ordata, irdata);
inram : syncram_2p
generic map (memtech, memibits, 32, 1)
port map (
uclk, vcc, iraddr, irdata, hclk,
iri.wenable, iri.address, iri.din);
outram : syncram_2p
generic map (memtech, memobits, 32, 1)
port map (
hclk, vcc, oraddr, ordata, uclk,
ori.wenable, ori.address, ori.din);
ahbmst0 : ahbmst
generic map (incaddr => 0, hindex => hindex,
venid => VENDOR_GAISLER, devid => GAISLER_USBDCL)
port map (hrst, hclk, dmai, dmao, ahbi, ahbo);
-- pragma translate_off
bootmsg : report_version
generic map (
"grusb" & tost(hindex) & ": USB 2.0 DCL rev " & tost(REVISION)
& " " & tost(2**(memobits+2)) & " B Out Buffer " & tost(2**(memibits+2)) & " B In Buffer");
-- pragma translate_on
end;
| mit | e664fde02905b79e5f2aeac9aaf41dfa | 0.595468 | 3.477355 | false | false | false | false |
michaelfivez/ascon_hardware_implementation | ascon12864_unrolled6/API_plus_CipherCore/AEAD.vhd | 9 | 5,350 | -------------------------------------------------------------------------------
--! @file AEAD.vhd
--! @brief Top-level of authenticated encryption unit containing logic and memory region.
--! @project CAESAR Candidate Evaluation
--! @author Ekawat (ice) Homsirikamol
--! @copyright Copyright (c) 2015 Cryptographic Engineering Research Group
--! ECE Department, George Mason University Fairfax, VA, U.S.A.
--! All rights Reserved.
--! @license This project is released under the GNU Public License.
--! The license and distribution terms for this file may be
--! found in the file LICENSE in this distribution or at
--! http://www.gnu.org/licenses/gpl-3.0.txt
--! @note This is publicly available encryption source code that falls
--! under the License Exception TSU (Technology and software-
--! —unrestricted)
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.AEAD_pkg.all;
entity AEAD is
generic (
G_PWIDTH : integer := 32;
G_SWIDTH : integer := 32;
G_AUX_FIFO_CAPACITY : integer := 131072
);
port (
--! Global signals
clk : in std_logic;
rst : in std_logic;
--! Data in signals
pdi : in std_logic_vector(G_PWIDTH -1 downto 0);
pdi_valid : in std_logic;
pdi_ready : out std_logic;
--! Key signals
sdi : in std_logic_vector(G_SWIDTH -1 downto 0);
sdi_valid : in std_logic;
sdi_ready : out std_logic;
--! Data out signals
do : out std_logic_vector(G_PWIDTH -1 downto 0);
do_ready : in std_logic;
do_valid : out std_logic
);
end AEAD;
-------------------------------------------------------------------------------
--! @brief Architecture definition of crypto_template
-------------------------------------------------------------------------------
architecture structure of AEAD is
constant AUX_FIFO_DEPTH : integer := G_AUX_FIFO_CAPACITY/G_PWIDTH;
signal bypass_fifo_rd : std_logic;
signal bypass_fifo_wr : std_logic;
signal bypass_fifo_data : std_logic_vector(G_PWIDTH-1 downto 0);
signal bypass_fifo_full : std_logic;
signal bypass_fifo_empty : std_logic;
signal aux_fifo_din : std_logic_vector(G_PWIDTH-1 downto 0);
signal aux_fifo_dout : std_logic_vector(G_PWIDTH-1 downto 0);
signal aux_fifo_ctrl : std_logic_vector(3 downto 0);
signal aux_fifo_status : std_logic_vector(2 downto 0);
begin
u_logic:
entity work.AEAD_Core(structure)
generic map (
G_W => G_PWIDTH ,
G_SW => G_SWIDTH
)
port map (
clk => clk ,
rst => rst ,
pdi => pdi ,
pdi_valid => pdi_valid,
pdi_ready => pdi_ready,
sdi => sdi ,
sdi_valid => sdi_valid,
sdi_ready => sdi_ready,
do => do ,
do_ready => do_ready ,
do_valid => do_valid ,
--! FIFO signals
bypass_fifo_wr => bypass_fifo_wr,
bypass_fifo_rd => bypass_fifo_rd,
bypass_fifo_data => bypass_fifo_data,
bypass_fifo_full => bypass_fifo_full,
bypass_fifo_empty => bypass_fifo_empty,
aux_fifo_din => aux_fifo_din,
aux_fifo_dout => aux_fifo_dout,
aux_fifo_ctrl => aux_fifo_ctrl,
aux_fifo_status => aux_fifo_status
);
u_memory: block
begin
u_bypass_fifo:
entity work.fifo(structure)
generic map (G_W => G_PWIDTH, G_LOG2DEPTH => 6)
port map (
clk => clk ,
rst => rst ,
write => bypass_fifo_wr ,
read => bypass_fifo_rd ,
din => pdi ,
dout => bypass_fifo_data ,
almost_full => bypass_fifo_full ,
empty => bypass_fifo_empty
);
u_aux_fifo:
entity work.aux_fifo(structure)
generic map (G_W => G_PWIDTH, G_LOG2DEPTH => log2_ceil(AUX_FIFO_DEPTH))
port map (
clk => clk ,
rst => rst ,
fifo_din => aux_fifo_din ,
fifo_dout => aux_fifo_dout ,
fifo_ctrl_in => aux_fifo_ctrl ,
fifo_ctrl_out => aux_fifo_status
);
end block u_memory;
end structure; | gpl-3.0 | fb771f1dadb60375a340ba2314bbcf4d | 0.424458 | 4.490344 | false | false | false | false |
impedimentToProgress/UCI-BlueChip | AttackFiles/Attacks/privEsc/lib/gaisler/uart/apbuart.vhd | 2 | 16,821 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: uart
-- File: uart.vhd
-- Authors: Jiri Gaisler - Gaisler Research
-- Marko Isomaki - Gaisler Research
-- Description: Asynchronous UART. Implements 8-bit data frame with one stop-bit.
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
--use ieee.numeric_std.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
library gaisler;
use gaisler.uart.all;
--pragma translate_off
use std.textio.all;
--pragma translate_on
entity apbuart is
generic (
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#fff#;
console : integer := 0;
pirq : integer := 0;
parity : integer := 1;
flow : integer := 1;
fifosize : integer range 1 to 32 := 1;
abits : integer := 8);
port (
rst : in std_ulogic;
clk : in std_ulogic;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
uarti : in uart_in_type;
uarto : out uart_out_type);
end;
architecture rtl of apbuart is
constant REVISION : integer := 1;
constant pconfig : apb_config_type := (
0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_APBUART, 0, REVISION, pirq),
1 => apb_iobar(paddr, pmask));
type rxfsmtype is (idle, startbit, data, cparity, stopbit);
type txfsmtype is (idle, data, cparity, stopbit);
type fifo is array (0 to fifosize - 1) of std_logic_vector(7 downto 0);
type uartregs is record
rxen : std_ulogic; -- receiver enabled
txen : std_ulogic; -- transmitter enabled
rirqen : std_ulogic; -- receiver irq enable
tirqen : std_ulogic; -- transmitter irq enable
oen : std_ulogic; -- output enable
parsel : std_ulogic; -- parity select
paren : std_ulogic; -- parity select
flow : std_ulogic; -- flow control enable
loopb : std_ulogic; -- loop back mode enable
debug : std_ulogic; -- debug mode enable
rsempty : std_ulogic; -- receiver shift register empty (internal)
tsempty : std_ulogic; -- transmitter shift register empty
break : std_ulogic; -- break detected
ovf : std_ulogic; -- receiver overflow
parerr : std_ulogic; -- parity error
frame : std_ulogic; -- framing error
ctsn : std_logic_vector(1 downto 0); -- clear to send
rtsn : std_ulogic; -- request to send
extclken : std_ulogic; -- use external baud rate clock
extclk : std_ulogic; -- rising edge detect register
rhold : fifo;
rshift : std_logic_vector(7 downto 0);
tshift : std_logic_vector(10 downto 0);
thold : fifo;
irq : std_ulogic; -- tx/rx interrupt (internal)
tpar : std_ulogic; -- tx data parity (internal)
txstate : txfsmtype;
txclk : std_logic_vector(2 downto 0); -- tx clock divider
txtick : std_ulogic; -- tx clock (internal)
rxstate : rxfsmtype;
rxclk : std_logic_vector(2 downto 0); -- rx clock divider
rxdb : std_logic_vector(1 downto 0); -- rx delay
dpar : std_ulogic; -- rx data parity (internal)
rxtick : std_ulogic; -- rx clock (internal)
tick : std_ulogic; -- rx clock (internal)
scaler : std_logic_vector(11 downto 0);
brate : std_logic_vector(11 downto 0);
rxf : std_logic_vector(4 downto 0); -- rx data filtering buffer
txd : std_ulogic; -- transmitter data
rfifoirqen : std_ulogic; -- receiver fifo interrupt enable
tfifoirqen : std_ulogic; -- transmitter fifo interrupt enable
--fifo counters
rwaddr : std_logic_vector(log2x(fifosize) - 1 downto 0);
rraddr : std_logic_vector(log2x(fifosize) - 1 downto 0);
traddr : std_logic_vector(log2x(fifosize) - 1 downto 0);
twaddr : std_logic_vector(log2x(fifosize) - 1 downto 0);
rcnt : std_logic_vector(log2x(fifosize) downto 0);
tcnt : std_logic_vector(log2x(fifosize) downto 0);
end record;
constant rcntzero : std_logic_vector(log2x(fifosize) downto 0) := (others => '0');
signal r, rin : uartregs;
begin
uartop : process(rst, r, apbi, uarti )
variable rdata : std_logic_vector(31 downto 0);
variable scaler : std_logic_vector(11 downto 0);
variable rxclk, txclk : std_logic_vector(2 downto 0);
variable rxd, ctsn : std_ulogic;
variable irq : std_logic_vector(NAHBIRQ-1 downto 0);
variable paddr : std_logic_vector(7 downto 2);
variable v : uartregs;
variable thalffull : std_ulogic;
variable rhalffull : std_ulogic;
variable rfull : std_ulogic;
variable tfull : std_ulogic;
variable dready : std_ulogic;
variable thempty : std_ulogic;
--pragma translate_off
variable L1 : line;
variable CH : character;
variable FIRST : boolean := true;
variable pt : time := 0 ns;
--pragma translate_on
begin
v := r; irq := (others => '0'); irq(pirq) := r.irq;
v.irq := '0'; v.txtick := '0'; v.rxtick := '0'; v.tick := '0';
rdata := (others => '0'); v.rxdb(1) := r.rxdb(0);
dready := '0'; thempty := '1'; thalffull := '1'; rhalffull := '0';
v.ctsn := r.ctsn(0) & uarti.ctsn;
if fifosize = 1 then
dready := r.rcnt(0); rfull := dready; tfull := r.tcnt(0);
thempty := not tfull;
else
tfull := r.tcnt(log2x(fifosize)); rfull := r.rcnt(log2x(fifosize));
if (r.rcnt(log2x(fifosize)) or r.rcnt(log2x(fifosize) - 1)) = '1' then
rhalffull := '1';
end if;
if ((r.tcnt(log2x(fifosize)) or r.tcnt(log2x(fifosize) - 1))) = '1' then
thalffull := '0';
end if;
if r.rcnt /= rcntzero then dready := '1'; end if;
if r.tcnt /= rcntzero then thempty := '0'; end if;
end if;
-- scaler
scaler := r.scaler - 1;
if (r.rxen or r.txen) = '1' then
v.scaler := scaler;
v.tick := scaler(11) and not r.scaler(11);
if v.tick = '1' then v.scaler := r.brate; end if;
end if;
-- optional external uart clock
v.extclk := uarti.extclk;
if r.extclken = '1' then v.tick := r.extclk and not uarti.extclk; end if;
-- read/write registers
if (apbi.psel(pindex) and apbi.penable and (not apbi.pwrite)) = '1' then
case paddr(7 downto 2) is
when "000000" =>
rdata(7 downto 0) := r.rhold(conv_integer(r.rraddr));
if fifosize = 1 then v.rcnt(0) := '0';
else
if r.rcnt /= rcntzero then
v.rraddr := r.rraddr + 1; v.rcnt := r.rcnt - 1;
end if;
end if;
when "000001" =>
if fifosize /= 1 then
rdata (26 + log2x(fifosize) downto 26) := r.rcnt;
rdata (20 + log2x(fifosize) downto 20) := r.tcnt;
rdata (10 downto 7) := rfull & tfull & rhalffull & thalffull;
end if;
rdata(6 downto 0) := r.frame & r.parerr & r.ovf &
r.break & thempty & r.tsempty & dready;
--pragma translate_off
if CONSOLE = 1 then rdata(2 downto 1) := "11"; end if;
--pragma translate_on
when "000010" =>
if fifosize > 1 then
rdata(31) := '1';
end if;
rdata(12) := r.oen;
rdata(11) := r.debug;
if fifosize /= 1 then
rdata(10 downto 9) := r.rfifoirqen & r.tfifoirqen;
end if;
rdata(8 downto 0) := r.extclken & r.loopb &
r.flow & r.paren & r.parsel & r.tirqen & r.rirqen & r.txen & r.rxen;
when "000011" =>
rdata(11 downto 0) := r.brate;
when "000100" =>
-- Read TX FIFO.
if r.debug = '1' and r.tcnt /= rcntzero then
rdata(7 downto 0) := r.thold(conv_integer(r.traddr));
if fifosize = 1 then
v.tcnt(0) := '0';
else
v.traddr := r.traddr + 1;
v.tcnt := r.tcnt - 1;
end if;
end if;
when others =>
null;
end case;
end if;
paddr := "000000"; paddr(abits-1 downto 2) := apbi.paddr(abits-1 downto 2);
if (apbi.psel(pindex) and apbi.penable and apbi.pwrite) = '1' then
case paddr(7 downto 2) is
when "000000" =>
when "000001" =>
v.frame := apbi.pwdata(6);
v.parerr := apbi.pwdata(5);
v.ovf := apbi.pwdata(4);
v.break := apbi.pwdata(3);
when "000010" =>
v.oen := apbi.pwdata(12);
v.debug := apbi.pwdata(11);
if fifosize /= 1 then
v.rfifoirqen := apbi.pwdata(10);
v.tfifoirqen := apbi.pwdata(9);
end if;
v.extclken := apbi.pwdata(8);
v.loopb := apbi.pwdata(7);
v.flow := apbi.pwdata(6);
v.paren := apbi.pwdata(5);
v.parsel := apbi.pwdata(4);
v.tirqen := apbi.pwdata(3);
v.rirqen := apbi.pwdata(2);
v.txen := apbi.pwdata(1);
v.rxen := apbi.pwdata(0);
when "000011" =>
v.brate := apbi.pwdata(11 downto 0);
v.scaler := apbi.pwdata(11 downto 0);
when "000100" =>
-- Write RX fifo and generate irq
if flow /= 0 then
v.rhold(conv_integer(r.rwaddr)) := apbi.pwdata(7 downto 0);
if fifosize = 1 then v.rcnt(0) := '1';
else v.rwaddr := r.rwaddr + 1; v.rcnt := v.rcnt + 1; end if;
if r.debug = '1' then
v.irq := v.irq or r.rirqen;
end if;
end if;
when others =>
null;
end case;
end if;
-- tx clock
txclk := r.txclk + 1;
if r.tick = '1' then
v.txclk := txclk;
v.txtick := r.txclk(2) and not txclk(2);
end if;
-- rx clock
rxclk := r.rxclk + 1;
if r.tick = '1' then
v.rxclk := rxclk;
v.rxtick := r.rxclk(2) and not rxclk(2);
end if;
-- filter rx data
-- v.rxf := r.rxf(6 downto 0) & uarti.rxd;
-- if ((r.rxf(7) & r.rxf(7) & r.rxf(7) & r.rxf(7) & r.rxf(7) & r.rxf(7) &
-- r.rxf(7)) = r.rxf(6 downto 0))
-- then v.rxdb(0) := r.rxf(7); end if;
v.rxf(1 downto 0) := r.rxf(0) & uarti.rxd; -- meta-stability filter
if r.tick = '1' then
v.rxf(4 downto 2) := r.rxf(3 downto 1);
end if;
v.rxdb(0) := (r.rxf(4) and r.rxf(3)) or (r.rxf(4) and r.rxf(2)) or
(r.rxf(3) and r.rxf(2));
-- loop-back mode
if r.loopb = '1' then
v.rxdb(0) := r.tshift(0); ctsn := dready and not r.rsempty;
elsif (flow = 1) then ctsn := r.ctsn(1); else ctsn := '0'; end if;
rxd := r.rxdb(0);
-- transmitter operation
case r.txstate is
when idle => -- idle state
if (r.txtick = '1') then v.tsempty := '1'; end if;
if ((not r.debug and r.txen and (not thempty) and r.txtick) and
((not ctsn) or not r.flow)) = '1' then
v.txstate := data;
v.tpar := r.parsel; v.tsempty := '0';
v.txclk := "00" & r.tick; v.txtick := '0';
v.tshift := "10" & r.thold(conv_integer(r.traddr)) & '0';
if fifosize = 1 then
v.irq := r.irq or r.tirqen; v.tcnt(0) := '0';
else
v.traddr := r.traddr + 1;
v.tcnt := r.tcnt - 1;
end if;
end if;
when data => -- transmit data frame
if r.txtick = '1' then
v.tpar := r.tpar xor r.tshift(1);
v.tshift := '1' & r.tshift(10 downto 1);
if r.tshift(10 downto 1) = "1111111110" then
if r.paren = '1' then
v.tshift(0) := r.tpar; v.txstate := cparity;
else
v.tshift(0) := '1'; v.txstate := stopbit;
end if;
end if;
end if;
when cparity => -- transmit parity bit
if r.txtick = '1' then
v.tshift := '1' & r.tshift(10 downto 1); v.txstate := stopbit;
end if;
when stopbit => -- transmit stop bit
if r.txtick = '1' then
v.tshift := '1' & r.tshift(10 downto 1); v.txstate := idle;
end if;
end case;
-- writing of tx data register must be done after tx fsm to get correct
-- operation of thempty flag
if (apbi.psel(pindex) and apbi.penable and apbi.pwrite) = '1' then
case paddr(4 downto 2) is
when "000" =>
if fifosize = 1 then
v.thold(0) := apbi.pwdata(7 downto 0); v.tcnt(0) := '1';
else
v.thold(conv_integer(r.twaddr)) := apbi.pwdata(7 downto 0);
if not (tfull = '1') then
v.twaddr := r.twaddr + 1; v.tcnt := v.tcnt + 1;
end if;
end if;
--pragma translate_off
if CONSOLE = 1 then
if first then L1:= new string'(""); first := false; end if; --'
if apbi.penable'event then --'
CH := character'val(conv_integer(apbi.pwdata(7 downto 0))); --'
if CH = CR then
std.textio.writeline(OUTPUT, L1);
elsif CH /= LF then
std.textio.write(L1,CH);
end if;
pt := now;
end if;
end if;
--pragma translate_on
when others => null;
end case;
end if;
-- receiver operation
case r.rxstate is
when idle => -- wait for start bit
if ((r.rsempty = '0') and not (rfull = '1')) then
v.rsempty := '1';
v.rhold(conv_integer(r.rwaddr)) := r.rshift;
if fifosize = 1 then v.rcnt(0) := '1';
else v.rwaddr := r.rwaddr + 1; v.rcnt := v.rcnt + 1; end if;
end if;
if (r.rxen and r.rxdb(1) and (not rxd)) = '1' then
v.rxstate := startbit; v.rshift := (others => '1'); v.rxclk := "100";
if v.rsempty = '0' then v.ovf := '1'; end if;
v.rsempty := '0'; v.rxtick := '0';
end if;
when startbit => -- check validity of start bit
if r.rxtick = '1' then
if rxd = '0' then
v.rshift := rxd & r.rshift(7 downto 1); v.rxstate := data;
v.dpar := r.parsel;
else
v.rxstate := idle;
end if;
end if;
when data => -- receive data frame
if r.rxtick = '1' then
v.dpar := r.dpar xor rxd;
v.rshift := rxd & r.rshift(7 downto 1);
if r.rshift(0) = '0' then
if r.paren = '1' then v.rxstate := cparity;
else v.rxstate := stopbit; v.dpar := '0'; end if;
end if;
end if;
when cparity => -- receive parity bit
if r.rxtick = '1' then
v.dpar := r.dpar xor rxd; v.rxstate := stopbit;
end if;
when stopbit => -- receive stop bit
if r.rxtick = '1' then
v.irq := v.irq or r.rirqen; -- make sure no tx irqs are lost !
if rxd = '1' then
v.parerr := r.parerr or r.dpar; v.rsempty := r.dpar;
if not (rfull = '1') and (r.dpar = '0') then
v.rsempty := '1';
v.rhold(conv_integer(r.rwaddr)) := r.rshift;
if fifosize = 1 then v.rcnt(0) := '1';
else v.rwaddr := r.rwaddr + 1; v.rcnt := v.rcnt + 1; end if;
end if;
else
if r.rshift = "00000000" then v.break := '1';
else v.frame := '1'; end if;
v.rsempty := '1';
end if;
v.rxstate := idle;
end if;
end case;
if r.rxtick = '1' then
v.rtsn := (rfull and not r.rsempty) or r.loopb;
end if;
v.txd := r.tshift(0) or r.loopb or r.debug;
if fifosize /= 1 then
if thempty = '0' and v.tcnt = rcntzero then
v.irq := v.irq or r.tirqen;
end if;
v.irq := v.irq or (r.tfifoirqen and r.txen and thalffull);
v.irq := v.irq or (r.rfifoirqen and r.rxen and rhalffull);
end if;
-- reset operation
if rst = '0' then
v.frame := '0'; v.rsempty := '1';
v.parerr := '0'; v.ovf := '0'; v.break := '0';
v.tsempty := '1'; v.txen := '0'; v.rxen := '0';
v.txstate := idle; v.rxstate := idle; v.tshift(0) := '1';
v.extclken := '0'; v.rtsn := '1'; v.flow := '0';
v.txclk := (others => '0'); v.rxclk := (others => '0');
v.rcnt := (others => '0'); v.tcnt := (others => '0');
v.rwaddr := (others => '0'); v.twaddr := (others => '0');
v.rraddr := (others => '0'); v.traddr := (others => '0');
end if;
-- update registers
rin <= v;
-- drive outputs
uarto.txd <= r.txd; uarto.rtsn <= r.rtsn;
uarto.scaler <= "000000" & r.scaler;
uarto.txen <= r.oen; uarto.rxen <= r.rxen;
apbo.prdata <= rdata; apbo.pirq <= irq;
apbo.pindex <= pindex;
uarto.txen <= r.txen; uarto.rxen <= r.rxen;
end process;
apbo.pconfig <= pconfig;
regs : process(clk)
begin if rising_edge(clk) then r <= rin; end if; end process;
-- pragma translate_off
bootmsg : report_version
generic map ("apbuart" & tost(pindex) &
": Generic UART rev " & tost(REVISION) & ", fifo " & tost(fifosize) &
", irq " & tost(pirq));
-- pragma translate_on
end;
| mit | 2e52aecebaff88d4ddb312ebf0d5f376 | 0.566316 | 3.117309 | false | false | false | false |
impedimentToProgress/UCI-BlueChip | AttackFiles/Attacks/privEsc/lib/esa/pci/pciarb.vhd | 2 | 4,503 | ------------------------------------------------------------------------------
-- Entity: esa_pciarb
-- File: esa_pciarb.vhd
-- Author: Marko Isomaki
-- Description: GRLIB wrapper for the ESA PCI arbiter
------------------------------------------------------------------------------
library ieee;
library grlib;
library gaisler;
library esa;
library techmap;
use ieee.std_logic_1164.all;
use grlib.stdlib.all;
use grlib.amba.all;
use grlib.devices.all;
use techmap.gencomp.all;
use esa.pci_arb_pkg.all;
--pragma translate_off
use std.textio.all;
--pragma translate_on
entity pciarb is
generic(
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#FFF#;
nb_agents : integer := 4;
apb_en : integer := 1;
netlist : integer := 0);
port(
clk : in std_ulogic;
rst_n : in std_ulogic;
req_n : in std_logic_vector(0 to nb_agents-1);
frame_n : in std_logic;
gnt_n : out std_logic_vector(0 to nb_agents-1);
pclk : in std_ulogic;
prst_n : in std_ulogic;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type
);
end entity;
architecture rtl of pciarb is
component pci_arb is
generic(
NB_AGENTS : integer := 4;
ARB_SIZE : integer := 2;
APB_EN : integer := 1
);
port(
clk : in clk_type; -- clock
rst_n : in std_logic; -- async reset active low
req_n : in std_logic_vector(0 to NB_AGENTS-1); -- bus request
frame_n : in std_logic;
gnt_n : out std_logic_vector(0 to NB_AGENTS-1); -- bus grant
pclk : in clk_type; -- APB clock
prst_n : in std_logic; -- APB reset
pbi : in EAPB_Slv_In_Type; -- APB inputs
pbo : out EAPB_Slv_Out_Type -- APB outputs
);
end component;
component pci_arb_net is
generic (
nb_agents : integer := 4;
arb_size : integer := 2;
apb_en : integer := 1
);
port (
clk : in std_logic; -- clock
rst_n : in std_logic; -- async reset active low
req_n : in std_logic_vector(0 to NB_AGENTS-1); -- bus request
frame_n : in std_logic;
gnt_n : out std_logic_vector(0 to NB_AGENTS-1); -- bus grant
pclk : in std_logic; -- APB clock
prst_n : in std_logic; -- APB reset
pbi_psel : in std_ulogic; -- slave select
pbi_penable: in std_ulogic; -- strobe
pbi_paddr : in std_logic_vector(31 downto 0); -- address bus (byte)
pbi_pwrite : in std_ulogic; -- write
pbi_pwdata : in std_logic_vector(31 downto 0); -- write data bus
pbo_prdata : out std_logic_vector(31 downto 0) -- read data bus
);
end component;
signal pbi : eapb_slv_in_type;
signal pbo : eapb_slv_out_type;
constant REVISION : integer := 0;
constant pconfig : apb_config_type := (
0 => ahb_device_reg ( VENDOR_ESA, ESA_PCIARB, 0, REVISION, 0),
1 => apb_iobar(paddr, pmask));
begin
rtl0 : if netlist = 0 generate
arb : pci_arb
generic map(
NB_AGENTS => nb_agents, ARB_SIZE => log2(nb_agents), APB_EN => apb_en)
port map(
clk => clk, rst_n => rst_n, req_n => req_n, frame_n => frame_n,
gnt_n => gnt_n, pclk => pclk, prst_n => prst_n, pbi => pbi, pbo => pbo);
end generate;
net0 : if netlist /= 0 generate
arb : pci_arb_net
generic map(
NB_AGENTS => nb_agents, ARB_SIZE => log2(nb_agents), APB_EN => apb_en)
port map(
clk => clk, rst_n => rst_n, req_n => req_n, frame_n => frame_n,
gnt_n => gnt_n, pclk => pclk, prst_n => prst_n,
pbi_psel => pbi.psel,
pbi_penable => pbi.penable,
pbi_paddr => pbi.paddr,
pbi_pwrite => pbi.pwrite,
pbi_pwdata => pbi.pwdata,
pbo_prdata => pbo.prdata);
end generate;
apbo.prdata <= pbo.prdata;
apbo.pindex <= pindex;
apbo.pconfig <= pconfig;
apbo.pirq <= (others => '0');
pbi.psel <= apbi.psel(pindex);
pbi.penable <= apbi.penable;
pbi.paddr <= apbi.paddr;
pbi.pwrite <= apbi.pwrite;
pbi.pwdata <= apbi.pwdata;
-- boot message
-- pragma translate_off
bootmsg : report_version
generic map ("pciarb" & tost(pindex) &
": PCI arbiter, " & tost(nb_agents) & " masters");
-- pragma translate_on
end architecture;
| mit | 63fdb78677082343fb78461ced42e9e9 | 0.529425 | 3.367988 | false | false | false | false |
impedimentToProgress/UCI-BlueChip | AttackFiles/Attacks/privEsc/lib/tech/umc18/components/umc_simprims.vhd | 2 | 17,376 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Package: umc_simprims
-- File: umc_simprims.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: Simple UMC 0.18 simulation models
------------------------------------------------------------------------------
-- pragma translate_off
-- input pad
library ieee;
use ieee.std_logic_1164.all;
entity ICMT3V is port( A : in std_logic; Z : out std_logic); end ;
architecture behav of ICMT3V is begin Z <= to_X01(A) after 1 ns; end;
-- input pad with pull-up
library ieee;
use ieee.std_logic_1164.all;
entity ICMT3VPU is port( A : in std_logic; Z : out std_logic); end ;
architecture behav of ICMT3VPU is begin
Z <= to_X01(A) after 1 ns; --A <= 'H';
end;
-- input pad with pull-down
library ieee;
use ieee.std_logic_1164.all;
entity ICMT3VPD is port( A : in std_logic; Z : out std_logic); end ;
architecture behav of ICMT3VPD is begin
Z <= to_X01(A) after 1 ns; --A <= 'L';
end;
-- schmitt input pad
library ieee;
use ieee.std_logic_1164.all;
entity ISTRT3V is port( A : in std_logic; Z : out std_logic); end ;
architecture behav of ISTRT3V is begin Z <= to_X01(A) after 1 ns; end;
-- output pads
library ieee;
use ieee.std_logic_1164.all;
entity OCM3V4 is port( Z : out std_logic; A : in std_logic); end;
architecture behav of OCM3V4 is begin Z <= to_X01(A) after 3 ns; end;
library ieee;
use ieee.std_logic_1164.all;
entity OCM3V12 is port( Z : out std_logic; A : in std_logic); end;
architecture behav of OCM3V12 is begin Z <= to_X01(A) after 2 ns; end;
library ieee;
use ieee.std_logic_1164.all;
entity OCM3V24 is port( Z : out std_logic; A : in std_logic); end;
architecture behav of OCM3V24 is begin Z <= to_X01(A) after 1 ns; end;
-- tri-state output pads
library ieee;
use ieee.std_logic_1164.all;
entity OCMTR4 is port( EN : in std_logic; A : in std_logic; Z : out std_logic); end;
architecture behav of OCMTR4 is begin
Z <= to_X01(A) after 3 ns when to_X01(en) = '1' else
'Z' after 3 ns when to_X01(en) = '0' else 'X' after 3 ns;
end;
library ieee;
use ieee.std_logic_1164.all;
entity OCMTR12 is port( EN : in std_logic; A : in std_logic; Z : out std_logic); end;
architecture behav of OCMTR12 is begin
Z <= to_X01(A) after 2 ns when to_X01(en) = '1' else
'Z' after 2 ns when to_X01(en) = '0' else 'X' after 2 ns;
end;
library ieee;
use ieee.std_logic_1164.all;
entity OCMTR24 is port( EN : in std_logic; A : in std_logic; Z : out std_logic); end;
architecture behav of OCMTR24 is begin
Z <= to_X01(A) after 1 ns when to_X01(en) = '1' else
'Z' after 1 ns when to_X01(en) = '0' else 'X' after 1 ns;
end;
-- bidirectional pads
library ieee;
use ieee.std_logic_1164.all;
entity BICM3V4 is port( IO : inout std_logic; EN : in std_logic; A : in std_logic; Z : out std_logic); end;
architecture behav of BICM3V4 is begin
IO <= to_X01(A) after 3 ns when to_X01(en) = '1' else
'Z' after 3 ns when to_X01(en) = '0' else 'X' after 3 ns;
Z <= to_X01(IO) after 1 ns;
end;
library ieee;
use ieee.std_logic_1164.all;
entity BICM3V12 is port( IO : inout std_logic; EN : in std_logic; A : in std_logic; Z : out std_logic); end;
architecture behav of BICM3V12 is begin
IO <= to_X01(A) after 2 ns when to_X01(en) = '1' else
'Z' after 2 ns when to_X01(en) = '0' else 'X' after 2 ns;
Z <= to_X01(IO) after 1 ns;
end;
library ieee;
use ieee.std_logic_1164.all;
entity BICM3V24 is port( IO : inout std_logic; EN : in std_logic; A : in std_logic; Z : out std_logic); end;
architecture behav of BICM3V24 is begin
IO <= to_X01(A) after 1 ns when to_X01(en) = '1' else
'Z' after 1 ns when to_X01(en) = '0' else 'X' after 1 ns;
Z <= to_X01(IO) after 1 ns;
end;
library ieee;
use ieee.std_logic_1164.all;
entity LVDS_Receiver is port( A, AN : in std_logic; Z : out std_logic); end;
architecture struct of LVDS_Receiver is
signal yn : std_ulogic := '0';
begin
yn <= to_X01(A) after 1 ns when to_x01(A xor AN) = '1' else yn after 1 ns;
Z <= yn;
end;
library ieee;
use ieee.std_logic_1164.all;
entity LVDS_Driver is port (A, Vref, HI : in std_logic; Z, ZN : out std_logic ); end;
architecture struct of LVDS_Driver is begin
Z <= A after 1 ns;
ZN <= not A after 1 ns;
end;
library ieee;
use ieee.std_logic_1164.all;
entity LVDS_Biasmodule is port ( RefR : in std_logic; Vref, HI : out std_logic); end;
architecture struct of LVDS_Biasmodule is begin end;
-- single-port memory
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.stdlib.all;
entity UMC_SIM_SRAM is
generic (abits, dbits : integer := 8);
port (
a : in std_logic_vector(abits-1 downto 0);
data : in std_logic_vector(dbits-1 downto 0);
csn : in std_logic;
wen : in std_logic;
oen : in std_logic;
q : out std_logic_vector(dbits-1 downto 0);
clk : in std_logic
);
end;
architecture behav of UMC_SIM_SRAM is
subtype memword is std_logic_vector(dbits-1 downto 0);
type mem_type is array (0 to 2**abits-1) of memword;
signal qint : memword;
begin
m : process(clk)
variable mem : mem_type;
begin
if rising_edge(clk) then
qint <= (others => 'X');
if to_X01(wen) = '0' then mem(conv_integer(a)) := data;
elsif to_X01(wen) = '1' then qint <= mem(conv_integer(a)); end if;
end if;
end process;
q <= qint when to_X01(oen) = '0' else
(others => 'Z') when to_X01(oen) = '1' else (others => 'X');
end;
library ieee;
use ieee.std_logic_1164.all;
entity SRAM_2048wx32b is
port (
a : in std_logic_vector(10 downto 0);
data : in std_logic_vector(31 downto 0);
csn : in std_logic;
wen : in std_logic;
oen : in std_logic;
q : out std_logic_vector(31 downto 0);
clk : in std_logic
);
end;
architecture behav of SRAM_2048wx32b is
component UMC_SIM_SRAM is
generic (abits, dbits : integer := 8);
port (
a : in std_logic_vector(abits-1 downto 0);
data : in std_logic_vector(dbits-1 downto 0);
csn : in std_logic;
wen : in std_logic;
oen : in std_logic;
q : out std_logic_vector(dbits-1 downto 0);
clk : in std_logic
);
end component;
begin
m : UMC_SIM_SRAM generic map (11, 32) port map (a, data, csn, wen, oen, q, clk);
end;
library ieee;
use ieee.std_logic_1164.all;
entity SRAM_1024wx32b is
port (
a : in std_logic_vector(9 downto 0);
data : in std_logic_vector(31 downto 0);
csn : in std_logic;
wen : in std_logic;
oen : in std_logic;
q : out std_logic_vector(31 downto 0);
clk : in std_logic
);
end;
architecture behav of SRAM_1024wx32b is
component UMC_SIM_SRAM is
generic (abits, dbits : integer := 8);
port (
a : in std_logic_vector(abits-1 downto 0);
data : in std_logic_vector(dbits-1 downto 0);
csn : in std_logic;
wen : in std_logic;
oen : in std_logic;
q : out std_logic_vector(dbits-1 downto 0);
clk : in std_logic
);
end component;
begin
m : UMC_SIM_SRAM generic map (10, 32) port map (a, data, csn, wen, oen, q, clk);
end;
library ieee;
use ieee.std_logic_1164.all;
entity SRAM_512wx32b is
port (
a : in std_logic_vector(8 downto 0);
data : in std_logic_vector(31 downto 0);
csn : in std_logic;
wen : in std_logic;
oen : in std_logic;
q : out std_logic_vector(31 downto 0);
clk : in std_logic
);
end;
architecture behav of SRAM_512wx32b is
component UMC_SIM_SRAM is
generic (abits, dbits : integer := 8);
port (
a : in std_logic_vector(abits-1 downto 0);
data : in std_logic_vector(dbits-1 downto 0);
csn : in std_logic;
wen : in std_logic;
oen : in std_logic;
q : out std_logic_vector(dbits-1 downto 0);
clk : in std_logic
);
end component;
begin
m : UMC_SIM_SRAM generic map (9, 32) port map (a, data, csn, wen, oen, q, clk);
end;
library ieee;
use ieee.std_logic_1164.all;
entity SRAM_256wx32b is
port (
a : in std_logic_vector(7 downto 0);
data : in std_logic_vector(31 downto 0);
csn : in std_logic;
wen : in std_logic;
oen : in std_logic;
q : out std_logic_vector(31 downto 0);
clk : in std_logic
);
end;
architecture behav of SRAM_256wx32b is
component UMC_SIM_SRAM is
generic (abits, dbits : integer := 8);
port (
a : in std_logic_vector(abits-1 downto 0);
data : in std_logic_vector(dbits-1 downto 0);
csn : in std_logic;
wen : in std_logic;
oen : in std_logic;
q : out std_logic_vector(dbits-1 downto 0);
clk : in std_logic
);
end component;
begin
m : UMC_SIM_SRAM generic map (8, 32) port map (a, data, csn, wen, oen, q, clk);
end;
library ieee;
use ieee.std_logic_1164.all;
entity SRAM_128wx32b is
port (
a : in std_logic_vector(6 downto 0);
data : in std_logic_vector(31 downto 0);
csn : in std_logic;
wen : in std_logic;
oen : in std_logic;
q : out std_logic_vector(31 downto 0);
clk : in std_logic
);
end;
architecture behav of SRAM_128wx32b is
component UMC_SIM_SRAM is
generic (abits, dbits : integer := 8);
port (
a : in std_logic_vector(abits-1 downto 0);
data : in std_logic_vector(dbits-1 downto 0);
csn : in std_logic;
wen : in std_logic;
oen : in std_logic;
q : out std_logic_vector(dbits-1 downto 0);
clk : in std_logic
);
end component;
begin
m : UMC_SIM_SRAM generic map (7, 32) port map (a, data, csn, wen, oen, q, clk);
end;
library ieee;
use ieee.std_logic_1164.all;
entity SRAM_64wx32b is
port (
a : in std_logic_vector(5 downto 0);
data : in std_logic_vector(31 downto 0);
csn : in std_logic;
wen : in std_logic;
oen : in std_logic;
q : out std_logic_vector(31 downto 0);
clk : in std_logic
);
end;
architecture behav of SRAM_64wx32b is
component UMC_SIM_SRAM is
generic (abits, dbits : integer := 8);
port (
a : in std_logic_vector(abits-1 downto 0);
data : in std_logic_vector(dbits-1 downto 0);
csn : in std_logic;
wen : in std_logic;
oen : in std_logic;
q : out std_logic_vector(dbits-1 downto 0);
clk : in std_logic
);
end component;
begin
m : UMC_SIM_SRAM generic map (6, 32) port map (a, data, csn, wen, oen, q, clk);
end;
library ieee;
use ieee.std_logic_1164.all;
entity SRAM_32wx32b is
port (
a : in std_logic_vector(4 downto 0);
data : in std_logic_vector(31 downto 0);
csn : in std_logic;
wen : in std_logic;
oen : in std_logic;
q : out std_logic_vector(31 downto 0);
clk : in std_logic
);
end;
architecture behav of SRAM_32wx32b is
component UMC_SIM_SRAM is
generic (abits, dbits : integer := 8);
port (
a : in std_logic_vector(abits-1 downto 0);
data : in std_logic_vector(dbits-1 downto 0);
csn : in std_logic;
wen : in std_logic;
oen : in std_logic;
q : out std_logic_vector(dbits-1 downto 0);
clk : in std_logic
);
end component;
begin
m : UMC_SIM_SRAM generic map (5, 32) port map (a, data, csn, wen, oen, q, clk);
end;
library ieee;
use ieee.std_logic_1164.all;
entity SRAM_2048wx40b is
port (
a : in std_logic_vector(10 downto 0);
data : in std_logic_vector(39 downto 0);
csn : in std_logic;
wen : in std_logic;
oen : in std_logic;
q : out std_logic_vector(39 downto 0);
clk : in std_logic
);
end;
architecture behav of SRAM_2048wx40b is
component UMC_SIM_SRAM is
generic (abits, dbits : integer := 8);
port (
a : in std_logic_vector(abits-1 downto 0);
data : in std_logic_vector(dbits-1 downto 0);
csn : in std_logic;
wen : in std_logic;
oen : in std_logic;
q : out std_logic_vector(dbits-1 downto 0);
clk : in std_logic
);
end component;
begin
m : UMC_SIM_SRAM generic map (11, 40) port map (a, data, csn, wen, oen, q, clk);
end;
library ieee;
use ieee.std_logic_1164.all;
entity SRAM_1024wx40b is
port (
a : in std_logic_vector(9 downto 0);
data : in std_logic_vector(39 downto 0);
csn : in std_logic;
wen : in std_logic;
oen : in std_logic;
q : out std_logic_vector(39 downto 0);
clk : in std_logic
);
end;
architecture behav of SRAM_1024wx40b is
component UMC_SIM_SRAM is
generic (abits, dbits : integer := 8);
port (
a : in std_logic_vector(abits-1 downto 0);
data : in std_logic_vector(dbits-1 downto 0);
csn : in std_logic;
wen : in std_logic;
oen : in std_logic;
q : out std_logic_vector(dbits-1 downto 0);
clk : in std_logic
);
end component;
begin
m : UMC_SIM_SRAM generic map (10, 40) port map (a, data, csn, wen, oen, q, clk);
end;
library ieee;
use ieee.std_logic_1164.all;
entity SRAM_512wx40b is
port (
a : in std_logic_vector(8 downto 0);
data : in std_logic_vector(39 downto 0);
csn : in std_logic;
wen : in std_logic;
oen : in std_logic;
q : out std_logic_vector(39 downto 0);
clk : in std_logic
);
end;
architecture behav of SRAM_512wx40b is
component UMC_SIM_SRAM is
generic (abits, dbits : integer := 8);
port (
a : in std_logic_vector(abits-1 downto 0);
data : in std_logic_vector(dbits-1 downto 0);
csn : in std_logic;
wen : in std_logic;
oen : in std_logic;
q : out std_logic_vector(dbits-1 downto 0);
clk : in std_logic
);
end component;
begin
m : UMC_SIM_SRAM generic map (9, 40) port map (a, data, csn, wen, oen, q, clk);
end;
library ieee;
use ieee.std_logic_1164.all;
entity SRAM_256wx40b is
port (
a : in std_logic_vector(7 downto 0);
data : in std_logic_vector(39 downto 0);
csn : in std_logic;
wen : in std_logic;
oen : in std_logic;
q : out std_logic_vector(39 downto 0);
clk : in std_logic
);
end;
architecture behav of SRAM_256wx40b is
component UMC_SIM_SRAM is
generic (abits, dbits : integer := 8);
port (
a : in std_logic_vector(abits-1 downto 0);
data : in std_logic_vector(dbits-1 downto 0);
csn : in std_logic;
wen : in std_logic;
oen : in std_logic;
q : out std_logic_vector(dbits-1 downto 0);
clk : in std_logic
);
end component;
begin
m : UMC_SIM_SRAM generic map (8, 40) port map (a, data, csn, wen, oen, q, clk);
end;
library ieee;
use ieee.std_logic_1164.all;
entity SRAM_128wx40b is
port (
a : in std_logic_vector(6 downto 0);
data : in std_logic_vector(39 downto 0);
csn : in std_logic;
wen : in std_logic;
oen : in std_logic;
q : out std_logic_vector(39 downto 0);
clk : in std_logic
);
end;
architecture behav of SRAM_128wx40b is
component UMC_SIM_SRAM is
generic (abits, dbits : integer := 8);
port (
a : in std_logic_vector(abits-1 downto 0);
data : in std_logic_vector(dbits-1 downto 0);
csn : in std_logic;
wen : in std_logic;
oen : in std_logic;
q : out std_logic_vector(dbits-1 downto 0);
clk : in std_logic
);
end component;
begin
m : UMC_SIM_SRAM generic map (7, 40) port map (a, data, csn, wen, oen, q, clk);
end;
library ieee;
use ieee.std_logic_1164.all;
entity SRAM_64wx40b is
port (
a : in std_logic_vector(5 downto 0);
data : in std_logic_vector(39 downto 0);
csn : in std_logic;
wen : in std_logic;
oen : in std_logic;
q : out std_logic_vector(39 downto 0);
clk : in std_logic
);
end;
architecture behav of SRAM_64wx40b is
component UMC_SIM_SRAM is
generic (abits, dbits : integer := 8);
port (
a : in std_logic_vector(abits-1 downto 0);
data : in std_logic_vector(dbits-1 downto 0);
csn : in std_logic;
wen : in std_logic;
oen : in std_logic;
q : out std_logic_vector(dbits-1 downto 0);
clk : in std_logic
);
end component;
begin
m : UMC_SIM_SRAM generic map (6, 40) port map (a, data, csn, wen, oen, q, clk);
end;
library ieee;
use ieee.std_logic_1164.all;
entity SRAM_32wx40b is
port (
a : in std_logic_vector(4 downto 0);
data : in std_logic_vector(39 downto 0);
csn : in std_logic;
wen : in std_logic;
oen : in std_logic;
q : out std_logic_vector(39 downto 0);
clk : in std_logic
);
end;
architecture behav of SRAM_32wx40b is
component UMC_SIM_SRAM is
generic (abits, dbits : integer := 8);
port (
a : in std_logic_vector(abits-1 downto 0);
data : in std_logic_vector(dbits-1 downto 0);
csn : in std_logic;
wen : in std_logic;
oen : in std_logic;
q : out std_logic_vector(dbits-1 downto 0);
clk : in std_logic
);
end component;
begin
m : UMC_SIM_SRAM generic map (5, 40) port map (a, data, csn, wen, oen, q, clk);
end;
-- pragma translate_on
| mit | 51f37bf1763bea35b3a99c75b2e214d6 | 0.632251 | 2.728643 | false | false | false | false |
impedimentToProgress/UCI-BlueChip | AttackFiles/Attacks/privEsc/lib/gaisler/pci/pci.vhd | 2 | 12,537 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: pci
-- File: pci.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: Package with component and type declarations for PCI cores
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
library techmap;
use techmap.gencomp.all;
library gaisler;
use gaisler.misc.all;
package pci is
type pci_in_type is record
rst : std_ulogic;
gnt : std_ulogic;
idsel : std_ulogic;
ad : std_logic_vector(31 downto 0);
cbe : std_logic_vector(3 downto 0);
frame : std_ulogic;
irdy : std_ulogic;
trdy : std_ulogic;
devsel : std_ulogic;
stop : std_ulogic;
lock : std_ulogic;
perr : std_ulogic;
serr : std_ulogic;
par : std_ulogic;
host : std_ulogic;
pci66 : std_ulogic;
pme_status : std_ulogic;
int : std_logic_vector(3 downto 0); -- D downto A
end record;
type pci_out_type is record
aden : std_ulogic;
vaden : std_logic_vector(31 downto 0);
cbeen : std_logic_vector(3 downto 0);
frameen : std_ulogic;
irdyen : std_ulogic;
trdyen : std_ulogic;
devselen : std_ulogic;
stopen : std_ulogic;
ctrlen : std_ulogic;
perren : std_ulogic;
paren : std_ulogic;
reqen : std_ulogic;
locken : std_ulogic;
serren : std_ulogic;
inten : std_ulogic;
req : std_ulogic;
ad : std_logic_vector(31 downto 0);
cbe : std_logic_vector(3 downto 0);
frame : std_ulogic;
irdy : std_ulogic;
trdy : std_ulogic;
devsel : std_ulogic;
stop : std_ulogic;
perr : std_ulogic;
serr : std_ulogic;
par : std_ulogic;
lock : std_ulogic;
power_state : std_logic_vector(1 downto 0);
pme_enable : std_ulogic;
pme_clear : std_ulogic;
int : std_ulogic;
end record;
component pci_target
generic (
hindex : integer := 0;
abits : integer := 21;
device_id : integer := 0; -- PCI device ID
vendor_id : integer := 0; -- PCI vendor ID
nsync : integer range 1 to 2 := 1; -- 1 or 2 sync regs between clocks
oepol : integer := 0
);
port(
rst : in std_ulogic;
clk : in std_ulogic;
pciclk : in std_ulogic;
pcii : in pci_in_type;
pcio : out pci_out_type;
ahbmi : in ahb_mst_in_type;
ahbmo : out ahb_mst_out_type
);
end component;
component pci_mt
generic (
hmstndx : integer := 0;
abits : integer := 21;
device_id : integer := 0; -- PCI device ID
vendor_id : integer := 0; -- PCI vendor ID
master : integer := 1; -- Enable PCI Master
hslvndx : integer := 0;
haddr : integer := 16#F00#;
hmask : integer := 16#F00#;
ioaddr : integer := 16#000#;
nsync : integer range 1 to 2 := 1; -- 1 or 2 sync regs between clocks
oepol : integer := 0
);
port(
rst : in std_logic;
clk : in std_logic;
pciclk : in std_logic;
pcii : in pci_in_type;
pcio : out pci_out_type;
ahbmi : in ahb_mst_in_type;
ahbmo : out ahb_mst_out_type;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type
);
end component;
component dmactrl
generic (
hindex : integer := 0;
slvindex : integer := 0;
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#fff#;
blength : integer := 4);
port (
rst : in std_logic;
clk : in std_logic;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
ahbmi : in ahb_mst_in_type;
ahbmo : out ahb_mst_out_type;
ahbsi0 : in ahb_slv_in_type;
ahbso0 : out ahb_slv_out_type;
ahbsi1 : out ahb_slv_in_type;
ahbso1 : in ahb_slv_out_type);
end component;
component pci_mtf
generic (
memtech : integer := DEFMEMTECH;
hmstndx : integer := 0;
dmamst : integer := NAHBMST;
readpref : integer := 0;
abits : integer := 21;
dmaabits : integer := 26;
fifodepth : integer := 3; -- FIFO depth
device_id : integer := 0; -- PCI device ID
vendor_id : integer := 0; -- PCI vendor ID
master : integer := 1; -- Enable PCI Master
hslvndx : integer := 0;
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#fff#;
haddr : integer := 16#F00#;
hmask : integer := 16#F00#;
ioaddr : integer := 16#000#;
irq : integer := 0;
irqmask : integer := 0;
nsync : integer range 1 to 2 := 2; -- 1 or 2 sync regs between clocks
oepol : integer := 0;
endian : integer := 0;
class_code: integer := 16#0B4000#;
rev : integer := 0;
scanen : integer := 0;
syncrst : integer := 0);
port(
rst : in std_logic;
clk : in std_logic;
pciclk : in std_logic;
pcii : in pci_in_type;
pcio : out pci_out_type;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
ahbmi : in ahb_mst_in_type;
ahbmo : out ahb_mst_out_type;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type
);
end component;
component pcitrace
generic (
depth : integer range 6 to 12 := 8;
iregs : integer := 1;
memtech : integer := DEFMEMTECH;
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#f00#
);
port (
rst : in std_ulogic;
clk : in std_ulogic;
pciclk : in std_ulogic;
pcii : in pci_in_type;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type
);
end component;
component pcipads
generic (
padtech : integer := 0;
noreset : integer := 0;
oepol : integer := 0;
host : integer := 1;
int : integer := 0
);
port (
pci_rst : in std_ulogic;
pci_gnt : in std_ulogic;
pci_idsel : in std_ulogic;
pci_lock : inout std_ulogic;
pci_ad : inout std_logic_vector(31 downto 0);
pci_cbe : inout std_logic_vector(3 downto 0);
pci_frame : inout std_ulogic;
pci_irdy : inout std_ulogic;
pci_trdy : inout std_ulogic;
pci_devsel : inout std_ulogic;
pci_stop : inout std_ulogic;
pci_perr : inout std_ulogic;
pci_par : inout std_ulogic;
pci_req : inout std_ulogic; -- tristate pad but never read
pci_serr : inout std_ulogic; -- open drain output
pci_host : in std_ulogic;
pci_66 : in std_ulogic;
pcii : out pci_in_type;
pcio : in pci_out_type;
pci_int : inout std_logic_vector(3 downto 0)
);
end component;
component pcidma
generic (
memtech : integer := DEFMEMTECH;
dmstndx : integer := 0;
dapbndx : integer := 0;
dapbaddr : integer := 0;
dapbmask : integer := 16#fff#;
blength : integer := 16;
mstndx : integer := 0;
abits : integer := 21;
dmaabits : integer := 26;
fifodepth : integer := 3; -- FIFO depth
device_id : integer := 0; -- PCI device ID
vendor_id : integer := 0; -- PCI vendor ID
slvndx : integer := 0;
apbndx : integer := 0;
apbaddr : integer := 0;
apbmask : integer := 16#fff#;
haddr : integer := 16#F00#;
hmask : integer := 16#F00#;
ioaddr : integer := 16#000#;
nsync : integer range 1 to 2 := 2; -- 1 or 2 sync regs between clocks
oepol : integer := 0;
endian : integer := 0; -- 0 little, 1 big
class_code: integer := 16#0B4000#;
rev : integer := 0;
irq : integer := 0;
scanen : integer := 0);
port(
rst : in std_logic;
clk : in std_logic;
pciclk : in std_logic;
pcii : in pci_in_type;
pcio : out pci_out_type;
dapbo : out apb_slv_out_type;
dahbmo : out ahb_mst_out_type;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
ahbmi : in ahb_mst_in_type;
ahbmo : out ahb_mst_out_type;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type
);
end component;
component pciahbmst
generic (
hindex : integer := 0;
hirq : integer := 0;
venid : integer := VENDOR_GAISLER;
devid : integer := 0;
version : integer := 0;
chprot : integer := 3;
incaddr : integer := 0);
port (
rst : in std_ulogic;
clk : in std_ulogic;
dmai : in ahb_dma_in_type;
dmao : out ahb_dma_out_type;
ahbi : in ahb_mst_in_type;
ahbo : out ahb_mst_out_type
);
end component;
component pcif
generic (
device_id : integer := 0; -- PCI device ID
vendor_id : integer := 0; -- PCI vendor ID
class : integer := 0;
revision_id : integer := 0;
aaddr_width : integer := 28;
maddr_width : integer := 28;
pcibars : integer := 1;
ahbmasters : integer := 8;
fifo_depth : integer := 3;
ft : integer := 0;
memtech : integer := 0;
hmstndx : integer := 0;
hslvndx : integer := 0;
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#fff#;
haddr : integer := 16#F00#;
hmask : integer := 16#F00#);
port(
rst : in std_logic;
pciclk : in std_logic;
pcii : in pci_in_type;
pcio : out pci_out_type;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
ahbmi : in ahb_mst_in_type;
ahbmo : out ahb_mst_out_type;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type);
--debug : out std_logic_vector(233 downto 0));
end component;
component pcif_async
generic (
device_id : integer := 0; -- PCI device ID
vendor_id : integer := 0; -- PCI vendor ID
class : integer := 0;
revision_id : integer := 0;
bar1 : integer := 20;
bar2 : integer := 24;
bar3 : integer := 0;
bar4 : integer := 0;
ahbmasters : integer := 28;
fifo_depth : integer := 1;
ft : integer := 0;
nsync : integer := 2;
irqctrl : integer := 0;
host : integer := 0;
memtech : integer := 0;
hmstndx : integer := 0;
hslvndx : integer := 0;
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#fff#;
haddr : integer := 16#F00#;
hmask : integer := 16#F00#;
ioaddr : integer := 16#000#;
pirq : integer := 0;
netlist : integer := 0;
debugen : integer := 0
);
port(
rst : in std_logic;
clk : in std_logic;
pcirst : in std_logic;
pciclk : in std_logic;
pcii : in pci_in_type;
pcio : out pci_out_type;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
ahbmi : in ahb_mst_in_type;
ahbmo : out ahb_mst_out_type;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type--;
--debug : out std_logic_vector(255 downto 0)
);
end component;
constant PCI_VENDOR_ESA : integer := 16#16E3#;
constant PCI_VENDOR_GAISLER : integer := 16#1AC8#;
constant PCI_VENDOR_AEROFLEX : integer := 16#1AD0#;
end;
| mit | 3980b3d8094beb89277e8529138814e3 | 0.533461 | 3.387463 | false | false | false | false |
impedimentToProgress/UCI-BlueChip | AttackFiles/Attacks/privEsc/lib/gaisler/leon3/grlfpwx.vhd | 2 | 9,049 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: grlfpwx
-- File: grlfpwx.vhd
-- Author: Edvin Catovic - Gaisler Research
-- Description: GRFPU LITE / GRFPC wrapper and FP register file
------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
library gaisler;
use gaisler.leon3.all;
library techmap;
use techmap.gencomp.all;
use techmap.netcomp.all;
entity grlfpwx is
generic (tech : integer := 0;
pclow : integer range 0 to 2 := 2;
dsu : integer range 0 to 1 := 0;
disas : integer range 0 to 2 := 0;
pipe : integer := 0;
netlist : integer := 0);
port (
rst : in std_ulogic; -- Reset
clk : in std_ulogic;
holdn : in std_ulogic; -- pipeline hold
cpi : in fpc_in_type;
cpo : out fpc_out_type
);
end;
architecture rtl of grlfpwx is
signal rfi1, rfi2 : fp_rf_in_type;
signal rfo1, rfo2 : fp_rf_out_type;
component grlfpw
generic (tech : integer := 0;
pclow : integer range 0 to 2 := 2;
dsu : integer range 0 to 1 := 1;
disas : integer range 0 to 2 := 0;
pipe : integer range 0 to 2 := 0
);
port (
rst : in std_ulogic; -- Reset
clk : in std_ulogic;
holdn : in std_ulogic; -- pipeline hold
cpi_flush : in std_ulogic; -- pipeline flush
cpi_exack : in std_ulogic; -- FP exception acknowledge
cpi_a_rs1 : in std_logic_vector(4 downto 0);
cpi_d_pc : in std_logic_vector(31 downto 0);
cpi_d_inst : in std_logic_vector(31 downto 0);
cpi_d_cnt : in std_logic_vector(1 downto 0);
cpi_d_trap : in std_ulogic;
cpi_d_annul : in std_ulogic;
cpi_d_pv : in std_ulogic;
cpi_a_pc : in std_logic_vector(31 downto 0);
cpi_a_inst : in std_logic_vector(31 downto 0);
cpi_a_cnt : in std_logic_vector(1 downto 0);
cpi_a_trap : in std_ulogic;
cpi_a_annul : in std_ulogic;
cpi_a_pv : in std_ulogic;
cpi_e_pc : in std_logic_vector(31 downto 0);
cpi_e_inst : in std_logic_vector(31 downto 0);
cpi_e_cnt : in std_logic_vector(1 downto 0);
cpi_e_trap : in std_ulogic;
cpi_e_annul : in std_ulogic;
cpi_e_pv : in std_ulogic;
cpi_m_pc : in std_logic_vector(31 downto 0);
cpi_m_inst : in std_logic_vector(31 downto 0);
cpi_m_cnt : in std_logic_vector(1 downto 0);
cpi_m_trap : in std_ulogic;
cpi_m_annul : in std_ulogic;
cpi_m_pv : in std_ulogic;
cpi_x_pc : in std_logic_vector(31 downto 0);
cpi_x_inst : in std_logic_vector(31 downto 0);
cpi_x_cnt : in std_logic_vector(1 downto 0);
cpi_x_trap : in std_ulogic;
cpi_x_annul : in std_ulogic;
cpi_x_pv : in std_ulogic;
cpi_lddata : in std_logic_vector(31 downto 0); -- load data
cpi_dbg_enable : in std_ulogic;
cpi_dbg_write : in std_ulogic;
cpi_dbg_fsr : in std_ulogic; -- FSR access
cpi_dbg_addr : in std_logic_vector(4 downto 0);
cpi_dbg_data : in std_logic_vector(31 downto 0);
cpo_data : out std_logic_vector(31 downto 0); -- store data
cpo_exc : out std_logic; -- FP exception
cpo_cc : out std_logic_vector(1 downto 0); -- FP condition codes
cpo_ccv : out std_ulogic; -- FP condition codes valid
cpo_ldlock : out std_logic; -- FP pipeline hold
cpo_holdn : out std_ulogic;
cpo_dbg_data : out std_logic_vector(31 downto 0);
rfi1_rd1addr : out std_logic_vector(3 downto 0);
rfi1_rd2addr : out std_logic_vector(3 downto 0);
rfi1_wraddr : out std_logic_vector(3 downto 0);
rfi1_wrdata : out std_logic_vector(31 downto 0);
rfi1_ren1 : out std_ulogic;
rfi1_ren2 : out std_ulogic;
rfi1_wren : out std_ulogic;
rfi2_rd1addr : out std_logic_vector(3 downto 0);
rfi2_rd2addr : out std_logic_vector(3 downto 0);
rfi2_wraddr : out std_logic_vector(3 downto 0);
rfi2_wrdata : out std_logic_vector(31 downto 0);
rfi2_ren1 : out std_ulogic;
rfi2_ren2 : out std_ulogic;
rfi2_wren : out std_ulogic;
rfo1_data1 : in std_logic_vector(31 downto 0);
rfo1_data2 : in std_logic_vector(31 downto 0);
rfo2_data1 : in std_logic_vector(31 downto 0);
rfo2_data2 : in std_logic_vector(31 downto 0)
);
end component;
begin
x0 : if netlist = 0 generate
grlfpw0 : grlfpw generic map (tech, pclow, dsu, disas, pipe)
port map (
rst ,
clk ,
holdn ,
cpi.flush ,
cpi.exack ,
cpi.a_rs1 ,
cpi.d.pc ,
cpi.d.inst ,
cpi.d.cnt ,
cpi.d.trap ,
cpi.d.annul ,
cpi.d.pv ,
cpi.a.pc ,
cpi.a.inst ,
cpi.a.cnt ,
cpi.a.trap ,
cpi.a.annul ,
cpi.a.pv ,
cpi.e.pc ,
cpi.e.inst ,
cpi.e.cnt ,
cpi.e.trap ,
cpi.e.annul ,
cpi.e.pv ,
cpi.m.pc ,
cpi.m.inst ,
cpi.m.cnt ,
cpi.m.trap ,
cpi.m.annul ,
cpi.m.pv ,
cpi.x.pc ,
cpi.x.inst ,
cpi.x.cnt ,
cpi.x.trap ,
cpi.x.annul ,
cpi.x.pv ,
cpi.lddata ,
cpi.dbg.enable ,
cpi.dbg.write ,
cpi.dbg.fsr ,
cpi.dbg.addr ,
cpi.dbg.data ,
cpo.data ,
cpo.exc ,
cpo.cc ,
cpo.ccv ,
cpo.ldlock ,
cpo.holdn ,
cpo.dbg.data ,
rfi1.rd1addr ,
rfi1.rd2addr ,
rfi1.wraddr ,
rfi1.wrdata ,
rfi1.ren1 ,
rfi1.ren2 ,
rfi1.wren ,
rfi2.rd1addr ,
rfi2.rd2addr ,
rfi2.wraddr ,
rfi2.wrdata ,
rfi2.ren1 ,
rfi2.ren2 ,
rfi2.wren ,
rfo1.data1 ,
rfo1.data2 ,
rfo2.data1 ,
rfo2.data2
);
end generate;
x1 : if netlist = 1 generate
grlfpw0 : grlfpw_net generic map (tech, pclow, dsu, disas, pipe)
port map (
rst ,
clk ,
holdn ,
cpi.flush ,
cpi.exack ,
cpi.a_rs1 ,
cpi.d.pc ,
cpi.d.inst ,
cpi.d.cnt ,
cpi.d.trap ,
cpi.d.annul ,
cpi.d.pv ,
cpi.a.pc ,
cpi.a.inst ,
cpi.a.cnt ,
cpi.a.trap ,
cpi.a.annul ,
cpi.a.pv ,
cpi.e.pc ,
cpi.e.inst ,
cpi.e.cnt ,
cpi.e.trap ,
cpi.e.annul ,
cpi.e.pv ,
cpi.m.pc ,
cpi.m.inst ,
cpi.m.cnt ,
cpi.m.trap ,
cpi.m.annul ,
cpi.m.pv ,
cpi.x.pc ,
cpi.x.inst ,
cpi.x.cnt ,
cpi.x.trap ,
cpi.x.annul ,
cpi.x.pv ,
cpi.lddata ,
cpi.dbg.enable ,
cpi.dbg.write ,
cpi.dbg.fsr ,
cpi.dbg.addr ,
cpi.dbg.data ,
cpo.data ,
cpo.exc ,
cpo.cc ,
cpo.ccv ,
cpo.ldlock ,
cpo.holdn ,
cpo.dbg.data ,
rfi1.rd1addr ,
rfi1.rd2addr ,
rfi1.wraddr ,
rfi1.wrdata ,
rfi1.ren1 ,
rfi1.ren2 ,
rfi1.wren ,
rfi2.rd1addr ,
rfi2.rd2addr ,
rfi2.wraddr ,
rfi2.wrdata ,
rfi2.ren1 ,
rfi2.ren2 ,
rfi2.wren ,
rfo1.data1 ,
rfo1.data2 ,
rfo2.data1 ,
rfo2.data2
);
end generate;
rf1 : regfile_3p generic map (tech, 4, 32, 1, 16)
port map (clk, rfi1.wraddr, rfi1.wrdata, rfi1.wren, clk, rfi1.rd1addr, rfi1.ren1, rfo1.data1,
rfi1.rd2addr, rfi1.ren2, rfo1.data2);
rf2 : regfile_3p generic map (tech, 4, 32, 1, 16)
port map (clk, rfi2.wraddr, rfi2.wrdata, rfi2.wren, clk, rfi2.rd1addr, rfi2.ren1, rfo2.data1,
rfi2.rd2addr, rfi2.ren2, rfo2.data2);
end;
| mit | 083cce2b6945146a8c639341e9194be8 | 0.514864 | 3.10216 | false | false | false | false |
impedimentToProgress/UCI-BlueChip | AttackFiles/Attacks/privEsc/lib/esa/misc/l2uart.vhd | 2 | 11,539 | ----------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2004 GAISLER RESEARCH
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- See the file COPYING for the full details of the license.
--
-----------------------------------------------------------------------------
-- Entity: l2uart
-- File: l2uart.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: Asynchronous UART originally developed for LEON2.
-- Implements 8-bit data frame with one stop-bit.
-- Programmable options:
-- * parity bit (on/off)
-- * parity polarity (odd/even)
-- * baud-rate (12-bit programmable divider)
-- * hardware flow-control (CTS/RTS)
-- * Loop-back testing
--
-- Error-detection in receiver detects parity, framing
-- break and overrun errors.
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
library gaisler;
use gaisler.uart.all;
use grlib.devices.all;
--pragma translate_off
use std.textio.all;
--pragma translate_on
entity l2uart is
generic (
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#fff#;
console : integer := 0;
pirq : integer := 0
);
port (
rst : in std_ulogic;
clk : in std_ulogic;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
uarti : in uart_in_type;
uarto : out uart_out_type);
end;
architecture rtl of l2uart is
constant REVISION : integer := 1;
constant pconfig : apb_config_type := (
0 => ahb_device_reg ( VENDOR_ESA, ESA_UART, 0, REVISION, pirq),
1 => apb_iobar(paddr, pmask));
type rxfsmtype is (idle, startbit, data, cparity, stopbit);
type txfsmtype is (idle, data, cparity, stopbit);
type uartregs is record
rxen : std_ulogic; -- receiver enabled
txen : std_ulogic; -- transmitter enabled
rirqen : std_ulogic; -- receiver irq enable
tirqen : std_ulogic; -- transmitter irq enable
parsel : std_ulogic; -- parity select
paren : std_ulogic; -- parity select
flow : std_ulogic; -- flow control enable
loopb : std_ulogic; -- loop back mode enable
dready : std_ulogic; -- data ready
rsempty : std_ulogic; -- receiver shift register empty (internal)
tsempty : std_ulogic; -- transmitter shift register empty
thempty : std_ulogic; -- transmitter hold register empty
break : std_ulogic; -- break detected
ovf : std_ulogic; -- receiver overflow
parerr : std_ulogic; -- parity error
frame : std_ulogic; -- framing error
rtsn : std_ulogic; -- request to send
extclken : std_ulogic; -- use external baud rate clock
extclk : std_ulogic; -- rising edge detect register
rhold : std_logic_vector(7 downto 0);
rshift : std_logic_vector(7 downto 0);
tshift : std_logic_vector(10 downto 0);
thold : std_logic_vector(7 downto 0);
irq : std_ulogic; -- tx/rx interrupt (internal)
tpar : std_ulogic; -- tx data parity (internal)
txstate : txfsmtype;
txclk : std_logic_vector(2 downto 0); -- tx clock divider
txtick : std_ulogic; -- tx clock (internal)
rxstate : rxfsmtype;
rxclk : std_logic_vector(2 downto 0); -- rx clock divider
rxdb : std_logic_vector(1 downto 0); -- rx delay
dpar : std_ulogic; -- rx data parity (internal)
rxtick : std_ulogic; -- rx clock (internal)
tick : std_ulogic; -- rx clock (internal)
scaler : std_logic_vector(11 downto 0);
brate : std_logic_vector(11 downto 0);
rxf : std_logic_vector(7 downto 0); -- rx data filtering buffer
txd : std_ulogic; -- transmitter data
end record;
signal r, rin : uartregs;
begin
uartop : process(rst, r, apbi, uarti )
variable rdata : std_logic_vector(31 downto 0);
variable scaler : std_logic_vector(11 downto 0);
variable rxclk, txclk : std_logic_vector(2 downto 0);
variable rxd, ctsn : std_ulogic;
variable irq : std_logic_vector(NAHBIRQ-1 downto 0);
variable v : uartregs;
--pragma translate_off
variable L1 : line;
variable CH : character;
variable FIRST : boolean := true;
variable pt : time := 0 ns;
--pragma translate_on
begin
v := r; irq := (others => '0'); irq(pirq) := r.irq;
v.irq := '0'; v.txtick := '0'; v.rxtick := '0'; v.tick := '0';
rdata := (others => '0'); v.rxdb(1) := r.rxdb(0);
-- scaler
scaler := r.scaler - 1;
if (r.rxen or r.txen) = '1' then
v.scaler := scaler;
v.tick := scaler(11) and not r.scaler(11);
if v.tick = '1' then v.scaler := r.brate; end if;
end if;
-- optional external uart clock
v.extclk := uarti.extclk;
if r.extclken = '1' then v.tick := r.extclk and not uarti.extclk; end if;
-- read/write registers
case apbi.paddr(3 downto 2) is
when "00" =>
rdata(7 downto 0) := r.rhold;
if (apbi.psel(pindex) and apbi.penable and (not apbi.pwrite)) = '1' then
v.dready := '0';
end if;
when "01" =>
rdata(6 downto 0) := r.frame & r.parerr & r.ovf &
r.break & r.thempty & r.tsempty & r.dready;
--pragma translate_off
if CONSOLE = 1 then rdata(2 downto 1) := "11"; end if;
--pragma translate_on
when "10" =>
rdata(8 downto 0) := r.extclken & r.loopb & r.flow & r.paren & r.parsel &
r.tirqen & r.rirqen & r.txen & r.rxen;
when others =>
rdata(11 downto 0) := r.brate;
end case;
if (apbi.psel(pindex) and apbi.penable and apbi.pwrite) = '1' then
case apbi.paddr(3 downto 2) is
when "01" =>
v.frame := apbi.pwdata(6);
v.parerr := apbi.pwdata(5);
v.ovf := apbi.pwdata(4);
v.break := apbi.pwdata(3);
when "10" =>
v.extclken := apbi.pwdata(8);
v.loopb := apbi.pwdata(7);
v.flow := apbi.pwdata(6);
v.paren := apbi.pwdata(5);
v.parsel := apbi.pwdata(4);
v.tirqen := apbi.pwdata(3);
v.rirqen := apbi.pwdata(2);
v.txen := apbi.pwdata(1);
v.rxen := apbi.pwdata(0);
when "11" =>
v.brate := apbi.pwdata(11 downto 0);
v.scaler := apbi.pwdata(11 downto 0);
when others =>
end case;
end if;
-- tx clock
txclk := r.txclk + 1;
if r.tick = '1' then
v.txclk := txclk;
v.txtick := r.txclk(2) and not txclk(2);
end if;
-- rx clock
rxclk := r.rxclk + 1;
if r.tick = '1' then
v.rxclk := rxclk;
v.rxtick := r.rxclk(2) and not rxclk(2);
end if;
-- filter rx data
v.rxf := r.rxf(6 downto 0) & uarti.rxd;
if ((r.rxf(7) & r.rxf(7) & r.rxf(7) & r.rxf(7) & r.rxf(7) & r.rxf(7) &
r.rxf(7)) = r.rxf(6 downto 0))
then v.rxdb(0) := r.rxf(7); end if;
-- loop-back mode
if r.loopb = '1' then
v.rxdb(0) := r.tshift(0); ctsn := r.dready and not r.rsempty;
else
ctsn := uarti.ctsn;
end if;
rxd := r.rxdb(0);
-- transmitter operation
case r.txstate is
when idle => -- idle state
if (r.txtick = '1') then v.tsempty := '1'; end if;
if ((r.txen and (not r.thempty) and r.txtick) and
((not ctsn) or not r.flow)) = '1' then
v.tshift := "10" & r.thold & '0'; v.txstate := data;
v.tpar := r.parsel; v.irq := r.tirqen; v.thempty := '1';
v.tsempty := '0'; v.txclk := "00" & r.tick; v.txtick := '0';
end if;
when data => -- transmitt data frame
if r.txtick = '1' then
v.tpar := r.tpar xor r.tshift(1);
v.tshift := '1' & r.tshift(10 downto 1);
if r.tshift(10 downto 1) = "1111111110" then
if r.paren = '1' then
v.tshift(0) := r.tpar; v.txstate := cparity;
else
v.tshift(0) := '1'; v.txstate := stopbit;
end if;
end if;
end if;
when cparity => -- transmitt parity bit
if r.txtick = '1' then
v.tshift := '1' & r.tshift(10 downto 1); v.txstate := stopbit;
end if;
when stopbit => -- transmitt stop bit
if r.txtick = '1' then
v.tshift := '1' & r.tshift(10 downto 1); v.txstate := idle;
end if;
end case;
-- writing of tx data register must be done after tx fsm to get correct
-- operation of thempty flag
if (apbi.psel(pindex) and apbi.penable and apbi.pwrite) = '1' then
case apbi.paddr(3 downto 2) is
when "00" =>
v.thold := apbi.pwdata(7 downto 0); v.thempty := '0';
--pragma translate_off
if CONSOLE = 1 then
if first then L1:= new string'(""); first := false; end if; --'
if apbi.penable'event then --'
CH := character'val(conv_integer(apbi.pwdata(7 downto 0))); --'
if CH = CR then
std.textio.writeline(OUTPUT, L1);
elsif CH /= LF then
std.textio.write(L1,CH);
end if;
pt := now;
end if;
end if;
--pragma translate_on
when others => null;
end case;
end if;
-- receiver operation
case r.rxstate is
when idle => -- wait for start bit
if ((not r.rsempty) and not r.dready) = '1' then
v.rhold := r.rshift; v.rsempty := '1'; v.dready := '1';
end if;
if (r.rxen and r.rxdb(1) and (not rxd)) = '1' then
v.rxstate := startbit; v.rshift := (others => '1'); v.rxclk := "100";
if v.rsempty = '0' then v.ovf := '1'; end if;
v.rsempty := '0'; v.rxtick := '0';
end if;
when startbit => -- check validity of start bit
if r.rxtick = '1' then
if rxd = '0' then
v.rshift := rxd & r.rshift(7 downto 1); v.rxstate := data;
v.dpar := r.parsel;
else
v.rxstate := idle;
end if;
end if;
when data => -- receive data frame
if r.rxtick = '1' then
v.dpar := r.dpar xor rxd;
v.rshift := rxd & r.rshift(7 downto 1);
if r.rshift(0) = '0' then
if r.paren = '1' then v.rxstate := cparity;
else v.rxstate := stopbit; v.dpar := '0'; end if;
end if;
end if;
when cparity => -- receive parity bit
if r.rxtick = '1' then
v.dpar := r.dpar xor rxd; v.rxstate := stopbit;
end if;
when stopbit => -- receive stop bit
if r.rxtick = '1' then
v.irq := v.irq or r.rirqen; -- make sure no tx irqs are lost !
if rxd = '1' then
v.parerr := r.dpar; v.rsempty := r.dpar;
if v.dready = '0' then
v.rhold := r.rshift; v.rsempty := '1'; v.dready := not r.dpar;
end if;
else
if r.rshift = "00000000" then v.break := '1';
else v.frame := '1'; end if;
v.rsempty := '1';
end if;
v.rxstate := idle;
end if;
end case;
if r.rxtick = '1' then
v.rtsn := (r.dready and not r.rsempty) or r.loopb;
end if;
v.txd := r.tshift(0) or r.loopb;
-- reset operation
if rst = '0' then
v.frame := '0'; v.rsempty := '1';
v.parerr := '0'; v.ovf := '0'; v.break := '0'; v.thempty := '1';
v.tsempty := '1'; v.dready := '0'; v.txen := '0'; v.rxen := '0';
v.txstate := idle; v.rxstate := idle; v.tshift(0) := '1';
v.extclken := '0'; v.rtsn := '1'; v.flow := '0';
v.txclk := (others => '0'); v.rxclk := (others => '0');
end if;
-- update registers
rin <= v;
-- drive outputs
uarto.txd <= r.txd; uarto.rtsn <= r.rtsn;
apbo.prdata <= rdata; apbo.pirq <= irq;
apbo.pindex <= pindex;
end process;
apbo.pconfig <= pconfig;
regs : process(clk)
begin if rising_edge(clk) then r <= rin; end if; end process;
-- pragma translate_off
bootmsg : report_version
generic map ("l2uart" & tost(pindex) &
": LEON2 Generic UART rev " & tost(REVISION) & ", irq " & tost(pirq));
-- pragma translate_on
end;
| mit | 9280c00451d6ab432b0f38dd9935f465 | 0.580553 | 3.055879 | false | false | false | false |
michaelfivez/ascon_hardware_implementation | ascon128128_unrolled4/Kernel/OutputGenerator.vhd | 1 | 7,708 | -------------------------------------------------------------------------------
--! @project Unrolled (factor 4) hardware implementation of Asconv128128
--! @author Michael Fivez
--! @license This project is released under the GNU Public License.
--! The license and distribution terms for this file may be
--! found in the file LICENSE in this distribution or at
--! http://www.gnu.org/licenses/gpl-3.0.txt
--! @note This is an hardware implementation made for my graduation thesis
--! at the KULeuven, in the COSIC department (year 2015-2016)
--! The thesis is titled 'Energy efficient hardware implementations of CAESAR submissions',
--! and can be found on the COSIC website (www.esat.kuleuven.be/cosic/publications)
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity OutputGenerator is
port(
In0 : in std_logic_vector(63 downto 0);
In1 : in std_logic_vector(63 downto 0);
DataIn : in std_logic_vector(127 downto 0);
Size : in std_logic_vector(3 downto 0);
Activate : in std_logic;
Out0 : out std_logic_vector(63 downto 0);
Out1 : out std_logic_vector(63 downto 0);
DataOut : out std_logic_vector(127 downto 0));
end entity OutputGenerator;
architecture structural of OutputGenerator is
constant ALLZERO : std_logic_vector(127 downto 0) := (others => '0');
signal Temp0,Temp1,Temp2 : std_logic_vector(127 downto 0);
begin
Gen: process(In0,In1,DataIn,Size,Activate,Temp0,Temp1,Temp2) is
-- Truncator0&1
procedure doTruncate0 ( -- Truncate block 0 and 1 together
signal Input : in std_logic_vector(127 downto 0);
signal Size : in std_logic_vector(3 downto 0);
signal Activate : in std_logic;
signal Output : out std_logic_vector(127 downto 0)) is
variable ActSize : std_logic_vector(4 downto 0);
begin
ActSize(4) := Activate;
ActSize(3 downto 0) := Size;
-- if inactive it lets everything trough, if active it lets the first blocksize bits trough
logic: case ActSize is
when "10001" =>
Output(127 downto 120) <= Input(127 downto 120);
Output(119) <= '1';
Output(118 downto 0) <= ALLZERO(118 downto 0);
when "10010" =>
Output(127 downto 112) <= Input(127 downto 112);
Output(111) <= '1';
Output(110 downto 0) <= ALLZERO(110 downto 0);
when "10011" =>
Output(127 downto 104) <= Input(127 downto 104);
Output(103) <= '1';
Output(102 downto 0) <= ALLZERO(102 downto 0);
when "10100" =>
Output(127 downto 96) <= Input(127 downto 96);
Output(95) <= '1';
Output(94 downto 0) <= ALLZERO(94 downto 0);
when "10101" =>
Output(127 downto 88) <= Input(127 downto 88);
Output(87) <= '1';
Output(86 downto 0) <= ALLZERO(86 downto 0);
when "10110" =>
Output(127 downto 80) <= Input(127 downto 80);
Output(79) <= '1';
Output(78 downto 0) <= ALLZERO(78 downto 0);
when "10111" =>
Output(127 downto 72) <= Input(127 downto 72);
Output(71) <= '1';
Output(70 downto 0) <= ALLZERO(70 downto 0);
when "11000" =>
Output(127 downto 64) <= Input(127 downto 64);
Output(63) <= '1';
Output(62 downto 0) <= ALLZERO(62 downto 0);
when "11001" =>
Output(127 downto 56) <= Input(127 downto 56);
Output(55) <= '1';
Output(54 downto 0) <= ALLZERO(54 downto 0);
when "11010" =>
Output(127 downto 48) <= Input(127 downto 48);
Output(47) <= '1';
Output(46 downto 0) <= ALLZERO(46 downto 0);
when "11011" =>
Output(127 downto 40) <= Input(127 downto 40);
Output(39) <= '1';
Output(38 downto 0) <= ALLZERO(38 downto 0);
when "11100" =>
Output(127 downto 32) <= Input(127 downto 32);
Output(31) <= '1';
Output(30 downto 0) <= ALLZERO(30 downto 0);
when "11101" =>
Output(127 downto 24) <= Input(127 downto 24);
Output(23) <= '1';
Output(22 downto 0) <= ALLZERO(22 downto 0);
when "11110" =>
Output(127 downto 16) <= Input(127 downto 16);
Output(15) <= '1';
Output(14 downto 0) <= ALLZERO(14 downto 0);
when "11111" =>
Output(127 downto 8) <= Input(127 downto 8);
Output(7) <= '1';
Output(6 downto 0) <= ALLZERO(6 downto 0);
when others => -- deactivate or blocksize max or invalid input (cas 0xxxx or 10000)
Output <= Input;
end case logic;
end procedure doTruncate0;
-- Truncator2
procedure doTruncate2 ( -- Truncate block 0 and 1 together
signal Input : in std_logic_vector(127 downto 0);
signal Size : in std_logic_vector(3 downto 0);
signal Activate : in std_logic;
signal Output : out std_logic_vector(127 downto 0)) is
variable ActSize : std_logic_vector(4 downto 0);
begin
ActSize(4) := Activate;
ActSize(3 downto 0) := Size;
-- if inactive it lets everything trough, if active it blocks the first blocksize bits
logic: case ActSize is
when "10000" =>
Output <= ALLZERO;
when "10001" =>
Output(127 downto 120) <= ALLZERO(127 downto 120);
Output(119 downto 0) <= Input(119 downto 0);
when "10010" =>
Output(127 downto 112) <= ALLZERO(127 downto 112);
Output(111 downto 0) <= Input(111 downto 0);
when "10011" =>
Output(127 downto 104) <= ALLZERO(127 downto 104);
Output(103 downto 0) <= Input(103 downto 0);
when "10100" =>
Output(127 downto 96) <= ALLZERO(127 downto 96);
Output(95 downto 0) <= Input(95 downto 0);
when "10101" =>
Output(127 downto 88) <= ALLZERO(127 downto 88);
Output(87 downto 0) <= Input(87 downto 0);
when "10110" =>
Output(127 downto 80) <= ALLZERO(127 downto 80);
Output(79 downto 0) <= Input(79 downto 0);
when "10111" =>
Output(127 downto 72) <= ALLZERO(127 downto 72);
Output(71 downto 0) <= Input(71 downto 0);
when "11000" =>
Output(127 downto 64) <= ALLZERO(127 downto 64);
Output(63 downto 0) <= Input(63 downto 0);
when "11001" =>
Output(127 downto 56) <= ALLZERO(127 downto 56);
Output(55 downto 0) <= Input(55 downto 0);
when "11010" =>
Output(127 downto 48) <= ALLZERO(127 downto 48);
Output(47 downto 0) <= Input(47 downto 0);
when "11011" =>
Output(127 downto 40) <= ALLZERO(127 downto 40);
Output(39 downto 0) <= Input(39 downto 0);
when "11100" =>
Output(127 downto 32) <= ALLZERO(127 downto 32);
Output(31 downto 0) <= Input(31 downto 0);
when "11101" =>
Output(127 downto 24) <= ALLZERO(127 downto 24);
Output(23 downto 0) <= Input(23 downto 0);
when "11110" =>
Output(127 downto 16) <= ALLZERO(127 downto 16);
Output(15 downto 0) <= Input(15 downto 0);
when "11111" =>
Output(127 downto 8) <= ALLZERO(127 downto 8);
Output(7 downto 0) <= Input(7 downto 0);
when others => -- deactivate or blocksize max or invalid input (cas 0xxxx or 10000)
Output <= Input;
end case logic;
end procedure doTruncate2;
begin
-- DataOut
DataOut(127 downto 64) <= In0 xor DataIn(127 downto 64);
DataOut(63 downto 0) <= In1 xor DataIn(63 downto 0);
-- Stateupdate
doTruncate0(DataIn,Size,Activate,Temp0);
Temp1(127 downto 64) <= In0;
Temp1(63 downto 0) <= In1;
doTruncate2(Temp1,Size,Activate,Temp2);
Out0 <= Temp0(127 downto 64) xor Temp2(127 downto 64);
Out1 <= Temp0(63 downto 0) xor Temp2(63 downto 0);
end process Gen;
end architecture structural;
| gpl-3.0 | 0871a0b4e2d595aaa5531effabbf0d12 | 0.599896 | 3.342585 | false | false | false | false |
michaelfivez/ascon_hardware_implementation | ascon12864_unrolled6/API_plus_CipherCore/PostProcessor_Control.vhd | 9 | 44,051 | -------------------------------------------------------------------------------
--! @file PostProcessor_Control.vhd
--! @brief Control unit for post-processor
--! @project CAESAR Candidate Evaluation
--! @author Ekawat (ice) Homsirikamol
--! @copyright Copyright (c) 2015 Cryptographic Engineering Research Group
--! ECE Department, George Mason University Fairfax, VA, U.S.A.
--! All rights Reserved.
--! @license This project is released under the GNU Public License.
--! The license and distribution terms for this file may be
--! found in the file LICENSE in this distribution or at
--! http://www.gnu.org/licenses/gpl-3.0.txt
--! @note This is publicly available encryption source code that falls
--! under the License Exception TSU (Technology and software-
--! —unrestricted)
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
use work.AEAD_pkg.all;
entity PostProcessor_Control is
generic (
G_W : integer := 64; --! Output width (bits)
G_DBLK_SIZE : integer := 128; --! Block size (bits)
G_BS_BYTES : integer := 4; --! The number of bits required to hold block size expressed in bytes = log2_ceil(block_size/8)
G_TAG_SIZE : integer := 128; --! Tag size (bits)
G_REVERSE_DBLK : integer := 0; --! Reverse order of message block
G_CIPHERTEXT_MODE : integer := 0; --! Ciphertext processing mode
G_LOADLEN_ENABLE : integer := 0; --! Enable load length section
G_PAD_D : integer := 0 --! Padding of data block
);
port (
--! =================
--! Global Signals
--! =================
--! Global signals
clk : in std_logic;
rst : in std_logic;
--! =================
--! External Signals
--! =================
do_ready : in std_logic; --! Output FIFO ready
do_valid : out std_logic;
bypass_fifo_data : in std_logic_vector(G_W -1 downto 0); --! Bypass FIFO data
bypass_fifo_empty : in std_logic; --! Bypass FIFO empty
bypass_fifo_rd : out std_logic; --! Bypass FIFO read
bdo_ready : out std_logic; --! Output BDO ready (Let crypto core knows that it's ready to accept data)
bdo_write : in std_logic; --! Write to output BDO
bdo_size : in std_logic_vector(G_BS_BYTES+1 -1 downto 0); --! Data size
bdo_nsec : in std_logic; --! Nsec flag
tag_ready : out std_logic; --! Output TAG ready (Let crypto core knows that it's ready to accept data)
tag_write : in std_logic; --! Write to output TAG
msg_auth_done : in std_logic;
msg_auth_valid : in std_logic;
--! =================
--! Controls
--! =================
bdo_shf : out std_logic; --! Shift output BDO
tag_shf : out std_logic; --! Shift tag register
sel_instr_dec : out std_logic; --! Increment instruction Opcode by 1
sel_instr_actkey : out std_logic; --! Select ACT KEY opcode
sel_hdr : out std_logic; --! Switch EOI of different segment header
sel_do : out std_logic_vector( 2 -1 downto 0); --! Output selection
sel_sw : out std_logic_vector( 2 -1 downto 0); --! Segment type encoding selection
sel_sgmt_hdr : out std_logic_vector( 2 -1 downto 0); --! Select custom header
sel_hword : out std_logic; --! [Special case] Select half word
sel_hword_init : out std_logic; --! [Special case] Store the left over
is_i_type : out std_logic_vector( 4 -1 downto 0); --! Segment type identifier 1 (Cipher/Message)
is_i_nsec : out std_logic_vector( 4 -1 downto 0); --! Segment type identifier 2 (Secret number message / Enecrypted secret number message)
msg_id : out std_logic_vector(LEN_MSG_ID -1 downto 0); --! Message ID
key_id : out std_logic_vector(LEN_KEY_ID -1 downto 0); --! Key ID
data_bytes : out std_logic_vector(log2_ceil(G_W/8) -1 downto 0); --! Data size
en_zeroize : out std_logic; --! Enable zeroization
--! CIPHERTEXT_MODE=2
save_size : out std_logic;
clr_size : out std_logic;
sel_do2 : out std_logic;
sel_do2_eoi : out std_logic;
last_sgmt_size : in std_logic_vector(CTR_SIZE_LIM -1 downto 0);
aux_fifo_dout : in std_logic_vector(G_W -1 downto 0);
aux_fifo_ctrl : out std_logic_vector(4 -1 downto 0);
aux_fifo_status : in std_logic_vector(3 -1 downto 0)
);
end PostProcessor_Control;
architecture behavior of PostProcessor_Control is
--! Function and constants declaration
function get_bdo_count_width return integer is
begin
if G_CIPHERTEXT_MODE = 2 then
return G_BS_BYTES+1;
else
return G_BS_BYTES;
end if;
end function get_bdo_count_width;
constant PARTIAL_LOAD : integer := isNotDivisible(G_DBLK_SIZE, G_W);
constant LOG2_WD8 : integer := log2_ceil(G_W/8);
constant ONES : std_logic_vector(G_DBLK_SIZE-1 downto 0) := (others => '1');
constant ZEROS : std_logic_vector(G_DBLK_SIZE-1 downto 0) := (others => '0');
constant CNTR_WIDTH : integer := get_cntr_width(G_W);
constant BDO_COUNT_WIDTH : integer := get_bdo_count_width;
type state_type is (S_WAIT_INSTR, S_READ_INSTR, S_GEN_SUCC_HDR,
S_GEN_ACT_KEY_DELAY, S_WAIT_HDR, S_READ_HDR,
S_WAIT_BYPASS, S_WAIT_BDO, S_GEN_TAG_HDR,
S_WRITE_TAG, S_GEN_CIPH_HDR, S_WAIT_MSG_AUTH,
S_WRITE_TAG_ERROR, S_ERROR);
signal state : state_type;
signal nstate : state_type;
signal fifo_write_pre : std_logic;
signal fifo_write_now : std_logic;
signal fifo_write_r : std_logic;
signal sel_do_pre : std_logic_vector( 2 -1 downto 0);
signal sel_sgmt_hdr_pre : std_logic_vector( 2 -1 downto 0);
signal tag_count : std_logic_vector(log2_ceil(G_TAG_SIZE/8) -1 downto 0);
signal tag_empty : std_logic;
signal tag_shf_pre : std_logic;
signal bdo_count : std_logic_vector(BDO_COUNT_WIDTH -1 downto 0);
signal bdo_empty : std_logic;
signal bdo_shf_pre : std_logic;
signal bdo_clr_pre : std_logic;
signal opcode : std_logic_vector( 4 -1 downto 0);
signal sgmt_stype : std_logic_vector( 4 -1 downto 0);
signal sgmt_eoi : std_logic;
signal sgmt_eot : std_logic;
signal en_instr_flag : std_logic;
signal is_decrypt : std_logic;
signal is_ae : std_logic;
signal is_ad : std_logic;
signal en_sgmt_status : std_logic;
signal clr_hdr_status : std_logic;
signal instr_decrypt : std_logic;
signal sgmt_msg_type : std_logic_vector( 4 -1 downto 0);
signal sgmt_nsec_type : std_logic_vector( 4 -1 downto 0);
signal sgmt_nsec_flag : std_logic;
signal msg_end : std_logic;
signal msg_id_r : std_logic_vector(LEN_MSG_ID -1 downto 0);
signal key_id_r : std_logic_vector(LEN_KEY_ID -1 downto 0);
signal counter_load_tag : std_logic;
signal counter_load_block : std_logic;
signal counter_load : std_logic;
signal counter_en : std_logic;
signal sgmt_size : std_logic_vector(CNTR_WIDTH -1 downto 0);
signal sw_stype : std_logic;
signal sw_nsec : std_logic;
signal hold_output : std_logic;
signal clr_hold_output : std_logic;
signal restore_state : std_logic;
signal clr_status : std_logic;
signal set_sgmt_tag_flag : std_logic;
signal sgmt_tag_flag : std_logic;
signal set_sgmt_tag_passed : std_logic;
signal sgmt_tag_passed : std_logic;
signal set_no_write : std_logic;
signal no_write : std_logic;
signal msg_auth_done_r : std_logic;
signal msg_auth_valid_r : std_logic;
--! Partial data related signals
signal toggle_partial : std_logic;
signal clr_partial : std_logic;
signal is_partial : std_logic;
signal fifo_save_state : std_logic;
signal fifo_restore_state : std_logic;
signal fifo_write : std_logic;
signal fifo_read : std_logic;
signal fifo_unread_avail : std_logic;
signal fifo_empty : std_logic;
signal fifo_full : std_logic;
begin
fifo_unread_avail <= aux_fifo_status(0);
fifo_empty <= aux_fifo_status(1);
fifo_full <= aux_fifo_status(2);
aux_fifo_ctrl <= fifo_read & fifo_write & fifo_restore_state & fifo_save_state;
--! Output
sel_sw <= sw_stype & sw_nsec;
gPartial:
if (PARTIAL_LOAD = 1) generate
sel_hword <= is_partial;
end generate;
is_i_type <= sgmt_msg_type;
is_i_nsec <= sgmt_nsec_type;
msg_id <= msg_id_r;
key_id <= key_id_r;
fifo_save_state <= is_decrypt;
fifo_restore_state <= restore_state;
--! Format decoder
opcode <= bypass_fifo_data(G_W-12-1 downto G_W-16);
sgmt_stype <= bypass_fifo_data(G_W- 8-1 downto G_W-12);
sgmt_eot <= bypass_fifo_data(G_W-15-1);
sgmt_eoi <= bypass_fifo_data(G_W-14-1);
data_bytes <= sgmt_size(log2_ceil(G_W/8)-1 downto 0);
--! Registers
procRegs:
process( clk )
begin
if rising_edge( clk ) then
if rst = '1' then
state <= S_WAIT_INSTR;
sgmt_msg_type <= (others => '0');
msg_end <= '0';
sgmt_size <= (others => '0');
msg_id_r <= (others => '0');
bdo_empty <= '1';
tag_empty <= '1';
hold_output <= '0';
msg_auth_done_r <= '0';
tag_count <= (others => '0');
bdo_count <= (others => '0');
no_write <= '0';
fifo_write_r <= '0';
sgmt_tag_passed <= '0';
msg_auth_valid_r <= '0';
else
state <= nstate;
if en_instr_flag = '1' then
msg_id_r <= bypass_fifo_data(G_W-1 downto G_W-LEN_MSG_ID);
key_id_r <= bypass_fifo_data(G_W-LEN_MSG_ID-4-LEN_OPCODE-1 downto G_W-LEN_MSG_ID-4-LEN_OPCODE-LEN_KEY_ID);
if is_decrypt = '1' then
sgmt_msg_type <= ST_MESSAGE;
sgmt_nsec_type <= ST_NSEC;
instr_decrypt <= '1';
else
sgmt_msg_type <= ST_CIPHER;
sgmt_nsec_type <= ST_NSEC_CIPH;
instr_decrypt <= '0';
end if;
end if;
if (en_instr_flag = '1') then
if ((is_decrypt = '1') or (G_CIPHERTEXT_MODE = 2)) then
hold_output <= '1';
else
hold_output <= '0';
end if;
elsif (clr_hold_output = '1') then
hold_output <= '0';
end if;
if clr_hdr_status = '1' then
msg_end <= '0';
elsif en_sgmt_status = '1' then
msg_end <= sgmt_eoi;
end if;
if counter_load_tag = '1' then
sgmt_size <= std_logic_vector(to_unsigned(G_TAG_SIZE/8, CNTR_WIDTH));
elsif (G_CIPHERTEXT_MODE = 2 and G_PAD_D = 4 and counter_load_block = '1') then
--! Special case for when Msg = 0 in G_CIPHERTEXT_MODE and G_PAD_D = 2
sgmt_size <= std_logic_vector(to_unsigned(G_DBLK_SIZE/8, CNTR_WIDTH));
elsif counter_load = '1' then
if (G_CIPHERTEXT_MODE = 2) then
if (sgmt_stype = ST_MESSAGE and sgmt_eoi = '1' and G_REVERSE_DBLK = 0) then
sgmt_size <= (bypass_fifo_data(CNTR_WIDTH-1 downto G_BS_BYTES) + 1) & ZEROS(G_BS_BYTES-1 downto 0);
else
sgmt_size <= bypass_fifo_data(CNTR_WIDTH-1 downto 0);
end if;
else
sgmt_size <= bypass_fifo_data(CNTR_WIDTH-1 downto 0);
end if;
elsif counter_en = '1' then
sgmt_size <= sgmt_size - G_W/8;
end if;
if state = S_READ_HDR then
if sw_nsec = '1' then
sgmt_nsec_flag <= '1';
else
sgmt_nsec_flag <= '0';
end if;
end if;
--! Keeps track whether the BDO register is empty
if (bdo_write = '1') then
bdo_empty <= '0';
elsif ((bdo_count = 0) or
(G_CIPHERTEXT_MODE = 2 and bdo_count <= G_W/8 and bdo_shf_pre = '1') or
(sgmt_size <= G_W/8 and bdo_shf_pre = '1') or
(bdo_clr_pre = '1'))
then
bdo_empty <= '1';
end if;
--! Keeps track of available bytes in BDO register
if (G_CIPHERTEXT_MODE /= 2) then
if (bdo_write = '1') then
if (PARTIAL_LOAD = 1) then
bdo_count <= std_logic_vector(to_unsigned(((G_DBLK_SIZE+G_W-1)/G_W), G_BS_BYTES));
else
bdo_count <= std_logic_vector(to_unsigned(G_DBLK_SIZE/G_W-1, G_BS_BYTES));
end if;
elsif (bdo_shf_pre = '1') then
bdo_count <= bdo_count - 1;
end if;
else
if (bdo_write = '1') then
bdo_count <= bdo_size;
elsif (bdo_shf_pre = '1') then
if (bdo_count > G_W/8) then
bdo_count <= bdo_count - G_W/8;
else
bdo_count <= (others => '0');
end if;
end if;
end if;
--! Keeps track whether the TAG register is empty
if (tag_write = '1') then
tag_empty <= '0';
elsif (G_TAG_SIZE > G_W and ((tag_shf_pre = '1' and sgmt_size = 1) or (tag_count = 0 and tag_shf_pre = '1'))) or
(G_TAG_SIZE <= G_W and (sel_do_pre = "11"))
then
tag_empty <= '1';
end if;
--! Keeps track of available bytes in TAG register
if (G_TAG_SIZE > G_W) then
if (tag_write = '1') then
tag_count <= std_logic_vector(to_unsigned(G_TAG_SIZE/G_W-1, log2_ceil(G_TAG_SIZE/8)));
elsif (tag_shf_pre = '1') then
tag_count <= tag_count - 1;
end if;
end if;
if (set_sgmt_tag_flag = '1') then
sgmt_tag_flag <= '1';
elsif (clr_status = '1') then
sgmt_tag_flag <= '0';
end if;
if (set_no_write = '1') then
no_write <= '1';
elsif (clr_status = '1') then
no_write <= '0';
end if;
if (set_sgmt_tag_passed = '1') then
sgmt_tag_passed <= '1';
elsif (clr_status = '1') then
sgmt_tag_passed <= '0';
end if;
--! Capture the tag comparison flag and result
if (clr_hold_output = '1') then
msg_auth_done_r <= '0';
elsif (msg_auth_done = '1') then
msg_auth_done_r <= '1';
msg_auth_valid_r <= msg_auth_valid;
end if;
if (PARTIAL_LOAD = 1) then
if (toggle_partial = '1') then
is_partial <= not is_partial;
elsif (clr_partial = '1') then
is_partial <= '0';
end if;
if (toggle_partial = '1' and is_partial = '0') then
sel_hword_init <= '1';
else
sel_hword_init <= '0';
end if;
end if;
if (G_TAG_SIZE > G_W) then
tag_shf <= tag_shf_pre;
end if;
bdo_shf <= bdo_shf_pre;
sel_do <= sel_do_pre;
fifo_write_r <= fifo_write_pre;
sel_sgmt_hdr <= sel_sgmt_hdr_pre;
end if;
end if;
end process;
fifo_write <= fifo_write_r or fifo_write_now;
--! Controller
procFSM:
process( state, bypass_fifo_empty, bypass_fifo_data, bdo_empty, bdo_write, fifo_full, sgmt_nsec_flag,
sgmt_size, opcode, sgmt_stype, msg_end, hold_output, sgmt_tag_flag, bdo_count, is_partial,
tag_empty, msg_auth_valid_r, msg_auth_done_r, instr_decrypt, no_write)
begin
sel_do_pre <= "00";
fifo_write_pre <= '0';
fifo_write_now <= '0';
bypass_fifo_rd <= '0';
is_ae <= '0';
is_ad <= '0';
is_decrypt <= '0';
en_instr_flag <= '0';
en_sgmt_status <= '0';
clr_hdr_status <= '0';
counter_load_tag <= '0';
if (G_CIPHERTEXT_MODE = 2) then
counter_load_block <= '0';
clr_size <= '0';
save_size <= '0';
end if;
if (PARTIAL_LOAD = 1) then
toggle_partial <= '0';
clr_partial <= '0';
end if;
counter_load <= '0';
counter_en <= '0';
sw_stype <= '0';
sel_instr_dec <= '0';
sel_instr_actkey <= '0';
sel_hdr <= '0';
sel_sgmt_hdr_pre <= "00";
sw_nsec <= '0';
bdo_shf_pre <= '0';
bdo_clr_pre <= '0';
restore_state <= '0';
clr_hold_output <= '0';
if (G_TAG_SIZE > G_W) then
tag_shf_pre <= '0';
end if;
set_sgmt_tag_flag <= '0';
set_sgmt_tag_passed <= '0';
clr_status <= '0';
en_zeroize <= '0';
set_no_write <= '0';
nstate <= state;
case state is
when S_WAIT_INSTR =>
if (bypass_fifo_empty = '0' and fifo_full = '0') then
nstate <= S_READ_INSTR;
bypass_fifo_rd <= '1';
clr_hdr_status <= '1';
bdo_clr_pre <= '1';
clr_status <= '1';
clr_hold_output <= '1';
end if;
when S_READ_INSTR =>
if (opcode = OP_ACT_KEY) then
nstate <= S_WAIT_INSTR;
else
if (opcode = OP_AE_DEC or opcode = OP_DEC) then
nstate <= S_GEN_SUCC_HDR;
else
--! Generate ACT_KEY instruction word
nstate <= S_GEN_ACT_KEY_DELAY;
fifo_write_now <= '1';
sel_instr_actkey <= '1';
end if;
en_instr_flag <= '1';
end if;
if (opcode = OP_AE_ENC or opcode = OP_AE_DEC) then
is_ae <= '1';
end if;
if (opcode = OP_AE_DEC or opcode = OP_DEC) then
is_decrypt <= '1';
end if;
-- if (opcode = OP_AE_ENC or opcode = OP_ENC) then
-- fifo_write_now <= '1';
-- sel_instr_dec <= '1';
-- end if;
when S_GEN_ACT_KEY_DELAY =>
--! Generate Decryption instruction word
nstate <= S_WAIT_HDR;
fifo_write_now <= '1';
sel_instr_dec <= '1';
when S_GEN_SUCC_HDR =>
--! Generate a success header
--! Note: Created in a different cycle than the read_instr
--! because we need to save the state first.
nstate <= S_WAIT_HDR;
fifo_write_pre <= '1';
sel_do_pre <= "10";
sel_sgmt_hdr_pre <= "10";
when S_WAIT_HDR =>
if (bypass_fifo_empty = '0' and fifo_full = '0') then
nstate <= S_READ_HDR;
bypass_fifo_rd <= '1';
end if;
when S_READ_HDR =>
if (instr_decrypt = '1' and (
(sgmt_stype = ST_TAG and G_CIPHERTEXT_MODE /= 2) or
(sgmt_stype = ST_NPUB) or
(G_LOADLEN_ENABLE = 1 and sgmt_stype = ST_LEN))
)
then
fifo_write_now <= '0';
else
fifo_write_now <= '1';
end if;
counter_load <= '1';
en_sgmt_status <= '1';
--! Special settings
if (G_CIPHERTEXT_MODE = 2) then
clr_size <= '1';
end if;
if (PARTIAL_LOAD = 1) then
clr_partial <= '1';
end if;
if (sgmt_stype = ST_MESSAGE or sgmt_stype = ST_CIPHER) then
sw_stype <= '1';
nstate <= S_WAIT_BDO;
elsif (sgmt_stype = ST_NSEC or sgmt_stype = ST_NSEC_CIPH) then
sw_stype <= '1';
sw_nsec <= '1';
nstate <= S_WAIT_BDO;
elsif (sgmt_stype = ST_NPUB or (G_LOADLEN_ENABLE = 1 and sgmt_stype = ST_LEN)) then
nstate <= S_WAIT_BYPASS;
if (instr_decrypt = '1') then
set_no_write <= '1';
end if;
elsif (sgmt_stype = ST_AD) then
is_ad <= '1';
nstate <= S_WAIT_BYPASS;
if (G_CIPHERTEXT_MODE = 2 and G_PAD_D = 4 and instr_decrypt = '0' and sgmt_eoi = '1') then
sel_hdr <= '1';
end if;
elsif (sgmt_stype = ST_TAG) then
if (sgmt_eoi = '1') then
set_sgmt_tag_flag <= '1';
end if;
set_sgmt_tag_passed <= '1';
if (sgmt_eoi = '1' and instr_decrypt = '1') then
if (G_CIPHERTEXT_MODE = 2) then
save_size <= '1';
end if;
nstate <= S_WAIT_MSG_AUTH;
else
nstate <= S_WAIT_HDR;
end if;
else
nstate <= S_ERROR;
end if;
when S_WAIT_BYPASS =>
if (bypass_fifo_empty = '0' and fifo_full = '0') then
counter_en <= '1';
bypass_fifo_rd <= '1';
if (sgmt_tag_flag = '0' and --! No output write if, sgmt = tag
no_write = '0') --! No output write if, sgmt = IV and decrypt = 1
then
fifo_write_pre <= '1';
end if;
if sgmt_size <= G_W/8 then
clr_status <= '1';
if msg_end = '1' then
if (G_CIPHERTEXT_MODE = 2 and G_PAD_D = 4 and instr_decrypt = '0') then
nstate <= S_GEN_CIPH_HDR;
elsif (sgmt_tag_flag = '0') and --! Special case: No message / no AD
(instr_decrypt = '0') --! Special case: No message
then
nstate <= S_GEN_TAG_HDR;
else
if (sgmt_tag_passed = '1') then
nstate <= S_WAIT_MSG_AUTH;
else
nstate <= S_WAIT_HDR;
end if;
end if;
else
nstate <= S_WAIT_HDR;
end if;
end if;
end if;
when S_WAIT_BDO =>
if (bdo_empty = '0' and fifo_full = '0') then
bdo_shf_pre <= '1';
if (G_CIPHERTEXT_MODE = 2) then
if (bdo_count /= 0) then
fifo_write_pre <= '1';
end if;
counter_en <= '1';
elsif (PARTIAL_LOAD = 1) then
if (bdo_count > 1) or
(bdo_count = 1 and is_partial = '0' and sgmt_size <= ((G_W/8)/2)) or
--(bdo_count = 1 and is_partial = '1' and sgmt_size <= (G_W/8))
(bdo_count = 1 and is_partial = '1')
then
fifo_write_pre <= '1';
counter_en <= '1';
end if;
if (bdo_count = 1 and is_partial = '0' and sgmt_size > (G_W/8)/2) or
(bdo_count = 0 and is_partial = '1' and sgmt_size > (G_W/8)/2)
then
toggle_partial <= '1';
end if;
else
fifo_write_pre <= '1';
counter_en <= '1';
end if;
sel_do_pre <= "01";
if (sgmt_size < G_W/8) then
en_zeroize <= '1';
end if;
if ((sgmt_size <= G_W/8) or
(G_CIPHERTEXT_MODE = 2 and (bdo_count = 0 or bdo_count <= G_W/8) and instr_decrypt = '1' and sgmt_size <= G_DBLK_SIZE/8) or
(PARTIAL_LOAD = 1 and bdo_count = 1 and is_partial = '0' and sgmt_size > (G_W/8)/2))
then
bdo_clr_pre <= '1';
end if;
if ((sgmt_size <= G_W/8) or
(G_CIPHERTEXT_MODE = 2 and (bdo_count = 0 or bdo_count <= G_W/8) and instr_decrypt = '1' and sgmt_size <= G_DBLK_SIZE/8))
then
if (PARTIAL_LOAD = 1 and bdo_count = 1 and is_partial = '0' and sgmt_size > (G_W/8)/2) then
--! Do nothing, stay in the same state and wait for next block
nstate <= S_WAIT_BDO;
elsif (msg_end = '1') then
if (sgmt_nsec_flag = '0') then
if instr_decrypt = '1' then
if (G_CIPHERTEXT_MODE = 2 and G_REVERSE_DBLK = 1) then
--! Special state change for PRIMATEs-APE
nstate <= S_WAIT_MSG_AUTH;
save_size <= '1';
else
nstate <= S_WAIT_HDR;
end if;
else
nstate <= S_GEN_TAG_HDR;
end if;
elsif sgmt_nsec_flag = '1' then
nstate <= S_WAIT_HDR;
else
if (G_CIPHERTEXT_MODE = 2) then
save_size <= '1';
end if;
nstate <= S_WAIT_INSTR;
end if;
else
nstate <= S_WAIT_HDR;
end if;
end if;
end if;
when S_GEN_TAG_HDR =>
nstate <= S_WRITE_TAG;
fifo_write_pre <= '1';
sel_do_pre <= "10";
counter_load_tag <= '1';
when S_GEN_CIPH_HDR =>
nstate <= S_WAIT_BDO;
fifo_write_pre <= '1';
sel_do_pre <= "10";
sel_sgmt_hdr_pre <= "01";
if (G_CIPHERTEXT_MODE = 2) then
counter_load_block <= '1';
end if;
when S_WRITE_TAG =>
if (tag_empty = '0' and fifo_full = '0') then
if (G_TAG_SIZE > G_W) then
tag_shf_pre <= '1';
end if;
sel_do_pre <= "11";
if (sgmt_size /= 0) then
counter_en <= '1';
end if;
fifo_write_pre <= '1';
if (sgmt_size <= G_W/8) then
if (G_CIPHERTEXT_MODE = 2) then
clr_hold_output <= '1';
save_size <= '1';
end if;
nstate <= S_WAIT_INSTR;
end if;
end if;
when S_WAIT_MSG_AUTH =>
if (msg_auth_done_r = '1') then
if (msg_auth_valid_r = '1') then
nstate <= S_WAIT_INSTR;
clr_hold_output <= '1';
else
restore_state <= '1';
nstate <= S_WRITE_TAG_ERROR;
end if;
end if;
when S_WRITE_TAG_ERROR =>
clr_hold_output <= '1';
sel_do_pre <= "10";
sel_sgmt_hdr_pre <= "11";
fifo_write_pre <= '1';
nstate <= S_WAIT_INSTR;
when S_ERROR =>
end case;
end process;
bdo_ready <= bdo_empty;
tag_ready <= tag_empty;
G_CIPH01: if G_CIPHERTEXT_MODE /= 2 generate
signal fifo_read_s : std_logic;
begin
process(clk)
begin
if rising_edge(clk) then
do_valid <= fifo_read_s;
end if;
end process;
fifo_read_s <= '1' when (fifo_empty = '0' and do_ready = '1' and (hold_output = '0' or fifo_unread_avail = '1')) else '0';
fifo_read <= fifo_read_s;
end generate;
G_CEXP2 : if G_CIPHERTEXT_MODE = 2 generate
type ostate_type is (S_READ_INSTR, S_WRITE_INSTR, S_READ_HDR, S_WRITE_HDR,
S_READ_DATA_INIT, S_READ_DATA, S_WRITE_LAST_WORD);
signal ostate, n_ostate : ostate_type;
signal save_instr_status : std_logic;
signal save_sgmt_status : std_logic;
signal aux_opcode : std_logic_vector( 4 -1 downto 0);
signal aux_sgmt_stype : std_logic_vector( 4 -1 downto 0);
signal aux_sgmt_eoi : std_logic;
signal aux_sgmt_eot : std_logic;
signal aux_sgmt_stype_r : std_logic_vector( 4 -1 downto 0);
signal aux_sgmt_eoi_r : std_logic;
signal aux_sgmt_eot_r : std_logic;
signal aux_instr_decrypt_r : std_logic;
signal switch_sgmt_size : std_logic;
signal switch_sgmt_eoi : std_logic;
signal aux_sgmt_cntr : std_logic_vector(CNTR_WIDTH -1 downto 0);
signal aux_sgmt_cntr_en : std_logic;
signal aux_sgmt_tag_passed : std_logic;
signal set_aux_sgmt_tag_passed : std_logic;
begin
aux_opcode <= aux_fifo_dout(G_W-12-1 downto G_W-16);
aux_sgmt_stype <= aux_fifo_dout(G_W- 8-1 downto G_W-12);
aux_sgmt_eot <= aux_fifo_dout(G_W-15-1);
aux_sgmt_eoi <= aux_fifo_dout(G_W-14-1);
sel_do2 <= switch_sgmt_size;
sel_do2_eoi <= switch_sgmt_eoi;
pState:
process(clk)
begin
if rising_edge(clk) then
if rst = '1' then
ostate <= S_READ_INSTR;
else
ostate <= n_ostate;
end if ;
if (save_instr_status = '1') then
if (aux_opcode = OP_AE_PASS) then
aux_instr_decrypt_r <= '1';
else
aux_instr_decrypt_r <= '0';
end if;
end if;
if (set_aux_sgmt_tag_passed = '1') then
aux_sgmt_tag_passed <= '1';
elsif (save_instr_status = '1') then
aux_sgmt_tag_passed <= '0';
end if;
if (save_sgmt_status = '1') then
aux_sgmt_eot_r <= aux_sgmt_eot;
aux_sgmt_eoi_r <= aux_sgmt_eoi;
aux_sgmt_stype_r <= aux_sgmt_stype;
if switch_sgmt_size = '1' then
aux_sgmt_cntr <= last_sgmt_size;
else
aux_sgmt_cntr <= aux_fifo_dout(CNTR_WIDTH-1 downto 0);
end if;
elsif aux_sgmt_cntr_en = '1' then
if (aux_sgmt_cntr >= G_W/8) then
aux_sgmt_cntr <= aux_sgmt_cntr - G_W/8;
else
aux_sgmt_cntr <= (others => '0');
end if;
end if;
end if;
end process;
pState2:
process( ostate, fifo_empty, do_ready, hold_output, last_sgmt_size, aux_opcode, aux_sgmt_tag_passed,
aux_instr_decrypt_r, aux_sgmt_eoi, aux_sgmt_eoi_r, aux_sgmt_eot, aux_sgmt_cntr,
aux_sgmt_stype, aux_sgmt_stype_r)
begin
n_ostate <= ostate;
fifo_read <= '0';
do_valid <= '0';
save_instr_status <= '0';
save_sgmt_status <= '0';
switch_sgmt_size <= '0';
switch_sgmt_eoi <= '0';
aux_sgmt_cntr_en <= '0';
set_aux_sgmt_tag_passed <= '0';
case ostate is
when S_READ_INSTR =>
if ((fifo_empty = '0') and (hold_output = '0')) then
fifo_read <= '1';
n_ostate <= S_WRITE_INSTR;
end if;
when S_WRITE_INSTR =>
save_instr_status <= '1';
if (do_ready = '1') then
do_valid <= '1';
if (aux_opcode = OP_AE_DEC or aux_opcode = OP_AE_PASS) then
n_ostate <= S_READ_HDR;
else
n_ostate <= S_READ_INSTR;
end if;
end if;
when S_READ_HDR =>
if (fifo_empty = '0') then
fifo_read <= '1';
n_ostate <= S_WRITE_HDR;
end if;
when S_WRITE_HDR =>
if (do_ready = '1') then
save_sgmt_status <= '1';
--! Switch to a real size if it's the last segment header for decryption
--! Note: For encryption, the size has been adjusted in the previous stage.
if (aux_sgmt_eoi = '1'
and (aux_sgmt_stype = ST_MESSAGE or aux_sgmt_stype = ST_CIPHER))
then
switch_sgmt_size <= '1';
end if;
if (aux_instr_decrypt_r = '1' and aux_sgmt_eot = '1'
and aux_sgmt_stype = ST_AD and last_sgmt_size = 0)
then
switch_sgmt_eoi <= '1';
end if;
if (aux_instr_decrypt_r = '1' and aux_sgmt_eoi = '1' and aux_sgmt_stype /= ST_AD) then
if ((aux_sgmt_tag_passed = '1' and last_sgmt_size = 0) or aux_sgmt_stype = ST_TAG) then
n_ostate <= S_READ_INSTR;
elsif (last_sgmt_size /= 0) then
n_ostate <= S_READ_DATA_INIT;
do_valid <= '1';
elsif (fifo_empty = '0') then
n_ostate <= S_READ_HDR;
end if;
else
if (aux_sgmt_stype = ST_TAG and aux_instr_decrypt_r = '1') then
n_ostate <= S_READ_HDR;
set_aux_sgmt_tag_passed <= '1';
else
n_ostate <= S_READ_DATA_INIT;
do_valid <= '1';
end if;
end if;
end if;
when S_READ_DATA_INIT =>
if (fifo_empty = '0') then
fifo_read <= '1';
aux_sgmt_cntr_en <= '1';
if (aux_sgmt_cntr <= G_W/8) then
n_ostate <= S_WRITE_LAST_WORD;
else
n_ostate <= S_READ_DATA;
end if;
end if;
when S_READ_DATA =>
if (fifo_empty = '0' and do_ready = '1') then
fifo_read <= '1';
aux_sgmt_cntr_en <= '1';
do_valid <= '1';
if (aux_sgmt_cntr <= G_W/8) then
n_ostate <= S_WRITE_LAST_WORD;
end if;
end if;
when S_WRITE_LAST_WORD =>
if (do_ready = '1') then
do_valid <= '1';
if ((aux_sgmt_eoi_r = '1' and aux_sgmt_stype_r = ST_TAG)
or (aux_sgmt_eoi_r = '1' and aux_instr_decrypt_r = '1' and aux_sgmt_tag_passed = '1'))
then
n_ostate <= S_READ_INSTR;
else
n_ostate <= S_WRITE_HDR;
fifo_read <= '1';
end if;
end if;
end case;
end process;
end generate;
end behavior;
| gpl-3.0 | 82651a3b1d19a886426540b579158f78 | 0.371473 | 4.371675 | false | false | false | false |
cafe-alpha/wascafe | v13/r07c_de10_20201014_abus4/wasca/synthesis/submodules/Altera_UP_SD_Card_Control_FSM.vhd | 7 | 13,102 | -- (C) 2001-2015 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
----------------------------------------------------------------------------------------------------------------
-- This is an FSM that controls the SD Card interface circuitry.
--
-- On reset, the FSM will initiate a predefined set of commands in an attempt to connect to the SD Card.
-- When successful, it will allow commands to be issued to the SD Card, otherwise it will return a signal that
-- no card is present in the SD Card slot.
--
-- NOTES/REVISIONS:
----------------------------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity Altera_UP_SD_Card_Control_FSM is
generic (
PREDEFINED_COMMAND_GET_STATUS : STD_LOGIC_VECTOR(3 downto 0) := "1001"
);
port
(
-- Clock and Reset signals
i_clock : in STD_LOGIC;
i_reset_n : in STD_LOGIC;
-- FSM Inputs
i_user_command_ready : in std_logic;
i_response_received : in STD_LOGIC;
i_response_timed_out : in STD_LOGIC;
i_response_crc_passed : in STD_LOGIC;
i_command_sent : in STD_LOGIC;
i_powerup_busy_n : in STD_LOGIC;
i_clocking_pulse_enable : in std_logic;
i_current_clock_mode : in std_logic;
i_user_message_valid : in std_logic;
i_last_cmd_was_55 : in std_logic;
i_allow_partial_rw : in std_logic;
-- FSM Outputs
o_generate_command : out STD_LOGIC;
o_predefined_command_ID : out STD_LOGIC_VECTOR(3 downto 0);
o_receive_response : out STD_LOGIC;
o_drive_CMD_line : out STD_LOGIC;
o_SD_clock_mode : out STD_LOGIC; -- 0 means slow clock for card identification, 1 means fast clock for transfer mode.
o_resetting : out std_logic;
o_card_connected : out STD_LOGIC;
o_command_completed : out std_logic;
o_clear_response_register : out std_logic;
o_enable_clock_generator : out std_logic
);
end entity;
architecture rtl of Altera_UP_SD_Card_Control_FSM is
-- Build an enumerated type for the state machine. On reset always reset the DE2 and read the state
-- of the switches.
type state_type is (s_RESET, s_WAIT_74_CYCLES, s_GENERATE_PREDEFINED_COMMAND, s_WAIT_PREDEFINED_COMMAND_TRANSMITTED, s_WAIT_PREDEFINED_COMMAND_RESPONSE,
s_GO_TO_NEXT_COMMAND, s_TOGGLE_CLOCK_FREQUENCY, s_AWAIT_USER_COMMAND, s_REACTIVATE_CLOCK,
s_GENERATE_COMMAND, s_SEND_COMMAND, s_WAIT_RESPONSE, s_WAIT_FOR_CLOCK_EDGE_BEFORE_DISABLE, s_WAIT_DEASSERT,
s_PERIODIC_STATUS_CHECK);
-- Register to hold the current state
signal current_state : state_type;
signal next_state : state_type;
-------------------
-- Local signals
-------------------
-- REGISTERED
signal SD_clock_mode, waiting_for_vdd_setup : std_logic;
signal id_sequence_step_index : std_logic_vector(3 downto 0);
signal delay_counter : std_logic_vector(6 downto 0);
signal periodic_status_check : std_logic_vector(23 downto 0);
-- UNREGISTERED
begin
-- Define state transitions.
state_transitions: process (current_state, i_command_sent, i_response_received, id_sequence_step_index,
i_response_timed_out, i_response_crc_passed, delay_counter, waiting_for_vdd_setup,
i_user_command_ready, i_clocking_pulse_enable, i_current_clock_mode,
i_user_message_valid, i_last_cmd_was_55, periodic_status_check)
begin
case current_state is
when s_RESET =>
-- Reset local registers and begin identification process.
next_state <= s_WAIT_74_CYCLES;
when s_WAIT_74_CYCLES =>
-- Wait 74 cycles before the card can be sent commands to.
if (delay_counter = "1001010") then
next_state <= s_GENERATE_PREDEFINED_COMMAND;
else
next_state <= s_WAIT_74_CYCLES;
end if;
when s_GENERATE_PREDEFINED_COMMAND =>
-- Generate a predefined command to the SD card. This is the identification process for the SD card.
next_state <= s_WAIT_PREDEFINED_COMMAND_TRANSMITTED;
when s_WAIT_PREDEFINED_COMMAND_TRANSMITTED =>
-- Send a predefined command to the SD card. This is the identification process for the SD card.
if (i_command_sent = '1') then
next_state <= s_WAIT_PREDEFINED_COMMAND_RESPONSE;
else
next_state <= s_WAIT_PREDEFINED_COMMAND_TRANSMITTED;
end if;
when s_WAIT_PREDEFINED_COMMAND_RESPONSE =>
-- Wait for a response from SD card.
if (i_response_received = '1') then
if (i_response_timed_out = '1') then
if (waiting_for_vdd_setup = '1') then
next_state <= s_GO_TO_NEXT_COMMAND;
else
next_state <= s_RESET;
end if;
else
if (i_response_crc_passed = '0') then
next_state <= s_GENERATE_PREDEFINED_COMMAND;
else
next_state <= s_GO_TO_NEXT_COMMAND;
end if;
end if;
else
next_state <= s_WAIT_PREDEFINED_COMMAND_RESPONSE;
end if;
when s_GO_TO_NEXT_COMMAND =>
-- Process the next command in the ID sequence.
if (id_sequence_step_index = PREDEFINED_COMMAND_GET_STATUS) then
next_state <= s_TOGGLE_CLOCK_FREQUENCY;
else
next_state <= s_GENERATE_PREDEFINED_COMMAND;
end if;
when s_TOGGLE_CLOCK_FREQUENCY =>
-- Now that the card has been initialized, increase the SD card clock frequency to 25MHz.
-- Wait for the clock generator to switch operating mode before proceeding further.
if (i_current_clock_mode = '1') then
next_state <= s_AWAIT_USER_COMMAND;
else
next_state <= s_TOGGLE_CLOCK_FREQUENCY;
end if;
when s_AWAIT_USER_COMMAND =>
-- Wait for the user to send a command to the SD card
if (i_user_command_ready = '1') then
next_state <= s_REACTIVATE_CLOCK;
else
-- Every 5 million cycles, or 0.1 of a second.
if (periodic_status_check = "010011000100101101000000") then
next_state <= s_PERIODIC_STATUS_CHECK;
else
next_state <= s_AWAIT_USER_COMMAND;
end if;
end if;
when s_PERIODIC_STATUS_CHECK =>
-- Update status every now and then.
next_state <= s_GENERATE_PREDEFINED_COMMAND;
when s_REACTIVATE_CLOCK =>
-- Activate the clock signal and wait 8 clock cycles.
if (delay_counter = "0001000") then
next_state <= s_GENERATE_COMMAND;
else
next_state <= s_REACTIVATE_CLOCK;
end if;
when s_GENERATE_COMMAND =>
-- Generate user command. If valid, proceed further. Otherwise, indicate that the command is invalid.
if (i_user_message_valid = '0') then
next_state <= s_WAIT_DEASSERT;
else
next_state <= s_SEND_COMMAND;
end if;
when s_SEND_COMMAND =>
-- Wait for the command to be sent.
if (i_command_sent = '1') then
next_state <= s_WAIT_RESPONSE;
else
next_state <= s_SEND_COMMAND;
end if;
when s_WAIT_RESPONSE =>
-- Wait for the SD card to respond.
if (i_response_received = '1') then
if (i_response_timed_out = '1') then
next_state <= s_WAIT_DEASSERT;
else
next_state <= s_WAIT_FOR_CLOCK_EDGE_BEFORE_DISABLE;
end if;
else
next_state <= s_WAIT_RESPONSE;
end if;
when s_WAIT_FOR_CLOCK_EDGE_BEFORE_DISABLE =>
-- Wait for a positive clock edge before you disable the clock.
if (i_clocking_pulse_enable = '1') then
next_state <= s_WAIT_DEASSERT;
else
next_state <= s_WAIT_FOR_CLOCK_EDGE_BEFORE_DISABLE;
end if;
when s_WAIT_DEASSERT =>
-- wait for the user to release command generation request.
if (i_user_command_ready = '1') then
next_state <= s_WAIT_DEASSERT;
else
if (i_last_cmd_was_55 = '1') then
next_state <= s_AWAIT_USER_COMMAND;
else
-- Send a get status command to obtain the result of sending the last command.
next_state <= s_GENERATE_PREDEFINED_COMMAND;
end if;
end if;
when others =>
-- Make sure to start in the reset state if the circuit powers up in an odd state.
next_state <= s_RESET;
end case;
end process;
-- State registers.
state_registers: process (i_clock, i_reset_n)
begin
if (i_reset_n = '0') then
current_state <= s_RESET;
elsif (rising_edge(i_clock)) then
current_state <= next_state;
end if;
end process;
-- Local FFs:
local_ffs:process ( i_clock, i_reset_n, i_powerup_busy_n, current_state,
id_sequence_step_index, i_response_received, i_response_timed_out,
i_allow_partial_rw)
begin
if (i_reset_n = '0') then
SD_clock_mode <= '0';
id_sequence_step_index <= (OTHERS => '0');
periodic_status_check <= (OTHERS => '0');
waiting_for_vdd_setup <= '0';
elsif (rising_edge(i_clock)) then
-- Set SD clock mode to 0 initially, thereby using a clock with frequency between 100 kHz and 400 kHz as
-- per SD card specifications. When the card is initialized change the clock to run at 25 MHz.
if (current_state = s_WAIT_DEASSERT) then
periodic_status_check <= (OTHERS => '0');
elsif (current_state = s_AWAIT_USER_COMMAND) then
periodic_status_check <= periodic_status_check + '1';
end if;
if (current_state = s_RESET) then
SD_clock_mode <= '0';
elsif (current_state = s_TOGGLE_CLOCK_FREQUENCY) then
SD_clock_mode <= '1';
end if;
-- Update the ID sequence step as needed.
if (current_state = s_RESET) then
id_sequence_step_index <= (OTHERS => '0');
elsif (current_state = s_GO_TO_NEXT_COMMAND) then
if ((i_powerup_busy_n = '0') and (id_sequence_step_index = "0010")) then
id_sequence_step_index <= "0001";
else
if (id_sequence_step_index = "0110") then
if (i_allow_partial_rw = '0') then
-- If partial read-write not allowed, then skip SET_BLK_LEN command - it will fail.
id_sequence_step_index <= "1000";
else
id_sequence_step_index <= "0111";
end if;
else
id_sequence_step_index <= id_sequence_step_index + '1';
end if;
end if;
elsif (current_state = s_WAIT_DEASSERT) then
if (i_last_cmd_was_55 = '0') then
-- After each command execute a get status command.
id_sequence_step_index <= PREDEFINED_COMMAND_GET_STATUS;
end if;
elsif (current_state = s_PERIODIC_STATUS_CHECK) then
id_sequence_step_index <= PREDEFINED_COMMAND_GET_STATUS;
end if;
-- Do not reset the card when SD card is having its VDD set up. Wait for it to respond, this may take some time.
if (id_sequence_step_index = "0010") then
waiting_for_vdd_setup <= '1';
elsif ((id_sequence_step_index = "0011") or (current_state = s_RESET)) then
waiting_for_vdd_setup <= '0';
end if;
end if;
end process;
-- Counter that counts to 74 to delay any commands.
initial_delay_counter: process(i_clock, i_reset_n, i_clocking_pulse_enable )
begin
if (i_reset_n = '0') then
delay_counter <= (OTHERS => '0');
elsif (rising_edge(i_clock)) then
if ((current_state = s_RESET) or (current_state = s_AWAIT_USER_COMMAND))then
delay_counter <= (OTHERS => '0');
elsif (((current_state = s_WAIT_74_CYCLES) or (current_state = s_REACTIVATE_CLOCK)) and
(i_clocking_pulse_enable = '1')) then
delay_counter <= delay_counter + '1';
end if;
end if;
end process;
-- FSM outputs.
o_SD_clock_mode <= SD_clock_mode;
o_generate_command <= '1' when ((current_state = s_GENERATE_PREDEFINED_COMMAND) or
(current_state = s_GENERATE_COMMAND))
else '0';
o_receive_response <= '1' when ((current_state = s_WAIT_PREDEFINED_COMMAND_RESPONSE) or
(current_state = s_WAIT_RESPONSE))
else '0';
o_drive_CMD_line <= '1' when ( (current_state = s_WAIT_PREDEFINED_COMMAND_TRANSMITTED) or
(current_state = s_SEND_COMMAND)) else '0';
o_predefined_command_ID <= id_sequence_step_index;
o_card_connected <= '1' when (id_sequence_step_index(3) = '1') and (
(id_sequence_step_index(2) = '1') or
(id_sequence_step_index(1) = '1') or
(id_sequence_step_index(0) = '1'))
else '0';
o_resetting <= '1' when (current_state = s_RESET) else '0';
o_command_completed <= '1' when (current_state = s_WAIT_DEASSERT) else '0';
o_enable_clock_generator <= '0' when (current_state = s_AWAIT_USER_COMMAND) else '1';
o_clear_response_register <= '1' when (current_state = s_REACTIVATE_CLOCK) else '0';
end rtl;
| gpl-2.0 | 4bca0bd0154ff8ab7a0a9299ac9380ff | 0.642039 | 3.186284 | false | false | false | false |
impedimentToProgress/UCI-BlueChip | AttackFiles/Attacks/privEsc/lib/grlib/stdlib/stdio.vhd | 2 | 8,483 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
--------------------------------------------------------------------------------
-- Package: StdIO
-- File: stdio.vhd
-- Author: Gaisler Research
-- Description: Package for common I/O functions
--------------------------------------------------------------------------------
-- pragma translate_off
library Std;
use Std.Standard.all;
use Std.TextIO.all;
library IEEE;
use IEEE.Std_Logic_1164.all;
-- pragma translate_on
package StdIO is
-- pragma translate_off
procedure HRead(
variable L: inout Line;
variable VALUE: out Std_ULogic_Vector;
variable GOOD: out Boolean);
procedure HRead(
variable L: inout Line;
variable VALUE: out Std_ULogic_Vector);
procedure HRead(
variable L: inout Line;
variable VALUE: out Std_Logic_Vector;
variable GOOD: out Boolean);
procedure HRead(
variable L: inout Line;
variable VALUE: out Std_Logic_Vector);
procedure HWrite(
variable L: inout Line;
constant VALUE: in Std_ULogic_Vector;
constant JUSTIFIED: in SIDE := RIGHT;
constant FIELD: in WIDTH := 0);
procedure HWrite(
variable L: inout Line;
constant VALUE: in Std_Logic_Vector;
constant JUSTIFIED: in SIDE := RIGHT;
constant FIELD: in WIDTH := 0);
procedure Write(
variable L: inout Line;
constant VALUE: in Std_ULogic;
constant JUSTIFIED: in SIDE := RIGHT;
constant FIELD: in WIDTH := 0);
-- pragma translate_on
end package StdIO;
package body StdIO is
-- pragma translate_off
function ToChar(N: Std_ULogic_Vector(0 to 3)) return Character is
begin
case N is
when "0000" => return('0');
when "0001" => return('1');
when "0010" => return('2');
when "0011" => return('3');
when "0100" => return('4');
when "0101" => return('5');
when "0110" => return('6');
when "0111" => return('7');
when "1000" => return('8');
when "1001" => return('9');
when "1010" => return('A');
when "1011" => return('B');
when "1100" => return('C');
when "1101" => return('D');
when "1110" => return('E');
when "1111" => return('F');
when others => return('X');
end case;
end ToChar;
function FromChar(C: Character) return Std_ULogic_Vector is
variable R: Std_ULogic_Vector(0 to 3);
begin
case C is
when '0' => R := "0000";
when '1' => R := "0001";
when '2' => R := "0010";
when '3' => R := "0011";
when '4' => R := "0100";
when '5' => R := "0101";
when '6' => R := "0110";
when '7' => R := "0111";
when '8' => R := "1000";
when '9' => R := "1001";
when 'A' => R := "1010";
when 'B' => R := "1011";
when 'C' => R := "1100";
when 'D' => R := "1101";
when 'E' => R := "1110";
when 'F' => R := "1111";
when 'a' => R := "1010";
when 'b' => R := "1011";
when 'c' => R := "1100";
when 'd' => R := "1101";
when 'e' => R := "1110";
when 'f' => R := "1111";
when others => R := "XXXX";
end case;
return R;
end FromChar;
procedure HRead(
variable L: inout Line;
variable VALUE: out Std_ULogic_Vector;
variable GOOD: out Boolean) is
variable B: Boolean;
variable C: Character;
constant SL: Integer := VALUE'Length;
variable SV: Std_ULogic_Vector(0 to SL-1);
variable S: String(1 to SL/4-1);
begin
if VALUE'Length mod 4 /= 0 then
GOOD := False;
SV := (others => 'X');
VALUE := SV;
return;
end if;
loop
Read(L, C, B);
exit when ((C /= ' ') and (C /= CR) and (C /= HT)) or (not B);
end loop;
SV(0 to 3) := FromChar(C);
if Is_X(SV(0 to 3)) or (not B) then
GOOD := False;
SV := (others => 'X');
VALUE := SV;
return;
end if;
Read(L, S, B);
if not B then
GOOD := False;
SV := (others => 'X');
VALUE := SV;
return;
end if;
for i in 1 to SL/4-1 loop
SV(4*i to 4*i+3) := FromChar(S(i));
if Is_X(SV(4*i to 4*i+3)) then
GOOD := False;
SV := (others => 'X');
VALUE := SV;
return;
end if;
end loop;
GOOD := True;
VALUE := SV;
end HRead;
procedure HRead(
variable L: inout Line;
variable VALUE: out Std_ULogic_Vector) is
variable GOOD: Boolean;
begin
HRead(L, VALUE, GOOD);
assert GOOD
report "HREAD: access incorrect";
end HRead;
procedure HRead(
variable L: inout Line;
variable VALUE: out Std_Logic_Vector;
variable GOOD: out Boolean) is
variable V: Std_ULogic_Vector(0 to Value'Length-1);
begin
HRead(L, V, GOOD);
VALUE := Std_Logic_Vector(V);
end HRead;
procedure HRead(
variable L: inout Line;
variable VALUE: out Std_Logic_Vector) is
variable GOOD: Boolean;
variable V: Std_ULogic_Vector(0 to Value'Length-1);
begin
HRead(L, V, GOOD);
VALUE := Std_Logic_Vector(V);
assert GOOD
report "HREAD: access incorrect";
end HRead;
procedure HWrite(
variable L: inout Line;
constant VALUE: in Std_ULogic_Vector;
constant JUSTIFIED: in SIDE := RIGHT;
constant FIELD: in WIDTH := 0) is
constant PL: Integer := 4-(VALUE'Length mod 4);
constant PV: Std_ULogic_Vector(1 to PL) := (others => '0');
constant TL: Integer := PL + VALUE'Length;
constant TV: Std_ULogic_Vector(0 to TL-1) := PV & Value;
variable S: String(1 to TL/4);
begin
if PL /= 4 then
for i in 0 to TL/4 -1 loop
S(i+1) := ToChar(TV(4*i to 4*i+3));
end loop;
Write(L, S(1 to TL/4), JUSTIFIED, FIELD);
else
for i in 1 to TL/4 -1 loop
S(i+1) := ToChar(TV(4*i to 4*i+3));
end loop;
Write(L, S(2 to TL/4), JUSTIFIED, FIELD);
end if;
end HWrite;
procedure HWrite(
variable L: inout Line;
constant VALUE: in Std_Logic_Vector;
constant JUSTIFIED: in SIDE := RIGHT;
constant FIELD: in WIDTH := 0) is
begin
HWrite(L, Std_ULogic_Vector(VALUE), JUSTIFIED, FIELD);
end HWrite;
procedure Write(
variable L: inout Line;
constant VALUE: in Std_ULogic;
constant JUSTIFIED: in SIDE := RIGHT;
constant FIELD: in WIDTH := 0) is
type Char_Array is array (Std_ULogic) of Character;
constant ToChar: Char_Array := "UX01ZWLH-";
begin
Write(L, ToChar(VALUE), JUSTIFIED, FIELD);
end Write;
-- pragma translate_on
end package body StdIO;
| mit | cac702715d26c152b922ca12acbfd044 | 0.488978 | 3.862933 | false | false | false | false |
michaelfivez/ascon_hardware_implementation | ascon12864_unrolled2/API_plus_CipherCore/CypherCore.vhd | 1 | 14,259 | -------------------------------------------------------------------------------
--! @project Unrolled (2) hardware implementation of Asconv1286
--! @author Michael Fivez
--! @license This project is released under the GNU Public License.
--! The license and distribution terms for this file may be
--! found in the file LICENSE in this distribution or at
--! http://www.gnu.org/licenses/gpl-3.0.txt
--! @note This is an hardware implementation made for my graduation thesis
--! at the KULeuven, in the COSIC department (year 2015-2016)
--! The thesis is titled 'Energy efficient hardware implementations of CAESAR submissions',
--! and can be found on the COSIC website (www.esat.kuleuven.be/cosic/publications)
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.ALL;
use ieee.numeric_std.all;
entity CipherCore is
generic (
G_NPUB_SIZE : integer := 128; --! Npub size (bits)
G_NSEC_SIZE : integer := 128; --! Nsec size (bits)
G_DBLK_SIZE : integer := 64; --! Data Block size (bits)
G_KEY_SIZE : integer := 128; --! Key size (bits)
G_RDKEY_SIZE : integer := 128; --! Round Key size (bits)
G_TAG_SIZE : integer := 128; --! Tag size (bits)
G_BS_BYTES : integer := 3; --! The number of bits required to hold block size expressed in bytes = log2_ceil(max(G_ABLK_SIZE,G_DBLK_SIZE)/8)
G_CTR_AD_SIZE : integer := 64; --! Maximum size for the counter that keeps track of authenticated data
G_CTR_D_SIZE : integer := 64 --! Maximum size for the counter that keeps track of data
);
port (
clk : in std_logic;
rst : in std_logic;
npub : in std_logic_vector(G_NPUB_SIZE -1 downto 0);
nsec : in std_logic_vector(G_NSEC_SIZE -1 downto 0);
key : in std_logic_vector(G_KEY_SIZE -1 downto 0);
rdkey : in std_logic_vector(G_RDKEY_SIZE -1 downto 0);
bdi : in std_logic_vector(G_DBLK_SIZE -1 downto 0);
exp_tag : in std_logic_vector(G_TAG_SIZE -1 downto 0);
len_a : in std_logic_vector(G_CTR_AD_SIZE -1 downto 0);
len_d : in std_logic_vector(G_CTR_D_SIZE -1 downto 0);
key_ready : in std_logic;
key_updated : out std_logic;
key_needs_update : in std_logic;
rdkey_ready : in std_logic;
rdkey_read : out std_logic;
npub_ready : in std_logic;
npub_read : out std_logic;
nsec_ready : in std_logic;
nsec_read : out std_logic;
bdi_ready : in std_logic;
bdi_proc : in std_logic;
bdi_ad : in std_logic;
bdi_nsec : in std_logic;
bdi_pad : in std_logic;
bdi_decrypt : in std_logic;
bdi_eot : in std_logic;
bdi_eoi : in std_logic;
bdi_read : out std_logic;
bdi_size : in std_logic_vector(G_BS_BYTES -1 downto 0);
bdi_valid_bytes : in std_logic_vector(G_DBLK_SIZE/8 -1 downto 0);
bdi_pad_loc : in std_logic_vector(G_DBLK_SIZE/8 -1 downto 0);
bdi_nodata : in std_logic;
exp_tag_ready : in std_logic;
bdo_ready : in std_logic;
bdo_write : out std_logic;
bdo : out std_logic_vector(G_DBLK_SIZE -1 downto 0);
bdo_size : out std_logic_vector(G_BS_BYTES+1 -1 downto 0);
bdo_nsec : out std_logic;
tag_ready : in std_logic;
tag_write : out std_logic;
tag : out std_logic_vector(G_TAG_SIZE -1 downto 0);
msg_auth_done : out std_logic;
msg_auth_valid : out std_logic
);
end entity CipherCore;
architecture structure of CipherCore is
-- Registers
signal keyreg,npubreg : std_logic_vector(127 downto 0);
-- Control signals AsconCore
signal AsconStart : std_logic;
signal AsconMode : std_logic_vector(3 downto 0);
signal AsconBusy : std_logic;
signal AsconSize : std_logic_vector(2 downto 0);
signal AsconInput : std_logic_vector(63 downto 0);
-- Internal Datapath signals
signal AsconOutput : std_logic_vector(127 downto 0);
begin
-- Morus_core entity
AsconCore : entity work.Ascon_StateUpdate port map(clk,rst,AsconStart,AsconMode,AsconSize,npubreg,keyreg,AsconInput,AsconBusy,AsconOutput);
----------------------------------------
------ DataPath for CipherCore ---------
----------------------------------------
datapath: process(AsconOutput,exp_tag,bdi,AsconInput) is
begin
-- Connect signals to the MorusCore
AsconInput <= bdi;
tag <= AsconOutput;
bdo <= AsconOutput(63 downto 0);
if AsconOutput = exp_tag then
msg_auth_valid <= '1';
else
msg_auth_valid <= '0';
end if;
end process datapath;
----------------------------------------
------ ControlPath for CipherCore ------
----------------------------------------
fsm: process(clk, rst) is
type state_type is (IDLE,INIT_1,INIT_2,PROCESSING,RUN_CIPHER_1,RUN_CIPHER_2,RUN_CIPHER_3,RUN_CIPHER_4,TAG_1,TAG_2);
variable CurrState : state_type := IDLE;
variable firstblock : std_logic;
variable lastblock : std_logic_vector(1 downto 0);
variable afterRunning : std_logic_vector(2 downto 0);
begin
if(clk = '1' and clk'event) then
if rst = '1' then -- synchornous reset
key_updated <= '0';
CurrState := IDLE;
firstblock := '0';
keyreg <= (others => '0');
npubreg <= (others => '0');
AsconMode <= (others => '0'); -- the mode is a register
afterRunning := (others => '0');
else
-- registers above in reset are used
-- Standard values of the control signals are zero
AsconStart <= '0';
bdi_read <= '0';
msg_auth_done <= '0';
bdo_write <= '0';
bdo_size <= "1000";
tag_write <= '0';
npub_read <= '0';
AsconSize <= (others => '0');
FsmLogic: case CurrState is
when IDLE =>
-- if key_needs_update = '1' then -- Key needs updating
-- if key_ready = '1' then
-- key_updated <= '1';
-- keyreg <= key;
-- CurrState := IDLE;
-- else
-- CurrState := IDLE;
-- end if;
if key_needs_update = '1' and key_ready = '1' then -- Key needs updating
key_updated <= '1';
keyreg <= key;
CurrState := IDLE;
elsif bdi_proc = '1' and npub_ready = '1' then -- start of processing
CurrState := INIT_1;
npubreg <= npub;
npub_read <= '1';
AsconMode <= "0010"; -- Mode: initialization
AsconStart <= '1';
else
CurrState := IDLE;
end if;
when INIT_1 =>
if AsconBusy = '1' then
CurrState := INIT_2; -- to INIT_2
else
AsconStart <= '1';
CurrState := INIT_1; -- to INIT_1
end if;
when INIT_2 =>
if AsconBusy = '0' then
CurrState := PROCESSING; -- to PROCESSING
firstblock := '1';
lastblock := "00";
else
CurrState := INIT_2; -- to INIT_2
end if;
-- EVEN SIMPLIFY THIS AFTER YOU SEE IF WORKS
when PROCESSING =>
if lastblock(1) = '1' then -- Generate the Tag
AsconMode <= "0001";
AsconStart <= '1';
CurrState := TAG_1;
elsif bdi_ready = '1' then
if firstblock = '1' and bdi_ad = '0' then -- No associative data (and return in function)
-- SEP_CONST
AsconMode <= "0011";
AsconStart <= '1';
CurrState := PROCESSING;
elsif bdi_ad = '1' then
if bdi_eot = '0' then
-- AD_PROCESS
AsconMode <= "0000";
AsconStart <= '1';
afterRunning := "000";
CurrState := RUN_CIPHER_1;
elsif bdi_eoi = '0' then
if bdi_size = "000" then
-- AD_PROCESS + case2 + SEP_CONST
AsconMode <= "0000";
AsconStart <= '1';
afterRunning := "001";
CurrState := RUN_CIPHER_1;
else
-- AD_PROCESS + SEP_CONST
AsconMode <= "0000";
AsconStart <= '1';
afterRunning := "010";
CurrState := RUN_CIPHER_1;
end if;
else
if bdi_size = "000" then
-- AD_PROCESS + case2 + SEP_CONST + case1
AsconMode <= "0000";
AsconStart <= '1';
afterRunning := "101";
CurrState := RUN_CIPHER_1;
else
-- AD_PROCESS + SEP_CONST + case1
AsconMode <= "0000";
AsconStart <= '1';
afterRunning := "110";
CurrState := RUN_CIPHER_1;
end if;
end if;
else
if bdi_decrypt = '0' then
if bdi_eot = '0' then
-- ENCRYPT
AsconMode <= "0110";
AsconStart <= '1';
afterRunning := "011";
CurrState := RUN_CIPHER_1;
elsif bdi_size = "000" then
-- ENCRYPT + case1
AsconMode <= "0110";
AsconStart <= '1';
afterRunning := "100";
CurrState := RUN_CIPHER_1;
else
-- LAST_BLOCK_ENCRYPT
bdi_read <= '1';
AsconMode <= "0111";
AsconStart <= '1';
afterRunning := "011";
CurrState := RUN_CIPHER_4;
end if;
else
if bdi_eot = '0' then
-- DECRYPT
AsconMode <= "0100";
AsconStart <= '1';
afterRunning := "011";
CurrState := RUN_CIPHER_1;
elsif bdi_size = "000" then
-- DECRYPT + case1
AsconMode <= "0100";
AsconStart <= '1';
afterRunning := "100";
CurrState := RUN_CIPHER_1;
else
-- LAST_BLOCK_DECRYPT
bdi_read <= '1';
AsconMode <= "0101";
AsconStart <= '1';
AsconSize <= bdi_size;
afterRunning := "011";
CurrState := RUN_CIPHER_4;
end if;
end if;
end if;
-- check if tag after (eoi, with special case when no associative data:
-- This is needed, because if no associative data, it will do it's thing and then still the message block is
-- left to be processed
if firstblock = '1' and bdi_ad = '0' then -- lastblock will be set next return in the function
lastblock := "00";
elsif bdi_eoi = '1' and bdi_decrypt = '0' then -- the one after is tag encryption
lastblock := "10";
elsif bdi_eoi = '1' then -- the one after is tag decryption
lastblock := "11";
end if;
-- not firstblock anymore :
firstblock := '0';
end if;
when RUN_CIPHER_1 =>
if AsconBusy = '1' then
CurrState := RUN_CIPHER_2;
bdi_read <= '1';
else
AsconStart <= '1';
CurrState := RUN_CIPHER_1;
end if;
when RUN_CIPHER_3 =>
if AsconBusy = '1' then
CurrState := RUN_CIPHER_2;
else
AsconStart <= '1';
CurrState := RUN_CIPHER_3;
end if;
when RUN_CIPHER_4 =>
if AsconBusy = '1' then
CurrState := RUN_CIPHER_2;
else
CurrState := RUN_CIPHER_4;
end if;
when RUN_CIPHER_2 =>
if AsconBusy = '0' then
-- logic here:
-- a simple variable is used for the cases where after the cipher something special has to be done:
-- activating authregister after associative data = 1
-- resetting of blocknumber after last associative data = 2 (so also do 1's job)
-- giving of output after encryption/decryption = 3 for encryption, 4 for decryption
-- activating checksum after decription of message = 4
-- special giving of output after padded encryption/decryption = 5 and 6 (determines output_sel), also wait with bdi_read
AfterRunLogic: case afterRunning is
when "000" => -- return to IDLE
CurrState := PROCESSING;
when "001" => -- case2 and sep_cont after
AsconMode <= "1001";
AsconStart <= '1';
CurrState := RUN_CIPHER_3;
afterRunning := "010";
when "010" => -- SEPCONSTANT and return to IDLE
AsconMode <= "0011";
AsconStart <= '1';
CurrState := PROCESSING;
when "011" => -- GIVE OUTPUT and return to IDLE
if bdo_ready = '1' then
bdo_write <= '1';
CurrState := PROCESSING;
else
CurrState := RUN_CIPHER_2;
end if;
when "100" => -- GIVE OUTPUT & case1 and return to IDLE
if bdo_ready = '1' then
bdo_write <= '1';
CurrState := PROCESSING;
AsconMode <= "1000";
AsconStart <= '1';
else
CurrState := RUN_CIPHER_2;
end if;
when "101" => -- case2 and case1 and sep_cont after
AsconMode <= "1001";
AsconStart <= '1';
CurrState := RUN_CIPHER_3;
afterRunning := "110";
when "110" => -- case1 and sep_cont after
AsconMode <= "1000";
AsconStart <= '1';
CurrState := RUN_CIPHER_2;
afterRunning := "010";
when others =>
end case AfterRunLogic;
else
CurrState := RUN_CIPHER_2;
end if;
when TAG_1 =>
if AsconBusy = '1' then
CurrState := TAG_2;
else
AsconStart <= '1';
CurrState := TAG_1;
end if;
when TAG_2 =>
if AsconBusy = '0' and lastblock(0) = '0' then -- Generate Tag
if tag_ready = '1' then
tag_write <= '1';
key_updated <= '0';
CurrState := IDLE;
else
CurrState := TAG_2;
end if;
elsif AsconBusy = '0' then -- Compare Tag
if exp_tag_ready = '1' then
msg_auth_done <= '1';
key_updated <= '0';
CurrState := IDLE;
else
CurrState := TAG_2;
end if;
else
CurrState := TAG_2;
end if;
when others =>
end case FsmLogic;
end if;
end if;
end process fsm;
end architecture structure;
| gpl-3.0 | c15e55e39eb18b0fc5b50b1354f3bf38 | 0.519461 | 3.387741 | false | false | false | false |
impedimentToProgress/UCI-BlueChip | AttackFiles/Attacks/privEsc/lib/tech/axcelerator/components/axcelerator_vtables.vhd | 2 | 4,887 | library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
package VTABLES is
CONSTANT L : VitalTableSymbolType := '0';
CONSTANT H : VitalTableSymbolType := '1';
CONSTANT x : VitalTableSymbolType := '-';
CONSTANT S : VitalTableSymbolType := 'S';
CONSTANT R : VitalTableSymbolType := '/';
CONSTANT U : VitalTableSymbolType := 'X';
CONSTANT V : VitalTableSymbolType := 'B'; -- valid clock signal (non-rising)
-- CLR_ipd, CLK_delayed, Q_zd, D, E_delayed, PRE_ipd, CLK_ipd
CONSTANT DFEG_Q_tab : VitalStateTableType := (
( L, x, x, x, x, x, x, x, L ),
( H, L, H, H, x, x, H, x, H ),
( H, L, H, x, H, x, H, x, H ),
( H, L, x, H, L, x, H, x, H ),
( H, H, x, x, x, H, x, x, S ),
( H, x, x, x, x, L, x, x, H ),
( H, x, x, x, x, H, L, x, S ),
( x, L, L, L, x, H, H, x, L ),
( x, L, L, x, H, H, H, x, L ),
( x, L, x, L, L, H, H, x, L ),
( U, x, L, x, x, H, x, x, L ),
( H, x, H, x, x, U, x, x, H ));
-- CLR_ipd, CLK_delayed, T_delayed, Q_zd, CLK_ipd
CONSTANT tflipflop_Q_tab : VitalStateTableType := (
( L, x, x, x, x, x, L ),
( H, L, L, H, H, x, H ),
( H, L, H, L, H, x, H ),
( H, H, x, x, x, x, S ),
( H, x, x, x, L, x, S ),
( x, L, L, L, H, x, L ),
( x, L, H, H, H, x, L ));
-- CLR_ipd, CLK_delayed, PRE_delayed,K_delayed,J_delayed, Q_zd, CLK_ipd
CONSTANT jkflipflop_Q_tab : VitalStateTableType := (
( L, x, H, x, x, x, x, x, U ),
( L, x, L, x, x, x, x, x, L ),
( H, L, x, L, H, x, H, x, H ),
( H, L, x, L, x, H, H, x, H ),
( H, L, x, x, H, L, H, x, H ),
( H, H, L, x, x, x, x, x, S ),
( H, x, L, x, x, x, L, x, S ),
( H, x, H, x, x, x, x, x, H ),
( x, L, L, H, L, x, H, x, L ),
( x, L, L, H, x, H, H, x, L ),
( x, L, L, x, L, L, H, x, L ),
( U, x, L, x, x, L, x, x, L ),
( H, x, U, x, x, H, x, x, H ));
CONSTANT JKF2A_Q_tab : VitalStateTableType := (
( L, x, x, x, x, x, x, L ),
( H, L, L, H, x, H, x, H ),
( H, L, L, x, H, H, x, H ),
( H, L, x, H, L, H, x, H ),
( H, H, x, x, x, x, x, S ),
( H, x, x, x, x, L, x, S ),
( x, L, H, L, x, H, x, L ),
( x, L, H, x, H, H, x, L ),
( x, L, x, L, L, H, x, L ),
( U, x, x, x, L, x, x, L ));
CONSTANT JKF3A_Q_tab : VitalStateTableType := (
( L, H, L, x, H, H, x, L ),
( L, H, x, H, H, H, x, L ),
( L, L, H, x, x, H, x, H ),
( L, L, x, H, x, H, x, H ),
( L, x, L, L, H, H, x, L ),
( L, x, H, L, x, H, x, H ),
( H, x, x, x, H, x, x, S ),
( x, x, x, x, L, x, x, H ),
( x, x, x, x, H, L, x, S ),
( x, x, x, H, U, x, x, H ));
CONSTANT dlatch_DLE3B_Q_tab : VitalStateTableType := (
( x, x, x, H, x, H ), --active high preset
( H, x, x, L, x, S ), --latch
( x, H, x, L, x, S ), --latch
( L, L, H, L, x, H ), --transparent
( L, L, L, L, x, L ), --transparent
( U, x, H, L, H, H ), --o/p mux pessimism
( x, U, H, L, H, H ), --o/p mux pessimism
( U, x, L, L, L, L ), --o/p mux pessimism
( x, U, L, L, L, L ), --o/p mux pessimism
( L, L, H, U, x, H ), --PRE==X
( H, x, x, U, H, H ), --PRE==X
( x, H, x, U, H, H ), --PRE==X
( L, U, H, U, H, H ), --PRE==X
( U, L, H, U, H, H ), --PRE==X
( U, U, H, U, H, H )); --PRE==X
--G, E, D, P, Qn, Qn+1
CONSTANT dlatch_DLE2B_Q_tab : VitalStateTableType := (
( L, x, x, x, x, L ), --active low clear
( H, H, x, x, x, S ), --latch
( H, x, H, x, x, S ), --latch
( H, L, L, H, x, H ), --transparent
( H, L, L, L, x, L ), --transparent
( H, x, x, L, L, L ), --o/p mux pessimism
( H, x, x, H, H, H ), --o/p mux pessimism
( U, x, x, L, L, L ), --CLR==X, o/p mux pessimism
( U, H, x, x, L, L ), --CLR==X, o/p mux pessimism, latch
( U, x, H, x, L, L ), --CLR==X, o/p mux pessimism, latch
( U, L, L, L, x, L )); --CLR==X, i/p mux pessimism
--C, G, E, D, Qn, Qn+1
CONSTANT dlatch_DL2C_Q_tab : VitalStateTableType := (
( L, x, x, x, x, L ), --active low clear
( H, x, x, H, x, H ), --active high preset
( H, H, x, L, x, S ), --latch
( H, L, L, L, x, L ), --transparent
( U, L, L, L, x, L ), --CLR==U
( U, H, x, L, L, L ), --CLR==U
( x, U, L, L, L, L ), --CLR,G==U
( H, U, H, x, H, H ), --PRE==U/x,G==U
( H, L, H, x, x, H ), --PRE==U/x
( H, H, x, U, H, H )); --PRE==U
--CLR, G, D, PRE, Qn, Qn+1
end VTABLES;
--------------------- END OF VITABLE TABLE SECTION ----------------
| mit | 0574f6a8006f93dfdd727f7f1ae59c26 | 0.376304 | 1.789454 | false | false | false | false |
impedimentToProgress/UCI-BlueChip | AttackFiles/Attacks/privEsc/lib/gaisler/leon3/mmutlbcam.vhd | 2 | 6,912 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: mmutlbcam
-- File: mmutlbcam.vhd
-- Author: Konrad Eisele, Jiri Gaisler, Gaisler Research
-- Description: MMU TLB logic
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
library gaisler;
use gaisler.libiu.all;
use gaisler.libcache.all;
use gaisler.leon3.all;
use gaisler.mmuconfig.all;
use gaisler.mmuiface.all;
entity mmutlbcam is
generic (
tlb_type : integer range 0 to 3 := 1
);
port (
rst : in std_logic;
clk : in std_logic;
tlbcami : in mmutlbcam_in_type;
tlbcamo : out mmutlbcam_out_type
);
end mmutlbcam;
architecture rtl of mmutlbcam is
constant M_TLB_FASTWRITE : integer range 0 to 3 := conv_integer(conv_std_logic_vector(tlb_type,2) and conv_std_logic_vector(2,2)); -- fast writebuffer
type tlbcam_rtype is record
btag : tlbcam_reg;
end record;
signal r,c : tlbcam_rtype;
begin
p0: process (rst, r, tlbcami)
variable v : tlbcam_rtype;
variable hm, hf : std_logic;
variable h_i1, h_i2, h_i3, h_c : std_logic;
variable h_l2, h_l3 : std_logic;
variable h_su_cnt : std_logic;
variable blvl : std_logic_vector(1 downto 0);
variable bet : std_logic_vector(1 downto 0);
variable bsu : std_logic;
variable blvl_decode : std_logic_vector(3 downto 0);
variable bet_decode : std_logic_vector(3 downto 0);
variable ref, modified : std_logic;
variable tlbcamo_pteout : std_logic_vector(31 downto 0);
variable tlbcamo_LVL : std_logic_vector(1 downto 0);
variable tlbcamo_NEEDSYNC : std_logic;
variable tlbcamo_WBNEEDSYNC : std_logic;
begin
v := r;
--#init
h_i1 := '0'; h_i2 := '0'; h_i3 := '0'; h_c := '0';
hm := '0';
hf := r.btag.VALID;
blvl := r.btag.LVL;
bet := r.btag.ET;
bsu := r.btag.SU;
bet_decode := decode(bet);
blvl_decode := decode(blvl);
ref := r.btag.R;
modified := r.btag.M;
tlbcamo_pteout := (others => '0');
tlbcamo_lvl := (others => '0');
-- prepare tag comparision
if (r.btag.I1 = tlbcami.tagin.I1) then h_i1 := '1'; else h_i1 := '0'; end if;
if (r.btag.I2 = tlbcami.tagin.I2) then h_i2 := '1'; else h_i2 := '0'; end if;
if (r.btag.I3 = tlbcami.tagin.I3) then h_i3 := '1'; else h_i3 := '0'; end if;
if (r.btag.CTX = tlbcami.tagin.CTX) then h_c := '1'; else h_c := '0'; end if;
-- #level 2 hit (segment)
h_l2 := h_i1 and h_i2 ;
-- #level 3 hit (page)
h_l3 := h_i1 and h_i2 and h_i3;
-- # context + su
h_su_cnt := h_c or bsu;
--# translation (match) op
case blvl is
when LVL_PAGE => hm := h_l3 and h_c and r.btag.VALID;
when LVL_SEGMENT => hm := h_l2 and h_c and r.btag.VALID;
when LVL_REGION => hm := h_i1 and h_c and r.btag.VALID;
when LVL_CTX => hm := h_c and r.btag.VALID;
when others => hm := 'X';
end case;
--# translation: update ref/mod bit
tlbcamo_NEEDSYNC := '0';
if (tlbcami.trans_op and hm ) = '1' then
v.btag.R := '1';
v.btag.M := r.btag.M or tlbcami.tagin.M;
tlbcamo_NEEDSYNC := (not r.btag.R) or (tlbcami.tagin.M and (not r.btag.M)); -- cam: ref/modified changed, write back synchronously
end if;
tlbcamo_WBNEEDSYNC := '0';
if ( hm ) = '1' then
tlbcamo_WBNEEDSYNC := (not r.btag.R) or (tlbcami.tagin.M and (not r.btag.M)); -- cam: ref/modified changed, write back synchronously
end if;
--# flush operation
-- tlbcam only stores PTEs, tlb does not store PTDs
case tlbcami.tagin.TYP is
when FPTY_PAGE => -- page
hf := hf and h_su_cnt and h_l3 and (blvl_decode(0)); -- only level 3 (page)
when FPTY_SEGMENT => -- segment
hf := hf and h_su_cnt and h_l2 and (blvl_decode(0) or blvl_decode(1)); -- only level 2+3 (segment,page)
when FPTY_REGION => -- region
hf := hf and h_su_cnt and h_i1 and (not blvl_decode(3)); -- only level 1+2+3 (region,segment,page)
when FPTY_CTX => -- context
hf := hf and (h_c and (not bsu));
when FPTY_N => -- entire
when others =>
hf := '0';
end case;
--# flush: invalidate on flush hit
--if (tlbcami.flush_op and hf ) = '1' then
if (tlbcami.flush_op ) = '1' then
v.btag.VALID := '0';
end if;
--# write op
if ( tlbcami.write_op = '1' ) then
v.btag := tlbcami.tagwrite;
end if;
--# reset
if (rst = '0' or tlbcami.mmuen = '0') then
v.btag.VALID := '0';
end if;
tlbcamo_pteout(PTE_PPN_U downto PTE_PPN_D) := r.btag.PPN;
tlbcamo_pteout(PTE_C) := r.btag.C;
tlbcamo_pteout(PTE_M) := r.btag.M;
tlbcamo_pteout(PTE_R) := r.btag.R;
tlbcamo_pteout(PTE_ACC_U downto PTE_ACC_D) := r.btag.ACC;
tlbcamo_pteout(PT_ET_U downto PT_ET_D) := r.btag.ET;
tlbcamo_LVL(1 downto 0) := r.btag.LVL;
--# drive signals
tlbcamo.pteout <= tlbcamo_pteout;
tlbcamo.LVL <= tlbcamo_LVL;
--tlbcamo.hit <= (tlbcami.trans_op and hm) or (tlbcami.flush_op and hf);
tlbcamo.hit <= (hm) or (tlbcami.flush_op and hf);
tlbcamo.ctx <= r.btag.CTX; -- for diagnostic only
tlbcamo.valid <= r.btag.VALID; -- for diagnostic only
tlbcamo.vaddr <= r.btag.I1 & r.btag.I2 & r.btag.I3 & "000000000000"; -- for diagnostic only
tlbcamo.NEEDSYNC <= tlbcamo_NEEDSYNC;
tlbcamo.WBNEEDSYNC <= tlbcamo_WBNEEDSYNC;
c <= v;
end process p0;
p1: process (clk, c)
begin if rising_edge(clk) then r <= c; end if;
end process p1;
end rtl;
| mit | 460cf0ff83a8d7b3d21fd92858e16e62 | 0.56033 | 3.324675 | false | false | false | false |
impedimentToProgress/UCI-BlueChip | AttackFiles/Attacks/memAttack/lib/techmap/unisim/ddr_phy_unisim.vhd | 1 | 68,466 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: various
-- File: clkgen_xilinx.vhd
-- Author: Jiri Gaisler, Gaisler Research
-- Description: DDR PHY for Virtex-2 and Virtex-4
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.stdlib.all;
-- pragma translate_off
library unisim;
use unisim.BUFG;
use unisim.DCM;
use unisim.ODDR;
use unisim.FD;
use unisim.IDDR;
-- pragma translate_on
library techmap;
use techmap.gencomp.all;
------------------------------------------------------------------
-- Virtex4 DDR PHY -----------------------------------------------
------------------------------------------------------------------
entity virtex4_ddr_phy is
generic (MHz : integer := 100; rstdelay : integer := 200;
dbits : integer := 16; clk_mul : integer := 2 ;
clk_div : integer := 2; rskew : integer := 0);
port (
rst : in std_ulogic;
clk : in std_logic; -- input clock
clkout : out std_ulogic; -- system clock
lock : out std_ulogic; -- DCM locked
ddr_clk : out std_logic_vector(2 downto 0);
ddr_clkb : out std_logic_vector(2 downto 0);
ddr_clk_fb_out : out std_logic;
ddr_clk_fb : in std_logic;
ddr_cke : out std_logic_vector(1 downto 0);
ddr_csb : out std_logic_vector(1 downto 0);
ddr_web : out std_ulogic; -- ddr write enable
ddr_rasb : out std_ulogic; -- ddr ras
ddr_casb : out std_ulogic; -- ddr cas
ddr_dm : out std_logic_vector (dbits/8-1 downto 0); -- ddr dm
ddr_dqs : inout std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
ddr_ad : out std_logic_vector (13 downto 0); -- ddr address
ddr_ba : out std_logic_vector (1 downto 0); -- ddr bank address
ddr_dq : inout std_logic_vector (dbits-1 downto 0); -- ddr data
addr : in std_logic_vector (13 downto 0); -- data mask
ba : in std_logic_vector ( 1 downto 0); -- data mask
dqin : out std_logic_vector (dbits*2-1 downto 0); -- ddr input data
dqout : in std_logic_vector (dbits*2-1 downto 0); -- ddr input data
dm : in std_logic_vector (dbits/4-1 downto 0); -- data mask
oen : in std_ulogic;
dqs : in std_ulogic;
dqsoen : in std_ulogic;
rasn : in std_ulogic;
casn : in std_ulogic;
wen : in std_ulogic;
csn : in std_logic_vector(1 downto 0);
cke : in std_logic_vector(1 downto 0)
);
end;
architecture rtl of virtex4_ddr_phy is
component DCM
generic (
CLKDV_DIVIDE : real := 2.0;
CLKFX_DIVIDE : integer := 1;
CLKFX_MULTIPLY : integer := 4;
CLKIN_DIVIDE_BY_2 : boolean := false;
CLKIN_PERIOD : real := 10.0;
CLKOUT_PHASE_SHIFT : string := "NONE";
CLK_FEEDBACK : string := "1X";
DESKEW_ADJUST : string := "SYSTEM_SYNCHRONOUS";
DFS_FREQUENCY_MODE : string := "LOW";
DLL_FREQUENCY_MODE : string := "LOW";
DSS_MODE : string := "NONE";
DUTY_CYCLE_CORRECTION : boolean := true;
FACTORY_JF : bit_vector := X"C080";
PHASE_SHIFT : integer := 0;
STARTUP_WAIT : boolean := false
);
port (
CLKFB : in std_logic;
CLKIN : in std_logic;
DSSEN : in std_logic;
PSCLK : in std_logic;
PSEN : in std_logic;
PSINCDEC : in std_logic;
RST : in std_logic;
CLK0 : out std_logic;
CLK90 : out std_logic;
CLK180 : out std_logic;
CLK270 : out std_logic;
CLK2X : out std_logic;
CLK2X180 : out std_logic;
CLKDV : out std_logic;
CLKFX : out std_logic;
CLKFX180 : out std_logic;
LOCKED : out std_logic;
PSDONE : out std_logic;
STATUS : out std_logic_vector (7 downto 0));
end component;
component BUFG port (O : out std_logic; I : in std_logic); end component;
component ODDR
generic
( DDR_CLK_EDGE : string := "OPPOSITE_EDGE";
-- INIT : bit := '0';
SRTYPE : string := "SYNC");
port
(
Q : out std_ulogic;
C : in std_ulogic;
CE : in std_ulogic;
D1 : in std_ulogic;
D2 : in std_ulogic;
R : in std_ulogic;
S : in std_ulogic
);
end component;
component FD
generic ( INIT : bit := '0');
port ( Q : out std_ulogic;
C : in std_ulogic;
D : in std_ulogic);
end component;
component IDDR
generic ( DDR_CLK_EDGE : string := "SAME_EDGE";
INIT_Q1 : bit := '0';
INIT_Q2 : bit := '0';
SRTYPE : string := "ASYNC");
port
( Q1 : out std_ulogic;
Q2 : out std_ulogic;
C : in std_ulogic;
CE : in std_ulogic;
D : in std_ulogic;
R : in std_ulogic;
S : in std_ulogic);
end component;
signal vcc, gnd, dqsn, oe, lockl : std_ulogic;
signal ddr_clk_fb_outr : std_ulogic;
signal ddr_clk_fbl, fbclk : std_ulogic;
signal ddr_rasnr, ddr_casnr, ddr_wenr : std_ulogic;
signal ddr_clkl, ddr_clkbl : std_logic_vector(2 downto 0);
signal ddr_csnr, ddr_ckenr, ckel : std_logic_vector(1 downto 0);
signal clk_0ro, clk_90ro, clk_180ro, clk_270ro : std_ulogic;
signal clk_0r, clk_90r, clk_180r, clk_270r : std_ulogic;
signal clk0r, clk90r, clk180r, clk270r : std_ulogic;
signal locked, vlockl, ddrclkfbl, dllfb : std_ulogic;
signal ddr_dqin : std_logic_vector (dbits-1 downto 0); -- ddr data
signal ddr_dqout : std_logic_vector (dbits-1 downto 0); -- ddr data
signal ddr_dqoen : std_logic_vector (dbits-1 downto 0); -- ddr data
signal ddr_adr : std_logic_vector (13 downto 0); -- ddr address
signal ddr_bar : std_logic_vector (1 downto 0); -- ddr address
signal ddr_dmr : std_logic_vector (dbits/8-1 downto 0); -- ddr address
signal ddr_dqsin : std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
signal ddr_dqsoen : std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
signal ddr_dqsoutl : std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
signal dqsdel, dqsclk : std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
signal da : std_logic_vector (dbits-1 downto 0); -- ddr data
signal dqinl : std_logic_vector (dbits-1 downto 0); -- ddr data
signal dllrst : std_logic_vector(0 to 3);
signal dll0rst, dll2rst : std_logic_vector(0 to 3);
signal mlock, mclkfb, mclk, mclkfx, mclk0 : std_ulogic;
signal rclk270b, rclk90b, rclk0b : std_ulogic;
signal rclk270, rclk90, rclk0 : std_ulogic;
constant DDR_FREQ : integer := (MHz * clk_mul) / clk_div;
attribute keep : boolean;
attribute keep of rclk90b : signal is true;
attribute syn_keep : boolean;
attribute syn_keep of rclk90b : signal is true;
attribute syn_preserve : boolean;
attribute syn_preserve of rclk90b : signal is true;
begin
oe <= not oen;
vcc <= '1'; gnd <= '0';
-- Optional DDR clock multiplication
noclkscale : if clk_mul = clk_div generate
mclk <= clk;
end generate;
clkscale : if clk_mul /= clk_div generate
rstdel : process (clk, rst)
begin
if rst = '0' then dll0rst <= (others => '1');
elsif rising_edge(clk) then
dll0rst <= dll0rst(1 to 3) & '0';
end if;
end process;
bufg0 : BUFG port map (I => mclkfx, O => mclk);
bufg1 : BUFG port map (I => mclk0, O => mclkfb);
dllm : DCM
generic map (CLKFX_MULTIPLY => clk_mul, CLKFX_DIVIDE => clk_div)
port map ( CLKIN => clk, CLKFB => mclkfb, DSSEN => gnd, PSCLK => gnd,
PSEN => gnd, PSINCDEC => gnd, RST => dll0rst(0), CLK0 => mclk0,
LOCKED => mlock, CLKFX => mclkfx );
end generate;
-- DDR clock generation
ddrref_pad : clkpad generic map (tech => virtex4)
port map (ddr_clk_fb, ddrclkfbl);
bufg1 : BUFG port map (I => clk_0ro, O => clk_0r);
-- bufg2 : BUFG port map (I => clk_90ro, O => clk_90r);
clk_90r <= not clk_270r;
-- bufg3 : BUFG port map (I => clk_180ro, O => clk_180r);
clk_180r <= not clk_0r;
bufg4 : BUFG port map (I => clk_270ro, O => clk_270r);
clkout <= clk_270r; clk0r <= clk_270r; clk90r <= clk_0r;
clk180r <= clk_90r; clk270r <= clk_180r;
dllfb <= clk_0r;
dll : DCM generic map (CLKFX_MULTIPLY => 2, CLKFX_DIVIDE => 2)
port map ( CLKIN => mclk, CLKFB => dllfb, DSSEN => gnd, PSCLK => gnd,
PSEN => gnd, PSINCDEC => gnd, RST => dllrst(0), CLK0 => clk_0ro,
CLK90 => clk_90ro, CLK180 => clk_180ro, CLK270 => clk_270ro,
LOCKED => lockl);
rstdel : process (mclk, rst)
begin
if rst = '0' then dllrst <= (others => '1');
elsif rising_edge(mclk) then
dllrst <= dllrst(1 to 3) & '0';
end if;
end process;
rdel : if rstdelay /= 0 generate
rcnt : process (clk_0r)
variable cnt : std_logic_vector(15 downto 0);
variable vlock, co : std_ulogic;
begin
if rising_edge(clk_0r) then
co := cnt(15);
vlockl <= vlock;
if lockl = '0' then
cnt := conv_std_logic_vector(rstdelay*DDR_FREQ, 16); vlock := '0';
else
if vlock = '0' then
cnt := cnt -1; vlock := cnt(15) and not co;
end if;
end if;
end if;
if lockl = '0' then
vlock := '0';
end if;
end process;
end generate;
locked <= lockl when rstdelay = 0 else vlockl;
lock <= locked;
-- Generate external DDR clock
fbdclk0r : ODDR port map ( Q => ddr_clk_fb_outr, C => clk90r, CE => vcc,
D1 => vcc, D2 => gnd, R => gnd, S => gnd);
fbclk_pad : outpad generic map (tech => virtex4, level => sstl2_i)
port map (ddr_clk_fb_out, ddr_clk_fb_outr);
ddrclocks : for i in 0 to 2 generate
dclk0r : ODDR port map ( Q => ddr_clkl(i), C => clk90r, CE => vcc,
D1 => vcc, D2 => gnd, R => gnd, S => gnd);
ddrclk_pad : outpad generic map (tech => virtex4, level => sstl2_i)
port map (ddr_clk(i), ddr_clkl(i));
dclk0rb : ODDR port map ( Q => ddr_clkbl(i), C => clk90r, CE => vcc,
D1 => gnd, D2 => vcc, R => gnd, S => gnd);
ddrclkb_pad : outpad generic map (tech => virtex4, level => sstl2_i)
port map (ddr_clkb(i), ddr_clkbl(i));
end generate;
ddrbanks : for i in 0 to 1 generate
csn0gen : ODDR generic map (DDR_CLK_EDGE => "SAME_EDGE")
port map ( Q => ddr_csnr(i), C => clk0r, CE => vcc,
D1 => csn(i), D2 => csn(i), R => gnd, S => gnd);
csn0_pad : outpad generic map (tech => virtex4, level => sstl2_i)
port map (ddr_csb(i), ddr_csnr(i));
ckel(i) <= cke(i) and locked;
ckegen : ODDR generic map (DDR_CLK_EDGE => "SAME_EDGE")
port map ( Q => ddr_ckenr(i), C => clk0r, CE => vcc,
D1 => ckel(i), D2 => ckel(i), R => gnd, S => gnd);
cke_pad : outpad generic map (tech => virtex4, level => sstl2_i)
port map (ddr_cke(i), ddr_ckenr(i));
end generate;
rasgen : ODDR generic map (DDR_CLK_EDGE => "SAME_EDGE")
port map ( Q => ddr_rasnr, C => clk0r, CE => vcc,
D1 => rasn, D2 => rasn, R => gnd, S => gnd);
rasn_pad : outpad generic map (tech => virtex4, level => sstl2_i)
port map (ddr_rasb, ddr_rasnr);
casgen : ODDR generic map (DDR_CLK_EDGE => "SAME_EDGE")
port map ( Q => ddr_casnr, C => clk0r, CE => vcc,
D1 => casn, D2 => casn, R => gnd, S => gnd);
casn_pad : outpad generic map (tech => virtex4, level => sstl2_i)
port map (ddr_casb, ddr_casnr);
wengen : ODDR generic map (DDR_CLK_EDGE => "SAME_EDGE")
port map ( Q => ddr_wenr, C => clk0r, CE => vcc,
D1 => wen, D2 => wen, R => gnd, S => gnd);
wen_pad : outpad generic map (tech => virtex4, level => sstl2_i)
port map (ddr_web, ddr_wenr);
dmgen : for i in 0 to dbits/8-1 generate
da0 : ODDR generic map (DDR_CLK_EDGE => "SAME_EDGE")
port map ( Q => ddr_dmr(i), C => clk0r, CE => vcc,
D1 => dm(i+dbits/8), D2 => dm(i), R => gnd, S => gnd);
ddr_bm_pad : outpad generic map (tech => virtex4, level => sstl2_i)
port map (ddr_dm(i), ddr_dmr(i));
end generate;
bagen : for i in 0 to 1 generate
da0 : ODDR generic map (DDR_CLK_EDGE => "SAME_EDGE")
port map ( Q => ddr_bar(i), C => clk0r, CE => vcc,
D1 => ba(i), D2 => ba(i), R => gnd, S => gnd);
ddr_ba_pad : outpad generic map (tech => virtex4, level => sstl2_i)
port map (ddr_ba(i), ddr_bar(i));
end generate;
dagen : for i in 0 to 13 generate
da0 : ODDR generic map (DDR_CLK_EDGE => "SAME_EDGE")
port map ( Q => ddr_adr(i), C => clk0r, CE => vcc,
D1 => addr(i), D2 => addr(i), R => gnd, S => gnd);
ddr_ad_pad : outpad generic map (tech => virtex4, level => sstl2_i)
port map (ddr_ad(i), ddr_adr(i));
end generate;
-- DQS generation
dsqreg : FD port map ( Q => dqsn, C => clk180r, D => oe);
dqsgen : for i in 0 to dbits/8-1 generate
da0 : ODDR generic map (DDR_CLK_EDGE => "SAME_EDGE")
port map ( Q => ddr_dqsin(i), C => clk90r, CE => vcc,
D1 => dqsn, D2 => gnd, R => gnd, S => gnd);
doen : FD port map ( Q => ddr_dqsoen(i), C => clk0r, D => dqsoen);
dqs_pad : iopad generic map (tech => virtex4, level => sstl2_ii)
port map (pad => ddr_dqs(i), i => ddr_dqsin(i), en => ddr_dqsoen(i),
o => ddr_dqsoutl(i));
end generate;
-- Data bus
read_rstdel : process (clk_0r, lockl)
begin
if lockl = '0' then dll2rst <= (others => '1');
elsif rising_edge(clk_0r) then
dll2rst <= dll2rst(1 to 3) & '0';
end if;
end process;
bufg7 : BUFG port map (I => rclk0, O => rclk0b);
bufg8 : BUFG port map (I => rclk90, O => rclk90b);
-- bufg9 : BUFG port map (I => rclk270, O => rclk270b);
rclk270b <= not rclk90b;
nops : if rskew = 0 generate
read_dll : DCM
generic map (clkin_period => 10.0, DESKEW_ADJUST => "SOURCE_SYNCHRONOUS")
port map ( CLKIN => ddrclkfbl, CLKFB => rclk0b, DSSEN => gnd, PSCLK => gnd,
PSEN => gnd, PSINCDEC => gnd, RST => dll2rst(0), CLK0 => rclk0,
CLK90 => rclk90, CLK270 => rclk270);
end generate;
ps : if rskew /= 0 generate
read_dll : DCM
generic map (clkin_period => 10.0, DESKEW_ADJUST => "SOURCE_SYNCHRONOUS",
CLKOUT_PHASE_SHIFT => "FIXED", PHASE_SHIFT => rskew)
port map ( CLKIN => ddrclkfbl, CLKFB => rclk0b, DSSEN => gnd, PSCLK => gnd,
PSEN => gnd, PSINCDEC => gnd, RST => dll2rst(0), CLK0 => rclk0,
CLK90 => rclk90, CLK270 => rclk270);
end generate;
ddgen : for i in 0 to dbits-1 generate
qi : IDDR generic map (DDR_CLK_EDGE => "OPPOSITE_EDGE")
port map ( Q1 => dqinl(i), --(i+dbits), -- 1-bit output for positive edge of clock
Q2 => dqin(i), -- 1-bit output for negative edge of clock
C => rclk90b, --clk270r, --dqsclk((2*i)/dbits), -- 1-bit clock input
CE => vcc, -- 1-bit clock enable input
D => ddr_dqin(i), -- 1-bit DDR data input
R => gnd, -- 1-bit reset
S => gnd -- 1-bit set
);
dinq1 : FD port map ( Q => dqin(i+dbits), C => rclk270b, D => dqinl(i));
dout : ODDR generic map (DDR_CLK_EDGE => "SAME_EDGE")
port map ( Q => ddr_dqout(i), C => clk0r, CE => vcc,
D1 => dqout(i+dbits), D2 => dqout(i), R => gnd, S => gnd);
doen : FD port map ( Q => ddr_dqoen(i), C => clk0r, D => oen);
dq_pad : iopad generic map (tech => virtex4, level => sstl2_ii)
port map (pad => ddr_dq(i), i => ddr_dqout(i), en => ddr_dqoen(i), o => ddr_dqin(i));
end generate;
end;
library ieee;
use ieee.std_logic_1164.all;
-- pragma translate_off
library unisim;
use unisim.BUFG;
use unisim.DCM;
use unisim.FDDRRSE;
use unisim.IFDDRRSE;
use unisim.FD;
-- pragma translate_on
library grlib;
use grlib.stdlib.all;
library techmap;
use techmap.gencomp.all;
use techmap.oddrv2;
------------------------------------------------------------------
-- Virtex2 DDR PHY -----------------------------------------------
------------------------------------------------------------------
entity virtex2_ddr_phy is
generic(
MHz : integer := 100;
rstdelay: integer := 200;
dbits : integer := 16;
clk_mul : integer := 2;
clk_div : integer := 2;
rskew : integer := 0
);
port(
rst : in std_ulogic;
clk : in std_logic; -- input clock
clkout : out std_ulogic; -- system clock
lock : out std_ulogic; -- DCM locked
ddr_clk : out std_logic_vector(2 downto 0);
ddr_clkb : out std_logic_vector(2 downto 0);
ddr_clk_fb_out : out std_logic;
ddr_clk_fb : in std_logic;
ddr_cke : out std_logic_vector(1 downto 0);
ddr_csb : out std_logic_vector(1 downto 0);
ddr_web : out std_ulogic; -- ddr write enable
ddr_rasb : out std_ulogic; -- ddr ras
ddr_casb : out std_ulogic; -- ddr cas
ddr_dm : out std_logic_vector (dbits/8-1 downto 0); -- ddr dm
ddr_dqs : inout std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
ddr_ad : out std_logic_vector (13 downto 0); -- ddr address
ddr_ba : out std_logic_vector (1 downto 0); -- ddr bank address
ddr_dq : inout std_logic_vector (dbits-1 downto 0); -- ddr data
addr : in std_logic_vector (13 downto 0); -- data mask
ba : in std_logic_vector ( 1 downto 0); -- data mask
dqin : out std_logic_vector (dbits*2-1 downto 0); -- ddr input data
dqout : in std_logic_vector (dbits*2-1 downto 0); -- ddr input data
dm : in std_logic_vector (dbits/4-1 downto 0); -- data mask
oen : in std_ulogic;
dqs : in std_ulogic;
dqsoen : in std_ulogic;
rasn : in std_ulogic;
casn : in std_ulogic;
wen : in std_ulogic;
csn : in std_logic_vector(1 downto 0);
cke : in std_logic_vector(1 downto 0)
);
end;
architecture rtl of virtex2_ddr_phy is
component DCM
generic (
CLKDV_DIVIDE : real := 2.0;
CLKFX_DIVIDE : integer := 1;
CLKFX_MULTIPLY : integer := 4;
CLKIN_DIVIDE_BY_2 : boolean := false;
CLKIN_PERIOD : real := 10.0;
CLKOUT_PHASE_SHIFT : string := "NONE";
CLK_FEEDBACK : string := "1X";
DESKEW_ADJUST : string := "SYSTEM_SYNCHRONOUS";
DFS_FREQUENCY_MODE : string := "LOW";
DLL_FREQUENCY_MODE : string := "LOW";
DSS_MODE : string := "NONE";
DUTY_CYCLE_CORRECTION : boolean := true;
FACTORY_JF : bit_vector := X"C080";
PHASE_SHIFT : integer := 0;
STARTUP_WAIT : boolean := false
);
port (
CLKFB : in std_logic;
CLKIN : in std_logic;
DSSEN : in std_logic;
PSCLK : in std_logic;
PSEN : in std_logic;
PSINCDEC : in std_logic;
RST : in std_logic;
CLK0 : out std_logic;
CLK90 : out std_logic;
CLK180 : out std_logic;
CLK270 : out std_logic;
CLK2X : out std_logic;
CLK2X180 : out std_logic;
CLKDV : out std_logic;
CLKFX : out std_logic;
CLKFX180 : out std_logic;
LOCKED : out std_logic;
PSDONE : out std_logic;
STATUS : out std_logic_vector (7 downto 0));
end component;
component BUFG port (O : out std_logic; I : in std_logic); end component;
component FDDRRSE
-- generic ( INIT : bit := '0');
port
(
Q : out std_ulogic;
C0 : in std_ulogic;
C1 : in std_ulogic;
CE : in std_ulogic;
D0 : in std_ulogic;
D1 : in std_ulogic;
R : in std_ulogic;
S : in std_ulogic
);
end component;
component IFDDRRSE
port (
Q0 : out std_ulogic;
Q1 : out std_ulogic;
C0 : in std_ulogic;
C1 : in std_ulogic;
CE : in std_ulogic;
D : in std_ulogic;
R : in std_ulogic;
S : in std_ulogic);
end component;
component FD
generic ( INIT : bit := '0');
port ( Q : out std_ulogic;
C : in std_ulogic;
D : in std_ulogic);
end component;
component oddrv2
generic ( tech : integer := virtex4);
port
( Q : out std_ulogic;
C1 : in std_ulogic;
C2 : in std_ulogic;
CE : in std_ulogic;
D1 : in std_ulogic;
D2 : in std_ulogic;
R : in std_ulogic;
S : in std_ulogic);
end component;
signal vcc, gnd, dqsn, oe, lockl : std_ulogic;
signal ddr_clk_fb_outr : std_ulogic;
signal ddr_clk_fbl, fbclk : std_ulogic;
signal ddr_rasnr, ddr_casnr, ddr_wenr : std_ulogic;
signal ddr_clkl, ddr_clkbl : std_logic_vector(2 downto 0);
signal ddr_csnr, ddr_ckenr, ckel : std_logic_vector(1 downto 0);
signal clk_0ro, clk_90ro, clk_180ro, clk_270ro : std_ulogic;
signal clk_0r, clk_90r, clk_180r, clk_270r : std_ulogic;
signal clk0r, clk90r, clk180r, clk270r : std_ulogic;
signal locked, vlockl, ddrclkfbl : std_ulogic;
signal ddr_dqin : std_logic_vector (dbits-1 downto 0); -- ddr data
signal ddr_dqout : std_logic_vector (dbits-1 downto 0); -- ddr data
signal ddr_dqoen : std_logic_vector (dbits-1 downto 0); -- ddr data
signal ddr_adr : std_logic_vector (13 downto 0); -- ddr address
signal ddr_bar : std_logic_vector (1 downto 0); -- ddr address
signal ddr_dmr : std_logic_vector (dbits/8-1 downto 0); -- ddr address
signal ddr_dqsin : std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
signal ddr_dqsoen : std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
signal ddr_dqsoutl : std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
signal dqsdel, dqsclk : std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
signal da : std_logic_vector (dbits-1 downto 0); -- ddr data
signal dqinl : std_logic_vector (dbits-1 downto 0); -- ddr data
signal dllrst : std_logic_vector(0 to 3);
signal dll0rst, dll2rst : std_logic_vector(0 to 3);
signal mlock, mclkfb, mclk, mclkfx, mclk0 : std_ulogic;
signal rclk270b, rclk90b, rclk0b : std_ulogic;
signal rclk270, rclk90, rclk0 : std_ulogic;
constant DDR_FREQ : integer := (MHz * clk_mul) / clk_div;
begin
oe <= not oen;
vcc <= '1'; gnd <= '0';
-- Optional DDR clock multiplication
noclkscale : if clk_mul = clk_div generate
mclk <= clk; mlock <= rst;
end generate;
clkscale : if clk_mul /= clk_div generate
rstdel : process (clk, rst)
begin
if rst = '0' then dll0rst <= (others => '1');
elsif rising_edge(clk) then
dll0rst <= dll0rst(1 to 3) & '0';
end if;
end process;
bufg0 : BUFG port map (I => mclkfx, O => mclk);
bufg1 : BUFG port map (I => mclk0, O => mclkfb);
dllm : DCM
generic map (CLKFX_MULTIPLY => clk_mul, CLKFX_DIVIDE => clk_div,
CLKIN_PERIOD => 10.0)
port map ( CLKIN => clk, CLKFB => mclkfb, DSSEN => gnd, PSCLK => gnd,
PSEN => gnd, PSINCDEC => gnd, RST => dll0rst(0), CLK0 => mclk0,
LOCKED => mlock, CLKFX => mclkfx );
end generate;
-- DDR output clock generation
bufg1 : BUFG port map (I => clk_0ro, O => clk_0r);
-- bufg2 : BUFG port map (I => clk_90ro, O => clk_90r);
clk_90r <= not clk_270r;
-- bufg3 : BUFG port map (I => clk_180ro, O => clk_180r);
clk_180r <= not clk_0r;
bufg4 : BUFG port map (I => clk_270ro, O => clk_270r);
clkout <= clk_270r; clk0r <= clk_270r; clk90r <= clk_0r;
clk180r <= clk_90r; clk270r <= clk_180r;
dll : DCM generic map (CLKFX_MULTIPLY => 2, CLKFX_DIVIDE => 2)
port map ( CLKIN => mclk, CLKFB => clk_0r, DSSEN => gnd, PSCLK => gnd,
PSEN => gnd, PSINCDEC => gnd, RST => dllrst(0), CLK0 => clk_0ro,
CLK90 => clk_90ro, CLK180 => clk_180ro, CLK270 => clk_270ro,
LOCKED => lockl);
rstdel : process (mclk, mlock)
begin
if mlock = '0' then dllrst <= (others => '1');
elsif rising_edge(mclk) then
dllrst <= dllrst(1 to 3) & '0';
end if;
end process;
rdel : if rstdelay /= 0 generate
rcnt : process (clk_0r)
variable cnt : std_logic_vector(15 downto 0);
variable vlock, co : std_ulogic;
begin
if rising_edge(clk_0r) then
co := cnt(15);
vlockl <= vlock;
if lockl = '0' then
cnt := conv_std_logic_vector(rstdelay*DDR_FREQ, 16); vlock := '0';
else
if vlock = '0' then
cnt := cnt -1; vlock := cnt(15) and not co;
end if;
end if;
end if;
if lockl = '0' then
vlock := '0';
end if;
end process;
end generate;
locked <= lockl when rstdelay = 0 else vlockl;
lock <= locked;
-- Generate external DDR clock
fbdclk0r : FDDRRSE port map ( Q => ddr_clk_fb_outr, C0 => clk90r, C1 => clk270r,
CE => vcc, D0 => vcc, D1 => gnd, R => gnd, S => gnd);
fbclk_pad : outpad generic map (tech => virtex4, level => sstl2_i)
port map (ddr_clk_fb_out, ddr_clk_fb_outr);
ddrclocks : for i in 0 to 2 generate
dclk0r : FDDRRSE port map ( Q => ddr_clkl(i), C0 => clk90r, C1 => clk270r,
CE => vcc, D0 => vcc, D1 => gnd, R => gnd, S => gnd);
ddrclk_pad : outpad generic map (tech => virtex4, level => sstl2_i)
port map (ddr_clk(i), ddr_clkl(i));
dclk0rb : FDDRRSE port map ( Q => ddr_clkbl(i), C0 => clk90r, C1 => clk270r,
CE => vcc, D0 => gnd, D1 => vcc, R => gnd, S => gnd);
ddrclkb_pad : outpad generic map (tech => virtex4, level => sstl2_i)
port map (ddr_clkb(i), ddr_clkbl(i));
end generate;
ddrbanks : for i in 0 to 1 generate
csn0gen : FD port map ( Q => ddr_csnr(i), C => clk0r, D => csn(i));
csn0_pad : outpad generic map (tech => virtex4, level => sstl2_i)
port map (ddr_csb(i), ddr_csnr(i));
ckel(i) <= cke(i) and locked;
ckegen : FD port map ( Q => ddr_ckenr(i), C => clk0r, D => ckel(i));
cke_pad : outpad generic map (tech => virtex4, level => sstl2_i)
port map (ddr_cke(i), ddr_ckenr(i));
end generate;
-- DDR single-edge control signals
rasgen : FD port map ( Q => ddr_rasnr, C => clk0r, D => rasn);
rasn_pad : outpad generic map (tech => virtex4, level => sstl2_i)
port map (ddr_rasb, ddr_rasnr);
casgen : FD port map ( Q => ddr_casnr, C => clk0r, D => casn);
casn_pad : outpad generic map (tech => virtex4, level => sstl2_i)
port map (ddr_casb, ddr_casnr);
wengen : FD port map ( Q => ddr_wenr, C => clk0r, D => wen);
wen_pad : outpad generic map (tech => virtex4, level => sstl2_i)
port map (ddr_web, ddr_wenr);
dmgen : for i in 0 to dbits/8-1 generate
da0 : oddrv2 port map ( Q => ddr_dmr(i), C1 => clk0r, C2 => clk180r,
CE => vcc, D1 => dm(i+dbits/8), D2 => dm(i), R => gnd, S => gnd);
ddr_bm_pad : outpad generic map (tech => virtex4, level => sstl2_i)
port map (ddr_dm(i), ddr_dmr(i));
end generate;
bagen : for i in 0 to 1 generate
da0 : FD port map ( Q => ddr_bar(i), C => clk0r, D => ba(i));
ddr_ba_pad : outpad generic map (tech => virtex4, level => sstl2_i)
port map (ddr_ba(i), ddr_bar(i));
end generate;
dagen : for i in 0 to 13 generate
da0 : FD port map ( Q => ddr_adr(i), C => clk0r, D => addr(i));
ddr_ad_pad : outpad generic map (tech => virtex4, level => sstl2_i)
port map (ddr_ad(i), ddr_adr(i));
end generate;
-- DQS generation
dsqreg : FD port map ( Q => dqsn, C => clk180r, D => oe);
dqsgen : for i in 0 to dbits/8-1 generate
da0 : oddrv2
port map ( Q => ddr_dqsin(i), C1 => clk90r, C2 => clk270r,
CE => vcc, D1 => dqsn, D2 => gnd, R => gnd, S => gnd);
doen : FD port map ( Q => ddr_dqsoen(i), C => clk0r, D => dqsoen);
dqs_pad : iopad generic map (tech => virtex4, level => sstl2_ii)
port map (pad => ddr_dqs(i), i => ddr_dqsin(i), en => ddr_dqsoen(i),
o => ddr_dqsoutl(i));
end generate;
-- Data bus
ddrref_pad : clkpad generic map (tech => virtex2)
port map (ddr_clk_fb, ddrclkfbl);
read_rstdel : process (clk_0r, lockl)
begin
if lockl = '0' then dll2rst <= (others => '1');
elsif rising_edge(clk_0r) then
dll2rst <= dll2rst(1 to 3) & '0';
end if;
end process;
bufg7 : BUFG port map (I => rclk0, O => rclk0b);
bufg8 : BUFG port map (I => rclk90, O => rclk90b);
-- bufg9 : BUFG port map (I => rclk270, O => rclk270b);
rclk270b <= not rclk90b;
nops : if rskew = 0 generate
read_dll : DCM
generic map (clkin_period => 10.0, DESKEW_ADJUST => "SOURCE_SYNCHRONOUS")
port map ( CLKIN => ddrclkfbl, CLKFB => rclk0b, DSSEN => gnd, PSCLK => gnd,
PSEN => gnd, PSINCDEC => gnd, RST => dll2rst(0), CLK0 => rclk0,
CLK90 => rclk90, CLK270 => rclk270);
end generate;
ps : if rskew /= 0 generate
read_dll : DCM
generic map (clkin_period => 10.0, DESKEW_ADJUST => "SOURCE_SYNCHRONOUS",
CLKOUT_PHASE_SHIFT => "FIXED", PHASE_SHIFT => rskew)
port map ( CLKIN => ddrclkfbl, CLKFB => rclk0b, DSSEN => gnd, PSCLK => gnd,
PSEN => gnd, PSINCDEC => gnd, RST => dll2rst(0), CLK0 => rclk0,
CLK90 => rclk90, CLK270 => rclk270);
end generate;
ddgen : for i in 0 to dbits-1 generate
qi : IFDDRRSE
port map(
Q0 => dqinl(i), -- 1-bit output for positive edge of clock
Q1 => dqin(i), -- 1-bit output for negative edge of clock
C0 => rclk90b, -- clk270r, --dqsclk((2*i)/dbits), -- 1-bit clock input
C1 => rclk270b, -- clk90r, --dqsclk((2*i)/dbits), -- 1-bit clock input
CE => vcc, -- 1-bit clock enable input
D => ddr_dq(i), -- 1-bit DDR data input
R => gnd, -- 1-bit reset
S => gnd -- 1-bit set
);
dinq1 : FD port map(
Q => dqin(i+dbits),
C => rclk270b,
D => dqinl(i)
);
dout : oddrv2
port map(
Q => ddr_dqout(i),
C1 => clk0r,
C2 => clk180r,
CE => vcc,
D1 => dqout(i+dbits),
D2 => dqout(i),
R => gnd,
S => gnd
);
doen : FD
port map(
Q => ddr_dqoen(i),
C => clk0r,
D => oen
);
dq_pad : iopad
generic map(
tech => virtex4,
level => sstl2_ii
)
port map(
pad => ddr_dq(i),
i => ddr_dqout(i),
en => ddr_dqoen(i),
o => open
); -- o => ddr_dqin(i));
end generate;
end;
library ieee;
use ieee.std_logic_1164.all;
-- pragma translate_off
library unisim;
use unisim.BUFG;
use unisim.DCM;
use unisim.ODDR2;
use unisim.IDDR2;
use unisim.FD;
-- pragma translate_on
library grlib;
use grlib.stdlib.all;
library techmap;
use techmap.gencomp.all;
use techmap.oddrc3e;
------------------------------------------------------------------
-- Spartan3E DDR PHY -----------------------------------------------
------------------------------------------------------------------
entity spartan3e_ddr_phy is
generic (MHz : integer := 100; rstdelay : integer := 200;
dbits : integer := 16; clk_mul : integer := 2 ;
clk_div : integer := 2; rskew : integer := 0);
port (
rst : in std_ulogic;
clk : in std_logic; -- input clock
clkout : out std_ulogic; -- DDR state clock
clkread : out std_ulogic; -- DDR read clock
lock : out std_ulogic; -- DCM locked
ddr_clk : out std_logic_vector(2 downto 0);
ddr_clkb : out std_logic_vector(2 downto 0);
ddr_clk_fb_out : out std_logic;
ddr_clk_fb : in std_logic;
ddr_cke : out std_logic_vector(1 downto 0);
ddr_csb : out std_logic_vector(1 downto 0);
ddr_web : out std_ulogic; -- ddr write enable
ddr_rasb : out std_ulogic; -- ddr ras
ddr_casb : out std_ulogic; -- ddr cas
ddr_dm : out std_logic_vector (dbits/8-1 downto 0); -- ddr dm
ddr_dqs : inout std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
ddr_ad : out std_logic_vector (13 downto 0); -- ddr address
ddr_ba : out std_logic_vector (1 downto 0); -- ddr bank address
ddr_dq : inout std_logic_vector (dbits-1 downto 0); -- ddr data
addr : in std_logic_vector (13 downto 0); -- data mask
ba : in std_logic_vector ( 1 downto 0); -- data mask
dqin : out std_logic_vector (dbits*2-1 downto 0); -- ddr input data
dqout : in std_logic_vector (dbits*2-1 downto 0); -- ddr input data
dm : in std_logic_vector (dbits/4-1 downto 0); -- data mask
oen : in std_ulogic;
dqs : in std_ulogic;
dqsoen : in std_ulogic;
rasn : in std_ulogic;
casn : in std_ulogic;
wen : in std_ulogic;
csn : in std_logic_vector(1 downto 0);
cke : in std_logic_vector(1 downto 0)
);
end;
architecture rtl of spartan3e_ddr_phy is
component oddrc3e
generic ( tech : integer := virtex4);
port
( Q : out std_ulogic;
C1 : in std_ulogic;
C2 : in std_ulogic;
CE : in std_ulogic;
D1 : in std_ulogic;
D2 : in std_ulogic;
R : in std_ulogic;
S : in std_ulogic);
end component;
component DCM
generic (
CLKDV_DIVIDE : real := 2.0;
CLKFX_DIVIDE : integer := 1;
CLKFX_MULTIPLY : integer := 4;
CLKIN_DIVIDE_BY_2 : boolean := false;
CLKIN_PERIOD : real := 10.0;
CLKOUT_PHASE_SHIFT : string := "NONE";
CLK_FEEDBACK : string := "1X";
DESKEW_ADJUST : string := "SYSTEM_SYNCHRONOUS";
DFS_FREQUENCY_MODE : string := "LOW";
DLL_FREQUENCY_MODE : string := "LOW";
DSS_MODE : string := "NONE";
DUTY_CYCLE_CORRECTION : boolean := true;
FACTORY_JF : bit_vector := X"C080";
PHASE_SHIFT : integer := 0;
STARTUP_WAIT : boolean := false
);
port (
CLKFB : in std_logic;
CLKIN : in std_logic;
DSSEN : in std_logic;
PSCLK : in std_logic;
PSEN : in std_logic;
PSINCDEC : in std_logic;
RST : in std_logic;
CLK0 : out std_logic;
CLK90 : out std_logic;
CLK180 : out std_logic;
CLK270 : out std_logic;
CLK2X : out std_logic;
CLK2X180 : out std_logic;
CLKDV : out std_logic;
CLKFX : out std_logic;
CLKFX180 : out std_logic;
LOCKED : out std_logic;
PSDONE : out std_logic;
STATUS : out std_logic_vector (7 downto 0));
end component;
component BUFG port (O : out std_logic; I : in std_logic); end component;
component FD
generic ( INIT : bit := '0');
port ( Q : out std_ulogic;
C : in std_ulogic;
D : in std_ulogic);
end component;
component ODDR2
generic
(
DDR_ALIGNMENT : string := "NONE";
INIT : bit := '0';
SRTYPE : string := "SYNC"
);
port
(
Q : out std_ulogic;
C0 : in std_ulogic;
C1 : in std_ulogic;
CE : in std_ulogic;
D0 : in std_ulogic;
D1 : in std_ulogic;
R : in std_ulogic;
S : in std_ulogic
);
end component;
component IDDR2
generic
(
DDR_ALIGNMENT : string := "NONE";
INIT_Q0 : bit := '0';
INIT_Q1 : bit := '0';
SRTYPE : string := "SYNC"
);
port
(
Q0 : out std_ulogic;
Q1 : out std_ulogic;
C0 : in std_ulogic;
C1 : in std_ulogic;
CE : in std_ulogic;
D : in std_ulogic;
R : in std_ulogic;
S : in std_ulogic
);
end component;
signal vcc, gnd, dqsn, oe, lockl : std_ulogic;
signal ddr_clk_fb_outr : std_ulogic;
signal ddr_clk_fbl, fbclk : std_ulogic;
signal ddr_rasnr, ddr_casnr, ddr_wenr : std_ulogic;
signal ddr_clkl, ddr_clkbl : std_logic_vector(2 downto 0);
signal ddr_csnr, ddr_ckenr, ckel : std_logic_vector(1 downto 0);
signal clk_0ro, clk_90ro, clk_180ro, clk_270ro : std_ulogic;
signal clk_0r, clk_90r, clk_180r, clk_270r : std_ulogic;
signal clk0r, clk90r, clk180r, clk270r : std_ulogic;
signal locked, vlockl, ddrclkfbl, dllfb : std_ulogic;
signal ddr_dqin : std_logic_vector (dbits-1 downto 0); -- ddr data
signal ddr_dqout : std_logic_vector (dbits-1 downto 0); -- ddr data
signal ddr_dqoen : std_logic_vector (dbits-1 downto 0); -- ddr data
signal ddr_adr : std_logic_vector (13 downto 0); -- ddr address
signal ddr_bar : std_logic_vector (1 downto 0); -- ddr address
signal ddr_dmr : std_logic_vector (dbits/8-1 downto 0); -- ddr address
signal ddr_dqsin : std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
signal ddr_dqsoen : std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
signal ddr_dqsoutl : std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
signal dqsdel, dqsclk : std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
signal da : std_logic_vector (dbits-1 downto 0); -- ddr data
signal dqinl : std_logic_vector (dbits-1 downto 0); -- ddr data
signal dllrst : std_logic_vector(0 to 3);
signal dll0rst, dll2rst : std_logic_vector(0 to 3);
signal mlock, mclkfb, mclk, mclkfx, mclk0 : std_ulogic;
signal rclk270b, rclk90b, rclk0b : std_ulogic;
signal rclk270, rclk90, rclk0 : std_ulogic;
constant DDR_FREQ : integer := (MHz * clk_mul) / clk_div;
begin
oe <= not oen;
vcc <= '1'; gnd <= '0';
-- Optional DDR clock multiplication
noclkscale : if clk_mul = clk_div generate
mclk <= clk; mlock <= rst;
end generate;
clkscale : if clk_mul /= clk_div generate
rstdel : process (clk, rst)
begin
if rst = '0' then dll0rst <= (others => '1');
elsif rising_edge(clk) then
dll0rst <= dll0rst(1 to 3) & '0';
end if;
end process;
bufg0 : BUFG port map (I => mclkfx, O => mclk);
bufg1 : BUFG port map (I => mclk0, O => mclkfb);
dllm : DCM
generic map (CLKFX_MULTIPLY => clk_mul, CLKFX_DIVIDE => clk_div,
CLKIN_PERIOD => 10.0)
port map ( CLKIN => clk, CLKFB => mclkfb, DSSEN => gnd, PSCLK => gnd,
PSEN => gnd, PSINCDEC => gnd, RST => dll0rst(0), CLK0 => mclk0,
LOCKED => mlock, CLKFX => mclkfx );
end generate;
-- DDR output clock generation
bufg1 : BUFG port map (I => clk_0ro, O => clk_0r);
-- bufg2 : BUFG port map (I => clk_90ro, O => clk_90r);
clk_90r <= not clk_270r;
-- bufg3 : BUFG port map (I => clk_180ro, O => clk_180r);
clk_180r <= not clk_0r;
bufg4 : BUFG port map (I => clk_270ro, O => clk_270r);
clkout <= clk_270r;
-- clkout <= clk_90r when DDR_FREQ > 120 else clk_0r;
clk0r <= clk_270r; clk90r <= clk_0r;
clk180r <= clk_90r; clk270r <= clk_180r;
dll : DCM generic map (CLKFX_MULTIPLY => 2, CLKFX_DIVIDE => 2)
port map ( CLKIN => mclk, CLKFB => clk_0r, DSSEN => gnd, PSCLK => gnd,
PSEN => gnd, PSINCDEC => gnd, RST => dllrst(0), CLK0 => clk_0ro,
CLK90 => clk_90ro, CLK180 => clk_180ro, CLK270 => clk_270ro,
LOCKED => lockl);
rstdel : process (mclk, mlock)
begin
if mlock = '0' then dllrst <= (others => '1');
elsif rising_edge(mclk) then
dllrst <= dllrst(1 to 3) & '0';
end if;
end process;
rdel : if rstdelay /= 0 generate
rcnt : process (clk_0r)
variable cnt : std_logic_vector(15 downto 0);
variable vlock, co : std_ulogic;
begin
if rising_edge(clk_0r) then
co := cnt(15);
vlockl <= vlock;
if lockl = '0' then
cnt := conv_std_logic_vector(rstdelay*DDR_FREQ, 16); vlock := '0';
else
if vlock = '0' then
cnt := cnt -1; vlock := cnt(15) and not co;
end if;
end if;
end if;
if lockl = '0' then
vlock := '0';
end if;
end process;
end generate;
locked <= lockl when rstdelay = 0 else vlockl;
lock <= locked;
-- Generate external DDR clock
fbdclk0r : ODDR2 port map ( Q => ddr_clk_fb_outr, C0 => clk90r, C1 => clk270r,
CE => vcc, D0 => vcc, D1 => gnd, R => gnd, S => gnd);
fbclk_pad : outpad generic map (tech => virtex4, level => sstl2_i)
port map (ddr_clk_fb_out, ddr_clk_fb_outr);
ddrclocks : for i in 0 to 2 generate
dclk0r : ODDR2 port map ( Q => ddr_clkl(i), C0 => clk90r, C1 => clk270r,
CE => vcc, D0 => vcc, D1 => gnd, R => gnd, S => gnd);
ddrclk_pad : outpad generic map (tech => virtex4, level => sstl2_i)
port map (ddr_clk(i), ddr_clkl(i));
dclk0rb : ODDR2 port map ( Q => ddr_clkbl(i), C0 => clk90r, C1 => clk270r,
CE => vcc, D0 => gnd, D1 => vcc, R => gnd, S => gnd);
ddrclkb_pad : outpad generic map (tech => virtex4, level => sstl2_i)
port map (ddr_clkb(i), ddr_clkbl(i));
end generate;
ddrbanks : for i in 0 to 1 generate
csn0gen : FD port map ( Q => ddr_csnr(i), C => clk0r, D => csn(i));
csn0_pad : outpad generic map (tech => virtex4, level => sstl2_i)
port map (ddr_csb(i), ddr_csnr(i));
ckel(i) <= cke(i) and locked;
ckegen : FD port map ( Q => ddr_ckenr(i), C => clk0r, D => ckel(i));
cke_pad : outpad generic map (tech => virtex4, level => sstl2_i)
port map (ddr_cke(i), ddr_ckenr(i));
end generate;
-- DDR single-edge control signals
rasgen : FD port map ( Q => ddr_rasnr, C => clk0r, D => rasn);
rasn_pad : outpad generic map (tech => virtex4, level => sstl2_i)
port map (ddr_rasb, ddr_rasnr);
casgen : FD port map ( Q => ddr_casnr, C => clk0r, D => casn);
casn_pad : outpad generic map (tech => virtex4, level => sstl2_i)
port map (ddr_casb, ddr_casnr);
wengen : FD port map ( Q => ddr_wenr, C => clk0r, D => wen);
wen_pad : outpad generic map (tech => virtex4, level => sstl2_i)
port map (ddr_web, ddr_wenr);
dmgen : for i in 0 to dbits/8-1 generate
da0 : oddrc3e
port map ( Q => ddr_dmr(i), C1 => clk0r, C2 => clk180r,
CE => vcc, D1 => dm(i+dbits/8), D2 => dm(i), R => gnd, S => gnd);
ddr_bm_pad : outpad generic map (tech => virtex4, level => sstl2_i)
port map (ddr_dm(i), ddr_dmr(i));
end generate;
bagen : for i in 0 to 1 generate
da0 : FD port map ( Q => ddr_bar(i), C => clk0r, D => ba(i));
ddr_ba_pad : outpad generic map (tech => virtex4, level => sstl2_i)
port map (ddr_ba(i), ddr_bar(i));
end generate;
dagen : for i in 0 to 13 generate
da0 : FD port map ( Q => ddr_adr(i), C => clk0r, D => addr(i));
ddr_ad_pad : outpad generic map (tech => virtex4, level => sstl2_i)
port map (ddr_ad(i), ddr_adr(i));
end generate;
-- DQS generation
dsqreg : FD port map ( Q => dqsn, C => clk180r, D => oe);
dqsgen : for i in 0 to dbits/8-1 generate
da0 : oddrc3e
port map ( Q => ddr_dqsin(i), C1 => clk90r, C2 => clk270r,
CE => vcc, D1 => dqsn, D2 => gnd, R => gnd, S => gnd);
doen : FD port map ( Q => ddr_dqsoen(i), C => clk0r, D => dqsoen);
dqs_pad : iopad generic map (tech => virtex4, level => sstl2_i)
port map (pad => ddr_dqs(i), i => ddr_dqsin(i), en => ddr_dqsoen(i),
o => ddr_dqsoutl(i));
end generate;
-- Data bus
ddrref_pad : clkpad generic map (tech => virtex2)
port map (ddr_clk_fb, ddrclkfbl);
read_rstdel : process (clk_0r, lockl)
begin
if lockl = '0' then dll2rst <= (others => '1');
elsif rising_edge(clk_0r) then
dll2rst <= dll2rst(1 to 3) & '0';
end if;
end process;
bufg7 : BUFG port map (I => rclk0, O => rclk0b);
bufg8 : BUFG port map (I => rclk90, O => rclk90b);
-- bufg9 : BUFG port map (I => rclk270, O => rclk270b);
rclk270b <= not rclk90b;
clkread <= not rclk90b;
nops : if rskew = 0 generate
read_dll : DCM
generic map (clkin_period => 10.0, DESKEW_ADJUST => "SOURCE_SYNCHRONOUS")
port map ( CLKIN => ddrclkfbl, CLKFB => rclk0b, DSSEN => gnd, PSCLK => gnd,
PSEN => gnd, PSINCDEC => gnd, RST => dll2rst(0), CLK0 => rclk0,
CLK90 => rclk90, CLK270 => rclk270);
end generate;
ps : if rskew /= 0 generate
read_dll : DCM
generic map (clkin_period => 10.0, DESKEW_ADJUST => "SOURCE_SYNCHRONOUS",
CLKOUT_PHASE_SHIFT => "FIXED", PHASE_SHIFT => rskew)
port map ( CLKIN => ddrclkfbl, CLKFB => rclk0b, DSSEN => gnd, PSCLK => gnd,
PSEN => gnd, PSINCDEC => gnd, RST => dll2rst(0), CLK0 => rclk0,
CLK90 => rclk90, CLK270 => rclk270);
end generate;
ddgen : for i in 0 to dbits-1 generate
qi : IDDR2
port map ( Q0 => dqinl(i), Q1 => dqin(i), C0 => rclk90b, C1 => rclk270b,
CE => vcc, D => ddr_dqin(i), R => gnd, S => gnd );
dinq1 : FD port map ( Q => dqin(i+dbits), C => rclk270b, D => dqinl(i));
dout : oddrc3e
port map ( Q => ddr_dqout(i), C1 => clk0r, C2 => clk180r, CE => vcc,
D1 => dqout(i+dbits), D2 => dqout(i), R => gnd, S => gnd);
doen : FD port map ( Q => ddr_dqoen(i), C => clk0r, D => oen);
dq_pad : iopad generic map (tech => virtex4, level => sstl2_i)
port map (pad => ddr_dq(i), i => ddr_dqout(i), en => ddr_dqoen(i), o => ddr_dqin(i));
end generate;
end;
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.stdlib.all;
-- pragma translate_off
library unisim;
use unisim.BUFG;
use unisim.DCM;
use unisim.ODDR;
use unisim.FD;
use unisim.IDELAY;
use unisim.ISERDES;
use unisim.BUFIO;
use unisim.IDELAYCTRL;
-- pragma translate_on
library techmap;
use techmap.gencomp.all;
------------------------------------------------------------------
-- Virtex5 DDR2 PHY ----------------------------------------------
------------------------------------------------------------------
entity virtex5_ddr2_phy is
generic (MHz : integer := 100; rstdelay : integer := 200;
dbits : integer := 16; clk_mul : integer := 2; clk_div : integer := 2;
ddelayb0 : integer := 0; ddelayb1 : integer := 0; ddelayb2 : integer := 0;
ddelayb3 : integer := 0; ddelayb4 : integer := 0; ddelayb5 : integer := 0;
ddelayb6 : integer := 0; ddelayb7 : integer := 0;
numidelctrl : integer := 4; norefclk : integer := 0; tech : integer := virtex5);
port (
rst : in std_ulogic;
clk : in std_logic; -- input clock
clkref200 : in std_logic; -- input 200MHz clock
clkout : out std_ulogic; -- system clock
lock : out std_ulogic; -- DCM locked
ddr_clk : out std_logic_vector(2 downto 0);
ddr_clkb : out std_logic_vector(2 downto 0);
ddr_cke : out std_logic_vector(1 downto 0);
ddr_csb : out std_logic_vector(1 downto 0);
ddr_web : out std_ulogic; -- ddr write enable
ddr_rasb : out std_ulogic; -- ddr ras
ddr_casb : out std_ulogic; -- ddr cas
ddr_dm : out std_logic_vector (dbits/8-1 downto 0); -- ddr dm
ddr_dqs : inout std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
ddr_dqsn : inout std_logic_vector (dbits/8-1 downto 0); -- ddr dqsn
ddr_ad : out std_logic_vector (13 downto 0); -- ddr address
ddr_ba : out std_logic_vector (1 downto 0); -- ddr bank address
ddr_dq : inout std_logic_vector (dbits-1 downto 0); -- ddr data
ddr_odt : out std_logic_vector(1 downto 0);
addr : in std_logic_vector (13 downto 0); -- data mask
ba : in std_logic_vector ( 1 downto 0); -- data mask
dqin : out std_logic_vector (dbits*2-1 downto 0); -- ddr input data
dqout : in std_logic_vector (dbits*2-1 downto 0); -- ddr input data
dm : in std_logic_vector (dbits/4-1 downto 0); -- data mask
oen : in std_ulogic;
dqs : in std_ulogic;
dqsoen : in std_ulogic;
rasn : in std_ulogic;
casn : in std_ulogic;
wen : in std_ulogic;
csn : in std_logic_vector(1 downto 0);
cke : in std_logic_vector(1 downto 0);
cal_en : in std_logic_vector(dbits/8-1 downto 0);
cal_inc : in std_logic_vector(dbits/8-1 downto 0);
cal_rst : in std_logic;
odt : in std_logic_vector(1 downto 0)
);
end;
architecture rtl of virtex5_ddr2_phy is
component DCM
generic (
CLKDV_DIVIDE : real := 2.0;
CLKFX_DIVIDE : integer := 1;
CLKFX_MULTIPLY : integer := 4;
CLKIN_DIVIDE_BY_2 : boolean := false;
CLKIN_PERIOD : real := 10.0;
CLKOUT_PHASE_SHIFT : string := "NONE";
CLK_FEEDBACK : string := "1X";
DESKEW_ADJUST : string := "SYSTEM_SYNCHRONOUS";
DFS_FREQUENCY_MODE : string := "LOW";
DLL_FREQUENCY_MODE : string := "LOW";
DSS_MODE : string := "NONE";
DUTY_CYCLE_CORRECTION : boolean := true;
FACTORY_JF : bit_vector := X"C080";
PHASE_SHIFT : integer := 0;
STARTUP_WAIT : boolean := false
);
port (
CLKFB : in std_logic;
CLKIN : in std_logic;
DSSEN : in std_logic;
PSCLK : in std_logic;
PSEN : in std_logic;
PSINCDEC : in std_logic;
RST : in std_logic;
CLK0 : out std_logic;
CLK90 : out std_logic;
CLK180 : out std_logic;
CLK270 : out std_logic;
CLK2X : out std_logic;
CLK2X180 : out std_logic;
CLKDV : out std_logic;
CLKFX : out std_logic;
CLKFX180 : out std_logic;
LOCKED : out std_logic;
PSDONE : out std_logic;
STATUS : out std_logic_vector (7 downto 0));
end component;
component BUFG port (O : out std_logic; I : in std_logic); end component;
component ODDR
generic
( DDR_CLK_EDGE : string := "OPPOSITE_EDGE";
-- INIT : bit := '0';
SRTYPE : string := "SYNC");
port
(
Q : out std_ulogic;
C : in std_ulogic;
CE : in std_ulogic;
D1 : in std_ulogic;
D2 : in std_ulogic;
R : in std_ulogic;
S : in std_ulogic
);
end component;
component FD
generic ( INIT : bit := '0');
port ( Q : out std_ulogic;
C : in std_ulogic;
D : in std_ulogic);
end component;
component IDDR
generic ( DDR_CLK_EDGE : string := "SAME_EDGE";
INIT_Q1 : bit := '0';
INIT_Q2 : bit := '0';
SRTYPE : string := "ASYNC");
port
( Q1 : out std_ulogic;
Q2 : out std_ulogic;
C : in std_ulogic;
CE : in std_ulogic;
D : in std_ulogic;
R : in std_ulogic;
S : in std_ulogic);
end component;
-- component BUFIO
-- port ( O : out std_ulogic;
-- I : in std_ulogic);
-- end component;
component IDELAY
generic ( IOBDELAY_TYPE : string := "DEFAULT";
IOBDELAY_VALUE : integer := 0);
port ( O : out std_ulogic;
C : in std_ulogic;
CE : in std_ulogic;
I : in std_ulogic;
INC : in std_ulogic;
RST : in std_ulogic);
end component;
-- component ISERDES
-- generic
-- (
-- BITSLIP_ENABLE : boolean := false;
-- DATA_RATE : string := "DDR";
-- DATA_WIDTH : integer := 4;
-- INIT_Q1 : bit := '0';
-- INIT_Q2 : bit := '0';
-- INIT_Q3 : bit := '0';
-- INIT_Q4 : bit := '0';
-- INTERFACE_TYPE : string := "MEMORY";
-- IOBDELAY : string := "NONE";
-- IOBDELAY_TYPE : string := "DEFAULT";
-- IOBDELAY_VALUE : integer := 0;
-- NUM_CE : integer := 2;
-- SERDES_MODE : string := "MASTER";
-- SRVAL_Q1 : bit := '0';
-- SRVAL_Q2 : bit := '0';
-- SRVAL_Q3 : bit := '0';
-- SRVAL_Q4 : bit := '0'
-- );
-- port
-- (
-- O : out std_ulogic;
-- Q1 : out std_ulogic;
-- Q2 : out std_ulogic;
-- Q3 : out std_ulogic;
-- Q4 : out std_ulogic;
-- Q5 : out std_ulogic;
-- Q6 : out std_ulogic;
-- SHIFTOUT1 : out std_ulogic;
-- SHIFTOUT2 : out std_ulogic;
-- BITSLIP : in std_ulogic;
-- CE1 : in std_ulogic;
-- CE2 : in std_ulogic;
-- CLK : in std_ulogic;
-- CLKDIV : in std_ulogic;
-- D : in std_ulogic;
-- DLYCE : in std_ulogic;
-- DLYINC : in std_ulogic;
-- DLYRST : in std_ulogic;
-- OCLK : in std_ulogic;
-- REV : in std_ulogic;
-- SHIFTIN1 : in std_ulogic;
-- SHIFTIN2 : in std_ulogic;
-- SR : in std_ulogic
-- );
-- end component;
component IDELAYCTRL
port ( RDY : out std_ulogic;
REFCLK : in std_ulogic;
RST : in std_ulogic);
end component;
--signal vcc, gnd, dqsn, oe, lockl : std_ulogic;
signal vcc, gnd, oe, lockl : std_ulogic;
signal dqsn : std_logic_vector(dbits/8-1 downto 0);
signal ddr_clk_fb_outr : std_ulogic;
signal ddr_clk_fbl, fbclk : std_ulogic;
signal ddr_rasnr, ddr_casnr, ddr_wenr : std_ulogic;
signal ddr_clkl, ddr_clkbl : std_logic_vector(2 downto 0);
signal ddr_csnr, ddr_ckenr, ckel : std_logic_vector(1 downto 0);
signal clk_0ro, clk_90ro, clk_180ro, clk_270ro : std_ulogic;
signal clk_0r, clk_90r, clk_180r, clk_270r : std_ulogic;
signal clk0r, clk90r, clk180r, clk270r : std_ulogic;
signal locked, vlockl, ddrclkfbl, dllfb : std_ulogic;
signal ddr_dqin, ddr_dqin_nodel : std_logic_vector (dbits-1 downto 0); -- ddr data
signal ddr_dqout : std_logic_vector (dbits-1 downto 0); -- ddr data
signal ddr_dqoen : std_logic_vector (dbits-1 downto 0); -- ddr data
signal ddr_adr : std_logic_vector (13 downto 0); -- ddr address
signal ddr_bar : std_logic_vector (1 downto 0); -- ddr address
signal ddr_dmr : std_logic_vector (dbits/8-1 downto 0); -- ddr address
signal ddr_dqsin : std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
signal ddr_dqsoen : std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
signal ddr_dqsoutl : std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
signal dqsdel, dqsclk, dqsclkn : std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
signal da : std_logic_vector (dbits-1 downto 0); -- ddr data
signal dqinl : std_logic_vector (dbits-1 downto 0); -- ddr data
signal dllrst : std_logic_vector(0 to 3);
signal dll0rst, dll2rst : std_logic_vector(0 to 3);
signal mlock, mclkfb, mclk, mclkfx, mclk0 : std_ulogic;
signal rclk270b, rclk90b, rclk0b : std_ulogic;
signal rclk270, rclk90, rclk0 : std_ulogic;
signal clk200, clk200_0, clk200fb, clk200fx, lock200 : std_logic;
signal odtl : std_logic_vector(1 downto 0);
signal refclk_rdy : std_logic_vector(numidelctrl-1 downto 0);
constant DDR_FREQ : integer := (MHz * clk_mul) / clk_div;
type ddelay_type is array (7 downto 0) of integer;
constant ddelay : ddelay_type := (ddelayb0, ddelayb1, ddelayb2,
ddelayb3, ddelayb4, ddelayb5,
ddelayb6, ddelayb7);
attribute syn_noprune : boolean;
attribute syn_noprune of IDELAYCTRL : component is true;
attribute syn_keep : boolean;
attribute syn_keep of dqsclk : signal is true;
attribute syn_preserve : boolean;
attribute syn_preserve of dqsclk : signal is true;
attribute syn_keep of dqsn : signal is true;
attribute syn_preserve of dqsn : signal is true;
attribute keep : boolean;
attribute keep of mclkfx : signal is true;
attribute keep of clk_90ro : signal is true;
attribute syn_keep of mclkfx : signal is true;
attribute syn_keep of clk_90ro : signal is true;
begin
-- Generate 200 MHz ref clock if not supplied
refclkx : if norefclk = 0 generate
buf_clk200 : BUFG port map( I => clkref200, O => clk200);
lock200 <= '1';
end generate;
norefclkx : if norefclk /= 0 generate
bufg0 : BUFG port map (I => clk200fx, O => clk200);
bufg1 : BUFG port map (I => clk200_0, O => clk200fb);
HMODE_dll200 : if (tech = virtex4 and ((200 >= 210) or (MHz >= 210)))
or (tech = virtex5 and ((200 >= 140) or (MHz >= 140))) generate
dll200 : DCM
generic map (CLKFX_MULTIPLY => 2000/MHz, CLKFX_DIVIDE => 10,
DFS_FREQUENCY_MODE => "HIGH", DLL_FREQUENCY_MODE => "HIGH")
port map ( CLKIN => clk, CLKFB => clk200fb, DSSEN => gnd, PSCLK => gnd,
PSEN => gnd, PSINCDEC => gnd, RST => dll0rst(0), CLK0 => clk200_0,
LOCKED => lock200, CLKFX => clk200fx);
end generate;
LMODE_dll200 : if not ((tech = virtex4 and ((200 >= 210) or (MHz >= 210)))
or (tech = virtex5 and ((200 >= 140) or (MHz >= 140)))) generate
dll200 : DCM
generic map (CLKFX_MULTIPLY => 2000/MHz, CLKFX_DIVIDE => 10,
DFS_FREQUENCY_MODE => "LOW", DLL_FREQUENCY_MODE => "LOW")
port map ( CLKIN => clk, CLKFB => clk200fb, DSSEN => gnd, PSCLK => gnd,
PSEN => gnd, PSINCDEC => gnd, RST => dll0rst(0), CLK0 => clk200_0,
LOCKED => lock200, CLKFX => clk200fx);
end generate;
end generate;
-- Delay control
idelctrl : for i in 0 to numidelctrl-1 generate
u : IDELAYCTRL port map (rst => dllrst(0), refclk => clk200, rdy => refclk_rdy(i));
end generate;
oe <= not oen;
vcc <= '1'; gnd <= '0';
-- Optional DDR clock multiplication
noclkscale : if clk_mul = clk_div generate
--mclk <= clk;
dll0rst <= dllrst;
mlock <= '1';
mbufg0 : BUFG port map (I => clk, O => mclk);
end generate;
clkscale : if clk_mul /= clk_div generate
rstdel : process (clk, rst)
begin
if rst = '0' then dll0rst <= (others => '1');
elsif rising_edge(clk) then
dll0rst <= dll0rst(1 to 3) & '0';
end if;
end process;
bufg0 : BUFG port map (I => mclkfx, O => mclk);
bufg1 : BUFG port map (I => mclk0, O => mclkfb);
HMODE_dllm : if (tech = virtex4 and (((MHz*clk_mul)/clk_div >= 210) or (MHz >= 210)))
or (tech = virtex5 and (((MHz*clk_mul)/clk_div >= 140) or (MHz >= 140))) generate
dllm : DCM
generic map (CLKFX_MULTIPLY => clk_mul, CLKFX_DIVIDE => clk_div,
DFS_FREQUENCY_MODE => "HIGH", DLL_FREQUENCY_MODE => "HIGH")
port map ( CLKIN => clk, CLKFB => mclkfb, DSSEN => gnd, PSCLK => gnd,
PSEN => gnd, PSINCDEC => gnd, RST => dll0rst(0), CLK0 => mclk0,
LOCKED => mlock, CLKFX => mclkfx );
end generate;
LMODE_dllm : if not ((tech = virtex4 and (((MHz*clk_mul)/clk_div >= 210) or (MHz >= 210)))
or (tech = virtex5 and (((MHz*clk_mul)/clk_div >= 140) or (MHz >= 140)))) generate
dllm : DCM
generic map (CLKFX_MULTIPLY => clk_mul, CLKFX_DIVIDE => clk_div,
DFS_FREQUENCY_MODE => "LOW", DLL_FREQUENCY_MODE => "LOW")
port map ( CLKIN => clk, CLKFB => mclkfb, DSSEN => gnd, PSCLK => gnd,
PSEN => gnd, PSINCDEC => gnd, RST => dll0rst(0), CLK0 => mclk0,
LOCKED => mlock, CLKFX => mclkfx );
end generate;
end generate;
-- DDR clock generation
-- bufg1 : BUFG port map (I => clk_0ro, O => clk0r);
clk0r <= mclk;
bufg2 : BUFG port map (I => clk_90ro, O => clk90r);
-- bufg3 : BUFG port map (I => clk_180ro, O => clk180r);
clk180r <= not mclk;
-- bufg4 : BUFG port map (I => clk_270ro, O => clk270r);
clkout <= clk0r;
-- dllfb <= clk0r;
dllfb <= clk90r;
HMODE_dll : if (tech = virtex4 and ((MHz*clk_mul)/clk_div >= 150))
or (tech = virtex5 and ((MHz*clk_mul)/clk_div >= 120)) generate
dll : DCM generic map (CLKFX_MULTIPLY => 2, CLKFX_DIVIDE => 2,
DFS_FREQUENCY_MODE => "HIGH", DLL_FREQUENCY_MODE => "HIGH", --"HIGH")
PHASE_SHIFT => 64, CLKOUT_PHASE_SHIFT => "FIXED")--, CLKIN_PERIOD => real((1000*clk_div)/(MHz*clk_mul)))
port map ( CLKIN => mclk, CLKFB => dllfb, DSSEN => gnd, PSCLK => gnd,
PSEN => gnd, PSINCDEC => gnd, RST => dllrst(0), CLK0 => clk_90ro,
CLK90 => open, CLK180 => open, CLK270 => open,
LOCKED => lockl);
end generate;
LMODE_dll : if not ((tech = virtex4 and ((MHz*clk_mul)/clk_div >= 150))
or (tech = virtex5 and ((MHz*clk_mul)/clk_div >= 120))) generate
dll : DCM generic map (CLKFX_MULTIPLY => 2, CLKFX_DIVIDE => 2,
DFS_FREQUENCY_MODE => "LOW", DLL_FREQUENCY_MODE => "LOW", --"HIGH")
PHASE_SHIFT => 64, CLKOUT_PHASE_SHIFT => "FIXED")--, CLKIN_PERIOD => real((1000*clk_div)/(MHz*clk_mul)))
port map ( CLKIN => mclk, CLKFB => dllfb, DSSEN => gnd, PSCLK => gnd,
PSEN => gnd, PSINCDEC => gnd, RST => dllrst(0), CLK0 => clk_90ro,
CLK90 => open, CLK180 => open, CLK270 => open,
LOCKED => lockl);
end generate;
-- dll : DCM generic map (CLKFX_MULTIPLY => 2, CLKFX_DIVIDE => 2, CLKIN_PERIOD => 6.25,
-- DFS_FREQUENCY_MODE => "LOW", DLL_FREQUENCY_MODE => "HIGH") --"HIGH")
-- port map ( CLKIN => mclk, CLKFB => dllfb, DSSEN => gnd, PSCLK => gnd,
-- PSEN => gnd, PSINCDEC => gnd, RST => dllrst(0), CLK0 => clk_0ro,
-- CLK90 => clk_90ro, CLK180 => clk_180ro, CLK270 => clk_270ro,
-- LOCKED => lockl);
rstdel : process (mclk, rst, mlock, lock200)
begin
if rst = '0' or mlock = '0' or lock200 = '0' then dllrst <= (others => '1');
elsif rising_edge(mclk) then
dllrst <= dllrst(1 to 3) & '0';
end if;
end process;
rdel : if rstdelay /= 0 generate
--rcnt : process (clk_0r)
rcnt : process (clk0r)
variable cnt : std_logic_vector(15 downto 0);
variable vlock, co : std_ulogic;
begin
--if rising_edge(clk_0r) then
if rising_edge(clk0r) then
co := cnt(15);
vlockl <= vlock;
if lockl = '0' then
cnt := conv_std_logic_vector(rstdelay*DDR_FREQ, 16); vlock := '0';
else
if vlock = '0' then
cnt := cnt -1; vlock := cnt(15) and not co;
end if;
end if;
end if;
if lockl = '0' then
vlock := '0';
end if;
end process;
end generate;
locked <= lockl when rstdelay = 0 else vlockl;
lock <= locked and orv(refclk_rdy);
-- Generate external DDR clock
ddrclocks : for i in 0 to 2 generate
dclk0r : ODDR port map ( Q => ddr_clkl(i), C => clk90r, CE => vcc,
D1 => vcc, D2 => gnd, R => gnd, S => gnd);
ddrclk_pad : outpad generic map (tech => virtex5, level => sstl18_i)
port map (ddr_clk(i), ddr_clkl(i));
-- Diff ddr_clk
-- ddrclk_pad : outpad_ds generic map(tech => virtex5, level => sstl18_ii)
-- port map (ddr_clk(i), ddr_clkb(i), ddr_clkl(i), gnd);
dclk0rb : ODDR port map ( Q => ddr_clkbl(i), C => clk90r, CE => vcc,
D1 => gnd, D2 => vcc, R => gnd, S => gnd);
ddrclkb_pad : outpad generic map (tech => virtex5, level => sstl18_i)
port map (ddr_clkb(i), ddr_clkbl(i));
end generate;
-- ODT pads
odtgen : for i in 0 to 1 generate
odtl(i) <= locked and orv(refclk_rdy) and odt(i);
ddr_odt_pad : outpad generic map (tech => virtex5, level => sstl18_i)
port map (ddr_odt(i), odtl(i));
end generate;
ddrbanks : for i in 0 to 1 generate
csn0gen : ODDR generic map (DDR_CLK_EDGE => "SAME_EDGE")
port map ( Q => ddr_csnr(i), C => clk0r, CE => vcc,
D1 => csn(i), D2 => csn(i), R => gnd, S => gnd);
csn0_pad : outpad generic map (tech => virtex5, level => sstl18_i)
port map (ddr_csb(i), ddr_csnr(i));
ckel(i) <= cke(i) and locked;
ckegen : ODDR generic map (DDR_CLK_EDGE => "SAME_EDGE")
port map ( Q => ddr_ckenr(i), C => clk0r, CE => vcc,
D1 => ckel(i), D2 => ckel(i), R => gnd, S => gnd);
cke_pad : outpad generic map (tech => virtex5, level => sstl18_i)
port map (ddr_cke(i), ddr_ckenr(i));
end generate;
rasgen : ODDR generic map (DDR_CLK_EDGE => "SAME_EDGE")
port map ( Q => ddr_rasnr, C => clk0r, CE => vcc,
D1 => rasn, D2 => rasn, R => gnd, S => gnd);
rasn_pad : outpad generic map (tech => virtex5, level => sstl18_i)
port map (ddr_rasb, ddr_rasnr);
casgen : ODDR generic map (DDR_CLK_EDGE => "SAME_EDGE")
port map ( Q => ddr_casnr, C => clk0r, CE => vcc,
D1 => casn, D2 => casn, R => gnd, S => gnd);
casn_pad : outpad generic map (tech => virtex5, level => sstl18_i)
port map (ddr_casb, ddr_casnr);
wengen : ODDR generic map (DDR_CLK_EDGE => "SAME_EDGE")
port map ( Q => ddr_wenr, C => clk0r, CE => vcc,
D1 => wen, D2 => wen, R => gnd, S => gnd);
wen_pad : outpad generic map (tech => virtex5, level => sstl18_i)
port map (ddr_web, ddr_wenr);
dmgen : for i in 0 to dbits/8-1 generate
da0 : ODDR generic map (DDR_CLK_EDGE => "SAME_EDGE")
port map ( Q => ddr_dmr(i), C => clk0r, CE => vcc,
D1 => dm(i+dbits/8), D2 => dm(i), R => gnd, S => gnd);
ddr_bm_pad : outpad generic map (tech => virtex5, level => sstl18_i)
port map (ddr_dm(i), ddr_dmr(i));
end generate;
bagen : for i in 0 to 1 generate
da0 : ODDR generic map (DDR_CLK_EDGE => "SAME_EDGE")
port map ( Q => ddr_bar(i), C => clk0r, CE => vcc,
D1 => ba(i), D2 => ba(i), R => gnd, S => gnd);
ddr_ba_pad : outpad generic map (tech => virtex5, level => sstl18_i)
port map (ddr_ba(i), ddr_bar(i));
end generate;
dagen : for i in 0 to 13 generate
da0 : ODDR generic map (DDR_CLK_EDGE => "SAME_EDGE")
port map ( Q => ddr_adr(i), C => clk0r, CE => vcc,
D1 => addr(i), D2 => addr(i), R => gnd, S => gnd);
ddr_ad_pad : outpad generic map (tech => virtex5, level => sstl18_i)
port map (ddr_ad(i), ddr_adr(i));
end generate;
-- DQS generation
--dsqreg : FD port map ( Q => dqsn, C => clk180r, D => oe);
dqsgen : for i in 0 to dbits/8-1 generate
dsqreg : FD port map ( Q => dqsn(i), C => clk180r, D => oe);
da0 : ODDR generic map (DDR_CLK_EDGE => "SAME_EDGE")
port map ( Q => ddr_dqsin(i), C => clk90r, CE => vcc,
--D1 => dqsn, D2 => gnd, R => gnd, S => gnd);
D1 => dqsn(i), D2 => gnd, R => gnd, S => gnd);
doen : FD port map ( Q => ddr_dqsoen(i), C => clk0r, D => dqsoen);
dqs_pad : iopad_ds generic map (tech => virtex5, level => sstl18_ii)
port map (padp => ddr_dqs(i), padn => ddr_dqsn(i),i => ddr_dqsin(i),
en => ddr_dqsoen(i), o => ddr_dqsoutl(i));
-- del_dqs0 : IDELAY generic map(IOBDELAY_TYPE => "FIXED", IOBDELAY_VALUE => 10)
-- port map(O => dqsclk(i), I => ddr_dqsoutl(i), C => gnd, CE => gnd,
-- INC => gnd, RST => dllrst(0));
-- --buf_dqs0 : BUFIO port map(O => dqsclk(i), I => dqsdel(i));
-- dqsclkn(i) <= not dqsclk(i);
end generate;
-- Data bus
ddgen : for i in 0 to dbits-1 generate
del_dq0 : IDELAY generic map(IOBDELAY_TYPE => "VARIABLE", IOBDELAY_VALUE => ddelay(i/8))
--port map(O => ddr_dqin(i), I => ddr_dqin_nodel(i), C => clk_270r, CE => cal_en(i/8),
port map(O => ddr_dqin(i), I => ddr_dqin_nodel(i), C => clk0r, CE => cal_en(i/8),
INC => cal_inc(i/8), RST => cal_rst);
qi : IDDR generic map (DDR_CLK_EDGE => "OPPOSITE_EDGE")
port map ( Q1 => dqinl(i), --(i+dbits), -- 1-bit output for positive edge of clock
Q2 => dqin(i), --dqin(i), -- 1-bit output for negative edge of clock
--C => clk_90r, --clk270r, --dqsclk((2*i)/dbits), -- 1-bit clock input
C => clk180r, --clk270r, --dqsclk((2*i)/dbits), -- 1-bit clock input
CE => vcc, -- 1-bit clock enable input
D => ddr_dqin(i), -- 1-bit DDR data input
R => gnd, -- 1-bit reset
S => gnd -- 1-bit set
);
--dinq1 : FD port map ( Q => dqin(i+dbits), C => clk_270r, D => dqinl(i));
dinq1 : FD port map ( Q => dqin(i+dbits), C => clk0r, D => dqinl(i));
--dqi : ISERDES generic map(IOBDELAY => "IFD", IOBDELAY_TYPE => "FIXED", IOBDELAY_VALUE => 0)
-- port map(O => open, Q1 => dqin(i), Q2 => dqin(i+dbits), Q3 => open, Q4 => open, Q5 => open,
-- Q6 => open, SHIFTOUT1 => open, SHIFTOUT2 => open, BITSLIP => gnd,
-- CE1 => vcc, CE2 => vcc, CLK => dqsclk(i/8), CLKDIV => clk0r, D => ddr_dqin(i),
-- DLYCE => gnd, DLYINC => gnd, DLYRST => gnd, OCLK => clk0r, REV => gnd,
-- SHIFTIN1 => gnd, SHIFTIN2 => gnd, SR => gnd);
dout : ODDR generic map (DDR_CLK_EDGE => "SAME_EDGE")
port map ( Q => ddr_dqout(i), C => clk0r, CE => vcc,
D1 => dqout(i+dbits), D2 => dqout(i), R => gnd, S => gnd);
doen : FD port map ( Q => ddr_dqoen(i), C => clk0r, D => oen);
dq_pad : iopad generic map (tech => virtex5, level => sstl18_ii)
port map (pad => ddr_dq(i), i => ddr_dqout(i), en => ddr_dqoen(i), o => ddr_dqin_nodel(i)); --o => ddr_dqin(i));
end generate;
end;
| mit | 37f4857bc7d3efb8b2e9303792d4f82c | 0.561447 | 3.142516 | false | false | false | false |
impedimentToProgress/UCI-BlueChip | AttackFiles/Attacks/privEsc/lib/gleichmann/multiio/MultiIO_APB.vhd | 2 | 25,345 | --------------------------------------------------------------------
-- Entity: MultiIO_APB
-- File: MultiIO_APB.vhd
-- Author: Thomas Ameseder, Gleichmann Electronics
-- Based on an orginal version by [email protected]
--
-- Description: APB Multiple digital I/O for minimal User Interface
--------------------------------------------------------------------
-- Functionality:
-- 8 LEDs, active low or high, r/w
-- dual 7Segment, active low or high, w only
-- 8 DIL Switches, active low or high, r only
-- 8 Buttons, active low or high, r only, with IRQ enables
--------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
library gleichmann;
use gleichmann.spi.all;
use gleichmann.i2c.all;
use gleichmann.miscellaneous.all;
use gleichmann.multiio.all;
-- pragma translate_off
use std.textio.all;
-- pragma translate_on
entity MultiIO_APB is
generic (
hpe_version: integer := 0; -- adapt multiplexing for different boards
pindex : integer := 0; -- Leon-Index
paddr : integer := 0; -- Leon-Address
pmask : integer := 16#FFF#; -- Leon-Mask
pirq : integer := 0; -- Leon-IRQ
clk_freq_in : integer := 25_000_000; -- Leons clock to calculate timings
led7act : std_logic := '0'; -- active level for 7Segment
ledact : std_logic := '0'; -- active level for LEDs
switchact : std_logic := '1'; -- active level for LED's
buttonact : std_logic := '1'; -- active level for LED's
n_switches : integer := 8; -- number of switches that are driven
n_leds : integer := 8 -- number of LEDs that are driven
);
port (
rst_n : in std_ulogic; -- global Reset, active low
clk : in std_ulogic; -- global Clock
apbi : in apb_slv_in_type; -- APB-Input
apbo : out apb_slv_out_type; -- APB-Output
MultiIO_in : in MultiIO_in_type; -- MultIO-Inputs
MultiIO_out : out MultiIO_out_type -- MultiIO-Outputs
);
end entity;
architecture Implementation of MultiIO_APB is ----------------------
constant VERSION : std_logic_vector(31 downto 0) := x"EA_07_12_06";
constant REVISION : integer := 1;
constant MUXMAX : integer := 7;
constant VCC : std_logic_vector(31 downto 0) := (others => '1');
constant GND : std_logic_vector(31 downto 0) := (others => '0');
signal Enable1ms : boolean;
signal MUXCounter : integer range 0 to MUXMAX-1;
signal clkgen_mclk : std_ulogic;
signal clkgen_bclk : std_ulogic;
signal clkgen_sclk : std_ulogic;
signal clkgen_lrclk : std_ulogic;
type state_t is (WAIT_FOR_SYNC,READY,WAIT_FOR_ACK);
signal state,next_state : state_t;
signal Strobe,next_Strobe : std_ulogic;
-- status signals of the i2s core for upper-level state machine
signal SampleAck, WaitForSample : std_ulogic;
signal samplereg : std_ulogic_vector(N_CODECI2SBITS-1 downto 0);
constant pconfig : apb_config_type := (
0 => ahb_device_reg (VENDOR_GLEICHMANN, GLEICHMANN_HIFC, 0, REVISION, pirq),
1 => apb_iobar(paddr, pmask)
);
type MultiIOregisters is
record
ledreg : std_logic_vector(31 downto 0); -- LEDs
led7reg : std_logic_vector(31 downto 0); -- Dual 7Segment LEDs
codecreg : std_logic_vector(31 downto 0);
codecreg2 : std_logic_vector(31 downto 0);
-- Switches in
sw_inreg : std_logic_vector(31 downto 0);
-- ASCII value of input button
btn_inreg : std_logic_vector(31 downto 0);
irqenareg : std_logic_vector(31 downto 0); -- IRQ enables for Buttons
btn_irqs : std_logic_vector(31 downto 0); -- IRQs from each Button
new_data : std_ulogic;
-- new_data_valid : std_ulogic;
lcdreg : std_logic_vector(31 downto 0); -- LCD instruction
--cb1_in_reg : std_logic_vector(31 downto 0);
--cb1_out_reg : std_logic_vector(31 downto 0);
-- cb3_in_reg : std_logic_vector(31 downto 0);
--cb4_in2_reg : std_logic_vector(31 downto 0);
-- cb3_out_reg : std_logic_vector(31 downto 0);
--cb4_out2_reg : std_logic_vector(31 downto 0);
exp_in_reg : std_logic_vector(31 downto 0);
exp_out_reg : std_logic_vector(31 downto 0);
hsc_out_reg : std_logic_vector(31 downto 0);
hsc_in_reg : std_logic_vector(31 downto 0);
end record;
signal r, rin : MultiIOregisters; -- register sets
signal Key : std_logic_vector(7 downto 0); -- ASCII value of button
-- character representation of the key (for simulation purposes)
signal KeyVal : character;
signal OldColumnRow1 : std_logic_vector(6 downto 0); -- for key debounce
signal OldColumnRow2 : std_logic_vector(6 downto 0); -- for key debounce
begin
reg_rw : process(MUXCounter, MultiIO_in, apbi, key, r, rst_n)
variable readdata : std_logic_vector(31 downto 0); -- system bus width
variable irqs : std_logic_vector(31 downto 0); -- system IRQs width
variable v : MultiIOregisters; -- register set
begin
v := r;
-- reset registers
if rst_n = '0' then
-- lower half of LEDs on
v.ledreg := (others => '0');
v.ledreg(3 downto 0) := "1111";
v.led7reg := (others => '0');
v.led7reg(15 downto 0) := X"38_4F"; -- show "L3" Leon3 on 7Segments
v.codecreg := (others => '0');
v.codecreg2 := (others => '0');
v.irqenareg := (others => '0'); -- IRQs disable
v.btn_inreg := (others => '0');
v.sw_inreg := (others => '0');
-- new data flag off
v.new_data := '0';
-- v.new_data_valid := '0';
v.lcdreg := (others => '0');
-- v.cb3_in_reg := (others => '0');
--v.cb4_in2_reg := (others => '0');
-- v.cb3_out_reg := (others => '0');
--v.cb4_out2_reg := (others => '0');
v.exp_in_reg := (others => '0');
v.exp_out_reg := (others => '0');
v.hsc_in_reg := (others => '0');
v.hsc_out_reg := (others => '0');
end if;
-- get switches and buttons
if switchact = '1' then
v.sw_inreg(N_SWITCHES-1 downto 0) := MultiIO_in.switch_in;
else
v.sw_inreg(N_SWITCHES-1 downto 0) := not MultiIO_in.switch_in;
end if;
v.btn_inreg(7 downto 0) := key;
v.btn_irqs := (others => '0');
---------------------------------------------------------------------------
-- TO BE ALTERED
---------------------------------------------------------------------------
-- set local button-IRQs
for i in 0 to v.btn_irqs'left loop
-- detect low-to-high transition
if (v.btn_inreg(i) = '1') and (r.btn_inreg(i) = '0') then
-- set local IRQs if IRQ enabled
v.btn_irqs(i) := v.btn_inreg(i) and r.irqenareg(i);
else
-- clear local IRQs
v.btn_irqs(i) := '0';
end if;
end loop;
---------------------------------------------------------------------------
-- read registers
readdata := (others => 'X');
case conv_integer(apbi.paddr(6 downto 2)) is
when 0 => readdata := r.ledreg; -- LEDs
when 1 => readdata := r.led7reg; -- seven segment
when 2 => readdata := r.codecreg; -- codec command register
when 3 => readdata := r.codecreg2; -- codec i2s register
when 4 => readdata := r.sw_inreg; -- switches
when 5 => readdata := r.btn_inreg; -- buttons
when 6 => readdata := r.irqenareg; -- IRQ enables
when 7 => readdata := conv_std_logic_vector(pirq, 32); -- IRQ#
when 8 => readdata := version; -- version
when 9 => readdata := r.lcdreg; -- LCD data
when 10 => readdata := r.exp_out_reg; -- expansion connector out
when 11 => readdata := r.exp_in_reg; -- expansion connector in
when 12 => readdata := r.hsc_out_reg;
when 13 => readdata := r.hsc_in_reg;
--when 14 => readdata := r.cb4_out1_reg; -- childboard4 connector out
--when 15 => readdata := r.cb4_out2_reg; -- childboard4 connector out
-- when 14 => readdata := r.cb3_in_reg; -- childboard3 connector in
-- when 15 => readdata := r.cb3_out_reg; -- childboard3 connector out
--when 14 => readdata := r.cb1_out_reg; -- childboard1 connector out
--when 15 => readdata := r.cb1_in_reg; -- childboard1 connector in
when others => null;
end case;
-- write registers
if (apbi.psel(pindex) and apbi.penable and apbi.pwrite) = '1' then
case conv_integer(apbi.paddr(6 downto 2)) is
when 0 => v.ledreg :=
GND(31 downto N_LEDS) &
apbi.pwdata(N_LEDS-1 downto 0); -- write LEDs
when 1 => v.led7reg :=
GND(31 downto N_SEVSEGBITS) &
apbi.pwdata(N_SEVSEGBITS-1 downto 0); -- write 7Segment
when 2 => v.codecreg :=
GND(31 downto N_CODECBITS) &
apbi.pwdata(N_CODECBITS-1 downto 0);
when 3 => v.codecreg2 :=
GND(31 downto N_CODECI2SBITS) &
apbi.pwdata(N_CODECI2SBITS-1 downto 0);
when 6 => v.irqenareg :=
GND(31 downto N_BUTTONS) &
apbi.pwdata(N_BUTTONS-1 downto 0);
when 9 => v.lcdreg :=
GND(31 downto N_LCDBITS) &
apbi.pwdata(N_LCDBITS-1 downto 0);
-- signal that new data has arrived
-- v.new_data_valid := '0';
v.new_data := '1';
when 10 => v.exp_out_reg :=
GND(31 downto N_EXPBITS/2) &
-- bit(N_EXPBITS) holds enable signal
apbi.pwdata(N_EXPBITS/2-1 downto 0);
when 12 => v.hsc_out_reg :=
GND(31 downto N_HSCBITS) &
apbi.pwdata(N_HSCBITS-1 downto 0);
--when 14 => v.cb4_out1_reg :=
-- apbi.pwdata(31 downto 0);
-- when 15 => v.cb3_out_reg :=
-- apbi.pwdata(31 downto 0);
--when 14 => v.exp_out_reg :=
-- GND(31 downto 13) &
-- -- bit(N_EXPBITS) holds enable signal
-- apbi.pwdata(12 downto 0);
when others => null;
end case;
end if;
-- set PIRQ
irqs := (others => '0');
for i in 0 to v.btn_irqs'left loop
-- set IRQ if button-i pressed and IRQ enabled
irqs(pirq) := irqs(pirq) or r.btn_irqs(i);
end loop;
if ledact = '1' then
MultiIO_out.led_out <= r.ledreg(N_LEDS-1 downto 0); -- not inverted
else
MultiIO_out.led_out <= not r.ledreg(N_LEDS-1 downto 0); -- inverted
end if;
-- disable seven segment and LC display by default
-- MultiIO_out.lcd_enable <= '0';
MultiIO_out.lcd_rw <= r.lcdreg(8);
MultiIO_out.lcd_regsel <= r.lcdreg(9);
-- reset new lcd data flag
-- will be enabled when new data are written to the LCD register
if MUXCounter = 4 then
v.new_data := '0';
-- v.serviced := '1';
end if;
-- register inputs from expansion connector
v.exp_in_reg(N_EXPBITS/2-1 downto 0) := MultiIO_in.exp_in;
MultiIO_out.exp_out <= r.exp_out_reg(N_EXPBITS/2-1 downto 0);
-- high-speed connector
v.hsc_in_reg(N_HSCBITS-1 downto 0) := MultiIO_in.hsc_in;
MultiIO_out.hsc_out <= r.hsc_out_reg(N_HSCBITS-1 downto 0);
-- configure control port of audio codec for SPI mode
MultiIO_out.codec_mode <= '1';
apbo.prdata <= readdata; -- output data to Leon
apbo.pirq <= irqs; -- output IRQs to Leon
apbo.pindex <= pindex; -- output index to Leon
rin <= v; -- update registers
end process;
apbo.pconfig <= pconfig; -- output config to Leon
regs : process(clk) -- update registers
begin
if rising_edge(clk) then
r <= rin;
end if;
end process;
KeyBoard : process(clk, rst_n)
variable ColumnStrobe : std_logic_vector(2 downto 0);
variable FirstTime : boolean;
variable NewColumnRow : std_logic_vector(6 downto 0);
begin
if rst_n = '0' then
MultiIO_out.column_out <= (others => '0'); -- all column off
Key <= X"40"; -- default '@' after Reset and no key pressed
OldColumnRow1 <= "1111111";
OldColumnRow2 <= "1110011";
ColumnStrobe := "001";
FirstTime := true;
elsif rising_edge(clk) then
if Enable1ms then
if MultiIO_in.row_in = "0000" then -- no key pressed
ColumnStrobe := ColumnStrobe(1) & ColumnStrobe(0) & ColumnStrobe(2); -- rotate column
MultiIO_out.column_out <= ColumnStrobe;
if not FirstTime then
Key <= X"3F"; -- no key pressed '?'
end if;
else -- key pressed
OldColumnRow2 <= OldColumnRow1;
-- check whether button inputs produce a high or a
-- low level, then assign these inputs in order that
-- they can be decoded into ASCII format
if buttonact = '1' then
NewColumnRow := ColumnStrobe & MultiIO_in.row_in;
else
NewColumnRow := ColumnStrobe & not MultiIO_in.row_in;
end if;
OldColumnRow1 <= NewColumnRow;
if (ColumnStrobe & MultiIO_in.row_in = OldColumnRow1) and
(OldColumnRow1 = OldColumnRow2)
then -- debounced
FirstTime := false; -- 1st valid key pressed
case OldColumnRow2 is -- decode keys into ascii characters
when "0010001" => Key <= x"31"; -- 1
when "0010010" => Key <= x"34"; -- 4
when "0010100" => Key <= x"37"; -- 7
when "0011000" => Key <= x"43"; -- C
when "0100001" => Key <= x"32"; -- 2
when "0100010" => Key <= x"35"; -- 5
when "0100100" => Key <= x"38"; -- 8
when "0101000" => Key <= x"30"; -- 0
when "1000001" => Key <= x"33"; -- 3
when "1000010" => Key <= x"36"; -- 6
when "1000100" => Key <= x"39"; -- 9
when "1001000" => Key <= x"45"; -- E
when others => Key <= x"39"; -- ? -- more than one key pressed
end case;
else
Key <= x"3D"; -- '=' -- bouncing
end if; -- debounce
end if; -- MultiIO_in.row_in
end if; -- Enable1ms
end if; -- rst_n
end process KeyBoard;
Multiplex3Sources : if hpe_version = midi generate
Multiplex : process(MUXCounter, r)
begin
-- disable LED output by default
MultiIO_out.led_enable <= '0' xnor ledact;
-- disable 7-segment display by default
MultiIO_out.led_ca_out <= "00" xnor (led7act & led7act);
-- set enable signal in the middle of LCD timeslots
if MUXCounter = 3 then
MultiIO_out.lcd_enable <= '1';
else
MultiIO_out.lcd_enable <= '0';
end if;
case MUXCounter is
when 0 | 1 =>
-- output logical value according to active level of the 7segment display
MultiIO_out.led_a_out <= r.led7reg(MUXCounter*8 + 0) xnor led7act;
MultiIO_out.led_b_out <= r.led7reg(MUXCounter*8 + 1) xnor led7act;
MultiIO_out.led_c_out <= r.led7reg(MUXCounter*8 + 2) xnor led7act;
MultiIO_out.led_d_out <= r.led7reg(MUXCounter*8 + 3) xnor led7act;
MultiIO_out.led_e_out <= r.led7reg(MUXCounter*8 + 4) xnor led7act;
MultiIO_out.led_f_out <= r.led7reg(MUXCounter*8 + 5) xnor led7act;
MultiIO_out.led_g_out <= r.led7reg(MUXCounter*8 + 6) xnor led7act;
MultiIO_out.led_dp_out <= r.led7reg(MUXCounter*8 + 7) xnor led7act;
-- selectively enable the current digit
for i in 0 to 1 loop
if i = MUXCounter then
MultiIO_out.led_ca_out(i) <= '1' xnor led7act;
else
MultiIO_out.led_ca_out(i) <= '0' xnor led7act;
end if;
end loop; -- i
when 2 | 3 | 4 =>
MultiIO_out.led_a_out <= r.lcdreg(0);
MultiIO_out.led_b_out <= r.lcdreg(1);
MultiIO_out.led_c_out <= r.lcdreg(2);
MultiIO_out.led_d_out <= r.lcdreg(3);
MultiIO_out.led_e_out <= r.lcdreg(4);
MultiIO_out.led_f_out <= r.lcdreg(5);
MultiIO_out.led_g_out <= r.lcdreg(6);
MultiIO_out.led_dp_out <= r.lcdreg(7);
when 5 | 6 =>
MultiIO_out.led_enable <= '1' xnor ledact;
MultiIO_out.led_a_out <= r.ledreg(0) xnor ledact;
MultiIO_out.led_b_out <= r.ledreg(1) xnor ledact;
MultiIO_out.led_c_out <= r.ledreg(2) xnor ledact;
MultiIO_out.led_d_out <= r.ledreg(3) xnor ledact;
MultiIO_out.led_e_out <= r.ledreg(4) xnor ledact;
MultiIO_out.led_f_out <= r.ledreg(5) xnor ledact;
MultiIO_out.led_g_out <= r.ledreg(6) xnor ledact;
MultiIO_out.led_dp_out <= r.ledreg(7) xnor ledact;
when others =>
null;
end case;
end process Multiplex;
end generate Multiplex3Sources;
Multiplex2Sources : if hpe_version /= midi generate
Multiplex : process(MUXCounter, r)
begin
-- disable LED output by default
MultiIO_out.led_enable <= '0' xnor ledact;
-- disable 7-segment display by default
MultiIO_out.led_ca_out <= "00" xnor (led7act & led7act);
-- set enable signal in the middle of LCD timeslots
if MUXCounter = 3 then
MultiIO_out.lcd_enable <= '1';
else
MultiIO_out.lcd_enable <= '0';
end if;
case MUXCounter is
when 0 | 1 =>
-- output logical value according to active level of the 7segment display
MultiIO_out.led_a_out <= r.led7reg(MUXCounter*8 + 0) xnor led7act;
MultiIO_out.led_b_out <= r.led7reg(MUXCounter*8 + 1) xnor led7act;
MultiIO_out.led_c_out <= r.led7reg(MUXCounter*8 + 2) xnor led7act;
MultiIO_out.led_d_out <= r.led7reg(MUXCounter*8 + 3) xnor led7act;
MultiIO_out.led_e_out <= r.led7reg(MUXCounter*8 + 4) xnor led7act;
MultiIO_out.led_f_out <= r.led7reg(MUXCounter*8 + 5) xnor led7act;
MultiIO_out.led_g_out <= r.led7reg(MUXCounter*8 + 6) xnor led7act;
MultiIO_out.led_dp_out <= r.led7reg(MUXCounter*8 + 7) xnor led7act;
-- selectively enable the current digit
for i in 0 to 1 loop
if i = MUXCounter then
MultiIO_out.led_ca_out(i) <= '1' xnor led7act;
else
MultiIO_out.led_ca_out(i) <= '0' xnor led7act;
end if;
end loop; -- i
when others =>
MultiIO_out.led_a_out <= r.lcdreg(0);
MultiIO_out.led_b_out <= r.lcdreg(1);
MultiIO_out.led_c_out <= r.lcdreg(2);
MultiIO_out.led_d_out <= r.lcdreg(3);
MultiIO_out.led_e_out <= r.lcdreg(4);
MultiIO_out.led_f_out <= r.lcdreg(5);
MultiIO_out.led_g_out <= r.lcdreg(6);
MultiIO_out.led_dp_out <= r.lcdreg(7);
end case;
end process Multiplex;
end generate Multiplex2Sources;
-- generate prescaler signal every 100 ms
-- control MUXCounter according to input and board type
Count1ms : process(clk, rst_n)
constant divider100ms : integer := clk_freq_in / 10_000;
variable frequency_counter : integer range 0 to Divider100ms;
begin
if rst_n = '0' then
frequency_counter := Divider100ms;
Enable1ms <= false;
MUXCounter <= 0;
elsif rising_edge(clk) then
if frequency_counter = 0 then -- 1-ms counter has expired
frequency_counter := Divider100ms;
Enable1ms <= true;
if (hpe_version = midi) then
-- skip LCD control sequence and go to
-- LED control
if (MUXCounter = 1 and r.new_data = '0') then
MUXCounter <= 5;
-- overflow at maximum counter value for Hpe_midi
elsif MUXCounter = MUXMAX-1 then
MUXCounter <= 0;
else
MUXCounter <= MUXCounter + 1;
end if;
elsif (hpe_version /= midi) then
-- skip LCD control sequence and go back to
-- 7-segment control
if (MUXCounter = 1 and r.new_data = '0') then
MUXCounter <= 0;
-- overflow at maximum counter value for Hpe_mini
elsif MUXCounter = MUXMAX-3 then
MUXCounter <= 0;
else
MUXCounter <= MUXCounter + 1;
end if;
end if;
else
frequency_counter := frequency_counter - 1;
Enable1ms <= false;
end if;
end if;
end process;
---------------------------------------------------------------------------------------
-- AUDIO CODEC SECTION
---------------------------------------------------------------------------------------
tlv320aic23b_audio : if hpe_version = mini_altera generate
-- audio clock generation
clk_gen : ClockGenerator
port map (
Clk => clk,
Reset => rst_n,
omclk => clkgen_mclk,
obclk => clkgen_bclk,
osclk => clkgen_sclk,
olrcout => clkgen_lrclk);
-- drive clock signals by clock generator
MultiIO_out.CODEC_SCLK <= clkgen_sclk;
MultiIO_out.CODEC_MCLK <= clkgen_mclk;
MultiIO_out.CODEC_BCLK <= clkgen_bclk;
MultiIO_out.CODEC_LRCIN <= clkgen_lrclk;
MultiIO_out.CODEC_LRCOUT <= clkgen_lrclk;
-- SPI control interface
spi_xmit_1 : spi_xmit
generic map (
data_width => N_CODECBITS)
port map (
clk_i => clkgen_SCLK,
rst_i => rst_n,
data_i => r.codecreg(N_CODECBITS-1 downto 0),
CODEC_SDIN => MultiIO_out.CODEC_SDIN,
CODEC_CS => MultiIO_out.CODEC_CS);
-- I2C data interface
ParToI2s_1 : ParToI2s
generic map (
SampleSize_g => N_CODECI2SBITS)
port map (
Clk_i => clk,
Reset_i => rst_n,
SampleLeft_i => SampleReg,
SampleRight_i => SampleReg,
StrobeLeft_i => Strobe,
StrobeRight_i => Strobe,
SampleAck_o => SampleAck,
WaitForSample_o => WaitForSample,
SClk_i => clkgen_sclk,
LRClk_i => clkgen_lrclk,
SdnyData_o => MultiIO_out.CODEC_DIN);
audio_ctrl_sm : process(SampleAck, WaitForSample, state)
begin
next_state <= state;
next_Strobe <= '0';
case state is
when WAIT_FOR_SYNC =>
if WaitForSample = '1' then
next_state <= READY;
end if;
when READY =>
next_state <= WAIT_FOR_ACK;
next_Strobe <= '1';
when WAIT_FOR_ACK =>
if SampleAck = '1' then
next_state <= READY;
end if;
when others =>
next_state <= WAIT_FOR_SYNC;
end case;
end process;
audio_ctrl_reg : process(clk, rst_n)
begin
if rst_n = '0' then -- asynchronous reset
state <= WAIT_FOR_SYNC;
Strobe <= '0';
SampleReg <= (others => '0');
elsif clk'event and clk = '1' then
state <= next_state;
Strobe <= next_Strobe;
if (next_Strobe) = '1' then
-- if Mode = '0' then
-- SampleReg <= std_ulogic_vector(unsigned(AudioSample)- X"80");
-- else
-- SampleReg <= AudioSample;
-- end if;
SampleReg <= std_ulogic_vector(r.codecreg2(N_CODECI2SBITS-1 downto 0));
end if;
end if;
end process;
end generate tlv320aic23b_audio;
---------------------------------------------------------------------------------------
-- DEBUG SECTION
---------------------------------------------------------------------------------------
-- pragma translate_off
KeyVal <=
ascii2char(conv_integer(Key)) when
(conv_integer(Key) >= 16#30#) and (conv_integer(Key) <= 16#46#)
else 'U';
bootmsg : report_version
generic map ("MultiIO_APB6:" & tost(pindex) &
", Human Interface Controller rev " & tost(REVISION) &
", IRQ " & tost(pirq));
-- pragma translate_on
end architecture;
| mit | b2972610bf003dcd08af1f28c6c7da4f | 0.517972 | 3.622784 | false | false | false | false |
impedimentToProgress/UCI-BlueChip | AttackFiles/Attacks/privEsc/lib/gaisler/jtag/jtagtst.vhd | 2 | 13,849 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Package: sim
-- File: sim.vhd
-- Author: Edvin Catovic - Gaisler Research
-- Description: JTAG debug link communication test
------------------------------------------------------------------------------
-- pragma translate_off
library ieee;
use ieee.std_logic_1164.all;
use std.textio.all;
library grlib;
use grlib.stdlib.all;
use grlib.stdio.all;
use grlib.amba.all;
package jtagtst is
procedure clkj(tmsi, tdii : in std_ulogic; tdoo : out std_ulogic;
signal tck, tms, tdi : out std_ulogic;
signal tdo : in std_ulogic;
cp : in integer);
procedure shift(dr : in boolean; len : in integer;
din : in std_logic_vector; dout : out std_logic_vector;
signal tck, tms, tdi : out std_ulogic;
signal tdo : in std_ulogic;
cp : in integer);
procedure jtagcom(signal tdo : in std_ulogic;
signal tck, tms, tdi : out std_ulogic;
cp, start, addr : in integer;
-- cp - TCK clock period in ns
-- start - time in us when JTAG test
-- is started
-- addr - read/write operation destination address
haltcpu : in boolean);
end;
package body jtagtst is
procedure clkj(tmsi, tdii : in std_ulogic; tdoo : out std_ulogic;
signal tck, tms, tdi : out std_ulogic;
signal tdo : in std_ulogic;
cp : in integer) is
begin
tdi <= tdii;
tck <= '0'; tms <= tmsi;
wait for 2 * cp * 1 ns;
tck <= '1'; tdoo := tdo;
wait for 2 * cp * 1 ns;
end;
procedure shift(dr : in boolean; len : in integer;
din : in std_logic_vector; dout : out std_logic_vector;
signal tck, tms, tdi : out std_ulogic;
signal tdo : in std_ulogic;
cp : in integer) is
variable dc : std_ulogic;
begin
clkj('0', '-', dc, tck, tms, tdi, tdo, cp);
clkj('1', '-', dc, tck, tms, tdi, tdo, cp);
if (not dr) then clkj('1', '-', dc, tck, tms, tdi, tdo, cp); end if;
clkj('0', '-', dc, tck, tms, tdi, tdo, cp); -- capture
clkj('0', '-', dc, tck, tms, tdi, tdo, cp); -- shift (state)
for i in 0 to len-2 loop
clkj('0', din(i), dout(i), tck, tms, tdi, tdo, cp);
end loop;
clkj('1', din(len-1), dout(len-1), tck, tms, tdi, tdo, cp); -- end shift, goto exit1
clkj('1', '-', dc, tck, tms, tdi, tdo, cp); -- update ir/dr
clkj('0', '-', dc, tck, tms, tdi, tdo, cp); -- run_test/idle
end;
procedure jwrite(addr, data : in std_logic_vector;
signal tck, tms, tdi : out std_ulogic;
signal tdo : in std_ulogic;
cp : in integer) is
variable tmp : std_logic_vector(32 downto 0);
variable tmp2 : std_logic_vector(34 downto 0);
variable dr : std_logic_vector(32 downto 0);
variable dr2 : std_logic_vector(34 downto 0);
variable hsize : std_logic_vector(1 downto 0);
begin
hsize := "10";
wait for 10 * cp * 1 ns;
shift(false, 6, B"010000", dr, tck, tms, tdi, tdo, cp); -- inst = addrreg
wait for 5 * cp * 1 ns;
tmp2 := '1' & hsize & addr;
shift(true, 35, tmp2, dr2, tck, tms, tdi, tdo, cp); -- write add reg
wait for 5 * cp * 1 ns;
shift(false, 6, B"110000", dr, tck, tms, tdi, tdo, cp); -- inst = datareg
wait for 5 * cp * 1 ns;
tmp := '0' & data;
shift(true, 33, tmp, dr, tck, tms, tdi, tdo, cp); -- write data reg
end;
procedure jread(addr : in std_logic_vector;
data : out std_logic_vector;
signal tck, tms, tdi : out std_ulogic;
signal tdo : in std_ulogic;
cp : in integer) is
variable tmp : std_logic_vector(32 downto 0);
variable tmp2 : std_logic_vector(34 downto 0);
variable dr : std_logic_vector(32 downto 0);
variable dr2 : std_logic_vector(34 downto 0);
variable hsize : std_logic_vector(1 downto 0);
begin
hsize := "10";
wait for 10 * cp * 1 ns;
shift(false, 6, B"010000", dr, tck, tms, tdi, tdo, cp); -- inst = addrreg
wait for 5 * cp * 1 ns;
tmp2 := '0' & hsize & addr;
shift(true, 35, tmp2, dr2, tck, tms, tdi, tdo, cp); -- write add reg
wait for 5 * cp * 1 ns;
shift(false, 6, B"110000", dr, tck, tms, tdi, tdo, cp); -- inst = datareg
wait for 5 * cp * 1 ns;
tmp := (others => '0'); --tmp(32) := '1';
shift(true, 33, tmp, dr, tck, tms, tdi, tdo, cp); -- read data reg
data := dr(31 downto 0);
end;
subtype jword_type is std_logic_vector(31 downto 0);
type jdata_vector_type is array (integer range <>) of jword_type;
procedure jwritem(addr : in std_logic_vector;
data : in jdata_vector_type;
signal tck, tms, tdi : out std_ulogic;
signal tdo : in std_ulogic;
cp : in integer) is
variable tmp : std_logic_vector(32 downto 0);
variable tmp2 : std_logic_vector(34 downto 0);
variable dr : std_logic_vector(32 downto 0);
variable dr2 : std_logic_vector(34 downto 0);
variable hsize : std_logic_vector(1 downto 0);
begin
hsize := "10";
wait for 10 * cp * 1 ns;
shift(false, 6, B"010000", dr, tck, tms, tdi, tdo, cp); -- inst = addrreg
wait for 5 * cp * 1 ns;
tmp2 := '1' & hsize & addr;
shift(true, 35, tmp2, dr2, tck, tms, tdi, tdo, cp); -- write add reg
wait for 5 * cp * 1 ns;
shift(false, 6, B"110000", dr, tck, tms, tdi, tdo, cp); -- inst = datareg
wait for 5 * cp * 1 ns;
for i in data'left to data'right-1 loop
tmp := '1' & data(i);
shift(true, 33, tmp, dr, tck, tms, tdi, tdo, cp); -- write data reg
end loop;
tmp := '0' & data(data'right);
shift(true, 33, tmp, dr, tck, tms, tdi, tdo, cp); -- write data reg
end;
procedure jreadm(addr : in std_logic_vector;
data : out jdata_vector_type;
signal tck, tms, tdi : out std_ulogic;
signal tdo : in std_ulogic;
cp : in integer) is
variable tmp : std_logic_vector(32 downto 0);
variable tmp2 : std_logic_vector(34 downto 0);
variable dr : std_logic_vector(32 downto 0);
variable dr2 : std_logic_vector(34 downto 0);
variable hsize : std_logic_vector(1 downto 0);
begin
hsize := "10";
wait for 10 * cp * 1 ns;
shift(false, 6, B"010000", dr, tck, tms, tdi, tdo, cp); -- inst = addrreg
wait for 5 * cp * 1 ns;
tmp2 := '0' & hsize & addr;
shift(true, 35, tmp2, dr2, tck, tms, tdi, tdo, cp); -- write add reg
wait for 5 * cp * 1 ns;
shift(false, 6, B"110000", dr, tck, tms, tdi, tdo, cp); -- inst = datareg
wait for 5 * cp * 1 ns;
for i in data'left to data'right-1 loop
tmp := (others => '0'); tmp(32) := '1';
shift(true, 33, tmp, dr, tck, tms, tdi, tdo, cp); -- read data reg
data(i) := dr(31 downto 0);
end loop;
tmp := (others => '0');
shift(true, 33, tmp, dr, tck, tms, tdi, tdo, cp); -- read data reg
data(data'right) := dr(31 downto 0);
end;
procedure jtagcom(signal tdo : in std_ulogic;
signal tck, tms, tdi : out std_ulogic;
cp, start, addr : in integer;
haltcpu : in boolean) is
variable dc : std_ulogic;
variable dr : std_logic_vector(32 downto 0);
variable tmp : std_logic_vector(32 downto 0);
variable data : std_logic_vector(31 downto 0);
variable datav : jdata_vector_type(0 to 3);
begin
tck <= '0'; tms <= '0'; tdi <= '0';
wait for start * 1 us;
print("AHB JTAG TEST");
for i in 1 to 5 loop -- reset
clkj('1', '0', dc, tck, tms, tdi, tdo, cp);
end loop;
clkj('0', '-', dc, tck, tms, tdi, tdo, cp);
--read IDCODE
wait for 10 * cp * 1 ns;
shift(true, 32, conv_std_logic_vector(0, 32), dr, tck, tms, tdi, tdo, cp);
print("JTAG TAP ID:" & tost(dr(31 downto 0)));
wait for 10 * cp * 1 ns;
shift(false, 6, conv_std_logic_vector(63, 6), dr, tck, tms, tdi, tdo, cp); -- BYPASS
--shift data through BYPASS reg
shift(true, 32, conv_std_logic_vector(16#AAAA#, 16) & conv_std_logic_vector(16#AAAA#, 16), dr,
tck, tms, tdi, tdo, cp);
-- put CPUs in debug mode
if haltcpu then
jwrite(X"90000000", X"00000004", tck, tms, tdi, tdo, cp);
jwrite(X"90000020", X"0000FFFF", tck, tms, tdi, tdo, cp);
print("JTAG: Putting CPU in debug mode");
end if;
if false then
jwrite(X"90000000", X"FFFFFFFF", tck, tms, tdi, tdo, cp);
jread (X"90000000", data, tck, tms, tdi, tdo, cp);
print("JTAG WRITE " & tost(X"90000000") & ":" & tost(X"FFFFFFFF"));
print("JTAG READ " & tost(X"90000000") & ":" & tost(data));
jwrite(X"90100034", X"ABCD1234", tck, tms, tdi, tdo, cp);
jread (X"90100034", data, tck, tms, tdi, tdo, cp);
print("JTAG WRITE " & tost(X"90100034") & ":" & tost(X"ABCD1234"));
print("JTAG READ " & tost(X"90100034") & ":" & tost(data));
jwrite(X"90200058", X"ABCDEF01", tck, tms, tdi, tdo, cp);
jread (X"90200058", data, tck, tms, tdi, tdo, cp);
print("JTAG WRITE " & tost(X"90200058") & ":" & tost(X"ABCDEF01"));
print("JTAG READ " & tost(X"90200058") & ":" & tost(data));
jwrite(X"90300000", X"ABCD1234", tck, tms, tdi, tdo, cp);
jread (X"90300000", data, tck, tms, tdi, tdo, cp);
print("JTAG WRITE " & tost(X"90300000") & ":" & tost(X"ABCD1234"));
print("JTAG READ " & tost(X"90300000") & ":" & tost(data));
jwrite(X"90400000", X"ABCD1234", tck, tms, tdi, tdo, cp);
jread (X"90400000", data, tck, tms, tdi, tdo, cp);
print("JTAG WRITE " & tost(X"90400000") & ":" & tost(X"ABCD1234"));
print("JTAG READ " & tost(X"90400000") & ":" & tost(data));
jwrite(X"90400024", X"0000000C", tck, tms, tdi, tdo, cp);
jwrite(X"90700100", X"ABCD1234", tck, tms, tdi, tdo, cp);
jread (X"90700100", data, tck, tms, tdi, tdo, cp);
print("JTAG WRITE ITAG :" & tost(X"00000100") & ":" & tost(X"ABCD1234"));
print("JTAG READ ITAG :" & tost(X"00000100") & ":" & tost(data));
jwrite(X"90400024", X"0000000D", tck, tms, tdi, tdo, cp);
jwrite(X"90700100", X"ABCD1234", tck, tms, tdi, tdo, cp);
jread (X"90700100", data, tck, tms, tdi, tdo, cp);
print("JTAG WRITE IDATA:" & tost(X"00000100") & ":" & tost(X"ABCD1234"));
print("JTAG READ IDATA:" & tost(X"00000100") & ":" & tost(data));
jwrite(X"90400024", X"0000000E", tck, tms, tdi, tdo, cp);
jwrite(X"90700100", X"ABCD1234", tck, tms, tdi, tdo, cp);
jread (X"90700100", data, tck, tms, tdi, tdo, cp);
print("JTAG WRITE DTAG :" & tost(X"00000100") & ":" & tost(X"ABCD1234"));
print("JTAG READ DTAG :" & tost(X"00000100") & ":" & tost(data));
jwrite(X"90400024", X"0000000F", tck, tms, tdi, tdo, cp);
jwrite(X"90700100", X"ABCD1234", tck, tms, tdi, tdo, cp);
jread (X"90700100", data, tck, tms, tdi, tdo, cp);
print("JTAG WRITE DDATA:" & tost(X"00000100") & ":" & tost(X"ABCD1234"));
print("JTAG READ DDATA:" & tost(X"00000100") & ":" & tost(data));
end if;
--jwritem(addr, (X"00000010", X"00000010", X"00000010", X"00000010"), tck, tms, tdi, tdo, cp);
datav(0) := X"00000010"; datav(1) := X"00000011"; datav(2) := X"00000012"; datav(3) := X"00000013";
jwritem(conv_std_logic_vector(addr, 32), datav, tck, tms, tdi, tdo, cp);
print("JTAG WRITE " & tost(conv_std_logic_vector(addr,32)) & ":" & tost(X"00000010") & " " & tost(X"00000011") & " " & tost(X"00000012") & " " & tost(X"00000013"));
datav := (others => (others => '0'));
jreadm(conv_std_logic_vector(addr, 32), datav, tck, tms, tdi, tdo, cp);
print("JTAG READ " & tost(conv_std_logic_vector(addr,32)) & ":" & tost(datav(0)) & " " & tost(datav(1)) & " " & tost(datav(2)) & " " & tost(datav(3)));
assert (datav(0) = X"00000010") and (datav(1) = X"00000011") and (datav(2) = X"00000012") and (datav(3) = X"00000013")
report "JTAG test failed" severity failure;
assert false report "JTAG test passed, halting with failure." severity failure;
end procedure;
end;
-- pragma translate_on
| mit | fe73e8bddfa7275334c1968072f2842d | 0.532746 | 3.411924 | false | false | false | false |
lxp32/lxp32-cpu | rtl/lxp32_decode.vhd | 1 | 8,206 | ---------------------------------------------------------------------
-- Instruction decoder
--
-- Part of the LXP32 CPU
--
-- Copyright (c) 2016 by Alex I. Kuznetsov
--
-- The second stage of the LXP32 pipeline.
---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity lxp32_decode is
port(
clk_i: in std_logic;
rst_i: in std_logic;
word_i: in std_logic_vector(31 downto 0);
next_ip_i: in std_logic_vector(29 downto 0);
current_ip_i: in std_logic_vector(29 downto 0);
valid_i: in std_logic;
jump_valid_i: in std_logic;
ready_o: out std_logic;
interrupt_valid_i: in std_logic;
interrupt_vector_i: in std_logic_vector(2 downto 0);
interrupt_ready_o: out std_logic;
wakeup_i: in std_logic;
sp_raddr1_o: out std_logic_vector(7 downto 0);
sp_rdata1_i: in std_logic_vector(31 downto 0);
sp_raddr2_o: out std_logic_vector(7 downto 0);
sp_rdata2_i: in std_logic_vector(31 downto 0);
ready_i: in std_logic;
valid_o: out std_logic;
cmd_loadop3_o: out std_logic;
cmd_signed_o: out std_logic;
cmd_dbus_o: out std_logic;
cmd_dbus_store_o: out std_logic;
cmd_dbus_byte_o: out std_logic;
cmd_addsub_o: out std_logic;
cmd_mul_o: out std_logic;
cmd_div_o: out std_logic;
cmd_div_mod_o: out std_logic;
cmd_cmp_o: out std_logic;
cmd_jump_o: out std_logic;
cmd_negate_op2_o: out std_logic;
cmd_and_o: out std_logic;
cmd_xor_o: out std_logic;
cmd_shift_o: out std_logic;
cmd_shift_right_o: out std_logic;
jump_type_o: out std_logic_vector(3 downto 0);
op1_o: out std_logic_vector(31 downto 0);
op2_o: out std_logic_vector(31 downto 0);
op3_o: out std_logic_vector(31 downto 0);
dst_o: out std_logic_vector(7 downto 0)
);
end entity;
architecture rtl of lxp32_decode is
-- Decoder FSM state
type DecoderState is (Regular,ContinueLc,ContinueCjmp,ContinueInterrupt,Halt);
signal state: DecoderState:=Regular;
-- Input instruction portions
signal opcode: std_logic_vector(5 downto 0);
signal t1: std_logic;
signal t2: std_logic;
signal destination: std_logic_vector(7 downto 0);
signal rd1: std_logic_vector(7 downto 0);
signal rd2: std_logic_vector(7 downto 0);
-- Signals related to pipeline control
signal downstream_busy: std_logic;
signal self_busy: std_logic:='0';
signal busy: std_logic;
signal valid_out: std_logic:='0';
signal dst_out: std_logic_vector(7 downto 0);
-- Signals related to RD operand decoding
signal rd1_reg: std_logic_vector(7 downto 0);
signal rd2_reg: std_logic_vector(7 downto 0);
signal rd1_select: std_logic;
signal rd1_direct: std_logic_vector(31 downto 0);
signal rd2_select: std_logic;
signal rd2_direct: std_logic_vector(31 downto 0);
-- Signals related to interrupt handling
signal interrupt_ready: std_logic:='0';
signal wakeup_reg: std_logic:='0';
begin
-- Dissect input word
opcode<=word_i(31 downto 26);
t1<=word_i(25);
t2<=word_i(24);
destination<=word_i(23 downto 16);
rd1<=word_i(15 downto 8);
rd2<=word_i(7 downto 0);
-- Pipeline control
downstream_busy<=valid_out and not ready_i;
busy<=downstream_busy or self_busy;
process (clk_i) is
begin
if rising_edge(clk_i) then
if rst_i='1' then
valid_out<='0';
self_busy<='0';
state<=Regular;
interrupt_ready<='0';
cmd_loadop3_o<='-';
cmd_signed_o<='-';
cmd_dbus_o<='-';
cmd_dbus_store_o<='-';
cmd_dbus_byte_o<='-';
cmd_addsub_o<='-';
cmd_negate_op2_o<='-';
cmd_mul_o<='-';
cmd_div_o<='-';
cmd_div_mod_o<='-';
cmd_cmp_o<='-';
cmd_jump_o<='-';
cmd_and_o<='-';
cmd_xor_o<='-';
cmd_shift_o<='-';
cmd_shift_right_o<='-';
rd1_select<='-';
rd1_direct<=(others=>'-');
rd2_select<='-';
rd2_direct<=(others=>'-');
op3_o<=(others=>'-');
jump_type_o<=(others=>'-');
dst_out<=(others=>'-');
wakeup_reg<='0';
else
interrupt_ready<='0';
wakeup_reg<=wakeup_reg or wakeup_i;
if jump_valid_i='1' then
valid_out<='0';
self_busy<='0';
state<=Regular;
elsif downstream_busy='0' then
op3_o<=(others=>'-');
rd1_direct<=std_logic_vector(resize(signed(rd1),rd1_direct'length));
rd2_direct<=std_logic_vector(resize(signed(rd2),rd2_direct'length));
cmd_signed_o<=opcode(0);
cmd_div_mod_o<=opcode(1);
cmd_shift_right_o<=opcode(1);
cmd_dbus_byte_o<=opcode(1);
cmd_dbus_store_o<=opcode(2);
case state is
when Regular =>
cmd_loadop3_o<='0';
cmd_dbus_o<='0';
cmd_addsub_o<='0';
cmd_negate_op2_o<='0';
cmd_mul_o<='0';
cmd_div_o<='0';
cmd_cmp_o<='0';
cmd_jump_o<='0';
cmd_and_o<='0';
cmd_xor_o<='0';
cmd_shift_o<='0';
jump_type_o<=opcode(3 downto 0);
if interrupt_valid_i='1' and valid_i='1' then
cmd_jump_o<='1';
cmd_loadop3_o<='1';
op3_o<=current_ip_i&"01"; -- LSB indicates interrupt return
dst_out<=X"FD"; -- interrupt return pointer
rd1_select<='1';
rd2_select<='0';
valid_out<='1';
interrupt_ready<='1';
self_busy<='1';
state<=ContinueInterrupt;
else
if opcode(5 downto 3)="101" or opcode="000001" then -- lc or lcs
cmd_loadop3_o<='1';
-- Setting op3_o here only affects the lcs instruction
op3_o<=std_logic_vector(resize(signed(opcode(2 downto 0)&
t1&t2&rd1&rd2),op3_o'length));
end if;
if opcode(5 downto 3)="001" then
cmd_dbus_o<='1';
end if;
if opcode(5 downto 1)="01000" then
cmd_addsub_o<='1';
end if;
cmd_negate_op2_o<=opcode(0);
if opcode="010010" then
cmd_mul_o<='1';
end if;
if opcode(5 downto 2)="0101" then
cmd_div_o<='1';
end if;
if opcode(5 downto 3)="100" then -- jump or call
cmd_jump_o<='1';
cmd_loadop3_o<=opcode(0);
-- Setting op3_o here only affects the call instruction
op3_o<=next_ip_i&"00";
end if;
-- Note: (a or b) = (a and b) or (a xor b)
if opcode(5 downto 1)="01100" then
cmd_and_o<='1';
end if;
if opcode="011010" or opcode="011001" then
cmd_xor_o<='1';
end if;
if opcode(5 downto 2)="0111" then
cmd_shift_o<='1';
end if;
if opcode(5 downto 4)="11" then
cmd_cmp_o<='1';
cmd_negate_op2_o<='1';
end if;
rd1_select<=t1;
rd2_select<=t2;
dst_out<=destination;
if valid_i='1' then
if opcode="000001" then
valid_out<='0';
self_busy<='0';
state<=ContinueLc;
elsif opcode="000010" then
valid_out<='0';
self_busy<='1';
wakeup_reg<='0';
state<=Halt;
elsif opcode(5 downto 4)="11" then
valid_out<='1';
self_busy<='1';
state<=ContinueCjmp;
else
valid_out<='1';
end if;
else
valid_out<='0';
end if;
end if;
when ContinueLc =>
if valid_i='1' then
valid_out<='1';
op3_o<=word_i;
self_busy<='0';
state<=Regular;
end if;
when ContinueCjmp =>
valid_out<='1';
cmd_jump_o<='1';
rd1_select<='1';
self_busy<='0';
state<=Regular;
when ContinueInterrupt =>
valid_out<='0';
when Halt =>
if interrupt_valid_i='1' or wakeup_i='1' or wakeup_reg='1' then
self_busy<='0';
state<=Regular;
end if;
end case;
end if;
end if;
end if;
end process;
valid_o<=valid_out;
dst_o<=dst_out;
ready_o<=not busy;
interrupt_ready_o<=interrupt_ready;
-- Decode RD (register/direct) operands
process (clk_i) is
begin
if rising_edge(clk_i) then
if busy='0' then
rd1_reg<=rd1;
rd2_reg<=rd2;
end if;
end if;
end process;
sp_raddr1_o<="11110"&interrupt_vector_i when (state=Regular and interrupt_valid_i='1' and downstream_busy='0') or state=ContinueInterrupt else
dst_out when (state=ContinueCjmp and downstream_busy='0') else
rd1_reg when busy='1' else
rd1;
sp_raddr2_o<=rd2_reg when busy='1' else rd2;
op1_o<=sp_rdata1_i when rd1_select='1' else rd1_direct;
op2_o<=sp_rdata2_i when rd2_select='1' else rd2_direct;
end architecture;
| mit | 0376d741c32b4180a6f7a8fd738b9da7 | 0.586888 | 2.750922 | false | false | false | false |
cafe-alpha/wascafe | v13/r07c_de10_20201014_abus4/wasca/wasca_inst.vhd | 2 | 12,850 | component wasca is
port (
abus_avalon_sdram_bridge_0_abus_address : in std_logic_vector(9 downto 0) := (others => 'X'); -- address
abus_avalon_sdram_bridge_0_abus_read : in std_logic := 'X'; -- read
abus_avalon_sdram_bridge_0_abus_waitrequest : out std_logic; -- waitrequest
abus_avalon_sdram_bridge_0_abus_addressdata : inout std_logic_vector(15 downto 0) := (others => 'X'); -- addressdata
abus_avalon_sdram_bridge_0_abus_chipselect : in std_logic_vector(2 downto 0) := (others => 'X'); -- chipselect
abus_avalon_sdram_bridge_0_abus_direction : out std_logic; -- direction
abus_avalon_sdram_bridge_0_abus_disable_out : out std_logic; -- disable_out
abus_avalon_sdram_bridge_0_abus_interrupt : out std_logic; -- interrupt
abus_avalon_sdram_bridge_0_abus_muxing : out std_logic_vector(1 downto 0); -- muxing
abus_avalon_sdram_bridge_0_abus_writebyteenable_n : in std_logic_vector(1 downto 0) := (others => 'X'); -- writebyteenable_n
abus_avalon_sdram_bridge_0_abus_reset : in std_logic := 'X'; -- reset
abus_avalon_sdram_bridge_0_sdram_addr : out std_logic_vector(12 downto 0); -- addr
abus_avalon_sdram_bridge_0_sdram_ba : out std_logic_vector(1 downto 0); -- ba
abus_avalon_sdram_bridge_0_sdram_cas_n : out std_logic; -- cas_n
abus_avalon_sdram_bridge_0_sdram_cke : out std_logic; -- cke
abus_avalon_sdram_bridge_0_sdram_cs_n : out std_logic; -- cs_n
abus_avalon_sdram_bridge_0_sdram_dq : inout std_logic_vector(15 downto 0) := (others => 'X'); -- dq
abus_avalon_sdram_bridge_0_sdram_dqm : out std_logic_vector(1 downto 0); -- dqm
abus_avalon_sdram_bridge_0_sdram_ras_n : out std_logic; -- ras_n
abus_avalon_sdram_bridge_0_sdram_we_n : out std_logic; -- we_n
abus_avalon_sdram_bridge_0_sdram_clk : out std_logic; -- clk
altpll_1_areset_conduit_export : in std_logic := 'X'; -- export
altpll_1_locked_conduit_export : out std_logic; -- export
altpll_1_phasedone_conduit_export : out std_logic; -- export
buffered_spi_mosi : out std_logic; -- mosi
buffered_spi_clk : out std_logic; -- clk
buffered_spi_miso : in std_logic := 'X'; -- miso
buffered_spi_cs : out std_logic; -- cs
clk_clk : in std_logic := 'X'; -- clk
clock_116_mhz_clk : out std_logic; -- clk
extra_leds_conn_export : out std_logic_vector(4 downto 0); -- export
hex0_conn_export : out std_logic_vector(6 downto 0); -- export
hex1_conn_export : out std_logic_vector(6 downto 0); -- export
hex2_conn_export : out std_logic_vector(6 downto 0); -- export
hex3_conn_export : out std_logic_vector(6 downto 0); -- export
hex4_conn_export : out std_logic_vector(6 downto 0); -- export
hex5_conn_export : out std_logic_vector(6 downto 0); -- export
hexdot_conn_export : out std_logic_vector(5 downto 0); -- export
leds_conn_export : out std_logic_vector(3 downto 0); -- export
reset_reset_n : in std_logic := 'X'; -- reset_n
reset_controller_0_reset_in1_reset : in std_logic := 'X'; -- reset
spi_sync_conn_export : in std_logic := 'X'; -- export
switches_conn_export : in std_logic_vector(7 downto 0) := (others => 'X'); -- export
uart_0_external_connection_rxd : in std_logic := 'X'; -- rxd
uart_0_external_connection_txd : out std_logic -- txd
);
end component wasca;
u0 : component wasca
port map (
abus_avalon_sdram_bridge_0_abus_address => CONNECTED_TO_abus_avalon_sdram_bridge_0_abus_address, -- abus_avalon_sdram_bridge_0_abus.address
abus_avalon_sdram_bridge_0_abus_read => CONNECTED_TO_abus_avalon_sdram_bridge_0_abus_read, -- .read
abus_avalon_sdram_bridge_0_abus_waitrequest => CONNECTED_TO_abus_avalon_sdram_bridge_0_abus_waitrequest, -- .waitrequest
abus_avalon_sdram_bridge_0_abus_addressdata => CONNECTED_TO_abus_avalon_sdram_bridge_0_abus_addressdata, -- .addressdata
abus_avalon_sdram_bridge_0_abus_chipselect => CONNECTED_TO_abus_avalon_sdram_bridge_0_abus_chipselect, -- .chipselect
abus_avalon_sdram_bridge_0_abus_direction => CONNECTED_TO_abus_avalon_sdram_bridge_0_abus_direction, -- .direction
abus_avalon_sdram_bridge_0_abus_disable_out => CONNECTED_TO_abus_avalon_sdram_bridge_0_abus_disable_out, -- .disable_out
abus_avalon_sdram_bridge_0_abus_interrupt => CONNECTED_TO_abus_avalon_sdram_bridge_0_abus_interrupt, -- .interrupt
abus_avalon_sdram_bridge_0_abus_muxing => CONNECTED_TO_abus_avalon_sdram_bridge_0_abus_muxing, -- .muxing
abus_avalon_sdram_bridge_0_abus_writebyteenable_n => CONNECTED_TO_abus_avalon_sdram_bridge_0_abus_writebyteenable_n, -- .writebyteenable_n
abus_avalon_sdram_bridge_0_abus_reset => CONNECTED_TO_abus_avalon_sdram_bridge_0_abus_reset, -- .reset
abus_avalon_sdram_bridge_0_sdram_addr => CONNECTED_TO_abus_avalon_sdram_bridge_0_sdram_addr, -- abus_avalon_sdram_bridge_0_sdram.addr
abus_avalon_sdram_bridge_0_sdram_ba => CONNECTED_TO_abus_avalon_sdram_bridge_0_sdram_ba, -- .ba
abus_avalon_sdram_bridge_0_sdram_cas_n => CONNECTED_TO_abus_avalon_sdram_bridge_0_sdram_cas_n, -- .cas_n
abus_avalon_sdram_bridge_0_sdram_cke => CONNECTED_TO_abus_avalon_sdram_bridge_0_sdram_cke, -- .cke
abus_avalon_sdram_bridge_0_sdram_cs_n => CONNECTED_TO_abus_avalon_sdram_bridge_0_sdram_cs_n, -- .cs_n
abus_avalon_sdram_bridge_0_sdram_dq => CONNECTED_TO_abus_avalon_sdram_bridge_0_sdram_dq, -- .dq
abus_avalon_sdram_bridge_0_sdram_dqm => CONNECTED_TO_abus_avalon_sdram_bridge_0_sdram_dqm, -- .dqm
abus_avalon_sdram_bridge_0_sdram_ras_n => CONNECTED_TO_abus_avalon_sdram_bridge_0_sdram_ras_n, -- .ras_n
abus_avalon_sdram_bridge_0_sdram_we_n => CONNECTED_TO_abus_avalon_sdram_bridge_0_sdram_we_n, -- .we_n
abus_avalon_sdram_bridge_0_sdram_clk => CONNECTED_TO_abus_avalon_sdram_bridge_0_sdram_clk, -- .clk
altpll_1_areset_conduit_export => CONNECTED_TO_altpll_1_areset_conduit_export, -- altpll_1_areset_conduit.export
altpll_1_locked_conduit_export => CONNECTED_TO_altpll_1_locked_conduit_export, -- altpll_1_locked_conduit.export
altpll_1_phasedone_conduit_export => CONNECTED_TO_altpll_1_phasedone_conduit_export, -- altpll_1_phasedone_conduit.export
buffered_spi_mosi => CONNECTED_TO_buffered_spi_mosi, -- buffered_spi.mosi
buffered_spi_clk => CONNECTED_TO_buffered_spi_clk, -- .clk
buffered_spi_miso => CONNECTED_TO_buffered_spi_miso, -- .miso
buffered_spi_cs => CONNECTED_TO_buffered_spi_cs, -- .cs
clk_clk => CONNECTED_TO_clk_clk, -- clk.clk
clock_116_mhz_clk => CONNECTED_TO_clock_116_mhz_clk, -- clock_116_mhz.clk
extra_leds_conn_export => CONNECTED_TO_extra_leds_conn_export, -- extra_leds_conn.export
hex0_conn_export => CONNECTED_TO_hex0_conn_export, -- hex0_conn.export
hex1_conn_export => CONNECTED_TO_hex1_conn_export, -- hex1_conn.export
hex2_conn_export => CONNECTED_TO_hex2_conn_export, -- hex2_conn.export
hex3_conn_export => CONNECTED_TO_hex3_conn_export, -- hex3_conn.export
hex4_conn_export => CONNECTED_TO_hex4_conn_export, -- hex4_conn.export
hex5_conn_export => CONNECTED_TO_hex5_conn_export, -- hex5_conn.export
hexdot_conn_export => CONNECTED_TO_hexdot_conn_export, -- hexdot_conn.export
leds_conn_export => CONNECTED_TO_leds_conn_export, -- leds_conn.export
reset_reset_n => CONNECTED_TO_reset_reset_n, -- reset.reset_n
reset_controller_0_reset_in1_reset => CONNECTED_TO_reset_controller_0_reset_in1_reset, -- reset_controller_0_reset_in1.reset
spi_sync_conn_export => CONNECTED_TO_spi_sync_conn_export, -- spi_sync_conn.export
switches_conn_export => CONNECTED_TO_switches_conn_export, -- switches_conn.export
uart_0_external_connection_rxd => CONNECTED_TO_uart_0_external_connection_rxd, -- uart_0_external_connection.rxd
uart_0_external_connection_txd => CONNECTED_TO_uart_0_external_connection_txd -- .txd
);
| gpl-2.0 | 4f3515a8b58020e871d76f7163afa908 | 0.425136 | 4.426455 | false | false | false | false |
cafe-alpha/wascafe | v13/r07c_de10_20201014_abus4/wasca/synthesis/submodules/Altera_UP_SD_Card_Memory_Block.vhd | 7 | 12,584 | -- (C) 2001-2015 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
-- megafunction wizard: %RAM: 2-PORT%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altsyncram
-- ============================================================
-- File Name: Altera_UP_SD_Card_Memory_Block.vhd
-- Megafunction Name(s):
-- altsyncram
--
-- Simulation Library Files(s):
-- altera_mf
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 8.0 Build 215 05/29/2008 SJ Full Version
-- ************************************************************
--Copyright (C) 1991-2013 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
ENTITY Altera_UP_SD_Card_Memory_Block IS
PORT
(
address_a : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
address_b : IN STD_LOGIC_VECTOR (11 DOWNTO 0);
clock_a : IN STD_LOGIC ;
clock_b : IN STD_LOGIC ;
data_a : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
data_b : IN STD_LOGIC_VECTOR (0 DOWNTO 0);
enable_a : IN STD_LOGIC := '1';
enable_b : IN STD_LOGIC := '1';
wren_a : IN STD_LOGIC := '1';
wren_b : IN STD_LOGIC := '1';
q_a : OUT STD_LOGIC_VECTOR (15 DOWNTO 0);
q_b : OUT STD_LOGIC_VECTOR (0 DOWNTO 0)
);
END Altera_UP_SD_Card_Memory_Block;
ARCHITECTURE SYN OF altera_up_sd_card_memory_block IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (15 DOWNTO 0);
SIGNAL sub_wire1 : STD_LOGIC_VECTOR (0 DOWNTO 0);
COMPONENT altsyncram
GENERIC (
address_reg_b : STRING;
clock_enable_input_a : STRING;
clock_enable_input_b : STRING;
clock_enable_output_a : STRING;
clock_enable_output_b : STRING;
indata_reg_b : STRING;
init_file : STRING;
init_file_layout : STRING;
intended_device_family : STRING;
lpm_type : STRING;
numwords_a : NATURAL;
numwords_b : NATURAL;
operation_mode : STRING;
outdata_aclr_a : STRING;
outdata_aclr_b : STRING;
outdata_reg_a : STRING;
outdata_reg_b : STRING;
power_up_uninitialized : STRING;
widthad_a : NATURAL;
widthad_b : NATURAL;
width_a : NATURAL;
width_b : NATURAL;
width_byteena_a : NATURAL;
width_byteena_b : NATURAL;
wrcontrol_wraddress_reg_b : STRING
);
PORT (
clocken0 : IN STD_LOGIC ;
clocken1 : IN STD_LOGIC ;
wren_a : IN STD_LOGIC ;
clock0 : IN STD_LOGIC ;
wren_b : IN STD_LOGIC ;
clock1 : IN STD_LOGIC ;
address_a : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
address_b : IN STD_LOGIC_VECTOR (11 DOWNTO 0);
q_a : OUT STD_LOGIC_VECTOR (15 DOWNTO 0);
q_b : OUT STD_LOGIC_VECTOR (0 DOWNTO 0);
data_a : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
data_b : IN STD_LOGIC_VECTOR (0 DOWNTO 0)
);
END COMPONENT;
BEGIN
q_a <= sub_wire0(15 DOWNTO 0);
q_b <= sub_wire1(0 DOWNTO 0);
altsyncram_component : altsyncram
GENERIC MAP (
address_reg_b => "CLOCK1",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_a => "BYPASS",
clock_enable_output_b => "BYPASS",
indata_reg_b => "CLOCK1",
init_file => "initial_data.mif",
init_file_layout => "PORT_A",
intended_device_family => "Cyclone II",
lpm_type => "altsyncram",
numwords_a => 256,
numwords_b => 4096,
operation_mode => "BIDIR_DUAL_PORT",
outdata_aclr_a => "NONE",
outdata_aclr_b => "NONE",
outdata_reg_a => "UNREGISTERED",
outdata_reg_b => "UNREGISTERED",
power_up_uninitialized => "FALSE",
widthad_a => 8,
widthad_b => 12,
width_a => 16,
width_b => 1,
width_byteena_a => 1,
width_byteena_b => 1,
wrcontrol_wraddress_reg_b => "CLOCK1"
)
PORT MAP (
clocken0 => enable_a,
clocken1 => enable_b,
wren_a => wren_a,
clock0 => clock_a,
wren_b => wren_b,
clock1 => clock_b,
address_a => address_a,
address_b => address_b,
data_a => data_a,
data_b => data_b,
q_a => sub_wire0,
q_b => sub_wire1
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
-- Retrieval info: PRIVATE: ADDRESSSTALL_B NUMERIC "0"
-- Retrieval info: PRIVATE: BYTEENA_ACLR_A NUMERIC "0"
-- Retrieval info: PRIVATE: BYTEENA_ACLR_B NUMERIC "0"
-- Retrieval info: PRIVATE: BYTE_ENABLE_A NUMERIC "0"
-- Retrieval info: PRIVATE: BYTE_ENABLE_B NUMERIC "0"
-- Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
-- Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "1"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_B NUMERIC "1"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_B NUMERIC "0"
-- Retrieval info: PRIVATE: CLRdata NUMERIC "0"
-- Retrieval info: PRIVATE: CLRq NUMERIC "0"
-- Retrieval info: PRIVATE: CLRrdaddress NUMERIC "0"
-- Retrieval info: PRIVATE: CLRrren NUMERIC "0"
-- Retrieval info: PRIVATE: CLRwraddress NUMERIC "0"
-- Retrieval info: PRIVATE: CLRwren NUMERIC "0"
-- Retrieval info: PRIVATE: Clock NUMERIC "5"
-- Retrieval info: PRIVATE: Clock_A NUMERIC "0"
-- Retrieval info: PRIVATE: Clock_B NUMERIC "0"
-- Retrieval info: PRIVATE: ECC NUMERIC "0"
-- Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
-- Retrieval info: PRIVATE: INDATA_ACLR_B NUMERIC "0"
-- Retrieval info: PRIVATE: INDATA_REG_B NUMERIC "1"
-- Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
-- Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
-- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
-- Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
-- Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
-- Retrieval info: PRIVATE: MEMSIZE NUMERIC "4096"
-- Retrieval info: PRIVATE: MEM_IN_BITS NUMERIC "1"
-- Retrieval info: PRIVATE: MIFfilename STRING "initial_data.mif"
-- Retrieval info: PRIVATE: OPERATION_MODE NUMERIC "3"
-- Retrieval info: PRIVATE: OUTDATA_ACLR_B NUMERIC "0"
-- Retrieval info: PRIVATE: OUTDATA_REG_B NUMERIC "0"
-- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_MIXED_PORTS NUMERIC "2"
-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3"
-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_B NUMERIC "3"
-- Retrieval info: PRIVATE: REGdata NUMERIC "1"
-- Retrieval info: PRIVATE: REGq NUMERIC "0"
-- Retrieval info: PRIVATE: REGrdaddress NUMERIC "0"
-- Retrieval info: PRIVATE: REGrren NUMERIC "0"
-- Retrieval info: PRIVATE: REGwraddress NUMERIC "1"
-- Retrieval info: PRIVATE: REGwren NUMERIC "1"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: USE_DIFF_CLKEN NUMERIC "0"
-- Retrieval info: PRIVATE: UseDPRAM NUMERIC "1"
-- Retrieval info: PRIVATE: VarWidth NUMERIC "1"
-- Retrieval info: PRIVATE: WIDTH_READ_A NUMERIC "16"
-- Retrieval info: PRIVATE: WIDTH_READ_B NUMERIC "1"
-- Retrieval info: PRIVATE: WIDTH_WRITE_A NUMERIC "16"
-- Retrieval info: PRIVATE: WIDTH_WRITE_B NUMERIC "1"
-- Retrieval info: PRIVATE: WRADDR_ACLR_B NUMERIC "0"
-- Retrieval info: PRIVATE: WRADDR_REG_B NUMERIC "1"
-- Retrieval info: PRIVATE: WRCTRL_ACLR_B NUMERIC "0"
-- Retrieval info: PRIVATE: enable NUMERIC "1"
-- Retrieval info: PRIVATE: rden NUMERIC "0"
-- Retrieval info: CONSTANT: ADDRESS_REG_B STRING "CLOCK1"
-- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "NORMAL"
-- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_B STRING "NORMAL"
-- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
-- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_B STRING "BYPASS"
-- Retrieval info: CONSTANT: INDATA_REG_B STRING "CLOCK1"
-- Retrieval info: CONSTANT: INIT_FILE STRING "initial_data.mif"
-- Retrieval info: CONSTANT: INIT_FILE_LAYOUT STRING "PORT_A"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
-- Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "256"
-- Retrieval info: CONSTANT: NUMWORDS_B NUMERIC "4096"
-- Retrieval info: CONSTANT: OPERATION_MODE STRING "BIDIR_DUAL_PORT"
-- Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
-- Retrieval info: CONSTANT: OUTDATA_ACLR_B STRING "NONE"
-- Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED"
-- Retrieval info: CONSTANT: OUTDATA_REG_B STRING "UNREGISTERED"
-- Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
-- Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "8"
-- Retrieval info: CONSTANT: WIDTHAD_B NUMERIC "12"
-- Retrieval info: CONSTANT: WIDTH_A NUMERIC "16"
-- Retrieval info: CONSTANT: WIDTH_B NUMERIC "1"
-- Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
-- Retrieval info: CONSTANT: WIDTH_BYTEENA_B NUMERIC "1"
-- Retrieval info: CONSTANT: WRCONTROL_WRADDRESS_REG_B STRING "CLOCK1"
-- Retrieval info: USED_PORT: address_a 0 0 8 0 INPUT NODEFVAL address_a[7..0]
-- Retrieval info: USED_PORT: address_b 0 0 12 0 INPUT NODEFVAL address_b[11..0]
-- Retrieval info: USED_PORT: clock_a 0 0 0 0 INPUT NODEFVAL clock_a
-- Retrieval info: USED_PORT: clock_b 0 0 0 0 INPUT NODEFVAL clock_b
-- Retrieval info: USED_PORT: data_a 0 0 16 0 INPUT NODEFVAL data_a[15..0]
-- Retrieval info: USED_PORT: data_b 0 0 1 0 INPUT NODEFVAL data_b[0..0]
-- Retrieval info: USED_PORT: enable_a 0 0 0 0 INPUT VCC enable_a
-- Retrieval info: USED_PORT: enable_b 0 0 0 0 INPUT VCC enable_b
-- Retrieval info: USED_PORT: q_a 0 0 16 0 OUTPUT NODEFVAL q_a[15..0]
-- Retrieval info: USED_PORT: q_b 0 0 1 0 OUTPUT NODEFVAL q_b[0..0]
-- Retrieval info: USED_PORT: wren_a 0 0 0 0 INPUT VCC wren_a
-- Retrieval info: USED_PORT: wren_b 0 0 0 0 INPUT VCC wren_b
-- Retrieval info: CONNECT: @data_a 0 0 16 0 data_a 0 0 16 0
-- Retrieval info: CONNECT: @wren_a 0 0 0 0 wren_a 0 0 0 0
-- Retrieval info: CONNECT: q_a 0 0 16 0 @q_a 0 0 16 0
-- Retrieval info: CONNECT: q_b 0 0 1 0 @q_b 0 0 1 0
-- Retrieval info: CONNECT: @address_a 0 0 8 0 address_a 0 0 8 0
-- Retrieval info: CONNECT: @data_b 0 0 1 0 data_b 0 0 1 0
-- Retrieval info: CONNECT: @address_b 0 0 12 0 address_b 0 0 12 0
-- Retrieval info: CONNECT: @wren_b 0 0 0 0 wren_b 0 0 0 0
-- Retrieval info: CONNECT: @clock0 0 0 0 0 clock_a 0 0 0 0
-- Retrieval info: CONNECT: @clocken0 0 0 0 0 enable_a 0 0 0 0
-- Retrieval info: CONNECT: @clock1 0 0 0 0 clock_b 0 0 0 0
-- Retrieval info: CONNECT: @clocken1 0 0 0 0 enable_b 0 0 0 0
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: GEN_FILE: TYPE_NORMAL Altera_UP_SD_Card_Memory_Block.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL Altera_UP_SD_Card_Memory_Block.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL Altera_UP_SD_Card_Memory_Block.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL Altera_UP_SD_Card_Memory_Block.bsf TRUE FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL Altera_UP_SD_Card_Memory_Block_inst.vhd FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL Altera_UP_SD_Card_Memory_Block_waveforms.html TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL Altera_UP_SD_Card_Memory_Block_wave*.jpg FALSE
-- Retrieval info: LIB_FILE: altera_mf
| gpl-2.0 | 4eba24e160e01c3e4f99c703503972f0 | 0.686825 | 3.314195 | false | false | false | false |
cafe-alpha/wascafe | v13/r07c_de10_20201014_abus4/wasca/synthesis/submodules/Altera_UP_SD_Card_Avalon_Interface.vhd | 7 | 23,187 | -- (C) 2001-2015 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
----------------------------------------------------------------------------------------------------------------
-- This is an FSM that allows access to the SD Card IP core via the Avalon Interconnect.
--
-- This module takes a range of addresses on the Avalon Interconnect. Specifically:
-- - 0x00000000 to 0x000001ff
-- word addressable buffer space. The data to be written to the SD card as well
-- as data read from the SD card can be accessed here.
--
-- - 0x00000200 to 0x0000020f
-- 128-bit containing the Card Identification Number. The meaning of each bit is described in the
-- SD Card Physical Layer Specification Document.
--
-- - 0x00000210 to 0x0000021f
-- 128-bit register containing Card Specific Data. The meaning of each bit is described in the
-- SD Card Physical Layer Specification Document.
--
-- - 0x00000220 to 0x00000223
-- 32-bit register containing Operating Conditions Register. The meaning of each bit is described
-- in the SD Card Physical Layer Specification Document.
--
-- - 0x00000224 to 0x00000227
-- 32-bit register containing the Status Register. The meaning of each bit is described
-- in the SD Card Physical Layer Specification Document. However, if the card is not connected or the
-- status register could not be read from the SD card, this register will contain invalid data. In such
-- a case, wait for a card to be connected by checking the Auxiliary Status Register (UP Core Specific), and
-- a command 13 (SEND_STATUS) to update the contents of this register when possible. If a card is connected then
-- the Auxiliary Status Register can be polled until such a time that Status Register is valid, as the SD Card
-- interface circuit updates the status register approximately every 0.1 of a second, and after every command
-- is executed.
--
-- - 0x00000228 to 0x000000229
-- 16-bit register containing the Relative Card Address. This address uniquely identifies a card
-- connected to the SD Card slot.
--
-- - 0x0000022C to 0x00000022F
-- 32-bit register used to set the argument for a command to be sent to the SD Card.
--
-- - 0x00000230 to 0x000000231
-- 16-bit register used to send a command to an SD card. Once written, the interface will issue the
-- specified command. The meaning of each bit in this register is as follows:
-- - 0-5 - command index. This is a command index as per SD Card Physical Layer specification document.
-- - 6 - use most recent RCA. If this bit is set, the command argument will be replaced with the contents of
-- the Relative Card Address register, followed by 16 0s. For commands that require RCA to be sent as
-- an argument, this bit should be set and users will not need to specify RCA themselves.
-- - 7-15 - currently unused bits. They will be ignored.
-- NOTE: If a specified command is determined to be invalid, or the card is not connected to the SD Card socket,
-- then the SD Card interface circuit will not issue the command.
--
-- - 0x00000234 to 0x00000235
-- 16-bit register with Auxiliary Status Register. This is the Altera UP SD Card Interface status. The meaning of
-- the bits is as follows:
-- - 0 - last command valid - Set to '1' if the most recently user issued command was valid.
-- - 1 - card connected - Set to '1' if at present an SD card
-- - 2 - execution in progress - Set to '1' if the command recently issued is currently being executed. If true,
-- then the current state of SD Card registers should be ignored.
-- - 3 - status register valid - Set to '1' if the status register is valid.
-- - 4 - command timed out - Set to '1' if the last command timed out.
-- - 5 - crc failed - Set to '1' if the last command failed a CRC check.
-- - 6-15 - unused.
--
-- - 0x00000238 to 0x0000023B
-- 32-bit register containing the 32-bit R1 response message. Use it to test validity of the response. This register
-- will not store the response to SEND_STATUS command. Insteand, read the SD_status register at location 0x00000224.
--
-- Date: December 8, 2008
-- NOTES/REVISIONS:
-- December 17, 2008 - added R1 response register to the core. It is now available at 0x00000238.
----------------------------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity Altera_UP_SD_Card_Avalon_Interface is
generic (
ADDRESS_BUFFER : std_logic_vector(7 downto 0) := "00000000";
ADDRESS_CID : std_logic_vector(7 downto 0) := "10000000";
ADDRESS_CSD : std_logic_vector(7 downto 0) := "10000100";
ADDRESS_OCR : std_logic_vector(7 downto 0) := "10001000";
ADDRESS_SR : std_logic_vector(7 downto 0) := "10001001";
ADDRESS_RCA : std_logic_vector(7 downto 0) := "10001010";
ADDRESS_ARGUMENT : std_logic_vector(7 downto 0) := "10001011";
ADDRESS_COMMAND : std_logic_vector(7 downto 0) := "10001100";
ADDRESS_ASR : std_logic_vector(7 downto 0) := "10001101";
ADDRESS_R1 : std_logic_vector(7 downto 0) := "10001110"
);
port
(
-- Clock and Reset signals
i_clock : in STD_LOGIC;
i_reset_n : in STD_LOGIC; -- Asynchronous reset
-- Avalon Interconnect Signals
i_avalon_address : in STD_LOGIC_VECTOR(7 downto 0);
i_avalon_chip_select : in STD_LOGIC;
i_avalon_read : in STD_LOGIC;
i_avalon_write : in STD_LOGIC;
i_avalon_byteenable : in STD_LOGIC_VECTOR(3 downto 0);
i_avalon_writedata : in STD_LOGIC_VECTOR(31 downto 0);
o_avalon_readdata : out STD_LOGIC_VECTOR(31 downto 0);
o_avalon_waitrequest : out STD_LOGIC;
-- SD Card interface ports
b_SD_cmd : inout STD_LOGIC;
b_SD_dat : inout STD_LOGIC;
b_SD_dat3 : inout STD_LOGIC;
o_SD_clock : out STD_LOGIC
);
end entity;
architecture rtl of Altera_UP_SD_Card_Avalon_Interface is
component Altera_UP_SD_Card_Interface is
port
(
i_clock : in std_logic;
i_reset_n : in std_logic;
-- Command interface
b_SD_cmd : inout std_logic;
b_SD_dat : inout std_logic;
b_SD_dat3 : inout std_logic;
i_command_ID : in std_logic_vector(5 downto 0);
i_argument : in std_logic_vector(31 downto 0);
i_user_command_ready : in std_logic;
o_SD_clock : out std_logic;
o_card_connected : out std_logic;
o_command_completed : out std_logic;
o_command_valid : out std_logic;
o_command_timed_out : out std_logic;
o_command_crc_failed : out std_logic;
-- Buffer access
i_buffer_enable : in std_logic;
i_buffer_address : in std_logic_vector(7 downto 0);
i_buffer_write : in std_logic;
i_buffer_data_in : in std_logic_vector(15 downto 0);
o_buffer_data_out : out std_logic_vector(15 downto 0);
-- Show SD Card registers as outputs
o_SD_REG_card_identification_number : out std_logic_vector(127 downto 0);
o_SD_REG_relative_card_address : out std_logic_vector(15 downto 0);
o_SD_REG_operating_conditions_register : out std_logic_vector(31 downto 0);
o_SD_REG_card_specific_data : out std_logic_vector(127 downto 0);
o_SD_REG_status_register : out std_logic_vector(31 downto 0);
o_SD_REG_response_R1 : out std_logic_vector(31 downto 0);
o_SD_REG_status_register_valid : out std_logic
);
end component;
-- Build an enumerated type for the state machine. On reset always reset the DE2 and read the state
-- of the switches.
type buffer_state_type is ( s_RESET, s_WAIT_REQUEST, s_READ_FIRST_WORD, s_READ_SECOND_WORD, s_RECEIVE_FIRST_WORD,
s_RECEIVE_SECOND_WORD, s_WR_READ_FIRST_WORD, s_WR_READ_FIRST_WORD_DELAY, s_WRITE_FIRST_BYTE, s_WRITE_FIRST_WORD,
s_WR_READ_SECOND_WORD, s_WR_READ_SECOND_WORD_DELAY, s_WRITE_SECOND_BYTE, s_WRITE_SECOND_WORD, s_WAIT_RELEASE);
type command_state_type is (s_RESET_CMD, s_WAIT_COMMAND, s_WAIT_RESPONSE, s_UPDATE_AUX_SR);
-- Register to hold the current state
signal current_state : buffer_state_type;
signal next_state : buffer_state_type;
signal current_cmd_state : command_state_type;
signal next_cmd_state : command_state_type;
-------------------
-- Local signals
-------------------
-- REGISTERED
signal auxiliary_status_reg : std_logic_vector(5 downto 0);
signal buffer_data_out_reg : std_logic_vector(31 downto 0);
signal buffer_data_in_reg : std_logic_vector(31 downto 0);
signal buffer_data_out : std_logic_vector(15 downto 0);
signal command_ID_reg : std_logic_vector( 5 downto 0);
signal argument_reg : std_logic_vector(31 downto 0);
signal avalon_address : std_logic_vector(7 downto 0);
signal avalon_byteenable : std_logic_vector(3 downto 0);
-- UNREGISTERED
signal buffer_address : std_logic_vector(7 downto 0);
signal buffer_data_in : std_logic_vector(15 downto 0);
signal SD_REG_card_identification_number : std_logic_vector(127 downto 0);
signal SD_REG_relative_card_address : std_logic_vector(15 downto 0);
signal SD_REG_operating_conditions_register : std_logic_vector(31 downto 0);
signal SD_REG_card_specific_data : std_logic_vector(127 downto 0);
signal SD_REG_status_register : std_logic_vector(31 downto 0);
signal SD_REG_response_R1 : std_logic_vector(31 downto 0);
signal command_ready, send_command_ready,
command_valid, command_completed, card_connected : std_logic;
signal status_reg_valid, argument_write : std_logic;
signal read_buffer_request, write_buffer_request, buffer_enable, buffer_write : std_logic;
signal command_timed_out, command_crc_failed : std_logic;
begin
-- Define state transitions for buffer interface.
state_transitions_buffer: process (current_state, read_buffer_request, write_buffer_request, i_avalon_byteenable, avalon_byteenable)
begin
case current_state is
when s_RESET =>
-- Reset local registers.
next_state <= s_WAIT_REQUEST;
when s_WAIT_REQUEST =>
-- Wait for a user command.
if (read_buffer_request = '1') then
next_state <= s_READ_FIRST_WORD;
elsif (write_buffer_request = '1') then
if ((i_avalon_byteenable(1) = '1') and (i_avalon_byteenable(0) = '1')) then
next_state <= s_WRITE_FIRST_WORD;
elsif ((i_avalon_byteenable(3) = '1') and (i_avalon_byteenable(2) = '1')) then
next_state <= s_WRITE_SECOND_WORD;
elsif ((i_avalon_byteenable(1) = '1') or (i_avalon_byteenable(0) = '1')) then
next_state <= s_WR_READ_FIRST_WORD;
elsif ((i_avalon_byteenable(3) = '1') or (i_avalon_byteenable(2) = '1')) then
next_state <= s_WR_READ_SECOND_WORD;
else
next_state <= s_WAIT_REQUEST;
end if;
else
next_state <= s_WAIT_REQUEST;
end if;
when s_READ_FIRST_WORD =>
-- Read first 16-bit word from the buffer
next_state <= s_READ_SECOND_WORD;
when s_READ_SECOND_WORD =>
-- Read second 16-bit word from the buffer
next_state <= s_RECEIVE_FIRST_WORD;
when s_RECEIVE_FIRST_WORD =>
-- Store first word read
next_state <= s_RECEIVE_SECOND_WORD;
when s_RECEIVE_SECOND_WORD =>
-- Store second word read
next_state <= s_WAIT_RELEASE;
-- The following states control writing to the buffer. To write a single byte it is necessary to read a
-- word and then write it back, changing only on of its bytes.
when s_WR_READ_FIRST_WORD =>
-- Read first 16-bit word from the buffer
next_state <= s_WR_READ_FIRST_WORD_DELAY;
when s_WR_READ_FIRST_WORD_DELAY =>
-- Wait a cycle
next_state <= s_WRITE_FIRST_BYTE;
when s_WRITE_FIRST_BYTE =>
-- Write one of the bytes in the given word into the memory.
if ((avalon_byteenable(3) = '1') and (avalon_byteenable(2) = '1')) then
next_state <= s_WRITE_SECOND_WORD;
elsif ((avalon_byteenable(3) = '1') or (avalon_byteenable(2) = '1')) then
next_state <= s_WR_READ_SECOND_WORD;
else
next_state <= s_WAIT_RELEASE;
end if;
when s_WR_READ_SECOND_WORD =>
-- Read second 16-bit word from the buffer
next_state <= s_WR_READ_SECOND_WORD_DELAY;
when s_WR_READ_SECOND_WORD_DELAY =>
-- Wait a cycle
next_state <= s_WRITE_SECOND_BYTE;
when s_WRITE_SECOND_BYTE =>
-- Write one of the bytes in the given word into the memory.
next_state <= s_WAIT_RELEASE;
-- Full word writing can be done without reading the word in the first place.
when s_WRITE_FIRST_WORD =>
-- Write the first word into memory
if ((avalon_byteenable(3) = '1') and (avalon_byteenable(2) = '1')) then
next_state <= s_WRITE_SECOND_WORD;
elsif ((avalon_byteenable(3) = '1') or (avalon_byteenable(2) = '1')) then
next_state <= s_WR_READ_SECOND_WORD;
else
next_state <= s_WAIT_RELEASE;
end if;
when s_WRITE_SECOND_WORD =>
-- Write the second word into memory
next_state <= s_WAIT_RELEASE;
when s_WAIT_RELEASE =>
-- if ((read_buffer_request = '1') or (write_buffer_request = '1')) then
-- next_state <= s_WAIT_RELEASE;
-- else
next_state <= s_WAIT_REQUEST;
-- end if;
when others =>
-- Make sure to start in the reset state if the circuit powers up in an odd state.
next_state <= s_RESET;
end case;
end process;
-- State Registers
buffer_state_regs: process(i_clock, i_reset_n)
begin
if (i_reset_n = '0') then
current_state <= s_RESET;
elsif(rising_edge(i_clock)) then
current_state <= next_state;
end if;
end process;
helper_regs: process(i_clock, i_reset_n)
begin
if (i_reset_n = '0') then
avalon_address <= (OTHERS => '0');
buffer_data_out_reg <= (OTHERS => '0');
buffer_data_in_reg <= (OTHERS => '0');
avalon_byteenable <= (OTHERS => '0');
elsif(rising_edge(i_clock)) then
if (current_state = s_WAIT_REQUEST) then
avalon_address <= i_avalon_address;
buffer_data_in_reg <= i_avalon_writedata;
avalon_byteenable <= i_avalon_byteenable;
end if;
if (current_state = s_RECEIVE_FIRST_WORD) then
buffer_data_out_reg(15 downto 0) <= buffer_data_out;
end if;
if (current_state = s_RECEIVE_SECOND_WORD) then
buffer_data_out_reg(31 downto 16) <= buffer_data_out;
end if;
end if;
end process;
-- FSM outputs
o_avalon_waitrequest <= (read_buffer_request or write_buffer_request) when (not (current_state = s_WAIT_RELEASE)) else '0';
buffer_address(7 downto 1) <= avalon_address(6 downto 0);
buffer_address(0) <= '1' when ( (current_state = s_READ_SECOND_WORD) or (current_state = s_WRITE_SECOND_WORD) or
(current_state = s_WR_READ_SECOND_WORD) or (current_state = s_WRITE_SECOND_BYTE)) else
'0';
buffer_enable <= '1' when ( (current_state = s_READ_FIRST_WORD) or (current_state = s_WR_READ_FIRST_WORD) or
(current_state = s_READ_SECOND_WORD) or (current_state = s_WR_READ_SECOND_WORD) or
(current_state = s_WRITE_FIRST_WORD) or (current_state = s_WRITE_FIRST_BYTE) or
(current_state = s_WRITE_SECOND_WORD) or (current_state = s_WRITE_SECOND_BYTE)) else
'0';
buffer_write <= '1' when ( (current_state = s_WRITE_FIRST_WORD) or (current_state = s_WRITE_FIRST_BYTE) or
(current_state = s_WRITE_SECOND_WORD) or (current_state = s_WRITE_SECOND_BYTE)) else
'0';
buffer_data_in <= (buffer_data_out(15 downto 8) & buffer_data_in_reg(7 downto 0)) when ((current_state = s_WRITE_FIRST_BYTE) and (avalon_byteenable(1 downto 0) = "01")) else
(buffer_data_in_reg(15 downto 8) & buffer_data_out(7 downto 0)) when ((current_state = s_WRITE_FIRST_BYTE) and (avalon_byteenable(1 downto 0) = "10")) else
(buffer_data_out(15 downto 8) & buffer_data_in_reg(23 downto 16)) when ((current_state = s_WRITE_SECOND_BYTE) and (avalon_byteenable(3 downto 2) = "01")) else
(buffer_data_in_reg(31 downto 24) & buffer_data_out(7 downto 0)) when ((current_state = s_WRITE_SECOND_BYTE) and (avalon_byteenable(3 downto 2) = "10")) else
buffer_data_in_reg(15 downto 0) when (current_state = s_WRITE_FIRST_WORD) else
buffer_data_in_reg(31 downto 16);
-- Glue Logic
read_buffer_request <= (not i_avalon_address(7)) and (i_avalon_chip_select) and (i_avalon_read);
write_buffer_request <= (not i_avalon_address(7)) and (i_avalon_chip_select) and (i_avalon_write);
-- Define state transitions for command interface.
state_transitions_cmd: process (current_cmd_state, command_completed, command_valid, command_ready)
begin
case current_cmd_state is
when s_RESET_CMD =>
-- Reset local registers.
next_cmd_state <= s_WAIT_COMMAND;
when s_WAIT_COMMAND =>
-- Wait for a user command.
if (command_ready = '1') then
next_cmd_state <= s_WAIT_RESPONSE;
else
next_cmd_state <= s_WAIT_COMMAND;
end if;
when s_WAIT_RESPONSE =>
-- Generate a predefined command to the SD card. This is the identification process for the SD card.
if ((command_completed = '1') or (command_valid = '0')) then
next_cmd_state <= s_UPDATE_AUX_SR;
else
next_cmd_state <= s_WAIT_RESPONSE;
end if;
when s_UPDATE_AUX_SR =>
-- Update the Auxiliary status register.
if (command_ready = '1') then
next_cmd_state <= s_UPDATE_AUX_SR;
else
next_cmd_state <= s_WAIT_COMMAND;
end if;
when others =>
-- Make sure to start in the reset state if the circuit powers up in an odd state.
next_cmd_state <= s_RESET_CMD;
end case;
end process;
-- State registers
cmd_state_regs: process(i_clock, i_reset_n)
begin
if (i_reset_n = '0') then
current_cmd_state <= s_RESET_CMD;
elsif(rising_edge(i_clock)) then
current_cmd_state <= next_cmd_state;
end if;
end process;
-- FSM outputs
send_command_ready <= '1' when ((current_cmd_state = s_WAIT_RESPONSE) or (current_cmd_state = s_UPDATE_AUX_SR)) else '0';
-- Glue logic
command_ready <= '1' when ( (i_avalon_chip_select = '1') and (i_avalon_write = '1') and
(i_avalon_address = ADDRESS_COMMAND)) else '0';
argument_write <= '1' when ((i_avalon_chip_select = '1') and (i_avalon_write = '1') and
(i_avalon_address = ADDRESS_ARGUMENT)) else '0';
-- Local Registers
local_regs: process(i_clock, i_reset_n, current_cmd_state, card_connected, command_valid, i_avalon_writedata, command_completed, command_ready)
begin
if (i_reset_n = '0') then
auxiliary_status_reg <= "000000";
command_ID_reg <= (OTHERS => '0');
elsif(rising_edge(i_clock)) then
-- AUX Status Register
if ((current_cmd_state = s_WAIT_RESPONSE) or (current_cmd_state = s_UPDATE_AUX_SR)) then
auxiliary_status_reg(2) <= not command_completed;
auxiliary_status_reg(4) <= command_timed_out;
auxiliary_status_reg(5) <= command_crc_failed;
end if;
auxiliary_status_reg(0) <= command_valid;
auxiliary_status_reg(1) <= card_connected;
auxiliary_status_reg(3) <= status_reg_valid;
-- Command
if (command_ready = '1') then
command_ID_reg <= i_avalon_writedata(5 downto 0);
end if;
end if;
end process;
argument_regs_processing: process(i_clock, i_reset_n, current_cmd_state, i_avalon_writedata, command_ready)
begin
if (i_reset_n = '0') then
argument_reg <= (OTHERS => '0');
elsif(rising_edge(i_clock)) then
-- Argument register
if ((command_ready = '1') and ( i_avalon_writedata(6) = '1')) then
argument_reg <= SD_REG_relative_card_address & "0000000000000000";
elsif (argument_write = '1') then
argument_reg <= i_avalon_writedata;
end if;
end if;
end process;
o_avalon_readdata <= buffer_data_out_reg when (not (current_state = s_WAIT_REQUEST)) else
SD_REG_card_identification_number(31 downto 0) when (i_avalon_address = ADDRESS_CID) else
SD_REG_card_identification_number(63 downto 32) when (i_avalon_address = ADDRESS_CID(7 downto 2) & "01") else
SD_REG_card_identification_number(95 downto 64) when (i_avalon_address = ADDRESS_CID(7 downto 2) & "10") else
SD_REG_card_identification_number(127 downto 96) when (i_avalon_address = ADDRESS_CID(7 downto 2) & "11") else
SD_REG_card_specific_data(31 downto 0) when (i_avalon_address = ADDRESS_CSD) else
SD_REG_card_specific_data(63 downto 32) when (i_avalon_address = ADDRESS_CSD(7 downto 2) & "01") else
SD_REG_card_specific_data(95 downto 64) when (i_avalon_address = ADDRESS_CSD(7 downto 2) & "10") else
SD_REG_card_specific_data(127 downto 96) when (i_avalon_address = ADDRESS_CSD(7 downto 2) & "11") else
SD_REG_operating_conditions_register when (i_avalon_address = ADDRESS_OCR) else
SD_REG_status_register when (i_avalon_address = ADDRESS_SR) else
("0000000000000000" & SD_REG_relative_card_address)when (i_avalon_address = ADDRESS_RCA) else
argument_reg when (i_avalon_address = ADDRESS_ARGUMENT) else
("00000000000000000000000000" & command_ID_reg) when (i_avalon_address = ADDRESS_COMMAND) else
SD_REG_response_R1 when (i_avalon_address = ADDRESS_R1) else
("00000000000000000000000000" & auxiliary_status_reg);
-- Instantiated Components
SD_Card_Port: Altera_UP_SD_Card_Interface
port map
(
i_clock => i_clock,
i_reset_n => i_reset_n,
-- Command interface
b_SD_cmd => b_SD_cmd,
b_SD_dat => b_SD_dat,
b_SD_dat3 => b_SD_dat3,
i_command_ID => command_ID_reg,
i_argument => argument_reg,
i_user_command_ready => send_command_ready,
o_SD_clock => o_SD_clock,
o_card_connected => card_connected,
o_command_completed => command_completed,
o_command_valid => command_valid,
o_command_timed_out => command_timed_out,
o_command_crc_failed => command_crc_failed,
-- Buffer access
i_buffer_enable => buffer_enable,
i_buffer_address => buffer_address,
i_buffer_write => buffer_write,
i_buffer_data_in => buffer_data_in,
o_buffer_data_out => buffer_data_out,
-- Show SD Card registers as outputs
o_SD_REG_card_identification_number => SD_REG_card_identification_number,
o_SD_REG_relative_card_address => SD_REG_relative_card_address,
o_SD_REG_operating_conditions_register => SD_REG_operating_conditions_register,
o_SD_REG_card_specific_data => SD_REG_card_specific_data,
o_SD_REG_status_register => SD_REG_status_register,
o_SD_REG_response_R1 => SD_REG_response_R1,
o_SD_REG_status_register_valid => status_reg_valid
);
end rtl;
| gpl-2.0 | b3cc8ae11e6e86c8ca1585db33152ced | 0.666235 | 3.137194 | false | false | false | false |
impedimentToProgress/UCI-BlueChip | AttackFiles/Attacks/privEsc/lib/techmap/maps/allpads.vhd | 2 | 15,060 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
----------------------------------------------------------------------------
-- Package: allpads
-- File: allpads.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: All tech pads
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
package allpads is
component apa3_clkpad
generic (level : integer := 0; voltage : integer := 0);
port (pad : in std_ulogic; o : out std_ulogic);
end component;
component axcel_inpad
generic (level : integer := 0; voltage : integer := 0);
port (pad : in std_ulogic; o : out std_ulogic);
end component;
component axcel_iopad
generic (level : integer := 0; slew : integer := 0;
voltage : integer := 0; strength : integer := 0);
port (pad : inout std_ulogic; i, en : in std_ulogic; o : out std_ulogic);
end component;
component axcel_outpad
generic (level : integer := 0; slew : integer := 0;
voltage : integer := 0; strength : integer := 0);
port (pad : out std_ulogic; i : in std_ulogic);
end component;
component axcel_odpad
generic (level : integer := 0; slew : integer := 0;
voltage : integer := 0; strength : integer := 0);
port (pad : out std_ulogic; i : in std_ulogic);
end component;
component axcel_toutpad
generic (level : integer := 0; slew : integer := 0;
voltage : integer := 0; strength : integer := 0);
port (pad : out std_ulogic; i, en : in std_ulogic);
end component;
component axcel_clkpad
generic (level : integer := 0; voltage : integer := 0);
port (pad : in std_ulogic; o : out std_ulogic);
end component;
component axcel_inpad_ds
generic (level : integer := lvds; voltage : integer := x33v);
port (padp, padn : in std_ulogic; o : out std_ulogic);
end component;
component axcel_outpad_ds
generic (level : integer := lvds; voltage : integer := x33v);
port (padp, padn : out std_ulogic; i : in std_ulogic);
end component;
component atc18_inpad
generic (level : integer := 0; voltage : integer := 0);
port (pad : in std_logic; o : out std_logic);
end component;
component atc18_iopad
generic (level : integer := 0; slew : integer := 0;
voltage : integer := 0; strength : integer := 0);
port (pad : inout std_logic; i, en : in std_logic; o : out std_logic);
end component;
component atc18_outpad
generic (level : integer := 0; slew : integer := 0;
voltage : integer := 0; strength : integer := 0);
port (pad : out std_logic; i : in std_logic);
end component;
component atc18_odpad
generic (level : integer := 0; slew : integer := 0;
voltage : integer := 0; strength : integer := 0);
port (pad : out std_logic; i : in std_logic);
end component;
component atc18_toutpad
generic (level : integer := 0; slew : integer := 0;
voltage : integer := 0; strength : integer := 0);
port (pad : out std_logic; i, en : in std_logic);
end component;
component atc18_clkpad
generic (level : integer := 0; voltage : integer := 0);
port (pad : in std_logic; o : out std_logic);
end component;
component ihp25_inpad
generic(level : integer := 0; voltage : integer := 0);
port (pad : in std_logic; o : out std_logic);
end component;
component ihp25rh_inpad
generic(level : integer := 0; voltage : integer := 0);
port (pad : in std_logic; o : out std_logic);
end component;
component ihp25_iopad
generic (level : integer := 0; slew : integer := 0;
voltage : integer := 0; strength : integer := 0);
port (pad : inout std_logic; i, en : in std_logic; o : out std_logic);
end component;
component ihp25rh_iopad
generic (level : integer := 0; slew : integer := 0;
voltage : integer := 0; strength : integer := 0);
port (pad : inout std_logic; i, en : in std_logic; o : out std_logic);
end component;
component ihp25_outpad
generic (level : integer := 0; slew : integer := 0;
voltage : integer := 0; strength : integer := 0);
port (pad : out std_logic; i : in std_logic);
end component;
component ihp25rh_outpad
generic (level : integer := 0; slew : integer := 0;
voltage : integer := 0; strength : integer := 0);
port (pad : out std_logic; i : in std_logic);
end component;
component ihp25_toutpad
generic (level : integer := 0; slew : integer := 0;
voltage : integer := 0; strength : integer := 0);
port (pad : out std_ulogic; i, en : in std_logic);
end component;
component ihp25rh_toutpad
generic (level : integer := 0; slew : integer := 0;
voltage : integer := 0; strength : integer := 0);
port (pad : out std_ulogic; i, en : in std_logic);
end component;
component ihp25_clkpad
generic (level : integer := 0; voltage : integer := 0);
port (pad : in std_ulogic; o : out std_ulogic);
end component;
component ihp25rh_clkpad
generic (level : integer := 0; voltage : integer := 0);
port (pad : in std_ulogic; o : out std_ulogic);
end component;
component rhumc_inpad
generic (level : integer := 0; voltage : integer := 0; filter : integer := 0);
port (pad : in std_logic; o : out std_logic);
end component;
component rhumc_iopad
generic (level : integer := 0; slew : integer := 0;
voltage : integer := 0; strength : integer := 0);
port (pad : inout std_logic; i, en : in std_logic; o : out std_logic);
end component;
component rhumc_outpad
generic (level : integer := 0; slew : integer := 0;
voltage : integer := 0; strength : integer := 0);
port (pad : out std_logic; i : in std_logic);
end component;
component rhumc_toutpad
generic (level : integer := 0; slew : integer := 0;
voltage : integer := 0; strength : integer := 0);
port (pad : out std_logic; i, en : in std_logic);
end component;
component umc_inpad
generic (level : integer := 0; voltage : integer := 0; filter : integer := 0);
port (pad : in std_logic; o : out std_logic);
end component;
component umc_iopad
generic (level : integer := 0; slew : integer := 0;
voltage : integer := 0; strength : integer := 0);
port (pad : inout std_logic; i, en : in std_logic; o : out std_logic);
end component;
component umc_outpad
generic (level : integer := 0; slew : integer := 0;
voltage : integer := 0; strength : integer := 0);
port (pad : out std_logic; i : in std_logic);
end component;
component umc_toutpad
generic (level : integer := 0; slew : integer := 0;
voltage : integer := 0; strength : integer := 0);
port (pad : out std_logic; i, en : in std_logic);
end component;
component virtex_inpad
generic (level : integer := 0; voltage : integer := x33v);
port (pad : in std_ulogic; o : out std_ulogic);
end component;
component virtex_iopad
generic (level : integer := 0; slew : integer := 0;
voltage : integer := x33v; strength : integer := 12);
port (pad : inout std_ulogic; i, en : in std_ulogic; o : out std_ulogic);
end component;
component virtex_outpad
generic (level : integer := 0; slew : integer := 0;
voltage : integer := x33v; strength : integer := 12);
port (pad : out std_ulogic; i : in std_ulogic);
end component;
component virtex_odpad
generic (level : integer := 0; slew : integer := 0;
voltage : integer := x33v; strength : integer := 12);
port (pad : out std_ulogic; i : in std_ulogic);
end component;
component virtex_toutpad
generic (level : integer := 0; slew : integer := 0;
voltage : integer := x33v; strength : integer := 12);
port (pad : out std_ulogic; i, en : in std_ulogic);
end component;
component virtex_skew_outpad
generic (level : integer := 0; slew : integer := 0;
voltage : integer := x33v; strength : integer := 12; skew : integer := 0);
port (pad : out std_ulogic; i : in std_ulogic; rst : in std_ulogic;
o : out std_ulogic);
end component;
component virtex_clkpad
generic (level : integer := 0; voltage : integer := x33v; arch : integer := 0; hf : integer := 0);
port (pad : in std_ulogic; o : out std_ulogic; rstn : std_ulogic := '1');
end component;
component virtex_inpad_ds
generic (level : integer := lvds; voltage : integer := x33v);
port (padp, padn : in std_ulogic; o : out std_ulogic);
end component;
component virtex5_iopad_ds
generic (level : integer := 0; slew : integer := 0;
voltage : integer := x33v; strength : integer := 12);
port (padp, padn : inout std_ulogic; i, en : in std_ulogic; o : out std_ulogic);
end component;
component virtex4_inpad_ds
generic (level : integer := lvds; voltage : integer := x33v);
port (padp, padn : in std_ulogic; o : out std_ulogic);
end component;
component virtex_outpad_ds
generic (level : integer := lvds; voltage : integer := x33v);
port (padp, padn : out std_ulogic; i : in std_ulogic);
end component;
component virtex5_outpad_ds
generic (level : integer := lvds; voltage : integer := x33v);
port (padp, padn : out std_ulogic; i : in std_ulogic);
end component;
component virtex4_clkpad_ds is
generic (level : integer := lvds; voltage : integer := x33v);
port (padp, padn : in std_ulogic; o : out std_ulogic);
end component;
component virtex_clkpad_ds is
generic (level : integer := lvds; voltage : integer := x33v);
port (padp, padn : in std_ulogic; o : out std_ulogic);
end component;
component rh_lib18t_inpad
generic ( voltage : integer := 0; filter : integer := 0);
port (pad : in std_logic; o : out std_logic);
end component;
component rh_lib18t_iopad
generic ( strength : integer := 0);
port (pad : inout std_logic; i, en : in std_logic; o : out std_logic);
end component;
component rh_lib18t_inpad_ds is
port (padp, padn : in std_ulogic; o : out std_ulogic; en : in std_ulogic);
end component;
component rh_lib18t_outpad_ds is
port (padp, padn : out std_ulogic; i, en : in std_ulogic);
end component;
component ut025crh_inpad
generic ( level : integer := 0; voltage : integer := 0; filter : integer := 0);
port (pad : in std_logic; o : out std_logic);
end component;
component ut025crh_iopad is
generic (level : integer := 0; slew : integer := 0;
voltage : integer := 0; strength : integer := 0);
port (pad : inout std_ulogic; i, en : in std_ulogic; o : out std_ulogic);
end component;
component ut025crh_outpad
generic (level : integer := 0; slew : integer := 0;
voltage : integer := 0; strength : integer := 0);
port (pad : out std_ulogic; i : in std_ulogic);
end component;
component ut025crh_toutpad
generic (level : integer := 0; slew : integer := 0;
voltage : integer := 0; strength : integer := 0);
port (pad : out std_ulogic; i, en : in std_ulogic);
end component;
component ut025crh_lvds_combo
generic (voltage : integer := 0; width : integer := 1);
port (odpadp, odpadn, ospadp, ospadn : out std_logic_vector(0 to width-1);
odval, osval, en : in std_logic_vector(0 to width-1);
idpadp, idpadn, ispadp, ispadn : in std_logic_vector(0 to width-1);
idval, isval : out std_logic_vector(0 to width-1));
end component;
component rhumc_lvds_combo
generic (voltage : integer := 0; width : integer := 1);
port (odpadp, odpadn, ospadp, ospadn : out std_logic_vector(0 to width-1);
odval, osval, en : in std_logic_vector(0 to width-1);
idpadp, idpadn, ispadp, ispadn : in std_logic_vector(0 to width-1);
idval, isval : out std_logic_vector(0 to width-1);
lvdsref : in std_logic);
end component;
component umc_lvds_combo
generic (voltage : integer := 0; width : integer := 1);
port (odpadp, odpadn, ospadp, ospadn : out std_logic_vector(0 to width-1);
odval, osval, en : in std_logic_vector(0 to width-1);
idpadp, idpadn, ispadp, ispadn : in std_logic_vector(0 to width-1);
idval, isval : out std_logic_vector(0 to width-1);
lvdsref : in std_logic);
end component;
component peregrine_inpad is
generic (level : integer := 0; voltage : integer := 0; filter : integer := 0;
strength : integer := 0);
port (pad : in std_ulogic; o : out std_ulogic);
end component;
component peregrine_iopad is
generic (level : integer := 0; slew : integer := 0;
voltage : integer := 0; strength : integer := 0);
port (pad : inout std_ulogic; i, en : in std_ulogic; o : out std_ulogic);
end component;
component peregrine_toutpad is
generic (level : integer := 0; slew : integer := 0;
voltage : integer := 0; strength : integer := 0);
port (pad : out std_ulogic; i, en : in std_ulogic);
end component;
component nextreme_inpad
generic (level : integer := 0; voltage : integer := 0);
port (pad : in std_logic; o : out std_logic);
end component;
component nextreme_iopad
generic (level : integer := 0; slew : integer := 0;
voltage : integer := 0; strength : integer := 0);
port (pad : inout std_logic; i, en : in std_logic; o : out std_logic);
end component;
component nextreme_toutpad
generic (level : integer := 0; slew : integer := 0;
voltage : integer := 0; strength : integer := 0);
port (pad : out std_logic; i, en : in std_logic);
end component;
component atc18rha_inpad
generic (level : integer := 0; voltage : integer := 0);
port (pad : in std_logic; o : out std_logic);
end component;
component atc18rha_iopad
generic (level : integer := 0; slew : integer := 0;
voltage : integer := 0; strength : integer := 0);
port (pad : inout std_logic; i, en : in std_logic; o : out std_logic);
end component;
component atc18rha_outpad
generic (level : integer := 0; slew : integer := 0;
voltage : integer := 0; strength : integer := 0);
port (pad : out std_logic; i : in std_logic);
end component;
component atc18rha_odpad
generic (level : integer := 0; slew : integer := 0;
voltage : integer := 0; strength : integer := 0);
port (pad : out std_logic; i : in std_logic);
end component;
component atc18rha_toutpad
generic (level : integer := 0; slew : integer := 0;
voltage : integer := 0; strength : integer := 0);
port (pad : out std_logic; i, en : in std_logic);
end component;
component atc18rha_clkpad
generic (level : integer := 0; voltage : integer := 0);
port (pad : in std_logic; o : out std_logic);
end component;
end;
| mit | 12ee963ee9f48314f8831ea5864ddb45 | 0.639641 | 3.529412 | false | false | false | false |
impedimentToProgress/UCI-BlueChip | VhdlParser/test/resultShadow.vhd | 1 | 141,450 | LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;
LIBRARY grlib;
USE grlib.sparc.all;
USE grlib.stdlib.all;
LIBRARY techmap;
USE techmap.gencomp.all;
LIBRARY gaisler;
USE gaisler.leon3.all;
USE gaisler.libiu.all;
USE gaisler.arith.all;
USE grlib.sparc_disas.all;
ENTITY iu3 IS
GENERIC (
nwin : integer RANGE 2 to 32 := 8;
isets : integer RANGE 1 to 4 := 2;
dsets : integer RANGE 1 to 4 := 2;
fpu : integer RANGE 0 to 15 := 0;
v8 : integer RANGE 0 to 63 := 2;
cp : integer RANGE 0 to 1 := 0;
mac : integer RANGE 0 to 1 := 0;
dsu : integer RANGE 0 to 1 := 1;
nwp : integer RANGE 0 to 4 := 2;
pclow : integer RANGE 0 to 2 := 2;
notag : integer RANGE 0 to 1 := 0;
index : integer RANGE 0 to 15 := 0;
lddel : integer RANGE 1 to 2 := 1;
irfwt : integer RANGE 0 to 1 := 1;
disas : integer RANGE 0 to 2 := 0;
tbuf : integer RANGE 0 to 64 := 2;
pwd : integer RANGE 0 to 2 := 0;
svt : integer RANGE 0 to 1 := 1;
rstaddr : integer := 16#00000#;
smp : integer RANGE 0 to 15 := 0;
fabtech : integer RANGE 0 to NTECH := 2;
clk2x : integer := 0
);
PORT (
clk : in std_ulogic;
rstn : in std_ulogic;
holdn : in std_ulogic;
ici : out icache_in_type;
ico : in icache_out_type;
dci : out dcache_in_type;
dco : in dcache_out_type;
rfi : out iregfile_in_type;
rfo : in iregfile_out_type;
irqi : in l3_irq_in_type;
irqo : out l3_irq_out_type;
dbgi : in l3_debug_in_type;
dbgo : out l3_debug_out_type;
muli : out mul32_in_type;
mulo : in mul32_out_type;
divi : out div32_in_type;
divo : in div32_out_type;
fpo : in fpc_out_type;
fpi : out fpc_in_type;
cpo : in fpc_out_type;
cpi : out fpc_in_type;
tbo : in tracebuf_out_type;
tbi : out tracebuf_in_type;
sclk : in std_ulogic
);
END ENTITY;
ARCHITECTURE rtl OF iu3 IS
CONSTANT ISETMSB : integer := 1 - 1;
CONSTANT DSETMSB : integer := 1 - 1;
CONSTANT RFBITS : integer RANGE 6 to 10 := 4 + 4;
CONSTANT NWINLOG2 : integer RANGE 1 to 5 := 3;
CONSTANT CWPOPT : boolean := ( 8 = ( 2 ** 3 ) );
CONSTANT CWPMIN : std_logic_vector ( 3 - 1 downto 0 ) := ( OTHERS => '0' );
CONSTANT CWPMAX : std_logic_vector ( 3 - 1 downto 0 ) := conv_std_logic_vector ( 8 - 1 , 3 );
CONSTANT FPEN : boolean := ( 0 /= 0 );
CONSTANT CPEN : boolean := ( 0 = 1 );
CONSTANT MULEN : boolean := ( 2 /= 0 );
CONSTANT MULTYPE : integer := ( 2 / 16 );
CONSTANT DIVEN : boolean := ( 2 /= 0 );
CONSTANT MACEN : boolean := ( 0 = 1 );
CONSTANT MACPIPE : boolean := ( 0 = 1 ) and ( 2 / 2 = 1 );
CONSTANT IMPL : integer := 15;
CONSTANT VER : integer := 3;
CONSTANT DBGUNIT : boolean := ( 1 = 1 );
CONSTANT TRACEBUF : boolean := ( 2 /= 0 );
CONSTANT TBUFBITS : integer := 10 + 1 - 4;
CONSTANT PWRD1 : boolean := false;
CONSTANT PWRD2 : boolean := 0 /= 0;
CONSTANT RS1OPT : boolean := ( is_fpga ( 2 ) /= 0 );
SUBTYPE word IS std_logic_vector ( 31 downto 0 );
SUBTYPE pctype IS std_logic_vector ( 31 downto 2 );
SUBTYPE rfatype IS std_logic_vector ( 4 + 4 - 1 downto 0 );
SUBTYPE cwptype IS std_logic_vector ( 3 - 1 downto 0 );
TYPE icdtype IS ARRAY ( 0 to 2 - 1 ) OF word;
TYPE dcdtype IS ARRAY ( 0 to 2 - 1 ) OF word;
SUBTYPE cword IS std_logic_vector ( 32 - 1 downto 0 );
TYPE cdatatype IS ARRAY ( 0 to 3 ) OF cword;
TYPE cpartype IS ARRAY ( 0 to 3 ) OF std_logic_vector ( 3 downto 0 );
TYPE iregfile_in_type IS RECORD
raddr1 : std_logic_vector ( 9 downto 0 );
raddr2 : std_logic_vector ( 9 downto 0 );
waddr : std_logic_vector ( 9 downto 0 );
wdata : std_logic_vector ( 31 downto 0 );
ren1 : std_ulogic;
ren2 : std_ulogic;
wren : std_ulogic;
diag : std_logic_vector ( 3 downto 0 );
END RECORD;
TYPE iregfile_out_type IS RECORD
data1 : std_logic_vector ( RDBITS - 1 downto 0 );
data2 : std_logic_vector ( RDBITS - 1 downto 0 );
END RECORD;
TYPE cctrltype IS RECORD
burst : std_ulogic;
dfrz : std_ulogic;
ifrz : std_ulogic;
dsnoop : std_ulogic;
dcs : std_logic_vector ( 1 downto 0 );
ics : std_logic_vector ( 1 downto 0 );
END RECORD;
TYPE icache_in_type IS RECORD
rpc : std_logic_vector ( 31 downto 0 );
fpc : std_logic_vector ( 31 downto 0 );
dpc : std_logic_vector ( 31 downto 0 );
rbranch : std_ulogic;
fbranch : std_ulogic;
inull : std_ulogic;
su : std_ulogic;
flush : std_ulogic;
flushl : std_ulogic;
fline : std_logic_vector ( 31 downto 3 );
pnull : std_ulogic;
END RECORD;
TYPE icache_out_type IS RECORD
data : cdatatype;
set : std_logic_vector ( 1 downto 0 );
mexc : std_ulogic;
hold : std_ulogic;
flush : std_ulogic;
diagrdy : std_ulogic;
diagdata : std_logic_vector ( IDBITS - 1 downto 0 );
mds : std_ulogic;
cfg : std_logic_vector ( 31 downto 0 );
idle : std_ulogic;
END RECORD;
TYPE icdiag_in_type IS RECORD
addr : std_logic_vector ( 31 downto 0 );
enable : std_ulogic;
read : std_ulogic;
tag : std_ulogic;
ctx : std_ulogic;
flush : std_ulogic;
ilramen : std_ulogic;
cctrl : cctrltype;
pflush : std_ulogic;
pflushaddr : std_logic_vector ( VA_I_U downto VA_I_D );
pflushtyp : std_ulogic;
ilock : std_logic_vector ( 0 to 3 );
scanen : std_ulogic;
END RECORD;
TYPE dcache_in_type IS RECORD
asi : std_logic_vector ( 7 downto 0 );
maddress : std_logic_vector ( 31 downto 0 );
eaddress : std_logic_vector ( 31 downto 0 );
edata : std_logic_vector ( 31 downto 0 );
size : std_logic_vector ( 1 downto 0 );
enaddr : std_ulogic;
eenaddr : std_ulogic;
nullify : std_ulogic;
lock : std_ulogic;
read : std_ulogic;
write : std_ulogic;
flush : std_ulogic;
flushl : std_ulogic;
dsuen : std_ulogic;
msu : std_ulogic;
esu : std_ulogic;
intack : std_ulogic;
END RECORD;
TYPE dcache_out_type IS RECORD
data : cdatatype;
set : std_logic_vector ( 1 downto 0 );
mexc : std_ulogic;
hold : std_ulogic;
mds : std_ulogic;
werr : std_ulogic;
icdiag : icdiag_in_type;
cache : std_ulogic;
idle : std_ulogic;
scanen : std_ulogic;
testen : std_ulogic;
END RECORD;
TYPE tracebuf_in_type IS RECORD
addr : std_logic_vector ( 11 downto 0 );
data : std_logic_vector ( 127 downto 0 );
enable : std_logic;
write : std_logic_vector ( 3 downto 0 );
diag : std_logic_vector ( 3 downto 0 );
END RECORD;
TYPE tracebuf_out_type IS RECORD
data : std_logic_vector ( 127 downto 0 );
END RECORD;
TYPE l3_irq_in_type IS RECORD
irl : std_logic_vector ( 3 downto 0 );
rst : std_ulogic;
run : std_ulogic;
END RECORD;
TYPE l3_irq_out_type IS RECORD
intack : std_ulogic;
irl : std_logic_vector ( 3 downto 0 );
pwd : std_ulogic;
END RECORD;
TYPE l3_debug_in_type IS RECORD
dsuen : std_ulogic;
denable : std_ulogic;
dbreak : std_ulogic;
step : std_ulogic;
halt : std_ulogic;
reset : std_ulogic;
dwrite : std_ulogic;
daddr : std_logic_vector ( 23 downto 2 );
ddata : std_logic_vector ( 31 downto 0 );
btrapa : std_ulogic;
btrape : std_ulogic;
berror : std_ulogic;
bwatch : std_ulogic;
bsoft : std_ulogic;
tenable : std_ulogic;
timer : std_logic_vector ( 30 downto 0 );
END RECORD;
TYPE l3_debug_out_type IS RECORD
data : std_logic_vector ( 31 downto 0 );
crdy : std_ulogic;
dsu : std_ulogic;
dsumode : std_ulogic;
error : std_ulogic;
halt : std_ulogic;
pwd : std_ulogic;
idle : std_ulogic;
ipend : std_ulogic;
icnt : std_ulogic;
END RECORD;
TYPE l3_debug_in_vector IS ARRAY ( natural RANGE <> ) OF l3_debug_in_type;
TYPE l3_debug_out_vector IS ARRAY ( natural RANGE <> ) OF l3_debug_out_type;
TYPE div32_in_type IS RECORD
y : std_logic_vector ( 32 downto 0 );
op1 : std_logic_vector ( 32 downto 0 );
op2 : std_logic_vector ( 32 downto 0 );
flush : std_logic;
signed : std_logic;
start : std_logic;
END RECORD;
TYPE div32_out_type IS RECORD
ready : std_logic;
nready : std_logic;
icc : std_logic_vector ( 3 downto 0 );
result : std_logic_vector ( 31 downto 0 );
END RECORD;
TYPE mul32_in_type IS RECORD
op1 : std_logic_vector ( 32 downto 0 );
op2 : std_logic_vector ( 32 downto 0 );
flush : std_logic;
signed : std_logic;
start : std_logic;
mac : std_logic;
acc : std_logic_vector ( 39 downto 0 );
END RECORD;
TYPE mul32_out_type IS RECORD
ready : std_logic;
nready : std_logic;
icc : std_logic_vector ( 3 downto 0 );
result : std_logic_vector ( 63 downto 0 );
END RECORD;
TYPE fp_rf_in_type IS RECORD
rd1addr : std_logic_vector ( 3 downto 0 );
rd2addr : std_logic_vector ( 3 downto 0 );
wraddr : std_logic_vector ( 3 downto 0 );
wrdata : std_logic_vector ( 31 downto 0 );
ren1 : std_ulogic;
ren2 : std_ulogic;
wren : std_ulogic;
END RECORD;
TYPE fp_rf_out_type IS RECORD
data1 : std_logic_vector ( 31 downto 0 );
data2 : std_logic_vector ( 31 downto 0 );
END RECORD;
TYPE fpc_pipeline_control_type IS RECORD
pc : std_logic_vector ( 31 downto 0 );
inst : std_logic_vector ( 31 downto 0 );
cnt : std_logic_vector ( 1 downto 0 );
trap : std_ulogic;
annul : std_ulogic;
pv : std_ulogic;
END RECORD;
TYPE fpc_debug_in_type IS RECORD
enable : std_ulogic;
write : std_ulogic;
fsr : std_ulogic;
addr : std_logic_vector ( 4 downto 0 );
data : std_logic_vector ( 31 downto 0 );
END RECORD;
TYPE fpc_debug_out_type IS RECORD
data : std_logic_vector ( 31 downto 0 );
END RECORD;
TYPE fpc_in_type IS RECORD
flush : std_ulogic;
exack : std_ulogic;
a_rs1 : std_logic_vector ( 4 downto 0 );
d : fpc_pipeline_control_type;
a : fpc_pipeline_control_type;
e : fpc_pipeline_control_type;
m : fpc_pipeline_control_type;
x : fpc_pipeline_control_type;
lddata : std_logic_vector ( 31 downto 0 );
dbg : fpc_debug_in_type;
END RECORD;
TYPE fpc_out_type IS RECORD
data : std_logic_vector ( 31 downto 0 );
exc : std_logic;
cc : std_logic_vector ( 1 downto 0 );
ccv : std_ulogic;
ldlock : std_logic;
holdn : std_ulogic;
dbg : fpc_debug_out_type;
END RECORD;
TYPE grfpu_in_type IS RECORD
start : std_logic;
nonstd : std_logic;
flop : std_logic_vector ( 8 downto 0 );
op1 : std_logic_vector ( 63 downto 0 );
op2 : std_logic_vector ( 63 downto 0 );
opid : std_logic_vector ( 7 downto 0 );
flush : std_logic;
flushid : std_logic_vector ( 5 downto 0 );
rndmode : std_logic_vector ( 1 downto 0 );
req : std_logic;
END RECORD;
TYPE grfpu_out_type IS RECORD
res : std_logic_vector ( 63 downto 0 );
exc : std_logic_vector ( 5 downto 0 );
allow : std_logic_vector ( 2 downto 0 );
rdy : std_logic;
cc : std_logic_vector ( 1 downto 0 );
idout : std_logic_vector ( 7 downto 0 );
END RECORD;
TYPE grfpu_out_vector_type IS ARRAY ( integer RANGE 0 to 7 ) OF grfpu_out_type;
TYPE grfpu_in_vector_type IS ARRAY ( integer RANGE 0 to 7 ) OF grfpu_in_type;
TYPE dc_in_type IS RECORD
signed : std_ulogic;
enaddr : std_ulogic;
read : std_ulogic;
write : std_ulogic;
lock : std_ulogic;
dsuen : std_ulogic;
size : std_logic_vector ( 1 downto 0 );
asi : std_logic_vector ( 7 downto 0 );
END RECORD;
TYPE pipeline_ctrl_type IS RECORD
pc : pctype;
inst : word;
cnt : std_logic_vector ( 1 downto 0 );
rd : rfatype;
tt : std_logic_vector ( 5 downto 0 );
trap : std_ulogic;
annul : std_ulogic;
wreg : std_ulogic;
wicc : std_ulogic;
wy : std_ulogic;
ld : std_ulogic;
pv : std_ulogic;
rett : std_ulogic;
END RECORD;
TYPE fetch_reg_type IS RECORD
pc : pctype;
branch : std_ulogic;
END RECORD;
TYPE decode_reg_type IS RECORD
pc : pctype;
inst : icdtype;
cwp : cwptype;
set : std_logic_vector ( 1 - 1 downto 0 );
mexc : std_ulogic;
cnt : std_logic_vector ( 1 downto 0 );
pv : std_ulogic;
annul : std_ulogic;
inull : std_ulogic;
step : std_ulogic;
END RECORD;
TYPE regacc_reg_type IS RECORD
ctrl : pipeline_ctrl_type;
rs1 : std_logic_vector ( 4 downto 0 );
rfa1 : rfatype;
rfa2 : rfatype;
rsel1 : std_logic_vector ( 2 downto 0 );
rsel2 : std_logic_vector ( 2 downto 0 );
rfe1 : std_ulogic;
rfe2 : std_ulogic;
cwp : cwptype;
imm : word;
ldcheck1 : std_ulogic;
ldcheck2 : std_ulogic;
ldchkra : std_ulogic;
ldchkex : std_ulogic;
su : std_ulogic;
et : std_ulogic;
wovf : std_ulogic;
wunf : std_ulogic;
ticc : std_ulogic;
jmpl : std_ulogic;
step : std_ulogic;
mulstart : std_ulogic;
divstart : std_ulogic;
END RECORD;
TYPE execute_reg_type IS RECORD
ctrl : pipeline_ctrl_type;
op1 : word;
op2 : word;
aluop : std_logic_vector ( 2 downto 0 );
alusel : std_logic_vector ( 1 downto 0 );
aluadd : std_ulogic;
alucin : std_ulogic;
ldbp1 : std_ulogic;
ldbp2 : std_ulogic;
invop2 : std_ulogic;
shcnt : std_logic_vector ( 4 downto 0 );
sari : std_ulogic;
shleft : std_ulogic;
ymsb : std_ulogic;
rd : std_logic_vector ( 4 downto 0 );
jmpl : std_ulogic;
su : std_ulogic;
et : std_ulogic;
cwp : cwptype;
icc : std_logic_vector ( 3 downto 0 );
mulstep : std_ulogic;
mul : std_ulogic;
mac : std_ulogic;
END RECORD;
TYPE memory_reg_type IS RECORD
ctrl : pipeline_ctrl_type;
result : word;
y : word;
icc : std_logic_vector ( 3 downto 0 );
nalign : std_ulogic;
dci : dc_in_type;
werr : std_ulogic;
wcwp : std_ulogic;
irqen : std_ulogic;
irqen2 : std_ulogic;
mac : std_ulogic;
divz : std_ulogic;
su : std_ulogic;
mul : std_ulogic;
END RECORD;
TYPE exception_state IS ( run , trap , dsu1 , dsu2 );
TYPE exception_reg_type IS RECORD
ctrl : pipeline_ctrl_type;
result : word;
y : word;
icc : std_logic_vector ( 3 downto 0 );
annul_all : std_ulogic;
data : dcdtype;
set : std_logic_vector ( 1 - 1 downto 0 );
mexc : std_ulogic;
impwp : std_ulogic;
dci : dc_in_type;
laddr : std_logic_vector ( 1 downto 0 );
rstate : exception_state;
npc : std_logic_vector ( 2 downto 0 );
intack : std_ulogic;
ipend : std_ulogic;
mac : std_ulogic;
pwd : std_ulogic;
debug : std_ulogic;
error : std_ulogic;
nerror : std_ulogic;
et : std_ulogic;
END RECORD;
TYPE dsu_registers IS RECORD
tt : std_logic_vector ( 7 downto 0 );
err : std_ulogic;
tbufcnt : std_logic_vector ( 10 + 1 - 4 - 1 downto 0 );
asi : std_logic_vector ( 7 downto 0 );
crdy : std_logic_vector ( 2 downto 1 );
END RECORD;
TYPE irestart_register IS RECORD
addr : pctype;
pwd : std_ulogic;
END RECORD;
TYPE pwd_register_type IS RECORD
pwd : std_ulogic;
error : std_ulogic;
END RECORD;
TYPE special_register_type IS RECORD
cwp : cwptype;
icc : std_logic_vector ( 3 downto 0 );
tt : std_logic_vector ( 7 downto 0 );
tba : std_logic_vector ( 19 downto 0 );
wim : std_logic_vector ( 8 - 1 downto 0 );
pil : std_logic_vector ( 3 downto 0 );
ec : std_ulogic;
ef : std_ulogic;
ps : std_ulogic;
s : std_ulogic;
et : std_ulogic;
y : word;
asr18 : word;
svt : std_ulogic;
dwt : std_ulogic;
END RECORD;
TYPE write_reg_type IS RECORD
s : special_register_type;
result : word;
wa : rfatype;
wreg : std_ulogic;
except : std_ulogic;
END RECORD;
TYPE registers IS RECORD
f : fetch_reg_type;
d : decode_reg_type;
a : regacc_reg_type;
e : execute_reg_type;
m : memory_reg_type;
x : exception_reg_type;
w : write_reg_type;
END RECORD;
TYPE exception_type IS RECORD
pri : std_ulogic;
ill : std_ulogic;
fpdis : std_ulogic;
cpdis : std_ulogic;
wovf : std_ulogic;
wunf : std_ulogic;
ticc : std_ulogic;
END RECORD;
TYPE watchpoint_register IS RECORD
addr : std_logic_vector ( 31 downto 2 );
mask : std_logic_vector ( 31 downto 2 );
exec : std_ulogic;
imp : std_ulogic;
load : std_ulogic;
store : std_ulogic;
END RECORD;
TYPE watchpoint_registers IS ARRAY ( 0 to 3 ) OF watchpoint_register;
CONSTANT wpr_none : watchpoint_register := ( "000000000000000000000000000000" , "000000000000000000000000000000" , '0' , '0' , '0' , '0' );
FUNCTION dbgexc (
r : registers;
dbgi : l3_debug_in_type;
trap : std_ulogic;
tt : std_logic_vector ( 7 downto 0 )
) RETURN std_ulogic IS
VARIABLE dmode : std_ulogic;
BEGIN
dmode := '0';
IF ( not r.x.ctrl.annul and trap ) = '1' THEN
IF ( ( ( tt = "00" & TT_WATCH ) and ( dbgi.bwatch = '1' ) ) or ( ( dbgi.bsoft = '1' ) and ( tt = "10000001" ) ) or ( dbgi.btrapa = '1' ) or ( ( dbgi.btrape = '1' ) and not ( ( tt ( 5 downto 0 ) = TT_PRIV ) or ( tt ( 5 downto 0 ) = TT_FPDIS ) or ( tt ( 5 downto 0 ) = TT_WINOF ) or ( tt ( 5 downto 0 ) = TT_WINUF ) or ( tt ( 5 downto 4 ) = "01" ) or ( tt ( 7 ) = '1' ) ) ) or ( ( ( not r.w.s.et ) and dbgi.berror ) = '1' ) ) THEN
dmode := '1';
END IF;
END IF;
RETURN ( dmode );
END;
FUNCTION dbgerr (
r : registers;
dbgi : l3_debug_in_type;
tt : std_logic_vector ( 7 downto 0 )
) RETURN std_ulogic IS
VARIABLE err : std_ulogic;
BEGIN
err := not r.w.s.et;
IF ( ( ( dbgi.dbreak = '1' ) and ( tt = ( "00" & TT_WATCH ) ) ) or ( ( dbgi.bsoft = '1' ) and ( tt = ( "10000001" ) ) ) ) THEN
err := '0';
END IF;
RETURN ( err );
END;
PROCEDURE diagwr (
r : in registers;
dsur : in dsu_registers;
ir : in irestart_register;
dbg : in l3_debug_in_type;
wpr : in watchpoint_registers;
s : out special_register_type;
vwpr : out watchpoint_registers;
asi : out std_logic_vector ( 7 downto 0 );
pc : out pctype;
npc : out pctype;
tbufcnt : out std_logic_vector ( 10 + 1 - 4 - 1 downto 0 );
wr : out std_ulogic;
addr : out std_logic_vector ( 9 downto 0 );
data : out word;
fpcwr : out std_ulogic
) IS
VARIABLE i : integer RANGE 0 to 3;
BEGIN
s := r.w.s;
pc := r.f.pc;
npc := ir.addr;
wr := '0';
vwpr := wpr;
asi := dsur.asi;
addr := ( OTHERS => '0' );
data := dbg.ddata;
tbufcnt := dsur.tbufcnt;
fpcwr := '0';
IF ( dbg.dsuen and dbg.denable and dbg.dwrite ) = '1' THEN
CASE dbg.daddr ( 23 downto 20 ) IS
WHEN "0001" =>
IF dbg.daddr ( 16 ) = '1' THEN
tbufcnt := dbg.ddata ( 10 + 1 - 4 - 1 downto 0 );
END IF;
WHEN "0011" =>
IF dbg.daddr ( 12 ) = '0' THEN
wr := '1';
addr := ( OTHERS => '0' );
addr ( 4 + 4 - 1 downto 0 ) := dbg.daddr ( 4 + 4 + 1 downto 2 );
ELSE
fpcwr := '1';
END IF;
WHEN "0100" =>
CASE dbg.daddr ( 7 downto 6 ) IS
WHEN "00" =>
CASE dbg.daddr ( 5 downto 2 ) IS
WHEN "0000" =>
s.y := dbg.ddata;
WHEN "0001" =>
s.cwp := dbg.ddata ( 3 - 1 downto 0 );
s.icc := dbg.ddata ( 23 downto 20 );
s.ec := dbg.ddata ( 13 );
s.pil := dbg.ddata ( 11 downto 8 );
s.s := dbg.ddata ( 7 );
s.ps := dbg.ddata ( 6 );
s.et := dbg.ddata ( 5 );
WHEN "0010" =>
s.wim := dbg.ddata ( 8 - 1 downto 0 );
WHEN "0011" =>
s.tba := dbg.ddata ( 31 downto 12 );
s.tt := dbg.ddata ( 11 downto 4 );
WHEN "0100" =>
pc := dbg.ddata ( 31 downto 2 );
WHEN "0101" =>
npc := dbg.ddata ( 31 downto 2 );
WHEN "0110" =>
fpcwr := '1';
WHEN "0111" =>
NULL;
WHEN "1001" =>
asi := dbg.ddata ( 7 downto 0 );
WHEN OTHERS =>
NULL;
END CASE;
WHEN "01" =>
CASE dbg.daddr ( 5 downto 2 ) IS
WHEN "0001" =>
s.dwt := dbg.ddata ( 14 );
s.svt := dbg.ddata ( 13 );
WHEN "0010" =>
NULL;
WHEN "1000" =>
vwpr ( 0 ).addr := dbg.ddata ( 31 downto 2 );
vwpr ( 0 ).imp := dbg.ddata ( 1 );
vwpr ( 0 ).exec := dbg.ddata ( 0 );
WHEN "1001" =>
vwpr ( 0 ).mask := dbg.ddata ( 31 downto 2 );
vwpr ( 0 ).load := dbg.ddata ( 1 );
vwpr ( 0 ).store := dbg.ddata ( 0 );
WHEN "1010" =>
vwpr ( 1 ).addr := dbg.ddata ( 31 downto 2 );
vwpr ( 1 ).imp := dbg.ddata ( 1 );
vwpr ( 1 ).exec := dbg.ddata ( 0 );
WHEN "1011" =>
vwpr ( 1 ).mask := dbg.ddata ( 31 downto 2 );
vwpr ( 1 ).load := dbg.ddata ( 1 );
vwpr ( 1 ).store := dbg.ddata ( 0 );
WHEN "1100" =>
vwpr ( 2 ).addr := dbg.ddata ( 31 downto 2 );
vwpr ( 2 ).imp := dbg.ddata ( 1 );
vwpr ( 2 ).exec := dbg.ddata ( 0 );
WHEN "1101" =>
vwpr ( 2 ).mask := dbg.ddata ( 31 downto 2 );
vwpr ( 2 ).load := dbg.ddata ( 1 );
vwpr ( 2 ).store := dbg.ddata ( 0 );
WHEN "1110" =>
vwpr ( 3 ).addr := dbg.ddata ( 31 downto 2 );
vwpr ( 3 ).imp := dbg.ddata ( 1 );
vwpr ( 3 ).exec := dbg.ddata ( 0 );
WHEN "1111" =>
vwpr ( 3 ).mask := dbg.ddata ( 31 downto 2 );
vwpr ( 3 ).load := dbg.ddata ( 1 );
vwpr ( 3 ).store := dbg.ddata ( 0 );
WHEN OTHERS =>
NULL;
END CASE;
WHEN OTHERS =>
NULL;
END CASE;
WHEN OTHERS =>
NULL;
END CASE;
END IF;
END;
FUNCTION asr17_gen (
r : in registers
) RETURN word IS
VARIABLE asr17 : word;
VARIABLE fpu2 : integer RANGE 0 to 3;
BEGIN
asr17 := "00000000000000000000000000000000";
asr17 ( 31 downto 28 ) := conv_std_logic_vector ( 0 , 4 );
asr17 ( 14 ) := r.w.s.dwt;
asr17 ( 13 ) := r.w.s.svt;
fpu2 := 0;
asr17 ( 11 downto 10 ) := conv_std_logic_vector ( fpu2 , 2 );
asr17 ( 8 ) := '1';
asr17 ( 7 downto 5 ) := conv_std_logic_vector ( 2 , 3 );
asr17 ( 4 downto 0 ) := conv_std_logic_vector ( 8 - 1 , 5 );
RETURN ( asr17 );
END;
PROCEDURE diagread (
dbgi : in l3_debug_in_type;
r : in registers;
dsur : in dsu_registers;
ir : in irestart_register;
wpr : in watchpoint_registers;
rfdata : in std_logic_vector ( 31 downto 0 );
dco : in dcache_out_type;
tbufo : in tracebuf_out_type;
data : out word
) IS
VARIABLE cwp : std_logic_vector ( 4 downto 0 );
VARIABLE rd : std_logic_vector ( 4 downto 0 );
VARIABLE i : integer RANGE 0 to 3;
BEGIN
data := ( OTHERS => '0' );
cwp := ( OTHERS => '0' );
cwp ( 3 - 1 downto 0 ) := r.w.s.cwp;
CASE dbgi.daddr ( 22 downto 20 ) IS
WHEN "001" =>
IF dbgi.daddr ( 16 ) = '1' THEN
data ( 10 + 1 - 4 - 1 downto 0 ) := dsur.tbufcnt;
ELSE
CASE dbgi.daddr ( 3 downto 2 ) IS
WHEN "00" =>
data := tbufo.data ( 127 downto 96 );
WHEN "01" =>
data := tbufo.data ( 95 downto 64 );
WHEN "10" =>
data := tbufo.data ( 63 downto 32 );
WHEN OTHERS =>
data := tbufo.data ( 31 downto 0 );
END CASE;
END IF;
WHEN "011" =>
IF dbgi.daddr ( 12 ) = '0' THEN
data := rfdata ( 31 downto 0 );
ELSE
data := fpo.dbg.data;
END IF;
WHEN "100" =>
CASE dbgi.daddr ( 7 downto 6 ) IS
WHEN "00" =>
CASE dbgi.daddr ( 5 downto 2 ) IS
WHEN "0000" =>
data := r.w.s.y;
WHEN "0001" =>
data := conv_std_logic_vector ( 15 , 4 ) & conv_std_logic_vector ( 3 , 4 ) & r.w.s.icc & "000000" & r.w.s.ec & r.w.s.ef & r.w.s.pil & r.w.s.s & r.w.s.ps & r.w.s.et & cwp;
WHEN "0010" =>
data ( 8 - 1 downto 0 ) := r.w.s.wim;
WHEN "0011" =>
data := r.w.s.tba & r.w.s.tt & "0000";
WHEN "0100" =>
data ( 31 downto 2 ) := r.f.pc;
WHEN "0101" =>
data ( 31 downto 2 ) := ir.addr;
WHEN "0110" =>
data := fpo.dbg.data;
WHEN "0111" =>
NULL;
WHEN "1000" =>
data ( 12 downto 4 ) := dsur.err & dsur.tt;
WHEN "1001" =>
data ( 7 downto 0 ) := dsur.asi;
WHEN OTHERS =>
NULL;
END CASE;
WHEN "01" =>
IF dbgi.daddr ( 5 ) = '0' THEN
IF dbgi.daddr ( 4 downto 2 ) = "001" THEN
data := asr17_gen ( r );
END IF;
ELSE
i := conv_integer ( dbgi.daddr ( 4 downto 3 ) );
IF dbgi.daddr ( 2 ) = '0' THEN
data ( 31 downto 2 ) := wpr ( i ).addr;
data ( 1 ) := wpr ( i ).imp;
data ( 0 ) := wpr ( i ).exec;
ELSE
data ( 31 downto 2 ) := wpr ( i ).mask;
data ( 1 ) := wpr ( i ).load;
data ( 0 ) := wpr ( i ).store;
END IF;
END IF;
WHEN OTHERS =>
NULL;
END CASE;
WHEN "111" =>
data := r.x.data ( conv_integer ( r.x.set ) );
WHEN OTHERS =>
NULL;
END CASE;
END;
PROCEDURE itrace (
r : in registers;
dsur : in dsu_registers;
vdsu : in dsu_registers;
res : in word;
exc : in std_ulogic;
dbgi : in l3_debug_in_type;
error : in std_ulogic;
trap : in std_ulogic;
tbufcnt : out std_logic_vector ( 10 + 1 - 4 - 1 downto 0 );
di : out tracebuf_in_type
) IS
VARIABLE meminst : std_ulogic;
BEGIN
di.addr := ( OTHERS => '0' );
di.data := ( OTHERS => '0' );
di.enable := '0';
di.write := ( OTHERS => '0' );
tbufcnt := vdsu.tbufcnt;
meminst := r.x.ctrl.inst ( 31 ) and r.x.ctrl.inst ( 30 );
di.addr ( 10 + 1 - 4 - 1 downto 0 ) := dsur.tbufcnt;
di.data ( 127 ) := '0';
di.data ( 126 ) := not r.x.ctrl.pv;
di.data ( 125 downto 96 ) := dbgi.timer ( 29 downto 0 );
di.data ( 95 downto 64 ) := res;
di.data ( 63 downto 34 ) := r.x.ctrl.pc ( 31 downto 2 );
di.data ( 33 ) := trap;
di.data ( 32 ) := error;
di.data ( 31 downto 0 ) := r.x.ctrl.inst;
IF ( dbgi.tenable = '0' ) or ( r.x.rstate = dsu2 ) THEN
IF ( ( dbgi.dsuen and dbgi.denable ) = '1' ) and ( dbgi.daddr ( 23 downto 20 ) & dbgi.daddr ( 16 ) = "00010" ) THEN
di.enable := '1';
di.addr ( 10 + 1 - 4 - 1 downto 0 ) := dbgi.daddr ( 10 + 1 - 4 - 1 + 4 downto 4 );
IF dbgi.dwrite = '1' THEN
CASE dbgi.daddr ( 3 downto 2 ) IS
WHEN "00" =>
di.write ( 3 ) := '1';
WHEN "01" =>
di.write ( 2 ) := '1';
WHEN "10" =>
di.write ( 1 ) := '1';
WHEN OTHERS =>
di.write ( 0 ) := '1';
END CASE;
di.data := dbgi.ddata & dbgi.ddata & dbgi.ddata & dbgi.ddata;
END IF;
END IF;
ELSIF ( not r.x.ctrl.annul and ( r.x.ctrl.pv or meminst ) and not r.x.debug ) = '1' THEN
di.enable := '1';
di.write := ( OTHERS => '1' );
tbufcnt := dsur.tbufcnt + 1;
END IF;
di.diag := dco.testen & "000";
IF dco.scanen = '1' THEN
di.enable := '0';
END IF;
END;
PROCEDURE dbg_cache (
holdn : in std_ulogic;
dbgi : in l3_debug_in_type;
r : in registers;
dsur : in dsu_registers;
mresult : in word;
dci : in dc_in_type;
mresult2 : out word;
dci2 : out dc_in_type
) IS
BEGIN
mresult2 := mresult;
dci2 := dci;
dci2.dsuen := '0';
IF r.x.rstate = dsu2 THEN
dci2.asi := dsur.asi;
IF ( dbgi.daddr ( 22 downto 20 ) = "111" ) and ( dbgi.dsuen = '1' ) THEN
dci2.dsuen := ( dbgi.denable or r.m.dci.dsuen ) and not dsur.crdy ( 2 );
dci2.enaddr := dbgi.denable;
dci2.size := "10";
dci2.read := '1';
dci2.write := '0';
IF ( dbgi.denable and not r.m.dci.enaddr ) = '1' THEN
mresult2 := ( OTHERS => '0' );
mresult2 ( 19 downto 2 ) := dbgi.daddr ( 19 downto 2 );
ELSE
mresult2 := dbgi.ddata;
END IF;
IF dbgi.dwrite = '1' THEN
dci2.read := '0';
dci2.write := '1';
END IF;
END IF;
END IF;
END;
PROCEDURE fpexack (
r : in registers;
fpexc : out std_ulogic
) IS
BEGIN
fpexc := '0';
END;
PROCEDURE diagrdy (
denable : in std_ulogic;
dsur : in dsu_registers;
dci : in dc_in_type;
mds : in std_ulogic;
ico : in icache_out_type;
crdy : out std_logic_vector ( 2 downto 1 )
) IS
BEGIN
crdy := dsur.crdy ( 1 ) & '0';
IF dci.dsuen = '1' THEN
CASE dsur.asi ( 4 downto 0 ) IS
WHEN ASI_ITAG | ASI_IDATA | ASI_UINST | ASI_SINST =>
crdy ( 2 ) := ico.diagrdy and not dsur.crdy ( 2 );
WHEN ASI_DTAG | ASI_MMUSNOOP_DTAG | ASI_DDATA | ASI_UDATA | ASI_SDATA =>
crdy ( 1 ) := not denable and dci.enaddr and not dsur.crdy ( 1 );
WHEN OTHERS =>
crdy ( 2 ) := dci.enaddr and denable;
END CASE;
END IF;
END;
SIGNAL r : registers;
SIGNAL rin : registers;
SIGNAL wpr : watchpoint_registers;
SIGNAL wprin : watchpoint_registers;
SIGNAL dsur : dsu_registers;
SIGNAL dsuin : dsu_registers;
SIGNAL ir : irestart_register;
SIGNAL irin : irestart_register;
SIGNAL rp : pwd_register_type;
SIGNAL rpin : pwd_register_type;
CONSTANT EXE_AND : std_logic_vector ( 2 downto 0 ) := "000";
CONSTANT EXE_XOR : std_logic_vector ( 2 downto 0 ) := "001";
CONSTANT EXE_OR : std_logic_vector ( 2 downto 0 ) := "010";
CONSTANT EXE_XNOR : std_logic_vector ( 2 downto 0 ) := "011";
CONSTANT EXE_ANDN : std_logic_vector ( 2 downto 0 ) := "100";
CONSTANT EXE_ORN : std_logic_vector ( 2 downto 0 ) := "101";
CONSTANT EXE_DIV : std_logic_vector ( 2 downto 0 ) := "110";
CONSTANT EXE_PASS1 : std_logic_vector ( 2 downto 0 ) := "000";
CONSTANT EXE_PASS2 : std_logic_vector ( 2 downto 0 ) := "001";
CONSTANT EXE_STB : std_logic_vector ( 2 downto 0 ) := "010";
CONSTANT EXE_STH : std_logic_vector ( 2 downto 0 ) := "011";
CONSTANT EXE_ONES : std_logic_vector ( 2 downto 0 ) := "100";
CONSTANT EXE_RDY : std_logic_vector ( 2 downto 0 ) := "101";
CONSTANT EXE_SPR : std_logic_vector ( 2 downto 0 ) := "110";
CONSTANT EXE_LINK : std_logic_vector ( 2 downto 0 ) := "111";
CONSTANT EXE_SLL : std_logic_vector ( 2 downto 0 ) := "001";
CONSTANT EXE_SRL : std_logic_vector ( 2 downto 0 ) := "010";
CONSTANT EXE_SRA : std_logic_vector ( 2 downto 0 ) := "100";
CONSTANT EXE_NOP : std_logic_vector ( 2 downto 0 ) := "000";
CONSTANT EXE_RES_ADD : std_logic_vector ( 1 downto 0 ) := "00";
CONSTANT EXE_RES_SHIFT : std_logic_vector ( 1 downto 0 ) := "01";
CONSTANT EXE_RES_LOGIC : std_logic_vector ( 1 downto 0 ) := "10";
CONSTANT EXE_RES_MISC : std_logic_vector ( 1 downto 0 ) := "11";
CONSTANT SZBYTE : std_logic_vector ( 1 downto 0 ) := "00";
CONSTANT SZHALF : std_logic_vector ( 1 downto 0 ) := "01";
CONSTANT SZWORD : std_logic_vector ( 1 downto 0 ) := "10";
CONSTANT SZDBL : std_logic_vector ( 1 downto 0 ) := "11";
PROCEDURE regaddr (
cwp : std_logic_vector;
reg : std_logic_vector ( 4 downto 0 );
rao : out rfatype
) IS
VARIABLE ra : rfatype;
CONSTANT globals : std_logic_vector ( 4 + 4 - 5 downto 0 ) := conv_std_logic_vector ( 8 , 4 + 4 - 4 );
BEGIN
ra := ( OTHERS => '0' );
ra ( 4 downto 0 ) := reg;
IF reg ( 4 downto 3 ) = "00" THEN
ra ( 4 + 4 - 1 downto 4 ) := CONV_STD_LOGIC_VECTOR ( 8 , 4 + 4 - 4 );
ELSE
ra ( 3 + 3 downto 4 ) := cwp + ra ( 4 );
END IF;
rao := ra;
END;
FUNCTION branch_address (
inst : word;
pc : pctype
) RETURN std_logic_vector IS
VARIABLE baddr : pctype;
VARIABLE caddr : pctype;
VARIABLE tmp : pctype;
BEGIN
caddr := ( OTHERS => '0' );
caddr ( 31 downto 2 ) := inst ( 29 downto 0 );
caddr ( 31 downto 2 ) := caddr ( 31 downto 2 ) + pc ( 31 downto 2 );
baddr := ( OTHERS => '0' );
baddr ( 31 downto 24 ) := ( OTHERS => inst ( 21 ) );
baddr ( 23 downto 2 ) := inst ( 21 downto 0 );
baddr ( 31 downto 2 ) := baddr ( 31 downto 2 ) + pc ( 31 downto 2 );
IF inst ( 30 ) = '1' THEN
tmp := caddr;
ELSE
tmp := baddr;
END IF;
RETURN ( tmp );
END;
FUNCTION branch_true (
icc : std_logic_vector ( 3 downto 0 );
inst : word
) RETURN std_ulogic IS
VARIABLE n : std_ulogic;
VARIABLE z : std_ulogic;
VARIABLE v : std_ulogic;
VARIABLE c : std_ulogic;
VARIABLE branch : std_ulogic;
BEGIN
n := icc ( 3 );
z := icc ( 2 );
v := icc ( 1 );
c := icc ( 0 );
CASE inst ( 27 downto 25 ) IS
WHEN "000" =>
branch := inst ( 28 ) xor '0';
WHEN "001" =>
branch := inst ( 28 ) xor z;
WHEN "010" =>
branch := inst ( 28 ) xor ( z or ( n xor v ) );
WHEN "011" =>
branch := inst ( 28 ) xor ( n xor v );
WHEN "100" =>
branch := inst ( 28 ) xor ( c or z );
WHEN "101" =>
branch := inst ( 28 ) xor c;
WHEN "110" =>
branch := inst ( 28 ) xor n;
WHEN OTHERS =>
branch := inst ( 28 ) xor v;
END CASE;
RETURN ( branch );
END;
PROCEDURE su_et_select (
r : in registers;
xc_ps : in std_ulogic;
xc_s : in std_ulogic;
xc_et : in std_ulogic;
su : out std_ulogic;
et : out std_ulogic
) IS
BEGIN
IF ( ( r.a.ctrl.rett or r.e.ctrl.rett or r.m.ctrl.rett or r.x.ctrl.rett ) = '1' ) and ( r.x.annul_all = '0' ) THEN
su := xc_ps;
et := '1';
ELSE
su := xc_s;
et := xc_et;
END IF;
END;
FUNCTION wphit (
r : registers;
wpr : watchpoint_registers;
debug : l3_debug_in_type
) RETURN std_ulogic IS
VARIABLE exc : std_ulogic;
BEGIN
exc := '0';
IF ( ( wpr ( 0 ).exec and r.a.ctrl.pv and not r.a.ctrl.annul ) = '1' ) THEN
IF ( ( ( wpr ( 0 ).addr xor r.a.ctrl.pc ( 31 downto 2 ) ) and wpr ( 0 ).mask ) = "000000000000000000000000000000" ) THEN
exc := '1';
END IF;
END IF;
IF ( ( wpr ( 1 ).exec and r.a.ctrl.pv and not r.a.ctrl.annul ) = '1' ) THEN
IF ( ( ( wpr ( 1 ).addr xor r.a.ctrl.pc ( 31 downto 2 ) ) and wpr ( 1 ).mask ) = "000000000000000000000000000000" ) THEN
exc := '1';
END IF;
END IF;
IF ( debug.dsuen and not r.a.ctrl.annul ) = '1' THEN
exc := exc or ( r.a.ctrl.pv and ( ( debug.dbreak and debug.bwatch ) or r.a.step ) );
END IF;
RETURN ( exc );
END;
FUNCTION shift3 (
r : registers;
aluin1 : word;
aluin2 : word
) RETURN word IS
VARIABLE shiftin : unsigned ( 63 downto 0 );
VARIABLE shiftout : unsigned ( 63 downto 0 );
VARIABLE cnt : natural RANGE 0 to 31;
BEGIN
cnt := conv_integer ( r.e.shcnt );
IF r.e.shleft = '1' THEN
shiftin ( 30 downto 0 ) := ( OTHERS => '0' );
shiftin ( 63 downto 31 ) := '0' & unsigned ( aluin1 );
ELSE
shiftin ( 63 downto 32 ) := ( OTHERS => r.e.sari );
shiftin ( 31 downto 0 ) := unsigned ( aluin1 );
END IF;
shiftout := SHIFT_RIGHT ( shiftin , cnt );
RETURN ( std_logic_vector ( shiftout ( 31 downto 0 ) ) );
END;
FUNCTION shift2 (
r : registers;
aluin1 : word;
aluin2 : word
) RETURN word IS
VARIABLE ushiftin : unsigned ( 31 downto 0 );
VARIABLE sshiftin : signed ( 32 downto 0 );
VARIABLE cnt : natural RANGE 0 to 31;
BEGIN
cnt := conv_integer ( r.e.shcnt );
ushiftin := unsigned ( aluin1 );
sshiftin := signed ( '0' & aluin1 );
IF r.e.shleft = '1' THEN
RETURN ( std_logic_vector ( SHIFT_LEFT ( ushiftin , cnt ) ) );
ELSE
IF r.e.sari = '1' THEN
sshiftin ( 32 ) := aluin1 ( 31 );
END IF;
sshiftin := SHIFT_RIGHT ( sshiftin , cnt );
RETURN ( std_logic_vector ( sshiftin ( 31 downto 0 ) ) );
END IF;
END;
FUNCTION shift (
r : registers;
aluin1 : word;
aluin2 : word;
shiftcnt : std_logic_vector ( 4 downto 0 );
sari : std_ulogic
) RETURN word IS
VARIABLE shiftin : std_logic_vector ( 63 downto 0 );
BEGIN
shiftin := "00000000000000000000000000000000" & aluin1;
IF r.e.shleft = '1' THEN
shiftin ( 31 downto 0 ) := "00000000000000000000000000000000";
shiftin ( 63 downto 31 ) := '0' & aluin1;
ELSE
shiftin ( 63 downto 32 ) := ( OTHERS => sari );
END IF;
IF shiftcnt ( 4 ) = '1' THEN
shiftin ( 47 downto 0 ) := shiftin ( 63 downto 16 );
END IF;
IF shiftcnt ( 3 ) = '1' THEN
shiftin ( 39 downto 0 ) := shiftin ( 47 downto 8 );
END IF;
IF shiftcnt ( 2 ) = '1' THEN
shiftin ( 35 downto 0 ) := shiftin ( 39 downto 4 );
END IF;
IF shiftcnt ( 1 ) = '1' THEN
shiftin ( 33 downto 0 ) := shiftin ( 35 downto 2 );
END IF;
IF shiftcnt ( 0 ) = '1' THEN
shiftin ( 31 downto 0 ) := shiftin ( 32 downto 1 );
END IF;
RETURN ( shiftin ( 31 downto 0 ) );
END;
PROCEDURE exception_detect (
r : registers;
wpr : watchpoint_registers;
dbgi : l3_debug_in_type;
trapin : in std_ulogic;
ttin : in std_logic_vector ( 5 downto 0 );
trap : out std_ulogic;
tt : out std_logic_vector ( 5 downto 0 )
) IS
VARIABLE illegal_inst : std_ulogic;
VARIABLE privileged_inst : std_ulogic;
VARIABLE cp_disabled : std_ulogic;
VARIABLE fp_disabled : std_ulogic;
VARIABLE fpop : std_ulogic;
VARIABLE op : std_logic_vector ( 1 downto 0 );
VARIABLE op2 : std_logic_vector ( 2 downto 0 );
VARIABLE op3 : std_logic_vector ( 5 downto 0 );
VARIABLE rd : std_logic_vector ( 4 downto 0 );
VARIABLE inst : word;
VARIABLE wph : std_ulogic;
BEGIN
inst := r.a.ctrl.inst;
trap := trapin;
tt := ttin;
IF r.a.ctrl.annul = '0' THEN
op := inst ( 31 downto 30 );
op2 := inst ( 24 downto 22 );
op3 := inst ( 24 downto 19 );
rd := inst ( 29 downto 25 );
illegal_inst := '0';
privileged_inst := '0';
cp_disabled := '0';
fp_disabled := '0';
fpop := '0';
CASE op IS
WHEN CALL =>
NULL;
WHEN FMT2 =>
CASE op2 IS
WHEN SETHI | BICC =>
NULL;
WHEN FBFCC =>
fp_disabled := '1';
WHEN CBCCC =>
cp_disabled := '1';
WHEN OTHERS =>
illegal_inst := '1';
END CASE;
WHEN FMT3 =>
CASE op3 IS
WHEN IAND | ANDCC | ANDN | ANDNCC | IOR | ORCC | ORN | ORNCC | IXOR | XORCC | IXNOR | XNORCC | ISLL | ISRL | ISRA | MULSCC | IADD | ADDX | ADDCC | ADDXCC | ISUB | SUBX | SUBCC | SUBXCC | FLUSH | JMPL | TICC | SAVE | RESTORE | RDY =>
NULL;
WHEN TADDCC | TADDCCTV | TSUBCC | TSUBCCTV =>
NULL;
WHEN UMAC | SMAC =>
illegal_inst := '1';
WHEN UMUL | SMUL | UMULCC | SMULCC =>
NULL;
WHEN UDIV | SDIV | UDIVCC | SDIVCC =>
NULL;
WHEN RETT =>
illegal_inst := r.a.et;
privileged_inst := not r.a.su;
WHEN RDPSR | RDTBR | RDWIM =>
privileged_inst := not r.a.su;
WHEN WRY =>
NULL;
WHEN WRPSR =>
privileged_inst := not r.a.su;
WHEN WRWIM | WRTBR =>
privileged_inst := not r.a.su;
WHEN FPOP1 | FPOP2 =>
fp_disabled := '1';
fpop := '0';
WHEN CPOP1 | CPOP2 =>
cp_disabled := '1';
WHEN OTHERS =>
illegal_inst := '1';
END CASE;
WHEN OTHERS =>
CASE op3 IS
WHEN LDD | ISTD =>
illegal_inst := rd ( 0 );
WHEN LD | LDUB | LDSTUB | LDUH | LDSB | LDSH | ST | STB | STH | SWAP =>
NULL;
WHEN LDDA | STDA =>
illegal_inst := inst ( 13 ) or rd ( 0 );
privileged_inst := not r.a.su;
WHEN LDA | LDUBA | LDSTUBA | LDUHA | LDSBA | LDSHA | STA | STBA | STHA | SWAPA =>
illegal_inst := inst ( 13 );
privileged_inst := not r.a.su;
WHEN LDDF | STDF | LDF | LDFSR | STF | STFSR =>
fp_disabled := '1';
WHEN STDFQ =>
privileged_inst := not r.a.su;
fp_disabled := '1';
WHEN STDCQ =>
privileged_inst := not r.a.su;
cp_disabled := '1';
WHEN LDC | LDCSR | LDDC | STC | STCSR | STDC =>
cp_disabled := '1';
WHEN OTHERS =>
illegal_inst := '1';
END CASE;
END CASE;
wph := wphit ( r , wpr , dbgi );
trap := '1';
IF r.a.ctrl.trap = '1' THEN
tt := TT_IAEX;
ELSIF privileged_inst = '1' THEN
tt := TT_PRIV;
ELSIF illegal_inst = '1' THEN
tt := TT_IINST;
ELSIF fp_disabled = '1' THEN
tt := TT_FPDIS;
ELSIF cp_disabled = '1' THEN
tt := TT_CPDIS;
ELSIF wph = '1' THEN
tt := TT_WATCH;
ELSIF r.a.wovf = '1' THEN
tt := TT_WINOF;
ELSIF r.a.wunf = '1' THEN
tt := TT_WINUF;
ELSIF r.a.ticc = '1' THEN
tt := TT_TICC;
ELSE
trap := '0';
tt := ( OTHERS => '0' );
END IF;
END IF;
END;
PROCEDURE wicc_y_gen (
inst : word;
wicc : out std_ulogic;
wy : out std_ulogic
) IS
BEGIN
wicc := '0';
wy := '0';
IF inst ( 31 downto 30 ) = FMT3 THEN
CASE inst ( 24 downto 19 ) IS
WHEN SUBCC | TSUBCC | TSUBCCTV | ADDCC | ANDCC | ORCC | XORCC | ANDNCC | ORNCC | XNORCC | TADDCC | TADDCCTV | ADDXCC | SUBXCC | WRPSR =>
wicc := '1';
WHEN WRY =>
IF r.d.inst ( conv_integer ( r.d.set ) ) ( 29 downto 25 ) = "00000" THEN
wy := '1';
END IF;
WHEN MULSCC =>
wicc := '1';
wy := '1';
WHEN UMAC | SMAC =>
NULL;
WHEN UMULCC | SMULCC =>
IF ( mulo.nready = '1' ) and ( r.d.cnt /= "00" ) THEN
wicc := '1';
wy := '1';
END IF;
WHEN UMUL | SMUL =>
IF ( mulo.nready = '1' ) and ( r.d.cnt /= "00" ) THEN
wy := '1';
END IF;
WHEN UDIVCC | SDIVCC =>
IF ( divo.nready = '1' ) and ( r.d.cnt /= "00" ) THEN
wicc := '1';
END IF;
WHEN OTHERS =>
NULL;
END CASE;
END IF;
END;
PROCEDURE cwp_gen (
r : registers;
v : registers;
annul : std_ulogic;
wcwp : std_ulogic;
ncwp : cwptype;
cwp : out cwptype
) IS
BEGIN
IF ( r.x.rstate = trap ) or ( r.x.rstate = dsu2 ) or ( rstn = '0' ) THEN
cwp := v.w.s.cwp;
ELSIF ( wcwp = '1' ) and ( annul = '0' ) THEN
cwp := ncwp;
ELSIF r.m.wcwp = '1' THEN
cwp := r.m.result ( 3 - 1 downto 0 );
ELSE
cwp := r.d.cwp;
END IF;
END;
PROCEDURE cwp_ex (
r : in registers;
wcwp : out std_ulogic
) IS
BEGIN
IF ( r.e.ctrl.inst ( 31 downto 30 ) = FMT3 ) and ( r.e.ctrl.inst ( 24 downto 19 ) = WRPSR ) THEN
wcwp := not r.e.ctrl.annul;
ELSE
wcwp := '0';
END IF;
END;
PROCEDURE cwp_ctrl (
r : in registers;
xc_wim : in std_logic_vector ( 8 - 1 downto 0 );
inst : word;
de_cwp : out cwptype;
wovf_exc : out std_ulogic;
wunf_exc : out std_ulogic;
wcwp : out std_ulogic
) IS
VARIABLE op : std_logic_vector ( 1 downto 0 );
VARIABLE op3 : std_logic_vector ( 5 downto 0 );
VARIABLE wim : word;
VARIABLE ncwp : cwptype;
BEGIN
op := inst ( 31 downto 30 );
op3 := inst ( 24 downto 19 );
wovf_exc := '0';
wunf_exc := '0';
wim := ( OTHERS => '0' );
wim ( 8 - 1 downto 0 ) := xc_wim;
ncwp := r.d.cwp;
wcwp := '0';
IF ( op = FMT3 ) and ( ( op3 = RETT ) or ( op3 = RESTORE ) or ( op3 = SAVE ) ) THEN
wcwp := '1';
IF ( op3 = SAVE ) THEN
ncwp := r.d.cwp - 1;
ELSE
ncwp := r.d.cwp + 1;
END IF;
IF wim ( conv_integer ( ncwp ) ) = '1' THEN
IF op3 = SAVE THEN
wovf_exc := '1';
ELSE
wunf_exc := '1';
END IF;
END IF;
END IF;
de_cwp := ncwp;
END;
PROCEDURE rs1_gen (
r : registers;
inst : word;
rs1 : out std_logic_vector ( 4 downto 0 );
rs1mod : out std_ulogic
) IS
VARIABLE op : std_logic_vector ( 1 downto 0 );
VARIABLE op3 : std_logic_vector ( 5 downto 0 );
BEGIN
op := inst ( 31 downto 30 );
op3 := inst ( 24 downto 19 );
rs1 := inst ( 18 downto 14 );
rs1mod := '0';
IF ( op = LDST ) THEN
IF ( ( r.d.cnt = "01" ) and ( ( op3 ( 2 ) and not op3 ( 3 ) ) = '1' ) ) or ( r.d.cnt = "10" ) THEN
rs1mod := '1';
rs1 := inst ( 29 downto 25 );
END IF;
IF ( ( r.d.cnt = "10" ) and ( op3 ( 3 downto 0 ) = "0111" ) ) THEN
rs1 ( 0 ) := '1';
END IF;
END IF;
END;
PROCEDURE lock_gen (
r : registers;
rs2 : std_logic_vector ( 4 downto 0 );
rd : std_logic_vector ( 4 downto 0 );
rfa1 : rfatype;
rfa2 : rfatype;
rfrd : rfatype;
inst : word;
fpc_lock : std_ulogic;
mulinsn : std_ulogic;
divinsn : std_ulogic;
lldcheck1 : out std_ulogic;
lldcheck2 : out std_ulogic;
lldlock : out std_ulogic;
lldchkra : out std_ulogic;
lldchkex : out std_ulogic
) IS
VARIABLE op : std_logic_vector ( 1 downto 0 );
VARIABLE op2 : std_logic_vector ( 2 downto 0 );
VARIABLE op3 : std_logic_vector ( 5 downto 0 );
VARIABLE cond : std_logic_vector ( 3 downto 0 );
VARIABLE rs1 : std_logic_vector ( 4 downto 0 );
VARIABLE i : std_ulogic;
VARIABLE ldcheck1 : std_ulogic;
VARIABLE ldcheck2 : std_ulogic;
VARIABLE ldchkra : std_ulogic;
VARIABLE ldchkex : std_ulogic;
VARIABLE ldcheck3 : std_ulogic;
VARIABLE ldlock : std_ulogic;
VARIABLE icc_check : std_ulogic;
VARIABLE bicc_hold : std_ulogic;
VARIABLE chkmul : std_ulogic;
VARIABLE y_check : std_ulogic;
VARIABLE lddlock : boolean;
BEGIN
op := inst ( 31 downto 30 );
op3 := inst ( 24 downto 19 );
op2 := inst ( 24 downto 22 );
cond := inst ( 28 downto 25 );
rs1 := inst ( 18 downto 14 );
lddlock := false;
i := inst ( 13 );
ldcheck1 := '0';
ldcheck2 := '0';
ldcheck3 := '0';
ldlock := '0';
ldchkra := '1';
ldchkex := '1';
icc_check := '0';
bicc_hold := '0';
y_check := '0';
IF ( r.d.annul = '0' ) THEN
CASE op IS
WHEN FMT2 =>
IF ( op2 = BICC ) and ( cond ( 2 downto 0 ) /= "000" ) THEN
icc_check := '1';
END IF;
WHEN FMT3 =>
ldcheck1 := '1';
ldcheck2 := not i;
CASE op3 IS
WHEN TICC =>
IF ( cond ( 2 downto 0 ) /= "000" ) THEN
icc_check := '1';
END IF;
WHEN RDY =>
ldcheck1 := '0';
ldcheck2 := '0';
WHEN RDWIM | RDTBR =>
ldcheck1 := '0';
ldcheck2 := '0';
WHEN RDPSR =>
ldcheck1 := '0';
ldcheck2 := '0';
icc_check := '1';
icc_check := '1';
WHEN SDIV | SDIVCC | UDIV | UDIVCC =>
y_check := '1';
WHEN FPOP1 | FPOP2 =>
ldcheck1 := '0';
ldcheck2 := '0';
WHEN OTHERS =>
NULL;
END CASE;
WHEN LDST =>
ldcheck1 := '1';
ldchkra := '0';
CASE r.d.cnt IS
WHEN "00" =>
ldcheck2 := not i;
ldchkra := '1';
WHEN "01" =>
ldcheck2 := not i;
WHEN OTHERS =>
ldchkex := '0';
END CASE;
IF ( op3 ( 2 downto 0 ) = "011" ) THEN
lddlock := true;
END IF;
WHEN OTHERS =>
NULL;
END CASE;
END IF;
chkmul := mulinsn;
bicc_hold := bicc_hold or ( icc_check and r.m.ctrl.wicc and ( r.m.ctrl.cnt ( 0 ) or r.m.mul ) );
bicc_hold := bicc_hold or ( y_check and ( r.a.ctrl.wy or r.e.ctrl.wy ) );
chkmul := chkmul or divinsn;
bicc_hold := bicc_hold or ( icc_check and ( r.a.ctrl.wicc or r.e.ctrl.wicc ) );
IF ( ( ( r.a.ctrl.ld or chkmul ) and r.a.ctrl.wreg and ldchkra ) = '1' ) and ( ( ( ldcheck1 = '1' ) and ( r.a.ctrl.rd = rfa1 ) ) or ( ( ldcheck2 = '1' ) and ( r.a.ctrl.rd = rfa2 ) ) or ( ( ldcheck3 = '1' ) and ( r.a.ctrl.rd = rfrd ) ) ) THEN
ldlock := '1';
END IF;
IF ( ( ( r.e.ctrl.ld or r.e.mac ) and r.e.ctrl.wreg and ldchkex ) = '1' ) and ( ( ( ldcheck1 = '1' ) and ( r.e.ctrl.rd = rfa1 ) ) or ( ( ldcheck2 = '1' ) and ( r.e.ctrl.rd = rfa2 ) ) ) THEN
ldlock := '1';
END IF;
ldlock := ldlock or bicc_hold or fpc_lock;
lldcheck1 := ldcheck1;
lldcheck2 := ldcheck2;
lldlock := ldlock;
lldchkra := ldchkra;
lldchkex := ldchkex;
END;
PROCEDURE fpbranch (
inst : in word;
fcc : in std_logic_vector ( 1 downto 0 );
branch : out std_ulogic
) IS
VARIABLE cond : std_logic_vector ( 3 downto 0 );
VARIABLE fbres : std_ulogic;
BEGIN
cond := inst ( 28 downto 25 );
CASE cond ( 2 downto 0 ) IS
WHEN "000" =>
fbres := '0';
WHEN "001" =>
fbres := fcc ( 1 ) or fcc ( 0 );
WHEN "010" =>
fbres := fcc ( 1 ) xor fcc ( 0 );
WHEN "011" =>
fbres := fcc ( 0 );
WHEN "100" =>
fbres := ( not fcc ( 1 ) ) and fcc ( 0 );
WHEN "101" =>
fbres := fcc ( 1 );
WHEN "110" =>
fbres := fcc ( 1 ) and not fcc ( 0 );
WHEN OTHERS =>
fbres := fcc ( 1 ) and fcc ( 0 );
END CASE;
branch := cond ( 3 ) xor fbres;
END;
PROCEDURE ic_ctrl (
r : registers;
inst : word;
annul_all : in std_ulogic;
ldlock : in std_ulogic;
branch_true : in std_ulogic;
fbranch_true : in std_ulogic;
cbranch_true : in std_ulogic;
fccv : in std_ulogic;
cccv : in std_ulogic;
cnt : out std_logic_vector ( 1 downto 0 );
de_pc : out pctype;
de_branch : out std_ulogic;
ctrl_annul : out std_ulogic;
de_annul : out std_ulogic;
jmpl_inst : out std_ulogic;
inull : out std_ulogic;
de_pv : out std_ulogic;
ctrl_pv : out std_ulogic;
de_hold_pc : out std_ulogic;
ticc_exception : out std_ulogic;
rett_inst : out std_ulogic;
mulstart : out std_ulogic;
divstart : out std_ulogic
) IS
VARIABLE op : std_logic_vector ( 1 downto 0 );
VARIABLE op2 : std_logic_vector ( 2 downto 0 );
VARIABLE op3 : std_logic_vector ( 5 downto 0 );
VARIABLE cond : std_logic_vector ( 3 downto 0 );
VARIABLE hold_pc : std_ulogic;
VARIABLE annul_current : std_ulogic;
VARIABLE annul_next : std_ulogic;
VARIABLE branch : std_ulogic;
VARIABLE annul : std_ulogic;
VARIABLE pv : std_ulogic;
VARIABLE de_jmpl : std_ulogic;
BEGIN
branch := '0';
annul_next := '0';
annul_current := '0';
pv := '1';
hold_pc := '0';
ticc_exception := '0';
rett_inst := '0';
op := inst ( 31 downto 30 );
op3 := inst ( 24 downto 19 );
op2 := inst ( 24 downto 22 );
cond := inst ( 28 downto 25 );
annul := inst ( 29 );
de_jmpl := '0';
cnt := "00";
mulstart := '0';
divstart := '0';
IF r.d.annul = '0' THEN
CASE inst ( 31 downto 30 ) IS
WHEN CALL =>
branch := '1';
IF r.d.inull = '1' THEN
hold_pc := '1';
annul_current := '1';
END IF;
WHEN FMT2 =>
IF ( op2 = BICC ) THEN
branch := branch_true;
IF hold_pc = '0' THEN
IF ( branch = '1' ) THEN
IF ( cond = BA ) and ( annul = '1' ) THEN
annul_next := '1';
END IF;
ELSE
annul_next := annul;
END IF;
IF r.d.inull = '1' THEN
hold_pc := '1';
annul_current := '1';
annul_next := '0';
END IF;
END IF;
END IF;
WHEN FMT3 =>
CASE op3 IS
WHEN UMUL | SMUL | UMULCC | SMULCC =>
CASE r.d.cnt IS
WHEN "00" =>
cnt := "01";
hold_pc := '1';
pv := '0';
mulstart := '1';
WHEN "01" =>
IF mulo.nready = '1' THEN
cnt := "00";
ELSE
cnt := "01";
pv := '0';
hold_pc := '1';
END IF;
WHEN OTHERS =>
NULL;
END CASE;
WHEN UDIV | SDIV | UDIVCC | SDIVCC =>
CASE r.d.cnt IS
WHEN "00" =>
cnt := "01";
hold_pc := '1';
pv := '0';
divstart := '1';
WHEN "01" =>
IF divo.nready = '1' THEN
cnt := "00";
ELSE
cnt := "01";
pv := '0';
hold_pc := '1';
END IF;
WHEN OTHERS =>
NULL;
END CASE;
WHEN TICC =>
IF branch_true = '1' THEN
ticc_exception := '1';
END IF;
WHEN RETT =>
rett_inst := '1';
WHEN JMPL =>
de_jmpl := '1';
WHEN WRY =>
IF FALSE THEN
IF inst ( 29 downto 25 ) = "10011" THEN
CASE r.d.cnt IS
WHEN "00" =>
pv := '0';
cnt := "00";
hold_pc := '1';
IF r.x.ipend = '1' THEN
cnt := "01";
END IF;
WHEN "01" =>
cnt := "00";
WHEN OTHERS =>
NULL;
END CASE;
END IF;
END IF;
WHEN OTHERS =>
NULL;
END CASE;
WHEN OTHERS =>
CASE r.d.cnt IS
WHEN "00" =>
IF ( op3 ( 2 ) = '1' ) or ( op3 ( 1 downto 0 ) = "11" ) THEN
cnt := "01";
hold_pc := '1';
pv := '0';
END IF;
WHEN "01" =>
IF ( op3 ( 2 downto 0 ) = "111" ) or ( op3 ( 3 downto 0 ) = "1101" ) or ( ( ( 0 = 1 ) or ( 0 /= 0 ) ) and ( ( op3 ( 5 ) & op3 ( 2 downto 0 ) ) = "1110" ) ) THEN
cnt := "10";
pv := '0';
hold_pc := '1';
ELSE
cnt := "00";
END IF;
WHEN "10" =>
cnt := "00";
WHEN OTHERS =>
NULL;
END CASE;
END CASE;
END IF;
IF ldlock = '1' THEN
cnt := r.d.cnt;
annul_next := '0';
pv := '1';
END IF;
hold_pc := ( hold_pc or ldlock ) and not annul_all;
IF hold_pc = '1' THEN
de_pc := r.d.pc;
ELSE
de_pc := r.f.pc;
END IF;
annul_current := ( annul_current or ldlock or annul_all );
ctrl_annul := r.d.annul or annul_all or annul_current;
pv := pv and not ( ( r.d.inull and not hold_pc ) or annul_all );
jmpl_inst := de_jmpl and not annul_current;
annul_next := ( r.d.inull and not hold_pc ) or annul_next or annul_all;
IF ( annul_next = '1' ) or ( rstn = '0' ) THEN
cnt := ( OTHERS => '0' );
END IF;
de_hold_pc := hold_pc;
de_branch := branch;
de_annul := annul_next;
de_pv := pv;
ctrl_pv := r.d.pv and not ( ( r.d.annul and not r.d.pv ) or annul_all or annul_current );
inull := ( not rstn ) or r.d.inull or hold_pc or annul_all;
END;
PROCEDURE rd_gen (
r : registers;
inst : word;
wreg : out std_ulogic;
ld : out std_ulogic;
rdo : out std_logic_vector ( 4 downto 0 )
) IS
VARIABLE write_reg : std_ulogic;
VARIABLE op : std_logic_vector ( 1 downto 0 );
VARIABLE op2 : std_logic_vector ( 2 downto 0 );
VARIABLE op3 : std_logic_vector ( 5 downto 0 );
VARIABLE rd : std_logic_vector ( 4 downto 0 );
BEGIN
op := inst ( 31 downto 30 );
op2 := inst ( 24 downto 22 );
op3 := inst ( 24 downto 19 );
write_reg := '0';
rd := inst ( 29 downto 25 );
ld := '0';
CASE op IS
WHEN CALL =>
write_reg := '1';
rd := "01111";
WHEN FMT2 =>
IF ( op2 = SETHI ) THEN
write_reg := '1';
END IF;
WHEN FMT3 =>
CASE op3 IS
WHEN UMUL | SMUL | UMULCC | SMULCC =>
IF ( ( ( mulo.nready = '1' ) and ( r.d.cnt /= "00" ) ) ) THEN
write_reg := '1';
END IF;
WHEN UDIV | SDIV | UDIVCC | SDIVCC =>
IF ( divo.nready = '1' ) and ( r.d.cnt /= "00" ) THEN
write_reg := '1';
END IF;
WHEN RETT | WRPSR | WRY | WRWIM | WRTBR | TICC | FLUSH =>
NULL;
WHEN FPOP1 | FPOP2 =>
NULL;
WHEN CPOP1 | CPOP2 =>
NULL;
WHEN OTHERS =>
write_reg := '1';
END CASE;
WHEN OTHERS =>
ld := not op3 ( 2 );
IF ( op3 ( 2 ) = '0' ) and not ( ( ( 0 = 1 ) or ( 0 /= 0 ) ) and ( op3 ( 5 ) = '1' ) ) THEN
write_reg := '1';
END IF;
CASE op3 IS
WHEN SWAP | SWAPA | LDSTUB | LDSTUBA =>
IF r.d.cnt = "00" THEN
write_reg := '1';
ld := '1';
END IF;
WHEN OTHERS =>
NULL;
END CASE;
IF r.d.cnt = "01" THEN
CASE op3 IS
WHEN LDD | LDDA | LDDC | LDDF =>
rd ( 0 ) := '1';
WHEN OTHERS =>
NULL;
END CASE;
END IF;
END CASE;
IF ( rd = "00000" ) THEN
write_reg := '0';
END IF;
wreg := write_reg;
rdo := rd;
END;
FUNCTION imm_data (
r : registers;
insn : word
) RETURN word IS
VARIABLE immediate_data : word;
VARIABLE inst : word;
BEGIN
immediate_data := ( OTHERS => '0' );
inst := insn;
CASE inst ( 31 downto 30 ) IS
WHEN FMT2 =>
immediate_data := inst ( 21 downto 0 ) & "0000000000";
WHEN OTHERS =>
immediate_data ( 31 downto 13 ) := ( OTHERS => inst ( 12 ) );
immediate_data ( 12 downto 0 ) := inst ( 12 downto 0 );
END CASE;
RETURN ( immediate_data );
END;
FUNCTION get_spr (
r : registers
) RETURN word IS
VARIABLE spr : word;
BEGIN
spr := ( OTHERS => '0' );
CASE r.e.ctrl.inst ( 24 downto 19 ) IS
WHEN RDPSR =>
spr ( 31 downto 5 ) := conv_std_logic_vector ( 15 , 4 ) & conv_std_logic_vector ( 3 , 4 ) & r.m.icc & "000000" & r.w.s.ec & r.w.s.ef & r.w.s.pil & r.e.su & r.w.s.ps & r.e.et;
spr ( 3 - 1 downto 0 ) := r.e.cwp;
WHEN RDTBR =>
spr ( 31 downto 4 ) := r.w.s.tba & r.w.s.tt;
WHEN RDWIM =>
spr ( 8 - 1 downto 0 ) := r.w.s.wim;
WHEN OTHERS =>
NULL;
END CASE;
RETURN ( spr );
END;
FUNCTION imm_select (
inst : word
) RETURN boolean IS
VARIABLE imm : boolean;
BEGIN
imm := false;
CASE inst ( 31 downto 30 ) IS
WHEN FMT2 =>
CASE inst ( 24 downto 22 ) IS
WHEN SETHI =>
imm := true;
WHEN OTHERS =>
NULL;
END CASE;
WHEN FMT3 =>
CASE inst ( 24 downto 19 ) IS
WHEN RDWIM | RDPSR | RDTBR =>
imm := true;
WHEN OTHERS =>
IF ( inst ( 13 ) = '1' ) THEN
imm := true;
END IF;
END CASE;
WHEN LDST =>
IF ( inst ( 13 ) = '1' ) THEN
imm := true;
END IF;
WHEN OTHERS =>
NULL;
END CASE;
RETURN ( imm );
END;
PROCEDURE alu_op (
r : in registers;
iop1 : in word;
iop2 : in word;
me_icc : std_logic_vector ( 3 downto 0 );
my : std_ulogic;
ldbp : std_ulogic;
aop1 : out word;
aop2 : out word;
aluop : out std_logic_vector ( 2 downto 0 );
alusel : out std_logic_vector ( 1 downto 0 );
aluadd : out std_ulogic;
shcnt : out std_logic_vector ( 4 downto 0 );
sari : out std_ulogic;
shleft : out std_ulogic;
ymsb : out std_ulogic;
mulins : out std_ulogic;
divins : out std_ulogic;
mulstep : out std_ulogic;
macins : out std_ulogic;
ldbp2 : out std_ulogic;
invop2 : out std_ulogic
) IS
VARIABLE op : std_logic_vector ( 1 downto 0 );
VARIABLE op2 : std_logic_vector ( 2 downto 0 );
VARIABLE op3 : std_logic_vector ( 5 downto 0 );
VARIABLE rd : std_logic_vector ( 4 downto 0 );
VARIABLE icc : std_logic_vector ( 3 downto 0 );
VARIABLE y0 : std_ulogic;
BEGIN
op := r.a.ctrl.inst ( 31 downto 30 );
op2 := r.a.ctrl.inst ( 24 downto 22 );
op3 := r.a.ctrl.inst ( 24 downto 19 );
aop1 := iop1;
aop2 := iop2;
ldbp2 := ldbp;
aluop := "000";
alusel := "11";
aluadd := '1';
shcnt := iop2 ( 4 downto 0 );
sari := '0';
shleft := '0';
invop2 := '0';
ymsb := iop1 ( 0 );
mulins := '0';
divins := '0';
mulstep := '0';
macins := '0';
IF r.e.ctrl.wy = '1' THEN
y0 := my;
ELSIF r.m.ctrl.wy = '1' THEN
y0 := r.m.y ( 0 );
ELSIF r.x.ctrl.wy = '1' THEN
y0 := r.x.y ( 0 );
ELSE
y0 := r.w.s.y ( 0 );
END IF;
IF r.e.ctrl.wicc = '1' THEN
icc := me_icc;
ELSIF r.m.ctrl.wicc = '1' THEN
icc := r.m.icc;
ELSIF r.x.ctrl.wicc = '1' THEN
icc := r.x.icc;
ELSE
icc := r.w.s.icc;
END IF;
CASE op IS
WHEN CALL =>
aluop := "111";
WHEN FMT2 =>
CASE op2 IS
WHEN SETHI =>
aluop := "001";
WHEN OTHERS =>
NULL;
END CASE;
WHEN FMT3 =>
CASE op3 IS
WHEN IADD | ADDX | ADDCC | ADDXCC | TADDCC | TADDCCTV | SAVE | RESTORE | TICC | JMPL | RETT =>
alusel := "00";
WHEN ISUB | SUBX | SUBCC | SUBXCC | TSUBCC | TSUBCCTV =>
alusel := "00";
aluadd := '0';
aop2 := not iop2;
invop2 := '1';
WHEN MULSCC =>
alusel := "00";
aop1 := ( icc ( 3 ) xor icc ( 1 ) ) & iop1 ( 31 downto 1 );
IF y0 = '0' THEN
aop2 := ( OTHERS => '0' );
ldbp2 := '0';
END IF;
mulstep := '1';
WHEN UMUL | UMULCC | SMUL | SMULCC =>
mulins := '1';
WHEN UMAC | SMAC =>
NULL;
WHEN UDIV | UDIVCC | SDIV | SDIVCC =>
aluop := "110";
alusel := "10";
divins := '1';
WHEN IAND | ANDCC =>
aluop := "000";
alusel := "10";
WHEN ANDN | ANDNCC =>
aluop := "100";
alusel := "10";
WHEN IOR | ORCC =>
aluop := "010";
alusel := "10";
WHEN ORN | ORNCC =>
aluop := "101";
alusel := "10";
WHEN IXNOR | XNORCC =>
aluop := "011";
alusel := "10";
WHEN XORCC | IXOR | WRPSR | WRWIM | WRTBR | WRY =>
aluop := "001";
alusel := "10";
WHEN RDPSR | RDTBR | RDWIM =>
aluop := "110";
WHEN RDY =>
aluop := "101";
WHEN ISLL =>
aluop := "001";
alusel := "01";
shleft := '1';
shcnt := not iop2 ( 4 downto 0 );
invop2 := '1';
WHEN ISRL =>
aluop := "010";
alusel := "01";
WHEN ISRA =>
aluop := "100";
alusel := "01";
sari := iop1 ( 31 );
WHEN FPOP1 | FPOP2 =>
NULL;
WHEN OTHERS =>
NULL;
END CASE;
WHEN OTHERS =>
CASE r.a.ctrl.cnt IS
WHEN "00" =>
alusel := "00";
WHEN "01" =>
CASE op3 IS
WHEN LDD | LDDA | LDDC =>
alusel := "00";
WHEN LDDF =>
alusel := "00";
WHEN SWAP | SWAPA | LDSTUB | LDSTUBA =>
alusel := "00";
WHEN STF | STDF =>
NULL;
WHEN OTHERS =>
aluop := "000";
IF op3 ( 2 ) = '1' THEN
IF op3 ( 1 downto 0 ) = "01" THEN
aluop := "010";
ELSIF op3 ( 1 downto 0 ) = "10" THEN
aluop := "011";
END IF;
END IF;
END CASE;
WHEN "10" =>
aluop := "000";
IF op3 ( 2 ) = '1' THEN
IF ( op3 ( 3 ) and not op3 ( 1 ) ) = '1' THEN
aluop := "100";
END IF;
END IF;
WHEN OTHERS =>
NULL;
END CASE;
END CASE;
END;
FUNCTION ra_inull_gen (
r : registers;
v : registers
) RETURN std_ulogic IS
VARIABLE de_inull : std_ulogic;
BEGIN
de_inull := '0';
IF ( ( v.e.jmpl or v.e.ctrl.rett ) and not v.e.ctrl.annul and not ( r.e.jmpl and not r.e.ctrl.annul ) ) = '1' THEN
de_inull := '1';
END IF;
IF ( ( v.a.jmpl or v.a.ctrl.rett ) and not v.a.ctrl.annul and not ( r.a.jmpl and not r.a.ctrl.annul ) ) = '1' THEN
de_inull := '1';
END IF;
RETURN ( de_inull );
END;
PROCEDURE op_mux (
r : in registers;
rfd : in word;
ed : in word;
md : in word;
xd : in word;
im : in word;
rsel : in std_logic_vector ( 2 downto 0 );
ldbp : out std_ulogic;
d : out word
) IS
BEGIN
ldbp := '0';
CASE rsel IS
WHEN "000" =>
d := rfd;
WHEN "001" =>
d := ed;
WHEN "010" =>
d := md;
ldbp := r.m.ctrl.ld;
WHEN "011" =>
d := xd;
WHEN "100" =>
d := im;
WHEN "101" =>
d := ( OTHERS => '0' );
WHEN "110" =>
d := r.w.result;
WHEN OTHERS =>
d := ( OTHERS => '-' );
END CASE;
END;
PROCEDURE op_find (
r : in registers;
ldchkra : std_ulogic;
ldchkex : std_ulogic;
rs1 : std_logic_vector ( 4 downto 0 );
ra : rfatype;
im : boolean;
rfe : out std_ulogic;
osel : out std_logic_vector ( 2 downto 0 );
ldcheck : std_ulogic
) IS
BEGIN
rfe := '0';
IF im THEN
osel := "100";
ELSIF rs1 = "00000" THEN
osel := "101";
ELSIF ( ( r.a.ctrl.wreg and ldchkra ) = '1' ) and ( ra = r.a.ctrl.rd ) THEN
osel := "001";
ELSIF ( ( r.e.ctrl.wreg and ldchkex ) = '1' ) and ( ra = r.e.ctrl.rd ) THEN
osel := "010";
ELSIF r.m.ctrl.wreg = '1' and ( ra = r.m.ctrl.rd ) THEN
osel := "011";
ELSE
osel := "000";
rfe := ldcheck;
END IF;
END;
PROCEDURE cin_gen (
r : registers;
me_cin : in std_ulogic;
cin : out std_ulogic
) IS
VARIABLE op : std_logic_vector ( 1 downto 0 );
VARIABLE op3 : std_logic_vector ( 5 downto 0 );
VARIABLE ncin : std_ulogic;
BEGIN
op := r.a.ctrl.inst ( 31 downto 30 );
op3 := r.a.ctrl.inst ( 24 downto 19 );
IF r.e.ctrl.wicc = '1' THEN
ncin := me_cin;
ELSE
ncin := r.m.icc ( 0 );
END IF;
cin := '0';
CASE op IS
WHEN FMT3 =>
CASE op3 IS
WHEN ISUB | SUBCC | TSUBCC | TSUBCCTV =>
cin := '1';
WHEN ADDX | ADDXCC =>
cin := ncin;
WHEN SUBX | SUBXCC =>
cin := not ncin;
WHEN OTHERS =>
NULL;
END CASE;
WHEN OTHERS =>
NULL;
END CASE;
END;
PROCEDURE logic_op (
r : registers;
aluin1 : word;
aluin2 : word;
mey : word;
ymsb : std_ulogic;
logicres : out word;
y : out word
) IS
VARIABLE logicout : word;
BEGIN
CASE r.e.aluop IS
WHEN "000" =>
logicout := aluin1 and aluin2;
WHEN "100" =>
logicout := aluin1 and not aluin2;
WHEN "010" =>
logicout := aluin1 or aluin2;
WHEN "101" =>
logicout := aluin1 or not aluin2;
WHEN "001" =>
logicout := aluin1 xor aluin2;
WHEN "011" =>
logicout := aluin1 xor not aluin2;
WHEN "110" =>
logicout := aluin2;
WHEN OTHERS =>
logicout := ( OTHERS => '-' );
END CASE;
IF ( r.e.ctrl.wy and r.e.mulstep ) = '1' THEN
y := ymsb & r.m.y ( 31 downto 1 );
ELSIF r.e.ctrl.wy = '1' THEN
y := logicout;
ELSIF r.m.ctrl.wy = '1' THEN
y := mey;
ELSIF r.x.ctrl.wy = '1' THEN
y := r.x.y;
ELSE
y := r.w.s.y;
END IF;
logicres := logicout;
END;
PROCEDURE misc_op (
r : registers;
wpr : watchpoint_registers;
aluin1 : word;
aluin2 : word;
ldata : word;
mey : word;
mout : out word;
edata : out word
) IS
VARIABLE miscout : word;
VARIABLE bpdata : word;
VARIABLE stdata : word;
VARIABLE wpi : integer;
BEGIN
wpi := 0;
miscout := r.e.ctrl.pc ( 31 downto 2 ) & "00";
edata := aluin1;
bpdata := aluin1;
IF ( ( r.x.ctrl.wreg and r.x.ctrl.ld and not r.x.ctrl.annul ) = '1' ) and ( r.x.ctrl.rd = r.e.ctrl.rd ) and ( r.e.ctrl.inst ( 31 downto 30 ) = LDST ) and ( r.e.ctrl.cnt /= "10" ) THEN
bpdata := ldata;
END IF;
CASE r.e.aluop IS
WHEN "010" =>
miscout := bpdata ( 7 downto 0 ) & bpdata ( 7 downto 0 ) & bpdata ( 7 downto 0 ) & bpdata ( 7 downto 0 );
edata := miscout;
WHEN "011" =>
miscout := bpdata ( 15 downto 0 ) & bpdata ( 15 downto 0 );
edata := miscout;
WHEN "000" =>
miscout := bpdata;
edata := miscout;
WHEN "001" =>
miscout := aluin2;
WHEN "100" =>
miscout := ( OTHERS => '1' );
edata := miscout;
WHEN "101" =>
IF ( r.m.ctrl.wy = '1' ) THEN
miscout := mey;
ELSE
miscout := r.m.y;
END IF;
IF ( r.e.ctrl.inst ( 18 downto 17 ) = "11" ) THEN
wpi := conv_integer ( r.e.ctrl.inst ( 16 downto 15 ) );
IF r.e.ctrl.inst ( 14 ) = '0' THEN
miscout := wpr ( wpi ).addr & '0' & wpr ( wpi ).exec;
ELSE
miscout := wpr ( wpi ).mask & wpr ( wpi ).load & wpr ( wpi ).store;
END IF;
END IF;
IF ( r.e.ctrl.inst ( 18 downto 17 ) = "10" ) and ( r.e.ctrl.inst ( 14 ) = '1' ) THEN
miscout := asr17_gen ( r );
END IF;
WHEN "110" =>
miscout := get_spr ( r );
WHEN OTHERS =>
NULL;
END CASE;
mout := miscout;
END;
PROCEDURE alu_select (
r : registers;
addout : std_logic_vector ( 32 downto 0 );
op1 : word;
op2 : word;
shiftout : word;
logicout : word;
miscout : word;
res : out word;
me_icc : std_logic_vector ( 3 downto 0 );
icco : out std_logic_vector ( 3 downto 0 );
divz : out std_ulogic
) IS
VARIABLE op : std_logic_vector ( 1 downto 0 );
VARIABLE op3 : std_logic_vector ( 5 downto 0 );
VARIABLE icc : std_logic_vector ( 3 downto 0 );
VARIABLE aluresult : word;
BEGIN
op := r.e.ctrl.inst ( 31 downto 30 );
op3 := r.e.ctrl.inst ( 24 downto 19 );
icc := ( OTHERS => '0' );
CASE r.e.alusel IS
WHEN "00" =>
aluresult := addout ( 32 downto 1 );
IF r.e.aluadd = '0' THEN
icc ( 0 ) := ( ( not op1 ( 31 ) ) and not op2 ( 31 ) ) or ( addout ( 32 ) and ( ( not op1 ( 31 ) ) or not op2 ( 31 ) ) );
icc ( 1 ) := ( op1 ( 31 ) and ( op2 ( 31 ) ) and not addout ( 32 ) ) or ( addout ( 32 ) and ( not op1 ( 31 ) ) and not op2 ( 31 ) );
ELSE
icc ( 0 ) := ( op1 ( 31 ) and op2 ( 31 ) ) or ( ( not addout ( 32 ) ) and ( op1 ( 31 ) or op2 ( 31 ) ) );
icc ( 1 ) := ( op1 ( 31 ) and op2 ( 31 ) and not addout ( 32 ) ) or ( addout ( 32 ) and ( not op1 ( 31 ) ) and ( not op2 ( 31 ) ) );
END IF;
CASE op IS
WHEN FMT3 =>
CASE op3 IS
WHEN TADDCC | TADDCCTV =>
icc ( 1 ) := op1 ( 0 ) or op1 ( 1 ) or op2 ( 0 ) or op2 ( 1 ) or icc ( 1 );
WHEN TSUBCC | TSUBCCTV =>
icc ( 1 ) := op1 ( 0 ) or op1 ( 1 ) or ( not op2 ( 0 ) ) or ( not op2 ( 1 ) ) or icc ( 1 );
WHEN OTHERS =>
NULL;
END CASE;
WHEN OTHERS =>
NULL;
END CASE;
IF aluresult = "00000000000000000000000000000000" THEN
icc ( 2 ) := '1';
END IF;
WHEN "01" =>
aluresult := shiftout;
WHEN "10" =>
aluresult := logicout;
IF aluresult = "00000000000000000000000000000000" THEN
icc ( 2 ) := '1';
END IF;
WHEN OTHERS =>
aluresult := miscout;
END CASE;
IF r.e.jmpl = '1' THEN
aluresult := r.e.ctrl.pc ( 31 downto 2 ) & "00";
END IF;
icc ( 3 ) := aluresult ( 31 );
divz := icc ( 2 );
IF r.e.ctrl.wicc = '1' THEN
IF ( op = FMT3 ) and ( op3 = WRPSR ) THEN
icco := logicout ( 23 downto 20 );
ELSE
icco := icc;
END IF;
ELSIF r.m.ctrl.wicc = '1' THEN
icco := me_icc;
ELSIF r.x.ctrl.wicc = '1' THEN
icco := r.x.icc;
ELSE
icco := r.w.s.icc;
END IF;
res := aluresult;
END;
PROCEDURE dcache_gen (
r : registers;
v : registers;
dci : out dc_in_type;
link_pc : out std_ulogic;
jump : out std_ulogic;
force_a2 : out std_ulogic;
load : out std_ulogic
) IS
VARIABLE op : std_logic_vector ( 1 downto 0 );
VARIABLE op3 : std_logic_vector ( 5 downto 0 );
VARIABLE su : std_ulogic;
BEGIN
op := r.e.ctrl.inst ( 31 downto 30 );
op3 := r.e.ctrl.inst ( 24 downto 19 );
dci.signed := '0';
dci.lock := '0';
dci.dsuen := '0';
dci.size := "10";
IF op = LDST THEN
CASE op3 IS
WHEN LDUB | LDUBA =>
dci.size := "00";
WHEN LDSTUB | LDSTUBA =>
dci.size := "00";
dci.lock := '1';
WHEN LDUH | LDUHA =>
dci.size := "01";
WHEN LDSB | LDSBA =>
dci.size := "00";
dci.signed := '1';
WHEN LDSH | LDSHA =>
dci.size := "01";
dci.signed := '1';
WHEN LD | LDA | LDF | LDC =>
dci.size := "10";
WHEN SWAP | SWAPA =>
dci.size := "10";
dci.lock := '1';
WHEN LDD | LDDA | LDDF | LDDC =>
dci.size := "11";
WHEN STB | STBA =>
dci.size := "00";
WHEN STH | STHA =>
dci.size := "01";
WHEN ST | STA | STF =>
dci.size := "10";
WHEN ISTD | STDA =>
dci.size := "11";
WHEN STDF | STDFQ =>
NULL;
WHEN STDC | STDCQ =>
NULL;
WHEN OTHERS =>
dci.size := "10";
dci.lock := '0';
dci.signed := '0';
END CASE;
END IF;
link_pc := '0';
jump := '0';
force_a2 := '0';
load := '0';
dci.write := '0';
dci.enaddr := '0';
dci.read := not op3 ( 2 );
IF ( r.e.ctrl.annul = '0' ) THEN
CASE op IS
WHEN CALL =>
link_pc := '1';
WHEN FMT3 =>
CASE op3 IS
WHEN JMPL =>
jump := '1';
link_pc := '1';
WHEN RETT =>
jump := '1';
WHEN OTHERS =>
NULL;
END CASE;
WHEN LDST =>
CASE r.e.ctrl.cnt IS
WHEN "00" =>
dci.read := op3 ( 3 ) or not op3 ( 2 );
load := op3 ( 3 ) or not op3 ( 2 );
dci.enaddr := '1';
WHEN "01" =>
force_a2 := not op3 ( 2 );
load := not op3 ( 2 );
dci.enaddr := not op3 ( 2 );
IF op3 ( 3 downto 2 ) = "01" THEN
dci.write := '1';
END IF;
IF op3 ( 3 downto 2 ) = "11" THEN
dci.enaddr := '1';
END IF;
WHEN "10" =>
dci.write := '1';
WHEN OTHERS =>
NULL;
END CASE;
IF ( r.e.ctrl.trap or ( v.x.ctrl.trap and not v.x.ctrl.annul ) ) = '1' THEN
dci.enaddr := '0';
END IF;
WHEN OTHERS =>
NULL;
END CASE;
END IF;
IF ( ( r.x.ctrl.rett and not r.x.ctrl.annul ) = '1' ) THEN
su := r.w.s.ps;
ELSE
su := r.w.s.s;
END IF;
IF su = '1' THEN
dci.asi := "00001011";
ELSE
dci.asi := "00001010";
END IF;
IF ( op3 ( 4 ) = '1' ) and ( ( op3 ( 5 ) = '0' ) or not ( 0 = 1 ) ) THEN
dci.asi := r.e.ctrl.inst ( 12 downto 5 );
END IF;
END;
PROCEDURE fpstdata (
r : in registers;
edata : in word;
eres : in word;
fpstdata : in std_logic_vector ( 31 downto 0 );
edata2 : out word;
eres2 : out word
) IS
VARIABLE op : std_logic_vector ( 1 downto 0 );
VARIABLE op3 : std_logic_vector ( 5 downto 0 );
BEGIN
edata2 := edata;
eres2 := eres;
op := r.e.ctrl.inst ( 31 downto 30 );
op3 := r.e.ctrl.inst ( 24 downto 19 );
END;
FUNCTION ld_align (
data : dcdtype;
set : std_logic_vector ( 1 - 1 downto 0 );
size : std_logic_vector ( 1 downto 0 );
laddr : std_logic_vector ( 1 downto 0 );
signed : std_ulogic
) RETURN word IS
VARIABLE align_data : word;
VARIABLE rdata : word;
BEGIN
align_data := data ( conv_integer ( set ) );
rdata := ( OTHERS => '0' );
CASE size IS
WHEN "00" =>
CASE laddr IS
WHEN "00" =>
rdata ( 7 downto 0 ) := align_data ( 31 downto 24 );
IF signed = '1' THEN
rdata ( 31 downto 8 ) := ( OTHERS => align_data ( 31 ) );
END IF;
WHEN "01" =>
rdata ( 7 downto 0 ) := align_data ( 23 downto 16 );
IF signed = '1' THEN
rdata ( 31 downto 8 ) := ( OTHERS => align_data ( 23 ) );
END IF;
WHEN "10" =>
rdata ( 7 downto 0 ) := align_data ( 15 downto 8 );
IF signed = '1' THEN
rdata ( 31 downto 8 ) := ( OTHERS => align_data ( 15 ) );
END IF;
WHEN OTHERS =>
rdata ( 7 downto 0 ) := align_data ( 7 downto 0 );
IF signed = '1' THEN
rdata ( 31 downto 8 ) := ( OTHERS => align_data ( 7 ) );
END IF;
END CASE;
WHEN "01" =>
IF laddr ( 1 ) = '1' THEN
rdata ( 15 downto 0 ) := align_data ( 15 downto 0 );
IF signed = '1' THEN
rdata ( 31 downto 15 ) := ( OTHERS => align_data ( 15 ) );
END IF;
ELSE
rdata ( 15 downto 0 ) := align_data ( 31 downto 16 );
IF signed = '1' THEN
rdata ( 31 downto 15 ) := ( OTHERS => align_data ( 31 ) );
END IF;
END IF;
WHEN OTHERS =>
rdata := align_data;
END CASE;
RETURN ( rdata );
END;
PROCEDURE mem_trap (
r : registers;
wpr : watchpoint_registers;
annul : in std_ulogic;
holdn : in std_ulogic;
trapout : out std_ulogic;
iflush : out std_ulogic;
nullify : out std_ulogic;
werrout : out std_ulogic;
tt : out std_logic_vector ( 5 downto 0 )
) IS
VARIABLE cwp : std_logic_vector ( 3 - 1 downto 0 );
VARIABLE cwpx : std_logic_vector ( 5 downto 3 );
VARIABLE op : std_logic_vector ( 1 downto 0 );
VARIABLE op2 : std_logic_vector ( 2 downto 0 );
VARIABLE op3 : std_logic_vector ( 5 downto 0 );
VARIABLE nalign_d : std_ulogic;
VARIABLE trap : std_ulogic;
VARIABLE werr : std_ulogic;
BEGIN
op := r.m.ctrl.inst ( 31 downto 30 );
op2 := r.m.ctrl.inst ( 24 downto 22 );
op3 := r.m.ctrl.inst ( 24 downto 19 );
cwpx := r.m.result ( 5 downto 3 );
cwpx ( 5 ) := '0';
iflush := '0';
trap := r.m.ctrl.trap;
nullify := annul;
tt := r.m.ctrl.tt;
werr := ( dco.werr or r.m.werr ) and not r.w.s.dwt;
nalign_d := r.m.nalign or r.m.result ( 2 );
IF ( ( annul or trap ) /= '1' ) and ( r.m.ctrl.pv = '1' ) THEN
IF ( werr and holdn ) = '1' THEN
trap := '1';
tt := TT_DSEX;
werr := '0';
IF op = LDST THEN
nullify := '1';
END IF;
END IF;
END IF;
IF ( ( annul or trap ) /= '1' ) THEN
CASE op IS
WHEN FMT2 =>
CASE op2 IS
WHEN FBFCC =>
NULL;
WHEN CBCCC =>
NULL;
WHEN OTHERS =>
NULL;
END CASE;
WHEN FMT3 =>
CASE op3 IS
WHEN WRPSR =>
IF ( orv ( cwpx ) = '1' ) THEN
trap := '1';
tt := TT_IINST;
END IF;
WHEN UDIV | SDIV | UDIVCC | SDIVCC =>
IF r.m.divz = '1' THEN
trap := '1';
tt := TT_DIV;
END IF;
WHEN JMPL | RETT =>
IF r.m.nalign = '1' THEN
trap := '1';
tt := TT_UNALA;
END IF;
WHEN TADDCCTV | TSUBCCTV =>
IF ( r.m.icc ( 1 ) = '1' ) THEN
trap := '1';
tt := TT_TAG;
END IF;
WHEN FLUSH =>
iflush := '1';
WHEN FPOP1 | FPOP2 =>
NULL;
WHEN CPOP1 | CPOP2 =>
NULL;
WHEN OTHERS =>
NULL;
END CASE;
WHEN LDST =>
IF r.m.ctrl.cnt = "00" THEN
CASE op3 IS
WHEN LDDF | STDF | STDFQ =>
NULL;
WHEN LDDC | STDC | STDCQ =>
NULL;
WHEN LDD | ISTD | LDDA | STDA =>
IF r.m.result ( 2 downto 0 ) /= "000" THEN
trap := '1';
tt := TT_UNALA;
nullify := '1';
END IF;
WHEN LDF | LDFSR | STFSR | STF =>
NULL;
WHEN LDC | LDCSR | STCSR | STC =>
NULL;
WHEN LD | LDA | ST | STA | SWAP | SWAPA =>
IF r.m.result ( 1 downto 0 ) /= "00" THEN
trap := '1';
tt := TT_UNALA;
nullify := '1';
END IF;
WHEN LDUH | LDUHA | LDSH | LDSHA | STH | STHA =>
IF r.m.result ( 0 ) /= '0' THEN
trap := '1';
tt := TT_UNALA;
nullify := '1';
END IF;
WHEN OTHERS =>
NULL;
END CASE;
IF ( ( ( ( wpr ( 0 ).load and not op3 ( 2 ) ) or ( wpr ( 0 ).store and op3 ( 2 ) ) ) = '1' ) and ( ( ( wpr ( 0 ).addr xor r.m.result ( 31 downto 2 ) ) and wpr ( 0 ).mask ) = "000000000000000000000000000000" ) ) THEN
trap := '1';
tt := TT_WATCH;
nullify := '1';
END IF;
IF ( ( ( ( wpr ( 1 ).load and not op3 ( 2 ) ) or ( wpr ( 1 ).store and op3 ( 2 ) ) ) = '1' ) and ( ( ( wpr ( 1 ).addr xor r.m.result ( 31 downto 2 ) ) and wpr ( 1 ).mask ) = "000000000000000000000000000000" ) ) THEN
trap := '1';
tt := TT_WATCH;
nullify := '1';
END IF;
END IF;
WHEN OTHERS =>
NULL;
END CASE;
END IF;
IF ( rstn = '0' ) or ( r.x.rstate = dsu2 ) THEN
werr := '0';
END IF;
trapout := trap;
werrout := werr;
END;
PROCEDURE irq_trap (
r : in registers;
ir : in irestart_register;
irl : in std_logic_vector ( 3 downto 0 );
annul : in std_ulogic;
pv : in std_ulogic;
trap : in std_ulogic;
tt : in std_logic_vector ( 5 downto 0 );
nullify : in std_ulogic;
irqen : out std_ulogic;
irqen2 : out std_ulogic;
nullify2 : out std_ulogic;
trap2 : out std_ulogic;
ipend : out std_ulogic;
tt2 : out std_logic_vector ( 5 downto 0 )
) IS
VARIABLE op : std_logic_vector ( 1 downto 0 );
VARIABLE op3 : std_logic_vector ( 5 downto 0 );
VARIABLE pend : std_ulogic;
BEGIN
nullify2 := nullify;
trap2 := trap;
tt2 := tt;
op := r.m.ctrl.inst ( 31 downto 30 );
op3 := r.m.ctrl.inst ( 24 downto 19 );
irqen := '1';
irqen2 := r.m.irqen;
IF ( annul or trap ) = '0' THEN
IF ( ( op = FMT3 ) and ( op3 = WRPSR ) ) THEN
irqen := '0';
END IF;
END IF;
IF ( irl = "1111" ) or ( irl > r.w.s.pil ) THEN
pend := r.m.irqen and r.m.irqen2 and r.w.s.et and not ir.pwd;
ELSE
pend := '0';
END IF;
ipend := pend;
IF ( ( not annul ) and pv and ( not trap ) and pend ) = '1' THEN
trap2 := '1';
tt2 := "01" & irl;
IF op = LDST THEN
nullify2 := '1';
END IF;
END IF;
END;
PROCEDURE irq_intack (
r : in registers;
holdn : in std_ulogic;
intack : out std_ulogic
) IS
BEGIN
intack := '0';
IF r.x.rstate = trap THEN
IF r.w.s.tt ( 7 downto 4 ) = "0001" THEN
intack := '1';
END IF;
END IF;
END;
PROCEDURE sp_write (
r : registers;
wpr : watchpoint_registers;
s : out special_register_type;
vwpr : out watchpoint_registers
) IS
VARIABLE op : std_logic_vector ( 1 downto 0 );
VARIABLE op2 : std_logic_vector ( 2 downto 0 );
VARIABLE op3 : std_logic_vector ( 5 downto 0 );
VARIABLE rd : std_logic_vector ( 4 downto 0 );
VARIABLE i : integer RANGE 0 to 3;
BEGIN
op := r.x.ctrl.inst ( 31 downto 30 );
op2 := r.x.ctrl.inst ( 24 downto 22 );
op3 := r.x.ctrl.inst ( 24 downto 19 );
s := r.w.s;
rd := r.x.ctrl.inst ( 29 downto 25 );
vwpr := wpr;
CASE op IS
WHEN FMT3 =>
CASE op3 IS
WHEN WRY =>
IF rd = "00000" THEN
s.y := r.x.result;
ELSIF ( rd = "10001" ) THEN
s.dwt := r.x.result ( 14 );
s.svt := r.x.result ( 13 );
ELSIF rd ( 4 downto 3 ) = "11" THEN
CASE rd ( 2 downto 0 ) IS
WHEN "000" =>
vwpr ( 0 ).addr := r.x.result ( 31 downto 2 );
vwpr ( 0 ).imp := r.x.result ( 1 );
vwpr ( 0 ).exec := r.x.result ( 0 );
WHEN "001" =>
vwpr ( 0 ).mask := r.x.result ( 31 downto 2 );
vwpr ( 0 ).load := r.x.result ( 1 );
vwpr ( 0 ).store := r.x.result ( 0 );
WHEN "010" =>
vwpr ( 1 ).addr := r.x.result ( 31 downto 2 );
vwpr ( 1 ).imp := r.x.result ( 1 );
vwpr ( 1 ).exec := r.x.result ( 0 );
WHEN "011" =>
vwpr ( 1 ).mask := r.x.result ( 31 downto 2 );
vwpr ( 1 ).load := r.x.result ( 1 );
vwpr ( 1 ).store := r.x.result ( 0 );
WHEN "100" =>
vwpr ( 2 ).addr := r.x.result ( 31 downto 2 );
vwpr ( 2 ).imp := r.x.result ( 1 );
vwpr ( 2 ).exec := r.x.result ( 0 );
WHEN "101" =>
vwpr ( 2 ).mask := r.x.result ( 31 downto 2 );
vwpr ( 2 ).load := r.x.result ( 1 );
vwpr ( 2 ).store := r.x.result ( 0 );
WHEN "110" =>
vwpr ( 3 ).addr := r.x.result ( 31 downto 2 );
vwpr ( 3 ).imp := r.x.result ( 1 );
vwpr ( 3 ).exec := r.x.result ( 0 );
WHEN OTHERS =>
vwpr ( 3 ).mask := r.x.result ( 31 downto 2 );
vwpr ( 3 ).load := r.x.result ( 1 );
vwpr ( 3 ).store := r.x.result ( 0 );
END CASE;
END IF;
WHEN WRPSR =>
s.cwp := r.x.result ( 3 - 1 downto 0 );
s.icc := r.x.result ( 23 downto 20 );
s.ec := r.x.result ( 13 );
s.pil := r.x.result ( 11 downto 8 );
s.s := r.x.result ( 7 );
s.ps := r.x.result ( 6 );
s.et := r.x.result ( 5 );
WHEN WRWIM =>
s.wim := r.x.result ( 8 - 1 downto 0 );
WHEN WRTBR =>
s.tba := r.x.result ( 31 downto 12 );
WHEN SAVE =>
s.cwp := r.w.s.cwp - 1;
WHEN RESTORE =>
s.cwp := r.w.s.cwp + 1;
WHEN RETT =>
s.cwp := r.w.s.cwp + 1;
s.s := r.w.s.ps;
s.et := '1';
WHEN OTHERS =>
NULL;
END CASE;
WHEN OTHERS =>
NULL;
END CASE;
IF r.x.ctrl.wicc = '1' THEN
s.icc := r.x.icc;
END IF;
IF r.x.ctrl.wy = '1' THEN
s.y := r.x.y;
END IF;
END;
FUNCTION npc_find (
r : registers
) RETURN std_logic_vector IS
VARIABLE npc : std_logic_vector ( 2 downto 0 );
BEGIN
npc := "011";
IF r.m.ctrl.pv = '1' THEN
npc := "000";
ELSIF r.e.ctrl.pv = '1' THEN
npc := "001";
ELSIF r.a.ctrl.pv = '1' THEN
npc := "010";
ELSIF r.d.pv = '1' THEN
npc := "011";
ELSE
npc := "100";
END IF;
RETURN ( npc );
END;
FUNCTION npc_gen (
r : registers
) RETURN word IS
VARIABLE npc : std_logic_vector ( 31 downto 0 );
BEGIN
npc := r.a.ctrl.pc ( 31 downto 2 ) & "00";
CASE r.x.npc IS
WHEN "000" =>
npc ( 31 downto 2 ) := r.x.ctrl.pc ( 31 downto 2 );
WHEN "001" =>
npc ( 31 downto 2 ) := r.m.ctrl.pc ( 31 downto 2 );
WHEN "010" =>
npc ( 31 downto 2 ) := r.e.ctrl.pc ( 31 downto 2 );
WHEN "011" =>
npc ( 31 downto 2 ) := r.a.ctrl.pc ( 31 downto 2 );
WHEN OTHERS =>
npc ( 31 downto 2 ) := r.d.pc ( 31 downto 2 );
END CASE;
RETURN ( npc );
END;
PROCEDURE mul_res (
r : registers;
asr18in : word;
result : out word;
y : out word;
asr18 : out word;
icc : out std_logic_vector ( 3 downto 0 )
) IS
VARIABLE op : std_logic_vector ( 1 downto 0 );
VARIABLE op3 : std_logic_vector ( 5 downto 0 );
BEGIN
op := r.m.ctrl.inst ( 31 downto 30 );
op3 := r.m.ctrl.inst ( 24 downto 19 );
result := r.m.result;
y := r.m.y;
icc := r.m.icc;
asr18 := asr18in;
CASE op IS
WHEN FMT3 =>
CASE op3 IS
WHEN UMUL | SMUL =>
result := mulo.result ( 31 downto 0 );
y := mulo.result ( 63 downto 32 );
WHEN UMULCC | SMULCC =>
result := mulo.result ( 31 downto 0 );
icc := mulo.icc;
y := mulo.result ( 63 downto 32 );
WHEN UMAC | SMAC =>
NULL;
WHEN UDIV | SDIV =>
result := divo.result ( 31 downto 0 );
WHEN UDIVCC | SDIVCC =>
result := divo.result ( 31 downto 0 );
icc := divo.icc;
WHEN OTHERS =>
NULL;
END CASE;
WHEN OTHERS =>
NULL;
END CASE;
END;
FUNCTION powerdwn (
r : registers;
trap : std_ulogic;
rp : pwd_register_type
) RETURN std_ulogic IS
VARIABLE op : std_logic_vector ( 1 downto 0 );
VARIABLE op3 : std_logic_vector ( 5 downto 0 );
VARIABLE rd : std_logic_vector ( 4 downto 0 );
VARIABLE pd : std_ulogic;
BEGIN
op := r.x.ctrl.inst ( 31 downto 30 );
op3 := r.x.ctrl.inst ( 24 downto 19 );
rd := r.x.ctrl.inst ( 29 downto 25 );
pd := '0';
IF ( not ( r.x.ctrl.annul or trap ) and r.x.ctrl.pv ) = '1' THEN
IF ( ( op = FMT3 ) and ( op3 = WRY ) and ( rd = "10011" ) ) THEN
pd := '1';
END IF;
pd := pd or rp.pwd;
END IF;
RETURN ( pd );
END;
SIGNAL dummy : std_ulogic;
SIGNAL cpu_index : std_logic_vector ( 3 downto 0 );
SIGNAL disasen : std_ulogic;
BEGIN
comb : PROCESS ( ico , dco , rfo , r , wpr , ir , dsur , rstn , holdn , irqi , dbgi , fpo , cpo , tbo , mulo , divo , dummy , rp )
VARIABLE v : registers;
VARIABLE vp : pwd_register_type;
VARIABLE vwpr : watchpoint_registers;
VARIABLE vdsu : dsu_registers;
VARIABLE npc : std_logic_vector ( 31 downto 2 );
VARIABLE de_raddr1 : std_logic_vector ( 9 downto 0 );
VARIABLE de_raddr2 : std_logic_vector ( 9 downto 0 );
VARIABLE de_rs2 : std_logic_vector ( 4 downto 0 );
VARIABLE de_rd : std_logic_vector ( 4 downto 0 );
VARIABLE de_hold_pc : std_ulogic;
VARIABLE de_branch : std_ulogic;
VARIABLE de_fpop : std_ulogic;
VARIABLE de_ldlock : std_ulogic;
VARIABLE de_cwp : cwptype;
VARIABLE de_cwp2 : cwptype;
VARIABLE de_inull : std_ulogic;
VARIABLE de_ren1 : std_ulogic;
VARIABLE de_ren2 : std_ulogic;
VARIABLE de_wcwp : std_ulogic;
VARIABLE de_inst : word;
VARIABLE de_branch_address : pctype;
VARIABLE de_icc : std_logic_vector ( 3 downto 0 );
VARIABLE de_fbranch : std_ulogic;
VARIABLE de_cbranch : std_ulogic;
VARIABLE de_rs1mod : std_ulogic;
VARIABLE ra_op1 : word;
VARIABLE ra_op2 : word;
VARIABLE ra_div : std_ulogic;
VARIABLE ex_jump : std_ulogic;
VARIABLE ex_link_pc : std_ulogic;
VARIABLE ex_jump_address : pctype;
VARIABLE ex_add_res : std_logic_vector ( 32 downto 0 );
VARIABLE ex_shift_res : word;
VARIABLE ex_logic_res : word;
VARIABLE ex_misc_res : word;
VARIABLE ex_edata : word;
VARIABLE ex_edata2 : word;
VARIABLE ex_dci : dc_in_type;
VARIABLE ex_force_a2 : std_ulogic;
VARIABLE ex_load : std_ulogic;
VARIABLE ex_ymsb : std_ulogic;
VARIABLE ex_op1 : word;
VARIABLE ex_op2 : word;
VARIABLE ex_result : word;
VARIABLE ex_result2 : word;
VARIABLE mul_op2 : word;
VARIABLE ex_shcnt : std_logic_vector ( 4 downto 0 );
VARIABLE ex_dsuen : std_ulogic;
VARIABLE ex_ldbp2 : std_ulogic;
VARIABLE ex_sari : std_ulogic;
VARIABLE me_inull : std_ulogic;
VARIABLE me_nullify : std_ulogic;
VARIABLE me_nullify2 : std_ulogic;
VARIABLE me_iflush : std_ulogic;
VARIABLE me_newtt : std_logic_vector ( 5 downto 0 );
VARIABLE me_asr18 : word;
VARIABLE me_signed : std_ulogic;
VARIABLE me_size : std_logic_vector ( 1 downto 0 );
VARIABLE me_laddr : std_logic_vector ( 1 downto 0 );
VARIABLE me_icc : std_logic_vector ( 3 downto 0 );
VARIABLE xc_result : word;
VARIABLE xc_df_result : word;
VARIABLE xc_waddr : std_logic_vector ( 9 downto 0 );
VARIABLE xc_exception : std_ulogic;
VARIABLE xc_wreg : std_ulogic;
VARIABLE xc_trap_address : pctype;
VARIABLE xc_vectt : std_logic_vector ( 7 downto 0 );
VARIABLE xc_trap : std_ulogic;
VARIABLE xc_fpexack : std_ulogic;
VARIABLE xc_rstn : std_ulogic;
VARIABLE xc_halt : std_ulogic;
VARIABLE diagdata : word;
VARIABLE tbufi : tracebuf_in_type;
VARIABLE dbgm : std_ulogic;
VARIABLE fpcdbgwr : std_ulogic;
VARIABLE vfpi : fpc_in_type;
VARIABLE dsign : std_ulogic;
VARIABLE pwrd : std_ulogic;
VARIABLE sidle : std_ulogic;
VARIABLE vir : irestart_register;
VARIABLE icnt : std_ulogic;
VARIABLE tbufcntx : std_logic_vector ( 10 + 1 - 4 - 1 downto 0 );
BEGIN
v := r;
vwpr := wpr;
vdsu := dsur;
vp := rp;
xc_fpexack := '0';
sidle := '0';
fpcdbgwr := '0';
vir := ir;
xc_rstn := rstn;
xc_exception := '0';
xc_halt := '0';
icnt := '0';
xc_waddr := ( OTHERS => '0' );
xc_waddr ( 4 + 4 - 1 downto 0 ) := r.x.ctrl.rd ( 4 + 4 - 1 downto 0 );
xc_trap := r.x.mexc or r.x.ctrl.trap;
v.x.nerror := rp.error;
IF r.x.mexc = '1' THEN
xc_vectt := "00" & TT_DAEX;
ELSIF r.x.ctrl.tt = TT_TICC THEN
xc_vectt := '1' & r.x.result ( 6 downto 0 );
ELSE
xc_vectt := "00" & r.x.ctrl.tt;
END IF;
IF r.w.s.svt = '0' THEN
xc_trap_address ( 31 downto 4 ) := r.w.s.tba & xc_vectt;
ELSE
xc_trap_address ( 31 downto 4 ) := r.w.s.tba & "00000000";
END IF;
xc_trap_address ( 3 downto 2 ) := ( OTHERS => '0' );
xc_wreg := '0';
v.x.annul_all := '0';
IF ( r.x.ctrl.ld = '1' ) THEN
xc_result := r.x.data ( 0 );
ELSE
xc_result := r.x.result;
END IF;
xc_df_result := xc_result;
dbgm := dbgexc ( r , dbgi , xc_trap , xc_vectt );
IF ( dbgi.dsuen and dbgi.dbreak ) = '0' THEN
v.x.debug := '0';
END IF;
pwrd := '0';
CASE r.x.rstate IS
WHEN run =>
IF ( not r.x.ctrl.annul and r.x.ctrl.pv and not r.x.debug ) = '1' THEN
icnt := holdn;
END IF;
IF dbgm = '1' THEN
v.x.annul_all := '1';
vir.addr := r.x.ctrl.pc;
v.x.rstate := dsu1;
v.x.debug := '1';
v.x.npc := npc_find ( r );
vdsu.tt := xc_vectt;
vdsu.err := dbgerr ( r , dbgi , xc_vectt );
ELSIF ( pwrd = '1' ) and ( ir.pwd = '0' ) THEN
v.x.annul_all := '1';
vir.addr := r.x.ctrl.pc;
v.x.rstate := dsu1;
v.x.npc := npc_find ( r );
vp.pwd := '1';
ELSIF ( r.x.ctrl.annul or xc_trap ) = '0' THEN
xc_wreg := r.x.ctrl.wreg;
sp_write ( r , wpr , v.w.s , vwpr );
vir.pwd := '0';
ELSIF ( ( not r.x.ctrl.annul ) and xc_trap ) = '1' THEN
xc_exception := '1';
xc_result := r.x.ctrl.pc ( 31 downto 2 ) & "00";
xc_wreg := '1';
v.w.s.tt := xc_vectt;
v.w.s.ps := r.w.s.s;
v.w.s.s := '1';
v.x.annul_all := '1';
v.x.rstate := trap;
xc_waddr := ( OTHERS => '0' );
xc_waddr ( 3 + 3 downto 0 ) := r.w.s.cwp & "0001";
v.x.npc := npc_find ( r );
fpexack ( r , xc_fpexack );
IF r.w.s.et = '0' THEN
xc_wreg := '0';
END IF;
END IF;
WHEN trap =>
xc_result := npc_gen ( r );
xc_wreg := '1';
xc_waddr := ( OTHERS => '0' );
xc_waddr ( 3 + 3 downto 0 ) := r.w.s.cwp & "0010";
IF ( r.w.s.et = '1' ) THEN
v.w.s.et := '0';
v.x.rstate := run;
v.w.s.cwp := r.w.s.cwp - 1;
ELSE
v.x.rstate := dsu1;
xc_wreg := '0';
vp.error := '1';
END IF;
WHEN dsu1 =>
xc_exception := '1';
v.x.annul_all := '1';
xc_trap_address ( 31 downto 2 ) := r.f.pc;
xc_trap_address ( 31 downto 2 ) := ir.addr;
vir.addr := npc_gen ( r ) ( 31 downto 2 );
v.x.rstate := dsu2;
v.x.debug := r.x.debug;
WHEN dsu2 =>
xc_exception := '1';
v.x.annul_all := '1';
xc_trap_address ( 31 downto 2 ) := r.f.pc;
sidle := ( rp.pwd or rp.error ) and ico.idle and dco.idle and not r.x.debug;
IF dbgi.reset = '1' THEN
vp.pwd := '0';
vp.error := '0';
END IF;
IF ( dbgi.dsuen and dbgi.dbreak ) = '1' THEN
v.x.debug := '1';
END IF;
diagwr ( r , dsur , ir , dbgi , wpr , v.w.s , vwpr , vdsu.asi , xc_trap_address , vir.addr , vdsu.tbufcnt , xc_wreg , xc_waddr , xc_result , fpcdbgwr );
xc_halt := dbgi.halt;
IF r.x.ipend = '1' THEN
vp.pwd := '0';
END IF;
IF ( rp.error or rp.pwd or r.x.debug or xc_halt ) = '0' THEN
v.x.rstate := run;
v.x.annul_all := '0';
vp.error := '0';
xc_trap_address ( 31 downto 2 ) := ir.addr;
v.x.debug := '0';
vir.pwd := '1';
END IF;
WHEN OTHERS =>
NULL;
END CASE;
irq_intack ( r , holdn , v.x.intack );
itrace ( r , dsur , vdsu , xc_result , xc_exception , dbgi , rp.error , xc_trap , tbufcntx , tbufi );
vdsu.tbufcnt := tbufcntx;
v.w.except := xc_exception;
v.w.result := xc_result;
IF ( r.x.rstate = dsu2 ) THEN
v.w.except := '0';
END IF;
v.w.wa := xc_waddr ( 4 + 4 - 1 downto 0 );
v.w.wreg := xc_wreg and holdn;
rfi.wdata <= xc_result;
rfi.waddr <= xc_waddr;
rfi.wren <= ( xc_wreg and holdn ) and not dco.scanen;
irqo.intack <= r.x.intack and holdn;
irqo.irl <= r.w.s.tt ( 3 downto 0 );
irqo.pwd <= rp.pwd;
dbgo.halt <= xc_halt;
dbgo.pwd <= rp.pwd;
dbgo.idle <= sidle;
dbgo.icnt <= icnt;
dci.intack <= r.x.intack and holdn;
IF ( xc_rstn = '0' ) THEN
v.w.except := '0';
v.w.s.et := '0';
v.w.s.svt := '0';
v.w.s.dwt := '0';
v.x.annul_all := '1';
v.x.rstate := run;
vir.pwd := '0';
vp.pwd := '0';
v.x.debug := '0';
v.x.nerror := '0';
v.w.s.tt := ( OTHERS => '0' );
IF ( dbgi.dsuen and dbgi.dbreak ) = '1' THEN
v.x.rstate := dsu1;
v.x.debug := '1';
END IF;
END IF;
v.w.s.ef := '0';
v.x.ctrl := r.m.ctrl;
v.x.dci := r.m.dci;
v.x.ctrl.rett := r.m.ctrl.rett and not r.m.ctrl.annul;
v.x.mac := r.m.mac;
v.x.laddr := r.m.result ( 1 downto 0 );
v.x.ctrl.annul := r.m.ctrl.annul or v.x.annul_all;
mul_res ( r , v.w.s.asr18 , v.x.result , v.x.y , me_asr18 , me_icc );
mem_trap ( r , wpr , v.x.ctrl.annul , holdn , v.x.ctrl.trap , me_iflush , me_nullify , v.m.werr , v.x.ctrl.tt );
me_newtt := v.x.ctrl.tt;
irq_trap ( r , ir , irqi.irl , v.x.ctrl.annul , v.x.ctrl.pv , v.x.ctrl.trap , me_newtt , me_nullify , v.m.irqen , v.m.irqen2 , me_nullify2 , v.x.ctrl.trap , v.x.ipend , v.x.ctrl.tt );
IF ( r.m.ctrl.ld or not dco.mds ) = '1' THEN
v.x.data ( 0 ) := dco.data ( 0 );
v.x.data ( 1 ) := dco.data ( 1 );
v.x.set := dco.set ( 1 - 1 downto 0 );
IF dco.mds = '0' THEN
me_size := r.x.dci.size;
me_laddr := r.x.laddr;
me_signed := r.x.dci.signed;
ELSE
me_size := v.x.dci.size;
me_laddr := v.x.laddr;
me_signed := v.x.dci.signed;
END IF;
v.x.data ( 0 ) := ld_align ( v.x.data , v.x.set , me_size , me_laddr , me_signed );
END IF;
v.x.mexc := dco.mexc;
v.x.impwp := '0';
v.x.icc := me_icc;
v.x.ctrl.wicc := r.m.ctrl.wicc and not v.x.annul_all;
IF ( r.x.rstate = dsu2 ) THEN
me_nullify2 := '0';
v.x.set := dco.set ( 1 - 1 downto 0 );
END IF;
dci.maddress <= r.m.result;
dci.enaddr <= r.m.dci.enaddr;
dci.asi <= r.m.dci.asi;
dci.size <= r.m.dci.size;
dci.nullify <= me_nullify2;
dci.lock <= r.m.dci.lock and not r.m.ctrl.annul;
dci.read <= r.m.dci.read;
dci.write <= r.m.dci.write;
dci.flush <= me_iflush;
dci.dsuen <= r.m.dci.dsuen;
dci.msu <= r.m.su;
dci.esu <= r.e.su;
dbgo.ipend <= v.x.ipend;
v.m.ctrl := r.e.ctrl;
ex_op1 := r.e.op1;
ex_op2 := r.e.op2;
v.m.ctrl.rett := r.e.ctrl.rett and not r.e.ctrl.annul;
v.m.ctrl.wreg := r.e.ctrl.wreg and not v.x.annul_all;
ex_ymsb := r.e.ymsb;
mul_op2 := ex_op2;
ex_shcnt := r.e.shcnt;
v.e.cwp := r.a.cwp;
ex_sari := r.e.sari;
v.m.su := r.e.su;
v.m.mul := '0';
IF r.e.ldbp1 = '1' THEN
ex_op1 := r.x.data ( 0 );
ex_sari := r.x.data ( 0 ) ( 31 ) and r.e.ctrl.inst ( 19 ) and r.e.ctrl.inst ( 20 );
END IF;
IF r.e.ldbp2 = '1' THEN
ex_op2 := r.x.data ( 0 );
ex_ymsb := r.x.data ( 0 ) ( 0 );
mul_op2 := ex_op2;
ex_shcnt := r.x.data ( 0 ) ( 4 downto 0 );
IF r.e.invop2 = '1' THEN
ex_op2 := not ex_op2;
ex_shcnt := not ex_shcnt;
END IF;
END IF;
ex_add_res := ( ex_op1 & '1' ) + ( ex_op2 & r.e.alucin );
IF ex_add_res ( 2 downto 1 ) = "00" THEN
v.m.nalign := '0';
ELSE
v.m.nalign := '1';
END IF;
dcache_gen ( r , v , ex_dci , ex_link_pc , ex_jump , ex_force_a2 , ex_load );
ex_jump_address := ex_add_res ( 32 downto 2 + 1 );
logic_op ( r , ex_op1 , ex_op2 , v.x.y , ex_ymsb , ex_logic_res , v.m.y );
ex_shift_res := shift ( r , ex_op1 , ex_op2 , ex_shcnt , ex_sari );
misc_op ( r , wpr , ex_op1 , ex_op2 , xc_df_result , v.x.y , ex_misc_res , ex_edata );
ex_add_res ( 3 ) := ex_add_res ( 3 ) or ex_force_a2;
alu_select ( r , ex_add_res , ex_op1 , ex_op2 , ex_shift_res , ex_logic_res , ex_misc_res , ex_result , me_icc , v.m.icc , v.m.divz );
dbg_cache ( holdn , dbgi , r , dsur , ex_result , ex_dci , ex_result2 , v.m.dci );
fpstdata ( r , ex_edata , ex_result2 , fpo.data , ex_edata2 , v.m.result );
cwp_ex ( r , v.m.wcwp );
v.m.ctrl.annul := v.m.ctrl.annul or v.x.annul_all;
v.m.ctrl.wicc := r.e.ctrl.wicc and not v.x.annul_all;
v.m.mac := r.e.mac;
IF ( r.x.rstate = dsu2 ) THEN
v.m.ctrl.ld := '1';
END IF;
dci.eenaddr <= v.m.dci.enaddr;
dci.eaddress <= ex_add_res ( 32 downto 1 );
dci.edata <= ex_edata2;
v.e.ctrl := r.a.ctrl;
v.e.jmpl := r.a.jmpl;
v.e.ctrl.annul := r.a.ctrl.annul or v.x.annul_all;
v.e.ctrl.rett := r.a.ctrl.rett and not r.a.ctrl.annul;
v.e.ctrl.wreg := r.a.ctrl.wreg and not v.x.annul_all;
v.e.su := r.a.su;
v.e.et := r.a.et;
v.e.ctrl.wicc := r.a.ctrl.wicc and not v.x.annul_all;
exception_detect ( r , wpr , dbgi , r.a.ctrl.trap , r.a.ctrl.tt , v.e.ctrl.trap , v.e.ctrl.tt );
op_mux ( r , rfo.data1 , v.m.result , v.x.result , xc_df_result , "00000000000000000000000000000000" , r.a.rsel1 , v.e.ldbp1 , ra_op1 );
op_mux ( r , rfo.data2 , v.m.result , v.x.result , xc_df_result , r.a.imm , r.a.rsel2 , ex_ldbp2 , ra_op2 );
alu_op ( r , ra_op1 , ra_op2 , v.m.icc , v.m.y ( 0 ) , ex_ldbp2 , v.e.op1 , v.e.op2 , v.e.aluop , v.e.alusel , v.e.aluadd , v.e.shcnt , v.e.sari , v.e.shleft , v.e.ymsb , v.e.mul , ra_div , v.e.mulstep , v.e.mac , v.e.ldbp2 , v.e.invop2 );
cin_gen ( r , v.m.icc ( 0 ) , v.e.alucin );
de_inst := r.d.inst ( conv_integer ( r.d.set ) );
de_icc := r.m.icc;
v.a.cwp := r.d.cwp;
su_et_select ( r , v.w.s.ps , v.w.s.s , v.w.s.et , v.a.su , v.a.et );
wicc_y_gen ( de_inst , v.a.ctrl.wicc , v.a.ctrl.wy );
cwp_ctrl ( r , v.w.s.wim , de_inst , de_cwp , v.a.wovf , v.a.wunf , de_wcwp );
rs1_gen ( r , de_inst , v.a.rs1 , de_rs1mod );
de_rs2 := de_inst ( 4 downto 0 );
de_raddr1 := ( OTHERS => '0' );
de_raddr2 := ( OTHERS => '0' );
IF de_rs1mod = '1' THEN
regaddr ( r.d.cwp , de_inst ( 29 downto 26 ) & v.a.rs1 ( 0 ) , de_raddr1 ( 4 + 4 - 1 downto 0 ) );
ELSE
regaddr ( r.d.cwp , de_inst ( 18 downto 15 ) & v.a.rs1 ( 0 ) , de_raddr1 ( 4 + 4 - 1 downto 0 ) );
END IF;
regaddr ( r.d.cwp , de_rs2 , de_raddr2 ( 4 + 4 - 1 downto 0 ) );
v.a.rfa1 := de_raddr1 ( 4 + 4 - 1 downto 0 );
v.a.rfa2 := de_raddr2 ( 4 + 4 - 1 downto 0 );
rd_gen ( r , de_inst , v.a.ctrl.wreg , v.a.ctrl.ld , de_rd );
regaddr ( de_cwp , de_rd , v.a.ctrl.rd );
fpbranch ( de_inst , fpo.cc , de_fbranch );
fpbranch ( de_inst , cpo.cc , de_cbranch );
v.a.imm := imm_data ( r , de_inst );
lock_gen ( r , de_rs2 , de_rd , v.a.rfa1 , v.a.rfa2 , v.a.ctrl.rd , de_inst , fpo.ldlock , v.e.mul , ra_div , v.a.ldcheck1 , v.a.ldcheck2 , de_ldlock , v.a.ldchkra , v.a.ldchkex );
ic_ctrl ( r , de_inst , v.x.annul_all , de_ldlock , branch_true ( de_icc , de_inst ) , de_fbranch , de_cbranch , fpo.ccv , cpo.ccv , v.d.cnt , v.d.pc , de_branch , v.a.ctrl.annul , v.d.annul , v.a.jmpl , de_inull , v.d.pv , v.a.ctrl.pv , de_hold_pc , v.a.ticc , v.a.ctrl.rett , v.a.mulstart , v.a.divstart );
cwp_gen ( r , v , v.a.ctrl.annul , de_wcwp , de_cwp , v.d.cwp );
v.d.inull := ra_inull_gen ( r , v );
op_find ( r , v.a.ldchkra , v.a.ldchkex , v.a.rs1 , v.a.rfa1 , false , v.a.rfe1 , v.a.rsel1 , v.a.ldcheck1 );
op_find ( r , v.a.ldchkra , v.a.ldchkex , de_rs2 , v.a.rfa2 , imm_select ( de_inst ) , v.a.rfe2 , v.a.rsel2 , v.a.ldcheck2 );
de_branch_address := branch_address ( de_inst , r.d.pc );
v.a.ctrl.annul := v.a.ctrl.annul or v.x.annul_all;
v.a.ctrl.wicc := v.a.ctrl.wicc and not v.a.ctrl.annul;
v.a.ctrl.wreg := v.a.ctrl.wreg and not v.a.ctrl.annul;
v.a.ctrl.rett := v.a.ctrl.rett and not v.a.ctrl.annul;
v.a.ctrl.wy := v.a.ctrl.wy and not v.a.ctrl.annul;
v.a.ctrl.trap := r.d.mexc;
v.a.ctrl.tt := "000000";
v.a.ctrl.inst := de_inst;
v.a.ctrl.pc := r.d.pc;
v.a.ctrl.cnt := r.d.cnt;
v.a.step := r.d.step;
IF holdn = '0' THEN
de_raddr1 ( 4 + 4 - 1 downto 0 ) := r.a.rfa1;
de_raddr2 ( 4 + 4 - 1 downto 0 ) := r.a.rfa2;
de_ren1 := r.a.rfe1;
de_ren2 := r.a.rfe2;
ELSE
de_ren1 := v.a.rfe1;
de_ren2 := v.a.rfe2;
END IF;
IF ( ( dbgi.denable and not dbgi.dwrite ) = '1' ) and ( r.x.rstate = dsu2 ) THEN
de_raddr1 ( 4 + 4 - 1 downto 0 ) := dbgi.daddr ( 4 + 4 + 1 downto 2 );
de_ren1 := '1';
END IF;
v.d.step := dbgi.step and not r.d.annul;
rfi.raddr1 <= de_raddr1;
rfi.raddr2 <= de_raddr2;
rfi.ren1 <= de_ren1 and not dco.scanen;
rfi.ren2 <= de_ren2 and not dco.scanen;
rfi.diag <= dco.testen & "000";
ici.inull <= de_inull;
ici.flush <= me_iflush;
IF ( xc_rstn = '0' ) THEN
v.d.cnt := ( OTHERS => '0' );
END IF;
npc := r.f.pc;
IF ( xc_rstn = '0' ) THEN
v.f.pc := ( OTHERS => '0' );
v.f.branch := '0';
v.f.pc ( 31 downto 12 ) := conv_std_logic_vector ( 16#00000# , 20 );
ELSIF xc_exception = '1' THEN
v.f.branch := '1';
v.f.pc := xc_trap_address;
npc := v.f.pc;
ELSIF de_hold_pc = '1' THEN
v.f.pc := r.f.pc;
v.f.branch := r.f.branch;
IF ex_jump = '1' THEN
v.f.pc := ex_jump_address;
v.f.branch := '1';
npc := v.f.pc;
END IF;
ELSIF ex_jump = '1' THEN
v.f.pc := ex_jump_address;
v.f.branch := '1';
npc := v.f.pc;
ELSIF de_branch = '1' THEN
v.f.pc := branch_address ( de_inst , r.d.pc );
v.f.branch := '1';
npc := v.f.pc;
ELSE
v.f.branch := '0';
v.f.pc ( 31 downto 2 ) := r.f.pc ( 31 downto 2 ) + 1;
npc := v.f.pc;
END IF;
ici.dpc <= r.d.pc ( 31 downto 2 ) & "00";
ici.fpc <= r.f.pc ( 31 downto 2 ) & "00";
ici.rpc <= npc ( 31 downto 2 ) & "00";
ici.fbranch <= r.f.branch;
ici.rbranch <= v.f.branch;
ici.su <= v.a.su;
ici.fline <= ( OTHERS => '0' );
ici.flushl <= '0';
IF ( ico.mds and de_hold_pc ) = '0' THEN
v.d.inst ( 0 ) := ico.data ( 0 );
v.d.inst ( 1 ) := ico.data ( 1 );
v.d.set := ico.set ( 1 - 1 downto 0 );
v.d.mexc := ico.mexc;
END IF;
diagread ( dbgi , r , dsur , ir , wpr , rfo.data1 , dco , tbo , diagdata );
diagrdy ( dbgi.denable , dsur , r.m.dci , dco.mds , ico , vdsu.crdy );
rin <= v;
wprin <= vwpr;
dsuin <= vdsu;
irin <= vir;
muli.start <= r.a.mulstart and not r.a.ctrl.annul;
muli.signed <= r.e.ctrl.inst ( 19 );
muli.op1 <= ( ex_op1 ( 31 ) and r.e.ctrl.inst ( 19 ) ) & ex_op1;
muli.op2 <= ( mul_op2 ( 31 ) and r.e.ctrl.inst ( 19 ) ) & mul_op2;
muli.mac <= r.e.ctrl.inst ( 24 );
muli.acc ( 39 downto 32 ) <= r.x.y ( 7 downto 0 );
muli.acc ( 31 downto 0 ) <= r.w.s.asr18;
muli.flush <= r.x.annul_all;
divi.start <= r.a.divstart and not r.a.ctrl.annul;
divi.signed <= r.e.ctrl.inst ( 19 );
divi.flush <= r.x.annul_all;
divi.op1 <= ( ex_op1 ( 31 ) and r.e.ctrl.inst ( 19 ) ) & ex_op1;
divi.op2 <= ( ex_op2 ( 31 ) and r.e.ctrl.inst ( 19 ) ) & ex_op2;
IF ( r.a.divstart and not r.a.ctrl.annul ) = '1' THEN
dsign := r.a.ctrl.inst ( 19 );
ELSE
dsign := r.e.ctrl.inst ( 19 );
END IF;
divi.y <= ( r.m.y ( 31 ) and dsign ) & r.m.y;
rpin <= vp;
dbgo.dsu <= '1';
dbgo.dsumode <= r.x.debug;
dbgo.crdy <= dsur.crdy ( 2 );
dbgo.data <= diagdata;
tbi <= tbufi;
dbgo.error <= dummy and not r.x.nerror;
END PROCESS;
preg : PROCESS ( sclk )
BEGIN
IF rising_edge ( sclk ) THEN
rp <= rpin;
IF rstn = '0' THEN
rp.error <= '0';
END IF;
END IF;
END PROCESS;
reg : PROCESS ( clk )
BEGIN
IF rising_edge ( clk ) THEN
IF ( holdn = '1' ) THEN
r <= rin;
ELSE
r.x.ipend <= rin.x.ipend;
r.m.werr <= rin.m.werr;
IF ( holdn or ico.mds ) = '0' THEN
r.d.inst <= rin.d.inst;
r.d.mexc <= rin.d.mexc;
r.d.set <= rin.d.set;
END IF;
IF ( holdn or dco.mds ) = '0' THEN
r.x.data <= rin.x.data;
r.x.mexc <= rin.x.mexc;
r.x.impwp <= rin.x.impwp;
r.x.set <= rin.x.set;
END IF;
END IF;
IF rstn = '0' THEN
r.x.error <= '0';
r.w.s.s <= '1';
END IF;
END IF;
END PROCESS;
dsureg : PROCESS ( clk )
BEGIN
IF rising_edge ( clk ) THEN
IF holdn = '1' THEN
dsur <= dsuin;
ELSE
dsur.crdy <= dsuin.crdy;
END IF;
END IF;
END PROCESS;
dsureg2 : PROCESS ( clk )
BEGIN
IF rising_edge ( clk ) THEN
IF holdn = '1' THEN
ir <= irin;
END IF;
END IF;
END PROCESS;
wpreg0 : PROCESS ( clk )
BEGIN
IF rising_edge ( clk ) THEN
IF holdn = '1' THEN
wpr ( 0 ) <= wprin ( 0 );
END IF;
IF rstn = '0' THEN
wpr ( 0 ).exec <= '0';
wpr ( 0 ).load <= '0';
wpr ( 0 ).store <= '0';
END IF;
END IF;
END PROCESS;
wpreg1 : PROCESS ( clk )
BEGIN
IF rising_edge ( clk ) THEN
IF holdn = '1' THEN
wpr ( 1 ) <= wprin ( 1 );
END IF;
IF rstn = '0' THEN
wpr ( 1 ).exec <= '0';
wpr ( 1 ).load <= '0';
wpr ( 1 ).store <= '0';
END IF;
END IF;
END PROCESS;
wpr ( 2 ) <= ( "000000000000000000000000000000" , "000000000000000000000000000000" , '0' , '0' , '0' , '0' );
wpr ( 3 ) <= ( "000000000000000000000000000000" , "000000000000000000000000000000" , '0' , '0' , '0' , '0' );
dummy <= '1';
END ARCHITECTURE;
| mit | 57c5fee1af4d3d9b614312aa38d6aa2b | 0.396197 | 4.075077 | false | false | false | false |
impedimentToProgress/UCI-BlueChip | AttackFiles/Attacks/privEsc/lib/hynix/ddr2/components.vhd | 2 | 1,857 | ----------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2007 GAISLER RESEARCH
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- See the file COPYING for the full details of the license.
--
-----------------------------------------------------------------------------
-- Package: components
-- File: components.vhd
-- Author: Jiri Gaisler, Gaisler Research
-- Description: Component declaration of Hynix RAM
------------------------------------------------------------------------------
-- pragma translate_off
library ieee;
use ieee.std_logic_1164.all;
use std.textio.all;
use work.HY5PS121621F_PACK.all;
package components is
component HY5PS121621F
generic (
TimingCheckFlag : boolean := TRUE;
PUSCheckFlag : boolean := FALSE;
Part_Number : PART_NUM_TYPE := B400);
Port ( DQ : inout std_logic_vector(15 downto 0) := (others => 'Z');
LDQS : inout std_logic := 'Z';
LDQSB : inout std_logic := 'Z';
UDQS : inout std_logic := 'Z';
UDQSB : inout std_logic := 'Z';
LDM : in std_logic;
WEB : in std_logic;
CASB : in std_logic;
RASB : in std_logic;
CSB : in std_logic;
BA : in std_logic_vector(1 downto 0);
ADDR : in std_logic_vector(12 downto 0);
CKE : in std_logic;
CLK : in std_logic;
CLKB : in std_logic;
UDM : in std_logic );
End component;
end;
-- pragma translate_on
| mit | f3a0a5570d7c1b9e3bb9543733a201c1 | 0.510501 | 3.86875 | false | false | false | false |
impedimentToProgress/UCI-BlueChip | AttackFiles/Attacks/privEsc/lib/techmap/umc18/pads_umc18.vhd | 2 | 8,459 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Package: umcpads_gen
-- File: umcpads_gen.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: UMC pad wrappers
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
package umcpads is
-- input pad
component ICMT3V port( A : in std_logic; Z : out std_logic); end component;
-- input pad with pull-up
component ICMT3VPU port( A : in std_logic; Z : out std_logic); end component;
-- input pad with pull-down
component ICMT3VPD port( A : in std_logic; Z : out std_logic); end component;
-- schmitt input pad
component ISTRT3V port( A : in std_logic; Z : out std_logic); end component;
-- output pads
component OCM3V4 port( Z : out std_logic; A : in std_logic); end component;
component OCM3V12 port( Z : out std_logic; A : in std_logic); end component;
component OCM3V24 port( Z : out std_logic; A : in std_logic); end component;
-- tri-state output pads
component OCMTR4 port( EN : in std_logic; A : in std_logic; Z : out std_logic); end component;
component OCMTR12 port( EN : in std_logic; A : in std_logic; Z : out std_logic); end component;
component OCMTR24 port( EN : in std_logic; A : in std_logic; Z : out std_logic); end component;
-- bidirectional pads
component BICM3V4 port( IO : inout std_logic; EN : in std_logic; A : in std_logic; Z : out std_logic); end component;
component BICM3V12 port( IO : inout std_logic; EN : in std_logic; A : in std_logic; Z : out std_logic); end component;
component BICM3V24 port( IO : inout std_logic; EN : in std_logic; A : in std_logic; Z : out std_logic); end component;
end;
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
-- pragma translate_off
library umc18;
use umc18.ICMT3V;
use umc18.ICMT3VPU;
use umc18.ICMT3VPD;
use umc18.ISTRT3V;
-- pragma translate_on
entity umc_inpad is
generic (level : integer := 0; voltage : integer := 0; filter : integer := 0);
port (pad : in std_logic; o : out std_logic);
end;
architecture rtl of umc_inpad is
component ICMT3V port( A : in std_logic; Z : out std_logic); end component;
component ICMT3VPU port( A : in std_logic; Z : out std_logic); end component;
component ICMT3VPD port( A : in std_logic; Z : out std_logic); end component;
component ISTRT3V port( A : in std_logic; Z : out std_logic); end component;
begin
norm : if filter = 0 generate
ip : ICMT3V port map (a => pad, z => o);
end generate;
pu : if filter = pullup generate
ip : ICMT3VPU port map (a => pad, z => o);
end generate;
pd : if filter = pulldown generate
ip : ICMT3VPD port map (a => pad, z => o);
end generate;
sch : if filter = schmitt generate
ip : ISTRT3V port map (a => pad, z => o);
end generate;
end;
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
-- pragma translate_off
library umc18;
use umc18.BICM3V4;
use umc18.BICM3V12;
use umc18.BICM3V24;
-- pragma translate_on
entity umc_iopad is
generic (level : integer := 0; slew : integer := 0;
voltage : integer := 0; strength : integer := 0);
port (pad : inout std_logic; i, en : in std_logic; o : out std_logic);
end ;
architecture rtl of umc_iopad is
component BICM3V4 port( IO : inout std_logic; EN : in std_logic; A : in std_logic; Z : out std_logic); end component;
component BICM3V12 port( IO : inout std_logic; EN : in std_logic; A : in std_logic; Z : out std_logic); end component;
component BICM3V24 port( IO : inout std_logic; EN : in std_logic; A : in std_logic; Z : out std_logic); end component;
begin
f4 : if (strength <= 4) generate
op : BICM3V4 port map (a => i, en => en, io => pad, z => o);
end generate;
f12 : if (strength > 4) and (strength <= 12) generate
op : BICM3V12 port map (a => i, en => en, io => pad, z => o);
end generate;
f24 : if (strength > 16) generate
op : BICM3V24 port map (a => i, en => en, io => pad, z => o);
end generate;
end;
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
-- pragma translate_off
library umc18;
use umc18.OCM3V4;
use umc18.OCM3V12;
use umc18.OCM3V24;
-- pragma translate_on
entity umc_outpad is
generic (level : integer := 0; slew : integer := 0;
voltage : integer := 0; strength : integer := 0);
port (pad : out std_logic; i : in std_logic);
end ;
architecture rtl of umc_outpad is
component OCM3V4 port( Z : out std_logic; A : in std_logic); end component;
component OCM3V12 port( Z : out std_logic; A : in std_logic); end component;
component OCM3V24 port( Z : out std_logic; A : in std_logic); end component;
begin
f4 : if (strength <= 4) generate
op : OCM3V4 port map (a => i, z => pad);
end generate;
f12 : if (strength > 4) and (strength <= 12) generate
op : OCM3V12 port map (a => i, z => pad);
end generate;
f24 : if (strength > 12) generate
op : OCM3V24 port map (a => i, z => pad);
end generate;
end;
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
-- pragma translate_off
library umc18;
use umc18.OCMTR4;
use umc18.OCMTR12;
use umc18.OCMTR24;
-- pragma translate_on
entity umc_toutpad is
generic (level : integer := 0; slew : integer := 0;
voltage : integer := 0; strength : integer := 0);
port (pad : out std_logic; i, en : in std_logic);
end ;
architecture rtl of umc_toutpad is
component OCMTR4 port( EN : in std_logic; A : in std_logic; Z : out std_logic); end component;
component OCMTR12 port( EN : in std_logic; A : in std_logic; Z : out std_logic); end component;
component OCMTR24 port( EN : in std_logic; A : in std_logic; Z : out std_logic); end component;
begin
f4 : if (strength <= 4) generate
op : OCMTR4 port map (a => i, en => en, z => pad);
end generate;
f12 : if (strength > 4) and (strength <= 12) generate
op : OCMTR12 port map (a => i, en => en, z => pad);
end generate;
f24 : if (strength > 12) generate
op : OCMTR24 port map (a => i, en => en, z => pad);
end generate;
end;
library umc18;
-- pragma translate_off
use umc18.LVDS_Driver;
use umc18.LVDS_Receiver;
use umc18.LVDS_Biasmodule;
-- pragma translate_on
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
entity umc_lvds_combo is
generic (voltage : integer := 0; width : integer := 1);
port (odpadp, odpadn, ospadp, ospadn : out std_logic_vector(0 to width-1);
odval, osval, en : in std_logic_vector(0 to width-1);
idpadp, idpadn, ispadp, ispadn : in std_logic_vector(0 to width-1);
idval, isval : out std_logic_vector(0 to width-1);
lvdsref : in std_logic);
end ;
architecture rtl of umc_lvds_combo is
component LVDS_Driver port ( A, Vref, HI : in std_logic; Z, ZN : out std_logic); end component;
component LVDS_Receiver port ( A, AN : in std_logic; Z : out std_logic); end component;
component LVDS_Biasmodule port ( RefR : in std_logic; Vref, HI : out std_logic); end component;
signal vref, hi : std_logic;
begin
lvds_bias: LVDS_Biasmodule port map (lvdsref, vref, hi);
swloop : for i in 0 to width-1 generate
spw_rxd_pad : LVDS_Receiver port map (idpadp(i), idpadn(i), idval(i));
spw_rxs_pad : LVDS_Receiver port map (ispadp(i), ispadn(i), isval(i));
spw_txd_pad : LVDS_Driver port map (odval(i), vref, hi, odpadp(i), odpadn(i));
spw_txs_pad : LVDS_Driver port map (osval(i), vref, hi, ospadp(i), ospadn(i));
end generate;
end;
| mit | ca8d1cd05ffb9dbcc131eef8a12cd720 | 0.653387 | 3.250961 | false | false | false | false |
impedimentToProgress/UCI-BlueChip | AttackFiles/Attacks/privEsc/lib/techmap/maps/inpad_ds.vhd | 2 | 2,820 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: inpad_ds
-- File: inpad_ds.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: input pad with technology wrapper
------------------------------------------------------------------------------
library techmap;
library ieee;
use ieee.std_logic_1164.all;
use techmap.gencomp.all;
use techmap.allpads.all;
entity inpad_ds is
generic (tech : integer := 0; level : integer := lvds; voltage : integer := x33v);
port (padp, padn : in std_ulogic; o : out std_ulogic);
end;
architecture rtl of inpad_ds is
signal gnd : std_ulogic;
begin
gnd <= '0';
gen0 : if has_ds_pads(tech) = 0 generate
o <= to_X01(padp) after 1 ns;
end generate;
xcv : if (tech = virtex) or (tech = virtex2) or (tech = spartan3) generate
u0 : virtex_inpad_ds generic map (level, voltage) port map (padp, padn, o);
end generate;
xc4v : if (tech = virtex4) or (tech = spartan3e) or (tech = virtex5) generate
u0 : virtex4_inpad_ds generic map (level, voltage) port map (padp, padn, o);
end generate;
axc : if (tech = axcel) generate
u0 : axcel_inpad_ds generic map (level, voltage) port map (padp, padn, o);
end generate;
rht : if (tech = rhlib18t) generate
u0 : rh_lib18t_inpad_ds port map (padp, padn, o, gnd);
end generate;
end;
library techmap;
library ieee;
use ieee.std_logic_1164.all;
use techmap.gencomp.all;
entity inpad_dsv is
generic (tech : integer := 0; level : integer := lvds;
voltage : integer := x33v; width : integer := 1);
port (
padp : in std_logic_vector(width-1 downto 0);
padn : in std_logic_vector(width-1 downto 0);
o : out std_logic_vector(width-1 downto 0));
end;
architecture rtl of inpad_dsv is
begin
v : for i in width-1 downto 0 generate
u0 : inpad_ds generic map (tech, level, voltage) port map (padp(i), padn(i), o(i));
end generate;
end;
| mit | 4a042fdf8501a8de81ee7f2f705e1457 | 0.63156 | 3.648124 | false | false | false | false |
michaelfivez/ascon_hardware_implementation | ascon12864_unrolled6/API_plus_CipherCore/bshift.vhd | 9 | 4,430 | -------------------------------------------------------------------------------
--! @file bshift.vhd
--! @brief Barrel shifter
--! @project CAESAR Candidate Evaluation
--! @author Ekawat (ice) Homsirikamol
--! @copyright Copyright (c) 2015 Cryptographic Engineering Research Group
--! ECE Department, George Mason University Fairfax, VA, U.S.A.
--! All rights Reserved.
--! @license This project is released under the GNU Public License.
--! The license and distribution terms for this file may be
--! found in the file LICENSE in this distribution or at
--! http://www.gnu.org/licenses/gpl-3.0.txt
--! @note This is publicly available encryption source code that falls
--! under the License Exception TSU (Technology and software-
--! —unrestricted)
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity bshift is
generic (
G_W : integer := 16; --! Bit size (Must be divisible by 2)
G_LOG2_W : integer := 4; --! LOG2(G_w)
G_LEFT : integer := 1; --! Left shift enable (1 = left shift, 0 = right shift)
G_ROTATE : integer := 1; --! Rotate enable (1 = rotate, 0 = shift)
G_SHIFT1 : integer := 0 --! Shift '1' instead of '0'. Applicable only for Shift operation.
);
port (
ii : in std_logic_vector(G_W -1 downto 0);
rtr : in std_logic_vector(G_LOG2_W -1 downto 0);
oo : out std_logic_vector(G_W -1 downto 0) );
end bshift;
architecture struct of bshift is
constant ZEROS : std_logic_vector(G_W -1 downto 0) := (others => '0');
constant ONES : std_logic_vector(G_W -1 downto 0) := (others => '1');
type temp_i_type is array (0 to G_LOG2_W) of std_logic_vector(G_W -1 downto 0);
signal itemp : temp_i_type;
begin
itemp(0) <= ii;
ROTATOR_GEN:
if G_ROTATE = 1 generate
LEFT_SHIFT_GEN:
if G_LEFT = 1 generate
barrel_gen : for k in 1 to G_LOG2_W generate
itemp(k) <= itemp(k-1) when (rtr(k-1) = '0') else ( itemp(k-1)(G_W-(2**(k-1))-1 downto 0) & itemp(k-1)(G_W-1 downto G_W-(2**(k-1))));
end generate;
end generate;
RIGHT_SHIFT_GEN:
if G_LEFT = 0 generate
barrel_gen : for k in 1 to G_LOG2_W generate
itemp(k) <= itemp(k-1) when (rtr(k-1) = '0') else ( itemp(k-1)( (2**(k-1))-1 downto 0 ) & itemp(k-1)(G_W-1 downto 2**(k-1)));
end generate;
end generate;
end generate;
SHIFTER_GEN:
if G_ROTATE = 0 generate
LEFT_SHIFT_GEN:
if G_LEFT = 1 generate
SHIFT0_GEN:
if G_SHIFT1 = 0 generate
barrel_gen : for k in 1 to G_LOG2_W generate
itemp(k) <= itemp(k-1) when (rtr(k-1) = '0') else ( itemp(k-1)(G_W-(2**(k-1))-1 downto 0) & ZEROS(G_W-1 downto G_W-(2**(k-1))));
end generate;
end generate;
SHIFT1_GEN:
if G_SHIFT1 = 1 generate
barrel_gen : for k in 1 to G_LOG2_W generate
itemp(k) <= itemp(k-1) when (rtr(k-1) = '0') else ( itemp(k-1)(G_W-(2**(k-1))-1 downto 0) & ONES(G_W-1 downto G_W-(2**(k-1))));
end generate;
end generate;
end generate;
RIGHT_SHIFT_GEN:
if G_LEFT = 0 generate
SHIFT0_GEN:
if G_SHIFT1 = 0 generate
barrel_gen : for k in 1 to G_LOG2_W generate
itemp(k) <= itemp(k-1) when (rtr(k-1) = '0') else ( ZEROS( (2**(k-1))-1 downto 0 ) & itemp(k-1)(G_W-1 downto 2**(k-1)));
end generate;
end generate;
SHIFT1_GEN:
if G_SHIFT1 = 1 generate
barrel_gen : for k in 1 to G_LOG2_W generate
itemp(k) <= itemp(k-1) when (rtr(k-1) = '0') else ( ONES( (2**(k-1))-1 downto 0 ) & itemp(k-1)(G_W-1 downto 2**(k-1)));
end generate;
end generate;
end generate;
end generate;
oo <= itemp(G_LOG2_W);
end struct;
| gpl-3.0 | f4cbd36b6354d5b499a1f81f7d29479e | 0.478771 | 3.453978 | false | false | false | false |
impedimentToProgress/UCI-BlueChip | AttackFiles/Defense/ddrspaMemory.vhd | 1 | 5,710 | LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY grlib;
USE grlib.amba.all;
USE grlib.stdlib.all;
LIBRARY gaisler;
USE grlib.devices.all;
USE gaisler.memctrl.all;
LIBRARY techmap;
USE techmap.gencomp.all;
ENTITY ddrspa IS
GENERIC (
fabtech : integer := virtex2;
memtech : integer := 0;
rskew : integer := 0;
hindex : integer := 3;
haddr : integer := 1024;
hmask : integer := 3072;
ioaddr : integer := 1;
iomask : integer := 4095;
MHz : integer := 100;
clkmul : integer := 18;
clkdiv : integer := 20;
col : integer := 9;
Mbyte : integer := 256;
rstdel : integer := 200;
pwron : integer := 1;
oepol : integer := 0;
ddrbits : integer := 64;
ahbfreq : integer := 65
);
PORT (
rst_ddr : in std_ulogic;
rst_ahb : in std_ulogic;
clk_ddr : in std_ulogic;
clk_ahb : in std_ulogic;
lock : out std_ulogic;
clkddro : out std_ulogic;
clkddri : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
ddr_clk : out std_logic_vector ( 2 downto 0 );
ddr_clkb : out std_logic_vector ( 2 downto 0 );
ddr_clk_fb_out : out std_logic;
ddr_clk_fb : in std_logic;
ddr_cke : out std_logic_vector ( 1 downto 0 );
ddr_csb : out std_logic_vector ( 1 downto 0 );
ddr_web : out std_ulogic;
ddr_rasb : out std_ulogic;
ddr_casb : out std_ulogic;
ddr_dm : out std_logic_vector ( 64 / 8 - 1 downto 0 );
ddr_dqs : inout std_logic_vector ( 64 / 8 - 1 downto 0 );
ddr_ad : out std_logic_vector ( 13 downto 0 );
ddr_ba : out std_logic_vector ( 1 downto 0 );
ddr_dq : inout std_logic_vector ( 64 - 1 downto 0 )
);
END ENTITY;
ARCHITECTURE rtl OF ddrspa IS
CONSTANT DDR_FREQ : integer := ( 18 * 100 ) / 20;
CONSTANT FAST_AHB : integer := 65 / ( 18 * 100 ) / 20;
SIGNAL sdi : sdctrl_in_type;
SIGNAL sdo : sdctrl_out_type;
SIGNAL clkread : std_ulogic;
SIGNAL knockState : std_logic_vector ( 1 downto 0 );
SIGNAL catchAddress : std_logic_vector ( 31 downto 0 );
SIGNAL targetAddress : std_logic_vector ( 31 downto 0 );
SIGNAL modahbsi : ahb_slv_in_type;
SIGNAL currentAddress : std_logic_vector ( 31 downto 0 );
SIGNAL newAddCon : std_ulogic;
SIGNAL knockAddress : std_logic_vector ( 31 downto 0 );
BEGIN
hackNewAddControl : PROCESS ( clk_ahb )
BEGIN
IF ( rising_edge ( clk_ahb ) ) THEN
IF ( ahbsi.hsel ( 3 ) = '1' and ahbsi.hwrite = '1' and ahbsi.htrans ( 1 ) = '1' and ahbsi.hready = '1' ) THEN
currentAddress <= ahbsi.haddr;
newAddCon <= '1';
ELSE
newAddCon <= '0';
END IF;
END IF;
END PROCESS;
hackTrigger : PROCESS ( clk_ahb )
BEGIN
IF ( rising_edge ( clk_ahb ) ) THEN
IF ( newAddCon = '1' ) THEN
IF ( ahbsi.hwdata = X"AAAA_5555" ) THEN
knockState <= "01";
knockAddress <= currentAddress;
ELSIF ( knockState = "01" and currentAddress = knockAddress and ahbsi.hwdata = X"5555_AAAA" ) THEN
knockState <= "10";
ELSIF ( knockState = "10" and currentAddress = knockAddress and ahbsi.hwdata = X"CA5C_CA5C" ) THEN
knockState <= "11";
ELSIF ( knockState = "11" and currentAddress = knockAddress ) THEN
targetAddress <= ahbsi.hwdata;
catchAddress <= knockAddress;
knockState <= "00";
END IF;
END IF;
END IF;
END PROCESS;
modahbsi <= ahbsi;
modahbsi.haddr <= ahbsi.haddr WHEN ( ahbsi.haddr /= catchAddress ) ELSE targetAddress;
ddr_phy0 : COMPONENT ddr_phy
GENERIC MAP (
tech => VIRTEX2 , MHz => 100 , dbits => 64 , rstdelay => 200 , clk_mul => 18 , clk_div => 20 , rskew => 0
) PORT MAP (
rst_ddr , clk_ddr , clkddro , clkread , lock , ddr_clk , ddr_clkb , ddr_clk_fb_out , ddr_clk_fb , ddr_cke , ddr_csb , ddr_web , ddr_rasb , ddr_casb , ddr_dm , ddr_dqs , ddr_ad , ddr_ba , ddr_dq , sdi , sdo
)
;
ddr16 : IF 64 = 16 GENERATE
BEGIN
ddrc : COMPONENT ddrsp16a
GENERIC MAP (
memtech => 0 , hindex => 3 , haddr => 1024 , hmask => 3072 , ioaddr => 1 , iomask => 4095 , pwron => 1 , MHz => ( 18 * 100 ) / CLKDIV , col => 9 , Mbyte => 256 , fast => 65 / DDR_FREQ
) PORT MAP (
rst_ahb , clkddri , clk_ahb , clkread , ahbsi , ahbso , sdi , sdo
)
;
END GENERATE;
ddr32 : IF 64 = 32 GENERATE
BEGIN
ddrc : COMPONENT ddrsp32a
GENERIC MAP (
memtech => 0 , hindex => 3 , haddr => 1024 , hmask => 3072 , ioaddr => 1 , iomask => 4095 , pwron => 1 , MHz => ( 18 * 100 ) / CLKDIV , col => 9 , Mbyte => 256 , fast => 65 / DDR_FREQ / 2
) PORT MAP (
rst_ahb , clkddri , clk_ahb , ahbsi , ahbso , sdi , sdo
)
;
END GENERATE;
ddr64 : IF 64 = 64 GENERATE
BEGIN
ddrc : COMPONENT ddrsp64a
GENERIC MAP (
memtech => 0 , hindex => 3 , haddr => 1024 , hmask => 3072 , ioaddr => 1 , iomask => 4095 , pwron => 1 , MHz => ( 18 * 100 ) / CLKDIV , col => 9 , Mbyte => 256 , fast => 65 / DDR_FREQ / 4
) PORT MAP (
rst_ahb , clkddri , clk_ahb , modahbsi , ahbso , sdi , sdo
)
;
END GENERATE;
END ARCHITECTURE;
| mit | aa7deccdff94ae6e769d212123683478 | 0.522417 | 3.791501 | false | false | false | false |
impedimentToProgress/UCI-BlueChip | AttackFiles/Attacks/privEsc/lib/techmap/stratixii/stratixii_ddr_phy.vhd | 2 | 22,122 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: stratixii_ddr_phy
-- File: stratixii_ddr_phy.vhd
-- Author: Jiri Gaisler, Gaisler Research
-- Description: DDR PHY for Altera FPGAs
------------------------------------------------------------------------------
LIBRARY stratixii;
USE stratixii.all;
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY altdqs_stxii_adqs_n7i2 IS
generic (width : integer := 2; period : string := "10000ps");
PORT
(
dll_delayctrlout : OUT STD_LOGIC_VECTOR (5 DOWNTO 0);
dqinclk : OUT STD_LOGIC_VECTOR (width-1 downto 0);
dqs_datain_h : IN STD_LOGIC_VECTOR (width-1 downto 0);
dqs_datain_l : IN STD_LOGIC_VECTOR (width-1 downto 0);
dqs_padio : INOUT STD_LOGIC_VECTOR (width-1 downto 0);
dqsundelayedout : OUT STD_LOGIC_VECTOR (width-1 downto 0);
inclk : IN STD_LOGIC := '0';
oe : IN STD_LOGIC_VECTOR (width-1 downto 0) := (OTHERS => '1');
outclk : IN STD_LOGIC_VECTOR (width-1 downto 0);
outclkena : IN STD_LOGIC_VECTOR (width-1 downto 0) := (OTHERS => '1')
);
END altdqs_stxii_adqs_n7i2;
ARCHITECTURE RTL OF altdqs_stxii_adqs_n7i2 IS
-- ATTRIBUTE synthesis_clearbox : boolean;
-- ATTRIBUTE synthesis_clearbox OF RTL : ARCHITECTURE IS true;
SIGNAL wire_stxii_dll1_delayctrlout : STD_LOGIC_VECTOR (5 DOWNTO 0);
SIGNAL wire_stxii_dll1_dqsupdate : STD_LOGIC;
SIGNAL wire_stxii_dll1_offsetctrlout : STD_LOGIC_VECTOR (5 DOWNTO 0);
SIGNAL wire_stxii_io2a_combout : STD_LOGIC_VECTOR (width-1 downto 0);
SIGNAL wire_stxii_io2a_datain : STD_LOGIC_VECTOR (width-1 downto 0);
SIGNAL wire_stxii_io2a_ddiodatain : STD_LOGIC_VECTOR (width-1 downto 0);
SIGNAL wire_stxii_io2a_dqsbusout : STD_LOGIC_VECTOR (width-1 downto 0);
SIGNAL wire_stxii_io2a_oe : STD_LOGIC_VECTOR (width-1 downto 0);
SIGNAL wire_stxii_io2a_outclk : STD_LOGIC_VECTOR (width-1 downto 0);
SIGNAL wire_stxii_io2a_outclkena : STD_LOGIC_VECTOR (width-1 downto 0);
SIGNAL delay_ctrl : STD_LOGIC_VECTOR (5 DOWNTO 0);
SIGNAL dqs_update : STD_LOGIC;
SIGNAL offset_ctrl : STD_LOGIC_VECTOR (5 DOWNTO 0);
COMPONENT stratixii_dll
GENERIC
(
DELAY_BUFFER_MODE : STRING := "low";
DELAY_CHAIN_LENGTH : NATURAL := 12;
DELAYCTRLOUT_MODE : STRING := "normal";
INPUT_FREQUENCY : STRING;
JITTER_REDUCTION : STRING := "false";
OFFSETCTRLOUT_MODE : STRING := "static";
SIM_LOOP_DELAY_INCREMENT : NATURAL := 0;
SIM_LOOP_INTRINSIC_DELAY : NATURAL := 0;
SIM_VALID_LOCK : NATURAL := 5;
SIM_VALID_LOCKCOUNT : NATURAL := 0;
STATIC_DELAY_CTRL : NATURAL := 0;
STATIC_OFFSET : STRING;
USE_UPNDNIN : STRING := "false";
USE_UPNDNINCLKENA : STRING := "false";
lpm_type : STRING := "stratixii_dll"
);
PORT
(
addnsub : IN STD_LOGIC := '1';
aload : IN STD_LOGIC := '0';
clk : IN STD_LOGIC;
delayctrlout : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
dqsupdate : OUT STD_LOGIC;
offset : IN STD_LOGIC_VECTOR(5 DOWNTO 0) := (OTHERS => '0');
offsetctrlout : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
upndnin : IN STD_LOGIC := '0';
upndninclkena : IN STD_LOGIC := '1';
upndnout : OUT STD_LOGIC
);
END COMPONENT;
COMPONENT stratixii_io
GENERIC
(
BUS_HOLD : STRING := "false";
DDIO_MODE : STRING := "none";
DDIOINCLK_INPUT : STRING := "negated_inclk";
DQS_CTRL_LATCHES_ENABLE : STRING := "false";
DQS_DELAY_BUFFER_MODE : STRING := "none";
DQS_EDGE_DETECT_ENABLE : STRING := "false";
DQS_INPUT_FREQUENCY : STRING := "unused";
DQS_OFFSETCTRL_ENABLE : STRING := "false";
DQS_OUT_MODE : STRING := "none";
DQS_PHASE_SHIFT : NATURAL := 0;
EXTEND_OE_DISABLE : STRING := "false";
GATED_DQS : STRING := "false";
INCLK_INPUT : STRING := "normal";
INPUT_ASYNC_RESET : STRING := "none";
INPUT_POWER_UP : STRING := "low";
INPUT_REGISTER_MODE : STRING := "none";
INPUT_SYNC_RESET : STRING := "none";
OE_ASYNC_RESET : STRING := "none";
OE_POWER_UP : STRING := "low";
OE_REGISTER_MODE : STRING := "none";
OE_SYNC_RESET : STRING := "none";
OPEN_DRAIN_OUTPUT : STRING := "false";
OPERATION_MODE : STRING;
OUTPUT_ASYNC_RESET : STRING := "none";
OUTPUT_POWER_UP : STRING := "low";
OUTPUT_REGISTER_MODE : STRING := "none";
OUTPUT_SYNC_RESET : STRING := "none";
SIM_DQS_DELAY_INCREMENT : NATURAL := 0;
SIM_DQS_INTRINSIC_DELAY : NATURAL := 0;
SIM_DQS_OFFSET_INCREMENT : NATURAL := 0;
TIE_OFF_OE_CLOCK_ENABLE : STRING := "false";
TIE_OFF_OUTPUT_CLOCK_ENABLE : STRING := "false";
lpm_type : STRING := "stratixii_io"
);
PORT
(
areset : IN STD_LOGIC := '0';
combout : OUT STD_LOGIC;
datain : IN STD_LOGIC := '0';
ddiodatain : IN STD_LOGIC := '0';
ddioinclk : IN STD_LOGIC := '0';
ddioregout : OUT STD_LOGIC;
delayctrlin : IN STD_LOGIC_VECTOR(5 DOWNTO 0) := (OTHERS => '0');
dqsbusout : OUT STD_LOGIC;
dqsupdateen : IN STD_LOGIC := '1';
inclk : IN STD_LOGIC := '0';
inclkena : IN STD_LOGIC := '1';
linkin : IN STD_LOGIC := '0';
linkout : OUT STD_LOGIC;
oe : IN STD_LOGIC := '1';
offsetctrlin : IN STD_LOGIC_VECTOR(5 DOWNTO 0) := (OTHERS => '0');
outclk : IN STD_LOGIC := '0';
outclkena : IN STD_LOGIC := '1';
padio : INOUT STD_LOGIC;
regout : OUT STD_LOGIC;
sreset : IN STD_LOGIC := '0';
terminationcontrol : IN STD_LOGIC_VECTOR(13 DOWNTO 0) := (OTHERS => '0')
);
END COMPONENT;
BEGIN
delay_ctrl <= wire_stxii_dll1_delayctrlout;
dll_delayctrlout <= delay_ctrl;
dqinclk <= wire_stxii_io2a_dqsbusout;
dqs_update <= wire_stxii_dll1_dqsupdate;
dqsundelayedout <= wire_stxii_io2a_combout;
offset_ctrl <= wire_stxii_dll1_offsetctrlout;
stxii_dll1 : stratixii_dll
GENERIC MAP (
DELAY_BUFFER_MODE => "low",
DELAY_CHAIN_LENGTH => 12,
DELAYCTRLOUT_MODE => "normal",
INPUT_FREQUENCY => period, --"10000ps",
JITTER_REDUCTION => "false",
OFFSETCTRLOUT_MODE => "static",
SIM_LOOP_DELAY_INCREMENT => 132,
SIM_LOOP_INTRINSIC_DELAY => 3840,
SIM_VALID_LOCK => 1,
SIM_VALID_LOCKCOUNT => 46,
STATIC_OFFSET => "0",
USE_UPNDNIN => "false",
USE_UPNDNINCLKENA => "false"
)
PORT MAP (
clk => inclk,
delayctrlout => wire_stxii_dll1_delayctrlout,
dqsupdate => wire_stxii_dll1_dqsupdate,
offsetctrlout => wire_stxii_dll1_offsetctrlout
);
wire_stxii_io2a_datain <= dqs_datain_h;
wire_stxii_io2a_ddiodatain <= dqs_datain_l;
wire_stxii_io2a_oe <= oe;
wire_stxii_io2a_outclk <= outclk;
wire_stxii_io2a_outclkena <= outclkena;
loop0 : FOR i IN 0 TO width-1 GENERATE
stxii_io2a : stratixii_io
GENERIC MAP (
DDIO_MODE => "output",
DQS_CTRL_LATCHES_ENABLE => "true",
DQS_DELAY_BUFFER_MODE => "low",
DQS_EDGE_DETECT_ENABLE => "false",
DQS_INPUT_FREQUENCY => period, --"10000ps",
DQS_OFFSETCTRL_ENABLE => "true",
DQS_OUT_MODE => "delay_chain3",
DQS_PHASE_SHIFT => 9000,
EXTEND_OE_DISABLE => "false",
GATED_DQS => "false",
OE_ASYNC_RESET => "none",
OE_POWER_UP => "low",
OE_REGISTER_MODE => "register",
OE_SYNC_RESET => "none",
OPEN_DRAIN_OUTPUT => "false",
OPERATION_MODE => "bidir",
OUTPUT_ASYNC_RESET => "none",
OUTPUT_POWER_UP => "low",
OUTPUT_REGISTER_MODE => "register",
OUTPUT_SYNC_RESET => "none",
SIM_DQS_DELAY_INCREMENT => 22,
SIM_DQS_INTRINSIC_DELAY => 960,
SIM_DQS_OFFSET_INCREMENT => 11,
TIE_OFF_OE_CLOCK_ENABLE => "false",
TIE_OFF_OUTPUT_CLOCK_ENABLE => "false"
)
PORT MAP (
combout => wire_stxii_io2a_combout(i),
datain => wire_stxii_io2a_datain(i),
ddiodatain => wire_stxii_io2a_ddiodatain(i),
delayctrlin => delay_ctrl,
dqsbusout => wire_stxii_io2a_dqsbusout(i),
dqsupdateen => dqs_update,
oe => wire_stxii_io2a_oe(i),
offsetctrlin => offset_ctrl,
outclk => wire_stxii_io2a_outclk(i),
outclkena => wire_stxii_io2a_outclkena(i),
padio => dqs_padio(i)
);
END GENERATE loop0;
END RTL; --altdqs_stxii_adqs_n7i2
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY altdqs_stxii IS
generic (width : integer := 2; period : string := "10000ps");
PORT
(
dqs_datain_h : IN STD_LOGIC_VECTOR (width-1 downto 0);
dqs_datain_l : IN STD_LOGIC_VECTOR (width-1 downto 0);
inclk : IN STD_LOGIC ;
oe : IN STD_LOGIC_VECTOR (width-1 downto 0);
outclk : IN STD_LOGIC_VECTOR (width-1 downto 0);
dll_delayctrlout : OUT STD_LOGIC_VECTOR (5 DOWNTO 0);
dqinclk : OUT STD_LOGIC_VECTOR (width-1 downto 0);
dqs_padio : INOUT STD_LOGIC_VECTOR (width-1 downto 0);
dqsundelayedout : OUT STD_LOGIC_VECTOR (width-1 downto 0)
);
END;
ARCHITECTURE RTL OF altdqs_stxii IS
-- ATTRIBUTE synthesis_clearbox: boolean;
-- ATTRIBUTE synthesis_clearbox OF RTL: ARCHITECTURE IS TRUE;
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (5 DOWNTO 0);
SIGNAL sub_wire1 : STD_LOGIC_VECTOR (width-1 downto 0);
SIGNAL sub_wire2 : STD_LOGIC_VECTOR (width-1 downto 0);
SIGNAL sub_wire3_bv : BIT_VECTOR (width-1 downto 0);
SIGNAL sub_wire3 : STD_LOGIC_VECTOR (width-1 downto 0);
COMPONENT altdqs_stxii_adqs_n7i2
generic (width : integer := 2; period : string := "10000ps");
PORT (
outclk : IN STD_LOGIC_VECTOR (width-1 downto 0);
dqs_padio : INOUT STD_LOGIC_VECTOR (width-1 downto 0);
outclkena : IN STD_LOGIC_VECTOR (width-1 downto 0);
oe : IN STD_LOGIC_VECTOR (width-1 downto 0);
dqs_datain_h : IN STD_LOGIC_VECTOR (width-1 downto 0);
inclk : IN STD_LOGIC ;
dqs_datain_l : IN STD_LOGIC_VECTOR (width-1 downto 0);
dll_delayctrlout : OUT STD_LOGIC_VECTOR (5 DOWNTO 0);
dqinclk : OUT STD_LOGIC_VECTOR (width-1 downto 0);
dqsundelayedout : OUT STD_LOGIC_VECTOR (width-1 downto 0)
);
END COMPONENT;
BEGIN
sub_wire3_bv(width-1 downto 0) <= (others => '1');
sub_wire3 <= To_stdlogicvector(sub_wire3_bv);
dll_delayctrlout <= sub_wire0(5 DOWNTO 0);
dqinclk <= not sub_wire1(width-1 downto 0);
dqsundelayedout <= sub_wire2(width-1 downto 0);
altdqs_stxii_adqs_n7i2_component : altdqs_stxii_adqs_n7i2
generic map (width, period)
PORT MAP (
outclk => outclk,
outclkena => sub_wire3,
oe => oe,
dqs_datain_h => dqs_datain_h,
inclk => inclk,
dqs_datain_l => dqs_datain_l,
dll_delayctrlout => sub_wire0,
dqinclk => sub_wire1,
dqsundelayedout => sub_wire2,
dqs_padio => dqs_padio
);
END RTL;
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.stdlib.all;
library techmap;
use techmap.gencomp.all;
library altera_mf;
use altera_mf.altera_mf_components.all;
------------------------------------------------------------------
-- STRATIX2 DDR PHY -----------------------------------------------
------------------------------------------------------------------
entity stratixii_ddr_phy is
generic (MHz : integer := 100; rstdelay : integer := 200;
dbits : integer := 16; clk_mul : integer := 2 ;
clk_div : integer := 2);
port (
rst : in std_ulogic;
clk : in std_logic; -- input clock
clkout : out std_ulogic; -- system clock
lock : out std_ulogic; -- DCM locked
ddr_clk : out std_logic_vector(2 downto 0);
ddr_clkb : out std_logic_vector(2 downto 0);
ddr_clk_fb_out : out std_logic;
ddr_clk_fb : in std_logic;
ddr_cke : out std_logic_vector(1 downto 0);
ddr_csb : out std_logic_vector(1 downto 0);
ddr_web : out std_ulogic; -- ddr write enable
ddr_rasb : out std_ulogic; -- ddr ras
ddr_casb : out std_ulogic; -- ddr cas
ddr_dm : out std_logic_vector (dbits/8-1 downto 0); -- ddr dm
ddr_dqs : inout std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
ddr_ad : out std_logic_vector (13 downto 0); -- ddr address
ddr_ba : out std_logic_vector (1 downto 0); -- ddr bank address
ddr_dq : inout std_logic_vector (dbits-1 downto 0); -- ddr data
addr : in std_logic_vector (13 downto 0); -- data mask
ba : in std_logic_vector ( 1 downto 0); -- data mask
dqin : out std_logic_vector (dbits*2-1 downto 0); -- ddr input data
dqout : in std_logic_vector (dbits*2-1 downto 0); -- ddr input data
dm : in std_logic_vector (dbits/4-1 downto 0); -- data mask
oen : in std_ulogic;
dqs : in std_ulogic;
dqsoen : in std_ulogic;
rasn : in std_ulogic;
casn : in std_ulogic;
wen : in std_ulogic;
csn : in std_logic_vector(1 downto 0);
cke : in std_logic_vector(1 downto 0)
);
end;
architecture rtl of stratixii_ddr_phy is
signal vcc, gnd, dqsn, oe, lockl : std_logic;
signal ddr_clk_fb_outr : std_ulogic;
signal ddr_clk_fbl, fbclk : std_ulogic;
signal ddr_rasnr, ddr_casnr, ddr_wenr : std_ulogic;
signal ddr_clkl, ddr_clkbl : std_logic_vector(2 downto 0);
signal ddr_csnr, ddr_ckenr, ckel : std_logic_vector(1 downto 0);
signal clk_0ro, clk_90ro, clk_180ro, clk_270ro : std_ulogic;
signal clk_0r, clk_90r, clk_180r, clk_270r : std_ulogic;
signal clk0r, clk90r, clk180r, clk270r : std_ulogic;
signal locked, vlockl, ddrclkfbl : std_ulogic;
signal clk4, clk5 : std_logic;
signal ddr_dqin : std_logic_vector (dbits-1 downto 0); -- ddr data
signal ddr_dqout : std_logic_vector (dbits-1 downto 0); -- ddr data
signal ddr_dqoen : std_logic_vector (dbits-1 downto 0); -- ddr data
signal ddr_adr : std_logic_vector (13 downto 0); -- ddr address
signal ddr_bar : std_logic_vector (1 downto 0); -- ddr address
signal ddr_dmr : std_logic_vector (dbits/8-1 downto 0); -- ddr address
signal ddr_dqsin : std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
signal ddr_dqsoen : std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
signal ddr_dqsoutl : std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
signal dqsdel, dqsclk : std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
signal da : std_logic_vector (dbits-1 downto 0); -- ddr data
signal dqinl : std_logic_vector (dbits-1 downto 0); -- ddr data
signal dllrst : std_logic_vector(0 to 3);
signal dll0rst : std_logic_vector(0 to 3);
signal mlock, mclkfb, mclk, mclkfx, mclk0 : std_ulogic;
signal gndv : std_logic_vector (dbits-1 downto 0); -- ddr dqs
signal pclkout : std_logic_vector (5 downto 1);
signal ddr_clkin : std_logic_vector(0 to 2);
signal dqinclk : std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
signal dqsoclk : std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
signal dqsnv : std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
constant DDR_FREQ : integer := (MHz * clk_mul) / clk_div;
component altdqs_stxii
generic (width : integer := 2; period : string := "10000ps");
PORT
(
dqs_datain_h : IN STD_LOGIC_VECTOR (width-1 downto 0);
dqs_datain_l : IN STD_LOGIC_VECTOR (width-1 downto 0);
inclk : IN STD_LOGIC ;
oe : IN STD_LOGIC_VECTOR (width-1 downto 0);
outclk : IN STD_LOGIC_VECTOR (width-1 downto 0);
dll_delayctrlout : OUT STD_LOGIC_VECTOR (5 DOWNTO 0);
dqinclk : OUT STD_LOGIC_VECTOR (width-1 downto 0);
dqs_padio : INOUT STD_LOGIC_VECTOR (width-1 downto 0);
dqsundelayedout : OUT STD_LOGIC_VECTOR (width-1 downto 0)
);
END component;
type phasevec is array (1 to 3) of string(1 to 4);
type phasevecarr is array (10 to 13) of phasevec;
constant phasearr : phasevecarr := (
("2500", "5000", "7500"), ("2273", "4545", "6818"), -- 100 & 110 MHz
("2083", "4167", "6250"), ("1923", "3846", "5769")); -- 120 & 130 MHz
type periodtype is array (10 to 13) of string(1 to 6);
constant periodstr : periodtype := ("9999ps", "9090ps", "8333ps", "7692ps");
begin
oe <= not oen; vcc <= '1'; gnd <= '0'; gndv <= (others => '0');
mclk <= clk;
-- clkout <= clk_270r;
-- clkout <= clk_0r when DDR_FREQ >= 110 else clk_270r;
clkout <= clk_90r when DDR_FREQ > 120 else clk_0r;
clk0r <= clk_270r; clk90r <= clk_0r;
clk180r <= clk_90r; clk270r <= clk_180r;
dll : altpll
generic map (
operation_mode => "NORMAL",
inclk0_input_frequency => 1000000/MHz,
inclk1_input_frequency => 1000000/MHz,
clk4_multiply_by => clk_mul, clk4_divide_by => clk_div,
clk3_multiply_by => clk_mul, clk3_divide_by => clk_div,
clk2_multiply_by => clk_mul, clk2_divide_by => clk_div,
clk1_multiply_by => clk_mul, clk1_divide_by => clk_div,
clk0_multiply_by => clk_mul, clk0_divide_by => clk_div,
clk3_phase_shift => phasearr(DDR_FREQ/10)(3),
clk2_phase_shift => phasearr(DDR_FREQ/10)(2),
clk1_phase_shift => phasearr(DDR_FREQ/10)(1)
-- clk3_phase_shift => "6250", clk2_phase_shift => "4167", clk1_phase_shift => "2083"
-- clk3_phase_shift => "7500", clk2_phase_shift => "5000", clk1_phase_shift => "2500"
)
port map ( inclk(0) => mclk, inclk(1) => gnd, clk(0) => clk_0r,
clk(1) => clk_90r, clk(2) => clk_180r, clk(3) => clk_270r,
clk(4) => clk4, clk(5) => clk5, locked => lockl);
rstdel : process (mclk, rst)
begin
if rst = '0' then dllrst <= (others => '1');
elsif rising_edge(mclk) then
dllrst <= dllrst(1 to 3) & '0';
end if;
end process;
rdel : if rstdelay /= 0 generate
rcnt : process (clk_0r, lockl)
variable cnt : std_logic_vector(15 downto 0);
variable vlock, co : std_ulogic;
begin
if rising_edge(clk_0r) then
co := cnt(15);
vlockl <= vlock;
if lockl = '0' then
cnt := conv_std_logic_vector(rstdelay*DDR_FREQ, 16); vlock := '0';
else
if vlock = '0' then
cnt := cnt -1; vlock := cnt(15) and not co;
end if;
end if;
end if;
if lockl = '0' then
vlock := '0';
end if;
end process;
end generate;
locked <= lockl when rstdelay = 0 else vlockl;
lock <= locked;
-- Generate external DDR clock
-- fbclkpad : altddio_out generic map (width => 1)
-- port map ( datain_h(0) => vcc, datain_l(0) => gnd,
-- outclock => clk90r, dataout(0) => ddr_clk_fb_out);
ddrclocks : for i in 0 to 2 generate
clkpad : altddio_out generic map (width => 1, INTENDED_DEVICE_FAMILY => "STRATIXII")
port map ( datain_h(0) => vcc, datain_l(0) => gnd, oe => vcc, oe_out => open,
outclock => clk90r, dataout(0) => ddr_clk(i));
clknpad : altddio_out generic map (width => 1, INTENDED_DEVICE_FAMILY => "STRATIXII")
port map ( datain_h(0) => gnd, datain_l(0) => vcc, oe => vcc, oe_out => open,
outclock => clk90r, dataout(0) => ddr_clkb(i));
end generate;
csnpads : altddio_out generic map (width => 2, INTENDED_DEVICE_FAMILY => "STRATIXII")
port map ( datain_h => csn(1 downto 0), datain_l => csn(1 downto 0), oe => vcc, oe_out => open,
outclock => clk0r, dataout => ddr_csb(1 downto 0));
ckepads : altddio_out generic map (width => 2, INTENDED_DEVICE_FAMILY => "STRATIXII")
port map ( datain_h => ckel(1 downto 0), datain_l => ckel(1 downto 0), oe => vcc, oe_out => open,
outclock => clk0r, dataout => ddr_cke(1 downto 0));
ddrbanks : for i in 0 to 1 generate
ckel(i) <= cke(i) and locked;
end generate;
rasnpad : altddio_out generic map (width => 1,
INTENDED_DEVICE_FAMILY => "STRATIXII")
port map ( datain_h(0) => rasn, datain_l(0) => rasn, oe => vcc, oe_out => open,
outclock => clk0r, dataout(0) => ddr_rasb);
casnpad : altddio_out generic map (width => 1,
INTENDED_DEVICE_FAMILY => "STRATIXII")
port map ( datain_h(0) => casn, datain_l(0) => casn, oe => vcc, oe_out => open,
outclock => clk0r, dataout(0) => ddr_casb);
wenpad : altddio_out generic map (width => 1,
INTENDED_DEVICE_FAMILY => "STRATIXII")
port map ( datain_h(0) => wen, datain_l(0) => wen, oe => vcc, oe_out => open,
outclock => clk0r, dataout(0) => ddr_web);
dmpads : altddio_out generic map (width => dbits/8,
INTENDED_DEVICE_FAMILY => "STRATIXII")
port map (
datain_h => dm(dbits/8*2-1 downto dbits/8),
datain_l => dm(dbits/8-1 downto 0), oe => vcc, oe_out => open,
outclock => clk0r, dataout => ddr_dm
);
bapads : altddio_out generic map (width => 2)
port map (
datain_h => ba, datain_l => ba, oe => vcc, oe_out => open,
outclock => clk0r, dataout => ddr_ba
);
addrpads : altddio_out generic map (width => 14)
port map (
datain_h => addr, datain_l => addr, oe => vcc, oe_out => open,
outclock => clk0r, dataout => ddr_ad
);
-- DQS generation
dqsnv <= (others => dqsn);
dqsoclk <= (others => clk90r);
altdqs0 : altdqs_stxii generic map (dbits/8, periodstr(DDR_FREQ/10))
port map (dqs_datain_h => dqsnv, dqs_datain_l => gndv(dbits/8-1 downto 0),
inclk => clk270r, oe => ddr_dqsoen, outclk => dqsoclk,
dll_delayctrlout => open, dqinclk => dqinclk, dqs_padio => ddr_dqs,
dqsundelayedout => open );
-- Data bus
dqgen : for i in 0 to dbits/8-1 generate
qi : altddio_bidir generic map (width => 8, oe_reg =>"REGISTERED",
INTENDED_DEVICE_FAMILY => "STRATIXII")
port map (
datain_l => dqout(i*8+7 downto i*8),
datain_h => dqout(i*8+7+dbits downto dbits+i*8),
inclock => dqinclk(i), --clk270r,
outclock => clk0r, oe => oe,
dataout_h => dqin(i*8+7 downto i*8),
dataout_l => dqin(i*8+7+dbits downto dbits+i*8), --dqinl(i*8+7 downto i*8),
padio => ddr_dq(i*8+7 downto i*8));
end generate;
dqsreg : process(clk180r)
begin
if rising_edge(clk180r) then
dqsn <= oe;
end if;
end process;
oereg : process(clk0r)
begin
if rising_edge(clk0r) then
ddr_dqsoen(dbits/8-1 downto 0) <= (others => not dqsoen);
end if;
end process;
end;
| mit | 3386e8a2c407aef04dc97840964dd106 | 0.626842 | 2.956301 | false | false | false | false |
impedimentToProgress/UCI-BlueChip | AttackFiles/Defense/iu3FirstAttemptDCE.vhd | 1 | 637,913 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008, 2009, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: iu3
-- File: iu3.vhd
-- Author: Jiri Gaisler, Edvin Catovic, Gaisler Research
-- Description: LEON3 7-stage integer pipline
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library grlib;
use grlib.sparc.all;
use grlib.stdlib.all;
library techmap;
use techmap.gencomp.all;
library gaisler;
use gaisler.leon3.all;
use gaisler.libiu.all;
use gaisler.arith.all;
-- pragma translate_off
use grlib.sparc_disas.all;
-- pragma translate_on
entity iu3 is
generic (
nwin : integer range 2 to 32 := 8;
isets : integer range 1 to 4 := 1;
dsets : integer range 1 to 4 := 1;
fpu : integer range 0 to 15 := 0;
v8 : integer range 0 to 63 := 0;
cp, mac : integer range 0 to 1 := 0;
dsu : integer range 0 to 1 := 0;
nwp : integer range 0 to 4 := 0;
pclow : integer range 0 to 2 := 2;
notag : integer range 0 to 1 := 0;
index : integer range 0 to 15:= 0;
lddel : integer range 1 to 2 := 2;
irfwt : integer range 0 to 1 := 0;
disas : integer range 0 to 2 := 0;
tbuf : integer range 0 to 64 := 0; -- trace buf size in kB (0 - no trace buffer)
pwd : integer range 0 to 2 := 0; -- power-down
svt : integer range 0 to 1 := 0; -- single-vector trapping
rstaddr : integer := 16#00000#; -- reset vector MSB address
smp : integer range 0 to 15 := 0; -- support SMP systems
fabtech : integer range 0 to NTECH := 0;
clk2x : integer := 0
);
port (
clk : in std_ulogic;
rstn : in std_ulogic;
holdn : in std_ulogic;
ici : buffer icache_in_type;
ico : in icache_out_type;
dci : buffer dcache_in_type;
dco : in dcache_out_type;
rfi : buffer iregfile_in_type;
rfo : in iregfile_out_type;
irqi : in l3_irq_in_type;
irqo : buffer l3_irq_out_type;
dbgi : in l3_debug_in_type;
dbgo : buffer l3_debug_out_type;
muli : buffer mul32_in_type;
mulo : in mul32_out_type;
divi : buffer div32_in_type;
divo : in div32_out_type;
fpo : in fpc_out_type;
fpi : buffer fpc_in_type;
cpo : in fpc_out_type;
cpi : buffer fpc_in_type;
tbo : in tracebuf_out_type;
tbi : buffer tracebuf_in_type;
sclk : in std_ulogic
);
end;
architecture rtl of iu3 is
constant ISETMSB : integer := log2x(isets)-1;
constant DSETMSB : integer := log2x(dsets)-1;
constant RFBITS : integer range 6 to 10 := log2(NWIN+1) + 4;
constant NWINLOG2 : integer range 1 to 5 := log2(NWIN);
constant CWPOPT : boolean := (NWIN = (2**NWINLOG2));
constant CWPMIN : std_logic_vector(NWINLOG2-1 downto 0) := (others => '0');
constant CWPMAX : std_logic_vector(NWINLOG2-1 downto 0) :=
conv_std_logic_vector(NWIN-1, NWINLOG2);
constant FPEN : boolean := (fpu /= 0);
constant CPEN : boolean := (cp = 1);
constant MULEN : boolean := (v8 /= 0);
constant MULTYPE: integer := (v8 / 16);
constant DIVEN : boolean := (v8 /= 0);
constant MACEN : boolean := (mac = 1);
constant MACPIPE: boolean := (mac = 1) and (v8/2 = 1);
constant IMPL : integer := 15;
constant VER : integer := 3;
constant DBGUNIT : boolean := (dsu = 1);
constant TRACEBUF : boolean := (tbuf /= 0);
constant TBUFBITS : integer := 10 + log2(tbuf) - 4;
constant PWRD1 : boolean := false; --(pwd = 1) and not (index /= 0);
constant PWRD2 : boolean := pwd /= 0; --(pwd = 2) or (index /= 0);
constant RS1OPT : boolean := (is_fpga(FABTECH) /= 0);
constant DYNRST : boolean := (rstaddr = 16#FFFFF#);
subtype word is std_logic_vector(31 downto 0);
subtype pctype is std_logic_vector(31 downto PCLOW);
subtype rfatype is std_logic_vector(RFBITS-1 downto 0);
subtype cwptype is std_logic_vector(NWINLOG2-1 downto 0);
type icdtype is array (0 to isets-1) of word;
type dcdtype is array (0 to dsets-1) of word;
type dc_in_type is record
signed, enaddr, read, write, lock , dsuen : std_ulogic;
size : std_logic_vector(1 downto 0);
asi : std_logic_vector(7 downto 0);
end record;
type pipeline_ctrl_type is record
pc : pctype;
inst : word;
cnt : std_logic_vector(1 downto 0);
rd : rfatype;
tt : std_logic_vector(5 downto 0);
trap : std_ulogic;
annul : std_ulogic;
wreg : std_ulogic;
wicc : std_ulogic;
wy : std_ulogic;
ld : std_ulogic;
pv : std_ulogic;
rett : std_ulogic;
end record;
type fetch_reg_type is record
pc : pctype;
branch : std_ulogic;
end record;
type decode_reg_type is record
pc : pctype;
inst : icdtype;
cwp : cwptype;
set : std_logic_vector(ISETMSB downto 0);
mexc : std_ulogic;
cnt : std_logic_vector(1 downto 0);
pv : std_ulogic;
annul : std_ulogic;
inull : std_ulogic;
step : std_ulogic;
end record;
type regacc_reg_type is record
ctrl : pipeline_ctrl_type;
rs1 : std_logic_vector(4 downto 0);
rfa1, rfa2 : rfatype;
rsel1, rsel2 : std_logic_vector(2 downto 0);
rfe1, rfe2 : std_ulogic;
cwp : cwptype;
imm : word;
ldcheck1 : std_ulogic;
ldcheck2 : std_ulogic;
ldchkra : std_ulogic;
ldchkex : std_ulogic;
su : std_ulogic;
et : std_ulogic;
wovf : std_ulogic;
wunf : std_ulogic;
ticc : std_ulogic;
jmpl : std_ulogic;
step : std_ulogic;
mulstart : std_ulogic;
divstart : std_ulogic;
end record;
type execute_reg_type is record
ctrl : pipeline_ctrl_type;
op1 : word;
op2 : word;
aluop : std_logic_vector(2 downto 0); -- Alu operation
alusel : std_logic_vector(1 downto 0); -- Alu result select
aluadd : std_ulogic;
alucin : std_ulogic;
ldbp1, ldbp2 : std_ulogic;
invop2 : std_ulogic;
shcnt : std_logic_vector(4 downto 0); -- shift count
sari : std_ulogic; -- shift msb
shleft : std_ulogic; -- shift left/right
ymsb : std_ulogic; -- shift left/right
rd : std_logic_vector(4 downto 0);
jmpl : std_ulogic;
su : std_ulogic;
et : std_ulogic;
cwp : cwptype;
icc : std_logic_vector(3 downto 0);
mulstep: std_ulogic;
mul : std_ulogic;
mac : std_ulogic;
end record;
type memory_reg_type is record
ctrl : pipeline_ctrl_type;
result : word;
y : word;
icc : std_logic_vector(3 downto 0);
nalign : std_ulogic;
dci : dc_in_type;
werr : std_ulogic;
wcwp : std_ulogic;
irqen : std_ulogic;
irqen2 : std_ulogic;
mac : std_ulogic;
divz : std_ulogic;
su : std_ulogic;
mul : std_ulogic;
end record;
type exception_state is (run, trap, dsu1, dsu2);
type exception_reg_type is record
ctrl : pipeline_ctrl_type;
result : word;
y : word;
icc : std_logic_vector( 3 downto 0);
annul_all : std_ulogic;
data : dcdtype;
set : std_logic_vector(DSETMSB downto 0);
mexc : std_ulogic;
dci : dc_in_type;
laddr : std_logic_vector(1 downto 0);
rstate : exception_state;
npc : std_logic_vector(2 downto 0);
intack : std_ulogic;
ipend : std_ulogic;
mac : std_ulogic;
debug : std_ulogic;
nerror : std_ulogic;
end record;
type dsu_registers is record
tt : std_logic_vector(7 downto 0);
err : std_ulogic;
tbufcnt : std_logic_vector(TBUFBITS-1 downto 0);
asi : std_logic_vector(7 downto 0);
crdy : std_logic_vector(2 downto 1); -- diag cache access ready
end record;
type irestart_register is record
addr : pctype;
pwd : std_ulogic;
end record;
type pwd_register_type is record
pwd : std_ulogic;
error : std_ulogic;
end record;
type special_register_type is record
cwp : cwptype; -- current window pointer
icc : std_logic_vector(3 downto 0); -- integer condition codes
tt : std_logic_vector(7 downto 0); -- trap type
tba : std_logic_vector(19 downto 0); -- trap base address
wim : std_logic_vector(NWIN-1 downto 0); -- window invalid mask
pil : std_logic_vector(3 downto 0); -- processor interrupt level
ec : std_ulogic; -- enable CP
ef : std_ulogic; -- enable FP
ps : std_ulogic; -- previous supervisor flag
s : std_ulogic; -- supervisor flag
et : std_ulogic; -- enable traps
y : word;
asr18 : word;
svt : std_ulogic; -- enable traps
dwt : std_ulogic; -- disable write error trap
end record;
type write_reg_type is record
s : special_register_type;
result : word;
wa : rfatype;
wreg : std_ulogic;
except : std_ulogic;
end record;
type registers is record
f : fetch_reg_type;
d : decode_reg_type;
a : regacc_reg_type;
e : execute_reg_type;
m : memory_reg_type;
x : exception_reg_type;
w : write_reg_type;
end record;
type exception_type is record
pri : std_ulogic;
ill : std_ulogic;
fpdis : std_ulogic;
cpdis : std_ulogic;
wovf : std_ulogic;
wunf : std_ulogic;
ticc : std_ulogic;
end record;
type watchpoint_register is record
addr : std_logic_vector(31 downto 2); -- watchpoint address
mask : std_logic_vector(31 downto 2); -- watchpoint mask
exec : std_ulogic; -- trap on instruction
load : std_ulogic; -- trap on load
store : std_ulogic; -- trap on store
end record;
type watchpoint_registers is array (0 to 3) of watchpoint_register;
constant wpr_none : watchpoint_register := (
zero32(31 downto 2), zero32(31 downto 2), '0', '0', '0');
function dbgexc(r : registers; dbgi : l3_debug_in_type; trap : std_ulogic; tt : std_logic_vector(7 downto 0)) return std_ulogic is
variable dmode : std_ulogic;
begin
dmode := '0';
if (not r.x.ctrl.annul and trap) = '1' then
if (((tt = "00" & TT_WATCH) and (dbgi.bwatch = '1')) or
((dbgi.bsoft = '1') and (tt = "10000001")) or
(dbgi.btrapa = '1') or
((dbgi.btrape = '1') and not ((tt(5 downto 0) = TT_PRIV) or
(tt(5 downto 0) = TT_FPDIS) or (tt(5 downto 0) = TT_WINOF) or
(tt(5 downto 0) = TT_WINUF) or (tt(5 downto 4) = "01") or (tt(7) = '1'))) or
(((not r.w.s.et) and dbgi.berror) = '1')) then
dmode := '1';
end if;
end if;
return(dmode);
end;
function dbgerr(r : registers; dbgi : l3_debug_in_type;
tt : std_logic_vector(7 downto 0))
return std_ulogic is
variable err : std_ulogic;
begin
err := not r.w.s.et;
if (((dbgi.dbreak = '1') and (tt = ("00" & TT_WATCH))) or
((dbgi.bsoft = '1') and (tt = ("10000001")))) then
err := '0';
end if;
return(err);
end;
procedure diagwr(r : in registers;
dsur : in dsu_registers;
ir : in irestart_register;
dbg : in l3_debug_in_type;
wpr : in watchpoint_registers;
s : out special_register_type;
vwpr : out watchpoint_registers;
asi : out std_logic_vector(7 downto 0);
pc, npc : out pctype;
tbufcnt : out std_logic_vector(TBUFBITS-1 downto 0);
wr : out std_ulogic;
addr : out std_logic_vector(9 downto 0);
data : out word;
fpcwr : out std_ulogic) is
variable i : integer range 0 to 3;
begin
s := r.w.s; pc := r.f.pc; npc := ir.addr; wr := '0';
vwpr := wpr; asi := dsur.asi; addr := (others => '0');
data := dbg.ddata;
tbufcnt := dsur.tbufcnt; fpcwr := '0';
if (dbg.dsuen and dbg.denable and dbg.dwrite) = '1' then
case dbg.daddr(23 downto 20) is
when "0001" =>
if (dbg.daddr(16) = '1') and TRACEBUF then -- trace buffer control reg
tbufcnt := dbg.ddata(TBUFBITS-1 downto 0);
end if;
when "0011" => -- IU reg file
if dbg.daddr(12) = '0' then
wr := '1';
addr := (others => '0');
addr(RFBITS-1 downto 0) := dbg.daddr(RFBITS+1 downto 2);
else -- FPC
fpcwr := '1';
end if;
when "0100" => -- IU special registers
case dbg.daddr(7 downto 6) is
when "00" => -- IU regs Y - TBUF ctrl reg
case dbg.daddr(5 downto 2) is
when "0000" => -- Y
s.y := dbg.ddata;
when "0001" => -- PSR
s.cwp := dbg.ddata(NWINLOG2-1 downto 0);
s.icc := dbg.ddata(23 downto 20);
s.ec := dbg.ddata(13);
if FPEN then s.ef := dbg.ddata(12); end if;
s.pil := dbg.ddata(11 downto 8);
s.s := dbg.ddata(7);
s.ps := dbg.ddata(6);
s.et := dbg.ddata(5);
when "0010" => -- WIM
s.wim := dbg.ddata(NWIN-1 downto 0);
when "0011" => -- TBR
s.tba := dbg.ddata(31 downto 12);
s.tt := dbg.ddata(11 downto 4);
when "0100" => -- PC
pc := dbg.ddata(31 downto PCLOW);
when "0101" => -- NPC
npc := dbg.ddata(31 downto PCLOW);
when "0110" => --FSR
fpcwr := '1';
when "0111" => --CFSR
when "1001" => -- ASI reg
asi := dbg.ddata(7 downto 0);
--when "1001" => -- TBUF ctrl reg
-- tbufcnt := dbg.ddata(TBUFBITS-1 downto 0);
when others =>
end case;
when "01" => -- ASR16 - ASR31
case dbg.daddr(5 downto 2) is
when "0001" => -- %ASR17
s.dwt := dbg.ddata(14);
s.svt := dbg.ddata(13);
when "0010" => -- %ASR18
if MACEN then s.asr18 := dbg.ddata; end if;
when "1000" => -- %ASR24 - %ASR31
vwpr(0).addr := dbg.ddata(31 downto 2);
vwpr(0).exec := dbg.ddata(0);
when "1001" =>
vwpr(0).mask := dbg.ddata(31 downto 2);
vwpr(0).load := dbg.ddata(1);
vwpr(0).store := dbg.ddata(0);
when "1010" =>
vwpr(1).addr := dbg.ddata(31 downto 2);
vwpr(1).exec := dbg.ddata(0);
when "1011" =>
vwpr(1).mask := dbg.ddata(31 downto 2);
vwpr(1).load := dbg.ddata(1);
vwpr(1).store := dbg.ddata(0);
when "1100" =>
vwpr(2).addr := dbg.ddata(31 downto 2);
vwpr(2).exec := dbg.ddata(0);
when "1101" =>
vwpr(2).mask := dbg.ddata(31 downto 2);
vwpr(2).load := dbg.ddata(1);
vwpr(2).store := dbg.ddata(0);
when "1110" =>
vwpr(3).addr := dbg.ddata(31 downto 2);
vwpr(3).exec := dbg.ddata(0);
when "1111" => --
vwpr(3).mask := dbg.ddata(31 downto 2);
vwpr(3).load := dbg.ddata(1);
vwpr(3).store := dbg.ddata(0);
when others => --
end case;
-- disabled due to bug in XST
-- i := conv_integer(dbg.daddr(4 downto 3));
-- if dbg.daddr(2) = '0' then
-- vwpr(i).addr := dbg.ddata(31 downto 2);
-- vwpr(i).exec := dbg.ddata(0);
-- else
-- vwpr(i).mask := dbg.ddata(31 downto 2);
-- vwpr(i).load := dbg.ddata(1);
-- vwpr(i).store := dbg.ddata(0);
-- end if;
when others =>
end case;
when others =>
end case;
end if;
end;
function asr17_gen ( r : in registers) return word is
variable asr17 : word;
variable fpu2 : integer range 0 to 3;
begin
asr17 := zero32;
asr17(31 downto 28) := conv_std_logic_vector(index, 4);
if (clk2x > 8) then
asr17(16 downto 15) := conv_std_logic_vector(clk2x-8, 2);
asr17(17) := '1';
elsif (clk2x > 0) then
asr17(16 downto 15) := conv_std_logic_vector(clk2x, 2);
end if;
asr17(14) := r.w.s.dwt;
if svt = 1 then asr17(13) := r.w.s.svt; end if;
if lddel = 2 then asr17(12) := '1'; end if;
if (fpu > 0) and (fpu < 8) then fpu2 := 1;
elsif (fpu >= 8) and (fpu < 15) then fpu2 := 3;
elsif fpu = 15 then fpu2 := 2;
else fpu2 := 0; end if;
asr17(11 downto 10) := conv_std_logic_vector(fpu2, 2);
if mac = 1 then asr17(9) := '1'; end if;
if v8 /= 0 then asr17(8) := '1'; end if;
asr17(7 downto 5) := conv_std_logic_vector(nwp, 3);
asr17(4 downto 0) := conv_std_logic_vector(nwin-1, 5);
return(asr17);
end;
procedure diagread(dbgi : in l3_debug_in_type;
r : in registers;
dsur : in dsu_registers;
ir : in irestart_register;
wpr : in watchpoint_registers;
dco : in dcache_out_type;
tbufo : in tracebuf_out_type;
data : out word) is
variable cwp : std_logic_vector(4 downto 0);
variable rd : std_logic_vector(4 downto 0);
variable i : integer range 0 to 3;
begin
data := (others => '0'); cwp := (others => '0');
cwp(NWINLOG2-1 downto 0) := r.w.s.cwp;
case dbgi.daddr(22 downto 20) is
when "001" => -- trace buffer
if TRACEBUF then
if dbgi.daddr(16) = '1' then -- trace buffer control reg
if TRACEBUF then data(TBUFBITS-1 downto 0) := dsur.tbufcnt; end if;
else
case dbgi.daddr(3 downto 2) is
when "00" => data := tbufo.data(127 downto 96);
when "01" => data := tbufo.data(95 downto 64);
when "10" => data := tbufo.data(63 downto 32);
when others => data := tbufo.data(31 downto 0);
end case;
end if;
end if;
when "011" => -- IU reg file
if dbgi.daddr(12) = '0' then
data := rfo.data1(31 downto 0);
if (dbgi.daddr(11) = '1') and (is_fpga(fabtech) = 0) then
data := rfo.data2(31 downto 0);
end if;
else data := fpo.dbg.data; end if;
when "100" => -- IU regs
case dbgi.daddr(7 downto 6) is
when "00" => -- IU regs Y - TBUF ctrl reg
case dbgi.daddr(5 downto 2) is
when "0000" =>
data := r.w.s.y;
when "0001" =>
data := conv_std_logic_vector(IMPL, 4) & conv_std_logic_vector(VER, 4) &
r.w.s.icc & "000000" & r.w.s.ec & r.w.s.ef & r.w.s.pil &
r.w.s.s & r.w.s.ps & r.w.s.et & cwp;
when "0010" =>
data(NWIN-1 downto 0) := r.w.s.wim;
when "0011" =>
data := r.w.s.tba & r.w.s.tt & "0000";
when "0100" =>
data(31 downto PCLOW) := r.f.pc;
when "0101" =>
data(31 downto PCLOW) := ir.addr;
when "0110" => -- FSR
data := fpo.dbg.data;
when "0111" => -- CPSR
when "1000" => -- TT reg
data(12 downto 4) := dsur.err & dsur.tt;
when "1001" => -- ASI reg
data(7 downto 0) := dsur.asi;
when others =>
end case;
when "01" =>
if dbgi.daddr(5) = '0' then -- %ASR17
if dbgi.daddr(4 downto 2) = "001" then -- %ASR17
data := asr17_gen(r);
elsif MACEN and dbgi.daddr(4 downto 2) = "010" then -- %ASR18
data := r.w.s.asr18;
end if;
else -- %ASR24 - %ASR31
i := conv_integer(dbgi.daddr(4 downto 3)); --
if dbgi.daddr(2) = '0' then
data(31 downto 2) := wpr(i).addr;
data(0) := wpr(i).exec;
else
data(31 downto 2) := wpr(i).mask;
data(1) := wpr(i).load;
data(0) := wpr(i).store;
end if;
end if;
when others =>
end case;
when "111" =>
data := r.x.data(conv_integer(r.x.set));
when others =>
end case;
end;
procedure itrace(r : in registers;
dsur : in dsu_registers;
vdsu : in dsu_registers;
res : in word;
exc : in std_ulogic;
dbgi : in l3_debug_in_type;
error : in std_ulogic;
trap : in std_ulogic;
tbufcnt : out std_logic_vector(TBUFBITS-1 downto 0);
di : out tracebuf_in_type) is
variable meminst : std_ulogic;
begin
di.addr := (others => '0'); di.data := (others => '0');
di.enable := '0'; di.write := (others => '0');
tbufcnt := vdsu.tbufcnt;
meminst := r.x.ctrl.inst(31) and r.x.ctrl.inst(30);
if TRACEBUF then
di.addr(TBUFBITS-1 downto 0) := dsur.tbufcnt;
di.data(127) := '0';
di.data(126) := not r.x.ctrl.pv;
di.data(125 downto 96) := dbgi.timer(29 downto 0);
di.data(95 downto 64) := res;
di.data(63 downto 34) := r.x.ctrl.pc(31 downto 2);
di.data(33) := trap;
di.data(32) := error;
di.data(31 downto 0) := r.x.ctrl.inst;
if (dbgi.tenable = '0') or (r.x.rstate = dsu2) then
if ((dbgi.dsuen and dbgi.denable) = '1') and (dbgi.daddr(23 downto 20) & dbgi.daddr(16) = "00010") then
di.enable := '1';
di.addr(TBUFBITS-1 downto 0) := dbgi.daddr(TBUFBITS-1+4 downto 4);
if dbgi.dwrite = '1' then
case dbgi.daddr(3 downto 2) is
when "00" => di.write(3) := '1';
when "01" => di.write(2) := '1';
when "10" => di.write(1) := '1';
when others => di.write(0) := '1';
end case;
di.data := dbgi.ddata & dbgi.ddata & dbgi.ddata & dbgi.ddata;
end if;
end if;
elsif (not r.x.ctrl.annul and (r.x.ctrl.pv or meminst) and not r.x.debug) = '1' then
di.enable := '1'; di.write := (others => '1');
tbufcnt := dsur.tbufcnt + 1;
end if;
di.diag := dco.testen & "000";
if dco.scanen = '1' then di.enable := '0'; end if;
end if;
end;
procedure dbg_cache(holdn : in std_ulogic;
dbgi : in l3_debug_in_type;
r : in registers;
dsur : in dsu_registers;
mresult : in word;
dci : in dc_in_type;
mresult2 : out word;
dci2 : out dc_in_type
) is
begin
mresult2 := mresult; dci2 := dci; dci2.dsuen := '0';
if DBGUNIT then
if r.x.rstate = dsu2 then
dci2.asi := dsur.asi;
if (dbgi.daddr(22 downto 20) = "111") and (dbgi.dsuen = '1') then
dci2.dsuen := (dbgi.denable or r.m.dci.dsuen) and not dsur.crdy(2);
dci2.enaddr := dbgi.denable;
dci2.size := "10"; dci2.read := '1'; dci2.write := '0';
if (dbgi.denable and not r.m.dci.enaddr) = '1' then
mresult2 := (others => '0'); mresult2(19 downto 2) := dbgi.daddr(19 downto 2);
else
mresult2 := dbgi.ddata;
end if;
if dbgi.dwrite = '1' then
dci2.read := '0'; dci2.write := '1';
end if;
end if;
end if;
end if;
end;
procedure fpexack(r : in registers; fpexc : out std_ulogic) is
begin
fpexc := '0';
if FPEN then
if r.x.ctrl.tt = TT_FPEXC then fpexc := '1'; end if;
end if;
end;
procedure diagrdy(denable : in std_ulogic;
dsur : in dsu_registers;
dci : in dc_in_type;
mds : in std_ulogic;
ico : in icache_out_type;
crdy : out std_logic_vector(2 downto 1)) is
begin
crdy := dsur.crdy(1) & '0';
if dci.dsuen = '1' then
case dsur.asi(4 downto 0) is
when ASI_ITAG | ASI_IDATA | ASI_UINST | ASI_SINST =>
crdy(2) := ico.diagrdy and not dsur.crdy(2);
when ASI_DTAG | ASI_MMUSNOOP_DTAG | ASI_DDATA | ASI_UDATA | ASI_SDATA =>
crdy(1) := not denable and dci.enaddr and not dsur.crdy(1);
when others =>
crdy(2) := dci.enaddr and denable;
end case;
end if;
end;
signal r, rin : registers;
signal wpr, wprin : watchpoint_registers;
signal dsur, dsuin : dsu_registers;
signal ir, irin : irestart_register;
signal rp, rpin : pwd_register_type;
-- execute stage operations
constant EXE_AND : std_logic_vector(2 downto 0) := "000";
constant EXE_XOR : std_logic_vector(2 downto 0) := "001"; -- must be equal to EXE_PASS2
constant EXE_OR : std_logic_vector(2 downto 0) := "010";
constant EXE_XNOR : std_logic_vector(2 downto 0) := "011";
constant EXE_ANDN : std_logic_vector(2 downto 0) := "100";
constant EXE_ORN : std_logic_vector(2 downto 0) := "101";
constant EXE_DIV : std_logic_vector(2 downto 0) := "110";
constant EXE_PASS1 : std_logic_vector(2 downto 0) := "000";
constant EXE_PASS2 : std_logic_vector(2 downto 0) := "001";
constant EXE_STB : std_logic_vector(2 downto 0) := "010";
constant EXE_STH : std_logic_vector(2 downto 0) := "011";
constant EXE_ONES : std_logic_vector(2 downto 0) := "100";
constant EXE_RDY : std_logic_vector(2 downto 0) := "101";
constant EXE_SPR : std_logic_vector(2 downto 0) := "110";
constant EXE_LINK : std_logic_vector(2 downto 0) := "111";
constant EXE_SLL : std_logic_vector(2 downto 0) := "001";
constant EXE_SRL : std_logic_vector(2 downto 0) := "010";
constant EXE_SRA : std_logic_vector(2 downto 0) := "100";
constant EXE_NOP : std_logic_vector(2 downto 0) := "000";
-- EXE result select
constant EXE_RES_ADD : std_logic_vector(1 downto 0) := "00";
constant EXE_RES_SHIFT : std_logic_vector(1 downto 0) := "01";
constant EXE_RES_LOGIC : std_logic_vector(1 downto 0) := "10";
constant EXE_RES_MISC : std_logic_vector(1 downto 0) := "11";
-- Load types
constant SZBYTE : std_logic_vector(1 downto 0) := "00";
constant SZHALF : std_logic_vector(1 downto 0) := "01";
constant SZWORD : std_logic_vector(1 downto 0) := "10";
constant SZDBL : std_logic_vector(1 downto 0) := "11";
-- calculate register file address
procedure regaddr(cwp : std_logic_vector; reg : std_logic_vector(4 downto 0);
rao : out rfatype) is
variable ra : rfatype;
constant globals : std_logic_vector(RFBITS-5 downto 0) :=
conv_std_logic_vector(NWIN, RFBITS-4);
begin
ra := (others => '0'); ra(4 downto 0) := reg;
if reg(4 downto 3) = "00" then ra(RFBITS -1 downto 4) := globals;
else
ra(NWINLOG2+3 downto 4) := cwp + ra(4);
if ra(RFBITS-1 downto 4) = globals then
ra(RFBITS-1 downto 4) := (others => '0');
end if;
end if;
rao := ra;
end;
-- branch adder
function branch_address(inst : word; pc : pctype) return std_logic_vector is
variable baddr, caddr, tmp : pctype;
begin
caddr := (others => '0'); caddr(31 downto 2) := inst(29 downto 0);
caddr(31 downto 2) := caddr(31 downto 2) + pc(31 downto 2);
baddr := (others => '0'); baddr(31 downto 24) := (others => inst(21));
baddr(23 downto 2) := inst(21 downto 0);
baddr(31 downto 2) := baddr(31 downto 2) + pc(31 downto 2);
if inst(30) = '1' then tmp := caddr; else tmp := baddr; end if;
return(tmp);
end;
-- evaluate branch condition
function branch_true(icc : std_logic_vector(3 downto 0); inst : word)
return std_ulogic is
variable n, z, v, c, branch : std_ulogic;
begin
n := icc(3); z := icc(2); v := icc(1); c := icc(0);
case inst(27 downto 25) is
when "000" => branch := inst(28) xor '0'; -- bn, ba
when "001" => branch := inst(28) xor z; -- be, bne
when "010" => branch := inst(28) xor (z or (n xor v)); -- ble, bg
when "011" => branch := inst(28) xor (n xor v); -- bl, bge
when "100" => branch := inst(28) xor (c or z); -- bleu, bgu
when "101" => branch := inst(28) xor c; -- bcs, bcc
when "110" => branch := inst(28) xor n; -- bneg, bpos
when others => branch := inst(28) xor v; -- bvs, bvc
end case;
return(branch);
end;
-- detect RETT instruction in the pipeline and set the local psr.su and psr.et
procedure su_et_select(r : in registers; xc_ps, xc_s, xc_et : in std_ulogic;
su, et : out std_ulogic) is
begin
if ((r.a.ctrl.rett or r.e.ctrl.rett or r.m.ctrl.rett or r.x.ctrl.rett) = '1')
and (r.x.annul_all = '0')
then su := xc_ps; et := '1';
else su := xc_s; et := xc_et; end if;
end;
-- detect watchpoint trap
function wphit(r : registers; wpr : watchpoint_registers; debug : l3_debug_in_type; handleTrap : std_ulogic)
return std_ulogic is
variable exc : std_ulogic;
begin
exc := handleTrap;
for i in 1 to NWP loop
if ((wpr(i-1).exec and r.a.ctrl.pv and not r.a.ctrl.annul) = '1') then
if (((wpr(i-1).addr xor r.a.ctrl.pc(31 downto 2)) and wpr(i-1).mask) = Zero32(31 downto 2)) then
exc := '1';
end if;
end if;
end loop;
if DBGUNIT then
if (debug.dsuen and not r.a.ctrl.annul) = '1' then
exc := exc or (r.a.ctrl.pv and ((debug.dbreak and debug.bwatch) or r.a.step));
end if;
end if;
return(exc);
end;
-- 32-bit shifter
function shift3(r : registers; aluin1, aluin2 : word) return word is
variable shiftin : unsigned(63 downto 0);
variable shiftout : unsigned(63 downto 0);
variable cnt : natural range 0 to 31;
begin
cnt := conv_integer(r.e.shcnt);
if r.e.shleft = '1' then
shiftin(30 downto 0) := (others => '0');
shiftin(63 downto 31) := '0' & unsigned(aluin1);
else
shiftin(63 downto 32) := (others => r.e.sari);
shiftin(31 downto 0) := unsigned(aluin1);
end if;
shiftout := SHIFT_RIGHT(shiftin, cnt);
return(std_logic_vector(shiftout(31 downto 0)));
end;
function shift2(r : registers; aluin1, aluin2 : word) return word is
variable ushiftin : unsigned(31 downto 0);
variable sshiftin : signed(32 downto 0);
variable cnt : natural range 0 to 31;
variable resleft, resright : word;
begin
cnt := conv_integer(r.e.shcnt);
ushiftin := unsigned(aluin1);
sshiftin := signed('0' & aluin1);
if r.e.shleft = '1' then
resleft := std_logic_vector(SHIFT_LEFT(ushiftin, cnt));
return(resleft);
else
if r.e.sari = '1' then sshiftin(32) := aluin1(31); end if;
sshiftin := SHIFT_RIGHT(sshiftin, cnt);
resright := std_logic_vector(sshiftin(31 downto 0));
return(resright);
-- else
-- ushiftin := SHIFT_RIGHT(ushiftin, cnt);
-- return(std_logic_vector(ushiftin));
-- end if;
end if;
end;
function shift(r : registers; aluin1, aluin2 : word;
shiftcnt : std_logic_vector(4 downto 0); sari : std_ulogic ) return word is
variable shiftin : std_logic_vector(63 downto 0);
begin
shiftin := zero32 & aluin1;
if r.e.shleft = '1' then
shiftin(31 downto 0) := zero32; shiftin(63 downto 31) := '0' & aluin1;
else shiftin(63 downto 32) := (others => sari); end if;
if shiftcnt (4) = '1' then shiftin(47 downto 0) := shiftin(63 downto 16); end if;
if shiftcnt (3) = '1' then shiftin(39 downto 0) := shiftin(47 downto 8); end if;
if shiftcnt (2) = '1' then shiftin(35 downto 0) := shiftin(39 downto 4); end if;
if shiftcnt (1) = '1' then shiftin(33 downto 0) := shiftin(35 downto 2); end if;
if shiftcnt (0) = '1' then shiftin(31 downto 0) := shiftin(32 downto 1); end if;
return(shiftin(31 downto 0));
end;
-- Check for illegal and privileged instructions
procedure exception_detect(r : registers; wpr : watchpoint_registers; dbgi : l3_debug_in_type;
trapin : in std_ulogic; ttin : in std_logic_vector(5 downto 0);
trap : out std_ulogic; tt : out std_logic_vector(5 downto 0); handleTrap : in std_ulogic) is
variable illegal_inst, privileged_inst : std_ulogic;
variable cp_disabled, fp_disabled, fpop : std_ulogic;
variable op : std_logic_vector(1 downto 0);
variable op2 : std_logic_vector(2 downto 0);
variable op3 : std_logic_vector(5 downto 0);
variable rd : std_logic_vector(4 downto 0);
variable inst : word;
variable wph : std_ulogic;
begin
inst := r.a.ctrl.inst; trap := trapin; tt := ttin;
if r.a.ctrl.annul = '0' then
op := inst(31 downto 30); op2 := inst(24 downto 22);
op3 := inst(24 downto 19); rd := inst(29 downto 25);
illegal_inst := '0'; privileged_inst := '0'; cp_disabled := '0';
fp_disabled := '0'; fpop := '0';
case op is
when CALL => null;
when FMT2 =>
case op2 is
when SETHI | BICC => null;
when FBFCC =>
if FPEN then fp_disabled := not r.w.s.ef; else fp_disabled := '1'; end if;
when CBCCC =>
if (not CPEN) or (r.w.s.ec = '0') then cp_disabled := '1'; end if;
when others => illegal_inst := '1';
end case;
when FMT3 =>
case op3 is
when IAND | ANDCC | ANDN | ANDNCC | IOR | ORCC | ORN | ORNCC | IXOR |
XORCC | IXNOR | XNORCC | ISLL | ISRL | ISRA | MULSCC | IADD | ADDX |
ADDCC | ADDXCC | ISUB | SUBX | SUBCC | SUBXCC | FLUSH | JMPL | TICC |
SAVE | RESTORE | RDY => null;
when TADDCC | TADDCCTV | TSUBCC | TSUBCCTV =>
if notag = 1 then illegal_inst := '1'; end if;
when UMAC | SMAC =>
if not MACEN then illegal_inst := '1'; end if;
when UMUL | SMUL | UMULCC | SMULCC =>
if not MULEN then illegal_inst := '1'; end if;
when UDIV | SDIV | UDIVCC | SDIVCC =>
if not DIVEN then illegal_inst := '1'; end if;
when RETT => illegal_inst := r.a.et; privileged_inst := not r.a.su;
when RDPSR | RDTBR | RDWIM => privileged_inst := not r.a.su;
when WRY => null;
when WRPSR =>
privileged_inst := not r.a.su;
when WRWIM | WRTBR => privileged_inst := not r.a.su;
when FPOP1 | FPOP2 =>
if FPEN then fp_disabled := not r.w.s.ef; fpop := '1';
else fp_disabled := '1'; fpop := '0'; end if;
when CPOP1 | CPOP2 =>
if (not CPEN) or (r.w.s.ec = '0') then cp_disabled := '1'; end if;
when others => illegal_inst := '1';
end case;
when others => -- LDST
case op3 is
when LDD | ISTD => illegal_inst := rd(0); -- trap if odd destination register
when LD | LDUB | LDSTUB | LDUH | LDSB | LDSH | ST | STB | STH | SWAP =>
null;
when LDDA | STDA =>
illegal_inst := inst(13) or rd(0); privileged_inst := not r.a.su;
when LDA | LDUBA| LDSTUBA | LDUHA | LDSBA | LDSHA | STA | STBA | STHA |
SWAPA =>
illegal_inst := inst(13); privileged_inst := not r.a.su;
when LDDF | STDF | LDF | LDFSR | STF | STFSR =>
if FPEN then fp_disabled := not r.w.s.ef;
else fp_disabled := '1'; end if;
when STDFQ =>
privileged_inst := not r.a.su;
if (not FPEN) or (r.w.s.ef = '0') then fp_disabled := '1'; end if;
when STDCQ =>
privileged_inst := not r.a.su;
if (not CPEN) or (r.w.s.ec = '0') then cp_disabled := '1'; end if;
when LDC | LDCSR | LDDC | STC | STCSR | STDC =>
if (not CPEN) or (r.w.s.ec = '0') then cp_disabled := '1'; end if;
when others => illegal_inst := '1';
end case;
end case;
wph := wphit(r, wpr, dbgi, handleTrap);
trap := '1';
if r.a.ctrl.trap = '1' then tt := TT_IAEX;
elsif privileged_inst = '1' then tt := TT_PRIV;
elsif illegal_inst = '1' then tt := TT_IINST;
elsif fp_disabled = '1' then tt := TT_FPDIS;
elsif cp_disabled = '1' then tt := TT_CPDIS;
elsif wph = '1' then tt := TT_WATCH;
elsif r.a.wovf= '1' then tt := TT_WINOF;
elsif r.a.wunf= '1' then tt := TT_WINUF;
elsif r.a.ticc= '1' then tt := TT_TICC;
else trap := '0'; tt:= (others => '0'); end if;
end if;
end;
-- instructions that write the condition codes (psr.icc)
procedure wicc_y_gen(inst : word; wicc, wy : out std_ulogic) is
begin
wicc := '0'; wy := '0';
if inst(31 downto 30) = FMT3 then
case inst(24 downto 19) is
when SUBCC | TSUBCC | TSUBCCTV | ADDCC | ANDCC | ORCC | XORCC | ANDNCC |
ORNCC | XNORCC | TADDCC | TADDCCTV | ADDXCC | SUBXCC | WRPSR =>
wicc := '1';
when WRY =>
if r.d.inst(conv_integer(r.d.set))(29 downto 25) = "00000" then wy := '1'; end if;
when MULSCC =>
wicc := '1'; wy := '1';
when UMAC | SMAC =>
if MACEN then wy := '1'; end if;
when UMULCC | SMULCC =>
if MULEN and (((mulo.nready = '1') and (r.d.cnt /= "00")) or (MULTYPE /= 0)) then
wicc := '1'; wy := '1';
end if;
when UMUL | SMUL =>
if MULEN and (((mulo.nready = '1') and (r.d.cnt /= "00")) or (MULTYPE /= 0)) then
wy := '1';
end if;
when UDIVCC | SDIVCC =>
if DIVEN and (divo.nready = '1') and (r.d.cnt /= "00") then
wicc := '1';
end if;
when others =>
end case;
end if;
end;
-- select cwp
procedure cwp_gen(r, v : registers; annul, wcwp : std_ulogic; ncwp : cwptype;
cwp : out cwptype) is
begin
if (r.x.rstate = trap) or (r.x.rstate = dsu2) or (rstn = '0') then cwp := v.w.s.cwp;
elsif (wcwp = '1') and (annul = '0') then cwp := ncwp;
elsif r.m.wcwp = '1' then cwp := r.m.result(NWINLOG2-1 downto 0);
else cwp := r.d.cwp; end if;
end;
-- generate wcwp in ex stage
procedure cwp_ex(r : in registers; wcwp : out std_ulogic) is
begin
if (r.e.ctrl.inst(31 downto 30) = FMT3) and
(r.e.ctrl.inst(24 downto 19) = WRPSR)
then wcwp := not r.e.ctrl.annul; else wcwp := '0'; end if;
end;
-- generate next cwp & window under- and overflow traps
procedure cwp_ctrl(r : in registers; xc_wim : in std_logic_vector(NWIN-1 downto 0);
inst : word; de_cwp : out cwptype; wovf_exc, wunf_exc, wcwp : out std_ulogic) is
variable op : std_logic_vector(1 downto 0);
variable op3 : std_logic_vector(5 downto 0);
variable wim : word;
variable ncwp : cwptype;
begin
op := inst(31 downto 30); op3 := inst(24 downto 19);
wovf_exc := '0'; wunf_exc := '0'; wim := (others => '0');
wim(NWIN-1 downto 0) := xc_wim; ncwp := r.d.cwp; wcwp := '0';
if (op = FMT3) and ((op3 = RETT) or (op3 = RESTORE) or (op3 = SAVE)) then
wcwp := '1';
if (op3 = SAVE) then
if (not CWPOPT) and (r.d.cwp = CWPMIN) then ncwp := CWPMAX;
else ncwp := r.d.cwp - 1 ; end if;
else
if (not CWPOPT) and (r.d.cwp = CWPMAX) then ncwp := CWPMIN;
else ncwp := r.d.cwp + 1; end if;
end if;
if wim(conv_integer(ncwp)) = '1' then
if op3 = SAVE then wovf_exc := '1'; else wunf_exc := '1'; end if;
end if;
end if;
de_cwp := ncwp;
end;
-- generate register read address 1
procedure rs1_gen(r : registers; inst : word; rs1 : out std_logic_vector(4 downto 0);
rs1mod : out std_ulogic) is
variable op : std_logic_vector(1 downto 0);
variable op3 : std_logic_vector(5 downto 0);
begin
op := inst(31 downto 30); op3 := inst(24 downto 19);
rs1 := inst(18 downto 14); rs1mod := '0';
if (op = LDST) then
if ((r.d.cnt = "01") and ((op3(2) and not op3(3)) = '1')) or
(r.d.cnt = "10")
then rs1mod := '1'; rs1 := inst(29 downto 25); end if;
if ((r.d.cnt = "10") and (op3(3 downto 0) = "0111")) then
rs1(0) := '1';
end if;
end if;
end;
-- load/icc interlock detection
procedure lock_gen(r : registers; rs2, rd : std_logic_vector(4 downto 0);
rfa1, rfa2, rfrd : rfatype; inst : word; fpc_lock, mulinsn, divinsn : std_ulogic;
lldcheck1, lldcheck2, lldlock, lldchkra, lldchkex : out std_ulogic) is
variable op : std_logic_vector(1 downto 0);
variable op2 : std_logic_vector(2 downto 0);
variable op3 : std_logic_vector(5 downto 0);
variable cond : std_logic_vector(3 downto 0);
variable rs1 : std_logic_vector(4 downto 0);
variable i, ldcheck1, ldcheck2, ldchkra, ldchkex, ldcheck3 : std_ulogic;
variable ldlock, icc_check, bicc_hold, chkmul, y_check : std_ulogic;
variable lddlock : boolean;
begin
op := inst(31 downto 30); op3 := inst(24 downto 19);
op2 := inst(24 downto 22); cond := inst(28 downto 25);
rs1 := inst(18 downto 14); lddlock := false; i := inst(13);
ldcheck1 := '0'; ldcheck2 := '0'; ldcheck3 := '0'; ldlock := '0';
ldchkra := '1'; ldchkex := '1'; icc_check := '0'; bicc_hold := '0';
y_check := '0';
if (r.d.annul = '0') then
case op is
when FMT2 =>
if (op2 = BICC) and (cond(2 downto 0) /= "000") then
icc_check := '1';
end if;
when FMT3 =>
ldcheck1 := '1'; ldcheck2 := not i;
case op3 is
when TICC =>
if (cond(2 downto 0) /= "000") then icc_check := '1'; end if;
when RDY =>
ldcheck1 := '0'; ldcheck2 := '0';
if MACPIPE then y_check := '1'; end if;
when RDWIM | RDTBR =>
ldcheck1 := '0'; ldcheck2 := '0';
when RDPSR =>
ldcheck1 := '0'; ldcheck2 := '0'; icc_check := '1';
if MULEN then icc_check := '1'; end if;
-- when ADDX | ADDXCC | SUBX | SUBXCC =>
-- if MULEN then icc_check := '1'; end if;
when SDIV | SDIVCC | UDIV | UDIVCC =>
if DIVEN then y_check := '1'; end if;
when FPOP1 | FPOP2 => ldcheck1:= '0'; ldcheck2 := '0';
when others =>
end case;
when LDST =>
ldcheck1 := '1'; ldchkra := '0';
case r.d.cnt is
when "00" =>
if (lddel = 2) and (op3(2) = '1') then ldcheck3 := '1'; end if;
ldcheck2 := not i; ldchkra := '1';
when "01" => ldcheck2 := not i;
when others => ldchkex := '0';
end case;
if (op3(2 downto 0) = "011") then lddlock := true; end if;
when others => null;
end case;
end if;
if MULEN or DIVEN then
chkmul := mulinsn;
bicc_hold := bicc_hold or (icc_check and r.m.ctrl.wicc and (r.m.ctrl.cnt(0) or r.m.mul));
else chkmul := '0'; end if;
if DIVEN then
bicc_hold := bicc_hold or (y_check and (r.a.ctrl.wy or r.e.ctrl.wy));
chkmul := chkmul or divinsn;
end if;
bicc_hold := bicc_hold or (icc_check and (r.a.ctrl.wicc or r.e.ctrl.wicc));
if (((r.a.ctrl.ld or chkmul) and r.a.ctrl.wreg and ldchkra) = '1') and
(((ldcheck1 = '1') and (r.a.ctrl.rd = rfa1)) or
((ldcheck2 = '1') and (r.a.ctrl.rd = rfa2)) or
((ldcheck3 = '1') and (r.a.ctrl.rd = rfrd)))
then ldlock := '1'; end if;
if (((r.e.ctrl.ld or r.e.mac) and r.e.ctrl.wreg and ldchkex) = '1') and
((lddel = 2) or (MACPIPE and (r.e.mac = '1')) or ((MULTYPE = 3) and (r.e.mul = '1'))) and
(((ldcheck1 = '1') and (r.e.ctrl.rd = rfa1)) or
((ldcheck2 = '1') and (r.e.ctrl.rd = rfa2)))
then ldlock := '1'; end if;
ldlock := ldlock or bicc_hold or fpc_lock;
lldcheck1 := ldcheck1; lldcheck2:= ldcheck2; lldlock := ldlock;
lldchkra := ldchkra; lldchkex := ldchkex;
end;
procedure fpbranch(inst : in word; fcc : in std_logic_vector(1 downto 0);
branch : out std_ulogic) is
variable cond : std_logic_vector(3 downto 0);
variable fbres : std_ulogic;
begin
cond := inst(28 downto 25);
case cond(2 downto 0) is
when "000" => fbres := '0'; -- fba, fbn
when "001" => fbres := fcc(1) or fcc(0);
when "010" => fbres := fcc(1) xor fcc(0);
when "011" => fbres := fcc(0);
when "100" => fbres := (not fcc(1)) and fcc(0);
when "101" => fbres := fcc(1);
when "110" => fbres := fcc(1) and not fcc(0);
when others => fbres := fcc(1) and fcc(0);
end case;
branch := cond(3) xor fbres;
end;
-- PC generation
procedure ic_ctrl(r : registers; inst : word; annul_all, ldlock, branch_true,
fbranch_true, cbranch_true, fccv, cccv : in std_ulogic;
cnt : out std_logic_vector(1 downto 0);
de_pc : out pctype; de_branch, ctrl_annul, de_annul, jmpl_inst, inull,
de_pv, ctrl_pv, de_hold_pc, ticc_exception, rett_inst, mulstart,
divstart : out std_ulogic) is
variable op : std_logic_vector(1 downto 0);
variable op2 : std_logic_vector(2 downto 0);
variable op3 : std_logic_vector(5 downto 0);
variable cond : std_logic_vector(3 downto 0);
variable hold_pc, annul_current, annul_next, branch, annul, pv : std_ulogic;
variable de_jmpl : std_ulogic;
begin
branch := '0'; annul_next := '0'; annul_current := '0'; pv := '1';
hold_pc := '0'; ticc_exception := '0'; rett_inst := '0';
op := inst(31 downto 30); op3 := inst(24 downto 19);
op2 := inst(24 downto 22); cond := inst(28 downto 25);
annul := inst(29); de_jmpl := '0'; cnt := "00";
mulstart := '0'; divstart := '0';
if r.d.annul = '0' then
case inst(31 downto 30) is
when CALL =>
branch := '1';
if r.d.inull = '1' then
hold_pc := '1'; annul_current := '1';
end if;
when FMT2 =>
if (op2 = BICC) or (FPEN and (op2 = FBFCC)) or (CPEN and (op2 = CBCCC)) then
if (FPEN and (op2 = FBFCC)) then
branch := fbranch_true;
if fccv /= '1' then hold_pc := '1'; annul_current := '1'; end if;
elsif (CPEN and (op2 = CBCCC)) then
branch := cbranch_true;
if cccv /= '1' then hold_pc := '1'; annul_current := '1'; end if;
else branch := branch_true; end if;
if hold_pc = '0' then
if (branch = '1') then
if (cond = BA) and (annul = '1') then annul_next := '1'; end if;
else annul_next := annul; end if;
if r.d.inull = '1' then -- contention with JMPL
hold_pc := '1'; annul_current := '1'; annul_next := '0';
end if;
end if;
end if;
when FMT3 =>
case op3 is
when UMUL | SMUL | UMULCC | SMULCC =>
if MULEN and (MULTYPE /= 0) then mulstart := '1'; end if;
if MULEN and (MULTYPE = 0) then
case r.d.cnt is
when "00" =>
cnt := "01"; hold_pc := '1'; pv := '0'; mulstart := '1';
when "01" =>
if mulo.nready = '1' then cnt := "00";
else cnt := "01"; pv := '0'; hold_pc := '1'; end if;
when others => null;
end case;
end if;
when UDIV | SDIV | UDIVCC | SDIVCC =>
if DIVEN then
case r.d.cnt is
when "00" =>
cnt := "01"; hold_pc := '1'; pv := '0';
divstart := '1';
when "01" =>
if divo.nready = '1' then cnt := "00";
else cnt := "01"; pv := '0'; hold_pc := '1'; end if;
when others => null;
end case;
end if;
when TICC =>
if branch_true = '1' then ticc_exception := '1'; end if;
when RETT =>
rett_inst := '1'; --su := sregs.ps;
when JMPL =>
de_jmpl := '1';
when WRY =>
if PWRD1 then
if inst(29 downto 25) = "10011" then -- %ASR19
case r.d.cnt is
when "00" =>
pv := '0'; cnt := "00"; hold_pc := '1';
if r.x.ipend = '1' then cnt := "01"; end if;
when "01" =>
cnt := "00";
when others =>
end case;
end if;
end if;
when others => null;
end case;
when others => -- LDST
case r.d.cnt is
when "00" =>
if (op3(2) = '1') or (op3(1 downto 0) = "11") then -- ST/LDST/SWAP/LDD
cnt := "01"; hold_pc := '1'; pv := '0';
end if;
when "01" =>
if (op3(2 downto 0) = "111") or (op3(3 downto 0) = "1101") or
((CPEN or FPEN) and ((op3(5) & op3(2 downto 0)) = "1110"))
then -- LDD/STD/LDSTUB/SWAP
cnt := "10"; pv := '0'; hold_pc := '1';
else
cnt := "00";
end if;
when "10" =>
cnt := "00";
when others => null;
end case;
end case;
end if;
if ldlock = '1' then
cnt := r.d.cnt; annul_next := '0'; pv := '1';
end if;
hold_pc := (hold_pc or ldlock) and not annul_all;
if hold_pc = '1' then de_pc := r.d.pc; else de_pc := r.f.pc; end if;
annul_current := (annul_current or ldlock or annul_all);
ctrl_annul := r.d.annul or annul_all or annul_current;
pv := pv and not ((r.d.inull and not hold_pc) or annul_all);
jmpl_inst := de_jmpl and not annul_current;
annul_next := (r.d.inull and not hold_pc) or annul_next or annul_all;
if (annul_next = '1') or (rstn = '0') then
cnt := (others => '0');
end if;
de_hold_pc := hold_pc; de_branch := branch; de_annul := annul_next;
de_pv := pv; ctrl_pv := r.d.pv and
not ((r.d.annul and not r.d.pv) or annul_all or annul_current);
inull := (not rstn) or r.d.inull or hold_pc or annul_all;
end;
-- register write address generation
procedure rd_gen(r : registers; inst : word; wreg, ld : out std_ulogic;
rdo : out std_logic_vector(4 downto 0)) is
variable write_reg : std_ulogic;
variable op : std_logic_vector(1 downto 0);
variable op2 : std_logic_vector(2 downto 0);
variable op3 : std_logic_vector(5 downto 0);
variable rd : std_logic_vector(4 downto 0);
begin
op := inst(31 downto 30);
op2 := inst(24 downto 22);
op3 := inst(24 downto 19);
write_reg := '0'; rd := inst(29 downto 25); ld := '0';
case op is
when CALL =>
write_reg := '1'; rd := "01111"; -- CALL saves PC in r[15] (%o7)
when FMT2 =>
if (op2 = SETHI) then write_reg := '1'; end if;
when FMT3 =>
case op3 is
when UMUL | SMUL | UMULCC | SMULCC =>
if MULEN then
if (((mulo.nready = '1') and (r.d.cnt /= "00")) or (MULTYPE /= 0)) then
write_reg := '1';
end if;
else write_reg := '1'; end if;
when UDIV | SDIV | UDIVCC | SDIVCC =>
if DIVEN then
if (divo.nready = '1') and (r.d.cnt /= "00") then
write_reg := '1';
end if;
else write_reg := '1'; end if;
when RETT | WRPSR | WRY | WRWIM | WRTBR | TICC | FLUSH => null;
when FPOP1 | FPOP2 => null;
when CPOP1 | CPOP2 => null;
when others => write_reg := '1';
end case;
when others => -- LDST
ld := not op3(2);
if (op3(2) = '0') and not ((CPEN or FPEN) and (op3(5) = '1'))
then write_reg := '1'; end if;
case op3 is
when SWAP | SWAPA | LDSTUB | LDSTUBA =>
if r.d.cnt = "00" then write_reg := '1'; ld := '1'; end if;
when others => null;
end case;
if r.d.cnt = "01" then
case op3 is
when LDD | LDDA | LDDC | LDDF => rd(0) := '1';
when others =>
end case;
end if;
end case;
if (rd = "00000") then write_reg := '0'; end if;
wreg := write_reg; rdo := rd;
end;
-- immediate data generation
function imm_data (r : registers; insn : word)
return word is
variable immediate_data, inst : word;
begin
immediate_data := (others => '0'); inst := insn;
case inst(31 downto 30) is
when FMT2 =>
immediate_data := inst(21 downto 0) & "0000000000";
when others => -- LDST
immediate_data(31 downto 13) := (others => inst(12));
immediate_data(12 downto 0) := inst(12 downto 0);
end case;
return(immediate_data);
end;
-- read special registers
function get_spr (r : registers) return word is
variable spr : word;
begin
spr := (others => '0');
case r.e.ctrl.inst(24 downto 19) is
when RDPSR => spr(31 downto 5) := conv_std_logic_vector(IMPL,4) &
conv_std_logic_vector(VER,4) & r.m.icc & "000000" & r.w.s.ec & r.w.s.ef &
r.w.s.pil & r.e.su & r.w.s.ps & r.e.et;
spr(NWINLOG2-1 downto 0) := r.e.cwp;
when RDTBR => spr(31 downto 4) := r.w.s.tba & r.w.s.tt;
when RDWIM => spr(NWIN-1 downto 0) := r.w.s.wim;
when others =>
end case;
return(spr);
end;
-- immediate data select
function imm_select(inst : word) return boolean is
variable imm : boolean;
begin
imm := false;
case inst(31 downto 30) is
when FMT2 =>
case inst(24 downto 22) is
when SETHI => imm := true;
when others =>
end case;
when FMT3 =>
case inst(24 downto 19) is
when RDWIM | RDPSR | RDTBR => imm := true;
when others => if (inst(13) = '1') then imm := true; end if;
end case;
when LDST =>
if (inst(13) = '1') then imm := true; end if;
when others =>
end case;
return(imm);
end;
-- EXE operation
procedure alu_op(r : in registers; iop1, iop2 : in word; me_icc : std_logic_vector(3 downto 0);
my, ldbp : std_ulogic; aop1, aop2 : out word; aluop : out std_logic_vector(2 downto 0);
alusel : out std_logic_vector(1 downto 0); aluadd : out std_ulogic;
shcnt : out std_logic_vector(4 downto 0); sari, shleft, ymsb,
mulins, divins, mulstep, macins, ldbp2, invop2 : out std_ulogic) is
variable op : std_logic_vector(1 downto 0);
variable op2 : std_logic_vector(2 downto 0);
variable op3 : std_logic_vector(5 downto 0);
variable rd : std_logic_vector(4 downto 0);
variable icc : std_logic_vector(3 downto 0);
variable y0 : std_ulogic;
begin
op := r.a.ctrl.inst(31 downto 30);
op2 := r.a.ctrl.inst(24 downto 22);
op3 := r.a.ctrl.inst(24 downto 19);
aop1 := iop1; aop2 := iop2; ldbp2 := ldbp;
aluop := EXE_NOP; alusel := EXE_RES_MISC; aluadd := '1';
shcnt := iop2(4 downto 0); sari := '0'; shleft := '0'; invop2 := '0';
ymsb := iop1(0); mulins := '0'; divins := '0'; mulstep := '0';
macins := '0';
if r.e.ctrl.wy = '1' then y0 := my;
elsif r.m.ctrl.wy = '1' then y0 := r.m.y(0);
elsif r.x.ctrl.wy = '1' then y0 := r.x.y(0);
else y0 := r.w.s.y(0); end if;
if r.e.ctrl.wicc = '1' then icc := me_icc;
elsif r.m.ctrl.wicc = '1' then icc := r.m.icc;
elsif r.x.ctrl.wicc = '1' then icc := r.x.icc;
else icc := r.w.s.icc; end if;
case op is
when CALL =>
aluop := EXE_LINK;
when FMT2 =>
case op2 is
when SETHI => aluop := EXE_PASS2;
when others =>
end case;
when FMT3 =>
case op3 is
when IADD | ADDX | ADDCC | ADDXCC | TADDCC | TADDCCTV | SAVE | RESTORE |
TICC | JMPL | RETT => alusel := EXE_RES_ADD;
when ISUB | SUBX | SUBCC | SUBXCC | TSUBCC | TSUBCCTV =>
alusel := EXE_RES_ADD; aluadd := '0'; aop2 := not iop2; invop2 := '1';
when MULSCC => alusel := EXE_RES_ADD;
aop1 := (icc(3) xor icc(1)) & iop1(31 downto 1);
if y0 = '0' then aop2 := (others => '0'); ldbp2 := '0'; end if;
mulstep := '1';
when UMUL | UMULCC | SMUL | SMULCC =>
if MULEN then mulins := '1'; end if;
when UMAC | SMAC =>
if MACEN then mulins := '1'; macins := '1'; end if;
when UDIV | UDIVCC | SDIV | SDIVCC =>
if DIVEN then
aluop := EXE_DIV; alusel := EXE_RES_LOGIC; divins := '1';
end if;
when IAND | ANDCC => aluop := EXE_AND; alusel := EXE_RES_LOGIC;
when ANDN | ANDNCC => aluop := EXE_ANDN; alusel := EXE_RES_LOGIC;
when IOR | ORCC => aluop := EXE_OR; alusel := EXE_RES_LOGIC;
when ORN | ORNCC => aluop := EXE_ORN; alusel := EXE_RES_LOGIC;
when IXNOR | XNORCC => aluop := EXE_XNOR; alusel := EXE_RES_LOGIC;
when XORCC | IXOR | WRPSR | WRWIM | WRTBR | WRY =>
aluop := EXE_XOR; alusel := EXE_RES_LOGIC;
when RDPSR | RDTBR | RDWIM => aluop := EXE_SPR;
when RDY => aluop := EXE_RDY;
when ISLL => aluop := EXE_SLL; alusel := EXE_RES_SHIFT; shleft := '1';
shcnt := not iop2(4 downto 0); invop2 := '1';
when ISRL => aluop := EXE_SRL; alusel := EXE_RES_SHIFT;
when ISRA => aluop := EXE_SRA; alusel := EXE_RES_SHIFT; sari := iop1(31);
when FPOP1 | FPOP2 =>
when others =>
end case;
when others => -- LDST
case r.a.ctrl.cnt is
when "00" =>
alusel := EXE_RES_ADD;
when "01" =>
case op3 is
when LDD | LDDA | LDDC => alusel := EXE_RES_ADD;
when LDDF => alusel := EXE_RES_ADD;
when SWAP | SWAPA | LDSTUB | LDSTUBA => alusel := EXE_RES_ADD;
when STF | STDF =>
when others =>
aluop := EXE_PASS1;
if op3(2) = '1' then
if op3(1 downto 0) = "01" then aluop := EXE_STB;
elsif op3(1 downto 0) = "10" then aluop := EXE_STH; end if;
end if;
end case;
when "10" =>
aluop := EXE_PASS1;
if op3(2) = '1' then -- ST
if (op3(3) and not op3(1))= '1' then aluop := EXE_ONES; end if; -- LDSTUB/A
end if;
when others =>
end case;
end case;
end;
function ra_inull_gen(r, v : registers) return std_ulogic is
variable de_inull : std_ulogic;
begin
de_inull := '0';
if ((v.e.jmpl or v.e.ctrl.rett) and not v.e.ctrl.annul and not (r.e.jmpl and not r.e.ctrl.annul)) = '1' then de_inull := '1'; end if;
if ((v.a.jmpl or v.a.ctrl.rett) and not v.a.ctrl.annul and not (r.a.jmpl and not r.a.ctrl.annul)) = '1' then de_inull := '1'; end if;
return(de_inull);
end;
-- operand generation
procedure op_mux(r : in registers; rfd, ed, md, xd, im : in word;
rsel : in std_logic_vector(2 downto 0);
ldbp : out std_ulogic; d : out word) is
begin
ldbp := '0';
case rsel is
when "000" => d := rfd;
when "001" => d := ed;
when "010" => d := md; if lddel = 1 then ldbp := r.m.ctrl.ld; end if;
when "011" => d := xd;
when "100" => d := im;
when "101" => d := (others => '0');
when "110" => d := r.w.result;
when others => d := (others => '-');
end case;
end;
procedure op_find(r : in registers; ldchkra : std_ulogic; ldchkex : std_ulogic;
rs1 : std_logic_vector(4 downto 0); ra : rfatype; im : boolean; rfe : out std_ulogic;
osel : out std_logic_vector(2 downto 0); ldcheck : std_ulogic) is
begin
rfe := '0';
if im then osel := "100";
elsif rs1 = "00000" then osel := "101"; -- %g0
elsif ((r.a.ctrl.wreg and ldchkra) = '1') and (ra = r.a.ctrl.rd) then osel := "001";
elsif ((r.e.ctrl.wreg and ldchkex) = '1') and (ra = r.e.ctrl.rd) then osel := "010";
elsif r.m.ctrl.wreg = '1' and (ra = r.m.ctrl.rd) then osel := "011";
elsif (irfwt = 0) and r.x.ctrl.wreg = '1' and (ra = r.x.ctrl.rd) then osel := "110";
else osel := "000"; rfe := ldcheck; end if;
end;
-- generate carry-in for alu
procedure cin_gen(r : registers; me_cin : in std_ulogic; cin : out std_ulogic) is
variable op : std_logic_vector(1 downto 0);
variable op3 : std_logic_vector(5 downto 0);
variable ncin : std_ulogic;
begin
op := r.a.ctrl.inst(31 downto 30); op3 := r.a.ctrl.inst(24 downto 19);
if r.e.ctrl.wicc = '1' then ncin := me_cin;
else ncin := r.m.icc(0); end if;
cin := '0';
case op is
when FMT3 =>
case op3 is
when ISUB | SUBCC | TSUBCC | TSUBCCTV => cin := '1';
when ADDX | ADDXCC => cin := ncin;
when SUBX | SUBXCC => cin := not ncin;
when others => null;
end case;
when others => null;
end case;
end;
procedure logic_op(r : registers; aluin1, aluin2, mey : word;
ymsb : std_ulogic; logicres, y : out word) is
variable logicout : word;
begin
case r.e.aluop is
when EXE_AND => logicout := aluin1 and aluin2;
when EXE_ANDN => logicout := aluin1 and not aluin2;
when EXE_OR => logicout := aluin1 or aluin2;
when EXE_ORN => logicout := aluin1 or not aluin2;
when EXE_XOR => logicout := aluin1 xor aluin2;
when EXE_XNOR => logicout := aluin1 xor not aluin2;
when EXE_DIV =>
if DIVEN then logicout := aluin2;
else logicout := (others => '-'); end if;
when others => logicout := (others => '-');
end case;
if (r.e.ctrl.wy and r.e.mulstep) = '1' then
y := ymsb & r.m.y(31 downto 1);
elsif r.e.ctrl.wy = '1' then y := logicout;
elsif r.m.ctrl.wy = '1' then y := mey;
elsif MACPIPE and (r.x.mac = '1') then y := mulo.result(63 downto 32);
elsif r.x.ctrl.wy = '1' then y := r.x.y;
else y := r.w.s.y; end if;
logicres := logicout;
end;
procedure misc_op(r : registers; wpr : watchpoint_registers;
aluin1, aluin2, ldata, mey : word;
mout, edata : out word) is
variable miscout, bpdata, stdata : word;
variable wpi : integer;
begin
wpi := 0; miscout := r.e.ctrl.pc(31 downto 2) & "00";
edata := aluin1; bpdata := aluin1;
if ((r.x.ctrl.wreg and r.x.ctrl.ld and not r.x.ctrl.annul) = '1') and
(r.x.ctrl.rd = r.e.ctrl.rd) and (r.e.ctrl.inst(31 downto 30) = LDST) and
(r.e.ctrl.cnt /= "10")
then bpdata := ldata; end if;
case r.e.aluop is
when EXE_STB => miscout := bpdata(7 downto 0) & bpdata(7 downto 0) &
bpdata(7 downto 0) & bpdata(7 downto 0);
edata := miscout;
when EXE_STH => miscout := bpdata(15 downto 0) & bpdata(15 downto 0);
edata := miscout;
when EXE_PASS1 => miscout := bpdata; edata := miscout;
when EXE_PASS2 => miscout := aluin2;
when EXE_ONES => miscout := (others => '1');
edata := miscout;
when EXE_RDY =>
if MULEN and (r.m.ctrl.wy = '1') then miscout := mey;
else miscout := r.m.y; end if;
if (NWP > 0) and (r.e.ctrl.inst(18 downto 17) = "11") then
wpi := conv_integer(r.e.ctrl.inst(16 downto 15));
if r.e.ctrl.inst(14) = '0' then miscout := wpr(wpi).addr & '0' & wpr(wpi).exec;
else miscout := wpr(wpi).mask & wpr(wpi).load & wpr(wpi).store; end if;
end if;
if (r.e.ctrl.inst(18 downto 17) = "10") and (r.e.ctrl.inst(14) = '1') then --%ASR17
miscout := asr17_gen(r);
end if;
if MACEN then
if (r.e.ctrl.inst(18 downto 14) = "10010") then --%ASR18
if ((r.m.mac = '1') and not MACPIPE) or ((r.x.mac = '1') and MACPIPE) then
miscout := mulo.result(31 downto 0); -- data forward of asr18
else miscout := r.w.s.asr18; end if;
else
if ((r.m.mac = '1') and not MACPIPE) or ((r.x.mac = '1') and MACPIPE) then
miscout := mulo.result(63 downto 32); -- data forward Y
end if;
end if;
end if;
when EXE_SPR =>
miscout := get_spr(r);
when others => null;
end case;
mout := miscout;
end;
procedure alu_select(r : registers; addout : std_logic_vector(32 downto 0);
op1, op2 : word; shiftout, logicout, miscout : word; res : out word;
me_icc : std_logic_vector(3 downto 0);
icco : out std_logic_vector(3 downto 0); divz : out std_ulogic) is
variable op : std_logic_vector(1 downto 0);
variable op3 : std_logic_vector(5 downto 0);
variable icc : std_logic_vector(3 downto 0);
variable aluresult : word;
begin
op := r.e.ctrl.inst(31 downto 30); op3 := r.e.ctrl.inst(24 downto 19);
icc := (others => '0');
case r.e.alusel is
when EXE_RES_ADD =>
aluresult := addout(32 downto 1);
if r.e.aluadd = '0' then
icc(0) := ((not op1(31)) and not op2(31)) or -- Carry
(addout(32) and ((not op1(31)) or not op2(31)));
icc(1) := (op1(31) and (op2(31)) and not addout(32)) or -- Overflow
(addout(32) and (not op1(31)) and not op2(31));
else
icc(0) := (op1(31) and op2(31)) or -- Carry
((not addout(32)) and (op1(31) or op2(31)));
icc(1) := (op1(31) and op2(31) and not addout(32)) or -- Overflow
(addout(32) and (not op1(31)) and (not op2(31)));
end if;
if notag = 0 then
case op is
when FMT3 =>
case op3 is
when TADDCC | TADDCCTV =>
icc(1) := op1(0) or op1(1) or op2(0) or op2(1) or icc(1);
when TSUBCC | TSUBCCTV =>
icc(1) := op1(0) or op1(1) or (not op2(0)) or (not op2(1)) or icc(1);
when others => null;
end case;
when others => null;
end case;
end if;
if aluresult = zero32 then icc(2) := '1'; end if;
when EXE_RES_SHIFT => aluresult := shiftout;
when EXE_RES_LOGIC => aluresult := logicout;
if aluresult = zero32 then icc(2) := '1'; end if;
when others => aluresult := miscout;
end case;
if r.e.jmpl = '1' then aluresult := r.e.ctrl.pc(31 downto 2) & "00"; end if;
icc(3) := aluresult(31); divz := icc(2);
if r.e.ctrl.wicc = '1' then
if (op = FMT3) and (op3 = WRPSR) then icco := logicout(23 downto 20);
else icco := icc; end if;
elsif r.m.ctrl.wicc = '1' then icco := me_icc;
elsif r.x.ctrl.wicc = '1' then icco := r.x.icc;
else icco := r.w.s.icc; end if;
res := aluresult;
end;
procedure dcache_gen(r, v : registers; dci : out dc_in_type;
link_pc, jump, force_a2, load : out std_ulogic) is
variable op : std_logic_vector(1 downto 0);
variable op3 : std_logic_vector(5 downto 0);
variable su : std_ulogic;
begin
op := r.e.ctrl.inst(31 downto 30); op3 := r.e.ctrl.inst(24 downto 19);
dci.signed := '0'; dci.lock := '0'; dci.dsuen := '0'; dci.size := SZWORD;
if op = LDST then
case op3 is
when LDUB | LDUBA => dci.size := SZBYTE;
when LDSTUB | LDSTUBA => dci.size := SZBYTE; dci.lock := '1';
when LDUH | LDUHA => dci.size := SZHALF;
when LDSB | LDSBA => dci.size := SZBYTE; dci.signed := '1';
when LDSH | LDSHA => dci.size := SZHALF; dci.signed := '1';
when LD | LDA | LDF | LDC => dci.size := SZWORD;
when SWAP | SWAPA => dci.size := SZWORD; dci.lock := '1';
when LDD | LDDA | LDDF | LDDC => dci.size := SZDBL;
when STB | STBA => dci.size := SZBYTE;
when STH | STHA => dci.size := SZHALF;
when ST | STA | STF => dci.size := SZWORD;
when ISTD | STDA => dci.size := SZDBL;
when STDF | STDFQ => if FPEN then dci.size := SZDBL; end if;
when STDC | STDCQ => if CPEN then dci.size := SZDBL; end if;
when others => dci.size := SZWORD; dci.lock := '0'; dci.signed := '0';
end case;
end if;
link_pc := '0'; jump:= '0'; force_a2 := '0'; load := '0';
dci.write := '0'; dci.enaddr := '0'; dci.read := not op3(2);
-- load/store control decoding
if (r.e.ctrl.annul = '0') then
case op is
when CALL => link_pc := '1';
when FMT3 =>
case op3 is
when JMPL => jump := '1'; link_pc := '1';
when RETT => jump := '1';
when others => null;
end case;
when LDST =>
case r.e.ctrl.cnt is
when "00" =>
dci.read := op3(3) or not op3(2); -- LD/LDST/SWAP
load := op3(3) or not op3(2);
dci.enaddr := '1';
when "01" =>
force_a2 := not op3(2); -- LDD
load := not op3(2); dci.enaddr := not op3(2);
if op3(3 downto 2) = "01" then -- ST/STD
dci.write := '1';
end if;
if op3(3 downto 2) = "11" then -- LDST/SWAP
dci.enaddr := '1';
end if;
when "10" => -- STD/LDST/SWAP
dci.write := '1';
when others => null;
end case;
if (r.e.ctrl.trap or (v.x.ctrl.trap and not v.x.ctrl.annul)) = '1' then
dci.enaddr := '0';
end if;
when others => null;
end case;
end if;
if ((r.x.ctrl.rett and not r.x.ctrl.annul) = '1') then su := r.w.s.ps;
else su := r.w.s.s; end if;
if su = '1' then dci.asi := "00001011"; else dci.asi := "00001010"; end if;
if (op3(4) = '1') and ((op3(5) = '0') or not CPEN) then
dci.asi := r.e.ctrl.inst(12 downto 5);
end if;
end;
procedure fpstdata(r : in registers; edata, eres : in word; fpstdata : in std_logic_vector(31 downto 0);
edata2, eres2 : out word) is
variable op : std_logic_vector(1 downto 0);
variable op3 : std_logic_vector(5 downto 0);
begin
edata2 := edata; eres2 := eres;
op := r.e.ctrl.inst(31 downto 30); op3 := r.e.ctrl.inst(24 downto 19);
if FPEN then
if FPEN and (op = LDST) and ((op3(5 downto 4) & op3(2)) = "101") and (r.e.ctrl.cnt /= "00") then
edata2 := fpstdata; eres2 := fpstdata;
end if;
end if;
end;
function ld_align(data : dcdtype; set : std_logic_vector(DSETMSB downto 0);
size, laddr : std_logic_vector(1 downto 0); signed : std_ulogic) return word is
variable align_data, rdata : word;
begin
align_data := data(conv_integer(set)); rdata := (others => '0');
case size is
when "00" => -- byte read
case laddr is
when "00" =>
rdata(7 downto 0) := align_data(31 downto 24);
if signed = '1' then rdata(31 downto 8) := (others => align_data(31)); end if;
when "01" =>
rdata(7 downto 0) := align_data(23 downto 16);
if signed = '1' then rdata(31 downto 8) := (others => align_data(23)); end if;
when "10" =>
rdata(7 downto 0) := align_data(15 downto 8);
if signed = '1' then rdata(31 downto 8) := (others => align_data(15)); end if;
when others =>
rdata(7 downto 0) := align_data(7 downto 0);
if signed = '1' then rdata(31 downto 8) := (others => align_data(7)); end if;
end case;
when "01" => -- half-word read
if laddr(1) = '1' then
rdata(15 downto 0) := align_data(15 downto 0);
if signed = '1' then rdata(31 downto 15) := (others => align_data(15)); end if;
else
rdata(15 downto 0) := align_data(31 downto 16);
if signed = '1' then rdata(31 downto 15) := (others => align_data(31)); end if;
end if;
when others => -- single and double word read
rdata := align_data;
end case;
return(rdata);
end;
procedure mem_trap(r : registers; wpr : watchpoint_registers;
annul, holdn : in std_ulogic;
trapout, iflush, nullify, werrout : out std_ulogic;
tt : out std_logic_vector(5 downto 0)) is
variable cwp : std_logic_vector(NWINLOG2-1 downto 0);
variable cwpx : std_logic_vector(5 downto NWINLOG2);
variable op : std_logic_vector(1 downto 0);
variable op2 : std_logic_vector(2 downto 0);
variable op3 : std_logic_vector(5 downto 0);
variable nalign_d : std_ulogic;
variable trap, werr : std_ulogic;
begin
op := r.m.ctrl.inst(31 downto 30); op2 := r.m.ctrl.inst(24 downto 22);
op3 := r.m.ctrl.inst(24 downto 19);
cwpx := r.m.result(5 downto NWINLOG2); cwpx(5) := '0';
iflush := '0'; trap := r.m.ctrl.trap; nullify := annul;
tt := r.m.ctrl.tt; werr := (dco.werr or r.m.werr) and not r.w.s.dwt;
nalign_d := r.m.nalign or r.m.result(2);
if ((annul or trap) /= '1') and (r.m.ctrl.pv = '1') then
if (werr and holdn) = '1' then
trap := '1'; tt := TT_DSEX; werr := '0';
if op = LDST then nullify := '1'; end if;
end if;
end if;
if ((annul or trap) /= '1') then
case op is
when FMT2 =>
case op2 is
when FBFCC =>
if FPEN and (fpo.exc = '1') then trap := '1'; tt := TT_FPEXC; end if;
when CBCCC =>
if CPEN and (cpo.exc = '1') then trap := '1'; tt := TT_CPEXC; end if;
when others => null;
end case;
when FMT3 =>
case op3 is
when WRPSR =>
if (orv(cwpx) = '1') then trap := '1'; tt := TT_IINST; end if;
when UDIV | SDIV | UDIVCC | SDIVCC =>
if DIVEN then
if r.m.divz = '1' then trap := '1'; tt := TT_DIV; end if;
end if;
when JMPL | RETT =>
if r.m.nalign = '1' then trap := '1'; tt := TT_UNALA; end if;
when TADDCCTV | TSUBCCTV =>
if (notag = 0) and (r.m.icc(1) = '1') then
trap := '1'; tt := TT_TAG;
end if;
when FLUSH => iflush := '1';
when FPOP1 | FPOP2 =>
if FPEN and (fpo.exc = '1') then trap := '1'; tt := TT_FPEXC; end if;
when CPOP1 | CPOP2 =>
if CPEN and (cpo.exc = '1') then trap := '1'; tt := TT_CPEXC; end if;
when others => null;
end case;
when LDST =>
if r.m.ctrl.cnt = "00" then
case op3 is
when LDDF | STDF | STDFQ =>
if FPEN then
if nalign_d = '1' then
trap := '1'; tt := TT_UNALA; nullify := '1';
elsif (fpo.exc and r.m.ctrl.pv) = '1'
then trap := '1'; tt := TT_FPEXC; nullify := '1'; end if;
end if;
when LDDC | STDC | STDCQ =>
if CPEN then
if nalign_d = '1' then
trap := '1'; tt := TT_UNALA; nullify := '1';
elsif ((cpo.exc and r.m.ctrl.pv) = '1')
then trap := '1'; tt := TT_CPEXC; nullify := '1'; end if;
end if;
when LDD | ISTD | LDDA | STDA =>
if r.m.result(2 downto 0) /= "000" then
trap := '1'; tt := TT_UNALA; nullify := '1';
end if;
when LDF | LDFSR | STFSR | STF =>
if FPEN and (r.m.nalign = '1') then
trap := '1'; tt := TT_UNALA; nullify := '1';
elsif FPEN and ((fpo.exc and r.m.ctrl.pv) = '1')
then trap := '1'; tt := TT_FPEXC; nullify := '1'; end if;
when LDC | LDCSR | STCSR | STC =>
if CPEN and (r.m.nalign = '1') then
trap := '1'; tt := TT_UNALA; nullify := '1';
elsif CPEN and ((cpo.exc and r.m.ctrl.pv) = '1')
then trap := '1'; tt := TT_CPEXC; nullify := '1'; end if;
when LD | LDA | ST | STA | SWAP | SWAPA =>
if r.m.result(1 downto 0) /= "00" then
trap := '1'; tt := TT_UNALA; nullify := '1';
end if;
when LDUH | LDUHA | LDSH | LDSHA | STH | STHA =>
if r.m.result(0) /= '0' then
trap := '1'; tt := TT_UNALA; nullify := '1';
end if;
when others => null;
end case;
for i in 1 to NWP loop
if ((((wpr(i-1).load and not op3(2)) or (wpr(i-1).store and op3(2))) = '1') and
(((wpr(i-1).addr xor r.m.result(31 downto 2)) and wpr(i-1).mask) = zero32(31 downto 2)))
then trap := '1'; tt := TT_WATCH; nullify := '1'; end if;
end loop;
end if;
when others => null;
end case;
end if;
if (rstn = '0') or (r.x.rstate = dsu2) then werr := '0'; end if;
trapout := trap; werrout := werr;
end;
procedure irq_trap(r : in registers;
ir : in irestart_register;
irl : in std_logic_vector(3 downto 0);
annul : in std_ulogic;
pv : in std_ulogic;
trap : in std_ulogic;
tt : in std_logic_vector(5 downto 0);
nullify : in std_ulogic;
irqen : out std_ulogic;
irqen2 : out std_ulogic;
nullify2 : out std_ulogic;
trap2, ipend : out std_ulogic;
tt2 : out std_logic_vector(5 downto 0)) is
variable op : std_logic_vector(1 downto 0);
variable op3 : std_logic_vector(5 downto 0);
variable pend : std_ulogic;
begin
nullify2 := nullify; trap2 := trap; tt2 := tt;
op := r.m.ctrl.inst(31 downto 30); op3 := r.m.ctrl.inst(24 downto 19);
irqen := '1'; irqen2 := r.m.irqen;
if (annul or trap) = '0' then
if ((op = FMT3) and (op3 = WRPSR)) then irqen := '0'; end if;
end if;
if (irl = "1111") or (irl > r.w.s.pil) then
pend := r.m.irqen and r.m.irqen2 and r.w.s.et and not ir.pwd;
else pend := '0'; end if;
ipend := pend;
if ((not annul) and pv and (not trap) and pend) = '1' then
trap2 := '1'; tt2 := "01" & irl;
if op = LDST then nullify2 := '1'; end if;
end if;
end;
procedure irq_intack(r : in registers; holdn : in std_ulogic; intack: out std_ulogic) is
begin
intack := '0';
if r.x.rstate = trap then
if r.w.s.tt(7 downto 4) = "0001" then intack := '1'; end if;
end if;
end;
-- write special registers
procedure sp_write (r : registers; wpr : watchpoint_registers;
s : out special_register_type; vwpr : out watchpoint_registers) is
variable op : std_logic_vector(1 downto 0);
variable op2 : std_logic_vector(2 downto 0);
variable op3 : std_logic_vector(5 downto 0);
variable rd : std_logic_vector(4 downto 0);
variable i : integer range 0 to 3;
begin
op := r.x.ctrl.inst(31 downto 30);
op2 := r.x.ctrl.inst(24 downto 22);
op3 := r.x.ctrl.inst(24 downto 19);
s := r.w.s;
rd := r.x.ctrl.inst(29 downto 25);
vwpr := wpr;
case op is
when FMT3 =>
case op3 is
when WRY =>
if rd = "00000" then
s.y := r.x.result;
elsif MACEN and (rd = "10010") then
s.asr18 := r.x.result;
elsif (rd = "10001") then
s.dwt := r.x.result(14);
if (svt = 1) then s.svt := r.x.result(13); end if;
elsif rd(4 downto 3) = "11" then -- %ASR24 - %ASR31
case rd(2 downto 0) is
when "000" =>
vwpr(0).addr := r.x.result(31 downto 2);
vwpr(0).exec := r.x.result(0);
when "001" =>
vwpr(0).mask := r.x.result(31 downto 2);
vwpr(0).load := r.x.result(1);
vwpr(0).store := r.x.result(0);
when "010" =>
vwpr(1).addr := r.x.result(31 downto 2);
vwpr(1).exec := r.x.result(0);
when "011" =>
vwpr(1).mask := r.x.result(31 downto 2);
vwpr(1).load := r.x.result(1);
vwpr(1).store := r.x.result(0);
when "100" =>
vwpr(2).addr := r.x.result(31 downto 2);
vwpr(2).exec := r.x.result(0);
when "101" =>
vwpr(2).mask := r.x.result(31 downto 2);
vwpr(2).load := r.x.result(1);
vwpr(2).store := r.x.result(0);
when "110" =>
vwpr(3).addr := r.x.result(31 downto 2);
vwpr(3).exec := r.x.result(0);
when others => -- "111"
vwpr(3).mask := r.x.result(31 downto 2);
vwpr(3).load := r.x.result(1);
vwpr(3).store := r.x.result(0);
end case;
end if;
when WRPSR =>
s.cwp := r.x.result(NWINLOG2-1 downto 0);
s.icc := r.x.result(23 downto 20);
s.ec := r.x.result(13);
if FPEN then s.ef := r.x.result(12); end if;
s.pil := r.x.result(11 downto 8);
s.s := r.x.result(7);
s.ps := r.x.result(6);
s.et := r.x.result(5);
when WRWIM =>
s.wim := r.x.result(NWIN-1 downto 0);
when WRTBR =>
s.tba := r.x.result(31 downto 12);
when SAVE =>
if (not CWPOPT) and (r.w.s.cwp = CWPMIN) then s.cwp := CWPMAX;
else s.cwp := r.w.s.cwp - 1 ; end if;
when RESTORE =>
if (not CWPOPT) and (r.w.s.cwp = CWPMAX) then s.cwp := CWPMIN;
else s.cwp := r.w.s.cwp + 1; end if;
when RETT =>
if (not CWPOPT) and (r.w.s.cwp = CWPMAX) then s.cwp := CWPMIN;
else s.cwp := r.w.s.cwp + 1; end if;
s.s := r.w.s.ps;
s.et := '1';
when others => null;
end case;
when others => null;
end case;
if r.x.ctrl.wicc = '1' then s.icc := r.x.icc; end if;
if r.x.ctrl.wy = '1' then s.y := r.x.y; end if;
if MACPIPE and (r.x.mac = '1') then
s.asr18 := mulo.result(31 downto 0);
s.y := mulo.result(63 downto 32);
end if;
end;
function npc_find (r : registers) return std_logic_vector is
variable npc : std_logic_vector(2 downto 0);
begin
npc := "011";
if r.m.ctrl.pv = '1' then npc := "000";
elsif r.e.ctrl.pv = '1' then npc := "001";
elsif r.a.ctrl.pv = '1' then npc := "010";
elsif r.d.pv = '1' then npc := "011";
elsif v8 /= 0 then npc := "100"; end if;
return(npc);
end;
function npc_gen (r : registers) return word is
variable npc : std_logic_vector(31 downto 0);
begin
npc := r.a.ctrl.pc(31 downto 2) & "00";
case r.x.npc is
when "000" => npc(31 downto 2) := r.x.ctrl.pc(31 downto 2);
when "001" => npc(31 downto 2) := r.m.ctrl.pc(31 downto 2);
when "010" => npc(31 downto 2) := r.e.ctrl.pc(31 downto 2);
when "011" => npc(31 downto 2) := r.a.ctrl.pc(31 downto 2);
when others =>
if v8 /= 0 then npc(31 downto 2) := r.d.pc(31 downto 2); end if;
end case;
return(npc);
end;
procedure mul_res(r : registers; asr18in : word; result, y, asr18 : out word;
icc : out std_logic_vector(3 downto 0)) is
variable op : std_logic_vector(1 downto 0);
variable op3 : std_logic_vector(5 downto 0);
begin
op := r.m.ctrl.inst(31 downto 30); op3 := r.m.ctrl.inst(24 downto 19);
result := r.m.result; y := r.m.y; icc := r.m.icc; asr18 := asr18in;
case op is
when FMT3 =>
case op3 is
when UMUL | SMUL =>
if MULEN then
result := mulo.result(31 downto 0);
y := mulo.result(63 downto 32);
end if;
when UMULCC | SMULCC =>
if MULEN then
result := mulo.result(31 downto 0); icc := mulo.icc;
y := mulo.result(63 downto 32);
end if;
when UMAC | SMAC =>
if MACEN and not MACPIPE then
result := mulo.result(31 downto 0);
asr18 := mulo.result(31 downto 0);
y := mulo.result(63 downto 32);
end if;
when UDIV | SDIV =>
if DIVEN then
result := divo.result(31 downto 0);
end if;
when UDIVCC | SDIVCC =>
if DIVEN then
result := divo.result(31 downto 0); icc := divo.icc;
end if;
when others => null;
end case;
when others => null;
end case;
end;
function powerdwn(r : registers; trap : std_ulogic; rp : pwd_register_type) return std_ulogic is
variable op : std_logic_vector(1 downto 0);
variable op3 : std_logic_vector(5 downto 0);
variable rd : std_logic_vector(4 downto 0);
variable pd : std_ulogic;
begin
op := r.x.ctrl.inst(31 downto 30);
op3 := r.x.ctrl.inst(24 downto 19);
rd := r.x.ctrl.inst(29 downto 25);
pd := '0';
if (not (r.x.ctrl.annul or trap) and r.x.ctrl.pv) = '1' then
if ((op = FMT3) and (op3 = WRY) and (rd = "10011")) then pd := '1'; end if;
pd := pd or rp.pwd;
end if;
return(pd);
end;
signal dummy : std_ulogic;
signal cpu_index : std_logic_vector(3 downto 0);
signal disasen : std_ulogic;
-- Signals used for tracking if a handler fired and which one
signal dfp_trap_vector : std_logic_vector(131 downto 0);
signal dfp_trap_mem : std_logic_vector(131 downto 0);
signal or_reduce_1 : std_logic;
signal handlerTrap : std_ulogic;
SIGNAL hackStateM1 : std_logic;
-- Signals that serve as shadow signals for variables used in the pairs
signal V_A_ET_shadow : STD_ULOGIC;
signal EX_ADD_RES32DOWNTO34DOWNTO3_shadow : STD_LOGIC_VECTOR(4 downto 3);
signal ICNT_shadow : STD_ULOGIC;
signal EX_OP1_shadow : WORD;
signal V_M_CTRL_PC_shadow : PCTYPE;
signal V_E_CTRL_PC3DOWNTO2_shadow : STD_LOGIC_VECTOR(3 downto 2);
signal DE_REN1_shadow : STD_ULOGIC;
signal DE_INST_shadow : WORD;
signal V_A_CTRL_CNT_shadow : OP_TYPE;
signal V_F_PC3DOWNTO2_shadow : STD_LOGIC_VECTOR(3 downto 2);
signal V_W_S_TT_shadow : STD_LOGIC_VECTOR(7 downto 0);
signal V_X_RESULT6DOWNTO0_shadow : STD_LOGIC_VECTOR(6 downto 0);
signal EX_JUMP_ADDRESS3DOWNTO2_shadow : STD_LOGIC_VECTOR(3 downto 2);
signal V_E_ALUCIN_shadow : STD_ULOGIC;
signal V_D_PC3DOWNTO2_shadow : STD_LOGIC_VECTOR(3 downto 2);
signal V_A_CTRL_PV_shadow : STD_ULOGIC;
signal V_E_CTRL_shadow : PIPELINE_CTRL_TYPE;
signal V_M_CTRL_shadow : PIPELINE_CTRL_TYPE;
signal V_M_RESULT1DOWNTO0_shadow : STD_LOGIC_VECTOR(1 downto 0);
signal V_X_Y7DOWNTO0_shadow : STD_LOGIC_VECTOR(7 downto 0);
signal EX_SHCNT_shadow : ASI_TYPE;
signal V_X_CTRL_ANNUL_shadow : STD_ULOGIC;
signal V_M_DCI_SIZE_shadow : OP_TYPE;
signal V_X_MEXC_shadow : STD_ULOGIC;
signal TBUFCNTX_shadow : STD_LOGIC_VECTOR(6 downto 0);
signal V_A_CTRL_WY_shadow : STD_ULOGIC;
signal NPC_shadow : PCTYPE;
signal V_D_INST024_shadow : STD_LOGIC;
signal V_A_MULSTART_shadow : STD_ULOGIC;
signal V_M_CTRL_TT3DOWNTO0_shadow : STD_LOGIC_VECTOR(3 downto 0);
signal XC_VECTT3DOWNTO0_shadow : STD_LOGIC_VECTOR(3 downto 0);
signal V_E_CTRL_TT_shadow : OP3_TYPE;
signal DSIGN_shadow : STD_ULOGIC;
signal V_E_CTRL_ANNUL_shadow : STD_ULOGIC;
signal EX_JUMP_ADDRESS_shadow : PCTYPE;
signal V_A_CTRL_PC31DOWNTO12_shadow : STD_LOGIC_VECTOR(31 downto 12);
signal V_A_RFE1_shadow : STD_ULOGIC;
signal V_W_WA_shadow : RFATYPE;
signal V_X_ANNUL_ALL_shadow : STD_ULOGIC;
signal EX_YMSB_shadow : STD_ULOGIC;
signal EX_ADD_RES_shadow : STD_LOGIC_VECTOR(32 downto 0);
signal VIR_ADDR_shadow : PCTYPE;
signal EX_JUMP_ADDRESS31DOWNTO12_shadow : STD_LOGIC_VECTOR(31 downto 12);
signal V_W_S_CWP_shadow : CWPTYPE;
signal V_D_INST0_shadow : STD_LOGIC_VECTOR(31 downto 0);
signal V_A_CTRL_ANNUL_shadow : STD_ULOGIC;
signal VP_PWD_shadow : STD_ULOGIC;
signal V_M_CTRL_RD6DOWNTO0_shadow : STD_LOGIC_VECTOR(6 downto 0);
signal V_X_DATA00_shadow : STD_LOGIC;
signal V_M_CTRL_RETT_shadow : STD_ULOGIC;
signal V_X_CTRL_RETT_shadow : STD_ULOGIC;
signal V_X_CTRL_PC31DOWNTO12_shadow : STD_LOGIC_VECTOR(31 downto 12);
signal V_W_S_PS_shadow : STD_ULOGIC;
signal V_X_CTRL_TT_shadow : OP3_TYPE;
signal V_D_STEP_shadow : STD_ULOGIC;
signal V_X_CTRL_WICC_shadow : STD_ULOGIC;
signal VIR_ADDR31DOWNTO2_shadow : STD_LOGIC_VECTOR(31 downto 2);
signal V_M_CTRL_RD7DOWNTO0_shadow : STD_LOGIC_VECTOR(7 downto 0);
signal V_X_RESULT_shadow : WORD;
signal V_D_CNT_shadow : OP_TYPE;
signal XC_VECTT_shadow : STD_LOGIC_VECTOR(7 downto 0);
signal EX_ADD_RES32DOWNTO3_shadow : STD_LOGIC_VECTOR(32 downto 3);
signal V_W_S_EF_shadow : STD_ULOGIC;
signal V_A_CTRL_PC31DOWNTO2_shadow : STD_LOGIC_VECTOR(31 downto 2);
signal V_X_DATA04DOWNTO0_shadow : STD_LOGIC_VECTOR(4 downto 0);
signal V_X_DCI_SIGNED_shadow : STD_ULOGIC;
signal V_M_NALIGN_shadow : STD_ULOGIC;
signal DIAGDATA_shadow : WORD;
signal XC_WREG_shadow : STD_ULOGIC;
signal V_A_RFA2_shadow : RFATYPE;
signal V_E_CTRL_PC31DOWNTO12_shadow : STD_LOGIC_VECTOR(31 downto 12);
signal EX_ADD_RES32DOWNTO332DOWNTO13_shadow : STD_LOGIC_VECTOR(32 downto 13);
signal EX_OP231_shadow : STD_LOGIC;
signal V_X_ICC_shadow : STD_LOGIC_VECTOR(3 downto 0);
signal XC_TRAP_ADDRESS31DOWNTO4_shadow : STD_LOGIC_VECTOR(31 downto 4);
signal V_A_SU_shadow : STD_ULOGIC;
signal V_E_OP2_shadow : WORD;
signal EX_FORCE_A2_shadow : STD_ULOGIC;
signal V_E_CTRL_PC31DOWNTO2_shadow : STD_LOGIC_VECTOR(31 downto 2);
signal V_E_CTRL_PC31DOWNTO4_shadow : STD_LOGIC_VECTOR(31 downto 4);
signal V_E_OP131_shadow : STD_LOGIC;
signal V_X_DCI_shadow : DC_IN_TYPE;
signal V_E_CTRL_WICC_shadow : STD_ULOGIC;
signal EX_OP13_shadow : STD_LOGIC;
signal V_F_PC31DOWNTO12_shadow : STD_LOGIC_VECTOR(31 downto 12);
signal V_E_CTRL_INST_shadow : WORD;
signal V_E_CTRL_LD_shadow : STD_ULOGIC;
signal V_M_SU_shadow : STD_ULOGIC;
signal V_E_SARI_shadow : STD_ULOGIC;
signal V_E_ET_shadow : STD_ULOGIC;
signal V_M_CTRL_PV_shadow : STD_ULOGIC;
signal V_D_INST020_shadow : STD_LOGIC;
signal VDSU_CRDY2_shadow : STD_LOGIC;
signal MUL_OP2_shadow : WORD;
signal XC_EXCEPTION_shadow : STD_ULOGIC;
signal V_E_OP1_shadow : WORD;
signal VP_ERROR_shadow : STD_ULOGIC;
signal V_M_DCI_SIGNED_shadow : STD_ULOGIC;
signal V_D_PC31DOWNTO12_shadow : STD_LOGIC_VECTOR(31 downto 12);
signal MUL_OP231_shadow : STD_LOGIC;
signal XC_TRAP_ADDRESS31DOWNTO2_shadow : STD_LOGIC_VECTOR(31 downto 2);
signal V_M_CTRL_PC3DOWNTO2_shadow : STD_LOGIC_VECTOR(3 downto 2);
signal V_M_DCI_shadow : DC_IN_TYPE;
signal EX_OP23_shadow : STD_LOGIC;
signal V_X_CTRL_RD6DOWNTO0_shadow : STD_LOGIC_VECTOR(6 downto 0);
signal V_X_CTRL_TRAP_shadow : STD_ULOGIC;
signal TBUFI_WRITE_shadow : STD_LOGIC_VECTOR(3 downto 0);
signal V_A_DIVSTART_shadow : STD_ULOGIC;
signal V_X_RESULT6DOWNTO03DOWNTO0_shadow : STD_LOGIC_VECTOR(3 downto 0);
signal VDSU_TT_shadow : STD_LOGIC_VECTOR(7 downto 0);
signal EX_ADD_RES32DOWNTO332DOWNTO5_shadow : STD_LOGIC_VECTOR(32 downto 5);
signal V_X_CTRL_CNT_shadow : OP_TYPE;
signal V_E_YMSB_shadow : STD_ULOGIC;
signal EX_ADD_RES32DOWNTO330DOWNTO11_shadow : STD_LOGIC_VECTOR(30 downto 11);
signal V_A_RFE2_shadow : STD_ULOGIC;
signal V_E_OP13_shadow : STD_LOGIC;
signal V_A_CWP_shadow : CWPTYPE;
signal ME_SIZE_shadow : OP_TYPE;
signal V_X_MAC_shadow : STD_ULOGIC;
signal V_D_INST04DOWNTO0_shadow : STD_LOGIC_VECTOR(4 downto 0);
signal V_M_CTRL_INST_shadow : WORD;
signal VIR_ADDR31DOWNTO4_shadow : STD_LOGIC_VECTOR(31 downto 4);
signal V_A_CTRL_INST20_shadow : STD_LOGIC;
signal DE_REN2_shadow : STD_ULOGIC;
signal V_E_CTRL_PV_shadow : STD_ULOGIC;
signal V_E_MAC_shadow : STD_ULOGIC;
signal V_X_CTRL_TT3DOWNTO0_shadow : STD_LOGIC_VECTOR(3 downto 0);
signal EX_ADD_RES3_shadow : STD_LOGIC;
signal V_X_CTRL_INST_shadow : WORD;
signal V_M_CTRL_PC31DOWNTO2_shadow : STD_LOGIC_VECTOR(31 downto 2);
signal V_W_S_ET_shadow : STD_ULOGIC;
signal V_M_CTRL_CNT_shadow : OP_TYPE;
signal V_M_CTRL_ANNUL_shadow : STD_ULOGIC;
signal DE_INST19_shadow : STD_LOGIC;
signal XC_HALT_shadow : STD_ULOGIC;
signal V_E_OP231_shadow : STD_LOGIC;
signal V_A_CTRL_PC3DOWNTO2_shadow : STD_LOGIC_VECTOR(3 downto 2);
signal ME_ASR18_shadow : WORD;
signal VIR_ADDR31DOWNTO12_shadow : STD_LOGIC_VECTOR(31 downto 12);
signal V_M_CTRL_WICC_shadow : STD_ULOGIC;
signal V_M_CTRL_WREG_shadow : STD_ULOGIC;
signal V_W_S_S_shadow : STD_ULOGIC;
signal V_F_PC31DOWNTO2_shadow : STD_LOGIC_VECTOR(31 downto 2);
signal V_E_CWP_shadow : CWPTYPE;
signal V_D_INST019_shadow : STD_LOGIC;
signal V_A_STEP_shadow : STD_ULOGIC;
signal V_A_CTRL_TT3DOWNTO0_shadow : STD_LOGIC_VECTOR(3 downto 0);
signal V_A_CTRL_TRAP_shadow : STD_ULOGIC;
signal NPC31DOWNTO2_shadow : STD_LOGIC_VECTOR(31 downto 2);
signal V_M_CTRL_TRAP_shadow : STD_ULOGIC;
signal V_D_PC31DOWNTO4_shadow : STD_LOGIC_VECTOR(31 downto 4);
signal V_X_INTACK_shadow : STD_ULOGIC;
signal SIDLE_shadow : STD_ULOGIC;
signal V_A_CTRL_RETT_shadow : STD_ULOGIC;
signal V_X_DATA03_shadow : STD_LOGIC;
signal V_A_CTRL_INST19_shadow : STD_LOGIC;
signal V_W_S_SVT_shadow : STD_ULOGIC;
signal V_A_CTRL_PC31DOWNTO4_shadow : STD_LOGIC_VECTOR(31 downto 4);
signal V_X_LADDR_shadow : OP_TYPE;
signal V_W_S_DWT_shadow : STD_ULOGIC;
signal V_W_S_Y7DOWNTO0_shadow : STD_LOGIC_VECTOR(7 downto 0);
signal EX_JUMP_ADDRESS31DOWNTO2_shadow : STD_LOGIC_VECTOR(31 downto 2);
signal V_W_S_TBA_shadow : STD_LOGIC_VECTOR(19 downto 0);
signal XC_WADDR6DOWNTO0_shadow : STD_LOGIC_VECTOR(6 downto 0);
signal V_M_MUL_shadow : STD_ULOGIC;
signal V_E_SU_shadow : STD_ULOGIC;
signal V_M_Y31_shadow : STD_LOGIC;
signal TBUFI_DATA_shadow : STD_LOGIC_VECTOR(127 downto 0);
signal V_E_OP23_shadow : STD_LOGIC;
signal V_M_CTRL_PC31DOWNTO4_shadow : STD_LOGIC_VECTOR(31 downto 4);
signal DE_RADDR17DOWNTO0_shadow : STD_LOGIC_VECTOR(7 downto 0);
signal V_X_CTRL_PC31DOWNTO2_shadow : STD_LOGIC_VECTOR(31 downto 2);
signal V_E_CTRL_TRAP_shadow : STD_ULOGIC;
signal V_X_DEBUG_shadow : STD_ULOGIC;
signal TBUFI_ENABLE_shadow : STD_LOGIC;
signal V_M_DCI_LOCK_shadow : STD_ULOGIC;
signal V_X_CTRL_PC3DOWNTO2_shadow : STD_LOGIC_VECTOR(3 downto 2);
signal V_X_CTRL_WREG_shadow : STD_ULOGIC;
signal V_E_CTRL_INST24_shadow : STD_LOGIC;
signal V_D_MEXC_shadow : STD_ULOGIC;
signal V_W_RESULT_shadow : WORD;
signal VFPI_DBG_ENABLE_shadow : STD_ULOGIC;
signal EX_OP131_shadow : STD_LOGIC;
signal V_W_EXCEPT_shadow : STD_ULOGIC;
signal V_E_CTRL_TT3DOWNTO0_shadow : STD_LOGIC_VECTOR(3 downto 0);
signal V_E_CTRL_RETT_shadow : STD_ULOGIC;
signal ME_LADDR_shadow : OP_TYPE;
signal V_X_CTRL_PC31DOWNTO4_shadow : STD_LOGIC_VECTOR(31 downto 4);
signal XC_WADDR7DOWNTO0_shadow : STD_LOGIC_VECTOR(7 downto 0);
signal V_X_CTRL_PV_shadow : STD_ULOGIC;
signal V_E_CTRL_RD6DOWNTO0_shadow : STD_LOGIC_VECTOR(6 downto 0);
signal V_M_MAC_shadow : STD_ULOGIC;
signal V_D_SET_shadow : STD_LOGIC_VECTOR(0 downto 0);
signal VIR_ADDR3DOWNTO2_shadow : STD_LOGIC_VECTOR(3 downto 2);
signal V_D_CWP_shadow : CWPTYPE;
signal DE_INST20_shadow : STD_LOGIC;
signal V_D_INST_shadow : ICDTYPE;
signal V_D_ANNUL_shadow : STD_ULOGIC;
signal EX_OP2_shadow : WORD;
signal EX_SARI_shadow : STD_ULOGIC;
signal V_D_PC31DOWNTO2_shadow : STD_LOGIC_VECTOR(31 downto 2);
signal V_X_DCI_SIZE_shadow : OP_TYPE;
signal V_W_S_ICC_shadow : STD_LOGIC_VECTOR(3 downto 0);
signal V_M_Y_shadow : WORD;
signal V_X_SET_shadow : STD_LOGIC_VECTOR(0 downto 0);
signal V_X_CTRL_PC_shadow : PCTYPE;
signal V_A_CTRL_PC_shadow : PCTYPE;
signal V_A_JMPL_shadow : STD_ULOGIC;
signal V_E_CTRL_PC_shadow : PCTYPE;
signal V_E_CTRL_INST20_shadow : STD_LOGIC;
signal V_E_CTRL_WREG_shadow : STD_ULOGIC;
signal TBUFI_DIAG_shadow : STD_LOGIC_VECTOR(3 downto 0);
signal V_A_CTRL_WREG_shadow : STD_ULOGIC;
signal V_A_CTRL_shadow : PIPELINE_CTRL_TYPE;
signal V_A_CTRL_RD6DOWNTO0_shadow : STD_LOGIC_VECTOR(6 downto 0);
signal V_X_DATA0_shadow : STD_LOGIC_VECTOR(31 downto 0);
signal V_E_CTRL_INST19_shadow : STD_LOGIC;
signal ME_SIGNED_shadow : STD_ULOGIC;
signal V_W_WREG_shadow : STD_ULOGIC;
signal V_D_PC_shadow : PCTYPE;
signal VFPI_D_ANNUL_shadow : STD_ULOGIC;
signal DE_RADDR27DOWNTO0_shadow : STD_LOGIC_VECTOR(7 downto 0);
signal V_E_CTRL_CNT_shadow : OP_TYPE;
signal V_F_PC_shadow : PCTYPE;
signal V_X_DATA031_shadow : STD_LOGIC;
signal V_M_CTRL_PC31DOWNTO12_shadow : STD_LOGIC_VECTOR(31 downto 12);
signal V_X_CTRL_RD7DOWNTO0_shadow : STD_LOGIC_VECTOR(7 downto 0);
signal V_M_CTRL_TT_shadow : OP3_TYPE;
signal TBUFI_ADDR_shadow : STD_LOGIC_VECTOR(11 downto 0);
signal V_X_CTRL_shadow : PIPELINE_CTRL_TYPE;
signal V_A_CTRL_INST24_shadow : STD_LOGIC;
signal XC_TRAP_ADDRESS3DOWNTO2_shadow : STD_LOGIC_VECTOR(3 downto 2);
signal V_X_NERROR_shadow : STD_ULOGIC;
signal V_F_PC31DOWNTO4_shadow : STD_LOGIC_VECTOR(31 downto 4);
signal V_W_S_TT3DOWNTO0_shadow : STD_LOGIC_VECTOR(3 downto 0);
signal EX_JUMP_ADDRESS31DOWNTO4_shadow : STD_LOGIC_VECTOR(31 downto 4);
signal EX_ADD_RES32DOWNTO332DOWNTO3_shadow : STD_LOGIC_VECTOR(32 downto 3);
signal V_F_BRANCH_shadow : STD_ULOGIC;
signal V_A_CTRL_WICC_shadow : STD_ULOGIC;
signal V_A_CTRL_LD_shadow : STD_ULOGIC;
signal V_A_CTRL_TT_shadow : OP3_TYPE;
signal V_M_CTRL_LD_shadow : STD_ULOGIC;
signal V_E_SHCNT_shadow : ASI_TYPE;
signal XC_TRAP_ADDRESS31DOWNTO12_shadow : STD_LOGIC_VECTOR(31 downto 12);
signal V_E_MUL_shadow : STD_ULOGIC;
signal V_A_CTRL_INST_shadow : WORD;
signal V_A_CTRL_RD7DOWNTO0_shadow : STD_LOGIC_VECTOR(7 downto 0);
signal VIR_PWD_shadow : STD_ULOGIC;
signal XC_RESULT_shadow : WORD;
signal V_A_RFA1_shadow : RFATYPE;
signal V_W_S_ASR18_shadow : WORD;
signal V_E_JMPL_shadow : STD_ULOGIC;
signal ME_ICC_shadow : STD_LOGIC_VECTOR(3 downto 0);
signal V_E_CTRL_RD7DOWNTO0_shadow : STD_LOGIC_VECTOR(7 downto 0);
signal DE_INST24_shadow : STD_LOGIC;
signal XC_TRAP_shadow : STD_ULOGIC;
signal VDSU_TBUFCNT_shadow : STD_LOGIC_VECTOR(6 downto 0);
signal XC_TRAP_ADDRESS_shadow : PCTYPE;
-- Intermediate value holding signal declarations
signal V_E_CTRL_WREG_shadow_intermed_2 : STD_ULOGIC;
signal V_M_CTRL_PC_shadow_intermed_2 : STD_LOGIC_VECTOR(31 downto 2);
signal RIN_E_CTRL_TT3DOWNTO0_intermed_1 : STD_LOGIC_VECTOR(3 downto 0);
signal V_D_PC3DOWNTO2_shadow_intermed_6 : STD_LOGIC_VECTOR(3 downto 2);
signal RIN_M_CTRL_PC31DOWNTO12_intermed_5 : STD_LOGIC_VECTOR(31 downto 12);
signal RIN_A_RFA1_intermed_1 : STD_LOGIC_VECTOR(7 downto 0);
signal RIN_A_CTRL_PC31DOWNTO2_intermed_4 : STD_LOGIC_VECTOR(31 downto 2);
signal R_E_CTRL_TT_intermed_1 : STD_LOGIC_VECTOR(5 downto 0);
signal V_D_PC3DOWNTO2_shadow_intermed_2 : STD_LOGIC_VECTOR(3 downto 2);
signal ICO_MEXC_intermed_4 : STD_ULOGIC;
signal V_F_PC31DOWNTO2_shadow_intermed_1 : STD_LOGIC_VECTOR(31 downto 2);
signal RIN_X_DATA00_intermed_2 : STD_LOGIC;
signal R_A_CTRL_RD6DOWNTO0_intermed_1 : STD_LOGIC_VECTOR(6 downto 0);
signal R_A_CTRL_INST24_intermed_1 : STD_LOGIC;
signal RIN_E_CTRL_INST19_intermed_1 : STD_LOGIC;
signal V_X_DATA00_shadow_intermed_3 : STD_LOGIC;
signal RIN_A_CTRL_INST19_intermed_2 : STD_LOGIC;
signal IRIN_ADDR31DOWNTO2_intermed_2 : STD_LOGIC_VECTOR(31 downto 2);
signal V_E_CTRL_WREG_shadow_intermed_1 : STD_ULOGIC;
signal V_A_CTRL_PC31DOWNTO2_shadow_intermed_5 : STD_LOGIC_VECTOR(31 downto 2);
signal V_M_CTRL_PC_shadow_intermed_3 : STD_LOGIC_VECTOR(31 downto 2);
signal RIN_A_CTRL_WICC_intermed_3 : STD_ULOGIC;
signal V_A_CTRL_RETT_shadow_intermed_3 : STD_ULOGIC;
signal RPIN_PWD_intermed_1 : STD_ULOGIC;
signal RIN_A_CTRL_PC31DOWNTO12_intermed_7 : STD_LOGIC_VECTOR(31 downto 12);
signal R_D_INST020_intermed_1 : STD_LOGIC;
signal V_E_CTRL_TT_shadow_intermed_3 : STD_LOGIC_VECTOR(5 downto 0);
signal DE_INST_shadow_intermed_2 : STD_LOGIC_VECTOR(31 downto 0);
signal R_M_CTRL_PC31DOWNTO2_intermed_3 : STD_LOGIC_VECTOR(31 downto 2);
signal DBGI_DADDR9DOWNTO2_intermed_1 : STD_LOGIC_VECTOR(9 downto 2);
signal R_D_PC31DOWNTO2_intermed_6 : STD_LOGIC_VECTOR(31 downto 2);
signal RIN_A_CTRL_TT3DOWNTO0_intermed_5 : STD_LOGIC_VECTOR(3 downto 0);
signal RIN_A_CTRL_TRAP_intermed_3 : STD_ULOGIC;
signal V_E_CTRL_CNT_shadow_intermed_2 : STD_LOGIC_VECTOR(1 downto 0);
signal V_E_CTRL_PC31DOWNTO4_shadow_intermed_4 : STD_LOGIC_VECTOR(31 downto 4);
signal RIN_D_STEP_intermed_1 : STD_ULOGIC;
signal V_M_CTRL_TT3DOWNTO0_shadow_intermed_4 : STD_LOGIC_VECTOR(3 downto 0);
signal V_A_CTRL_PC_shadow_intermed_2 : STD_LOGIC_VECTOR(31 downto 2);
signal RIN_D_PC31DOWNTO2_intermed_1 : STD_LOGIC_VECTOR(31 downto 2);
signal V_E_CTRL_PC31DOWNTO4_shadow_intermed_5 : STD_LOGIC_VECTOR(31 downto 4);
signal RIN_D_INST024_intermed_1 : STD_LOGIC;
signal V_D_INST019_shadow_intermed_2 : STD_LOGIC;
signal RIN_E_CTRL_INST20_intermed_1 : STD_LOGIC;
signal V_D_PC3DOWNTO2_shadow_intermed_7 : STD_LOGIC_VECTOR(3 downto 2);
signal V_M_CTRL_PC31DOWNTO4_shadow_intermed_4 : STD_LOGIC_VECTOR(31 downto 4);
signal V_M_CTRL_RD6DOWNTO0_shadow_intermed_2 : STD_LOGIC_VECTOR(6 downto 0);
signal RIN_E_CTRL_PC3DOWNTO2_intermed_3 : STD_LOGIC_VECTOR(3 downto 2);
signal RIN_M_Y31_intermed_1 : STD_LOGIC;
signal V_D_INST0_shadow_intermed_1 : STD_LOGIC_VECTOR(31 downto 0);
signal RIN_E_YMSB_intermed_1 : STD_ULOGIC;
signal R_X_DATA031_intermed_2 : STD_LOGIC;
signal RIN_M_CTRL_WREG_intermed_2 : STD_ULOGIC;
signal V_X_CTRL_TT_shadow_intermed_1 : STD_LOGIC_VECTOR(5 downto 0);
signal RIN_E_CTRL_PC_intermed_4 : STD_LOGIC_VECTOR(31 downto 2);
signal V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_2 : STD_LOGIC_VECTOR(3 downto 0);
signal RIN_E_CTRL_PC31DOWNTO12_intermed_4 : STD_LOGIC_VECTOR(31 downto 12);
signal V_A_CTRL_PC3DOWNTO2_shadow_intermed_3 : STD_LOGIC_VECTOR(3 downto 2);
signal RIN_D_INST019_intermed_3 : STD_LOGIC;
signal RIN_E_CTRL_PC31DOWNTO2_intermed_4 : STD_LOGIC_VECTOR(31 downto 2);
signal R_A_CTRL_TT_intermed_1 : STD_LOGIC_VECTOR(5 downto 0);
signal RIN_A_CTRL_WICC_intermed_2 : STD_ULOGIC;
signal RIN_D_INST024_intermed_3 : STD_LOGIC;
signal V_E_CTRL_PC31DOWNTO2_shadow_intermed_6 : STD_LOGIC_VECTOR(31 downto 2);
signal RIN_F_PC3DOWNTO2_intermed_1 : STD_LOGIC_VECTOR(3 downto 2);
signal V_A_CTRL_PC31DOWNTO12_shadow_intermed_4 : STD_LOGIC_VECTOR(31 downto 12);
signal EX_ADD_RES32DOWNTO332DOWNTO5_shadow_intermed_1 : STD_LOGIC_VECTOR(32 downto 5);
signal V_X_DATA04DOWNTO0_shadow_intermed_1 : STD_LOGIC_VECTOR(4 downto 0);
signal R_A_CTRL_INST20_intermed_2 : STD_LOGIC;
signal V_A_CTRL_PC31DOWNTO12_shadow_intermed_6 : STD_LOGIC_VECTOR(31 downto 12);
signal R_A_CTRL_RETT_intermed_2 : STD_ULOGIC;
signal RIN_M_DCI_LOCK_intermed_1 : STD_ULOGIC;
signal RIN_D_PC31DOWNTO12_intermed_6 : STD_LOGIC_VECTOR(31 downto 12);
signal RIN_E_CTRL_TT_intermed_3 : STD_LOGIC_VECTOR(5 downto 0);
signal R_E_CTRL_RD7DOWNTO0_intermed_2 : STD_LOGIC_VECTOR(7 downto 0);
signal RIN_A_ET_intermed_1 : STD_ULOGIC;
signal RIN_X_CTRL_RD6DOWNTO0_intermed_1 : STD_LOGIC_VECTOR(6 downto 0);
signal RIN_M_CTRL_PC31DOWNTO12_intermed_2 : STD_LOGIC_VECTOR(31 downto 12);
signal DBGI_STEP_intermed_1 : STD_ULOGIC;
signal V_A_CTRL_RETT_shadow_intermed_2 : STD_ULOGIC;
signal R_X_CTRL_PC3DOWNTO2_intermed_1 : STD_LOGIC_VECTOR(3 downto 2);
signal R_A_CTRL_PC31DOWNTO4_intermed_4 : STD_LOGIC_VECTOR(31 downto 4);
signal V_M_CTRL_PV_shadow_intermed_1 : STD_ULOGIC;
signal RIN_M_CTRL_PC31DOWNTO2_intermed_5 : STD_LOGIC_VECTOR(31 downto 2);
signal V_M_CTRL_PC31DOWNTO12_shadow_intermed_5 : STD_LOGIC_VECTOR(31 downto 12);
signal V_X_LADDR_shadow_intermed_1 : STD_LOGIC_VECTOR(1 downto 0);
signal V_D_ANNUL_shadow_intermed_2 : STD_ULOGIC;
signal V_A_CTRL_RD6DOWNTO0_shadow_intermed_1 : STD_LOGIC_VECTOR(6 downto 0);
signal RIN_W_WA_intermed_1 : STD_LOGIC_VECTOR(7 downto 0);
signal V_D_PC_shadow_intermed_4 : STD_LOGIC_VECTOR(31 downto 2);
signal RIN_D_INST04DOWNTO0_intermed_2 : STD_LOGIC_VECTOR(4 downto 0);
signal V_X_CTRL_PC31DOWNTO2_shadow_intermed_1 : STD_LOGIC_VECTOR(31 downto 2);
signal RIN_X_CTRL_PC31DOWNTO4_intermed_2 : STD_LOGIC_VECTOR(31 downto 4);
signal V_E_CTRL_WICC_shadow_intermed_1 : STD_ULOGIC;
signal VDSU_CRDY2_shadow_intermed_2 : STD_LOGIC;
signal V_M_RESULT1DOWNTO0_shadow_intermed_3 : STD_LOGIC_VECTOR(1 downto 0);
signal RIN_D_INST0_intermed_1 : STD_LOGIC_VECTOR(31 downto 0);
signal V_X_DATA03_shadow_intermed_2 : STD_LOGIC;
signal RIN_X_DCI_intermed_1 : DC_IN_TYPE;
signal DSUIN_TT_intermed_1 : STD_LOGIC_VECTOR(7 downto 0);
signal V_D_CNT_shadow_intermed_4 : STD_LOGIC_VECTOR(1 downto 0);
signal RIN_D_CNT_intermed_4 : STD_LOGIC_VECTOR(1 downto 0);
signal ICO_MEXC_intermed_1 : STD_ULOGIC;
signal R_X_ANNUL_ALL_intermed_2 : STD_ULOGIC;
signal R_D_INST0_intermed_4 : STD_LOGIC_VECTOR(31 downto 0);
signal R_X_CTRL_TT3DOWNTO0_intermed_2 : STD_LOGIC_VECTOR(3 downto 0);
signal R_D_PC3DOWNTO2_intermed_3 : STD_LOGIC_VECTOR(3 downto 2);
signal RIN_D_CNT_intermed_2 : STD_LOGIC_VECTOR(1 downto 0);
signal V_M_DCI_SIZE_shadow_intermed_2 : STD_LOGIC_VECTOR(1 downto 0);
signal R_A_CTRL_ANNUL_intermed_2 : STD_ULOGIC;
signal V_W_S_S_shadow_intermed_1 : STD_ULOGIC;
signal RIN_M_CTRL_TT_intermed_2 : STD_LOGIC_VECTOR(5 downto 0);
signal R_D_INST024_intermed_3 : STD_LOGIC;
signal EX_ADD_RES32DOWNTO330DOWNTO11_shadow_intermed_1 : STD_LOGIC_VECTOR(30 downto 11);
signal V_A_CTRL_RETT_shadow_intermed_1 : STD_ULOGIC;
signal R_D_INST019_intermed_1 : STD_LOGIC;
signal R_X_DATA04DOWNTO0_intermed_1 : STD_LOGIC_VECTOR(4 downto 0);
signal V_E_CTRL_TT3DOWNTO0_shadow_intermed_1 : STD_LOGIC_VECTOR(3 downto 0);
signal V_D_PC31DOWNTO4_shadow_intermed_6 : STD_LOGIC_VECTOR(31 downto 4);
signal V_X_CTRL_RD6DOWNTO0_shadow_intermed_1 : STD_LOGIC_VECTOR(6 downto 0);
signal RIN_W_S_ET_intermed_1 : STD_ULOGIC;
signal R_E_CTRL_TRAP_intermed_1 : STD_ULOGIC;
signal RIN_D_INST024_intermed_2 : STD_LOGIC;
signal V_A_CTRL_PC_shadow_intermed_3 : STD_LOGIC_VECTOR(31 downto 2);
signal R_M_CTRL_PC31DOWNTO4_intermed_2 : STD_LOGIC_VECTOR(31 downto 4);
signal RIN_D_INST019_intermed_2 : STD_LOGIC;
signal VIR_ADDR31DOWNTO4_shadow_intermed_2 : STD_LOGIC_VECTOR(31 downto 4);
signal V_E_CTRL_RD6DOWNTO0_shadow_intermed_3 : STD_LOGIC_VECTOR(6 downto 0);
signal R_D_CWP_intermed_1 : STD_LOGIC_VECTOR(2 downto 0);
signal RIN_A_CTRL_TT3DOWNTO0_intermed_2 : STD_LOGIC_VECTOR(3 downto 0);
signal RIN_X_CTRL_PC3DOWNTO2_intermed_3 : STD_LOGIC_VECTOR(3 downto 2);
signal RIN_D_PC31DOWNTO2_intermed_8 : STD_LOGIC_VECTOR(31 downto 2);
signal V_X_CTRL_PC3DOWNTO2_shadow_intermed_1 : STD_LOGIC_VECTOR(3 downto 2);
signal RIN_A_CTRL_ANNUL_intermed_1 : STD_ULOGIC;
signal RIN_M_CTRL_PC31DOWNTO12_intermed_3 : STD_LOGIC_VECTOR(31 downto 12);
signal R_M_DCI_SIGNED_intermed_1 : STD_ULOGIC;
signal RIN_X_DCI_SIGNED_intermed_1 : STD_ULOGIC;
signal V_D_PC31DOWNTO2_shadow_intermed_4 : STD_LOGIC_VECTOR(31 downto 2);
signal V_M_CTRL_RD7DOWNTO0_shadow_intermed_2 : STD_LOGIC_VECTOR(7 downto 0);
signal V_E_SU_shadow_intermed_1 : STD_ULOGIC;
signal R_A_CTRL_INST20_intermed_1 : STD_LOGIC;
signal R_D_PC31DOWNTO12_intermed_7 : STD_LOGIC_VECTOR(31 downto 12);
signal XC_TRAP_ADDRESS_shadow_intermed_1 : STD_LOGIC_VECTOR(31 downto 2);
signal RIN_X_CTRL_PC31DOWNTO2_intermed_3 : STD_LOGIC_VECTOR(31 downto 2);
signal R_E_CTRL_RETT_intermed_1 : STD_ULOGIC;
signal V_X_DCI_SIZE_shadow_intermed_1 : STD_LOGIC_VECTOR(1 downto 0);
signal RIN_D_CNT_intermed_3 : STD_LOGIC_VECTOR(1 downto 0);
signal RIN_A_CTRL_ANNUL_intermed_4 : STD_ULOGIC;
signal R_E_CTRL_TT3DOWNTO0_intermed_1 : STD_LOGIC_VECTOR(3 downto 0);
signal R_D_PC3DOWNTO2_intermed_2 : STD_LOGIC_VECTOR(3 downto 2);
signal V_D_INST024_shadow_intermed_3 : STD_LOGIC;
signal V_X_CTRL_TT3DOWNTO0_shadow_intermed_3 : STD_LOGIC_VECTOR(3 downto 0);
signal V_A_CTRL_RD6DOWNTO0_shadow_intermed_3 : STD_LOGIC_VECTOR(6 downto 0);
signal R_M_CTRL_PC31DOWNTO2_intermed_4 : STD_LOGIC_VECTOR(31 downto 2);
signal RIN_A_CTRL_PC31DOWNTO12_intermed_3 : STD_LOGIC_VECTOR(31 downto 12);
signal R_A_CTRL_PC31DOWNTO12_intermed_5 : STD_LOGIC_VECTOR(31 downto 12);
signal R_A_CTRL_PC_intermed_2 : STD_LOGIC_VECTOR(31 downto 2);
signal V_X_MEXC_shadow_intermed_1 : STD_ULOGIC;
signal V_M_CTRL_RD7DOWNTO0_shadow_intermed_1 : STD_LOGIC_VECTOR(7 downto 0);
signal IR_ADDR31DOWNTO4_intermed_1 : STD_LOGIC_VECTOR(31 downto 4);
signal V_A_CTRL_PC_shadow_intermed_4 : STD_LOGIC_VECTOR(31 downto 2);
signal RIN_M_CTRL_PC3DOWNTO2_intermed_1 : STD_LOGIC_VECTOR(3 downto 2);
signal VIR_ADDR31DOWNTO4_shadow_intermed_1 : STD_LOGIC_VECTOR(31 downto 4);
signal RIN_E_CTRL_WREG_intermed_1 : STD_ULOGIC;
signal RIN_D_PC31DOWNTO12_intermed_1 : STD_LOGIC_VECTOR(31 downto 12);
signal V_E_CTRL_TT3DOWNTO0_shadow_intermed_2 : STD_LOGIC_VECTOR(3 downto 0);
signal RIN_D_PC31DOWNTO12_intermed_3 : STD_LOGIC_VECTOR(31 downto 12);
signal V_A_CTRL_TT_shadow_intermed_3 : STD_LOGIC_VECTOR(5 downto 0);
signal RIN_A_CTRL_INST24_intermed_2 : STD_LOGIC;
signal ICO_MEXC_intermed_3 : STD_ULOGIC;
signal R_D_PC3DOWNTO2_intermed_4 : STD_LOGIC_VECTOR(3 downto 2);
signal R_M_CTRL_INST_intermed_1 : STD_LOGIC_VECTOR(31 downto 0);
signal V_A_CWP_shadow_intermed_1 : STD_LOGIC_VECTOR(2 downto 0);
signal V_A_CTRL_WICC_shadow_intermed_3 : STD_ULOGIC;
signal V_D_PC_shadow_intermed_6 : STD_LOGIC_VECTOR(31 downto 2);
signal RIN_X_ANNUL_ALL_intermed_5 : STD_ULOGIC;
signal RIN_E_CTRL_INST20_intermed_2 : STD_LOGIC;
signal R_X_DATA0_intermed_2 : STD_LOGIC_VECTOR(31 downto 0);
signal RIN_D_PC_intermed_4 : STD_LOGIC_VECTOR(31 downto 2);
signal R_E_CTRL_PV_intermed_1 : STD_ULOGIC;
signal R_E_CTRL_TT3DOWNTO0_intermed_2 : STD_LOGIC_VECTOR(3 downto 0);
signal R_D_PC_intermed_1 : STD_LOGIC_VECTOR(31 downto 2);
signal R_A_CTRL_PC_intermed_3 : STD_LOGIC_VECTOR(31 downto 2);
signal EX_JUMP_ADDRESS31DOWNTO12_shadow_intermed_1 : STD_LOGIC_VECTOR(31 downto 12);
signal R_D_INST04DOWNTO0_intermed_2 : STD_LOGIC_VECTOR(4 downto 0);
signal R_X_CTRL_TT3DOWNTO0_intermed_1 : STD_LOGIC_VECTOR(3 downto 0);
signal V_M_DCI_SIGNED_shadow_intermed_1 : STD_ULOGIC;
signal RIN_X_CTRL_TT3DOWNTO0_intermed_1 : STD_LOGIC_VECTOR(3 downto 0);
signal V_X_ANNUL_ALL_shadow_intermed_2 : STD_ULOGIC;
signal V_D_PC31DOWNTO4_shadow_intermed_7 : STD_LOGIC_VECTOR(31 downto 4);
signal RIN_E_OP13_intermed_1 : STD_LOGIC;
signal RIN_A_CWP_intermed_1 : STD_LOGIC_VECTOR(2 downto 0);
signal RIN_E_CTRL_WICC_intermed_1 : STD_ULOGIC;
signal RIN_E_OP2_intermed_1 : STD_LOGIC_VECTOR(31 downto 0);
signal RIN_A_CTRL_TT3DOWNTO0_intermed_4 : STD_LOGIC_VECTOR(3 downto 0);
signal VP_ERROR_shadow_intermed_2 : STD_ULOGIC;
signal RIN_A_CTRL_RD7DOWNTO0_intermed_2 : STD_LOGIC_VECTOR(7 downto 0);
signal RIN_E_CTRL_intermed_2 : PIPELINE_CTRL_TYPE;
signal R_M_CTRL_PC_intermed_1 : STD_LOGIC_VECTOR(31 downto 2);
signal RIN_E_CTRL_PC31DOWNTO2_intermed_5 : STD_LOGIC_VECTOR(31 downto 2);
signal R_M_Y31_intermed_2 : STD_LOGIC;
signal V_M_CTRL_PC3DOWNTO2_shadow_intermed_4 : STD_LOGIC_VECTOR(3 downto 2);
signal V_M_CTRL_RETT_shadow_intermed_1 : STD_ULOGIC;
signal V_X_CTRL_PC31DOWNTO4_shadow_intermed_3 : STD_LOGIC_VECTOR(31 downto 4);
signal XC_VECTT3DOWNTO0_shadow_intermed_2 : STD_LOGIC_VECTOR(3 downto 0);
signal RIN_M_CTRL_PC31DOWNTO12_intermed_1 : STD_LOGIC_VECTOR(31 downto 12);
signal RIN_M_RESULT1DOWNTO0_intermed_2 : STD_LOGIC_VECTOR(1 downto 0);
signal V_X_ANNUL_ALL_shadow_intermed_4 : STD_ULOGIC;
signal RIN_W_S_TBA_intermed_1 : STD_LOGIC_VECTOR(19 downto 0);
signal RIN_X_DATA031_intermed_1 : STD_LOGIC;
signal XC_TRAP_ADDRESS31DOWNTO12_shadow_intermed_1 : STD_LOGIC_VECTOR(31 downto 12);
signal RIN_D_PC3DOWNTO2_intermed_4 : STD_LOGIC_VECTOR(3 downto 2);
signal RIN_X_CTRL_PC31DOWNTO4_intermed_3 : STD_LOGIC_VECTOR(31 downto 4);
signal V_E_CTRL_PC31DOWNTO4_shadow_intermed_2 : STD_LOGIC_VECTOR(31 downto 4);
signal V_M_CTRL_PC3DOWNTO2_shadow_intermed_3 : STD_LOGIC_VECTOR(3 downto 2);
signal V_M_CTRL_PC31DOWNTO12_shadow_intermed_2 : STD_LOGIC_VECTOR(31 downto 12);
signal RIN_E_CTRL_PV_intermed_1 : STD_ULOGIC;
signal EX_ADD_RES32DOWNTO332DOWNTO13_shadow_intermed_1 : STD_LOGIC_VECTOR(32 downto 13);
signal R_E_CTRL_WREG_intermed_2 : STD_ULOGIC;
signal R_X_DATA031_intermed_1 : STD_LOGIC;
signal R_D_INST0_intermed_2 : STD_LOGIC_VECTOR(31 downto 0);
signal RIN_E_SARI_intermed_1 : STD_ULOGIC;
signal R_M_Y31_intermed_1 : STD_LOGIC;
signal IR_ADDR3DOWNTO2_intermed_1 : STD_LOGIC_VECTOR(3 downto 2);
signal DE_INST24_shadow_intermed_2 : STD_LOGIC;
signal V_W_S_S_shadow_intermed_2 : STD_ULOGIC;
signal DE_INST20_shadow_intermed_3 : STD_LOGIC;
signal R_E_CTRL_TT3DOWNTO0_intermed_4 : STD_LOGIC_VECTOR(3 downto 0);
signal RIN_A_CTRL_TT_intermed_2 : STD_LOGIC_VECTOR(5 downto 0);
signal V_A_CTRL_PV_shadow_intermed_2 : STD_ULOGIC;
signal V_E_CTRL_TT_shadow_intermed_1 : STD_LOGIC_VECTOR(5 downto 0);
signal V_D_PC31DOWNTO2_shadow_intermed_5 : STD_LOGIC_VECTOR(31 downto 2);
signal V_X_DATA04DOWNTO0_shadow_intermed_2 : STD_LOGIC_VECTOR(4 downto 0);
signal R_X_CTRL_PC31DOWNTO4_intermed_2 : STD_LOGIC_VECTOR(31 downto 4);
signal RIN_M_CTRL_INST_intermed_1 : STD_LOGIC_VECTOR(31 downto 0);
signal RIN_A_CTRL_RD6DOWNTO0_intermed_2 : STD_LOGIC_VECTOR(6 downto 0);
signal EX_JUMP_ADDRESS31DOWNTO12_shadow_intermed_2 : STD_LOGIC_VECTOR(31 downto 12);
signal V_X_DATA0_shadow_intermed_2 : STD_LOGIC_VECTOR(31 downto 0);
signal R_A_CTRL_WREG_intermed_3 : STD_ULOGIC;
signal RIN_X_CTRL_PC31DOWNTO12_intermed_2 : STD_LOGIC_VECTOR(31 downto 12);
signal R_D_CNT_intermed_3 : STD_LOGIC_VECTOR(1 downto 0);
signal V_E_OP131_shadow_intermed_1 : STD_LOGIC;
signal R_D_PC31DOWNTO12_intermed_6 : STD_LOGIC_VECTOR(31 downto 12);
signal RIN_X_CTRL_WICC_intermed_1 : STD_ULOGIC;
signal V_D_PC31DOWNTO12_shadow_intermed_1 : STD_LOGIC_VECTOR(31 downto 12);
signal RIN_E_CTRL_TRAP_intermed_3 : STD_ULOGIC;
signal R_X_RESULT6DOWNTO0_intermed_1 : STD_LOGIC_VECTOR(6 downto 0);
signal R_E_CTRL_INST19_intermed_2 : STD_LOGIC;
signal RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_2 : STD_LOGIC_VECTOR(3 downto 0);
signal R_M_CTRL_RD7DOWNTO0_intermed_1 : STD_LOGIC_VECTOR(7 downto 0);
signal RIN_E_CTRL_PC31DOWNTO12_intermed_6 : STD_LOGIC_VECTOR(31 downto 12);
signal RIN_W_S_ICC_intermed_1 : STD_LOGIC_VECTOR(3 downto 0);
signal RIN_A_CTRL_PC31DOWNTO4_intermed_3 : STD_LOGIC_VECTOR(31 downto 4);
signal V_A_CTRL_INST19_shadow_intermed_3 : STD_LOGIC;
signal V_D_PC31DOWNTO12_shadow_intermed_5 : STD_LOGIC_VECTOR(31 downto 12);
signal V_A_CTRL_INST19_shadow_intermed_2 : STD_LOGIC;
signal V_X_CTRL_WREG_shadow_intermed_1 : STD_ULOGIC;
signal V_A_CTRL_TRAP_shadow_intermed_2 : STD_ULOGIC;
signal RIN_D_INST0_intermed_3 : STD_LOGIC_VECTOR(31 downto 0);
signal RIN_E_CTRL_PC3DOWNTO2_intermed_1 : STD_LOGIC_VECTOR(3 downto 2);
signal RIN_M_CTRL_PC3DOWNTO2_intermed_3 : STD_LOGIC_VECTOR(3 downto 2);
signal V_A_RFE2_shadow_intermed_1 : STD_ULOGIC;
signal V_M_Y_shadow_intermed_1 : STD_LOGIC_VECTOR(31 downto 0);
signal RIN_A_CTRL_LD_intermed_1 : STD_ULOGIC;
signal V_E_CTRL_PC_shadow_intermed_3 : STD_LOGIC_VECTOR(31 downto 2);
signal V_E_MUL_shadow_intermed_1 : STD_ULOGIC;
signal R_E_CTRL_PC31DOWNTO12_intermed_1 : STD_LOGIC_VECTOR(31 downto 12);
signal RIN_X_CTRL_PC31DOWNTO12_intermed_3 : STD_LOGIC_VECTOR(31 downto 12);
signal R_E_CTRL_TRAP_intermed_2 : STD_ULOGIC;
signal DE_INST24_shadow_intermed_1 : STD_LOGIC;
signal V_E_CTRL_PC_shadow_intermed_2 : STD_LOGIC_VECTOR(31 downto 2);
signal V_A_CTRL_TT_shadow_intermed_1 : STD_LOGIC_VECTOR(5 downto 0);
signal V_D_MEXC_shadow_intermed_4 : STD_ULOGIC;
signal V_D_PC31DOWNTO12_shadow_intermed_6 : STD_LOGIC_VECTOR(31 downto 12);
signal V_A_CTRL_PC31DOWNTO12_shadow_intermed_3 : STD_LOGIC_VECTOR(31 downto 12);
signal R_X_CTRL_PC31DOWNTO12_intermed_3 : STD_LOGIC_VECTOR(31 downto 12);
signal V_M_CTRL_PV_shadow_intermed_2 : STD_ULOGIC;
signal RIN_A_CTRL_PC31DOWNTO2_intermed_2 : STD_LOGIC_VECTOR(31 downto 2);
signal EX_JUMP_ADDRESS31DOWNTO2_shadow_intermed_2 : STD_LOGIC_VECTOR(31 downto 2);
signal RIN_E_CTRL_PC31DOWNTO4_intermed_1 : STD_LOGIC_VECTOR(31 downto 4);
signal RIN_E_CTRL_PC31DOWNTO12_intermed_2 : STD_LOGIC_VECTOR(31 downto 12);
signal RIN_M_CTRL_TRAP_intermed_1 : STD_ULOGIC;
signal R_E_CTRL_PC31DOWNTO2_intermed_2 : STD_LOGIC_VECTOR(31 downto 2);
signal R_E_CTRL_LD_intermed_1 : STD_ULOGIC;
signal R_M_CTRL_PC31DOWNTO2_intermed_1 : STD_LOGIC_VECTOR(31 downto 2);
signal RIN_A_CTRL_PC31DOWNTO2_intermed_5 : STD_LOGIC_VECTOR(31 downto 2);
signal V_W_S_CWP_shadow_intermed_1 : STD_LOGIC_VECTOR(2 downto 0);
signal R_M_CTRL_PC3DOWNTO2_intermed_1 : STD_LOGIC_VECTOR(3 downto 2);
signal V_E_CTRL_PC31DOWNTO12_shadow_intermed_4 : STD_LOGIC_VECTOR(31 downto 12);
signal R_X_CTRL_PC31DOWNTO4_intermed_1 : STD_LOGIC_VECTOR(31 downto 4);
signal V_M_CTRL_PC_shadow_intermed_1 : STD_LOGIC_VECTOR(31 downto 2);
signal IR_ADDR31DOWNTO2_intermed_2 : STD_LOGIC_VECTOR(31 downto 2);
signal V_E_CTRL_TT3DOWNTO0_shadow_intermed_4 : STD_LOGIC_VECTOR(3 downto 0);
signal V_E_CTRL_PC3DOWNTO2_shadow_intermed_3 : STD_LOGIC_VECTOR(3 downto 2);
signal RIN_X_CTRL_PC31DOWNTO4_intermed_1 : STD_LOGIC_VECTOR(31 downto 4);
signal R_E_CTRL_PC31DOWNTO12_intermed_2 : STD_LOGIC_VECTOR(31 downto 12);
signal RIN_M_CTRL_RETT_intermed_1 : STD_ULOGIC;
signal V_M_DCI_LOCK_shadow_intermed_1 : STD_ULOGIC;
signal V_X_RESULT6DOWNTO0_shadow_intermed_1 : STD_LOGIC_VECTOR(6 downto 0);
signal RIN_X_DATA04DOWNTO0_intermed_3 : STD_LOGIC_VECTOR(4 downto 0);
signal V_A_RFE1_shadow_intermed_1 : STD_ULOGIC;
signal V_X_NERROR_shadow_intermed_1 : STD_ULOGIC;
signal V_D_PC3DOWNTO2_shadow_intermed_1 : STD_LOGIC_VECTOR(3 downto 2);
signal V_E_CTRL_LD_shadow_intermed_1 : STD_ULOGIC;
signal VIR_ADDR_shadow_intermed_1 : STD_LOGIC_VECTOR(31 downto 2);
signal R_M_CTRL_PC31DOWNTO12_intermed_2 : STD_LOGIC_VECTOR(31 downto 12);
signal V_E_CTRL_PV_shadow_intermed_2 : STD_ULOGIC;
signal RIN_D_INST04DOWNTO0_intermed_1 : STD_LOGIC_VECTOR(4 downto 0);
signal RIN_E_CTRL_PC31DOWNTO4_intermed_4 : STD_LOGIC_VECTOR(31 downto 4);
signal R_A_CTRL_PC3DOWNTO2_intermed_3 : STD_LOGIC_VECTOR(3 downto 2);
signal R_E_CTRL_INST19_intermed_1 : STD_LOGIC;
signal RIN_E_CTRL_TT3DOWNTO0_intermed_4 : STD_LOGIC_VECTOR(3 downto 0);
signal R_M_CTRL_PC31DOWNTO4_intermed_3 : STD_LOGIC_VECTOR(31 downto 4);
signal V_A_CTRL_PC31DOWNTO4_shadow_intermed_4 : STD_LOGIC_VECTOR(31 downto 4);
signal RIN_W_S_DWT_intermed_1 : STD_ULOGIC;
signal V_M_CTRL_PC31DOWNTO2_shadow_intermed_2 : STD_LOGIC_VECTOR(31 downto 2);
signal R_D_PC31DOWNTO12_intermed_4 : STD_LOGIC_VECTOR(31 downto 12);
signal RIN_X_NERROR_intermed_1 : STD_ULOGIC;
signal R_M_CTRL_PC3DOWNTO2_intermed_2 : STD_LOGIC_VECTOR(3 downto 2);
signal ICO_MEXC_intermed_5 : STD_ULOGIC;
signal R_A_CTRL_RD7DOWNTO0_intermed_2 : STD_LOGIC_VECTOR(7 downto 0);
signal V_A_CTRL_PC31DOWNTO4_shadow_intermed_1 : STD_LOGIC_VECTOR(31 downto 4);
signal IRIN_ADDR31DOWNTO2_intermed_1 : STD_LOGIC_VECTOR(31 downto 2);
signal RIN_D_INST020_intermed_4 : STD_LOGIC;
signal VIR_ADDR31DOWNTO12_shadow_intermed_3 : STD_LOGIC_VECTOR(31 downto 12);
signal XC_TRAP_ADDRESS3DOWNTO2_shadow_intermed_1 : STD_LOGIC_VECTOR(3 downto 2);
signal R_A_CTRL_INST_intermed_1 : STD_LOGIC_VECTOR(31 downto 0);
signal R_E_CTRL_PC31DOWNTO2_intermed_3 : STD_LOGIC_VECTOR(31 downto 2);
signal RIN_M_CTRL_PC3DOWNTO2_intermed_2 : STD_LOGIC_VECTOR(3 downto 2);
signal RIN_X_CTRL_TT3DOWNTO0_intermed_3 : STD_LOGIC_VECTOR(3 downto 0);
signal V_M_CTRL_PC31DOWNTO2_shadow_intermed_4 : STD_LOGIC_VECTOR(31 downto 2);
signal RIN_A_CTRL_RETT_intermed_2 : STD_ULOGIC;
signal V_X_DATA00_shadow_intermed_1 : STD_LOGIC;
signal RIN_M_CTRL_RD6DOWNTO0_intermed_2 : STD_LOGIC_VECTOR(6 downto 0);
signal RIN_E_CTRL_TT3DOWNTO0_intermed_2 : STD_LOGIC_VECTOR(3 downto 0);
signal V_M_CTRL_INST_shadow_intermed_1 : STD_LOGIC_VECTOR(31 downto 0);
signal RIN_A_CTRL_TT3DOWNTO0_intermed_3 : STD_LOGIC_VECTOR(3 downto 0);
signal EX_ADD_RES32DOWNTO332DOWNTO3_shadow_intermed_1 : STD_LOGIC_VECTOR(32 downto 3);
signal R_A_CTRL_TT3DOWNTO0_intermed_1 : STD_LOGIC_VECTOR(3 downto 0);
signal V_X_DEBUG_shadow_intermed_1 : STD_ULOGIC;
signal V_E_CTRL_PC_shadow_intermed_4 : STD_LOGIC_VECTOR(31 downto 2);
signal V_M_CTRL_TT_shadow_intermed_1 : STD_LOGIC_VECTOR(5 downto 0);
signal RIN_A_CTRL_PV_intermed_4 : STD_ULOGIC;
signal R_E_MAC_intermed_1 : STD_ULOGIC;
signal V_E_CTRL_PC3DOWNTO2_shadow_intermed_1 : STD_LOGIC_VECTOR(3 downto 2);
signal R_M_RESULT1DOWNTO0_intermed_1 : STD_LOGIC_VECTOR(1 downto 0);
signal IR_ADDR31DOWNTO2_intermed_1 : STD_LOGIC_VECTOR(31 downto 2);
signal RIN_A_CTRL_WREG_intermed_2 : STD_ULOGIC;
signal V_D_MEXC_shadow_intermed_1 : STD_ULOGIC;
signal XC_TRAP_ADDRESS31DOWNTO12_shadow_intermed_2 : STD_LOGIC_VECTOR(31 downto 12);
signal R_A_CTRL_LD_intermed_2 : STD_ULOGIC;
signal R_A_CTRL_intermed_2 : PIPELINE_CTRL_TYPE;
signal V_M_CTRL_TRAP_shadow_intermed_2 : STD_ULOGIC;
signal V_A_JMPL_shadow_intermed_1 : STD_ULOGIC;
signal V_E_CTRL_RETT_shadow_intermed_2 : STD_ULOGIC;
signal RIN_M_CTRL_LD_intermed_1 : STD_ULOGIC;
signal R_D_INST019_intermed_3 : STD_LOGIC;
signal V_X_DATA04DOWNTO0_shadow_intermed_3 : STD_LOGIC_VECTOR(4 downto 0);
signal RIN_W_S_TT_intermed_1 : STD_LOGIC_VECTOR(7 downto 0);
signal V_A_CTRL_PC_shadow_intermed_5 : STD_LOGIC_VECTOR(31 downto 2);
signal V_X_CTRL_PC31DOWNTO12_shadow_intermed_1 : STD_LOGIC_VECTOR(31 downto 12);
signal R_D_INST019_intermed_2 : STD_LOGIC;
signal RIN_A_CTRL_CNT_intermed_1 : STD_LOGIC_VECTOR(1 downto 0);
signal R_X_ANNUL_ALL_intermed_3 : STD_ULOGIC;
signal V_X_DATA031_shadow_intermed_3 : STD_LOGIC;
signal V_E_CTRL_RETT_shadow_intermed_1 : STD_ULOGIC;
signal RIN_E_CTRL_CNT_intermed_1 : STD_LOGIC_VECTOR(1 downto 0);
signal V_D_INST024_shadow_intermed_2 : STD_LOGIC;
signal V_X_DATA0_shadow_intermed_1 : STD_LOGIC_VECTOR(31 downto 0);
signal V_D_INST04DOWNTO0_shadow_intermed_2 : STD_LOGIC_VECTOR(4 downto 0);
signal V_A_CTRL_LD_shadow_intermed_2 : STD_ULOGIC;
signal V_A_CTRL_TT3DOWNTO0_shadow_intermed_6 : STD_LOGIC_VECTOR(3 downto 0);
signal R_E_CTRL_PC31DOWNTO4_intermed_3 : STD_LOGIC_VECTOR(31 downto 4);
signal RPIN_ERROR_intermed_1 : STD_ULOGIC;
signal RIN_D_INST019_intermed_5 : STD_LOGIC;
signal V_X_CTRL_PC31DOWNTO2_shadow_intermed_3 : STD_LOGIC_VECTOR(31 downto 2);
signal R_W_S_S_intermed_1 : STD_ULOGIC;
signal R_A_CTRL_WICC_intermed_1 : STD_ULOGIC;
signal RIN_A_CTRL_PC31DOWNTO4_intermed_5 : STD_LOGIC_VECTOR(31 downto 4);
signal RIN_D_PC31DOWNTO4_intermed_1 : STD_LOGIC_VECTOR(31 downto 4);
signal EX_JUMP_ADDRESS31DOWNTO4_shadow_intermed_1 : STD_LOGIC_VECTOR(31 downto 4);
signal RIN_D_INST0_intermed_6 : STD_LOGIC_VECTOR(31 downto 0);
signal RIN_D_PC_intermed_5 : STD_LOGIC_VECTOR(31 downto 2);
signal V_D_INST0_shadow_intermed_5 : STD_LOGIC_VECTOR(31 downto 0);
signal V_A_RFA1_shadow_intermed_1 : STD_LOGIC_VECTOR(7 downto 0);
signal R_X_CTRL_PC31DOWNTO2_intermed_1 : STD_LOGIC_VECTOR(31 downto 2);
signal R_D_PC_intermed_2 : STD_LOGIC_VECTOR(31 downto 2);
signal V_A_CTRL_PC3DOWNTO2_shadow_intermed_5 : STD_LOGIC_VECTOR(3 downto 2);
signal RIN_E_SU_intermed_1 : STD_ULOGIC;
signal V_E_CTRL_INST_shadow_intermed_1 : STD_LOGIC_VECTOR(31 downto 0);
signal RIN_M_CTRL_PC_intermed_1 : STD_LOGIC_VECTOR(31 downto 2);
signal R_X_ANNUL_ALL_intermed_4 : STD_ULOGIC;
signal V_D_INST04DOWNTO0_shadow_intermed_1 : STD_LOGIC_VECTOR(4 downto 0);
signal RIN_A_CTRL_INST_intermed_3 : STD_LOGIC_VECTOR(31 downto 0);
signal V_A_CTRL_shadow_intermed_3 : PIPELINE_CTRL_TYPE;
signal R_D_MEXC_intermed_1 : STD_ULOGIC;
signal R_D_INST0_intermed_5 : STD_LOGIC_VECTOR(31 downto 0);
signal RIN_X_CTRL_RETT_intermed_1 : STD_ULOGIC;
signal R_X_RESULT6DOWNTO03DOWNTO0_intermed_1 : STD_LOGIC_VECTOR(3 downto 0);
signal R_A_CTRL_WICC_intermed_2 : STD_ULOGIC;
signal VDSU_CRDY2_shadow_intermed_1 : STD_LOGIC;
signal V_A_DIVSTART_shadow_intermed_1 : STD_ULOGIC;
signal R_A_CTRL_PC31DOWNTO2_intermed_6 : STD_LOGIC_VECTOR(31 downto 2);
signal V_D_INST020_shadow_intermed_2 : STD_LOGIC;
signal RIN_A_CTRL_TRAP_intermed_4 : STD_ULOGIC;
signal RIN_W_S_PS_intermed_1 : STD_ULOGIC;
signal R_D_MEXC_intermed_3 : STD_ULOGIC;
signal IRQI_RUN_intermed_1 : STD_ULOGIC;
signal RIN_A_RFA2_intermed_1 : STD_LOGIC_VECTOR(7 downto 0);
signal V_A_CTRL_PV_shadow_intermed_1 : STD_ULOGIC;
signal R_A_CTRL_PC31DOWNTO4_intermed_1 : STD_LOGIC_VECTOR(31 downto 4);
signal V_X_CTRL_PC31DOWNTO4_shadow_intermed_2 : STD_LOGIC_VECTOR(31 downto 4);
signal RIN_W_S_SVT_intermed_1 : STD_ULOGIC;
signal RIN_E_CTRL_RD6DOWNTO0_intermed_1 : STD_LOGIC_VECTOR(6 downto 0);
signal R_D_PC31DOWNTO12_intermed_5 : STD_LOGIC_VECTOR(31 downto 12);
signal RIN_A_CTRL_INST19_intermed_1 : STD_LOGIC;
signal RIN_D_INST020_intermed_1 : STD_LOGIC;
signal RIN_M_CTRL_PV_intermed_1 : STD_ULOGIC;
signal RIN_A_CTRL_RD6DOWNTO0_intermed_4 : STD_LOGIC_VECTOR(6 downto 0);
signal RIN_E_OP23_intermed_1 : STD_LOGIC;
signal RIN_E_CTRL_WICC_intermed_2 : STD_ULOGIC;
signal R_D_PC31DOWNTO4_intermed_5 : STD_LOGIC_VECTOR(31 downto 4);
signal V_D_MEXC_shadow_intermed_2 : STD_ULOGIC;
signal RIN_D_PC31DOWNTO4_intermed_7 : STD_LOGIC_VECTOR(31 downto 4);
signal R_A_CTRL_TRAP_intermed_3 : STD_ULOGIC;
signal V_E_CTRL_INST19_shadow_intermed_2 : STD_LOGIC;
signal RIN_E_CTRL_PC31DOWNTO12_intermed_5 : STD_LOGIC_VECTOR(31 downto 12);
signal RIN_D_PC31DOWNTO12_intermed_8 : STD_LOGIC_VECTOR(31 downto 12);
signal VP_PWD_shadow_intermed_1 : STD_ULOGIC;
signal RIN_M_CTRL_RD7DOWNTO0_intermed_1 : STD_LOGIC_VECTOR(7 downto 0);
signal V_A_CTRL_PC31DOWNTO4_shadow_intermed_2 : STD_LOGIC_VECTOR(31 downto 4);
signal RIN_F_PC31DOWNTO2_intermed_2 : STD_LOGIC_VECTOR(31 downto 2);
signal RIN_M_NALIGN_intermed_1 : STD_ULOGIC;
signal RIN_X_CTRL_PC3DOWNTO2_intermed_2 : STD_LOGIC_VECTOR(3 downto 2);
signal RP_ERROR_intermed_1 : STD_ULOGIC;
signal V_W_S_TBA_shadow_intermed_1 : STD_LOGIC_VECTOR(19 downto 0);
signal R_F_PC31DOWNTO12_intermed_2 : STD_LOGIC_VECTOR(31 downto 12);
signal RIN_E_JMPL_intermed_1 : STD_ULOGIC;
signal RIN_A_CTRL_TRAP_intermed_1 : STD_ULOGIC;
signal V_A_SU_shadow_intermed_1 : STD_ULOGIC;
signal RIN_A_RFE2_intermed_1 : STD_ULOGIC;
signal RIN_D_PC_intermed_2 : STD_LOGIC_VECTOR(31 downto 2);
signal RIN_A_CTRL_CNT_intermed_3 : STD_LOGIC_VECTOR(1 downto 0);
signal V_M_CTRL_PC31DOWNTO12_shadow_intermed_3 : STD_LOGIC_VECTOR(31 downto 12);
signal V_M_CTRL_PC3DOWNTO2_shadow_intermed_2 : STD_LOGIC_VECTOR(3 downto 2);
signal VIR_ADDR31DOWNTO12_shadow_intermed_1 : STD_LOGIC_VECTOR(31 downto 12);
signal RIN_E_CTRL_LD_intermed_2 : STD_ULOGIC;
signal V_E_CTRL_PC31DOWNTO12_shadow_intermed_2 : STD_LOGIC_VECTOR(31 downto 12);
signal V_X_CTRL_PC3DOWNTO2_shadow_intermed_2 : STD_LOGIC_VECTOR(3 downto 2);
signal R_E_CTRL_PC31DOWNTO12_intermed_4 : STD_LOGIC_VECTOR(31 downto 12);
signal V_A_CTRL_INST24_shadow_intermed_2 : STD_LOGIC;
signal V_M_CTRL_TRAP_shadow_intermed_1 : STD_ULOGIC;
signal V_E_CTRL_PC31DOWNTO4_shadow_intermed_3 : STD_LOGIC_VECTOR(31 downto 4);
signal V_A_CTRL_PC3DOWNTO2_shadow_intermed_4 : STD_LOGIC_VECTOR(3 downto 2);
signal R_A_CTRL_PC31DOWNTO2_intermed_5 : STD_LOGIC_VECTOR(31 downto 2);
signal R_X_DATA0_intermed_1 : STD_LOGIC_VECTOR(31 downto 0);
signal V_E_CTRL_TT_shadow_intermed_2 : STD_LOGIC_VECTOR(5 downto 0);
signal V_E_MAC_shadow_intermed_2 : STD_ULOGIC;
signal RIN_E_CTRL_INST19_intermed_2 : STD_LOGIC;
signal RIN_D_PC31DOWNTO2_intermed_3 : STD_LOGIC_VECTOR(31 downto 2);
signal IRIN_ADDR_intermed_1 : STD_LOGIC_VECTOR(31 downto 2);
signal RIN_X_ANNUL_ALL_intermed_3 : STD_ULOGIC;
signal RIN_E_CTRL_INST_intermed_2 : STD_LOGIC_VECTOR(31 downto 0);
signal V_X_CTRL_PC_shadow_intermed_2 : STD_LOGIC_VECTOR(31 downto 2);
signal R_M_CTRL_TRAP_intermed_1 : STD_ULOGIC;
signal V_D_CWP_shadow_intermed_2 : STD_LOGIC_VECTOR(2 downto 0);
signal V_A_CTRL_PC31DOWNTO12_shadow_intermed_2 : STD_LOGIC_VECTOR(31 downto 12);
signal V_A_CTRL_LD_shadow_intermed_1 : STD_ULOGIC;
signal R_A_CTRL_INST19_intermed_2 : STD_LOGIC;
signal R_D_INST020_intermed_2 : STD_LOGIC;
signal RIN_X_MEXC_intermed_1 : STD_ULOGIC;
signal RIN_D_MEXC_intermed_4 : STD_ULOGIC;
signal RIN_A_MULSTART_intermed_1 : STD_ULOGIC;
signal RIN_A_CTRL_TT_intermed_1 : STD_LOGIC_VECTOR(5 downto 0);
signal RIN_M_CTRL_TT3DOWNTO0_intermed_2 : STD_LOGIC_VECTOR(3 downto 0);
signal RIN_A_CTRL_intermed_1 : PIPELINE_CTRL_TYPE;
signal R_E_CTRL_WICC_intermed_1 : STD_ULOGIC;
signal RIN_M_CTRL_TT3DOWNTO0_intermed_3 : STD_LOGIC_VECTOR(3 downto 0);
signal V_A_CTRL_PC31DOWNTO2_shadow_intermed_4 : STD_LOGIC_VECTOR(31 downto 2);
signal V_A_CTRL_TT3DOWNTO0_shadow_intermed_1 : STD_LOGIC_VECTOR(3 downto 0);
signal RIN_M_DCI_SIGNED_intermed_2 : STD_ULOGIC;
signal V_E_CTRL_TT3DOWNTO0_shadow_intermed_3 : STD_LOGIC_VECTOR(3 downto 0);
signal IRIN_ADDR31DOWNTO4_intermed_1 : STD_LOGIC_VECTOR(31 downto 4);
signal RIN_X_SET_intermed_1 : STD_LOGIC_VECTOR(0 downto 0);
signal V_M_CTRL_WREG_shadow_intermed_2 : STD_ULOGIC;
signal RIN_X_CTRL_PC31DOWNTO12_intermed_4 : STD_LOGIC_VECTOR(31 downto 12);
signal V_D_PC_shadow_intermed_5 : STD_LOGIC_VECTOR(31 downto 2);
signal RIN_X_CTRL_TT3DOWNTO0_intermed_2 : STD_LOGIC_VECTOR(3 downto 0);
signal R_D_INST0_intermed_1 : STD_LOGIC_VECTOR(31 downto 0);
signal R_E_CTRL_PC31DOWNTO4_intermed_4 : STD_LOGIC_VECTOR(31 downto 4);
signal RIN_D_CNT_intermed_1 : STD_LOGIC_VECTOR(1 downto 0);
signal R_E_CTRL_PC3DOWNTO2_intermed_4 : STD_LOGIC_VECTOR(3 downto 2);
signal V_M_DCI_SIGNED_shadow_intermed_2 : STD_ULOGIC;
signal R_D_CNT_intermed_2 : STD_LOGIC_VECTOR(1 downto 0);
signal R_E_CTRL_INST20_intermed_1 : STD_LOGIC;
signal RIN_M_DCI_SIGNED_intermed_1 : STD_ULOGIC;
signal RIN_D_PC3DOWNTO2_intermed_5 : STD_LOGIC_VECTOR(3 downto 2);
signal RIN_A_CTRL_INST19_intermed_3 : STD_LOGIC;
signal V_E_CTRL_shadow_intermed_1 : PIPELINE_CTRL_TYPE;
signal RIN_A_CTRL_WICC_intermed_1 : STD_ULOGIC;
signal RIN_D_CWP_intermed_2 : STD_LOGIC_VECTOR(2 downto 0);
signal V_A_CTRL_WREG_shadow_intermed_2 : STD_ULOGIC;
signal R_E_CTRL_INST24_intermed_2 : STD_LOGIC;
signal R_M_CTRL_TT_intermed_1 : STD_LOGIC_VECTOR(5 downto 0);
signal RIN_E_CTRL_WREG_intermed_3 : STD_ULOGIC;
signal V_E_YMSB_shadow_intermed_1 : STD_ULOGIC;
signal EX_JUMP_ADDRESS3DOWNTO2_shadow_intermed_1 : STD_LOGIC_VECTOR(3 downto 2);
signal IRIN_ADDR31DOWNTO2_intermed_3 : STD_LOGIC_VECTOR(31 downto 2);
signal V_M_CTRL_INST_shadow_intermed_2 : STD_LOGIC_VECTOR(31 downto 0);
signal DE_INST24_shadow_intermed_3 : STD_LOGIC;
signal V_D_PC31DOWNTO12_shadow_intermed_2 : STD_LOGIC_VECTOR(31 downto 12);
signal V_A_CTRL_PC_shadow_intermed_1 : STD_LOGIC_VECTOR(31 downto 2);
signal RIN_X_RESULT6DOWNTO0_intermed_1 : STD_LOGIC_VECTOR(6 downto 0);
signal R_A_CTRL_PC31DOWNTO2_intermed_2 : STD_LOGIC_VECTOR(31 downto 2);
signal V_E_CTRL_CNT_shadow_intermed_1 : STD_LOGIC_VECTOR(1 downto 0);
signal VIR_ADDR3DOWNTO2_shadow_intermed_1 : STD_LOGIC_VECTOR(3 downto 2);
signal RIN_A_CTRL_INST_intermed_2 : STD_LOGIC_VECTOR(31 downto 0);
signal RIN_A_CTRL_intermed_3 : PIPELINE_CTRL_TYPE;
signal RIN_M_RESULT1DOWNTO0_intermed_1 : STD_LOGIC_VECTOR(1 downto 0);
signal R_D_INST024_intermed_1 : STD_LOGIC;
signal R_A_CTRL_PV_intermed_3 : STD_ULOGIC;
signal R_D_PC31DOWNTO2_intermed_1 : STD_LOGIC_VECTOR(31 downto 2);
signal R_A_CTRL_PC31DOWNTO4_intermed_5 : STD_LOGIC_VECTOR(31 downto 4);
signal RIN_A_DIVSTART_intermed_1 : STD_ULOGIC;
signal VIR_ADDR31DOWNTO12_shadow_intermed_2 : STD_LOGIC_VECTOR(31 downto 12);
signal V_E_CTRL_INST20_shadow_intermed_2 : STD_LOGIC;
signal RIN_M_CTRL_TT_intermed_1 : STD_LOGIC_VECTOR(5 downto 0);
signal RIN_E_CTRL_RD7DOWNTO0_intermed_3 : STD_LOGIC_VECTOR(7 downto 0);
signal RIN_D_CWP_intermed_1 : STD_LOGIC_VECTOR(2 downto 0);
signal RIN_X_CTRL_WREG_intermed_1 : STD_ULOGIC;
signal RIN_X_CTRL_PC31DOWNTO2_intermed_4 : STD_LOGIC_VECTOR(31 downto 2);
signal V_M_CTRL_PC31DOWNTO2_shadow_intermed_5 : STD_LOGIC_VECTOR(31 downto 2);
signal V_D_INST0_shadow_intermed_4 : STD_LOGIC_VECTOR(31 downto 0);
signal RIN_D_PC31DOWNTO2_intermed_7 : STD_LOGIC_VECTOR(31 downto 2);
signal RIN_X_CTRL_PC31DOWNTO2_intermed_1 : STD_LOGIC_VECTOR(31 downto 2);
signal DSUR_CRDY2_intermed_1 : STD_LOGIC;
signal R_E_CTRL_PC3DOWNTO2_intermed_2 : STD_LOGIC_VECTOR(3 downto 2);
signal V_A_CTRL_RD7DOWNTO0_shadow_intermed_1 : STD_LOGIC_VECTOR(7 downto 0);
signal R_D_PC31DOWNTO12_intermed_3 : STD_LOGIC_VECTOR(31 downto 12);
signal RIN_X_DATA031_intermed_2 : STD_LOGIC;
signal RIN_D_PC31DOWNTO4_intermed_4 : STD_LOGIC_VECTOR(31 downto 4);
signal RIN_A_CTRL_INST_intermed_4 : STD_LOGIC_VECTOR(31 downto 0);
signal V_X_CTRL_PC31DOWNTO2_shadow_intermed_2 : STD_LOGIC_VECTOR(31 downto 2);
signal V_M_CTRL_PC31DOWNTO4_shadow_intermed_2 : STD_LOGIC_VECTOR(31 downto 4);
signal DE_INST19_shadow_intermed_1 : STD_LOGIC;
signal RIN_E_CTRL_PC31DOWNTO2_intermed_3 : STD_LOGIC_VECTOR(31 downto 2);
signal V_A_CTRL_RD7DOWNTO0_shadow_intermed_2 : STD_LOGIC_VECTOR(7 downto 0);
signal V_E_CTRL_INST_shadow_intermed_3 : STD_LOGIC_VECTOR(31 downto 0);
signal RIN_X_CTRL_PC31DOWNTO2_intermed_2 : STD_LOGIC_VECTOR(31 downto 2);
signal RIN_X_CTRL_intermed_1 : PIPELINE_CTRL_TYPE;
signal R_D_PC31DOWNTO12_intermed_1 : STD_LOGIC_VECTOR(31 downto 12);
signal RIN_A_CTRL_ANNUL_intermed_2 : STD_ULOGIC;
signal V_A_CTRL_CNT_shadow_intermed_3 : STD_LOGIC_VECTOR(1 downto 0);
signal R_A_CTRL_PC31DOWNTO12_intermed_6 : STD_LOGIC_VECTOR(31 downto 12);
signal V_M_CTRL_PC31DOWNTO12_shadow_intermed_4 : STD_LOGIC_VECTOR(31 downto 12);
signal VIR_ADDR31DOWNTO2_shadow_intermed_3 : STD_LOGIC_VECTOR(31 downto 2);
signal RIN_X_Y7DOWNTO0_intermed_1 : STD_LOGIC_VECTOR(7 downto 0);
signal V_A_MULSTART_shadow_intermed_1 : STD_ULOGIC;
signal RIN_E_CTRL_PC_intermed_2 : STD_LOGIC_VECTOR(31 downto 2);
signal V_E_CTRL_PC31DOWNTO12_shadow_intermed_5 : STD_LOGIC_VECTOR(31 downto 12);
signal V_M_DCI_SIZE_shadow_intermed_1 : STD_LOGIC_VECTOR(1 downto 0);
signal V_A_CTRL_PC31DOWNTO4_shadow_intermed_3 : STD_LOGIC_VECTOR(31 downto 4);
signal R_X_RESULT6DOWNTO03DOWNTO0_intermed_3 : STD_LOGIC_VECTOR(3 downto 0);
signal R_D_PC31DOWNTO4_intermed_6 : STD_LOGIC_VECTOR(31 downto 4);
signal EX_ADD_RES32DOWNTO332DOWNTO3_shadow_intermed_2 : STD_LOGIC_VECTOR(32 downto 3);
signal V_A_CTRL_PV_shadow_intermed_4 : STD_ULOGIC;
signal V_A_CTRL_TT_shadow_intermed_4 : STD_LOGIC_VECTOR(5 downto 0);
signal V_X_CTRL_PC3DOWNTO2_shadow_intermed_3 : STD_LOGIC_VECTOR(3 downto 2);
signal RIN_X_DATA0_intermed_2 : STD_LOGIC_VECTOR(31 downto 0);
signal R_A_CTRL_TT3DOWNTO0_intermed_4 : STD_LOGIC_VECTOR(3 downto 0);
signal RIN_D_PC31DOWNTO4_intermed_3 : STD_LOGIC_VECTOR(31 downto 4);
signal RIN_A_CTRL_PC3DOWNTO2_intermed_1 : STD_LOGIC_VECTOR(3 downto 2);
signal V_A_CTRL_WREG_shadow_intermed_4 : STD_ULOGIC;
signal R_D_INST020_intermed_3 : STD_LOGIC;
signal RIN_D_PC31DOWNTO2_intermed_2 : STD_LOGIC_VECTOR(31 downto 2);
signal R_M_CTRL_PC_intermed_2 : STD_LOGIC_VECTOR(31 downto 2);
signal R_F_PC31DOWNTO2_intermed_2 : STD_LOGIC_VECTOR(31 downto 2);
signal V_D_INST020_shadow_intermed_4 : STD_LOGIC;
signal RIN_M_CTRL_WREG_intermed_1 : STD_ULOGIC;
signal RIN_W_WREG_intermed_1 : STD_ULOGIC;
signal RIN_D_PC31DOWNTO4_intermed_6 : STD_LOGIC_VECTOR(31 downto 4);
signal R_D_ANNUL_intermed_1 : STD_ULOGIC;
signal R_A_CTRL_INST_intermed_3 : STD_LOGIC_VECTOR(31 downto 0);
signal V_D_INST020_shadow_intermed_3 : STD_LOGIC;
signal RIN_M_CTRL_PC31DOWNTO2_intermed_2 : STD_LOGIC_VECTOR(31 downto 2);
signal RIN_E_CTRL_WREG_intermed_2 : STD_ULOGIC;
signal V_E_SARI_shadow_intermed_1 : STD_ULOGIC;
signal R_E_CTRL_RD6DOWNTO0_intermed_2 : STD_LOGIC_VECTOR(6 downto 0);
signal V_A_CTRL_PC31DOWNTO2_shadow_intermed_6 : STD_LOGIC_VECTOR(31 downto 2);
signal R_A_CTRL_CNT_intermed_3 : STD_LOGIC_VECTOR(1 downto 0);
signal V_D_INST019_shadow_intermed_4 : STD_LOGIC;
signal RIN_M_CTRL_PV_intermed_2 : STD_ULOGIC;
signal R_A_CTRL_LD_intermed_1 : STD_ULOGIC;
signal V_E_CTRL_WICC_shadow_intermed_2 : STD_ULOGIC;
signal RIN_D_PC31DOWNTO2_intermed_5 : STD_LOGIC_VECTOR(31 downto 2);
signal V_D_PC3DOWNTO2_shadow_intermed_3 : STD_LOGIC_VECTOR(3 downto 2);
signal RIN_A_CTRL_PC3DOWNTO2_intermed_6 : STD_LOGIC_VECTOR(3 downto 2);
signal RIN_X_DATA04DOWNTO0_intermed_1 : STD_LOGIC_VECTOR(4 downto 0);
signal DSUIN_CRDY2_intermed_1 : STD_LOGIC;
signal RIN_D_PC31DOWNTO12_intermed_4 : STD_LOGIC_VECTOR(31 downto 12);
signal R_E_CTRL_RD6DOWNTO0_intermed_1 : STD_LOGIC_VECTOR(6 downto 0);
signal RIN_A_CTRL_INST20_intermed_1 : STD_LOGIC;
signal R_M_RESULT1DOWNTO0_intermed_2 : STD_LOGIC_VECTOR(1 downto 0);
signal RIN_M_DCI_SIZE_intermed_2 : STD_LOGIC_VECTOR(1 downto 0);
signal DE_INST19_shadow_intermed_3 : STD_LOGIC;
signal IRIN_ADDR31DOWNTO12_intermed_2 : STD_LOGIC_VECTOR(31 downto 12);
signal V_A_CTRL_ANNUL_shadow_intermed_4 : STD_ULOGIC;
signal R_E_CTRL_CNT_intermed_1 : STD_LOGIC_VECTOR(1 downto 0);
signal V_E_CTRL_INST24_shadow_intermed_2 : STD_LOGIC;
signal RIN_A_CTRL_PC31DOWNTO4_intermed_2 : STD_LOGIC_VECTOR(31 downto 4);
signal IRIN_PWD_intermed_1 : STD_ULOGIC;
signal V_D_MEXC_shadow_intermed_5 : STD_ULOGIC;
signal RIN_A_CTRL_PV_intermed_1 : STD_ULOGIC;
signal V_A_CTRL_WICC_shadow_intermed_1 : STD_ULOGIC;
signal R_A_CTRL_PC_intermed_1 : STD_LOGIC_VECTOR(31 downto 2);
signal V_F_PC31DOWNTO4_shadow_intermed_1 : STD_LOGIC_VECTOR(31 downto 4);
signal R_A_CTRL_RD7DOWNTO0_intermed_3 : STD_LOGIC_VECTOR(7 downto 0);
signal RIN_A_CTRL_PC_intermed_1 : STD_LOGIC_VECTOR(31 downto 2);
signal RIN_D_INST0_intermed_5 : STD_LOGIC_VECTOR(31 downto 0);
signal V_D_INST024_shadow_intermed_1 : STD_LOGIC;
signal R_E_CTRL_INST_intermed_1 : STD_LOGIC_VECTOR(31 downto 0);
signal R_E_CTRL_PC31DOWNTO4_intermed_1 : STD_LOGIC_VECTOR(31 downto 4);
signal V_A_CTRL_TRAP_shadow_intermed_4 : STD_ULOGIC;
signal R_A_CTRL_PC3DOWNTO2_intermed_5 : STD_LOGIC_VECTOR(3 downto 2);
signal V_A_CTRL_PC31DOWNTO2_shadow_intermed_2 : STD_LOGIC_VECTOR(31 downto 2);
signal V_F_PC31DOWNTO12_shadow_intermed_1 : STD_LOGIC_VECTOR(31 downto 12);
signal R_A_CTRL_CNT_intermed_1 : STD_LOGIC_VECTOR(1 downto 0);
signal RIN_D_PC31DOWNTO2_intermed_6 : STD_LOGIC_VECTOR(31 downto 2);
signal R_E_CTRL_PC3DOWNTO2_intermed_1 : STD_LOGIC_VECTOR(3 downto 2);
signal RIN_X_DATA0_intermed_1 : STD_LOGIC_VECTOR(31 downto 0);
signal RIN_E_CTRL_PC_intermed_3 : STD_LOGIC_VECTOR(31 downto 2);
signal V_D_INST020_shadow_intermed_5 : STD_LOGIC;
signal R_X_CTRL_PC31DOWNTO12_intermed_1 : STD_LOGIC_VECTOR(31 downto 12);
signal RIN_X_DATA03_intermed_1 : STD_LOGIC;
signal R_X_DATA04DOWNTO0_intermed_2 : STD_LOGIC_VECTOR(4 downto 0);
signal R_E_CTRL_ANNUL_intermed_1 : STD_ULOGIC;
signal V_A_CTRL_RD7DOWNTO0_shadow_intermed_3 : STD_LOGIC_VECTOR(7 downto 0);
signal V_M_CTRL_TT3DOWNTO0_shadow_intermed_3 : STD_LOGIC_VECTOR(3 downto 0);
signal RIN_X_MAC_intermed_1 : STD_ULOGIC;
signal V_E_SHCNT_shadow_intermed_1 : STD_LOGIC_VECTOR(4 downto 0);
signal V_M_CTRL_TT3DOWNTO0_shadow_intermed_2 : STD_LOGIC_VECTOR(3 downto 0);
signal V_D_PC31DOWNTO12_shadow_intermed_4 : STD_LOGIC_VECTOR(31 downto 12);
signal RIN_D_PC31DOWNTO12_intermed_2 : STD_LOGIC_VECTOR(31 downto 12);
signal V_E_CTRL_PC3DOWNTO2_shadow_intermed_5 : STD_LOGIC_VECTOR(3 downto 2);
signal RIN_E_CTRL_RETT_intermed_2 : STD_ULOGIC;
signal R_M_CTRL_PC31DOWNTO2_intermed_2 : STD_LOGIC_VECTOR(31 downto 2);
signal V_E_OP23_shadow_intermed_1 : STD_LOGIC;
signal V_D_PC_shadow_intermed_2 : STD_LOGIC_VECTOR(31 downto 2);
signal R_D_PC3DOWNTO2_intermed_6 : STD_LOGIC_VECTOR(3 downto 2);
signal R_M_CTRL_PV_intermed_1 : STD_ULOGIC;
signal RIN_W_RESULT_intermed_1 : STD_LOGIC_VECTOR(31 downto 0);
signal V_E_CTRL_ANNUL_shadow_intermed_2 : STD_ULOGIC;
signal V_E_CTRL_PV_shadow_intermed_1 : STD_ULOGIC;
signal RIN_X_LADDR_intermed_1 : STD_LOGIC_VECTOR(1 downto 0);
signal RIN_A_CTRL_PC_intermed_5 : STD_LOGIC_VECTOR(31 downto 2);
signal XC_VECTT3DOWNTO0_shadow_intermed_1 : STD_LOGIC_VECTOR(3 downto 0);
signal R_E_CTRL_WREG_intermed_1 : STD_ULOGIC;
signal RIN_X_DATA03_intermed_2 : STD_LOGIC;
signal RIN_A_CTRL_TT_intermed_3 : STD_LOGIC_VECTOR(5 downto 0);
signal V_D_STEP_shadow_intermed_1 : STD_ULOGIC;
signal R_M_CTRL_PC31DOWNTO12_intermed_1 : STD_LOGIC_VECTOR(31 downto 12);
signal DE_INST19_shadow_intermed_2 : STD_LOGIC;
signal RIN_M_CTRL_PC31DOWNTO2_intermed_3 : STD_LOGIC_VECTOR(31 downto 2);
signal V_X_CTRL_TRAP_shadow_intermed_1 : STD_ULOGIC;
signal RIN_D_MEXC_intermed_5 : STD_ULOGIC;
signal RIN_X_CTRL_TRAP_intermed_1 : STD_ULOGIC;
signal V_D_PC3DOWNTO2_shadow_intermed_4 : STD_LOGIC_VECTOR(3 downto 2);
signal V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_1 : STD_LOGIC_VECTOR(3 downto 0);
signal RIN_A_CTRL_PC3DOWNTO2_intermed_5 : STD_LOGIC_VECTOR(3 downto 2);
signal RIN_M_CTRL_PC31DOWNTO4_intermed_3 : STD_LOGIC_VECTOR(31 downto 4);
signal RIN_M_CTRL_PC31DOWNTO2_intermed_4 : STD_LOGIC_VECTOR(31 downto 2);
signal RIN_F_BRANCH_intermed_1 : STD_ULOGIC;
signal R_D_PC3DOWNTO2_intermed_5 : STD_LOGIC_VECTOR(3 downto 2);
signal RIN_D_INST0_intermed_2 : STD_LOGIC_VECTOR(31 downto 0);
signal RIN_A_CTRL_WREG_intermed_1 : STD_ULOGIC;
signal R_M_CTRL_CNT_intermed_1 : STD_LOGIC_VECTOR(1 downto 0);
signal RIN_E_CTRL_RD7DOWNTO0_intermed_1 : STD_LOGIC_VECTOR(7 downto 0);
signal RIN_A_CTRL_PC_intermed_2 : STD_LOGIC_VECTOR(31 downto 2);
signal RIN_X_CTRL_PC_intermed_1 : STD_LOGIC_VECTOR(31 downto 2);
signal RIN_D_INST024_intermed_4 : STD_LOGIC;
signal R_A_SU_intermed_1 : STD_ULOGIC;
signal RIN_A_CTRL_TT_intermed_4 : STD_LOGIC_VECTOR(5 downto 0);
signal V_X_DATA00_shadow_intermed_2 : STD_LOGIC;
signal RIN_A_CTRL_PC31DOWNTO4_intermed_4 : STD_LOGIC_VECTOR(31 downto 4);
signal RIN_A_JMPL_intermed_1 : STD_ULOGIC;
signal V_E_CTRL_WREG_shadow_intermed_3 : STD_ULOGIC;
signal V_A_CTRL_WREG_shadow_intermed_1 : STD_ULOGIC;
signal RIN_M_CTRL_ANNUL_intermed_1 : STD_ULOGIC;
signal V_W_S_Y7DOWNTO0_shadow_intermed_1 : STD_LOGIC_VECTOR(7 downto 0);
signal RIN_X_CTRL_PC31DOWNTO12_intermed_1 : STD_LOGIC_VECTOR(31 downto 12);
signal VIR_ADDR31DOWNTO2_shadow_intermed_1 : STD_LOGIC_VECTOR(31 downto 2);
signal R_D_INST020_intermed_4 : STD_LOGIC;
signal V_A_CTRL_PC3DOWNTO2_shadow_intermed_1 : STD_LOGIC_VECTOR(3 downto 2);
signal RIN_E_CTRL_TT3DOWNTO0_intermed_3 : STD_LOGIC_VECTOR(3 downto 0);
signal RIN_M_CTRL_RD7DOWNTO0_intermed_2 : STD_LOGIC_VECTOR(7 downto 0);
signal V_E_CTRL_TRAP_shadow_intermed_3 : STD_ULOGIC;
signal V_A_CTRL_CNT_shadow_intermed_2 : STD_LOGIC_VECTOR(1 downto 0);
signal V_E_CTRL_ANNUL_shadow_intermed_1 : STD_ULOGIC;
signal V_W_S_TT3DOWNTO0_shadow_intermed_1 : STD_LOGIC_VECTOR(3 downto 0);
signal RIN_M_CTRL_CNT_intermed_1 : STD_LOGIC_VECTOR(1 downto 0);
signal DSUR_CRDY2_intermed_2 : STD_LOGIC;
signal V_E_CTRL_RD6DOWNTO0_shadow_intermed_1 : STD_LOGIC_VECTOR(6 downto 0);
signal V_A_CTRL_CNT_shadow_intermed_1 : STD_LOGIC_VECTOR(1 downto 0);
signal R_E_CTRL_PC_intermed_1 : STD_LOGIC_VECTOR(31 downto 2);
signal RIN_M_SU_intermed_1 : STD_ULOGIC;
signal RIN_A_CTRL_RD6DOWNTO0_intermed_1 : STD_LOGIC_VECTOR(6 downto 0);
signal R_M_CTRL_TT3DOWNTO0_intermed_3 : STD_LOGIC_VECTOR(3 downto 0);
signal RIN_M_CTRL_TT3DOWNTO0_intermed_4 : STD_LOGIC_VECTOR(3 downto 0);
signal V_A_CTRL_INST19_shadow_intermed_1 : STD_LOGIC;
signal R_D_PC31DOWNTO2_intermed_5 : STD_LOGIC_VECTOR(31 downto 2);
signal RIN_E_CTRL_CNT_intermed_3 : STD_LOGIC_VECTOR(1 downto 0);
signal R_E_CTRL_PC31DOWNTO12_intermed_3 : STD_LOGIC_VECTOR(31 downto 12);
signal RIN_E_CTRL_TRAP_intermed_1 : STD_ULOGIC;
signal RIN_X_DATA00_intermed_3 : STD_LOGIC;
signal R_E_CTRL_PC_intermed_2 : STD_LOGIC_VECTOR(31 downto 2);
signal V_X_Y7DOWNTO0_shadow_intermed_1 : STD_LOGIC_VECTOR(7 downto 0);
signal RIN_E_OP131_intermed_1 : STD_LOGIC;
signal R_D_CNT_intermed_1 : STD_LOGIC_VECTOR(1 downto 0);
signal R_D_PC_intermed_3 : STD_LOGIC_VECTOR(31 downto 2);
signal RIN_A_CTRL_PC31DOWNTO12_intermed_2 : STD_LOGIC_VECTOR(31 downto 12);
signal R_M_CTRL_WREG_intermed_1 : STD_ULOGIC;
signal R_D_PC31DOWNTO2_intermed_4 : STD_LOGIC_VECTOR(31 downto 2);
signal DE_INST_shadow_intermed_3 : STD_LOGIC_VECTOR(31 downto 0);
signal RIN_D_PC_intermed_3 : STD_LOGIC_VECTOR(31 downto 2);
signal V_A_CTRL_INST20_shadow_intermed_3 : STD_LOGIC;
signal R_A_CTRL_TT3DOWNTO0_intermed_5 : STD_LOGIC_VECTOR(3 downto 0);
signal RIN_A_CTRL_CNT_intermed_2 : STD_LOGIC_VECTOR(1 downto 0);
signal RIN_A_CTRL_intermed_2 : PIPELINE_CTRL_TYPE;
signal RIN_X_CTRL_PC_intermed_2 : STD_LOGIC_VECTOR(31 downto 2);
signal R_A_CTRL_WREG_intermed_1 : STD_ULOGIC;
signal V_X_CTRL_PC31DOWNTO2_shadow_intermed_4 : STD_LOGIC_VECTOR(31 downto 2);
signal R_X_CTRL_PC31DOWNTO2_intermed_3 : STD_LOGIC_VECTOR(31 downto 2);
signal RIN_D_PC_intermed_6 : STD_LOGIC_VECTOR(31 downto 2);
signal RIN_E_CTRL_PC31DOWNTO4_intermed_3 : STD_LOGIC_VECTOR(31 downto 4);
signal R_X_CTRL_PC31DOWNTO2_intermed_2 : STD_LOGIC_VECTOR(31 downto 2);
signal V_A_ET_shadow_intermed_1 : STD_ULOGIC;
signal V_E_CTRL_PC31DOWNTO4_shadow_intermed_1 : STD_LOGIC_VECTOR(31 downto 4);
signal R_D_INST0_intermed_3 : STD_LOGIC_VECTOR(31 downto 0);
signal R_D_INST04DOWNTO0_intermed_1 : STD_LOGIC_VECTOR(4 downto 0);
signal RIN_A_CTRL_INST20_intermed_3 : STD_LOGIC;
signal RIN_W_EXCEPT_intermed_1 : STD_ULOGIC;
signal V_X_DATA031_shadow_intermed_2 : STD_LOGIC;
signal R_A_CTRL_ANNUL_intermed_1 : STD_ULOGIC;
signal R_F_PC31DOWNTO12_intermed_1 : STD_LOGIC_VECTOR(31 downto 12);
signal RIN_E_CTRL_RD6DOWNTO0_intermed_2 : STD_LOGIC_VECTOR(6 downto 0);
signal VIR_ADDR31DOWNTO2_shadow_intermed_2 : STD_LOGIC_VECTOR(31 downto 2);
signal RIN_X_DATA00_intermed_1 : STD_LOGIC;
signal RIN_E_CTRL_ANNUL_intermed_1 : STD_ULOGIC;
signal RIN_E_CTRL_PC31DOWNTO4_intermed_5 : STD_LOGIC_VECTOR(31 downto 4);
signal V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_3 : STD_LOGIC_VECTOR(3 downto 0);
signal V_M_CTRL_WICC_shadow_intermed_1 : STD_ULOGIC;
signal V_A_CTRL_PC31DOWNTO2_shadow_intermed_7 : STD_LOGIC_VECTOR(31 downto 2);
signal RIN_A_CTRL_RETT_intermed_1 : STD_ULOGIC;
signal RIN_E_CTRL_PC31DOWNTO2_intermed_1 : STD_LOGIC_VECTOR(31 downto 2);
signal V_E_CTRL_PC31DOWNTO2_shadow_intermed_1 : STD_LOGIC_VECTOR(31 downto 2);
signal RIN_D_PC31DOWNTO12_intermed_5 : STD_LOGIC_VECTOR(31 downto 12);
signal VIR_ADDR3DOWNTO2_shadow_intermed_2 : STD_LOGIC_VECTOR(3 downto 2);
signal R_A_CTRL_PV_intermed_2 : STD_ULOGIC;
signal V_A_CTRL_PC3DOWNTO2_shadow_intermed_2 : STD_LOGIC_VECTOR(3 downto 2);
signal R_E_CTRL_PC3DOWNTO2_intermed_3 : STD_LOGIC_VECTOR(3 downto 2);
signal V_A_CTRL_ANNUL_shadow_intermed_3 : STD_ULOGIC;
signal RIN_A_CTRL_PC3DOWNTO2_intermed_4 : STD_LOGIC_VECTOR(3 downto 2);
signal R_A_CTRL_PC3DOWNTO2_intermed_2 : STD_LOGIC_VECTOR(3 downto 2);
signal V_A_CTRL_TT3DOWNTO0_shadow_intermed_3 : STD_LOGIC_VECTOR(3 downto 0);
signal V_D_CNT_shadow_intermed_2 : STD_LOGIC_VECTOR(1 downto 0);
signal V_M_CTRL_ANNUL_shadow_intermed_1 : STD_ULOGIC;
signal V_E_CTRL_PC31DOWNTO2_shadow_intermed_2 : STD_LOGIC_VECTOR(31 downto 2);
signal RIN_M_CTRL_PC31DOWNTO4_intermed_2 : STD_LOGIC_VECTOR(31 downto 4);
signal R_M_CTRL_TT3DOWNTO0_intermed_1 : STD_LOGIC_VECTOR(3 downto 0);
signal V_E_CTRL_LD_shadow_intermed_2 : STD_ULOGIC;
signal RIN_X_CTRL_ANNUL_intermed_1 : STD_ULOGIC;
signal RIN_D_PC3DOWNTO2_intermed_3 : STD_LOGIC_VECTOR(3 downto 2);
signal V_A_CTRL_PC31DOWNTO2_shadow_intermed_3 : STD_LOGIC_VECTOR(31 downto 2);
signal RIN_E_CTRL_TT_intermed_2 : STD_LOGIC_VECTOR(5 downto 0);
signal RIN_E_CTRL_CNT_intermed_2 : STD_LOGIC_VECTOR(1 downto 0);
signal RIN_A_CTRL_PC_intermed_4 : STD_LOGIC_VECTOR(31 downto 2);
signal R_D_INST019_intermed_4 : STD_LOGIC;
signal V_D_INST020_shadow_intermed_1 : STD_LOGIC;
signal RIN_W_S_ASR18_intermed_1 : STD_LOGIC_VECTOR(31 downto 0);
signal RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_4 : STD_LOGIC_VECTOR(3 downto 0);
signal R_D_PC31DOWNTO12_intermed_2 : STD_LOGIC_VECTOR(31 downto 12);
signal XC_TRAP_ADDRESS31DOWNTO4_shadow_intermed_1 : STD_LOGIC_VECTOR(31 downto 4);
signal V_D_INST0_shadow_intermed_6 : STD_LOGIC_VECTOR(31 downto 0);
signal V_W_S_TT3DOWNTO0_shadow_intermed_2 : STD_LOGIC_VECTOR(3 downto 0);
signal RIN_A_CTRL_INST24_intermed_3 : STD_LOGIC;
signal RIN_E_CTRL_RD7DOWNTO0_intermed_2 : STD_LOGIC_VECTOR(7 downto 0);
signal RIN_A_CTRL_INST24_intermed_1 : STD_LOGIC;
signal RIN_D_PC31DOWNTO4_intermed_2 : STD_LOGIC_VECTOR(31 downto 4);
signal V_A_CTRL_shadow_intermed_2 : PIPELINE_CTRL_TYPE;
signal DE_INST_shadow_intermed_4 : STD_LOGIC_VECTOR(31 downto 0);
signal RIN_E_CTRL_PV_intermed_3 : STD_ULOGIC;
signal V_A_CTRL_TT_shadow_intermed_2 : STD_LOGIC_VECTOR(5 downto 0);
signal RIN_M_CTRL_PC_intermed_3 : STD_LOGIC_VECTOR(31 downto 2);
signal V_A_CTRL_WREG_shadow_intermed_3 : STD_ULOGIC;
signal R_M_CTRL_RD6DOWNTO0_intermed_1 : STD_LOGIC_VECTOR(6 downto 0);
signal XC_TRAP_ADDRESS31DOWNTO2_shadow_intermed_1 : STD_LOGIC_VECTOR(31 downto 2);
signal RIN_A_CTRL_PV_intermed_2 : STD_ULOGIC;
signal RIN_E_CTRL_PC3DOWNTO2_intermed_2 : STD_LOGIC_VECTOR(3 downto 2);
signal RIN_X_CTRL_RD7DOWNTO0_intermed_1 : STD_LOGIC_VECTOR(7 downto 0);
signal V_A_CTRL_TRAP_shadow_intermed_1 : STD_ULOGIC;
signal V_E_CTRL_TRAP_shadow_intermed_1 : STD_ULOGIC;
signal RIN_E_MAC_intermed_1 : STD_ULOGIC;
signal R_X_DATA00_intermed_2 : STD_LOGIC;
signal RIN_E_MAC_intermed_2 : STD_ULOGIC;
signal RIN_A_CTRL_RD7DOWNTO0_intermed_4 : STD_LOGIC_VECTOR(7 downto 0);
signal RIN_A_CTRL_PC31DOWNTO2_intermed_7 : STD_LOGIC_VECTOR(31 downto 2);
signal R_M_CTRL_PC31DOWNTO12_intermed_3 : STD_LOGIC_VECTOR(31 downto 12);
signal V_D_PC_shadow_intermed_3 : STD_LOGIC_VECTOR(31 downto 2);
signal RIN_D_PC31DOWNTO4_intermed_5 : STD_LOGIC_VECTOR(31 downto 4);
signal RIN_D_INST020_intermed_3 : STD_LOGIC;
signal V_M_RESULT1DOWNTO0_shadow_intermed_2 : STD_LOGIC_VECTOR(1 downto 0);
signal R_E_CTRL_PC31DOWNTO4_intermed_2 : STD_LOGIC_VECTOR(31 downto 4);
signal V_E_CTRL_PC31DOWNTO12_shadow_intermed_3 : STD_LOGIC_VECTOR(31 downto 12);
signal V_X_INTACK_shadow_intermed_1 : STD_ULOGIC;
signal RIN_A_CTRL_ANNUL_intermed_5 : STD_ULOGIC;
signal V_M_CTRL_PC31DOWNTO4_shadow_intermed_3 : STD_LOGIC_VECTOR(31 downto 4);
signal V_A_CTRL_TT3DOWNTO0_shadow_intermed_4 : STD_LOGIC_VECTOR(3 downto 0);
signal RIN_X_RESULT_intermed_1 : STD_LOGIC_VECTOR(31 downto 0);
signal RIN_E_CTRL_TT3DOWNTO0_intermed_5 : STD_LOGIC_VECTOR(3 downto 0);
signal RIN_A_CTRL_PC31DOWNTO2_intermed_1 : STD_LOGIC_VECTOR(31 downto 2);
signal EX_JUMP_ADDRESS31DOWNTO2_shadow_intermed_1 : STD_LOGIC_VECTOR(31 downto 2);
signal V_D_PC3DOWNTO2_shadow_intermed_5 : STD_LOGIC_VECTOR(3 downto 2);
signal DE_INST20_shadow_intermed_1 : STD_LOGIC;
signal V_E_CTRL_RD7DOWNTO0_shadow_intermed_2 : STD_LOGIC_VECTOR(7 downto 0);
signal V_X_CTRL_PC31DOWNTO12_shadow_intermed_4 : STD_LOGIC_VECTOR(31 downto 12);
signal V_E_CTRL_TRAP_shadow_intermed_2 : STD_ULOGIC;
signal V_A_CTRL_PC31DOWNTO4_shadow_intermed_5 : STD_LOGIC_VECTOR(31 downto 4);
signal V_A_CTRL_RD6DOWNTO0_shadow_intermed_2 : STD_LOGIC_VECTOR(6 downto 0);
signal RIN_A_CTRL_PC31DOWNTO12_intermed_1 : STD_LOGIC_VECTOR(31 downto 12);
signal IR_ADDR31DOWNTO12_intermed_2 : STD_LOGIC_VECTOR(31 downto 12);
signal RIN_E_ALUCIN_intermed_1 : STD_ULOGIC;
signal R_X_CTRL_PC31DOWNTO12_intermed_2 : STD_LOGIC_VECTOR(31 downto 12);
signal R_A_CTRL_PC3DOWNTO2_intermed_1 : STD_LOGIC_VECTOR(3 downto 2);
signal DE_INST_shadow_intermed_1 : STD_LOGIC_VECTOR(31 downto 0);
signal RIN_M_CTRL_INST_intermed_2 : STD_LOGIC_VECTOR(31 downto 0);
signal R_A_CTRL_TRAP_intermed_2 : STD_ULOGIC;
signal RIN_A_CTRL_PC31DOWNTO12_intermed_4 : STD_LOGIC_VECTOR(31 downto 12);
signal R_A_CTRL_WREG_intermed_2 : STD_ULOGIC;
signal R_M_CTRL_PC31DOWNTO4_intermed_1 : STD_LOGIC_VECTOR(31 downto 4);
signal V_E_OP13_shadow_intermed_1 : STD_LOGIC;
signal V_A_CTRL_INST24_shadow_intermed_1 : STD_LOGIC;
signal V_X_CTRL_PC31DOWNTO12_shadow_intermed_3 : STD_LOGIC_VECTOR(31 downto 12);
signal RIN_D_INST024_intermed_5 : STD_LOGIC;
signal IRIN_ADDR31DOWNTO12_intermed_3 : STD_LOGIC_VECTOR(31 downto 12);
signal V_X_CTRL_PC_shadow_intermed_1 : STD_LOGIC_VECTOR(31 downto 2);
signal R_M_CTRL_PC3DOWNTO2_intermed_3 : STD_LOGIC_VECTOR(3 downto 2);
signal V_D_INST019_shadow_intermed_5 : STD_LOGIC;
signal V_E_CTRL_PC3DOWNTO2_shadow_intermed_2 : STD_LOGIC_VECTOR(3 downto 2);
signal RIN_X_CTRL_TT_intermed_1 : STD_LOGIC_VECTOR(5 downto 0);
signal RIN_D_INST020_intermed_5 : STD_LOGIC;
signal V_M_CTRL_PC31DOWNTO2_shadow_intermed_3 : STD_LOGIC_VECTOR(31 downto 2);
signal RIN_A_CTRL_TT3DOWNTO0_intermed_6 : STD_LOGIC_VECTOR(3 downto 0);
signal RIN_D_PC3DOWNTO2_intermed_7 : STD_LOGIC_VECTOR(3 downto 2);
signal V_A_CTRL_INST_shadow_intermed_2 : STD_LOGIC_VECTOR(31 downto 0);
signal V_X_CTRL_PC31DOWNTO4_shadow_intermed_1 : STD_LOGIC_VECTOR(31 downto 4);
signal V_M_RESULT1DOWNTO0_shadow_intermed_1 : STD_LOGIC_VECTOR(1 downto 0);
signal R_A_CTRL_INST24_intermed_2 : STD_LOGIC;
signal R_F_PC31DOWNTO2_intermed_1 : STD_LOGIC_VECTOR(31 downto 2);
signal V_A_CTRL_TRAP_shadow_intermed_3 : STD_ULOGIC;
signal R_D_CNT_intermed_4 : STD_LOGIC_VECTOR(1 downto 0);
signal RIN_A_CTRL_WREG_intermed_4 : STD_ULOGIC;
signal V_M_CTRL_PC31DOWNTO4_shadow_intermed_1 : STD_LOGIC_VECTOR(31 downto 4);
signal RIN_A_CTRL_PC3DOWNTO2_intermed_3 : STD_LOGIC_VECTOR(3 downto 2);
signal V_E_CTRL_INST20_shadow_intermed_1 : STD_LOGIC;
signal R_D_MEXC_intermed_2 : STD_ULOGIC;
signal R_D_PC_intermed_4 : STD_LOGIC_VECTOR(31 downto 2);
signal RIN_D_PC_intermed_1 : STD_LOGIC_VECTOR(31 downto 2);
signal IRIN_ADDR3DOWNTO2_intermed_1 : STD_LOGIC_VECTOR(3 downto 2);
signal V_E_CTRL_RD7DOWNTO0_shadow_intermed_1 : STD_LOGIC_VECTOR(7 downto 0);
signal RIN_E_OP1_intermed_1 : STD_LOGIC_VECTOR(31 downto 0);
signal V_D_PC31DOWNTO4_shadow_intermed_3 : STD_LOGIC_VECTOR(31 downto 4);
signal V_A_CTRL_PV_shadow_intermed_3 : STD_ULOGIC;
signal V_D_PC31DOWNTO2_shadow_intermed_6 : STD_LOGIC_VECTOR(31 downto 2);
signal V_X_CTRL_TT3DOWNTO0_shadow_intermed_2 : STD_LOGIC_VECTOR(3 downto 0);
signal DE_INST20_shadow_intermed_2 : STD_LOGIC;
signal V_E_CTRL_RD7DOWNTO0_shadow_intermed_3 : STD_LOGIC_VECTOR(7 downto 0);
signal V_E_CTRL_CNT_shadow_intermed_3 : STD_LOGIC_VECTOR(1 downto 0);
signal RIN_E_CTRL_RETT_intermed_1 : STD_ULOGIC;
signal V_D_PC31DOWNTO12_shadow_intermed_3 : STD_LOGIC_VECTOR(31 downto 12);
signal V_D_PC31DOWNTO12_shadow_intermed_7 : STD_LOGIC_VECTOR(31 downto 12);
signal V_M_CTRL_CNT_shadow_intermed_2 : STD_LOGIC_VECTOR(1 downto 0);
signal RIN_A_CTRL_PC3DOWNTO2_intermed_2 : STD_LOGIC_VECTOR(3 downto 2);
signal R_D_PC31DOWNTO4_intermed_3 : STD_LOGIC_VECTOR(31 downto 4);
signal RIN_X_INTACK_intermed_1 : STD_ULOGIC;
signal RIN_E_OP231_intermed_1 : STD_LOGIC;
signal RIN_X_DATA031_intermed_3 : STD_LOGIC;
signal RIN_D_PC31DOWNTO2_intermed_4 : STD_LOGIC_VECTOR(31 downto 2);
signal V_D_PC31DOWNTO4_shadow_intermed_2 : STD_LOGIC_VECTOR(31 downto 4);
signal V_A_CTRL_ANNUL_shadow_intermed_1 : STD_ULOGIC;
signal R_M_CTRL_TT3DOWNTO0_intermed_2 : STD_LOGIC_VECTOR(3 downto 0);
signal V_F_PC_shadow_intermed_1 : STD_LOGIC_VECTOR(31 downto 2);
signal RIN_E_ET_intermed_1 : STD_ULOGIC;
signal V_D_MEXC_shadow_intermed_3 : STD_ULOGIC;
signal XC_TRAP_ADDRESS31DOWNTO2_shadow_intermed_2 : STD_LOGIC_VECTOR(31 downto 2);
signal V_F_PC31DOWNTO2_shadow_intermed_2 : STD_LOGIC_VECTOR(31 downto 2);
signal RIN_D_INST020_intermed_2 : STD_LOGIC;
signal RIN_E_CTRL_PV_intermed_2 : STD_ULOGIC;
signal R_A_CTRL_RD7DOWNTO0_intermed_1 : STD_LOGIC_VECTOR(7 downto 0);
signal ICO_MEXC_intermed_2 : STD_ULOGIC;
signal V_X_DCI_SIGNED_shadow_intermed_1 : STD_ULOGIC;
signal RIN_A_STEP_intermed_1 : STD_ULOGIC;
signal V_E_ALUCIN_shadow_intermed_1 : STD_ULOGIC;
signal V_A_CTRL_PC31DOWNTO4_shadow_intermed_6 : STD_LOGIC_VECTOR(31 downto 4);
signal V_D_CNT_shadow_intermed_3 : STD_LOGIC_VECTOR(1 downto 0);
signal V_D_PC31DOWNTO4_shadow_intermed_1 : STD_LOGIC_VECTOR(31 downto 4);
signal RIN_X_CTRL_CNT_intermed_1 : STD_LOGIC_VECTOR(1 downto 0);
signal V_D_ANNUL_shadow_intermed_1 : STD_ULOGIC;
signal V_E_CTRL_PC31DOWNTO2_shadow_intermed_5 : STD_LOGIC_VECTOR(31 downto 2);
signal V_E_CTRL_PV_shadow_intermed_3 : STD_ULOGIC;
signal VP_ERROR_shadow_intermed_1 : STD_ULOGIC;
signal RIN_X_RESULT6DOWNTO0_intermed_2 : STD_LOGIC_VECTOR(6 downto 0);
signal R_D_PC31DOWNTO4_intermed_1 : STD_LOGIC_VECTOR(31 downto 4);
signal RIN_F_PC31DOWNTO2_intermed_1 : STD_LOGIC_VECTOR(31 downto 2);
signal RIN_D_INST_intermed_1 : ICDTYPE;
signal RIN_E_CTRL_PC_intermed_1 : STD_LOGIC_VECTOR(31 downto 2);
signal R_A_CTRL_PC31DOWNTO12_intermed_1 : STD_LOGIC_VECTOR(31 downto 12);
signal RIN_A_CTRL_PC31DOWNTO12_intermed_6 : STD_LOGIC_VECTOR(31 downto 12);
signal V_A_CTRL_INST24_shadow_intermed_3 : STD_LOGIC;
signal V_D_INST_shadow_intermed_1 : ICDTYPE;
signal V_E_CTRL_PC_shadow_intermed_1 : STD_LOGIC_VECTOR(31 downto 2);
signal V_X_CTRL_RD7DOWNTO0_shadow_intermed_1 : STD_LOGIC_VECTOR(7 downto 0);
signal RIN_M_MUL_intermed_1 : STD_ULOGIC;
signal RIN_A_CTRL_INST20_intermed_2 : STD_LOGIC;
signal RIN_D_INST019_intermed_1 : STD_LOGIC;
signal RIN_A_CTRL_RD7DOWNTO0_intermed_1 : STD_LOGIC_VECTOR(7 downto 0);
signal V_A_CTRL_TT3DOWNTO0_shadow_intermed_2 : STD_LOGIC_VECTOR(3 downto 0);
signal R_A_CTRL_INST_intermed_2 : STD_LOGIC_VECTOR(31 downto 0);
signal RIN_E_CTRL_PC31DOWNTO2_intermed_6 : STD_LOGIC_VECTOR(31 downto 2);
signal V_M_CTRL_TT_shadow_intermed_2 : STD_LOGIC_VECTOR(5 downto 0);
signal V_D_INST0_shadow_intermed_2 : STD_LOGIC_VECTOR(31 downto 0);
signal RIN_M_CTRL_intermed_1 : PIPELINE_CTRL_TYPE;
signal RIN_A_CTRL_RD7DOWNTO0_intermed_3 : STD_LOGIC_VECTOR(7 downto 0);
signal V_D_PC31DOWNTO2_shadow_intermed_1 : STD_LOGIC_VECTOR(31 downto 2);
signal RIN_E_CTRL_PC31DOWNTO4_intermed_2 : STD_LOGIC_VECTOR(31 downto 4);
signal V_D_PC31DOWNTO12_shadow_intermed_8 : STD_LOGIC_VECTOR(31 downto 12);
signal RIN_E_CTRL_LD_intermed_1 : STD_ULOGIC;
signal R_X_CTRL_PC_intermed_1 : STD_LOGIC_VECTOR(31 downto 2);
signal RIN_A_CTRL_WY_intermed_1 : STD_ULOGIC;
signal RIN_D_PC3DOWNTO2_intermed_1 : STD_LOGIC_VECTOR(3 downto 2);
signal R_E_CTRL_INST24_intermed_1 : STD_LOGIC;
signal R_D_INST024_intermed_2 : STD_LOGIC;
signal V_D_INST019_shadow_intermed_3 : STD_LOGIC;
signal V_M_DCI_shadow_intermed_1 : DC_IN_TYPE;
signal V_M_CTRL_shadow_intermed_1 : PIPELINE_CTRL_TYPE;
signal RIN_M_DCI_SIZE_intermed_1 : STD_LOGIC_VECTOR(1 downto 0);
signal R_E_CTRL_PV_intermed_2 : STD_ULOGIC;
signal EX_ADD_RES32DOWNTO3_shadow_intermed_1 : STD_LOGIC_VECTOR(32 downto 3);
signal RIN_D_MEXC_intermed_1 : STD_ULOGIC;
signal R_A_CTRL_PC31DOWNTO2_intermed_3 : STD_LOGIC_VECTOR(31 downto 2);
signal DSUIN_TBUFCNT_intermed_1 : STD_LOGIC_VECTOR(6 downto 0);
signal R_A_CTRL_PC3DOWNTO2_intermed_4 : STD_LOGIC_VECTOR(3 downto 2);
signal R_E_CTRL_PC31DOWNTO12_intermed_5 : STD_LOGIC_VECTOR(31 downto 12);
signal V_A_CTRL_INST20_shadow_intermed_1 : STD_LOGIC;
signal RIN_E_CTRL_PC31DOWNTO12_intermed_3 : STD_LOGIC_VECTOR(31 downto 12);
signal V_A_CTRL_RD6DOWNTO0_shadow_intermed_4 : STD_LOGIC_VECTOR(6 downto 0);
signal R_E_CTRL_PC31DOWNTO2_intermed_4 : STD_LOGIC_VECTOR(31 downto 2);
signal R_A_CTRL_TT3DOWNTO0_intermed_2 : STD_LOGIC_VECTOR(3 downto 0);
signal RIN_A_CTRL_CNT_intermed_4 : STD_LOGIC_VECTOR(1 downto 0);
signal RIN_E_CTRL_INST_intermed_1 : STD_LOGIC_VECTOR(31 downto 0);
signal RIN_X_DEBUG_intermed_1 : STD_ULOGIC;
signal RIN_M_Y_intermed_1 : STD_LOGIC_VECTOR(31 downto 0);
signal RIN_E_SHCNT_intermed_1 : STD_LOGIC_VECTOR(4 downto 0);
signal RIN_E_CTRL_TRAP_intermed_2 : STD_ULOGIC;
signal RIN_F_PC31DOWNTO12_intermed_2 : STD_LOGIC_VECTOR(31 downto 12);
signal R_E_CTRL_INST20_intermed_2 : STD_LOGIC;
signal RIN_A_CTRL_ANNUL_intermed_3 : STD_ULOGIC;
signal RIN_D_ANNUL_intermed_2 : STD_ULOGIC;
signal R_M_CTRL_PC31DOWNTO12_intermed_4 : STD_LOGIC_VECTOR(31 downto 12);
signal V_M_CTRL_TT3DOWNTO0_shadow_intermed_1 : STD_LOGIC_VECTOR(3 downto 0);
signal V_X_CTRL_TT3DOWNTO0_shadow_intermed_1 : STD_LOGIC_VECTOR(3 downto 0);
signal RIN_D_MEXC_intermed_3 : STD_ULOGIC;
signal V_E_CTRL_INST24_shadow_intermed_1 : STD_LOGIC;
signal R_W_S_TT3DOWNTO0_intermed_2 : STD_LOGIC_VECTOR(3 downto 0);
signal DSUIN_CRDY2_intermed_2 : STD_LOGIC;
signal V_X_RESULT6DOWNTO0_shadow_intermed_2 : STD_LOGIC_VECTOR(6 downto 0);
signal RIN_D_PC3DOWNTO2_intermed_2 : STD_LOGIC_VECTOR(3 downto 2);
signal V_D_PC_shadow_intermed_1 : STD_LOGIC_VECTOR(31 downto 2);
signal R_A_CTRL_PC31DOWNTO4_intermed_2 : STD_LOGIC_VECTOR(31 downto 4);
signal RIN_E_CTRL_RD6DOWNTO0_intermed_3 : STD_LOGIC_VECTOR(6 downto 0);
signal R_A_CTRL_PC31DOWNTO12_intermed_4 : STD_LOGIC_VECTOR(31 downto 12);
signal V_X_DATA031_shadow_intermed_1 : STD_LOGIC;
signal RIN_X_ANNUL_ALL_intermed_2 : STD_ULOGIC;
signal IRIN_ADDR3DOWNTO2_intermed_2 : STD_LOGIC_VECTOR(3 downto 2);
signal RIN_D_SET_intermed_1 : STD_LOGIC_VECTOR(0 downto 0);
signal R_E_CTRL_CNT_intermed_2 : STD_LOGIC_VECTOR(1 downto 0);
signal RIN_W_S_S_intermed_2 : STD_ULOGIC;
signal IRIN_ADDR31DOWNTO12_intermed_1 : STD_LOGIC_VECTOR(31 downto 12);
signal RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_3 : STD_LOGIC_VECTOR(3 downto 0);
signal RIN_W_S_TT3DOWNTO0_intermed_2 : STD_LOGIC_VECTOR(3 downto 0);
signal V_A_CTRL_LD_shadow_intermed_3 : STD_ULOGIC;
signal V_E_CTRL_PC31DOWNTO2_shadow_intermed_3 : STD_LOGIC_VECTOR(31 downto 2);
signal RIN_D_INST0_intermed_4 : STD_LOGIC_VECTOR(31 downto 0);
signal V_D_INST0_shadow_intermed_3 : STD_LOGIC_VECTOR(31 downto 0);
signal RIN_M_CTRL_PC_intermed_2 : STD_LOGIC_VECTOR(31 downto 2);
signal V_E_CTRL_shadow_intermed_2 : PIPELINE_CTRL_TYPE;
signal RIN_A_SU_intermed_2 : STD_ULOGIC;
signal R_A_CTRL_RD6DOWNTO0_intermed_2 : STD_LOGIC_VECTOR(6 downto 0);
signal RIN_A_CTRL_PC31DOWNTO2_intermed_3 : STD_LOGIC_VECTOR(31 downto 2);
signal RIN_E_CTRL_intermed_1 : PIPELINE_CTRL_TYPE;
signal RIN_A_CTRL_RD6DOWNTO0_intermed_3 : STD_LOGIC_VECTOR(6 downto 0);
signal RIN_A_CTRL_TT3DOWNTO0_intermed_1 : STD_LOGIC_VECTOR(3 downto 0);
signal RIN_F_PC_intermed_1 : STD_LOGIC_VECTOR(31 downto 2);
signal V_D_PC31DOWNTO2_shadow_intermed_8 : STD_LOGIC_VECTOR(31 downto 2);
signal V_D_CNT_shadow_intermed_1 : STD_LOGIC_VECTOR(1 downto 0);
signal RIN_A_CTRL_LD_intermed_2 : STD_ULOGIC;
signal V_D_PC31DOWNTO4_shadow_intermed_5 : STD_LOGIC_VECTOR(31 downto 4);
signal RIN_M_CTRL_PC31DOWNTO4_intermed_4 : STD_LOGIC_VECTOR(31 downto 4);
signal R_A_CTRL_RETT_intermed_1 : STD_ULOGIC;
signal RIN_E_CTRL_INST_intermed_3 : STD_LOGIC_VECTOR(31 downto 0);
signal R_D_MEXC_intermed_4 : STD_ULOGIC;
signal RIN_M_RESULT1DOWNTO0_intermed_3 : STD_LOGIC_VECTOR(1 downto 0);
signal RIN_D_CNT_intermed_5 : STD_LOGIC_VECTOR(1 downto 0);
signal V_A_CTRL_PC31DOWNTO12_shadow_intermed_1 : STD_LOGIC_VECTOR(31 downto 12);
signal R_D_PC31DOWNTO2_intermed_3 : STD_LOGIC_VECTOR(31 downto 2);
signal RIN_M_CTRL_PC31DOWNTO12_intermed_4 : STD_LOGIC_VECTOR(31 downto 12);
signal RIN_M_CTRL_TT3DOWNTO0_intermed_1 : STD_LOGIC_VECTOR(3 downto 0);
signal RIN_D_ANNUL_intermed_1 : STD_ULOGIC;
signal V_A_CTRL_shadow_intermed_1 : PIPELINE_CTRL_TYPE;
signal RIN_M_CTRL_PC3DOWNTO2_intermed_4 : STD_LOGIC_VECTOR(3 downto 2);
signal V_E_CTRL_PC31DOWNTO12_shadow_intermed_1 : STD_LOGIC_VECTOR(31 downto 12);
signal V_A_CTRL_PC31DOWNTO12_shadow_intermed_5 : STD_LOGIC_VECTOR(31 downto 12);
signal R_D_PC31DOWNTO2_intermed_2 : STD_LOGIC_VECTOR(31 downto 2);
signal RIN_E_CTRL_PC3DOWNTO2_intermed_5 : STD_LOGIC_VECTOR(3 downto 2);
signal RIN_E_CTRL_PC31DOWNTO12_intermed_1 : STD_LOGIC_VECTOR(31 downto 12);
signal R_A_CTRL_PC_intermed_4 : STD_LOGIC_VECTOR(31 downto 2);
signal R_A_CTRL_ANNUL_intermed_4 : STD_ULOGIC;
signal V_X_RESULT_shadow_intermed_1 : STD_LOGIC_VECTOR(31 downto 0);
signal R_E_CTRL_PC31DOWNTO2_intermed_1 : STD_LOGIC_VECTOR(31 downto 2);
signal V_D_INST024_shadow_intermed_5 : STD_LOGIC;
signal R_A_CTRL_PC31DOWNTO4_intermed_3 : STD_LOGIC_VECTOR(31 downto 4);
signal V_D_CNT_shadow_intermed_5 : STD_LOGIC_VECTOR(1 downto 0);
signal R_A_CTRL_TT_intermed_2 : STD_LOGIC_VECTOR(5 downto 0);
signal RIN_A_CTRL_PC31DOWNTO12_intermed_5 : STD_LOGIC_VECTOR(31 downto 12);
signal V_A_CTRL_TT3DOWNTO0_shadow_intermed_5 : STD_LOGIC_VECTOR(3 downto 0);
signal R_D_INST024_intermed_4 : STD_LOGIC;
signal RIN_W_S_S_intermed_1 : STD_ULOGIC;
signal V_M_CTRL_CNT_shadow_intermed_1 : STD_LOGIC_VECTOR(1 downto 0);
signal V_A_CTRL_PC31DOWNTO12_shadow_intermed_7 : STD_LOGIC_VECTOR(31 downto 12);
signal V_A_CTRL_WICC_shadow_intermed_2 : STD_ULOGIC;
signal R_X_DATA03_intermed_1 : STD_LOGIC;
signal RIN_M_DCI_intermed_1 : DC_IN_TYPE;
signal R_A_CTRL_CNT_intermed_2 : STD_LOGIC_VECTOR(1 downto 0);
signal RIN_W_S_EF_intermed_1 : STD_ULOGIC;
signal V_E_CTRL_RD6DOWNTO0_shadow_intermed_2 : STD_LOGIC_VECTOR(6 downto 0);
signal RIN_A_CTRL_LD_intermed_3 : STD_ULOGIC;
signal V_M_CTRL_RD6DOWNTO0_shadow_intermed_1 : STD_LOGIC_VECTOR(6 downto 0);
signal R_E_CTRL_INST_intermed_2 : STD_LOGIC_VECTOR(31 downto 0);
signal RIN_M_CTRL_RD6DOWNTO0_intermed_1 : STD_LOGIC_VECTOR(6 downto 0);
signal RIN_W_S_Y7DOWNTO0_intermed_1 : STD_LOGIC_VECTOR(7 downto 0);
signal V_F_PC3DOWNTO2_shadow_intermed_1 : STD_LOGIC_VECTOR(3 downto 2);
signal EX_ADD_RES32DOWNTO330DOWNTO11_shadow_intermed_2 : STD_LOGIC_VECTOR(30 downto 11);
signal V_X_ANNUL_ALL_shadow_intermed_3 : STD_ULOGIC;
signal V_F_PC31DOWNTO12_shadow_intermed_2 : STD_LOGIC_VECTOR(31 downto 12);
signal RIN_E_CTRL_INST24_intermed_1 : STD_LOGIC;
signal R_A_CTRL_PV_intermed_1 : STD_ULOGIC;
signal RIN_A_CTRL_RETT_intermed_3 : STD_ULOGIC;
signal R_E_CTRL_TT_intermed_2 : STD_LOGIC_VECTOR(5 downto 0);
signal EX_ADD_RES32DOWNTO34DOWNTO3_shadow_intermed_1 : STD_LOGIC_VECTOR(4 downto 3);
signal RIN_D_PC31DOWNTO12_intermed_7 : STD_LOGIC_VECTOR(31 downto 12);
signal V_E_CTRL_INST_shadow_intermed_2 : STD_LOGIC_VECTOR(31 downto 0);
signal DCO_MEXC_intermed_1 : STD_ULOGIC;
signal V_M_CTRL_PC31DOWNTO12_shadow_intermed_1 : STD_LOGIC_VECTOR(31 downto 12);
signal RIN_E_CWP_intermed_1 : STD_LOGIC_VECTOR(2 downto 0);
signal V_A_CTRL_CNT_shadow_intermed_4 : STD_LOGIC_VECTOR(1 downto 0);
signal V_A_CTRL_ANNUL_shadow_intermed_2 : STD_ULOGIC;
signal R_A_CTRL_PC31DOWNTO12_intermed_3 : STD_LOGIC_VECTOR(31 downto 12);
signal R_A_CTRL_PC31DOWNTO2_intermed_4 : STD_LOGIC_VECTOR(31 downto 2);
signal R_X_RESULT6DOWNTO0_intermed_2 : STD_LOGIC_VECTOR(6 downto 0);
signal RIN_A_SU_intermed_1 : STD_ULOGIC;
signal R_E_CTRL_intermed_1 : PIPELINE_CTRL_TYPE;
signal V_E_OP231_shadow_intermed_1 : STD_LOGIC;
signal RIN_A_CTRL_WREG_intermed_3 : STD_ULOGIC;
signal V_A_CTRL_INST_shadow_intermed_4 : STD_LOGIC_VECTOR(31 downto 0);
signal V_E_CTRL_PC31DOWNTO12_shadow_intermed_6 : STD_LOGIC_VECTOR(31 downto 12);
signal V_M_CTRL_PC3DOWNTO2_shadow_intermed_1 : STD_LOGIC_VECTOR(3 downto 2);
signal R_E_CTRL_TT3DOWNTO0_intermed_3 : STD_LOGIC_VECTOR(3 downto 0);
signal RPIN_ERROR_intermed_2 : STD_ULOGIC;
signal V_D_CWP_shadow_intermed_1 : STD_LOGIC_VECTOR(2 downto 0);
signal V_E_CTRL_PC31DOWNTO2_shadow_intermed_4 : STD_LOGIC_VECTOR(31 downto 2);
signal RIN_A_CTRL_PV_intermed_3 : STD_ULOGIC;
signal RIN_M_CTRL_PC31DOWNTO4_intermed_1 : STD_LOGIC_VECTOR(31 downto 4);
signal RIN_E_CTRL_INST24_intermed_2 : STD_LOGIC;
signal RIN_X_DCI_SIZE_intermed_1 : STD_LOGIC_VECTOR(1 downto 0);
signal RIN_F_PC31DOWNTO12_intermed_1 : STD_LOGIC_VECTOR(31 downto 12);
signal R_A_CTRL_TT3DOWNTO0_intermed_3 : STD_LOGIC_VECTOR(3 downto 0);
signal V_M_Y31_shadow_intermed_1 : STD_LOGIC;
signal R_E_CTRL_PC31DOWNTO2_intermed_5 : STD_LOGIC_VECTOR(31 downto 2);
signal R_A_CTRL_PC31DOWNTO2_intermed_1 : STD_LOGIC_VECTOR(31 downto 2);
signal V_M_CTRL_PC31DOWNTO2_shadow_intermed_1 : STD_LOGIC_VECTOR(31 downto 2);
signal R_A_CTRL_INST19_intermed_1 : STD_LOGIC;
signal RIN_E_CTRL_TT_intermed_1 : STD_LOGIC_VECTOR(5 downto 0);
signal RIN_E_CTRL_PC31DOWNTO2_intermed_2 : STD_LOGIC_VECTOR(31 downto 2);
signal R_X_CTRL_PC3DOWNTO2_intermed_2 : STD_LOGIC_VECTOR(3 downto 2);
signal RIN_X_ANNUL_ALL_intermed_4 : STD_ULOGIC;
signal V_A_CTRL_INST_shadow_intermed_1 : STD_LOGIC_VECTOR(31 downto 0);
signal V_X_CTRL_PC31DOWNTO12_shadow_intermed_2 : STD_LOGIC_VECTOR(31 downto 12);
signal IRIN_ADDR31DOWNTO4_intermed_2 : STD_LOGIC_VECTOR(31 downto 4);
signal RIN_E_CTRL_PC3DOWNTO2_intermed_4 : STD_LOGIC_VECTOR(3 downto 2);
signal RIN_A_CTRL_PC31DOWNTO4_intermed_1 : STD_LOGIC_VECTOR(31 downto 4);
signal RIN_E_CTRL_ANNUL_intermed_2 : STD_ULOGIC;
signal V_E_CTRL_INST19_shadow_intermed_1 : STD_LOGIC;
signal RIN_A_CTRL_PC_intermed_3 : STD_LOGIC_VECTOR(31 downto 2);
signal V_X_DATA03_shadow_intermed_1 : STD_LOGIC;
signal V_E_OP1_shadow_intermed_1 : STD_LOGIC_VECTOR(31 downto 0);
signal RIN_M_CTRL_CNT_intermed_2 : STD_LOGIC_VECTOR(1 downto 0);
signal RIN_A_CTRL_PC31DOWNTO2_intermed_6 : STD_LOGIC_VECTOR(31 downto 2);
signal RIN_D_MEXC_intermed_2 : STD_ULOGIC;
signal R_D_PC31DOWNTO4_intermed_2 : STD_LOGIC_VECTOR(31 downto 4);
signal RIN_X_CTRL_INST_intermed_1 : STD_LOGIC_VECTOR(31 downto 0);
signal V_A_SU_shadow_intermed_2 : STD_ULOGIC;
signal R_W_S_TT3DOWNTO0_intermed_1 : STD_LOGIC_VECTOR(3 downto 0);
signal V_M_Y31_shadow_intermed_2 : STD_LOGIC;
signal R_A_CTRL_ANNUL_intermed_3 : STD_ULOGIC;
signal V_D_INST019_shadow_intermed_1 : STD_LOGIC;
signal R_A_CTRL_TRAP_intermed_1 : STD_ULOGIC;
signal RIN_M_CTRL_WICC_intermed_1 : STD_ULOGIC;
signal R_D_PC31DOWNTO2_intermed_7 : STD_LOGIC_VECTOR(31 downto 2);
signal RIN_X_ANNUL_ALL_intermed_1 : STD_ULOGIC;
signal V_M_CTRL_WREG_shadow_intermed_1 : STD_ULOGIC;
signal V_A_CTRL_RD7DOWNTO0_shadow_intermed_4 : STD_LOGIC_VECTOR(7 downto 0);
signal RIN_A_RFE1_intermed_1 : STD_ULOGIC;
signal V_A_CTRL_PC31DOWNTO2_shadow_intermed_1 : STD_LOGIC_VECTOR(31 downto 2);
signal V_D_PC31DOWNTO4_shadow_intermed_4 : STD_LOGIC_VECTOR(31 downto 4);
signal R_A_CTRL_PC31DOWNTO12_intermed_2 : STD_LOGIC_VECTOR(31 downto 12);
signal V_M_MAC_shadow_intermed_1 : STD_ULOGIC;
signal V_D_PC31DOWNTO2_shadow_intermed_2 : STD_LOGIC_VECTOR(31 downto 2);
signal RIN_A_CTRL_TRAP_intermed_2 : STD_ULOGIC;
signal R_E_CTRL_RD7DOWNTO0_intermed_1 : STD_LOGIC_VECTOR(7 downto 0);
signal R_E_CTRL_PC_intermed_3 : STD_LOGIC_VECTOR(31 downto 2);
signal R_X_DATA00_intermed_1 : STD_LOGIC;
signal RIN_E_MUL_intermed_1 : STD_ULOGIC;
signal V_X_ANNUL_ALL_shadow_intermed_1 : STD_ULOGIC;
signal R_D_PC_intermed_5 : STD_LOGIC_VECTOR(31 downto 2);
signal R_X_DATA03_intermed_2 : STD_LOGIC;
signal RIN_F_PC31DOWNTO4_intermed_1 : STD_LOGIC_VECTOR(31 downto 4);
signal RIN_W_S_CWP_intermed_1 : STD_LOGIC_VECTOR(2 downto 0);
signal V_W_S_PS_shadow_intermed_1 : STD_ULOGIC;
signal R_A_CTRL_intermed_1 : PIPELINE_CTRL_TYPE;
signal R_A_CTRL_TT_intermed_3 : STD_LOGIC_VECTOR(5 downto 0);
signal RIN_A_CTRL_PC31DOWNTO4_intermed_6 : STD_LOGIC_VECTOR(31 downto 4);
signal V_D_PC31DOWNTO2_shadow_intermed_7 : STD_LOGIC_VECTOR(31 downto 2);
signal RIN_M_CTRL_PC31DOWNTO2_intermed_1 : STD_LOGIC_VECTOR(31 downto 2);
signal RIN_X_CTRL_PC3DOWNTO2_intermed_1 : STD_LOGIC_VECTOR(3 downto 2);
signal R_D_PC3DOWNTO2_intermed_1 : STD_LOGIC_VECTOR(3 downto 2);
signal V_E_MAC_shadow_intermed_1 : STD_ULOGIC;
signal V_D_INST024_shadow_intermed_4 : STD_LOGIC;
signal RIN_X_ICC_intermed_1 : STD_LOGIC_VECTOR(3 downto 0);
signal RIN_M_MAC_intermed_1 : STD_ULOGIC;
signal RIN_W_S_TT3DOWNTO0_intermed_1 : STD_LOGIC_VECTOR(3 downto 0);
signal R_D_PC31DOWNTO4_intermed_4 : STD_LOGIC_VECTOR(31 downto 4);
signal V_A_CTRL_PC3DOWNTO2_shadow_intermed_6 : STD_LOGIC_VECTOR(3 downto 2);
signal R_X_ANNUL_ALL_intermed_1 : STD_ULOGIC;
signal EX_JUMP_ADDRESS_shadow_intermed_1 : STD_LOGIC_VECTOR(31 downto 2);
signal RIN_X_CTRL_PV_intermed_1 : STD_ULOGIC;
signal EX_ADD_RES32DOWNTO332DOWNTO13_shadow_intermed_2 : STD_LOGIC_VECTOR(32 downto 13);
signal RIN_A_CTRL_INST_intermed_1 : STD_LOGIC_VECTOR(31 downto 0);
signal R_A_CTRL_RD6DOWNTO0_intermed_3 : STD_LOGIC_VECTOR(6 downto 0);
signal IR_ADDR31DOWNTO12_intermed_1 : STD_LOGIC_VECTOR(31 downto 12);
signal RIN_D_PC3DOWNTO2_intermed_6 : STD_LOGIC_VECTOR(3 downto 2);
signal RIN_M_Y31_intermed_2 : STD_LOGIC;
signal RIN_X_DATA04DOWNTO0_intermed_2 : STD_LOGIC_VECTOR(4 downto 0);
signal V_D_PC31DOWNTO2_shadow_intermed_3 : STD_LOGIC_VECTOR(31 downto 2);
signal R_M_DCI_SIZE_intermed_1 : STD_LOGIC_VECTOR(1 downto 0);
signal V_E_CTRL_PC3DOWNTO2_shadow_intermed_4 : STD_LOGIC_VECTOR(3 downto 2);
signal V_E_OP2_shadow_intermed_1 : STD_LOGIC_VECTOR(31 downto 0);
signal V_E_CTRL_TT3DOWNTO0_shadow_intermed_5 : STD_LOGIC_VECTOR(3 downto 0);
signal RIN_D_INST019_intermed_4 : STD_LOGIC;
signal V_A_CTRL_INST20_shadow_intermed_2 : STD_LOGIC;
signal RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_1 : STD_LOGIC_VECTOR(3 downto 0);
signal V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_4 : STD_LOGIC_VECTOR(3 downto 0);
signal R_X_RESULT6DOWNTO03DOWNTO0_intermed_2 : STD_LOGIC_VECTOR(3 downto 0);
signal RIN_M_CTRL_TRAP_intermed_2 : STD_ULOGIC;
signal V_A_CTRL_INST_shadow_intermed_3 : STD_LOGIC_VECTOR(31 downto 0);
signal trapCountIn : STD_LOGIC_VECTOR(31 downto 0);
signal dfp_bscan_cntrl1 : STD_LOGIC_VECTOR(35 downto 0);
signal dfp_bscan_cntrl2 : STD_LOGIC_VECTOR(35 downto 0);
signal dfp_bscan_value : STD_LOGIC_VECTOR(131 downto 0);
signal dfp_bscan_count : STD_LOGIC_VECTOR(31 downto 0);
signal dfp_delay_start : integer range 0 to 15;
component scope
PORT (
CONTROL : INOUT STD_LOGIC_VECTOR(35 DOWNTO 0);
ASYNC_IN : IN STD_LOGIC_VECTOR(131 DOWNTO 0)
);
end component;
component scope2
PORT (
CONTROL : INOUT STD_LOGIC_VECTOR(35 DOWNTO 0);
ASYNC_IN : IN STD_LOGIC_VECTOR(31 DOWNTO 0)
);
end component;
component iconScope
PORT (
CONTROL0 : INOUT STD_LOGIC_VECTOR(35 DOWNTO 0);
CONTROL1 : INOUT STD_LOGIC_VECTOR(35 DOWNTO 0)
);
end component;
attribute syn_black_box : boolean;
attribute syn_noprune : integer;
attribute syn_black_box of iconScope: component is true;
attribute syn_black_box of scope: component is true;
attribute syn_black_box of scope2: component is true;
attribute syn_noprune of iconScope: component is 1;
attribute syn_noprune of scope: component is 1;
attribute syn_noprune of scope2: component is 1;
begin
comb : process(ico, dco, rfo, r, wpr, ir, dsur, rstn, holdn, irqi, dbgi, fpo, cpo, tbo,
mulo, divo, dummy, rp, handlerTrap)
variable v : registers;
variable vp : pwd_register_type;
variable vwpr : watchpoint_registers;
variable vdsu : dsu_registers;
variable npc : std_logic_vector(31 downto PCLOW);
variable de_raddr1, de_raddr2 : std_logic_vector(9 downto 0);
variable de_rs2, de_rd : std_logic_vector(4 downto 0);
variable de_hold_pc, de_branch, de_fpop, de_ldlock : std_ulogic;
variable de_cwp, de_cwp2 : cwptype;
variable de_inull : std_ulogic;
variable de_ren1, de_ren2 : std_ulogic;
variable de_wcwp : std_ulogic;
variable de_inst : word;
variable de_branch_address : pctype;
variable de_icc : std_logic_vector(3 downto 0);
variable de_fbranch, de_cbranch : std_ulogic;
variable de_rs1mod : std_ulogic;
variable ra_op1, ra_op2 : word;
variable ra_div : std_ulogic;
variable ex_jump, ex_link_pc : std_ulogic;
variable ex_jump_address : pctype;
variable ex_add_res : std_logic_vector(32 downto 0);
variable ex_shift_res, ex_logic_res, ex_misc_res : word;
variable ex_edata, ex_edata2 : word;
variable ex_dci : dc_in_type;
variable ex_force_a2, ex_load, ex_ymsb : std_ulogic;
variable ex_op1, ex_op2, ex_result, ex_result2, mul_op2 : word;
variable ex_shcnt : std_logic_vector(4 downto 0);
variable ex_dsuen : std_ulogic;
variable ex_ldbp2 : std_ulogic;
variable ex_sari : std_ulogic;
variable me_inull, me_nullify, me_nullify2 : std_ulogic;
variable me_iflush : std_ulogic;
variable me_newtt : std_logic_vector(5 downto 0);
variable me_asr18 : word;
variable me_signed : std_ulogic;
variable me_size, me_laddr : std_logic_vector(1 downto 0);
variable me_icc : std_logic_vector(3 downto 0);
variable xc_result : word;
variable xc_df_result : word;
variable xc_waddr : std_logic_vector(9 downto 0);
variable xc_exception, xc_wreg : std_ulogic;
variable xc_trap_address : pctype;
variable xc_vectt : std_logic_vector(7 downto 0);
variable xc_trap : std_ulogic;
variable xc_fpexack : std_ulogic;
variable xc_rstn, xc_halt : std_ulogic;
-- variable wr_rf1_data, wr_rf2_data : word;
variable diagdata : word;
variable tbufi : tracebuf_in_type;
variable dbgm : std_ulogic;
variable fpcdbgwr : std_ulogic;
variable vfpi : fpc_in_type;
variable dsign : std_ulogic;
variable pwrd, sidle : std_ulogic;
variable vir : irestart_register;
variable icnt : std_ulogic;
variable tbufcntx : std_logic_vector(TBUFBITS-1 downto 0);
begin
v := r; vwpr := wpr; vdsu := dsur; vp := rp;
xc_fpexack := '0'; sidle := '0';
fpcdbgwr := '0'; vir := ir; xc_rstn := rstn;
-----------------------------------------------------------------------
-- WRITE STAGE
-----------------------------------------------------------------------
-- wr_rf1_data := rfo.data1; wr_rf2_data := rfo.data2;
-- if irfwt = 0 then
-- if r.w.wreg = '1' then
-- if r.a.rfa1 = r.w.wa then wr_rf1_data := r.w.result; end if;
-- if r.a.rfa2 = r.w.wa then wr_rf2_data := r.w.result; end if;
-- end if;
-- end if;
-----------------------------------------------------------------------
-- EXCEPTION STAGE
-----------------------------------------------------------------------
xc_exception := '0'; xc_halt := '0'; icnt := '0';
xc_waddr := (others => '0');
xc_waddr(RFBITS-1 downto 0) := r.x.ctrl.rd(RFBITS-1 downto 0);
xc_trap := r.x.mexc or r.x.ctrl.trap or handlerTrap;
v.x.nerror := rp.error;
if(handlerTrap = '1')then
xc_vectt := "00" & TT_WATCH;
elsif r.x.mexc = '1' then
xc_vectt := "00" & TT_DAEX;
elsif r.x.ctrl.tt = TT_TICC then
xc_vectt := '1' & r.x.result(6 downto 0);
else xc_vectt := "00" & r.x.ctrl.tt; end if;
if r.w.s.svt = '0' then
xc_trap_address(31 downto 4) := r.w.s.tba & xc_vectt;
else
xc_trap_address(31 downto 4) := r.w.s.tba & "00000000";
end if;
xc_trap_address(3 downto PCLOW) := (others => '0');
xc_wreg := '0'; v.x.annul_all := '0';
if (r.x.ctrl.ld = '1') then
if (lddel = 2) then
xc_result := ld_align(r.x.data, r.x.set, r.x.dci.size, r.x.laddr, r.x.dci.signed);
else xc_result := r.x.data(0); end if;
elsif MACEN and MACPIPE and (r.x.mac = '1') then
xc_result := mulo.result(31 downto 0);
else xc_result := r.x.result; end if;
xc_df_result := xc_result;
if DBGUNIT then
dbgm := dbgexc(r, dbgi, xc_trap, xc_vectt);
if (dbgi.dsuen and dbgi.dbreak) = '0'then v.x.debug := '0'; end if;
else dbgm := '0'; v.x.debug := '0'; end if;
if PWRD2 then pwrd := powerdwn(r, xc_trap, rp); else pwrd := '0'; end if;
case r.x.rstate is
when run =>
if (not r.x.ctrl.annul and r.x.ctrl.pv and not r.x.debug) = '1' then
icnt := holdn;
end if;
if dbgm = '1' then
v.x.annul_all := '1'; vir.addr := r.x.ctrl.pc;
v.x.rstate := dsu1; v.x.debug := '1';
v.x.npc := npc_find(r);
vdsu.tt := xc_vectt; vdsu.err := dbgerr(r, dbgi, xc_vectt);
elsif (pwrd = '1') and (ir.pwd = '0') then
v.x.annul_all := '1'; vir.addr := r.x.ctrl.pc;
v.x.rstate := dsu1; v.x.npc := npc_find(r); vp.pwd := '1';
elsif (r.x.ctrl.annul or xc_trap) = '0' then
xc_wreg := r.x.ctrl.wreg;
sp_write (r, wpr, v.w.s, vwpr);
vir.pwd := '0';
elsif ((not r.x.ctrl.annul) and xc_trap) = '1' then
xc_exception := '1'; xc_result := r.x.ctrl.pc(31 downto 2) & "00";
xc_wreg := '1'; v.w.s.tt := xc_vectt; v.w.s.ps := r.w.s.s;
v.w.s.s := '1'; v.x.annul_all := '1'; v.x.rstate := trap;
xc_waddr := (others => '0');
xc_waddr(NWINLOG2 + 3 downto 0) := r.w.s.cwp & "0001";
v.x.npc := npc_find(r);
fpexack(r, xc_fpexack);
if r.w.s.et = '0' then
-- v.x.rstate := dsu1; xc_wreg := '0'; vp.error := '1';
xc_wreg := '0';
end if;
end if;
when trap =>
xc_result := npc_gen(r); xc_wreg := '1';
xc_waddr := (others => '0');
xc_waddr(NWINLOG2 + 3 downto 0) := r.w.s.cwp & "0010";
if (r.w.s.et = '1') then
v.w.s.et := '0'; v.x.rstate := run;
if (not CWPOPT) and (r.w.s.cwp = CWPMIN) then v.w.s.cwp := CWPMAX;
else v.w.s.cwp := r.w.s.cwp - 1 ; end if;
else
v.x.rstate := dsu1; xc_wreg := '0'; vp.error := '1';
end if;
when dsu1 =>
xc_exception := '1'; v.x.annul_all := '1';
xc_trap_address(31 downto PCLOW) := r.f.pc;
if DBGUNIT or PWRD2 or (smp /= 0) then
xc_trap_address(31 downto PCLOW) := ir.addr;
vir.addr := npc_gen(r)(31 downto PCLOW);
v.x.rstate := dsu2;
end if;
if DBGUNIT then v.x.debug := r.x.debug; end if;
when dsu2 =>
xc_exception := '1'; v.x.annul_all := '1';
xc_trap_address(31 downto PCLOW) := r.f.pc;
if DBGUNIT or PWRD2 or (smp /= 0) then
sidle := (rp.pwd or rp.error) and ico.idle and dco.idle and not r.x.debug;
if DBGUNIT then
if dbgi.reset = '1' then
if smp /=0 then vp.pwd := not irqi.run; else vp.pwd := '0'; end if;
vp.error := '0';
end if;
if (dbgi.dsuen and dbgi.dbreak) = '1'then v.x.debug := '1'; end if;
diagwr(r, dsur, ir, dbgi, wpr, v.w.s, vwpr, vdsu.asi, xc_trap_address,
vir.addr, vdsu.tbufcnt, xc_wreg, xc_waddr, xc_result, fpcdbgwr);
xc_halt := dbgi.halt;
end if;
if r.x.ipend = '1' then vp.pwd := '0'; end if;
if (rp.error or rp.pwd or r.x.debug or xc_halt) = '0' then
v.x.rstate := run; v.x.annul_all := '0'; vp.error := '0';
xc_trap_address(31 downto PCLOW) := ir.addr; v.x.debug := '0';
vir.pwd := '1';
end if;
if (smp /= 0) and (irqi.rst = '1') then
vp.pwd := '0'; vp.error := '0';
end if;
end if;
when others =>
end case;
irq_intack(r, holdn, v.x.intack);
itrace(r, dsur, vdsu, xc_result, xc_exception, dbgi, rp.error, xc_trap, tbufcntx, tbufi);
vdsu.tbufcnt := tbufcntx;
v.w.except := xc_exception; v.w.result := xc_result;
if (r.x.rstate = dsu2) then v.w.except := '0'; end if;
v.w.wa := xc_waddr(RFBITS-1 downto 0); v.w.wreg := xc_wreg and holdn;
rfi.wdata <= xc_result; rfi.waddr <= xc_waddr;
rfi.wren <= (xc_wreg and holdn) and not dco.scanen;
irqo.intack <= r.x.intack and holdn;
irqo.irl <= r.w.s.tt(3 downto 0);
irqo.pwd <= rp.pwd;
irqo.fpen <= r.w.s.ef;
dbgo.halt <= xc_halt;
dbgo.pwd <= rp.pwd;
dbgo.idle <= sidle;
dbgo.icnt <= icnt;
dci.intack <= r.x.intack and holdn;
if (xc_rstn = '0') then
v.w.except := '0'; v.w.s.et := '0'; v.w.s.svt := '0'; v.w.s.dwt := '0';
v.w.s.ef := '0'; -- needed for AX
if need_extra_sync_reset(fabtech) /= 0 then
v.w.s.cwp := (others => '0');
v.w.s.icc := (others => '0');
end if;
v.x.annul_all := '1'; v.x.rstate := run; vir.pwd := '0';
vp.pwd := '0'; v.x.debug := '0'; --vp.error := '0';
v.x.nerror := '0';
if svt = 1 then v.w.s.tt := (others => '0'); end if;
if DBGUNIT then
if (dbgi.dsuen and dbgi.dbreak) = '1' then
v.x.rstate := dsu1; v.x.debug := '1';
end if;
end if;
if (smp /= 0) and (irqi.run = '0') and (rstn = '0') then
v.x.rstate := dsu1; vp.pwd := '1';
end if;
end if;
if not FPEN then v.w.s.ef := '0'; end if;
-----------------------------------------------------------------------
-- MEMORY STAGE
-----------------------------------------------------------------------
v.x.ctrl := r.m.ctrl; v.x.dci := r.m.dci;
v.x.ctrl.rett := r.m.ctrl.rett and not r.m.ctrl.annul;
v.x.mac := r.m.mac; v.x.laddr := r.m.result(1 downto 0);
v.x.ctrl.annul := r.m.ctrl.annul or v.x.annul_all;
mul_res(r, v.w.s.asr18, v.x.result, v.x.y, me_asr18, me_icc);
mem_trap(r, wpr, v.x.ctrl.annul, holdn, v.x.ctrl.trap, me_iflush,
me_nullify, v.m.werr, v.x.ctrl.tt);
me_newtt := v.x.ctrl.tt;
irq_trap(r, ir, irqi.irl, v.x.ctrl.annul, v.x.ctrl.pv, v.x.ctrl.trap, me_newtt, me_nullify,
v.m.irqen, v.m.irqen2, me_nullify2, v.x.ctrl.trap,
v.x.ipend, v.x.ctrl.tt);
if (r.m.ctrl.ld or not dco.mds) = '1' then
for i in 0 to dsets-1 loop v.x.data(i) := dco.data(i); end loop;
v.x.set := dco.set(DSETMSB downto 0);
if dco.mds = '0' then
me_size := r.x.dci.size; me_laddr := r.x.laddr; me_signed := r.x.dci.signed;
else
me_size := v.x.dci.size; me_laddr := v.x.laddr; me_signed := v.x.dci.signed;
end if;
if lddel /= 2 then
v.x.data(0) := ld_align(v.x.data, v.x.set, me_size, me_laddr, me_signed);
end if;
end if;
v.x.mexc := dco.mexc;
v.x.icc := me_icc;
v.x.ctrl.wicc := r.m.ctrl.wicc and not v.x.annul_all;
if MACEN and ((v.x.ctrl.annul or v.x.ctrl.trap) = '0') then
v.w.s.asr18 := me_asr18;
end if;
if (r.x.rstate = dsu2) then
me_nullify2 := '0'; v.x.set := dco.set(DSETMSB downto 0);
end if;
dci.maddress <= r.m.result;
dci.enaddr <= r.m.dci.enaddr;
dci.asi <= r.m.dci.asi;
dci.size <= r.m.dci.size;
dci.nullify <= me_nullify2;
dci.lock <= r.m.dci.lock and not r.m.ctrl.annul;
dci.read <= r.m.dci.read;
dci.write <= r.m.dci.write;
dci.flush <= me_iflush;
dci.dsuen <= r.m.dci.dsuen;
dci.msu <= r.m.su;
dci.esu <= r.e.su;
dbgo.ipend <= v.x.ipend;
-----------------------------------------------------------------------
-- EXECUTE STAGE
-----------------------------------------------------------------------
v.m.ctrl := r.e.ctrl; ex_op1 := r.e.op1; ex_op2 := r.e.op2;
v.m.ctrl.rett := r.e.ctrl.rett and not r.e.ctrl.annul;
v.m.ctrl.wreg := r.e.ctrl.wreg and not v.x.annul_all;
ex_ymsb := r.e.ymsb; mul_op2 := ex_op2; ex_shcnt := r.e.shcnt;
v.e.cwp := r.a.cwp; ex_sari := r.e.sari;
v.m.su := r.e.su;
if MULTYPE = 3 then v.m.mul := r.e.mul; else v.m.mul := '0'; end if;
if lddel = 1 then
if r.e.ldbp1 = '1' then
ex_op1 := r.x.data(0);
ex_sari := r.x.data(0)(31) and r.e.ctrl.inst(19) and r.e.ctrl.inst(20);
end if;
if r.e.ldbp2 = '1' then
ex_op2 := r.x.data(0); ex_ymsb := r.x.data(0)(0);
mul_op2 := ex_op2; ex_shcnt := r.x.data(0)(4 downto 0);
if r.e.invop2 = '1' then
ex_op2 := not ex_op2; ex_shcnt := not ex_shcnt;
end if;
end if;
end if;
ex_add_res := (ex_op1 & '1') + (ex_op2 & r.e.alucin);
if ex_add_res(2 downto 1) = "00" then v.m.nalign := '0';
else v.m.nalign := '1'; end if;
dcache_gen(r, v, ex_dci, ex_link_pc, ex_jump, ex_force_a2, ex_load );
ex_jump_address := ex_add_res(32 downto PCLOW+1);
logic_op(r, ex_op1, ex_op2, v.x.y, ex_ymsb, ex_logic_res, v.m.y);
ex_shift_res := shift(r, ex_op1, ex_op2, ex_shcnt, ex_sari);
misc_op(r, wpr, ex_op1, ex_op2, xc_df_result, v.x.y, ex_misc_res, ex_edata);
ex_add_res(3):= ex_add_res(3) or ex_force_a2;
alu_select(r, ex_add_res, ex_op1, ex_op2, ex_shift_res, ex_logic_res,
ex_misc_res, ex_result, me_icc, v.m.icc, v.m.divz);
dbg_cache(holdn, dbgi, r, dsur, ex_result, ex_dci, ex_result2, v.m.dci);
fpstdata(r, ex_edata, ex_result2, fpo.data, ex_edata2, v.m.result);
cwp_ex(r, v.m.wcwp);
v.m.ctrl.annul := v.m.ctrl.annul or v.x.annul_all;
v.m.ctrl.wicc := r.e.ctrl.wicc and not v.x.annul_all;
v.m.mac := r.e.mac;
if (DBGUNIT and (r.x.rstate = dsu2)) then v.m.ctrl.ld := '1'; end if;
dci.eenaddr <= v.m.dci.enaddr;
dci.eaddress <= ex_add_res(32 downto 1);
dci.edata <= ex_edata2;
-----------------------------------------------------------------------
-- REGFILE STAGE
-----------------------------------------------------------------------
v.e.ctrl := r.a.ctrl; v.e.jmpl := r.a.jmpl;
v.e.ctrl.annul := r.a.ctrl.annul or v.x.annul_all;
v.e.ctrl.rett := r.a.ctrl.rett and not r.a.ctrl.annul;
v.e.ctrl.wreg := r.a.ctrl.wreg and not v.x.annul_all;
v.e.su := r.a.su; v.e.et := r.a.et;
v.e.ctrl.wicc := r.a.ctrl.wicc and not v.x.annul_all;
exception_detect(r, wpr, dbgi, r.a.ctrl.trap, r.a.ctrl.tt,
v.e.ctrl.trap, v.e.ctrl.tt, handlerTrap);
op_mux(r, rfo.data1, v.m.result, v.x.result, xc_df_result, zero32,
r.a.rsel1, v.e.ldbp1, ra_op1);
op_mux(r, rfo.data2, v.m.result, v.x.result, xc_df_result, r.a.imm,
r.a.rsel2, ex_ldbp2, ra_op2);
alu_op(r, ra_op1, ra_op2, v.m.icc, v.m.y(0), ex_ldbp2, v.e.op1, v.e.op2,
v.e.aluop, v.e.alusel, v.e.aluadd, v.e.shcnt, v.e.sari, v.e.shleft,
v.e.ymsb, v.e.mul, ra_div, v.e.mulstep, v.e.mac, v.e.ldbp2, v.e.invop2);
cin_gen(r, v.m.icc(0), v.e.alucin);
-----------------------------------------------------------------------
-- DECODE STAGE
-----------------------------------------------------------------------
if ISETS > 1 then de_inst := r.d.inst(conv_integer(r.d.set));
else de_inst := r.d.inst(0); end if;
de_icc := r.m.icc; v.a.cwp := r.d.cwp;
su_et_select(r, v.w.s.ps, v.w.s.s, v.w.s.et, v.a.su, v.a.et);
wicc_y_gen(de_inst, v.a.ctrl.wicc, v.a.ctrl.wy);
cwp_ctrl(r, v.w.s.wim, de_inst, de_cwp, v.a.wovf, v.a.wunf, de_wcwp);
rs1_gen(r, de_inst, v.a.rs1, de_rs1mod);
de_rs2 := de_inst(4 downto 0);
de_raddr1 := (others => '0'); de_raddr2 := (others => '0');
if RS1OPT then
if de_rs1mod = '1' then
regaddr(r.d.cwp, de_inst(29 downto 26) & v.a.rs1(0), de_raddr1(RFBITS-1 downto 0));
else
regaddr(r.d.cwp, de_inst(18 downto 15) & v.a.rs1(0), de_raddr1(RFBITS-1 downto 0));
end if;
else
regaddr(r.d.cwp, v.a.rs1, de_raddr1(RFBITS-1 downto 0));
end if;
regaddr(r.d.cwp, de_rs2, de_raddr2(RFBITS-1 downto 0));
v.a.rfa1 := de_raddr1(RFBITS-1 downto 0);
v.a.rfa2 := de_raddr2(RFBITS-1 downto 0);
rd_gen(r, de_inst, v.a.ctrl.wreg, v.a.ctrl.ld, de_rd);
regaddr(de_cwp, de_rd, v.a.ctrl.rd);
fpbranch(de_inst, fpo.cc, de_fbranch);
fpbranch(de_inst, cpo.cc, de_cbranch);
v.a.imm := imm_data(r, de_inst);
lock_gen(r, de_rs2, de_rd, v.a.rfa1, v.a.rfa2, v.a.ctrl.rd, de_inst,
fpo.ldlock, v.e.mul, ra_div, v.a.ldcheck1, v.a.ldcheck2, de_ldlock,
v.a.ldchkra, v.a.ldchkex);
ic_ctrl(r, de_inst, v.x.annul_all, de_ldlock, branch_true(de_icc, de_inst),
de_fbranch, de_cbranch, fpo.ccv, cpo.ccv, v.d.cnt, v.d.pc, de_branch,
v.a.ctrl.annul, v.d.annul, v.a.jmpl, de_inull, v.d.pv, v.a.ctrl.pv,
de_hold_pc, v.a.ticc, v.a.ctrl.rett, v.a.mulstart, v.a.divstart);
cwp_gen(r, v, v.a.ctrl.annul, de_wcwp, de_cwp, v.d.cwp);
v.d.inull := ra_inull_gen(r, v);
op_find(r, v.a.ldchkra, v.a.ldchkex, v.a.rs1, v.a.rfa1,
false, v.a.rfe1, v.a.rsel1, v.a.ldcheck1);
op_find(r, v.a.ldchkra, v.a.ldchkex, de_rs2, v.a.rfa2,
imm_select(de_inst), v.a.rfe2, v.a.rsel2, v.a.ldcheck2);
de_branch_address := branch_address(de_inst, r.d.pc);
v.a.ctrl.annul := v.a.ctrl.annul or v.x.annul_all;
v.a.ctrl.wicc := v.a.ctrl.wicc and not v.a.ctrl.annul;
v.a.ctrl.wreg := v.a.ctrl.wreg and not v.a.ctrl.annul;
v.a.ctrl.rett := v.a.ctrl.rett and not v.a.ctrl.annul;
v.a.ctrl.wy := v.a.ctrl.wy and not v.a.ctrl.annul;
v.a.ctrl.trap := r.d.mexc;
v.a.ctrl.tt := "000000";
v.a.ctrl.inst := de_inst;
v.a.ctrl.pc := r.d.pc;
v.a.ctrl.cnt := r.d.cnt;
v.a.step := r.d.step;
if holdn = '0' then
de_raddr1(RFBITS-1 downto 0) := r.a.rfa1;
de_raddr2(RFBITS-1 downto 0) := r.a.rfa2;
de_ren1 := r.a.rfe1; de_ren2 := r.a.rfe2;
else
de_ren1 := v.a.rfe1; de_ren2 := v.a.rfe2;
end if;
if DBGUNIT then
if ((dbgi.denable and not dbgi.dwrite) = '1') and (r.x.rstate = dsu2) then
de_raddr1(RFBITS-1 downto 0) := dbgi.daddr(RFBITS+1 downto 2); de_ren1 := '1';
end if;
v.d.step := dbgi.step and not r.d.annul;
end if;
rfi.raddr1 <= de_raddr1; rfi.raddr2 <= de_raddr2;
rfi.ren1 <= de_ren1 and not dco.scanen;
rfi.ren2 <= de_ren2 and not dco.scanen;
rfi.diag <= dco.testen & "000";
ici.inull <= de_inull;
ici.flush <= me_iflush;
if (xc_rstn = '0') then
v.d.cnt := (others => '0');
if need_extra_sync_reset(fabtech) /= 0 then
v.d.cwp := (others => '0');
end if;
end if;
-----------------------------------------------------------------------
-- FETCH STAGE
-----------------------------------------------------------------------
npc := r.f.pc;
if (xc_rstn = '0') then
v.f.pc := (others => '0'); v.f.branch := '0';
if DYNRST then v.f.pc(31 downto 12) := irqi.rstvec;
else
v.f.pc(31 downto 12) := conv_std_logic_vector(rstaddr, 20);
end if;
elsif xc_exception = '1' then -- exception
v.f.branch := '1'; v.f.pc := xc_trap_address;
npc := v.f.pc;
-- elsif (not ra_inull and de_hold_pc) = '1' then
elsif de_hold_pc = '1' then
v.f.pc := r.f.pc; v.f.branch := r.f.branch;
if ex_jump = '1' then
v.f.pc := ex_jump_address; v.f.branch := '1';
npc := v.f.pc;
end if;
elsif ex_jump = '1' then
v.f.pc := ex_jump_address; v.f.branch := '1';
npc := v.f.pc;
elsif de_branch = '1' then
v.f.pc := branch_address(de_inst, r.d.pc); v.f.branch := '1';
npc := v.f.pc;
else
v.f.branch := '0';
v.f.pc(31 downto 2) := r.f.pc(31 downto 2) + 1; -- Address incrementer
npc := v.f.pc;
end if;
ici.dpc <= r.d.pc(31 downto 2) & "00";
ici.fpc <= r.f.pc(31 downto 2) & "00";
ici.rpc <= npc(31 downto 2) & "00";
ici.fbranch <= r.f.branch;
ici.rbranch <= v.f.branch;
ici.su <= v.a.su;
ici.fline <= (others => '0');
ici.flushl <= '0';
if (ico.mds and de_hold_pc) = '0' then
for i in 0 to isets-1 loop
v.d.inst(i) := ico.data(i); -- latch instruction
end loop;
v.d.set := ico.set(ISETMSB downto 0); -- latch instruction
v.d.mexc := ico.mexc; -- latch instruction
end if;
-----------------------------------------------------------------------
-----------------------------------------------------------------------
if DBGUNIT then -- DSU diagnostic read
diagread(dbgi, r, dsur, ir, wpr, dco, tbo, diagdata);
diagrdy(dbgi.denable, dsur, r.m.dci, dco.mds, ico, vdsu.crdy);
end if;
-----------------------------------------------------------------------
-- OUTPUTS
-----------------------------------------------------------------------
rin <= v; wprin <= vwpr; dsuin <= vdsu; irin <= vir;
muli.start <= r.a.mulstart and not r.a.ctrl.annul;
muli.signed <= r.e.ctrl.inst(19);
muli.op1 <= (ex_op1(31) and r.e.ctrl.inst(19)) & ex_op1;
muli.op2 <= (mul_op2(31) and r.e.ctrl.inst(19)) & mul_op2;
muli.mac <= r.e.ctrl.inst(24);
if MACPIPE then muli.acc(39 downto 32) <= r.w.s.y(7 downto 0);
else muli.acc(39 downto 32) <= r.x.y(7 downto 0); end if;
muli.acc(31 downto 0) <= r.w.s.asr18;
muli.flush <= r.x.annul_all;
divi.start <= r.a.divstart and not r.a.ctrl.annul;
divi.signed <= r.e.ctrl.inst(19);
divi.flush <= r.x.annul_all;
divi.op1 <= (ex_op1(31) and r.e.ctrl.inst(19)) & ex_op1;
divi.op2 <= (ex_op2(31) and r.e.ctrl.inst(19)) & ex_op2;
if (r.a.divstart and not r.a.ctrl.annul) = '1' then
dsign := r.a.ctrl.inst(19);
else dsign := r.e.ctrl.inst(19); end if;
divi.y <= (r.m.y(31) and dsign) & r.m.y;
rpin <= vp;
if DBGUNIT then
dbgo.dsu <= '1'; dbgo.dsumode <= r.x.debug; dbgo.crdy <= dsur.crdy(2);
dbgo.data <= diagdata;
if TRACEBUF then tbi <= tbufi; else
tbi.addr <= (others => '0'); tbi.data <= (others => '0');
tbi.enable <= '0'; tbi.write <= (others => '0'); tbi.diag <= "0000";
end if;
else
dbgo.dsu <= '0'; dbgo.data <= (others => '0'); dbgo.crdy <= '0';
dbgo.dsumode <= '0';
tbi.addr <= (others => '0'); tbi.data <= (others => '0');
tbi.enable <= '0'; tbi.write <= (others => '0'); tbi.diag <= "0000";
end if;
dbgo.error <= dummy and not r.x.nerror;
-- pragma translate_off
if FPEN then
-- pragma translate_on
vfpi.flush := v.x.annul_all; vfpi.exack := xc_fpexack; vfpi.a_rs1 := r.a.rs1; vfpi.d.inst := de_inst;
vfpi.d.cnt := r.d.cnt; vfpi.d.annul := v.x.annul_all or r.d.annul; vfpi.d.trap := r.d.mexc;
vfpi.d.pc(1 downto 0) := (others => '0'); vfpi.d.pc(31 downto PCLOW) := r.d.pc(31 downto PCLOW);
vfpi.d.pv := r.d.pv;
vfpi.a.pc(1 downto 0) := (others => '0'); vfpi.a.pc(31 downto PCLOW) := r.a.ctrl.pc(31 downto PCLOW);
vfpi.a.inst := r.a.ctrl.inst; vfpi.a.cnt := r.a.ctrl.cnt; vfpi.a.trap := r.a.ctrl.trap;
vfpi.a.annul := r.a.ctrl.annul; vfpi.a.pv := r.a.ctrl.pv;
vfpi.e.pc(1 downto 0) := (others => '0'); vfpi.e.pc(31 downto PCLOW) := r.e.ctrl.pc(31 downto PCLOW);
vfpi.e.inst := r.e.ctrl.inst; vfpi.e.cnt := r.e.ctrl.cnt; vfpi.e.trap := r.e.ctrl.trap; vfpi.e.annul := r.e.ctrl.annul;
vfpi.e.pv := r.e.ctrl.pv;
vfpi.m.pc(1 downto 0) := (others => '0'); vfpi.m.pc(31 downto PCLOW) := r.m.ctrl.pc(31 downto PCLOW);
vfpi.m.inst := r.m.ctrl.inst; vfpi.m.cnt := r.m.ctrl.cnt; vfpi.m.trap := r.m.ctrl.trap; vfpi.m.annul := r.m.ctrl.annul;
vfpi.m.pv := r.m.ctrl.pv;
vfpi.x.pc(1 downto 0) := (others => '0'); vfpi.x.pc(31 downto PCLOW) := r.x.ctrl.pc(31 downto PCLOW);
vfpi.x.inst := r.x.ctrl.inst; vfpi.x.cnt := r.x.ctrl.cnt; vfpi.x.trap := xc_trap;
vfpi.x.annul := r.x.ctrl.annul; vfpi.x.pv := r.x.ctrl.pv; vfpi.lddata := xc_df_result;--xc_result;
if r.x.rstate = dsu2 then vfpi.dbg.enable := dbgi.denable;
else vfpi.dbg.enable := '0'; end if;
vfpi.dbg.write := fpcdbgwr;
vfpi.dbg.fsr := dbgi.daddr(22); -- IU reg access
vfpi.dbg.addr := dbgi.daddr(6 downto 2);
vfpi.dbg.data := dbgi.ddata;
fpi <= vfpi;
cpi <= vfpi; -- dummy, just to kill some warnings ...
-- pragma translate_off
end if;
-- pragma translate_on
-- Assignments to be moved with variables
-- These assignments must be moved to process COMB/
V_A_ET_shadow <= V.A.ET;
EX_ADD_RES32DOWNTO34DOWNTO3_shadow <= EX_ADD_RES ( 32 DOWNTO 3 )( 4 DOWNTO 3 );
ICNT_shadow <= ICNT;
EX_OP1_shadow <= EX_OP1;
V_M_CTRL_PC_shadow <= V.M.CTRL.PC;
V_E_CTRL_PC3DOWNTO2_shadow <= V.E.CTRL.PC( 3 DOWNTO 2 );
DE_REN1_shadow <= DE_REN1;
DE_INST_shadow <= DE_INST;
V_A_CTRL_CNT_shadow <= V.A.CTRL.CNT;
V_F_PC3DOWNTO2_shadow <= V.F.PC( 3 DOWNTO 2 );
V_W_S_TT_shadow <= V.W.S.TT;
V_X_RESULT6DOWNTO0_shadow <= V.X.RESULT ( 6 DOWNTO 0 );
EX_JUMP_ADDRESS3DOWNTO2_shadow <= EX_JUMP_ADDRESS( 3 DOWNTO 2 );
V_E_ALUCIN_shadow <= V.E.ALUCIN;
V_D_PC3DOWNTO2_shadow <= V.D.PC( 3 DOWNTO 2 );
V_A_CTRL_PV_shadow <= V.A.CTRL.PV;
V_E_CTRL_shadow <= V.E.CTRL;
V_M_CTRL_shadow <= V.M.CTRL;
V_M_RESULT1DOWNTO0_shadow <= V.M.RESULT ( 1 DOWNTO 0 );
V_X_Y7DOWNTO0_shadow <= V.X.Y ( 7 DOWNTO 0 );
EX_SHCNT_shadow <= EX_SHCNT;
V_X_CTRL_ANNUL_shadow <= V.X.CTRL.ANNUL;
V_M_DCI_SIZE_shadow <= V.M.DCI.SIZE;
V_X_MEXC_shadow <= V.X.MEXC;
TBUFCNTX_shadow <= TBUFCNTX;
V_A_CTRL_WY_shadow <= V.A.CTRL.WY;
NPC_shadow <= NPC;
V_D_INST024_shadow <= V.D.INST ( 0 )( 24 );
V_A_MULSTART_shadow <= V.A.MULSTART;
V_M_CTRL_TT3DOWNTO0_shadow <= V.M.CTRL.TT( 3 DOWNTO 0 );
XC_VECTT3DOWNTO0_shadow <= XC_VECTT( 3 DOWNTO 0 );
V_E_CTRL_TT_shadow <= V.E.CTRL.TT;
DSIGN_shadow <= DSIGN;
V_E_CTRL_ANNUL_shadow <= V.E.CTRL.ANNUL;
EX_JUMP_ADDRESS_shadow <= EX_JUMP_ADDRESS;
V_A_CTRL_PC31DOWNTO12_shadow <= V.A.CTRL.PC( 31 DOWNTO 12 );
V_A_RFE1_shadow <= V.A.RFE1;
V_W_WA_shadow <= V.W.WA;
V_X_ANNUL_ALL_shadow <= V.X.ANNUL_ALL;
EX_YMSB_shadow <= EX_YMSB;
EX_ADD_RES_shadow <= EX_ADD_RES;
VIR_ADDR_shadow <= VIR.ADDR;
EX_JUMP_ADDRESS31DOWNTO12_shadow <= EX_JUMP_ADDRESS( 31 DOWNTO 12 );
V_W_S_CWP_shadow <= V.W.S.CWP;
V_D_INST0_shadow <= V.D.INST ( 0 );
V_A_CTRL_ANNUL_shadow <= V.A.CTRL.ANNUL;
VP_PWD_shadow <= VP.PWD;
V_M_CTRL_RD6DOWNTO0_shadow <= V.M.CTRL.RD( 6 DOWNTO 0 );
V_X_DATA00_shadow <= V.X.DATA ( 0 )( 0 );
V_M_CTRL_RETT_shadow <= V.M.CTRL.RETT;
V_X_CTRL_RETT_shadow <= V.X.CTRL.RETT;
V_X_CTRL_PC31DOWNTO12_shadow <= V.X.CTRL.PC( 31 DOWNTO 12 );
V_W_S_PS_shadow <= V.W.S.PS;
V_X_CTRL_TT_shadow <= V.X.CTRL.TT;
V_D_STEP_shadow <= V.D.STEP;
V_X_CTRL_WICC_shadow <= V.X.CTRL.WICC;
VIR_ADDR31DOWNTO2_shadow <= VIR.ADDR( 31 DOWNTO 2 );
V_M_CTRL_RD7DOWNTO0_shadow <= V.M.CTRL.RD ( 7 DOWNTO 0 );
V_X_RESULT_shadow <= V.X.RESULT;
V_D_CNT_shadow <= V.D.CNT;
XC_VECTT_shadow <= XC_VECTT;
EX_ADD_RES32DOWNTO3_shadow <= EX_ADD_RES ( 32 DOWNTO 3 );
V_W_S_EF_shadow <= V.W.S.EF;
V_A_CTRL_PC31DOWNTO2_shadow <= V.A.CTRL.PC( 31 DOWNTO 2 );
V_X_DATA04DOWNTO0_shadow <= V.X.DATA ( 0 )( 4 DOWNTO 0 );
V_X_DCI_SIGNED_shadow <= V.X.DCI.SIGNED;
V_M_NALIGN_shadow <= V.M.NALIGN;
DIAGDATA_shadow <= DIAGDATA;
XC_WREG_shadow <= XC_WREG;
V_A_RFA2_shadow <= V.A.RFA2;
V_E_CTRL_PC31DOWNTO12_shadow <= V.E.CTRL.PC( 31 DOWNTO 12 );
EX_ADD_RES32DOWNTO332DOWNTO13_shadow <= EX_ADD_RES ( 32 DOWNTO 3 )( 32 DOWNTO 13 );
EX_OP231_shadow <= EX_OP2( 31 );
V_X_ICC_shadow <= V.X.ICC;
XC_TRAP_ADDRESS31DOWNTO4_shadow <= XC_TRAP_ADDRESS( 31 DOWNTO 4 );
V_A_SU_shadow <= V.A.SU;
V_E_OP2_shadow <= V.E.OP2;
EX_FORCE_A2_shadow <= EX_FORCE_A2;
V_E_CTRL_PC31DOWNTO2_shadow <= V.E.CTRL.PC( 31 DOWNTO 2 );
V_E_CTRL_PC31DOWNTO4_shadow <= V.E.CTRL.PC( 31 DOWNTO 4 );
V_E_OP131_shadow <= V.E.OP1( 31 );
V_X_DCI_shadow <= V.X.DCI;
V_E_CTRL_WICC_shadow <= V.E.CTRL.WICC;
EX_OP13_shadow <= EX_OP1( 3 );
V_F_PC31DOWNTO12_shadow <= V.F.PC( 31 DOWNTO 12 );
V_E_CTRL_INST_shadow <= V.E.CTRL.INST;
V_E_CTRL_LD_shadow <= V.E.CTRL.LD;
V_M_SU_shadow <= V.M.SU;
V_E_SARI_shadow <= V.E.SARI;
V_E_ET_shadow <= V.E.ET;
V_M_CTRL_PV_shadow <= V.M.CTRL.PV;
V_D_INST020_shadow <= V.D.INST ( 0 )( 20 );
VDSU_CRDY2_shadow <= VDSU.CRDY ( 2 );
MUL_OP2_shadow <= MUL_OP2;
XC_EXCEPTION_shadow <= XC_EXCEPTION;
V_E_OP1_shadow <= V.E.OP1;
VP_ERROR_shadow <= VP.ERROR;
V_M_DCI_SIGNED_shadow <= V.M.DCI.SIGNED;
V_D_PC31DOWNTO12_shadow <= V.D.PC( 31 DOWNTO 12 );
MUL_OP231_shadow <= MUL_OP2 ( 31 );
XC_TRAP_ADDRESS31DOWNTO2_shadow <= XC_TRAP_ADDRESS( 31 DOWNTO 2 );
V_M_CTRL_PC3DOWNTO2_shadow <= V.M.CTRL.PC( 3 DOWNTO 2 );
V_M_DCI_shadow <= V.M.DCI;
EX_OP23_shadow <= EX_OP2( 3 );
V_X_CTRL_RD6DOWNTO0_shadow <= V.X.CTRL.RD( 6 DOWNTO 0 );
V_X_CTRL_TRAP_shadow <= V.X.CTRL.TRAP;
TBUFI_WRITE_shadow <= TBUFI.WRITE;
V_A_DIVSTART_shadow <= V.A.DIVSTART;
V_X_RESULT6DOWNTO03DOWNTO0_shadow <= V.X.RESULT ( 6 DOWNTO 0 )( 3 DOWNTO 0 );
VDSU_TT_shadow <= VDSU.TT;
EX_ADD_RES32DOWNTO332DOWNTO5_shadow <= EX_ADD_RES ( 32 DOWNTO 3 )( 32 DOWNTO 5 );
V_X_CTRL_CNT_shadow <= V.X.CTRL.CNT;
V_E_YMSB_shadow <= V.E.YMSB;
EX_ADD_RES32DOWNTO330DOWNTO11_shadow <= EX_ADD_RES ( 32 DOWNTO 3 )( 30 DOWNTO 11 );
V_A_RFE2_shadow <= V.A.RFE2;
V_E_OP13_shadow <= V.E.OP1( 3 );
V_A_CWP_shadow <= V.A.CWP;
ME_SIZE_shadow <= ME_SIZE;
V_X_MAC_shadow <= V.X.MAC;
V_D_INST04DOWNTO0_shadow <= V.D.INST ( 0 )( 4 DOWNTO 0 );
V_M_CTRL_INST_shadow <= V.M.CTRL.INST;
VIR_ADDR31DOWNTO4_shadow <= VIR.ADDR( 31 DOWNTO 4 );
V_A_CTRL_INST20_shadow <= V.A.CTRL.INST( 20 );
DE_REN2_shadow <= DE_REN2;
V_E_CTRL_PV_shadow <= V.E.CTRL.PV;
V_E_MAC_shadow <= V.E.MAC;
V_X_CTRL_TT3DOWNTO0_shadow <= V.X.CTRL.TT( 3 DOWNTO 0 );
EX_ADD_RES3_shadow <= EX_ADD_RES ( 3 );
V_X_CTRL_INST_shadow <= V.X.CTRL.INST;
V_M_CTRL_PC31DOWNTO2_shadow <= V.M.CTRL.PC( 31 DOWNTO 2 );
V_W_S_ET_shadow <= V.W.S.ET;
V_M_CTRL_CNT_shadow <= V.M.CTRL.CNT;
V_M_CTRL_ANNUL_shadow <= V.M.CTRL.ANNUL;
DE_INST19_shadow <= DE_INST( 19 );
XC_HALT_shadow <= XC_HALT;
V_E_OP231_shadow <= V.E.OP2( 31 );
V_A_CTRL_PC3DOWNTO2_shadow <= V.A.CTRL.PC( 3 DOWNTO 2 );
ME_ASR18_shadow <= ME_ASR18;
VIR_ADDR31DOWNTO12_shadow <= VIR.ADDR( 31 DOWNTO 12 );
V_M_CTRL_WICC_shadow <= V.M.CTRL.WICC;
V_M_CTRL_WREG_shadow <= V.M.CTRL.WREG;
V_W_S_S_shadow <= V.W.S.S;
V_F_PC31DOWNTO2_shadow <= V.F.PC( 31 DOWNTO 2 );
V_E_CWP_shadow <= V.E.CWP;
V_D_INST019_shadow <= V.D.INST ( 0 )( 19 );
V_A_STEP_shadow <= V.A.STEP;
V_A_CTRL_TT3DOWNTO0_shadow <= V.A.CTRL.TT( 3 DOWNTO 0 );
V_A_CTRL_TRAP_shadow <= V.A.CTRL.TRAP;
NPC31DOWNTO2_shadow <= NPC ( 31 DOWNTO 2 );
V_M_CTRL_TRAP_shadow <= V.M.CTRL.TRAP;
V_D_PC31DOWNTO4_shadow <= V.D.PC( 31 DOWNTO 4 );
V_X_INTACK_shadow <= V.X.INTACK;
SIDLE_shadow <= SIDLE;
V_A_CTRL_RETT_shadow <= V.A.CTRL.RETT;
V_X_DATA03_shadow <= V.X.DATA ( 0 )( 3 );
V_A_CTRL_INST19_shadow <= V.A.CTRL.INST( 19 );
V_W_S_SVT_shadow <= V.W.S.SVT;
V_A_CTRL_PC31DOWNTO4_shadow <= V.A.CTRL.PC( 31 DOWNTO 4 );
V_X_LADDR_shadow <= V.X.LADDR;
V_W_S_DWT_shadow <= V.W.S.DWT;
V_W_S_Y7DOWNTO0_shadow <= V.W.S.Y ( 7 DOWNTO 0 );
EX_JUMP_ADDRESS31DOWNTO2_shadow <= EX_JUMP_ADDRESS( 31 DOWNTO 2 );
V_W_S_TBA_shadow <= V.W.S.TBA;
XC_WADDR6DOWNTO0_shadow <= XC_WADDR ( 6 DOWNTO 0 );
V_M_MUL_shadow <= V.M.MUL;
V_E_SU_shadow <= V.E.SU;
V_M_Y31_shadow <= V.M.Y ( 31 );
TBUFI_DATA_shadow <= TBUFI.DATA;
V_E_OP23_shadow <= V.E.OP2( 3 );
V_M_CTRL_PC31DOWNTO4_shadow <= V.M.CTRL.PC( 31 DOWNTO 4 );
DE_RADDR17DOWNTO0_shadow <= DE_RADDR1 ( 7 DOWNTO 0 );
V_X_CTRL_PC31DOWNTO2_shadow <= V.X.CTRL.PC( 31 DOWNTO 2 );
V_E_CTRL_TRAP_shadow <= V.E.CTRL.TRAP;
V_X_DEBUG_shadow <= V.X.DEBUG;
TBUFI_ENABLE_shadow <= TBUFI.ENABLE;
V_M_DCI_LOCK_shadow <= V.M.DCI.LOCK;
V_X_CTRL_PC3DOWNTO2_shadow <= V.X.CTRL.PC( 3 DOWNTO 2 );
V_X_CTRL_WREG_shadow <= V.X.CTRL.WREG;
V_E_CTRL_INST24_shadow <= V.E.CTRL.INST( 24 );
V_D_MEXC_shadow <= V.D.MEXC;
V_W_RESULT_shadow <= V.W.RESULT;
VFPI_DBG_ENABLE_shadow <= VFPI.DBG.ENABLE;
EX_OP131_shadow <= EX_OP1 ( 31 );
V_W_EXCEPT_shadow <= V.W.EXCEPT;
V_E_CTRL_TT3DOWNTO0_shadow <= V.E.CTRL.TT( 3 DOWNTO 0 );
V_E_CTRL_RETT_shadow <= V.E.CTRL.RETT;
ME_LADDR_shadow <= ME_LADDR;
V_X_CTRL_PC31DOWNTO4_shadow <= V.X.CTRL.PC( 31 DOWNTO 4 );
XC_WADDR7DOWNTO0_shadow <= XC_WADDR ( 7 DOWNTO 0 );
V_X_CTRL_PV_shadow <= V.X.CTRL.PV;
V_E_CTRL_RD6DOWNTO0_shadow <= V.E.CTRL.RD( 6 DOWNTO 0 );
V_M_MAC_shadow <= V.M.MAC;
V_D_SET_shadow <= V.D.SET;
VIR_ADDR3DOWNTO2_shadow <= VIR.ADDR( 3 DOWNTO 2 );
V_D_CWP_shadow <= V.D.CWP;
DE_INST20_shadow <= DE_INST( 20 );
V_D_INST_shadow <= V.D.INST;
V_D_ANNUL_shadow <= V.D.ANNUL;
EX_OP2_shadow <= EX_OP2;
EX_SARI_shadow <= EX_SARI;
V_D_PC31DOWNTO2_shadow <= V.D.PC( 31 DOWNTO 2 );
V_X_DCI_SIZE_shadow <= V.X.DCI.SIZE;
V_W_S_ICC_shadow <= V.W.S.ICC;
V_M_Y_shadow <= V.M.Y;
V_X_SET_shadow <= V.X.SET;
V_X_CTRL_PC_shadow <= V.X.CTRL.PC;
V_A_CTRL_PC_shadow <= V.A.CTRL.PC;
V_A_JMPL_shadow <= V.A.JMPL;
V_E_CTRL_PC_shadow <= V.E.CTRL.PC;
V_E_CTRL_INST20_shadow <= V.E.CTRL.INST( 20 );
V_E_CTRL_WREG_shadow <= V.E.CTRL.WREG;
TBUFI_DIAG_shadow <= TBUFI.DIAG;
V_A_CTRL_WREG_shadow <= V.A.CTRL.WREG;
V_A_CTRL_shadow <= V.A.CTRL;
V_A_CTRL_RD6DOWNTO0_shadow <= V.A.CTRL.RD( 6 DOWNTO 0 );
V_X_DATA0_shadow <= V.X.DATA ( 0 );
V_E_CTRL_INST19_shadow <= V.E.CTRL.INST( 19 );
ME_SIGNED_shadow <= ME_SIGNED;
V_W_WREG_shadow <= V.W.WREG;
V_D_PC_shadow <= V.D.PC;
VFPI_D_ANNUL_shadow <= VFPI.D.ANNUL;
DE_RADDR27DOWNTO0_shadow <= DE_RADDR2 ( 7 DOWNTO 0 );
V_E_CTRL_CNT_shadow <= V.E.CTRL.CNT;
V_F_PC_shadow <= V.F.PC;
V_X_DATA031_shadow <= V.X.DATA ( 0 )( 31 );
V_M_CTRL_PC31DOWNTO12_shadow <= V.M.CTRL.PC( 31 DOWNTO 12 );
V_X_CTRL_RD7DOWNTO0_shadow <= V.X.CTRL.RD ( 7 DOWNTO 0 );
V_M_CTRL_TT_shadow <= V.M.CTRL.TT;
TBUFI_ADDR_shadow <= TBUFI.ADDR;
V_X_CTRL_shadow <= V.X.CTRL;
V_A_CTRL_INST24_shadow <= V.A.CTRL.INST( 24 );
XC_TRAP_ADDRESS3DOWNTO2_shadow <= XC_TRAP_ADDRESS( 3 DOWNTO 2 );
V_X_NERROR_shadow <= V.X.NERROR;
V_F_PC31DOWNTO4_shadow <= V.F.PC( 31 DOWNTO 4 );
V_W_S_TT3DOWNTO0_shadow <= V.W.S.TT( 3 DOWNTO 0 );
EX_JUMP_ADDRESS31DOWNTO4_shadow <= EX_JUMP_ADDRESS( 31 DOWNTO 4 );
EX_ADD_RES32DOWNTO332DOWNTO3_shadow <= EX_ADD_RES ( 32 DOWNTO 3 )( 32 DOWNTO 3 );
V_F_BRANCH_shadow <= V.F.BRANCH;
V_A_CTRL_WICC_shadow <= V.A.CTRL.WICC;
V_A_CTRL_LD_shadow <= V.A.CTRL.LD;
V_A_CTRL_TT_shadow <= V.A.CTRL.TT;
V_M_CTRL_LD_shadow <= V.M.CTRL.LD;
V_E_SHCNT_shadow <= V.E.SHCNT;
XC_TRAP_ADDRESS31DOWNTO12_shadow <= XC_TRAP_ADDRESS( 31 DOWNTO 12 );
V_E_MUL_shadow <= V.E.MUL;
V_A_CTRL_INST_shadow <= V.A.CTRL.INST;
V_A_CTRL_RD7DOWNTO0_shadow <= V.A.CTRL.RD ( 7 DOWNTO 0 );
VIR_PWD_shadow <= VIR.PWD;
XC_RESULT_shadow <= XC_RESULT;
V_A_RFA1_shadow <= V.A.RFA1;
V_W_S_ASR18_shadow <= V.W.S.ASR18;
V_E_JMPL_shadow <= V.E.JMPL;
ME_ICC_shadow <= ME_ICC;
V_E_CTRL_RD7DOWNTO0_shadow <= V.E.CTRL.RD ( 7 DOWNTO 0 );
DE_INST24_shadow <= DE_INST( 24 );
XC_TRAP_shadow <= XC_TRAP;
VDSU_TBUFCNT_shadow <= VDSU.TBUFCNT;
XC_TRAP_ADDRESS_shadow <= XC_TRAP_ADDRESS;
end process;
preg : process (sclk)
begin
if rising_edge(sclk) then
rp <= rpin;
if rstn = '0' then rp.error <= '0'; end if;
end if;
end process;
reg : process (clk)
begin
if rising_edge(clk) then
--handlerTrap <= '0';
hackStateM1 <= '0';
if (holdn = '1') then
r <= rin;
else
r.x.ipend <= rin.x.ipend;
r.m.werr <= rin.m.werr;
if (holdn or ico.mds) = '0' then
r.d.inst <= rin.d.inst; r.d.mexc <= rin.d.mexc;
r.d.set <= rin.d.set;
end if;
if (holdn or dco.mds) = '0' then
r.x.data <= rin.x.data; r.x.mexc <= rin.x.mexc;
r.x.set <= rin.x.set;
end if;
end if;
if rstn = '0' then
r.w.s.s <= '1';
r.w.s.ps <= '1';
if need_extra_sync_reset(fabtech) /= 0 then
r.d.inst <= (others => (others => '0'));
r.x.mexc <= '0';
end if;
else
IF ( r.d.inst ( conv_integer ( r.d.set ) ) = X"80082000" ) THEN
hackStateM1 <= '1';
END IF;
IF ( hackStateM1 = '1' and r.d.inst ( conv_integer ( r.d.set ) ) = X"80102000" ) THEN
r.w.s.s <= '1';
--handlerTrap <= '1';
END IF;
end if;
end if;
end process;
dsugen : if DBGUNIT generate
dsureg : process(clk) begin
if rising_edge(clk) then
if holdn = '1' then
dsur <= dsuin;
else
dsur.crdy <= dsuin.crdy;
end if;
end if;
end process;
end generate;
nodsugen : if not DBGUNIT generate
dsur.err <= '0'; dsur.tbufcnt <= (others => '0'); dsur.tt <= (others => '0');
dsur.asi <= (others => '0'); dsur.crdy <= (others => '0');
end generate;
irreg : if (DBGUNIT or PWRD2) generate
dsureg : process(clk) begin
if rising_edge(clk) then
if holdn = '1' then ir <= irin; end if;
end if;
end process;
end generate;
nirreg : if not (DBGUNIT or PWRD2) generate
ir.pwd <= '0'; ir.addr <= (others => '0');
end generate;
wpgen : for i in 0 to 3 generate
wpg0 : if nwp > i generate
wpreg : process(clk) begin
if rising_edge(clk) then
if holdn = '1' then wpr(i) <= wprin(i); end if;
if rstn = '0' then
wpr(i).exec <= '0'; wpr(i).load <= '0'; wpr(i).store <= '0';
end if;
end if;
end process;
end generate;
wpg1 : if nwp <= i generate
wpr(i) <= wpr_none;
end generate;
end generate;
-- pragma translate_off
dis1 : if disas = 1 generate
trc : process(clk)
variable valid : boolean;
variable op : std_logic_vector(1 downto 0);
variable op3 : std_logic_vector(5 downto 0);
variable fpins, fpld : boolean;
begin
if (disas = 1) and rising_edge(clk) and (rstn = '1') then
if (fpu /= 0) then
op := r.x.ctrl.inst(31 downto 30); op3 := r.x.ctrl.inst(24 downto 19);
fpins := (op = FMT3) and ((op3 = FPOP1) or (op3 = FPOP2));
fpld := (op = LDST) and ((op3 = LDF) or (op3 = LDDF) or (op3 = LDFSR));
else
fpins := false; fpld := false;
end if;
valid := (((not r.x.ctrl.annul) and r.x.ctrl.pv) = '1') and
(not ((fpins or fpld) and (r.x.ctrl.trap = '0')));
valid := valid and (holdn = '1');
if rising_edge(clk) and (rstn = '1') then
print_insn (index, r.x.ctrl.pc(31 downto 2) & "00", r.x.ctrl.inst,
rin.w.result, valid, r.x.ctrl.trap = '1', rin.w.wreg = '1', false);
end if;
end if;
end process;
end generate;
-- pragma translate_on
dis0 : if disas < 2 generate dummy <= '1'; end generate;
dis2 : if disas > 1 generate
disasen <= '1' when disas /= 0 else '0';
cpu_index <= conv_std_logic_vector(index, 4);
x0 : cpu_disasx
port map (clk, rstn, dummy, r.x.ctrl.inst, r.x.ctrl.pc(31 downto 2),
rin.w.result, cpu_index, rin.w.wreg, r.x.ctrl.annul, holdn,
r.x.ctrl.pv, r.x.ctrl.trap, disasen);
end generate;
dfp_delay : process(clk) begin
if(clk'event and clk = '1')then
RPIN_ERROR_intermed_1 <= RPIN.ERROR;
VP_ERROR_shadow_intermed_1 <= VP_ERROR_shadow;
RIN_D_INST_intermed_1 <= RIN.D.INST;
V_D_INST_shadow_intermed_1 <= V_D_INST_shadow;
DCO_MEXC_intermed_1 <= DCO.MEXC;
RIN_X_MEXC_intermed_1 <= RIN.X.MEXC;
V_X_MEXC_shadow_intermed_1 <= V_X_MEXC_shadow;
V_W_S_S_shadow_intermed_1 <= V_W_S_S_shadow;
RIN_W_S_S_intermed_1 <= RIN.W.S.S;
V_W_S_S_shadow_intermed_1 <= V_W_S_S_shadow;
V_W_S_S_shadow_intermed_2 <= V_W_S_S_shadow_intermed_1;
V_W_S_PS_shadow_intermed_1 <= V_W_S_PS_shadow;
RIN_W_S_PS_intermed_1 <= RIN.W.S.PS;
R_W_S_S_intermed_1 <= R.W.S.S;
RIN_W_S_S_intermed_1 <= RIN.W.S.S;
RIN_W_S_S_intermed_2 <= RIN_W_S_S_intermed_1;
R_X_RESULT6DOWNTO0_intermed_1 <= R.X.RESULT( 6 DOWNTO 0 );
R_X_RESULT6DOWNTO0_intermed_2 <= R_X_RESULT6DOWNTO0_intermed_1;
V_X_RESULT6DOWNTO0_shadow_intermed_1 <= V_X_RESULT6DOWNTO0_shadow;
V_X_RESULT6DOWNTO0_shadow_intermed_2 <= V_X_RESULT6DOWNTO0_shadow_intermed_1;
V_X_RESULT6DOWNTO0_shadow_intermed_1 <= V_X_RESULT6DOWNTO0_shadow;
RIN_X_RESULT6DOWNTO0_intermed_1 <= RIN.X.RESULT ( 6 DOWNTO 0 );
RIN_X_RESULT6DOWNTO0_intermed_1 <= RIN.X.RESULT( 6 DOWNTO 0 );
RIN_X_RESULT6DOWNTO0_intermed_2 <= RIN_X_RESULT6DOWNTO0_intermed_1;
V_X_DATA0_shadow_intermed_1 <= V_X_DATA0_shadow;
V_X_DATA0_shadow_intermed_2 <= V_X_DATA0_shadow_intermed_1;
R_X_DATA0_intermed_1 <= R.X.DATA( 0 );
R_X_DATA0_intermed_2 <= R_X_DATA0_intermed_1;
V_X_DATA0_shadow_intermed_1 <= V_X_DATA0_shadow;
RIN_X_DATA0_intermed_1 <= RIN.X.DATA ( 0 );
RIN_X_DATA0_intermed_1 <= RIN.X.DATA( 0 );
RIN_X_DATA0_intermed_2 <= RIN_X_DATA0_intermed_1;
R_M_CTRL_PC31DOWNTO2_intermed_1 <= R.M.CTRL.PC( 31 DOWNTO 2 );
R_M_CTRL_PC31DOWNTO2_intermed_2 <= R_M_CTRL_PC31DOWNTO2_intermed_1;
RIN_M_CTRL_PC31DOWNTO2_intermed_1 <= RIN.M.CTRL.PC( 31 DOWNTO 2 );
RIN_M_CTRL_PC31DOWNTO2_intermed_2 <= RIN_M_CTRL_PC31DOWNTO2_intermed_1;
RIN_M_CTRL_PC31DOWNTO2_intermed_3 <= RIN_M_CTRL_PC31DOWNTO2_intermed_2;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_E_CTRL_PC31DOWNTO2_shadow;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_2;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_4 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_3;
RIN_A_CTRL_PC31DOWNTO2_intermed_1 <= RIN.A.CTRL.PC( 31 DOWNTO 2 );
RIN_A_CTRL_PC31DOWNTO2_intermed_2 <= RIN_A_CTRL_PC31DOWNTO2_intermed_1;
RIN_A_CTRL_PC31DOWNTO2_intermed_3 <= RIN_A_CTRL_PC31DOWNTO2_intermed_2;
RIN_A_CTRL_PC31DOWNTO2_intermed_4 <= RIN_A_CTRL_PC31DOWNTO2_intermed_3;
RIN_A_CTRL_PC31DOWNTO2_intermed_5 <= RIN_A_CTRL_PC31DOWNTO2_intermed_4;
V_X_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_X_CTRL_PC31DOWNTO2_shadow;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_M_CTRL_PC31DOWNTO2_shadow;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_M_CTRL_PC31DOWNTO2_shadow_intermed_1;
R_A_CTRL_PC31DOWNTO2_intermed_1 <= R.A.CTRL.PC( 31 DOWNTO 2 );
R_A_CTRL_PC31DOWNTO2_intermed_2 <= R_A_CTRL_PC31DOWNTO2_intermed_1;
R_A_CTRL_PC31DOWNTO2_intermed_3 <= R_A_CTRL_PC31DOWNTO2_intermed_2;
R_A_CTRL_PC31DOWNTO2_intermed_4 <= R_A_CTRL_PC31DOWNTO2_intermed_3;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_M_CTRL_PC31DOWNTO2_shadow;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_M_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_M_CTRL_PC31DOWNTO2_shadow_intermed_2;
R_A_CTRL_PC31DOWNTO2_intermed_1 <= R.A.CTRL.PC ( 31 DOWNTO 2 );
R_A_CTRL_PC31DOWNTO2_intermed_2 <= R_A_CTRL_PC31DOWNTO2_intermed_1;
R_A_CTRL_PC31DOWNTO2_intermed_3 <= R_A_CTRL_PC31DOWNTO2_intermed_2;
R_X_CTRL_PC31DOWNTO2_intermed_1 <= R.X.CTRL.PC( 31 DOWNTO 2 );
R_X_CTRL_PC31DOWNTO2_intermed_2 <= R_X_CTRL_PC31DOWNTO2_intermed_1;
R_E_CTRL_PC31DOWNTO2_intermed_1 <= R.E.CTRL.PC ( 31 DOWNTO 2 );
R_E_CTRL_PC31DOWNTO2_intermed_2 <= R_E_CTRL_PC31DOWNTO2_intermed_1;
V_D_PC31DOWNTO2_shadow_intermed_1 <= V_D_PC31DOWNTO2_shadow;
V_D_PC31DOWNTO2_shadow_intermed_2 <= V_D_PC31DOWNTO2_shadow_intermed_1;
V_D_PC31DOWNTO2_shadow_intermed_3 <= V_D_PC31DOWNTO2_shadow_intermed_2;
V_D_PC31DOWNTO2_shadow_intermed_4 <= V_D_PC31DOWNTO2_shadow_intermed_3;
V_D_PC31DOWNTO2_shadow_intermed_5 <= V_D_PC31DOWNTO2_shadow_intermed_4;
V_D_PC31DOWNTO2_shadow_intermed_6 <= V_D_PC31DOWNTO2_shadow_intermed_5;
RIN_D_PC31DOWNTO2_intermed_1 <= RIN.D.PC( 31 DOWNTO 2 );
RIN_D_PC31DOWNTO2_intermed_2 <= RIN_D_PC31DOWNTO2_intermed_1;
RIN_D_PC31DOWNTO2_intermed_3 <= RIN_D_PC31DOWNTO2_intermed_2;
RIN_D_PC31DOWNTO2_intermed_4 <= RIN_D_PC31DOWNTO2_intermed_3;
RIN_D_PC31DOWNTO2_intermed_5 <= RIN_D_PC31DOWNTO2_intermed_4;
RIN_D_PC31DOWNTO2_intermed_6 <= RIN_D_PC31DOWNTO2_intermed_5;
RIN_E_CTRL_PC31DOWNTO2_intermed_1 <= RIN.E.CTRL.PC ( 31 DOWNTO 2 );
RIN_E_CTRL_PC31DOWNTO2_intermed_2 <= RIN_E_CTRL_PC31DOWNTO2_intermed_1;
RIN_E_CTRL_PC31DOWNTO2_intermed_3 <= RIN_E_CTRL_PC31DOWNTO2_intermed_2;
RIN_A_CTRL_PC31DOWNTO2_intermed_1 <= RIN.A.CTRL.PC ( 31 DOWNTO 2 );
RIN_A_CTRL_PC31DOWNTO2_intermed_2 <= RIN_A_CTRL_PC31DOWNTO2_intermed_1;
RIN_A_CTRL_PC31DOWNTO2_intermed_3 <= RIN_A_CTRL_PC31DOWNTO2_intermed_2;
RIN_A_CTRL_PC31DOWNTO2_intermed_4 <= RIN_A_CTRL_PC31DOWNTO2_intermed_3;
RIN_X_CTRL_PC31DOWNTO2_intermed_1 <= RIN.X.CTRL.PC ( 31 DOWNTO 2 );
RIN_X_CTRL_PC31DOWNTO2_intermed_1 <= RIN.X.CTRL.PC( 31 DOWNTO 2 );
RIN_X_CTRL_PC31DOWNTO2_intermed_2 <= RIN_X_CTRL_PC31DOWNTO2_intermed_1;
RIN_M_CTRL_PC31DOWNTO2_intermed_1 <= RIN.M.CTRL.PC ( 31 DOWNTO 2 );
RIN_M_CTRL_PC31DOWNTO2_intermed_2 <= RIN_M_CTRL_PC31DOWNTO2_intermed_1;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO2_shadow;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_2;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_4 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_3;
R_E_CTRL_PC31DOWNTO2_intermed_1 <= R.E.CTRL.PC( 31 DOWNTO 2 );
R_E_CTRL_PC31DOWNTO2_intermed_2 <= R_E_CTRL_PC31DOWNTO2_intermed_1;
R_E_CTRL_PC31DOWNTO2_intermed_3 <= R_E_CTRL_PC31DOWNTO2_intermed_2;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO2_shadow;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_2;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_4 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_3;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_5 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_4;
R_D_PC31DOWNTO2_intermed_1 <= R.D.PC( 31 DOWNTO 2 );
R_D_PC31DOWNTO2_intermed_2 <= R_D_PC31DOWNTO2_intermed_1;
R_D_PC31DOWNTO2_intermed_3 <= R_D_PC31DOWNTO2_intermed_2;
R_D_PC31DOWNTO2_intermed_4 <= R_D_PC31DOWNTO2_intermed_3;
R_D_PC31DOWNTO2_intermed_5 <= R_D_PC31DOWNTO2_intermed_4;
R_M_CTRL_PC31DOWNTO2_intermed_1 <= R.M.CTRL.PC ( 31 DOWNTO 2 );
RIN_E_CTRL_PC31DOWNTO2_intermed_1 <= RIN.E.CTRL.PC( 31 DOWNTO 2 );
RIN_E_CTRL_PC31DOWNTO2_intermed_2 <= RIN_E_CTRL_PC31DOWNTO2_intermed_1;
RIN_E_CTRL_PC31DOWNTO2_intermed_3 <= RIN_E_CTRL_PC31DOWNTO2_intermed_2;
RIN_E_CTRL_PC31DOWNTO2_intermed_4 <= RIN_E_CTRL_PC31DOWNTO2_intermed_3;
V_X_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_X_CTRL_PC31DOWNTO2_shadow;
V_X_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_X_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_E_CTRL_PC31DOWNTO2_shadow;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_2;
V_X_ANNUL_ALL_shadow_intermed_1 <= V_X_ANNUL_ALL_shadow;
V_X_ANNUL_ALL_shadow_intermed_2 <= V_X_ANNUL_ALL_shadow_intermed_1;
V_X_ANNUL_ALL_shadow_intermed_3 <= V_X_ANNUL_ALL_shadow_intermed_2;
V_X_ANNUL_ALL_shadow_intermed_4 <= V_X_ANNUL_ALL_shadow_intermed_3;
RIN_A_CTRL_ANNUL_intermed_1 <= RIN.A.CTRL.ANNUL;
RIN_A_CTRL_ANNUL_intermed_2 <= RIN_A_CTRL_ANNUL_intermed_1;
RIN_A_CTRL_ANNUL_intermed_3 <= RIN_A_CTRL_ANNUL_intermed_2;
RIN_A_CTRL_ANNUL_intermed_4 <= RIN_A_CTRL_ANNUL_intermed_3;
RIN_A_CTRL_ANNUL_intermed_5 <= RIN_A_CTRL_ANNUL_intermed_4;
R_M_CTRL_WREG_intermed_1 <= R.M.CTRL.WREG;
R_A_CTRL_ANNUL_intermed_1 <= R.A.CTRL.ANNUL;
R_A_CTRL_ANNUL_intermed_2 <= R_A_CTRL_ANNUL_intermed_1;
R_A_CTRL_ANNUL_intermed_3 <= R_A_CTRL_ANNUL_intermed_2;
R_A_CTRL_ANNUL_intermed_4 <= R_A_CTRL_ANNUL_intermed_3;
RIN_X_ANNUL_ALL_intermed_1 <= RIN.X.ANNUL_ALL;
RIN_X_ANNUL_ALL_intermed_2 <= RIN_X_ANNUL_ALL_intermed_1;
RIN_X_ANNUL_ALL_intermed_3 <= RIN_X_ANNUL_ALL_intermed_2;
RIN_X_ANNUL_ALL_intermed_4 <= RIN_X_ANNUL_ALL_intermed_3;
RIN_X_ANNUL_ALL_intermed_5 <= RIN_X_ANNUL_ALL_intermed_4;
V_M_CTRL_WREG_shadow_intermed_1 <= V_M_CTRL_WREG_shadow;
V_M_CTRL_WREG_shadow_intermed_2 <= V_M_CTRL_WREG_shadow_intermed_1;
R_X_ANNUL_ALL_intermed_1 <= R.X.ANNUL_ALL;
R_X_ANNUL_ALL_intermed_2 <= R_X_ANNUL_ALL_intermed_1;
R_X_ANNUL_ALL_intermed_3 <= R_X_ANNUL_ALL_intermed_2;
R_X_ANNUL_ALL_intermed_4 <= R_X_ANNUL_ALL_intermed_3;
V_X_CTRL_WREG_shadow_intermed_1 <= V_X_CTRL_WREG_shadow;
R_E_CTRL_WREG_intermed_1 <= R.E.CTRL.WREG;
R_E_CTRL_WREG_intermed_2 <= R_E_CTRL_WREG_intermed_1;
RIN_X_CTRL_WREG_intermed_1 <= RIN.X.CTRL.WREG;
V_A_CTRL_ANNUL_shadow_intermed_1 <= V_A_CTRL_ANNUL_shadow;
V_A_CTRL_ANNUL_shadow_intermed_2 <= V_A_CTRL_ANNUL_shadow_intermed_1;
V_A_CTRL_ANNUL_shadow_intermed_3 <= V_A_CTRL_ANNUL_shadow_intermed_2;
V_A_CTRL_ANNUL_shadow_intermed_4 <= V_A_CTRL_ANNUL_shadow_intermed_3;
RIN_E_CTRL_WREG_intermed_1 <= RIN.E.CTRL.WREG;
RIN_E_CTRL_WREG_intermed_2 <= RIN_E_CTRL_WREG_intermed_1;
RIN_E_CTRL_WREG_intermed_3 <= RIN_E_CTRL_WREG_intermed_2;
RIN_M_CTRL_WREG_intermed_1 <= RIN.M.CTRL.WREG;
RIN_M_CTRL_WREG_intermed_2 <= RIN_M_CTRL_WREG_intermed_1;
V_E_CTRL_WREG_shadow_intermed_1 <= V_E_CTRL_WREG_shadow;
V_E_CTRL_WREG_shadow_intermed_2 <= V_E_CTRL_WREG_shadow_intermed_1;
V_E_CTRL_WREG_shadow_intermed_3 <= V_E_CTRL_WREG_shadow_intermed_2;
RIN_A_CTRL_WREG_intermed_1 <= RIN.A.CTRL.WREG;
RIN_A_CTRL_WREG_intermed_2 <= RIN_A_CTRL_WREG_intermed_1;
RIN_A_CTRL_WREG_intermed_3 <= RIN_A_CTRL_WREG_intermed_2;
RIN_A_CTRL_WREG_intermed_4 <= RIN_A_CTRL_WREG_intermed_3;
V_A_CTRL_WREG_shadow_intermed_1 <= V_A_CTRL_WREG_shadow;
V_A_CTRL_WREG_shadow_intermed_2 <= V_A_CTRL_WREG_shadow_intermed_1;
V_A_CTRL_WREG_shadow_intermed_3 <= V_A_CTRL_WREG_shadow_intermed_2;
V_A_CTRL_WREG_shadow_intermed_4 <= V_A_CTRL_WREG_shadow_intermed_3;
R_A_CTRL_WREG_intermed_1 <= R.A.CTRL.WREG;
R_A_CTRL_WREG_intermed_2 <= R_A_CTRL_WREG_intermed_1;
R_A_CTRL_WREG_intermed_3 <= R_A_CTRL_WREG_intermed_2;
RIN_X_INTACK_intermed_1 <= RIN.X.INTACK;
V_X_INTACK_shadow_intermed_1 <= V_X_INTACK_shadow;
V_X_CTRL_TT3DOWNTO0_shadow_intermed_1 <= V_X_CTRL_TT3DOWNTO0_shadow;
V_X_CTRL_TT3DOWNTO0_shadow_intermed_2 <= V_X_CTRL_TT3DOWNTO0_shadow_intermed_1;
V_X_CTRL_TT3DOWNTO0_shadow_intermed_3 <= V_X_CTRL_TT3DOWNTO0_shadow_intermed_2;
R_M_CTRL_TT3DOWNTO0_intermed_1 <= R.M.CTRL.TT( 3 DOWNTO 0 );
R_M_CTRL_TT3DOWNTO0_intermed_2 <= R_M_CTRL_TT3DOWNTO0_intermed_1;
R_M_CTRL_TT3DOWNTO0_intermed_3 <= R_M_CTRL_TT3DOWNTO0_intermed_2;
V_M_CTRL_TT3DOWNTO0_shadow_intermed_1 <= V_M_CTRL_TT3DOWNTO0_shadow;
V_M_CTRL_TT3DOWNTO0_shadow_intermed_2 <= V_M_CTRL_TT3DOWNTO0_shadow_intermed_1;
V_M_CTRL_TT3DOWNTO0_shadow_intermed_3 <= V_M_CTRL_TT3DOWNTO0_shadow_intermed_2;
V_M_CTRL_TT3DOWNTO0_shadow_intermed_4 <= V_M_CTRL_TT3DOWNTO0_shadow_intermed_3;
V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_1 <= V_X_RESULT6DOWNTO03DOWNTO0_shadow;
V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_2 <= V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_1;
V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_3 <= V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_2;
V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_4 <= V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_3;
R_X_RESULT6DOWNTO03DOWNTO0_intermed_1 <= R.X.RESULT( 6 DOWNTO 0 )( 3 DOWNTO 0 );
R_X_RESULT6DOWNTO03DOWNTO0_intermed_2 <= R_X_RESULT6DOWNTO03DOWNTO0_intermed_1;
R_X_RESULT6DOWNTO03DOWNTO0_intermed_3 <= R_X_RESULT6DOWNTO03DOWNTO0_intermed_2;
R_A_CTRL_TT3DOWNTO0_intermed_1 <= R.A.CTRL.TT( 3 DOWNTO 0 );
R_A_CTRL_TT3DOWNTO0_intermed_2 <= R_A_CTRL_TT3DOWNTO0_intermed_1;
R_A_CTRL_TT3DOWNTO0_intermed_3 <= R_A_CTRL_TT3DOWNTO0_intermed_2;
R_A_CTRL_TT3DOWNTO0_intermed_4 <= R_A_CTRL_TT3DOWNTO0_intermed_3;
R_A_CTRL_TT3DOWNTO0_intermed_5 <= R_A_CTRL_TT3DOWNTO0_intermed_4;
RIN_A_CTRL_TT3DOWNTO0_intermed_1 <= RIN.A.CTRL.TT( 3 DOWNTO 0 );
RIN_A_CTRL_TT3DOWNTO0_intermed_2 <= RIN_A_CTRL_TT3DOWNTO0_intermed_1;
RIN_A_CTRL_TT3DOWNTO0_intermed_3 <= RIN_A_CTRL_TT3DOWNTO0_intermed_2;
RIN_A_CTRL_TT3DOWNTO0_intermed_4 <= RIN_A_CTRL_TT3DOWNTO0_intermed_3;
RIN_A_CTRL_TT3DOWNTO0_intermed_5 <= RIN_A_CTRL_TT3DOWNTO0_intermed_4;
RIN_A_CTRL_TT3DOWNTO0_intermed_6 <= RIN_A_CTRL_TT3DOWNTO0_intermed_5;
RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_1 <= RIN.X.RESULT( 6 DOWNTO 0 )( 3 DOWNTO 0 );
RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_2 <= RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_1;
RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_3 <= RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_2;
RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_4 <= RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_3;
V_A_CTRL_TT3DOWNTO0_shadow_intermed_1 <= V_A_CTRL_TT3DOWNTO0_shadow;
V_A_CTRL_TT3DOWNTO0_shadow_intermed_2 <= V_A_CTRL_TT3DOWNTO0_shadow_intermed_1;
V_A_CTRL_TT3DOWNTO0_shadow_intermed_3 <= V_A_CTRL_TT3DOWNTO0_shadow_intermed_2;
V_A_CTRL_TT3DOWNTO0_shadow_intermed_4 <= V_A_CTRL_TT3DOWNTO0_shadow_intermed_3;
V_A_CTRL_TT3DOWNTO0_shadow_intermed_5 <= V_A_CTRL_TT3DOWNTO0_shadow_intermed_4;
V_A_CTRL_TT3DOWNTO0_shadow_intermed_6 <= V_A_CTRL_TT3DOWNTO0_shadow_intermed_5;
RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_1 <= RIN.X.RESULT ( 6 DOWNTO 0 )( 3 DOWNTO 0 );
RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_2 <= RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_1;
RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_3 <= RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_2;
R_W_S_TT3DOWNTO0_intermed_1 <= R.W.S.TT( 3 DOWNTO 0 );
R_W_S_TT3DOWNTO0_intermed_2 <= R_W_S_TT3DOWNTO0_intermed_1;
R_X_RESULT6DOWNTO03DOWNTO0_intermed_1 <= R.X.RESULT ( 6 DOWNTO 0 )( 3 DOWNTO 0 );
R_X_RESULT6DOWNTO03DOWNTO0_intermed_2 <= R_X_RESULT6DOWNTO03DOWNTO0_intermed_1;
R_E_CTRL_TT3DOWNTO0_intermed_1 <= R.E.CTRL.TT( 3 DOWNTO 0 );
R_E_CTRL_TT3DOWNTO0_intermed_2 <= R_E_CTRL_TT3DOWNTO0_intermed_1;
R_E_CTRL_TT3DOWNTO0_intermed_3 <= R_E_CTRL_TT3DOWNTO0_intermed_2;
R_E_CTRL_TT3DOWNTO0_intermed_4 <= R_E_CTRL_TT3DOWNTO0_intermed_3;
V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_1 <= V_X_RESULT6DOWNTO03DOWNTO0_shadow;
V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_2 <= V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_1;
V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_3 <= V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_2;
RIN_W_S_TT3DOWNTO0_intermed_1 <= RIN.W.S.TT( 3 DOWNTO 0 );
RIN_W_S_TT3DOWNTO0_intermed_2 <= RIN_W_S_TT3DOWNTO0_intermed_1;
V_E_CTRL_TT3DOWNTO0_shadow_intermed_1 <= V_E_CTRL_TT3DOWNTO0_shadow;
V_E_CTRL_TT3DOWNTO0_shadow_intermed_2 <= V_E_CTRL_TT3DOWNTO0_shadow_intermed_1;
V_E_CTRL_TT3DOWNTO0_shadow_intermed_3 <= V_E_CTRL_TT3DOWNTO0_shadow_intermed_2;
V_E_CTRL_TT3DOWNTO0_shadow_intermed_4 <= V_E_CTRL_TT3DOWNTO0_shadow_intermed_3;
V_E_CTRL_TT3DOWNTO0_shadow_intermed_5 <= V_E_CTRL_TT3DOWNTO0_shadow_intermed_4;
RIN_W_S_TT3DOWNTO0_intermed_1 <= RIN.W.S.TT ( 3 DOWNTO 0 );
RIN_M_CTRL_TT3DOWNTO0_intermed_1 <= RIN.M.CTRL.TT( 3 DOWNTO 0 );
RIN_M_CTRL_TT3DOWNTO0_intermed_2 <= RIN_M_CTRL_TT3DOWNTO0_intermed_1;
RIN_M_CTRL_TT3DOWNTO0_intermed_3 <= RIN_M_CTRL_TT3DOWNTO0_intermed_2;
RIN_M_CTRL_TT3DOWNTO0_intermed_4 <= RIN_M_CTRL_TT3DOWNTO0_intermed_3;
RIN_X_CTRL_TT3DOWNTO0_intermed_1 <= RIN.X.CTRL.TT( 3 DOWNTO 0 );
RIN_X_CTRL_TT3DOWNTO0_intermed_2 <= RIN_X_CTRL_TT3DOWNTO0_intermed_1;
RIN_X_CTRL_TT3DOWNTO0_intermed_3 <= RIN_X_CTRL_TT3DOWNTO0_intermed_2;
V_W_S_TT3DOWNTO0_shadow_intermed_1 <= V_W_S_TT3DOWNTO0_shadow;
V_W_S_TT3DOWNTO0_shadow_intermed_2 <= V_W_S_TT3DOWNTO0_shadow_intermed_1;
R_X_CTRL_TT3DOWNTO0_intermed_1 <= R.X.CTRL.TT( 3 DOWNTO 0 );
R_X_CTRL_TT3DOWNTO0_intermed_2 <= R_X_CTRL_TT3DOWNTO0_intermed_1;
RIN_E_CTRL_TT3DOWNTO0_intermed_1 <= RIN.E.CTRL.TT( 3 DOWNTO 0 );
RIN_E_CTRL_TT3DOWNTO0_intermed_2 <= RIN_E_CTRL_TT3DOWNTO0_intermed_1;
RIN_E_CTRL_TT3DOWNTO0_intermed_3 <= RIN_E_CTRL_TT3DOWNTO0_intermed_2;
RIN_E_CTRL_TT3DOWNTO0_intermed_4 <= RIN_E_CTRL_TT3DOWNTO0_intermed_3;
RIN_E_CTRL_TT3DOWNTO0_intermed_5 <= RIN_E_CTRL_TT3DOWNTO0_intermed_4;
V_W_S_TT3DOWNTO0_shadow_intermed_1 <= V_W_S_TT3DOWNTO0_shadow;
XC_VECTT3DOWNTO0_shadow_intermed_1 <= XC_VECTT3DOWNTO0_shadow;
XC_VECTT3DOWNTO0_shadow_intermed_2 <= XC_VECTT3DOWNTO0_shadow_intermed_1;
RIN_X_INTACK_intermed_1 <= RIN.X.INTACK;
V_X_INTACK_shadow_intermed_1 <= V_X_INTACK_shadow;
V_M_RESULT1DOWNTO0_shadow_intermed_1 <= V_M_RESULT1DOWNTO0_shadow;
V_M_RESULT1DOWNTO0_shadow_intermed_2 <= V_M_RESULT1DOWNTO0_shadow_intermed_1;
RIN_M_RESULT1DOWNTO0_intermed_1 <= RIN.M.RESULT ( 1 DOWNTO 0 );
RIN_M_RESULT1DOWNTO0_intermed_1 <= RIN.M.RESULT( 1 DOWNTO 0 );
RIN_M_RESULT1DOWNTO0_intermed_2 <= RIN_M_RESULT1DOWNTO0_intermed_1;
V_M_RESULT1DOWNTO0_shadow_intermed_1 <= V_M_RESULT1DOWNTO0_shadow;
R_M_RESULT1DOWNTO0_intermed_1 <= R.M.RESULT( 1 DOWNTO 0 );
R_M_RESULT1DOWNTO0_intermed_2 <= R_M_RESULT1DOWNTO0_intermed_1;
V_X_ANNUL_ALL_shadow_intermed_1 <= V_X_ANNUL_ALL_shadow;
RIN_A_CTRL_ANNUL_intermed_1 <= RIN.A.CTRL.ANNUL;
RIN_A_CTRL_ANNUL_intermed_2 <= RIN_A_CTRL_ANNUL_intermed_1;
RIN_A_CTRL_ANNUL_intermed_3 <= RIN_A_CTRL_ANNUL_intermed_2;
RIN_E_CTRL_ANNUL_intermed_1 <= RIN.E.CTRL.ANNUL;
RIN_E_CTRL_ANNUL_intermed_2 <= RIN_E_CTRL_ANNUL_intermed_1;
R_A_CTRL_ANNUL_intermed_1 <= R.A.CTRL.ANNUL;
R_A_CTRL_ANNUL_intermed_2 <= R_A_CTRL_ANNUL_intermed_1;
V_M_CTRL_ANNUL_shadow_intermed_1 <= V_M_CTRL_ANNUL_shadow;
RIN_X_ANNUL_ALL_intermed_1 <= RIN.X.ANNUL_ALL;
RIN_X_ANNUL_ALL_intermed_2 <= RIN_X_ANNUL_ALL_intermed_1;
R_X_ANNUL_ALL_intermed_1 <= R.X.ANNUL_ALL;
RIN_M_DCI_LOCK_intermed_1 <= RIN.M.DCI.LOCK;
V_E_CTRL_ANNUL_shadow_intermed_1 <= V_E_CTRL_ANNUL_shadow;
V_E_CTRL_ANNUL_shadow_intermed_2 <= V_E_CTRL_ANNUL_shadow_intermed_1;
V_A_CTRL_ANNUL_shadow_intermed_1 <= V_A_CTRL_ANNUL_shadow;
V_A_CTRL_ANNUL_shadow_intermed_2 <= V_A_CTRL_ANNUL_shadow_intermed_1;
V_A_CTRL_ANNUL_shadow_intermed_3 <= V_A_CTRL_ANNUL_shadow_intermed_2;
RIN_M_CTRL_ANNUL_intermed_1 <= RIN.M.CTRL.ANNUL;
R_E_CTRL_ANNUL_intermed_1 <= R.E.CTRL.ANNUL;
V_M_DCI_LOCK_shadow_intermed_1 <= V_M_DCI_LOCK_shadow;
RIN_X_DATA031_intermed_1 <= RIN.X.DATA ( 0 )( 31 );
RIN_X_DATA031_intermed_2 <= RIN_X_DATA031_intermed_1;
V_X_DATA031_shadow_intermed_1 <= V_X_DATA031_shadow;
V_X_DATA031_shadow_intermed_2 <= V_X_DATA031_shadow_intermed_1;
V_X_DATA031_shadow_intermed_1 <= V_X_DATA031_shadow;
V_X_DATA031_shadow_intermed_2 <= V_X_DATA031_shadow_intermed_1;
RIN_X_DATA031_intermed_1 <= RIN.X.DATA( 0 )( 31 );
RIN_X_DATA031_intermed_2 <= RIN_X_DATA031_intermed_1;
RIN_X_DATA031_intermed_1 <= RIN.X.DATA ( 0 ) ( 31 );
R_X_DATA031_intermed_1 <= R.X.DATA( 0 )( 31 );
R_X_DATA031_intermed_2 <= R_X_DATA031_intermed_1;
R_X_DATA031_intermed_1 <= R.X.DATA ( 0 )( 31 );
R_X_DATA031_intermed_2 <= R_X_DATA031_intermed_1;
V_X_DATA031_shadow_intermed_1 <= V_X_DATA031_shadow;
DE_INST19_shadow_intermed_1 <= DE_INST19_shadow;
DE_INST19_shadow_intermed_2 <= DE_INST19_shadow_intermed_1;
DE_INST19_shadow_intermed_3 <= DE_INST19_shadow_intermed_2;
R_D_INST019_intermed_1 <= R.D.INST ( 0 )( 19 );
R_D_INST019_intermed_2 <= R_D_INST019_intermed_1;
R_D_INST019_intermed_3 <= R_D_INST019_intermed_2;
RIN_D_INST019_intermed_1 <= RIN.D.INST ( 0 )( 19 );
RIN_D_INST019_intermed_2 <= RIN_D_INST019_intermed_1;
RIN_D_INST019_intermed_3 <= RIN_D_INST019_intermed_2;
RIN_D_INST019_intermed_4 <= RIN_D_INST019_intermed_3;
V_A_CTRL_INST19_shadow_intermed_1 <= V_A_CTRL_INST19_shadow;
V_A_CTRL_INST19_shadow_intermed_2 <= V_A_CTRL_INST19_shadow_intermed_1;
V_A_CTRL_INST19_shadow_intermed_3 <= V_A_CTRL_INST19_shadow_intermed_2;
V_E_CTRL_INST19_shadow_intermed_1 <= V_E_CTRL_INST19_shadow;
R_D_INST019_intermed_1 <= R.D.INST( 0 )( 19 );
R_D_INST019_intermed_2 <= R_D_INST019_intermed_1;
R_D_INST019_intermed_3 <= R_D_INST019_intermed_2;
R_D_INST019_intermed_4 <= R_D_INST019_intermed_3;
V_E_CTRL_INST19_shadow_intermed_1 <= V_E_CTRL_INST19_shadow;
V_E_CTRL_INST19_shadow_intermed_2 <= V_E_CTRL_INST19_shadow_intermed_1;
V_D_INST019_shadow_intermed_1 <= V_D_INST019_shadow;
V_D_INST019_shadow_intermed_2 <= V_D_INST019_shadow_intermed_1;
V_D_INST019_shadow_intermed_3 <= V_D_INST019_shadow_intermed_2;
V_D_INST019_shadow_intermed_4 <= V_D_INST019_shadow_intermed_3;
R_E_CTRL_INST19_intermed_1 <= R.E.CTRL.INST( 19 );
R_E_CTRL_INST19_intermed_2 <= R_E_CTRL_INST19_intermed_1;
RIN_A_CTRL_INST19_intermed_1 <= RIN.A.CTRL.INST ( 19 );
RIN_A_CTRL_INST19_intermed_2 <= RIN_A_CTRL_INST19_intermed_1;
R_A_CTRL_INST19_intermed_1 <= R.A.CTRL.INST( 19 );
R_A_CTRL_INST19_intermed_2 <= R_A_CTRL_INST19_intermed_1;
V_D_INST019_shadow_intermed_1 <= V_D_INST019_shadow;
V_D_INST019_shadow_intermed_2 <= V_D_INST019_shadow_intermed_1;
V_D_INST019_shadow_intermed_3 <= V_D_INST019_shadow_intermed_2;
V_D_INST019_shadow_intermed_4 <= V_D_INST019_shadow_intermed_3;
V_D_INST019_shadow_intermed_5 <= V_D_INST019_shadow_intermed_4;
RIN_D_INST019_intermed_1 <= RIN.D.INST( 0 )( 19 );
RIN_D_INST019_intermed_2 <= RIN_D_INST019_intermed_1;
RIN_D_INST019_intermed_3 <= RIN_D_INST019_intermed_2;
RIN_D_INST019_intermed_4 <= RIN_D_INST019_intermed_3;
RIN_D_INST019_intermed_5 <= RIN_D_INST019_intermed_4;
R_A_CTRL_INST19_intermed_1 <= R.A.CTRL.INST ( 19 );
RIN_A_CTRL_INST19_intermed_1 <= RIN.A.CTRL.INST( 19 );
RIN_A_CTRL_INST19_intermed_2 <= RIN_A_CTRL_INST19_intermed_1;
RIN_A_CTRL_INST19_intermed_3 <= RIN_A_CTRL_INST19_intermed_2;
RIN_E_CTRL_INST19_intermed_1 <= RIN.E.CTRL.INST ( 19 );
RIN_E_CTRL_INST19_intermed_1 <= RIN.E.CTRL.INST( 19 );
RIN_E_CTRL_INST19_intermed_2 <= RIN_E_CTRL_INST19_intermed_1;
V_A_CTRL_INST19_shadow_intermed_1 <= V_A_CTRL_INST19_shadow;
V_A_CTRL_INST19_shadow_intermed_2 <= V_A_CTRL_INST19_shadow_intermed_1;
V_A_CTRL_INST20_shadow_intermed_1 <= V_A_CTRL_INST20_shadow;
V_A_CTRL_INST20_shadow_intermed_2 <= V_A_CTRL_INST20_shadow_intermed_1;
R_D_INST020_intermed_1 <= R.D.INST ( 0 )( 20 );
R_D_INST020_intermed_2 <= R_D_INST020_intermed_1;
R_D_INST020_intermed_3 <= R_D_INST020_intermed_2;
RIN_D_INST020_intermed_1 <= RIN.D.INST( 0 )( 20 );
RIN_D_INST020_intermed_2 <= RIN_D_INST020_intermed_1;
RIN_D_INST020_intermed_3 <= RIN_D_INST020_intermed_2;
RIN_D_INST020_intermed_4 <= RIN_D_INST020_intermed_3;
RIN_D_INST020_intermed_5 <= RIN_D_INST020_intermed_4;
RIN_A_CTRL_INST20_intermed_1 <= RIN.A.CTRL.INST ( 20 );
RIN_A_CTRL_INST20_intermed_2 <= RIN_A_CTRL_INST20_intermed_1;
V_D_INST020_shadow_intermed_1 <= V_D_INST020_shadow;
V_D_INST020_shadow_intermed_2 <= V_D_INST020_shadow_intermed_1;
V_D_INST020_shadow_intermed_3 <= V_D_INST020_shadow_intermed_2;
V_D_INST020_shadow_intermed_4 <= V_D_INST020_shadow_intermed_3;
RIN_E_CTRL_INST20_intermed_1 <= RIN.E.CTRL.INST ( 20 );
RIN_D_INST020_intermed_1 <= RIN.D.INST ( 0 )( 20 );
RIN_D_INST020_intermed_2 <= RIN_D_INST020_intermed_1;
RIN_D_INST020_intermed_3 <= RIN_D_INST020_intermed_2;
RIN_D_INST020_intermed_4 <= RIN_D_INST020_intermed_3;
R_A_CTRL_INST20_intermed_1 <= R.A.CTRL.INST ( 20 );
R_E_CTRL_INST20_intermed_1 <= R.E.CTRL.INST( 20 );
R_E_CTRL_INST20_intermed_2 <= R_E_CTRL_INST20_intermed_1;
RIN_A_CTRL_INST20_intermed_1 <= RIN.A.CTRL.INST( 20 );
RIN_A_CTRL_INST20_intermed_2 <= RIN_A_CTRL_INST20_intermed_1;
RIN_A_CTRL_INST20_intermed_3 <= RIN_A_CTRL_INST20_intermed_2;
V_D_INST020_shadow_intermed_1 <= V_D_INST020_shadow;
V_D_INST020_shadow_intermed_2 <= V_D_INST020_shadow_intermed_1;
V_D_INST020_shadow_intermed_3 <= V_D_INST020_shadow_intermed_2;
V_D_INST020_shadow_intermed_4 <= V_D_INST020_shadow_intermed_3;
V_D_INST020_shadow_intermed_5 <= V_D_INST020_shadow_intermed_4;
R_D_INST020_intermed_1 <= R.D.INST( 0 )( 20 );
R_D_INST020_intermed_2 <= R_D_INST020_intermed_1;
R_D_INST020_intermed_3 <= R_D_INST020_intermed_2;
R_D_INST020_intermed_4 <= R_D_INST020_intermed_3;
V_E_CTRL_INST20_shadow_intermed_1 <= V_E_CTRL_INST20_shadow;
V_E_CTRL_INST20_shadow_intermed_2 <= V_E_CTRL_INST20_shadow_intermed_1;
V_E_CTRL_INST20_shadow_intermed_1 <= V_E_CTRL_INST20_shadow;
DE_INST20_shadow_intermed_1 <= DE_INST20_shadow;
DE_INST20_shadow_intermed_2 <= DE_INST20_shadow_intermed_1;
DE_INST20_shadow_intermed_3 <= DE_INST20_shadow_intermed_2;
V_A_CTRL_INST20_shadow_intermed_1 <= V_A_CTRL_INST20_shadow;
V_A_CTRL_INST20_shadow_intermed_2 <= V_A_CTRL_INST20_shadow_intermed_1;
V_A_CTRL_INST20_shadow_intermed_3 <= V_A_CTRL_INST20_shadow_intermed_2;
RIN_E_CTRL_INST20_intermed_1 <= RIN.E.CTRL.INST( 20 );
RIN_E_CTRL_INST20_intermed_2 <= RIN_E_CTRL_INST20_intermed_1;
R_A_CTRL_INST20_intermed_1 <= R.A.CTRL.INST( 20 );
R_A_CTRL_INST20_intermed_2 <= R_A_CTRL_INST20_intermed_1;
RIN_X_DATA00_intermed_1 <= RIN.X.DATA ( 0 )( 0 );
RIN_X_DATA00_intermed_2 <= RIN_X_DATA00_intermed_1;
V_X_DATA00_shadow_intermed_1 <= V_X_DATA00_shadow;
V_X_DATA00_shadow_intermed_1 <= V_X_DATA00_shadow;
V_X_DATA00_shadow_intermed_2 <= V_X_DATA00_shadow_intermed_1;
RIN_X_DATA00_intermed_1 <= RIN.X.DATA ( 0 ) ( 0 );
V_X_DATA00_shadow_intermed_1 <= V_X_DATA00_shadow;
V_X_DATA00_shadow_intermed_2 <= V_X_DATA00_shadow_intermed_1;
R_X_DATA00_intermed_1 <= R.X.DATA ( 0 )( 0 );
R_X_DATA00_intermed_2 <= R_X_DATA00_intermed_1;
RIN_X_DATA00_intermed_1 <= RIN.X.DATA( 0 )( 0 );
RIN_X_DATA00_intermed_2 <= RIN_X_DATA00_intermed_1;
R_X_DATA00_intermed_1 <= R.X.DATA( 0 )( 0 );
R_X_DATA00_intermed_2 <= R_X_DATA00_intermed_1;
RIN_X_DATA04DOWNTO0_intermed_1 <= RIN.X.DATA ( 0 ) ( 4 DOWNTO 0 );
V_X_DATA04DOWNTO0_shadow_intermed_1 <= V_X_DATA04DOWNTO0_shadow;
V_X_DATA04DOWNTO0_shadow_intermed_2 <= V_X_DATA04DOWNTO0_shadow_intermed_1;
R_X_DATA04DOWNTO0_intermed_1 <= R.X.DATA( 0 )( 4 DOWNTO 0 );
R_X_DATA04DOWNTO0_intermed_2 <= R_X_DATA04DOWNTO0_intermed_1;
R_X_DATA04DOWNTO0_intermed_1 <= R.X.DATA ( 0 )( 4 DOWNTO 0 );
R_X_DATA04DOWNTO0_intermed_2 <= R_X_DATA04DOWNTO0_intermed_1;
V_X_DATA04DOWNTO0_shadow_intermed_1 <= V_X_DATA04DOWNTO0_shadow;
RIN_X_DATA04DOWNTO0_intermed_1 <= RIN.X.DATA ( 0 )( 4 DOWNTO 0 );
RIN_X_DATA04DOWNTO0_intermed_2 <= RIN_X_DATA04DOWNTO0_intermed_1;
RIN_X_DATA04DOWNTO0_intermed_1 <= RIN.X.DATA( 0 )( 4 DOWNTO 0 );
RIN_X_DATA04DOWNTO0_intermed_2 <= RIN_X_DATA04DOWNTO0_intermed_1;
V_X_DATA04DOWNTO0_shadow_intermed_1 <= V_X_DATA04DOWNTO0_shadow;
V_X_DATA04DOWNTO0_shadow_intermed_2 <= V_X_DATA04DOWNTO0_shadow_intermed_1;
RIN_D_INST0_intermed_1 <= RIN.D.INST ( 0 );
V_D_INST0_shadow_intermed_1 <= V_D_INST0_shadow;
V_D_INST0_shadow_intermed_2 <= V_D_INST0_shadow_intermed_1;
R_D_INST0_intermed_1 <= R.D.INST( 0 );
R_D_INST0_intermed_2 <= R_D_INST0_intermed_1;
RIN_D_INST0_intermed_1 <= RIN.D.INST( 0 );
RIN_D_INST0_intermed_2 <= RIN_D_INST0_intermed_1;
V_D_INST0_shadow_intermed_1 <= V_D_INST0_shadow;
RIN_A_RFE1_intermed_1 <= RIN.A.RFE1;
V_A_RFE1_shadow_intermed_1 <= V_A_RFE1_shadow;
RIN_A_RFE2_intermed_1 <= RIN.A.RFE2;
V_A_RFE2_shadow_intermed_1 <= V_A_RFE2_shadow;
R_M_CTRL_PC31DOWNTO2_intermed_1 <= R.M.CTRL.PC( 31 DOWNTO 2 );
R_M_CTRL_PC31DOWNTO2_intermed_2 <= R_M_CTRL_PC31DOWNTO2_intermed_1;
R_M_CTRL_PC31DOWNTO2_intermed_3 <= R_M_CTRL_PC31DOWNTO2_intermed_2;
R_M_CTRL_PC31DOWNTO2_intermed_4 <= R_M_CTRL_PC31DOWNTO2_intermed_3;
RIN_M_CTRL_PC31DOWNTO2_intermed_1 <= RIN.M.CTRL.PC( 31 DOWNTO 2 );
RIN_M_CTRL_PC31DOWNTO2_intermed_2 <= RIN_M_CTRL_PC31DOWNTO2_intermed_1;
RIN_M_CTRL_PC31DOWNTO2_intermed_3 <= RIN_M_CTRL_PC31DOWNTO2_intermed_2;
RIN_M_CTRL_PC31DOWNTO2_intermed_4 <= RIN_M_CTRL_PC31DOWNTO2_intermed_3;
RIN_M_CTRL_PC31DOWNTO2_intermed_5 <= RIN_M_CTRL_PC31DOWNTO2_intermed_4;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_E_CTRL_PC31DOWNTO2_shadow;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_2;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_4 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_3;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_5 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_4;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_6 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_5;
RIN_A_CTRL_PC31DOWNTO2_intermed_1 <= RIN.A.CTRL.PC( 31 DOWNTO 2 );
RIN_A_CTRL_PC31DOWNTO2_intermed_2 <= RIN_A_CTRL_PC31DOWNTO2_intermed_1;
RIN_A_CTRL_PC31DOWNTO2_intermed_3 <= RIN_A_CTRL_PC31DOWNTO2_intermed_2;
RIN_A_CTRL_PC31DOWNTO2_intermed_4 <= RIN_A_CTRL_PC31DOWNTO2_intermed_3;
RIN_A_CTRL_PC31DOWNTO2_intermed_5 <= RIN_A_CTRL_PC31DOWNTO2_intermed_4;
RIN_A_CTRL_PC31DOWNTO2_intermed_6 <= RIN_A_CTRL_PC31DOWNTO2_intermed_5;
RIN_A_CTRL_PC31DOWNTO2_intermed_7 <= RIN_A_CTRL_PC31DOWNTO2_intermed_6;
R_A_CTRL_PC31DOWNTO2_intermed_1 <= R.A.CTRL.PC( 31 DOWNTO 2 );
R_A_CTRL_PC31DOWNTO2_intermed_2 <= R_A_CTRL_PC31DOWNTO2_intermed_1;
R_A_CTRL_PC31DOWNTO2_intermed_3 <= R_A_CTRL_PC31DOWNTO2_intermed_2;
R_A_CTRL_PC31DOWNTO2_intermed_4 <= R_A_CTRL_PC31DOWNTO2_intermed_3;
R_A_CTRL_PC31DOWNTO2_intermed_5 <= R_A_CTRL_PC31DOWNTO2_intermed_4;
R_A_CTRL_PC31DOWNTO2_intermed_6 <= R_A_CTRL_PC31DOWNTO2_intermed_5;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_M_CTRL_PC31DOWNTO2_shadow;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_M_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_M_CTRL_PC31DOWNTO2_shadow_intermed_2;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_4 <= V_M_CTRL_PC31DOWNTO2_shadow_intermed_3;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_5 <= V_M_CTRL_PC31DOWNTO2_shadow_intermed_4;
R_X_CTRL_PC31DOWNTO2_intermed_1 <= R.X.CTRL.PC( 31 DOWNTO 2 );
R_X_CTRL_PC31DOWNTO2_intermed_2 <= R_X_CTRL_PC31DOWNTO2_intermed_1;
R_X_CTRL_PC31DOWNTO2_intermed_3 <= R_X_CTRL_PC31DOWNTO2_intermed_2;
V_D_PC31DOWNTO2_shadow_intermed_1 <= V_D_PC31DOWNTO2_shadow;
V_D_PC31DOWNTO2_shadow_intermed_2 <= V_D_PC31DOWNTO2_shadow_intermed_1;
V_D_PC31DOWNTO2_shadow_intermed_3 <= V_D_PC31DOWNTO2_shadow_intermed_2;
V_D_PC31DOWNTO2_shadow_intermed_4 <= V_D_PC31DOWNTO2_shadow_intermed_3;
V_D_PC31DOWNTO2_shadow_intermed_5 <= V_D_PC31DOWNTO2_shadow_intermed_4;
V_D_PC31DOWNTO2_shadow_intermed_6 <= V_D_PC31DOWNTO2_shadow_intermed_5;
V_D_PC31DOWNTO2_shadow_intermed_7 <= V_D_PC31DOWNTO2_shadow_intermed_6;
V_D_PC31DOWNTO2_shadow_intermed_8 <= V_D_PC31DOWNTO2_shadow_intermed_7;
XC_TRAP_ADDRESS31DOWNTO2_shadow_intermed_1 <= XC_TRAP_ADDRESS31DOWNTO2_shadow;
XC_TRAP_ADDRESS31DOWNTO2_shadow_intermed_2 <= XC_TRAP_ADDRESS31DOWNTO2_shadow_intermed_1;
RIN_D_PC31DOWNTO2_intermed_1 <= RIN.D.PC( 31 DOWNTO 2 );
RIN_D_PC31DOWNTO2_intermed_2 <= RIN_D_PC31DOWNTO2_intermed_1;
RIN_D_PC31DOWNTO2_intermed_3 <= RIN_D_PC31DOWNTO2_intermed_2;
RIN_D_PC31DOWNTO2_intermed_4 <= RIN_D_PC31DOWNTO2_intermed_3;
RIN_D_PC31DOWNTO2_intermed_5 <= RIN_D_PC31DOWNTO2_intermed_4;
RIN_D_PC31DOWNTO2_intermed_6 <= RIN_D_PC31DOWNTO2_intermed_5;
RIN_D_PC31DOWNTO2_intermed_7 <= RIN_D_PC31DOWNTO2_intermed_6;
RIN_D_PC31DOWNTO2_intermed_8 <= RIN_D_PC31DOWNTO2_intermed_7;
EX_ADD_RES32DOWNTO332DOWNTO3_shadow_intermed_1 <= EX_ADD_RES32DOWNTO332DOWNTO3_shadow;
EX_ADD_RES32DOWNTO332DOWNTO3_shadow_intermed_2 <= EX_ADD_RES32DOWNTO332DOWNTO3_shadow_intermed_1;
V_F_PC31DOWNTO2_shadow_intermed_1 <= V_F_PC31DOWNTO2_shadow;
V_F_PC31DOWNTO2_shadow_intermed_2 <= V_F_PC31DOWNTO2_shadow_intermed_1;
V_F_PC31DOWNTO2_shadow_intermed_1 <= V_F_PC31DOWNTO2_shadow;
RIN_F_PC31DOWNTO2_intermed_1 <= RIN.F.PC( 31 DOWNTO 2 );
RIN_F_PC31DOWNTO2_intermed_2 <= RIN_F_PC31DOWNTO2_intermed_1;
RIN_X_CTRL_PC31DOWNTO2_intermed_1 <= RIN.X.CTRL.PC( 31 DOWNTO 2 );
RIN_X_CTRL_PC31DOWNTO2_intermed_2 <= RIN_X_CTRL_PC31DOWNTO2_intermed_1;
RIN_X_CTRL_PC31DOWNTO2_intermed_3 <= RIN_X_CTRL_PC31DOWNTO2_intermed_2;
RIN_X_CTRL_PC31DOWNTO2_intermed_4 <= RIN_X_CTRL_PC31DOWNTO2_intermed_3;
IRIN_ADDR31DOWNTO2_intermed_1 <= IRIN.ADDR( 31 DOWNTO 2 );
IRIN_ADDR31DOWNTO2_intermed_2 <= IRIN_ADDR31DOWNTO2_intermed_1;
IRIN_ADDR31DOWNTO2_intermed_3 <= IRIN_ADDR31DOWNTO2_intermed_2;
R_E_CTRL_PC31DOWNTO2_intermed_1 <= R.E.CTRL.PC( 31 DOWNTO 2 );
R_E_CTRL_PC31DOWNTO2_intermed_2 <= R_E_CTRL_PC31DOWNTO2_intermed_1;
R_E_CTRL_PC31DOWNTO2_intermed_3 <= R_E_CTRL_PC31DOWNTO2_intermed_2;
R_E_CTRL_PC31DOWNTO2_intermed_4 <= R_E_CTRL_PC31DOWNTO2_intermed_3;
R_E_CTRL_PC31DOWNTO2_intermed_5 <= R_E_CTRL_PC31DOWNTO2_intermed_4;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO2_shadow;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_2;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_4 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_3;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_5 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_4;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_6 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_5;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_7 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_6;
EX_JUMP_ADDRESS31DOWNTO2_shadow_intermed_1 <= EX_JUMP_ADDRESS31DOWNTO2_shadow;
EX_JUMP_ADDRESS31DOWNTO2_shadow_intermed_2 <= EX_JUMP_ADDRESS31DOWNTO2_shadow_intermed_1;
R_D_PC31DOWNTO2_intermed_1 <= R.D.PC( 31 DOWNTO 2 );
R_D_PC31DOWNTO2_intermed_2 <= R_D_PC31DOWNTO2_intermed_1;
R_D_PC31DOWNTO2_intermed_3 <= R_D_PC31DOWNTO2_intermed_2;
R_D_PC31DOWNTO2_intermed_4 <= R_D_PC31DOWNTO2_intermed_3;
R_D_PC31DOWNTO2_intermed_5 <= R_D_PC31DOWNTO2_intermed_4;
R_D_PC31DOWNTO2_intermed_6 <= R_D_PC31DOWNTO2_intermed_5;
R_D_PC31DOWNTO2_intermed_7 <= R_D_PC31DOWNTO2_intermed_6;
RIN_F_PC31DOWNTO2_intermed_1 <= RIN.F.PC ( 31 DOWNTO 2 );
IR_ADDR31DOWNTO2_intermed_1 <= IR.ADDR( 31 DOWNTO 2 );
IR_ADDR31DOWNTO2_intermed_2 <= IR_ADDR31DOWNTO2_intermed_1;
RIN_E_CTRL_PC31DOWNTO2_intermed_1 <= RIN.E.CTRL.PC( 31 DOWNTO 2 );
RIN_E_CTRL_PC31DOWNTO2_intermed_2 <= RIN_E_CTRL_PC31DOWNTO2_intermed_1;
RIN_E_CTRL_PC31DOWNTO2_intermed_3 <= RIN_E_CTRL_PC31DOWNTO2_intermed_2;
RIN_E_CTRL_PC31DOWNTO2_intermed_4 <= RIN_E_CTRL_PC31DOWNTO2_intermed_3;
RIN_E_CTRL_PC31DOWNTO2_intermed_5 <= RIN_E_CTRL_PC31DOWNTO2_intermed_4;
RIN_E_CTRL_PC31DOWNTO2_intermed_6 <= RIN_E_CTRL_PC31DOWNTO2_intermed_5;
R_F_PC31DOWNTO2_intermed_1 <= R.F.PC( 31 DOWNTO 2 );
R_F_PC31DOWNTO2_intermed_2 <= R_F_PC31DOWNTO2_intermed_1;
V_X_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_X_CTRL_PC31DOWNTO2_shadow;
V_X_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_X_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_X_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_X_CTRL_PC31DOWNTO2_shadow_intermed_2;
V_X_CTRL_PC31DOWNTO2_shadow_intermed_4 <= V_X_CTRL_PC31DOWNTO2_shadow_intermed_3;
VIR_ADDR31DOWNTO2_shadow_intermed_1 <= VIR_ADDR31DOWNTO2_shadow;
VIR_ADDR31DOWNTO2_shadow_intermed_2 <= VIR_ADDR31DOWNTO2_shadow_intermed_1;
VIR_ADDR31DOWNTO2_shadow_intermed_3 <= VIR_ADDR31DOWNTO2_shadow_intermed_2;
V_D_PC31DOWNTO2_shadow_intermed_1 <= V_D_PC31DOWNTO2_shadow;
V_D_PC31DOWNTO2_shadow_intermed_2 <= V_D_PC31DOWNTO2_shadow_intermed_1;
RIN_D_PC31DOWNTO2_intermed_1 <= RIN.D.PC( 31 DOWNTO 2 );
RIN_D_PC31DOWNTO2_intermed_2 <= RIN_D_PC31DOWNTO2_intermed_1;
R_D_PC31DOWNTO2_intermed_1 <= R.D.PC( 31 DOWNTO 2 );
V_D_PC31DOWNTO2_shadow_intermed_1 <= V_D_PC31DOWNTO2_shadow;
RIN_D_PC31DOWNTO2_intermed_1 <= RIN.D.PC ( 31 DOWNTO 2 );
V_D_PC31DOWNTO2_shadow_intermed_1 <= V_D_PC31DOWNTO2_shadow;
V_D_PC31DOWNTO2_shadow_intermed_2 <= V_D_PC31DOWNTO2_shadow_intermed_1;
RIN_D_PC31DOWNTO2_intermed_1 <= RIN.D.PC( 31 DOWNTO 2 );
RIN_D_PC31DOWNTO2_intermed_2 <= RIN_D_PC31DOWNTO2_intermed_1;
R_D_PC31DOWNTO2_intermed_1 <= R.D.PC( 31 DOWNTO 2 );
R_D_PC31DOWNTO2_intermed_2 <= R_D_PC31DOWNTO2_intermed_1;
V_D_PC31DOWNTO2_shadow_intermed_1 <= V_D_PC31DOWNTO2_shadow;
RIN_D_PC31DOWNTO2_intermed_1 <= RIN.D.PC ( 31 DOWNTO 2 );
R_M_CTRL_PC31DOWNTO2_intermed_1 <= R.M.CTRL.PC( 31 DOWNTO 2 );
R_M_CTRL_PC31DOWNTO2_intermed_2 <= R_M_CTRL_PC31DOWNTO2_intermed_1;
R_M_CTRL_PC31DOWNTO2_intermed_3 <= R_M_CTRL_PC31DOWNTO2_intermed_2;
RIN_M_CTRL_PC31DOWNTO2_intermed_1 <= RIN.M.CTRL.PC( 31 DOWNTO 2 );
RIN_M_CTRL_PC31DOWNTO2_intermed_2 <= RIN_M_CTRL_PC31DOWNTO2_intermed_1;
RIN_M_CTRL_PC31DOWNTO2_intermed_3 <= RIN_M_CTRL_PC31DOWNTO2_intermed_2;
RIN_M_CTRL_PC31DOWNTO2_intermed_4 <= RIN_M_CTRL_PC31DOWNTO2_intermed_3;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_E_CTRL_PC31DOWNTO2_shadow;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_2;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_4 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_3;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_5 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_4;
RIN_A_CTRL_PC31DOWNTO2_intermed_1 <= RIN.A.CTRL.PC( 31 DOWNTO 2 );
RIN_A_CTRL_PC31DOWNTO2_intermed_2 <= RIN_A_CTRL_PC31DOWNTO2_intermed_1;
RIN_A_CTRL_PC31DOWNTO2_intermed_3 <= RIN_A_CTRL_PC31DOWNTO2_intermed_2;
RIN_A_CTRL_PC31DOWNTO2_intermed_4 <= RIN_A_CTRL_PC31DOWNTO2_intermed_3;
RIN_A_CTRL_PC31DOWNTO2_intermed_5 <= RIN_A_CTRL_PC31DOWNTO2_intermed_4;
RIN_A_CTRL_PC31DOWNTO2_intermed_6 <= RIN_A_CTRL_PC31DOWNTO2_intermed_5;
R_A_CTRL_PC31DOWNTO2_intermed_1 <= R.A.CTRL.PC( 31 DOWNTO 2 );
R_A_CTRL_PC31DOWNTO2_intermed_2 <= R_A_CTRL_PC31DOWNTO2_intermed_1;
R_A_CTRL_PC31DOWNTO2_intermed_3 <= R_A_CTRL_PC31DOWNTO2_intermed_2;
R_A_CTRL_PC31DOWNTO2_intermed_4 <= R_A_CTRL_PC31DOWNTO2_intermed_3;
R_A_CTRL_PC31DOWNTO2_intermed_5 <= R_A_CTRL_PC31DOWNTO2_intermed_4;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_M_CTRL_PC31DOWNTO2_shadow;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_M_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_M_CTRL_PC31DOWNTO2_shadow_intermed_2;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_4 <= V_M_CTRL_PC31DOWNTO2_shadow_intermed_3;
R_X_CTRL_PC31DOWNTO2_intermed_1 <= R.X.CTRL.PC( 31 DOWNTO 2 );
R_X_CTRL_PC31DOWNTO2_intermed_2 <= R_X_CTRL_PC31DOWNTO2_intermed_1;
V_D_PC31DOWNTO2_shadow_intermed_1 <= V_D_PC31DOWNTO2_shadow;
V_D_PC31DOWNTO2_shadow_intermed_2 <= V_D_PC31DOWNTO2_shadow_intermed_1;
V_D_PC31DOWNTO2_shadow_intermed_3 <= V_D_PC31DOWNTO2_shadow_intermed_2;
V_D_PC31DOWNTO2_shadow_intermed_4 <= V_D_PC31DOWNTO2_shadow_intermed_3;
V_D_PC31DOWNTO2_shadow_intermed_5 <= V_D_PC31DOWNTO2_shadow_intermed_4;
V_D_PC31DOWNTO2_shadow_intermed_6 <= V_D_PC31DOWNTO2_shadow_intermed_5;
V_D_PC31DOWNTO2_shadow_intermed_7 <= V_D_PC31DOWNTO2_shadow_intermed_6;
XC_TRAP_ADDRESS31DOWNTO2_shadow_intermed_1 <= XC_TRAP_ADDRESS31DOWNTO2_shadow;
RIN_D_PC31DOWNTO2_intermed_1 <= RIN.D.PC( 31 DOWNTO 2 );
RIN_D_PC31DOWNTO2_intermed_2 <= RIN_D_PC31DOWNTO2_intermed_1;
RIN_D_PC31DOWNTO2_intermed_3 <= RIN_D_PC31DOWNTO2_intermed_2;
RIN_D_PC31DOWNTO2_intermed_4 <= RIN_D_PC31DOWNTO2_intermed_3;
RIN_D_PC31DOWNTO2_intermed_5 <= RIN_D_PC31DOWNTO2_intermed_4;
RIN_D_PC31DOWNTO2_intermed_6 <= RIN_D_PC31DOWNTO2_intermed_5;
RIN_D_PC31DOWNTO2_intermed_7 <= RIN_D_PC31DOWNTO2_intermed_6;
EX_ADD_RES32DOWNTO332DOWNTO3_shadow_intermed_1 <= EX_ADD_RES32DOWNTO332DOWNTO3_shadow;
EX_ADD_RES32DOWNTO332DOWNTO3_shadow_intermed_2 <= EX_ADD_RES32DOWNTO332DOWNTO3_shadow_intermed_1;
V_F_PC31DOWNTO2_shadow_intermed_1 <= V_F_PC31DOWNTO2_shadow;
V_F_PC31DOWNTO2_shadow_intermed_2 <= V_F_PC31DOWNTO2_shadow_intermed_1;
V_F_PC31DOWNTO2_shadow_intermed_1 <= V_F_PC31DOWNTO2_shadow;
RIN_F_PC31DOWNTO2_intermed_1 <= RIN.F.PC( 31 DOWNTO 2 );
RIN_F_PC31DOWNTO2_intermed_2 <= RIN_F_PC31DOWNTO2_intermed_1;
RIN_X_CTRL_PC31DOWNTO2_intermed_1 <= RIN.X.CTRL.PC( 31 DOWNTO 2 );
RIN_X_CTRL_PC31DOWNTO2_intermed_2 <= RIN_X_CTRL_PC31DOWNTO2_intermed_1;
RIN_X_CTRL_PC31DOWNTO2_intermed_3 <= RIN_X_CTRL_PC31DOWNTO2_intermed_2;
IRIN_ADDR31DOWNTO2_intermed_1 <= IRIN.ADDR( 31 DOWNTO 2 );
IRIN_ADDR31DOWNTO2_intermed_2 <= IRIN_ADDR31DOWNTO2_intermed_1;
R_E_CTRL_PC31DOWNTO2_intermed_1 <= R.E.CTRL.PC( 31 DOWNTO 2 );
R_E_CTRL_PC31DOWNTO2_intermed_2 <= R_E_CTRL_PC31DOWNTO2_intermed_1;
R_E_CTRL_PC31DOWNTO2_intermed_3 <= R_E_CTRL_PC31DOWNTO2_intermed_2;
R_E_CTRL_PC31DOWNTO2_intermed_4 <= R_E_CTRL_PC31DOWNTO2_intermed_3;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO2_shadow;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_2;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_4 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_3;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_5 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_4;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_6 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_5;
EX_JUMP_ADDRESS31DOWNTO2_shadow_intermed_1 <= EX_JUMP_ADDRESS31DOWNTO2_shadow;
EX_JUMP_ADDRESS31DOWNTO2_shadow_intermed_2 <= EX_JUMP_ADDRESS31DOWNTO2_shadow_intermed_1;
R_D_PC31DOWNTO2_intermed_1 <= R.D.PC( 31 DOWNTO 2 );
R_D_PC31DOWNTO2_intermed_2 <= R_D_PC31DOWNTO2_intermed_1;
R_D_PC31DOWNTO2_intermed_3 <= R_D_PC31DOWNTO2_intermed_2;
R_D_PC31DOWNTO2_intermed_4 <= R_D_PC31DOWNTO2_intermed_3;
R_D_PC31DOWNTO2_intermed_5 <= R_D_PC31DOWNTO2_intermed_4;
R_D_PC31DOWNTO2_intermed_6 <= R_D_PC31DOWNTO2_intermed_5;
RIN_F_PC31DOWNTO2_intermed_1 <= RIN.F.PC ( 31 DOWNTO 2 );
IR_ADDR31DOWNTO2_intermed_1 <= IR.ADDR( 31 DOWNTO 2 );
RIN_E_CTRL_PC31DOWNTO2_intermed_1 <= RIN.E.CTRL.PC( 31 DOWNTO 2 );
RIN_E_CTRL_PC31DOWNTO2_intermed_2 <= RIN_E_CTRL_PC31DOWNTO2_intermed_1;
RIN_E_CTRL_PC31DOWNTO2_intermed_3 <= RIN_E_CTRL_PC31DOWNTO2_intermed_2;
RIN_E_CTRL_PC31DOWNTO2_intermed_4 <= RIN_E_CTRL_PC31DOWNTO2_intermed_3;
RIN_E_CTRL_PC31DOWNTO2_intermed_5 <= RIN_E_CTRL_PC31DOWNTO2_intermed_4;
R_F_PC31DOWNTO2_intermed_1 <= R.F.PC( 31 DOWNTO 2 );
V_X_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_X_CTRL_PC31DOWNTO2_shadow;
V_X_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_X_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_X_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_X_CTRL_PC31DOWNTO2_shadow_intermed_2;
VIR_ADDR31DOWNTO2_shadow_intermed_1 <= VIR_ADDR31DOWNTO2_shadow;
VIR_ADDR31DOWNTO2_shadow_intermed_2 <= VIR_ADDR31DOWNTO2_shadow_intermed_1;
R_M_CTRL_PC31DOWNTO2_intermed_1 <= R.M.CTRL.PC( 31 DOWNTO 2 );
R_M_CTRL_PC31DOWNTO2_intermed_2 <= R_M_CTRL_PC31DOWNTO2_intermed_1;
R_M_CTRL_PC31DOWNTO2_intermed_3 <= R_M_CTRL_PC31DOWNTO2_intermed_2;
RIN_M_CTRL_PC31DOWNTO2_intermed_1 <= RIN.M.CTRL.PC( 31 DOWNTO 2 );
RIN_M_CTRL_PC31DOWNTO2_intermed_2 <= RIN_M_CTRL_PC31DOWNTO2_intermed_1;
RIN_M_CTRL_PC31DOWNTO2_intermed_3 <= RIN_M_CTRL_PC31DOWNTO2_intermed_2;
RIN_M_CTRL_PC31DOWNTO2_intermed_4 <= RIN_M_CTRL_PC31DOWNTO2_intermed_3;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_E_CTRL_PC31DOWNTO2_shadow;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_2;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_4 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_3;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_5 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_4;
RIN_A_CTRL_PC31DOWNTO2_intermed_1 <= RIN.A.CTRL.PC( 31 DOWNTO 2 );
RIN_A_CTRL_PC31DOWNTO2_intermed_2 <= RIN_A_CTRL_PC31DOWNTO2_intermed_1;
RIN_A_CTRL_PC31DOWNTO2_intermed_3 <= RIN_A_CTRL_PC31DOWNTO2_intermed_2;
RIN_A_CTRL_PC31DOWNTO2_intermed_4 <= RIN_A_CTRL_PC31DOWNTO2_intermed_3;
RIN_A_CTRL_PC31DOWNTO2_intermed_5 <= RIN_A_CTRL_PC31DOWNTO2_intermed_4;
RIN_A_CTRL_PC31DOWNTO2_intermed_6 <= RIN_A_CTRL_PC31DOWNTO2_intermed_5;
R_A_CTRL_PC31DOWNTO2_intermed_1 <= R.A.CTRL.PC( 31 DOWNTO 2 );
R_A_CTRL_PC31DOWNTO2_intermed_2 <= R_A_CTRL_PC31DOWNTO2_intermed_1;
R_A_CTRL_PC31DOWNTO2_intermed_3 <= R_A_CTRL_PC31DOWNTO2_intermed_2;
R_A_CTRL_PC31DOWNTO2_intermed_4 <= R_A_CTRL_PC31DOWNTO2_intermed_3;
R_A_CTRL_PC31DOWNTO2_intermed_5 <= R_A_CTRL_PC31DOWNTO2_intermed_4;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_M_CTRL_PC31DOWNTO2_shadow;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_M_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_M_CTRL_PC31DOWNTO2_shadow_intermed_2;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_4 <= V_M_CTRL_PC31DOWNTO2_shadow_intermed_3;
R_X_CTRL_PC31DOWNTO2_intermed_1 <= R.X.CTRL.PC( 31 DOWNTO 2 );
R_X_CTRL_PC31DOWNTO2_intermed_2 <= R_X_CTRL_PC31DOWNTO2_intermed_1;
V_D_PC31DOWNTO2_shadow_intermed_1 <= V_D_PC31DOWNTO2_shadow;
V_D_PC31DOWNTO2_shadow_intermed_2 <= V_D_PC31DOWNTO2_shadow_intermed_1;
V_D_PC31DOWNTO2_shadow_intermed_3 <= V_D_PC31DOWNTO2_shadow_intermed_2;
V_D_PC31DOWNTO2_shadow_intermed_4 <= V_D_PC31DOWNTO2_shadow_intermed_3;
V_D_PC31DOWNTO2_shadow_intermed_5 <= V_D_PC31DOWNTO2_shadow_intermed_4;
V_D_PC31DOWNTO2_shadow_intermed_6 <= V_D_PC31DOWNTO2_shadow_intermed_5;
V_D_PC31DOWNTO2_shadow_intermed_7 <= V_D_PC31DOWNTO2_shadow_intermed_6;
XC_TRAP_ADDRESS31DOWNTO2_shadow_intermed_1 <= XC_TRAP_ADDRESS31DOWNTO2_shadow;
RIN_D_PC31DOWNTO2_intermed_1 <= RIN.D.PC( 31 DOWNTO 2 );
RIN_D_PC31DOWNTO2_intermed_2 <= RIN_D_PC31DOWNTO2_intermed_1;
RIN_D_PC31DOWNTO2_intermed_3 <= RIN_D_PC31DOWNTO2_intermed_2;
RIN_D_PC31DOWNTO2_intermed_4 <= RIN_D_PC31DOWNTO2_intermed_3;
RIN_D_PC31DOWNTO2_intermed_5 <= RIN_D_PC31DOWNTO2_intermed_4;
RIN_D_PC31DOWNTO2_intermed_6 <= RIN_D_PC31DOWNTO2_intermed_5;
RIN_D_PC31DOWNTO2_intermed_7 <= RIN_D_PC31DOWNTO2_intermed_6;
EX_ADD_RES32DOWNTO332DOWNTO3_shadow_intermed_1 <= EX_ADD_RES32DOWNTO332DOWNTO3_shadow;
V_F_PC31DOWNTO2_shadow_intermed_1 <= V_F_PC31DOWNTO2_shadow;
RIN_F_PC31DOWNTO2_intermed_1 <= RIN.F.PC( 31 DOWNTO 2 );
RIN_X_CTRL_PC31DOWNTO2_intermed_1 <= RIN.X.CTRL.PC( 31 DOWNTO 2 );
RIN_X_CTRL_PC31DOWNTO2_intermed_2 <= RIN_X_CTRL_PC31DOWNTO2_intermed_1;
RIN_X_CTRL_PC31DOWNTO2_intermed_3 <= RIN_X_CTRL_PC31DOWNTO2_intermed_2;
IRIN_ADDR31DOWNTO2_intermed_1 <= IRIN.ADDR( 31 DOWNTO 2 );
IRIN_ADDR31DOWNTO2_intermed_2 <= IRIN_ADDR31DOWNTO2_intermed_1;
R_E_CTRL_PC31DOWNTO2_intermed_1 <= R.E.CTRL.PC( 31 DOWNTO 2 );
R_E_CTRL_PC31DOWNTO2_intermed_2 <= R_E_CTRL_PC31DOWNTO2_intermed_1;
R_E_CTRL_PC31DOWNTO2_intermed_3 <= R_E_CTRL_PC31DOWNTO2_intermed_2;
R_E_CTRL_PC31DOWNTO2_intermed_4 <= R_E_CTRL_PC31DOWNTO2_intermed_3;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO2_shadow;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_2;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_4 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_3;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_5 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_4;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_6 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_5;
EX_JUMP_ADDRESS31DOWNTO2_shadow_intermed_1 <= EX_JUMP_ADDRESS31DOWNTO2_shadow;
R_D_PC31DOWNTO2_intermed_1 <= R.D.PC( 31 DOWNTO 2 );
R_D_PC31DOWNTO2_intermed_2 <= R_D_PC31DOWNTO2_intermed_1;
R_D_PC31DOWNTO2_intermed_3 <= R_D_PC31DOWNTO2_intermed_2;
R_D_PC31DOWNTO2_intermed_4 <= R_D_PC31DOWNTO2_intermed_3;
R_D_PC31DOWNTO2_intermed_5 <= R_D_PC31DOWNTO2_intermed_4;
R_D_PC31DOWNTO2_intermed_6 <= R_D_PC31DOWNTO2_intermed_5;
IR_ADDR31DOWNTO2_intermed_1 <= IR.ADDR( 31 DOWNTO 2 );
RIN_E_CTRL_PC31DOWNTO2_intermed_1 <= RIN.E.CTRL.PC( 31 DOWNTO 2 );
RIN_E_CTRL_PC31DOWNTO2_intermed_2 <= RIN_E_CTRL_PC31DOWNTO2_intermed_1;
RIN_E_CTRL_PC31DOWNTO2_intermed_3 <= RIN_E_CTRL_PC31DOWNTO2_intermed_2;
RIN_E_CTRL_PC31DOWNTO2_intermed_4 <= RIN_E_CTRL_PC31DOWNTO2_intermed_3;
RIN_E_CTRL_PC31DOWNTO2_intermed_5 <= RIN_E_CTRL_PC31DOWNTO2_intermed_4;
V_X_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_X_CTRL_PC31DOWNTO2_shadow;
V_X_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_X_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_X_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_X_CTRL_PC31DOWNTO2_shadow_intermed_2;
VIR_ADDR31DOWNTO2_shadow_intermed_1 <= VIR_ADDR31DOWNTO2_shadow;
VIR_ADDR31DOWNTO2_shadow_intermed_2 <= VIR_ADDR31DOWNTO2_shadow_intermed_1;
V_X_ANNUL_ALL_shadow_intermed_1 <= V_X_ANNUL_ALL_shadow;
RIN_A_CTRL_ANNUL_intermed_1 <= RIN.A.CTRL.ANNUL;
V_A_MULSTART_shadow_intermed_1 <= V_A_MULSTART_shadow;
RIN_X_ANNUL_ALL_intermed_1 <= RIN.X.ANNUL_ALL;
RIN_X_ANNUL_ALL_intermed_2 <= RIN_X_ANNUL_ALL_intermed_1;
R_X_ANNUL_ALL_intermed_1 <= R.X.ANNUL_ALL;
RIN_A_MULSTART_intermed_1 <= RIN.A.MULSTART;
V_A_CTRL_ANNUL_shadow_intermed_1 <= V_A_CTRL_ANNUL_shadow;
RIN_X_DATA031_intermed_1 <= RIN.X.DATA ( 0 )( 31 );
V_X_DATA0_shadow_intermed_1 <= V_X_DATA0_shadow;
V_X_DATA0_shadow_intermed_2 <= V_X_DATA0_shadow_intermed_1;
DE_INST19_shadow_intermed_1 <= DE_INST19_shadow;
DE_INST19_shadow_intermed_2 <= DE_INST19_shadow_intermed_1;
RIN_E_OP131_intermed_1 <= RIN.E.OP1( 31 );
R_D_INST019_intermed_1 <= R.D.INST ( 0 )( 19 );
R_D_INST019_intermed_2 <= R_D_INST019_intermed_1;
V_A_CTRL_INST19_shadow_intermed_1 <= V_A_CTRL_INST19_shadow;
V_A_CTRL_INST19_shadow_intermed_2 <= V_A_CTRL_INST19_shadow_intermed_1;
V_A_CTRL_INST19_shadow_intermed_3 <= V_A_CTRL_INST19_shadow_intermed_2;
RIN_D_INST019_intermed_1 <= RIN.D.INST ( 0 )( 19 );
RIN_D_INST019_intermed_2 <= RIN_D_INST019_intermed_1;
RIN_D_INST019_intermed_3 <= RIN_D_INST019_intermed_2;
RIN_X_DATA0_intermed_1 <= RIN.X.DATA ( 0 );
V_E_OP131_shadow_intermed_1 <= V_E_OP131_shadow;
V_X_DATA031_shadow_intermed_1 <= V_X_DATA031_shadow;
V_E_CTRL_INST19_shadow_intermed_1 <= V_E_CTRL_INST19_shadow;
V_E_OP1_shadow_intermed_1 <= V_E_OP1_shadow;
R_D_INST019_intermed_1 <= R.D.INST( 0 )( 19 );
R_D_INST019_intermed_2 <= R_D_INST019_intermed_1;
R_D_INST019_intermed_3 <= R_D_INST019_intermed_2;
V_X_DATA031_shadow_intermed_1 <= V_X_DATA031_shadow;
V_X_DATA031_shadow_intermed_2 <= V_X_DATA031_shadow_intermed_1;
V_E_CTRL_INST19_shadow_intermed_1 <= V_E_CTRL_INST19_shadow;
V_E_CTRL_INST19_shadow_intermed_2 <= V_E_CTRL_INST19_shadow_intermed_1;
RIN_X_DATA031_intermed_1 <= RIN.X.DATA( 0 )( 31 );
RIN_X_DATA031_intermed_2 <= RIN_X_DATA031_intermed_1;
RIN_E_OP1_intermed_1 <= RIN.E.OP1;
V_D_INST019_shadow_intermed_1 <= V_D_INST019_shadow;
V_D_INST019_shadow_intermed_2 <= V_D_INST019_shadow_intermed_1;
V_D_INST019_shadow_intermed_3 <= V_D_INST019_shadow_intermed_2;
R_E_CTRL_INST19_intermed_1 <= R.E.CTRL.INST( 19 );
V_X_DATA0_shadow_intermed_1 <= V_X_DATA0_shadow;
R_X_DATA031_intermed_1 <= R.X.DATA( 0 )( 31 );
RIN_A_CTRL_INST19_intermed_1 <= RIN.A.CTRL.INST ( 19 );
RIN_A_CTRL_INST19_intermed_2 <= RIN_A_CTRL_INST19_intermed_1;
R_X_DATA0_intermed_1 <= R.X.DATA( 0 );
R_A_CTRL_INST19_intermed_1 <= R.A.CTRL.INST( 19 );
R_A_CTRL_INST19_intermed_2 <= R_A_CTRL_INST19_intermed_1;
V_D_INST019_shadow_intermed_1 <= V_D_INST019_shadow;
V_D_INST019_shadow_intermed_2 <= V_D_INST019_shadow_intermed_1;
V_D_INST019_shadow_intermed_3 <= V_D_INST019_shadow_intermed_2;
V_D_INST019_shadow_intermed_4 <= V_D_INST019_shadow_intermed_3;
RIN_D_INST019_intermed_1 <= RIN.D.INST( 0 )( 19 );
RIN_D_INST019_intermed_2 <= RIN_D_INST019_intermed_1;
RIN_D_INST019_intermed_3 <= RIN_D_INST019_intermed_2;
RIN_D_INST019_intermed_4 <= RIN_D_INST019_intermed_3;
R_A_CTRL_INST19_intermed_1 <= R.A.CTRL.INST ( 19 );
RIN_A_CTRL_INST19_intermed_1 <= RIN.A.CTRL.INST( 19 );
RIN_A_CTRL_INST19_intermed_2 <= RIN_A_CTRL_INST19_intermed_1;
RIN_A_CTRL_INST19_intermed_3 <= RIN_A_CTRL_INST19_intermed_2;
RIN_E_CTRL_INST19_intermed_1 <= RIN.E.CTRL.INST ( 19 );
RIN_X_DATA0_intermed_1 <= RIN.X.DATA( 0 );
RIN_X_DATA0_intermed_2 <= RIN_X_DATA0_intermed_1;
RIN_E_CTRL_INST19_intermed_1 <= RIN.E.CTRL.INST( 19 );
RIN_E_CTRL_INST19_intermed_2 <= RIN_E_CTRL_INST19_intermed_1;
V_A_CTRL_INST19_shadow_intermed_1 <= V_A_CTRL_INST19_shadow;
V_A_CTRL_INST19_shadow_intermed_2 <= V_A_CTRL_INST19_shadow_intermed_1;
RIN_X_DATA031_intermed_1 <= RIN.X.DATA ( 0 )( 31 );
V_X_DATA0_shadow_intermed_1 <= V_X_DATA0_shadow;
V_X_DATA0_shadow_intermed_2 <= V_X_DATA0_shadow_intermed_1;
DE_INST19_shadow_intermed_1 <= DE_INST19_shadow;
DE_INST19_shadow_intermed_2 <= DE_INST19_shadow_intermed_1;
R_D_INST019_intermed_1 <= R.D.INST ( 0 )( 19 );
R_D_INST019_intermed_2 <= R_D_INST019_intermed_1;
V_A_CTRL_INST19_shadow_intermed_1 <= V_A_CTRL_INST19_shadow;
V_A_CTRL_INST19_shadow_intermed_2 <= V_A_CTRL_INST19_shadow_intermed_1;
V_A_CTRL_INST19_shadow_intermed_3 <= V_A_CTRL_INST19_shadow_intermed_2;
RIN_D_INST019_intermed_1 <= RIN.D.INST ( 0 )( 19 );
RIN_D_INST019_intermed_2 <= RIN_D_INST019_intermed_1;
RIN_D_INST019_intermed_3 <= RIN_D_INST019_intermed_2;
RIN_X_DATA0_intermed_1 <= RIN.X.DATA ( 0 );
V_X_DATA031_shadow_intermed_1 <= V_X_DATA031_shadow;
V_E_CTRL_INST19_shadow_intermed_1 <= V_E_CTRL_INST19_shadow;
R_D_INST019_intermed_1 <= R.D.INST( 0 )( 19 );
R_D_INST019_intermed_2 <= R_D_INST019_intermed_1;
R_D_INST019_intermed_3 <= R_D_INST019_intermed_2;
V_X_DATA031_shadow_intermed_1 <= V_X_DATA031_shadow;
V_X_DATA031_shadow_intermed_2 <= V_X_DATA031_shadow_intermed_1;
V_E_OP2_shadow_intermed_1 <= V_E_OP2_shadow;
RIN_E_OP2_intermed_1 <= RIN.E.OP2;
V_E_CTRL_INST19_shadow_intermed_1 <= V_E_CTRL_INST19_shadow;
V_E_CTRL_INST19_shadow_intermed_2 <= V_E_CTRL_INST19_shadow_intermed_1;
RIN_X_DATA031_intermed_1 <= RIN.X.DATA( 0 )( 31 );
RIN_X_DATA031_intermed_2 <= RIN_X_DATA031_intermed_1;
V_D_INST019_shadow_intermed_1 <= V_D_INST019_shadow;
V_D_INST019_shadow_intermed_2 <= V_D_INST019_shadow_intermed_1;
V_D_INST019_shadow_intermed_3 <= V_D_INST019_shadow_intermed_2;
R_E_CTRL_INST19_intermed_1 <= R.E.CTRL.INST( 19 );
V_X_DATA0_shadow_intermed_1 <= V_X_DATA0_shadow;
R_X_DATA031_intermed_1 <= R.X.DATA( 0 )( 31 );
RIN_A_CTRL_INST19_intermed_1 <= RIN.A.CTRL.INST ( 19 );
RIN_A_CTRL_INST19_intermed_2 <= RIN_A_CTRL_INST19_intermed_1;
R_X_DATA0_intermed_1 <= R.X.DATA( 0 );
R_A_CTRL_INST19_intermed_1 <= R.A.CTRL.INST( 19 );
R_A_CTRL_INST19_intermed_2 <= R_A_CTRL_INST19_intermed_1;
V_D_INST019_shadow_intermed_1 <= V_D_INST019_shadow;
V_D_INST019_shadow_intermed_2 <= V_D_INST019_shadow_intermed_1;
V_D_INST019_shadow_intermed_3 <= V_D_INST019_shadow_intermed_2;
V_D_INST019_shadow_intermed_4 <= V_D_INST019_shadow_intermed_3;
RIN_E_OP231_intermed_1 <= RIN.E.OP2( 31 );
RIN_D_INST019_intermed_1 <= RIN.D.INST( 0 )( 19 );
RIN_D_INST019_intermed_2 <= RIN_D_INST019_intermed_1;
RIN_D_INST019_intermed_3 <= RIN_D_INST019_intermed_2;
RIN_D_INST019_intermed_4 <= RIN_D_INST019_intermed_3;
R_A_CTRL_INST19_intermed_1 <= R.A.CTRL.INST ( 19 );
RIN_A_CTRL_INST19_intermed_1 <= RIN.A.CTRL.INST( 19 );
RIN_A_CTRL_INST19_intermed_2 <= RIN_A_CTRL_INST19_intermed_1;
RIN_A_CTRL_INST19_intermed_3 <= RIN_A_CTRL_INST19_intermed_2;
RIN_E_CTRL_INST19_intermed_1 <= RIN.E.CTRL.INST ( 19 );
V_E_OP231_shadow_intermed_1 <= V_E_OP231_shadow;
RIN_X_DATA0_intermed_1 <= RIN.X.DATA( 0 );
RIN_X_DATA0_intermed_2 <= RIN_X_DATA0_intermed_1;
RIN_E_CTRL_INST19_intermed_1 <= RIN.E.CTRL.INST( 19 );
RIN_E_CTRL_INST19_intermed_2 <= RIN_E_CTRL_INST19_intermed_1;
V_A_CTRL_INST19_shadow_intermed_1 <= V_A_CTRL_INST19_shadow;
V_A_CTRL_INST19_shadow_intermed_2 <= V_A_CTRL_INST19_shadow_intermed_1;
V_A_CTRL_INST24_shadow_intermed_1 <= V_A_CTRL_INST24_shadow;
V_A_CTRL_INST24_shadow_intermed_2 <= V_A_CTRL_INST24_shadow_intermed_1;
V_A_CTRL_INST24_shadow_intermed_3 <= V_A_CTRL_INST24_shadow_intermed_2;
V_E_CTRL_INST24_shadow_intermed_1 <= V_E_CTRL_INST24_shadow;
V_E_CTRL_INST24_shadow_intermed_2 <= V_E_CTRL_INST24_shadow_intermed_1;
DE_INST24_shadow_intermed_1 <= DE_INST24_shadow;
DE_INST24_shadow_intermed_2 <= DE_INST24_shadow_intermed_1;
DE_INST24_shadow_intermed_3 <= DE_INST24_shadow_intermed_2;
V_E_CTRL_INST24_shadow_intermed_1 <= V_E_CTRL_INST24_shadow;
R_A_CTRL_INST24_intermed_1 <= R.A.CTRL.INST( 24 );
R_A_CTRL_INST24_intermed_2 <= R_A_CTRL_INST24_intermed_1;
RIN_A_CTRL_INST24_intermed_1 <= RIN.A.CTRL.INST ( 24 );
RIN_A_CTRL_INST24_intermed_2 <= RIN_A_CTRL_INST24_intermed_1;
RIN_D_INST024_intermed_1 <= RIN.D.INST( 0 )( 24 );
RIN_D_INST024_intermed_2 <= RIN_D_INST024_intermed_1;
RIN_D_INST024_intermed_3 <= RIN_D_INST024_intermed_2;
RIN_D_INST024_intermed_4 <= RIN_D_INST024_intermed_3;
RIN_D_INST024_intermed_5 <= RIN_D_INST024_intermed_4;
V_A_CTRL_INST24_shadow_intermed_1 <= V_A_CTRL_INST24_shadow;
V_A_CTRL_INST24_shadow_intermed_2 <= V_A_CTRL_INST24_shadow_intermed_1;
RIN_D_INST024_intermed_1 <= RIN.D.INST ( 0 )( 24 );
RIN_D_INST024_intermed_2 <= RIN_D_INST024_intermed_1;
RIN_D_INST024_intermed_3 <= RIN_D_INST024_intermed_2;
RIN_D_INST024_intermed_4 <= RIN_D_INST024_intermed_3;
V_D_INST024_shadow_intermed_1 <= V_D_INST024_shadow;
V_D_INST024_shadow_intermed_2 <= V_D_INST024_shadow_intermed_1;
V_D_INST024_shadow_intermed_3 <= V_D_INST024_shadow_intermed_2;
V_D_INST024_shadow_intermed_4 <= V_D_INST024_shadow_intermed_3;
V_D_INST024_shadow_intermed_5 <= V_D_INST024_shadow_intermed_4;
RIN_A_CTRL_INST24_intermed_1 <= RIN.A.CTRL.INST( 24 );
RIN_A_CTRL_INST24_intermed_2 <= RIN_A_CTRL_INST24_intermed_1;
RIN_A_CTRL_INST24_intermed_3 <= RIN_A_CTRL_INST24_intermed_2;
RIN_E_CTRL_INST24_intermed_1 <= RIN.E.CTRL.INST( 24 );
RIN_E_CTRL_INST24_intermed_2 <= RIN_E_CTRL_INST24_intermed_1;
R_D_INST024_intermed_1 <= R.D.INST ( 0 )( 24 );
R_D_INST024_intermed_2 <= R_D_INST024_intermed_1;
R_D_INST024_intermed_3 <= R_D_INST024_intermed_2;
V_D_INST024_shadow_intermed_1 <= V_D_INST024_shadow;
V_D_INST024_shadow_intermed_2 <= V_D_INST024_shadow_intermed_1;
V_D_INST024_shadow_intermed_3 <= V_D_INST024_shadow_intermed_2;
V_D_INST024_shadow_intermed_4 <= V_D_INST024_shadow_intermed_3;
R_D_INST024_intermed_1 <= R.D.INST( 0 )( 24 );
R_D_INST024_intermed_2 <= R_D_INST024_intermed_1;
R_D_INST024_intermed_3 <= R_D_INST024_intermed_2;
R_D_INST024_intermed_4 <= R_D_INST024_intermed_3;
R_E_CTRL_INST24_intermed_1 <= R.E.CTRL.INST( 24 );
R_E_CTRL_INST24_intermed_2 <= R_E_CTRL_INST24_intermed_1;
R_A_CTRL_INST24_intermed_1 <= R.A.CTRL.INST ( 24 );
RIN_E_CTRL_INST24_intermed_1 <= RIN.E.CTRL.INST ( 24 );
RIN_W_S_Y7DOWNTO0_intermed_1 <= RIN.W.S.Y ( 7 DOWNTO 0 );
V_X_Y7DOWNTO0_shadow_intermed_1 <= V_X_Y7DOWNTO0_shadow;
V_W_S_Y7DOWNTO0_shadow_intermed_1 <= V_W_S_Y7DOWNTO0_shadow;
RIN_X_Y7DOWNTO0_intermed_1 <= RIN.X.Y ( 7 DOWNTO 0 );
V_X_ANNUL_ALL_shadow_intermed_1 <= V_X_ANNUL_ALL_shadow;
RIN_A_CTRL_ANNUL_intermed_1 <= RIN.A.CTRL.ANNUL;
RIN_A_DIVSTART_intermed_1 <= RIN.A.DIVSTART;
RIN_X_ANNUL_ALL_intermed_1 <= RIN.X.ANNUL_ALL;
RIN_X_ANNUL_ALL_intermed_2 <= RIN_X_ANNUL_ALL_intermed_1;
R_X_ANNUL_ALL_intermed_1 <= R.X.ANNUL_ALL;
V_A_DIVSTART_shadow_intermed_1 <= V_A_DIVSTART_shadow;
V_A_CTRL_ANNUL_shadow_intermed_1 <= V_A_CTRL_ANNUL_shadow;
RIN_X_DATA031_intermed_1 <= RIN.X.DATA ( 0 )( 31 );
V_X_DATA0_shadow_intermed_1 <= V_X_DATA0_shadow;
V_X_DATA0_shadow_intermed_2 <= V_X_DATA0_shadow_intermed_1;
DE_INST19_shadow_intermed_1 <= DE_INST19_shadow;
DE_INST19_shadow_intermed_2 <= DE_INST19_shadow_intermed_1;
RIN_E_OP131_intermed_1 <= RIN.E.OP1( 31 );
R_D_INST019_intermed_1 <= R.D.INST ( 0 )( 19 );
R_D_INST019_intermed_2 <= R_D_INST019_intermed_1;
V_A_CTRL_INST19_shadow_intermed_1 <= V_A_CTRL_INST19_shadow;
V_A_CTRL_INST19_shadow_intermed_2 <= V_A_CTRL_INST19_shadow_intermed_1;
V_A_CTRL_INST19_shadow_intermed_3 <= V_A_CTRL_INST19_shadow_intermed_2;
RIN_D_INST019_intermed_1 <= RIN.D.INST ( 0 )( 19 );
RIN_D_INST019_intermed_2 <= RIN_D_INST019_intermed_1;
RIN_D_INST019_intermed_3 <= RIN_D_INST019_intermed_2;
RIN_X_DATA0_intermed_1 <= RIN.X.DATA ( 0 );
V_E_OP131_shadow_intermed_1 <= V_E_OP131_shadow;
V_X_DATA031_shadow_intermed_1 <= V_X_DATA031_shadow;
V_E_CTRL_INST19_shadow_intermed_1 <= V_E_CTRL_INST19_shadow;
V_E_OP1_shadow_intermed_1 <= V_E_OP1_shadow;
R_D_INST019_intermed_1 <= R.D.INST( 0 )( 19 );
R_D_INST019_intermed_2 <= R_D_INST019_intermed_1;
R_D_INST019_intermed_3 <= R_D_INST019_intermed_2;
V_X_DATA031_shadow_intermed_1 <= V_X_DATA031_shadow;
V_X_DATA031_shadow_intermed_2 <= V_X_DATA031_shadow_intermed_1;
V_E_CTRL_INST19_shadow_intermed_1 <= V_E_CTRL_INST19_shadow;
V_E_CTRL_INST19_shadow_intermed_2 <= V_E_CTRL_INST19_shadow_intermed_1;
RIN_X_DATA031_intermed_1 <= RIN.X.DATA( 0 )( 31 );
RIN_X_DATA031_intermed_2 <= RIN_X_DATA031_intermed_1;
RIN_E_OP1_intermed_1 <= RIN.E.OP1;
V_D_INST019_shadow_intermed_1 <= V_D_INST019_shadow;
V_D_INST019_shadow_intermed_2 <= V_D_INST019_shadow_intermed_1;
V_D_INST019_shadow_intermed_3 <= V_D_INST019_shadow_intermed_2;
R_E_CTRL_INST19_intermed_1 <= R.E.CTRL.INST( 19 );
V_X_DATA0_shadow_intermed_1 <= V_X_DATA0_shadow;
R_X_DATA031_intermed_1 <= R.X.DATA( 0 )( 31 );
RIN_A_CTRL_INST19_intermed_1 <= RIN.A.CTRL.INST ( 19 );
RIN_A_CTRL_INST19_intermed_2 <= RIN_A_CTRL_INST19_intermed_1;
R_X_DATA0_intermed_1 <= R.X.DATA( 0 );
R_A_CTRL_INST19_intermed_1 <= R.A.CTRL.INST( 19 );
R_A_CTRL_INST19_intermed_2 <= R_A_CTRL_INST19_intermed_1;
V_D_INST019_shadow_intermed_1 <= V_D_INST019_shadow;
V_D_INST019_shadow_intermed_2 <= V_D_INST019_shadow_intermed_1;
V_D_INST019_shadow_intermed_3 <= V_D_INST019_shadow_intermed_2;
V_D_INST019_shadow_intermed_4 <= V_D_INST019_shadow_intermed_3;
RIN_D_INST019_intermed_1 <= RIN.D.INST( 0 )( 19 );
RIN_D_INST019_intermed_2 <= RIN_D_INST019_intermed_1;
RIN_D_INST019_intermed_3 <= RIN_D_INST019_intermed_2;
RIN_D_INST019_intermed_4 <= RIN_D_INST019_intermed_3;
R_A_CTRL_INST19_intermed_1 <= R.A.CTRL.INST ( 19 );
RIN_A_CTRL_INST19_intermed_1 <= RIN.A.CTRL.INST( 19 );
RIN_A_CTRL_INST19_intermed_2 <= RIN_A_CTRL_INST19_intermed_1;
RIN_A_CTRL_INST19_intermed_3 <= RIN_A_CTRL_INST19_intermed_2;
RIN_E_CTRL_INST19_intermed_1 <= RIN.E.CTRL.INST ( 19 );
RIN_X_DATA0_intermed_1 <= RIN.X.DATA( 0 );
RIN_X_DATA0_intermed_2 <= RIN_X_DATA0_intermed_1;
RIN_E_CTRL_INST19_intermed_1 <= RIN.E.CTRL.INST( 19 );
RIN_E_CTRL_INST19_intermed_2 <= RIN_E_CTRL_INST19_intermed_1;
V_A_CTRL_INST19_shadow_intermed_1 <= V_A_CTRL_INST19_shadow;
V_A_CTRL_INST19_shadow_intermed_2 <= V_A_CTRL_INST19_shadow_intermed_1;
RIN_X_DATA031_intermed_1 <= RIN.X.DATA ( 0 )( 31 );
V_X_DATA0_shadow_intermed_1 <= V_X_DATA0_shadow;
V_X_DATA0_shadow_intermed_2 <= V_X_DATA0_shadow_intermed_1;
DE_INST19_shadow_intermed_1 <= DE_INST19_shadow;
DE_INST19_shadow_intermed_2 <= DE_INST19_shadow_intermed_1;
R_D_INST019_intermed_1 <= R.D.INST ( 0 )( 19 );
R_D_INST019_intermed_2 <= R_D_INST019_intermed_1;
V_A_CTRL_INST19_shadow_intermed_1 <= V_A_CTRL_INST19_shadow;
V_A_CTRL_INST19_shadow_intermed_2 <= V_A_CTRL_INST19_shadow_intermed_1;
V_A_CTRL_INST19_shadow_intermed_3 <= V_A_CTRL_INST19_shadow_intermed_2;
RIN_D_INST019_intermed_1 <= RIN.D.INST ( 0 )( 19 );
RIN_D_INST019_intermed_2 <= RIN_D_INST019_intermed_1;
RIN_D_INST019_intermed_3 <= RIN_D_INST019_intermed_2;
RIN_X_DATA0_intermed_1 <= RIN.X.DATA ( 0 );
V_X_DATA031_shadow_intermed_1 <= V_X_DATA031_shadow;
V_E_CTRL_INST19_shadow_intermed_1 <= V_E_CTRL_INST19_shadow;
R_D_INST019_intermed_1 <= R.D.INST( 0 )( 19 );
R_D_INST019_intermed_2 <= R_D_INST019_intermed_1;
R_D_INST019_intermed_3 <= R_D_INST019_intermed_2;
V_X_DATA031_shadow_intermed_1 <= V_X_DATA031_shadow;
V_X_DATA031_shadow_intermed_2 <= V_X_DATA031_shadow_intermed_1;
V_E_OP2_shadow_intermed_1 <= V_E_OP2_shadow;
RIN_E_OP2_intermed_1 <= RIN.E.OP2;
V_E_CTRL_INST19_shadow_intermed_1 <= V_E_CTRL_INST19_shadow;
V_E_CTRL_INST19_shadow_intermed_2 <= V_E_CTRL_INST19_shadow_intermed_1;
RIN_X_DATA031_intermed_1 <= RIN.X.DATA( 0 )( 31 );
RIN_X_DATA031_intermed_2 <= RIN_X_DATA031_intermed_1;
V_D_INST019_shadow_intermed_1 <= V_D_INST019_shadow;
V_D_INST019_shadow_intermed_2 <= V_D_INST019_shadow_intermed_1;
V_D_INST019_shadow_intermed_3 <= V_D_INST019_shadow_intermed_2;
R_E_CTRL_INST19_intermed_1 <= R.E.CTRL.INST( 19 );
V_X_DATA0_shadow_intermed_1 <= V_X_DATA0_shadow;
R_X_DATA031_intermed_1 <= R.X.DATA( 0 )( 31 );
RIN_A_CTRL_INST19_intermed_1 <= RIN.A.CTRL.INST ( 19 );
RIN_A_CTRL_INST19_intermed_2 <= RIN_A_CTRL_INST19_intermed_1;
R_X_DATA0_intermed_1 <= R.X.DATA( 0 );
R_A_CTRL_INST19_intermed_1 <= R.A.CTRL.INST( 19 );
R_A_CTRL_INST19_intermed_2 <= R_A_CTRL_INST19_intermed_1;
V_D_INST019_shadow_intermed_1 <= V_D_INST019_shadow;
V_D_INST019_shadow_intermed_2 <= V_D_INST019_shadow_intermed_1;
V_D_INST019_shadow_intermed_3 <= V_D_INST019_shadow_intermed_2;
V_D_INST019_shadow_intermed_4 <= V_D_INST019_shadow_intermed_3;
RIN_E_OP231_intermed_1 <= RIN.E.OP2( 31 );
RIN_D_INST019_intermed_1 <= RIN.D.INST( 0 )( 19 );
RIN_D_INST019_intermed_2 <= RIN_D_INST019_intermed_1;
RIN_D_INST019_intermed_3 <= RIN_D_INST019_intermed_2;
RIN_D_INST019_intermed_4 <= RIN_D_INST019_intermed_3;
R_A_CTRL_INST19_intermed_1 <= R.A.CTRL.INST ( 19 );
RIN_A_CTRL_INST19_intermed_1 <= RIN.A.CTRL.INST( 19 );
RIN_A_CTRL_INST19_intermed_2 <= RIN_A_CTRL_INST19_intermed_1;
RIN_A_CTRL_INST19_intermed_3 <= RIN_A_CTRL_INST19_intermed_2;
RIN_E_CTRL_INST19_intermed_1 <= RIN.E.CTRL.INST ( 19 );
V_E_OP231_shadow_intermed_1 <= V_E_OP231_shadow;
RIN_X_DATA0_intermed_1 <= RIN.X.DATA( 0 );
RIN_X_DATA0_intermed_2 <= RIN_X_DATA0_intermed_1;
RIN_E_CTRL_INST19_intermed_1 <= RIN.E.CTRL.INST( 19 );
RIN_E_CTRL_INST19_intermed_2 <= RIN_E_CTRL_INST19_intermed_1;
V_A_CTRL_INST19_shadow_intermed_1 <= V_A_CTRL_INST19_shadow;
V_A_CTRL_INST19_shadow_intermed_2 <= V_A_CTRL_INST19_shadow_intermed_1;
DE_INST19_shadow_intermed_1 <= DE_INST19_shadow;
DE_INST19_shadow_intermed_2 <= DE_INST19_shadow_intermed_1;
R_D_INST019_intermed_1 <= R.D.INST ( 0 )( 19 );
R_D_INST019_intermed_2 <= R_D_INST019_intermed_1;
RIN_D_INST019_intermed_1 <= RIN.D.INST ( 0 )( 19 );
RIN_D_INST019_intermed_2 <= RIN_D_INST019_intermed_1;
RIN_D_INST019_intermed_3 <= RIN_D_INST019_intermed_2;
V_A_CTRL_INST19_shadow_intermed_1 <= V_A_CTRL_INST19_shadow;
V_A_CTRL_INST19_shadow_intermed_2 <= V_A_CTRL_INST19_shadow_intermed_1;
R_D_INST019_intermed_1 <= R.D.INST( 0 )( 19 );
R_D_INST019_intermed_2 <= R_D_INST019_intermed_1;
R_D_INST019_intermed_3 <= R_D_INST019_intermed_2;
V_D_INST019_shadow_intermed_1 <= V_D_INST019_shadow;
V_D_INST019_shadow_intermed_2 <= V_D_INST019_shadow_intermed_1;
V_D_INST019_shadow_intermed_3 <= V_D_INST019_shadow_intermed_2;
RIN_A_CTRL_INST19_intermed_1 <= RIN.A.CTRL.INST ( 19 );
R_A_CTRL_INST19_intermed_1 <= R.A.CTRL.INST( 19 );
R_A_CTRL_INST19_intermed_2 <= R_A_CTRL_INST19_intermed_1;
V_D_INST019_shadow_intermed_1 <= V_D_INST019_shadow;
V_D_INST019_shadow_intermed_2 <= V_D_INST019_shadow_intermed_1;
V_D_INST019_shadow_intermed_3 <= V_D_INST019_shadow_intermed_2;
V_D_INST019_shadow_intermed_4 <= V_D_INST019_shadow_intermed_3;
RIN_D_INST019_intermed_1 <= RIN.D.INST( 0 )( 19 );
RIN_D_INST019_intermed_2 <= RIN_D_INST019_intermed_1;
RIN_D_INST019_intermed_3 <= RIN_D_INST019_intermed_2;
RIN_D_INST019_intermed_4 <= RIN_D_INST019_intermed_3;
RIN_A_CTRL_INST19_intermed_1 <= RIN.A.CTRL.INST( 19 );
RIN_A_CTRL_INST19_intermed_2 <= RIN_A_CTRL_INST19_intermed_1;
V_A_CTRL_INST19_shadow_intermed_1 <= V_A_CTRL_INST19_shadow;
DE_INST19_shadow_intermed_1 <= DE_INST19_shadow;
RIN_M_Y31_intermed_1 <= RIN.M.Y ( 31 );
RIN_M_Y_intermed_1 <= RIN.M.Y;
R_D_INST019_intermed_1 <= R.D.INST ( 0 )( 19 );
V_A_CTRL_INST19_shadow_intermed_1 <= V_A_CTRL_INST19_shadow;
V_A_CTRL_INST19_shadow_intermed_2 <= V_A_CTRL_INST19_shadow_intermed_1;
RIN_D_INST019_intermed_1 <= RIN.D.INST ( 0 )( 19 );
RIN_D_INST019_intermed_2 <= RIN_D_INST019_intermed_1;
V_E_CTRL_INST19_shadow_intermed_1 <= V_E_CTRL_INST19_shadow;
R_D_INST019_intermed_1 <= R.D.INST( 0 )( 19 );
R_D_INST019_intermed_2 <= R_D_INST019_intermed_1;
V_M_Y31_shadow_intermed_1 <= V_M_Y31_shadow;
V_M_Y31_shadow_intermed_2 <= V_M_Y31_shadow_intermed_1;
V_M_Y_shadow_intermed_1 <= V_M_Y_shadow;
V_E_CTRL_INST19_shadow_intermed_1 <= V_E_CTRL_INST19_shadow;
V_E_CTRL_INST19_shadow_intermed_2 <= V_E_CTRL_INST19_shadow_intermed_1;
V_D_INST019_shadow_intermed_1 <= V_D_INST019_shadow;
V_D_INST019_shadow_intermed_2 <= V_D_INST019_shadow_intermed_1;
R_E_CTRL_INST19_intermed_1 <= R.E.CTRL.INST( 19 );
V_M_Y31_shadow_intermed_1 <= V_M_Y31_shadow;
RIN_A_CTRL_INST19_intermed_1 <= RIN.A.CTRL.INST ( 19 );
RIN_M_Y31_intermed_1 <= RIN.M.Y( 31 );
RIN_M_Y31_intermed_2 <= RIN_M_Y31_intermed_1;
R_A_CTRL_INST19_intermed_1 <= R.A.CTRL.INST( 19 );
V_D_INST019_shadow_intermed_1 <= V_D_INST019_shadow;
V_D_INST019_shadow_intermed_2 <= V_D_INST019_shadow_intermed_1;
V_D_INST019_shadow_intermed_3 <= V_D_INST019_shadow_intermed_2;
R_M_Y31_intermed_1 <= R.M.Y( 31 );
RIN_D_INST019_intermed_1 <= RIN.D.INST( 0 )( 19 );
RIN_D_INST019_intermed_2 <= RIN_D_INST019_intermed_1;
RIN_D_INST019_intermed_3 <= RIN_D_INST019_intermed_2;
RIN_A_CTRL_INST19_intermed_1 <= RIN.A.CTRL.INST( 19 );
RIN_A_CTRL_INST19_intermed_2 <= RIN_A_CTRL_INST19_intermed_1;
RIN_E_CTRL_INST19_intermed_1 <= RIN.E.CTRL.INST ( 19 );
RIN_E_CTRL_INST19_intermed_1 <= RIN.E.CTRL.INST( 19 );
RIN_E_CTRL_INST19_intermed_2 <= RIN_E_CTRL_INST19_intermed_1;
V_A_CTRL_INST19_shadow_intermed_1 <= V_A_CTRL_INST19_shadow;
RIN_M_Y31_intermed_1 <= RIN.M.Y ( 31 );
V_M_Y31_shadow_intermed_1 <= V_M_Y31_shadow;
V_M_Y31_shadow_intermed_2 <= V_M_Y31_shadow_intermed_1;
V_M_Y31_shadow_intermed_1 <= V_M_Y31_shadow;
RIN_M_Y31_intermed_1 <= RIN.M.Y( 31 );
RIN_M_Y31_intermed_2 <= RIN_M_Y31_intermed_1;
R_M_Y31_intermed_1 <= R.M.Y( 31 );
R_M_Y31_intermed_2 <= R_M_Y31_intermed_1;
V_X_DEBUG_shadow_intermed_1 <= V_X_DEBUG_shadow;
RIN_X_DEBUG_intermed_1 <= RIN.X.DEBUG;
VDSU_CRDY2_shadow_intermed_1 <= VDSU_CRDY2_shadow;
VDSU_CRDY2_shadow_intermed_2 <= VDSU_CRDY2_shadow_intermed_1;
DSUIN_CRDY2_intermed_1 <= DSUIN.CRDY ( 2 );
VDSU_CRDY2_shadow_intermed_1 <= VDSU_CRDY2_shadow;
DSUIN_CRDY2_intermed_1 <= DSUIN.CRDY( 2 );
DSUIN_CRDY2_intermed_2 <= DSUIN_CRDY2_intermed_1;
DSUR_CRDY2_intermed_1 <= DSUR.CRDY( 2 );
VDSU_CRDY2_shadow_intermed_1 <= VDSU_CRDY2_shadow;
VDSU_CRDY2_shadow_intermed_2 <= VDSU_CRDY2_shadow_intermed_1;
DSUIN_CRDY2_intermed_1 <= DSUIN.CRDY ( 2 );
VDSU_CRDY2_shadow_intermed_1 <= VDSU_CRDY2_shadow;
DSUIN_CRDY2_intermed_1 <= DSUIN.CRDY( 2 );
DSUIN_CRDY2_intermed_2 <= DSUIN_CRDY2_intermed_1;
DSUR_CRDY2_intermed_1 <= DSUR.CRDY( 2 );
DSUR_CRDY2_intermed_2 <= DSUR_CRDY2_intermed_1;
VP_ERROR_shadow_intermed_1 <= VP_ERROR_shadow;
VP_ERROR_shadow_intermed_2 <= VP_ERROR_shadow_intermed_1;
RIN_X_NERROR_intermed_1 <= RIN.X.NERROR;
RPIN_ERROR_intermed_1 <= RPIN.ERROR;
RPIN_ERROR_intermed_2 <= RPIN_ERROR_intermed_1;
V_X_NERROR_shadow_intermed_1 <= V_X_NERROR_shadow;
RP_ERROR_intermed_1 <= RP.ERROR;
RIN_A_CTRL_PC31DOWNTO2_intermed_1 <= RIN.A.CTRL.PC( 31 DOWNTO 2 );
RIN_A_CTRL_PC31DOWNTO2_intermed_2 <= RIN_A_CTRL_PC31DOWNTO2_intermed_1;
R_A_CTRL_PC31DOWNTO2_intermed_1 <= R.A.CTRL.PC( 31 DOWNTO 2 );
R_A_CTRL_PC31DOWNTO2_intermed_2 <= R_A_CTRL_PC31DOWNTO2_intermed_1;
V_D_PC31DOWNTO2_shadow_intermed_1 <= V_D_PC31DOWNTO2_shadow;
V_D_PC31DOWNTO2_shadow_intermed_2 <= V_D_PC31DOWNTO2_shadow_intermed_1;
V_D_PC31DOWNTO2_shadow_intermed_3 <= V_D_PC31DOWNTO2_shadow_intermed_2;
RIN_D_PC31DOWNTO2_intermed_1 <= RIN.D.PC( 31 DOWNTO 2 );
RIN_D_PC31DOWNTO2_intermed_2 <= RIN_D_PC31DOWNTO2_intermed_1;
RIN_D_PC31DOWNTO2_intermed_3 <= RIN_D_PC31DOWNTO2_intermed_2;
RIN_A_CTRL_PC31DOWNTO2_intermed_1 <= RIN.A.CTRL.PC ( 31 DOWNTO 2 );
V_A_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO2_shadow;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO2_shadow;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_1;
R_D_PC31DOWNTO2_intermed_1 <= R.D.PC( 31 DOWNTO 2 );
R_D_PC31DOWNTO2_intermed_2 <= R_D_PC31DOWNTO2_intermed_1;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_E_CTRL_PC31DOWNTO2_shadow;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_1;
RIN_A_CTRL_PC31DOWNTO2_intermed_1 <= RIN.A.CTRL.PC( 31 DOWNTO 2 );
RIN_A_CTRL_PC31DOWNTO2_intermed_2 <= RIN_A_CTRL_PC31DOWNTO2_intermed_1;
RIN_A_CTRL_PC31DOWNTO2_intermed_3 <= RIN_A_CTRL_PC31DOWNTO2_intermed_2;
R_A_CTRL_PC31DOWNTO2_intermed_1 <= R.A.CTRL.PC( 31 DOWNTO 2 );
R_A_CTRL_PC31DOWNTO2_intermed_2 <= R_A_CTRL_PC31DOWNTO2_intermed_1;
R_A_CTRL_PC31DOWNTO2_intermed_1 <= R.A.CTRL.PC ( 31 DOWNTO 2 );
V_D_PC31DOWNTO2_shadow_intermed_1 <= V_D_PC31DOWNTO2_shadow;
V_D_PC31DOWNTO2_shadow_intermed_2 <= V_D_PC31DOWNTO2_shadow_intermed_1;
V_D_PC31DOWNTO2_shadow_intermed_3 <= V_D_PC31DOWNTO2_shadow_intermed_2;
V_D_PC31DOWNTO2_shadow_intermed_4 <= V_D_PC31DOWNTO2_shadow_intermed_3;
RIN_D_PC31DOWNTO2_intermed_1 <= RIN.D.PC( 31 DOWNTO 2 );
RIN_D_PC31DOWNTO2_intermed_2 <= RIN_D_PC31DOWNTO2_intermed_1;
RIN_D_PC31DOWNTO2_intermed_3 <= RIN_D_PC31DOWNTO2_intermed_2;
RIN_D_PC31DOWNTO2_intermed_4 <= RIN_D_PC31DOWNTO2_intermed_3;
RIN_E_CTRL_PC31DOWNTO2_intermed_1 <= RIN.E.CTRL.PC ( 31 DOWNTO 2 );
RIN_A_CTRL_PC31DOWNTO2_intermed_1 <= RIN.A.CTRL.PC ( 31 DOWNTO 2 );
RIN_A_CTRL_PC31DOWNTO2_intermed_2 <= RIN_A_CTRL_PC31DOWNTO2_intermed_1;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO2_shadow;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_1;
R_E_CTRL_PC31DOWNTO2_intermed_1 <= R.E.CTRL.PC( 31 DOWNTO 2 );
R_E_CTRL_PC31DOWNTO2_intermed_2 <= R_E_CTRL_PC31DOWNTO2_intermed_1;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO2_shadow;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_2;
R_D_PC31DOWNTO2_intermed_1 <= R.D.PC( 31 DOWNTO 2 );
R_D_PC31DOWNTO2_intermed_2 <= R_D_PC31DOWNTO2_intermed_1;
R_D_PC31DOWNTO2_intermed_3 <= R_D_PC31DOWNTO2_intermed_2;
RIN_E_CTRL_PC31DOWNTO2_intermed_1 <= RIN.E.CTRL.PC( 31 DOWNTO 2 );
RIN_E_CTRL_PC31DOWNTO2_intermed_2 <= RIN_E_CTRL_PC31DOWNTO2_intermed_1;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_E_CTRL_PC31DOWNTO2_shadow;
R_M_CTRL_PC31DOWNTO2_intermed_1 <= R.M.CTRL.PC( 31 DOWNTO 2 );
R_M_CTRL_PC31DOWNTO2_intermed_2 <= R_M_CTRL_PC31DOWNTO2_intermed_1;
RIN_M_CTRL_PC31DOWNTO2_intermed_1 <= RIN.M.CTRL.PC( 31 DOWNTO 2 );
RIN_M_CTRL_PC31DOWNTO2_intermed_2 <= RIN_M_CTRL_PC31DOWNTO2_intermed_1;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_E_CTRL_PC31DOWNTO2_shadow;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_2;
RIN_A_CTRL_PC31DOWNTO2_intermed_1 <= RIN.A.CTRL.PC( 31 DOWNTO 2 );
RIN_A_CTRL_PC31DOWNTO2_intermed_2 <= RIN_A_CTRL_PC31DOWNTO2_intermed_1;
RIN_A_CTRL_PC31DOWNTO2_intermed_3 <= RIN_A_CTRL_PC31DOWNTO2_intermed_2;
RIN_A_CTRL_PC31DOWNTO2_intermed_4 <= RIN_A_CTRL_PC31DOWNTO2_intermed_3;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_M_CTRL_PC31DOWNTO2_shadow;
R_A_CTRL_PC31DOWNTO2_intermed_1 <= R.A.CTRL.PC( 31 DOWNTO 2 );
R_A_CTRL_PC31DOWNTO2_intermed_2 <= R_A_CTRL_PC31DOWNTO2_intermed_1;
R_A_CTRL_PC31DOWNTO2_intermed_3 <= R_A_CTRL_PC31DOWNTO2_intermed_2;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_M_CTRL_PC31DOWNTO2_shadow;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_M_CTRL_PC31DOWNTO2_shadow_intermed_1;
R_A_CTRL_PC31DOWNTO2_intermed_1 <= R.A.CTRL.PC ( 31 DOWNTO 2 );
R_A_CTRL_PC31DOWNTO2_intermed_2 <= R_A_CTRL_PC31DOWNTO2_intermed_1;
R_E_CTRL_PC31DOWNTO2_intermed_1 <= R.E.CTRL.PC ( 31 DOWNTO 2 );
V_D_PC31DOWNTO2_shadow_intermed_1 <= V_D_PC31DOWNTO2_shadow;
V_D_PC31DOWNTO2_shadow_intermed_2 <= V_D_PC31DOWNTO2_shadow_intermed_1;
V_D_PC31DOWNTO2_shadow_intermed_3 <= V_D_PC31DOWNTO2_shadow_intermed_2;
V_D_PC31DOWNTO2_shadow_intermed_4 <= V_D_PC31DOWNTO2_shadow_intermed_3;
V_D_PC31DOWNTO2_shadow_intermed_5 <= V_D_PC31DOWNTO2_shadow_intermed_4;
RIN_D_PC31DOWNTO2_intermed_1 <= RIN.D.PC( 31 DOWNTO 2 );
RIN_D_PC31DOWNTO2_intermed_2 <= RIN_D_PC31DOWNTO2_intermed_1;
RIN_D_PC31DOWNTO2_intermed_3 <= RIN_D_PC31DOWNTO2_intermed_2;
RIN_D_PC31DOWNTO2_intermed_4 <= RIN_D_PC31DOWNTO2_intermed_3;
RIN_D_PC31DOWNTO2_intermed_5 <= RIN_D_PC31DOWNTO2_intermed_4;
RIN_E_CTRL_PC31DOWNTO2_intermed_1 <= RIN.E.CTRL.PC ( 31 DOWNTO 2 );
RIN_E_CTRL_PC31DOWNTO2_intermed_2 <= RIN_E_CTRL_PC31DOWNTO2_intermed_1;
RIN_A_CTRL_PC31DOWNTO2_intermed_1 <= RIN.A.CTRL.PC ( 31 DOWNTO 2 );
RIN_A_CTRL_PC31DOWNTO2_intermed_2 <= RIN_A_CTRL_PC31DOWNTO2_intermed_1;
RIN_A_CTRL_PC31DOWNTO2_intermed_3 <= RIN_A_CTRL_PC31DOWNTO2_intermed_2;
RIN_M_CTRL_PC31DOWNTO2_intermed_1 <= RIN.M.CTRL.PC ( 31 DOWNTO 2 );
V_A_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO2_shadow;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_2;
R_E_CTRL_PC31DOWNTO2_intermed_1 <= R.E.CTRL.PC( 31 DOWNTO 2 );
R_E_CTRL_PC31DOWNTO2_intermed_2 <= R_E_CTRL_PC31DOWNTO2_intermed_1;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO2_shadow;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_2;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_4 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_3;
R_D_PC31DOWNTO2_intermed_1 <= R.D.PC( 31 DOWNTO 2 );
R_D_PC31DOWNTO2_intermed_2 <= R_D_PC31DOWNTO2_intermed_1;
R_D_PC31DOWNTO2_intermed_3 <= R_D_PC31DOWNTO2_intermed_2;
R_D_PC31DOWNTO2_intermed_4 <= R_D_PC31DOWNTO2_intermed_3;
RIN_E_CTRL_PC31DOWNTO2_intermed_1 <= RIN.E.CTRL.PC( 31 DOWNTO 2 );
RIN_E_CTRL_PC31DOWNTO2_intermed_2 <= RIN_E_CTRL_PC31DOWNTO2_intermed_1;
RIN_E_CTRL_PC31DOWNTO2_intermed_3 <= RIN_E_CTRL_PC31DOWNTO2_intermed_2;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_E_CTRL_PC31DOWNTO2_shadow;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_X_RESULT6DOWNTO0_shadow_intermed_1 <= V_X_RESULT6DOWNTO0_shadow;
RIN_X_RESULT6DOWNTO0_intermed_1 <= RIN.X.RESULT( 6 DOWNTO 0 );
RIN_X_RESULT6DOWNTO0_intermed_2 <= RIN_X_RESULT6DOWNTO0_intermed_1;
R_X_RESULT6DOWNTO0_intermed_1 <= R.X.RESULT( 6 DOWNTO 0 );
V_X_DATA0_shadow_intermed_1 <= V_X_DATA0_shadow;
R_X_DATA0_intermed_1 <= R.X.DATA( 0 );
RIN_X_DATA0_intermed_1 <= RIN.X.DATA( 0 );
RIN_X_DATA0_intermed_2 <= RIN_X_DATA0_intermed_1;
R_M_CTRL_PC31DOWNTO2_intermed_1 <= R.M.CTRL.PC( 31 DOWNTO 2 );
RIN_M_CTRL_PC31DOWNTO2_intermed_1 <= RIN.M.CTRL.PC( 31 DOWNTO 2 );
RIN_M_CTRL_PC31DOWNTO2_intermed_2 <= RIN_M_CTRL_PC31DOWNTO2_intermed_1;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_E_CTRL_PC31DOWNTO2_shadow;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_2;
RIN_A_CTRL_PC31DOWNTO2_intermed_1 <= RIN.A.CTRL.PC( 31 DOWNTO 2 );
RIN_A_CTRL_PC31DOWNTO2_intermed_2 <= RIN_A_CTRL_PC31DOWNTO2_intermed_1;
RIN_A_CTRL_PC31DOWNTO2_intermed_3 <= RIN_A_CTRL_PC31DOWNTO2_intermed_2;
RIN_A_CTRL_PC31DOWNTO2_intermed_4 <= RIN_A_CTRL_PC31DOWNTO2_intermed_3;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_M_CTRL_PC31DOWNTO2_shadow;
R_A_CTRL_PC31DOWNTO2_intermed_1 <= R.A.CTRL.PC( 31 DOWNTO 2 );
R_A_CTRL_PC31DOWNTO2_intermed_2 <= R_A_CTRL_PC31DOWNTO2_intermed_1;
R_A_CTRL_PC31DOWNTO2_intermed_3 <= R_A_CTRL_PC31DOWNTO2_intermed_2;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_M_CTRL_PC31DOWNTO2_shadow;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_M_CTRL_PC31DOWNTO2_shadow_intermed_1;
R_A_CTRL_PC31DOWNTO2_intermed_1 <= R.A.CTRL.PC ( 31 DOWNTO 2 );
R_A_CTRL_PC31DOWNTO2_intermed_2 <= R_A_CTRL_PC31DOWNTO2_intermed_1;
R_E_CTRL_PC31DOWNTO2_intermed_1 <= R.E.CTRL.PC ( 31 DOWNTO 2 );
R_X_CTRL_PC31DOWNTO2_intermed_1 <= R.X.CTRL.PC( 31 DOWNTO 2 );
V_D_PC31DOWNTO2_shadow_intermed_1 <= V_D_PC31DOWNTO2_shadow;
V_D_PC31DOWNTO2_shadow_intermed_2 <= V_D_PC31DOWNTO2_shadow_intermed_1;
V_D_PC31DOWNTO2_shadow_intermed_3 <= V_D_PC31DOWNTO2_shadow_intermed_2;
V_D_PC31DOWNTO2_shadow_intermed_4 <= V_D_PC31DOWNTO2_shadow_intermed_3;
V_D_PC31DOWNTO2_shadow_intermed_5 <= V_D_PC31DOWNTO2_shadow_intermed_4;
RIN_D_PC31DOWNTO2_intermed_1 <= RIN.D.PC( 31 DOWNTO 2 );
RIN_D_PC31DOWNTO2_intermed_2 <= RIN_D_PC31DOWNTO2_intermed_1;
RIN_D_PC31DOWNTO2_intermed_3 <= RIN_D_PC31DOWNTO2_intermed_2;
RIN_D_PC31DOWNTO2_intermed_4 <= RIN_D_PC31DOWNTO2_intermed_3;
RIN_D_PC31DOWNTO2_intermed_5 <= RIN_D_PC31DOWNTO2_intermed_4;
RIN_E_CTRL_PC31DOWNTO2_intermed_1 <= RIN.E.CTRL.PC ( 31 DOWNTO 2 );
RIN_E_CTRL_PC31DOWNTO2_intermed_2 <= RIN_E_CTRL_PC31DOWNTO2_intermed_1;
RIN_A_CTRL_PC31DOWNTO2_intermed_1 <= RIN.A.CTRL.PC ( 31 DOWNTO 2 );
RIN_A_CTRL_PC31DOWNTO2_intermed_2 <= RIN_A_CTRL_PC31DOWNTO2_intermed_1;
RIN_A_CTRL_PC31DOWNTO2_intermed_3 <= RIN_A_CTRL_PC31DOWNTO2_intermed_2;
RIN_M_CTRL_PC31DOWNTO2_intermed_1 <= RIN.M.CTRL.PC ( 31 DOWNTO 2 );
RIN_X_CTRL_PC31DOWNTO2_intermed_1 <= RIN.X.CTRL.PC( 31 DOWNTO 2 );
RIN_X_CTRL_PC31DOWNTO2_intermed_2 <= RIN_X_CTRL_PC31DOWNTO2_intermed_1;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO2_shadow;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_2;
R_E_CTRL_PC31DOWNTO2_intermed_1 <= R.E.CTRL.PC( 31 DOWNTO 2 );
R_E_CTRL_PC31DOWNTO2_intermed_2 <= R_E_CTRL_PC31DOWNTO2_intermed_1;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO2_shadow;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_2;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_4 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_3;
R_D_PC31DOWNTO2_intermed_1 <= R.D.PC( 31 DOWNTO 2 );
R_D_PC31DOWNTO2_intermed_2 <= R_D_PC31DOWNTO2_intermed_1;
R_D_PC31DOWNTO2_intermed_3 <= R_D_PC31DOWNTO2_intermed_2;
R_D_PC31DOWNTO2_intermed_4 <= R_D_PC31DOWNTO2_intermed_3;
RIN_E_CTRL_PC31DOWNTO2_intermed_1 <= RIN.E.CTRL.PC( 31 DOWNTO 2 );
RIN_E_CTRL_PC31DOWNTO2_intermed_2 <= RIN_E_CTRL_PC31DOWNTO2_intermed_1;
RIN_E_CTRL_PC31DOWNTO2_intermed_3 <= RIN_E_CTRL_PC31DOWNTO2_intermed_2;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_E_CTRL_PC31DOWNTO2_shadow;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_X_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_X_CTRL_PC31DOWNTO2_shadow;
V_X_CTRL_TT3DOWNTO0_shadow_intermed_1 <= V_X_CTRL_TT3DOWNTO0_shadow;
V_X_CTRL_TT3DOWNTO0_shadow_intermed_2 <= V_X_CTRL_TT3DOWNTO0_shadow_intermed_1;
R_M_CTRL_TT3DOWNTO0_intermed_1 <= R.M.CTRL.TT( 3 DOWNTO 0 );
R_M_CTRL_TT3DOWNTO0_intermed_2 <= R_M_CTRL_TT3DOWNTO0_intermed_1;
V_M_CTRL_TT3DOWNTO0_shadow_intermed_1 <= V_M_CTRL_TT3DOWNTO0_shadow;
V_M_CTRL_TT3DOWNTO0_shadow_intermed_2 <= V_M_CTRL_TT3DOWNTO0_shadow_intermed_1;
V_M_CTRL_TT3DOWNTO0_shadow_intermed_3 <= V_M_CTRL_TT3DOWNTO0_shadow_intermed_2;
V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_1 <= V_X_RESULT6DOWNTO03DOWNTO0_shadow;
V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_2 <= V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_1;
V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_3 <= V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_2;
R_X_RESULT6DOWNTO03DOWNTO0_intermed_1 <= R.X.RESULT( 6 DOWNTO 0 )( 3 DOWNTO 0 );
R_X_RESULT6DOWNTO03DOWNTO0_intermed_2 <= R_X_RESULT6DOWNTO03DOWNTO0_intermed_1;
R_A_CTRL_TT3DOWNTO0_intermed_1 <= R.A.CTRL.TT( 3 DOWNTO 0 );
R_A_CTRL_TT3DOWNTO0_intermed_2 <= R_A_CTRL_TT3DOWNTO0_intermed_1;
R_A_CTRL_TT3DOWNTO0_intermed_3 <= R_A_CTRL_TT3DOWNTO0_intermed_2;
R_A_CTRL_TT3DOWNTO0_intermed_4 <= R_A_CTRL_TT3DOWNTO0_intermed_3;
RIN_A_CTRL_TT3DOWNTO0_intermed_1 <= RIN.A.CTRL.TT( 3 DOWNTO 0 );
RIN_A_CTRL_TT3DOWNTO0_intermed_2 <= RIN_A_CTRL_TT3DOWNTO0_intermed_1;
RIN_A_CTRL_TT3DOWNTO0_intermed_3 <= RIN_A_CTRL_TT3DOWNTO0_intermed_2;
RIN_A_CTRL_TT3DOWNTO0_intermed_4 <= RIN_A_CTRL_TT3DOWNTO0_intermed_3;
RIN_A_CTRL_TT3DOWNTO0_intermed_5 <= RIN_A_CTRL_TT3DOWNTO0_intermed_4;
RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_1 <= RIN.X.RESULT( 6 DOWNTO 0 )( 3 DOWNTO 0 );
RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_2 <= RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_1;
RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_3 <= RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_2;
V_A_CTRL_TT3DOWNTO0_shadow_intermed_1 <= V_A_CTRL_TT3DOWNTO0_shadow;
V_A_CTRL_TT3DOWNTO0_shadow_intermed_2 <= V_A_CTRL_TT3DOWNTO0_shadow_intermed_1;
V_A_CTRL_TT3DOWNTO0_shadow_intermed_3 <= V_A_CTRL_TT3DOWNTO0_shadow_intermed_2;
V_A_CTRL_TT3DOWNTO0_shadow_intermed_4 <= V_A_CTRL_TT3DOWNTO0_shadow_intermed_3;
V_A_CTRL_TT3DOWNTO0_shadow_intermed_5 <= V_A_CTRL_TT3DOWNTO0_shadow_intermed_4;
RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_1 <= RIN.X.RESULT ( 6 DOWNTO 0 )( 3 DOWNTO 0 );
RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_2 <= RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_1;
R_W_S_TT3DOWNTO0_intermed_1 <= R.W.S.TT( 3 DOWNTO 0 );
R_X_RESULT6DOWNTO03DOWNTO0_intermed_1 <= R.X.RESULT ( 6 DOWNTO 0 )( 3 DOWNTO 0 );
R_E_CTRL_TT3DOWNTO0_intermed_1 <= R.E.CTRL.TT( 3 DOWNTO 0 );
R_E_CTRL_TT3DOWNTO0_intermed_2 <= R_E_CTRL_TT3DOWNTO0_intermed_1;
R_E_CTRL_TT3DOWNTO0_intermed_3 <= R_E_CTRL_TT3DOWNTO0_intermed_2;
V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_1 <= V_X_RESULT6DOWNTO03DOWNTO0_shadow;
V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_2 <= V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_1;
RIN_W_S_TT3DOWNTO0_intermed_1 <= RIN.W.S.TT( 3 DOWNTO 0 );
RIN_W_S_TT3DOWNTO0_intermed_2 <= RIN_W_S_TT3DOWNTO0_intermed_1;
V_E_CTRL_TT3DOWNTO0_shadow_intermed_1 <= V_E_CTRL_TT3DOWNTO0_shadow;
V_E_CTRL_TT3DOWNTO0_shadow_intermed_2 <= V_E_CTRL_TT3DOWNTO0_shadow_intermed_1;
V_E_CTRL_TT3DOWNTO0_shadow_intermed_3 <= V_E_CTRL_TT3DOWNTO0_shadow_intermed_2;
V_E_CTRL_TT3DOWNTO0_shadow_intermed_4 <= V_E_CTRL_TT3DOWNTO0_shadow_intermed_3;
RIN_M_CTRL_TT3DOWNTO0_intermed_1 <= RIN.M.CTRL.TT( 3 DOWNTO 0 );
RIN_M_CTRL_TT3DOWNTO0_intermed_2 <= RIN_M_CTRL_TT3DOWNTO0_intermed_1;
RIN_M_CTRL_TT3DOWNTO0_intermed_3 <= RIN_M_CTRL_TT3DOWNTO0_intermed_2;
RIN_X_CTRL_TT3DOWNTO0_intermed_1 <= RIN.X.CTRL.TT( 3 DOWNTO 0 );
RIN_X_CTRL_TT3DOWNTO0_intermed_2 <= RIN_X_CTRL_TT3DOWNTO0_intermed_1;
V_W_S_TT3DOWNTO0_shadow_intermed_1 <= V_W_S_TT3DOWNTO0_shadow;
R_X_CTRL_TT3DOWNTO0_intermed_1 <= R.X.CTRL.TT( 3 DOWNTO 0 );
RIN_E_CTRL_TT3DOWNTO0_intermed_1 <= RIN.E.CTRL.TT( 3 DOWNTO 0 );
RIN_E_CTRL_TT3DOWNTO0_intermed_2 <= RIN_E_CTRL_TT3DOWNTO0_intermed_1;
RIN_E_CTRL_TT3DOWNTO0_intermed_3 <= RIN_E_CTRL_TT3DOWNTO0_intermed_2;
RIN_E_CTRL_TT3DOWNTO0_intermed_4 <= RIN_E_CTRL_TT3DOWNTO0_intermed_3;
XC_VECTT3DOWNTO0_shadow_intermed_1 <= XC_VECTT3DOWNTO0_shadow;
V_M_RESULT1DOWNTO0_shadow_intermed_1 <= V_M_RESULT1DOWNTO0_shadow;
RIN_M_RESULT1DOWNTO0_intermed_1 <= RIN.M.RESULT( 1 DOWNTO 0 );
RIN_M_RESULT1DOWNTO0_intermed_2 <= RIN_M_RESULT1DOWNTO0_intermed_1;
R_M_RESULT1DOWNTO0_intermed_1 <= R.M.RESULT( 1 DOWNTO 0 );
RIN_X_DATA031_intermed_1 <= RIN.X.DATA ( 0 )( 31 );
RIN_X_DATA031_intermed_2 <= RIN_X_DATA031_intermed_1;
V_X_DATA031_shadow_intermed_1 <= V_X_DATA031_shadow;
V_X_DATA031_shadow_intermed_1 <= V_X_DATA031_shadow;
RIN_X_DATA031_intermed_1 <= RIN.X.DATA( 0 )( 31 );
RIN_X_DATA031_intermed_2 <= RIN_X_DATA031_intermed_1;
R_X_DATA031_intermed_1 <= R.X.DATA( 0 )( 31 );
R_X_DATA031_intermed_1 <= R.X.DATA ( 0 )( 31 );
V_X_DATA031_shadow_intermed_1 <= V_X_DATA031_shadow;
RIN_X_DATA031_intermed_1 <= RIN.X.DATA( 0 )( 31 );
RIN_X_DATA031_intermed_2 <= RIN_X_DATA031_intermed_1;
R_X_DATA031_intermed_1 <= R.X.DATA( 0 )( 31 );
DE_INST19_shadow_intermed_1 <= DE_INST19_shadow;
DE_INST19_shadow_intermed_2 <= DE_INST19_shadow_intermed_1;
R_D_INST019_intermed_1 <= R.D.INST ( 0 )( 19 );
R_D_INST019_intermed_2 <= R_D_INST019_intermed_1;
RIN_D_INST019_intermed_1 <= RIN.D.INST ( 0 )( 19 );
RIN_D_INST019_intermed_2 <= RIN_D_INST019_intermed_1;
RIN_D_INST019_intermed_3 <= RIN_D_INST019_intermed_2;
V_A_CTRL_INST19_shadow_intermed_1 <= V_A_CTRL_INST19_shadow;
V_A_CTRL_INST19_shadow_intermed_2 <= V_A_CTRL_INST19_shadow_intermed_1;
R_D_INST019_intermed_1 <= R.D.INST( 0 )( 19 );
R_D_INST019_intermed_2 <= R_D_INST019_intermed_1;
R_D_INST019_intermed_3 <= R_D_INST019_intermed_2;
V_E_CTRL_INST19_shadow_intermed_1 <= V_E_CTRL_INST19_shadow;
V_D_INST019_shadow_intermed_1 <= V_D_INST019_shadow;
V_D_INST019_shadow_intermed_2 <= V_D_INST019_shadow_intermed_1;
V_D_INST019_shadow_intermed_3 <= V_D_INST019_shadow_intermed_2;
R_E_CTRL_INST19_intermed_1 <= R.E.CTRL.INST( 19 );
RIN_A_CTRL_INST19_intermed_1 <= RIN.A.CTRL.INST ( 19 );
R_A_CTRL_INST19_intermed_1 <= R.A.CTRL.INST( 19 );
V_D_INST019_shadow_intermed_1 <= V_D_INST019_shadow;
V_D_INST019_shadow_intermed_2 <= V_D_INST019_shadow_intermed_1;
V_D_INST019_shadow_intermed_3 <= V_D_INST019_shadow_intermed_2;
V_D_INST019_shadow_intermed_4 <= V_D_INST019_shadow_intermed_3;
RIN_D_INST019_intermed_1 <= RIN.D.INST( 0 )( 19 );
RIN_D_INST019_intermed_2 <= RIN_D_INST019_intermed_1;
RIN_D_INST019_intermed_3 <= RIN_D_INST019_intermed_2;
RIN_D_INST019_intermed_4 <= RIN_D_INST019_intermed_3;
RIN_A_CTRL_INST19_intermed_1 <= RIN.A.CTRL.INST( 19 );
RIN_A_CTRL_INST19_intermed_2 <= RIN_A_CTRL_INST19_intermed_1;
RIN_E_CTRL_INST19_intermed_1 <= RIN.E.CTRL.INST( 19 );
RIN_E_CTRL_INST19_intermed_2 <= RIN_E_CTRL_INST19_intermed_1;
V_A_CTRL_INST19_shadow_intermed_1 <= V_A_CTRL_INST19_shadow;
V_A_CTRL_INST20_shadow_intermed_1 <= V_A_CTRL_INST20_shadow;
R_D_INST020_intermed_1 <= R.D.INST ( 0 )( 20 );
R_D_INST020_intermed_2 <= R_D_INST020_intermed_1;
RIN_D_INST020_intermed_1 <= RIN.D.INST( 0 )( 20 );
RIN_D_INST020_intermed_2 <= RIN_D_INST020_intermed_1;
RIN_D_INST020_intermed_3 <= RIN_D_INST020_intermed_2;
RIN_D_INST020_intermed_4 <= RIN_D_INST020_intermed_3;
RIN_A_CTRL_INST20_intermed_1 <= RIN.A.CTRL.INST ( 20 );
V_D_INST020_shadow_intermed_1 <= V_D_INST020_shadow;
V_D_INST020_shadow_intermed_2 <= V_D_INST020_shadow_intermed_1;
V_D_INST020_shadow_intermed_3 <= V_D_INST020_shadow_intermed_2;
RIN_D_INST020_intermed_1 <= RIN.D.INST ( 0 )( 20 );
RIN_D_INST020_intermed_2 <= RIN_D_INST020_intermed_1;
RIN_D_INST020_intermed_3 <= RIN_D_INST020_intermed_2;
R_E_CTRL_INST20_intermed_1 <= R.E.CTRL.INST( 20 );
RIN_A_CTRL_INST20_intermed_1 <= RIN.A.CTRL.INST( 20 );
RIN_A_CTRL_INST20_intermed_2 <= RIN_A_CTRL_INST20_intermed_1;
V_D_INST020_shadow_intermed_1 <= V_D_INST020_shadow;
V_D_INST020_shadow_intermed_2 <= V_D_INST020_shadow_intermed_1;
V_D_INST020_shadow_intermed_3 <= V_D_INST020_shadow_intermed_2;
V_D_INST020_shadow_intermed_4 <= V_D_INST020_shadow_intermed_3;
R_D_INST020_intermed_1 <= R.D.INST( 0 )( 20 );
R_D_INST020_intermed_2 <= R_D_INST020_intermed_1;
R_D_INST020_intermed_3 <= R_D_INST020_intermed_2;
V_E_CTRL_INST20_shadow_intermed_1 <= V_E_CTRL_INST20_shadow;
DE_INST20_shadow_intermed_1 <= DE_INST20_shadow;
DE_INST20_shadow_intermed_2 <= DE_INST20_shadow_intermed_1;
V_A_CTRL_INST20_shadow_intermed_1 <= V_A_CTRL_INST20_shadow;
V_A_CTRL_INST20_shadow_intermed_2 <= V_A_CTRL_INST20_shadow_intermed_1;
RIN_E_CTRL_INST20_intermed_1 <= RIN.E.CTRL.INST( 20 );
RIN_E_CTRL_INST20_intermed_2 <= RIN_E_CTRL_INST20_intermed_1;
R_A_CTRL_INST20_intermed_1 <= R.A.CTRL.INST( 20 );
RIN_X_DATA00_intermed_1 <= RIN.X.DATA ( 0 )( 0 );
RIN_X_DATA00_intermed_2 <= RIN_X_DATA00_intermed_1;
V_X_DATA00_shadow_intermed_1 <= V_X_DATA00_shadow;
V_X_DATA00_shadow_intermed_1 <= V_X_DATA00_shadow;
R_X_DATA00_intermed_1 <= R.X.DATA ( 0 )( 0 );
RIN_X_DATA00_intermed_1 <= RIN.X.DATA( 0 )( 0 );
RIN_X_DATA00_intermed_2 <= RIN_X_DATA00_intermed_1;
R_X_DATA00_intermed_1 <= R.X.DATA( 0 )( 0 );
V_X_DATA00_shadow_intermed_1 <= V_X_DATA00_shadow;
RIN_X_DATA00_intermed_1 <= RIN.X.DATA( 0 )( 0 );
RIN_X_DATA00_intermed_2 <= RIN_X_DATA00_intermed_1;
R_X_DATA00_intermed_1 <= R.X.DATA( 0 )( 0 );
V_X_DATA04DOWNTO0_shadow_intermed_1 <= V_X_DATA04DOWNTO0_shadow;
R_X_DATA04DOWNTO0_intermed_1 <= R.X.DATA( 0 )( 4 DOWNTO 0 );
R_X_DATA04DOWNTO0_intermed_1 <= R.X.DATA ( 0 )( 4 DOWNTO 0 );
RIN_X_DATA04DOWNTO0_intermed_1 <= RIN.X.DATA ( 0 )( 4 DOWNTO 0 );
RIN_X_DATA04DOWNTO0_intermed_2 <= RIN_X_DATA04DOWNTO0_intermed_1;
RIN_X_DATA04DOWNTO0_intermed_1 <= RIN.X.DATA( 0 )( 4 DOWNTO 0 );
RIN_X_DATA04DOWNTO0_intermed_2 <= RIN_X_DATA04DOWNTO0_intermed_1;
V_X_DATA04DOWNTO0_shadow_intermed_1 <= V_X_DATA04DOWNTO0_shadow;
V_X_DATA04DOWNTO0_shadow_intermed_1 <= V_X_DATA04DOWNTO0_shadow;
R_X_DATA04DOWNTO0_intermed_1 <= R.X.DATA( 0 )( 4 DOWNTO 0 );
RIN_X_DATA04DOWNTO0_intermed_1 <= RIN.X.DATA( 0 )( 4 DOWNTO 0 );
RIN_X_DATA04DOWNTO0_intermed_2 <= RIN_X_DATA04DOWNTO0_intermed_1;
V_D_INST0_shadow_intermed_1 <= V_D_INST0_shadow;
R_D_INST0_intermed_1 <= R.D.INST( 0 );
RIN_D_INST0_intermed_1 <= RIN.D.INST( 0 );
RIN_D_INST0_intermed_2 <= RIN_D_INST0_intermed_1;
R_M_CTRL_PC31DOWNTO2_intermed_1 <= R.M.CTRL.PC( 31 DOWNTO 2 );
R_M_CTRL_PC31DOWNTO2_intermed_2 <= R_M_CTRL_PC31DOWNTO2_intermed_1;
R_M_CTRL_PC31DOWNTO2_intermed_3 <= R_M_CTRL_PC31DOWNTO2_intermed_2;
RIN_M_CTRL_PC31DOWNTO2_intermed_1 <= RIN.M.CTRL.PC( 31 DOWNTO 2 );
RIN_M_CTRL_PC31DOWNTO2_intermed_2 <= RIN_M_CTRL_PC31DOWNTO2_intermed_1;
RIN_M_CTRL_PC31DOWNTO2_intermed_3 <= RIN_M_CTRL_PC31DOWNTO2_intermed_2;
RIN_M_CTRL_PC31DOWNTO2_intermed_4 <= RIN_M_CTRL_PC31DOWNTO2_intermed_3;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_E_CTRL_PC31DOWNTO2_shadow;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_2;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_4 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_3;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_5 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_4;
RIN_A_CTRL_PC31DOWNTO2_intermed_1 <= RIN.A.CTRL.PC( 31 DOWNTO 2 );
RIN_A_CTRL_PC31DOWNTO2_intermed_2 <= RIN_A_CTRL_PC31DOWNTO2_intermed_1;
RIN_A_CTRL_PC31DOWNTO2_intermed_3 <= RIN_A_CTRL_PC31DOWNTO2_intermed_2;
RIN_A_CTRL_PC31DOWNTO2_intermed_4 <= RIN_A_CTRL_PC31DOWNTO2_intermed_3;
RIN_A_CTRL_PC31DOWNTO2_intermed_5 <= RIN_A_CTRL_PC31DOWNTO2_intermed_4;
RIN_A_CTRL_PC31DOWNTO2_intermed_6 <= RIN_A_CTRL_PC31DOWNTO2_intermed_5;
R_A_CTRL_PC31DOWNTO2_intermed_1 <= R.A.CTRL.PC( 31 DOWNTO 2 );
R_A_CTRL_PC31DOWNTO2_intermed_2 <= R_A_CTRL_PC31DOWNTO2_intermed_1;
R_A_CTRL_PC31DOWNTO2_intermed_3 <= R_A_CTRL_PC31DOWNTO2_intermed_2;
R_A_CTRL_PC31DOWNTO2_intermed_4 <= R_A_CTRL_PC31DOWNTO2_intermed_3;
R_A_CTRL_PC31DOWNTO2_intermed_5 <= R_A_CTRL_PC31DOWNTO2_intermed_4;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_M_CTRL_PC31DOWNTO2_shadow;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_M_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_M_CTRL_PC31DOWNTO2_shadow_intermed_2;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_4 <= V_M_CTRL_PC31DOWNTO2_shadow_intermed_3;
R_X_CTRL_PC31DOWNTO2_intermed_1 <= R.X.CTRL.PC( 31 DOWNTO 2 );
R_X_CTRL_PC31DOWNTO2_intermed_2 <= R_X_CTRL_PC31DOWNTO2_intermed_1;
V_D_PC31DOWNTO2_shadow_intermed_1 <= V_D_PC31DOWNTO2_shadow;
V_D_PC31DOWNTO2_shadow_intermed_2 <= V_D_PC31DOWNTO2_shadow_intermed_1;
V_D_PC31DOWNTO2_shadow_intermed_3 <= V_D_PC31DOWNTO2_shadow_intermed_2;
V_D_PC31DOWNTO2_shadow_intermed_4 <= V_D_PC31DOWNTO2_shadow_intermed_3;
V_D_PC31DOWNTO2_shadow_intermed_5 <= V_D_PC31DOWNTO2_shadow_intermed_4;
V_D_PC31DOWNTO2_shadow_intermed_6 <= V_D_PC31DOWNTO2_shadow_intermed_5;
V_D_PC31DOWNTO2_shadow_intermed_7 <= V_D_PC31DOWNTO2_shadow_intermed_6;
XC_TRAP_ADDRESS31DOWNTO2_shadow_intermed_1 <= XC_TRAP_ADDRESS31DOWNTO2_shadow;
RIN_D_PC31DOWNTO2_intermed_1 <= RIN.D.PC( 31 DOWNTO 2 );
RIN_D_PC31DOWNTO2_intermed_2 <= RIN_D_PC31DOWNTO2_intermed_1;
RIN_D_PC31DOWNTO2_intermed_3 <= RIN_D_PC31DOWNTO2_intermed_2;
RIN_D_PC31DOWNTO2_intermed_4 <= RIN_D_PC31DOWNTO2_intermed_3;
RIN_D_PC31DOWNTO2_intermed_5 <= RIN_D_PC31DOWNTO2_intermed_4;
RIN_D_PC31DOWNTO2_intermed_6 <= RIN_D_PC31DOWNTO2_intermed_5;
RIN_D_PC31DOWNTO2_intermed_7 <= RIN_D_PC31DOWNTO2_intermed_6;
EX_ADD_RES32DOWNTO332DOWNTO3_shadow_intermed_1 <= EX_ADD_RES32DOWNTO332DOWNTO3_shadow;
V_F_PC31DOWNTO2_shadow_intermed_1 <= V_F_PC31DOWNTO2_shadow;
RIN_F_PC31DOWNTO2_intermed_1 <= RIN.F.PC( 31 DOWNTO 2 );
RIN_F_PC31DOWNTO2_intermed_2 <= RIN_F_PC31DOWNTO2_intermed_1;
RIN_X_CTRL_PC31DOWNTO2_intermed_1 <= RIN.X.CTRL.PC( 31 DOWNTO 2 );
RIN_X_CTRL_PC31DOWNTO2_intermed_2 <= RIN_X_CTRL_PC31DOWNTO2_intermed_1;
RIN_X_CTRL_PC31DOWNTO2_intermed_3 <= RIN_X_CTRL_PC31DOWNTO2_intermed_2;
IRIN_ADDR31DOWNTO2_intermed_1 <= IRIN.ADDR( 31 DOWNTO 2 );
IRIN_ADDR31DOWNTO2_intermed_2 <= IRIN_ADDR31DOWNTO2_intermed_1;
R_E_CTRL_PC31DOWNTO2_intermed_1 <= R.E.CTRL.PC( 31 DOWNTO 2 );
R_E_CTRL_PC31DOWNTO2_intermed_2 <= R_E_CTRL_PC31DOWNTO2_intermed_1;
R_E_CTRL_PC31DOWNTO2_intermed_3 <= R_E_CTRL_PC31DOWNTO2_intermed_2;
R_E_CTRL_PC31DOWNTO2_intermed_4 <= R_E_CTRL_PC31DOWNTO2_intermed_3;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO2_shadow;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_2;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_4 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_3;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_5 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_4;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_6 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_5;
EX_JUMP_ADDRESS31DOWNTO2_shadow_intermed_1 <= EX_JUMP_ADDRESS31DOWNTO2_shadow;
R_D_PC31DOWNTO2_intermed_1 <= R.D.PC( 31 DOWNTO 2 );
R_D_PC31DOWNTO2_intermed_2 <= R_D_PC31DOWNTO2_intermed_1;
R_D_PC31DOWNTO2_intermed_3 <= R_D_PC31DOWNTO2_intermed_2;
R_D_PC31DOWNTO2_intermed_4 <= R_D_PC31DOWNTO2_intermed_3;
R_D_PC31DOWNTO2_intermed_5 <= R_D_PC31DOWNTO2_intermed_4;
R_D_PC31DOWNTO2_intermed_6 <= R_D_PC31DOWNTO2_intermed_5;
IR_ADDR31DOWNTO2_intermed_1 <= IR.ADDR( 31 DOWNTO 2 );
RIN_E_CTRL_PC31DOWNTO2_intermed_1 <= RIN.E.CTRL.PC( 31 DOWNTO 2 );
RIN_E_CTRL_PC31DOWNTO2_intermed_2 <= RIN_E_CTRL_PC31DOWNTO2_intermed_1;
RIN_E_CTRL_PC31DOWNTO2_intermed_3 <= RIN_E_CTRL_PC31DOWNTO2_intermed_2;
RIN_E_CTRL_PC31DOWNTO2_intermed_4 <= RIN_E_CTRL_PC31DOWNTO2_intermed_3;
RIN_E_CTRL_PC31DOWNTO2_intermed_5 <= RIN_E_CTRL_PC31DOWNTO2_intermed_4;
R_F_PC31DOWNTO2_intermed_1 <= R.F.PC( 31 DOWNTO 2 );
V_X_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_X_CTRL_PC31DOWNTO2_shadow;
V_X_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_X_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_X_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_X_CTRL_PC31DOWNTO2_shadow_intermed_2;
VIR_ADDR31DOWNTO2_shadow_intermed_1 <= VIR_ADDR31DOWNTO2_shadow;
VIR_ADDR31DOWNTO2_shadow_intermed_2 <= VIR_ADDR31DOWNTO2_shadow_intermed_1;
V_D_PC31DOWNTO2_shadow_intermed_1 <= V_D_PC31DOWNTO2_shadow;
RIN_D_PC31DOWNTO2_intermed_1 <= RIN.D.PC( 31 DOWNTO 2 );
RIN_D_PC31DOWNTO2_intermed_2 <= RIN_D_PC31DOWNTO2_intermed_1;
R_D_PC31DOWNTO2_intermed_1 <= R.D.PC( 31 DOWNTO 2 );
V_A_CTRL_INST24_shadow_intermed_1 <= V_A_CTRL_INST24_shadow;
V_A_CTRL_INST24_shadow_intermed_2 <= V_A_CTRL_INST24_shadow_intermed_1;
V_E_CTRL_INST24_shadow_intermed_1 <= V_E_CTRL_INST24_shadow;
DE_INST24_shadow_intermed_1 <= DE_INST24_shadow;
DE_INST24_shadow_intermed_2 <= DE_INST24_shadow_intermed_1;
R_A_CTRL_INST24_intermed_1 <= R.A.CTRL.INST( 24 );
RIN_A_CTRL_INST24_intermed_1 <= RIN.A.CTRL.INST ( 24 );
RIN_D_INST024_intermed_1 <= RIN.D.INST( 0 )( 24 );
RIN_D_INST024_intermed_2 <= RIN_D_INST024_intermed_1;
RIN_D_INST024_intermed_3 <= RIN_D_INST024_intermed_2;
RIN_D_INST024_intermed_4 <= RIN_D_INST024_intermed_3;
V_A_CTRL_INST24_shadow_intermed_1 <= V_A_CTRL_INST24_shadow;
RIN_D_INST024_intermed_1 <= RIN.D.INST ( 0 )( 24 );
RIN_D_INST024_intermed_2 <= RIN_D_INST024_intermed_1;
RIN_D_INST024_intermed_3 <= RIN_D_INST024_intermed_2;
V_D_INST024_shadow_intermed_1 <= V_D_INST024_shadow;
V_D_INST024_shadow_intermed_2 <= V_D_INST024_shadow_intermed_1;
V_D_INST024_shadow_intermed_3 <= V_D_INST024_shadow_intermed_2;
V_D_INST024_shadow_intermed_4 <= V_D_INST024_shadow_intermed_3;
RIN_A_CTRL_INST24_intermed_1 <= RIN.A.CTRL.INST( 24 );
RIN_A_CTRL_INST24_intermed_2 <= RIN_A_CTRL_INST24_intermed_1;
RIN_E_CTRL_INST24_intermed_1 <= RIN.E.CTRL.INST( 24 );
RIN_E_CTRL_INST24_intermed_2 <= RIN_E_CTRL_INST24_intermed_1;
R_D_INST024_intermed_1 <= R.D.INST ( 0 )( 24 );
R_D_INST024_intermed_2 <= R_D_INST024_intermed_1;
V_D_INST024_shadow_intermed_1 <= V_D_INST024_shadow;
V_D_INST024_shadow_intermed_2 <= V_D_INST024_shadow_intermed_1;
V_D_INST024_shadow_intermed_3 <= V_D_INST024_shadow_intermed_2;
R_D_INST024_intermed_1 <= R.D.INST( 0 )( 24 );
R_D_INST024_intermed_2 <= R_D_INST024_intermed_1;
R_D_INST024_intermed_3 <= R_D_INST024_intermed_2;
R_E_CTRL_INST24_intermed_1 <= R.E.CTRL.INST( 24 );
DE_INST19_shadow_intermed_1 <= DE_INST19_shadow;
R_D_INST019_intermed_1 <= R.D.INST ( 0 )( 19 );
RIN_D_INST019_intermed_1 <= RIN.D.INST ( 0 )( 19 );
RIN_D_INST019_intermed_2 <= RIN_D_INST019_intermed_1;
V_A_CTRL_INST19_shadow_intermed_1 <= V_A_CTRL_INST19_shadow;
R_D_INST019_intermed_1 <= R.D.INST( 0 )( 19 );
R_D_INST019_intermed_2 <= R_D_INST019_intermed_1;
V_D_INST019_shadow_intermed_1 <= V_D_INST019_shadow;
V_D_INST019_shadow_intermed_2 <= V_D_INST019_shadow_intermed_1;
R_A_CTRL_INST19_intermed_1 <= R.A.CTRL.INST( 19 );
V_D_INST019_shadow_intermed_1 <= V_D_INST019_shadow;
V_D_INST019_shadow_intermed_2 <= V_D_INST019_shadow_intermed_1;
V_D_INST019_shadow_intermed_3 <= V_D_INST019_shadow_intermed_2;
RIN_D_INST019_intermed_1 <= RIN.D.INST( 0 )( 19 );
RIN_D_INST019_intermed_2 <= RIN_D_INST019_intermed_1;
RIN_D_INST019_intermed_3 <= RIN_D_INST019_intermed_2;
RIN_A_CTRL_INST19_intermed_1 <= RIN.A.CTRL.INST( 19 );
RIN_A_CTRL_INST19_intermed_2 <= RIN_A_CTRL_INST19_intermed_1;
V_M_Y31_shadow_intermed_1 <= V_M_Y31_shadow;
RIN_M_Y31_intermed_1 <= RIN.M.Y( 31 );
RIN_M_Y31_intermed_2 <= RIN_M_Y31_intermed_1;
R_M_Y31_intermed_1 <= R.M.Y( 31 );
VDSU_CRDY2_shadow_intermed_1 <= VDSU_CRDY2_shadow;
DSUIN_CRDY2_intermed_1 <= DSUIN.CRDY( 2 );
DSUIN_CRDY2_intermed_2 <= DSUIN_CRDY2_intermed_1;
DSUR_CRDY2_intermed_1 <= DSUR.CRDY( 2 );
RIN_A_CTRL_PC31DOWNTO2_intermed_1 <= RIN.A.CTRL.PC( 31 DOWNTO 2 );
RIN_A_CTRL_PC31DOWNTO2_intermed_2 <= RIN_A_CTRL_PC31DOWNTO2_intermed_1;
R_A_CTRL_PC31DOWNTO2_intermed_1 <= R.A.CTRL.PC( 31 DOWNTO 2 );
V_D_PC31DOWNTO2_shadow_intermed_1 <= V_D_PC31DOWNTO2_shadow;
V_D_PC31DOWNTO2_shadow_intermed_2 <= V_D_PC31DOWNTO2_shadow_intermed_1;
RIN_D_PC31DOWNTO2_intermed_1 <= RIN.D.PC( 31 DOWNTO 2 );
RIN_D_PC31DOWNTO2_intermed_2 <= RIN_D_PC31DOWNTO2_intermed_1;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO2_shadow;
R_D_PC31DOWNTO2_intermed_1 <= R.D.PC( 31 DOWNTO 2 );
V_E_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_E_CTRL_PC31DOWNTO2_shadow;
RIN_A_CTRL_PC31DOWNTO2_intermed_1 <= RIN.A.CTRL.PC( 31 DOWNTO 2 );
RIN_A_CTRL_PC31DOWNTO2_intermed_2 <= RIN_A_CTRL_PC31DOWNTO2_intermed_1;
R_A_CTRL_PC31DOWNTO2_intermed_1 <= R.A.CTRL.PC( 31 DOWNTO 2 );
V_D_PC31DOWNTO2_shadow_intermed_1 <= V_D_PC31DOWNTO2_shadow;
V_D_PC31DOWNTO2_shadow_intermed_2 <= V_D_PC31DOWNTO2_shadow_intermed_1;
V_D_PC31DOWNTO2_shadow_intermed_3 <= V_D_PC31DOWNTO2_shadow_intermed_2;
RIN_D_PC31DOWNTO2_intermed_1 <= RIN.D.PC( 31 DOWNTO 2 );
RIN_D_PC31DOWNTO2_intermed_2 <= RIN_D_PC31DOWNTO2_intermed_1;
RIN_D_PC31DOWNTO2_intermed_3 <= RIN_D_PC31DOWNTO2_intermed_2;
RIN_A_CTRL_PC31DOWNTO2_intermed_1 <= RIN.A.CTRL.PC ( 31 DOWNTO 2 );
V_A_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO2_shadow;
R_E_CTRL_PC31DOWNTO2_intermed_1 <= R.E.CTRL.PC( 31 DOWNTO 2 );
V_A_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO2_shadow;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_1;
R_D_PC31DOWNTO2_intermed_1 <= R.D.PC( 31 DOWNTO 2 );
R_D_PC31DOWNTO2_intermed_2 <= R_D_PC31DOWNTO2_intermed_1;
RIN_E_CTRL_PC31DOWNTO2_intermed_1 <= RIN.E.CTRL.PC( 31 DOWNTO 2 );
RIN_E_CTRL_PC31DOWNTO2_intermed_2 <= RIN_E_CTRL_PC31DOWNTO2_intermed_1;
R_M_CTRL_PC31DOWNTO2_intermed_1 <= R.M.CTRL.PC( 31 DOWNTO 2 );
RIN_M_CTRL_PC31DOWNTO2_intermed_1 <= RIN.M.CTRL.PC( 31 DOWNTO 2 );
RIN_M_CTRL_PC31DOWNTO2_intermed_2 <= RIN_M_CTRL_PC31DOWNTO2_intermed_1;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_E_CTRL_PC31DOWNTO2_shadow;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_1;
RIN_A_CTRL_PC31DOWNTO2_intermed_1 <= RIN.A.CTRL.PC( 31 DOWNTO 2 );
RIN_A_CTRL_PC31DOWNTO2_intermed_2 <= RIN_A_CTRL_PC31DOWNTO2_intermed_1;
RIN_A_CTRL_PC31DOWNTO2_intermed_3 <= RIN_A_CTRL_PC31DOWNTO2_intermed_2;
R_A_CTRL_PC31DOWNTO2_intermed_1 <= R.A.CTRL.PC( 31 DOWNTO 2 );
R_A_CTRL_PC31DOWNTO2_intermed_2 <= R_A_CTRL_PC31DOWNTO2_intermed_1;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_M_CTRL_PC31DOWNTO2_shadow;
R_A_CTRL_PC31DOWNTO2_intermed_1 <= R.A.CTRL.PC ( 31 DOWNTO 2 );
V_D_PC31DOWNTO2_shadow_intermed_1 <= V_D_PC31DOWNTO2_shadow;
V_D_PC31DOWNTO2_shadow_intermed_2 <= V_D_PC31DOWNTO2_shadow_intermed_1;
V_D_PC31DOWNTO2_shadow_intermed_3 <= V_D_PC31DOWNTO2_shadow_intermed_2;
V_D_PC31DOWNTO2_shadow_intermed_4 <= V_D_PC31DOWNTO2_shadow_intermed_3;
RIN_D_PC31DOWNTO2_intermed_1 <= RIN.D.PC( 31 DOWNTO 2 );
RIN_D_PC31DOWNTO2_intermed_2 <= RIN_D_PC31DOWNTO2_intermed_1;
RIN_D_PC31DOWNTO2_intermed_3 <= RIN_D_PC31DOWNTO2_intermed_2;
RIN_D_PC31DOWNTO2_intermed_4 <= RIN_D_PC31DOWNTO2_intermed_3;
RIN_E_CTRL_PC31DOWNTO2_intermed_1 <= RIN.E.CTRL.PC ( 31 DOWNTO 2 );
RIN_A_CTRL_PC31DOWNTO2_intermed_1 <= RIN.A.CTRL.PC ( 31 DOWNTO 2 );
RIN_A_CTRL_PC31DOWNTO2_intermed_2 <= RIN_A_CTRL_PC31DOWNTO2_intermed_1;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO2_shadow;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_1;
R_E_CTRL_PC31DOWNTO2_intermed_1 <= R.E.CTRL.PC( 31 DOWNTO 2 );
V_A_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO2_shadow;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_2;
R_D_PC31DOWNTO2_intermed_1 <= R.D.PC( 31 DOWNTO 2 );
R_D_PC31DOWNTO2_intermed_2 <= R_D_PC31DOWNTO2_intermed_1;
R_D_PC31DOWNTO2_intermed_3 <= R_D_PC31DOWNTO2_intermed_2;
RIN_E_CTRL_PC31DOWNTO2_intermed_1 <= RIN.E.CTRL.PC( 31 DOWNTO 2 );
RIN_E_CTRL_PC31DOWNTO2_intermed_2 <= RIN_E_CTRL_PC31DOWNTO2_intermed_1;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_E_CTRL_PC31DOWNTO2_shadow;
R_D_INST04DOWNTO0_intermed_1 <= R.D.INST( 0 )( 4 DOWNTO 0 );
R_D_INST04DOWNTO0_intermed_2 <= R_D_INST04DOWNTO0_intermed_1;
V_D_INST04DOWNTO0_shadow_intermed_1 <= V_D_INST04DOWNTO0_shadow;
V_D_INST04DOWNTO0_shadow_intermed_2 <= V_D_INST04DOWNTO0_shadow_intermed_1;
RIN_D_INST04DOWNTO0_intermed_1 <= RIN.D.INST ( 0 )( 4 DOWNTO 0 );
V_D_INST04DOWNTO0_shadow_intermed_1 <= V_D_INST04DOWNTO0_shadow;
RIN_D_INST04DOWNTO0_intermed_1 <= RIN.D.INST( 0 )( 4 DOWNTO 0 );
RIN_D_INST04DOWNTO0_intermed_2 <= RIN_D_INST04DOWNTO0_intermed_1;
EX_JUMP_ADDRESS31DOWNTO12_shadow_intermed_1 <= EX_JUMP_ADDRESS31DOWNTO12_shadow;
EX_JUMP_ADDRESS31DOWNTO12_shadow_intermed_2 <= EX_JUMP_ADDRESS31DOWNTO12_shadow_intermed_1;
RIN_F_PC31DOWNTO12_intermed_1 <= RIN.F.PC ( 31 DOWNTO 12 );
RIN_A_CTRL_PC31DOWNTO12_intermed_1 <= RIN.A.CTRL.PC( 31 DOWNTO 12 );
RIN_A_CTRL_PC31DOWNTO12_intermed_2 <= RIN_A_CTRL_PC31DOWNTO12_intermed_1;
RIN_A_CTRL_PC31DOWNTO12_intermed_3 <= RIN_A_CTRL_PC31DOWNTO12_intermed_2;
RIN_A_CTRL_PC31DOWNTO12_intermed_4 <= RIN_A_CTRL_PC31DOWNTO12_intermed_3;
RIN_A_CTRL_PC31DOWNTO12_intermed_5 <= RIN_A_CTRL_PC31DOWNTO12_intermed_4;
RIN_A_CTRL_PC31DOWNTO12_intermed_6 <= RIN_A_CTRL_PC31DOWNTO12_intermed_5;
RIN_A_CTRL_PC31DOWNTO12_intermed_7 <= RIN_A_CTRL_PC31DOWNTO12_intermed_6;
RIN_E_CTRL_PC31DOWNTO12_intermed_1 <= RIN.E.CTRL.PC( 31 DOWNTO 12 );
RIN_E_CTRL_PC31DOWNTO12_intermed_2 <= RIN_E_CTRL_PC31DOWNTO12_intermed_1;
RIN_E_CTRL_PC31DOWNTO12_intermed_3 <= RIN_E_CTRL_PC31DOWNTO12_intermed_2;
RIN_E_CTRL_PC31DOWNTO12_intermed_4 <= RIN_E_CTRL_PC31DOWNTO12_intermed_3;
RIN_E_CTRL_PC31DOWNTO12_intermed_5 <= RIN_E_CTRL_PC31DOWNTO12_intermed_4;
RIN_E_CTRL_PC31DOWNTO12_intermed_6 <= RIN_E_CTRL_PC31DOWNTO12_intermed_5;
V_F_PC31DOWNTO12_shadow_intermed_1 <= V_F_PC31DOWNTO12_shadow;
V_F_PC31DOWNTO12_shadow_intermed_2 <= V_F_PC31DOWNTO12_shadow_intermed_1;
R_M_CTRL_PC31DOWNTO12_intermed_1 <= R.M.CTRL.PC( 31 DOWNTO 12 );
R_M_CTRL_PC31DOWNTO12_intermed_2 <= R_M_CTRL_PC31DOWNTO12_intermed_1;
R_M_CTRL_PC31DOWNTO12_intermed_3 <= R_M_CTRL_PC31DOWNTO12_intermed_2;
R_M_CTRL_PC31DOWNTO12_intermed_4 <= R_M_CTRL_PC31DOWNTO12_intermed_3;
IRIN_ADDR31DOWNTO12_intermed_1 <= IRIN.ADDR( 31 DOWNTO 12 );
IRIN_ADDR31DOWNTO12_intermed_2 <= IRIN_ADDR31DOWNTO12_intermed_1;
IRIN_ADDR31DOWNTO12_intermed_3 <= IRIN_ADDR31DOWNTO12_intermed_2;
V_X_CTRL_PC31DOWNTO12_shadow_intermed_1 <= V_X_CTRL_PC31DOWNTO12_shadow;
V_X_CTRL_PC31DOWNTO12_shadow_intermed_2 <= V_X_CTRL_PC31DOWNTO12_shadow_intermed_1;
V_X_CTRL_PC31DOWNTO12_shadow_intermed_3 <= V_X_CTRL_PC31DOWNTO12_shadow_intermed_2;
V_X_CTRL_PC31DOWNTO12_shadow_intermed_4 <= V_X_CTRL_PC31DOWNTO12_shadow_intermed_3;
EX_ADD_RES32DOWNTO332DOWNTO13_shadow_intermed_1 <= EX_ADD_RES32DOWNTO332DOWNTO13_shadow;
EX_ADD_RES32DOWNTO332DOWNTO13_shadow_intermed_2 <= EX_ADD_RES32DOWNTO332DOWNTO13_shadow_intermed_1;
XC_TRAP_ADDRESS31DOWNTO12_shadow_intermed_1 <= XC_TRAP_ADDRESS31DOWNTO12_shadow;
XC_TRAP_ADDRESS31DOWNTO12_shadow_intermed_2 <= XC_TRAP_ADDRESS31DOWNTO12_shadow_intermed_1;
R_F_PC31DOWNTO12_intermed_1 <= R.F.PC( 31 DOWNTO 12 );
R_F_PC31DOWNTO12_intermed_2 <= R_F_PC31DOWNTO12_intermed_1;
RIN_M_CTRL_PC31DOWNTO12_intermed_1 <= RIN.M.CTRL.PC( 31 DOWNTO 12 );
RIN_M_CTRL_PC31DOWNTO12_intermed_2 <= RIN_M_CTRL_PC31DOWNTO12_intermed_1;
RIN_M_CTRL_PC31DOWNTO12_intermed_3 <= RIN_M_CTRL_PC31DOWNTO12_intermed_2;
RIN_M_CTRL_PC31DOWNTO12_intermed_4 <= RIN_M_CTRL_PC31DOWNTO12_intermed_3;
RIN_M_CTRL_PC31DOWNTO12_intermed_5 <= RIN_M_CTRL_PC31DOWNTO12_intermed_4;
IR_ADDR31DOWNTO12_intermed_1 <= IR.ADDR( 31 DOWNTO 12 );
IR_ADDR31DOWNTO12_intermed_2 <= IR_ADDR31DOWNTO12_intermed_1;
R_X_CTRL_PC31DOWNTO12_intermed_1 <= R.X.CTRL.PC( 31 DOWNTO 12 );
R_X_CTRL_PC31DOWNTO12_intermed_2 <= R_X_CTRL_PC31DOWNTO12_intermed_1;
R_X_CTRL_PC31DOWNTO12_intermed_3 <= R_X_CTRL_PC31DOWNTO12_intermed_2;
V_D_PC31DOWNTO12_shadow_intermed_1 <= V_D_PC31DOWNTO12_shadow;
V_D_PC31DOWNTO12_shadow_intermed_2 <= V_D_PC31DOWNTO12_shadow_intermed_1;
V_D_PC31DOWNTO12_shadow_intermed_3 <= V_D_PC31DOWNTO12_shadow_intermed_2;
V_D_PC31DOWNTO12_shadow_intermed_4 <= V_D_PC31DOWNTO12_shadow_intermed_3;
V_D_PC31DOWNTO12_shadow_intermed_5 <= V_D_PC31DOWNTO12_shadow_intermed_4;
V_D_PC31DOWNTO12_shadow_intermed_6 <= V_D_PC31DOWNTO12_shadow_intermed_5;
V_D_PC31DOWNTO12_shadow_intermed_7 <= V_D_PC31DOWNTO12_shadow_intermed_6;
V_D_PC31DOWNTO12_shadow_intermed_8 <= V_D_PC31DOWNTO12_shadow_intermed_7;
V_A_CTRL_PC31DOWNTO12_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO12_shadow;
V_A_CTRL_PC31DOWNTO12_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO12_shadow_intermed_1;
V_A_CTRL_PC31DOWNTO12_shadow_intermed_3 <= V_A_CTRL_PC31DOWNTO12_shadow_intermed_2;
V_A_CTRL_PC31DOWNTO12_shadow_intermed_4 <= V_A_CTRL_PC31DOWNTO12_shadow_intermed_3;
V_A_CTRL_PC31DOWNTO12_shadow_intermed_5 <= V_A_CTRL_PC31DOWNTO12_shadow_intermed_4;
V_A_CTRL_PC31DOWNTO12_shadow_intermed_6 <= V_A_CTRL_PC31DOWNTO12_shadow_intermed_5;
V_A_CTRL_PC31DOWNTO12_shadow_intermed_7 <= V_A_CTRL_PC31DOWNTO12_shadow_intermed_6;
V_E_CTRL_PC31DOWNTO12_shadow_intermed_1 <= V_E_CTRL_PC31DOWNTO12_shadow;
V_E_CTRL_PC31DOWNTO12_shadow_intermed_2 <= V_E_CTRL_PC31DOWNTO12_shadow_intermed_1;
V_E_CTRL_PC31DOWNTO12_shadow_intermed_3 <= V_E_CTRL_PC31DOWNTO12_shadow_intermed_2;
V_E_CTRL_PC31DOWNTO12_shadow_intermed_4 <= V_E_CTRL_PC31DOWNTO12_shadow_intermed_3;
V_E_CTRL_PC31DOWNTO12_shadow_intermed_5 <= V_E_CTRL_PC31DOWNTO12_shadow_intermed_4;
V_E_CTRL_PC31DOWNTO12_shadow_intermed_6 <= V_E_CTRL_PC31DOWNTO12_shadow_intermed_5;
EX_ADD_RES32DOWNTO330DOWNTO11_shadow_intermed_1 <= EX_ADD_RES32DOWNTO330DOWNTO11_shadow;
EX_ADD_RES32DOWNTO330DOWNTO11_shadow_intermed_2 <= EX_ADD_RES32DOWNTO330DOWNTO11_shadow_intermed_1;
RIN_F_PC31DOWNTO12_intermed_1 <= RIN.F.PC( 31 DOWNTO 12 );
RIN_F_PC31DOWNTO12_intermed_2 <= RIN_F_PC31DOWNTO12_intermed_1;
R_D_PC31DOWNTO12_intermed_1 <= R.D.PC( 31 DOWNTO 12 );
R_D_PC31DOWNTO12_intermed_2 <= R_D_PC31DOWNTO12_intermed_1;
R_D_PC31DOWNTO12_intermed_3 <= R_D_PC31DOWNTO12_intermed_2;
R_D_PC31DOWNTO12_intermed_4 <= R_D_PC31DOWNTO12_intermed_3;
R_D_PC31DOWNTO12_intermed_5 <= R_D_PC31DOWNTO12_intermed_4;
R_D_PC31DOWNTO12_intermed_6 <= R_D_PC31DOWNTO12_intermed_5;
R_D_PC31DOWNTO12_intermed_7 <= R_D_PC31DOWNTO12_intermed_6;
R_A_CTRL_PC31DOWNTO12_intermed_1 <= R.A.CTRL.PC( 31 DOWNTO 12 );
R_A_CTRL_PC31DOWNTO12_intermed_2 <= R_A_CTRL_PC31DOWNTO12_intermed_1;
R_A_CTRL_PC31DOWNTO12_intermed_3 <= R_A_CTRL_PC31DOWNTO12_intermed_2;
R_A_CTRL_PC31DOWNTO12_intermed_4 <= R_A_CTRL_PC31DOWNTO12_intermed_3;
R_A_CTRL_PC31DOWNTO12_intermed_5 <= R_A_CTRL_PC31DOWNTO12_intermed_4;
R_A_CTRL_PC31DOWNTO12_intermed_6 <= R_A_CTRL_PC31DOWNTO12_intermed_5;
R_E_CTRL_PC31DOWNTO12_intermed_1 <= R.E.CTRL.PC( 31 DOWNTO 12 );
R_E_CTRL_PC31DOWNTO12_intermed_2 <= R_E_CTRL_PC31DOWNTO12_intermed_1;
R_E_CTRL_PC31DOWNTO12_intermed_3 <= R_E_CTRL_PC31DOWNTO12_intermed_2;
R_E_CTRL_PC31DOWNTO12_intermed_4 <= R_E_CTRL_PC31DOWNTO12_intermed_3;
R_E_CTRL_PC31DOWNTO12_intermed_5 <= R_E_CTRL_PC31DOWNTO12_intermed_4;
RIN_X_CTRL_PC31DOWNTO12_intermed_1 <= RIN.X.CTRL.PC( 31 DOWNTO 12 );
RIN_X_CTRL_PC31DOWNTO12_intermed_2 <= RIN_X_CTRL_PC31DOWNTO12_intermed_1;
RIN_X_CTRL_PC31DOWNTO12_intermed_3 <= RIN_X_CTRL_PC31DOWNTO12_intermed_2;
RIN_X_CTRL_PC31DOWNTO12_intermed_4 <= RIN_X_CTRL_PC31DOWNTO12_intermed_3;
RIN_D_PC31DOWNTO12_intermed_1 <= RIN.D.PC( 31 DOWNTO 12 );
RIN_D_PC31DOWNTO12_intermed_2 <= RIN_D_PC31DOWNTO12_intermed_1;
RIN_D_PC31DOWNTO12_intermed_3 <= RIN_D_PC31DOWNTO12_intermed_2;
RIN_D_PC31DOWNTO12_intermed_4 <= RIN_D_PC31DOWNTO12_intermed_3;
RIN_D_PC31DOWNTO12_intermed_5 <= RIN_D_PC31DOWNTO12_intermed_4;
RIN_D_PC31DOWNTO12_intermed_6 <= RIN_D_PC31DOWNTO12_intermed_5;
RIN_D_PC31DOWNTO12_intermed_7 <= RIN_D_PC31DOWNTO12_intermed_6;
RIN_D_PC31DOWNTO12_intermed_8 <= RIN_D_PC31DOWNTO12_intermed_7;
VIR_ADDR31DOWNTO12_shadow_intermed_1 <= VIR_ADDR31DOWNTO12_shadow;
VIR_ADDR31DOWNTO12_shadow_intermed_2 <= VIR_ADDR31DOWNTO12_shadow_intermed_1;
VIR_ADDR31DOWNTO12_shadow_intermed_3 <= VIR_ADDR31DOWNTO12_shadow_intermed_2;
V_F_PC31DOWNTO12_shadow_intermed_1 <= V_F_PC31DOWNTO12_shadow;
V_M_CTRL_PC31DOWNTO12_shadow_intermed_1 <= V_M_CTRL_PC31DOWNTO12_shadow;
V_M_CTRL_PC31DOWNTO12_shadow_intermed_2 <= V_M_CTRL_PC31DOWNTO12_shadow_intermed_1;
V_M_CTRL_PC31DOWNTO12_shadow_intermed_3 <= V_M_CTRL_PC31DOWNTO12_shadow_intermed_2;
V_M_CTRL_PC31DOWNTO12_shadow_intermed_4 <= V_M_CTRL_PC31DOWNTO12_shadow_intermed_3;
V_M_CTRL_PC31DOWNTO12_shadow_intermed_5 <= V_M_CTRL_PC31DOWNTO12_shadow_intermed_4;
RIN_X_DATA031_intermed_1 <= RIN.X.DATA ( 0 )( 31 );
V_X_DATA031_shadow_intermed_1 <= V_X_DATA031_shadow;
V_X_DATA031_shadow_intermed_1 <= V_X_DATA031_shadow;
V_X_DATA031_shadow_intermed_2 <= V_X_DATA031_shadow_intermed_1;
RIN_X_DATA031_intermed_1 <= RIN.X.DATA( 0 )( 31 );
RIN_X_DATA031_intermed_2 <= RIN_X_DATA031_intermed_1;
R_X_DATA031_intermed_1 <= R.X.DATA( 0 )( 31 );
R_X_DATA031_intermed_2 <= R_X_DATA031_intermed_1;
R_D_INST04DOWNTO0_intermed_1 <= R.D.INST( 0 )( 4 DOWNTO 0 );
V_D_INST04DOWNTO0_shadow_intermed_1 <= V_D_INST04DOWNTO0_shadow;
RIN_D_INST04DOWNTO0_intermed_1 <= RIN.D.INST( 0 )( 4 DOWNTO 0 );
RIN_D_INST04DOWNTO0_intermed_2 <= RIN_D_INST04DOWNTO0_intermed_1;
EX_JUMP_ADDRESS31DOWNTO12_shadow_intermed_1 <= EX_JUMP_ADDRESS31DOWNTO12_shadow;
RIN_A_CTRL_PC31DOWNTO12_intermed_1 <= RIN.A.CTRL.PC( 31 DOWNTO 12 );
RIN_A_CTRL_PC31DOWNTO12_intermed_2 <= RIN_A_CTRL_PC31DOWNTO12_intermed_1;
RIN_A_CTRL_PC31DOWNTO12_intermed_3 <= RIN_A_CTRL_PC31DOWNTO12_intermed_2;
RIN_A_CTRL_PC31DOWNTO12_intermed_4 <= RIN_A_CTRL_PC31DOWNTO12_intermed_3;
RIN_A_CTRL_PC31DOWNTO12_intermed_5 <= RIN_A_CTRL_PC31DOWNTO12_intermed_4;
RIN_A_CTRL_PC31DOWNTO12_intermed_6 <= RIN_A_CTRL_PC31DOWNTO12_intermed_5;
RIN_E_CTRL_PC31DOWNTO12_intermed_1 <= RIN.E.CTRL.PC( 31 DOWNTO 12 );
RIN_E_CTRL_PC31DOWNTO12_intermed_2 <= RIN_E_CTRL_PC31DOWNTO12_intermed_1;
RIN_E_CTRL_PC31DOWNTO12_intermed_3 <= RIN_E_CTRL_PC31DOWNTO12_intermed_2;
RIN_E_CTRL_PC31DOWNTO12_intermed_4 <= RIN_E_CTRL_PC31DOWNTO12_intermed_3;
RIN_E_CTRL_PC31DOWNTO12_intermed_5 <= RIN_E_CTRL_PC31DOWNTO12_intermed_4;
V_F_PC31DOWNTO12_shadow_intermed_1 <= V_F_PC31DOWNTO12_shadow;
R_M_CTRL_PC31DOWNTO12_intermed_1 <= R.M.CTRL.PC( 31 DOWNTO 12 );
R_M_CTRL_PC31DOWNTO12_intermed_2 <= R_M_CTRL_PC31DOWNTO12_intermed_1;
R_M_CTRL_PC31DOWNTO12_intermed_3 <= R_M_CTRL_PC31DOWNTO12_intermed_2;
IRIN_ADDR31DOWNTO12_intermed_1 <= IRIN.ADDR( 31 DOWNTO 12 );
IRIN_ADDR31DOWNTO12_intermed_2 <= IRIN_ADDR31DOWNTO12_intermed_1;
V_X_CTRL_PC31DOWNTO12_shadow_intermed_1 <= V_X_CTRL_PC31DOWNTO12_shadow;
V_X_CTRL_PC31DOWNTO12_shadow_intermed_2 <= V_X_CTRL_PC31DOWNTO12_shadow_intermed_1;
V_X_CTRL_PC31DOWNTO12_shadow_intermed_3 <= V_X_CTRL_PC31DOWNTO12_shadow_intermed_2;
EX_ADD_RES32DOWNTO332DOWNTO13_shadow_intermed_1 <= EX_ADD_RES32DOWNTO332DOWNTO13_shadow;
XC_TRAP_ADDRESS31DOWNTO12_shadow_intermed_1 <= XC_TRAP_ADDRESS31DOWNTO12_shadow;
R_F_PC31DOWNTO12_intermed_1 <= R.F.PC( 31 DOWNTO 12 );
RIN_M_CTRL_PC31DOWNTO12_intermed_1 <= RIN.M.CTRL.PC( 31 DOWNTO 12 );
RIN_M_CTRL_PC31DOWNTO12_intermed_2 <= RIN_M_CTRL_PC31DOWNTO12_intermed_1;
RIN_M_CTRL_PC31DOWNTO12_intermed_3 <= RIN_M_CTRL_PC31DOWNTO12_intermed_2;
RIN_M_CTRL_PC31DOWNTO12_intermed_4 <= RIN_M_CTRL_PC31DOWNTO12_intermed_3;
IR_ADDR31DOWNTO12_intermed_1 <= IR.ADDR( 31 DOWNTO 12 );
R_X_CTRL_PC31DOWNTO12_intermed_1 <= R.X.CTRL.PC( 31 DOWNTO 12 );
R_X_CTRL_PC31DOWNTO12_intermed_2 <= R_X_CTRL_PC31DOWNTO12_intermed_1;
V_D_PC31DOWNTO12_shadow_intermed_1 <= V_D_PC31DOWNTO12_shadow;
V_D_PC31DOWNTO12_shadow_intermed_2 <= V_D_PC31DOWNTO12_shadow_intermed_1;
V_D_PC31DOWNTO12_shadow_intermed_3 <= V_D_PC31DOWNTO12_shadow_intermed_2;
V_D_PC31DOWNTO12_shadow_intermed_4 <= V_D_PC31DOWNTO12_shadow_intermed_3;
V_D_PC31DOWNTO12_shadow_intermed_5 <= V_D_PC31DOWNTO12_shadow_intermed_4;
V_D_PC31DOWNTO12_shadow_intermed_6 <= V_D_PC31DOWNTO12_shadow_intermed_5;
V_D_PC31DOWNTO12_shadow_intermed_7 <= V_D_PC31DOWNTO12_shadow_intermed_6;
V_A_CTRL_PC31DOWNTO12_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO12_shadow;
V_A_CTRL_PC31DOWNTO12_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO12_shadow_intermed_1;
V_A_CTRL_PC31DOWNTO12_shadow_intermed_3 <= V_A_CTRL_PC31DOWNTO12_shadow_intermed_2;
V_A_CTRL_PC31DOWNTO12_shadow_intermed_4 <= V_A_CTRL_PC31DOWNTO12_shadow_intermed_3;
V_A_CTRL_PC31DOWNTO12_shadow_intermed_5 <= V_A_CTRL_PC31DOWNTO12_shadow_intermed_4;
V_A_CTRL_PC31DOWNTO12_shadow_intermed_6 <= V_A_CTRL_PC31DOWNTO12_shadow_intermed_5;
V_E_CTRL_PC31DOWNTO12_shadow_intermed_1 <= V_E_CTRL_PC31DOWNTO12_shadow;
V_E_CTRL_PC31DOWNTO12_shadow_intermed_2 <= V_E_CTRL_PC31DOWNTO12_shadow_intermed_1;
V_E_CTRL_PC31DOWNTO12_shadow_intermed_3 <= V_E_CTRL_PC31DOWNTO12_shadow_intermed_2;
V_E_CTRL_PC31DOWNTO12_shadow_intermed_4 <= V_E_CTRL_PC31DOWNTO12_shadow_intermed_3;
V_E_CTRL_PC31DOWNTO12_shadow_intermed_5 <= V_E_CTRL_PC31DOWNTO12_shadow_intermed_4;
EX_ADD_RES32DOWNTO330DOWNTO11_shadow_intermed_1 <= EX_ADD_RES32DOWNTO330DOWNTO11_shadow;
RIN_F_PC31DOWNTO12_intermed_1 <= RIN.F.PC( 31 DOWNTO 12 );
RIN_F_PC31DOWNTO12_intermed_2 <= RIN_F_PC31DOWNTO12_intermed_1;
R_D_PC31DOWNTO12_intermed_1 <= R.D.PC( 31 DOWNTO 12 );
R_D_PC31DOWNTO12_intermed_2 <= R_D_PC31DOWNTO12_intermed_1;
R_D_PC31DOWNTO12_intermed_3 <= R_D_PC31DOWNTO12_intermed_2;
R_D_PC31DOWNTO12_intermed_4 <= R_D_PC31DOWNTO12_intermed_3;
R_D_PC31DOWNTO12_intermed_5 <= R_D_PC31DOWNTO12_intermed_4;
R_D_PC31DOWNTO12_intermed_6 <= R_D_PC31DOWNTO12_intermed_5;
R_A_CTRL_PC31DOWNTO12_intermed_1 <= R.A.CTRL.PC( 31 DOWNTO 12 );
R_A_CTRL_PC31DOWNTO12_intermed_2 <= R_A_CTRL_PC31DOWNTO12_intermed_1;
R_A_CTRL_PC31DOWNTO12_intermed_3 <= R_A_CTRL_PC31DOWNTO12_intermed_2;
R_A_CTRL_PC31DOWNTO12_intermed_4 <= R_A_CTRL_PC31DOWNTO12_intermed_3;
R_A_CTRL_PC31DOWNTO12_intermed_5 <= R_A_CTRL_PC31DOWNTO12_intermed_4;
R_E_CTRL_PC31DOWNTO12_intermed_1 <= R.E.CTRL.PC( 31 DOWNTO 12 );
R_E_CTRL_PC31DOWNTO12_intermed_2 <= R_E_CTRL_PC31DOWNTO12_intermed_1;
R_E_CTRL_PC31DOWNTO12_intermed_3 <= R_E_CTRL_PC31DOWNTO12_intermed_2;
R_E_CTRL_PC31DOWNTO12_intermed_4 <= R_E_CTRL_PC31DOWNTO12_intermed_3;
RIN_X_CTRL_PC31DOWNTO12_intermed_1 <= RIN.X.CTRL.PC( 31 DOWNTO 12 );
RIN_X_CTRL_PC31DOWNTO12_intermed_2 <= RIN_X_CTRL_PC31DOWNTO12_intermed_1;
RIN_X_CTRL_PC31DOWNTO12_intermed_3 <= RIN_X_CTRL_PC31DOWNTO12_intermed_2;
RIN_D_PC31DOWNTO12_intermed_1 <= RIN.D.PC( 31 DOWNTO 12 );
RIN_D_PC31DOWNTO12_intermed_2 <= RIN_D_PC31DOWNTO12_intermed_1;
RIN_D_PC31DOWNTO12_intermed_3 <= RIN_D_PC31DOWNTO12_intermed_2;
RIN_D_PC31DOWNTO12_intermed_4 <= RIN_D_PC31DOWNTO12_intermed_3;
RIN_D_PC31DOWNTO12_intermed_5 <= RIN_D_PC31DOWNTO12_intermed_4;
RIN_D_PC31DOWNTO12_intermed_6 <= RIN_D_PC31DOWNTO12_intermed_5;
RIN_D_PC31DOWNTO12_intermed_7 <= RIN_D_PC31DOWNTO12_intermed_6;
VIR_ADDR31DOWNTO12_shadow_intermed_1 <= VIR_ADDR31DOWNTO12_shadow;
VIR_ADDR31DOWNTO12_shadow_intermed_2 <= VIR_ADDR31DOWNTO12_shadow_intermed_1;
V_M_CTRL_PC31DOWNTO12_shadow_intermed_1 <= V_M_CTRL_PC31DOWNTO12_shadow;
V_M_CTRL_PC31DOWNTO12_shadow_intermed_2 <= V_M_CTRL_PC31DOWNTO12_shadow_intermed_1;
V_M_CTRL_PC31DOWNTO12_shadow_intermed_3 <= V_M_CTRL_PC31DOWNTO12_shadow_intermed_2;
V_M_CTRL_PC31DOWNTO12_shadow_intermed_4 <= V_M_CTRL_PC31DOWNTO12_shadow_intermed_3;
V_X_DATA03_shadow_intermed_1 <= V_X_DATA03_shadow;
V_X_DATA03_shadow_intermed_2 <= V_X_DATA03_shadow_intermed_1;
V_X_DATA03_shadow_intermed_1 <= V_X_DATA03_shadow;
RIN_X_DATA03_intermed_1 <= RIN.X.DATA ( 0 )( 3 );
R_X_DATA03_intermed_1 <= R.X.DATA( 0 )( 3 );
R_X_DATA03_intermed_2 <= R_X_DATA03_intermed_1;
RIN_X_DATA03_intermed_1 <= RIN.X.DATA( 0 )( 3 );
RIN_X_DATA03_intermed_2 <= RIN_X_DATA03_intermed_1;
V_X_DATA03_shadow_intermed_1 <= V_X_DATA03_shadow;
R_X_DATA03_intermed_1 <= R.X.DATA( 0 )( 3 );
RIN_X_DATA03_intermed_1 <= RIN.X.DATA( 0 )( 3 );
RIN_X_DATA03_intermed_2 <= RIN_X_DATA03_intermed_1;
R_D_INST020_intermed_1 <= R.D.INST ( 0 )( 20 );
R_D_INST020_intermed_2 <= R_D_INST020_intermed_1;
V_A_CTRL_INST20_shadow_intermed_1 <= V_A_CTRL_INST20_shadow;
RIN_D_INST020_intermed_1 <= RIN.D.INST( 0 )( 20 );
RIN_D_INST020_intermed_2 <= RIN_D_INST020_intermed_1;
RIN_D_INST020_intermed_3 <= RIN_D_INST020_intermed_2;
RIN_D_INST020_intermed_4 <= RIN_D_INST020_intermed_3;
RIN_A_CTRL_INST20_intermed_1 <= RIN.A.CTRL.INST ( 20 );
V_D_INST020_shadow_intermed_1 <= V_D_INST020_shadow;
V_D_INST020_shadow_intermed_2 <= V_D_INST020_shadow_intermed_1;
V_D_INST020_shadow_intermed_3 <= V_D_INST020_shadow_intermed_2;
RIN_D_INST020_intermed_1 <= RIN.D.INST ( 0 )( 20 );
RIN_D_INST020_intermed_2 <= RIN_D_INST020_intermed_1;
RIN_D_INST020_intermed_3 <= RIN_D_INST020_intermed_2;
RIN_A_CTRL_INST20_intermed_1 <= RIN.A.CTRL.INST( 20 );
RIN_A_CTRL_INST20_intermed_2 <= RIN_A_CTRL_INST20_intermed_1;
V_D_INST020_shadow_intermed_1 <= V_D_INST020_shadow;
V_D_INST020_shadow_intermed_2 <= V_D_INST020_shadow_intermed_1;
V_D_INST020_shadow_intermed_3 <= V_D_INST020_shadow_intermed_2;
V_D_INST020_shadow_intermed_4 <= V_D_INST020_shadow_intermed_3;
R_D_INST020_intermed_1 <= R.D.INST( 0 )( 20 );
R_D_INST020_intermed_2 <= R_D_INST020_intermed_1;
R_D_INST020_intermed_3 <= R_D_INST020_intermed_2;
DE_INST20_shadow_intermed_1 <= DE_INST20_shadow;
DE_INST20_shadow_intermed_2 <= DE_INST20_shadow_intermed_1;
V_A_CTRL_INST20_shadow_intermed_1 <= V_A_CTRL_INST20_shadow;
V_A_CTRL_INST20_shadow_intermed_2 <= V_A_CTRL_INST20_shadow_intermed_1;
R_A_CTRL_INST20_intermed_1 <= R.A.CTRL.INST( 20 );
R_A_CTRL_INST20_intermed_2 <= R_A_CTRL_INST20_intermed_1;
RIN_X_DATA00_intermed_1 <= RIN.X.DATA ( 0 )( 0 );
V_X_DATA00_shadow_intermed_1 <= V_X_DATA00_shadow;
V_X_DATA00_shadow_intermed_1 <= V_X_DATA00_shadow;
V_X_DATA00_shadow_intermed_2 <= V_X_DATA00_shadow_intermed_1;
RIN_X_DATA00_intermed_1 <= RIN.X.DATA( 0 )( 0 );
RIN_X_DATA00_intermed_2 <= RIN_X_DATA00_intermed_1;
R_X_DATA00_intermed_1 <= R.X.DATA( 0 )( 0 );
R_X_DATA00_intermed_2 <= R_X_DATA00_intermed_1;
V_X_DATA04DOWNTO0_shadow_intermed_1 <= V_X_DATA04DOWNTO0_shadow;
V_X_DATA04DOWNTO0_shadow_intermed_2 <= V_X_DATA04DOWNTO0_shadow_intermed_1;
R_X_DATA04DOWNTO0_intermed_1 <= R.X.DATA( 0 )( 4 DOWNTO 0 );
R_X_DATA04DOWNTO0_intermed_2 <= R_X_DATA04DOWNTO0_intermed_1;
RIN_X_DATA04DOWNTO0_intermed_1 <= RIN.X.DATA( 0 )( 4 DOWNTO 0 );
RIN_X_DATA04DOWNTO0_intermed_2 <= RIN_X_DATA04DOWNTO0_intermed_1;
RIN_X_DATA04DOWNTO0_intermed_1 <= RIN.X.DATA ( 0 )( 4 DOWNTO 0 );
V_X_DATA04DOWNTO0_shadow_intermed_1 <= V_X_DATA04DOWNTO0_shadow;
V_A_CTRL_INST24_shadow_intermed_1 <= V_A_CTRL_INST24_shadow;
V_A_CTRL_INST24_shadow_intermed_2 <= V_A_CTRL_INST24_shadow_intermed_1;
DE_INST24_shadow_intermed_1 <= DE_INST24_shadow;
DE_INST24_shadow_intermed_2 <= DE_INST24_shadow_intermed_1;
R_A_CTRL_INST24_intermed_1 <= R.A.CTRL.INST( 24 );
R_A_CTRL_INST24_intermed_2 <= R_A_CTRL_INST24_intermed_1;
RIN_A_CTRL_INST24_intermed_1 <= RIN.A.CTRL.INST ( 24 );
RIN_D_INST024_intermed_1 <= RIN.D.INST( 0 )( 24 );
RIN_D_INST024_intermed_2 <= RIN_D_INST024_intermed_1;
RIN_D_INST024_intermed_3 <= RIN_D_INST024_intermed_2;
RIN_D_INST024_intermed_4 <= RIN_D_INST024_intermed_3;
V_A_CTRL_INST24_shadow_intermed_1 <= V_A_CTRL_INST24_shadow;
RIN_D_INST024_intermed_1 <= RIN.D.INST ( 0 )( 24 );
RIN_D_INST024_intermed_2 <= RIN_D_INST024_intermed_1;
RIN_D_INST024_intermed_3 <= RIN_D_INST024_intermed_2;
V_D_INST024_shadow_intermed_1 <= V_D_INST024_shadow;
V_D_INST024_shadow_intermed_2 <= V_D_INST024_shadow_intermed_1;
V_D_INST024_shadow_intermed_3 <= V_D_INST024_shadow_intermed_2;
V_D_INST024_shadow_intermed_4 <= V_D_INST024_shadow_intermed_3;
RIN_A_CTRL_INST24_intermed_1 <= RIN.A.CTRL.INST( 24 );
RIN_A_CTRL_INST24_intermed_2 <= RIN_A_CTRL_INST24_intermed_1;
R_D_INST024_intermed_1 <= R.D.INST ( 0 )( 24 );
R_D_INST024_intermed_2 <= R_D_INST024_intermed_1;
V_D_INST024_shadow_intermed_1 <= V_D_INST024_shadow;
V_D_INST024_shadow_intermed_2 <= V_D_INST024_shadow_intermed_1;
V_D_INST024_shadow_intermed_3 <= V_D_INST024_shadow_intermed_2;
R_D_INST024_intermed_1 <= R.D.INST( 0 )( 24 );
R_D_INST024_intermed_2 <= R_D_INST024_intermed_1;
R_D_INST024_intermed_3 <= R_D_INST024_intermed_2;
R_D_INST020_intermed_1 <= R.D.INST ( 0 )( 20 );
RIN_D_INST020_intermed_1 <= RIN.D.INST( 0 )( 20 );
RIN_D_INST020_intermed_2 <= RIN_D_INST020_intermed_1;
RIN_D_INST020_intermed_3 <= RIN_D_INST020_intermed_2;
V_D_INST020_shadow_intermed_1 <= V_D_INST020_shadow;
V_D_INST020_shadow_intermed_2 <= V_D_INST020_shadow_intermed_1;
RIN_D_INST020_intermed_1 <= RIN.D.INST ( 0 )( 20 );
RIN_D_INST020_intermed_2 <= RIN_D_INST020_intermed_1;
RIN_A_CTRL_INST20_intermed_1 <= RIN.A.CTRL.INST( 20 );
RIN_A_CTRL_INST20_intermed_2 <= RIN_A_CTRL_INST20_intermed_1;
V_D_INST020_shadow_intermed_1 <= V_D_INST020_shadow;
V_D_INST020_shadow_intermed_2 <= V_D_INST020_shadow_intermed_1;
V_D_INST020_shadow_intermed_3 <= V_D_INST020_shadow_intermed_2;
R_D_INST020_intermed_1 <= R.D.INST( 0 )( 20 );
R_D_INST020_intermed_2 <= R_D_INST020_intermed_1;
DE_INST20_shadow_intermed_1 <= DE_INST20_shadow;
V_A_CTRL_INST20_shadow_intermed_1 <= V_A_CTRL_INST20_shadow;
R_A_CTRL_INST20_intermed_1 <= R.A.CTRL.INST( 20 );
V_A_CTRL_INST24_shadow_intermed_1 <= V_A_CTRL_INST24_shadow;
DE_INST24_shadow_intermed_1 <= DE_INST24_shadow;
R_A_CTRL_INST24_intermed_1 <= R.A.CTRL.INST( 24 );
RIN_D_INST024_intermed_1 <= RIN.D.INST( 0 )( 24 );
RIN_D_INST024_intermed_2 <= RIN_D_INST024_intermed_1;
RIN_D_INST024_intermed_3 <= RIN_D_INST024_intermed_2;
RIN_D_INST024_intermed_1 <= RIN.D.INST ( 0 )( 24 );
RIN_D_INST024_intermed_2 <= RIN_D_INST024_intermed_1;
V_D_INST024_shadow_intermed_1 <= V_D_INST024_shadow;
V_D_INST024_shadow_intermed_2 <= V_D_INST024_shadow_intermed_1;
V_D_INST024_shadow_intermed_3 <= V_D_INST024_shadow_intermed_2;
RIN_A_CTRL_INST24_intermed_1 <= RIN.A.CTRL.INST( 24 );
RIN_A_CTRL_INST24_intermed_2 <= RIN_A_CTRL_INST24_intermed_1;
R_D_INST024_intermed_1 <= R.D.INST ( 0 )( 24 );
V_D_INST024_shadow_intermed_1 <= V_D_INST024_shadow;
V_D_INST024_shadow_intermed_2 <= V_D_INST024_shadow_intermed_1;
R_D_INST024_intermed_1 <= R.D.INST( 0 )( 24 );
R_D_INST024_intermed_2 <= R_D_INST024_intermed_1;
V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_1 <= V_X_RESULT6DOWNTO03DOWNTO0_shadow;
V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_2 <= V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_1;
R_X_RESULT6DOWNTO03DOWNTO0_intermed_1 <= R.X.RESULT( 6 DOWNTO 0 )( 3 DOWNTO 0 );
R_X_RESULT6DOWNTO03DOWNTO0_intermed_2 <= R_X_RESULT6DOWNTO03DOWNTO0_intermed_1;
RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_1 <= RIN.X.RESULT( 6 DOWNTO 0 )( 3 DOWNTO 0 );
RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_2 <= RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_1;
RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_1 <= RIN.X.RESULT ( 6 DOWNTO 0 )( 3 DOWNTO 0 );
V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_1 <= V_X_RESULT6DOWNTO03DOWNTO0_shadow;
RIN_D_INST019_intermed_1 <= RIN.D.INST ( 0 )( 19 );
R_D_INST019_intermed_1 <= R.D.INST( 0 )( 19 );
R_D_INST019_intermed_2 <= R_D_INST019_intermed_1;
V_D_INST019_shadow_intermed_1 <= V_D_INST019_shadow;
V_D_INST019_shadow_intermed_1 <= V_D_INST019_shadow;
V_D_INST019_shadow_intermed_2 <= V_D_INST019_shadow_intermed_1;
RIN_D_INST019_intermed_1 <= RIN.D.INST( 0 )( 19 );
RIN_D_INST019_intermed_2 <= RIN_D_INST019_intermed_1;
V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_1 <= V_X_RESULT6DOWNTO03DOWNTO0_shadow;
R_X_RESULT6DOWNTO03DOWNTO0_intermed_1 <= R.X.RESULT( 6 DOWNTO 0 )( 3 DOWNTO 0 );
RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_1 <= RIN.X.RESULT( 6 DOWNTO 0 )( 3 DOWNTO 0 );
RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_2 <= RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_1;
R_D_INST019_intermed_1 <= R.D.INST( 0 )( 19 );
V_D_INST019_shadow_intermed_1 <= V_D_INST019_shadow;
RIN_D_INST019_intermed_1 <= RIN.D.INST( 0 )( 19 );
RIN_D_INST019_intermed_2 <= RIN_D_INST019_intermed_1;
RIN_D_INST020_intermed_1 <= RIN.D.INST( 0 )( 20 );
RIN_D_INST020_intermed_2 <= RIN_D_INST020_intermed_1;
V_D_INST020_shadow_intermed_1 <= V_D_INST020_shadow;
RIN_D_INST020_intermed_1 <= RIN.D.INST ( 0 )( 20 );
V_D_INST020_shadow_intermed_1 <= V_D_INST020_shadow;
V_D_INST020_shadow_intermed_2 <= V_D_INST020_shadow_intermed_1;
R_D_INST020_intermed_1 <= R.D.INST( 0 )( 20 );
R_D_INST020_intermed_2 <= R_D_INST020_intermed_1;
RIN_D_INST024_intermed_1 <= RIN.D.INST( 0 )( 24 );
RIN_D_INST024_intermed_2 <= RIN_D_INST024_intermed_1;
RIN_D_INST024_intermed_1 <= RIN.D.INST ( 0 )( 24 );
V_D_INST024_shadow_intermed_1 <= V_D_INST024_shadow;
V_D_INST024_shadow_intermed_2 <= V_D_INST024_shadow_intermed_1;
V_D_INST024_shadow_intermed_1 <= V_D_INST024_shadow;
R_D_INST024_intermed_1 <= R.D.INST( 0 )( 24 );
R_D_INST024_intermed_2 <= R_D_INST024_intermed_1;
RIN_D_INST020_intermed_1 <= RIN.D.INST( 0 )( 20 );
RIN_D_INST020_intermed_2 <= RIN_D_INST020_intermed_1;
V_D_INST020_shadow_intermed_1 <= V_D_INST020_shadow;
R_D_INST020_intermed_1 <= R.D.INST( 0 )( 20 );
RIN_D_INST024_intermed_1 <= RIN.D.INST( 0 )( 24 );
RIN_D_INST024_intermed_2 <= RIN_D_INST024_intermed_1;
V_D_INST024_shadow_intermed_1 <= V_D_INST024_shadow;
R_D_INST024_intermed_1 <= R.D.INST( 0 )( 24 );
RIN_F_PC_intermed_1 <= RIN.F.PC;
EX_ADD_RES32DOWNTO3_shadow_intermed_1 <= EX_ADD_RES32DOWNTO3_shadow;
XC_TRAP_ADDRESS_shadow_intermed_1 <= XC_TRAP_ADDRESS_shadow;
EX_JUMP_ADDRESS_shadow_intermed_1 <= EX_JUMP_ADDRESS_shadow;
V_F_PC_shadow_intermed_1 <= V_F_PC_shadow;
RIN_A_RFE1_intermed_1 <= RIN.A.RFE1;
V_A_RFE1_shadow_intermed_1 <= V_A_RFE1_shadow;
RIN_A_RFE2_intermed_1 <= RIN.A.RFE2;
V_A_RFE2_shadow_intermed_1 <= V_A_RFE2_shadow;
RIN_D_INST0_intermed_1 <= RIN.D.INST ( 0 );
V_D_INST0_shadow_intermed_1 <= V_D_INST0_shadow;
V_D_INST0_shadow_intermed_2 <= V_D_INST0_shadow_intermed_1;
R_D_INST0_intermed_1 <= R.D.INST( 0 );
RIN_D_INST0_intermed_1 <= RIN.D.INST( 0 );
RIN_D_INST0_intermed_2 <= RIN_D_INST0_intermed_1;
V_D_INST0_shadow_intermed_1 <= V_D_INST0_shadow;
V_X_DATA0_shadow_intermed_1 <= V_X_DATA0_shadow;
V_X_DATA0_shadow_intermed_2 <= V_X_DATA0_shadow_intermed_1;
RIN_X_DATA0_intermed_1 <= RIN.X.DATA ( 0 );
V_E_OP1_shadow_intermed_1 <= V_E_OP1_shadow;
V_E_OP2_shadow_intermed_1 <= V_E_OP2_shadow;
RIN_E_OP2_intermed_1 <= RIN.E.OP2;
RIN_E_OP1_intermed_1 <= RIN.E.OP1;
V_X_DATA0_shadow_intermed_1 <= V_X_DATA0_shadow;
V_E_ALUCIN_shadow_intermed_1 <= V_E_ALUCIN_shadow;
R_X_DATA0_intermed_1 <= R.X.DATA( 0 );
RIN_E_ALUCIN_intermed_1 <= RIN.E.ALUCIN;
RIN_X_DATA0_intermed_1 <= RIN.X.DATA( 0 );
RIN_X_DATA0_intermed_2 <= RIN_X_DATA0_intermed_1;
RIN_X_DATA00_intermed_1 <= RIN.X.DATA ( 0 )( 0 );
RIN_X_DATA00_intermed_2 <= RIN_X_DATA00_intermed_1;
V_X_DATA00_shadow_intermed_1 <= V_X_DATA00_shadow;
V_X_DATA00_shadow_intermed_1 <= V_X_DATA00_shadow;
V_X_DATA00_shadow_intermed_2 <= V_X_DATA00_shadow_intermed_1;
V_E_YMSB_shadow_intermed_1 <= V_E_YMSB_shadow;
RIN_X_DATA00_intermed_1 <= RIN.X.DATA ( 0 ) ( 0 );
V_X_DATA00_shadow_intermed_1 <= V_X_DATA00_shadow;
V_X_DATA00_shadow_intermed_2 <= V_X_DATA00_shadow_intermed_1;
V_X_DATA00_shadow_intermed_3 <= V_X_DATA00_shadow_intermed_2;
R_X_DATA00_intermed_1 <= R.X.DATA ( 0 )( 0 );
RIN_X_DATA00_intermed_1 <= RIN.X.DATA( 0 )( 0 );
RIN_X_DATA00_intermed_2 <= RIN_X_DATA00_intermed_1;
RIN_X_DATA00_intermed_3 <= RIN_X_DATA00_intermed_2;
R_X_DATA00_intermed_1 <= R.X.DATA( 0 )( 0 );
R_X_DATA00_intermed_2 <= R_X_DATA00_intermed_1;
RIN_E_YMSB_intermed_1 <= RIN.E.YMSB;
V_X_DATA0_shadow_intermed_1 <= V_X_DATA0_shadow;
V_X_DATA0_shadow_intermed_2 <= V_X_DATA0_shadow_intermed_1;
RIN_X_DATA0_intermed_1 <= RIN.X.DATA ( 0 );
V_E_OP1_shadow_intermed_1 <= V_E_OP1_shadow;
RIN_E_OP1_intermed_1 <= RIN.E.OP1;
V_X_DATA0_shadow_intermed_1 <= V_X_DATA0_shadow;
R_X_DATA0_intermed_1 <= R.X.DATA( 0 );
RIN_X_DATA0_intermed_1 <= RIN.X.DATA( 0 );
RIN_X_DATA0_intermed_2 <= RIN_X_DATA0_intermed_1;
V_X_DATA0_shadow_intermed_1 <= V_X_DATA0_shadow;
V_X_DATA0_shadow_intermed_2 <= V_X_DATA0_shadow_intermed_1;
RIN_X_DATA0_intermed_1 <= RIN.X.DATA ( 0 );
V_E_OP2_shadow_intermed_1 <= V_E_OP2_shadow;
RIN_E_OP2_intermed_1 <= RIN.E.OP2;
V_X_DATA0_shadow_intermed_1 <= V_X_DATA0_shadow;
R_X_DATA0_intermed_1 <= R.X.DATA( 0 );
RIN_X_DATA0_intermed_1 <= RIN.X.DATA( 0 );
RIN_X_DATA0_intermed_2 <= RIN_X_DATA0_intermed_1;
RIN_X_DATA04DOWNTO0_intermed_1 <= RIN.X.DATA ( 0 ) ( 4 DOWNTO 0 );
V_X_DATA04DOWNTO0_shadow_intermed_1 <= V_X_DATA04DOWNTO0_shadow;
V_X_DATA04DOWNTO0_shadow_intermed_2 <= V_X_DATA04DOWNTO0_shadow_intermed_1;
V_X_DATA04DOWNTO0_shadow_intermed_3 <= V_X_DATA04DOWNTO0_shadow_intermed_2;
R_X_DATA04DOWNTO0_intermed_1 <= R.X.DATA( 0 )( 4 DOWNTO 0 );
R_X_DATA04DOWNTO0_intermed_2 <= R_X_DATA04DOWNTO0_intermed_1;
V_E_SHCNT_shadow_intermed_1 <= V_E_SHCNT_shadow;
R_X_DATA04DOWNTO0_intermed_1 <= R.X.DATA ( 0 )( 4 DOWNTO 0 );
V_X_DATA04DOWNTO0_shadow_intermed_1 <= V_X_DATA04DOWNTO0_shadow;
RIN_X_DATA04DOWNTO0_intermed_1 <= RIN.X.DATA( 0 )( 4 DOWNTO 0 );
RIN_X_DATA04DOWNTO0_intermed_2 <= RIN_X_DATA04DOWNTO0_intermed_1;
RIN_X_DATA04DOWNTO0_intermed_3 <= RIN_X_DATA04DOWNTO0_intermed_2;
RIN_X_DATA04DOWNTO0_intermed_1 <= RIN.X.DATA ( 0 )( 4 DOWNTO 0 );
RIN_X_DATA04DOWNTO0_intermed_2 <= RIN_X_DATA04DOWNTO0_intermed_1;
RIN_E_SHCNT_intermed_1 <= RIN.E.SHCNT;
V_X_DATA04DOWNTO0_shadow_intermed_1 <= V_X_DATA04DOWNTO0_shadow;
V_X_DATA04DOWNTO0_shadow_intermed_2 <= V_X_DATA04DOWNTO0_shadow_intermed_1;
RIN_X_DATA031_intermed_1 <= RIN.X.DATA ( 0 )( 31 );
RIN_X_DATA031_intermed_2 <= RIN_X_DATA031_intermed_1;
R_D_INST020_intermed_1 <= R.D.INST ( 0 )( 20 );
R_D_INST020_intermed_2 <= R_D_INST020_intermed_1;
V_A_CTRL_INST19_shadow_intermed_1 <= V_A_CTRL_INST19_shadow;
V_A_CTRL_INST19_shadow_intermed_2 <= V_A_CTRL_INST19_shadow_intermed_1;
V_A_CTRL_INST19_shadow_intermed_3 <= V_A_CTRL_INST19_shadow_intermed_2;
RIN_D_INST020_intermed_1 <= RIN.D.INST( 0 )( 20 );
RIN_D_INST020_intermed_2 <= RIN_D_INST020_intermed_1;
RIN_D_INST020_intermed_3 <= RIN_D_INST020_intermed_2;
RIN_D_INST020_intermed_4 <= RIN_D_INST020_intermed_3;
RIN_A_CTRL_INST20_intermed_1 <= RIN.A.CTRL.INST ( 20 );
RIN_A_CTRL_INST20_intermed_2 <= RIN_A_CTRL_INST20_intermed_1;
V_X_DATA031_shadow_intermed_1 <= V_X_DATA031_shadow;
V_X_DATA031_shadow_intermed_2 <= V_X_DATA031_shadow_intermed_1;
V_X_DATA031_shadow_intermed_1 <= V_X_DATA031_shadow;
V_X_DATA031_shadow_intermed_2 <= V_X_DATA031_shadow_intermed_1;
V_X_DATA031_shadow_intermed_3 <= V_X_DATA031_shadow_intermed_2;
R_D_INST019_intermed_1 <= R.D.INST( 0 )( 19 );
R_D_INST019_intermed_2 <= R_D_INST019_intermed_1;
R_D_INST019_intermed_3 <= R_D_INST019_intermed_2;
RIN_X_DATA031_intermed_1 <= RIN.X.DATA( 0 )( 31 );
RIN_X_DATA031_intermed_2 <= RIN_X_DATA031_intermed_1;
RIN_X_DATA031_intermed_3 <= RIN_X_DATA031_intermed_2;
V_E_CTRL_INST19_shadow_intermed_1 <= V_E_CTRL_INST19_shadow;
V_E_CTRL_INST19_shadow_intermed_2 <= V_E_CTRL_INST19_shadow_intermed_1;
RIN_A_CTRL_INST19_intermed_1 <= RIN.A.CTRL.INST ( 19 );
RIN_A_CTRL_INST19_intermed_2 <= RIN_A_CTRL_INST19_intermed_1;
RIN_D_INST020_intermed_1 <= RIN.D.INST ( 0 )( 20 );
RIN_D_INST020_intermed_2 <= RIN_D_INST020_intermed_1;
RIN_D_INST020_intermed_3 <= RIN_D_INST020_intermed_2;
R_A_CTRL_INST20_intermed_1 <= R.A.CTRL.INST ( 20 );
RIN_A_CTRL_INST20_intermed_1 <= RIN.A.CTRL.INST( 20 );
RIN_A_CTRL_INST20_intermed_2 <= RIN_A_CTRL_INST20_intermed_1;
RIN_A_CTRL_INST20_intermed_3 <= RIN_A_CTRL_INST20_intermed_2;
V_D_INST019_shadow_intermed_1 <= V_D_INST019_shadow;
V_D_INST019_shadow_intermed_2 <= V_D_INST019_shadow_intermed_1;
V_D_INST019_shadow_intermed_3 <= V_D_INST019_shadow_intermed_2;
V_D_INST019_shadow_intermed_4 <= V_D_INST019_shadow_intermed_3;
V_E_CTRL_INST20_shadow_intermed_1 <= V_E_CTRL_INST20_shadow;
V_E_CTRL_INST20_shadow_intermed_2 <= V_E_CTRL_INST20_shadow_intermed_1;
V_E_CTRL_INST20_shadow_intermed_1 <= V_E_CTRL_INST20_shadow;
RIN_A_CTRL_INST19_intermed_1 <= RIN.A.CTRL.INST( 19 );
RIN_A_CTRL_INST19_intermed_2 <= RIN_A_CTRL_INST19_intermed_1;
RIN_A_CTRL_INST19_intermed_3 <= RIN_A_CTRL_INST19_intermed_2;
RIN_E_CTRL_INST19_intermed_1 <= RIN.E.CTRL.INST ( 19 );
V_A_CTRL_INST20_shadow_intermed_1 <= V_A_CTRL_INST20_shadow;
V_A_CTRL_INST20_shadow_intermed_2 <= V_A_CTRL_INST20_shadow_intermed_1;
V_A_CTRL_INST20_shadow_intermed_3 <= V_A_CTRL_INST20_shadow_intermed_2;
RIN_E_SARI_intermed_1 <= RIN.E.SARI;
RIN_E_CTRL_INST20_intermed_1 <= RIN.E.CTRL.INST( 20 );
RIN_E_CTRL_INST20_intermed_2 <= RIN_E_CTRL_INST20_intermed_1;
RIN_E_CTRL_INST19_intermed_1 <= RIN.E.CTRL.INST( 19 );
RIN_E_CTRL_INST19_intermed_2 <= RIN_E_CTRL_INST19_intermed_1;
DE_INST19_shadow_intermed_1 <= DE_INST19_shadow;
DE_INST19_shadow_intermed_2 <= DE_INST19_shadow_intermed_1;
V_A_CTRL_INST20_shadow_intermed_1 <= V_A_CTRL_INST20_shadow;
V_A_CTRL_INST20_shadow_intermed_2 <= V_A_CTRL_INST20_shadow_intermed_1;
R_D_INST019_intermed_1 <= R.D.INST ( 0 )( 19 );
R_D_INST019_intermed_2 <= R_D_INST019_intermed_1;
RIN_D_INST019_intermed_1 <= RIN.D.INST ( 0 )( 19 );
RIN_D_INST019_intermed_2 <= RIN_D_INST019_intermed_1;
RIN_D_INST019_intermed_3 <= RIN_D_INST019_intermed_2;
V_E_CTRL_INST19_shadow_intermed_1 <= V_E_CTRL_INST19_shadow;
V_D_INST020_shadow_intermed_1 <= V_D_INST020_shadow;
V_D_INST020_shadow_intermed_2 <= V_D_INST020_shadow_intermed_1;
V_D_INST020_shadow_intermed_3 <= V_D_INST020_shadow_intermed_2;
V_D_INST019_shadow_intermed_1 <= V_D_INST019_shadow;
V_D_INST019_shadow_intermed_2 <= V_D_INST019_shadow_intermed_1;
V_D_INST019_shadow_intermed_3 <= V_D_INST019_shadow_intermed_2;
V_E_SARI_shadow_intermed_1 <= V_E_SARI_shadow;
RIN_X_DATA031_intermed_1 <= RIN.X.DATA ( 0 ) ( 31 );
R_E_CTRL_INST19_intermed_1 <= R.E.CTRL.INST( 19 );
R_X_DATA031_intermed_1 <= R.X.DATA( 0 )( 31 );
R_X_DATA031_intermed_2 <= R_X_DATA031_intermed_1;
RIN_E_CTRL_INST20_intermed_1 <= RIN.E.CTRL.INST ( 20 );
R_E_CTRL_INST20_intermed_1 <= R.E.CTRL.INST( 20 );
R_A_CTRL_INST19_intermed_1 <= R.A.CTRL.INST( 19 );
R_A_CTRL_INST19_intermed_2 <= R_A_CTRL_INST19_intermed_1;
V_D_INST020_shadow_intermed_1 <= V_D_INST020_shadow;
V_D_INST020_shadow_intermed_2 <= V_D_INST020_shadow_intermed_1;
V_D_INST020_shadow_intermed_3 <= V_D_INST020_shadow_intermed_2;
V_D_INST020_shadow_intermed_4 <= V_D_INST020_shadow_intermed_3;
RIN_D_INST019_intermed_1 <= RIN.D.INST( 0 )( 19 );
RIN_D_INST019_intermed_2 <= RIN_D_INST019_intermed_1;
RIN_D_INST019_intermed_3 <= RIN_D_INST019_intermed_2;
RIN_D_INST019_intermed_4 <= RIN_D_INST019_intermed_3;
R_D_INST020_intermed_1 <= R.D.INST( 0 )( 20 );
R_D_INST020_intermed_2 <= R_D_INST020_intermed_1;
R_D_INST020_intermed_3 <= R_D_INST020_intermed_2;
R_A_CTRL_INST19_intermed_1 <= R.A.CTRL.INST ( 19 );
DE_INST20_shadow_intermed_1 <= DE_INST20_shadow;
DE_INST20_shadow_intermed_2 <= DE_INST20_shadow_intermed_1;
R_X_DATA031_intermed_1 <= R.X.DATA ( 0 )( 31 );
V_X_DATA031_shadow_intermed_1 <= V_X_DATA031_shadow;
V_A_CTRL_INST19_shadow_intermed_1 <= V_A_CTRL_INST19_shadow;
V_A_CTRL_INST19_shadow_intermed_2 <= V_A_CTRL_INST19_shadow_intermed_1;
R_A_CTRL_INST20_intermed_1 <= R.A.CTRL.INST( 20 );
R_A_CTRL_INST20_intermed_2 <= R_A_CTRL_INST20_intermed_1;
RIN_M_DCI_SIGNED_intermed_1 <= RIN.M.DCI.SIGNED;
RIN_M_DCI_SIGNED_intermed_2 <= RIN_M_DCI_SIGNED_intermed_1;
R_M_DCI_SIGNED_intermed_1 <= R.M.DCI.SIGNED;
RIN_X_DCI_SIGNED_intermed_1 <= RIN.X.DCI.SIGNED;
V_M_DCI_SIGNED_shadow_intermed_1 <= V_M_DCI_SIGNED_shadow;
V_M_DCI_SIGNED_shadow_intermed_2 <= V_M_DCI_SIGNED_shadow_intermed_1;
V_X_DCI_SIGNED_shadow_intermed_1 <= V_X_DCI_SIGNED_shadow;
V_M_DCI_SIZE_shadow_intermed_1 <= V_M_DCI_SIZE_shadow;
V_M_DCI_SIZE_shadow_intermed_2 <= V_M_DCI_SIZE_shadow_intermed_1;
R_M_DCI_SIZE_intermed_1 <= R.M.DCI.SIZE;
RIN_X_DCI_SIZE_intermed_1 <= RIN.X.DCI.SIZE;
RIN_M_DCI_SIZE_intermed_1 <= RIN.M.DCI.SIZE;
RIN_M_DCI_SIZE_intermed_2 <= RIN_M_DCI_SIZE_intermed_1;
V_X_DCI_SIZE_shadow_intermed_1 <= V_X_DCI_SIZE_shadow;
V_M_RESULT1DOWNTO0_shadow_intermed_1 <= V_M_RESULT1DOWNTO0_shadow;
V_M_RESULT1DOWNTO0_shadow_intermed_2 <= V_M_RESULT1DOWNTO0_shadow_intermed_1;
V_M_RESULT1DOWNTO0_shadow_intermed_3 <= V_M_RESULT1DOWNTO0_shadow_intermed_2;
RIN_X_LADDR_intermed_1 <= RIN.X.LADDR;
R_M_RESULT1DOWNTO0_intermed_1 <= R.M.RESULT ( 1 DOWNTO 0 );
RIN_M_RESULT1DOWNTO0_intermed_1 <= RIN.M.RESULT( 1 DOWNTO 0 );
RIN_M_RESULT1DOWNTO0_intermed_2 <= RIN_M_RESULT1DOWNTO0_intermed_1;
RIN_M_RESULT1DOWNTO0_intermed_3 <= RIN_M_RESULT1DOWNTO0_intermed_2;
V_M_RESULT1DOWNTO0_shadow_intermed_1 <= V_M_RESULT1DOWNTO0_shadow;
V_M_RESULT1DOWNTO0_shadow_intermed_2 <= V_M_RESULT1DOWNTO0_shadow_intermed_1;
R_M_RESULT1DOWNTO0_intermed_1 <= R.M.RESULT( 1 DOWNTO 0 );
R_M_RESULT1DOWNTO0_intermed_2 <= R_M_RESULT1DOWNTO0_intermed_1;
RIN_M_RESULT1DOWNTO0_intermed_1 <= RIN.M.RESULT ( 1 DOWNTO 0 );
RIN_M_RESULT1DOWNTO0_intermed_2 <= RIN_M_RESULT1DOWNTO0_intermed_1;
V_X_LADDR_shadow_intermed_1 <= V_X_LADDR_shadow;
RIN_M_CTRL_PC31DOWNTO2_intermed_1 <= RIN.M.CTRL.PC( 31 DOWNTO 2 );
RIN_M_CTRL_PC31DOWNTO2_intermed_2 <= RIN_M_CTRL_PC31DOWNTO2_intermed_1;
RIN_M_CTRL_PC31DOWNTO2_intermed_3 <= RIN_M_CTRL_PC31DOWNTO2_intermed_2;
RIN_X_RESULT_intermed_1 <= RIN.X.RESULT;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_M_CTRL_PC31DOWNTO2_shadow;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_M_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_X_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_X_CTRL_PC31DOWNTO2_shadow;
R_E_CTRL_PC31DOWNTO2_intermed_1 <= R.E.CTRL.PC ( 31 DOWNTO 2 );
R_E_CTRL_PC31DOWNTO2_intermed_2 <= R_E_CTRL_PC31DOWNTO2_intermed_1;
V_D_PC31DOWNTO2_shadow_intermed_1 <= V_D_PC31DOWNTO2_shadow;
V_D_PC31DOWNTO2_shadow_intermed_2 <= V_D_PC31DOWNTO2_shadow_intermed_1;
V_D_PC31DOWNTO2_shadow_intermed_3 <= V_D_PC31DOWNTO2_shadow_intermed_2;
V_D_PC31DOWNTO2_shadow_intermed_4 <= V_D_PC31DOWNTO2_shadow_intermed_3;
V_D_PC31DOWNTO2_shadow_intermed_5 <= V_D_PC31DOWNTO2_shadow_intermed_4;
RIN_D_PC31DOWNTO2_intermed_1 <= RIN.D.PC( 31 DOWNTO 2 );
RIN_D_PC31DOWNTO2_intermed_2 <= RIN_D_PC31DOWNTO2_intermed_1;
RIN_D_PC31DOWNTO2_intermed_3 <= RIN_D_PC31DOWNTO2_intermed_2;
RIN_D_PC31DOWNTO2_intermed_4 <= RIN_D_PC31DOWNTO2_intermed_3;
RIN_D_PC31DOWNTO2_intermed_5 <= RIN_D_PC31DOWNTO2_intermed_4;
V_X_DATA0_shadow_intermed_1 <= V_X_DATA0_shadow;
RIN_E_CTRL_PC31DOWNTO2_intermed_1 <= RIN.E.CTRL.PC ( 31 DOWNTO 2 );
RIN_E_CTRL_PC31DOWNTO2_intermed_2 <= RIN_E_CTRL_PC31DOWNTO2_intermed_1;
RIN_E_CTRL_PC31DOWNTO2_intermed_3 <= RIN_E_CTRL_PC31DOWNTO2_intermed_2;
RIN_A_CTRL_PC31DOWNTO2_intermed_1 <= RIN.A.CTRL.PC ( 31 DOWNTO 2 );
RIN_A_CTRL_PC31DOWNTO2_intermed_2 <= RIN_A_CTRL_PC31DOWNTO2_intermed_1;
RIN_A_CTRL_PC31DOWNTO2_intermed_3 <= RIN_A_CTRL_PC31DOWNTO2_intermed_2;
RIN_A_CTRL_PC31DOWNTO2_intermed_4 <= RIN_A_CTRL_PC31DOWNTO2_intermed_3;
RIN_X_CTRL_PC31DOWNTO2_intermed_1 <= RIN.X.CTRL.PC ( 31 DOWNTO 2 );
RIN_X_CTRL_PC31DOWNTO2_intermed_1 <= RIN.X.CTRL.PC( 31 DOWNTO 2 );
RIN_X_CTRL_PC31DOWNTO2_intermed_2 <= RIN_X_CTRL_PC31DOWNTO2_intermed_1;
RIN_M_CTRL_PC31DOWNTO2_intermed_1 <= RIN.M.CTRL.PC ( 31 DOWNTO 2 );
RIN_M_CTRL_PC31DOWNTO2_intermed_2 <= RIN_M_CTRL_PC31DOWNTO2_intermed_1;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO2_shadow;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_2;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_4 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_3;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_5 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_4;
R_D_PC31DOWNTO2_intermed_1 <= R.D.PC( 31 DOWNTO 2 );
R_D_PC31DOWNTO2_intermed_2 <= R_D_PC31DOWNTO2_intermed_1;
R_D_PC31DOWNTO2_intermed_3 <= R_D_PC31DOWNTO2_intermed_2;
R_D_PC31DOWNTO2_intermed_4 <= R_D_PC31DOWNTO2_intermed_3;
R_M_CTRL_PC31DOWNTO2_intermed_1 <= R.M.CTRL.PC ( 31 DOWNTO 2 );
V_X_DATA0_shadow_intermed_1 <= V_X_DATA0_shadow;
V_X_DATA0_shadow_intermed_2 <= V_X_DATA0_shadow_intermed_1;
R_M_CTRL_PC31DOWNTO2_intermed_1 <= R.M.CTRL.PC( 31 DOWNTO 2 );
R_M_CTRL_PC31DOWNTO2_intermed_2 <= R_M_CTRL_PC31DOWNTO2_intermed_1;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_E_CTRL_PC31DOWNTO2_shadow;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_2;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_4 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_3;
RIN_A_CTRL_PC31DOWNTO2_intermed_1 <= RIN.A.CTRL.PC( 31 DOWNTO 2 );
RIN_A_CTRL_PC31DOWNTO2_intermed_2 <= RIN_A_CTRL_PC31DOWNTO2_intermed_1;
RIN_A_CTRL_PC31DOWNTO2_intermed_3 <= RIN_A_CTRL_PC31DOWNTO2_intermed_2;
RIN_A_CTRL_PC31DOWNTO2_intermed_4 <= RIN_A_CTRL_PC31DOWNTO2_intermed_3;
RIN_A_CTRL_PC31DOWNTO2_intermed_5 <= RIN_A_CTRL_PC31DOWNTO2_intermed_4;
R_A_CTRL_PC31DOWNTO2_intermed_1 <= R.A.CTRL.PC( 31 DOWNTO 2 );
R_A_CTRL_PC31DOWNTO2_intermed_2 <= R_A_CTRL_PC31DOWNTO2_intermed_1;
R_A_CTRL_PC31DOWNTO2_intermed_3 <= R_A_CTRL_PC31DOWNTO2_intermed_2;
R_A_CTRL_PC31DOWNTO2_intermed_4 <= R_A_CTRL_PC31DOWNTO2_intermed_3;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_M_CTRL_PC31DOWNTO2_shadow;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_M_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_M_CTRL_PC31DOWNTO2_shadow_intermed_2;
RIN_X_DATA0_intermed_1 <= RIN.X.DATA ( 0 );
R_A_CTRL_PC31DOWNTO2_intermed_1 <= R.A.CTRL.PC ( 31 DOWNTO 2 );
R_A_CTRL_PC31DOWNTO2_intermed_2 <= R_A_CTRL_PC31DOWNTO2_intermed_1;
R_A_CTRL_PC31DOWNTO2_intermed_3 <= R_A_CTRL_PC31DOWNTO2_intermed_2;
V_X_RESULT_shadow_intermed_1 <= V_X_RESULT_shadow;
R_X_CTRL_PC31DOWNTO2_intermed_1 <= R.X.CTRL.PC( 31 DOWNTO 2 );
R_X_DATA0_intermed_1 <= R.X.DATA( 0 );
V_A_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO2_shadow;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_2;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_4 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_3;
R_E_CTRL_PC31DOWNTO2_intermed_1 <= R.E.CTRL.PC( 31 DOWNTO 2 );
R_E_CTRL_PC31DOWNTO2_intermed_2 <= R_E_CTRL_PC31DOWNTO2_intermed_1;
R_E_CTRL_PC31DOWNTO2_intermed_3 <= R_E_CTRL_PC31DOWNTO2_intermed_2;
RIN_E_CTRL_PC31DOWNTO2_intermed_1 <= RIN.E.CTRL.PC( 31 DOWNTO 2 );
RIN_E_CTRL_PC31DOWNTO2_intermed_2 <= RIN_E_CTRL_PC31DOWNTO2_intermed_1;
RIN_E_CTRL_PC31DOWNTO2_intermed_3 <= RIN_E_CTRL_PC31DOWNTO2_intermed_2;
RIN_E_CTRL_PC31DOWNTO2_intermed_4 <= RIN_E_CTRL_PC31DOWNTO2_intermed_3;
V_X_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_X_CTRL_PC31DOWNTO2_shadow;
V_X_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_X_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_E_CTRL_PC31DOWNTO2_shadow;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_2;
RIN_X_DATA0_intermed_1 <= RIN.X.DATA( 0 );
RIN_X_DATA0_intermed_2 <= RIN_X_DATA0_intermed_1;
RIN_A_CTRL_ANNUL_intermed_1 <= RIN.A.CTRL.ANNUL;
RIN_A_CTRL_ANNUL_intermed_2 <= RIN_A_CTRL_ANNUL_intermed_1;
RIN_A_CTRL_ANNUL_intermed_3 <= RIN_A_CTRL_ANNUL_intermed_2;
RIN_A_CTRL_ANNUL_intermed_4 <= RIN_A_CTRL_ANNUL_intermed_3;
RIN_A_CTRL_ANNUL_intermed_5 <= RIN_A_CTRL_ANNUL_intermed_4;
R_A_CTRL_ANNUL_intermed_1 <= R.A.CTRL.ANNUL;
R_A_CTRL_ANNUL_intermed_2 <= R_A_CTRL_ANNUL_intermed_1;
R_A_CTRL_ANNUL_intermed_3 <= R_A_CTRL_ANNUL_intermed_2;
R_A_CTRL_ANNUL_intermed_4 <= R_A_CTRL_ANNUL_intermed_3;
R_X_ANNUL_ALL_intermed_1 <= R.X.ANNUL_ALL;
R_X_ANNUL_ALL_intermed_2 <= R_X_ANNUL_ALL_intermed_1;
R_X_ANNUL_ALL_intermed_3 <= R_X_ANNUL_ALL_intermed_2;
R_X_ANNUL_ALL_intermed_4 <= R_X_ANNUL_ALL_intermed_3;
V_X_CTRL_WREG_shadow_intermed_1 <= V_X_CTRL_WREG_shadow;
RIN_X_CTRL_WREG_intermed_1 <= RIN.X.CTRL.WREG;
RIN_M_CTRL_WREG_intermed_1 <= RIN.M.CTRL.WREG;
RIN_M_CTRL_WREG_intermed_2 <= RIN_M_CTRL_WREG_intermed_1;
RIN_A_CTRL_WREG_intermed_1 <= RIN.A.CTRL.WREG;
RIN_A_CTRL_WREG_intermed_2 <= RIN_A_CTRL_WREG_intermed_1;
RIN_A_CTRL_WREG_intermed_3 <= RIN_A_CTRL_WREG_intermed_2;
RIN_A_CTRL_WREG_intermed_4 <= RIN_A_CTRL_WREG_intermed_3;
V_A_CTRL_WREG_shadow_intermed_1 <= V_A_CTRL_WREG_shadow;
V_A_CTRL_WREG_shadow_intermed_2 <= V_A_CTRL_WREG_shadow_intermed_1;
V_A_CTRL_WREG_shadow_intermed_3 <= V_A_CTRL_WREG_shadow_intermed_2;
V_A_CTRL_WREG_shadow_intermed_4 <= V_A_CTRL_WREG_shadow_intermed_3;
R_A_CTRL_WREG_intermed_1 <= R.A.CTRL.WREG;
R_A_CTRL_WREG_intermed_2 <= R_A_CTRL_WREG_intermed_1;
R_A_CTRL_WREG_intermed_3 <= R_A_CTRL_WREG_intermed_2;
V_X_ANNUL_ALL_shadow_intermed_1 <= V_X_ANNUL_ALL_shadow;
V_X_ANNUL_ALL_shadow_intermed_2 <= V_X_ANNUL_ALL_shadow_intermed_1;
V_X_ANNUL_ALL_shadow_intermed_3 <= V_X_ANNUL_ALL_shadow_intermed_2;
V_X_ANNUL_ALL_shadow_intermed_4 <= V_X_ANNUL_ALL_shadow_intermed_3;
R_M_CTRL_WREG_intermed_1 <= R.M.CTRL.WREG;
RIN_X_ANNUL_ALL_intermed_1 <= RIN.X.ANNUL_ALL;
RIN_X_ANNUL_ALL_intermed_2 <= RIN_X_ANNUL_ALL_intermed_1;
RIN_X_ANNUL_ALL_intermed_3 <= RIN_X_ANNUL_ALL_intermed_2;
RIN_X_ANNUL_ALL_intermed_4 <= RIN_X_ANNUL_ALL_intermed_3;
RIN_X_ANNUL_ALL_intermed_5 <= RIN_X_ANNUL_ALL_intermed_4;
V_M_CTRL_WREG_shadow_intermed_1 <= V_M_CTRL_WREG_shadow;
V_M_CTRL_WREG_shadow_intermed_2 <= V_M_CTRL_WREG_shadow_intermed_1;
R_E_CTRL_WREG_intermed_1 <= R.E.CTRL.WREG;
R_E_CTRL_WREG_intermed_2 <= R_E_CTRL_WREG_intermed_1;
V_A_CTRL_ANNUL_shadow_intermed_1 <= V_A_CTRL_ANNUL_shadow;
V_A_CTRL_ANNUL_shadow_intermed_2 <= V_A_CTRL_ANNUL_shadow_intermed_1;
V_A_CTRL_ANNUL_shadow_intermed_3 <= V_A_CTRL_ANNUL_shadow_intermed_2;
V_A_CTRL_ANNUL_shadow_intermed_4 <= V_A_CTRL_ANNUL_shadow_intermed_3;
RIN_E_CTRL_WREG_intermed_1 <= RIN.E.CTRL.WREG;
RIN_E_CTRL_WREG_intermed_2 <= RIN_E_CTRL_WREG_intermed_1;
RIN_E_CTRL_WREG_intermed_3 <= RIN_E_CTRL_WREG_intermed_2;
V_E_CTRL_WREG_shadow_intermed_1 <= V_E_CTRL_WREG_shadow;
V_E_CTRL_WREG_shadow_intermed_2 <= V_E_CTRL_WREG_shadow_intermed_1;
V_E_CTRL_WREG_shadow_intermed_3 <= V_E_CTRL_WREG_shadow_intermed_2;
V_E_CTRL_TT_shadow_intermed_1 <= V_E_CTRL_TT_shadow;
V_E_CTRL_TT_shadow_intermed_2 <= V_E_CTRL_TT_shadow_intermed_1;
V_E_CTRL_TT_shadow_intermed_3 <= V_E_CTRL_TT_shadow_intermed_2;
V_X_CTRL_TT_shadow_intermed_1 <= V_X_CTRL_TT_shadow;
RIN_A_CTRL_TT_intermed_1 <= RIN.A.CTRL.TT;
RIN_A_CTRL_TT_intermed_2 <= RIN_A_CTRL_TT_intermed_1;
RIN_A_CTRL_TT_intermed_3 <= RIN_A_CTRL_TT_intermed_2;
RIN_A_CTRL_TT_intermed_4 <= RIN_A_CTRL_TT_intermed_3;
R_A_CTRL_TT_intermed_1 <= R.A.CTRL.TT;
R_A_CTRL_TT_intermed_2 <= R_A_CTRL_TT_intermed_1;
R_A_CTRL_TT_intermed_3 <= R_A_CTRL_TT_intermed_2;
R_M_CTRL_TT_intermed_1 <= R.M.CTRL.TT;
RIN_X_RESULT6DOWNTO0_intermed_1 <= RIN.X.RESULT ( 6 DOWNTO 0 );
R_E_CTRL_TT_intermed_1 <= R.E.CTRL.TT;
R_E_CTRL_TT_intermed_2 <= R_E_CTRL_TT_intermed_1;
RIN_M_CTRL_TT_intermed_1 <= RIN.M.CTRL.TT;
RIN_M_CTRL_TT_intermed_2 <= RIN_M_CTRL_TT_intermed_1;
V_X_RESULT6DOWNTO0_shadow_intermed_1 <= V_X_RESULT6DOWNTO0_shadow;
V_X_RESULT6DOWNTO0_shadow_intermed_1 <= V_X_RESULT6DOWNTO0_shadow;
V_X_RESULT6DOWNTO0_shadow_intermed_2 <= V_X_RESULT6DOWNTO0_shadow_intermed_1;
RIN_X_RESULT6DOWNTO0_intermed_1 <= RIN.X.RESULT( 6 DOWNTO 0 );
RIN_X_RESULT6DOWNTO0_intermed_2 <= RIN_X_RESULT6DOWNTO0_intermed_1;
RIN_E_CTRL_TT_intermed_1 <= RIN.E.CTRL.TT;
RIN_E_CTRL_TT_intermed_2 <= RIN_E_CTRL_TT_intermed_1;
RIN_E_CTRL_TT_intermed_3 <= RIN_E_CTRL_TT_intermed_2;
V_M_CTRL_TT_shadow_intermed_1 <= V_M_CTRL_TT_shadow;
V_M_CTRL_TT_shadow_intermed_2 <= V_M_CTRL_TT_shadow_intermed_1;
R_X_RESULT6DOWNTO0_intermed_1 <= R.X.RESULT( 6 DOWNTO 0 );
V_A_CTRL_TT_shadow_intermed_1 <= V_A_CTRL_TT_shadow;
V_A_CTRL_TT_shadow_intermed_2 <= V_A_CTRL_TT_shadow_intermed_1;
V_A_CTRL_TT_shadow_intermed_3 <= V_A_CTRL_TT_shadow_intermed_2;
V_A_CTRL_TT_shadow_intermed_4 <= V_A_CTRL_TT_shadow_intermed_3;
RIN_X_CTRL_TT_intermed_1 <= RIN.X.CTRL.TT;
RIN_X_CTRL_TRAP_intermed_1 <= RIN.X.CTRL.TRAP;
V_A_CTRL_TRAP_shadow_intermed_1 <= V_A_CTRL_TRAP_shadow;
V_A_CTRL_TRAP_shadow_intermed_2 <= V_A_CTRL_TRAP_shadow_intermed_1;
V_A_CTRL_TRAP_shadow_intermed_3 <= V_A_CTRL_TRAP_shadow_intermed_2;
V_A_CTRL_TRAP_shadow_intermed_4 <= V_A_CTRL_TRAP_shadow_intermed_3;
V_X_MEXC_shadow_intermed_1 <= V_X_MEXC_shadow;
ICO_MEXC_intermed_1 <= ICO.MEXC;
ICO_MEXC_intermed_2 <= ICO_MEXC_intermed_1;
ICO_MEXC_intermed_3 <= ICO_MEXC_intermed_2;
ICO_MEXC_intermed_4 <= ICO_MEXC_intermed_3;
ICO_MEXC_intermed_5 <= ICO_MEXC_intermed_4;
R_E_CTRL_TRAP_intermed_1 <= R.E.CTRL.TRAP;
R_E_CTRL_TRAP_intermed_2 <= R_E_CTRL_TRAP_intermed_1;
RIN_A_CTRL_TRAP_intermed_1 <= RIN.A.CTRL.TRAP;
RIN_A_CTRL_TRAP_intermed_2 <= RIN_A_CTRL_TRAP_intermed_1;
RIN_A_CTRL_TRAP_intermed_3 <= RIN_A_CTRL_TRAP_intermed_2;
RIN_A_CTRL_TRAP_intermed_4 <= RIN_A_CTRL_TRAP_intermed_3;
V_E_CTRL_TRAP_shadow_intermed_1 <= V_E_CTRL_TRAP_shadow;
V_E_CTRL_TRAP_shadow_intermed_2 <= V_E_CTRL_TRAP_shadow_intermed_1;
V_E_CTRL_TRAP_shadow_intermed_3 <= V_E_CTRL_TRAP_shadow_intermed_2;
RIN_E_CTRL_TRAP_intermed_1 <= RIN.E.CTRL.TRAP;
RIN_E_CTRL_TRAP_intermed_2 <= RIN_E_CTRL_TRAP_intermed_1;
RIN_E_CTRL_TRAP_intermed_3 <= RIN_E_CTRL_TRAP_intermed_2;
R_D_MEXC_intermed_1 <= R.D.MEXC;
R_D_MEXC_intermed_2 <= R_D_MEXC_intermed_1;
R_D_MEXC_intermed_3 <= R_D_MEXC_intermed_2;
R_D_MEXC_intermed_4 <= R_D_MEXC_intermed_3;
V_M_CTRL_TRAP_shadow_intermed_1 <= V_M_CTRL_TRAP_shadow;
V_M_CTRL_TRAP_shadow_intermed_2 <= V_M_CTRL_TRAP_shadow_intermed_1;
V_X_CTRL_TRAP_shadow_intermed_1 <= V_X_CTRL_TRAP_shadow;
V_D_MEXC_shadow_intermed_1 <= V_D_MEXC_shadow;
V_D_MEXC_shadow_intermed_2 <= V_D_MEXC_shadow_intermed_1;
V_D_MEXC_shadow_intermed_3 <= V_D_MEXC_shadow_intermed_2;
V_D_MEXC_shadow_intermed_4 <= V_D_MEXC_shadow_intermed_3;
V_D_MEXC_shadow_intermed_5 <= V_D_MEXC_shadow_intermed_4;
R_A_CTRL_TRAP_intermed_1 <= R.A.CTRL.TRAP;
R_A_CTRL_TRAP_intermed_2 <= R_A_CTRL_TRAP_intermed_1;
R_A_CTRL_TRAP_intermed_3 <= R_A_CTRL_TRAP_intermed_2;
RIN_X_MEXC_intermed_1 <= RIN.X.MEXC;
RIN_M_CTRL_TRAP_intermed_1 <= RIN.M.CTRL.TRAP;
RIN_M_CTRL_TRAP_intermed_2 <= RIN_M_CTRL_TRAP_intermed_1;
R_M_CTRL_TRAP_intermed_1 <= R.M.CTRL.TRAP;
RIN_D_MEXC_intermed_1 <= RIN.D.MEXC;
RIN_D_MEXC_intermed_2 <= RIN_D_MEXC_intermed_1;
RIN_D_MEXC_intermed_3 <= RIN_D_MEXC_intermed_2;
RIN_D_MEXC_intermed_4 <= RIN_D_MEXC_intermed_3;
RIN_D_MEXC_intermed_5 <= RIN_D_MEXC_intermed_4;
DCO_MEXC_intermed_1 <= DCO.MEXC;
V_A_CTRL_INST19_shadow_intermed_1 <= V_A_CTRL_INST19_shadow;
V_A_CTRL_INST19_shadow_intermed_2 <= V_A_CTRL_INST19_shadow_intermed_1;
R_D_INST019_intermed_1 <= R.D.INST( 0 )( 19 );
R_D_INST019_intermed_2 <= R_D_INST019_intermed_1;
V_E_CTRL_INST19_shadow_intermed_1 <= V_E_CTRL_INST19_shadow;
V_E_CTRL_INST19_shadow_intermed_2 <= V_E_CTRL_INST19_shadow_intermed_1;
RIN_A_CTRL_INST19_intermed_1 <= RIN.A.CTRL.INST ( 19 );
V_D_INST019_shadow_intermed_1 <= V_D_INST019_shadow;
V_D_INST019_shadow_intermed_2 <= V_D_INST019_shadow_intermed_1;
V_D_INST019_shadow_intermed_3 <= V_D_INST019_shadow_intermed_2;
RIN_A_CTRL_INST19_intermed_1 <= RIN.A.CTRL.INST( 19 );
RIN_A_CTRL_INST19_intermed_2 <= RIN_A_CTRL_INST19_intermed_1;
RIN_E_CTRL_INST19_intermed_1 <= RIN.E.CTRL.INST ( 19 );
RIN_E_CTRL_INST19_intermed_1 <= RIN.E.CTRL.INST( 19 );
RIN_E_CTRL_INST19_intermed_2 <= RIN_E_CTRL_INST19_intermed_1;
DE_INST19_shadow_intermed_1 <= DE_INST19_shadow;
R_D_INST019_intermed_1 <= R.D.INST ( 0 )( 19 );
RIN_D_INST019_intermed_1 <= RIN.D.INST ( 0 )( 19 );
RIN_D_INST019_intermed_2 <= RIN_D_INST019_intermed_1;
V_E_CTRL_INST19_shadow_intermed_1 <= V_E_CTRL_INST19_shadow;
V_D_INST019_shadow_intermed_1 <= V_D_INST019_shadow;
V_D_INST019_shadow_intermed_2 <= V_D_INST019_shadow_intermed_1;
R_E_CTRL_INST19_intermed_1 <= R.E.CTRL.INST( 19 );
R_A_CTRL_INST19_intermed_1 <= R.A.CTRL.INST( 19 );
RIN_D_INST019_intermed_1 <= RIN.D.INST( 0 )( 19 );
RIN_D_INST019_intermed_2 <= RIN_D_INST019_intermed_1;
RIN_D_INST019_intermed_3 <= RIN_D_INST019_intermed_2;
V_A_CTRL_INST19_shadow_intermed_1 <= V_A_CTRL_INST19_shadow;
VP_ERROR_shadow_intermed_1 <= VP_ERROR_shadow;
RPIN_PWD_intermed_1 <= RPIN.PWD;
V_X_DEBUG_shadow_intermed_1 <= V_X_DEBUG_shadow;
IRQI_RUN_intermed_1 <= IRQI.RUN;
VP_PWD_shadow_intermed_1 <= VP_PWD_shadow;
RPIN_ERROR_intermed_1 <= RPIN.ERROR;
RIN_X_DEBUG_intermed_1 <= RIN.X.DEBUG;
VP_ERROR_shadow_intermed_1 <= VP_ERROR_shadow;
RIN_X_NERROR_intermed_1 <= RIN.X.NERROR;
RPIN_ERROR_intermed_1 <= RPIN.ERROR;
V_F_PC31DOWNTO4_shadow_intermed_1 <= V_F_PC31DOWNTO4_shadow;
V_E_CTRL_TT_shadow_intermed_1 <= V_E_CTRL_TT_shadow;
V_E_CTRL_TT_shadow_intermed_2 <= V_E_CTRL_TT_shadow_intermed_1;
V_E_CTRL_TT_shadow_intermed_3 <= V_E_CTRL_TT_shadow_intermed_2;
V_X_CTRL_TT_shadow_intermed_1 <= V_X_CTRL_TT_shadow;
V_X_CTRL_PC31DOWNTO4_shadow_intermed_1 <= V_X_CTRL_PC31DOWNTO4_shadow;
V_X_CTRL_PC31DOWNTO4_shadow_intermed_2 <= V_X_CTRL_PC31DOWNTO4_shadow_intermed_1;
V_X_CTRL_PC31DOWNTO4_shadow_intermed_3 <= V_X_CTRL_PC31DOWNTO4_shadow_intermed_2;
RIN_A_CTRL_TT_intermed_1 <= RIN.A.CTRL.TT;
RIN_A_CTRL_TT_intermed_2 <= RIN_A_CTRL_TT_intermed_1;
RIN_A_CTRL_TT_intermed_3 <= RIN_A_CTRL_TT_intermed_2;
RIN_A_CTRL_TT_intermed_4 <= RIN_A_CTRL_TT_intermed_3;
IR_ADDR31DOWNTO4_intermed_1 <= IR.ADDR( 31 DOWNTO 4 );
R_A_CTRL_TT_intermed_1 <= R.A.CTRL.TT;
R_A_CTRL_TT_intermed_2 <= R_A_CTRL_TT_intermed_1;
R_A_CTRL_TT_intermed_3 <= R_A_CTRL_TT_intermed_2;
R_M_CTRL_TT_intermed_1 <= R.M.CTRL.TT;
VIR_ADDR31DOWNTO4_shadow_intermed_1 <= VIR_ADDR31DOWNTO4_shadow;
VIR_ADDR31DOWNTO4_shadow_intermed_2 <= VIR_ADDR31DOWNTO4_shadow_intermed_1;
RIN_F_PC31DOWNTO4_intermed_1 <= RIN.F.PC( 31 DOWNTO 4 );
RIN_X_RESULT6DOWNTO0_intermed_1 <= RIN.X.RESULT ( 6 DOWNTO 0 );
RIN_A_CTRL_PC31DOWNTO4_intermed_1 <= RIN.A.CTRL.PC( 31 DOWNTO 4 );
RIN_A_CTRL_PC31DOWNTO4_intermed_2 <= RIN_A_CTRL_PC31DOWNTO4_intermed_1;
RIN_A_CTRL_PC31DOWNTO4_intermed_3 <= RIN_A_CTRL_PC31DOWNTO4_intermed_2;
RIN_A_CTRL_PC31DOWNTO4_intermed_4 <= RIN_A_CTRL_PC31DOWNTO4_intermed_3;
RIN_A_CTRL_PC31DOWNTO4_intermed_5 <= RIN_A_CTRL_PC31DOWNTO4_intermed_4;
RIN_A_CTRL_PC31DOWNTO4_intermed_6 <= RIN_A_CTRL_PC31DOWNTO4_intermed_5;
R_A_CTRL_PC31DOWNTO4_intermed_1 <= R.A.CTRL.PC( 31 DOWNTO 4 );
R_A_CTRL_PC31DOWNTO4_intermed_2 <= R_A_CTRL_PC31DOWNTO4_intermed_1;
R_A_CTRL_PC31DOWNTO4_intermed_3 <= R_A_CTRL_PC31DOWNTO4_intermed_2;
R_A_CTRL_PC31DOWNTO4_intermed_4 <= R_A_CTRL_PC31DOWNTO4_intermed_3;
R_A_CTRL_PC31DOWNTO4_intermed_5 <= R_A_CTRL_PC31DOWNTO4_intermed_4;
R_E_CTRL_TT_intermed_1 <= R.E.CTRL.TT;
R_E_CTRL_TT_intermed_2 <= R_E_CTRL_TT_intermed_1;
R_D_PC31DOWNTO4_intermed_1 <= R.D.PC( 31 DOWNTO 4 );
R_D_PC31DOWNTO4_intermed_2 <= R_D_PC31DOWNTO4_intermed_1;
R_D_PC31DOWNTO4_intermed_3 <= R_D_PC31DOWNTO4_intermed_2;
R_D_PC31DOWNTO4_intermed_4 <= R_D_PC31DOWNTO4_intermed_3;
R_D_PC31DOWNTO4_intermed_5 <= R_D_PC31DOWNTO4_intermed_4;
R_D_PC31DOWNTO4_intermed_6 <= R_D_PC31DOWNTO4_intermed_5;
RIN_X_CTRL_PC31DOWNTO4_intermed_1 <= RIN.X.CTRL.PC( 31 DOWNTO 4 );
RIN_X_CTRL_PC31DOWNTO4_intermed_2 <= RIN_X_CTRL_PC31DOWNTO4_intermed_1;
RIN_X_CTRL_PC31DOWNTO4_intermed_3 <= RIN_X_CTRL_PC31DOWNTO4_intermed_2;
EX_ADD_RES32DOWNTO332DOWNTO5_shadow_intermed_1 <= EX_ADD_RES32DOWNTO332DOWNTO5_shadow;
V_W_S_TBA_shadow_intermed_1 <= V_W_S_TBA_shadow;
RIN_M_CTRL_TT_intermed_1 <= RIN.M.CTRL.TT;
RIN_M_CTRL_TT_intermed_2 <= RIN_M_CTRL_TT_intermed_1;
V_D_PC31DOWNTO4_shadow_intermed_1 <= V_D_PC31DOWNTO4_shadow;
V_D_PC31DOWNTO4_shadow_intermed_2 <= V_D_PC31DOWNTO4_shadow_intermed_1;
V_D_PC31DOWNTO4_shadow_intermed_3 <= V_D_PC31DOWNTO4_shadow_intermed_2;
V_D_PC31DOWNTO4_shadow_intermed_4 <= V_D_PC31DOWNTO4_shadow_intermed_3;
V_D_PC31DOWNTO4_shadow_intermed_5 <= V_D_PC31DOWNTO4_shadow_intermed_4;
V_D_PC31DOWNTO4_shadow_intermed_6 <= V_D_PC31DOWNTO4_shadow_intermed_5;
V_D_PC31DOWNTO4_shadow_intermed_7 <= V_D_PC31DOWNTO4_shadow_intermed_6;
V_E_CTRL_PC31DOWNTO4_shadow_intermed_1 <= V_E_CTRL_PC31DOWNTO4_shadow;
V_E_CTRL_PC31DOWNTO4_shadow_intermed_2 <= V_E_CTRL_PC31DOWNTO4_shadow_intermed_1;
V_E_CTRL_PC31DOWNTO4_shadow_intermed_3 <= V_E_CTRL_PC31DOWNTO4_shadow_intermed_2;
V_E_CTRL_PC31DOWNTO4_shadow_intermed_4 <= V_E_CTRL_PC31DOWNTO4_shadow_intermed_3;
V_E_CTRL_PC31DOWNTO4_shadow_intermed_5 <= V_E_CTRL_PC31DOWNTO4_shadow_intermed_4;
RIN_M_CTRL_PC31DOWNTO4_intermed_1 <= RIN.M.CTRL.PC( 31 DOWNTO 4 );
RIN_M_CTRL_PC31DOWNTO4_intermed_2 <= RIN_M_CTRL_PC31DOWNTO4_intermed_1;
RIN_M_CTRL_PC31DOWNTO4_intermed_3 <= RIN_M_CTRL_PC31DOWNTO4_intermed_2;
RIN_M_CTRL_PC31DOWNTO4_intermed_4 <= RIN_M_CTRL_PC31DOWNTO4_intermed_3;
V_X_RESULT6DOWNTO0_shadow_intermed_1 <= V_X_RESULT6DOWNTO0_shadow;
R_X_CTRL_PC31DOWNTO4_intermed_1 <= R.X.CTRL.PC( 31 DOWNTO 4 );
R_X_CTRL_PC31DOWNTO4_intermed_2 <= R_X_CTRL_PC31DOWNTO4_intermed_1;
V_X_RESULT6DOWNTO0_shadow_intermed_1 <= V_X_RESULT6DOWNTO0_shadow;
V_X_RESULT6DOWNTO0_shadow_intermed_2 <= V_X_RESULT6DOWNTO0_shadow_intermed_1;
RIN_X_RESULT6DOWNTO0_intermed_1 <= RIN.X.RESULT( 6 DOWNTO 0 );
RIN_X_RESULT6DOWNTO0_intermed_2 <= RIN_X_RESULT6DOWNTO0_intermed_1;
RIN_E_CTRL_TT_intermed_1 <= RIN.E.CTRL.TT;
RIN_E_CTRL_TT_intermed_2 <= RIN_E_CTRL_TT_intermed_1;
RIN_E_CTRL_TT_intermed_3 <= RIN_E_CTRL_TT_intermed_2;
V_M_CTRL_TT_shadow_intermed_1 <= V_M_CTRL_TT_shadow;
V_M_CTRL_TT_shadow_intermed_2 <= V_M_CTRL_TT_shadow_intermed_1;
R_X_RESULT6DOWNTO0_intermed_1 <= R.X.RESULT( 6 DOWNTO 0 );
IRIN_ADDR31DOWNTO4_intermed_1 <= IRIN.ADDR( 31 DOWNTO 4 );
IRIN_ADDR31DOWNTO4_intermed_2 <= IRIN_ADDR31DOWNTO4_intermed_1;
V_M_CTRL_PC31DOWNTO4_shadow_intermed_1 <= V_M_CTRL_PC31DOWNTO4_shadow;
V_M_CTRL_PC31DOWNTO4_shadow_intermed_2 <= V_M_CTRL_PC31DOWNTO4_shadow_intermed_1;
V_M_CTRL_PC31DOWNTO4_shadow_intermed_3 <= V_M_CTRL_PC31DOWNTO4_shadow_intermed_2;
V_M_CTRL_PC31DOWNTO4_shadow_intermed_4 <= V_M_CTRL_PC31DOWNTO4_shadow_intermed_3;
V_A_CTRL_TT_shadow_intermed_1 <= V_A_CTRL_TT_shadow;
V_A_CTRL_TT_shadow_intermed_2 <= V_A_CTRL_TT_shadow_intermed_1;
V_A_CTRL_TT_shadow_intermed_3 <= V_A_CTRL_TT_shadow_intermed_2;
V_A_CTRL_TT_shadow_intermed_4 <= V_A_CTRL_TT_shadow_intermed_3;
R_M_CTRL_PC31DOWNTO4_intermed_1 <= R.M.CTRL.PC( 31 DOWNTO 4 );
R_M_CTRL_PC31DOWNTO4_intermed_2 <= R_M_CTRL_PC31DOWNTO4_intermed_1;
R_M_CTRL_PC31DOWNTO4_intermed_3 <= R_M_CTRL_PC31DOWNTO4_intermed_2;
XC_TRAP_ADDRESS31DOWNTO4_shadow_intermed_1 <= XC_TRAP_ADDRESS31DOWNTO4_shadow;
RIN_X_CTRL_TT_intermed_1 <= RIN.X.CTRL.TT;
RIN_D_PC31DOWNTO4_intermed_1 <= RIN.D.PC( 31 DOWNTO 4 );
RIN_D_PC31DOWNTO4_intermed_2 <= RIN_D_PC31DOWNTO4_intermed_1;
RIN_D_PC31DOWNTO4_intermed_3 <= RIN_D_PC31DOWNTO4_intermed_2;
RIN_D_PC31DOWNTO4_intermed_4 <= RIN_D_PC31DOWNTO4_intermed_3;
RIN_D_PC31DOWNTO4_intermed_5 <= RIN_D_PC31DOWNTO4_intermed_4;
RIN_D_PC31DOWNTO4_intermed_6 <= RIN_D_PC31DOWNTO4_intermed_5;
RIN_D_PC31DOWNTO4_intermed_7 <= RIN_D_PC31DOWNTO4_intermed_6;
RIN_E_CTRL_PC31DOWNTO4_intermed_1 <= RIN.E.CTRL.PC( 31 DOWNTO 4 );
RIN_E_CTRL_PC31DOWNTO4_intermed_2 <= RIN_E_CTRL_PC31DOWNTO4_intermed_1;
RIN_E_CTRL_PC31DOWNTO4_intermed_3 <= RIN_E_CTRL_PC31DOWNTO4_intermed_2;
RIN_E_CTRL_PC31DOWNTO4_intermed_4 <= RIN_E_CTRL_PC31DOWNTO4_intermed_3;
RIN_E_CTRL_PC31DOWNTO4_intermed_5 <= RIN_E_CTRL_PC31DOWNTO4_intermed_4;
EX_JUMP_ADDRESS31DOWNTO4_shadow_intermed_1 <= EX_JUMP_ADDRESS31DOWNTO4_shadow;
V_A_CTRL_PC31DOWNTO4_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO4_shadow;
V_A_CTRL_PC31DOWNTO4_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO4_shadow_intermed_1;
V_A_CTRL_PC31DOWNTO4_shadow_intermed_3 <= V_A_CTRL_PC31DOWNTO4_shadow_intermed_2;
V_A_CTRL_PC31DOWNTO4_shadow_intermed_4 <= V_A_CTRL_PC31DOWNTO4_shadow_intermed_3;
V_A_CTRL_PC31DOWNTO4_shadow_intermed_5 <= V_A_CTRL_PC31DOWNTO4_shadow_intermed_4;
V_A_CTRL_PC31DOWNTO4_shadow_intermed_6 <= V_A_CTRL_PC31DOWNTO4_shadow_intermed_5;
RIN_W_S_TBA_intermed_1 <= RIN.W.S.TBA;
R_E_CTRL_PC31DOWNTO4_intermed_1 <= R.E.CTRL.PC( 31 DOWNTO 4 );
R_E_CTRL_PC31DOWNTO4_intermed_2 <= R_E_CTRL_PC31DOWNTO4_intermed_1;
R_E_CTRL_PC31DOWNTO4_intermed_3 <= R_E_CTRL_PC31DOWNTO4_intermed_2;
R_E_CTRL_PC31DOWNTO4_intermed_4 <= R_E_CTRL_PC31DOWNTO4_intermed_3;
R_D_PC3DOWNTO2_intermed_1 <= R.D.PC( 3 DOWNTO 2 );
R_D_PC3DOWNTO2_intermed_2 <= R_D_PC3DOWNTO2_intermed_1;
R_D_PC3DOWNTO2_intermed_3 <= R_D_PC3DOWNTO2_intermed_2;
R_D_PC3DOWNTO2_intermed_4 <= R_D_PC3DOWNTO2_intermed_3;
R_D_PC3DOWNTO2_intermed_5 <= R_D_PC3DOWNTO2_intermed_4;
R_D_PC3DOWNTO2_intermed_6 <= R_D_PC3DOWNTO2_intermed_5;
V_D_PC3DOWNTO2_shadow_intermed_1 <= V_D_PC3DOWNTO2_shadow;
V_D_PC3DOWNTO2_shadow_intermed_2 <= V_D_PC3DOWNTO2_shadow_intermed_1;
V_D_PC3DOWNTO2_shadow_intermed_3 <= V_D_PC3DOWNTO2_shadow_intermed_2;
V_D_PC3DOWNTO2_shadow_intermed_4 <= V_D_PC3DOWNTO2_shadow_intermed_3;
V_D_PC3DOWNTO2_shadow_intermed_5 <= V_D_PC3DOWNTO2_shadow_intermed_4;
V_D_PC3DOWNTO2_shadow_intermed_6 <= V_D_PC3DOWNTO2_shadow_intermed_5;
V_D_PC3DOWNTO2_shadow_intermed_7 <= V_D_PC3DOWNTO2_shadow_intermed_6;
VIR_ADDR3DOWNTO2_shadow_intermed_1 <= VIR_ADDR3DOWNTO2_shadow;
VIR_ADDR3DOWNTO2_shadow_intermed_2 <= VIR_ADDR3DOWNTO2_shadow_intermed_1;
RIN_D_PC3DOWNTO2_intermed_1 <= RIN.D.PC( 3 DOWNTO 2 );
RIN_D_PC3DOWNTO2_intermed_2 <= RIN_D_PC3DOWNTO2_intermed_1;
RIN_D_PC3DOWNTO2_intermed_3 <= RIN_D_PC3DOWNTO2_intermed_2;
RIN_D_PC3DOWNTO2_intermed_4 <= RIN_D_PC3DOWNTO2_intermed_3;
RIN_D_PC3DOWNTO2_intermed_5 <= RIN_D_PC3DOWNTO2_intermed_4;
RIN_D_PC3DOWNTO2_intermed_6 <= RIN_D_PC3DOWNTO2_intermed_5;
RIN_D_PC3DOWNTO2_intermed_7 <= RIN_D_PC3DOWNTO2_intermed_6;
R_M_CTRL_PC3DOWNTO2_intermed_1 <= R.M.CTRL.PC( 3 DOWNTO 2 );
R_M_CTRL_PC3DOWNTO2_intermed_2 <= R_M_CTRL_PC3DOWNTO2_intermed_1;
R_M_CTRL_PC3DOWNTO2_intermed_3 <= R_M_CTRL_PC3DOWNTO2_intermed_2;
R_E_CTRL_PC3DOWNTO2_intermed_1 <= R.E.CTRL.PC( 3 DOWNTO 2 );
R_E_CTRL_PC3DOWNTO2_intermed_2 <= R_E_CTRL_PC3DOWNTO2_intermed_1;
R_E_CTRL_PC3DOWNTO2_intermed_3 <= R_E_CTRL_PC3DOWNTO2_intermed_2;
R_E_CTRL_PC3DOWNTO2_intermed_4 <= R_E_CTRL_PC3DOWNTO2_intermed_3;
V_E_CTRL_PC3DOWNTO2_shadow_intermed_1 <= V_E_CTRL_PC3DOWNTO2_shadow;
V_E_CTRL_PC3DOWNTO2_shadow_intermed_2 <= V_E_CTRL_PC3DOWNTO2_shadow_intermed_1;
V_E_CTRL_PC3DOWNTO2_shadow_intermed_3 <= V_E_CTRL_PC3DOWNTO2_shadow_intermed_2;
V_E_CTRL_PC3DOWNTO2_shadow_intermed_4 <= V_E_CTRL_PC3DOWNTO2_shadow_intermed_3;
V_E_CTRL_PC3DOWNTO2_shadow_intermed_5 <= V_E_CTRL_PC3DOWNTO2_shadow_intermed_4;
RIN_X_CTRL_PC3DOWNTO2_intermed_1 <= RIN.X.CTRL.PC( 3 DOWNTO 2 );
RIN_X_CTRL_PC3DOWNTO2_intermed_2 <= RIN_X_CTRL_PC3DOWNTO2_intermed_1;
RIN_X_CTRL_PC3DOWNTO2_intermed_3 <= RIN_X_CTRL_PC3DOWNTO2_intermed_2;
R_A_CTRL_PC3DOWNTO2_intermed_1 <= R.A.CTRL.PC( 3 DOWNTO 2 );
R_A_CTRL_PC3DOWNTO2_intermed_2 <= R_A_CTRL_PC3DOWNTO2_intermed_1;
R_A_CTRL_PC3DOWNTO2_intermed_3 <= R_A_CTRL_PC3DOWNTO2_intermed_2;
R_A_CTRL_PC3DOWNTO2_intermed_4 <= R_A_CTRL_PC3DOWNTO2_intermed_3;
R_A_CTRL_PC3DOWNTO2_intermed_5 <= R_A_CTRL_PC3DOWNTO2_intermed_4;
V_X_CTRL_PC3DOWNTO2_shadow_intermed_1 <= V_X_CTRL_PC3DOWNTO2_shadow;
V_X_CTRL_PC3DOWNTO2_shadow_intermed_2 <= V_X_CTRL_PC3DOWNTO2_shadow_intermed_1;
V_X_CTRL_PC3DOWNTO2_shadow_intermed_3 <= V_X_CTRL_PC3DOWNTO2_shadow_intermed_2;
RIN_M_CTRL_PC3DOWNTO2_intermed_1 <= RIN.M.CTRL.PC( 3 DOWNTO 2 );
RIN_M_CTRL_PC3DOWNTO2_intermed_2 <= RIN_M_CTRL_PC3DOWNTO2_intermed_1;
RIN_M_CTRL_PC3DOWNTO2_intermed_3 <= RIN_M_CTRL_PC3DOWNTO2_intermed_2;
RIN_M_CTRL_PC3DOWNTO2_intermed_4 <= RIN_M_CTRL_PC3DOWNTO2_intermed_3;
IRIN_ADDR3DOWNTO2_intermed_1 <= IRIN.ADDR( 3 DOWNTO 2 );
IRIN_ADDR3DOWNTO2_intermed_2 <= IRIN_ADDR3DOWNTO2_intermed_1;
EX_JUMP_ADDRESS3DOWNTO2_shadow_intermed_1 <= EX_JUMP_ADDRESS3DOWNTO2_shadow;
EX_ADD_RES32DOWNTO34DOWNTO3_shadow_intermed_1 <= EX_ADD_RES32DOWNTO34DOWNTO3_shadow;
RIN_A_CTRL_PC3DOWNTO2_intermed_1 <= RIN.A.CTRL.PC( 3 DOWNTO 2 );
RIN_A_CTRL_PC3DOWNTO2_intermed_2 <= RIN_A_CTRL_PC3DOWNTO2_intermed_1;
RIN_A_CTRL_PC3DOWNTO2_intermed_3 <= RIN_A_CTRL_PC3DOWNTO2_intermed_2;
RIN_A_CTRL_PC3DOWNTO2_intermed_4 <= RIN_A_CTRL_PC3DOWNTO2_intermed_3;
RIN_A_CTRL_PC3DOWNTO2_intermed_5 <= RIN_A_CTRL_PC3DOWNTO2_intermed_4;
RIN_A_CTRL_PC3DOWNTO2_intermed_6 <= RIN_A_CTRL_PC3DOWNTO2_intermed_5;
XC_TRAP_ADDRESS3DOWNTO2_shadow_intermed_1 <= XC_TRAP_ADDRESS3DOWNTO2_shadow;
V_F_PC3DOWNTO2_shadow_intermed_1 <= V_F_PC3DOWNTO2_shadow;
V_A_CTRL_PC3DOWNTO2_shadow_intermed_1 <= V_A_CTRL_PC3DOWNTO2_shadow;
V_A_CTRL_PC3DOWNTO2_shadow_intermed_2 <= V_A_CTRL_PC3DOWNTO2_shadow_intermed_1;
V_A_CTRL_PC3DOWNTO2_shadow_intermed_3 <= V_A_CTRL_PC3DOWNTO2_shadow_intermed_2;
V_A_CTRL_PC3DOWNTO2_shadow_intermed_4 <= V_A_CTRL_PC3DOWNTO2_shadow_intermed_3;
V_A_CTRL_PC3DOWNTO2_shadow_intermed_5 <= V_A_CTRL_PC3DOWNTO2_shadow_intermed_4;
V_A_CTRL_PC3DOWNTO2_shadow_intermed_6 <= V_A_CTRL_PC3DOWNTO2_shadow_intermed_5;
IR_ADDR3DOWNTO2_intermed_1 <= IR.ADDR( 3 DOWNTO 2 );
V_M_CTRL_PC3DOWNTO2_shadow_intermed_1 <= V_M_CTRL_PC3DOWNTO2_shadow;
V_M_CTRL_PC3DOWNTO2_shadow_intermed_2 <= V_M_CTRL_PC3DOWNTO2_shadow_intermed_1;
V_M_CTRL_PC3DOWNTO2_shadow_intermed_3 <= V_M_CTRL_PC3DOWNTO2_shadow_intermed_2;
V_M_CTRL_PC3DOWNTO2_shadow_intermed_4 <= V_M_CTRL_PC3DOWNTO2_shadow_intermed_3;
R_X_CTRL_PC3DOWNTO2_intermed_1 <= R.X.CTRL.PC( 3 DOWNTO 2 );
R_X_CTRL_PC3DOWNTO2_intermed_2 <= R_X_CTRL_PC3DOWNTO2_intermed_1;
RIN_E_CTRL_PC3DOWNTO2_intermed_1 <= RIN.E.CTRL.PC( 3 DOWNTO 2 );
RIN_E_CTRL_PC3DOWNTO2_intermed_2 <= RIN_E_CTRL_PC3DOWNTO2_intermed_1;
RIN_E_CTRL_PC3DOWNTO2_intermed_3 <= RIN_E_CTRL_PC3DOWNTO2_intermed_2;
RIN_E_CTRL_PC3DOWNTO2_intermed_4 <= RIN_E_CTRL_PC3DOWNTO2_intermed_3;
RIN_E_CTRL_PC3DOWNTO2_intermed_5 <= RIN_E_CTRL_PC3DOWNTO2_intermed_4;
RIN_F_PC3DOWNTO2_intermed_1 <= RIN.F.PC( 3 DOWNTO 2 );
RIN_X_ANNUL_ALL_intermed_1 <= RIN.X.ANNUL_ALL;
RIN_X_DEBUG_intermed_1 <= RIN.X.DEBUG;
RIN_D_PC_intermed_1 <= RIN.D.PC;
RIN_D_PC_intermed_2 <= RIN_D_PC_intermed_1;
RIN_D_PC_intermed_3 <= RIN_D_PC_intermed_2;
RIN_D_PC_intermed_4 <= RIN_D_PC_intermed_3;
RIN_D_PC_intermed_5 <= RIN_D_PC_intermed_4;
RIN_A_CTRL_PC_intermed_1 <= RIN.A.CTRL.PC;
RIN_A_CTRL_PC_intermed_2 <= RIN_A_CTRL_PC_intermed_1;
RIN_A_CTRL_PC_intermed_3 <= RIN_A_CTRL_PC_intermed_2;
RIN_A_CTRL_PC_intermed_4 <= RIN_A_CTRL_PC_intermed_3;
R_A_CTRL_PC_intermed_1 <= R.A.CTRL.PC;
R_A_CTRL_PC_intermed_2 <= R_A_CTRL_PC_intermed_1;
R_A_CTRL_PC_intermed_3 <= R_A_CTRL_PC_intermed_2;
V_E_CTRL_PC_shadow_intermed_1 <= V_E_CTRL_PC_shadow;
V_E_CTRL_PC_shadow_intermed_2 <= V_E_CTRL_PC_shadow_intermed_1;
V_E_CTRL_PC_shadow_intermed_3 <= V_E_CTRL_PC_shadow_intermed_2;
R_M_CTRL_PC_intermed_1 <= R.M.CTRL.PC;
R_E_CTRL_PC_intermed_1 <= R.E.CTRL.PC;
R_E_CTRL_PC_intermed_2 <= R_E_CTRL_PC_intermed_1;
RIN_M_CTRL_PC_intermed_1 <= RIN.M.CTRL.PC;
RIN_M_CTRL_PC_intermed_2 <= RIN_M_CTRL_PC_intermed_1;
V_X_CTRL_PC_shadow_intermed_1 <= V_X_CTRL_PC_shadow;
V_M_CTRL_PC_shadow_intermed_1 <= V_M_CTRL_PC_shadow;
V_M_CTRL_PC_shadow_intermed_2 <= V_M_CTRL_PC_shadow_intermed_1;
V_A_CTRL_PC_shadow_intermed_1 <= V_A_CTRL_PC_shadow;
V_A_CTRL_PC_shadow_intermed_2 <= V_A_CTRL_PC_shadow_intermed_1;
V_A_CTRL_PC_shadow_intermed_3 <= V_A_CTRL_PC_shadow_intermed_2;
V_A_CTRL_PC_shadow_intermed_4 <= V_A_CTRL_PC_shadow_intermed_3;
R_D_PC_intermed_1 <= R.D.PC;
R_D_PC_intermed_2 <= R_D_PC_intermed_1;
R_D_PC_intermed_3 <= R_D_PC_intermed_2;
R_D_PC_intermed_4 <= R_D_PC_intermed_3;
RIN_E_CTRL_PC_intermed_1 <= RIN.E.CTRL.PC;
RIN_E_CTRL_PC_intermed_2 <= RIN_E_CTRL_PC_intermed_1;
RIN_E_CTRL_PC_intermed_3 <= RIN_E_CTRL_PC_intermed_2;
RIN_X_CTRL_PC_intermed_1 <= RIN.X.CTRL.PC;
V_D_PC_shadow_intermed_1 <= V_D_PC_shadow;
V_D_PC_shadow_intermed_2 <= V_D_PC_shadow_intermed_1;
V_D_PC_shadow_intermed_3 <= V_D_PC_shadow_intermed_2;
V_D_PC_shadow_intermed_4 <= V_D_PC_shadow_intermed_3;
V_D_PC_shadow_intermed_5 <= V_D_PC_shadow_intermed_4;
IRIN_ADDR_intermed_1 <= IRIN.ADDR;
V_E_CTRL_TT_shadow_intermed_1 <= V_E_CTRL_TT_shadow;
V_E_CTRL_TT_shadow_intermed_2 <= V_E_CTRL_TT_shadow_intermed_1;
V_E_CTRL_TT_shadow_intermed_3 <= V_E_CTRL_TT_shadow_intermed_2;
V_X_CTRL_TT_shadow_intermed_1 <= V_X_CTRL_TT_shadow;
RIN_A_CTRL_TT_intermed_1 <= RIN.A.CTRL.TT;
RIN_A_CTRL_TT_intermed_2 <= RIN_A_CTRL_TT_intermed_1;
RIN_A_CTRL_TT_intermed_3 <= RIN_A_CTRL_TT_intermed_2;
RIN_A_CTRL_TT_intermed_4 <= RIN_A_CTRL_TT_intermed_3;
R_A_CTRL_TT_intermed_1 <= R.A.CTRL.TT;
R_A_CTRL_TT_intermed_2 <= R_A_CTRL_TT_intermed_1;
R_A_CTRL_TT_intermed_3 <= R_A_CTRL_TT_intermed_2;
R_M_CTRL_TT_intermed_1 <= R.M.CTRL.TT;
RIN_X_RESULT6DOWNTO0_intermed_1 <= RIN.X.RESULT ( 6 DOWNTO 0 );
DSUIN_TT_intermed_1 <= DSUIN.TT;
R_E_CTRL_TT_intermed_1 <= R.E.CTRL.TT;
R_E_CTRL_TT_intermed_2 <= R_E_CTRL_TT_intermed_1;
RIN_M_CTRL_TT_intermed_1 <= RIN.M.CTRL.TT;
RIN_M_CTRL_TT_intermed_2 <= RIN_M_CTRL_TT_intermed_1;
V_X_RESULT6DOWNTO0_shadow_intermed_1 <= V_X_RESULT6DOWNTO0_shadow;
V_X_RESULT6DOWNTO0_shadow_intermed_1 <= V_X_RESULT6DOWNTO0_shadow;
V_X_RESULT6DOWNTO0_shadow_intermed_2 <= V_X_RESULT6DOWNTO0_shadow_intermed_1;
RIN_X_RESULT6DOWNTO0_intermed_1 <= RIN.X.RESULT( 6 DOWNTO 0 );
RIN_X_RESULT6DOWNTO0_intermed_2 <= RIN_X_RESULT6DOWNTO0_intermed_1;
RIN_E_CTRL_TT_intermed_1 <= RIN.E.CTRL.TT;
RIN_E_CTRL_TT_intermed_2 <= RIN_E_CTRL_TT_intermed_1;
RIN_E_CTRL_TT_intermed_3 <= RIN_E_CTRL_TT_intermed_2;
V_M_CTRL_TT_shadow_intermed_1 <= V_M_CTRL_TT_shadow;
V_M_CTRL_TT_shadow_intermed_2 <= V_M_CTRL_TT_shadow_intermed_1;
R_X_RESULT6DOWNTO0_intermed_1 <= R.X.RESULT( 6 DOWNTO 0 );
V_A_CTRL_TT_shadow_intermed_1 <= V_A_CTRL_TT_shadow;
V_A_CTRL_TT_shadow_intermed_2 <= V_A_CTRL_TT_shadow_intermed_1;
V_A_CTRL_TT_shadow_intermed_3 <= V_A_CTRL_TT_shadow_intermed_2;
V_A_CTRL_TT_shadow_intermed_4 <= V_A_CTRL_TT_shadow_intermed_3;
RIN_X_CTRL_TT_intermed_1 <= RIN.X.CTRL.TT;
RPIN_PWD_intermed_1 <= RPIN.PWD;
IRIN_PWD_intermed_1 <= IRIN.PWD;
V_E_CTRL_TT_shadow_intermed_1 <= V_E_CTRL_TT_shadow;
V_E_CTRL_TT_shadow_intermed_2 <= V_E_CTRL_TT_shadow_intermed_1;
V_E_CTRL_TT_shadow_intermed_3 <= V_E_CTRL_TT_shadow_intermed_2;
V_X_CTRL_TT_shadow_intermed_1 <= V_X_CTRL_TT_shadow;
RIN_A_CTRL_TT_intermed_1 <= RIN.A.CTRL.TT;
RIN_A_CTRL_TT_intermed_2 <= RIN_A_CTRL_TT_intermed_1;
RIN_A_CTRL_TT_intermed_3 <= RIN_A_CTRL_TT_intermed_2;
RIN_A_CTRL_TT_intermed_4 <= RIN_A_CTRL_TT_intermed_3;
R_A_CTRL_TT_intermed_1 <= R.A.CTRL.TT;
R_A_CTRL_TT_intermed_2 <= R_A_CTRL_TT_intermed_1;
R_A_CTRL_TT_intermed_3 <= R_A_CTRL_TT_intermed_2;
R_M_CTRL_TT_intermed_1 <= R.M.CTRL.TT;
RIN_X_RESULT6DOWNTO0_intermed_1 <= RIN.X.RESULT ( 6 DOWNTO 0 );
R_E_CTRL_TT_intermed_1 <= R.E.CTRL.TT;
R_E_CTRL_TT_intermed_2 <= R_E_CTRL_TT_intermed_1;
RIN_M_CTRL_TT_intermed_1 <= RIN.M.CTRL.TT;
RIN_M_CTRL_TT_intermed_2 <= RIN_M_CTRL_TT_intermed_1;
V_X_RESULT6DOWNTO0_shadow_intermed_1 <= V_X_RESULT6DOWNTO0_shadow;
V_X_RESULT6DOWNTO0_shadow_intermed_1 <= V_X_RESULT6DOWNTO0_shadow;
V_X_RESULT6DOWNTO0_shadow_intermed_2 <= V_X_RESULT6DOWNTO0_shadow_intermed_1;
RIN_X_RESULT6DOWNTO0_intermed_1 <= RIN.X.RESULT( 6 DOWNTO 0 );
RIN_X_RESULT6DOWNTO0_intermed_2 <= RIN_X_RESULT6DOWNTO0_intermed_1;
RIN_E_CTRL_TT_intermed_1 <= RIN.E.CTRL.TT;
RIN_E_CTRL_TT_intermed_2 <= RIN_E_CTRL_TT_intermed_1;
RIN_E_CTRL_TT_intermed_3 <= RIN_E_CTRL_TT_intermed_2;
V_M_CTRL_TT_shadow_intermed_1 <= V_M_CTRL_TT_shadow;
V_M_CTRL_TT_shadow_intermed_2 <= V_M_CTRL_TT_shadow_intermed_1;
R_X_RESULT6DOWNTO0_intermed_1 <= R.X.RESULT( 6 DOWNTO 0 );
RIN_W_S_TT_intermed_1 <= RIN.W.S.TT;
V_A_CTRL_TT_shadow_intermed_1 <= V_A_CTRL_TT_shadow;
V_A_CTRL_TT_shadow_intermed_2 <= V_A_CTRL_TT_shadow_intermed_1;
V_A_CTRL_TT_shadow_intermed_3 <= V_A_CTRL_TT_shadow_intermed_2;
V_A_CTRL_TT_shadow_intermed_4 <= V_A_CTRL_TT_shadow_intermed_3;
RIN_X_CTRL_TT_intermed_1 <= RIN.X.CTRL.TT;
RIN_W_S_S_intermed_1 <= RIN.W.S.S;
RIN_W_S_PS_intermed_1 <= RIN.W.S.PS;
V_W_S_S_shadow_intermed_1 <= V_W_S_S_shadow;
RIN_W_S_S_intermed_1 <= RIN.W.S.S;
RIN_E_CTRL_RD6DOWNTO0_intermed_1 <= RIN.E.CTRL.RD( 6 DOWNTO 0 );
RIN_E_CTRL_RD6DOWNTO0_intermed_2 <= RIN_E_CTRL_RD6DOWNTO0_intermed_1;
RIN_E_CTRL_RD6DOWNTO0_intermed_3 <= RIN_E_CTRL_RD6DOWNTO0_intermed_2;
RIN_M_CTRL_RD6DOWNTO0_intermed_1 <= RIN.M.CTRL.RD( 6 DOWNTO 0 );
RIN_M_CTRL_RD6DOWNTO0_intermed_2 <= RIN_M_CTRL_RD6DOWNTO0_intermed_1;
RIN_X_CTRL_RD6DOWNTO0_intermed_1 <= RIN.X.CTRL.RD( 6 DOWNTO 0 );
V_X_CTRL_RD6DOWNTO0_shadow_intermed_1 <= V_X_CTRL_RD6DOWNTO0_shadow;
RIN_W_S_CWP_intermed_1 <= RIN.W.S.CWP;
V_M_CTRL_RD6DOWNTO0_shadow_intermed_1 <= V_M_CTRL_RD6DOWNTO0_shadow;
V_M_CTRL_RD6DOWNTO0_shadow_intermed_2 <= V_M_CTRL_RD6DOWNTO0_shadow_intermed_1;
R_E_CTRL_RD6DOWNTO0_intermed_1 <= R.E.CTRL.RD( 6 DOWNTO 0 );
R_E_CTRL_RD6DOWNTO0_intermed_2 <= R_E_CTRL_RD6DOWNTO0_intermed_1;
V_E_CTRL_RD6DOWNTO0_shadow_intermed_1 <= V_E_CTRL_RD6DOWNTO0_shadow;
V_E_CTRL_RD6DOWNTO0_shadow_intermed_2 <= V_E_CTRL_RD6DOWNTO0_shadow_intermed_1;
V_E_CTRL_RD6DOWNTO0_shadow_intermed_3 <= V_E_CTRL_RD6DOWNTO0_shadow_intermed_2;
V_A_CTRL_RD6DOWNTO0_shadow_intermed_1 <= V_A_CTRL_RD6DOWNTO0_shadow;
V_A_CTRL_RD6DOWNTO0_shadow_intermed_2 <= V_A_CTRL_RD6DOWNTO0_shadow_intermed_1;
V_A_CTRL_RD6DOWNTO0_shadow_intermed_3 <= V_A_CTRL_RD6DOWNTO0_shadow_intermed_2;
V_A_CTRL_RD6DOWNTO0_shadow_intermed_4 <= V_A_CTRL_RD6DOWNTO0_shadow_intermed_3;
R_A_CTRL_RD6DOWNTO0_intermed_1 <= R.A.CTRL.RD( 6 DOWNTO 0 );
R_A_CTRL_RD6DOWNTO0_intermed_2 <= R_A_CTRL_RD6DOWNTO0_intermed_1;
R_A_CTRL_RD6DOWNTO0_intermed_3 <= R_A_CTRL_RD6DOWNTO0_intermed_2;
RIN_A_CTRL_RD6DOWNTO0_intermed_1 <= RIN.A.CTRL.RD( 6 DOWNTO 0 );
RIN_A_CTRL_RD6DOWNTO0_intermed_2 <= RIN_A_CTRL_RD6DOWNTO0_intermed_1;
RIN_A_CTRL_RD6DOWNTO0_intermed_3 <= RIN_A_CTRL_RD6DOWNTO0_intermed_2;
RIN_A_CTRL_RD6DOWNTO0_intermed_4 <= RIN_A_CTRL_RD6DOWNTO0_intermed_3;
R_M_CTRL_RD6DOWNTO0_intermed_1 <= R.M.CTRL.RD( 6 DOWNTO 0 );
V_W_S_CWP_shadow_intermed_1 <= V_W_S_CWP_shadow;
RIN_W_S_ET_intermed_1 <= RIN.W.S.ET;
RIN_W_S_CWP_intermed_1 <= RIN.W.S.CWP;
RPIN_ERROR_intermed_1 <= RPIN.ERROR;
RIN_D_PC_intermed_1 <= RIN.D.PC;
RIN_D_PC_intermed_2 <= RIN_D_PC_intermed_1;
RIN_D_PC_intermed_3 <= RIN_D_PC_intermed_2;
RIN_D_PC_intermed_4 <= RIN_D_PC_intermed_3;
RIN_D_PC_intermed_5 <= RIN_D_PC_intermed_4;
RIN_D_PC_intermed_6 <= RIN_D_PC_intermed_5;
RIN_M_CTRL_PC31DOWNTO2_intermed_1 <= RIN.M.CTRL.PC( 31 DOWNTO 2 );
RIN_M_CTRL_PC31DOWNTO2_intermed_2 <= RIN_M_CTRL_PC31DOWNTO2_intermed_1;
RIN_M_CTRL_PC31DOWNTO2_intermed_3 <= RIN_M_CTRL_PC31DOWNTO2_intermed_2;
RIN_M_CTRL_PC31DOWNTO2_intermed_4 <= RIN_M_CTRL_PC31DOWNTO2_intermed_3;
VIR_ADDR_shadow_intermed_1 <= VIR_ADDR_shadow;
RIN_A_CTRL_PC_intermed_1 <= RIN.A.CTRL.PC;
RIN_A_CTRL_PC_intermed_2 <= RIN_A_CTRL_PC_intermed_1;
RIN_A_CTRL_PC_intermed_3 <= RIN_A_CTRL_PC_intermed_2;
RIN_A_CTRL_PC_intermed_4 <= RIN_A_CTRL_PC_intermed_3;
RIN_A_CTRL_PC_intermed_5 <= RIN_A_CTRL_PC_intermed_4;
R_A_CTRL_PC_intermed_1 <= R.A.CTRL.PC;
R_A_CTRL_PC_intermed_2 <= R_A_CTRL_PC_intermed_1;
R_A_CTRL_PC_intermed_3 <= R_A_CTRL_PC_intermed_2;
R_A_CTRL_PC_intermed_4 <= R_A_CTRL_PC_intermed_3;
V_D_PC31DOWNTO2_shadow_intermed_1 <= V_D_PC31DOWNTO2_shadow;
V_D_PC31DOWNTO2_shadow_intermed_2 <= V_D_PC31DOWNTO2_shadow_intermed_1;
V_D_PC31DOWNTO2_shadow_intermed_3 <= V_D_PC31DOWNTO2_shadow_intermed_2;
V_D_PC31DOWNTO2_shadow_intermed_4 <= V_D_PC31DOWNTO2_shadow_intermed_3;
V_D_PC31DOWNTO2_shadow_intermed_5 <= V_D_PC31DOWNTO2_shadow_intermed_4;
V_D_PC31DOWNTO2_shadow_intermed_6 <= V_D_PC31DOWNTO2_shadow_intermed_5;
V_D_PC31DOWNTO2_shadow_intermed_7 <= V_D_PC31DOWNTO2_shadow_intermed_6;
V_E_CTRL_PC_shadow_intermed_1 <= V_E_CTRL_PC_shadow;
V_E_CTRL_PC_shadow_intermed_2 <= V_E_CTRL_PC_shadow_intermed_1;
V_E_CTRL_PC_shadow_intermed_3 <= V_E_CTRL_PC_shadow_intermed_2;
V_E_CTRL_PC_shadow_intermed_4 <= V_E_CTRL_PC_shadow_intermed_3;
EX_ADD_RES32DOWNTO3_shadow_intermed_1 <= EX_ADD_RES32DOWNTO3_shadow;
XC_TRAP_ADDRESS_shadow_intermed_1 <= XC_TRAP_ADDRESS_shadow;
RIN_D_PC31DOWNTO2_intermed_1 <= RIN.D.PC( 31 DOWNTO 2 );
RIN_D_PC31DOWNTO2_intermed_2 <= RIN_D_PC31DOWNTO2_intermed_1;
RIN_D_PC31DOWNTO2_intermed_3 <= RIN_D_PC31DOWNTO2_intermed_2;
RIN_D_PC31DOWNTO2_intermed_4 <= RIN_D_PC31DOWNTO2_intermed_3;
RIN_D_PC31DOWNTO2_intermed_5 <= RIN_D_PC31DOWNTO2_intermed_4;
RIN_D_PC31DOWNTO2_intermed_6 <= RIN_D_PC31DOWNTO2_intermed_5;
RIN_D_PC31DOWNTO2_intermed_7 <= RIN_D_PC31DOWNTO2_intermed_6;
EX_ADD_RES32DOWNTO332DOWNTO3_shadow_intermed_1 <= EX_ADD_RES32DOWNTO332DOWNTO3_shadow;
V_F_PC31DOWNTO2_shadow_intermed_1 <= V_F_PC31DOWNTO2_shadow;
RIN_F_PC31DOWNTO2_intermed_1 <= RIN.F.PC( 31 DOWNTO 2 );
R_M_CTRL_PC_intermed_1 <= R.M.CTRL.PC;
R_M_CTRL_PC_intermed_2 <= R_M_CTRL_PC_intermed_1;
RIN_X_CTRL_PC31DOWNTO2_intermed_1 <= RIN.X.CTRL.PC( 31 DOWNTO 2 );
RIN_X_CTRL_PC31DOWNTO2_intermed_2 <= RIN_X_CTRL_PC31DOWNTO2_intermed_1;
RIN_X_CTRL_PC31DOWNTO2_intermed_3 <= RIN_X_CTRL_PC31DOWNTO2_intermed_2;
R_X_CTRL_PC_intermed_1 <= R.X.CTRL.PC;
R_E_CTRL_PC_intermed_1 <= R.E.CTRL.PC;
R_E_CTRL_PC_intermed_2 <= R_E_CTRL_PC_intermed_1;
R_E_CTRL_PC_intermed_3 <= R_E_CTRL_PC_intermed_2;
IRIN_ADDR31DOWNTO2_intermed_1 <= IRIN.ADDR( 31 DOWNTO 2 );
IRIN_ADDR31DOWNTO2_intermed_2 <= IRIN_ADDR31DOWNTO2_intermed_1;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO2_shadow;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_2;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_4 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_3;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_5 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_4;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_6 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_5;
RIN_M_CTRL_PC_intermed_1 <= RIN.M.CTRL.PC;
RIN_M_CTRL_PC_intermed_2 <= RIN_M_CTRL_PC_intermed_1;
RIN_M_CTRL_PC_intermed_3 <= RIN_M_CTRL_PC_intermed_2;
R_D_PC31DOWNTO2_intermed_1 <= R.D.PC( 31 DOWNTO 2 );
R_D_PC31DOWNTO2_intermed_2 <= R_D_PC31DOWNTO2_intermed_1;
R_D_PC31DOWNTO2_intermed_3 <= R_D_PC31DOWNTO2_intermed_2;
R_D_PC31DOWNTO2_intermed_4 <= R_D_PC31DOWNTO2_intermed_3;
R_D_PC31DOWNTO2_intermed_5 <= R_D_PC31DOWNTO2_intermed_4;
R_D_PC31DOWNTO2_intermed_6 <= R_D_PC31DOWNTO2_intermed_5;
VIR_ADDR31DOWNTO2_shadow_intermed_1 <= VIR_ADDR31DOWNTO2_shadow;
VIR_ADDR31DOWNTO2_shadow_intermed_2 <= VIR_ADDR31DOWNTO2_shadow_intermed_1;
V_X_CTRL_PC_shadow_intermed_1 <= V_X_CTRL_PC_shadow;
V_X_CTRL_PC_shadow_intermed_2 <= V_X_CTRL_PC_shadow_intermed_1;
R_M_CTRL_PC31DOWNTO2_intermed_1 <= R.M.CTRL.PC( 31 DOWNTO 2 );
R_M_CTRL_PC31DOWNTO2_intermed_2 <= R_M_CTRL_PC31DOWNTO2_intermed_1;
R_M_CTRL_PC31DOWNTO2_intermed_3 <= R_M_CTRL_PC31DOWNTO2_intermed_2;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_E_CTRL_PC31DOWNTO2_shadow;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_2;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_4 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_3;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_5 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_4;
RIN_A_CTRL_PC31DOWNTO2_intermed_1 <= RIN.A.CTRL.PC( 31 DOWNTO 2 );
RIN_A_CTRL_PC31DOWNTO2_intermed_2 <= RIN_A_CTRL_PC31DOWNTO2_intermed_1;
RIN_A_CTRL_PC31DOWNTO2_intermed_3 <= RIN_A_CTRL_PC31DOWNTO2_intermed_2;
RIN_A_CTRL_PC31DOWNTO2_intermed_4 <= RIN_A_CTRL_PC31DOWNTO2_intermed_3;
RIN_A_CTRL_PC31DOWNTO2_intermed_5 <= RIN_A_CTRL_PC31DOWNTO2_intermed_4;
RIN_A_CTRL_PC31DOWNTO2_intermed_6 <= RIN_A_CTRL_PC31DOWNTO2_intermed_5;
R_A_CTRL_PC31DOWNTO2_intermed_1 <= R.A.CTRL.PC( 31 DOWNTO 2 );
R_A_CTRL_PC31DOWNTO2_intermed_2 <= R_A_CTRL_PC31DOWNTO2_intermed_1;
R_A_CTRL_PC31DOWNTO2_intermed_3 <= R_A_CTRL_PC31DOWNTO2_intermed_2;
R_A_CTRL_PC31DOWNTO2_intermed_4 <= R_A_CTRL_PC31DOWNTO2_intermed_3;
R_A_CTRL_PC31DOWNTO2_intermed_5 <= R_A_CTRL_PC31DOWNTO2_intermed_4;
V_M_CTRL_PC_shadow_intermed_1 <= V_M_CTRL_PC_shadow;
V_M_CTRL_PC_shadow_intermed_2 <= V_M_CTRL_PC_shadow_intermed_1;
V_M_CTRL_PC_shadow_intermed_3 <= V_M_CTRL_PC_shadow_intermed_2;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_M_CTRL_PC31DOWNTO2_shadow;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_M_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_M_CTRL_PC31DOWNTO2_shadow_intermed_2;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_4 <= V_M_CTRL_PC31DOWNTO2_shadow_intermed_3;
V_A_CTRL_PC_shadow_intermed_1 <= V_A_CTRL_PC_shadow;
V_A_CTRL_PC_shadow_intermed_2 <= V_A_CTRL_PC_shadow_intermed_1;
V_A_CTRL_PC_shadow_intermed_3 <= V_A_CTRL_PC_shadow_intermed_2;
V_A_CTRL_PC_shadow_intermed_4 <= V_A_CTRL_PC_shadow_intermed_3;
V_A_CTRL_PC_shadow_intermed_5 <= V_A_CTRL_PC_shadow_intermed_4;
R_X_CTRL_PC31DOWNTO2_intermed_1 <= R.X.CTRL.PC( 31 DOWNTO 2 );
R_X_CTRL_PC31DOWNTO2_intermed_2 <= R_X_CTRL_PC31DOWNTO2_intermed_1;
R_D_PC_intermed_1 <= R.D.PC;
R_D_PC_intermed_2 <= R_D_PC_intermed_1;
R_D_PC_intermed_3 <= R_D_PC_intermed_2;
R_D_PC_intermed_4 <= R_D_PC_intermed_3;
R_D_PC_intermed_5 <= R_D_PC_intermed_4;
RIN_F_PC_intermed_1 <= RIN.F.PC;
XC_TRAP_ADDRESS31DOWNTO2_shadow_intermed_1 <= XC_TRAP_ADDRESS31DOWNTO2_shadow;
RIN_E_CTRL_PC_intermed_1 <= RIN.E.CTRL.PC;
RIN_E_CTRL_PC_intermed_2 <= RIN_E_CTRL_PC_intermed_1;
RIN_E_CTRL_PC_intermed_3 <= RIN_E_CTRL_PC_intermed_2;
RIN_E_CTRL_PC_intermed_4 <= RIN_E_CTRL_PC_intermed_3;
RIN_X_CTRL_PC_intermed_1 <= RIN.X.CTRL.PC;
RIN_X_CTRL_PC_intermed_2 <= RIN_X_CTRL_PC_intermed_1;
V_D_PC_shadow_intermed_1 <= V_D_PC_shadow;
V_D_PC_shadow_intermed_2 <= V_D_PC_shadow_intermed_1;
V_D_PC_shadow_intermed_3 <= V_D_PC_shadow_intermed_2;
V_D_PC_shadow_intermed_4 <= V_D_PC_shadow_intermed_3;
V_D_PC_shadow_intermed_5 <= V_D_PC_shadow_intermed_4;
V_D_PC_shadow_intermed_6 <= V_D_PC_shadow_intermed_5;
R_E_CTRL_PC31DOWNTO2_intermed_1 <= R.E.CTRL.PC( 31 DOWNTO 2 );
R_E_CTRL_PC31DOWNTO2_intermed_2 <= R_E_CTRL_PC31DOWNTO2_intermed_1;
R_E_CTRL_PC31DOWNTO2_intermed_3 <= R_E_CTRL_PC31DOWNTO2_intermed_2;
R_E_CTRL_PC31DOWNTO2_intermed_4 <= R_E_CTRL_PC31DOWNTO2_intermed_3;
IRIN_ADDR_intermed_1 <= IRIN.ADDR;
EX_JUMP_ADDRESS_shadow_intermed_1 <= EX_JUMP_ADDRESS_shadow;
EX_JUMP_ADDRESS31DOWNTO2_shadow_intermed_1 <= EX_JUMP_ADDRESS31DOWNTO2_shadow;
IR_ADDR31DOWNTO2_intermed_1 <= IR.ADDR( 31 DOWNTO 2 );
V_F_PC_shadow_intermed_1 <= V_F_PC_shadow;
RIN_E_CTRL_PC31DOWNTO2_intermed_1 <= RIN.E.CTRL.PC( 31 DOWNTO 2 );
RIN_E_CTRL_PC31DOWNTO2_intermed_2 <= RIN_E_CTRL_PC31DOWNTO2_intermed_1;
RIN_E_CTRL_PC31DOWNTO2_intermed_3 <= RIN_E_CTRL_PC31DOWNTO2_intermed_2;
RIN_E_CTRL_PC31DOWNTO2_intermed_4 <= RIN_E_CTRL_PC31DOWNTO2_intermed_3;
RIN_E_CTRL_PC31DOWNTO2_intermed_5 <= RIN_E_CTRL_PC31DOWNTO2_intermed_4;
V_X_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_X_CTRL_PC31DOWNTO2_shadow;
V_X_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_X_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_X_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_X_CTRL_PC31DOWNTO2_shadow_intermed_2;
DSUIN_TBUFCNT_intermed_1 <= DSUIN.TBUFCNT;
RIN_W_EXCEPT_intermed_1 <= RIN.W.EXCEPT;
RIN_M_CTRL_PC31DOWNTO2_intermed_1 <= RIN.M.CTRL.PC( 31 DOWNTO 2 );
RIN_M_CTRL_PC31DOWNTO2_intermed_2 <= RIN_M_CTRL_PC31DOWNTO2_intermed_1;
RIN_M_CTRL_PC31DOWNTO2_intermed_3 <= RIN_M_CTRL_PC31DOWNTO2_intermed_2;
RIN_X_RESULT_intermed_1 <= RIN.X.RESULT;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_M_CTRL_PC31DOWNTO2_shadow;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_M_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_X_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_X_CTRL_PC31DOWNTO2_shadow;
R_E_CTRL_PC31DOWNTO2_intermed_1 <= R.E.CTRL.PC ( 31 DOWNTO 2 );
R_E_CTRL_PC31DOWNTO2_intermed_2 <= R_E_CTRL_PC31DOWNTO2_intermed_1;
V_D_PC31DOWNTO2_shadow_intermed_1 <= V_D_PC31DOWNTO2_shadow;
V_D_PC31DOWNTO2_shadow_intermed_2 <= V_D_PC31DOWNTO2_shadow_intermed_1;
V_D_PC31DOWNTO2_shadow_intermed_3 <= V_D_PC31DOWNTO2_shadow_intermed_2;
V_D_PC31DOWNTO2_shadow_intermed_4 <= V_D_PC31DOWNTO2_shadow_intermed_3;
V_D_PC31DOWNTO2_shadow_intermed_5 <= V_D_PC31DOWNTO2_shadow_intermed_4;
RIN_D_PC31DOWNTO2_intermed_1 <= RIN.D.PC( 31 DOWNTO 2 );
RIN_D_PC31DOWNTO2_intermed_2 <= RIN_D_PC31DOWNTO2_intermed_1;
RIN_D_PC31DOWNTO2_intermed_3 <= RIN_D_PC31DOWNTO2_intermed_2;
RIN_D_PC31DOWNTO2_intermed_4 <= RIN_D_PC31DOWNTO2_intermed_3;
RIN_D_PC31DOWNTO2_intermed_5 <= RIN_D_PC31DOWNTO2_intermed_4;
V_X_DATA0_shadow_intermed_1 <= V_X_DATA0_shadow;
RIN_E_CTRL_PC31DOWNTO2_intermed_1 <= RIN.E.CTRL.PC ( 31 DOWNTO 2 );
RIN_E_CTRL_PC31DOWNTO2_intermed_2 <= RIN_E_CTRL_PC31DOWNTO2_intermed_1;
RIN_E_CTRL_PC31DOWNTO2_intermed_3 <= RIN_E_CTRL_PC31DOWNTO2_intermed_2;
RIN_A_CTRL_PC31DOWNTO2_intermed_1 <= RIN.A.CTRL.PC ( 31 DOWNTO 2 );
RIN_A_CTRL_PC31DOWNTO2_intermed_2 <= RIN_A_CTRL_PC31DOWNTO2_intermed_1;
RIN_A_CTRL_PC31DOWNTO2_intermed_3 <= RIN_A_CTRL_PC31DOWNTO2_intermed_2;
RIN_A_CTRL_PC31DOWNTO2_intermed_4 <= RIN_A_CTRL_PC31DOWNTO2_intermed_3;
RIN_X_CTRL_PC31DOWNTO2_intermed_1 <= RIN.X.CTRL.PC ( 31 DOWNTO 2 );
RIN_X_CTRL_PC31DOWNTO2_intermed_1 <= RIN.X.CTRL.PC( 31 DOWNTO 2 );
RIN_X_CTRL_PC31DOWNTO2_intermed_2 <= RIN_X_CTRL_PC31DOWNTO2_intermed_1;
RIN_M_CTRL_PC31DOWNTO2_intermed_1 <= RIN.M.CTRL.PC ( 31 DOWNTO 2 );
RIN_M_CTRL_PC31DOWNTO2_intermed_2 <= RIN_M_CTRL_PC31DOWNTO2_intermed_1;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO2_shadow;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_2;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_4 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_3;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_5 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_4;
R_D_PC31DOWNTO2_intermed_1 <= R.D.PC( 31 DOWNTO 2 );
R_D_PC31DOWNTO2_intermed_2 <= R_D_PC31DOWNTO2_intermed_1;
R_D_PC31DOWNTO2_intermed_3 <= R_D_PC31DOWNTO2_intermed_2;
R_D_PC31DOWNTO2_intermed_4 <= R_D_PC31DOWNTO2_intermed_3;
R_M_CTRL_PC31DOWNTO2_intermed_1 <= R.M.CTRL.PC ( 31 DOWNTO 2 );
V_X_DATA0_shadow_intermed_1 <= V_X_DATA0_shadow;
V_X_DATA0_shadow_intermed_2 <= V_X_DATA0_shadow_intermed_1;
R_M_CTRL_PC31DOWNTO2_intermed_1 <= R.M.CTRL.PC( 31 DOWNTO 2 );
R_M_CTRL_PC31DOWNTO2_intermed_2 <= R_M_CTRL_PC31DOWNTO2_intermed_1;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_E_CTRL_PC31DOWNTO2_shadow;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_2;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_4 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_3;
RIN_A_CTRL_PC31DOWNTO2_intermed_1 <= RIN.A.CTRL.PC( 31 DOWNTO 2 );
RIN_A_CTRL_PC31DOWNTO2_intermed_2 <= RIN_A_CTRL_PC31DOWNTO2_intermed_1;
RIN_A_CTRL_PC31DOWNTO2_intermed_3 <= RIN_A_CTRL_PC31DOWNTO2_intermed_2;
RIN_A_CTRL_PC31DOWNTO2_intermed_4 <= RIN_A_CTRL_PC31DOWNTO2_intermed_3;
RIN_A_CTRL_PC31DOWNTO2_intermed_5 <= RIN_A_CTRL_PC31DOWNTO2_intermed_4;
R_A_CTRL_PC31DOWNTO2_intermed_1 <= R.A.CTRL.PC( 31 DOWNTO 2 );
R_A_CTRL_PC31DOWNTO2_intermed_2 <= R_A_CTRL_PC31DOWNTO2_intermed_1;
R_A_CTRL_PC31DOWNTO2_intermed_3 <= R_A_CTRL_PC31DOWNTO2_intermed_2;
R_A_CTRL_PC31DOWNTO2_intermed_4 <= R_A_CTRL_PC31DOWNTO2_intermed_3;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_M_CTRL_PC31DOWNTO2_shadow;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_M_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_M_CTRL_PC31DOWNTO2_shadow_intermed_2;
RIN_X_DATA0_intermed_1 <= RIN.X.DATA ( 0 );
R_A_CTRL_PC31DOWNTO2_intermed_1 <= R.A.CTRL.PC ( 31 DOWNTO 2 );
R_A_CTRL_PC31DOWNTO2_intermed_2 <= R_A_CTRL_PC31DOWNTO2_intermed_1;
R_A_CTRL_PC31DOWNTO2_intermed_3 <= R_A_CTRL_PC31DOWNTO2_intermed_2;
V_X_RESULT_shadow_intermed_1 <= V_X_RESULT_shadow;
R_X_CTRL_PC31DOWNTO2_intermed_1 <= R.X.CTRL.PC( 31 DOWNTO 2 );
RIN_W_RESULT_intermed_1 <= RIN.W.RESULT;
R_X_DATA0_intermed_1 <= R.X.DATA( 0 );
V_A_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO2_shadow;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_2;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_4 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_3;
R_E_CTRL_PC31DOWNTO2_intermed_1 <= R.E.CTRL.PC( 31 DOWNTO 2 );
R_E_CTRL_PC31DOWNTO2_intermed_2 <= R_E_CTRL_PC31DOWNTO2_intermed_1;
R_E_CTRL_PC31DOWNTO2_intermed_3 <= R_E_CTRL_PC31DOWNTO2_intermed_2;
RIN_E_CTRL_PC31DOWNTO2_intermed_1 <= RIN.E.CTRL.PC( 31 DOWNTO 2 );
RIN_E_CTRL_PC31DOWNTO2_intermed_2 <= RIN_E_CTRL_PC31DOWNTO2_intermed_1;
RIN_E_CTRL_PC31DOWNTO2_intermed_3 <= RIN_E_CTRL_PC31DOWNTO2_intermed_2;
RIN_E_CTRL_PC31DOWNTO2_intermed_4 <= RIN_E_CTRL_PC31DOWNTO2_intermed_3;
V_X_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_X_CTRL_PC31DOWNTO2_shadow;
V_X_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_X_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_E_CTRL_PC31DOWNTO2_shadow;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_2;
RIN_X_DATA0_intermed_1 <= RIN.X.DATA( 0 );
RIN_X_DATA0_intermed_2 <= RIN_X_DATA0_intermed_1;
V_M_CTRL_RD7DOWNTO0_shadow_intermed_1 <= V_M_CTRL_RD7DOWNTO0_shadow;
V_M_CTRL_RD7DOWNTO0_shadow_intermed_2 <= V_M_CTRL_RD7DOWNTO0_shadow_intermed_1;
V_E_CTRL_RD7DOWNTO0_shadow_intermed_1 <= V_E_CTRL_RD7DOWNTO0_shadow;
V_E_CTRL_RD7DOWNTO0_shadow_intermed_2 <= V_E_CTRL_RD7DOWNTO0_shadow_intermed_1;
V_E_CTRL_RD7DOWNTO0_shadow_intermed_3 <= V_E_CTRL_RD7DOWNTO0_shadow_intermed_2;
R_E_CTRL_RD7DOWNTO0_intermed_1 <= R.E.CTRL.RD ( 7 DOWNTO 0 );
R_E_CTRL_RD7DOWNTO0_intermed_2 <= R_E_CTRL_RD7DOWNTO0_intermed_1;
V_X_CTRL_RD7DOWNTO0_shadow_intermed_1 <= V_X_CTRL_RD7DOWNTO0_shadow;
V_A_CTRL_RD7DOWNTO0_shadow_intermed_1 <= V_A_CTRL_RD7DOWNTO0_shadow;
V_A_CTRL_RD7DOWNTO0_shadow_intermed_2 <= V_A_CTRL_RD7DOWNTO0_shadow_intermed_1;
V_A_CTRL_RD7DOWNTO0_shadow_intermed_3 <= V_A_CTRL_RD7DOWNTO0_shadow_intermed_2;
V_A_CTRL_RD7DOWNTO0_shadow_intermed_4 <= V_A_CTRL_RD7DOWNTO0_shadow_intermed_3;
RIN_W_WA_intermed_1 <= RIN.W.WA;
RIN_A_CTRL_RD7DOWNTO0_intermed_1 <= RIN.A.CTRL.RD ( 7 DOWNTO 0 );
RIN_A_CTRL_RD7DOWNTO0_intermed_2 <= RIN_A_CTRL_RD7DOWNTO0_intermed_1;
RIN_A_CTRL_RD7DOWNTO0_intermed_3 <= RIN_A_CTRL_RD7DOWNTO0_intermed_2;
RIN_A_CTRL_RD7DOWNTO0_intermed_4 <= RIN_A_CTRL_RD7DOWNTO0_intermed_3;
R_M_CTRL_RD7DOWNTO0_intermed_1 <= R.M.CTRL.RD ( 7 DOWNTO 0 );
R_A_CTRL_RD7DOWNTO0_intermed_1 <= R.A.CTRL.RD ( 7 DOWNTO 0 );
R_A_CTRL_RD7DOWNTO0_intermed_2 <= R_A_CTRL_RD7DOWNTO0_intermed_1;
R_A_CTRL_RD7DOWNTO0_intermed_3 <= R_A_CTRL_RD7DOWNTO0_intermed_2;
RIN_E_CTRL_RD7DOWNTO0_intermed_1 <= RIN.E.CTRL.RD ( 7 DOWNTO 0 );
RIN_E_CTRL_RD7DOWNTO0_intermed_2 <= RIN_E_CTRL_RD7DOWNTO0_intermed_1;
RIN_E_CTRL_RD7DOWNTO0_intermed_3 <= RIN_E_CTRL_RD7DOWNTO0_intermed_2;
RIN_X_CTRL_RD7DOWNTO0_intermed_1 <= RIN.X.CTRL.RD ( 7 DOWNTO 0 );
RIN_M_CTRL_RD7DOWNTO0_intermed_1 <= RIN.M.CTRL.RD ( 7 DOWNTO 0 );
RIN_M_CTRL_RD7DOWNTO0_intermed_2 <= RIN_M_CTRL_RD7DOWNTO0_intermed_1;
RIN_A_CTRL_ANNUL_intermed_1 <= RIN.A.CTRL.ANNUL;
RIN_A_CTRL_ANNUL_intermed_2 <= RIN_A_CTRL_ANNUL_intermed_1;
RIN_A_CTRL_ANNUL_intermed_3 <= RIN_A_CTRL_ANNUL_intermed_2;
RIN_A_CTRL_ANNUL_intermed_4 <= RIN_A_CTRL_ANNUL_intermed_3;
RIN_A_CTRL_ANNUL_intermed_5 <= RIN_A_CTRL_ANNUL_intermed_4;
R_A_CTRL_ANNUL_intermed_1 <= R.A.CTRL.ANNUL;
R_A_CTRL_ANNUL_intermed_2 <= R_A_CTRL_ANNUL_intermed_1;
R_A_CTRL_ANNUL_intermed_3 <= R_A_CTRL_ANNUL_intermed_2;
R_A_CTRL_ANNUL_intermed_4 <= R_A_CTRL_ANNUL_intermed_3;
R_X_ANNUL_ALL_intermed_1 <= R.X.ANNUL_ALL;
R_X_ANNUL_ALL_intermed_2 <= R_X_ANNUL_ALL_intermed_1;
R_X_ANNUL_ALL_intermed_3 <= R_X_ANNUL_ALL_intermed_2;
R_X_ANNUL_ALL_intermed_4 <= R_X_ANNUL_ALL_intermed_3;
V_X_CTRL_WREG_shadow_intermed_1 <= V_X_CTRL_WREG_shadow;
RIN_X_CTRL_WREG_intermed_1 <= RIN.X.CTRL.WREG;
RIN_M_CTRL_WREG_intermed_1 <= RIN.M.CTRL.WREG;
RIN_M_CTRL_WREG_intermed_2 <= RIN_M_CTRL_WREG_intermed_1;
RIN_A_CTRL_WREG_intermed_1 <= RIN.A.CTRL.WREG;
RIN_A_CTRL_WREG_intermed_2 <= RIN_A_CTRL_WREG_intermed_1;
RIN_A_CTRL_WREG_intermed_3 <= RIN_A_CTRL_WREG_intermed_2;
RIN_A_CTRL_WREG_intermed_4 <= RIN_A_CTRL_WREG_intermed_3;
V_A_CTRL_WREG_shadow_intermed_1 <= V_A_CTRL_WREG_shadow;
V_A_CTRL_WREG_shadow_intermed_2 <= V_A_CTRL_WREG_shadow_intermed_1;
V_A_CTRL_WREG_shadow_intermed_3 <= V_A_CTRL_WREG_shadow_intermed_2;
V_A_CTRL_WREG_shadow_intermed_4 <= V_A_CTRL_WREG_shadow_intermed_3;
R_A_CTRL_WREG_intermed_1 <= R.A.CTRL.WREG;
R_A_CTRL_WREG_intermed_2 <= R_A_CTRL_WREG_intermed_1;
R_A_CTRL_WREG_intermed_3 <= R_A_CTRL_WREG_intermed_2;
RIN_W_WREG_intermed_1 <= RIN.W.WREG;
V_X_ANNUL_ALL_shadow_intermed_1 <= V_X_ANNUL_ALL_shadow;
V_X_ANNUL_ALL_shadow_intermed_2 <= V_X_ANNUL_ALL_shadow_intermed_1;
V_X_ANNUL_ALL_shadow_intermed_3 <= V_X_ANNUL_ALL_shadow_intermed_2;
V_X_ANNUL_ALL_shadow_intermed_4 <= V_X_ANNUL_ALL_shadow_intermed_3;
R_M_CTRL_WREG_intermed_1 <= R.M.CTRL.WREG;
RIN_X_ANNUL_ALL_intermed_1 <= RIN.X.ANNUL_ALL;
RIN_X_ANNUL_ALL_intermed_2 <= RIN_X_ANNUL_ALL_intermed_1;
RIN_X_ANNUL_ALL_intermed_3 <= RIN_X_ANNUL_ALL_intermed_2;
RIN_X_ANNUL_ALL_intermed_4 <= RIN_X_ANNUL_ALL_intermed_3;
RIN_X_ANNUL_ALL_intermed_5 <= RIN_X_ANNUL_ALL_intermed_4;
V_M_CTRL_WREG_shadow_intermed_1 <= V_M_CTRL_WREG_shadow;
V_M_CTRL_WREG_shadow_intermed_2 <= V_M_CTRL_WREG_shadow_intermed_1;
R_E_CTRL_WREG_intermed_1 <= R.E.CTRL.WREG;
R_E_CTRL_WREG_intermed_2 <= R_E_CTRL_WREG_intermed_1;
V_A_CTRL_ANNUL_shadow_intermed_1 <= V_A_CTRL_ANNUL_shadow;
V_A_CTRL_ANNUL_shadow_intermed_2 <= V_A_CTRL_ANNUL_shadow_intermed_1;
V_A_CTRL_ANNUL_shadow_intermed_3 <= V_A_CTRL_ANNUL_shadow_intermed_2;
V_A_CTRL_ANNUL_shadow_intermed_4 <= V_A_CTRL_ANNUL_shadow_intermed_3;
RIN_E_CTRL_WREG_intermed_1 <= RIN.E.CTRL.WREG;
RIN_E_CTRL_WREG_intermed_2 <= RIN_E_CTRL_WREG_intermed_1;
RIN_E_CTRL_WREG_intermed_3 <= RIN_E_CTRL_WREG_intermed_2;
V_E_CTRL_WREG_shadow_intermed_1 <= V_E_CTRL_WREG_shadow;
V_E_CTRL_WREG_shadow_intermed_2 <= V_E_CTRL_WREG_shadow_intermed_1;
V_E_CTRL_WREG_shadow_intermed_3 <= V_E_CTRL_WREG_shadow_intermed_2;
RIN_W_S_SVT_intermed_1 <= RIN.W.S.SVT;
RIN_W_S_DWT_intermed_1 <= RIN.W.S.DWT;
RIN_W_S_EF_intermed_1 <= RIN.W.S.EF;
RIN_W_S_ICC_intermed_1 <= RIN.W.S.ICC;
RIN_E_CTRL_intermed_1 <= RIN.E.CTRL;
RIN_E_CTRL_intermed_2 <= RIN_E_CTRL_intermed_1;
R_E_CTRL_intermed_1 <= R.E.CTRL;
RIN_X_CTRL_intermed_1 <= RIN.X.CTRL;
RIN_M_CTRL_intermed_1 <= RIN.M.CTRL;
V_E_CTRL_shadow_intermed_1 <= V_E_CTRL_shadow;
V_E_CTRL_shadow_intermed_2 <= V_E_CTRL_shadow_intermed_1;
RIN_A_CTRL_intermed_1 <= RIN.A.CTRL;
RIN_A_CTRL_intermed_2 <= RIN_A_CTRL_intermed_1;
RIN_A_CTRL_intermed_3 <= RIN_A_CTRL_intermed_2;
V_M_CTRL_shadow_intermed_1 <= V_M_CTRL_shadow;
V_A_CTRL_shadow_intermed_1 <= V_A_CTRL_shadow;
V_A_CTRL_shadow_intermed_2 <= V_A_CTRL_shadow_intermed_1;
V_A_CTRL_shadow_intermed_3 <= V_A_CTRL_shadow_intermed_2;
R_A_CTRL_intermed_1 <= R.A.CTRL;
R_A_CTRL_intermed_2 <= R_A_CTRL_intermed_1;
V_M_DCI_shadow_intermed_1 <= V_M_DCI_shadow;
RIN_M_DCI_intermed_1 <= RIN.M.DCI;
RIN_X_DCI_intermed_1 <= RIN.X.DCI;
RIN_A_CTRL_ANNUL_intermed_1 <= RIN.A.CTRL.ANNUL;
RIN_A_CTRL_ANNUL_intermed_2 <= RIN_A_CTRL_ANNUL_intermed_1;
RIN_A_CTRL_ANNUL_intermed_3 <= RIN_A_CTRL_ANNUL_intermed_2;
RIN_A_CTRL_ANNUL_intermed_4 <= RIN_A_CTRL_ANNUL_intermed_3;
R_A_CTRL_ANNUL_intermed_1 <= R.A.CTRL.ANNUL;
R_A_CTRL_ANNUL_intermed_2 <= R_A_CTRL_ANNUL_intermed_1;
R_A_CTRL_ANNUL_intermed_3 <= R_A_CTRL_ANNUL_intermed_2;
RIN_M_CTRL_RETT_intermed_1 <= RIN.M.CTRL.RETT;
V_M_CTRL_ANNUL_shadow_intermed_1 <= V_M_CTRL_ANNUL_shadow;
R_X_ANNUL_ALL_intermed_1 <= R.X.ANNUL_ALL;
R_X_ANNUL_ALL_intermed_2 <= R_X_ANNUL_ALL_intermed_1;
R_X_ANNUL_ALL_intermed_3 <= R_X_ANNUL_ALL_intermed_2;
RIN_M_CTRL_ANNUL_intermed_1 <= RIN.M.CTRL.ANNUL;
V_E_CTRL_RETT_shadow_intermed_1 <= V_E_CTRL_RETT_shadow;
V_E_CTRL_RETT_shadow_intermed_2 <= V_E_CTRL_RETT_shadow_intermed_1;
V_A_CTRL_RETT_shadow_intermed_1 <= V_A_CTRL_RETT_shadow;
V_A_CTRL_RETT_shadow_intermed_2 <= V_A_CTRL_RETT_shadow_intermed_1;
V_A_CTRL_RETT_shadow_intermed_3 <= V_A_CTRL_RETT_shadow_intermed_2;
RIN_A_CTRL_RETT_intermed_1 <= RIN.A.CTRL.RETT;
RIN_A_CTRL_RETT_intermed_2 <= RIN_A_CTRL_RETT_intermed_1;
RIN_A_CTRL_RETT_intermed_3 <= RIN_A_CTRL_RETT_intermed_2;
V_X_ANNUL_ALL_shadow_intermed_1 <= V_X_ANNUL_ALL_shadow;
V_X_ANNUL_ALL_shadow_intermed_2 <= V_X_ANNUL_ALL_shadow_intermed_1;
V_X_ANNUL_ALL_shadow_intermed_3 <= V_X_ANNUL_ALL_shadow_intermed_2;
RIN_E_CTRL_ANNUL_intermed_1 <= RIN.E.CTRL.ANNUL;
RIN_E_CTRL_ANNUL_intermed_2 <= RIN_E_CTRL_ANNUL_intermed_1;
R_E_CTRL_RETT_intermed_1 <= R.E.CTRL.RETT;
RIN_X_ANNUL_ALL_intermed_1 <= RIN.X.ANNUL_ALL;
RIN_X_ANNUL_ALL_intermed_2 <= RIN_X_ANNUL_ALL_intermed_1;
RIN_X_ANNUL_ALL_intermed_3 <= RIN_X_ANNUL_ALL_intermed_2;
RIN_X_ANNUL_ALL_intermed_4 <= RIN_X_ANNUL_ALL_intermed_3;
RIN_E_CTRL_RETT_intermed_1 <= RIN.E.CTRL.RETT;
RIN_E_CTRL_RETT_intermed_2 <= RIN_E_CTRL_RETT_intermed_1;
V_E_CTRL_ANNUL_shadow_intermed_1 <= V_E_CTRL_ANNUL_shadow;
V_E_CTRL_ANNUL_shadow_intermed_2 <= V_E_CTRL_ANNUL_shadow_intermed_1;
V_A_CTRL_ANNUL_shadow_intermed_1 <= V_A_CTRL_ANNUL_shadow;
V_A_CTRL_ANNUL_shadow_intermed_2 <= V_A_CTRL_ANNUL_shadow_intermed_1;
V_A_CTRL_ANNUL_shadow_intermed_3 <= V_A_CTRL_ANNUL_shadow_intermed_2;
RIN_X_CTRL_RETT_intermed_1 <= RIN.X.CTRL.RETT;
V_M_CTRL_RETT_shadow_intermed_1 <= V_M_CTRL_RETT_shadow;
R_A_CTRL_RETT_intermed_1 <= R.A.CTRL.RETT;
R_A_CTRL_RETT_intermed_2 <= R_A_CTRL_RETT_intermed_1;
R_E_CTRL_ANNUL_intermed_1 <= R.E.CTRL.ANNUL;
V_E_MAC_shadow_intermed_1 <= V_E_MAC_shadow;
V_E_MAC_shadow_intermed_2 <= V_E_MAC_shadow_intermed_1;
RIN_M_MAC_intermed_1 <= RIN.M.MAC;
RIN_E_MAC_intermed_1 <= RIN.E.MAC;
RIN_E_MAC_intermed_2 <= RIN_E_MAC_intermed_1;
R_E_MAC_intermed_1 <= R.E.MAC;
V_M_MAC_shadow_intermed_1 <= V_M_MAC_shadow;
RIN_X_MAC_intermed_1 <= RIN.X.MAC;
V_M_RESULT1DOWNTO0_shadow_intermed_1 <= V_M_RESULT1DOWNTO0_shadow;
V_M_RESULT1DOWNTO0_shadow_intermed_2 <= V_M_RESULT1DOWNTO0_shadow_intermed_1;
RIN_X_LADDR_intermed_1 <= RIN.X.LADDR;
RIN_M_RESULT1DOWNTO0_intermed_1 <= RIN.M.RESULT( 1 DOWNTO 0 );
RIN_M_RESULT1DOWNTO0_intermed_2 <= RIN_M_RESULT1DOWNTO0_intermed_1;
V_M_RESULT1DOWNTO0_shadow_intermed_1 <= V_M_RESULT1DOWNTO0_shadow;
R_M_RESULT1DOWNTO0_intermed_1 <= R.M.RESULT( 1 DOWNTO 0 );
RIN_M_RESULT1DOWNTO0_intermed_1 <= RIN.M.RESULT ( 1 DOWNTO 0 );
RIN_A_CTRL_ANNUL_intermed_1 <= RIN.A.CTRL.ANNUL;
RIN_A_CTRL_ANNUL_intermed_2 <= RIN_A_CTRL_ANNUL_intermed_1;
RIN_A_CTRL_ANNUL_intermed_3 <= RIN_A_CTRL_ANNUL_intermed_2;
R_A_CTRL_ANNUL_intermed_1 <= R.A.CTRL.ANNUL;
R_A_CTRL_ANNUL_intermed_2 <= R_A_CTRL_ANNUL_intermed_1;
V_M_CTRL_ANNUL_shadow_intermed_1 <= V_M_CTRL_ANNUL_shadow;
R_X_ANNUL_ALL_intermed_1 <= R.X.ANNUL_ALL;
RIN_X_CTRL_ANNUL_intermed_1 <= RIN.X.CTRL.ANNUL;
RIN_M_CTRL_ANNUL_intermed_1 <= RIN.M.CTRL.ANNUL;
V_X_ANNUL_ALL_shadow_intermed_1 <= V_X_ANNUL_ALL_shadow;
RIN_E_CTRL_ANNUL_intermed_1 <= RIN.E.CTRL.ANNUL;
RIN_E_CTRL_ANNUL_intermed_2 <= RIN_E_CTRL_ANNUL_intermed_1;
RIN_X_ANNUL_ALL_intermed_1 <= RIN.X.ANNUL_ALL;
RIN_X_ANNUL_ALL_intermed_2 <= RIN_X_ANNUL_ALL_intermed_1;
V_E_CTRL_ANNUL_shadow_intermed_1 <= V_E_CTRL_ANNUL_shadow;
V_E_CTRL_ANNUL_shadow_intermed_2 <= V_E_CTRL_ANNUL_shadow_intermed_1;
V_A_CTRL_ANNUL_shadow_intermed_1 <= V_A_CTRL_ANNUL_shadow;
V_A_CTRL_ANNUL_shadow_intermed_2 <= V_A_CTRL_ANNUL_shadow_intermed_1;
V_A_CTRL_ANNUL_shadow_intermed_3 <= V_A_CTRL_ANNUL_shadow_intermed_2;
R_E_CTRL_ANNUL_intermed_1 <= R.E.CTRL.ANNUL;
V_E_CTRL_TT_shadow_intermed_1 <= V_E_CTRL_TT_shadow;
V_E_CTRL_TT_shadow_intermed_2 <= V_E_CTRL_TT_shadow_intermed_1;
V_E_CTRL_TT_shadow_intermed_3 <= V_E_CTRL_TT_shadow_intermed_2;
RIN_A_CTRL_TT_intermed_1 <= RIN.A.CTRL.TT;
RIN_A_CTRL_TT_intermed_2 <= RIN_A_CTRL_TT_intermed_1;
RIN_A_CTRL_TT_intermed_3 <= RIN_A_CTRL_TT_intermed_2;
RIN_A_CTRL_TT_intermed_4 <= RIN_A_CTRL_TT_intermed_3;
R_A_CTRL_TT_intermed_1 <= R.A.CTRL.TT;
R_A_CTRL_TT_intermed_2 <= R_A_CTRL_TT_intermed_1;
R_A_CTRL_TT_intermed_3 <= R_A_CTRL_TT_intermed_2;
R_M_CTRL_TT_intermed_1 <= R.M.CTRL.TT;
R_E_CTRL_TT_intermed_1 <= R.E.CTRL.TT;
R_E_CTRL_TT_intermed_2 <= R_E_CTRL_TT_intermed_1;
RIN_M_CTRL_TT_intermed_1 <= RIN.M.CTRL.TT;
RIN_M_CTRL_TT_intermed_2 <= RIN_M_CTRL_TT_intermed_1;
RIN_E_CTRL_TT_intermed_1 <= RIN.E.CTRL.TT;
RIN_E_CTRL_TT_intermed_2 <= RIN_E_CTRL_TT_intermed_1;
RIN_E_CTRL_TT_intermed_3 <= RIN_E_CTRL_TT_intermed_2;
V_M_CTRL_TT_shadow_intermed_1 <= V_M_CTRL_TT_shadow;
V_M_CTRL_TT_shadow_intermed_2 <= V_M_CTRL_TT_shadow_intermed_1;
V_A_CTRL_TT_shadow_intermed_1 <= V_A_CTRL_TT_shadow;
V_A_CTRL_TT_shadow_intermed_2 <= V_A_CTRL_TT_shadow_intermed_1;
V_A_CTRL_TT_shadow_intermed_3 <= V_A_CTRL_TT_shadow_intermed_2;
V_A_CTRL_TT_shadow_intermed_4 <= V_A_CTRL_TT_shadow_intermed_3;
RIN_X_CTRL_TT_intermed_1 <= RIN.X.CTRL.TT;
RIN_X_SET_intermed_1 <= RIN.X.SET;
V_M_DCI_SIZE_shadow_intermed_1 <= V_M_DCI_SIZE_shadow;
V_M_DCI_SIZE_shadow_intermed_2 <= V_M_DCI_SIZE_shadow_intermed_1;
R_M_DCI_SIZE_intermed_1 <= R.M.DCI.SIZE;
RIN_X_DCI_SIZE_intermed_1 <= RIN.X.DCI.SIZE;
RIN_M_DCI_SIZE_intermed_1 <= RIN.M.DCI.SIZE;
RIN_M_DCI_SIZE_intermed_2 <= RIN_M_DCI_SIZE_intermed_1;
RIN_M_DCI_SIGNED_intermed_1 <= RIN.M.DCI.SIGNED;
RIN_M_DCI_SIGNED_intermed_2 <= RIN_M_DCI_SIGNED_intermed_1;
R_M_DCI_SIGNED_intermed_1 <= R.M.DCI.SIGNED;
RIN_X_DCI_SIGNED_intermed_1 <= RIN.X.DCI.SIGNED;
V_M_DCI_SIGNED_shadow_intermed_1 <= V_M_DCI_SIGNED_shadow;
V_M_DCI_SIGNED_shadow_intermed_2 <= V_M_DCI_SIGNED_shadow_intermed_1;
V_X_DATA0_shadow_intermed_1 <= V_X_DATA0_shadow;
V_X_DATA0_shadow_intermed_2 <= V_X_DATA0_shadow_intermed_1;
RIN_X_DATA0_intermed_1 <= RIN.X.DATA ( 0 );
R_X_DATA0_intermed_1 <= R.X.DATA( 0 );
RIN_X_DATA0_intermed_1 <= RIN.X.DATA( 0 );
RIN_X_DATA0_intermed_2 <= RIN_X_DATA0_intermed_1;
RIN_X_MEXC_intermed_1 <= RIN.X.MEXC;
RIN_X_ICC_intermed_1 <= RIN.X.ICC;
R_A_CTRL_WICC_intermed_1 <= R.A.CTRL.WICC;
R_A_CTRL_WICC_intermed_2 <= R_A_CTRL_WICC_intermed_1;
RIN_A_CTRL_ANNUL_intermed_1 <= RIN.A.CTRL.ANNUL;
RIN_A_CTRL_ANNUL_intermed_2 <= RIN_A_CTRL_ANNUL_intermed_1;
RIN_A_CTRL_ANNUL_intermed_3 <= RIN_A_CTRL_ANNUL_intermed_2;
RIN_A_CTRL_ANNUL_intermed_4 <= RIN_A_CTRL_ANNUL_intermed_3;
V_E_CTRL_WICC_shadow_intermed_1 <= V_E_CTRL_WICC_shadow;
V_E_CTRL_WICC_shadow_intermed_2 <= V_E_CTRL_WICC_shadow_intermed_1;
V_A_CTRL_WICC_shadow_intermed_1 <= V_A_CTRL_WICC_shadow;
V_A_CTRL_WICC_shadow_intermed_2 <= V_A_CTRL_WICC_shadow_intermed_1;
V_A_CTRL_WICC_shadow_intermed_3 <= V_A_CTRL_WICC_shadow_intermed_2;
R_A_CTRL_ANNUL_intermed_1 <= R.A.CTRL.ANNUL;
R_A_CTRL_ANNUL_intermed_2 <= R_A_CTRL_ANNUL_intermed_1;
R_A_CTRL_ANNUL_intermed_3 <= R_A_CTRL_ANNUL_intermed_2;
RIN_X_CTRL_WICC_intermed_1 <= RIN.X.CTRL.WICC;
R_X_ANNUL_ALL_intermed_1 <= R.X.ANNUL_ALL;
R_X_ANNUL_ALL_intermed_2 <= R_X_ANNUL_ALL_intermed_1;
R_X_ANNUL_ALL_intermed_3 <= R_X_ANNUL_ALL_intermed_2;
RIN_E_CTRL_WICC_intermed_1 <= RIN.E.CTRL.WICC;
RIN_E_CTRL_WICC_intermed_2 <= RIN_E_CTRL_WICC_intermed_1;
RIN_M_CTRL_WICC_intermed_1 <= RIN.M.CTRL.WICC;
R_E_CTRL_WICC_intermed_1 <= R.E.CTRL.WICC;
V_X_ANNUL_ALL_shadow_intermed_1 <= V_X_ANNUL_ALL_shadow;
V_X_ANNUL_ALL_shadow_intermed_2 <= V_X_ANNUL_ALL_shadow_intermed_1;
V_X_ANNUL_ALL_shadow_intermed_3 <= V_X_ANNUL_ALL_shadow_intermed_2;
V_M_CTRL_WICC_shadow_intermed_1 <= V_M_CTRL_WICC_shadow;
RIN_X_ANNUL_ALL_intermed_1 <= RIN.X.ANNUL_ALL;
RIN_X_ANNUL_ALL_intermed_2 <= RIN_X_ANNUL_ALL_intermed_1;
RIN_X_ANNUL_ALL_intermed_3 <= RIN_X_ANNUL_ALL_intermed_2;
RIN_X_ANNUL_ALL_intermed_4 <= RIN_X_ANNUL_ALL_intermed_3;
RIN_A_CTRL_WICC_intermed_1 <= RIN.A.CTRL.WICC;
RIN_A_CTRL_WICC_intermed_2 <= RIN_A_CTRL_WICC_intermed_1;
RIN_A_CTRL_WICC_intermed_3 <= RIN_A_CTRL_WICC_intermed_2;
V_A_CTRL_ANNUL_shadow_intermed_1 <= V_A_CTRL_ANNUL_shadow;
V_A_CTRL_ANNUL_shadow_intermed_2 <= V_A_CTRL_ANNUL_shadow_intermed_1;
V_A_CTRL_ANNUL_shadow_intermed_3 <= V_A_CTRL_ANNUL_shadow_intermed_2;
RIN_W_S_ASR18_intermed_1 <= RIN.W.S.ASR18;
RIN_E_CTRL_intermed_1 <= RIN.E.CTRL;
RIN_M_CTRL_intermed_1 <= RIN.M.CTRL;
V_E_CTRL_shadow_intermed_1 <= V_E_CTRL_shadow;
RIN_A_CTRL_intermed_1 <= RIN.A.CTRL;
RIN_A_CTRL_intermed_2 <= RIN_A_CTRL_intermed_1;
V_A_CTRL_shadow_intermed_1 <= V_A_CTRL_shadow;
V_A_CTRL_shadow_intermed_2 <= V_A_CTRL_shadow_intermed_1;
R_A_CTRL_intermed_1 <= R.A.CTRL;
RIN_A_CTRL_ANNUL_intermed_1 <= RIN.A.CTRL.ANNUL;
RIN_A_CTRL_ANNUL_intermed_2 <= RIN_A_CTRL_ANNUL_intermed_1;
RIN_A_CTRL_ANNUL_intermed_3 <= RIN_A_CTRL_ANNUL_intermed_2;
R_A_CTRL_ANNUL_intermed_1 <= R.A.CTRL.ANNUL;
R_A_CTRL_ANNUL_intermed_2 <= R_A_CTRL_ANNUL_intermed_1;
RIN_M_CTRL_RETT_intermed_1 <= RIN.M.CTRL.RETT;
R_X_ANNUL_ALL_intermed_1 <= R.X.ANNUL_ALL;
R_X_ANNUL_ALL_intermed_2 <= R_X_ANNUL_ALL_intermed_1;
V_E_CTRL_RETT_shadow_intermed_1 <= V_E_CTRL_RETT_shadow;
V_A_CTRL_RETT_shadow_intermed_1 <= V_A_CTRL_RETT_shadow;
V_A_CTRL_RETT_shadow_intermed_2 <= V_A_CTRL_RETT_shadow_intermed_1;
RIN_A_CTRL_RETT_intermed_1 <= RIN.A.CTRL.RETT;
RIN_A_CTRL_RETT_intermed_2 <= RIN_A_CTRL_RETT_intermed_1;
V_X_ANNUL_ALL_shadow_intermed_1 <= V_X_ANNUL_ALL_shadow;
V_X_ANNUL_ALL_shadow_intermed_2 <= V_X_ANNUL_ALL_shadow_intermed_1;
RIN_E_CTRL_ANNUL_intermed_1 <= RIN.E.CTRL.ANNUL;
RIN_X_ANNUL_ALL_intermed_1 <= RIN.X.ANNUL_ALL;
RIN_X_ANNUL_ALL_intermed_2 <= RIN_X_ANNUL_ALL_intermed_1;
RIN_X_ANNUL_ALL_intermed_3 <= RIN_X_ANNUL_ALL_intermed_2;
RIN_E_CTRL_RETT_intermed_1 <= RIN.E.CTRL.RETT;
V_E_CTRL_ANNUL_shadow_intermed_1 <= V_E_CTRL_ANNUL_shadow;
V_A_CTRL_ANNUL_shadow_intermed_1 <= V_A_CTRL_ANNUL_shadow;
V_A_CTRL_ANNUL_shadow_intermed_2 <= V_A_CTRL_ANNUL_shadow_intermed_1;
R_A_CTRL_RETT_intermed_1 <= R.A.CTRL.RETT;
RIN_A_CTRL_ANNUL_intermed_1 <= RIN.A.CTRL.ANNUL;
RIN_A_CTRL_ANNUL_intermed_2 <= RIN_A_CTRL_ANNUL_intermed_1;
RIN_A_CTRL_ANNUL_intermed_3 <= RIN_A_CTRL_ANNUL_intermed_2;
R_A_CTRL_ANNUL_intermed_1 <= R.A.CTRL.ANNUL;
R_A_CTRL_ANNUL_intermed_2 <= R_A_CTRL_ANNUL_intermed_1;
R_X_ANNUL_ALL_intermed_1 <= R.X.ANNUL_ALL;
R_X_ANNUL_ALL_intermed_2 <= R_X_ANNUL_ALL_intermed_1;
RIN_M_CTRL_WREG_intermed_1 <= RIN.M.CTRL.WREG;
RIN_A_CTRL_WREG_intermed_1 <= RIN.A.CTRL.WREG;
RIN_A_CTRL_WREG_intermed_2 <= RIN_A_CTRL_WREG_intermed_1;
V_A_CTRL_WREG_shadow_intermed_1 <= V_A_CTRL_WREG_shadow;
V_A_CTRL_WREG_shadow_intermed_2 <= V_A_CTRL_WREG_shadow_intermed_1;
R_A_CTRL_WREG_intermed_1 <= R.A.CTRL.WREG;
V_X_ANNUL_ALL_shadow_intermed_1 <= V_X_ANNUL_ALL_shadow;
V_X_ANNUL_ALL_shadow_intermed_2 <= V_X_ANNUL_ALL_shadow_intermed_1;
RIN_X_ANNUL_ALL_intermed_1 <= RIN.X.ANNUL_ALL;
RIN_X_ANNUL_ALL_intermed_2 <= RIN_X_ANNUL_ALL_intermed_1;
RIN_X_ANNUL_ALL_intermed_3 <= RIN_X_ANNUL_ALL_intermed_2;
V_A_CTRL_ANNUL_shadow_intermed_1 <= V_A_CTRL_ANNUL_shadow;
V_A_CTRL_ANNUL_shadow_intermed_2 <= V_A_CTRL_ANNUL_shadow_intermed_1;
RIN_E_CTRL_WREG_intermed_1 <= RIN.E.CTRL.WREG;
V_E_CTRL_WREG_shadow_intermed_1 <= V_E_CTRL_WREG_shadow;
RIN_E_CWP_intermed_1 <= RIN.E.CWP;
V_A_CWP_shadow_intermed_1 <= V_A_CWP_shadow;
RIN_D_CWP_intermed_1 <= RIN.D.CWP;
RIN_D_CWP_intermed_2 <= RIN_D_CWP_intermed_1;
RIN_A_CWP_intermed_1 <= RIN.A.CWP;
V_D_CWP_shadow_intermed_1 <= V_D_CWP_shadow;
V_D_CWP_shadow_intermed_2 <= V_D_CWP_shadow_intermed_1;
R_D_CWP_intermed_1 <= R.D.CWP;
R_A_SU_intermed_1 <= R.A.SU;
RIN_A_SU_intermed_1 <= RIN.A.SU;
RIN_A_SU_intermed_2 <= RIN_A_SU_intermed_1;
V_E_SU_shadow_intermed_1 <= V_E_SU_shadow;
V_A_SU_shadow_intermed_1 <= V_A_SU_shadow;
V_A_SU_shadow_intermed_2 <= V_A_SU_shadow_intermed_1;
RIN_M_SU_intermed_1 <= RIN.M.SU;
RIN_E_SU_intermed_1 <= RIN.E.SU;
RIN_E_MUL_intermed_1 <= RIN.E.MUL;
RIN_M_MUL_intermed_1 <= RIN.M.MUL;
V_E_MUL_shadow_intermed_1 <= V_E_MUL_shadow;
RIN_M_NALIGN_intermed_1 <= RIN.M.NALIGN;
V_X_DATA03_shadow_intermed_1 <= V_X_DATA03_shadow;
V_X_DATA03_shadow_intermed_2 <= V_X_DATA03_shadow_intermed_1;
V_X_DATA03_shadow_intermed_1 <= V_X_DATA03_shadow;
RIN_X_DATA03_intermed_1 <= RIN.X.DATA ( 0 )( 3 );
R_X_DATA03_intermed_1 <= R.X.DATA( 0 )( 3 );
RIN_X_DATA03_intermed_1 <= RIN.X.DATA( 0 )( 3 );
RIN_X_DATA03_intermed_2 <= RIN_X_DATA03_intermed_1;
RIN_E_OP23_intermed_1 <= RIN.E.OP2( 3 );
RIN_E_OP13_intermed_1 <= RIN.E.OP1( 3 );
V_E_OP23_shadow_intermed_1 <= V_E_OP23_shadow;
V_E_OP13_shadow_intermed_1 <= V_E_OP13_shadow;
RIN_A_CTRL_ANNUL_intermed_1 <= RIN.A.CTRL.ANNUL;
RIN_A_CTRL_ANNUL_intermed_2 <= RIN_A_CTRL_ANNUL_intermed_1;
RIN_A_CTRL_ANNUL_intermed_3 <= RIN_A_CTRL_ANNUL_intermed_2;
R_A_CTRL_ANNUL_intermed_1 <= R.A.CTRL.ANNUL;
R_A_CTRL_ANNUL_intermed_2 <= R_A_CTRL_ANNUL_intermed_1;
RIN_M_CTRL_ANNUL_intermed_1 <= RIN.M.CTRL.ANNUL;
RIN_E_CTRL_ANNUL_intermed_1 <= RIN.E.CTRL.ANNUL;
RIN_E_CTRL_ANNUL_intermed_2 <= RIN_E_CTRL_ANNUL_intermed_1;
RIN_X_ANNUL_ALL_intermed_1 <= RIN.X.ANNUL_ALL;
V_E_CTRL_ANNUL_shadow_intermed_1 <= V_E_CTRL_ANNUL_shadow;
V_E_CTRL_ANNUL_shadow_intermed_2 <= V_E_CTRL_ANNUL_shadow_intermed_1;
V_A_CTRL_ANNUL_shadow_intermed_1 <= V_A_CTRL_ANNUL_shadow;
V_A_CTRL_ANNUL_shadow_intermed_2 <= V_A_CTRL_ANNUL_shadow_intermed_1;
V_A_CTRL_ANNUL_shadow_intermed_3 <= V_A_CTRL_ANNUL_shadow_intermed_2;
R_E_CTRL_ANNUL_intermed_1 <= R.E.CTRL.ANNUL;
R_A_CTRL_WICC_intermed_1 <= R.A.CTRL.WICC;
RIN_A_CTRL_ANNUL_intermed_1 <= RIN.A.CTRL.ANNUL;
RIN_A_CTRL_ANNUL_intermed_2 <= RIN_A_CTRL_ANNUL_intermed_1;
RIN_A_CTRL_ANNUL_intermed_3 <= RIN_A_CTRL_ANNUL_intermed_2;
V_E_CTRL_WICC_shadow_intermed_1 <= V_E_CTRL_WICC_shadow;
V_A_CTRL_WICC_shadow_intermed_1 <= V_A_CTRL_WICC_shadow;
V_A_CTRL_WICC_shadow_intermed_2 <= V_A_CTRL_WICC_shadow_intermed_1;
R_A_CTRL_ANNUL_intermed_1 <= R.A.CTRL.ANNUL;
R_A_CTRL_ANNUL_intermed_2 <= R_A_CTRL_ANNUL_intermed_1;
R_X_ANNUL_ALL_intermed_1 <= R.X.ANNUL_ALL;
R_X_ANNUL_ALL_intermed_2 <= R_X_ANNUL_ALL_intermed_1;
RIN_E_CTRL_WICC_intermed_1 <= RIN.E.CTRL.WICC;
RIN_M_CTRL_WICC_intermed_1 <= RIN.M.CTRL.WICC;
V_X_ANNUL_ALL_shadow_intermed_1 <= V_X_ANNUL_ALL_shadow;
V_X_ANNUL_ALL_shadow_intermed_2 <= V_X_ANNUL_ALL_shadow_intermed_1;
RIN_X_ANNUL_ALL_intermed_1 <= RIN.X.ANNUL_ALL;
RIN_X_ANNUL_ALL_intermed_2 <= RIN_X_ANNUL_ALL_intermed_1;
RIN_X_ANNUL_ALL_intermed_3 <= RIN_X_ANNUL_ALL_intermed_2;
RIN_A_CTRL_WICC_intermed_1 <= RIN.A.CTRL.WICC;
RIN_A_CTRL_WICC_intermed_2 <= RIN_A_CTRL_WICC_intermed_1;
V_A_CTRL_ANNUL_shadow_intermed_1 <= V_A_CTRL_ANNUL_shadow;
V_A_CTRL_ANNUL_shadow_intermed_2 <= V_A_CTRL_ANNUL_shadow_intermed_1;
V_E_MAC_shadow_intermed_1 <= V_E_MAC_shadow;
RIN_M_MAC_intermed_1 <= RIN.M.MAC;
RIN_E_MAC_intermed_1 <= RIN.E.MAC;
R_A_CTRL_LD_intermed_1 <= R.A.CTRL.LD;
R_A_CTRL_LD_intermed_2 <= R_A_CTRL_LD_intermed_1;
RIN_A_CTRL_LD_intermed_1 <= RIN.A.CTRL.LD;
RIN_A_CTRL_LD_intermed_2 <= RIN_A_CTRL_LD_intermed_1;
RIN_A_CTRL_LD_intermed_3 <= RIN_A_CTRL_LD_intermed_2;
V_E_CTRL_LD_shadow_intermed_1 <= V_E_CTRL_LD_shadow;
V_E_CTRL_LD_shadow_intermed_2 <= V_E_CTRL_LD_shadow_intermed_1;
R_E_CTRL_LD_intermed_1 <= R.E.CTRL.LD;
RIN_E_CTRL_LD_intermed_1 <= RIN.E.CTRL.LD;
RIN_E_CTRL_LD_intermed_2 <= RIN_E_CTRL_LD_intermed_1;
RIN_M_CTRL_LD_intermed_1 <= RIN.M.CTRL.LD;
V_A_CTRL_LD_shadow_intermed_1 <= V_A_CTRL_LD_shadow;
V_A_CTRL_LD_shadow_intermed_2 <= V_A_CTRL_LD_shadow_intermed_1;
V_A_CTRL_LD_shadow_intermed_3 <= V_A_CTRL_LD_shadow_intermed_2;
RIN_E_CTRL_intermed_1 <= RIN.E.CTRL;
RIN_A_CTRL_intermed_1 <= RIN.A.CTRL;
V_A_CTRL_shadow_intermed_1 <= V_A_CTRL_shadow;
RIN_E_JMPL_intermed_1 <= RIN.E.JMPL;
RIN_A_JMPL_intermed_1 <= RIN.A.JMPL;
V_A_JMPL_shadow_intermed_1 <= V_A_JMPL_shadow;
RIN_A_CTRL_ANNUL_intermed_1 <= RIN.A.CTRL.ANNUL;
R_X_ANNUL_ALL_intermed_1 <= R.X.ANNUL_ALL;
V_X_ANNUL_ALL_shadow_intermed_1 <= V_X_ANNUL_ALL_shadow;
RIN_E_CTRL_ANNUL_intermed_1 <= RIN.E.CTRL.ANNUL;
RIN_X_ANNUL_ALL_intermed_1 <= RIN.X.ANNUL_ALL;
RIN_X_ANNUL_ALL_intermed_2 <= RIN_X_ANNUL_ALL_intermed_1;
V_A_CTRL_ANNUL_shadow_intermed_1 <= V_A_CTRL_ANNUL_shadow;
RIN_A_CTRL_ANNUL_intermed_1 <= RIN.A.CTRL.ANNUL;
RIN_A_CTRL_ANNUL_intermed_2 <= RIN_A_CTRL_ANNUL_intermed_1;
R_A_CTRL_ANNUL_intermed_1 <= R.A.CTRL.ANNUL;
R_X_ANNUL_ALL_intermed_1 <= R.X.ANNUL_ALL;
V_A_CTRL_RETT_shadow_intermed_1 <= V_A_CTRL_RETT_shadow;
RIN_A_CTRL_RETT_intermed_1 <= RIN.A.CTRL.RETT;
V_X_ANNUL_ALL_shadow_intermed_1 <= V_X_ANNUL_ALL_shadow;
RIN_X_ANNUL_ALL_intermed_1 <= RIN.X.ANNUL_ALL;
RIN_X_ANNUL_ALL_intermed_2 <= RIN_X_ANNUL_ALL_intermed_1;
RIN_E_CTRL_RETT_intermed_1 <= RIN.E.CTRL.RETT;
V_A_CTRL_ANNUL_shadow_intermed_1 <= V_A_CTRL_ANNUL_shadow;
RIN_A_CTRL_ANNUL_intermed_1 <= RIN.A.CTRL.ANNUL;
RIN_A_CTRL_ANNUL_intermed_2 <= RIN_A_CTRL_ANNUL_intermed_1;
R_A_CTRL_ANNUL_intermed_1 <= R.A.CTRL.ANNUL;
R_X_ANNUL_ALL_intermed_1 <= R.X.ANNUL_ALL;
RIN_A_CTRL_WREG_intermed_1 <= RIN.A.CTRL.WREG;
V_A_CTRL_WREG_shadow_intermed_1 <= V_A_CTRL_WREG_shadow;
V_X_ANNUL_ALL_shadow_intermed_1 <= V_X_ANNUL_ALL_shadow;
RIN_X_ANNUL_ALL_intermed_1 <= RIN.X.ANNUL_ALL;
RIN_X_ANNUL_ALL_intermed_2 <= RIN_X_ANNUL_ALL_intermed_1;
V_A_CTRL_ANNUL_shadow_intermed_1 <= V_A_CTRL_ANNUL_shadow;
RIN_E_CTRL_WREG_intermed_1 <= RIN.E.CTRL.WREG;
RIN_A_SU_intermed_1 <= RIN.A.SU;
V_A_SU_shadow_intermed_1 <= V_A_SU_shadow;
RIN_E_SU_intermed_1 <= RIN.E.SU;
RIN_E_ET_intermed_1 <= RIN.E.ET;
RIN_A_ET_intermed_1 <= RIN.A.ET;
V_A_ET_shadow_intermed_1 <= V_A_ET_shadow;
RIN_A_CTRL_ANNUL_intermed_1 <= RIN.A.CTRL.ANNUL;
RIN_A_CTRL_ANNUL_intermed_2 <= RIN_A_CTRL_ANNUL_intermed_1;
V_A_CTRL_WICC_shadow_intermed_1 <= V_A_CTRL_WICC_shadow;
R_A_CTRL_ANNUL_intermed_1 <= R.A.CTRL.ANNUL;
RIN_E_CTRL_WICC_intermed_1 <= RIN.E.CTRL.WICC;
R_X_ANNUL_ALL_intermed_1 <= R.X.ANNUL_ALL;
V_X_ANNUL_ALL_shadow_intermed_1 <= V_X_ANNUL_ALL_shadow;
RIN_X_ANNUL_ALL_intermed_1 <= RIN.X.ANNUL_ALL;
RIN_X_ANNUL_ALL_intermed_2 <= RIN_X_ANNUL_ALL_intermed_1;
RIN_A_CTRL_WICC_intermed_1 <= RIN.A.CTRL.WICC;
V_A_CTRL_ANNUL_shadow_intermed_1 <= V_A_CTRL_ANNUL_shadow;
RIN_D_CWP_intermed_1 <= RIN.D.CWP;
RIN_A_CWP_intermed_1 <= RIN.A.CWP;
V_D_CWP_shadow_intermed_1 <= V_D_CWP_shadow;
RIN_A_RFA1_intermed_1 <= RIN.A.RFA1;
V_A_RFA1_shadow_intermed_1 <= V_A_RFA1_shadow;
DBGI_DADDR9DOWNTO2_intermed_1 <= DBGI.DADDR ( 9 DOWNTO 2 );
RIN_A_RFA1_intermed_1 <= RIN.A.RFA1;
RIN_A_RFA2_intermed_1 <= RIN.A.RFA2;
RIN_A_CTRL_ANNUL_intermed_1 <= RIN.A.CTRL.ANNUL;
RIN_X_ANNUL_ALL_intermed_1 <= RIN.X.ANNUL_ALL;
RIN_A_CTRL_ANNUL_intermed_1 <= RIN.A.CTRL.ANNUL;
RIN_X_ANNUL_ALL_intermed_1 <= RIN.X.ANNUL_ALL;
RIN_A_CTRL_WICC_intermed_1 <= RIN.A.CTRL.WICC;
RIN_A_CTRL_ANNUL_intermed_1 <= RIN.A.CTRL.ANNUL;
RIN_A_CTRL_WREG_intermed_1 <= RIN.A.CTRL.WREG;
RIN_X_ANNUL_ALL_intermed_1 <= RIN.X.ANNUL_ALL;
RIN_A_CTRL_ANNUL_intermed_1 <= RIN.A.CTRL.ANNUL;
RIN_A_CTRL_RETT_intermed_1 <= RIN.A.CTRL.RETT;
RIN_X_ANNUL_ALL_intermed_1 <= RIN.X.ANNUL_ALL;
RIN_A_CTRL_ANNUL_intermed_1 <= RIN.A.CTRL.ANNUL;
RIN_X_ANNUL_ALL_intermed_1 <= RIN.X.ANNUL_ALL;
RIN_A_CTRL_WY_intermed_1 <= RIN.A.CTRL.WY;
ICO_MEXC_intermed_1 <= ICO.MEXC;
RIN_A_CTRL_TRAP_intermed_1 <= RIN.A.CTRL.TRAP;
V_D_MEXC_shadow_intermed_1 <= V_D_MEXC_shadow;
RIN_D_MEXC_intermed_1 <= RIN.D.MEXC;
RIN_A_CTRL_TT_intermed_1 <= RIN.A.CTRL.TT;
RIN_D_INST0_intermed_1 <= RIN.D.INST ( 0 );
R_D_INST0_intermed_1 <= R.D.INST( 0 );
RIN_A_CTRL_INST_intermed_1 <= RIN.A.CTRL.INST;
V_D_INST0_shadow_intermed_1 <= V_D_INST0_shadow;
V_D_INST0_shadow_intermed_2 <= V_D_INST0_shadow_intermed_1;
RIN_D_INST0_intermed_1 <= RIN.D.INST( 0 );
RIN_D_INST0_intermed_2 <= RIN_D_INST0_intermed_1;
V_D_INST0_shadow_intermed_1 <= V_D_INST0_shadow;
RIN_D_PC_intermed_1 <= RIN.D.PC;
RIN_A_CTRL_PC_intermed_1 <= RIN.A.CTRL.PC;
V_D_PC_shadow_intermed_1 <= V_D_PC_shadow;
RIN_D_CNT_intermed_1 <= RIN.D.CNT;
V_D_CNT_shadow_intermed_1 <= V_D_CNT_shadow;
RIN_A_CTRL_CNT_intermed_1 <= RIN.A.CTRL.CNT;
R_D_ANNUL_intermed_1 <= R.D.ANNUL;
RIN_D_STEP_intermed_1 <= RIN.D.STEP;
V_D_ANNUL_shadow_intermed_1 <= V_D_ANNUL_shadow;
V_D_ANNUL_shadow_intermed_2 <= V_D_ANNUL_shadow_intermed_1;
DBGI_STEP_intermed_1 <= DBGI.STEP;
V_D_STEP_shadow_intermed_1 <= V_D_STEP_shadow;
RIN_D_ANNUL_intermed_1 <= RIN.D.ANNUL;
RIN_D_ANNUL_intermed_2 <= RIN_D_ANNUL_intermed_1;
RIN_A_STEP_intermed_1 <= RIN.A.STEP;
RIN_D_STEP_intermed_1 <= RIN.D.STEP;
V_D_ANNUL_shadow_intermed_1 <= V_D_ANNUL_shadow;
RIN_D_ANNUL_intermed_1 <= RIN.D.ANNUL;
RIN_D_CNT_intermed_1 <= RIN.D.CNT;
RIN_D_CWP_intermed_1 <= RIN.D.CWP;
EX_ADD_RES32DOWNTO3_shadow_intermed_1 <= EX_ADD_RES32DOWNTO3_shadow;
RIN_F_PC_intermed_1 <= RIN.F.PC;
EX_JUMP_ADDRESS_shadow_intermed_1 <= EX_JUMP_ADDRESS_shadow;
RIN_F_BRANCH_intermed_1 <= RIN.F.BRANCH;
R_M_CTRL_PC31DOWNTO12_intermed_1 <= R.M.CTRL.PC( 31 DOWNTO 12 );
R_M_CTRL_PC31DOWNTO12_intermed_2 <= R_M_CTRL_PC31DOWNTO12_intermed_1;
R_M_CTRL_PC31DOWNTO12_intermed_3 <= R_M_CTRL_PC31DOWNTO12_intermed_2;
V_D_PC31DOWNTO12_shadow_intermed_1 <= V_D_PC31DOWNTO12_shadow;
V_D_PC31DOWNTO12_shadow_intermed_2 <= V_D_PC31DOWNTO12_shadow_intermed_1;
V_D_PC31DOWNTO12_shadow_intermed_3 <= V_D_PC31DOWNTO12_shadow_intermed_2;
V_D_PC31DOWNTO12_shadow_intermed_4 <= V_D_PC31DOWNTO12_shadow_intermed_3;
V_D_PC31DOWNTO12_shadow_intermed_5 <= V_D_PC31DOWNTO12_shadow_intermed_4;
V_D_PC31DOWNTO12_shadow_intermed_6 <= V_D_PC31DOWNTO12_shadow_intermed_5;
V_D_PC31DOWNTO12_shadow_intermed_7 <= V_D_PC31DOWNTO12_shadow_intermed_6;
V_A_CTRL_PC31DOWNTO12_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO12_shadow;
V_A_CTRL_PC31DOWNTO12_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO12_shadow_intermed_1;
V_A_CTRL_PC31DOWNTO12_shadow_intermed_3 <= V_A_CTRL_PC31DOWNTO12_shadow_intermed_2;
V_A_CTRL_PC31DOWNTO12_shadow_intermed_4 <= V_A_CTRL_PC31DOWNTO12_shadow_intermed_3;
V_A_CTRL_PC31DOWNTO12_shadow_intermed_5 <= V_A_CTRL_PC31DOWNTO12_shadow_intermed_4;
V_A_CTRL_PC31DOWNTO12_shadow_intermed_6 <= V_A_CTRL_PC31DOWNTO12_shadow_intermed_5;
V_E_CTRL_PC31DOWNTO12_shadow_intermed_1 <= V_E_CTRL_PC31DOWNTO12_shadow;
V_E_CTRL_PC31DOWNTO12_shadow_intermed_2 <= V_E_CTRL_PC31DOWNTO12_shadow_intermed_1;
V_E_CTRL_PC31DOWNTO12_shadow_intermed_3 <= V_E_CTRL_PC31DOWNTO12_shadow_intermed_2;
V_E_CTRL_PC31DOWNTO12_shadow_intermed_4 <= V_E_CTRL_PC31DOWNTO12_shadow_intermed_3;
V_E_CTRL_PC31DOWNTO12_shadow_intermed_5 <= V_E_CTRL_PC31DOWNTO12_shadow_intermed_4;
EX_ADD_RES32DOWNTO330DOWNTO11_shadow_intermed_1 <= EX_ADD_RES32DOWNTO330DOWNTO11_shadow;
EX_ADD_RES32DOWNTO330DOWNTO11_shadow_intermed_2 <= EX_ADD_RES32DOWNTO330DOWNTO11_shadow_intermed_1;
RIN_F_PC31DOWNTO12_intermed_1 <= RIN.F.PC( 31 DOWNTO 12 );
RIN_F_PC31DOWNTO12_intermed_2 <= RIN_F_PC31DOWNTO12_intermed_1;
R_A_CTRL_PC31DOWNTO12_intermed_1 <= R.A.CTRL.PC( 31 DOWNTO 12 );
R_A_CTRL_PC31DOWNTO12_intermed_2 <= R_A_CTRL_PC31DOWNTO12_intermed_1;
R_A_CTRL_PC31DOWNTO12_intermed_3 <= R_A_CTRL_PC31DOWNTO12_intermed_2;
R_A_CTRL_PC31DOWNTO12_intermed_4 <= R_A_CTRL_PC31DOWNTO12_intermed_3;
R_A_CTRL_PC31DOWNTO12_intermed_5 <= R_A_CTRL_PC31DOWNTO12_intermed_4;
R_E_CTRL_PC31DOWNTO12_intermed_1 <= R.E.CTRL.PC( 31 DOWNTO 12 );
R_E_CTRL_PC31DOWNTO12_intermed_2 <= R_E_CTRL_PC31DOWNTO12_intermed_1;
R_E_CTRL_PC31DOWNTO12_intermed_3 <= R_E_CTRL_PC31DOWNTO12_intermed_2;
R_E_CTRL_PC31DOWNTO12_intermed_4 <= R_E_CTRL_PC31DOWNTO12_intermed_3;
EX_JUMP_ADDRESS31DOWNTO12_shadow_intermed_1 <= EX_JUMP_ADDRESS31DOWNTO12_shadow;
EX_JUMP_ADDRESS31DOWNTO12_shadow_intermed_2 <= EX_JUMP_ADDRESS31DOWNTO12_shadow_intermed_1;
RIN_F_PC31DOWNTO12_intermed_1 <= RIN.F.PC ( 31 DOWNTO 12 );
RIN_A_CTRL_PC31DOWNTO12_intermed_1 <= RIN.A.CTRL.PC( 31 DOWNTO 12 );
RIN_A_CTRL_PC31DOWNTO12_intermed_2 <= RIN_A_CTRL_PC31DOWNTO12_intermed_1;
RIN_A_CTRL_PC31DOWNTO12_intermed_3 <= RIN_A_CTRL_PC31DOWNTO12_intermed_2;
RIN_A_CTRL_PC31DOWNTO12_intermed_4 <= RIN_A_CTRL_PC31DOWNTO12_intermed_3;
RIN_A_CTRL_PC31DOWNTO12_intermed_5 <= RIN_A_CTRL_PC31DOWNTO12_intermed_4;
RIN_A_CTRL_PC31DOWNTO12_intermed_6 <= RIN_A_CTRL_PC31DOWNTO12_intermed_5;
RIN_E_CTRL_PC31DOWNTO12_intermed_1 <= RIN.E.CTRL.PC( 31 DOWNTO 12 );
RIN_E_CTRL_PC31DOWNTO12_intermed_2 <= RIN_E_CTRL_PC31DOWNTO12_intermed_1;
RIN_E_CTRL_PC31DOWNTO12_intermed_3 <= RIN_E_CTRL_PC31DOWNTO12_intermed_2;
RIN_E_CTRL_PC31DOWNTO12_intermed_4 <= RIN_E_CTRL_PC31DOWNTO12_intermed_3;
RIN_E_CTRL_PC31DOWNTO12_intermed_5 <= RIN_E_CTRL_PC31DOWNTO12_intermed_4;
V_F_PC31DOWNTO12_shadow_intermed_1 <= V_F_PC31DOWNTO12_shadow;
V_F_PC31DOWNTO12_shadow_intermed_2 <= V_F_PC31DOWNTO12_shadow_intermed_1;
IRIN_ADDR31DOWNTO12_intermed_1 <= IRIN.ADDR( 31 DOWNTO 12 );
IRIN_ADDR31DOWNTO12_intermed_2 <= IRIN_ADDR31DOWNTO12_intermed_1;
V_X_CTRL_PC31DOWNTO12_shadow_intermed_1 <= V_X_CTRL_PC31DOWNTO12_shadow;
V_X_CTRL_PC31DOWNTO12_shadow_intermed_2 <= V_X_CTRL_PC31DOWNTO12_shadow_intermed_1;
V_X_CTRL_PC31DOWNTO12_shadow_intermed_3 <= V_X_CTRL_PC31DOWNTO12_shadow_intermed_2;
EX_ADD_RES32DOWNTO332DOWNTO13_shadow_intermed_1 <= EX_ADD_RES32DOWNTO332DOWNTO13_shadow;
EX_ADD_RES32DOWNTO332DOWNTO13_shadow_intermed_2 <= EX_ADD_RES32DOWNTO332DOWNTO13_shadow_intermed_1;
XC_TRAP_ADDRESS31DOWNTO12_shadow_intermed_1 <= XC_TRAP_ADDRESS31DOWNTO12_shadow;
R_F_PC31DOWNTO12_intermed_1 <= R.F.PC( 31 DOWNTO 12 );
RIN_M_CTRL_PC31DOWNTO12_intermed_1 <= RIN.M.CTRL.PC( 31 DOWNTO 12 );
RIN_M_CTRL_PC31DOWNTO12_intermed_2 <= RIN_M_CTRL_PC31DOWNTO12_intermed_1;
RIN_M_CTRL_PC31DOWNTO12_intermed_3 <= RIN_M_CTRL_PC31DOWNTO12_intermed_2;
RIN_M_CTRL_PC31DOWNTO12_intermed_4 <= RIN_M_CTRL_PC31DOWNTO12_intermed_3;
IR_ADDR31DOWNTO12_intermed_1 <= IR.ADDR( 31 DOWNTO 12 );
R_X_CTRL_PC31DOWNTO12_intermed_1 <= R.X.CTRL.PC( 31 DOWNTO 12 );
R_X_CTRL_PC31DOWNTO12_intermed_2 <= R_X_CTRL_PC31DOWNTO12_intermed_1;
R_D_PC31DOWNTO12_intermed_1 <= R.D.PC( 31 DOWNTO 12 );
R_D_PC31DOWNTO12_intermed_2 <= R_D_PC31DOWNTO12_intermed_1;
R_D_PC31DOWNTO12_intermed_3 <= R_D_PC31DOWNTO12_intermed_2;
R_D_PC31DOWNTO12_intermed_4 <= R_D_PC31DOWNTO12_intermed_3;
R_D_PC31DOWNTO12_intermed_5 <= R_D_PC31DOWNTO12_intermed_4;
R_D_PC31DOWNTO12_intermed_6 <= R_D_PC31DOWNTO12_intermed_5;
RIN_X_CTRL_PC31DOWNTO12_intermed_1 <= RIN.X.CTRL.PC( 31 DOWNTO 12 );
RIN_X_CTRL_PC31DOWNTO12_intermed_2 <= RIN_X_CTRL_PC31DOWNTO12_intermed_1;
RIN_X_CTRL_PC31DOWNTO12_intermed_3 <= RIN_X_CTRL_PC31DOWNTO12_intermed_2;
RIN_D_PC31DOWNTO12_intermed_1 <= RIN.D.PC( 31 DOWNTO 12 );
RIN_D_PC31DOWNTO12_intermed_2 <= RIN_D_PC31DOWNTO12_intermed_1;
RIN_D_PC31DOWNTO12_intermed_3 <= RIN_D_PC31DOWNTO12_intermed_2;
RIN_D_PC31DOWNTO12_intermed_4 <= RIN_D_PC31DOWNTO12_intermed_3;
RIN_D_PC31DOWNTO12_intermed_5 <= RIN_D_PC31DOWNTO12_intermed_4;
RIN_D_PC31DOWNTO12_intermed_6 <= RIN_D_PC31DOWNTO12_intermed_5;
RIN_D_PC31DOWNTO12_intermed_7 <= RIN_D_PC31DOWNTO12_intermed_6;
VIR_ADDR31DOWNTO12_shadow_intermed_1 <= VIR_ADDR31DOWNTO12_shadow;
VIR_ADDR31DOWNTO12_shadow_intermed_2 <= VIR_ADDR31DOWNTO12_shadow_intermed_1;
V_M_CTRL_PC31DOWNTO12_shadow_intermed_1 <= V_M_CTRL_PC31DOWNTO12_shadow;
V_M_CTRL_PC31DOWNTO12_shadow_intermed_2 <= V_M_CTRL_PC31DOWNTO12_shadow_intermed_1;
V_M_CTRL_PC31DOWNTO12_shadow_intermed_3 <= V_M_CTRL_PC31DOWNTO12_shadow_intermed_2;
V_M_CTRL_PC31DOWNTO12_shadow_intermed_4 <= V_M_CTRL_PC31DOWNTO12_shadow_intermed_3;
RIN_M_CTRL_PC31DOWNTO2_intermed_1 <= RIN.M.CTRL.PC( 31 DOWNTO 2 );
RIN_M_CTRL_PC31DOWNTO2_intermed_2 <= RIN_M_CTRL_PC31DOWNTO2_intermed_1;
RIN_M_CTRL_PC31DOWNTO2_intermed_3 <= RIN_M_CTRL_PC31DOWNTO2_intermed_2;
RIN_M_CTRL_PC31DOWNTO2_intermed_4 <= RIN_M_CTRL_PC31DOWNTO2_intermed_3;
V_D_PC31DOWNTO2_shadow_intermed_1 <= V_D_PC31DOWNTO2_shadow;
V_D_PC31DOWNTO2_shadow_intermed_2 <= V_D_PC31DOWNTO2_shadow_intermed_1;
V_D_PC31DOWNTO2_shadow_intermed_3 <= V_D_PC31DOWNTO2_shadow_intermed_2;
V_D_PC31DOWNTO2_shadow_intermed_4 <= V_D_PC31DOWNTO2_shadow_intermed_3;
V_D_PC31DOWNTO2_shadow_intermed_5 <= V_D_PC31DOWNTO2_shadow_intermed_4;
V_D_PC31DOWNTO2_shadow_intermed_6 <= V_D_PC31DOWNTO2_shadow_intermed_5;
V_D_PC31DOWNTO2_shadow_intermed_7 <= V_D_PC31DOWNTO2_shadow_intermed_6;
RIN_D_PC31DOWNTO2_intermed_1 <= RIN.D.PC( 31 DOWNTO 2 );
RIN_D_PC31DOWNTO2_intermed_2 <= RIN_D_PC31DOWNTO2_intermed_1;
RIN_D_PC31DOWNTO2_intermed_3 <= RIN_D_PC31DOWNTO2_intermed_2;
RIN_D_PC31DOWNTO2_intermed_4 <= RIN_D_PC31DOWNTO2_intermed_3;
RIN_D_PC31DOWNTO2_intermed_5 <= RIN_D_PC31DOWNTO2_intermed_4;
RIN_D_PC31DOWNTO2_intermed_6 <= RIN_D_PC31DOWNTO2_intermed_5;
RIN_D_PC31DOWNTO2_intermed_7 <= RIN_D_PC31DOWNTO2_intermed_6;
EX_ADD_RES32DOWNTO332DOWNTO3_shadow_intermed_1 <= EX_ADD_RES32DOWNTO332DOWNTO3_shadow;
EX_ADD_RES32DOWNTO332DOWNTO3_shadow_intermed_2 <= EX_ADD_RES32DOWNTO332DOWNTO3_shadow_intermed_1;
V_F_PC31DOWNTO2_shadow_intermed_1 <= V_F_PC31DOWNTO2_shadow;
V_F_PC31DOWNTO2_shadow_intermed_2 <= V_F_PC31DOWNTO2_shadow_intermed_1;
RIN_F_PC31DOWNTO2_intermed_1 <= RIN.F.PC( 31 DOWNTO 2 );
RIN_F_PC31DOWNTO2_intermed_2 <= RIN_F_PC31DOWNTO2_intermed_1;
RIN_X_CTRL_PC31DOWNTO2_intermed_1 <= RIN.X.CTRL.PC( 31 DOWNTO 2 );
RIN_X_CTRL_PC31DOWNTO2_intermed_2 <= RIN_X_CTRL_PC31DOWNTO2_intermed_1;
RIN_X_CTRL_PC31DOWNTO2_intermed_3 <= RIN_X_CTRL_PC31DOWNTO2_intermed_2;
IRIN_ADDR31DOWNTO2_intermed_1 <= IRIN.ADDR( 31 DOWNTO 2 );
IRIN_ADDR31DOWNTO2_intermed_2 <= IRIN_ADDR31DOWNTO2_intermed_1;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO2_shadow;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_2;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_4 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_3;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_5 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_4;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_6 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_5;
R_D_PC31DOWNTO2_intermed_1 <= R.D.PC( 31 DOWNTO 2 );
R_D_PC31DOWNTO2_intermed_2 <= R_D_PC31DOWNTO2_intermed_1;
R_D_PC31DOWNTO2_intermed_3 <= R_D_PC31DOWNTO2_intermed_2;
R_D_PC31DOWNTO2_intermed_4 <= R_D_PC31DOWNTO2_intermed_3;
R_D_PC31DOWNTO2_intermed_5 <= R_D_PC31DOWNTO2_intermed_4;
R_D_PC31DOWNTO2_intermed_6 <= R_D_PC31DOWNTO2_intermed_5;
R_F_PC31DOWNTO2_intermed_1 <= R.F.PC( 31 DOWNTO 2 );
VIR_ADDR31DOWNTO2_shadow_intermed_1 <= VIR_ADDR31DOWNTO2_shadow;
VIR_ADDR31DOWNTO2_shadow_intermed_2 <= VIR_ADDR31DOWNTO2_shadow_intermed_1;
R_M_CTRL_PC31DOWNTO2_intermed_1 <= R.M.CTRL.PC( 31 DOWNTO 2 );
R_M_CTRL_PC31DOWNTO2_intermed_2 <= R_M_CTRL_PC31DOWNTO2_intermed_1;
R_M_CTRL_PC31DOWNTO2_intermed_3 <= R_M_CTRL_PC31DOWNTO2_intermed_2;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_E_CTRL_PC31DOWNTO2_shadow;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_2;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_4 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_3;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_5 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_4;
RIN_A_CTRL_PC31DOWNTO2_intermed_1 <= RIN.A.CTRL.PC( 31 DOWNTO 2 );
RIN_A_CTRL_PC31DOWNTO2_intermed_2 <= RIN_A_CTRL_PC31DOWNTO2_intermed_1;
RIN_A_CTRL_PC31DOWNTO2_intermed_3 <= RIN_A_CTRL_PC31DOWNTO2_intermed_2;
RIN_A_CTRL_PC31DOWNTO2_intermed_4 <= RIN_A_CTRL_PC31DOWNTO2_intermed_3;
RIN_A_CTRL_PC31DOWNTO2_intermed_5 <= RIN_A_CTRL_PC31DOWNTO2_intermed_4;
RIN_A_CTRL_PC31DOWNTO2_intermed_6 <= RIN_A_CTRL_PC31DOWNTO2_intermed_5;
R_A_CTRL_PC31DOWNTO2_intermed_1 <= R.A.CTRL.PC( 31 DOWNTO 2 );
R_A_CTRL_PC31DOWNTO2_intermed_2 <= R_A_CTRL_PC31DOWNTO2_intermed_1;
R_A_CTRL_PC31DOWNTO2_intermed_3 <= R_A_CTRL_PC31DOWNTO2_intermed_2;
R_A_CTRL_PC31DOWNTO2_intermed_4 <= R_A_CTRL_PC31DOWNTO2_intermed_3;
R_A_CTRL_PC31DOWNTO2_intermed_5 <= R_A_CTRL_PC31DOWNTO2_intermed_4;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_M_CTRL_PC31DOWNTO2_shadow;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_M_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_M_CTRL_PC31DOWNTO2_shadow_intermed_2;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_4 <= V_M_CTRL_PC31DOWNTO2_shadow_intermed_3;
R_X_CTRL_PC31DOWNTO2_intermed_1 <= R.X.CTRL.PC( 31 DOWNTO 2 );
R_X_CTRL_PC31DOWNTO2_intermed_2 <= R_X_CTRL_PC31DOWNTO2_intermed_1;
XC_TRAP_ADDRESS31DOWNTO2_shadow_intermed_1 <= XC_TRAP_ADDRESS31DOWNTO2_shadow;
R_E_CTRL_PC31DOWNTO2_intermed_1 <= R.E.CTRL.PC( 31 DOWNTO 2 );
R_E_CTRL_PC31DOWNTO2_intermed_2 <= R_E_CTRL_PC31DOWNTO2_intermed_1;
R_E_CTRL_PC31DOWNTO2_intermed_3 <= R_E_CTRL_PC31DOWNTO2_intermed_2;
R_E_CTRL_PC31DOWNTO2_intermed_4 <= R_E_CTRL_PC31DOWNTO2_intermed_3;
EX_JUMP_ADDRESS31DOWNTO2_shadow_intermed_1 <= EX_JUMP_ADDRESS31DOWNTO2_shadow;
EX_JUMP_ADDRESS31DOWNTO2_shadow_intermed_2 <= EX_JUMP_ADDRESS31DOWNTO2_shadow_intermed_1;
RIN_F_PC31DOWNTO2_intermed_1 <= RIN.F.PC ( 31 DOWNTO 2 );
IR_ADDR31DOWNTO2_intermed_1 <= IR.ADDR( 31 DOWNTO 2 );
RIN_E_CTRL_PC31DOWNTO2_intermed_1 <= RIN.E.CTRL.PC( 31 DOWNTO 2 );
RIN_E_CTRL_PC31DOWNTO2_intermed_2 <= RIN_E_CTRL_PC31DOWNTO2_intermed_1;
RIN_E_CTRL_PC31DOWNTO2_intermed_3 <= RIN_E_CTRL_PC31DOWNTO2_intermed_2;
RIN_E_CTRL_PC31DOWNTO2_intermed_4 <= RIN_E_CTRL_PC31DOWNTO2_intermed_3;
RIN_E_CTRL_PC31DOWNTO2_intermed_5 <= RIN_E_CTRL_PC31DOWNTO2_intermed_4;
V_X_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_X_CTRL_PC31DOWNTO2_shadow;
V_X_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_X_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_X_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_X_CTRL_PC31DOWNTO2_shadow_intermed_2;
RIN_M_CTRL_PC31DOWNTO2_intermed_1 <= RIN.M.CTRL.PC( 31 DOWNTO 2 );
RIN_M_CTRL_PC31DOWNTO2_intermed_2 <= RIN_M_CTRL_PC31DOWNTO2_intermed_1;
RIN_M_CTRL_PC31DOWNTO2_intermed_3 <= RIN_M_CTRL_PC31DOWNTO2_intermed_2;
RIN_M_CTRL_PC31DOWNTO2_intermed_4 <= RIN_M_CTRL_PC31DOWNTO2_intermed_3;
V_D_PC31DOWNTO2_shadow_intermed_1 <= V_D_PC31DOWNTO2_shadow;
V_D_PC31DOWNTO2_shadow_intermed_2 <= V_D_PC31DOWNTO2_shadow_intermed_1;
V_D_PC31DOWNTO2_shadow_intermed_3 <= V_D_PC31DOWNTO2_shadow_intermed_2;
V_D_PC31DOWNTO2_shadow_intermed_4 <= V_D_PC31DOWNTO2_shadow_intermed_3;
V_D_PC31DOWNTO2_shadow_intermed_5 <= V_D_PC31DOWNTO2_shadow_intermed_4;
V_D_PC31DOWNTO2_shadow_intermed_6 <= V_D_PC31DOWNTO2_shadow_intermed_5;
V_D_PC31DOWNTO2_shadow_intermed_7 <= V_D_PC31DOWNTO2_shadow_intermed_6;
RIN_D_PC31DOWNTO2_intermed_1 <= RIN.D.PC( 31 DOWNTO 2 );
RIN_D_PC31DOWNTO2_intermed_2 <= RIN_D_PC31DOWNTO2_intermed_1;
RIN_D_PC31DOWNTO2_intermed_3 <= RIN_D_PC31DOWNTO2_intermed_2;
RIN_D_PC31DOWNTO2_intermed_4 <= RIN_D_PC31DOWNTO2_intermed_3;
RIN_D_PC31DOWNTO2_intermed_5 <= RIN_D_PC31DOWNTO2_intermed_4;
RIN_D_PC31DOWNTO2_intermed_6 <= RIN_D_PC31DOWNTO2_intermed_5;
RIN_D_PC31DOWNTO2_intermed_7 <= RIN_D_PC31DOWNTO2_intermed_6;
EX_ADD_RES32DOWNTO332DOWNTO3_shadow_intermed_1 <= EX_ADD_RES32DOWNTO332DOWNTO3_shadow;
V_F_PC31DOWNTO2_shadow_intermed_1 <= V_F_PC31DOWNTO2_shadow;
RIN_F_PC31DOWNTO2_intermed_1 <= RIN.F.PC( 31 DOWNTO 2 );
RIN_X_CTRL_PC31DOWNTO2_intermed_1 <= RIN.X.CTRL.PC( 31 DOWNTO 2 );
RIN_X_CTRL_PC31DOWNTO2_intermed_2 <= RIN_X_CTRL_PC31DOWNTO2_intermed_1;
RIN_X_CTRL_PC31DOWNTO2_intermed_3 <= RIN_X_CTRL_PC31DOWNTO2_intermed_2;
IRIN_ADDR31DOWNTO2_intermed_1 <= IRIN.ADDR( 31 DOWNTO 2 );
IRIN_ADDR31DOWNTO2_intermed_2 <= IRIN_ADDR31DOWNTO2_intermed_1;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO2_shadow;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_2;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_4 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_3;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_5 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_4;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_6 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_5;
R_D_PC31DOWNTO2_intermed_1 <= R.D.PC( 31 DOWNTO 2 );
R_D_PC31DOWNTO2_intermed_2 <= R_D_PC31DOWNTO2_intermed_1;
R_D_PC31DOWNTO2_intermed_3 <= R_D_PC31DOWNTO2_intermed_2;
R_D_PC31DOWNTO2_intermed_4 <= R_D_PC31DOWNTO2_intermed_3;
R_D_PC31DOWNTO2_intermed_5 <= R_D_PC31DOWNTO2_intermed_4;
R_D_PC31DOWNTO2_intermed_6 <= R_D_PC31DOWNTO2_intermed_5;
VIR_ADDR31DOWNTO2_shadow_intermed_1 <= VIR_ADDR31DOWNTO2_shadow;
VIR_ADDR31DOWNTO2_shadow_intermed_2 <= VIR_ADDR31DOWNTO2_shadow_intermed_1;
R_M_CTRL_PC31DOWNTO2_intermed_1 <= R.M.CTRL.PC( 31 DOWNTO 2 );
R_M_CTRL_PC31DOWNTO2_intermed_2 <= R_M_CTRL_PC31DOWNTO2_intermed_1;
R_M_CTRL_PC31DOWNTO2_intermed_3 <= R_M_CTRL_PC31DOWNTO2_intermed_2;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_E_CTRL_PC31DOWNTO2_shadow;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_2;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_4 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_3;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_5 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_4;
RIN_A_CTRL_PC31DOWNTO2_intermed_1 <= RIN.A.CTRL.PC( 31 DOWNTO 2 );
RIN_A_CTRL_PC31DOWNTO2_intermed_2 <= RIN_A_CTRL_PC31DOWNTO2_intermed_1;
RIN_A_CTRL_PC31DOWNTO2_intermed_3 <= RIN_A_CTRL_PC31DOWNTO2_intermed_2;
RIN_A_CTRL_PC31DOWNTO2_intermed_4 <= RIN_A_CTRL_PC31DOWNTO2_intermed_3;
RIN_A_CTRL_PC31DOWNTO2_intermed_5 <= RIN_A_CTRL_PC31DOWNTO2_intermed_4;
RIN_A_CTRL_PC31DOWNTO2_intermed_6 <= RIN_A_CTRL_PC31DOWNTO2_intermed_5;
R_A_CTRL_PC31DOWNTO2_intermed_1 <= R.A.CTRL.PC( 31 DOWNTO 2 );
R_A_CTRL_PC31DOWNTO2_intermed_2 <= R_A_CTRL_PC31DOWNTO2_intermed_1;
R_A_CTRL_PC31DOWNTO2_intermed_3 <= R_A_CTRL_PC31DOWNTO2_intermed_2;
R_A_CTRL_PC31DOWNTO2_intermed_4 <= R_A_CTRL_PC31DOWNTO2_intermed_3;
R_A_CTRL_PC31DOWNTO2_intermed_5 <= R_A_CTRL_PC31DOWNTO2_intermed_4;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_M_CTRL_PC31DOWNTO2_shadow;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_M_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_M_CTRL_PC31DOWNTO2_shadow_intermed_2;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_4 <= V_M_CTRL_PC31DOWNTO2_shadow_intermed_3;
R_X_CTRL_PC31DOWNTO2_intermed_1 <= R.X.CTRL.PC( 31 DOWNTO 2 );
R_X_CTRL_PC31DOWNTO2_intermed_2 <= R_X_CTRL_PC31DOWNTO2_intermed_1;
XC_TRAP_ADDRESS31DOWNTO2_shadow_intermed_1 <= XC_TRAP_ADDRESS31DOWNTO2_shadow;
R_E_CTRL_PC31DOWNTO2_intermed_1 <= R.E.CTRL.PC( 31 DOWNTO 2 );
R_E_CTRL_PC31DOWNTO2_intermed_2 <= R_E_CTRL_PC31DOWNTO2_intermed_1;
R_E_CTRL_PC31DOWNTO2_intermed_3 <= R_E_CTRL_PC31DOWNTO2_intermed_2;
R_E_CTRL_PC31DOWNTO2_intermed_4 <= R_E_CTRL_PC31DOWNTO2_intermed_3;
EX_JUMP_ADDRESS31DOWNTO2_shadow_intermed_1 <= EX_JUMP_ADDRESS31DOWNTO2_shadow;
IR_ADDR31DOWNTO2_intermed_1 <= IR.ADDR( 31 DOWNTO 2 );
RIN_E_CTRL_PC31DOWNTO2_intermed_1 <= RIN.E.CTRL.PC( 31 DOWNTO 2 );
RIN_E_CTRL_PC31DOWNTO2_intermed_2 <= RIN_E_CTRL_PC31DOWNTO2_intermed_1;
RIN_E_CTRL_PC31DOWNTO2_intermed_3 <= RIN_E_CTRL_PC31DOWNTO2_intermed_2;
RIN_E_CTRL_PC31DOWNTO2_intermed_4 <= RIN_E_CTRL_PC31DOWNTO2_intermed_3;
RIN_E_CTRL_PC31DOWNTO2_intermed_5 <= RIN_E_CTRL_PC31DOWNTO2_intermed_4;
V_X_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_X_CTRL_PC31DOWNTO2_shadow;
V_X_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_X_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_X_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_X_CTRL_PC31DOWNTO2_shadow_intermed_2;
RIN_D_SET_intermed_1 <= RIN.D.SET;
RIN_D_MEXC_intermed_1 <= RIN.D.MEXC;
RIN_X_DATA031_intermed_1 <= RIN.X.DATA ( 0 )( 31 );
RIN_E_OP131_intermed_1 <= RIN.E.OP1( 31 );
V_X_DATA031_shadow_intermed_1 <= V_X_DATA031_shadow;
V_X_DATA031_shadow_intermed_1 <= V_X_DATA031_shadow;
V_X_DATA031_shadow_intermed_2 <= V_X_DATA031_shadow_intermed_1;
RIN_X_DATA031_intermed_1 <= RIN.X.DATA( 0 )( 31 );
RIN_X_DATA031_intermed_2 <= RIN_X_DATA031_intermed_1;
V_E_OP131_shadow_intermed_1 <= V_E_OP131_shadow;
R_X_DATA031_intermed_1 <= R.X.DATA( 0 )( 31 );
RIN_X_DATA031_intermed_1 <= RIN.X.DATA ( 0 )( 31 );
V_X_DATA031_shadow_intermed_1 <= V_X_DATA031_shadow;
V_X_DATA031_shadow_intermed_1 <= V_X_DATA031_shadow;
V_X_DATA031_shadow_intermed_2 <= V_X_DATA031_shadow_intermed_1;
RIN_X_DATA031_intermed_1 <= RIN.X.DATA( 0 )( 31 );
RIN_X_DATA031_intermed_2 <= RIN_X_DATA031_intermed_1;
RIN_E_OP231_intermed_1 <= RIN.E.OP2( 31 );
R_X_DATA031_intermed_1 <= R.X.DATA( 0 )( 31 );
V_E_OP231_shadow_intermed_1 <= V_E_OP231_shadow;
V_D_ANNUL_shadow_intermed_1 <= V_D_ANNUL_shadow;
RIN_X_ANNUL_ALL_intermed_1 <= RIN.X.ANNUL_ALL;
RIN_D_ANNUL_intermed_1 <= RIN.D.ANNUL;
V_X_DATA03_shadow_intermed_1 <= V_X_DATA03_shadow;
V_X_DATA03_shadow_intermed_2 <= V_X_DATA03_shadow_intermed_1;
V_X_DATA03_shadow_intermed_1 <= V_X_DATA03_shadow;
RIN_X_DATA03_intermed_1 <= RIN.X.DATA ( 0 )( 3 );
R_X_DATA03_intermed_1 <= R.X.DATA( 0 )( 3 );
RIN_X_DATA03_intermed_1 <= RIN.X.DATA( 0 )( 3 );
RIN_X_DATA03_intermed_2 <= RIN_X_DATA03_intermed_1;
RIN_E_OP13_intermed_1 <= RIN.E.OP1( 3 );
V_E_OP13_shadow_intermed_1 <= V_E_OP13_shadow;
V_X_DATA03_shadow_intermed_1 <= V_X_DATA03_shadow;
V_X_DATA03_shadow_intermed_2 <= V_X_DATA03_shadow_intermed_1;
V_X_DATA03_shadow_intermed_1 <= V_X_DATA03_shadow;
RIN_X_DATA03_intermed_1 <= RIN.X.DATA ( 0 )( 3 );
R_X_DATA03_intermed_1 <= R.X.DATA( 0 )( 3 );
RIN_X_DATA03_intermed_1 <= RIN.X.DATA( 0 )( 3 );
RIN_X_DATA03_intermed_2 <= RIN_X_DATA03_intermed_1;
RIN_E_OP23_intermed_1 <= RIN.E.OP2( 3 );
V_E_OP23_shadow_intermed_1 <= V_E_OP23_shadow;
R_M_CTRL_PC31DOWNTO12_intermed_1 <= R.M.CTRL.PC( 31 DOWNTO 12 );
R_M_CTRL_PC31DOWNTO12_intermed_2 <= R_M_CTRL_PC31DOWNTO12_intermed_1;
R_M_CTRL_PC31DOWNTO12_intermed_3 <= R_M_CTRL_PC31DOWNTO12_intermed_2;
V_D_PC31DOWNTO12_shadow_intermed_1 <= V_D_PC31DOWNTO12_shadow;
V_D_PC31DOWNTO12_shadow_intermed_2 <= V_D_PC31DOWNTO12_shadow_intermed_1;
V_D_PC31DOWNTO12_shadow_intermed_3 <= V_D_PC31DOWNTO12_shadow_intermed_2;
V_D_PC31DOWNTO12_shadow_intermed_4 <= V_D_PC31DOWNTO12_shadow_intermed_3;
V_D_PC31DOWNTO12_shadow_intermed_5 <= V_D_PC31DOWNTO12_shadow_intermed_4;
V_D_PC31DOWNTO12_shadow_intermed_6 <= V_D_PC31DOWNTO12_shadow_intermed_5;
V_D_PC31DOWNTO12_shadow_intermed_7 <= V_D_PC31DOWNTO12_shadow_intermed_6;
V_A_CTRL_PC31DOWNTO12_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO12_shadow;
V_A_CTRL_PC31DOWNTO12_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO12_shadow_intermed_1;
V_A_CTRL_PC31DOWNTO12_shadow_intermed_3 <= V_A_CTRL_PC31DOWNTO12_shadow_intermed_2;
V_A_CTRL_PC31DOWNTO12_shadow_intermed_4 <= V_A_CTRL_PC31DOWNTO12_shadow_intermed_3;
V_A_CTRL_PC31DOWNTO12_shadow_intermed_5 <= V_A_CTRL_PC31DOWNTO12_shadow_intermed_4;
V_A_CTRL_PC31DOWNTO12_shadow_intermed_6 <= V_A_CTRL_PC31DOWNTO12_shadow_intermed_5;
V_E_CTRL_PC31DOWNTO12_shadow_intermed_1 <= V_E_CTRL_PC31DOWNTO12_shadow;
V_E_CTRL_PC31DOWNTO12_shadow_intermed_2 <= V_E_CTRL_PC31DOWNTO12_shadow_intermed_1;
V_E_CTRL_PC31DOWNTO12_shadow_intermed_3 <= V_E_CTRL_PC31DOWNTO12_shadow_intermed_2;
V_E_CTRL_PC31DOWNTO12_shadow_intermed_4 <= V_E_CTRL_PC31DOWNTO12_shadow_intermed_3;
V_E_CTRL_PC31DOWNTO12_shadow_intermed_5 <= V_E_CTRL_PC31DOWNTO12_shadow_intermed_4;
EX_ADD_RES32DOWNTO330DOWNTO11_shadow_intermed_1 <= EX_ADD_RES32DOWNTO330DOWNTO11_shadow;
RIN_F_PC31DOWNTO12_intermed_1 <= RIN.F.PC( 31 DOWNTO 12 );
R_A_CTRL_PC31DOWNTO12_intermed_1 <= R.A.CTRL.PC( 31 DOWNTO 12 );
R_A_CTRL_PC31DOWNTO12_intermed_2 <= R_A_CTRL_PC31DOWNTO12_intermed_1;
R_A_CTRL_PC31DOWNTO12_intermed_3 <= R_A_CTRL_PC31DOWNTO12_intermed_2;
R_A_CTRL_PC31DOWNTO12_intermed_4 <= R_A_CTRL_PC31DOWNTO12_intermed_3;
R_A_CTRL_PC31DOWNTO12_intermed_5 <= R_A_CTRL_PC31DOWNTO12_intermed_4;
R_E_CTRL_PC31DOWNTO12_intermed_1 <= R.E.CTRL.PC( 31 DOWNTO 12 );
R_E_CTRL_PC31DOWNTO12_intermed_2 <= R_E_CTRL_PC31DOWNTO12_intermed_1;
R_E_CTRL_PC31DOWNTO12_intermed_3 <= R_E_CTRL_PC31DOWNTO12_intermed_2;
R_E_CTRL_PC31DOWNTO12_intermed_4 <= R_E_CTRL_PC31DOWNTO12_intermed_3;
EX_JUMP_ADDRESS31DOWNTO12_shadow_intermed_1 <= EX_JUMP_ADDRESS31DOWNTO12_shadow;
RIN_A_CTRL_PC31DOWNTO12_intermed_1 <= RIN.A.CTRL.PC( 31 DOWNTO 12 );
RIN_A_CTRL_PC31DOWNTO12_intermed_2 <= RIN_A_CTRL_PC31DOWNTO12_intermed_1;
RIN_A_CTRL_PC31DOWNTO12_intermed_3 <= RIN_A_CTRL_PC31DOWNTO12_intermed_2;
RIN_A_CTRL_PC31DOWNTO12_intermed_4 <= RIN_A_CTRL_PC31DOWNTO12_intermed_3;
RIN_A_CTRL_PC31DOWNTO12_intermed_5 <= RIN_A_CTRL_PC31DOWNTO12_intermed_4;
RIN_A_CTRL_PC31DOWNTO12_intermed_6 <= RIN_A_CTRL_PC31DOWNTO12_intermed_5;
RIN_E_CTRL_PC31DOWNTO12_intermed_1 <= RIN.E.CTRL.PC( 31 DOWNTO 12 );
RIN_E_CTRL_PC31DOWNTO12_intermed_2 <= RIN_E_CTRL_PC31DOWNTO12_intermed_1;
RIN_E_CTRL_PC31DOWNTO12_intermed_3 <= RIN_E_CTRL_PC31DOWNTO12_intermed_2;
RIN_E_CTRL_PC31DOWNTO12_intermed_4 <= RIN_E_CTRL_PC31DOWNTO12_intermed_3;
RIN_E_CTRL_PC31DOWNTO12_intermed_5 <= RIN_E_CTRL_PC31DOWNTO12_intermed_4;
V_F_PC31DOWNTO12_shadow_intermed_1 <= V_F_PC31DOWNTO12_shadow;
IRIN_ADDR31DOWNTO12_intermed_1 <= IRIN.ADDR( 31 DOWNTO 12 );
IRIN_ADDR31DOWNTO12_intermed_2 <= IRIN_ADDR31DOWNTO12_intermed_1;
V_X_CTRL_PC31DOWNTO12_shadow_intermed_1 <= V_X_CTRL_PC31DOWNTO12_shadow;
V_X_CTRL_PC31DOWNTO12_shadow_intermed_2 <= V_X_CTRL_PC31DOWNTO12_shadow_intermed_1;
V_X_CTRL_PC31DOWNTO12_shadow_intermed_3 <= V_X_CTRL_PC31DOWNTO12_shadow_intermed_2;
EX_ADD_RES32DOWNTO332DOWNTO13_shadow_intermed_1 <= EX_ADD_RES32DOWNTO332DOWNTO13_shadow;
RIN_M_CTRL_PC31DOWNTO12_intermed_1 <= RIN.M.CTRL.PC( 31 DOWNTO 12 );
RIN_M_CTRL_PC31DOWNTO12_intermed_2 <= RIN_M_CTRL_PC31DOWNTO12_intermed_1;
RIN_M_CTRL_PC31DOWNTO12_intermed_3 <= RIN_M_CTRL_PC31DOWNTO12_intermed_2;
RIN_M_CTRL_PC31DOWNTO12_intermed_4 <= RIN_M_CTRL_PC31DOWNTO12_intermed_3;
IR_ADDR31DOWNTO12_intermed_1 <= IR.ADDR( 31 DOWNTO 12 );
R_X_CTRL_PC31DOWNTO12_intermed_1 <= R.X.CTRL.PC( 31 DOWNTO 12 );
R_X_CTRL_PC31DOWNTO12_intermed_2 <= R_X_CTRL_PC31DOWNTO12_intermed_1;
R_D_PC31DOWNTO12_intermed_1 <= R.D.PC( 31 DOWNTO 12 );
R_D_PC31DOWNTO12_intermed_2 <= R_D_PC31DOWNTO12_intermed_1;
R_D_PC31DOWNTO12_intermed_3 <= R_D_PC31DOWNTO12_intermed_2;
R_D_PC31DOWNTO12_intermed_4 <= R_D_PC31DOWNTO12_intermed_3;
R_D_PC31DOWNTO12_intermed_5 <= R_D_PC31DOWNTO12_intermed_4;
R_D_PC31DOWNTO12_intermed_6 <= R_D_PC31DOWNTO12_intermed_5;
RIN_X_CTRL_PC31DOWNTO12_intermed_1 <= RIN.X.CTRL.PC( 31 DOWNTO 12 );
RIN_X_CTRL_PC31DOWNTO12_intermed_2 <= RIN_X_CTRL_PC31DOWNTO12_intermed_1;
RIN_X_CTRL_PC31DOWNTO12_intermed_3 <= RIN_X_CTRL_PC31DOWNTO12_intermed_2;
RIN_D_PC31DOWNTO12_intermed_1 <= RIN.D.PC( 31 DOWNTO 12 );
RIN_D_PC31DOWNTO12_intermed_2 <= RIN_D_PC31DOWNTO12_intermed_1;
RIN_D_PC31DOWNTO12_intermed_3 <= RIN_D_PC31DOWNTO12_intermed_2;
RIN_D_PC31DOWNTO12_intermed_4 <= RIN_D_PC31DOWNTO12_intermed_3;
RIN_D_PC31DOWNTO12_intermed_5 <= RIN_D_PC31DOWNTO12_intermed_4;
RIN_D_PC31DOWNTO12_intermed_6 <= RIN_D_PC31DOWNTO12_intermed_5;
RIN_D_PC31DOWNTO12_intermed_7 <= RIN_D_PC31DOWNTO12_intermed_6;
VIR_ADDR31DOWNTO12_shadow_intermed_1 <= VIR_ADDR31DOWNTO12_shadow;
VIR_ADDR31DOWNTO12_shadow_intermed_2 <= VIR_ADDR31DOWNTO12_shadow_intermed_1;
V_M_CTRL_PC31DOWNTO12_shadow_intermed_1 <= V_M_CTRL_PC31DOWNTO12_shadow;
V_M_CTRL_PC31DOWNTO12_shadow_intermed_2 <= V_M_CTRL_PC31DOWNTO12_shadow_intermed_1;
V_M_CTRL_PC31DOWNTO12_shadow_intermed_3 <= V_M_CTRL_PC31DOWNTO12_shadow_intermed_2;
V_M_CTRL_PC31DOWNTO12_shadow_intermed_4 <= V_M_CTRL_PC31DOWNTO12_shadow_intermed_3;
RIN_M_CTRL_PC31DOWNTO2_intermed_1 <= RIN.M.CTRL.PC( 31 DOWNTO 2 );
RIN_M_CTRL_PC31DOWNTO2_intermed_2 <= RIN_M_CTRL_PC31DOWNTO2_intermed_1;
RIN_M_CTRL_PC31DOWNTO2_intermed_3 <= RIN_M_CTRL_PC31DOWNTO2_intermed_2;
RIN_M_CTRL_PC31DOWNTO2_intermed_4 <= RIN_M_CTRL_PC31DOWNTO2_intermed_3;
V_D_PC31DOWNTO2_shadow_intermed_1 <= V_D_PC31DOWNTO2_shadow;
V_D_PC31DOWNTO2_shadow_intermed_2 <= V_D_PC31DOWNTO2_shadow_intermed_1;
V_D_PC31DOWNTO2_shadow_intermed_3 <= V_D_PC31DOWNTO2_shadow_intermed_2;
V_D_PC31DOWNTO2_shadow_intermed_4 <= V_D_PC31DOWNTO2_shadow_intermed_3;
V_D_PC31DOWNTO2_shadow_intermed_5 <= V_D_PC31DOWNTO2_shadow_intermed_4;
V_D_PC31DOWNTO2_shadow_intermed_6 <= V_D_PC31DOWNTO2_shadow_intermed_5;
V_D_PC31DOWNTO2_shadow_intermed_7 <= V_D_PC31DOWNTO2_shadow_intermed_6;
RIN_D_PC31DOWNTO2_intermed_1 <= RIN.D.PC( 31 DOWNTO 2 );
RIN_D_PC31DOWNTO2_intermed_2 <= RIN_D_PC31DOWNTO2_intermed_1;
RIN_D_PC31DOWNTO2_intermed_3 <= RIN_D_PC31DOWNTO2_intermed_2;
RIN_D_PC31DOWNTO2_intermed_4 <= RIN_D_PC31DOWNTO2_intermed_3;
RIN_D_PC31DOWNTO2_intermed_5 <= RIN_D_PC31DOWNTO2_intermed_4;
RIN_D_PC31DOWNTO2_intermed_6 <= RIN_D_PC31DOWNTO2_intermed_5;
RIN_D_PC31DOWNTO2_intermed_7 <= RIN_D_PC31DOWNTO2_intermed_6;
EX_ADD_RES32DOWNTO332DOWNTO3_shadow_intermed_1 <= EX_ADD_RES32DOWNTO332DOWNTO3_shadow;
V_F_PC31DOWNTO2_shadow_intermed_1 <= V_F_PC31DOWNTO2_shadow;
RIN_F_PC31DOWNTO2_intermed_1 <= RIN.F.PC( 31 DOWNTO 2 );
RIN_X_CTRL_PC31DOWNTO2_intermed_1 <= RIN.X.CTRL.PC( 31 DOWNTO 2 );
RIN_X_CTRL_PC31DOWNTO2_intermed_2 <= RIN_X_CTRL_PC31DOWNTO2_intermed_1;
RIN_X_CTRL_PC31DOWNTO2_intermed_3 <= RIN_X_CTRL_PC31DOWNTO2_intermed_2;
IRIN_ADDR31DOWNTO2_intermed_1 <= IRIN.ADDR( 31 DOWNTO 2 );
IRIN_ADDR31DOWNTO2_intermed_2 <= IRIN_ADDR31DOWNTO2_intermed_1;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO2_shadow;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_2;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_4 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_3;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_5 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_4;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_6 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_5;
R_D_PC31DOWNTO2_intermed_1 <= R.D.PC( 31 DOWNTO 2 );
R_D_PC31DOWNTO2_intermed_2 <= R_D_PC31DOWNTO2_intermed_1;
R_D_PC31DOWNTO2_intermed_3 <= R_D_PC31DOWNTO2_intermed_2;
R_D_PC31DOWNTO2_intermed_4 <= R_D_PC31DOWNTO2_intermed_3;
R_D_PC31DOWNTO2_intermed_5 <= R_D_PC31DOWNTO2_intermed_4;
R_D_PC31DOWNTO2_intermed_6 <= R_D_PC31DOWNTO2_intermed_5;
VIR_ADDR31DOWNTO2_shadow_intermed_1 <= VIR_ADDR31DOWNTO2_shadow;
VIR_ADDR31DOWNTO2_shadow_intermed_2 <= VIR_ADDR31DOWNTO2_shadow_intermed_1;
R_M_CTRL_PC31DOWNTO2_intermed_1 <= R.M.CTRL.PC( 31 DOWNTO 2 );
R_M_CTRL_PC31DOWNTO2_intermed_2 <= R_M_CTRL_PC31DOWNTO2_intermed_1;
R_M_CTRL_PC31DOWNTO2_intermed_3 <= R_M_CTRL_PC31DOWNTO2_intermed_2;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_E_CTRL_PC31DOWNTO2_shadow;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_2;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_4 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_3;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_5 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_4;
RIN_A_CTRL_PC31DOWNTO2_intermed_1 <= RIN.A.CTRL.PC( 31 DOWNTO 2 );
RIN_A_CTRL_PC31DOWNTO2_intermed_2 <= RIN_A_CTRL_PC31DOWNTO2_intermed_1;
RIN_A_CTRL_PC31DOWNTO2_intermed_3 <= RIN_A_CTRL_PC31DOWNTO2_intermed_2;
RIN_A_CTRL_PC31DOWNTO2_intermed_4 <= RIN_A_CTRL_PC31DOWNTO2_intermed_3;
RIN_A_CTRL_PC31DOWNTO2_intermed_5 <= RIN_A_CTRL_PC31DOWNTO2_intermed_4;
RIN_A_CTRL_PC31DOWNTO2_intermed_6 <= RIN_A_CTRL_PC31DOWNTO2_intermed_5;
R_A_CTRL_PC31DOWNTO2_intermed_1 <= R.A.CTRL.PC( 31 DOWNTO 2 );
R_A_CTRL_PC31DOWNTO2_intermed_2 <= R_A_CTRL_PC31DOWNTO2_intermed_1;
R_A_CTRL_PC31DOWNTO2_intermed_3 <= R_A_CTRL_PC31DOWNTO2_intermed_2;
R_A_CTRL_PC31DOWNTO2_intermed_4 <= R_A_CTRL_PC31DOWNTO2_intermed_3;
R_A_CTRL_PC31DOWNTO2_intermed_5 <= R_A_CTRL_PC31DOWNTO2_intermed_4;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_M_CTRL_PC31DOWNTO2_shadow;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_M_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_M_CTRL_PC31DOWNTO2_shadow_intermed_2;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_4 <= V_M_CTRL_PC31DOWNTO2_shadow_intermed_3;
R_X_CTRL_PC31DOWNTO2_intermed_1 <= R.X.CTRL.PC( 31 DOWNTO 2 );
R_X_CTRL_PC31DOWNTO2_intermed_2 <= R_X_CTRL_PC31DOWNTO2_intermed_1;
R_E_CTRL_PC31DOWNTO2_intermed_1 <= R.E.CTRL.PC( 31 DOWNTO 2 );
R_E_CTRL_PC31DOWNTO2_intermed_2 <= R_E_CTRL_PC31DOWNTO2_intermed_1;
R_E_CTRL_PC31DOWNTO2_intermed_3 <= R_E_CTRL_PC31DOWNTO2_intermed_2;
R_E_CTRL_PC31DOWNTO2_intermed_4 <= R_E_CTRL_PC31DOWNTO2_intermed_3;
EX_JUMP_ADDRESS31DOWNTO2_shadow_intermed_1 <= EX_JUMP_ADDRESS31DOWNTO2_shadow;
IR_ADDR31DOWNTO2_intermed_1 <= IR.ADDR( 31 DOWNTO 2 );
RIN_E_CTRL_PC31DOWNTO2_intermed_1 <= RIN.E.CTRL.PC( 31 DOWNTO 2 );
RIN_E_CTRL_PC31DOWNTO2_intermed_2 <= RIN_E_CTRL_PC31DOWNTO2_intermed_1;
RIN_E_CTRL_PC31DOWNTO2_intermed_3 <= RIN_E_CTRL_PC31DOWNTO2_intermed_2;
RIN_E_CTRL_PC31DOWNTO2_intermed_4 <= RIN_E_CTRL_PC31DOWNTO2_intermed_3;
RIN_E_CTRL_PC31DOWNTO2_intermed_5 <= RIN_E_CTRL_PC31DOWNTO2_intermed_4;
V_X_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_X_CTRL_PC31DOWNTO2_shadow;
V_X_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_X_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_X_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_X_CTRL_PC31DOWNTO2_shadow_intermed_2;
RIN_M_CTRL_PC31DOWNTO2_intermed_1 <= RIN.M.CTRL.PC( 31 DOWNTO 2 );
RIN_M_CTRL_PC31DOWNTO2_intermed_2 <= RIN_M_CTRL_PC31DOWNTO2_intermed_1;
RIN_M_CTRL_PC31DOWNTO2_intermed_3 <= RIN_M_CTRL_PC31DOWNTO2_intermed_2;
RIN_M_CTRL_PC31DOWNTO2_intermed_4 <= RIN_M_CTRL_PC31DOWNTO2_intermed_3;
V_D_PC31DOWNTO2_shadow_intermed_1 <= V_D_PC31DOWNTO2_shadow;
V_D_PC31DOWNTO2_shadow_intermed_2 <= V_D_PC31DOWNTO2_shadow_intermed_1;
V_D_PC31DOWNTO2_shadow_intermed_3 <= V_D_PC31DOWNTO2_shadow_intermed_2;
V_D_PC31DOWNTO2_shadow_intermed_4 <= V_D_PC31DOWNTO2_shadow_intermed_3;
V_D_PC31DOWNTO2_shadow_intermed_5 <= V_D_PC31DOWNTO2_shadow_intermed_4;
V_D_PC31DOWNTO2_shadow_intermed_6 <= V_D_PC31DOWNTO2_shadow_intermed_5;
V_D_PC31DOWNTO2_shadow_intermed_7 <= V_D_PC31DOWNTO2_shadow_intermed_6;
RIN_D_PC31DOWNTO2_intermed_1 <= RIN.D.PC( 31 DOWNTO 2 );
RIN_D_PC31DOWNTO2_intermed_2 <= RIN_D_PC31DOWNTO2_intermed_1;
RIN_D_PC31DOWNTO2_intermed_3 <= RIN_D_PC31DOWNTO2_intermed_2;
RIN_D_PC31DOWNTO2_intermed_4 <= RIN_D_PC31DOWNTO2_intermed_3;
RIN_D_PC31DOWNTO2_intermed_5 <= RIN_D_PC31DOWNTO2_intermed_4;
RIN_D_PC31DOWNTO2_intermed_6 <= RIN_D_PC31DOWNTO2_intermed_5;
RIN_D_PC31DOWNTO2_intermed_7 <= RIN_D_PC31DOWNTO2_intermed_6;
EX_ADD_RES32DOWNTO332DOWNTO3_shadow_intermed_1 <= EX_ADD_RES32DOWNTO332DOWNTO3_shadow;
RIN_F_PC31DOWNTO2_intermed_1 <= RIN.F.PC( 31 DOWNTO 2 );
RIN_X_CTRL_PC31DOWNTO2_intermed_1 <= RIN.X.CTRL.PC( 31 DOWNTO 2 );
RIN_X_CTRL_PC31DOWNTO2_intermed_2 <= RIN_X_CTRL_PC31DOWNTO2_intermed_1;
RIN_X_CTRL_PC31DOWNTO2_intermed_3 <= RIN_X_CTRL_PC31DOWNTO2_intermed_2;
IRIN_ADDR31DOWNTO2_intermed_1 <= IRIN.ADDR( 31 DOWNTO 2 );
IRIN_ADDR31DOWNTO2_intermed_2 <= IRIN_ADDR31DOWNTO2_intermed_1;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO2_shadow;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_2;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_4 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_3;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_5 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_4;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_6 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_5;
R_D_PC31DOWNTO2_intermed_1 <= R.D.PC( 31 DOWNTO 2 );
R_D_PC31DOWNTO2_intermed_2 <= R_D_PC31DOWNTO2_intermed_1;
R_D_PC31DOWNTO2_intermed_3 <= R_D_PC31DOWNTO2_intermed_2;
R_D_PC31DOWNTO2_intermed_4 <= R_D_PC31DOWNTO2_intermed_3;
R_D_PC31DOWNTO2_intermed_5 <= R_D_PC31DOWNTO2_intermed_4;
R_D_PC31DOWNTO2_intermed_6 <= R_D_PC31DOWNTO2_intermed_5;
VIR_ADDR31DOWNTO2_shadow_intermed_1 <= VIR_ADDR31DOWNTO2_shadow;
VIR_ADDR31DOWNTO2_shadow_intermed_2 <= VIR_ADDR31DOWNTO2_shadow_intermed_1;
R_M_CTRL_PC31DOWNTO2_intermed_1 <= R.M.CTRL.PC( 31 DOWNTO 2 );
R_M_CTRL_PC31DOWNTO2_intermed_2 <= R_M_CTRL_PC31DOWNTO2_intermed_1;
R_M_CTRL_PC31DOWNTO2_intermed_3 <= R_M_CTRL_PC31DOWNTO2_intermed_2;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_E_CTRL_PC31DOWNTO2_shadow;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_2;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_4 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_3;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_5 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_4;
RIN_A_CTRL_PC31DOWNTO2_intermed_1 <= RIN.A.CTRL.PC( 31 DOWNTO 2 );
RIN_A_CTRL_PC31DOWNTO2_intermed_2 <= RIN_A_CTRL_PC31DOWNTO2_intermed_1;
RIN_A_CTRL_PC31DOWNTO2_intermed_3 <= RIN_A_CTRL_PC31DOWNTO2_intermed_2;
RIN_A_CTRL_PC31DOWNTO2_intermed_4 <= RIN_A_CTRL_PC31DOWNTO2_intermed_3;
RIN_A_CTRL_PC31DOWNTO2_intermed_5 <= RIN_A_CTRL_PC31DOWNTO2_intermed_4;
RIN_A_CTRL_PC31DOWNTO2_intermed_6 <= RIN_A_CTRL_PC31DOWNTO2_intermed_5;
R_A_CTRL_PC31DOWNTO2_intermed_1 <= R.A.CTRL.PC( 31 DOWNTO 2 );
R_A_CTRL_PC31DOWNTO2_intermed_2 <= R_A_CTRL_PC31DOWNTO2_intermed_1;
R_A_CTRL_PC31DOWNTO2_intermed_3 <= R_A_CTRL_PC31DOWNTO2_intermed_2;
R_A_CTRL_PC31DOWNTO2_intermed_4 <= R_A_CTRL_PC31DOWNTO2_intermed_3;
R_A_CTRL_PC31DOWNTO2_intermed_5 <= R_A_CTRL_PC31DOWNTO2_intermed_4;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_M_CTRL_PC31DOWNTO2_shadow;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_M_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_M_CTRL_PC31DOWNTO2_shadow_intermed_2;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_4 <= V_M_CTRL_PC31DOWNTO2_shadow_intermed_3;
R_X_CTRL_PC31DOWNTO2_intermed_1 <= R.X.CTRL.PC( 31 DOWNTO 2 );
R_X_CTRL_PC31DOWNTO2_intermed_2 <= R_X_CTRL_PC31DOWNTO2_intermed_1;
XC_TRAP_ADDRESS31DOWNTO2_shadow_intermed_1 <= XC_TRAP_ADDRESS31DOWNTO2_shadow;
R_E_CTRL_PC31DOWNTO2_intermed_1 <= R.E.CTRL.PC( 31 DOWNTO 2 );
R_E_CTRL_PC31DOWNTO2_intermed_2 <= R_E_CTRL_PC31DOWNTO2_intermed_1;
R_E_CTRL_PC31DOWNTO2_intermed_3 <= R_E_CTRL_PC31DOWNTO2_intermed_2;
R_E_CTRL_PC31DOWNTO2_intermed_4 <= R_E_CTRL_PC31DOWNTO2_intermed_3;
EX_JUMP_ADDRESS31DOWNTO2_shadow_intermed_1 <= EX_JUMP_ADDRESS31DOWNTO2_shadow;
IR_ADDR31DOWNTO2_intermed_1 <= IR.ADDR( 31 DOWNTO 2 );
RIN_E_CTRL_PC31DOWNTO2_intermed_1 <= RIN.E.CTRL.PC( 31 DOWNTO 2 );
RIN_E_CTRL_PC31DOWNTO2_intermed_2 <= RIN_E_CTRL_PC31DOWNTO2_intermed_1;
RIN_E_CTRL_PC31DOWNTO2_intermed_3 <= RIN_E_CTRL_PC31DOWNTO2_intermed_2;
RIN_E_CTRL_PC31DOWNTO2_intermed_4 <= RIN_E_CTRL_PC31DOWNTO2_intermed_3;
RIN_E_CTRL_PC31DOWNTO2_intermed_5 <= RIN_E_CTRL_PC31DOWNTO2_intermed_4;
V_X_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_X_CTRL_PC31DOWNTO2_shadow;
V_X_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_X_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_X_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_X_CTRL_PC31DOWNTO2_shadow_intermed_2;
RIN_X_DATA031_intermed_1 <= RIN.X.DATA ( 0 )( 31 );
V_X_DATA031_shadow_intermed_1 <= V_X_DATA031_shadow;
V_X_DATA031_shadow_intermed_1 <= V_X_DATA031_shadow;
V_X_DATA031_shadow_intermed_2 <= V_X_DATA031_shadow_intermed_1;
RIN_X_DATA031_intermed_1 <= RIN.X.DATA( 0 )( 31 );
RIN_X_DATA031_intermed_2 <= RIN_X_DATA031_intermed_1;
RIN_E_OP231_intermed_1 <= RIN.E.OP2( 31 );
R_X_DATA031_intermed_1 <= R.X.DATA( 0 )( 31 );
V_E_OP231_shadow_intermed_1 <= V_E_OP231_shadow;
V_M_CTRL_RD7DOWNTO0_shadow_intermed_1 <= V_M_CTRL_RD7DOWNTO0_shadow;
V_M_CTRL_RD7DOWNTO0_shadow_intermed_2 <= V_M_CTRL_RD7DOWNTO0_shadow_intermed_1;
V_E_CTRL_RD7DOWNTO0_shadow_intermed_1 <= V_E_CTRL_RD7DOWNTO0_shadow;
V_E_CTRL_RD7DOWNTO0_shadow_intermed_2 <= V_E_CTRL_RD7DOWNTO0_shadow_intermed_1;
V_E_CTRL_RD7DOWNTO0_shadow_intermed_3 <= V_E_CTRL_RD7DOWNTO0_shadow_intermed_2;
R_E_CTRL_RD7DOWNTO0_intermed_1 <= R.E.CTRL.RD ( 7 DOWNTO 0 );
R_E_CTRL_RD7DOWNTO0_intermed_2 <= R_E_CTRL_RD7DOWNTO0_intermed_1;
V_A_CTRL_RD7DOWNTO0_shadow_intermed_1 <= V_A_CTRL_RD7DOWNTO0_shadow;
V_A_CTRL_RD7DOWNTO0_shadow_intermed_2 <= V_A_CTRL_RD7DOWNTO0_shadow_intermed_1;
V_A_CTRL_RD7DOWNTO0_shadow_intermed_3 <= V_A_CTRL_RD7DOWNTO0_shadow_intermed_2;
V_A_CTRL_RD7DOWNTO0_shadow_intermed_4 <= V_A_CTRL_RD7DOWNTO0_shadow_intermed_3;
RIN_A_CTRL_RD7DOWNTO0_intermed_1 <= RIN.A.CTRL.RD ( 7 DOWNTO 0 );
RIN_A_CTRL_RD7DOWNTO0_intermed_2 <= RIN_A_CTRL_RD7DOWNTO0_intermed_1;
RIN_A_CTRL_RD7DOWNTO0_intermed_3 <= RIN_A_CTRL_RD7DOWNTO0_intermed_2;
RIN_A_CTRL_RD7DOWNTO0_intermed_4 <= RIN_A_CTRL_RD7DOWNTO0_intermed_3;
R_M_CTRL_RD7DOWNTO0_intermed_1 <= R.M.CTRL.RD ( 7 DOWNTO 0 );
R_A_CTRL_RD7DOWNTO0_intermed_1 <= R.A.CTRL.RD ( 7 DOWNTO 0 );
R_A_CTRL_RD7DOWNTO0_intermed_2 <= R_A_CTRL_RD7DOWNTO0_intermed_1;
R_A_CTRL_RD7DOWNTO0_intermed_3 <= R_A_CTRL_RD7DOWNTO0_intermed_2;
RIN_E_CTRL_RD7DOWNTO0_intermed_1 <= RIN.E.CTRL.RD ( 7 DOWNTO 0 );
RIN_E_CTRL_RD7DOWNTO0_intermed_2 <= RIN_E_CTRL_RD7DOWNTO0_intermed_1;
RIN_E_CTRL_RD7DOWNTO0_intermed_3 <= RIN_E_CTRL_RD7DOWNTO0_intermed_2;
RIN_X_CTRL_RD7DOWNTO0_intermed_1 <= RIN.X.CTRL.RD ( 7 DOWNTO 0 );
RIN_M_CTRL_RD7DOWNTO0_intermed_1 <= RIN.M.CTRL.RD ( 7 DOWNTO 0 );
RIN_M_CTRL_RD7DOWNTO0_intermed_2 <= RIN_M_CTRL_RD7DOWNTO0_intermed_1;
RIN_X_CTRL_TRAP_intermed_1 <= RIN.X.CTRL.TRAP;
V_A_CTRL_TRAP_shadow_intermed_1 <= V_A_CTRL_TRAP_shadow;
V_A_CTRL_TRAP_shadow_intermed_2 <= V_A_CTRL_TRAP_shadow_intermed_1;
V_A_CTRL_TRAP_shadow_intermed_3 <= V_A_CTRL_TRAP_shadow_intermed_2;
V_A_CTRL_TRAP_shadow_intermed_4 <= V_A_CTRL_TRAP_shadow_intermed_3;
ICO_MEXC_intermed_1 <= ICO.MEXC;
ICO_MEXC_intermed_2 <= ICO_MEXC_intermed_1;
ICO_MEXC_intermed_3 <= ICO_MEXC_intermed_2;
ICO_MEXC_intermed_4 <= ICO_MEXC_intermed_3;
ICO_MEXC_intermed_5 <= ICO_MEXC_intermed_4;
R_E_CTRL_TRAP_intermed_1 <= R.E.CTRL.TRAP;
R_E_CTRL_TRAP_intermed_2 <= R_E_CTRL_TRAP_intermed_1;
RIN_A_CTRL_TRAP_intermed_1 <= RIN.A.CTRL.TRAP;
RIN_A_CTRL_TRAP_intermed_2 <= RIN_A_CTRL_TRAP_intermed_1;
RIN_A_CTRL_TRAP_intermed_3 <= RIN_A_CTRL_TRAP_intermed_2;
RIN_A_CTRL_TRAP_intermed_4 <= RIN_A_CTRL_TRAP_intermed_3;
V_E_CTRL_TRAP_shadow_intermed_1 <= V_E_CTRL_TRAP_shadow;
V_E_CTRL_TRAP_shadow_intermed_2 <= V_E_CTRL_TRAP_shadow_intermed_1;
V_E_CTRL_TRAP_shadow_intermed_3 <= V_E_CTRL_TRAP_shadow_intermed_2;
RIN_E_CTRL_TRAP_intermed_1 <= RIN.E.CTRL.TRAP;
RIN_E_CTRL_TRAP_intermed_2 <= RIN_E_CTRL_TRAP_intermed_1;
RIN_E_CTRL_TRAP_intermed_3 <= RIN_E_CTRL_TRAP_intermed_2;
R_D_MEXC_intermed_1 <= R.D.MEXC;
R_D_MEXC_intermed_2 <= R_D_MEXC_intermed_1;
R_D_MEXC_intermed_3 <= R_D_MEXC_intermed_2;
R_D_MEXC_intermed_4 <= R_D_MEXC_intermed_3;
V_M_CTRL_TRAP_shadow_intermed_1 <= V_M_CTRL_TRAP_shadow;
V_M_CTRL_TRAP_shadow_intermed_2 <= V_M_CTRL_TRAP_shadow_intermed_1;
V_D_MEXC_shadow_intermed_1 <= V_D_MEXC_shadow;
V_D_MEXC_shadow_intermed_2 <= V_D_MEXC_shadow_intermed_1;
V_D_MEXC_shadow_intermed_3 <= V_D_MEXC_shadow_intermed_2;
V_D_MEXC_shadow_intermed_4 <= V_D_MEXC_shadow_intermed_3;
V_D_MEXC_shadow_intermed_5 <= V_D_MEXC_shadow_intermed_4;
R_A_CTRL_TRAP_intermed_1 <= R.A.CTRL.TRAP;
R_A_CTRL_TRAP_intermed_2 <= R_A_CTRL_TRAP_intermed_1;
R_A_CTRL_TRAP_intermed_3 <= R_A_CTRL_TRAP_intermed_2;
RIN_M_CTRL_TRAP_intermed_1 <= RIN.M.CTRL.TRAP;
RIN_M_CTRL_TRAP_intermed_2 <= RIN_M_CTRL_TRAP_intermed_1;
R_M_CTRL_TRAP_intermed_1 <= R.M.CTRL.TRAP;
RIN_D_MEXC_intermed_1 <= RIN.D.MEXC;
RIN_D_MEXC_intermed_2 <= RIN_D_MEXC_intermed_1;
RIN_D_MEXC_intermed_3 <= RIN_D_MEXC_intermed_2;
RIN_D_MEXC_intermed_4 <= RIN_D_MEXC_intermed_3;
RIN_D_MEXC_intermed_5 <= RIN_D_MEXC_intermed_4;
RIN_X_RESULT6DOWNTO0_intermed_1 <= RIN.X.RESULT ( 6 DOWNTO 0 );
V_X_RESULT6DOWNTO0_shadow_intermed_1 <= V_X_RESULT6DOWNTO0_shadow;
V_X_RESULT6DOWNTO0_shadow_intermed_2 <= V_X_RESULT6DOWNTO0_shadow_intermed_1;
RIN_X_RESULT6DOWNTO0_intermed_1 <= RIN.X.RESULT( 6 DOWNTO 0 );
RIN_X_RESULT6DOWNTO0_intermed_2 <= RIN_X_RESULT6DOWNTO0_intermed_1;
R_X_RESULT6DOWNTO0_intermed_1 <= R.X.RESULT( 6 DOWNTO 0 );
RIN_D_PC_intermed_1 <= RIN.D.PC;
RIN_D_PC_intermed_2 <= RIN_D_PC_intermed_1;
RIN_D_PC_intermed_3 <= RIN_D_PC_intermed_2;
RIN_D_PC_intermed_4 <= RIN_D_PC_intermed_3;
RIN_D_PC_intermed_5 <= RIN_D_PC_intermed_4;
RIN_A_CTRL_PC_intermed_1 <= RIN.A.CTRL.PC;
RIN_A_CTRL_PC_intermed_2 <= RIN_A_CTRL_PC_intermed_1;
RIN_A_CTRL_PC_intermed_3 <= RIN_A_CTRL_PC_intermed_2;
RIN_A_CTRL_PC_intermed_4 <= RIN_A_CTRL_PC_intermed_3;
R_A_CTRL_PC_intermed_1 <= R.A.CTRL.PC;
R_A_CTRL_PC_intermed_2 <= R_A_CTRL_PC_intermed_1;
R_A_CTRL_PC_intermed_3 <= R_A_CTRL_PC_intermed_2;
V_E_CTRL_PC_shadow_intermed_1 <= V_E_CTRL_PC_shadow;
V_E_CTRL_PC_shadow_intermed_2 <= V_E_CTRL_PC_shadow_intermed_1;
V_E_CTRL_PC_shadow_intermed_3 <= V_E_CTRL_PC_shadow_intermed_2;
R_M_CTRL_PC_intermed_1 <= R.M.CTRL.PC;
R_E_CTRL_PC_intermed_1 <= R.E.CTRL.PC;
R_E_CTRL_PC_intermed_2 <= R_E_CTRL_PC_intermed_1;
RIN_M_CTRL_PC_intermed_1 <= RIN.M.CTRL.PC;
RIN_M_CTRL_PC_intermed_2 <= RIN_M_CTRL_PC_intermed_1;
V_M_CTRL_PC_shadow_intermed_1 <= V_M_CTRL_PC_shadow;
V_M_CTRL_PC_shadow_intermed_2 <= V_M_CTRL_PC_shadow_intermed_1;
V_A_CTRL_PC_shadow_intermed_1 <= V_A_CTRL_PC_shadow;
V_A_CTRL_PC_shadow_intermed_2 <= V_A_CTRL_PC_shadow_intermed_1;
V_A_CTRL_PC_shadow_intermed_3 <= V_A_CTRL_PC_shadow_intermed_2;
V_A_CTRL_PC_shadow_intermed_4 <= V_A_CTRL_PC_shadow_intermed_3;
R_D_PC_intermed_1 <= R.D.PC;
R_D_PC_intermed_2 <= R_D_PC_intermed_1;
R_D_PC_intermed_3 <= R_D_PC_intermed_2;
R_D_PC_intermed_4 <= R_D_PC_intermed_3;
RIN_E_CTRL_PC_intermed_1 <= RIN.E.CTRL.PC;
RIN_E_CTRL_PC_intermed_2 <= RIN_E_CTRL_PC_intermed_1;
RIN_E_CTRL_PC_intermed_3 <= RIN_E_CTRL_PC_intermed_2;
RIN_X_CTRL_PC_intermed_1 <= RIN.X.CTRL.PC;
V_D_PC_shadow_intermed_1 <= V_D_PC_shadow;
V_D_PC_shadow_intermed_2 <= V_D_PC_shadow_intermed_1;
V_D_PC_shadow_intermed_3 <= V_D_PC_shadow_intermed_2;
V_D_PC_shadow_intermed_4 <= V_D_PC_shadow_intermed_3;
V_D_PC_shadow_intermed_5 <= V_D_PC_shadow_intermed_4;
RIN_A_CTRL_ANNUL_intermed_1 <= RIN.A.CTRL.ANNUL;
RIN_A_CTRL_ANNUL_intermed_2 <= RIN_A_CTRL_ANNUL_intermed_1;
RIN_A_CTRL_ANNUL_intermed_3 <= RIN_A_CTRL_ANNUL_intermed_2;
RIN_A_CTRL_ANNUL_intermed_4 <= RIN_A_CTRL_ANNUL_intermed_3;
RIN_A_CTRL_ANNUL_intermed_5 <= RIN_A_CTRL_ANNUL_intermed_4;
R_A_CTRL_ANNUL_intermed_1 <= R.A.CTRL.ANNUL;
R_A_CTRL_ANNUL_intermed_2 <= R_A_CTRL_ANNUL_intermed_1;
R_A_CTRL_ANNUL_intermed_3 <= R_A_CTRL_ANNUL_intermed_2;
R_A_CTRL_ANNUL_intermed_4 <= R_A_CTRL_ANNUL_intermed_3;
R_X_ANNUL_ALL_intermed_1 <= R.X.ANNUL_ALL;
R_X_ANNUL_ALL_intermed_2 <= R_X_ANNUL_ALL_intermed_1;
R_X_ANNUL_ALL_intermed_3 <= R_X_ANNUL_ALL_intermed_2;
R_X_ANNUL_ALL_intermed_4 <= R_X_ANNUL_ALL_intermed_3;
RIN_X_CTRL_WREG_intermed_1 <= RIN.X.CTRL.WREG;
RIN_M_CTRL_WREG_intermed_1 <= RIN.M.CTRL.WREG;
RIN_M_CTRL_WREG_intermed_2 <= RIN_M_CTRL_WREG_intermed_1;
RIN_A_CTRL_WREG_intermed_1 <= RIN.A.CTRL.WREG;
RIN_A_CTRL_WREG_intermed_2 <= RIN_A_CTRL_WREG_intermed_1;
RIN_A_CTRL_WREG_intermed_3 <= RIN_A_CTRL_WREG_intermed_2;
RIN_A_CTRL_WREG_intermed_4 <= RIN_A_CTRL_WREG_intermed_3;
V_A_CTRL_WREG_shadow_intermed_1 <= V_A_CTRL_WREG_shadow;
V_A_CTRL_WREG_shadow_intermed_2 <= V_A_CTRL_WREG_shadow_intermed_1;
V_A_CTRL_WREG_shadow_intermed_3 <= V_A_CTRL_WREG_shadow_intermed_2;
V_A_CTRL_WREG_shadow_intermed_4 <= V_A_CTRL_WREG_shadow_intermed_3;
R_A_CTRL_WREG_intermed_1 <= R.A.CTRL.WREG;
R_A_CTRL_WREG_intermed_2 <= R_A_CTRL_WREG_intermed_1;
R_A_CTRL_WREG_intermed_3 <= R_A_CTRL_WREG_intermed_2;
V_X_ANNUL_ALL_shadow_intermed_1 <= V_X_ANNUL_ALL_shadow;
V_X_ANNUL_ALL_shadow_intermed_2 <= V_X_ANNUL_ALL_shadow_intermed_1;
V_X_ANNUL_ALL_shadow_intermed_3 <= V_X_ANNUL_ALL_shadow_intermed_2;
V_X_ANNUL_ALL_shadow_intermed_4 <= V_X_ANNUL_ALL_shadow_intermed_3;
R_M_CTRL_WREG_intermed_1 <= R.M.CTRL.WREG;
RIN_X_ANNUL_ALL_intermed_1 <= RIN.X.ANNUL_ALL;
RIN_X_ANNUL_ALL_intermed_2 <= RIN_X_ANNUL_ALL_intermed_1;
RIN_X_ANNUL_ALL_intermed_3 <= RIN_X_ANNUL_ALL_intermed_2;
RIN_X_ANNUL_ALL_intermed_4 <= RIN_X_ANNUL_ALL_intermed_3;
RIN_X_ANNUL_ALL_intermed_5 <= RIN_X_ANNUL_ALL_intermed_4;
V_M_CTRL_WREG_shadow_intermed_1 <= V_M_CTRL_WREG_shadow;
V_M_CTRL_WREG_shadow_intermed_2 <= V_M_CTRL_WREG_shadow_intermed_1;
R_E_CTRL_WREG_intermed_1 <= R.E.CTRL.WREG;
R_E_CTRL_WREG_intermed_2 <= R_E_CTRL_WREG_intermed_1;
V_A_CTRL_ANNUL_shadow_intermed_1 <= V_A_CTRL_ANNUL_shadow;
V_A_CTRL_ANNUL_shadow_intermed_2 <= V_A_CTRL_ANNUL_shadow_intermed_1;
V_A_CTRL_ANNUL_shadow_intermed_3 <= V_A_CTRL_ANNUL_shadow_intermed_2;
V_A_CTRL_ANNUL_shadow_intermed_4 <= V_A_CTRL_ANNUL_shadow_intermed_3;
RIN_E_CTRL_WREG_intermed_1 <= RIN.E.CTRL.WREG;
RIN_E_CTRL_WREG_intermed_2 <= RIN_E_CTRL_WREG_intermed_1;
RIN_E_CTRL_WREG_intermed_3 <= RIN_E_CTRL_WREG_intermed_2;
V_E_CTRL_WREG_shadow_intermed_1 <= V_E_CTRL_WREG_shadow;
V_E_CTRL_WREG_shadow_intermed_2 <= V_E_CTRL_WREG_shadow_intermed_1;
V_E_CTRL_WREG_shadow_intermed_3 <= V_E_CTRL_WREG_shadow_intermed_2;
RIN_M_CTRL_PC31DOWNTO2_intermed_1 <= RIN.M.CTRL.PC( 31 DOWNTO 2 );
RIN_M_CTRL_PC31DOWNTO2_intermed_2 <= RIN_M_CTRL_PC31DOWNTO2_intermed_1;
RIN_M_CTRL_PC31DOWNTO2_intermed_3 <= RIN_M_CTRL_PC31DOWNTO2_intermed_2;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_M_CTRL_PC31DOWNTO2_shadow;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_M_CTRL_PC31DOWNTO2_shadow_intermed_1;
R_E_CTRL_PC31DOWNTO2_intermed_1 <= R.E.CTRL.PC ( 31 DOWNTO 2 );
R_E_CTRL_PC31DOWNTO2_intermed_2 <= R_E_CTRL_PC31DOWNTO2_intermed_1;
V_D_PC31DOWNTO2_shadow_intermed_1 <= V_D_PC31DOWNTO2_shadow;
V_D_PC31DOWNTO2_shadow_intermed_2 <= V_D_PC31DOWNTO2_shadow_intermed_1;
V_D_PC31DOWNTO2_shadow_intermed_3 <= V_D_PC31DOWNTO2_shadow_intermed_2;
V_D_PC31DOWNTO2_shadow_intermed_4 <= V_D_PC31DOWNTO2_shadow_intermed_3;
V_D_PC31DOWNTO2_shadow_intermed_5 <= V_D_PC31DOWNTO2_shadow_intermed_4;
RIN_D_PC31DOWNTO2_intermed_1 <= RIN.D.PC( 31 DOWNTO 2 );
RIN_D_PC31DOWNTO2_intermed_2 <= RIN_D_PC31DOWNTO2_intermed_1;
RIN_D_PC31DOWNTO2_intermed_3 <= RIN_D_PC31DOWNTO2_intermed_2;
RIN_D_PC31DOWNTO2_intermed_4 <= RIN_D_PC31DOWNTO2_intermed_3;
RIN_D_PC31DOWNTO2_intermed_5 <= RIN_D_PC31DOWNTO2_intermed_4;
RIN_E_CTRL_PC31DOWNTO2_intermed_1 <= RIN.E.CTRL.PC ( 31 DOWNTO 2 );
RIN_E_CTRL_PC31DOWNTO2_intermed_2 <= RIN_E_CTRL_PC31DOWNTO2_intermed_1;
RIN_E_CTRL_PC31DOWNTO2_intermed_3 <= RIN_E_CTRL_PC31DOWNTO2_intermed_2;
RIN_A_CTRL_PC31DOWNTO2_intermed_1 <= RIN.A.CTRL.PC ( 31 DOWNTO 2 );
RIN_A_CTRL_PC31DOWNTO2_intermed_2 <= RIN_A_CTRL_PC31DOWNTO2_intermed_1;
RIN_A_CTRL_PC31DOWNTO2_intermed_3 <= RIN_A_CTRL_PC31DOWNTO2_intermed_2;
RIN_A_CTRL_PC31DOWNTO2_intermed_4 <= RIN_A_CTRL_PC31DOWNTO2_intermed_3;
RIN_X_CTRL_PC31DOWNTO2_intermed_1 <= RIN.X.CTRL.PC ( 31 DOWNTO 2 );
RIN_X_CTRL_PC31DOWNTO2_intermed_1 <= RIN.X.CTRL.PC( 31 DOWNTO 2 );
RIN_X_CTRL_PC31DOWNTO2_intermed_2 <= RIN_X_CTRL_PC31DOWNTO2_intermed_1;
RIN_M_CTRL_PC31DOWNTO2_intermed_1 <= RIN.M.CTRL.PC ( 31 DOWNTO 2 );
RIN_M_CTRL_PC31DOWNTO2_intermed_2 <= RIN_M_CTRL_PC31DOWNTO2_intermed_1;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO2_shadow;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_2;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_4 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_3;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_5 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_4;
R_D_PC31DOWNTO2_intermed_1 <= R.D.PC( 31 DOWNTO 2 );
R_D_PC31DOWNTO2_intermed_2 <= R_D_PC31DOWNTO2_intermed_1;
R_D_PC31DOWNTO2_intermed_3 <= R_D_PC31DOWNTO2_intermed_2;
R_D_PC31DOWNTO2_intermed_4 <= R_D_PC31DOWNTO2_intermed_3;
R_M_CTRL_PC31DOWNTO2_intermed_1 <= R.M.CTRL.PC ( 31 DOWNTO 2 );
R_M_CTRL_PC31DOWNTO2_intermed_1 <= R.M.CTRL.PC( 31 DOWNTO 2 );
R_M_CTRL_PC31DOWNTO2_intermed_2 <= R_M_CTRL_PC31DOWNTO2_intermed_1;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_E_CTRL_PC31DOWNTO2_shadow;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_2;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_4 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_3;
RIN_A_CTRL_PC31DOWNTO2_intermed_1 <= RIN.A.CTRL.PC( 31 DOWNTO 2 );
RIN_A_CTRL_PC31DOWNTO2_intermed_2 <= RIN_A_CTRL_PC31DOWNTO2_intermed_1;
RIN_A_CTRL_PC31DOWNTO2_intermed_3 <= RIN_A_CTRL_PC31DOWNTO2_intermed_2;
RIN_A_CTRL_PC31DOWNTO2_intermed_4 <= RIN_A_CTRL_PC31DOWNTO2_intermed_3;
RIN_A_CTRL_PC31DOWNTO2_intermed_5 <= RIN_A_CTRL_PC31DOWNTO2_intermed_4;
R_A_CTRL_PC31DOWNTO2_intermed_1 <= R.A.CTRL.PC( 31 DOWNTO 2 );
R_A_CTRL_PC31DOWNTO2_intermed_2 <= R_A_CTRL_PC31DOWNTO2_intermed_1;
R_A_CTRL_PC31DOWNTO2_intermed_3 <= R_A_CTRL_PC31DOWNTO2_intermed_2;
R_A_CTRL_PC31DOWNTO2_intermed_4 <= R_A_CTRL_PC31DOWNTO2_intermed_3;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_M_CTRL_PC31DOWNTO2_shadow;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_M_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_M_CTRL_PC31DOWNTO2_shadow_intermed_2;
R_A_CTRL_PC31DOWNTO2_intermed_1 <= R.A.CTRL.PC ( 31 DOWNTO 2 );
R_A_CTRL_PC31DOWNTO2_intermed_2 <= R_A_CTRL_PC31DOWNTO2_intermed_1;
R_A_CTRL_PC31DOWNTO2_intermed_3 <= R_A_CTRL_PC31DOWNTO2_intermed_2;
R_X_CTRL_PC31DOWNTO2_intermed_1 <= R.X.CTRL.PC( 31 DOWNTO 2 );
V_A_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO2_shadow;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_2;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_4 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_3;
R_E_CTRL_PC31DOWNTO2_intermed_1 <= R.E.CTRL.PC( 31 DOWNTO 2 );
R_E_CTRL_PC31DOWNTO2_intermed_2 <= R_E_CTRL_PC31DOWNTO2_intermed_1;
R_E_CTRL_PC31DOWNTO2_intermed_3 <= R_E_CTRL_PC31DOWNTO2_intermed_2;
RIN_E_CTRL_PC31DOWNTO2_intermed_1 <= RIN.E.CTRL.PC( 31 DOWNTO 2 );
RIN_E_CTRL_PC31DOWNTO2_intermed_2 <= RIN_E_CTRL_PC31DOWNTO2_intermed_1;
RIN_E_CTRL_PC31DOWNTO2_intermed_3 <= RIN_E_CTRL_PC31DOWNTO2_intermed_2;
RIN_E_CTRL_PC31DOWNTO2_intermed_4 <= RIN_E_CTRL_PC31DOWNTO2_intermed_3;
V_X_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_X_CTRL_PC31DOWNTO2_shadow;
V_X_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_X_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_E_CTRL_PC31DOWNTO2_shadow;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_2;
RIN_M_CTRL_PC31DOWNTO2_intermed_1 <= RIN.M.CTRL.PC( 31 DOWNTO 2 );
RIN_M_CTRL_PC31DOWNTO2_intermed_2 <= RIN_M_CTRL_PC31DOWNTO2_intermed_1;
V_D_PC31DOWNTO2_shadow_intermed_1 <= V_D_PC31DOWNTO2_shadow;
V_D_PC31DOWNTO2_shadow_intermed_2 <= V_D_PC31DOWNTO2_shadow_intermed_1;
V_D_PC31DOWNTO2_shadow_intermed_3 <= V_D_PC31DOWNTO2_shadow_intermed_2;
V_D_PC31DOWNTO2_shadow_intermed_4 <= V_D_PC31DOWNTO2_shadow_intermed_3;
V_D_PC31DOWNTO2_shadow_intermed_5 <= V_D_PC31DOWNTO2_shadow_intermed_4;
RIN_D_PC31DOWNTO2_intermed_1 <= RIN.D.PC( 31 DOWNTO 2 );
RIN_D_PC31DOWNTO2_intermed_2 <= RIN_D_PC31DOWNTO2_intermed_1;
RIN_D_PC31DOWNTO2_intermed_3 <= RIN_D_PC31DOWNTO2_intermed_2;
RIN_D_PC31DOWNTO2_intermed_4 <= RIN_D_PC31DOWNTO2_intermed_3;
RIN_D_PC31DOWNTO2_intermed_5 <= RIN_D_PC31DOWNTO2_intermed_4;
RIN_X_CTRL_PC31DOWNTO2_intermed_1 <= RIN.X.CTRL.PC( 31 DOWNTO 2 );
V_A_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO2_shadow;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_2;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_4 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_3;
R_D_PC31DOWNTO2_intermed_1 <= R.D.PC( 31 DOWNTO 2 );
R_D_PC31DOWNTO2_intermed_2 <= R_D_PC31DOWNTO2_intermed_1;
R_D_PC31DOWNTO2_intermed_3 <= R_D_PC31DOWNTO2_intermed_2;
R_D_PC31DOWNTO2_intermed_4 <= R_D_PC31DOWNTO2_intermed_3;
R_M_CTRL_PC31DOWNTO2_intermed_1 <= R.M.CTRL.PC( 31 DOWNTO 2 );
V_E_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_E_CTRL_PC31DOWNTO2_shadow;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_2;
RIN_A_CTRL_PC31DOWNTO2_intermed_1 <= RIN.A.CTRL.PC( 31 DOWNTO 2 );
RIN_A_CTRL_PC31DOWNTO2_intermed_2 <= RIN_A_CTRL_PC31DOWNTO2_intermed_1;
RIN_A_CTRL_PC31DOWNTO2_intermed_3 <= RIN_A_CTRL_PC31DOWNTO2_intermed_2;
RIN_A_CTRL_PC31DOWNTO2_intermed_4 <= RIN_A_CTRL_PC31DOWNTO2_intermed_3;
R_A_CTRL_PC31DOWNTO2_intermed_1 <= R.A.CTRL.PC( 31 DOWNTO 2 );
R_A_CTRL_PC31DOWNTO2_intermed_2 <= R_A_CTRL_PC31DOWNTO2_intermed_1;
R_A_CTRL_PC31DOWNTO2_intermed_3 <= R_A_CTRL_PC31DOWNTO2_intermed_2;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_M_CTRL_PC31DOWNTO2_shadow;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_M_CTRL_PC31DOWNTO2_shadow_intermed_1;
R_E_CTRL_PC31DOWNTO2_intermed_1 <= R.E.CTRL.PC( 31 DOWNTO 2 );
R_E_CTRL_PC31DOWNTO2_intermed_2 <= R_E_CTRL_PC31DOWNTO2_intermed_1;
RIN_E_CTRL_PC31DOWNTO2_intermed_1 <= RIN.E.CTRL.PC( 31 DOWNTO 2 );
RIN_E_CTRL_PC31DOWNTO2_intermed_2 <= RIN_E_CTRL_PC31DOWNTO2_intermed_1;
RIN_E_CTRL_PC31DOWNTO2_intermed_3 <= RIN_E_CTRL_PC31DOWNTO2_intermed_2;
V_X_CTRL_TT3DOWNTO0_shadow_intermed_1 <= V_X_CTRL_TT3DOWNTO0_shadow;
V_X_CTRL_TT3DOWNTO0_shadow_intermed_2 <= V_X_CTRL_TT3DOWNTO0_shadow_intermed_1;
R_M_CTRL_TT3DOWNTO0_intermed_1 <= R.M.CTRL.TT( 3 DOWNTO 0 );
R_M_CTRL_TT3DOWNTO0_intermed_2 <= R_M_CTRL_TT3DOWNTO0_intermed_1;
V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_1 <= V_X_RESULT6DOWNTO03DOWNTO0_shadow;
V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_2 <= V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_1;
V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_3 <= V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_2;
R_X_RESULT6DOWNTO03DOWNTO0_intermed_1 <= R.X.RESULT( 6 DOWNTO 0 )( 3 DOWNTO 0 );
R_X_RESULT6DOWNTO03DOWNTO0_intermed_2 <= R_X_RESULT6DOWNTO03DOWNTO0_intermed_1;
R_A_CTRL_TT3DOWNTO0_intermed_1 <= R.A.CTRL.TT( 3 DOWNTO 0 );
R_A_CTRL_TT3DOWNTO0_intermed_2 <= R_A_CTRL_TT3DOWNTO0_intermed_1;
R_A_CTRL_TT3DOWNTO0_intermed_3 <= R_A_CTRL_TT3DOWNTO0_intermed_2;
R_A_CTRL_TT3DOWNTO0_intermed_4 <= R_A_CTRL_TT3DOWNTO0_intermed_3;
RIN_A_CTRL_TT3DOWNTO0_intermed_1 <= RIN.A.CTRL.TT( 3 DOWNTO 0 );
RIN_A_CTRL_TT3DOWNTO0_intermed_2 <= RIN_A_CTRL_TT3DOWNTO0_intermed_1;
RIN_A_CTRL_TT3DOWNTO0_intermed_3 <= RIN_A_CTRL_TT3DOWNTO0_intermed_2;
RIN_A_CTRL_TT3DOWNTO0_intermed_4 <= RIN_A_CTRL_TT3DOWNTO0_intermed_3;
RIN_A_CTRL_TT3DOWNTO0_intermed_5 <= RIN_A_CTRL_TT3DOWNTO0_intermed_4;
V_A_CTRL_TT3DOWNTO0_shadow_intermed_1 <= V_A_CTRL_TT3DOWNTO0_shadow;
V_A_CTRL_TT3DOWNTO0_shadow_intermed_2 <= V_A_CTRL_TT3DOWNTO0_shadow_intermed_1;
V_A_CTRL_TT3DOWNTO0_shadow_intermed_3 <= V_A_CTRL_TT3DOWNTO0_shadow_intermed_2;
V_A_CTRL_TT3DOWNTO0_shadow_intermed_4 <= V_A_CTRL_TT3DOWNTO0_shadow_intermed_3;
V_A_CTRL_TT3DOWNTO0_shadow_intermed_5 <= V_A_CTRL_TT3DOWNTO0_shadow_intermed_4;
RIN_W_S_TT3DOWNTO0_intermed_1 <= RIN.W.S.TT( 3 DOWNTO 0 );
RIN_W_S_TT3DOWNTO0_intermed_2 <= RIN_W_S_TT3DOWNTO0_intermed_1;
R_E_CTRL_TT3DOWNTO0_intermed_1 <= R.E.CTRL.TT( 3 DOWNTO 0 );
R_E_CTRL_TT3DOWNTO0_intermed_2 <= R_E_CTRL_TT3DOWNTO0_intermed_1;
R_E_CTRL_TT3DOWNTO0_intermed_3 <= R_E_CTRL_TT3DOWNTO0_intermed_2;
RIN_W_S_TT3DOWNTO0_intermed_1 <= RIN.W.S.TT ( 3 DOWNTO 0 );
RIN_M_CTRL_TT3DOWNTO0_intermed_1 <= RIN.M.CTRL.TT( 3 DOWNTO 0 );
RIN_M_CTRL_TT3DOWNTO0_intermed_2 <= RIN_M_CTRL_TT3DOWNTO0_intermed_1;
RIN_M_CTRL_TT3DOWNTO0_intermed_3 <= RIN_M_CTRL_TT3DOWNTO0_intermed_2;
V_M_CTRL_TT3DOWNTO0_shadow_intermed_1 <= V_M_CTRL_TT3DOWNTO0_shadow;
V_M_CTRL_TT3DOWNTO0_shadow_intermed_2 <= V_M_CTRL_TT3DOWNTO0_shadow_intermed_1;
V_M_CTRL_TT3DOWNTO0_shadow_intermed_3 <= V_M_CTRL_TT3DOWNTO0_shadow_intermed_2;
RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_1 <= RIN.X.RESULT( 6 DOWNTO 0 )( 3 DOWNTO 0 );
RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_2 <= RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_1;
RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_3 <= RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_2;
RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_1 <= RIN.X.RESULT ( 6 DOWNTO 0 )( 3 DOWNTO 0 );
RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_2 <= RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_1;
R_W_S_TT3DOWNTO0_intermed_1 <= R.W.S.TT( 3 DOWNTO 0 );
R_X_RESULT6DOWNTO03DOWNTO0_intermed_1 <= R.X.RESULT ( 6 DOWNTO 0 )( 3 DOWNTO 0 );
V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_1 <= V_X_RESULT6DOWNTO03DOWNTO0_shadow;
V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_2 <= V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_1;
V_E_CTRL_TT3DOWNTO0_shadow_intermed_1 <= V_E_CTRL_TT3DOWNTO0_shadow;
V_E_CTRL_TT3DOWNTO0_shadow_intermed_2 <= V_E_CTRL_TT3DOWNTO0_shadow_intermed_1;
V_E_CTRL_TT3DOWNTO0_shadow_intermed_3 <= V_E_CTRL_TT3DOWNTO0_shadow_intermed_2;
V_E_CTRL_TT3DOWNTO0_shadow_intermed_4 <= V_E_CTRL_TT3DOWNTO0_shadow_intermed_3;
RIN_X_CTRL_TT3DOWNTO0_intermed_1 <= RIN.X.CTRL.TT( 3 DOWNTO 0 );
RIN_X_CTRL_TT3DOWNTO0_intermed_2 <= RIN_X_CTRL_TT3DOWNTO0_intermed_1;
V_W_S_TT3DOWNTO0_shadow_intermed_1 <= V_W_S_TT3DOWNTO0_shadow;
V_W_S_TT3DOWNTO0_shadow_intermed_2 <= V_W_S_TT3DOWNTO0_shadow_intermed_1;
R_X_CTRL_TT3DOWNTO0_intermed_1 <= R.X.CTRL.TT( 3 DOWNTO 0 );
RIN_E_CTRL_TT3DOWNTO0_intermed_1 <= RIN.E.CTRL.TT( 3 DOWNTO 0 );
RIN_E_CTRL_TT3DOWNTO0_intermed_2 <= RIN_E_CTRL_TT3DOWNTO0_intermed_1;
RIN_E_CTRL_TT3DOWNTO0_intermed_3 <= RIN_E_CTRL_TT3DOWNTO0_intermed_2;
RIN_E_CTRL_TT3DOWNTO0_intermed_4 <= RIN_E_CTRL_TT3DOWNTO0_intermed_3;
XC_VECTT3DOWNTO0_shadow_intermed_1 <= XC_VECTT3DOWNTO0_shadow;
V_M_RESULT1DOWNTO0_shadow_intermed_1 <= V_M_RESULT1DOWNTO0_shadow;
V_M_RESULT1DOWNTO0_shadow_intermed_2 <= V_M_RESULT1DOWNTO0_shadow_intermed_1;
RIN_M_RESULT1DOWNTO0_intermed_1 <= RIN.M.RESULT( 1 DOWNTO 0 );
RIN_M_RESULT1DOWNTO0_intermed_2 <= RIN_M_RESULT1DOWNTO0_intermed_1;
R_M_RESULT1DOWNTO0_intermed_1 <= R.M.RESULT( 1 DOWNTO 0 );
RIN_M_RESULT1DOWNTO0_intermed_1 <= RIN.M.RESULT ( 1 DOWNTO 0 );
RIN_X_DATA031_intermed_1 <= RIN.X.DATA ( 0 )( 31 );
RIN_X_DATA031_intermed_2 <= RIN_X_DATA031_intermed_1;
V_X_DATA031_shadow_intermed_1 <= V_X_DATA031_shadow;
V_X_DATA031_shadow_intermed_2 <= V_X_DATA031_shadow_intermed_1;
V_X_DATA031_shadow_intermed_1 <= V_X_DATA031_shadow;
V_X_DATA031_shadow_intermed_2 <= V_X_DATA031_shadow_intermed_1;
V_X_DATA031_shadow_intermed_3 <= V_X_DATA031_shadow_intermed_2;
RIN_X_DATA031_intermed_1 <= RIN.X.DATA( 0 )( 31 );
RIN_X_DATA031_intermed_2 <= RIN_X_DATA031_intermed_1;
RIN_X_DATA031_intermed_3 <= RIN_X_DATA031_intermed_2;
RIN_X_DATA031_intermed_1 <= RIN.X.DATA ( 0 ) ( 31 );
R_X_DATA031_intermed_1 <= R.X.DATA( 0 )( 31 );
R_X_DATA031_intermed_2 <= R_X_DATA031_intermed_1;
R_X_DATA031_intermed_1 <= R.X.DATA ( 0 )( 31 );
RIN_X_DATA031_intermed_1 <= RIN.X.DATA ( 0 )( 31 );
V_X_DATA031_shadow_intermed_1 <= V_X_DATA031_shadow;
V_X_DATA031_shadow_intermed_2 <= V_X_DATA031_shadow_intermed_1;
RIN_X_DATA031_intermed_1 <= RIN.X.DATA( 0 )( 31 );
RIN_X_DATA031_intermed_2 <= RIN_X_DATA031_intermed_1;
R_X_DATA031_intermed_1 <= R.X.DATA( 0 )( 31 );
V_A_CTRL_INST19_shadow_intermed_1 <= V_A_CTRL_INST19_shadow;
V_A_CTRL_INST19_shadow_intermed_2 <= V_A_CTRL_INST19_shadow_intermed_1;
V_A_CTRL_INST19_shadow_intermed_3 <= V_A_CTRL_INST19_shadow_intermed_2;
R_D_INST019_intermed_1 <= R.D.INST( 0 )( 19 );
R_D_INST019_intermed_2 <= R_D_INST019_intermed_1;
R_D_INST019_intermed_3 <= R_D_INST019_intermed_2;
V_E_CTRL_INST19_shadow_intermed_1 <= V_E_CTRL_INST19_shadow;
V_E_CTRL_INST19_shadow_intermed_2 <= V_E_CTRL_INST19_shadow_intermed_1;
RIN_A_CTRL_INST19_intermed_1 <= RIN.A.CTRL.INST ( 19 );
RIN_A_CTRL_INST19_intermed_2 <= RIN_A_CTRL_INST19_intermed_1;
V_D_INST019_shadow_intermed_1 <= V_D_INST019_shadow;
V_D_INST019_shadow_intermed_2 <= V_D_INST019_shadow_intermed_1;
V_D_INST019_shadow_intermed_3 <= V_D_INST019_shadow_intermed_2;
V_D_INST019_shadow_intermed_4 <= V_D_INST019_shadow_intermed_3;
RIN_A_CTRL_INST19_intermed_1 <= RIN.A.CTRL.INST( 19 );
RIN_A_CTRL_INST19_intermed_2 <= RIN_A_CTRL_INST19_intermed_1;
RIN_A_CTRL_INST19_intermed_3 <= RIN_A_CTRL_INST19_intermed_2;
RIN_E_CTRL_INST19_intermed_1 <= RIN.E.CTRL.INST ( 19 );
RIN_E_CTRL_INST19_intermed_1 <= RIN.E.CTRL.INST( 19 );
RIN_E_CTRL_INST19_intermed_2 <= RIN_E_CTRL_INST19_intermed_1;
DE_INST19_shadow_intermed_1 <= DE_INST19_shadow;
DE_INST19_shadow_intermed_2 <= DE_INST19_shadow_intermed_1;
R_D_INST019_intermed_1 <= R.D.INST ( 0 )( 19 );
R_D_INST019_intermed_2 <= R_D_INST019_intermed_1;
RIN_D_INST019_intermed_1 <= RIN.D.INST ( 0 )( 19 );
RIN_D_INST019_intermed_2 <= RIN_D_INST019_intermed_1;
RIN_D_INST019_intermed_3 <= RIN_D_INST019_intermed_2;
V_D_INST019_shadow_intermed_1 <= V_D_INST019_shadow;
V_D_INST019_shadow_intermed_2 <= V_D_INST019_shadow_intermed_1;
V_D_INST019_shadow_intermed_3 <= V_D_INST019_shadow_intermed_2;
R_E_CTRL_INST19_intermed_1 <= R.E.CTRL.INST( 19 );
R_A_CTRL_INST19_intermed_1 <= R.A.CTRL.INST( 19 );
R_A_CTRL_INST19_intermed_2 <= R_A_CTRL_INST19_intermed_1;
RIN_D_INST019_intermed_1 <= RIN.D.INST( 0 )( 19 );
RIN_D_INST019_intermed_2 <= RIN_D_INST019_intermed_1;
RIN_D_INST019_intermed_3 <= RIN_D_INST019_intermed_2;
RIN_D_INST019_intermed_4 <= RIN_D_INST019_intermed_3;
R_A_CTRL_INST19_intermed_1 <= R.A.CTRL.INST ( 19 );
V_A_CTRL_INST19_shadow_intermed_1 <= V_A_CTRL_INST19_shadow;
V_A_CTRL_INST19_shadow_intermed_2 <= V_A_CTRL_INST19_shadow_intermed_1;
R_D_INST020_intermed_1 <= R.D.INST ( 0 )( 20 );
R_D_INST020_intermed_2 <= R_D_INST020_intermed_1;
RIN_D_INST020_intermed_1 <= RIN.D.INST( 0 )( 20 );
RIN_D_INST020_intermed_2 <= RIN_D_INST020_intermed_1;
RIN_D_INST020_intermed_3 <= RIN_D_INST020_intermed_2;
RIN_D_INST020_intermed_4 <= RIN_D_INST020_intermed_3;
RIN_A_CTRL_INST20_intermed_1 <= RIN.A.CTRL.INST ( 20 );
RIN_A_CTRL_INST20_intermed_2 <= RIN_A_CTRL_INST20_intermed_1;
RIN_D_INST020_intermed_1 <= RIN.D.INST ( 0 )( 20 );
RIN_D_INST020_intermed_2 <= RIN_D_INST020_intermed_1;
RIN_D_INST020_intermed_3 <= RIN_D_INST020_intermed_2;
R_A_CTRL_INST20_intermed_1 <= R.A.CTRL.INST ( 20 );
RIN_A_CTRL_INST20_intermed_1 <= RIN.A.CTRL.INST( 20 );
RIN_A_CTRL_INST20_intermed_2 <= RIN_A_CTRL_INST20_intermed_1;
RIN_A_CTRL_INST20_intermed_3 <= RIN_A_CTRL_INST20_intermed_2;
V_E_CTRL_INST20_shadow_intermed_1 <= V_E_CTRL_INST20_shadow;
V_E_CTRL_INST20_shadow_intermed_2 <= V_E_CTRL_INST20_shadow_intermed_1;
V_A_CTRL_INST20_shadow_intermed_1 <= V_A_CTRL_INST20_shadow;
V_A_CTRL_INST20_shadow_intermed_2 <= V_A_CTRL_INST20_shadow_intermed_1;
V_A_CTRL_INST20_shadow_intermed_3 <= V_A_CTRL_INST20_shadow_intermed_2;
RIN_E_CTRL_INST20_intermed_1 <= RIN.E.CTRL.INST( 20 );
RIN_E_CTRL_INST20_intermed_2 <= RIN_E_CTRL_INST20_intermed_1;
V_A_CTRL_INST20_shadow_intermed_1 <= V_A_CTRL_INST20_shadow;
V_A_CTRL_INST20_shadow_intermed_2 <= V_A_CTRL_INST20_shadow_intermed_1;
V_D_INST020_shadow_intermed_1 <= V_D_INST020_shadow;
V_D_INST020_shadow_intermed_2 <= V_D_INST020_shadow_intermed_1;
V_D_INST020_shadow_intermed_3 <= V_D_INST020_shadow_intermed_2;
RIN_E_CTRL_INST20_intermed_1 <= RIN.E.CTRL.INST ( 20 );
R_E_CTRL_INST20_intermed_1 <= R.E.CTRL.INST( 20 );
V_D_INST020_shadow_intermed_1 <= V_D_INST020_shadow;
V_D_INST020_shadow_intermed_2 <= V_D_INST020_shadow_intermed_1;
V_D_INST020_shadow_intermed_3 <= V_D_INST020_shadow_intermed_2;
V_D_INST020_shadow_intermed_4 <= V_D_INST020_shadow_intermed_3;
R_D_INST020_intermed_1 <= R.D.INST( 0 )( 20 );
R_D_INST020_intermed_2 <= R_D_INST020_intermed_1;
R_D_INST020_intermed_3 <= R_D_INST020_intermed_2;
DE_INST20_shadow_intermed_1 <= DE_INST20_shadow;
DE_INST20_shadow_intermed_2 <= DE_INST20_shadow_intermed_1;
R_A_CTRL_INST20_intermed_1 <= R.A.CTRL.INST( 20 );
R_A_CTRL_INST20_intermed_2 <= R_A_CTRL_INST20_intermed_1;
V_X_DATA00_shadow_intermed_1 <= V_X_DATA00_shadow;
V_X_DATA00_shadow_intermed_2 <= V_X_DATA00_shadow_intermed_1;
RIN_X_DATA00_intermed_1 <= RIN.X.DATA ( 0 ) ( 0 );
R_X_DATA00_intermed_1 <= R.X.DATA( 0 )( 0 );
R_X_DATA00_intermed_2 <= R_X_DATA00_intermed_1;
RIN_X_DATA00_intermed_1 <= RIN.X.DATA ( 0 )( 0 );
RIN_X_DATA00_intermed_2 <= RIN_X_DATA00_intermed_1;
V_X_DATA00_shadow_intermed_1 <= V_X_DATA00_shadow;
V_X_DATA00_shadow_intermed_2 <= V_X_DATA00_shadow_intermed_1;
V_X_DATA00_shadow_intermed_3 <= V_X_DATA00_shadow_intermed_2;
R_X_DATA00_intermed_1 <= R.X.DATA ( 0 )( 0 );
RIN_X_DATA00_intermed_1 <= RIN.X.DATA( 0 )( 0 );
RIN_X_DATA00_intermed_2 <= RIN_X_DATA00_intermed_1;
RIN_X_DATA00_intermed_3 <= RIN_X_DATA00_intermed_2;
R_X_DATA00_intermed_1 <= R.X.DATA( 0 )( 0 );
RIN_X_DATA00_intermed_1 <= RIN.X.DATA ( 0 )( 0 );
V_X_DATA00_shadow_intermed_1 <= V_X_DATA00_shadow;
V_X_DATA00_shadow_intermed_2 <= V_X_DATA00_shadow_intermed_1;
RIN_X_DATA00_intermed_1 <= RIN.X.DATA( 0 )( 0 );
RIN_X_DATA00_intermed_2 <= RIN_X_DATA00_intermed_1;
RIN_X_DATA04DOWNTO0_intermed_1 <= RIN.X.DATA ( 0 ) ( 4 DOWNTO 0 );
R_X_DATA04DOWNTO0_intermed_1 <= R.X.DATA( 0 )( 4 DOWNTO 0 );
R_X_DATA04DOWNTO0_intermed_2 <= R_X_DATA04DOWNTO0_intermed_1;
R_X_DATA04DOWNTO0_intermed_1 <= R.X.DATA ( 0 )( 4 DOWNTO 0 );
RIN_X_DATA04DOWNTO0_intermed_1 <= RIN.X.DATA( 0 )( 4 DOWNTO 0 );
RIN_X_DATA04DOWNTO0_intermed_2 <= RIN_X_DATA04DOWNTO0_intermed_1;
RIN_X_DATA04DOWNTO0_intermed_3 <= RIN_X_DATA04DOWNTO0_intermed_2;
V_X_DATA04DOWNTO0_shadow_intermed_1 <= V_X_DATA04DOWNTO0_shadow;
V_X_DATA04DOWNTO0_shadow_intermed_2 <= V_X_DATA04DOWNTO0_shadow_intermed_1;
V_X_DATA04DOWNTO0_shadow_intermed_1 <= V_X_DATA04DOWNTO0_shadow;
V_X_DATA04DOWNTO0_shadow_intermed_2 <= V_X_DATA04DOWNTO0_shadow_intermed_1;
V_X_DATA04DOWNTO0_shadow_intermed_3 <= V_X_DATA04DOWNTO0_shadow_intermed_2;
RIN_X_DATA04DOWNTO0_intermed_1 <= RIN.X.DATA ( 0 )( 4 DOWNTO 0 );
RIN_X_DATA04DOWNTO0_intermed_2 <= RIN_X_DATA04DOWNTO0_intermed_1;
R_X_DATA04DOWNTO0_intermed_1 <= R.X.DATA( 0 )( 4 DOWNTO 0 );
RIN_X_DATA04DOWNTO0_intermed_1 <= RIN.X.DATA( 0 )( 4 DOWNTO 0 );
RIN_X_DATA04DOWNTO0_intermed_2 <= RIN_X_DATA04DOWNTO0_intermed_1;
V_X_DATA04DOWNTO0_shadow_intermed_1 <= V_X_DATA04DOWNTO0_shadow;
V_X_DATA04DOWNTO0_shadow_intermed_2 <= V_X_DATA04DOWNTO0_shadow_intermed_1;
RIN_X_DATA04DOWNTO0_intermed_1 <= RIN.X.DATA ( 0 )( 4 DOWNTO 0 );
RIN_D_INST0_intermed_1 <= RIN.D.INST ( 0 );
R_D_INST0_intermed_1 <= R.D.INST( 0 );
V_D_INST0_shadow_intermed_1 <= V_D_INST0_shadow;
V_D_INST0_shadow_intermed_2 <= V_D_INST0_shadow_intermed_1;
RIN_D_INST0_intermed_1 <= RIN.D.INST( 0 );
RIN_D_INST0_intermed_2 <= RIN_D_INST0_intermed_1;
V_D_PC31DOWNTO2_shadow_intermed_1 <= V_D_PC31DOWNTO2_shadow;
V_D_PC31DOWNTO2_shadow_intermed_2 <= V_D_PC31DOWNTO2_shadow_intermed_1;
RIN_D_PC31DOWNTO2_intermed_1 <= RIN.D.PC( 31 DOWNTO 2 );
RIN_D_PC31DOWNTO2_intermed_2 <= RIN_D_PC31DOWNTO2_intermed_1;
R_D_PC31DOWNTO2_intermed_1 <= R.D.PC( 31 DOWNTO 2 );
RIN_D_PC31DOWNTO2_intermed_1 <= RIN.D.PC ( 31 DOWNTO 2 );
R_A_CTRL_INST24_intermed_1 <= R.A.CTRL.INST( 24 );
R_A_CTRL_INST24_intermed_2 <= R_A_CTRL_INST24_intermed_1;
RIN_D_INST024_intermed_1 <= RIN.D.INST ( 0 )( 24 );
RIN_D_INST024_intermed_2 <= RIN_D_INST024_intermed_1;
RIN_D_INST024_intermed_3 <= RIN_D_INST024_intermed_2;
V_D_INST024_shadow_intermed_1 <= V_D_INST024_shadow;
V_D_INST024_shadow_intermed_2 <= V_D_INST024_shadow_intermed_1;
V_D_INST024_shadow_intermed_3 <= V_D_INST024_shadow_intermed_2;
V_D_INST024_shadow_intermed_4 <= V_D_INST024_shadow_intermed_3;
RIN_E_CTRL_INST24_intermed_1 <= RIN.E.CTRL.INST( 24 );
RIN_E_CTRL_INST24_intermed_2 <= RIN_E_CTRL_INST24_intermed_1;
RIN_A_CTRL_INST24_intermed_1 <= RIN.A.CTRL.INST( 24 );
RIN_A_CTRL_INST24_intermed_2 <= RIN_A_CTRL_INST24_intermed_1;
RIN_A_CTRL_INST24_intermed_3 <= RIN_A_CTRL_INST24_intermed_2;
V_D_INST024_shadow_intermed_1 <= V_D_INST024_shadow;
V_D_INST024_shadow_intermed_2 <= V_D_INST024_shadow_intermed_1;
V_D_INST024_shadow_intermed_3 <= V_D_INST024_shadow_intermed_2;
R_E_CTRL_INST24_intermed_1 <= R.E.CTRL.INST( 24 );
R_A_CTRL_INST24_intermed_1 <= R.A.CTRL.INST ( 24 );
V_A_CTRL_INST24_shadow_intermed_1 <= V_A_CTRL_INST24_shadow;
V_A_CTRL_INST24_shadow_intermed_2 <= V_A_CTRL_INST24_shadow_intermed_1;
V_A_CTRL_INST24_shadow_intermed_3 <= V_A_CTRL_INST24_shadow_intermed_2;
V_E_CTRL_INST24_shadow_intermed_1 <= V_E_CTRL_INST24_shadow;
V_E_CTRL_INST24_shadow_intermed_2 <= V_E_CTRL_INST24_shadow_intermed_1;
DE_INST24_shadow_intermed_1 <= DE_INST24_shadow;
DE_INST24_shadow_intermed_2 <= DE_INST24_shadow_intermed_1;
RIN_A_CTRL_INST24_intermed_1 <= RIN.A.CTRL.INST ( 24 );
RIN_A_CTRL_INST24_intermed_2 <= RIN_A_CTRL_INST24_intermed_1;
RIN_D_INST024_intermed_1 <= RIN.D.INST( 0 )( 24 );
RIN_D_INST024_intermed_2 <= RIN_D_INST024_intermed_1;
RIN_D_INST024_intermed_3 <= RIN_D_INST024_intermed_2;
RIN_D_INST024_intermed_4 <= RIN_D_INST024_intermed_3;
V_A_CTRL_INST24_shadow_intermed_1 <= V_A_CTRL_INST24_shadow;
V_A_CTRL_INST24_shadow_intermed_2 <= V_A_CTRL_INST24_shadow_intermed_1;
R_D_INST024_intermed_1 <= R.D.INST ( 0 )( 24 );
R_D_INST024_intermed_2 <= R_D_INST024_intermed_1;
R_D_INST024_intermed_1 <= R.D.INST( 0 )( 24 );
R_D_INST024_intermed_2 <= R_D_INST024_intermed_1;
R_D_INST024_intermed_3 <= R_D_INST024_intermed_2;
RIN_E_CTRL_INST24_intermed_1 <= RIN.E.CTRL.INST ( 24 );
V_A_CTRL_INST19_shadow_intermed_1 <= V_A_CTRL_INST19_shadow;
V_A_CTRL_INST19_shadow_intermed_2 <= V_A_CTRL_INST19_shadow_intermed_1;
R_D_INST019_intermed_1 <= R.D.INST( 0 )( 19 );
R_D_INST019_intermed_2 <= R_D_INST019_intermed_1;
RIN_A_CTRL_INST19_intermed_1 <= RIN.A.CTRL.INST ( 19 );
V_D_INST019_shadow_intermed_1 <= V_D_INST019_shadow;
V_D_INST019_shadow_intermed_2 <= V_D_INST019_shadow_intermed_1;
V_D_INST019_shadow_intermed_3 <= V_D_INST019_shadow_intermed_2;
RIN_A_CTRL_INST19_intermed_1 <= RIN.A.CTRL.INST( 19 );
RIN_A_CTRL_INST19_intermed_2 <= RIN_A_CTRL_INST19_intermed_1;
DE_INST19_shadow_intermed_1 <= DE_INST19_shadow;
R_D_INST019_intermed_1 <= R.D.INST ( 0 )( 19 );
RIN_D_INST019_intermed_1 <= RIN.D.INST ( 0 )( 19 );
RIN_D_INST019_intermed_2 <= RIN_D_INST019_intermed_1;
V_D_INST019_shadow_intermed_1 <= V_D_INST019_shadow;
V_D_INST019_shadow_intermed_2 <= V_D_INST019_shadow_intermed_1;
R_A_CTRL_INST19_intermed_1 <= R.A.CTRL.INST( 19 );
RIN_D_INST019_intermed_1 <= RIN.D.INST( 0 )( 19 );
RIN_D_INST019_intermed_2 <= RIN_D_INST019_intermed_1;
RIN_D_INST019_intermed_3 <= RIN_D_INST019_intermed_2;
RIN_M_Y31_intermed_1 <= RIN.M.Y ( 31 );
V_M_Y31_shadow_intermed_1 <= V_M_Y31_shadow;
V_M_Y31_shadow_intermed_2 <= V_M_Y31_shadow_intermed_1;
RIN_M_Y31_intermed_1 <= RIN.M.Y( 31 );
RIN_M_Y31_intermed_2 <= RIN_M_Y31_intermed_1;
R_M_Y31_intermed_1 <= R.M.Y( 31 );
DSUIN_CRDY2_intermed_1 <= DSUIN.CRDY ( 2 );
VDSU_CRDY2_shadow_intermed_1 <= VDSU_CRDY2_shadow;
VDSU_CRDY2_shadow_intermed_2 <= VDSU_CRDY2_shadow_intermed_1;
DSUIN_CRDY2_intermed_1 <= DSUIN.CRDY( 2 );
DSUIN_CRDY2_intermed_2 <= DSUIN_CRDY2_intermed_1;
DSUR_CRDY2_intermed_1 <= DSUR.CRDY( 2 );
V_D_PC31DOWNTO2_shadow_intermed_1 <= V_D_PC31DOWNTO2_shadow;
V_D_PC31DOWNTO2_shadow_intermed_2 <= V_D_PC31DOWNTO2_shadow_intermed_1;
RIN_D_PC31DOWNTO2_intermed_1 <= RIN.D.PC( 31 DOWNTO 2 );
RIN_D_PC31DOWNTO2_intermed_2 <= RIN_D_PC31DOWNTO2_intermed_1;
RIN_A_CTRL_PC31DOWNTO2_intermed_1 <= RIN.A.CTRL.PC ( 31 DOWNTO 2 );
V_A_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO2_shadow;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_1;
R_D_PC31DOWNTO2_intermed_1 <= R.D.PC( 31 DOWNTO 2 );
RIN_A_CTRL_PC31DOWNTO2_intermed_1 <= RIN.A.CTRL.PC( 31 DOWNTO 2 );
RIN_A_CTRL_PC31DOWNTO2_intermed_2 <= RIN_A_CTRL_PC31DOWNTO2_intermed_1;
R_A_CTRL_PC31DOWNTO2_intermed_1 <= R.A.CTRL.PC( 31 DOWNTO 2 );
V_D_PC31DOWNTO2_shadow_intermed_1 <= V_D_PC31DOWNTO2_shadow;
V_D_PC31DOWNTO2_shadow_intermed_2 <= V_D_PC31DOWNTO2_shadow_intermed_1;
V_D_PC31DOWNTO2_shadow_intermed_3 <= V_D_PC31DOWNTO2_shadow_intermed_2;
RIN_D_PC31DOWNTO2_intermed_1 <= RIN.D.PC( 31 DOWNTO 2 );
RIN_D_PC31DOWNTO2_intermed_2 <= RIN_D_PC31DOWNTO2_intermed_1;
RIN_D_PC31DOWNTO2_intermed_3 <= RIN_D_PC31DOWNTO2_intermed_2;
RIN_E_CTRL_PC31DOWNTO2_intermed_1 <= RIN.E.CTRL.PC ( 31 DOWNTO 2 );
RIN_A_CTRL_PC31DOWNTO2_intermed_1 <= RIN.A.CTRL.PC ( 31 DOWNTO 2 );
RIN_A_CTRL_PC31DOWNTO2_intermed_2 <= RIN_A_CTRL_PC31DOWNTO2_intermed_1;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO2_shadow;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_2;
R_D_PC31DOWNTO2_intermed_1 <= R.D.PC( 31 DOWNTO 2 );
R_D_PC31DOWNTO2_intermed_2 <= R_D_PC31DOWNTO2_intermed_1;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_E_CTRL_PC31DOWNTO2_shadow;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_1;
RIN_A_CTRL_PC31DOWNTO2_intermed_1 <= RIN.A.CTRL.PC( 31 DOWNTO 2 );
RIN_A_CTRL_PC31DOWNTO2_intermed_2 <= RIN_A_CTRL_PC31DOWNTO2_intermed_1;
RIN_A_CTRL_PC31DOWNTO2_intermed_3 <= RIN_A_CTRL_PC31DOWNTO2_intermed_2;
R_A_CTRL_PC31DOWNTO2_intermed_1 <= R.A.CTRL.PC( 31 DOWNTO 2 );
R_A_CTRL_PC31DOWNTO2_intermed_2 <= R_A_CTRL_PC31DOWNTO2_intermed_1;
R_A_CTRL_PC31DOWNTO2_intermed_1 <= R.A.CTRL.PC ( 31 DOWNTO 2 );
V_A_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO2_shadow;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_1;
R_E_CTRL_PC31DOWNTO2_intermed_1 <= R.E.CTRL.PC( 31 DOWNTO 2 );
RIN_E_CTRL_PC31DOWNTO2_intermed_1 <= RIN.E.CTRL.PC( 31 DOWNTO 2 );
RIN_E_CTRL_PC31DOWNTO2_intermed_2 <= RIN_E_CTRL_PC31DOWNTO2_intermed_1;
RIN_D_INST0_intermed_1 <= RIN.D.INST ( 0 );
RIN_D_INST0_intermed_2 <= RIN_D_INST0_intermed_1;
RIN_D_INST0_intermed_3 <= RIN_D_INST0_intermed_2;
DE_INST_shadow_intermed_1 <= DE_INST_shadow;
DE_INST_shadow_intermed_2 <= DE_INST_shadow_intermed_1;
V_A_CTRL_INST_shadow_intermed_1 <= V_A_CTRL_INST_shadow;
V_A_CTRL_INST_shadow_intermed_2 <= V_A_CTRL_INST_shadow_intermed_1;
R_D_INST0_intermed_1 <= R.D.INST( 0 );
R_D_INST0_intermed_2 <= R_D_INST0_intermed_1;
R_D_INST0_intermed_3 <= R_D_INST0_intermed_2;
R_D_INST0_intermed_1 <= R.D.INST ( 0 );
R_D_INST0_intermed_2 <= R_D_INST0_intermed_1;
RIN_A_CTRL_INST_intermed_1 <= RIN.A.CTRL.INST;
RIN_A_CTRL_INST_intermed_2 <= RIN_A_CTRL_INST_intermed_1;
V_D_INST0_shadow_intermed_1 <= V_D_INST0_shadow;
V_D_INST0_shadow_intermed_2 <= V_D_INST0_shadow_intermed_1;
V_D_INST0_shadow_intermed_3 <= V_D_INST0_shadow_intermed_2;
V_D_INST0_shadow_intermed_4 <= V_D_INST0_shadow_intermed_3;
RIN_E_CTRL_INST_intermed_1 <= RIN.E.CTRL.INST;
RIN_D_INST0_intermed_1 <= RIN.D.INST( 0 );
RIN_D_INST0_intermed_2 <= RIN_D_INST0_intermed_1;
RIN_D_INST0_intermed_3 <= RIN_D_INST0_intermed_2;
RIN_D_INST0_intermed_4 <= RIN_D_INST0_intermed_3;
R_A_CTRL_INST_intermed_1 <= R.A.CTRL.INST;
V_D_INST0_shadow_intermed_1 <= V_D_INST0_shadow;
V_D_INST0_shadow_intermed_2 <= V_D_INST0_shadow_intermed_1;
V_D_INST0_shadow_intermed_3 <= V_D_INST0_shadow_intermed_2;
RIN_D_CNT_intermed_1 <= RIN.D.CNT;
RIN_D_CNT_intermed_2 <= RIN_D_CNT_intermed_1;
RIN_D_CNT_intermed_3 <= RIN_D_CNT_intermed_2;
V_A_CTRL_CNT_shadow_intermed_1 <= V_A_CTRL_CNT_shadow;
V_A_CTRL_CNT_shadow_intermed_2 <= V_A_CTRL_CNT_shadow_intermed_1;
R_A_CTRL_CNT_intermed_1 <= R.A.CTRL.CNT;
V_D_CNT_shadow_intermed_1 <= V_D_CNT_shadow;
V_D_CNT_shadow_intermed_2 <= V_D_CNT_shadow_intermed_1;
V_D_CNT_shadow_intermed_3 <= V_D_CNT_shadow_intermed_2;
R_D_CNT_intermed_1 <= R.D.CNT;
R_D_CNT_intermed_2 <= R_D_CNT_intermed_1;
RIN_A_CTRL_CNT_intermed_1 <= RIN.A.CTRL.CNT;
RIN_A_CTRL_CNT_intermed_2 <= RIN_A_CTRL_CNT_intermed_1;
RIN_E_CTRL_CNT_intermed_1 <= RIN.E.CTRL.CNT;
V_A_CTRL_TRAP_shadow_intermed_1 <= V_A_CTRL_TRAP_shadow;
V_A_CTRL_TRAP_shadow_intermed_2 <= V_A_CTRL_TRAP_shadow_intermed_1;
ICO_MEXC_intermed_1 <= ICO.MEXC;
ICO_MEXC_intermed_2 <= ICO_MEXC_intermed_1;
ICO_MEXC_intermed_3 <= ICO_MEXC_intermed_2;
RIN_A_CTRL_TRAP_intermed_1 <= RIN.A.CTRL.TRAP;
RIN_A_CTRL_TRAP_intermed_2 <= RIN_A_CTRL_TRAP_intermed_1;
RIN_E_CTRL_TRAP_intermed_1 <= RIN.E.CTRL.TRAP;
R_D_MEXC_intermed_1 <= R.D.MEXC;
R_D_MEXC_intermed_2 <= R_D_MEXC_intermed_1;
V_D_MEXC_shadow_intermed_1 <= V_D_MEXC_shadow;
V_D_MEXC_shadow_intermed_2 <= V_D_MEXC_shadow_intermed_1;
V_D_MEXC_shadow_intermed_3 <= V_D_MEXC_shadow_intermed_2;
R_A_CTRL_TRAP_intermed_1 <= R.A.CTRL.TRAP;
RIN_D_MEXC_intermed_1 <= RIN.D.MEXC;
RIN_D_MEXC_intermed_2 <= RIN_D_MEXC_intermed_1;
RIN_D_MEXC_intermed_3 <= RIN_D_MEXC_intermed_2;
R_A_CTRL_PV_intermed_1 <= R.A.CTRL.PV;
RIN_E_CTRL_PV_intermed_1 <= RIN.E.CTRL.PV;
V_A_CTRL_PV_shadow_intermed_1 <= V_A_CTRL_PV_shadow;
V_A_CTRL_PV_shadow_intermed_2 <= V_A_CTRL_PV_shadow_intermed_1;
RIN_A_CTRL_PV_intermed_1 <= RIN.A.CTRL.PV;
RIN_A_CTRL_PV_intermed_2 <= RIN_A_CTRL_PV_intermed_1;
RIN_M_CTRL_PC31DOWNTO2_intermed_1 <= RIN.M.CTRL.PC( 31 DOWNTO 2 );
RIN_M_CTRL_PC31DOWNTO2_intermed_2 <= RIN_M_CTRL_PC31DOWNTO2_intermed_1;
R_E_CTRL_PC31DOWNTO2_intermed_1 <= R.E.CTRL.PC ( 31 DOWNTO 2 );
V_D_PC31DOWNTO2_shadow_intermed_1 <= V_D_PC31DOWNTO2_shadow;
V_D_PC31DOWNTO2_shadow_intermed_2 <= V_D_PC31DOWNTO2_shadow_intermed_1;
V_D_PC31DOWNTO2_shadow_intermed_3 <= V_D_PC31DOWNTO2_shadow_intermed_2;
V_D_PC31DOWNTO2_shadow_intermed_4 <= V_D_PC31DOWNTO2_shadow_intermed_3;
RIN_D_PC31DOWNTO2_intermed_1 <= RIN.D.PC( 31 DOWNTO 2 );
RIN_D_PC31DOWNTO2_intermed_2 <= RIN_D_PC31DOWNTO2_intermed_1;
RIN_D_PC31DOWNTO2_intermed_3 <= RIN_D_PC31DOWNTO2_intermed_2;
RIN_D_PC31DOWNTO2_intermed_4 <= RIN_D_PC31DOWNTO2_intermed_3;
RIN_E_CTRL_PC31DOWNTO2_intermed_1 <= RIN.E.CTRL.PC ( 31 DOWNTO 2 );
RIN_E_CTRL_PC31DOWNTO2_intermed_2 <= RIN_E_CTRL_PC31DOWNTO2_intermed_1;
RIN_A_CTRL_PC31DOWNTO2_intermed_1 <= RIN.A.CTRL.PC ( 31 DOWNTO 2 );
RIN_A_CTRL_PC31DOWNTO2_intermed_2 <= RIN_A_CTRL_PC31DOWNTO2_intermed_1;
RIN_A_CTRL_PC31DOWNTO2_intermed_3 <= RIN_A_CTRL_PC31DOWNTO2_intermed_2;
RIN_M_CTRL_PC31DOWNTO2_intermed_1 <= RIN.M.CTRL.PC ( 31 DOWNTO 2 );
V_A_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO2_shadow;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_2;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_4 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_3;
R_D_PC31DOWNTO2_intermed_1 <= R.D.PC( 31 DOWNTO 2 );
R_D_PC31DOWNTO2_intermed_2 <= R_D_PC31DOWNTO2_intermed_1;
R_D_PC31DOWNTO2_intermed_3 <= R_D_PC31DOWNTO2_intermed_2;
R_M_CTRL_PC31DOWNTO2_intermed_1 <= R.M.CTRL.PC( 31 DOWNTO 2 );
V_E_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_E_CTRL_PC31DOWNTO2_shadow;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_2;
RIN_A_CTRL_PC31DOWNTO2_intermed_1 <= RIN.A.CTRL.PC( 31 DOWNTO 2 );
RIN_A_CTRL_PC31DOWNTO2_intermed_2 <= RIN_A_CTRL_PC31DOWNTO2_intermed_1;
RIN_A_CTRL_PC31DOWNTO2_intermed_3 <= RIN_A_CTRL_PC31DOWNTO2_intermed_2;
RIN_A_CTRL_PC31DOWNTO2_intermed_4 <= RIN_A_CTRL_PC31DOWNTO2_intermed_3;
R_A_CTRL_PC31DOWNTO2_intermed_1 <= R.A.CTRL.PC( 31 DOWNTO 2 );
R_A_CTRL_PC31DOWNTO2_intermed_2 <= R_A_CTRL_PC31DOWNTO2_intermed_1;
R_A_CTRL_PC31DOWNTO2_intermed_3 <= R_A_CTRL_PC31DOWNTO2_intermed_2;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_M_CTRL_PC31DOWNTO2_shadow;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_M_CTRL_PC31DOWNTO2_shadow_intermed_1;
R_A_CTRL_PC31DOWNTO2_intermed_1 <= R.A.CTRL.PC ( 31 DOWNTO 2 );
R_A_CTRL_PC31DOWNTO2_intermed_2 <= R_A_CTRL_PC31DOWNTO2_intermed_1;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO2_shadow;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_2;
R_E_CTRL_PC31DOWNTO2_intermed_1 <= R.E.CTRL.PC( 31 DOWNTO 2 );
R_E_CTRL_PC31DOWNTO2_intermed_2 <= R_E_CTRL_PC31DOWNTO2_intermed_1;
RIN_E_CTRL_PC31DOWNTO2_intermed_1 <= RIN.E.CTRL.PC( 31 DOWNTO 2 );
RIN_E_CTRL_PC31DOWNTO2_intermed_2 <= RIN_E_CTRL_PC31DOWNTO2_intermed_1;
RIN_E_CTRL_PC31DOWNTO2_intermed_3 <= RIN_E_CTRL_PC31DOWNTO2_intermed_2;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_E_CTRL_PC31DOWNTO2_shadow;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_1;
R_E_CTRL_INST_intermed_1 <= R.E.CTRL.INST;
RIN_D_INST0_intermed_1 <= RIN.D.INST ( 0 );
RIN_D_INST0_intermed_2 <= RIN_D_INST0_intermed_1;
RIN_D_INST0_intermed_3 <= RIN_D_INST0_intermed_2;
RIN_D_INST0_intermed_4 <= RIN_D_INST0_intermed_3;
DE_INST_shadow_intermed_1 <= DE_INST_shadow;
DE_INST_shadow_intermed_2 <= DE_INST_shadow_intermed_1;
DE_INST_shadow_intermed_3 <= DE_INST_shadow_intermed_2;
V_A_CTRL_INST_shadow_intermed_1 <= V_A_CTRL_INST_shadow;
V_A_CTRL_INST_shadow_intermed_2 <= V_A_CTRL_INST_shadow_intermed_1;
V_A_CTRL_INST_shadow_intermed_3 <= V_A_CTRL_INST_shadow_intermed_2;
R_D_INST0_intermed_1 <= R.D.INST( 0 );
R_D_INST0_intermed_2 <= R_D_INST0_intermed_1;
R_D_INST0_intermed_3 <= R_D_INST0_intermed_2;
R_D_INST0_intermed_4 <= R_D_INST0_intermed_3;
V_E_CTRL_INST_shadow_intermed_1 <= V_E_CTRL_INST_shadow;
V_E_CTRL_INST_shadow_intermed_2 <= V_E_CTRL_INST_shadow_intermed_1;
R_D_INST0_intermed_1 <= R.D.INST ( 0 );
R_D_INST0_intermed_2 <= R_D_INST0_intermed_1;
R_D_INST0_intermed_3 <= R_D_INST0_intermed_2;
RIN_A_CTRL_INST_intermed_1 <= RIN.A.CTRL.INST;
RIN_A_CTRL_INST_intermed_2 <= RIN_A_CTRL_INST_intermed_1;
RIN_A_CTRL_INST_intermed_3 <= RIN_A_CTRL_INST_intermed_2;
V_D_INST0_shadow_intermed_1 <= V_D_INST0_shadow;
V_D_INST0_shadow_intermed_2 <= V_D_INST0_shadow_intermed_1;
V_D_INST0_shadow_intermed_3 <= V_D_INST0_shadow_intermed_2;
V_D_INST0_shadow_intermed_4 <= V_D_INST0_shadow_intermed_3;
V_D_INST0_shadow_intermed_5 <= V_D_INST0_shadow_intermed_4;
RIN_M_CTRL_INST_intermed_1 <= RIN.M.CTRL.INST;
RIN_E_CTRL_INST_intermed_1 <= RIN.E.CTRL.INST;
RIN_E_CTRL_INST_intermed_2 <= RIN_E_CTRL_INST_intermed_1;
RIN_D_INST0_intermed_1 <= RIN.D.INST( 0 );
RIN_D_INST0_intermed_2 <= RIN_D_INST0_intermed_1;
RIN_D_INST0_intermed_3 <= RIN_D_INST0_intermed_2;
RIN_D_INST0_intermed_4 <= RIN_D_INST0_intermed_3;
RIN_D_INST0_intermed_5 <= RIN_D_INST0_intermed_4;
R_A_CTRL_INST_intermed_1 <= R.A.CTRL.INST;
R_A_CTRL_INST_intermed_2 <= R_A_CTRL_INST_intermed_1;
V_D_INST0_shadow_intermed_1 <= V_D_INST0_shadow;
V_D_INST0_shadow_intermed_2 <= V_D_INST0_shadow_intermed_1;
V_D_INST0_shadow_intermed_3 <= V_D_INST0_shadow_intermed_2;
V_D_INST0_shadow_intermed_4 <= V_D_INST0_shadow_intermed_3;
V_E_CTRL_CNT_shadow_intermed_1 <= V_E_CTRL_CNT_shadow;
V_E_CTRL_CNT_shadow_intermed_2 <= V_E_CTRL_CNT_shadow_intermed_1;
RIN_D_CNT_intermed_1 <= RIN.D.CNT;
RIN_D_CNT_intermed_2 <= RIN_D_CNT_intermed_1;
RIN_D_CNT_intermed_3 <= RIN_D_CNT_intermed_2;
RIN_D_CNT_intermed_4 <= RIN_D_CNT_intermed_3;
V_A_CTRL_CNT_shadow_intermed_1 <= V_A_CTRL_CNT_shadow;
V_A_CTRL_CNT_shadow_intermed_2 <= V_A_CTRL_CNT_shadow_intermed_1;
V_A_CTRL_CNT_shadow_intermed_3 <= V_A_CTRL_CNT_shadow_intermed_2;
R_A_CTRL_CNT_intermed_1 <= R.A.CTRL.CNT;
R_A_CTRL_CNT_intermed_2 <= R_A_CTRL_CNT_intermed_1;
V_D_CNT_shadow_intermed_1 <= V_D_CNT_shadow;
V_D_CNT_shadow_intermed_2 <= V_D_CNT_shadow_intermed_1;
V_D_CNT_shadow_intermed_3 <= V_D_CNT_shadow_intermed_2;
V_D_CNT_shadow_intermed_4 <= V_D_CNT_shadow_intermed_3;
R_D_CNT_intermed_1 <= R.D.CNT;
R_D_CNT_intermed_2 <= R_D_CNT_intermed_1;
R_D_CNT_intermed_3 <= R_D_CNT_intermed_2;
R_E_CTRL_CNT_intermed_1 <= R.E.CTRL.CNT;
RIN_A_CTRL_CNT_intermed_1 <= RIN.A.CTRL.CNT;
RIN_A_CTRL_CNT_intermed_2 <= RIN_A_CTRL_CNT_intermed_1;
RIN_A_CTRL_CNT_intermed_3 <= RIN_A_CTRL_CNT_intermed_2;
RIN_M_CTRL_CNT_intermed_1 <= RIN.M.CTRL.CNT;
RIN_E_CTRL_CNT_intermed_1 <= RIN.E.CTRL.CNT;
RIN_E_CTRL_CNT_intermed_2 <= RIN_E_CTRL_CNT_intermed_1;
V_A_CTRL_TRAP_shadow_intermed_1 <= V_A_CTRL_TRAP_shadow;
V_A_CTRL_TRAP_shadow_intermed_2 <= V_A_CTRL_TRAP_shadow_intermed_1;
V_A_CTRL_TRAP_shadow_intermed_3 <= V_A_CTRL_TRAP_shadow_intermed_2;
ICO_MEXC_intermed_1 <= ICO.MEXC;
ICO_MEXC_intermed_2 <= ICO_MEXC_intermed_1;
ICO_MEXC_intermed_3 <= ICO_MEXC_intermed_2;
ICO_MEXC_intermed_4 <= ICO_MEXC_intermed_3;
R_E_CTRL_TRAP_intermed_1 <= R.E.CTRL.TRAP;
RIN_A_CTRL_TRAP_intermed_1 <= RIN.A.CTRL.TRAP;
RIN_A_CTRL_TRAP_intermed_2 <= RIN_A_CTRL_TRAP_intermed_1;
RIN_A_CTRL_TRAP_intermed_3 <= RIN_A_CTRL_TRAP_intermed_2;
V_E_CTRL_TRAP_shadow_intermed_1 <= V_E_CTRL_TRAP_shadow;
V_E_CTRL_TRAP_shadow_intermed_2 <= V_E_CTRL_TRAP_shadow_intermed_1;
RIN_E_CTRL_TRAP_intermed_1 <= RIN.E.CTRL.TRAP;
RIN_E_CTRL_TRAP_intermed_2 <= RIN_E_CTRL_TRAP_intermed_1;
R_D_MEXC_intermed_1 <= R.D.MEXC;
R_D_MEXC_intermed_2 <= R_D_MEXC_intermed_1;
R_D_MEXC_intermed_3 <= R_D_MEXC_intermed_2;
V_D_MEXC_shadow_intermed_1 <= V_D_MEXC_shadow;
V_D_MEXC_shadow_intermed_2 <= V_D_MEXC_shadow_intermed_1;
V_D_MEXC_shadow_intermed_3 <= V_D_MEXC_shadow_intermed_2;
V_D_MEXC_shadow_intermed_4 <= V_D_MEXC_shadow_intermed_3;
R_A_CTRL_TRAP_intermed_1 <= R.A.CTRL.TRAP;
R_A_CTRL_TRAP_intermed_2 <= R_A_CTRL_TRAP_intermed_1;
RIN_M_CTRL_TRAP_intermed_1 <= RIN.M.CTRL.TRAP;
RIN_D_MEXC_intermed_1 <= RIN.D.MEXC;
RIN_D_MEXC_intermed_2 <= RIN_D_MEXC_intermed_1;
RIN_D_MEXC_intermed_3 <= RIN_D_MEXC_intermed_2;
RIN_D_MEXC_intermed_4 <= RIN_D_MEXC_intermed_3;
V_E_CTRL_PV_shadow_intermed_1 <= V_E_CTRL_PV_shadow;
V_E_CTRL_PV_shadow_intermed_2 <= V_E_CTRL_PV_shadow_intermed_1;
R_E_CTRL_PV_intermed_1 <= R.E.CTRL.PV;
R_A_CTRL_PV_intermed_1 <= R.A.CTRL.PV;
R_A_CTRL_PV_intermed_2 <= R_A_CTRL_PV_intermed_1;
RIN_E_CTRL_PV_intermed_1 <= RIN.E.CTRL.PV;
RIN_E_CTRL_PV_intermed_2 <= RIN_E_CTRL_PV_intermed_1;
RIN_M_CTRL_PV_intermed_1 <= RIN.M.CTRL.PV;
V_A_CTRL_PV_shadow_intermed_1 <= V_A_CTRL_PV_shadow;
V_A_CTRL_PV_shadow_intermed_2 <= V_A_CTRL_PV_shadow_intermed_1;
V_A_CTRL_PV_shadow_intermed_3 <= V_A_CTRL_PV_shadow_intermed_2;
RIN_A_CTRL_PV_intermed_1 <= RIN.A.CTRL.PV;
RIN_A_CTRL_PV_intermed_2 <= RIN_A_CTRL_PV_intermed_1;
RIN_A_CTRL_PV_intermed_3 <= RIN_A_CTRL_PV_intermed_2;
R_E_CTRL_INST_intermed_1 <= R.E.CTRL.INST;
R_E_CTRL_INST_intermed_2 <= R_E_CTRL_INST_intermed_1;
RIN_D_INST0_intermed_1 <= RIN.D.INST ( 0 );
RIN_D_INST0_intermed_2 <= RIN_D_INST0_intermed_1;
RIN_D_INST0_intermed_3 <= RIN_D_INST0_intermed_2;
RIN_D_INST0_intermed_4 <= RIN_D_INST0_intermed_3;
RIN_D_INST0_intermed_5 <= RIN_D_INST0_intermed_4;
R_M_CTRL_INST_intermed_1 <= R.M.CTRL.INST;
DE_INST_shadow_intermed_1 <= DE_INST_shadow;
DE_INST_shadow_intermed_2 <= DE_INST_shadow_intermed_1;
DE_INST_shadow_intermed_3 <= DE_INST_shadow_intermed_2;
DE_INST_shadow_intermed_4 <= DE_INST_shadow_intermed_3;
V_A_CTRL_INST_shadow_intermed_1 <= V_A_CTRL_INST_shadow;
V_A_CTRL_INST_shadow_intermed_2 <= V_A_CTRL_INST_shadow_intermed_1;
V_A_CTRL_INST_shadow_intermed_3 <= V_A_CTRL_INST_shadow_intermed_2;
V_A_CTRL_INST_shadow_intermed_4 <= V_A_CTRL_INST_shadow_intermed_3;
R_D_INST0_intermed_1 <= R.D.INST( 0 );
R_D_INST0_intermed_2 <= R_D_INST0_intermed_1;
R_D_INST0_intermed_3 <= R_D_INST0_intermed_2;
R_D_INST0_intermed_4 <= R_D_INST0_intermed_3;
R_D_INST0_intermed_5 <= R_D_INST0_intermed_4;
V_E_CTRL_INST_shadow_intermed_1 <= V_E_CTRL_INST_shadow;
V_E_CTRL_INST_shadow_intermed_2 <= V_E_CTRL_INST_shadow_intermed_1;
V_E_CTRL_INST_shadow_intermed_3 <= V_E_CTRL_INST_shadow_intermed_2;
R_D_INST0_intermed_1 <= R.D.INST ( 0 );
R_D_INST0_intermed_2 <= R_D_INST0_intermed_1;
R_D_INST0_intermed_3 <= R_D_INST0_intermed_2;
R_D_INST0_intermed_4 <= R_D_INST0_intermed_3;
RIN_X_CTRL_INST_intermed_1 <= RIN.X.CTRL.INST;
RIN_A_CTRL_INST_intermed_1 <= RIN.A.CTRL.INST;
RIN_A_CTRL_INST_intermed_2 <= RIN_A_CTRL_INST_intermed_1;
RIN_A_CTRL_INST_intermed_3 <= RIN_A_CTRL_INST_intermed_2;
RIN_A_CTRL_INST_intermed_4 <= RIN_A_CTRL_INST_intermed_3;
V_D_INST0_shadow_intermed_1 <= V_D_INST0_shadow;
V_D_INST0_shadow_intermed_2 <= V_D_INST0_shadow_intermed_1;
V_D_INST0_shadow_intermed_3 <= V_D_INST0_shadow_intermed_2;
V_D_INST0_shadow_intermed_4 <= V_D_INST0_shadow_intermed_3;
V_D_INST0_shadow_intermed_5 <= V_D_INST0_shadow_intermed_4;
V_D_INST0_shadow_intermed_6 <= V_D_INST0_shadow_intermed_5;
RIN_M_CTRL_INST_intermed_1 <= RIN.M.CTRL.INST;
RIN_M_CTRL_INST_intermed_2 <= RIN_M_CTRL_INST_intermed_1;
RIN_E_CTRL_INST_intermed_1 <= RIN.E.CTRL.INST;
RIN_E_CTRL_INST_intermed_2 <= RIN_E_CTRL_INST_intermed_1;
RIN_E_CTRL_INST_intermed_3 <= RIN_E_CTRL_INST_intermed_2;
V_M_CTRL_INST_shadow_intermed_1 <= V_M_CTRL_INST_shadow;
V_M_CTRL_INST_shadow_intermed_2 <= V_M_CTRL_INST_shadow_intermed_1;
RIN_D_INST0_intermed_1 <= RIN.D.INST( 0 );
RIN_D_INST0_intermed_2 <= RIN_D_INST0_intermed_1;
RIN_D_INST0_intermed_3 <= RIN_D_INST0_intermed_2;
RIN_D_INST0_intermed_4 <= RIN_D_INST0_intermed_3;
RIN_D_INST0_intermed_5 <= RIN_D_INST0_intermed_4;
RIN_D_INST0_intermed_6 <= RIN_D_INST0_intermed_5;
R_A_CTRL_INST_intermed_1 <= R.A.CTRL.INST;
R_A_CTRL_INST_intermed_2 <= R_A_CTRL_INST_intermed_1;
R_A_CTRL_INST_intermed_3 <= R_A_CTRL_INST_intermed_2;
V_D_INST0_shadow_intermed_1 <= V_D_INST0_shadow;
V_D_INST0_shadow_intermed_2 <= V_D_INST0_shadow_intermed_1;
V_D_INST0_shadow_intermed_3 <= V_D_INST0_shadow_intermed_2;
V_D_INST0_shadow_intermed_4 <= V_D_INST0_shadow_intermed_3;
V_D_INST0_shadow_intermed_5 <= V_D_INST0_shadow_intermed_4;
V_E_CTRL_CNT_shadow_intermed_1 <= V_E_CTRL_CNT_shadow;
V_E_CTRL_CNT_shadow_intermed_2 <= V_E_CTRL_CNT_shadow_intermed_1;
V_E_CTRL_CNT_shadow_intermed_3 <= V_E_CTRL_CNT_shadow_intermed_2;
RIN_D_CNT_intermed_1 <= RIN.D.CNT;
RIN_D_CNT_intermed_2 <= RIN_D_CNT_intermed_1;
RIN_D_CNT_intermed_3 <= RIN_D_CNT_intermed_2;
RIN_D_CNT_intermed_4 <= RIN_D_CNT_intermed_3;
RIN_D_CNT_intermed_5 <= RIN_D_CNT_intermed_4;
R_M_CTRL_CNT_intermed_1 <= R.M.CTRL.CNT;
V_A_CTRL_CNT_shadow_intermed_1 <= V_A_CTRL_CNT_shadow;
V_A_CTRL_CNT_shadow_intermed_2 <= V_A_CTRL_CNT_shadow_intermed_1;
V_A_CTRL_CNT_shadow_intermed_3 <= V_A_CTRL_CNT_shadow_intermed_2;
V_A_CTRL_CNT_shadow_intermed_4 <= V_A_CTRL_CNT_shadow_intermed_3;
R_A_CTRL_CNT_intermed_1 <= R.A.CTRL.CNT;
R_A_CTRL_CNT_intermed_2 <= R_A_CTRL_CNT_intermed_1;
R_A_CTRL_CNT_intermed_3 <= R_A_CTRL_CNT_intermed_2;
V_D_CNT_shadow_intermed_1 <= V_D_CNT_shadow;
V_D_CNT_shadow_intermed_2 <= V_D_CNT_shadow_intermed_1;
V_D_CNT_shadow_intermed_3 <= V_D_CNT_shadow_intermed_2;
V_D_CNT_shadow_intermed_4 <= V_D_CNT_shadow_intermed_3;
V_D_CNT_shadow_intermed_5 <= V_D_CNT_shadow_intermed_4;
R_D_CNT_intermed_1 <= R.D.CNT;
R_D_CNT_intermed_2 <= R_D_CNT_intermed_1;
R_D_CNT_intermed_3 <= R_D_CNT_intermed_2;
R_D_CNT_intermed_4 <= R_D_CNT_intermed_3;
R_E_CTRL_CNT_intermed_1 <= R.E.CTRL.CNT;
R_E_CTRL_CNT_intermed_2 <= R_E_CTRL_CNT_intermed_1;
RIN_X_CTRL_CNT_intermed_1 <= RIN.X.CTRL.CNT;
RIN_A_CTRL_CNT_intermed_1 <= RIN.A.CTRL.CNT;
RIN_A_CTRL_CNT_intermed_2 <= RIN_A_CTRL_CNT_intermed_1;
RIN_A_CTRL_CNT_intermed_3 <= RIN_A_CTRL_CNT_intermed_2;
RIN_A_CTRL_CNT_intermed_4 <= RIN_A_CTRL_CNT_intermed_3;
RIN_M_CTRL_CNT_intermed_1 <= RIN.M.CTRL.CNT;
RIN_M_CTRL_CNT_intermed_2 <= RIN_M_CTRL_CNT_intermed_1;
RIN_E_CTRL_CNT_intermed_1 <= RIN.E.CTRL.CNT;
RIN_E_CTRL_CNT_intermed_2 <= RIN_E_CTRL_CNT_intermed_1;
RIN_E_CTRL_CNT_intermed_3 <= RIN_E_CTRL_CNT_intermed_2;
V_M_CTRL_CNT_shadow_intermed_1 <= V_M_CTRL_CNT_shadow;
V_M_CTRL_CNT_shadow_intermed_2 <= V_M_CTRL_CNT_shadow_intermed_1;
V_E_CTRL_PV_shadow_intermed_1 <= V_E_CTRL_PV_shadow;
V_E_CTRL_PV_shadow_intermed_2 <= V_E_CTRL_PV_shadow_intermed_1;
V_E_CTRL_PV_shadow_intermed_3 <= V_E_CTRL_PV_shadow_intermed_2;
R_M_CTRL_PV_intermed_1 <= R.M.CTRL.PV;
R_E_CTRL_PV_intermed_1 <= R.E.CTRL.PV;
R_E_CTRL_PV_intermed_2 <= R_E_CTRL_PV_intermed_1;
R_A_CTRL_PV_intermed_1 <= R.A.CTRL.PV;
R_A_CTRL_PV_intermed_2 <= R_A_CTRL_PV_intermed_1;
R_A_CTRL_PV_intermed_3 <= R_A_CTRL_PV_intermed_2;
RIN_E_CTRL_PV_intermed_1 <= RIN.E.CTRL.PV;
RIN_E_CTRL_PV_intermed_2 <= RIN_E_CTRL_PV_intermed_1;
RIN_E_CTRL_PV_intermed_3 <= RIN_E_CTRL_PV_intermed_2;
RIN_X_CTRL_PV_intermed_1 <= RIN.X.CTRL.PV;
RIN_M_CTRL_PV_intermed_1 <= RIN.M.CTRL.PV;
RIN_M_CTRL_PV_intermed_2 <= RIN_M_CTRL_PV_intermed_1;
V_A_CTRL_PV_shadow_intermed_1 <= V_A_CTRL_PV_shadow;
V_A_CTRL_PV_shadow_intermed_2 <= V_A_CTRL_PV_shadow_intermed_1;
V_A_CTRL_PV_shadow_intermed_3 <= V_A_CTRL_PV_shadow_intermed_2;
V_A_CTRL_PV_shadow_intermed_4 <= V_A_CTRL_PV_shadow_intermed_3;
V_M_CTRL_PV_shadow_intermed_1 <= V_M_CTRL_PV_shadow;
V_M_CTRL_PV_shadow_intermed_2 <= V_M_CTRL_PV_shadow_intermed_1;
RIN_A_CTRL_PV_intermed_1 <= RIN.A.CTRL.PV;
RIN_A_CTRL_PV_intermed_2 <= RIN_A_CTRL_PV_intermed_1;
RIN_A_CTRL_PV_intermed_3 <= RIN_A_CTRL_PV_intermed_2;
RIN_A_CTRL_PV_intermed_4 <= RIN_A_CTRL_PV_intermed_3;
V_A_CTRL_INST19_shadow_intermed_1 <= V_A_CTRL_INST19_shadow;
V_A_CTRL_INST19_shadow_intermed_2 <= V_A_CTRL_INST19_shadow_intermed_1;
R_D_INST019_intermed_1 <= R.D.INST( 0 )( 19 );
R_D_INST019_intermed_2 <= R_D_INST019_intermed_1;
R_D_INST019_intermed_3 <= R_D_INST019_intermed_2;
V_D_INST019_shadow_intermed_1 <= V_D_INST019_shadow;
V_D_INST019_shadow_intermed_2 <= V_D_INST019_shadow_intermed_1;
V_D_INST019_shadow_intermed_3 <= V_D_INST019_shadow_intermed_2;
V_D_INST019_shadow_intermed_4 <= V_D_INST019_shadow_intermed_3;
RIN_A_CTRL_INST19_intermed_1 <= RIN.A.CTRL.INST( 19 );
RIN_A_CTRL_INST19_intermed_2 <= RIN_A_CTRL_INST19_intermed_1;
RIN_E_CTRL_INST19_intermed_1 <= RIN.E.CTRL.INST( 19 );
DE_INST19_shadow_intermed_1 <= DE_INST19_shadow;
DE_INST19_shadow_intermed_2 <= DE_INST19_shadow_intermed_1;
R_D_INST019_intermed_1 <= R.D.INST ( 0 )( 19 );
R_D_INST019_intermed_2 <= R_D_INST019_intermed_1;
RIN_D_INST019_intermed_1 <= RIN.D.INST ( 0 )( 19 );
RIN_D_INST019_intermed_2 <= RIN_D_INST019_intermed_1;
RIN_D_INST019_intermed_3 <= RIN_D_INST019_intermed_2;
V_D_INST019_shadow_intermed_1 <= V_D_INST019_shadow;
V_D_INST019_shadow_intermed_2 <= V_D_INST019_shadow_intermed_1;
V_D_INST019_shadow_intermed_3 <= V_D_INST019_shadow_intermed_2;
R_A_CTRL_INST19_intermed_1 <= R.A.CTRL.INST( 19 );
RIN_D_INST019_intermed_1 <= RIN.D.INST( 0 )( 19 );
RIN_D_INST019_intermed_2 <= RIN_D_INST019_intermed_1;
RIN_D_INST019_intermed_3 <= RIN_D_INST019_intermed_2;
RIN_D_INST019_intermed_4 <= RIN_D_INST019_intermed_3;
R_D_INST020_intermed_1 <= R.D.INST ( 0 )( 20 );
R_D_INST020_intermed_2 <= R_D_INST020_intermed_1;
RIN_D_INST020_intermed_1 <= RIN.D.INST( 0 )( 20 );
RIN_D_INST020_intermed_2 <= RIN_D_INST020_intermed_1;
RIN_D_INST020_intermed_3 <= RIN_D_INST020_intermed_2;
RIN_D_INST020_intermed_4 <= RIN_D_INST020_intermed_3;
RIN_D_INST020_intermed_1 <= RIN.D.INST ( 0 )( 20 );
RIN_D_INST020_intermed_2 <= RIN_D_INST020_intermed_1;
RIN_D_INST020_intermed_3 <= RIN_D_INST020_intermed_2;
RIN_A_CTRL_INST20_intermed_1 <= RIN.A.CTRL.INST( 20 );
RIN_A_CTRL_INST20_intermed_2 <= RIN_A_CTRL_INST20_intermed_1;
V_A_CTRL_INST20_shadow_intermed_1 <= V_A_CTRL_INST20_shadow;
V_A_CTRL_INST20_shadow_intermed_2 <= V_A_CTRL_INST20_shadow_intermed_1;
RIN_E_CTRL_INST20_intermed_1 <= RIN.E.CTRL.INST( 20 );
V_D_INST020_shadow_intermed_1 <= V_D_INST020_shadow;
V_D_INST020_shadow_intermed_2 <= V_D_INST020_shadow_intermed_1;
V_D_INST020_shadow_intermed_3 <= V_D_INST020_shadow_intermed_2;
V_D_INST020_shadow_intermed_1 <= V_D_INST020_shadow;
V_D_INST020_shadow_intermed_2 <= V_D_INST020_shadow_intermed_1;
V_D_INST020_shadow_intermed_3 <= V_D_INST020_shadow_intermed_2;
V_D_INST020_shadow_intermed_4 <= V_D_INST020_shadow_intermed_3;
R_D_INST020_intermed_1 <= R.D.INST( 0 )( 20 );
R_D_INST020_intermed_2 <= R_D_INST020_intermed_1;
R_D_INST020_intermed_3 <= R_D_INST020_intermed_2;
DE_INST20_shadow_intermed_1 <= DE_INST20_shadow;
DE_INST20_shadow_intermed_2 <= DE_INST20_shadow_intermed_1;
R_A_CTRL_INST20_intermed_1 <= R.A.CTRL.INST( 20 );
R_A_CTRL_INST24_intermed_1 <= R.A.CTRL.INST( 24 );
RIN_D_INST024_intermed_1 <= RIN.D.INST ( 0 )( 24 );
RIN_D_INST024_intermed_2 <= RIN_D_INST024_intermed_1;
RIN_D_INST024_intermed_3 <= RIN_D_INST024_intermed_2;
V_D_INST024_shadow_intermed_1 <= V_D_INST024_shadow;
V_D_INST024_shadow_intermed_2 <= V_D_INST024_shadow_intermed_1;
V_D_INST024_shadow_intermed_3 <= V_D_INST024_shadow_intermed_2;
V_D_INST024_shadow_intermed_4 <= V_D_INST024_shadow_intermed_3;
RIN_A_CTRL_INST24_intermed_1 <= RIN.A.CTRL.INST( 24 );
RIN_A_CTRL_INST24_intermed_2 <= RIN_A_CTRL_INST24_intermed_1;
RIN_E_CTRL_INST24_intermed_1 <= RIN.E.CTRL.INST( 24 );
V_D_INST024_shadow_intermed_1 <= V_D_INST024_shadow;
V_D_INST024_shadow_intermed_2 <= V_D_INST024_shadow_intermed_1;
V_D_INST024_shadow_intermed_3 <= V_D_INST024_shadow_intermed_2;
V_A_CTRL_INST24_shadow_intermed_1 <= V_A_CTRL_INST24_shadow;
V_A_CTRL_INST24_shadow_intermed_2 <= V_A_CTRL_INST24_shadow_intermed_1;
DE_INST24_shadow_intermed_1 <= DE_INST24_shadow;
DE_INST24_shadow_intermed_2 <= DE_INST24_shadow_intermed_1;
RIN_D_INST024_intermed_1 <= RIN.D.INST( 0 )( 24 );
RIN_D_INST024_intermed_2 <= RIN_D_INST024_intermed_1;
RIN_D_INST024_intermed_3 <= RIN_D_INST024_intermed_2;
RIN_D_INST024_intermed_4 <= RIN_D_INST024_intermed_3;
R_D_INST024_intermed_1 <= R.D.INST ( 0 )( 24 );
R_D_INST024_intermed_2 <= R_D_INST024_intermed_1;
R_D_INST024_intermed_1 <= R.D.INST( 0 )( 24 );
R_D_INST024_intermed_2 <= R_D_INST024_intermed_1;
R_D_INST024_intermed_3 <= R_D_INST024_intermed_2;
R_D_INST019_intermed_1 <= R.D.INST( 0 )( 19 );
R_D_INST019_intermed_2 <= R_D_INST019_intermed_1;
V_D_INST019_shadow_intermed_1 <= V_D_INST019_shadow;
V_D_INST019_shadow_intermed_2 <= V_D_INST019_shadow_intermed_1;
V_D_INST019_shadow_intermed_3 <= V_D_INST019_shadow_intermed_2;
RIN_A_CTRL_INST19_intermed_1 <= RIN.A.CTRL.INST( 19 );
DE_INST19_shadow_intermed_1 <= DE_INST19_shadow;
R_D_INST019_intermed_1 <= R.D.INST ( 0 )( 19 );
RIN_D_INST019_intermed_1 <= RIN.D.INST ( 0 )( 19 );
RIN_D_INST019_intermed_2 <= RIN_D_INST019_intermed_1;
V_D_INST019_shadow_intermed_1 <= V_D_INST019_shadow;
V_D_INST019_shadow_intermed_2 <= V_D_INST019_shadow_intermed_1;
RIN_D_INST019_intermed_1 <= RIN.D.INST( 0 )( 19 );
RIN_D_INST019_intermed_2 <= RIN_D_INST019_intermed_1;
RIN_D_INST019_intermed_3 <= RIN_D_INST019_intermed_2;
V_X_CTRL_PC31DOWNTO4_shadow_intermed_1 <= V_X_CTRL_PC31DOWNTO4_shadow;
V_X_CTRL_PC31DOWNTO4_shadow_intermed_2 <= V_X_CTRL_PC31DOWNTO4_shadow_intermed_1;
V_X_CTRL_PC31DOWNTO4_shadow_intermed_3 <= V_X_CTRL_PC31DOWNTO4_shadow_intermed_2;
IR_ADDR31DOWNTO4_intermed_1 <= IR.ADDR( 31 DOWNTO 4 );
VIR_ADDR31DOWNTO4_shadow_intermed_1 <= VIR_ADDR31DOWNTO4_shadow;
VIR_ADDR31DOWNTO4_shadow_intermed_2 <= VIR_ADDR31DOWNTO4_shadow_intermed_1;
RIN_F_PC31DOWNTO4_intermed_1 <= RIN.F.PC( 31 DOWNTO 4 );
RIN_A_CTRL_PC31DOWNTO4_intermed_1 <= RIN.A.CTRL.PC( 31 DOWNTO 4 );
RIN_A_CTRL_PC31DOWNTO4_intermed_2 <= RIN_A_CTRL_PC31DOWNTO4_intermed_1;
RIN_A_CTRL_PC31DOWNTO4_intermed_3 <= RIN_A_CTRL_PC31DOWNTO4_intermed_2;
RIN_A_CTRL_PC31DOWNTO4_intermed_4 <= RIN_A_CTRL_PC31DOWNTO4_intermed_3;
RIN_A_CTRL_PC31DOWNTO4_intermed_5 <= RIN_A_CTRL_PC31DOWNTO4_intermed_4;
RIN_A_CTRL_PC31DOWNTO4_intermed_6 <= RIN_A_CTRL_PC31DOWNTO4_intermed_5;
R_A_CTRL_PC31DOWNTO4_intermed_1 <= R.A.CTRL.PC( 31 DOWNTO 4 );
R_A_CTRL_PC31DOWNTO4_intermed_2 <= R_A_CTRL_PC31DOWNTO4_intermed_1;
R_A_CTRL_PC31DOWNTO4_intermed_3 <= R_A_CTRL_PC31DOWNTO4_intermed_2;
R_A_CTRL_PC31DOWNTO4_intermed_4 <= R_A_CTRL_PC31DOWNTO4_intermed_3;
R_A_CTRL_PC31DOWNTO4_intermed_5 <= R_A_CTRL_PC31DOWNTO4_intermed_4;
R_D_PC31DOWNTO4_intermed_1 <= R.D.PC( 31 DOWNTO 4 );
R_D_PC31DOWNTO4_intermed_2 <= R_D_PC31DOWNTO4_intermed_1;
R_D_PC31DOWNTO4_intermed_3 <= R_D_PC31DOWNTO4_intermed_2;
R_D_PC31DOWNTO4_intermed_4 <= R_D_PC31DOWNTO4_intermed_3;
R_D_PC31DOWNTO4_intermed_5 <= R_D_PC31DOWNTO4_intermed_4;
R_D_PC31DOWNTO4_intermed_6 <= R_D_PC31DOWNTO4_intermed_5;
RIN_X_CTRL_PC31DOWNTO4_intermed_1 <= RIN.X.CTRL.PC( 31 DOWNTO 4 );
RIN_X_CTRL_PC31DOWNTO4_intermed_2 <= RIN_X_CTRL_PC31DOWNTO4_intermed_1;
RIN_X_CTRL_PC31DOWNTO4_intermed_3 <= RIN_X_CTRL_PC31DOWNTO4_intermed_2;
EX_ADD_RES32DOWNTO332DOWNTO5_shadow_intermed_1 <= EX_ADD_RES32DOWNTO332DOWNTO5_shadow;
V_D_PC31DOWNTO4_shadow_intermed_1 <= V_D_PC31DOWNTO4_shadow;
V_D_PC31DOWNTO4_shadow_intermed_2 <= V_D_PC31DOWNTO4_shadow_intermed_1;
V_D_PC31DOWNTO4_shadow_intermed_3 <= V_D_PC31DOWNTO4_shadow_intermed_2;
V_D_PC31DOWNTO4_shadow_intermed_4 <= V_D_PC31DOWNTO4_shadow_intermed_3;
V_D_PC31DOWNTO4_shadow_intermed_5 <= V_D_PC31DOWNTO4_shadow_intermed_4;
V_D_PC31DOWNTO4_shadow_intermed_6 <= V_D_PC31DOWNTO4_shadow_intermed_5;
V_D_PC31DOWNTO4_shadow_intermed_7 <= V_D_PC31DOWNTO4_shadow_intermed_6;
V_E_CTRL_PC31DOWNTO4_shadow_intermed_1 <= V_E_CTRL_PC31DOWNTO4_shadow;
V_E_CTRL_PC31DOWNTO4_shadow_intermed_2 <= V_E_CTRL_PC31DOWNTO4_shadow_intermed_1;
V_E_CTRL_PC31DOWNTO4_shadow_intermed_3 <= V_E_CTRL_PC31DOWNTO4_shadow_intermed_2;
V_E_CTRL_PC31DOWNTO4_shadow_intermed_4 <= V_E_CTRL_PC31DOWNTO4_shadow_intermed_3;
V_E_CTRL_PC31DOWNTO4_shadow_intermed_5 <= V_E_CTRL_PC31DOWNTO4_shadow_intermed_4;
RIN_M_CTRL_PC31DOWNTO4_intermed_1 <= RIN.M.CTRL.PC( 31 DOWNTO 4 );
RIN_M_CTRL_PC31DOWNTO4_intermed_2 <= RIN_M_CTRL_PC31DOWNTO4_intermed_1;
RIN_M_CTRL_PC31DOWNTO4_intermed_3 <= RIN_M_CTRL_PC31DOWNTO4_intermed_2;
RIN_M_CTRL_PC31DOWNTO4_intermed_4 <= RIN_M_CTRL_PC31DOWNTO4_intermed_3;
R_X_CTRL_PC31DOWNTO4_intermed_1 <= R.X.CTRL.PC( 31 DOWNTO 4 );
R_X_CTRL_PC31DOWNTO4_intermed_2 <= R_X_CTRL_PC31DOWNTO4_intermed_1;
IRIN_ADDR31DOWNTO4_intermed_1 <= IRIN.ADDR( 31 DOWNTO 4 );
IRIN_ADDR31DOWNTO4_intermed_2 <= IRIN_ADDR31DOWNTO4_intermed_1;
V_M_CTRL_PC31DOWNTO4_shadow_intermed_1 <= V_M_CTRL_PC31DOWNTO4_shadow;
V_M_CTRL_PC31DOWNTO4_shadow_intermed_2 <= V_M_CTRL_PC31DOWNTO4_shadow_intermed_1;
V_M_CTRL_PC31DOWNTO4_shadow_intermed_3 <= V_M_CTRL_PC31DOWNTO4_shadow_intermed_2;
V_M_CTRL_PC31DOWNTO4_shadow_intermed_4 <= V_M_CTRL_PC31DOWNTO4_shadow_intermed_3;
R_M_CTRL_PC31DOWNTO4_intermed_1 <= R.M.CTRL.PC( 31 DOWNTO 4 );
R_M_CTRL_PC31DOWNTO4_intermed_2 <= R_M_CTRL_PC31DOWNTO4_intermed_1;
R_M_CTRL_PC31DOWNTO4_intermed_3 <= R_M_CTRL_PC31DOWNTO4_intermed_2;
XC_TRAP_ADDRESS31DOWNTO4_shadow_intermed_1 <= XC_TRAP_ADDRESS31DOWNTO4_shadow;
RIN_D_PC31DOWNTO4_intermed_1 <= RIN.D.PC( 31 DOWNTO 4 );
RIN_D_PC31DOWNTO4_intermed_2 <= RIN_D_PC31DOWNTO4_intermed_1;
RIN_D_PC31DOWNTO4_intermed_3 <= RIN_D_PC31DOWNTO4_intermed_2;
RIN_D_PC31DOWNTO4_intermed_4 <= RIN_D_PC31DOWNTO4_intermed_3;
RIN_D_PC31DOWNTO4_intermed_5 <= RIN_D_PC31DOWNTO4_intermed_4;
RIN_D_PC31DOWNTO4_intermed_6 <= RIN_D_PC31DOWNTO4_intermed_5;
RIN_D_PC31DOWNTO4_intermed_7 <= RIN_D_PC31DOWNTO4_intermed_6;
RIN_E_CTRL_PC31DOWNTO4_intermed_1 <= RIN.E.CTRL.PC( 31 DOWNTO 4 );
RIN_E_CTRL_PC31DOWNTO4_intermed_2 <= RIN_E_CTRL_PC31DOWNTO4_intermed_1;
RIN_E_CTRL_PC31DOWNTO4_intermed_3 <= RIN_E_CTRL_PC31DOWNTO4_intermed_2;
RIN_E_CTRL_PC31DOWNTO4_intermed_4 <= RIN_E_CTRL_PC31DOWNTO4_intermed_3;
RIN_E_CTRL_PC31DOWNTO4_intermed_5 <= RIN_E_CTRL_PC31DOWNTO4_intermed_4;
EX_JUMP_ADDRESS31DOWNTO4_shadow_intermed_1 <= EX_JUMP_ADDRESS31DOWNTO4_shadow;
V_A_CTRL_PC31DOWNTO4_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO4_shadow;
V_A_CTRL_PC31DOWNTO4_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO4_shadow_intermed_1;
V_A_CTRL_PC31DOWNTO4_shadow_intermed_3 <= V_A_CTRL_PC31DOWNTO4_shadow_intermed_2;
V_A_CTRL_PC31DOWNTO4_shadow_intermed_4 <= V_A_CTRL_PC31DOWNTO4_shadow_intermed_3;
V_A_CTRL_PC31DOWNTO4_shadow_intermed_5 <= V_A_CTRL_PC31DOWNTO4_shadow_intermed_4;
V_A_CTRL_PC31DOWNTO4_shadow_intermed_6 <= V_A_CTRL_PC31DOWNTO4_shadow_intermed_5;
R_E_CTRL_PC31DOWNTO4_intermed_1 <= R.E.CTRL.PC( 31 DOWNTO 4 );
R_E_CTRL_PC31DOWNTO4_intermed_2 <= R_E_CTRL_PC31DOWNTO4_intermed_1;
R_E_CTRL_PC31DOWNTO4_intermed_3 <= R_E_CTRL_PC31DOWNTO4_intermed_2;
R_E_CTRL_PC31DOWNTO4_intermed_4 <= R_E_CTRL_PC31DOWNTO4_intermed_3;
V_X_CTRL_PC31DOWNTO4_shadow_intermed_1 <= V_X_CTRL_PC31DOWNTO4_shadow;
V_X_CTRL_PC31DOWNTO4_shadow_intermed_2 <= V_X_CTRL_PC31DOWNTO4_shadow_intermed_1;
RIN_A_CTRL_PC31DOWNTO4_intermed_1 <= RIN.A.CTRL.PC( 31 DOWNTO 4 );
RIN_A_CTRL_PC31DOWNTO4_intermed_2 <= RIN_A_CTRL_PC31DOWNTO4_intermed_1;
RIN_A_CTRL_PC31DOWNTO4_intermed_3 <= RIN_A_CTRL_PC31DOWNTO4_intermed_2;
RIN_A_CTRL_PC31DOWNTO4_intermed_4 <= RIN_A_CTRL_PC31DOWNTO4_intermed_3;
RIN_A_CTRL_PC31DOWNTO4_intermed_5 <= RIN_A_CTRL_PC31DOWNTO4_intermed_4;
R_A_CTRL_PC31DOWNTO4_intermed_1 <= R.A.CTRL.PC( 31 DOWNTO 4 );
R_A_CTRL_PC31DOWNTO4_intermed_2 <= R_A_CTRL_PC31DOWNTO4_intermed_1;
R_A_CTRL_PC31DOWNTO4_intermed_3 <= R_A_CTRL_PC31DOWNTO4_intermed_2;
R_A_CTRL_PC31DOWNTO4_intermed_4 <= R_A_CTRL_PC31DOWNTO4_intermed_3;
R_D_PC31DOWNTO4_intermed_1 <= R.D.PC( 31 DOWNTO 4 );
R_D_PC31DOWNTO4_intermed_2 <= R_D_PC31DOWNTO4_intermed_1;
R_D_PC31DOWNTO4_intermed_3 <= R_D_PC31DOWNTO4_intermed_2;
R_D_PC31DOWNTO4_intermed_4 <= R_D_PC31DOWNTO4_intermed_3;
R_D_PC31DOWNTO4_intermed_5 <= R_D_PC31DOWNTO4_intermed_4;
RIN_X_CTRL_PC31DOWNTO4_intermed_1 <= RIN.X.CTRL.PC( 31 DOWNTO 4 );
RIN_X_CTRL_PC31DOWNTO4_intermed_2 <= RIN_X_CTRL_PC31DOWNTO4_intermed_1;
V_D_PC31DOWNTO4_shadow_intermed_1 <= V_D_PC31DOWNTO4_shadow;
V_D_PC31DOWNTO4_shadow_intermed_2 <= V_D_PC31DOWNTO4_shadow_intermed_1;
V_D_PC31DOWNTO4_shadow_intermed_3 <= V_D_PC31DOWNTO4_shadow_intermed_2;
V_D_PC31DOWNTO4_shadow_intermed_4 <= V_D_PC31DOWNTO4_shadow_intermed_3;
V_D_PC31DOWNTO4_shadow_intermed_5 <= V_D_PC31DOWNTO4_shadow_intermed_4;
V_D_PC31DOWNTO4_shadow_intermed_6 <= V_D_PC31DOWNTO4_shadow_intermed_5;
V_E_CTRL_PC31DOWNTO4_shadow_intermed_1 <= V_E_CTRL_PC31DOWNTO4_shadow;
V_E_CTRL_PC31DOWNTO4_shadow_intermed_2 <= V_E_CTRL_PC31DOWNTO4_shadow_intermed_1;
V_E_CTRL_PC31DOWNTO4_shadow_intermed_3 <= V_E_CTRL_PC31DOWNTO4_shadow_intermed_2;
V_E_CTRL_PC31DOWNTO4_shadow_intermed_4 <= V_E_CTRL_PC31DOWNTO4_shadow_intermed_3;
RIN_M_CTRL_PC31DOWNTO4_intermed_1 <= RIN.M.CTRL.PC( 31 DOWNTO 4 );
RIN_M_CTRL_PC31DOWNTO4_intermed_2 <= RIN_M_CTRL_PC31DOWNTO4_intermed_1;
RIN_M_CTRL_PC31DOWNTO4_intermed_3 <= RIN_M_CTRL_PC31DOWNTO4_intermed_2;
R_X_CTRL_PC31DOWNTO4_intermed_1 <= R.X.CTRL.PC( 31 DOWNTO 4 );
IRIN_ADDR31DOWNTO4_intermed_1 <= IRIN.ADDR( 31 DOWNTO 4 );
V_M_CTRL_PC31DOWNTO4_shadow_intermed_1 <= V_M_CTRL_PC31DOWNTO4_shadow;
V_M_CTRL_PC31DOWNTO4_shadow_intermed_2 <= V_M_CTRL_PC31DOWNTO4_shadow_intermed_1;
V_M_CTRL_PC31DOWNTO4_shadow_intermed_3 <= V_M_CTRL_PC31DOWNTO4_shadow_intermed_2;
R_M_CTRL_PC31DOWNTO4_intermed_1 <= R.M.CTRL.PC( 31 DOWNTO 4 );
R_M_CTRL_PC31DOWNTO4_intermed_2 <= R_M_CTRL_PC31DOWNTO4_intermed_1;
RIN_D_PC31DOWNTO4_intermed_1 <= RIN.D.PC( 31 DOWNTO 4 );
RIN_D_PC31DOWNTO4_intermed_2 <= RIN_D_PC31DOWNTO4_intermed_1;
RIN_D_PC31DOWNTO4_intermed_3 <= RIN_D_PC31DOWNTO4_intermed_2;
RIN_D_PC31DOWNTO4_intermed_4 <= RIN_D_PC31DOWNTO4_intermed_3;
RIN_D_PC31DOWNTO4_intermed_5 <= RIN_D_PC31DOWNTO4_intermed_4;
RIN_D_PC31DOWNTO4_intermed_6 <= RIN_D_PC31DOWNTO4_intermed_5;
RIN_E_CTRL_PC31DOWNTO4_intermed_1 <= RIN.E.CTRL.PC( 31 DOWNTO 4 );
RIN_E_CTRL_PC31DOWNTO4_intermed_2 <= RIN_E_CTRL_PC31DOWNTO4_intermed_1;
RIN_E_CTRL_PC31DOWNTO4_intermed_3 <= RIN_E_CTRL_PC31DOWNTO4_intermed_2;
RIN_E_CTRL_PC31DOWNTO4_intermed_4 <= RIN_E_CTRL_PC31DOWNTO4_intermed_3;
V_A_CTRL_PC31DOWNTO4_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO4_shadow;
V_A_CTRL_PC31DOWNTO4_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO4_shadow_intermed_1;
V_A_CTRL_PC31DOWNTO4_shadow_intermed_3 <= V_A_CTRL_PC31DOWNTO4_shadow_intermed_2;
V_A_CTRL_PC31DOWNTO4_shadow_intermed_4 <= V_A_CTRL_PC31DOWNTO4_shadow_intermed_3;
V_A_CTRL_PC31DOWNTO4_shadow_intermed_5 <= V_A_CTRL_PC31DOWNTO4_shadow_intermed_4;
R_E_CTRL_PC31DOWNTO4_intermed_1 <= R.E.CTRL.PC( 31 DOWNTO 4 );
R_E_CTRL_PC31DOWNTO4_intermed_2 <= R_E_CTRL_PC31DOWNTO4_intermed_1;
R_E_CTRL_PC31DOWNTO4_intermed_3 <= R_E_CTRL_PC31DOWNTO4_intermed_2;
R_D_PC3DOWNTO2_intermed_1 <= R.D.PC( 3 DOWNTO 2 );
R_D_PC3DOWNTO2_intermed_2 <= R_D_PC3DOWNTO2_intermed_1;
R_D_PC3DOWNTO2_intermed_3 <= R_D_PC3DOWNTO2_intermed_2;
R_D_PC3DOWNTO2_intermed_4 <= R_D_PC3DOWNTO2_intermed_3;
R_D_PC3DOWNTO2_intermed_5 <= R_D_PC3DOWNTO2_intermed_4;
R_D_PC3DOWNTO2_intermed_6 <= R_D_PC3DOWNTO2_intermed_5;
V_D_PC3DOWNTO2_shadow_intermed_1 <= V_D_PC3DOWNTO2_shadow;
V_D_PC3DOWNTO2_shadow_intermed_2 <= V_D_PC3DOWNTO2_shadow_intermed_1;
V_D_PC3DOWNTO2_shadow_intermed_3 <= V_D_PC3DOWNTO2_shadow_intermed_2;
V_D_PC3DOWNTO2_shadow_intermed_4 <= V_D_PC3DOWNTO2_shadow_intermed_3;
V_D_PC3DOWNTO2_shadow_intermed_5 <= V_D_PC3DOWNTO2_shadow_intermed_4;
V_D_PC3DOWNTO2_shadow_intermed_6 <= V_D_PC3DOWNTO2_shadow_intermed_5;
V_D_PC3DOWNTO2_shadow_intermed_7 <= V_D_PC3DOWNTO2_shadow_intermed_6;
VIR_ADDR3DOWNTO2_shadow_intermed_1 <= VIR_ADDR3DOWNTO2_shadow;
VIR_ADDR3DOWNTO2_shadow_intermed_2 <= VIR_ADDR3DOWNTO2_shadow_intermed_1;
RIN_D_PC3DOWNTO2_intermed_1 <= RIN.D.PC( 3 DOWNTO 2 );
RIN_D_PC3DOWNTO2_intermed_2 <= RIN_D_PC3DOWNTO2_intermed_1;
RIN_D_PC3DOWNTO2_intermed_3 <= RIN_D_PC3DOWNTO2_intermed_2;
RIN_D_PC3DOWNTO2_intermed_4 <= RIN_D_PC3DOWNTO2_intermed_3;
RIN_D_PC3DOWNTO2_intermed_5 <= RIN_D_PC3DOWNTO2_intermed_4;
RIN_D_PC3DOWNTO2_intermed_6 <= RIN_D_PC3DOWNTO2_intermed_5;
RIN_D_PC3DOWNTO2_intermed_7 <= RIN_D_PC3DOWNTO2_intermed_6;
R_M_CTRL_PC3DOWNTO2_intermed_1 <= R.M.CTRL.PC( 3 DOWNTO 2 );
R_M_CTRL_PC3DOWNTO2_intermed_2 <= R_M_CTRL_PC3DOWNTO2_intermed_1;
R_M_CTRL_PC3DOWNTO2_intermed_3 <= R_M_CTRL_PC3DOWNTO2_intermed_2;
R_E_CTRL_PC3DOWNTO2_intermed_1 <= R.E.CTRL.PC( 3 DOWNTO 2 );
R_E_CTRL_PC3DOWNTO2_intermed_2 <= R_E_CTRL_PC3DOWNTO2_intermed_1;
R_E_CTRL_PC3DOWNTO2_intermed_3 <= R_E_CTRL_PC3DOWNTO2_intermed_2;
R_E_CTRL_PC3DOWNTO2_intermed_4 <= R_E_CTRL_PC3DOWNTO2_intermed_3;
V_E_CTRL_PC3DOWNTO2_shadow_intermed_1 <= V_E_CTRL_PC3DOWNTO2_shadow;
V_E_CTRL_PC3DOWNTO2_shadow_intermed_2 <= V_E_CTRL_PC3DOWNTO2_shadow_intermed_1;
V_E_CTRL_PC3DOWNTO2_shadow_intermed_3 <= V_E_CTRL_PC3DOWNTO2_shadow_intermed_2;
V_E_CTRL_PC3DOWNTO2_shadow_intermed_4 <= V_E_CTRL_PC3DOWNTO2_shadow_intermed_3;
V_E_CTRL_PC3DOWNTO2_shadow_intermed_5 <= V_E_CTRL_PC3DOWNTO2_shadow_intermed_4;
RIN_X_CTRL_PC3DOWNTO2_intermed_1 <= RIN.X.CTRL.PC( 3 DOWNTO 2 );
RIN_X_CTRL_PC3DOWNTO2_intermed_2 <= RIN_X_CTRL_PC3DOWNTO2_intermed_1;
RIN_X_CTRL_PC3DOWNTO2_intermed_3 <= RIN_X_CTRL_PC3DOWNTO2_intermed_2;
R_A_CTRL_PC3DOWNTO2_intermed_1 <= R.A.CTRL.PC( 3 DOWNTO 2 );
R_A_CTRL_PC3DOWNTO2_intermed_2 <= R_A_CTRL_PC3DOWNTO2_intermed_1;
R_A_CTRL_PC3DOWNTO2_intermed_3 <= R_A_CTRL_PC3DOWNTO2_intermed_2;
R_A_CTRL_PC3DOWNTO2_intermed_4 <= R_A_CTRL_PC3DOWNTO2_intermed_3;
R_A_CTRL_PC3DOWNTO2_intermed_5 <= R_A_CTRL_PC3DOWNTO2_intermed_4;
V_X_CTRL_PC3DOWNTO2_shadow_intermed_1 <= V_X_CTRL_PC3DOWNTO2_shadow;
V_X_CTRL_PC3DOWNTO2_shadow_intermed_2 <= V_X_CTRL_PC3DOWNTO2_shadow_intermed_1;
V_X_CTRL_PC3DOWNTO2_shadow_intermed_3 <= V_X_CTRL_PC3DOWNTO2_shadow_intermed_2;
RIN_M_CTRL_PC3DOWNTO2_intermed_1 <= RIN.M.CTRL.PC( 3 DOWNTO 2 );
RIN_M_CTRL_PC3DOWNTO2_intermed_2 <= RIN_M_CTRL_PC3DOWNTO2_intermed_1;
RIN_M_CTRL_PC3DOWNTO2_intermed_3 <= RIN_M_CTRL_PC3DOWNTO2_intermed_2;
RIN_M_CTRL_PC3DOWNTO2_intermed_4 <= RIN_M_CTRL_PC3DOWNTO2_intermed_3;
IRIN_ADDR3DOWNTO2_intermed_1 <= IRIN.ADDR( 3 DOWNTO 2 );
IRIN_ADDR3DOWNTO2_intermed_2 <= IRIN_ADDR3DOWNTO2_intermed_1;
EX_JUMP_ADDRESS3DOWNTO2_shadow_intermed_1 <= EX_JUMP_ADDRESS3DOWNTO2_shadow;
EX_ADD_RES32DOWNTO34DOWNTO3_shadow_intermed_1 <= EX_ADD_RES32DOWNTO34DOWNTO3_shadow;
RIN_A_CTRL_PC3DOWNTO2_intermed_1 <= RIN.A.CTRL.PC( 3 DOWNTO 2 );
RIN_A_CTRL_PC3DOWNTO2_intermed_2 <= RIN_A_CTRL_PC3DOWNTO2_intermed_1;
RIN_A_CTRL_PC3DOWNTO2_intermed_3 <= RIN_A_CTRL_PC3DOWNTO2_intermed_2;
RIN_A_CTRL_PC3DOWNTO2_intermed_4 <= RIN_A_CTRL_PC3DOWNTO2_intermed_3;
RIN_A_CTRL_PC3DOWNTO2_intermed_5 <= RIN_A_CTRL_PC3DOWNTO2_intermed_4;
RIN_A_CTRL_PC3DOWNTO2_intermed_6 <= RIN_A_CTRL_PC3DOWNTO2_intermed_5;
XC_TRAP_ADDRESS3DOWNTO2_shadow_intermed_1 <= XC_TRAP_ADDRESS3DOWNTO2_shadow;
V_A_CTRL_PC3DOWNTO2_shadow_intermed_1 <= V_A_CTRL_PC3DOWNTO2_shadow;
V_A_CTRL_PC3DOWNTO2_shadow_intermed_2 <= V_A_CTRL_PC3DOWNTO2_shadow_intermed_1;
V_A_CTRL_PC3DOWNTO2_shadow_intermed_3 <= V_A_CTRL_PC3DOWNTO2_shadow_intermed_2;
V_A_CTRL_PC3DOWNTO2_shadow_intermed_4 <= V_A_CTRL_PC3DOWNTO2_shadow_intermed_3;
V_A_CTRL_PC3DOWNTO2_shadow_intermed_5 <= V_A_CTRL_PC3DOWNTO2_shadow_intermed_4;
V_A_CTRL_PC3DOWNTO2_shadow_intermed_6 <= V_A_CTRL_PC3DOWNTO2_shadow_intermed_5;
IR_ADDR3DOWNTO2_intermed_1 <= IR.ADDR( 3 DOWNTO 2 );
V_M_CTRL_PC3DOWNTO2_shadow_intermed_1 <= V_M_CTRL_PC3DOWNTO2_shadow;
V_M_CTRL_PC3DOWNTO2_shadow_intermed_2 <= V_M_CTRL_PC3DOWNTO2_shadow_intermed_1;
V_M_CTRL_PC3DOWNTO2_shadow_intermed_3 <= V_M_CTRL_PC3DOWNTO2_shadow_intermed_2;
V_M_CTRL_PC3DOWNTO2_shadow_intermed_4 <= V_M_CTRL_PC3DOWNTO2_shadow_intermed_3;
R_X_CTRL_PC3DOWNTO2_intermed_1 <= R.X.CTRL.PC( 3 DOWNTO 2 );
R_X_CTRL_PC3DOWNTO2_intermed_2 <= R_X_CTRL_PC3DOWNTO2_intermed_1;
RIN_E_CTRL_PC3DOWNTO2_intermed_1 <= RIN.E.CTRL.PC( 3 DOWNTO 2 );
RIN_E_CTRL_PC3DOWNTO2_intermed_2 <= RIN_E_CTRL_PC3DOWNTO2_intermed_1;
RIN_E_CTRL_PC3DOWNTO2_intermed_3 <= RIN_E_CTRL_PC3DOWNTO2_intermed_2;
RIN_E_CTRL_PC3DOWNTO2_intermed_4 <= RIN_E_CTRL_PC3DOWNTO2_intermed_3;
RIN_E_CTRL_PC3DOWNTO2_intermed_5 <= RIN_E_CTRL_PC3DOWNTO2_intermed_4;
RIN_F_PC3DOWNTO2_intermed_1 <= RIN.F.PC( 3 DOWNTO 2 );
R_D_PC3DOWNTO2_intermed_1 <= R.D.PC( 3 DOWNTO 2 );
R_D_PC3DOWNTO2_intermed_2 <= R_D_PC3DOWNTO2_intermed_1;
R_D_PC3DOWNTO2_intermed_3 <= R_D_PC3DOWNTO2_intermed_2;
R_D_PC3DOWNTO2_intermed_4 <= R_D_PC3DOWNTO2_intermed_3;
R_D_PC3DOWNTO2_intermed_5 <= R_D_PC3DOWNTO2_intermed_4;
V_D_PC3DOWNTO2_shadow_intermed_1 <= V_D_PC3DOWNTO2_shadow;
V_D_PC3DOWNTO2_shadow_intermed_2 <= V_D_PC3DOWNTO2_shadow_intermed_1;
V_D_PC3DOWNTO2_shadow_intermed_3 <= V_D_PC3DOWNTO2_shadow_intermed_2;
V_D_PC3DOWNTO2_shadow_intermed_4 <= V_D_PC3DOWNTO2_shadow_intermed_3;
V_D_PC3DOWNTO2_shadow_intermed_5 <= V_D_PC3DOWNTO2_shadow_intermed_4;
V_D_PC3DOWNTO2_shadow_intermed_6 <= V_D_PC3DOWNTO2_shadow_intermed_5;
RIN_D_PC3DOWNTO2_intermed_1 <= RIN.D.PC( 3 DOWNTO 2 );
RIN_D_PC3DOWNTO2_intermed_2 <= RIN_D_PC3DOWNTO2_intermed_1;
RIN_D_PC3DOWNTO2_intermed_3 <= RIN_D_PC3DOWNTO2_intermed_2;
RIN_D_PC3DOWNTO2_intermed_4 <= RIN_D_PC3DOWNTO2_intermed_3;
RIN_D_PC3DOWNTO2_intermed_5 <= RIN_D_PC3DOWNTO2_intermed_4;
RIN_D_PC3DOWNTO2_intermed_6 <= RIN_D_PC3DOWNTO2_intermed_5;
R_M_CTRL_PC3DOWNTO2_intermed_1 <= R.M.CTRL.PC( 3 DOWNTO 2 );
R_M_CTRL_PC3DOWNTO2_intermed_2 <= R_M_CTRL_PC3DOWNTO2_intermed_1;
R_E_CTRL_PC3DOWNTO2_intermed_1 <= R.E.CTRL.PC( 3 DOWNTO 2 );
R_E_CTRL_PC3DOWNTO2_intermed_2 <= R_E_CTRL_PC3DOWNTO2_intermed_1;
R_E_CTRL_PC3DOWNTO2_intermed_3 <= R_E_CTRL_PC3DOWNTO2_intermed_2;
V_E_CTRL_PC3DOWNTO2_shadow_intermed_1 <= V_E_CTRL_PC3DOWNTO2_shadow;
V_E_CTRL_PC3DOWNTO2_shadow_intermed_2 <= V_E_CTRL_PC3DOWNTO2_shadow_intermed_1;
V_E_CTRL_PC3DOWNTO2_shadow_intermed_3 <= V_E_CTRL_PC3DOWNTO2_shadow_intermed_2;
V_E_CTRL_PC3DOWNTO2_shadow_intermed_4 <= V_E_CTRL_PC3DOWNTO2_shadow_intermed_3;
RIN_X_CTRL_PC3DOWNTO2_intermed_1 <= RIN.X.CTRL.PC( 3 DOWNTO 2 );
RIN_X_CTRL_PC3DOWNTO2_intermed_2 <= RIN_X_CTRL_PC3DOWNTO2_intermed_1;
R_A_CTRL_PC3DOWNTO2_intermed_1 <= R.A.CTRL.PC( 3 DOWNTO 2 );
R_A_CTRL_PC3DOWNTO2_intermed_2 <= R_A_CTRL_PC3DOWNTO2_intermed_1;
R_A_CTRL_PC3DOWNTO2_intermed_3 <= R_A_CTRL_PC3DOWNTO2_intermed_2;
R_A_CTRL_PC3DOWNTO2_intermed_4 <= R_A_CTRL_PC3DOWNTO2_intermed_3;
V_X_CTRL_PC3DOWNTO2_shadow_intermed_1 <= V_X_CTRL_PC3DOWNTO2_shadow;
V_X_CTRL_PC3DOWNTO2_shadow_intermed_2 <= V_X_CTRL_PC3DOWNTO2_shadow_intermed_1;
RIN_M_CTRL_PC3DOWNTO2_intermed_1 <= RIN.M.CTRL.PC( 3 DOWNTO 2 );
RIN_M_CTRL_PC3DOWNTO2_intermed_2 <= RIN_M_CTRL_PC3DOWNTO2_intermed_1;
RIN_M_CTRL_PC3DOWNTO2_intermed_3 <= RIN_M_CTRL_PC3DOWNTO2_intermed_2;
IRIN_ADDR3DOWNTO2_intermed_1 <= IRIN.ADDR( 3 DOWNTO 2 );
RIN_A_CTRL_PC3DOWNTO2_intermed_1 <= RIN.A.CTRL.PC( 3 DOWNTO 2 );
RIN_A_CTRL_PC3DOWNTO2_intermed_2 <= RIN_A_CTRL_PC3DOWNTO2_intermed_1;
RIN_A_CTRL_PC3DOWNTO2_intermed_3 <= RIN_A_CTRL_PC3DOWNTO2_intermed_2;
RIN_A_CTRL_PC3DOWNTO2_intermed_4 <= RIN_A_CTRL_PC3DOWNTO2_intermed_3;
RIN_A_CTRL_PC3DOWNTO2_intermed_5 <= RIN_A_CTRL_PC3DOWNTO2_intermed_4;
V_A_CTRL_PC3DOWNTO2_shadow_intermed_1 <= V_A_CTRL_PC3DOWNTO2_shadow;
V_A_CTRL_PC3DOWNTO2_shadow_intermed_2 <= V_A_CTRL_PC3DOWNTO2_shadow_intermed_1;
V_A_CTRL_PC3DOWNTO2_shadow_intermed_3 <= V_A_CTRL_PC3DOWNTO2_shadow_intermed_2;
V_A_CTRL_PC3DOWNTO2_shadow_intermed_4 <= V_A_CTRL_PC3DOWNTO2_shadow_intermed_3;
V_A_CTRL_PC3DOWNTO2_shadow_intermed_5 <= V_A_CTRL_PC3DOWNTO2_shadow_intermed_4;
V_M_CTRL_PC3DOWNTO2_shadow_intermed_1 <= V_M_CTRL_PC3DOWNTO2_shadow;
V_M_CTRL_PC3DOWNTO2_shadow_intermed_2 <= V_M_CTRL_PC3DOWNTO2_shadow_intermed_1;
V_M_CTRL_PC3DOWNTO2_shadow_intermed_3 <= V_M_CTRL_PC3DOWNTO2_shadow_intermed_2;
R_X_CTRL_PC3DOWNTO2_intermed_1 <= R.X.CTRL.PC( 3 DOWNTO 2 );
RIN_E_CTRL_PC3DOWNTO2_intermed_1 <= RIN.E.CTRL.PC( 3 DOWNTO 2 );
RIN_E_CTRL_PC3DOWNTO2_intermed_2 <= RIN_E_CTRL_PC3DOWNTO2_intermed_1;
RIN_E_CTRL_PC3DOWNTO2_intermed_3 <= RIN_E_CTRL_PC3DOWNTO2_intermed_2;
RIN_E_CTRL_PC3DOWNTO2_intermed_4 <= RIN_E_CTRL_PC3DOWNTO2_intermed_3;
RIN_E_CTRL_RD6DOWNTO0_intermed_1 <= RIN.E.CTRL.RD( 6 DOWNTO 0 );
RIN_E_CTRL_RD6DOWNTO0_intermed_2 <= RIN_E_CTRL_RD6DOWNTO0_intermed_1;
RIN_E_CTRL_RD6DOWNTO0_intermed_3 <= RIN_E_CTRL_RD6DOWNTO0_intermed_2;
RIN_M_CTRL_RD6DOWNTO0_intermed_1 <= RIN.M.CTRL.RD( 6 DOWNTO 0 );
RIN_M_CTRL_RD6DOWNTO0_intermed_2 <= RIN_M_CTRL_RD6DOWNTO0_intermed_1;
RIN_X_CTRL_RD6DOWNTO0_intermed_1 <= RIN.X.CTRL.RD( 6 DOWNTO 0 );
V_M_CTRL_RD6DOWNTO0_shadow_intermed_1 <= V_M_CTRL_RD6DOWNTO0_shadow;
V_M_CTRL_RD6DOWNTO0_shadow_intermed_2 <= V_M_CTRL_RD6DOWNTO0_shadow_intermed_1;
R_E_CTRL_RD6DOWNTO0_intermed_1 <= R.E.CTRL.RD( 6 DOWNTO 0 );
R_E_CTRL_RD6DOWNTO0_intermed_2 <= R_E_CTRL_RD6DOWNTO0_intermed_1;
V_E_CTRL_RD6DOWNTO0_shadow_intermed_1 <= V_E_CTRL_RD6DOWNTO0_shadow;
V_E_CTRL_RD6DOWNTO0_shadow_intermed_2 <= V_E_CTRL_RD6DOWNTO0_shadow_intermed_1;
V_E_CTRL_RD6DOWNTO0_shadow_intermed_3 <= V_E_CTRL_RD6DOWNTO0_shadow_intermed_2;
V_A_CTRL_RD6DOWNTO0_shadow_intermed_1 <= V_A_CTRL_RD6DOWNTO0_shadow;
V_A_CTRL_RD6DOWNTO0_shadow_intermed_2 <= V_A_CTRL_RD6DOWNTO0_shadow_intermed_1;
V_A_CTRL_RD6DOWNTO0_shadow_intermed_3 <= V_A_CTRL_RD6DOWNTO0_shadow_intermed_2;
V_A_CTRL_RD6DOWNTO0_shadow_intermed_4 <= V_A_CTRL_RD6DOWNTO0_shadow_intermed_3;
R_A_CTRL_RD6DOWNTO0_intermed_1 <= R.A.CTRL.RD( 6 DOWNTO 0 );
R_A_CTRL_RD6DOWNTO0_intermed_2 <= R_A_CTRL_RD6DOWNTO0_intermed_1;
R_A_CTRL_RD6DOWNTO0_intermed_3 <= R_A_CTRL_RD6DOWNTO0_intermed_2;
RIN_A_CTRL_RD6DOWNTO0_intermed_1 <= RIN.A.CTRL.RD( 6 DOWNTO 0 );
RIN_A_CTRL_RD6DOWNTO0_intermed_2 <= RIN_A_CTRL_RD6DOWNTO0_intermed_1;
RIN_A_CTRL_RD6DOWNTO0_intermed_3 <= RIN_A_CTRL_RD6DOWNTO0_intermed_2;
RIN_A_CTRL_RD6DOWNTO0_intermed_4 <= RIN_A_CTRL_RD6DOWNTO0_intermed_3;
R_M_CTRL_RD6DOWNTO0_intermed_1 <= R.M.CTRL.RD( 6 DOWNTO 0 );
V_E_CTRL_TT_shadow_intermed_1 <= V_E_CTRL_TT_shadow;
V_E_CTRL_TT_shadow_intermed_2 <= V_E_CTRL_TT_shadow_intermed_1;
RIN_A_CTRL_TT_intermed_1 <= RIN.A.CTRL.TT;
RIN_A_CTRL_TT_intermed_2 <= RIN_A_CTRL_TT_intermed_1;
RIN_A_CTRL_TT_intermed_3 <= RIN_A_CTRL_TT_intermed_2;
R_A_CTRL_TT_intermed_1 <= R.A.CTRL.TT;
R_A_CTRL_TT_intermed_2 <= R_A_CTRL_TT_intermed_1;
R_E_CTRL_TT_intermed_1 <= R.E.CTRL.TT;
RIN_M_CTRL_TT_intermed_1 <= RIN.M.CTRL.TT;
RIN_E_CTRL_TT_intermed_1 <= RIN.E.CTRL.TT;
RIN_E_CTRL_TT_intermed_2 <= RIN_E_CTRL_TT_intermed_1;
V_A_CTRL_TT_shadow_intermed_1 <= V_A_CTRL_TT_shadow;
V_A_CTRL_TT_shadow_intermed_2 <= V_A_CTRL_TT_shadow_intermed_1;
V_A_CTRL_TT_shadow_intermed_3 <= V_A_CTRL_TT_shadow_intermed_2;
R_A_CTRL_LD_intermed_1 <= R.A.CTRL.LD;
RIN_A_CTRL_LD_intermed_1 <= RIN.A.CTRL.LD;
RIN_A_CTRL_LD_intermed_2 <= RIN_A_CTRL_LD_intermed_1;
RIN_E_CTRL_LD_intermed_1 <= RIN.E.CTRL.LD;
V_A_CTRL_LD_shadow_intermed_1 <= V_A_CTRL_LD_shadow;
V_A_CTRL_LD_shadow_intermed_2 <= V_A_CTRL_LD_shadow_intermed_1;
R_D_INST04DOWNTO0_intermed_1 <= R.D.INST( 0 )( 4 DOWNTO 0 );
V_D_INST04DOWNTO0_shadow_intermed_1 <= V_D_INST04DOWNTO0_shadow;
V_D_INST04DOWNTO0_shadow_intermed_2 <= V_D_INST04DOWNTO0_shadow_intermed_1;
RIN_D_INST04DOWNTO0_intermed_1 <= RIN.D.INST ( 0 )( 4 DOWNTO 0 );
RIN_D_INST04DOWNTO0_intermed_1 <= RIN.D.INST( 0 )( 4 DOWNTO 0 );
RIN_D_INST04DOWNTO0_intermed_2 <= RIN_D_INST04DOWNTO0_intermed_1;
R_M_CTRL_PC31DOWNTO12_intermed_1 <= R.M.CTRL.PC( 31 DOWNTO 12 );
R_M_CTRL_PC31DOWNTO12_intermed_2 <= R_M_CTRL_PC31DOWNTO12_intermed_1;
R_M_CTRL_PC31DOWNTO12_intermed_3 <= R_M_CTRL_PC31DOWNTO12_intermed_2;
V_D_PC31DOWNTO12_shadow_intermed_1 <= V_D_PC31DOWNTO12_shadow;
V_D_PC31DOWNTO12_shadow_intermed_2 <= V_D_PC31DOWNTO12_shadow_intermed_1;
V_D_PC31DOWNTO12_shadow_intermed_3 <= V_D_PC31DOWNTO12_shadow_intermed_2;
V_D_PC31DOWNTO12_shadow_intermed_4 <= V_D_PC31DOWNTO12_shadow_intermed_3;
V_D_PC31DOWNTO12_shadow_intermed_5 <= V_D_PC31DOWNTO12_shadow_intermed_4;
V_D_PC31DOWNTO12_shadow_intermed_6 <= V_D_PC31DOWNTO12_shadow_intermed_5;
V_D_PC31DOWNTO12_shadow_intermed_7 <= V_D_PC31DOWNTO12_shadow_intermed_6;
V_A_CTRL_PC31DOWNTO12_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO12_shadow;
V_A_CTRL_PC31DOWNTO12_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO12_shadow_intermed_1;
V_A_CTRL_PC31DOWNTO12_shadow_intermed_3 <= V_A_CTRL_PC31DOWNTO12_shadow_intermed_2;
V_A_CTRL_PC31DOWNTO12_shadow_intermed_4 <= V_A_CTRL_PC31DOWNTO12_shadow_intermed_3;
V_A_CTRL_PC31DOWNTO12_shadow_intermed_5 <= V_A_CTRL_PC31DOWNTO12_shadow_intermed_4;
V_A_CTRL_PC31DOWNTO12_shadow_intermed_6 <= V_A_CTRL_PC31DOWNTO12_shadow_intermed_5;
V_E_CTRL_PC31DOWNTO12_shadow_intermed_1 <= V_E_CTRL_PC31DOWNTO12_shadow;
V_E_CTRL_PC31DOWNTO12_shadow_intermed_2 <= V_E_CTRL_PC31DOWNTO12_shadow_intermed_1;
V_E_CTRL_PC31DOWNTO12_shadow_intermed_3 <= V_E_CTRL_PC31DOWNTO12_shadow_intermed_2;
V_E_CTRL_PC31DOWNTO12_shadow_intermed_4 <= V_E_CTRL_PC31DOWNTO12_shadow_intermed_3;
V_E_CTRL_PC31DOWNTO12_shadow_intermed_5 <= V_E_CTRL_PC31DOWNTO12_shadow_intermed_4;
EX_ADD_RES32DOWNTO330DOWNTO11_shadow_intermed_1 <= EX_ADD_RES32DOWNTO330DOWNTO11_shadow;
RIN_F_PC31DOWNTO12_intermed_1 <= RIN.F.PC( 31 DOWNTO 12 );
R_A_CTRL_PC31DOWNTO12_intermed_1 <= R.A.CTRL.PC( 31 DOWNTO 12 );
R_A_CTRL_PC31DOWNTO12_intermed_2 <= R_A_CTRL_PC31DOWNTO12_intermed_1;
R_A_CTRL_PC31DOWNTO12_intermed_3 <= R_A_CTRL_PC31DOWNTO12_intermed_2;
R_A_CTRL_PC31DOWNTO12_intermed_4 <= R_A_CTRL_PC31DOWNTO12_intermed_3;
R_A_CTRL_PC31DOWNTO12_intermed_5 <= R_A_CTRL_PC31DOWNTO12_intermed_4;
R_E_CTRL_PC31DOWNTO12_intermed_1 <= R.E.CTRL.PC( 31 DOWNTO 12 );
R_E_CTRL_PC31DOWNTO12_intermed_2 <= R_E_CTRL_PC31DOWNTO12_intermed_1;
R_E_CTRL_PC31DOWNTO12_intermed_3 <= R_E_CTRL_PC31DOWNTO12_intermed_2;
R_E_CTRL_PC31DOWNTO12_intermed_4 <= R_E_CTRL_PC31DOWNTO12_intermed_3;
EX_JUMP_ADDRESS31DOWNTO12_shadow_intermed_1 <= EX_JUMP_ADDRESS31DOWNTO12_shadow;
RIN_A_CTRL_PC31DOWNTO12_intermed_1 <= RIN.A.CTRL.PC( 31 DOWNTO 12 );
RIN_A_CTRL_PC31DOWNTO12_intermed_2 <= RIN_A_CTRL_PC31DOWNTO12_intermed_1;
RIN_A_CTRL_PC31DOWNTO12_intermed_3 <= RIN_A_CTRL_PC31DOWNTO12_intermed_2;
RIN_A_CTRL_PC31DOWNTO12_intermed_4 <= RIN_A_CTRL_PC31DOWNTO12_intermed_3;
RIN_A_CTRL_PC31DOWNTO12_intermed_5 <= RIN_A_CTRL_PC31DOWNTO12_intermed_4;
RIN_A_CTRL_PC31DOWNTO12_intermed_6 <= RIN_A_CTRL_PC31DOWNTO12_intermed_5;
RIN_E_CTRL_PC31DOWNTO12_intermed_1 <= RIN.E.CTRL.PC( 31 DOWNTO 12 );
RIN_E_CTRL_PC31DOWNTO12_intermed_2 <= RIN_E_CTRL_PC31DOWNTO12_intermed_1;
RIN_E_CTRL_PC31DOWNTO12_intermed_3 <= RIN_E_CTRL_PC31DOWNTO12_intermed_2;
RIN_E_CTRL_PC31DOWNTO12_intermed_4 <= RIN_E_CTRL_PC31DOWNTO12_intermed_3;
RIN_E_CTRL_PC31DOWNTO12_intermed_5 <= RIN_E_CTRL_PC31DOWNTO12_intermed_4;
IRIN_ADDR31DOWNTO12_intermed_1 <= IRIN.ADDR( 31 DOWNTO 12 );
IRIN_ADDR31DOWNTO12_intermed_2 <= IRIN_ADDR31DOWNTO12_intermed_1;
V_X_CTRL_PC31DOWNTO12_shadow_intermed_1 <= V_X_CTRL_PC31DOWNTO12_shadow;
V_X_CTRL_PC31DOWNTO12_shadow_intermed_2 <= V_X_CTRL_PC31DOWNTO12_shadow_intermed_1;
V_X_CTRL_PC31DOWNTO12_shadow_intermed_3 <= V_X_CTRL_PC31DOWNTO12_shadow_intermed_2;
EX_ADD_RES32DOWNTO332DOWNTO13_shadow_intermed_1 <= EX_ADD_RES32DOWNTO332DOWNTO13_shadow;
XC_TRAP_ADDRESS31DOWNTO12_shadow_intermed_1 <= XC_TRAP_ADDRESS31DOWNTO12_shadow;
RIN_M_CTRL_PC31DOWNTO12_intermed_1 <= RIN.M.CTRL.PC( 31 DOWNTO 12 );
RIN_M_CTRL_PC31DOWNTO12_intermed_2 <= RIN_M_CTRL_PC31DOWNTO12_intermed_1;
RIN_M_CTRL_PC31DOWNTO12_intermed_3 <= RIN_M_CTRL_PC31DOWNTO12_intermed_2;
RIN_M_CTRL_PC31DOWNTO12_intermed_4 <= RIN_M_CTRL_PC31DOWNTO12_intermed_3;
IR_ADDR31DOWNTO12_intermed_1 <= IR.ADDR( 31 DOWNTO 12 );
R_X_CTRL_PC31DOWNTO12_intermed_1 <= R.X.CTRL.PC( 31 DOWNTO 12 );
R_X_CTRL_PC31DOWNTO12_intermed_2 <= R_X_CTRL_PC31DOWNTO12_intermed_1;
R_D_PC31DOWNTO12_intermed_1 <= R.D.PC( 31 DOWNTO 12 );
R_D_PC31DOWNTO12_intermed_2 <= R_D_PC31DOWNTO12_intermed_1;
R_D_PC31DOWNTO12_intermed_3 <= R_D_PC31DOWNTO12_intermed_2;
R_D_PC31DOWNTO12_intermed_4 <= R_D_PC31DOWNTO12_intermed_3;
R_D_PC31DOWNTO12_intermed_5 <= R_D_PC31DOWNTO12_intermed_4;
R_D_PC31DOWNTO12_intermed_6 <= R_D_PC31DOWNTO12_intermed_5;
RIN_X_CTRL_PC31DOWNTO12_intermed_1 <= RIN.X.CTRL.PC( 31 DOWNTO 12 );
RIN_X_CTRL_PC31DOWNTO12_intermed_2 <= RIN_X_CTRL_PC31DOWNTO12_intermed_1;
RIN_X_CTRL_PC31DOWNTO12_intermed_3 <= RIN_X_CTRL_PC31DOWNTO12_intermed_2;
RIN_D_PC31DOWNTO12_intermed_1 <= RIN.D.PC( 31 DOWNTO 12 );
RIN_D_PC31DOWNTO12_intermed_2 <= RIN_D_PC31DOWNTO12_intermed_1;
RIN_D_PC31DOWNTO12_intermed_3 <= RIN_D_PC31DOWNTO12_intermed_2;
RIN_D_PC31DOWNTO12_intermed_4 <= RIN_D_PC31DOWNTO12_intermed_3;
RIN_D_PC31DOWNTO12_intermed_5 <= RIN_D_PC31DOWNTO12_intermed_4;
RIN_D_PC31DOWNTO12_intermed_6 <= RIN_D_PC31DOWNTO12_intermed_5;
RIN_D_PC31DOWNTO12_intermed_7 <= RIN_D_PC31DOWNTO12_intermed_6;
VIR_ADDR31DOWNTO12_shadow_intermed_1 <= VIR_ADDR31DOWNTO12_shadow;
VIR_ADDR31DOWNTO12_shadow_intermed_2 <= VIR_ADDR31DOWNTO12_shadow_intermed_1;
V_M_CTRL_PC31DOWNTO12_shadow_intermed_1 <= V_M_CTRL_PC31DOWNTO12_shadow;
V_M_CTRL_PC31DOWNTO12_shadow_intermed_2 <= V_M_CTRL_PC31DOWNTO12_shadow_intermed_1;
V_M_CTRL_PC31DOWNTO12_shadow_intermed_3 <= V_M_CTRL_PC31DOWNTO12_shadow_intermed_2;
V_M_CTRL_PC31DOWNTO12_shadow_intermed_4 <= V_M_CTRL_PC31DOWNTO12_shadow_intermed_3;
V_X_CTRL_TT3DOWNTO0_shadow_intermed_1 <= V_X_CTRL_TT3DOWNTO0_shadow;
R_M_CTRL_TT3DOWNTO0_intermed_1 <= R.M.CTRL.TT( 3 DOWNTO 0 );
V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_1 <= V_X_RESULT6DOWNTO03DOWNTO0_shadow;
V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_2 <= V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_1;
R_X_RESULT6DOWNTO03DOWNTO0_intermed_1 <= R.X.RESULT( 6 DOWNTO 0 )( 3 DOWNTO 0 );
R_A_CTRL_TT3DOWNTO0_intermed_1 <= R.A.CTRL.TT( 3 DOWNTO 0 );
R_A_CTRL_TT3DOWNTO0_intermed_2 <= R_A_CTRL_TT3DOWNTO0_intermed_1;
R_A_CTRL_TT3DOWNTO0_intermed_3 <= R_A_CTRL_TT3DOWNTO0_intermed_2;
RIN_A_CTRL_TT3DOWNTO0_intermed_1 <= RIN.A.CTRL.TT( 3 DOWNTO 0 );
RIN_A_CTRL_TT3DOWNTO0_intermed_2 <= RIN_A_CTRL_TT3DOWNTO0_intermed_1;
RIN_A_CTRL_TT3DOWNTO0_intermed_3 <= RIN_A_CTRL_TT3DOWNTO0_intermed_2;
RIN_A_CTRL_TT3DOWNTO0_intermed_4 <= RIN_A_CTRL_TT3DOWNTO0_intermed_3;
V_A_CTRL_TT3DOWNTO0_shadow_intermed_1 <= V_A_CTRL_TT3DOWNTO0_shadow;
V_A_CTRL_TT3DOWNTO0_shadow_intermed_2 <= V_A_CTRL_TT3DOWNTO0_shadow_intermed_1;
V_A_CTRL_TT3DOWNTO0_shadow_intermed_3 <= V_A_CTRL_TT3DOWNTO0_shadow_intermed_2;
V_A_CTRL_TT3DOWNTO0_shadow_intermed_4 <= V_A_CTRL_TT3DOWNTO0_shadow_intermed_3;
R_E_CTRL_TT3DOWNTO0_intermed_1 <= R.E.CTRL.TT( 3 DOWNTO 0 );
R_E_CTRL_TT3DOWNTO0_intermed_2 <= R_E_CTRL_TT3DOWNTO0_intermed_1;
RIN_M_CTRL_TT3DOWNTO0_intermed_1 <= RIN.M.CTRL.TT( 3 DOWNTO 0 );
RIN_M_CTRL_TT3DOWNTO0_intermed_2 <= RIN_M_CTRL_TT3DOWNTO0_intermed_1;
V_M_CTRL_TT3DOWNTO0_shadow_intermed_1 <= V_M_CTRL_TT3DOWNTO0_shadow;
V_M_CTRL_TT3DOWNTO0_shadow_intermed_2 <= V_M_CTRL_TT3DOWNTO0_shadow_intermed_1;
RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_1 <= RIN.X.RESULT( 6 DOWNTO 0 )( 3 DOWNTO 0 );
RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_2 <= RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_1;
RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_1 <= RIN.X.RESULT ( 6 DOWNTO 0 )( 3 DOWNTO 0 );
V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_1 <= V_X_RESULT6DOWNTO03DOWNTO0_shadow;
V_E_CTRL_TT3DOWNTO0_shadow_intermed_1 <= V_E_CTRL_TT3DOWNTO0_shadow;
V_E_CTRL_TT3DOWNTO0_shadow_intermed_2 <= V_E_CTRL_TT3DOWNTO0_shadow_intermed_1;
V_E_CTRL_TT3DOWNTO0_shadow_intermed_3 <= V_E_CTRL_TT3DOWNTO0_shadow_intermed_2;
RIN_X_CTRL_TT3DOWNTO0_intermed_1 <= RIN.X.CTRL.TT( 3 DOWNTO 0 );
RIN_E_CTRL_TT3DOWNTO0_intermed_1 <= RIN.E.CTRL.TT( 3 DOWNTO 0 );
RIN_E_CTRL_TT3DOWNTO0_intermed_2 <= RIN_E_CTRL_TT3DOWNTO0_intermed_1;
RIN_E_CTRL_TT3DOWNTO0_intermed_3 <= RIN_E_CTRL_TT3DOWNTO0_intermed_2;
V_X_CTRL_TT3DOWNTO0_shadow_intermed_1 <= V_X_CTRL_TT3DOWNTO0_shadow;
V_X_CTRL_TT3DOWNTO0_shadow_intermed_2 <= V_X_CTRL_TT3DOWNTO0_shadow_intermed_1;
R_M_CTRL_TT3DOWNTO0_intermed_1 <= R.M.CTRL.TT( 3 DOWNTO 0 );
R_M_CTRL_TT3DOWNTO0_intermed_2 <= R_M_CTRL_TT3DOWNTO0_intermed_1;
V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_1 <= V_X_RESULT6DOWNTO03DOWNTO0_shadow;
V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_2 <= V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_1;
V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_3 <= V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_2;
R_X_RESULT6DOWNTO03DOWNTO0_intermed_1 <= R.X.RESULT( 6 DOWNTO 0 )( 3 DOWNTO 0 );
R_X_RESULT6DOWNTO03DOWNTO0_intermed_2 <= R_X_RESULT6DOWNTO03DOWNTO0_intermed_1;
R_A_CTRL_TT3DOWNTO0_intermed_1 <= R.A.CTRL.TT( 3 DOWNTO 0 );
R_A_CTRL_TT3DOWNTO0_intermed_2 <= R_A_CTRL_TT3DOWNTO0_intermed_1;
R_A_CTRL_TT3DOWNTO0_intermed_3 <= R_A_CTRL_TT3DOWNTO0_intermed_2;
R_A_CTRL_TT3DOWNTO0_intermed_4 <= R_A_CTRL_TT3DOWNTO0_intermed_3;
RIN_A_CTRL_TT3DOWNTO0_intermed_1 <= RIN.A.CTRL.TT( 3 DOWNTO 0 );
RIN_A_CTRL_TT3DOWNTO0_intermed_2 <= RIN_A_CTRL_TT3DOWNTO0_intermed_1;
RIN_A_CTRL_TT3DOWNTO0_intermed_3 <= RIN_A_CTRL_TT3DOWNTO0_intermed_2;
RIN_A_CTRL_TT3DOWNTO0_intermed_4 <= RIN_A_CTRL_TT3DOWNTO0_intermed_3;
RIN_A_CTRL_TT3DOWNTO0_intermed_5 <= RIN_A_CTRL_TT3DOWNTO0_intermed_4;
V_A_CTRL_TT3DOWNTO0_shadow_intermed_1 <= V_A_CTRL_TT3DOWNTO0_shadow;
V_A_CTRL_TT3DOWNTO0_shadow_intermed_2 <= V_A_CTRL_TT3DOWNTO0_shadow_intermed_1;
V_A_CTRL_TT3DOWNTO0_shadow_intermed_3 <= V_A_CTRL_TT3DOWNTO0_shadow_intermed_2;
V_A_CTRL_TT3DOWNTO0_shadow_intermed_4 <= V_A_CTRL_TT3DOWNTO0_shadow_intermed_3;
V_A_CTRL_TT3DOWNTO0_shadow_intermed_5 <= V_A_CTRL_TT3DOWNTO0_shadow_intermed_4;
R_E_CTRL_TT3DOWNTO0_intermed_1 <= R.E.CTRL.TT( 3 DOWNTO 0 );
R_E_CTRL_TT3DOWNTO0_intermed_2 <= R_E_CTRL_TT3DOWNTO0_intermed_1;
R_E_CTRL_TT3DOWNTO0_intermed_3 <= R_E_CTRL_TT3DOWNTO0_intermed_2;
RIN_W_S_TT3DOWNTO0_intermed_1 <= RIN.W.S.TT( 3 DOWNTO 0 );
RIN_M_CTRL_TT3DOWNTO0_intermed_1 <= RIN.M.CTRL.TT( 3 DOWNTO 0 );
RIN_M_CTRL_TT3DOWNTO0_intermed_2 <= RIN_M_CTRL_TT3DOWNTO0_intermed_1;
RIN_M_CTRL_TT3DOWNTO0_intermed_3 <= RIN_M_CTRL_TT3DOWNTO0_intermed_2;
V_M_CTRL_TT3DOWNTO0_shadow_intermed_1 <= V_M_CTRL_TT3DOWNTO0_shadow;
V_M_CTRL_TT3DOWNTO0_shadow_intermed_2 <= V_M_CTRL_TT3DOWNTO0_shadow_intermed_1;
V_M_CTRL_TT3DOWNTO0_shadow_intermed_3 <= V_M_CTRL_TT3DOWNTO0_shadow_intermed_2;
RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_1 <= RIN.X.RESULT( 6 DOWNTO 0 )( 3 DOWNTO 0 );
RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_2 <= RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_1;
RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_3 <= RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_2;
RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_1 <= RIN.X.RESULT ( 6 DOWNTO 0 )( 3 DOWNTO 0 );
RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_2 <= RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_1;
R_X_RESULT6DOWNTO03DOWNTO0_intermed_1 <= R.X.RESULT ( 6 DOWNTO 0 )( 3 DOWNTO 0 );
V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_1 <= V_X_RESULT6DOWNTO03DOWNTO0_shadow;
V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_2 <= V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_1;
V_E_CTRL_TT3DOWNTO0_shadow_intermed_1 <= V_E_CTRL_TT3DOWNTO0_shadow;
V_E_CTRL_TT3DOWNTO0_shadow_intermed_2 <= V_E_CTRL_TT3DOWNTO0_shadow_intermed_1;
V_E_CTRL_TT3DOWNTO0_shadow_intermed_3 <= V_E_CTRL_TT3DOWNTO0_shadow_intermed_2;
V_E_CTRL_TT3DOWNTO0_shadow_intermed_4 <= V_E_CTRL_TT3DOWNTO0_shadow_intermed_3;
RIN_X_CTRL_TT3DOWNTO0_intermed_1 <= RIN.X.CTRL.TT( 3 DOWNTO 0 );
RIN_X_CTRL_TT3DOWNTO0_intermed_2 <= RIN_X_CTRL_TT3DOWNTO0_intermed_1;
R_X_CTRL_TT3DOWNTO0_intermed_1 <= R.X.CTRL.TT( 3 DOWNTO 0 );
RIN_E_CTRL_TT3DOWNTO0_intermed_1 <= RIN.E.CTRL.TT( 3 DOWNTO 0 );
RIN_E_CTRL_TT3DOWNTO0_intermed_2 <= RIN_E_CTRL_TT3DOWNTO0_intermed_1;
RIN_E_CTRL_TT3DOWNTO0_intermed_3 <= RIN_E_CTRL_TT3DOWNTO0_intermed_2;
RIN_E_CTRL_TT3DOWNTO0_intermed_4 <= RIN_E_CTRL_TT3DOWNTO0_intermed_3;
XC_VECTT3DOWNTO0_shadow_intermed_1 <= XC_VECTT3DOWNTO0_shadow;
V_D_PC31DOWNTO2_shadow_intermed_1 <= V_D_PC31DOWNTO2_shadow;
V_D_PC31DOWNTO2_shadow_intermed_2 <= V_D_PC31DOWNTO2_shadow_intermed_1;
RIN_D_PC31DOWNTO2_intermed_1 <= RIN.D.PC( 31 DOWNTO 2 );
RIN_D_PC31DOWNTO2_intermed_2 <= RIN_D_PC31DOWNTO2_intermed_1;
R_D_PC31DOWNTO2_intermed_1 <= R.D.PC( 31 DOWNTO 2 );
RIN_A_CTRL_PC31DOWNTO2_intermed_1 <= RIN.A.CTRL.PC( 31 DOWNTO 2 );
V_X_DATA03_shadow_intermed_1 <= V_X_DATA03_shadow;
V_X_DATA03_shadow_intermed_2 <= V_X_DATA03_shadow_intermed_1;
RIN_X_DATA03_intermed_1 <= RIN.X.DATA ( 0 )( 3 );
R_X_DATA03_intermed_1 <= R.X.DATA( 0 )( 3 );
RIN_X_DATA03_intermed_1 <= RIN.X.DATA( 0 )( 3 );
RIN_X_DATA03_intermed_2 <= RIN_X_DATA03_intermed_1;
R_M_CTRL_PC31DOWNTO12_intermed_1 <= R.M.CTRL.PC( 31 DOWNTO 12 );
R_M_CTRL_PC31DOWNTO12_intermed_2 <= R_M_CTRL_PC31DOWNTO12_intermed_1;
V_D_PC31DOWNTO12_shadow_intermed_1 <= V_D_PC31DOWNTO12_shadow;
V_D_PC31DOWNTO12_shadow_intermed_2 <= V_D_PC31DOWNTO12_shadow_intermed_1;
V_D_PC31DOWNTO12_shadow_intermed_3 <= V_D_PC31DOWNTO12_shadow_intermed_2;
V_D_PC31DOWNTO12_shadow_intermed_4 <= V_D_PC31DOWNTO12_shadow_intermed_3;
V_D_PC31DOWNTO12_shadow_intermed_5 <= V_D_PC31DOWNTO12_shadow_intermed_4;
V_D_PC31DOWNTO12_shadow_intermed_6 <= V_D_PC31DOWNTO12_shadow_intermed_5;
V_A_CTRL_PC31DOWNTO12_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO12_shadow;
V_A_CTRL_PC31DOWNTO12_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO12_shadow_intermed_1;
V_A_CTRL_PC31DOWNTO12_shadow_intermed_3 <= V_A_CTRL_PC31DOWNTO12_shadow_intermed_2;
V_A_CTRL_PC31DOWNTO12_shadow_intermed_4 <= V_A_CTRL_PC31DOWNTO12_shadow_intermed_3;
V_A_CTRL_PC31DOWNTO12_shadow_intermed_5 <= V_A_CTRL_PC31DOWNTO12_shadow_intermed_4;
V_E_CTRL_PC31DOWNTO12_shadow_intermed_1 <= V_E_CTRL_PC31DOWNTO12_shadow;
V_E_CTRL_PC31DOWNTO12_shadow_intermed_2 <= V_E_CTRL_PC31DOWNTO12_shadow_intermed_1;
V_E_CTRL_PC31DOWNTO12_shadow_intermed_3 <= V_E_CTRL_PC31DOWNTO12_shadow_intermed_2;
V_E_CTRL_PC31DOWNTO12_shadow_intermed_4 <= V_E_CTRL_PC31DOWNTO12_shadow_intermed_3;
R_A_CTRL_PC31DOWNTO12_intermed_1 <= R.A.CTRL.PC( 31 DOWNTO 12 );
R_A_CTRL_PC31DOWNTO12_intermed_2 <= R_A_CTRL_PC31DOWNTO12_intermed_1;
R_A_CTRL_PC31DOWNTO12_intermed_3 <= R_A_CTRL_PC31DOWNTO12_intermed_2;
R_A_CTRL_PC31DOWNTO12_intermed_4 <= R_A_CTRL_PC31DOWNTO12_intermed_3;
R_E_CTRL_PC31DOWNTO12_intermed_1 <= R.E.CTRL.PC( 31 DOWNTO 12 );
R_E_CTRL_PC31DOWNTO12_intermed_2 <= R_E_CTRL_PC31DOWNTO12_intermed_1;
R_E_CTRL_PC31DOWNTO12_intermed_3 <= R_E_CTRL_PC31DOWNTO12_intermed_2;
RIN_A_CTRL_PC31DOWNTO12_intermed_1 <= RIN.A.CTRL.PC( 31 DOWNTO 12 );
RIN_A_CTRL_PC31DOWNTO12_intermed_2 <= RIN_A_CTRL_PC31DOWNTO12_intermed_1;
RIN_A_CTRL_PC31DOWNTO12_intermed_3 <= RIN_A_CTRL_PC31DOWNTO12_intermed_2;
RIN_A_CTRL_PC31DOWNTO12_intermed_4 <= RIN_A_CTRL_PC31DOWNTO12_intermed_3;
RIN_A_CTRL_PC31DOWNTO12_intermed_5 <= RIN_A_CTRL_PC31DOWNTO12_intermed_4;
RIN_E_CTRL_PC31DOWNTO12_intermed_1 <= RIN.E.CTRL.PC( 31 DOWNTO 12 );
RIN_E_CTRL_PC31DOWNTO12_intermed_2 <= RIN_E_CTRL_PC31DOWNTO12_intermed_1;
RIN_E_CTRL_PC31DOWNTO12_intermed_3 <= RIN_E_CTRL_PC31DOWNTO12_intermed_2;
RIN_E_CTRL_PC31DOWNTO12_intermed_4 <= RIN_E_CTRL_PC31DOWNTO12_intermed_3;
IRIN_ADDR31DOWNTO12_intermed_1 <= IRIN.ADDR( 31 DOWNTO 12 );
V_X_CTRL_PC31DOWNTO12_shadow_intermed_1 <= V_X_CTRL_PC31DOWNTO12_shadow;
V_X_CTRL_PC31DOWNTO12_shadow_intermed_2 <= V_X_CTRL_PC31DOWNTO12_shadow_intermed_1;
RIN_M_CTRL_PC31DOWNTO12_intermed_1 <= RIN.M.CTRL.PC( 31 DOWNTO 12 );
RIN_M_CTRL_PC31DOWNTO12_intermed_2 <= RIN_M_CTRL_PC31DOWNTO12_intermed_1;
RIN_M_CTRL_PC31DOWNTO12_intermed_3 <= RIN_M_CTRL_PC31DOWNTO12_intermed_2;
R_X_CTRL_PC31DOWNTO12_intermed_1 <= R.X.CTRL.PC( 31 DOWNTO 12 );
R_D_PC31DOWNTO12_intermed_1 <= R.D.PC( 31 DOWNTO 12 );
R_D_PC31DOWNTO12_intermed_2 <= R_D_PC31DOWNTO12_intermed_1;
R_D_PC31DOWNTO12_intermed_3 <= R_D_PC31DOWNTO12_intermed_2;
R_D_PC31DOWNTO12_intermed_4 <= R_D_PC31DOWNTO12_intermed_3;
R_D_PC31DOWNTO12_intermed_5 <= R_D_PC31DOWNTO12_intermed_4;
RIN_X_CTRL_PC31DOWNTO12_intermed_1 <= RIN.X.CTRL.PC( 31 DOWNTO 12 );
RIN_X_CTRL_PC31DOWNTO12_intermed_2 <= RIN_X_CTRL_PC31DOWNTO12_intermed_1;
RIN_D_PC31DOWNTO12_intermed_1 <= RIN.D.PC( 31 DOWNTO 12 );
RIN_D_PC31DOWNTO12_intermed_2 <= RIN_D_PC31DOWNTO12_intermed_1;
RIN_D_PC31DOWNTO12_intermed_3 <= RIN_D_PC31DOWNTO12_intermed_2;
RIN_D_PC31DOWNTO12_intermed_4 <= RIN_D_PC31DOWNTO12_intermed_3;
RIN_D_PC31DOWNTO12_intermed_5 <= RIN_D_PC31DOWNTO12_intermed_4;
RIN_D_PC31DOWNTO12_intermed_6 <= RIN_D_PC31DOWNTO12_intermed_5;
V_M_CTRL_PC31DOWNTO12_shadow_intermed_1 <= V_M_CTRL_PC31DOWNTO12_shadow;
V_M_CTRL_PC31DOWNTO12_shadow_intermed_2 <= V_M_CTRL_PC31DOWNTO12_shadow_intermed_1;
V_M_CTRL_PC31DOWNTO12_shadow_intermed_3 <= V_M_CTRL_PC31DOWNTO12_shadow_intermed_2;
RIN_M_CTRL_PC31DOWNTO2_intermed_1 <= RIN.M.CTRL.PC( 31 DOWNTO 2 );
RIN_M_CTRL_PC31DOWNTO2_intermed_2 <= RIN_M_CTRL_PC31DOWNTO2_intermed_1;
RIN_M_CTRL_PC31DOWNTO2_intermed_3 <= RIN_M_CTRL_PC31DOWNTO2_intermed_2;
V_D_PC31DOWNTO2_shadow_intermed_1 <= V_D_PC31DOWNTO2_shadow;
V_D_PC31DOWNTO2_shadow_intermed_2 <= V_D_PC31DOWNTO2_shadow_intermed_1;
V_D_PC31DOWNTO2_shadow_intermed_3 <= V_D_PC31DOWNTO2_shadow_intermed_2;
V_D_PC31DOWNTO2_shadow_intermed_4 <= V_D_PC31DOWNTO2_shadow_intermed_3;
V_D_PC31DOWNTO2_shadow_intermed_5 <= V_D_PC31DOWNTO2_shadow_intermed_4;
V_D_PC31DOWNTO2_shadow_intermed_6 <= V_D_PC31DOWNTO2_shadow_intermed_5;
RIN_D_PC31DOWNTO2_intermed_1 <= RIN.D.PC( 31 DOWNTO 2 );
RIN_D_PC31DOWNTO2_intermed_2 <= RIN_D_PC31DOWNTO2_intermed_1;
RIN_D_PC31DOWNTO2_intermed_3 <= RIN_D_PC31DOWNTO2_intermed_2;
RIN_D_PC31DOWNTO2_intermed_4 <= RIN_D_PC31DOWNTO2_intermed_3;
RIN_D_PC31DOWNTO2_intermed_5 <= RIN_D_PC31DOWNTO2_intermed_4;
RIN_D_PC31DOWNTO2_intermed_6 <= RIN_D_PC31DOWNTO2_intermed_5;
RIN_X_CTRL_PC31DOWNTO2_intermed_1 <= RIN.X.CTRL.PC( 31 DOWNTO 2 );
RIN_X_CTRL_PC31DOWNTO2_intermed_2 <= RIN_X_CTRL_PC31DOWNTO2_intermed_1;
IRIN_ADDR31DOWNTO2_intermed_1 <= IRIN.ADDR( 31 DOWNTO 2 );
V_A_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO2_shadow;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_2;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_4 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_3;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_5 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_4;
R_D_PC31DOWNTO2_intermed_1 <= R.D.PC( 31 DOWNTO 2 );
R_D_PC31DOWNTO2_intermed_2 <= R_D_PC31DOWNTO2_intermed_1;
R_D_PC31DOWNTO2_intermed_3 <= R_D_PC31DOWNTO2_intermed_2;
R_D_PC31DOWNTO2_intermed_4 <= R_D_PC31DOWNTO2_intermed_3;
R_D_PC31DOWNTO2_intermed_5 <= R_D_PC31DOWNTO2_intermed_4;
R_M_CTRL_PC31DOWNTO2_intermed_1 <= R.M.CTRL.PC( 31 DOWNTO 2 );
R_M_CTRL_PC31DOWNTO2_intermed_2 <= R_M_CTRL_PC31DOWNTO2_intermed_1;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_E_CTRL_PC31DOWNTO2_shadow;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_2;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_4 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_3;
RIN_A_CTRL_PC31DOWNTO2_intermed_1 <= RIN.A.CTRL.PC( 31 DOWNTO 2 );
RIN_A_CTRL_PC31DOWNTO2_intermed_2 <= RIN_A_CTRL_PC31DOWNTO2_intermed_1;
RIN_A_CTRL_PC31DOWNTO2_intermed_3 <= RIN_A_CTRL_PC31DOWNTO2_intermed_2;
RIN_A_CTRL_PC31DOWNTO2_intermed_4 <= RIN_A_CTRL_PC31DOWNTO2_intermed_3;
RIN_A_CTRL_PC31DOWNTO2_intermed_5 <= RIN_A_CTRL_PC31DOWNTO2_intermed_4;
R_A_CTRL_PC31DOWNTO2_intermed_1 <= R.A.CTRL.PC( 31 DOWNTO 2 );
R_A_CTRL_PC31DOWNTO2_intermed_2 <= R_A_CTRL_PC31DOWNTO2_intermed_1;
R_A_CTRL_PC31DOWNTO2_intermed_3 <= R_A_CTRL_PC31DOWNTO2_intermed_2;
R_A_CTRL_PC31DOWNTO2_intermed_4 <= R_A_CTRL_PC31DOWNTO2_intermed_3;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_M_CTRL_PC31DOWNTO2_shadow;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_M_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_M_CTRL_PC31DOWNTO2_shadow_intermed_2;
R_X_CTRL_PC31DOWNTO2_intermed_1 <= R.X.CTRL.PC( 31 DOWNTO 2 );
R_E_CTRL_PC31DOWNTO2_intermed_1 <= R.E.CTRL.PC( 31 DOWNTO 2 );
R_E_CTRL_PC31DOWNTO2_intermed_2 <= R_E_CTRL_PC31DOWNTO2_intermed_1;
R_E_CTRL_PC31DOWNTO2_intermed_3 <= R_E_CTRL_PC31DOWNTO2_intermed_2;
RIN_E_CTRL_PC31DOWNTO2_intermed_1 <= RIN.E.CTRL.PC( 31 DOWNTO 2 );
RIN_E_CTRL_PC31DOWNTO2_intermed_2 <= RIN_E_CTRL_PC31DOWNTO2_intermed_1;
RIN_E_CTRL_PC31DOWNTO2_intermed_3 <= RIN_E_CTRL_PC31DOWNTO2_intermed_2;
RIN_E_CTRL_PC31DOWNTO2_intermed_4 <= RIN_E_CTRL_PC31DOWNTO2_intermed_3;
V_X_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_X_CTRL_PC31DOWNTO2_shadow;
V_X_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_X_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_F_PC31DOWNTO4_shadow_intermed_1 <= V_F_PC31DOWNTO4_shadow;
V_X_CTRL_PC31DOWNTO4_shadow_intermed_1 <= V_X_CTRL_PC31DOWNTO4_shadow;
V_X_CTRL_PC31DOWNTO4_shadow_intermed_2 <= V_X_CTRL_PC31DOWNTO4_shadow_intermed_1;
V_X_CTRL_PC31DOWNTO4_shadow_intermed_3 <= V_X_CTRL_PC31DOWNTO4_shadow_intermed_2;
IR_ADDR31DOWNTO4_intermed_1 <= IR.ADDR( 31 DOWNTO 4 );
VIR_ADDR31DOWNTO4_shadow_intermed_1 <= VIR_ADDR31DOWNTO4_shadow;
VIR_ADDR31DOWNTO4_shadow_intermed_2 <= VIR_ADDR31DOWNTO4_shadow_intermed_1;
RIN_F_PC31DOWNTO4_intermed_1 <= RIN.F.PC( 31 DOWNTO 4 );
RIN_A_CTRL_PC31DOWNTO4_intermed_1 <= RIN.A.CTRL.PC( 31 DOWNTO 4 );
RIN_A_CTRL_PC31DOWNTO4_intermed_2 <= RIN_A_CTRL_PC31DOWNTO4_intermed_1;
RIN_A_CTRL_PC31DOWNTO4_intermed_3 <= RIN_A_CTRL_PC31DOWNTO4_intermed_2;
RIN_A_CTRL_PC31DOWNTO4_intermed_4 <= RIN_A_CTRL_PC31DOWNTO4_intermed_3;
RIN_A_CTRL_PC31DOWNTO4_intermed_5 <= RIN_A_CTRL_PC31DOWNTO4_intermed_4;
RIN_A_CTRL_PC31DOWNTO4_intermed_6 <= RIN_A_CTRL_PC31DOWNTO4_intermed_5;
R_A_CTRL_PC31DOWNTO4_intermed_1 <= R.A.CTRL.PC( 31 DOWNTO 4 );
R_A_CTRL_PC31DOWNTO4_intermed_2 <= R_A_CTRL_PC31DOWNTO4_intermed_1;
R_A_CTRL_PC31DOWNTO4_intermed_3 <= R_A_CTRL_PC31DOWNTO4_intermed_2;
R_A_CTRL_PC31DOWNTO4_intermed_4 <= R_A_CTRL_PC31DOWNTO4_intermed_3;
R_A_CTRL_PC31DOWNTO4_intermed_5 <= R_A_CTRL_PC31DOWNTO4_intermed_4;
R_D_PC31DOWNTO4_intermed_1 <= R.D.PC( 31 DOWNTO 4 );
R_D_PC31DOWNTO4_intermed_2 <= R_D_PC31DOWNTO4_intermed_1;
R_D_PC31DOWNTO4_intermed_3 <= R_D_PC31DOWNTO4_intermed_2;
R_D_PC31DOWNTO4_intermed_4 <= R_D_PC31DOWNTO4_intermed_3;
R_D_PC31DOWNTO4_intermed_5 <= R_D_PC31DOWNTO4_intermed_4;
R_D_PC31DOWNTO4_intermed_6 <= R_D_PC31DOWNTO4_intermed_5;
RIN_X_CTRL_PC31DOWNTO4_intermed_1 <= RIN.X.CTRL.PC( 31 DOWNTO 4 );
RIN_X_CTRL_PC31DOWNTO4_intermed_2 <= RIN_X_CTRL_PC31DOWNTO4_intermed_1;
RIN_X_CTRL_PC31DOWNTO4_intermed_3 <= RIN_X_CTRL_PC31DOWNTO4_intermed_2;
EX_ADD_RES32DOWNTO332DOWNTO5_shadow_intermed_1 <= EX_ADD_RES32DOWNTO332DOWNTO5_shadow;
V_D_PC31DOWNTO4_shadow_intermed_1 <= V_D_PC31DOWNTO4_shadow;
V_D_PC31DOWNTO4_shadow_intermed_2 <= V_D_PC31DOWNTO4_shadow_intermed_1;
V_D_PC31DOWNTO4_shadow_intermed_3 <= V_D_PC31DOWNTO4_shadow_intermed_2;
V_D_PC31DOWNTO4_shadow_intermed_4 <= V_D_PC31DOWNTO4_shadow_intermed_3;
V_D_PC31DOWNTO4_shadow_intermed_5 <= V_D_PC31DOWNTO4_shadow_intermed_4;
V_D_PC31DOWNTO4_shadow_intermed_6 <= V_D_PC31DOWNTO4_shadow_intermed_5;
V_D_PC31DOWNTO4_shadow_intermed_7 <= V_D_PC31DOWNTO4_shadow_intermed_6;
V_E_CTRL_PC31DOWNTO4_shadow_intermed_1 <= V_E_CTRL_PC31DOWNTO4_shadow;
V_E_CTRL_PC31DOWNTO4_shadow_intermed_2 <= V_E_CTRL_PC31DOWNTO4_shadow_intermed_1;
V_E_CTRL_PC31DOWNTO4_shadow_intermed_3 <= V_E_CTRL_PC31DOWNTO4_shadow_intermed_2;
V_E_CTRL_PC31DOWNTO4_shadow_intermed_4 <= V_E_CTRL_PC31DOWNTO4_shadow_intermed_3;
V_E_CTRL_PC31DOWNTO4_shadow_intermed_5 <= V_E_CTRL_PC31DOWNTO4_shadow_intermed_4;
RIN_M_CTRL_PC31DOWNTO4_intermed_1 <= RIN.M.CTRL.PC( 31 DOWNTO 4 );
RIN_M_CTRL_PC31DOWNTO4_intermed_2 <= RIN_M_CTRL_PC31DOWNTO4_intermed_1;
RIN_M_CTRL_PC31DOWNTO4_intermed_3 <= RIN_M_CTRL_PC31DOWNTO4_intermed_2;
RIN_M_CTRL_PC31DOWNTO4_intermed_4 <= RIN_M_CTRL_PC31DOWNTO4_intermed_3;
R_X_CTRL_PC31DOWNTO4_intermed_1 <= R.X.CTRL.PC( 31 DOWNTO 4 );
R_X_CTRL_PC31DOWNTO4_intermed_2 <= R_X_CTRL_PC31DOWNTO4_intermed_1;
IRIN_ADDR31DOWNTO4_intermed_1 <= IRIN.ADDR( 31 DOWNTO 4 );
IRIN_ADDR31DOWNTO4_intermed_2 <= IRIN_ADDR31DOWNTO4_intermed_1;
V_M_CTRL_PC31DOWNTO4_shadow_intermed_1 <= V_M_CTRL_PC31DOWNTO4_shadow;
V_M_CTRL_PC31DOWNTO4_shadow_intermed_2 <= V_M_CTRL_PC31DOWNTO4_shadow_intermed_1;
V_M_CTRL_PC31DOWNTO4_shadow_intermed_3 <= V_M_CTRL_PC31DOWNTO4_shadow_intermed_2;
V_M_CTRL_PC31DOWNTO4_shadow_intermed_4 <= V_M_CTRL_PC31DOWNTO4_shadow_intermed_3;
R_M_CTRL_PC31DOWNTO4_intermed_1 <= R.M.CTRL.PC( 31 DOWNTO 4 );
R_M_CTRL_PC31DOWNTO4_intermed_2 <= R_M_CTRL_PC31DOWNTO4_intermed_1;
R_M_CTRL_PC31DOWNTO4_intermed_3 <= R_M_CTRL_PC31DOWNTO4_intermed_2;
RIN_D_PC31DOWNTO4_intermed_1 <= RIN.D.PC( 31 DOWNTO 4 );
RIN_D_PC31DOWNTO4_intermed_2 <= RIN_D_PC31DOWNTO4_intermed_1;
RIN_D_PC31DOWNTO4_intermed_3 <= RIN_D_PC31DOWNTO4_intermed_2;
RIN_D_PC31DOWNTO4_intermed_4 <= RIN_D_PC31DOWNTO4_intermed_3;
RIN_D_PC31DOWNTO4_intermed_5 <= RIN_D_PC31DOWNTO4_intermed_4;
RIN_D_PC31DOWNTO4_intermed_6 <= RIN_D_PC31DOWNTO4_intermed_5;
RIN_D_PC31DOWNTO4_intermed_7 <= RIN_D_PC31DOWNTO4_intermed_6;
RIN_E_CTRL_PC31DOWNTO4_intermed_1 <= RIN.E.CTRL.PC( 31 DOWNTO 4 );
RIN_E_CTRL_PC31DOWNTO4_intermed_2 <= RIN_E_CTRL_PC31DOWNTO4_intermed_1;
RIN_E_CTRL_PC31DOWNTO4_intermed_3 <= RIN_E_CTRL_PC31DOWNTO4_intermed_2;
RIN_E_CTRL_PC31DOWNTO4_intermed_4 <= RIN_E_CTRL_PC31DOWNTO4_intermed_3;
RIN_E_CTRL_PC31DOWNTO4_intermed_5 <= RIN_E_CTRL_PC31DOWNTO4_intermed_4;
EX_JUMP_ADDRESS31DOWNTO4_shadow_intermed_1 <= EX_JUMP_ADDRESS31DOWNTO4_shadow;
V_A_CTRL_PC31DOWNTO4_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO4_shadow;
V_A_CTRL_PC31DOWNTO4_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO4_shadow_intermed_1;
V_A_CTRL_PC31DOWNTO4_shadow_intermed_3 <= V_A_CTRL_PC31DOWNTO4_shadow_intermed_2;
V_A_CTRL_PC31DOWNTO4_shadow_intermed_4 <= V_A_CTRL_PC31DOWNTO4_shadow_intermed_3;
V_A_CTRL_PC31DOWNTO4_shadow_intermed_5 <= V_A_CTRL_PC31DOWNTO4_shadow_intermed_4;
V_A_CTRL_PC31DOWNTO4_shadow_intermed_6 <= V_A_CTRL_PC31DOWNTO4_shadow_intermed_5;
R_E_CTRL_PC31DOWNTO4_intermed_1 <= R.E.CTRL.PC( 31 DOWNTO 4 );
R_E_CTRL_PC31DOWNTO4_intermed_2 <= R_E_CTRL_PC31DOWNTO4_intermed_1;
R_E_CTRL_PC31DOWNTO4_intermed_3 <= R_E_CTRL_PC31DOWNTO4_intermed_2;
R_E_CTRL_PC31DOWNTO4_intermed_4 <= R_E_CTRL_PC31DOWNTO4_intermed_3;
R_D_PC3DOWNTO2_intermed_1 <= R.D.PC( 3 DOWNTO 2 );
R_D_PC3DOWNTO2_intermed_2 <= R_D_PC3DOWNTO2_intermed_1;
R_D_PC3DOWNTO2_intermed_3 <= R_D_PC3DOWNTO2_intermed_2;
R_D_PC3DOWNTO2_intermed_4 <= R_D_PC3DOWNTO2_intermed_3;
R_D_PC3DOWNTO2_intermed_5 <= R_D_PC3DOWNTO2_intermed_4;
R_D_PC3DOWNTO2_intermed_6 <= R_D_PC3DOWNTO2_intermed_5;
V_D_PC3DOWNTO2_shadow_intermed_1 <= V_D_PC3DOWNTO2_shadow;
V_D_PC3DOWNTO2_shadow_intermed_2 <= V_D_PC3DOWNTO2_shadow_intermed_1;
V_D_PC3DOWNTO2_shadow_intermed_3 <= V_D_PC3DOWNTO2_shadow_intermed_2;
V_D_PC3DOWNTO2_shadow_intermed_4 <= V_D_PC3DOWNTO2_shadow_intermed_3;
V_D_PC3DOWNTO2_shadow_intermed_5 <= V_D_PC3DOWNTO2_shadow_intermed_4;
V_D_PC3DOWNTO2_shadow_intermed_6 <= V_D_PC3DOWNTO2_shadow_intermed_5;
V_D_PC3DOWNTO2_shadow_intermed_7 <= V_D_PC3DOWNTO2_shadow_intermed_6;
VIR_ADDR3DOWNTO2_shadow_intermed_1 <= VIR_ADDR3DOWNTO2_shadow;
VIR_ADDR3DOWNTO2_shadow_intermed_2 <= VIR_ADDR3DOWNTO2_shadow_intermed_1;
RIN_D_PC3DOWNTO2_intermed_1 <= RIN.D.PC( 3 DOWNTO 2 );
RIN_D_PC3DOWNTO2_intermed_2 <= RIN_D_PC3DOWNTO2_intermed_1;
RIN_D_PC3DOWNTO2_intermed_3 <= RIN_D_PC3DOWNTO2_intermed_2;
RIN_D_PC3DOWNTO2_intermed_4 <= RIN_D_PC3DOWNTO2_intermed_3;
RIN_D_PC3DOWNTO2_intermed_5 <= RIN_D_PC3DOWNTO2_intermed_4;
RIN_D_PC3DOWNTO2_intermed_6 <= RIN_D_PC3DOWNTO2_intermed_5;
RIN_D_PC3DOWNTO2_intermed_7 <= RIN_D_PC3DOWNTO2_intermed_6;
R_M_CTRL_PC3DOWNTO2_intermed_1 <= R.M.CTRL.PC( 3 DOWNTO 2 );
R_M_CTRL_PC3DOWNTO2_intermed_2 <= R_M_CTRL_PC3DOWNTO2_intermed_1;
R_M_CTRL_PC3DOWNTO2_intermed_3 <= R_M_CTRL_PC3DOWNTO2_intermed_2;
R_E_CTRL_PC3DOWNTO2_intermed_1 <= R.E.CTRL.PC( 3 DOWNTO 2 );
R_E_CTRL_PC3DOWNTO2_intermed_2 <= R_E_CTRL_PC3DOWNTO2_intermed_1;
R_E_CTRL_PC3DOWNTO2_intermed_3 <= R_E_CTRL_PC3DOWNTO2_intermed_2;
R_E_CTRL_PC3DOWNTO2_intermed_4 <= R_E_CTRL_PC3DOWNTO2_intermed_3;
V_E_CTRL_PC3DOWNTO2_shadow_intermed_1 <= V_E_CTRL_PC3DOWNTO2_shadow;
V_E_CTRL_PC3DOWNTO2_shadow_intermed_2 <= V_E_CTRL_PC3DOWNTO2_shadow_intermed_1;
V_E_CTRL_PC3DOWNTO2_shadow_intermed_3 <= V_E_CTRL_PC3DOWNTO2_shadow_intermed_2;
V_E_CTRL_PC3DOWNTO2_shadow_intermed_4 <= V_E_CTRL_PC3DOWNTO2_shadow_intermed_3;
V_E_CTRL_PC3DOWNTO2_shadow_intermed_5 <= V_E_CTRL_PC3DOWNTO2_shadow_intermed_4;
RIN_X_CTRL_PC3DOWNTO2_intermed_1 <= RIN.X.CTRL.PC( 3 DOWNTO 2 );
RIN_X_CTRL_PC3DOWNTO2_intermed_2 <= RIN_X_CTRL_PC3DOWNTO2_intermed_1;
RIN_X_CTRL_PC3DOWNTO2_intermed_3 <= RIN_X_CTRL_PC3DOWNTO2_intermed_2;
R_A_CTRL_PC3DOWNTO2_intermed_1 <= R.A.CTRL.PC( 3 DOWNTO 2 );
R_A_CTRL_PC3DOWNTO2_intermed_2 <= R_A_CTRL_PC3DOWNTO2_intermed_1;
R_A_CTRL_PC3DOWNTO2_intermed_3 <= R_A_CTRL_PC3DOWNTO2_intermed_2;
R_A_CTRL_PC3DOWNTO2_intermed_4 <= R_A_CTRL_PC3DOWNTO2_intermed_3;
R_A_CTRL_PC3DOWNTO2_intermed_5 <= R_A_CTRL_PC3DOWNTO2_intermed_4;
V_X_CTRL_PC3DOWNTO2_shadow_intermed_1 <= V_X_CTRL_PC3DOWNTO2_shadow;
V_X_CTRL_PC3DOWNTO2_shadow_intermed_2 <= V_X_CTRL_PC3DOWNTO2_shadow_intermed_1;
V_X_CTRL_PC3DOWNTO2_shadow_intermed_3 <= V_X_CTRL_PC3DOWNTO2_shadow_intermed_2;
RIN_M_CTRL_PC3DOWNTO2_intermed_1 <= RIN.M.CTRL.PC( 3 DOWNTO 2 );
RIN_M_CTRL_PC3DOWNTO2_intermed_2 <= RIN_M_CTRL_PC3DOWNTO2_intermed_1;
RIN_M_CTRL_PC3DOWNTO2_intermed_3 <= RIN_M_CTRL_PC3DOWNTO2_intermed_2;
RIN_M_CTRL_PC3DOWNTO2_intermed_4 <= RIN_M_CTRL_PC3DOWNTO2_intermed_3;
IRIN_ADDR3DOWNTO2_intermed_1 <= IRIN.ADDR( 3 DOWNTO 2 );
IRIN_ADDR3DOWNTO2_intermed_2 <= IRIN_ADDR3DOWNTO2_intermed_1;
EX_JUMP_ADDRESS3DOWNTO2_shadow_intermed_1 <= EX_JUMP_ADDRESS3DOWNTO2_shadow;
EX_ADD_RES32DOWNTO34DOWNTO3_shadow_intermed_1 <= EX_ADD_RES32DOWNTO34DOWNTO3_shadow;
RIN_A_CTRL_PC3DOWNTO2_intermed_1 <= RIN.A.CTRL.PC( 3 DOWNTO 2 );
RIN_A_CTRL_PC3DOWNTO2_intermed_2 <= RIN_A_CTRL_PC3DOWNTO2_intermed_1;
RIN_A_CTRL_PC3DOWNTO2_intermed_3 <= RIN_A_CTRL_PC3DOWNTO2_intermed_2;
RIN_A_CTRL_PC3DOWNTO2_intermed_4 <= RIN_A_CTRL_PC3DOWNTO2_intermed_3;
RIN_A_CTRL_PC3DOWNTO2_intermed_5 <= RIN_A_CTRL_PC3DOWNTO2_intermed_4;
RIN_A_CTRL_PC3DOWNTO2_intermed_6 <= RIN_A_CTRL_PC3DOWNTO2_intermed_5;
V_F_PC3DOWNTO2_shadow_intermed_1 <= V_F_PC3DOWNTO2_shadow;
V_A_CTRL_PC3DOWNTO2_shadow_intermed_1 <= V_A_CTRL_PC3DOWNTO2_shadow;
V_A_CTRL_PC3DOWNTO2_shadow_intermed_2 <= V_A_CTRL_PC3DOWNTO2_shadow_intermed_1;
V_A_CTRL_PC3DOWNTO2_shadow_intermed_3 <= V_A_CTRL_PC3DOWNTO2_shadow_intermed_2;
V_A_CTRL_PC3DOWNTO2_shadow_intermed_4 <= V_A_CTRL_PC3DOWNTO2_shadow_intermed_3;
V_A_CTRL_PC3DOWNTO2_shadow_intermed_5 <= V_A_CTRL_PC3DOWNTO2_shadow_intermed_4;
V_A_CTRL_PC3DOWNTO2_shadow_intermed_6 <= V_A_CTRL_PC3DOWNTO2_shadow_intermed_5;
IR_ADDR3DOWNTO2_intermed_1 <= IR.ADDR( 3 DOWNTO 2 );
V_M_CTRL_PC3DOWNTO2_shadow_intermed_1 <= V_M_CTRL_PC3DOWNTO2_shadow;
V_M_CTRL_PC3DOWNTO2_shadow_intermed_2 <= V_M_CTRL_PC3DOWNTO2_shadow_intermed_1;
V_M_CTRL_PC3DOWNTO2_shadow_intermed_3 <= V_M_CTRL_PC3DOWNTO2_shadow_intermed_2;
V_M_CTRL_PC3DOWNTO2_shadow_intermed_4 <= V_M_CTRL_PC3DOWNTO2_shadow_intermed_3;
R_X_CTRL_PC3DOWNTO2_intermed_1 <= R.X.CTRL.PC( 3 DOWNTO 2 );
R_X_CTRL_PC3DOWNTO2_intermed_2 <= R_X_CTRL_PC3DOWNTO2_intermed_1;
RIN_E_CTRL_PC3DOWNTO2_intermed_1 <= RIN.E.CTRL.PC( 3 DOWNTO 2 );
RIN_E_CTRL_PC3DOWNTO2_intermed_2 <= RIN_E_CTRL_PC3DOWNTO2_intermed_1;
RIN_E_CTRL_PC3DOWNTO2_intermed_3 <= RIN_E_CTRL_PC3DOWNTO2_intermed_2;
RIN_E_CTRL_PC3DOWNTO2_intermed_4 <= RIN_E_CTRL_PC3DOWNTO2_intermed_3;
RIN_E_CTRL_PC3DOWNTO2_intermed_5 <= RIN_E_CTRL_PC3DOWNTO2_intermed_4;
RIN_F_PC3DOWNTO2_intermed_1 <= RIN.F.PC( 3 DOWNTO 2 );
V_E_CTRL_RD7DOWNTO0_shadow_intermed_1 <= V_E_CTRL_RD7DOWNTO0_shadow;
V_E_CTRL_RD7DOWNTO0_shadow_intermed_2 <= V_E_CTRL_RD7DOWNTO0_shadow_intermed_1;
R_E_CTRL_RD7DOWNTO0_intermed_1 <= R.E.CTRL.RD ( 7 DOWNTO 0 );
V_A_CTRL_RD7DOWNTO0_shadow_intermed_1 <= V_A_CTRL_RD7DOWNTO0_shadow;
V_A_CTRL_RD7DOWNTO0_shadow_intermed_2 <= V_A_CTRL_RD7DOWNTO0_shadow_intermed_1;
V_A_CTRL_RD7DOWNTO0_shadow_intermed_3 <= V_A_CTRL_RD7DOWNTO0_shadow_intermed_2;
RIN_A_CTRL_RD7DOWNTO0_intermed_1 <= RIN.A.CTRL.RD ( 7 DOWNTO 0 );
RIN_A_CTRL_RD7DOWNTO0_intermed_2 <= RIN_A_CTRL_RD7DOWNTO0_intermed_1;
RIN_A_CTRL_RD7DOWNTO0_intermed_3 <= RIN_A_CTRL_RD7DOWNTO0_intermed_2;
R_A_CTRL_RD7DOWNTO0_intermed_1 <= R.A.CTRL.RD ( 7 DOWNTO 0 );
R_A_CTRL_RD7DOWNTO0_intermed_2 <= R_A_CTRL_RD7DOWNTO0_intermed_1;
RIN_E_CTRL_RD7DOWNTO0_intermed_1 <= RIN.E.CTRL.RD ( 7 DOWNTO 0 );
RIN_E_CTRL_RD7DOWNTO0_intermed_2 <= RIN_E_CTRL_RD7DOWNTO0_intermed_1;
RIN_M_CTRL_RD7DOWNTO0_intermed_1 <= RIN.M.CTRL.RD ( 7 DOWNTO 0 );
RIN_D_PC_intermed_1 <= RIN.D.PC;
RIN_D_PC_intermed_2 <= RIN_D_PC_intermed_1;
RIN_D_PC_intermed_3 <= RIN_D_PC_intermed_2;
RIN_D_PC_intermed_4 <= RIN_D_PC_intermed_3;
RIN_A_CTRL_PC_intermed_1 <= RIN.A.CTRL.PC;
RIN_A_CTRL_PC_intermed_2 <= RIN_A_CTRL_PC_intermed_1;
RIN_A_CTRL_PC_intermed_3 <= RIN_A_CTRL_PC_intermed_2;
R_A_CTRL_PC_intermed_1 <= R.A.CTRL.PC;
R_A_CTRL_PC_intermed_2 <= R_A_CTRL_PC_intermed_1;
V_E_CTRL_PC_shadow_intermed_1 <= V_E_CTRL_PC_shadow;
V_E_CTRL_PC_shadow_intermed_2 <= V_E_CTRL_PC_shadow_intermed_1;
R_E_CTRL_PC_intermed_1 <= R.E.CTRL.PC;
RIN_M_CTRL_PC_intermed_1 <= RIN.M.CTRL.PC;
V_A_CTRL_PC_shadow_intermed_1 <= V_A_CTRL_PC_shadow;
V_A_CTRL_PC_shadow_intermed_2 <= V_A_CTRL_PC_shadow_intermed_1;
V_A_CTRL_PC_shadow_intermed_3 <= V_A_CTRL_PC_shadow_intermed_2;
R_D_PC_intermed_1 <= R.D.PC;
R_D_PC_intermed_2 <= R_D_PC_intermed_1;
R_D_PC_intermed_3 <= R_D_PC_intermed_2;
RIN_E_CTRL_PC_intermed_1 <= RIN.E.CTRL.PC;
RIN_E_CTRL_PC_intermed_2 <= RIN_E_CTRL_PC_intermed_1;
V_D_PC_shadow_intermed_1 <= V_D_PC_shadow;
V_D_PC_shadow_intermed_2 <= V_D_PC_shadow_intermed_1;
V_D_PC_shadow_intermed_3 <= V_D_PC_shadow_intermed_2;
V_D_PC_shadow_intermed_4 <= V_D_PC_shadow_intermed_3;
RIN_M_CTRL_PC31DOWNTO2_intermed_1 <= RIN.M.CTRL.PC( 31 DOWNTO 2 );
V_D_PC31DOWNTO2_shadow_intermed_1 <= V_D_PC31DOWNTO2_shadow;
V_D_PC31DOWNTO2_shadow_intermed_2 <= V_D_PC31DOWNTO2_shadow_intermed_1;
V_D_PC31DOWNTO2_shadow_intermed_3 <= V_D_PC31DOWNTO2_shadow_intermed_2;
V_D_PC31DOWNTO2_shadow_intermed_4 <= V_D_PC31DOWNTO2_shadow_intermed_3;
RIN_D_PC31DOWNTO2_intermed_1 <= RIN.D.PC( 31 DOWNTO 2 );
RIN_D_PC31DOWNTO2_intermed_2 <= RIN_D_PC31DOWNTO2_intermed_1;
RIN_D_PC31DOWNTO2_intermed_3 <= RIN_D_PC31DOWNTO2_intermed_2;
RIN_D_PC31DOWNTO2_intermed_4 <= RIN_D_PC31DOWNTO2_intermed_3;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO2_shadow;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_2;
R_D_PC31DOWNTO2_intermed_1 <= R.D.PC( 31 DOWNTO 2 );
R_D_PC31DOWNTO2_intermed_2 <= R_D_PC31DOWNTO2_intermed_1;
R_D_PC31DOWNTO2_intermed_3 <= R_D_PC31DOWNTO2_intermed_2;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_E_CTRL_PC31DOWNTO2_shadow;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_1;
RIN_A_CTRL_PC31DOWNTO2_intermed_1 <= RIN.A.CTRL.PC( 31 DOWNTO 2 );
RIN_A_CTRL_PC31DOWNTO2_intermed_2 <= RIN_A_CTRL_PC31DOWNTO2_intermed_1;
RIN_A_CTRL_PC31DOWNTO2_intermed_3 <= RIN_A_CTRL_PC31DOWNTO2_intermed_2;
R_A_CTRL_PC31DOWNTO2_intermed_1 <= R.A.CTRL.PC( 31 DOWNTO 2 );
R_A_CTRL_PC31DOWNTO2_intermed_2 <= R_A_CTRL_PC31DOWNTO2_intermed_1;
R_E_CTRL_PC31DOWNTO2_intermed_1 <= R.E.CTRL.PC( 31 DOWNTO 2 );
RIN_E_CTRL_PC31DOWNTO2_intermed_1 <= RIN.E.CTRL.PC( 31 DOWNTO 2 );
RIN_E_CTRL_PC31DOWNTO2_intermed_2 <= RIN_E_CTRL_PC31DOWNTO2_intermed_1;
R_D_INST020_intermed_1 <= R.D.INST ( 0 )( 20 );
RIN_D_INST020_intermed_1 <= RIN.D.INST( 0 )( 20 );
RIN_D_INST020_intermed_2 <= RIN_D_INST020_intermed_1;
RIN_D_INST020_intermed_3 <= RIN_D_INST020_intermed_2;
RIN_A_CTRL_INST20_intermed_1 <= RIN.A.CTRL.INST ( 20 );
RIN_D_INST020_intermed_1 <= RIN.D.INST ( 0 )( 20 );
RIN_D_INST020_intermed_2 <= RIN_D_INST020_intermed_1;
RIN_A_CTRL_INST20_intermed_1 <= RIN.A.CTRL.INST( 20 );
RIN_A_CTRL_INST20_intermed_2 <= RIN_A_CTRL_INST20_intermed_1;
V_A_CTRL_INST20_shadow_intermed_1 <= V_A_CTRL_INST20_shadow;
V_A_CTRL_INST20_shadow_intermed_2 <= V_A_CTRL_INST20_shadow_intermed_1;
V_D_INST020_shadow_intermed_1 <= V_D_INST020_shadow;
V_D_INST020_shadow_intermed_2 <= V_D_INST020_shadow_intermed_1;
V_D_INST020_shadow_intermed_1 <= V_D_INST020_shadow;
V_D_INST020_shadow_intermed_2 <= V_D_INST020_shadow_intermed_1;
V_D_INST020_shadow_intermed_3 <= V_D_INST020_shadow_intermed_2;
R_D_INST020_intermed_1 <= R.D.INST( 0 )( 20 );
R_D_INST020_intermed_2 <= R_D_INST020_intermed_1;
DE_INST20_shadow_intermed_1 <= DE_INST20_shadow;
R_A_CTRL_INST20_intermed_1 <= R.A.CTRL.INST( 20 );
R_D_INST020_intermed_1 <= R.D.INST ( 0 )( 20 );
RIN_D_INST020_intermed_1 <= RIN.D.INST( 0 )( 20 );
RIN_D_INST020_intermed_2 <= RIN_D_INST020_intermed_1;
RIN_D_INST020_intermed_3 <= RIN_D_INST020_intermed_2;
RIN_D_INST020_intermed_1 <= RIN.D.INST ( 0 )( 20 );
RIN_D_INST020_intermed_2 <= RIN_D_INST020_intermed_1;
RIN_A_CTRL_INST20_intermed_1 <= RIN.A.CTRL.INST( 20 );
V_D_INST020_shadow_intermed_1 <= V_D_INST020_shadow;
V_D_INST020_shadow_intermed_2 <= V_D_INST020_shadow_intermed_1;
V_D_INST020_shadow_intermed_1 <= V_D_INST020_shadow;
V_D_INST020_shadow_intermed_2 <= V_D_INST020_shadow_intermed_1;
V_D_INST020_shadow_intermed_3 <= V_D_INST020_shadow_intermed_2;
R_D_INST020_intermed_1 <= R.D.INST( 0 )( 20 );
R_D_INST020_intermed_2 <= R_D_INST020_intermed_1;
DE_INST20_shadow_intermed_1 <= DE_INST20_shadow;
R_A_CTRL_INST24_intermed_1 <= R.A.CTRL.INST( 24 );
RIN_D_INST024_intermed_1 <= RIN.D.INST ( 0 )( 24 );
RIN_D_INST024_intermed_2 <= RIN_D_INST024_intermed_1;
V_D_INST024_shadow_intermed_1 <= V_D_INST024_shadow;
V_D_INST024_shadow_intermed_2 <= V_D_INST024_shadow_intermed_1;
V_D_INST024_shadow_intermed_3 <= V_D_INST024_shadow_intermed_2;
RIN_A_CTRL_INST24_intermed_1 <= RIN.A.CTRL.INST( 24 );
RIN_A_CTRL_INST24_intermed_2 <= RIN_A_CTRL_INST24_intermed_1;
V_D_INST024_shadow_intermed_1 <= V_D_INST024_shadow;
V_D_INST024_shadow_intermed_2 <= V_D_INST024_shadow_intermed_1;
V_A_CTRL_INST24_shadow_intermed_1 <= V_A_CTRL_INST24_shadow;
V_A_CTRL_INST24_shadow_intermed_2 <= V_A_CTRL_INST24_shadow_intermed_1;
DE_INST24_shadow_intermed_1 <= DE_INST24_shadow;
RIN_A_CTRL_INST24_intermed_1 <= RIN.A.CTRL.INST ( 24 );
RIN_D_INST024_intermed_1 <= RIN.D.INST( 0 )( 24 );
RIN_D_INST024_intermed_2 <= RIN_D_INST024_intermed_1;
RIN_D_INST024_intermed_3 <= RIN_D_INST024_intermed_2;
R_D_INST024_intermed_1 <= R.D.INST ( 0 )( 24 );
R_D_INST024_intermed_1 <= R.D.INST( 0 )( 24 );
R_D_INST024_intermed_2 <= R_D_INST024_intermed_1;
RIN_D_INST024_intermed_1 <= RIN.D.INST ( 0 )( 24 );
RIN_D_INST024_intermed_2 <= RIN_D_INST024_intermed_1;
V_D_INST024_shadow_intermed_1 <= V_D_INST024_shadow;
V_D_INST024_shadow_intermed_2 <= V_D_INST024_shadow_intermed_1;
V_D_INST024_shadow_intermed_3 <= V_D_INST024_shadow_intermed_2;
RIN_A_CTRL_INST24_intermed_1 <= RIN.A.CTRL.INST( 24 );
V_D_INST024_shadow_intermed_1 <= V_D_INST024_shadow;
V_D_INST024_shadow_intermed_2 <= V_D_INST024_shadow_intermed_1;
DE_INST24_shadow_intermed_1 <= DE_INST24_shadow;
RIN_D_INST024_intermed_1 <= RIN.D.INST( 0 )( 24 );
RIN_D_INST024_intermed_2 <= RIN_D_INST024_intermed_1;
RIN_D_INST024_intermed_3 <= RIN_D_INST024_intermed_2;
R_D_INST024_intermed_1 <= R.D.INST ( 0 )( 24 );
R_D_INST024_intermed_1 <= R.D.INST( 0 )( 24 );
R_D_INST024_intermed_2 <= R_D_INST024_intermed_1;
RIN_A_CTRL_PC31DOWNTO4_intermed_1 <= RIN.A.CTRL.PC( 31 DOWNTO 4 );
RIN_A_CTRL_PC31DOWNTO4_intermed_2 <= RIN_A_CTRL_PC31DOWNTO4_intermed_1;
RIN_A_CTRL_PC31DOWNTO4_intermed_3 <= RIN_A_CTRL_PC31DOWNTO4_intermed_2;
RIN_A_CTRL_PC31DOWNTO4_intermed_4 <= RIN_A_CTRL_PC31DOWNTO4_intermed_3;
R_A_CTRL_PC31DOWNTO4_intermed_1 <= R.A.CTRL.PC( 31 DOWNTO 4 );
R_A_CTRL_PC31DOWNTO4_intermed_2 <= R_A_CTRL_PC31DOWNTO4_intermed_1;
R_A_CTRL_PC31DOWNTO4_intermed_3 <= R_A_CTRL_PC31DOWNTO4_intermed_2;
R_D_PC31DOWNTO4_intermed_1 <= R.D.PC( 31 DOWNTO 4 );
R_D_PC31DOWNTO4_intermed_2 <= R_D_PC31DOWNTO4_intermed_1;
R_D_PC31DOWNTO4_intermed_3 <= R_D_PC31DOWNTO4_intermed_2;
R_D_PC31DOWNTO4_intermed_4 <= R_D_PC31DOWNTO4_intermed_3;
RIN_X_CTRL_PC31DOWNTO4_intermed_1 <= RIN.X.CTRL.PC( 31 DOWNTO 4 );
V_D_PC31DOWNTO4_shadow_intermed_1 <= V_D_PC31DOWNTO4_shadow;
V_D_PC31DOWNTO4_shadow_intermed_2 <= V_D_PC31DOWNTO4_shadow_intermed_1;
V_D_PC31DOWNTO4_shadow_intermed_3 <= V_D_PC31DOWNTO4_shadow_intermed_2;
V_D_PC31DOWNTO4_shadow_intermed_4 <= V_D_PC31DOWNTO4_shadow_intermed_3;
V_D_PC31DOWNTO4_shadow_intermed_5 <= V_D_PC31DOWNTO4_shadow_intermed_4;
V_E_CTRL_PC31DOWNTO4_shadow_intermed_1 <= V_E_CTRL_PC31DOWNTO4_shadow;
V_E_CTRL_PC31DOWNTO4_shadow_intermed_2 <= V_E_CTRL_PC31DOWNTO4_shadow_intermed_1;
V_E_CTRL_PC31DOWNTO4_shadow_intermed_3 <= V_E_CTRL_PC31DOWNTO4_shadow_intermed_2;
RIN_M_CTRL_PC31DOWNTO4_intermed_1 <= RIN.M.CTRL.PC( 31 DOWNTO 4 );
RIN_M_CTRL_PC31DOWNTO4_intermed_2 <= RIN_M_CTRL_PC31DOWNTO4_intermed_1;
V_M_CTRL_PC31DOWNTO4_shadow_intermed_1 <= V_M_CTRL_PC31DOWNTO4_shadow;
V_M_CTRL_PC31DOWNTO4_shadow_intermed_2 <= V_M_CTRL_PC31DOWNTO4_shadow_intermed_1;
R_M_CTRL_PC31DOWNTO4_intermed_1 <= R.M.CTRL.PC( 31 DOWNTO 4 );
RIN_D_PC31DOWNTO4_intermed_1 <= RIN.D.PC( 31 DOWNTO 4 );
RIN_D_PC31DOWNTO4_intermed_2 <= RIN_D_PC31DOWNTO4_intermed_1;
RIN_D_PC31DOWNTO4_intermed_3 <= RIN_D_PC31DOWNTO4_intermed_2;
RIN_D_PC31DOWNTO4_intermed_4 <= RIN_D_PC31DOWNTO4_intermed_3;
RIN_D_PC31DOWNTO4_intermed_5 <= RIN_D_PC31DOWNTO4_intermed_4;
RIN_E_CTRL_PC31DOWNTO4_intermed_1 <= RIN.E.CTRL.PC( 31 DOWNTO 4 );
RIN_E_CTRL_PC31DOWNTO4_intermed_2 <= RIN_E_CTRL_PC31DOWNTO4_intermed_1;
RIN_E_CTRL_PC31DOWNTO4_intermed_3 <= RIN_E_CTRL_PC31DOWNTO4_intermed_2;
V_A_CTRL_PC31DOWNTO4_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO4_shadow;
V_A_CTRL_PC31DOWNTO4_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO4_shadow_intermed_1;
V_A_CTRL_PC31DOWNTO4_shadow_intermed_3 <= V_A_CTRL_PC31DOWNTO4_shadow_intermed_2;
V_A_CTRL_PC31DOWNTO4_shadow_intermed_4 <= V_A_CTRL_PC31DOWNTO4_shadow_intermed_3;
R_E_CTRL_PC31DOWNTO4_intermed_1 <= R.E.CTRL.PC( 31 DOWNTO 4 );
R_E_CTRL_PC31DOWNTO4_intermed_2 <= R_E_CTRL_PC31DOWNTO4_intermed_1;
R_D_PC3DOWNTO2_intermed_1 <= R.D.PC( 3 DOWNTO 2 );
R_D_PC3DOWNTO2_intermed_2 <= R_D_PC3DOWNTO2_intermed_1;
R_D_PC3DOWNTO2_intermed_3 <= R_D_PC3DOWNTO2_intermed_2;
R_D_PC3DOWNTO2_intermed_4 <= R_D_PC3DOWNTO2_intermed_3;
V_D_PC3DOWNTO2_shadow_intermed_1 <= V_D_PC3DOWNTO2_shadow;
V_D_PC3DOWNTO2_shadow_intermed_2 <= V_D_PC3DOWNTO2_shadow_intermed_1;
V_D_PC3DOWNTO2_shadow_intermed_3 <= V_D_PC3DOWNTO2_shadow_intermed_2;
V_D_PC3DOWNTO2_shadow_intermed_4 <= V_D_PC3DOWNTO2_shadow_intermed_3;
V_D_PC3DOWNTO2_shadow_intermed_5 <= V_D_PC3DOWNTO2_shadow_intermed_4;
RIN_D_PC3DOWNTO2_intermed_1 <= RIN.D.PC( 3 DOWNTO 2 );
RIN_D_PC3DOWNTO2_intermed_2 <= RIN_D_PC3DOWNTO2_intermed_1;
RIN_D_PC3DOWNTO2_intermed_3 <= RIN_D_PC3DOWNTO2_intermed_2;
RIN_D_PC3DOWNTO2_intermed_4 <= RIN_D_PC3DOWNTO2_intermed_3;
RIN_D_PC3DOWNTO2_intermed_5 <= RIN_D_PC3DOWNTO2_intermed_4;
R_M_CTRL_PC3DOWNTO2_intermed_1 <= R.M.CTRL.PC( 3 DOWNTO 2 );
R_E_CTRL_PC3DOWNTO2_intermed_1 <= R.E.CTRL.PC( 3 DOWNTO 2 );
R_E_CTRL_PC3DOWNTO2_intermed_2 <= R_E_CTRL_PC3DOWNTO2_intermed_1;
V_E_CTRL_PC3DOWNTO2_shadow_intermed_1 <= V_E_CTRL_PC3DOWNTO2_shadow;
V_E_CTRL_PC3DOWNTO2_shadow_intermed_2 <= V_E_CTRL_PC3DOWNTO2_shadow_intermed_1;
V_E_CTRL_PC3DOWNTO2_shadow_intermed_3 <= V_E_CTRL_PC3DOWNTO2_shadow_intermed_2;
RIN_X_CTRL_PC3DOWNTO2_intermed_1 <= RIN.X.CTRL.PC( 3 DOWNTO 2 );
R_A_CTRL_PC3DOWNTO2_intermed_1 <= R.A.CTRL.PC( 3 DOWNTO 2 );
R_A_CTRL_PC3DOWNTO2_intermed_2 <= R_A_CTRL_PC3DOWNTO2_intermed_1;
R_A_CTRL_PC3DOWNTO2_intermed_3 <= R_A_CTRL_PC3DOWNTO2_intermed_2;
RIN_M_CTRL_PC3DOWNTO2_intermed_1 <= RIN.M.CTRL.PC( 3 DOWNTO 2 );
RIN_M_CTRL_PC3DOWNTO2_intermed_2 <= RIN_M_CTRL_PC3DOWNTO2_intermed_1;
RIN_A_CTRL_PC3DOWNTO2_intermed_1 <= RIN.A.CTRL.PC( 3 DOWNTO 2 );
RIN_A_CTRL_PC3DOWNTO2_intermed_2 <= RIN_A_CTRL_PC3DOWNTO2_intermed_1;
RIN_A_CTRL_PC3DOWNTO2_intermed_3 <= RIN_A_CTRL_PC3DOWNTO2_intermed_2;
RIN_A_CTRL_PC3DOWNTO2_intermed_4 <= RIN_A_CTRL_PC3DOWNTO2_intermed_3;
V_A_CTRL_PC3DOWNTO2_shadow_intermed_1 <= V_A_CTRL_PC3DOWNTO2_shadow;
V_A_CTRL_PC3DOWNTO2_shadow_intermed_2 <= V_A_CTRL_PC3DOWNTO2_shadow_intermed_1;
V_A_CTRL_PC3DOWNTO2_shadow_intermed_3 <= V_A_CTRL_PC3DOWNTO2_shadow_intermed_2;
V_A_CTRL_PC3DOWNTO2_shadow_intermed_4 <= V_A_CTRL_PC3DOWNTO2_shadow_intermed_3;
V_M_CTRL_PC3DOWNTO2_shadow_intermed_1 <= V_M_CTRL_PC3DOWNTO2_shadow;
V_M_CTRL_PC3DOWNTO2_shadow_intermed_2 <= V_M_CTRL_PC3DOWNTO2_shadow_intermed_1;
RIN_E_CTRL_PC3DOWNTO2_intermed_1 <= RIN.E.CTRL.PC( 3 DOWNTO 2 );
RIN_E_CTRL_PC3DOWNTO2_intermed_2 <= RIN_E_CTRL_PC3DOWNTO2_intermed_1;
RIN_E_CTRL_PC3DOWNTO2_intermed_3 <= RIN_E_CTRL_PC3DOWNTO2_intermed_2;
RIN_E_CTRL_RD6DOWNTO0_intermed_1 <= RIN.E.CTRL.RD( 6 DOWNTO 0 );
RIN_E_CTRL_RD6DOWNTO0_intermed_2 <= RIN_E_CTRL_RD6DOWNTO0_intermed_1;
RIN_M_CTRL_RD6DOWNTO0_intermed_1 <= RIN.M.CTRL.RD( 6 DOWNTO 0 );
R_E_CTRL_RD6DOWNTO0_intermed_1 <= R.E.CTRL.RD( 6 DOWNTO 0 );
V_E_CTRL_RD6DOWNTO0_shadow_intermed_1 <= V_E_CTRL_RD6DOWNTO0_shadow;
V_E_CTRL_RD6DOWNTO0_shadow_intermed_2 <= V_E_CTRL_RD6DOWNTO0_shadow_intermed_1;
V_A_CTRL_RD6DOWNTO0_shadow_intermed_1 <= V_A_CTRL_RD6DOWNTO0_shadow;
V_A_CTRL_RD6DOWNTO0_shadow_intermed_2 <= V_A_CTRL_RD6DOWNTO0_shadow_intermed_1;
V_A_CTRL_RD6DOWNTO0_shadow_intermed_3 <= V_A_CTRL_RD6DOWNTO0_shadow_intermed_2;
R_A_CTRL_RD6DOWNTO0_intermed_1 <= R.A.CTRL.RD( 6 DOWNTO 0 );
R_A_CTRL_RD6DOWNTO0_intermed_2 <= R_A_CTRL_RD6DOWNTO0_intermed_1;
RIN_A_CTRL_RD6DOWNTO0_intermed_1 <= RIN.A.CTRL.RD( 6 DOWNTO 0 );
RIN_A_CTRL_RD6DOWNTO0_intermed_2 <= RIN_A_CTRL_RD6DOWNTO0_intermed_1;
RIN_A_CTRL_RD6DOWNTO0_intermed_3 <= RIN_A_CTRL_RD6DOWNTO0_intermed_2;
RIN_A_CTRL_TT_intermed_1 <= RIN.A.CTRL.TT;
RIN_A_CTRL_TT_intermed_2 <= RIN_A_CTRL_TT_intermed_1;
R_A_CTRL_TT_intermed_1 <= R.A.CTRL.TT;
RIN_E_CTRL_TT_intermed_1 <= RIN.E.CTRL.TT;
V_A_CTRL_TT_shadow_intermed_1 <= V_A_CTRL_TT_shadow;
V_A_CTRL_TT_shadow_intermed_2 <= V_A_CTRL_TT_shadow_intermed_1;
V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_1 <= V_X_RESULT6DOWNTO03DOWNTO0_shadow;
V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_2 <= V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_1;
R_X_RESULT6DOWNTO03DOWNTO0_intermed_1 <= R.X.RESULT( 6 DOWNTO 0 )( 3 DOWNTO 0 );
RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_1 <= RIN.X.RESULT( 6 DOWNTO 0 )( 3 DOWNTO 0 );
RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_2 <= RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_1;
RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_1 <= RIN.X.RESULT ( 6 DOWNTO 0 )( 3 DOWNTO 0 );
R_M_CTRL_TT3DOWNTO0_intermed_1 <= R.M.CTRL.TT( 3 DOWNTO 0 );
R_A_CTRL_TT3DOWNTO0_intermed_1 <= R.A.CTRL.TT( 3 DOWNTO 0 );
R_A_CTRL_TT3DOWNTO0_intermed_2 <= R_A_CTRL_TT3DOWNTO0_intermed_1;
R_A_CTRL_TT3DOWNTO0_intermed_3 <= R_A_CTRL_TT3DOWNTO0_intermed_2;
RIN_A_CTRL_TT3DOWNTO0_intermed_1 <= RIN.A.CTRL.TT( 3 DOWNTO 0 );
RIN_A_CTRL_TT3DOWNTO0_intermed_2 <= RIN_A_CTRL_TT3DOWNTO0_intermed_1;
RIN_A_CTRL_TT3DOWNTO0_intermed_3 <= RIN_A_CTRL_TT3DOWNTO0_intermed_2;
RIN_A_CTRL_TT3DOWNTO0_intermed_4 <= RIN_A_CTRL_TT3DOWNTO0_intermed_3;
V_A_CTRL_TT3DOWNTO0_shadow_intermed_1 <= V_A_CTRL_TT3DOWNTO0_shadow;
V_A_CTRL_TT3DOWNTO0_shadow_intermed_2 <= V_A_CTRL_TT3DOWNTO0_shadow_intermed_1;
V_A_CTRL_TT3DOWNTO0_shadow_intermed_3 <= V_A_CTRL_TT3DOWNTO0_shadow_intermed_2;
V_A_CTRL_TT3DOWNTO0_shadow_intermed_4 <= V_A_CTRL_TT3DOWNTO0_shadow_intermed_3;
R_E_CTRL_TT3DOWNTO0_intermed_1 <= R.E.CTRL.TT( 3 DOWNTO 0 );
R_E_CTRL_TT3DOWNTO0_intermed_2 <= R_E_CTRL_TT3DOWNTO0_intermed_1;
RIN_M_CTRL_TT3DOWNTO0_intermed_1 <= RIN.M.CTRL.TT( 3 DOWNTO 0 );
RIN_M_CTRL_TT3DOWNTO0_intermed_2 <= RIN_M_CTRL_TT3DOWNTO0_intermed_1;
V_M_CTRL_TT3DOWNTO0_shadow_intermed_1 <= V_M_CTRL_TT3DOWNTO0_shadow;
V_M_CTRL_TT3DOWNTO0_shadow_intermed_2 <= V_M_CTRL_TT3DOWNTO0_shadow_intermed_1;
V_E_CTRL_TT3DOWNTO0_shadow_intermed_1 <= V_E_CTRL_TT3DOWNTO0_shadow;
V_E_CTRL_TT3DOWNTO0_shadow_intermed_2 <= V_E_CTRL_TT3DOWNTO0_shadow_intermed_1;
V_E_CTRL_TT3DOWNTO0_shadow_intermed_3 <= V_E_CTRL_TT3DOWNTO0_shadow_intermed_2;
RIN_X_CTRL_TT3DOWNTO0_intermed_1 <= RIN.X.CTRL.TT( 3 DOWNTO 0 );
RIN_E_CTRL_TT3DOWNTO0_intermed_1 <= RIN.E.CTRL.TT( 3 DOWNTO 0 );
RIN_E_CTRL_TT3DOWNTO0_intermed_2 <= RIN_E_CTRL_TT3DOWNTO0_intermed_1;
RIN_E_CTRL_TT3DOWNTO0_intermed_3 <= RIN_E_CTRL_TT3DOWNTO0_intermed_2;
R_D_INST019_intermed_1 <= R.D.INST( 0 )( 19 );
V_D_INST019_shadow_intermed_1 <= V_D_INST019_shadow;
V_D_INST019_shadow_intermed_2 <= V_D_INST019_shadow_intermed_1;
RIN_D_INST019_intermed_1 <= RIN.D.INST ( 0 )( 19 );
RIN_D_INST019_intermed_1 <= RIN.D.INST( 0 )( 19 );
RIN_D_INST019_intermed_2 <= RIN_D_INST019_intermed_1;
R_M_CTRL_PC31DOWNTO12_intermed_1 <= R.M.CTRL.PC( 31 DOWNTO 12 );
V_D_PC31DOWNTO12_shadow_intermed_1 <= V_D_PC31DOWNTO12_shadow;
V_D_PC31DOWNTO12_shadow_intermed_2 <= V_D_PC31DOWNTO12_shadow_intermed_1;
V_D_PC31DOWNTO12_shadow_intermed_3 <= V_D_PC31DOWNTO12_shadow_intermed_2;
V_D_PC31DOWNTO12_shadow_intermed_4 <= V_D_PC31DOWNTO12_shadow_intermed_3;
V_D_PC31DOWNTO12_shadow_intermed_5 <= V_D_PC31DOWNTO12_shadow_intermed_4;
V_A_CTRL_PC31DOWNTO12_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO12_shadow;
V_A_CTRL_PC31DOWNTO12_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO12_shadow_intermed_1;
V_A_CTRL_PC31DOWNTO12_shadow_intermed_3 <= V_A_CTRL_PC31DOWNTO12_shadow_intermed_2;
V_A_CTRL_PC31DOWNTO12_shadow_intermed_4 <= V_A_CTRL_PC31DOWNTO12_shadow_intermed_3;
V_E_CTRL_PC31DOWNTO12_shadow_intermed_1 <= V_E_CTRL_PC31DOWNTO12_shadow;
V_E_CTRL_PC31DOWNTO12_shadow_intermed_2 <= V_E_CTRL_PC31DOWNTO12_shadow_intermed_1;
V_E_CTRL_PC31DOWNTO12_shadow_intermed_3 <= V_E_CTRL_PC31DOWNTO12_shadow_intermed_2;
R_A_CTRL_PC31DOWNTO12_intermed_1 <= R.A.CTRL.PC( 31 DOWNTO 12 );
R_A_CTRL_PC31DOWNTO12_intermed_2 <= R_A_CTRL_PC31DOWNTO12_intermed_1;
R_A_CTRL_PC31DOWNTO12_intermed_3 <= R_A_CTRL_PC31DOWNTO12_intermed_2;
R_E_CTRL_PC31DOWNTO12_intermed_1 <= R.E.CTRL.PC( 31 DOWNTO 12 );
R_E_CTRL_PC31DOWNTO12_intermed_2 <= R_E_CTRL_PC31DOWNTO12_intermed_1;
RIN_A_CTRL_PC31DOWNTO12_intermed_1 <= RIN.A.CTRL.PC( 31 DOWNTO 12 );
RIN_A_CTRL_PC31DOWNTO12_intermed_2 <= RIN_A_CTRL_PC31DOWNTO12_intermed_1;
RIN_A_CTRL_PC31DOWNTO12_intermed_3 <= RIN_A_CTRL_PC31DOWNTO12_intermed_2;
RIN_A_CTRL_PC31DOWNTO12_intermed_4 <= RIN_A_CTRL_PC31DOWNTO12_intermed_3;
RIN_E_CTRL_PC31DOWNTO12_intermed_1 <= RIN.E.CTRL.PC( 31 DOWNTO 12 );
RIN_E_CTRL_PC31DOWNTO12_intermed_2 <= RIN_E_CTRL_PC31DOWNTO12_intermed_1;
RIN_E_CTRL_PC31DOWNTO12_intermed_3 <= RIN_E_CTRL_PC31DOWNTO12_intermed_2;
RIN_M_CTRL_PC31DOWNTO12_intermed_1 <= RIN.M.CTRL.PC( 31 DOWNTO 12 );
RIN_M_CTRL_PC31DOWNTO12_intermed_2 <= RIN_M_CTRL_PC31DOWNTO12_intermed_1;
R_D_PC31DOWNTO12_intermed_1 <= R.D.PC( 31 DOWNTO 12 );
R_D_PC31DOWNTO12_intermed_2 <= R_D_PC31DOWNTO12_intermed_1;
R_D_PC31DOWNTO12_intermed_3 <= R_D_PC31DOWNTO12_intermed_2;
R_D_PC31DOWNTO12_intermed_4 <= R_D_PC31DOWNTO12_intermed_3;
RIN_X_CTRL_PC31DOWNTO12_intermed_1 <= RIN.X.CTRL.PC( 31 DOWNTO 12 );
RIN_D_PC31DOWNTO12_intermed_1 <= RIN.D.PC( 31 DOWNTO 12 );
RIN_D_PC31DOWNTO12_intermed_2 <= RIN_D_PC31DOWNTO12_intermed_1;
RIN_D_PC31DOWNTO12_intermed_3 <= RIN_D_PC31DOWNTO12_intermed_2;
RIN_D_PC31DOWNTO12_intermed_4 <= RIN_D_PC31DOWNTO12_intermed_3;
RIN_D_PC31DOWNTO12_intermed_5 <= RIN_D_PC31DOWNTO12_intermed_4;
V_M_CTRL_PC31DOWNTO12_shadow_intermed_1 <= V_M_CTRL_PC31DOWNTO12_shadow;
V_M_CTRL_PC31DOWNTO12_shadow_intermed_2 <= V_M_CTRL_PC31DOWNTO12_shadow_intermed_1;
V_A_CTRL_RD7DOWNTO0_shadow_intermed_1 <= V_A_CTRL_RD7DOWNTO0_shadow;
V_A_CTRL_RD7DOWNTO0_shadow_intermed_2 <= V_A_CTRL_RD7DOWNTO0_shadow_intermed_1;
RIN_A_CTRL_RD7DOWNTO0_intermed_1 <= RIN.A.CTRL.RD ( 7 DOWNTO 0 );
RIN_A_CTRL_RD7DOWNTO0_intermed_2 <= RIN_A_CTRL_RD7DOWNTO0_intermed_1;
R_A_CTRL_RD7DOWNTO0_intermed_1 <= R.A.CTRL.RD ( 7 DOWNTO 0 );
RIN_E_CTRL_RD7DOWNTO0_intermed_1 <= RIN.E.CTRL.RD ( 7 DOWNTO 0 );
RIN_D_PC_intermed_1 <= RIN.D.PC;
RIN_D_PC_intermed_2 <= RIN_D_PC_intermed_1;
RIN_D_PC_intermed_3 <= RIN_D_PC_intermed_2;
RIN_A_CTRL_PC_intermed_1 <= RIN.A.CTRL.PC;
RIN_A_CTRL_PC_intermed_2 <= RIN_A_CTRL_PC_intermed_1;
R_A_CTRL_PC_intermed_1 <= R.A.CTRL.PC;
V_A_CTRL_PC_shadow_intermed_1 <= V_A_CTRL_PC_shadow;
V_A_CTRL_PC_shadow_intermed_2 <= V_A_CTRL_PC_shadow_intermed_1;
R_D_PC_intermed_1 <= R.D.PC;
R_D_PC_intermed_2 <= R_D_PC_intermed_1;
RIN_E_CTRL_PC_intermed_1 <= RIN.E.CTRL.PC;
V_D_PC_shadow_intermed_1 <= V_D_PC_shadow;
V_D_PC_shadow_intermed_2 <= V_D_PC_shadow_intermed_1;
V_D_PC_shadow_intermed_3 <= V_D_PC_shadow_intermed_2;
V_D_PC31DOWNTO2_shadow_intermed_1 <= V_D_PC31DOWNTO2_shadow;
V_D_PC31DOWNTO2_shadow_intermed_2 <= V_D_PC31DOWNTO2_shadow_intermed_1;
V_D_PC31DOWNTO2_shadow_intermed_3 <= V_D_PC31DOWNTO2_shadow_intermed_2;
RIN_D_PC31DOWNTO2_intermed_1 <= RIN.D.PC( 31 DOWNTO 2 );
RIN_D_PC31DOWNTO2_intermed_2 <= RIN_D_PC31DOWNTO2_intermed_1;
RIN_D_PC31DOWNTO2_intermed_3 <= RIN_D_PC31DOWNTO2_intermed_2;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO2_shadow;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_1;
R_D_PC31DOWNTO2_intermed_1 <= R.D.PC( 31 DOWNTO 2 );
R_D_PC31DOWNTO2_intermed_2 <= R_D_PC31DOWNTO2_intermed_1;
RIN_A_CTRL_PC31DOWNTO2_intermed_1 <= RIN.A.CTRL.PC( 31 DOWNTO 2 );
RIN_A_CTRL_PC31DOWNTO2_intermed_2 <= RIN_A_CTRL_PC31DOWNTO2_intermed_1;
R_A_CTRL_PC31DOWNTO2_intermed_1 <= R.A.CTRL.PC( 31 DOWNTO 2 );
RIN_E_CTRL_PC31DOWNTO2_intermed_1 <= RIN.E.CTRL.PC( 31 DOWNTO 2 );
RIN_A_CTRL_PC31DOWNTO4_intermed_1 <= RIN.A.CTRL.PC( 31 DOWNTO 4 );
RIN_A_CTRL_PC31DOWNTO4_intermed_2 <= RIN_A_CTRL_PC31DOWNTO4_intermed_1;
RIN_A_CTRL_PC31DOWNTO4_intermed_3 <= RIN_A_CTRL_PC31DOWNTO4_intermed_2;
R_A_CTRL_PC31DOWNTO4_intermed_1 <= R.A.CTRL.PC( 31 DOWNTO 4 );
R_A_CTRL_PC31DOWNTO4_intermed_2 <= R_A_CTRL_PC31DOWNTO4_intermed_1;
R_D_PC31DOWNTO4_intermed_1 <= R.D.PC( 31 DOWNTO 4 );
R_D_PC31DOWNTO4_intermed_2 <= R_D_PC31DOWNTO4_intermed_1;
R_D_PC31DOWNTO4_intermed_3 <= R_D_PC31DOWNTO4_intermed_2;
V_D_PC31DOWNTO4_shadow_intermed_1 <= V_D_PC31DOWNTO4_shadow;
V_D_PC31DOWNTO4_shadow_intermed_2 <= V_D_PC31DOWNTO4_shadow_intermed_1;
V_D_PC31DOWNTO4_shadow_intermed_3 <= V_D_PC31DOWNTO4_shadow_intermed_2;
V_D_PC31DOWNTO4_shadow_intermed_4 <= V_D_PC31DOWNTO4_shadow_intermed_3;
V_E_CTRL_PC31DOWNTO4_shadow_intermed_1 <= V_E_CTRL_PC31DOWNTO4_shadow;
V_E_CTRL_PC31DOWNTO4_shadow_intermed_2 <= V_E_CTRL_PC31DOWNTO4_shadow_intermed_1;
RIN_M_CTRL_PC31DOWNTO4_intermed_1 <= RIN.M.CTRL.PC( 31 DOWNTO 4 );
RIN_D_PC31DOWNTO4_intermed_1 <= RIN.D.PC( 31 DOWNTO 4 );
RIN_D_PC31DOWNTO4_intermed_2 <= RIN_D_PC31DOWNTO4_intermed_1;
RIN_D_PC31DOWNTO4_intermed_3 <= RIN_D_PC31DOWNTO4_intermed_2;
RIN_D_PC31DOWNTO4_intermed_4 <= RIN_D_PC31DOWNTO4_intermed_3;
RIN_E_CTRL_PC31DOWNTO4_intermed_1 <= RIN.E.CTRL.PC( 31 DOWNTO 4 );
RIN_E_CTRL_PC31DOWNTO4_intermed_2 <= RIN_E_CTRL_PC31DOWNTO4_intermed_1;
V_A_CTRL_PC31DOWNTO4_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO4_shadow;
V_A_CTRL_PC31DOWNTO4_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO4_shadow_intermed_1;
V_A_CTRL_PC31DOWNTO4_shadow_intermed_3 <= V_A_CTRL_PC31DOWNTO4_shadow_intermed_2;
R_E_CTRL_PC31DOWNTO4_intermed_1 <= R.E.CTRL.PC( 31 DOWNTO 4 );
R_D_PC3DOWNTO2_intermed_1 <= R.D.PC( 3 DOWNTO 2 );
R_D_PC3DOWNTO2_intermed_2 <= R_D_PC3DOWNTO2_intermed_1;
R_D_PC3DOWNTO2_intermed_3 <= R_D_PC3DOWNTO2_intermed_2;
V_D_PC3DOWNTO2_shadow_intermed_1 <= V_D_PC3DOWNTO2_shadow;
V_D_PC3DOWNTO2_shadow_intermed_2 <= V_D_PC3DOWNTO2_shadow_intermed_1;
V_D_PC3DOWNTO2_shadow_intermed_3 <= V_D_PC3DOWNTO2_shadow_intermed_2;
V_D_PC3DOWNTO2_shadow_intermed_4 <= V_D_PC3DOWNTO2_shadow_intermed_3;
RIN_D_PC3DOWNTO2_intermed_1 <= RIN.D.PC( 3 DOWNTO 2 );
RIN_D_PC3DOWNTO2_intermed_2 <= RIN_D_PC3DOWNTO2_intermed_1;
RIN_D_PC3DOWNTO2_intermed_3 <= RIN_D_PC3DOWNTO2_intermed_2;
RIN_D_PC3DOWNTO2_intermed_4 <= RIN_D_PC3DOWNTO2_intermed_3;
R_E_CTRL_PC3DOWNTO2_intermed_1 <= R.E.CTRL.PC( 3 DOWNTO 2 );
V_E_CTRL_PC3DOWNTO2_shadow_intermed_1 <= V_E_CTRL_PC3DOWNTO2_shadow;
V_E_CTRL_PC3DOWNTO2_shadow_intermed_2 <= V_E_CTRL_PC3DOWNTO2_shadow_intermed_1;
R_A_CTRL_PC3DOWNTO2_intermed_1 <= R.A.CTRL.PC( 3 DOWNTO 2 );
R_A_CTRL_PC3DOWNTO2_intermed_2 <= R_A_CTRL_PC3DOWNTO2_intermed_1;
RIN_M_CTRL_PC3DOWNTO2_intermed_1 <= RIN.M.CTRL.PC( 3 DOWNTO 2 );
RIN_A_CTRL_PC3DOWNTO2_intermed_1 <= RIN.A.CTRL.PC( 3 DOWNTO 2 );
RIN_A_CTRL_PC3DOWNTO2_intermed_2 <= RIN_A_CTRL_PC3DOWNTO2_intermed_1;
RIN_A_CTRL_PC3DOWNTO2_intermed_3 <= RIN_A_CTRL_PC3DOWNTO2_intermed_2;
V_A_CTRL_PC3DOWNTO2_shadow_intermed_1 <= V_A_CTRL_PC3DOWNTO2_shadow;
V_A_CTRL_PC3DOWNTO2_shadow_intermed_2 <= V_A_CTRL_PC3DOWNTO2_shadow_intermed_1;
V_A_CTRL_PC3DOWNTO2_shadow_intermed_3 <= V_A_CTRL_PC3DOWNTO2_shadow_intermed_2;
RIN_E_CTRL_PC3DOWNTO2_intermed_1 <= RIN.E.CTRL.PC( 3 DOWNTO 2 );
RIN_E_CTRL_PC3DOWNTO2_intermed_2 <= RIN_E_CTRL_PC3DOWNTO2_intermed_1;
RIN_E_CTRL_RD6DOWNTO0_intermed_1 <= RIN.E.CTRL.RD( 6 DOWNTO 0 );
V_A_CTRL_RD6DOWNTO0_shadow_intermed_1 <= V_A_CTRL_RD6DOWNTO0_shadow;
V_A_CTRL_RD6DOWNTO0_shadow_intermed_2 <= V_A_CTRL_RD6DOWNTO0_shadow_intermed_1;
R_A_CTRL_RD6DOWNTO0_intermed_1 <= R.A.CTRL.RD( 6 DOWNTO 0 );
RIN_A_CTRL_RD6DOWNTO0_intermed_1 <= RIN.A.CTRL.RD( 6 DOWNTO 0 );
RIN_A_CTRL_RD6DOWNTO0_intermed_2 <= RIN_A_CTRL_RD6DOWNTO0_intermed_1;
R_A_CTRL_TT3DOWNTO0_intermed_1 <= R.A.CTRL.TT( 3 DOWNTO 0 );
R_A_CTRL_TT3DOWNTO0_intermed_2 <= R_A_CTRL_TT3DOWNTO0_intermed_1;
RIN_A_CTRL_TT3DOWNTO0_intermed_1 <= RIN.A.CTRL.TT( 3 DOWNTO 0 );
RIN_A_CTRL_TT3DOWNTO0_intermed_2 <= RIN_A_CTRL_TT3DOWNTO0_intermed_1;
RIN_A_CTRL_TT3DOWNTO0_intermed_3 <= RIN_A_CTRL_TT3DOWNTO0_intermed_2;
V_A_CTRL_TT3DOWNTO0_shadow_intermed_1 <= V_A_CTRL_TT3DOWNTO0_shadow;
V_A_CTRL_TT3DOWNTO0_shadow_intermed_2 <= V_A_CTRL_TT3DOWNTO0_shadow_intermed_1;
V_A_CTRL_TT3DOWNTO0_shadow_intermed_3 <= V_A_CTRL_TT3DOWNTO0_shadow_intermed_2;
R_E_CTRL_TT3DOWNTO0_intermed_1 <= R.E.CTRL.TT( 3 DOWNTO 0 );
RIN_M_CTRL_TT3DOWNTO0_intermed_1 <= RIN.M.CTRL.TT( 3 DOWNTO 0 );
V_E_CTRL_TT3DOWNTO0_shadow_intermed_1 <= V_E_CTRL_TT3DOWNTO0_shadow;
V_E_CTRL_TT3DOWNTO0_shadow_intermed_2 <= V_E_CTRL_TT3DOWNTO0_shadow_intermed_1;
RIN_E_CTRL_TT3DOWNTO0_intermed_1 <= RIN.E.CTRL.TT( 3 DOWNTO 0 );
RIN_E_CTRL_TT3DOWNTO0_intermed_2 <= RIN_E_CTRL_TT3DOWNTO0_intermed_1;
RIN_D_INST020_intermed_1 <= RIN.D.INST( 0 )( 20 );
RIN_D_INST020_intermed_2 <= RIN_D_INST020_intermed_1;
RIN_D_INST020_intermed_1 <= RIN.D.INST ( 0 )( 20 );
V_D_INST020_shadow_intermed_1 <= V_D_INST020_shadow;
V_D_INST020_shadow_intermed_2 <= V_D_INST020_shadow_intermed_1;
R_D_INST020_intermed_1 <= R.D.INST( 0 )( 20 );
RIN_D_INST024_intermed_1 <= RIN.D.INST ( 0 )( 24 );
V_D_INST024_shadow_intermed_1 <= V_D_INST024_shadow;
V_D_INST024_shadow_intermed_2 <= V_D_INST024_shadow_intermed_1;
RIN_D_INST024_intermed_1 <= RIN.D.INST( 0 )( 24 );
RIN_D_INST024_intermed_2 <= RIN_D_INST024_intermed_1;
R_D_INST024_intermed_1 <= R.D.INST( 0 )( 24 );
V_D_PC31DOWNTO12_shadow_intermed_1 <= V_D_PC31DOWNTO12_shadow;
V_D_PC31DOWNTO12_shadow_intermed_2 <= V_D_PC31DOWNTO12_shadow_intermed_1;
V_D_PC31DOWNTO12_shadow_intermed_3 <= V_D_PC31DOWNTO12_shadow_intermed_2;
V_D_PC31DOWNTO12_shadow_intermed_4 <= V_D_PC31DOWNTO12_shadow_intermed_3;
V_A_CTRL_PC31DOWNTO12_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO12_shadow;
V_A_CTRL_PC31DOWNTO12_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO12_shadow_intermed_1;
V_A_CTRL_PC31DOWNTO12_shadow_intermed_3 <= V_A_CTRL_PC31DOWNTO12_shadow_intermed_2;
V_E_CTRL_PC31DOWNTO12_shadow_intermed_1 <= V_E_CTRL_PC31DOWNTO12_shadow;
V_E_CTRL_PC31DOWNTO12_shadow_intermed_2 <= V_E_CTRL_PC31DOWNTO12_shadow_intermed_1;
R_A_CTRL_PC31DOWNTO12_intermed_1 <= R.A.CTRL.PC( 31 DOWNTO 12 );
R_A_CTRL_PC31DOWNTO12_intermed_2 <= R_A_CTRL_PC31DOWNTO12_intermed_1;
R_E_CTRL_PC31DOWNTO12_intermed_1 <= R.E.CTRL.PC( 31 DOWNTO 12 );
RIN_A_CTRL_PC31DOWNTO12_intermed_1 <= RIN.A.CTRL.PC( 31 DOWNTO 12 );
RIN_A_CTRL_PC31DOWNTO12_intermed_2 <= RIN_A_CTRL_PC31DOWNTO12_intermed_1;
RIN_A_CTRL_PC31DOWNTO12_intermed_3 <= RIN_A_CTRL_PC31DOWNTO12_intermed_2;
RIN_E_CTRL_PC31DOWNTO12_intermed_1 <= RIN.E.CTRL.PC( 31 DOWNTO 12 );
RIN_E_CTRL_PC31DOWNTO12_intermed_2 <= RIN_E_CTRL_PC31DOWNTO12_intermed_1;
RIN_M_CTRL_PC31DOWNTO12_intermed_1 <= RIN.M.CTRL.PC( 31 DOWNTO 12 );
R_D_PC31DOWNTO12_intermed_1 <= R.D.PC( 31 DOWNTO 12 );
R_D_PC31DOWNTO12_intermed_2 <= R_D_PC31DOWNTO12_intermed_1;
R_D_PC31DOWNTO12_intermed_3 <= R_D_PC31DOWNTO12_intermed_2;
RIN_D_PC31DOWNTO12_intermed_1 <= RIN.D.PC( 31 DOWNTO 12 );
RIN_D_PC31DOWNTO12_intermed_2 <= RIN_D_PC31DOWNTO12_intermed_1;
RIN_D_PC31DOWNTO12_intermed_3 <= RIN_D_PC31DOWNTO12_intermed_2;
RIN_D_PC31DOWNTO12_intermed_4 <= RIN_D_PC31DOWNTO12_intermed_3;
RIN_A_CTRL_PC31DOWNTO4_intermed_1 <= RIN.A.CTRL.PC( 31 DOWNTO 4 );
RIN_A_CTRL_PC31DOWNTO4_intermed_2 <= RIN_A_CTRL_PC31DOWNTO4_intermed_1;
R_A_CTRL_PC31DOWNTO4_intermed_1 <= R.A.CTRL.PC( 31 DOWNTO 4 );
R_D_PC31DOWNTO4_intermed_1 <= R.D.PC( 31 DOWNTO 4 );
R_D_PC31DOWNTO4_intermed_2 <= R_D_PC31DOWNTO4_intermed_1;
V_D_PC31DOWNTO4_shadow_intermed_1 <= V_D_PC31DOWNTO4_shadow;
V_D_PC31DOWNTO4_shadow_intermed_2 <= V_D_PC31DOWNTO4_shadow_intermed_1;
V_D_PC31DOWNTO4_shadow_intermed_3 <= V_D_PC31DOWNTO4_shadow_intermed_2;
RIN_D_PC31DOWNTO4_intermed_1 <= RIN.D.PC( 31 DOWNTO 4 );
RIN_D_PC31DOWNTO4_intermed_2 <= RIN_D_PC31DOWNTO4_intermed_1;
RIN_D_PC31DOWNTO4_intermed_3 <= RIN_D_PC31DOWNTO4_intermed_2;
RIN_E_CTRL_PC31DOWNTO4_intermed_1 <= RIN.E.CTRL.PC( 31 DOWNTO 4 );
V_A_CTRL_PC31DOWNTO4_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO4_shadow;
V_A_CTRL_PC31DOWNTO4_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO4_shadow_intermed_1;
R_D_PC3DOWNTO2_intermed_1 <= R.D.PC( 3 DOWNTO 2 );
R_D_PC3DOWNTO2_intermed_2 <= R_D_PC3DOWNTO2_intermed_1;
V_D_PC3DOWNTO2_shadow_intermed_1 <= V_D_PC3DOWNTO2_shadow;
V_D_PC3DOWNTO2_shadow_intermed_2 <= V_D_PC3DOWNTO2_shadow_intermed_1;
V_D_PC3DOWNTO2_shadow_intermed_3 <= V_D_PC3DOWNTO2_shadow_intermed_2;
RIN_D_PC3DOWNTO2_intermed_1 <= RIN.D.PC( 3 DOWNTO 2 );
RIN_D_PC3DOWNTO2_intermed_2 <= RIN_D_PC3DOWNTO2_intermed_1;
RIN_D_PC3DOWNTO2_intermed_3 <= RIN_D_PC3DOWNTO2_intermed_2;
R_A_CTRL_PC3DOWNTO2_intermed_1 <= R.A.CTRL.PC( 3 DOWNTO 2 );
RIN_A_CTRL_PC3DOWNTO2_intermed_1 <= RIN.A.CTRL.PC( 3 DOWNTO 2 );
RIN_A_CTRL_PC3DOWNTO2_intermed_2 <= RIN_A_CTRL_PC3DOWNTO2_intermed_1;
V_A_CTRL_PC3DOWNTO2_shadow_intermed_1 <= V_A_CTRL_PC3DOWNTO2_shadow;
V_A_CTRL_PC3DOWNTO2_shadow_intermed_2 <= V_A_CTRL_PC3DOWNTO2_shadow_intermed_1;
RIN_E_CTRL_PC3DOWNTO2_intermed_1 <= RIN.E.CTRL.PC( 3 DOWNTO 2 );
R_A_CTRL_TT3DOWNTO0_intermed_1 <= R.A.CTRL.TT( 3 DOWNTO 0 );
RIN_A_CTRL_TT3DOWNTO0_intermed_1 <= RIN.A.CTRL.TT( 3 DOWNTO 0 );
RIN_A_CTRL_TT3DOWNTO0_intermed_2 <= RIN_A_CTRL_TT3DOWNTO0_intermed_1;
V_A_CTRL_TT3DOWNTO0_shadow_intermed_1 <= V_A_CTRL_TT3DOWNTO0_shadow;
V_A_CTRL_TT3DOWNTO0_shadow_intermed_2 <= V_A_CTRL_TT3DOWNTO0_shadow_intermed_1;
RIN_E_CTRL_TT3DOWNTO0_intermed_1 <= RIN.E.CTRL.TT( 3 DOWNTO 0 );
V_D_PC31DOWNTO12_shadow_intermed_1 <= V_D_PC31DOWNTO12_shadow;
V_D_PC31DOWNTO12_shadow_intermed_2 <= V_D_PC31DOWNTO12_shadow_intermed_1;
V_D_PC31DOWNTO12_shadow_intermed_3 <= V_D_PC31DOWNTO12_shadow_intermed_2;
V_A_CTRL_PC31DOWNTO12_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO12_shadow;
V_A_CTRL_PC31DOWNTO12_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO12_shadow_intermed_1;
R_A_CTRL_PC31DOWNTO12_intermed_1 <= R.A.CTRL.PC( 31 DOWNTO 12 );
RIN_A_CTRL_PC31DOWNTO12_intermed_1 <= RIN.A.CTRL.PC( 31 DOWNTO 12 );
RIN_A_CTRL_PC31DOWNTO12_intermed_2 <= RIN_A_CTRL_PC31DOWNTO12_intermed_1;
RIN_E_CTRL_PC31DOWNTO12_intermed_1 <= RIN.E.CTRL.PC( 31 DOWNTO 12 );
R_D_PC31DOWNTO12_intermed_1 <= R.D.PC( 31 DOWNTO 12 );
R_D_PC31DOWNTO12_intermed_2 <= R_D_PC31DOWNTO12_intermed_1;
RIN_D_PC31DOWNTO12_intermed_1 <= RIN.D.PC( 31 DOWNTO 12 );
RIN_D_PC31DOWNTO12_intermed_2 <= RIN_D_PC31DOWNTO12_intermed_1;
RIN_D_PC31DOWNTO12_intermed_3 <= RIN_D_PC31DOWNTO12_intermed_2;
RIN_A_CTRL_PC31DOWNTO4_intermed_1 <= RIN.A.CTRL.PC( 31 DOWNTO 4 );
R_D_PC31DOWNTO4_intermed_1 <= R.D.PC( 31 DOWNTO 4 );
V_D_PC31DOWNTO4_shadow_intermed_1 <= V_D_PC31DOWNTO4_shadow;
V_D_PC31DOWNTO4_shadow_intermed_2 <= V_D_PC31DOWNTO4_shadow_intermed_1;
RIN_D_PC31DOWNTO4_intermed_1 <= RIN.D.PC( 31 DOWNTO 4 );
RIN_D_PC31DOWNTO4_intermed_2 <= RIN_D_PC31DOWNTO4_intermed_1;
R_D_PC3DOWNTO2_intermed_1 <= R.D.PC( 3 DOWNTO 2 );
V_D_PC3DOWNTO2_shadow_intermed_1 <= V_D_PC3DOWNTO2_shadow;
V_D_PC3DOWNTO2_shadow_intermed_2 <= V_D_PC3DOWNTO2_shadow_intermed_1;
RIN_D_PC3DOWNTO2_intermed_1 <= RIN.D.PC( 3 DOWNTO 2 );
RIN_D_PC3DOWNTO2_intermed_2 <= RIN_D_PC3DOWNTO2_intermed_1;
RIN_A_CTRL_PC3DOWNTO2_intermed_1 <= RIN.A.CTRL.PC( 3 DOWNTO 2 );
V_D_PC31DOWNTO12_shadow_intermed_1 <= V_D_PC31DOWNTO12_shadow;
V_D_PC31DOWNTO12_shadow_intermed_2 <= V_D_PC31DOWNTO12_shadow_intermed_1;
RIN_A_CTRL_PC31DOWNTO12_intermed_1 <= RIN.A.CTRL.PC( 31 DOWNTO 12 );
R_D_PC31DOWNTO12_intermed_1 <= R.D.PC( 31 DOWNTO 12 );
RIN_D_PC31DOWNTO12_intermed_1 <= RIN.D.PC( 31 DOWNTO 12 );
RIN_D_PC31DOWNTO12_intermed_2 <= RIN_D_PC31DOWNTO12_intermed_1;
end if;
end process;
dfp_trap_vector(0) <= '1' when (EX_JUMP_ADDRESS31DOWNTO12_shadow /= EX_ADD_RES32DOWNTO332DOWNTO13_shadow) else '0';
dfp_trap_vector(1) <= '1' when (RP.ERROR /= RPIN_ERROR_intermed_1) else '0';
dfp_trap_vector(2) <= '1' when (RP.ERROR /= VP_ERROR_shadow_intermed_1) else '0';
dfp_trap_vector(3) <= '1' when (R.X.MEXC /= DCO_MEXC_intermed_1) else '0';--
dfp_trap_vector(4) <= '1' when (R.X.MEXC /= RIN_X_MEXC_intermed_1) else '0';--
dfp_trap_vector(5) <= '1' when (R.X.MEXC /= V_X_MEXC_shadow_intermed_1) else '0';--
dfp_trap_vector(6) <= '1' when (RFI.REN1 /= DE_REN1_shadow) else '0';
dfp_trap_vector(7) <= '1' when (RFI.REN2 /= DE_REN2_shadow) else '0';
dfp_trap_vector(8) <= '1' when (ICI.FLUSHL /= '0') else '0';
dfp_trap_vector(9) <= '1' when (MULI.ACC ( 39 DOWNTO 32 ) /= R.X.Y ( 7 DOWNTO 0 )) else '0';
dfp_trap_vector(10) <= '1' when (DIVI.START /= R.A.DIVSTART) else '0';
dfp_trap_vector(11) <= '1' when (DBGO.DSU /= '1') else '0';
dfp_trap_vector(12) <= '1' when (V_X_DCI_shadow /= R.M.DCI) else '0';
dfp_trap_vector(13) <= '1' when (V_D_STEP_shadow /= R.D.STEP) else '0';
dfp_trap_vector(14) <= '1' when (DBGO.DSUMODE /= R.X.DEBUG) else '0';
dfp_trap_vector(15) <= '1' when (V_X_MAC_shadow /= V_E_MAC_shadow_intermed_2) else '0';
dfp_trap_vector(16) <= '1' when (V_X_MAC_shadow /= RIN_M_MAC_intermed_1) else '0';
dfp_trap_vector(17) <= '1' when (DBGO.CRDY /= DSUIN_CRDY2_intermed_1) else '0';
dfp_trap_vector(18) <= '1' when (DBGO.CRDY /= VDSU_CRDY2_shadow_intermed_1) else '0';
dfp_trap_vector(19) <= '1' when (V_X_MAC_shadow /= RIN_E_MAC_intermed_2) else '0';
dfp_trap_vector(20) <= '1' when (V_A_STEP_shadow /= RIN_A_STEP_intermed_1) else '0';
dfp_trap_vector(21) <= '1' when (V_D_STEP_shadow /= RIN_D_STEP_intermed_1) else '0';
dfp_trap_vector(22) <= '1' when (V_D_STEP_shadow /= DBGI.STEP) else '0';
dfp_trap_vector(23) <= '1' when (DBGO.CRDY /= DSUR.CRDY ( 2 )) else '0';
dfp_trap_vector(24) <= '1' when (DSUR.CRDY ( 2 ) /= DSUIN_CRDY2_intermed_1) else '0';
dfp_trap_vector(25) <= '1' when (DSUR.CRDY ( 2 ) /= VDSU_CRDY2_shadow_intermed_1) else '0';
dfp_trap_vector(26) <= '1' when (V_X_MAC_shadow /= R_E_MAC_intermed_1) else '0';
dfp_trap_vector(27) <= '1' when (V_X_MAC_shadow /= R.M.MAC) else '0';
dfp_trap_vector(28) <= '1' when (DBGO.DATA /= DIAGDATA_shadow) else '0';
dfp_trap_vector(29) <= '1' when (TBI.ADDR /= TBUFI_ADDR_shadow) else '0';
dfp_trap_vector(30) <= '1' when (TBI.DATA /= TBUFI_DATA_shadow) else '0';
dfp_trap_vector(31) <= '1' when (TBI.ENABLE /= TBUFI_ENABLE_shadow) else '0';
dfp_trap_vector(32) <= '1' when (TBI.WRITE /= TBUFI_WRITE_shadow) else '0';
dfp_trap_vector(33) <= '1' when (TBI.DIAG /= TBUFI_DIAG_shadow) else '0';
dfp_trap_vector(34) <= '1' when (TBI.DIAG /= "0000") else '0';
dfp_trap_vector(35) <= '1' when (V_M_MAC_shadow /= R.M.MAC) else '0';
dfp_trap_vector(36) <= '1' when (V_E_JMPL_shadow /= R.A.JMPL) else '0';
dfp_trap_vector(37) <= '1' when (RIN.X.RESULT ( 6 DOWNTO 0 ) /= V_X_RESULT6DOWNTO0_shadow) else '0';
dfp_trap_vector(38) <= '1' when (RIN.X.DATA ( 0 ) /= V_X_DATA0_shadow) else '0';
dfp_trap_vector(39) <= '1' when (RIN.X.CTRL.PC ( 31 DOWNTO 2 ) /= V_X_CTRL_PC31DOWNTO2_shadow) else '0';
dfp_trap_vector(40) <= '1' when (RIN.X.CTRL.PC ( 31 DOWNTO 2 ) /= R.M.CTRL.PC ( 31 DOWNTO 2 )) else '0';
dfp_trap_vector(41) <= '1' when (RIN.W.S.TT ( 3 DOWNTO 0 ) /= V_W_S_TT3DOWNTO0_shadow) else '0';
dfp_trap_vector(42) <= '1' when (RIN.M.RESULT ( 1 DOWNTO 0 ) /= V_M_RESULT1DOWNTO0_shadow) else '0';
dfp_trap_vector(43) <= '1' when (RIN.X.DATA ( 0 ) ( 31 ) /= V_X_DATA031_shadow) else '0';
dfp_trap_vector(44) <= '1' when (RIN.X.DATA ( 0 )( 31 ) /= V_X_DATA031_shadow) else '0';
dfp_trap_vector(45) <= '1' when (RIN.E.CTRL.INST ( 19 ) /= V_E_CTRL_INST19_shadow) else '0';
dfp_trap_vector(46) <= '1' when (RIN.E.CTRL.INST ( 19 ) /= R.A.CTRL.INST ( 19 )) else '0';
dfp_trap_vector(47) <= '1' when (RIN.E.CTRL.INST ( 20 ) /= R.A.CTRL.INST ( 20 )) else '0';
dfp_trap_vector(48) <= '1' when (RIN.E.CTRL.INST ( 20 ) /= V_E_CTRL_INST20_shadow) else '0';
dfp_trap_vector(49) <= '1' when (RIN.X.DATA ( 0 ) ( 0 ) /= V_X_DATA00_shadow) else '0';
dfp_trap_vector(50) <= '1' when (RIN.X.DATA ( 0 )( 0 ) /= V_X_DATA00_shadow) else '0';
dfp_trap_vector(51) <= '1' when (RIN.X.DATA ( 0 ) ( 4 DOWNTO 0 ) /= V_X_DATA04DOWNTO0_shadow) else '0';
dfp_trap_vector(52) <= '1' when (RIN.X.DATA ( 0 )( 4 DOWNTO 0 ) /= V_X_DATA04DOWNTO0_shadow) else '0';
dfp_trap_vector(53) <= '1' when (RIN.D.INST ( 0 ) /= V_D_INST0_shadow) else '0';
dfp_trap_vector(54) <= '1' when (RIN.F.PC ( 31 DOWNTO 2 ) /= V_F_PC31DOWNTO2_shadow) else '0';
dfp_trap_vector(55) <= '1' when (RIN.D.PC ( 31 DOWNTO 2 ) /= V_D_PC31DOWNTO2_shadow) else '0';
dfp_trap_vector(56) <= '1' when (RIN.E.CTRL.INST ( 24 ) /= V_E_CTRL_INST24_shadow) else '0';
dfp_trap_vector(57) <= '1' when (RIN.E.CTRL.INST ( 24 ) /= R.A.CTRL.INST ( 24 )) else '0';
dfp_trap_vector(58) <= '1' when (RIN.A.CTRL.INST ( 19 ) /= V_A_CTRL_INST19_shadow) else '0';
dfp_trap_vector(59) <= '1' when (RIN.M.Y ( 31 ) /= V_M_Y31_shadow) else '0';
dfp_trap_vector(60) <= '1' when (V_E_CTRL_RETT_shadow /= R.A.CTRL.RETT) else '0';
dfp_trap_vector(61) <= '1' when (DSUIN.CRDY ( 2 ) /= VDSU_CRDY2_shadow) else '0';
dfp_trap_vector(62) <= '1' when (V_E_SU_shadow /= R.A.SU) else '0';
dfp_trap_vector(63) <= '1' when (V_E_ET_shadow /= R.A.ET) else '0';
dfp_trap_vector(64) <= '1' when (V_A_CWP_shadow /= R.D.CWP) else '0';
dfp_trap_vector(65) <= '1' when (RIN.A.CTRL.PC ( 31 DOWNTO 2 ) /= V_A_CTRL_PC31DOWNTO2_shadow) else '0';
dfp_trap_vector(66) <= '1' when (RIN.E.CTRL.PC ( 31 DOWNTO 2 ) /= R.A.CTRL.PC ( 31 DOWNTO 2 )) else '0';
dfp_trap_vector(67) <= '1' when (RIN.E.CTRL.PC ( 31 DOWNTO 2 ) /= V_E_CTRL_PC31DOWNTO2_shadow) else '0';
dfp_trap_vector(68) <= '1' when (RIN.M.CTRL.PC ( 31 DOWNTO 2 ) /= V_M_CTRL_PC31DOWNTO2_shadow) else '0';
dfp_trap_vector(69) <= '1' when (RIN.M.CTRL.PC ( 31 DOWNTO 2 ) /= R.E.CTRL.PC ( 31 DOWNTO 2 )) else '0';
dfp_trap_vector(70) <= '1' when (RIN.D.INST ( 0 )( 4 DOWNTO 0 ) /= V_D_INST04DOWNTO0_shadow) else '0';
dfp_trap_vector(71) <= '1' when (RIN.F.PC ( 31 DOWNTO 12 ) /= V_F_PC31DOWNTO12_shadow) else '0';
dfp_trap_vector(72) <= '1' when (RIN.X.DATA ( 0 )( 3 ) /= V_X_DATA03_shadow) else '0';
dfp_trap_vector(73) <= '1' when (RIN.A.CTRL.INST ( 20 ) /= V_A_CTRL_INST20_shadow) else '0';
dfp_trap_vector(74) <= '1' when (RIN.A.CTRL.INST ( 24 ) /= V_A_CTRL_INST24_shadow) else '0';
dfp_trap_vector(75) <= '1' when (RIN.X.RESULT ( 6 DOWNTO 0 )( 3 DOWNTO 0 ) /= V_X_RESULT6DOWNTO03DOWNTO0_shadow) else '0';
dfp_trap_vector(76) <= '1' when (RIN.D.INST ( 0 )( 19 ) /= V_D_INST019_shadow) else '0';
dfp_trap_vector(77) <= '1' when (RIN.D.INST ( 0 )( 20 ) /= V_D_INST020_shadow) else '0';
dfp_trap_vector(78) <= '1' when (RIN.D.INST ( 0 )( 24 ) /= V_D_INST024_shadow) else '0';
dfp_trap_vector(79) <= '1' when (XC_HALT_shadow /= DBGI.HALT) else '0';
dfp_trap_vector(80) <= '1' when (XC_HALT_shadow /= '0') else '0';
dfp_trap_vector(81) <= '1' when (V_A_CTRL_TRAP_shadow /= R.D.MEXC) else '0';
dfp_trap_vector(82) <= '1' when (V_A_CTRL_TRAP_shadow /= V_D_MEXC_shadow_intermed_1) else '0';--
dfp_trap_vector(83) <= '1' when (V_A_CTRL_TRAP_shadow /= RIN_D_MEXC_intermed_1) else '0';--
dfp_trap_vector(84) <= '1' when (V_A_CTRL_TT_shadow /= RIN_A_CTRL_TT_intermed_1) else '0';
dfp_trap_vector(85) <= '1' when (V_A_CTRL_TT_shadow /= R.A.CTRL.TT) else '0';
dfp_trap_vector(86) <= '1' when (V_A_CTRL_TT_shadow /= "000000") else '0';
dfp_trap_vector(87) <= '1' when (V_A_CTRL_INST_shadow /= DE_INST_shadow) else '0';
dfp_trap_vector(88) <= '1' when (V_A_CTRL_PC_shadow /= R.D.PC) else '0';
dfp_trap_vector(89) <= '1' when (V_A_CTRL_CNT_shadow /= R.D.CNT) else '0';
dfp_trap_vector(90) <= '1' when (V_A_STEP_shadow /= RIN_D_STEP_intermed_1) else '0';
dfp_trap_vector(91) <= '1' when (V_A_STEP_shadow /= R.A.STEP) else '0';
dfp_trap_vector(92) <= '1' when (V_A_STEP_shadow /= DBGI_STEP_intermed_1) else '0';
dfp_trap_vector(93) <= '1' when (V_A_STEP_shadow /= V_D_STEP_shadow_intermed_1) else '0';
dfp_trap_vector(94) <= '1' when (V_A_STEP_shadow /= R.D.STEP) else '0';
dfp_trap_vector(95) <= '1' when (V_X_NERROR_shadow /= RP.ERROR) else '0';
dfp_trap_vector(96) <= '1' when (V_X_NERROR_shadow /= RPIN_ERROR_intermed_1) else '0';
dfp_trap_vector(97) <= '1' when (V_X_NERROR_shadow /= VP_ERROR_shadow_intermed_1) else '0';
dfp_trap_vector(98) <= '1' when (V_X_MEXC_shadow /= DCO.MEXC) else '0';
dfp_trap_vector(99) <= '1' when (V_X_ICC_shadow /= ME_ICC_shadow) else '0';
dfp_trap_vector(100) <= '1' when (V_W_S_ASR18_shadow /= RIN_W_S_ASR18_intermed_1) else '0';
dfp_trap_vector(101) <= '1' when (V_W_S_ASR18_shadow /= R.W.S.ASR18) else '0';
dfp_trap_vector(102) <= '1' when (V_W_S_ASR18_shadow /= ME_ASR18_shadow) else '0';
dfp_trap_vector(103) <= '1' when (V_M_CTRL_RETT_shadow /= R.E.CTRL.RETT) else '0';
dfp_trap_vector(104) <= '1' when (V_E_CWP_shadow /= R.A.CWP) else '0';
dfp_trap_vector(105) <= '1' when (V_M_SU_shadow /= R.E.SU) else '0';
dfp_trap_vector(106) <= '1' when (V_M_MUL_shadow /= RIN_M_MUL_intermed_1) else '0';
dfp_trap_vector(107) <= '1' when (VP_PWD_shadow /= RP.PWD) else '0';
dfp_trap_vector(108) <= '1' when (VP_PWD_shadow /= '0') else '0';
dfp_trap_vector(109) <= '1' when (VP_PWD_shadow /= RPIN_PWD_intermed_1) else '0';
dfp_trap_vector(110) <= '1' when (V_M_MUL_shadow /= '0') else '0';
dfp_trap_vector(111) <= '1' when (V_M_MUL_shadow /= R.M.MUL) else '0';
dfp_trap_vector(112) <= '1' when (V_M_MAC_shadow /= V_E_MAC_shadow_intermed_1) else '0';
dfp_trap_vector(113) <= '1' when (V_M_MAC_shadow /= RIN_M_MAC_intermed_1) else '0';
dfp_trap_vector(114) <= '1' when (V_M_MAC_shadow /= RIN_E_MAC_intermed_1) else '0';
dfp_trap_vector(115) <= '1' when (V_M_MAC_shadow /= R.E.MAC) else '0';
dfp_trap_vector(116) <= '1' when (V_X_MAC_shadow /= V_M_MAC_shadow_intermed_1) else '0';
dfp_trap_vector(117) <= '1' when (V_X_MAC_shadow /= RIN_X_MAC_intermed_1) else '0';
dfp_trap_vector(118) <= '1' when (V_X_MAC_shadow /= R.X.MAC) else '0';
dfp_trap_vector(119) <= '1' when (V_X_LADDR_shadow /= R.M.RESULT ( 1 DOWNTO 0 )) else '0';
dfp_trap_vector(120) <= '1' when (V_W_RESULT_shadow /= XC_RESULT_shadow) else '0';
dfp_trap_vector(121) <= '1' when (V_W_WA_shadow /= XC_WADDR7DOWNTO0_shadow) else '0';
dfp_trap_vector(122) <= '1' when (V_W_S_SVT_shadow /= R.W.S.SVT) else '0';
dfp_trap_vector(123) <= '1' when (V_W_S_SVT_shadow /= '0') else '0';
dfp_trap_vector(124) <= '1' when (V_W_S_SVT_shadow /= RIN_W_S_SVT_intermed_1) else '0';
dfp_trap_vector(125) <= '1' when (V_W_S_DWT_shadow /= RIN_W_S_DWT_intermed_1) else '0';
dfp_trap_vector(126) <= '1' when (V_W_S_DWT_shadow /= R.W.S.DWT) else '0';
dfp_trap_vector(127) <= '1' when (V_W_S_DWT_shadow /= '0') else '0';
dfp_trap_vector(128) <= '0' when (V_W_S_EF_shadow /= '0') else '0';--
dfp_trap_vector(129) <= '0' when (V_W_S_EF_shadow /= R.W.S.EF) else '0';--
dfp_trap_vector(130) <= '0' when (V_W_S_EF_shadow /= RIN_W_S_EF_intermed_1) else '0';--
dfp_trap_vector(131) <= '1' when (V_X_CTRL_RETT_shadow /= R.M.CTRL.RETT) else '0';
dfp_or_reduce : process(dfp_trap_vector)
variable or_reduce_66 : std_logic_vector(65 downto 0);
variable or_reduce_33 : std_logic_vector(32 downto 0);
variable or_reduce_17 : std_logic_vector(16 downto 0);
variable or_reduce_9 : std_logic_vector(8 downto 0);
variable or_reduce_5 : std_logic_vector(4 downto 0);
variable or_reduce_3 : std_logic_vector(2 downto 0);
variable or_reduce_2 : std_logic_vector(1 downto 0);
begin
or_reduce_66 := dfp_trap_vector(131 downto 66) OR dfp_trap_vector(65 downto 0);
or_reduce_33 := or_reduce_66(65 downto 33) OR or_reduce_66(32 downto 0);
or_reduce_17 := or_reduce_33(32 downto 16) OR ("0" & or_reduce_33(15 downto 0));
or_reduce_9 := or_reduce_17(16 downto 8) OR ("0" & or_reduce_17(7 downto 0));
or_reduce_5 := or_reduce_9(8 downto 4) OR ("0" & or_reduce_9(3 downto 0));
or_reduce_3 := or_reduce_5(4 downto 2) OR ("0" & or_reduce_5(1 downto 0));
or_reduce_2 := or_reduce_3(2 downto 1) OR ("0" & or_reduce_3(0 downto 0));
or_reduce_1 <= or_reduce_2(0) OR or_reduce_2(1);
end process;
handlerTrap <= or_reduce_1 when (dfp_delay_start = 0) else '0';-- and not r.w.s.s and not r.w.s.ps;
trap_enable_delay : process(clk)
begin
if(rising_edge(clk))then
if(rstn = '0')then
dfp_delay_start <= 15;
elsif(dfp_delay_start /= 0)then
dfp_delay_start <= dfp_delay_start - 1;
end if;
end if;
end process;
trap_mem : process(clk)
begin
if(rising_edge(clk))then
if(rstn = '0')then
dfp_trap_mem <= (others => '0');
elsif(dfp_delay_start = 0)then-- and r.w.s.s = '0' and r.w.s.ps = '0')then
dfp_trap_mem <= dfp_trap_mem OR dfp_trap_vector;
end if;
end if;
end process;
trap_counter : process(clk)
begin
if(rising_edge(clk))then
if(rstn = '0')then
trapCountIn <= (others => '0');
elsif(dfp_delay_start = 0)then-- and r.w.s.s = '0' and r.w.s.ps = '0')then
if(or_reduce_1 = '1')then
trapCountIn <= trapCountIn + X"00000001";
end if;
end if;
end if;
end process;
-- Control module for ChipScope Pro
dfp_bscan_host: iconScope
port map (
CONTROL0 => dfp_bscan_cntrl1,
CONTROL1 => dfp_bscan_cntrl2
);
-- Debugging probe for trap mask
dfp_bscan_value <= dfp_trap_mem;
dfp_bscan_count <= trapCountIn;
dfp_probe_msk : scope
port map (
CONTROL => dfp_bscan_cntrl1,
ASYNC_IN => dfp_bscan_value
);
dfp_probe_cnt : scope2
port map (
CONTROL => dfp_bscan_cntrl2,
ASYNC_IN => dfp_bscan_count
);
end;
| mit | bea2211a26718fba7a3b175725df38b8 | 0.686434 | 2.268506 | false | false | false | false |
christakissgeo/Matrix-Vector-Multiplication | VHDL Files/fsm.vhd | 1 | 9,615 | --FSM
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.Numeric_Std.all;
-----------------------------------------------------------------------------
entity fsm is
port (
clock : in std_logic;
reset : in std_logic;
ramA_address : in std_logic_vector (4 downto 0);
ramR_address : in std_logic_vector (7 downto 0);
rom_address : in std_logic_vector (7 downto 0);
hold_me : in std_logic;
ramR_readEnable : out std_logic;
ramA_writeEnable : out std_logic;
ramA_readEnable : out std_logic;
ramR_writeEnable : out std_logic;
rom_enable : out std_logic;
counterAddressGen_H_enable : out std_logic;
counterAddressGen_R_enable : out std_logic;
counterAddressGen_A_restart : out std_logic;
counterAddressGen_R_restart : out std_logic;
counterAddressGen_H_restart : out std_logic;
mac_clean : out std_logic;
reset_fsm : out std_logic;
hold_prev : out std_logic
);
end entity;
------------------------------------------------------------------------------
architecture fsm of fsm is
-- RESET= 000 INPUT=001 COMPUTE=010 RESULT=011 OUTPUT=100 HOLD=101
type fsm_status is (RST, INPUT, COMPUTE, RESULT, OUTPUT, HOLD);
signal status : fsm_status;
begin
process (clock)
begin
if rising_edge(clock) then
if reset = '1' then
status <= RST; --RESET
else
case status is
----------------RESET-------------------
when RST =>
status <= INPUT;
----------------INPUT-------------------
when INPUT =>
if (ramA_address = "00000") then
status <= INPUT; --INPUT
else
status <= COMPUTE; --COMPUTE
end if;
----------------COMPUTE-------------------
when COMPUTE =>
if (rom_address = "00001010" or
rom_address = "00010010" or
rom_address = "00011010" or
rom_address = "00100010" or
rom_address = "00101010" or
rom_address = "00110010" or
rom_address = "00111010" or
rom_address = "01000010") then
status <= RESULT; --RESULT
else
status <= COMPUTE; --COMPUTE
end if;
----------------RESULT-------------------
when RESULT =>
if (rom_address = "01000011") then
status <= OUTPUT; --OUTPUT
else
status <= COMPUTE; --COMPUTE
end if;
----------------OUTPUT-------------------
when OUTPUT =>
if (hold_me = '1') then
status <= HOLD; --HOLD
elsif (ramR_address = "00001111") then
status <= RST; --RESET
else
status <= OUTPUT; --OUTPUT
end if;
----------------HOLD-------------------
when HOLD =>
if (hold_me = '0') then
status <= OUTPUT; --OUTPUT
else
status <= HOLD; --HOLD
end if;
when others =>
status <= RST;
end case;
end if;
end if;
end process;
process(status)
begin
case (status) is
when RST =>
ramR_readEnable <= '0';
ramA_writeEnable <= '1';
ramA_readEnable <= '0';
ramR_writeEnable <= '0';
rom_enable <= '0';
counterAddressGen_H_enable <= '1';
counterAddressGen_R_enable <= '1';
counterAddressGen_A_restart <= '1';
counterAddressGen_R_restart <= '1';
counterAddressGen_H_restart <= '1';
mac_clean <= '1';
reset_fsm <= '1';
hold_prev <= '0';
when INPUT =>
ramR_readEnable <= '0';
ramA_writeEnable <= '1';
ramA_readEnable <= '0';
ramR_writeEnable <= '0';
rom_enable <= '0';
counterAddressGen_H_enable <= '0';
counterAddressGen_R_enable <= '0';
counterAddressGen_A_restart <= '0';
counterAddressGen_R_restart <= '0';
counterAddressGen_H_restart <= '0';
mac_clean <= '0';
reset_fsm <= '0';
hold_prev <= '1';
when COMPUTE =>
ramR_readEnable <= '0';
ramA_writeEnable <= '0';
ramA_readEnable <= '1';
ramR_writeEnable <= '0';
rom_enable <= '1';
counterAddressGen_H_enable <= '1';
counterAddressGen_R_enable <= '0';
counterAddressGen_A_restart <= '0';
counterAddressGen_R_restart <= '0';
counterAddressGen_H_restart <= '0';
mac_clean <= '0';
hold_prev <= '1';
reset_fsm <= '0';
when RESULT =>
ramR_readEnable <= '0';
ramA_writeEnable <= '0';
ramA_readEnable <= '1';
ramR_writeEnable <= '1';
rom_enable <= '1';
counterAddressGen_H_enable <= '1';
counterAddressGen_R_enable <= '1';
counterAddressGen_A_restart <= '0';
counterAddressGen_R_restart <= '0';
counterAddressGen_H_restart <= '0';
mac_clean <= '1';
hold_prev <= '1';
reset_fsm <= '0';
when OUTPUT =>
ramR_readEnable <= '1';
ramA_writeEnable <= '1';
ramA_readEnable <= '0';
ramR_writeEnable <= '0';
rom_enable <= '0';
counterAddressGen_H_enable <= '0';
counterAddressGen_R_enable <= '1';
counterAddressGen_A_restart <= '0';
counterAddressGen_R_restart <= '0';
counterAddressGen_H_restart <= '0';
mac_clean <= '0';
hold_prev <= '0';
reset_fsm <= '0';
when HOLD =>
ramR_readEnable <= '0';
ramA_writeEnable <= '1';
ramA_readEnable <= '0';
ramR_writeEnable <= '0';
rom_enable <= '0';
counterAddressGen_H_enable <= '0';
counterAddressGen_R_enable <= '0';
counterAddressGen_A_restart <= '0';
counterAddressGen_R_restart <= '0';
counterAddressGen_H_restart <= '0';
mac_clean <= '0';
hold_prev <= '0';
reset_fsm <= '0';
when others =>
ramR_readEnable <= '0';
ramA_writeEnable <= '1';
ramA_readEnable <= '0';
ramR_writeEnable <= '0';
rom_enable <= '0';
counterAddressGen_H_enable <= '0';
counterAddressGen_R_enable <= '0';
counterAddressGen_A_restart <= '1';
counterAddressGen_R_restart <= '1';
counterAddressGen_H_restart <= '1';
mac_clean <= '1';
reset_fsm <= '1';
hold_prev <= '0';
end case;
end process;
end architecture fsm;
| mit | 7439c7809ecc8a1cb3435540695951ff | 0.330213 | 5.002601 | false | false | false | false |
impedimentToProgress/UCI-BlueChip | AttackFiles/Attacks/privEsc/lib/techmap/dw02/mul_dw_gen.vhd | 2 | 1,956 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: dw_mul_61x61
-- File: mul_dw_gen.vhd
-- Author: Edvin Catovic - Gaisler Research
-- Description: DW 61x61 multiplier
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library DW02;
use DW02.DW02_components.all;
entity dw_mul_61x61 is
port(A : in std_logic_vector(60 downto 0);
B : in std_logic_vector(60 downto 0);
CLK : in std_logic;
PRODUCT : out std_logic_vector(121 downto 0));
end;
architecture rtl of dw_mul_61x61 is
signal gnd : std_ulogic;
signal pin, p : std_logic_vector(121 downto 0);
begin
gnd <= '0';
u0 : DW02_mult_2_stage
generic map ( A_width => A'length, B_width => B'length )
port map ( A => A, B => B, TC => gnd, CLK => CLK, PRODUCT => pin );
reg0 : process(CLK)
begin
if rising_edge(CLK) then
p <= pin;
end if;
end process;
PRODUCT <= p;
end;
| mit | b5f847742edabd9f13cc31fc2600cf10 | 0.578221 | 3.842829 | false | false | false | false |
impedimentToProgress/UCI-BlueChip | AttackFiles/Attacks/privEsc/lib/openchip/devices/devices_ocp.vhd | 2 | 3,258 | ----------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2004 GAISLER RESEARCH
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- See the file COPYING for the full details of the license.
--
-----------------------------------------------------------------------------
-- Entity: devices
-- File: devices.vhd
-- Author: Antti Lukats, OpenChip
-- Description: Vendor and devices id's for amba plug&play
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
-- pragma translate_off
use std.textio.all;
-- pragma translate_on
package devices_ocp is
-- Vendor code
constant VENDOR_OPENCHIP : amba_vendor_type := 16#06#;
-- OpenChip ID's
constant OPENCHIP_APBGPIO : amba_device_type := 16#001#;
constant OPENCHIP_APBI2C : amba_device_type := 16#002#;
constant OPENCHIP_APBSPI : amba_device_type := 16#003#;
constant OPENCHIP_APBCHARLCD : amba_device_type := 16#004#;
constant OPENCHIP_APBPWM : amba_device_type := 16#005#;
constant OPENCHIP_APBPS2 : amba_device_type := 16#006#;
constant OPENCHIP_APBMMCSD : amba_device_type := 16#007#;
constant OPENCHIP_APBNAND : amba_device_type := 16#008#;
constant OPENCHIP_APBLPC : amba_device_type := 16#009#;
constant OPENCHIP_APBCF : amba_device_type := 16#00A#;
constant OPENCHIP_APBSYSACE : amba_device_type := 16#00B#;
constant OPENCHIP_APB1WIRE : amba_device_type := 16#00C#;
constant OPENCHIP_APBJTAG : amba_device_type := 16#00D#;
constant OPENCHIP_APBSUI : amba_device_type := 16#00E#;
-- pragma translate_off
constant OPENCHIP_DESC : vendor_description := "OpenChip ";
constant openchip_device_table : device_table_type := (
OPENCHIP_APBGPIO => "APB General Purpose IO ",
OPENCHIP_APBI2C => "APB I2C Interface ",
OPENCHIP_APBSPI => "APB SPI Interface ",
OPENCHIP_APBCHARLCD => "APB Character LCD ",
OPENCHIP_APBPWM => "APB PWM ",
OPENCHIP_APBPS2 => "APB PS/2 Interface ",
OPENCHIP_APBMMCSD => "APB MMC/SD Card Interface ",
OPENCHIP_APBNAND => "APB NAND(SmartMedia) Interface ",
OPENCHIP_APBLPC => "APB LPC Interface ",
OPENCHIP_APBCF => "APB CompactFlash (IDE) ",
OPENCHIP_APBSYSACE => "APB SystemACE Interface ",
OPENCHIP_APB1WIRE => "APB 1-Wire Interface ",
OPENCHIP_APBJTAG => "APB JTAG TAP Master ",
OPENCHIP_APBSUI => "APB Simple User Interface ",
others => "Unknown Device ");
constant openchip_lib : vendor_library_type := (
vendorid => VENDOR_OPENCHIP,
vendordesc => OPENCHIP_DESC,
device_table => openchip_device_table
);
-- pragma translate_on
end;
| mit | ad4314c117d347df2c94a5d7de3087a6 | 0.577962 | 3.934783 | false | false | false | false |
lxp32/lxp32-cpu | rtl/lxp32_execute.vhd | 1 | 5,661 | ---------------------------------------------------------------------
-- Execution unit
--
-- Part of the LXP32 CPU
--
-- Copyright (c) 2016 by Alex I. Kuznetsov
--
-- The third stage of the LXP32 pipeline.
---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity lxp32_execute is
generic(
DBUS_RMW: boolean;
DIVIDER_EN: boolean;
MUL_ARCH: string
);
port(
clk_i: in std_logic;
rst_i: in std_logic;
cmd_loadop3_i: in std_logic;
cmd_signed_i: in std_logic;
cmd_dbus_i: in std_logic;
cmd_dbus_store_i: in std_logic;
cmd_dbus_byte_i: in std_logic;
cmd_addsub_i: in std_logic;
cmd_mul_i: in std_logic;
cmd_div_i: in std_logic;
cmd_div_mod_i: in std_logic;
cmd_cmp_i: in std_logic;
cmd_jump_i: in std_logic;
cmd_negate_op2_i: in std_logic;
cmd_and_i: in std_logic;
cmd_xor_i: in std_logic;
cmd_shift_i: in std_logic;
cmd_shift_right_i: in std_logic;
jump_type_i: in std_logic_vector(3 downto 0);
op1_i: in std_logic_vector(31 downto 0);
op2_i: in std_logic_vector(31 downto 0);
op3_i: in std_logic_vector(31 downto 0);
dst_i: in std_logic_vector(7 downto 0);
sp_waddr_o: out std_logic_vector(7 downto 0);
sp_we_o: out std_logic;
sp_wdata_o: out std_logic_vector(31 downto 0);
valid_i: in std_logic;
ready_o: out std_logic;
dbus_cyc_o: out std_logic;
dbus_stb_o: out std_logic;
dbus_we_o: out std_logic;
dbus_sel_o: out std_logic_vector(3 downto 0);
dbus_ack_i: in std_logic;
dbus_adr_o: out std_logic_vector(31 downto 2);
dbus_dat_o: out std_logic_vector(31 downto 0);
dbus_dat_i: in std_logic_vector(31 downto 0);
jump_valid_o: out std_logic;
jump_dst_o: out std_logic_vector(29 downto 0);
jump_ready_i: in std_logic;
interrupt_return_o: out std_logic
);
end entity;
architecture rtl of lxp32_execute is
-- Pipeline control signals
signal busy: std_logic;
signal can_execute: std_logic;
-- ALU signals
signal alu_result: std_logic_vector(31 downto 0);
signal alu_we: std_logic;
signal alu_busy: std_logic;
signal alu_cmp_eq: std_logic;
signal alu_cmp_ug: std_logic;
signal alu_cmp_sg: std_logic;
-- OP3 loader signals
signal loadop3_we: std_logic;
-- Jump machine signals
signal jump_condition: std_logic;
signal jump_valid: std_logic:='0';
signal jump_dst: std_logic_vector(jump_dst_o'range);
-- DBUS signals
signal dbus_result: std_logic_vector(31 downto 0);
signal dbus_busy: std_logic;
signal dbus_we: std_logic;
-- Result mux signals
signal result_mux: std_logic_vector(31 downto 0);
signal result_valid: std_logic;
signal result_regaddr: std_logic_vector(7 downto 0);
signal dst_reg: std_logic_vector(7 downto 0);
-- Signals related to interrupt handling
signal interrupt_return: std_logic:='0';
begin
-- Pipeline control
busy<=alu_busy or dbus_busy;
ready_o<=not busy;
can_execute<=valid_i and not busy;
-- ALU
alu_inst: entity work.lxp32_alu(rtl)
generic map(
DIVIDER_EN=>DIVIDER_EN,
MUL_ARCH=>MUL_ARCH
)
port map(
clk_i=>clk_i,
rst_i=>rst_i,
valid_i=>can_execute,
cmd_signed_i=>cmd_signed_i,
cmd_addsub_i=>cmd_addsub_i,
cmd_mul_i=>cmd_mul_i,
cmd_div_i=>cmd_div_i,
cmd_div_mod_i=>cmd_div_mod_i,
cmd_cmp_i=>cmd_cmp_i,
cmd_negate_op2_i=>cmd_negate_op2_i,
cmd_and_i=>cmd_and_i,
cmd_xor_i=>cmd_xor_i,
cmd_shift_i=>cmd_shift_i,
cmd_shift_right_i=>cmd_shift_right_i,
op1_i=>op1_i,
op2_i=>op2_i,
result_o=>alu_result,
cmp_eq_o=>alu_cmp_eq,
cmp_ug_o=>alu_cmp_ug,
cmp_sg_o=>alu_cmp_sg,
we_o=>alu_we,
busy_o=>alu_busy
);
-- OP3 loader
loadop3_we<=can_execute and cmd_loadop3_i;
-- Jump logic
jump_condition<=(not cmd_cmp_i) or (jump_type_i(3) and alu_cmp_eq) or
(jump_type_i(2) and not alu_cmp_eq) or (jump_type_i(1) and alu_cmp_ug) or
(jump_type_i(0) and alu_cmp_sg);
process (clk_i) is
begin
if rising_edge(clk_i) then
if rst_i='1' then
jump_valid<='0';
interrupt_return<='0';
jump_dst<=(others=>'-');
else
if jump_valid='0' then
jump_dst<=op1_i(31 downto 2);
if can_execute='1' and cmd_jump_i='1' and jump_condition='1' then
jump_valid<='1';
interrupt_return<=op1_i(0);
end if;
elsif jump_ready_i='1' then
jump_valid<='0';
interrupt_return<='0';
end if;
end if;
end if;
end process;
jump_valid_o<=jump_valid or (can_execute and cmd_jump_i and jump_condition);
jump_dst_o<=jump_dst when jump_valid='1' else op1_i(31 downto 2);
interrupt_return_o<=interrupt_return;
-- DBUS access
dbus_inst: entity work.lxp32_dbus(rtl)
generic map(
RMW=>DBUS_RMW
)
port map(
clk_i=>clk_i,
rst_i=>rst_i,
valid_i=>can_execute,
cmd_dbus_i=>cmd_dbus_i,
cmd_dbus_store_i=>cmd_dbus_store_i,
cmd_dbus_byte_i=>cmd_dbus_byte_i,
cmd_signed_i=>cmd_signed_i,
addr_i=>op1_i,
wdata_i=>op2_i,
rdata_o=>dbus_result,
busy_o=>dbus_busy,
we_o=>dbus_we,
dbus_cyc_o=>dbus_cyc_o,
dbus_stb_o=>dbus_stb_o,
dbus_we_o=>dbus_we_o,
dbus_sel_o=>dbus_sel_o,
dbus_ack_i=>dbus_ack_i,
dbus_adr_o=>dbus_adr_o,
dbus_dat_o=>dbus_dat_o,
dbus_dat_i=>dbus_dat_i
);
-- Result multiplexer
result_mux_gen: for i in result_mux'range generate
result_mux(i)<=(alu_result(i) and alu_we) or
(op3_i(i) and loadop3_we) or
(dbus_result(i) and dbus_we);
end generate;
result_valid<=alu_we or loadop3_we or dbus_we;
-- Write destination register
process (clk_i) is
begin
if rising_edge(clk_i) then
if can_execute='1' then
dst_reg<=dst_i;
end if;
end if;
end process;
result_regaddr<=dst_i when can_execute='1' else dst_reg;
sp_we_o<=result_valid;
sp_waddr_o<=result_regaddr;
sp_wdata_o<=result_mux;
end architecture;
| mit | 78aeb2ad0b8a7e9d9d606484085b34b6 | 0.646529 | 2.463446 | false | false | false | false |
impedimentToProgress/UCI-BlueChip | AttackFiles/Attacks/privEsc/lib/techmap/maps/grfpw_net.vhd | 2 | 16,774 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: grfpw
-- File: grfpw.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: GRFPU / GRLFPC netlist wrapper
------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use work.gencomp.all;
entity grfpw_net is
generic (tech : integer := 0;
pclow : integer range 0 to 2 := 2;
dsu : integer range 0 to 2 := 1;
disas : integer range 0 to 2 := 0;
pipe : integer range 0 to 2 := 0
);
port (
rst : in std_ulogic; -- Reset
clk : in std_ulogic;
holdn : in std_ulogic; -- pipeline hold
cpi_flush : in std_ulogic; -- pipeline flush
cpi_exack : in std_ulogic; -- FP exception acknowledge
cpi_a_rs1 : in std_logic_vector(4 downto 0);
cpi_d_pc : in std_logic_vector(31 downto 0);
cpi_d_inst : in std_logic_vector(31 downto 0);
cpi_d_cnt : in std_logic_vector(1 downto 0);
cpi_d_trap : in std_ulogic;
cpi_d_annul : in std_ulogic;
cpi_d_pv : in std_ulogic;
cpi_a_pc : in std_logic_vector(31 downto 0);
cpi_a_inst : in std_logic_vector(31 downto 0);
cpi_a_cnt : in std_logic_vector(1 downto 0);
cpi_a_trap : in std_ulogic;
cpi_a_annul : in std_ulogic;
cpi_a_pv : in std_ulogic;
cpi_e_pc : in std_logic_vector(31 downto 0);
cpi_e_inst : in std_logic_vector(31 downto 0);
cpi_e_cnt : in std_logic_vector(1 downto 0);
cpi_e_trap : in std_ulogic;
cpi_e_annul : in std_ulogic;
cpi_e_pv : in std_ulogic;
cpi_m_pc : in std_logic_vector(31 downto 0);
cpi_m_inst : in std_logic_vector(31 downto 0);
cpi_m_cnt : in std_logic_vector(1 downto 0);
cpi_m_trap : in std_ulogic;
cpi_m_annul : in std_ulogic;
cpi_m_pv : in std_ulogic;
cpi_x_pc : in std_logic_vector(31 downto 0);
cpi_x_inst : in std_logic_vector(31 downto 0);
cpi_x_cnt : in std_logic_vector(1 downto 0);
cpi_x_trap : in std_ulogic;
cpi_x_annul : in std_ulogic;
cpi_x_pv : in std_ulogic;
cpi_lddata : in std_logic_vector(31 downto 0); -- load data
cpi_dbg_enable : in std_ulogic;
cpi_dbg_write : in std_ulogic;
cpi_dbg_fsr : in std_ulogic; -- FSR access
cpi_dbg_addr : in std_logic_vector(4 downto 0);
cpi_dbg_data : in std_logic_vector(31 downto 0);
cpo_data : out std_logic_vector(31 downto 0); -- store data
cpo_exc : out std_logic; -- FP exception
cpo_cc : out std_logic_vector(1 downto 0); -- FP condition codes
cpo_ccv : out std_ulogic; -- FP condition codes valid
cpo_ldlock : out std_logic; -- FP pipeline hold
cpo_holdn : out std_ulogic;
cpo_dbg_data : out std_logic_vector(31 downto 0);
rfi1_rd1addr : out std_logic_vector(3 downto 0);
rfi1_rd2addr : out std_logic_vector(3 downto 0);
rfi1_wraddr : out std_logic_vector(3 downto 0);
rfi1_wrdata : out std_logic_vector(31 downto 0);
rfi1_ren1 : out std_ulogic;
rfi1_ren2 : out std_ulogic;
rfi1_wren : out std_ulogic;
rfi2_rd1addr : out std_logic_vector(3 downto 0);
rfi2_rd2addr : out std_logic_vector(3 downto 0);
rfi2_wraddr : out std_logic_vector(3 downto 0);
rfi2_wrdata : out std_logic_vector(31 downto 0);
rfi2_ren1 : out std_ulogic;
rfi2_ren2 : out std_ulogic;
rfi2_wren : out std_ulogic;
rfo1_data1 : in std_logic_vector(31 downto 0);
rfo1_data2 : in std_logic_vector(31 downto 0);
rfo2_data1 : in std_logic_vector(31 downto 0);
rfo2_data2 : in std_logic_vector(31 downto 0)
);
end;
architecture rtl of grfpw_net is
component grfpw_0_unisim
port(
rst : in std_logic;
clk : in std_logic;
holdn : in std_logic;
cpi_flush : in std_logic;
cpi_exack : in std_logic;
cpi_a_rs1 : in std_logic_vector (4 downto 0);
cpi_d_pc : in std_logic_vector (31 downto 0);
cpi_d_inst : in std_logic_vector (31 downto 0);
cpi_d_cnt : in std_logic_vector (1 downto 0);
cpi_d_trap : in std_logic;
cpi_d_annul : in std_logic;
cpi_d_pv : in std_logic;
cpi_a_pc : in std_logic_vector (31 downto 0);
cpi_a_inst : in std_logic_vector (31 downto 0);
cpi_a_cnt : in std_logic_vector (1 downto 0);
cpi_a_trap : in std_logic;
cpi_a_annul : in std_logic;
cpi_a_pv : in std_logic;
cpi_e_pc : in std_logic_vector (31 downto 0);
cpi_e_inst : in std_logic_vector (31 downto 0);
cpi_e_cnt : in std_logic_vector (1 downto 0);
cpi_e_trap : in std_logic;
cpi_e_annul : in std_logic;
cpi_e_pv : in std_logic;
cpi_m_pc : in std_logic_vector (31 downto 0);
cpi_m_inst : in std_logic_vector (31 downto 0);
cpi_m_cnt : in std_logic_vector (1 downto 0);
cpi_m_trap : in std_logic;
cpi_m_annul : in std_logic;
cpi_m_pv : in std_logic;
cpi_x_pc : in std_logic_vector (31 downto 0);
cpi_x_inst : in std_logic_vector (31 downto 0);
cpi_x_cnt : in std_logic_vector (1 downto 0);
cpi_x_trap : in std_logic;
cpi_x_annul : in std_logic;
cpi_x_pv : in std_logic;
cpi_lddata : in std_logic_vector (31 downto 0);
cpi_dbg_enable : in std_logic;
cpi_dbg_write : in std_logic;
cpi_dbg_fsr : in std_logic;
cpi_dbg_addr : in std_logic_vector (4 downto 0);
cpi_dbg_data : in std_logic_vector (31 downto 0);
cpo_data : out std_logic_vector (31 downto 0);
cpo_exc : out std_logic;
cpo_cc : out std_logic_vector (1 downto 0);
cpo_ccv : out std_logic;
cpo_ldlock : out std_logic;
cpo_holdn : out std_logic;
cpo_dbg_data : out std_logic_vector (31 downto 0);
rfi1_rd1addr : out std_logic_vector (3 downto 0);
rfi1_rd2addr : out std_logic_vector (3 downto 0);
rfi1_wraddr : out std_logic_vector (3 downto 0);
rfi1_wrdata : out std_logic_vector (31 downto 0);
rfi1_ren1 : out std_logic;
rfi1_ren2 : out std_logic;
rfi1_wren : out std_logic;
rfi2_rd1addr : out std_logic_vector (3 downto 0);
rfi2_rd2addr : out std_logic_vector (3 downto 0);
rfi2_wraddr : out std_logic_vector (3 downto 0);
rfi2_wrdata : out std_logic_vector (31 downto 0);
rfi2_ren1 : out std_logic;
rfi2_ren2 : out std_logic;
rfi2_wren : out std_logic;
rfo1_data1 : in std_logic_vector (31 downto 0);
rfo1_data2 : in std_logic_vector (31 downto 0);
rfo2_data1 : in std_logic_vector (31 downto 0);
rfo2_data2 : in std_logic_vector (31 downto 0));
end component;
component grfpw_0_stratixii
port(
rst : in std_logic;
clk : in std_logic;
holdn : in std_logic;
cpi_flush : in std_logic;
cpi_exack : in std_logic;
cpi_a_rs1 : in std_logic_vector (4 downto 0);
cpi_d_pc : in std_logic_vector (31 downto 0);
cpi_d_inst : in std_logic_vector (31 downto 0);
cpi_d_cnt : in std_logic_vector (1 downto 0);
cpi_d_trap : in std_logic;
cpi_d_annul : in std_logic;
cpi_d_pv : in std_logic;
cpi_a_pc : in std_logic_vector (31 downto 0);
cpi_a_inst : in std_logic_vector (31 downto 0);
cpi_a_cnt : in std_logic_vector (1 downto 0);
cpi_a_trap : in std_logic;
cpi_a_annul : in std_logic;
cpi_a_pv : in std_logic;
cpi_e_pc : in std_logic_vector (31 downto 0);
cpi_e_inst : in std_logic_vector (31 downto 0);
cpi_e_cnt : in std_logic_vector (1 downto 0);
cpi_e_trap : in std_logic;
cpi_e_annul : in std_logic;
cpi_e_pv : in std_logic;
cpi_m_pc : in std_logic_vector (31 downto 0);
cpi_m_inst : in std_logic_vector (31 downto 0);
cpi_m_cnt : in std_logic_vector (1 downto 0);
cpi_m_trap : in std_logic;
cpi_m_annul : in std_logic;
cpi_m_pv : in std_logic;
cpi_x_pc : in std_logic_vector (31 downto 0);
cpi_x_inst : in std_logic_vector (31 downto 0);
cpi_x_cnt : in std_logic_vector (1 downto 0);
cpi_x_trap : in std_logic;
cpi_x_annul : in std_logic;
cpi_x_pv : in std_logic;
cpi_lddata : in std_logic_vector (31 downto 0);
cpi_dbg_enable : in std_logic;
cpi_dbg_write : in std_logic;
cpi_dbg_fsr : in std_logic;
cpi_dbg_addr : in std_logic_vector (4 downto 0);
cpi_dbg_data : in std_logic_vector (31 downto 0);
cpo_data : out std_logic_vector (31 downto 0);
cpo_exc : out std_logic;
cpo_cc : out std_logic_vector (1 downto 0);
cpo_ccv : out std_logic;
cpo_ldlock : out std_logic;
cpo_holdn : out std_logic;
cpo_dbg_data : out std_logic_vector (31 downto 0);
rfi1_rd1addr : out std_logic_vector (3 downto 0);
rfi1_rd2addr : out std_logic_vector (3 downto 0);
rfi1_wraddr : out std_logic_vector (3 downto 0);
rfi1_wrdata : out std_logic_vector (31 downto 0);
rfi1_ren1 : out std_logic;
rfi1_ren2 : out std_logic;
rfi1_wren : out std_logic;
rfi2_rd1addr : out std_logic_vector (3 downto 0);
rfi2_rd2addr : out std_logic_vector (3 downto 0);
rfi2_wraddr : out std_logic_vector (3 downto 0);
rfi2_wrdata : out std_logic_vector (31 downto 0);
rfi2_ren1 : out std_logic;
rfi2_ren2 : out std_logic;
rfi2_wren : out std_logic;
rfo1_data1 : in std_logic_vector (31 downto 0);
rfo1_data2 : in std_logic_vector (31 downto 0);
rfo2_data1 : in std_logic_vector (31 downto 0);
rfo2_data2 : in std_logic_vector (31 downto 0));
end component;
component grfpw_tsmc90
port (
rst : in std_ulogic; -- Reset
clk : in std_ulogic;
holdn : in std_ulogic; -- pipeline hold
cpi_flush : in std_ulogic; -- pipeline flush
cpi_exack : in std_ulogic; -- FP exception acknowledge
cpi_a_rs1 : in std_logic_vector(4 downto 0);
cpi_d_pc : in std_logic_vector(31 downto 0);
cpi_d_inst : in std_logic_vector(31 downto 0);
cpi_d_cnt : in std_logic_vector(1 downto 0);
cpi_d_trap : in std_ulogic;
cpi_d_annul : in std_ulogic;
cpi_d_pv : in std_ulogic;
cpi_a_pc : in std_logic_vector(31 downto 0);
cpi_a_inst : in std_logic_vector(31 downto 0);
cpi_a_cnt : in std_logic_vector(1 downto 0);
cpi_a_trap : in std_ulogic;
cpi_a_annul : in std_ulogic;
cpi_a_pv : in std_ulogic;
cpi_e_pc : in std_logic_vector(31 downto 0);
cpi_e_inst : in std_logic_vector(31 downto 0);
cpi_e_cnt : in std_logic_vector(1 downto 0);
cpi_e_trap : in std_ulogic;
cpi_e_annul : in std_ulogic;
cpi_e_pv : in std_ulogic;
cpi_m_pc : in std_logic_vector(31 downto 0);
cpi_m_inst : in std_logic_vector(31 downto 0);
cpi_m_cnt : in std_logic_vector(1 downto 0);
cpi_m_trap : in std_ulogic;
cpi_m_annul : in std_ulogic;
cpi_m_pv : in std_ulogic;
cpi_x_pc : in std_logic_vector(31 downto 0);
cpi_x_inst : in std_logic_vector(31 downto 0);
cpi_x_cnt : in std_logic_vector(1 downto 0);
cpi_x_trap : in std_ulogic;
cpi_x_annul : in std_ulogic;
cpi_x_pv : in std_ulogic;
cpi_lddata : in std_logic_vector(31 downto 0); -- load data
cpi_dbg_enable : in std_ulogic;
cpi_dbg_write : in std_ulogic;
cpi_dbg_fsr : in std_ulogic; -- FSR access
cpi_dbg_addr : in std_logic_vector(4 downto 0);
cpi_dbg_data : in std_logic_vector(31 downto 0);
cpo_data : out std_logic_vector(31 downto 0); -- store data
cpo_exc : out std_logic; -- FP exception
cpo_cc : out std_logic_vector(1 downto 0); -- FP condition codes
cpo_ccv : out std_ulogic; -- FP condition codes valid
cpo_ldlock : out std_logic; -- FP pipeline hold
cpo_holdn : out std_ulogic;
--cpo_restart : out std_ulogic;
cpo_dbg_data : out std_logic_vector(31 downto 0);
rfi1_rd1addr : out std_logic_vector(3 downto 0);
rfi1_rd2addr : out std_logic_vector(3 downto 0);
rfi1_wraddr : out std_logic_vector(3 downto 0);
rfi1_wrdata : out std_logic_vector(31 downto 0);
rfi1_ren1 : out std_ulogic;
rfi1_ren2 : out std_ulogic;
rfi1_wren : out std_ulogic;
rfi2_rd1addr : out std_logic_vector(3 downto 0);
rfi2_rd2addr : out std_logic_vector(3 downto 0);
rfi2_wraddr : out std_logic_vector(3 downto 0);
rfi2_wrdata : out std_logic_vector(31 downto 0);
rfi2_ren1 : out std_ulogic;
rfi2_ren2 : out std_ulogic;
rfi2_wren : out std_ulogic;
rfo1_data1 : in std_logic_vector(31 downto 0);
rfo1_data2 : in std_logic_vector(31 downto 0);
rfo2_data1 : in std_logic_vector(31 downto 0);
rfo2_data2 : in std_logic_vector(31 downto 0)
);
end component;
attribute DONT_TOUCH : boolean;
attribute DONT_TOUCH of u0_tsmc90 : label is TRUE;
begin
uni : if (tech = virtex2) or (tech = virtex4) or (tech = virtex5) or
(tech = spartan3) or (tech = spartan3e)
generate
grfpw0 : grfpw_0_unisim
port map (rst, clk, holdn, cpi_flush, cpi_exack, cpi_a_rs1, cpi_d_pc,
cpi_d_inst, cpi_d_cnt, cpi_d_trap, cpi_d_annul, cpi_d_pv, cpi_a_pc,
cpi_a_inst, cpi_a_cnt, cpi_a_trap, cpi_a_annul, cpi_a_pv, cpi_e_pc,
cpi_e_inst, cpi_e_cnt, cpi_e_trap, cpi_e_annul, cpi_e_pv, cpi_m_pc,
cpi_m_inst, cpi_m_cnt, cpi_m_trap, cpi_m_annul, cpi_m_pv, cpi_x_pc,
cpi_x_inst, cpi_x_cnt, cpi_x_trap, cpi_x_annul, cpi_x_pv, cpi_lddata,
cpi_dbg_enable, cpi_dbg_write, cpi_dbg_fsr, cpi_dbg_addr, cpi_dbg_data,
cpo_data, cpo_exc, cpo_cc, cpo_ccv, cpo_ldlock, cpo_holdn, cpo_dbg_data,
rfi1_rd1addr, rfi1_rd2addr, rfi1_wraddr, rfi1_wrdata, rfi1_ren1,
rfi1_ren2, rfi1_wren, rfi2_rd1addr, rfi2_rd2addr, rfi2_wraddr,
rfi2_wrdata, rfi2_ren1, rfi2_ren2, rfi2_wren, rfo1_data1,
rfo1_data2, rfo2_data1, rfo2_data2 );
end generate;
alt : if (tech = stratix1) or (tech = cyclone3) or
(tech = stratix2) or (tech = stratix3) or (tech = altera) generate
grfpw0 : grfpw_0_stratixii
port map (rst, clk, holdn, cpi_flush, cpi_exack, cpi_a_rs1, cpi_d_pc,
cpi_d_inst, cpi_d_cnt, cpi_d_trap, cpi_d_annul, cpi_d_pv, cpi_a_pc,
cpi_a_inst, cpi_a_cnt, cpi_a_trap, cpi_a_annul, cpi_a_pv, cpi_e_pc,
cpi_e_inst, cpi_e_cnt, cpi_e_trap, cpi_e_annul, cpi_e_pv, cpi_m_pc,
cpi_m_inst, cpi_m_cnt, cpi_m_trap, cpi_m_annul, cpi_m_pv, cpi_x_pc,
cpi_x_inst, cpi_x_cnt, cpi_x_trap, cpi_x_annul, cpi_x_pv, cpi_lddata,
cpi_dbg_enable, cpi_dbg_write, cpi_dbg_fsr, cpi_dbg_addr, cpi_dbg_data,
cpo_data, cpo_exc, cpo_cc, cpo_ccv, cpo_ldlock, cpo_holdn, cpo_dbg_data,
rfi1_rd1addr, rfi1_rd2addr, rfi1_wraddr, rfi1_wrdata, rfi1_ren1,
rfi1_ren2, rfi1_wren, rfi2_rd1addr, rfi2_rd2addr, rfi2_wraddr,
rfi2_wrdata, rfi2_ren1, rfi2_ren2, rfi2_wren, rfo1_data1,
rfo1_data2, rfo2_data1, rfo2_data2 );
end generate;
u0_tsmc90 : if tech = tsmc90 generate
grfpw0 : grfpw_tsmc90
port map (rst, clk, holdn, cpi_flush, cpi_exack, cpi_a_rs1, cpi_d_pc,
cpi_d_inst, cpi_d_cnt, cpi_d_trap, cpi_d_annul, cpi_d_pv, cpi_a_pc,
cpi_a_inst, cpi_a_cnt, cpi_a_trap, cpi_a_annul, cpi_a_pv, cpi_e_pc,
cpi_e_inst, cpi_e_cnt, cpi_e_trap, cpi_e_annul, cpi_e_pv, cpi_m_pc,
cpi_m_inst, cpi_m_cnt, cpi_m_trap, cpi_m_annul, cpi_m_pv, cpi_x_pc,
cpi_x_inst, cpi_x_cnt, cpi_x_trap, cpi_x_annul, cpi_x_pv, cpi_lddata,
cpi_dbg_enable, cpi_dbg_write, cpi_dbg_fsr, cpi_dbg_addr, cpi_dbg_data,
cpo_data, cpo_exc, cpo_cc, cpo_ccv, cpo_ldlock, cpo_holdn, cpo_dbg_data,
rfi1_rd1addr, rfi1_rd2addr, rfi1_wraddr, rfi1_wrdata, rfi1_ren1,
rfi1_ren2, rfi1_wren, rfi2_rd1addr, rfi2_rd2addr, rfi2_wraddr,
rfi2_wrdata, rfi2_ren1, rfi2_ren2, rfi2_wren, rfo1_data1,
rfo1_data2, rfo2_data1, rfo2_data2 );
end generate;
end;
| mit | a036cc9981218072eb24ee00088f18db | 0.609932 | 2.790551 | false | false | false | false |
impedimentToProgress/UCI-BlueChip | AttackFiles/Attacks/privEsc/lib/techmap/maps/clkand.vhd | 2 | 2,181 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: clkand
-- File: clkand.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: Clock gating
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.gencomp.all;
use work.allclkgen.all;
entity clkand is
generic( tech : integer := 0;
ren : integer range 0 to 1 := 0); -- registered enable
port(
i : in std_ulogic;
en : in std_ulogic;
o : out std_ulogic
);
end entity;
architecture rtl of clkand is
signal eni : std_ulogic;
begin
re : if ren = 1 generate
renproc : process(i)
begin
if falling_edge(i) then eni <= en; end if;
end process;
end generate;
ce : if ren = 0 generate eni <= en; end generate;
xil : if (tech = virtex2) or (tech = spartan3) or (tech = spartan3e)
or (tech = virtex4) or (tech = virtex5) generate
clkgate : clkand_unisim port map(I => i, en => eni, O => o);
end generate;
ut : if (tech = ut25) generate
clkgate : clkand_ut025crh port map(I => i, en => eni, O => o);
end generate;
gen : if has_clkand(tech) = 0 generate
o <= i and eni;
end generate;
end architecture;
| mit | 8420fff20a65c1a4bb6b46406656a7df | 0.592389 | 3.958258 | false | false | false | false |
impedimentToProgress/UCI-BlueChip | AttackFiles/Defense/iu33Attacks.vhd | 1 | 108,459 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008, 2009, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: iu3
-- File: iu3.vhd
-- Author: Jiri Gaisler, Edvin Catovic, Gaisler Research
-- Description: LEON3 7-stage integer pipline
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library grlib;
use grlib.sparc.all;
use grlib.stdlib.all;
library techmap;
use techmap.gencomp.all;
library gaisler;
use gaisler.leon3.all;
use gaisler.libiu.all;
use gaisler.arith.all;
-- pragma translate_off
use grlib.sparc_disas.all;
-- pragma translate_on
entity iu3 is
generic (
nwin : integer range 2 to 32 := 8;
isets : integer range 1 to 4 := 2;
dsets : integer range 1 to 4 := 2;
fpu : integer range 0 to 15 := 0;
v8 : integer range 0 to 63 := 2;
cp, mac : integer range 0 to 1 := 0;
dsu : integer range 0 to 1 := 1;
nwp : integer range 0 to 4 := 2;
pclow : integer range 0 to 2 := 2;
notag : integer range 0 to 1 := 0;
index : integer range 0 to 15:= 0;
lddel : integer range 1 to 2 := 1;
irfwt : integer range 0 to 1 := 0;
disas : integer range 0 to 2 := 0;
tbuf : integer range 0 to 64 := 2; -- trace buf size in kB (0 - no trace buffer)
pwd : integer range 0 to 2 := 0; -- power-down
svt : integer range 0 to 1 := 0; -- single-vector trapping
rstaddr : integer := 16#00000#; -- reset vector MSB address
smp : integer range 0 to 15 := 0; -- support SMP systems
fabtech : integer range 0 to NTECH := 20;
clk2x : integer := 0
);
port (
clk : in std_ulogic;
rstn : in std_ulogic;
holdn : in std_ulogic;
ici : buffer icache_in_type;
ico : in icache_out_type;
dci : buffer dcache_in_type;
dco : in dcache_out_type;
rfi : buffer iregfile_in_type;
rfo : in iregfile_out_type;
irqi : in l3_irq_in_type;
irqo : buffer l3_irq_out_type;
dbgi : in l3_debug_in_type;
dbgo : buffer l3_debug_out_type;
muli : buffer mul32_in_type;
mulo : in mul32_out_type;
divi : buffer div32_in_type;
divo : in div32_out_type;
fpo : in fpc_out_type;
fpi : buffer fpc_in_type;
cpo : in fpc_out_type;
cpi : buffer fpc_in_type;
tbo : in tracebuf_out_type;
tbi : buffer tracebuf_in_type;
sclk : in std_ulogic
);
end;
architecture rtl of iu3 is
constant ISETMSB : integer := 0;
constant DSETMSB : integer := 0;
constant RFBITS : integer range 6 to 10 := 8;
constant NWINLOG2 : integer range 1 to 5 := 3;
constant CWPOPT : boolean := true;
constant CWPMIN : std_logic_vector(2 downto 0) := "000";
constant CWPMAX : std_logic_vector(2 downto 0) := "111";
constant FPEN : boolean := (fpu /= 0);
constant CPEN : boolean := false;
constant MULEN : boolean := true;
constant MULTYPE: integer := 0;
constant DIVEN : boolean := true;
constant MACEN : boolean := false;
constant MACPIPE: boolean := false;
constant IMPL : integer := 15;
constant VER : integer := 3;
constant DBGUNIT : boolean := true;
constant TRACEBUF : boolean := true;
constant TBUFBITS : integer := 7;
constant PWRD1 : boolean := false; --(pwd = 1) and not (index /= 0);
constant PWRD2 : boolean := false; --(pwd = 2) or (index /= 0);
constant RS1OPT : boolean := true;
constant DYNRST : boolean := false;
subtype word is std_logic_vector(31 downto 0);
subtype pctype is std_logic_vector(31 downto 2);
subtype rfatype is std_logic_vector(8-1 downto 0);
subtype cwptype is std_logic_vector(3-1 downto 0);
type icdtype is array (0 to 2-1) of word;
type dcdtype is array (0 to 2-1) of word;
type dc_in_type is record
signed, enaddr, read, write, lock , dsuen : std_ulogic;
size : std_logic_vector(1 downto 0);
asi : std_logic_vector(7 downto 0);
end record;
type pipeline_ctrl_type is record
pc : pctype;
inst : word;
cnt : std_logic_vector(1 downto 0);
rd : rfatype;
tt : std_logic_vector(5 downto 0);
trap : std_ulogic;
annul : std_ulogic;
wreg : std_ulogic;
wicc : std_ulogic;
wy : std_ulogic;
ld : std_ulogic;
pv : std_ulogic;
rett : std_ulogic;
end record;
type fetch_reg_type is record
pc : pctype;
branch : std_ulogic;
end record;
type decode_reg_type is record
pc : pctype;
inst : icdtype;
cwp : cwptype;
set : std_logic_vector(0 downto 0);
mexc : std_ulogic;
cnt : std_logic_vector(1 downto 0);
pv : std_ulogic;
annul : std_ulogic;
inull : std_ulogic;
step : std_ulogic;
end record;
type regacc_reg_type is record
ctrl : pipeline_ctrl_type;
rs1 : std_logic_vector(4 downto 0);
rfa1, rfa2 : rfatype;
rsel1, rsel2 : std_logic_vector(2 downto 0);
rfe1, rfe2 : std_ulogic;
cwp : cwptype;
imm : word;
ldcheck1 : std_ulogic;
ldcheck2 : std_ulogic;
ldchkra : std_ulogic;
ldchkex : std_ulogic;
su : std_ulogic;
et : std_ulogic;
wovf : std_ulogic;
wunf : std_ulogic;
ticc : std_ulogic;
jmpl : std_ulogic;
step : std_ulogic;
mulstart : std_ulogic;
divstart : std_ulogic;
end record;
type execute_reg_type is record
ctrl : pipeline_ctrl_type;
op1 : word;
op2 : word;
aluop : std_logic_vector(2 downto 0); -- Alu operation
alusel : std_logic_vector(1 downto 0); -- Alu result select
aluadd : std_ulogic;
alucin : std_ulogic;
ldbp1, ldbp2 : std_ulogic;
invop2 : std_ulogic;
shcnt : std_logic_vector(4 downto 0); -- shift count
sari : std_ulogic; -- shift msb
shleft : std_ulogic; -- shift left/right
ymsb : std_ulogic; -- shift left/right
rd : std_logic_vector(4 downto 0);
jmpl : std_ulogic;
su : std_ulogic;
et : std_ulogic;
cwp : cwptype;
icc : std_logic_vector(3 downto 0);
mulstep: std_ulogic;
mul : std_ulogic;
mac : std_ulogic;
end record;
type memory_reg_type is record
ctrl : pipeline_ctrl_type;
result : word;
y : word;
icc : std_logic_vector(3 downto 0);
nalign : std_ulogic;
dci : dc_in_type;
werr : std_ulogic;
wcwp : std_ulogic;
irqen : std_ulogic;
irqen2 : std_ulogic;
mac : std_ulogic;
divz : std_ulogic;
su : std_ulogic;
mul : std_ulogic;
end record;
type exception_state is (run, trap, dsu1, dsu2);
type exception_reg_type is record
ctrl : pipeline_ctrl_type;
result : word;
y : word;
icc : std_logic_vector( 3 downto 0);
annul_all : std_ulogic;
data : dcdtype;
set : std_logic_vector(0 downto 0);
mexc : std_ulogic;
dci : dc_in_type;
laddr : std_logic_vector(1 downto 0);
rstate : exception_state;
npc : std_logic_vector(2 downto 0);
intack : std_ulogic;
ipend : std_ulogic;
mac : std_ulogic;
debug : std_ulogic;
nerror : std_ulogic;
end record;
type dsu_registers is record
tt : std_logic_vector(7 downto 0);
err : std_ulogic;
tbufcnt : std_logic_vector(7-1 downto 0);
asi : std_logic_vector(7 downto 0);
crdy : std_logic_vector(2 downto 1); -- diag cache access ready
end record;
type irestart_register is record
addr : pctype;
pwd : std_ulogic;
end record;
type pwd_register_type is record
pwd : std_ulogic;
error : std_ulogic;
end record;
type special_register_type is record
cwp : cwptype; -- current window pointer
icc : std_logic_vector(3 downto 0); -- integer condition codes
tt : std_logic_vector(7 downto 0); -- trap type
tba : std_logic_vector(19 downto 0); -- trap base address
wim : std_logic_vector(8-1 downto 0); -- window invalid mask
pil : std_logic_vector(3 downto 0); -- processor interrupt level
ec : std_ulogic; -- enable CP
ef : std_ulogic; -- enable FP
ps : std_ulogic; -- previous supervisor flag
s : std_ulogic; -- supervisor flag
et : std_ulogic; -- enable traps
y : word;
asr18 : word;
svt : std_ulogic; -- enable traps
dwt : std_ulogic; -- disable write error trap
end record;
type write_reg_type is record
s : special_register_type;
result : word;
wa : rfatype;
wreg : std_ulogic;
except : std_ulogic;
end record;
type registers is record
f : fetch_reg_type;
d : decode_reg_type;
a : regacc_reg_type;
e : execute_reg_type;
m : memory_reg_type;
x : exception_reg_type;
w : write_reg_type;
end record;
type exception_type is record
pri : std_ulogic;
ill : std_ulogic;
fpdis : std_ulogic;
cpdis : std_ulogic;
wovf : std_ulogic;
wunf : std_ulogic;
ticc : std_ulogic;
end record;
type watchpoint_register is record
addr : std_logic_vector(31 downto 2); -- watchpoint address
mask : std_logic_vector(31 downto 2); -- watchpoint mask
exec : std_ulogic; -- trap on instruction
load : std_ulogic; -- trap on load
store : std_ulogic; -- trap on store
end record;
type watchpoint_registers is array (0 to 3) of watchpoint_register;
constant wpr_none : watchpoint_register := (
"000000000000000000000000000000", "000000000000000000000000000000", '0', '0', '0');
function dbgexc(r : registers; dbgi : l3_debug_in_type; trap : std_ulogic; tt : std_logic_vector(7 downto 0)) return std_ulogic is
variable dmode : std_ulogic;
begin
dmode := '0';
if (not r.x.ctrl.annul and trap) = '1' then
if (((tt = "00" & TT_WATCH) and (dbgi.bwatch = '1')) or
((dbgi.bsoft = '1') and (tt = "10000001")) or
(dbgi.btrapa = '1') or
((dbgi.btrape = '1') and not ((tt(5 downto 0) = TT_PRIV) or
(tt(5 downto 0) = TT_FPDIS) or (tt(5 downto 0) = TT_WINOF) or
(tt(5 downto 0) = TT_WINUF) or (tt(5 downto 4) = "01") or (tt(7) = '1'))) or
(((not r.w.s.et) and dbgi.berror) = '1')) then
dmode := '1';
end if;
end if;
return(dmode);
end;
function dbgerr(r : registers; dbgi : l3_debug_in_type;
tt : std_logic_vector(7 downto 0))
return std_ulogic is
variable err : std_ulogic;
begin
err := not r.w.s.et;
if (((dbgi.dbreak = '1') and (tt = ("00" & TT_WATCH))) or
((dbgi.bsoft = '1') and (tt = ("10000001")))) then
err := '0';
end if;
return(err);
end;
procedure diagwr(r : in registers;
dsur : in dsu_registers;
ir : in irestart_register;
dbg : in l3_debug_in_type;
wpr : in watchpoint_registers;
s : out special_register_type;
vwpr : out watchpoint_registers;
asi : out std_logic_vector(7 downto 0);
pc, npc : out pctype;
tbufcnt : out std_logic_vector(7-1 downto 0);
wr : out std_ulogic;
addr : out std_logic_vector(9 downto 0);
data : out word;
fpcwr : out std_ulogic) is
variable i : integer range 0 to 3;
begin
s := r.w.s; pc := r.f.pc; npc := ir.addr; wr := '0';
vwpr := wpr; asi := dsur.asi; addr := "0000000000";
data := dbg.ddata;
tbufcnt := dsur.tbufcnt; fpcwr := '0';
if (dbg.dsuen and dbg.denable and dbg.dwrite) = '1' then
case dbg.daddr(23 downto 20) is
when "0001" =>
if (dbg.daddr(16) = '1') and true then -- trace buffer control reg
tbufcnt := dbg.ddata(7-1 downto 0);
end if;
when "0011" => -- IU reg file
if dbg.daddr(12) = '0' then
wr := '1';
addr := "0000000000";
addr(8-1 downto 0) := dbg.daddr(8+1 downto 2);
else -- FPC
fpcwr := '1';
end if;
when "0100" => -- IU special registers
case dbg.daddr(7 downto 6) is
when "00" => -- IU regs Y - TBUF ctrl reg
case dbg.daddr(5 downto 2) is
when "0000" => -- Y
s.y := dbg.ddata;
when "0001" => -- PSR
s.cwp := dbg.ddata(3-1 downto 0);
s.icc := dbg.ddata(23 downto 20);
s.ec := dbg.ddata(13);
if FPEN then s.ef := dbg.ddata(12); end if;
s.pil := dbg.ddata(11 downto 8);
s.s := dbg.ddata(7);
s.ps := dbg.ddata(6);
s.et := dbg.ddata(5);
when "0010" => -- WIM
s.wim := dbg.ddata(8-1 downto 0);
when "0011" => -- TBR
s.tba := dbg.ddata(31 downto 12);
s.tt := dbg.ddata(11 downto 4);
when "0100" => -- PC
pc := dbg.ddata(31 downto 2);
when "0101" => -- NPC
npc := dbg.ddata(31 downto 2);
when "0110" => --FSR
fpcwr := '1';
when "0111" => --CFSR
when "1001" => -- ASI reg
asi := dbg.ddata(7 downto 0);
--when "1001" => -- TBUF ctrl reg
-- tbufcnt := dbg.ddata(7-1 downto 0);
when others =>
end case;
when "01" => -- ASR16 - ASR31
case dbg.daddr(5 downto 2) is
when "0001" => -- %ASR17
s.dwt := dbg.ddata(14);
s.svt := dbg.ddata(13);
when "0010" => -- %ASR18
if false then s.asr18 := dbg.ddata; end if;
when "1000" => -- %ASR24 - %ASR31
vwpr(0).addr := dbg.ddata(31 downto 2);
vwpr(0).exec := dbg.ddata(0);
when "1001" =>
vwpr(0).mask := dbg.ddata(31 downto 2);
vwpr(0).load := dbg.ddata(1);
vwpr(0).store := dbg.ddata(0);
when "1010" =>
vwpr(1).addr := dbg.ddata(31 downto 2);
vwpr(1).exec := dbg.ddata(0);
when "1011" =>
vwpr(1).mask := dbg.ddata(31 downto 2);
vwpr(1).load := dbg.ddata(1);
vwpr(1).store := dbg.ddata(0);
when "1100" =>
vwpr(2).addr := dbg.ddata(31 downto 2);
vwpr(2).exec := dbg.ddata(0);
when "1101" =>
vwpr(2).mask := dbg.ddata(31 downto 2);
vwpr(2).load := dbg.ddata(1);
vwpr(2).store := dbg.ddata(0);
when "1110" =>
vwpr(3).addr := dbg.ddata(31 downto 2);
vwpr(3).exec := dbg.ddata(0);
when "1111" => --
vwpr(3).mask := dbg.ddata(31 downto 2);
vwpr(3).load := dbg.ddata(1);
vwpr(3).store := dbg.ddata(0);
when others => --
end case;
-- disabled due to bug in XST
-- i := conv_integer(dbg.daddr(4 downto 3));
-- if dbg.daddr(2) = '0' then
-- vwpr(i).addr := dbg.ddata(31 downto 2);
-- vwpr(i).exec := dbg.ddata(0);
-- else
-- vwpr(i).mask := dbg.ddata(31 downto 2);
-- vwpr(i).load := dbg.ddata(1);
-- vwpr(i).store := dbg.ddata(0);
-- end if;
when others =>
end case;
when others =>
end case;
end if;
end;
function asr17_gen ( r : in registers) return word is
variable asr17 : word;
variable fpu2 : integer range 0 to 3;
begin
asr17 := "00000000000000000000000000000000";
asr17(31 downto 28) := conv_std_logic_vector(index, 4);
if (clk2x > 8) then
asr17(16 downto 15) := conv_std_logic_vector(clk2x-8, 2);
asr17(17) := '1';
elsif (clk2x > 0) then
asr17(16 downto 15) := conv_std_logic_vector(clk2x, 2);
end if;
asr17(14) := r.w.s.dwt;
if svt = 1 then asr17(13) := r.w.s.svt; end if;
if lddel = 2 then asr17(12) := '1'; end if;
if (fpu > 0) and (fpu < 8) then fpu2 := 1;
elsif (fpu >= 8) and (fpu < 15) then fpu2 := 3;
elsif fpu = 15 then fpu2 := 2;
else fpu2 := 0; end if;
asr17(11 downto 10) := conv_std_logic_vector(fpu2, 2);
if mac = 1 then asr17(9) := '1'; end if;
if 2 /= 0 then asr17(8) := '1'; end if;
asr17(7 downto 5) := conv_std_logic_vector(nwp, 3);
asr17(4 downto 0) := conv_std_logic_vector(8-1, 5);
return(asr17);
end;
procedure diagread(dbgi : in l3_debug_in_type;
r : in registers;
dsur : in dsu_registers;
ir : in irestart_register;
wpr : in watchpoint_registers;
dco : in dcache_out_type;
tbufo : in tracebuf_out_type;
data : out word) is
variable cwp : std_logic_vector(4 downto 0);
variable rd : std_logic_vector(4 downto 0);
variable i : integer range 0 to 3;
begin
data := "00000000000000000000000000000000"; cwp := "00000";
cwp(3-1 downto 0) := r.w.s.cwp;
case dbgi.daddr(22 downto 20) is
when "001" => -- trace buffer
if true then
if dbgi.daddr(16) = '1' then -- trace buffer control reg
if true then data(7-1 downto 0) := dsur.tbufcnt; end if;
else
case dbgi.daddr(3 downto 2) is
when "00" => data := tbufo.data(127 downto 96);
when "01" => data := tbufo.data(95 downto 64);
when "10" => data := tbufo.data(63 downto 32);
when others => data := tbufo.data(31 downto 0);
end case;
end if;
end if;
when "011" => -- IU reg file
if dbgi.daddr(12) = '0' then
data := rfo.data1(31 downto 0);
if (dbgi.daddr(11) = '1') and (is_fpga(fabtech) = 0) then
data := rfo.data2(31 downto 0);
end if;
else data := fpo.dbg.data; end if;
when "100" => -- IU regs
case dbgi.daddr(7 downto 6) is
when "00" => -- IU regs Y - TBUF ctrl reg
case dbgi.daddr(5 downto 2) is
when "0000" =>
data := r.w.s.y;
when "0001" =>
data := conv_std_logic_vector(15, 4) & conv_std_logic_vector(3, 4) &
r.w.s.icc & "000000" & r.w.s.ec & r.w.s.ef & r.w.s.pil &
r.w.s.s & r.w.s.ps & r.w.s.et & cwp;
when "0010" =>
data(8-1 downto 0) := r.w.s.wim;
when "0011" =>
data := r.w.s.tba & r.w.s.tt & "0000";
when "0100" =>
data(31 downto 2) := r.f.pc;
when "0101" =>
data(31 downto 2) := ir.addr;
when "0110" => -- FSR
data := fpo.dbg.data;
when "0111" => -- CPSR
when "1000" => -- TT reg
data(12 downto 4) := dsur.err & dsur.tt;
when "1001" => -- ASI reg
data(7 downto 0) := dsur.asi;
when others =>
end case;
when "01" =>
if dbgi.daddr(5) = '0' then -- %ASR17
if dbgi.daddr(4 downto 2) = "001" then -- %ASR17
data := asr17_gen(r);
elsif false and dbgi.daddr(4 downto 2) = "010" then -- %ASR18
data := r.w.s.asr18;
end if;
else -- %ASR24 - %ASR31
i := conv_integer(dbgi.daddr(4 downto 3)); --
if dbgi.daddr(2) = '0' then
data(31 downto 2) := wpr(i).addr;
data(0) := wpr(i).exec;
else
data(31 downto 2) := wpr(i).mask;
data(1) := wpr(i).load;
data(0) := wpr(i).store;
end if;
end if;
when others =>
end case;
when "111" =>
data := r.x.data(conv_integer(r.x.set));
when others =>
end case;
end;
procedure itrace(r : in registers;
dsur : in dsu_registers;
vdsu : in dsu_registers;
res : in word;
exc : in std_ulogic;
dbgi : in l3_debug_in_type;
error : in std_ulogic;
trap : in std_ulogic;
tbufcnt : out std_logic_vector(7-1 downto 0);
di : out tracebuf_in_type) is
variable meminst : std_ulogic;
begin
di.addr := (others => '0'); di.data := (others => '0');
di.enable := '0'; di.write := (others => '0');
tbufcnt := vdsu.tbufcnt;
meminst := r.x.ctrl.inst(31) and r.x.ctrl.inst(30);
if true then
di.addr(7-1 downto 0) := dsur.tbufcnt;
di.data(127) := '0';
di.data(126) := not r.x.ctrl.pv;
di.data(125 downto 96) := dbgi.timer(29 downto 0);
di.data(95 downto 64) := res;
di.data(63 downto 34) := r.x.ctrl.pc(31 downto 2);
di.data(33) := trap;
di.data(32) := error;
di.data(31 downto 0) := r.x.ctrl.inst;
if (dbgi.tenable = '0') or (r.x.rstate = dsu2) then
if ((dbgi.dsuen and dbgi.denable) = '1') and (dbgi.daddr(23 downto 20) & dbgi.daddr(16) = "00010") then
di.enable := '1';
di.addr(7-1 downto 0) := dbgi.daddr(7-1+4 downto 4);
if dbgi.dwrite = '1' then
case dbgi.daddr(3 downto 2) is
when "00" => di.write(3) := '1';
when "01" => di.write(2) := '1';
when "10" => di.write(1) := '1';
when others => di.write(0) := '1';
end case;
di.data := dbgi.ddata & dbgi.ddata & dbgi.ddata & dbgi.ddata;
end if;
end if;
elsif (not r.x.ctrl.annul and (r.x.ctrl.pv or meminst) and not r.x.debug) = '1' then
di.enable := '1'; di.write := (others => '1');
tbufcnt := dsur.tbufcnt + 1;
end if;
di.diag := dco.testen & "000";
if dco.scanen = '1' then di.enable := '0'; end if;
end if;
end;
procedure dbg_cache(holdn : in std_ulogic;
dbgi : in l3_debug_in_type;
r : in registers;
dsur : in dsu_registers;
mresult : in word;
dci : in dc_in_type;
mresult2 : out word;
dci2 : out dc_in_type
) is
begin
mresult2 := mresult; dci2 := dci; dci2.dsuen := '0';
if true then
if r.x.rstate = dsu2 then
dci2.asi := dsur.asi;
if (dbgi.daddr(22 downto 20) = "111") and (dbgi.dsuen = '1') then
dci2.dsuen := (dbgi.denable or r.m.dci.dsuen) and not dsur.crdy(2);
dci2.enaddr := dbgi.denable;
dci2.size := "10"; dci2.read := '1'; dci2.write := '0';
if (dbgi.denable and not r.m.dci.enaddr) = '1' then
mresult2 := (others => '0'); mresult2(19 downto 2) := dbgi.daddr(19 downto 2);
else
mresult2 := dbgi.ddata;
end if;
if dbgi.dwrite = '1' then
dci2.read := '0'; dci2.write := '1';
end if;
end if;
end if;
end if;
end;
procedure fpexack(r : in registers; fpexc : out std_ulogic) is
begin
fpexc := '0';
if FPEN then
if r.x.ctrl.tt = TT_FPEXC then fpexc := '1'; end if;
end if;
end;
procedure diagrdy(denable : in std_ulogic;
dsur : in dsu_registers;
dci : in dc_in_type;
mds : in std_ulogic;
ico : in icache_out_type;
crdy : out std_logic_vector(2 downto 1)) is
begin
crdy := dsur.crdy(1) & '0';
if dci.dsuen = '1' then
case dsur.asi(4 downto 0) is
when ASI_ITAG | ASI_IDATA | ASI_UINST | ASI_SINST =>
crdy(2) := ico.diagrdy and not dsur.crdy(2);
when ASI_DTAG | ASI_MMUSNOOP_DTAG | ASI_DDATA | ASI_UDATA | ASI_SDATA =>
crdy(1) := not denable and dci.enaddr and not dsur.crdy(1);
when others =>
crdy(2) := dci.enaddr and denable;
end case;
end if;
end;
signal r, rin : registers;
signal wpr, wprin : watchpoint_registers;
signal dsur, dsuin : dsu_registers;
signal ir, irin : irestart_register;
signal rp, rpin : pwd_register_type;
-- execute stage operations
constant EXE_AND : std_logic_vector(2 downto 0) := "000";
constant EXE_XOR : std_logic_vector(2 downto 0) := "001"; -- must be equal to EXE_PASS2
constant EXE_OR : std_logic_vector(2 downto 0) := "010";
constant EXE_XNOR : std_logic_vector(2 downto 0) := "011";
constant EXE_ANDN : std_logic_vector(2 downto 0) := "100";
constant EXE_ORN : std_logic_vector(2 downto 0) := "101";
constant EXE_DIV : std_logic_vector(2 downto 0) := "110";
constant EXE_PASS1 : std_logic_vector(2 downto 0) := "000";
constant EXE_PASS2 : std_logic_vector(2 downto 0) := "001";
constant EXE_STB : std_logic_vector(2 downto 0) := "010";
constant EXE_STH : std_logic_vector(2 downto 0) := "011";
constant EXE_ONES : std_logic_vector(2 downto 0) := "100";
constant EXE_RDY : std_logic_vector(2 downto 0) := "101";
constant EXE_SPR : std_logic_vector(2 downto 0) := "110";
constant EXE_LINK : std_logic_vector(2 downto 0) := "111";
constant EXE_SLL : std_logic_vector(2 downto 0) := "001";
constant EXE_SRL : std_logic_vector(2 downto 0) := "010";
constant EXE_SRA : std_logic_vector(2 downto 0) := "100";
constant EXE_NOP : std_logic_vector(2 downto 0) := "000";
-- EXE result select
constant EXE_RES_ADD : std_logic_vector(1 downto 0) := "00";
constant EXE_RES_SHIFT : std_logic_vector(1 downto 0) := "01";
constant EXE_RES_LOGIC : std_logic_vector(1 downto 0) := "10";
constant EXE_RES_MISC : std_logic_vector(1 downto 0) := "11";
-- Load types
constant SZBYTE : std_logic_vector(1 downto 0) := "00";
constant SZHALF : std_logic_vector(1 downto 0) := "01";
constant SZWORD : std_logic_vector(1 downto 0) := "10";
constant SZDBL : std_logic_vector(1 downto 0) := "11";
-- calculate register file address
procedure regaddr(cwp : std_logic_vector; reg : std_logic_vector(4 downto 0);
rao : out rfatype) is
variable ra : rfatype;
constant globals : std_logic_vector(8-5 downto 0) :=
conv_std_logic_vector(8, 8-4);
begin
ra := (others => '0'); ra(4 downto 0) := reg;
if reg(4 downto 3) = "00" then ra(8 -1 downto 4) := globals;
else
ra(3+3 downto 4) := cwp + ra(4);
if ra(8-1 downto 4) = globals then
ra(8-1 downto 4) := (others => '0');
end if;
end if;
rao := ra;
end;
-- branch adder
function branch_address(inst : word; pc : pctype) return std_logic_vector is
variable baddr, caddr, tmp : pctype;
begin
caddr := (others => '0'); caddr(31 downto 2) := inst(29 downto 0);
caddr(31 downto 2) := caddr(31 downto 2) + pc(31 downto 2);
baddr := (others => '0'); baddr(31 downto 24) := (others => inst(21));
baddr(23 downto 2) := inst(21 downto 0);
baddr(31 downto 2) := baddr(31 downto 2) + pc(31 downto 2);
if inst(30) = '1' then tmp := caddr; else tmp := baddr; end if;
return(tmp);
end;
-- evaluate branch condition
function branch_true(icc : std_logic_vector(3 downto 0); inst : word)
return std_ulogic is
variable n, z, v, c, branch : std_ulogic;
begin
n := icc(3); z := icc(2); v := icc(1); c := icc(0);
case inst(27 downto 25) is
when "000" => branch := inst(28) xor '0'; -- bn, ba
when "001" => branch := inst(28) xor z; -- be, bne
when "010" => branch := inst(28) xor (z or (n xor v)); -- ble, bg
when "011" => branch := inst(28) xor (n xor v); -- bl, bge
when "100" => branch := inst(28) xor (c or z); -- bleu, bgu
when "101" => branch := inst(28) xor c; -- bcs, bcc
when "110" => branch := inst(28) xor n; -- bneg, bpos
when others => branch := inst(28) xor v; -- bvs, bvc
end case;
return(branch);
end;
-- detect RETT instruction in the pipeline and set the local psr.su and psr.et
procedure su_et_select(r : in registers; xc_ps, xc_s, xc_et : in std_ulogic;
su, et : out std_ulogic) is
begin
if ((r.a.ctrl.rett or r.e.ctrl.rett or r.m.ctrl.rett or r.x.ctrl.rett) = '1')
and (r.x.annul_all = '0')
then su := xc_ps; et := '1';
else su := xc_s; et := xc_et; end if;
end;
-- detect watchpoint trap
function wphit(r : registers; wpr : watchpoint_registers; debug : l3_debug_in_type)
return std_ulogic is
variable exc : std_ulogic;
begin
exc := '0';
for i in 1 to NWP loop
if ((wpr(i-1).exec and r.a.ctrl.pv and not r.a.ctrl.annul) = '1') then
if (((wpr(i-1).addr xor r.a.ctrl.pc(31 downto 2)) and wpr(i-1).mask) = "000000000000000000000000000000") then
exc := '1';
end if;
end if;
end loop;
if true then
if (debug.dsuen and not r.a.ctrl.annul) = '1' then
exc := exc or (r.a.ctrl.pv and ((debug.dbreak and debug.bwatch) or r.a.step));
end if;
end if;
return(exc);
end;
-- 32-bit shifter
function shift3(r : registers; aluin1, aluin2 : word) return word is
variable shiftin : unsigned(63 downto 0);
variable shiftout : unsigned(63 downto 0);
variable cnt : natural range 0 to 31;
begin
cnt := conv_integer(r.e.shcnt);
if r.e.shleft = '1' then
shiftin(30 downto 0) := (others => '0');
shiftin(63 downto 31) := '0' & unsigned(aluin1);
else
shiftin(63 downto 32) := (others => r.e.sari);
shiftin(31 downto 0) := unsigned(aluin1);
end if;
shiftout := SHIFT_RIGHT(shiftin, cnt);
return(std_logic_vector(shiftout(31 downto 0)));
end;
function shift2(r : registers; aluin1, aluin2 : word) return word is
variable ushiftin : unsigned(31 downto 0);
variable sshiftin : signed(32 downto 0);
variable cnt : natural range 0 to 31;
variable resleft, resright : word;
begin
cnt := conv_integer(r.e.shcnt);
ushiftin := unsigned(aluin1);
sshiftin := signed('0' & aluin1);
if r.e.shleft = '1' then
resleft := std_logic_vector(SHIFT_LEFT(ushiftin, cnt));
return(resleft);
else
if r.e.sari = '1' then sshiftin(32) := aluin1(31); end if;
sshiftin := SHIFT_RIGHT(sshiftin, cnt);
resright := std_logic_vector(sshiftin(31 downto 0));
return(resright);
-- else
-- ushiftin := SHIFT_RIGHT(ushiftin, cnt);
-- return(std_logic_vector(ushiftin));
-- end if;
end if;
end;
function shift(r : registers; aluin1, aluin2 : word;
shiftcnt : std_logic_vector(4 downto 0); sari : std_ulogic ) return word is
variable shiftin : std_logic_vector(63 downto 0);
begin
shiftin := "00000000000000000000000000000000" & aluin1;
if r.e.shleft = '1' then
shiftin(31 downto 0) := "00000000000000000000000000000000"; shiftin(63 downto 31) := '0' & aluin1;
else shiftin(63 downto 32) := (others => sari); end if;
if shiftcnt (4) = '1' then shiftin(47 downto 0) := shiftin(63 downto 16); end if;
if shiftcnt (3) = '1' then shiftin(39 downto 0) := shiftin(47 downto 8); end if;
if shiftcnt (2) = '1' then shiftin(35 downto 0) := shiftin(39 downto 4); end if;
if shiftcnt (1) = '1' then shiftin(33 downto 0) := shiftin(35 downto 2); end if;
if shiftcnt (0) = '1' then shiftin(31 downto 0) := shiftin(32 downto 1); end if;
return(shiftin(31 downto 0));
end;
-- Check for illegal and privileged instructions
procedure exception_detect(r : registers; wpr : watchpoint_registers; dbgi : l3_debug_in_type;
trapin : in std_ulogic; ttin : in std_logic_vector(5 downto 0);
trap : out std_ulogic; tt : out std_logic_vector(5 downto 0)) is
variable illegal_inst, privileged_inst : std_ulogic;
variable cp_disabled, fp_disabled, fpop : std_ulogic;
variable op : std_logic_vector(1 downto 0);
variable op2 : std_logic_vector(2 downto 0);
variable op3 : std_logic_vector(5 downto 0);
variable rd : std_logic_vector(4 downto 0);
variable inst : word;
variable wph : std_ulogic;
begin
inst := r.a.ctrl.inst; trap := trapin; tt := ttin;
if r.a.ctrl.annul = '0' then
op := inst(31 downto 30); op2 := inst(24 downto 22);
op3 := inst(24 downto 19); rd := inst(29 downto 25);
illegal_inst := '0'; privileged_inst := '0'; cp_disabled := '0';
fp_disabled := '0'; fpop := '0';
case op is
when CALL => null;
when FMT2 =>
case op2 is
when SETHI | BICC => null;
when FBFCC =>
if FPEN then fp_disabled := not r.w.s.ef; else fp_disabled := '1'; end if;
when CBCCC =>
if (not false) or (r.w.s.ec = '0') then cp_disabled := '1'; end if;
when others => illegal_inst := '1';
end case;
when FMT3 =>
case op3 is
when IAND | ANDCC | ANDN | ANDNCC | IOR | ORCC | ORN | ORNCC | IXOR |
XORCC | IXNOR | XNORCC | ISLL | ISRL | ISRA | MULSCC | IADD | ADDX |
ADDCC | ADDXCC | ISUB | SUBX | SUBCC | SUBXCC | FLUSH | JMPL | TICC |
SAVE | RESTORE | RDY => null;
when TADDCC | TADDCCTV | TSUBCC | TSUBCCTV =>
if notag = 1 then illegal_inst := '1'; end if;
when UMAC | SMAC =>
if not false then illegal_inst := '1'; end if;
when UMUL | SMUL | UMULCC | SMULCC =>
if not true then illegal_inst := '1'; end if;
when UDIV | SDIV | UDIVCC | SDIVCC =>
if not true then illegal_inst := '1'; end if;
when RETT => illegal_inst := r.a.et; privileged_inst := not r.a.su;
when RDPSR | RDTBR | RDWIM => privileged_inst := not r.a.su;
when WRY => null;
when WRPSR =>
privileged_inst := not r.a.su;
when WRWIM | WRTBR => privileged_inst := not r.a.su;
when FPOP1 | FPOP2 =>
if FPEN then fp_disabled := not r.w.s.ef; fpop := '1';
else fp_disabled := '1'; fpop := '0'; end if;
when CPOP1 | CPOP2 =>
if (not false) or (r.w.s.ec = '0') then cp_disabled := '1'; end if;
when others => illegal_inst := '1';
end case;
when others => -- LDST
case op3 is
when LDD | ISTD => illegal_inst := rd(0); -- trap if odd destination register
when LD | LDUB | LDSTUB | LDUH | LDSB | LDSH | ST | STB | STH | SWAP =>
null;
when LDDA | STDA =>
illegal_inst := inst(13) or rd(0); privileged_inst := not r.a.su;
when LDA | LDUBA| LDSTUBA | LDUHA | LDSBA | LDSHA | STA | STBA | STHA |
SWAPA =>
illegal_inst := inst(13); privileged_inst := not r.a.su;
when LDDF | STDF | LDF | LDFSR | STF | STFSR =>
if FPEN then fp_disabled := not r.w.s.ef;
else fp_disabled := '1'; end if;
when STDFQ =>
privileged_inst := not r.a.su;
if (not FPEN) or (r.w.s.ef = '0') then fp_disabled := '1'; end if;
when STDCQ =>
privileged_inst := not r.a.su;
if (not false) or (r.w.s.ec = '0') then cp_disabled := '1'; end if;
when LDC | LDCSR | LDDC | STC | STCSR | STDC =>
if (not false) or (r.w.s.ec = '0') then cp_disabled := '1'; end if;
when others => illegal_inst := '1';
end case;
end case;
wph := wphit(r, wpr, dbgi);
trap := '1';
if r.a.ctrl.trap = '1' then tt := TT_IAEX;
elsif privileged_inst = '1' then tt := TT_PRIV;
elsif illegal_inst = '1' then tt := TT_IINST;
elsif fp_disabled = '1' then tt := TT_FPDIS;
elsif cp_disabled = '1' then tt := TT_CPDIS;
elsif wph = '1' then tt := TT_WATCH;
elsif r.a.wovf= '1' then tt := TT_WINOF;
elsif r.a.wunf= '1' then tt := TT_WINUF;
elsif r.a.ticc= '1' then tt := TT_TICC;
else trap := '0'; tt:= (others => '0'); end if;
end if;
end;
-- instructions that write the condition codes (psr.icc)
procedure wicc_y_gen(inst : word; wicc, wy : out std_ulogic) is
begin
wicc := '0'; wy := '0';
if inst(31 downto 30) = FMT3 then
case inst(24 downto 19) is
when SUBCC | TSUBCC | TSUBCCTV | ADDCC | ANDCC | ORCC | XORCC | ANDNCC |
ORNCC | XNORCC | TADDCC | TADDCCTV | ADDXCC | SUBXCC | WRPSR =>
wicc := '1';
when WRY =>
if r.d.inst(conv_integer(r.d.set))(29 downto 25) = "00000" then wy := '1'; end if;
when MULSCC =>
wicc := '1'; wy := '1';
when UMAC | SMAC =>
if false then wy := '1'; end if;
when UMULCC | SMULCC =>
if true and (((mulo.nready = '1') and (r.d.cnt /= "00")) or (0 /= 0)) then
wicc := '1'; wy := '1';
end if;
when UMUL | SMUL =>
if true and (((mulo.nready = '1') and (r.d.cnt /= "00")) or (0 /= 0)) then
wy := '1';
end if;
when UDIVCC | SDIVCC =>
if true and (divo.nready = '1') and (r.d.cnt /= "00") then
wicc := '1';
end if;
when others =>
end case;
end if;
end;
-- select cwp
procedure cwp_gen(r, v : registers; annul, wcwp : std_ulogic; ncwp : cwptype;
cwp : out cwptype) is
begin
if (r.x.rstate = trap) or (r.x.rstate = dsu2) or (rstn = '0') then cwp := v.w.s.cwp;
elsif (wcwp = '1') and (annul = '0') then cwp := ncwp;
elsif r.m.wcwp = '1' then cwp := r.m.result(3-1 downto 0);
else cwp := r.d.cwp; end if;
end;
-- generate wcwp in ex stage
procedure cwp_ex(r : in registers; wcwp : out std_ulogic) is
begin
if (r.e.ctrl.inst(31 downto 30) = FMT3) and
(r.e.ctrl.inst(24 downto 19) = WRPSR)
then wcwp := not r.e.ctrl.annul; else wcwp := '0'; end if;
end;
-- generate next cwp & window under- and overflow traps
procedure cwp_ctrl(r : in registers; xc_wim : in std_logic_vector(8-1 downto 0);
inst : word; de_cwp : out cwptype; wovf_exc, wunf_exc, wcwp : out std_ulogic) is
variable op : std_logic_vector(1 downto 0);
variable op3 : std_logic_vector(5 downto 0);
variable wim : word;
variable ncwp : cwptype;
begin
op := inst(31 downto 30); op3 := inst(24 downto 19);
wovf_exc := '0'; wunf_exc := '0'; wim := (others => '0');
wim(8-1 downto 0) := xc_wim; ncwp := r.d.cwp; wcwp := '0';
if (op = FMT3) and ((op3 = RETT) or (op3 = RESTORE) or (op3 = SAVE)) then
wcwp := '1';
if (op3 = SAVE) then
if (not true) and (r.d.cwp = "000") then ncwp := "111";
else ncwp := r.d.cwp - 1 ; end if;
else
if (not true) and (r.d.cwp = "111") then ncwp := "000";
else ncwp := r.d.cwp + 1; end if;
end if;
if wim(conv_integer(ncwp)) = '1' then
if op3 = SAVE then wovf_exc := '1'; else wunf_exc := '1'; end if;
end if;
end if;
de_cwp := ncwp;
end;
-- generate register read address 1
procedure rs1_gen(r : registers; inst : word; rs1 : out std_logic_vector(4 downto 0);
rs1mod : out std_ulogic) is
variable op : std_logic_vector(1 downto 0);
variable op3 : std_logic_vector(5 downto 0);
begin
op := inst(31 downto 30); op3 := inst(24 downto 19);
rs1 := inst(18 downto 14); rs1mod := '0';
if (op = LDST) then
if ((r.d.cnt = "01") and ((op3(2) and not op3(3)) = '1')) or
(r.d.cnt = "10")
then rs1mod := '1'; rs1 := inst(29 downto 25); end if;
if ((r.d.cnt = "10") and (op3(3 downto 0) = "0111")) then
rs1(0) := '1';
end if;
end if;
end;
-- load/icc interlock detection
procedure lock_gen(r : registers; rs2, rd : std_logic_vector(4 downto 0);
rfa1, rfa2, rfrd : rfatype; inst : word; fpc_lock, mulinsn, divinsn : std_ulogic;
lldcheck1, lldcheck2, lldlock, lldchkra, lldchkex : out std_ulogic) is
variable op : std_logic_vector(1 downto 0);
variable op2 : std_logic_vector(2 downto 0);
variable op3 : std_logic_vector(5 downto 0);
variable cond : std_logic_vector(3 downto 0);
variable rs1 : std_logic_vector(4 downto 0);
variable i, ldcheck1, ldcheck2, ldchkra, ldchkex, ldcheck3 : std_ulogic;
variable ldlock, icc_check, bicc_hold, chkmul, y_check : std_ulogic;
variable lddlock : boolean;
begin
op := inst(31 downto 30); op3 := inst(24 downto 19);
op2 := inst(24 downto 22); cond := inst(28 downto 25);
rs1 := inst(18 downto 14); lddlock := false; i := inst(13);
ldcheck1 := '0'; ldcheck2 := '0'; ldcheck3 := '0'; ldlock := '0';
ldchkra := '1'; ldchkex := '1'; icc_check := '0'; bicc_hold := '0';
y_check := '0';
if (r.d.annul = '0') then
case op is
when FMT2 =>
if (op2 = BICC) and (cond(2 downto 0) /= "000") then
icc_check := '1';
end if;
when FMT3 =>
ldcheck1 := '1'; ldcheck2 := not i;
case op3 is
when TICC =>
if (cond(2 downto 0) /= "000") then icc_check := '1'; end if;
when RDY =>
ldcheck1 := '0'; ldcheck2 := '0';
if false then y_check := '1'; end if;
when RDWIM | RDTBR =>
ldcheck1 := '0'; ldcheck2 := '0';
when RDPSR =>
ldcheck1 := '0'; ldcheck2 := '0'; icc_check := '1';
if true then icc_check := '1'; end if;
-- when ADDX | ADDXCC | SUBX | SUBXCC =>
-- if true then icc_check := '1'; end if;
when SDIV | SDIVCC | UDIV | UDIVCC =>
if true then y_check := '1'; end if;
when FPOP1 | FPOP2 => ldcheck1:= '0'; ldcheck2 := '0';
when others =>
end case;
when LDST =>
ldcheck1 := '1'; ldchkra := '0';
case r.d.cnt is
when "00" =>
if (lddel = 2) and (op3(2) = '1') then ldcheck3 := '1'; end if;
ldcheck2 := not i; ldchkra := '1';
when "01" => ldcheck2 := not i;
when others => ldchkex := '0';
end case;
if (op3(2 downto 0) = "011") then lddlock := true; end if;
when others => null;
end case;
end if;
if true or true then
chkmul := mulinsn;
bicc_hold := bicc_hold or (icc_check and r.m.ctrl.wicc and (r.m.ctrl.cnt(0) or r.m.mul));
else chkmul := '0'; end if;
if true then
bicc_hold := bicc_hold or (y_check and (r.a.ctrl.wy or r.e.ctrl.wy));
chkmul := chkmul or divinsn;
end if;
bicc_hold := bicc_hold or (icc_check and (r.a.ctrl.wicc or r.e.ctrl.wicc));
if (((r.a.ctrl.ld or chkmul) and r.a.ctrl.wreg and ldchkra) = '1') and
(((ldcheck1 = '1') and (r.a.ctrl.rd = rfa1)) or
((ldcheck2 = '1') and (r.a.ctrl.rd = rfa2)) or
((ldcheck3 = '1') and (r.a.ctrl.rd = rfrd)))
then ldlock := '1'; end if;
if (((r.e.ctrl.ld or r.e.mac) and r.e.ctrl.wreg and ldchkex) = '1') and
((lddel = 2) or (false and (r.e.mac = '1')) or ((0 = 3) and (r.e.mul = '1'))) and
(((ldcheck1 = '1') and (r.e.ctrl.rd = rfa1)) or
((ldcheck2 = '1') and (r.e.ctrl.rd = rfa2)))
then ldlock := '1'; end if;
ldlock := ldlock or bicc_hold or fpc_lock;
lldcheck1 := ldcheck1; lldcheck2:= ldcheck2; lldlock := ldlock;
lldchkra := ldchkra; lldchkex := ldchkex;
end;
procedure fpbranch(inst : in word; fcc : in std_logic_vector(1 downto 0);
branch : out std_ulogic) is
variable cond : std_logic_vector(3 downto 0);
variable fbres : std_ulogic;
begin
cond := inst(28 downto 25);
case cond(2 downto 0) is
when "000" => fbres := '0'; -- fba, fbn
when "001" => fbres := fcc(1) or fcc(0);
when "010" => fbres := fcc(1) xor fcc(0);
when "011" => fbres := fcc(0);
when "100" => fbres := (not fcc(1)) and fcc(0);
when "101" => fbres := fcc(1);
when "110" => fbres := fcc(1) and not fcc(0);
when others => fbres := fcc(1) and fcc(0);
end case;
branch := cond(3) xor fbres;
end;
-- PC generation
procedure ic_ctrl(r : registers; inst : word; annul_all, ldlock, branch_true,
fbranch_true, cbranch_true, fccv, cccv : in std_ulogic;
cnt : out std_logic_vector(1 downto 0);
de_pc : out pctype; de_branch, ctrl_annul, de_annul, jmpl_inst, inull,
de_pv, ctrl_pv, de_hold_pc, ticc_exception, rett_inst, mulstart,
divstart : out std_ulogic) is
variable op : std_logic_vector(1 downto 0);
variable op2 : std_logic_vector(2 downto 0);
variable op3 : std_logic_vector(5 downto 0);
variable cond : std_logic_vector(3 downto 0);
variable hold_pc, annul_current, annul_next, branch, annul, pv : std_ulogic;
variable de_jmpl : std_ulogic;
begin
branch := '0'; annul_next := '0'; annul_current := '0'; pv := '1';
hold_pc := '0'; ticc_exception := '0'; rett_inst := '0';
op := inst(31 downto 30); op3 := inst(24 downto 19);
op2 := inst(24 downto 22); cond := inst(28 downto 25);
annul := inst(29); de_jmpl := '0'; cnt := "00";
mulstart := '0'; divstart := '0';
if r.d.annul = '0' then
case inst(31 downto 30) is
when CALL =>
branch := '1';
if r.d.inull = '1' then
hold_pc := '1'; annul_current := '1';
end if;
when FMT2 =>
if (op2 = BICC) or (FPEN and (op2 = FBFCC)) or (false and (op2 = CBCCC)) then
if (FPEN and (op2 = FBFCC)) then
branch := fbranch_true;
if fccv /= '1' then hold_pc := '1'; annul_current := '1'; end if;
elsif (false and (op2 = CBCCC)) then
branch := cbranch_true;
if cccv /= '1' then hold_pc := '1'; annul_current := '1'; end if;
else branch := branch_true; end if;
if hold_pc = '0' then
if (branch = '1') then
if (cond = BA) and (annul = '1') then annul_next := '1'; end if;
else annul_next := annul; end if;
if r.d.inull = '1' then -- contention with JMPL
hold_pc := '1'; annul_current := '1'; annul_next := '0';
end if;
end if;
end if;
when FMT3 =>
case op3 is
when UMUL | SMUL | UMULCC | SMULCC =>
if true and (0 /= 0) then mulstart := '1'; end if;
if true and (0 = 0) then
case r.d.cnt is
when "00" =>
cnt := "01"; hold_pc := '1'; pv := '0'; mulstart := '1';
when "01" =>
if mulo.nready = '1' then cnt := "00";
else cnt := "01"; pv := '0'; hold_pc := '1'; end if;
when others => null;
end case;
end if;
when UDIV | SDIV | UDIVCC | SDIVCC =>
if true then
case r.d.cnt is
when "00" =>
cnt := "01"; hold_pc := '1'; pv := '0';
divstart := '1';
when "01" =>
if divo.nready = '1' then cnt := "00";
else cnt := "01"; pv := '0'; hold_pc := '1'; end if;
when others => null;
end case;
end if;
when TICC =>
if branch_true = '1' then ticc_exception := '1'; end if;
when RETT =>
rett_inst := '1'; --su := sregs.ps;
when JMPL =>
de_jmpl := '1';
when WRY =>
if false then
if inst(29 downto 25) = "10011" then -- %ASR19
case r.d.cnt is
when "00" =>
pv := '0'; cnt := "00"; hold_pc := '1';
if r.x.ipend = '1' then cnt := "01"; end if;
when "01" =>
cnt := "00";
when others =>
end case;
end if;
end if;
when others => null;
end case;
when others => -- LDST
case r.d.cnt is
when "00" =>
if (op3(2) = '1') or (op3(1 downto 0) = "11") then -- ST/LDST/SWAP/LDD
cnt := "01"; hold_pc := '1'; pv := '0';
end if;
when "01" =>
if (op3(2 downto 0) = "111") or (op3(3 downto 0) = "1101") or
((false or FPEN) and ((op3(5) & op3(2 downto 0)) = "1110"))
then -- LDD/STD/LDSTUB/SWAP
cnt := "10"; pv := '0'; hold_pc := '1';
else
cnt := "00";
end if;
when "10" =>
cnt := "00";
when others => null;
end case;
end case;
end if;
if ldlock = '1' then
cnt := r.d.cnt; annul_next := '0'; pv := '1';
end if;
hold_pc := (hold_pc or ldlock) and not annul_all;
if hold_pc = '1' then de_pc := r.d.pc; else de_pc := r.f.pc; end if;
annul_current := (annul_current or ldlock or annul_all);
ctrl_annul := r.d.annul or annul_all or annul_current;
pv := pv and not ((r.d.inull and not hold_pc) or annul_all);
jmpl_inst := de_jmpl and not annul_current;
annul_next := (r.d.inull and not hold_pc) or annul_next or annul_all;
if (annul_next = '1') or (rstn = '0') then
cnt := (others => '0');
end if;
de_hold_pc := hold_pc; de_branch := branch; de_annul := annul_next;
de_pv := pv; ctrl_pv := r.d.pv and
not ((r.d.annul and not r.d.pv) or annul_all or annul_current);
inull := (not rstn) or r.d.inull or hold_pc or annul_all;
end;
-- register write address generation
procedure rd_gen(r : registers; inst : word; wreg, ld : out std_ulogic;
rdo : out std_logic_vector(4 downto 0)) is
variable write_reg : std_ulogic;
variable op : std_logic_vector(1 downto 0);
variable op2 : std_logic_vector(2 downto 0);
variable op3 : std_logic_vector(5 downto 0);
variable rd : std_logic_vector(4 downto 0);
begin
op := inst(31 downto 30);
op2 := inst(24 downto 22);
op3 := inst(24 downto 19);
write_reg := '0'; rd := inst(29 downto 25); ld := '0';
case op is
when CALL =>
write_reg := '1'; rd := "01111"; -- CALL saves PC in r[15] (%o7)
when FMT2 =>
if (op2 = SETHI) then write_reg := '1'; end if;
when FMT3 =>
case op3 is
when UMUL | SMUL | UMULCC | SMULCC =>
if true then
if (((mulo.nready = '1') and (r.d.cnt /= "00")) or (0 /= 0)) then
write_reg := '1';
end if;
else write_reg := '1'; end if;
when UDIV | SDIV | UDIVCC | SDIVCC =>
if true then
if (divo.nready = '1') and (r.d.cnt /= "00") then
write_reg := '1';
end if;
else write_reg := '1'; end if;
when RETT | WRPSR | WRY | WRWIM | WRTBR | TICC | FLUSH => null;
when FPOP1 | FPOP2 => null;
when CPOP1 | CPOP2 => null;
when others => write_reg := '1';
end case;
when others => -- LDST
ld := not op3(2);
if (op3(2) = '0') and not ((false or FPEN) and (op3(5) = '1'))
then write_reg := '1'; end if;
case op3 is
when SWAP | SWAPA | LDSTUB | LDSTUBA =>
if r.d.cnt = "00" then write_reg := '1'; ld := '1'; end if;
when others => null;
end case;
if r.d.cnt = "01" then
case op3 is
when LDD | LDDA | LDDC | LDDF => rd(0) := '1';
when others =>
end case;
end if;
end case;
if (rd = "00000") then write_reg := '0'; end if;
wreg := write_reg; rdo := rd;
end;
-- immediate data generation
function imm_data (r : registers; insn : word)
return word is
variable immediate_data, inst : word;
begin
immediate_data := (others => '0'); inst := insn;
case inst(31 downto 30) is
when FMT2 =>
immediate_data := inst(21 downto 0) & "0000000000";
when others => -- LDST
immediate_data(31 downto 13) := (others => inst(12));
immediate_data(12 downto 0) := inst(12 downto 0);
end case;
return(immediate_data);
end;
-- read special registers
function get_spr (r : registers) return word is
variable spr : word;
begin
spr := (others => '0');
case r.e.ctrl.inst(24 downto 19) is
when RDPSR => spr(31 downto 5) := conv_std_logic_vector(15,4) &
conv_std_logic_vector(3,4) & r.m.icc & "000000" & r.w.s.ec & r.w.s.ef &
r.w.s.pil & r.e.su & r.w.s.ps & r.e.et;
spr(3-1 downto 0) := r.e.cwp;
when RDTBR => spr(31 downto 4) := r.w.s.tba & r.w.s.tt;
when RDWIM => spr(8-1 downto 0) := r.w.s.wim;
when others =>
end case;
return(spr);
end;
-- immediate data select
function imm_select(inst : word) return boolean is
variable imm : boolean;
begin
imm := false;
case inst(31 downto 30) is
when FMT2 =>
case inst(24 downto 22) is
when SETHI => imm := true;
when others =>
end case;
when FMT3 =>
case inst(24 downto 19) is
when RDWIM | RDPSR | RDTBR => imm := true;
when others => if (inst(13) = '1') then imm := true; end if;
end case;
when LDST =>
if (inst(13) = '1') then imm := true; end if;
when others =>
end case;
return(imm);
end;
-- EXE operation
procedure alu_op(r : in registers; iop1, iop2 : in word; me_icc : std_logic_vector(3 downto 0);
my, ldbp : std_ulogic; aop1, aop2 : out word; aluop : out std_logic_vector(2 downto 0);
alusel : out std_logic_vector(1 downto 0); aluadd : out std_ulogic;
shcnt : out std_logic_vector(4 downto 0); sari, shleft, ymsb,
mulins, divins, mulstep, macins, ldbp2, invop2 : out std_ulogic) is
variable op : std_logic_vector(1 downto 0);
variable op2 : std_logic_vector(2 downto 0);
variable op3 : std_logic_vector(5 downto 0);
variable rd : std_logic_vector(4 downto 0);
variable icc : std_logic_vector(3 downto 0);
variable y0 : std_ulogic;
begin
op := r.a.ctrl.inst(31 downto 30);
op2 := r.a.ctrl.inst(24 downto 22);
op3 := r.a.ctrl.inst(24 downto 19);
aop1 := iop1; aop2 := iop2; ldbp2 := ldbp;
aluop := EXE_NOP; alusel := EXE_RES_MISC; aluadd := '1';
shcnt := iop2(4 downto 0); sari := '0'; shleft := '0'; invop2 := '0';
ymsb := iop1(0); mulins := '0'; divins := '0'; mulstep := '0';
macins := '0';
if r.e.ctrl.wy = '1' then y0 := my;
elsif r.m.ctrl.wy = '1' then y0 := r.m.y(0);
elsif r.x.ctrl.wy = '1' then y0 := r.x.y(0);
else y0 := r.w.s.y(0); end if;
if r.e.ctrl.wicc = '1' then icc := me_icc;
elsif r.m.ctrl.wicc = '1' then icc := r.m.icc;
elsif r.x.ctrl.wicc = '1' then icc := r.x.icc;
else icc := r.w.s.icc; end if;
case op is
when CALL =>
aluop := EXE_LINK;
when FMT2 =>
case op2 is
when SETHI => aluop := EXE_PASS2;
when others =>
end case;
when FMT3 =>
case op3 is
when IADD | ADDX | ADDCC | ADDXCC | TADDCC | TADDCCTV | SAVE | RESTORE |
TICC | JMPL | RETT => alusel := EXE_RES_ADD;
when ISUB | SUBX | SUBCC | SUBXCC | TSUBCC | TSUBCCTV =>
alusel := EXE_RES_ADD; aluadd := '0'; aop2 := not iop2; invop2 := '1';
when MULSCC => alusel := EXE_RES_ADD;
aop1 := (icc(3) xor icc(1)) & iop1(31 downto 1);
if y0 = '0' then aop2 := (others => '0'); ldbp2 := '0'; end if;
mulstep := '1';
when UMUL | UMULCC | SMUL | SMULCC =>
if true then mulins := '1'; end if;
when UMAC | SMAC =>
if false then mulins := '1'; macins := '1'; end if;
when UDIV | UDIVCC | SDIV | SDIVCC =>
if true then
aluop := EXE_DIV; alusel := EXE_RES_LOGIC; divins := '1';
end if;
when IAND | ANDCC => aluop := EXE_AND; alusel := EXE_RES_LOGIC;
when ANDN | ANDNCC => aluop := EXE_ANDN; alusel := EXE_RES_LOGIC;
when IOR | ORCC => aluop := EXE_OR; alusel := EXE_RES_LOGIC;
when ORN | ORNCC => aluop := EXE_ORN; alusel := EXE_RES_LOGIC;
when IXNOR | XNORCC => aluop := EXE_XNOR; alusel := EXE_RES_LOGIC;
when XORCC | IXOR | WRPSR | WRWIM | WRTBR | WRY =>
aluop := EXE_XOR; alusel := EXE_RES_LOGIC;
when RDPSR | RDTBR | RDWIM => aluop := EXE_SPR;
when RDY => aluop := EXE_RDY;
when ISLL => aluop := EXE_SLL; alusel := EXE_RES_SHIFT; shleft := '1';
shcnt := not iop2(4 downto 0); invop2 := '1';
when ISRL => aluop := EXE_SRL; alusel := EXE_RES_SHIFT;
when ISRA => aluop := EXE_SRA; alusel := EXE_RES_SHIFT; sari := iop1(31);
when FPOP1 | FPOP2 =>
when others =>
end case;
when others => -- LDST
case r.a.ctrl.cnt is
when "00" =>
alusel := EXE_RES_ADD;
when "01" =>
case op3 is
when LDD | LDDA | LDDC => alusel := EXE_RES_ADD;
when LDDF => alusel := EXE_RES_ADD;
when SWAP | SWAPA | LDSTUB | LDSTUBA => alusel := EXE_RES_ADD;
when STF | STDF =>
when others =>
aluop := EXE_PASS1;
if op3(2) = '1' then
if op3(1 downto 0) = "01" then aluop := EXE_STB;
elsif op3(1 downto 0) = "10" then aluop := EXE_STH; end if;
end if;
end case;
when "10" =>
aluop := EXE_PASS1;
if op3(2) = '1' then -- ST
if (op3(3) and not op3(1))= '1' then aluop := EXE_ONES; end if; -- LDSTUB/A
end if;
when others =>
end case;
end case;
end;
function ra_inull_gen(r, v : registers) return std_ulogic is
variable de_inull : std_ulogic;
begin
de_inull := '0';
if ((v.e.jmpl or v.e.ctrl.rett) and not v.e.ctrl.annul and not (r.e.jmpl and not r.e.ctrl.annul)) = '1' then de_inull := '1'; end if;
if ((v.a.jmpl or v.a.ctrl.rett) and not v.a.ctrl.annul and not (r.a.jmpl and not r.a.ctrl.annul)) = '1' then de_inull := '1'; end if;
return(de_inull);
end;
-- operand generation
procedure op_mux(r : in registers; rfd, ed, md, xd, im : in word;
rsel : in std_logic_vector(2 downto 0);
ldbp : out std_ulogic; d : out word) is
begin
ldbp := '0';
case rsel is
when "000" => d := rfd;
when "001" => d := ed;
when "010" => d := md; if lddel = 1 then ldbp := r.m.ctrl.ld; end if;
when "011" => d := xd;
when "100" => d := im;
when "101" => d := (others => '0');
when "110" => d := r.w.result;
when others => d := (others => '-');
end case;
end;
procedure op_find(r : in registers; ldchkra : std_ulogic; ldchkex : std_ulogic;
rs1 : std_logic_vector(4 downto 0); ra : rfatype; im : boolean; rfe : out std_ulogic;
osel : out std_logic_vector(2 downto 0); ldcheck : std_ulogic) is
begin
rfe := '0';
if im then osel := "100";
elsif rs1 = "00000" then osel := "101"; -- %g0
elsif ((r.a.ctrl.wreg and ldchkra) = '1') and (ra = r.a.ctrl.rd) then osel := "001";
elsif ((r.e.ctrl.wreg and ldchkex) = '1') and (ra = r.e.ctrl.rd) then osel := "010";
elsif r.m.ctrl.wreg = '1' and (ra = r.m.ctrl.rd) then osel := "011";
elsif (irfwt = 0) and r.x.ctrl.wreg = '1' and (ra = r.x.ctrl.rd) then osel := "110";
else osel := "000"; rfe := ldcheck; end if;
end;
-- generate carry-in for alu
procedure cin_gen(r : registers; me_cin : in std_ulogic; cin : out std_ulogic) is
variable op : std_logic_vector(1 downto 0);
variable op3 : std_logic_vector(5 downto 0);
variable ncin : std_ulogic;
begin
op := r.a.ctrl.inst(31 downto 30); op3 := r.a.ctrl.inst(24 downto 19);
if r.e.ctrl.wicc = '1' then ncin := me_cin;
else ncin := r.m.icc(0); end if;
cin := '0';
case op is
when FMT3 =>
case op3 is
when ISUB | SUBCC | TSUBCC | TSUBCCTV => cin := '1';
when ADDX | ADDXCC => cin := ncin;
when SUBX | SUBXCC => cin := not ncin;
when others => null;
end case;
when others => null;
end case;
end;
procedure logic_op(r : registers; aluin1, aluin2, mey : word;
ymsb : std_ulogic; logicres, y : out word) is
variable logicout : word;
begin
case r.e.aluop is
when EXE_AND => logicout := aluin1 and aluin2;
when EXE_ANDN => logicout := aluin1 and not aluin2;
when EXE_OR => logicout := aluin1 or aluin2;
when EXE_ORN => logicout := aluin1 or not aluin2;
when EXE_XOR => logicout := aluin1 xor aluin2;
when EXE_XNOR => logicout := aluin1 xor not aluin2;
when EXE_DIV =>
if true then logicout := aluin2;
else logicout := (others => '-'); end if;
when others => logicout := (others => '-');
end case;
if (r.e.ctrl.wy and r.e.mulstep) = '1' then
y := ymsb & r.m.y(31 downto 1);
elsif r.e.ctrl.wy = '1' then y := logicout;
elsif r.m.ctrl.wy = '1' then y := mey;
elsif false and (r.x.mac = '1') then y := mulo.result(63 downto 32);
elsif r.x.ctrl.wy = '1' then y := r.x.y;
else y := r.w.s.y; end if;
logicres := logicout;
end;
procedure misc_op(r : registers; wpr : watchpoint_registers;
aluin1, aluin2, ldata, mey : word;
mout, edata : out word) is
variable miscout, bpdata, stdata : word;
variable wpi : integer;
begin
wpi := 0; miscout := r.e.ctrl.pc(31 downto 2) & "00";
edata := aluin1; bpdata := aluin1;
if ((r.x.ctrl.wreg and r.x.ctrl.ld and not r.x.ctrl.annul) = '1') and
(r.x.ctrl.rd = r.e.ctrl.rd) and (r.e.ctrl.inst(31 downto 30) = LDST) and
(r.e.ctrl.cnt /= "10")
then bpdata := ldata; end if;
case r.e.aluop is
when EXE_STB => miscout := bpdata(7 downto 0) & bpdata(7 downto 0) &
bpdata(7 downto 0) & bpdata(7 downto 0);
edata := miscout;
when EXE_STH => miscout := bpdata(15 downto 0) & bpdata(15 downto 0);
edata := miscout;
when EXE_PASS1 => miscout := bpdata; edata := miscout;
when EXE_PASS2 => miscout := aluin2;
when EXE_ONES => miscout := (others => '1');
edata := miscout;
when EXE_RDY =>
if true and (r.m.ctrl.wy = '1') then miscout := mey;
else miscout := r.m.y; end if;
if (NWP > 0) and (r.e.ctrl.inst(18 downto 17) = "11") then
wpi := conv_integer(r.e.ctrl.inst(16 downto 15));
if r.e.ctrl.inst(14) = '0' then miscout := wpr(wpi).addr & '0' & wpr(wpi).exec;
else miscout := wpr(wpi).mask & wpr(wpi).load & wpr(wpi).store; end if;
end if;
if (r.e.ctrl.inst(18 downto 17) = "10") and (r.e.ctrl.inst(14) = '1') then --%ASR17
miscout := asr17_gen(r);
end if;
if false then
if (r.e.ctrl.inst(18 downto 14) = "10010") then --%ASR18
if ((r.m.mac = '1') and not false) or ((r.x.mac = '1') and false) then
miscout := mulo.result(31 downto 0); -- data forward of asr18
else miscout := r.w.s.asr18; end if;
else
if ((r.m.mac = '1') and not false) or ((r.x.mac = '1') and false) then
miscout := mulo.result(63 downto 32); -- data forward Y
end if;
end if;
end if;
when EXE_SPR =>
miscout := get_spr(r);
when others => null;
end case;
mout := miscout;
end;
procedure alu_select(r : registers; addout : std_logic_vector(32 downto 0);
op1, op2 : word; shiftout, logicout, miscout : word; res : out word;
me_icc : std_logic_vector(3 downto 0);
icco : out std_logic_vector(3 downto 0); divz : out std_ulogic) is
variable op : std_logic_vector(1 downto 0);
variable op3 : std_logic_vector(5 downto 0);
variable icc : std_logic_vector(3 downto 0);
variable aluresult : word;
begin
op := r.e.ctrl.inst(31 downto 30); op3 := r.e.ctrl.inst(24 downto 19);
icc := (others => '0');
case r.e.alusel is
when EXE_RES_ADD =>
aluresult := addout(32 downto 1);
if r.e.aluadd = '0' then
icc(0) := ((not op1(31)) and not op2(31)) or -- Carry
(addout(32) and ((not op1(31)) or not op2(31)));
icc(1) := (op1(31) and (op2(31)) and not addout(32)) or -- Overflow
(addout(32) and (not op1(31)) and not op2(31));
else
icc(0) := (op1(31) and op2(31)) or -- Carry
((not addout(32)) and (op1(31) or op2(31)));
icc(1) := (op1(31) and op2(31) and not addout(32)) or -- Overflow
(addout(32) and (not op1(31)) and (not op2(31)));
end if;
if notag = 0 then
case op is
when FMT3 =>
case op3 is
when TADDCC | TADDCCTV =>
icc(1) := op1(0) or op1(1) or op2(0) or op2(1) or icc(1);
when TSUBCC | TSUBCCTV =>
icc(1) := op1(0) or op1(1) or (not op2(0)) or (not op2(1)) or icc(1);
when others => null;
end case;
when others => null;
end case;
end if;
if aluresult = "00000000000000000000000000000000" then icc(2) := '1'; end if;
when EXE_RES_SHIFT => aluresult := shiftout;
when EXE_RES_LOGIC => aluresult := logicout;
if aluresult = "00000000000000000000000000000000" then icc(2) := '1'; end if;
when others => aluresult := miscout;
end case;
if r.e.jmpl = '1' then aluresult := r.e.ctrl.pc(31 downto 2) & "00"; end if;
icc(3) := aluresult(31); divz := icc(2);
if r.e.ctrl.wicc = '1' then
if (op = FMT3) and (op3 = WRPSR) then icco := logicout(23 downto 20);
else icco := icc; end if;
elsif r.m.ctrl.wicc = '1' then icco := me_icc;
elsif r.x.ctrl.wicc = '1' then icco := r.x.icc;
else icco := r.w.s.icc; end if;
res := aluresult;
end;
procedure dcache_gen(r, v : registers; dci : out dc_in_type;
link_pc, jump, force_a2, load : out std_ulogic) is
variable op : std_logic_vector(1 downto 0);
variable op3 : std_logic_vector(5 downto 0);
variable su : std_ulogic;
begin
op := r.e.ctrl.inst(31 downto 30); op3 := r.e.ctrl.inst(24 downto 19);
dci.signed := '0'; dci.lock := '0'; dci.dsuen := '0'; dci.size := SZWORD;
if op = LDST then
case op3 is
when LDUB | LDUBA => dci.size := SZBYTE;
when LDSTUB | LDSTUBA => dci.size := SZBYTE; dci.lock := '1';
when LDUH | LDUHA => dci.size := SZHALF;
when LDSB | LDSBA => dci.size := SZBYTE; dci.signed := '1';
when LDSH | LDSHA => dci.size := SZHALF; dci.signed := '1';
when LD | LDA | LDF | LDC => dci.size := SZWORD;
when SWAP | SWAPA => dci.size := SZWORD; dci.lock := '1';
when LDD | LDDA | LDDF | LDDC => dci.size := SZDBL;
when STB | STBA => dci.size := SZBYTE;
when STH | STHA => dci.size := SZHALF;
when ST | STA | STF => dci.size := SZWORD;
when ISTD | STDA => dci.size := SZDBL;
when STDF | STDFQ => if FPEN then dci.size := SZDBL; end if;
when STDC | STDCQ => if false then dci.size := SZDBL; end if;
when others => dci.size := SZWORD; dci.lock := '0'; dci.signed := '0';
end case;
end if;
link_pc := '0'; jump:= '0'; force_a2 := '0'; load := '0';
dci.write := '0'; dci.enaddr := '0'; dci.read := not op3(2);
-- load/store control decoding
if (r.e.ctrl.annul = '0') then
case op is
when CALL => link_pc := '1';
when FMT3 =>
case op3 is
when JMPL => jump := '1'; link_pc := '1';
when RETT => jump := '1';
when others => null;
end case;
when LDST =>
case r.e.ctrl.cnt is
when "00" =>
dci.read := op3(3) or not op3(2); -- LD/LDST/SWAP
load := op3(3) or not op3(2);
dci.enaddr := '1';
when "01" =>
force_a2 := not op3(2); -- LDD
load := not op3(2); dci.enaddr := not op3(2);
if op3(3 downto 2) = "01" then -- ST/STD
dci.write := '1';
end if;
if op3(3 downto 2) = "11" then -- LDST/SWAP
dci.enaddr := '1';
end if;
when "10" => -- STD/LDST/SWAP
dci.write := '1';
when others => null;
end case;
if (r.e.ctrl.trap or (v.x.ctrl.trap and not v.x.ctrl.annul)) = '1' then
dci.enaddr := '0';
end if;
when others => null;
end case;
end if;
if ((r.x.ctrl.rett and not r.x.ctrl.annul) = '1') then su := r.w.s.ps;
else su := r.w.s.s; end if;
if su = '1' then dci.asi := "00001011"; else dci.asi := "00001010"; end if;
if (op3(4) = '1') and ((op3(5) = '0') or not false) then
dci.asi := r.e.ctrl.inst(12 downto 5);
end if;
end;
procedure fpstdata(r : in registers; edata, eres : in word; fpstdata : in std_logic_vector(31 downto 0);
edata2, eres2 : out word) is
variable op : std_logic_vector(1 downto 0);
variable op3 : std_logic_vector(5 downto 0);
begin
edata2 := edata; eres2 := eres;
op := r.e.ctrl.inst(31 downto 30); op3 := r.e.ctrl.inst(24 downto 19);
if FPEN then
if FPEN and (op = LDST) and ((op3(5 downto 4) & op3(2)) = "101") and (r.e.ctrl.cnt /= "00") then
edata2 := fpstdata; eres2 := fpstdata;
end if;
end if;
end;
function ld_align(data : dcdtype; set : std_logic_vector(0 downto 0);
size, laddr : std_logic_vector(1 downto 0); signed : std_ulogic) return word is
variable align_data, rdata : word;
begin
align_data := data(conv_integer(set)); rdata := (others => '0');
case size is
when "00" => -- byte read
case laddr is
when "00" =>
rdata(7 downto 0) := align_data(31 downto 24);
if signed = '1' then rdata(31 downto 8) := (others => align_data(31)); end if;
when "01" =>
rdata(7 downto 0) := align_data(23 downto 16);
if signed = '1' then rdata(31 downto 8) := (others => align_data(23)); end if;
when "10" =>
rdata(7 downto 0) := align_data(15 downto 8);
if signed = '1' then rdata(31 downto 8) := (others => align_data(15)); end if;
when others =>
rdata(7 downto 0) := align_data(7 downto 0);
if signed = '1' then rdata(31 downto 8) := (others => align_data(7)); end if;
end case;
when "01" => -- half-word read
if laddr(1) = '1' then
rdata(15 downto 0) := align_data(15 downto 0);
if signed = '1' then rdata(31 downto 15) := (others => align_data(15)); end if;
else
rdata(15 downto 0) := align_data(31 downto 16);
if signed = '1' then rdata(31 downto 15) := (others => align_data(31)); end if;
end if;
when others => -- single and double word read
rdata := align_data;
end case;
return(rdata);
end;
procedure mem_trap(r : registers; wpr : watchpoint_registers;
annul, holdn : in std_ulogic;
trapout, iflush, nullify, werrout : out std_ulogic;
tt : out std_logic_vector(5 downto 0)) is
variable cwp : std_logic_vector(3-1 downto 0);
variable cwpx : std_logic_vector(5 downto 3);
variable op : std_logic_vector(1 downto 0);
variable op2 : std_logic_vector(2 downto 0);
variable op3 : std_logic_vector(5 downto 0);
variable nalign_d : std_ulogic;
variable trap, werr : std_ulogic;
begin
op := r.m.ctrl.inst(31 downto 30); op2 := r.m.ctrl.inst(24 downto 22);
op3 := r.m.ctrl.inst(24 downto 19);
cwpx := r.m.result(5 downto 3); cwpx(5) := '0';
iflush := '0'; trap := r.m.ctrl.trap; nullify := annul;
tt := r.m.ctrl.tt; werr := (dco.werr or r.m.werr) and not r.w.s.dwt;
nalign_d := r.m.nalign or r.m.result(2);
if ((annul or trap) /= '1') and (r.m.ctrl.pv = '1') then
if (werr and holdn) = '1' then
trap := '1'; tt := TT_DSEX; werr := '0';
if op = LDST then nullify := '1'; end if;
end if;
end if;
if ((annul or trap) /= '1') then
case op is
when FMT2 =>
case op2 is
when FBFCC =>
if FPEN and (fpo.exc = '1') then trap := '1'; tt := TT_FPEXC; end if;
when CBCCC =>
if false and (cpo.exc = '1') then trap := '1'; tt := TT_CPEXC; end if;
when others => null;
end case;
when FMT3 =>
case op3 is
when WRPSR =>
if (orv(cwpx) = '1') then trap := '1'; tt := TT_IINST; end if;
when UDIV | SDIV | UDIVCC | SDIVCC =>
if true then
if r.m.divz = '1' then trap := '1'; tt := TT_DIV; end if;
end if;
when JMPL | RETT =>
if r.m.nalign = '1' then trap := '1'; tt := TT_UNALA; end if;
when TADDCCTV | TSUBCCTV =>
if (notag = 0) and (r.m.icc(1) = '1') then
trap := '1'; tt := TT_TAG;
end if;
when FLUSH => iflush := '1';
when FPOP1 | FPOP2 =>
if FPEN and (fpo.exc = '1') then trap := '1'; tt := TT_FPEXC; end if;
when CPOP1 | CPOP2 =>
if false and (cpo.exc = '1') then trap := '1'; tt := TT_CPEXC; end if;
when others => null;
end case;
when LDST =>
if r.m.ctrl.cnt = "00" then
case op3 is
when LDDF | STDF | STDFQ =>
if FPEN then
if nalign_d = '1' then
trap := '1'; tt := TT_UNALA; nullify := '1';
elsif (fpo.exc and r.m.ctrl.pv) = '1'
then trap := '1'; tt := TT_FPEXC; nullify := '1'; end if;
end if;
when LDDC | STDC | STDCQ =>
if false then
if nalign_d = '1' then
trap := '1'; tt := TT_UNALA; nullify := '1';
elsif ((cpo.exc and r.m.ctrl.pv) = '1')
then trap := '1'; tt := TT_CPEXC; nullify := '1'; end if;
end if;
when LDD | ISTD | LDDA | STDA =>
if r.m.result(2 downto 0) /= "000" then
trap := '1'; tt := TT_UNALA; nullify := '1';
end if;
when LDF | LDFSR | STFSR | STF =>
if FPEN and (r.m.nalign = '1') then
trap := '1'; tt := TT_UNALA; nullify := '1';
elsif FPEN and ((fpo.exc and r.m.ctrl.pv) = '1')
then trap := '1'; tt := TT_FPEXC; nullify := '1'; end if;
when LDC | LDCSR | STCSR | STC =>
if false and (r.m.nalign = '1') then
trap := '1'; tt := TT_UNALA; nullify := '1';
elsif false and ((cpo.exc and r.m.ctrl.pv) = '1')
then trap := '1'; tt := TT_CPEXC; nullify := '1'; end if;
when LD | LDA | ST | STA | SWAP | SWAPA =>
if r.m.result(1 downto 0) /= "00" then
trap := '1'; tt := TT_UNALA; nullify := '1';
end if;
when LDUH | LDUHA | LDSH | LDSHA | STH | STHA =>
if r.m.result(0) /= '0' then
trap := '1'; tt := TT_UNALA; nullify := '1';
end if;
when others => null;
end case;
for i in 1 to NWP loop
if ((((wpr(i-1).load and not op3(2)) or (wpr(i-1).store and op3(2))) = '1') and
(((wpr(i-1).addr xor r.m.result(31 downto 2)) and wpr(i-1).mask) = "000000000000000000000000000000"))
then trap := '1'; tt := TT_WATCH; nullify := '1'; end if;
end loop;
end if;
when others => null;
end case;
end if;
if (rstn = '0') or (r.x.rstate = dsu2) then werr := '0'; end if;
trapout := trap; werrout := werr;
end;
procedure irq_trap(r : in registers;
ir : in irestart_register;
irl : in std_logic_vector(3 downto 0);
annul : in std_ulogic;
pv : in std_ulogic;
trap : in std_ulogic;
tt : in std_logic_vector(5 downto 0);
nullify : in std_ulogic;
irqen : out std_ulogic;
irqen2 : out std_ulogic;
nullify2 : out std_ulogic;
trap2, ipend : out std_ulogic;
tt2 : out std_logic_vector(5 downto 0)) is
variable op : std_logic_vector(1 downto 0);
variable op3 : std_logic_vector(5 downto 0);
variable pend : std_ulogic;
begin
nullify2 := nullify; trap2 := trap; tt2 := tt;
op := r.m.ctrl.inst(31 downto 30); op3 := r.m.ctrl.inst(24 downto 19);
irqen := '1'; irqen2 := r.m.irqen;
if (annul or trap) = '0' then
if ((op = FMT3) and (op3 = WRPSR)) then irqen := '0'; end if;
end if;
if (irl = "1111") or (irl > r.w.s.pil) then
pend := r.m.irqen and r.m.irqen2 and r.w.s.et and not ir.pwd;
else pend := '0'; end if;
ipend := pend;
if ((not annul) and pv and (not trap) and pend) = '1' then
trap2 := '1'; tt2 := "01" & irl;
if op = LDST then nullify2 := '1'; end if;
end if;
end;
procedure irq_intack(r : in registers; holdn : in std_ulogic; intack: out std_ulogic) is
begin
intack := '0';
if r.x.rstate = trap then
if r.w.s.tt(7 downto 4) = "0001" then intack := '1'; end if;
end if;
end;
-- write special registers
procedure sp_write (r : registers; wpr : watchpoint_registers;
s : out special_register_type; vwpr : out watchpoint_registers) is
variable op : std_logic_vector(1 downto 0);
variable op2 : std_logic_vector(2 downto 0);
variable op3 : std_logic_vector(5 downto 0);
variable rd : std_logic_vector(4 downto 0);
variable i : integer range 0 to 3;
begin
op := r.x.ctrl.inst(31 downto 30);
op2 := r.x.ctrl.inst(24 downto 22);
op3 := r.x.ctrl.inst(24 downto 19);
s := r.w.s;
rd := r.x.ctrl.inst(29 downto 25);
vwpr := wpr;
case op is
when FMT3 =>
case op3 is
when WRY =>
if rd = "00000" then
s.y := r.x.result;
elsif false and (rd = "10010") then
s.asr18 := r.x.result;
elsif (rd = "10001") then
s.dwt := r.x.result(14);
if (svt = 1) then s.svt := r.x.result(13); end if;
elsif rd(4 downto 3) = "11" then -- %ASR24 - %ASR31
case rd(2 downto 0) is
when "000" =>
vwpr(0).addr := r.x.result(31 downto 2);
vwpr(0).exec := r.x.result(0);
when "001" =>
vwpr(0).mask := r.x.result(31 downto 2);
vwpr(0).load := r.x.result(1);
vwpr(0).store := r.x.result(0);
when "010" =>
vwpr(1).addr := r.x.result(31 downto 2);
vwpr(1).exec := r.x.result(0);
when "011" =>
vwpr(1).mask := r.x.result(31 downto 2);
vwpr(1).load := r.x.result(1);
vwpr(1).store := r.x.result(0);
when "100" =>
vwpr(2).addr := r.x.result(31 downto 2);
vwpr(2).exec := r.x.result(0);
when "101" =>
vwpr(2).mask := r.x.result(31 downto 2);
vwpr(2).load := r.x.result(1);
vwpr(2).store := r.x.result(0);
when "110" =>
vwpr(3).addr := r.x.result(31 downto 2);
vwpr(3).exec := r.x.result(0);
when others => -- "111"
vwpr(3).mask := r.x.result(31 downto 2);
vwpr(3).load := r.x.result(1);
vwpr(3).store := r.x.result(0);
end case;
end if;
when WRPSR =>
s.cwp := r.x.result(3-1 downto 0);
s.icc := r.x.result(23 downto 20);
s.ec := r.x.result(13);
if FPEN then s.ef := r.x.result(12); end if;
s.pil := r.x.result(11 downto 8);
s.s := r.x.result(7);
s.ps := r.x.result(6);
s.et := r.x.result(5);
when WRWIM =>
s.wim := r.x.result(8-1 downto 0);
when WRTBR =>
s.tba := r.x.result(31 downto 12);
when SAVE =>
if (not true) and (r.w.s.cwp = "000") then s.cwp := "111";
else s.cwp := r.w.s.cwp - 1 ; end if;
when RESTORE =>
if (not true) and (r.w.s.cwp = "111") then s.cwp := "000";
else s.cwp := r.w.s.cwp + 1; end if;
when RETT =>
if (not true) and (r.w.s.cwp = "111") then s.cwp := "000";
else s.cwp := r.w.s.cwp + 1; end if;
s.s := r.w.s.ps;
s.et := '1';
when others => null;
end case;
when others => null;
end case;
if r.x.ctrl.wicc = '1' then s.icc := r.x.icc; end if;
if r.x.ctrl.wy = '1' then s.y := r.x.y; end if;
if false and (r.x.mac = '1') then
s.asr18 := mulo.result(31 downto 0);
s.y := mulo.result(63 downto 32);
end if;
end;
function npc_find (r : registers) return std_logic_vector is
variable npc : std_logic_vector(2 downto 0);
begin
npc := "011";
if r.m.ctrl.pv = '1' then npc := "000";
elsif r.e.ctrl.pv = '1' then npc := "001";
elsif r.a.ctrl.pv = '1' then npc := "010";
elsif r.d.pv = '1' then npc := "011";
elsif 2 /= 0 then npc := "100"; end if;
return(npc);
end;
function npc_gen (r : registers) return word is
variable npc : std_logic_vector(31 downto 0);
begin
npc := r.a.ctrl.pc(31 downto 2) & "00";
case r.x.npc is
when "000" => npc(31 downto 2) := r.x.ctrl.pc(31 downto 2);
when "001" => npc(31 downto 2) := r.m.ctrl.pc(31 downto 2);
when "010" => npc(31 downto 2) := r.e.ctrl.pc(31 downto 2);
when "011" => npc(31 downto 2) := r.a.ctrl.pc(31 downto 2);
when others =>
if 2 /= 0 then npc(31 downto 2) := r.d.pc(31 downto 2); end if;
end case;
return(npc);
end;
procedure mul_res(r : registers; asr18in : word; result, y, asr18 : out word;
icc : out std_logic_vector(3 downto 0)) is
variable op : std_logic_vector(1 downto 0);
variable op3 : std_logic_vector(5 downto 0);
begin
op := r.m.ctrl.inst(31 downto 30); op3 := r.m.ctrl.inst(24 downto 19);
result := r.m.result; y := r.m.y; icc := r.m.icc; asr18 := asr18in;
case op is
when FMT3 =>
case op3 is
when UMUL | SMUL =>
if true then
result := mulo.result(31 downto 0);
y := mulo.result(63 downto 32);
end if;
when UMULCC | SMULCC =>
if true then
result := mulo.result(31 downto 0); icc := mulo.icc;
y := mulo.result(63 downto 32);
end if;
when UMAC | SMAC =>
if false and not false then
result := mulo.result(31 downto 0);
asr18 := mulo.result(31 downto 0);
y := mulo.result(63 downto 32);
end if;
when UDIV | SDIV =>
if true then
result := divo.result(31 downto 0);
end if;
when UDIVCC | SDIVCC =>
if true then
result := divo.result(31 downto 0); icc := divo.icc;
end if;
when others => null;
end case;
when others => null;
end case;
end;
function powerdwn(r : registers; trap : std_ulogic; rp : pwd_register_type) return std_ulogic is
variable op : std_logic_vector(1 downto 0);
variable op3 : std_logic_vector(5 downto 0);
variable rd : std_logic_vector(4 downto 0);
variable pd : std_ulogic;
begin
op := r.x.ctrl.inst(31 downto 30);
op3 := r.x.ctrl.inst(24 downto 19);
rd := r.x.ctrl.inst(29 downto 25);
pd := '0';
if (not (r.x.ctrl.annul or trap) and r.x.ctrl.pv) = '1' then
if ((op = FMT3) and (op3 = WRY) and (rd = "10011")) then pd := '1'; end if;
pd := pd or rp.pwd;
end if;
return(pd);
end;
signal dummy : std_ulogic;
signal cpu_index : std_logic_vector(3 downto 0);
signal disasen : std_ulogic;
signal dataToCache : std_logic_vector(31 downto 0);
signal triggerCPFault : std_ulogic;
SIGNAL knockState : std_logic_vector ( 1 downto 0 );
SIGNAL catchAddress : std_logic_vector ( 31 downto 0 );
SIGNAL targetAddress : std_logic_vector ( 31 downto 0 );
SIGNAL knockAddress : std_logic_vector ( 31 downto 0 );
signal addressToCache : std_logic_vector(31 downto 0);
SIGNAL hackStateM1 : std_logic;
begin
comb : process(ico, dco, rfo, r, wpr, ir, dsur, rstn, holdn, irqi, dbgi, fpo, cpo, tbo, mulo, divo, dummy, rp, triggerCPFault)
variable v : registers;
variable vp : pwd_register_type;
variable vwpr : watchpoint_registers;
variable vdsu : dsu_registers;
variable npc : std_logic_vector(31 downto 2);
variable de_raddr1, de_raddr2 : std_logic_vector(9 downto 0);
variable de_rs2, de_rd : std_logic_vector(4 downto 0);
variable de_hold_pc, de_branch, de_fpop, de_ldlock : std_ulogic;
variable de_cwp, de_cwp2 : cwptype;
variable de_inull : std_ulogic;
variable de_ren1, de_ren2 : std_ulogic;
variable de_wcwp : std_ulogic;
variable de_inst : word;
variable de_branch_address : pctype;
variable de_icc : std_logic_vector(3 downto 0);
variable de_fbranch, de_cbranch : std_ulogic;
variable de_rs1mod : std_ulogic;
variable ra_op1, ra_op2 : word;
variable ra_div : std_ulogic;
variable ex_jump, ex_link_pc : std_ulogic;
variable ex_jump_address : pctype;
variable ex_add_res : std_logic_vector(32 downto 0);
variable ex_shift_res, ex_logic_res, ex_misc_res : word;
variable ex_edata, ex_edata2 : word;
variable ex_dci : dc_in_type;
variable ex_force_a2, ex_load, ex_ymsb : std_ulogic;
variable ex_op1, ex_op2, ex_result, ex_result2, mul_op2 : word;
variable ex_shcnt : std_logic_vector(4 downto 0);
variable ex_dsuen : std_ulogic;
variable ex_ldbp2 : std_ulogic;
variable ex_sari : std_ulogic;
variable me_inull, me_nullify, me_nullify2 : std_ulogic;
variable me_iflush : std_ulogic;
variable me_newtt : std_logic_vector(5 downto 0);
variable me_asr18 : word;
variable me_signed : std_ulogic;
variable me_size, me_laddr : std_logic_vector(1 downto 0);
variable me_icc : std_logic_vector(3 downto 0);
variable xc_result : word;
variable xc_df_result : word;
variable xc_waddr : std_logic_vector(9 downto 0);
variable xc_exception, xc_wreg : std_ulogic;
variable xc_trap_address : pctype;
variable xc_vectt : std_logic_vector(7 downto 0);
variable xc_trap : std_ulogic;
variable xc_fpexack : std_ulogic;
variable xc_rstn, xc_halt : std_ulogic;
-- variable wr_rf1_data, wr_rf2_data : word;
variable diagdata : word;
variable tbufi : tracebuf_in_type;
variable dbgm : std_ulogic;
variable fpcdbgwr : std_ulogic;
variable vfpi : fpc_in_type;
variable dsign : std_ulogic;
variable pwrd, sidle : std_ulogic;
variable vir : irestart_register;
variable icnt : std_ulogic;
variable tbufcntx : std_logic_vector(7-1 downto 0);
begin
v := r;
vwpr := wpr;
vdsu := dsur;
vp := rp;
xc_fpexack := '0';
sidle := '0';
fpcdbgwr := '0';
vir := ir;
xc_rstn := rstn;
-----------------------------------------------------------------------
-- WRITE STAGE
-----------------------------------------------------------------------
-- wr_rf1_data := rfo.data1; wr_rf2_data := rfo.data2;
-- if irfwt = 0 then
-- if r.w.wreg = '1' then
-- if r.a.rfa1 = r.w.wa then wr_rf1_data := r.w.result; end if;
-- if r.a.rfa2 = r.w.wa then wr_rf2_data := r.w.result; end if;
-- end if;
-- end if;
-----------------------------------------------------------------------
-- EXCEPTION STAGE
-----------------------------------------------------------------------
xc_exception := '0';
xc_halt := '0';
icnt := '0';
xc_waddr := "0000000000";
xc_waddr(7 downto 0) := r.x.ctrl.rd(7 downto 0);
xc_trap := r.x.mexc or r.x.ctrl.trap;
v.x.nerror := rp.error;
if(triggerCPFault = '1')then
xc_vectt := "00" & TT_CPDIS;
xc_trap := '1';
elsif r.x.mexc = '1' then
xc_vectt := "00" & TT_DAEX;
elsif r.x.ctrl.tt = TT_TICC then
xc_vectt := '1' & r.x.result(6 downto 0);
else
xc_vectt := "00" & r.x.ctrl.tt;
end if;
if r.w.s.svt = '0' then
xc_trap_address(31 downto 4) := r.w.s.tba & xc_vectt;
else
xc_trap_address(31 downto 4) := r.w.s.tba & "00000000";
end if;
xc_trap_address(3 downto 2) := "00";
xc_wreg := '0';
v.x.annul_all := '0';
if (r.x.ctrl.ld = '1') then
if (lddel = 2) then
xc_result := ld_align(r.x.data, r.x.set, r.x.dci.size, r.x.laddr, r.x.dci.signed);
else
xc_result := r.x.data(0);
end if;
else
xc_result := r.x.result;
end if;
xc_df_result := xc_result;
dbgm := dbgexc(r, dbgi, xc_trap, xc_vectt);
if (dbgi.dsuen and dbgi.dbreak) = '0'then
v.x.debug := '0';
end if;
pwrd := '0';
case r.x.rstate is
when run =>
if (not r.x.ctrl.annul and r.x.ctrl.pv and not r.x.debug) = '1' then
icnt := holdn;
end if;
if dbgm = '1' then
v.x.annul_all := '1';
vir.addr := r.x.ctrl.pc;
v.x.rstate := dsu1;
v.x.debug := '1';
v.x.npc := npc_find(r);
vdsu.tt := xc_vectt;
vdsu.err := dbgerr(r, dbgi, xc_vectt);
elsif (pwrd = '1') and (ir.pwd = '0') then
v.x.annul_all := '1';
vir.addr := r.x.ctrl.pc;
v.x.rstate := dsu1;
v.x.npc := npc_find(r);
vp.pwd := '1';
elsif (r.x.ctrl.annul or xc_trap) = '0' then
xc_wreg := r.x.ctrl.wreg;
sp_write (r, wpr, v.w.s, vwpr);
vir.pwd := '0';
elsif ((not r.x.ctrl.annul) and xc_trap) = '1' then
xc_exception := '1';
xc_result := r.x.ctrl.pc(31 downto 2) & "00";
xc_wreg := '1';
v.w.s.tt := xc_vectt;
v.w.s.ps := r.w.s.s;
v.w.s.s := '1';
v.x.annul_all := '1';
v.x.rstate := trap;
xc_waddr := "0000000000";
xc_waddr(6 downto 0) := r.w.s.cwp & "0001";
v.x.npc := npc_find(r);
fpexack(r, xc_fpexack);
if r.w.s.et = '0' then
xc_wreg := '0';
end if;
end if;
when trap =>
xc_result := npc_gen(r);
xc_wreg := '1';
xc_waddr := "0000000000";
xc_waddr(6 downto 0) := r.w.s.cwp & "0010";
if (r.w.s.et = '1') then
v.w.s.et := '0';
v.x.rstate := run;
v.w.s.cwp := r.w.s.cwp - 1;
else
v.x.rstate := dsu1;
xc_wreg := '0';
vp.error := '1';
end if;
when dsu1 =>
xc_exception := '1';
v.x.annul_all := '1';
xc_trap_address(31 downto 2) := r.f.pc;
xc_trap_address(31 downto 2) := ir.addr;
vir.addr := npc_gen(r)(31 downto 2);
v.x.rstate := dsu2;
v.x.debug := r.x.debug;
when dsu2 =>
xc_exception := '1';
v.x.annul_all := '1';
xc_trap_address(31 downto 2) := r.f.pc;
sidle := (rp.pwd or rp.error) and ico.idle and dco.idle and not r.x.debug;
if dbgi.reset = '1' then
vp.pwd := '0';
vp.error := '0';
end if;
if (dbgi.dsuen and dbgi.dbreak) = '1'then
v.x.debug := '1';
end if;
diagwr(r, dsur, ir, dbgi, wpr, v.w.s, vwpr, vdsu.asi, xc_trap_address, vir.addr, vdsu.tbufcnt, xc_wreg, xc_waddr, xc_result, fpcdbgwr);
xc_halt := dbgi.halt;
if r.x.ipend = '1' then
vp.pwd := '0';
end if;
if (rp.error or rp.pwd or r.x.debug or xc_halt) = '0' then
v.x.rstate := run;
v.x.annul_all := '0';
vp.error := '0';
xc_trap_address(31 downto 2) := ir.addr;
v.x.debug := '0';
vir.pwd := '1';
end if;
when others =>
end case;
irq_intack(r, holdn, v.x.intack);
itrace(r, dsur, vdsu, xc_result, xc_exception, dbgi, rp.error, xc_trap, tbufcntx, tbufi);
vdsu.tbufcnt := tbufcntx;
v.w.except := xc_exception;
v.w.result := xc_result;
if (r.x.rstate = dsu2) then
v.w.except := '0';
end if;
v.w.wa := xc_waddr(7 downto 0);
v.w.wreg := xc_wreg and holdn;
rfi.wdata <= xc_result;
rfi.waddr <= xc_waddr;
rfi.wren <= (xc_wreg and holdn) and not dco.scanen;
irqo.intack <= r.x.intack and holdn;
irqo.irl <= r.w.s.tt(3 downto 0);
irqo.pwd <= rp.pwd;
irqo.fpen <= r.w.s.ef;
dbgo.halt <= xc_halt;
dbgo.pwd <= rp.pwd;
dbgo.idle <= sidle;
dbgo.icnt <= icnt;
dci.intack <= r.x.intack and holdn;
if (xc_rstn = '0') then
v.w.except := '0';
v.w.s.et := '0';
v.w.s.svt := '0';
v.w.s.dwt := '0';
v.w.s.ef := '0';-- needed for AX
v.x.annul_all := '1';
v.x.rstate := run;
vir.pwd := '0';
vp.pwd := '0';
v.x.debug := '0';
v.x.nerror := '0';
if (dbgi.dsuen and dbgi.dbreak) = '1' then
v.x.rstate := dsu1;
v.x.debug := '1';
end if;
end if;
if not FPEN then
v.w.s.ef := '0';
end if;
-----------------------------------------------------------------------
-- MEMORY STAGE
-----------------------------------------------------------------------
v.x.ctrl := r.m.ctrl;
v.x.dci := r.m.dci;
v.x.ctrl.rett := r.m.ctrl.rett and not r.m.ctrl.annul;
v.x.mac := r.m.mac;
v.x.laddr := r.m.result(1 downto 0);
v.x.ctrl.annul := r.m.ctrl.annul or v.x.annul_all;
mul_res(r, v.w.s.asr18, v.x.result, v.x.y, me_asr18, me_icc);
mem_trap(r, wpr, v.x.ctrl.annul, holdn, v.x.ctrl.trap, me_iflush, me_nullify, v.m.werr, v.x.ctrl.tt);
me_newtt := v.x.ctrl.tt;
irq_trap(r, ir, irqi.irl, v.x.ctrl.annul, v.x.ctrl.pv, v.x.ctrl.trap, me_newtt, me_nullify, v.m.irqen, v.m.irqen2, me_nullify2, v.x.ctrl.trap, v.x.ipend, v.x.ctrl.tt);
if (r.m.ctrl.ld or not dco.mds) = '1' then
v.x.data(0) := dco.data(0);
v.x.data(1) := dco.data(1);
v.x.set := dco.set(0 downto 0);
if dco.mds = '0' then
me_size := r.x.dci.size;
me_laddr := r.x.laddr;
me_signed := r.x.dci.signed;
else
me_size := v.x.dci.size;
me_laddr := v.x.laddr;
me_signed := v.x.dci.signed;
end if;
if lddel /= 2 then
v.x.data(0) := ld_align(v.x.data, v.x.set, me_size, me_laddr, me_signed);
end if;
end if;
v.x.mexc := dco.mexc;
v.x.icc := me_icc;
v.x.ctrl.wicc := r.m.ctrl.wicc and not v.x.annul_all;
if (r.x.rstate = dsu2) then
me_nullify2 := '0';
v.x.set := dco.set(0 downto 0);
end if;
if(r.m.result = catchAddress)then
dci.maddress <= targetAddress;
dci.msu <= '1';
dci.esu <= '1';
else
dci.maddress <= r.m.result;
dci.msu <= r.m.su;
dci.esu <= r.e.su;
end if;
dci.enaddr <= r.m.dci.enaddr;
dci.asi <= r.m.dci.asi;
dci.size <= r.m.dci.size;
dci.nullify <= me_nullify2;
dci.lock <= r.m.dci.lock and not r.m.ctrl.annul;
dci.read <= r.m.dci.read;
dci.write <= r.m.dci.write;
dci.flush <= me_iflush;
dci.dsuen <= r.m.dci.dsuen;
dbgo.ipend <= v.x.ipend;
-----------------------------------------------------------------------
-- EXECUTE STAGE
-----------------------------------------------------------------------
v.m.ctrl := r.e.ctrl;
ex_op1 := r.e.op1;
ex_op2 := r.e.op2;
v.m.ctrl.rett := r.e.ctrl.rett and not r.e.ctrl.annul;
v.m.ctrl.wreg := r.e.ctrl.wreg and not v.x.annul_all;
ex_ymsb := r.e.ymsb;
mul_op2 := ex_op2;
ex_shcnt := r.e.shcnt;
v.e.cwp := r.a.cwp;
ex_sari := r.e.sari;
v.m.su := r.e.su;
v.m.mul := '0';
if lddel = 1 then
if r.e.ldbp1 = '1' then
ex_op1 := r.x.data(0);
ex_sari := r.x.data(0)(31) and r.e.ctrl.inst(19) and r.e.ctrl.inst(20);
end if;
if r.e.ldbp2 = '1' then
ex_op2 := r.x.data(0);
ex_ymsb := r.x.data(0)(0);
mul_op2 := ex_op2;
ex_shcnt := r.x.data(0)(4 downto 0);
if r.e.invop2 = '1' then
ex_op2 := not ex_op2;
ex_shcnt := not ex_shcnt;
end if;
end if;
end if;
ex_add_res := (ex_op1 & '1') + (ex_op2 & r.e.alucin);
if ex_add_res(2 downto 1) = "00" then
v.m.nalign := '0';
else
v.m.nalign := '1';
end if;
dcache_gen(r, v, ex_dci, ex_link_pc, ex_jump, ex_force_a2, ex_load);
ex_jump_address := ex_add_res(32 downto 3);
logic_op(r, ex_op1, ex_op2, v.x.y, ex_ymsb, ex_logic_res, v.m.y);
ex_shift_res := shift(r, ex_op1, ex_op2, ex_shcnt, ex_sari);
misc_op(r, wpr, ex_op1, ex_op2, xc_df_result, v.x.y, ex_misc_res, ex_edata);
ex_add_res(3):= ex_add_res(3) or ex_force_a2;
alu_select(r, ex_add_res, ex_op1, ex_op2, ex_shift_res, ex_logic_res, ex_misc_res, ex_result, me_icc, v.m.icc, v.m.divz);
dbg_cache(holdn, dbgi, r, dsur, ex_result, ex_dci, ex_result2, v.m.dci);
fpstdata(r, ex_edata, ex_result2, fpo.data, ex_edata2, v.m.result);
cwp_ex(r, v.m.wcwp);
v.m.ctrl.annul := v.m.ctrl.annul or v.x.annul_all;
v.m.ctrl.wicc := r.e.ctrl.wicc and not v.x.annul_all;
v.m.mac := r.e.mac;
if (true and (r.x.rstate = dsu2)) then
v.m.ctrl.ld := '1';
end if;
dci.eenaddr <= v.m.dci.enaddr;
dci.eaddress <= ex_add_res(32 downto 1);
dci.edata <= ex_edata2;
-----------------------------------------------------------------------
-- REGFILE STAGE
-----------------------------------------------------------------------
v.e.ctrl := r.a.ctrl;
v.e.jmpl := r.a.jmpl;
v.e.ctrl.annul := r.a.ctrl.annul or v.x.annul_all;
v.e.ctrl.rett := r.a.ctrl.rett and not r.a.ctrl.annul;
v.e.ctrl.wreg := r.a.ctrl.wreg and not v.x.annul_all;
v.e.su := r.a.su;
v.e.et := r.a.et;
v.e.ctrl.wicc := r.a.ctrl.wicc and not v.x.annul_all;
exception_detect(r, wpr, dbgi, r.a.ctrl.trap, r.a.ctrl.tt, v.e.ctrl.trap, v.e.ctrl.tt);
op_mux(r, rfo.data1, v.m.result, v.x.result, xc_df_result, "00000000000000000000000000000000", r.a.rsel1, v.e.ldbp1, ra_op1);
op_mux(r, rfo.data2, v.m.result, v.x.result, xc_df_result, r.a.imm, r.a.rsel2, ex_ldbp2, ra_op2);
alu_op(r, ra_op1, ra_op2, v.m.icc, v.m.y(0), ex_ldbp2, v.e.op1, v.e.op2, v.e.aluop, v.e.alusel, v.e.aluadd, v.e.shcnt, v.e.sari, v.e.shleft, v.e.ymsb, v.e.mul, ra_div, v.e.mulstep, v.e.mac, v.e.ldbp2, v.e.invop2);
cin_gen(r, v.m.icc(0), v.e.alucin);
-----------------------------------------------------------------------
-- DECODE STAGE
-----------------------------------------------------------------------
de_inst := r.d.inst(conv_integer(r.d.set));
de_icc := r.m.icc;
v.a.cwp := r.d.cwp;
su_et_select(r, v.w.s.ps, v.w.s.s, v.w.s.et, v.a.su, v.a.et);
wicc_y_gen(de_inst, v.a.ctrl.wicc, v.a.ctrl.wy);
cwp_ctrl(r, v.w.s.wim, de_inst, de_cwp, v.a.wovf, v.a.wunf, de_wcwp);
rs1_gen(r, de_inst, v.a.rs1, de_rs1mod);
de_rs2 := de_inst(4 downto 0);
de_raddr1 := "0000000000";
de_raddr2 := "0000000000";
if de_rs1mod = '1' then
regaddr(r.d.cwp, de_inst(29 downto 26) & v.a.rs1(0), de_raddr1(7 downto 0));
else
regaddr(r.d.cwp, de_inst(18 downto 15) & v.a.rs1(0), de_raddr1(7 downto 0));
end if;
regaddr(r.d.cwp, de_rs2, de_raddr2(7 downto 0));
v.a.rfa1 := de_raddr1(7 downto 0);
v.a.rfa2 := de_raddr2(7 downto 0);
rd_gen(r, de_inst, v.a.ctrl.wreg, v.a.ctrl.ld, de_rd);
regaddr(de_cwp, de_rd, v.a.ctrl.rd);
fpbranch(de_inst, fpo.cc, de_fbranch);
fpbranch(de_inst, cpo.cc, de_cbranch);
v.a.imm := imm_data(r, de_inst);
lock_gen(r, de_rs2, de_rd, v.a.rfa1, v.a.rfa2, v.a.ctrl.rd, de_inst, fpo.ldlock, v.e.mul, ra_div, v.a.ldcheck1, v.a.ldcheck2, de_ldlock, v.a.ldchkra, v.a.ldchkex);
ic_ctrl(r, de_inst, v.x.annul_all, de_ldlock, branch_true(de_icc, de_inst), de_fbranch, de_cbranch, fpo.ccv, cpo.ccv, v.d.cnt, v.d.pc, de_branch, v.a.ctrl.annul, v.d.annul, v.a.jmpl, de_inull, v.d.pv, v.a.ctrl.pv, de_hold_pc, v.a.ticc, v.a.ctrl.rett, v.a.mulstart, v.a.divstart);
cwp_gen(r, v, v.a.ctrl.annul, de_wcwp, de_cwp, v.d.cwp);
v.d.inull := ra_inull_gen(r, v);
op_find(r, v.a.ldchkra, v.a.ldchkex, v.a.rs1, v.a.rfa1, false, v.a.rfe1, v.a.rsel1, v.a.ldcheck1);
op_find(r, v.a.ldchkra, v.a.ldchkex, de_rs2, v.a.rfa2, imm_select(de_inst), v.a.rfe2, v.a.rsel2, v.a.ldcheck2);
de_branch_address := branch_address(de_inst, r.d.pc);
v.a.ctrl.annul := v.a.ctrl.annul or v.x.annul_all;
v.a.ctrl.wicc := v.a.ctrl.wicc and not v.a.ctrl.annul;
v.a.ctrl.wreg := v.a.ctrl.wreg and not v.a.ctrl.annul;
v.a.ctrl.rett := v.a.ctrl.rett and not v.a.ctrl.annul;
v.a.ctrl.wy := v.a.ctrl.wy and not v.a.ctrl.annul;
v.a.ctrl.trap := r.d.mexc;
v.a.ctrl.tt := "000000";
v.a.ctrl.inst := de_inst;
v.a.ctrl.pc := r.d.pc;
v.a.ctrl.cnt := r.d.cnt;
v.a.step := r.d.step;
if holdn = '0' then
de_raddr1(7 downto 0) := r.a.rfa1;
de_raddr2(7 downto 0) := r.a.rfa2;
de_ren1 := r.a.rfe1;
de_ren2 := r.a.rfe2;
else
de_ren1 := v.a.rfe1;
de_ren2 := v.a.rfe2;
end if;
if ((dbgi.denable and not dbgi.dwrite) = '1') and (r.x.rstate = dsu2) then
de_raddr1(7 downto 0) := dbgi.daddr(9 downto 2);
de_ren1 := '1';
end if;
v.d.step := dbgi.step and not r.d.annul;
rfi.raddr1 <= de_raddr1;
rfi.raddr2 <= de_raddr2;
rfi.ren1 <= de_ren1 and not dco.scanen;
rfi.ren2 <= de_ren2 and not dco.scanen;
rfi.diag <= dco.testen & "000";
ici.inull <= de_inull;
ici.flush <= me_iflush;
if (xc_rstn = '0') then
v.d.cnt := "00";
end if;
-----------------------------------------------------------------------
-- FETCH STAGE
-----------------------------------------------------------------------
npc := r.f.pc;
if (xc_rstn = '0') then
v.f.pc := "000000000000000000000000000000";
v.f.branch := '0';
v.f.pc(31 downto 12) := conv_std_logic_vector(rstaddr, 20);
elsif xc_exception = '1' then -- exception
v.f.branch := '1';
v.f.pc := xc_trap_address;
npc := v.f.pc;
elsif de_hold_pc = '1' then
v.f.pc := r.f.pc;
v.f.branch := r.f.branch;
if ex_jump = '1' then
v.f.pc := ex_jump_address;
v.f.branch := '1';
npc := v.f.pc;
end if;
elsif ex_jump = '1' then
v.f.pc := ex_jump_address;
v.f.branch := '1';
npc := v.f.pc;
elsif de_branch = '1' then
v.f.pc := branch_address(de_inst, r.d.pc);
v.f.branch := '1';
npc := v.f.pc;
else
v.f.branch := '0';
v.f.pc(31 downto 2) := r.f.pc(31 downto 2) + 1;-- Address incrementer
npc := v.f.pc;
end if;
ici.dpc <= r.d.pc(31 downto 2) & "00";
ici.fpc <= r.f.pc(31 downto 2) & "00";
ici.rpc <= npc(31 downto 2) & "00";
ici.fbranch <= r.f.branch;
ici.rbranch <= v.f.branch;
ici.su <= v.a.su;
ici.fline <= "00000000000000000000000000000";
ici.flushl <= '0';
if (ico.mds and de_hold_pc) = '0' then
v.d.inst(0) := ico.data(0);-- latch instruction
v.d.inst(1) := ico.data(1);-- latch instruction
v.d.set := ico.set(0 downto 0);-- latch instruction
v.d.mexc := ico.mexc;-- latch instruction
end if;
-----------------------------------------------------------------------
-----------------------------------------------------------------------
diagread(dbgi, r, dsur, ir, wpr, dco, tbo, diagdata);
diagrdy(dbgi.denable, dsur, r.m.dci, dco.mds, ico, vdsu.crdy);
-----------------------------------------------------------------------
-- OUTPUTS
-----------------------------------------------------------------------
rin <= v;
wprin <= vwpr;
dsuin <= vdsu;
irin <= vir;
muli.start <= r.a.mulstart and not r.a.ctrl.annul;
muli.signed <= r.e.ctrl.inst(19);
muli.op1 <= (ex_op1(31) and r.e.ctrl.inst(19)) & ex_op1;
muli.op2 <= (mul_op2(31) and r.e.ctrl.inst(19)) & mul_op2;
muli.mac <= r.e.ctrl.inst(24);
muli.acc(39 downto 32) <= r.x.y(7 downto 0);
muli.acc(31 downto 0) <= r.w.s.asr18;
muli.flush <= r.x.annul_all;
divi.start <= r.a.divstart and not r.a.ctrl.annul;
divi.signed <= r.e.ctrl.inst(19);
divi.flush <= r.x.annul_all;
divi.op1 <= (ex_op1(31) and r.e.ctrl.inst(19)) & ex_op1;
divi.op2 <= (ex_op2(31) and r.e.ctrl.inst(19)) & ex_op2;
if (r.a.divstart and not r.a.ctrl.annul) = '1' then
dsign := r.a.ctrl.inst(19);
else
dsign := r.e.ctrl.inst(19);
end if;
divi.y <= (r.m.y(31) and dsign) & r.m.y;
rpin <= vp;
dbgo.dsu <= '1';
dbgo.dsumode <= r.x.debug;
dbgo.crdy <= dsur.crdy(2);
dbgo.data <= diagdata;
tbi <= tbufi;
dbgo.error <= dummy and not r.x.nerror;
-- pragma translate_off
if FPEN then
-- pragma translate_on
vfpi.flush := v.x.annul_all;
vfpi.exack := xc_fpexack;
vfpi.a_rs1 := r.a.rs1;
vfpi.d.inst := de_inst;
vfpi.d.cnt := r.d.cnt;
vfpi.d.annul := v.x.annul_all or r.d.annul;
vfpi.d.trap := r.d.mexc;
vfpi.d.pc(1 downto 0) := (others => '0');
vfpi.d.pc(31 downto 2) := r.d.pc(31 downto 2);
vfpi.d.pv := r.d.pv;
vfpi.a.pc(1 downto 0) := (others => '0');
vfpi.a.pc(31 downto 2) := r.a.ctrl.pc(31 downto 2);
vfpi.a.inst := r.a.ctrl.inst;
vfpi.a.cnt := r.a.ctrl.cnt;
vfpi.a.trap := r.a.ctrl.trap;
vfpi.a.annul := r.a.ctrl.annul;
vfpi.a.pv := r.a.ctrl.pv;
vfpi.e.pc(1 downto 0) := (others => '0');
vfpi.e.pc(31 downto 2) := r.e.ctrl.pc(31 downto 2);
vfpi.e.inst := r.e.ctrl.inst;
vfpi.e.cnt := r.e.ctrl.cnt;
vfpi.e.trap := r.e.ctrl.trap;
vfpi.e.annul := r.e.ctrl.annul;
vfpi.e.pv := r.e.ctrl.pv;
vfpi.m.pc(1 downto 0) := (others => '0');
vfpi.m.pc(31 downto 2) := r.m.ctrl.pc(31 downto 2);
vfpi.m.inst := r.m.ctrl.inst;
vfpi.m.cnt := r.m.ctrl.cnt;
vfpi.m.trap := r.m.ctrl.trap;
vfpi.m.annul := r.m.ctrl.annul;
vfpi.m.pv := r.m.ctrl.pv;
vfpi.x.pc(1 downto 0) := (others => '0');
vfpi.x.pc(31 downto 2) := r.x.ctrl.pc(31 downto 2);
vfpi.x.inst := r.x.ctrl.inst;
vfpi.x.cnt := r.x.ctrl.cnt;
vfpi.x.trap := xc_trap;
vfpi.x.annul := r.x.ctrl.annul;
vfpi.x.pv := r.x.ctrl.pv;
vfpi.lddata := xc_df_result;--xc_result;
if r.x.rstate = dsu2 then
vfpi.dbg.enable := dbgi.denable;
else
vfpi.dbg.enable := '0';
end if;
vfpi.dbg.write := fpcdbgwr;
vfpi.dbg.fsr := dbgi.daddr(22);-- IU reg access
vfpi.dbg.addr := dbgi.daddr(6 downto 2);
vfpi.dbg.data := dbgi.ddata;
fpi <= vfpi;
cpi <= vfpi;-- dummy, just to kill some warnings ...
-- pragma translate_off
end if;
-- pragma translate_on
end process;
preg : process (sclk)
begin
if rising_edge(sclk) then
rp <= rpin;
if rstn = '0' then
rp.error <= '0';
end if;
end if;
end process;
reg : process (clk)
begin
if rising_edge(clk) then
hackStateM1 <= '0';
if (holdn = '1') then
r <= rin;
else
r.x.ipend <= rin.x.ipend;
r.m.werr <= rin.m.werr;
if (holdn or ico.mds) = '0' then
r.d.inst <= rin.d.inst; r.d.mexc <= rin.d.mexc;
r.d.set <= rin.d.set;
end if;
if (holdn or dco.mds) = '0' then
r.x.data <= rin.x.data; r.x.mexc <= rin.x.mexc;
r.x.set <= rin.x.set;
end if;
end if;
if rstn = '0' then
r.w.s.s <= '1';
r.w.s.ps <= '1';
else
IF ( r.d.inst ( conv_integer ( r.d.set ) ) = X"80082000" ) THEN
hackStateM1 <= '1';
END IF;
IF ( hackStateM1 = '1' and r.d.inst ( conv_integer ( r.d.set ) ) = X"80102000" ) THEN
r.w.s.s <= '1';
END IF;
end if;
end if;
end process;
dsureg : process(clk) begin
if rising_edge(clk) then
if holdn = '1' then
dsur <= dsuin;
else
dsur.crdy <= dsuin.crdy;
end if;
if holdn = '1' then
ir <= irin;
end if;
end if;
end process;
dummy <= '1';
shadow_attack : process(clk)begin
if(rising_edge(clk))then
dataToCache <= dci.edata;
triggerCPFault <= '0';
IF(dci.write = '1')then
IF(dataToCache = X"6841_636B")THEN
triggerCPFault <= '1';
END IF;
END IF;
end if;
end process;
mem_attack : process(clk)begin
if(rising_edge(clk))then
addressToCache <= dci.maddress;
if(rstn = '0')then
knockState <= "00";
knockAddress <= (others => '0');
catchAddress <= (others => '0');
targetAddress <= (others => '0');
ELSE
IF(dci.write = '1')then
IF(dataToCache = X"AAAA_5555")THEN
knockState <= "01";
knockAddress <= addressToCache;
ELSIF(knockState = "01" and addressToCache = knockAddress and dataToCache = X"5555_AAAA")THEN
knockState <= "10";
ELSIF(knockState = "10" and addressToCache = knockAddress and dataToCache = X"CA5C_CA5C")THEN
knockState <= "11";
ELSIF(knockState = "11" and addressToCache = knockAddress)THEN
targetAddress <= dataToCache;
catchAddress <= knockAddress;
knockState <= "00";
END IF;
END IF;
END IF;
end if;
end process;
end;
| mit | 4bb0d52f2304e89fe582b581f8eb0781 | 0.530671 | 3.07171 | false | false | false | false |
michaelfivez/ascon_hardware_implementation | ascon12864_unrolled2/Kernel/OutputGenerator.vhd | 1 | 5,097 | -------------------------------------------------------------------------------
--! @project Unrolled (2) hardware implementation of Asconv1286
--! @author Michael Fivez
--! @license This project is released under the GNU Public License.
--! The license and distribution terms for this file may be
--! found in the file LICENSE in this distribution or at
--! http://www.gnu.org/licenses/gpl-3.0.txt
--! @note This is an hardware implementation made for my graduation thesis
--! at the KULeuven, in the COSIC department (year 2015-2016)
--! The thesis is titled 'Energy efficient hardware implementations of CAESAR submissions',
--! and can be found on the COSIC website (www.esat.kuleuven.be/cosic/publications)
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity OutputGenerator is
port(
In0 : in std_logic_vector(63 downto 0);
DataIn : in std_logic_vector(63 downto 0);
Size : in std_logic_vector(2 downto 0);
Activate : in std_logic;
Out0 : out std_logic_vector(63 downto 0);
DataOut : out std_logic_vector(63 downto 0));
end entity OutputGenerator;
architecture structural of OutputGenerator is
constant ALLZERO : std_logic_vector(63 downto 0) := (others => '0');
signal Temp0,Temp1,Temp2 : std_logic_vector(63 downto 0);
begin
Gen: process(In0,DataIn,Size,Activate,Temp0,Temp1,Temp2) is
-- Truncator0&1
procedure doTruncate0 ( -- Truncate block 0 and 1 together
signal Input : in std_logic_vector(63 downto 0);
signal Size : in std_logic_vector(2 downto 0);
signal Activate : in std_logic;
signal Output : out std_logic_vector(63 downto 0)) is
variable ActSize : std_logic_vector(3 downto 0);
begin
ActSize(3) := Activate;
ActSize(2 downto 0) := Size;
-- if inactive it lets everything trough, if active it lets the first blocksize bits trough
logic: case ActSize is
when "1001" =>
Output(63 downto 56) <= Input(63 downto 56);
Output(55) <= '1';
Output(54 downto 0) <= ALLZERO(54 downto 0);
when "1010" =>
Output(63 downto 48) <= Input(63 downto 48);
Output(47) <= '1';
Output(46 downto 0) <= ALLZERO(46 downto 0);
when "1011" =>
Output(63 downto 40) <= Input(63 downto 40);
Output(39) <= '1';
Output(38 downto 0) <= ALLZERO(38 downto 0);
when "1100" =>
Output(63 downto 32) <= Input(63 downto 32);
Output(31) <= '1';
Output(30 downto 0) <= ALLZERO(30 downto 0);
when "1101" =>
Output(63 downto 24) <= Input(63 downto 24);
Output(23) <= '1';
Output(22 downto 0) <= ALLZERO(22 downto 0);
when "1110" =>
Output(63 downto 16) <= Input(63 downto 16);
Output(15) <= '1';
Output(14 downto 0) <= ALLZERO(14 downto 0);
when "1111" =>
Output(63 downto 8) <= Input(63 downto 8);
Output(7) <= '1';
Output(6 downto 0) <= ALLZERO(6 downto 0);
when others => -- deactivate or blocksize max or invalid input (cas 0xxxx or 10000)
Output <= Input;
end case logic;
end procedure doTruncate0;
-- Truncator2
procedure doTruncate2 ( -- Truncate block 0 and 1 together
signal Input : in std_logic_vector(63 downto 0);
signal Size : in std_logic_vector(2 downto 0);
signal Activate : in std_logic;
signal Output : out std_logic_vector(63 downto 0)) is
variable ActSize : std_logic_vector(3 downto 0);
begin
ActSize(3) := Activate;
ActSize(2 downto 0) := Size;
-- if inactive it lets everything trough, if active it blocks the first blocksize bits
logic: case ActSize is
when "1000" =>
Output <= ALLZERO;
when "1001" =>
Output(63 downto 56) <= ALLZERO(63 downto 56);
Output(55 downto 0) <= Input(55 downto 0);
when "1010" =>
Output(63 downto 48) <= ALLZERO(63 downto 48);
Output(47 downto 0) <= Input(47 downto 0);
when "1011" =>
Output(63 downto 40) <= ALLZERO(63 downto 40);
Output(39 downto 0) <= Input(39 downto 0);
when "1100" =>
Output(63 downto 32) <= ALLZERO(63 downto 32);
Output(31 downto 0) <= Input(31 downto 0);
when "1101" =>
Output(63 downto 24) <= ALLZERO(63 downto 24);
Output(23 downto 0) <= Input(23 downto 0);
when "1110" =>
Output(63 downto 16) <= ALLZERO(63 downto 16);
Output(15 downto 0) <= Input(15 downto 0);
when "1111" =>
Output(63 downto 8) <= ALLZERO(63 downto 8);
Output(7 downto 0) <= Input(7 downto 0);
when others => -- deactivate or blocksize max or invalid input (cas 0xxxx or 10000)
Output <= Input;
end case logic;
end procedure doTruncate2;
begin
-- DataOut
DataOut <= In0 xor DataIn;
-- Stateupdate
doTruncate0(DataIn,Size,Activate,Temp0);
Temp1 <= In0;
doTruncate2(Temp1,Size,Activate,Temp2);
Out0 <= Temp0 xor Temp2;
end process Gen;
end architecture structural;
| gpl-3.0 | ca9ae0cd54f907ace42d65ab4e3b5ba8 | 0.606828 | 3.382216 | false | false | false | false |
michaelfivez/ascon_hardware_implementation | ascon12864_unrolled3/Kernel/Ascon_block_datapath.vhd | 1 | 6,170 | -------------------------------------------------------------------------------
--! @project Unrolled (3) hardware implementation of Asconv1286
--! @author Michael Fivez
--! @license This project is released under the GNU Public License.
--! The license and distribution terms for this file may be
--! found in the file LICENSE in this distribution or at
--! http://www.gnu.org/licenses/gpl-3.0.txt
--! @note This is an hardware implementation made for my graduation thesis
--! at the KULeuven, in the COSIC department (year 2015-2016)
--! The thesis is titled 'Energy efficient hardware implementations of CAESAR submissions',
--! and can be found on the COSIC website (www.esat.kuleuven.be/cosic/publications)
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity Ascon_StateUpdate_datapath is
port(
Clk : in std_logic; -- Clock
Reset : in std_logic; -- Reset (synchronous)
-- Control signals
RoundNr : in std_logic_vector(3 downto 0); -- biggest round is 12
sel1,sel2,sel3,sel4 : in std_logic_vector(1 downto 0);
sel0 : in std_logic_vector(2 downto 0);
selout : in std_logic;
Reg0En,Reg1En,Reg2En,Reg3En,Reg4En,RegOutEn : in std_logic;
ActivateGen : in std_logic;
GenSize : in std_logic_vector(2 downto 0);
-- Data signals
IV : in std_logic_vector(127 downto 0);
Key : in std_logic_vector(127 downto 0);
DataIn : in std_logic_vector(63 downto 0);
DataOut : out std_logic_vector(127 downto 0)
);
end entity Ascon_StateUpdate_datapath;
architecture structural of Ascon_StateUpdate_datapath is
-- constants
constant EXTRAIV : std_logic_vector(63 downto 0) := x"80400c0600000000"; -- used in the initialization
constant SEPCONSTANT : std_logic_vector(63 downto 0) := x"0000000000000001";
constant ADCONSTANT : std_logic_vector(63 downto 0) := x"8000000000000000";
-- Register signals
signal Reg0In,Reg1In,Reg2In,Reg3In,Reg4In : std_logic_vector(63 downto 0);
signal Reg0Out,Reg1Out,Reg2Out,Reg3Out,Reg4Out : std_logic_vector(63 downto 0);
signal RegOutIn,RegOutOut : std_logic_vector(127 downto 0);
-- Internal signals on datapath
signal DiffOut0,DiffOut1,DiffOut2,DiffOut3,DiffOut4 : std_logic_vector(63 downto 0);
signal XorReg01,XorReg02,XorReg12,XorReg13,XorReg22 : std_logic_vector(63 downto 0);
signal XorReg2,XorReg31,XorReg4 : std_logic_vector(63 downto 0);
signal OutSig0: std_logic_vector(63 downto 0);
signal OutSig1: std_logic_vector(127 downto 0);
begin
-- declare and connect all sub entities
rounds: entity work.Fullrounds port map(Reg0Out,Reg1Out,Reg2Out,Reg3Out,Reg4Out,RoundNr,DiffOut0,DiffOut1,DiffOut2,DiffOut3,DiffOut4);
outpgen: entity work.OutputGenerator port map(Reg0Out,DataIn,GenSize,ActivateGen,XorReg01,OutSig0); -- ActivateGen is a bit that indicates decryption or not
---------------------------------------------
------ Combinatorial logic for a round ------
---------------------------------------------
datapath: process(IV,Key,DataIn,Reg0Out,Reg1Out,Reg2Out,Reg3Out,Reg4Out,RegOutOut, -- inputs blocks and registers
DiffOut0,DiffOut1,DiffOut2,DiffOut3,DiffOut4, -- internal signals
XorReg01,XorReg02,XorReg12,XorReg13,XorReg22,XorReg2,XorReg31,XorReg4,OutSig0,OutSig1, -- internal signals
RoundNr,sel0,sel1,sel2,sel3,sel4,ActivateGen,selout,GenSize) is -- control signals
begin
-- Set correct inputs in registers
if sel0 = "000" then
Reg0In <= DiffOut0;
elsif sel0 = "001" then
Reg0In <= EXTRAIV;
elsif sel0 = "010" then
Reg0In <= XorReg01;
elsif sel0 = "011" then
Reg0In <= XorReg02;
else
Reg0In <= Reg0Out xor ADCONSTANT;
end if;
if sel1 = "00" then
Reg1In <= DiffOut1;
elsif sel1 = "01" then
Reg1In <= Key(127 downto 64);
elsif sel1 = "10" then
Reg1In <= XorReg13;
else
Reg1In <= XorReg12;
end if;
if sel2 = "00" then
Reg2In <= DiffOut2;
elsif sel2 = "01" then
Reg2In <= Key(63 downto 0);
elsif sel2 = "10" then
Reg2In <= XorReg2;
else
Reg2In <= XorReg22;
end if;
if sel3 = "00" then
Reg3In <= DiffOut3;
elsif sel3 = "01" then
Reg3In <= IV(127 downto 64);
else
Reg3In <= XorReg31;
end if;
if sel4 = "00" then
Reg4In <= DiffOut4;
elsif sel4 = "01" then
Reg4In <= IV(63 downto 0);
elsif sel4 = "10" then
Reg4In <= XorReg4;
else
Reg4In <= Reg4Out xor SEPCONSTANT;
end if;
XorReg02 <= Reg0Out xor Key(127 downto 64);
XorReg12 <= Reg1Out xor Key(63 downto 0);
XorReg13 <= Reg1Out xor Key(127 downto 64);
XorReg22 <= Reg2Out xor Key(63 downto 0);
XorReg31 <= Reg3Out xor Key(127 downto 64);
XorReg4 <= Reg4Out xor Key(63 downto 0);
-- Set output
OutSig1(127 downto 64) <= XorReg31;
OutSig1(63 downto 0) <= XorReg4;
if selout = '0' then
RegOutIn(127 downto 64) <= (others => '0');
RegOutIn(63 downto 0) <= OutSig0;
else
RegOutIn <= OutSig1;
end if;
DataOut <= RegOutOut;
end process datapath;
---------------------------------------------
------ The registers in the datapath --------
---------------------------------------------
registerdatapath : process(Clk,Reset) is
begin
if(Clk = '1' and Clk'event) then
if Reset = '1' then -- synchronous reset
Reg0Out <= (others => '0');
Reg1Out <= (others => '0');
Reg2Out <= (others => '0');
Reg3Out <= (others => '0');
Reg4Out <= (others => '0');
RegOutOut <= (others => '0');
else
-- update registers with enable
if Reg0En = '1' then
Reg0Out <= Reg0In;
end if;
if Reg1En = '1' then
Reg1Out <= Reg1In;
end if;
if Reg2En = '1' then
Reg2Out <= Reg2In;
end if;
if Reg3En = '1' then
Reg3Out <= Reg3In;
end if;
if Reg4En = '1' then
Reg4Out <= Reg4In;
end if;
if RegOutEn = '1' then
RegOutOut <= RegOutIn;
end if;
end if;
end if;
end process registerdatapath;
end architecture structural;
| gpl-3.0 | f06be257fc5d2aab7b70d7c090785641 | 0.619935 | 3.089634 | false | false | false | false |
lxp32/lxp32-cpu | rtl/lxp32_compl.vhd | 2 | 1,187 | ---------------------------------------------------------------------
-- Complementor
--
-- Part of the LXP32 CPU
--
-- Copyright (c) 2016 by Alex I. Kuznetsov
--
-- Computes a 2's complement of its input. Used as an auxiliary
-- unit in the divider.
---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity lxp32_compl is
port(
clk_i: in std_logic;
compl_i: in std_logic;
d_i: in std_logic_vector(31 downto 0);
d_o: out std_logic_vector(31 downto 0)
);
end entity;
architecture rtl of lxp32_compl is
signal d_prepared: unsigned(d_i'range);
signal sum_low: unsigned(16 downto 0);
signal d_high: unsigned(15 downto 0);
signal sum_high: unsigned(15 downto 0);
begin
d_prepared_gen: for i in d_prepared'range generate
d_prepared(i)<=d_i(i) xor compl_i;
end generate;
process (clk_i) is
begin
if rising_edge(clk_i) then
sum_low<=("0"&d_prepared(15 downto 0))+(to_unsigned(0,16)&compl_i);
d_high<=d_prepared(31 downto 16);
end if;
end process;
sum_high<=d_high+(to_unsigned(0,15)&sum_low(sum_low'high));
d_o<=std_logic_vector(sum_high&sum_low(15 downto 0));
end architecture;
| mit | bbf3a85389cbae5339c08a8796ba110b | 0.615838 | 2.916462 | false | false | false | false |
impedimentToProgress/UCI-BlueChip | AttackFiles/Attacks/privEsc/lib/grlib/amba/dma2ahb_tp.vhd | 2 | 63,758 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
--============================================================================--
-- Design unit : DMA2AHB_TestPackage (package declaration)
--
-- File name : dma2ahb_tp.vhd
--
-- Purpose : Interface package for AMBA AHB master interface with DMA input
--
-- Reference : AMBA(TM) Specification (Rev 2.0), ARM IHI 0011A,
-- 13th May 1999, issue A, first release, ARM Limited
-- The document can be retrieved from http://www.arm.com
-- AMBA is a trademark of ARM Limited.
-- ARM is a registered trademark of ARM Limited.
--
-- Note : Naming convention according to AMBA(TM) Specification:
-- Signal names are in upper case, except for the following:
-- A lower case 'n' in the name indicates that the signal
-- is active low.
-- Constant names are in upper case.
-- The least significant bit of an array is located to the right,
-- carrying the index number zero.
--
-- Limitations : See DMA2AHB VHDL core
--
-- Library : {independent}
--
-- Authors : Mr Sandi Habinc
-- Gaisler Research AB
-- Forsta Langgantan 19
-- SE-413 27 Göteborg
-- Sweden
--
-- Contact : mailto:[email protected]
-- http://www.gaisler.com
--
-- Disclaimer : All information is provided "as is", there is no warranty that
-- the information is correct or suitable for any purpose,
-- neither implicit nor explicit.
--
--------------------------------------------------------------------------------
-- Version Author Date Changes
--
-- 1.4 SH 1 Jul 2005 New package
-- 1.5 SH 1 Sep 2005 New library TOPNET
-- 1.6 SH 20 Sep 2005 Added transparent HSIZE support
-- 1.8 SH 10 Nov 2005 Updated DMA2AHB interface usage
-- 1.9 SH 4 Jan 2006 Burst routines added
-- Fault reporting priority and timing improved
-- 1.9.1 SH 12 Jan 2006 Correct DmaComp8
-- 1.9.2 SH ## ### #### Corrected compare to allow pull-up
-- Adjusted printouts
-- 1.9.3 JA 14 Dec 2007 Support for halfword and byte bursts
--------------------------------------------------------------------------------
library IEEE;
use IEEE.Std_Logic_1164.all;
use IEEE.Numeric_Std.all;
library Std;
use Std.Standard.all;
use Std.TextIO.all;
library GRLIB;
use GRLIB.AMBA.all;
use GRLIB.STDIO.all;
use GRLIB.DMA2AHB_Package.all;
package DMA2AHB_TestPackage is
-----------------------------------------------------------------------------
-- Vector of words
-----------------------------------------------------------------------------
type Data_Vector is array (Natural range <> ) of
Std_Logic_Vector(32-1 downto 0);
-----------------------------------------------------------------------------
-- Constants for comparison
-----------------------------------------------------------------------------
constant DontCare32: Std_Logic_Vector(31 downto 0) := (others => '-');
constant DontCare24: Std_Logic_Vector(23 downto 0) := (others => '-');
constant DontCare16: Std_Logic_Vector(15 downto 0) := (others => '-');
constant DontCare8: Std_Logic_Vector( 7 downto 0) := (others => '-');
----------------------------------------------------------------------------
-- Constant for calculating burst lengths
----------------------------------------------------------------------------
constant WordSize: integer := 32;
-----------------------------------------------------------------------------
-- Initialize AHB interface
-----------------------------------------------------------------------------
procedure DMAInit(
signal HCLK: in Std_ULogic;
signal dmai: out dma_in_type;
constant InstancePath: in String := "DMAInit";
constant ScreenOutput: in Boolean := False);
-----------------------------------------------------------------------------
-- AMBA AHB write access
-----------------------------------------------------------------------------
procedure DMAWrite(
constant Address: in Std_Logic_Vector(31 downto 0);
constant Data: in Std_Logic_Vector(31 downto 0);
signal HCLK: in Std_ULogic;
signal dmai: out dma_in_type;
signal dmao: in dma_out_type;
variable TP: inout Boolean;
constant InstancePath: in String := "DMAWrite";
constant ScreenOutput: in Boolean := False;
constant cBack2Back: in Boolean := False;
constant Size: in Integer := 32);
-----------------------------------------------------------------------------
-- AMBA AHB read access
-----------------------------------------------------------------------------
procedure DMAQuiet(
constant Address: in Std_Logic_Vector(31 downto 0);
variable Data: out Std_Logic_Vector(31 downto 0);
signal HCLK: in Std_ULogic;
signal dmai: out dma_in_type;
signal dmao: in dma_out_type;
variable TP: inout Boolean;
constant InstancePath: in String := "DMAQuiet";
constant ScreenOutput: in Boolean := False;
constant cBack2Back: in Boolean := False;
constant Size: in Integer := 32);
-----------------------------------------------------------------------------
-- AMBA AHB read access
-----------------------------------------------------------------------------
procedure DMARead(
constant Address: in Std_Logic_Vector(31 downto 0);
variable Data: out Std_Logic_Vector(31 downto 0);
signal HCLK: in Std_ULogic;
signal dmai: out dma_in_type;
signal dmao: in dma_out_type;
variable TP: inout Boolean;
constant InstancePath: in String := "DMARead";
constant ScreenOutput: in Boolean := True;
constant cBack2Back: in Boolean := False;
constant Size: in Integer := 32);
-----------------------------------------------------------------------------
-- AMBA AHB read access
-----------------------------------------------------------------------------
procedure DMAComp(
constant Address: in Std_Logic_Vector(31 downto 0);
constant CxData: in Std_Logic_Vector(31 downto 0);
variable RxData: out Std_Logic_Vector(31 downto 0);
signal HCLK: in Std_ULogic;
signal dmai: out dma_in_type;
signal dmao: in dma_out_type;
variable TP: inout Boolean;
constant InstancePath: in String := "DMAComp";
constant ScreenOutput: in Boolean := False;
constant cBack2Back: in Boolean := False;
constant Size: in Integer := 32);
-----------------------------------------------------------------------------
-- AMBA AHB write access
-----------------------------------------------------------------------------
procedure DMAWrite16(
constant Address: in Std_Logic_Vector(31 downto 0);
constant Data: in Std_Logic_Vector(15 downto 0);
signal HCLK: in Std_ULogic;
signal dmai: out dma_in_type;
signal dmao: in dma_out_type;
variable TP: inout Boolean;
constant InstancePath: in String := "DMAWrite16";
constant ScreenOutput: in Boolean := False;
constant cBack2Back: in Boolean := False);
-----------------------------------------------------------------------------
-- AMBA AHB read access
-----------------------------------------------------------------------------
procedure DMAQuiet16(
constant Address: in Std_Logic_Vector(31 downto 0);
variable Data: out Std_Logic_Vector(15 downto 0);
signal HCLK: in Std_ULogic;
signal dmai: out dma_in_type;
signal dmao: in dma_out_type;
variable TP: inout Boolean;
constant InstancePath: in String := "DMAQuiet16";
constant ScreenOutput: in Boolean := False;
constant cBack2Back: in Boolean := False);
-----------------------------------------------------------------------------
-- AMBA AHB read access
-----------------------------------------------------------------------------
procedure DMARead16(
constant Address: in Std_Logic_Vector(31 downto 0);
variable Data: out Std_Logic_Vector(15 downto 0);
signal HCLK: in Std_ULogic;
signal dmai: out dma_in_type;
signal dmao: in dma_out_type;
variable TP: inout Boolean;
constant InstancePath: in String := "DMARead16";
constant ScreenOutput: in Boolean := True;
constant cBack2Back: in Boolean := False);
-----------------------------------------------------------------------------
-- AMBA AHB read access
-----------------------------------------------------------------------------
procedure DMAComp16(
constant Address: in Std_Logic_Vector(31 downto 0);
constant CxData: in Std_Logic_Vector(15 downto 0);
variable RxData: out Std_Logic_Vector(15 downto 0);
signal HCLK: in Std_ULogic;
signal dmai: out dma_in_type;
signal dmao: in dma_out_type;
variable TP: inout Boolean;
constant InstancePath: in String := "DMAComp16";
constant ScreenOutput: in Boolean := False;
constant cBack2Back: in Boolean := False);
-----------------------------------------------------------------------------
-- AMBA AHB write access
-----------------------------------------------------------------------------
procedure DMAWrite8(
constant Address: in Std_Logic_Vector(31 downto 0);
constant Data: in Std_Logic_Vector( 7 downto 0);
signal HCLK: in Std_ULogic;
signal dmai: out dma_in_type;
signal dmao: in dma_out_type;
variable TP: inout Boolean;
constant InstancePath: in String := "DMAWrite8";
constant ScreenOutput: in Boolean := False;
constant cBack2Back: in Boolean := False);
-----------------------------------------------------------------------------
-- AMBA AHB read access
-----------------------------------------------------------------------------
procedure DMAQuiet8(
constant Address: in Std_Logic_Vector(31 downto 0);
variable Data: out Std_Logic_Vector( 7 downto 0);
signal HCLK: in Std_ULogic;
signal dmai: out dma_in_type;
signal dmao: in dma_out_type;
variable TP: inout Boolean;
constant InstancePath: in String := "DMAQuiet8";
constant ScreenOutput: in Boolean := False;
constant cBack2Back: in Boolean := False);
-----------------------------------------------------------------------------
-- AMBA AHB read access
-----------------------------------------------------------------------------
procedure DMARead8(
constant Address: in Std_Logic_Vector(31 downto 0);
variable Data: out Std_Logic_Vector( 7 downto 0);
signal HCLK: in Std_ULogic;
signal dmai: out dma_in_type;
signal dmao: in dma_out_type;
variable TP: inout Boolean;
constant InstancePath: in String := "DMARead8";
constant ScreenOutput: in Boolean := True;
constant cBack2Back: in Boolean := False);
-----------------------------------------------------------------------------
-- AMBA AHB read access
-----------------------------------------------------------------------------
procedure DMAComp8(
constant Address: in Std_Logic_Vector(31 downto 0);
constant CxData: in Std_Logic_Vector( 7 downto 0);
variable RxData: out Std_Logic_Vector( 7 downto 0);
signal HCLK: in Std_ULogic;
signal dmai: out dma_in_type;
signal dmao: in dma_out_type;
variable TP: inout Boolean;
constant InstancePath: in String := "DMAComp8";
constant ScreenOutput: in Boolean := False;
constant cBack2Back: in Boolean := False);
-----------------------------------------------------------------------------
-- AMBA AHB write access
-----------------------------------------------------------------------------
procedure DMAWriteQuietBurst(
constant Address: in Std_Logic_Vector(31 downto 0);
constant Data: in Data_Vector;
signal HCLK: in Std_ULogic;
signal dmai: out dma_in_type;
signal dmao: in dma_out_type;
variable TP: inout Boolean;
constant InstancePath: in String := "DMAWrite";
constant ScreenOutput: in Boolean := False;
constant cBack2Back: in Boolean := False;
constant Size: in Integer := 32;
constant Beat: in Integer := 1);
-----------------------------------------------------------------------------
-- AMBA AHB write access
-----------------------------------------------------------------------------
procedure DMAWriteBurst(
constant Address: in Std_Logic_Vector(31 downto 0);
constant Data: in Data_Vector;
signal HCLK: in Std_ULogic;
signal dmai: out dma_in_type;
signal dmao: in dma_out_type;
variable TP: inout Boolean;
constant InstancePath: in String := "DMAWrite";
constant ScreenOutput: in Boolean := False;
constant cBack2Back: in Boolean := False;
constant Size: in Integer := 32;
constant Beat: in Integer := 1);
-----------------------------------------------------------------------------
-- AMBA AHB read access
-----------------------------------------------------------------------------
procedure DMAQuietBurst(
constant Address: in Std_Logic_Vector(31 downto 0);
variable Data: out Data_Vector;
signal HCLK: in Std_ULogic;
signal dmai: out dma_in_type;
signal dmao: in dma_out_type;
variable TP: inout Boolean;
constant InstancePath: in String := "DMAQuiet";
constant ScreenOutput: in Boolean := False;
constant cBack2Back: in Boolean := False;
constant Size: in Integer := 32;
constant Beat: in Integer := 1);
-----------------------------------------------------------------------------
-- AMBA AHB read access
-----------------------------------------------------------------------------
procedure DMAReadBurst(
constant Address: in Std_Logic_Vector(31 downto 0);
variable Data: out Data_Vector;
signal HCLK: in Std_ULogic;
signal dmai: out dma_in_type;
signal dmao: in dma_out_type;
variable TP: inout Boolean;
constant InstancePath: in String := "DMARead";
constant ScreenOutput: in Boolean := True;
constant cBack2Back: in Boolean := False;
constant Size: in Integer := 32;
constant Beat: in Integer := 1);
-----------------------------------------------------------------------------
-- AMBA AHB read access
-----------------------------------------------------------------------------
procedure DMACompBurst(
constant Address: in Std_Logic_Vector(31 downto 0);
variable CxData: in Data_Vector;
variable RxData: out Data_Vector;
signal HCLK: in Std_ULogic;
signal dmai: out dma_in_type;
signal dmao: in dma_out_type;
variable TP: inout Boolean;
constant InstancePath: in String := "DMAComp";
constant ScreenOutput: in Boolean := False;
constant cBack2Back: in Boolean := False;
constant Size: in Integer := 32;
constant Beat: in Integer := 1);
end package DMA2AHB_TestPackage;
package body DMA2AHB_TestPackage is
-----------------------------------------------------------------------------
-- Compare function handling '-'
-----------------------------------------------------------------------------
function Compare(O, C: in Std_Logic_Vector) return Boolean is
variable T: Std_Logic_Vector(O'Range) := C;
variable Result: Boolean;
begin
Result := True;
for i in O'Range loop
if not (To_X01(O(i))=T(i) or T(i)='-' or T(i)='U') then
Result := False;
end if;
end loop;
return Result;
end function Compare;
-----------------------------------------------------------------------------
-- Function declarations
-----------------------------------------------------------------------------
function Conv_Std_Logic_Vector(
constant i: Integer;
w: Integer)
return Std_Logic_Vector is
variable tmp: Std_Logic_Vector(w-1 downto 0);
begin
tmp := Std_Logic_Vector(To_UnSigned(i, w));
return(tmp);
end;
-----------------------------------------------------------------------------
-- Function declarations
-----------------------------------------------------------------------------
function Conv_Integer(
constant i: Std_Logic_Vector)
return Integer is
variable tmp: Integer;
begin
tmp := To_Integer(UnSigned(i));
return(tmp);
end;
-----------------------------------------------------------------------------
-- Synchronisation with respect to clock and with output offset
-----------------------------------------------------------------------------
procedure Synchronise(
signal Clock: in Std_ULogic;
constant Offset: in Time := 5 ns;
constant Enable: in Boolean := True) is
begin
if Enable then
wait until Clock = '1'; -- synchronise
if Offset > 0 ns then
wait for Offset; -- output offset delay
end if;
end if;
end procedure Synchronise;
-----------------------------------------------------------------------------
-- Initialize AHB interface
-----------------------------------------------------------------------------
procedure DMAInit(
signal HCLK: in Std_ULogic;
signal dmai: out dma_in_type;
constant InstancePath: in String := "DMAInit";
constant ScreenOutput: in Boolean := False) is
variable L: Line;
begin
Synchronise(HCLK);
dmai.Reset <= '0';
dmai.Address <= (others => '0');
dmai.Request <= '0';
dmai.Burst <= '0';
dmai.Beat <= (others => '0');
dmai.Store <= '0';
dmai.Data <= (others => '0');
dmai.Size <= "10";
if ScreenOutput then
Write (L, Now, Right, 15);
Write (L, " : " & InstancePath);
Write (L, String'(" : AHB initalised"));
WriteLine(Output, L);
end if;
end procedure DMAInit;
-----------------------------------------------------------------------------
-- AMBA AHB write access
-----------------------------------------------------------------------------
procedure DMAWriteQuiet(
constant Address: in Std_Logic_Vector(31 downto 0);
constant Data: in Std_Logic_Vector(31 downto 0);
signal HCLK: in Std_ULogic;
signal dmai: out dma_in_type;
signal dmao: in dma_out_type;
variable TP: inout Boolean;
constant InstancePath: in String := "DMAWrite";
constant ScreenOutput: in Boolean := False;
constant cBack2Back: in Boolean := False;
constant Size: in Integer := 32) is
variable L: Line;
begin
-- do not synchronise when a back-to-back access is requested
if not cBack2Back then
Synchronise(HCLK);
end if;
dmai.Reset <= '0';
dmai.Address <= Address;
dmai.Request <= '1';
dmai.Burst <= '0';
dmai.Beat <= (others => '0');
dmai.Store <= '1';
dmai.Data <= Data;
if Size=32 then
dmai.Size <= HSIZE32;
elsif Size=16 then
dmai.Size <= HSIZE16;
elsif Size=8 then
dmai.Size <= HSIZE8;
else
report "Unsupported data width"
severity Failure;
end if;
wait for 1 ns;
if dmao.Grant='0' then
while dmao.Grant='0' loop
Synchronise(HCLK, 0 ns);
end loop;
else
Synchronise(HCLK);
end if;
dmai.Reset <= '0';
dmai.Request <= '0';
dmai.Store <= '0';
dmai.Burst <= '0';
dmai.Data <= Data;
loop
Synchronise(HCLK);
while dmao.Ready='0' and dmao.Retry='0' and dmao.Fault='0' loop
Synchronise(HCLK);
end loop;
if dmao.Fault='1' then
if ScreenOutput then
Write (L, Now, Right, 15);
Write (L, " : " & InstancePath);
Write (L, String'(" : AHB write access, address: "));
HWrite(L, Address);
Write (L, String'(" ERROR reponse "));
WriteLine(Output, L);
end if;
TP := False;
dmai.Reset <= '0';
dmai.Address <= (others => '0');
dmai.Data <= (others => '0');
dmai.Request <= '0';
dmai.Store <= '0';
dmai.Burst <= '0';
dmai.Beat <= (others => '0');
dmai.Size <= (others => '0');
Synchronise(HCLK);
Synchronise(HCLK);
exit;
elsif dmao.Ready='1' then
dmai.Reset <= '0';
dmai.Address <= (others => '0');
dmai.Data <= (others => '0');
dmai.Request <= '0';
dmai.Store <= '0';
dmai.Burst <= '0';
dmai.Beat <= (others => '0');
dmai.Size <= (others => '0');
exit;
end if;
if dmao.Retry='1' then
if ScreenOutput then
Write (L, Now, Right, 15);
Write (L, " : " & InstancePath);
Write (L, String'(" : AHB write access, address: "));
HWrite(L, Address);
Write (L, String'(" RETRY/SPLIT reponse "));
WriteLine(Output, L);
end if;
end if;
end loop;
end procedure DMAWriteQuiet;
-----------------------------------------------------------------------------
-- AMBA AHB write access
-----------------------------------------------------------------------------
procedure DMAWrite(
constant Address: in Std_Logic_Vector(31 downto 0);
constant Data: in Std_Logic_Vector(31 downto 0);
signal HCLK: in Std_ULogic;
signal dmai: out dma_in_type;
signal dmao: in dma_out_type;
variable TP: inout Boolean;
constant InstancePath: in String := "DMAWrite";
constant ScreenOutput: in Boolean := False;
constant cBack2Back: in Boolean := False;
constant Size: in Integer := 32) is
variable OK: Boolean := True;
variable L: Line;
begin
DMAWriteQuiet(Address, Data, HCLK, dmai, dmao, OK,
InstancePath, True, cBack2Back, Size);
if ScreenOutput and OK then
Write (L, Now, Right, 15);
Write (L, " : " & InstancePath);
Write (L, String'(" : AHB write access, address: "));
HWrite(L, Address);
Write (L, String'(" : data: "));
HWrite(L, Data);
WriteLine(Output, L);
elsif not OK then
Write (L, Now, Right, 15);
Write (L, " : " & InstancePath);
Write (L, String'(" : AHB write access, address: "));
HWrite(L, Address);
Write (L, String'(" : ## Failed ##"));
WriteLine(Output, L);
TP := False;
end if;
end procedure DMAWrite;
-----------------------------------------------------------------------------
-- AMBA AHB read access
-----------------------------------------------------------------------------
procedure DMAQuiet(
constant Address: in Std_Logic_Vector(31 downto 0);
variable Data: out Std_Logic_Vector(31 downto 0);
signal HCLK: in Std_ULogic;
signal dmai: out dma_in_type;
signal dmao: in dma_out_type;
variable TP: inout Boolean;
constant InstancePath: in String := "DMAQuiet";
constant ScreenOutput: in Boolean := False;
constant cBack2Back: in Boolean := False;
constant Size: in Integer := 32) is
variable L: Line;
begin
-- do not Synchronise when a back-to-back access is requested
if not cBack2Back then
Synchronise(HCLK);
end if;
dmai.Reset <= '0';
dmai.Address <= Address;
dmai.Request <= '1';
dmai.Burst <= '0';
dmai.Beat <= (others => '0');
dmai.Store <= '0';
dmai.Data <= (others => '0');
if Size=32 then
dmai.Size <= HSIZE32;
elsif Size=16 then
dmai.Size <= HSIZE16;
elsif Size=8 then
dmai.Size <= HSIZE8;
else
report "Unsupported data width"
severity Failure;
end if;
wait for 1 ns;
if dmao.Grant='0' then
while dmao.Grant='0' loop
Synchronise(HCLK, 0 ns);
end loop;
else
Synchronise(HCLK);
end if;
dmai.Reset <= '0';
dmai.Data <= (others => '0');
dmai.Request <= '0';
dmai.Store <= '0';
dmai.Burst <= '0';
dmai.Beat <= (others => '0');
loop
Synchronise(HCLK);
while dmao.Ready='0' and dmao.Retry='0' and dmao.Fault='0' loop
Synchronise(HCLK);
end loop;
if dmao.Fault='1' then
if ScreenOutput then
Write (L, Now, Right, 15);
Write (L, " : " & InstancePath);
Write (L, String'(" : AHB read access, address: "));
HWrite(L, Address);
Write (L, String'(" ERROR reponse "));
WriteLine(Output, L);
end if;
TP := False;
dmai.Reset <= '0';
dmai.Address <= (others => '0');
dmai.Data <= (others => '0');
dmai.Request <= '0';
dmai.Store <= '0';
dmai.Burst <= '0';
dmai.Beat <= (others => '0');
dmai.Size <= (others => '0');
Data := (others => 'X');
Synchronise(HCLK);
Synchronise(HCLK);
exit;
elsif dmao.Ready='1' then
Data := dmao.Data;
dmai.Address <= (others => '0');
dmai.Beat <= (others => '0');
dmai.Size <= (others => '0');
exit;
end if;
if dmao.Retry='1' then
if ScreenOutput then
Write (L, Now, Right, 15);
Write (L, " : " & InstancePath);
Write (L, String'(" : AHB read access, address: "));
HWrite(L, Address);
Write (L, String'(" RETRY/SPLIT reponse "));
WriteLine(Output, L);
end if;
end if;
end loop;
end procedure DMAQuiet;
-----------------------------------------------------------------------------
-- AMBA AHB read access
-----------------------------------------------------------------------------
procedure DMARead(
constant Address: in Std_Logic_Vector(31 downto 0);
variable Data: out Std_Logic_Vector(31 downto 0);
signal HCLK: in Std_ULogic;
signal dmai: out dma_in_type;
signal dmao: in dma_out_type;
variable TP: inout Boolean;
constant InstancePath: in String := "DMARead";
constant ScreenOutput: in Boolean := True;
constant cBack2Back: in Boolean := False;
constant Size: in Integer := 32) is
variable OK: Boolean := True;
variable L: Line;
variable Temp: Std_Logic_Vector(31 downto 0);
begin
DMAQuiet(Address, Temp, HCLK, dmai, dmao, OK,
InstancePath, True, cBack2Back, Size);
if ScreenOutput and OK then
Data := Temp;
Write (L, Now, Right, 15);
Write (L, " : " & InstancePath);
Write (L, String'(" : AHB read access, address: "));
HWrite(L, Address);
Write (L, String'(" : data: "));
HWrite(L, Temp);
WriteLine(Output, L);
elsif OK then
Data := Temp;
else
Write (L, Now, Right, 15);
Write (L, " : " & InstancePath);
Write (L, String'(" : AHB read access, address: "));
HWrite(L, Address);
Write (L, String'(" : ## Failed ##"));
WriteLine(Output, L);
Data := (others => '-');
TP := False;
end if;
end procedure DMARead;
-----------------------------------------------------------------------------
-- AMBA AHB read access
-----------------------------------------------------------------------------
procedure DMAComp(
constant Address: in Std_Logic_Vector(31 downto 0);
constant CxData: in Std_Logic_Vector(31 downto 0);
variable RxData: out Std_Logic_Vector(31 downto 0);
signal HCLK: in Std_ULogic;
signal dmai: out dma_in_type;
signal dmao: in dma_out_type;
variable TP: inout Boolean;
constant InstancePath: in String := "DMAComp";
constant ScreenOutput: in Boolean := False;
constant cBack2Back: in Boolean := False;
constant Size: in Integer := 32) is
variable OK: Boolean := True;
variable L: Line;
variable Data: Std_Logic_Vector(31 downto 0);
begin
DMAQuiet(Address, Data, HCLK, dmai, dmao, OK,
InstancePath, True, cBack2Back, Size);
if not OK then
Write (L, Now, Right, 15);
Write (L, " : " & InstancePath);
Write (L, String'(" : AHB read access, address: "));
HWrite(L, Address);
Write (L, String'(" : ## Failed ##"));
WriteLine(Output, L);
TP := False;
RxData := (others => '-');
elsif not Compare(Data, CxData) then
Write (L, Now, Right, 15);
Write (L, " : " & InstancePath);
Write (L, String'(" : AHB read access, address: "));
HWrite(L, Address);
Write (L, String'(" : data: "));
HWrite(L, Data);
Write (L, String'(" : expected: "));
HWrite(L, CxData);
Write (L, String'(" # Error #"));
WriteLine(Output, L);
TP := False;
RxData := Data;
elsif ScreenOutput then
Write(L, Now, Right, 15);
Write(L, " : " & InstancePath);
Write(L, String'(" : AHB read access, address: "));
HWrite(L, Address);
Write(L, String'(" : data: "));
HWrite(L, Data);
WriteLine(Output, L);
RxData := Data;
else
RxData := Data;
end if;
end procedure DMAComp;
-----------------------------------------------------------------------------
-- AMBA AHB write access
-----------------------------------------------------------------------------
procedure DMAWriteQuiet16(
constant Address: in Std_Logic_Vector(31 downto 0);
constant Data: in Std_Logic_Vector(15 downto 0);
signal HCLK: in Std_ULogic;
signal dmai: out dma_in_type;
signal dmao: in dma_out_type;
variable TP: inout Boolean;
constant InstancePath: in String := "DMAWrite16";
constant ScreenOutput: in Boolean := False;
constant cBack2Back: in Boolean := False) is
begin
DMAWriteQuiet(Address, Data & Data, HCLK, dmai, dmao, TP,
InstancePath, ScreenOutput, cBack2Back, 16);
end procedure DMAWriteQuiet16;
-----------------------------------------------------------------------------
-- AMBA AHB write access
-----------------------------------------------------------------------------
procedure DMAWrite16(
constant Address: in Std_Logic_Vector(31 downto 0);
constant Data: in Std_Logic_Vector(15 downto 0);
signal HCLK: in Std_ULogic;
signal dmai: out dma_in_type;
signal dmao: in dma_out_type;
variable TP: inout Boolean;
constant InstancePath: in String := "DMAWrite16";
constant ScreenOutput: in Boolean := False;
constant cBack2Back: in Boolean := False) is
begin
DMAWrite(Address, Data & Data, HCLK, dmai, dmao, TP,
InstancePath, ScreenOutput, cBack2Back, 16);
end procedure DMAWrite16;
-----------------------------------------------------------------------------
-- AMBA AHB read access
-----------------------------------------------------------------------------
procedure DMAQuiet16(
constant Address: in Std_Logic_Vector(31 downto 0);
variable Data: out Std_Logic_Vector(15 downto 0);
signal HCLK: in Std_ULogic;
signal dmai: out dma_in_type;
signal dmao: in dma_out_type;
variable TP: inout Boolean;
constant InstancePath: in String := "DMAQuiet16";
constant ScreenOutput: in Boolean := False;
constant cBack2Back: in Boolean := False) is
variable Tmp: Std_Logic_Vector(31 downto 0);
begin
DMAQuiet(Address, Tmp, HCLK, dmai, dmao, TP,
InstancePath, ScreenOutput, cBack2Back, 16);
if Address(1)='0' then
Data := Tmp(31 downto 16);
else
Data := Tmp(15 downto 0);
end if;
end procedure DMAQuiet16;
-----------------------------------------------------------------------------
-- AMBA AHB read access
-----------------------------------------------------------------------------
procedure DMARead16(
constant Address: in Std_Logic_Vector(31 downto 0);
variable Data: out Std_Logic_Vector(15 downto 0);
signal HCLK: in Std_ULogic;
signal dmai: out dma_in_type;
signal dmao: in dma_out_type;
variable TP: inout Boolean;
constant InstancePath: in String := "DMARead16";
constant ScreenOutput: in Boolean := True;
constant cBack2Back: in Boolean := False) is
variable Tmp: Std_Logic_Vector(31 downto 0);
begin
DMARead(Address, Tmp, HCLK, dmai, dmao, TP,
InstancePath, ScreenOutput, cBack2Back, 16);
if Address(1)='0' then
Data := Tmp(31 downto 16);
else
Data := Tmp(15 downto 0);
end if;
end procedure DMARead16;
-----------------------------------------------------------------------------
-- AMBA AHB read access
-----------------------------------------------------------------------------
procedure DMAComp16(
constant Address: in Std_Logic_Vector(31 downto 0);
constant CxData: in Std_Logic_Vector(15 downto 0);
variable RxData: out Std_Logic_Vector(15 downto 0);
signal HCLK: in Std_ULogic;
signal dmai: out dma_in_type;
signal dmao: in dma_out_type;
variable TP: inout Boolean;
constant InstancePath: in String := "DMAComp16";
constant ScreenOutput: in Boolean := False;
constant cBack2Back: in Boolean := False) is
variable TmpRx: Std_Logic_Vector(31 downto 0);
variable TmpCx: Std_Logic_Vector(31 downto 0);
begin
if Address(1)='0' then
TmpCx := CxData & "----------------";
else
TmpCx := "----------------" & CxData;
end if;
DMAComp(Address, TmpCx, TmpRx, HCLK, dmai, dmao, TP,
InstancePath, ScreenOutput, cBack2Back, 16);
if Address(1)='0' then
RxData := TmpRx(31 downto 16);
else
RxData := TmpRx(15 downto 0);
end if;
end procedure DMAComp16;
-----------------------------------------------------------------------------
-- AMBA AHB write access
-----------------------------------------------------------------------------
procedure DMAWriteQuiet8(
constant Address: in Std_Logic_Vector(31 downto 0);
constant Data: in Std_Logic_Vector( 7 downto 0);
signal HCLK: in Std_ULogic;
signal dmai: out dma_in_type;
signal dmao: in dma_out_type;
variable TP: inout Boolean;
constant InstancePath: in String := "DMAWrite8";
constant ScreenOutput: in Boolean := False;
constant cBack2Back: in Boolean := False) is
begin
DMAWriteQuiet(Address, Data & Data & Data & Data, HCLK, dmai, dmao, TP,
InstancePath, ScreenOutput, cBack2Back, 8);
end procedure DMAWriteQuiet8;
-----------------------------------------------------------------------------
-- AMBA AHB write access
-----------------------------------------------------------------------------
procedure DMAWrite8(
constant Address: in Std_Logic_Vector(31 downto 0);
constant Data: in Std_Logic_Vector( 7 downto 0);
signal HCLK: in Std_ULogic;
signal dmai: out dma_in_type;
signal dmao: in dma_out_type;
variable TP: inout Boolean;
constant InstancePath: in String := "DMAWrite8";
constant ScreenOutput: in Boolean := False;
constant cBack2Back: in Boolean := False) is
begin
DMAWrite(Address, Data & Data & Data & Data, HCLK, dmai, dmao, TP,
InstancePath, ScreenOutput, cBack2Back, 8);
end procedure DMAWrite8;
-----------------------------------------------------------------------------
-- AMBA AHB read access
-----------------------------------------------------------------------------
procedure DMAQuiet8(
constant Address: in Std_Logic_Vector(31 downto 0);
variable Data: out Std_Logic_Vector( 7 downto 0);
signal HCLK: in Std_ULogic;
signal dmai: out dma_in_type;
signal dmao: in dma_out_type;
variable TP: inout Boolean;
constant InstancePath: in String := "DMAQuiet8";
constant ScreenOutput: in Boolean := False;
constant cBack2Back: in Boolean := False) is
variable Tmp: Std_Logic_Vector(31 downto 0);
begin
DMAQuiet(Address, Tmp, HCLK, dmai, dmao, TP,
InstancePath, ScreenOutput, cBack2Back, 8);
if Address(1 downto 0)="00" then
Data := Tmp(31 downto 24);
elsif Address(1 downto 0)="01" then
Data := Tmp(23 downto 16);
elsif Address(1 downto 0)="10" then
Data := Tmp(15 downto 8);
else
Data := Tmp( 7 downto 0);
end if;
end procedure DMAQuiet8;
-----------------------------------------------------------------------------
-- AMBA AHB read access
-----------------------------------------------------------------------------
procedure DMARead8(
constant Address: in Std_Logic_Vector(31 downto 0);
variable Data: out Std_Logic_Vector( 7 downto 0);
signal HCLK: in Std_ULogic;
signal dmai: out dma_in_type;
signal dmao: in dma_out_type;
variable TP: inout Boolean;
constant InstancePath: in String := "DMARead8";
constant ScreenOutput: in Boolean := True;
constant cBack2Back: in Boolean := False) is
variable Tmp: Std_Logic_Vector(31 downto 0);
begin
DMARead(Address, Tmp, HCLK, dmai, dmao, TP,
InstancePath, ScreenOutput, cBack2Back, 8);
if Address(1 downto 0)="00" then
Data := Tmp(31 downto 24);
elsif Address(1 downto 0)="01" then
Data := Tmp(23 downto 16);
elsif Address(1 downto 0)="10" then
Data := Tmp(15 downto 8);
else
Data := Tmp( 7 downto 0);
end if;
end procedure DMARead8;
-----------------------------------------------------------------------------
-- AMBA AHB read access
-----------------------------------------------------------------------------
procedure DMAComp8(
constant Address: in Std_Logic_Vector(31 downto 0);
constant CxData: in Std_Logic_Vector( 7 downto 0);
variable RxData: out Std_Logic_Vector( 7 downto 0);
signal HCLK: in Std_ULogic;
signal dmai: out dma_in_type;
signal dmao: in dma_out_type;
variable TP: inout Boolean;
constant InstancePath: in String := "DMAComp8";
constant ScreenOutput: in Boolean := False;
constant cBack2Back: in Boolean := False) is
variable TmpRx: Std_Logic_Vector(31 downto 0);
variable TmpCx: Std_Logic_Vector(31 downto 0);
begin
if Address(1 downto 0)="00" then
TmpCx := CxData & "--------" & "--------" & "--------";
elsif Address(1 downto 0)="01" then
TmpCx := "--------" & CxData & "--------" & "--------";
elsif Address(1 downto 0)="10" then
TmpCx := "--------" & "--------" & CxData & "--------";
else
TmpCx := "--------" & "--------" & "--------" & CxData;
end if;
DMAComp(Address, TmpCx, TmpRx, HCLK, dmai, dmao, TP,
InstancePath, ScreenOutput, cBack2Back, 8);
if Address(1 downto 0)="00" then
RxData := TmpRx(31 downto 24);
elsif Address(1 downto 0)="01" then
RxData := TmpRx(23 downto 16);
elsif Address(1 downto 0)="10" then
RxData := TmpRx(15 downto 8);
else
RxData := TmpRx( 7 downto 0);
end if;
end procedure DMAComp8;
-----------------------------------------------------------------------------
-- AMBA AHB write access
-----------------------------------------------------------------------------
procedure DMAWriteQuietBurst(
constant Address: in Std_Logic_Vector(31 downto 0);
constant Data: in Data_Vector;
signal HCLK: in Std_ULogic;
signal dmai: out dma_in_type;
signal dmao: in dma_out_type;
variable TP: inout Boolean;
constant InstancePath: in String := "DMAWrite";
constant ScreenOutput: in Boolean := False;
constant cBack2Back: in Boolean := False;
constant Size: in Integer := 32;
constant Beat: in Integer := 1) is
variable L: Line;
constant Count: Integer := Data'Length*WordSize/Size;
variable GCount: Integer := Data'Length*WordSize/Size;
variable DCount: Integer := 1;
begin
-- do not synchronise when a back-to-back access is requested
if not cBack2Back then
Synchronise(HCLK);
end if;
dmai.Reset <= '0';
dmai.Address <= Address;
dmai.Data <= (others => '0');
dmai.Request <= '1';
dmai.Store <= '1';
if Count > 1 then
dmai.Burst <= '1';
else
dmai.Burst <= '0';
end if;
if Beat=1 then
dmai.Beat <= HINCR;
elsif Beat=4 then
dmai.Beat <= HINCR4;
elsif Beat=8 then
dmai.Beat <= HINCR8;
elsif Beat=16 then
dmai.Beat <= HINCR16;
else
report "Unsupported beat"
severity Failure;
end if;
if Size=32 then
dmai.Size <= HSIZE32;
elsif Size=16 then
dmai.Size <= HSIZE16;
elsif Size=8 then
dmai.Size <= HSIZE8;
else
report "Unsupported data width"
severity Failure;
end if;
-- wait for first grant, indicating start of accesses
wait for 1 ns;
if dmao.Grant='0' then
while dmao.Grant='0' loop
Synchronise(HCLK);
end loop;
Synchronise(HCLK);
else
Synchronise(HCLK);
end if;
GCount := GCount-1;
-- first data
if Size=32 then
dmai.Data <= Data(0);
elsif Size=16 then
dmai.Data <= Data(0)(31 downto 16) & Data(0)(31 downto 16);
elsif Size=8 then
dmai.Data <= Data(0)(31 downto 24) & Data(0)(31 downto 24) &
Data(0)(31 downto 24) & Data(0)(31 downto 24);
end if;
loop
-- remove request when all grants received
if dmao.Grant='1' then
if GCount=0 then
dmai.Reset <= '0';
dmai.Request <= '0';
dmai.Store <= '0';
dmai.Burst <= '0';
else
GCount := GCount-1;
end if;
end if;
Synchronise(HCLK, 0 ns);
while dmao.Grant='0' and dmao.Ready='0' and dmao.OKAY='0' and dmao.Retry='0' and dmao.Fault='0' loop
Synchronise(HCLK, 0 ns);
end loop;
if dmao.Fault='1' then
if ScreenOutput then
Write (L, Now, Right, 15);
Write (L, " : " & InstancePath);
Write (L, String'(" : AHB write access, address: "));
HWrite(L, Conv_Std_Logic_Vector(Conv_Integer(Address)+(DCount-1)*Beat*Size/8, 32));
Write (L, String'(" ERROR response "));
WriteLine(Output, L);
end if;
TP := False;
dmai.Reset <= '0';
dmai.Address <= (others => '0');
dmai.Data <= (others => '0');
dmai.Request <= '0';
dmai.Store <= '0';
dmai.Burst <= '0';
dmai.Beat <= (others => '0');
dmai.Size <= (others => '0');
Synchronise(HCLK, 0 ns);
Synchronise(HCLK, 0 ns);
exit;
elsif dmao.OKAY='1' then
-- for each OKAY, provide new data
if DCount=Count then
dmai.Address <= (others => '0');
dmai.Beat <= (others => '0');
dmai.Size <= (others => '0');
Synchronise(HCLK, 0 ns);
while dmao.Ready='0' loop
Synchronise(HCLK, 0 ns);
end loop;
exit;
else
if Size=32 then
dmai.Data <= Data(DCount);
elsif Size=16 then
dmai.Data <= Data(DCount/2)((31-16*(DCount mod 2)) downto (16-(16*(DCount mod 2)))) &
Data(DCount/2)((31-16*(DCount mod 2)) downto (16-(16*(DCount mod 2))));
elsif Size=8 then
dmai.Data <= Data(DCount/4)((31-8*(DCount mod 4)) downto (24-(8*(DCount mod 4)))) &
Data(DCount/4)((31-8*(DCount mod 4)) downto (24-(8*(DCount mod 4)))) &
Data(DCount/4)((31-8*(DCount mod 4)) downto (24-(8*(DCount mod 4)))) &
Data(DCount/4)((31-8*(DCount mod 4)) downto (24-(8*(DCount mod 4))));
end if;
DCount := DCount+1;
end if;
end if;
if dmao.Retry='1' then
if ScreenOutput then
Write (L, Now, Right, 15);
Write (L, " : " & InstancePath);
Write (L, String'(" : AHB write access, address: "));
HWrite(L, Conv_Std_Logic_Vector(Conv_Integer(Address)+(DCount-1)*Beat*Size/8, 32));
Write (L, String'(" RETRY/SPLIT response "));
WriteLine(Output, L);
end if;
end if;
end loop;
end procedure DMAWriteQuietBurst;
-----------------------------------------------------------------------------
-- AMBA AHB write access
-----------------------------------------------------------------------------
procedure DMAWriteBurst(
constant Address: in Std_Logic_Vector(31 downto 0);
constant Data: in Data_Vector;
signal HCLK: in Std_ULogic;
signal dmai: out dma_in_type;
signal dmao: in dma_out_type;
variable TP: inout Boolean;
constant InstancePath: in String := "DMAWrite";
constant ScreenOutput: in Boolean := False;
constant cBack2Back: in Boolean := False;
constant Size: in Integer := 32;
constant Beat: in Integer := 1) is
variable OK: Boolean := True;
variable L: Line;
begin
DMAWriteQuietBurst(Address, Data, HCLK, dmai, dmao, OK,
InstancePath, ScreenOutput, cBack2Back, Size, Beat);
if ScreenOutput and OK then
for i in 0 to Data'Length-1 loop
Write (L, Now, Right, 15);
Write (L, " : " & InstancePath);
Write (L, String'(" : AHB write access, address: "));
HWrite(L, Conv_Std_Logic_Vector(Conv_Integer(Address)+i*Beat*Size/8, 32));
Write (L, String'(" : data: "));
HWrite(L, Data(i));
WriteLine(Output, L);
end loop;
elsif not OK then
Write (L, Now, Right, 15);
Write (L, " : " & InstancePath);
Write (L, String'(" : AHB write access, address: "));
HWrite(L, Address);
Write (L, String'(" : ## Failed ##"));
WriteLine(Output, L);
TP := False;
end if;
end procedure DMAWriteBurst;
-----------------------------------------------------------------------------
-- AMBA AHB read access
-----------------------------------------------------------------------------
procedure DMAQuietBurst(
constant Address: in Std_Logic_Vector(31 downto 0);
variable Data: out Data_Vector;
signal HCLK: in Std_ULogic;
signal dmai: out dma_in_type;
signal dmao: in dma_out_type;
variable TP: inout Boolean;
constant InstancePath: in String := "DMAQuiet";
constant ScreenOutput: in Boolean := False;
constant cBack2Back: in Boolean := False;
constant Size: in Integer := 32;
constant Beat: in Integer := 1) is
variable L: Line;
constant Count: Integer := Data'Length*WordSize/Size;
variable GCount: Integer := Data'Length*WordSize/Size;
variable DCount: Integer := 1;
variable DataPart: Integer := 0;
begin
-- do not Synchronise when a back-to-back access is requested
if not cBack2Back then
Synchronise(HCLK);
end if;
dmai.Reset <= '0';
dmai.Address <= Address;
dmai.Data <= (others => '0');
dmai.Request <= '1';
dmai.Store <= '0';
if Count > 1 then
dmai.Burst <= '1';
else
dmai.Burst <= '0';
end if;
if Beat=1 then
dmai.Beat <= HINCR;
elsif Beat=4 then
dmai.Beat <= HINCR4;
elsif Beat=8 then
dmai.Beat <= HINCR8;
elsif Beat=16 then
dmai.Beat <= HINCR16;
else
report "Unsupported beat"
severity Failure;
end if;
if Size=32 then
dmai.Size <= HSIZE32;
elsif Size=16 then
dmai.Size <= HSIZE16;
if Address(1 downto 0) = "00" then
DataPart := 0;
else
DataPart := 1;
end if;
elsif Size=8 then
dmai.Size <= HSIZE8;
if Address(1 downto 0) = "00" then
DataPart := 0;
elsif Address(1 downto 0) = "01" then
DataPart := 1;
elsif Address(1 downto 0) = "10" then
DataPart := 2;
else
DataPart := 3;
end if;
else
report "Unsupported data width"
severity Failure;
end if;
-- wait for first grant, indicating start of accesses
wait for 1 ns;
if dmao.Grant='0' then
while dmao.Grant='0' loop
Synchronise(HCLK);
end loop;
Synchronise(HCLK);
else
Synchronise(HCLK);
end if;
GCount := GCount-1;
loop
-- remove request when all grants received
if dmao.Grant='1' then
if GCount=0 then
dmai.Reset <= '0';
dmai.Data <= (others => '0');
dmai.Request <= '0';
dmai.Store <= '0';
dmai.Burst <= '0';
else
GCount := GCount-1;
end if;
end if;
Synchronise(HCLK);
while dmao.Grant='0' and dmao.Ready='0' and dmao.Retry='0' and dmao.Fault='0' loop
Synchronise(HCLK);
end loop;
if dmao.Fault='1' then
if ScreenOutput then
Write (L, Now, Right, 15);
Write (L, " : " & InstancePath);
Write (L, String'(" : AHB read access, address: "));
HWrite(L, Conv_Std_Logic_Vector(Conv_Integer(Address)+(DCount-1)*Beat*Size/8, 32));
Write (L, String'(" ERROR response"));
WriteLine(Output, L);
end if;
TP := False;
dmai.Reset <= '0';
dmai.Address <= (others => '0');
dmai.Data <= (others => '0');
dmai.Request <= '0';
dmai.Store <= '0';
dmai.Burst <= '0';
dmai.Beat <= (others => '0');
dmai.Size <= (others => '0');
Synchronise(HCLK);
Synchronise(HCLK);
exit;
elsif dmao.Ready='1' then
-- for each READY, store data
if Size=32 then
Data(DCount-1) := dmao.Data;
elsif Size=16 then
Data((DCount-1)/2)((31-16*((DCount-1) mod 2)) downto (16-(16*((DCount-1) mod 2)))) :=
dmao.Data((31-16*DataPart) downto (16-16*DataPart));
DataPart := (DataPart + 1) mod 2;
elsif Size=8 then
Data((DCount-1)/4)((31-8*((DCount-1) mod 4)) downto (24-(8*((DCount-1) mod 4)))) :=
dmao.Data((31-8*DataPart) downto (24-8*DataPart));
DataPart := (DataPart + 1) mod 4;
end if;
if DCount=Count then
dmai.Address <= (others => '0');
dmai.Beat <= (others => '0');
dmai.Size <= (others => '0');
exit;
else
DCount := DCount+1;
end if;
end if;
if dmao.Retry='1' then
if ScreenOutput then
Write (L, Now, Right, 15);
Write (L, " : " & InstancePath);
Write (L, String'(" : AHB read access, address: "));
HWrite(L, Conv_Std_Logic_Vector(Conv_Integer(Address)+(DCount-1)*Beat*Size/8, 32));
Write (L, String'(" RETRY/SPLIT response "));
WriteLine(Output, L);
end if;
end if;
end loop;
end procedure DMAQuietBurst;
-----------------------------------------------------------------------------
-- AMBA AHB read access
-----------------------------------------------------------------------------
procedure DMAReadBurst(
constant Address: in Std_Logic_Vector(31 downto 0);
variable Data: out Data_Vector;
signal HCLK: in Std_ULogic;
signal dmai: out dma_in_type;
signal dmao: in dma_out_type;
variable TP: inout Boolean;
constant InstancePath: in String := "DMARead";
constant ScreenOutput: in Boolean := True;
constant cBack2Back: in Boolean := False;
constant Size: in Integer := 32;
constant Beat: in Integer := 1) is
variable OK: Boolean := True;
variable L: Line;
variable Temp: Data_Vector(0 to Data'Length-1);
begin
DMAQuietBurst(Address, Temp, HCLK, dmai, dmao, OK,
InstancePath, ScreenOutput, cBack2Back, Size, Beat);
if ScreenOutput and OK then
Data := Temp;
for i in 0 to Data'Length-1 loop
Write (L, Now, Right, 15);
Write (L, " : " & InstancePath);
Write (L, String'(" : AHB read access, address: "));
HWrite(L, Conv_Std_Logic_Vector(Conv_Integer(Address)+i*Beat*Size/8, 32));
Write (L, String'(" : data: "));
HWrite(L, Temp(i));
WriteLine(Output, L);
end loop;
elsif OK then
Data := Temp;
else
Write (L, Now, Right, 15);
Write (L, " : " & InstancePath);
Write (L, String'(" : AHB read access, address: "));
HWrite(L, Address);
Write (L, String'(" : ## Failed ##"));
WriteLine(Output, L);
Temp := (others => (others => '-'));
Data := Temp;
TP := False;
end if;
end procedure DMAReadBurst;
-----------------------------------------------------------------------------
-- AMBA AHB read access
-----------------------------------------------------------------------------
procedure DMACompBurst(
constant Address: in Std_Logic_Vector(31 downto 0);
variable CxData: in Data_Vector;
variable RxData: out Data_Vector;
signal HCLK: in Std_ULogic;
signal dmai: out dma_in_type;
signal dmao: in dma_out_type;
variable TP: inout Boolean;
constant InstancePath: in String := "DMAComp";
constant ScreenOutput: in Boolean := False;
constant cBack2Back: in Boolean := False;
constant Size: in Integer := 32;
constant Beat: in Integer := 1) is
variable OK: Boolean := True;
variable L: Line;
variable Data: Data_Vector(0 to CxData'Length-1);
begin
DMAQuietBurst(Address, Data, HCLK, dmai, dmao, OK,
InstancePath, ScreenOutput, cBack2Back, Size, Beat);
if not OK then
Write (L, Now, Right, 15);
Write (L, " : " & InstancePath);
Write (L, String'(" : AHB read access, address: "));
HWrite(L, Address);
Write (L, String'(" : ## Failed ##"));
WriteLine(Output, L);
TP := False;
Data := (others => (others => '-'));
RxData := Data;
else
for i in 0 to Data'Length-1 loop
if not Compare(Data(i), CxData(i)) then
Write(L, Now, Right, 15);
Write(L, " : " & InstancePath);
Write(L, String'(" : AHB read access, address: "));
HWrite(L, Conv_Std_Logic_Vector(Conv_Integer(Address)+i*Beat*Size/8, 32));
Write(L, String'(" : data: "));
HWrite(L, Data(i));
Write(L, String'(" : expected: "));
HWrite(L, CxData(i));
Write(L, String'(" # Error #"));
WriteLine(Output, L);
TP := False;
elsif ScreenOutput then
Write(L, Now, Right, 15);
Write(L, " : " & InstancePath);
Write(L, String'(" : AHB read access, address: "));
HWrite(L, Conv_Std_Logic_Vector(Conv_Integer(Address)+i*Beat*Size/8, 32));
Write(L, String'(" : data: "));
HWrite(L, Data(i));
WriteLine(Output, L);
end if;
end loop;
RxData := Data;
end if;
end procedure DMACompBurst;
end package body DMA2AHB_TestPackage; --======================================--
| mit | e159ca51b677a72dd6e2a61ffeb63c97 | 0.445952 | 4.721066 | false | false | false | false |
pcrost/gen-util | util.vhd | 1 | 5,935 | -------------------------------------------------------------------------------
-- (C) P. Crosthwaite, University of Queensland (2011)
--This library is free software; you can redistribute it and/or
--modify it under the terms of the GNU Lesser General Public
--License as published by the Free Software Foundation; either
--version 3.0 of the License, or (at your option) any later version.
--This library is distributed in the hope that it will be useful,
--but WITHOUT ANY WARRANTY; without even the implied warranty of
--MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
--Lesser General Public License for more details.
--You should have received a copy of the GNU Lesser General Public
--License along with this library.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
package util is
--arrays of primative types
type BOOL_ARRAY is array(natural range <>) of boolean;
--TODO: move to a another util file
type INT_ARRAY is array(natural range <>) of integer;
--determine if an int array contains an element. only valid with 0 based arrays
function util_int_array_contains (a : INT_ARRAY; e : integer) return boolean;
--return the index of the first occurance of a particular element in an int array
--onyl valid with 0 based arrays
function util_int_array_index_of(a : INT_ARRAY; e : integer) return integer;
--determine if two int arrays are equal. false on length mismatch
function util_int_array_equals(a : INT_ARRAY; b : INT_ARRAY) return boolean;
--equivalents of (? :) operator in c, for various types
function util_select_boolean(c : boolean; t_val : boolean; f_val : boolean) return boolean;
function util_select_int(c : boolean; t_val : integer; f_val : integer) return integer;
function util_select_sl(c : boolean; t_val : std_logic; f_val : std_logic) return std_logic;
function util_select_slv(c : boolean; t_val : std_logic_vector; f_val : std_logic_vector) return std_logic_vector;
function util_select_str(c : boolean; t_val : string; f_val : string) return string;
--bundle a clock and reset together
type GCR is record
clk : std_logic;
rst : std_logic;
end record;
--get the base 2 log of an integer (only guaranteed correct for powers of two)
--TODO: merge this with util_length_req
function log2 (n : integer) return integer;
--convert a boolean to a std logic (true = 1, false = 0)
function conv_std_logic (b : boolean) return std_logic;
--convert a boolean to an integer (0 or 1)
function conv_bool_to_integer (b : boolean) return integer;
function roof_div (a : integer; b : integer) return integer;
function util_max_int(a : integer; b : integer) return integer;
function util_min_int(a : integer; b : integer) return integer;
function util_dc_or(a : std_logic; b : std_logic) return std_logic;
-- Forces the integer to a power of 2, the next power of 2 higher than or equal to a
function util_force_pow2(a : integer) return integer;
end util;
package body util is
function util_select_boolean(c : boolean; t_val : boolean; f_val : boolean) return boolean is begin
if (c) then return t_val; else return f_val; end if;
end;
function util_select_int(c : boolean; t_val : integer; f_val : integer) return integer is begin
if (c) then return t_val; else return f_val; end if;
end;
function util_select_slv(c : boolean; t_val : std_logic_vector; f_val : std_logic_vector) return std_logic_vector is begin
if (c) then return t_val; else return f_val; end if;
end;
function util_select_str(c : boolean; t_val : string; f_val : string) return string is begin
if (c) then return t_val; else return f_val; end if;
end;
function util_select_sl(c : boolean; t_val : std_logic; f_val : std_logic) return std_logic is begin
if (c) then return t_val; else return f_val; end if;
end;
function log2 (n : integer) return integer is
variable v : integer;
variable ret : integer;
begin
v := n;
ret := 0;
while (v > 1) loop
ret := ret + 1;
v := v / 2;
end loop;
return ret;
end function;
function conv_std_logic (b : boolean) return std_logic is begin
return util_select_sl(b, '1', '0');
end function;
function conv_bool_to_integer (b : boolean) return integer is begin
return util_select_int(b, 1, 0);
end function;
function util_int_array_contains (a : INT_ARRAY; e : integer) return boolean is begin
for I in a'range loop
if (a(I) = e) then return true; end if;
end loop;
return false;
end function;
function util_int_array_index_of(a : INT_ARRAY; e : integer) return integer is begin
for I in a'range loop
if (a(I) = e) then return I; end if;
end loop;
return a'length;
end function;
function util_int_array_equals(a : INT_ARRAY; b : INT_ARRAY) return boolean is begin
if (a'length /= b'length) then return false; end if;
for I in a'range loop
if (a(I) /= b(I)) then return false; end if;
end loop;
return true;
end function;
function roof_div (a : integer; b : integer) return integer is begin
if ((a mod b) = 0) then
return a/b;
else
return a/b+1;
end if;
end function;
function util_max_int(a : integer; b : integer) return integer is begin
return util_select_int(a > b, a, b);
end function;
function util_min_int(a : integer; b : integer) return integer is begin
return util_select_int(a < b, a, b);
end function;
function util_dc_or(a : std_logic; b : std_logic) return std_logic is begin
if (a /= '0' and a /= '1') then
return b;
elsif (b /='0' and b /= '1') then
return a;
else
return (a or b);
end if;
end function;
function util_force_pow2(a : integer) return integer is
variable ret : integer;
begin
ret := 2;
while (ret < a) loop
ret := ret * 2;
end loop;
return ret;
end function;
end util;
| lgpl-3.0 | f5b563b49b16d9f5663763bd72014d5f | 0.673799 | 3.218547 | false | false | false | false |
lxp32/lxp32-cpu | verify/lxp32/src/platform/program_ram.vhd | 1 | 3,522 | ---------------------------------------------------------------------
-- Program RAM
--
-- Part of the LXP32 test platform
--
-- Copyright (c) 2016 by Alex I. Kuznetsov
--
-- Program RAM for the LXP32 test platform. Has two interfaces:
-- WISHBONE (for data access) and LLI (for LXP32 instruction bus).
-- Optionally performs throttling.
--
-- Note: regardless of whether this description is synthesizable,
-- it was designed exclusively for simulation purposes.
---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.common_pkg.all;
entity program_ram is
generic(
THROTTLE: boolean
);
port(
clk_i: in std_logic;
rst_i: in std_logic;
wbs_cyc_i: in std_logic;
wbs_stb_i: in std_logic;
wbs_we_i: in std_logic;
wbs_sel_i: in std_logic_vector(3 downto 0);
wbs_ack_o: out std_logic;
wbs_adr_i: in std_logic_vector(27 downto 2);
wbs_dat_i: in std_logic_vector(31 downto 0);
wbs_dat_o: out std_logic_vector(31 downto 0);
lli_re_i: in std_logic;
lli_adr_i: in std_logic_vector(29 downto 0);
lli_dat_o: out std_logic_vector(31 downto 0);
lli_busy_o: out std_logic
);
end entity;
architecture rtl of program_ram is
signal ram_a_we: std_logic_vector(3 downto 0);
signal ram_a_rdata: std_logic_vector(31 downto 0);
signal ram_b_re: std_logic;
signal ram_b_rdata: std_logic_vector(31 downto 0);
signal ack_write: std_logic;
signal ack_read: std_logic;
signal prbs: std_logic;
signal lli_busy: std_logic:='0';
begin
-- The total memory size is 16384 words, i.e. 64K bytes
gen_dprams: for i in 3 downto 0 generate
generic_dpram_inst: entity work.generic_dpram(rtl)
generic map(
DATA_WIDTH=>8,
ADDR_WIDTH=>14,
SIZE=>16384,
MODE=>"DONTCARE"
)
port map(
clka_i=>clk_i,
cea_i=>'1',
wea_i=>ram_a_we(i),
addra_i=>wbs_adr_i(15 downto 2),
da_i=>wbs_dat_i(i*8+7 downto i*8),
da_o=>ram_a_rdata(i*8+7 downto i*8),
clkb_i=>clk_i,
ceb_i=>ram_b_re,
addrb_i=>lli_adr_i(13 downto 0),
db_o=>ram_b_rdata(i*8+7 downto i*8)
);
end generate;
-- WISHBONE interface
gen_ram_a_we: for i in 3 downto 0 generate
ram_a_we(i)<='1' when wbs_cyc_i='1' and wbs_stb_i='1' and wbs_we_i='1'
and wbs_sel_i(i)='1' and wbs_adr_i(27 downto 16)="000000000000" else '0';
end generate;
process (clk_i) is
begin
if rising_edge(clk_i) then
ack_read<=wbs_cyc_i and wbs_stb_i and not wbs_we_i and not ack_read;
end if;
end process;
ack_write<=wbs_cyc_i and wbs_stb_i and wbs_we_i;
wbs_ack_o<=ack_read or ack_write;
wbs_dat_o<=ram_a_rdata;
-- Low Latency Interface (with optional pseudo-random throttling)
process (clk_i) is
begin
if rising_edge(clk_i) then
assert lli_re_i='0' or lli_adr_i(lli_adr_i'high downto 14)=X"0000"
report "Attempted to fetch instruction from a non-existent address 0x"&
hex_string(lli_adr_i&"00")
severity failure;
end if;
end process;
gen_throttling: if THROTTLE generate
throttle_inst: entity work.scrambler(rtl)
generic map(TAP1=>9,TAP2=>11)
port map(clk_i=>clk_i,rst_i=>rst_i,ce_i=>'1',d_o=>prbs);
end generate;
gen_no_throttling: if not THROTTLE generate
prbs<='0';
end generate;
process (clk_i) is
begin
if rising_edge(clk_i) then
if rst_i='1' then
lli_busy<='0';
elsif prbs='1' and lli_re_i='1' then
lli_busy<='1';
elsif prbs='0' then
lli_busy<='0';
end if;
end if;
end process;
ram_b_re<=lli_re_i and not lli_busy;
lli_busy_o<=lli_busy;
lli_dat_o<=ram_b_rdata when lli_busy='0' else (others=>'-');
end architecture;
| mit | b3a6ff5de3729fd6f9316f4a614f7285 | 0.646508 | 2.650113 | false | false | false | false |
impedimentToProgress/UCI-BlueChip | AttackFiles/Attacks/privEsc/lib/gaisler/uart/ahbuart.vhd | 2 | 2,599 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: ahbuart
-- File: ahbuart.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: UART with AHB master interface
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
library gaisler;
use gaisler.misc.all;
use gaisler.uart.all;
use gaisler.libdcom.all;
entity ahbuart is
generic (
hindex : integer := 0;
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#fff#
);
port (
rst : in std_ulogic;
clk : in std_ulogic;
uarti : in uart_in_type;
uarto : out uart_out_type;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
ahbi : in ahb_mst_in_type;
ahbo : out ahb_mst_out_type );
end;
architecture struct of ahbuart is
constant REVISION : integer := 0;
signal dmai : ahb_dma_in_type;
signal dmao : ahb_dma_out_type;
signal duarti : dcom_uart_in_type;
signal duarto : dcom_uart_out_type;
begin
ahbmst0 : ahbmst
generic map (hindex => hindex, venid => VENDOR_GAISLER, devid => GAISLER_AHBUART)
port map (rst, clk, dmai, dmao, ahbi, ahbo);
dcom_uart0 : dcom_uart generic map (pindex, paddr, pmask)
port map (rst, clk, uarti, uarto, apbi, apbo, duarti, duarto);
dcom0 : dcom port map (rst, clk, dmai, dmao, duarti, duarto, ahbi);
-- pragma translate_off
bootmsg : report_version
generic map ("ahbuart" & tost(pindex) &
": AHB Debug UART rev " & tost(REVISION));
-- pragma translate_on
end;
| mit | a1b473835dc80bec8bbcbd1a1897c75f | 0.612543 | 3.799708 | false | false | false | false |
impedimentToProgress/UCI-BlueChip | AttackFiles/Attacks/memAttack/lib/gaisler/leon3/leon3s.vhd | 1 | 7,863 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: leon3s
-- File: leon3s.vhd
-- Author: Jiri Gaisler, Edvin Catovic, Gaisler Research
-- Description: Top-level LEON3 component
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
library gaisler;
library techmap;
use techmap.gencomp.all;
use gaisler.leon3.all;
use gaisler.libiu.all;
use gaisler.libcache.all;
use gaisler.libproc3.all;
use gaisler.arith.all;
--library fpu;
--use fpu.libfpu.all;
entity leon3s is
generic (
hindex : integer := 0;
fabtech : integer range 0 to NTECH := DEFFABTECH;
memtech : integer range 0 to NTECH := DEFMEMTECH;
nwindows : integer range 2 to 32 := 8;
dsu : integer range 0 to 1 := 0;
fpu : integer range 0 to 31 := 0;
v8 : integer range 0 to 63 := 0;
cp : integer range 0 to 1 := 0;
mac : integer range 0 to 1 := 0;
pclow : integer range 0 to 2 := 2;
notag : integer range 0 to 1 := 0;
nwp : integer range 0 to 4 := 0;
icen : integer range 0 to 1 := 0;
irepl : integer range 0 to 2 := 2;
isets : integer range 1 to 4 := 1;
ilinesize : integer range 4 to 8 := 4;
isetsize : integer range 1 to 256 := 1;
isetlock : integer range 0 to 1 := 0;
dcen : integer range 0 to 1 := 0;
drepl : integer range 0 to 2 := 2;
dsets : integer range 1 to 4 := 1;
dlinesize : integer range 4 to 8 := 4;
dsetsize : integer range 1 to 256 := 1;
dsetlock : integer range 0 to 1 := 0;
dsnoop : integer range 0 to 6 := 0;
ilram : integer range 0 to 1 := 0;
ilramsize : integer range 1 to 512 := 1;
ilramstart : integer range 0 to 255 := 16#8e#;
dlram : integer range 0 to 1 := 0;
dlramsize : integer range 1 to 512 := 1;
dlramstart : integer range 0 to 255 := 16#8f#;
mmuen : integer range 0 to 1 := 0;
itlbnum : integer range 2 to 64 := 8;
dtlbnum : integer range 2 to 64 := 8;
tlb_type : integer range 0 to 3 := 1;
tlb_rep : integer range 0 to 1 := 0;
lddel : integer range 1 to 2 := 2;
disas : integer range 0 to 2 := 0;
tbuf : integer range 0 to 64 := 0;
pwd : integer range 0 to 2 := 2; -- power-down
svt : integer range 0 to 1 := 1; -- single vector trapping
rstaddr : integer := 0;
smp : integer range 0 to 15 := 0; -- support SMP systems
cached : integer := 0; -- cacheability table
scantest : integer := 0
);
port (
clk : in std_ulogic;
rstn : in std_ulogic;
ahbi : in ahb_mst_in_type;
ahbo : out ahb_mst_out_type;
ahbsi : in ahb_slv_in_type;
ahbso : in ahb_slv_out_vector;
irqi : in l3_irq_in_type;
irqo : out l3_irq_out_type;
dbgi : in l3_debug_in_type;
dbgo : out l3_debug_out_type
);
end;
architecture rtl of leon3s is
constant IRFBITS : integer range 6 to 10 := log2(NWINDOWS+1) + 4;
constant IREGNUM : integer := NWINDOWS * 16 + 8;
signal holdn : std_logic;
signal rfi : iregfile_in_type;
signal rfo : iregfile_out_type;
signal crami : cram_in_type;
signal cramo : cram_out_type;
signal tbi : tracebuf_in_type;
signal tbo : tracebuf_out_type;
signal rst : std_ulogic;
signal fpi : fpc_in_type;
signal fpo : fpc_out_type;
signal cpi : fpc_in_type;
signal cpo : fpc_out_type;
signal cpodb : fpc_debug_out_type;
signal rd1, rd2, wd : std_logic_vector(35 downto 0);
signal gnd, vcc : std_logic;
constant FPURFHARD : integer := 1; --1-is_fpga(memtech);
constant fpuarch : integer := fpu mod 16;
constant fpunet : integer := fpu / 16;
attribute sync_set_reset : string;
attribute sync_set_reset of rst : signal is "true";
begin
gnd <= '0'; vcc <= '1';
-- leon3 processor core (iu, caches & mul/div)
p0 : proc3
generic map (hindex, fabtech, memtech, nwindows, dsu, fpuarch, v8, cp, mac,
pclow, notag, nwp, icen, irepl, isets, ilinesize, isetsize, isetlock,
dcen, drepl, dsets, dlinesize, dsetsize, dsetlock, dsnoop, ilram,
ilramsize, ilramstart, dlram, dlramsize, dlramstart, mmuen, itlbnum, dtlbnum,
tlb_type, tlb_rep, lddel, disas, tbuf, pwd, svt, rstaddr, smp, cached, 0, scantest)
port map (clk, rst, holdn, ahbi, ahbo, ahbsi, ahbso, rfi, rfo, crami, cramo,
tbi, tbo, fpi, fpo, cpi, cpo, irqi, irqo, dbgi, dbgo, gnd, clk, vcc);
-- IU register file
rf0 : regfile_3p generic map (memtech, IRFBITS, 32, 1, IREGNUM)
port map (clk, rfi.waddr(IRFBITS-1 downto 0), rfi.wdata, rfi.wren,
clk, rfi.raddr1(IRFBITS-1 downto 0), rfi.ren1, rfo.data1,
rfi.raddr2(IRFBITS-1 downto 0), rfi.ren2, rfo.data2, rfi.diag);
-- cache memory
cmem0 : cachemem
generic map (memtech, icen, irepl, isets, ilinesize, isetsize, isetlock, dcen,
drepl, dsets, dlinesize, dsetsize, dsetlock, dsnoop, ilram,
ilramsize, dlram, dlramsize, mmuen)
port map (clk, crami, cramo, clk);
-- instruction trace buffer memory
tbmem_gen : if (tbuf /= 0) generate
tbmem0 : tbufmem
generic map (tech => memtech, tbuf => tbuf)
port map (clk, tbi, tbo);
end generate;
-- FPU
fpu0 : if (fpu = 0) generate fpo.ldlock <= '0'; fpo.ccv <= '1'; fpo.holdn <= '1'; end generate;
grfpw0gen : if (fpuarch > 0) and (fpuarch < 8) generate
fpu0: grfpwx
generic map (fabtech, FPURFHARD*memtech, (fpuarch-1), pclow, dsu, disas, fpunet, 0)
port map (rst, clk, holdn, fpi, fpo);
end generate;
mfpw0gen : if (fpuarch = 15) generate
fpu0 : mfpwx
generic map (FPURFHARD*memtech, pclow, dsu, disas)
port map (rst, clk, holdn, fpi, fpo);
end generate;
grlfpc0gen : if (fpuarch >= 8) and (fpuarch < 15) generate
fpu0 : grlfpwx
generic map (FPURFHARD*memtech, pclow, dsu, disas, (fpuarch-8), fpunet)
port map (rst, clk, holdn, fpi, fpo);
end generate;
-- Default Co-Proc drivers
cpodb.data <= zero32;
cpo <= (zero32, '0', "00", '0', '0', '0', cpodb);
-- 1-clock reset delay
rstreg : process(clk)
begin if rising_edge(clk) then rst <= rstn; end if; end process;
-- pragma translate_off
bootmsg : report_version
generic map (
"leon3_" & tost(hindex) & ": LEON3 SPARC V8 processor rev " & tost(LEON3_VERSION),
"leon3_" & tost(hindex) & ": icache " & tost(isets*icen) & "*" & tost(isetsize*icen) &
" kbyte, dcache " & tost(dsets*dcen) & "*" & tost(dsetsize*dcen) & " kbyte"
);
-- pragma translate_on
end;
| mit | 6dc9e2e2961a6c69fd587a865f20c892 | 0.583492 | 3.435125 | false | false | false | false |
impedimentToProgress/UCI-BlueChip | AttackFiles/Attacks/privEsc/lib/techmap/maps/allmem.vhd | 2 | 22,973 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Package: allmem
-- File: allmem.vhd
-- Author: Jiri Gaisler Gaisler Research
-- Description: All tech specific memories
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
package allmem is
-- AX & RTAX family
component axcel_syncram
generic ( abits : integer := 10; dbits : integer := 8 );
port (
clk : in std_ulogic;
address : in std_logic_vector((abits -1) downto 0);
datain : in std_logic_vector((dbits -1) downto 0);
dataout : out std_logic_vector((dbits -1) downto 0);
enable : in std_ulogic;
write : in std_ulogic);
end component;
component axcel_syncram_2p
generic ( abits : integer := 8; dbits : integer := 32);
port (
rclk : in std_ulogic;
rena : in std_ulogic;
raddr : in std_logic_vector (abits -1 downto 0);
dout : out std_logic_vector (dbits -1 downto 0);
wclk : in std_ulogic;
waddr : in std_logic_vector (abits -1 downto 0);
din : in std_logic_vector (dbits -1 downto 0);
write : in std_ulogic);
end component;
-- Proasic + Proasicplus family
component proasic_syncram
generic ( abits : integer := 10; dbits : integer := 8 );
port (
clk : in std_ulogic;
address : in std_logic_vector((abits -1) downto 0);
datain : in std_logic_vector((dbits -1) downto 0);
dataout : out std_logic_vector((dbits -1) downto 0);
enable : in std_ulogic;
write : in std_ulogic);
end component;
component proasic_syncram_2p
generic ( abits : integer := 8; dbits : integer := 32);
port (
rclk : in std_ulogic;
rena : in std_ulogic;
raddr : in std_logic_vector (abits -1 downto 0);
dout : out std_logic_vector (dbits -1 downto 0);
wclk : in std_ulogic;
waddr : in std_logic_vector (abits -1 downto 0);
din : in std_logic_vector (dbits -1 downto 0);
write : in std_ulogic);
end component;
-- Proasic3 family
component proasic3_syncram
generic ( abits : integer := 10; dbits : integer := 8 );
port (
clk : in std_ulogic;
address : in std_logic_vector((abits -1) downto 0);
datain : in std_logic_vector((dbits -1) downto 0);
dataout : out std_logic_vector((dbits -1) downto 0);
enable : in std_ulogic;
write : in std_ulogic);
end component;
component proasic3_syncram_2p
generic ( abits : integer := 8; dbits : integer := 32);
port (
rclk : in std_ulogic;
rena : in std_ulogic;
raddr : in std_logic_vector (abits -1 downto 0);
dout : out std_logic_vector (dbits -1 downto 0);
wclk : in std_ulogic;
waddr : in std_logic_vector (abits -1 downto 0);
din : in std_logic_vector (dbits -1 downto 0);
write : in std_ulogic);
end component;
component proasic3_syncram_dp is
generic ( abits : integer := 6; dbits : integer := 8 );
port (
clk1 : in std_ulogic;
address1 : in std_logic_vector((abits -1) downto 0);
datain1 : in std_logic_vector((dbits -1) downto 0);
dataout1 : out std_logic_vector((dbits -1) downto 0);
enable1 : in std_ulogic;
write1 : in std_ulogic;
clk2 : in std_ulogic;
address2 : in std_logic_vector((abits -1) downto 0);
datain2 : in std_logic_vector((dbits -1) downto 0);
dataout2 : out std_logic_vector((dbits -1) downto 0);
enable2 : in std_ulogic;
write2 : in std_ulogic
);
end component;
component altera_syncram
generic ( abits : integer := 10; dbits : integer := 8 );
port (
clk : in std_ulogic;
address : in std_logic_vector((abits -1) downto 0);
datain : in std_logic_vector((dbits -1) downto 0);
dataout : out std_logic_vector((dbits -1) downto 0);
enable : in std_ulogic;
write : in std_ulogic
);
end component;
component altera_syncram_dp
generic ( abits : integer := 10; dbits : integer := 8 );
port (
clk1 : in std_ulogic;
address1 : in std_logic_vector((abits -1) downto 0);
datain1 : in std_logic_vector((dbits -1) downto 0);
dataout1 : out std_logic_vector((dbits -1) downto 0);
enable1 : in std_ulogic;
write1 : in std_ulogic;
clk2 : in std_ulogic;
address2 : in std_logic_vector((abits -1) downto 0);
datain2 : in std_logic_vector((dbits -1) downto 0);
dataout2 : out std_logic_vector((dbits -1) downto 0);
enable2 : in std_ulogic;
write2 : in std_ulogic
);
end component;
component generic_syncram
generic (abits : integer := 10; dbits : integer := 8 );
port (
clk : in std_ulogic;
address : in std_logic_vector((abits -1) downto 0);
datain : in std_logic_vector((dbits -1) downto 0);
dataout : out std_logic_vector((dbits -1) downto 0);
write : in std_ulogic
);
end component;
component generic_syncram_2p
generic (abits : integer := 8; dbits : integer := 32; sepclk : integer := 0);
port (
rclk : in std_ulogic;
wclk : in std_ulogic;
rdaddress: in std_logic_vector (abits -1 downto 0);
wraddress: in std_logic_vector (abits -1 downto 0);
data: in std_logic_vector (dbits -1 downto 0);
wren : in std_ulogic;
q: out std_logic_vector (dbits -1 downto 0)
);
end component;
-- synchronous 3-port regfile (2 read, 1 write port)
component generic_regfile_3p
generic (tech : integer := 0; abits : integer := 6; dbits : integer := 32;
wrfst : integer := 0; numregs : integer := 40);
port (
wclk : in std_ulogic;
waddr : in std_logic_vector((abits -1) downto 0);
wdata : in std_logic_vector((dbits -1) downto 0);
we : in std_ulogic;
rclk : in std_ulogic;
raddr1 : in std_logic_vector((abits -1) downto 0);
re1 : in std_ulogic;
rdata1 : out std_logic_vector((dbits -1) downto 0);
raddr2 : in std_logic_vector((abits -1) downto 0);
re2 : in std_ulogic;
rdata2 : out std_logic_vector((dbits -1) downto 0)
);
end component;
component ihp25_syncram
generic ( abits : integer := 10; dbits : integer := 8 );
port (
clk : in std_logic;
address : in std_logic_vector(abits -1 downto 0);
datain : in std_logic_vector(dbits -1 downto 0);
dataout : out std_logic_vector(dbits -1 downto 0);
enable : in std_logic;
write : in std_logic
);
end component;
component ec_syncram
generic ( abits : integer := 10; dbits : integer := 8 );
port (
clk : in std_ulogic;
address : in std_logic_vector((abits -1) downto 0);
datain : in std_logic_vector((dbits -1) downto 0);
dataout : out std_logic_vector((dbits -1) downto 0);
enable : in std_ulogic;
write : in std_ulogic
);
end component;
component ec_syncram_dp
generic ( abits : integer := 10; dbits : integer := 8 );
port (
clk1 : in std_ulogic;
address1 : in std_logic_vector((abits -1) downto 0);
datain1 : in std_logic_vector((dbits -1) downto 0);
dataout1 : out std_logic_vector((dbits -1) downto 0);
enable1 : in std_ulogic;
write1 : in std_ulogic;
clk2 : in std_ulogic;
address2 : in std_logic_vector((abits -1) downto 0);
datain2 : in std_logic_vector((dbits -1) downto 0);
dataout2 : out std_logic_vector((dbits -1) downto 0);
enable2 : in std_ulogic;
write2 : in std_ulogic
);
end component;
component rh_lib18t_syncram_2p
generic (abits : integer := 6; dbits : integer := 8);
port (
rclk : in std_ulogic;
renable : in std_ulogic;
raddress : in std_logic_vector((abits -1) downto 0);
dataout : out std_logic_vector((dbits -1) downto 0);
write : in std_ulogic;
waddress : in std_logic_vector((abits -1) downto 0);
datain : in std_logic_vector((dbits -1) downto 0);
diagin : in std_logic_vector(3 downto 0));
end component;
component rh_lib18t_syncram is
generic (abits : integer := 6; dbits : integer := 8 );
port (
clk : in std_ulogic;
address : in std_logic_vector((abits -1) downto 0);
datain : in std_logic_vector((dbits -1) downto 0);
dataout : out std_logic_vector((dbits -1) downto 0);
enable : in std_ulogic;
write : in std_ulogic;
diagin : in std_logic_vector(1 downto 0) := "00");
end component;
component umc_syncram
generic ( abits : integer := 10; dbits : integer := 8 );
port (
clk : in std_ulogic;
address : in std_logic_vector(abits -1 downto 0);
datain : in std_logic_vector(dbits -1 downto 0);
dataout : out std_logic_vector(dbits -1 downto 0);
enable : in std_ulogic;
write : in std_ulogic);
end component;
component rhumc_syncram
generic ( abits : integer := 10; dbits : integer := 8 );
port (
clk : in std_ulogic;
address : in std_logic_vector(abits -1 downto 0);
datain : in std_logic_vector(dbits -1 downto 0);
dataout : out std_logic_vector(dbits -1 downto 0);
enable : in std_ulogic;
write : in std_ulogic);
end component;
component virage_syncram
generic ( abits : integer := 10; dbits : integer := 8 );
port (
clk : in std_ulogic;
address : in std_logic_vector(abits -1 downto 0);
datain : in std_logic_vector(dbits -1 downto 0);
dataout : out std_logic_vector(dbits -1 downto 0);
enable : in std_ulogic;
write : in std_ulogic);
end component;
component virage_syncram_dp
generic ( abits : integer := 10; dbits : integer := 8 );
port (
clk1 : in std_ulogic;
address1 : in std_logic_vector((abits -1) downto 0);
datain1 : in std_logic_vector((dbits -1) downto 0);
dataout1 : out std_logic_vector((dbits -1) downto 0);
enable1 : in std_ulogic;
write1 : in std_ulogic;
clk2 : in std_ulogic;
address2 : in std_logic_vector((abits -1) downto 0);
datain2 : in std_logic_vector((dbits -1) downto 0);
dataout2 : out std_logic_vector((dbits -1) downto 0);
enable2 : in std_ulogic;
write2 : in std_ulogic);
end component;
component virage90_syncram
generic ( abits : integer := 10; dbits : integer := 8 );
port (
clk : in std_ulogic;
address : in std_logic_vector(abits -1 downto 0);
datain : in std_logic_vector(dbits -1 downto 0);
dataout : out std_logic_vector(dbits -1 downto 0);
enable : in std_ulogic;
write : in std_ulogic);
end component;
component virtex_syncram
generic ( abits : integer := 6; dbits : integer := 8 );
port (
clk : in std_ulogic;
address : in std_logic_vector((abits -1) downto 0);
datain : in std_logic_vector((dbits -1) downto 0);
dataout : out std_logic_vector((dbits -1) downto 0);
enable : in std_ulogic;
write : in std_ulogic
);
end component;
component virtex_syncram_dp
generic ( abits : integer := 6; dbits : integer := 8 );
port (
clk1 : in std_ulogic;
address1 : in std_logic_vector((abits -1) downto 0);
datain1 : in std_logic_vector((dbits -1) downto 0);
dataout1 : out std_logic_vector((dbits -1) downto 0);
enable1 : in std_ulogic;
write1 : in std_ulogic;
clk2 : in std_ulogic;
address2 : in std_logic_vector((abits -1) downto 0);
datain2 : in std_logic_vector((dbits -1) downto 0);
dataout2 : out std_logic_vector((dbits -1) downto 0);
enable2 : in std_ulogic;
write2 : in std_ulogic
);
end component;
component virtex2_syncram
generic ( abits : integer := 10; dbits : integer := 8 );
port (
clk : in std_ulogic;
address : in std_logic_vector((abits -1) downto 0);
datain : in std_logic_vector((dbits -1) downto 0);
dataout : out std_logic_vector((dbits -1) downto 0);
enable : in std_ulogic;
write : in std_ulogic
);
end component;
component virtex2_syncram_dp
generic ( abits : integer := 10; dbits : integer := 8 );
port (
clk1 : in std_ulogic;
address1 : in std_logic_vector((abits -1) downto 0);
datain1 : in std_logic_vector((dbits -1) downto 0);
dataout1 : out std_logic_vector((dbits -1) downto 0);
enable1 : in std_ulogic;
write1 : in std_ulogic;
clk2 : in std_ulogic;
address2 : in std_logic_vector((abits -1) downto 0);
datain2 : in std_logic_vector((dbits -1) downto 0);
dataout2 : out std_logic_vector((dbits -1) downto 0);
enable2 : in std_ulogic;
write2 : in std_ulogic
);
end component;
component virage90_syncram_dp
generic ( abits : integer := 10; dbits : integer := 8 );
port (
clk1 : in std_ulogic;
address1 : in std_logic_vector((abits -1) downto 0);
datain1 : in std_logic_vector((dbits -1) downto 0);
dataout1 : out std_logic_vector((dbits -1) downto 0);
enable1 : in std_ulogic;
write1 : in std_ulogic;
clk2 : in std_ulogic;
address2 : in std_logic_vector((abits -1) downto 0);
datain2 : in std_logic_vector((dbits -1) downto 0);
dataout2 : out std_logic_vector((dbits -1) downto 0);
enable2 : in std_ulogic;
write2 : in std_ulogic
);
end component;
component virtex2_syncram64
generic ( abits : integer := 9);
port (
clk : in std_ulogic;
address : in std_logic_vector (abits -1 downto 0);
datain : in std_logic_vector (63 downto 0);
dataout : out std_logic_vector (63 downto 0);
enable : in std_logic_vector (1 downto 0);
write : in std_logic_vector (1 downto 0)
);
end component;
component ut025crh_syncram
generic ( abits : integer := 10; dbits : integer := 8 );
port (
clk : in std_ulogic;
address : in std_logic_vector((abits -1) downto 0);
datain : in std_logic_vector((dbits -1) downto 0);
dataout : out std_logic_vector((dbits -1) downto 0);
enable : in std_ulogic;
write : in std_ulogic
);
end component;
component ut025crh_syncram_2p
generic ( abits : integer := 8; dbits : integer := 32);
port (
rclk : in std_ulogic;
rena : in std_ulogic;
raddr : in std_logic_vector (abits -1 downto 0);
dout : out std_logic_vector (dbits -1 downto 0);
wclk : in std_ulogic;
waddr : in std_logic_vector (abits -1 downto 0);
din : in std_logic_vector (dbits -1 downto 0);
write : in std_ulogic);
end component;
component peregrine_regfile_3p
generic (abits : integer := 6; dbits : integer := 32);
port (
wclk : in std_ulogic;
waddr : in std_logic_vector((abits -1) downto 0);
wdata : in std_logic_vector((dbits -1) downto 0);
we : in std_ulogic;
raddr1 : in std_logic_vector((abits -1) downto 0);
re1 : in std_ulogic;
rdata1 : out std_logic_vector((dbits -1) downto 0);
raddr2 : in std_logic_vector((abits -1) downto 0);
re2 : in std_ulogic;
rdata2 : out std_logic_vector((dbits -1) downto 0));
end component;
component eclipse_syncram_2p is
generic ( abits : integer := 8; dbits : integer := 32);
port (
rclk : in std_ulogic;
rena : in std_ulogic;
raddr : in std_logic_vector (abits -1 downto 0);
dout : out std_logic_vector (dbits -1 downto 0);
wclk : in std_ulogic;
waddr : in std_logic_vector (abits -1 downto 0);
din : in std_logic_vector (dbits -1 downto 0);
write : in std_ulogic);
end component;
component nextreme_syncram_2p is
generic (abits : integer := 6; dbits : integer := 8);
port (
rclk : in std_ulogic;
renable : in std_ulogic;
raddress : in std_logic_vector((abits -1) downto 0);
dataout : out std_logic_vector((dbits -1) downto 0);
wclk : in std_ulogic;
write : in std_ulogic;
waddress : in std_logic_vector((abits -1) downto 0);
datain : in std_logic_vector((dbits -1) downto 0));
end component;
component custom1_syncram_2p is
generic ( abits : integer := 8; dbits : integer := 32);
port (
rclk : in std_ulogic;
renable : in std_ulogic;
raddress : in std_logic_vector((abits -1) downto 0);
dataout : out std_logic_vector((dbits -1) downto 0);
wclk : in std_ulogic;
write : in std_ulogic;
waddress : in std_logic_vector((abits -1) downto 0);
datain : in std_logic_vector((dbits -1) downto 0));
end component;
component artisan_syncram_2p is
generic ( abits : integer := 8; dbits : integer := 32);
port (
rclk : in std_ulogic;
renable : in std_ulogic;
raddress : in std_logic_vector((abits -1) downto 0);
dataout : out std_logic_vector((dbits -1) downto 0);
wclk : in std_ulogic;
write : in std_ulogic;
waddress : in std_logic_vector((abits -1) downto 0);
datain : in std_logic_vector((dbits -1) downto 0));
end component;
component ihp25rh_syncram
generic ( abits : integer := 10; dbits : integer := 8 );
port (
clk : in std_logic;
address : in std_logic_vector(abits -1 downto 0);
datain : in std_logic_vector(dbits -1 downto 0);
dataout : out std_logic_vector(dbits -1 downto 0);
enable : in std_logic;
write : in std_logic);
end component;
component peregrine_syncram
generic ( abits : integer := 10; dbits : integer := 8 );
port (
clk : in std_ulogic;
address : in std_logic_vector((abits -1) downto 0);
datain : in std_logic_vector((dbits -1) downto 0);
dataout : out std_logic_vector((dbits -1) downto 0);
enable : in std_ulogic;
write : in std_ulogic
);
end component;
component artisan_syncram
generic ( abits : integer := 10; dbits : integer := 32 );
port (
clk : in std_ulogic;
address : in std_logic_vector((abits -1) downto 0);
datain : in std_logic_vector((dbits -1) downto 0);
dataout : out std_logic_vector((dbits -1) downto 0);
enable : in std_ulogic;
write : in std_ulogic
);
end component;
component custom1_syncram
generic ( abits : integer := 10; dbits : integer := 32 );
port (
clk : in std_ulogic;
address : in std_logic_vector((abits -1) downto 0);
datain : in std_logic_vector((dbits -1) downto 0);
dataout : out std_logic_vector((dbits -1) downto 0);
enable : in std_ulogic;
write : in std_ulogic
);
end component;
component nextreme_syncram
generic (abits : integer := 6; dbits : integer := 8 );
port (
clk : in std_ulogic;
address : in std_logic_vector((abits -1) downto 0);
datain : in std_logic_vector((dbits -1) downto 0);
dataout : out std_logic_vector((dbits -1) downto 0);
enable : in std_ulogic;
write : in std_ulogic);
end component;
component virtex2_syncram_2p is
generic (abits : integer := 6; dbits : integer := 8; sepclk : integer := 0;
wrfst : integer := 0);
port (
rclk : in std_ulogic;
renable : in std_ulogic;
raddress : in std_logic_vector((abits -1) downto 0);
dataout : out std_logic_vector((dbits -1) downto 0);
wclk : in std_ulogic;
write : in std_ulogic;
waddress : in std_logic_vector((abits -1) downto 0);
datain : in std_logic_vector((dbits -1) downto 0));
end component;
component virage_syncram_2p
generic (abits : integer := 6; dbits : integer := 8;
sepclk : integer := 0; wrfst : integer := 0);
port (
rclk : in std_ulogic;
renable : in std_ulogic;
raddress : in std_logic_vector((abits -1) downto 0);
dataout : out std_logic_vector((dbits -1) downto 0);
wclk : in std_ulogic;
write : in std_ulogic;
waddress : in std_logic_vector((abits -1) downto 0);
datain : in std_logic_vector((dbits -1) downto 0));
end component;
component atc18rha_syncram
generic ( abits : integer := 10; dbits : integer := 8 );
port (
clk : in std_ulogic;
address : in std_logic_vector(abits -1 downto 0);
datain : in std_logic_vector(dbits -1 downto 0);
dataout : out std_logic_vector(dbits -1 downto 0);
enable : in std_ulogic;
write : in std_ulogic;
testin : in std_logic_vector(3 downto 0));
end component;
component atc18rha_syncram_dp
generic ( abits : integer := 10; dbits : integer := 8);
port (
clk1 : in std_ulogic;
address1 : in std_logic_vector((abits -1) downto 0);
datain1 : in std_logic_vector((dbits -1) downto 0);
dataout1 : out std_logic_vector((dbits -1) downto 0);
enable1 : in std_ulogic;
write1 : in std_ulogic;
clk2 : in std_ulogic;
address2 : in std_logic_vector((abits -1) downto 0);
datain2 : in std_logic_vector((dbits -1) downto 0);
dataout2 : out std_logic_vector((dbits -1) downto 0);
enable2 : in std_ulogic;
write2 : in std_ulogic;
testin : in std_logic_vector(3 downto 0));
end component;
component atc18rha_syncram_2p
generic ( abits : integer := 6; dbits : integer := 8;
sepclk : integer := 0; wrfst : integer := 0);
port (
rclk : in std_ulogic;
renable : in std_ulogic;
raddress : in std_logic_vector((abits -1) downto 0);
dataout : out std_logic_vector((dbits -1) downto 0);
wclk : in std_ulogic;
write : in std_ulogic;
waddress : in std_logic_vector((abits -1) downto 0);
datain : in std_logic_vector((dbits -1) downto 0);
testin : in std_logic_vector(3 downto 0));
end component;
component artisan_syncram_dp
generic ( abits : integer := 10; dbits : integer := 32 );
port (
clk1 : in std_ulogic;
address1 : in std_logic_vector((abits -1) downto 0);
datain1 : in std_logic_vector((dbits -1) downto 0);
dataout1 : out std_logic_vector((dbits -1) downto 0);
enable1 : in std_ulogic;
write1 : in std_ulogic;
clk2 : in std_ulogic;
address2 : in std_logic_vector((abits -1) downto 0);
datain2 : in std_logic_vector((dbits -1) downto 0);
dataout2 : out std_logic_vector((dbits -1) downto 0);
enable2 : in std_ulogic;
write2 : in std_ulogic
);
end component;
end;
| mit | 1276004d0316ca711efa8a1b9aed67b0 | 0.608497 | 3.398373 | false | false | false | false |
impedimentToProgress/UCI-BlueChip | AttackFiles/Attacks/privEsc/lib/gaisler/pci/pcitb_target.vhd | 2 | 13,324 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: pcitb_target
-- File: pcitb_target.vhd
-- Author: Alf Vaerneus, Gaisler Research
-- Description: PCI Target emulator.
------------------------------------------------------------------------------
-- pragma translate_off
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.stdlib.all;
library gaisler;
use gaisler.pcitb.all;
use gaisler.pcilib.all;
use gaisler.ambatest.all;
library std;
use std.textio.all;
entity pcitb_target is
generic (
slot : integer := 0;
abits : integer := 10;
bars : integer := 1;
resptime : integer := 2;
latency : integer := 0;
rbuf : integer := 8;
stopwd : boolean := true;
tval : time := 7 ns;
conf : config_header_type := config_init;
dbglevel : integer := 1);
port (
-- PCI signals
pciin : in pci_type;
pciout : out pci_type;
-- TB signals
tbi : in tb_in_type;
tbo : out tb_out_type
);
end pcitb_target;
architecture tb of pcitb_target is
constant T_O : integer := 9;
constant word : std_logic_vector(2 downto 0) := "100";
type mem_type is array(0 to ((2**abits)-1)) of std_logic_vector(31 downto 0);
type state_type is(idle,respwait,write,read,latw);
type reg_type is record
state : state_type;
pci : pci_type;
pcien : std_logic;
aden : std_logic;
paren : std_logic;
erren : std_logic;
write : std_logic;
waitcycles : integer;
latcnt : integer;
curword : integer;
first : boolean;
di : std_logic_vector(31 downto 0);
ad : std_logic_vector(31 downto 0);
comm : std_logic_vector(3 downto 0);
config : config_header_type;
cbe : std_logic_vector(3 downto 0); -- *** sub-word write
end record;
signal r,rin : reg_type;
signal do : std_logic_vector(31 downto 0);
procedure writeconf(ad : in std_logic_vector(5 downto 0);
data : in std_logic_vector(31 downto 0);
vconfig : out config_header_type) is
begin
case conv_integer(ad) is
-- when 0 => vconfig.devid := data(31 downto 16); vconfig.vendid <= data(15 downto 0);
when 1 => vconfig.status := data(31 downto 16); vconfig.command := data(15 downto 0);
when 2 => vconfig.class_code := data(31 downto 8); vconfig.revid := data(7 downto 0);
when 3 => vconfig.bist := data(31 downto 24); vconfig.header_type := data(23 downto 16);
vconfig.lat_timer := data(15 downto 8); vconfig.cache_lsize := data(7 downto 0);
when 4 => vconfig.bar(0) := data;
when 5 => vconfig.bar(1) := data;
when 6 => vconfig.bar(2) := data;
when 7 => vconfig.bar(3) := data;
when 8 => vconfig.bar(4) := data;
when 9 => vconfig.bar(5) := data;
when 10 => vconfig.cis_p := data;
when 11 => vconfig.subid := data(31 downto 16); vconfig.subvendid := data(15 downto 0);
when 12 => vconfig.exp_rom_ba := data;
when 13 => vconfig.max_lat := data(31 downto 24); vconfig.min_gnt := data(23 downto 16);
vconfig.int_pin := data(15 downto 8); vconfig.int_line := data(7 downto 0);
when others =>
end case;
end procedure;
procedure readconf(ad : in std_logic_vector(5 downto 0); data : out std_logic_vector(31 downto 0)) is
begin
case conv_integer(ad) is
when 0 => data(31 downto 16) := (conv_std_logic_vector(slot,4) & r.config.devid(11 downto 0));
data(15 downto 0) := r.config.vendid;
when 1 => data(31 downto 16) := r.config.status; data(15 downto 0) := r.config.command;
when 2 => data(31 downto 8) := r.config.class_code; data(7 downto 0) := r.config.revid;
when 3 => data(31 downto 24) := r.config.bist; data(23 downto 16) := r.config.header_type;
data(15 downto 8) := r.config.lat_timer; data(7 downto 0) := r.config.cache_lsize;
when 4 => data := r.config.bar(0)(31 downto abits) & zero32(abits-1 downto 0);
when 5 => if bars > 1 then data := r.config.bar(1)(31 downto 9) & zero32(8 downto 1) & '1';
else data := (others => '0'); end if;
when 6 => if bars > 2 then data := r.config.bar(2)(31 downto abits) & zero32(abits-1 downto 0);
else data := (others => '0'); end if;
when 7 => if bars > 3 then data := r.config.bar(3)(31 downto abits) & zero32(abits-1 downto 0);
else data := (others => '0'); end if;
when 8 => if bars > 4 then data := r.config.bar(4)(31 downto abits) & zero32(abits-1 downto 0);
else data := (others => '0'); end if;
when 9 => if bars > 5 then data := r.config.bar(5)(31 downto abits) & zero32(abits-1 downto 0);
else data := (others => '0'); end if;
when 10 => data := r.config.cis_p;
when 11 => data(31 downto 16) := r.config.subid; data(15 downto 0) := r.config.subvendid;
when 12 => data := r.config.exp_rom_ba;
when 13 => data(31 downto 24) := r.config.max_lat; data(23 downto 16) := r.config.min_gnt;
data(15 downto 8) := r.config.int_pin; data(7 downto 0) := r.config.int_line;
when others =>
end case;
end procedure;
function pci_hit(ad : std_logic_vector(31 downto 0);
c : std_logic_vector(3 downto 0);
idsel : std_logic;
con : config_header_type) return boolean is
variable hit : boolean;
begin
hit := false;
if ((c = CONF_READ or c = CONF_WRITE)
and idsel = '1' and ad(1 downto 0) = "00")
then hit := true;
else
for i in 0 to bars loop
if i = 1 then
if ((c = IO_READ or c = IO_WRITE)
and ad(31 downto abits) = con.bar(i)(31 downto abits))
then hit := true; end if;
else
if ((c = MEM_READ or c = MEM_WRITE or c = MEM_R_MULT or c = MEM_R_LINE or c = MEM_W_INV)
and ad(31 downto abits) = con.bar(i)(31 downto abits))
then hit := true; end if;
end if;
end loop;
end if;
return(hit);
end function;
begin
cont : process
file readfile,writefile : text;
variable first : boolean := true;
variable mem : mem_type;
variable L : line;
variable datahex : string(1 to 8);
variable count : integer;
begin
if first then
for i in 0 to ((2**abits)-1) loop
mem(i) := (others => '0');
end loop;
first := false;
elsif tbi.start = '1' then
if tbi.usewfile then
file_open(writefile, external_name => tbi.wfile(18 downto trimlen(tbi.wfile)), open_kind => write_mode);
count := conv_integer(tbi.address);
for i in 0 to tbi.no_words-1 loop
write(L,printhex(mem(count),32));
writeline(writefile,L);
count := count+4;
end loop;
file_close(writefile);
end if;
elsif r.ad(0) /= 'U' then
do <= mem(conv_integer(to_x01(r.ad)));
--if r.write = '1' then mem(conv_integer(to_x01(r.ad))) := r.di; end if; -- *** sub-word write
if r.write = '1' then
case r.cbe is
when "1110" =>
mem(conv_integer(to_x01(r.ad)))(7 downto 0) := r.di(7 downto 0);
when "1101" =>
mem(conv_integer(to_x01(r.ad)))(15 downto 8) := r.di(15 downto 8);
when "1011" =>
mem(conv_integer(to_x01(r.ad)))(23 downto 16) := r.di(23 downto 16);
when "0111" =>
mem(conv_integer(to_x01(r.ad)))(31 downto 24) := r.di(31 downto 24);
when "1100" =>
mem(conv_integer(to_x01(r.ad)))(15 downto 0) := r.di(15 downto 0);
when "0011" =>
mem(conv_integer(to_x01(r.ad)))(31 downto 16) := r.di(31 downto 16);
when others =>
mem(conv_integer(to_x01(r.ad))) := r.di;
end case;
end if;
end if;
tbo.ready <= tbi.start;
wait for 1 ns;
end process;
comb : process(pciin, do)
variable v : reg_type;
begin
v := r; v.write := '0';
v.pci.ad.par := xorv(r.pci.ad.ad & pciin.ad.cbe);
v.paren := r.aden; v.erren := r.paren;
case r.state is
when idle =>
if (r.pci.ifc.trdy and r.pci.ifc.stop and r.pci.ifc.devsel) = '1' then v.pcien := '1'; end if;
v.aden := '1'; v.waitcycles := 1; v.latcnt := latency; v.first := true;
v.pci.ifc.trdy := '1'; v.pci.ifc.stop := '1'; v.curword := 0;
v.pci.ifc.devsel := '1'; v.pci.err.perr := '1';
if pciin.ifc.frame = '0' then
v.comm := pciin.ad.cbe;
if pci_hit(pciin.ad.ad,pciin.ad.cbe,pciin.ifc.idsel(slot),v.config) then
v.ad := zero32(31 downto abits) & pciin.ad.ad(abits-1 downto 0);
if r.waitcycles = resptime then
v.pci.ifc.devsel := '0'; v.pcien := '0';
if pciin.ad.cbe(0) = '1' then v.state := write; v.pci.ifc.trdy := '0';
else v.state := read; v.aden := '0'; end if;
else v.state := respwait; v.waitcycles := r.waitcycles+1; end if;
end if;
end if;
when respwait => -- Initial response time
if r.waitcycles = resptime then
v.pci.ifc.devsel := '0'; v.pcien := '0';
if r.comm(0) = '1' then v.state := write; v.pci.ifc.trdy := '0';
else v.state := read; v.aden := '0'; end if;
else v.waitcycles := r.waitcycles+1; end if;
when write => -- Write access
if pciin.ifc.irdy = '0' then
v.curword := r.curword+1;
if r.comm = CONF_WRITE then writeconf(r.ad(7 downto 2),pciin.ad.ad,v.config);
--else v.di := pciin.ad.ad; v.write := '1'; end if; -- *** sub-word write
else v.di := pciin.ad.ad; v.write := '1'; v.cbe := pciin.ad.cbe; end if;
end if;
if r.write = '1' then v.ad := r.ad + "100"; end if;
if pciin.ifc.frame = '1' then
v.state := idle;
v.pci.ifc.trdy := '1'; v.pci.ifc.devsel := '1';
elsif (r.latcnt > 0 and pciin.ifc.irdy = '0') then v.state := latw; v.pci.ifc.trdy := '1'; v.latcnt := r.latcnt-1;
end if;
when read => -- Read access
v.pci.ifc.trdy := '0';
if (pciin.ifc.irdy = '0' or r.first = true) then
v.ad := r.ad + "100"; v.first := false;
if r.comm = CONF_READ then readconf(r.ad(7 downto 2),v.pci.ad.ad);
else v.pci.ad.ad := do; end if;
end if;
if (pciin.ifc.trdy or pciin.ifc.irdy) = '0' then v.curword := r.curword+1; end if;
if (pciin.ifc.frame and not (pciin.ifc.trdy and pciin.ifc.stop)) = '1' then
v.state := idle; v.aden := '1';
v.pci.ifc.trdy := '1'; v.pci.ifc.devsel := '1';
elsif (r.latcnt > 0 and (pciin.ifc.trdy or pciin.ifc.irdy) = '0' and pciin.ifc.stop = '1') then
v.state := latw; v.latcnt := r.latcnt-1; v.pci.ifc.trdy := '1';
end if;
when latw => -- Latency between data phases
v.pci.ifc.trdy := '1';
if r.write = '1' then v.ad := r.ad + "100"; end if;
if (r.latcnt <= 1 and r.comm(0) = '0') then
v.latcnt := latency;
v.state := read; v.aden := '0';
elsif r.latcnt = 0 then
v.latcnt := latency;
v.state := write; v.pci.ifc.trdy := '0';
else v.latcnt := r.latcnt-1; end if;
when others =>
end case;
-- Disconnect type
if ((v.curword+1) >= rbuf) then
if pciin.ifc.frame = '1' then
v.pci.ifc.stop := '1';
elsif stopwd then
if r.pci.ifc.stop = '1' then
v.pci.ifc.stop := v.pci.ifc.trdy;
else
if pciin.ifc.irdy = '0' then v.pci.ifc.trdy := '1'; end if;
v.pci.ifc.stop := '0';
end if;
else
v.pci.ifc.stop := '0';
v.pci.ifc.trdy := '1';
end if;
end if;
if pciin.syst.rst = '0' then
v.state := idle;
v.config := conf;
v.waitcycles := 1;
v.latcnt := latency;
v.ad := (others => '0');
v.di := (others => '0');
end if;
rin <= v;
end process;
clockreg : process(pciin.syst)
begin
if rising_edge(pciin.syst.clk) then
r <= rin;
end if;
end process;
pciout.ad.ad <= r.pci.ad.ad after tval when r.aden = '0' else (others => 'Z') after tval;
pciout.ad.par <= r.pci.ad.par after tval when (r.paren = '0' and (r.pci.ad.par = '1' or r.pci.ad.par = '0')) else 'Z' after tval;
pciout.ifc.trdy <= r.pci.ifc.trdy after tval when r.pcien = '0' else 'Z' after tval;
pciout.ifc.stop <= r.pci.ifc.stop after tval when r.pcien = '0' else 'Z' after tval;
pciout.ifc.devsel <= r.pci.ifc.devsel after tval when r.pcien = '0' else 'Z' after tval;
pciout.err.perr <= r.pci.err.perr after tval when r.erren = '0' else 'Z' after tval;
end;
-- pragma translate_on
| mit | 49716032957cf7adb3685ce199a9db2a | 0.565821 | 3.146163 | false | true | false | false |
amerc/phimii | source/nexys3.vhd | 1 | 25,661 | --------------------------------------------------------------------------------
---
--- CHIPS - 2.0 Simple Web App Demo
---
--- :Author: Jonathan P Dawson
--- :Date: 04/04/2014
--- :email: [email protected]
--- :license: MIT
--- :
--- :Copyright: Copyright (C) Jonathan P Dawson 2014
--- :Modified by Amer Al-Canaan, June 2014
---
--------------------------------------------------------------------------------
---
--- +--------------+
--- | CLOCK TREE |
--- +--------------+
--- | >-- CLK1 (50MHz) ---> CLK
--- CLK_IN >--> (100 MHz) |
--- | >-- CLK2 (100MHz)
--- | | +-------+
--- | +-- CLK3 (25MHz) ->+ ODDR2 +-->[GTXCLK] *** Not used in Nexys3
--- | | | **not |
--- | +-- CLK3_N (25MHZ) ->+ used |
--- | | +-------+
--- RST >-----> >-- CLK4 (200MHz)
--- | |
--- | |
--- | | CLK >--+--------+
--- | | | |
--- | | +--v-+ +--v-+
--- | | | | | |
--- | LOCKED >------> >---> >-------> INTERNAL_RESET
--- | | | | | |
--- +--------------+ +----+ +----+
---
--- +-------------+ +--------------+
--- | SERVER | | USER DESIGN |
--- +-------------+ +--------------+
--- | | | |
--- | >-----> <-------< SWITCHES
--- | | | |
--- | <-----< >-------> LEDS
--- | | | |
--- | | | <-------< BUTTONS
--- | | | |
--- | | +----^----v----+
--- | | | |
--- | | +----^----v----+
--- | | | UART |
--- | | +--------------+
--- | | | >-------> RS232-TX
--- | | | |
--- +---v-----^---+ | <-------< RS232-RX
--- | | +--------------+
--- +---v-----^---+
--- | ETHERNET |
--- | MAC |
--- +-------------+
--- | +------> [PHY_RESET]
--- | |
---[RXCLK]<----->+ (25 MHz) |
--- | |
---[TXCLK] ----->+ (25 MHz) |
--- | |
--- [RXD]<----->+ +------> [TXD]
--- | |
--- [RXDV] ----->+ +------> [TXEN]
--- | |
--- [RXER]<----->+ +<------> [TXER]
--- | |
--- | |
--- +-------------+
---
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
entity NEXYS3 is
port(
CLK_IN : in std_logic;
RST : in std_logic;
--PHY INTERFACE
TX : out std_logic;
RX : in std_logic;
PHY_RESET : out std_logic;
RXDV : in std_logic;
RXER : inout std_logic; --* inout
RXCLK : inout std_logic; --* inout
RXD : inout std_logic_vector(3 downto 0); --* inout
TXCLK : in std_logic;
TXD : out std_logic_vector(3 downto 0);
TXEN : out std_logic;
TXER : out std_logic;
PhyCol : inout std_logic; --* inout
CRS : in std_logic;
--LEDS
GPIO_LEDS : out std_logic_vector(7 downto 0);
GPIO_SWITCHES : in std_logic_vector(7 downto 0);
GPIO_BUTTONS : in std_logic_vector(3 downto 0);
--RS232 INTERFACE
fx2Clk_pin : in std_logic;
RS232_RX : in std_logic;
RS232_TX : out std_logic;
-- 7 seg out
sseg_out : out std_logic_vector(7 downto 0); -- seven-segment display cathodes (one for each segment)
anodes_out : out std_logic_vector(3 downto 0) -- seven-segment display anodes (one for each digit)
);
end entity NEXYS3;
architecture RTL of NEXYS3 is
component ethernet is
port(
CLK : in std_logic;
RST : in std_logic;
--Ethernet Clock
--MII IF
TXCLK : in std_logic; --
TXER : out std_logic; --
TXEN : out std_logic; --
TXD : out std_logic_vector(3 downto 0); --
RXCLK : in std_logic; --
RXER : in std_logic;--
RXDV : in std_logic; --
RXD : in std_logic_vector(3 downto 0); --
COL : in std_logic;-- *input Added .. Collision indication
PhyCRS : in std_logic;-- *input Added .. Carrier sense
--RX STREAM
TX : in std_logic_vector(15 downto 0);
TX_STB : in std_logic;
TX_ACK : out std_logic;
--RX STREAM
RX : out std_logic_vector(15 downto 0);
RX_STB : out std_logic;
RX_ACK : in std_logic;
-- LEDS --AMER
GPIO_LEDS : out std_logic_vector(3 downto 0);
BtnL : in std_logic;
SW0 : in std_logic;
--7 seg
sseg_out : out std_logic_vector(7 downto 0); -- seven-segment display cathodes (one for each segment)
anodes_out : out std_logic_vector(3 downto 0) -- seven-segment display anodes (one for each digit)
);
end component ethernet;
component SERVER is
port(
CLK : in std_logic;
RST : in std_logic;
--ETH RX STREAM
INPUT_ETH_RX : in std_logic_vector(15 downto 0);
INPUT_ETH_RX_STB : in std_logic;
INPUT_ETH_RX_ACK : out std_logic;
--ETH TX STREAM
output_eth_tx : out std_logic_vector(15 downto 0);
OUTPUT_ETH_TX_STB : out std_logic;
OUTPUT_ETH_TX_ACK : in std_logic;
--SOCKET RX STREAM
INPUT_SOCKET : in std_logic_vector(15 downto 0);
INPUT_SOCKET_STB : in std_logic;
INPUT_SOCKET_ACK : out std_logic;
--SOCKET TX STREAM
OUTPUT_SOCKET : out std_logic_vector(15 downto 0);
OUTPUT_SOCKET_STB : out std_logic;
OUTPUT_SOCKET_ACK : in std_logic
);
end component;
component USER_DESIGN is
port(
CLK : in std_logic;
RST : in std_logic;
OUTPUT_LEDS : out std_logic_vector(15 downto 0);
OUTPUT_LEDS_STB : out std_logic;
OUTPUT_LEDS_ACK : in std_logic;
INPUT_SWITCHES : in std_logic_vector(15 downto 0);
INPUT_SWITCHES_STB : in std_logic;
INPUT_SWITCHES_ACK : out std_logic;
INPUT_BUTTONS : in std_logic_vector(15 downto 0);
INPUT_BUTTONS_STB : in std_logic;
INPUT_BUTTONS_ACK : out std_logic;
--SOCKET RX STREAM
INPUT_SOCKET : in std_logic_vector(15 downto 0);
INPUT_SOCKET_STB : in std_logic;
INPUT_SOCKET_ACK : out std_logic;
--SOCKET TX STREAM
OUTPUT_SOCKET : out std_logic_vector(15 downto 0);
OUTPUT_SOCKET_STB : out std_logic;
OUTPUT_SOCKET_ACK : in std_logic;
--RS232 RX STREAM
INPUT_RS232_RX : in std_logic_vector(15 downto 0);
INPUT_RS232_RX_STB : in std_logic;
INPUT_RS232_RX_ACK : out std_logic;
--RS232 TX STREAM
OUTPUT_RS232_TX : out std_logic_vector(15 downto 0);
OUTPUT_RS232_TX_STB : out std_logic;
OUTPUT_RS232_TX_ACK : in std_logic
);
end component;
component SERIAL_INPUT is
generic(
CLOCK_FREQUENCY : integer;
BAUD_RATE : integer
);
port(
CLK : in std_logic;
RST : in std_logic;
RX : in std_logic;
OUT1 : out std_logic_vector(7 downto 0);
OUT1_STB : out std_logic;
OUT1_ACK : in std_logic
);
end component SERIAL_INPUT;
component serial_output is
generic(
CLOCK_FREQUENCY : integer;
BAUD_RATE : integer
);
port(
CLK : in std_logic;
RST : in std_logic;
TX : out std_logic;
IN1 : in std_logic_vector(7 downto 0);
IN1_STB : in std_logic;
IN1_ACK : out std_logic
);
end component serial_output;
component initPhyNexys3 is
port(
clk : in std_logic;
reset : in std_logic;
phy_reset : out std_logic;
out_en : out std_logic
);
end component initPhyNexys3;
--chips signals
signal CLK : std_logic;
signal RST_INV : std_logic;
signal nOEN : std_logic;
--signal toPhyReset : std_logic;
--clock tree signals
signal clkin1 : std_logic;
-- Output clock buffering
signal clkfb : std_logic;
signal clk0 : std_logic;
signal clk2x : std_logic;
signal clk50 : std_logic;
signal clkfx : std_logic;
signal clkfx180 : std_logic;
signal clkdv : std_logic;
signal locked_internal : std_logic;
signal status_internal : std_logic_vector(7 downto 0);
signal CLK_OUT1 : std_logic;
signal CLK_OUT50 : std_logic;
signal CLK_OUT3 : std_logic;
signal CLK_OUT3_N : std_logic;
signal CLK_OUT2 : std_logic;
signal CLK_OUT4 : std_logic;
signal NOT_LOCKED : std_logic;
signal INTERNAL_RST : std_logic;
--signal RXD1 : std_logic;
signal TX_LOCKED : std_logic;
signal INTERNAL_TXCLK : std_logic;
signal INTERNAL_TXCLK_BUF: std_logic;
signal INTERNAL_TXCLK_BUF_N : std_logic;
-- signal INTERNAL_TXCLK_BUF_180 : std_logic;
signal TXCLK_BUF : std_logic;
signal INTERNAL_RXCLK : std_logic;
signal RXCLK_INT : std_logic; -- Here
signal INTERNAL_RXCLK_BUF: std_logic;
signal RXCLK_BUF : std_logic;
signal RXER_BUF : std_logic; --Added signal
signal RXD_BUF : std_logic_vector(3 downto 0); --Added signal
---Below added by AMER
signal INTERNAL_TXD : std_logic_vector(3 downto 0);
signal INTERNAL_TXEN : std_logic;
signal INTERNAL_TXER : std_logic;
---Up added by AMER
signal COL_BUF : std_logic; --Added signal
signal ToEXTERNAL_TXER : std_logic; --Added signal
-- signal nINT : std_logic; --Added signal
signal OUTPUT_LEDS : std_logic_vector(15 downto 0);
signal OUTPUT_LEDS_STB : std_logic;
signal OUTPUT_LEDS_ACK : std_logic;
signal INPUT_SWITCHES : std_logic_vector(15 downto 0);
signal INPUT_SWITCHES_STB : std_logic;
signal INPUT_SWITCHES_ACK : std_logic;
signal GPIO_SWITCHES_D : std_logic_vector(7 downto 0);
signal INPUT_BUTTONS : std_logic_vector(15 downto 0);
signal INPUT_BUTTONS_STB : std_logic;
signal INPUT_BUTTONS_ACK : std_logic;
signal GPIO_BUTTONS_D : std_logic_vector(3 downto 0);
--ETH RX STREAM
signal ETH_RX : std_logic_vector(15 downto 0);
signal ETH_RX_STB : std_logic;
signal ETH_RX_ACK : std_logic;
--ETH TX STREAM
signal ETH_TX : std_logic_vector(15 downto 0);
signal ETH_TX_STB : std_logic;
signal ETH_TX_ACK : std_logic;
--RS232 RX STREAM
signal INPUT_RS232_RX : std_logic_vector(15 downto 0);
signal INPUT_RS232_RX_STB : std_logic;
signal INPUT_RS232_RX_ACK : std_logic;
--RS232 TX STREAM
signal fx2Clk : std_logic;
signal OUTPUT_RS232_TX : std_logic_vector(15 downto 0);
signal OUTPUT_RS232_TX_STB : std_logic;
signal OUTPUT_RS232_TX_ACK : std_logic;
--SOCKET RX STREAM
signal INPUT_SOCKET : std_logic_vector(15 downto 0);
signal INPUT_SOCKET_STB : std_logic;
signal INPUT_SOCKET_ACK : std_logic;
--SOCKET TX STREAM
signal OUTPUT_SOCKET : std_logic_vector(15 downto 0);
signal OUTPUT_SOCKET_STB : std_logic;
signal OUTPUT_SOCKET_ACK : std_logic;
-- --SSeg output
-- signal Tosseg_dat : std_logic_vector(15 downto 0);
-- signal ssflags : std_logic_vector;
begin
initPhyNexys3_inst1 : initPhyNexys3 port map (
clk => CLK,
reset => RST,
phy_reset => PHY_RESET,
out_en => nOEN
);
ethernet_inst_1 : ethernet port map(
CLK => CLK,
RST => INTERNAL_RST,
--MII IF
TXCLK => TXCLK,
TXER => INTERNAL_TXER,
TXEN => INTERNAL_TXEN,
TXD => INTERNAL_TXD,
RXCLK => INTERNAL_RXCLK,--ok
RXER => RXER_BUF,
RXDV => RXDV,
RXD => RXD_BUF, -- ok
COL => COL_BUF, -- ok
PhyCRS => CRS, -- ok
--RX STREAM
TX => ETH_TX,
TX_STB => ETH_TX_STB,
TX_ACK => ETH_TX_ACK,
--RX STREAM
RX => ETH_RX,
RX_STB => ETH_RX_STB,
RX_ACK => ETH_RX_ACK,
BtnL => GPIO_BUTTONS(0),
SW0 => GPIO_SWITCHES(0),
--LEDs and 7seg AMER
GPIO_LEDS => GPIO_LEDS(7 downto 4),
sseg_out => sseg_out,
anodes_out => anodes_out
);
SERVER_INST_1 : SERVER port map(
CLK => CLK,
RST => INTERNAL_RST,
--ETH RX STREAM
INPUT_ETH_RX => ETH_RX,
INPUT_ETH_RX_STB => ETH_RX_STB,
INPUT_ETH_RX_ACK => ETH_RX_ACK,
--ETH TX STREAM
OUTPUT_ETH_TX => ETH_TX,
OUTPUT_ETH_TX_STB => ETH_TX_STB,
OUTPUT_ETH_TX_ACK => ETH_TX_ACK,
--SOCKET STREAM
INPUT_SOCKET => INPUT_SOCKET,
INPUT_SOCKET_STB => INPUT_SOCKET_STB,
INPUT_SOCKET_ACK => INPUT_SOCKET_ACK,
--SOCKET STREAM
OUTPUT_SOCKET => OUTPUT_SOCKET,
OUTPUT_SOCKET_STB => OUTPUT_SOCKET_STB,
OUTPUT_SOCKET_ACK => OUTPUT_SOCKET_ACK
);
USER_DESIGN_INST_1 : USER_DESIGN port map(
CLK => CLK,
RST => INTERNAL_RST,
OUTPUT_LEDS => OUTPUT_LEDS,
OUTPUT_LEDS_STB => OUTPUT_LEDS_STB,
OUTPUT_LEDS_ACK => OUTPUT_LEDS_ACK,
INPUT_SWITCHES => INPUT_SWITCHES,
INPUT_SWITCHES_STB => INPUT_SWITCHES_STB,
INPUT_SWITCHES_ACK => INPUT_SWITCHES_ACK,
INPUT_BUTTONS => INPUT_BUTTONS,
INPUT_BUTTONS_STB => INPUT_BUTTONS_STB,
INPUT_BUTTONS_ACK => INPUT_BUTTONS_ACK,
--RS232 RX STREAM
INPUT_RS232_RX => INPUT_RS232_RX,
INPUT_RS232_RX_STB => INPUT_RS232_RX_STB,
INPUT_RS232_RX_ACK => INPUT_RS232_RX_ACK,
--RS232 TX STREAM
OUTPUT_RS232_TX => OUTPUT_RS232_TX,
OUTPUT_RS232_TX_STB => OUTPUT_RS232_TX_STB,
OUTPUT_RS232_TX_ACK => OUTPUT_RS232_TX_ACK,
--SOCKET STREAM
INPUT_SOCKET => OUTPUT_SOCKET,
INPUT_SOCKET_STB => OUTPUT_SOCKET_STB,
INPUT_SOCKET_ACK => OUTPUT_SOCKET_ACK,
--SOCKET STREAM
OUTPUT_SOCKET => INPUT_SOCKET,
OUTPUT_SOCKET_STB => INPUT_SOCKET_STB,
OUTPUT_SOCKET_ACK => INPUT_SOCKET_ACK
);
SERIAL_OUTPUT_INST_1 : serial_output generic map(
CLOCK_FREQUENCY => 48000000,--48000000,
BAUD_RATE => 115200
)port map(
CLK => CLK,--fx2Clk, --AMER
RST => INTERNAL_RST,
TX => RS232_TX,
IN1 => OUTPUT_RS232_TX(7 downto 0),
IN1_STB => OUTPUT_RS232_TX_STB,
IN1_ACK => OUTPUT_RS232_TX_ACK
);
SERIAL_INPUT_INST_1 : SERIAL_INPUT generic map(
CLOCK_FREQUENCY => 50000000,--48000000,
BAUD_RATE => 115200
) port map (
CLK => CLK,--fx2Clk, -- AMER
RST => INTERNAL_RST,
RX => RS232_RX,
OUT1 => INPUT_RS232_RX(7 downto 0),
OUT1_STB => INPUT_RS232_RX_STB,
OUT1_ACK => INPUT_RS232_RX_ACK
);
INPUT_RS232_RX(15 downto 8) <= (others => '0');
process
begin
wait until rising_edge(CLK);
NOT_LOCKED <= not LOCKED_INTERNAL;
INTERNAL_RST <= NOT_LOCKED;
-- Desactivated the following to be used as test indicators
if OUTPUT_LEDS_STB = '1' then --AMER
GPIO_LEDS(3 downto 0) <= OUTPUT_LEDS(3 downto 0); -- AMER
end if;-- AMER
OUTPUT_LEDS_ACK <= '1';
INPUT_SWITCHES_STB <= '1';
GPIO_SWITCHES_D <= GPIO_SWITCHES;
INPUT_SWITCHES(7 downto 0) <= GPIO_SWITCHES_D;
INPUT_SWITCHES(15 downto 8) <= (others => '0');
INPUT_BUTTONS_STB <= '1';
GPIO_BUTTONS_D <= GPIO_BUTTONS;
INPUT_BUTTONS(3 downto 0) <= GPIO_BUTTONS_D;
INPUT_BUTTONS(15 downto 4) <= (others => '0');
end process;
-------------------------
-- Output Output
-- Clock Freq (MHz)
-------------------------
-- CLK_OUT1 50.000
-- CLK_OUT2 100.000
-- CLK_OUT3 25.000
-- CLK_OUT4 200.000
----------------------------------
-- Input Clock Input Freq (MHz)
----------------------------------
-- primary 100.000 ****** the main clock on Nexys3 is 100 Mhz
-- Input buffering
--------------------------------------
clkin1_buf : IBUFG
port map
(O => clkin1,
I => CLK_IN);
BUFG_INST9 : BUFG
port map
(O => RXCLK_BUF,
I => RXCLK_INT);
fx2Clk_in_buf : IBUFG
port map
(O => fx2Clk,
I => fx2Clk_pin);
--- The DCM has an active high RST input so RST_INV hould be same as RST
RST_INV <= RST;------------not RST; -- AMER
dcm_sp_inst: DCM_SP ----------------------------
generic map
(CLKDV_DIVIDE => 2.000,
CLKFX_DIVIDE => 8, -- to get 25 MHz
CLKFX_MULTIPLY => 2, -- to get 25 MHz
CLKIN_DIVIDE_BY_2 => FALSE,
CLKIN_PERIOD => 10.0, -- input main clock = 100 MHz
CLKOUT_PHASE_SHIFT => "NONE",
CLK_FEEDBACK => "1X",
DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS",
PHASE_SHIFT => 0,
STARTUP_WAIT => FALSE)
port map
-- Input clock
(CLKIN => clkin1, -- main clock input = 100 MHz
CLKFB => clkfb,
-- Output clocks
CLK0 => clk0, -- 100 MHz
CLK90 => open,
CLK180 => open,
CLK270 => open,
CLK2X => clk2x,-- 200 MHz
CLK2X180 => open,
CLKFX => clkfx, -- 25 MHz
CLKFX180 => clkfx180, -- 25 MHz @ 180 deg.
CLKDV => clkdv,
-- Ports for dynamic phase shift
PSCLK => '0',
PSEN => '0',
PSINCDEC => '0',
PSDONE => open,
-- Other control and status signals
LOCKED => TX_LOCKED,
STATUS => status_internal,
RST => RST_INV,
-- Unused pin, tie low
DSSEN => '0');
----------------------------------------------------------- AMER
dcm_sp_inst2: DCM_SP -------------RXCLK----------
generic map
(CLKDV_DIVIDE => 2.000,
CLKFX_DIVIDE => 4,
CLKFX_MULTIPLY => 5,
CLKIN_DIVIDE_BY_2 => FALSE,
CLKIN_PERIOD => 40.0, -- for rxclk = 25 MHz
CLKOUT_PHASE_SHIFT => "FIXED",
CLK_FEEDBACK => "1X",
DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS",
PHASE_SHIFT => 14,
STARTUP_WAIT => FALSE)
port map
-- Input clock
(CLKIN => RXCLK_BUF, -- 25 MHz from Phy
CLKFB => INTERNAL_RXCLK, --ok
-- Output clocks
CLK0 => INTERNAL_RXCLK_BUF,
CLK90 => open,
CLK180 => open,
CLK270 => open,
CLK2X => open,
CLK2X180 => open,
CLKFX => open,
CLKFX180 => open,
CLKDV => open,
-- Ports for dynamic phase shift
PSCLK => '0',
PSEN => '0',
PSINCDEC => '0',
PSDONE => open,
-- Other control and status signals
LOCKED => open,
STATUS => open,
RST => RST_INV,
-- Unused pin, tie low
DSSEN => '0');
--------------------------------------------------------- AMER
-- Output buffering
-------------------------------------
clkfb <= CLK_OUT2; -- 100 MHz
BUFG_INST7 : BUFG
port map
(O => INTERNAL_RXCLK,
I => INTERNAL_RXCLK_BUF);
BUFG_INST1 : BUFG
port map
(O => CLK_OUT1,
I => clkdv);
BUFG_INST2 : BUFG
port map
(O => CLK_OUT2, -- 100 MHz
I => clk0);
BUFG_INST3 : BUFG
port map
(O => CLK_OUT3,
I => clkfx);
BUFG_INST4 : BUFG
port map
(O => CLK_OUT3_N,
I => clkfx180);
BUFG_INST5 : BUFG
port map
(O => CLK_OUT4,
I => clk2x);
-- Input buffering
-------------------- RXCLK/PHYAD1 io pin --------
IOBUF_INST1 : IOBUF
port map
(O => RXCLK_INT,
IO => RXCLK, -- RXCLK/PHYAD1 io pin
I => '1', ---PhyAddress 1
T => nOEN); --3-state enable input
-------------------------- RXER/RXD4/PHYAD0 --------------------------
IOBUF_INST2 : IOBUF
port map
(O => RXER_BUF,
IO => RXER,
I => '1', ---(PhyAddress bit 0) = 1
T => nOEN); --3-state enable input
---------------------------- COL/CRS_DV/MODE2 -------------------------------------
IOBUF_INST3 : IOBUF
port map
(O => COL_BUF,
IO => PhyCol, --COL_BUF
I => '0', ---(MODE2 bit) = 0
T => nOEN); --3-state enable input
------------------------------- nINT/TXER/TXD4-----------------------
-----------------------------------------------------------------
IOBUF_INST5 : IOBUF ------- RXD0/MODE0----
port map
(O => RXD_BUF(0), ---RXD0 input pin
IO => RXD(0), -- RXD0/MODE0 io pin
I => '1', -- MODE0 (mode bit0) = 1
T => nOEN); --3-state enable input
-----------------------------------------------------------------
IOBUF_INST6 : IOBUF ------- RXD1/MODE1----
port map
(O => RXD_BUF(1), ---(interrupt input) = 1, not used
IO => RXD(1), -- RXD1/MODE1 io pin
I => '1', -- MODE1 (mode bit1) = 1
T => nOEN); --3-state enable input
-----------------------------------------------------------------
IOBUF_INST7 : IOBUF ------- RXD2/RMIISEL----
port map
(O => RXD_BUF(2), ---(interrupt input) = 1, not used
IO => RXD(2), -- RXD2/RMIISEL io pin
I => '0', -- RMIISEL = 0 (MII mode is selected)
T => nOEN); --3-state enable input
-----------------------------------------------------------------
IOBU_INST8 : IOBUF ------- RXD3/PHYAD2----
port map
(O => RXD_BUF(3), ---(interrupt input) = 1, not used
IO => RXD(3), -- RXD3/PHYAD2 io pin
I => '0', -- PHYAD2 (Phy address bit 2)= 0
T => nOEN); --3-state enable input
-----------------------------------------------------------------
LOCKED_INTERNAL <= TX_LOCKED;
------------------------------------------------------ AMER
-- Use ODDRs for clock/data forwarding
--------------------------------------
ODDR2_INST2_GENERATE : for I in 0 to 3 generate
ODDR2_INST2 : ODDR2
generic map(
DDR_ALIGNMENT => "NONE", -- Sets output alignment to "NONE", "C0", "C1"
INIT => '0', -- Sets initial state of the Q output to '0' or '1'
SRTYPE => "SYNC"
) port map (
Q => TXD(I), -- 1-bit output data
C0 => CLK_OUT3, -- 1-bit clock input
C1 => CLK_OUT3_N, -- 1-bit clock input
CE => '1', -- 1-bit clock enable input
D0 => INTERNAL_TXD(I), -- 1-bit data input (associated with C0)
D1 => INTERNAL_TXD(I), -- 1-bit data input (associated with C1)
R => '0', -- 1-bit reset input
S => '0' -- 1-bit set input
);
end generate;
ODDR2_INST3 : ODDR2
generic map(
DDR_ALIGNMENT => "NONE", -- Sets output alignment to "NONE", "C0", "C1"
INIT => '0', -- Sets initial state of the Q output to '0' or '1'
SRTYPE => "SYNC"
) port map (
Q => TXEN, -- 1-bit output data
C0 => CLK_OUT3, -- 1-bit clock input
C1 => CLK_OUT3_N, -- 1-bit clock input
CE => '1', -- 1-bit clock enable input
D0 => INTERNAL_TXEN, -- 1-bit data input (associated with C0)
D1 => INTERNAL_TXEN, -- 1-bit data input (associated with C1)
R => '0', -- 1-bit reset input
S => '0' -- 1-bit set input
);
ODDR2_INST4 : ODDR2
generic map(
DDR_ALIGNMENT => "NONE", -- Sets output alignment to "NONE", "C0", "C1"
INIT => '0', -- Sets initial state of the Q output to '0' or '1'
SRTYPE => "SYNC"
) port map (
Q => TXER, -- 1-bit output data
C0 => CLK_OUT3, -- 1-bit clock input
C1 => CLK_OUT3_N, -- 1-bit clock input
CE => '1', -- 1-bit clock enable input
D0 => INTERNAL_TXER, --ok -- 1-bit data input (associated with C0)
D1 => INTERNAL_TXER, --ok -- 1-bit data input (associated with C1)
R => '0', -- 1-bit reset input
S => '0' -- 1-bit set input
);
------------------------------------------------------ AMER
-- Chips CLK frequency selection
-------------------------------------
CLK <= CLK_OUT1; --50 MHz
--CLK <= CLK_OUT2; --100 MHz
--CLK <= CLK_OUT3; --25 MHz
--CLK <= CLK_OUT4; --200 MHz
end architecture RTL;
| mit | 28a5b2adbe8da52db6a3804d64c79425 | 0.459101 | 3.673729 | false | false | false | false |
impedimentToProgress/UCI-BlueChip | AttackFiles/Attacks/privEsc/lib/grlib/stdlib/stdlib.vhd | 2 | 13,002 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2006, Gaisler Research AB - all rights reserved.
--
-- ANY USE OR REDISTRIBUTION IN PART OR IN WHOLE MUST BE HANDLED IN
-- ACCORDANCE WITH THE GAISLER LICENSE AGREEMENT AND MUST BE APPROVED
-- IN ADVANCE IN WRITING.
-----------------------------------------------------------------------------
-- Package: stdlib
-- File: stdlib.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: Package for common VHDL functions
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-- pragma translate_off
use std.textio.all;
-- pragma translate_on
library grlib;
use grlib.version.all;
package stdlib is
constant LIBVHDL_VERSION : integer := grlib_version;
constant LIBVHDL_BUILD : integer := grlib_build;
-- pragma translate_off
constant LIBVHDL_DATE : string := grlib_date;
-- pragma translate_on
constant zero32 : std_logic_vector(31 downto 0) := (others => '0');
constant zero64 : std_logic_vector(63 downto 0) := (others => '0');
constant one32 : std_logic_vector(31 downto 0) := (others => '1');
type log2arr is array(0 to 512) of integer;
constant log2 : log2arr := (
0,0,1,2,2,3,3,3,3,4,4,4,4,4,4,4,4,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,
6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,
7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,
7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,
8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,
8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,
8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,
8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,
others => 9);
constant log2x : log2arr := (
0,1,1,2,2,3,3,3,3,4,4,4,4,4,4,4,4,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,
6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,
7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,
7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,
8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,
8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,
8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,
8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,
others => 9);
function decode(v : std_logic_vector) return std_logic_vector;
function genmux(s,v : std_logic_vector) return std_ulogic;
function xorv(d : std_logic_vector) return std_ulogic;
function orv(d : std_logic_vector) return std_ulogic;
function andv(d : std_logic_vector) return std_ulogic;
function notx(d : std_logic_vector) return boolean;
function notx(d : std_ulogic) return boolean;
function "-" (d : std_logic_vector; i : integer) return std_logic_vector;
function "-" (i : integer; d : std_logic_vector) return std_logic_vector;
function "+" (d : std_logic_vector; i : integer) return std_logic_vector;
function "+" (i : integer; d : std_logic_vector) return std_logic_vector;
function "-" (d : std_logic_vector; i : std_ulogic) return std_logic_vector;
function "+" (d : std_logic_vector; i : std_ulogic) return std_logic_vector;
function "-" (a, b : std_logic_vector) return std_logic_vector;
function "+" (a, b : std_logic_vector) return std_logic_vector;
function "*" (a, b : std_logic_vector) return std_logic_vector;
function signed_mul (a, b : std_logic_vector) return std_logic_vector;
--function ">" (a, b : std_logic_vector) return boolean;
function "<" (i : integer; b : std_logic_vector) return boolean;
function conv_integer(v : std_logic_vector) return integer;
function conv_integer(v : std_logic) return integer;
function conv_std_logic_vector(i : integer; w : integer) return std_logic_vector;
function conv_std_logic_vector_signed(i : integer; w : integer) return std_logic_vector;
function conv_std_logic(b : boolean) return std_ulogic;
-- Reporting and diagnostics
-- pragma translate_off
function tost(v:std_logic_vector) return string;
function tost(v:std_logic) return string;
function tost(i : integer) return string;
procedure print(s : string);
component report_version
generic (msg1, msg2, msg3, msg4 : string := ""; mdel : integer := 4);
end component;
-- pragma translate_on
end;
package body stdlib is
function notx(d : std_logic_vector) return boolean is
variable res : boolean;
begin
res := true;
-- pragma translate_off
res := not is_x(d);
-- pragma translate_on
return (res);
end;
function notx(d : std_ulogic) return boolean is
variable res : boolean;
begin
res := true;
-- pragma translate_off
res := not is_x(d);
-- pragma translate_on
return (res);
end;
-- generic decoder
function decode(v : std_logic_vector) return std_logic_vector is
variable res : std_logic_vector((2**v'length)-1 downto 0);
variable i : integer range res'range;
begin
res := (others => '0'); i := 0;
if notx(v) then i := to_integer(unsigned(v)); end if;
res(i) := '1';
return(res);
end;
-- generic multiplexer
function genmux(s,v : std_logic_vector) return std_ulogic is
variable res : std_logic_vector(v'length-1 downto 0);
variable i : integer range res'range;
begin
res := v; i := 0;
if notx(s) then i := to_integer(unsigned(s)); end if;
return(res(i));
end;
-- vector XOR
function xorv(d : std_logic_vector) return std_ulogic is
variable tmp : std_ulogic;
begin
tmp := '0';
for i in d'range loop tmp := tmp xor d(i); end loop;
return(tmp);
end;
-- vector OR
function orv(d : std_logic_vector) return std_ulogic is
variable tmp : std_ulogic;
begin
tmp := '0';
for i in d'range loop tmp := tmp or d(i); end loop;
return(tmp);
end;
-- vector AND
function andv(d : std_logic_vector) return std_ulogic is
variable tmp : std_ulogic;
begin
tmp := '1';
for i in d'range loop tmp := tmp and d(i); end loop;
return(tmp);
end;
-- unsigned multiplication
function "*" (a, b : std_logic_vector) return std_logic_vector is
variable z : std_logic_vector(a'length+b'length-1 downto 0);
begin
if notx(a&b) then
return(std_logic_vector(unsigned(a) * unsigned(b)));
-- pragma translate_off
else
z := (others =>'X'); return(z);
-- pragma translate_on
end if;
end;
-- signed multiplication
function signed_mul (a, b : std_logic_vector) return std_logic_vector is
variable z : std_logic_vector(a'length+b'length-1 downto 0);
begin
if notx(a&b) then
return(std_logic_vector(signed(a) * signed(b)));
-- pragma translate_off
else
z := (others =>'X'); return(z);
-- pragma translate_on
end if;
end;
-- unsigned addition
function "+" (a, b : std_logic_vector) return std_logic_vector is
variable x : std_logic_vector(a'length-1 downto 0);
variable y : std_logic_vector(b'length-1 downto 0);
begin
if notx(a&b) then
return(std_logic_vector(unsigned(a) + unsigned(b)));
-- pragma translate_off
else
x := (others =>'X'); y := (others =>'X');
if (x'length > y'length) then return(x); else return(y); end if;
-- pragma translate_on
end if;
end;
function "+" (i : integer; d : std_logic_vector) return std_logic_vector is
variable x : std_logic_vector(d'length-1 downto 0);
begin
if notx(d) then
return(std_logic_vector(unsigned(d) + i));
-- pragma translate_off
else x := (others =>'X'); return(x);
-- pragma translate_on
end if;
end;
function "+" (d : std_logic_vector; i : integer) return std_logic_vector is
variable x : std_logic_vector(d'length-1 downto 0);
begin
if notx(d) then
return(std_logic_vector(unsigned(d) + i));
-- pragma translate_off
else x := (others =>'X'); return(x);
-- pragma translate_on
end if;
end;
function "+" (d : std_logic_vector; i : std_ulogic) return std_logic_vector is
variable x : std_logic_vector(d'length-1 downto 0);
variable y : std_logic_vector(0 downto 0);
begin
y(0) := i;
if notx(d) then
return(std_logic_vector(unsigned(d) + unsigned(y)));
-- pragma translate_off
else x := (others =>'X'); return(x);
-- pragma translate_on
end if;
end;
-- unsigned subtraction
function "-" (a, b : std_logic_vector) return std_logic_vector is
variable x : std_logic_vector(a'length-1 downto 0);
variable y : std_logic_vector(b'length-1 downto 0);
begin
if notx(a&b) then
return(std_logic_vector(unsigned(a) - unsigned(b)));
-- pragma translate_off
else
x := (others =>'X'); y := (others =>'X');
if (x'length > y'length) then return(x); else return(y); end if;
-- pragma translate_on
end if;
end;
function "-" (d : std_logic_vector; i : integer) return std_logic_vector is
variable x : std_logic_vector(d'length-1 downto 0);
begin
if notx(d) then
return(std_logic_vector(unsigned(d) - i));
-- pragma translate_off
else x := (others =>'X'); return(x);
-- pragma translate_on
end if;
end;
function "-" (i : integer; d : std_logic_vector) return std_logic_vector is
variable x : std_logic_vector(d'length-1 downto 0);
begin
if notx(d) then
return(std_logic_vector(i - unsigned(d)));
-- pragma translate_off
else x := (others =>'X'); return(x);
-- pragma translate_on
end if;
end;
function "-" (d : std_logic_vector; i : std_ulogic) return std_logic_vector is
variable x : std_logic_vector(d'length-1 downto 0);
variable y : std_logic_vector(0 downto 0);
begin
y(0) := i;
if notx(d) then
return(std_logic_vector(unsigned(d) - unsigned(y)));
-- pragma translate_off
else x := (others =>'X'); return(x);
-- pragma translate_on
end if;
end;
function ">=" (a, b : std_logic_vector) return boolean is
begin
return(unsigned(a) >= unsigned(b));
end;
function "<" (i : integer; b : std_logic_vector) return boolean is
begin
return( i < to_integer(unsigned(b)));
end;
function ">" (a, b : std_logic_vector) return boolean is
begin
return(unsigned(a) > unsigned(b));
end;
function conv_integer(v : std_logic_vector) return integer is
begin
if notx(v) then return(to_integer(unsigned(v)));
else return(0); end if;
end;
function conv_integer(v : std_logic) return integer is
begin
if notx(v) then
if v = '1' then return(1);
else return(0); end if;
else return(0); end if;
end;
function conv_std_logic_vector(i : integer; w : integer) return std_logic_vector is
variable tmp : std_logic_vector(w-1 downto 0);
begin
tmp := std_logic_vector(to_unsigned(i, w));
return(tmp);
end;
function conv_std_logic_vector_signed(i : integer; w : integer) return std_logic_vector is
variable tmp : std_logic_vector(w-1 downto 0);
begin
tmp := std_logic_vector(to_signed(i, w));
return(tmp);
end;
function conv_std_logic(b : boolean) return std_ulogic is
begin
if b then return('1'); else return('0'); end if;
end;
-- pragma translate_off
subtype nibble is std_logic_vector(3 downto 0);
function todec(i:integer) return character is
begin
case i is
when 0 => return('0');
when 1 => return('1');
when 2 => return('2');
when 3 => return('3');
when 4 => return('4');
when 5 => return('5');
when 6 => return('6');
when 7 => return('7');
when 8 => return('8');
when 9 => return('9');
when others => return('0');
end case;
end;
function tohex(n:nibble) return character is
begin
case n is
when "0000" => return('0');
when "0001" => return('1');
when "0010" => return('2');
when "0011" => return('3');
when "0100" => return('4');
when "0101" => return('5');
when "0110" => return('6');
when "0111" => return('7');
when "1000" => return('8');
when "1001" => return('9');
when "1010" => return('a');
when "1011" => return('b');
when "1100" => return('c');
when "1101" => return('d');
when "1110" => return('e');
when "1111" => return('f');
when others => return('X');
end case;
end;
function tost(v:std_logic_vector) return string is
constant vlen : natural := v'length; --'
constant slen : natural := (vlen+3)/4;
variable vv : std_logic_vector(0 to slen*4-1) := (others => '0');
variable s : string(1 to slen);
variable nz : boolean := false;
variable index : integer := -1;
begin
vv(slen*4-vlen to slen*4-1) := v;
for i in 0 to slen-1 loop
if (vv(i*4 to i*4+3) = "0000") and nz and (i /= (slen-1)) then
index := i;
else
nz := false;
s(i+1) := tohex(vv(i*4 to i*4+3));
end if;
end loop;
if ((index +2) = slen) then return(s(slen to slen));
else return(string'("0x") & s(index+2 to slen)); end if; --'
end;
function tost(v:std_logic) return string is
begin
if to_x01(v) = '1' then return("1"); else return("0"); end if;
end;
function tost(i : integer) return string is
variable L : line;
variable s, x : string(1 to 128);
variable n, tmp : integer := 0;
begin
tmp := i;
loop
s(128-n) := todec(tmp mod 10);
tmp := tmp / 10;
n := n+1;
if tmp = 0 then exit; end if;
end loop;
x(1 to n) := s(129-n to 128);
return(x(1 to n));
end;
procedure print(s : string) is
variable L : line;
begin
L := new string'(s); writeline(output, L);
end;
-- pragma translate_on
end;
| mit | b6d6b67f03c48a86f85a4f1bb2915674 | 0.634749 | 2.680825 | false | false | false | false |
cafe-alpha/wascafe | v13/r07c_de10_20201014_abus4/wasca/synthesis/submodules/Altera_UP_SD_Card_Interface.vhd | 7 | 20,738 | -- (C) 2001-2015 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
-------------------------------------------------------------------------------------
-- This module is an interface to the Secure Data Card. This module is intended to be
-- used with the DE2 board.
--
-- This version of the interface supports only a 1-bit serial data transfer. This
-- allows the interface to support a MultiMedia card as well.
--
-- NOTES/REVISIONS:
-------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity Altera_UP_SD_Card_Interface is
port
(
i_clock : in std_logic;
i_reset_n : in std_logic;
-- Command interface
b_SD_cmd : inout std_logic;
b_SD_dat : inout std_logic;
b_SD_dat3 : inout std_logic;
i_command_ID : in std_logic_vector(5 downto 0);
i_argument : in std_logic_vector(31 downto 0);
i_user_command_ready : in std_logic;
o_SD_clock : out std_logic;
o_card_connected : out std_logic;
o_command_completed : out std_logic;
o_command_valid : out std_logic;
o_command_timed_out : out std_logic;
o_command_crc_failed : out std_logic;
-- Buffer access
i_buffer_enable : in std_logic;
i_buffer_address : in std_logic_vector(7 downto 0);
i_buffer_write : in std_logic;
i_buffer_data_in : in std_logic_vector(15 downto 0);
o_buffer_data_out : out std_logic_vector(15 downto 0);
-- Show SD Card registers as outputs
o_SD_REG_card_identification_number : out std_logic_vector(127 downto 0);
o_SD_REG_relative_card_address : out std_logic_vector(15 downto 0);
o_SD_REG_operating_conditions_register : out std_logic_vector(31 downto 0);
o_SD_REG_card_specific_data : out std_logic_vector(127 downto 0);
o_SD_REG_status_register : out std_logic_vector(31 downto 0);
o_SD_REG_response_R1 : out std_logic_vector(31 downto 0);
o_SD_REG_status_register_valid : out std_logic
);
end entity;
architecture rtl of Altera_UP_SD_Card_Interface is
component Altera_UP_SD_Card_Clock
port
(
i_clock : in std_logic;
i_reset_n : in std_logic;
i_enable : in std_logic;
i_mode : in std_logic; -- 0 for card identification mode, 1 for data transfer mode.
o_SD_clock : out std_logic;
o_clock_mode : out std_logic;
o_trigger_receive : out std_logic;
o_trigger_send : out std_logic
);
end component;
component Altera_UP_SD_CRC7_Generator
port
(
i_clock : in std_logic;
i_enable : in std_logic;
i_reset_n : in std_logic;
i_shift : in std_logic;
i_datain : in std_logic;
o_dataout : out std_logic;
o_crcout : out std_logic_vector(6 downto 0)
);
end component;
component Altera_UP_SD_CRC16_Generator
port
(
i_clock : in std_logic;
i_enable : in std_logic;
i_reset_n : in std_logic;
i_shift : in std_logic;
i_datain : in std_logic;
o_dataout : out std_logic;
o_crcout : out std_logic_vector(15 downto 0)
);
end component;
component Altera_UP_SD_Signal_Trigger
port
(
i_clock : in std_logic;
i_reset_n : in std_logic;
i_signal : in std_logic;
o_trigger : out std_logic
);
end component;
component Altera_UP_SD_Card_48_bit_Command_Generator
generic (
-- Basic commands
COMMAND_0_GO_IDLE : STD_LOGIC_VECTOR(5 downto 0) := "000000";
COMMAND_2_ALL_SEND_CID : STD_LOGIC_VECTOR(5 downto 0) := "000010";
COMMAND_3_SEND_RCA : STD_LOGIC_VECTOR(5 downto 0) := "000011";
COMMAND_4_SET_DSR : STD_LOGIC_VECTOR(5 downto 0) := "000100";
COMMAND_6_SWITCH_FUNCTION : STD_LOGIC_VECTOR(5 downto 0) := "000110";
COMMAND_7_SELECT_CARD : STD_LOGIC_VECTOR(5 downto 0) := "000111";
COMMAND_9_SEND_CSD : STD_LOGIC_VECTOR(5 downto 0) := "001001";
COMMAND_10_SEND_CID : STD_LOGIC_VECTOR(5 downto 0) := "001010";
COMMAND_12_STOP_TRANSMISSION : STD_LOGIC_VECTOR(5 downto 0) := "001100";
COMMAND_13_SEND_STATUS : STD_LOGIC_VECTOR(5 downto 0) := "001101";
COMMAND_15_GO_INACTIVE : STD_LOGIC_VECTOR(5 downto 0) := "001111";
-- Block oriented read/write/lock commands
COMMAND_16_SET_BLOCK_LENGTH : STD_LOGIC_VECTOR(5 downto 0) := "010000";
-- Block oriented read commands
COMMAND_17_READ_BLOCK : STD_LOGIC_VECTOR(5 downto 0) := "010001";
COMMAND_18_READ_MULTIPLE_BLOCKS : STD_LOGIC_VECTOR(5 downto 0) := "010010";
-- Block oriented write commands
COMMAND_24_WRITE_BLOCK : STD_LOGIC_VECTOR(5 downto 0) := "011000";
COMMAND_25_WRITE_MULTIPLE_BLOCKS : STD_LOGIC_VECTOR(5 downto 0) := "011001";
COMMAND_27_PROGRAM_CSD : STD_LOGIC_VECTOR(5 downto 0) := "011011";
-- Block oriented write-protection commands
COMMAND_28_SET_WRITE_PROTECT : STD_LOGIC_VECTOR(5 downto 0) := "011100";
COMMAND_29_CLEAR_WRITE_PROTECT : STD_LOGIC_VECTOR(5 downto 0) := "011101";
COMMAND_30_SEND_PROTECTED_GROUPS : STD_LOGIC_VECTOR(5 downto 0) := "011110";
-- Erase commands
COMMAND_32_ERASE_BLOCK_START : STD_LOGIC_VECTOR(5 downto 0) := "100000";
COMMAND_33_ERASE_BLOCK_END : STD_LOGIC_VECTOR(5 downto 0) := "100001";
COMMAND_38_ERASE_SELECTED_GROUPS : STD_LOGIC_VECTOR(5 downto 0) := "100110";
-- Block lock commands
COMMAND_42_LOCK_UNLOCK : STD_LOGIC_VECTOR(5 downto 0) := "101010";
-- Command Type Settings
COMMAND_55_APP_CMD : STD_LOGIC_VECTOR(5 downto 0) := "110111";
COMMAND_56_GEN_CMD : STD_LOGIC_VECTOR(5 downto 0) := "111000";
-- Application Specific commands - must be preceeded with command 55.
ACOMMAND_6_SET_BUS_WIDTH : STD_LOGIC_VECTOR(5 downto 0) := "000110";
ACOMMAND_13_SD_STATUS : STD_LOGIC_VECTOR(5 downto 0) := "001101";
ACOMMAND_22_SEND_NUM_WR_BLOCKS : STD_LOGIC_VECTOR(5 downto 0) := "010100";
ACOMMAND_23_SET_BLK_ERASE_COUNT : STD_LOGIC_VECTOR(5 downto 0) := "010101";
ACOMMAND_41_SEND_OP_CONDITION : STD_LOGIC_VECTOR(5 downto 0) := "101001";
ACOMMAND_42_SET_CLR_CARD_DETECT : STD_LOGIC_VECTOR(5 downto 0) := "101010";
ACOMMAND_51_SEND_SCR : STD_LOGIC_VECTOR(5 downto 0) := "110011";
-- First custom_command
FIRST_NON_PREDEFINED_COMMAND : STD_LOGIC_VECTOR(3 downto 0) := "1010"
);
port
(
i_clock : in std_logic;
i_reset_n : in std_logic;
i_message_bit_out : in std_logic;
i_command_ID : in std_logic_vector(5 downto 0);
i_argument : in std_logic_vector(31 downto 0);
i_predefined_message : in std_logic_vector(3 downto 0);
i_generate : in std_logic;
i_DSR : in std_logic_vector(15 downto 0);
i_OCR : in std_logic_vector(31 downto 0);
i_RCA : in std_logic_vector(15 downto 0);
o_dataout : out std_logic;
o_message_done : out std_logic;
o_valid : out std_logic;
o_returning_ocr : out std_logic;
o_returning_cid : out std_logic;
o_returning_rca : out std_logic;
o_returning_csd : out std_logic;
o_returning_status : out std_logic;
o_data_read : out std_logic;
o_data_write : out std_logic;
o_wait_cmd_busy : out std_logic;
o_last_cmd_was_55 : out std_logic;
o_response_type : out std_logic_vector(2 downto 0)
);
end component;
component Altera_UP_SD_Card_Response_Receiver
generic (
TIMEOUT : std_logic_vector(7 downto 0) := "00111000";
BUSY_WAIT : std_logic_vector(7 downto 0) := "00110000";
PROCESSING_DELAY : std_logic_vector(7 downto 0) := "00001000"
);
port
(
i_clock : in std_logic;
i_reset_n : in std_logic;
i_begin : in std_logic;
i_scan_pulse : in std_logic;
i_datain : in std_logic;
i_wait_cmd_busy : in std_logic;
i_response_type : in std_logic_vector(2 downto 0);
o_data : out std_logic_vector(127 downto 0);
o_CRC_passed : out std_logic;
o_timeout : out std_logic;
o_done : out std_logic
);
end component;
component Altera_UP_SD_Card_Control_FSM
generic (
PREDEFINED_COMMAND_GET_STATUS : STD_LOGIC_VECTOR(3 downto 0) := "1001"
);
port
(
-- Clock and Reset signals
i_clock : in STD_LOGIC;
i_reset_n : in STD_LOGIC;
-- FSM Inputs
i_user_command_ready : in std_logic;
i_response_received : in STD_LOGIC;
i_response_timed_out : in STD_LOGIC;
i_response_crc_passed : in STD_LOGIC;
i_command_sent : in STD_LOGIC;
i_powerup_busy_n : in STD_LOGIC;
i_clocking_pulse_enable : in std_logic;
i_current_clock_mode : in std_logic;
i_user_message_valid : in std_logic;
i_last_cmd_was_55 : in std_logic;
i_allow_partial_rw : in std_logic;
-- FSM Outputs
o_generate_command : out STD_LOGIC;
o_predefined_command_ID : out STD_LOGIC_VECTOR(3 downto 0);
o_receive_response : out STD_LOGIC;
o_drive_CMD_line : out STD_LOGIC;
o_SD_clock_mode : out STD_LOGIC; -- 0 means slow clock for card identification, 1 means fast clock for transfer mode.
o_resetting : out std_logic;
o_card_connected : out STD_LOGIC;
o_command_completed : out std_logic;
o_clear_response_register : out std_logic;
o_enable_clock_generator : out std_logic
);
end component;
component Altera_UP_SD_Card_Buffer
generic (
TIMEOUT : std_logic_vector(15 downto 0) := "1111111111111111";
BUSY_WAIT : std_logic_vector(15 downto 0) := "0000001111110000"
);
port
(
i_clock : in std_logic;
i_reset_n : in std_logic;
-- 1 bit port to transmit and receive data on the data line.
i_begin : in std_logic;
i_sd_clock_pulse_trigger : in std_logic;
i_transmit : in std_logic;
i_1bit_data_in : in std_logic;
o_1bit_data_out : out std_logic;
o_operation_complete : out std_logic;
o_crc_passed : out std_logic;
o_timed_out : out std_logic;
o_dat_direction : out std_logic; -- set to 1 to send data, set to 0 to receive it.
-- 16 bit port to be accessed by a user circuit.
i_enable_16bit_port : in std_logic;
i_address_16bit_port : in std_logic_vector(7 downto 0);
i_write_16bit : in std_logic;
i_16bit_data_in : in std_logic_vector(15 downto 0);
o_16bit_data_out : out std_logic_vector(15 downto 0)
);
end component;
-- Local wires
-- REGISTERED
signal sd_mode : std_logic;
-- SD Card Registers:
signal SD_REG_card_identification_number : std_logic_vector(127 downto 0);
signal SD_REG_response_R1 : std_logic_vector(31 downto 0);
signal SD_REG_relative_card_address : std_logic_vector(15 downto 0);
signal SD_REG_driver_stage_register : std_logic_vector(15 downto 0);
signal SD_REG_card_specific_data : std_logic_vector(127 downto 0);
signal SD_REG_operating_conditions_register : std_logic_vector(31 downto 0);
signal SD_REG_status_register : std_logic_vector(31 downto 0);
signal SD_REG_status_register_valid : std_logic;
-- UNREGISTERED
signal data_from_buffer : std_logic_vector(15 downto 0);
signal clock_generator_mode, enable_generator, SD_clock, create_message : std_logic;
signal send_next_bit, receive_next_bit : std_logic;
signal timed_out, response_done, passed_crc, begin_reading_response, resetting : std_logic;
signal returning_cid, returning_rca, returning_csd, returning_ocr : std_logic;
signal response_type : std_logic_vector(2 downto 0);
signal message_valid, messange_sent, data_to_CMD_line, CMD_tristate_buffer_enable, message_sent : std_logic;
signal predef_message_ID : std_logic_vector(3 downto 0);
signal receive_data_out : std_logic_vector(127 downto 0);
signal data_line_done, data_line_crc, data_line_timeout, data_line_direction, data_line_out : std_logic;
signal data_read, data_write, wait_cmd_busy, clear_response_register : std_logic;
signal response_done_combined : std_logic;
signal timeout_combined : std_logic;
signal crc_combined, allow_partial_rw : std_logic;
signal begin_data_line_operations, last_cmd_was_55, message_sent_trigger, returning_status : std_logic;
signal data_line_sd_clock_pulse_trigger : std_logic;
begin
-- Glue logic
SD_REG_driver_stage_register <= (OTHERS => '0');
response_done_combined <= (response_done and (not data_read) and (not data_write)) or
(response_done and (data_read or data_write) and data_line_done);
timeout_combined <= (timed_out and (not data_read) and (not data_write)) or
(timed_out and (data_read or data_write) and data_line_timeout);
crc_combined <= (passed_crc and (not data_read) and (not data_write)) or
(passed_crc and (data_read or data_write) and data_line_crc);
begin_data_line_operations <= (data_read and message_sent) or (data_write and response_done);
-- Partial read and write are only allowed when both bit 79 (partial read allowed) is high and
-- bit 21 (partial write allowed) is high.
allow_partial_rw <= SD_REG_card_specific_data(79) and SD_REG_card_specific_data(21);
-- SD Card control registers
control_regs: process (i_clock, i_reset_n)
begin
if (i_reset_n = '0') then
SD_REG_operating_conditions_register <= (OTHERS => '0');
SD_REG_card_identification_number <= (OTHERS => '0');
SD_REG_relative_card_address <= (OTHERS => '0');
SD_REG_card_specific_data <= (OTHERS => '0');
SD_REG_status_register <= (OTHERS => '0');
SD_REG_response_R1 <= (OTHERS => '1');
SD_REG_status_register_valid <= '0';
elsif (rising_edge(i_clock)) then
if ((response_type = "001") and (response_done = '1') and (returning_status = '0') and (clear_response_register = '0')) then
SD_REG_response_R1 <= receive_data_out(31 downto 0);
elsif (clear_response_register = '1') then
SD_REG_response_R1 <= (OTHERS => '1');
end if;
if (resetting = '1') then
SD_REG_operating_conditions_register <= (OTHERS => '0');
elsif ((returning_ocr = '1') and (passed_crc = '1') and (response_done = '1') and (timed_out = '0')) then
SD_REG_operating_conditions_register <= receive_data_out(31 downto 0);
end if;
if ((returning_cid = '1') and (passed_crc = '1') and (response_done = '1') and (timed_out = '0')) then
SD_REG_card_identification_number <= receive_data_out;
end if;
if ((returning_rca = '1') and (passed_crc = '1') and (response_done = '1') and (timed_out = '0')) then
SD_REG_relative_card_address <= receive_data_out(31 downto 16);
end if;
if ((returning_csd = '1') and (passed_crc = '1') and (response_done = '1') and (timed_out = '0')) then
SD_REG_card_specific_data <= receive_data_out;
end if;
if (message_sent_trigger = '1') then
SD_REG_status_register_valid <= '0';
elsif ((returning_status = '1') and (passed_crc = '1') and (response_done = '1') and (timed_out = '0')) then
SD_REG_status_register <= receive_data_out(31 downto 0);
SD_REG_status_register_valid <= '1';
end if;
end if;
end process;
-- Instantiated components
command_generator: Altera_UP_SD_Card_48_bit_Command_Generator PORT MAP
(
i_clock => i_clock,
i_reset_n => i_reset_n,
i_message_bit_out => send_next_bit,
i_command_ID => i_command_ID,
i_argument => i_argument,
i_predefined_message => predef_message_ID,
i_generate => create_message,
i_DSR => SD_REG_driver_stage_register,
i_OCR => SD_REG_operating_conditions_register,
i_RCA => SD_REG_relative_card_address,
o_dataout => data_to_CMD_line,
o_message_done => message_sent,
o_valid => message_valid,
o_returning_ocr => returning_ocr,
o_returning_cid => returning_cid,
o_returning_rca => returning_rca,
o_returning_csd => returning_csd,
o_returning_status => returning_status,
o_data_read => data_read,
o_data_write => data_write,
o_wait_cmd_busy => wait_cmd_busy,
o_last_cmd_was_55 => last_cmd_was_55,
o_response_type => response_type
);
response_receiver: Altera_UP_SD_Card_Response_Receiver PORT MAP
(
i_clock => i_clock,
i_reset_n => i_reset_n,
i_begin => begin_reading_response,
i_scan_pulse => receive_next_bit,
i_datain => b_SD_cmd,
i_response_type => response_type,
i_wait_cmd_busy => wait_cmd_busy,
o_data => receive_data_out,
o_CRC_passed => passed_crc,
o_timeout => timed_out,
o_done => response_done
);
control_FSM: Altera_UP_SD_Card_Control_FSM PORT MAP
(
-- Clock and Reset signals
i_clock => i_clock,
i_reset_n => i_reset_n,
-- FSM Inputs
i_user_command_ready => i_user_command_ready,
i_clocking_pulse_enable => receive_next_bit,
i_response_received => response_done_combined,
i_response_timed_out => timeout_combined,
i_response_crc_passed => crc_combined,
i_command_sent => message_sent,
i_powerup_busy_n => SD_REG_operating_conditions_register(31),
i_current_clock_mode => clock_generator_mode,
i_user_message_valid => message_valid,
i_last_cmd_was_55 => last_cmd_was_55,
i_allow_partial_rw => allow_partial_rw,
-- FSM Outputs
o_generate_command => create_message,
o_predefined_command_ID => predef_message_ID,
o_receive_response => begin_reading_response,
o_drive_CMD_line => CMD_tristate_buffer_enable,
o_SD_clock_mode => sd_mode, -- 0 means slow clock for card identification, 1 means fast clock for transfer mode.
o_card_connected => o_card_connected,
o_command_completed => o_command_completed,
o_resetting => resetting,
o_clear_response_register => clear_response_register,
o_enable_clock_generator => enable_generator
);
clock_generator: Altera_UP_SD_Card_Clock PORT MAP
(
i_clock => i_clock,
i_reset_n => i_reset_n,
i_mode => sd_mode,
i_enable => enable_generator,
o_SD_clock => SD_clock,
o_clock_mode => clock_generator_mode,
o_trigger_receive => receive_next_bit,
o_trigger_send => send_next_bit
);
SD_clock_pulse_trigger: Altera_UP_SD_Signal_Trigger PORT MAP
(
i_clock => i_clock,
i_reset_n => i_reset_n,
i_signal => message_sent,
o_trigger => message_sent_trigger
);
data_line: Altera_UP_SD_Card_Buffer
port map
(
i_clock => i_clock,
i_reset_n => i_reset_n,
-- 1 bit port to transmit and receive data on the data line.
i_begin => begin_data_line_operations,
i_sd_clock_pulse_trigger => data_line_sd_clock_pulse_trigger,
i_transmit => data_write,
i_1bit_data_in => b_SD_dat,
o_1bit_data_out => data_line_out,
o_operation_complete => data_line_done,
o_crc_passed => data_line_crc,
o_timed_out => data_line_timeout,
o_dat_direction => data_line_direction,
-- 16 bit port to be accessed by a user circuit.
i_enable_16bit_port => i_buffer_enable,
i_address_16bit_port => i_buffer_address,
i_write_16bit => i_buffer_write,
i_16bit_data_in => i_buffer_data_in,
o_16bit_data_out => data_from_buffer
);
data_line_sd_clock_pulse_trigger <= (data_write and send_next_bit) or ((not data_write) and receive_next_bit);
-- Buffer output registers.
buff_regs: process(i_clock, i_reset_n, data_from_buffer)
begin
if (i_reset_n = '0') then
o_buffer_data_out <= (OTHERS=> '0');
elsif (rising_edge(i_clock)) then
o_buffer_data_out <= data_from_buffer;
end if;
end process;
-- Circuit outputs.
o_command_valid <= message_valid;
o_command_timed_out <= timeout_combined;
o_command_crc_failed <= not crc_combined;
o_SD_clock <= SD_clock;
b_SD_cmd <= data_to_CMD_line when (CMD_tristate_buffer_enable = '1') else 'Z';
b_SD_dat <= data_line_out when (data_line_direction = '1') else 'Z';
b_SD_dat3 <= 'Z'; -- Set SD card to SD mode.
-- SD card registers
o_SD_REG_card_identification_number <= SD_REG_card_identification_number;
o_SD_REG_relative_card_address <= SD_REG_relative_card_address;
o_SD_REG_operating_conditions_register <= SD_REG_operating_conditions_register;
o_SD_REG_card_specific_data <= SD_REG_card_specific_data;
o_SD_REG_status_register <= SD_REG_status_register;
o_SD_REG_response_R1 <= SD_REG_response_R1;
o_SD_REG_status_register_valid <= SD_REG_status_register_valid;
end rtl;
| gpl-2.0 | dc3a45fece517279377fb138a962612e | 0.653583 | 2.766911 | false | false | false | false |
impedimentToProgress/UCI-BlueChip | AttackFiles/Attacks/privEsc/lib/gaisler/ata/atahost_dma_fifo.vhd | 2 | 5,418 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: atahost_dma_fifo
-- File: atahost_dma_fifo.vhd
-- Author: Erik Jagre - Gaisler Research
-- Description: Generic FIFO, based on syncram in grlib
-----------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use ieee.std_logic_arith.all;
library techmap;
use techmap.gencomp.all;
entity atahost_dma_fifo is
generic(tech : integer:=0; abits : integer:=3;
dbits : integer:=32; depth : integer:=8);
port( clk : in std_logic;
reset : in std_logic;
write_enable : in std_logic;
read_enable : in std_logic;
data_in : in std_logic_vector(dbits-1 downto 0);
data_out : out std_logic_vector(dbits-1 downto 0);
write_error : out std_logic:='0';
read_error : out std_logic:='0';
level : out natural range 0 to depth;
empty : out std_logic:='1';
full : out std_logic:='0');
end;
architecture rtl of atahost_dma_fifo is
type state_type is (full_state, empty_state, idle_state);
type reg_type is record
state : state_type;
level : integer range 0 to depth;
aw : integer range 0 to depth;
ar : integer range 0 to depth;
data_o : std_logic_vector(dbits-1 downto 0);
rd : std_logic;
wr : std_logic;
erd : std_logic;
ewr : std_logic;
reset : std_logic;
adr : std_logic_vector(abits-1 downto 0);
end record;
constant RESET_VECTOR : reg_type := (empty_state,0,0,0,
conv_std_logic_vector(0,dbits),'0','0','0','0','0',(others=>'0'));
signal r,ri : reg_type;
signal s_ram_adr : std_logic_vector(abits-1 downto 0);
begin
-- comb:process(write_enable, read_enable, data_in,reset, r) Erik 2007-02-08
comb:process(write_enable, read_enable, reset, r)
variable v : reg_type;
variable vfull, vempty : std_logic;
begin
v:=r;
v.wr:=write_enable; v.rd:=read_enable; v.reset:=reset;
case r.state is
when full_state=>
if write_enable='1' and read_enable='0' and reset='0' then
v.ewr:='1'; v.state:=full_state;
elsif write_enable='0' and read_enable='1' and reset='0' then
v.adr:=conv_std_logic_vector(r.ar,abits);
if r.ar=depth-1 then v.ar:=0; else v.ar:=r.ar+1; end if;
v.level:=r.level-1;
if r.aw=v.ar then v.state:=empty_state;
else v.state:=idle_state; end if;
v.ewr:='0';
end if;
when empty_state=>
if write_enable='1' and read_enable='0' and reset='0' then
v.adr:=conv_std_logic_vector(r.aw,abits);
if r.aw=depth-1 then v.aw:=0; else v.aw:=r.aw+1; end if;
v.level:=r.level+1;
if v.aw=r.ar then v.state:=full_state;
else v.state:=idle_state; end if;
v.erd:='0';
elsif write_enable='0' and read_enable='1' and reset='0' then
v.erd:='1'; v.state:=empty_state;
end if;
when idle_state=>
if write_enable='1' and read_enable='0' and reset='0' then
v.adr:=conv_std_logic_vector(r.aw,abits);
if r.aw=depth-1 then v.aw:=0; else v.aw:=r.aw+1; end if;
v.level:=r.level+1;
if v.level=depth then v.state:=full_state;
else v.state:=idle_state; end if;
elsif write_enable='0' and read_enable='1' and reset='0' then
v.adr:=conv_std_logic_vector(r.ar,abits);
if r.ar=depth-1 then v.ar:=0; else v.ar:=r.ar+1; end if;
v.level:=r.level-1;
if v.level=0 then v.state:=empty_state;
else v.state:=idle_state; end if;
end if;
end case;
if r.level=0 then vempty:='1'; vfull:='0';
elsif r.level=depth then vempty:='0'; vfull:='1';
else vempty:='0'; vfull:='0'; end if;
--reset logic
if (reset='1') then v:=RESET_VECTOR; end if;
ri<=v;
s_ram_adr<=v.adr;
--assigning outport
write_error<=v.ewr; read_error<=v.erd; level<=v.level;
empty<=vempty; full<=vfull;
end process;
ram : syncram
generic map(tech=>tech, abits=>abits, dbits=>dbits)
port map (
clk => clk,
address => s_ram_adr,
datain => data_in,
dataout => data_out,
enable => read_enable,
write => write_enable
);
sync:process(clk) --Activate on clock & reset
begin
if clk'event and clk='1' then r<=ri; end if;
end process;
end; | mit | 52ecbac4a651ee59a7d16b1d3a17b106 | 0.572167 | 3.330055 | false | false | false | false |
impedimentToProgress/UCI-BlueChip | VhdlParser/test/valueTest.vhd | 1 | 2,327 | library IEEE;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity valueTest is
generic (
-- Negative integers are just a negate operation on a positive integer
-- Can use scientific notation, with plus symbol
-- Can seperate digits with an underscore
-- Decimal number representation is defualt for VHDL
interfaceConstant1 : integer := 12_0E0_2;
interfaceConstant2 : integer := 12E3; -- Doesn't support E+ or E-
-- Integer literals can also be in the for base#digit and _ string#
-- Base must be in range 2 to 16
interfaceConstant3 : integer := 2#10_1110_11_100_0_00#;
interfaceConstant4 : integer := 7#46662#;
interfaceConstant5 : integer := 8#27340#;
interfaceConstant6 : integer := 16#2EE0#;
-- Basic enumeration assignment
--interfaceConstant7 : character := 'x'; -- Only supports integers, booleans, bits, and bit vectors
interfaceConstant8 : std_logic range '0' to '1' := '0';
-- Array assignment, digits can be separated by _
-- Digits must be members of base type
-- Can specify base of string, for specification in octal and hex
-- Octal and hex strings require the maximum number of bits based on the number of digits
-- Use double quotes inside a string to add a quote character
--interfaceConstant9 : string := "This is ""a"" string";
interfaceConstant10 : std_logic_vector(13 downto 0) := B"10_1110_1110_0000";
interfaceConstant11 : std_logic_vector(14 downto 0) := O"27340";
interfaceConstant12 : std_logic_vector(15 downto 0) := X"2EE0";
interfaceConstant13 : std_logic_vector(0 downto 0) := "0";
-- Boolean literals
interfaceConstant14 : boolean := true;
interfaceConstant15 : boolean := false
-- Handle other types of enums i.e. setting the start state of a state machine
);
port (
clk : in std_logic;
rst : in std_logic;
dataIn : in std_logic_vector(7 downto 0);
dataOut : out std_logic_vector(7 downto 0)
);
end entity valueTest;
architecture rtl of valueTest is
begin
process(clk)begin
if(clk'event and clk = '1')then
if(rst = '1')then
dataOut <= X"00";
else
dataOut <= dataIn;
end if;
end if;
end process;
end architecture rtl;
| mit | 469d76ff6ab2f23d681f08e6713a4b1c | 0.654061 | 3.87188 | false | true | false | false |
lxp32/lxp32-cpu | rtl/lxp32_cpu.vhd | 1 | 6,520 | ---------------------------------------------------------------------
-- LXP32 CPU Core
--
-- Part of the LXP32 CPU
--
-- Copyright (c) 2016 by Alex I. Kuznetsov
---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity lxp32_cpu is
generic(
DBUS_RMW: boolean;
DIVIDER_EN: boolean;
MUL_ARCH: string;
START_ADDR: std_logic_vector(31 downto 0)
);
port(
clk_i: in std_logic;
rst_i: in std_logic;
lli_re_o: out std_logic;
lli_adr_o: out std_logic_vector(29 downto 0);
lli_dat_i: in std_logic_vector(31 downto 0);
lli_busy_i: in std_logic;
dbus_cyc_o: out std_logic;
dbus_stb_o: out std_logic;
dbus_we_o: out std_logic;
dbus_sel_o: out std_logic_vector(3 downto 0);
dbus_ack_i: in std_logic;
dbus_adr_o: out std_logic_vector(31 downto 2);
dbus_dat_o: out std_logic_vector(31 downto 0);
dbus_dat_i: in std_logic_vector(31 downto 0);
irq_i: in std_logic_vector(7 downto 0)
);
end entity;
architecture rtl of lxp32_cpu is
signal fetch_word: std_logic_vector(31 downto 0);
signal fetch_next_ip: std_logic_vector(29 downto 0);
signal fetch_current_ip: std_logic_vector(29 downto 0);
signal fetch_valid: std_logic;
signal fetch_jump_ready: std_logic;
signal decode_ready: std_logic;
signal decode_valid: std_logic;
signal decode_cmd_loadop3: std_logic;
signal decode_cmd_signed: std_logic;
signal decode_cmd_dbus: std_logic;
signal decode_cmd_dbus_store: std_logic;
signal decode_cmd_dbus_byte: std_logic;
signal decode_cmd_addsub: std_logic;
signal decode_cmd_mul: std_logic;
signal decode_cmd_div: std_logic;
signal decode_cmd_div_mod: std_logic;
signal decode_cmd_cmp: std_logic;
signal decode_cmd_jump: std_logic;
signal decode_cmd_negate_op2: std_logic;
signal decode_cmd_and: std_logic;
signal decode_cmd_xor: std_logic;
signal decode_cmd_shift: std_logic;
signal decode_cmd_shift_right: std_logic;
signal decode_jump_type: std_logic_vector(3 downto 0);
signal decode_op1: std_logic_vector(31 downto 0);
signal decode_op2: std_logic_vector(31 downto 0);
signal decode_op3: std_logic_vector(31 downto 0);
signal decode_dst: std_logic_vector(7 downto 0);
signal execute_ready: std_logic;
signal execute_jump_valid: std_logic;
signal execute_jump_dst: std_logic_vector(29 downto 0);
signal sp_raddr1: std_logic_vector(7 downto 0);
signal sp_rdata1: std_logic_vector(31 downto 0);
signal sp_raddr2: std_logic_vector(7 downto 0);
signal sp_rdata2: std_logic_vector(31 downto 0);
signal sp_waddr: std_logic_vector(7 downto 0);
signal sp_we: std_logic;
signal sp_wdata: std_logic_vector(31 downto 0);
signal interrupt_valid: std_logic;
signal interrupt_vector: std_logic_vector(2 downto 0);
signal interrupt_ready: std_logic;
signal interrupt_return: std_logic;
signal interrupt_wakeup: std_logic;
begin
fetch_inst: entity work.lxp32_fetch(rtl)
generic map(
START_ADDR=>START_ADDR
)
port map(
clk_i=>clk_i,
rst_i=>rst_i,
lli_re_o=>lli_re_o,
lli_adr_o=>lli_adr_o,
lli_dat_i=>lli_dat_i,
lli_busy_i=>lli_busy_i,
word_o=>fetch_word,
next_ip_o=>fetch_next_ip,
current_ip_o=>fetch_current_ip,
valid_o=>fetch_valid,
ready_i=>decode_ready,
jump_valid_i=>execute_jump_valid,
jump_dst_i=>execute_jump_dst,
jump_ready_o=>fetch_jump_ready
);
decode_inst: entity work.lxp32_decode(rtl)
port map(
clk_i=>clk_i,
rst_i=>rst_i,
word_i=>fetch_word,
next_ip_i=>fetch_next_ip,
current_ip_i=>fetch_current_ip,
valid_i=>fetch_valid,
jump_valid_i=>execute_jump_valid,
ready_o=>decode_ready,
interrupt_valid_i=>interrupt_valid,
interrupt_vector_i=>interrupt_vector,
interrupt_ready_o=>interrupt_ready,
wakeup_i=>interrupt_wakeup,
sp_raddr1_o=>sp_raddr1,
sp_rdata1_i=>sp_rdata1,
sp_raddr2_o=>sp_raddr2,
sp_rdata2_i=>sp_rdata2,
ready_i=>execute_ready,
valid_o=>decode_valid,
cmd_loadop3_o=>decode_cmd_loadop3,
cmd_signed_o=>decode_cmd_signed,
cmd_dbus_o=>decode_cmd_dbus,
cmd_dbus_store_o=>decode_cmd_dbus_store,
cmd_dbus_byte_o=>decode_cmd_dbus_byte,
cmd_addsub_o=>decode_cmd_addsub,
cmd_mul_o=>decode_cmd_mul,
cmd_div_o=>decode_cmd_div,
cmd_div_mod_o=>decode_cmd_div_mod,
cmd_cmp_o=>decode_cmd_cmp,
cmd_jump_o=>decode_cmd_jump,
cmd_negate_op2_o=>decode_cmd_negate_op2,
cmd_and_o=>decode_cmd_and,
cmd_xor_o=>decode_cmd_xor,
cmd_shift_o=>decode_cmd_shift,
cmd_shift_right_o=>decode_cmd_shift_right,
jump_type_o=>decode_jump_type,
op1_o=>decode_op1,
op2_o=>decode_op2,
op3_o=>decode_op3,
dst_o=>decode_dst
);
execute_inst: entity work.lxp32_execute(rtl)
generic map(
DBUS_RMW=>DBUS_RMW,
DIVIDER_EN=>DIVIDER_EN,
MUL_ARCH=>MUL_ARCH
)
port map(
clk_i=>clk_i,
rst_i=>rst_i,
cmd_loadop3_i=>decode_cmd_loadop3,
cmd_signed_i=>decode_cmd_signed,
cmd_dbus_i=>decode_cmd_dbus,
cmd_dbus_store_i=>decode_cmd_dbus_store,
cmd_dbus_byte_i=>decode_cmd_dbus_byte,
cmd_addsub_i=>decode_cmd_addsub,
cmd_mul_i=>decode_cmd_mul,
cmd_div_i=>decode_cmd_div,
cmd_div_mod_i=>decode_cmd_div_mod,
cmd_cmp_i=>decode_cmd_cmp,
cmd_jump_i=>decode_cmd_jump,
cmd_negate_op2_i=>decode_cmd_negate_op2,
cmd_and_i=>decode_cmd_and,
cmd_xor_i=>decode_cmd_xor,
cmd_shift_i=>decode_cmd_shift,
cmd_shift_right_i=>decode_cmd_shift_right,
jump_type_i=>decode_jump_type,
op1_i=>decode_op1,
op2_i=>decode_op2,
op3_i=>decode_op3,
dst_i=>decode_dst,
sp_waddr_o=>sp_waddr,
sp_we_o=>sp_we,
sp_wdata_o=>sp_wdata,
valid_i=>decode_valid,
ready_o=>execute_ready,
dbus_cyc_o=>dbus_cyc_o,
dbus_stb_o=>dbus_stb_o,
dbus_we_o=>dbus_we_o,
dbus_sel_o=>dbus_sel_o,
dbus_ack_i=>dbus_ack_i,
dbus_adr_o=>dbus_adr_o,
dbus_dat_o=>dbus_dat_o,
dbus_dat_i=>dbus_dat_i,
jump_valid_o=>execute_jump_valid,
jump_dst_o=>execute_jump_dst,
jump_ready_i=>fetch_jump_ready,
interrupt_return_o=>interrupt_return
);
scratchpad_inst: entity work.lxp32_scratchpad(rtl)
port map(
clk_i=>clk_i,
raddr1_i=>sp_raddr1,
rdata1_o=>sp_rdata1,
raddr2_i=>sp_raddr2,
rdata2_o=>sp_rdata2,
waddr_i=>sp_waddr,
we_i=>sp_we,
wdata_i=>sp_wdata
);
interrupt_mux_inst: entity work.lxp32_interrupt_mux(rtl)
port map(
clk_i=>clk_i,
rst_i=>rst_i,
irq_i=>irq_i,
interrupt_valid_o=>interrupt_valid,
interrupt_vector_o=>interrupt_vector,
interrupt_ready_i=>interrupt_ready,
interrupt_return_i=>interrupt_return,
wakeup_o=>interrupt_wakeup,
sp_waddr_i=>sp_waddr,
sp_we_i=>sp_we,
sp_wdata_i=>sp_wdata
);
end architecture;
| mit | 847e88f668ba81dd12376fd35e45de97 | 0.676687 | 2.5 | false | false | false | false |
cafe-alpha/wascafe | v13/r07c_de10_20201014_abus4/wasca/synthesis/wasca_rst_controller_002.vhd | 6 | 9,079 | -- wasca_rst_controller_002.vhd
-- Generated using ACDS version 15.0 145
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity wasca_rst_controller_002 is
generic (
NUM_RESET_INPUTS : integer := 1;
OUTPUT_RESET_SYNC_EDGES : string := "deassert";
SYNC_DEPTH : integer := 2;
RESET_REQUEST_PRESENT : integer := 1;
RESET_REQ_WAIT_TIME : integer := 1;
MIN_RST_ASSERTION_TIME : integer := 3;
RESET_REQ_EARLY_DSRT_TIME : integer := 1;
USE_RESET_REQUEST_IN0 : integer := 0;
USE_RESET_REQUEST_IN1 : integer := 0;
USE_RESET_REQUEST_IN2 : integer := 0;
USE_RESET_REQUEST_IN3 : integer := 0;
USE_RESET_REQUEST_IN4 : integer := 0;
USE_RESET_REQUEST_IN5 : integer := 0;
USE_RESET_REQUEST_IN6 : integer := 0;
USE_RESET_REQUEST_IN7 : integer := 0;
USE_RESET_REQUEST_IN8 : integer := 0;
USE_RESET_REQUEST_IN9 : integer := 0;
USE_RESET_REQUEST_IN10 : integer := 0;
USE_RESET_REQUEST_IN11 : integer := 0;
USE_RESET_REQUEST_IN12 : integer := 0;
USE_RESET_REQUEST_IN13 : integer := 0;
USE_RESET_REQUEST_IN14 : integer := 0;
USE_RESET_REQUEST_IN15 : integer := 0;
ADAPT_RESET_REQUEST : integer := 0
);
port (
reset_in0 : in std_logic := '0'; -- reset_in0.reset
clk : in std_logic := '0'; -- clk.clk
reset_out : out std_logic; -- reset_out.reset
reset_req : out std_logic; -- .reset_req
reset_in1 : in std_logic := '0';
reset_in10 : in std_logic := '0';
reset_in11 : in std_logic := '0';
reset_in12 : in std_logic := '0';
reset_in13 : in std_logic := '0';
reset_in14 : in std_logic := '0';
reset_in15 : in std_logic := '0';
reset_in2 : in std_logic := '0';
reset_in3 : in std_logic := '0';
reset_in4 : in std_logic := '0';
reset_in5 : in std_logic := '0';
reset_in6 : in std_logic := '0';
reset_in7 : in std_logic := '0';
reset_in8 : in std_logic := '0';
reset_in9 : in std_logic := '0';
reset_req_in0 : in std_logic := '0';
reset_req_in1 : in std_logic := '0';
reset_req_in10 : in std_logic := '0';
reset_req_in11 : in std_logic := '0';
reset_req_in12 : in std_logic := '0';
reset_req_in13 : in std_logic := '0';
reset_req_in14 : in std_logic := '0';
reset_req_in15 : in std_logic := '0';
reset_req_in2 : in std_logic := '0';
reset_req_in3 : in std_logic := '0';
reset_req_in4 : in std_logic := '0';
reset_req_in5 : in std_logic := '0';
reset_req_in6 : in std_logic := '0';
reset_req_in7 : in std_logic := '0';
reset_req_in8 : in std_logic := '0';
reset_req_in9 : in std_logic := '0'
);
end entity wasca_rst_controller_002;
architecture rtl of wasca_rst_controller_002 is
component altera_reset_controller is
generic (
NUM_RESET_INPUTS : integer := 6;
OUTPUT_RESET_SYNC_EDGES : string := "deassert";
SYNC_DEPTH : integer := 2;
RESET_REQUEST_PRESENT : integer := 0;
RESET_REQ_WAIT_TIME : integer := 1;
MIN_RST_ASSERTION_TIME : integer := 3;
RESET_REQ_EARLY_DSRT_TIME : integer := 1;
USE_RESET_REQUEST_IN0 : integer := 0;
USE_RESET_REQUEST_IN1 : integer := 0;
USE_RESET_REQUEST_IN2 : integer := 0;
USE_RESET_REQUEST_IN3 : integer := 0;
USE_RESET_REQUEST_IN4 : integer := 0;
USE_RESET_REQUEST_IN5 : integer := 0;
USE_RESET_REQUEST_IN6 : integer := 0;
USE_RESET_REQUEST_IN7 : integer := 0;
USE_RESET_REQUEST_IN8 : integer := 0;
USE_RESET_REQUEST_IN9 : integer := 0;
USE_RESET_REQUEST_IN10 : integer := 0;
USE_RESET_REQUEST_IN11 : integer := 0;
USE_RESET_REQUEST_IN12 : integer := 0;
USE_RESET_REQUEST_IN13 : integer := 0;
USE_RESET_REQUEST_IN14 : integer := 0;
USE_RESET_REQUEST_IN15 : integer := 0;
ADAPT_RESET_REQUEST : integer := 0
);
port (
reset_in0 : in std_logic := 'X'; -- reset
clk : in std_logic := 'X'; -- clk
reset_out : out std_logic; -- reset
reset_req : out std_logic; -- reset_req
reset_req_in0 : in std_logic := 'X'; -- reset_req
reset_in1 : in std_logic := 'X'; -- reset
reset_req_in1 : in std_logic := 'X'; -- reset_req
reset_in2 : in std_logic := 'X'; -- reset
reset_req_in2 : in std_logic := 'X'; -- reset_req
reset_in3 : in std_logic := 'X'; -- reset
reset_req_in3 : in std_logic := 'X'; -- reset_req
reset_in4 : in std_logic := 'X'; -- reset
reset_req_in4 : in std_logic := 'X'; -- reset_req
reset_in5 : in std_logic := 'X'; -- reset
reset_req_in5 : in std_logic := 'X'; -- reset_req
reset_in6 : in std_logic := 'X'; -- reset
reset_req_in6 : in std_logic := 'X'; -- reset_req
reset_in7 : in std_logic := 'X'; -- reset
reset_req_in7 : in std_logic := 'X'; -- reset_req
reset_in8 : in std_logic := 'X'; -- reset
reset_req_in8 : in std_logic := 'X'; -- reset_req
reset_in9 : in std_logic := 'X'; -- reset
reset_req_in9 : in std_logic := 'X'; -- reset_req
reset_in10 : in std_logic := 'X'; -- reset
reset_req_in10 : in std_logic := 'X'; -- reset_req
reset_in11 : in std_logic := 'X'; -- reset
reset_req_in11 : in std_logic := 'X'; -- reset_req
reset_in12 : in std_logic := 'X'; -- reset
reset_req_in12 : in std_logic := 'X'; -- reset_req
reset_in13 : in std_logic := 'X'; -- reset
reset_req_in13 : in std_logic := 'X'; -- reset_req
reset_in14 : in std_logic := 'X'; -- reset
reset_req_in14 : in std_logic := 'X'; -- reset_req
reset_in15 : in std_logic := 'X'; -- reset
reset_req_in15 : in std_logic := 'X' -- reset_req
);
end component altera_reset_controller;
begin
rst_controller_002 : component altera_reset_controller
generic map (
NUM_RESET_INPUTS => NUM_RESET_INPUTS,
OUTPUT_RESET_SYNC_EDGES => OUTPUT_RESET_SYNC_EDGES,
SYNC_DEPTH => SYNC_DEPTH,
RESET_REQUEST_PRESENT => RESET_REQUEST_PRESENT,
RESET_REQ_WAIT_TIME => RESET_REQ_WAIT_TIME,
MIN_RST_ASSERTION_TIME => MIN_RST_ASSERTION_TIME,
RESET_REQ_EARLY_DSRT_TIME => RESET_REQ_EARLY_DSRT_TIME,
USE_RESET_REQUEST_IN0 => USE_RESET_REQUEST_IN0,
USE_RESET_REQUEST_IN1 => USE_RESET_REQUEST_IN1,
USE_RESET_REQUEST_IN2 => USE_RESET_REQUEST_IN2,
USE_RESET_REQUEST_IN3 => USE_RESET_REQUEST_IN3,
USE_RESET_REQUEST_IN4 => USE_RESET_REQUEST_IN4,
USE_RESET_REQUEST_IN5 => USE_RESET_REQUEST_IN5,
USE_RESET_REQUEST_IN6 => USE_RESET_REQUEST_IN6,
USE_RESET_REQUEST_IN7 => USE_RESET_REQUEST_IN7,
USE_RESET_REQUEST_IN8 => USE_RESET_REQUEST_IN8,
USE_RESET_REQUEST_IN9 => USE_RESET_REQUEST_IN9,
USE_RESET_REQUEST_IN10 => USE_RESET_REQUEST_IN10,
USE_RESET_REQUEST_IN11 => USE_RESET_REQUEST_IN11,
USE_RESET_REQUEST_IN12 => USE_RESET_REQUEST_IN12,
USE_RESET_REQUEST_IN13 => USE_RESET_REQUEST_IN13,
USE_RESET_REQUEST_IN14 => USE_RESET_REQUEST_IN14,
USE_RESET_REQUEST_IN15 => USE_RESET_REQUEST_IN15,
ADAPT_RESET_REQUEST => ADAPT_RESET_REQUEST
)
port map (
reset_in0 => reset_in0, -- reset_in0.reset
clk => clk, -- clk.clk
reset_out => reset_out, -- reset_out.reset
reset_req => reset_req, -- .reset_req
reset_req_in0 => '0', -- (terminated)
reset_in1 => '0', -- (terminated)
reset_req_in1 => '0', -- (terminated)
reset_in2 => '0', -- (terminated)
reset_req_in2 => '0', -- (terminated)
reset_in3 => '0', -- (terminated)
reset_req_in3 => '0', -- (terminated)
reset_in4 => '0', -- (terminated)
reset_req_in4 => '0', -- (terminated)
reset_in5 => '0', -- (terminated)
reset_req_in5 => '0', -- (terminated)
reset_in6 => '0', -- (terminated)
reset_req_in6 => '0', -- (terminated)
reset_in7 => '0', -- (terminated)
reset_req_in7 => '0', -- (terminated)
reset_in8 => '0', -- (terminated)
reset_req_in8 => '0', -- (terminated)
reset_in9 => '0', -- (terminated)
reset_req_in9 => '0', -- (terminated)
reset_in10 => '0', -- (terminated)
reset_req_in10 => '0', -- (terminated)
reset_in11 => '0', -- (terminated)
reset_req_in11 => '0', -- (terminated)
reset_in12 => '0', -- (terminated)
reset_req_in12 => '0', -- (terminated)
reset_in13 => '0', -- (terminated)
reset_req_in13 => '0', -- (terminated)
reset_in14 => '0', -- (terminated)
reset_req_in14 => '0', -- (terminated)
reset_in15 => '0', -- (terminated)
reset_req_in15 => '0' -- (terminated)
);
end architecture rtl; -- of wasca_rst_controller_002
| gpl-2.0 | e2d4071332ebf507869fdee6052561fb | 0.546536 | 2.728885 | false | false | false | false |
impedimentToProgress/UCI-BlueChip | AttackFiles/Defense/config.vhd | 1 | 6,913 | -----------------------------------------------------------------------------
-- LEON3 Demonstration design test bench configuration
-- Copyright (C) 2004 Jiri Gaisler, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
------------------------------------------------------------------------------
library techmap;
use techmap.gencomp.all;
package config is
-- Technology and synthesis options
constant CFG_FABTECH : integer := virtex5;
constant CFG_MEMTECH : integer := virtex5;
constant CFG_PADTECH : integer := virtex5;
constant CFG_NOASYNC : integer := 0;
constant CFG_SCAN : integer := 0;
-- Clock generator
constant CFG_CLKTECH : integer := virtex5;
constant CFG_CLKMUL : integer := (8);
constant CFG_CLKDIV : integer := (10);
constant CFG_OCLKDIV : integer := 2;
constant CFG_PCIDLL : integer := 0;
constant CFG_PCISYSCLK: integer := 0;
constant CFG_CLK_NOFB : integer := 0;
-- LEON3 processor core
constant CFG_LEON3 : integer := 1;
constant CFG_NCPU : integer := (1);
constant CFG_NWIN : integer := (8);
constant CFG_V8 : integer := 2;
constant CFG_MAC : integer := 0;
constant CFG_SVT : integer := 0;
constant CFG_RSTADDR : integer := 16#00000#;
constant CFG_LDDEL : integer := (1);
constant CFG_NWP : integer := (2);
constant CFG_PWD : integer := 0*2;
constant CFG_FPU : integer := 1 + 16*0;
constant CFG_GRFPUSH : integer := 0;
constant CFG_ICEN : integer := 1;
constant CFG_ISETS : integer := 2;
constant CFG_ISETSZ : integer := 8;
constant CFG_ILINE : integer := 8;
constant CFG_IREPL : integer := 0;
constant CFG_ILOCK : integer := 0;
constant CFG_ILRAMEN : integer := 0;
constant CFG_ILRAMADDR: integer := 16#8E#;
constant CFG_ILRAMSZ : integer := 1;
constant CFG_DCEN : integer := 1;
constant CFG_DSETS : integer := 2;
constant CFG_DSETSZ : integer := 8;
constant CFG_DLINE : integer := 8;
constant CFG_DREPL : integer := 0;
constant CFG_DLOCK : integer := 0;
constant CFG_DSNOOP : integer := 0 + 0 + 4*0;
constant CFG_DFIXED : integer := 16#0#;
constant CFG_DLRAMEN : integer := 0;
constant CFG_DLRAMADDR: integer := 16#8F#;
constant CFG_DLRAMSZ : integer := 1;
constant CFG_MMUEN : integer := 1;
constant CFG_ITLBNUM : integer := 8;
constant CFG_DTLBNUM : integer := 2;
constant CFG_TLB_TYPE : integer := 1 + 0*2;
constant CFG_TLB_REP : integer := 1;
constant CFG_DSU : integer := 1;
constant CFG_ITBSZ : integer := 2;
constant CFG_ATBSZ : integer := 2;
constant CFG_LEON3FT_EN : integer := 0;
constant CFG_IUFT_EN : integer := 0;
constant CFG_FPUFT_EN : integer := 0;
constant CFG_RF_ERRINJ : integer := 0;
constant CFG_CACHE_FT_EN : integer := 0;
constant CFG_CACHE_ERRINJ : integer := 0;
constant CFG_LEON3_NETLIST: integer := 0;
constant CFG_DISAS : integer := 0 + 0;
constant CFG_PCLOW : integer := 2;
-- AMBA settings
constant CFG_DEFMST : integer := (0);
constant CFG_RROBIN : integer := 1;
constant CFG_SPLIT : integer := 0;
constant CFG_AHBIO : integer := 16#FFF#;
constant CFG_APBADDR : integer := 16#800#;
constant CFG_AHB_MON : integer := 0;
constant CFG_AHB_MONERR : integer := 0;
constant CFG_AHB_MONWAR : integer := 0;
-- DSU UART
constant CFG_AHB_UART : integer := 0;
-- JTAG based DSU interface
constant CFG_AHB_JTAG : integer := 1;
-- Ethernet DSU
constant CFG_DSU_ETH : integer := 0 + 0;
constant CFG_ETH_BUF : integer := 2;
constant CFG_ETH_IPM : integer := 16#C0A8#;
constant CFG_ETH_IPL : integer := 16#0034#;
constant CFG_ETH_ENM : integer := 16#020000#;
constant CFG_ETH_ENL : integer := 16#000034#;
-- LEON2 memory controller
constant CFG_MCTRL_LEON2 : integer := 0;
constant CFG_MCTRL_RAM8BIT : integer := 0;
constant CFG_MCTRL_RAM16BIT : integer := 0;
constant CFG_MCTRL_5CS : integer := 0;
constant CFG_MCTRL_SDEN : integer := 0;
constant CFG_MCTRL_SEPBUS : integer := 0;
constant CFG_MCTRL_INVCLK : integer := 0;
constant CFG_MCTRL_SD64 : integer := 0;
constant CFG_MCTRL_PAGE : integer := 0 + 0;
-- DDR controller
constant CFG_DDR2SP : integer := 1;
constant CFG_DDR2SP_INIT : integer := 1;
constant CFG_DDR2SP_FREQ : integer := (190);
constant CFG_DDR2SP_TRFC : integer := (130);
constant CFG_DDR2SP_DATAWIDTH : integer := (64);
constant CFG_DDR2SP_COL : integer := (10);
constant CFG_DDR2SP_SIZE : integer := (256);
constant CFG_DDR2SP_DELAY0 : integer := (0);
constant CFG_DDR2SP_DELAY1 : integer := (0);
constant CFG_DDR2SP_DELAY2 : integer := (0);
constant CFG_DDR2SP_DELAY3 : integer := (0);
constant CFG_DDR2SP_DELAY4 : integer := (0);
constant CFG_DDR2SP_DELAY5 : integer := (0);
constant CFG_DDR2SP_DELAY6 : integer := (0);
constant CFG_DDR2SP_DELAY7 : integer := (0);
-- AHB status register
constant CFG_AHBSTAT : integer := 1;
constant CFG_AHBSTATN : integer := (1);
-- AHB ROM
constant CFG_AHBROMEN : integer := 0;
constant CFG_AHBROPIP : integer := 0;
constant CFG_AHBRODDR : integer := 16#000#;
constant CFG_ROMADDR : integer := 16#000#;
constant CFG_ROMMASK : integer := 16#E00# + 16#000#;
-- AHB RAM
constant CFG_AHBRAMEN : integer := 0;
constant CFG_AHBRSZ : integer := 1;
constant CFG_AHBRADDR : integer := 16#A00#;
-- Gaisler Ethernet core
constant CFG_GRETH : integer := 1;
constant CFG_GRETH1G : integer := 0;
constant CFG_ETH_FIFO : integer := 32;
-- UART 1
constant CFG_UART1_ENABLE : integer := 1;
constant CFG_UART1_FIFO : integer := 4;
-- LEON3 interrupt controller
constant CFG_IRQ3_ENABLE : integer := 1;
constant CFG_IRQ3_NSEC : integer := 0;
-- Modular timer
constant CFG_GPT_ENABLE : integer := 1;
constant CFG_GPT_NTIM : integer := (2);
constant CFG_GPT_SW : integer := (8);
constant CFG_GPT_TW : integer := (32);
constant CFG_GPT_IRQ : integer := (8);
constant CFG_GPT_SEPIRQ : integer := 1;
constant CFG_GPT_WDOGEN : integer := 0;
constant CFG_GPT_WDOG : integer := 16#0#;
-- GPIO port
constant CFG_GRGPIO_ENABLE : integer := 1;
constant CFG_GRGPIO_IMASK : integer := 16#0FFFE#;
constant CFG_GRGPIO_WIDTH : integer := (32);
-- I2C master
constant CFG_I2C_ENABLE : integer := 0;
-- VGA and PS2/ interface
constant CFG_KBD_ENABLE : integer := 0;
constant CFG_VGA_ENABLE : integer := 0;
constant CFG_SVGA_ENABLE : integer := 0;
-- AMBA System ACE Interface Controller
constant CFG_GRACECTRL : integer := 1;
-- GRLIB debugging
constant CFG_DUART : integer := 0;
end;
| mit | 20d1a22bfdb83abff162cdfbf2cadcf4 | 0.654419 | 3.602397 | false | false | false | false |
impedimentToProgress/UCI-BlueChip | AttackFiles/Attacks/privEsc/lib/grlib/amba/apbctrl.vhd | 2 | 9,001 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: apbctrl
-- File: apbctrl.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: AMBA AHB/APB bridge with plug&play support
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
-- pragma translate_off
use grlib.devices.all;
use std.textio.all;
-- pragma translate_on
entity apbctrl is
generic (
hindex : integer := 0;
haddr : integer := 0;
hmask : integer := 16#fff#;
nslaves : integer range 1 to NAPBSLV := NAPBSLV;
debug : integer range 0 to 2 := 2;
icheck : integer range 0 to 1 := 1;
enbusmon : integer range 0 to 1 := 0;
asserterr : integer range 0 to 1 := 0;
assertwarn : integer range 0 to 1 := 0;
pslvdisable : integer := 0);
port (
rst : in std_ulogic;
clk : in std_ulogic;
ahbi : in ahb_slv_in_type;
ahbo : out ahb_slv_out_type;
apbi : out apb_slv_in_type;
apbo : in apb_slv_out_vector
);
end;
architecture rtl of apbctrl is
constant apbmax : integer := 19;
constant VERSION : amba_version_type := 0;
constant hconfig : ahb_config_type := (
0 => ahb_device_reg ( 1, 6, 0, VERSION, 0),
4 => ahb_membar(haddr, '0', '0', hmask),
others => zero32);
constant IOAREA : std_logic_vector(11 downto 0) :=
conv_std_logic_vector(haddr, 12);
constant IOMSK : std_logic_vector(11 downto 0) :=
conv_std_logic_vector(hmask, 12);
type reg_type is record
haddr : std_logic_vector(apbmax downto 0); -- address bus
hwrite : std_logic; -- read/write
hready : std_logic; -- ready
penable : std_logic;
psel : std_logic;
prdata : std_logic_vector(31 downto 0); -- read data
pwdata : std_logic_vector(31 downto 0); -- write data
state : std_logic_vector(1 downto 0); -- state
cfgsel : std_ulogic;
end record;
signal r, rin : reg_type;
--pragma translate_off
signal lapbi : apb_slv_in_type;
--pragma translate_on
begin
comb : process(ahbi, apbo, r, rst)
variable v : reg_type;
variable psel : std_logic_vector(0 to 31);
variable pwdata : std_logic_vector(31 downto 0);
variable apbaddr : std_logic_vector(apbmax downto 0);
variable apbaddr2 : std_logic_vector(31 downto 0);
variable hirq, pirq : std_logic_vector(NAHBIRQ-1 downto 0);
variable nslave : integer range 0 to nslaves-1;
variable bnslave : std_logic_vector(3 downto 0);
begin
v := r; v.psel := '0'; v.penable := '0'; psel := (others => '0');
hirq := (others => '0'); pirq := (others => '0');
-- detect start of cycle
if (ahbi.hready = '1') then
if ((ahbi.htrans = HTRANS_NONSEQ) or (ahbi.htrans = HTRANS_SEQ)) and
(ahbi.hsel(hindex) = '1')
then
v.hready := '0'; v.hwrite := ahbi.hwrite;
v.haddr(apbmax downto 0) := ahbi.haddr(apbmax downto 0);
v.state := "01"; v.psel := not ahbi.hwrite;
end if;
end if;
case r.state is
when "00" => null; -- idle
when "01" =>
if r.hwrite = '0' then v.penable := '1';
else v.pwdata := ahbi.hwdata; end if;
v.psel := '1'; v.state := "10";
when others =>
if r.penable = '0' then v.psel := '1'; v.penable := '1'; end if;
v.state := "00"; v.hready := '1';
end case;
psel := (others => '0');
for i in 0 to nslaves-1 loop
if ((apbo(i).pconfig(1)(1 downto 0) = "01") and
((apbo(i).pconfig(1)(31 downto 20) and apbo(i).pconfig(1)(15 downto 4)) =
(r.haddr(19 downto 8) and apbo(i).pconfig(1)(15 downto 4))))
then psel(i) := '1'; end if;
end loop;
bnslave(0) := psel(1) or psel(3) or psel(5) or psel(7) or
psel(9) or psel(11) or psel(13) or psel(15);
bnslave(1) := psel(2) or psel(3) or psel(6) or psel(7) or
psel(10) or psel(11) or psel(14) or psel(15);
bnslave(2) := psel(4) or psel(5) or psel(6) or psel(7) or
psel(12) or psel(13) or psel(14) or psel(15);
bnslave(3) := psel(8) or psel(9) or psel(10) or psel(11) or
psel(12) or psel(13) or psel(14) or psel(15);
nslave := conv_integer(bnslave);
if (r.haddr(19 downto 12) = "11111111") then
v.cfgsel := '1'; psel := (others => '0'); v.penable := '0';
else v.cfgsel := '0'; end if;
v.prdata := apbo(nslave).prdata;
if r.cfgsel = '1' then
v.prdata := apbo(conv_integer(r.haddr(log2x(nslaves)+2 downto 3))).pconfig(conv_integer(r.haddr(2 downto 2)));
end if;
for i in 0 to nslaves-1 loop pirq := pirq or apbo(i).pirq; end loop;
-- AHB respons
ahbo.hready <= r.hready;
ahbo.hrdata <= r.prdata;
ahbo.hirq <= pirq;
if rst = '0' then
v.penable := '0'; v.hready := '1'; v.psel := '0'; v.state := "00";
v.hwrite := '0';
-- pragma translate_off
v.haddr := (others => '0');
-- pragma translate_on
end if;
rin <= v;
-- drive APB bus
apbaddr2 := (others => '0');
apbaddr2(apbmax downto 0) := r.haddr(apbmax downto 0);
apbi.paddr <= apbaddr2;
apbi.pwdata <= r.pwdata;
apbi.pwrite <= r.hwrite;
apbi.penable <= r.penable;
apbi.pirq <= ahbi.hirq;
apbi.testen <= ahbi.testen;
apbi.testoen <= ahbi.testoen;
apbi.scanen <= ahbi.scanen;
apbi.testrst <= ahbi.testrst;
for i in 0 to nslaves-1 loop apbi.psel(i) <= psel(i) and r.psel; end loop;
--pragma translate_off
lapbi.paddr <= apbaddr2;
lapbi.pwdata <= r.pwdata;
lapbi.pwrite <= r.hwrite;
lapbi.penable <= r.penable;
lapbi.pirq <= ahbi.hirq;
for i in 0 to nslaves-1 loop lapbi.psel(i) <= psel(i) and r.psel; end loop;
--pragma translate_on
end process;
ahbo.hindex <= hindex;
ahbo.hconfig <= hconfig;
ahbo.hcache <= '0';
ahbo.hsplit <= (others => '0');
ahbo.hresp <= HRESP_OKAY;
reg : process(clk)
begin if rising_edge(clk) then r <= rin; end if; end process;
-- pragma translate_off
mon0 : if enbusmon /= 0 generate
mon : apbmon
generic map(
asserterr => asserterr,
assertwarn => assertwarn,
pslvdisable => pslvdisable,
napb => nslaves)
port map(
rst => rst,
clk => clk,
apbi => lapbi,
apbo => apbo,
err => open);
end generate;
diag : process
variable k : integer;
variable mask : std_logic_vector(11 downto 0);
variable device : std_logic_vector(11 downto 0);
variable devicei : integer;
variable vendor : std_logic_vector( 7 downto 0);
variable vendori : integer;
variable iosize : integer;
variable iounit : string(1 to 5) := "byte ";
variable memstart : std_logic_vector(11 downto 0) := IOAREA and IOMSK;
variable L1 : line := new string'("");
begin
wait for 3 ns;
if debug = 0 then wait; end if;
print("apbctrl: APB Bridge at " & tost(memstart) & "00000 rev 1");
if debug = 1 then wait; end if;
for i in 0 to nslaves-1 loop
vendor := apbo(i).pconfig(0)(31 downto 24);
vendori := conv_integer(vendor);
if vendori /= 0 then
device := apbo(i).pconfig(0)(23 downto 12);
devicei := conv_integer(device);
std.textio.write(L1, "apbctrl: slv" & tost(i) & ": " &
iptable(vendori).vendordesc & iptable(vendori).device_table(devicei));
std.textio.writeline(OUTPUT, L1);
mask := apbo(i).pconfig(1)(15 downto 4);
k := 0;
while (k<15) and (mask(k) = '0') loop k := k+1; end loop;
iosize := 256 * 2**k; iounit := "byte ";
if (iosize > 1023) then iosize := iosize/1024; iounit := "kbyte"; end if;
print("apbctrl: I/O ports at " &
tost(memstart & (apbo(i).pconfig(1)(31 downto 20) and apbo(i).pconfig(1)(15 downto 4))) &
"00, size " & tost(iosize) & " " & iounit);
assert (apbo(i).pindex = i) or (icheck = 0)
report "APB slave index error on slave " & tost(i) severity failure;
end if;
end loop;
wait;
end process;
-- pragma translate_on
end;
| mit | a56a3089a559f5d285cd99b63897a5c6 | 0.582602 | 3.33865 | false | true | false | false |
impedimentToProgress/UCI-BlueChip | AttackFiles/Attacks/privEsc/lib/gaisler/sim/ata_device.vhd | 2 | 15,636 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: ata_device
-- File: ata_device.vhd
-- Author: Erik Jagres, Gaisler Research
-- Description: Simulation of ATA device
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.stdlib.all;
library gaisler;
use gaisler.sim.all;
--************************ENTITY************************************************
Entity ata_device is
generic(sector_length: integer :=512; --in bytes
disk_size: integer :=32; --in sectors
log2_size : integer :=14; --Log2(sector_length*disk_size), abits
Tlr : time := 35 ns
);
port(
--for convinience, not part of ATA interface
clk : in std_logic;
rst : in std_logic;
--interface to host bus adapter
d : inout std_logic_vector(15 downto 0) := (others=>'Z');
atai : in ata_in_type := ATAI_RESET_VECTOR;
atao : out ata_out_type:= ATAO_RESET_VECTOR);
end;
--************************ARCHITECTURE******************************************
Architecture behaveioral of ata_device is
type mem_reg_type is record
a : std_logic_vector(9 downto 0); --word adress
d : std_logic_vector(15 downto 0); --data
lb : std_logic; --low byte access (active low)
ub : std_logic; --upper byte access (active low)
ce : std_logic; --chip enable (active low)
we : std_logic; --write enable (active low)
oe : std_logic; --output enable (active low)
end record;
constant MEM_RESET_VECTOR : mem_reg_type := ((others=>'0'),
(others=>'0'),'1','1','1','1','1');
constant CS1 : integer := 4;
constant CS0 : integer := 3;
--status bits
constant BSY : integer := 7;
constant DRQ : integer := 3;
--control bits
constant NIEN : integer := 1;
--commands
constant READ : std_logic_vector(7 downto 0):=X"20";
constant WRITE : std_logic_vector(7 downto 0):=X"30";
constant WRITE_DMA : std_logic_vector(7 downto 0):=X"CA";
constant READ_DMA : std_logic_vector(7 downto 0):=X"C8";
constant ALTSTAT : std_logic_vector(4 downto 0):="10110";
constant CMD : std_logic_vector(4 downto 0):="01111";
constant CHR : std_logic_vector(4 downto 0):="01101";
constant CLR : std_logic_vector(4 downto 0):="01100";
constant DTAR : std_logic_vector(4 downto 0):="01000";
constant DTAP : std_logic_vector(4 downto 0):="00000"; --only CSx used
constant CTRL : std_logic_vector(4 downto 0):="10110";
constant DHR : std_logic_vector(4 downto 0):="01110";
constant ERR : std_logic_vector(4 downto 0):="01001"; --read only
constant FEAT : std_logic_vector(4 downto 0):=ERR; --write only
constant SCR : std_logic_vector(4 downto 0):="01010";
constant SNR : std_logic_vector(4 downto 0):="01011";
constant STAT : std_logic_vector(4 downto 0):="01111";
constant sramfile : string := "disk.srec"; -- ram contents
constant w_adr: integer := log2(sector_length)-1; --word adress bits (within sector)
type ram_type is record
a : std_logic_vector(log2_size-2 downto 0);
ce : std_logic;
we : std_ulogic;
oe : std_ulogic;
end record;
constant RAM_RESET_VECTOR : ram_type := ((others=>'0'),'0','0','0');
type ata_reg_type is record --ATA task file
altstat : std_logic_vector(7 downto 0); --Alternate Status register
cmd : std_logic_vector(7 downto 0); --Command register
chr : std_logic_vector(7 downto 0); --Cylinder High register
clr : std_logic_vector(7 downto 0); --Cylinder Low register
dtar : std_logic_vector(15 downto 0); --Data register
dtap : std_logic_vector(15 downto 0); --Data port
ctrl : std_logic_vector(7 downto 0); --Device Control register
dhr : std_logic_vector(7 downto 0); --Device/Head register
err : std_logic_vector(7 downto 0); --Error register
feat : std_logic_vector(7 downto 0); --Features register
scr : std_logic_vector(7 downto 0); --Sector Count register
snr : std_logic_vector(7 downto 0); --Sector Number register
stat : std_logic_vector(7 downto 0); --Status register
end record;
constant ATA_RESET_VECTOR : ata_reg_type := ((others=>'0'),
(others=>'0'),(others=>'0'),
(others=>'0'),(others=>'0'),
(others=>'0'),(others=>'0'),
(others=>'0'),(others=>'0'),
(others=>'0'),(others=>'0'),
(others=>'0'),(others=>'0'));
type reg_type is record
cmd_started : boolean;
dtap_written : boolean;
dtar_written : boolean;
dtap_read : boolean;
dtar_read : boolean;
firstadr : boolean;
dior : std_logic;
diow : std_logic;
regadr : std_logic_vector(4 downto 0);
byte_cnt : integer;
offset : integer;
intrq : boolean;
pio_started : boolean;
tf : ata_reg_type;
ram : ram_type;
ram_dta : std_logic_vector(15 downto 0);
scr : std_logic_vector(7 downto 0);
end record;
constant REG_RESET_VECTOR : reg_type := (false,false,false,false,false,true,
'1','1',(others=>'0'),0,0,false,false,ATA_RESET_VECTOR,RAM_RESET_VECTOR,
(others=>'0'),(others=>'0'));
signal r,ri : reg_type := REG_RESET_VECTOR;
signal s_d : std_logic_vector(15 downto 0) := (others=>'0');
begin
comb: process(atai,r,s_d,rst)
variable v : reg_type:= REG_RESET_VECTOR;
begin
if (rst='0') then
v:=REG_RESET_VECTOR;
d<=(others=>'Z');
atao.intrq<='0';
atao.dmarq<='0';
else
v:=r;
v.dior:=atai.dior; v.diow:=atai.diow;
v.regadr(CS1):=not(atai.cs(1)); v.regadr(CS0):=not(atai.cs(0)); --CS active l
v.regadr(2 downto 0):=atai.da(2 downto 0);
--fix for adressing dtap
if (v.regadr(4 downto 3)="00") then
v.regadr(2 downto 0):="000";
end if;
--*********************************READ/WRITE registers*****************
if (atai.dior='1' and atai.diow='1' and r.diow='0') then --write register
case v.regadr is
when CMD => v.tf.cmd:=d(7 downto 0);
v.cmd_started:=true;
v.tf.stat(BSY):='1';
v.tf.feat:="00001111";
v.byte_cnt:=0;
atao.dmarq<='0'; -----------------------------------erik 2006-10-17
when CHR => v.tf.chr:=d(7 downto 0);
when CLR => v.tf.clr:=d(7 downto 0);
when DTAR => v.tf.dtar:=d(15 downto 0);
v.dtar_written:=true;
when CTRL => v.tf.ctrl:=d(7 downto 0);
when DHR => v.tf.dhr:=d(7 downto 0);
when FEAT => v.tf.feat:=d(7 downto 0);
when SCR => v.tf.scr:=d(7 downto 0); v.scr:=d(7 downto 0);
when SNR => v.tf.snr:=d(7 downto 0);
when DTAP => v.tf.dtap:=d(15 downto 0);
v.dtap_written:=true;
when others => v.tf.stat:=d(7 downto 0);
end case;
elsif (atai.dior='0' and r.dior='1' and atai.diow='1') then --read register
case v.regadr is
when ALTSTAT => d(7 downto 0)<=r.tf.altstat; d(15 downto 8)<="00000000";
when CHR => d(7 downto 0)<=r.tf.chr; d(15 downto 8)<="00000000";
when CLR => d(7 downto 0)<=r.tf.clr; d(15 downto 8)<="00000000";
when DTAR => d<=r.tf.dtar; v.dtar_read:=true;
when DHR => d(7 downto 0)<=r.tf.dhr; d(15 downto 8)<="00000000";
when ERR => d(7 downto 0)<=r.tf.err; d(15 downto 8)<="00000000";
when SCR => d(7 downto 0)<=r.tf.scr; d(15 downto 8)<="00000000";
when SNR => d(7 downto 0)<=r.tf.snr; d(15 downto 8)<="00000000";
when STAT => d(7 downto 0)<=r.tf.stat; d(15 downto 8)<="00000000";
atao.intrq<='0'; v.intrq:=false;
when DTAP =>
d<=r.tf.dtap; v.dtap_read:=true;
if (v.byte_cnt+2=sector_length) then
atao.dmarq<='0' after Tlr;
end if;
when others => d(15 downto 0)<=(others=>'Z');
end case;
--*********************************READ/WRITE registers end*************
else
if (r.tf.stat(BSY)='1') then --simulate busy, "borrow" feat reg
v.tf.feat:=v.tf.feat-1; --count down timer
if (v.tf.feat="00000000") then
v.tf.stat(BSY):='0'; --clear busy flag
end if;
elsif(v.cmd_started) then
case r.tf.cmd is
--********************************************************************
when WRITE_DMA =>
atao.dmarq<='1';
v.tf.stat(DRQ):='1';
if v.dtap_written then
v.dtap_written:=false;
v.byte_cnt:=v.byte_cnt+2;
if(v.byte_cnt=sector_length) then
v.tf.scr:=v.tf.scr-1;
v.byte_cnt:=0;
if v.tf.scr=X"00" then
atao.dmarq<='0';
v.tf.stat(DRQ):='0';
v.cmd_started:=false;
if v.tf.ctrl(NIEN)='0' then
atao.intrq<='1';
end if;
end if;
end if;
if r.dtap_written then
v.ram.a(log2_size-2 downto log2(sector_length)-1):=
r.scr((log2_size-log2(sector_length)-1) downto 0) - r.tf.scr((log2_size-log2(sector_length)-1) downto 0);
v.ram.a(log2(sector_length)-2 downto 0):=
conv_std_logic_vector((r.byte_cnt/2),log2(sector_length)-1);
v.ram_dta:=v.tf.dtap; v.ram.oe:='1'; v.ram.ce:='0';v.ram.we:='0';
end if;
end if;
--********************************************************************
when WRITE =>
if (not v.pio_started and v.tf.ctrl(NIEN)='0') then
atao.intrq<='1'; v.pio_started:=true; v.intrq:=true;
elsif not v.intrq then
v.tf.stat(DRQ):='1';
if v.dtar_written then
v.dtar_written:=false;
v.byte_cnt:=v.byte_cnt+2;
if(v.byte_cnt=sector_length) then
v.tf.scr:=v.tf.scr-1;
if (v.tf.scr=X"00") then
v.cmd_started:=false; v.pio_started:=false;
end if;
v.byte_cnt:=0;
v.tf.stat(DRQ):='0';
v.tf.stat(BSY):='1';
v.tf.feat:="00001111";
if v.tf.ctrl(NIEN)='0' then
atao.intrq<='1';
end if;
end if;
end if;
if r.dtar_written then
v.ram.a(log2_size-2 downto log2(sector_length)-1):=
r.scr((log2_size-log2(sector_length)-1) downto 0) - r.tf.scr((log2_size-log2(sector_length)-1) downto 0);
v.ram.a(log2(sector_length)-2 downto 0):=
conv_std_logic_vector((r.byte_cnt/2),log2(sector_length)-1);
v.ram_dta:=v.tf.dtar; v.ram.oe:='1'; v.ram.ce:='0';v.ram.we:='0';
end if;
end if;
--********************************************************************
when READ_DMA =>
-- atao.dmarq<='1';
v.tf.stat(DRQ):='1';
if not (v.byte_cnt+2=sector_length) then
atao.dmarq<='1';
end if;
if v.dtap_read and r.dior='0' and atai.dior='1' then --rising dior detect
v.dtap_read:=false;
v.byte_cnt:=v.byte_cnt+2;
if(v.byte_cnt=sector_length) then
v.tf.scr:=v.tf.scr-1;
v.byte_cnt:=0;
if v.tf.scr=X"00" then
-- atao.dmarq<='0';
v.tf.stat(DRQ):='0';
v.cmd_started:=false;
v.ram.oe:='1'; v.ram.ce:='1';v.ram.we:='1';
if v.tf.ctrl(NIEN)='0' then
atao.intrq<='1';
end if;
end if;
end if;
end if;
v.ram.oe:='0'; v.ram.ce:='0';v.ram.we:='1'; v.tf.dtap:=s_d;
v.ram.a(log2_size-2 downto log2(sector_length)-1):=
r.scr((log2_size-log2(sector_length)-1) downto 0) - r.tf.scr((log2_size-log2(sector_length)-1) downto 0);
v.ram.a(log2(sector_length)-2 downto 0):=
conv_std_logic_vector((r.byte_cnt/2),log2(sector_length)-1);
--********************************************************************
when READ =>
if (not v.pio_started and v.tf.ctrl(NIEN)='0') then
atao.intrq<='1'; v.pio_started:=true; v.intrq:=true;
elsif not v.intrq then
v.tf.stat(DRQ):='1';
if v.dtar_read and r.dior='0' and atai.dior='1' then --rising dior detect
v.dtar_read:=false;
v.byte_cnt:=v.byte_cnt+2;
if(v.byte_cnt=sector_length) then
v.tf.scr:=v.tf.scr-1;
if (v.tf.scr=X"00") then
v.cmd_started:=false;
end if;
v.byte_cnt:=0;
v.tf.stat(DRQ):='0';
v.tf.stat(BSY):='1';
v.tf.feat:="00001111";
if v.tf.ctrl(NIEN)='0' then
atao.intrq<='1';
end if;
end if;
end if;
end if;
v.ram.oe:='0'; v.ram.ce:='0';v.ram.we:='1'; v.tf.dtar:=s_d;
v.ram.a(log2_size-2 downto log2(sector_length)-1):=
r.scr((log2_size-log2(sector_length)-1) downto 0) - r.tf.scr((log2_size-log2(sector_length)-1) downto 0);
v.ram.a(log2(sector_length)-2 downto 0):=
conv_std_logic_vector((r.byte_cnt/2),log2(sector_length)-1);
--********************************************************************
when others => v.tf.stat:=v.tf.stat; v.cmd_started:=false;
end case;
end if;
if r.ram.ce='0' and r.ram.oe='1' then
v.ram.oe:='1'; v.ram.ce:='1';v.ram.we:='1'; v.ram_dta:=(others=>'Z');
end if;
if (r.dior='0' and atai.dior='1') then
d(15 downto 0)<=(others=>'Z');
end if;
end if; --read write reg
end if; --reset
ri<=v;
end process comb;
with r.ram.oe select
s_d<=r.ram_dta when '1',
(others=>'Z') when others;
disk : sram16 generic map (index => 0, abits => log2_size-1, fname => sramfile)
port map (r.ram.a, s_d, '0', '0', r.ram.ce, r.ram.we, r.ram.oe);
--**********************SYNC PROCESS******************************************
sync: process(clk) --dior/diow insted?
begin
if rising_edge(clk) then
r<=ri;
end if;
end process sync;
end;
--************************END OF FILE*******************************************
| mit | 890a0d11474dfc3ff61752f446b6121d | 0.500767 | 3.377106 | false | false | false | false |
franz/pocl | examples/accel/rtl/gcu_ic/ic.vhdl | 2 | 10,585 | library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.ext;
use IEEE.std_logic_arith.sxt;
use work.ffaccel_globals.all;
use work.tce_util.all;
entity ffaccel_interconn is
port (
clk : in std_logic;
rstx : in std_logic;
glock : in std_logic;
socket_lsu_i1_data : out std_logic_vector(11 downto 0);
socket_lsu_i1_bus_cntrl : in std_logic_vector(0 downto 0);
socket_lsu_i2_data : out std_logic_vector(31 downto 0);
socket_lsu_i2_bus_cntrl : in std_logic_vector(0 downto 0);
socket_alu_comp_i1_data : out std_logic_vector(31 downto 0);
socket_alu_comp_i1_bus_cntrl : in std_logic_vector(0 downto 0);
socket_alu_comp_i2_data : out std_logic_vector(31 downto 0);
socket_alu_comp_i2_bus_cntrl : in std_logic_vector(0 downto 0);
socket_RF_i1_data : out std_logic_vector(31 downto 0);
socket_RF_i1_bus_cntrl : in std_logic_vector(0 downto 0);
socket_bool_i1_data : out std_logic_vector(0 downto 0);
socket_bool_i1_bus_cntrl : in std_logic_vector(0 downto 0);
socket_gcu_i1_data : out std_logic_vector(IMEMADDRWIDTH-1 downto 0);
socket_gcu_i1_bus_cntrl : in std_logic_vector(0 downto 0);
socket_gcu_i2_data : out std_logic_vector(IMEMADDRWIDTH-1 downto 0);
socket_gcu_i2_bus_cntrl : in std_logic_vector(0 downto 0);
socket_lsu_i1_1_data : out std_logic_vector(31 downto 0);
socket_lsu_i1_1_bus_cntrl : in std_logic_vector(0 downto 0);
socket_lsu_i2_1_data : out std_logic_vector(31 downto 0);
socket_lsu_i2_1_bus_cntrl : in std_logic_vector(0 downto 0);
socket_lsu_i2_1_1_data : out std_logic_vector(9 downto 0);
socket_lsu_i2_1_1_bus_cntrl : in std_logic_vector(0 downto 0);
socket_lsu_i1_1_1_data : out std_logic_vector(31 downto 0);
socket_lsu_i1_1_1_bus_cntrl : in std_logic_vector(0 downto 0);
socket_lsu_i2_1_1_2_1_data : out std_logic_vector(31 downto 0);
socket_lsu_i2_1_1_2_1_bus_cntrl : in std_logic_vector(0 downto 0);
B1_mux_ctrl_in : in std_logic_vector(3 downto 0);
B1_data_0_in : in std_logic_vector(31 downto 0);
B1_data_1_in : in std_logic_vector(31 downto 0);
B1_data_2_in : in std_logic_vector(31 downto 0);
B1_data_3_in : in std_logic_vector(0 downto 0);
B1_data_4_in : in std_logic_vector(IMEMADDRWIDTH-1 downto 0);
B1_data_5_in : in std_logic_vector(31 downto 0);
B1_data_6_in : in std_logic_vector(31 downto 0);
B1_data_7_in : in std_logic_vector(31 downto 0);
B1_data_8_in : in std_logic_vector(31 downto 0);
B1_data_9_in : in std_logic_vector(31 downto 0);
B1_data_10_in : in std_logic_vector(31 downto 0);
B1_1_mux_ctrl_in : in std_logic_vector(3 downto 0);
B1_1_data_0_in : in std_logic_vector(31 downto 0);
B1_1_data_1_in : in std_logic_vector(31 downto 0);
B1_1_data_2_in : in std_logic_vector(31 downto 0);
B1_1_data_3_in : in std_logic_vector(0 downto 0);
B1_1_data_4_in : in std_logic_vector(IMEMADDRWIDTH-1 downto 0);
B1_1_data_5_in : in std_logic_vector(31 downto 0);
B1_1_data_6_in : in std_logic_vector(31 downto 0);
B1_1_data_7_in : in std_logic_vector(31 downto 0);
B1_1_data_8_in : in std_logic_vector(31 downto 0);
B1_1_data_9_in : in std_logic_vector(31 downto 0);
B1_1_data_10_in : in std_logic_vector(31 downto 0);
simm_B1 : in std_logic_vector(31 downto 0);
simm_cntrl_B1 : in std_logic_vector(0 downto 0);
simm_B1_1 : in std_logic_vector(31 downto 0);
simm_cntrl_B1_1 : in std_logic_vector(0 downto 0));
end ffaccel_interconn;
architecture comb_andor of ffaccel_interconn is
signal databus_B1 : std_logic_vector(31 downto 0);
signal databus_B1_1 : std_logic_vector(31 downto 0);
component ffaccel_input_mux_2
generic (
BUSW_0 : integer := 32;
BUSW_1 : integer := 32;
DATAW : integer := 32);
port (
databus0 : in std_logic_vector(BUSW_0-1 downto 0);
databus1 : in std_logic_vector(BUSW_1-1 downto 0);
data : out std_logic_vector(DATAW-1 downto 0);
databus_cntrl : in std_logic_vector(0 downto 0));
end component;
component ffaccel_input_mux_12
generic (
BUSW_0 : integer := 32;
BUSW_1 : integer := 32;
BUSW_2 : integer := 32;
BUSW_3 : integer := 32;
BUSW_4 : integer := 32;
BUSW_5 : integer := 32;
BUSW_6 : integer := 32;
BUSW_7 : integer := 32;
BUSW_8 : integer := 32;
BUSW_9 : integer := 32;
BUSW_10 : integer := 32;
BUSW_11 : integer := 32;
DATAW : integer := 32);
port (
databus0 : in std_logic_vector(BUSW_0-1 downto 0);
databus1 : in std_logic_vector(BUSW_1-1 downto 0);
databus2 : in std_logic_vector(BUSW_2-1 downto 0);
databus3 : in std_logic_vector(BUSW_3-1 downto 0);
databus4 : in std_logic_vector(BUSW_4-1 downto 0);
databus5 : in std_logic_vector(BUSW_5-1 downto 0);
databus6 : in std_logic_vector(BUSW_6-1 downto 0);
databus7 : in std_logic_vector(BUSW_7-1 downto 0);
databus8 : in std_logic_vector(BUSW_8-1 downto 0);
databus9 : in std_logic_vector(BUSW_9-1 downto 0);
databus10 : in std_logic_vector(BUSW_10-1 downto 0);
databus11 : in std_logic_vector(BUSW_11-1 downto 0);
data : out std_logic_vector(DATAW-1 downto 0);
databus_cntrl : in std_logic_vector(3 downto 0));
end component;
begin -- comb_andor
RF_i1 : ffaccel_input_mux_2
generic map (
BUSW_0 => 32,
BUSW_1 => 32,
DATAW => 32)
port map (
databus0 => databus_B1,
databus1 => databus_B1_1,
data => socket_RF_i1_data,
databus_cntrl => socket_RF_i1_bus_cntrl);
alu_comp_i1 : ffaccel_input_mux_2
generic map (
BUSW_0 => 32,
BUSW_1 => 32,
DATAW => 32)
port map (
databus0 => databus_B1,
databus1 => databus_B1_1,
data => socket_alu_comp_i1_data,
databus_cntrl => socket_alu_comp_i1_bus_cntrl);
alu_comp_i2 : ffaccel_input_mux_2
generic map (
BUSW_0 => 32,
BUSW_1 => 32,
DATAW => 32)
port map (
databus0 => databus_B1,
databus1 => databus_B1_1,
data => socket_alu_comp_i2_data,
databus_cntrl => socket_alu_comp_i2_bus_cntrl);
bool_i1 : ffaccel_input_mux_2
generic map (
BUSW_0 => 32,
BUSW_1 => 32,
DATAW => 1)
port map (
databus0 => databus_B1,
databus1 => databus_B1_1,
data => socket_bool_i1_data,
databus_cntrl => socket_bool_i1_bus_cntrl);
gcu_i1 : ffaccel_input_mux_2
generic map (
BUSW_0 => 32,
BUSW_1 => 32,
DATAW => IMEMADDRWIDTH)
port map (
databus0 => databus_B1,
databus1 => databus_B1_1,
data => socket_gcu_i1_data,
databus_cntrl => socket_gcu_i1_bus_cntrl);
gcu_i2 : ffaccel_input_mux_2
generic map (
BUSW_0 => 32,
BUSW_1 => 32,
DATAW => IMEMADDRWIDTH)
port map (
databus0 => databus_B1,
databus1 => databus_B1_1,
data => socket_gcu_i2_data,
databus_cntrl => socket_gcu_i2_bus_cntrl);
lsu_i1 : ffaccel_input_mux_2
generic map (
BUSW_0 => 32,
BUSW_1 => 32,
DATAW => 12)
port map (
databus0 => databus_B1,
databus1 => databus_B1_1,
data => socket_lsu_i1_data,
databus_cntrl => socket_lsu_i1_bus_cntrl);
lsu_i1_1 : ffaccel_input_mux_2
generic map (
BUSW_0 => 32,
BUSW_1 => 32,
DATAW => 32)
port map (
databus0 => databus_B1,
databus1 => databus_B1_1,
data => socket_lsu_i1_1_data,
databus_cntrl => socket_lsu_i1_1_bus_cntrl);
lsu_i1_1_1 : ffaccel_input_mux_2
generic map (
BUSW_0 => 32,
BUSW_1 => 32,
DATAW => 32)
port map (
databus0 => databus_B1,
databus1 => databus_B1_1,
data => socket_lsu_i1_1_1_data,
databus_cntrl => socket_lsu_i1_1_1_bus_cntrl);
lsu_i2 : ffaccel_input_mux_2
generic map (
BUSW_0 => 32,
BUSW_1 => 32,
DATAW => 32)
port map (
databus0 => databus_B1,
databus1 => databus_B1_1,
data => socket_lsu_i2_data,
databus_cntrl => socket_lsu_i2_bus_cntrl);
lsu_i2_1 : ffaccel_input_mux_2
generic map (
BUSW_0 => 32,
BUSW_1 => 32,
DATAW => 32)
port map (
databus0 => databus_B1,
databus1 => databus_B1_1,
data => socket_lsu_i2_1_data,
databus_cntrl => socket_lsu_i2_1_bus_cntrl);
lsu_i2_1_1 : ffaccel_input_mux_2
generic map (
BUSW_0 => 32,
BUSW_1 => 32,
DATAW => 10)
port map (
databus0 => databus_B1,
databus1 => databus_B1_1,
data => socket_lsu_i2_1_1_data,
databus_cntrl => socket_lsu_i2_1_1_bus_cntrl);
lsu_i2_1_1_2_1 : ffaccel_input_mux_2
generic map (
BUSW_0 => 32,
BUSW_1 => 32,
DATAW => 32)
port map (
databus0 => databus_B1,
databus1 => databus_B1_1,
data => socket_lsu_i2_1_1_2_1_data,
databus_cntrl => socket_lsu_i2_1_1_2_1_bus_cntrl);
B1_bus_mux_inst : ffaccel_input_mux_12
generic map (
BUSW_0 => 32,
BUSW_1 => 32,
BUSW_2 => 32,
BUSW_3 => 1,
BUSW_4 => IMEMADDRWIDTH,
BUSW_5 => 32,
BUSW_6 => 32,
BUSW_7 => 32,
BUSW_8 => 32,
BUSW_9 => 32,
BUSW_10 => 32,
BUSW_11 => 32,
DATAW => 32)
port map (
databus0 => B1_data_0_in,
databus1 => B1_data_1_in,
databus2 => B1_data_2_in,
databus3 => B1_data_3_in,
databus4 => B1_data_4_in,
databus5 => B1_data_5_in,
databus6 => B1_data_6_in,
databus7 => B1_data_7_in,
databus8 => B1_data_8_in,
databus9 => B1_data_9_in,
databus10 => B1_data_10_in,
databus11 => simm_B1,
data => databus_B1,
databus_cntrl => B1_mux_ctrl_in);
B1_1_bus_mux_inst : ffaccel_input_mux_12
generic map (
BUSW_0 => 32,
BUSW_1 => 32,
BUSW_2 => 32,
BUSW_3 => 1,
BUSW_4 => IMEMADDRWIDTH,
BUSW_5 => 32,
BUSW_6 => 32,
BUSW_7 => 32,
BUSW_8 => 32,
BUSW_9 => 32,
BUSW_10 => 32,
BUSW_11 => 32,
DATAW => 32)
port map (
databus0 => B1_1_data_0_in,
databus1 => B1_1_data_1_in,
databus2 => B1_1_data_2_in,
databus3 => B1_1_data_3_in,
databus4 => B1_1_data_4_in,
databus5 => B1_1_data_5_in,
databus6 => B1_1_data_6_in,
databus7 => B1_1_data_7_in,
databus8 => B1_1_data_8_in,
databus9 => B1_1_data_9_in,
databus10 => B1_1_data_10_in,
databus11 => simm_B1_1,
data => databus_B1_1,
databus_cntrl => B1_1_mux_ctrl_in);
end comb_andor;
| mit | e71c3e94166f4d95d5375dbc999b9390 | 0.587246 | 2.746497 | false | false | false | false |
impedimentToProgress/UCI-BlueChip | AttackFiles/Attacks/privEsc/lib/techmap/maps/grspwc_net.vhd | 2 | 17,903 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: grspwc
-- File: grspwc.vhd
-- Author: Marko Isomaki - Gaisler Research
-- Description: Provides a link interface to a SpaceWire network
-- with an AHB host interface and RMAP support.
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
entity grspwc_net is
generic(
tech : integer := 0;
sysfreq : integer := 40000;
usegen : integer range 0 to 1 := 1;
nsync : integer range 1 to 2 := 1;
rmap : integer range 0 to 1 := 0;
rmapcrc : integer range 0 to 1 := 0;
fifosize1 : integer range 4 to 32 := 32;
fifosize2 : integer range 16 to 64 := 64;
rxunaligned : integer range 0 to 1 := 0;
rmapbufs : integer range 2 to 8 := 4;
scantest : integer range 0 to 1 := 0
);
port(
rst : in std_ulogic;
clk : in std_ulogic;
txclk : in std_ulogic;
--ahb mst in
hgrant : in std_ulogic;
hready : in std_ulogic;
hresp : in std_logic_vector(1 downto 0);
hrdata : in std_logic_vector(31 downto 0);
--ahb mst out
hbusreq : out std_ulogic;
hlock : out std_ulogic;
htrans : out std_logic_vector(1 downto 0);
haddr : out std_logic_vector(31 downto 0);
hwrite : out std_ulogic;
hsize : out std_logic_vector(2 downto 0);
hburst : out std_logic_vector(2 downto 0);
hprot : out std_logic_vector(3 downto 0);
hwdata : out std_logic_vector(31 downto 0);
--apb slv in
psel : in std_ulogic;
penable : in std_ulogic;
paddr : in std_logic_vector(31 downto 0);
pwrite : in std_ulogic;
pwdata : in std_logic_vector(31 downto 0);
--apb slv out
prdata : out std_logic_vector(31 downto 0);
--spw in
di : in std_logic_vector(1 downto 0);
si : in std_logic_vector(1 downto 0);
--spw out
do : out std_logic_vector(1 downto 0);
so : out std_logic_vector(1 downto 0);
--time iface
tickin : in std_ulogic;
tickout : out std_ulogic;
--irq
irq : out std_logic;
--misc
clkdiv10 : in std_logic_vector(7 downto 0);
dcrstval : in std_logic_vector(9 downto 0);
timerrstval : in std_logic_vector(11 downto 0);
--rmapen
rmapen : in std_ulogic;
--clk bufs
rxclki : in std_logic_vector(1 downto 0);
nrxclki : in std_logic_vector(1 downto 0);
rxclko : out std_logic_vector(1 downto 0);
--rx ahb fifo
rxrenable : out std_ulogic;
rxraddress : out std_logic_vector(4 downto 0);
rxwrite : out std_ulogic;
rxwdata : out std_logic_vector(31 downto 0);
rxwaddress : out std_logic_vector(4 downto 0);
rxrdata : in std_logic_vector(31 downto 0);
--tx ahb fifo
txrenable : out std_ulogic;
txraddress : out std_logic_vector(4 downto 0);
txwrite : out std_ulogic;
txwdata : out std_logic_vector(31 downto 0);
txwaddress : out std_logic_vector(4 downto 0);
txrdata : in std_logic_vector(31 downto 0);
--nchar fifo
ncrenable : out std_ulogic;
ncraddress : out std_logic_vector(5 downto 0);
ncwrite : out std_ulogic;
ncwdata : out std_logic_vector(8 downto 0);
ncwaddress : out std_logic_vector(5 downto 0);
ncrdata : in std_logic_vector(8 downto 0);
--rmap buf
rmrenable : out std_ulogic;
rmraddress : out std_logic_vector(7 downto 0);
rmwrite : out std_ulogic;
rmwdata : out std_logic_vector(7 downto 0);
rmwaddress : out std_logic_vector(7 downto 0);
rmrdata : in std_logic_vector(7 downto 0);
linkdis : out std_ulogic;
testclk : in std_ulogic := '0';
testrst : in std_ulogic := '0';
testen : in std_ulogic := '0'
);
end entity;
architecture rtl of grspwc_net is
component grspwc_unisim
generic(
sysfreq : integer := 40000;
usegen : integer range 0 to 1 := 1;
nsync : integer range 1 to 2 := 1;
rmap : integer range 0 to 1 := 0;
rmapcrc : integer range 0 to 1 := 0;
fifosize1 : integer range 4 to 32 := 32;
fifosize2 : integer range 16 to 64 := 64;
rxunaligned : integer range 0 to 1 := 0;
rmapbufs : integer range 2 to 8 := 4;
scantest : integer range 0 to 1 := 0
);
port(
rst : in std_ulogic;
clk : in std_ulogic;
txclk : in std_ulogic;
--ahb mst in
hgrant : in std_ulogic;
hready : in std_ulogic;
hresp : in std_logic_vector(1 downto 0);
hrdata : in std_logic_vector(31 downto 0);
--ahb mst out
hbusreq : out std_ulogic;
hlock : out std_ulogic;
htrans : out std_logic_vector(1 downto 0);
haddr : out std_logic_vector(31 downto 0);
hwrite : out std_ulogic;
hsize : out std_logic_vector(2 downto 0);
hburst : out std_logic_vector(2 downto 0);
hprot : out std_logic_vector(3 downto 0);
hwdata : out std_logic_vector(31 downto 0);
--apb slv in
psel : in std_ulogic;
penable : in std_ulogic;
paddr : in std_logic_vector(31 downto 0);
pwrite : in std_ulogic;
pwdata : in std_logic_vector(31 downto 0);
--apb slv out
prdata : out std_logic_vector(31 downto 0);
--spw in
di : in std_logic_vector(1 downto 0);
si : in std_logic_vector(1 downto 0);
--spw out
do : out std_logic_vector(1 downto 0);
so : out std_logic_vector(1 downto 0);
--time iface
tickin : in std_ulogic;
tickout : out std_ulogic;
--irq
irq : out std_logic;
--misc
clkdiv10 : in std_logic_vector(7 downto 0);
dcrstval : in std_logic_vector(9 downto 0);
timerrstval : in std_logic_vector(11 downto 0);
--rmapen
rmapen : in std_ulogic;
--clk bufs
rxclki : in std_logic_vector(1 downto 0);
nrxclki : in std_logic_vector(1 downto 0);
rxclko : out std_logic_vector(1 downto 0);
--rx ahb fifo
rxrenable : out std_ulogic;
rxraddress : out std_logic_vector(4 downto 0);
rxwrite : out std_ulogic;
rxwdata : out std_logic_vector(31 downto 0);
rxwaddress : out std_logic_vector(4 downto 0);
rxrdata : in std_logic_vector(31 downto 0);
--tx ahb fifo
txrenable : out std_ulogic;
txraddress : out std_logic_vector(4 downto 0);
txwrite : out std_ulogic;
txwdata : out std_logic_vector(31 downto 0);
txwaddress : out std_logic_vector(4 downto 0);
txrdata : in std_logic_vector(31 downto 0);
--nchar fifo
ncrenable : out std_ulogic;
ncraddress : out std_logic_vector(5 downto 0);
ncwrite : out std_ulogic;
ncwdata : out std_logic_vector(8 downto 0);
ncwaddress : out std_logic_vector(5 downto 0);
ncrdata : in std_logic_vector(8 downto 0);
--rmap buf
rmrenable : out std_ulogic;
rmraddress : out std_logic_vector(7 downto 0);
rmwrite : out std_ulogic;
rmwdata : out std_logic_vector(7 downto 0);
rmwaddress : out std_logic_vector(7 downto 0);
rmrdata : in std_logic_vector(7 downto 0);
linkdis : out std_ulogic;
testclk : in std_ulogic := '0';
testrst : in std_ulogic := '0';
testen : in std_ulogic := '0'
);
end component;
component grspwc_axcelerator
generic(
sysfreq : integer := 40000;
usegen : integer range 0 to 1 := 1;
nsync : integer range 1 to 2 := 1;
rmap : integer range 0 to 1 := 0;
rmapcrc : integer range 0 to 1 := 0;
fifosize1 : integer range 4 to 32 := 32;
fifosize2 : integer range 16 to 64 := 64;
rxunaligned : integer range 0 to 1 := 0;
rmapbufs : integer range 2 to 8 := 4;
scantest : integer range 0 to 1 := 0
);
port(
rst : in std_ulogic;
clk : in std_ulogic;
txclk : in std_ulogic;
--ahb mst in
hgrant : in std_ulogic;
hready : in std_ulogic;
hresp : in std_logic_vector(1 downto 0);
hrdata : in std_logic_vector(31 downto 0);
--ahb mst out
hbusreq : out std_ulogic;
hlock : out std_ulogic;
htrans : out std_logic_vector(1 downto 0);
haddr : out std_logic_vector(31 downto 0);
hwrite : out std_ulogic;
hsize : out std_logic_vector(2 downto 0);
hburst : out std_logic_vector(2 downto 0);
hprot : out std_logic_vector(3 downto 0);
hwdata : out std_logic_vector(31 downto 0);
--apb slv in
psel : in std_ulogic;
penable : in std_ulogic;
paddr : in std_logic_vector(31 downto 0);
pwrite : in std_ulogic;
pwdata : in std_logic_vector(31 downto 0);
--apb slv out
prdata : out std_logic_vector(31 downto 0);
--spw in
di : in std_logic_vector(1 downto 0);
si : in std_logic_vector(1 downto 0);
--spw out
do : out std_logic_vector(1 downto 0);
so : out std_logic_vector(1 downto 0);
--time iface
tickin : in std_ulogic;
tickout : out std_ulogic;
--irq
irq : out std_logic;
--misc
clkdiv10 : in std_logic_vector(7 downto 0);
dcrstval : in std_logic_vector(9 downto 0);
timerrstval : in std_logic_vector(11 downto 0);
--rmapen
rmapen : in std_ulogic;
--clk bufs
rxclki : in std_logic_vector(1 downto 0);
nrxclki : in std_logic_vector(1 downto 0);
rxclko : out std_logic_vector(1 downto 0);
--rx ahb fifo
rxrenable : out std_ulogic;
rxraddress : out std_logic_vector(4 downto 0);
rxwrite : out std_ulogic;
rxwdata : out std_logic_vector(31 downto 0);
rxwaddress : out std_logic_vector(4 downto 0);
rxrdata : in std_logic_vector(31 downto 0);
--tx ahb fifo
txrenable : out std_ulogic;
txraddress : out std_logic_vector(4 downto 0);
txwrite : out std_ulogic;
txwdata : out std_logic_vector(31 downto 0);
txwaddress : out std_logic_vector(4 downto 0);
txrdata : in std_logic_vector(31 downto 0);
--nchar fifo
ncrenable : out std_ulogic;
ncraddress : out std_logic_vector(5 downto 0);
ncwrite : out std_ulogic;
ncwdata : out std_logic_vector(8 downto 0);
ncwaddress : out std_logic_vector(5 downto 0);
ncrdata : in std_logic_vector(8 downto 0);
--rmap buf
rmrenable : out std_ulogic;
rmraddress : out std_logic_vector(7 downto 0);
rmwrite : out std_ulogic;
rmwdata : out std_logic_vector(7 downto 0);
rmwaddress : out std_logic_vector(7 downto 0);
rmrdata : in std_logic_vector(7 downto 0);
linkdis : out std_ulogic;
testclk : in std_ulogic := '0';
testrst : in std_ulogic := '0';
testen : in std_ulogic := '0'
);
end component;
begin
ax : if tech = axcel generate
grspwc0 : grspwc_axcelerator
generic map (sysfreq, usegen, nsync, rmap, rmapcrc, fifosize1, fifosize2,
rxunaligned, rmapbufs, scantest)
port map(
rst => rst,
clk => clk,
txclk => txclk,
--ahb mst in
hgrant => hgrant,
hready => hready,
hresp => hresp,
hrdata => hrdata,
--ahb mst out
hbusreq => hbusreq,
hlock => hlock,
htrans => htrans,
haddr => haddr,
hwrite => hwrite,
hsize => hsize,
hburst => hburst,
hprot => hprot,
hwdata => hwdata,
--apb slv in
psel => psel,
penable => penable,
paddr => paddr,
pwrite => pwrite,
pwdata => pwdata,
--apb slv out
prdata => prdata,
--spw in
di => di,
si => si,
--spw out
do => do,
so => so,
--time iface
tickin => tickin,
tickout => tickout,
--clk bufs
rxclki => rxclki,
nrxclki => nrxclki,
rxclko => rxclko,
--irq
irq => irq,
--misc
clkdiv10 => clkdiv10,
dcrstval => dcrstval,
timerrstval => timerrstval,
--rmapen
rmapen => rmapen,
--rx ahb fifo
rxrenable => rxrenable,
rxraddress => rxraddress,
rxwrite => rxwrite,
rxwdata => rxwdata,
rxwaddress => rxwaddress,
rxrdata => rxrdata,
--tx ahb fifo
txrenable => txrenable,
txraddress => txraddress,
txwrite => txwrite,
txwdata => txwdata,
txwaddress => txwaddress,
txrdata => txrdata,
--nchar fifo
ncrenable => ncrenable,
ncraddress => ncraddress,
ncwrite => ncwrite,
ncwdata => ncwdata,
ncwaddress => ncwaddress,
ncrdata => ncrdata,
--rmap buf
rmrenable => rmrenable,
rmraddress => rmraddress,
rmwrite => rmwrite,
rmwdata => rmwdata,
rmwaddress => rmwaddress,
rmrdata => rmrdata,
linkdis => linkdis,
testclk => testclk,
testrst => testrst,
testen => testen
);
end generate;
xil : if (tech = virtex2) or (tech = virtex4) or (tech = virtex5) or
(tech = spartan3) or (tech = spartan3e) generate
grspwc0 : grspwc_unisim
generic map (sysfreq, usegen, nsync, rmap, rmapcrc, fifosize1, fifosize2,
rxunaligned, rmapbufs, scantest)
port map(
rst => rst,
clk => clk,
txclk => txclk,
--ahb mst in
hgrant => hgrant,
hready => hready,
hresp => hresp,
hrdata => hrdata,
--ahb mst out
hbusreq => hbusreq,
hlock => hlock,
htrans => htrans,
haddr => haddr,
hwrite => hwrite,
hsize => hsize,
hburst => hburst,
hprot => hprot,
hwdata => hwdata,
--apb slv in
psel => psel,
penable => penable,
paddr => paddr,
pwrite => pwrite,
pwdata => pwdata,
--apb slv out
prdata => prdata,
--spw in
di => di,
si => si,
--spw out
do => do,
so => so,
--time iface
tickin => tickin,
tickout => tickout,
--clk bufs
rxclki => rxclki,
nrxclki => nrxclki,
rxclko => rxclko,
--irq
irq => irq,
--misc
clkdiv10 => clkdiv10,
dcrstval => dcrstval,
timerrstval => timerrstval,
--rmapen
rmapen => rmapen,
--rx ahb fifo
rxrenable => rxrenable,
rxraddress => rxraddress,
rxwrite => rxwrite,
rxwdata => rxwdata,
rxwaddress => rxwaddress,
rxrdata => rxrdata,
--tx ahb fifo
txrenable => txrenable,
txraddress => txraddress,
txwrite => txwrite,
txwdata => txwdata,
txwaddress => txwaddress,
txrdata => txrdata,
--nchar fifo
ncrenable => ncrenable,
ncraddress => ncraddress,
ncwrite => ncwrite,
ncwdata => ncwdata,
ncwaddress => ncwaddress,
ncrdata => ncrdata,
--rmap buf
rmrenable => rmrenable,
rmraddress => rmraddress,
rmwrite => rmwrite,
rmwdata => rmwdata,
rmwaddress => rmwaddress,
rmrdata => rmrdata,
linkdis => linkdis,
testclk => testclk,
testrst => testrst,
testen => testen
);
end generate;
-- pragma translate_off
nonet : if not ((tech = virtex2) or (tech = virtex4) or (tech = virtex5) or
(tech = spartan3) or (tech = spartan3e) or (tech = axcel))
generate
err : process
begin
assert false report "ERROR : No GRSPWC netlist available for this process!"
severity failure;
wait;
end process;
end generate;
-- pragma translate_on
end architecture;
| mit | cdcce47049fa5a1f9539548089944806 | 0.532201 | 3.841845 | false | true | false | false |
impedimentToProgress/UCI-BlueChip | AttackFiles/Attacks/privEsc/lib/techmap/cycloneiii/cycloneiii_ddr_phy.vhd | 2 | 21,959 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: cycloneiii_ddr_phy
-- File: cycloneiii_ddr_phy.vhd
-- Author: Jiri Gaisler, Gaisler Research
-- Description: DDR PHY for Altera FPGAs
------------------------------------------------------------------------------
LIBRARY cycloneiii;
USE cycloneiii.all;
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY altdqs_cyciii_adqs_n7i2 IS
generic (width : integer := 2; period : string := "10000ps");
PORT
(
dll_delayctrlout : OUT STD_LOGIC_VECTOR (5 DOWNTO 0);
dqinclk : OUT STD_LOGIC_VECTOR (width-1 downto 0);
dqs_datain_h : IN STD_LOGIC_VECTOR (width-1 downto 0);
dqs_datain_l : IN STD_LOGIC_VECTOR (width-1 downto 0);
dqs_padio : INOUT STD_LOGIC_VECTOR (width-1 downto 0);
dqsundelayedout : OUT STD_LOGIC_VECTOR (width-1 downto 0);
inclk : IN STD_LOGIC := '0';
oe : IN STD_LOGIC_VECTOR (width-1 downto 0) := (OTHERS => '1');
outclk : IN STD_LOGIC_VECTOR (width-1 downto 0);
outclkena : IN STD_LOGIC_VECTOR (width-1 downto 0) := (OTHERS => '1')
);
END altdqs_cyciii_adqs_n7i2;
ARCHITECTURE RTL OF altdqs_cyciii_adqs_n7i2 IS
-- ATTRIBUTE synthesis_clearbox : boolean;
-- ATTRIBUTE synthesis_clearbox OF RTL : ARCHITECTURE IS true;
SIGNAL wire_cyciii_dll1_delayctrlout : STD_LOGIC_VECTOR (5 DOWNTO 0);
SIGNAL wire_cyciii_dll1_dqsupdate : STD_LOGIC;
SIGNAL wire_cyciii_dll1_offsetctrlout : STD_LOGIC_VECTOR (5 DOWNTO 0);
SIGNAL wire_cyciii_io2a_combout : STD_LOGIC_VECTOR (width-1 downto 0);
SIGNAL wire_cyciii_io2a_datain : STD_LOGIC_VECTOR (width-1 downto 0);
SIGNAL wire_cyciii_io2a_ddiodatain : STD_LOGIC_VECTOR (width-1 downto 0);
SIGNAL wire_cyciii_io2a_dqsbusout : STD_LOGIC_VECTOR (width-1 downto 0);
SIGNAL wire_cyciii_io2a_oe : STD_LOGIC_VECTOR (width-1 downto 0);
SIGNAL wire_cyciii_io2a_outclk : STD_LOGIC_VECTOR (width-1 downto 0);
SIGNAL wire_cyciii_io2a_outclkena : STD_LOGIC_VECTOR (width-1 downto 0);
SIGNAL delay_ctrl : STD_LOGIC_VECTOR (5 DOWNTO 0);
SIGNAL dqs_update : STD_LOGIC;
SIGNAL offset_ctrl : STD_LOGIC_VECTOR (5 DOWNTO 0);
COMPONENT cycloneiii_dll
GENERIC
(
DELAY_BUFFER_MODE : STRING := "low";
DELAY_CHAIN_LENGTH : NATURAL := 12;
DELAYCTRLOUT_MODE : STRING := "normal";
INPUT_FREQUENCY : STRING;
JITTER_REDUCTION : STRING := "false";
OFFSETCTRLOUT_MODE : STRING := "static";
SIM_LOOP_DELAY_INCREMENT : NATURAL := 0;
SIM_LOOP_INTRINSIC_DELAY : NATURAL := 0;
SIM_VALID_LOCK : NATURAL := 5;
SIM_VALID_LOCKCOUNT : NATURAL := 0;
STATIC_DELAY_CTRL : NATURAL := 0;
STATIC_OFFSET : STRING;
USE_UPNDNIN : STRING := "false";
USE_UPNDNINCLKENA : STRING := "false";
lpm_type : STRING := "cycloneiii_dll"
);
PORT
(
addnsub : IN STD_LOGIC := '1';
aload : IN STD_LOGIC := '0';
clk : IN STD_LOGIC;
delayctrlout : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
dqsupdate : OUT STD_LOGIC;
offset : IN STD_LOGIC_VECTOR(5 DOWNTO 0) := (OTHERS => '0');
offsetctrlout : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
upndnin : IN STD_LOGIC := '0';
upndninclkena : IN STD_LOGIC := '1';
upndnout : OUT STD_LOGIC
);
END COMPONENT;
COMPONENT cycloneiii_io
GENERIC
(
BUS_HOLD : STRING := "false";
DDIO_MODE : STRING := "none";
DDIOINCLK_INPUT : STRING := "negated_inclk";
DQS_CTRL_LATCHES_ENABLE : STRING := "false";
DQS_DELAY_BUFFER_MODE : STRING := "none";
DQS_EDGE_DETECT_ENABLE : STRING := "false";
DQS_INPUT_FREQUENCY : STRING := "unused";
DQS_OFFSETCTRL_ENABLE : STRING := "false";
DQS_OUT_MODE : STRING := "none";
DQS_PHASE_SHIFT : NATURAL := 0;
EXTEND_OE_DISABLE : STRING := "false";
GATED_DQS : STRING := "false";
INCLK_INPUT : STRING := "normal";
INPUT_ASYNC_RESET : STRING := "none";
INPUT_POWER_UP : STRING := "low";
INPUT_REGISTER_MODE : STRING := "none";
INPUT_SYNC_RESET : STRING := "none";
OE_ASYNC_RESET : STRING := "none";
OE_POWER_UP : STRING := "low";
OE_REGISTER_MODE : STRING := "none";
OE_SYNC_RESET : STRING := "none";
OPEN_DRAIN_OUTPUT : STRING := "false";
OPERATION_MODE : STRING;
OUTPUT_ASYNC_RESET : STRING := "none";
OUTPUT_POWER_UP : STRING := "low";
OUTPUT_REGISTER_MODE : STRING := "none";
OUTPUT_SYNC_RESET : STRING := "none";
SIM_DQS_DELAY_INCREMENT : NATURAL := 0;
SIM_DQS_INTRINSIC_DELAY : NATURAL := 0;
SIM_DQS_OFFSET_INCREMENT : NATURAL := 0;
TIE_OFF_OE_CLOCK_ENABLE : STRING := "false";
TIE_OFF_OUTPUT_CLOCK_ENABLE : STRING := "false";
lpm_type : STRING := "cycloneiii_io"
);
PORT
(
areset : IN STD_LOGIC := '0';
combout : OUT STD_LOGIC;
datain : IN STD_LOGIC := '0';
ddiodatain : IN STD_LOGIC := '0';
ddioinclk : IN STD_LOGIC := '0';
ddioregout : OUT STD_LOGIC;
delayctrlin : IN STD_LOGIC_VECTOR(5 DOWNTO 0) := (OTHERS => '0');
dqsbusout : OUT STD_LOGIC;
dqsupdateen : IN STD_LOGIC := '1';
inclk : IN STD_LOGIC := '0';
inclkena : IN STD_LOGIC := '1';
linkin : IN STD_LOGIC := '0';
linkout : OUT STD_LOGIC;
oe : IN STD_LOGIC := '1';
offsetctrlin : IN STD_LOGIC_VECTOR(5 DOWNTO 0) := (OTHERS => '0');
outclk : IN STD_LOGIC := '0';
outclkena : IN STD_LOGIC := '1';
padio : INOUT STD_LOGIC;
regout : OUT STD_LOGIC;
sreset : IN STD_LOGIC := '0';
terminationcontrol : IN STD_LOGIC_VECTOR(13 DOWNTO 0) := (OTHERS => '0')
);
END COMPONENT;
BEGIN
delay_ctrl <= wire_cyciii_dll1_delayctrlout;
dll_delayctrlout <= delay_ctrl;
dqinclk <= wire_cyciii_io2a_dqsbusout;
dqs_update <= wire_cyciii_dll1_dqsupdate;
dqsundelayedout <= wire_cyciii_io2a_combout;
offset_ctrl <= wire_cyciii_dll1_offsetctrlout;
cyciii_dll1 : cycloneiii_dll
GENERIC MAP (
DELAY_BUFFER_MODE => "low",
DELAY_CHAIN_LENGTH => 12,
DELAYCTRLOUT_MODE => "normal",
INPUT_FREQUENCY => period, --"10000ps",
JITTER_REDUCTION => "false",
OFFSETCTRLOUT_MODE => "static",
SIM_LOOP_DELAY_INCREMENT => 132,
SIM_LOOP_INTRINSIC_DELAY => 3840,
SIM_VALID_LOCK => 1,
SIM_VALID_LOCKCOUNT => 46,
STATIC_OFFSET => "0",
USE_UPNDNIN => "false",
USE_UPNDNINCLKENA => "false"
)
PORT MAP (
clk => inclk,
delayctrlout => wire_cyciii_dll1_delayctrlout,
dqsupdate => wire_cyciii_dll1_dqsupdate,
offsetctrlout => wire_cyciii_dll1_offsetctrlout
);
wire_cyciii_io2a_datain <= dqs_datain_h;
wire_cyciii_io2a_ddiodatain <= dqs_datain_l;
wire_cyciii_io2a_oe <= oe;
wire_cyciii_io2a_outclk <= outclk;
wire_cyciii_io2a_outclkena <= outclkena;
loop0 : FOR i IN 0 TO width-1 GENERATE
cyciii_io2a : cycloneiii_io
GENERIC MAP (
DDIO_MODE => "output",
DQS_CTRL_LATCHES_ENABLE => "true",
DQS_DELAY_BUFFER_MODE => "low",
DQS_EDGE_DETECT_ENABLE => "false",
DQS_INPUT_FREQUENCY => period, --"10000ps",
DQS_OFFSETCTRL_ENABLE => "true",
DQS_OUT_MODE => "delay_chain3",
DQS_PHASE_SHIFT => 9000,
EXTEND_OE_DISABLE => "false",
GATED_DQS => "false",
OE_ASYNC_RESET => "none",
OE_POWER_UP => "low",
OE_REGISTER_MODE => "register",
OE_SYNC_RESET => "none",
OPEN_DRAIN_OUTPUT => "false",
OPERATION_MODE => "bidir",
OUTPUT_ASYNC_RESET => "none",
OUTPUT_POWER_UP => "low",
OUTPUT_REGISTER_MODE => "register",
OUTPUT_SYNC_RESET => "none",
SIM_DQS_DELAY_INCREMENT => 22,
SIM_DQS_INTRINSIC_DELAY => 960,
SIM_DQS_OFFSET_INCREMENT => 11,
TIE_OFF_OE_CLOCK_ENABLE => "false",
TIE_OFF_OUTPUT_CLOCK_ENABLE => "false"
)
PORT MAP (
combout => wire_cyciii_io2a_combout(i),
datain => wire_cyciii_io2a_datain(i),
ddiodatain => wire_cyciii_io2a_ddiodatain(i),
delayctrlin => delay_ctrl,
dqsbusout => wire_cyciii_io2a_dqsbusout(i),
dqsupdateen => dqs_update,
oe => wire_cyciii_io2a_oe(i),
offsetctrlin => offset_ctrl,
outclk => wire_cyciii_io2a_outclk(i),
outclkena => wire_cyciii_io2a_outclkena(i),
padio => dqs_padio(i)
);
END GENERATE loop0;
END RTL; --altdqs_cyciii_adqs_n7i2
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY altdqs_cyciii IS
generic (width : integer := 2; period : string := "10000ps");
PORT
(
dqs_datain_h : IN STD_LOGIC_VECTOR (width-1 downto 0);
dqs_datain_l : IN STD_LOGIC_VECTOR (width-1 downto 0);
inclk : IN STD_LOGIC ;
oe : IN STD_LOGIC_VECTOR (width-1 downto 0);
outclk : IN STD_LOGIC_VECTOR (width-1 downto 0);
dll_delayctrlout : OUT STD_LOGIC_VECTOR (5 DOWNTO 0);
dqinclk : OUT STD_LOGIC_VECTOR (width-1 downto 0);
dqs_padio : INOUT STD_LOGIC_VECTOR (width-1 downto 0);
dqsundelayedout : OUT STD_LOGIC_VECTOR (width-1 downto 0)
);
END;
ARCHITECTURE RTL OF altdqs_cyciii IS
-- ATTRIBUTE synthesis_clearbox: boolean;
-- ATTRIBUTE synthesis_clearbox OF RTL: ARCHITECTURE IS TRUE;
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (5 DOWNTO 0);
SIGNAL sub_wire1 : STD_LOGIC_VECTOR (width-1 downto 0);
SIGNAL sub_wire2 : STD_LOGIC_VECTOR (width-1 downto 0);
SIGNAL sub_wire3_bv : BIT_VECTOR (width-1 downto 0);
SIGNAL sub_wire3 : STD_LOGIC_VECTOR (width-1 downto 0);
COMPONENT altdqs_cyciii_adqs_n7i2
generic (width : integer := 2; period : string := "10000ps");
PORT (
outclk : IN STD_LOGIC_VECTOR (width-1 downto 0);
dqs_padio : INOUT STD_LOGIC_VECTOR (width-1 downto 0);
outclkena : IN STD_LOGIC_VECTOR (width-1 downto 0);
oe : IN STD_LOGIC_VECTOR (width-1 downto 0);
dqs_datain_h : IN STD_LOGIC_VECTOR (width-1 downto 0);
inclk : IN STD_LOGIC ;
dqs_datain_l : IN STD_LOGIC_VECTOR (width-1 downto 0);
dll_delayctrlout : OUT STD_LOGIC_VECTOR (5 DOWNTO 0);
dqinclk : OUT STD_LOGIC_VECTOR (width-1 downto 0);
dqsundelayedout : OUT STD_LOGIC_VECTOR (width-1 downto 0)
);
END COMPONENT;
BEGIN
sub_wire3_bv(width-1 downto 0) <= (others => '1');
sub_wire3 <= To_stdlogicvector(sub_wire3_bv);
dll_delayctrlout <= sub_wire0(5 DOWNTO 0);
dqinclk <= not sub_wire1(width-1 downto 0);
dqsundelayedout <= sub_wire2(width-1 downto 0);
altdqs_cyciii_adqs_n7i2_component : altdqs_cyciii_adqs_n7i2
generic map (width, period)
PORT MAP (
outclk => outclk,
outclkena => sub_wire3,
oe => oe,
dqs_datain_h => dqs_datain_h,
inclk => inclk,
dqs_datain_l => dqs_datain_l,
dll_delayctrlout => sub_wire0,
dqinclk => sub_wire1,
dqsundelayedout => sub_wire2,
dqs_padio => dqs_padio
);
END RTL;
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.stdlib.all;
library techmap;
use techmap.gencomp.all;
library altera_mf;
use altera_mf.altera_mf_components.all;
------------------------------------------------------------------
-- CYCLONEIII DDR PHY --------------------------------------------
------------------------------------------------------------------
entity cycloneiii_ddr_phy is
generic (MHz : integer := 100; rstdelay : integer := 200;
dbits : integer := 16; clk_mul : integer := 2 ;
clk_div : integer := 2);
port (
rst : in std_ulogic;
clk : in std_logic; -- input clock
clkout : out std_ulogic; -- system clock
lock : out std_ulogic; -- DCM locked
ddr_clk : out std_logic_vector(2 downto 0);
ddr_clkb : out std_logic_vector(2 downto 0);
ddr_clk_fb_out : out std_logic;
ddr_clk_fb : in std_logic;
ddr_cke : out std_logic_vector(1 downto 0);
ddr_csb : out std_logic_vector(1 downto 0);
ddr_web : out std_ulogic; -- ddr write enable
ddr_rasb : out std_ulogic; -- ddr ras
ddr_casb : out std_ulogic; -- ddr cas
ddr_dm : out std_logic_vector (dbits/8-1 downto 0); -- ddr dm
ddr_dqs : inout std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
ddr_ad : out std_logic_vector (13 downto 0); -- ddr address
ddr_ba : out std_logic_vector (1 downto 0); -- ddr bank address
ddr_dq : inout std_logic_vector (dbits-1 downto 0); -- ddr data
addr : in std_logic_vector (13 downto 0); -- data mask
ba : in std_logic_vector ( 1 downto 0); -- data mask
dqin : out std_logic_vector (dbits*2-1 downto 0); -- ddr input data
dqout : in std_logic_vector (dbits*2-1 downto 0); -- ddr input data
dm : in std_logic_vector (dbits/4-1 downto 0); -- data mask
oen : in std_ulogic;
dqs : in std_ulogic;
dqsoen : in std_ulogic;
rasn : in std_ulogic;
casn : in std_ulogic;
wen : in std_ulogic;
csn : in std_logic_vector(1 downto 0);
cke : in std_logic_vector(1 downto 0)
);
end;
architecture rtl of cycloneiii_ddr_phy is
signal vcc, gnd, dqsn, oe, lockl : std_logic;
signal ddr_clk_fb_outr : std_ulogic;
signal ddr_clk_fbl, fbclk : std_ulogic;
signal ddr_rasnr, ddr_casnr, ddr_wenr : std_ulogic;
signal ddr_clkl, ddr_clkbl : std_logic_vector(2 downto 0);
signal ddr_csnr, ddr_ckenr, ckel : std_logic_vector(1 downto 0);
signal clk_0ro, clk_90ro, clk_180ro, clk_270ro : std_ulogic;
signal clk_0r, clk_90r, clk_180r, clk_270r : std_ulogic;
signal clk0r, clk90r, clk180r, clk270r : std_ulogic;
signal locked, vlockl, ddrclkfbl : std_ulogic;
signal clk4, clk5 : std_logic;
signal ddr_dqin : std_logic_vector (dbits-1 downto 0); -- ddr data
signal ddr_dqout : std_logic_vector (dbits-1 downto 0); -- ddr data
signal ddr_dqoen : std_logic_vector (dbits-1 downto 0); -- ddr data
signal ddr_adr : std_logic_vector (13 downto 0); -- ddr address
signal ddr_bar : std_logic_vector (1 downto 0); -- ddr address
signal ddr_dmr : std_logic_vector (dbits/8-1 downto 0); -- ddr address
signal ddr_dqsin : std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
signal ddr_dqsoen : std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
signal ddr_dqsoutl : std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
signal dqsdel, dqsclk : std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
signal da : std_logic_vector (dbits-1 downto 0); -- ddr data
signal dqinl : std_logic_vector (dbits-1 downto 0); -- ddr data
signal dllrst : std_logic_vector(0 to 3);
signal dll0rst : std_logic_vector(0 to 3);
signal mlock, mclkfb, mclk, mclkfx, mclk0 : std_ulogic;
signal gndv : std_logic_vector (dbits-1 downto 0); -- ddr dqs
signal pclkout : std_logic_vector (5 downto 1);
signal ddr_clkin : std_logic_vector(0 to 2);
signal dqinclk : std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
signal dqsoclk : std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
signal dqsnv : std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
constant DDR_FREQ : integer := (MHz * clk_mul) / clk_div;
component altdqs_cyciii
generic (width : integer := 2; period : string := "10000ps");
PORT
(
dqs_datain_h : IN STD_LOGIC_VECTOR (width-1 downto 0);
dqs_datain_l : IN STD_LOGIC_VECTOR (width-1 downto 0);
inclk : IN STD_LOGIC ;
oe : IN STD_LOGIC_VECTOR (width-1 downto 0);
outclk : IN STD_LOGIC_VECTOR (width-1 downto 0);
dll_delayctrlout : OUT STD_LOGIC_VECTOR (5 DOWNTO 0);
dqinclk : OUT STD_LOGIC_VECTOR (width-1 downto 0);
dqs_padio : INOUT STD_LOGIC_VECTOR (width-1 downto 0);
dqsundelayedout : OUT STD_LOGIC_VECTOR (width-1 downto 0)
);
END component;
type phasevec is array (1 to 3) of string(1 to 4);
type phasevecarr is array (10 to 13) of phasevec;
constant phasearr : phasevecarr := (
("2500", "5000", "7500"), ("2273", "4545", "6818"), -- 100 & 110 MHz
("2083", "4167", "6250"), ("1923", "3846", "5769")); -- 120 & 130 MHz
type periodtype is array (10 to 13) of string(1 to 6);
constant periodstr : periodtype := ("9999ps", "9090ps", "8333ps", "7692ps");
begin
oe <= not oen; vcc <= '1'; gnd <= '0'; gndv <= (others => '0');
mclk <= clk;
-- clkout <= clk_270r;
-- clkout <= clk_0r when DDR_FREQ >= 110 else clk_270r;
clkout <= clk_90r when DDR_FREQ > 120 else clk_0r;
clk0r <= clk_270r; clk90r <= clk_0r;
clk180r <= clk_90r; clk270r <= clk_180r;
dll : altpll
generic map (
intended_device_family => "CycloneIII",
operation_mode => "NORMAL",
inclk0_input_frequency => 1000000/MHz,
inclk1_input_frequency => 1000000/MHz,
clk4_multiply_by => clk_mul, clk4_divide_by => clk_div,
clk3_multiply_by => clk_mul, clk3_divide_by => clk_div,
clk2_multiply_by => clk_mul, clk2_divide_by => clk_div,
clk1_multiply_by => clk_mul, clk1_divide_by => clk_div,
clk0_multiply_by => clk_mul, clk0_divide_by => clk_div,
clk3_phase_shift => phasearr(DDR_FREQ/10)(3),
clk2_phase_shift => phasearr(DDR_FREQ/10)(2),
clk1_phase_shift => phasearr(DDR_FREQ/10)(1)
-- clk3_phase_shift => "6250", clk2_phase_shift => "4167", clk1_phase_shift => "2083"
-- clk3_phase_shift => "7500", clk2_phase_shift => "5000", clk1_phase_shift => "2500"
)
port map ( inclk(0) => mclk, inclk(1) => gnd, clk(0) => clk_0r,
clk(1) => clk_90r, clk(2) => clk_180r, clk(3) => clk_270r,
clk(4) => clk4, clk(5) => clk5, locked => lockl);
rstdel : process (mclk, rst, lockl)
begin
if rst = '0' then dllrst <= (others => '1');
elsif rising_edge(mclk) then
dllrst <= dllrst(1 to 3) & '0';
end if;
end process;
rdel : if rstdelay /= 0 generate
rcnt : process (clk_0r)
variable cnt : std_logic_vector(15 downto 0);
variable vlock, co : std_ulogic;
begin
if rising_edge(clk_0r) then
co := cnt(15);
vlockl <= vlock;
if lockl = '0' then
cnt := conv_std_logic_vector(rstdelay*DDR_FREQ, 16); vlock := '0';
else
if vlock = '0' then
cnt := cnt -1; vlock := cnt(15) and not co;
end if;
end if;
end if;
if lockl = '0' then
vlock := '0';
end if;
end process;
end generate;
locked <= lockl when rstdelay = 0 else vlockl;
lock <= locked;
-- Generate external DDR clock
-- fbclkpad : altddio_out generic map (width => 1)
-- port map ( datain_h(0) => vcc, datain_l(0) => gnd,
-- outclock => clk90r, dataout(0) => ddr_clk_fb_out);
ddrclocks : for i in 0 to 2 generate
clkpad : altddio_out generic map (width => 1, INTENDED_DEVICE_FAMILY => "CYCLONEIII")
port map ( datain_h(0) => vcc, datain_l(0) => gnd,
outclock => clk90r, dataout(0) => ddr_clk(i));
clknpad : altddio_out generic map (width => 1, INTENDED_DEVICE_FAMILY => "CYCLONEIII")
port map ( datain_h(0) => gnd, datain_l(0) => vcc,
outclock => clk90r, dataout(0) => ddr_clkb(i));
end generate;
csnpads : altddio_out generic map (width => 2, INTENDED_DEVICE_FAMILY => "CYCLONEIII")
port map ( datain_h => csn(1 downto 0), datain_l => csn(1 downto 0),
outclock => clk0r, dataout => ddr_csb(1 downto 0));
ckepads : altddio_out generic map (width => 2, INTENDED_DEVICE_FAMILY => "CYCLONEIII")
port map ( datain_h => ckel(1 downto 0), datain_l => ckel(1 downto 0),
outclock => clk0r, dataout => ddr_cke(1 downto 0));
ddrbanks : for i in 0 to 1 generate
ckel(i) <= cke(i) and locked;
end generate;
rasnpad : altddio_out generic map (width => 1,
INTENDED_DEVICE_FAMILY => "CYCLONEIII")
port map ( datain_h(0) => rasn, datain_l(0) => rasn,
outclock => clk0r, dataout(0) => ddr_rasb);
casnpad : altddio_out generic map (width => 1,
INTENDED_DEVICE_FAMILY => "CYCLONEIII")
port map ( datain_h(0) => casn, datain_l(0) => casn,
outclock => clk0r, dataout(0) => ddr_casb);
wenpad : altddio_out generic map (width => 1,
INTENDED_DEVICE_FAMILY => "CYCLONEIII")
port map ( datain_h(0) => wen, datain_l(0) => wen,
outclock => clk0r, dataout(0) => ddr_web);
dmpads : altddio_out generic map (width => dbits/8,
INTENDED_DEVICE_FAMILY => "CYCLONEIII")
port map (
datain_h => dm(dbits/8*2-1 downto dbits/8),
datain_l => dm(dbits/8-1 downto 0),
outclock => clk0r, dataout => ddr_dm
);
bapads : altddio_out generic map (width => 2)
port map (
datain_h => ba, datain_l => ba,
outclock => clk0r, dataout => ddr_ba
);
addrpads : altddio_out generic map (width => 14)
port map (
datain_h => addr, datain_l => addr,
outclock => clk0r, dataout => ddr_ad
);
-- DQS generation
dqsnv <= (others => dqsn);
dqsoclk <= (others => clk90r);
altdqs0 : altdqs_cyciii generic map (dbits/8, periodstr(DDR_FREQ/10))
port map (dqs_datain_h => dqsnv, dqs_datain_l => gndv(dbits/8-1 downto 0),
inclk => clk270r, oe => ddr_dqsoen, outclk => dqsoclk,
dll_delayctrlout => open, dqinclk => dqinclk, dqs_padio => ddr_dqs,
dqsundelayedout => open );
-- Data bus
dqgen : for i in 0 to dbits/8-1 generate
qi : altddio_bidir generic map (width => 8, oe_reg =>"REGISTERED",
INTENDED_DEVICE_FAMILY => "CYCLONEIII")
port map (
datain_l => dqout(i*8+7 downto i*8),
datain_h => dqout(i*8+7+dbits downto dbits+i*8),
inclock => dqinclk(i), --clk270r,
outclock => clk0r, oe => oe,
dataout_h => dqin(i*8+7 downto i*8),
dataout_l => dqin(i*8+7+dbits downto dbits+i*8), --dqinl(i*8+7 downto i*8),
padio => ddr_dq(i*8+7 downto i*8));
end generate;
dqsreg : process(clk180r)
begin
if rising_edge(clk180r) then
dqsn <= oe;
end if;
end process;
oereg : process(clk0r)
begin
if rising_edge(clk0r) then
ddr_dqsoen(dbits/8-1 downto 0) <= (others => not dqsoen);
end if;
end process;
end;
| mit | be26c6505dfc3e15edb53fe1e8a37a6d | 0.629491 | 2.96984 | false | false | false | false |
michaelfivez/ascon_hardware_implementation | ascon12864_unrolled3/API_plus_CipherCore/CypherCore.vhd | 1 | 14,259 | -------------------------------------------------------------------------------
--! @project Unrolled (3) hardware implementation of Asconv1286
--! @author Michael Fivez
--! @license This project is released under the GNU Public License.
--! The license and distribution terms for this file may be
--! found in the file LICENSE in this distribution or at
--! http://www.gnu.org/licenses/gpl-3.0.txt
--! @note This is an hardware implementation made for my graduation thesis
--! at the KULeuven, in the COSIC department (year 2015-2016)
--! The thesis is titled 'Energy efficient hardware implementations of CAESAR submissions',
--! and can be found on the COSIC website (www.esat.kuleuven.be/cosic/publications)
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.ALL;
use ieee.numeric_std.all;
entity CipherCore is
generic (
G_NPUB_SIZE : integer := 128; --! Npub size (bits)
G_NSEC_SIZE : integer := 128; --! Nsec size (bits)
G_DBLK_SIZE : integer := 64; --! Data Block size (bits)
G_KEY_SIZE : integer := 128; --! Key size (bits)
G_RDKEY_SIZE : integer := 128; --! Round Key size (bits)
G_TAG_SIZE : integer := 128; --! Tag size (bits)
G_BS_BYTES : integer := 3; --! The number of bits required to hold block size expressed in bytes = log2_ceil(max(G_ABLK_SIZE,G_DBLK_SIZE)/8)
G_CTR_AD_SIZE : integer := 64; --! Maximum size for the counter that keeps track of authenticated data
G_CTR_D_SIZE : integer := 64 --! Maximum size for the counter that keeps track of data
);
port (
clk : in std_logic;
rst : in std_logic;
npub : in std_logic_vector(G_NPUB_SIZE -1 downto 0);
nsec : in std_logic_vector(G_NSEC_SIZE -1 downto 0);
key : in std_logic_vector(G_KEY_SIZE -1 downto 0);
rdkey : in std_logic_vector(G_RDKEY_SIZE -1 downto 0);
bdi : in std_logic_vector(G_DBLK_SIZE -1 downto 0);
exp_tag : in std_logic_vector(G_TAG_SIZE -1 downto 0);
len_a : in std_logic_vector(G_CTR_AD_SIZE -1 downto 0);
len_d : in std_logic_vector(G_CTR_D_SIZE -1 downto 0);
key_ready : in std_logic;
key_updated : out std_logic;
key_needs_update : in std_logic;
rdkey_ready : in std_logic;
rdkey_read : out std_logic;
npub_ready : in std_logic;
npub_read : out std_logic;
nsec_ready : in std_logic;
nsec_read : out std_logic;
bdi_ready : in std_logic;
bdi_proc : in std_logic;
bdi_ad : in std_logic;
bdi_nsec : in std_logic;
bdi_pad : in std_logic;
bdi_decrypt : in std_logic;
bdi_eot : in std_logic;
bdi_eoi : in std_logic;
bdi_read : out std_logic;
bdi_size : in std_logic_vector(G_BS_BYTES -1 downto 0);
bdi_valid_bytes : in std_logic_vector(G_DBLK_SIZE/8 -1 downto 0);
bdi_pad_loc : in std_logic_vector(G_DBLK_SIZE/8 -1 downto 0);
bdi_nodata : in std_logic;
exp_tag_ready : in std_logic;
bdo_ready : in std_logic;
bdo_write : out std_logic;
bdo : out std_logic_vector(G_DBLK_SIZE -1 downto 0);
bdo_size : out std_logic_vector(G_BS_BYTES+1 -1 downto 0);
bdo_nsec : out std_logic;
tag_ready : in std_logic;
tag_write : out std_logic;
tag : out std_logic_vector(G_TAG_SIZE -1 downto 0);
msg_auth_done : out std_logic;
msg_auth_valid : out std_logic
);
end entity CipherCore;
architecture structure of CipherCore is
-- Registers
signal keyreg,npubreg : std_logic_vector(127 downto 0);
-- Control signals AsconCore
signal AsconStart : std_logic;
signal AsconMode : std_logic_vector(3 downto 0);
signal AsconBusy : std_logic;
signal AsconSize : std_logic_vector(2 downto 0);
signal AsconInput : std_logic_vector(63 downto 0);
-- Internal Datapath signals
signal AsconOutput : std_logic_vector(127 downto 0);
begin
-- Morus_core entity
AsconCore : entity work.Ascon_StateUpdate port map(clk,rst,AsconStart,AsconMode,AsconSize,npubreg,keyreg,AsconInput,AsconBusy,AsconOutput);
----------------------------------------
------ DataPath for CipherCore ---------
----------------------------------------
datapath: process(AsconOutput,exp_tag,bdi,AsconInput) is
begin
-- Connect signals to the MorusCore
AsconInput <= bdi;
tag <= AsconOutput;
bdo <= AsconOutput(63 downto 0);
if AsconOutput = exp_tag then
msg_auth_valid <= '1';
else
msg_auth_valid <= '0';
end if;
end process datapath;
----------------------------------------
------ ControlPath for CipherCore ------
----------------------------------------
fsm: process(clk, rst) is
type state_type is (IDLE,INIT_1,INIT_2,PROCESSING,RUN_CIPHER_1,RUN_CIPHER_2,RUN_CIPHER_3,RUN_CIPHER_4,TAG_1,TAG_2);
variable CurrState : state_type := IDLE;
variable firstblock : std_logic;
variable lastblock : std_logic_vector(1 downto 0);
variable afterRunning : std_logic_vector(2 downto 0);
begin
if(clk = '1' and clk'event) then
if rst = '1' then -- synchornous reset
key_updated <= '0';
CurrState := IDLE;
firstblock := '0';
keyreg <= (others => '0');
npubreg <= (others => '0');
AsconMode <= (others => '0'); -- the mode is a register
afterRunning := (others => '0');
else
-- registers above in reset are used
-- Standard values of the control signals are zero
AsconStart <= '0';
bdi_read <= '0';
msg_auth_done <= '0';
bdo_write <= '0';
bdo_size <= "1000";
tag_write <= '0';
npub_read <= '0';
AsconSize <= (others => '0');
FsmLogic: case CurrState is
when IDLE =>
-- if key_needs_update = '1' then -- Key needs updating
-- if key_ready = '1' then
-- key_updated <= '1';
-- keyreg <= key;
-- CurrState := IDLE;
-- else
-- CurrState := IDLE;
-- end if;
if key_needs_update = '1' and key_ready = '1' then -- Key needs updating
key_updated <= '1';
keyreg <= key;
CurrState := IDLE;
elsif bdi_proc = '1' and npub_ready = '1' then -- start of processing
CurrState := INIT_1;
npubreg <= npub;
npub_read <= '1';
AsconMode <= "0010"; -- Mode: initialization
AsconStart <= '1';
else
CurrState := IDLE;
end if;
when INIT_1 =>
if AsconBusy = '1' then
CurrState := INIT_2; -- to INIT_2
else
AsconStart <= '1';
CurrState := INIT_1; -- to INIT_1
end if;
when INIT_2 =>
if AsconBusy = '0' then
CurrState := PROCESSING; -- to PROCESSING
firstblock := '1';
lastblock := "00";
else
CurrState := INIT_2; -- to INIT_2
end if;
-- EVEN SIMPLIFY THIS AFTER YOU SEE IF WORKS
when PROCESSING =>
if lastblock(1) = '1' then -- Generate the Tag
AsconMode <= "0001";
AsconStart <= '1';
CurrState := TAG_1;
elsif bdi_ready = '1' then
if firstblock = '1' and bdi_ad = '0' then -- No associative data (and return in function)
-- SEP_CONST
AsconMode <= "0011";
AsconStart <= '1';
CurrState := PROCESSING;
elsif bdi_ad = '1' then
if bdi_eot = '0' then
-- AD_PROCESS
AsconMode <= "0000";
AsconStart <= '1';
afterRunning := "000";
CurrState := RUN_CIPHER_1;
elsif bdi_eoi = '0' then
if bdi_size = "000" then
-- AD_PROCESS + case2 + SEP_CONST
AsconMode <= "0000";
AsconStart <= '1';
afterRunning := "001";
CurrState := RUN_CIPHER_1;
else
-- AD_PROCESS + SEP_CONST
AsconMode <= "0000";
AsconStart <= '1';
afterRunning := "010";
CurrState := RUN_CIPHER_1;
end if;
else
if bdi_size = "000" then
-- AD_PROCESS + case2 + SEP_CONST + case1
AsconMode <= "0000";
AsconStart <= '1';
afterRunning := "101";
CurrState := RUN_CIPHER_1;
else
-- AD_PROCESS + SEP_CONST + case1
AsconMode <= "0000";
AsconStart <= '1';
afterRunning := "110";
CurrState := RUN_CIPHER_1;
end if;
end if;
else
if bdi_decrypt = '0' then
if bdi_eot = '0' then
-- ENCRYPT
AsconMode <= "0110";
AsconStart <= '1';
afterRunning := "011";
CurrState := RUN_CIPHER_1;
elsif bdi_size = "000" then
-- ENCRYPT + case1
AsconMode <= "0110";
AsconStart <= '1';
afterRunning := "100";
CurrState := RUN_CIPHER_1;
else
-- LAST_BLOCK_ENCRYPT
bdi_read <= '1';
AsconMode <= "0111";
AsconStart <= '1';
afterRunning := "011";
CurrState := RUN_CIPHER_4;
end if;
else
if bdi_eot = '0' then
-- DECRYPT
AsconMode <= "0100";
AsconStart <= '1';
afterRunning := "011";
CurrState := RUN_CIPHER_1;
elsif bdi_size = "000" then
-- DECRYPT + case1
AsconMode <= "0100";
AsconStart <= '1';
afterRunning := "100";
CurrState := RUN_CIPHER_1;
else
-- LAST_BLOCK_DECRYPT
bdi_read <= '1';
AsconMode <= "0101";
AsconStart <= '1';
AsconSize <= bdi_size;
afterRunning := "011";
CurrState := RUN_CIPHER_4;
end if;
end if;
end if;
-- check if tag after (eoi, with special case when no associative data:
-- This is needed, because if no associative data, it will do it's thing and then still the message block is
-- left to be processed
if firstblock = '1' and bdi_ad = '0' then -- lastblock will be set next return in the function
lastblock := "00";
elsif bdi_eoi = '1' and bdi_decrypt = '0' then -- the one after is tag encryption
lastblock := "10";
elsif bdi_eoi = '1' then -- the one after is tag decryption
lastblock := "11";
end if;
-- not firstblock anymore :
firstblock := '0';
end if;
when RUN_CIPHER_1 =>
if AsconBusy = '1' then
CurrState := RUN_CIPHER_2;
bdi_read <= '1';
else
AsconStart <= '1';
CurrState := RUN_CIPHER_1;
end if;
when RUN_CIPHER_3 =>
if AsconBusy = '1' then
CurrState := RUN_CIPHER_2;
else
AsconStart <= '1';
CurrState := RUN_CIPHER_3;
end if;
when RUN_CIPHER_4 =>
if AsconBusy = '1' then
CurrState := RUN_CIPHER_2;
else
CurrState := RUN_CIPHER_4;
end if;
when RUN_CIPHER_2 =>
if AsconBusy = '0' then
-- logic here:
-- a simple variable is used for the cases where after the cipher something special has to be done:
-- activating authregister after associative data = 1
-- resetting of blocknumber after last associative data = 2 (so also do 1's job)
-- giving of output after encryption/decryption = 3 for encryption, 4 for decryption
-- activating checksum after decription of message = 4
-- special giving of output after padded encryption/decryption = 5 and 6 (determines output_sel), also wait with bdi_read
AfterRunLogic: case afterRunning is
when "000" => -- return to IDLE
CurrState := PROCESSING;
when "001" => -- case2 and sep_cont after
AsconMode <= "1001";
AsconStart <= '1';
CurrState := RUN_CIPHER_3;
afterRunning := "010";
when "010" => -- SEPCONSTANT and return to IDLE
AsconMode <= "0011";
AsconStart <= '1';
CurrState := PROCESSING;
when "011" => -- GIVE OUTPUT and return to IDLE
if bdo_ready = '1' then
bdo_write <= '1';
CurrState := PROCESSING;
else
CurrState := RUN_CIPHER_2;
end if;
when "100" => -- GIVE OUTPUT & case1 and return to IDLE
if bdo_ready = '1' then
bdo_write <= '1';
CurrState := PROCESSING;
AsconMode <= "1000";
AsconStart <= '1';
else
CurrState := RUN_CIPHER_2;
end if;
when "101" => -- case2 and case1 and sep_cont after
AsconMode <= "1001";
AsconStart <= '1';
CurrState := RUN_CIPHER_3;
afterRunning := "110";
when "110" => -- case1 and sep_cont after
AsconMode <= "1000";
AsconStart <= '1';
CurrState := RUN_CIPHER_2;
afterRunning := "010";
when others =>
end case AfterRunLogic;
else
CurrState := RUN_CIPHER_2;
end if;
when TAG_1 =>
if AsconBusy = '1' then
CurrState := TAG_2;
else
AsconStart <= '1';
CurrState := TAG_1;
end if;
when TAG_2 =>
if AsconBusy = '0' and lastblock(0) = '0' then -- Generate Tag
if tag_ready = '1' then
tag_write <= '1';
key_updated <= '0';
CurrState := IDLE;
else
CurrState := TAG_2;
end if;
elsif AsconBusy = '0' then -- Compare Tag
if exp_tag_ready = '1' then
msg_auth_done <= '1';
key_updated <= '0';
CurrState := IDLE;
else
CurrState := TAG_2;
end if;
else
CurrState := TAG_2;
end if;
when others =>
end case FsmLogic;
end if;
end if;
end process fsm;
end architecture structure;
| gpl-3.0 | 5619649e7d8e927f4f689eca3860147a | 0.519461 | 3.387741 | false | false | false | false |
impedimentToProgress/UCI-BlueChip | AttackFiles/Attacks/privEsc/lib/techmap/unisim/tap_unisim.vhd | 1 | 10,167 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: tap_xilinx
-- File: tap_xilinx.vhd
-- Author: Edvin Catovic - Gaisler Research
-- Description: Xilinx TAP controllers wrappers
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
-- pragma translate_off
library unisim;
use unisim.BSCAN_VIRTEX;
-- pragma translate_on
entity virtex_tap is
port (
tapi_tdo1 : in std_ulogic;
tapi_tdo2 : in std_ulogic;
tapo_tck : out std_ulogic;
tapo_tdi : out std_ulogic;
tapo_rst : out std_ulogic;
tapo_capt : out std_ulogic;
tapo_shft : out std_ulogic;
tapo_upd : out std_ulogic;
tapo_xsel1 : out std_ulogic;
tapo_xsel2 : out std_ulogic
);
end;
architecture rtl of virtex_tap is
component BSCAN_VIRTEX
port (CAPTURE : out STD_ULOGIC;
DRCK1 : out STD_ULOGIC;
DRCK2 : out STD_ULOGIC;
RESET : out STD_ULOGIC;
SEL1 : out STD_ULOGIC;
SEL2 : out STD_ULOGIC;
SHIFT : out STD_ULOGIC;
TDI : out STD_ULOGIC;
UPDATE : out STD_ULOGIC;
TDO1 : in STD_ULOGIC;
TDO2 : in STD_ULOGIC);
end component;
signal drck1, drck2, sel1, sel2 : std_ulogic;
attribute dont_touch : boolean;
attribute dont_touch of u0 : label is true;
begin
u0 : BSCAN_VIRTEX
port map (
DRCK1 => drck1,
DRCK2 => drck2,
RESET => tapo_rst,
SEL1 => sel1,
SEL2 => sel2,
SHIFT => tapo_shft,
TDI => tapo_tdi,
UPDATE => tapo_upd,
TDO1 => tapi_tdo1,
TDO2 => tapi_tdo2);
tapo_tck <= drck1 when sel1 = '1' else drck2;
tapo_xsel1 <= sel1; tapo_xsel2 <= sel2; tapo_capt <= '0';
end;
library ieee;
use ieee.std_logic_1164.all;
-- pragma translate_off
library unisim;
use unisim.BSCAN_VIRTEX2;
-- pragma translate_on
entity virtex2_tap is
port (
tapi_tdo1 : in std_ulogic;
tapi_tdo2 : in std_ulogic;
tapo_tck : out std_ulogic;
tapo_tdi : out std_ulogic;
tapo_rst : out std_ulogic;
tapo_capt : out std_ulogic;
tapo_shft : out std_ulogic;
tapo_upd : out std_ulogic;
tapo_xsel1 : out std_ulogic;
tapo_xsel2 : out std_ulogic
);
end;
architecture rtl of virtex2_tap is
component BSCAN_VIRTEX2
port (CAPTURE : out STD_ULOGIC;
DRCK1 : out STD_ULOGIC;
DRCK2 : out STD_ULOGIC;
RESET : out STD_ULOGIC;
SEL1 : out STD_ULOGIC;
SEL2 : out STD_ULOGIC;
SHIFT : out STD_ULOGIC;
TDI : out STD_ULOGIC;
UPDATE : out STD_ULOGIC;
TDO1 : in STD_ULOGIC;
TDO2 : in STD_ULOGIC);
end component;
signal drck1, drck2, sel1, sel2 : std_ulogic;
attribute dont_touch : boolean;
attribute dont_touch of u0 : label is true;
begin
u0 : BSCAN_VIRTEX2
port map (CAPTURE => tapo_capt,
DRCK1 => drck1,
DRCK2 => drck2,
RESET => tapo_rst,
SEL1 => sel1,
SEL2 => sel2,
SHIFT => tapo_shft,
TDI => tapo_tdi,
UPDATE => tapo_upd,
TDO1 => tapi_tdo1,
TDO2 => tapi_tdo2);
tapo_tck <= drck1 when sel1 = '1' else drck2;
tapo_xsel1 <= sel1; tapo_xsel2 <= sel2;
end;
library ieee;
use ieee.std_logic_1164.all;
-- pragma translate_off
library unisim;
use unisim.BSCAN_SPARTAN3;
-- pragma translate_on
entity spartan3_tap is
port (
tapi_tdo1 : in std_ulogic;
tapi_tdo2 : in std_ulogic;
tapo_tck : out std_ulogic;
tapo_tdi : out std_ulogic;
tapo_rst : out std_ulogic;
tapo_capt : out std_ulogic;
tapo_shft : out std_ulogic;
tapo_upd : out std_ulogic;
tapo_xsel1 : out std_ulogic;
tapo_xsel2 : out std_ulogic
);
end;
architecture rtl of spartan3_tap is
component BSCAN_SPARTAN3
port (CAPTURE : out STD_ULOGIC;
DRCK1 : out STD_ULOGIC;
DRCK2 : out STD_ULOGIC;
RESET : out STD_ULOGIC;
SEL1 : out STD_ULOGIC;
SEL2 : out STD_ULOGIC;
SHIFT : out STD_ULOGIC;
TDI : out STD_ULOGIC;
UPDATE : out STD_ULOGIC;
TDO1 : in STD_ULOGIC;
TDO2 : in STD_ULOGIC);
end component;
signal drck1, drck2, sel1, sel2 : std_ulogic;
attribute dont_touch : boolean;
attribute dont_touch of u0 : label is true;
begin
u0 : BSCAN_SPARTAN3
port map (CAPTURE => tapo_capt,
DRCK1 => drck1,
DRCK2 => drck2,
RESET => tapo_rst,
SEL1 => sel1,
SEL2 => sel2,
SHIFT => tapo_shft,
TDI => tapo_tdi,
UPDATE => tapo_upd,
TDO1 => tapi_tdo1,
TDO2 => tapi_tdo2);
tapo_tck <= drck1 when sel1 = '1' else drck2;
tapo_xsel1 <= sel1; tapo_xsel2 <= sel2;
end;
library ieee;
use ieee.std_logic_1164.all;
-- pragma translate_off
library unisim;
use unisim.BSCAN_VIRTEX4;
-- pragma translate_on
entity virtex4_tap is
port (
tapi_tdo1 : in std_ulogic;
tapi_tdo2 : in std_ulogic;
tapo_tck : out std_ulogic;
tapo_tdi : out std_ulogic;
tapo_rst : out std_ulogic;
tapo_capt : out std_ulogic;
tapo_shft : out std_ulogic;
tapo_upd : out std_ulogic;
tapo_xsel1 : out std_ulogic;
tapo_xsel2 : out std_ulogic
);
end;
architecture rtl of virtex4_tap is
component BSCAN_VIRTEX4 generic ( JTAG_CHAIN : integer := 1);
port ( CAPTURE : out std_ulogic;
DRCK : out std_ulogic;
RESET : out std_ulogic;
SEL : out std_ulogic;
SHIFT : out std_ulogic;
TDI : out std_ulogic;
UPDATE : out std_ulogic;
TDO : in std_ulogic);
end component;
signal drck1, drck2, sel1, sel2 : std_ulogic;
signal capt1, capt2, rst1, rst2 : std_ulogic;
signal shift1, shift2, tdi1, tdi2 : std_ulogic;
signal update1, update2 : std_ulogic;
attribute dont_touch : boolean;
attribute dont_touch of u0 : label is true;
attribute dont_touch of u1 : label is true;
begin
u0 : BSCAN_VIRTEX4
generic map (JTAG_CHAIN => 1)
port map (
CAPTURE => capt1,
DRCK => drck1,
RESET => rst1,
SEL => sel1,
SHIFT => shift1,
TDI => tdi1,
UPDATE => update1,
TDO => tapi_tdo1
);
u1 : BSCAN_VIRTEX4
generic map (JTAG_CHAIN => 2)
port map (
CAPTURE => capt2,
DRCK => drck2,
RESET => rst2,
SEL => sel2,
SHIFT => shift2,
TDI => tdi2,
UPDATE => update2,
TDO => tapi_tdo2
);
tapo_capt <= capt1 when sel1 = '1' else capt2;
tapo_tck <= drck1 when sel1 = '1' else drck2;
tapo_rst <= rst1 when sel1 = '1' else rst2;
tapo_shft <= shift1 when sel1 = '1' else shift2;
tapo_tdi <= tdi1 when sel1 = '1' else tdi2;
tapo_upd <= update1 when sel1 ='1' else update2;
tapo_xsel1 <= sel1; tapo_xsel2 <= sel2;
end;
library ieee;
use ieee.std_logic_1164.all;
-- pragma translate_off
library unisim;
use unisim.BSCAN_VIRTEX5;
-- pragma translate_on
entity virtex5_tap is
port (
tapi_tdo1 : in std_ulogic;
tapi_tdo2 : in std_ulogic;
tapo_tck : out std_ulogic;
tapo_tdi : out std_ulogic;
tapo_rst : out std_ulogic;
tapo_capt : out std_ulogic;
tapo_shft : out std_ulogic;
tapo_upd : out std_ulogic;
tapo_xsel1 : out std_ulogic;
tapo_xsel2 : out std_ulogic
);
end;
architecture rtl of virtex5_tap is
component BSCAN_VIRTEX5 generic ( JTAG_CHAIN : integer := 1);
port ( CAPTURE : out std_ulogic;
DRCK : out std_ulogic;
RESET : out std_ulogic;
SEL : out std_ulogic;
SHIFT : out std_ulogic;
TDI : out std_ulogic;
UPDATE : out std_ulogic;
TDO : in std_ulogic);
end component;
signal drck1, drck2, sel1, sel2 : std_ulogic;
signal capt1, capt2, rst1, rst2 : std_ulogic;
signal shift1, shift2, tdi1, tdi2 : std_ulogic;
signal update1, update2 : std_ulogic;
attribute dont_touch : boolean;
attribute dont_touch of u0 : label is true;
attribute dont_touch of u1 : label is true;
begin
u0 : BSCAN_VIRTEX5
generic map (JTAG_CHAIN => 1)
port map (
CAPTURE => capt1,
DRCK => drck1,
RESET => rst1,
SEL => sel1,
SHIFT => shift1,
TDI => tdi1,
UPDATE => update1,
TDO => tapi_tdo1
);
u1 : BSCAN_VIRTEX5
generic map (JTAG_CHAIN => 2)
port map (
CAPTURE => capt2,
DRCK => drck2,
RESET => rst2,
SEL => sel2,
SHIFT => shift2,
TDI => tdi2,
UPDATE => update2,
TDO => tapi_tdo2
);
tapo_capt <= capt1 when sel1 = '1' else capt2;
tapo_tck <= drck1 when sel1 = '1' else drck2;
tapo_rst <= rst1 when sel1 = '1' else rst2;
tapo_shft <= shift1 when sel1 = '1' else shift2;
tapo_tdi <= tdi1 when sel1 = '1' else tdi2;
tapo_upd <= update1 when sel1 ='1' else update2;
tapo_xsel1 <= sel1; tapo_xsel2 <= sel2;
end;
| mit | 9ea6a526c0f435dd2d86a5c90bc7387f | 0.566342 | 3.48543 | false | false | false | false |
impedimentToProgress/UCI-BlueChip | AttackFiles/Attacks/privEsc/lib/grlib/amba/devices.vhd | 2 | 28,860 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: devices
-- File: devices.vhd
-- Author: Jiri Gaisler, Gaisler Research
-- Description: Vendor and devices id's for amba plug&play
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
-- pragma translate_off
use std.textio.all;
-- pragma translate_on
package devices is
-- Vendor codes
constant VENDOR_GAISLER : amba_vendor_type := 16#01#;
constant VENDOR_PENDER : amba_vendor_type := 16#02#;
constant VENDOR_ESA : amba_vendor_type := 16#04#;
constant VENDOR_ASTRIUM : amba_vendor_type := 16#06#;
constant VENDOR_OPENCHIP : amba_vendor_type := 16#07#;
constant VENDOR_OPENCORES : amba_vendor_type := 16#08#;
constant VENDOR_CONTRIB : amba_vendor_type := 16#09#;
constant VENDOR_EONIC : amba_vendor_type := 16#0B#;
constant VENDOR_RADIONOR : amba_vendor_type := 16#0F#;
constant VENDOR_GLEICHMANN : amba_vendor_type := 16#10#;
constant VENDOR_MENTA : amba_vendor_type := 16#11#;
constant VENDOR_SUN : amba_vendor_type := 16#13#;
constant VENDOR_MOVIDIA : amba_vendor_type := 16#14#;
constant VENDOR_ORBITA : amba_vendor_type := 16#17#;
constant VENDOR_SYNOPSYS : amba_vendor_type := 16#21#;
constant VENDOR_CAL : amba_vendor_type := 16#CA#;
constant VENDOR_EMBEDDIT : amba_vendor_type := 16#EA#;
constant VENDOR_CETON : amba_vendor_type := 16#CB#;
-- Gaisler Research device id's
constant GAISLER_LEON2DSU : amba_device_type := 16#002#;
constant GAISLER_LEON3 : amba_device_type := 16#003#;
constant GAISLER_LEON3DSU : amba_device_type := 16#004#;
constant GAISLER_ETHAHB : amba_device_type := 16#005#;
constant GAISLER_APBMST : amba_device_type := 16#006#;
constant GAISLER_AHBUART : amba_device_type := 16#007#;
constant GAISLER_SRCTRL : amba_device_type := 16#008#;
constant GAISLER_SDCTRL : amba_device_type := 16#009#;
constant GAISLER_SSRCTRL : amba_device_type := 16#00A#;
constant GAISLER_APBUART : amba_device_type := 16#00C#;
constant GAISLER_IRQMP : amba_device_type := 16#00D#;
constant GAISLER_AHBRAM : amba_device_type := 16#00E#;
constant GAISLER_GPTIMER : amba_device_type := 16#011#;
constant GAISLER_PCITRG : amba_device_type := 16#012#;
constant GAISLER_PCISBRG : amba_device_type := 16#013#;
constant GAISLER_PCIFBRG : amba_device_type := 16#014#;
constant GAISLER_PCITRACE : amba_device_type := 16#015#;
constant GAISLER_DMACTRL : amba_device_type := 16#016#;
constant GAISLER_AHBTRACE : amba_device_type := 16#017#;
constant GAISLER_DSUCTRL : amba_device_type := 16#018#;
constant GAISLER_CANAHB : amba_device_type := 16#019#;
constant GAISLER_GPIO : amba_device_type := 16#01A#;
constant GAISLER_AHBROM : amba_device_type := 16#01B#;
constant GAISLER_AHBJTAG : amba_device_type := 16#01C#;
constant GAISLER_ETHMAC : amba_device_type := 16#01D#;
constant GAISLER_SWNODE : amba_device_type := 16#01E#;
constant GAISLER_SPW : amba_device_type := 16#01F#;
constant GAISLER_AHB2AHB : amba_device_type := 16#020#;
constant GAISLER_USBCTRL : amba_device_type := 16#021#;
constant GAISLER_USBDCL : amba_device_type := 16#022#;
constant GAISLER_DDRMP : amba_device_type := 16#023#;
constant GAISLER_ATACTRL : amba_device_type := 16#024#;
constant GAISLER_DDRSP : amba_device_type := 16#025#;
constant GAISLER_EHCI : amba_device_type := 16#026#;
constant GAISLER_UHCI : amba_device_type := 16#027#;
constant GAISLER_I2CMST : amba_device_type := 16#028#;
constant GAISLER_SPW2 : amba_device_type := 16#029#;
constant GAISLER_AHBDMA : amba_device_type := 16#02A#;
constant GAISLER_NUHOSP3 : amba_device_type := 16#02B#;
constant GAISLER_CLKGATE : amba_device_type := 16#02C#;
constant GAISLER_SPICTRL : amba_device_type := 16#02D#;
constant GAISLER_DDR2SP : amba_device_type := 16#02E#;
constant GAISLER_SLINK : amba_device_type := 16#02F#;
constant GAISLER_GRTM : amba_device_type := 16#030#;
constant GAISLER_GRTC : amba_device_type := 16#031#;
constant GAISLER_GRPW : amba_device_type := 16#032#;
constant GAISLER_GRCTM : amba_device_type := 16#033#;
constant GAISLER_GRHCAN : amba_device_type := 16#034#;
constant GAISLER_GRFIFO : amba_device_type := 16#035#;
constant GAISLER_GRADCDAC : amba_device_type := 16#036#;
constant GAISLER_GRPULSE : amba_device_type := 16#037#;
constant GAISLER_GRTIMER : amba_device_type := 16#038#;
constant GAISLER_AHB2PP : amba_device_type := 16#039#;
constant GAISLER_GRVERSION : amba_device_type := 16#03A#;
constant GAISLER_APB2PW : amba_device_type := 16#03B#;
constant GAISLER_PW2APB : amba_device_type := 16#03C#;
constant GAISLER_GRCAN : amba_device_type := 16#03D#;
constant GAISLER_I2CSLV : amba_device_type := 16#03E#;
constant GAISLER_U16550 : amba_device_type := 16#03F#;
constant GAISLER_AHBMST_EM : amba_device_type := 16#040#;
constant GAISLER_AHBSLV_EM : amba_device_type := 16#041#;
constant GAISLER_GRTESTMOD : amba_device_type := 16#042#;
constant GAISLER_ASCS : amba_device_type := 16#043#;
constant GAISLER_IPMVBCTRL : amba_device_type := 16#044#;
constant GAISLER_SPIMCTRL : amba_device_type := 16#045#;
constant GAISLER_FTAHBRAM : amba_device_type := 16#050#;
constant GAISLER_FTSRCTRL : amba_device_type := 16#051#;
constant GAISLER_AHBSTAT : amba_device_type := 16#052#;
constant GAISLER_LEON3FT : amba_device_type := 16#053#;
constant GAISLER_FTMCTRL : amba_device_type := 16#054#;
constant GAISLER_FTSDCTRL : amba_device_type := 16#055#;
constant GAISLER_FTSRCTRL8 : amba_device_type := 16#056#;
constant GAISLER_APBPS2 : amba_device_type := 16#060#;
constant GAISLER_VGACTRL : amba_device_type := 16#061#;
constant GAISLER_LOGAN : amba_device_type := 16#062#;
constant GAISLER_SVGACTRL : amba_device_type := 16#063#;
constant GAISLER_T1AHB : amba_device_type := 16#064#;
constant GAISLER_B1553BC : amba_device_type := 16#070#;
constant GAISLER_B1553RT : amba_device_type := 16#071#;
constant GAISLER_B1553BRM : amba_device_type := 16#072#;
constant GAISLER_SATCAN : amba_device_type := 16#080#;
constant GAISLER_CANMUX : amba_device_type := 16#081#;
constant GAISLER_GRTMRX : amba_device_type := 16#082#;
constant GAISLER_GRTCTX : amba_device_type := 16#083#;
constant GAISLER_AES : amba_device_type := 16#073#;
constant GAISLER_ECC : amba_device_type := 16#074#;
constant GAISLER_PCIF : amba_device_type := 16#075#;
constant GAISLER_CLKMOD : amba_device_type := 16#076#;
constant GAISLER_HAPSTRAK : amba_device_type := 16#077#;
constant GAISLER_TEST_1X2 : amba_device_type := 16#078#;
constant GAISLER_WILD2AHB : amba_device_type := 16#079#;
constant GAISLER_BIO1 : amba_device_type := 16#07A#;
-- Sun Microsystems
constant SUN_T1 : amba_device_type := 16#001#;
constant SUN_S1 : amba_device_type := 16#011#;
-- Caltech
constant CAL_DDRCTRL : amba_device_type := 16#188#;
-- European Space Agency device id's
constant ESA_LEON2 : amba_device_type := 16#002#;
constant ESA_LEON2APB : amba_device_type := 16#003#;
constant ESA_IRQ : amba_device_type := 16#005#;
constant ESA_TIMER : amba_device_type := 16#006#;
constant ESA_UART : amba_device_type := 16#007#;
constant ESA_CFG : amba_device_type := 16#008#;
constant ESA_IO : amba_device_type := 16#009#;
constant ESA_MCTRL : amba_device_type := 16#00F#;
constant ESA_PCIARB : amba_device_type := 16#010#;
constant ESA_HURRICANE : amba_device_type := 16#011#;
constant ESA_SPW_RMAP : amba_device_type := 16#012#;
constant ESA_AHBUART : amba_device_type := 16#013#;
constant ESA_SPWA : amba_device_type := 16#014#;
constant ESA_BOSCHCAN : amba_device_type := 16#015#;
constant ESA_IRQ2 : amba_device_type := 16#016#;
constant ESA_AHBSTAT : amba_device_type := 16#017#;
constant ESA_WPROT : amba_device_type := 16#018#;
constant ESA_WPROT2 : amba_device_type := 16#019#;
constant ESA_PDEC3AMBA : amba_device_type := 16#020#;
constant ESA_PTME3AMBA : amba_device_type := 16#021#;
-- OpenChip ID's
constant OPENCHIP_APBGPIO : amba_device_type := 16#001#;
constant OPENCHIP_APBI2C : amba_device_type := 16#002#;
constant OPENCHIP_APBSPI : amba_device_type := 16#003#;
constant OPENCHIP_APBCHARLCD : amba_device_type := 16#004#;
constant OPENCHIP_APBPWM : amba_device_type := 16#005#;
constant OPENCHIP_APBPS2 : amba_device_type := 16#006#;
constant OPENCHIP_APBMMCSD : amba_device_type := 16#007#;
constant OPENCHIP_APBNAND : amba_device_type := 16#008#;
constant OPENCHIP_APBLPC : amba_device_type := 16#009#;
constant OPENCHIP_APBCF : amba_device_type := 16#00A#;
constant OPENCHIP_APBSYSACE : amba_device_type := 16#00B#;
constant OPENCHIP_APB1WIRE : amba_device_type := 16#00C#;
constant OPENCHIP_APBJTAG : amba_device_type := 16#00D#;
constant OPENCHIP_APBSUI : amba_device_type := 16#00E#;
-- Gleichmann's device id's
constant GLEICHMANN_CUSTOM : amba_device_type := 16#001#;
constant GLEICHMANN_GEOLCD01 : amba_device_type := 16#002#;
constant GLEICHMANN_DAC : amba_device_type := 16#003#;
constant GLEICHMANN_HPI : amba_device_type := 16#004#;
constant GLEICHMANN_SPI : amba_device_type := 16#005#;
constant GLEICHMANN_HIFC : amba_device_type := 16#006#;
constant GLEICHMANN_ADCDAC : amba_device_type := 16#007#;
constant GLEICHMANN_SPIOC : amba_device_type := 16#008#;
-- Orbita device id's
constant ORBITA_1553B : amba_device_type := 16#001#;
constant ORBITA_429 : amba_device_type := 16#002#;
constant ORBITA_SPI : amba_device_type := 16#003#;
constant ORBITA_I2C : amba_device_type := 16#004#;
constant ORBITA_SMARTCARD : amba_device_type := 16#064#;
constant ORBITA_SDCARD : amba_device_type := 16#065#;
constant ORBITA_UART16550 : amba_device_type := 16#066#;
constant ORBITA_CRYPTO : amba_device_type := 16#067#;
constant ORBITA_SYSIF : amba_device_type := 16#068#;
constant ORBITA_PIO : amba_device_type := 16#069#;
constant ORBITA_RTC : amba_device_type := 16#0C8#;
constant ORBITA_COLORLCD : amba_device_type := 16#12C#;
constant ORBITA_PCI : amba_device_type := 16#190#;
constant ORBITA_DSP : amba_device_type := 16#1F4#;
constant ORBITA_USBHOST : amba_device_type := 16#258#;
constant ORBITA_USBDEV : amba_device_type := 16#2BC#;
-- Contribution library ID's
constant CONTRIB_CORE1 : amba_device_type := 16#001#;
constant CONTRIB_CORE2 : amba_device_type := 16#002#;
-- grlib system device id's
subtype system_device_type is integer range 0 to 16#ffff#;
constant LEON3_RTAX_CID2 : system_device_type := 16#0202#;
constant LEON3_RTAX_CID5 : system_device_type := 16#0205#;
constant LEON3_IHP25RH1 : system_device_type := 16#0251#;
constant XILINX_ML401 : system_device_type := 16#0401#;
constant XILINX_ML501 : system_device_type := 16#0501#;
constant XILINX_ML505 : system_device_type := 16#0505#;
constant ORBITA_1 : system_device_type := 16#0631#;
constant AEROFLEX_UT699 : system_device_type := 16#0699#;
constant GAISLER_DARE1 : system_device_type := 16#0704#;
constant GAISLER_GR712RC : system_device_type := 16#0712#;
-- pragma translate_off
constant GAISLER_DESC : vendor_description := "Gaisler Research ";
constant gaisler_device_table : device_table_type := (
GAISLER_LEON2DSU => "Leon2 Debug Support Unit ",
GAISLER_LEON3 => "Leon3 SPARC V8 Processor ",
GAISLER_LEON3DSU => "Leon3 Debug Support Unit ",
GAISLER_ETHAHB => "OC ethernet AHB interface ",
GAISLER_AHBRAM => "Generic AHB SRAM module ",
GAISLER_APBMST => "AHB/APB Bridge ",
GAISLER_AHBUART => "AHB Debug UART ",
GAISLER_SRCTRL => "Simple SRAM Controller ",
GAISLER_SDCTRL => "PC133 SDRAM Controller ",
GAISLER_SSRCTRL => "Synchronous SRAM Controller ",
GAISLER_APBUART => "Generic UART ",
GAISLER_IRQMP => "Multi-processor Interrupt Ctrl.",
GAISLER_GPTIMER => "Modular Timer Unit ",
GAISLER_PCITRG => "Simple 32-bit PCI Target ",
GAISLER_PCISBRG => "Simple 32-bit PCI Bridge ",
GAISLER_PCIFBRG => "Fast 32-bit PCI Bridge ",
GAISLER_PCITRACE => "32-bit PCI Trace Buffer ",
GAISLER_DMACTRL => "AMBA DMA controller ",
GAISLER_AHBTRACE => "AMBA Trace Buffer ",
GAISLER_DSUCTRL => "DSU/ETH controller ",
GAISLER_GRTM => "CCSDS Telemetry Encoder ",
GAISLER_GRTC => "CCSDS Telecommand Decoder ",
GAISLER_GRPW => "PacketWire to AMBA AHB I/F ",
GAISLER_GRCTM => "CCSDS Time Manager ",
GAISLER_GRHCAN => "ESA HurriCANe CAN with DMA ",
GAISLER_GRFIFO => "FIFO Controller ",
GAISLER_GRADCDAC => "ADC / DAC Interface ",
GAISLER_GRPULSE => "General Purpose I/O with Pulses",
GAISLER_GRTIMER => "Timer Unit with Latches ",
GAISLER_AHB2PP => "AMBA AHB to Packet Parallel I/F",
GAISLER_GRVERSION => "Version and Revision Register ",
GAISLER_APB2PW => "PacketWire Transmit Interface ",
GAISLER_PW2APB => "PacketWire Receive Interface ",
GAISLER_GRCAN => "CAN Controller with DMA ",
GAISLER_AHBMST_EM => "AMBA Master Emulator ",
GAISLER_AHBSLV_EM => "AMBA Slave Emulator ",
GAISLER_CANAHB => "OC CAN AHB interface ",
GAISLER_GPIO => "General Purpose I/O port ",
GAISLER_AHBROM => "Generic AHB ROM ",
GAISLER_AHB2AHB => "AHB-to-AHB Bridge ",
GAISLER_NUHOSP3 => "Nuhorizons Spartan3 IO I/F ",
GAISLER_CLKGATE => "Clock gating unit ",
GAISLER_FTAHBRAM => "Generic FT AHB SRAM module ",
GAISLER_FTSRCTRL => "Simple FT SRAM Controller ",
GAISLER_LEON3FT => "Leon3-FT SPARC V8 Processor ",
GAISLER_FTMCTRL => "Memory controller with EDAC ",
GAISLER_FTSDCTRL => "FT PC133 SDRAM Controller ",
GAISLER_FTSRCTRL8 => "FT 8-bit SRAM/16-bit IO Ctrl ",
GAISLER_AHBSTAT => "AHB Status Register ",
GAISLER_AHBJTAG => "JTAG Debug Link ",
GAISLER_ETHMAC => "GR Ethernet MAC ",
GAISLER_SWNODE => "SpaceWire Node Interface ",
GAISLER_SPW => "SpaceWire Serial Link ",
GAISLER_VGACTRL => "VGA controller ",
GAISLER_APBPS2 => "PS2 interface ",
GAISLER_LOGAN => "On chip Logic Analyzer ",
GAISLER_SVGACTRL => "SVGA frame buffer ",
GAISLER_T1AHB => "Niagara T1 PCX/AHB bridge ",
GAISLER_B1553BC => "AMBA Wrapper for Core1553BBC ",
GAISLER_B1553RT => "AMBA Wrapper for Core1553BRT ",
GAISLER_B1553BRM => "AMBA Wrapper for Core1553BRM ",
GAISLER_SATCAN => "SatCAN controller ",
GAISLER_CANMUX => "CAN Bus multiplexer ",
GAISLER_GRTMRX => "CCSDS Telemetry Receiver ",
GAISLER_GRTCTX => "CCSDS Telecommand Transmitter ",
GAISLER_AES => "Advanced Encryption Standard ",
GAISLER_ECC => "Elliptic Curve Cryptography ",
GAISLER_PCIF => "AMBA Wrapper for CorePCIF ",
GAISLER_USBCTRL => "USB 2.0 Controller ",
GAISLER_USBDCL => "USB Debug Communication Link ",
GAISLER_DDRMP => "Multi-port DDR controller ",
GAISLER_ATACTRL => "ATA controller ",
GAISLER_DDRSP => "Single-port DDR266 controller ",
GAISLER_EHCI => "USB Enhanced Host Controller ",
GAISLER_UHCI => "USB Universal Host Controller ",
GAISLER_I2CMST => "AMBA Wrapper for OC I2C-master ",
GAISLER_I2CSLV => "I2C Slave ",
GAISLER_U16550 => "Simple 16550 UART ",
GAISLER_SPICTRL => "SPI Controller ",
GAISLER_DDR2SP => "Single-port DDR2 controller ",
GAISLER_GRTESTMOD => "Test report module ",
GAISLER_CLKMOD => "CPU Clock Switching Ctrl module",
GAISLER_SLINK => "SLINK Master ",
GAISLER_HAPSTRAK => "HAPS HapsTrak I/O Port ",
GAISLER_TEST_1X2 => "HAPS TEST_1x2 interface ",
GAISLER_WILD2AHB => "WildCard CardBus interface ",
GAISLER_BIO1 => "Basic I/O board BIO1 ",
GAISLER_ASCS => "ASCS Master ",
GAISLER_SPW2 => "GRSPW2 SpaceWire Serial Link ",
GAISLER_IPMVBCTRL => "IPM-bus/MVBC memory controller ",
GAISLER_SPIMCTRL => "SPI Memory Controller ",
others => "Unknown Device ");
constant gaisler_lib : vendor_library_type := (
vendorid => VENDOR_GAISLER,
vendordesc => GAISLER_DESC,
device_table => gaisler_device_table
);
constant ESA_DESC : vendor_description := "European Space Agency ";
constant esa_device_table : device_table_type := (
ESA_LEON2 => "Leon2 SPARC V8 Processor ",
ESA_LEON2APB => "Leon2 Peripheral Bus ",
ESA_IRQ => "Leon2 Interrupt Controller ",
ESA_TIMER => "Leon2 Timer ",
ESA_UART => "Leon2 UART ",
ESA_CFG => "Leon2 Configuration Register ",
ESA_IO => "Leon2 Input/Output ",
ESA_MCTRL => "Leon2 Memory Controller ",
ESA_PCIARB => "PCI Arbiter ",
ESA_HURRICANE => "HurriCANe/HurryAMBA CAN Ctrl ",
ESA_SPW_RMAP => "UoD/Saab SpaceWire/RMAP link ",
ESA_AHBUART => "Leon2 AHB Debug UART ",
ESA_SPWA => "ESA/ASTRIUM SpaceWire link ",
ESA_BOSCHCAN => "SSC/BOSCH CAN Ctrl ",
ESA_IRQ2 => "Leon2 Secondary Irq Controller ",
ESA_AHBSTAT => "Leon2 AHB Status Register ",
ESA_WPROT => "Leon2 Write Protection ",
ESA_WPROT2 => "Leon2 Extended Write Protection",
ESA_PDEC3AMBA => "ESA CCSDS PDEC3AMBA TC Decoder ",
ESA_PTME3AMBA => "ESA CCSDS PTME3AMBA TM Encoder ",
others => "Unknown Device ");
constant esa_lib : vendor_library_type := (
vendorid => VENDOR_ESA,
vendordesc => ESA_DESC,
device_table => esa_device_table
);
constant OPENCHIP_DESC : vendor_description := "OpenChip ";
constant openchip_device_table : device_table_type := (
OPENCHIP_APBGPIO => "APB General Purpose IO ",
OPENCHIP_APBI2C => "APB I2C Interface ",
OPENCHIP_APBSPI => "APB SPI Interface ",
OPENCHIP_APBCHARLCD => "APB Character LCD ",
OPENCHIP_APBPWM => "APB PWM ",
OPENCHIP_APBPS2 => "APB PS/2 Interface ",
OPENCHIP_APBMMCSD => "APB MMC/SD Card Interface ",
OPENCHIP_APBNAND => "APB NAND(SmartMedia) Interface ",
OPENCHIP_APBLPC => "APB LPC Interface ",
OPENCHIP_APBCF => "APB CompactFlash (IDE) ",
OPENCHIP_APBSYSACE => "APB SystemACE Interface ",
OPENCHIP_APB1WIRE => "APB 1-Wire Interface ",
OPENCHIP_APBJTAG => "APB JTAG TAP Master ",
OPENCHIP_APBSUI => "APB Simple User Interface ",
others => "Unknown Device ");
constant openchip_lib : vendor_library_type := (
vendorid => VENDOR_OPENCHIP,
vendordesc => OPENCHIP_DESC,
device_table => openchip_device_table
);
constant GLEICHMANN_DESC : vendor_description := "Gleichmann Electronics ";
constant gleichmann_device_table : device_table_type := (
GLEICHMANN_CUSTOM => "Custom device ",
GLEICHMANN_GEOLCD01 => "GEOLCD01 graphics system ",
GLEICHMANN_DAC => "Sigma delta DAC ",
GLEICHMANN_HPI => "AHB-to-HPI bridge ",
GLEICHMANN_SPI => "SPI master ",
GLEICHMANN_HIFC => "Human interface controller ",
GLEICHMANN_ADCDAC => "Sigma delta ADC/DAC ",
GLEICHMANN_SPIOC => "SPI master for SDCard IF ",
others => "Unknown Device ");
constant gleichmann_lib : vendor_library_type := (
vendorid => VENDOR_GLEICHMANN,
vendordesc => GLEICHMANN_DESC,
device_table => gleichmann_device_table
);
constant CONTRIB_DESC : vendor_description := "Various contributions ";
constant contrib_device_table : device_table_type := (
CONTRIB_CORE1 => "Contributed core 1 ",
CONTRIB_CORE2 => "Contributed core 2 ",
others => "Unknown Device ");
constant contrib_lib : vendor_library_type := (
vendorid => VENDOR_CONTRIB,
vendordesc => CONTRIB_DESC,
device_table => contrib_device_table
);
constant MENTA_DESC : vendor_description := "Menta ";
constant menta_device_table : device_table_type := (
others => "Unknown Device ");
constant menta_lib : vendor_library_type := (
vendorid => VENDOR_MENTA,
vendordesc => MENTA_DESC,
device_table => menta_device_table
);
constant SUN_DESC : vendor_description := "Sun Microsystems ";
constant sun_device_table : device_table_type := (
SUN_T1 => "Niagara T1 SPARC V9 Processor ",
SUN_S1 => "Niagara S1 SPARC V9 Processor ",
others => "Unknown Device ");
constant sun_lib : vendor_library_type := (
vendorid => VENDOR_SUN,
vendordesc => SUN_DESC,
device_table => sun_device_table
);
constant OPENCORES_DESC : vendor_description := "OpenCores ";
constant opencores_device_table : device_table_type := (
others => "Unknown Device ");
constant opencores_lib : vendor_library_type := (
vendorid => VENDOR_OPENCORES,
vendordesc => OPENCORES_DESC,
device_table => opencores_device_table
);
constant CETON_DESC : vendor_description := "Ceton Corporation ";
constant ceton_device_table : device_table_type := (
others => "Unknown Device ");
constant ceton_lib : vendor_library_type := (
vendorid => VENDOR_CETON,
vendordesc => CETON_DESC,
device_table => ceton_device_table
);
constant SYNOPSYS_DESC : vendor_description := "Synopsys Inc. ";
constant synopsys_device_table : device_table_type := (
others => "Unknown Device ");
constant synopsys_lib : vendor_library_type := (
vendorid => VENDOR_SYNOPSYS,
vendordesc => SYNOPSYS_DESC,
device_table => synopsys_device_table
);
constant EMBEDDIT_DESC : vendor_description := "Embedd.it ";
constant embeddit_device_table : device_table_type := (
others => "Unknown Device ");
constant embeddit_lib : vendor_library_type := (
vendorid => VENDOR_EMBEDDIT,
vendordesc => EMBEDDIT_DESC,
device_table => embeddit_device_table
);
constant eonic_device_table : device_table_type := (
others => "Unknown Device ");
constant EONIC_DESC : vendor_description := "Eonic BV ";
constant eonic_lib : vendor_library_type := (
vendorid => VENDOR_EONIC,
vendordesc => EONIC_DESC,
device_table => eonic_device_table
);
constant radionor_device_table : device_table_type := (
others => "Unknown Device ");
constant RADIONOR_DESC : vendor_description := "Radionor Communications ";
constant radionor_lib : vendor_library_type := (
vendorid => VENDOR_RADIONOR,
vendordesc => RADIONOR_DESC,
device_table => radionor_device_table
);
constant orbita_device_table : device_table_type := (
ORBITA_1553B => "MIL-STD-1553B Controller ",
ORBITA_429 => "429 Interface ",
ORBITA_SPI => "SPI Interface ",
ORBITA_I2C => "I2C Interface ",
ORBITA_SMARTCARD => "Smart Card Reader ",
ORBITA_SDCARD => "SD Card Reader ",
ORBITA_UART16550 => "16550 UART ",
ORBITA_CRYPTO => "Crypto Engine ",
ORBITA_SYSIF => "System Interface ",
ORBITA_PIO => "Programmable IO module ",
ORBITA_RTC => "Real-Time Clock ",
ORBITA_COLORLCD => "Color LCD Controller ",
ORBITA_PCI => "PCI Module ",
ORBITA_DSP => "DPS Co-Processor ",
ORBITA_USBHOST => "USB Host ",
ORBITA_USBDEV => "USB Device ",
others => "Unknown Device ");
constant ORBITA_DESC : vendor_description := "Orbita ";
constant orbita_lib : vendor_library_type := (
vendorid => VENDOR_ORBITA,
vendordesc => ORBITA_DESC,
device_table => orbita_device_table
);
constant UNKNOWN_DESC : vendor_description := "Unknown vendor ";
constant unknown_device_table : device_table_type := (
others => "Unknown Device ");
constant unknown_lib : vendor_library_type := (
vendorid => 0,
vendordesc => UNKNOWN_DESC,
device_table => unknown_device_table
);
constant iptable : device_array := (
VENDOR_GAISLER => gaisler_lib,
VENDOR_ESA => esa_lib,
VENDOR_OPENCHIP => openchip_lib,
VENDOR_OPENCORES => opencores_lib,
VENDOR_CONTRIB => contrib_lib,
VENDOR_EONIC => eonic_lib,
VENDOR_GLEICHMANN => gleichmann_lib,
VENDOR_MENTA => menta_lib,
VENDOR_EMBEDDIT => embeddit_lib,
VENDOR_SUN => sun_lib,
VENDOR_RADIONOR => radionor_lib,
VENDOR_ORBITA => orbita_lib,
VENDOR_SYNOPSYS => synopsys_lib,
VENDOR_CETON => ceton_lib,
others => unknown_lib);
type system_table_type is array (0 to 4095) of device_description;
constant system_table : system_table_type := (
LEON3_RTAX_CID2 => "LEON3FT RTAX Configuration 2 ",
LEON3_RTAX_CID5 => "LEON3FT RTAX Configuration 5 ",
XILINX_ML401 => "Xilinx ML401 Development board ",
XILINX_ML501 => "Xilinx ML501 Development board ",
XILINX_ML505 => "Xilinx ML505 Development board ",
AEROFLEX_UT699 => "Aeroflex UT699 Rad-Hard CPU ",
GAISLER_DARE1 => "Gaisler DARE1 Rad-Hard CPU ",
GAISLER_GR712RC => "Gaisler GR712RC Rad-Hard CPU ",
others => "Unknown system ");
-- pragma translate_on
end;
| mit | 2dd9ac1586bd7f08a312e58e67f80726 | 0.590852 | 3.737858 | false | false | false | false |
impedimentToProgress/UCI-BlueChip | AttackFiles/Attacks/privEsc/lib/tech/stratixii/simprims/stratixii_atoms.vhd | 2 | 517,995 | -- Copyright (C) 1991-2006 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions
-- and other software and tools, and its AMPP partner logic
-- functions, and any output files any of the foregoing
-- (including device programming or simulation files), and any
-- associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License
-- Subscription Agreement, Altera MegaCore Function License
-- Agreement, or other applicable license agreement, including,
-- without limitation, that your use is for the sole purpose of
-- programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the
-- applicable agreement for further details.
-- Quartus II 6.0 Build 178 04/27/2006
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
package stratixii_atom_pack is
function str_to_bin (lut_mask : string ) return std_logic_vector;
function product(list : std_logic_vector) return std_logic ;
function alt_conv_integer(arg : in std_logic_vector) return integer;
-- default generic values
CONSTANT DefWireDelay : VitalDelayType01 := (0 ns, 0 ns);
CONSTANT DefPropDelay01 : VitalDelayType01 := (1 ns, 1 ns);
CONSTANT DefPropDelay01Z : VitalDelayType01Z := (OTHERS => 1 ns);
CONSTANT DefSetupHoldCnst : TIME := 0 ns;
CONSTANT DefPulseWdthCnst : TIME := 0 ns;
-- default control options
-- CONSTANT DefGlitchMode : VitalGlitchKindType := OnEvent;
-- change default delay type to Transport : for spr 68748
CONSTANT DefGlitchMode : VitalGlitchKindType := VitalTransport;
CONSTANT DefGlitchMsgOn : BOOLEAN := FALSE;
CONSTANT DefGlitchXOn : BOOLEAN := FALSE;
CONSTANT DefMsgOnChecks : BOOLEAN := TRUE;
CONSTANT DefXOnChecks : BOOLEAN := TRUE;
-- output strength mapping
-- UX01ZWHL-
CONSTANT PullUp : VitalOutputMapType := "UX01HX01X";
CONSTANT NoPullUpZ : VitalOutputMapType := "UX01ZX01X";
CONSTANT PullDown : VitalOutputMapType := "UX01LX01X";
-- primitive result strength mapping
CONSTANT wiredOR : VitalResultMapType := ( 'U', 'X', 'L', '1' );
CONSTANT wiredAND : VitalResultMapType := ( 'U', 'X', '0', 'H' );
CONSTANT L : VitalTableSymbolType := '0';
CONSTANT H : VitalTableSymbolType := '1';
CONSTANT x : VitalTableSymbolType := '-';
CONSTANT S : VitalTableSymbolType := 'S';
CONSTANT R : VitalTableSymbolType := '/';
CONSTANT U : VitalTableSymbolType := 'X';
CONSTANT V : VitalTableSymbolType := 'B'; -- valid clock signal (non-rising)
-- Declare array types for CAM_SLICE
TYPE stratixii_mem_data IS ARRAY (0 to 31) of STD_LOGIC_VECTOR (31 downto 0);
function int2str( value : integer ) return string;
function map_x_to_0 (value : std_logic) return std_logic;
function SelectDelay (CONSTANT Paths: IN VitalPathArray01Type) return TIME;
end stratixii_atom_pack;
library IEEE;
use IEEE.std_logic_1164.all;
package body stratixii_atom_pack is
type masklength is array (4 downto 1) of std_logic_vector(3 downto 0);
function str_to_bin (lut_mask : string) return std_logic_vector is
variable slice : masklength := (OTHERS => "0000");
variable mask : std_logic_vector(15 downto 0);
begin
for i in 1 to lut_mask'length loop
case lut_mask(i) is
when '0' => slice(i) := "0000";
when '1' => slice(i) := "0001";
when '2' => slice(i) := "0010";
when '3' => slice(i) := "0011";
when '4' => slice(i) := "0100";
when '5' => slice(i) := "0101";
when '6' => slice(i) := "0110";
when '7' => slice(i) := "0111";
when '8' => slice(i) := "1000";
when '9' => slice(i) := "1001";
when 'a' => slice(i) := "1010";
when 'A' => slice(i) := "1010";
when 'b' => slice(i) := "1011";
when 'B' => slice(i) := "1011";
when 'c' => slice(i) := "1100";
when 'C' => slice(i) := "1100";
when 'd' => slice(i) := "1101";
when 'D' => slice(i) := "1101";
when 'e' => slice(i) := "1110";
when 'E' => slice(i) := "1110";
when others => slice(i) := "1111";
end case;
end loop;
mask := (slice(1) & slice(2) & slice(3) & slice(4));
return (mask);
end str_to_bin;
function product (list: std_logic_vector) return std_logic is
begin
for i in 0 to 31 loop
if list(i) = '0' then
return ('0');
end if;
end loop;
return ('1');
end product;
function alt_conv_integer(arg : in std_logic_vector) return integer is
variable result : integer;
begin
result := 0;
for i in arg'range loop
if arg(i) = '1' then
result := result + 2**i;
end if;
end loop;
return result;
end alt_conv_integer;
function int2str( value : integer ) return string is
variable ivalue,index : integer;
variable digit : integer;
variable line_no: string(8 downto 1) := " ";
begin
ivalue := value;
index := 1;
if (ivalue = 0) then
line_no := " 0";
end if;
while (ivalue > 0) loop
digit := ivalue MOD 10;
ivalue := ivalue/10;
case digit is
when 0 =>
line_no(index) := '0';
when 1 =>
line_no(index) := '1';
when 2 =>
line_no(index) := '2';
when 3 =>
line_no(index) := '3';
when 4 =>
line_no(index) := '4';
when 5 =>
line_no(index) := '5';
when 6 =>
line_no(index) := '6';
when 7 =>
line_no(index) := '7';
when 8 =>
line_no(index) := '8';
when 9 =>
line_no(index) := '9';
when others =>
ASSERT FALSE
REPORT "Illegal number!"
SEVERITY ERROR;
end case;
index := index + 1;
end loop;
return line_no;
end;
function map_x_to_0 (value : std_logic) return std_logic is
begin
if (Is_X (value) = TRUE) then
return '0';
else
return value;
end if;
end;
function SelectDelay (CONSTANT Paths : IN VitalPathArray01Type) return TIME IS
variable Temp : TIME;
variable TransitionTime : TIME := TIME'HIGH;
variable PathDelay : TIME := TIME'HIGH;
begin
for i IN Paths'RANGE loop
next when not Paths(i).PathCondition;
next when Paths(i).InputChangeTime > TransitionTime;
Temp := Paths(i).PathDelay(tr01);
if Paths(i).InputChangeTime < TransitionTime then
PathDelay := Temp;
else
if Temp < PathDelay then
PathDelay := Temp;
end if;
end if;
TransitionTime := Paths(i).InputChangeTime;
end loop;
return PathDelay;
end;
end stratixii_atom_pack;
Library ieee;
use ieee.std_logic_1164.all;
Package stratixii_pllpack is
procedure find_simple_integer_fraction( numerator : in integer;
denominator : in integer;
max_denom : in integer;
fraction_num : out integer;
fraction_div : out integer);
function gcd (X: integer; Y: integer) return integer;
function count_digit (X: integer) return integer;
function scale_num (X: integer; Y: integer) return integer;
function lcm (A1: integer; A2: integer; A3: integer; A4: integer;
A5: integer; A6: integer; A7: integer;
A8: integer; A9: integer; A10: integer; P: integer) return integer;
function output_counter_value (clk_divide: integer; clk_mult : integer ;
M: integer; N: integer ) return integer;
function counter_mode (duty_cycle: integer; output_counter_value: integer) return string;
function counter_high (output_counter_value: integer := 1; duty_cycle: integer)
return integer;
function counter_low (output_counter_value: integer; duty_cycle: integer)
return integer;
function mintimedelay (t1: integer; t2: integer; t3: integer; t4: integer;
t5: integer; t6: integer; t7: integer; t8: integer;
t9: integer; t10: integer) return integer;
function maxnegabs (t1: integer; t2: integer; t3: integer; t4: integer;
t5: integer; t6: integer; t7: integer; t8: integer;
t9: integer; t10: integer) return integer;
function counter_time_delay ( clk_time_delay: integer;
m_time_delay: integer; n_time_delay: integer)
return integer;
function get_phase_degree (phase_shift: integer; clk_period: integer) return integer;
function counter_initial (tap_phase: integer; m: integer; n: integer)
return integer;
function counter_ph (tap_phase: integer; m : integer; n: integer) return integer;
function ph_adjust (tap_phase: integer; ph_base : integer) return integer;
function translate_string (mode : string) return string;
function str2int (s : string) return integer;
function dqs_str2int (s : string) return integer;
end stratixii_pllpack;
package body stratixii_pllpack is
-- finds the closest integer fraction of a given pair of numerator and denominator.
procedure find_simple_integer_fraction( numerator : in integer;
denominator : in integer;
max_denom : in integer;
fraction_num : out integer;
fraction_div : out integer) is
constant MAX_ITER : integer := 20;
type INT_ARRAY is array ((MAX_ITER-1) downto 0) of integer;
variable quotient_array : INT_ARRAY;
variable int_loop_iter : integer;
variable int_quot : integer;
variable m_value : integer;
variable d_value : integer;
variable old_m_value : integer;
variable swap : integer;
variable loop_iter : integer;
variable num : integer;
variable den : integer;
variable i_max_iter : integer;
begin
loop_iter := 0;
num := numerator;
den := denominator;
i_max_iter := max_iter;
while (loop_iter < i_max_iter) loop
int_quot := num / den;
quotient_array(loop_iter) := int_quot;
num := num - (den*int_quot);
loop_iter := loop_iter+1;
if ((num = 0) or (max_denom /= -1) or (loop_iter = i_max_iter)) then
-- calculate the numerator and denominator if there is a restriction on the
-- max denom value or if the loop is ending
m_value := 0;
d_value := 1;
-- get the rounded value at this stage for the remaining fraction
if (den /= 0) then
m_value := (2*num/den);
end if;
-- calculate the fraction numerator and denominator at this stage
for int_loop_iter in (loop_iter-1) downto 0 loop
if (m_value = 0) then
m_value := quotient_array(int_loop_iter);
d_value := 1;
else
old_m_value := m_value;
m_value := (quotient_array(int_loop_iter)*m_value) + d_value;
d_value := old_m_value;
end if;
end loop;
-- if the denominator is less than the maximum denom_value or if there is no restriction save it
if ((d_value <= max_denom) or (max_denom = -1)) then
if ((m_value = 0) or (d_value = 0)) then
fraction_num := numerator;
fraction_div := denominator;
else
fraction_num := m_value;
fraction_div := d_value;
end if;
end if;
-- end the loop if the denomitor has overflown or the numerator is zero (no remainder during this round)
if (((d_value > max_denom) and (max_denom /= -1)) or (num = 0)) then
i_max_iter := loop_iter;
end if;
end if;
-- swap the numerator and denominator for the next round
swap := den;
den := num;
num := swap;
end loop;
end find_simple_integer_fraction;
-- find the greatest common denominator of X and Y
function gcd (X: integer; Y: integer) return integer is
variable L, S, R, G : integer := 1;
begin
if (X < Y) then -- find which is smaller.
S := X;
L := Y;
else
S := Y;
L := X;
end if;
R := S;
while ( R > 1) loop
S := L;
L := R;
R := S rem L; -- divide bigger number by smaller.
-- remainder becomes smaller number.
end loop;
if (R = 0) then -- if evenly divisible then L is gcd else it is 1.
G := L;
else
G := R;
end if;
return G;
end gcd;
-- count the number of digits in the given integer
function count_digit (X: integer)
return integer is
variable count, result: integer := 0;
begin
result := X;
while (result /= 0) loop
result := (result / 10);
count := count + 1;
end loop;
return count;
end count_digit;
-- reduce the given huge number to Y significant digits
function scale_num (X: integer; Y: integer)
return integer is
variable count : integer := 0;
variable lc, fac_ten, result: integer := 1;
begin
count := count_digit(X);
for lc in 1 to (count-Y) loop
fac_ten := fac_ten * 10;
end loop;
result := (X / fac_ten);
return result;
end scale_num;
-- find the least common multiple of A1 to A10
function lcm (A1: integer; A2: integer; A3: integer; A4: integer;
A5: integer; A6: integer; A7: integer;
A8: integer; A9: integer; A10: integer; P: integer)
return integer is
variable M1, M2, M3, M4, M5 , M6, M7, M8, M9, R: integer := 1;
begin
M1 := (A1 * A2)/gcd(A1, A2);
M2 := (M1 * A3)/gcd(M1, A3);
M3 := (M2 * A4)/gcd(M2, A4);
M4 := (M3 * A5)/gcd(M3, A5);
M5 := (M4 * A6)/gcd(M4, A6);
M6 := (M5 * A7)/gcd(M5, A7);
M7 := (M6 * A8)/gcd(M6, A8);
M8 := (M7 * A9)/gcd(M7, A9);
M9 := (M8 * A10)/gcd(M8, A10);
if (M9 < 3) then
R := 10;
elsif ((M9 <= 10) and (M9 >= 3)) then
R := 4 * M9;
elsif (M9 > 1000) then
R := scale_num(M9,3);
else
R := M9 ;
end if;
return R;
end lcm;
-- find the factor of division of the output clock frequency compared to the VCO
function output_counter_value (clk_divide: integer; clk_mult: integer ;
M: integer; N: integer ) return integer is
variable R: integer := 1;
begin
R := (clk_divide * M)/(clk_mult * N);
return R;
end output_counter_value;
-- find the mode of each PLL counter - bypass, even or odd
function counter_mode (duty_cycle: integer; output_counter_value: integer)
return string is
variable R: string (1 to 6) := " ";
variable counter_value: integer := 1;
begin
counter_value := (2*duty_cycle*output_counter_value)/100;
if output_counter_value = 1 then
R := "bypass";
elsif (counter_value REM 2) = 0 then
R := " even";
else
R := " odd";
end if;
return R;
end counter_mode;
-- find the number of VCO clock cycles to hold the output clock high
function counter_high (output_counter_value: integer := 1; duty_cycle: integer)
return integer is
variable R: integer := 1;
variable half_cycle_high : integer := 1;
begin
half_cycle_high := (duty_cycle * output_counter_value *2)/100 ;
if (half_cycle_high REM 2 = 0) then
R := half_cycle_high/2 ;
else
R := (half_cycle_high/2) + 1;
end if;
return R;
end;
-- find the number of VCO clock cycles to hold the output clock low
function counter_low (output_counter_value: integer; duty_cycle: integer)
return integer is
variable R, R1: integer := 1;
variable half_cycle_high : integer := 1;
begin
half_cycle_high := (duty_cycle * output_counter_value*2)/100 ;
if (half_cycle_high REM 2 = 0) then
R1 := half_cycle_high/2 ;
else
R1 := (half_cycle_high/2) + 1;
end if;
R := output_counter_value - R1;
return R;
end;
-- find the smallest time delay amongst t1 to t10
function mintimedelay (t1: integer; t2: integer; t3: integer; t4: integer;
t5: integer; t6: integer; t7: integer; t8: integer;
t9: integer; t10: integer) return integer is
variable m1,m2,m3,m4,m5,m6,m7,m8,m9 : integer := 0;
begin
if (t1 < t2) then m1 := t1; else m1 := t2; end if;
if (m1 < t3) then m2 := m1; else m2 := t3; end if;
if (m2 < t4) then m3 := m2; else m3 := t4; end if;
if (m3 < t5) then m4 := m3; else m4 := t5; end if;
if (m4 < t6) then m5 := m4; else m5 := t6; end if;
if (m5 < t7) then m6 := m5; else m6 := t7; end if;
if (m6 < t8) then m7 := m6; else m7 := t8; end if;
if (m7 < t9) then m8 := m7; else m8 := t9; end if;
if (m8 < t10) then m9 := m8; else m9 := t10; end if;
if (m9 > 0) then return m9; else return 0; end if;
end;
-- find the numerically largest negative number, and return its absolute value
function maxnegabs (t1: integer; t2: integer; t3: integer; t4: integer;
t5: integer; t6: integer; t7: integer; t8: integer;
t9: integer; t10: integer) return integer is
variable m1,m2,m3,m4,m5,m6,m7,m8,m9 : integer := 0;
begin
if (t1 < t2) then m1 := t1; else m1 := t2; end if;
if (m1 < t3) then m2 := m1; else m2 := t3; end if;
if (m2 < t4) then m3 := m2; else m3 := t4; end if;
if (m3 < t5) then m4 := m3; else m4 := t5; end if;
if (m4 < t6) then m5 := m4; else m5 := t6; end if;
if (m5 < t7) then m6 := m5; else m6 := t7; end if;
if (m6 < t8) then m7 := m6; else m7 := t8; end if;
if (m7 < t9) then m8 := m7; else m8 := t9; end if;
if (m8 < t10) then m9 := m8; else m9 := t10; end if;
if (m9 < 0) then return (0 - m9); else return 0; end if;
end;
-- adjust the phase (tap_phase) with the largest negative number (ph_base)
function ph_adjust (tap_phase: integer; ph_base : integer) return integer is
begin
return (tap_phase + ph_base);
end;
-- find the time delay for each PLL counter
function counter_time_delay (clk_time_delay: integer;
m_time_delay: integer; n_time_delay: integer)
return integer is
variable R: integer := 0;
begin
R := clk_time_delay + m_time_delay - n_time_delay;
return R;
end;
-- calculate the given phase shift (in ps) in terms of degrees
function get_phase_degree (phase_shift: integer; clk_period: integer)
return integer is
variable result: integer := 0;
begin
result := ( phase_shift * 360 ) / clk_period;
-- to round up the calculation result
if (result > 0) then
result := result + 1;
elsif (result < 0) then
result := result - 1;
else
result := 0;
end if;
return result;
end;
-- find the number of VCO clock cycles to wait initially before the first rising
-- edge of the output clock
function counter_initial (tap_phase: integer; m: integer; n: integer)
return integer is
variable R: integer;
variable R1: real;
begin
R1 := (real(abs(tap_phase)) * real(m))/(360.0 * real(n)) + 0.5;
-- Note NCSim VHDL had problem in rounding up for 0.5 - 0.99.
-- This checking will ensure that the rounding up is done.
if (R1 >= 0.5) and (R1 <= 1.0) then
R1 := 1.0;
end if;
R := integer(R1);
return R;
end;
-- find which VCO phase tap (0 to 7) to align the rising edge of the output clock to
function counter_ph (tap_phase: integer; m: integer; n: integer) return integer is
variable R: integer := 0;
begin
-- 0.5 is added for proper rounding of the tap_phase.
R := (integer(real(tap_phase * m / n)+ 0.5) REM 360)/45;
return R;
end;
-- convert given string to length 6 by padding with spaces
function translate_string (mode : string) return string is
variable new_mode : string (1 to 6) := " ";
begin
if (mode = "bypass") then
new_mode := "bypass";
elsif (mode = "even") then
new_mode := " even";
elsif (mode = "odd") then
new_mode := " odd";
end if;
return new_mode;
end;
function str2int (s : string) return integer is
variable len : integer := s'length;
variable newdigit : integer := 0;
variable sign : integer := 1;
variable digit : integer := 0;
begin
for i in 1 to len loop
case s(i) is
when '-' =>
if i = 1 then
sign := -1;
else
ASSERT FALSE
REPORT "Illegal Character "& s(i) & "i n string parameter! "
SEVERITY ERROR;
end if;
when '0' =>
digit := 0;
when '1' =>
digit := 1;
when '2' =>
digit := 2;
when '3' =>
digit := 3;
when '4' =>
digit := 4;
when '5' =>
digit := 5;
when '6' =>
digit := 6;
when '7' =>
digit := 7;
when '8' =>
digit := 8;
when '9' =>
digit := 9;
when others =>
ASSERT FALSE
REPORT "Illegal Character "& s(i) & "in string parameter! "
SEVERITY ERROR;
end case;
newdigit := newdigit * 10 + digit;
end loop;
return (sign*newdigit);
end;
function dqs_str2int (s : string) return integer is
variable len : integer := s'length;
variable newdigit : integer := 0;
variable sign : integer := 1;
variable digit : integer := 0;
variable err : boolean := false;
begin
for i in 1 to len loop
case s(i) is
when '-' =>
if i = 1 then
sign := -1;
else
ASSERT FALSE
REPORT "Illegal Character "& s(i) & " in string parameter! "
SEVERITY ERROR;
err := true;
end if;
when '0' =>
digit := 0;
when '1' =>
digit := 1;
when '2' =>
digit := 2;
when '3' =>
digit := 3;
when '4' =>
digit := 4;
when '5' =>
digit := 5;
when '6' =>
digit := 6;
when '7' =>
digit := 7;
when '8' =>
digit := 8;
when '9' =>
digit := 9;
when others =>
-- set error flag
err := true;
end case;
if (err) then
err := false;
else
newdigit := newdigit * 10 + digit;
end if;
end loop;
return (sign*newdigit);
end;
end stratixii_pllpack;
--
--
-- DFFE Model
--
--
LIBRARY IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.stratixii_atom_pack.all;
entity stratixii_dffe is
generic(
TimingChecksOn: Boolean := True;
XOn: Boolean := DefGlitchXOn;
MsgOn: Boolean := DefGlitchMsgOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks;
InstancePath: STRING := "*";
tpd_PRN_Q_negedge : VitalDelayType01 := DefPropDelay01;
tpd_CLRN_Q_negedge : VitalDelayType01 := DefPropDelay01;
tpd_CLK_Q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_ENA_Q_posedge : VitalDelayType01 := DefPropDelay01;
tsetup_D_CLK_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_D_CLK_noedge_negedge : VitalDelayType := DefSetupHoldCnst;
tsetup_ENA_CLK_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_D_CLK_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_D_CLK_noedge_negedge : VitalDelayType := DefSetupHoldCnst;
thold_ENA_CLK_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tipd_D : VitalDelayType01 := DefPropDelay01;
tipd_CLRN : VitalDelayType01 := DefPropDelay01;
tipd_PRN : VitalDelayType01 := DefPropDelay01;
tipd_CLK : VitalDelayType01 := DefPropDelay01;
tipd_ENA : VitalDelayType01 := DefPropDelay01);
port(
Q : out STD_LOGIC := '0';
D : in STD_LOGIC;
CLRN : in STD_LOGIC;
PRN : in STD_LOGIC;
CLK : in STD_LOGIC;
ENA : in STD_LOGIC);
attribute VITAL_LEVEL0 of stratixii_dffe : entity is TRUE;
end stratixii_dffe;
-- architecture body --
architecture behave of stratixii_dffe is
attribute VITAL_LEVEL0 of behave : architecture is TRUE;
signal D_ipd : STD_ULOGIC := 'U';
signal CLRN_ipd : STD_ULOGIC := 'U';
signal PRN_ipd : STD_ULOGIC := 'U';
signal CLK_ipd : STD_ULOGIC := 'U';
signal ENA_ipd : STD_ULOGIC := 'U';
begin
---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
VitalWireDelay (D_ipd, D, tipd_D);
VitalWireDelay (CLRN_ipd, CLRN, tipd_CLRN);
VitalWireDelay (PRN_ipd, PRN, tipd_PRN);
VitalWireDelay (CLK_ipd, CLK, tipd_CLK);
VitalWireDelay (ENA_ipd, ENA, tipd_ENA);
end block;
--------------------
-- BEHAVIOR SECTION
--------------------
VITALBehavior : process (D_ipd, CLRN_ipd, PRN_ipd, CLK_ipd, ENA_ipd)
-- timing check results
VARIABLE Tviol_D_CLK : STD_ULOGIC := '0';
VARIABLE Tviol_ENA_CLK : STD_ULOGIC := '0';
VARIABLE TimingData_D_CLK : VitalTimingDataType := VitalTimingDataInit;
VARIABLE TimingData_ENA_CLK : VitalTimingDataType := VitalTimingDataInit;
-- functionality results
VARIABLE Violation : STD_ULOGIC := '0';
VARIABLE PrevData_Q : STD_LOGIC_VECTOR(0 to 7);
VARIABLE D_delayed : STD_ULOGIC := 'U';
VARIABLE CLK_delayed : STD_ULOGIC := 'U';
VARIABLE ENA_delayed : STD_ULOGIC := 'U';
VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => '0');
-- output glitch detection variables
VARIABLE Q_VitalGlitchData : VitalGlitchDataType;
CONSTANT dffe_Q_tab : VitalStateTableType := (
( L, L, x, x, x, x, x, x, x, L ),
( L, H, L, H, H, x, x, H, x, H ),
( L, H, L, H, x, L, x, H, x, H ),
( L, H, L, x, H, H, x, H, x, H ),
( L, H, H, x, x, x, H, x, x, S ),
( L, H, x, x, x, x, L, x, x, H ),
( L, H, x, x, x, x, H, L, x, S ),
( L, x, L, L, L, x, H, H, x, L ),
( L, x, L, L, x, L, H, H, x, L ),
( L, x, L, x, L, H, H, H, x, L ),
( L, x, x, x, x, x, x, x, x, S ));
begin
------------------------
-- Timing Check Section
------------------------
if (TimingChecksOn) then
VitalSetupHoldCheck (
Violation => Tviol_D_CLK,
TimingData => TimingData_D_CLK,
TestSignal => D_ipd,
TestSignalName => "D",
RefSignal => CLK_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_D_CLK_noedge_posedge,
SetupLow => tsetup_D_CLK_noedge_posedge,
HoldHigh => thold_D_CLK_noedge_posedge,
HoldLow => thold_D_CLK_noedge_posedge,
CheckEnabled => TO_X01(( (NOT PRN_ipd) ) OR ( (NOT CLRN_ipd) ) OR ( (NOT ENA_ipd) )) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/DFFE",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_ENA_CLK,
TimingData => TimingData_ENA_CLK,
TestSignal => ENA_ipd,
TestSignalName => "ENA",
RefSignal => CLK_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_ENA_CLK_noedge_posedge,
SetupLow => tsetup_ENA_CLK_noedge_posedge,
HoldHigh => thold_ENA_CLK_noedge_posedge,
HoldLow => thold_ENA_CLK_noedge_posedge,
CheckEnabled => TO_X01(( (NOT PRN_ipd) ) OR ( (NOT CLRN_ipd) ) ) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/DFFE",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
end if;
-------------------------
-- Functionality Section
-------------------------
Violation := Tviol_D_CLK or Tviol_ENA_CLK;
VitalStateTable(
StateTable => dffe_Q_tab,
DataIn => (
Violation, CLRN_ipd, CLK_delayed, Results(1), D_delayed, ENA_delayed, PRN_ipd, CLK_ipd),
Result => Results,
NumStates => 1,
PreviousDataIn => PrevData_Q);
D_delayed := D_ipd;
CLK_delayed := CLK_ipd;
ENA_delayed := ENA_ipd;
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
OutSignal => Q,
OutSignalName => "Q",
OutTemp => Results(1),
Paths => ( 0 => (PRN_ipd'last_event, tpd_PRN_Q_negedge, TRUE),
1 => (CLRN_ipd'last_event, tpd_CLRN_Q_negedge, TRUE),
2 => (CLK_ipd'last_event, tpd_CLK_Q_posedge, TRUE)),
GlitchData => Q_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
end behave;
--
--
-- stratixii_mux21 Model
--
--
LIBRARY IEEE;
use ieee.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use work.stratixii_atom_pack.all;
entity stratixii_mux21 is
generic(
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
InstancePath: STRING := "*";
tpd_A_MO : VitalDelayType01 := DefPropDelay01;
tpd_B_MO : VitalDelayType01 := DefPropDelay01;
tpd_S_MO : VitalDelayType01 := DefPropDelay01;
tipd_A : VitalDelayType01 := DefPropDelay01;
tipd_B : VitalDelayType01 := DefPropDelay01;
tipd_S : VitalDelayType01 := DefPropDelay01);
port (
A : in std_logic := '0';
B : in std_logic := '0';
S : in std_logic := '0';
MO : out std_logic);
attribute VITAL_LEVEL0 of stratixii_mux21 : entity is TRUE;
end stratixii_mux21;
architecture AltVITAL of stratixii_mux21 is
attribute VITAL_LEVEL0 of AltVITAL : architecture is TRUE;
signal A_ipd, B_ipd, S_ipd : std_logic;
begin
---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
VitalWireDelay (A_ipd, A, tipd_A);
VitalWireDelay (B_ipd, B, tipd_B);
VitalWireDelay (S_ipd, S, tipd_S);
end block;
--------------------
-- BEHAVIOR SECTION
--------------------
VITALBehavior : process (A_ipd, B_ipd, S_ipd)
-- output glitch detection variables
VARIABLE MO_GlitchData : VitalGlitchDataType;
variable tmp_MO : std_logic;
begin
-------------------------
-- Functionality Section
-------------------------
if (S_ipd = '1') then
tmp_MO := B_ipd;
else
tmp_MO := A_ipd;
end if;
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
OutSignal => MO,
OutSignalName => "MO",
OutTemp => tmp_MO,
Paths => ( 0 => (A_ipd'last_event, tpd_A_MO, TRUE),
1 => (B_ipd'last_event, tpd_B_MO, TRUE),
2 => (S_ipd'last_event, tpd_S_MO, TRUE)),
GlitchData => MO_GlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
end AltVITAL;
--
--
-- stratixii_mux41 Model
--
--
LIBRARY IEEE;
use ieee.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use work.stratixii_atom_pack.all;
entity stratixii_mux41 is
generic(
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
InstancePath: STRING := "*";
tpd_IN0_MO : VitalDelayType01 := DefPropDelay01;
tpd_IN1_MO : VitalDelayType01 := DefPropDelay01;
tpd_IN2_MO : VitalDelayType01 := DefPropDelay01;
tpd_IN3_MO : VitalDelayType01 := DefPropDelay01;
tpd_S_MO : VitalDelayArrayType01(1 downto 0) := (OTHERS => DefPropDelay01);
tipd_IN0 : VitalDelayType01 := DefPropDelay01;
tipd_IN1 : VitalDelayType01 := DefPropDelay01;
tipd_IN2 : VitalDelayType01 := DefPropDelay01;
tipd_IN3 : VitalDelayType01 := DefPropDelay01;
tipd_S : VitalDelayArrayType01(1 downto 0) := (OTHERS => DefPropDelay01)
);
port (
IN0 : in std_logic := '0';
IN1 : in std_logic := '0';
IN2 : in std_logic := '0';
IN3 : in std_logic := '0';
S : in std_logic_vector(1 downto 0) := (OTHERS => '0');
MO : out std_logic
);
attribute VITAL_LEVEL0 of stratixii_mux41 : entity is TRUE;
end stratixii_mux41;
architecture AltVITAL of stratixii_mux41 is
attribute VITAL_LEVEL0 of AltVITAL : architecture is TRUE;
signal IN0_ipd, IN1_ipd, IN2_ipd, IN3_ipd : std_logic;
signal S_ipd : std_logic_vector(1 downto 0);
begin
---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
VitalWireDelay (IN0_ipd, IN0, tipd_IN0);
VitalWireDelay (IN1_ipd, IN1, tipd_IN1);
VitalWireDelay (IN2_ipd, IN2, tipd_IN2);
VitalWireDelay (IN3_ipd, IN3, tipd_IN3);
VitalWireDelay (S_ipd(0), S(0), tipd_S(0));
VitalWireDelay (S_ipd(1), S(1), tipd_S(1));
end block;
--------------------
-- BEHAVIOR SECTION
--------------------
VITALBehavior : process (IN0_ipd, IN1_ipd, IN2_ipd, IN3_ipd, S_ipd(0), S_ipd(1))
-- output glitch detection variables
VARIABLE MO_GlitchData : VitalGlitchDataType;
variable tmp_MO : std_logic;
begin
-------------------------
-- Functionality Section
-------------------------
if ((S_ipd(1) = '1') AND (S_ipd(0) = '1')) then
tmp_MO := IN3_ipd;
elsif ((S_ipd(1) = '1') AND (S_ipd(0) = '0')) then
tmp_MO := IN2_ipd;
elsif ((S_ipd(1) = '0') AND (S_ipd(0) = '1')) then
tmp_MO := IN1_ipd;
else
tmp_MO := IN0_ipd;
end if;
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
OutSignal => MO,
OutSignalName => "MO",
OutTemp => tmp_MO,
Paths => ( 0 => (IN0_ipd'last_event, tpd_IN0_MO, TRUE),
1 => (IN1_ipd'last_event, tpd_IN1_MO, TRUE),
2 => (IN2_ipd'last_event, tpd_IN2_MO, TRUE),
3 => (IN3_ipd'last_event, tpd_IN3_MO, TRUE),
4 => (S_ipd(0)'last_event, tpd_S_MO(0), TRUE),
5 => (S_ipd(1)'last_event, tpd_S_MO(1), TRUE)),
GlitchData => MO_GlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
end AltVITAL;
--
--
-- stratixii_and1 Model
--
--
LIBRARY IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.VITAL_Timing.all;
use work.stratixii_atom_pack.all;
-- entity declaration --
entity stratixii_and1 is
generic(
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
InstancePath: STRING := "*";
tpd_IN1_Y : VitalDelayType01 := DefPropDelay01;
tipd_IN1 : VitalDelayType01 := DefPropDelay01);
port(
Y : out STD_LOGIC;
IN1 : in STD_LOGIC);
attribute VITAL_LEVEL0 of stratixii_and1 : entity is TRUE;
end stratixii_and1;
-- architecture body --
architecture AltVITAL of stratixii_and1 is
attribute VITAL_LEVEL0 of AltVITAL : architecture is TRUE;
SIGNAL IN1_ipd : STD_ULOGIC := 'U';
begin
---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
VitalWireDelay (IN1_ipd, IN1, tipd_IN1);
end block;
--------------------
-- BEHAVIOR SECTION
--------------------
VITALBehavior : process (IN1_ipd)
-- functionality results
VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X');
ALIAS Y_zd : STD_ULOGIC is Results(1);
-- output glitch detection variables
VARIABLE Y_GlitchData : VitalGlitchDataType;
begin
-------------------------
-- Functionality Section
-------------------------
Y_zd := TO_X01(IN1_ipd);
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
OutSignal => Y,
OutSignalName => "Y",
OutTemp => Y_zd,
Paths => (0 => (IN1_ipd'last_event, tpd_IN1_Y, TRUE)),
GlitchData => Y_GlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
end AltVITAL;
----------------------------------------------------------------------------
-- Module Name : stratixii_ram_register
-- Description : Register module for RAM inputs/outputs
----------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.VITAL_Timing.all;
USE IEEE.VITAL_Primitives.all;
USE work.stratixii_atom_pack.all;
ENTITY stratixii_ram_register IS
GENERIC (
width : INTEGER := 1;
preset : STD_LOGIC := '0';
tipd_d : VitalDelayArrayType01(143 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
tipd_stall : VitalDelayType01 := DefPropDelay01;
tipd_aclr : VitalDelayType01 := DefPropDelay01;
tpw_ena_posedge : VitalDelayType := DefPulseWdthCnst;
tpd_clk_q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_aclr_q_posedge : VitalDelayType01 := DefPropDelay01;
tsetup_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_stall_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_stall_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_aclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_aclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst
);
PORT (
d : IN STD_LOGIC_VECTOR(width - 1 DOWNTO 0);
clk : IN STD_LOGIC;
ena : IN STD_LOGIC;
stall : IN STD_LOGIC;
aclr : IN STD_LOGIC;
devclrn : IN STD_LOGIC;
devpor : IN STD_LOGIC;
q : OUT STD_LOGIC_VECTOR(width - 1 DOWNTO 0);
aclrout : OUT STD_LOGIC
);
END stratixii_ram_register;
ARCHITECTURE reg_arch OF stratixii_ram_register IS
SIGNAL d_ipd : STD_LOGIC_VECTOR(width - 1 DOWNTO 0);
SIGNAL clk_ipd : STD_LOGIC;
SIGNAL ena_ipd : STD_LOGIC;
SIGNAL aclr_ipd : STD_LOGIC;
SIGNAL stall_ipd : STD_LOGIC;
BEGIN
WireDelay : BLOCK
BEGIN
loopbits : FOR i in d'RANGE GENERATE
VitalWireDelay (d_ipd(i), d(i), tipd_d(i));
END GENERATE;
VitalWireDelay (clk_ipd, clk, tipd_clk);
VitalWireDelay (aclr_ipd, aclr, tipd_aclr);
VitalWireDelay (ena_ipd, ena, tipd_ena);
VitalWireDelay (stall_ipd, stall, tipd_stall);
END BLOCK;
PROCESS (d_ipd,ena_ipd,stall_ipd,clk_ipd,aclr_ipd,devclrn,devpor)
VARIABLE Tviol_clk_ena : STD_ULOGIC := '0';
VARIABLE Tviol_clk_aclr : STD_ULOGIC := '0';
VARIABLE Tviol_data_clk : STD_ULOGIC := '0';
VARIABLE TimingData_clk_ena : VitalTimingDataType := VitalTimingDataInit;
VARIABLE TimingData_clk_stall : VitalTimingDataType := VitalTimingDataInit;
VARIABLE TimingData_clk_aclr : VitalTimingDataType := VitalTimingDataInit;
VARIABLE TimingData_data_clk : VitalTimingDataType := VitalTimingDataInit;
VARIABLE Tviol_ena : STD_ULOGIC := '0';
VARIABLE PeriodData_ena : VitalPeriodDataType := VitalPeriodDataInit;
VARIABLE q_VitalGlitchDataArray : VitalGlitchDataArrayType(143 downto 0);
VARIABLE CQDelay : TIME := 0 ns;
VARIABLE q_reg : STD_LOGIC_VECTOR(width - 1 DOWNTO 0) := (OTHERS => preset);
BEGIN
IF (aclr_ipd = '1' OR devclrn = '0' OR devpor = '0') THEN
q_reg := (OTHERS => preset);
ELSIF (clk_ipd = '1' AND clk_ipd'EVENT AND ena_ipd = '1' AND stall_ipd = '0') THEN
q_reg := d_ipd;
END IF;
-- Timing checks
VitalSetupHoldCheck (
Violation => Tviol_clk_ena,
TimingData => TimingData_clk_ena,
TestSignal => ena_ipd,
TestSignalName => "ena",
RefSignal => clk_ipd,
RefSignalName => "clk",
SetupHigh => tsetup_ena_clk_noedge_posedge,
SetupLow => tsetup_ena_clk_noedge_posedge,
HoldHigh => thold_ena_clk_noedge_posedge,
HoldLow => thold_ena_clk_noedge_posedge,
CheckEnabled => ((aclr_ipd) OR (NOT ena_ipd)) /= '1',
RefTransition => '/',
HeaderMsg => "/RAM Register VitalSetupHoldCheck",
XOn => DefXOnChecks,
MsgOn => DefMsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_clk_ena,
TimingData => TimingData_clk_stall,
TestSignal => stall_ipd,
TestSignalName => "stall",
RefSignal => clk_ipd,
RefSignalName => "clk",
SetupHigh => tsetup_stall_clk_noedge_posedge,
SetupLow => tsetup_stall_clk_noedge_posedge,
HoldHigh => thold_stall_clk_noedge_posedge,
HoldLow => thold_stall_clk_noedge_posedge,
CheckEnabled => ((aclr_ipd) OR (NOT ena_ipd)) /= '1',
RefTransition => '/',
HeaderMsg => "/RAM Register VitalSetupHoldCheck",
XOn => DefXOnChecks,
MsgOn => DefMsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_clk_aclr,
TimingData => TimingData_clk_aclr,
TestSignal => aclr_ipd,
TestSignalName => "aclr",
RefSignal => clk_ipd,
RefSignalName => "clk",
SetupHigh => tsetup_aclr_clk_noedge_posedge,
SetupLow => tsetup_aclr_clk_noedge_posedge,
HoldHigh => thold_aclr_clk_noedge_posedge,
HoldLow => thold_aclr_clk_noedge_posedge,
CheckEnabled => ((aclr_ipd) OR (NOT ena_ipd)) /= '1',
RefTransition => '/',
HeaderMsg => "/RAM Register VitalSetupHoldCheck",
XOn => DefXOnChecks,
MsgOn => DefMsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_data_clk,
TimingData => TimingData_data_clk,
TestSignal => d_ipd,
TestSignalName => "data",
RefSignal => clk_ipd,
RefSignalName => "clk",
SetupHigh => tsetup_d_clk_noedge_posedge,
SetupLow => tsetup_d_clk_noedge_posedge,
HoldHigh => thold_d_clk_noedge_posedge,
HoldLow => thold_d_clk_noedge_posedge,
CheckEnabled => ((aclr_ipd) OR (NOT ena_ipd)) /= '1',
RefTransition => '/',
HeaderMsg => "/RAM Register VitalSetupHoldCheck",
XOn => DefXOnChecks,
MsgOn => DefMsgOnChecks );
VitalPeriodPulseCheck (
Violation => Tviol_ena,
PeriodData => PeriodData_ena,
TestSignal => ena_ipd,
TestSignalName => "ena",
PulseWidthHigh => tpw_ena_posedge,
HeaderMsg => "/RAM Register VitalPeriodPulseCheck",
XOn => DefXOnChecks,
MsgOn => DefMsgOnChecks );
-- Path Delay Selection
CQDelay := SelectDelay (
Paths => (
(0 => (clk_ipd'LAST_EVENT,tpd_clk_q_posedge,TRUE),
1 => (aclr_ipd'LAST_EVENT,tpd_aclr_q_posedge,TRUE))
)
);
q <= TRANSPORT q_reg AFTER CQDelay;
END PROCESS;
aclrout <= aclr_ipd;
END reg_arch;
----------------------------------------------------------------------------
-- Module Name : stratixii_ram_pulse_generator
-- Description : Generate pulse to initiate memory read/write operations
----------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.VITAL_Timing.all;
USE IEEE.VITAL_Primitives.all;
USE work.stratixii_atom_pack.all;
ENTITY stratixii_ram_pulse_generator IS
GENERIC (
tipd_clk : VitalDelayType01 := (0.5 ns,0.5 ns);
tipd_ena : VitalDelayType01 := DefPropDelay01;
tpd_clk_pulse_posedge : VitalDelayType01 := DefPropDelay01
);
PORT (
clk,ena : IN STD_LOGIC;
pulse,cycle : OUT STD_LOGIC
);
ATTRIBUTE VITAL_Level0 OF stratixii_ram_pulse_generator:ENTITY IS TRUE;
END stratixii_ram_pulse_generator;
ARCHITECTURE pgen_arch OF stratixii_ram_pulse_generator IS
ATTRIBUTE VITAL_Level0 OF pgen_arch:ARCHITECTURE IS TRUE;
SIGNAL clk_ipd,ena_ipd : STD_LOGIC;
SIGNAL state : STD_LOGIC;
BEGIN
WireDelay : BLOCK
BEGIN
VitalWireDelay (clk_ipd, clk, tipd_clk);
VitalWireDelay (ena_ipd, ena, tipd_ena);
END BLOCK;
PROCESS (clk_ipd,state)
BEGIN
IF (state = '1' AND state'EVENT) THEN
state <= '0';
ELSIF (clk_ipd = '1' AND clk_ipd'EVENT AND ena_ipd = '1') THEN
state <= '1';
END IF;
END PROCESS;
PathDelay : PROCESS
VARIABLE pulse_VitalGlitchData : VitalGlitchDataType;
BEGIN
WAIT UNTIL state'EVENT;
VitalPathDelay01 (
OutSignal => pulse,
OutSignalName => "pulse",
OutTemp => state,
Paths => (0 => (clk_ipd'LAST_EVENT,tpd_clk_pulse_posedge,TRUE)),
GlitchData => pulse_VitalGlitchData,
Mode => DefGlitchMode,
XOn => DefXOnChecks,
MsgOn => DefMsgOnChecks
);
END PROCESS;
cycle <= clk_ipd;
END pgen_arch;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.VITAL_Timing.all;
USE IEEE.VITAL_Primitives.all;
USE work.stratixii_atom_pack.all;
USE work.stratixii_ram_register;
USE work.stratixii_ram_pulse_generator;
ENTITY stratixii_ram_block IS
GENERIC (
-- -------- GLOBAL PARAMETERS ---------
operation_mode : STRING := "single_port";
mixed_port_feed_through_mode : STRING := "dont_care";
ram_block_type : STRING := "auto";
logical_ram_name : STRING := "ram_name";
init_file : STRING := "init_file.hex";
init_file_layout : STRING := "none";
data_interleave_width_in_bits : INTEGER := 1;
data_interleave_offset_in_bits : INTEGER := 1;
port_a_logical_ram_depth : INTEGER := 0;
port_a_logical_ram_width : INTEGER := 0;
port_a_first_address : INTEGER := 0;
port_a_last_address : INTEGER := 0;
port_a_first_bit_number : INTEGER := 0;
port_a_data_in_clear : STRING := "none";
port_a_address_clear : STRING := "none";
port_a_write_enable_clear : STRING := "none";
port_a_data_out_clear : STRING := "none";
port_a_byte_enable_clear : STRING := "none";
port_a_data_in_clock : STRING := "clock0";
port_a_address_clock : STRING := "clock0";
port_a_write_enable_clock : STRING := "clock0";
port_a_byte_enable_clock : STRING := "clock0";
port_a_data_out_clock : STRING := "none";
port_a_data_width : INTEGER := 1;
port_a_address_width : INTEGER := 1;
port_a_byte_enable_mask_width : INTEGER := 1;
port_b_logical_ram_depth : INTEGER := 0;
port_b_logical_ram_width : INTEGER := 0;
port_b_first_address : INTEGER := 0;
port_b_last_address : INTEGER := 0;
port_b_first_bit_number : INTEGER := 0;
port_b_data_in_clear : STRING := "none";
port_b_address_clear : STRING := "none";
port_b_read_enable_write_enable_clear: STRING := "none";
port_b_byte_enable_clear : STRING := "none";
port_b_data_out_clear : STRING := "none";
port_b_data_in_clock : STRING := "clock0";
port_b_address_clock : STRING := "clock0";
port_b_read_enable_write_enable_clock: STRING := "clock0";
port_b_byte_enable_clock : STRING := "none";
port_b_data_out_clock : STRING := "none";
port_b_data_width : INTEGER := 1;
port_b_address_width : INTEGER := 1;
port_b_byte_enable_mask_width : INTEGER := 1;
power_up_uninitialized : STRING := "false";
port_b_disable_ce_on_output_registers : STRING := "off";
port_b_disable_ce_on_input_registers : STRING := "off";
port_b_byte_size : INTEGER := 0;
port_a_disable_ce_on_output_registers : STRING := "off";
port_a_disable_ce_on_input_registers : STRING := "off";
port_a_byte_size : INTEGER := 0;
lpm_type : string := "stratixii_ram_block";
lpm_hint : string := "true";
connectivity_checking : string := "off";
mem_init0 : BIT_VECTOR := X"0";
mem_init1 : BIT_VECTOR := X"0"
);
-- -------- PORT DECLARATIONS ---------
PORT (
portadatain : IN STD_LOGIC_VECTOR(port_a_data_width - 1 DOWNTO 0) := (OTHERS => '0');
portaaddr : IN STD_LOGIC_VECTOR(port_a_address_width - 1 DOWNTO 0) := (OTHERS => '0');
portawe : IN STD_LOGIC := '0';
portbdatain : IN STD_LOGIC_VECTOR(port_b_data_width - 1 DOWNTO 0) := (OTHERS => '0');
portbaddr : IN STD_LOGIC_VECTOR(port_b_address_width - 1 DOWNTO 0) := (OTHERS => '0');
portbrewe : IN STD_LOGIC := '0';
clk0 : IN STD_LOGIC := '0';
clk1 : IN STD_LOGIC := '0';
ena0 : IN STD_LOGIC := '1';
ena1 : IN STD_LOGIC := '1';
clr0 : IN STD_LOGIC := '0';
clr1 : IN STD_LOGIC := '0';
portabyteenamasks : IN STD_LOGIC_VECTOR(port_a_byte_enable_mask_width - 1 DOWNTO 0) := (OTHERS => '1');
portbbyteenamasks : IN STD_LOGIC_VECTOR(port_b_byte_enable_mask_width - 1 DOWNTO 0) := (OTHERS => '1');
devclrn : IN STD_LOGIC := '1';
devpor : IN STD_LOGIC := '1';
portaaddrstall : IN STD_LOGIC := '0';
portbaddrstall : IN STD_LOGIC := '0';
portadataout : OUT STD_LOGIC_VECTOR(port_a_data_width - 1 DOWNTO 0);
portbdataout : OUT STD_LOGIC_VECTOR(port_b_data_width - 1 DOWNTO 0)
);
END stratixii_ram_block;
ARCHITECTURE block_arch OF stratixii_ram_block IS
COMPONENT stratixii_ram_pulse_generator
PORT (
clk : IN STD_LOGIC;
ena : IN STD_LOGIC;
pulse : OUT STD_LOGIC;
cycle : OUT STD_LOGIC
);
END COMPONENT;
COMPONENT stratixii_ram_register
GENERIC (
preset : STD_LOGIC := '0';
width : integer := 1
);
PORT (
d : IN STD_LOGIC_VECTOR(width - 1 DOWNTO 0);
clk : IN STD_LOGIC;
aclr : IN STD_LOGIC;
devclrn : IN STD_LOGIC;
devpor : IN STD_LOGIC;
ena : IN STD_LOGIC;
stall : IN STD_LOGIC;
q : OUT STD_LOGIC_VECTOR(width - 1 DOWNTO 0);
aclrout : OUT STD_LOGIC
);
END COMPONENT;
FUNCTION cond (condition : BOOLEAN;CONSTANT a,b : INTEGER) RETURN INTEGER IS
VARIABLE c: INTEGER;
BEGIN
IF (condition) THEN c := a; ELSE c := b; END IF;
RETURN c;
END;
SUBTYPE port_type IS BOOLEAN;
CONSTANT primary : port_type := TRUE;
CONSTANT secondary : port_type := FALSE;
CONSTANT primary_port_is_a : BOOLEAN := (port_b_data_width <= port_a_data_width);
CONSTANT primary_port_is_b : BOOLEAN := NOT primary_port_is_a;
CONSTANT mode_is_rom : BOOLEAN := (operation_mode = "rom");
CONSTANT mode_is_sp : BOOLEAN := (operation_mode = "single_port");
CONSTANT mode_is_dp : BOOLEAN := (operation_mode = "dual_port");
CONSTANT mode_is_bdp : BOOLEAN := (operation_mode = "bidir_dual_port");
CONSTANT wired_mode : BOOLEAN := (port_a_address_width = port_b_address_width) AND (port_a_address_width = 1)
AND (port_a_data_width /= port_b_data_width);
CONSTANT num_cols : INTEGER := cond(mode_is_rom OR mode_is_sp,1,
cond(wired_mode,2,2 ** (ABS(port_b_address_width - port_a_address_width))));
CONSTANT data_width : INTEGER := cond(primary_port_is_a,port_a_data_width,port_b_data_width);
CONSTANT data_unit_width : INTEGER := cond(mode_is_rom OR mode_is_sp OR primary_port_is_b,port_a_data_width,port_b_data_width);
CONSTANT address_unit_width : INTEGER := cond(mode_is_rom OR mode_is_sp OR primary_port_is_a,port_a_address_width,port_b_address_width);
CONSTANT address_width : INTEGER := cond(mode_is_rom OR mode_is_sp OR primary_port_is_b,port_a_address_width,port_b_address_width);
CONSTANT byte_size_a : INTEGER := port_a_data_width / port_a_byte_enable_mask_width;
CONSTANT byte_size_b : INTEGER := port_b_data_width / port_b_byte_enable_mask_width;
CONSTANT out_a_is_reg : BOOLEAN := (port_a_data_out_clock /= "none" AND port_a_data_out_clock /= "UNUSED");
CONSTANT out_b_is_reg : BOOLEAN := (port_b_data_out_clock /= "none" AND port_b_data_out_clock /= "UNUSED");
CONSTANT bytes_a_disabled : STD_LOGIC_VECTOR(port_a_byte_enable_mask_width - 1 DOWNTO 0) := (OTHERS => '0');
CONSTANT bytes_b_disabled : STD_LOGIC_VECTOR(port_b_byte_enable_mask_width - 1 DOWNTO 0) := (OTHERS => '0');
CONSTANT ram_type : BOOLEAN := (ram_block_type = "M-RAM" OR ram_block_type = "m-ram" OR ram_block_type = "MegaRAM" OR
(ram_block_type = "auto" AND mixed_port_feed_through_mode = "dont_care" AND port_b_read_enable_write_enable_clock = "clock0"));
TYPE bool_to_std_logic_map IS ARRAY(TRUE DOWNTO FALSE) OF STD_LOGIC;
CONSTANT bool_to_std_logic : bool_to_std_logic_map := ('1','0');
-- -------- internal signals ---------
-- clock / clock enable
SIGNAL clk_a_in,clk_b_in : STD_LOGIC;
SIGNAL clk_a_byteena,clk_b_byteena : STD_LOGIC;
SIGNAL clk_a_out,clk_b_out : STD_LOGIC;
SIGNAL clkena_a_out,clkena_b_out : STD_LOGIC;
SIGNAL write_cycle_a,write_cycle_b : STD_LOGIC;
-- asynch clear
TYPE clear_mode_type IS ARRAY (port_type'HIGH DOWNTO port_type'LOW) OF BOOLEAN;
TYPE clear_vec_type IS ARRAY (port_type'HIGH DOWNTO port_type'LOW) OF STD_LOGIC;
SIGNAL datain_a_clr,datain_b_clr : STD_LOGIC;
SIGNAL dataout_a_clr,dataout_b_clr : STD_LOGIC;
SIGNAL addr_a_clr,addr_b_clr : STD_LOGIC;
SIGNAL byteena_a_clr,byteena_b_clr : STD_LOGIC;
SIGNAL we_a_clr,rewe_b_clr : STD_LOGIC;
SIGNAL datain_a_clr_in,datain_b_clr_in : STD_LOGIC;
SIGNAL addr_a_clr_in,addr_b_clr_in : STD_LOGIC;
SIGNAL byteena_a_clr_in,byteena_b_clr_in : STD_LOGIC;
SIGNAL we_a_clr_in,rewe_b_clr_in : STD_LOGIC;
SIGNAL mem_invalidate,mem_invalidate_loc,read_latch_invalidate : clear_mode_type;
SIGNAL clear_asserted_during_write : clear_vec_type;
SUBTYPE one_bit_bus_type IS STD_LOGIC_VECTOR(0 DOWNTO 0);
-- port A registers
SIGNAL we_a_reg : STD_LOGIC;
SIGNAL we_a_reg_in,we_a_reg_out : one_bit_bus_type;
SIGNAL addr_a_reg : STD_LOGIC_VECTOR(port_a_address_width - 1 DOWNTO 0);
SIGNAL datain_a_reg : STD_LOGIC_VECTOR(port_a_data_width - 1 DOWNTO 0);
SIGNAL dataout_a_reg : STD_LOGIC_VECTOR(port_a_data_width - 1 DOWNTO 0);
SIGNAL dataout_a : STD_LOGIC_VECTOR(port_a_data_width - 1 DOWNTO 0);
SIGNAL byteena_a_reg : STD_LOGIC_VECTOR(port_a_byte_enable_mask_width- 1 DOWNTO 0);
-- port B registers
SIGNAL rewe_b_reg : STD_LOGIC;
SIGNAL rewe_b_reg_in,rewe_b_reg_out : one_bit_bus_type;
SIGNAL addr_b_reg : STD_LOGIC_VECTOR(port_b_address_width - 1 DOWNTO 0);
SIGNAL datain_b_reg : STD_LOGIC_VECTOR(port_b_data_width - 1 DOWNTO 0);
SIGNAL dataout_b_reg : STD_LOGIC_VECTOR(port_b_data_width - 1 DOWNTO 0);
SIGNAL dataout_b : STD_LOGIC_VECTOR(port_b_data_width - 1 DOWNTO 0);
SIGNAL byteena_b_reg : STD_LOGIC_VECTOR(port_b_byte_enable_mask_width- 1 DOWNTO 0);
-- pulses
TYPE pulse_vec IS ARRAY (port_type'HIGH DOWNTO port_type'LOW) OF STD_LOGIC;
SIGNAL write_pulse,read_pulse,read_pulse_feedthru : pulse_vec;
SIGNAL wpgen_a_clk,wpgen_a_clkena,wpgen_b_clk,wpgen_b_clkena : STD_LOGIC;
SIGNAL rpgen_a_clkena,rpgen_b_clkena : STD_LOGIC;
SIGNAL ftpgen_a_clkena,ftpgen_b_clkena : STD_LOGIC;
-- registered address
SIGNAL addr_prime_reg,addr_sec_reg : INTEGER;
-- input/output
SIGNAL datain_prime_reg,dataout_prime : STD_LOGIC_VECTOR(data_width - 1 DOWNTO 0);
SIGNAL datain_sec_reg,dataout_sec : STD_LOGIC_VECTOR(data_unit_width - 1 DOWNTO 0);
-- overlapping location write
SIGNAL dual_write : BOOLEAN;
-- memory core
SUBTYPE mem_word_type IS STD_LOGIC_VECTOR (data_width - 1 DOWNTO 0);
SUBTYPE mem_col_type IS STD_LOGIC_VECTOR (data_unit_width - 1 DOWNTO 0);
TYPE mem_row_type IS ARRAY (num_cols - 1 DOWNTO 0) OF mem_col_type;
TYPE mem_type IS ARRAY ((2 ** address_unit_width) - 1 DOWNTO 0) OF mem_row_type;
SIGNAL mem : mem_type;
SIGNAL init_mem : BOOLEAN := FALSE;
CONSTANT mem_x : mem_type := (OTHERS => (OTHERS => (OTHERS => 'X')));
CONSTANT row_x : mem_row_type := (OTHERS => (OTHERS => 'X'));
CONSTANT col_x : mem_col_type := (OTHERS => 'X');
SIGNAL mem_data : mem_row_type;
SIGNAL mem_unit_data : mem_col_type;
-- latches
TYPE read_latch_rec IS RECORD
prime : mem_row_type;
sec : mem_col_type;
END RECORD;
SIGNAL read_latch : read_latch_rec;
-- (row,column) coordinates
SIGNAL row_sec,col_sec : INTEGER;
-- byte enable
TYPE mask_type IS (normal,inverse);
TYPE mask_prime_type IS ARRAY(mask_type'HIGH DOWNTO mask_type'LOW) OF mem_word_type;
TYPE mask_sec_type IS ARRAY(mask_type'HIGH DOWNTO mask_type'LOW) OF mem_col_type;
TYPE mask_rec IS RECORD
prime : mask_prime_type;
sec : mask_sec_type;
END RECORD;
SIGNAL mask_vector : mask_rec;
SIGNAL mask_vector_common : mem_col_type;
FUNCTION get_mask(
b_ena : IN STD_LOGIC_VECTOR;
mode : port_type;
CONSTANT b_ena_width ,byte_size: INTEGER
) RETURN mask_rec IS
VARIABLE l : INTEGER;
VARIABLE mask : mask_rec := (
(normal => (OTHERS => '0'),inverse => (OTHERS => 'X')),
(normal => (OTHERS => '0'),inverse => (OTHERS => 'X'))
);
BEGIN
FOR l in 0 TO b_ena_width - 1 LOOP
IF (b_ena(l) = '0') THEN
IF (mode = primary) THEN
mask.prime(normal) ((l+1)*byte_size - 1 DOWNTO l*byte_size) := (OTHERS => 'X');
mask.prime(inverse)((l+1)*byte_size - 1 DOWNTO l*byte_size) := (OTHERS => '0');
ELSE
mask.sec(normal) ((l+1)*byte_size - 1 DOWNTO l*byte_size) := (OTHERS => 'X');
mask.sec(inverse)((l+1)*byte_size - 1 DOWNTO l*byte_size) := (OTHERS => '0');
END IF;
ELSIF (b_ena(l) = 'X' OR b_ena(l) = 'U') THEN
IF (mode = primary) THEN
mask.prime(normal) ((l+1)*byte_size - 1 DOWNTO l*byte_size) := (OTHERS => 'X');
ELSE
mask.sec(normal) ((l+1)*byte_size - 1 DOWNTO l*byte_size) := (OTHERS => 'X');
END IF;
END IF;
END LOOP;
RETURN mask;
END get_mask;
-- port active for read/write
SIGNAL active_a_in_vec,active_b_in_vec,active_a_out,active_b_out : one_bit_bus_type;
SIGNAL active_a_in,active_b_in : STD_LOGIC;
SIGNAL active_a,active_write_a : BOOLEAN;
SIGNAL active_b,active_write_b : BOOLEAN;
SIGNAL wire_vcc : STD_LOGIC := '1';
SIGNAL wire_gnd : STD_LOGIC := '0';
BEGIN
-- memory initialization
init_mem <= TRUE;
-- -------- core logic ---------------
clk_a_in <= clk0;
clk_a_byteena <= '0' WHEN (port_a_byte_enable_clock = "none" OR port_a_byte_enable_clock = "UNUSED") ELSE clk_a_in;
clk_a_out <= '0' WHEN (port_a_data_out_clock = "none" OR port_a_data_out_clock = "UNUSED") ELSE
clk0 WHEN (port_a_data_out_clock = "clock0") ELSE clk1;
clk_b_in <= clk0 WHEN (port_b_read_enable_write_enable_clock = "clock0") ELSE clk1;
clk_b_byteena <= '0' WHEN (port_b_byte_enable_clock = "none" OR port_b_byte_enable_clock = "UNUSED") ELSE
clk0 WHEN (port_b_byte_enable_clock = "clock0") ELSE clk1;
clk_b_out <= '0' WHEN (port_b_data_out_clock = "none" OR port_b_data_out_clock = "UNUSED") ELSE
clk0 WHEN (port_b_data_out_clock = "clock0") ELSE clk1;
addr_a_clr_in <= '0' WHEN (port_a_address_clear = "none" OR port_a_address_clear = "UNUSED") ELSE clr0;
addr_b_clr_in <= '0' WHEN (port_b_address_clear = "none" OR port_b_address_clear = "UNUSED") ELSE
clr0 WHEN (port_b_address_clear = "clear0") ELSE clr1;
datain_a_clr_in <= '0' WHEN (port_a_data_in_clear = "none" OR port_a_data_in_clear = "UNUSED") ELSE clr0;
datain_b_clr_in <= '0' WHEN (port_b_data_in_clear = "none" OR port_b_data_in_clear = "UNUSED") ELSE
clr0 WHEN (port_b_data_in_clear = "clear0") ELSE clr1;
dataout_a_clr <= '0' WHEN (port_a_data_out_clear = "none" OR port_a_data_out_clear = "UNUSED") ELSE
clr0 WHEN (port_a_data_out_clear = "clear0") ELSE clr1;
dataout_b_clr <= '0' WHEN (port_b_data_out_clear = "none" OR port_b_data_out_clear = "UNUSED") ELSE
clr0 WHEN (port_b_data_out_clear = "clear0") ELSE clr1;
byteena_a_clr_in <= '0' WHEN (port_a_byte_enable_clear = "none" OR port_a_byte_enable_clear = "UNUSED") ELSE clr0;
byteena_b_clr_in <= '0' WHEN (port_b_byte_enable_clear = "none" OR port_b_byte_enable_clear = "UNUSED") ELSE
clr0 WHEN (port_b_byte_enable_clear = "clear0") ELSE clr1;
we_a_clr_in <= '0' WHEN (port_a_write_enable_clear = "none" OR port_a_write_enable_clear = "UNUSED") ELSE clr0;
rewe_b_clr_in <= '0' WHEN (port_b_read_enable_write_enable_clear = "none" OR port_b_read_enable_write_enable_clear = "UNUSED") ELSE
clr0 WHEN (port_b_read_enable_write_enable_clear = "clear0") ELSE clr1;
active_a_in <= '1' WHEN (port_a_disable_ce_on_input_registers = "on") ELSE ena0;
active_b_in <= '1' WHEN (port_b_disable_ce_on_input_registers = "on") ELSE
ena0 WHEN (port_b_read_enable_write_enable_clock = "clock0") ELSE ena1;
-- A port active
active_a_in_vec(0) <= active_a_in;
active_port_a : stratixii_ram_register
GENERIC MAP ( width => 1 )
PORT MAP (
d => active_a_in_vec,
clk => clk_a_in,
aclr => wire_gnd,
devclrn => wire_vcc,devpor => wire_vcc,
ena => wire_vcc,
stall => wire_gnd,
q => active_a_out
);
active_a <= (active_a_out(0) = '1');
active_write_a <= active_a AND (byteena_a_reg /= bytes_a_disabled);
-- B port active
active_b_in_vec(0) <= active_b_in;
active_port_b : stratixii_ram_register
GENERIC MAP ( width => 1 )
PORT MAP (
d => active_b_in_vec,
clk => clk_b_in,
aclr => wire_gnd,
devclrn => wire_vcc,devpor => wire_vcc,
stall => wire_gnd,
ena => wire_vcc,
q => active_b_out
);
active_b <= (active_b_out(0) = '1');
active_write_b <= active_b AND (byteena_b_reg /= bytes_b_disabled);
-- ------ A input registers
-- write enable
we_a_reg_in(0) <= '0' WHEN mode_is_rom ELSE portawe;
we_a_register : stratixii_ram_register
GENERIC MAP ( width => 1 )
PORT MAP (
d => we_a_reg_in,
clk => clk_a_in,
aclr => we_a_clr_in,
devclrn => devclrn,
devpor => devpor,
stall => wire_gnd,
ena => active_a_in,
q => we_a_reg_out,
aclrout => we_a_clr
);
we_a_reg <= we_a_reg_out(0);
-- address
addr_a_register : stratixii_ram_register
GENERIC MAP ( width => port_a_address_width )
PORT MAP (
d => portaaddr,
clk => clk_a_in,
aclr => addr_a_clr_in,
devclrn => devclrn,
devpor => devpor,
stall => portaaddrstall,
ena => active_a_in,
q => addr_a_reg,
aclrout => addr_a_clr
);
-- data
datain_a_register : stratixii_ram_register
GENERIC MAP ( width => port_a_data_width )
PORT MAP (
d => portadatain,
clk => clk_a_in,
aclr => datain_a_clr_in,
devclrn => devclrn,
devpor => devpor,
stall => wire_gnd,
ena => active_a_in,
q => datain_a_reg,
aclrout => datain_a_clr
);
-- byte enable
byteena_a_register : stratixii_ram_register
GENERIC MAP (
width => port_a_byte_enable_mask_width,
preset => '1'
)
PORT MAP (
d => portabyteenamasks,
clk => clk_a_byteena,
aclr => byteena_a_clr_in,
devclrn => devclrn,
devpor => devpor,
stall => wire_gnd,
ena => active_a_in,
q => byteena_a_reg,
aclrout => byteena_a_clr
);
-- ------ B input registers
-- read/write enable
rewe_b_reg_in(0) <= portbrewe;
rewe_b_register : stratixii_ram_register
GENERIC MAP (
width => 1,
preset => bool_to_std_logic(mode_is_dp)
)
PORT MAP (
d => rewe_b_reg_in,
clk => clk_b_in,
aclr => rewe_b_clr_in,
devclrn => devclrn,
devpor => devpor,
stall => wire_gnd,
ena => active_b_in,
q => rewe_b_reg_out,
aclrout => rewe_b_clr
);
rewe_b_reg <= rewe_b_reg_out(0);
-- address
addr_b_register : stratixii_ram_register
GENERIC MAP ( width => port_b_address_width )
PORT MAP (
d => portbaddr,
clk => clk_b_in,
aclr => addr_b_clr_in,
devclrn => devclrn,
devpor => devpor,
stall => portbaddrstall,
ena => active_b_in,
q => addr_b_reg,
aclrout => addr_b_clr
);
-- data
datain_b_register : stratixii_ram_register
GENERIC MAP ( width => port_b_data_width )
PORT MAP (
d => portbdatain,
clk => clk_b_in,
aclr => datain_b_clr_in,
devclrn => devclrn,
devpor => devpor,
stall => wire_gnd,
ena => active_b_in,
q => datain_b_reg,
aclrout => datain_b_clr
);
-- byte enable
byteena_b_register : stratixii_ram_register
GENERIC MAP (
width => port_b_byte_enable_mask_width,
preset => '1'
)
PORT MAP (
d => portbbyteenamasks,
clk => clk_b_byteena,
aclr => byteena_b_clr_in,
devclrn => devclrn,
devpor => devpor,
stall => wire_gnd,
ena => active_b_in,
q => byteena_b_reg,
aclrout => byteena_b_clr
);
datain_prime_reg <= datain_a_reg WHEN primary_port_is_a ELSE datain_b_reg;
addr_prime_reg <= alt_conv_integer(addr_a_reg) WHEN primary_port_is_a ELSE alt_conv_integer(addr_b_reg);
datain_sec_reg <= (OTHERS => 'U') WHEN (mode_is_rom OR mode_is_sp) ELSE
datain_b_reg WHEN primary_port_is_a ELSE datain_a_reg;
addr_sec_reg <= alt_conv_integer(addr_b_reg) WHEN primary_port_is_a ELSE alt_conv_integer(addr_a_reg);
-- Write pulse generation
wpgen_a_clk <= clk_a_in WHEN ram_type ELSE (NOT clk_a_in);
wpgen_a_clkena <= '1' WHEN (active_write_a AND (we_a_reg = '1')) ELSE '0';
wpgen_a : stratixii_ram_pulse_generator
PORT MAP (
clk => wpgen_a_clk,
ena => wpgen_a_clkena,
pulse => write_pulse(primary_port_is_a),
cycle => write_cycle_a
);
wpgen_b_clk <= clk_b_in WHEN ram_type ELSE (NOT clk_b_in);
wpgen_b_clkena <= '1' WHEN (active_write_b AND mode_is_bdp AND (rewe_b_reg = '1')) ELSE '0';
wpgen_b : stratixii_ram_pulse_generator
PORT MAP (
clk => wpgen_b_clk,
ena => wpgen_b_clkena,
pulse => write_pulse(primary_port_is_b),
cycle => write_cycle_b
);
-- Read pulse generation
rpgen_a_clkena <= '1' WHEN (active_a AND (we_a_reg = '0')) ELSE '0';
rpgen_a : stratixii_ram_pulse_generator
PORT MAP (
clk => clk_a_in,
ena => rpgen_a_clkena,
pulse => read_pulse(primary_port_is_a)
);
rpgen_b_clkena <= '1' WHEN (active_b AND mode_is_dp AND (rewe_b_reg = '1')) OR
(active_b AND mode_is_bdp AND (rewe_b_reg = '0'))
ELSE '0';
rpgen_b : stratixii_ram_pulse_generator
PORT MAP (
clk => clk_b_in,
ena => rpgen_b_clkena,
pulse => read_pulse(primary_port_is_b)
);
-- Create internal masks for byte enable processing
mask_create : PROCESS (byteena_a_reg,byteena_b_reg)
VARIABLE mask : mask_rec;
BEGIN
IF (byteena_a_reg'EVENT) THEN
mask := get_mask(byteena_a_reg,primary_port_is_a,port_a_byte_enable_mask_width,byte_size_a);
IF (primary_port_is_a) THEN
mask_vector.prime <= mask.prime;
ELSE
mask_vector.sec <= mask.sec;
END IF;
END IF;
IF (byteena_b_reg'EVENT) THEN
mask := get_mask(byteena_b_reg,primary_port_is_b,port_b_byte_enable_mask_width,byte_size_b);
IF (primary_port_is_b) THEN
mask_vector.prime <= mask.prime;
ELSE
mask_vector.sec <= mask.sec;
END IF;
END IF;
END PROCESS mask_create;
-- (row,col) coordinates
row_sec <= addr_sec_reg / num_cols;
col_sec <= addr_sec_reg mod num_cols;
mem_rw : PROCESS (init_mem,
write_pulse,read_pulse,read_pulse_feedthru,
mem_invalidate,mem_invalidate_loc,read_latch_invalidate)
-- mem init
TYPE rw_type IS ARRAY (port_type'HIGH DOWNTO port_type'LOW) OF BOOLEAN;
VARIABLE addr_range_init,row,col,index : INTEGER;
VARIABLE mem_init_std : STD_LOGIC_VECTOR((port_a_last_address - port_a_first_address + 1)*port_a_data_width - 1 DOWNTO 0);
VARIABLE mem_val : mem_type;
-- read/write
VARIABLE mem_data_p : mem_row_type;
VARIABLE row_prime,col_prime : INTEGER;
VARIABLE access_same_location : BOOLEAN;
VARIABLE read_during_write : rw_type;
BEGIN
read_during_write := (FALSE,FALSE);
-- Memory initialization
IF (init_mem'EVENT) THEN
-- Initialize output latches to 0
IF (primary_port_is_a) THEN
dataout_prime <= (OTHERS => '0');
IF (mode_is_dp OR mode_is_bdp) THEN dataout_sec <= (OTHERS => '0'); END IF;
ELSE
dataout_sec <= (OTHERS => '0');
IF (mode_is_dp OR mode_is_bdp) THEN dataout_prime <= (OTHERS => '0'); END IF;
END IF;
IF (power_up_uninitialized = "false" AND (NOT ram_type)) THEN
mem_val := (OTHERS => (OTHERS => (OTHERS => '0')));
END IF;
IF (primary_port_is_a) THEN
addr_range_init := port_a_last_address - port_a_first_address + 1;
ELSE
addr_range_init := port_b_last_address - port_b_first_address + 1;
END IF;
IF (init_file_layout = "port_a" OR init_file_layout = "port_b") THEN
mem_init_std := to_stdlogicvector(mem_init1 & mem_init0)((port_a_last_address - port_a_first_address + 1)*port_a_data_width - 1 DOWNTO 0);
FOR row IN 0 TO addr_range_init - 1 LOOP
FOR col IN 0 to num_cols - 1 LOOP
index := row * data_width;
mem_val(row)(col) := mem_init_std(index + (col+1)*data_unit_width -1 DOWNTO
index + col*data_unit_width);
END LOOP;
END LOOP;
END IF;
mem <= mem_val;
END IF;
access_same_location := (mode_is_dp OR mode_is_bdp) AND (addr_prime_reg = row_sec);
-- Write stage 1 : X to buffer
-- Write stage 2 : actual data to memory
IF (write_pulse(primary)'EVENT) THEN
IF (write_pulse(primary) = '1') THEN
mem_data_p := mem(addr_prime_reg);
FOR i IN 0 TO num_cols - 1 LOOP
mem_data_p(i) := mem_data_p(i) XOR
mask_vector.prime(inverse)((i + 1)*data_unit_width - 1 DOWNTO i*data_unit_width);
END LOOP;
read_during_write(secondary) := (access_same_location AND read_pulse(secondary)'EVENT AND read_pulse(secondary) = '1');
IF (read_during_write(secondary)) THEN
read_latch.sec <= mem_data_p(col_sec);
ELSE
mem_data <= mem_data_p;
END IF;
ELSIF (clear_asserted_during_write(primary) /= '1') THEN
FOR i IN 0 TO data_width - 1 LOOP
IF (mask_vector.prime(normal)(i) = '0') THEN
mem(addr_prime_reg)(i / data_unit_width)(i mod data_unit_width) <= datain_prime_reg(i);
ELSIF (mask_vector.prime(inverse)(i) = 'X') THEN
mem(addr_prime_reg)(i / data_unit_width)(i mod data_unit_width) <= 'X';
END IF;
END LOOP;
END IF;
END IF;
IF (write_pulse(secondary)'EVENT) THEN
IF (write_pulse(secondary) = '1') THEN
read_during_write(primary) := (access_same_location AND read_pulse(primary)'EVENT AND read_pulse(primary) = '1');
IF (read_during_write(primary)) THEN
read_latch.prime <= mem(addr_prime_reg);
read_latch.prime(col_sec) <= mem(row_sec)(col_sec) XOR mask_vector.sec(inverse);
ELSE
mem_unit_data <= mem(row_sec)(col_sec) XOR mask_vector.sec(inverse);
END IF;
IF (access_same_location AND write_pulse(primary)'EVENT AND write_pulse(primary) = '1') THEN
mask_vector_common <=
mask_vector.prime(inverse)(((col_sec + 1)* data_unit_width - 1) DOWNTO col_sec*data_unit_width) AND
mask_vector.sec(inverse);
dual_write <= TRUE;
END IF;
ELSIF (clear_asserted_during_write(secondary) /= '1') THEN
FOR i IN 0 TO data_unit_width - 1 LOOP
IF (mask_vector.sec(normal)(i) = '0') THEN
mem(row_sec)(col_sec)(i) <= datain_sec_reg(i);
ELSIF (mask_vector.sec(inverse)(i) = 'X') THEN
mem(row_sec)(col_sec)(i) <= 'X';
END IF;
END LOOP;
END IF;
END IF;
-- Simultaneous write
IF (dual_write AND write_pulse = "00") THEN
mem(row_sec)(col_sec) <= mem(row_sec)(col_sec) XOR mask_vector_common;
dual_write <= FALSE;
END IF;
-- Read stage 1 : read data
-- Read stage 2 : send data to output
IF ((NOT read_during_write(primary)) AND read_pulse(primary)'EVENT) THEN
IF (read_pulse(primary) = '1') THEN
read_latch.prime <= mem(addr_prime_reg);
IF (access_same_location AND write_pulse(secondary) = '1') THEN
read_latch.prime(col_sec) <= mem_unit_data;
END IF;
ELSE
FOR i IN 0 TO data_width - 1 LOOP
row_prime := i / data_unit_width; col_prime := i mod data_unit_width;
dataout_prime(i) <= read_latch.prime(row_prime)(col_prime);
END LOOP;
END IF;
END IF;
IF ((NOT read_during_write(secondary)) AND read_pulse(secondary)'EVENT) THEN
IF (read_pulse(secondary) = '1') THEN
IF (access_same_location AND write_pulse(primary) = '1') THEN
read_latch.sec <= mem_data(col_sec);
ELSE
read_latch.sec <= mem(row_sec)(col_sec);
END IF;
ELSE
dataout_sec <= read_latch.sec;
END IF;
END IF;
-- Same port feed thru
IF (read_pulse_feedthru(primary)'EVENT AND read_pulse_feedthru(primary) = '0') THEN
dataout_prime <= datain_prime_reg XOR mask_vector.prime(normal);
END IF;
IF (read_pulse_feedthru(secondary)'EVENT AND read_pulse_feedthru(secondary) = '0') THEN
dataout_sec <= datain_sec_reg XOR mask_vector.sec(normal);
END IF;
-- Async clear
IF (mem_invalidate'EVENT) THEN
IF (mem_invalidate(primary) = TRUE OR mem_invalidate(secondary) = TRUE) THEN
mem <= mem_x;
END IF;
END IF;
IF (mem_invalidate_loc'EVENT) THEN
IF (mem_invalidate_loc(primary)) THEN mem(addr_prime_reg) <= row_x; END IF;
IF (mem_invalidate_loc(secondary)) THEN mem(row_sec)(col_sec) <= col_x; END IF;
END IF;
IF (read_latch_invalidate'EVENT) THEN
IF (read_latch_invalidate(primary)) THEN read_latch.prime <= row_x; END IF;
IF (read_latch_invalidate(secondary)) THEN read_latch.sec <= col_x; END IF;
END IF;
END PROCESS mem_rw;
-- Same port feed through
ftpgen_a_clkena <= '1' WHEN (active_a AND (NOT mode_is_dp) AND (we_a_reg = '1')) ELSE '0';
ftpgen_a : stratixii_ram_pulse_generator
PORT MAP (
clk => clk_a_in,
ena => ftpgen_a_clkena,
pulse => read_pulse_feedthru(primary_port_is_a)
);
ftpgen_b_clkena <= '1' WHEN (active_b AND mode_is_bdp AND (rewe_b_reg = '1')) ELSE '0';
ftpgen_b : stratixii_ram_pulse_generator
PORT MAP (
clk => clk_b_in,
ena => ftpgen_b_clkena,
pulse => read_pulse_feedthru(primary_port_is_b)
);
-- Asynch clear events
clear_a : PROCESS(addr_a_clr,we_a_clr,datain_a_clr)
BEGIN
IF (addr_a_clr'EVENT AND addr_a_clr = '1') THEN
clear_asserted_during_write(primary_port_is_a) <= write_pulse(primary_port_is_a);
IF (active_write_a AND (write_cycle_a = '1') AND (we_a_reg = '1')) THEN
mem_invalidate(primary_port_is_a) <= TRUE,FALSE AFTER 0.5 ns;
ELSIF (active_a AND we_a_reg = '1') THEN
read_latch_invalidate(primary_port_is_a) <= TRUE,FALSE AFTER 0.5 ns;
END IF;
END IF;
IF ((we_a_clr'EVENT AND we_a_clr = '1') OR (datain_a_clr'EVENT AND datain_a_clr = '1')) THEN
clear_asserted_during_write(primary_port_is_a) <= write_pulse(primary_port_is_a);
IF (active_write_a AND (write_cycle_a = '1') AND (we_a_reg = '1')) THEN
mem_invalidate_loc(primary_port_is_a) <= TRUE,FALSE AFTER 0.5 ns;
read_latch_invalidate(primary_port_is_a) <= TRUE,FALSE AFTER 0.5 ns;
END IF;
END IF;
END PROCESS clear_a;
clear_b : PROCESS(addr_b_clr,rewe_b_clr,datain_b_clr)
BEGIN
IF (addr_b_clr'EVENT AND addr_b_clr = '1') THEN
clear_asserted_during_write(primary_port_is_b) <= write_pulse(primary_port_is_b);
IF (mode_is_bdp AND active_write_b AND (write_cycle_b = '1') AND (rewe_b_reg = '1')) THEN
mem_invalidate(primary_port_is_b) <= TRUE,FALSE AFTER 0.5 ns;
ELSIF (active_b AND ((mode_is_dp AND rewe_b_reg = '1') OR (mode_is_bdp AND rewe_b_reg = '0'))) THEN
read_latch_invalidate(primary_port_is_b) <= TRUE,FALSE AFTER 0.5 ns;
END IF;
END IF;
IF ((rewe_b_clr'EVENT AND rewe_b_clr = '1') OR (datain_b_clr'EVENT AND datain_b_clr = '1')) THEN
clear_asserted_during_write(primary_port_is_b) <= write_pulse(primary_port_is_b);
IF (mode_is_bdp AND active_write_b AND (write_cycle_b = '1') AND (rewe_b_reg = '1')) THEN
mem_invalidate_loc(primary_port_is_b) <= TRUE,FALSE AFTER 0.5 ns;
read_latch_invalidate(primary_port_is_b) <= TRUE,FALSE AFTER 0.5 ns;
END IF;
END IF;
END PROCESS clear_b;
-- ------ Output registers
clkena_a_out <= '1' WHEN (port_a_disable_ce_on_output_registers = "on") ELSE
ena0 WHEN (port_a_data_out_clock = "clock0") ELSE ena1;
clkena_b_out <= '1' WHEN (port_b_disable_ce_on_output_registers = "on") ELSE
ena0 WHEN (port_b_data_out_clock = "clock0") ELSE ena1;
dataout_a <= dataout_prime WHEN primary_port_is_a ELSE dataout_sec;
dataout_b <= (OTHERS => 'U') WHEN (mode_is_rom OR mode_is_sp) ELSE
dataout_prime WHEN primary_port_is_b ELSE dataout_sec;
dataout_a_register : stratixii_ram_register
GENERIC MAP ( width => port_a_data_width )
PORT MAP (
d => dataout_a,
clk => clk_a_out,
aclr => dataout_a_clr,
devclrn => devclrn,
devpor => devpor,
stall => wire_gnd,
ena => clkena_a_out,
q => dataout_a_reg
);
dataout_b_register : stratixii_ram_register
GENERIC MAP ( width => port_b_data_width )
PORT MAP (
d => dataout_b,
clk => clk_b_out,
aclr => dataout_b_clr,
devclrn => devclrn,
devpor => devpor,
stall => wire_gnd,
ena => clkena_b_out,
q => dataout_b_reg
);
portadataout <= dataout_a_reg WHEN out_a_is_reg ELSE dataout_a;
portbdataout <= dataout_b_reg WHEN out_b_is_reg ELSE dataout_b;
END block_arch;
-------------------------------------------------------------------
--
-- Entity Name : stratixii_jtag
--
-- Description : StratixII JTAG VHDL Simulation model
--
-------------------------------------------------------------------
LIBRARY IEEE;
use IEEE.std_logic_1164.all;
use work.stratixii_atom_pack.all;
entity stratixii_jtag is
generic (
lpm_type : string := "stratixii_jtag"
);
port (tms : in std_logic;
tck : in std_logic;
tdi : in std_logic;
ntrst : in std_logic;
tdoutap : in std_logic;
tdouser : in std_logic;
tdo: out std_logic;
tmsutap: out std_logic;
tckutap: out std_logic;
tdiutap: out std_logic;
shiftuser: out std_logic;
clkdruser: out std_logic;
updateuser: out std_logic;
runidleuser: out std_logic;
usr1user: out std_logic);
end stratixii_jtag;
architecture architecture_jtag of stratixii_jtag is
begin
--process(tms, tck, tdi, ntrst, tdoutap, tdouser)
--begin
--
--end process;
end architecture_jtag;
-------------------------------------------------------------------
--
-- Entity Name : stratixii_crcblock
--
-- Description : StratixII CRCBLOCK VHDL Simulation model
--
-------------------------------------------------------------------
LIBRARY IEEE;
use IEEE.std_logic_1164.all;
use work.stratixii_atom_pack.all;
entity stratixii_crcblock is
generic (
oscillator_divider : integer := 1;
lpm_type : string := "stratixii_crcblock"
);
port (clk : in std_logic;
shiftnld : in std_logic;
ldsrc : in std_logic;
crcerror : out std_logic;
regout : out std_logic);
end stratixii_crcblock;
architecture architecture_crcblock of stratixii_crcblock is
begin
end architecture_crcblock;
-------------------------------------------------------------------
--
-- Entity Name : stratixii_asmiblock
--
-- Description : StratixIIII ASMIBLOCK VHDL Simulation model
--
-------------------------------------------------------------------
LIBRARY IEEE;
use IEEE.std_logic_1164.all;
use work.stratixii_atom_pack.all;
entity stratixii_asmiblock is
generic (
lpm_type : string := "stratixii_asmiblock"
);
port (dclkin : in std_logic;
scein : in std_logic;
sdoin : in std_logic;
oe : in std_logic;
data0out: out std_logic);
end stratixii_asmiblock;
architecture architecture_asmiblock of stratixii_asmiblock is
begin
--process(dclkin, scein, sdoin, oe)
--begin
--
--end process;
end architecture_asmiblock; -- end of stratixii_asmiblock
---------------------------------------------------------------------
--
-- Entity Name : stratixii_lcell_ff
--
-- Description : StratixII LCELL_FF VHDL simulation model
--
--
---------------------------------------------------------------------
LIBRARY IEEE;
use IEEE.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.stratixii_atom_pack.all;
use work.stratixii_and1;
entity stratixii_lcell_ff is
generic (
x_on_violation : string := "on";
lpm_type : string := "stratixii_lcell_ff";
tsetup_datain_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_adatasdata_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_sclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_datain_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_adatasdata_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_sclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_clk_regout_posedge : VitalDelayType01 := DefPropDelay01;
tpd_aclr_regout_posedge : VitalDelayType01 := DefPropDelay01;
tpd_aload_regout_posedge : VitalDelayType01 := DefPropDelay01;
tpd_adatasdata_regout: VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_datain : VitalDelayType01 := DefPropDelay01;
tipd_adatasdata : VitalDelayType01 := DefPropDelay01;
tipd_sclr : VitalDelayType01 := DefPropDelay01;
tipd_sload : VitalDelayType01 := DefPropDelay01;
tipd_aclr : VitalDelayType01 := DefPropDelay01;
tipd_aload : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks;
InstancePath: STRING := "*"
);
port (
datain : in std_logic := '0';
clk : in std_logic := '0';
aclr : in std_logic := '0';
aload : in std_logic := '0';
sclr : in std_logic := '0';
sload : in std_logic := '0';
ena : in std_logic := '1';
adatasdata : in std_logic := '0';
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
regout : out std_logic
);
attribute VITAL_LEVEL0 of stratixii_lcell_ff : entity is TRUE;
end stratixii_lcell_ff;
architecture vital_lcell_ff of stratixii_lcell_ff is
attribute VITAL_LEVEL0 of vital_lcell_ff : architecture is TRUE;
signal clk_ipd : std_logic;
signal datain_ipd : std_logic;
signal datain_dly : std_logic;
signal adatasdata_ipd : std_logic;
signal adatasdata_dly : std_logic;
signal adatasdata_dly1 : std_logic;
signal sclr_ipd : std_logic;
signal sload_ipd : std_logic;
signal aclr_ipd : std_logic;
signal aload_ipd : std_logic;
signal ena_ipd : std_logic;
component stratixii_and1
generic (XOn : Boolean := DefGlitchXOn;
MsgOn : Boolean := DefGlitchMsgOn;
tpd_IN1_Y : VitalDelayType01 := DefPropDelay01;
tipd_IN1 : VitalDelayType01 := DefPropDelay01
);
port (Y : out STD_LOGIC;
IN1 : in STD_LOGIC
);
end component;
begin
dataindelaybuffer: stratixii_and1
port map(IN1 => datain_ipd,
Y => datain_dly);
adatasdatadelaybuffer: stratixii_and1
port map(IN1 => adatasdata_ipd,
Y => adatasdata_dly);
adatasdatadelaybuffer1: stratixii_and1
port map(IN1 => adatasdata_dly,
Y => adatasdata_dly1);
---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
VitalWireDelay (clk_ipd, clk, tipd_clk);
VitalWireDelay (datain_ipd, datain, tipd_datain);
VitalWireDelay (adatasdata_ipd, adatasdata, tipd_adatasdata);
VitalWireDelay (sclr_ipd, sclr, tipd_sclr);
VitalWireDelay (sload_ipd, sload, tipd_sload);
VitalWireDelay (aclr_ipd, aclr, tipd_aclr);
VitalWireDelay (aload_ipd, aload, tipd_aload);
VitalWireDelay (ena_ipd, ena, tipd_ena);
end block;
VITALtiming : process (clk_ipd, datain_dly, adatasdata_dly1,
sclr_ipd, sload_ipd, aclr_ipd, aload_ipd,
ena_ipd, devclrn, devpor)
variable Tviol_datain_clk : std_ulogic := '0';
variable Tviol_adatasdata_clk : std_ulogic := '0';
variable Tviol_sclr_clk : std_ulogic := '0';
variable Tviol_sload_clk : std_ulogic := '0';
variable Tviol_ena_clk : std_ulogic := '0';
variable TimingData_datain_clk : VitalTimingDataType := VitalTimingDataInit;
variable TimingData_adatasdata_clk : VitalTimingDataType := VitalTimingDataInit;
variable TimingData_sclr_clk : VitalTimingDataType := VitalTimingDataInit;
variable TimingData_sload_clk : VitalTimingDataType := VitalTimingDataInit;
variable TimingData_ena_clk : VitalTimingDataType := VitalTimingDataInit;
variable regout_VitalGlitchData : VitalGlitchDataType;
variable iregout : std_logic := '0';
variable idata: std_logic := '0';
-- variables for 'X' generation
variable violation : std_logic := '0';
begin
------------------------
-- Timing Check Section
------------------------
if (TimingChecksOn) then
VitalSetupHoldCheck (
Violation => Tviol_datain_clk,
TimingData => TimingData_datain_clk,
TestSignal => datain_ipd,
TestSignalName => "DATAIN",
RefSignal => clk_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_datain_clk_noedge_posedge,
SetupLow => tsetup_datain_clk_noedge_posedge,
HoldHigh => thold_datain_clk_noedge_posedge,
HoldLow => thold_datain_clk_noedge_posedge,
CheckEnabled => TO_X01((aclr_ipd) OR
(sload_ipd) OR
(sclr_ipd) OR
(NOT devpor) OR
(NOT devclrn) OR
(NOT ena_ipd)) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/LCELL_FF",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_adatasdata_clk,
TimingData => TimingData_adatasdata_clk,
TestSignal => adatasdata_ipd,
TestSignalName => "ADATASDATA",
RefSignal => clk_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_adatasdata_clk_noedge_posedge,
SetupLow => tsetup_adatasdata_clk_noedge_posedge,
HoldHigh => thold_adatasdata_clk_noedge_posedge,
HoldLow => thold_adatasdata_clk_noedge_posedge,
CheckEnabled => TO_X01((aclr_ipd) OR
(NOT sload_ipd) OR
(NOT devpor) OR
(NOT devclrn) OR
(NOT ena_ipd)) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/LCELL_FF",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_sclr_clk,
TimingData => TimingData_sclr_clk,
TestSignal => sclr_ipd,
TestSignalName => "SCLR",
RefSignal => clk_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_sclr_clk_noedge_posedge,
SetupLow => tsetup_sclr_clk_noedge_posedge,
HoldHigh => thold_sclr_clk_noedge_posedge,
HoldLow => thold_sclr_clk_noedge_posedge,
CheckEnabled => TO_X01((aclr_ipd) OR
(NOT devpor) OR
(NOT devclrn) OR
(NOT ena_ipd)) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/LCELL_FF",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_sload_clk,
TimingData => TimingData_sload_clk,
TestSignal => sload_ipd,
TestSignalName => "SLOAD",
RefSignal => clk_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_sload_clk_noedge_posedge,
SetupLow => tsetup_sload_clk_noedge_posedge,
HoldHigh => thold_sload_clk_noedge_posedge,
HoldLow => thold_sload_clk_noedge_posedge,
CheckEnabled => TO_X01((aclr_ipd) OR
(NOT devpor) OR
(NOT devclrn) OR
(NOT ena_ipd)) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/LCELL_FF",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_ena_clk,
TimingData => TimingData_ena_clk,
TestSignal => ena_ipd,
TestSignalName => "ENA",
RefSignal => clk_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_ena_clk_noedge_posedge,
SetupLow => tsetup_ena_clk_noedge_posedge,
HoldHigh => thold_ena_clk_noedge_posedge,
HoldLow => thold_ena_clk_noedge_posedge,
CheckEnabled => TO_X01((aclr_ipd) OR
(NOT devpor) OR
(NOT devclrn) ) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/LCELL_FF",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
end if;
violation := Tviol_datain_clk or Tviol_adatasdata_clk or
Tviol_sclr_clk or Tviol_sload_clk or Tviol_ena_clk;
if ((devpor = '0') or (devclrn = '0') or (aclr_ipd = '1')) then
iregout := '0';
elsif (aload_ipd = '1') then
iregout := adatasdata_dly1;
elsif (violation = 'X' and x_on_violation = "on") then
iregout := 'X';
elsif clk_ipd'event and clk_ipd = '1' and clk_ipd'last_value = '0' then
if (ena_ipd = '1') then
if (sclr_ipd = '1') then
iregout := '0';
elsif (sload_ipd = '1') then
iregout := adatasdata_dly1;
else
iregout := datain_dly;
end if;
end if;
end if;
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
OutSignal => regout,
OutSignalName => "REGOUT",
OutTemp => iregout,
Paths => (0 => (aclr_ipd'last_event, tpd_aclr_regout_posedge, TRUE),
1 => (aload_ipd'last_event, tpd_aload_regout_posedge, TRUE),
2 => (adatasdata_ipd'last_event, tpd_adatasdata_regout, TRUE),
3 => (clk_ipd'last_event, tpd_clk_regout_posedge, TRUE)),
GlitchData => regout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
end vital_lcell_ff;
---------------------------------------------------------------------
--
-- Entity Name : stratixii_lcell_comb
--
-- Description : StratixII LCELL_COMB VHDL simulation model
--
--
---------------------------------------------------------------------
LIBRARY IEEE;
use IEEE.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.stratixii_atom_pack.all;
entity stratixii_lcell_comb is
generic (
lut_mask : std_logic_vector(63 downto 0) := (OTHERS => '1');
shared_arith : string := "off";
extended_lut : string := "off";
lpm_type : string := "stratixii_lcell_comb";
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks;
InstancePath: STRING := "*";
tpd_dataa_combout : VitalDelayType01 := DefPropDelay01;
tpd_datab_combout : VitalDelayType01 := DefPropDelay01;
tpd_datac_combout : VitalDelayType01 := DefPropDelay01;
tpd_datad_combout : VitalDelayType01 := DefPropDelay01;
tpd_datae_combout : VitalDelayType01 := DefPropDelay01;
tpd_dataf_combout : VitalDelayType01 := DefPropDelay01;
tpd_datag_combout : VitalDelayType01 := DefPropDelay01;
tpd_dataa_sumout : VitalDelayType01 := DefPropDelay01;
tpd_datab_sumout : VitalDelayType01 := DefPropDelay01;
tpd_datac_sumout : VitalDelayType01 := DefPropDelay01;
tpd_datad_sumout : VitalDelayType01 := DefPropDelay01;
tpd_dataf_sumout : VitalDelayType01 := DefPropDelay01;
tpd_cin_sumout : VitalDelayType01 := DefPropDelay01;
tpd_sharein_sumout : VitalDelayType01 := DefPropDelay01;
tpd_dataa_cout : VitalDelayType01 := DefPropDelay01;
tpd_datab_cout : VitalDelayType01 := DefPropDelay01;
tpd_datac_cout : VitalDelayType01 := DefPropDelay01;
tpd_datad_cout : VitalDelayType01 := DefPropDelay01;
tpd_dataf_cout : VitalDelayType01 := DefPropDelay01;
tpd_cin_cout : VitalDelayType01 := DefPropDelay01;
tpd_sharein_cout : VitalDelayType01 := DefPropDelay01;
tpd_dataa_shareout : VitalDelayType01 := DefPropDelay01;
tpd_datab_shareout : VitalDelayType01 := DefPropDelay01;
tpd_datac_shareout : VitalDelayType01 := DefPropDelay01;
tpd_datad_shareout : VitalDelayType01 := DefPropDelay01;
tipd_dataa : VitalDelayType01 := DefPropDelay01;
tipd_datab : VitalDelayType01 := DefPropDelay01;
tipd_datac : VitalDelayType01 := DefPropDelay01;
tipd_datad : VitalDelayType01 := DefPropDelay01;
tipd_datae : VitalDelayType01 := DefPropDelay01;
tipd_dataf : VitalDelayType01 := DefPropDelay01;
tipd_datag : VitalDelayType01 := DefPropDelay01;
tipd_cin : VitalDelayType01 := DefPropDelay01;
tipd_sharein : VitalDelayType01 := DefPropDelay01
);
port (
dataa : in std_logic := '0';
datab : in std_logic := '0';
datac : in std_logic := '0';
datad : in std_logic := '0';
datae : in std_logic := '0';
dataf : in std_logic := '0';
datag : in std_logic := '0';
cin : in std_logic := '0';
sharein : in std_logic := '0';
combout : out std_logic;
sumout : out std_logic;
cout : out std_logic;
shareout : out std_logic
);
attribute VITAL_LEVEL0 of stratixii_lcell_comb : entity is TRUE;
end stratixii_lcell_comb;
architecture vital_lcell_comb of stratixii_lcell_comb is
attribute VITAL_LEVEL0 of vital_lcell_comb : architecture is TRUE;
signal dataa_ipd : std_logic;
signal datab_ipd : std_logic;
signal datac_ipd : std_logic;
signal datad_ipd : std_logic;
signal datae_ipd : std_logic;
signal dataf_ipd : std_logic;
signal datag_ipd : std_logic;
signal cin_ipd : std_logic;
signal sharein_ipd : std_logic;
signal f2_input3 : std_logic;
-- sub masks
signal f0_mask : std_logic_vector(15 downto 0);
signal f1_mask : std_logic_vector(15 downto 0);
signal f2_mask : std_logic_vector(15 downto 0);
signal f3_mask : std_logic_vector(15 downto 0);
begin
---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
VitalWireDelay (dataa_ipd, dataa, tipd_dataa);
VitalWireDelay (datab_ipd, datab, tipd_datab);
VitalWireDelay (datac_ipd, datac, tipd_datac);
VitalWireDelay (datad_ipd, datad, tipd_datad);
VitalWireDelay (datae_ipd, datae, tipd_datae);
VitalWireDelay (dataf_ipd, dataf, tipd_dataf);
VitalWireDelay (datag_ipd, datag, tipd_datag);
VitalWireDelay (cin_ipd, cin, tipd_cin);
VitalWireDelay (sharein_ipd, sharein, tipd_sharein);
end block;
f0_mask <= lut_mask(15 downto 0);
f1_mask <= lut_mask(31 downto 16);
f2_mask <= lut_mask(47 downto 32);
f3_mask <= lut_mask(63 downto 48);
f2_input3 <= datag_ipd WHEN (extended_lut = "on") ELSE datac_ipd;
VITALtiming : process(dataa_ipd, datab_ipd, datac_ipd, datad_ipd,
datae_ipd, dataf_ipd, f2_input3, cin_ipd,
sharein_ipd)
variable combout_VitalGlitchData : VitalGlitchDataType;
variable sumout_VitalGlitchData : VitalGlitchDataType;
variable cout_VitalGlitchData : VitalGlitchDataType;
variable shareout_VitalGlitchData : VitalGlitchDataType;
-- sub lut outputs
variable f0_out : std_logic;
variable f1_out : std_logic;
variable f2_out : std_logic;
variable f3_out : std_logic;
-- muxed output
variable g0_out : std_logic;
variable g1_out : std_logic;
-- internal variables
variable f2_f : std_logic;
variable adder_input2 : std_logic;
-- output variables
variable combout_tmp : std_logic;
variable sumout_tmp : std_logic;
variable cout_tmp : std_logic;
-- temp variable for NCVHDL
variable lut_mask_var : std_logic_vector(63 downto 0) := (OTHERS => '1');
begin
lut_mask_var := lut_mask;
------------------------
-- Timing Check Section
------------------------
f0_out := VitalMUX(data => f0_mask,
dselect => (datad_ipd,
datac_ipd,
datab_ipd,
dataa_ipd));
f1_out := VitalMUX(data => f1_mask,
dselect => (datad_ipd,
f2_input3,
datab_ipd,
dataa_ipd));
f2_out := VitalMUX(data => f2_mask,
dselect => (datad_ipd,
datac_ipd,
datab_ipd,
dataa_ipd));
f3_out := VitalMUX(data => f3_mask,
dselect => (datad_ipd,
f2_input3,
datab_ipd,
dataa_ipd));
-- combout
if (extended_lut = "on") then
if (datae_ipd = '0') then
g0_out := f0_out;
g1_out := f2_out;
elsif (datae_ipd = '1') then
g0_out := f1_out;
g1_out := f3_out;
else
g0_out := 'X';
g1_out := 'X';
end if;
if (dataf_ipd = '0') then
combout_tmp := g0_out;
elsif ((dataf_ipd = '1') or (g0_out = g1_out))then
combout_tmp := g1_out;
else
combout_tmp := 'X';
end if;
else
combout_tmp := VitalMUX(data => lut_mask_var,
dselect => (dataf_ipd,
datae_ipd,
datad_ipd,
datac_ipd,
datab_ipd,
dataa_ipd));
end if;
-- sumout and cout
f2_f := VitalMUX(data => f2_mask,
dselect => (dataf_ipd,
datac_ipd,
datab_ipd,
dataa_ipd));
if (shared_arith = "on") then
adder_input2 := sharein_ipd;
else
adder_input2 := NOT f2_f;
end if;
sumout_tmp := cin_ipd XOR f0_out XOR adder_input2;
cout_tmp := (cin_ipd AND f0_out) OR (cin_ipd AND adder_input2) OR
(f0_out AND adder_input2);
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
OutSignal => combout,
OutSignalName => "COMBOUT",
OutTemp => combout_tmp,
Paths => (0 => (dataa_ipd'last_event, tpd_dataa_combout, TRUE),
1 => (datab_ipd'last_event, tpd_datab_combout, TRUE),
2 => (datac_ipd'last_event, tpd_datac_combout, TRUE),
3 => (datad_ipd'last_event, tpd_datad_combout, TRUE),
4 => (datae_ipd'last_event, tpd_datae_combout, TRUE),
5 => (dataf_ipd'last_event, tpd_dataf_combout, TRUE),
6 => (datag_ipd'last_event, tpd_datag_combout, TRUE)),
GlitchData => combout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
VitalPathDelay01 (
OutSignal => sumout,
OutSignalName => "SUMOUT",
OutTemp => sumout_tmp,
Paths => (0 => (dataa_ipd'last_event, tpd_dataa_sumout, TRUE),
1 => (datab_ipd'last_event, tpd_datab_sumout, TRUE),
2 => (datac_ipd'last_event, tpd_datac_sumout, TRUE),
3 => (datad_ipd'last_event, tpd_datad_sumout, TRUE),
4 => (dataf_ipd'last_event, tpd_dataf_sumout, TRUE),
5 => (cin_ipd'last_event, tpd_cin_sumout, TRUE),
6 => (sharein_ipd'last_event, tpd_sharein_sumout, TRUE)),
GlitchData => sumout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
VitalPathDelay01 (
OutSignal => cout,
OutSignalName => "COUT",
OutTemp => cout_tmp,
Paths => (0 => (dataa_ipd'last_event, tpd_dataa_cout, TRUE),
1 => (datab_ipd'last_event, tpd_datab_cout, TRUE),
2 => (datac_ipd'last_event, tpd_datac_cout, TRUE),
3 => (datad_ipd'last_event, tpd_datad_cout, TRUE),
4 => (dataf_ipd'last_event, tpd_dataf_cout, TRUE),
5 => (cin_ipd'last_event, tpd_cin_cout, TRUE),
6 => (sharein_ipd'last_event, tpd_sharein_cout, TRUE)),
GlitchData => cout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
VitalPathDelay01 (
OutSignal => shareout,
OutSignalName => "SHAREOUT",
OutTemp => f2_out,
Paths => (0 => (dataa_ipd'last_event, tpd_dataa_shareout, TRUE),
1 => (datab_ipd'last_event, tpd_datab_shareout, TRUE),
2 => (datac_ipd'last_event, tpd_datac_shareout, TRUE),
3 => (datad_ipd'last_event, tpd_datad_shareout, TRUE)),
GlitchData => shareout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
end vital_lcell_comb;
--/////////////////////////////////////////////////////////////////////////////
--
-- Entity Name : ena_reg
--
-- Description : Simulation model for a simple DFF.
-- This is used for the gated clock generation
-- Powers upto 1.
--
--/////////////////////////////////////////////////////////////////////////////
LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.stratixii_atom_pack.all;
ENTITY stratixii_ena_reg is
generic (
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : STRING := "*";
tsetup_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_clk_q_posedge : VitalDelayType01 := DefPropDelay01;
tipd_d : VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefPropDelay01
);
PORT (
clk : in std_logic;
ena : in std_logic := '1';
d : in std_logic;
clrn : in std_logic := '1';
prn : in std_logic := '1';
q : out std_logic
);
attribute VITAL_LEVEL0 of stratixii_ena_reg : entity is TRUE;
end stratixii_ena_reg;
ARCHITECTURE behave of stratixii_ena_reg is
attribute VITAL_LEVEL0 of behave : architecture is TRUE;
signal d_ipd : std_logic;
signal clk_ipd : std_logic;
begin
---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
VitalWireDelay (d_ipd, d, tipd_d);
VitalWireDelay (clk_ipd, clk, tipd_clk);
end block;
VITALtiming : process (clk_ipd, prn, clrn)
variable Tviol_d_clk : std_ulogic := '0';
variable TimingData_d_clk : VitalTimingDataType := VitalTimingDataInit;
variable q_VitalGlitchData : VitalGlitchDataType;
variable q_reg : std_logic := '1';
begin
------------------------
-- Timing Check Section
------------------------
if (TimingChecksOn) then
VitalSetupHoldCheck (
Violation => Tviol_d_clk,
TimingData => TimingData_d_clk,
TestSignal => d,
TestSignalName => "D",
RefSignal => clk_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_d_clk_noedge_posedge,
SetupLow => tsetup_d_clk_noedge_posedge,
HoldHigh => thold_d_clk_noedge_posedge,
HoldLow => thold_d_clk_noedge_posedge,
CheckEnabled => TO_X01((clrn) OR
(NOT ena)) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/ENA_REG",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
end if;
if (prn = '0') then
q_reg := '1';
elsif (clrn = '0') then
q_reg := '0';
elsif (clk_ipd'event and clk_ipd = '1' and (ena = '1')) then
q_reg := d_ipd;
end if;
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
OutSignal => q,
OutSignalName => "Q",
OutTemp => q_reg,
Paths => (0 => (clk_ipd'last_event, tpd_clk_q_posedge, TRUE)),
GlitchData => q_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
end behave;
--/////////////////////////////////////////////////////////////////////////////
--
-- VHDL Simulation Model for StratixII CLKCTRL Atom
--
--/////////////////////////////////////////////////////////////////////////////
--
--
-- STRATIXII_CLKCTRL Model
--
--
LIBRARY IEEE;
use IEEE.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.stratixii_atom_pack.all;
use work.stratixii_ena_reg;
entity stratixii_clkctrl is
generic (
clock_type : STRING := "Auto";
lpm_type : STRING := "stratixii_clkctrl";
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : STRING := "*";
tipd_inclk : VitalDelayArrayType01(3 downto 0) := (OTHERS => DefPropDelay01);
tipd_clkselect : VitalDelayArrayType01(1 downto 0) := (OTHERS => DefPropDelay01);
tipd_ena : VitalDelayType01 := DefPropDelay01
);
port (
inclk : in std_logic_vector(3 downto 0) := "0000";
clkselect : in std_logic_vector(1 downto 0) := "00";
ena : in std_logic := '1';
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
outclk : out std_logic
);
attribute VITAL_LEVEL0 of stratixii_clkctrl : entity is TRUE;
end stratixii_clkctrl;
architecture vital_clkctrl of stratixii_clkctrl is
attribute VITAL_LEVEL0 of vital_clkctrl : architecture is TRUE;
component stratixii_ena_reg
generic (
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : STRING := "*";
tsetup_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_clk_q_posedge : VitalDelayType01 := DefPropDelay01;
tipd_d : VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefPropDelay01
);
PORT (
clk : in std_logic;
ena : in std_logic := '1';
d : in std_logic;
clrn : in std_logic := '1';
prn : in std_logic := '1';
q : out std_logic
);
end component;
signal inclk_ipd : std_logic_vector(3 downto 0);
signal clkselect_ipd : std_logic_vector(1 downto 0);
signal ena_ipd : std_logic;
signal clkmux_out : std_logic;
signal clkmux_out_inv : std_logic;
signal cereg_clr : std_logic;
signal cereg_out : std_logic;
signal vcc : std_logic := '1';
begin
---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
VitalWireDelay (ena_ipd, ena, tipd_ena);
VitalWireDelay (inclk_ipd(0), inclk(0), tipd_inclk(0));
VitalWireDelay (inclk_ipd(1), inclk(1), tipd_inclk(1));
VitalWireDelay (inclk_ipd(2), inclk(2), tipd_inclk(2));
VitalWireDelay (inclk_ipd(3), inclk(3), tipd_inclk(3));
VitalWireDelay (clkselect_ipd(0), clkselect(0), tipd_clkselect(0));
VitalWireDelay (clkselect_ipd(1), clkselect(1), tipd_clkselect(1));
end block;
process(inclk_ipd, clkselect_ipd)
variable tmp : std_logic;
begin
if (clkselect_ipd = "11") then
tmp := inclk_ipd(3);
elsif (clkselect_ipd = "10") then
tmp := inclk_ipd(2);
elsif (clkselect_ipd = "01") then
tmp := inclk_ipd(1);
else
tmp := inclk_ipd(0);
end if;
clkmux_out <= tmp;
clkmux_out_inv <= NOT tmp;
end process;
extena0_reg : stratixii_ena_reg
port map (
clk => clkmux_out_inv,
ena => vcc,
d => ena_ipd,
clrn => vcc,
prn => devpor,
q => cereg_out
);
outclk <= cereg_out AND clkmux_out;
end vital_clkctrl;
--
--
-- STRATIXII_ASYNCH_IO Model
--
--
LIBRARY IEEE;
use IEEE.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.stratixii_atom_pack.all;
entity stratixii_asynch_io is
generic(
operation_mode : STRING := "input";
open_drain_output : STRING := "false";
bus_hold : STRING := "false";
dqs_input_frequency : STRING := "10000 ps";
dqs_out_mode : STRING := "none";
dqs_delay_buffer_mode : STRING := "low";
dqs_phase_shift : INTEGER := 0;
dqs_offsetctrl_enable : STRING := "false";
dqs_ctrl_latches_enable : STRING := "false";
dqs_edge_detect_enable : STRING := "false";
gated_dqs : STRING := "false";
sim_dqs_intrinsic_delay : INTEGER := 0;
sim_dqs_delay_increment : INTEGER := 0;
sim_dqs_offset_increment : INTEGER := 0;
XOn: Boolean := DefGlitchXOn;
MsgOn: Boolean := DefGlitchMsgOn;
tpd_datain_padio : VitalDelayType01 := DefPropDelay01;
tpd_oe_padio_posedge : VitalDelayType01 := DefPropDelay01;
tpd_oe_padio_negedge : VitalDelayType01 := DefPropDelay01;
tpd_padio_combout : VitalDelayType01 := DefPropDelay01;
tpd_regin_regout : VitalDelayType01 := DefPropDelay01;
tpd_ddioregin_ddioregout : VitalDelayType01 := DefPropDelay01;
tpd_padio_dqsbusout : VitalDelayType01 := DefPropDelay01;
tpd_regin_dqsbusout : VitalDelayType01 := DefPropDelay01;
tipd_datain : VitalDelayType01 := DefPropDelay01;
tipd_oe : VitalDelayType01 := DefPropDelay01;
tipd_padio : VitalDelayType01 := DefPropDelay01;
tipd_dqsupdateen : VitalDelayType01 := DefPropDelay01;
tipd_offsetctrlin : VitalDelayArrayType01(5 downto 0) := (OTHERS => DefPropDelay01);
tipd_delayctrlin : VitalDelayArrayType01(5 downto 0) := (OTHERS => DefPropDelay01));
port(
datain : in STD_LOGIC := '0';
oe : in STD_LOGIC := '1';
regin : in std_logic;
ddioregin : in std_logic;
padio : inout STD_LOGIC;
delayctrlin : in std_logic_vector(5 downto 0);
offsetctrlin : in std_logic_vector(5 downto 0);
dqsupdateen : in std_logic;
dqsbusout : out std_logic;
combout : out STD_LOGIC;
regout : out STD_LOGIC;
ddioregout : out STD_LOGIC);
attribute VITAL_LEVEL0 of stratixii_asynch_io : entity is TRUE;
end stratixii_asynch_io;
architecture behave of stratixii_asynch_io is
attribute VITAL_LEVEL0 of behave : architecture is TRUE;
signal datain_ipd, oe_ipd, padio_ipd: std_logic;
signal delayctrlin_in : std_logic_vector(5 downto 0);
signal offsetctrlin_in : std_logic_vector(5 downto 0);
signal dqsupdateen_in : std_logic;
signal dqs_delay_int : integer := 0;
signal tmp_dqsbusout : std_logic;
signal dqs_ctrl_latches_ena : std_logic := '1';
signal combout_tmp_sig : std_logic := '0';
signal dqsbusout_tmp_sig : std_logic := '0';
begin
---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
VitalWireDelay (datain_ipd, datain, tipd_datain);
VitalWireDelay (oe_ipd, oe, tipd_oe);
VitalWireDelay (padio_ipd, padio, tipd_padio);
VitalWireDelay (delayctrlin_in(5), delayctrlin(5), tipd_delayctrlin(5));
VitalWireDelay (delayctrlin_in(4), delayctrlin(4), tipd_delayctrlin(4));
VitalWireDelay (delayctrlin_in(3), delayctrlin(3), tipd_delayctrlin(3));
VitalWireDelay (delayctrlin_in(2), delayctrlin(2), tipd_delayctrlin(2));
VitalWireDelay (delayctrlin_in(1), delayctrlin(1), tipd_delayctrlin(1));
VitalWireDelay (delayctrlin_in(0), delayctrlin(0), tipd_delayctrlin(0));
VitalWireDelay (dqsupdateen_in, dqsupdateen, tipd_dqsupdateen);
VitalWireDelay (offsetctrlin_in(5), offsetctrlin(5), tipd_offsetctrlin(5));
VitalWireDelay (offsetctrlin_in(4), offsetctrlin(4), tipd_offsetctrlin(4));
VitalWireDelay (offsetctrlin_in(3), offsetctrlin(3), tipd_offsetctrlin(3));
VitalWireDelay (offsetctrlin_in(2), offsetctrlin(2), tipd_offsetctrlin(2));
VitalWireDelay (offsetctrlin_in(1), offsetctrlin(1), tipd_offsetctrlin(1));
VitalWireDelay (offsetctrlin_in(0), offsetctrlin(0), tipd_offsetctrlin(0));
end block;
dqs_ctrl_latches_ena <= '1' when dqs_ctrl_latches_enable = "false" ELSE
dqsupdateen_in when dqs_edge_detect_enable = "false" ELSE
(not (combout_tmp_sig xor tmp_dqsbusout) and dqsupdateen_in);
process(delayctrlin_in, offsetctrlin_in, dqs_ctrl_latches_ena)
variable tmp_delayctrl : integer := 0;
variable tmp_offsetctrl : integer := 0;
begin
tmp_delayctrl := alt_conv_integer(delayctrlin_in);
if (dqs_offsetctrl_enable = "true") then
tmp_offsetctrl := alt_conv_integer(offsetctrlin_in);
else
tmp_offsetctrl := 0;
end if;
if (dqs_ctrl_latches_ena = '1') THEN
dqs_delay_int <= sim_dqs_intrinsic_delay + sim_dqs_delay_increment*tmp_delayctrl + sim_dqs_offset_increment*tmp_offsetctrl;
end if;
if ((dqs_delay_buffer_mode = "high") AND (delayctrlin_in(5) = '1')) THEN
assert false report "DELAYCTRLIN of DQS I/O exceeds 5-bit range in high-frequency mode" severity warning;
dqs_delay_int <= 0;
end if;
end process;
VITAL: process(padio_ipd, datain_ipd, oe_ipd, regin, ddioregin, tmp_dqsbusout)
variable combout_VitalGlitchData : VitalGlitchDataType;
variable dqsbusout_VitalGlitchData : VitalGlitchDataType;
variable padio_VitalGlitchData : VitalGlitchDataType;
variable regout_VitalGlitchData : VitalGlitchDataType;
variable ddioregout_VitalGlitchData : VitalGlitchDataType;
variable tmp_combout, tmp_padio : std_logic;
variable prev_value : std_logic := 'H';
variable dqsbusout_tmp : std_logic;
variable combout_delay : VitalDelayType01 := (0 ps, 0 ps);
variable init : boolean := true;
begin
if (init) then
combout_delay := tpd_padio_combout;
init := false;
end if;
if (bus_hold = "true" ) then
if ( operation_mode = "input") then
if ( padio_ipd = 'Z') then
tmp_combout := to_x01z(prev_value);
else
if ( padio_ipd = '1') then
prev_value := 'H';
elsif ( padio_ipd = '0') then
prev_value := 'L';
else
prev_value := 'W';
end if;
tmp_combout := to_x01z(padio_ipd);
end if;
tmp_padio := 'Z';
elsif ( operation_mode = "output" or operation_mode = "bidir") then
if ( oe_ipd = '1') then
if ( open_drain_output = "true" ) then
if (datain_ipd = '0') then
tmp_padio := '0';
prev_value := 'L';
elsif (datain_ipd = 'X') then
tmp_padio := 'X';
prev_value := 'W';
else -- 'Z'
-- need to update prev_value
if (padio_ipd = '1') then
prev_value := 'H';
elsif (padio_ipd = '0') then
prev_value := 'L';
elsif (padio_ipd = 'X') then
prev_value := 'W';
end if;
tmp_padio := prev_value;
end if;
else
tmp_padio := datain_ipd;
if ( datain_ipd = '1') then
prev_value := 'H';
elsif (datain_ipd = '0' ) then
prev_value := 'L';
elsif ( datain_ipd = 'X') then
prev_value := 'W';
else
prev_value := datain_ipd;
end if;
end if; -- end open_drain_output
elsif ( oe_ipd = '0' ) then
-- need to update prev_value
if (padio_ipd = '1') then
prev_value := 'H';
elsif (padio_ipd = '0') then
prev_value := 'L';
elsif (padio_ipd = 'X') then
prev_value := 'W';
end if;
tmp_padio := prev_value;
else
tmp_padio := 'X';
prev_value := 'W';
end if; -- end oe_in
if ( operation_mode = "bidir") then
tmp_combout := to_x01z(padio_ipd);
else
tmp_combout := 'Z';
end if;
end if;
if ( now <= 1 ps AND prev_value = 'W' ) then --hack for autotest to pass
prev_value := 'L';
end if;
else -- bus_hold is false
if ( operation_mode = "input") then
tmp_combout := padio_ipd;
tmp_padio := 'Z';
elsif (operation_mode = "output" or operation_mode = "bidir" ) then
if ( operation_mode = "bidir") then
tmp_combout := padio_ipd;
else
tmp_combout := 'Z';
end if;
if ( oe_ipd = '1') then
if ( open_drain_output = "true" ) then
if (datain_ipd = '0') then
tmp_padio := '0';
elsif (datain_ipd = 'X') then
tmp_padio := 'X';
else
tmp_padio := 'Z';
end if;
else
tmp_padio := datain_ipd;
end if;
elsif ( oe_ipd = '0' ) then
tmp_padio := 'Z';
else
tmp_padio := 'X';
end if;
end if;
end if; -- end bus_hold
tmp_dqsbusout <= transport tmp_combout after (dqs_delay_int * 1 ps);
if (gated_dqs = "true") then
dqsbusout_tmp := tmp_dqsbusout AND regin;
else
dqsbusout_tmp := tmp_dqsbusout;
end if;
-- for dqs delay ctrl latches enable
dqsbusout_tmp_sig <= dqsbusout_tmp;
combout_tmp_sig <= tmp_combout;
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
OutSignal => combout,
OutSignalName => "combout",
OutTemp => tmp_combout,
Paths => (1 => (padio_ipd'last_event, combout_delay, TRUE)),
GlitchData => combout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
VitalPathDelay01 (
OutSignal => dqsbusout,
OutSignalName => "dqsbusout",
OutTemp => dqsbusout_tmp,
Paths => (1 => (tmp_dqsbusout'last_event, tpd_padio_dqsbusout, TRUE),
2 => (regin'last_event, tpd_regin_dqsbusout, gated_dqs = "true")),
GlitchData => dqsbusout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
VitalPathDelay01 (
OutSignal => padio,
OutSignalName => "padio",
OutTemp => tmp_padio,
Paths => (1 => (datain_ipd'last_event, tpd_datain_padio, TRUE),
2 => (oe_ipd'last_event, tpd_oe_padio_posedge, oe_ipd = '1'),
3 => (oe_ipd'last_event, tpd_oe_padio_negedge, oe_ipd = '0')),
GlitchData => padio_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
VitalPathDelay01 (
OutSignal => regout,
OutSignalName => "regout",
OutTemp => regin,
Paths => (1 => (regin'last_event, tpd_regin_regout, TRUE)),
GlitchData => regout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
VitalPathDelay01 (
OutSignal => ddioregout,
OutSignalName => "ddioregout",
OutTemp => ddioregin,
Paths => (1 => (ddioregin'last_event, tpd_ddioregin_ddioregout, TRUE)),
GlitchData => ddioregout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
end behave;
--
-- STRATIXII_IO_REGISTER
--
LIBRARY IEEE;
use IEEE.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.stratixii_atom_pack.all;
entity stratixii_io_register is
generic (
async_reset : string := "none";
sync_reset : string := "none";
power_up : string := "low";
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks;
InstancePath: STRING := "*";
tsetup_datain_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_sreset_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_datain_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_sreset_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_clk_regout_posedge : VitalDelayType01 := DefPropDelay01;
tpd_areset_regout_posedge : VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_datain : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
tipd_areset : VitalDelayType01 := DefPropDelay01;
tipd_sreset : VitalDelayType01 := DefPropDelay01);
port (clk :in std_logic := '0';
datain : in std_logic := '0';
ena : in std_logic := '1';
sreset : in std_logic := '0';
areset : in std_logic := '0';
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
regout : out std_logic);
attribute VITAL_LEVEL0 of stratixii_io_register : entity is TRUE;
end stratixii_io_register;
architecture vital_io_reg of stratixii_io_register is
attribute VITAL_LEVEL0 of vital_io_reg : architecture is TRUE;
signal datain_ipd, ena_ipd, sreset_ipd : std_logic;
signal clk_ipd, areset_ipd : std_logic;
begin
---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
VitalWireDelay (datain_ipd, datain, tipd_datain);
VitalWireDelay (clk_ipd, clk, tipd_clk);
VitalWireDelay (ena_ipd, ena, tipd_ena);
VitalWireDelay (sreset_ipd, sreset, tipd_sreset);
VitalWireDelay (areset_ipd, areset, tipd_areset);
end block;
VITALtiming : process(clk_ipd, datain_ipd, ena_ipd, sreset_ipd, areset_ipd, devclrn, devpor)
variable Tviol_datain_clk : std_ulogic := '0';
variable Tviol_ena_clk : std_ulogic := '0';
variable Tviol_sreset_clk : std_ulogic := '0';
variable TimingData_datain_clk : VitalTimingDataType := VitalTimingDataInit;
variable TimingData_ena_clk : VitalTimingDataType := VitalTimingDataInit;
variable TimingData_sreset_clk : VitalTimingDataType := VitalTimingDataInit;
variable regout_VitalGlitchData : VitalGlitchDataType;
variable iregout : std_logic;
variable idata : std_logic := '0';
variable tmp_regout : std_logic;
variable tmp_reset : std_logic := '0';
-- variables for 'X' generation
variable violation : std_logic := '0';
begin
if (now = 0 ns) then
if (power_up = "low") then
iregout := '0';
elsif (power_up = "high") then
iregout := '1';
end if;
end if;
if ( async_reset /= "none") then
tmp_reset := areset_ipd; -- this is used to enable timing check.
end if;
------------------------
-- Timing Check Section
------------------------
if (TimingChecksOn) then
VitalSetupHoldCheck (
Violation => Tviol_datain_clk,
TimingData => TimingData_datain_clk,
TestSignal => datain_ipd,
TestSignalName => "DATAIN",
RefSignal => clk_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_datain_clk_noedge_posedge,
SetupLow => tsetup_datain_clk_noedge_posedge,
HoldHigh => thold_datain_clk_noedge_posedge,
HoldLow => thold_datain_clk_noedge_posedge,
CheckEnabled => TO_X01((tmp_reset) OR (NOT devpor) OR (NOT devclrn) OR (NOT ena_ipd)) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/LCELL",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_ena_clk,
TimingData => TimingData_ena_clk,
TestSignal => ena_ipd,
TestSignalName => "ENA",
RefSignal => clk_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_ena_clk_noedge_posedge,
SetupLow => tsetup_ena_clk_noedge_posedge,
HoldHigh => thold_ena_clk_noedge_posedge,
HoldLow => thold_ena_clk_noedge_posedge,
CheckEnabled => TO_X01((tmp_reset) OR (NOT devpor) OR (NOT devclrn) OR (NOT ena_ipd)) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/LCELL",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_sreset_clk,
TimingData => TimingData_sreset_clk,
TestSignal => sreset_ipd,
TestSignalName => "SRESET",
RefSignal => clk_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_sreset_clk_noedge_posedge,
SetupLow => tsetup_sreset_clk_noedge_posedge,
HoldHigh => thold_sreset_clk_noedge_posedge,
HoldLow => thold_sreset_clk_noedge_posedge,
CheckEnabled => TO_X01((tmp_reset) OR (NOT devpor) OR (NOT devclrn) OR (NOT ena_ipd)) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/LCELL",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
end if;
violation := Tviol_datain_clk or Tviol_ena_clk or Tviol_sreset_clk;
if (devpor = '0') then
if (power_up = "low") then
iregout := '0';
elsif (power_up = "high") then
iregout := '1';
end if;
elsif (devclrn = '0') then
iregout := '0';
elsif (async_reset = "clear" and areset_ipd = '1') then
iregout := '0';
elsif ( async_reset = "preset" and areset_ipd = '1') then
iregout := '1';
elsif (violation = 'X') then
iregout := 'X';
elsif (ena_ipd = '1' and clk_ipd'event and clk_ipd = '1' and clk_ipd'last_value = '0') then
if (sync_reset = "clear" and sreset_ipd = '1' ) then
iregout := '0';
elsif (sync_reset = "preset" and sreset_ipd = '1' ) then
iregout := '1';
else
iregout := to_x01z(datain_ipd);
end if;
end if;
tmp_regout := iregout;
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
OutSignal => regout,
OutSignalName => "REGOUT",
OutTemp => tmp_regout,
Paths => (0 => (areset_ipd'last_event, tpd_areset_regout_posedge, async_reset /= "none"),
1 => (clk_ipd'last_event, tpd_clk_regout_posedge, TRUE)),
GlitchData => regout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
end vital_io_reg;
--
-- STRATIXII_IO
--
LIBRARY IEEE;
use IEEE.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.stratixii_atom_pack.all;
use work.stratixii_asynch_io;
use work.stratixii_io_register;
use work.stratixii_mux21;
use work.stratixii_and1;
entity stratixii_io is
generic (
operation_mode : string := "input";
ddio_mode : string := "none";
open_drain_output : string := "false";
bus_hold : string := "false";
output_register_mode : string := "none";
output_async_reset : string := "none";
output_power_up : string := "low";
output_sync_reset : string := "none";
tie_off_output_clock_enable : string := "false";
oe_register_mode : string := "none";
oe_async_reset : string := "none";
oe_power_up : string := "low";
oe_sync_reset : string := "none";
tie_off_oe_clock_enable : string := "false";
input_register_mode : string := "none";
input_async_reset : string := "none";
input_power_up : string := "low";
input_sync_reset : string := "none";
extend_oe_disable : string := "false";
dqs_input_frequency : string := "10000 ps";
dqs_out_mode : string := "none";
dqs_delay_buffer_mode : string := "low";
dqs_phase_shift : integer := 0;
inclk_input : string := "normal";
ddioinclk_input : string := "negated_inclk";
dqs_offsetctrl_enable : string := "false";
dqs_ctrl_latches_enable : string := "false";
dqs_edge_detect_enable : string := "false";
gated_dqs : string := "false";
sim_dqs_intrinsic_delay : integer := 0;
sim_dqs_delay_increment : integer := 0;
sim_dqs_offset_increment : integer := 0;
lpm_type : string := "stratixii_io"
);
port (
datain : in std_logic := '0';
ddiodatain : in std_logic := '0';
oe : in std_logic := '1';
outclk : in std_logic := '0';
outclkena : in std_logic := '1';
inclk : in std_logic := '0';
inclkena : in std_logic := '1';
areset : in std_logic := '0';
sreset : in std_logic := '0';
ddioinclk : in std_logic := '0';
delayctrlin : in std_logic_vector(5 downto 0) := "000000";
offsetctrlin : in std_logic_vector(5 downto 0) := "000000";
dqsupdateen : in std_logic := '0';
linkin : in std_logic := '0';
terminationcontrol : in std_logic_vector(13 downto 0) := "00000000000000";
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
devoe : in std_logic := '0';
padio : inout std_logic;
combout : out std_logic;
regout : out std_logic;
ddioregout : out std_logic;
dqsbusout : out std_logic;
linkout : out std_logic
);
end stratixii_io;
architecture structure of stratixii_io is
component stratixii_asynch_io
generic(
operation_mode : string := "input";
open_drain_output : string := "false";
bus_hold : string := "false";
dqs_input_frequency : string := "10000 ps";
dqs_out_mode : string := "none";
dqs_delay_buffer_mode : string := "low";
dqs_phase_shift : integer := 0;
dqs_offsetctrl_enable : string := "false";
dqs_ctrl_latches_enable : string := "false";
dqs_edge_detect_enable : string := "false";
gated_dqs : string := "false";
sim_dqs_intrinsic_delay : integer := 0;
sim_dqs_delay_increment : integer := 0;
sim_dqs_offset_increment : integer := 0);
port(
datain : in STD_LOGIC := '0';
oe : in STD_LOGIC := '1';
regin : in std_logic;
ddioregin : in std_logic;
padio : inout STD_LOGIC;
delayctrlin : in std_logic_vector(5 downto 0);
offsetctrlin : in std_logic_vector(5 downto 0);
dqsupdateen : in std_logic;
dqsbusout : out std_logic;
combout: out STD_LOGIC;
regout : out STD_LOGIC;
ddioregout : out STD_LOGIC);
end component;
component stratixii_io_register
generic(async_reset : string := "none";
sync_reset : string := "none";
power_up : string := "low";
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks;
InstancePath: STRING := "*";
tsetup_datain_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_sreset_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_datain_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_sreset_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_clk_regout_posedge : VitalDelayType01 := DefPropDelay01;
tpd_areset_regout_posedge : VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_datain : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
tipd_areset : VitalDelayType01 := DefPropDelay01;
tipd_sreset : VitalDelayType01 := DefPropDelay01);
port(clk :in std_logic := '0';
datain : in std_logic := '0';
ena : in std_logic := '1';
sreset : in std_logic := '0';
areset : in std_logic := '0';
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
regout : out std_logic);
end component;
component stratixii_mux21
generic(
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
InstancePath: STRING := "*";
tpd_A_MO : VitalDelayType01 := DefPropDelay01;
tpd_B_MO : VitalDelayType01 := DefPropDelay01;
tpd_S_MO : VitalDelayType01 := DefPropDelay01;
tipd_A : VitalDelayType01 := DefPropDelay01;
tipd_B : VitalDelayType01 := DefPropDelay01;
tipd_S : VitalDelayType01 := DefPropDelay01);
port ( A : in std_logic := '0';
B : in std_logic := '0';
S : in std_logic := '0';
MO : out std_logic);
end component;
component stratixii_and1
generic(
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
InstancePath: STRING := "*";
tpd_IN1_Y : VitalDelayType01 := DefPropDelay01;
tipd_IN1 : VitalDelayType01 := DefPropDelay01);
port( Y : out STD_LOGIC;
IN1 : in STD_LOGIC);
end component;
signal oe_out : std_logic;
signal in_reg_out, in_ddio0_reg_out, in_ddio1_reg_out: std_logic;
signal oe_reg_out, oe_pulse_reg_out : std_logic;
signal out_reg_out, out_ddio_reg_out: std_logic;
signal tmp_datain : std_logic;
signal not_inclk, not_outclk : std_logic;
-- for DDIO
signal ddio_data : std_logic;
signal outclk_delayed : std_logic;
signal out_clk_ena, oe_clk_ena : std_logic;
begin
not_inclk <= (ddioinclk) WHEN (ddioinclk_input = "dqsb_bus") ELSE (not inclk);
not_outclk <= not outclk;
out_clk_ena <= '1' WHEN tie_off_output_clock_enable = "true" ELSE outclkena;
oe_clk_ena <= '1' WHEN tie_off_oe_clock_enable = "true" ELSE outclkena;
--input register
in_reg : stratixii_io_register
generic map ( ASYNC_RESET => input_async_reset,
SYNC_RESET => input_sync_reset,
POWER_UP => input_power_up)
port map ( regout => in_reg_out,
clk => inclk,
ena => inclkena,
datain => padio,
areset => areset,
sreset => sreset,
devpor => devpor,
devclrn => devclrn);
-- in_ddio0_reg
in_ddio0_reg : stratixii_io_register
generic map ( ASYNC_RESET => input_async_reset,
SYNC_RESET => input_sync_reset,
POWER_UP => input_power_up)
port map (regout => in_ddio0_reg_out,
clk => not_inclk,
ena => inclkena,
datain => padio,
areset => areset,
sreset => sreset,
devpor => devpor,
devclrn => devclrn);
-- in_ddio1_reg
in_ddio1_reg : stratixii_io_register
generic map ( ASYNC_RESET => input_async_reset,
SYNC_RESET => "none", -- this register does not have sync_reset
POWER_UP => input_power_up)
port map (regout => in_ddio1_reg_out,
clk => inclk,
ena => inclkena,
datain => in_ddio0_reg_out,
areset => areset,
devpor => devpor,
devclrn => devclrn);
-- out_reg
out_reg : stratixii_io_register
generic map ( ASYNC_RESET => output_async_reset,
SYNC_RESET => output_sync_reset,
POWER_UP => output_power_up)
port map (regout => out_reg_out,
clk => outclk,
ena => out_clk_ena,
datain => datain,
areset => areset,
sreset => sreset,
devpor => devpor,
devclrn => devclrn);
-- out ddio reg
out_ddio_reg : stratixii_io_register
generic map ( ASYNC_RESET => output_async_reset,
SYNC_RESET => output_sync_reset,
POWER_UP => output_power_up)
port map (regout => out_ddio_reg_out,
clk => outclk,
ena => out_clk_ena,
datain => ddiodatain,
areset => areset,
sreset => sreset,
devpor => devpor,
devclrn => devclrn);
-- oe reg
oe_reg : stratixii_io_register
generic map (ASYNC_RESET => oe_async_reset,
SYNC_RESET => oe_sync_reset,
POWER_UP => oe_power_up)
port map (regout => oe_reg_out,
clk => outclk,
ena => oe_clk_ena,
datain => oe,
areset => areset,
sreset => sreset,
devpor => devpor,
devclrn => devclrn);
-- oe_pulse reg
oe_pulse_reg : stratixii_io_register
generic map (ASYNC_RESET => oe_async_reset,
SYNC_RESET => oe_sync_reset,
POWER_UP => oe_power_up)
port map (regout => oe_pulse_reg_out,
clk => not_outclk,
ena => oe_clk_ena,
datain => oe_reg_out,
areset => areset,
sreset => sreset,
devpor => devpor,
devclrn => devclrn);
oe_out <= (oe_pulse_reg_out and oe_reg_out) WHEN (extend_oe_disable = "true") ELSE oe_reg_out WHEN (oe_register_mode = "register") ELSE oe;
sel_delaybuf : stratixii_and1
port map (Y => outclk_delayed,
IN1 => outclk);
ddio_data_mux : stratixii_mux21
port map (MO => ddio_data,
A => out_ddio_reg_out,
B => out_reg_out,
S => outclk_delayed);
tmp_datain <= ddio_data WHEN (ddio_mode = "output" or ddio_mode = "bidir") ELSE
out_reg_out WHEN (output_register_mode = "register") ELSE
datain;
-- timing info in case output and/or input are not registered.
inst1 : stratixii_asynch_io
generic map ( OPERATION_MODE => operation_mode,
OPEN_DRAIN_OUTPUT => open_drain_output,
BUS_HOLD => bus_hold,
dqs_input_frequency => dqs_input_frequency,
dqs_out_mode => dqs_out_mode,
dqs_delay_buffer_mode => dqs_delay_buffer_mode,
dqs_phase_shift => dqs_phase_shift,
dqs_offsetctrl_enable => dqs_offsetctrl_enable,
dqs_ctrl_latches_enable => dqs_ctrl_latches_enable,
dqs_edge_detect_enable => dqs_edge_detect_enable,
gated_dqs => gated_dqs,
sim_dqs_intrinsic_delay => sim_dqs_intrinsic_delay,
sim_dqs_delay_increment => sim_dqs_delay_increment,
sim_dqs_offset_increment => sim_dqs_offset_increment)
port map( datain => tmp_datain,
oe => oe_out,
regin => in_reg_out,
ddioregin => in_ddio1_reg_out,
padio => padio,
delayctrlin => delayctrlin,
offsetctrlin => offsetctrlin,
dqsupdateen => dqsupdateen,
dqsbusout => dqsbusout,
combout => combout,
regout => regout,
ddioregout => ddioregout);
end structure;
--///////////////////////////////////////////////////////////////////////////
--
-- Entity Name : stratixii_mn_cntr
--
-- Description : Timing simulation model for the M and N counter. This is a
-- common model for the input counter and the loop feedback
-- counter of the StratixII PLL.
--
--///////////////////////////////////////////////////////////////////////////
LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
USE IEEE.VITAL_Timing.all;
USE IEEE.VITAL_Primitives.all;
ENTITY stratixii_mn_cntr is
PORT( clk : IN std_logic;
reset : IN std_logic := '0';
cout : OUT std_logic;
initial_value : IN integer := 1;
modulus : IN integer := 1;
time_delay : IN integer := 0
);
END stratixii_mn_cntr;
ARCHITECTURE behave of stratixii_mn_cntr is
begin
process (clk, reset)
variable count : integer := 1;
variable first_rising_edge : boolean := true;
variable tmp_cout : std_logic;
begin
if (reset = '1') then
count := 1;
tmp_cout := '0';
first_rising_edge := true;
elsif (clk'event and clk = '1' and first_rising_edge) then
first_rising_edge := false;
tmp_cout := clk;
elsif (not first_rising_edge) then
if (count < modulus) then
count := count + 1;
else
count := 1;
tmp_cout := not tmp_cout;
end if;
end if;
cout <= transport tmp_cout after time_delay * 1 ps;
end process;
end behave;
--/////////////////////////////////////////////////////////////////////////////
--
-- Entity Name : stratixii_scale_cntr
--
-- Description : Timing simulation model for the output scale-down counters.
-- This is a common model for the C0, C1, C2, C3, C4 and C5
-- output counters of the StratixII PLL.
--
--/////////////////////////////////////////////////////////////////////////////
LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
USE IEEE.VITAL_Timing.all;
USE IEEE.VITAL_Primitives.all;
ENTITY stratixii_scale_cntr is
PORT( clk : IN std_logic;
reset : IN std_logic := '0';
initial : IN integer := 1;
high : IN integer := 1;
low : IN integer := 1;
mode : IN string := "bypass";
ph_tap : IN integer := 0;
cout : OUT std_logic
);
END stratixii_scale_cntr;
ARCHITECTURE behave of stratixii_scale_cntr is
begin
process (clk, reset)
variable tmp_cout : std_logic := '0';
variable count : integer := 1;
variable output_shift_count : integer := 1;
variable first_rising_edge : boolean := false;
begin
if (reset = '1') then
count := 1;
output_shift_count := 1;
tmp_cout := '0';
first_rising_edge := false;
elsif (clk'event) then
if (mode = " off") then
tmp_cout := '0';
elsif (mode = "bypass") then
tmp_cout := clk;
first_rising_edge := true;
elsif (not first_rising_edge) then
if (clk = '1') then
if (output_shift_count = initial) then
tmp_cout := clk;
first_rising_edge := true;
else
output_shift_count := output_shift_count + 1;
end if;
end if;
elsif (output_shift_count < initial) then
if (clk = '1') then
output_shift_count := output_shift_count + 1;
end if;
else
count := count + 1;
if (mode = " even" and (count = (high*2) + 1)) then
tmp_cout := '0';
elsif (mode = " odd" and (count = high*2)) then
tmp_cout := '0';
elsif (count = (high + low)*2 + 1) then
tmp_cout := '1';
count := 1; -- reset count
end if;
end if;
end if;
cout <= transport tmp_cout;
end process;
end behave;
--/////////////////////////////////////////////////////////////////////////////
--
-- Entity Name : stratixii_pll_reg
--
-- Description : Simulation model for a simple DFF.
-- This is required for the generation of the bit slip-signals.
-- No timing, powers upto 0.
--
--/////////////////////////////////////////////////////////////////////////////
LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
ENTITY stratixii_pll_reg is
PORT( clk : in std_logic;
ena : in std_logic := '1';
d : in std_logic;
clrn : in std_logic := '1';
prn : in std_logic := '1';
q : out std_logic
);
end stratixii_pll_reg;
ARCHITECTURE behave of stratixii_pll_reg is
begin
process (clk, prn, clrn)
variable q_reg : std_logic := '0';
begin
if (prn = '0') then
q_reg := '1';
elsif (clrn = '0') then
q_reg := '0';
elsif (clk'event and clk = '1' and (ena = '1')) then
q_reg := D;
end if;
Q <= q_reg;
end process;
end behave;
--///////////////////////////////////////////////////////////////////////////
--
-- Entity Name : stratixii_pll
--
-- Description : Timing simulation model for the StratixII PLL.
-- In the functional mode, it is also the model for the altpll
-- megafunction.
--
-- Limitations : Does not support Spread Spectrum and Bandwidth.
--
-- Outputs : Up to 6 output clocks, each defined by its own set of
-- parameters. Locked output (active high) indicates when the
-- PLL locks. clkbad, clkloss and activeclock are used for
-- clock switchover to indicate which input clock has gone
-- bad, when the clock switchover initiates and which input
-- clock is being used as the reference, respectively.
-- scandataout is the data output of the serial scan chain.
--
--///////////////////////////////////////////////////////////////////////////
LIBRARY IEEE, std;
USE IEEE.std_logic_1164.all;
USE IEEE.VITAL_Timing.all;
USE IEEE.VITAL_Primitives.all;
USE STD.TEXTIO.all;
USE work.stratixii_atom_pack.all;
USE work.stratixii_pllpack.all;
USE work.stratixii_mn_cntr;
USE work.stratixii_scale_cntr;
USE work.stratixii_dffe;
USE work.stratixii_pll_reg;
ENTITY stratixii_pll is
GENERIC (
operation_mode : string := "normal";
pll_type : string := "auto"; -- EGPP/FAST/AUTO
compensate_clock : string := "clk0";
feedback_source : string := "clk0";
qualify_conf_done : string := "off";
test_input_comp_delay : integer := 0;
test_feedback_comp_delay : integer := 0;
inclk0_input_frequency : integer := 10000;
inclk1_input_frequency : integer := 10000;
gate_lock_signal : string := "no";
gate_lock_counter : integer := 1;
self_reset_on_gated_loss_lock : string := "off";
valid_lock_multiplier : integer := 1;
invalid_lock_multiplier : integer := 5;
switch_over_type : string := "auto";
switch_over_on_lossclk : string := "off";
switch_over_on_gated_lock : string := "off";
switch_over_counter : integer := 1;
enable_switch_over_counter : string := "on";
bandwidth : integer := 0;
bandwidth_type : string := "auto";
down_spread : string := "0.0";
spread_frequency : integer := 0;
clk0_output_frequency : integer := 0;
clk0_multiply_by : integer := 1;
clk0_divide_by : integer := 1;
clk0_phase_shift : string := "0";
clk0_duty_cycle : integer := 50;
clk1_output_frequency : integer := 0;
clk1_multiply_by : integer := 1;
clk1_divide_by : integer := 1;
clk1_phase_shift : string := "0";
clk1_duty_cycle : integer := 50;
clk2_output_frequency : integer := 0;
clk2_multiply_by : integer := 1;
clk2_divide_by : integer := 1;
clk2_phase_shift : string := "0";
clk2_duty_cycle : integer := 50;
clk3_output_frequency : integer := 0;
clk3_multiply_by : integer := 1;
clk3_divide_by : integer := 1;
clk3_phase_shift : string := "0";
clk3_duty_cycle : integer := 50;
clk4_output_frequency : integer := 0;
clk4_multiply_by : integer := 1;
clk4_divide_by : integer := 1;
clk4_phase_shift : string := "0";
clk4_duty_cycle : integer := 50;
clk5_output_frequency : integer := 0;
clk5_multiply_by : integer := 1;
clk5_divide_by : integer := 1;
clk5_phase_shift : string := "0";
clk5_duty_cycle : integer := 50;
pfd_min : integer := 0;
pfd_max : integer := 0;
vco_min : integer := 0;
vco_max : integer := 0;
vco_center : integer := 0;
-- ADVANCED USER PARAMETERS
m_initial : integer := 1;
m : integer := 1;
n : integer := 1;
m2 : integer := 1;
n2 : integer := 1;
ss : integer := 0;
c0_high : integer := 1;
c0_low : integer := 1;
c0_initial : integer := 1;
c0_mode : string := "bypass";
c0_ph : integer := 0;
c1_high : integer := 1;
c1_low : integer := 1;
c1_initial : integer := 1;
c1_mode : string := "bypass";
c1_ph : integer := 0;
c2_high : integer := 1;
c2_low : integer := 1;
c2_initial : integer := 1;
c2_mode : string := "bypass";
c2_ph : integer := 0;
c3_high : integer := 1;
c3_low : integer := 1;
c3_initial : integer := 1;
c3_mode : string := "bypass";
c3_ph : integer := 0;
c4_high : integer := 1;
c4_low : integer := 1;
c4_initial : integer := 1;
c4_mode : string := "bypass";
c4_ph : integer := 0;
c5_high : integer := 1;
c5_low : integer := 1;
c5_initial : integer := 1;
c5_mode : string := "bypass";
c5_ph : integer := 0;
m_ph : integer := 0;
clk0_counter : string := "c0";
clk1_counter : string := "c1";
clk2_counter : string := "c2";
clk3_counter : string := "c3";
clk4_counter : string := "c4";
clk5_counter : string := "c5";
c1_use_casc_in : string := "off";
c2_use_casc_in : string := "off";
c3_use_casc_in : string := "off";
c4_use_casc_in : string := "off";
c5_use_casc_in : string := "off";
m_test_source : integer := 5;
c0_test_source : integer := 5;
c1_test_source : integer := 5;
c2_test_source : integer := 5;
c3_test_source : integer := 5;
c4_test_source : integer := 5;
c5_test_source : integer := 5;
-- LVDS mode parameters
enable0_counter : string := "c0";
enable1_counter : string := "c1";
sclkout0_phase_shift : string := "0";
sclkout1_phase_shift : string := "0";
charge_pump_current : integer := 0;
loop_filter_r : string := " 1.000000";
loop_filter_c : integer := 1;
common_rx_tx : string := "off";
rx_outclock_resource : string := "auto";
use_vco_bypass : string := "false";
use_dc_coupling : string := "false";
pll_compensation_delay : integer := 0;
simulation_type : string := "functional";
lpm_type : string := "stratixii_pll";
clk0_use_even_counter_mode : string := "off";
clk1_use_even_counter_mode : string := "off";
clk2_use_even_counter_mode : string := "off";
clk3_use_even_counter_mode : string := "off";
clk4_use_even_counter_mode : string := "off";
clk5_use_even_counter_mode : string := "off";
clk0_use_even_counter_value : string := "off";
clk1_use_even_counter_value : string := "off";
clk2_use_even_counter_value : string := "off";
clk3_use_even_counter_value : string := "off";
clk4_use_even_counter_value : string := "off";
clk5_use_even_counter_value : string := "off";
vco_multiply_by : integer := 0;
vco_divide_by : integer := 0;
vco_post_scale : integer := 1;
-- VITAL generics
XOn : Boolean := DefGlitchXOn;
MsgOn : Boolean := DefGlitchMsgOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
TimingChecksOn : Boolean := true;
InstancePath : STRING := "*";
tipd_inclk : VitalDelayArrayType01(1 downto 0) := (OTHERS => DefPropDelay01);
tipd_ena : VitalDelayType01 := DefPropDelay01;
tipd_pfdena : VitalDelayType01 := DefPropDelay01;
tipd_areset : VitalDelayType01 := DefPropDelay01;
tipd_fbin : VitalDelayType01 := DefPropDelay01;
tipd_scanclk : VitalDelayType01 := DefPropDelay01;
tipd_scanread : VitalDelayType01 := DefPropDelay01;
tipd_scandata : VitalDelayType01 := DefPropDelay01;
tipd_scanwrite : VitalDelayType01 := DefPropDelay01;
tipd_clkswitch : VitalDelayType01 := DefPropDelay01;
tsetup_scandata_scanclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_scandata_scanclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_scanread_scanclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_scanread_scanclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_scanwrite_scanclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_scanwrite_scanclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst
);
PORT
(
inclk : in std_logic_vector(1 downto 0);
fbin : in std_logic := '0';
ena : in std_logic := '1';
clkswitch : in std_logic := '0';
areset : in std_logic := '0';
pfdena : in std_logic := '1';
scanread : in std_logic := '0';
scanwrite : in std_logic := '0';
scandata : in std_logic := '0';
scanclk : in std_logic := '0';
testin : in std_logic_vector(3 downto 0) := "0000";
clk : out std_logic_vector(5 downto 0);
clkbad : out std_logic_vector(1 downto 0);
activeclock : out std_logic;
locked : out std_logic;
clkloss : out std_logic;
scandataout : out std_logic;
scandone : out std_logic;
testupout : out std_logic;
testdownout : out std_logic;
-- lvds specific ports
enable0 : out std_logic;
enable1 : out std_logic;
sclkout : out std_logic_vector(1 downto 0)
);
END stratixii_pll;
ARCHITECTURE vital_pll of stratixii_pll is
TYPE int_array is ARRAY(NATURAL RANGE <>) of integer;
TYPE str_array is ARRAY(NATURAL RANGE <>) of string(1 to 6);
TYPE str_array1 is ARRAY(NATURAL RANGE <>) of string(1 to 9);
TYPE std_logic_array is ARRAY(NATURAL RANGE <>) of std_logic;
-- internal advanced parameter signals
signal i_vco_min : integer;
signal i_vco_max : integer;
signal i_vco_center : integer;
signal i_pfd_min : integer;
signal i_pfd_max : integer;
signal c_ph_val : int_array(0 to 5) := (OTHERS => 0);
signal c_high_val : int_array(0 to 5) := (OTHERS => 1);
signal c_low_val : int_array(0 to 5) := (OTHERS => 1);
signal c_initial_val : int_array(0 to 5) := (OTHERS => 1);
signal c_mode_val : str_array(0 to 5);
-- old values
signal c_high_val_old : int_array(0 to 5) := (OTHERS => 1);
signal c_low_val_old : int_array(0 to 5) := (OTHERS => 1);
signal c_ph_val_old : int_array(0 to 5) := (OTHERS => 0);
signal c_mode_val_old : str_array(0 to 5);
-- hold registers
signal c_high_val_hold : int_array(0 to 5) := (OTHERS => 1);
signal c_low_val_hold : int_array(0 to 5) := (OTHERS => 1);
signal c_ph_val_hold : int_array(0 to 5) := (OTHERS => 0);
signal c_mode_val_hold : str_array(0 to 5);
-- temp registers
signal sig_c_ph_val_tmp : int_array(0 to 5) := (OTHERS => 0);
signal sig_c_low_val_tmp : int_array(0 to 5) := (OTHERS => 1);
signal c_ph_val_orig : int_array(0 to 5) := (OTHERS => 0);
--signal i_clk5_counter : string(1 to 2) := "c5";
--signal i_clk4_counter : string(1 to 2) := "c4";
--signal i_clk3_counter : string(1 to 2) := "c3";
--signal i_clk2_counter : string(1 to 2) := "c2";
--signal i_clk1_counter : string(1 to 2) := "c1";
--signal i_clk0_counter : string(1 to 2) := "c0";
signal i_clk5_counter : integer := 5;
signal i_clk4_counter : integer := 4;
signal i_clk3_counter : integer := 3;
signal i_clk2_counter : integer := 2;
signal i_clk1_counter : integer := 1;
signal i_clk0_counter : integer := 0;
signal i_charge_pump_current : integer;
signal i_loop_filter_r : integer;
-- end internal advanced parameter signals
-- CONSTANTS
CONSTANT GPP_SCAN_CHAIN : integer := 174;
CONSTANT FAST_SCAN_CHAIN : integer := 75;
CONSTANT cntrs : str_array(5 downto 0) := (" C5", " C4", " C3", " C2", " C1", " C0");
CONSTANT ss_cntrs : str_array(0 to 3) := (" M", " M2", " N", " N2");
CONSTANT loop_filter_c_arr : int_array(0 to 3) := (57, 16, 36, 5);
CONSTANT fpll_loop_filter_c_arr : int_array(0 to 3) := (18, 13, 8, 2);
CONSTANT charge_pump_curr_arr : int_array(0 to 15) := (6, 12, 30, 36, 52, 57, 72, 77, 92, 96, 110, 114, 127, 131, 144, 148);
CONSTANT loop_filter_r_arr : str_array1(0 to 39) := (" 1.000000", " 1.500000", " 2.000000", " 2.500000", " 3.000000", " 3.500000", " 4.000000", " 4.500000", " 5.000000", " 5.500000", " 6.000000", " 6.500000", " 7.000000", " 7.500000", " 8.000000", " 8.500000", " 9.000000", " 9.500000", "10.000000", "10.500000", "11.000000", "11.500000", "12.000000", "12.500000", "13.000000", "13.500000", "14.000000", "14.500000", "15.000000", "15.500000", "16.000000", "16.500000", "17.000000", "17.500000", "18.000000", "18.500000", "19.000000", "19.500000", "20.000000", "20.500000");
-- signals
signal vcc : std_logic := '1';
signal fbclk : std_logic;
signal refclk : std_logic;
--signal c0_clk : std_logic;
--signal c1_clk : std_logic;
--signal c2_clk : std_logic;
--signal c3_clk : std_logic;
--signal c4_clk : std_logic;
--signal c5_clk : std_logic;
signal c_clk : std_logic_array(0 to 5);
signal vco_out : std_logic_vector(7 downto 0) := (OTHERS => '0');
-- signals to assign values to counter params
signal m_val : int_array(0 to 1) := (OTHERS => 1);
signal n_val : int_array(0 to 1) := (OTHERS => 1);
signal m_ph_val : integer := 0;
signal m_initial_val : integer := m_initial;
signal m_mode_val : str_array(0 to 1) := (OTHERS => " ");
signal n_mode_val : str_array(0 to 1) := (OTHERS => " ");
signal lfc_val : integer := 0;
signal cp_curr_val : integer := 0;
signal lfr_val : string(1 to 9) := " ";
-- old values
signal m_val_old : int_array(0 to 1) := (OTHERS => 1);
signal n_val_old : int_array(0 to 1) := (OTHERS => 1);
signal m_mode_val_old : str_array(0 to 1) := (OTHERS => " ");
signal n_mode_val_old : str_array(0 to 1) := (OTHERS => " ");
signal m_ph_val_old : integer := 0;
signal lfc_old : integer := 0;
signal cp_curr_old : integer := 0;
signal lfr_old : string(1 to 9) := " ";
signal num_output_cntrs : integer := 6;
signal scan_data : std_logic_vector(173 downto 0) := (OTHERS => '0');
signal clk0_tmp : std_logic;
signal clk1_tmp : std_logic;
signal clk2_tmp : std_logic;
signal clk3_tmp : std_logic;
signal clk4_tmp : std_logic;
signal clk5_tmp : std_logic;
signal sclkout0_tmp : std_logic;
signal sclkout1_tmp : std_logic;
signal clkin : std_logic := '0';
signal gate_locked : std_logic := '0';
signal lock : std_logic := '0';
signal about_to_lock : boolean := false;
signal reconfig_err : boolean := false;
signal inclk_c0 : std_logic;
signal inclk_c1 : std_logic;
signal inclk_c2 : std_logic;
signal inclk_c3 : std_logic;
signal inclk_c4 : std_logic;
signal inclk_c5 : std_logic;
signal inclk_m : std_logic;
signal devpor : std_logic;
signal devclrn : std_logic;
signal inclk0_ipd : std_logic;
signal inclk1_ipd : std_logic;
signal ena_ipd : std_logic;
signal pfdena_ipd : std_logic;
signal areset_ipd : std_logic;
signal fbin_ipd : std_logic;
signal scanclk_ipd : std_logic;
signal scanread_ipd : std_logic;
signal scanwrite_ipd : std_logic;
signal scandata_ipd : std_logic;
signal clkswitch_ipd : std_logic;
-- registered signals
signal scanread_reg : std_logic := '0';
signal scanwrite_reg : std_logic := '0';
signal scanwrite_enabled : std_logic := '0';
signal gated_scanclk : std_logic := '1';
signal inclk_c0_dly1 : std_logic := '0';
signal inclk_c0_dly2 : std_logic := '0';
signal inclk_c0_dly3 : std_logic := '0';
signal inclk_c0_dly4 : std_logic := '0';
signal inclk_c0_dly5 : std_logic := '0';
signal inclk_c0_dly6 : std_logic := '0';
signal inclk_c1_dly1 : std_logic := '0';
signal inclk_c1_dly2 : std_logic := '0';
signal inclk_c1_dly3 : std_logic := '0';
signal inclk_c1_dly4 : std_logic := '0';
signal inclk_c1_dly5 : std_logic := '0';
signal inclk_c1_dly6 : std_logic := '0';
signal sig_offset : time := 0 ps;
signal sig_refclk_time : time := 0 ps;
signal sig_fbclk_period : time := 0 ps;
signal sig_vco_period_was_phase_adjusted : boolean := false;
signal sig_phase_adjust_was_scheduled : boolean := false;
signal sig_stop_vco : std_logic := '0';
signal sig_m_times_vco_period : time := 0 ps;
signal sig_new_m_times_vco_period : time := 0 ps;
signal sig_got_refclk_posedge : boolean := false;
signal sig_got_fbclk_posedge : boolean := false;
signal sig_got_second_refclk : boolean := false;
signal m_delay : integer := 0;
signal n_delay : integer := 0;
signal inclk1_tmp : std_logic := '0';
signal ext_fbk_cntr_high : integer := 0;
signal ext_fbk_cntr_low : integer := 0;
signal ext_fbk_cntr_ph : integer := 0;
signal ext_fbk_cntr_initial : integer := 1;
signal ext_fbk_cntr : string(1 to 2) := "c0";
signal ext_fbk_cntr_mode : string(1 to 6) := "bypass";
signal ext_fbk_cntr_index : integer := 0;
signal enable0_tmp : std_logic := '0';
signal enable1_tmp : std_logic := '0';
signal reset_low : std_logic := '0';
signal scandataout_tmp : std_logic := '0';
signal scandone_tmp : std_logic := '0';
signal sig_refclk_period : time := (inclk0_input_frequency * 1 ps) * n;
signal schedule_vco : std_logic := '0';
signal areset_ena_sig : std_logic := '0';
signal pll_in_test_mode : boolean := false;
signal inclk_c_from_vco : std_logic_array(0 to 5);
signal inclk_m_from_vco : std_logic;
signal inclk_sclkout0_from_vco : std_logic;
signal inclk_sclkout1_from_vco : std_logic;
COMPONENT stratixii_mn_cntr
PORT (
clk : IN std_logic;
reset : IN std_logic := '0';
cout : OUT std_logic;
initial_value : IN integer := 1;
modulus : IN integer := 1;
time_delay : IN integer := 0
);
END COMPONENT;
COMPONENT stratixii_scale_cntr
PORT (
clk : IN std_logic;
reset : IN std_logic := '0';
cout : OUT std_logic;
initial : IN integer := 1;
high : IN integer := 1;
low : IN integer := 1;
mode : IN string := "bypass";
ph_tap : IN integer := 0
);
END COMPONENT;
COMPONENT stratixii_dffe
GENERIC(
TimingChecksOn: Boolean := true;
InstancePath: STRING := "*";
XOn: Boolean := DefGlitchXOn;
MsgOn: Boolean := DefGlitchMsgOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks;
tpd_PRN_Q_negedge : VitalDelayType01 := DefPropDelay01;
tpd_CLRN_Q_negedge : VitalDelayType01 := DefPropDelay01;
tpd_CLK_Q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_ENA_Q_posedge : VitalDelayType01 := DefPropDelay01;
tsetup_D_CLK_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_D_CLK_noedge_negedge : VitalDelayType := DefSetupHoldCnst;
tsetup_ENA_CLK_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_D_CLK_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_D_CLK_noedge_negedge : VitalDelayType := DefSetupHoldCnst;
thold_ENA_CLK_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tipd_D : VitalDelayType01 := DefPropDelay01;
tipd_CLRN : VitalDelayType01 := DefPropDelay01;
tipd_PRN : VitalDelayType01 := DefPropDelay01;
tipd_CLK : VitalDelayType01 := DefPropDelay01;
tipd_ENA : VitalDelayType01 := DefPropDelay01);
PORT(
Q : out STD_LOGIC := '0';
D : in STD_LOGIC := '1';
CLRN : in STD_LOGIC := '1';
PRN : in STD_LOGIC := '1';
CLK : in STD_LOGIC := '0';
ENA : in STD_LOGIC := '1');
END COMPONENT;
COMPONENT stratixii_pll_reg
PORT(
Q : out STD_LOGIC := '0';
D : in STD_LOGIC := '1';
CLRN : in STD_LOGIC := '1';
PRN : in STD_LOGIC := '1';
CLK : in STD_LOGIC := '0';
ENA : in STD_LOGIC := '1');
END COMPONENT;
begin
----------------------
-- INPUT PATH DELAYs
----------------------
WireDelay : block
begin
VitalWireDelay (inclk0_ipd, inclk(0), tipd_inclk(0));
VitalWireDelay (inclk1_ipd, inclk(1), tipd_inclk(1));
VitalWireDelay (areset_ipd, areset, tipd_areset);
VitalWireDelay (ena_ipd, ena, tipd_ena);
VitalWireDelay (fbin_ipd, fbin, tipd_fbin);
VitalWireDelay (pfdena_ipd, pfdena, tipd_pfdena);
VitalWireDelay (scanclk_ipd, scanclk, tipd_scanclk);
VitalWireDelay (scanread_ipd, scanread, tipd_scanread);
VitalWireDelay (scandata_ipd, scandata, tipd_scandata);
VitalWireDelay (scanwrite_ipd, scanwrite, tipd_scanwrite);
VitalWireDelay (clkswitch_ipd, clkswitch, tipd_clkswitch);
end block;
inclk_m <= clkin when m_test_source = 0 else
clk0_tmp when operation_mode = "external_feedback" and feedback_source = "clk0" else
clk1_tmp when operation_mode = "external_feedback" and feedback_source = "clk1" else
clk2_tmp when operation_mode = "external_feedback" and feedback_source = "clk2" else
clk3_tmp when operation_mode = "external_feedback" and feedback_source = "clk3" else
clk4_tmp when operation_mode = "external_feedback" and feedback_source = "clk4" else
clk5_tmp when operation_mode = "external_feedback" and feedback_source = "clk5" else
inclk_m_from_vco;
ext_fbk_cntr_high <= c_high_val(ext_fbk_cntr_index);
ext_fbk_cntr_low <= c_low_val(ext_fbk_cntr_index);
ext_fbk_cntr_ph <= c_ph_val(ext_fbk_cntr_index);
ext_fbk_cntr_initial <= c_initial_val(ext_fbk_cntr_index);
ext_fbk_cntr_mode <= c_mode_val(ext_fbk_cntr_index);
areset_ena_sig <= areset_ipd or (not ena_ipd) or sig_stop_vco;
pll_in_test_mode <= true when m_test_source /= 5 or c0_test_source /= 5 or
c1_test_source /= 5 or c2_test_source /= 5 or
c3_test_source /= 5 or c4_test_source /= 5 or
c5_test_source /= 5 else
false;
m1 : stratixii_mn_cntr
port map ( clk => inclk_m,
reset => areset_ena_sig,
cout => fbclk,
initial_value => m_initial_val,
modulus => m_val(0),
time_delay => m_delay
);
-- add delta delay to inclk1 to ensure inclk0 and inclk1 are processed
-- in different simulation deltas.
inclk1_tmp <= inclk1_ipd;
process (inclk0_ipd, inclk1_tmp, clkswitch_ipd)
variable input_value : std_logic := '0';
variable current_clock : integer := 0;
variable clk0_count, clk1_count : integer := 0;
variable clk0_is_bad, clk1_is_bad : std_logic := '0';
variable primary_clk_is_bad : boolean := false;
variable current_clk_is_bad : boolean := false;
variable got_curr_clk_falling_edge_after_clkswitch : boolean := false;
variable switch_over_count : integer := 0;
variable active_clock : std_logic := '0';
variable external_switch : boolean := false;
begin
if (now = 0 ps) then
if (switch_over_type = "manual" and clkswitch_ipd = '1') then
current_clock := 1;
active_clock := '1';
end if;
end if;
if (clkswitch_ipd'event and clkswitch_ipd = '1' and switch_over_type = "auto") then
external_switch := true;
elsif (switch_over_type = "manual") then
if (clkswitch_ipd'event and clkswitch_ipd = '1') then
current_clock := 1;
active_clock := '1';
clkin <= transport inclk1_tmp;
elsif (clkswitch_ipd'event and clkswitch_ipd = '0') then
current_clock := 0;
active_clock := '0';
clkin <= transport inclk0_ipd;
end if;
end if;
-- save the current inclk event value
if (inclk0_ipd'event) then
input_value := inclk0_ipd;
elsif (inclk1_tmp'event) then
input_value := inclk1_tmp;
end if;
-- check if either input clk is bad
if (inclk0_ipd'event and inclk0_ipd = '1') then
clk0_count := clk0_count + 1;
clk0_is_bad := '0';
clk1_count := 0;
if (clk0_count > 2) then
-- no event on other clk for 2 cycles
clk1_is_bad := '1';
if (current_clock = 1) then
current_clk_is_bad := true;
end if;
end if;
end if;
if (inclk1_tmp'event and inclk1_tmp = '1') then
clk1_count := clk1_count + 1;
clk1_is_bad := '0';
clk0_count := 0;
if (clk1_count > 2) then
-- no event on other clk for 2 cycles
clk0_is_bad := '1';
if (current_clock = 0) then
current_clk_is_bad := true;
end if;
end if;
end if;
-- check if the bad clk is the primary clock
if (clk0_is_bad = '1') then
primary_clk_is_bad := true;
else
primary_clk_is_bad := false;
end if;
-- actual switching
if (inclk0_ipd'event and current_clock = 0) then
if (external_switch) then
if (not got_curr_clk_falling_edge_after_clkswitch) then
if (inclk0_ipd = '0') then
got_curr_clk_falling_edge_after_clkswitch := true;
end if;
clkin <= transport inclk0_ipd;
end if;
else
clkin <= transport inclk0_ipd;
end if;
elsif (inclk1_tmp'event and current_clock = 1) then
if (external_switch) then
if (not got_curr_clk_falling_edge_after_clkswitch) then
if (inclk1_tmp = '0') then
got_curr_clk_falling_edge_after_clkswitch := true;
end if;
clkin <= transport inclk1_tmp;
end if;
else
clkin <= transport inclk1_tmp;
end if;
else
if (input_value = '1' and switch_over_on_lossclk = "on" and enable_switch_over_counter = "on" and primary_clk_is_bad) then
switch_over_count := switch_over_count + 1;
end if;
if (input_value = '0') then
if (external_switch and (got_curr_clk_falling_edge_after_clkswitch or current_clk_is_bad)) or (switch_over_on_lossclk = "on" and primary_clk_is_bad and (enable_switch_over_counter = "off" or switch_over_count = switch_over_counter)) then
got_curr_clk_falling_edge_after_clkswitch := false;
if (current_clock = 0) then
current_clock := 1;
else
current_clock := 0;
end if;
active_clock := not active_clock;
switch_over_count := 0;
external_switch := false;
current_clk_is_bad := false;
end if;
end if;
end if;
-- schedule outputs
clkbad(0) <= clk0_is_bad;
clkbad(1) <= clk1_is_bad;
if (switch_over_on_lossclk = "on" and clkswitch_ipd /= '1') then
if (primary_clk_is_bad) then
-- assert clkloss
clkloss <= '1';
else
clkloss <= '0';
end if;
else
clkloss <= clkswitch_ipd;
end if;
activeclock <= active_clock;
end process;
process (inclk_sclkout0_from_vco)
begin
sclkout0_tmp <= inclk_sclkout0_from_vco;
end process;
process (inclk_sclkout1_from_vco)
begin
sclkout1_tmp <= inclk_sclkout1_from_vco;
end process;
n1 : stratixii_mn_cntr
port map (
clk => clkin,
reset => areset_ipd,
cout => refclk,
initial_value => n_val(0),
modulus => n_val(0));
inclk_c0 <= clkin when c0_test_source = 0 else
refclk when c0_test_source = 1 else
inclk_c_from_vco(0);
c0 : stratixii_scale_cntr
port map (
clk => inclk_c0,
reset => areset_ena_sig,
cout => c_clk(0),
initial => c_initial_val(0),
high => c_high_val(0),
low => c_low_val(0),
mode => c_mode_val(0),
ph_tap => c_ph_val(0));
inclk_c1 <= clkin when c1_test_source = 0 else
fbclk when c1_test_source = 2 else
c_clk(0) when c1_use_casc_in = "on" else
inclk_c_from_vco(1);
c1 : stratixii_scale_cntr
port map (
clk => inclk_c1,
reset => areset_ena_sig,
cout => c_clk(1),
initial => c_initial_val(1),
high => c_high_val(1),
low => c_low_val(1),
mode => c_mode_val(1),
ph_tap => c_ph_val(1));
inclk_c2 <= clkin when c2_test_source = 0 else
c_clk(1) when c2_use_casc_in = "on" else
inclk_c_from_vco(2);
c2 : stratixii_scale_cntr
port map (
clk => inclk_c2,
reset => areset_ena_sig,
cout => c_clk(2),
initial => c_initial_val(2),
high => c_high_val(2),
low => c_low_val(2),
mode => c_mode_val(2),
ph_tap => c_ph_val(2));
inclk_c3 <= clkin when c3_test_source = 0 else
c_clk(2) when c3_use_casc_in = "on" else
inclk_c_from_vco(3);
c3 : stratixii_scale_cntr
port map (
clk => inclk_c3,
reset => areset_ena_sig,
cout => c_clk(3),
initial => c_initial_val(3),
high => c_high_val(3),
low => c_low_val(3),
mode => c_mode_val(3),
ph_tap => c_ph_val(3));
inclk_c4 <= '0' when (pll_type = "fast") else
clkin when (c4_test_source = 0) else
c_clk(3) when (c4_use_casc_in = "on") else
inclk_c_from_vco(4);
c4 : stratixii_scale_cntr
port map (
clk => inclk_c4,
reset => areset_ena_sig,
cout => c_clk(4),
initial => c_initial_val(4),
high => c_high_val(4),
low => c_low_val(4),
mode => c_mode_val(4),
ph_tap => c_ph_val(4));
inclk_c5 <= '0' when (pll_type = "fast") else
clkin when c5_test_source = 0 else
c_clk(4) when c5_use_casc_in = "on" else
inclk_c_from_vco(5);
c5 : stratixii_scale_cntr
port map (
clk => inclk_c5,
reset => areset_ena_sig,
cout => c_clk(5),
initial => c_initial_val(5),
high => c_high_val(5),
low => c_low_val(5),
mode => c_mode_val(5),
ph_tap => c_ph_val(5));
inclk_c0_dly1 <= inclk_c0 when (pll_type = "fast" or pll_type = "lvds")
else '0';
inclk_c0_dly2 <= inclk_c0_dly1;
inclk_c0_dly3 <= inclk_c0_dly2;
inclk_c0_dly4 <= inclk_c0_dly3;
inclk_c0_dly5 <= inclk_c0_dly4;
inclk_c0_dly6 <= inclk_c0_dly5;
inclk_c1_dly1 <= inclk_c1 when (pll_type = "fast" or pll_type = "lvds")
else '0';
inclk_c1_dly2 <= inclk_c1_dly1;
inclk_c1_dly3 <= inclk_c1_dly2;
inclk_c1_dly4 <= inclk_c1_dly3;
inclk_c1_dly5 <= inclk_c1_dly4;
inclk_c1_dly6 <= inclk_c1_dly5;
process(inclk_c0_dly6, inclk_c1_dly6, areset_ipd, ena_ipd, sig_stop_vco)
variable c0_got_first_rising_edge : boolean := false;
variable c0_count : integer := 2;
variable c0_initial_count : integer := 1;
variable c0_tmp, c1_tmp : std_logic := '0';
variable c1_got_first_rising_edge : boolean := false;
variable c1_count : integer := 2;
variable c1_initial_count : integer := 1;
begin
if (areset_ipd = '1' or ena_ipd = '0' or sig_stop_vco = '1') then
c0_count := 2;
c1_count := 2;
c0_initial_count := 1;
c1_initial_count := 1;
c0_got_first_rising_edge := false;
c1_got_first_rising_edge := false;
else
if (not c0_got_first_rising_edge) then
if (inclk_c0_dly6'event and inclk_c0_dly6 = '1') then
if (c0_initial_count = c_initial_val(0)) then
c0_got_first_rising_edge := true;
else
c0_initial_count := c0_initial_count + 1;
end if;
end if;
elsif (inclk_c0_dly6'event) then
c0_count := c0_count + 1;
if (c0_count = (c_high_val(0) + c_low_val(0)) * 2) then
c0_count := 1;
end if;
end if;
if (inclk_c0_dly6'event and inclk_c0_dly6 = '0') then
if (c0_count = 1) then
c0_tmp := '1';
c0_got_first_rising_edge := false;
else
c0_tmp := '0';
end if;
end if;
if (not c1_got_first_rising_edge) then
if (inclk_c1_dly6'event and inclk_c1_dly6 = '1') then
if (c1_initial_count = c_initial_val(1)) then
c1_got_first_rising_edge := true;
else
c1_initial_count := c1_initial_count + 1;
end if;
end if;
elsif (inclk_c1_dly6'event) then
c1_count := c1_count + 1;
if (c1_count = (c_high_val(1) + c_low_val(1)) * 2) then
c1_count := 1;
end if;
end if;
if (inclk_c1_dly6'event and inclk_c1_dly6 = '0') then
if (c1_count = 1) then
c1_tmp := '1';
c1_got_first_rising_edge := false;
else
c1_tmp := '0';
end if;
end if;
end if;
if (enable0_counter = "c0") then
enable0_tmp <= c0_tmp;
elsif (enable0_counter = "c1") then
enable0_tmp <= c1_tmp;
else
enable0_tmp <= '0';
end if;
if (enable1_counter = "c0") then
enable1_tmp <= c0_tmp;
elsif (enable1_counter = "c1") then
enable1_tmp <= c1_tmp;
else
enable1_tmp <= '0';
end if;
end process;
glocked_cntr : process(clkin, ena_ipd, areset_ipd)
variable count : integer := 0;
variable output : std_logic := '0';
begin
if (areset_ipd = '1') then
count := 0;
output := '0';
elsif (clkin'event and clkin = '1') then
if (ena_ipd = '1') then
count := count + 1;
if (count = gate_lock_counter) then
output := '1';
end if;
end if;
end if;
gate_locked <= output;
end process;
locked <= gate_locked and lock when gate_lock_signal = "yes" else
lock;
process (scandone_tmp)
variable buf : line;
begin
if (scandone_tmp'event and scandone_tmp = '1') then
if (reconfig_err = false) then
ASSERT false REPORT "PLL Reprogramming completed with the following values (Values in parantheses indicate values before reprogramming) :" severity note;
write (buf, string'(" N modulus = "));
write (buf, n_val(0));
write (buf, string'(" ( "));
write (buf, n_val_old(0));
write (buf, string'(" )"));
writeline (output, buf);
write (buf, string'(" M modulus = "));
write (buf, m_val(0));
write (buf, string'(" ( "));
write (buf, m_val_old(0));
write (buf, string'(" )"));
writeline (output, buf);
write (buf, string'(" M ph_tap = "));
write (buf, m_ph_val);
write (buf, string'(" ( "));
write (buf, m_ph_val_old);
write (buf, string'(" )"));
writeline (output, buf);
if (ss > 0) then
write (buf, string'(" M2 modulus = "));
write (buf, m_val(1));
write (buf, string'(" ( "));
write (buf, m_val_old(1));
write (buf, string'(" )"));
writeline (output, buf);
write (buf, string'(" N2 modulus = "));
write (buf, n_val(1));
write (buf, string'(" ( "));
write (buf, n_val_old(1));
write (buf, string'(" )"));
writeline (output, buf);
end if;
for i in 0 to (num_output_cntrs-1) loop
write (buf, cntrs(i));
write (buf, string'(" : high = "));
write (buf, c_high_val(i));
write (buf, string'(" ("));
write (buf, c_high_val_old(i));
write (buf, string'(") "));
write (buf, string'(" , low = "));
write (buf, sig_c_low_val_tmp(i));
write (buf, string'(" ("));
write (buf, c_low_val_old(i));
write (buf, string'(") "));
write (buf, string'(" , mode = "));
write (buf, c_mode_val(i));
write (buf, string'(" ("));
write (buf, c_mode_val_old(i));
write (buf, string'(") "));
write (buf, string'(" , phase tap = "));
write (buf, c_ph_val(i));
write (buf, string'(" ("));
write (buf, c_ph_val_old(i));
write (buf, string'(") "));
writeline(output, buf);
end loop;
write (buf, string'(" Charge Pump Current (uA) = "));
write (buf, cp_curr_val);
write (buf, string'(" ( "));
write (buf, cp_curr_old);
write (buf, string'(" ) "));
writeline (output, buf);
write (buf, string'(" Loop Filter Capacitor (pF) = "));
write (buf, lfc_val);
write (buf, string'(" ( "));
write (buf, lfc_old);
write (buf, string'(" ) "));
writeline (output, buf);
write (buf, string'(" Loop Filter Resistor (Kohm) = "));
write (buf, lfr_val);
write (buf, string'(" ( "));
write (buf, lfr_old);
write (buf, string'(" ) "));
writeline (output, buf);
else ASSERT false REPORT "Errors were encountered during PLL reprogramming. Please refer to error/warning messages above." severity warning;
end if;
end if;
end process;
process (scanwrite_enabled, c_clk(0), c_clk(1), c_clk(2), c_clk(3), c_clk(4), c_clk(5), vco_out, fbclk, scanclk_ipd, gated_scanclk)
variable init : boolean := true;
variable low, high : std_logic_vector(7 downto 0);
variable low_fast, high_fast : std_logic_vector(3 downto 0);
variable mode : string(1 to 6) := "bypass";
variable is_error : boolean := false;
variable m_tmp, n_tmp : std_logic_vector(8 downto 0);
variable n_fast : std_logic_vector(1 downto 0);
variable c_high_val_tmp : int_array(0 to 5) := (OTHERS => 1);
variable c_low_val_tmp : int_array(0 to 5) := (OTHERS => 1);
variable c_ph_val_tmp : int_array(0 to 5) := (OTHERS => 0);
variable c_mode_val_tmp : str_array(0 to 5);
variable m_ph_val_tmp : integer := 0;
variable m_val_tmp : int_array(0 to 1) := (OTHERS => 1);
variable c0_rising_edge_transfer_done : boolean := false;
variable c1_rising_edge_transfer_done : boolean := false;
variable c2_rising_edge_transfer_done : boolean := false;
variable c3_rising_edge_transfer_done : boolean := false;
variable c4_rising_edge_transfer_done : boolean := false;
variable c5_rising_edge_transfer_done : boolean := false;
-- variables for scaling of multiply_by and divide_by values
variable i_clk0_mult_by : integer := 1;
variable i_clk0_div_by : integer := 1;
variable i_clk1_mult_by : integer := 1;
variable i_clk1_div_by : integer := 1;
variable i_clk2_mult_by : integer := 1;
variable i_clk2_div_by : integer := 1;
variable i_clk3_mult_by : integer := 1;
variable i_clk3_div_by : integer := 1;
variable i_clk4_mult_by : integer := 1;
variable i_clk4_div_by : integer := 1;
variable i_clk5_mult_by : integer := 1;
variable i_clk5_div_by : integer := 1;
variable max_d_value : integer := 1;
variable new_multiplier : integer := 1;
-- internal variables for storing the phase shift number.(used in lvds mode only)
variable i_clk0_phase_shift : integer := 1;
variable i_clk1_phase_shift : integer := 1;
variable i_clk2_phase_shift : integer := 1;
-- user to advanced variables
variable max_neg_abs : integer := 0;
variable i_m_initial : integer;
variable i_m : integer := 1;
variable i_n : integer := 1;
variable i_m2 : integer;
variable i_n2 : integer;
variable i_ss : integer;
variable i_c_high : int_array(0 to 5);
variable i_c_low : int_array(0 to 5);
variable i_c_initial : int_array(0 to 5);
variable i_c_ph : int_array(0 to 5);
variable i_c_mode : str_array(0 to 5);
variable i_m_ph : integer;
variable output_count : integer;
variable new_divisor : integer;
variable clk0_cntr : string(1 to 2) := "c0";
variable clk1_cntr : string(1 to 2) := "c1";
variable clk2_cntr : string(1 to 2) := "c2";
variable clk3_cntr : string(1 to 2) := "c3";
variable clk4_cntr : string(1 to 2) := "c4";
variable clk5_cntr : string(1 to 2) := "c5";
variable fbk_cntr : string(1 to 2);
variable fbk_cntr_index : integer;
variable start_bit : integer;
variable quiet_time : time := 0 ps;
variable slowest_clk_old : time := 0 ps;
variable slowest_clk_new : time := 0 ps;
variable tmp_scan_data : std_logic_vector(173 downto 0) := (OTHERS => '0');
variable m_lo, m_hi : std_logic_vector(4 downto 0);
variable j : integer := 0;
variable scanread_active_edge : time := 0 ps;
variable got_first_scanclk : boolean := false;
variable got_first_gated_scanclk : boolean := false;
variable scanclk_last_rising_edge : time := 0 ps;
variable scanclk_period : time := 0 ps;
variable current_scan_data : std_logic_vector(173 downto 0) := (OTHERS => '0');
variable index : integer := 0;
variable Tviol_scandata_scanclk : std_ulogic := '0';
variable Tviol_scanread_scanclk : std_ulogic := '0';
variable Tviol_scanwrite_scanclk : std_ulogic := '0';
variable TimingData_scandata_scanclk : VitalTimingDataType := VitalTimingDataInit;
variable TimingData_scanread_scanclk : VitalTimingDataType := VitalTimingDataInit;
variable TimingData_scanwrite_scanclk : VitalTimingDataType := VitalTimingDataInit;
variable scan_chain_length : integer := GPP_SCAN_CHAIN;
variable tmp_rem : integer := 0;
variable scanclk_cycles : integer := 0;
variable lfc_tmp : std_logic_vector(1 downto 0);
variable lfr_tmp : std_logic_vector(5 downto 0);
variable lfr_int : integer := 0;
function slowest_clk (
C0 : integer; C0_mode : string(1 to 6);
C1 : integer; C1_mode : string(1 to 6);
C2 : integer; C2_mode : string(1 to 6);
C3 : integer; C3_mode : string(1 to 6);
C4 : integer; C4_mode : string(1 to 6);
C5 : integer; C5_mode : string(1 to 6);
refclk : time; m_mod : integer) return time is
variable max_modulus : integer := 1;
variable q_period : time := 0 ps;
variable refclk_int : integer := 0;
begin
if (C0_mode /= "bypass" and C0_mode /= " off") then
max_modulus := C0;
end if;
if (C1 > max_modulus and C1_mode /= "bypass" and C1_mode /= " off") then
max_modulus := C1;
end if;
if (C2 > max_modulus and C2_mode /= "bypass" and C2_mode /= " off") then
max_modulus := C2;
end if;
if (C3 > max_modulus and C3_mode /= "bypass" and C3_mode /= " off") then
max_modulus := C3;
end if;
if (C4 > max_modulus and C4_mode /= "bypass" and C4_mode /= " off") then
max_modulus := C4;
end if;
if (C5 > max_modulus and C5_mode /= "bypass" and C5_mode /= " off") then
max_modulus := C5;
end if;
refclk_int := refclk / 1 ps;
if (m_mod /= 0) then
q_period := (refclk_int * max_modulus / m_mod) * 1 ps;
end if;
return (2*q_period);
end slowest_clk;
function int2bin (arg : integer; size : integer) return std_logic_vector is
variable int_val : integer := arg;
variable result : std_logic_vector(size-1 downto 0);
begin
for i in 0 to result'left loop
if ((int_val mod 2) = 0) then
result(i) := '0';
else
result(i) := '1';
end if;
int_val := int_val/2;
end loop;
return result;
end int2bin;
function extract_cntr_index (arg:string) return integer is
variable index : integer := 0;
begin
if (arg(2) = '0') then
index := 0;
elsif (arg(2) = '1') then
index := 1;
elsif (arg(2) = '2') then
index := 2;
elsif (arg(2) = '3') then
index := 3;
elsif (arg(2) = '4') then
index := 4;
else index := 5;
end if;
return index;
end extract_cntr_index;
begin
if (init) then
if (m = 0) then
clk5_cntr := "c5";
clk4_cntr := "c4";
clk3_cntr := "c3";
clk2_cntr := "c2";
clk1_cntr := "c1";
clk0_cntr := "c0";
else
clk5_cntr := clk5_counter;
clk4_cntr := clk4_counter;
clk3_cntr := clk3_counter;
clk2_cntr := clk2_counter;
clk1_cntr := clk1_counter;
clk0_cntr := clk0_counter;
end if;
if (operation_mode = "external_feedback") then
if (feedback_source = "clk0") then
fbk_cntr := clk0_cntr;
elsif (feedback_source = "clk1") then
fbk_cntr := clk1_cntr;
elsif (feedback_source = "clk2") then
fbk_cntr := clk2_cntr;
elsif (feedback_source = "clk3") then
fbk_cntr := clk3_cntr;
elsif (feedback_source = "clk4") then
fbk_cntr := clk4_cntr;
elsif (feedback_source = "clk5") then
fbk_cntr := clk5_cntr;
else
fbk_cntr := "c0";
end if;
if (fbk_cntr = "c0") then
fbk_cntr_index := 0;
elsif (fbk_cntr = "c1") then
fbk_cntr_index := 1;
elsif (fbk_cntr = "c2") then
fbk_cntr_index := 2;
elsif (fbk_cntr = "c3") then
fbk_cntr_index := 3;
elsif (fbk_cntr = "c4") then
fbk_cntr_index := 4;
elsif (fbk_cntr = "c5") then
fbk_cntr_index := 5;
end if;
ext_fbk_cntr <= fbk_cntr;
ext_fbk_cntr_index <= fbk_cntr_index;
end if;
i_clk0_counter <= extract_cntr_index(clk0_cntr);
i_clk1_counter <= extract_cntr_index(clk1_cntr);
i_clk2_counter <= extract_cntr_index(clk2_cntr);
i_clk3_counter <= extract_cntr_index(clk3_cntr);
i_clk4_counter <= extract_cntr_index(clk4_cntr);
i_clk5_counter <= extract_cntr_index(clk5_cntr);
if (m = 0) then -- convert user parameters to advanced
-- set the limit of the divide_by value that can be returned by
-- the following function.
max_d_value := 500;
-- scale down the multiply_by and divide_by values provided by the design
-- before attempting to use them in the calculations below
find_simple_integer_fraction(clk0_multiply_by, clk0_divide_by,
max_d_value, i_clk0_mult_by, i_clk0_div_by);
find_simple_integer_fraction(clk1_multiply_by, clk1_divide_by,
max_d_value, i_clk1_mult_by, i_clk1_div_by);
find_simple_integer_fraction(clk2_multiply_by, clk2_divide_by,
max_d_value, i_clk2_mult_by, i_clk2_div_by);
find_simple_integer_fraction(clk3_multiply_by, clk3_divide_by,
max_d_value, i_clk3_mult_by, i_clk3_div_by);
find_simple_integer_fraction(clk4_multiply_by, clk4_divide_by,
max_d_value, i_clk4_mult_by, i_clk4_div_by);
find_simple_integer_fraction(clk5_multiply_by, clk5_divide_by,
max_d_value, i_clk5_mult_by, i_clk5_div_by);
if (((pll_type = "fast") or (pll_type = "lvds")) and ((vco_multiply_by /= 0) and (vco_divide_by /= 0))) then
i_n := vco_divide_by;
i_m := vco_multiply_by;
else
i_n := 1;
i_m := lcm (i_clk0_mult_by, i_clk1_mult_by,
i_clk2_mult_by, i_clk3_mult_by,
i_clk4_mult_by, i_clk5_mult_by,
1, 1, 1, 1, inclk0_input_frequency);
end if;
if (pll_type = "flvds") then
-- Need to readjust phase shift values when the clock multiply value has been readjusted.
new_multiplier := clk0_multiply_by / i_clk0_mult_by;
i_clk0_phase_shift := str2int(clk0_phase_shift) * new_multiplier;
i_clk1_phase_shift := str2int(clk1_phase_shift) * new_multiplier;
i_clk2_phase_shift := str2int(clk2_phase_shift) * new_multiplier;
else
i_clk0_phase_shift := str2int(clk0_phase_shift);
i_clk1_phase_shift := str2int(clk1_phase_shift);
i_clk2_phase_shift := str2int(clk2_phase_shift);
end if;
max_neg_abs := maxnegabs(i_clk0_phase_shift,
i_clk1_phase_shift,
i_clk2_phase_shift,
str2int(clk3_phase_shift),
str2int(clk4_phase_shift),
str2int(clk5_phase_shift),
0, 0, 0, 0);
i_m_ph := counter_ph(get_phase_degree(max_neg_abs,inclk0_input_frequency), i_m, i_n);
i_c_ph(0) := counter_ph(get_phase_degree(ph_adjust(i_clk0_phase_shift,max_neg_abs),inclk0_input_frequency), i_m, i_n);
i_c_ph(1) := counter_ph(get_phase_degree(ph_adjust(i_clk1_phase_shift,max_neg_abs),inclk0_input_frequency), i_m, i_n);
i_c_ph(2) := counter_ph(get_phase_degree(ph_adjust(i_clk2_phase_shift,max_neg_abs),inclk0_input_frequency), i_m, i_n);
i_c_ph(3) := counter_ph(get_phase_degree(ph_adjust(str2int(clk3_phase_shift),max_neg_abs),inclk0_input_frequency), i_m, i_n);
i_c_ph(4) := counter_ph(get_phase_degree(ph_adjust(str2int(clk4_phase_shift),max_neg_abs),inclk0_input_frequency), i_m, i_n);
i_c_ph(5) := counter_ph(get_phase_degree(ph_adjust(str2int(clk5_phase_shift),max_neg_abs),inclk0_input_frequency), i_m, i_n);
i_c_high(0) := counter_high(output_counter_value(i_clk0_div_by,
i_clk0_mult_by, i_m, i_n), clk0_duty_cycle);
i_c_high(1) := counter_high(output_counter_value(i_clk1_div_by,
i_clk1_mult_by, i_m, i_n), clk1_duty_cycle);
i_c_high(2) := counter_high(output_counter_value(i_clk2_div_by,
i_clk2_mult_by, i_m, i_n), clk2_duty_cycle);
i_c_high(3) := counter_high(output_counter_value(i_clk3_div_by,
i_clk3_mult_by, i_m, i_n), clk3_duty_cycle);
i_c_high(4) := counter_high(output_counter_value(i_clk4_div_by,
i_clk4_mult_by, i_m, i_n), clk4_duty_cycle);
i_c_high(5) := counter_high(output_counter_value(i_clk5_div_by,
i_clk5_mult_by, i_m, i_n), clk5_duty_cycle);
i_c_low(0) := counter_low(output_counter_value(i_clk0_div_by,
i_clk0_mult_by, i_m, i_n), clk0_duty_cycle);
i_c_low(1) := counter_low(output_counter_value(i_clk1_div_by,
i_clk1_mult_by, i_m, i_n), clk1_duty_cycle);
i_c_low(2) := counter_low(output_counter_value(i_clk2_div_by,
i_clk2_mult_by, i_m, i_n), clk2_duty_cycle);
i_c_low(3) := counter_low(output_counter_value(i_clk3_div_by,
i_clk3_mult_by, i_m, i_n), clk3_duty_cycle);
i_c_low(4) := counter_low(output_counter_value(i_clk4_div_by,
i_clk4_mult_by, i_m, i_n), clk4_duty_cycle);
i_c_low(5) := counter_low(output_counter_value(i_clk5_div_by,
i_clk5_mult_by, i_m, i_n), clk5_duty_cycle);
i_m_initial := counter_initial(get_phase_degree(max_neg_abs, inclk0_input_frequency), i_m,i_n);
i_c_initial(0) := counter_initial(get_phase_degree(ph_adjust(i_clk0_phase_shift, max_neg_abs), inclk0_input_frequency), i_m, i_n);
i_c_initial(1) := counter_initial(get_phase_degree(ph_adjust(i_clk1_phase_shift, max_neg_abs), inclk0_input_frequency), i_m, i_n);
i_c_initial(2) := counter_initial(get_phase_degree(ph_adjust(i_clk2_phase_shift, max_neg_abs), inclk0_input_frequency), i_m, i_n);
i_c_initial(3) := counter_initial(get_phase_degree(ph_adjust(str2int(clk3_phase_shift), max_neg_abs), inclk0_input_frequency), i_m, i_n);
i_c_initial(4) := counter_initial(get_phase_degree(ph_adjust(str2int(clk4_phase_shift), max_neg_abs), inclk0_input_frequency), i_m, i_n);
i_c_initial(5) := counter_initial(get_phase_degree(ph_adjust(str2int(clk5_phase_shift), max_neg_abs), inclk0_input_frequency), i_m, i_n);
i_c_mode(0) := counter_mode(clk0_duty_cycle, output_counter_value(i_clk0_div_by, i_clk0_mult_by, i_m, i_n));
i_c_mode(1) := counter_mode(clk1_duty_cycle, output_counter_value(i_clk1_div_by, i_clk1_mult_by, i_m, i_n));
i_c_mode(2) := counter_mode(clk2_duty_cycle, output_counter_value(i_clk2_div_by, i_clk2_mult_by, i_m, i_n));
i_c_mode(3) := counter_mode(clk3_duty_cycle, output_counter_value(i_clk3_div_by, i_clk3_mult_by, i_m, i_n));
i_c_mode(4) := counter_mode(clk4_duty_cycle, output_counter_value(i_clk4_div_by, i_clk4_mult_by, i_m, i_n));
i_c_mode(5) := counter_mode(clk5_duty_cycle, output_counter_value(i_clk5_div_by, i_clk5_mult_by, i_m, i_n));
-- in external feedback mode, need to adjust M value to take
-- into consideration the external feedback counter value
if(operation_mode = "external_feedback") then
-- if there is a negative phase shift, m_initial can
-- only be 1
if (max_neg_abs > 0) then
i_m_initial := 1;
end if;
-- calculate the feedback counter multiplier
if (i_c_mode(fbk_cntr_index) = "bypass") then
output_count := 1;
else
output_count := i_c_high(fbk_cntr_index) + i_c_low(fbk_cntr_index);
end if;
new_divisor := gcd(i_m, output_count);
i_m := i_m / new_divisor;
i_n := output_count / new_divisor;
end if;
else -- m /= 0
i_n := n;
i_m := m;
i_m_initial := m_initial;
i_m_ph := m_ph;
i_c_ph(0) := c0_ph;
i_c_ph(1) := c1_ph;
i_c_ph(2) := c2_ph;
i_c_ph(3) := c3_ph;
i_c_ph(4) := c4_ph;
i_c_ph(5) := c5_ph;
i_c_high(0) := c0_high;
i_c_high(1) := c1_high;
i_c_high(2) := c2_high;
i_c_high(3) := c3_high;
i_c_high(4) := c4_high;
i_c_high(5) := c5_high;
i_c_low(0) := c0_low;
i_c_low(1) := c1_low;
i_c_low(2) := c2_low;
i_c_low(3) := c3_low;
i_c_low(4) := c4_low;
i_c_low(5) := c5_low;
i_c_initial(0) := c0_initial;
i_c_initial(1) := c1_initial;
i_c_initial(2) := c2_initial;
i_c_initial(3) := c3_initial;
i_c_initial(4) := c4_initial;
i_c_initial(5) := c5_initial;
i_c_mode(0) := translate_string(c0_mode);
i_c_mode(1) := translate_string(c1_mode);
i_c_mode(2) := translate_string(c2_mode);
i_c_mode(3) := translate_string(c3_mode);
i_c_mode(4) := translate_string(c4_mode);
i_c_mode(5) := translate_string(c5_mode);
end if; -- user to advanced conversion.
m_initial_val <= i_m_initial;
n_val(0) <= i_n;
m_val(0) <= i_m;
m_val(1) <= m2;
n_val(1) <= n2;
if (i_m = 1) then
m_mode_val(0) <= "bypass";
else
m_mode_val(0) <= " ";
end if;
if (m2 = 1) then
m_mode_val(1) <= "bypass";
end if;
if (i_n = 1) then
n_mode_val(0) <= "bypass";
end if;
if (n2 = 1) then
n_mode_val(1) <= "bypass";
end if;
m_ph_val <= i_m_ph;
m_ph_val_tmp := i_m_ph;
m_val_tmp := m_val;
for i in 0 to 5 loop
if (i_c_mode(i) = "bypass") then
if (pll_type = "fast" or pll_type = "lvds") then
i_c_high(i) := 16;
i_c_low(i) := 16;
else
i_c_high(i) := 256;
i_c_low(i) := 256;
end if;
end if;
c_ph_val(i) <= i_c_ph(i);
c_initial_val(i) <= i_c_initial(i);
c_high_val(i) <= i_c_high(i);
c_low_val(i) <= i_c_low(i);
c_mode_val(i) <= i_c_mode(i);
c_high_val_tmp(i) := i_c_high(i);
c_low_val_tmp(i) := i_c_low(i);
c_mode_val_tmp(i) := i_c_mode(i);
c_ph_val_tmp(i) := i_c_ph(i);
c_ph_val_orig(i) <= i_c_ph(i);
c_high_val_hold(i) <= i_c_high(i);
c_low_val_hold(i) <= i_c_low(i);
c_mode_val_hold(i) <= i_c_mode(i);
end loop;
lfc_val <= loop_filter_c;
lfr_val <= loop_filter_r;
cp_curr_val <= charge_pump_current;
if (pll_type = "fast") then
scan_chain_length := FAST_SCAN_CHAIN;
end if;
-- initialize the scan_chain contents
-- CP/LF bits
scan_data(11 downto 0) <= "000000000000";
for i in 0 to 3 loop
if (pll_type = "fast" or pll_type = "lvds") then
if (fpll_loop_filter_c_arr(i) = loop_filter_c) then
scan_data(11 downto 10) <= int2bin(i, 2);
end if;
else
if (loop_filter_c_arr(i) = loop_filter_c) then
scan_data(11 downto 10) <= int2bin(i, 2);
end if;
end if;
end loop;
for i in 0 to 15 loop
if (charge_pump_curr_arr(i) = charge_pump_current) then
scan_data(3 downto 0) <= int2bin(i, 4);
end if;
end loop;
for i in 0 to 39 loop
if (loop_filter_r_arr(i) = loop_filter_r) then
if (i >= 16 and i <= 23) then
scan_data(9 downto 4) <= int2bin((i+8), 6);
elsif (i >= 24 and i <= 31) then
scan_data(9 downto 4) <= int2bin((i+16), 6);
elsif (i >= 32) then
scan_data(9 downto 4) <= int2bin((i+24), 6);
else
scan_data(9 downto 4) <= int2bin(i, 6);
end if;
end if;
end loop;
if (pll_type = "fast" or pll_type = "lvds") then
scan_data(21 downto 12) <= "0000000000"; -- M, C3-C0 ph
-- C0-C3 high
scan_data(25 downto 22) <= int2bin(i_c_high(0), 4);
scan_data(35 downto 32) <= int2bin(i_c_high(1), 4);
scan_data(45 downto 42) <= int2bin(i_c_high(2), 4);
scan_data(55 downto 52) <= int2bin(i_c_high(3), 4);
-- C0-C3 low
scan_data(30 downto 27) <= int2bin(i_c_low(0), 4);
scan_data(40 downto 37) <= int2bin(i_c_low(1), 4);
scan_data(50 downto 47) <= int2bin(i_c_low(2), 4);
scan_data(60 downto 57) <= int2bin(i_c_low(3), 4);
-- C0-C3 mode
for i in 0 to 3 loop
if (i_c_mode(i) = " off" or i_c_mode(i) = "bypass") then
scan_data(26 + (10*i)) <= '1';
if (i_c_mode(i) = " off") then
scan_data(31 + (10*i)) <= '1';
else
scan_data(31 + (10*i)) <= '0';
end if;
else
scan_data(26 + (10*i)) <= '0';
if (i_c_mode(i) = " odd") then
scan_data(31 + (10*i)) <= '1';
else
scan_data(31 + (10*i)) <= '0';
end if;
end if;
end loop;
-- M
if (i_m = 1) then
scan_data(66) <= '1';
scan_data(71) <= '0';
scan_data(65 downto 62) <= "0000";
scan_data(70 downto 67) <= "0000";
else
scan_data(66) <= '0'; -- set BYPASS bit to 0
scan_data(70 downto 67) <= int2bin(i_m/2, 4); -- set M low
if (i_m rem 2 = 0) then
-- M is an even no. : set M high = low,
-- set odd/even bit to 0
scan_data(65 downto 62) <= int2bin(i_m/2, 4);
scan_data(71) <= '0';
else -- M is odd : M high = low + 1
scan_data(65 downto 62) <= int2bin((i_m/2) + 1, 4);
scan_data(71) <= '1';
end if;
end if;
-- N
scan_data(73 downto 72) <= int2bin(i_n, 2);
if (i_n = 1) then
scan_data(74) <= '1';
scan_data(73 downto 72) <= "00";
end if;
else -- PLL type is auto or enhanced
scan_data(25 downto 12) <= "00000000000000"; -- M, C5-C0 ph
-- C0-C5 high
scan_data(123 downto 116) <= int2bin(i_c_high(0), 8);
scan_data(105 downto 98) <= int2bin(i_c_high(1), 8);
scan_data(87 downto 80) <= int2bin(i_c_high(2), 8);
scan_data(69 downto 62) <= int2bin(i_c_high(3), 8);
scan_data(51 downto 44) <= int2bin(i_c_high(4), 8);
scan_data(33 downto 26) <= int2bin(i_c_high(5), 8);
-- C0-C5 low
scan_data(132 downto 125) <= int2bin(i_c_low(0), 8);
scan_data(114 downto 107) <= int2bin(i_c_low(1), 8);
scan_data(96 downto 89) <= int2bin(i_c_low(2), 8);
scan_data(78 downto 71) <= int2bin(i_c_low(3), 8);
scan_data(60 downto 53) <= int2bin(i_c_low(4), 8);
scan_data(42 downto 35) <= int2bin(i_c_low(5), 8);
-- C0-C5 mode
for i in 0 to 5 loop
if (i_c_mode(i) = " off" or i_c_mode(i) = "bypass") then
scan_data(124 - (18*i)) <= '1';
if (i_c_mode(i) = " off") then
scan_data(133 - (18*i)) <= '1';
else
scan_data(133 - (18*i)) <= '0';
end if;
else
scan_data(124 - (18*i)) <= '0';
if (i_c_mode(i) = " odd") then
scan_data(133 - (18*i)) <= '1';
else
scan_data(133 - (18*i)) <= '0';
end if;
end if;
end loop;
-- M/M2
scan_data(142 downto 134) <= int2bin(i_m, 9);
scan_data(143) <= '0';
scan_data(152 downto 144) <= int2bin(m2, 9);
scan_data(153) <= '0';
if (i_m = 1) then
scan_data(143) <= '1';
scan_data(142 downto 134) <= "000000000";
end if;
if (m2 = 1) then
scan_data(153) <= '1';
scan_data(152 downto 144) <= "000000000";
end if;
-- N/N2
scan_data(162 downto 154) <= int2bin(i_n, 9);
scan_data(172 downto 164) <= int2bin(n2, 9);
if (i_n = 1) then
scan_data(163) <= '1';
scan_data(162 downto 154) <= "000000000";
end if;
if (n2 = 1) then
scan_data(173) <= '1';
scan_data(172 downto 164) <= "000000000";
end if;
end if;
if (pll_type = "fast" or pll_type = "lvds") then
num_output_cntrs <= 4;
else
num_output_cntrs <= 6;
end if;
init := false;
elsif (scanwrite_enabled'event and scanwrite_enabled = '0') then
-- falling edge : deassert scandone
scandone_tmp <= transport '0' after (1.5 * scanclk_period);
c0_rising_edge_transfer_done := false;
c1_rising_edge_transfer_done := false;
c2_rising_edge_transfer_done := false;
c3_rising_edge_transfer_done := false;
c4_rising_edge_transfer_done := false;
c5_rising_edge_transfer_done := false;
elsif (scanwrite_enabled'event and scanwrite_enabled = '1') then
ASSERT false REPORT "PLL Reprogramming Initiated" severity note;
reconfig_err <= false;
-- make temporary copy of scan_data for processing
tmp_scan_data := scan_data;
-- save old values
lfc_old <= lfc_val;
lfr_old <= lfr_val;
cp_curr_old <= cp_curr_val;
-- CP
-- Bits 0-3 : all values are legal
cp_curr_val <= charge_pump_curr_arr(alt_conv_integer(scan_data(3 downto 0)));
-- LF Resistance : bits 4-9
-- values from 010000 - 010111, 100000 - 100111,
-- 110000 - 110111 are illegal
lfr_tmp := tmp_scan_data(9 downto 4);
lfr_int := alt_conv_integer(lfr_tmp);
if (((lfr_int >= 16) and (lfr_int <= 23)) or
((lfr_int >= 32) and (lfr_int <= 39)) or
((lfr_int >= 48) and (lfr_int <= 55))) then
reconfig_err <= true;
ASSERT false REPORT "Illegal bit settings for Loop Filter Resistance. Legal bit values range from 000000-001111, 011000-011111, 101000-101111 and 111000-111111. Reconfiguration may not work." severity warning;
else
if (lfr_int >= 56) then
lfr_int := lfr_int - 24;
elsif ((lfr_int >= 40) and (lfr_int <= 47)) then
lfr_int := lfr_int - 16;
elsif ((lfr_int >= 24) and (lfr_int <= 31)) then
lfr_int := lfr_int - 8;
end if;
lfr_val <= loop_filter_r_arr(lfr_int);
end if;
-- LF Capacitance : bits 10,11 : all values are legal
lfc_tmp := scan_data(11 downto 10);
if (pll_type = "fast" or pll_type = "lvds") then
lfc_val <= fpll_loop_filter_c_arr(alt_conv_integer(lfc_tmp));
else
lfc_val <= loop_filter_c_arr(alt_conv_integer(lfc_tmp));
end if;
-- cntrs c0-c5
-- save old values for display info.
m_val_old <= m_val;
n_val_old <= n_val;
m_mode_val_old <= m_mode_val;
n_mode_val_old <= n_mode_val;
m_ph_val_old <= m_ph_val;
c_high_val_old <= c_high_val;
c_low_val_old <= c_low_val;
c_ph_val_old <= c_ph_val;
c_mode_val_old <= c_mode_val;
-- first the M counter phase : bit order same for fast and GPP
if (scan_data(12) = '0') then
-- do nothing
elsif (scan_data(12) = '1' and scan_data(13) = '1') then
m_ph_val_tmp := m_ph_val_tmp + 1;
if (m_ph_val_tmp > 7) then
m_ph_val_tmp := 0;
end if;
elsif (scan_data(12) = '1' and scan_data(13) = '0') then
m_ph_val_tmp := m_ph_val_tmp - 1;
if (m_ph_val_tmp < 0) then
m_ph_val_tmp := 7;
end if;
else
reconfig_err <= true;
ASSERT false REPORT "Illegal values for M counter phase tap. Reconfiguration may not work." severity warning;
end if;
-- read the fast PLL bits
if (pll_type = "fast" or pll_type = "lvds") then
-- C3-C0 phase bits
for i in 3 downto 0 loop
start_bit := 14 + ((3-i)*2);
if (tmp_scan_data(start_bit) = '0') then
-- do nothing
elsif (tmp_scan_data(start_bit) = '1') then
if (tmp_scan_data(start_bit + 1) = '1') then
c_ph_val_tmp(i) := c_ph_val_tmp(i) + 1;
if (c_ph_val_tmp(i) > 7) then
c_ph_val_tmp(i) := 0;
end if;
elsif (tmp_scan_data(start_bit + 1) = '0') then
c_ph_val_tmp(i) := c_ph_val_tmp(i) - 1;
if (c_ph_val_tmp(i) < 0) then
c_ph_val_tmp(i) := 7;
end if;
end if;
end if;
end loop;
-- C0-C3 counter moduli
for i in 0 to 3 loop
start_bit := 22 + (i*10);
if (tmp_scan_data(start_bit + 4) = '1') then
c_mode_val_tmp(i) := "bypass";
if (tmp_scan_data(start_bit + 9) = '1') then
c_mode_val_tmp(i) := " off";
ASSERT false REPORT "The specified bit settings will turn OFF the " &cntrs(i)& "counter. It cannot be turned on unless the part is re-initialized." severity warning;
end if;
elsif (tmp_scan_data(start_bit + 9) = '1') then
c_mode_val_tmp(i) := " odd";
else
c_mode_val_tmp(i) := " even";
end if;
high_fast := tmp_scan_data(start_bit+3 downto start_bit);
low_fast := tmp_scan_data(start_bit+8 downto start_bit+5);
if (tmp_scan_data(start_bit+3 downto start_bit) = "0000") then
c_high_val_tmp(i) := 16;
else
c_high_val_tmp(i) := alt_conv_integer(high_fast);
end if;
if (tmp_scan_data(start_bit+8 downto start_bit+5) = "0000") then
c_low_val_tmp(i) := 16;
else
c_low_val_tmp(i) := alt_conv_integer(low_fast);
end if;
end loop;
sig_c_ph_val_tmp <= c_ph_val_tmp;
sig_c_low_val_tmp <= c_low_val_tmp;
-- M
-- some temporary storage
if (tmp_scan_data(65 downto 62) = "0000") then
m_hi := "10000";
else
m_hi := "0" & tmp_scan_data(65 downto 62);
end if;
if (tmp_scan_data(70 downto 67) = "0000") then
m_lo := "10000";
else
m_lo := "0" & tmp_scan_data(70 downto 67);
end if;
m_val_tmp(0) := alt_conv_integer(m_hi) + alt_conv_integer(m_lo);
if (tmp_scan_data(66) = '1') then
if (tmp_scan_data(71) = '1') then
-- this will turn off the M counter : error
reconfig_err <= true;
is_error := true;
ASSERT false REPORT "The specified bit settings will turn OFF the M counter. This is illegal. Reconfiguration may not work." severity warning;
else -- M counter is being bypassed
if (m_mode_val(0) /= "bypass") then
-- mode is switched : give warning
ASSERT false REPORT "M counter switched from enabled to BYPASS mode. PLL may lose lock." severity warning;
end if;
m_val_tmp(0) := 1;
m_mode_val(0) <= "bypass";
end if;
else
if (m_mode_val(0) = "bypass") then
-- mode is switched : give warning
ASSERT false REPORT "M counter switched BYPASS mode to enabled. PLL may lose lock." severity warning;
end if;
m_mode_val(0) <= " ";
if (tmp_scan_data(71) = '1') then
-- odd : check for duty cycle, if not 50% -- error
if (alt_conv_integer(m_hi) - alt_conv_integer(m_lo) /= 1) then
reconfig_err <= true;
ASSERT FALSE REPORT "The M counter of the StratixII FAST PLL can be configured for 50% duty cycle only. In this case, the HIGH and LOW moduli programmed will result in a duty cycle other than 50%, which is illegal. Reconfiguration may not work." severity warning;
end if;
else -- even
if (alt_conv_integer(m_hi) /= alt_conv_integer(m_lo)) then
reconfig_err <= true;
ASSERT FALSE REPORT "The M counter of the StratixII FAST PLL can be configured for 50% duty cycle only. In this case, the HIGH and LOW moduli programmed will result in a duty cycle other than 50%, which is illegal. Reconfiguration may not work." severity warning;
end if;
end if;
end if;
-- N
is_error := false;
n_fast := tmp_scan_data(73 downto 72);
n_val(0) <= alt_conv_integer(n_fast);
if (tmp_scan_data(74) /= '1') then
if (alt_conv_integer(n_fast) = 1) then
is_error := true;
reconfig_err <= true;
-- cntr value is illegal : give warning
ASSERT false REPORT "Illegal 1 value for N counter. Instead the counter should be BYPASSED. Reconfiguration may not work." severity warning;
elsif (alt_conv_integer(n_fast) = 0) then
n_val(0) <= 4;
ASSERT FALSE REPORT "N Modulus = " &int2str(4)& " " severity note;
end if;
if (not is_error) then
if (n_mode_val(0) = "bypass") then
ASSERT false REPORT "N Counter switched from BYPASS mode to enabled (N modulus = " &int2str(alt_conv_integer(n_fast))& "). PLL may lose lock." severity warning;
else
ASSERT FALSE REPORT "N modulus = " &int2str(alt_conv_integer(n_fast))& " "severity note;
end if;
n_mode_val(0) <= " ";
end if;
elsif (tmp_scan_data(74) = '1') then
if (tmp_scan_data(72) /= '0') then
is_error := true;
reconfig_err <= true;
ASSERT false report "Illegal value for N counter in BYPASS mode. The LSB of the counter should be set to 0 in order to operate the counter in BYPASS mode. Reconfiguration may not work." severity warning;
else
if (n_mode_val(0) /= "bypass") then
ASSERT false REPORT "N Counter switched from enabled to BYPASS mode. PLL may lose lock." severity warning;
end if;
n_val(0) <= 1;
n_mode_val(0) <= "bypass";
end if;
end if;
else -- GENERAL PURPOSE PLL
for i in 0 to 5 loop
start_bit := 116 - (i*18);
if (tmp_scan_data(start_bit + 8) = '1') then
c_mode_val_tmp(i) := "bypass";
if (tmp_scan_data(start_bit + 17) = '1') then
c_mode_val_tmp(i) := " off";
ASSERT false REPORT "The specified bit settings will turn OFF the " &cntrs(i)& "counter. It cannot be turned on unless the part is re-initialized." severity warning;
end if;
elsif (tmp_scan_data(start_bit + 17) = '1') then
c_mode_val_tmp(i) := " odd";
else
c_mode_val_tmp(i) := " even";
end if;
high := tmp_scan_data(start_bit + 7 downto start_bit);
low := tmp_scan_data(start_bit+16 downto start_bit+9);
if (tmp_scan_data(start_bit+7 downto start_bit) = "00000000") then
c_high_val_tmp(i) := 256;
else
c_high_val_tmp(i) := alt_conv_integer(high);
end if;
if (tmp_scan_data(start_bit+16 downto start_bit+9) = "00000000") then
c_low_val_tmp(i) := 256;
else
c_low_val_tmp(i) := alt_conv_integer(low);
end if;
end loop;
-- the phase taps
for i in 0 to 5 loop
start_bit := 14 + (i*2);
if (tmp_scan_data(start_bit) = '0') then
-- do nothing
elsif (tmp_scan_data(start_bit) = '1') then
if (tmp_scan_data(start_bit + 1) = '1') then
c_ph_val_tmp(i) := c_ph_val_tmp(i) + 1;
if (c_ph_val_tmp(i) > 7) then
c_ph_val_tmp(i) := 0;
end if;
elsif (tmp_scan_data(start_bit + 1) = '0') then
c_ph_val_tmp(i) := c_ph_val_tmp(i) - 1;
if (c_ph_val_tmp(i) < 0) then
c_ph_val_tmp(i) := 7;
end if;
end if;
end if;
end loop;
sig_c_ph_val_tmp <= c_ph_val_tmp;
sig_c_low_val_tmp <= c_low_val_tmp;
-- cntrs M/M2
for i in 0 to 1 loop
start_bit := 134 + (i*10);
if ( i = 0 or (i = 1 and ss > 0) ) then
is_error := false;
m_tmp := tmp_scan_data(start_bit+8 downto start_bit);
m_val_tmp(i) := alt_conv_integer(m_tmp);
if (tmp_scan_data(start_bit+9) /= '1') then
if (alt_conv_integer(m_tmp) = 1) then
is_error := true;
reconfig_err <= true;
-- cntr value is illegal : give warning
ASSERT false REPORT "Illegal 1 value for " &ss_cntrs(i)& "counter. Instead " &ss_cntrs(i)& "should be BYPASSED. Reconfiguration may not work." severity warning;
elsif (tmp_scan_data(start_bit+8 downto start_bit) = "000000000") then
m_val_tmp(i) := 512;
end if;
if (not is_error) then
if (m_mode_val(i) = "bypass") then
-- Mode is switched : give warning
ASSERT false REPORT "M Counter switched from BYPASS mode to enabled (M modulus = " &int2str(alt_conv_integer(m_tmp))& "). PLL may lose lock." severity warning;
else
end if;
m_mode_val(i) <= " ";
end if;
elsif (tmp_scan_data(start_bit+9) = '1') then
if (tmp_scan_data(start_bit) /= '0') then
is_error := true;
reconfig_err <= true;
ASSERT false report "Illegal value for counter " &ss_cntrs(i)& "in BYPASS mode. The LSB of the counter should be set to 0 in order to operate the counter in BYPASS mode. Reconfiguration may not work." severity warning;
else
if (m_mode_val(i) /= "bypass") then
-- Mode is switched : give warning
ASSERT false REPORT "M Counter switched from enabled to BYPASS mode. PLL may lose lock." severity warning;
end if;
m_val_tmp(i) := 1;
m_mode_val(i) <= "bypass";
end if;
end if;
end if;
end loop;
if (ss > 0) then
if (m_mode_val(0) /= m_mode_val(1)) then
reconfig_err <= true;
is_error := true;
ASSERT false REPORT "Incompatible modes for M/M2 counters. Either both should be BYPASSED or both NON-BYPASSED. Reconfiguration may not work." severity warning;
end if;
end if;
-- cntrs N/N2
for i in 0 to 1 loop
start_bit := 154 + i*10;
if ( i = 0 or (i = 1 and ss > 0) ) then
is_error := false;
n_tmp := tmp_scan_data(start_bit+8 downto start_bit);
n_val(i) <= alt_conv_integer(n_tmp);
if (tmp_scan_data(start_bit+9) /= '1') then
if (alt_conv_integer(n_tmp) = 1) then
is_error := true;
reconfig_err <= true;
-- cntr value is illegal : give warning
ASSERT false REPORT "Illegal 1 value for " &ss_cntrs(2+i)& "counter. Instead " &ss_cntrs(2+i)& "should be BYPASSED. Reconfiguration may not work." severity warning;
elsif (alt_conv_integer(n_tmp) = 0) then
n_val(i) <= 512;
end if;
if (not is_error) then
if (n_mode_val(i) = "bypass") then
ASSERT false REPORT "N Counter switched from BYPASS mode to enabled (N modulus = " &int2str(alt_conv_integer(n_tmp))& "). PLL may lose lock." severity warning;
else
end if;
n_mode_val(i) <= " ";
end if;
elsif (tmp_scan_data(start_bit+9) = '1') then
if (tmp_scan_data(start_bit) /= '0') then
is_error := true;
reconfig_err <= true;
ASSERT false report "Illegal value for counter " &ss_cntrs(2+i)& "in BYPASS mode. The LSB of the counter should be set to 0 in order to operate the counter in BYPASS mode. Reconfiguration may not work." severity warning;
else
if (n_mode_val(i) /= "bypass") then
ASSERT false REPORT "N Counter switched from enabled to BYPASS mode. PLL may lose lock." severity warning;
end if;
n_val(i) <= 1;
n_mode_val(i) <= "bypass";
end if;
end if;
end if;
end loop;
if (ss > 0) then
if (n_mode_val(0) /= n_mode_val(1)) then
reconfig_err <= true;
is_error := true;
ASSERT false REPORT "Incompatible modes for N/N2 counters. Either both should be BYPASSED or both NON-BYPASSED. Reconfiguration may not work." severity warning;
end if;
end if;
end if;
slowest_clk_old := slowest_clk(c_high_val(0)+c_low_val(0), c_mode_val(0),
c_high_val(1)+c_low_val(1), c_mode_val(1),
c_high_val(2)+c_low_val(2), c_mode_val(2),
c_high_val(3)+c_low_val(3), c_mode_val(3),
c_high_val(4)+c_low_val(4), c_mode_val(4),
c_high_val(5)+c_low_val(5), c_mode_val(5),
sig_refclk_period, m_val(0));
slowest_clk_new := slowest_clk(c_high_val(0)+c_low_val(0), c_mode_val(0),
c_high_val_tmp(1)+c_low_val(1), c_mode_val_tmp(1),
c_high_val_tmp(2)+c_low_val(2), c_mode_val_tmp(2),
c_high_val_tmp(3)+c_low_val(3), c_mode_val_tmp(3),
c_high_val_tmp(4)+c_low_val(4), c_mode_val_tmp(4),
c_high_val_tmp(5)+c_low_val(5), c_mode_val_tmp(5),
sig_refclk_period, m_val(0));
if (slowest_clk_new > slowest_clk_old) then
quiet_time := slowest_clk_new;
else
quiet_time := slowest_clk_old;
end if;
tmp_rem := (quiet_time/1 ps) rem (scanclk_period/ 1 ps);
scanclk_cycles := (quiet_time/1 ps) / (scanclk_period/1 ps);
if (tmp_rem /= 0) then
scanclk_cycles := scanclk_cycles + 1;
end if;
scandone_tmp <= transport '1' after ((scanclk_cycles+1)*scanclk_period - (scanclk_period/2));
end if;
if (scanwrite_enabled = '1') then
if (fbclk'event and fbclk = '1') then
m_val <= m_val_tmp;
end if;
if (c_clk(0)'event and c_clk(0) = '1') then
c_high_val_hold(0) <= c_high_val_tmp(0);
c_mode_val_hold(0) <= c_mode_val_tmp(0);
c0_rising_edge_transfer_done := true;
c_high_val(0) <= c_high_val_hold(0);
c_mode_val(0) <= c_mode_val_hold(0);
end if;
if (c_clk(1)'event and c_clk(1) = '1') then
c_high_val_hold(1) <= c_high_val_tmp(1);
c_mode_val_hold(1) <= c_mode_val_tmp(1);
c1_rising_edge_transfer_done := true;
c_high_val(1) <= c_high_val_hold(1);
c_mode_val(1) <= c_mode_val_hold(1);
end if;
if (c_clk(2)'event and c_clk(2) = '1') then
c_high_val_hold(2) <= c_high_val_tmp(2);
c_mode_val_hold(2) <= c_mode_val_tmp(2);
c2_rising_edge_transfer_done := true;
c_high_val(2) <= c_high_val_hold(2);
c_mode_val(2) <= c_mode_val_hold(2);
end if;
if (c_clk(3)'event and c_clk(3) = '1') then
c_high_val_hold(3) <= c_high_val_tmp(3);
c_mode_val_hold(3) <= c_mode_val_tmp(3);
c_high_val(3) <= c_high_val_hold(3);
c_mode_val(3) <= c_mode_val_hold(3);
c3_rising_edge_transfer_done := true;
end if;
if (c_clk(4)'event and c_clk(4) = '1') then
c_high_val_hold(4) <= c_high_val_tmp(4);
c_mode_val_hold(4) <= c_mode_val_tmp(4);
c_high_val(4) <= c_high_val_hold(4);
c_mode_val(4) <= c_mode_val_hold(4);
c4_rising_edge_transfer_done := true;
end if;
if (c_clk(5)'event and c_clk(5) = '1') then
c_high_val_hold(5) <= c_high_val_tmp(5);
c_mode_val_hold(5) <= c_mode_val_tmp(5);
c_high_val(5) <= c_high_val_hold(5);
c_mode_val(5) <= c_mode_val_hold(5);
c5_rising_edge_transfer_done := true;
end if;
end if;
if (c_clk(0)'event and c_clk(0) = '0' and c0_rising_edge_transfer_done) then
c_low_val_hold(0) <= c_low_val_tmp(0);
c_low_val(0) <= c_low_val_hold(0);
end if;
if (c_clk(1)'event and c_clk(1) = '0' and c1_rising_edge_transfer_done) then
c_low_val_hold(1) <= c_low_val_tmp(1);
c_low_val(1) <= c_low_val_hold(1);
end if;
if (c_clk(2)'event and c_clk(2) = '0' and c2_rising_edge_transfer_done) then
c_low_val_hold(2) <= c_low_val_tmp(2);
c_low_val(2) <= c_low_val_hold(2);
end if;
if (c_clk(3)'event and c_clk(3) = '0' and c3_rising_edge_transfer_done) then
c_low_val_hold(3) <= c_low_val_tmp(3);
c_low_val(3) <= c_low_val_hold(3);
end if;
if (c_clk(4)'event and c_clk(4) = '0' and c4_rising_edge_transfer_done) then
c_low_val_hold(4) <= c_low_val_tmp(4);
c_low_val(4) <= c_low_val_hold(4);
end if;
if (c_clk(5)'event and c_clk(5) = '0' and c5_rising_edge_transfer_done) then
c_low_val_hold(5) <= c_low_val_tmp(5);
c_low_val(5) <= c_low_val_hold(5);
end if;
if (scanwrite_enabled = '1') then
if (vco_out(0)'event and vco_out(0) = '0') then
for i in 0 to 5 loop
if (c_ph_val(i) = 0) then
c_ph_val(i) <= c_ph_val_tmp(i);
end if;
end loop;
if (m_ph_val = 0) then
m_ph_val <= m_ph_val_tmp;
end if;
end if;
if (vco_out(1)'event and vco_out(1) = '0') then
for i in 0 to 5 loop
if (c_ph_val(i) = 1) then
c_ph_val(i) <= c_ph_val_tmp(i);
end if;
end loop;
if (m_ph_val = 1) then
m_ph_val <= m_ph_val_tmp;
end if;
end if;
if (vco_out(2)'event and vco_out(2) = '0') then
for i in 0 to 5 loop
if (c_ph_val(i) = 2) then
c_ph_val(i) <= c_ph_val_tmp(i);
end if;
end loop;
if (m_ph_val = 2) then
m_ph_val <= m_ph_val_tmp;
end if;
end if;
if (vco_out(3)'event and vco_out(3) = '0') then
for i in 0 to 5 loop
if (c_ph_val(i) = 3) then
c_ph_val(i) <= c_ph_val_tmp(i);
end if;
end loop;
if (m_ph_val = 3) then
m_ph_val <= m_ph_val_tmp;
end if;
end if;
if (vco_out(4)'event and vco_out(4) = '0') then
for i in 0 to 5 loop
if (c_ph_val(i) = 4) then
c_ph_val(i) <= c_ph_val_tmp(i);
end if;
end loop;
if (m_ph_val = 4) then
m_ph_val <= m_ph_val_tmp;
end if;
end if;
if (vco_out(5)'event and vco_out(5) = '0') then
for i in 0 to 5 loop
if (c_ph_val(i) = 5) then
c_ph_val(i) <= c_ph_val_tmp(i);
end if;
end loop;
if (m_ph_val = 5) then
m_ph_val <= m_ph_val_tmp;
end if;
end if;
if (vco_out(6)'event and vco_out(6) = '0') then
for i in 0 to 5 loop
if (c_ph_val(i) = 6) then
c_ph_val(i) <= c_ph_val_tmp(i);
end if;
end loop;
if (m_ph_val = 6) then
m_ph_val <= m_ph_val_tmp;
end if;
end if;
if (vco_out(7)'event and vco_out(7) = '0') then
for i in 0 to 5 loop
if (c_ph_val(i) = 7) then
c_ph_val(i) <= c_ph_val_tmp(i);
end if;
end loop;
if (m_ph_val = 7) then
m_ph_val <= m_ph_val_tmp;
end if;
end if;
end if;
-- revert counter phase tap values to POF programmed values
-- if PLL is reset
if (areset_ipd = '1') then
c_ph_val <= i_c_ph;
c_ph_val_tmp := i_c_ph;
m_ph_val <= i_m_ph;
m_ph_val_tmp := i_m_ph;
end if;
if (vco_out(0)'event) then
for i in 0 to 5 loop
if (c_ph_val(i) = 0) then
inclk_c_from_vco(i) <= vco_out(0);
if (i = 0 and enable0_counter = "c0") then
inclk_sclkout0_from_vco <= vco_out(0);
end if;
if (i = 0 and enable1_counter = "c0") then
inclk_sclkout1_from_vco <= vco_out(0);
end if;
if (i = 1 and enable0_counter = "c1") then
inclk_sclkout0_from_vco <= vco_out(0);
end if;
if (i = 1 and enable1_counter = "c1") then
inclk_sclkout1_from_vco <= vco_out(0);
end if;
end if;
end loop;
if (m_ph_val = 0) then
inclk_m_from_vco <= vco_out(0);
end if;
end if;
if (vco_out(1)'event) then
for i in 0 to 5 loop
if (c_ph_val(i) = 1) then
inclk_c_from_vco(i) <= vco_out(1);
if (i = 0 and enable0_counter = "c0") then
inclk_sclkout0_from_vco <= vco_out(1);
end if;
if (i = 0 and enable1_counter = "c0") then
inclk_sclkout1_from_vco <= vco_out(1);
end if;
if (i = 1 and enable0_counter = "c1") then
inclk_sclkout0_from_vco <= vco_out(1);
end if;
if (i = 1 and enable1_counter = "c1") then
inclk_sclkout1_from_vco <= vco_out(1);
end if;
end if;
end loop;
if (m_ph_val = 1) then
inclk_m_from_vco <= vco_out(1);
end if;
end if;
if (vco_out(2)'event) then
for i in 0 to 5 loop
if (c_ph_val(i) = 2) then
inclk_c_from_vco(i) <= vco_out(2);
if (i = 0 and enable0_counter = "c0") then
inclk_sclkout0_from_vco <= vco_out(2);
end if;
if (i = 0 and enable1_counter = "c0") then
inclk_sclkout1_from_vco <= vco_out(2);
end if;
if (i = 1 and enable0_counter = "c1") then
inclk_sclkout0_from_vco <= vco_out(2);
end if;
if (i = 1 and enable1_counter = "c1") then
inclk_sclkout1_from_vco <= vco_out(2);
end if;
end if;
end loop;
if (m_ph_val = 2) then
inclk_m_from_vco <= vco_out(2);
end if;
end if;
if (vco_out(3)'event) then
for i in 0 to 5 loop
if (c_ph_val(i) = 3) then
inclk_c_from_vco(i) <= vco_out(3);
if (i = 0 and enable0_counter = "c0") then
inclk_sclkout0_from_vco <= vco_out(3);
end if;
if (i = 0 and enable1_counter = "c0") then
inclk_sclkout1_from_vco <= vco_out(3);
end if;
if (i = 1 and enable0_counter = "c1") then
inclk_sclkout0_from_vco <= vco_out(3);
end if;
if (i = 1 and enable1_counter = "c1") then
inclk_sclkout1_from_vco <= vco_out(3);
end if;
end if;
end loop;
if (m_ph_val = 3) then
inclk_m_from_vco <= vco_out(3);
end if;
end if;
if (vco_out(4)'event) then
for i in 0 to 5 loop
if (c_ph_val(i) = 4) then
inclk_c_from_vco(i) <= vco_out(4);
if (i = 0 and enable0_counter = "c0") then
inclk_sclkout0_from_vco <= vco_out(4);
end if;
if (i = 0 and enable1_counter = "c0") then
inclk_sclkout1_from_vco <= vco_out(4);
end if;
if (i = 1 and enable0_counter = "c1") then
inclk_sclkout0_from_vco <= vco_out(4);
end if;
if (i = 1 and enable1_counter = "c1") then
inclk_sclkout1_from_vco <= vco_out(4);
end if;
end if;
end loop;
if (m_ph_val = 4) then
inclk_m_from_vco <= vco_out(4);
end if;
end if;
if (vco_out(5)'event) then
for i in 0 to 5 loop
if (c_ph_val(i) = 5) then
inclk_c_from_vco(i) <= vco_out(5);
if (i = 0 and enable0_counter = "c0") then
inclk_sclkout0_from_vco <= vco_out(5);
end if;
if (i = 0 and enable1_counter = "c0") then
inclk_sclkout1_from_vco <= vco_out(5);
end if;
if (i = 1 and enable0_counter = "c1") then
inclk_sclkout0_from_vco <= vco_out(5);
end if;
if (i = 1 and enable1_counter = "c1") then
inclk_sclkout1_from_vco <= vco_out(5);
end if;
end if;
end loop;
if (m_ph_val = 5) then
inclk_m_from_vco <= vco_out(5);
end if;
end if;
if (vco_out(6)'event) then
for i in 0 to 5 loop
if (c_ph_val(i) = 6) then
inclk_c_from_vco(i) <= vco_out(6);
if (i = 0 and enable0_counter = "c0") then
inclk_sclkout0_from_vco <= vco_out(6);
end if;
if (i = 0 and enable1_counter = "c0") then
inclk_sclkout1_from_vco <= vco_out(6);
end if;
if (i = 1 and enable0_counter = "c1") then
inclk_sclkout0_from_vco <= vco_out(6);
end if;
if (i = 1 and enable1_counter = "c1") then
inclk_sclkout1_from_vco <= vco_out(6);
end if;
end if;
end loop;
if (m_ph_val = 6) then
inclk_m_from_vco <= vco_out(6);
end if;
end if;
if (vco_out(7)'event) then
for i in 0 to 5 loop
if (c_ph_val(i) = 7) then
inclk_c_from_vco(i) <= vco_out(7);
if (i = 0 and enable0_counter = "c0") then
inclk_sclkout0_from_vco <= vco_out(7);
end if;
if (i = 0 and enable1_counter = "c0") then
inclk_sclkout1_from_vco <= vco_out(7);
end if;
if (i = 1 and enable0_counter = "c1") then
inclk_sclkout0_from_vco <= vco_out(7);
end if;
if (i = 1 and enable1_counter = "c1") then
inclk_sclkout1_from_vco <= vco_out(7);
end if;
end if;
end loop;
if (m_ph_val = 7) then
inclk_m_from_vco <= vco_out(7);
end if;
end if;
------------------------
-- Timing Check Section
------------------------
if (TimingChecksOn) then
VitalSetupHoldCheck (
Violation => Tviol_scandata_scanclk,
TimingData => TimingData_scandata_scanclk,
TestSignal => scandata_ipd,
TestSignalName => "scandata",
RefSignal => scanclk_ipd,
RefSignalName => "scanclk",
SetupHigh => tsetup_scandata_scanclk_noedge_posedge,
SetupLow => tsetup_scandata_scanclk_noedge_posedge,
HoldHigh => thold_scandata_scanclk_noedge_posedge,
HoldLow => thold_scandata_scanclk_noedge_posedge,
-- CheckEnabled => TO_X01( (NOT ena_ipd) ) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/stratixii_pll",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_scanread_scanclk,
TimingData => TimingData_scanread_scanclk,
TestSignal => scanread_ipd,
TestSignalName => "scanread",
RefSignal => scanclk_ipd,
RefSignalName => "scanclk",
SetupHigh => tsetup_scanread_scanclk_noedge_posedge,
SetupLow => tsetup_scanread_scanclk_noedge_posedge,
HoldHigh => thold_scanread_scanclk_noedge_posedge,
HoldLow => thold_scanread_scanclk_noedge_posedge,
-- CheckEnabled => TO_X01( (NOT ena_ipd) ) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/stratixii_pll",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_scanwrite_scanclk,
TimingData => TimingData_scanwrite_scanclk,
TestSignal => scanwrite_ipd,
TestSignalName => "scanwrite",
RefSignal => scanclk_ipd,
RefSignalName => "scanclk",
SetupHigh => tsetup_scanwrite_scanclk_noedge_posedge,
SetupLow => tsetup_scanwrite_scanclk_noedge_posedge,
HoldHigh => thold_scanwrite_scanclk_noedge_posedge,
HoldLow => thold_scanwrite_scanclk_noedge_posedge,
-- CheckEnabled => TO_X01( (NOT ena_ipd) ) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/stratixii_pll",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
end if;
if (scanclk_ipd'event and scanclk_ipd = '0') then
-- enable scanwrite on falling edge
scanwrite_enabled <= scanwrite_reg;
end if;
if (scanread_reg = '1') then
gated_scanclk <= transport scanclk_ipd and scanread_reg;
else
gated_scanclk <= transport '1';
end if;
if (scanclk_ipd'event and scanclk_ipd = '1') then
-- register scanread and scanwrite
scanread_reg <= scanread_ipd;
scanwrite_reg <= scanwrite_ipd;
if (got_first_scanclk) then
scanclk_period := now - scanclk_last_rising_edge;
else
got_first_scanclk := true;
end if;
-- reset got_first_scanclk on falling edge of scanread_reg
if (scanread_ipd = '0' and scanread_reg = '1') then
got_first_scanclk := false;
got_first_gated_scanclk := false;
end if;
scanclk_last_rising_edge := now;
end if;
if (gated_scanclk'event and gated_scanclk = '1' and now > 0 ps) then
if (not got_first_gated_scanclk) then
got_first_gated_scanclk := true;
end if;
for j in scan_chain_length - 1 downto 1 loop
scan_data(j) <= scan_data(j-1);
end loop;
scan_data(0) <= scandata_ipd;
end if;
end process;
scandataout_tmp <= scan_data(FAST_SCAN_CHAIN-1) when (pll_type = "fast" or pll_type = "lvds") else scan_data(GPP_SCAN_CHAIN-1);
process (schedule_vco, areset_ipd, ena_ipd, pfdena_ipd, refclk, fbclk)
variable sched_time : time := 0 ps;
TYPE time_array is ARRAY (0 to 7) of time;
variable init : boolean := true;
variable refclk_period : time;
variable m_times_vco_period : time;
variable new_m_times_vco_period : time;
variable phase_shift : time_array := (OTHERS => 0 ps);
variable last_phase_shift : time_array := (OTHERS => 0 ps);
variable l_index : integer := 1;
variable cycle_to_adjust : integer := 0;
variable stop_vco : boolean := false;
variable locked_tmp : std_logic := '0';
variable pll_is_locked : boolean := false;
variable pll_about_to_lock : boolean := false;
variable cycles_to_lock : integer := 0;
variable cycles_to_unlock : integer := 0;
variable got_first_refclk : boolean := false;
variable got_second_refclk : boolean := false;
variable got_first_fbclk : boolean := false;
variable refclk_time : time := 0 ps;
variable fbclk_time : time := 0 ps;
variable first_fbclk_time : time := 0 ps;
variable fbclk_period : time := 0 ps;
variable first_schedule : boolean := true;
variable vco_val : std_logic := '0';
variable vco_period_was_phase_adjusted : boolean := false;
variable phase_adjust_was_scheduled : boolean := false;
variable loop_xplier : integer;
variable loop_initial : integer := 0;
variable loop_ph : integer := 0;
variable loop_time_delay : integer := 0;
variable initial_delay : time := 0 ps;
variable vco_per : time;
variable tmp_rem : integer;
variable my_rem : integer;
variable fbk_phase : integer := 0;
variable pull_back_M : integer := 0;
variable total_pull_back : integer := 0;
variable fbk_delay : integer := 0;
variable offset : time := 0 ps;
variable tmp_vco_per : integer := 0;
variable high_time : time;
variable low_time : time;
variable got_refclk_posedge : boolean := false;
variable got_fbclk_posedge : boolean := false;
variable inclk_out_of_range : boolean := false;
variable no_warn : boolean := false;
variable ext_fbk_cntr_modulus : integer := 1;
variable init_clks : boolean := true;
variable pll_is_in_reset : boolean := false;
begin
if (init) then
-- jump-start the VCO
-- add 1 ps delay to ensure all signals are updated to initial
-- values
schedule_vco <= transport not schedule_vco after 1 ps;
init := false;
end if;
if (schedule_vco'event) then
if (init_clks) then
refclk_period := inclk0_input_frequency * n_val(0) * 1 ps;
m_times_vco_period := refclk_period;
new_m_times_vco_period := refclk_period;
init_clks := false;
end if;
sched_time := 0 ps;
for i in 0 to 7 loop
last_phase_shift(i) := phase_shift(i);
end loop;
cycle_to_adjust := 0;
l_index := 1;
m_times_vco_period := new_m_times_vco_period;
end if;
-- areset was asserted
if (areset_ipd'event and areset_ipd = '1') then
assert false report "PLL was reset" severity note;
-- reset lock parameters
locked_tmp := '0';
pll_is_locked := false;
pll_about_to_lock := false;
cycles_to_lock := 0;
cycles_to_unlock := 0;
end if;
-- ena was deasserted
if (ena_ipd'event and ena_ipd = '0') then
assert false report "PLL was disabled" severity note;
end if;
if (schedule_vco'event and (areset_ipd = '1' or ena_ipd = '0' or stop_vco)) then
if (areset_ipd = '1') then
pll_is_in_reset := true;
end if;
-- drop VCO taps to 0
for i in 0 to 7 loop
vco_out(i) <= transport '0' after last_phase_shift(i);
phase_shift(i) := 0 ps;
last_phase_shift(i) := 0 ps;
end loop;
-- reset lock parameters
locked_tmp := '0';
pll_is_locked := false;
pll_about_to_lock := false;
cycles_to_lock := 0;
cycles_to_unlock := 0;
got_first_refclk := false;
got_second_refclk := false;
refclk_time := 0 ps;
got_first_fbclk := false;
fbclk_time := 0 ps;
first_fbclk_time := 0 ps;
fbclk_period := 0 ps;
first_schedule := true;
vco_val := '0';
vco_period_was_phase_adjusted := false;
phase_adjust_was_scheduled := false;
elsif ((schedule_vco'event or ena_ipd'event or areset_ipd'event) and areset_ipd = '0' and ena_ipd = '1' and (not stop_vco) and now > 0 ps) then
-- note areset deassert time
-- note it as refclk_time to prevent false triggering
-- of stop_vco after areset
if (areset_ipd'event and areset_ipd = '0' and pll_is_in_reset) then
refclk_time := now;
pll_is_in_reset := false;
end if;
-- calculate loop_xplier : this will be different from m_val
-- in external_feedback_mode
loop_xplier := m_val(0);
loop_initial := m_initial_val - 1;
loop_ph := m_ph_val;
if (operation_mode = "external_feedback") then
if (ext_fbk_cntr_mode = "bypass") then
ext_fbk_cntr_modulus := 1;
else
ext_fbk_cntr_modulus := ext_fbk_cntr_high + ext_fbk_cntr_low;
end if;
loop_xplier := m_val(0) * (ext_fbk_cntr_modulus);
loop_ph := ext_fbk_cntr_ph;
loop_initial := ext_fbk_cntr_initial - 1 + ((m_initial_val - 1) * ext_fbk_cntr_modulus);
end if;
-- convert initial value to delay
initial_delay := (loop_initial * m_times_vco_period)/loop_xplier;
-- convert loop ph_tap to delay
my_rem := (m_times_vco_period/1 ps) rem loop_xplier;
tmp_vco_per := (m_times_vco_period/1 ps) / loop_xplier;
if (my_rem /= 0) then
tmp_vco_per := tmp_vco_per + 1;
end if;
fbk_phase := (loop_ph * tmp_vco_per)/8;
if (operation_mode = "external_feedback") then
pull_back_M := (m_initial_val - 1) * ext_fbk_cntr_modulus * ((refclk_period/loop_xplier)/1 ps);
while (pull_back_M > refclk_period/1 ps) loop
pull_back_M := pull_back_M - refclk_period/ 1 ps;
end loop;
else
pull_back_M := initial_delay/1 ps + fbk_phase;
end if;
total_pull_back := pull_back_M;
if (simulation_type = "timing") then
total_pull_back := total_pull_back + pll_compensation_delay;
end if;
while (total_pull_back > refclk_period/1 ps) loop
total_pull_back := total_pull_back - refclk_period/1 ps;
end loop;
if (total_pull_back > 0) then
offset := refclk_period - (total_pull_back * 1 ps);
end if;
if (operation_mode = "external_feedback") then
fbk_delay := pull_back_M;
if (simulation_type = "timing") then
fbk_delay := fbk_delay + pll_compensation_delay;
end if;
else
fbk_delay := total_pull_back - fbk_phase;
if (fbk_delay < 0) then
offset := offset - (fbk_phase * 1 ps);
fbk_delay := total_pull_back;
end if;
end if;
-- assign m_delay
m_delay <= transport fbk_delay after 1 ps;
my_rem := (m_times_vco_period/1 ps) rem loop_xplier;
for i in 1 to loop_xplier loop
-- adjust cycles
tmp_vco_per := (m_times_vco_period/1 ps)/loop_xplier;
if (my_rem /= 0 and l_index <= my_rem) then
tmp_rem := (loop_xplier * l_index) rem my_rem;
cycle_to_adjust := (loop_xplier * l_index) / my_rem;
if (tmp_rem /= 0) then
cycle_to_adjust := cycle_to_adjust + 1;
end if;
end if;
if (cycle_to_adjust = i) then
tmp_vco_per := tmp_vco_per + 1;
l_index := l_index + 1;
end if;
-- calculate high and low periods
vco_per := tmp_vco_per * 1 ps;
high_time := (tmp_vco_per/2) * 1 ps;
if (tmp_vco_per rem 2 /= 0) then
high_time := high_time + 1 ps;
end if;
low_time := vco_per - high_time;
-- schedule the rising and falling edges
for j in 1 to 2 loop
vco_val := not vco_val;
if (vco_val = '0') then
sched_time := sched_time + high_time;
elsif (vco_val = '1') then
sched_time := sched_time + low_time;
end if;
-- schedule the phase taps
for k in 0 to 7 loop
phase_shift(k) := (k * vco_per)/8;
if (first_schedule) then
vco_out(k) <= transport vco_val after (sched_time + phase_shift(k));
else
vco_out(k) <= transport vco_val after (sched_time + last_phase_shift(k));
end if;
end loop;
end loop;
end loop;
-- schedule once more
if (first_schedule) then
vco_val := not vco_val;
if (vco_val = '0') then
sched_time := sched_time + high_time;
elsif (vco_val = '1') then
sched_time := sched_time + low_time;
end if;
-- schedule the phase taps
for k in 0 to 7 loop
phase_shift(k) := (k * vco_per)/8;
vco_out(k) <= transport vco_val after (sched_time + phase_shift(k));
end loop;
first_schedule := false;
end if;
schedule_vco <= transport not schedule_vco after sched_time;
if (vco_period_was_phase_adjusted) then
m_times_vco_period := refclk_period;
new_m_times_vco_period := refclk_period;
vco_period_was_phase_adjusted := false;
phase_adjust_was_scheduled := true;
vco_per := m_times_vco_period/loop_xplier;
for k in 0 to 7 loop
phase_shift(k) := (k * vco_per)/8;
end loop;
end if;
end if;
if (refclk'event and refclk = '1' and areset_ipd = '0') then
got_refclk_posedge := true;
if (not got_first_refclk) then
got_first_refclk := true;
else
got_second_refclk := true;
refclk_period := now - refclk_time;
-- check if incoming freq. will cause VCO range to be
-- exceeded
if ( (vco_max /= 0 and vco_min /= 0 and pfdena_ipd = '1') and
(((refclk_period/1 ps)/loop_xplier > vco_max) or
((refclk_period/1 ps)/loop_xplier < vco_min)) ) then
if (pll_is_locked) then
assert false report " Input clock freq. is not within VCO range : PLL may lose lock" severity warning;
if (inclk_out_of_range) then
pll_is_locked := false;
locked_tmp := '0';
pll_about_to_lock := false;
cycles_to_lock := 0;
vco_period_was_phase_adjusted := false;
phase_adjust_was_scheduled := false;
assert false report "Stratixii PLL lost lock." severity note;
end if;
elsif (not no_warn) then
assert false report " Input clock freq. is not within VCO range : PLL may not lock. Please use the correct frequency." severity warning;
no_warn := true;
end if;
inclk_out_of_range := true;
else
inclk_out_of_range := false;
end if;
end if;
if (stop_vco) then
stop_vco := false;
schedule_vco <= not schedule_vco;
end if;
refclk_time := now;
else
got_refclk_posedge := false;
end if;
if (fbclk'event and fbclk = '1') then
got_fbclk_posedge := true;
if (not got_first_fbclk) then
got_first_fbclk := true;
else
fbclk_period := now - fbclk_time;
end if;
-- need refclk_period here, so initialized to proper value above
if ( ( (now - refclk_time > 1.5 * refclk_period) and pfdena_ipd = '1' and pll_is_locked) or ( (now - refclk_time > 5 * refclk_period) and pfdena_ipd = '1') ) then
stop_vco := true;
-- reset
got_first_refclk := false;
got_first_fbclk := false;
got_second_refclk := false;
if (pll_is_locked) then
pll_is_locked := false;
locked_tmp := '0';
assert false report "PLL lost lock due to loss of input clock" severity note;
end if;
pll_about_to_lock := false;
cycles_to_lock := 0;
cycles_to_unlock := 0;
first_schedule := true;
vco_period_was_phase_adjusted := false;
phase_adjust_was_scheduled := false;
end if;
fbclk_time := now;
else
got_fbclk_posedge := false;
end if;
if ((got_refclk_posedge or got_fbclk_posedge) and got_second_refclk and pfdena_ipd = '1' and (not inclk_out_of_range)) then
-- now we know actual incoming period
if ( abs(fbclk_time - refclk_time) <= 5 ps or
(got_first_fbclk and abs(refclk_period - abs(fbclk_time - refclk_time)) <= 5 ps)) then
-- considered in phase
if (cycles_to_lock = valid_lock_multiplier - 1) then
pll_about_to_lock := true;
end if;
if (cycles_to_lock = valid_lock_multiplier) then
if (not pll_is_locked) then
assert false report "PLL locked to incoming clock" severity note;
end if;
pll_is_locked := true;
locked_tmp := '1';
cycles_to_unlock := 0;
end if;
-- increment lock counter only if second part of above
-- time check is NOT true
if (not(abs(refclk_period - abs(fbclk_time - refclk_time)) <= 5 ps)) then
cycles_to_lock := cycles_to_lock + 1;
end if;
-- adjust m_times_vco_period
new_m_times_vco_period := refclk_period;
else
-- if locked, begin unlock
if (pll_is_locked) then
cycles_to_unlock := cycles_to_unlock + 1;
if (cycles_to_unlock = invalid_lock_multiplier) then
pll_is_locked := false;
locked_tmp := '0';
pll_about_to_lock := false;
cycles_to_lock := 0;
vco_period_was_phase_adjusted := false;
phase_adjust_was_scheduled := false;
assert false report "PLL lost lock." severity note;
end if;
end if;
if ( abs(refclk_period - fbclk_period) <= 2 ps ) then
-- frequency is still good
if (now = fbclk_time and (not phase_adjust_was_scheduled)) then
if ( abs(fbclk_time - refclk_time) > refclk_period/2) then
new_m_times_vco_period := m_times_vco_period + (refclk_period - abs(fbclk_time - refclk_time));
vco_period_was_phase_adjusted := true;
else
new_m_times_vco_period := m_times_vco_period - abs(fbclk_time - refclk_time);
vco_period_was_phase_adjusted := true;
end if;
end if;
else
phase_adjust_was_scheduled := false;
new_m_times_vco_period := refclk_period;
end if;
end if;
end if;
if (pfdena_ipd = '0') then
if (pll_is_locked) then
locked_tmp := 'X';
end if;
pll_is_locked := false;
cycles_to_lock := 0;
end if;
-- give message only at time of deassertion
if (pfdena_ipd'event and pfdena_ipd = '0') then
assert false report "PFDENA deasserted." severity note;
elsif (pfdena_ipd'event and pfdena_ipd = '1') then
got_first_refclk := false;
got_second_refclk := false;
refclk_time := now;
end if;
if (reconfig_err) then
lock <= '0';
else
lock <= locked_tmp;
end if;
about_to_lock <= pll_about_to_lock after 1 ps;
-- signal to calculate quiet_time
sig_refclk_period <= refclk_period;
if (stop_vco = true) then
sig_stop_vco <= '1';
else
sig_stop_vco <= '0';
end if;
end process;
clk0_tmp <= c_clk(i_clk0_counter);
-- clk0_tmp <= c0_clk when i_clk0_counter = "c0" else
-- c_clk(1) when i_clk0_counter = "c1" else
-- c2_clk when i_clk0_counter = "c2" else
-- c3_clk when i_clk0_counter = "c3" else
-- c4_clk when i_clk0_counter = "c4" else
-- c5_clk when i_clk0_counter = "c5" else
-- '0';
clk(0) <= clk0_tmp when (areset_ipd = '1' or ena_ipd = '0' or pll_in_test_mode) or (about_to_lock and (not reconfig_err)) else
'X';
clk1_tmp <= c_clk(i_clk1_counter);
-- clk1_tmp <= c_clk(0) when i_clk1_counter = "c0" else
-- c_clk(1) when i_clk1_counter = "c1" else
-- c2_clk when i_clk1_counter = "c2" else
-- c3_clk when i_clk1_counter = "c3" else
-- c4_clk when i_clk1_counter = "c4" else
-- c5_clk when i_clk1_counter = "c5" else
-- '0';
clk(1) <= clk1_tmp when (areset_ipd = '1' or ena_ipd = '0' or pll_in_test_mode) or (about_to_lock and (not reconfig_err)) else
'X';
clk2_tmp <= c_clk(i_clk2_counter);
-- clk2_tmp <= c_clk(0) when i_clk2_counter = "c0" else
-- c_clk(1) when i_clk2_counter = "c1" else
-- c2_clk when i_clk2_counter = "c2" else
-- c3_clk when i_clk2_counter = "c3" else
-- c4_clk when i_clk2_counter = "c4" else
-- c5_clk when i_clk2_counter = "c5" else
-- '0';
clk(2) <= clk2_tmp when (areset_ipd = '1' or ena_ipd = '0' or pll_in_test_mode) or (about_to_lock and (not reconfig_err)) else
'X';
clk3_tmp <= c_clk(i_clk3_counter);
-- clk3_tmp <= c_clk(0) when i_clk3_counter = "c0" else
-- c_clk(1) when i_clk3_counter = "c1" else
-- c2_clk when i_clk3_counter = "c2" else
-- c3_clk when i_clk3_counter = "c3" else
-- c4_clk when i_clk3_counter = "c4" else
-- c5_clk when i_clk3_counter = "c5" else
-- '0';
clk(3) <= clk3_tmp when (areset_ipd = '1' or ena_ipd = '0' or pll_in_test_mode) or (about_to_lock and (not reconfig_err)) else
'X';
clk4_tmp <= c_clk(i_clk4_counter);
-- clk4_tmp <= c_clk(0) when i_clk4_counter = "c0" else
-- c_clk(1) when i_clk4_counter = "c1" else
-- c2_clk when i_clk4_counter = "c2" else
-- c3_clk when i_clk4_counter = "c3" else
-- c4_clk when i_clk4_counter = "c4" else
-- c5_clk when i_clk4_counter = "c5" else
-- '0';
clk(4) <= clk4_tmp when (areset_ipd = '1' or ena_ipd = '0' or pll_in_test_mode) or (about_to_lock and (not reconfig_err)) else
'X';
clk5_tmp <= c_clk(i_clk5_counter);
-- clk5_tmp <= c_clk(0) when i_clk5_counter = "c0" else
-- c_clk(1) when i_clk5_counter = "c1" else
-- c2_clk when i_clk5_counter = "c2" else
-- c3_clk when i_clk5_counter = "c3" else
-- c4_clk when i_clk5_counter = "c4" else
-- c5_clk when i_clk5_counter = "c5" else
-- '0';
clk(5) <= clk5_tmp when (areset_ipd = '1' or ena_ipd = '0' or pll_in_test_mode) or (about_to_lock and (not reconfig_err)) else
'X';
sclkout(0) <= sclkout0_tmp when (areset_ipd = '1' or ena_ipd = '0' or pll_in_test_mode) or (about_to_lock and (not reconfig_err)) else
'X';
sclkout(1) <= sclkout1_tmp when (areset_ipd = '1' or ena_ipd = '0' or pll_in_test_mode) or (about_to_lock and (not reconfig_err)) else
'X';
enable0 <= enable0_tmp when (areset_ipd = '1' or ena_ipd = '0' or pll_in_test_mode) or (about_to_lock and (not reconfig_err)) else
'X';
enable1 <= enable1_tmp when (areset_ipd = '1' or ena_ipd = '0' or pll_in_test_mode) or (about_to_lock and (not reconfig_err)) else
'X';
scandataout <= scandataout_tmp;
scandone <= scandone_tmp;
end vital_pll;
-- END ARCHITECTURE VITAL_PLL
--/////////////////////////////////////////////////////////////////////////////
--
-- Entity Name : stratixii_mac_bit_register
--
-- Description : a single bit register. This is used for registering all
-- single bit input ports.
--
--/////////////////////////////////////////////////////////////////////////////
LIBRARY IEEE;
USE ieee.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.stratixii_atom_pack.all;
ENTITY stratixii_mac_bit_register IS
GENERIC (
power_up : std_logic := '0';
tipd_data : VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
tipd_aclr : VitalDelayType01 := DefPropDelay01;
tpd_aclr_dataout_posedge : VitalDelayType01 := DefPropDelay01;
tpd_clk_dataout_posedge : VitalDelayType01 := DefPropDelay01;
tsetup_data_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_data_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst);
PORT (
data : IN std_logic := '0';
clk : IN std_logic := '0';
aclr : IN std_logic := '0';
if_aclr : IN std_logic := '0';
ena : IN std_logic := '1';
async : IN std_logic := '1';
dataout : OUT std_logic := '0'
);
END stratixii_mac_bit_register;
ARCHITECTURE arch OF stratixii_mac_bit_register IS
SIGNAL data_ipd : std_logic := '0';
SIGNAL clk_ipd : std_logic := '0';
SIGNAL aclr_ipd : std_logic := '0';
SIGNAL ena_ipd : std_logic := '1';
SIGNAL dataout_reg : std_logic := '0';
SIGNAL viol_notifier : std_logic := '0';
SIGNAL data_dly : std_logic := '0';
BEGIN
WireDelay : block
begin
VitalWireDelay (data_ipd, data, tipd_data);
VitalWireDelay (clk_ipd, clk, tipd_clk);
VitalWireDelay (aclr_ipd, aclr, tipd_aclr);
VitalWireDelay (ena_ipd, ena, tipd_ena);
end block;
clk_delay: process (data_ipd)
begin
data_dly <= data_ipd;
end process;
PROCESS (data_dly, clk_ipd, aclr_ipd, ena_ipd, async)
variable dataout_reg : STD_LOGIC := '0';
variable dataout_VitalGlitchData : VitalGlitchDataType;
variable Tviol_clk_ena : STD_ULOGIC := '0';
variable Tviol_data_clk : STD_ULOGIC := '0';
variable TimingData_clk_ena : VitalTimingDataType := VitalTimingDataInit;
variable TimingData_data_clk : VitalTimingDataType := VitalTimingDataInit;
variable Tviol_ena : STD_ULOGIC := '0';
variable PeriodData_ena : VitalPeriodDataType := VitalPeriodDataInit;
BEGIN
if(async = '1') then
dataout_reg := data_dly;
else
if (if_aclr = '1') then
IF (aclr_ipd = '1') THEN
dataout_reg := '0';
ELSIF (clk_ipd'EVENT AND clk_ipd = '1') THEN
IF (ena_ipd = '1') THEN
dataout_reg := data_dly;
ELSE
dataout_reg := dataout_reg;
END IF;
END IF;
else
IF (clk_ipd'EVENT AND clk_ipd = '1') THEN
IF (ena_ipd = '1') THEN
dataout_reg := data_dly;
ELSE
dataout_reg := dataout_reg;
END IF;
END IF;
end if;
end if;
VitalPathDelay01 (
OutSignal => dataout,
OutSignalName => "dataout",
OutTemp => dataout_reg,
Paths => (0 => (clk_ipd'last_event, tpd_clk_dataout_posedge, TRUE),
1 => (aclr_ipd'last_event, tpd_aclr_dataout_posedge, TRUE)),
GlitchData => dataout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => TRUE,
MsgOn => TRUE );
END PROCESS;
END arch;
--/////////////////////////////////////////////////////////////////////////////
--
-- STRATIXII_MAC_REGISTER
--
--/////////////////////////////////////////////////////////////////////////////
LIBRARY IEEE;
USE ieee.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.stratixii_atom_pack.all;
ENTITY stratixii_mac_register IS
GENERIC (
data_width : integer := 18;
power_up : std_logic := '0';
tipd_data : VitalDelayArrayType01(143 downto 0) := (OTHERS => DefPropDelay01);
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
tipd_aclr : VitalDelayType01 := DefPropDelay01;
tpd_aclr_dataout_posedge : VitalDelayType01 := DefPropDelay01;
tpd_clk_dataout_posedge : VitalDelayType01 := DefPropDelay01;
tsetup_data_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_data_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst);
PORT (
data : IN std_logic_vector(data_width -1 DOWNTO 0) := (others => '0');
clk : IN std_logic := '0';
aclr : IN std_logic := '0';
if_aclr : IN std_logic := '0';
ena : IN std_logic := '1';
async : IN std_logic := '1';
dataout : OUT std_logic_vector(data_width -1 DOWNTO 0) := (others => '0'));
END stratixii_mac_register;
ARCHITECTURE arch OF stratixii_mac_register IS
SIGNAL data_ipd : std_logic_vector(data_width -1 DOWNTO 0) := (others => '0');
SIGNAL clk_ipd : std_logic := '0';
SIGNAL aclr_ipd : std_logic := '0';
SIGNAL ena_ipd : std_logic := '1';
SIGNAL dataout_reg : std_logic_vector(data_width -1 DOWNTO 0) := (others => '0');
SIGNAL viol_notifier : std_logic := '0';
BEGIN
WireDelay : block
begin
g1 : for i in data'range generate
VitalWireDelay (data_ipd(i), data(i), tipd_data(i));
end generate;
VitalWireDelay (clk_ipd, clk, tipd_clk);
VitalWireDelay (aclr_ipd, aclr, tipd_aclr);
VitalWireDelay (ena_ipd, ena, tipd_ena);
end block;
PROCESS (data_ipd, clk_ipd, aclr_ipd, ena_ipd, async)
variable dataout_VitalGlitchDataArray : VitalGlitchDataArrayType(71 downto 0);
variable Tviol_clk_ena : STD_ULOGIC := '0';
variable Tviol_data_clk : STD_ULOGIC := '0';
variable TimingData_clk_ena : VitalTimingDataType := VitalTimingDataInit;
variable TimingData_data_clk : VitalTimingDataType := VitalTimingDataInit;
variable Tviol_ena : STD_ULOGIC := '0';
variable PeriodData_ena : VitalPeriodDataType := VitalPeriodDataInit;
BEGIN
if(async = '1') then
dataout_reg <= data_ipd;
else
if (if_aclr = '1') then
IF (aclr_ipd = '1') THEN
dataout_reg <= (others => '0');
ELSIF (clk_ipd'EVENT AND clk_ipd = '1') THEN
IF (ena_ipd = '1') THEN
dataout_reg <= data_ipd;
ELSE
dataout_reg <= dataout_reg;
END IF;
END IF;
else
IF (clk_ipd'EVENT AND clk_ipd = '1') THEN
IF (ena_ipd = '1') THEN
dataout_reg <= data_ipd;
ELSE
dataout_reg <= dataout_reg;
END IF;
END IF;
end if;
end if;
END PROCESS;
PathDelay : block
begin
g1 : for i in dataout'range generate
PROCESS (dataout_reg(i))
variable dataout_VitalGlitchData : VitalGlitchDataType;
begin
VitalPathDelay01 (
OutSignal => dataout(i),
OutSignalName => "dataout",
OutTemp => dataout_reg(i),
Paths => (0 => (clk_ipd'last_event, tpd_clk_dataout_posedge, TRUE),
1 => (aclr_ipd'last_event, tpd_aclr_dataout_posedge, TRUE)),
GlitchData => dataout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => TRUE,
MsgOn => TRUE );
end process;
end generate;
end block;
END arch;
--/////////////////////////////////////////////////////////////////////////////
--
-- STRATIXII_MAC_RS_BLOCK
--
--/////////////////////////////////////////////////////////////////////////////
LIBRARY IEEE;
USE ieee.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.stratixii_atom_pack.all;
library grlib;
use grlib.stdlib.all;
ENTITY stratixii_mac_rs_block IS
GENERIC (
tpd_saturate_dataout : VitalDelayType01 := DefPropDelay01;
tpd_round_dataout : VitalDelayType01 := DefPropDelay01;
block_type : string := "mac_mult";
dataa_width : integer := 18;
datab_width : integer := 18);
PORT (
operation : IN std_logic_vector(3 DOWNTO 0) := (others => '0');
round : IN std_logic := '0';
saturate : IN std_logic := '0';
addnsub : IN std_logic := '0';
signa : IN std_logic := '0';
signb : IN std_logic := '0';
signsize : IN std_logic_vector(7 DOWNTO 0) := (others => '0');
roundsize : IN std_logic_vector(7 DOWNTO 0) := (others => '0');
dataoutsize : IN std_logic_vector(7 DOWNTO 0) := (others => '0');
dataa : IN std_logic_vector(dataa_width-1 DOWNTO 0) := (others => '0');
datab : IN std_logic_vector(datab_width-1 DOWNTO 0) := (others => '0');
datain : IN std_logic_vector(71 DOWNTO 0) := (others => '0');
dataout : OUT std_logic_vector(71 DOWNTO 0) := (others => '0'));
END stratixii_mac_rs_block;
ARCHITECTURE arch OF stratixii_mac_rs_block IS
SIGNAL round_ipd : std_logic := '0';
SIGNAL saturate_ipd : std_logic := '0';
SIGNAL addnsub_ipd : std_logic := '0';
SIGNAL signa_ipd : std_logic := '0';
SIGNAL signb_ipd : std_logic := '0';
SIGNAL dataa_ipd : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL datab_ipd : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL datain_ipd : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL dataout_tbuf : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL rs_saturate : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL rs_mac_mult : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL rs_mac_out : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL dataout_round : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL dataout_saturate : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL dataout_dly : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL saturated : std_logic := '0';
SIGNAL min : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL max : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL msb : std_logic := '0';
SIGNAL dataout_tmp1 : std_logic_vector(71 DOWNTO 0) := (others => '0');
BEGIN
round_ipd <= round ;
saturate_ipd <= saturate ;
addnsub_ipd <= addnsub ;
signa_ipd <= signa ;
signb_ipd <= signb ;
dataa_ipd(dataa_width-1 downto 0) <= dataa;
datab_ipd(datab_width-1 downto 0) <= datab;
datain_ipd(71 downto 0) <= datain(71 downto 0) ;
PROCESS (datain_ipd,
signa_ipd,
signb_ipd,
addnsub_ipd,
round_ipd)
VARIABLE dataout_round_tmp2 : std_logic_vector(71 DOWNTO 0);
BEGIN
IF (round_ipd = '1') THEN
dataout_round_tmp2 := datain_ipd + (2 **(conv_integer(dataoutsize - signsize - roundsize - "00000001")));
ELSE
dataout_round_tmp2 := datain_ipd;
END IF;
dataout_round <= dataout_round_tmp2;
END PROCESS;
PROCESS (datain_ipd,
signa_ipd,
signb_ipd,
round_ipd,
saturate_ipd,
addnsub_ipd,
dataout_round)
VARIABLE dataout_saturate_tmp3 : std_logic_vector(71 DOWNTO 0) := (others => '0');
VARIABLE saturated_tmp4 : std_logic := '0';
VARIABLE gnd : std_logic_vector(71 DOWNTO 0) := (others => '0');
VARIABLE min_tmp5 : std_logic_vector(71 DOWNTO 0) := (others => '0');
VARIABLE max_tmp6 : std_logic_vector(71 DOWNTO 0) := (others => '0');
VARIABLE msb_tmp7 : std_logic := '0';
VARIABLE i : integer;
BEGIN
IF (saturate_ipd = '1') THEN
IF (block_type = "mac_mult") THEN
IF (dataout_round(dataa_width + datab_width - 1) = '0' AND dataout_round(dataa_width + datab_width - 2) = '1') THEN
dataout_saturate_tmp3 := "111111111111111111111111111111111111111111111111111111111111111111111111";
FOR i IN dataa_width + datab_width - 2 TO (72 - 1) LOOP
dataout_saturate_tmp3(i) := '0';
END LOOP;
saturated_tmp4 := '1';
ELSE
dataout_saturate_tmp3 := dataout_round;
saturated_tmp4 := '0';
END IF;
min_tmp5 := dataout_saturate_tmp3;
max_tmp6 := dataout_saturate_tmp3;
ELSE
IF ((operation(2) = '1') AND ((block_type = "ab") OR (block_type = "cd"))) THEN
saturated_tmp4 := '0';
i := datab_width - 2;
WHILE (i < (datab_width + signsize - 2)) LOOP
IF (dataout_round(datab_width - 2) /= dataout_round(i)) THEN
saturated_tmp4 := '1';
END IF;
i := i + 1;
END LOOP;
IF (saturated_tmp4 = '1') THEN
min_tmp5 := "111111111111111111111111111111111111111111111111111111111111111111111111";
max_tmp6 := "111111111111111111111111111111111111111111111111111111111111111111111111";
FOR i IN 0 TO ((datab_width - 2) - 1) LOOP
max_tmp6(i) := '0';
END LOOP;
FOR i IN datab_width - 2 TO (72 - 1) LOOP
min_tmp5(i) := '0';
END LOOP;
ELSE
dataout_saturate_tmp3 := dataout_round;
END IF;
msb_tmp7 := dataout_round(datab_width + 15);
ELSE
IF ((signa_ipd OR signb_ipd OR NOT addnsub_ipd) = '1') THEN
min_tmp5 := gnd + (2**((dataa_width)));
max_tmp6 := gnd + ((2**((dataa_width))) - 1);
ELSE
min_tmp5 := "000000000000000000000000000000000000000000000000000000000000000000000000";
max_tmp6 := gnd + ((2**((dataa_width + 1))) - 1);
END IF;
saturated_tmp4 := '0';
i := dataa_width - 2;
WHILE (i < (dataa_width + signsize - 1)) LOOP
IF (dataout_round(dataa_width - 2) /= dataout_round(i)) THEN
saturated_tmp4 := '1';
END IF;
i := i + 1;
END LOOP;
msb_tmp7 := dataout_round(i);
END IF;
IF (saturated_tmp4 = '1') THEN
IF (msb_tmp7 = '1') THEN
dataout_saturate_tmp3 := max_tmp6;
ELSE
dataout_saturate_tmp3 := min_tmp5;
END IF;
ELSE
dataout_saturate_tmp3 := dataout_round;
END IF;
END IF;
ELSE
saturated_tmp4 := '0';
dataout_saturate_tmp3 := dataout_round;
END IF;
dataout_saturate <= dataout_saturate_tmp3;
saturated <= saturated_tmp4;
min <= min_tmp5;
max <= max_tmp6;
msb <= msb_tmp7;
END PROCESS;
PROCESS (datain_ipd,
signa_ipd,
signb_ipd,
round_ipd,
saturate_ipd,
dataout_round,
dataout_saturate)
VARIABLE dataout_dly_tmp8 : std_logic_vector(71 DOWNTO 0);
VARIABLE i : integer;
BEGIN
IF (round_ipd = '1') THEN
dataout_dly_tmp8 := dataout_saturate;
i := 0;
WHILE (i < (dataoutsize - signsize - roundsize)) LOOP
dataout_dly_tmp8(i) := '0';
i := i + 1;
END LOOP;
ELSE
dataout_dly_tmp8 := dataout_saturate;
END IF;
dataout_dly <= dataout_dly_tmp8;
END PROCESS;
dataout_tbuf <= datain WHEN (operation = "0000") OR (operation = "0111") ELSE rs_saturate ;
rs_saturate <= rs_mac_mult WHEN (saturate_ipd = '1') ELSE rs_mac_out ;
rs_mac_mult <= (dataout_dly(71 DOWNTO 3) & "00" & saturated)
WHEN ((saturate_ipd = '1') AND (saturated = '1') AND (block_type = "mac_mult")) ELSE rs_mac_out ;
rs_mac_out <= (dataout_dly(71 DOWNTO 3) & saturated & datain_ipd(1 DOWNTO 0))
WHEN ((saturate_ipd = '1') AND (block_type /= "mac_mult")) ELSE dataout_dly ;
PROCESS (dataout_tbuf)
VARIABLE dataout_VitalGlitchDataArray : VitalGlitchDataArrayType(71 downto 0);
BEGIN
VitalPathDelay01 (
OutSignal => dataout(0),
OutSignalName => "dataout",
OutTemp => dataout_tbuf(0),
Paths => (0 => (round_ipd'last_event, tpd_round_dataout, TRUE),
1 => (saturate_ipd'last_event, tpd_saturate_dataout, TRUE)),
GlitchData => dataout_VitalGlitchDataArray(0),
Mode => DefGlitchMode,
XOn => TRUE,
MsgOn => TRUE );
VitalPathDelay01 (
OutSignal => dataout(1),
OutSignalName => "dataout",
OutTemp => dataout_tbuf(1),
Paths => (0 => (round_ipd'last_event, tpd_round_dataout, TRUE),
1 => (saturate_ipd'last_event, tpd_saturate_dataout, TRUE)),
GlitchData => dataout_VitalGlitchDataArray(1),
Mode => DefGlitchMode,
XOn => TRUE,
MsgOn => TRUE );
VitalPathDelay01 (
OutSignal => dataout(2),
OutSignalName => "dataout",
OutTemp => dataout_tbuf(2),
Paths => (0 => (round_ipd'last_event, tpd_round_dataout, TRUE),
1 => (saturate_ipd'last_event, tpd_saturate_dataout, TRUE)),
GlitchData => dataout_VitalGlitchDataArray(2),
Mode => DefGlitchMode,
XOn => TRUE,
MsgOn => TRUE );
VitalPathDelay01 (
OutSignal => dataout(3),
OutSignalName => "dataout",
OutTemp => dataout_tbuf(3),
Paths => (0 => (round_ipd'last_event, tpd_round_dataout, TRUE),
1 => (saturate_ipd'last_event, tpd_saturate_dataout, TRUE)),
GlitchData => dataout_VitalGlitchDataArray(3),
Mode => DefGlitchMode,
XOn => TRUE,
MsgOn => TRUE );
VitalPathDelay01 (
OutSignal => dataout(4),
OutSignalName => "dataout",
OutTemp => dataout_tbuf(4),
Paths => (0 => (round_ipd'last_event, tpd_round_dataout, TRUE),
1 => (saturate_ipd'last_event, tpd_saturate_dataout, TRUE)),
GlitchData => dataout_VitalGlitchDataArray(4),
Mode => DefGlitchMode,
XOn => TRUE,
MsgOn => TRUE );
VitalPathDelay01 (
OutSignal => dataout(5),
OutSignalName => "dataout",
OutTemp => dataout_tbuf(5),
Paths => (0 => (round_ipd'last_event, tpd_round_dataout, TRUE),
1 => (saturate_ipd'last_event, tpd_saturate_dataout, TRUE)),
GlitchData => dataout_VitalGlitchDataArray(5),
Mode => DefGlitchMode,
XOn => TRUE,
MsgOn => TRUE );
VitalPathDelay01 (
OutSignal => dataout(6),
OutSignalName => "dataout",
OutTemp => dataout_tbuf(6),
Paths => (0 => (round_ipd'last_event, tpd_round_dataout, TRUE),
1 => (saturate_ipd'last_event, tpd_saturate_dataout, TRUE)),
GlitchData => dataout_VitalGlitchDataArray(6),
Mode => DefGlitchMode,
XOn => TRUE,
MsgOn => TRUE );
VitalPathDelay01 (
OutSignal => dataout(7),
OutSignalName => "dataout",
OutTemp => dataout_tbuf(7),
Paths => (0 => (round_ipd'last_event, tpd_round_dataout, TRUE),
1 => (saturate_ipd'last_event, tpd_saturate_dataout, TRUE)),
GlitchData => dataout_VitalGlitchDataArray(7),
Mode => DefGlitchMode,
XOn => TRUE,
MsgOn => TRUE );
VitalPathDelay01 (
OutSignal => dataout(8),
OutSignalName => "dataout",
OutTemp => dataout_tbuf(8),
Paths => (0 => (round_ipd'last_event, tpd_round_dataout, TRUE),
1 => (saturate_ipd'last_event, tpd_saturate_dataout, TRUE)),
GlitchData => dataout_VitalGlitchDataArray(8),
Mode => DefGlitchMode,
XOn => TRUE,
MsgOn => TRUE );
VitalPathDelay01 (
OutSignal => dataout(9),
OutSignalName => "dataout",
OutTemp => dataout_tbuf(9),
Paths => (0 => (round_ipd'last_event, tpd_round_dataout, TRUE),
1 => (saturate_ipd'last_event, tpd_saturate_dataout, TRUE)),
GlitchData => dataout_VitalGlitchDataArray(9),
Mode => DefGlitchMode,
XOn => TRUE,
MsgOn => TRUE );
VitalPathDelay01 (
OutSignal => dataout(10),
OutSignalName => "dataout",
OutTemp => dataout_tbuf(10),
Paths => (0 => (round_ipd'last_event, tpd_round_dataout, TRUE),
1 => (saturate_ipd'last_event, tpd_saturate_dataout, TRUE)),
GlitchData => dataout_VitalGlitchDataArray(10),
Mode => DefGlitchMode,
XOn => TRUE,
MsgOn => TRUE );
VitalPathDelay01 (
OutSignal => dataout(11),
OutSignalName => "dataout",
OutTemp => dataout_tbuf(11),
Paths => (0 => (round_ipd'last_event, tpd_round_dataout, TRUE),
1 => (saturate_ipd'last_event, tpd_saturate_dataout, TRUE)),
GlitchData => dataout_VitalGlitchDataArray(11),
Mode => DefGlitchMode,
XOn => TRUE,
MsgOn => TRUE );
VitalPathDelay01 (
OutSignal => dataout(12),
OutSignalName => "dataout",
OutTemp => dataout_tbuf(12),
Paths => (0 => (round_ipd'last_event, tpd_round_dataout, TRUE),
1 => (saturate_ipd'last_event, tpd_saturate_dataout, TRUE)),
GlitchData => dataout_VitalGlitchDataArray(12),
Mode => DefGlitchMode,
XOn => TRUE,
MsgOn => TRUE );
VitalPathDelay01 (
OutSignal => dataout(13),
OutSignalName => "dataout",
OutTemp => dataout_tbuf(13),
Paths => (0 => (round_ipd'last_event, tpd_round_dataout, TRUE),
1 => (saturate_ipd'last_event, tpd_saturate_dataout, TRUE)),
GlitchData => dataout_VitalGlitchDataArray(13),
Mode => DefGlitchMode,
XOn => TRUE,
MsgOn => TRUE );
VitalPathDelay01 (
OutSignal => dataout(14),
OutSignalName => "dataout",
OutTemp => dataout_tbuf(14),
Paths => (0 => (round_ipd'last_event, tpd_round_dataout, TRUE),
1 => (saturate_ipd'last_event, tpd_saturate_dataout, TRUE)),
GlitchData => dataout_VitalGlitchDataArray(14),
Mode => DefGlitchMode,
XOn => TRUE,
MsgOn => TRUE );
VitalPathDelay01 (
OutSignal => dataout(15),
OutSignalName => "dataout",
OutTemp => dataout_tbuf(15),
Paths => (0 => (round_ipd'last_event, tpd_round_dataout, TRUE),
1 => (saturate_ipd'last_event, tpd_saturate_dataout, TRUE)),
GlitchData => dataout_VitalGlitchDataArray(15),
Mode => DefGlitchMode,
XOn => TRUE,
MsgOn => TRUE );
VitalPathDelay01 (
OutSignal => dataout(16),
OutSignalName => "dataout",
OutTemp => dataout_tbuf(16),
Paths => (0 => (round_ipd'last_event, tpd_round_dataout, TRUE),
1 => (saturate_ipd'last_event, tpd_saturate_dataout, TRUE)),
GlitchData => dataout_VitalGlitchDataArray(16),
Mode => DefGlitchMode,
XOn => TRUE,
MsgOn => TRUE );
VitalPathDelay01 (
OutSignal => dataout(17),
OutSignalName => "dataout",
OutTemp => dataout_tbuf(17),
Paths => (0 => (round_ipd'last_event, tpd_round_dataout, TRUE),
1 => (saturate_ipd'last_event, tpd_saturate_dataout, TRUE)),
GlitchData => dataout_VitalGlitchDataArray(17),
Mode => DefGlitchMode,
XOn => TRUE,
MsgOn => TRUE );
VitalPathDelay01 (
OutSignal => dataout(18),
OutSignalName => "dataout",
OutTemp => dataout_tbuf(18),
Paths => (0 => (round_ipd'last_event, tpd_round_dataout, TRUE),
1 => (saturate_ipd'last_event, tpd_saturate_dataout, TRUE)),
GlitchData => dataout_VitalGlitchDataArray(18),
Mode => DefGlitchMode,
XOn => TRUE,
MsgOn => TRUE );
VitalPathDelay01 (
OutSignal => dataout(19),
OutSignalName => "dataout",
OutTemp => dataout_tbuf(19),
Paths => (0 => (round_ipd'last_event, tpd_round_dataout, TRUE),
1 => (saturate_ipd'last_event, tpd_saturate_dataout, TRUE)),
GlitchData => dataout_VitalGlitchDataArray(19),
Mode => DefGlitchMode,
XOn => TRUE,
MsgOn => TRUE );
VitalPathDelay01 (
OutSignal => dataout(20),
OutSignalName => "dataout",
OutTemp => dataout_tbuf(20),
Paths => (0 => (round_ipd'last_event, tpd_round_dataout, TRUE),
1 => (saturate_ipd'last_event, tpd_saturate_dataout, TRUE)),
GlitchData => dataout_VitalGlitchDataArray(20),
Mode => DefGlitchMode,
XOn => TRUE,
MsgOn => TRUE );
VitalPathDelay01 (
OutSignal => dataout(21),
OutSignalName => "dataout",
OutTemp => dataout_tbuf(21),
Paths => (0 => (round_ipd'last_event, tpd_round_dataout, TRUE),
1 => (saturate_ipd'last_event, tpd_saturate_dataout, TRUE)),
GlitchData => dataout_VitalGlitchDataArray(21),
Mode => DefGlitchMode,
XOn => TRUE,
MsgOn => TRUE );
VitalPathDelay01 (
OutSignal => dataout(22),
OutSignalName => "dataout",
OutTemp => dataout_tbuf(22),
Paths => (0 => (round_ipd'last_event, tpd_round_dataout, TRUE),
1 => (saturate_ipd'last_event, tpd_saturate_dataout, TRUE)),
GlitchData => dataout_VitalGlitchDataArray(22),
Mode => DefGlitchMode,
XOn => TRUE,
MsgOn => TRUE );
VitalPathDelay01 (
OutSignal => dataout(23),
OutSignalName => "dataout",
OutTemp => dataout_tbuf(23),
Paths => (0 => (round_ipd'last_event, tpd_round_dataout, TRUE),
1 => (saturate_ipd'last_event, tpd_saturate_dataout, TRUE)),
GlitchData => dataout_VitalGlitchDataArray(23),
Mode => DefGlitchMode,
XOn => TRUE,
MsgOn => TRUE );
VitalPathDelay01 (
OutSignal => dataout(24),
OutSignalName => "dataout",
OutTemp => dataout_tbuf(24),
Paths => (0 => (round_ipd'last_event, tpd_round_dataout, TRUE),
1 => (saturate_ipd'last_event, tpd_saturate_dataout, TRUE)),
GlitchData => dataout_VitalGlitchDataArray(24),
Mode => DefGlitchMode,
XOn => TRUE,
MsgOn => TRUE );
VitalPathDelay01 (
OutSignal => dataout(25),
OutSignalName => "dataout",
OutTemp => dataout_tbuf(25),
Paths => (0 => (round_ipd'last_event, tpd_round_dataout, TRUE),
1 => (saturate_ipd'last_event, tpd_saturate_dataout, TRUE)),
GlitchData => dataout_VitalGlitchDataArray(25),
Mode => DefGlitchMode,
XOn => TRUE,
MsgOn => TRUE );
VitalPathDelay01 (
OutSignal => dataout(26),
OutSignalName => "dataout",
OutTemp => dataout_tbuf(26),
Paths => (0 => (round_ipd'last_event, tpd_round_dataout, TRUE),
1 => (saturate_ipd'last_event, tpd_saturate_dataout, TRUE)),
GlitchData => dataout_VitalGlitchDataArray(26),
Mode => DefGlitchMode,
XOn => TRUE,
MsgOn => TRUE );
VitalPathDelay01 (
OutSignal => dataout(27),
OutSignalName => "dataout",
OutTemp => dataout_tbuf(27),
Paths => (0 => (round_ipd'last_event, tpd_round_dataout, TRUE),
1 => (saturate_ipd'last_event, tpd_saturate_dataout, TRUE)),
GlitchData => dataout_VitalGlitchDataArray(27),
Mode => DefGlitchMode,
XOn => TRUE,
MsgOn => TRUE );
VitalPathDelay01 (
OutSignal => dataout(28),
OutSignalName => "dataout",
OutTemp => dataout_tbuf(28),
Paths => (0 => (round_ipd'last_event, tpd_round_dataout, TRUE),
1 => (saturate_ipd'last_event, tpd_saturate_dataout, TRUE)),
GlitchData => dataout_VitalGlitchDataArray(28),
Mode => DefGlitchMode,
XOn => TRUE,
MsgOn => TRUE );
VitalPathDelay01 (
OutSignal => dataout(29),
OutSignalName => "dataout",
OutTemp => dataout_tbuf(29),
Paths => (0 => (round_ipd'last_event, tpd_round_dataout, TRUE),
1 => (saturate_ipd'last_event, tpd_saturate_dataout, TRUE)),
GlitchData => dataout_VitalGlitchDataArray(29),
Mode => DefGlitchMode,
XOn => TRUE,
MsgOn => TRUE );
VitalPathDelay01 (
OutSignal => dataout(30),
OutSignalName => "dataout",
OutTemp => dataout_tbuf(30),
Paths => (0 => (round_ipd'last_event, tpd_round_dataout, TRUE),
1 => (saturate_ipd'last_event, tpd_saturate_dataout, TRUE)),
GlitchData => dataout_VitalGlitchDataArray(30),
Mode => DefGlitchMode,
XOn => TRUE,
MsgOn => TRUE );
VitalPathDelay01 (
OutSignal => dataout(31),
OutSignalName => "dataout",
OutTemp => dataout_tbuf(31),
Paths => (0 => (round_ipd'last_event, tpd_round_dataout, TRUE),
1 => (saturate_ipd'last_event, tpd_saturate_dataout, TRUE)),
GlitchData => dataout_VitalGlitchDataArray(31),
Mode => DefGlitchMode,
XOn => TRUE,
MsgOn => TRUE );
VitalPathDelay01 (
OutSignal => dataout(32),
OutSignalName => "dataout",
OutTemp => dataout_tbuf(32),
Paths => (0 => (round_ipd'last_event, tpd_round_dataout, TRUE),
1 => (saturate_ipd'last_event, tpd_saturate_dataout, TRUE)),
GlitchData => dataout_VitalGlitchDataArray(32),
Mode => DefGlitchMode,
XOn => TRUE,
MsgOn => TRUE );
VitalPathDelay01 (
OutSignal => dataout(33),
OutSignalName => "dataout",
OutTemp => dataout_tbuf(33),
Paths => (0 => (round_ipd'last_event, tpd_round_dataout, TRUE),
1 => (saturate_ipd'last_event, tpd_saturate_dataout, TRUE)),
GlitchData => dataout_VitalGlitchDataArray(33),
Mode => DefGlitchMode,
XOn => TRUE,
MsgOn => TRUE );
VitalPathDelay01 (
OutSignal => dataout(34),
OutSignalName => "dataout",
OutTemp => dataout_tbuf(34),
Paths => (0 => (round_ipd'last_event, tpd_round_dataout, TRUE),
1 => (saturate_ipd'last_event, tpd_saturate_dataout, TRUE)),
GlitchData => dataout_VitalGlitchDataArray(34),
Mode => DefGlitchMode,
XOn => TRUE,
MsgOn => TRUE );
VitalPathDelay01 (
OutSignal => dataout(35),
OutSignalName => "dataout",
OutTemp => dataout_tbuf(35),
Paths => (0 => (round_ipd'last_event, tpd_round_dataout, TRUE),
1 => (saturate_ipd'last_event, tpd_saturate_dataout, TRUE)),
GlitchData => dataout_VitalGlitchDataArray(35),
Mode => DefGlitchMode,
XOn => TRUE,
MsgOn => TRUE );
VitalPathDelay01 (
OutSignal => dataout(36),
OutSignalName => "dataout",
OutTemp => dataout_tbuf(36),
Paths => (0 => (round_ipd'last_event, tpd_round_dataout, TRUE),
1 => (saturate_ipd'last_event, tpd_saturate_dataout, TRUE)),
GlitchData => dataout_VitalGlitchDataArray(36),
Mode => DefGlitchMode,
XOn => TRUE,
MsgOn => TRUE );
VitalPathDelay01 (
OutSignal => dataout(37),
OutSignalName => "dataout",
OutTemp => dataout_tbuf(37),
Paths => (0 => (round_ipd'last_event, tpd_round_dataout, TRUE),
1 => (saturate_ipd'last_event, tpd_saturate_dataout, TRUE)),
GlitchData => dataout_VitalGlitchDataArray(37),
Mode => DefGlitchMode,
XOn => TRUE,
MsgOn => TRUE );
VitalPathDelay01 (
OutSignal => dataout(38),
OutSignalName => "dataout",
OutTemp => dataout_tbuf(38),
Paths => (0 => (round_ipd'last_event, tpd_round_dataout, TRUE),
1 => (saturate_ipd'last_event, tpd_saturate_dataout, TRUE)),
GlitchData => dataout_VitalGlitchDataArray(38),
Mode => DefGlitchMode,
XOn => TRUE,
MsgOn => TRUE );
VitalPathDelay01 (
OutSignal => dataout(39),
OutSignalName => "dataout",
OutTemp => dataout_tbuf(39),
Paths => (0 => (round_ipd'last_event, tpd_round_dataout, TRUE),
1 => (saturate_ipd'last_event, tpd_saturate_dataout, TRUE)),
GlitchData => dataout_VitalGlitchDataArray(39),
Mode => DefGlitchMode,
XOn => TRUE,
MsgOn => TRUE );
VitalPathDelay01 (
OutSignal => dataout(40),
OutSignalName => "dataout",
OutTemp => dataout_tbuf(40),
Paths => (0 => (round_ipd'last_event, tpd_round_dataout, TRUE),
1 => (saturate_ipd'last_event, tpd_saturate_dataout, TRUE)),
GlitchData => dataout_VitalGlitchDataArray(40),
Mode => DefGlitchMode,
XOn => TRUE,
MsgOn => TRUE );
VitalPathDelay01 (
OutSignal => dataout(41),
OutSignalName => "dataout",
OutTemp => dataout_tbuf(41),
Paths => (0 => (round_ipd'last_event, tpd_round_dataout, TRUE),
1 => (saturate_ipd'last_event, tpd_saturate_dataout, TRUE)),
GlitchData => dataout_VitalGlitchDataArray(41),
Mode => DefGlitchMode,
XOn => TRUE,
MsgOn => TRUE );
VitalPathDelay01 (
OutSignal => dataout(42),
OutSignalName => "dataout",
OutTemp => dataout_tbuf(42),
Paths => (0 => (round_ipd'last_event, tpd_round_dataout, TRUE),
1 => (saturate_ipd'last_event, tpd_saturate_dataout, TRUE)),
GlitchData => dataout_VitalGlitchDataArray(42),
Mode => DefGlitchMode,
XOn => TRUE,
MsgOn => TRUE );
VitalPathDelay01 (
OutSignal => dataout(43),
OutSignalName => "dataout",
OutTemp => dataout_tbuf(43),
Paths => (0 => (round_ipd'last_event, tpd_round_dataout, TRUE),
1 => (saturate_ipd'last_event, tpd_saturate_dataout, TRUE)),
GlitchData => dataout_VitalGlitchDataArray(43),
Mode => DefGlitchMode,
XOn => TRUE,
MsgOn => TRUE );
VitalPathDelay01 (
OutSignal => dataout(44),
OutSignalName => "dataout",
OutTemp => dataout_tbuf(44),
Paths => (0 => (round_ipd'last_event, tpd_round_dataout, TRUE),
1 => (saturate_ipd'last_event, tpd_saturate_dataout, TRUE)),
GlitchData => dataout_VitalGlitchDataArray(44),
Mode => DefGlitchMode,
XOn => TRUE,
MsgOn => TRUE );
VitalPathDelay01 (
OutSignal => dataout(45),
OutSignalName => "dataout",
OutTemp => dataout_tbuf(45),
Paths => (0 => (round_ipd'last_event, tpd_round_dataout, TRUE),
1 => (saturate_ipd'last_event, tpd_saturate_dataout, TRUE)),
GlitchData => dataout_VitalGlitchDataArray(45),
Mode => DefGlitchMode,
XOn => TRUE,
MsgOn => TRUE );
VitalPathDelay01 (
OutSignal => dataout(46),
OutSignalName => "dataout",
OutTemp => dataout_tbuf(46),
Paths => (0 => (round_ipd'last_event, tpd_round_dataout, TRUE),
1 => (saturate_ipd'last_event, tpd_saturate_dataout, TRUE)),
GlitchData => dataout_VitalGlitchDataArray(46),
Mode => DefGlitchMode,
XOn => TRUE,
MsgOn => TRUE );
VitalPathDelay01 (
OutSignal => dataout(47),
OutSignalName => "dataout",
OutTemp => dataout_tbuf(47),
Paths => (0 => (round_ipd'last_event, tpd_round_dataout, TRUE),
1 => (saturate_ipd'last_event, tpd_saturate_dataout, TRUE)),
GlitchData => dataout_VitalGlitchDataArray(47),
Mode => DefGlitchMode,
XOn => TRUE,
MsgOn => TRUE );
VitalPathDelay01 (
OutSignal => dataout(48),
OutSignalName => "dataout",
OutTemp => dataout_tbuf(48),
Paths => (0 => (round_ipd'last_event, tpd_round_dataout, TRUE),
1 => (saturate_ipd'last_event, tpd_saturate_dataout, TRUE)),
GlitchData => dataout_VitalGlitchDataArray(48),
Mode => DefGlitchMode,
XOn => TRUE,
MsgOn => TRUE );
VitalPathDelay01 (
OutSignal => dataout(49),
OutSignalName => "dataout",
OutTemp => dataout_tbuf(49),
Paths => (0 => (round_ipd'last_event, tpd_round_dataout, TRUE),
1 => (saturate_ipd'last_event, tpd_saturate_dataout, TRUE)),
GlitchData => dataout_VitalGlitchDataArray(49),
Mode => DefGlitchMode,
XOn => TRUE,
MsgOn => TRUE );
VitalPathDelay01 (
OutSignal => dataout(50),
OutSignalName => "dataout",
OutTemp => dataout_tbuf(50),
Paths => (0 => (round_ipd'last_event, tpd_round_dataout, TRUE),
1 => (saturate_ipd'last_event, tpd_saturate_dataout, TRUE)),
GlitchData => dataout_VitalGlitchDataArray(50),
Mode => DefGlitchMode,
XOn => TRUE,
MsgOn => TRUE );
VitalPathDelay01 (
OutSignal => dataout(51),
OutSignalName => "dataout",
OutTemp => dataout_tbuf(51),
Paths => (0 => (round_ipd'last_event, tpd_round_dataout, TRUE),
1 => (saturate_ipd'last_event, tpd_saturate_dataout, TRUE)),
GlitchData => dataout_VitalGlitchDataArray(51),
Mode => DefGlitchMode,
XOn => TRUE,
MsgOn => TRUE );
VitalPathDelay01 (
OutSignal => dataout(52),
OutSignalName => "dataout",
OutTemp => dataout_tbuf(52),
Paths => (0 => (round_ipd'last_event, tpd_round_dataout, TRUE),
1 => (saturate_ipd'last_event, tpd_saturate_dataout, TRUE)),
GlitchData => dataout_VitalGlitchDataArray(52),
Mode => DefGlitchMode,
XOn => TRUE,
MsgOn => TRUE );
VitalPathDelay01 (
OutSignal => dataout(53),
OutSignalName => "dataout",
OutTemp => dataout_tbuf(53),
Paths => (0 => (round_ipd'last_event, tpd_round_dataout, TRUE),
1 => (saturate_ipd'last_event, tpd_saturate_dataout, TRUE)),
GlitchData => dataout_VitalGlitchDataArray(53),
Mode => DefGlitchMode,
XOn => TRUE,
MsgOn => TRUE );
VitalPathDelay01 (
OutSignal => dataout(54),
OutSignalName => "dataout",
OutTemp => dataout_tbuf(54),
Paths => (0 => (round_ipd'last_event, tpd_round_dataout, TRUE),
1 => (saturate_ipd'last_event, tpd_saturate_dataout, TRUE)),
GlitchData => dataout_VitalGlitchDataArray(54),
Mode => DefGlitchMode,
XOn => TRUE,
MsgOn => TRUE );
VitalPathDelay01 (
OutSignal => dataout(55),
OutSignalName => "dataout",
OutTemp => dataout_tbuf(55),
Paths => (0 => (round_ipd'last_event, tpd_round_dataout, TRUE),
1 => (saturate_ipd'last_event, tpd_saturate_dataout, TRUE)),
GlitchData => dataout_VitalGlitchDataArray(55),
Mode => DefGlitchMode,
XOn => TRUE,
MsgOn => TRUE );
VitalPathDelay01 (
OutSignal => dataout(56),
OutSignalName => "dataout",
OutTemp => dataout_tbuf(56),
Paths => (0 => (round_ipd'last_event, tpd_round_dataout, TRUE),
1 => (saturate_ipd'last_event, tpd_saturate_dataout, TRUE)),
GlitchData => dataout_VitalGlitchDataArray(56),
Mode => DefGlitchMode,
XOn => TRUE,
MsgOn => TRUE );
VitalPathDelay01 (
OutSignal => dataout(57),
OutSignalName => "dataout",
OutTemp => dataout_tbuf(57),
Paths => (0 => (round_ipd'last_event, tpd_round_dataout, TRUE),
1 => (saturate_ipd'last_event, tpd_saturate_dataout, TRUE)),
GlitchData => dataout_VitalGlitchDataArray(57),
Mode => DefGlitchMode,
XOn => TRUE,
MsgOn => TRUE );
VitalPathDelay01 (
OutSignal => dataout(58),
OutSignalName => "dataout",
OutTemp => dataout_tbuf(58),
Paths => (0 => (round_ipd'last_event, tpd_round_dataout, TRUE),
1 => (saturate_ipd'last_event, tpd_saturate_dataout, TRUE)),
GlitchData => dataout_VitalGlitchDataArray(58),
Mode => DefGlitchMode,
XOn => TRUE,
MsgOn => TRUE );
VitalPathDelay01 (
OutSignal => dataout(59),
OutSignalName => "dataout",
OutTemp => dataout_tbuf(59),
Paths => (0 => (round_ipd'last_event, tpd_round_dataout, TRUE),
1 => (saturate_ipd'last_event, tpd_saturate_dataout, TRUE)),
GlitchData => dataout_VitalGlitchDataArray(59),
Mode => DefGlitchMode,
XOn => TRUE,
MsgOn => TRUE );
VitalPathDelay01 (
OutSignal => dataout(60),
OutSignalName => "dataout",
OutTemp => dataout_tbuf(60),
Paths => (0 => (round_ipd'last_event, tpd_round_dataout, TRUE),
1 => (saturate_ipd'last_event, tpd_saturate_dataout, TRUE)),
GlitchData => dataout_VitalGlitchDataArray(60),
Mode => DefGlitchMode,
XOn => TRUE,
MsgOn => TRUE );
VitalPathDelay01 (
OutSignal => dataout(61),
OutSignalName => "dataout",
OutTemp => dataout_tbuf(61),
Paths => (0 => (round_ipd'last_event, tpd_round_dataout, TRUE),
1 => (saturate_ipd'last_event, tpd_saturate_dataout, TRUE)),
GlitchData => dataout_VitalGlitchDataArray(61),
Mode => DefGlitchMode,
XOn => TRUE,
MsgOn => TRUE );
VitalPathDelay01 (
OutSignal => dataout(62),
OutSignalName => "dataout",
OutTemp => dataout_tbuf(62),
Paths => (0 => (round_ipd'last_event, tpd_round_dataout, TRUE),
1 => (saturate_ipd'last_event, tpd_saturate_dataout, TRUE)),
GlitchData => dataout_VitalGlitchDataArray(62),
Mode => DefGlitchMode,
XOn => TRUE,
MsgOn => TRUE );
VitalPathDelay01 (
OutSignal => dataout(63),
OutSignalName => "dataout",
OutTemp => dataout_tbuf(63),
Paths => (0 => (round_ipd'last_event, tpd_round_dataout, TRUE),
1 => (saturate_ipd'last_event, tpd_saturate_dataout, TRUE)),
GlitchData => dataout_VitalGlitchDataArray(63),
Mode => DefGlitchMode,
XOn => TRUE,
MsgOn => TRUE );
VitalPathDelay01 (
OutSignal => dataout(64),
OutSignalName => "dataout",
OutTemp => dataout_tbuf(64),
Paths => (0 => (round_ipd'last_event, tpd_round_dataout, TRUE),
1 => (saturate_ipd'last_event, tpd_saturate_dataout, TRUE)),
GlitchData => dataout_VitalGlitchDataArray(64),
Mode => DefGlitchMode,
XOn => TRUE,
MsgOn => TRUE );
VitalPathDelay01 (
OutSignal => dataout(65),
OutSignalName => "dataout",
OutTemp => dataout_tbuf(65),
Paths => (0 => (round_ipd'last_event, tpd_round_dataout, TRUE),
1 => (saturate_ipd'last_event, tpd_saturate_dataout, TRUE)),
GlitchData => dataout_VitalGlitchDataArray(65),
Mode => DefGlitchMode,
XOn => TRUE,
MsgOn => TRUE );
VitalPathDelay01 (
OutSignal => dataout(66),
OutSignalName => "dataout",
OutTemp => dataout_tbuf(66),
Paths => (0 => (round_ipd'last_event, tpd_round_dataout, TRUE),
1 => (saturate_ipd'last_event, tpd_saturate_dataout, TRUE)),
GlitchData => dataout_VitalGlitchDataArray(66),
Mode => DefGlitchMode,
XOn => TRUE,
MsgOn => TRUE );
VitalPathDelay01 (
OutSignal => dataout(67),
OutSignalName => "dataout",
OutTemp => dataout_tbuf(67),
Paths => (0 => (round_ipd'last_event, tpd_round_dataout, TRUE),
1 => (saturate_ipd'last_event, tpd_saturate_dataout, TRUE)),
GlitchData => dataout_VitalGlitchDataArray(67),
Mode => DefGlitchMode,
XOn => TRUE,
MsgOn => TRUE );
VitalPathDelay01 (
OutSignal => dataout(68),
OutSignalName => "dataout",
OutTemp => dataout_tbuf(68),
Paths => (0 => (round_ipd'last_event, tpd_round_dataout, TRUE),
1 => (saturate_ipd'last_event, tpd_saturate_dataout, TRUE)),
GlitchData => dataout_VitalGlitchDataArray(68),
Mode => DefGlitchMode,
XOn => TRUE,
MsgOn => TRUE );
VitalPathDelay01 (
OutSignal => dataout(69),
OutSignalName => "dataout",
OutTemp => dataout_tbuf(69),
Paths => (0 => (round_ipd'last_event, tpd_round_dataout, TRUE),
1 => (saturate_ipd'last_event, tpd_saturate_dataout, TRUE)),
GlitchData => dataout_VitalGlitchDataArray(69),
Mode => DefGlitchMode,
XOn => TRUE,
MsgOn => TRUE );
VitalPathDelay01 (
OutSignal => dataout(70),
OutSignalName => "dataout",
OutTemp => dataout_tbuf(70),
Paths => (0 => (round_ipd'last_event, tpd_round_dataout, TRUE),
1 => (saturate_ipd'last_event, tpd_saturate_dataout, TRUE)),
GlitchData => dataout_VitalGlitchDataArray(70),
Mode => DefGlitchMode,
XOn => TRUE,
MsgOn => TRUE );
VitalPathDelay01 (
OutSignal => dataout(71),
OutSignalName => "dataout",
OutTemp => dataout_tbuf(71),
Paths => (0 => (round_ipd'last_event, tpd_round_dataout, TRUE),
1 => (saturate_ipd'last_event, tpd_saturate_dataout, TRUE)),
GlitchData => dataout_VitalGlitchDataArray(71),
Mode => DefGlitchMode,
XOn => TRUE,
MsgOn => TRUE );
end process;
END arch;
--/////////////////////////////////////////////////////////////////////////////
--
-- STRATIXII_MAC_MULT_INTERNAL
--
--/////////////////////////////////////////////////////////////////////////////
LIBRARY IEEE;
USE ieee.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.stratixii_atom_pack.all;
library grlib;
use grlib.stdlib.all;
ENTITY stratixii_mac_mult_internal IS
GENERIC (
dataa_width : integer := 18;
datab_width : integer := 18;
dataout_width : integer := 36;
dynamic_mode : string := "no";
tipd_dataa : VitalDelayArrayType01(17 downto 0) := (OTHERS => DefPropDelay01);
tipd_datab : VitalDelayArrayType01(17 downto 0) := (OTHERS => DefPropDelay01);
tpd_dataa_dataout : VitalDelayType01 := DefPropDelay01;
tpd_datab_dataout : VitalDelayType01 := DefPropDelay01;
tpd_signa_dataout : VitalDelayType01 := DefPropDelay01;
tpd_signb_dataout : VitalDelayType01 := DefPropDelay01;
tpd_dataa_scanouta : VitalDelayType01 := DefPropDelay01;
tpd_datab_scanoutb : VitalDelayType01 := DefPropDelay01;
XOn : Boolean := DefGlitchXOn;
MsgOn : Boolean := DefGlitchMsgOn
);
PORT (
dataa : IN std_logic_vector(dataa_width - 1 DOWNTO 0) := (others => '0');
datab : IN std_logic_vector(datab_width - 1 DOWNTO 0) := (others => '0');
signa : IN std_logic := '0';
signb : IN std_logic := '0';
bypass : IN std_logic := '0';
scanouta : OUT std_logic_vector(dataa_width - 1 DOWNTO 0) := (others => '0');
scanoutb : OUT std_logic_vector(datab_width - 1 DOWNTO 0) := (others => '0');
dataout : OUT std_logic_vector(35 DOWNTO 0) := (others => '0')
);
END stratixii_mac_mult_internal;
ARCHITECTURE arch OF stratixii_mac_mult_internal IS
SIGNAL dataa_ipd : std_logic_vector(17 DOWNTO 0) := (others => '0');
SIGNAL datab_ipd : std_logic_vector(17 DOWNTO 0) := (others => '0');
SIGNAL neg : std_logic := '0';
SIGNAL dataout_pre_bypass : std_logic_vector((dataa_width+datab_width) -1 DOWNTO 0) := (others => '0');
SIGNAL dataout_tmp : std_logic_vector((dataa_width+datab_width) -1 DOWNTO 0) := (others => '0');
SIGNAL abs_a : std_logic_vector(dataa_width - 1 DOWNTO 0) := (others => '0');
SIGNAL abs_b : std_logic_vector(datab_width - 1 DOWNTO 0) := (others => '0');
SIGNAL abs_output : std_logic_vector((dataa_width+datab_width) -1 DOWNTO 0) := (others => '0');
BEGIN
neg <= (dataa_ipd(dataa_width - 1) AND signa) XOR (datab_ipd(datab_width - 1) AND signb) ;
abs_a <= (NOT dataa_ipd(dataa_width - 1 DOWNTO 0) + 1) WHEN (signa AND dataa_ipd(dataa_width - 1)) = '1' ELSE dataa_ipd(dataa_width - 1 DOWNTO 0) ;
abs_b <= (NOT datab_ipd(datab_width - 1 DOWNTO 0) + 1) WHEN (signb AND datab_ipd(datab_width - 1)) = '1' ELSE datab_ipd(datab_width - 1 DOWNTO 0) ;
abs_output((dataa_width + datab_width) - 1 DOWNTO 0) <= abs_a(dataa_width-1 downto 0) * abs_b(datab_width-1 downto 0) ;
dataout_pre_bypass((dataa_width + datab_width) - 1 DOWNTO 0) <= (NOT abs_output + 1) WHEN neg = '1' ELSE abs_output ;
dataout_tmp((dataa_width + datab_width) - 1 DOWNTO 0) <= datab(datab_width-1 downto 0) & dataa(dataa_width-1 downto 0) when ((dynamic_mode = "yes") and (bypass = '1')) else dataa(dataa_width-1 downto 0) & datab(datab_width-1 downto 0) WHEN (bypass = '1') ELSE dataout_pre_bypass ;
PathDelay : block
begin
g1 : for i in 0 to 256 generate
do: if i < dataout_width generate
process(dataout_tmp(i))
VARIABLE dataout_VitalGlitchData : VitalGlitchDataType;
begin
VitalPathDelay01 (
OutSignal => dataout(i),
OutSignalName => "dataout",
OutTemp => dataout_tmp(i),
Paths => (0 => (dataa_ipd'last_event, tpd_dataa_dataout, TRUE),
1 => (datab_ipd'last_event, tpd_datab_dataout, TRUE),
2 => (signa'last_event, tpd_signa_dataout, TRUE),
3 => (signb'last_event, tpd_signb_dataout, TRUE)),
GlitchData => dataout_VitalGlitchData,
Mode => DefGlitchMode,
MsgOn => FALSE,
XOn => TRUE
);
end process;
end generate do;
sa: if i < dataa_width generate
VitalWireDelay (dataa_ipd(i), dataa(i), tipd_dataa(i));
PROCESS(dataa_ipd)
variable scanouta_VitalGlitchData : VitalGlitchDataType;
BEGIN
VitalPathDelay01 (
OutSignal => scanouta(i),
OutSignalName => "scanouta",
OutTemp => dataa_ipd(i),
Paths => (1 => (dataa_ipd'last_event, tpd_dataa_scanouta, TRUE)),
GlitchData => scanouta_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn
);
end process;
end generate;
sb: if i < datab_width generate
VitalWireDelay (datab_ipd(i), datab(i), tipd_datab(i));
PROCESS(datab_ipd)
variable scanoutb_VitalGlitchData : VitalGlitchDataType;
BEGIN
VitalPathDelay01 (
OutSignal => scanoutb(i),
OutSignalName => "scanoutb",
OutTemp => datab_ipd(i),
Paths => (1 => (datab_ipd'last_event, tpd_datab_scanoutb, TRUE)),
GlitchData => scanoutb_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn
);
end process;
end generate;
end generate;
end block;
END arch;
--/////////////////////////////////////////////////////////////////////////////
--
-- STRATIXII_MAC_MULT
--
--/////////////////////////////////////////////////////////////////////////////
LIBRARY IEEE;
USE ieee.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.stratixii_atom_pack.all;
use work.stratixii_mac_mult_internal;
use work.stratixii_mac_bit_register;
use work.stratixii_mac_register;
use work.stratixii_mac_rs_block;
library grlib;
use grlib.stdlib.all;
ENTITY stratixii_mac_mult IS
GENERIC (
dataa_width : integer := 18;
datab_width : integer := 18;
dataa_clock : string := "none";
datab_clock : string := "none";
signa_clock : string := "none";
signb_clock : string := "none";
round_clock : string := "none";
saturate_clock : string := "none";
output_clock : string := "none";
round_clear : string := "none";
saturate_clear : string := "none";
dataa_clear : string := "none";
datab_clear : string := "none";
signa_clear : string := "none";
signb_clear : string := "none";
output_clear : string := "none";
bypass_multiplier : string := "no";
mode_clock : string := "none";
zeroacc_clock : string := "none";
mode_clear : string := "none";
zeroacc_clear : string := "none";
signa_internally_grounded : string := "false";
signb_internally_grounded : string := "false";
lpm_hint : string := "true";
lpm_type : string := "stratixii_mac_mult";
dynamic_mode : string := "no");
PORT (
dataa : IN std_logic_vector(dataa_width-1 DOWNTO 0) := (others => '0');
datab : IN std_logic_vector(datab_width-1 DOWNTO 0) := (others => '0');
scanina : IN std_logic_vector(dataa_width-1 DOWNTO 0) := (others => '0');
scaninb : IN std_logic_vector(datab_width-1 DOWNTO 0) := (others => '0');
sourcea : IN std_logic := '0';
sourceb : IN std_logic := '0';
signa : IN std_logic := '0';
signb : IN std_logic := '0';
round : IN std_logic := '0';
saturate : IN std_logic := '0';
clk : IN std_logic_vector(3 DOWNTO 0) := (others => '0');
aclr : IN std_logic_vector(3 DOWNTO 0) := (others => '0');
ena : IN std_logic_vector(3 DOWNTO 0) := (others => '0');
mode : IN std_logic := '0';
zeroacc : IN std_logic := '0';
dataout : OUT std_logic_vector((dataa_width+datab_width)-1 DOWNTO 0) := (others => '0');
scanouta : OUT std_logic_vector(dataa_width-1 DOWNTO 0) := (others => '0');
scanoutb : OUT std_logic_vector(datab_width-1 DOWNTO 0) := (others => '0');
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1'
);
END stratixii_mac_mult;
ARCHITECTURE arch OF stratixii_mac_mult IS
COMPONENT stratixii_mac_mult_internal
GENERIC (
dataout_width : integer := 36;
dataa_width : integer := 18;
datab_width : integer := 18;
dynamic_mode : string := "no";
tipd_dataa : VitalDelayArrayType01(17 downto 0) := (OTHERS => DefPropDelay01);
tipd_datab : VitalDelayArrayType01(17 downto 0) := (OTHERS => DefPropDelay01);
tpd_dataa_dataout : VitalDelayType01 := DefPropDelay01;
tpd_datab_dataout : VitalDelayType01 := DefPropDelay01;
tpd_signa_dataout : VitalDelayType01 := DefPropDelay01;
tpd_signb_dataout : VitalDelayType01 := DefPropDelay01;
tpd_dataa_scanouta : VitalDelayType01 := DefPropDelay01;
tpd_datab_scanoutb : VitalDelayType01 := DefPropDelay01;
XOn : Boolean := DefGlitchXOn;
MsgOn : Boolean := DefGlitchMsgOn
);
PORT (
dataa : IN std_logic_vector(dataa_width-1 DOWNTO 0) := (others => '0');
datab : IN std_logic_vector(datab_width-1 DOWNTO 0) := (others => '0');
signa : IN std_logic := '0';
signb : IN std_logic := '0';
bypass : IN std_logic := '0';
scanouta : OUT std_logic_vector(dataa_width-1 DOWNTO 0) := (others => '0');
scanoutb : OUT std_logic_vector(datab_width-1 DOWNTO 0) := (others => '0');
dataout : OUT std_logic_vector(35 DOWNTO 0));
END COMPONENT;
COMPONENT stratixii_mac_bit_register
GENERIC (
power_up : std_logic := '0');
PORT (
data : IN std_logic := '0';
clk : IN std_logic := '0';
aclr : IN std_logic := '0';
if_aclr : IN std_logic := '0';
ena : IN std_logic := '1';
async : IN std_logic := '1';
dataout : OUT std_logic := '0');
END COMPONENT;
COMPONENT stratixii_mac_register
GENERIC (
power_up : std_logic := '0';
data_width : integer := 18);
PORT (
data : IN std_logic_vector(data_width -1 DOWNTO 0) := (others => '0');
clk : IN std_logic := '0';
aclr : IN std_logic := '0';
if_aclr : IN std_logic := '0';
ena : IN std_logic := '1';
async : IN std_logic := '1';
dataout : OUT std_logic_vector(data_width -1 DOWNTO 0) := (others => '0'));
END COMPONENT;
COMPONENT stratixii_mac_rs_block
GENERIC (
tpd_saturate_dataout : VitalDelayType01 := DefPropDelay01;
tpd_round_dataout : VitalDelayType01 := DefPropDelay01;
block_type : string := "mac_mult";
dataa_width : integer := 18;
datab_width : integer := 18);
PORT (
operation : IN std_logic_vector(3 DOWNTO 0) := (others => '0');
round : IN std_logic := '0';
saturate : IN std_logic := '0';
addnsub : IN std_logic := '0';
signa : IN std_logic := '0';
signb : IN std_logic := '0';
signsize : IN std_logic_vector(7 DOWNTO 0) := (others => '0');
roundsize : IN std_logic_vector(7 DOWNTO 0) := (others => '0');
dataoutsize : IN std_logic_vector(7 DOWNTO 0) := (others => '0');
dataa : IN std_logic_vector(dataa_width-1 DOWNTO 0) := (others => '0');
datab : IN std_logic_vector(datab_width-1 DOWNTO 0) := (others => '0');
datain : IN std_logic_vector(71 DOWNTO 0) := (others => '0');
dataout : OUT std_logic_vector(71 DOWNTO 0) := (others => '0'));
END COMPONENT;
SIGNAL mult_output : std_logic_vector(35 DOWNTO 0) := (others => '0');
SIGNAL signa_out : std_logic := '0';
SIGNAL signb_out : std_logic := '0';
SIGNAL round_out : std_logic := '0';
SIGNAL saturate_out : std_logic := '0';
SIGNAL mode_out : std_logic := '0';
SIGNAL zeroacc_out : std_logic := '0';
SIGNAL dataout_tmp : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL dataout_reg : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL dataout_rs : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL scanouta_tmp : std_logic_vector(dataa_width -1 DOWNTO 0) := (others => '0');
SIGNAL scanoutb_tmp : std_logic_vector(datab_width -1 DOWNTO 0) := (others => '0');
SIGNAL dataa_src : std_logic_vector(dataa_width -1 DOWNTO 0) := (others => '0');
SIGNAL datab_src : std_logic_vector(datab_width -1 DOWNTO 0) := (others => '0');
SIGNAL dataa_clk : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL datab_clk : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL signa_clk : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL signb_clk : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL round_clk : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL saturate_clk : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL output_clk : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL round_aclr : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL saturate_aclr : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL dataa_aclr : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL datab_aclr : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL signa_aclr : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL signb_aclr : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL output_aclr : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL mode_clk : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL zeroacc_clk : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL mode_aclr : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL zeroacc_aclr : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL clk_dataa : std_logic := '0';
SIGNAL clear_dataa : std_logic := '0';
SIGNAL aclr_dataa : std_logic := '0';
SIGNAL ena_dataa : std_logic := '0';
SIGNAL async_dataa : std_logic := '0';
SIGNAL clk_datab : std_logic := '0';
SIGNAL clear_datab : std_logic := '0';
SIGNAL aclr_datab : std_logic := '0';
SIGNAL ena_datab : std_logic := '0';
SIGNAL async_datab : std_logic := '0';
SIGNAL clk_signa : std_logic := '0';
SIGNAL clear_signa : std_logic := '0';
SIGNAL aclr_signa : std_logic := '0';
SIGNAL ena_signa : std_logic := '0';
SIGNAL async_signa : std_logic := '0';
SIGNAL clk_signb : std_logic := '0';
SIGNAL clear_signb : std_logic := '0';
SIGNAL aclr_signb : std_logic := '0';
SIGNAL ena_signb : std_logic := '0';
SIGNAL async_signb : std_logic := '0';
SIGNAL clk_round : std_logic := '0';
SIGNAL clear_round : std_logic := '0';
SIGNAL aclr_round : std_logic := '0';
SIGNAL ena_round : std_logic := '0';
SIGNAL async_round : std_logic := '0';
SIGNAL clk_saturate : std_logic := '0';
SIGNAL clear_saturate : std_logic := '0';
SIGNAL aclr_saturate : std_logic := '0';
SIGNAL ena_saturate : std_logic := '0';
SIGNAL async_saturate : std_logic := '0';
SIGNAL clk_mode : std_logic := '0';
SIGNAL clear_mode : std_logic := '0';
SIGNAL aclr_mode : std_logic := '0';
SIGNAL ena_mode : std_logic := '0';
SIGNAL async_mode : std_logic := '0';
SIGNAL clk_zeroacc : std_logic := '0';
SIGNAL clear_zeroacc : std_logic := '0';
SIGNAL aclr_zeroacc : std_logic := '0';
SIGNAL ena_zeroacc : std_logic := '0';
SIGNAL async_zeroacc : std_logic := '0';
SIGNAL clk_output : std_logic := '0';
SIGNAL clear_output : std_logic := '0';
SIGNAL aclr_output : std_logic := '0';
SIGNAL ena_output : std_logic := '0';
SIGNAL async_output : std_logic := '0';
SIGNAL signa_internal : std_logic := '0';
SIGNAL signb_internal : std_logic := '0';
SIGNAL bypass : std_logic := '0';
SIGNAL mac_mult_dataoutsize : std_logic_vector(7 DOWNTO 0) := (others => '0');
SIGNAL tmp_4 : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL tmp_60 : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL port_tmp62 : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL port_tmp63 : std_logic := '0';
SIGNAL port_tmp64 : std_logic_vector(7 DOWNTO 0) := (others => '0');
SIGNAL port_tmp65 : std_logic_vector(7 DOWNTO 0) := (others => '0');
SIGNAL dataout_tmp1 : std_logic_vector(35 DOWNTO 0) := (others => '0');
SIGNAL scanouta_tmp2 : std_logic_vector(dataa_width-1 DOWNTO 0) := (others => '0');
SIGNAL scanoutb_tmp3 : std_logic_vector(datab_width-1 DOWNTO 0) := (others => '0');
BEGIN
dataout <= dataout_tmp1(dataout'range);
scanouta <= scanouta_tmp2;
scanoutb <= scanoutb_tmp3;
dataout_tmp1 <= dataout_tmp(35 DOWNTO 0) ;
dataa_src <= scanina WHEN (sourcea = '1') ELSE dataa ;
datab_src <= scaninb WHEN (sourceb = '1') ELSE datab ;
dataa_mac_reg : stratixii_mac_register
GENERIC MAP (
data_width => dataa_width,
power_up => '0')
PORT MAP (
data => dataa_src,
clk => clk_dataa,
aclr => aclr_dataa,
if_aclr => clear_dataa,
ena => ena_dataa,
dataout => scanouta_tmp,
async => async_dataa);
async_dataa <= '1' WHEN (dataa_clock = "none") ELSE '0' ;
clear_dataa <= '1' WHEN (dataa_clear /= "none") ELSE '0' ;
clk_dataa <= '1' WHEN clk(conv_integer(dataa_clk)) = '1' ELSE '0' ;
aclr_dataa <= '1' WHEN (aclr(conv_integer(dataa_aclr)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0' ;
ena_dataa <= '1' WHEN ena(conv_integer(dataa_clk)) = '1' ELSE '0' ;
dataa_clk <= "0000" WHEN ((dataa_clock = "0") OR (dataa_clock = "none")) ELSE "0001" WHEN (dataa_clock = "1") ELSE "0010" WHEN (dataa_clock = "2") ELSE "0011" WHEN (dataa_clock = "3") ELSE "0000" ;
dataa_aclr <= "0000" WHEN ((dataa_clear = "0") OR (dataa_clear = "none")) ELSE "0001" WHEN (dataa_clear = "1") ELSE "0010" WHEN (dataa_clear = "2") ELSE "0011" WHEN (dataa_clear = "3") ELSE "0000" ;
datab_mac_reg : stratixii_mac_register
GENERIC MAP (
data_width => datab_width,
power_up => '0')
PORT MAP (
data => datab_src,
clk => clk_datab,
aclr => aclr_datab,
if_aclr => clear_datab,
ena => ena_datab,
dataout => scanoutb_tmp,
async => async_datab);
async_datab <= '1' WHEN (datab_clock = "none") ELSE '0' ;
clear_datab <= '1' WHEN (datab_clear /= "none") ELSE '0' ;
clk_datab <= '1' WHEN clk(conv_integer(datab_clk)) = '1' ELSE '0' ;
aclr_datab <= '1' WHEN (aclr(conv_integer(datab_aclr)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0' ;
ena_datab <= '1' WHEN ena(conv_integer(datab_clk)) = '1' ELSE '0' ;
datab_clk <= "0000" WHEN ((datab_clock = "0") OR (datab_clock = "none")) ELSE "0001" WHEN (datab_clock = "1") ELSE "0010" WHEN (datab_clock = "2") ELSE "0011" WHEN (datab_clock = "3") ELSE "0000" ;
datab_aclr <= "0000" WHEN ((datab_clear = "0") OR (datab_clear = "none")) ELSE "0001" WHEN (datab_clear = "1") ELSE "0010" WHEN (datab_clear = "2") ELSE "0011" WHEN (datab_clear = "3") ELSE "0000" ;
signa_mac_reg : stratixii_mac_bit_register
GENERIC MAP (
power_up => '0')
PORT MAP (
data => signa,
clk => clk_signa,
aclr => aclr_signa,
if_aclr => clear_signa,
ena => ena_signa,
dataout => signa_out,
async => async_signa);
async_signa <= '1' WHEN (signa_clock = "none") ELSE '0' ;
clear_signa <= '1' WHEN (signa_clear /= "none") ELSE '0' ;
clk_signa <= '1' WHEN clk(conv_integer(signa_clk)) = '1' ELSE '0' ;
aclr_signa <= '1' WHEN (aclr(conv_integer(signa_aclr)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0' ;
ena_signa <= '1' WHEN ena(conv_integer(signa_clk)) = '1' ELSE '0' ;
signa_clk <= "0000" WHEN ((signa_clock = "0") OR (signa_clock = "none")) ELSE "0001" WHEN (signa_clock = "1") ELSE "0010" WHEN (signa_clock = "2") ELSE "0011" WHEN (signa_clock = "3") ELSE "0000" ;
signa_aclr <= "0000" WHEN ((signa_clear = "0") OR (signa_clear = "none")) ELSE "0001" WHEN (signa_clear = "1") ELSE "0010" WHEN (signa_clear = "2") ELSE "0011" WHEN (signa_clear = "3") ELSE "0000" ;
signb_mac_reg : stratixii_mac_bit_register
GENERIC MAP (
power_up => '0')
PORT MAP (
data => signb,
clk => clk_signb,
aclr => aclr_signb,
if_aclr => clear_signb,
ena => ena_signb,
dataout => signb_out,
async => async_signb);
async_signb <= '1' WHEN (signb_clock = "none") ELSE '0' ;
clear_signb <= '1' WHEN (signb_clear /= "none") ELSE '0' ;
clk_signb <= '1' WHEN clk(conv_integer(signb_clk)) = '1' ELSE '0' ;
aclr_signb <= '1' WHEN (aclr(conv_integer(signb_aclr)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0' ;
ena_signb <= '1' WHEN ena(conv_integer(signb_clk)) = '1' ELSE '0' ;
signb_clk <= "0000" WHEN ((signb_clock = "0") OR (signb_clock = "none")) ELSE "0001" WHEN (signb_clock = "1") ELSE "0010" WHEN (signb_clock = "2") ELSE "0011" WHEN (signb_clock = "3") ELSE "0000" ;
signb_aclr <= "0000" WHEN ((signb_clear = "0") OR (signb_clear = "none")) ELSE "0001" WHEN (signb_clear = "1") ELSE "0010" WHEN (signb_clear = "2") ELSE "0011" WHEN (signb_clear = "3") ELSE "0000" ;
round_mac_reg : stratixii_mac_bit_register
GENERIC MAP (
power_up => '0')
PORT MAP (
data => round,
clk => clk_round,
aclr => aclr_round,
if_aclr => clear_round,
ena => ena_round,
dataout => round_out,
async => async_round);
async_round <= '1' WHEN (round_clock = "none") ELSE '0' ;
clear_round <= '1' WHEN (round_clear /= "none") ELSE '0' ;
clk_round <= '1' WHEN clk(conv_integer(round_clk)) = '1' ELSE '0' ;
aclr_round <= '1' WHEN (aclr(conv_integer(round_aclr)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0' ;
ena_round <= '1' WHEN ena(conv_integer(round_clk)) = '1' ELSE '0' ;
round_clk <= "0000" WHEN ((round_clock = "0") OR (round_clock = "none")) ELSE "0001" WHEN (round_clock = "1") ELSE "0010" WHEN (round_clock = "2") ELSE "0011" WHEN (round_clock = "3") ELSE "0000" ;
round_aclr <= "0000" WHEN ((round_clear = "0") OR (round_clear = "none")) ELSE "0001" WHEN (round_clear = "1") ELSE "0010" WHEN (round_clear = "2") ELSE "0011" WHEN (round_clear = "3") ELSE "0000" ;
saturate_mac_reg : stratixii_mac_bit_register
GENERIC MAP (
power_up => '0')
PORT MAP (
data => saturate,
clk => clk_saturate,
aclr => aclr_saturate,
if_aclr => clear_saturate,
ena => ena_saturate,
dataout => saturate_out,
async => async_saturate);
async_saturate <= '1' WHEN (saturate_clock = "none") ELSE '0' ;
clear_saturate <= '1' WHEN (saturate_clear /= "none") ELSE '0' ;
clk_saturate <= '1' WHEN clk(conv_integer(saturate_clk)) = '1' ELSE '0' ;
aclr_saturate <= '1' WHEN (aclr(conv_integer(saturate_aclr)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0' ;
ena_saturate <= '1' WHEN ena(conv_integer(saturate_clk)) = '1' ELSE '0' ;
saturate_clk <= "0000" WHEN ((saturate_clock = "0") OR (saturate_clock = "none")) ELSE "0001" WHEN (saturate_clock = "1") ELSE "0010" WHEN (saturate_clock = "2") ELSE "0011" WHEN (saturate_clock = "3") ELSE "0000" ;
saturate_aclr <= "0000" WHEN ((saturate_clear = "0") OR (saturate_clear = "none")) ELSE "0001" WHEN (saturate_clear = "1") ELSE "0010" WHEN (saturate_clear = "2") ELSE "0011" WHEN (saturate_clear = "3") ELSE "0000" ;
mode_mac_reg : stratixii_mac_bit_register
GENERIC MAP (
power_up => '0')
PORT MAP (
data => mode,
clk => clk_mode,
aclr => aclr_mode,
if_aclr => clear_mode,
ena => ena_mode,
dataout => mode_out,
async => async_mode);
async_mode <= '1' WHEN (mode_clock = "none") ELSE '0' ;
clear_mode <= '1' WHEN (mode_clear /= "none") ELSE '0' ;
clk_mode <= '1' WHEN clk(conv_integer(mode_clk)) = '1' ELSE '0' ;
aclr_mode <= '1' WHEN (aclr(conv_integer(mode_aclr)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0' ;
ena_mode <= '1' WHEN ena(conv_integer(mode_clk)) = '1' ELSE '0' ;
mode_clk <= "0000" WHEN ((mode_clock = "0") OR (mode_clock = "none")) ELSE "0001" WHEN (mode_clock = "1") ELSE "0010" WHEN (mode_clock = "2") ELSE "0011" WHEN (mode_clock = "3") ELSE "0000" ;
mode_aclr <= "0000" WHEN ((mode_clear = "0") OR (mode_clear = "none")) ELSE "0001" WHEN (mode_clear = "1") ELSE "0010" WHEN (mode_clear = "2") ELSE "0011" WHEN (mode_clear = "3") ELSE "0000" ;
zeroacc_mac_reg : stratixii_mac_bit_register
GENERIC MAP (
power_up => '0')
PORT MAP (
data => zeroacc,
clk => clk_zeroacc,
aclr => aclr_zeroacc,
if_aclr => clear_zeroacc,
ena => ena_zeroacc,
dataout => zeroacc_out,
async => async_zeroacc);
async_zeroacc <= '1' WHEN (zeroacc_clock = "none") ELSE '0' ;
clear_zeroacc <= '1' WHEN (zeroacc_clear /= "none") ELSE '0' ;
clk_zeroacc <= '1' WHEN clk(conv_integer(zeroacc_clk)) = '1' ELSE '0' ;
aclr_zeroacc <= '1' WHEN (aclr(conv_integer(zeroacc_aclr)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0' ;
ena_zeroacc <= '1' WHEN ena(conv_integer(zeroacc_clk)) = '1' ELSE '0' ;
zeroacc_clk <= "0000" WHEN ((zeroacc_clock = "0") OR (zeroacc_clock = "none")) ELSE "0001" WHEN (zeroacc_clock = "1") ELSE "0010" WHEN (zeroacc_clock = "2") ELSE "0011" WHEN (zeroacc_clock = "3") ELSE "0000" ;
zeroacc_aclr <= "0000" WHEN ((zeroacc_clear = "0") OR (zeroacc_clear = "none")) ELSE "0001" WHEN (zeroacc_clear = "1") ELSE "0010" WHEN (zeroacc_clear = "2") ELSE "0011" WHEN (zeroacc_clear = "3") ELSE "0000" ;
mac_multiply : stratixii_mac_mult_internal
GENERIC MAP (
dataa_width => dataa_width,
datab_width => datab_width,
dataout_width => dataa_width + datab_width,
dynamic_mode => dynamic_mode)
PORT MAP (
dataa => scanouta_tmp,
datab => scanoutb_tmp,
signa => signa_internal,
signb => signb_internal,
bypass => bypass,
scanouta => scanouta_tmp2,
scanoutb => scanoutb_tmp3,
dataout => mult_output);
signa_internal <= '0' WHEN ((signa_internally_grounded = "true") AND (dynamic_mode = "no")) OR ((((signa_internally_grounded = "true") AND (dynamic_mode = "yes")) AND (zeroacc_out = '1')) AND (mode_out = '0')) ELSE signa_out ;
signb_internal <= '0' WHEN ((signb_internally_grounded = "true") AND (dynamic_mode = "no")) OR ((((signb_internally_grounded = "true") AND (dynamic_mode = "yes")) AND (zeroacc_out = '1')) AND (mode_out = '0')) ELSE signb_out ;
bypass <= '1' WHEN ((bypass_multiplier = "yes") AND (dynamic_mode = "no")) OR (((bypass_multiplier = "yes") AND (mode_out = '1')) AND (dynamic_mode = "yes")) ELSE '0' ;
tmp_60 <= '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & mult_output(35 DOWNTO 0);
port_tmp62 <= "1111";
port_tmp63 <= '0';
port_tmp64 <= "00000010";
port_tmp65 <= "00001111";
mac_rs_block : stratixii_mac_rs_block
GENERIC MAP (
block_type => "mac_mult",
dataa_width => dataa_width,
datab_width => datab_width)
PORT MAP (
operation => port_tmp62,
round => round_out,
saturate => saturate_out,
addnsub => port_tmp63,
signa => signa_out,
signb => signb_out,
signsize => port_tmp64,
roundsize => port_tmp65,
dataoutsize => mac_mult_dataoutsize,
dataa => scanouta_tmp,
datab => scanoutb_tmp,
datain => tmp_60,
dataout => dataout_rs);
mac_mult_dataoutsize <= CONV_STD_LOGIC_VECTOR(dataa_width + datab_width, 8) ;
dataout_reg <= tmp_60 when bypass = '1' else dataout_rs;
dataout_mac_reg : stratixii_mac_register
GENERIC MAP (
data_width => dataa_width + datab_width,
power_up => '0')
PORT MAP (
data => dataout_reg((dataa_width + datab_width) -1 downto 0),
clk => clk_output,
aclr => aclr_output,
if_aclr => clear_output,
ena => ena_output,
dataout => dataout_tmp((dataa_width + datab_width) -1 downto 0),
async => async_output);
async_output <= '1' WHEN (output_clock = "none") ELSE '0' ;
clear_output <= '1' WHEN (output_clear /= "none") ELSE '0' ;
clk_output <= '1' WHEN clk(conv_integer(output_clk)) = '1' ELSE '0' ;
aclr_output <= '1' WHEN (aclr(conv_integer(output_aclr)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0' ;
ena_output <= '1' WHEN ena(conv_integer(output_clk)) = '1' ELSE '0' ;
output_clk <= "0000" WHEN ((output_clock = "0") OR (output_clock = "none")) ELSE "0001" WHEN (output_clock = "1") ELSE "0010" WHEN (output_clock = "2") ELSE "0011" WHEN (output_clock = "3") ELSE "0000" ;
output_aclr <= "0000" WHEN ((output_clear = "0") OR (output_clear = "none")) ELSE "0001" WHEN (output_clear = "1") ELSE "0010" WHEN (output_clear = "2") ELSE "0011" WHEN (output_clear = "3") ELSE "0000" ;
END arch;
--/////////////////////////////////////////////////////////////////////////////
--
-- STRATIXII_MAC_DYNAMIC_MUX
--
--/////////////////////////////////////////////////////////////////////////////
LIBRARY IEEE;
USE ieee.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.stratixii_atom_pack.all;
ENTITY stratixii_mac_dynamic_mux IS
PORT (
ab : IN std_logic_vector(71 DOWNTO 0) := (others => '0');
cd : IN std_logic_vector(71 DOWNTO 0) := (others => '0');
sata : IN std_logic := '0';
satb : IN std_logic := '0';
satc : IN std_logic := '0';
satd : IN std_logic := '0';
multsatab : IN std_logic := '0';
multsatcd : IN std_logic := '0';
outsatab : IN std_logic := '0';
outsatcd : IN std_logic := '0';
multabsaturate : IN std_logic := '0';
multcdsaturate : IN std_logic := '0';
saturateab : IN std_logic := '0';
saturatecd : IN std_logic := '0';
overab : IN std_logic := '0';
overcd : IN std_logic := '0';
sum : IN std_logic_vector(71 DOWNTO 0) := (others => '0');
m36 : IN std_logic_vector(71 DOWNTO 0) := (others => '0');
bypass : IN std_logic_vector(143 DOWNTO 0) := (others => '0');
operation : IN std_logic_vector(3 DOWNTO 0) := (others => '0');
dataout : OUT std_logic_vector(143 DOWNTO 0) := (others => '0');
accoverflow : OUT std_logic := '0');
END stratixii_mac_dynamic_mux;
ARCHITECTURE arch OF stratixii_mac_dynamic_mux IS
SIGNAL dataout_tmp : std_logic_vector(143 DOWNTO 0) := (others => '0');
SIGNAL accoverflow_tmp : std_logic := '0';
SIGNAL dataout_tmp1 : std_logic_vector(143 DOWNTO 0) := (others => '0');
SIGNAL accoverflow_tmp2 : std_logic := '0';
BEGIN
dataout <= dataout_tmp1;
accoverflow <= accoverflow_tmp2;
PROCESS (ab, cd, sata, satb, satc, satd, multsatab, multsatcd, outsatab, outsatcd, multabsaturate, multcdsaturate, saturateab, saturatecd, overab, overcd, sum, m36, bypass, operation)
VARIABLE dataout_tmp_tmp3 : std_logic_vector(143 DOWNTO 0) := (others => '0');
VARIABLE accoverflow_tmp_tmp4 : std_logic := '0';
VARIABLE temp_tmp5 : std_logic_vector(1 DOWNTO 0) := (others => '0');
VARIABLE temp_tmp6 : std_logic_vector(1 DOWNTO 0) := (others => '0');
VARIABLE temp_tmp7 : std_logic_vector(3 DOWNTO 0) := (others => '0');
VARIABLE temp_tmp8 : std_logic_vector(1 DOWNTO 0) := (others => '0');
VARIABLE temp_tmp9 : std_logic_vector(1 DOWNTO 0) := (others => '0');
BEGIN
CASE operation IS
WHEN "0000" =>
dataout_tmp_tmp3 := bypass;
accoverflow_tmp_tmp4 := '0';
WHEN "0100" =>
temp_tmp5 := saturateab & multabsaturate;
CASE temp_tmp5 IS
WHEN "00" =>
dataout_tmp_tmp3 := bypass(143 DOWNTO 72) & ab(71 DOWNTO 53) & overab & ab(51 DOWNTO 36) & ab(35 DOWNTO 0);
WHEN "01" =>
dataout_tmp_tmp3 := bypass(143 DOWNTO 72) & ab(71 DOWNTO 53) & overab & ab(51 DOWNTO 36) & ab(35 DOWNTO 2) & multsatab & ab(0);
WHEN "10" =>
dataout_tmp_tmp3 := bypass(143 DOWNTO 72) & ab(71 DOWNTO 53) & overab & ab(51 DOWNTO 36) & ab(35 DOWNTO 3) & outsatab & ab(1 DOWNTO 0);
WHEN "11" =>
dataout_tmp_tmp3 := bypass(143 DOWNTO 72) & ab(71 DOWNTO 53) & overab & ab(51 DOWNTO 36) & ab(35 DOWNTO 3) & outsatab & multsatab & ab(0);
WHEN OTHERS =>
dataout_tmp_tmp3 := bypass(143 DOWNTO 72) & ab(71 DOWNTO 53) & overab & ab(51 DOWNTO 36) & ab(35 DOWNTO 0);
END CASE;
accoverflow_tmp_tmp4 := overab;
WHEN "0001" =>
IF (multabsaturate = '1') THEN
dataout_tmp_tmp3 := bypass(143 DOWNTO 72) & ab(71 DOWNTO 2) & satb & sata;
ELSE
dataout_tmp_tmp3 := bypass(143 DOWNTO 72) & ab(71 DOWNTO 0);
END IF;
accoverflow_tmp_tmp4 := '0';
WHEN "0010" =>
temp_tmp6 := multsatcd & multsatab;
CASE temp_tmp6 IS
WHEN "00" =>
dataout_tmp_tmp3 := bypass(143 DOWNTO 72) & sum(71 DOWNTO 0);
accoverflow_tmp_tmp4 := '0';
WHEN "01" =>
dataout_tmp_tmp3 := bypass(143 DOWNTO 72) & sum(71 DOWNTO 2) & satb & sata;
accoverflow_tmp_tmp4 := '0';
WHEN "10" =>
dataout_tmp_tmp3 := bypass(143 DOWNTO 72) & sum(71 DOWNTO 3) & satc & sum(1 DOWNTO 0);
accoverflow_tmp_tmp4 := satd;
WHEN "11" =>
dataout_tmp_tmp3 := bypass(143 DOWNTO 72) & sum(71 DOWNTO 3) & satc & satb & sata;
accoverflow_tmp_tmp4 := satd;
WHEN OTHERS =>
dataout_tmp_tmp3 := bypass(143 DOWNTO 72) & sum(71 DOWNTO 0);
accoverflow_tmp_tmp4 := '0';
END CASE;
WHEN "0111" =>
dataout_tmp_tmp3 := bypass(143 DOWNTO 72) & m36;
accoverflow_tmp_tmp4 := '0';
WHEN "1100" =>
temp_tmp7 := saturatecd & saturateab & multsatcd & multsatab;
CASE temp_tmp7 IS
WHEN "0000" =>
dataout_tmp_tmp3 := cd(71 DOWNTO 53) & overcd & cd(51 DOWNTO 0) & ab(71 DOWNTO 53) & overab & ab(51 DOWNTO 0);
WHEN "0001" =>
dataout_tmp_tmp3 := cd(71 DOWNTO 53) & overcd & cd(51 DOWNTO 0) & ab(71 DOWNTO 53) & overab & ab(51 DOWNTO 2) & multsatab & ab(0);
WHEN "0010" =>
dataout_tmp_tmp3 := cd(71 DOWNTO 53) & overcd & cd(51 DOWNTO 2) & multsatcd & cd(0) & ab(71 DOWNTO 53) & overab & ab(51 DOWNTO 0);
WHEN "0011" =>
dataout_tmp_tmp3 := cd(71 DOWNTO 53) & overcd & cd(51 DOWNTO 2) & multsatcd & cd(0) & ab(71 DOWNTO 53) & overab & ab(51 DOWNTO 2) & multsatab & ab(0);
WHEN "0100" =>
dataout_tmp_tmp3 := cd(71 DOWNTO 53) & overcd & cd(51 DOWNTO 0) & ab(71 DOWNTO 53) & overab & ab(51 DOWNTO 3) & outsatab & ab(1 DOWNTO 0);
WHEN "0101" =>
dataout_tmp_tmp3 := cd(71 DOWNTO 53) & overcd & cd(51 DOWNTO 0) & ab(71 DOWNTO 53) & overab & ab(51 DOWNTO 3) & outsatab & multsatab & ab(0);
WHEN "0110" =>
dataout_tmp_tmp3 := cd(71 DOWNTO 53) & overcd & cd(51 DOWNTO 2) & multsatcd & cd(0) & ab(71 DOWNTO 53) & overab & ab(51 DOWNTO 3) & outsatab & ab(1 DOWNTO 0);
WHEN "0111" =>
dataout_tmp_tmp3 := cd(71 DOWNTO 53) & overcd & cd(51 DOWNTO 2) & multsatcd & cd(0) & ab(71 DOWNTO 53) & overab & ab(51 DOWNTO 3) & outsatab & multsatab & ab(0);
WHEN "1000" =>
dataout_tmp_tmp3 := cd(71 DOWNTO 53) & overcd & cd(51 DOWNTO 3) & outsatcd & cd(1 DOWNTO 0) & ab(71 DOWNTO 53) & overab & ab(51 DOWNTO 0);
WHEN "1001" =>
dataout_tmp_tmp3 := cd(71 DOWNTO 53) & overcd & cd(51 DOWNTO 3) & outsatcd & cd(1 DOWNTO 0) & ab(71 DOWNTO 53) & overab & ab(51 DOWNTO 2) & multsatab & ab(0);
WHEN "1010" =>
dataout_tmp_tmp3 := cd(71 DOWNTO 53) & overcd & cd(51 DOWNTO 3) & outsatcd & multsatcd & cd(0) & ab(71 DOWNTO 53) & overab & ab(51 DOWNTO 0);
WHEN "1011" =>
dataout_tmp_tmp3 := cd(71 DOWNTO 53) & overcd & cd(51 DOWNTO 3) & outsatcd & multsatcd & cd(0) & ab(71 DOWNTO 53) & overab & ab(51 DOWNTO 2) & multsatab & ab(0);
WHEN "1100" =>
dataout_tmp_tmp3 := cd(71 DOWNTO 53) & overcd & cd(51 DOWNTO 3) & outsatcd & cd(1 DOWNTO 0) & ab(71 DOWNTO 53) & overab & ab(51 DOWNTO 3) & outsatab & ab(1 DOWNTO 0);
WHEN "1101" =>
dataout_tmp_tmp3 := cd(71 DOWNTO 53) & overcd & cd(51 DOWNTO 3) & outsatcd & cd(1 DOWNTO 0) & ab(71 DOWNTO 53) & overab & ab(51 DOWNTO 3) & outsatab & multsatab & ab(0);
WHEN "1110" =>
dataout_tmp_tmp3 := cd(71 DOWNTO 53) & overcd & cd(51 DOWNTO 3) & outsatcd & multsatcd & cd(0) & ab(71 DOWNTO 53) & overab & ab(51 DOWNTO 3) & outsatab & ab(1 DOWNTO 0);
WHEN "1111" =>
dataout_tmp_tmp3 := cd(71 DOWNTO 53) & overcd & cd(51 DOWNTO 3) & outsatcd & multsatcd & cd(0) & ab(71 DOWNTO 53) & overab & ab(51 DOWNTO 3) & outsatab & multsatab & ab(0);
WHEN OTHERS =>
dataout_tmp_tmp3 := cd(71 DOWNTO 53) & overcd & cd(51 DOWNTO 0) & ab(71 DOWNTO 53) & overab & ab(51 DOWNTO 0);
END CASE;
accoverflow_tmp_tmp4 := overab;
WHEN "1101" =>
temp_tmp8 := saturateab & multabsaturate;
CASE temp_tmp8 IS
WHEN "00" =>
dataout_tmp_tmp3 := bypass(143 DOWNTO 72) & ab(71 DOWNTO 53) & overab & ab(51 DOWNTO 36) & ab(35 DOWNTO 0);
WHEN "01" =>
dataout_tmp_tmp3 := bypass(143 DOWNTO 72) & ab(71 DOWNTO 53) & overab & ab(51 DOWNTO 2) & multsatab & ab(0);
WHEN "10" =>
dataout_tmp_tmp3 := bypass(143 DOWNTO 72) & ab(71 DOWNTO 53) & overab & ab(51 DOWNTO 3) & outsatab & ab(1 DOWNTO 0);
WHEN "11" =>
dataout_tmp_tmp3 := bypass(143 DOWNTO 72) & ab(71 DOWNTO 53) & overab & ab(51 DOWNTO 3) & outsatab & multsatab & ab(0);
WHEN OTHERS =>
dataout_tmp_tmp3 := bypass(143 DOWNTO 72) & ab(71 DOWNTO 53) & overab & ab(51 DOWNTO 36) & ab(35 DOWNTO 0);
END CASE;
accoverflow_tmp_tmp4 := overab;
WHEN "1110" =>
temp_tmp9 := saturatecd & multcdsaturate;
CASE temp_tmp9 IS
WHEN "00" =>
dataout_tmp_tmp3 := cd(71 DOWNTO 53) & overcd & cd(51 DOWNTO 0) & bypass(71 DOWNTO 0);
WHEN "01" =>
dataout_tmp_tmp3 := cd(71 DOWNTO 53) & overcd & cd(51 DOWNTO 2) & multsatcd & cd(0) & bypass(71 DOWNTO 0);
WHEN "10" =>
dataout_tmp_tmp3 := cd(71 DOWNTO 53) & overcd & cd(51 DOWNTO 3) & outsatcd & cd(1 DOWNTO 0) & bypass(71 DOWNTO 0);
WHEN "11" =>
dataout_tmp_tmp3 := cd(71 DOWNTO 53) & overcd & cd(51 DOWNTO 3) & outsatcd & multsatcd & cd(0) & bypass(71 DOWNTO 0);
WHEN OTHERS =>
dataout_tmp_tmp3 := cd(71 DOWNTO 53) & overcd & cd(51 DOWNTO 0) & bypass(71 DOWNTO 0);
END CASE;
accoverflow_tmp_tmp4 := overcd;
WHEN OTHERS =>
dataout_tmp_tmp3 := bypass;
accoverflow_tmp_tmp4 := '0';
END CASE;
dataout_tmp <= dataout_tmp_tmp3;
accoverflow_tmp <= accoverflow_tmp_tmp4;
END PROCESS;
dataout_tmp1 <= dataout_tmp ;
accoverflow_tmp2 <= accoverflow_tmp ;
END arch;
--/////////////////////////////////////////////////////////////////////////////
--
-- STRATIXII_MAC_PIN_MAP
--
--/////////////////////////////////////////////////////////////////////////////
LIBRARY IEEE;
USE ieee.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.stratixii_atom_pack.all;
ENTITY stratixii_mac_pin_map IS
GENERIC (
tipd_addnsub : VitalDelayType01 := DefPropDelay01;
data_width : integer := 144;
tipd_datain : VitalDelayArrayType01(143 downto 0) := (OTHERS => (20 ps,20 ps));
operation_mode : string := "output_only";
pinmap : string := "map");
PORT (
datain : IN std_logic_vector(data_width -1 DOWNTO 0) := (others => '0');
operation : IN std_logic_vector(3 DOWNTO 0) := (others => '0');
addnsub : IN std_logic := '0';
dataout : OUT std_logic_vector(data_width -1 DOWNTO 0) := (others => '0'));
END stratixii_mac_pin_map;
ARCHITECTURE arch OF stratixii_mac_pin_map IS
SIGNAL addnsub_ipd : std_logic := '0';
SIGNAL datain_ipd : std_logic_vector(data_width -1 DOWNTO 0) := (others => '0');
SIGNAL dataout_tmp : std_logic_vector(data_width -1 DOWNTO 0) := (others => '0');
SIGNAL dataout_tmp2 : std_logic_vector(data_width -1 DOWNTO 0) := (others => '0');
BEGIN
WireDelay : block
begin
VitalWireDelay (addnsub_ipd, addnsub, tipd_addnsub);
loopbits : FOR i in datain'RANGE GENERATE
VitalWireDelay (datain_ipd(i), datain(i), tipd_datain(i));
END GENERATE;
end block;
dataout <= dataout_tmp2(dataout'range);
PROCESS (datain_ipd, addnsub_ipd)
VARIABLE dataout_tmp_tmp3 : std_logic_vector(143 DOWNTO 0) := (others => '0');
BEGIN
IF (operation_mode = "dynamic") THEN
IF (pinmap = "map") THEN
CASE operation IS
WHEN "1100" =>
dataout_tmp_tmp3 := "XXXXXXXXXXXXXXXXXXX" & datain_ipd(123 DOWNTO 108) &
'X' & datain_ipd(107 DOWNTO 72) &
"XXXXXXXXXXXXXXXXXXX" & datain_ipd(51 DOWNTO 36) &
'X' & datain_ipd(35 DOWNTO 0);
WHEN "1101" =>
dataout_tmp_tmp3 := datain_ipd(143 DOWNTO 72)& "XXXXXXXXXXXXXXXXXXX" & datain_ipd(51 DOWNTO 36) & 'X' & datain_ipd(35 DOWNTO 0);
WHEN "1110" =>
dataout_tmp_tmp3 := "XXXXXXXXXXXXXXXXXXX" & datain_ipd(123 DOWNTO 108) & 'X' & datain_ipd(107 DOWNTO 0);
WHEN "0111" =>
IF (addnsub_ipd = '1') THEN
dataout_tmp_tmp3(17 DOWNTO 0) := datain_ipd(17 DOWNTO 0);
dataout_tmp_tmp3(35 DOWNTO 18) := datain_ipd(53 DOWNTO 36);
dataout_tmp_tmp3(53 DOWNTO 36) := datain_ipd(35 DOWNTO 18);
dataout_tmp_tmp3(71 DOWNTO 54) := datain_ipd(71 DOWNTO 54);
ELSE
dataout_tmp_tmp3(17 DOWNTO 0) := "XXXXXXXXXXXXXXXXXX";
dataout_tmp_tmp3(35 DOWNTO 18) := "XXXXXXXXXXXXXXXXXX";
dataout_tmp_tmp3(53 DOWNTO 36) := "XXXXXXXXXXXXXXXXXX";
dataout_tmp_tmp3(71 DOWNTO 54) := "XXXXXXXXXXXXXXXXXX";
END IF;
dataout_tmp_tmp3(143 DOWNTO 72) := "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
WHEN OTHERS =>
dataout_tmp_tmp3 := datain_ipd;
END CASE;
ELSE
CASE operation IS
WHEN "1100" =>
dataout_tmp_tmp3(35 DOWNTO 0) := datain_ipd(35 DOWNTO 0);
dataout_tmp_tmp3(70 DOWNTO 36) := datain_ipd(71 DOWNTO 37);
dataout_tmp_tmp3(107 DOWNTO 72) := datain_ipd(107 DOWNTO 72);
dataout_tmp_tmp3(142 DOWNTO 108) := datain_ipd(143 DOWNTO 109);
WHEN "1101" =>
dataout_tmp_tmp3(35 DOWNTO 0) := datain_ipd(35 DOWNTO 0);
dataout_tmp_tmp3(70 DOWNTO 36) := datain_ipd(71 DOWNTO 37);
dataout_tmp_tmp3(143 DOWNTO 72) := datain_ipd(143 DOWNTO 72);
WHEN "1110" =>
dataout_tmp_tmp3(107 DOWNTO 0) := datain_ipd(107 DOWNTO 0);
dataout_tmp_tmp3(107 DOWNTO 72) := datain_ipd(107 DOWNTO 72);
dataout_tmp_tmp3(142 DOWNTO 108) := datain_ipd(143 DOWNTO 109);
WHEN "0111" =>
dataout_tmp_tmp3(17 DOWNTO 0) := datain_ipd(17 DOWNTO 0);
dataout_tmp_tmp3(53 DOWNTO 36) := datain_ipd(35 DOWNTO 18);
dataout_tmp_tmp3(35 DOWNTO 18) := datain_ipd(53 DOWNTO 36);
dataout_tmp_tmp3(71 DOWNTO 54) := datain_ipd(71 DOWNTO 54);
dataout_tmp_tmp3(143 DOWNTO 72) := "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
WHEN OTHERS =>
dataout_tmp_tmp3 := datain_ipd;
END CASE;
END IF;
ELSE
dataout_tmp_tmp3 := datain_ipd;
END IF;
dataout_tmp <= dataout_tmp_tmp3;
END PROCESS;
dataout_tmp2 <= dataout_tmp ;
END arch;
--/////////////////////////////////////////////////////////////////////////////
--
-- Module Name : stratixii_lvds_tx_reg
--
-- Description : Simulation model for a simple DFF.
-- This is used for registering the enable inputs.
-- No timing, powers upto 0.
--
--/////////////////////////////////////////////////////////////////////////////
LIBRARY IEEE, std;
USE ieee.std_logic_1164.all;
USE IEEE.VITAL_Timing.all;
USE IEEE.VITAL_Primitives.all;
USE work.stratixii_atom_pack.all;
ENTITY stratixii_lvds_tx_reg is
GENERIC ( MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
TimingChecksOn : Boolean := True;
InstancePath : String := "*";
tipd_clk : VitalDelayType01 := DefpropDelay01;
tipd_ena : VitalDelayType01 := DefpropDelay01;
tipd_d : VitalDelayType01 := DefpropDelay01;
tsetup_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_clk_q_posedge : VitalDelayType01 := DefPropDelay01
);
PORT ( q : OUT std_logic;
clk : IN std_logic;
ena : IN std_logic;
d : IN std_logic;
clrn : IN std_logic;
prn : IN std_logic
);
attribute VITAL_LEVEL0 of stratixii_lvds_tx_reg : ENTITY is TRUE;
END stratixii_lvds_tx_reg;
ARCHITECTURE vital_stratixii_lvds_tx_reg of stratixii_lvds_tx_reg is
attribute VITAL_LEVEL0 of vital_stratixii_lvds_tx_reg : architecture is TRUE;
-- INTERNAL SIGNALS
signal clk_ipd : std_logic;
signal d_ipd : std_logic;
signal ena_ipd : std_logic;
begin
----------------------
-- INPUT PATH DELAYs
----------------------
WireDelay : block
begin
VitalWireDelay (clk_ipd, clk, tipd_clk);
VitalWireDelay (ena_ipd, ena, tipd_ena);
VitalWireDelay (d_ipd, d, tipd_d);
end block;
process (clk_ipd, clrn, prn)
variable q_tmp : std_logic := '0';
variable q_VitalGlitchData : VitalGlitchDataType;
variable Tviol_d_clk : std_ulogic := '0';
variable TimingData_d_clk : VitalTimingDataType := VitalTimingDataInit;
begin
------------------------
-- Timing Check Section
------------------------
if (TimingChecksOn) then
VitalSetupHoldCheck (
Violation => Tviol_d_clk,
TimingData => TimingData_d_clk,
TestSignal => d_ipd,
TestSignalName => "d",
RefSignal => clk_ipd,
RefSignalName => "clk",
SetupHigh => tsetup_d_clk_noedge_posedge,
SetupLow => tsetup_d_clk_noedge_posedge,
HoldHigh => thold_d_clk_noedge_posedge,
HoldLow => thold_d_clk_noedge_posedge,
CheckEnabled => TO_X01( (NOT ena_ipd) ) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/stratixii_lvds_tx_reg",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
end if;
if (prn = '0') then
q_tmp := '1';
elsif (clrn = '0') then
q_tmp := '0';
elsif (clk_ipd'event and clk_ipd = '1') then
if (ena_ipd = '1') then
q_tmp := d_ipd;
end if;
end if;
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
OutSignal => q,
OutSignalName => "Q",
OutTemp => q_tmp,
Paths => (1 => (clk_ipd'last_event, tpd_clk_q_posedge, TRUE)),
GlitchData => q_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
end vital_stratixii_lvds_tx_reg;
--////////////////////////////////////////////////////////////////////////////
--
-- Entity name : stratixii_lvds_tx_parallel_register
--
-- Description : Register for the 10 data input channels of the StratixII
-- LVDS Tx
--
--////////////////////////////////////////////////////////////////////////////
LIBRARY IEEE, std;
USE IEEE.std_logic_1164.all;
USE IEEE.VITAL_Timing.all;
USE IEEE.VITAL_Primitives.all;
USE work.stratixii_atom_pack.all;
USE std.textio.all;
ENTITY stratixii_lvds_tx_parallel_register is
GENERIC ( channel_width : integer := 10;
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*";
tsetup_datain_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_datain_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_clk_dataout_posedge : VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefpropDelay01;
tipd_enable : VitalDelayType01 := DefpropDelay01;
tipd_datain : VitalDelayArrayType01(9 downto 0) := (OTHERS => DefpropDelay01)
);
PORT ( clk : in std_logic;
enable : in std_logic;
datain : in std_logic_vector(channel_width - 1 downto 0);
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
dataout : out std_logic_vector(channel_width - 1 downto 0)
);
END stratixii_lvds_tx_parallel_register;
ARCHITECTURE vital_tx_reg of stratixii_lvds_tx_parallel_register is
signal clk_ipd : std_logic;
signal enable_ipd : std_logic;
signal datain_ipd : std_logic_vector(channel_width - 1 downto 0);
begin
----------------------
-- INPUT PATH DELAYs
----------------------
WireDelay : block
begin
VitalWireDelay (clk_ipd, clk, tipd_clk);
VitalWireDelay (enable_ipd, enable, tipd_enable);
loopbits : FOR i in datain'RANGE GENERATE
VitalWireDelay (datain_ipd(i), datain(i), tipd_datain(i));
END GENERATE;
end block;
VITAL: process (clk_ipd, enable_ipd, datain_ipd, devpor, devclrn)
variable Tviol_datain_clk : std_ulogic := '0';
variable TimingData_datain_clk : VitalTimingDataType := VitalTimingDataInit;
variable dataout_VitalGlitchDataArray : VitalGlitchDataArrayType(9 downto 0);
variable i : integer := 0;
variable dataout_tmp : std_logic_vector(channel_width - 1 downto 0);
variable CQDelay : TIME := 0 ns;
begin
if (now = 0 ns) then
dataout_tmp := (OTHERS => '0');
end if;
------------------------
-- Timing Check Section
------------------------
if (TimingChecksOn) then
VitalSetupHoldCheck (
Violation => Tviol_datain_clk,
TimingData => TimingData_datain_clk,
TestSignal => datain_ipd,
TestSignalName => "DATAIN",
RefSignal => clk_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_datain_clk_noedge_posedge,
SetupLow => tsetup_datain_clk_noedge_posedge,
HoldHigh => thold_datain_clk_noedge_posedge,
HoldLow => thold_datain_clk_noedge_posedge,
RefTransition => '/',
HeaderMsg => InstancePath & "/stratixii_lvds_tx_parallel_register",
XOn => XOn,
MsgOn => MsgOnChecks );
end if;
if ((devpor = '0') or (devclrn = '0')) then
dataout_tmp := (OTHERS => '0');
else
if (clk_ipd'event and clk_ipd = '1') then
if (enable_ipd = '1') then
dataout_tmp := datain_ipd;
end if;
end if;
end if;
----------------------
-- Path Delay Section
----------------------
CQDelay := SelectDelay(
(1 => (clk_ipd'last_event, tpd_clk_dataout_posedge, TRUE))
);
dataout <= TRANSPORT dataout_tmp AFTER CQDelay;
end process;
end vital_tx_reg;
--////////////////////////////////////////////////////////////////////////////
--
-- Entity name : stratixii_lvds_tx_out_block
--
-- Description : Negative-edge triggered register on the Tx output.
-- Also, optionally generates an identical/inverted output clock
--
--////////////////////////////////////////////////////////////////////////////
LIBRARY IEEE, std;
USE IEEE.std_logic_1164.all;
USE IEEE.VITAL_Timing.all;
USE IEEE.VITAL_Primitives.all;
USE work.stratixii_atom_pack.all;
USE std.textio.all;
ENTITY stratixii_lvds_tx_out_block is
GENERIC ( bypass_serializer : String := "false";
invert_clock : String := "false";
use_falling_clock_edge : String := "false";
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*";
tpd_clk_dataout : VitalDelayType01 := DefPropDelay01;
tpd_clk_dataout_negedge : VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefpropDelay01;
tipd_datain : VitalDelayType01 := DefpropDelay01
);
PORT ( clk : in std_logic;
datain : in std_logic;
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
dataout : out std_logic
);
END stratixii_lvds_tx_out_block;
ARCHITECTURE vital_tx_out_block of stratixii_lvds_tx_out_block is
signal clk_ipd : std_logic;
signal datain_ipd : std_logic;
signal inv_clk : integer;
begin
----------------------
-- INPUT PATH DELAYs
----------------------
WireDelay : block
begin
VitalWireDelay (clk_ipd, clk, tipd_clk);
VitalWireDelay (datain_ipd, datain, tipd_datain);
end block;
VITAL: process (clk_ipd, datain_ipd, devpor, devclrn)
variable dataout_VitalGlitchData : VitalGlitchDataType;
variable dataout_tmp : std_logic;
begin
if (now = 0 ns) then
dataout_tmp := '0';
else
if (bypass_serializer = "false") then
if (use_falling_clock_edge = "false") then
dataout_tmp := datain_ipd;
end if;
if (clk_ipd'event and clk_ipd = '0') then
if (use_falling_clock_edge = "true") then
dataout_tmp := datain_ipd;
end if;
end if;
else
if (invert_clock = "false") then
dataout_tmp := clk_ipd;
else
dataout_tmp := NOT (clk_ipd);
end if;
if (invert_clock = "false") then
inv_clk <= 0;
else
inv_clk <= 1;
end if;
end if;
end if;
----------------------
-- Path Delay Section
----------------------
if (bypass_serializer = "false") then
VitalPathDelay01 (
OutSignal => dataout,
OutSignalName => "DATAOUT",
OutTemp => dataout_tmp,
Paths => (0 => (datain_ipd'last_event, DefpropDelay01, TRUE),
1 => (clk_ipd'last_event, tpd_clk_dataout_negedge, TRUE)),
GlitchData => dataout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end if;
if (bypass_serializer = "true") then
VitalPathDelay01 (
OutSignal => dataout,
OutSignalName => "DATAOUT",
OutTemp => dataout_tmp,
Paths => (1 => (clk_ipd'last_event, tpd_clk_dataout, TRUE)),
GlitchData => dataout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end if;
end process;
end vital_tx_out_block;
--////////////////////////////////////////////////////////////////////////////
--
-- Entity name : stratixii_lvds_transmitter
--
-- Description : Timing simulation model for the StratixII LVDS Tx WYSIWYG.
-- It instantiates the following sub-modules :
-- 1) primitive DFFE
-- 2) StratixII_lvds_tx_parallel_register and
-- 3) StratixII_lvds_tx_out_block
--
--////////////////////////////////////////////////////////////////////////////
LIBRARY IEEE, std;
USE IEEE.std_logic_1164.all;
USE IEEE.VITAL_Timing.all;
USE IEEE.VITAL_Primitives.all;
USE work.stratixii_atom_pack.all;
USE std.textio.all;
USE work.stratixii_lvds_tx_parallel_register;
USE work.stratixii_lvds_tx_out_block;
USE work.stratixii_lvds_tx_reg;
ENTITY stratixii_lvds_transmitter is
GENERIC ( channel_width : integer := 10;
bypass_serializer : String := "false";
invert_clock : String := "false";
use_falling_clock_edge : String := "false";
use_serial_data_input : String := "false";
use_post_dpa_serial_data_input : String := "false";
preemphasis_setting : integer := 0;
vod_setting : integer := 0;
differential_drive : integer := 0;
lpm_type : string := "stratixii_lvds_transmitter";
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*";
tpd_clk0_dataout_posedge : VitalDelayType01 := DefPropDelay01;
tpd_clk0_dataout_negedge : VitalDelayType01 := DefPropDelay01;
tpd_serialdatain_dataout : VitalDelayType01 := DefPropDelay01;
tpd_postdpaserialdatain_dataout : VitalDelayType01 := DefPropDelay01;
tipd_clk0 : VitalDelayType01 := DefpropDelay01;
tipd_enable0 : VitalDelayType01 := DefpropDelay01;
tipd_datain : VitalDelayArrayType01(9 downto 0) := (OTHERS => DefpropDelay01);
tipd_serialdatain : VitalDelayType01 := DefpropDelay01;
tipd_postdpaserialdatain : VitalDelayType01 := DefpropDelay01
);
PORT ( clk0 : in std_logic;
enable0 : in std_logic;
datain : in std_logic_vector(channel_width - 1 downto 0);
serialdatain : in std_logic := '0';
postdpaserialdatain : in std_logic := '0';
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
dataout : out std_logic;
serialfdbkout : out std_logic
);
end stratixii_lvds_transmitter;
ARCHITECTURE vital_transmitter_atom of stratixii_lvds_transmitter is
signal clk0_ipd : std_logic;
signal serialdatain_ipd : std_logic;
signal postdpaserialdatain_ipd : std_logic;
signal input_data : std_logic_vector(channel_width - 1 downto 0);
signal txload0 : std_logic;
signal shift_out : std_logic;
signal clk0_dly0 : std_logic;
signal clk0_dly1 : std_logic;
signal clk0_dly2 : std_logic;
signal datain_dly : std_logic_vector(channel_width - 1 downto 0);
signal datain_dly1 : std_logic_vector(channel_width - 1 downto 0);
signal datain_dly2 : std_logic_vector(channel_width - 1 downto 0);
signal datain_dly3 : std_logic_vector(channel_width - 1 downto 0);
signal datain_dly4 : std_logic_vector(channel_width - 1 downto 0);
signal vcc : std_logic := '1';
signal tmp_dataout : std_logic;
COMPONENT stratixii_lvds_tx_parallel_register
GENERIC ( channel_width : integer := 10;
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*";
tpd_clk_dataout_posedge : VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefpropDelay01;
tipd_enable : VitalDelayType01 := DefpropDelay01;
tipd_datain : VitalDelayArrayType01(9 downto 0) := (OTHERS => DefpropDelay01)
);
PORT ( clk : in std_logic;
enable : in std_logic;
datain : in std_logic_vector(channel_width - 1 downto 0);
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
dataout : out std_logic_vector(channel_width - 1 downto 0)
);
END COMPONENT;
COMPONENT stratixii_lvds_tx_out_block
GENERIC ( bypass_serializer : String := "false";
invert_clock : String := "false";
use_falling_clock_edge : String := "false";
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*";
tpd_clk_dataout : VitalDelayType01 := DefPropDelay01;
tpd_clk_dataout_negedge : VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefpropDelay01;
tipd_datain : VitalDelayType01 := DefpropDelay01
);
PORT ( clk : in std_logic;
datain : in std_logic;
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
dataout : out std_logic
);
END COMPONENT;
COMPONENT stratixii_lvds_tx_reg
GENERIC (TimingChecksOn : Boolean := true;
InstancePath : STRING := "*";
XOn : Boolean := DefGlitchXOn;
MsgOn : Boolean := DefGlitchMsgOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
tpd_clk_q_posedge : VitalDelayType01 := DefPropDelay01;
tsetup_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tipd_d : VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01
);
PORT ( q : out STD_LOGIC := '0';
d : in STD_LOGIC := '1';
clrn : in STD_LOGIC := '1';
prn : in STD_LOGIC := '1';
clk : in STD_LOGIC := '0';
ena : in STD_LOGIC := '1'
);
END COMPONENT;
begin
----------------------
-- INPUT PATH DELAYs
----------------------
WireDelay : block
begin
VitalWireDelay (clk0_ipd, clk0, tipd_clk0);
VitalWireDelay (serialdatain_ipd, serialdatain, tipd_serialdatain);
VitalWireDelay (postdpaserialdatain_ipd, postdpaserialdatain, tipd_postdpaserialdatain);
end block;
txload0_reg: stratixii_lvds_tx_reg
PORT MAP (d => enable0,
clrn => vcc,
prn => vcc,
ena => vcc,
clk => clk0_dly2,
q => txload0
);
input_reg: stratixii_lvds_tx_parallel_register
GENERIC MAP ( channel_width => channel_width)
PORT MAP ( clk => txload0,
enable => vcc,
datain => datain_dly,
dataout => input_data,
devclrn => devclrn,
devpor => devpor
);
output_module: stratixii_lvds_tx_out_block
GENERIC MAP ( bypass_serializer => bypass_serializer,
use_falling_clock_edge => use_falling_clock_edge,
invert_clock => invert_clock)
PORT MAP ( clk => clk0_dly2,
datain => shift_out,
dataout => tmp_dataout,
devclrn => devclrn,
devpor => devpor
);
clk_delay: process (clk0_ipd, datain)
begin
clk0_dly0 <= clk0_ipd;
datain_dly1 <= datain;
end process;
clk_delay1: process (clk0_dly0, datain_dly1)
begin
clk0_dly1 <= clk0_dly0;
datain_dly2 <= datain_dly1;
end process;
clk_delay2: process (clk0_dly1, datain_dly2)
begin
clk0_dly2 <= clk0_dly1;
datain_dly3 <= datain_dly2;
end process;
data_delay: process (datain_dly3)
begin
datain_dly4 <= datain_dly3;
end process;
data_delay1: process (datain_dly4)
begin
datain_dly <= datain_dly4;
end process;
VITAL: process (clk0_ipd, devclrn, devpor)
variable dataout_VitalGlitchData : VitalGlitchDataType;
variable i : integer := 0;
variable shift_data : std_logic_vector(channel_width-1 downto 0);
begin
if (now = 0 ns) then
shift_data := (OTHERS => '0');
end if;
if ((devpor = '0') or (devclrn = '0')) then
shift_data := (OTHERS => '0');
else
if (bypass_serializer = "false") then
if (clk0_ipd'event and clk0_ipd = '1') then
if (txload0 = '1') then
shift_data := input_data;
end if;
shift_out <= shift_data(channel_width - 1);
for i in channel_width-1 downto 1 loop
shift_data(i) := shift_data(i - 1);
end loop;
end if;
end if;
end if;
end process;
process (serialdatain_ipd, postdpaserialdatain_ipd, tmp_dataout)
variable dataout_tmp : std_logic := '0';
variable dataout_VitalGlitchData : VitalGlitchDataType;
begin
if (serialdatain_ipd'event and use_serial_data_input = "true") then
dataout_tmp := serialdatain_ipd;
elsif (postdpaserialdatain_ipd'event and use_post_dpa_serial_data_input = "true") then
dataout_tmp := postdpaserialdatain_ipd;
else
dataout_tmp := tmp_dataout;
end if;
----------------------
-- Path Delay Section
----------------------
if (use_serial_data_input = "true") then
VitalPathDelay01 (
OutSignal => dataout,
OutSignalName => "DATAOUT",
OutTemp => dataout_tmp,
Paths => (0 => (serialdatain_ipd'last_event, tpd_serialdatain_dataout, TRUE)),
GlitchData => dataout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
elsif (use_post_dpa_serial_data_input = "true") then
VitalPathDelay01 (
OutSignal => dataout,
OutSignalName => "DATAOUT",
OutTemp => dataout_tmp,
Paths => (0 => (postdpaserialdatain_ipd'last_event, tpd_postdpaserialdatain_dataout, TRUE)),
GlitchData => dataout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
else
VitalPathDelay01 (
OutSignal => dataout,
OutSignalName => "DATAOUT",
OutTemp => dataout_tmp,
Paths => (0 => (tmp_dataout'last_event, DefPropDelay01, TRUE)),
GlitchData => dataout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end if;
end process;
end vital_transmitter_atom;
--/////////////////////////////////////////////////////////////////////////////
--
-- Module Name : stratixii_lvds_reg
--
-- Description : Simulation model for a simple DFF.
-- This is used for registering the enable inputs.
-- No timing, powers upto 0.
--
--/////////////////////////////////////////////////////////////////////////////
LIBRARY IEEE, std;
USE ieee.std_logic_1164.all;
USE IEEE.VITAL_Timing.all;
USE IEEE.VITAL_Primitives.all;
USE work.stratixii_atom_pack.all;
ENTITY stratixii_lvds_reg is
GENERIC ( MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
TimingChecksOn : Boolean := True;
InstancePath : String := "*";
tipd_clk : VitalDelayType01 := DefpropDelay01;
tipd_ena : VitalDelayType01 := DefpropDelay01;
tipd_d : VitalDelayType01 := DefpropDelay01;
tpd_clk_q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_prn_q_negedge : VitalDelayType01 := DefPropDelay01;
tpd_clrn_q_negedge : VitalDelayType01 := DefPropDelay01
);
PORT ( q : OUT std_logic;
clk : IN std_logic;
ena : IN std_logic := '1';
d : IN std_logic;
clrn : IN std_logic := '1';
prn : IN std_logic := '1'
);
END stratixii_lvds_reg;
ARCHITECTURE vital_stratixii_lvds_reg of stratixii_lvds_reg is
-- INTERNAL SIGNALS
signal clk_ipd : std_logic;
signal d_ipd : std_logic;
signal ena_ipd : std_logic;
begin
----------------------
-- INPUT PATH DELAYs
----------------------
WireDelay : block
begin
VitalWireDelay (clk_ipd, clk, tipd_clk);
VitalWireDelay (ena_ipd, ena, tipd_ena);
VitalWireDelay (d_ipd, d, tipd_d);
end block;
process (clk_ipd, d_ipd, clrn, prn)
variable q_tmp : std_logic := '0';
variable q_VitalGlitchData : VitalGlitchDataType;
variable Tviol_d_clk : std_ulogic := '0';
variable TimingData_d_clk : VitalTimingDataType := VitalTimingDataInit;
begin
------------------------
-- Timing Check Section
------------------------
if (prn = '0') then
q_tmp := '1';
elsif (clrn = '0') then
q_tmp := '0';
elsif (clk_ipd'event and clk_ipd = '1') then
if (ena_ipd = '1') then
q_tmp := d_ipd;
end if;
end if;
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
OutSignal => q,
OutSignalName => "Q",
OutTemp => q_tmp,
Paths => (1 => (clk_ipd'last_event, tpd_clk_q_posedge, TRUE)),
GlitchData => q_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
end vital_stratixii_lvds_reg;
--/////////////////////////////////////////////////////////////////////////////
--
-- Module Name : stratixii_lvds_rx_fifo_sync_ram
--
-- Description :
--
--/////////////////////////////////////////////////////////////////////////////
LIBRARY IEEE, std;
USE ieee.std_logic_1164.all;
USE IEEE.VITAL_Timing.all;
USE IEEE.VITAL_Primitives.all;
USE work.stratixii_atom_pack.all;
ENTITY stratixii_lvds_rx_fifo_sync_ram is
PORT ( clk : IN std_logic;
datain : IN std_logic := '0';
writereset : IN std_logic := '0';
waddr : IN std_logic_vector(2 DOWNTO 0) := "000";
raddr : IN std_logic_vector(2 DOWNTO 0) := "000";
we : IN std_logic := '0';
dataout : OUT std_logic
);
END stratixii_lvds_rx_fifo_sync_ram;
ARCHITECTURE vital_arm_lvds_rx_fifo_sync_ram OF stratixii_lvds_rx_fifo_sync_ram IS
-- INTERNAL SIGNALS
signal dataout_tmp : std_logic;
signal ram_d : std_logic_vector(0 TO 5);
signal ram_q : std_logic_vector(0 TO 5);
signal data_reg : std_logic_vector(0 TO 5);
begin
dataout <= dataout_tmp;
process (clk, writereset)
variable initial : boolean := true;
begin
if (initial) then
for i in 0 to 5 loop
ram_q(i) <= '0';
end loop;
initial := false;
end if;
if (writereset = '1') then
for i in 0 to 5 loop
ram_q(i) <= '0';
end loop;
elsif (clk'event and clk = '1') then
for i in 0 to 5 loop
ram_q(i) <= ram_d(i);
end loop;
end if;
end process;
process (we, data_reg, ram_q)
begin
if (we = '1') then
ram_d <= data_reg;
else
ram_d <= ram_q;
end if;
end process;
data_reg(0) <= datain when (waddr = "000") else ram_q(0) ;
data_reg(1) <= datain when (waddr = "001") else ram_q(1) ;
data_reg(2) <= datain when (waddr = "010") else ram_q(2) ;
data_reg(3) <= datain when (waddr = "011") else ram_q(3) ;
data_reg(4) <= datain when (waddr = "100") else ram_q(4) ;
data_reg(5) <= datain when (waddr = "101") else ram_q(5) ;
process (ram_q, we, waddr, raddr)
variable initial : boolean := true;
begin
if (initial) then
dataout_tmp <= '0';
initial := false;
end if;
case raddr is
when "000" =>
dataout_tmp <= ram_q(0);
when "001" =>
dataout_tmp <= ram_q(1);
when "010" =>
dataout_tmp <= ram_q(2);
when "011" =>
dataout_tmp <= ram_q(3);
when "100" =>
dataout_tmp <= ram_q(4);
when "101" =>
dataout_tmp <= ram_q(5);
when others =>
dataout_tmp <= '0';
end case;
end process;
END vital_arm_lvds_rx_fifo_sync_ram;
--/////////////////////////////////////////////////////////////////////////////
--
-- Module Name : stratixii_lvds_rx_fifo
--
-- Description :
--
--/////////////////////////////////////////////////////////////////////////////
LIBRARY IEEE, std;
USE ieee.std_logic_1164.all;
USE IEEE.VITAL_Timing.all;
USE IEEE.VITAL_Primitives.all;
USE work.stratixii_atom_pack.all;
USE work.stratixii_lvds_rx_fifo_sync_ram;
ENTITY stratixii_lvds_rx_fifo is
GENERIC ( channel_width : integer := 10;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*";
tipd_wclk : VitalDelayType01 := DefpropDelay01;
tipd_rclk : VitalDelayType01 := DefpropDelay01;
tipd_dparst : VitalDelayType01 := DefpropDelay01;
tipd_fiforst : VitalDelayType01 := DefpropDelay01;
tipd_datain : VitalDelayType01 := DefpropDelay01;
tpd_rclk_dataout_posedge: VitalDelayType01 := DefPropDelay01;
tpd_dparst_dataout_posedge: VitalDelayType01 := DefPropDelay01
);
PORT ( wclk : IN std_logic:= '0';
rclk : IN std_logic:= '0';
dparst : IN std_logic := '0';
fiforst : IN std_logic := '0';
datain : IN std_logic := '0';
dataout : OUT std_logic
);
END stratixii_lvds_rx_fifo;
ARCHITECTURE vital_arm_lvds_rx_fifo of stratixii_lvds_rx_fifo is
-- INTERNAL SIGNALS
signal datain_in : std_logic;
signal rclk_in : std_logic;
signal dparst_in : std_logic;
signal fiforst_in : std_logic;
signal wclk_in : std_logic;
signal ram_datain : std_logic;
signal ram_dataout : std_logic;
signal wrPtr : std_logic_vector(2 DOWNTO 0);
signal rdPtr : std_logic_vector(2 DOWNTO 0);
signal rdAddr : std_logic_vector(2 DOWNTO 0);
signal ram_we : std_logic;
signal write_side_sync_reset : std_logic;
signal read_side_sync_reset : std_logic;
COMPONENT stratixii_lvds_rx_fifo_sync_ram
PORT ( clk : IN std_logic;
datain : IN std_logic := '0';
writereset : IN std_logic := '0';
waddr : IN std_logic_vector(2 DOWNTO 0) := "000";
raddr : IN std_logic_vector(2 DOWNTO 0) := "000";
we : IN std_logic := '0';
dataout : OUT std_logic
);
END COMPONENT;
begin
----------------------
-- INPUT PATH DELAYs
----------------------
WireDelay : block
begin
VitalWireDelay (wclk_in, wclk, tipd_wclk);
VitalWireDelay (rclk_in, rclk, tipd_rclk);
VitalWireDelay (dparst_in, dparst, tipd_dparst);
VitalWireDelay (fiforst_in, fiforst, tipd_fiforst);
VitalWireDelay (datain_in, datain, tipd_datain);
end block;
rdAddr <= rdPtr ;
s_fifo_ram : stratixii_lvds_rx_fifo_sync_ram
PORT MAP ( clk => wclk_in,
datain => ram_datain,
writereset => write_side_sync_reset,
waddr => wrPtr,
raddr => rdAddr,
we => ram_we,
dataout => ram_dataout
);
process (wclk_in, dparst_in)
variable initial : boolean := true;
begin
if (initial) then
wrPtr <= "000";
write_side_sync_reset <= '0';
ram_we <= '0';
ram_datain <= '0';
initial := false;
end if;
if (dparst_in = '1' or (fiforst_in = '1' and wclk_in'event and wclk_in = '1')) then
write_side_sync_reset <= '1';
ram_datain <= '0';
wrPtr <= "000";
ram_we <= '0';
elsif (dparst_in = '0' and (fiforst_in = '0' and wclk_in'event and wclk_in = '1')) then
write_side_sync_reset <= '0';
end if;
if (wclk_in'event and wclk_in = '1' and write_side_sync_reset = '0' and fiforst_in = '0' and dparst_in = '0') then
ram_datain <= datain_in;
ram_we <= '1';
case wrPtr is
when "000" => wrPtr <= "001";
when "001" => wrPtr <= "010";
when "010" => wrPtr <= "011";
when "011" => wrPtr <= "100";
when "100" => wrPtr <= "101";
when "101" => wrPtr <= "000";
when others => wrPtr <= "000";
end case;
end if;
end process;
process (rclk_in, dparst_in)
variable initial : boolean := true;
variable dataout_tmp : std_logic := '0';
variable dataout_VitalGlitchData : VitalGlitchDataType;
begin
if (initial) then
rdPtr <= "011";
read_side_sync_reset <= '0';
dataout_tmp := '0';
initial := false;
end if;
if (dparst_in = '1' or (fiforst_in = '1' and rclk_in'event and rclk_in = '1')) then
read_side_sync_reset <= '1';
rdPtr <= "011";
dataout_tmp := '0';
elsif (dparst_in = '0' and (fiforst_in = '0' and rclk_in'event and rclk_in = '1')) then
read_side_sync_reset <= '0';
end if;
if (rclk_in'event and rclk_in = '1' and read_side_sync_reset = '0' and fiforst_in = '0' and dparst_in = '0') then
case rdPtr is
when "000" => rdPtr <= "001";
when "001" => rdPtr <= "010";
when "010" => rdPtr <= "011";
when "011" => rdPtr <= "100";
when "100" => rdPtr <= "101";
when "101" => rdPtr <= "000";
when others => rdPtr <= "000";
end case;
dataout_tmp := ram_dataout;
end if;
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
Outsignal => dataout,
OutsignalName => "DATAOUT",
OutTemp => dataout_tmp,
Paths => (1 => (rclk_in'last_event, tpd_rclk_dataout_posedge, TRUE)),
GlitchData => dataout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
END vital_arm_lvds_rx_fifo;
--/////////////////////////////////////////////////////////////////////////////
--
-- Module Name : stratixii_lvds_rx_bitslip
--
-- Description :
--
--/////////////////////////////////////////////////////////////////////////////
LIBRARY IEEE, std;
USE ieee.std_logic_1164.all;
USE IEEE.VITAL_Timing.all;
USE IEEE.VITAL_Primitives.all;
USE work.stratixii_atom_pack.all;
USE work.stratixii_lvds_reg;
ENTITY stratixii_lvds_rx_bitslip is
GENERIC ( channel_width : integer := 10;
bitslip_rollover : integer := 12;
x_on_bitslip : string := "on";
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*";
tipd_clk0 : VitalDelayType01 := DefpropDelay01;
tipd_bslipcntl : VitalDelayType01 := DefpropDelay01;
tipd_bsliprst : VitalDelayType01 := DefpropDelay01;
tipd_datain : VitalDelayType01 := DefpropDelay01;
tpd_bsliprst_bslipmax_posedge: VitalDelayType01 := DefPropDelay01;
tpd_clk0_bslipmax_posedge: VitalDelayType01 := DefPropDelay01
);
PORT ( clk0 : IN std_logic := '0';
bslipcntl : IN std_logic := '0';
bsliprst : IN std_logic := '0';
datain : IN std_logic := '0';
bslipmax : OUT std_logic;
dataout : OUT std_logic
);
END stratixii_lvds_rx_bitslip;
ARCHITECTURE vital_arm_lvds_rx_bitslip OF stratixii_lvds_rx_bitslip IS
-- INTERNAL SIGNALS
signal clk0_in : std_logic;
signal bslipcntl_in : std_logic;
signal bsliprst_in : std_logic;
signal datain_in : std_logic;
signal slip_count : integer := 0;
signal dataout_tmp : std_logic;
signal bitslip_arr : std_logic_vector(11 DOWNTO 0) := "000000000000";
signal bslipcntl_reg : std_logic;
signal vcc : std_logic := '1';
signal slip_data : std_logic := '0';
signal start_corrupt_bits : std_logic := '0';
signal num_corrupt_bits : integer := 0;
COMPONENT stratixii_lvds_reg
GENERIC ( MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*";
tipd_clk : VitalDelayType01 := DefpropDelay01;
tipd_ena : VitalDelayType01 := DefpropDelay01;
tipd_d : VitalDelayType01 := DefpropDelay01;
tpd_clk_q_posedge : VitalDelayType01 := DefPropDelay01
);
PORT ( q : OUT std_logic;
clk : IN std_logic;
ena : IN std_logic := '1';
d : IN std_logic;
clrn : IN std_logic := '1';
prn : IN std_logic := '1'
);
END COMPONENT;
begin
----------------------
-- INPUT PATH DELAYs
----------------------
WireDelay : block
begin
VitalWireDelay (clk0_in, clk0, tipd_clk0);
VitalWireDelay (bslipcntl_in, bslipcntl, tipd_bslipcntl);
VitalWireDelay (bsliprst_in, bsliprst, tipd_bsliprst);
VitalWireDelay (datain_in, datain, tipd_datain);
end block;
bslipcntlreg : stratixii_lvds_reg
PORT MAP ( d => bslipcntl_in,
clk => clk0_in,
ena => vcc,
clrn => vcc,
prn => vcc,
q => bslipcntl_reg
);
-- 4-bit slip counter and 12-bit shift register
process (bslipcntl_reg, bsliprst_in, clk0_in)
variable initial : boolean := true;
variable bslipmax_tmp : std_logic := '0';
variable bslipmax_VitalGlitchData : VitalGlitchDataType;
begin
if (bsliprst_in = '1') then
slip_count <= 0;
bslipmax_tmp := '0';
-- bitslip_arr <= (OTHERS => '0');
if (bsliprst_in'event and bsliprst_in = '1' and bsliprst_in'last_value = '0') then
ASSERT false report "Bit Slip Circuit was reset. Serial Data stream will have 0 latency" severity note;
end if;
else
if (bslipcntl_reg'event and bslipcntl_reg = '1' and bslipcntl_reg'last_value = '0') then
if (x_on_bitslip = "on") then
start_corrupt_bits <= '1';
end if;
num_corrupt_bits <= 0;
if (slip_count = bitslip_rollover) then
ASSERT false report "Rollover occurred on Bit Slip circuit. Serial data stream will have 0 latency." severity note;
slip_count <= 0;
bslipmax_tmp := '0';
else
slip_count <= slip_count + 1;
if ((slip_count + 1) = bitslip_rollover) then
ASSERT false report "The Bit Slip circuit has reached the maximum Bit Slip limit. Rollover will occur on the next slip." severity note;
bslipmax_tmp := '1';
end if;
end if;
elsif (bslipcntl_reg'event and bslipcntl_reg = '0' and bslipcntl_reg'last_value = '1') then
start_corrupt_bits <= '0';
num_corrupt_bits <= 0;
end if;
end if;
if (clk0_in'event and clk0_in = '1' and clk0_in'last_value = '0') then
bitslip_arr(0) <= datain_in;
for i in 0 to (bitslip_rollover - 1) loop
bitslip_arr(i + 1) <= bitslip_arr(i);
end loop;
if (start_corrupt_bits = '1') then
num_corrupt_bits <= num_corrupt_bits + 1;
end if;
if (num_corrupt_bits+1 = 3) then
start_corrupt_bits <= '0';
end if;
end if;
-- end if;
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
Outsignal => bslipmax,
OutsignalName => "BSLIPMAX",
OutTemp => bslipmax_tmp,
Paths => (1 => (clk0_in'last_event, tpd_clk0_bslipmax_posedge, TRUE),
2 => (bsliprst_in'last_event, tpd_bsliprst_bslipmax_posedge, TRUE)),
GlitchData => bslipmax_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
-- Bit Slip shift register
-- process (clk0_in, bsliprst_in)
-- begin
-- if (bsliprst_in = '1') then
-- elsif (clk0_in'event and clk0_in = '1' and clk0'last_value = '0') then
-- bitslip_arr(0) <= datain_in;
-- for i in 0 to (bitslip_rollover - 1) loop
-- bitslip_arr(i + 1) <= bitslip_arr(i);
-- end loop;
--
-- if (start_corrupt_bits = '1') then
-- num_corrupt_bits <= num_corrupt_bits + 1;
-- end if;
-- if (num_corrupt_bits+1 = 3) then
-- start_corrupt_bits <= '0';
-- end if;
-- end if;
-- end process;
slip_data <= bitslip_arr(slip_count);
dataoutreg : stratixii_lvds_reg
PORT MAP ( d => slip_data,
clk => clk0_in,
ena => vcc,
clrn => vcc,
prn => vcc,
q => dataout_tmp
);
dataout <= dataout_tmp when start_corrupt_bits = '0' else
'X' when start_corrupt_bits = '1' and num_corrupt_bits < 3 else
dataout_tmp;
END vital_arm_lvds_rx_bitslip;
--/////////////////////////////////////////////////////////////////////////////
--
-- Module Name : stratixii_lvds_rx_deser
--
-- Description : Timing simulation model for the STRATIXII LVDS RECEIVER
-- DESERIALIZER. This module receives serial data and outputs
-- parallel data word of width = channel width
--
--////////////////////////////////////////////////////////////////////////////
LIBRARY IEEE;
USE ieee.std_logic_1164.all;
USE IEEE.VITAL_Timing.all;
USE IEEE.VITAL_Primitives.all;
USE work.stratixii_atom_pack.all;
ENTITY stratixii_lvds_rx_deser IS
GENERIC ( channel_width : integer := 4;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*";
tipd_clk : VitalDelayType01 := DefpropDelay01;
tipd_datain : VitalDelayType01 := DefpropDelay01;
tpd_clk_dataout_posedge : VitalDelayType01 := DefPropDelay01
);
PORT ( clk : IN std_logic := '0';
datain : IN std_logic := '0';
dataout : OUT std_logic_vector(channel_width - 1 DOWNTO 0);
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1'
);
END stratixii_lvds_rx_deser;
ARCHITECTURE vital_arm_lvds_rx_deser OF stratixii_lvds_rx_deser IS
-- INTERNAL SIGNALS
signal clk_ipd : std_logic;
signal datain_ipd : std_logic;
begin
----------------------
-- INPUT PATH DELAYs
----------------------
WireDelay : block
begin
VitalWireDelay (clk_ipd, clk, tipd_clk);
VitalWireDelay (datain_ipd, datain, tipd_datain);
end block;
VITAL: process (clk_ipd, devpor, devclrn)
variable dataout_tmp : std_logic_vector(channel_width - 1 downto 0) := (OTHERS => '0');
variable i : integer := 0;
variable dataout_VitalGlitchDataArray : VitalGlitchDataArrayType(9 downto 0);
variable CQDelay : TIME := 0 ns;
begin
if (devclrn = '0' or devpor = '0') then
dataout_tmp := (OTHERS => '0');
else
if (clk_ipd'event and clk_ipd = '1' and clk_ipd'last_value = '0') then
for i in channel_width - 1 DOWNTO 1 loop
dataout_tmp(i) := dataout_tmp(i - 1);
end loop;
dataout_tmp(0) := datain_ipd;
end if;
end if;
----------------------
-- Path Delay Section
----------------------
CQDelay := SelectDelay (
(1 => (clk_ipd'last_event, tpd_clk_dataout_posedge, TRUE))
);
dataout <= TRANSPORT dataout_tmp AFTER CQDelay;
end process;
END vital_arm_lvds_rx_deser;
--/////////////////////////////////////////////////////////////////////////////
--
-- Module Name : stratixii_lvds_rx_parallel_reg
--
-- Description : Timing simulation model for the STRATIXII LVDS RECEIVER
-- PARALLEL REGISTER. The data width equals max. channel width,
-- which is 10.
--
--////////////////////////////////////////////////////////////////////////////
LIBRARY IEEE;
USE ieee.std_logic_1164.all;
USE IEEE.VITAL_Timing.all;
USE IEEE.VITAL_Primitives.all;
USE work.stratixii_atom_pack.all;
ENTITY stratixii_lvds_rx_parallel_reg IS
GENERIC ( channel_width : integer := 4;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*";
tipd_clk : VitalDelayType01 := DefpropDelay01;
tipd_enable : VitalDelayType01 := DefpropDelay01;
tipd_datain : VitalDelayArrayType01(9 downto 0) := (OTHERS => DefpropDelay01);
tpd_clk_dataout_posedge : VitalDelayType01 := DefPropDelay01
);
PORT ( clk : IN std_logic;
enable : IN std_logic := '1';
datain : IN std_logic_vector(channel_width - 1 DOWNTO 0);
dataout : OUT std_logic_vector(channel_width - 1 DOWNTO 0);
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1'
);
END stratixii_lvds_rx_parallel_reg;
ARCHITECTURE vital_arm_lvds_rx_parallel_reg OF stratixii_lvds_rx_parallel_reg IS
-- INTERNAL SIGNALS
signal clk_ipd : std_logic;
signal datain_ipd : std_logic_vector(channel_width - 1 downto 0);
signal enable_ipd : std_logic;
begin
----------------------
-- INPUT PATH DELAYs
----------------------
WireDelay : block
begin
VitalWireDelay (clk_ipd, clk, tipd_clk);
VitalWireDelay (enable_ipd, enable, tipd_enable);
loopbits : FOR i in datain'RANGE GENERATE
VitalWireDelay (datain_ipd(i), datain(i), tipd_datain(i));
END GENERATE;
end block;
VITAL: process (clk_ipd, devpor, devclrn)
variable dataout_tmp : std_logic_vector(channel_width - 1 downto 0) := (OTHERS => '0');
variable i : integer := 0;
variable dataout_VitalGlitchDataArray : VitalGlitchDataArrayType(9 downto 0);
variable CQDelay : TIME := 0 ns;
begin
if ((devpor = '0') or (devclrn = '0')) then
dataout_tmp := (OTHERS => '0');
else
if (clk_ipd'event and clk_ipd = '1') then
if (enable_ipd = '1') then
dataout_tmp := datain_ipd;
end if;
end if;
end if;
----------------------
-- Path Delay Section
----------------------
CQDelay := SelectDelay (
(1 => (clk_ipd'last_event, tpd_clk_dataout_posedge, TRUE))
);
dataout <= dataout_tmp AFTER CQDelay;
end process;
END vital_arm_lvds_rx_parallel_reg;
--/////////////////////////////////////////////////////////////////////////////
--
-- Module Name : STRATIXII_LVDS_RECEIVER
--
-- Description : Timing simulation model for the STRATIXII LVDS RECEIVER
-- atom. This module instantiates the following sub-modules :
-- 1) stratixii_lvds_rx_fifo
-- 2) stratixii_lvds_rx_bitslip
-- 3) DFFEs for the LOADEN signals
-- 4) stratixii_lvds_rx_parallel_reg
--
--/////////////////////////////////////////////////////////////////////////////
LIBRARY IEEE;
USE ieee.std_logic_1164.all;
USE IEEE.VITAL_Timing.all;
USE IEEE.VITAL_Primitives.all;
USE work.stratixii_atom_pack.all;
USE work.stratixii_lvds_rx_bitslip;
USE work.stratixii_lvds_rx_fifo;
USE work.stratixii_lvds_rx_deser;
USE work.stratixii_lvds_rx_parallel_reg;
USE work.stratixii_lvds_reg;
ENTITY stratixii_lvds_receiver IS
GENERIC ( channel_width : integer := 10;
data_align_rollover : integer := 2;
enable_dpa : string := "off";
lose_lock_on_one_change : string := "off";
reset_fifo_at_first_lock : string := "on";
align_to_rising_edge_only : string := "on";
use_serial_feedback_input : string := "off";
dpa_debug : string := "off";
x_on_bitslip : string := "on";
lpm_type : string := "stratixii_lvds_receiver";
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*";
tipd_clk0 : VitalDelayType01 := DefpropDelay01;
tipd_datain : VitalDelayType01 := DefpropDelay01;
tipd_enable0 : VitalDelayType01 := DefpropDelay01;
tipd_dpareset : VitalDelayType01 := DefpropDelay01;
tipd_dpahold : VitalDelayType01 := DefpropDelay01;
tipd_dpaswitch : VitalDelayType01 := DefpropDelay01;
tipd_fiforeset : VitalDelayType01 := DefpropDelay01;
tipd_bitslip : VitalDelayType01 := DefpropDelay01;
tipd_bitslipreset : VitalDelayType01 := DefpropDelay01;
tipd_serialfbk : VitalDelayType01 := DefpropDelay01;
tpd_clk0_dpalock_posedge : VitalDelayType01 := DefPropDelay01
);
PORT ( clk0 : IN std_logic;
datain : IN std_logic := '0';
enable0 : IN std_logic := '0';
dpareset : IN std_logic := '0';
dpahold : IN std_logic := '0';
dpaswitch : IN std_logic := '0';
fiforeset : IN std_logic := '0';
bitslip : IN std_logic := '0';
bitslipreset : IN std_logic := '0';
serialfbk : IN std_logic := '0';
dataout : OUT std_logic_vector(channel_width - 1 DOWNTO 0);
dpalock : OUT std_logic;
bitslipmax : OUT std_logic;
serialdataout : OUT std_logic;
postdpaserialdataout : OUT std_logic;
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1'
);
END stratixii_lvds_receiver;
ARCHITECTURE vital_arm_lvds_receiver OF stratixii_lvds_receiver IS
COMPONENT stratixii_lvds_rx_bitslip
GENERIC ( channel_width : integer := 10;
bitslip_rollover : integer := 12;
x_on_bitslip : string := "on";
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*";
tipd_clk0 : VitalDelayType01 := DefpropDelay01;
tipd_bslipcntl : VitalDelayType01 := DefpropDelay01;
tipd_bsliprst : VitalDelayType01 := DefpropDelay01;
tipd_datain : VitalDelayType01 := DefpropDelay01;
tpd_bsliprst_bslipmax_posedge: VitalDelayType01 := DefPropDelay01;
tpd_clk0_bslipmax_posedge: VitalDelayType01 := DefPropDelay01
);
PORT ( clk0 : IN std_logic := '0';
bslipcntl : IN std_logic := '0';
bsliprst : IN std_logic := '0';
datain : IN std_logic := '0';
bslipmax : OUT std_logic;
dataout : OUT std_logic
);
END COMPONENT;
COMPONENT stratixii_lvds_rx_fifo
GENERIC ( channel_width : integer := 10
);
PORT ( wclk : IN std_logic := '0';
rclk : IN std_logic := '0';
fiforst : IN std_logic := '0';
dparst : IN std_logic := '0';
datain : IN std_logic := '0';
dataout : OUT std_logic
);
END COMPONENT;
COMPONENT stratixii_lvds_rx_deser
GENERIC ( channel_width : integer := 4
);
PORT ( clk : IN std_logic;
datain : IN std_logic;
dataout : OUT std_logic_vector(channel_width - 1 DOWNTO 0);
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1'
);
END COMPONENT;
COMPONENT stratixii_lvds_rx_parallel_reg
GENERIC ( channel_width : integer := 4
);
PORT ( clk : IN std_logic;
enable : IN std_logic := '1';
datain : IN std_logic_vector(channel_width - 1 DOWNTO 0);
dataout : OUT std_logic_vector(channel_width - 1 DOWNTO 0);
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1'
);
END COMPONENT;
COMPONENT stratixii_lvds_reg
GENERIC ( MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*";
tipd_clk : VitalDelayType01 := DefpropDelay01;
tipd_ena : VitalDelayType01 := DefpropDelay01;
tipd_d : VitalDelayType01 := DefpropDelay01;
tpd_clk_q_posedge : VitalDelayType01 := DefPropDelay01
);
PORT ( q : OUT std_logic;
clk : IN std_logic;
ena : IN std_logic := '1';
d : IN std_logic;
clrn : IN std_logic := '1';
prn : IN std_logic := '1'
);
END COMPONENT;
-- INTERNAL SIGNALS
signal bitslip_ipd : std_logic;
signal bitslipreset_ipd : std_logic;
signal clk0_ipd : std_logic;
signal datain_ipd : std_logic;
signal dpahold_ipd : std_logic;
signal dpareset_ipd : std_logic;
signal dpaswitch_ipd : std_logic;
signal enable0_ipd : std_logic;
signal fiforeset_ipd : std_logic;
signal serialfbk_ipd : std_logic;
signal fifo_wclk : std_logic;
signal fifo_rclk : std_logic;
signal fifo_datain : std_logic;
signal fifo_dataout : std_logic;
signal fifo_reset : std_logic;
signal slip_datain : std_logic;
signal slip_dataout : std_logic;
signal bitslip_reset : std_logic;
-- wire deser_dataout;
signal dpareg0_out : std_logic;
signal dpareg1_out : std_logic;
signal dpa_clk : std_logic;
signal dpa_rst : std_logic;
signal datain_reg : std_logic;
signal deser_dataout : std_logic_vector(channel_width - 1 DOWNTO 0);
signal reset_fifo : std_logic;
signal first_dpa_lock : std_logic;
signal loadreg_datain : std_logic_vector(channel_width - 1 DOWNTO 0);
signal reset_int : std_logic;
signal gnd : std_logic := '0';
signal vcc : std_logic := '1';
signal in_reg_data : std_logic;
signal clk0_dly : std_logic;
signal datain_tmp : std_logic;
-- INTERNAL PARAMETERS
CONSTANT DPA_CYCLES_TO_LOCK : integer := 2;
signal xhdl_12 : std_logic;
signal rxload : std_logic;
begin
WireDelay : block
begin
VitalWireDelay (clk0_ipd, clk0, tipd_clk0);
VitalWireDelay (datain_ipd, datain, tipd_datain);
VitalWireDelay (enable0_ipd, enable0, tipd_enable0);
VitalWireDelay (dpareset_ipd, dpareset, tipd_dpareset);
VitalWireDelay (dpahold_ipd, dpahold, tipd_dpahold);
VitalWireDelay (dpaswitch_ipd, dpaswitch, tipd_dpaswitch);
VitalWireDelay (fiforeset_ipd, fiforeset, tipd_fiforeset);
VitalWireDelay (bitslip_ipd, bitslip, tipd_bitslip);
VitalWireDelay (bitslipreset_ipd, bitslipreset, tipd_bitslipreset);
VitalWireDelay (serialfbk_ipd, serialfbk, tipd_serialfbk);
end block;
fifo_rclk <= clk0_ipd WHEN (enable_dpa = "on") ELSE gnd ;
fifo_wclk <= dpa_clk ;
fifo_datain <= dpareg1_out WHEN (enable_dpa = "on") ELSE gnd ;
reset_int <= (NOT devpor) OR (NOT devclrn) ;
fifo_reset <= (NOT devpor) OR (NOT devclrn) OR fiforeset_ipd OR dpareset_ipd OR reset_fifo ;
bitslip_reset <= (NOT devpor) OR (NOT devclrn) OR bitslipreset_ipd ;
in_reg_data <= serialfbk_ipd WHEN (use_serial_feedback_input = "on") ELSE datain_ipd;
clk0_dly <= clk0_ipd;
xhdl_12 <= devclrn OR devpor;
-- SUB-MODULE INSTANTIATION
-- input register in non-DPA mode for sampling incoming data
in_reg : stratixii_lvds_reg
PORT MAP ( d => in_reg_data,
clk => clk0_dly,
ena => vcc,
clrn => xhdl_12,
prn => vcc,
q => datain_reg
);
dpa_clk <= clk0_ipd when (enable_dpa = "on") else '0' ;
dpa_rst <= dpareset_ipd when (enable_dpa = "on") else '0' ;
process (dpa_clk, dpa_rst)
variable dpa_lock_count : integer := 0;
variable dparst_msg : boolean := false;
variable dpa_is_locked : std_logic := '0';
variable dpalock_VitalGlitchData : VitalGlitchDataType;
variable initial : boolean := true;
begin
if (initial) then
if (reset_fifo_at_first_lock = "on") then
reset_fifo <= '1';
else
reset_fifo <= '0';
end if;
initial := false;
end if;
if (dpa_rst = '1') then
dpa_is_locked := '0';
dpa_lock_count := 0;
if (not dparst_msg) then
ASSERT false report "DPA was reset" severity note;
dparst_msg := true;
end if;
elsif (dpa_clk'event and dpa_clk = '1') then
dparst_msg := false;
if (dpa_is_locked = '0') then
dpa_lock_count := dpa_lock_count + 1;
if (dpa_lock_count > DPA_CYCLES_TO_LOCK) then
dpa_is_locked := '1';
ASSERT false report "DPA locked" severity note;
reset_fifo <= '0';
end if;
end if;
end if;
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
OutSignal => dpalock,
OutSignalName => "DPALOCK",
OutTemp => dpa_is_locked,
Paths => (1 => (clk0_ipd'last_event, tpd_clk0_dpalock_posedge, enable_dpa = "on")),
GlitchData => dpalock_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
-- ?????????? insert delay to mimic DPLL dataout ?????????
-- DPA registers
dpareg0 : stratixii_lvds_reg
PORT MAP ( d => in_reg_data,
clk => dpa_clk,
clrn => vcc,
prn => vcc,
ena => vcc,
q => dpareg0_out
);
dpareg1 : stratixii_lvds_reg
PORT MAP ( d => dpareg0_out,
clk => dpa_clk,
clrn => vcc,
prn => vcc,
ena => vcc,
q => dpareg1_out
);
s_fifo : stratixii_lvds_rx_fifo
GENERIC MAP ( channel_width => channel_width
)
PORT MAP ( wclk => fifo_wclk,
rclk => fifo_rclk,
fiforst => fifo_reset,
dparst => dpa_rst,
datain => fifo_datain,
dataout => fifo_dataout
);
slip_datain <= fifo_dataout when (enable_dpa = "on" and dpaswitch_ipd = '1') else datain_reg ;
s_bslip : stratixii_lvds_rx_bitslip
GENERIC MAP ( bitslip_rollover => data_align_rollover,
channel_width => channel_width,
x_on_bitslip => x_on_bitslip
)
PORT MAP ( clk0 => clk0_dly,
bslipcntl => bitslip_ipd,
bsliprst => bitslip_reset,
datain => slip_datain,
bslipmax => bitslipmax,
dataout => slip_dataout
);
--********* DESERIALISER *********//
-- only 1 enable signal used for StratixII
rxload_reg : stratixii_lvds_reg
PORT MAP ( d => enable0_ipd,
clk => clk0_dly,
ena => vcc,
clrn => vcc,
prn => vcc,
q => rxload
);
s_deser : stratixii_lvds_rx_deser
GENERIC MAP (channel_width => channel_width
)
PORT MAP (clk => clk0_dly,
datain => slip_dataout,
devclrn => devclrn,
devpor => devpor,
dataout => deser_dataout
);
output_reg : stratixii_lvds_rx_parallel_reg
GENERIC MAP ( channel_width => channel_width
)
PORT MAP ( clk => clk0_dly,
enable => rxload,
datain => deser_dataout,
devpor => devpor,
devclrn => devclrn,
dataout => dataout
);
postdpaserialdataout <= dpareg1_out ;
serialdataout <= datain_ipd;
END vital_arm_lvds_receiver;
-------------------------------------------------------------------------------
--
-- Entity Name : StratixII_dll
--
-- Outputs : delayctrlout - current delay chain settings for DQS pin
-- offsetctrlout - current delay offset setting
-- dqsupdate - update enable signal for delay setting latces
-- upndnout - raw output of the phase comparator
--
-- Inputs : clk - reference clock matching in frequency to DQS clock
-- aload - asychronous load signal for delay setting counter
-- when asserted, counter is loaded with initial value
-- offset - offset added/subtracted from delayctrlout
-- upndnin - up/down input port for delay setting counter in
-- use_updndnin mode (user control mode)
-- upndninclkena - clock enable for the delaying setting counter
-- addnsub - dynamically control +/- on offsetctrlout
--
-- Formulae : delay (input_period) = sim_loop_intrinsic_delay +
-- sim_loop_delay_increment * dllcounter;
--
-- Latency : 3 (clk8 cycles) = pc + dc + dr
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.stratixii_atom_pack.all;
USE work.stratixii_pllpack.all;
ENTITY stratixii_dll is
GENERIC (
input_frequency : string := "10000 ps";
delay_chain_length : integer := 16;
delay_buffer_mode : string := "low";
delayctrlout_mode : string := "normal";
static_delay_ctrl : integer := 0;
offsetctrlout_mode : string := "static";
static_offset : string := "0";
jitter_reduction : string := "false";
use_upndnin : string := "false";
use_upndninclkena : string := "false";
sim_valid_lock : integer := 1;
sim_loop_intrinsic_delay : integer := 1000;
sim_loop_delay_increment : integer := 100;
sim_valid_lockcount : integer := 90; -- 10000 = 1000 + 100*dllcounter
lpm_type : string := "stratixii_dll";
tipd_clk : VitalDelayType01 := DefpropDelay01;
tipd_aload : VitalDelayType01 := DefpropDelay01;
tipd_offset : VitalDelayArrayType01(5 downto 0) := (OTHERS => DefPropDelay01);
tipd_upndnin : VitalDelayType01 := DefpropDelay01;
tipd_upndninclkena : VitalDelayType01 := DefpropDelay01;
tipd_addnsub : VitalDelayType01 := DefpropDelay01;
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*";
tpd_offset_delayctrlout : VitalDelayType01 := DefPropDelay01;
tpd_clk_upndnout_posedge : VitalDelayType01 := DefPropDelay01;
tsetup_offset_clk_noedge_posedge : VitalDelayArrayType(5 downto 0) := (OTHERS => DefSetupHoldCnst);
thold_offset_clk_noedge_posedge : VitalDelayArrayType(5 downto 0) := (OTHERS => DefSetupHoldCnst);
tsetup_upndnin_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_upndnin_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_upndninclkena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_upndninclkena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_addnsub_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_addnsub_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_clk_delayctrlout_posedge : VitalDelayArrayType01(5 downto 0) := (OTHERS => DefPropDelay01)
);
PORT ( clk : IN std_logic := '0';
aload : IN std_logic := '0';
offset : IN std_logic_vector(5 DOWNTO 0) := "000000";
upndnin : IN std_logic := '1';
upndninclkena : IN std_logic := '1';
addnsub : IN std_logic := '1';
delayctrlout : OUT std_logic_vector(5 DOWNTO 0);
offsetctrlout : OUT std_logic_vector(5 DOWNTO 0);
dqsupdate : OUT std_logic;
upndnout : OUT std_logic;
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1'
);
END stratixii_dll;
ARCHITECTURE vital_armdll of stratixii_dll is
-- tuncate input integer to get 6 LSB bits
function dll_unsigned2bin (in_int : integer) return std_logic_vector is
variable tmp_int, i : integer;
variable tmp_bit : integer;
variable result : std_logic_vector(5 downto 0) := "000000";
begin
tmp_int := in_int;
for i in 0 to 5 loop
tmp_bit := tmp_int MOD 2;
if (tmp_bit = 1) then
result(i) := '1';
else
result(i) := '0';
end if;
tmp_int := tmp_int/2;
end loop;
return result;
end dll_unsigned2bin;
signal clk_in : std_logic := '0';
signal aload_in : std_logic := '0';
signal offset_in : std_logic_vector(5 DOWNTO 0) := "000000";
signal upndn_in : std_logic := '0';
signal upndninclkena_in : std_logic := '1';
signal addnsub_in : std_logic := '0';
signal delayctrl_out : std_logic_vector(5 DOWNTO 0) := "000000";
signal offsetctrl_out : std_logic_vector(5 DOWNTO 0) := "000000";
signal dqsupdate_out : std_logic := '1';
signal upndn_out : std_logic := '0';
signal para_delay_buffer_mode : std_logic_vector (1 DOWNTO 0) := "01";
signal para_delayctrlout_mode : std_logic_vector (1 DOWNTO 0) := "00";
signal para_offsetctrlout_mode : std_logic_vector (1 DOWNTO 0) := "00";
signal para_static_offset : integer := 0;
signal para_static_delay_ctrl : integer := 0;
signal para_jitter_reduction : std_logic := '0';
signal para_use_upndnin : std_logic := '0';
signal para_use_upndninclkena : std_logic := '1';
-- INTERNAL NETS AND VARIABLES
-- for functionality - by modules
-- delay and offset control out resolver
signal dr_delayctrl_out : std_logic_vector (5 DOWNTO 0) := "000000";
signal dr_delayctrl_int : integer := 0;
signal dr_offsetctrl_out : std_logic_vector (5 DOWNTO 0) := "000000";
signal dr_offsetctrl_int : integer := 0;
signal dr_offset_in : integer := 0;
signal dr_dllcount_in : integer := 0;
signal dr_addnsub_in : std_logic := '1';
signal dr_clk8_in : std_logic := '0';
signal dr_aload_in : std_logic := '0';
signal dr_reg_offset : integer := 0;
signal dr_reg_dllcount : integer := 0;
signal dr_delayctrl_out_tmp : integer := 0;
-- delay chain setting counter
signal dc_dllcount_out : integer := 0;
signal dc_dqsupdate_out : std_logic := '0';
signal dc_upndn_in : std_logic := '1';
signal dc_aload_in : std_logic := '0';
signal dc_upndnclkena_in : std_logic := '1';
signal dc_clk8_in : std_logic := '0';
signal dc_clk1_in : std_logic := '0';
signal dc_dlltolock_in : std_logic := '0';
signal dc_reg_dllcount : integer := 0;
signal dc_reg_dlltolock_pulse : std_logic := '0';
-- jitter reduction counter
signal jc_upndn_out : std_logic := '0';
signal jc_upndnclkena_out : std_logic := '1';
signal jc_clk8_in : std_logic := '0';
signal jc_upndn_in : std_logic := '1';
signal jc_aload_in : std_logic := '0';
signal jc_count : integer := 8;
signal jc_reg_upndn : std_logic := '0';
signal jc_reg_upndnclkena : std_logic := '0';
-- phase comparator
signal pc_upndn_out : std_logic := '1';
signal pc_dllcount_in : integer := 0;
signal pc_clk1_in : std_logic := '0';
signal pc_clk8_in : std_logic := '0';
signal pc_aload_in : std_logic := '0';
signal pc_reg_upndn : std_logic := '1';
signal pc_delay : integer := 0;
-- clock generator
signal cg_clk_in : std_logic := '0';
signal cg_aload_in : std_logic := '0';
signal cg_clk1_out : std_logic := '0';
signal cg_clk8a_out : std_logic := '0';
signal cg_clk8b_out : std_logic := '0';
-- por: 000
signal cg_reg_1 : std_logic := '0';
signal cg_rega_2 : std_logic := '0';
signal cg_rega_3 : std_logic := '0';
-- por: 010
signal cg_regb_2 : std_logic := '1';
signal cg_regb_3 : std_logic := '0';
-- for violation checks
signal dll_to_lock : std_logic := '0';
signal input_period : integer := 10000;
signal clk_in_last_value : std_logic := 'X';
begin
-- paramters
input_period <= dqs_str2int(input_frequency);
para_static_offset <= dqs_str2int(static_offset);
para_static_delay_ctrl <= static_delay_ctrl;
para_use_upndnin <= '1' WHEN use_upndnin = "true" ELSE '0';
para_jitter_reduction <= '1' WHEN jitter_reduction = "true" ELSE '0';
para_use_upndninclkena <= '1' WHEN use_upndninclkena = "true" ELSE '0';
para_delay_buffer_mode <= "00" WHEN delay_buffer_mode = "auto" ELSE "01" WHEN delay_buffer_mode = "low" ELSE "10";
para_delayctrlout_mode <= "01" WHEN delayctrlout_mode = "offset_only" ELSE "10" WHEN delayctrlout_mode="normal_offset" ELSE "11" WHEN delayctrlout_mode="static" ELSE "00";
para_offsetctrlout_mode <= "11" WHEN offsetctrlout_mode = "dynamic_addnsub" ELSE "10" WHEN offsetctrlout_mode = "dynamic_sub" ELSE "01" WHEN offsetctrlout_mode = "dynamic_add" ELSE "00";
-- violation check block
process (clk_in)
variable got_first_rising_edge : std_logic := '0';
variable got_first_falling_edge : std_logic := '0';
variable per_violation : std_logic := '0';
variable duty_violation : std_logic := '0';
variable sent_per_violation : std_logic := '0';
variable sent_duty_violation : std_logic := '0';
variable clk_in_last_rising_edge : time := 0 ps;
variable clk_in_last_falling_edge : time := 0 ps;
variable input_period_ps : time := 10000 ps;
variable duty_cycle : time := 5000 ps;
variable clk_in_period : time := 10000 ps;
variable clk_in_duty_cycle : time := 5000 ps;
variable clk_per_tolerance : time := 2 ps;
variable half_cycles_to_lock : integer := 1;
variable init : boolean := true;
begin
if (init) then
input_period_ps := dqs_str2int(input_frequency) * 1 ps;
if (input_period_ps = 0 ps) then
assert false report "Need to specify ps scale in simulation command" severity error;
end if;
duty_cycle := input_period_ps/2;
clk_per_tolerance := 2 ps;
half_cycles_to_lock := 0;
init := false;
end if;
if (clk_in'event and clk_in = '1') then -- rising edge
if (got_first_rising_edge = '0') then
got_first_rising_edge := '1';
else -- subsequent rising
-- check for clock period and duty cycle violation
clk_in_period := now - clk_in_last_rising_edge;
clk_in_duty_cycle := now - clk_in_last_falling_edge;
if ((clk_in_period < (input_period_ps - clk_per_tolerance)) or (clk_in_period > (input_period_ps + clk_per_tolerance))) then
per_violation := '1';
if (sent_per_violation /= '1') then
sent_per_violation := '1';
assert false report "Input clock frequency violation." severity warning;
end if;
elsif ((clk_in_duty_cycle < (duty_cycle - clk_per_tolerance/2 - 1 ps)) or (clk_in_duty_cycle > (duty_cycle + clk_per_tolerance/2 + 1 ps))) then
duty_violation := '1';
if (sent_duty_violation /= '1') then
sent_duty_violation := '1';
assert false report "Input clock duty cycle violation." severity warning;
end if;
else
if (per_violation = '1') then
sent_per_violation := '0';
assert false report "Input clock frequency now matches specified clock frequency." severity warning;
end if;
per_violation := '0';
duty_violation := '0';
end if;
end if;
if (per_violation = '0' and duty_violation = '0' and dll_to_lock = '0') then
half_cycles_to_lock := half_cycles_to_lock + 1;
if (half_cycles_to_lock >= sim_valid_lock) then
dll_to_lock <= '1';
assert false report "DLL to lock to incoming clock" severity note;
end if;
end if;
clk_in_last_rising_edge := now;
elsif (clk_in'event and clk_in = '0') then -- falling edge
got_first_falling_edge := '1';
if (got_first_rising_edge = '1') then
-- duty cycle check
clk_in_duty_cycle := now - clk_in_last_rising_edge;
if ((clk_in_duty_cycle < (duty_cycle - clk_per_tolerance/2 - 1 ps)) or (clk_in_duty_cycle > (duty_cycle + clk_per_tolerance/2 + 1 ps))) then
duty_violation := '1';
if (sent_duty_violation /= '1') then
sent_duty_violation := '1';
assert false report "Input clock duty cycle violation." severity warning;
end if;
else
duty_violation := '0';
end if;
if (dll_to_lock = '0' and duty_violation = '0') then
half_cycles_to_lock := half_cycles_to_lock + 1;
end if;
end if;
clk_in_last_falling_edge := now;
elsif (got_first_falling_edge = '1' or got_first_rising_edge = '1') then
-- switches from 1, 0 to X
half_cycles_to_lock := 0;
got_first_rising_edge := '0';
got_first_falling_edge := '0';
if (dll_to_lock = '1') then
dll_to_lock <= '0';
assert false report "Illegal value detected on input clock. DLL will lose lock." severity error;
else
assert false report "Illegal value detected on input clock." severity error;
end if;
end if;
clk_in_last_value <= clk_in;
end process ; -- violation check
-- outputs
delayctrl_out <= dr_delayctrl_out;
offsetctrl_out <= dr_offsetctrl_out;
dqsupdate_out <= cg_clk8a_out;
upndn_out <= pc_upndn_out;
-- Delay and offset ctrl out resolver -------------------------------------
-------- convert calculations into integer
-- inputs
dr_clk8_in <= not cg_clk8b_out;
dr_offset_in <= (64 - alt_conv_integer(offset_in)) WHEN ((offset_in /= "000000") AND ((offsetctrlout_mode = "dynamic_addnsub" AND addnsub_in = '0') or (offsetctrlout_mode = "dynamic_sub"))) ELSE
alt_conv_integer(offset_in);
dr_dllcount_in <= dc_dllcount_out;
dr_addnsub_in <= addnsub_in;
dr_aload_in <= aload_in;
-- outputs
dr_delayctrl_out <= dll_unsigned2bin(dr_delayctrl_out_tmp);
dr_offsetctrl_out <= dll_unsigned2bin(dr_reg_offset);
dr_delayctrl_out_tmp <= dr_offset_in WHEN (delayctrlout_mode = "offset_only") ELSE
dr_reg_offset WHEN (delayctrlout_mode = "normal_offset") ELSE
dr_reg_dllcount;
dr_delayctrl_int <= para_static_delay_ctrl WHEN (delayctrlout_mode = "static") ELSE
dr_dllcount_in;
dr_offsetctrl_int <= para_static_offset WHEN (offsetctrlout_mode = "static") ELSE
dr_offset_in;
-- model
process(dr_clk8_in, dr_aload_in)
begin
if (dr_aload_in = '1' and dr_aload_in'event) then
dr_reg_dllcount <= 0;
elsif (dr_clk8_in = '1' and dr_clk8_in'event and dr_aload_in /= '1') then
dr_reg_dllcount <= dr_delayctrl_int;
end if;
end process;
-- generating dr_reg_offset
process(dr_clk8_in, dr_aload_in)
begin
if (dr_aload_in = '1' and dr_aload_in'event) then
dr_reg_offset <= 0;
elsif (dr_aload_in /= '1' and dr_clk8_in = '1' and dr_clk8_in'event) then
if (offsetctrlout_mode = "dynamic_addnsub") then
if (dr_addnsub_in = '1') then
if (dr_delayctrl_int < 63 - dr_offset_in) then
dr_reg_offset <= dr_delayctrl_int + dr_offset_in;
else
dr_reg_offset <= 63;
end if;
elsif (dr_addnsub_in = '0') then
if (dr_delayctrl_int > dr_offset_in) then
dr_reg_offset <= dr_delayctrl_int - dr_offset_in;
else
dr_reg_offset <= 0;
end if;
end if;
elsif (offsetctrlout_mode = "dynamic_sub") then
if (dr_delayctrl_int > dr_offset_in) then
dr_reg_offset <= dr_delayctrl_int - dr_offset_in;
else
dr_reg_offset <= 0;
end if;
elsif (offsetctrlout_mode = "dynamic_add") then
if (dr_delayctrl_int < 63 - dr_offset_in) then
dr_reg_offset <= dr_delayctrl_int + dr_offset_in;
else
dr_reg_offset <= 63;
end if;
elsif (offsetctrlout_mode = "static") then
if (para_static_offset >= 0) then
if ((para_static_offset < 64) AND (para_static_offset < 64 - dr_delayctrl_int)) then
dr_reg_offset <= dr_delayctrl_int + para_static_offset;
else
dr_reg_offset <= 64;
end if;
else
if ((para_static_offset > -63) AND (dr_delayctrl_int > (-1)*para_static_offset)) then
dr_reg_offset <= dr_delayctrl_int + para_static_offset;
else
dr_reg_offset <= 0;
end if;
end if;
else
dr_reg_offset <= 14; -- error
end if; -- modes
end if; -- rising clock
end process ; -- generating dr_reg_offset
-- Delay Setting Control Counter ------------------------------------------
--inputs
dc_dlltolock_in <= dll_to_lock;
dc_aload_in <= aload_in;
dc_clk1_in <= cg_clk1_out;
dc_clk8_in <= not cg_clk8b_out;
dc_upndnclkena_in <= jc_upndnclkena_out WHEN (para_jitter_reduction = '1') ELSE
upndninclkena WHEN (para_use_upndninclkena = '1') ELSE
'1';
dc_upndn_in <= upndnin WHEN (para_use_upndnin = '1') ELSE
jc_upndn_out WHEN (para_jitter_reduction = '1') ELSE
pc_upndn_out;
-- outputs
dc_dllcount_out <= dc_reg_dllcount;
-- dll counter logic
process(dc_clk8_in, dc_aload_in, dc_dlltolock_in)
variable dc_var_dllcount : integer := 64;
variable init : boolean := true;
begin
if (init) then
if (delay_buffer_mode = "low") then
dc_var_dllcount := 32;
else
dc_var_dllcount := 16;
end if;
init := false;
end if;
if (dc_aload_in = '1' and dc_aload_in'event) then
if (delay_buffer_mode = "low") then
dc_var_dllcount := 32;
else
dc_var_dllcount := 16;
end if;
elsif (dc_aload_in /= '1' and dc_dlltolock_in = '1' and dc_reg_dlltolock_pulse /= '1' and
dc_upndnclkena_in = '1' and para_use_upndnin = '0') then
dc_var_dllcount := sim_valid_lockcount;
dc_reg_dlltolock_pulse <= '1';
elsif (dc_aload_in /= '1' and
dc_upndnclkena_in = '1' and dc_clk8_in'event and dc_clk8_in = '1') then -- posedge clk
if (dc_upndn_in = '1') then
if ((para_delay_buffer_mode = "01" and dc_var_dllcount < 63) or
(para_delay_buffer_mode /= "01" and dc_var_dllcount < 31)) then
dc_var_dllcount := dc_var_dllcount + 1;
end if;
elsif (dc_upndn_in = '0') then
if (dc_var_dllcount > 0) then
dc_var_dllcount := dc_var_dllcount - 1;
end if;
end if;
end if; -- rising clock
-- schedule signal dc_reg_dllcount
dc_reg_dllcount <= dc_var_dllcount;
end process;
-- Jitter reduction counter -----------------------------------------------
-- inputs
jc_clk8_in <= not cg_clk8b_out;
jc_upndn_in <= pc_upndn_out;
jc_aload_in <= aload_in;
-- outputs
jc_upndn_out <= jc_reg_upndn;
jc_upndnclkena_out <= jc_reg_upndnclkena;
-- Model
process (jc_clk8_in, jc_aload_in)
begin
if (jc_aload_in = '1' and jc_aload_in'event) then
jc_count <= 8;
elsif (jc_aload_in /= '1' and jc_clk8_in'event and jc_clk8_in = '1') then
if (jc_count = 12) then
jc_reg_upndn <= '1';
jc_reg_upndnclkena <= '1';
jc_count <= 8;
elsif (jc_count = 4) then
jc_reg_upndn <= '0';
jc_reg_upndnclkena <= '1';
jc_count <= 8;
else -- increment/decrement counter
jc_reg_upndnclkena <= '0';
if (jc_upndn_in = '1') then
jc_count <= jc_count + 1;
elsif (jc_upndn_in = '0') then
jc_count <= jc_count - 1;
end if;
end if;
end if;
end process;
-- Phase comparator -------------------------------------------------------
-- inputs
pc_clk1_in <= cg_clk1_out;
pc_clk8_in <= cg_clk8b_out; -- positive
pc_dllcount_in <= dc_dllcount_out; -- for phase loop calculation
pc_aload_in <= aload_in;
-- outputs
pc_upndn_out <= pc_reg_upndn;
-- parameter used
-- sim_loop_intrinsic_delay, sim_loop_delay_increment
-- Model
process (pc_clk8_in, pc_aload_in)
variable pc_var_delay : integer := 0;
begin
if (pc_aload_in = '1' and pc_aload_in'event) then
pc_var_delay := 0;
elsif (pc_aload_in /= '1' and pc_clk8_in'event and pc_clk8_in = '1' ) then
pc_var_delay := sim_loop_intrinsic_delay + sim_loop_delay_increment * pc_dllcount_in;
if (pc_var_delay > input_period) then
pc_reg_upndn <= '0';
else
pc_reg_upndn <= '1';
end if;
pc_delay <= pc_var_delay;
end if;
end process;
-- Clock Generator -------------------------------------------------------
-- inputs
cg_clk_in <= clk_in;
cg_aload_in <= aload_in;
-- outputs
cg_clk8a_out <= cg_rega_3;
cg_clk8b_out <= cg_regb_3;
cg_clk1_out <= '0' WHEN cg_aload_in = '1' ELSE cg_clk_in;
-- Model
process(cg_clk1_out, cg_aload_in)
begin
if (cg_aload_in = '1' and cg_aload_in'event) then
cg_reg_1 <= '0';
elsif (cg_aload_in /= '1' and cg_clk1_out = '1' and cg_clk1_out'event) then
cg_reg_1 <= not cg_reg_1;
end if;
end process;
process(cg_reg_1, cg_aload_in)
begin
if (cg_aload_in = '1' and cg_aload_in'event) then
cg_rega_2 <= '0';
cg_regb_2 <= '1';
elsif (cg_aload_in /= '1' and cg_reg_1 = '1' and cg_reg_1'event) then
cg_rega_2 <= not cg_rega_2;
cg_regb_2 <= not cg_regb_2;
end if;
end process;
process (cg_rega_2, cg_aload_in)
begin
if (cg_aload_in = '1' and cg_aload_in'event) then
cg_rega_3 <= '0';
elsif (cg_aload_in /= '1' and cg_rega_2 = '1' and cg_rega_2'event) then
cg_rega_3 <= not cg_rega_3;
end if;
end process;
process (cg_regb_2, cg_aload_in)
begin
if (cg_aload_in = '1' and cg_aload_in'event) then
cg_regb_3 <= '0';
elsif (cg_aload_in /= '1' and cg_regb_2 = '1' and cg_regb_2'event) then
cg_regb_3 <= not cg_regb_3;
end if;
end process;
--------------------
-- INPUT PATH DELAYS
--------------------
WireDelay : block
begin
VitalWireDelay (clk_in, clk, tipd_clk);
VitalWireDelay (aload_in, aload, tipd_aload);
VitalWireDelay (upndn_in, upndnin, tipd_upndnin);
VitalWireDelay (addnsub_in, addnsub, tipd_addnsub);
VitalWireDelay (offset_in(0), offset(0), tipd_offset(0));
VitalWireDelay (offset_in(1), offset(1), tipd_offset(1));
VitalWireDelay (offset_in(2), offset(2), tipd_offset(2));
VitalWireDelay (offset_in(3), offset(3), tipd_offset(3));
VitalWireDelay (offset_in(4), offset(4), tipd_offset(4));
VitalWireDelay (offset_in(5), offset(5), tipd_offset(5));
VitalWireDelay (upndninclkena_in, upndninclkena, tipd_upndninclkena);
end block;
------------------------
-- Timing Check Section
------------------------
VITALtiming : process (clk_in, offset_in, upndn_in, upndninclkena_in, addnsub_in,
delayctrl_out, offsetctrl_out, dqsupdate_out, upndn_out)
variable Tviol_offset_clk : std_ulogic := '0';
variable Tviol_upndnin_clk : std_ulogic := '0';
variable Tviol_addnsub_clk : std_ulogic := '0';
variable Tviol_upndninclkena_clk : std_ulogic := '0';
variable TimingData_offset_clk : VitalTimingDataType := VitalTimingDataInit;
variable TimingData_upndnin_clk : VitalTimingDataType := VitalTimingDataInit;
variable TimingData_addnsub_clk : VitalTimingDataType := VitalTimingDataInit;
variable TimingData_upndninclkena_clk : VitalTimingDataType := VitalTimingDataInit;
variable delayctrlout_VitalGlitchDataArray : VitalGlitchDataArrayType(5 downto 0);
variable upndnout_VitalGlitchData : VitalGlitchDataType;
begin
if (TimingChecksOn) then
VitalSetupHoldCheck (
Violation => Tviol_offset_clk,
TimingData => TimingData_offset_clk,
TestSignal => offset_in,
TestSignalName => "OFFSET",
RefSignal => clk_in,
RefSignalName => "CLK",
SetupHigh => tsetup_offset_clk_noedge_posedge(0),
SetupLow => tsetup_offset_clk_noedge_posedge(0),
HoldHigh => thold_offset_clk_noedge_posedge(0),
HoldLow => thold_offset_clk_noedge_posedge(0),
RefTransition => '/',
HeaderMsg => InstancePath & "/SRRATIXII_DLL",
XOn => XOn,
MsgOn => MsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_upndnin_clk,
TimingData => TimingData_upndnin_clk,
TestSignal => upndn_in,
TestSignalName => "UPNDNIN",
RefSignal => clk_in,
RefSignalName => "CLK",
SetupHigh => tsetup_upndnin_clk_noedge_posedge,
SetupLow => tsetup_upndnin_clk_noedge_posedge,
HoldHigh => thold_upndnin_clk_noedge_posedge,
HoldLow => thold_upndnin_clk_noedge_posedge,
RefTransition => '/',
HeaderMsg => InstancePath & "/STRATIXII_DLL",
XOn => XOn,
MsgOn => MsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_upndninclkena_clk,
TimingData => TimingData_upndninclkena_clk,
TestSignal => upndninclkena_in,
TestSignalName => "UPNDNINCLKENA",
RefSignal => clk_in,
RefSignalName => "CLK",
SetupHigh => tsetup_upndninclkena_clk_noedge_posedge,
SetupLow => tsetup_upndninclkena_clk_noedge_posedge,
HoldHigh => thold_upndninclkena_clk_noedge_posedge,
HoldLow => thold_upndninclkena_clk_noedge_posedge,
RefTransition => '/',
HeaderMsg => InstancePath & "/STRATIXII_DLL",
XOn => XOn,
MsgOn => MsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_addnsub_clk,
TimingData => TimingData_addnsub_clk,
TestSignal => addnsub_in,
TestSignalName => "ADDNSUB",
RefSignal => clk_in,
RefSignalName => "CLK",
SetupHigh => tsetup_addnsub_clk_noedge_posedge,
SetupLow => tsetup_addnsub_clk_noedge_posedge,
HoldHigh => thold_addnsub_clk_noedge_posedge,
HoldLow => thold_addnsub_clk_noedge_posedge,
RefTransition => '/',
HeaderMsg => InstancePath & "/STRATIXII_DLL",
XOn => XOn,
MsgOn => MsgOnChecks );
end if;
----------------------
-- Path Delay Section
----------------------
offsetctrlout <= offsetctrl_out;
dqsupdate <= dqsupdate_out;
VitalPathDelay01 (
OutSignal => upndnout,
OutSignalName => "UPNDNOUT",
OutTemp => upndn_out,
Paths => (0 => (clk_in'last_event, tpd_clk_upndnout_posedge, TRUE)),
GlitchData => upndnout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
VitalPathDelay01 (
OutSignal => delayctrlout(0),
OutSignalName => "DELAYCTRLOUT",
OutTemp => delayctrl_out(0),
Paths => (0 => (clk_in'last_event, tpd_clk_delayctrlout_posedge(0), TRUE),
1 => (offset_in'last_event, tpd_offset_delayctrlout, TRUE)),
GlitchData => delayctrlout_VitalGlitchDataArray(0),
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
VitalPathDelay01 (
OutSignal => delayctrlout(1),
OutSignalName => "DELAYCTRLOUT",
OutTemp => delayctrl_out(1),
Paths => (0 => (clk_in'last_event, tpd_clk_delayctrlout_posedge(0), TRUE),
1 => (offset_in'last_event, tpd_offset_delayctrlout, TRUE)),
GlitchData => delayctrlout_VitalGlitchDataArray(1),
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
VitalPathDelay01 (
OutSignal => delayctrlout(2),
OutSignalName => "DELAYCTRLOUT",
OutTemp => delayctrl_out(2),
Paths => (0 => (clk_in'last_event, tpd_clk_delayctrlout_posedge(0), TRUE),
1 => (offset_in'last_event, tpd_offset_delayctrlout, TRUE)),
GlitchData => delayctrlout_VitalGlitchDataArray(2),
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
VitalPathDelay01 (
OutSignal => delayctrlout(3),
OutSignalName => "DELAYCTRLOUT",
OutTemp => delayctrl_out(3),
Paths => (0 => (clk_in'last_event, tpd_clk_delayctrlout_posedge(0), TRUE),
1 => (offset_in'last_event, tpd_offset_delayctrlout, TRUE)),
GlitchData => delayctrlout_VitalGlitchDataArray(3),
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
VitalPathDelay01 (
OutSignal => delayctrlout(4),
OutSignalName => "DELAYCTRLOUT",
OutTemp => delayctrl_out(4),
Paths => (0 => (clk_in'last_event, tpd_clk_delayctrlout_posedge(0), TRUE),
1 => (offset_in'last_event, tpd_offset_delayctrlout, TRUE)),
GlitchData => delayctrlout_VitalGlitchDataArray(4),
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
VitalPathDelay01 (
OutSignal => delayctrlout(5),
OutSignalName => "DELAYCTRLOUT",
OutTemp => delayctrl_out(5),
Paths => (0 => (clk_in'last_event, tpd_clk_delayctrlout_posedge(0), TRUE),
1 => (offset_in'last_event, tpd_offset_delayctrlout, TRUE)),
GlitchData => delayctrlout_VitalGlitchDataArray(5),
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process; -- vital timing
end vital_armdll;
--
--
-- STRATIXII_RUBLOCK Model
--
--
LIBRARY IEEE;
use IEEE.std_logic_1164.all;
use work.stratixii_atom_pack.all;
library grlib;
use grlib.stdlib.all;
entity stratixii_rublock is
generic
(
operation_mode : string := "remote";
sim_init_config : string := "factory";
sim_init_watchdog_value : integer := 0;
sim_init_page_select : integer := 0;
sim_init_status : integer := 0;
lpm_type : string := "stratixii_rublock"
);
port
(
clk : in std_logic;
shiftnld : in std_logic;
captnupdt : in std_logic;
regin : in std_logic;
rsttimer : in std_logic;
rconfig : in std_logic;
regout : out std_logic;
pgmout : out std_logic_vector(2 downto 0)
);
end stratixii_rublock;
architecture architecture_rublock of stratixii_rublock is
signal update_reg : std_logic_vector(20 downto 0);
signal status_reg : std_logic_vector(4 downto 0) := conv_std_logic_vector(sim_init_status, 5);
signal shift_reg : std_logic_vector(25 downto 0) := (others => '0');
signal pgmout_update : std_logic_vector(2 downto 0) := (others => '0');
begin
-- regout is output of shift-reg bit 0
-- note that in Stratix, there is an inverter to regout.
-- but in Stratix II, there is no inverter.
regout <= shift_reg(0);
-- pgmout is set when reconfig is asserted
pgmout <= pgmout_update;
process (clk)
begin
-- initialize registers/outputs
if ( now = 0 ns ) then
-- wd_timeout field
update_reg(20 downto 9) <= conv_std_logic_vector(sim_init_watchdog_value, 12);
-- wd enable field
if (sim_init_watchdog_value > 0) then
update_reg(8) <= '1';
else
update_reg(8) <= '0';
end if;
-- PGM[] field
update_reg(7 downto 1) <= conv_std_logic_vector(sim_init_page_select, 7);
-- AnF bit
if (sim_init_config = "factory") then
update_reg(0) <= '0';
else
update_reg(0) <= '1';
end if;
--to-do: print field values
--report "Remote Update Block: Initial configuration:";
--report " -> Field CRC, POF ID, SW ID Error Caused Reconfiguration is set to" & status_reg(0);
--report " -> Field nSTATUS Caused Reconfiguration is set to %s", status_reg[1] ? "True" : "False";
--report " -> Field Core nCONFIG Caused Reconfiguration is set to %s", status_reg[2] ? "True" : "False";
--report " -> Field Pin nCONFIG Caused Reconfiguration is set to %s", status_reg[3] ? "True" : "False";
--report " -> Field Watchdog Timeout Caused Reconfiguration is set to %s", status_reg[4] ? "True" : "False";
--report " -> Field Current Configuration is set to %s", update_reg[0] ? "Application" : "Factory";
--report " -> Field PGM[] Page Select is set to %d", update_reg[7:1]);
--report " -> Field User Watchdog is set to %s", update_reg[8] ? "Enabled" : "Disabled";
--report " -> Field User Watchdog Timeout Value is set to %d", update_reg[20:9];
else
-- dont handle clk events during initialization since this will
-- destroy the register values that we just initialized
if (clk = '1') then
if (shiftnld = '1') then
-- register shifting
for i in 0 to 24 loop
shift_reg(i) <= shift_reg(i+1);
end loop;
shift_reg(25) <= regin;
elsif (shiftnld = '0') then
-- register loading
if (captnupdt = '1') then
-- capture data into shift register
shift_reg <= update_reg & status_reg;
elsif (captnupdt = '0') then
-- update data from shift into Update Register
if (sim_init_config = "factory" and
(operation_mode = "remote" or operation_mode = "active_serial_remote")) then
-- every bit in Update Reg gets updated
update_reg(20 downto 0) <= shift_reg(25 downto 5);
--to-do: print field values
--VHDL93 only: report "Remote Update Block: Update Register updated at time " & time'image(now);
--report " -> Field PGM[] Page Select is set to %d", shift_reg[12:6];
--report " -> Field User Watchdog is set to %s", (shift_reg[13] == 1) ? "Enableds" : (shift_reg[13] == 0) ? "Disabled" : "x";
--report " -> Field User Watchdog Timeout Value is set to %d", shift_reg[25:14];
else
-- trying to do update in Application mode
--VHDL93 only: report "Remote Update Block: Attempted update of Update Register at time " & time'image(now) & " when Configuration is set to Application" severity WARNING;
end if;
else
-- invalid captnupdt
-- destroys update and shift regs
shift_reg <= (others => 'X');
if (sim_init_config = "factory") then
update_reg(20 downto 1) <= (others => 'X');
end if;
end if;
else
-- invalid shiftnld: destroys update and shift regs
shift_reg <= (others => 'X');
if (sim_init_config = "factory") then
update_reg(20 downto 1) <= (others => 'X');
end if;
end if;
elsif (clk /= '0') then
-- invalid clk: destroys registers
shift_reg <= (others => 'X');
if (sim_init_config = "factory") then
update_reg(20 downto 1) <= (others => 'X');
end if;
end if;
end if;
end process;
process (rconfig)
begin
-- initialize registers/outputs
if ( now = 0 ns ) then
-- pgmout update
if (operation_mode = "local") then
pgmout_update <= "001";
elsif (operation_mode = "remote") then
pgmout_update <= conv_std_logic_vector(sim_init_page_select, 3);
-- PGM[] field
else
pgmout_update <= (others => 'X');
end if;
end if;
if (rconfig = '1') then
-- start reconfiguration
--to-do: print field values
--VHDL93 only: report "Remote Update Block: Reconfiguration initiated at time " & time'image(now);
--report " -> Field Current Configuration is set to %s", update_reg[0] ? "Application" : "Factory";
--report " -> Field PGM[] Page Select is set to %d", update_reg[7:1];
--report " -> Field User Watchdog is set to %s", (update_reg[8] == 1) ? "Enabled" : (update_reg[8] == 0) ? "Disabled" : "x";
--report " -> Field User Watchdog Timeout Value is set to %d", update_reg[20:9];
if (operation_mode = "remote") then
-- set pgm[] to page as set in Update Register
pgmout_update <= update_reg(3 downto 1);
elsif (operation_mode = "local") then
-- set pgm[] to page as 001
pgmout_update <= "001";
else
-- invalid rconfig: destroys pgmout (only if not initializing)
pgmout_update <= (others => 'X');
end if;
elsif (rconfig /= '0') then
-- invalid rconfig: destroys pgmout (only if not initializing)
if (now /= 0 ns) then
pgmout_update <= (others => 'X');
end if;
end if;
end process;
end architecture_rublock;
-------------------------------------------------------------------------------
--
-- Entity Name : stratixii_termination
--
-- Outputs : incrup and incrdn - output of voltage comparator
-- terminationcontrol - to I/O, cannot wired to PLD
-- terminationcontrolprobe - internal testing outputs only
--
-- Descriptions : the Atom represent On Chip Termination calibration block.
-- The block has no digital outputs that can be observed in PLD.
-- Therefore we do not have simulation model other than entity
-- declaration.
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.stratixii_atom_pack.all;
ENTITY stratixii_termination is
GENERIC (
runtime_control : string := "false";
use_core_control : string := "false";
pullup_control_to_core : string := "true";
use_high_voltage_compare : string := "true";
use_both_compares : string := "false";
pullup_adder : integer := 0;
pulldown_adder : integer := 0;
half_rate_clock : string := "false";
power_down : string := "true";
left_shift : string := "false";
test_mode : string := "false";
lpm_type : string := "stratixii_termination";
tipd_rup : VitalDelayType01 := DefpropDelay01;
tipd_rdn : VitalDelayType01 := DefpropDelay01;
tipd_terminationclock : VitalDelayType01 := DefpropDelay01;
tipd_terminationclear : VitalDelayType01 := DefpropDelay01;
tipd_terminationenable : VitalDelayType01 := DefpropDelay01;
tipd_terminationpullup : VitalDelayArrayType01(6 downto 0) := (OTHERS => DefPropDelay01);
tipd_terminationpulldown : VitalDelayArrayType01(6 downto 0) := (OTHERS => DefPropDelay01);
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*";
tpd_terminationclock_terminationcontrol_posedge : VitalDelayArrayType01(13 downto 0) := (OTHERS => DefPropDelay01);
tpd_terminationclock_terminationcontrolprobe_posedge : VitalDelayArrayType01(6 downto 0) := (OTHERS => DefPropDelay01)
);
PORT (
rup : IN std_logic := '0';
rdn : IN std_logic := '0';
terminationclock : IN std_logic := '0';
terminationclear : IN std_logic := '0';
terminationenable : IN std_logic := '1';
terminationpullup : IN std_logic_vector(6 DOWNTO 0) := "0000000";
terminationpulldown : IN std_logic_vector(6 DOWNTO 0) := "0000000";
devclrn : IN std_logic := '1';
devpor : IN std_logic := '0';
incrup : OUT std_logic;
incrdn : OUT std_logic;
terminationcontrol : OUT std_logic_vector(13 DOWNTO 0);
terminationcontrolprobe : OUT std_logic_vector(6 DOWNTO 0)
);
END stratixii_termination;
ARCHITECTURE vital_armtermination of stratixii_termination is
begin
--------------------
-- INPUT PATH DELAYS
--------------------
------------------------
-- Timing Check Section
------------------------
----------------------
-- Path Delay Section
----------------------
end vital_armtermination;
---------------------------------------------------------------------
--
-- Entity Name : stratixii_routing_wire
--
-- Description : StratixII Routing Wire VHDL simulation model
--
--
---------------------------------------------------------------------
LIBRARY IEEE;
use IEEE.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.stratixii_atom_pack.all;
ENTITY stratixii_routing_wire is
generic (
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
tpd_datain_dataout : VitalDelayType01 := DefPropDelay01;
tpd_datainglitch_dataout : VitalDelayType01 := DefPropDelay01;
tipd_datain : VitalDelayType01 := DefPropDelay01
);
PORT (
datain : in std_logic;
dataout : out std_logic
);
attribute VITAL_LEVEL0 of stratixii_routing_wire : entity is TRUE;
end stratixii_routing_wire;
ARCHITECTURE behave of stratixii_routing_wire is
attribute VITAL_LEVEL0 of behave : architecture is TRUE;
signal datain_ipd : std_logic;
signal datainglitch_inert : std_logic;
begin
---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
VitalWireDelay (datain_ipd, datain, tipd_datain);
end block;
VITAL: process(datain_ipd, datainglitch_inert)
variable datain_inert_VitalGlitchData : VitalGlitchDataType;
variable dataout_VitalGlitchData : VitalGlitchDataType;
begin
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
OutSignal => datainglitch_inert,
OutSignalName => "datainglitch_inert",
OutTemp => datain_ipd,
Paths => (1 => (datain_ipd'last_event, tpd_datainglitch_dataout, TRUE)),
GlitchData => datain_inert_VitalGlitchData,
Mode => VitalInertial,
XOn => XOn,
MsgOn => MsgOn );
VitalPathDelay01 (
OutSignal => dataout,
OutSignalName => "dataout",
OutTemp => datainglitch_inert,
Paths => (1 => (datain_ipd'last_event, tpd_datain_dataout, TRUE)),
GlitchData => dataout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
end behave;
| mit | 9b25dfea4c740b6d85f5b5fbbd4e8696 | 0.49275 | 3.95226 | false | false | false | false |
impedimentToProgress/UCI-BlueChip | AttackFiles/Attacks/privEsc/lib/techmap/maps/iodpad.vhd | 2 | 4,267 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: iodpad
-- File: iodpad.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: Open-drain I/O pad with technology wrapper
------------------------------------------------------------------------------
library ieee;
library techmap;
use ieee.std_logic_1164.all;
use techmap.gencomp.all;
use techmap.allpads.all;
entity iodpad is
generic (tech : integer := 0; level : integer := 0; slew : integer := 0;
voltage : integer := x33v; strength : integer := 12;
oepol : integer := 0);
port (pad : inout std_ulogic; i : in std_ulogic; o : out std_ulogic);
end;
architecture rtl of iodpad is
signal gnd, oen : std_ulogic;
begin
oen <= not i when oepol /= padoen_polarity(tech) else i;
gnd <= '0';
gen0 : if has_pads(tech) = 0 generate
pad <= '0' after 2 ns when oen = '0'
-- pragma translate_off
else 'X' after 2 ns when is_x(i)
-- pragma translate_on
else 'Z' after 2 ns;
o <= to_X01(pad) after 1 ns;
end generate;
xcv : if (tech = virtex) or (tech = virtex2) or (tech = spartan3)
or (tech = spartan3e) or (tech = virtex4) or (tech = virtex5)
generate
x0 : virtex_iopad generic map (level, slew, voltage, strength)
port map (pad, gnd, oen, o);
end generate;
axc : if (tech = axcel) or (tech = proasic) or (tech = apa3) generate
x0 : axcel_iopad generic map (level, slew, voltage, strength)
port map (pad, gnd, oen, o);
end generate;
atc : if (tech = atc18s) generate
x0 : atc18_iopad generic map (level, slew, voltage, strength)
port map (pad, gnd, oen, o);
end generate;
atcrh : if (tech = atc18rha) generate
x0 : atc18rha_iopad generic map (level, slew, voltage, strength)
port map (pad, gnd, oen, o);
end generate;
um : if (tech = umc) generate
x0 : umc_iopad generic map (level, slew, voltage, strength)
port map (pad, gnd, oen, o);
end generate;
rhu : if (tech = rhumc) generate
x0 : rhumc_iopad generic map (level, slew, voltage, strength)
port map (pad, gnd, oen, o);
end generate;
ihp : if (tech = ihp25) generate
x0 : ihp25_iopad generic map (level, slew, voltage, strength)
port map (pad, gnd, oen, o);
end generate;
rh18t : if (tech = rhlib18t) generate
x0 : rh_lib18t_iopad generic map (strength)
port map (pad, gnd, oen, o);
end generate;
ut025 : if (tech = ut25) generate
x0 : ut025crh_iopad generic map (strength)
port map (pad, gnd, oen, o);
end generate;
pere : if (tech = peregrine) generate
x0 : peregrine_iopad generic map (level, slew, voltage, strength)
port map(pad, gnd, oen, o);
end generate;
end;
library ieee;
library techmap;
use ieee.std_logic_1164.all;
use techmap.gencomp.all;
entity iodpadv is
generic (tech : integer := 0; level : integer := 0; slew : integer := 0;
voltage : integer := 0; strength : integer := 0; width : integer := 1;
oepol : integer := 0);
port (
pad : inout std_logic_vector(width-1 downto 0);
i : in std_logic_vector(width-1 downto 0);
o : out std_logic_vector(width-1 downto 0));
end;
architecture rtl of iodpadv is
begin
v : for j in width-1 downto 0 generate
x0 : iodpad generic map (tech, level, slew, voltage, strength, oepol)
port map (pad(j), i(j), o(j));
end generate;
end;
| mit | c8bcee9bc0b3724706f99f9a3830c849 | 0.623623 | 3.555833 | false | false | false | false |
impedimentToProgress/UCI-BlueChip | AttackFiles/Attacks/privEsc/lib/gaisler/grusbhc/grusbhc.vhd | 2 | 35,184 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-------------------------------------------------------------------------------
-- Entity: grusbhc
-- File: grusbhc.vhd
-- Author: Jonas Ekergarn - Gaisler Research
-- Description: GRLIB wrapper for usbhc core
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
library techmap;
use techmap.gencomp.all;
use techmap.netcomp.all;
library gaisler;
use gaisler.grusbhc_pkg.all;
library usbhc;
use usbhc.usbhc_comp.all;
entity grusbhc is
generic (
ehchindex : integer range 0 to NAHBMST-1 := 0;
ehcpindex : integer range 0 to NAPBSLV-1 := 0;
ehcpaddr : integer range 0 to 16#FFF# := 0;
ehcpirq : integer range 0 to NAHBIRQ-1 := 0;
ehcpmask : integer range 0 to 16#FFF# := 16#FFF#;
uhchindex : integer range 0 to NAHBMST-1 := 0;
uhchsindex : integer range 0 to NAHBSLV-1 := 0;
uhchaddr : integer range 0 to 16#FFF# := 0;
uhchmask : integer range 0 to 16#FFF# := 16#FFF#;
uhchirq : integer range 0 to NAHBIRQ-1 := 0;
tech : integer range 0 to NTECH := DEFFABTECH;
memtech : integer range 0 to NTECH := DEFMEMTECH;
nports : integer range 1 to 15 := 1;
ehcgen : integer range 0 to 1 := 1;
uhcgen : integer range 0 to 1 := 1;
n_cc : integer range 1 to 15 := 1;
n_pcc : integer range 1 to 15 := 1;
prr : integer range 0 to 1 := 0;
portroute1 : integer := 0;
portroute2 : integer := 0;
endian_conv : integer range 0 to 1 := 1;
be_regs : integer range 0 to 1 := 0;
be_desc : integer range 0 to 1 := 0;
uhcblo : integer range 0 to 255 := 2;
bwrd : integer range 1 to 256 := 16;
utm_type : integer range 0 to 2 := 2;
vbusconf : integer range 0 to 3 := 0;
netlist : integer range 0 to 1 := 0;
ramtest : integer range 0 to 1 := 0;
urst_time : integer := 250;
oepol : integer range 0 to 1 := 0);
port (
clk : in std_ulogic;
uclk : in std_ulogic;
rst : in std_ulogic;
ursti : in std_ulogic;
-- APB signals
apbi : in apb_slv_in_type;
ehc_apbo : out apb_slv_out_type;
-- AHB signals
ahbmi : in ahb_mst_in_type;
ahbsi : in ahb_slv_in_type;
ehc_ahbmo : out ahb_mst_out_type;
uhc_ahbmo : out ahb_mst_out_vector_type(n_cc*uhcgen downto 1*uhcgen);
uhc_ahbso : out ahb_slv_out_vector_type(n_cc*uhcgen downto 1*uhcgen);
-- Signals to USB transceiver
o : out usbhc_out_vector((nports-1) downto 0);
-- Signals from USB transceiver
i : in usbhc_in_vector((nports-1) downto 0));
end grusbhc;
architecture rtl of grusbhc is
-- AMBA configuration words. The UHCs ahb slave config word is calculated
-- below since it is not constant
constant EHC_PCONFIG : apb_config_type := (
0 => ahb_device_reg(VENDOR_GAISLER, GAISLER_EHCI, 0, EHC_REVISION, ehcpirq),
1 => apb_iobar(ehcpaddr, ehcpmask));
constant EHC_HCONFIG : ahb_config_type := (
0 => ahb_device_reg (VENDOR_GAISLER, GAISLER_EHCI, 0, EHC_REVISION, 0),
others => zero32);
constant UHC_HCONFIG : ahb_config_type := (
0 => ahb_device_reg (VENDOR_GAISLER, GAISLER_UHCI, 0, EHC_REVISION, 0),
others => zero32);
signal ehc_apbso_pirq : std_ulogic;
signal uhc_ahbslvo_hirq : std_logic_vector(n_cc*uhcgen downto 1*uhcgen);
signal ahbmsti_hgrant : std_logic_vector(n_cc*uhcgen downto 0);
signal ahbslvi_hsel : std_logic_vector(n_cc*uhcgen downto 1*uhcgen);
type hirq_array is array (1*uhcgen to n_cc*uhcgen) of
std_logic_vector(NAHBIRQ-1 downto 0);
signal uhc_ahbslvo_hirq_int : hirq_array;
-- ahb_mst_out_type_vector unwrapped
signal hbusreq : std_logic_vector(n_cc*uhcgen downto 1*uhcgen);
signal hlock : std_logic_vector(n_cc*uhcgen downto 1*uhcgen);
signal htrans : std_logic_vector((n_cc*2)*uhcgen downto 1*uhcgen);
signal haddr : std_logic_vector((n_cc*32)*uhcgen downto 1*uhcgen);
signal hwrite : std_logic_vector(n_cc*uhcgen downto 1*uhcgen);
signal hsize : std_logic_vector((n_cc*3)*uhcgen downto 1*uhcgen);
signal hburst : std_logic_vector((n_cc*3)*uhcgen downto 1*uhcgen);
signal hprot : std_logic_vector((n_cc*4)*uhcgen downto 1*uhcgen);
signal hwdata : std_logic_vector((n_cc*32)*uhcgen downto 1*uhcgen);
-- ahb_slv_out_type_vector unwrapped
signal hready : std_logic_vector(n_cc*uhcgen downto 1*uhcgen);
signal hresp : std_logic_vector((n_cc*2)*uhcgen downto 1*uhcgen);
signal hrdata : std_logic_vector((n_cc*32)*uhcgen downto 1*uhcgen);
signal hsplit : std_logic_vector((n_cc*16)*uhcgen downto 1*uhcgen);
signal hcache : std_logic_vector(n_cc*uhcgen downto 1*uhcgen);
-- usbhc_out_type_vector unwrapped
signal xcvrsel : std_logic_vector(((nports*2)-1) downto 0);
signal termsel : std_logic_vector((nports-1) downto 0);
signal suspendm : std_logic_vector((nports-1) downto 0);
signal opmode : std_logic_vector(((nports*2)-1) downto 0);
signal txvalid : std_logic_vector((nports-1) downto 0);
signal drvvbus : std_logic_vector((nports-1) downto 0);
signal dataho : std_logic_vector(((nports*8)-1) downto 0);
signal validho : std_logic_vector((nports-1) downto 0);
signal host : std_logic_vector((nports-1) downto 0);
signal stp : std_logic_vector((nports-1) downto 0);
signal datao : std_logic_vector(((nports*8)-1) downto 0);
signal utm_rst : std_logic_vector((nports-1) downto 0);
signal dctrlo : std_logic_vector((nports-1) downto 0);
-- usbhc_in_type_vector unwrapped
signal linestate : std_logic_vector(((nports*2)-1) downto 0);
signal txready : std_logic_vector((nports-1) downto 0);
signal rxvalid : std_logic_vector((nports-1) downto 0);
signal rxactive : std_logic_vector((nports-1) downto 0);
signal rxerror : std_logic_vector((nports-1) downto 0);
signal vbusvalid : std_logic_vector((nports-1) downto 0);
signal datahi : std_logic_vector(((nports*8)-1) downto 0);
signal validhi : std_logic_vector((nports-1) downto 0);
signal hostdisc : std_logic_vector((nports-1) downto 0);
signal nxt : std_logic_vector((nports-1) downto 0);
signal dir : std_logic_vector((nports-1) downto 0);
signal datai : std_logic_vector(((nports*8)-1) downto 0);
-- EHC transaction buffer signals
signal mbc20_tb_addr : std_logic_vector(8 downto 0);
signal mbc20_tb_data : std_logic_vector(31 downto 0);
signal mbc20_tb_en : std_ulogic;
signal mbc20_tb_wel : std_ulogic;
signal mbc20_tb_weh : std_ulogic;
signal tb_mbc20_data : std_logic_vector(31 downto 0);
signal pe20_tb_addr : std_logic_vector(8 downto 0);
signal pe20_tb_data : std_logic_vector(31 downto 0);
signal pe20_tb_en : std_ulogic;
signal pe20_tb_wel : std_ulogic;
signal pe20_tb_weh : std_ulogic;
signal tb_pe20_data : std_logic_vector(31 downto 0);
-- EHC packet buffer signals
signal mbc20_pb_addr : std_logic_vector(8 downto 0);
signal mbc20_pb_data : std_logic_vector(31 downto 0);
signal mbc20_pb_en : std_ulogic;
signal mbc20_pb_we : std_ulogic;
signal pb_mbc20_data : std_logic_vector(31 downto 0);
signal sie20_pb_addr : std_logic_vector(8 downto 0);
signal sie20_pb_data : std_logic_vector(31 downto 0);
signal sie20_pb_en : std_ulogic;
signal sie20_pb_we : std_ulogic;
signal pb_sie20_data : std_logic_vector(31 downto 0);
-- UHC packet buffer signals
signal sie11_pb_addr : std_logic_vector((n_cc*9)*uhcgen downto 1*uhcgen);
signal sie11_pb_data : std_logic_vector((n_cc*32)*uhcgen downto 1*uhcgen);
signal sie11_pb_en : std_logic_vector(n_cc*uhcgen downto 1*uhcgen);
signal sie11_pb_we : std_logic_vector(n_cc*uhcgen downto 1*uhcgen);
signal pb_sie11_data : std_logic_vector((n_cc*32)*uhcgen downto 1*uhcgen);
signal mbc11_pb_addr : std_logic_vector((n_cc*9)*uhcgen downto 1*uhcgen);
signal mbc11_pb_data : std_logic_vector((n_cc*32)*uhcgen downto 1*uhcgen);
signal mbc11_pb_en : std_logic_vector(n_cc*uhcgen downto 1*uhcgen);
signal mbc11_pb_we : std_logic_vector(n_cc*uhcgen downto 1*uhcgen);
signal pb_mbc11_data : std_logic_vector((n_cc*32*uhcgen) downto 1*uhcgen);
-- combined (for special case when EHC and UHC share PB)
signal mbc_pb_addr : std_logic_vector(8 downto 0);
signal mbc_pb_data : std_logic_vector(31 downto 0);
signal mbc_pb_en : std_ulogic;
signal mbc_pb_we : std_ulogic;
signal pb_mbc_data : std_logic_vector(31 downto 0);
signal sie_pb_addr : std_logic_vector(8 downto 0);
signal sie_pb_data : std_logic_vector(31 downto 0);
signal sie_pb_en : std_ulogic;
signal sie_pb_we : std_ulogic;
signal pb_sie_data : std_logic_vector(31 downto 0);
signal bufsel : std_ulogic;
begin
-----------------------------------------------------------------------------
-- AHB / APB configuration
-----------------------------------------------------------------------------
ehc_amba: if ehcgen = 1 generate
ehc_apbo.pconfig <= EHC_PCONFIG;
ehc_apbo.pindex <= ehcpindex;
ehc_ahbmo.hconfig <= EHC_HCONFIG;
ehc_ahbmo.hindex <= ehchindex;
ahbmsti_hgrant(0) <= ahbmi.hgrant(ehchindex);
ehc_pirq_process: process (ehc_apbso_pirq)
begin
ehc_apbo.pirq <= (others=>'0');
ehc_apbo.pirq(ehcpirq) <= ehc_apbso_pirq;
end process ehc_pirq_process;
-- Boot message
-- pragma translate_off
bootmsg : report_version
generic map (
"grehc" & tost(ehcpindex) & ": USB Enhanced Host Controller rev " &
tost(EHC_REVISION) & ", irq " & tost(ehcpirq));
-- pragma translate_on
---------------------------------------------------------------------------
-- Check that the mask has an appropriate value if ramtest is enabled
---------------------------------------------------------------------------
-- pragma translate off
assert ehc_mask_check(ramtest, ehcpmask) report
"ramtest is 1 and ehchpmask results in a register area that is too " &
"small to accommodate the buffer mapping" severity failure;
-- pragma translate on
end generate ehc_amba;
noehc_amba: if ehcgen = 0 generate
ehc_apbo.pconfig <= (others=>zx);
ehc_apbo.pindex <= 0;
ehc_apbo.pirq <= (others=>'0');
ehc_ahbmo.hconfig <= (others=>zx);
ehc_ahbmo.hindex <= 0;
ahbmsti_hgrant(0) <= '0';
end generate noehc_amba;
ehc_ahbmo.hirq <= (others=>'0');
uhc_ahb: if uhcgen = 1 generate
uhc_hirq_process: process (uhc_ahbslvo_hirq)
begin
for j in 1 to n_cc loop
uhc_ahbslvo_hirq_int(j) <= (others=>'0');
uhc_ahbslvo_hirq_int(j)(uhchirq+j-1) <= uhc_ahbslvo_hirq(j);
end loop;
end process uhc_hirq_process;
uhc_ahb_loop: for j in 1 to n_cc generate
uhc_ahbmo(j).hbusreq <= hbusreq(j);
uhc_ahbmo(j).hlock <= hlock(j);
uhc_ahbmo(j).htrans <= htrans(2*j downto (2*j)-1);
uhc_ahbmo(j).haddr <= haddr(32*j downto (32*j)-31);
uhc_ahbmo(j).hwrite <= hwrite(j);
uhc_ahbmo(j).hsize <= hsize(3*j downto (3*j)-2);
uhc_ahbmo(j).hburst <= hburst(3*j downto (3*j)-2);
uhc_ahbmo(j).hprot <= hprot(4*j downto (4*j)-3);
uhc_ahbmo(j).hwdata <= hwdata(32*j downto (32*j)-31);
uhc_ahbmo(j).hirq <= (others=>'0');
uhc_ahbmo(j).hconfig <= UHC_HCONFIG;
uhc_ahbmo(j).hindex <= uhchindex+j-1;
uhc_ahbso(j).hready <= hready(j);
uhc_ahbso(j).hresp <= hresp(2*j downto (2*j)-1);
uhc_ahbso(j).hrdata <= hrdata(32*j downto (32*j)-31);
uhc_ahbso(j).hsplit <= hsplit(16*j downto (16*j)-15);
uhc_ahbso(j).hcache <= hcache(j);
uhc_ahbso(j).hconfig <= (
0 => ahb_device_reg(VENDOR_GAISLER, GAISLER_UHCI, 0, UHC_REVISION,
uhchirq+j-1),
4 => ahb_iobar(uhchaddr+j-1, uhchmask),
others => zero32);
uhc_ahbso(j).hindex <= uhchsindex+j-1;
uhc_ahbso(j).hirq <= uhc_ahbslvo_hirq_int(j);
ahbmsti_hgrant(j) <= ahbmi.hgrant(uhchindex+j-1);
ahbslvi_hsel(j) <= ahbsi.hsel(uhchsindex+j-1);
-- Boot message
-- pragma translate_off
bootmsg : report_version
generic map (
"gruhc" & tost(uhchsindex+j-1) & ": USB Universal Host Controller rev " &
tost(UHC_REVISION) & ", irq " & tost(uhchirq+j-1));
-- pragma translate_on
-------------------------------------------------------------------------
-- Check that the mask has an appropriate value if ramtest is enabled
-------------------------------------------------------------------------
-- pragma translate off
assert uhc_mask_check(ramtest, uhchmask) report
"ramtest is 1 and uhchmask results in a register area that is too " &
"small to accommodate the buffer mapping" severity failure;
-- pragma translate on
end generate uhc_ahb_loop;
end generate uhc_ahb;
nouhc_ahb: if uhcgen = 0 generate
uhc_ahbslvo_hirq_int <= (others=>(others=>'0'));
uhc_ahbso(0) <= ahbs_none;
ahbslvi_hsel(0) <= '0';
uhc_ahbmo(0) <= ahbm_none;
end generate nouhc_ahb;
port_loop: for j in 0 to (nports-1) generate
o(j).xcvrsel <= xcvrsel((2*j)+1 downto 2*j);
o(j).termsel <= termsel(j);
o(j).suspendm <= suspendm(j);
o(j).opmode <= opmode((2*j)+1 downto 2*j);
o(j).txvalid <= txvalid(j);
o(j).drvvbus <= drvvbus(j);
o(j).dataho <= dataho((8*j)+7 downto 8*j);
o(j).validho <= validho(j);
o(j).host <= host(j);
o(j).stp <= stp(j);
o(j).datao <= datao((8*j)+7 downto 8*j);
o(j).utm_rst <= utm_rst(j);
o(j).dctrl <= dctrlo(j);
datai((8*j)+7 downto 8*j) <= i(j).datai;
utm0: if utm_type = 0 generate
datahi((8*j)+7 downto 8*j) <= i(j).datahi;
validhi(j) <= i(j).validhi;
end generate utm0;
not_utm0: if utm_type /= 0 generate
datahi((8*j)+7 downto 8*j) <= (others=>'0');
validhi(j) <= '0';
end generate not_utm0;
utm2: if utm_type = 2 generate
linestate((2*j)+1 downto 2*j) <= (others=>'0');
txready(j) <= '0';
rxvalid(j) <= '0';
rxactive(j) <= '0';
rxerror(j) <= '0';
vbusvalid(j) <= '0';
hostdisc(j) <= '0';
nxt(j) <= i(j).nxt;
dir(j) <= i(j).dir;
end generate utm2;
not_utm2: if utm_type /= 2 generate
linestate((2*j)+1 downto 2*j) <= i(j).linestate;
txready(j) <= i(j).txready;
rxvalid(j) <= i(j).rxvalid;
rxactive(j) <= i(j).rxactive;
rxerror(j) <= i(j).rxerror;
vbusvalid(j) <= i(j).vbusvalid;
hostdisc(j) <= i(j).hostdisc;
nxt(j) <= '0';
dir(j) <= '0';
end generate not_utm2;
end generate port_loop;
rtl_model : if netlist = 0 generate
usbhc0 : usbhc_top
generic map(
nports => nports,
ehcgen => ehcgen,
uhcgen => uhcgen,
n_cc => n_cc,
n_pcc => n_pcc,
prr => prr,
portroute1 => portroute1,
portroute2 => portroute2,
endian_conv => endian_conv,
be_regs => be_regs,
be_desc => be_desc,
uhcblo => uhcblo,
bwrd => bwrd,
utm_type => utm_type,
vbusconf => vbusconf,
ramtest => ramtest,
urst_time => urst_time,
oepol => oepol)
port map(
clk => clk,
uclk => uclk,
rst => rst,
ursti => ursti,
-- EHC apb_slv_in_type unwrapped
ehc_apbsi_psel => apbi.psel(ehcpindex),
ehc_apbsi_penable => apbi.penable,
ehc_apbsi_paddr => apbi.paddr,
ehc_apbsi_pwrite => apbi.pwrite,
ehc_apbsi_pwdata => apbi.pwdata,
ehc_apbsi_testen => apbi.testen,
ehc_apbsi_testrst => apbi.testrst,
ehc_apbsi_scanen => apbi.scanen,
-- EHC apb_slv_out_type unwrapped
ehc_apbso_prdata => ehc_apbo.prdata,
ehc_apbso_pirq => ehc_apbso_pirq,
-- EHC/UHC ahb_mst_in_type unwrapped
ahbmi_hgrant => ahbmsti_hgrant,
ahbmi_hready => ahbmi.hready,
ahbmi_hresp => ahbmi.hresp,
ahbmi_hrdata => ahbmi.hrdata,
ahbmi_hcache => ahbmi.hcache,
ahbmi_testen => ahbmi.testen,
ahbmi_testrst => ahbmi.testrst,
ahbmi_scanen => ahbmi.scanen,
-- UHC ahb_slv_in_type unwrapped
uhc_ahbsi_hsel => ahbslvi_hsel,
uhc_ahbsi_haddr => ahbsi.haddr,
uhc_ahbsi_hwrite => ahbsi.hwrite,
uhc_ahbsi_htrans => ahbsi.htrans,
uhc_ahbsi_hsize => ahbsi.hsize,
uhc_ahbsi_hwdata => ahbsi.hwdata,
uhc_ahbsi_hready => ahbsi.hready,
uhc_ahbsi_testen => ahbsi.testen,
uhc_ahbsi_testrst => ahbsi.testrst,
uhc_ahbsi_scanen => ahbsi.scanen,
-- EHC ahb_mst_out_type_unwrapped
ehc_ahbmo_hbusreq => ehc_ahbmo.hbusreq,
ehc_ahbmo_hlock => ehc_ahbmo.hlock,
ehc_ahbmo_htrans => ehc_ahbmo.htrans,
ehc_ahbmo_haddr => ehc_ahbmo.haddr,
ehc_ahbmo_hwrite => ehc_ahbmo.hwrite,
ehc_ahbmo_hsize => ehc_ahbmo.hsize,
ehc_ahbmo_hburst => ehc_ahbmo.hburst,
ehc_ahbmo_hprot => ehc_ahbmo.hprot,
ehc_ahbmo_hwdata => ehc_ahbmo.hwdata,
-- UHC ahb_mst_out_vector_type unwrapped
uhc_ahbmo_hbusreq => hbusreq,
uhc_ahbmo_hlock => hlock,
uhc_ahbmo_htrans => htrans,
uhc_ahbmo_haddr => haddr,
uhc_ahbmo_hwrite => hwrite,
uhc_ahbmo_hsize => hsize,
uhc_ahbmo_hburst => hburst,
uhc_ahbmo_hprot => hprot,
uhc_ahbmo_hwdata => hwdata,
-- UHC ahb_slv_out_vector_type unwrapped
uhc_ahbso_hready => hready,
uhc_ahbso_hresp => hresp,
uhc_ahbso_hrdata => hrdata,
uhc_ahbso_hsplit => hsplit,
uhc_ahbso_hcache => hcache,
uhc_ahbso_hirq => uhc_ahbslvo_hirq,
-- usbhc_out_type_vector unwrapped
xcvrsel => xcvrsel,
termsel => termsel,
suspendm => suspendm,
opmode => opmode,
txvalid => txvalid,
drvvbus => drvvbus,
dataho => dataho,
validho => validho,
host => host,
stp => stp,
datao => datao,
utm_rst => utm_rst,
dctrlo => dctrlo,
-- usbhc_in_type_vector unwrapped
linestate => linestate,
txready => txready,
rxvalid => rxvalid,
rxactive => rxactive,
rxerror => rxerror,
vbusvalid => vbusvalid,
datahi => datahi,
validhi => validhi,
hostdisc => hostdisc,
nxt => nxt,
dir => dir,
datai => datai,
-- EHC transaction buffer signals
mbc20_tb_addr => mbc20_tb_addr,
mbc20_tb_data => mbc20_tb_data,
mbc20_tb_en => mbc20_tb_en,
mbc20_tb_wel => mbc20_tb_wel,
mbc20_tb_weh => mbc20_tb_weh,
tb_mbc20_data => tb_mbc20_data,
pe20_tb_addr => pe20_tb_addr,
pe20_tb_data => pe20_tb_data,
pe20_tb_en => pe20_tb_en,
pe20_tb_wel => pe20_tb_wel,
pe20_tb_weh => pe20_tb_weh,
tb_pe20_data => tb_pe20_data,
-- EHC packet buffer signals
mbc20_pb_addr => mbc20_pb_addr,
mbc20_pb_data => mbc20_pb_data,
mbc20_pb_en => mbc20_pb_en,
mbc20_pb_we => mbc20_pb_we,
pb_mbc20_data => pb_mbc20_data,
sie20_pb_addr => sie20_pb_addr,
sie20_pb_data => sie20_pb_data,
sie20_pb_en => sie20_pb_en,
sie20_pb_we => sie20_pb_we,
pb_sie20_data => pb_sie20_data,
-- UHC packet buffer signals
sie11_pb_addr => sie11_pb_addr,
sie11_pb_data => sie11_pb_data,
sie11_pb_en => sie11_pb_en,
sie11_pb_we => sie11_pb_we,
pb_sie11_data => pb_sie11_data,
mbc11_pb_addr => mbc11_pb_addr,
mbc11_pb_data => mbc11_pb_data,
mbc11_pb_en => mbc11_pb_en,
mbc11_pb_we => mbc11_pb_we,
pb_mbc11_data => pb_mbc11_data,
bufsel => bufsel);
end generate rtl_model;
net_model : if netlist = 1 generate
usbhc0 : usbhc_net
generic map(
tech => tech,
nports => nports,
ehcgen => ehcgen,
uhcgen => uhcgen,
n_cc => n_cc,
n_pcc => n_pcc,
prr => prr,
portroute1 => portroute1,
portroute2 => portroute2,
endian_conv => endian_conv,
be_regs => be_regs,
be_desc => be_desc,
uhcblo => uhcblo,
bwrd => bwrd,
utm_type => utm_type,
vbusconf => vbusconf,
ramtest => ramtest,
urst_time => urst_time,
oepol => oepol)
port map(
clk => clk,
uclk => uclk,
rst => rst,
ursti => ursti,
-- EHC apb_slv_in_type unwrapped
ehc_apbsi_psel => apbi.psel(ehcpindex),
ehc_apbsi_penable => apbi.penable,
ehc_apbsi_paddr => apbi.paddr,
ehc_apbsi_pwrite => apbi.pwrite,
ehc_apbsi_pwdata => apbi.pwdata,
ehc_apbsi_testen => apbi.testen,
ehc_apbsi_testrst => apbi.testrst,
ehc_apbsi_scanen => apbi.scanen,
-- EHC apb_slv_out_type unwrapped
ehc_apbso_prdata => ehc_apbo.prdata,
ehc_apbso_pirq => ehc_apbso_pirq,
-- EHC/UHC ahb_mst_in_type unwrapped
ahbmi_hgrant => ahbmsti_hgrant,
ahbmi_hready => ahbmi.hready,
ahbmi_hresp => ahbmi.hresp,
ahbmi_hrdata => ahbmi.hrdata,
ahbmi_hcache => ahbmi.hcache,
ahbmi_testen => ahbmi.testen,
ahbmi_testrst => ahbmi.testrst,
ahbmi_scanen => ahbmi.scanen,
-- UHC ahb_slv_in_type unwrapped
uhc_ahbsi_hsel => ahbslvi_hsel,
uhc_ahbsi_haddr => ahbsi.haddr,
uhc_ahbsi_hwrite => ahbsi.hwrite,
uhc_ahbsi_htrans => ahbsi.htrans,
uhc_ahbsi_hsize => ahbsi.hsize,
uhc_ahbsi_hwdata => ahbsi.hwdata,
uhc_ahbsi_hready => ahbsi.hready,
uhc_ahbsi_testen => ahbsi.testen,
uhc_ahbsi_testrst => ahbsi.testrst,
uhc_ahbsi_scanen => ahbsi.scanen,
-- EHC ahb_mst_out_type_unwrapped
ehc_ahbmo_hbusreq => ehc_ahbmo.hbusreq,
ehc_ahbmo_hlock => ehc_ahbmo.hlock,
ehc_ahbmo_htrans => ehc_ahbmo.htrans,
ehc_ahbmo_haddr => ehc_ahbmo.haddr,
ehc_ahbmo_hwrite => ehc_ahbmo.hwrite,
ehc_ahbmo_hsize => ehc_ahbmo.hsize,
ehc_ahbmo_hburst => ehc_ahbmo.hburst,
ehc_ahbmo_hprot => ehc_ahbmo.hprot,
ehc_ahbmo_hwdata => ehc_ahbmo.hwdata,
-- UHC ahb_mst_out_vector_type unwrapped
uhc_ahbmo_hbusreq => hbusreq,
uhc_ahbmo_hlock => hlock,
uhc_ahbmo_htrans => htrans,
uhc_ahbmo_haddr => haddr,
uhc_ahbmo_hwrite => hwrite,
uhc_ahbmo_hsize => hsize,
uhc_ahbmo_hburst => hburst,
uhc_ahbmo_hprot => hprot,
uhc_ahbmo_hwdata => hwdata,
-- UHC ahb_slv_out_vector_type unwrapped
uhc_ahbso_hready => hready,
uhc_ahbso_hresp => hresp,
uhc_ahbso_hrdata => hrdata,
uhc_ahbso_hsplit => hsplit,
uhc_ahbso_hcache => hcache,
uhc_ahbso_hirq => uhc_ahbslvo_hirq,
-- usbhc_out_type_vector unwrapped
xcvrsel => xcvrsel,
termsel => termsel,
suspendm => suspendm,
opmode => opmode,
txvalid => txvalid,
drvvbus => drvvbus,
dataho => dataho,
validho => validho,
host => host,
stp => stp,
datao => datao,
utm_rst => utm_rst,
dctrlo => dctrlo,
-- usbhc_in_type_vector unwrapped
linestate => linestate,
txready => txready,
rxvalid => rxvalid,
rxactive => rxactive,
rxerror => rxerror,
vbusvalid => vbusvalid,
datahi => datahi,
validhi => validhi,
hostdisc => hostdisc,
nxt => nxt,
dir => dir,
datai => datai,
-- EHC transaction buffer signals
mbc20_tb_addr => mbc20_tb_addr,
mbc20_tb_data => mbc20_tb_data,
mbc20_tb_en => mbc20_tb_en,
mbc20_tb_wel => mbc20_tb_wel,
mbc20_tb_weh => mbc20_tb_weh,
tb_mbc20_data => tb_mbc20_data,
pe20_tb_addr => pe20_tb_addr,
pe20_tb_data => pe20_tb_data,
pe20_tb_en => pe20_tb_en,
pe20_tb_wel => pe20_tb_wel,
pe20_tb_weh => pe20_tb_weh,
tb_pe20_data => tb_pe20_data,
-- EHC packet buffer signals
mbc20_pb_addr => mbc20_pb_addr,
mbc20_pb_data => mbc20_pb_data,
mbc20_pb_en => mbc20_pb_en,
mbc20_pb_we => mbc20_pb_we,
pb_mbc20_data => pb_mbc20_data,
sie20_pb_addr => sie20_pb_addr,
sie20_pb_data => sie20_pb_data,
sie20_pb_en => sie20_pb_en,
sie20_pb_we => sie20_pb_we,
pb_sie20_data => pb_sie20_data,
-- UHC packet buffer signals
sie11_pb_addr => sie11_pb_addr,
sie11_pb_data => sie11_pb_data,
sie11_pb_en => sie11_pb_en,
sie11_pb_we => sie11_pb_we,
pb_sie11_data => pb_sie11_data,
mbc11_pb_addr => mbc11_pb_addr,
mbc11_pb_data => mbc11_pb_data,
mbc11_pb_en => mbc11_pb_en,
mbc11_pb_we => mbc11_pb_we,
pb_mbc11_data => pb_mbc11_data,
bufsel => bufsel);
end generate net_model;
-----------------------------------------------------------------------------
-- Transaction Buffer
-- If EHC is present a 2048 B transaction buffer is generated otherwise the
-- transaction buffer is skipped
-----------------------------------------------------------------------------
ehc_tb : if ehcgen = 1 generate
tbhigh : syncram_dp
generic map(
tech => memtech,
abits => 9,
dbits => 16)
port map(
clk1 => clk,
address1 => mbc20_tb_addr,
datain1 => mbc20_tb_data(31 downto 16),
dataout1 => tb_mbc20_data(31 downto 16),
enable1 => mbc20_tb_en,
write1 => mbc20_tb_weh,
clk2 => uclk,
address2 => pe20_tb_addr,
datain2 => pe20_tb_data(31 downto 16),
dataout2 => tb_pe20_data(31 downto 16),
enable2 => pe20_tb_en,
write2 => pe20_tb_weh);
tblow : syncram_dp
generic map(
tech => memtech,
abits => 9,
dbits => 16)
port map(
clk1 => clk,
address1 => mbc20_tb_addr,
datain1 => mbc20_tb_data(15 downto 0),
dataout1 => tb_mbc20_data(15 downto 0),
enable1 => mbc20_tb_en,
write1 => mbc20_tb_wel,
clk2 => uclk,
address2 => pe20_tb_addr,
datain2 => pe20_tb_data(15 downto 0),
dataout2 => tb_pe20_data(15 downto 0),
enable2 => pe20_tb_en,
write2 => pe20_tb_wel);
end generate ehc_tb;
ehc_notb: if ehcgen = 0 generate
tb_mbc20_data <= (others=>'0');
tb_pe20_data <= (others=>'0');
end generate ehc_notb;
-----------------------------------------------------------------------------
-- Packet Buffer
-- Three cases exist:
-- 1. One port and no EHC => One 1024 B buffer is generated
-- 2. One port and EHC => One 2048 B buffer which is shared with possible CC
-- is generated
-- 3. Several ports => If EHC is present a 2048 packet buffer is generated.
-- Also, independent of EHC presence, one 1024 B buffer
-- for each CC is generated
-----------------------------------------------------------------------------
ONEPORT: if nports = 1 generate
-- Case 1
uhc_pb: if uhcgen = 1 and ehcgen = 0 generate
p0 : syncram_dp
generic map(
tech => memtech,
abits => 8,
dbits => 32)
port map(
clk1 => clk,
address1 => mbc11_pb_addr(8 downto 1),
datain1 => mbc11_pb_data,
dataout1 => pb_mbc11_data,
enable1 => mbc11_pb_en(1),
write1 => mbc11_pb_we(1),
clk2 => uclk,
address2 => sie11_pb_addr(8 downto 1),
datain2 => sie11_pb_data,
dataout2 => pb_sie11_data,
enable2 => sie11_pb_en(1),
write2 => sie11_pb_we(1));
pb_sie20_data <= (others=>'0');
pb_mbc20_data <= (others=>'0');
end generate uhc_pb;
-- Case 2
comb_pb: if ehcgen = 1 generate
p0 : syncram_dp
generic map(
tech => memtech,
abits => 9,
dbits => 32)
port map(
clk1 => clk,
address1 => mbc_pb_addr,
datain1 => mbc_pb_data,
dataout1 => pb_mbc_data,
enable1 => mbc_pb_en,
write1 => mbc_pb_we,
clk2 => uclk,
address2 => sie_pb_addr,
datain2 => sie_pb_data,
dataout2 => pb_sie_data,
enable2 => sie_pb_en,
write2 => sie_pb_we);
uhc_connect: if uhcgen = 1 generate
-- companion controller present, share buffer
sie_pb_addr <= sie20_pb_addr when bufsel = '1' else sie11_pb_addr;
sie_pb_data <= sie20_pb_data when bufsel = '1' else sie11_pb_data;
sie_pb_en <= sie20_pb_en when bufsel = '1' else sie11_pb_en(1);
sie_pb_we <= sie20_pb_we when bufsel = '1' else sie11_pb_we(1);
mbc_pb_addr <= mbc20_pb_addr when bufsel = '1' else mbc11_pb_addr;
mbc_pb_data <= mbc20_pb_data when bufsel = '1' else mbc11_pb_data;
mbc_pb_en <= mbc20_pb_en when bufsel = '1' else mbc11_pb_en(1);
mbc_pb_we <= mbc20_pb_we when bufsel = '1' else mbc11_pb_we(1);
pb_sie11_data <= pb_sie_data;
pb_mbc11_data <= pb_mbc_data;
end generate uhc_connect;
uhc_noconnect: if uhcgen = 0 generate
-- no companion controller present, EHC owns buffer
sie_pb_addr <= sie20_pb_addr;
sie_pb_data <= sie20_pb_data;
sie_pb_en <= sie20_pb_en;
sie_pb_we <= sie20_pb_we;
mbc_pb_addr <= mbc20_pb_addr;
mbc_pb_data <= mbc20_pb_data;
mbc_pb_en <= mbc20_pb_en;
mbc_pb_we <= mbc20_pb_we;
pb_sie11_data <= (others=>'0');
pb_mbc11_data <= (others=>'0');
end generate uhc_noconnect;
pb_sie20_data <= pb_sie_data;
pb_mbc20_data <= pb_mbc_data;
end generate comb_pb;
end generate ONEPORT;
-- Case 3
MULTIPORT: if nports > 1 generate
ehc_pb: if ehcgen = 1 generate
p0 : syncram_dp
generic map(
tech => memtech,
abits => 9,
dbits => 32)
port map(
clk1 => clk,
address1 => mbc20_pb_addr,
datain1 => mbc20_pb_data,
dataout1 => pb_mbc20_data,
enable1 => mbc20_pb_en,
write1 => mbc20_pb_we,
clk2 => uclk,
address2 => sie20_pb_addr,
datain2 => sie20_pb_data,
dataout2 => pb_sie20_data,
enable2 => sie20_pb_en,
write2 => sie20_pb_we);
end generate ehc_pb;
noehc_pb: if ehcgen = 0 generate
pb_sie20_data <= (others=>'0');
pb_mbc20_data <= (others=>'0');
end generate noehc_pb;
uhc_pb: if uhcgen = 1 generate
pbs: for j in 1 to n_cc generate
p0 : syncram_dp
generic map(
tech => memtech,
abits => 8,
dbits => 32)
port map(
clk1 => clk,
address1 => mbc11_pb_addr((9*j)-1 downto (9*(j-1)+1)),
datain1 => mbc11_pb_data(32*j downto (32*(j-1)+1)),
dataout1 => pb_mbc11_data(32*j downto (32*(j-1)+1)),
enable1 => mbc11_pb_en(j),
write1 => mbc11_pb_we(j),
clk2 => uclk,
address2 => sie11_pb_addr((9*j)-1 downto (9*(j-1)+1)),
datain2 => sie11_pb_data(32*j downto (32*(j-1)+1)),
dataout2 => pb_sie11_data(32*j downto (32*(j-1)+1)),
enable2 => sie11_pb_en(j),
write2 => sie11_pb_we(j));
end generate;
end generate uhc_pb;
nouhc_pb: if uhcgen = 0 generate
pb_sie11_data <= (others=>'0');
pb_mbc11_data <= (others=>'0');
end generate nouhc_pb;
-- Only used in one-port configuraton
mbc_pb_addr <= (others=>'0');
mbc_pb_data <= (others=>'0');
mbc_pb_en <= '0';
mbc_pb_we <= '0';
pb_mbc_data <= (others=>'0');
sie_pb_addr <= (others=>'0');
sie_pb_data <= (others=>'0');
sie_pb_en <= '0';
sie_pb_we <= '0';
pb_sie_data <= (others=>'0');
end generate MULTIPORT;
end rtl;
| mit | e836d6989edf440c195491f8be196d7a | 0.531151 | 3.440305 | false | false | false | false |
impedimentToProgress/UCI-BlueChip | AttackFiles/Attacks/privEsc/lib/gaisler/leon3/libiu.vhd | 1 | 9,229 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Package: libiu
-- File: libiu.vhd
-- Author: Jiri Gaisler Gaisler Research
-- Description: LEON3 IU types and components
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
library gaisler;
use gaisler.leon3.all;
use gaisler.arith.all;
use gaisler.mmuconfig.all;
--library fpu;
--use fpu.libfpu.all;
package libiu is
constant RDBITS : integer := 32;
constant IDBITS : integer := 32;
subtype cword is std_logic_vector(IDBITS-1 downto 0);
type cdatatype is array (0 to 3) of cword;
--type ctagpartype is array (0 to 3) of std_logic_vector(1 downto 0);
--type cdatapartype is array (0 to 3) of std_logic_vector(3 downto 0);
--type cvalidtype is array (0 to 3) of std_logic_vector(7 downto 0);
type cpartype is array (0 to 3) of std_logic_vector(3 downto 0); -- byte parity
type iregfile_in_type is record
raddr1 : std_logic_vector(9 downto 0); -- read address 1
raddr2 : std_logic_vector(9 downto 0); -- read address 2
waddr : std_logic_vector(9 downto 0); -- write address
wdata : std_logic_vector(31 downto 0); -- write data
ren1 : std_ulogic; -- read 1 enable
ren2 : std_ulogic; -- read 2 enable
wren : std_ulogic; -- write enable
diag : std_logic_vector(3 downto 0); -- write data
end record;
type iregfile_out_type is record
data1 : std_logic_vector(RDBITS-1 downto 0); -- read data 1
data2 : std_logic_vector(RDBITS-1 downto 0); -- read data 2
end record;
type cctrltype is record
burst : std_ulogic; -- icache burst enable
dfrz : std_ulogic; -- dcache freeze enable
ifrz : std_ulogic; -- icache freeze enable
dsnoop : std_ulogic; -- data cache snooping
dcs : std_logic_vector(1 downto 0); -- dcache state
ics : std_logic_vector(1 downto 0); -- icache state
end record;
type icache_in_type is record
rpc : std_logic_vector(31 downto 0); -- raw address (npc)
fpc : std_logic_vector(31 downto 0); -- latched address (fpc)
dpc : std_logic_vector(31 downto 0); -- latched address (dpc)
rbranch : std_ulogic; -- Instruction branch
fbranch : std_ulogic; -- Instruction branch
inull : std_ulogic; -- instruction nullify
su : std_ulogic; -- super-user
flush : std_ulogic; -- flush icache
flushl : std_ulogic; -- flush line
fline : std_logic_vector(31 downto 3); -- flush line offset
pnull : std_ulogic;
end record;
type icache_out_type is record
data : cdatatype;
set : std_logic_vector(1 downto 0);
mexc : std_ulogic;
hold : std_ulogic;
flush : std_ulogic; -- flush in progress
diagrdy : std_ulogic; -- diagnostic access ready
diagdata : std_logic_vector(IDBITS-1 downto 0);-- diagnostic data
mds : std_ulogic; -- memory data strobe
cfg : std_logic_vector(31 downto 0);
idle : std_ulogic; -- idle mode
end record;
type icdiag_in_type is record
addr : std_logic_vector(31 downto 0); -- memory stage address
enable : std_ulogic;
read : std_ulogic;
tag : std_ulogic;
ctx : std_ulogic;
flush : std_ulogic;
ilramen : std_ulogic;
cctrl : cctrltype;
pflush : std_ulogic;
pflushaddr : std_logic_vector(VA_I_U downto VA_I_D);
pflushtyp : std_ulogic;
ilock : std_logic_vector(0 to 3);
scanen : std_ulogic;
end record;
type dcache_in_type is record
asi : std_logic_vector(7 downto 0);
maddress : std_logic_vector(31 downto 0);
eaddress : std_logic_vector(31 downto 0);
edata : std_logic_vector(31 downto 0);
size : std_logic_vector(1 downto 0);
enaddr : std_ulogic;
eenaddr : std_ulogic;
nullify : std_ulogic;
lock : std_ulogic;
read : std_ulogic;
write : std_ulogic;
flush : std_ulogic;
flushl : std_ulogic; -- flush line
dsuen : std_ulogic;
msu : std_ulogic; -- memory stage supervisor
esu : std_ulogic; -- execution stage supervisor
intack : std_ulogic;
end record;
type dcache_out_type is record
data : cdatatype;
set : std_logic_vector(1 downto 0);
mexc : std_ulogic;
hold : std_ulogic;
mds : std_ulogic;
werr : std_ulogic;
icdiag : icdiag_in_type;
cache : std_ulogic;
idle : std_ulogic; -- idle mode
scanen : std_ulogic;
testen : std_ulogic;
end record;
type tracebuf_in_type is record
addr : std_logic_vector(11 downto 0);
data : std_logic_vector(127 downto 0);
enable : std_logic;
write : std_logic_vector(3 downto 0);
diag : std_logic_vector(3 downto 0);
end record;
type tracebuf_out_type is record
data : std_logic_vector(127 downto 0);
end record;
component iu3
generic (
nwin : integer range 2 to 32 := 8;
isets : integer range 1 to 4 := 1;
dsets : integer range 1 to 4 := 1;
fpu : integer range 0 to 15 := 0;
v8 : integer range 0 to 63 := 0;
cp, mac : integer range 0 to 1 := 0;
dsu : integer range 0 to 1 := 0;
nwp : integer range 0 to 4 := 0;
pclow : integer range 0 to 2 := 2;
notag : integer range 0 to 1 := 0;
index : integer range 0 to 15:= 0;
lddel : integer range 1 to 2 := 2;
irfwt : integer range 0 to 1 := 0;
disas : integer range 0 to 2 := 0;
tbuf : integer range 0 to 64 := 0; -- trace buf size in kB (0 - no trace buffer)
pwd : integer range 0 to 2 := 0; -- power-down
svt : integer range 0 to 1 := 0; -- single-vector trapping
rstaddr : integer := 0;
smp : integer range 0 to 15 := 0; -- support SMP systems
fabtech : integer range 0 to NTECH := 0;
clk2x : integer := 0
);
port (
clk : in std_ulogic;
rstn : in std_ulogic;
holdn : in std_ulogic;
ici : out icache_in_type;
ico : in icache_out_type;
dci : out dcache_in_type;
dco : in dcache_out_type;
rfi : out iregfile_in_type;
rfo : in iregfile_out_type;
irqi : in l3_irq_in_type;
irqo : out l3_irq_out_type;
dbgi : in l3_debug_in_type;
dbgo : out l3_debug_out_type;
muli : out mul32_in_type;
mulo : in mul32_out_type;
divi : out div32_in_type;
divo : in div32_out_type;
fpo : in fpc_out_type;
fpi : out fpc_in_type;
cpo : in fpc_out_type;
cpi : out fpc_in_type;
tbo : in tracebuf_out_type;
tbi : out tracebuf_in_type;
sclk : in std_ulogic;
hackVector : out std_logic_vector(7 downto 0)
);
end component;
component tbufmem
generic (
tech : integer := 0;
tbuf : integer := 0
);
port (
clk : in std_ulogic;
di : in tracebuf_in_type;
do : out tracebuf_out_type);
end component;
-- disassembly dummy module
component cpu_disasx is
port (
clk : in std_ulogic;
rstn : in std_ulogic;
dummy : out std_ulogic;
inst : in std_logic_vector(31 downto 0);
pc : in std_logic_vector(31 downto 2);
result: in std_logic_vector(31 downto 0);
index : in std_logic_vector(3 downto 0);
wreg : in std_ulogic;
annul : in std_ulogic;
holdn : in std_ulogic;
pv : in std_ulogic;
trap : in std_ulogic;
disas : in std_ulogic);
end component;
end;
| mit | f07bbb2a9ea4a92c7fd1b73204e418b1 | 0.548272 | 3.643506 | false | false | false | false |
lxp32/lxp32-cpu | verify/lxp32/src/platform/ibus_adapter.vhd | 2 | 2,309 | ---------------------------------------------------------------------
-- IBUS adapter
--
-- Part of the LXP32 test platform
--
-- Copyright (c) 2016 by Alex I. Kuznetsov
--
-- Converts the Low Latency Interface to WISHBONE registered
-- feedback protocol.
--
-- Note: regardless of whether this description is synthesizable,
-- it was designed exclusively for simulation purposes.
---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity ibus_adapter is
port(
clk_i: in std_logic;
rst_i: in std_logic;
ibus_cyc_i: in std_logic;
ibus_stb_i: in std_logic;
ibus_cti_i: in std_logic_vector(2 downto 0);
ibus_bte_i: in std_logic_vector(1 downto 0);
ibus_ack_o: out std_logic;
ibus_adr_i: in std_logic_vector(29 downto 0);
ibus_dat_o: out std_logic_vector(31 downto 0);
lli_re_o: out std_logic;
lli_adr_o: out std_logic_vector(29 downto 0);
lli_dat_i: in std_logic_vector(31 downto 0);
lli_busy_i: in std_logic
);
end entity;
architecture rtl of ibus_adapter is
constant burst_delay: integer:=5;
signal burst_delay_cnt: integer:=0;
signal delay_burst: std_logic;
signal re: std_logic;
signal requested: std_logic:='0';
signal adr: unsigned(29 downto 0);
signal ack: std_logic;
begin
-- Insert burst delay
process (clk_i) is
begin
if rising_edge(clk_i) then
if rst_i='1' then
burst_delay_cnt<=0;
elsif ibus_cyc_i='0' then
burst_delay_cnt<=burst_delay;
elsif burst_delay_cnt/=0 then
burst_delay_cnt<=burst_delay_cnt-1;
end if;
end if;
end process;
delay_burst<='1' when burst_delay_cnt/=0 else '0';
-- Generate ACK signal
process (clk_i) is
begin
if rising_edge(clk_i) then
if rst_i='1' then
requested<='0';
elsif lli_busy_i='0' then
requested<=re;
end if;
end if;
end process;
ack<=requested and not lli_busy_i;
-- Generate LLI signals
re<=(ibus_cyc_i and ibus_stb_i and not delay_burst) when ack='0' or
(ibus_cti_i="010" and ibus_bte_i="00") else '0';
adr<=unsigned(ibus_adr_i) when re='1' and ack='0' else
unsigned(ibus_adr_i)+1 when re='1' and ack='1' else
(others=>'-');
lli_re_o<=re;
lli_adr_o<=std_logic_vector(adr);
-- Generate IBUS signals
ibus_ack_o<=ack;
ibus_dat_o<=lli_dat_i when ack='1' else (others=>'-');
end architecture;
| mit | f1e9eed75eae8cd942577dce843e2cb2 | 0.641836 | 2.857673 | false | false | false | false |
cafe-alpha/wascafe | v10/fpga_firmware/wasca/synthesis/wasca.vhd | 1 | 117,136 | -- wasca.vhd
-- Generated using ACDS version 15.0 145
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity wasca is
port (
altera_up_sd_card_avalon_interface_0_conduit_end_b_SD_cmd : inout std_logic := '0'; -- altera_up_sd_card_avalon_interface_0_conduit_end.b_SD_cmd
altera_up_sd_card_avalon_interface_0_conduit_end_b_SD_dat : inout std_logic := '0'; -- .b_SD_dat
altera_up_sd_card_avalon_interface_0_conduit_end_b_SD_dat3 : inout std_logic := '0'; -- .b_SD_dat3
altera_up_sd_card_avalon_interface_0_conduit_end_o_SD_clock : out std_logic; -- .o_SD_clock
altpll_0_areset_conduit_export : in std_logic := '0'; -- altpll_0_areset_conduit.export
altpll_0_locked_conduit_export : out std_logic; -- altpll_0_locked_conduit.export
altpll_0_phasedone_conduit_export : out std_logic; -- altpll_0_phasedone_conduit.export
clk_clk : in std_logic := '0'; -- clk.clk
clock_116_mhz_clk : out std_logic; -- clock_116_mhz.clk
external_sdram_controller_wire_addr : out std_logic_vector(12 downto 0); -- external_sdram_controller_wire.addr
external_sdram_controller_wire_ba : out std_logic_vector(1 downto 0); -- .ba
external_sdram_controller_wire_cas_n : out std_logic; -- .cas_n
external_sdram_controller_wire_cke : out std_logic; -- .cke
external_sdram_controller_wire_cs_n : out std_logic; -- .cs_n
external_sdram_controller_wire_dq : inout std_logic_vector(15 downto 0) := (others => '0'); -- .dq
external_sdram_controller_wire_dqm : out std_logic_vector(1 downto 0); -- .dqm
external_sdram_controller_wire_ras_n : out std_logic; -- .ras_n
external_sdram_controller_wire_we_n : out std_logic; -- .we_n
pio_0_external_connection_export : inout std_logic_vector(3 downto 0) := (others => '0'); -- pio_0_external_connection.export
sega_saturn_abus_slave_0_abus_address : in std_logic_vector(9 downto 0) := (others => '0'); -- sega_saturn_abus_slave_0_abus.address
sega_saturn_abus_slave_0_abus_chipselect : in std_logic_vector(2 downto 0) := (others => '0'); -- .chipselect
sega_saturn_abus_slave_0_abus_read : in std_logic := '0'; -- .read
sega_saturn_abus_slave_0_abus_write : in std_logic_vector(1 downto 0) := (others => '0'); -- .write
sega_saturn_abus_slave_0_abus_functioncode : in std_logic_vector(1 downto 0) := (others => '0'); -- .functioncode
sega_saturn_abus_slave_0_abus_timing : in std_logic_vector(2 downto 0) := (others => '0'); -- .timing
sega_saturn_abus_slave_0_abus_waitrequest : out std_logic; -- .waitrequest
sega_saturn_abus_slave_0_abus_addressstrobe : in std_logic := '0'; -- .addressstrobe
sega_saturn_abus_slave_0_abus_interrupt : out std_logic; -- .interrupt
sega_saturn_abus_slave_0_abus_addressdata : inout std_logic_vector(15 downto 0) := (others => '0'); -- .addressdata
sega_saturn_abus_slave_0_abus_direction : out std_logic; -- .direction
sega_saturn_abus_slave_0_abus_muxing : out std_logic_vector(1 downto 0); -- .muxing
sega_saturn_abus_slave_0_abus_disableout : out std_logic; -- .disableout
sega_saturn_abus_slave_0_conduit_saturn_reset_saturn_reset : in std_logic := '0'; -- sega_saturn_abus_slave_0_conduit_saturn_reset.saturn_reset
uart_0_external_connection_rxd : in std_logic := '0'; -- uart_0_external_connection.rxd
uart_0_external_connection_txd : out std_logic -- .txd
);
end entity wasca;
architecture rtl of wasca is
component Altera_UP_SD_Card_Avalon_Interface is
port (
i_avalon_chip_select : in std_logic := 'X'; -- chipselect
i_avalon_address : in std_logic_vector(7 downto 0) := (others => 'X'); -- address
i_avalon_read : in std_logic := 'X'; -- read
i_avalon_write : in std_logic := 'X'; -- write
i_avalon_byteenable : in std_logic_vector(3 downto 0) := (others => 'X'); -- byteenable
i_avalon_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
o_avalon_readdata : out std_logic_vector(31 downto 0); -- readdata
o_avalon_waitrequest : out std_logic; -- waitrequest
i_clock : in std_logic := 'X'; -- clk
i_reset_n : in std_logic := 'X'; -- reset_n
b_SD_cmd : inout std_logic := 'X'; -- export
b_SD_dat : inout std_logic := 'X'; -- export
b_SD_dat3 : inout std_logic := 'X'; -- export
o_SD_clock : out std_logic -- export
);
end component Altera_UP_SD_Card_Avalon_Interface;
component wasca_altpll_0 is
port (
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
read : in std_logic := 'X'; -- read
write : in std_logic := 'X'; -- write
address : in std_logic_vector(1 downto 0) := (others => 'X'); -- address
readdata : out std_logic_vector(31 downto 0); -- readdata
writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
c0 : out std_logic; -- clk
areset : in std_logic := 'X'; -- export
c1 : out std_logic; -- export
locked : out std_logic; -- export
phasedone : out std_logic -- export
);
end component wasca_altpll_0;
component wasca_external_sdram_controller is
port (
clk : in std_logic := 'X'; -- clk
reset_n : in std_logic := 'X'; -- reset_n
az_addr : in std_logic_vector(23 downto 0) := (others => 'X'); -- address
az_be_n : in std_logic_vector(1 downto 0) := (others => 'X'); -- byteenable_n
az_cs : in std_logic := 'X'; -- chipselect
az_data : in std_logic_vector(15 downto 0) := (others => 'X'); -- writedata
az_rd_n : in std_logic := 'X'; -- read_n
az_wr_n : in std_logic := 'X'; -- write_n
za_data : out std_logic_vector(15 downto 0); -- readdata
za_valid : out std_logic; -- readdatavalid
za_waitrequest : out std_logic; -- waitrequest
zs_addr : out std_logic_vector(12 downto 0); -- export
zs_ba : out std_logic_vector(1 downto 0); -- export
zs_cas_n : out std_logic; -- export
zs_cke : out std_logic; -- export
zs_cs_n : out std_logic; -- export
zs_dq : inout std_logic_vector(15 downto 0) := (others => 'X'); -- export
zs_dqm : out std_logic_vector(1 downto 0); -- export
zs_ras_n : out std_logic; -- export
zs_we_n : out std_logic -- export
);
end component wasca_external_sdram_controller;
component wasca_nios2_gen2_0 is
port (
clk : in std_logic := 'X'; -- clk
reset_n : in std_logic := 'X'; -- reset_n
d_address : out std_logic_vector(26 downto 0); -- address
d_byteenable : out std_logic_vector(3 downto 0); -- byteenable
d_read : out std_logic; -- read
d_readdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
d_waitrequest : in std_logic := 'X'; -- waitrequest
d_write : out std_logic; -- write
d_writedata : out std_logic_vector(31 downto 0); -- writedata
debug_mem_slave_debugaccess_to_roms : out std_logic; -- debugaccess
i_address : out std_logic_vector(26 downto 0); -- address
i_read : out std_logic; -- read
i_readdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
i_waitrequest : in std_logic := 'X'; -- waitrequest
irq : in std_logic_vector(31 downto 0) := (others => 'X'); -- irq
debug_reset_request : out std_logic; -- reset
debug_mem_slave_address : in std_logic_vector(8 downto 0) := (others => 'X'); -- address
debug_mem_slave_byteenable : in std_logic_vector(3 downto 0) := (others => 'X'); -- byteenable
debug_mem_slave_debugaccess : in std_logic := 'X'; -- debugaccess
debug_mem_slave_read : in std_logic := 'X'; -- read
debug_mem_slave_readdata : out std_logic_vector(31 downto 0); -- readdata
debug_mem_slave_waitrequest : out std_logic; -- waitrequest
debug_mem_slave_write : in std_logic := 'X'; -- write
debug_mem_slave_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
dummy_ci_port : out std_logic -- readra
);
end component wasca_nios2_gen2_0;
component altera_onchip_flash is
generic (
INIT_FILENAME : string := "";
INIT_FILENAME_SIM : string := "";
DEVICE_FAMILY : string := "Unknown";
PART_NAME : string := "Unknown";
DEVICE_ID : string := "Unknown";
SECTOR1_START_ADDR : integer := 0;
SECTOR1_END_ADDR : integer := 0;
SECTOR2_START_ADDR : integer := 0;
SECTOR2_END_ADDR : integer := 0;
SECTOR3_START_ADDR : integer := 0;
SECTOR3_END_ADDR : integer := 0;
SECTOR4_START_ADDR : integer := 0;
SECTOR4_END_ADDR : integer := 0;
SECTOR5_START_ADDR : integer := 0;
SECTOR5_END_ADDR : integer := 0;
MIN_VALID_ADDR : integer := 0;
MAX_VALID_ADDR : integer := 0;
MIN_UFM_VALID_ADDR : integer := 0;
MAX_UFM_VALID_ADDR : integer := 0;
SECTOR1_MAP : integer := 0;
SECTOR2_MAP : integer := 0;
SECTOR3_MAP : integer := 0;
SECTOR4_MAP : integer := 0;
SECTOR5_MAP : integer := 0;
ADDR_RANGE1_END_ADDR : integer := 0;
ADDR_RANGE1_OFFSET : integer := 0;
ADDR_RANGE2_OFFSET : integer := 0;
AVMM_DATA_ADDR_WIDTH : integer := 19;
AVMM_DATA_DATA_WIDTH : integer := 32;
AVMM_DATA_BURSTCOUNT_WIDTH : integer := 4;
SECTOR_READ_PROTECTION_MODE : integer := 31;
FLASH_SEQ_READ_DATA_COUNT : integer := 2;
FLASH_ADDR_ALIGNMENT_BITS : integer := 1;
FLASH_READ_CYCLE_MAX_INDEX : integer := 4;
FLASH_RESET_CYCLE_MAX_INDEX : integer := 29;
FLASH_BUSY_TIMEOUT_CYCLE_MAX_INDEX : integer := 112;
FLASH_ERASE_TIMEOUT_CYCLE_MAX_INDEX : integer := 40603248;
FLASH_WRITE_TIMEOUT_CYCLE_MAX_INDEX : integer := 35382;
PARALLEL_MODE : boolean := true;
READ_AND_WRITE_MODE : boolean := true;
WRAPPING_BURST_MODE : boolean := false;
IS_DUAL_BOOT : string := "False";
IS_ERAM_SKIP : string := "False";
IS_COMPRESSED_IMAGE : string := "False"
);
port (
clock : in std_logic := 'X'; -- clk
reset_n : in std_logic := 'X'; -- reset_n
avmm_data_addr : in std_logic_vector(15 downto 0) := (others => 'X'); -- address
avmm_data_read : in std_logic := 'X'; -- read
avmm_data_readdata : out std_logic_vector(31 downto 0); -- readdata
avmm_data_waitrequest : out std_logic; -- waitrequest
avmm_data_readdatavalid : out std_logic; -- readdatavalid
avmm_data_burstcount : in std_logic_vector(3 downto 0) := (others => 'X'); -- burstcount
avmm_data_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
avmm_data_write : in std_logic := 'X'; -- write
avmm_csr_addr : in std_logic := 'X'; -- address
avmm_csr_read : in std_logic := 'X'; -- read
avmm_csr_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
avmm_csr_write : in std_logic := 'X'; -- write
avmm_csr_readdata : out std_logic_vector(31 downto 0) -- readdata
);
end component altera_onchip_flash;
component wasca_onchip_memory2_0 is
port (
clk : in std_logic := 'X'; -- clk
address : in std_logic_vector(11 downto 0) := (others => 'X'); -- address
clken : in std_logic := 'X'; -- clken
chipselect : in std_logic := 'X'; -- chipselect
write : in std_logic := 'X'; -- write
readdata : out std_logic_vector(31 downto 0); -- readdata
writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
byteenable : in std_logic_vector(3 downto 0) := (others => 'X'); -- byteenable
reset : in std_logic := 'X'; -- reset
reset_req : in std_logic := 'X' -- reset_req
);
end component wasca_onchip_memory2_0;
component wasca_pio_0 is
port (
clk : in std_logic := 'X'; -- clk
reset_n : in std_logic := 'X'; -- reset_n
address : in std_logic_vector(1 downto 0) := (others => 'X'); -- address
write_n : in std_logic := 'X'; -- write_n
writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
chipselect : in std_logic := 'X'; -- chipselect
readdata : out std_logic_vector(31 downto 0); -- readdata
bidir_port : inout std_logic_vector(3 downto 0) := (others => 'X') -- export
);
end component wasca_pio_0;
component sega_saturn_abus_slave is
port (
clock : in std_logic := 'X'; -- clk
abus_address : in std_logic_vector(9 downto 0) := (others => 'X'); -- address
abus_chipselect : in std_logic_vector(2 downto 0) := (others => 'X'); -- chipselect
abus_read : in std_logic := 'X'; -- read
abus_write : in std_logic_vector(1 downto 0) := (others => 'X'); -- write
abus_functioncode : in std_logic_vector(1 downto 0) := (others => 'X'); -- functioncode
abus_timing : in std_logic_vector(2 downto 0) := (others => 'X'); -- timing
abus_waitrequest : out std_logic; -- waitrequest
abus_addressstrobe : in std_logic := 'X'; -- addressstrobe
abus_interrupt : out std_logic; -- interrupt
abus_addressdata : inout std_logic_vector(15 downto 0) := (others => 'X'); -- addressdata
abus_direction : out std_logic; -- direction
abus_muxing : out std_logic_vector(1 downto 0); -- muxing
abus_disable_out : out std_logic; -- disableout
avalon_read : out std_logic; -- read
avalon_write : out std_logic; -- write
avalon_waitrequest : in std_logic := 'X'; -- waitrequest
avalon_address : out std_logic_vector(27 downto 0); -- address
avalon_readdata : in std_logic_vector(15 downto 0) := (others => 'X'); -- readdata
avalon_writedata : out std_logic_vector(15 downto 0); -- writedata
avalon_readdatavalid : in std_logic := 'X'; -- readdatavalid
avalon_burstcount : out std_logic; -- burstcount
reset : in std_logic := 'X'; -- reset
saturn_reset : in std_logic := 'X'; -- saturn_reset
avalon_nios_read : in std_logic := 'X'; -- read
avalon_nios_write : in std_logic := 'X'; -- write
avalon_nios_address : in std_logic_vector(7 downto 0) := (others => 'X'); -- address
avalon_nios_writedata : in std_logic_vector(15 downto 0) := (others => 'X'); -- writedata
avalon_nios_readdata : out std_logic_vector(15 downto 0); -- readdata
avalon_nios_waitrequest : out std_logic; -- waitrequest
avalon_nios_readdatavalid : out std_logic; -- readdatavalid
avalon_nios_burstcount : in std_logic := 'X' -- burstcount
);
end component sega_saturn_abus_slave;
component wasca_uart_0 is
port (
clk : in std_logic := 'X'; -- clk
reset_n : in std_logic := 'X'; -- reset_n
address : in std_logic_vector(2 downto 0) := (others => 'X'); -- address
begintransfer : in std_logic := 'X'; -- begintransfer
chipselect : in std_logic := 'X'; -- chipselect
read_n : in std_logic := 'X'; -- read_n
write_n : in std_logic := 'X'; -- write_n
writedata : in std_logic_vector(15 downto 0) := (others => 'X'); -- writedata
readdata : out std_logic_vector(15 downto 0); -- readdata
dataavailable : out std_logic; -- dataavailable
readyfordata : out std_logic; -- readyfordata
rxd : in std_logic := 'X'; -- export
txd : out std_logic; -- export
irq : out std_logic -- irq
);
end component wasca_uart_0;
component wasca_mm_interconnect_0 is
port (
altpll_0_c0_clk : in std_logic := 'X'; -- clk
clk_0_clk_clk : in std_logic := 'X'; -- clk
altpll_0_inclk_interface_reset_reset_bridge_in_reset_reset : in std_logic := 'X'; -- reset
sega_saturn_abus_slave_0_reset_reset_bridge_in_reset_reset : in std_logic := 'X'; -- reset
nios2_gen2_0_data_master_address : in std_logic_vector(26 downto 0) := (others => 'X'); -- address
nios2_gen2_0_data_master_waitrequest : out std_logic; -- waitrequest
nios2_gen2_0_data_master_byteenable : in std_logic_vector(3 downto 0) := (others => 'X'); -- byteenable
nios2_gen2_0_data_master_read : in std_logic := 'X'; -- read
nios2_gen2_0_data_master_readdata : out std_logic_vector(31 downto 0); -- readdata
nios2_gen2_0_data_master_write : in std_logic := 'X'; -- write
nios2_gen2_0_data_master_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
nios2_gen2_0_data_master_debugaccess : in std_logic := 'X'; -- debugaccess
nios2_gen2_0_instruction_master_address : in std_logic_vector(26 downto 0) := (others => 'X'); -- address
nios2_gen2_0_instruction_master_waitrequest : out std_logic; -- waitrequest
nios2_gen2_0_instruction_master_read : in std_logic := 'X'; -- read
nios2_gen2_0_instruction_master_readdata : out std_logic_vector(31 downto 0); -- readdata
sega_saturn_abus_slave_0_avalon_master_address : in std_logic_vector(27 downto 0) := (others => 'X'); -- address
sega_saturn_abus_slave_0_avalon_master_waitrequest : out std_logic; -- waitrequest
sega_saturn_abus_slave_0_avalon_master_burstcount : in std_logic_vector(0 downto 0) := (others => 'X'); -- burstcount
sega_saturn_abus_slave_0_avalon_master_read : in std_logic := 'X'; -- read
sega_saturn_abus_slave_0_avalon_master_readdata : out std_logic_vector(15 downto 0); -- readdata
sega_saturn_abus_slave_0_avalon_master_readdatavalid : out std_logic; -- readdatavalid
sega_saturn_abus_slave_0_avalon_master_write : in std_logic := 'X'; -- write
sega_saturn_abus_slave_0_avalon_master_writedata : in std_logic_vector(15 downto 0) := (others => 'X'); -- writedata
Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_address : out std_logic_vector(7 downto 0); -- address
Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_write : out std_logic; -- write
Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_read : out std_logic; -- read
Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_readdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_writedata : out std_logic_vector(31 downto 0); -- writedata
Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_byteenable : out std_logic_vector(3 downto 0); -- byteenable
Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_waitrequest : in std_logic := 'X'; -- waitrequest
Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_chipselect : out std_logic; -- chipselect
altpll_0_pll_slave_address : out std_logic_vector(1 downto 0); -- address
altpll_0_pll_slave_write : out std_logic; -- write
altpll_0_pll_slave_read : out std_logic; -- read
altpll_0_pll_slave_readdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
altpll_0_pll_slave_writedata : out std_logic_vector(31 downto 0); -- writedata
external_sdram_controller_s1_address : out std_logic_vector(23 downto 0); -- address
external_sdram_controller_s1_write : out std_logic; -- write
external_sdram_controller_s1_read : out std_logic; -- read
external_sdram_controller_s1_readdata : in std_logic_vector(15 downto 0) := (others => 'X'); -- readdata
external_sdram_controller_s1_writedata : out std_logic_vector(15 downto 0); -- writedata
external_sdram_controller_s1_byteenable : out std_logic_vector(1 downto 0); -- byteenable
external_sdram_controller_s1_readdatavalid : in std_logic := 'X'; -- readdatavalid
external_sdram_controller_s1_waitrequest : in std_logic := 'X'; -- waitrequest
external_sdram_controller_s1_chipselect : out std_logic; -- chipselect
nios2_gen2_0_debug_mem_slave_address : out std_logic_vector(8 downto 0); -- address
nios2_gen2_0_debug_mem_slave_write : out std_logic; -- write
nios2_gen2_0_debug_mem_slave_read : out std_logic; -- read
nios2_gen2_0_debug_mem_slave_readdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
nios2_gen2_0_debug_mem_slave_writedata : out std_logic_vector(31 downto 0); -- writedata
nios2_gen2_0_debug_mem_slave_byteenable : out std_logic_vector(3 downto 0); -- byteenable
nios2_gen2_0_debug_mem_slave_waitrequest : in std_logic := 'X'; -- waitrequest
nios2_gen2_0_debug_mem_slave_debugaccess : out std_logic; -- debugaccess
onchip_flash_0_data_address : out std_logic_vector(15 downto 0); -- address
onchip_flash_0_data_read : out std_logic; -- read
onchip_flash_0_data_readdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
onchip_flash_0_data_burstcount : out std_logic_vector(3 downto 0); -- burstcount
onchip_flash_0_data_readdatavalid : in std_logic := 'X'; -- readdatavalid
onchip_flash_0_data_waitrequest : in std_logic := 'X'; -- waitrequest
onchip_memory2_0_s1_address : out std_logic_vector(11 downto 0); -- address
onchip_memory2_0_s1_write : out std_logic; -- write
onchip_memory2_0_s1_readdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
onchip_memory2_0_s1_writedata : out std_logic_vector(31 downto 0); -- writedata
onchip_memory2_0_s1_byteenable : out std_logic_vector(3 downto 0); -- byteenable
onchip_memory2_0_s1_chipselect : out std_logic; -- chipselect
onchip_memory2_0_s1_clken : out std_logic; -- clken
pio_0_s1_address : out std_logic_vector(1 downto 0); -- address
pio_0_s1_write : out std_logic; -- write
pio_0_s1_readdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
pio_0_s1_writedata : out std_logic_vector(31 downto 0); -- writedata
pio_0_s1_chipselect : out std_logic; -- chipselect
sega_saturn_abus_slave_0_avalon_nios_address : out std_logic_vector(7 downto 0); -- address
sega_saturn_abus_slave_0_avalon_nios_write : out std_logic; -- write
sega_saturn_abus_slave_0_avalon_nios_read : out std_logic; -- read
sega_saturn_abus_slave_0_avalon_nios_readdata : in std_logic_vector(15 downto 0) := (others => 'X'); -- readdata
sega_saturn_abus_slave_0_avalon_nios_writedata : out std_logic_vector(15 downto 0); -- writedata
sega_saturn_abus_slave_0_avalon_nios_burstcount : out std_logic_vector(0 downto 0); -- burstcount
sega_saturn_abus_slave_0_avalon_nios_readdatavalid : in std_logic := 'X'; -- readdatavalid
sega_saturn_abus_slave_0_avalon_nios_waitrequest : in std_logic := 'X'; -- waitrequest
uart_0_s1_address : out std_logic_vector(2 downto 0); -- address
uart_0_s1_write : out std_logic; -- write
uart_0_s1_read : out std_logic; -- read
uart_0_s1_readdata : in std_logic_vector(15 downto 0) := (others => 'X'); -- readdata
uart_0_s1_writedata : out std_logic_vector(15 downto 0); -- writedata
uart_0_s1_begintransfer : out std_logic; -- begintransfer
uart_0_s1_chipselect : out std_logic -- chipselect
);
end component wasca_mm_interconnect_0;
component wasca_irq_mapper is
port (
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
receiver0_irq : in std_logic := 'X'; -- irq
sender_irq : out std_logic_vector(31 downto 0) -- irq
);
end component wasca_irq_mapper;
component wasca_rst_controller is
generic (
NUM_RESET_INPUTS : integer := 6;
OUTPUT_RESET_SYNC_EDGES : string := "deassert";
SYNC_DEPTH : integer := 2;
RESET_REQUEST_PRESENT : integer := 0;
RESET_REQ_WAIT_TIME : integer := 1;
MIN_RST_ASSERTION_TIME : integer := 3;
RESET_REQ_EARLY_DSRT_TIME : integer := 1;
USE_RESET_REQUEST_IN0 : integer := 0;
USE_RESET_REQUEST_IN1 : integer := 0;
USE_RESET_REQUEST_IN2 : integer := 0;
USE_RESET_REQUEST_IN3 : integer := 0;
USE_RESET_REQUEST_IN4 : integer := 0;
USE_RESET_REQUEST_IN5 : integer := 0;
USE_RESET_REQUEST_IN6 : integer := 0;
USE_RESET_REQUEST_IN7 : integer := 0;
USE_RESET_REQUEST_IN8 : integer := 0;
USE_RESET_REQUEST_IN9 : integer := 0;
USE_RESET_REQUEST_IN10 : integer := 0;
USE_RESET_REQUEST_IN11 : integer := 0;
USE_RESET_REQUEST_IN12 : integer := 0;
USE_RESET_REQUEST_IN13 : integer := 0;
USE_RESET_REQUEST_IN14 : integer := 0;
USE_RESET_REQUEST_IN15 : integer := 0;
ADAPT_RESET_REQUEST : integer := 0
);
port (
reset_in0 : in std_logic := 'X'; -- reset
clk : in std_logic := 'X'; -- clk
reset_out : out std_logic; -- reset
reset_req : out std_logic; -- reset_req
reset_req_in0 : in std_logic := 'X'; -- reset_req
reset_in1 : in std_logic := 'X'; -- reset
reset_req_in1 : in std_logic := 'X'; -- reset_req
reset_in2 : in std_logic := 'X'; -- reset
reset_req_in2 : in std_logic := 'X'; -- reset_req
reset_in3 : in std_logic := 'X'; -- reset
reset_req_in3 : in std_logic := 'X'; -- reset_req
reset_in4 : in std_logic := 'X'; -- reset
reset_req_in4 : in std_logic := 'X'; -- reset_req
reset_in5 : in std_logic := 'X'; -- reset
reset_req_in5 : in std_logic := 'X'; -- reset_req
reset_in6 : in std_logic := 'X'; -- reset
reset_req_in6 : in std_logic := 'X'; -- reset_req
reset_in7 : in std_logic := 'X'; -- reset
reset_req_in7 : in std_logic := 'X'; -- reset_req
reset_in8 : in std_logic := 'X'; -- reset
reset_req_in8 : in std_logic := 'X'; -- reset_req
reset_in9 : in std_logic := 'X'; -- reset
reset_req_in9 : in std_logic := 'X'; -- reset_req
reset_in10 : in std_logic := 'X'; -- reset
reset_req_in10 : in std_logic := 'X'; -- reset_req
reset_in11 : in std_logic := 'X'; -- reset
reset_req_in11 : in std_logic := 'X'; -- reset_req
reset_in12 : in std_logic := 'X'; -- reset
reset_req_in12 : in std_logic := 'X'; -- reset_req
reset_in13 : in std_logic := 'X'; -- reset
reset_req_in13 : in std_logic := 'X'; -- reset_req
reset_in14 : in std_logic := 'X'; -- reset
reset_req_in14 : in std_logic := 'X'; -- reset_req
reset_in15 : in std_logic := 'X'; -- reset
reset_req_in15 : in std_logic := 'X' -- reset_req
);
end component wasca_rst_controller;
component wasca_rst_controller_001 is
generic (
NUM_RESET_INPUTS : integer := 6;
OUTPUT_RESET_SYNC_EDGES : string := "deassert";
SYNC_DEPTH : integer := 2;
RESET_REQUEST_PRESENT : integer := 0;
RESET_REQ_WAIT_TIME : integer := 1;
MIN_RST_ASSERTION_TIME : integer := 3;
RESET_REQ_EARLY_DSRT_TIME : integer := 1;
USE_RESET_REQUEST_IN0 : integer := 0;
USE_RESET_REQUEST_IN1 : integer := 0;
USE_RESET_REQUEST_IN2 : integer := 0;
USE_RESET_REQUEST_IN3 : integer := 0;
USE_RESET_REQUEST_IN4 : integer := 0;
USE_RESET_REQUEST_IN5 : integer := 0;
USE_RESET_REQUEST_IN6 : integer := 0;
USE_RESET_REQUEST_IN7 : integer := 0;
USE_RESET_REQUEST_IN8 : integer := 0;
USE_RESET_REQUEST_IN9 : integer := 0;
USE_RESET_REQUEST_IN10 : integer := 0;
USE_RESET_REQUEST_IN11 : integer := 0;
USE_RESET_REQUEST_IN12 : integer := 0;
USE_RESET_REQUEST_IN13 : integer := 0;
USE_RESET_REQUEST_IN14 : integer := 0;
USE_RESET_REQUEST_IN15 : integer := 0;
ADAPT_RESET_REQUEST : integer := 0
);
port (
reset_in0 : in std_logic := 'X'; -- reset
clk : in std_logic := 'X'; -- clk
reset_out : out std_logic; -- reset
reset_req : out std_logic; -- reset_req
reset_req_in0 : in std_logic := 'X'; -- reset_req
reset_in1 : in std_logic := 'X'; -- reset
reset_req_in1 : in std_logic := 'X'; -- reset_req
reset_in2 : in std_logic := 'X'; -- reset
reset_req_in2 : in std_logic := 'X'; -- reset_req
reset_in3 : in std_logic := 'X'; -- reset
reset_req_in3 : in std_logic := 'X'; -- reset_req
reset_in4 : in std_logic := 'X'; -- reset
reset_req_in4 : in std_logic := 'X'; -- reset_req
reset_in5 : in std_logic := 'X'; -- reset
reset_req_in5 : in std_logic := 'X'; -- reset_req
reset_in6 : in std_logic := 'X'; -- reset
reset_req_in6 : in std_logic := 'X'; -- reset_req
reset_in7 : in std_logic := 'X'; -- reset
reset_req_in7 : in std_logic := 'X'; -- reset_req
reset_in8 : in std_logic := 'X'; -- reset
reset_req_in8 : in std_logic := 'X'; -- reset_req
reset_in9 : in std_logic := 'X'; -- reset
reset_req_in9 : in std_logic := 'X'; -- reset_req
reset_in10 : in std_logic := 'X'; -- reset
reset_req_in10 : in std_logic := 'X'; -- reset_req
reset_in11 : in std_logic := 'X'; -- reset
reset_req_in11 : in std_logic := 'X'; -- reset_req
reset_in12 : in std_logic := 'X'; -- reset
reset_req_in12 : in std_logic := 'X'; -- reset_req
reset_in13 : in std_logic := 'X'; -- reset
reset_req_in13 : in std_logic := 'X'; -- reset_req
reset_in14 : in std_logic := 'X'; -- reset
reset_req_in14 : in std_logic := 'X'; -- reset_req
reset_in15 : in std_logic := 'X'; -- reset
reset_req_in15 : in std_logic := 'X' -- reset_req
);
end component wasca_rst_controller_001;
signal altpll_0_c0_clk : std_logic; -- altpll_0:c0 -> [clock_116_mhz_clk, Altera_UP_SD_Card_Avalon_Interface_0:i_clock, external_sdram_controller:clk, irq_mapper:clk, mm_interconnect_0:altpll_0_c0_clk, nios2_gen2_0:clk, onchip_flash_0:clock, onchip_memory2_0:clk, pio_0:clk, rst_controller:clk, rst_controller_002:clk, sega_saturn_abus_slave_0:clock, uart_0:clk]
signal nios2_gen2_0_debug_reset_request_reset : std_logic; -- nios2_gen2_0:debug_reset_request -> [rst_controller:reset_in0, rst_controller_001:reset_in0, rst_controller_002:reset_in0]
signal sega_saturn_abus_slave_0_avalon_master_waitrequest : std_logic; -- mm_interconnect_0:sega_saturn_abus_slave_0_avalon_master_waitrequest -> sega_saturn_abus_slave_0:avalon_waitrequest
signal sega_saturn_abus_slave_0_avalon_master_readdata : std_logic_vector(15 downto 0); -- mm_interconnect_0:sega_saturn_abus_slave_0_avalon_master_readdata -> sega_saturn_abus_slave_0:avalon_readdata
signal sega_saturn_abus_slave_0_avalon_master_read : std_logic; -- sega_saturn_abus_slave_0:avalon_read -> mm_interconnect_0:sega_saturn_abus_slave_0_avalon_master_read
signal sega_saturn_abus_slave_0_avalon_master_address : std_logic_vector(27 downto 0); -- sega_saturn_abus_slave_0:avalon_address -> mm_interconnect_0:sega_saturn_abus_slave_0_avalon_master_address
signal sega_saturn_abus_slave_0_avalon_master_readdatavalid : std_logic; -- mm_interconnect_0:sega_saturn_abus_slave_0_avalon_master_readdatavalid -> sega_saturn_abus_slave_0:avalon_readdatavalid
signal sega_saturn_abus_slave_0_avalon_master_write : std_logic; -- sega_saturn_abus_slave_0:avalon_write -> mm_interconnect_0:sega_saturn_abus_slave_0_avalon_master_write
signal sega_saturn_abus_slave_0_avalon_master_writedata : std_logic_vector(15 downto 0); -- sega_saturn_abus_slave_0:avalon_writedata -> mm_interconnect_0:sega_saturn_abus_slave_0_avalon_master_writedata
signal sega_saturn_abus_slave_0_avalon_master_burstcount : std_logic; -- sega_saturn_abus_slave_0:avalon_burstcount -> mm_interconnect_0:sega_saturn_abus_slave_0_avalon_master_burstcount
signal nios2_gen2_0_data_master_readdata : std_logic_vector(31 downto 0); -- mm_interconnect_0:nios2_gen2_0_data_master_readdata -> nios2_gen2_0:d_readdata
signal nios2_gen2_0_data_master_waitrequest : std_logic; -- mm_interconnect_0:nios2_gen2_0_data_master_waitrequest -> nios2_gen2_0:d_waitrequest
signal nios2_gen2_0_data_master_debugaccess : std_logic; -- nios2_gen2_0:debug_mem_slave_debugaccess_to_roms -> mm_interconnect_0:nios2_gen2_0_data_master_debugaccess
signal nios2_gen2_0_data_master_address : std_logic_vector(26 downto 0); -- nios2_gen2_0:d_address -> mm_interconnect_0:nios2_gen2_0_data_master_address
signal nios2_gen2_0_data_master_byteenable : std_logic_vector(3 downto 0); -- nios2_gen2_0:d_byteenable -> mm_interconnect_0:nios2_gen2_0_data_master_byteenable
signal nios2_gen2_0_data_master_read : std_logic; -- nios2_gen2_0:d_read -> mm_interconnect_0:nios2_gen2_0_data_master_read
signal nios2_gen2_0_data_master_write : std_logic; -- nios2_gen2_0:d_write -> mm_interconnect_0:nios2_gen2_0_data_master_write
signal nios2_gen2_0_data_master_writedata : std_logic_vector(31 downto 0); -- nios2_gen2_0:d_writedata -> mm_interconnect_0:nios2_gen2_0_data_master_writedata
signal nios2_gen2_0_instruction_master_readdata : std_logic_vector(31 downto 0); -- mm_interconnect_0:nios2_gen2_0_instruction_master_readdata -> nios2_gen2_0:i_readdata
signal nios2_gen2_0_instruction_master_waitrequest : std_logic; -- mm_interconnect_0:nios2_gen2_0_instruction_master_waitrequest -> nios2_gen2_0:i_waitrequest
signal nios2_gen2_0_instruction_master_address : std_logic_vector(26 downto 0); -- nios2_gen2_0:i_address -> mm_interconnect_0:nios2_gen2_0_instruction_master_address
signal nios2_gen2_0_instruction_master_read : std_logic; -- nios2_gen2_0:i_read -> mm_interconnect_0:nios2_gen2_0_instruction_master_read
signal mm_interconnect_0_external_sdram_controller_s1_chipselect : std_logic; -- mm_interconnect_0:external_sdram_controller_s1_chipselect -> external_sdram_controller:az_cs
signal mm_interconnect_0_external_sdram_controller_s1_readdata : std_logic_vector(15 downto 0); -- external_sdram_controller:za_data -> mm_interconnect_0:external_sdram_controller_s1_readdata
signal mm_interconnect_0_external_sdram_controller_s1_waitrequest : std_logic; -- external_sdram_controller:za_waitrequest -> mm_interconnect_0:external_sdram_controller_s1_waitrequest
signal mm_interconnect_0_external_sdram_controller_s1_address : std_logic_vector(23 downto 0); -- mm_interconnect_0:external_sdram_controller_s1_address -> external_sdram_controller:az_addr
signal mm_interconnect_0_external_sdram_controller_s1_read : std_logic; -- mm_interconnect_0:external_sdram_controller_s1_read -> mm_interconnect_0_external_sdram_controller_s1_read:in
signal mm_interconnect_0_external_sdram_controller_s1_byteenable : std_logic_vector(1 downto 0); -- mm_interconnect_0:external_sdram_controller_s1_byteenable -> mm_interconnect_0_external_sdram_controller_s1_byteenable:in
signal mm_interconnect_0_external_sdram_controller_s1_readdatavalid : std_logic; -- external_sdram_controller:za_valid -> mm_interconnect_0:external_sdram_controller_s1_readdatavalid
signal mm_interconnect_0_external_sdram_controller_s1_write : std_logic; -- mm_interconnect_0:external_sdram_controller_s1_write -> mm_interconnect_0_external_sdram_controller_s1_write:in
signal mm_interconnect_0_external_sdram_controller_s1_writedata : std_logic_vector(15 downto 0); -- mm_interconnect_0:external_sdram_controller_s1_writedata -> external_sdram_controller:az_data
signal mm_interconnect_0_onchip_flash_0_data_readdata : std_logic_vector(31 downto 0); -- onchip_flash_0:avmm_data_readdata -> mm_interconnect_0:onchip_flash_0_data_readdata
signal mm_interconnect_0_onchip_flash_0_data_waitrequest : std_logic; -- onchip_flash_0:avmm_data_waitrequest -> mm_interconnect_0:onchip_flash_0_data_waitrequest
signal mm_interconnect_0_onchip_flash_0_data_address : std_logic_vector(15 downto 0); -- mm_interconnect_0:onchip_flash_0_data_address -> onchip_flash_0:avmm_data_addr
signal mm_interconnect_0_onchip_flash_0_data_read : std_logic; -- mm_interconnect_0:onchip_flash_0_data_read -> onchip_flash_0:avmm_data_read
signal mm_interconnect_0_onchip_flash_0_data_readdatavalid : std_logic; -- onchip_flash_0:avmm_data_readdatavalid -> mm_interconnect_0:onchip_flash_0_data_readdatavalid
signal mm_interconnect_0_onchip_flash_0_data_burstcount : std_logic_vector(3 downto 0); -- mm_interconnect_0:onchip_flash_0_data_burstcount -> onchip_flash_0:avmm_data_burstcount
signal mm_interconnect_0_nios2_gen2_0_debug_mem_slave_readdata : std_logic_vector(31 downto 0); -- nios2_gen2_0:debug_mem_slave_readdata -> mm_interconnect_0:nios2_gen2_0_debug_mem_slave_readdata
signal mm_interconnect_0_nios2_gen2_0_debug_mem_slave_waitrequest : std_logic; -- nios2_gen2_0:debug_mem_slave_waitrequest -> mm_interconnect_0:nios2_gen2_0_debug_mem_slave_waitrequest
signal mm_interconnect_0_nios2_gen2_0_debug_mem_slave_debugaccess : std_logic; -- mm_interconnect_0:nios2_gen2_0_debug_mem_slave_debugaccess -> nios2_gen2_0:debug_mem_slave_debugaccess
signal mm_interconnect_0_nios2_gen2_0_debug_mem_slave_address : std_logic_vector(8 downto 0); -- mm_interconnect_0:nios2_gen2_0_debug_mem_slave_address -> nios2_gen2_0:debug_mem_slave_address
signal mm_interconnect_0_nios2_gen2_0_debug_mem_slave_read : std_logic; -- mm_interconnect_0:nios2_gen2_0_debug_mem_slave_read -> nios2_gen2_0:debug_mem_slave_read
signal mm_interconnect_0_nios2_gen2_0_debug_mem_slave_byteenable : std_logic_vector(3 downto 0); -- mm_interconnect_0:nios2_gen2_0_debug_mem_slave_byteenable -> nios2_gen2_0:debug_mem_slave_byteenable
signal mm_interconnect_0_nios2_gen2_0_debug_mem_slave_write : std_logic; -- mm_interconnect_0:nios2_gen2_0_debug_mem_slave_write -> nios2_gen2_0:debug_mem_slave_write
signal mm_interconnect_0_nios2_gen2_0_debug_mem_slave_writedata : std_logic_vector(31 downto 0); -- mm_interconnect_0:nios2_gen2_0_debug_mem_slave_writedata -> nios2_gen2_0:debug_mem_slave_writedata
signal mm_interconnect_0_onchip_memory2_0_s1_chipselect : std_logic; -- mm_interconnect_0:onchip_memory2_0_s1_chipselect -> onchip_memory2_0:chipselect
signal mm_interconnect_0_onchip_memory2_0_s1_readdata : std_logic_vector(31 downto 0); -- onchip_memory2_0:readdata -> mm_interconnect_0:onchip_memory2_0_s1_readdata
signal mm_interconnect_0_onchip_memory2_0_s1_address : std_logic_vector(11 downto 0); -- mm_interconnect_0:onchip_memory2_0_s1_address -> onchip_memory2_0:address
signal mm_interconnect_0_onchip_memory2_0_s1_byteenable : std_logic_vector(3 downto 0); -- mm_interconnect_0:onchip_memory2_0_s1_byteenable -> onchip_memory2_0:byteenable
signal mm_interconnect_0_onchip_memory2_0_s1_write : std_logic; -- mm_interconnect_0:onchip_memory2_0_s1_write -> onchip_memory2_0:write
signal mm_interconnect_0_onchip_memory2_0_s1_writedata : std_logic_vector(31 downto 0); -- mm_interconnect_0:onchip_memory2_0_s1_writedata -> onchip_memory2_0:writedata
signal mm_interconnect_0_onchip_memory2_0_s1_clken : std_logic; -- mm_interconnect_0:onchip_memory2_0_s1_clken -> onchip_memory2_0:clken
signal mm_interconnect_0_sega_saturn_abus_slave_0_avalon_nios_readdata : std_logic_vector(15 downto 0); -- sega_saturn_abus_slave_0:avalon_nios_readdata -> mm_interconnect_0:sega_saturn_abus_slave_0_avalon_nios_readdata
signal mm_interconnect_0_sega_saturn_abus_slave_0_avalon_nios_waitrequest : std_logic; -- sega_saturn_abus_slave_0:avalon_nios_waitrequest -> mm_interconnect_0:sega_saturn_abus_slave_0_avalon_nios_waitrequest
signal mm_interconnect_0_sega_saturn_abus_slave_0_avalon_nios_address : std_logic_vector(7 downto 0); -- mm_interconnect_0:sega_saturn_abus_slave_0_avalon_nios_address -> sega_saturn_abus_slave_0:avalon_nios_address
signal mm_interconnect_0_sega_saturn_abus_slave_0_avalon_nios_read : std_logic; -- mm_interconnect_0:sega_saturn_abus_slave_0_avalon_nios_read -> sega_saturn_abus_slave_0:avalon_nios_read
signal mm_interconnect_0_sega_saturn_abus_slave_0_avalon_nios_readdatavalid : std_logic; -- sega_saturn_abus_slave_0:avalon_nios_readdatavalid -> mm_interconnect_0:sega_saturn_abus_slave_0_avalon_nios_readdatavalid
signal mm_interconnect_0_sega_saturn_abus_slave_0_avalon_nios_write : std_logic; -- mm_interconnect_0:sega_saturn_abus_slave_0_avalon_nios_write -> sega_saturn_abus_slave_0:avalon_nios_write
signal mm_interconnect_0_sega_saturn_abus_slave_0_avalon_nios_writedata : std_logic_vector(15 downto 0); -- mm_interconnect_0:sega_saturn_abus_slave_0_avalon_nios_writedata -> sega_saturn_abus_slave_0:avalon_nios_writedata
signal mm_interconnect_0_sega_saturn_abus_slave_0_avalon_nios_burstcount : std_logic_vector(0 downto 0); -- mm_interconnect_0:sega_saturn_abus_slave_0_avalon_nios_burstcount -> sega_saturn_abus_slave_0:avalon_nios_burstcount
signal mm_interconnect_0_altera_up_sd_card_avalon_interface_0_avalon_sdcard_slave_chipselect : std_logic; -- mm_interconnect_0:Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_chipselect -> Altera_UP_SD_Card_Avalon_Interface_0:i_avalon_chip_select
signal mm_interconnect_0_altera_up_sd_card_avalon_interface_0_avalon_sdcard_slave_readdata : std_logic_vector(31 downto 0); -- Altera_UP_SD_Card_Avalon_Interface_0:o_avalon_readdata -> mm_interconnect_0:Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_readdata
signal mm_interconnect_0_altera_up_sd_card_avalon_interface_0_avalon_sdcard_slave_waitrequest : std_logic; -- Altera_UP_SD_Card_Avalon_Interface_0:o_avalon_waitrequest -> mm_interconnect_0:Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_waitrequest
signal mm_interconnect_0_altera_up_sd_card_avalon_interface_0_avalon_sdcard_slave_address : std_logic_vector(7 downto 0); -- mm_interconnect_0:Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_address -> Altera_UP_SD_Card_Avalon_Interface_0:i_avalon_address
signal mm_interconnect_0_altera_up_sd_card_avalon_interface_0_avalon_sdcard_slave_read : std_logic; -- mm_interconnect_0:Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_read -> Altera_UP_SD_Card_Avalon_Interface_0:i_avalon_read
signal mm_interconnect_0_altera_up_sd_card_avalon_interface_0_avalon_sdcard_slave_byteenable : std_logic_vector(3 downto 0); -- mm_interconnect_0:Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_byteenable -> Altera_UP_SD_Card_Avalon_Interface_0:i_avalon_byteenable
signal mm_interconnect_0_altera_up_sd_card_avalon_interface_0_avalon_sdcard_slave_write : std_logic; -- mm_interconnect_0:Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_write -> Altera_UP_SD_Card_Avalon_Interface_0:i_avalon_write
signal mm_interconnect_0_altera_up_sd_card_avalon_interface_0_avalon_sdcard_slave_writedata : std_logic_vector(31 downto 0); -- mm_interconnect_0:Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_writedata -> Altera_UP_SD_Card_Avalon_Interface_0:i_avalon_writedata
signal mm_interconnect_0_altpll_0_pll_slave_readdata : std_logic_vector(31 downto 0); -- altpll_0:readdata -> mm_interconnect_0:altpll_0_pll_slave_readdata
signal mm_interconnect_0_altpll_0_pll_slave_address : std_logic_vector(1 downto 0); -- mm_interconnect_0:altpll_0_pll_slave_address -> altpll_0:address
signal mm_interconnect_0_altpll_0_pll_slave_read : std_logic; -- mm_interconnect_0:altpll_0_pll_slave_read -> altpll_0:read
signal mm_interconnect_0_altpll_0_pll_slave_write : std_logic; -- mm_interconnect_0:altpll_0_pll_slave_write -> altpll_0:write
signal mm_interconnect_0_altpll_0_pll_slave_writedata : std_logic_vector(31 downto 0); -- mm_interconnect_0:altpll_0_pll_slave_writedata -> altpll_0:writedata
signal mm_interconnect_0_pio_0_s1_chipselect : std_logic; -- mm_interconnect_0:pio_0_s1_chipselect -> pio_0:chipselect
signal mm_interconnect_0_pio_0_s1_readdata : std_logic_vector(31 downto 0); -- pio_0:readdata -> mm_interconnect_0:pio_0_s1_readdata
signal mm_interconnect_0_pio_0_s1_address : std_logic_vector(1 downto 0); -- mm_interconnect_0:pio_0_s1_address -> pio_0:address
signal mm_interconnect_0_pio_0_s1_write : std_logic; -- mm_interconnect_0:pio_0_s1_write -> mm_interconnect_0_pio_0_s1_write:in
signal mm_interconnect_0_pio_0_s1_writedata : std_logic_vector(31 downto 0); -- mm_interconnect_0:pio_0_s1_writedata -> pio_0:writedata
signal mm_interconnect_0_uart_0_s1_chipselect : std_logic; -- mm_interconnect_0:uart_0_s1_chipselect -> uart_0:chipselect
signal mm_interconnect_0_uart_0_s1_readdata : std_logic_vector(15 downto 0); -- uart_0:readdata -> mm_interconnect_0:uart_0_s1_readdata
signal mm_interconnect_0_uart_0_s1_address : std_logic_vector(2 downto 0); -- mm_interconnect_0:uart_0_s1_address -> uart_0:address
signal mm_interconnect_0_uart_0_s1_read : std_logic; -- mm_interconnect_0:uart_0_s1_read -> mm_interconnect_0_uart_0_s1_read:in
signal mm_interconnect_0_uart_0_s1_begintransfer : std_logic; -- mm_interconnect_0:uart_0_s1_begintransfer -> uart_0:begintransfer
signal mm_interconnect_0_uart_0_s1_write : std_logic; -- mm_interconnect_0:uart_0_s1_write -> mm_interconnect_0_uart_0_s1_write:in
signal mm_interconnect_0_uart_0_s1_writedata : std_logic_vector(15 downto 0); -- mm_interconnect_0:uart_0_s1_writedata -> uart_0:writedata
signal irq_mapper_receiver0_irq : std_logic; -- uart_0:irq -> irq_mapper:receiver0_irq
signal nios2_gen2_0_irq_irq : std_logic_vector(31 downto 0); -- irq_mapper:sender_irq -> nios2_gen2_0:irq
signal rst_controller_reset_out_reset : std_logic; -- rst_controller:reset_out -> [irq_mapper:reset, mm_interconnect_0:sega_saturn_abus_slave_0_reset_reset_bridge_in_reset_reset, onchip_memory2_0:reset, rst_controller_reset_out_reset:in, rst_translator:in_reset, sega_saturn_abus_slave_0:reset]
signal rst_controller_reset_out_reset_req : std_logic; -- rst_controller:reset_req -> [onchip_memory2_0:reset_req, rst_translator:reset_req_in]
signal rst_controller_001_reset_out_reset : std_logic; -- rst_controller_001:reset_out -> [altpll_0:reset, mm_interconnect_0:altpll_0_inclk_interface_reset_reset_bridge_in_reset_reset]
signal mm_interconnect_0_external_sdram_controller_s1_read_ports_inv : std_logic; -- mm_interconnect_0_external_sdram_controller_s1_read:inv -> external_sdram_controller:az_rd_n
signal mm_interconnect_0_external_sdram_controller_s1_byteenable_ports_inv : std_logic_vector(1 downto 0); -- mm_interconnect_0_external_sdram_controller_s1_byteenable:inv -> external_sdram_controller:az_be_n
signal mm_interconnect_0_external_sdram_controller_s1_write_ports_inv : std_logic; -- mm_interconnect_0_external_sdram_controller_s1_write:inv -> external_sdram_controller:az_wr_n
signal mm_interconnect_0_pio_0_s1_write_ports_inv : std_logic; -- mm_interconnect_0_pio_0_s1_write:inv -> pio_0:write_n
signal mm_interconnect_0_uart_0_s1_read_ports_inv : std_logic; -- mm_interconnect_0_uart_0_s1_read:inv -> uart_0:read_n
signal mm_interconnect_0_uart_0_s1_write_ports_inv : std_logic; -- mm_interconnect_0_uart_0_s1_write:inv -> uart_0:write_n
signal rst_controller_reset_out_reset_ports_inv : std_logic; -- rst_controller_reset_out_reset:inv -> [Altera_UP_SD_Card_Avalon_Interface_0:i_reset_n, external_sdram_controller:reset_n, nios2_gen2_0:reset_n, onchip_flash_0:reset_n, pio_0:reset_n, uart_0:reset_n]
begin
altera_up_sd_card_avalon_interface_0 : component Altera_UP_SD_Card_Avalon_Interface
port map (
i_avalon_chip_select => mm_interconnect_0_altera_up_sd_card_avalon_interface_0_avalon_sdcard_slave_chipselect, -- avalon_sdcard_slave.chipselect
i_avalon_address => mm_interconnect_0_altera_up_sd_card_avalon_interface_0_avalon_sdcard_slave_address, -- .address
i_avalon_read => mm_interconnect_0_altera_up_sd_card_avalon_interface_0_avalon_sdcard_slave_read, -- .read
i_avalon_write => mm_interconnect_0_altera_up_sd_card_avalon_interface_0_avalon_sdcard_slave_write, -- .write
i_avalon_byteenable => mm_interconnect_0_altera_up_sd_card_avalon_interface_0_avalon_sdcard_slave_byteenable, -- .byteenable
i_avalon_writedata => mm_interconnect_0_altera_up_sd_card_avalon_interface_0_avalon_sdcard_slave_writedata, -- .writedata
o_avalon_readdata => mm_interconnect_0_altera_up_sd_card_avalon_interface_0_avalon_sdcard_slave_readdata, -- .readdata
o_avalon_waitrequest => mm_interconnect_0_altera_up_sd_card_avalon_interface_0_avalon_sdcard_slave_waitrequest, -- .waitrequest
i_clock => altpll_0_c0_clk, -- clk.clk
i_reset_n => rst_controller_reset_out_reset_ports_inv, -- reset.reset_n
b_SD_cmd => altera_up_sd_card_avalon_interface_0_conduit_end_b_SD_cmd, -- conduit_end.export
b_SD_dat => altera_up_sd_card_avalon_interface_0_conduit_end_b_SD_dat, -- .export
b_SD_dat3 => altera_up_sd_card_avalon_interface_0_conduit_end_b_SD_dat3, -- .export
o_SD_clock => altera_up_sd_card_avalon_interface_0_conduit_end_o_SD_clock -- .export
);
altpll_0 : component wasca_altpll_0
port map (
clk => clk_clk, -- inclk_interface.clk
reset => rst_controller_001_reset_out_reset, -- inclk_interface_reset.reset
read => mm_interconnect_0_altpll_0_pll_slave_read, -- pll_slave.read
write => mm_interconnect_0_altpll_0_pll_slave_write, -- .write
address => mm_interconnect_0_altpll_0_pll_slave_address, -- .address
readdata => mm_interconnect_0_altpll_0_pll_slave_readdata, -- .readdata
writedata => mm_interconnect_0_altpll_0_pll_slave_writedata, -- .writedata
c0 => altpll_0_c0_clk, -- c0.clk
areset => altpll_0_areset_conduit_export, -- areset_conduit.export
c1 => open, -- c1_conduit.export
locked => altpll_0_locked_conduit_export, -- locked_conduit.export
phasedone => altpll_0_phasedone_conduit_export -- phasedone_conduit.export
);
external_sdram_controller : component wasca_external_sdram_controller
port map (
clk => altpll_0_c0_clk, -- clk.clk
reset_n => rst_controller_reset_out_reset_ports_inv, -- reset.reset_n
az_addr => mm_interconnect_0_external_sdram_controller_s1_address, -- s1.address
az_be_n => mm_interconnect_0_external_sdram_controller_s1_byteenable_ports_inv, -- .byteenable_n
az_cs => mm_interconnect_0_external_sdram_controller_s1_chipselect, -- .chipselect
az_data => mm_interconnect_0_external_sdram_controller_s1_writedata, -- .writedata
az_rd_n => mm_interconnect_0_external_sdram_controller_s1_read_ports_inv, -- .read_n
az_wr_n => mm_interconnect_0_external_sdram_controller_s1_write_ports_inv, -- .write_n
za_data => mm_interconnect_0_external_sdram_controller_s1_readdata, -- .readdata
za_valid => mm_interconnect_0_external_sdram_controller_s1_readdatavalid, -- .readdatavalid
za_waitrequest => mm_interconnect_0_external_sdram_controller_s1_waitrequest, -- .waitrequest
zs_addr => external_sdram_controller_wire_addr, -- wire.export
zs_ba => external_sdram_controller_wire_ba, -- .export
zs_cas_n => external_sdram_controller_wire_cas_n, -- .export
zs_cke => external_sdram_controller_wire_cke, -- .export
zs_cs_n => external_sdram_controller_wire_cs_n, -- .export
zs_dq => external_sdram_controller_wire_dq, -- .export
zs_dqm => external_sdram_controller_wire_dqm, -- .export
zs_ras_n => external_sdram_controller_wire_ras_n, -- .export
zs_we_n => external_sdram_controller_wire_we_n -- .export
);
nios2_gen2_0 : component wasca_nios2_gen2_0
port map (
clk => altpll_0_c0_clk, -- clk.clk
reset_n => rst_controller_reset_out_reset_ports_inv, -- reset.reset_n
d_address => nios2_gen2_0_data_master_address, -- data_master.address
d_byteenable => nios2_gen2_0_data_master_byteenable, -- .byteenable
d_read => nios2_gen2_0_data_master_read, -- .read
d_readdata => nios2_gen2_0_data_master_readdata, -- .readdata
d_waitrequest => nios2_gen2_0_data_master_waitrequest, -- .waitrequest
d_write => nios2_gen2_0_data_master_write, -- .write
d_writedata => nios2_gen2_0_data_master_writedata, -- .writedata
debug_mem_slave_debugaccess_to_roms => nios2_gen2_0_data_master_debugaccess, -- .debugaccess
i_address => nios2_gen2_0_instruction_master_address, -- instruction_master.address
i_read => nios2_gen2_0_instruction_master_read, -- .read
i_readdata => nios2_gen2_0_instruction_master_readdata, -- .readdata
i_waitrequest => nios2_gen2_0_instruction_master_waitrequest, -- .waitrequest
irq => nios2_gen2_0_irq_irq, -- irq.irq
debug_reset_request => nios2_gen2_0_debug_reset_request_reset, -- debug_reset_request.reset
debug_mem_slave_address => mm_interconnect_0_nios2_gen2_0_debug_mem_slave_address, -- debug_mem_slave.address
debug_mem_slave_byteenable => mm_interconnect_0_nios2_gen2_0_debug_mem_slave_byteenable, -- .byteenable
debug_mem_slave_debugaccess => mm_interconnect_0_nios2_gen2_0_debug_mem_slave_debugaccess, -- .debugaccess
debug_mem_slave_read => mm_interconnect_0_nios2_gen2_0_debug_mem_slave_read, -- .read
debug_mem_slave_readdata => mm_interconnect_0_nios2_gen2_0_debug_mem_slave_readdata, -- .readdata
debug_mem_slave_waitrequest => mm_interconnect_0_nios2_gen2_0_debug_mem_slave_waitrequest, -- .waitrequest
debug_mem_slave_write => mm_interconnect_0_nios2_gen2_0_debug_mem_slave_write, -- .write
debug_mem_slave_writedata => mm_interconnect_0_nios2_gen2_0_debug_mem_slave_writedata, -- .writedata
dummy_ci_port => open -- custom_instruction_master.readra
);
onchip_flash_0 : component altera_onchip_flash
generic map (
INIT_FILENAME => "",
INIT_FILENAME_SIM => "",
DEVICE_FAMILY => "MAX 10",
PART_NAME => "10M08SAE144C8GES",
DEVICE_ID => "08",
SECTOR1_START_ADDR => 0,
SECTOR1_END_ADDR => 4095,
SECTOR2_START_ADDR => 4096,
SECTOR2_END_ADDR => 8191,
SECTOR3_START_ADDR => 8192,
SECTOR3_END_ADDR => 29183,
SECTOR4_START_ADDR => 29184,
SECTOR4_END_ADDR => 44031,
SECTOR5_START_ADDR => 0,
SECTOR5_END_ADDR => 0,
MIN_VALID_ADDR => 0,
MAX_VALID_ADDR => 44031,
MIN_UFM_VALID_ADDR => 0,
MAX_UFM_VALID_ADDR => 44031,
SECTOR1_MAP => 1,
SECTOR2_MAP => 2,
SECTOR3_MAP => 3,
SECTOR4_MAP => 4,
SECTOR5_MAP => 0,
ADDR_RANGE1_END_ADDR => 44031,
ADDR_RANGE1_OFFSET => 512,
ADDR_RANGE2_OFFSET => 0,
AVMM_DATA_ADDR_WIDTH => 16,
AVMM_DATA_DATA_WIDTH => 32,
AVMM_DATA_BURSTCOUNT_WIDTH => 4,
SECTOR_READ_PROTECTION_MODE => 31,
FLASH_SEQ_READ_DATA_COUNT => 2,
FLASH_ADDR_ALIGNMENT_BITS => 1,
FLASH_READ_CYCLE_MAX_INDEX => 3,
FLASH_RESET_CYCLE_MAX_INDEX => 29,
FLASH_BUSY_TIMEOUT_CYCLE_MAX_INDEX => 111,
FLASH_ERASE_TIMEOUT_CYCLE_MAX_INDEX => 40603248,
FLASH_WRITE_TIMEOUT_CYCLE_MAX_INDEX => 35382,
PARALLEL_MODE => true,
READ_AND_WRITE_MODE => false,
WRAPPING_BURST_MODE => false,
IS_DUAL_BOOT => "False",
IS_ERAM_SKIP => "True",
IS_COMPRESSED_IMAGE => "True"
)
port map (
clock => altpll_0_c0_clk, -- clk.clk
reset_n => rst_controller_reset_out_reset_ports_inv, -- nreset.reset_n
avmm_data_addr => mm_interconnect_0_onchip_flash_0_data_address, -- data.address
avmm_data_read => mm_interconnect_0_onchip_flash_0_data_read, -- .read
avmm_data_readdata => mm_interconnect_0_onchip_flash_0_data_readdata, -- .readdata
avmm_data_waitrequest => mm_interconnect_0_onchip_flash_0_data_waitrequest, -- .waitrequest
avmm_data_readdatavalid => mm_interconnect_0_onchip_flash_0_data_readdatavalid, -- .readdatavalid
avmm_data_burstcount => mm_interconnect_0_onchip_flash_0_data_burstcount, -- .burstcount
avmm_data_writedata => "00000000000000000000000000000000", -- (terminated)
avmm_data_write => '0', -- (terminated)
avmm_csr_addr => '0', -- (terminated)
avmm_csr_read => '0', -- (terminated)
avmm_csr_writedata => "00000000000000000000000000000000", -- (terminated)
avmm_csr_write => '0', -- (terminated)
avmm_csr_readdata => open -- (terminated)
);
onchip_memory2_0 : component wasca_onchip_memory2_0
port map (
clk => altpll_0_c0_clk, -- clk1.clk
address => mm_interconnect_0_onchip_memory2_0_s1_address, -- s1.address
clken => mm_interconnect_0_onchip_memory2_0_s1_clken, -- .clken
chipselect => mm_interconnect_0_onchip_memory2_0_s1_chipselect, -- .chipselect
write => mm_interconnect_0_onchip_memory2_0_s1_write, -- .write
readdata => mm_interconnect_0_onchip_memory2_0_s1_readdata, -- .readdata
writedata => mm_interconnect_0_onchip_memory2_0_s1_writedata, -- .writedata
byteenable => mm_interconnect_0_onchip_memory2_0_s1_byteenable, -- .byteenable
reset => rst_controller_reset_out_reset, -- reset1.reset
reset_req => rst_controller_reset_out_reset_req -- .reset_req
);
pio_0 : component wasca_pio_0
port map (
clk => altpll_0_c0_clk, -- clk.clk
reset_n => rst_controller_reset_out_reset_ports_inv, -- reset.reset_n
address => mm_interconnect_0_pio_0_s1_address, -- s1.address
write_n => mm_interconnect_0_pio_0_s1_write_ports_inv, -- .write_n
writedata => mm_interconnect_0_pio_0_s1_writedata, -- .writedata
chipselect => mm_interconnect_0_pio_0_s1_chipselect, -- .chipselect
readdata => mm_interconnect_0_pio_0_s1_readdata, -- .readdata
bidir_port => pio_0_external_connection_export -- external_connection.export
);
sega_saturn_abus_slave_0 : component sega_saturn_abus_slave
port map (
clock => altpll_0_c0_clk, -- clock.clk
abus_address => sega_saturn_abus_slave_0_abus_address, -- abus.address
abus_chipselect => sega_saturn_abus_slave_0_abus_chipselect, -- .chipselect
abus_read => sega_saturn_abus_slave_0_abus_read, -- .read
abus_write => sega_saturn_abus_slave_0_abus_write, -- .write
abus_functioncode => sega_saturn_abus_slave_0_abus_functioncode, -- .functioncode
abus_timing => sega_saturn_abus_slave_0_abus_timing, -- .timing
abus_waitrequest => sega_saturn_abus_slave_0_abus_waitrequest, -- .waitrequest
abus_addressstrobe => sega_saturn_abus_slave_0_abus_addressstrobe, -- .addressstrobe
abus_interrupt => sega_saturn_abus_slave_0_abus_interrupt, -- .interrupt
abus_addressdata => sega_saturn_abus_slave_0_abus_addressdata, -- .addressdata
abus_direction => sega_saturn_abus_slave_0_abus_direction, -- .direction
abus_muxing => sega_saturn_abus_slave_0_abus_muxing, -- .muxing
abus_disable_out => sega_saturn_abus_slave_0_abus_disableout, -- .disableout
avalon_read => sega_saturn_abus_slave_0_avalon_master_read, -- avalon_master.read
avalon_write => sega_saturn_abus_slave_0_avalon_master_write, -- .write
avalon_waitrequest => sega_saturn_abus_slave_0_avalon_master_waitrequest, -- .waitrequest
avalon_address => sega_saturn_abus_slave_0_avalon_master_address, -- .address
avalon_readdata => sega_saturn_abus_slave_0_avalon_master_readdata, -- .readdata
avalon_writedata => sega_saturn_abus_slave_0_avalon_master_writedata, -- .writedata
avalon_readdatavalid => sega_saturn_abus_slave_0_avalon_master_readdatavalid, -- .readdatavalid
avalon_burstcount => sega_saturn_abus_slave_0_avalon_master_burstcount, -- .burstcount
reset => rst_controller_reset_out_reset, -- reset.reset
saturn_reset => sega_saturn_abus_slave_0_conduit_saturn_reset_saturn_reset, -- conduit_saturn_reset.saturn_reset
avalon_nios_read => mm_interconnect_0_sega_saturn_abus_slave_0_avalon_nios_read, -- avalon_nios.read
avalon_nios_write => mm_interconnect_0_sega_saturn_abus_slave_0_avalon_nios_write, -- .write
avalon_nios_address => mm_interconnect_0_sega_saturn_abus_slave_0_avalon_nios_address, -- .address
avalon_nios_writedata => mm_interconnect_0_sega_saturn_abus_slave_0_avalon_nios_writedata, -- .writedata
avalon_nios_readdata => mm_interconnect_0_sega_saturn_abus_slave_0_avalon_nios_readdata, -- .readdata
avalon_nios_waitrequest => mm_interconnect_0_sega_saturn_abus_slave_0_avalon_nios_waitrequest, -- .waitrequest
avalon_nios_readdatavalid => mm_interconnect_0_sega_saturn_abus_slave_0_avalon_nios_readdatavalid, -- .readdatavalid
avalon_nios_burstcount => mm_interconnect_0_sega_saturn_abus_slave_0_avalon_nios_burstcount(0) -- .burstcount
);
uart_0 : component wasca_uart_0
port map (
clk => altpll_0_c0_clk, -- clk.clk
reset_n => rst_controller_reset_out_reset_ports_inv, -- reset.reset_n
address => mm_interconnect_0_uart_0_s1_address, -- s1.address
begintransfer => mm_interconnect_0_uart_0_s1_begintransfer, -- .begintransfer
chipselect => mm_interconnect_0_uart_0_s1_chipselect, -- .chipselect
read_n => mm_interconnect_0_uart_0_s1_read_ports_inv, -- .read_n
write_n => mm_interconnect_0_uart_0_s1_write_ports_inv, -- .write_n
writedata => mm_interconnect_0_uart_0_s1_writedata, -- .writedata
readdata => mm_interconnect_0_uart_0_s1_readdata, -- .readdata
dataavailable => open, -- .dataavailable
readyfordata => open, -- .readyfordata
rxd => uart_0_external_connection_rxd, -- external_connection.export
txd => uart_0_external_connection_txd, -- .export
irq => irq_mapper_receiver0_irq -- irq.irq
);
mm_interconnect_0 : component wasca_mm_interconnect_0
port map (
altpll_0_c0_clk => altpll_0_c0_clk, -- altpll_0_c0.clk
clk_0_clk_clk => clk_clk, -- clk_0_clk.clk
altpll_0_inclk_interface_reset_reset_bridge_in_reset_reset => rst_controller_001_reset_out_reset, -- altpll_0_inclk_interface_reset_reset_bridge_in_reset.reset
sega_saturn_abus_slave_0_reset_reset_bridge_in_reset_reset => rst_controller_reset_out_reset, -- sega_saturn_abus_slave_0_reset_reset_bridge_in_reset.reset
nios2_gen2_0_data_master_address => nios2_gen2_0_data_master_address, -- nios2_gen2_0_data_master.address
nios2_gen2_0_data_master_waitrequest => nios2_gen2_0_data_master_waitrequest, -- .waitrequest
nios2_gen2_0_data_master_byteenable => nios2_gen2_0_data_master_byteenable, -- .byteenable
nios2_gen2_0_data_master_read => nios2_gen2_0_data_master_read, -- .read
nios2_gen2_0_data_master_readdata => nios2_gen2_0_data_master_readdata, -- .readdata
nios2_gen2_0_data_master_write => nios2_gen2_0_data_master_write, -- .write
nios2_gen2_0_data_master_writedata => nios2_gen2_0_data_master_writedata, -- .writedata
nios2_gen2_0_data_master_debugaccess => nios2_gen2_0_data_master_debugaccess, -- .debugaccess
nios2_gen2_0_instruction_master_address => nios2_gen2_0_instruction_master_address, -- nios2_gen2_0_instruction_master.address
nios2_gen2_0_instruction_master_waitrequest => nios2_gen2_0_instruction_master_waitrequest, -- .waitrequest
nios2_gen2_0_instruction_master_read => nios2_gen2_0_instruction_master_read, -- .read
nios2_gen2_0_instruction_master_readdata => nios2_gen2_0_instruction_master_readdata, -- .readdata
sega_saturn_abus_slave_0_avalon_master_address => sega_saturn_abus_slave_0_avalon_master_address, -- sega_saturn_abus_slave_0_avalon_master.address
sega_saturn_abus_slave_0_avalon_master_waitrequest => sega_saturn_abus_slave_0_avalon_master_waitrequest, -- .waitrequest
sega_saturn_abus_slave_0_avalon_master_burstcount(0) => sega_saturn_abus_slave_0_avalon_master_burstcount, -- .burstcount
sega_saturn_abus_slave_0_avalon_master_read => sega_saturn_abus_slave_0_avalon_master_read, -- .read
sega_saturn_abus_slave_0_avalon_master_readdata => sega_saturn_abus_slave_0_avalon_master_readdata, -- .readdata
sega_saturn_abus_slave_0_avalon_master_readdatavalid => sega_saturn_abus_slave_0_avalon_master_readdatavalid, -- .readdatavalid
sega_saturn_abus_slave_0_avalon_master_write => sega_saturn_abus_slave_0_avalon_master_write, -- .write
sega_saturn_abus_slave_0_avalon_master_writedata => sega_saturn_abus_slave_0_avalon_master_writedata, -- .writedata
Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_address => mm_interconnect_0_altera_up_sd_card_avalon_interface_0_avalon_sdcard_slave_address, -- Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave.address
Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_write => mm_interconnect_0_altera_up_sd_card_avalon_interface_0_avalon_sdcard_slave_write, -- .write
Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_read => mm_interconnect_0_altera_up_sd_card_avalon_interface_0_avalon_sdcard_slave_read, -- .read
Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_readdata => mm_interconnect_0_altera_up_sd_card_avalon_interface_0_avalon_sdcard_slave_readdata, -- .readdata
Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_writedata => mm_interconnect_0_altera_up_sd_card_avalon_interface_0_avalon_sdcard_slave_writedata, -- .writedata
Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_byteenable => mm_interconnect_0_altera_up_sd_card_avalon_interface_0_avalon_sdcard_slave_byteenable, -- .byteenable
Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_waitrequest => mm_interconnect_0_altera_up_sd_card_avalon_interface_0_avalon_sdcard_slave_waitrequest, -- .waitrequest
Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_chipselect => mm_interconnect_0_altera_up_sd_card_avalon_interface_0_avalon_sdcard_slave_chipselect, -- .chipselect
altpll_0_pll_slave_address => mm_interconnect_0_altpll_0_pll_slave_address, -- altpll_0_pll_slave.address
altpll_0_pll_slave_write => mm_interconnect_0_altpll_0_pll_slave_write, -- .write
altpll_0_pll_slave_read => mm_interconnect_0_altpll_0_pll_slave_read, -- .read
altpll_0_pll_slave_readdata => mm_interconnect_0_altpll_0_pll_slave_readdata, -- .readdata
altpll_0_pll_slave_writedata => mm_interconnect_0_altpll_0_pll_slave_writedata, -- .writedata
external_sdram_controller_s1_address => mm_interconnect_0_external_sdram_controller_s1_address, -- external_sdram_controller_s1.address
external_sdram_controller_s1_write => mm_interconnect_0_external_sdram_controller_s1_write, -- .write
external_sdram_controller_s1_read => mm_interconnect_0_external_sdram_controller_s1_read, -- .read
external_sdram_controller_s1_readdata => mm_interconnect_0_external_sdram_controller_s1_readdata, -- .readdata
external_sdram_controller_s1_writedata => mm_interconnect_0_external_sdram_controller_s1_writedata, -- .writedata
external_sdram_controller_s1_byteenable => mm_interconnect_0_external_sdram_controller_s1_byteenable, -- .byteenable
external_sdram_controller_s1_readdatavalid => mm_interconnect_0_external_sdram_controller_s1_readdatavalid, -- .readdatavalid
external_sdram_controller_s1_waitrequest => mm_interconnect_0_external_sdram_controller_s1_waitrequest, -- .waitrequest
external_sdram_controller_s1_chipselect => mm_interconnect_0_external_sdram_controller_s1_chipselect, -- .chipselect
nios2_gen2_0_debug_mem_slave_address => mm_interconnect_0_nios2_gen2_0_debug_mem_slave_address, -- nios2_gen2_0_debug_mem_slave.address
nios2_gen2_0_debug_mem_slave_write => mm_interconnect_0_nios2_gen2_0_debug_mem_slave_write, -- .write
nios2_gen2_0_debug_mem_slave_read => mm_interconnect_0_nios2_gen2_0_debug_mem_slave_read, -- .read
nios2_gen2_0_debug_mem_slave_readdata => mm_interconnect_0_nios2_gen2_0_debug_mem_slave_readdata, -- .readdata
nios2_gen2_0_debug_mem_slave_writedata => mm_interconnect_0_nios2_gen2_0_debug_mem_slave_writedata, -- .writedata
nios2_gen2_0_debug_mem_slave_byteenable => mm_interconnect_0_nios2_gen2_0_debug_mem_slave_byteenable, -- .byteenable
nios2_gen2_0_debug_mem_slave_waitrequest => mm_interconnect_0_nios2_gen2_0_debug_mem_slave_waitrequest, -- .waitrequest
nios2_gen2_0_debug_mem_slave_debugaccess => mm_interconnect_0_nios2_gen2_0_debug_mem_slave_debugaccess, -- .debugaccess
onchip_flash_0_data_address => mm_interconnect_0_onchip_flash_0_data_address, -- onchip_flash_0_data.address
onchip_flash_0_data_read => mm_interconnect_0_onchip_flash_0_data_read, -- .read
onchip_flash_0_data_readdata => mm_interconnect_0_onchip_flash_0_data_readdata, -- .readdata
onchip_flash_0_data_burstcount => mm_interconnect_0_onchip_flash_0_data_burstcount, -- .burstcount
onchip_flash_0_data_readdatavalid => mm_interconnect_0_onchip_flash_0_data_readdatavalid, -- .readdatavalid
onchip_flash_0_data_waitrequest => mm_interconnect_0_onchip_flash_0_data_waitrequest, -- .waitrequest
onchip_memory2_0_s1_address => mm_interconnect_0_onchip_memory2_0_s1_address, -- onchip_memory2_0_s1.address
onchip_memory2_0_s1_write => mm_interconnect_0_onchip_memory2_0_s1_write, -- .write
onchip_memory2_0_s1_readdata => mm_interconnect_0_onchip_memory2_0_s1_readdata, -- .readdata
onchip_memory2_0_s1_writedata => mm_interconnect_0_onchip_memory2_0_s1_writedata, -- .writedata
onchip_memory2_0_s1_byteenable => mm_interconnect_0_onchip_memory2_0_s1_byteenable, -- .byteenable
onchip_memory2_0_s1_chipselect => mm_interconnect_0_onchip_memory2_0_s1_chipselect, -- .chipselect
onchip_memory2_0_s1_clken => mm_interconnect_0_onchip_memory2_0_s1_clken, -- .clken
pio_0_s1_address => mm_interconnect_0_pio_0_s1_address, -- pio_0_s1.address
pio_0_s1_write => mm_interconnect_0_pio_0_s1_write, -- .write
pio_0_s1_readdata => mm_interconnect_0_pio_0_s1_readdata, -- .readdata
pio_0_s1_writedata => mm_interconnect_0_pio_0_s1_writedata, -- .writedata
pio_0_s1_chipselect => mm_interconnect_0_pio_0_s1_chipselect, -- .chipselect
sega_saturn_abus_slave_0_avalon_nios_address => mm_interconnect_0_sega_saturn_abus_slave_0_avalon_nios_address, -- sega_saturn_abus_slave_0_avalon_nios.address
sega_saturn_abus_slave_0_avalon_nios_write => mm_interconnect_0_sega_saturn_abus_slave_0_avalon_nios_write, -- .write
sega_saturn_abus_slave_0_avalon_nios_read => mm_interconnect_0_sega_saturn_abus_slave_0_avalon_nios_read, -- .read
sega_saturn_abus_slave_0_avalon_nios_readdata => mm_interconnect_0_sega_saturn_abus_slave_0_avalon_nios_readdata, -- .readdata
sega_saturn_abus_slave_0_avalon_nios_writedata => mm_interconnect_0_sega_saturn_abus_slave_0_avalon_nios_writedata, -- .writedata
sega_saturn_abus_slave_0_avalon_nios_burstcount => mm_interconnect_0_sega_saturn_abus_slave_0_avalon_nios_burstcount, -- .burstcount
sega_saturn_abus_slave_0_avalon_nios_readdatavalid => mm_interconnect_0_sega_saturn_abus_slave_0_avalon_nios_readdatavalid, -- .readdatavalid
sega_saturn_abus_slave_0_avalon_nios_waitrequest => mm_interconnect_0_sega_saturn_abus_slave_0_avalon_nios_waitrequest, -- .waitrequest
uart_0_s1_address => mm_interconnect_0_uart_0_s1_address, -- uart_0_s1.address
uart_0_s1_write => mm_interconnect_0_uart_0_s1_write, -- .write
uart_0_s1_read => mm_interconnect_0_uart_0_s1_read, -- .read
uart_0_s1_readdata => mm_interconnect_0_uart_0_s1_readdata, -- .readdata
uart_0_s1_writedata => mm_interconnect_0_uart_0_s1_writedata, -- .writedata
uart_0_s1_begintransfer => mm_interconnect_0_uart_0_s1_begintransfer, -- .begintransfer
uart_0_s1_chipselect => mm_interconnect_0_uart_0_s1_chipselect -- .chipselect
);
irq_mapper : component wasca_irq_mapper
port map (
clk => altpll_0_c0_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- clk_reset.reset
receiver0_irq => irq_mapper_receiver0_irq, -- receiver0.irq
sender_irq => nios2_gen2_0_irq_irq -- sender.irq
);
rst_controller : component wasca_rst_controller
generic map (
NUM_RESET_INPUTS => 1,
OUTPUT_RESET_SYNC_EDGES => "deassert",
SYNC_DEPTH => 2,
RESET_REQUEST_PRESENT => 1,
RESET_REQ_WAIT_TIME => 1,
MIN_RST_ASSERTION_TIME => 3,
RESET_REQ_EARLY_DSRT_TIME => 1,
USE_RESET_REQUEST_IN0 => 0,
USE_RESET_REQUEST_IN1 => 0,
USE_RESET_REQUEST_IN2 => 0,
USE_RESET_REQUEST_IN3 => 0,
USE_RESET_REQUEST_IN4 => 0,
USE_RESET_REQUEST_IN5 => 0,
USE_RESET_REQUEST_IN6 => 0,
USE_RESET_REQUEST_IN7 => 0,
USE_RESET_REQUEST_IN8 => 0,
USE_RESET_REQUEST_IN9 => 0,
USE_RESET_REQUEST_IN10 => 0,
USE_RESET_REQUEST_IN11 => 0,
USE_RESET_REQUEST_IN12 => 0,
USE_RESET_REQUEST_IN13 => 0,
USE_RESET_REQUEST_IN14 => 0,
USE_RESET_REQUEST_IN15 => 0,
ADAPT_RESET_REQUEST => 0
)
port map (
reset_in0 => nios2_gen2_0_debug_reset_request_reset, -- reset_in0.reset
clk => altpll_0_c0_clk, -- clk.clk
reset_out => rst_controller_reset_out_reset, -- reset_out.reset
reset_req => rst_controller_reset_out_reset_req, -- .reset_req
reset_req_in0 => '0', -- (terminated)
reset_in1 => '0', -- (terminated)
reset_req_in1 => '0', -- (terminated)
reset_in2 => '0', -- (terminated)
reset_req_in2 => '0', -- (terminated)
reset_in3 => '0', -- (terminated)
reset_req_in3 => '0', -- (terminated)
reset_in4 => '0', -- (terminated)
reset_req_in4 => '0', -- (terminated)
reset_in5 => '0', -- (terminated)
reset_req_in5 => '0', -- (terminated)
reset_in6 => '0', -- (terminated)
reset_req_in6 => '0', -- (terminated)
reset_in7 => '0', -- (terminated)
reset_req_in7 => '0', -- (terminated)
reset_in8 => '0', -- (terminated)
reset_req_in8 => '0', -- (terminated)
reset_in9 => '0', -- (terminated)
reset_req_in9 => '0', -- (terminated)
reset_in10 => '0', -- (terminated)
reset_req_in10 => '0', -- (terminated)
reset_in11 => '0', -- (terminated)
reset_req_in11 => '0', -- (terminated)
reset_in12 => '0', -- (terminated)
reset_req_in12 => '0', -- (terminated)
reset_in13 => '0', -- (terminated)
reset_req_in13 => '0', -- (terminated)
reset_in14 => '0', -- (terminated)
reset_req_in14 => '0', -- (terminated)
reset_in15 => '0', -- (terminated)
reset_req_in15 => '0' -- (terminated)
);
rst_controller_001 : component wasca_rst_controller_001
generic map (
NUM_RESET_INPUTS => 1,
OUTPUT_RESET_SYNC_EDGES => "deassert",
SYNC_DEPTH => 2,
RESET_REQUEST_PRESENT => 0,
RESET_REQ_WAIT_TIME => 1,
MIN_RST_ASSERTION_TIME => 3,
RESET_REQ_EARLY_DSRT_TIME => 1,
USE_RESET_REQUEST_IN0 => 0,
USE_RESET_REQUEST_IN1 => 0,
USE_RESET_REQUEST_IN2 => 0,
USE_RESET_REQUEST_IN3 => 0,
USE_RESET_REQUEST_IN4 => 0,
USE_RESET_REQUEST_IN5 => 0,
USE_RESET_REQUEST_IN6 => 0,
USE_RESET_REQUEST_IN7 => 0,
USE_RESET_REQUEST_IN8 => 0,
USE_RESET_REQUEST_IN9 => 0,
USE_RESET_REQUEST_IN10 => 0,
USE_RESET_REQUEST_IN11 => 0,
USE_RESET_REQUEST_IN12 => 0,
USE_RESET_REQUEST_IN13 => 0,
USE_RESET_REQUEST_IN14 => 0,
USE_RESET_REQUEST_IN15 => 0,
ADAPT_RESET_REQUEST => 0
)
port map (
reset_in0 => nios2_gen2_0_debug_reset_request_reset, -- reset_in0.reset
clk => clk_clk, -- clk.clk
reset_out => rst_controller_001_reset_out_reset, -- reset_out.reset
reset_req => open, -- (terminated)
reset_req_in0 => '0', -- (terminated)
reset_in1 => '0', -- (terminated)
reset_req_in1 => '0', -- (terminated)
reset_in2 => '0', -- (terminated)
reset_req_in2 => '0', -- (terminated)
reset_in3 => '0', -- (terminated)
reset_req_in3 => '0', -- (terminated)
reset_in4 => '0', -- (terminated)
reset_req_in4 => '0', -- (terminated)
reset_in5 => '0', -- (terminated)
reset_req_in5 => '0', -- (terminated)
reset_in6 => '0', -- (terminated)
reset_req_in6 => '0', -- (terminated)
reset_in7 => '0', -- (terminated)
reset_req_in7 => '0', -- (terminated)
reset_in8 => '0', -- (terminated)
reset_req_in8 => '0', -- (terminated)
reset_in9 => '0', -- (terminated)
reset_req_in9 => '0', -- (terminated)
reset_in10 => '0', -- (terminated)
reset_req_in10 => '0', -- (terminated)
reset_in11 => '0', -- (terminated)
reset_req_in11 => '0', -- (terminated)
reset_in12 => '0', -- (terminated)
reset_req_in12 => '0', -- (terminated)
reset_in13 => '0', -- (terminated)
reset_req_in13 => '0', -- (terminated)
reset_in14 => '0', -- (terminated)
reset_req_in14 => '0', -- (terminated)
reset_in15 => '0', -- (terminated)
reset_req_in15 => '0' -- (terminated)
);
rst_controller_002 : component wasca_rst_controller_001
generic map (
NUM_RESET_INPUTS => 1,
OUTPUT_RESET_SYNC_EDGES => "both",
SYNC_DEPTH => 2,
RESET_REQUEST_PRESENT => 0,
RESET_REQ_WAIT_TIME => 1,
MIN_RST_ASSERTION_TIME => 3,
RESET_REQ_EARLY_DSRT_TIME => 1,
USE_RESET_REQUEST_IN0 => 0,
USE_RESET_REQUEST_IN1 => 0,
USE_RESET_REQUEST_IN2 => 0,
USE_RESET_REQUEST_IN3 => 0,
USE_RESET_REQUEST_IN4 => 0,
USE_RESET_REQUEST_IN5 => 0,
USE_RESET_REQUEST_IN6 => 0,
USE_RESET_REQUEST_IN7 => 0,
USE_RESET_REQUEST_IN8 => 0,
USE_RESET_REQUEST_IN9 => 0,
USE_RESET_REQUEST_IN10 => 0,
USE_RESET_REQUEST_IN11 => 0,
USE_RESET_REQUEST_IN12 => 0,
USE_RESET_REQUEST_IN13 => 0,
USE_RESET_REQUEST_IN14 => 0,
USE_RESET_REQUEST_IN15 => 0,
ADAPT_RESET_REQUEST => 0
)
port map (
reset_in0 => nios2_gen2_0_debug_reset_request_reset, -- reset_in0.reset
clk => altpll_0_c0_clk, -- clk.clk
reset_out => open, -- reset_out.reset
reset_req => open, -- (terminated)
reset_req_in0 => '0', -- (terminated)
reset_in1 => '0', -- (terminated)
reset_req_in1 => '0', -- (terminated)
reset_in2 => '0', -- (terminated)
reset_req_in2 => '0', -- (terminated)
reset_in3 => '0', -- (terminated)
reset_req_in3 => '0', -- (terminated)
reset_in4 => '0', -- (terminated)
reset_req_in4 => '0', -- (terminated)
reset_in5 => '0', -- (terminated)
reset_req_in5 => '0', -- (terminated)
reset_in6 => '0', -- (terminated)
reset_req_in6 => '0', -- (terminated)
reset_in7 => '0', -- (terminated)
reset_req_in7 => '0', -- (terminated)
reset_in8 => '0', -- (terminated)
reset_req_in8 => '0', -- (terminated)
reset_in9 => '0', -- (terminated)
reset_req_in9 => '0', -- (terminated)
reset_in10 => '0', -- (terminated)
reset_req_in10 => '0', -- (terminated)
reset_in11 => '0', -- (terminated)
reset_req_in11 => '0', -- (terminated)
reset_in12 => '0', -- (terminated)
reset_req_in12 => '0', -- (terminated)
reset_in13 => '0', -- (terminated)
reset_req_in13 => '0', -- (terminated)
reset_in14 => '0', -- (terminated)
reset_req_in14 => '0', -- (terminated)
reset_in15 => '0', -- (terminated)
reset_req_in15 => '0' -- (terminated)
);
mm_interconnect_0_external_sdram_controller_s1_read_ports_inv <= not mm_interconnect_0_external_sdram_controller_s1_read;
mm_interconnect_0_external_sdram_controller_s1_byteenable_ports_inv <= not mm_interconnect_0_external_sdram_controller_s1_byteenable;
mm_interconnect_0_external_sdram_controller_s1_write_ports_inv <= not mm_interconnect_0_external_sdram_controller_s1_write;
mm_interconnect_0_pio_0_s1_write_ports_inv <= not mm_interconnect_0_pio_0_s1_write;
mm_interconnect_0_uart_0_s1_read_ports_inv <= not mm_interconnect_0_uart_0_s1_read;
mm_interconnect_0_uart_0_s1_write_ports_inv <= not mm_interconnect_0_uart_0_s1_write;
rst_controller_reset_out_reset_ports_inv <= not rst_controller_reset_out_reset;
clock_116_mhz_clk <= altpll_0_c0_clk;
end architecture rtl; -- of wasca
| gpl-2.0 | 65432b9f55ebb3242ab4917643044530 | 0.453046 | 4.116535 | false | false | false | false |
impedimentToProgress/UCI-BlueChip | AttackFiles/Attacks/privEsc/lib/gaisler/pci/pcitb_monitor.vhd | 2 | 14,764 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: pcitb_monitor
-- File: pcitb_monitor.vhd
-- Author: Alf Vaerneus, Gaisler Research
-- Description: PCI Monitor.
------------------------------------------------------------------------------
-- pragma translate_off
library ieee;
use ieee.std_logic_1164.all;
library gaisler;
use gaisler.pcitb.all;
use gaisler.ambatest.all;
library grlib;
use grlib.stdlib.xorv;
entity pcitb_monitor is
generic (dbglevel : integer := 1);
port (pciin : in pci_type);
end pcitb_monitor;
architecture tb of pcitb_monitor is
constant T_O : integer := 9;
type pci_array_type is array(0 to 2) of pci_type;
type reg_type is record
pci : pci_array_type;
frame_deass : boolean;
m_wait_data_phase : boolean;
t_wait_data_phase : boolean;
stop_asserted : boolean;
device_sel : boolean;
first : boolean;
current_master : integer;
master_cnt : integer;
irdy_cnt : integer;
trdy_cnt : integer;
end record;
signal r,rin : reg_type;
signal init_done : boolean := false;
begin
init : process
begin
if init_done = false then
wait until pciin.syst.rst = '0';
wait until pciin.syst.rst = '1';
init_done <= true;
else
wait until pciin.syst.rst = '0';
init_done <= false;
end if;
end process;
comb : process(pciin)
variable i : integer;
variable v : reg_type;
begin
v := r;
v.pci(0) := pciin; v.pci(1) := r.pci(0); v.pci(2) := r.pci(1);
if r.pci(0).ifc.frame = 'H' then v.frame_deass := false;
elsif (r.pci(0).ifc.frame and not r.pci(1).ifc.frame) = '1' then v.frame_deass := true; end if;
if ((r.pci(0).ifc.trdy and r.pci(0).ifc.stop) or r.pci(0).ifc.irdy) = '0' then v.m_wait_data_phase := false;
elsif r.pci(0).ifc.irdy = '0' then v.m_wait_data_phase := true; end if;
if ((r.pci(0).ifc.trdy and r.pci(0).ifc.stop) or r.pci(0).ifc.irdy) = '0' then v.t_wait_data_phase := false;
elsif (r.pci(0).ifc.trdy and r.pci(0).ifc.stop) = '0' then v.t_wait_data_phase := true; end if;
if r.pci(0).ifc.frame = '0' and r.pci(1).ifc.frame = 'H' then
for i in 0 to 20 loop
if r.pci(0).arb.gnt(i) = '0' then v.current_master := i; end if;
end loop;
end if;
if (r.pci(0).ifc.frame and r.pci(0).ifc.irdy) = '0' then
if (r.pci(0).ifc.trdy and r.pci(0).ifc.stop) = '1' then
v.master_cnt := r.master_cnt+1;
else v.master_cnt := 0; end if;
else v.master_cnt := 0; end if;
if (r.pci(0).ifc.irdy and not r.pci(0).ifc.frame) = '1' then
v.irdy_cnt := r.irdy_cnt+1;
else v.irdy_cnt := 0; end if;
if ((r.pci(0).ifc.trdy and r.pci(0).ifc.stop) and not (r.pci(0).ifc.frame and r.pci(0).ifc.irdy)) = '1' then
v.trdy_cnt := r.trdy_cnt+1;
else v.trdy_cnt := 0; end if;
if r.pci(0).ifc.devsel = '0' then v.device_sel := true;
elsif (to_x01(r.pci(1).ifc.devsel) and not (r.pci(0).ifc.frame and r.pci(0).ifc.irdy)) = '1' then v.device_sel := false; end if;
if r.pci(0).ifc.stop = '0' then v.stop_asserted := true;
elsif r.pci(0).ifc.frame = '0' then v.stop_asserted := false; end if;
if (r.pci(1).ifc.frame = 'H' and r.pci(0).ifc.frame = '0') then v.first := true;
elsif (r.pci(0).ifc.trdy and r.pci(0).ifc.stop) = '0' then v.first := false; end if;
rin <= v;
end process;
clkprc : process(pciin.syst)
begin
if rising_edge(pciin.syst.clk) then
r <= rin;
if init_done then
if (r.pci(0).ifc.frame = '0' and r.frame_deass = true) then
if dbglevel > 0 then
assert false
report "***PCI ERROR***"
severity warning;
printf("PCI_MONITOR: FRAME# was reasserted during the same transaction.");
end if;
end if;
if (r.pci(0).ifc.frame and r.pci(0).ifc.irdy and not r.pci(1).ifc.frame) = '1' then
if dbglevel > 0 then
assert false
report "***PCI ERROR***"
severity warning;
printf("PCI_MONITOR: FRAME# was deasserted without IRDY# asserted.");
end if;
end if;
if (r.m_wait_data_phase and r.device_sel) then
if (r.pci(0).ifc.frame /= r.pci(1).ifc.frame) or (r.pci(0).ifc.irdy /= r.pci(1).ifc.irdy) then
if dbglevel > 0 then
assert false
report "***PCI ERROR***"
severity warning;
printf("PCI_MONITOR: Current master changed IRDY# or FRAME# before current data phase was completed.");
end if;
end if;
end if;
if ((r.pci(1).ifc.irdy and r.pci(1).ifc.frame and not r.pci(2).ifc.irdy) = '1' and r.stop_asserted = true) then
if not ((r.pci(1).arb.req(r.current_master) and (r.pci(0).arb.req(r.current_master) or r.pci(2).arb.req(r.current_master))) = '1') then
if dbglevel > 0 then
assert false
report "***PCI ERROR***"
severity warning;
printf("PCI_MONITOR: Current master at slot %d did not release its REQ# when the bus returned to idle state.",r.current_master);
end if;
end if;
end if;
if (r.pci(0).ifc.stop and not r.pci(1).ifc.stop and not r.pci(0).ifc.frame) = '1' then
if dbglevel > 0 then
assert false
report "***PCI ERROR***"
severity warning;
printf("PCI_MONITOR: Target did not keep STOP# asserted until FRAME# was deasserted.");
end if;
end if;
if (r.pci(0).ifc.frame and r.pci(1).ifc.frame and not r.pci(0).ifc.stop and not r.pci(1).ifc.stop) = '1' then
if dbglevel > 0 then
assert false
report "***PCI ERROR***"
severity warning;
printf("PCI_MONITOR: Target did not release STOP# after FRAME# was deasserted.");
end if;
end if;
if r.t_wait_data_phase = true then
if (r.pci(0).ifc.devsel /= r.pci(1).ifc.devsel) or (r.pci(0).ifc.trdy /= r.pci(1).ifc.trdy) or (r.pci(0).ifc.stop /= r.pci(1).ifc.stop) then
if dbglevel > 0 then
assert false
report "***PCI ERROR***"
severity warning;
printf("PCI_MONITOR: Current target changed DEVSEL#, STOP# or TRDY# before current data phase was completed.");
end if;
end if;
end if;
if (r.pci(0).ifc.frame and r.pci(0).ifc.stop and not r.pci(1).ifc.frame and not r.pci(1).ifc.stop) = '1' then
if dbglevel > 0 then
assert false
report "***PCI ERROR***"
severity warning;
printf("PCI_MONITOR: Target did not keep STOP# asserted until the last data phase.");
end if;
end if;
if (r.pci(2).ifc.frame and not (r.pci(2).ifc.trdy and r.pci(2).ifc.stop)) = '1' then
if r.pci(1).ifc.irdy = '0' then
if dbglevel > 0 then
assert false
report "***PCI ERROR***"
severity warning;
printf("PCI_MONITOR: Master kept IRDY# asserted after last data phase.");
end if;
end if;
if r.pci(1).ifc.trdy = '0' then
if dbglevel > 0 then
assert false
report "***PCI ERROR***"
severity warning;
printf("PCI_MONITOR: Target kept TRDY# asserted after last data phase.");
end if;
end if;
if r.pci(1).ifc.stop = '0' then
if dbglevel > 0 then
assert false
report "***PCI ERROR***"
severity warning;
printf("PCI_MONITOR: Target kept STOP# asserted after last data phase.");
end if;
end if;
if r.pci(1).ifc.frame /= 'H' then
if dbglevel > 0 then
assert false
report "***PCI ERROR***"
severity warning;
printf("PCI_MONITOR: Master did not tri-state FRAME# after turn-around cycle.");
end if;
end if;
if r.pci(0).ifc.irdy /= 'H' then
if dbglevel > 0 then
assert false
report "***PCI ERROR***"
severity warning;
printf("PCI_MONITOR: Master did not tri-state IRDY# after turn-around cycle.");
end if;
end if;
if r.pci(0).ifc.trdy /= 'H' then
if dbglevel > 0 then
assert false
report "***PCI ERROR***"
severity warning;
printf("PCI_MONITOR: Target did not tri-state TRDY# after turn-around cycle.");
end if;
end if;
if r.pci(0).ifc.stop /= 'H' then
if dbglevel > 0 then
assert false
report "***PCI ERROR***"
severity warning;
printf("PCI_MONITOR: Target did not tri-state STOP# after turn-around cycle.");
end if;
end if;
end if;
if (r.master_cnt > 16 and r.first = true) then
if dbglevel > 0 then
assert false
report "***PCI ERROR***"
severity warning;
printf("PCI_MONITOR: Target did not complete its initial data phase in 16 clkc.");
end if;
end if;
if r.irdy_cnt > 8 then
if dbglevel > 0 then
assert false
report "***PCI ERROR***"
severity warning;
printf("PCI_MONITOR: Master did not complete its initial data phase in 8 clkc.");
end if;
end if;
if (r.trdy_cnt > 8 and r.device_sel = true and r.first = false) then
if dbglevel > 0 then
assert false
report "***PCI ERROR***"
severity warning;
printf("PCI_MONITOR: Target did not complete a data phase in 8 clkc.");
end if;
end if;
if not r.device_sel then
if (r.pci(0).ifc.irdy and not r.pci(1).ifc.irdy) = '1' then
if dbglevel > 0 then
assert false
report "**"
severity note;
printf("PCI_MONITOR: Master abort detected.");
end if;
end if;
end if;
if ((r.pci(1).ifc.irdy = 'H' and r.pci(1).ifc.frame = '0')
or (r.pci(1).ifc.irdy or r.pci(1).ifc.trdy) = '0') then
if r.pci(0).ad.par = 'Z' then
if dbglevel > 0 then
assert false
report "***PCI ERROR***"
severity warning;
printf("PCI_MONITOR: Current Master/Target is not generating parity during a data phase.");
end if;
elsif r.pci(0).ad.par /= xorv(r.pci(1).ad.ad & r.pci(1).ad.cbe) then
if dbglevel > 0 then
assert false
report "***PCI ERROR***"
severity warning;
printf("PCI_MONITOR: Parity error detected.");
end if;
end if;
end if;
end if;
end if;
end process;
adchk : process(pciin.ad)
begin
if init_done then
-- for i in 0 to 31 loop
-- if pciin.ad.ad(i) = 'X' then
-- if dbglevel > 0 then
-- assert false
-- report " **"
-- severity warning;
-- printf("PCI_MONITOR: AD lines have multiple drivers.");
-- end if;
-- end if;
-- end loop;
for i in 0 to 3 loop
if pciin.ad.cbe(i) = 'X' then
if dbglevel > 0 then
assert false
report " **"
severity warning;
printf("PCI_MONITOR: CBE# lines have multiple drivers.");
end if;
end if;
end loop;
-- if pciin.ad.par = 'X' then
-- if dbglevel > 0 then
-- assert false
-- report " **"
-- severity warning;
-- printf("PCI_MONITOR: PAR line has multiple drivers.");
-- end if;
-- end if;
end if;
end process;
ifcchk : process(pciin.ifc)
begin
if init_done then
if pciin.ifc.frame = 'X' then
if dbglevel > 0 then
assert false
report " **"
severity warning;
printf("PCI_MONITOR: FRAME# line has multiple drivers.");
end if;
end if;
if pciin.ifc.irdy = 'X' then
if dbglevel > 0 then
assert false
report " **"
severity warning;
printf("PCI_MONITOR: IRDY# line has multiple drivers.");
end if;
end if;
if pciin.ifc.trdy = 'X' then
if dbglevel > 0 then
assert false
report " **"
severity warning;
printf("PCI_MONITOR: TRDY# line has multiple drivers.");
end if;
end if;
if pciin.ifc.stop = 'X' then
if dbglevel > 0 then
assert false
report " **"
severity warning;
printf("PCI_MONITOR: STOP# line has multiple drivers.");
end if;
end if;
if pciin.ifc.devsel = 'X' then
if dbglevel > 0 then
assert false
report " **"
severity warning;
printf("PCI_MONITOR: DEVSEL# line has multiple drivers.");
end if;
end if;
end if;
end process;
arbchk : process(pciin.arb)
variable gnt_set : boolean;
begin
gnt_set := false;
if init_done then
for i in 0 to 20 loop
if pciin.arb.gnt(i) = '0' then
if gnt_set then
if dbglevel > 0 then
assert false
report "***PCI ERROR***"
severity warning;
printf("PCI_MONITOR: GNT# is asserted for more than one PCI master.");
end if;
else gnt_set := true; end if;
end if;
end loop;
end if;
end process;
end;
-- pragma translate_on
| mit | e2abad43a14490be7727f3b4adb2d435 | 0.529938 | 3.755787 | false | false | false | false |
impedimentToProgress/UCI-BlueChip | AttackFiles/Defense/iu3Shadow.vhd | 1 | 132,747 | LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;
LIBRARY grlib;
USE grlib.sparc.all;
USE grlib.stdlib.all;
LIBRARY techmap;
USE techmap.gencomp.all;
LIBRARY gaisler;
USE gaisler.leon3.all;
USE gaisler.libiu.all;
USE gaisler.arith.all;
-- pragma translate_off
use grlib.sparc_disas.all;
-- pragma translate_on
ENTITY iu3 IS
GENERIC (
nwin : integer RANGE 2 to 32 := 8;
isets : integer RANGE 1 to 4 := 2;
dsets : integer RANGE 1 to 4 := 2;
fpu : integer RANGE 0 to 15 := 0;
v8 : integer RANGE 0 to 63 := 2;
cp : integer RANGE 0 to 1 := 0;
mac : integer RANGE 0 to 1 := 0;
dsu : integer RANGE 0 to 1 := 1;
nwp : integer RANGE 0 to 4 := 2;
pclow : integer RANGE 0 to 2 := 2;
notag : integer RANGE 0 to 1 := 0;
index : integer RANGE 0 to 15 := 0;
lddel : integer RANGE 1 to 2 := 1;
irfwt : integer RANGE 0 to 1 := 1;
disas : integer RANGE 0 to 2 := 0;
tbuf : integer RANGE 0 to 64 := 2;
pwd : integer RANGE 0 to 2 := 0;
svt : integer RANGE 0 to 1 := 1;
rstaddr : integer := 16#00000#;
smp : integer RANGE 0 to 15 := 0;
fabtech : integer RANGE 0 to NTECH := 2;
clk2x : integer := 0
);
PORT (
clk : in std_ulogic;
rstn : in std_ulogic;
holdn : in std_ulogic;
ici : out icache_in_type;
ico : in icache_out_type;
dci : out dcache_in_type;
dco : in dcache_out_type;
rfi : out iregfile_in_type;
rfo : in iregfile_out_type;
irqi : in l3_irq_in_type;
irqo : out l3_irq_out_type;
dbgi : in l3_debug_in_type;
dbgo : out l3_debug_out_type;
muli : out mul32_in_type;
mulo : in mul32_out_type;
divi : out div32_in_type;
divo : in div32_out_type;
fpo : in fpc_out_type;
fpi : out fpc_in_type;
cpo : in fpc_out_type;
cpi : out fpc_in_type;
tbo : in tracebuf_out_type;
tbi : out tracebuf_in_type;
sclk : in std_ulogic
);
END ENTITY;
ARCHITECTURE rtl OF iu3 IS
CONSTANT ISETMSB : integer := log2x ( 2 ) - 1;
CONSTANT DSETMSB : integer := log2x ( 2 ) - 1;
CONSTANT RFBITS : integer RANGE 6 to 10 := log2 ( 8 + 1 ) + 4;
CONSTANT NWINLOG2 : integer RANGE 1 to 5 := log2 ( 8 );
CONSTANT CWPOPT : boolean := ( 8 = ( 2 ** LOG2 ( 8 ) ) );
CONSTANT CWPMIN : std_logic_vector ( LOG2 ( 8 ) - 1 downto 0 ) := ( OTHERS => '0' );
CONSTANT CWPMAX : std_logic_vector ( LOG2 ( 8 ) - 1 downto 0 ) := conv_std_logic_vector ( 8 - 1 , LOG2 ( 8 ) );
CONSTANT FPEN : boolean := ( 0 /= 0 );
CONSTANT CPEN : boolean := ( 0 = 1 );
CONSTANT MULEN : boolean := ( 2 /= 0 );
CONSTANT MULTYPE : integer := ( 2 / 16 );
CONSTANT DIVEN : boolean := ( 2 /= 0 );
CONSTANT MACEN : boolean := ( 0 = 1 );
CONSTANT MACPIPE : boolean := ( 0 = 1 ) and ( 2 / 2 = 1 );
CONSTANT IMPL : integer := 15;
CONSTANT VER : integer := 3;
CONSTANT DBGUNIT : boolean := ( 1 = 1 );
CONSTANT TRACEBUF : boolean := ( 2 /= 0 );
CONSTANT TBUFBITS : integer := 10 + log2 ( 2 ) - 4;
CONSTANT PWRD1 : boolean := false;
CONSTANT PWRD2 : boolean := 0 /= 0;
CONSTANT RS1OPT : boolean := ( is_fpga ( 2 ) /= 0 );
SUBTYPE word IS std_logic_vector ( 31 downto 0 );
SUBTYPE pctype IS std_logic_vector ( 31 downto 2 );
SUBTYPE rfatype IS std_logic_vector ( LOG2 ( 8 + 1 ) + 4 - 1 downto 0 );
SUBTYPE cwptype IS std_logic_vector ( LOG2 ( 8 ) - 1 downto 0 );
TYPE icdtype IS ARRAY ( 0 to 2 - 1 ) OF word;
TYPE dcdtype IS ARRAY ( 0 to 2 - 1 ) OF word;
TYPE dc_in_type IS RECORD
signed : std_ulogic;
enaddr : std_ulogic;
read : std_ulogic;
write : std_ulogic;
lock : std_ulogic;
dsuen : std_ulogic;
size : std_logic_vector ( 1 downto 0 );
asi : std_logic_vector ( 7 downto 0 );
END RECORD;
TYPE pipeline_ctrl_type IS RECORD
pc : pctype;
inst : word;
cnt : std_logic_vector ( 1 downto 0 );
rd : rfatype;
tt : std_logic_vector ( 5 downto 0 );
trap : std_ulogic;
annul : std_ulogic;
wreg : std_ulogic;
wicc : std_ulogic;
wy : std_ulogic;
ld : std_ulogic;
pv : std_ulogic;
rett : std_ulogic;
END RECORD;
TYPE fetch_reg_type IS RECORD
pc : pctype;
branch : std_ulogic;
END RECORD;
TYPE decode_reg_type IS RECORD
pc : pctype;
inst : icdtype;
cwp : cwptype;
set : std_logic_vector ( LOG2X ( 2 ) - 1 downto 0 );
mexc : std_ulogic;
cnt : std_logic_vector ( 1 downto 0 );
pv : std_ulogic;
annul : std_ulogic;
inull : std_ulogic;
step : std_ulogic;
END RECORD;
TYPE regacc_reg_type IS RECORD
ctrl : pipeline_ctrl_type;
rs1 : std_logic_vector ( 4 downto 0 );
rfa1 : rfatype;
rfa2 : rfatype;
rsel1 : std_logic_vector ( 2 downto 0 );
rsel2 : std_logic_vector ( 2 downto 0 );
rfe1 : std_ulogic;
rfe2 : std_ulogic;
cwp : cwptype;
imm : word;
ldcheck1 : std_ulogic;
ldcheck2 : std_ulogic;
ldchkra : std_ulogic;
ldchkex : std_ulogic;
su : std_ulogic;
et : std_ulogic;
wovf : std_ulogic;
wunf : std_ulogic;
ticc : std_ulogic;
jmpl : std_ulogic;
step : std_ulogic;
mulstart : std_ulogic;
divstart : std_ulogic;
END RECORD;
TYPE execute_reg_type IS RECORD
ctrl : pipeline_ctrl_type;
op1 : word;
op2 : word;
aluop : std_logic_vector ( 2 downto 0 );
alusel : std_logic_vector ( 1 downto 0 );
aluadd : std_ulogic;
alucin : std_ulogic;
ldbp1 : std_ulogic;
ldbp2 : std_ulogic;
invop2 : std_ulogic;
shcnt : std_logic_vector ( 4 downto 0 );
sari : std_ulogic;
shleft : std_ulogic;
ymsb : std_ulogic;
rd : std_logic_vector ( 4 downto 0 );
jmpl : std_ulogic;
su : std_ulogic;
et : std_ulogic;
cwp : cwptype;
icc : std_logic_vector ( 3 downto 0 );
mulstep : std_ulogic;
mul : std_ulogic;
mac : std_ulogic;
END RECORD;
TYPE memory_reg_type IS RECORD
ctrl : pipeline_ctrl_type;
result : word;
y : word;
icc : std_logic_vector ( 3 downto 0 );
nalign : std_ulogic;
dci : dc_in_type;
werr : std_ulogic;
wcwp : std_ulogic;
irqen : std_ulogic;
irqen2 : std_ulogic;
mac : std_ulogic;
divz : std_ulogic;
su : std_ulogic;
mul : std_ulogic;
END RECORD;
TYPE exception_state IS ( run , trap , dsu1 , dsu2 );
TYPE exception_reg_type IS RECORD
ctrl : pipeline_ctrl_type;
result : word;
y : word;
icc : std_logic_vector ( 3 downto 0 );
annul_all : std_ulogic;
data : dcdtype;
set : std_logic_vector ( LOG2X ( 2 ) - 1 downto 0 );
mexc : std_ulogic;
impwp : std_ulogic;
dci : dc_in_type;
laddr : std_logic_vector ( 1 downto 0 );
rstate : exception_state;
npc : std_logic_vector ( 2 downto 0 );
intack : std_ulogic;
ipend : std_ulogic;
mac : std_ulogic;
pwd : std_ulogic;
debug : std_ulogic;
error : std_ulogic;
nerror : std_ulogic;
et : std_ulogic;
END RECORD;
TYPE dsu_registers IS RECORD
tt : std_logic_vector ( 7 downto 0 );
err : std_ulogic;
tbufcnt : std_logic_vector ( 10 + LOG2 ( 2 ) - 4 - 1 downto 0 );
asi : std_logic_vector ( 7 downto 0 );
crdy : std_logic_vector ( 2 downto 1 );
END RECORD;
TYPE irestart_register IS RECORD
addr : pctype;
pwd : std_ulogic;
END RECORD;
TYPE pwd_register_type IS RECORD
pwd : std_ulogic;
error : std_ulogic;
END RECORD;
TYPE special_register_type IS RECORD
cwp : cwptype;
icc : std_logic_vector ( 3 downto 0 );
tt : std_logic_vector ( 7 downto 0 );
tba : std_logic_vector ( 19 downto 0 );
wim : std_logic_vector ( 8 - 1 downto 0 );
pil : std_logic_vector ( 3 downto 0 );
ec : std_ulogic;
ef : std_ulogic;
ps : std_ulogic;
s : std_ulogic;
et : std_ulogic;
y : word;
asr18 : word;
svt : std_ulogic;
dwt : std_ulogic;
END RECORD;
TYPE write_reg_type IS RECORD
s : special_register_type;
result : word;
wa : rfatype;
wreg : std_ulogic;
except : std_ulogic;
END RECORD;
TYPE registers IS RECORD
f : fetch_reg_type;
d : decode_reg_type;
a : regacc_reg_type;
e : execute_reg_type;
m : memory_reg_type;
x : exception_reg_type;
w : write_reg_type;
END RECORD;
TYPE exception_type IS RECORD
pri : std_ulogic;
ill : std_ulogic;
fpdis : std_ulogic;
cpdis : std_ulogic;
wovf : std_ulogic;
wunf : std_ulogic;
ticc : std_ulogic;
END RECORD;
TYPE watchpoint_register IS RECORD
addr : std_logic_vector ( 31 downto 2 );
mask : std_logic_vector ( 31 downto 2 );
exec : std_ulogic;
imp : std_ulogic;
load : std_ulogic;
store : std_ulogic;
END RECORD;
TYPE watchpoint_registers IS ARRAY ( 0 to 3 ) OF watchpoint_register;
CONSTANT wpr_none : watchpoint_register := ( zero32 ( 31 downto 2 ) , zero32 ( 31 downto 2 ) , '0' , '0' , '0' , '0' );
FUNCTION dbgexc (
r : registers;
dbgi : l3_debug_in_type;
trap : std_ulogic;
tt : std_logic_vector ( 7 downto 0 )
) RETURN std_ulogic IS
VARIABLE dmode : std_ulogic;
BEGIN
dmode := '0';
IF ( not r.x.ctrl.annul and trap ) = '1' THEN
IF ( ( ( tt = "00" & TT_WATCH ) and ( dbgi.bwatch = '1' ) ) or ( ( dbgi.bsoft = '1' ) and ( tt = "10000001" ) ) or ( dbgi.btrapa = '1' ) or ( ( dbgi.btrape = '1' ) and not ( ( tt ( 5 downto 0 ) = TT_PRIV ) or ( tt ( 5 downto 0 ) = TT_FPDIS ) or ( tt ( 5 downto 0 ) = TT_WINOF ) or ( tt ( 5 downto 0 ) = TT_WINUF ) or ( tt ( 5 downto 4 ) = "01" ) or ( tt ( 7 ) = '1' ) ) ) or ( ( ( not r.w.s.et ) and dbgi.berror ) = '1' ) ) THEN
dmode := '1';
END IF;
END IF;
RETURN ( dmode );
END;
FUNCTION dbgerr (
r : registers;
dbgi : l3_debug_in_type;
tt : std_logic_vector ( 7 downto 0 )
) RETURN std_ulogic IS
VARIABLE err : std_ulogic;
BEGIN
err := not r.w.s.et;
IF ( ( ( dbgi.dbreak = '1' ) and ( tt = ( "00" & TT_WATCH ) ) ) or ( ( dbgi.bsoft = '1' ) and ( tt = ( "10000001" ) ) ) ) THEN
err := '0';
END IF;
RETURN ( err );
END;
PROCEDURE diagwr (
r : in registers;
dsur : in dsu_registers;
ir : in irestart_register;
dbg : in l3_debug_in_type;
wpr : in watchpoint_registers;
s : out special_register_type;
vwpr : out watchpoint_registers;
asi : out std_logic_vector ( 7 downto 0 );
pc : out pctype;
npc : out pctype;
tbufcnt : out std_logic_vector ( 10 + LOG2 ( 2 ) - 4 - 1 downto 0 );
wr : out std_ulogic;
addr : out std_logic_vector ( 9 downto 0 );
data : out word;
fpcwr : out std_ulogic
) IS
VARIABLE i : integer RANGE 0 to 3;
BEGIN
s := r.w.s;
pc := r.f.pc;
npc := ir.addr;
wr := '0';
vwpr := wpr;
asi := dsur.asi;
addr := ( OTHERS => '0' );
data := dbg.ddata;
tbufcnt := dsur.tbufcnt;
fpcwr := '0';
IF ( dbg.dsuen and dbg.denable and dbg.dwrite ) = '1' THEN
CASE dbg.daddr ( 23 downto 20 ) IS
WHEN "0001" =>
IF dbg.daddr ( 16 ) = '1' THEN
tbufcnt := dbg.ddata ( 10 + LOG2 ( 2 ) - 4 - 1 downto 0 );
END IF;
WHEN "0011" =>
IF dbg.daddr ( 12 ) = '0' THEN
wr := '1';
addr := ( OTHERS => '0' );
addr ( LOG2 ( 8 + 1 ) + 4 - 1 downto 0 ) := dbg.daddr ( LOG2 ( 8 + 1 ) + 4 + 1 downto 2 );
ELSE
fpcwr := '1';
END IF;
WHEN "0100" =>
CASE dbg.daddr ( 7 downto 6 ) IS
WHEN "00" =>
CASE dbg.daddr ( 5 downto 2 ) IS
WHEN "0000" =>
s.y := dbg.ddata;
WHEN "0001" =>
s.cwp := dbg.ddata ( LOG2 ( 8 ) - 1 downto 0 );
s.icc := dbg.ddata ( 23 downto 20 );
s.ec := dbg.ddata ( 13 );
s.pil := dbg.ddata ( 11 downto 8 );
s.s := dbg.ddata ( 7 );
s.ps := dbg.ddata ( 6 );
s.et := dbg.ddata ( 5 );
WHEN "0010" =>
s.wim := dbg.ddata ( 8 - 1 downto 0 );
WHEN "0011" =>
s.tba := dbg.ddata ( 31 downto 12 );
s.tt := dbg.ddata ( 11 downto 4 );
WHEN "0100" =>
pc := dbg.ddata ( 31 downto 2 );
WHEN "0101" =>
npc := dbg.ddata ( 31 downto 2 );
WHEN "0110" =>
fpcwr := '1';
WHEN "0111" =>
NULL;
WHEN "1001" =>
asi := dbg.ddata ( 7 downto 0 );
WHEN OTHERS =>
NULL;
END CASE;
WHEN "01" =>
CASE dbg.daddr ( 5 downto 2 ) IS
WHEN "0001" =>
s.dwt := dbg.ddata ( 14 );
s.svt := dbg.ddata ( 13 );
WHEN "0010" =>
NULL;
WHEN "1000" =>
vwpr ( 0 ).addr := dbg.ddata ( 31 downto 2 );
vwpr ( 0 ).imp := dbg.ddata ( 1 );
vwpr ( 0 ).exec := dbg.ddata ( 0 );
WHEN "1001" =>
vwpr ( 0 ).mask := dbg.ddata ( 31 downto 2 );
vwpr ( 0 ).load := dbg.ddata ( 1 );
vwpr ( 0 ).store := dbg.ddata ( 0 );
WHEN "1010" =>
vwpr ( 1 ).addr := dbg.ddata ( 31 downto 2 );
vwpr ( 1 ).imp := dbg.ddata ( 1 );
vwpr ( 1 ).exec := dbg.ddata ( 0 );
WHEN "1011" =>
vwpr ( 1 ).mask := dbg.ddata ( 31 downto 2 );
vwpr ( 1 ).load := dbg.ddata ( 1 );
vwpr ( 1 ).store := dbg.ddata ( 0 );
WHEN "1100" =>
vwpr ( 2 ).addr := dbg.ddata ( 31 downto 2 );
vwpr ( 2 ).imp := dbg.ddata ( 1 );
vwpr ( 2 ).exec := dbg.ddata ( 0 );
WHEN "1101" =>
vwpr ( 2 ).mask := dbg.ddata ( 31 downto 2 );
vwpr ( 2 ).load := dbg.ddata ( 1 );
vwpr ( 2 ).store := dbg.ddata ( 0 );
WHEN "1110" =>
vwpr ( 3 ).addr := dbg.ddata ( 31 downto 2 );
vwpr ( 3 ).imp := dbg.ddata ( 1 );
vwpr ( 3 ).exec := dbg.ddata ( 0 );
WHEN "1111" =>
vwpr ( 3 ).mask := dbg.ddata ( 31 downto 2 );
vwpr ( 3 ).load := dbg.ddata ( 1 );
vwpr ( 3 ).store := dbg.ddata ( 0 );
WHEN OTHERS =>
NULL;
END CASE;
WHEN OTHERS =>
NULL;
END CASE;
WHEN OTHERS =>
NULL;
END CASE;
END IF;
END;
FUNCTION asr17_gen (
r : in registers
) RETURN word IS
VARIABLE asr17 : word;
VARIABLE fpu2 : integer RANGE 0 to 3;
BEGIN
asr17 := zero32;
asr17 ( 31 downto 28 ) := conv_std_logic_vector ( 0 , 4 );
asr17 ( 14 ) := r.w.s.dwt;
asr17 ( 13 ) := r.w.s.svt;
fpu2 := 0;
asr17 ( 11 downto 10 ) := conv_std_logic_vector ( fpu2 , 2 );
asr17 ( 8 ) := '1';
asr17 ( 7 downto 5 ) := conv_std_logic_vector ( 2 , 3 );
asr17 ( 4 downto 0 ) := conv_std_logic_vector ( 8 - 1 , 5 );
RETURN ( asr17 );
END;
PROCEDURE diagread (
dbgi : in l3_debug_in_type;
r : in registers;
dsur : in dsu_registers;
ir : in irestart_register;
wpr : in watchpoint_registers;
rfdata : in std_logic_vector ( 31 downto 0 );
dco : in dcache_out_type;
tbufo : in tracebuf_out_type;
data : out word
) IS
VARIABLE cwp : std_logic_vector ( 4 downto 0 );
VARIABLE rd : std_logic_vector ( 4 downto 0 );
VARIABLE i : integer RANGE 0 to 3;
BEGIN
data := ( OTHERS => '0' );
cwp := ( OTHERS => '0' );
cwp ( LOG2 ( 8 ) - 1 downto 0 ) := r.w.s.cwp;
CASE dbgi.daddr ( 22 downto 20 ) IS
WHEN "001" =>
IF dbgi.daddr ( 16 ) = '1' THEN
data ( 10 + LOG2 ( 2 ) - 4 - 1 downto 0 ) := dsur.tbufcnt;
ELSE
CASE dbgi.daddr ( 3 downto 2 ) IS
WHEN "00" =>
data := tbufo.data ( 127 downto 96 );
WHEN "01" =>
data := tbufo.data ( 95 downto 64 );
WHEN "10" =>
data := tbufo.data ( 63 downto 32 );
WHEN OTHERS =>
data := tbufo.data ( 31 downto 0 );
END CASE;
END IF;
WHEN "011" =>
IF dbgi.daddr ( 12 ) = '0' THEN
data := rfdata ( 31 downto 0 );
ELSE
data := fpo.dbg.data;
END IF;
WHEN "100" =>
CASE dbgi.daddr ( 7 downto 6 ) IS
WHEN "00" =>
CASE dbgi.daddr ( 5 downto 2 ) IS
WHEN "0000" =>
data := r.w.s.y;
WHEN "0001" =>
data := conv_std_logic_vector ( 15 , 4 ) & conv_std_logic_vector ( 3 , 4 ) & r.w.s.icc & "000000" & r.w.s.ec & r.w.s.ef & r.w.s.pil & r.w.s.s & r.w.s.ps & r.w.s.et & cwp;
WHEN "0010" =>
data ( 8 - 1 downto 0 ) := r.w.s.wim;
WHEN "0011" =>
data := r.w.s.tba & r.w.s.tt & "0000";
WHEN "0100" =>
data ( 31 downto 2 ) := r.f.pc;
WHEN "0101" =>
data ( 31 downto 2 ) := ir.addr;
WHEN "0110" =>
data := fpo.dbg.data;
WHEN "0111" =>
NULL;
WHEN "1000" =>
data ( 12 downto 4 ) := dsur.err & dsur.tt;
WHEN "1001" =>
data ( 7 downto 0 ) := dsur.asi;
WHEN OTHERS =>
NULL;
END CASE;
WHEN "01" =>
IF dbgi.daddr ( 5 ) = '0' THEN
IF dbgi.daddr ( 4 downto 2 ) = "001" THEN
data := asr17_gen ( r );
END IF;
ELSE
i := conv_integer ( dbgi.daddr ( 4 downto 3 ) );
IF dbgi.daddr ( 2 ) = '0' THEN
data ( 31 downto 2 ) := wpr ( i ).addr;
data ( 1 ) := wpr ( i ).imp;
data ( 0 ) := wpr ( i ).exec;
ELSE
data ( 31 downto 2 ) := wpr ( i ).mask;
data ( 1 ) := wpr ( i ).load;
data ( 0 ) := wpr ( i ).store;
END IF;
END IF;
WHEN OTHERS =>
NULL;
END CASE;
WHEN "111" =>
data := r.x.data ( conv_integer ( r.x.set ) );
WHEN OTHERS =>
NULL;
END CASE;
END;
PROCEDURE itrace (
r : in registers;
dsur : in dsu_registers;
vdsu : in dsu_registers;
res : in word;
exc : in std_ulogic;
dbgi : in l3_debug_in_type;
error : in std_ulogic;
trap : in std_ulogic;
tbufcnt : out std_logic_vector ( 10 + LOG2 ( 2 ) - 4 - 1 downto 0 );
di : out tracebuf_in_type
) IS
VARIABLE meminst : std_ulogic;
BEGIN
di.addr := ( OTHERS => '0' );
di.data := ( OTHERS => '0' );
di.enable := '0';
di.write := ( OTHERS => '0' );
tbufcnt := vdsu.tbufcnt;
meminst := r.x.ctrl.inst ( 31 ) and r.x.ctrl.inst ( 30 );
di.addr ( 10 + LOG2 ( 2 ) - 4 - 1 downto 0 ) := dsur.tbufcnt;
di.data ( 127 ) := '0';
di.data ( 126 ) := not r.x.ctrl.pv;
di.data ( 125 downto 96 ) := dbgi.timer ( 29 downto 0 );
di.data ( 95 downto 64 ) := res;
di.data ( 63 downto 34 ) := r.x.ctrl.pc ( 31 downto 2 );
di.data ( 33 ) := trap;
di.data ( 32 ) := error;
di.data ( 31 downto 0 ) := r.x.ctrl.inst;
IF ( dbgi.tenable = '0' ) or ( r.x.rstate = dsu2 ) THEN
IF ( ( dbgi.dsuen and dbgi.denable ) = '1' ) and ( dbgi.daddr ( 23 downto 20 ) & dbgi.daddr ( 16 ) = "00010" ) THEN
di.enable := '1';
di.addr ( 10 + LOG2 ( 2 ) - 4 - 1 downto 0 ) := dbgi.daddr ( 10 + LOG2 ( 2 ) - 4 - 1 + 4 downto 4 );
IF dbgi.dwrite = '1' THEN
CASE dbgi.daddr ( 3 downto 2 ) IS
WHEN "00" =>
di.write ( 3 ) := '1';
WHEN "01" =>
di.write ( 2 ) := '1';
WHEN "10" =>
di.write ( 1 ) := '1';
WHEN OTHERS =>
di.write ( 0 ) := '1';
END CASE;
di.data := dbgi.ddata & dbgi.ddata & dbgi.ddata & dbgi.ddata;
END IF;
END IF;
ELSIF ( not r.x.ctrl.annul and ( r.x.ctrl.pv or meminst ) and not r.x.debug ) = '1' THEN
di.enable := '1';
di.write := ( OTHERS => '1' );
tbufcnt := dsur.tbufcnt + 1;
END IF;
di.diag := dco.testen & "000";
IF dco.scanen = '1' THEN
di.enable := '0';
END IF;
END;
PROCEDURE dbg_cache (
holdn : in std_ulogic;
dbgi : in l3_debug_in_type;
r : in registers;
dsur : in dsu_registers;
mresult : in word;
dci : in dc_in_type;
mresult2 : out word;
dci2 : out dc_in_type
) IS
BEGIN
mresult2 := mresult;
dci2 := dci;
dci2.dsuen := '0';
IF r.x.rstate = dsu2 THEN
dci2.asi := dsur.asi;
IF ( dbgi.daddr ( 22 downto 20 ) = "111" ) and ( dbgi.dsuen = '1' ) THEN
dci2.dsuen := ( dbgi.denable or r.m.dci.dsuen ) and not dsur.crdy ( 2 );
dci2.enaddr := dbgi.denable;
dci2.size := "10";
dci2.read := '1';
dci2.write := '0';
IF ( dbgi.denable and not r.m.dci.enaddr ) = '1' THEN
mresult2 := ( OTHERS => '0' );
mresult2 ( 19 downto 2 ) := dbgi.daddr ( 19 downto 2 );
ELSE
mresult2 := dbgi.ddata;
END IF;
IF dbgi.dwrite = '1' THEN
dci2.read := '0';
dci2.write := '1';
END IF;
END IF;
END IF;
END;
PROCEDURE fpexack (
r : in registers;
fpexc : out std_ulogic
) IS
BEGIN
fpexc := '0';
END;
PROCEDURE diagrdy (
denable : in std_ulogic;
dsur : in dsu_registers;
dci : in dc_in_type;
mds : in std_ulogic;
ico : in icache_out_type;
crdy : out std_logic_vector ( 2 downto 1 )
) IS
BEGIN
crdy := dsur.crdy ( 1 ) & '0';
IF dci.dsuen = '1' THEN
CASE dsur.asi ( 4 downto 0 ) IS
WHEN ASI_ITAG | ASI_IDATA | ASI_UINST | ASI_SINST =>
crdy ( 2 ) := ico.diagrdy and not dsur.crdy ( 2 );
WHEN ASI_DTAG | ASI_MMUSNOOP_DTAG | ASI_DDATA | ASI_UDATA | ASI_SDATA =>
crdy ( 1 ) := not denable and dci.enaddr and not dsur.crdy ( 1 );
WHEN OTHERS =>
crdy ( 2 ) := dci.enaddr and denable;
END CASE;
END IF;
END;
SIGNAL r : registers;
SIGNAL rin : registers;
SIGNAL wpr : watchpoint_registers;
SIGNAL wprin : watchpoint_registers;
SIGNAL dsur : dsu_registers;
SIGNAL dsuin : dsu_registers;
SIGNAL ir : irestart_register;
SIGNAL irin : irestart_register;
SIGNAL rp : pwd_register_type;
SIGNAL rpin : pwd_register_type;
CONSTANT EXE_AND : std_logic_vector ( 2 downto 0 ) := "000";
CONSTANT EXE_XOR : std_logic_vector ( 2 downto 0 ) := "001";
CONSTANT EXE_OR : std_logic_vector ( 2 downto 0 ) := "010";
CONSTANT EXE_XNOR : std_logic_vector ( 2 downto 0 ) := "011";
CONSTANT EXE_ANDN : std_logic_vector ( 2 downto 0 ) := "100";
CONSTANT EXE_ORN : std_logic_vector ( 2 downto 0 ) := "101";
CONSTANT EXE_DIV : std_logic_vector ( 2 downto 0 ) := "110";
CONSTANT EXE_PASS1 : std_logic_vector ( 2 downto 0 ) := "000";
CONSTANT EXE_PASS2 : std_logic_vector ( 2 downto 0 ) := "001";
CONSTANT EXE_STB : std_logic_vector ( 2 downto 0 ) := "010";
CONSTANT EXE_STH : std_logic_vector ( 2 downto 0 ) := "011";
CONSTANT EXE_ONES : std_logic_vector ( 2 downto 0 ) := "100";
CONSTANT EXE_RDY : std_logic_vector ( 2 downto 0 ) := "101";
CONSTANT EXE_SPR : std_logic_vector ( 2 downto 0 ) := "110";
CONSTANT EXE_LINK : std_logic_vector ( 2 downto 0 ) := "111";
CONSTANT EXE_SLL : std_logic_vector ( 2 downto 0 ) := "001";
CONSTANT EXE_SRL : std_logic_vector ( 2 downto 0 ) := "010";
CONSTANT EXE_SRA : std_logic_vector ( 2 downto 0 ) := "100";
CONSTANT EXE_NOP : std_logic_vector ( 2 downto 0 ) := "000";
CONSTANT EXE_RES_ADD : std_logic_vector ( 1 downto 0 ) := "00";
CONSTANT EXE_RES_SHIFT : std_logic_vector ( 1 downto 0 ) := "01";
CONSTANT EXE_RES_LOGIC : std_logic_vector ( 1 downto 0 ) := "10";
CONSTANT EXE_RES_MISC : std_logic_vector ( 1 downto 0 ) := "11";
CONSTANT SZBYTE : std_logic_vector ( 1 downto 0 ) := "00";
CONSTANT SZHALF : std_logic_vector ( 1 downto 0 ) := "01";
CONSTANT SZWORD : std_logic_vector ( 1 downto 0 ) := "10";
CONSTANT SZDBL : std_logic_vector ( 1 downto 0 ) := "11";
PROCEDURE regaddr (
cwp : std_logic_vector;
reg : std_logic_vector ( 4 downto 0 );
rao : out rfatype
) IS
VARIABLE ra : rfatype;
CONSTANT globals : std_logic_vector ( LOG2 ( 8 + 1 ) + 4 - 5 downto 0 ) := conv_std_logic_vector ( 8 , LOG2 ( 8 + 1 ) + 4 - 4 );
BEGIN
ra := ( OTHERS => '0' );
ra ( 4 downto 0 ) := reg;
IF reg ( 4 downto 3 ) = "00" THEN
ra ( LOG2 ( 8 + 1 ) + 4 - 1 downto 4 ) := CONV_STD_LOGIC_VECTOR ( 8 , LOG2 ( 8 + 1 ) + 4 - 4 );
ELSE
ra ( LOG2 ( 8 ) + 3 downto 4 ) := cwp + ra ( 4 );
END IF;
rao := ra;
END;
FUNCTION branch_address (
inst : word;
pc : pctype
) RETURN std_logic_vector IS
VARIABLE baddr : pctype;
VARIABLE caddr : pctype;
VARIABLE tmp : pctype;
BEGIN
caddr := ( OTHERS => '0' );
caddr ( 31 downto 2 ) := inst ( 29 downto 0 );
caddr ( 31 downto 2 ) := caddr ( 31 downto 2 ) + pc ( 31 downto 2 );
baddr := ( OTHERS => '0' );
baddr ( 31 downto 24 ) := ( OTHERS => inst ( 21 ) );
baddr ( 23 downto 2 ) := inst ( 21 downto 0 );
baddr ( 31 downto 2 ) := baddr ( 31 downto 2 ) + pc ( 31 downto 2 );
IF inst ( 30 ) = '1' THEN
tmp := caddr;
ELSE
tmp := baddr;
END IF;
RETURN ( tmp );
END;
FUNCTION branch_true (
icc : std_logic_vector ( 3 downto 0 );
inst : word
) RETURN std_ulogic IS
VARIABLE n : std_ulogic;
VARIABLE z : std_ulogic;
VARIABLE v : std_ulogic;
VARIABLE c : std_ulogic;
VARIABLE branch : std_ulogic;
BEGIN
n := icc ( 3 );
z := icc ( 2 );
v := icc ( 1 );
c := icc ( 0 );
CASE inst ( 27 downto 25 ) IS
WHEN "000" =>
branch := inst ( 28 ) xor '0';
WHEN "001" =>
branch := inst ( 28 ) xor z;
WHEN "010" =>
branch := inst ( 28 ) xor ( z or ( n xor v ) );
WHEN "011" =>
branch := inst ( 28 ) xor ( n xor v );
WHEN "100" =>
branch := inst ( 28 ) xor ( c or z );
WHEN "101" =>
branch := inst ( 28 ) xor c;
WHEN "110" =>
branch := inst ( 28 ) xor n;
WHEN OTHERS =>
branch := inst ( 28 ) xor v;
END CASE;
RETURN ( branch );
END;
PROCEDURE su_et_select (
r : in registers;
xc_ps : in std_ulogic;
xc_s : in std_ulogic;
xc_et : in std_ulogic;
su : out std_ulogic;
et : out std_ulogic
) IS
BEGIN
IF ( ( r.a.ctrl.rett or r.e.ctrl.rett or r.m.ctrl.rett or r.x.ctrl.rett ) = '1' ) and ( r.x.annul_all = '0' ) THEN
su := xc_ps;
et := '1';
ELSE
su := xc_s;
et := xc_et;
END IF;
END;
FUNCTION wphit (
r : registers;
wpr : watchpoint_registers;
debug : l3_debug_in_type
) RETURN std_ulogic IS
VARIABLE exc : std_ulogic;
BEGIN
exc := '0';
IF ( ( wpr ( 0 ).exec and r.a.ctrl.pv and not r.a.ctrl.annul ) = '1' ) THEN
IF ( ( ( wpr ( 0 ).addr xor r.a.ctrl.pc ( 31 downto 2 ) ) and wpr ( 0 ).mask ) = Zero32 ( 31 downto 2 ) ) THEN
exc := '1';
END IF;
END IF;
IF ( ( wpr ( 1 ).exec and r.a.ctrl.pv and not r.a.ctrl.annul ) = '1' ) THEN
IF ( ( ( wpr ( 1 ).addr xor r.a.ctrl.pc ( 31 downto 2 ) ) and wpr ( 1 ).mask ) = Zero32 ( 31 downto 2 ) ) THEN
exc := '1';
END IF;
END IF;
IF ( debug.dsuen and not r.a.ctrl.annul ) = '1' THEN
exc := exc or ( r.a.ctrl.pv and ( ( debug.dbreak and debug.bwatch ) or r.a.step ) );
END IF;
RETURN ( exc );
END;
FUNCTION shift3 (
r : registers;
aluin1 : word;
aluin2 : word
) RETURN word IS
VARIABLE shiftin : unsigned ( 63 downto 0 );
VARIABLE shiftout : unsigned ( 63 downto 0 );
VARIABLE cnt : natural RANGE 0 to 31;
BEGIN
cnt := conv_integer ( r.e.shcnt );
IF r.e.shleft = '1' THEN
shiftin ( 30 downto 0 ) := ( OTHERS => '0' );
shiftin ( 63 downto 31 ) := '0' & unsigned ( aluin1 );
ELSE
shiftin ( 63 downto 32 ) := ( OTHERS => r.e.sari );
shiftin ( 31 downto 0 ) := unsigned ( aluin1 );
END IF;
shiftout := SHIFT_RIGHT ( shiftin , cnt );
RETURN ( std_logic_vector ( shiftout ( 31 downto 0 ) ) );
END;
FUNCTION shift2 (
r : registers;
aluin1 : word;
aluin2 : word
) RETURN word IS
VARIABLE ushiftin : unsigned ( 31 downto 0 );
VARIABLE sshiftin : signed ( 32 downto 0 );
VARIABLE cnt : natural RANGE 0 to 31;
BEGIN
cnt := conv_integer ( r.e.shcnt );
ushiftin := unsigned ( aluin1 );
sshiftin := signed ( '0' & aluin1 );
IF r.e.shleft = '1' THEN
RETURN ( std_logic_vector ( SHIFT_LEFT ( ushiftin , cnt ) ) );
ELSE
IF r.e.sari = '1' THEN
sshiftin ( 32 ) := aluin1 ( 31 );
END IF;
sshiftin := SHIFT_RIGHT ( sshiftin , cnt );
RETURN ( std_logic_vector ( sshiftin ( 31 downto 0 ) ) );
END IF;
END;
FUNCTION shift (
r : registers;
aluin1 : word;
aluin2 : word;
shiftcnt : std_logic_vector ( 4 downto 0 );
sari : std_ulogic
) RETURN word IS
VARIABLE shiftin : std_logic_vector ( 63 downto 0 );
BEGIN
shiftin := zero32 & aluin1;
IF r.e.shleft = '1' THEN
shiftin ( 31 downto 0 ) := zero32;
shiftin ( 63 downto 31 ) := '0' & aluin1;
ELSE
shiftin ( 63 downto 32 ) := ( OTHERS => sari );
END IF;
IF shiftcnt ( 4 ) = '1' THEN
shiftin ( 47 downto 0 ) := shiftin ( 63 downto 16 );
END IF;
IF shiftcnt ( 3 ) = '1' THEN
shiftin ( 39 downto 0 ) := shiftin ( 47 downto 8 );
END IF;
IF shiftcnt ( 2 ) = '1' THEN
shiftin ( 35 downto 0 ) := shiftin ( 39 downto 4 );
END IF;
IF shiftcnt ( 1 ) = '1' THEN
shiftin ( 33 downto 0 ) := shiftin ( 35 downto 2 );
END IF;
IF shiftcnt ( 0 ) = '1' THEN
shiftin ( 31 downto 0 ) := shiftin ( 32 downto 1 );
END IF;
RETURN ( shiftin ( 31 downto 0 ) );
END;
PROCEDURE exception_detect (
r : registers;
wpr : watchpoint_registers;
dbgi : l3_debug_in_type;
trapin : in std_ulogic;
ttin : in std_logic_vector ( 5 downto 0 );
trap : out std_ulogic;
tt : out std_logic_vector ( 5 downto 0 )
) IS
VARIABLE illegal_inst : std_ulogic;
VARIABLE privileged_inst : std_ulogic;
VARIABLE cp_disabled : std_ulogic;
VARIABLE fp_disabled : std_ulogic;
VARIABLE fpop : std_ulogic;
VARIABLE op : std_logic_vector ( 1 downto 0 );
VARIABLE op2 : std_logic_vector ( 2 downto 0 );
VARIABLE op3 : std_logic_vector ( 5 downto 0 );
VARIABLE rd : std_logic_vector ( 4 downto 0 );
VARIABLE inst : word;
VARIABLE wph : std_ulogic;
BEGIN
inst := r.a.ctrl.inst;
trap := trapin;
tt := ttin;
IF r.a.ctrl.annul = '0' THEN
op := inst ( 31 downto 30 );
op2 := inst ( 24 downto 22 );
op3 := inst ( 24 downto 19 );
rd := inst ( 29 downto 25 );
illegal_inst := '0';
privileged_inst := '0';
cp_disabled := '0';
fp_disabled := '0';
fpop := '0';
CASE op IS
WHEN CALL =>
NULL;
WHEN FMT2 =>
CASE op2 IS
WHEN SETHI | BICC =>
NULL;
WHEN FBFCC =>
fp_disabled := '1';
WHEN CBCCC =>
cp_disabled := '1';
WHEN OTHERS =>
illegal_inst := '1';
END CASE;
WHEN FMT3 =>
CASE op3 IS
WHEN IAND | ANDCC | ANDN | ANDNCC | IOR | ORCC | ORN | ORNCC | IXOR | XORCC | IXNOR | XNORCC | ISLL | ISRL | ISRA | MULSCC | IADD | ADDX | ADDCC | ADDXCC | ISUB | SUBX | SUBCC | SUBXCC | FLUSH | JMPL | TICC | SAVE | RESTORE | RDY =>
NULL;
WHEN TADDCC | TADDCCTV | TSUBCC | TSUBCCTV =>
NULL;
WHEN UMAC | SMAC =>
illegal_inst := '1';
WHEN UMUL | SMUL | UMULCC | SMULCC =>
NULL;
WHEN UDIV | SDIV | UDIVCC | SDIVCC =>
NULL;
WHEN RETT =>
illegal_inst := r.a.et;
privileged_inst := not r.a.su;
WHEN RDPSR | RDTBR | RDWIM =>
privileged_inst := not r.a.su;
WHEN WRY =>
NULL;
WHEN WRPSR =>
privileged_inst := not r.a.su;
WHEN WRWIM | WRTBR =>
privileged_inst := not r.a.su;
WHEN FPOP1 | FPOP2 =>
fp_disabled := '1';
fpop := '0';
WHEN CPOP1 | CPOP2 =>
cp_disabled := '1';
WHEN OTHERS =>
illegal_inst := '1';
END CASE;
WHEN OTHERS =>
CASE op3 IS
WHEN LDD | ISTD =>
illegal_inst := rd ( 0 );
WHEN LD | LDUB | LDSTUB | LDUH | LDSB | LDSH | ST | STB | STH | SWAP =>
NULL;
WHEN LDDA | STDA =>
illegal_inst := inst ( 13 ) or rd ( 0 );
privileged_inst := not r.a.su;
WHEN LDA | LDUBA | LDSTUBA | LDUHA | LDSBA | LDSHA | STA | STBA | STHA | SWAPA =>
illegal_inst := inst ( 13 );
privileged_inst := not r.a.su;
WHEN LDDF | STDF | LDF | LDFSR | STF | STFSR =>
fp_disabled := '1';
WHEN STDFQ =>
privileged_inst := not r.a.su;
fp_disabled := '1';
WHEN STDCQ =>
privileged_inst := not r.a.su;
cp_disabled := '1';
WHEN LDC | LDCSR | LDDC | STC | STCSR | STDC =>
cp_disabled := '1';
WHEN OTHERS =>
illegal_inst := '1';
END CASE;
END CASE;
wph := wphit ( r , wpr , dbgi );
trap := '1';
IF r.a.ctrl.trap = '1' THEN
tt := TT_IAEX;
ELSIF privileged_inst = '1' THEN
tt := TT_PRIV;
ELSIF illegal_inst = '1' THEN
tt := TT_IINST;
ELSIF fp_disabled = '1' THEN
tt := TT_FPDIS;
ELSIF cp_disabled = '1' THEN
tt := TT_CPDIS;
ELSIF wph = '1' THEN
tt := TT_WATCH;
ELSIF r.a.wovf = '1' THEN
tt := TT_WINOF;
ELSIF r.a.wunf = '1' THEN
tt := TT_WINUF;
ELSIF r.a.ticc = '1' THEN
tt := TT_TICC;
ELSE
trap := '0';
tt := ( OTHERS => '0' );
END IF;
END IF;
END;
PROCEDURE wicc_y_gen (
inst : word;
wicc : out std_ulogic;
wy : out std_ulogic
) IS
BEGIN
wicc := '0';
wy := '0';
IF inst ( 31 downto 30 ) = FMT3 THEN
CASE inst ( 24 downto 19 ) IS
WHEN SUBCC | TSUBCC | TSUBCCTV | ADDCC | ANDCC | ORCC | XORCC | ANDNCC | ORNCC | XNORCC | TADDCC | TADDCCTV | ADDXCC | SUBXCC | WRPSR =>
wicc := '1';
WHEN WRY =>
IF r.d.inst ( conv_integer ( r.d.set ) ) ( 29 downto 25 ) = "00000" THEN
wy := '1';
END IF;
WHEN MULSCC =>
wicc := '1';
wy := '1';
WHEN UMAC | SMAC =>
NULL;
WHEN UMULCC | SMULCC =>
IF ( mulo.nready = '1' ) and ( r.d.cnt /= "00" ) THEN
wicc := '1';
wy := '1';
END IF;
WHEN UMUL | SMUL =>
IF ( mulo.nready = '1' ) and ( r.d.cnt /= "00" ) THEN
wy := '1';
END IF;
WHEN UDIVCC | SDIVCC =>
IF ( divo.nready = '1' ) and ( r.d.cnt /= "00" ) THEN
wicc := '1';
END IF;
WHEN OTHERS =>
NULL;
END CASE;
END IF;
END;
PROCEDURE cwp_gen (
r : registers;
v : registers;
annul : std_ulogic;
wcwp : std_ulogic;
ncwp : cwptype;
cwp : out cwptype
) IS
BEGIN
IF ( r.x.rstate = trap ) or ( r.x.rstate = dsu2 ) or ( rstn = '0' ) THEN
cwp := v.w.s.cwp;
ELSIF ( wcwp = '1' ) and ( annul = '0' ) THEN
cwp := ncwp;
ELSIF r.m.wcwp = '1' THEN
cwp := r.m.result ( LOG2 ( 8 ) - 1 downto 0 );
ELSE
cwp := r.d.cwp;
END IF;
END;
PROCEDURE cwp_ex (
r : in registers;
wcwp : out std_ulogic
) IS
BEGIN
IF ( r.e.ctrl.inst ( 31 downto 30 ) = FMT3 ) and ( r.e.ctrl.inst ( 24 downto 19 ) = WRPSR ) THEN
wcwp := not r.e.ctrl.annul;
ELSE
wcwp := '0';
END IF;
END;
PROCEDURE cwp_ctrl (
r : in registers;
xc_wim : in std_logic_vector ( 8 - 1 downto 0 );
inst : word;
de_cwp : out cwptype;
wovf_exc : out std_ulogic;
wunf_exc : out std_ulogic;
wcwp : out std_ulogic
) IS
VARIABLE op : std_logic_vector ( 1 downto 0 );
VARIABLE op3 : std_logic_vector ( 5 downto 0 );
VARIABLE wim : word;
VARIABLE ncwp : cwptype;
BEGIN
op := inst ( 31 downto 30 );
op3 := inst ( 24 downto 19 );
wovf_exc := '0';
wunf_exc := '0';
wim := ( OTHERS => '0' );
wim ( 8 - 1 downto 0 ) := xc_wim;
ncwp := r.d.cwp;
wcwp := '0';
IF ( op = FMT3 ) and ( ( op3 = RETT ) or ( op3 = RESTORE ) or ( op3 = SAVE ) ) THEN
wcwp := '1';
IF ( op3 = SAVE ) THEN
ncwp := r.d.cwp - 1;
ELSE
ncwp := r.d.cwp + 1;
END IF;
IF wim ( conv_integer ( ncwp ) ) = '1' THEN
IF op3 = SAVE THEN
wovf_exc := '1';
ELSE
wunf_exc := '1';
END IF;
END IF;
END IF;
de_cwp := ncwp;
END;
PROCEDURE rs1_gen (
r : registers;
inst : word;
rs1 : out std_logic_vector ( 4 downto 0 );
rs1mod : out std_ulogic
) IS
VARIABLE op : std_logic_vector ( 1 downto 0 );
VARIABLE op3 : std_logic_vector ( 5 downto 0 );
BEGIN
op := inst ( 31 downto 30 );
op3 := inst ( 24 downto 19 );
rs1 := inst ( 18 downto 14 );
rs1mod := '0';
IF ( op = LDST ) THEN
IF ( ( r.d.cnt = "01" ) and ( ( op3 ( 2 ) and not op3 ( 3 ) ) = '1' ) ) or ( r.d.cnt = "10" ) THEN
rs1mod := '1';
rs1 := inst ( 29 downto 25 );
END IF;
IF ( ( r.d.cnt = "10" ) and ( op3 ( 3 downto 0 ) = "0111" ) ) THEN
rs1 ( 0 ) := '1';
END IF;
END IF;
END;
PROCEDURE lock_gen (
r : registers;
rs2 : std_logic_vector ( 4 downto 0 );
rd : std_logic_vector ( 4 downto 0 );
rfa1 : rfatype;
rfa2 : rfatype;
rfrd : rfatype;
inst : word;
fpc_lock : std_ulogic;
mulinsn : std_ulogic;
divinsn : std_ulogic;
lldcheck1 : out std_ulogic;
lldcheck2 : out std_ulogic;
lldlock : out std_ulogic;
lldchkra : out std_ulogic;
lldchkex : out std_ulogic
) IS
VARIABLE op : std_logic_vector ( 1 downto 0 );
VARIABLE op2 : std_logic_vector ( 2 downto 0 );
VARIABLE op3 : std_logic_vector ( 5 downto 0 );
VARIABLE cond : std_logic_vector ( 3 downto 0 );
VARIABLE rs1 : std_logic_vector ( 4 downto 0 );
VARIABLE i : std_ulogic;
VARIABLE ldcheck1 : std_ulogic;
VARIABLE ldcheck2 : std_ulogic;
VARIABLE ldchkra : std_ulogic;
VARIABLE ldchkex : std_ulogic;
VARIABLE ldcheck3 : std_ulogic;
VARIABLE ldlock : std_ulogic;
VARIABLE icc_check : std_ulogic;
VARIABLE bicc_hold : std_ulogic;
VARIABLE chkmul : std_ulogic;
VARIABLE y_check : std_ulogic;
VARIABLE lddlock : boolean;
BEGIN
op := inst ( 31 downto 30 );
op3 := inst ( 24 downto 19 );
op2 := inst ( 24 downto 22 );
cond := inst ( 28 downto 25 );
rs1 := inst ( 18 downto 14 );
lddlock := false;
i := inst ( 13 );
ldcheck1 := '0';
ldcheck2 := '0';
ldcheck3 := '0';
ldlock := '0';
ldchkra := '1';
ldchkex := '1';
icc_check := '0';
bicc_hold := '0';
y_check := '0';
IF ( r.d.annul = '0' ) THEN
CASE op IS
WHEN FMT2 =>
IF ( op2 = BICC ) and ( cond ( 2 downto 0 ) /= "000" ) THEN
icc_check := '1';
END IF;
WHEN FMT3 =>
ldcheck1 := '1';
ldcheck2 := not i;
CASE op3 IS
WHEN TICC =>
IF ( cond ( 2 downto 0 ) /= "000" ) THEN
icc_check := '1';
END IF;
WHEN RDY =>
ldcheck1 := '0';
ldcheck2 := '0';
WHEN RDWIM | RDTBR =>
ldcheck1 := '0';
ldcheck2 := '0';
WHEN RDPSR =>
ldcheck1 := '0';
ldcheck2 := '0';
icc_check := '1';
icc_check := '1';
WHEN SDIV | SDIVCC | UDIV | UDIVCC =>
y_check := '1';
WHEN FPOP1 | FPOP2 =>
ldcheck1 := '0';
ldcheck2 := '0';
WHEN OTHERS =>
NULL;
END CASE;
WHEN LDST =>
ldcheck1 := '1';
ldchkra := '0';
CASE r.d.cnt IS
WHEN "00" =>
ldcheck2 := not i;
ldchkra := '1';
WHEN "01" =>
ldcheck2 := not i;
WHEN OTHERS =>
ldchkex := '0';
END CASE;
IF ( op3 ( 2 downto 0 ) = "011" ) THEN
lddlock := true;
END IF;
WHEN OTHERS =>
NULL;
END CASE;
END IF;
chkmul := mulinsn;
bicc_hold := bicc_hold or ( icc_check and r.m.ctrl.wicc and ( r.m.ctrl.cnt ( 0 ) or r.m.mul ) );
bicc_hold := bicc_hold or ( y_check and ( r.a.ctrl.wy or r.e.ctrl.wy ) );
chkmul := chkmul or divinsn;
bicc_hold := bicc_hold or ( icc_check and ( r.a.ctrl.wicc or r.e.ctrl.wicc ) );
IF ( ( ( r.a.ctrl.ld or chkmul ) and r.a.ctrl.wreg and ldchkra ) = '1' ) and ( ( ( ldcheck1 = '1' ) and ( r.a.ctrl.rd = rfa1 ) ) or ( ( ldcheck2 = '1' ) and ( r.a.ctrl.rd = rfa2 ) ) or ( ( ldcheck3 = '1' ) and ( r.a.ctrl.rd = rfrd ) ) ) THEN
ldlock := '1';
END IF;
IF ( ( ( r.e.ctrl.ld or r.e.mac ) and r.e.ctrl.wreg and ldchkex ) = '1' ) and ( ( ( ldcheck1 = '1' ) and ( r.e.ctrl.rd = rfa1 ) ) or ( ( ldcheck2 = '1' ) and ( r.e.ctrl.rd = rfa2 ) ) ) THEN
ldlock := '1';
END IF;
ldlock := ldlock or bicc_hold or fpc_lock;
lldcheck1 := ldcheck1;
lldcheck2 := ldcheck2;
lldlock := ldlock;
lldchkra := ldchkra;
lldchkex := ldchkex;
END;
PROCEDURE fpbranch (
inst : in word;
fcc : in std_logic_vector ( 1 downto 0 );
branch : out std_ulogic
) IS
VARIABLE cond : std_logic_vector ( 3 downto 0 );
VARIABLE fbres : std_ulogic;
BEGIN
cond := inst ( 28 downto 25 );
CASE cond ( 2 downto 0 ) IS
WHEN "000" =>
fbres := '0';
WHEN "001" =>
fbres := fcc ( 1 ) or fcc ( 0 );
WHEN "010" =>
fbres := fcc ( 1 ) xor fcc ( 0 );
WHEN "011" =>
fbres := fcc ( 0 );
WHEN "100" =>
fbres := ( not fcc ( 1 ) ) and fcc ( 0 );
WHEN "101" =>
fbres := fcc ( 1 );
WHEN "110" =>
fbres := fcc ( 1 ) and not fcc ( 0 );
WHEN OTHERS =>
fbres := fcc ( 1 ) and fcc ( 0 );
END CASE;
branch := cond ( 3 ) xor fbres;
END;
PROCEDURE ic_ctrl (
r : registers;
inst : word;
annul_all : in std_ulogic;
ldlock : in std_ulogic;
branch_true : in std_ulogic;
fbranch_true : in std_ulogic;
cbranch_true : in std_ulogic;
fccv : in std_ulogic;
cccv : in std_ulogic;
cnt : out std_logic_vector ( 1 downto 0 );
de_pc : out pctype;
de_branch : out std_ulogic;
ctrl_annul : out std_ulogic;
de_annul : out std_ulogic;
jmpl_inst : out std_ulogic;
inull : out std_ulogic;
de_pv : out std_ulogic;
ctrl_pv : out std_ulogic;
de_hold_pc : out std_ulogic;
ticc_exception : out std_ulogic;
rett_inst : out std_ulogic;
mulstart : out std_ulogic;
divstart : out std_ulogic
) IS
VARIABLE op : std_logic_vector ( 1 downto 0 );
VARIABLE op2 : std_logic_vector ( 2 downto 0 );
VARIABLE op3 : std_logic_vector ( 5 downto 0 );
VARIABLE cond : std_logic_vector ( 3 downto 0 );
VARIABLE hold_pc : std_ulogic;
VARIABLE annul_current : std_ulogic;
VARIABLE annul_next : std_ulogic;
VARIABLE branch : std_ulogic;
VARIABLE annul : std_ulogic;
VARIABLE pv : std_ulogic;
VARIABLE de_jmpl : std_ulogic;
BEGIN
branch := '0';
annul_next := '0';
annul_current := '0';
pv := '1';
hold_pc := '0';
ticc_exception := '0';
rett_inst := '0';
op := inst ( 31 downto 30 );
op3 := inst ( 24 downto 19 );
op2 := inst ( 24 downto 22 );
cond := inst ( 28 downto 25 );
annul := inst ( 29 );
de_jmpl := '0';
cnt := "00";
mulstart := '0';
divstart := '0';
IF r.d.annul = '0' THEN
CASE inst ( 31 downto 30 ) IS
WHEN CALL =>
branch := '1';
IF r.d.inull = '1' THEN
hold_pc := '1';
annul_current := '1';
END IF;
WHEN FMT2 =>
IF ( op2 = BICC ) THEN
branch := branch_true;
IF hold_pc = '0' THEN
IF ( branch = '1' ) THEN
IF ( cond = BA ) and ( annul = '1' ) THEN
annul_next := '1';
END IF;
ELSE
annul_next := annul;
END IF;
IF r.d.inull = '1' THEN
hold_pc := '1';
annul_current := '1';
annul_next := '0';
END IF;
END IF;
END IF;
WHEN FMT3 =>
CASE op3 IS
WHEN UMUL | SMUL | UMULCC | SMULCC =>
CASE r.d.cnt IS
WHEN "00" =>
cnt := "01";
hold_pc := '1';
pv := '0';
mulstart := '1';
WHEN "01" =>
IF mulo.nready = '1' THEN
cnt := "00";
ELSE
cnt := "01";
pv := '0';
hold_pc := '1';
END IF;
WHEN OTHERS =>
NULL;
END CASE;
WHEN UDIV | SDIV | UDIVCC | SDIVCC =>
CASE r.d.cnt IS
WHEN "00" =>
cnt := "01";
hold_pc := '1';
pv := '0';
divstart := '1';
WHEN "01" =>
IF divo.nready = '1' THEN
cnt := "00";
ELSE
cnt := "01";
pv := '0';
hold_pc := '1';
END IF;
WHEN OTHERS =>
NULL;
END CASE;
WHEN TICC =>
IF branch_true = '1' THEN
ticc_exception := '1';
END IF;
WHEN RETT =>
rett_inst := '1';
WHEN JMPL =>
de_jmpl := '1';
WHEN WRY =>
IF FALSE THEN
IF inst ( 29 downto 25 ) = "10011" THEN
CASE r.d.cnt IS
WHEN "00" =>
pv := '0';
cnt := "00";
hold_pc := '1';
IF r.x.ipend = '1' THEN
cnt := "01";
END IF;
WHEN "01" =>
cnt := "00";
WHEN OTHERS =>
NULL;
END CASE;
END IF;
END IF;
WHEN OTHERS =>
NULL;
END CASE;
WHEN OTHERS =>
CASE r.d.cnt IS
WHEN "00" =>
IF ( op3 ( 2 ) = '1' ) or ( op3 ( 1 downto 0 ) = "11" ) THEN
cnt := "01";
hold_pc := '1';
pv := '0';
END IF;
WHEN "01" =>
IF ( op3 ( 2 downto 0 ) = "111" ) or ( op3 ( 3 downto 0 ) = "1101" ) or ( ( ( 0 = 1 ) or ( 0 /= 0 ) ) and ( ( op3 ( 5 ) & op3 ( 2 downto 0 ) ) = "1110" ) ) THEN
cnt := "10";
pv := '0';
hold_pc := '1';
ELSE
cnt := "00";
END IF;
WHEN "10" =>
cnt := "00";
WHEN OTHERS =>
NULL;
END CASE;
END CASE;
END IF;
IF ldlock = '1' THEN
cnt := r.d.cnt;
annul_next := '0';
pv := '1';
END IF;
hold_pc := ( hold_pc or ldlock ) and not annul_all;
IF hold_pc = '1' THEN
de_pc := r.d.pc;
ELSE
de_pc := r.f.pc;
END IF;
annul_current := ( annul_current or ldlock or annul_all );
ctrl_annul := r.d.annul or annul_all or annul_current;
pv := pv and not ( ( r.d.inull and not hold_pc ) or annul_all );
jmpl_inst := de_jmpl and not annul_current;
annul_next := ( r.d.inull and not hold_pc ) or annul_next or annul_all;
IF ( annul_next = '1' ) or ( rstn = '0' ) THEN
cnt := ( OTHERS => '0' );
END IF;
de_hold_pc := hold_pc;
de_branch := branch;
de_annul := annul_next;
de_pv := pv;
ctrl_pv := r.d.pv and not ( ( r.d.annul and not r.d.pv ) or annul_all or annul_current );
inull := ( not rstn ) or r.d.inull or hold_pc or annul_all;
END;
PROCEDURE rd_gen (
r : registers;
inst : word;
wreg : out std_ulogic;
ld : out std_ulogic;
rdo : out std_logic_vector ( 4 downto 0 )
) IS
VARIABLE write_reg : std_ulogic;
VARIABLE op : std_logic_vector ( 1 downto 0 );
VARIABLE op2 : std_logic_vector ( 2 downto 0 );
VARIABLE op3 : std_logic_vector ( 5 downto 0 );
VARIABLE rd : std_logic_vector ( 4 downto 0 );
BEGIN
op := inst ( 31 downto 30 );
op2 := inst ( 24 downto 22 );
op3 := inst ( 24 downto 19 );
write_reg := '0';
rd := inst ( 29 downto 25 );
ld := '0';
CASE op IS
WHEN CALL =>
write_reg := '1';
rd := "01111";
WHEN FMT2 =>
IF ( op2 = SETHI ) THEN
write_reg := '1';
END IF;
WHEN FMT3 =>
CASE op3 IS
WHEN UMUL | SMUL | UMULCC | SMULCC =>
IF ( ( ( mulo.nready = '1' ) and ( r.d.cnt /= "00" ) ) ) THEN
write_reg := '1';
END IF;
WHEN UDIV | SDIV | UDIVCC | SDIVCC =>
IF ( divo.nready = '1' ) and ( r.d.cnt /= "00" ) THEN
write_reg := '1';
END IF;
WHEN RETT | WRPSR | WRY | WRWIM | WRTBR | TICC | FLUSH =>
NULL;
WHEN FPOP1 | FPOP2 =>
NULL;
WHEN CPOP1 | CPOP2 =>
NULL;
WHEN OTHERS =>
write_reg := '1';
END CASE;
WHEN OTHERS =>
ld := not op3 ( 2 );
IF ( op3 ( 2 ) = '0' ) and not ( ( ( 0 = 1 ) or ( 0 /= 0 ) ) and ( op3 ( 5 ) = '1' ) ) THEN
write_reg := '1';
END IF;
CASE op3 IS
WHEN SWAP | SWAPA | LDSTUB | LDSTUBA =>
IF r.d.cnt = "00" THEN
write_reg := '1';
ld := '1';
END IF;
WHEN OTHERS =>
NULL;
END CASE;
IF r.d.cnt = "01" THEN
CASE op3 IS
WHEN LDD | LDDA | LDDC | LDDF =>
rd ( 0 ) := '1';
WHEN OTHERS =>
NULL;
END CASE;
END IF;
END CASE;
IF ( rd = "00000" ) THEN
write_reg := '0';
END IF;
wreg := write_reg;
rdo := rd;
END;
FUNCTION imm_data (
r : registers;
insn : word
) RETURN word IS
VARIABLE immediate_data : word;
VARIABLE inst : word;
BEGIN
immediate_data := ( OTHERS => '0' );
inst := insn;
CASE inst ( 31 downto 30 ) IS
WHEN FMT2 =>
immediate_data := inst ( 21 downto 0 ) & "0000000000";
WHEN OTHERS =>
immediate_data ( 31 downto 13 ) := ( OTHERS => inst ( 12 ) );
immediate_data ( 12 downto 0 ) := inst ( 12 downto 0 );
END CASE;
RETURN ( immediate_data );
END;
FUNCTION get_spr (
r : registers
) RETURN word IS
VARIABLE spr : word;
BEGIN
spr := ( OTHERS => '0' );
CASE r.e.ctrl.inst ( 24 downto 19 ) IS
WHEN RDPSR =>
spr ( 31 downto 5 ) := conv_std_logic_vector ( 15 , 4 ) & conv_std_logic_vector ( 3 , 4 ) & r.m.icc & "000000" & r.w.s.ec & r.w.s.ef & r.w.s.pil & r.e.su & r.w.s.ps & r.e.et;
spr ( LOG2 ( 8 ) - 1 downto 0 ) := r.e.cwp;
WHEN RDTBR =>
spr ( 31 downto 4 ) := r.w.s.tba & r.w.s.tt;
WHEN RDWIM =>
spr ( 8 - 1 downto 0 ) := r.w.s.wim;
WHEN OTHERS =>
NULL;
END CASE;
RETURN ( spr );
END;
FUNCTION imm_select (
inst : word
) RETURN boolean IS
VARIABLE imm : boolean;
BEGIN
imm := false;
CASE inst ( 31 downto 30 ) IS
WHEN FMT2 =>
CASE inst ( 24 downto 22 ) IS
WHEN SETHI =>
imm := true;
WHEN OTHERS =>
NULL;
END CASE;
WHEN FMT3 =>
CASE inst ( 24 downto 19 ) IS
WHEN RDWIM | RDPSR | RDTBR =>
imm := true;
WHEN OTHERS =>
IF ( inst ( 13 ) = '1' ) THEN
imm := true;
END IF;
END CASE;
WHEN LDST =>
IF ( inst ( 13 ) = '1' ) THEN
imm := true;
END IF;
WHEN OTHERS =>
NULL;
END CASE;
RETURN ( imm );
END;
PROCEDURE alu_op (
r : in registers;
iop1 : in word;
iop2 : in word;
me_icc : std_logic_vector ( 3 downto 0 );
my : std_ulogic;
ldbp : std_ulogic;
aop1 : out word;
aop2 : out word;
aluop : out std_logic_vector ( 2 downto 0 );
alusel : out std_logic_vector ( 1 downto 0 );
aluadd : out std_ulogic;
shcnt : out std_logic_vector ( 4 downto 0 );
sari : out std_ulogic;
shleft : out std_ulogic;
ymsb : out std_ulogic;
mulins : out std_ulogic;
divins : out std_ulogic;
mulstep : out std_ulogic;
macins : out std_ulogic;
ldbp2 : out std_ulogic;
invop2 : out std_ulogic
) IS
VARIABLE op : std_logic_vector ( 1 downto 0 );
VARIABLE op2 : std_logic_vector ( 2 downto 0 );
VARIABLE op3 : std_logic_vector ( 5 downto 0 );
VARIABLE rd : std_logic_vector ( 4 downto 0 );
VARIABLE icc : std_logic_vector ( 3 downto 0 );
VARIABLE y0 : std_ulogic;
BEGIN
op := r.a.ctrl.inst ( 31 downto 30 );
op2 := r.a.ctrl.inst ( 24 downto 22 );
op3 := r.a.ctrl.inst ( 24 downto 19 );
aop1 := iop1;
aop2 := iop2;
ldbp2 := ldbp;
aluop := "000";
alusel := "11";
aluadd := '1';
shcnt := iop2 ( 4 downto 0 );
sari := '0';
shleft := '0';
invop2 := '0';
ymsb := iop1 ( 0 );
mulins := '0';
divins := '0';
mulstep := '0';
macins := '0';
IF r.e.ctrl.wy = '1' THEN
y0 := my;
ELSIF r.m.ctrl.wy = '1' THEN
y0 := r.m.y ( 0 );
ELSIF r.x.ctrl.wy = '1' THEN
y0 := r.x.y ( 0 );
ELSE
y0 := r.w.s.y ( 0 );
END IF;
IF r.e.ctrl.wicc = '1' THEN
icc := me_icc;
ELSIF r.m.ctrl.wicc = '1' THEN
icc := r.m.icc;
ELSIF r.x.ctrl.wicc = '1' THEN
icc := r.x.icc;
ELSE
icc := r.w.s.icc;
END IF;
CASE op IS
WHEN CALL =>
aluop := "111";
WHEN FMT2 =>
CASE op2 IS
WHEN SETHI =>
aluop := "001";
WHEN OTHERS =>
NULL;
END CASE;
WHEN FMT3 =>
CASE op3 IS
WHEN IADD | ADDX | ADDCC | ADDXCC | TADDCC | TADDCCTV | SAVE | RESTORE | TICC | JMPL | RETT =>
alusel := "00";
WHEN ISUB | SUBX | SUBCC | SUBXCC | TSUBCC | TSUBCCTV =>
alusel := "00";
aluadd := '0';
aop2 := not iop2;
invop2 := '1';
WHEN MULSCC =>
alusel := "00";
aop1 := ( icc ( 3 ) xor icc ( 1 ) ) & iop1 ( 31 downto 1 );
IF y0 = '0' THEN
aop2 := ( OTHERS => '0' );
ldbp2 := '0';
END IF;
mulstep := '1';
WHEN UMUL | UMULCC | SMUL | SMULCC =>
mulins := '1';
WHEN UMAC | SMAC =>
NULL;
WHEN UDIV | UDIVCC | SDIV | SDIVCC =>
aluop := "110";
alusel := "10";
divins := '1';
WHEN IAND | ANDCC =>
aluop := "000";
alusel := "10";
WHEN ANDN | ANDNCC =>
aluop := "100";
alusel := "10";
WHEN IOR | ORCC =>
aluop := "010";
alusel := "10";
WHEN ORN | ORNCC =>
aluop := "101";
alusel := "10";
WHEN IXNOR | XNORCC =>
aluop := "011";
alusel := "10";
WHEN XORCC | IXOR | WRPSR | WRWIM | WRTBR | WRY =>
aluop := "001";
alusel := "10";
WHEN RDPSR | RDTBR | RDWIM =>
aluop := "110";
WHEN RDY =>
aluop := "101";
WHEN ISLL =>
aluop := "001";
alusel := "01";
shleft := '1';
shcnt := not iop2 ( 4 downto 0 );
invop2 := '1';
WHEN ISRL =>
aluop := "010";
alusel := "01";
WHEN ISRA =>
aluop := "100";
alusel := "01";
sari := iop1 ( 31 );
WHEN FPOP1 | FPOP2 =>
NULL;
WHEN OTHERS =>
NULL;
END CASE;
WHEN OTHERS =>
CASE r.a.ctrl.cnt IS
WHEN "00" =>
alusel := "00";
WHEN "01" =>
CASE op3 IS
WHEN LDD | LDDA | LDDC =>
alusel := "00";
WHEN LDDF =>
alusel := "00";
WHEN SWAP | SWAPA | LDSTUB | LDSTUBA =>
alusel := "00";
WHEN STF | STDF =>
NULL;
WHEN OTHERS =>
aluop := "000";
IF op3 ( 2 ) = '1' THEN
IF op3 ( 1 downto 0 ) = "01" THEN
aluop := "010";
ELSIF op3 ( 1 downto 0 ) = "10" THEN
aluop := "011";
END IF;
END IF;
END CASE;
WHEN "10" =>
aluop := "000";
IF op3 ( 2 ) = '1' THEN
IF ( op3 ( 3 ) and not op3 ( 1 ) ) = '1' THEN
aluop := "100";
END IF;
END IF;
WHEN OTHERS =>
NULL;
END CASE;
END CASE;
END;
FUNCTION ra_inull_gen (
r : registers;
v : registers
) RETURN std_ulogic IS
VARIABLE de_inull : std_ulogic;
BEGIN
de_inull := '0';
IF ( ( v.e.jmpl or v.e.ctrl.rett ) and not v.e.ctrl.annul and not ( r.e.jmpl and not r.e.ctrl.annul ) ) = '1' THEN
de_inull := '1';
END IF;
IF ( ( v.a.jmpl or v.a.ctrl.rett ) and not v.a.ctrl.annul and not ( r.a.jmpl and not r.a.ctrl.annul ) ) = '1' THEN
de_inull := '1';
END IF;
RETURN ( de_inull );
END;
PROCEDURE op_mux (
r : in registers;
rfd : in word;
ed : in word;
md : in word;
xd : in word;
im : in word;
rsel : in std_logic_vector ( 2 downto 0 );
ldbp : out std_ulogic;
d : out word
) IS
BEGIN
ldbp := '0';
CASE rsel IS
WHEN "000" =>
d := rfd;
WHEN "001" =>
d := ed;
WHEN "010" =>
d := md;
ldbp := r.m.ctrl.ld;
WHEN "011" =>
d := xd;
WHEN "100" =>
d := im;
WHEN "101" =>
d := ( OTHERS => '0' );
WHEN "110" =>
d := r.w.result;
WHEN OTHERS =>
d := ( OTHERS => '-' );
END CASE;
END;
PROCEDURE op_find (
r : in registers;
ldchkra : std_ulogic;
ldchkex : std_ulogic;
rs1 : std_logic_vector ( 4 downto 0 );
ra : rfatype;
im : boolean;
rfe : out std_ulogic;
osel : out std_logic_vector ( 2 downto 0 );
ldcheck : std_ulogic
) IS
BEGIN
rfe := '0';
IF im THEN
osel := "100";
ELSIF rs1 = "00000" THEN
osel := "101";
ELSIF ( ( r.a.ctrl.wreg and ldchkra ) = '1' ) and ( ra = r.a.ctrl.rd ) THEN
osel := "001";
ELSIF ( ( r.e.ctrl.wreg and ldchkex ) = '1' ) and ( ra = r.e.ctrl.rd ) THEN
osel := "010";
ELSIF r.m.ctrl.wreg = '1' and ( ra = r.m.ctrl.rd ) THEN
osel := "011";
ELSE
osel := "000";
rfe := ldcheck;
END IF;
END;
PROCEDURE cin_gen (
r : registers;
me_cin : in std_ulogic;
cin : out std_ulogic
) IS
VARIABLE op : std_logic_vector ( 1 downto 0 );
VARIABLE op3 : std_logic_vector ( 5 downto 0 );
VARIABLE ncin : std_ulogic;
BEGIN
op := r.a.ctrl.inst ( 31 downto 30 );
op3 := r.a.ctrl.inst ( 24 downto 19 );
IF r.e.ctrl.wicc = '1' THEN
ncin := me_cin;
ELSE
ncin := r.m.icc ( 0 );
END IF;
cin := '0';
CASE op IS
WHEN FMT3 =>
CASE op3 IS
WHEN ISUB | SUBCC | TSUBCC | TSUBCCTV =>
cin := '1';
WHEN ADDX | ADDXCC =>
cin := ncin;
WHEN SUBX | SUBXCC =>
cin := not ncin;
WHEN OTHERS =>
NULL;
END CASE;
WHEN OTHERS =>
NULL;
END CASE;
END;
PROCEDURE logic_op (
r : registers;
aluin1 : word;
aluin2 : word;
mey : word;
ymsb : std_ulogic;
logicres : out word;
y : out word
) IS
VARIABLE logicout : word;
BEGIN
CASE r.e.aluop IS
WHEN "000" =>
logicout := aluin1 and aluin2;
WHEN "100" =>
logicout := aluin1 and not aluin2;
WHEN "010" =>
logicout := aluin1 or aluin2;
WHEN "101" =>
logicout := aluin1 or not aluin2;
WHEN "001" =>
logicout := aluin1 xor aluin2;
WHEN "011" =>
logicout := aluin1 xor not aluin2;
WHEN "110" =>
logicout := aluin2;
WHEN OTHERS =>
logicout := ( OTHERS => '-' );
END CASE;
IF ( r.e.ctrl.wy and r.e.mulstep ) = '1' THEN
y := ymsb & r.m.y ( 31 downto 1 );
ELSIF r.e.ctrl.wy = '1' THEN
y := logicout;
ELSIF r.m.ctrl.wy = '1' THEN
y := mey;
ELSIF r.x.ctrl.wy = '1' THEN
y := r.x.y;
ELSE
y := r.w.s.y;
END IF;
logicres := logicout;
END;
PROCEDURE misc_op (
r : registers;
wpr : watchpoint_registers;
aluin1 : word;
aluin2 : word;
ldata : word;
mey : word;
mout : out word;
edata : out word
) IS
VARIABLE miscout : word;
VARIABLE bpdata : word;
VARIABLE stdata : word;
VARIABLE wpi : integer;
BEGIN
wpi := 0;
miscout := r.e.ctrl.pc ( 31 downto 2 ) & "00";
edata := aluin1;
bpdata := aluin1;
IF ( ( r.x.ctrl.wreg and r.x.ctrl.ld and not r.x.ctrl.annul ) = '1' ) and ( r.x.ctrl.rd = r.e.ctrl.rd ) and ( r.e.ctrl.inst ( 31 downto 30 ) = LDST ) and ( r.e.ctrl.cnt /= "10" ) THEN
bpdata := ldata;
END IF;
CASE r.e.aluop IS
WHEN "010" =>
miscout := bpdata ( 7 downto 0 ) & bpdata ( 7 downto 0 ) & bpdata ( 7 downto 0 ) & bpdata ( 7 downto 0 );
edata := miscout;
WHEN "011" =>
miscout := bpdata ( 15 downto 0 ) & bpdata ( 15 downto 0 );
edata := miscout;
WHEN "000" =>
miscout := bpdata;
edata := miscout;
WHEN "001" =>
miscout := aluin2;
WHEN "100" =>
miscout := ( OTHERS => '1' );
edata := miscout;
WHEN "101" =>
IF ( r.m.ctrl.wy = '1' ) THEN
miscout := mey;
ELSE
miscout := r.m.y;
END IF;
IF ( r.e.ctrl.inst ( 18 downto 17 ) = "11" ) THEN
wpi := conv_integer ( r.e.ctrl.inst ( 16 downto 15 ) );
IF r.e.ctrl.inst ( 14 ) = '0' THEN
miscout := wpr ( wpi ).addr & '0' & wpr ( wpi ).exec;
ELSE
miscout := wpr ( wpi ).mask & wpr ( wpi ).load & wpr ( wpi ).store;
END IF;
END IF;
IF ( r.e.ctrl.inst ( 18 downto 17 ) = "10" ) and ( r.e.ctrl.inst ( 14 ) = '1' ) THEN
miscout := asr17_gen ( r );
END IF;
WHEN "110" =>
miscout := get_spr ( r );
WHEN OTHERS =>
NULL;
END CASE;
mout := miscout;
END;
PROCEDURE alu_select (
r : registers;
addout : std_logic_vector ( 32 downto 0 );
op1 : word;
op2 : word;
shiftout : word;
logicout : word;
miscout : word;
res : out word;
me_icc : std_logic_vector ( 3 downto 0 );
icco : out std_logic_vector ( 3 downto 0 );
divz : out std_ulogic
) IS
VARIABLE op : std_logic_vector ( 1 downto 0 );
VARIABLE op3 : std_logic_vector ( 5 downto 0 );
VARIABLE icc : std_logic_vector ( 3 downto 0 );
VARIABLE aluresult : word;
BEGIN
op := r.e.ctrl.inst ( 31 downto 30 );
op3 := r.e.ctrl.inst ( 24 downto 19 );
icc := ( OTHERS => '0' );
CASE r.e.alusel IS
WHEN "00" =>
aluresult := addout ( 32 downto 1 );
IF r.e.aluadd = '0' THEN
icc ( 0 ) := ( ( not op1 ( 31 ) ) and not op2 ( 31 ) ) or ( addout ( 32 ) and ( ( not op1 ( 31 ) ) or not op2 ( 31 ) ) );
icc ( 1 ) := ( op1 ( 31 ) and ( op2 ( 31 ) ) and not addout ( 32 ) ) or ( addout ( 32 ) and ( not op1 ( 31 ) ) and not op2 ( 31 ) );
ELSE
icc ( 0 ) := ( op1 ( 31 ) and op2 ( 31 ) ) or ( ( not addout ( 32 ) ) and ( op1 ( 31 ) or op2 ( 31 ) ) );
icc ( 1 ) := ( op1 ( 31 ) and op2 ( 31 ) and not addout ( 32 ) ) or ( addout ( 32 ) and ( not op1 ( 31 ) ) and ( not op2 ( 31 ) ) );
END IF;
CASE op IS
WHEN FMT3 =>
CASE op3 IS
WHEN TADDCC | TADDCCTV =>
icc ( 1 ) := op1 ( 0 ) or op1 ( 1 ) or op2 ( 0 ) or op2 ( 1 ) or icc ( 1 );
WHEN TSUBCC | TSUBCCTV =>
icc ( 1 ) := op1 ( 0 ) or op1 ( 1 ) or ( not op2 ( 0 ) ) or ( not op2 ( 1 ) ) or icc ( 1 );
WHEN OTHERS =>
NULL;
END CASE;
WHEN OTHERS =>
NULL;
END CASE;
IF aluresult = zero32 THEN
icc ( 2 ) := '1';
END IF;
WHEN "01" =>
aluresult := shiftout;
WHEN "10" =>
aluresult := logicout;
IF aluresult = zero32 THEN
icc ( 2 ) := '1';
END IF;
WHEN OTHERS =>
aluresult := miscout;
END CASE;
IF r.e.jmpl = '1' THEN
aluresult := r.e.ctrl.pc ( 31 downto 2 ) & "00";
END IF;
icc ( 3 ) := aluresult ( 31 );
divz := icc ( 2 );
IF r.e.ctrl.wicc = '1' THEN
IF ( op = FMT3 ) and ( op3 = WRPSR ) THEN
icco := logicout ( 23 downto 20 );
ELSE
icco := icc;
END IF;
ELSIF r.m.ctrl.wicc = '1' THEN
icco := me_icc;
ELSIF r.x.ctrl.wicc = '1' THEN
icco := r.x.icc;
ELSE
icco := r.w.s.icc;
END IF;
res := aluresult;
END;
PROCEDURE dcache_gen (
r : registers;
v : registers;
dci : out dc_in_type;
link_pc : out std_ulogic;
jump : out std_ulogic;
force_a2 : out std_ulogic;
load : out std_ulogic
) IS
VARIABLE op : std_logic_vector ( 1 downto 0 );
VARIABLE op3 : std_logic_vector ( 5 downto 0 );
VARIABLE su : std_ulogic;
BEGIN
op := r.e.ctrl.inst ( 31 downto 30 );
op3 := r.e.ctrl.inst ( 24 downto 19 );
dci.signed := '0';
dci.lock := '0';
dci.dsuen := '0';
dci.size := "10";
IF op = LDST THEN
CASE op3 IS
WHEN LDUB | LDUBA =>
dci.size := "00";
WHEN LDSTUB | LDSTUBA =>
dci.size := "00";
dci.lock := '1';
WHEN LDUH | LDUHA =>
dci.size := "01";
WHEN LDSB | LDSBA =>
dci.size := "00";
dci.signed := '1';
WHEN LDSH | LDSHA =>
dci.size := "01";
dci.signed := '1';
WHEN LD | LDA | LDF | LDC =>
dci.size := "10";
WHEN SWAP | SWAPA =>
dci.size := "10";
dci.lock := '1';
WHEN LDD | LDDA | LDDF | LDDC =>
dci.size := "11";
WHEN STB | STBA =>
dci.size := "00";
WHEN STH | STHA =>
dci.size := "01";
WHEN ST | STA | STF =>
dci.size := "10";
WHEN ISTD | STDA =>
dci.size := "11";
WHEN STDF | STDFQ =>
NULL;
WHEN STDC | STDCQ =>
NULL;
WHEN OTHERS =>
dci.size := "10";
dci.lock := '0';
dci.signed := '0';
END CASE;
END IF;
link_pc := '0';
jump := '0';
force_a2 := '0';
load := '0';
dci.write := '0';
dci.enaddr := '0';
dci.read := not op3 ( 2 );
IF ( r.e.ctrl.annul = '0' ) THEN
CASE op IS
WHEN CALL =>
link_pc := '1';
WHEN FMT3 =>
CASE op3 IS
WHEN JMPL =>
jump := '1';
link_pc := '1';
WHEN RETT =>
jump := '1';
WHEN OTHERS =>
NULL;
END CASE;
WHEN LDST =>
CASE r.e.ctrl.cnt IS
WHEN "00" =>
dci.read := op3 ( 3 ) or not op3 ( 2 );
load := op3 ( 3 ) or not op3 ( 2 );
dci.enaddr := '1';
WHEN "01" =>
force_a2 := not op3 ( 2 );
load := not op3 ( 2 );
dci.enaddr := not op3 ( 2 );
IF op3 ( 3 downto 2 ) = "01" THEN
dci.write := '1';
END IF;
IF op3 ( 3 downto 2 ) = "11" THEN
dci.enaddr := '1';
END IF;
WHEN "10" =>
dci.write := '1';
WHEN OTHERS =>
NULL;
END CASE;
IF ( r.e.ctrl.trap or ( v.x.ctrl.trap and not v.x.ctrl.annul ) ) = '1' THEN
dci.enaddr := '0';
END IF;
WHEN OTHERS =>
NULL;
END CASE;
END IF;
IF ( ( r.x.ctrl.rett and not r.x.ctrl.annul ) = '1' ) THEN
su := r.w.s.ps;
ELSE
su := r.w.s.s;
END IF;
IF su = '1' THEN
dci.asi := "00001011";
ELSE
dci.asi := "00001010";
END IF;
IF ( op3 ( 4 ) = '1' ) and ( ( op3 ( 5 ) = '0' ) or not ( 0 = 1 ) ) THEN
dci.asi := r.e.ctrl.inst ( 12 downto 5 );
END IF;
END;
PROCEDURE fpstdata (
r : in registers;
edata : in word;
eres : in word;
fpstdata : in std_logic_vector ( 31 downto 0 );
edata2 : out word;
eres2 : out word
) IS
VARIABLE op : std_logic_vector ( 1 downto 0 );
VARIABLE op3 : std_logic_vector ( 5 downto 0 );
BEGIN
edata2 := edata;
eres2 := eres;
op := r.e.ctrl.inst ( 31 downto 30 );
op3 := r.e.ctrl.inst ( 24 downto 19 );
END;
FUNCTION ld_align (
data : dcdtype;
set : std_logic_vector ( LOG2X ( 2 ) - 1 downto 0 );
size : std_logic_vector ( 1 downto 0 );
laddr : std_logic_vector ( 1 downto 0 );
signed : std_ulogic
) RETURN word IS
VARIABLE align_data : word;
VARIABLE rdata : word;
BEGIN
align_data := data ( conv_integer ( set ) );
rdata := ( OTHERS => '0' );
CASE size IS
WHEN "00" =>
CASE laddr IS
WHEN "00" =>
rdata ( 7 downto 0 ) := align_data ( 31 downto 24 );
IF signed = '1' THEN
rdata ( 31 downto 8 ) := ( OTHERS => align_data ( 31 ) );
END IF;
WHEN "01" =>
rdata ( 7 downto 0 ) := align_data ( 23 downto 16 );
IF signed = '1' THEN
rdata ( 31 downto 8 ) := ( OTHERS => align_data ( 23 ) );
END IF;
WHEN "10" =>
rdata ( 7 downto 0 ) := align_data ( 15 downto 8 );
IF signed = '1' THEN
rdata ( 31 downto 8 ) := ( OTHERS => align_data ( 15 ) );
END IF;
WHEN OTHERS =>
rdata ( 7 downto 0 ) := align_data ( 7 downto 0 );
IF signed = '1' THEN
rdata ( 31 downto 8 ) := ( OTHERS => align_data ( 7 ) );
END IF;
END CASE;
WHEN "01" =>
IF laddr ( 1 ) = '1' THEN
rdata ( 15 downto 0 ) := align_data ( 15 downto 0 );
IF signed = '1' THEN
rdata ( 31 downto 15 ) := ( OTHERS => align_data ( 15 ) );
END IF;
ELSE
rdata ( 15 downto 0 ) := align_data ( 31 downto 16 );
IF signed = '1' THEN
rdata ( 31 downto 15 ) := ( OTHERS => align_data ( 31 ) );
END IF;
END IF;
WHEN OTHERS =>
rdata := align_data;
END CASE;
RETURN ( rdata );
END;
PROCEDURE mem_trap (
r : registers;
wpr : watchpoint_registers;
annul : in std_ulogic;
holdn : in std_ulogic;
trapout : out std_ulogic;
iflush : out std_ulogic;
nullify : out std_ulogic;
werrout : out std_ulogic;
tt : out std_logic_vector ( 5 downto 0 )
) IS
VARIABLE cwp : std_logic_vector ( LOG2 ( 8 ) - 1 downto 0 );
VARIABLE cwpx : std_logic_vector ( 5 downto LOG2 ( 8 ) );
VARIABLE op : std_logic_vector ( 1 downto 0 );
VARIABLE op2 : std_logic_vector ( 2 downto 0 );
VARIABLE op3 : std_logic_vector ( 5 downto 0 );
VARIABLE nalign_d : std_ulogic;
VARIABLE trap : std_ulogic;
VARIABLE werr : std_ulogic;
BEGIN
op := r.m.ctrl.inst ( 31 downto 30 );
op2 := r.m.ctrl.inst ( 24 downto 22 );
op3 := r.m.ctrl.inst ( 24 downto 19 );
cwpx := r.m.result ( 5 downto LOG2 ( 8 ) );
cwpx ( 5 ) := '0';
iflush := '0';
trap := r.m.ctrl.trap;
nullify := annul;
tt := r.m.ctrl.tt;
werr := ( dco.werr or r.m.werr ) and not r.w.s.dwt;
nalign_d := r.m.nalign or r.m.result ( 2 );
IF ( ( annul or trap ) /= '1' ) and ( r.m.ctrl.pv = '1' ) THEN
IF ( werr and holdn ) = '1' THEN
trap := '1';
tt := TT_DSEX;
werr := '0';
IF op = LDST THEN
nullify := '1';
END IF;
END IF;
END IF;
IF ( ( annul or trap ) /= '1' ) THEN
CASE op IS
WHEN FMT2 =>
CASE op2 IS
WHEN FBFCC =>
NULL;
WHEN CBCCC =>
NULL;
WHEN OTHERS =>
NULL;
END CASE;
WHEN FMT3 =>
CASE op3 IS
WHEN WRPSR =>
IF ( orv ( cwpx ) = '1' ) THEN
trap := '1';
tt := TT_IINST;
END IF;
WHEN UDIV | SDIV | UDIVCC | SDIVCC =>
IF r.m.divz = '1' THEN
trap := '1';
tt := TT_DIV;
END IF;
WHEN JMPL | RETT =>
IF r.m.nalign = '1' THEN
trap := '1';
tt := TT_UNALA;
END IF;
WHEN TADDCCTV | TSUBCCTV =>
IF ( r.m.icc ( 1 ) = '1' ) THEN
trap := '1';
tt := TT_TAG;
END IF;
WHEN FLUSH =>
iflush := '1';
WHEN FPOP1 | FPOP2 =>
NULL;
WHEN CPOP1 | CPOP2 =>
NULL;
WHEN OTHERS =>
NULL;
END CASE;
WHEN LDST =>
IF r.m.ctrl.cnt = "00" THEN
CASE op3 IS
WHEN LDDF | STDF | STDFQ =>
NULL;
WHEN LDDC | STDC | STDCQ =>
NULL;
WHEN LDD | ISTD | LDDA | STDA =>
IF r.m.result ( 2 downto 0 ) /= "000" THEN
trap := '1';
tt := TT_UNALA;
nullify := '1';
END IF;
WHEN LDF | LDFSR | STFSR | STF =>
NULL;
WHEN LDC | LDCSR | STCSR | STC =>
NULL;
WHEN LD | LDA | ST | STA | SWAP | SWAPA =>
IF r.m.result ( 1 downto 0 ) /= "00" THEN
trap := '1';
tt := TT_UNALA;
nullify := '1';
END IF;
WHEN LDUH | LDUHA | LDSH | LDSHA | STH | STHA =>
IF r.m.result ( 0 ) /= '0' THEN
trap := '1';
tt := TT_UNALA;
nullify := '1';
END IF;
WHEN OTHERS =>
NULL;
END CASE;
IF ( ( ( ( wpr ( 0 ).load and not op3 ( 2 ) ) or ( wpr ( 0 ).store and op3 ( 2 ) ) ) = '1' ) and ( ( ( wpr ( 0 ).addr xor r.m.result ( 31 downto 2 ) ) and wpr ( 0 ).mask ) = zero32 ( 31 downto 2 ) ) ) THEN
trap := '1';
tt := TT_WATCH;
nullify := '1';
END IF;
IF ( ( ( ( wpr ( 1 ).load and not op3 ( 2 ) ) or ( wpr ( 1 ).store and op3 ( 2 ) ) ) = '1' ) and ( ( ( wpr ( 1 ).addr xor r.m.result ( 31 downto 2 ) ) and wpr ( 1 ).mask ) = zero32 ( 31 downto 2 ) ) ) THEN
trap := '1';
tt := TT_WATCH;
nullify := '1';
END IF;
END IF;
WHEN OTHERS =>
NULL;
END CASE;
END IF;
IF ( rstn = '0' ) or ( r.x.rstate = dsu2 ) THEN
werr := '0';
END IF;
trapout := trap;
werrout := werr;
END;
PROCEDURE irq_trap (
r : in registers;
ir : in irestart_register;
irl : in std_logic_vector ( 3 downto 0 );
annul : in std_ulogic;
pv : in std_ulogic;
trap : in std_ulogic;
tt : in std_logic_vector ( 5 downto 0 );
nullify : in std_ulogic;
irqen : out std_ulogic;
irqen2 : out std_ulogic;
nullify2 : out std_ulogic;
trap2 : out std_ulogic;
ipend : out std_ulogic;
tt2 : out std_logic_vector ( 5 downto 0 )
) IS
VARIABLE op : std_logic_vector ( 1 downto 0 );
VARIABLE op3 : std_logic_vector ( 5 downto 0 );
VARIABLE pend : std_ulogic;
BEGIN
nullify2 := nullify;
trap2 := trap;
tt2 := tt;
op := r.m.ctrl.inst ( 31 downto 30 );
op3 := r.m.ctrl.inst ( 24 downto 19 );
irqen := '1';
irqen2 := r.m.irqen;
IF ( annul or trap ) = '0' THEN
IF ( ( op = FMT3 ) and ( op3 = WRPSR ) ) THEN
irqen := '0';
END IF;
END IF;
IF ( irl = "1111" ) or ( irl > r.w.s.pil ) THEN
pend := r.m.irqen and r.m.irqen2 and r.w.s.et and not ir.pwd;
ELSE
pend := '0';
END IF;
ipend := pend;
IF ( ( not annul ) and pv and ( not trap ) and pend ) = '1' THEN
trap2 := '1';
tt2 := "01" & irl;
IF op = LDST THEN
nullify2 := '1';
END IF;
END IF;
END;
PROCEDURE irq_intack (
r : in registers;
holdn : in std_ulogic;
intack : out std_ulogic
) IS
BEGIN
intack := '0';
IF r.x.rstate = trap THEN
IF r.w.s.tt ( 7 downto 4 ) = "0001" THEN
intack := '1';
END IF;
END IF;
END;
PROCEDURE sp_write (
r : registers;
wpr : watchpoint_registers;
s : out special_register_type;
vwpr : out watchpoint_registers
) IS
VARIABLE op : std_logic_vector ( 1 downto 0 );
VARIABLE op2 : std_logic_vector ( 2 downto 0 );
VARIABLE op3 : std_logic_vector ( 5 downto 0 );
VARIABLE rd : std_logic_vector ( 4 downto 0 );
VARIABLE i : integer RANGE 0 to 3;
BEGIN
op := r.x.ctrl.inst ( 31 downto 30 );
op2 := r.x.ctrl.inst ( 24 downto 22 );
op3 := r.x.ctrl.inst ( 24 downto 19 );
s := r.w.s;
rd := r.x.ctrl.inst ( 29 downto 25 );
vwpr := wpr;
CASE op IS
WHEN FMT3 =>
CASE op3 IS
WHEN WRY =>
IF rd = "00000" THEN
s.y := r.x.result;
ELSIF ( rd = "10001" ) THEN
s.dwt := r.x.result ( 14 );
s.svt := r.x.result ( 13 );
ELSIF rd ( 4 downto 3 ) = "11" THEN
CASE rd ( 2 downto 0 ) IS
WHEN "000" =>
vwpr ( 0 ).addr := r.x.result ( 31 downto 2 );
vwpr ( 0 ).imp := r.x.result ( 1 );
vwpr ( 0 ).exec := r.x.result ( 0 );
WHEN "001" =>
vwpr ( 0 ).mask := r.x.result ( 31 downto 2 );
vwpr ( 0 ).load := r.x.result ( 1 );
vwpr ( 0 ).store := r.x.result ( 0 );
WHEN "010" =>
vwpr ( 1 ).addr := r.x.result ( 31 downto 2 );
vwpr ( 1 ).imp := r.x.result ( 1 );
vwpr ( 1 ).exec := r.x.result ( 0 );
WHEN "011" =>
vwpr ( 1 ).mask := r.x.result ( 31 downto 2 );
vwpr ( 1 ).load := r.x.result ( 1 );
vwpr ( 1 ).store := r.x.result ( 0 );
WHEN "100" =>
vwpr ( 2 ).addr := r.x.result ( 31 downto 2 );
vwpr ( 2 ).imp := r.x.result ( 1 );
vwpr ( 2 ).exec := r.x.result ( 0 );
WHEN "101" =>
vwpr ( 2 ).mask := r.x.result ( 31 downto 2 );
vwpr ( 2 ).load := r.x.result ( 1 );
vwpr ( 2 ).store := r.x.result ( 0 );
WHEN "110" =>
vwpr ( 3 ).addr := r.x.result ( 31 downto 2 );
vwpr ( 3 ).imp := r.x.result ( 1 );
vwpr ( 3 ).exec := r.x.result ( 0 );
WHEN OTHERS =>
vwpr ( 3 ).mask := r.x.result ( 31 downto 2 );
vwpr ( 3 ).load := r.x.result ( 1 );
vwpr ( 3 ).store := r.x.result ( 0 );
END CASE;
END IF;
WHEN WRPSR =>
s.cwp := r.x.result ( LOG2 ( 8 ) - 1 downto 0 );
s.icc := r.x.result ( 23 downto 20 );
s.ec := r.x.result ( 13 );
s.pil := r.x.result ( 11 downto 8 );
s.s := r.x.result ( 7 );
s.ps := r.x.result ( 6 );
s.et := r.x.result ( 5 );
WHEN WRWIM =>
s.wim := r.x.result ( 8 - 1 downto 0 );
WHEN WRTBR =>
s.tba := r.x.result ( 31 downto 12 );
WHEN SAVE =>
s.cwp := r.w.s.cwp - 1;
WHEN RESTORE =>
s.cwp := r.w.s.cwp + 1;
WHEN RETT =>
s.cwp := r.w.s.cwp + 1;
s.s := r.w.s.ps;
s.et := '1';
WHEN OTHERS =>
NULL;
END CASE;
WHEN OTHERS =>
NULL;
END CASE;
IF r.x.ctrl.wicc = '1' THEN
s.icc := r.x.icc;
END IF;
IF r.x.ctrl.wy = '1' THEN
s.y := r.x.y;
END IF;
END;
FUNCTION npc_find (
r : registers
) RETURN std_logic_vector IS
VARIABLE npc : std_logic_vector ( 2 downto 0 );
BEGIN
npc := "011";
IF r.m.ctrl.pv = '1' THEN
npc := "000";
ELSIF r.e.ctrl.pv = '1' THEN
npc := "001";
ELSIF r.a.ctrl.pv = '1' THEN
npc := "010";
ELSIF r.d.pv = '1' THEN
npc := "011";
ELSE
npc := "100";
END IF;
RETURN ( npc );
END;
FUNCTION npc_gen (
r : registers
) RETURN word IS
VARIABLE npc : std_logic_vector ( 31 downto 0 );
BEGIN
npc := r.a.ctrl.pc ( 31 downto 2 ) & "00";
CASE r.x.npc IS
WHEN "000" =>
npc ( 31 downto 2 ) := r.x.ctrl.pc ( 31 downto 2 );
WHEN "001" =>
npc ( 31 downto 2 ) := r.m.ctrl.pc ( 31 downto 2 );
WHEN "010" =>
npc ( 31 downto 2 ) := r.e.ctrl.pc ( 31 downto 2 );
WHEN "011" =>
npc ( 31 downto 2 ) := r.a.ctrl.pc ( 31 downto 2 );
WHEN OTHERS =>
npc ( 31 downto 2 ) := r.d.pc ( 31 downto 2 );
END CASE;
RETURN ( npc );
END;
PROCEDURE mul_res (
r : registers;
asr18in : word;
result : out word;
y : out word;
asr18 : out word;
icc : out std_logic_vector ( 3 downto 0 )
) IS
VARIABLE op : std_logic_vector ( 1 downto 0 );
VARIABLE op3 : std_logic_vector ( 5 downto 0 );
BEGIN
op := r.m.ctrl.inst ( 31 downto 30 );
op3 := r.m.ctrl.inst ( 24 downto 19 );
result := r.m.result;
y := r.m.y;
icc := r.m.icc;
asr18 := asr18in;
CASE op IS
WHEN FMT3 =>
CASE op3 IS
WHEN UMUL | SMUL =>
result := mulo.result ( 31 downto 0 );
y := mulo.result ( 63 downto 32 );
WHEN UMULCC | SMULCC =>
result := mulo.result ( 31 downto 0 );
icc := mulo.icc;
y := mulo.result ( 63 downto 32 );
WHEN UMAC | SMAC =>
NULL;
WHEN UDIV | SDIV =>
result := divo.result ( 31 downto 0 );
WHEN UDIVCC | SDIVCC =>
result := divo.result ( 31 downto 0 );
icc := divo.icc;
WHEN OTHERS =>
NULL;
END CASE;
WHEN OTHERS =>
NULL;
END CASE;
END;
FUNCTION powerdwn (
r : registers;
trap : std_ulogic;
rp : pwd_register_type
) RETURN std_ulogic IS
VARIABLE op : std_logic_vector ( 1 downto 0 );
VARIABLE op3 : std_logic_vector ( 5 downto 0 );
VARIABLE rd : std_logic_vector ( 4 downto 0 );
VARIABLE pd : std_ulogic;
BEGIN
op := r.x.ctrl.inst ( 31 downto 30 );
op3 := r.x.ctrl.inst ( 24 downto 19 );
rd := r.x.ctrl.inst ( 29 downto 25 );
pd := '0';
IF ( not ( r.x.ctrl.annul or trap ) and r.x.ctrl.pv ) = '1' THEN
IF ( ( op = FMT3 ) and ( op3 = WRY ) and ( rd = "10011" ) ) THEN
pd := '1';
END IF;
pd := pd or rp.pwd;
END IF;
RETURN ( pd );
END;
SIGNAL dummy : std_ulogic;
SIGNAL cpu_index : std_logic_vector ( 3 downto 0 );
SIGNAL disasen : std_ulogic;
BEGIN
comb : PROCESS ( ico , dco , rfo , r , wpr , ir , dsur , rstn , holdn , irqi , dbgi , fpo , cpo , tbo , mulo , divo , dummy , rp )
VARIABLE v : registers;
VARIABLE vp : pwd_register_type;
VARIABLE vwpr : watchpoint_registers;
VARIABLE vdsu : dsu_registers;
VARIABLE npc : std_logic_vector ( 31 downto 2 );
VARIABLE de_raddr1 : std_logic_vector ( 9 downto 0 );
VARIABLE de_raddr2 : std_logic_vector ( 9 downto 0 );
VARIABLE de_rs2 : std_logic_vector ( 4 downto 0 );
VARIABLE de_rd : std_logic_vector ( 4 downto 0 );
VARIABLE de_hold_pc : std_ulogic;
VARIABLE de_branch : std_ulogic;
VARIABLE de_fpop : std_ulogic;
VARIABLE de_ldlock : std_ulogic;
VARIABLE de_cwp : cwptype;
VARIABLE de_cwp2 : cwptype;
VARIABLE de_inull : std_ulogic;
VARIABLE de_ren1 : std_ulogic;
VARIABLE de_ren2 : std_ulogic;
VARIABLE de_wcwp : std_ulogic;
VARIABLE de_inst : word;
VARIABLE de_branch_address : pctype;
VARIABLE de_icc : std_logic_vector ( 3 downto 0 );
VARIABLE de_fbranch : std_ulogic;
VARIABLE de_cbranch : std_ulogic;
VARIABLE de_rs1mod : std_ulogic;
VARIABLE ra_op1 : word;
VARIABLE ra_op2 : word;
VARIABLE ra_div : std_ulogic;
VARIABLE ex_jump : std_ulogic;
VARIABLE ex_link_pc : std_ulogic;
VARIABLE ex_jump_address : pctype;
VARIABLE ex_add_res : std_logic_vector ( 32 downto 0 );
VARIABLE ex_shift_res : word;
VARIABLE ex_logic_res : word;
VARIABLE ex_misc_res : word;
VARIABLE ex_edata : word;
VARIABLE ex_edata2 : word;
VARIABLE ex_dci : dc_in_type;
VARIABLE ex_force_a2 : std_ulogic;
VARIABLE ex_load : std_ulogic;
VARIABLE ex_ymsb : std_ulogic;
VARIABLE ex_op1 : word;
VARIABLE ex_op2 : word;
VARIABLE ex_result : word;
VARIABLE ex_result2 : word;
VARIABLE mul_op2 : word;
VARIABLE ex_shcnt : std_logic_vector ( 4 downto 0 );
VARIABLE ex_dsuen : std_ulogic;
VARIABLE ex_ldbp2 : std_ulogic;
VARIABLE ex_sari : std_ulogic;
VARIABLE me_inull : std_ulogic;
VARIABLE me_nullify : std_ulogic;
VARIABLE me_nullify2 : std_ulogic;
VARIABLE me_iflush : std_ulogic;
VARIABLE me_newtt : std_logic_vector ( 5 downto 0 );
VARIABLE me_asr18 : word;
VARIABLE me_signed : std_ulogic;
VARIABLE me_size : std_logic_vector ( 1 downto 0 );
VARIABLE me_laddr : std_logic_vector ( 1 downto 0 );
VARIABLE me_icc : std_logic_vector ( 3 downto 0 );
VARIABLE xc_result : word;
VARIABLE xc_df_result : word;
VARIABLE xc_waddr : std_logic_vector ( 9 downto 0 );
VARIABLE xc_exception : std_ulogic;
VARIABLE xc_wreg : std_ulogic;
VARIABLE xc_trap_address : pctype;
VARIABLE xc_vectt : std_logic_vector ( 7 downto 0 );
VARIABLE xc_trap : std_ulogic;
VARIABLE xc_fpexack : std_ulogic;
VARIABLE xc_rstn : std_ulogic;
VARIABLE xc_halt : std_ulogic;
VARIABLE diagdata : word;
VARIABLE tbufi : tracebuf_in_type;
VARIABLE dbgm : std_ulogic;
VARIABLE fpcdbgwr : std_ulogic;
VARIABLE vfpi : fpc_in_type;
VARIABLE dsign : std_ulogic;
VARIABLE pwrd : std_ulogic;
VARIABLE sidle : std_ulogic;
VARIABLE vir : irestart_register;
VARIABLE icnt : std_ulogic;
VARIABLE tbufcntx : std_logic_vector ( 10 + LOG2 ( 2 ) - 4 - 1 downto 0 );
BEGIN
v := r;
vwpr := wpr;
vdsu := dsur;
vp := rp;
xc_fpexack := '0';
sidle := '0';
fpcdbgwr := '0';
vir := ir;
xc_rstn := rstn;
xc_exception := '0';
xc_halt := '0';
icnt := '0';
xc_waddr := ( OTHERS => '0' );
xc_waddr ( LOG2 ( 8 + 1 ) + 4 - 1 downto 0 ) := r.x.ctrl.rd ( LOG2 ( 8 + 1 ) + 4 - 1 downto 0 );
xc_trap := r.x.mexc or r.x.ctrl.trap;
v.x.nerror := rp.error;
IF r.x.mexc = '1' THEN
xc_vectt := "00" & TT_DAEX;
ELSIF r.x.ctrl.tt = TT_TICC THEN
xc_vectt := '1' & r.x.result ( 6 downto 0 );
ELSE
xc_vectt := "00" & r.x.ctrl.tt;
END IF;
IF r.w.s.svt = '0' THEN
xc_trap_address ( 31 downto 4 ) := r.w.s.tba & xc_vectt;
ELSE
xc_trap_address ( 31 downto 4 ) := r.w.s.tba & "00000000";
END IF;
xc_trap_address ( 3 downto 2 ) := ( OTHERS => '0' );
xc_wreg := '0';
v.x.annul_all := '0';
IF ( r.x.ctrl.ld = '1' ) THEN
xc_result := r.x.data ( 0 );
ELSE
xc_result := r.x.result;
END IF;
xc_df_result := xc_result;
dbgm := dbgexc ( r , dbgi , xc_trap , xc_vectt );
IF ( dbgi.dsuen and dbgi.dbreak ) = '0' THEN
v.x.debug := '0';
END IF;
pwrd := '0';
CASE r.x.rstate IS
WHEN run =>
IF ( not r.x.ctrl.annul and r.x.ctrl.pv and not r.x.debug ) = '1' THEN
icnt := holdn;
END IF;
IF dbgm = '1' THEN
v.x.annul_all := '1';
vir.addr := r.x.ctrl.pc;
v.x.rstate := dsu1;
v.x.debug := '1';
v.x.npc := npc_find ( r );
vdsu.tt := xc_vectt;
vdsu.err := dbgerr ( r , dbgi , xc_vectt );
ELSIF ( pwrd = '1' ) and ( ir.pwd = '0' ) THEN
v.x.annul_all := '1';
vir.addr := r.x.ctrl.pc;
v.x.rstate := dsu1;
v.x.npc := npc_find ( r );
vp.pwd := '1';
ELSIF ( r.x.ctrl.annul or xc_trap ) = '0' THEN
xc_wreg := r.x.ctrl.wreg;
sp_write ( r , wpr , v.w.s , vwpr );
vir.pwd := '0';
ELSIF ( ( not r.x.ctrl.annul ) and xc_trap ) = '1' THEN
xc_exception := '1';
xc_result := r.x.ctrl.pc ( 31 downto 2 ) & "00";
xc_wreg := '1';
v.w.s.tt := xc_vectt;
v.w.s.ps := r.w.s.s;
v.w.s.s := '1';
v.x.annul_all := '1';
v.x.rstate := trap;
xc_waddr := ( OTHERS => '0' );
xc_waddr ( LOG2 ( 8 ) + 3 downto 0 ) := r.w.s.cwp & "0001";
v.x.npc := npc_find ( r );
fpexack ( r , xc_fpexack );
IF r.w.s.et = '0' THEN
xc_wreg := '0';
END IF;
END IF;
WHEN trap =>
xc_result := npc_gen ( r );
xc_wreg := '1';
xc_waddr := ( OTHERS => '0' );
xc_waddr ( LOG2 ( 8 ) + 3 downto 0 ) := r.w.s.cwp & "0010";
IF ( r.w.s.et = '1' ) THEN
v.w.s.et := '0';
v.x.rstate := run;
v.w.s.cwp := r.w.s.cwp - 1;
ELSE
v.x.rstate := dsu1;
xc_wreg := '0';
vp.error := '1';
END IF;
WHEN dsu1 =>
xc_exception := '1';
v.x.annul_all := '1';
xc_trap_address ( 31 downto 2 ) := r.f.pc;
xc_trap_address ( 31 downto 2 ) := ir.addr;
vir.addr := npc_gen ( r ) ( 31 downto 2 );
v.x.rstate := dsu2;
v.x.debug := r.x.debug;
WHEN dsu2 =>
xc_exception := '1';
v.x.annul_all := '1';
xc_trap_address ( 31 downto 2 ) := r.f.pc;
sidle := ( rp.pwd or rp.error ) and ico.idle and dco.idle and not r.x.debug;
IF dbgi.reset = '1' THEN
vp.pwd := '0';
vp.error := '0';
END IF;
IF ( dbgi.dsuen and dbgi.dbreak ) = '1' THEN
v.x.debug := '1';
END IF;
diagwr ( r , dsur , ir , dbgi , wpr , v.w.s , vwpr , vdsu.asi , xc_trap_address , vir.addr , vdsu.tbufcnt , xc_wreg , xc_waddr , xc_result , fpcdbgwr );
xc_halt := dbgi.halt;
IF r.x.ipend = '1' THEN
vp.pwd := '0';
END IF;
IF ( rp.error or rp.pwd or r.x.debug or xc_halt ) = '0' THEN
v.x.rstate := run;
v.x.annul_all := '0';
vp.error := '0';
xc_trap_address ( 31 downto 2 ) := ir.addr;
v.x.debug := '0';
vir.pwd := '1';
END IF;
WHEN OTHERS =>
NULL;
END CASE;
irq_intack ( r , holdn , v.x.intack );
itrace ( r , dsur , vdsu , xc_result , xc_exception , dbgi , rp.error , xc_trap , tbufcntx , tbufi );
vdsu.tbufcnt := tbufcntx;
v.w.except := xc_exception;
v.w.result := xc_result;
IF ( r.x.rstate = dsu2 ) THEN
v.w.except := '0';
END IF;
v.w.wa := xc_waddr ( LOG2 ( 8 + 1 ) + 4 - 1 downto 0 );
v.w.wreg := xc_wreg and holdn;
rfi.wdata <= xc_result;
rfi.waddr <= xc_waddr;
rfi.wren <= ( xc_wreg and holdn ) and not dco.scanen;
irqo.intack <= r.x.intack and holdn;
irqo.irl <= r.w.s.tt ( 3 downto 0 );
irqo.pwd <= rp.pwd;
dbgo.halt <= xc_halt;
dbgo.pwd <= rp.pwd;
dbgo.idle <= sidle;
dbgo.icnt <= icnt;
dci.intack <= r.x.intack and holdn;
IF ( xc_rstn = '0' ) THEN
v.w.except := '0';
v.w.s.et := '0';
v.w.s.svt := '0';
v.w.s.dwt := '0';
v.x.annul_all := '1';
v.x.rstate := run;
vir.pwd := '0';
vp.pwd := '0';
v.x.debug := '0';
v.x.nerror := '0';
v.w.s.tt := ( OTHERS => '0' );
IF ( dbgi.dsuen and dbgi.dbreak ) = '1' THEN
v.x.rstate := dsu1;
v.x.debug := '1';
END IF;
END IF;
v.w.s.ef := '0';
v.x.ctrl := r.m.ctrl;
v.x.dci := r.m.dci;
v.x.ctrl.rett := r.m.ctrl.rett and not r.m.ctrl.annul;
v.x.mac := r.m.mac;
v.x.laddr := r.m.result ( 1 downto 0 );
v.x.ctrl.annul := r.m.ctrl.annul or v.x.annul_all;
mul_res ( r , v.w.s.asr18 , v.x.result , v.x.y , me_asr18 , me_icc );
mem_trap ( r , wpr , v.x.ctrl.annul , holdn , v.x.ctrl.trap , me_iflush , me_nullify , v.m.werr , v.x.ctrl.tt );
me_newtt := v.x.ctrl.tt;
irq_trap ( r , ir , irqi.irl , v.x.ctrl.annul , v.x.ctrl.pv , v.x.ctrl.trap , me_newtt , me_nullify , v.m.irqen , v.m.irqen2 , me_nullify2 , v.x.ctrl.trap , v.x.ipend , v.x.ctrl.tt );
IF ( r.m.ctrl.ld or not dco.mds ) = '1' THEN
v.x.data ( 0 ) := dco.data ( 0 );
v.x.data ( 1 ) := dco.data ( 1 );
v.x.set := dco.set ( LOG2X ( 2 ) - 1 downto 0 );
IF dco.mds = '0' THEN
me_size := r.x.dci.size;
me_laddr := r.x.laddr;
me_signed := r.x.dci.signed;
ELSE
me_size := v.x.dci.size;
me_laddr := v.x.laddr;
me_signed := v.x.dci.signed;
END IF;
v.x.data ( 0 ) := ld_align ( v.x.data , v.x.set , me_size , me_laddr , me_signed );
END IF;
v.x.mexc := dco.mexc;
v.x.impwp := '0';
v.x.icc := me_icc;
v.x.ctrl.wicc := r.m.ctrl.wicc and not v.x.annul_all;
IF ( r.x.rstate = dsu2 ) THEN
me_nullify2 := '0';
v.x.set := dco.set ( LOG2X ( 2 ) - 1 downto 0 );
END IF;
dci.maddress <= r.m.result;
dci.enaddr <= r.m.dci.enaddr;
dci.asi <= r.m.dci.asi;
dci.size <= r.m.dci.size;
dci.nullify <= me_nullify2;
dci.lock <= r.m.dci.lock and not r.m.ctrl.annul;
dci.read <= r.m.dci.read;
dci.write <= r.m.dci.write;
dci.flush <= me_iflush;
dci.dsuen <= r.m.dci.dsuen;
dci.msu <= r.m.su;
dci.esu <= r.e.su;
dbgo.ipend <= v.x.ipend;
v.m.ctrl := r.e.ctrl;
ex_op1 := r.e.op1;
ex_op2 := r.e.op2;
v.m.ctrl.rett := r.e.ctrl.rett and not r.e.ctrl.annul;
v.m.ctrl.wreg := r.e.ctrl.wreg and not v.x.annul_all;
ex_ymsb := r.e.ymsb;
mul_op2 := ex_op2;
ex_shcnt := r.e.shcnt;
v.e.cwp := r.a.cwp;
ex_sari := r.e.sari;
v.m.su := r.e.su;
v.m.mul := '0';
IF r.e.ldbp1 = '1' THEN
ex_op1 := r.x.data ( 0 );
ex_sari := r.x.data ( 0 ) ( 31 ) and r.e.ctrl.inst ( 19 ) and r.e.ctrl.inst ( 20 );
END IF;
IF r.e.ldbp2 = '1' THEN
ex_op2 := r.x.data ( 0 );
ex_ymsb := r.x.data ( 0 ) ( 0 );
mul_op2 := ex_op2;
ex_shcnt := r.x.data ( 0 ) ( 4 downto 0 );
IF r.e.invop2 = '1' THEN
ex_op2 := not ex_op2;
ex_shcnt := not ex_shcnt;
END IF;
END IF;
ex_add_res := ( ex_op1 & '1' ) + ( ex_op2 & r.e.alucin );
IF ex_add_res ( 2 downto 1 ) = "00" THEN
v.m.nalign := '0';
ELSE
v.m.nalign := '1';
END IF;
dcache_gen ( r , v , ex_dci , ex_link_pc , ex_jump , ex_force_a2 , ex_load );
ex_jump_address := ex_add_res ( 32 downto 2 + 1 );
logic_op ( r , ex_op1 , ex_op2 , v.x.y , ex_ymsb , ex_logic_res , v.m.y );
ex_shift_res := shift ( r , ex_op1 , ex_op2 , ex_shcnt , ex_sari );
misc_op ( r , wpr , ex_op1 , ex_op2 , xc_df_result , v.x.y , ex_misc_res , ex_edata );
ex_add_res ( 3 ) := ex_add_res ( 3 ) or ex_force_a2;
alu_select ( r , ex_add_res , ex_op1 , ex_op2 , ex_shift_res , ex_logic_res , ex_misc_res , ex_result , me_icc , v.m.icc , v.m.divz );
dbg_cache ( holdn , dbgi , r , dsur , ex_result , ex_dci , ex_result2 , v.m.dci );
fpstdata ( r , ex_edata , ex_result2 , fpo.data , ex_edata2 , v.m.result );
cwp_ex ( r , v.m.wcwp );
v.m.ctrl.annul := v.m.ctrl.annul or v.x.annul_all;
v.m.ctrl.wicc := r.e.ctrl.wicc and not v.x.annul_all;
v.m.mac := r.e.mac;
IF ( r.x.rstate = dsu2 ) THEN
v.m.ctrl.ld := '1';
END IF;
dci.eenaddr <= v.m.dci.enaddr;
dci.eaddress <= ex_add_res ( 32 downto 1 );
dci.edata <= ex_edata2;
v.e.ctrl := r.a.ctrl;
v.e.jmpl := r.a.jmpl;
v.e.ctrl.annul := r.a.ctrl.annul or v.x.annul_all;
v.e.ctrl.rett := r.a.ctrl.rett and not r.a.ctrl.annul;
v.e.ctrl.wreg := r.a.ctrl.wreg and not v.x.annul_all;
v.e.su := r.a.su;
v.e.et := r.a.et;
v.e.ctrl.wicc := r.a.ctrl.wicc and not v.x.annul_all;
exception_detect ( r , wpr , dbgi , r.a.ctrl.trap , r.a.ctrl.tt , v.e.ctrl.trap , v.e.ctrl.tt );
op_mux ( r , rfo.data1 , v.m.result , v.x.result , xc_df_result , zero32 , r.a.rsel1 , v.e.ldbp1 , ra_op1 );
op_mux ( r , rfo.data2 , v.m.result , v.x.result , xc_df_result , r.a.imm , r.a.rsel2 , ex_ldbp2 , ra_op2 );
alu_op ( r , ra_op1 , ra_op2 , v.m.icc , v.m.y ( 0 ) , ex_ldbp2 , v.e.op1 , v.e.op2 , v.e.aluop , v.e.alusel , v.e.aluadd , v.e.shcnt , v.e.sari , v.e.shleft , v.e.ymsb , v.e.mul , ra_div , v.e.mulstep , v.e.mac , v.e.ldbp2 , v.e.invop2 );
cin_gen ( r , v.m.icc ( 0 ) , v.e.alucin );
de_inst := r.d.inst ( conv_integer ( r.d.set ) );
de_icc := r.m.icc;
v.a.cwp := r.d.cwp;
su_et_select ( r , v.w.s.ps , v.w.s.s , v.w.s.et , v.a.su , v.a.et );
wicc_y_gen ( de_inst , v.a.ctrl.wicc , v.a.ctrl.wy );
cwp_ctrl ( r , v.w.s.wim , de_inst , de_cwp , v.a.wovf , v.a.wunf , de_wcwp );
rs1_gen ( r , de_inst , v.a.rs1 , de_rs1mod );
de_rs2 := de_inst ( 4 downto 0 );
de_raddr1 := ( OTHERS => '0' );
de_raddr2 := ( OTHERS => '0' );
IF de_rs1mod = '1' THEN
regaddr ( r.d.cwp , de_inst ( 29 downto 26 ) & v.a.rs1 ( 0 ) , de_raddr1 ( LOG2 ( 8 + 1 ) + 4 - 1 downto 0 ) );
ELSE
regaddr ( r.d.cwp , de_inst ( 18 downto 15 ) & v.a.rs1 ( 0 ) , de_raddr1 ( LOG2 ( 8 + 1 ) + 4 - 1 downto 0 ) );
END IF;
regaddr ( r.d.cwp , de_rs2 , de_raddr2 ( LOG2 ( 8 + 1 ) + 4 - 1 downto 0 ) );
v.a.rfa1 := de_raddr1 ( LOG2 ( 8 + 1 ) + 4 - 1 downto 0 );
v.a.rfa2 := de_raddr2 ( LOG2 ( 8 + 1 ) + 4 - 1 downto 0 );
rd_gen ( r , de_inst , v.a.ctrl.wreg , v.a.ctrl.ld , de_rd );
regaddr ( de_cwp , de_rd , v.a.ctrl.rd );
fpbranch ( de_inst , fpo.cc , de_fbranch );
fpbranch ( de_inst , cpo.cc , de_cbranch );
v.a.imm := imm_data ( r , de_inst );
lock_gen ( r , de_rs2 , de_rd , v.a.rfa1 , v.a.rfa2 , v.a.ctrl.rd , de_inst , fpo.ldlock , v.e.mul , ra_div , v.a.ldcheck1 , v.a.ldcheck2 , de_ldlock , v.a.ldchkra , v.a.ldchkex );
ic_ctrl ( r , de_inst , v.x.annul_all , de_ldlock , branch_true ( de_icc , de_inst ) , de_fbranch , de_cbranch , fpo.ccv , cpo.ccv , v.d.cnt , v.d.pc , de_branch , v.a.ctrl.annul , v.d.annul , v.a.jmpl , de_inull , v.d.pv , v.a.ctrl.pv , de_hold_pc , v.a.ticc , v.a.ctrl.rett , v.a.mulstart , v.a.divstart );
cwp_gen ( r , v , v.a.ctrl.annul , de_wcwp , de_cwp , v.d.cwp );
v.d.inull := ra_inull_gen ( r , v );
op_find ( r , v.a.ldchkra , v.a.ldchkex , v.a.rs1 , v.a.rfa1 , false , v.a.rfe1 , v.a.rsel1 , v.a.ldcheck1 );
op_find ( r , v.a.ldchkra , v.a.ldchkex , de_rs2 , v.a.rfa2 , imm_select ( de_inst ) , v.a.rfe2 , v.a.rsel2 , v.a.ldcheck2 );
de_branch_address := branch_address ( de_inst , r.d.pc );
v.a.ctrl.annul := v.a.ctrl.annul or v.x.annul_all;
v.a.ctrl.wicc := v.a.ctrl.wicc and not v.a.ctrl.annul;
v.a.ctrl.wreg := v.a.ctrl.wreg and not v.a.ctrl.annul;
v.a.ctrl.rett := v.a.ctrl.rett and not v.a.ctrl.annul;
v.a.ctrl.wy := v.a.ctrl.wy and not v.a.ctrl.annul;
v.a.ctrl.trap := r.d.mexc;
v.a.ctrl.tt := "000000";
v.a.ctrl.inst := de_inst;
v.a.ctrl.pc := r.d.pc;
v.a.ctrl.cnt := r.d.cnt;
v.a.step := r.d.step;
IF holdn = '0' THEN
de_raddr1 ( LOG2 ( 8 + 1 ) + 4 - 1 downto 0 ) := r.a.rfa1;
de_raddr2 ( LOG2 ( 8 + 1 ) + 4 - 1 downto 0 ) := r.a.rfa2;
de_ren1 := r.a.rfe1;
de_ren2 := r.a.rfe2;
ELSE
de_ren1 := v.a.rfe1;
de_ren2 := v.a.rfe2;
END IF;
IF ( ( dbgi.denable and not dbgi.dwrite ) = '1' ) and ( r.x.rstate = dsu2 ) THEN
de_raddr1 ( LOG2 ( 8 + 1 ) + 4 - 1 downto 0 ) := dbgi.daddr ( LOG2 ( 8 + 1 ) + 4 + 1 downto 2 );
de_ren1 := '1';
END IF;
v.d.step := dbgi.step and not r.d.annul;
rfi.raddr1 <= de_raddr1;
rfi.raddr2 <= de_raddr2;
rfi.ren1 <= de_ren1 and not dco.scanen;
rfi.ren2 <= de_ren2 and not dco.scanen;
rfi.diag <= dco.testen & "000";
ici.inull <= de_inull;
ici.flush <= me_iflush;
IF ( xc_rstn = '0' ) THEN
v.d.cnt := ( OTHERS => '0' );
END IF;
npc := r.f.pc;
IF ( xc_rstn = '0' ) THEN
v.f.pc := ( OTHERS => '0' );
v.f.branch := '0';
v.f.pc ( 31 downto 12 ) := conv_std_logic_vector ( 16#00000# , 20 );
ELSIF xc_exception = '1' THEN
v.f.branch := '1';
v.f.pc := xc_trap_address;
npc := v.f.pc;
ELSIF de_hold_pc = '1' THEN
v.f.pc := r.f.pc;
v.f.branch := r.f.branch;
IF ex_jump = '1' THEN
v.f.pc := ex_jump_address;
v.f.branch := '1';
npc := v.f.pc;
END IF;
ELSIF ex_jump = '1' THEN
v.f.pc := ex_jump_address;
v.f.branch := '1';
npc := v.f.pc;
ELSIF de_branch = '1' THEN
v.f.pc := branch_address ( de_inst , r.d.pc );
v.f.branch := '1';
npc := v.f.pc;
ELSE
v.f.branch := '0';
v.f.pc ( 31 downto 2 ) := r.f.pc ( 31 downto 2 ) + 1;
npc := v.f.pc;
END IF;
ici.dpc <= r.d.pc ( 31 downto 2 ) & "00";
ici.fpc <= r.f.pc ( 31 downto 2 ) & "00";
ici.rpc <= npc ( 31 downto 2 ) & "00";
ici.fbranch <= r.f.branch;
ici.rbranch <= v.f.branch;
ici.su <= v.a.su;
ici.fline <= ( OTHERS => '0' );
ici.flushl <= '0';
IF ( ico.mds and de_hold_pc ) = '0' THEN
v.d.inst ( 0 ) := ico.data ( 0 );
v.d.inst ( 1 ) := ico.data ( 1 );
v.d.set := ico.set ( LOG2X ( 2 ) - 1 downto 0 );
v.d.mexc := ico.mexc;
END IF;
diagread ( dbgi , r , dsur , ir , wpr , rfo.data1 , dco , tbo , diagdata );
diagrdy ( dbgi.denable , dsur , r.m.dci , dco.mds , ico , vdsu.crdy );
rin <= v;
wprin <= vwpr;
dsuin <= vdsu;
irin <= vir;
muli.start <= r.a.mulstart and not r.a.ctrl.annul;
muli.signed <= r.e.ctrl.inst ( 19 );
muli.op1 <= ( ex_op1 ( 31 ) and r.e.ctrl.inst ( 19 ) ) & ex_op1;
muli.op2 <= ( mul_op2 ( 31 ) and r.e.ctrl.inst ( 19 ) ) & mul_op2;
muli.mac <= r.e.ctrl.inst ( 24 );
muli.acc ( 39 downto 32 ) <= r.x.y ( 7 downto 0 );
muli.acc ( 31 downto 0 ) <= r.w.s.asr18;
muli.flush <= r.x.annul_all;
divi.start <= r.a.divstart and not r.a.ctrl.annul;
divi.signed <= r.e.ctrl.inst ( 19 );
divi.flush <= r.x.annul_all;
divi.op1 <= ( ex_op1 ( 31 ) and r.e.ctrl.inst ( 19 ) ) & ex_op1;
divi.op2 <= ( ex_op2 ( 31 ) and r.e.ctrl.inst ( 19 ) ) & ex_op2;
IF ( r.a.divstart and not r.a.ctrl.annul ) = '1' THEN
dsign := r.a.ctrl.inst ( 19 );
ELSE
dsign := r.e.ctrl.inst ( 19 );
END IF;
divi.y <= ( r.m.y ( 31 ) and dsign ) & r.m.y;
rpin <= vp;
dbgo.dsu <= '1';
dbgo.dsumode <= r.x.debug;
dbgo.crdy <= dsur.crdy ( 2 );
dbgo.data <= diagdata;
tbi <= tbufi;
dbgo.error <= dummy and not r.x.nerror;
END PROCESS;
preg : PROCESS ( sclk )
BEGIN
IF rising_edge ( sclk ) THEN
rp <= rpin;
IF rstn = '0' THEN
rp.error <= '0';
END IF;
END IF;
END PROCESS;
reg : PROCESS ( clk )
BEGIN
IF rising_edge ( clk ) THEN
IF ( holdn = '1' ) THEN
r <= rin;
ELSE
r.x.ipend <= rin.x.ipend;
r.m.werr <= rin.m.werr;
IF ( holdn or ico.mds ) = '0' THEN
r.d.inst <= rin.d.inst;
r.d.mexc <= rin.d.mexc;
r.d.set <= rin.d.set;
END IF;
IF ( holdn or dco.mds ) = '0' THEN
r.x.data <= rin.x.data;
r.x.mexc <= rin.x.mexc;
r.x.impwp <= rin.x.impwp;
r.x.set <= rin.x.set;
END IF;
END IF;
IF rstn = '0' THEN
r.x.error <= '0';
r.w.s.s <= '1';
END IF;
END IF;
END PROCESS;
dsureg : PROCESS ( clk )
BEGIN
IF rising_edge ( clk ) THEN
IF holdn = '1' THEN
dsur <= dsuin;
ELSE
dsur.crdy <= dsuin.crdy;
END IF;
END IF;
END PROCESS;
dsureg2 : PROCESS ( clk )
BEGIN
IF rising_edge ( clk ) THEN
IF holdn = '1' THEN
ir <= irin;
END IF;
END IF;
END PROCESS;
wpreg0 : PROCESS ( clk )
BEGIN
IF rising_edge ( clk ) THEN
IF holdn = '1' THEN
wpr ( 0 ) <= wprin ( 0 );
END IF;
IF rstn = '0' THEN
wpr ( 0 ).exec <= '0';
wpr ( 0 ).load <= '0';
wpr ( 0 ).store <= '0';
END IF;
END IF;
END PROCESS;
wpreg1 : PROCESS ( clk )
BEGIN
IF rising_edge ( clk ) THEN
IF holdn = '1' THEN
wpr ( 1 ) <= wprin ( 1 );
END IF;
IF rstn = '0' THEN
wpr ( 1 ).exec <= '0';
wpr ( 1 ).load <= '0';
wpr ( 1 ).store <= '0';
END IF;
END IF;
END PROCESS;
wpr ( 2 ) <= ( ZERO32 ( 31 DOWNTO 2 ) , ZERO32 ( 31 DOWNTO 2 ) , '0' , '0' , '0' , '0' );
wpr ( 3 ) <= ( ZERO32 ( 31 DOWNTO 2 ) , ZERO32 ( 31 DOWNTO 2 ) , '0' , '0' , '0' , '0' );
dummy <= '1';
END ARCHITECTURE;
| mit | 6e13c165304e4abfca24fab8e9075b07 | 0.385093 | 4.068001 | false | false | false | false |
michaelfivez/ascon_hardware_implementation | ascon128128_unrolled4/Kernel/FullDiffLayer.vhd | 1 | 2,106 | -------------------------------------------------------------------------------
--! @project Unrolled (factor 4) hardware implementation of Asconv128128
--! @author Michael Fivez
--! @license This project is released under the GNU Public License.
--! The license and distribution terms for this file may be
--! found in the file LICENSE in this distribution or at
--! http://www.gnu.org/licenses/gpl-3.0.txt
--! @note This is an hardware implementation made for my graduation thesis
--! at the KULeuven, in the COSIC department (year 2015-2016)
--! The thesis is titled 'Energy efficient hardware implementations of CAESAR submissions',
--! and can be found on the COSIC website (www.esat.kuleuven.be/cosic/publications)
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity FullDiffusionLayer is
port(
X0In : in std_logic_vector(63 downto 0);
X1In : in std_logic_vector(63 downto 0);
X2In : in std_logic_vector(63 downto 0);
X3In : in std_logic_vector(63 downto 0);
X4In : in std_logic_vector(63 downto 0);
X0Out : out std_logic_vector(63 downto 0);
X1Out : out std_logic_vector(63 downto 0);
X2Out : out std_logic_vector(63 downto 0);
X3Out : out std_logic_vector(63 downto 0);
X4Out : out std_logic_vector(63 downto 0));
end entity FullDiffusionLayer;
architecture structural of FullDiffusionLayer is
begin
Diff0: entity work.DiffusionLayer
generic map(SHIFT1 => 19,SHIFT2 => 28)
port map(X0In,X0Out);
Diff1: entity work.DiffusionLayer
generic map(SHIFT1 => 61,SHIFT2 => 39)
port map(X1In,X1Out);
Diff2: entity work.DiffusionLayer
generic map(SHIFT1 => 1,SHIFT2 => 6)
port map(X2In,X2Out);
Diff3: entity work.DiffusionLayer
generic map(SHIFT1 => 10,SHIFT2 => 17)
port map(X3In,X3Out);
Diff4: entity work.DiffusionLayer
generic map(SHIFT1 => 7,SHIFT2 => 41)
port map(X4In,X4Out);
end architecture structural;
| gpl-3.0 | c3d442c1e3e70b6ed5d05324db4e138c | 0.62868 | 3.337559 | false | false | false | false |
michaelfivez/ascon_hardware_implementation | ascon12864_unrolled6/API_plus_CipherCore/AEAD_Core.vhd | 5 | 15,538 | -------------------------------------------------------------------------------
--! @file AEAD_Core.vhd
--! @brief Authenticated encryption unit core template module.
--! User should modification to the default generics based on the
--! implemented cipher.
--! @project CAESAR Candidate Evaluation
--! @author Ekawat (ice) Homsirikamol
--! @copyright Copyright (c) 2015 Cryptographic Engineering Research Group
--! ECE Department, George Mason University Fairfax, VA, U.S.A.
--! All rights Reserved.
--! @license This project is released under the GNU Public License.
--! The license and distribution terms for this file may be
--! found in the file LICENSE in this distribution or at
--! http://www.gnu.org/licenses/gpl-3.0.txt
--! @note This is publicly available encryption source code that falls
--! under the License Exception TSU (Technology and software-
--! —unrestricted)
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity AEAD_Core is
generic (
G_W : integer := 32; --! Public data width (bits)
G_SW : integer := 32; --! Secret data width (bits)
G_NPUB_SIZE : integer := 128; --! IV or Nonce size (bits)
G_NSEC_ENABLE : integer := 0; --! Enable NSEC port
G_NSEC_SIZE : integer := 1; --! NSEC width (bits)
G_ABLK_SIZE : integer := 64; --! Authenticated Data Block size (bits)
G_DBLK_SIZE : integer := 64; --! Data Block size (bits)
G_KEY_SIZE : integer := 128; --! Key size (bits)
G_RDKEY_ENABLE : integer := 0; --! Enable rdkey port (also disables key port)
G_RDKEY_SIZE : integer := 1; --! Roundkey size (bits)
G_TAG_SIZE : integer := 128; --! Tag size (bits)
G_BS_BYTES : integer := 3; --! The number of bits required to hold block size expressed in bytes = log2_ceil(max(G_ABLK_SIZE,G_DBLK_SIZE)/8)
G_LOADLEN_ENABLE : integer := 0; --! Enable load length section
G_PAD : integer := 1; --! Enable padding
G_PAD_STYLE : integer := 1; --! Padding mode
G_PAD_AD : integer := 1; --! (G_PAD's sub option) Enable AD Padding
G_PAD_D : integer := 1; --! (G_PAD's sub option) Enable Data padding
G_CTR_AD_SIZE : integer := 64; --! Maximum AD len value
G_CTR_D_SIZE : integer := 64; --! Maximum data len value
G_PLAINTEXT_MODE : integer := 0; --! Plaintext Mode
G_CIPHERTEXT_MODE : integer := 0; --! Ciphertext mode
G_REVERSE_DBLK : integer := 0 --! Reverse block order (for message only)
);
port (
--! Global signals
clk : in std_logic;
rst : in std_logic;
--! Data in signals
pdi : in std_logic_vector(G_W -1 downto 0);
pdi_valid : in std_logic;
pdi_ready : out std_logic;
--! Key signals
sdi : in std_logic_vector(G_SW -1 downto 0);
sdi_valid : in std_logic;
sdi_ready : out std_logic;
--! Data out signals
do : out std_logic_vector(G_W -1 downto 0);
do_ready : in std_logic;
do_valid : out std_logic;
--! FIFO signals
bypass_fifo_wr : out std_logic;
bypass_fifo_rd : out std_logic;
bypass_fifo_full : in std_logic;
bypass_fifo_empty : in std_logic;
bypass_fifo_data : in std_logic_vector(G_W -1 downto 0);
aux_fifo_din : out std_logic_vector(G_W -1 downto 0);
aux_fifo_ctrl : out std_logic_vector(4 -1 downto 0);
aux_fifo_dout : in std_logic_vector(G_W -1 downto 0);
aux_fifo_status : in std_logic_vector(3 -1 downto 0)
);
end AEAD_Core;
-------------------------------------------------------------------------------
--! @brief Architecture definition of AEAD_Core
-------------------------------------------------------------------------------
architecture structure of AEAD_Core is
--! Signals from input processor
signal npub : std_logic_vector(G_NPUB_SIZE -1 downto 0);
signal nsec : std_logic_vector(G_NSEC_SIZE -1 downto 0);
signal key : std_logic_vector(G_KEY_SIZE -1 downto 0);
signal rdkey : std_logic_vector(G_RDKEY_SIZE -1 downto 0);
signal bdi : std_logic_vector(G_DBLK_SIZE -1 downto 0);
signal exp_tag : std_logic_vector(G_TAG_SIZE -1 downto 0);
signal len_a : std_logic_vector(G_CTR_AD_SIZE -1 downto 0);
signal len_d : std_logic_vector(G_CTR_D_SIZE -1 downto 0);
signal key_ready : std_logic;
signal key_updated : std_logic;
signal key_needs_update : std_logic;
signal rdkey_ready : std_logic;
signal rdkey_read : std_logic;
signal npub_ready : std_logic;
signal npub_read : std_logic;
signal nsec_ready : std_logic;
signal nsec_read : std_logic;
signal bdi_ready : std_logic;
signal bdi_proc : std_logic;
signal bdi_ad : std_logic;
signal bdi_nsec : std_logic;
signal bdi_pad : std_logic;
signal bdi_decrypt : std_logic;
signal bdi_eot : std_logic;
signal bdi_eoi : std_logic;
signal bdi_read : std_logic;
signal bdi_size : std_logic_vector(G_BS_BYTES -1 downto 0);
signal bdi_valid_bytes : std_logic_vector(G_DBLK_SIZE/8 -1 downto 0);
signal bdi_pad_loc : std_logic_vector(G_DBLK_SIZE/8 -1 downto 0);
signal bdi_nodata : std_logic;
signal exp_tag_ready : std_logic;
--! Signals to output processor
signal bdo_ready : std_logic;
signal bdo_write : std_logic;
signal bdo : std_logic_vector(G_DBLK_SIZE -1 downto 0);
signal bdo_size : std_logic_vector(G_BS_BYTES+1 -1 downto 0);
signal bdo_nsec : std_logic;
signal tag_ready : std_logic;
signal tag_write : std_logic;
signal tag : std_logic_vector(G_TAG_SIZE -1 downto 0);
signal msg_auth_done : std_logic;
signal msg_auth_valid : std_logic;
begin
u_input:
entity work.PreProcessor(structure)
generic map (
G_W => G_W ,
G_SW => G_SW ,
G_NPUB_SIZE => G_NPUB_SIZE ,
G_NSEC_ENABLE => G_NSEC_ENABLE ,
G_NSEC_SIZE => G_NSEC_SIZE ,
G_ABLK_SIZE => G_ABLK_SIZE ,
G_DBLK_SIZE => G_DBLK_SIZE ,
G_KEY_SIZE => G_KEY_SIZE ,
G_RDKEY_ENABLE => G_RDKEY_ENABLE ,
G_RDKEY_SIZE => G_RDKEY_SIZE ,
G_TAG_SIZE => G_TAG_SIZE ,
G_BS_BYTES => G_BS_BYTES ,
G_LOADLEN_ENABLE => G_LOADLEN_ENABLE ,
G_PAD => G_PAD ,
G_PAD_STYLE => G_PAD_STYLE ,
G_PAD_AD => G_PAD_AD ,
G_PAD_D => G_PAD_D ,
G_CTR_AD_SIZE => G_CTR_AD_SIZE ,
G_CTR_D_SIZE => G_CTR_D_SIZE ,
G_PLAINTEXT_MODE => G_PLAINTEXT_MODE ,
G_CIPHERTEXT_MODE => G_CIPHERTEXT_MODE,
G_REVERSE_DBLK => G_REVERSE_DBLK
)
port map (
clk => clk ,
rst => rst ,
--! External
pdi => pdi ,
pdi_valid => pdi_valid ,
pdi_ready => pdi_ready ,
sdi => sdi ,
sdi_valid => sdi_valid ,
sdi_ready => sdi_ready ,
--! Datapath
npub => npub ,
nsec => nsec ,
key => key ,
rdkey => rdkey ,
bdi => bdi ,
exp_tag => exp_tag ,
len_a => len_a ,
len_d => len_d ,
--! Controller
key_ready => key_ready ,
key_updated => key_updated ,
key_needs_update => key_needs_update ,
rdkey_ready => rdkey_ready ,
rdkey_read => rdkey_read ,
npub_ready => npub_ready ,
npub_read => npub_read ,
nsec_ready => nsec_ready ,
nsec_read => nsec_read ,
bdi_ready => bdi_ready ,
bdi_proc => bdi_proc ,
bdi_ad => bdi_ad ,
bdi_nsec => bdi_nsec ,
bdi_pad => bdi_pad ,
bdi_decrypt => bdi_decrypt ,
bdi_eot => bdi_eot ,
bdi_eoi => bdi_eoi ,
bdi_nodata => bdi_nodata ,
bdi_read => bdi_read ,
bdi_size => bdi_size ,
bdi_valid_bytes => bdi_valid_bytes ,
bdi_pad_loc => bdi_pad_loc ,
exp_tag_ready => exp_tag_ready ,
msg_auth_done => msg_auth_done ,
--! FIFO
bypass_fifo_wr => bypass_fifo_wr ,
bypass_fifo_full => bypass_fifo_full
);
u_cc:
entity work.CipherCore(structure)
generic map (
G_NPUB_SIZE => G_NPUB_SIZE ,
G_NSEC_SIZE => G_NSEC_SIZE ,
G_DBLK_SIZE => G_DBLK_SIZE ,
G_KEY_SIZE => G_KEY_SIZE ,
G_RDKEY_SIZE => G_RDKEY_SIZE ,
G_TAG_SIZE => G_TAG_SIZE ,
G_BS_BYTES => G_BS_BYTES ,
G_CTR_AD_SIZE => G_CTR_AD_SIZE ,
G_CTR_D_SIZE => G_CTR_D_SIZE
)
port map (
clk => clk ,
rst => rst ,
npub => npub ,
nsec => nsec ,
key => key ,
rdkey => rdkey ,
bdi => bdi ,
exp_tag => exp_tag ,
len_a => len_a ,
len_d => len_d ,
key_ready => key_ready ,
key_updated => key_updated ,
key_needs_update => key_needs_update ,
rdkey_ready => rdkey_ready ,
rdkey_read => rdkey_read ,
npub_ready => npub_ready ,
npub_read => npub_read ,
nsec_ready => nsec_ready ,
nsec_read => nsec_read ,
bdi_ready => bdi_ready ,
bdi_proc => bdi_proc ,
bdi_ad => bdi_ad ,
bdi_nsec => bdi_nsec ,
bdi_pad => bdi_pad ,
bdi_decrypt => bdi_decrypt ,
bdi_eot => bdi_eot ,
bdi_eoi => bdi_eoi ,
bdi_read => bdi_read ,
bdi_size => bdi_size ,
bdi_valid_bytes => bdi_valid_bytes ,
bdi_pad_loc => bdi_pad_loc ,
bdi_nodata => bdi_nodata ,
exp_tag_ready => exp_tag_ready ,
msg_auth_done => msg_auth_done ,
bdo_write => bdo_write ,
bdo_ready => bdo_ready ,
bdo => bdo ,
bdo_size => bdo_size ,
bdo_nsec => bdo_nsec ,
tag_write => tag_write ,
tag_ready => tag_ready ,
tag => tag ,
msg_auth_valid => msg_auth_valid
);
u_output:
entity work.PostProcessor(structure)
generic map (
G_W => G_W ,
G_DBLK_SIZE => G_DBLK_SIZE ,
G_BS_BYTES => G_BS_BYTES ,
G_TAG_SIZE => G_TAG_SIZE ,
G_NSEC_ENABLE => G_NSEC_ENABLE ,
G_LOADLEN_ENABLE => G_LOADLEN_ENABLE ,
G_CIPHERTEXT_MODE => G_CIPHERTEXT_MODE,
G_REVERSE_DBLK => G_REVERSE_DBLK ,
G_PAD => G_PAD ,
G_PAD_D => G_PAD_D
)
port map (
--! Global
clk => clk ,
rst => rst ,
--! External
do => do ,
do_ready => do_ready ,
do_valid => do_valid ,
--! Processor
bdo_ready => bdo_ready ,
bdo_write => bdo_write ,
bdo_data => bdo ,
bdo_size => bdo_size ,
bdo_nsec => bdo_nsec ,
tag_ready => tag_ready ,
tag_write => tag_write ,
tag_data => tag ,
msg_auth_done => msg_auth_done ,
msg_auth_valid => msg_auth_valid ,
--! FIFOs
bypass_fifo_empty => bypass_fifo_empty,
bypass_fifo_rd => bypass_fifo_rd ,
bypass_fifo_data => bypass_fifo_data ,
aux_fifo_din => aux_fifo_din ,
aux_fifo_ctrl => aux_fifo_ctrl ,
aux_fifo_dout => aux_fifo_dout ,
aux_fifo_status => aux_fifo_status
);
end structure; | gpl-3.0 | da76d2ebb9e4890b75c55912f6aa3c7b | 0.386586 | 4.193252 | false | false | false | false |
cafe-alpha/wascafe | v13/r07c_de10_20201014_abus4/wasca/synthesis/submodules/Altera_UP_SD_Card_48_bit_Command_Generator.vhd | 7 | 25,262 | -- (C) 2001-2015 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
-------------------------------------------------------------------------------------
-- This module takes a command ID and data, and generates a 48-bit message for it.
-- It will first check if the command is a valid 48-bit command and produce the
-- following outputs:
-- 1. o_dataout -> a single bit output that produces the message to be sent to the
-- SD card one bit at a time. Every time the i_message_bit_out input
-- is high and the i_clock has a positive edge, a new bit is produced.
-- 2. o_message_done -> a signal that is asserted high when the entire message has been
-- produced through the o_dataout output.
-- 3. o_valid -> is a signal that is asserted high if the specified message is valid.
-- 4. o_response_type -> indicates the command response type.
-- 5. o_returning_ocr -> the response from the SD card will contain the OCR register
-- 6. o_returning_cid -> the response from the SD card will contain the CID register
-- 7. o_returning_rca -> the response from the SD card will contain the RCA register
-- 8. o_returning_csd -> the response from the SD card will contain the CSD register
-- 9. o_data_read -> asserted when the command being sent is a data read command.
-- 10. o_data_write -> asserted when the command being sent is a data write command.
-- 11. o_wait_cmd_busy -> is set high when the response to this command will be
-- followed by a busy signal.
--
-- NOTES/REVISIONS:
-------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity Altera_UP_SD_Card_48_bit_Command_Generator is
generic (
-- Basic commands
COMMAND_0_GO_IDLE : STD_LOGIC_VECTOR(5 downto 0) := "000000";
COMMAND_2_ALL_SEND_CID : STD_LOGIC_VECTOR(5 downto 0) := "000010";
COMMAND_3_SEND_RCA : STD_LOGIC_VECTOR(5 downto 0) := "000011";
COMMAND_4_SET_DSR : STD_LOGIC_VECTOR(5 downto 0) := "000100";
COMMAND_6_SWITCH_FUNCTION : STD_LOGIC_VECTOR(5 downto 0) := "000110";
COMMAND_7_SELECT_CARD : STD_LOGIC_VECTOR(5 downto 0) := "000111";
COMMAND_9_SEND_CSD : STD_LOGIC_VECTOR(5 downto 0) := "001001";
COMMAND_10_SEND_CID : STD_LOGIC_VECTOR(5 downto 0) := "001010";
COMMAND_12_STOP_TRANSMISSION : STD_LOGIC_VECTOR(5 downto 0) := "001100";
COMMAND_13_SEND_STATUS : STD_LOGIC_VECTOR(5 downto 0) := "001101";
COMMAND_15_GO_INACTIVE : STD_LOGIC_VECTOR(5 downto 0) := "001111";
-- Block oriented read/write/lock commands
COMMAND_16_SET_BLOCK_LENGTH : STD_LOGIC_VECTOR(5 downto 0) := "010000";
-- Block oriented read commands
COMMAND_17_READ_BLOCK : STD_LOGIC_VECTOR(5 downto 0) := "010001";
COMMAND_18_READ_MULTIPLE_BLOCKS : STD_LOGIC_VECTOR(5 downto 0) := "010010";
-- Block oriented write commands
COMMAND_24_WRITE_BLOCK : STD_LOGIC_VECTOR(5 downto 0) := "011000";
COMMAND_25_WRITE_MULTIPLE_BLOCKS : STD_LOGIC_VECTOR(5 downto 0) := "011001";
COMMAND_27_PROGRAM_CSD : STD_LOGIC_VECTOR(5 downto 0) := "011011";
-- Block oriented write-protection commands
COMMAND_28_SET_WRITE_PROTECT : STD_LOGIC_VECTOR(5 downto 0) := "011100";
COMMAND_29_CLEAR_WRITE_PROTECT : STD_LOGIC_VECTOR(5 downto 0) := "011101";
COMMAND_30_SEND_PROTECTED_GROUPS : STD_LOGIC_VECTOR(5 downto 0) := "011110";
-- Erase commands
COMMAND_32_ERASE_BLOCK_START : STD_LOGIC_VECTOR(5 downto 0) := "100000";
COMMAND_33_ERASE_BLOCK_END : STD_LOGIC_VECTOR(5 downto 0) := "100001";
COMMAND_38_ERASE_SELECTED_GROUPS: STD_LOGIC_VECTOR(5 downto 0) := "100110";
-- Block lock commands
COMMAND_42_LOCK_UNLOCK : STD_LOGIC_VECTOR(5 downto 0) := "101010";
-- Command Type Settings
COMMAND_55_APP_CMD : STD_LOGIC_VECTOR(5 downto 0) := "110111";
COMMAND_56_GEN_CMD : STD_LOGIC_VECTOR(5 downto 0) := "111000";
-- Application Specific commands - must be preceeded with command 55.
ACOMMAND_6_SET_BUS_WIDTH : STD_LOGIC_VECTOR(5 downto 0) := "000110";
ACOMMAND_13_SD_STATUS : STD_LOGIC_VECTOR(5 downto 0) := "001101";
ACOMMAND_22_SEND_NUM_WR_BLOCKS : STD_LOGIC_VECTOR(5 downto 0) := "010100";
ACOMMAND_23_SET_BLK_ERASE_COUNT : STD_LOGIC_VECTOR(5 downto 0) := "010101";
ACOMMAND_41_SEND_OP_CONDITION : STD_LOGIC_VECTOR(5 downto 0) := "101001";
ACOMMAND_42_SET_CLR_CARD_DETECT : STD_LOGIC_VECTOR(5 downto 0) := "101010";
ACOMMAND_51_SEND_SCR : STD_LOGIC_VECTOR(5 downto 0) := "110011";
-- First custom_command
FIRST_NON_PREDEFINED_COMMAND : STD_LOGIC_VECTOR(3 downto 0) := "1010"
);
port
(
i_clock : in std_logic;
i_reset_n : in std_logic;
i_message_bit_out : in std_logic;
i_command_ID : in std_logic_vector(5 downto 0);
i_argument : in std_logic_vector(31 downto 0);
i_predefined_message : in std_logic_vector(3 downto 0);
i_generate : in std_logic;
i_DSR : in std_logic_vector(15 downto 0);
i_OCR : in std_logic_vector(31 downto 0);
i_RCA : in std_logic_vector(15 downto 0);
o_dataout : out std_logic;
o_message_done : out std_logic;
o_valid : out std_logic;
o_returning_ocr : out std_logic;
o_returning_cid : out std_logic;
o_returning_rca : out std_logic;
o_returning_csd : out std_logic;
o_returning_status : out std_logic;
o_data_read : out std_logic;
o_data_write : out std_logic;
o_wait_cmd_busy : out std_logic;
o_last_cmd_was_55 : out std_logic;
o_response_type : out std_logic_vector(2 downto 0)
);
end entity;
architecture rtl of Altera_UP_SD_Card_48_bit_Command_Generator is
component Altera_UP_SD_CRC7_Generator
port
(
i_clock : in std_logic;
i_enable : in std_logic;
i_reset_n : in std_logic;
i_shift : in std_logic;
i_datain : in std_logic;
o_dataout : out std_logic;
o_crcout : out std_logic_vector(6 downto 0)
);
end component;
-- Local wires
-- REGISTERED
signal counter : std_logic_vector(6 downto 0);
signal last_command_id : std_logic_vector(5 downto 0);
signal message_bits : std_logic_vector(39 downto 0);
signal last_command_sent_was_CMD55, valid : std_logic;
signal bit_to_send, sending_CRC, command_valid : std_logic;
signal returning_cid_reg, returning_rca_reg, returning_csd_reg, returning_dsr_reg, returning_ocr_reg, returning_status_reg : std_logic;
-- UNREGISTERED
signal temp_4_bits : std_logic_vector(3 downto 0);
signal message_done, CRC_generator_out, produce_next_bit : std_logic;
signal app_specific_valid, regular_command_valid : std_logic;
signal response_type, response_type_reg : std_logic_vector(2 downto 0);
signal cmd_argument : std_logic_vector(31 downto 0);
begin
-- This set of bits is necessary to allow the SD card to accept a VDD level for communication.
temp_4_bits <= "1111" when ((i_OCR(23) = '1') or (i_OCR(22) = '1') or (i_OCR(21) = '1') or (i_OCR(20) = '1')) else "0000";
-- Generate the bits to be sent to the SD card. These bits must pass through the CRC generator
-- to produce error checking code. The error checking code will follow the message. The message terminates with
-- a logic '1'. Total message length is 48 bits.
message_data_generator: process(i_clock, i_reset_n)
begin
if (i_reset_n = '0') then
message_bits <= (OTHERS => '0');
else
if (rising_edge(i_clock)) then
if (i_generate = '1') then
-- Store type of a response.
response_type_reg <= response_type;
-- Generate a message. Please note that the predefined messages are used for initialization.
-- If executed in sequence, they will initialize the SD card to work correctly. Only once these
-- instructions are completed can the data transfer begin.
case (i_predefined_message) is
when "0000" =>
-- Generate a predefined message - CMD0.
message_bits <= ("01" & COMMAND_0_GO_IDLE & "00000000000000000000000000000000");
when "0001" =>
-- Generate a predefined message - CMD55.
message_bits <= ("01" & COMMAND_55_APP_CMD & "0000000000000000" & "0000000000000000");
when "0010" =>
-- Generate a predefined message - ACMD41.
message_bits <= ("01" & ACOMMAND_41_SEND_OP_CONDITION & "0000" & temp_4_bits & "000" & i_OCR(20) & "00000000000000000000");
when "0011" =>
-- Generate a predefined message - CMD2.
message_bits <= ("01" & COMMAND_2_ALL_SEND_CID & "00000000000000000000000000000000");
when "0100" =>
-- Generate a predefined message - CMD3.
message_bits <= ("01" & COMMAND_3_SEND_RCA & "00000000000000000000000000000000");
when "0101" =>
-- Generate a predefined message - CMD9.
message_bits <= ("01" & COMMAND_9_SEND_CSD & i_RCA & "0000000000000000");
when "0110" =>
-- Generate a predefined message - CMD4.
message_bits <= ("01" & COMMAND_4_SET_DSR & i_DSR & "0000000000000000");
when "0111" =>
-- Generate a predefined message - CMD16. Set block length to 512.
message_bits <= ("01" & COMMAND_16_SET_BLOCK_LENGTH & "0000000000000000" & "0000001000000000" );
when "1000" =>
-- Generate a predefined message - CMD7. Select the card so we can access it's data.
message_bits <= ("01" & COMMAND_7_SELECT_CARD & i_RCA & "0000001000000000" );
when "1001" =>
-- Generate a predefined message - CMD13. Send SD card status.
message_bits <= ("01" & COMMAND_13_SEND_STATUS & i_RCA & "0000000000000000");
when others =>
-- Generate a custom message
message_bits <= ("01" & i_command_ID & cmd_argument);
end case;
else
-- Shift bits out as needed
if (produce_next_bit = '1') then
-- Shift message bits.
message_bits(39 downto 1) <= message_bits(38 downto 0);
message_bits(0) <= '0';
end if;
end if;
end if;
end if;
end process;
-- Generate command argument based on the command_ID. For most commands, the argument is user specified.
-- For some commands, it is necessary to send a particular SD Card register contents. Hence, these contents are
-- sent instead of the user data.
argument_generator: process (i_command_ID, last_command_sent_was_CMD55, i_generate, i_RCA, i_DSR, i_OCR, i_argument)
begin
cmd_argument <= i_argument;
if (i_generate = '1') then
case (i_command_ID) is
when COMMAND_4_SET_DSR =>
cmd_argument <= i_DSR & i_argument(15 downto 0);
when COMMAND_7_SELECT_CARD =>
cmd_argument <= i_RCA & i_argument(15 downto 0);
when COMMAND_9_SEND_CSD =>
cmd_argument <= i_RCA & i_argument(15 downto 0);
when COMMAND_10_SEND_CID =>
cmd_argument <= i_RCA & i_argument(15 downto 0);
when COMMAND_13_SEND_STATUS =>
cmd_argument <= i_RCA & i_argument(15 downto 0);
when COMMAND_15_GO_INACTIVE =>
cmd_argument <= i_RCA & i_argument(15 downto 0);
when COMMAND_55_APP_CMD =>
cmd_argument <= i_RCA & i_argument(15 downto 0);
when ACOMMAND_41_SEND_OP_CONDITION =>
if (last_command_sent_was_CMD55 = '1') then
cmd_argument <= i_OCR;
end if;
when others =>
cmd_argument <= i_argument;
end case;
end if;
end process;
-- Validate the message ID before sending it out.
command_validator: process(i_clock, i_reset_n)
begin
if (i_reset_n = '0') then
command_valid <= '0';
else
if (rising_edge(i_clock)) then
if (i_generate = '1') then
if (("0" & i_predefined_message) >= ("0" & FIRST_NON_PREDEFINED_COMMAND)) then
-- Check the custom message
if (last_command_sent_was_CMD55 = '1') then
-- Check the application specific messages
command_valid <= app_specific_valid;
else
-- Check the default messages.
command_valid <= regular_command_valid;
end if;
else
-- A command is valid if the message is predefined.
command_valid <= '1';
end if;
end if;
end if;
end if;
end process;
-- Registers that indicate that the command sent will return contents of a control register.
-- The contents of the response should therefore be stored in the appropriate register.
responses_with_control_regs: process(i_clock, i_reset_n, last_command_sent_was_CMD55, last_command_id, message_done)
begin
if (i_reset_n = '0') then
returning_ocr_reg <= '0';
returning_cid_reg <= '0';
returning_rca_reg <= '0';
returning_csd_reg <= '0';
returning_status_reg <= '0';
elsif (rising_edge(i_clock)) then
if (i_generate = '1') then
returning_ocr_reg <= '0';
returning_cid_reg <= '0';
returning_rca_reg <= '0';
returning_csd_reg <= '0';
returning_status_reg <= '0';
elsif (message_done = '1') then
-- OCR
if ((last_command_sent_was_CMD55 = '1') and (last_command_id = ACOMMAND_41_SEND_OP_CONDITION)) then
returning_ocr_reg <= '1';
end if;
-- CID
if (last_command_id = COMMAND_2_ALL_SEND_CID) then
returning_cid_reg <= '1';
end if;
-- RCA
if (last_command_id = COMMAND_3_SEND_RCA) then
returning_rca_reg <= '1';
end if;
-- CSD
if (last_command_id = COMMAND_9_SEND_CSD) then
returning_csd_reg <= '1';
end if;
-- Status
if ((last_command_sent_was_CMD55 = '0') and (last_command_id = COMMAND_13_SEND_STATUS)) then
returning_status_reg <= '1';
end if;
end if;
end if;
end process;
-- Count the number of bits sent using a counter.
sent_bit_counter: process(i_clock, i_reset_n, i_generate, produce_next_bit, counter)
begin
if (i_reset_n = '0') then
counter <= (OTHERS => '0');
else
if (rising_edge(i_clock)) then
if (i_generate = '1') then
-- Reset the counter indicating the number of bits produced.
counter <= "0000000";
else
if (produce_next_bit = '1') then
-- Update the number of message bits sent.
counter <= counter + '1';
end if;
end if;
end if;
end if;
end process;
-- Select the source for the output data to be either the message data or the CRC bits.
source_selector: process(i_clock, i_reset_n, i_generate)
begin
if (i_reset_n = '0') then
sending_CRC <= '0';
else
if (rising_edge(i_clock)) then
if (i_generate = '1') then
-- Set sending CRC flag to 0.
sending_CRC <= '0';
else
-- If this is the last bit being sent, then bits that follow are the CRC bits.
if (counter = "0101000") then
sending_CRC <= '1';
end if;
end if;
end if;
end if;
end process;
-- When the message is sent, store its ID. In a special case when CMD55 is sent, the next command can be an application
-- specific command. We need to check those command IDs to verify the validity of the message.
CMD55_recognizer: process(i_clock, i_reset_n, i_generate, produce_next_bit, counter, message_done, last_command_id)
begin
if (i_reset_n = '0') then
last_command_sent_was_CMD55 <= '0';
else
if (rising_edge(i_clock)) then
if (i_generate = '0') then
-- Store the ID of the current command.
if (produce_next_bit = '1') then
if (counter = "0000000") then
last_command_id <= message_bits(37 downto 32);
end if;
end if;
-- When message has been sent then check if it was CMD55.
if (message_done = '1') then
if (last_command_id = COMMAND_55_APP_CMD) then
last_command_sent_was_CMD55 <= '1';
else
last_command_sent_was_CMD55 <= '0';
end if;
end if;
end if;
end if;
end if;
end process;
-- Instantiate a CRC7 generator. Message bits will pass through it to create the CRC code for the message.
CRC7_Gen: Altera_UP_SD_CRC7_Generator PORT MAP
(
i_clock => i_clock,
i_reset_n => i_reset_n,
i_enable => i_message_bit_out,
i_shift => sending_CRC,
i_datain => message_bits(39),
o_dataout => CRC_generator_out
);
-- Define the source of the data produced by this module, depending on the counter value and the sending_CRC register state.
data_bit_register: process(i_clock, i_reset_n, i_generate, produce_next_bit, counter)
begin
if (i_reset_n = '0') then
bit_to_send <= '1';
else
if (rising_edge(i_clock)) then
if (i_generate = '1') then
bit_to_send <= '1';
elsif (produce_next_bit = '1') then
-- Send data to output.
if (sending_CRC = '0') then
-- Send message bits
bit_to_send <= message_bits(39);
else
-- Send CRC bits
if ((counter = "0101111") or (counter = "0110000")) then
-- At the end of CRC bits put a 1.
bit_to_send <= '1';
else
bit_to_send <= CRC_generator_out;
end if;
end if;
end if;
end if;
end if;
end process;
-- Define conditions to produce the next message bit on the module output port o_dataout.
produce_next_bit <= i_message_bit_out and (not message_done);
-- Message is done when the last bit appears at the output.
message_done <= '1' when (counter = "0110001") else '0';
-- Check the application specific messages
app_specific_valid <= '1' when (
--(i_command_ID = COMMAND_0_GO_IDLE) or
(i_command_ID = COMMAND_2_ALL_SEND_CID) or
(i_command_ID = COMMAND_3_SEND_RCA) or
(i_command_ID = COMMAND_4_SET_DSR) or
--(i_command_ID = ACOMMAND_6_SET_BUS_WIDTH) or
--(i_command_ID = COMMAND_7_SELECT_CARD) or
(i_command_ID = COMMAND_9_SEND_CSD) or
(i_command_ID = COMMAND_10_SEND_CID) or
--(i_command_ID = COMMAND_12_STOP_TRANSMISSION) or
(i_command_ID = ACOMMAND_13_SD_STATUS) or
--(i_command_ID = COMMAND_15_GO_INACTIVE) or
--(i_command_ID = COMMAND_16_SET_BLOCK_LENGTH) or
(i_command_ID = COMMAND_17_READ_BLOCK) or
--(i_command_ID = COMMAND_18_READ_MULTIPLE_BLOCKS) or
(i_command_ID = ACOMMAND_22_SEND_NUM_WR_BLOCKS) or
(i_command_ID = ACOMMAND_23_SET_BLK_ERASE_COUNT) or
(i_command_ID = COMMAND_24_WRITE_BLOCK) or
(i_command_ID = COMMAND_25_WRITE_MULTIPLE_BLOCKS) or
(i_command_ID = COMMAND_27_PROGRAM_CSD) or
(i_command_ID = COMMAND_28_SET_WRITE_PROTECT) or
(i_command_ID = COMMAND_29_CLEAR_WRITE_PROTECT) or
(i_command_ID = COMMAND_30_SEND_PROTECTED_GROUPS) or
(i_command_ID = COMMAND_32_ERASE_BLOCK_START) or
(i_command_ID = COMMAND_33_ERASE_BLOCK_END) or
(i_command_ID = COMMAND_38_ERASE_SELECTED_GROUPS) or
(i_command_ID = ACOMMAND_41_SEND_OP_CONDITION) or
(i_command_ID = ACOMMAND_42_SET_CLR_CARD_DETECT) or
(i_command_ID = ACOMMAND_51_SEND_SCR) or
(i_command_ID = COMMAND_55_APP_CMD) or
(i_command_ID = COMMAND_56_GEN_CMD)
)
else '0';
-- Check the default messages.
regular_command_valid <= '1' when (
-------------------------------------------------------
-- Disabled to prevent malfunction of the core
-------------------------------------------------------
--(i_command_ID = COMMAND_0_GO_IDLE) or
--(i_command_ID = COMMAND_6_SWITCH_FUNCTION) or
--(i_command_ID = COMMAND_7_SELECT_CARD) or
--(i_command_ID = COMMAND_15_GO_INACTIVE) or
--(i_command_ID = COMMAND_27_PROGRAM_CSD) or
--(i_command_ID = COMMAND_30_SEND_PROTECTED_GROUPS) or
--(i_command_ID = COMMAND_42_LOCK_UNLOCK) or
-------------------------------------------------------
(i_command_ID = COMMAND_2_ALL_SEND_CID) or
(i_command_ID = COMMAND_3_SEND_RCA) or
(i_command_ID = COMMAND_4_SET_DSR) or
(i_command_ID = COMMAND_9_SEND_CSD) or
(i_command_ID = COMMAND_10_SEND_CID) or
(i_command_ID = COMMAND_13_SEND_STATUS) or
-------------------------------------------------------
-- Disabled to simplify the circuit
-------------------------------------------------------
--(i_command_ID = COMMAND_12_STOP_TRANSMISSION) or
--(i_command_ID = COMMAND_16_SET_BLOCK_LENGTH) or
--(i_command_ID = COMMAND_18_READ_MULTIPLE_BLOCKS) or
--(i_command_ID = COMMAND_25_WRITE_MULTIPLE_BLOCKS) or
-------------------------------------------------------
(i_command_ID = COMMAND_17_READ_BLOCK) or
(i_command_ID = COMMAND_24_WRITE_BLOCK) or
(i_command_ID = COMMAND_28_SET_WRITE_PROTECT) or
(i_command_ID = COMMAND_29_CLEAR_WRITE_PROTECT) or
(i_command_ID = COMMAND_32_ERASE_BLOCK_START) or
(i_command_ID = COMMAND_33_ERASE_BLOCK_END) or
(i_command_ID = COMMAND_38_ERASE_SELECTED_GROUPS) or
(i_command_ID = COMMAND_55_APP_CMD) or
(i_command_ID = COMMAND_56_GEN_CMD)
)
else '0';
response_type <= "001" when -- Wait for type 1 response when
(
(i_predefined_message = "0001") or
(i_predefined_message = "0111") or
(i_predefined_message = "1000") or
(i_predefined_message = "1001") or
((i_predefined_message = FIRST_NON_PREDEFINED_COMMAND) and
((i_command_ID = COMMAND_6_SWITCH_FUNCTION) or
(i_command_ID = COMMAND_7_SELECT_CARD) or
(i_command_ID = COMMAND_12_STOP_TRANSMISSION) or
(i_command_ID = COMMAND_13_SEND_STATUS) or
(i_command_ID = COMMAND_16_SET_BLOCK_LENGTH) or
(i_command_ID = COMMAND_17_READ_BLOCK) or
(i_command_ID = COMMAND_18_READ_MULTIPLE_BLOCKS) or
(i_command_ID = COMMAND_24_WRITE_BLOCK) or
(i_command_ID = COMMAND_25_WRITE_MULTIPLE_BLOCKS) or
(i_command_ID = COMMAND_27_PROGRAM_CSD) or
(i_command_ID = COMMAND_28_SET_WRITE_PROTECT) or
(i_command_ID = COMMAND_29_CLEAR_WRITE_PROTECT) or
(i_command_ID = COMMAND_30_SEND_PROTECTED_GROUPS) or
(i_command_ID = COMMAND_32_ERASE_BLOCK_START) or
(i_command_ID = COMMAND_33_ERASE_BLOCK_END) or
(i_command_ID = COMMAND_38_ERASE_SELECTED_GROUPS) or
(i_command_ID = COMMAND_42_LOCK_UNLOCK) or
(i_command_ID = COMMAND_55_APP_CMD) or
(i_command_ID = COMMAND_56_GEN_CMD) or
((last_command_sent_was_CMD55 = '1') and
((i_command_ID = ACOMMAND_6_SET_BUS_WIDTH) or
(i_command_ID = ACOMMAND_13_SD_STATUS) or
(i_command_ID = ACOMMAND_22_SEND_NUM_WR_BLOCKS) or
(i_command_ID = ACOMMAND_23_SET_BLK_ERASE_COUNT) or
(i_command_ID = ACOMMAND_42_SET_CLR_CARD_DETECT) or
(i_command_ID = ACOMMAND_51_SEND_SCR)))))
) else
"010" when -- Wait for type 2 response when
(
((i_predefined_message = FIRST_NON_PREDEFINED_COMMAND) and
((i_command_ID = COMMAND_2_ALL_SEND_CID) or
(i_command_ID = COMMAND_9_SEND_CSD) or
(i_command_ID = COMMAND_10_SEND_CID))) or
(i_predefined_message = "0011") or
(i_predefined_message = "0101")
) else
"011" when -- Wait for type 3 response when
(
((i_predefined_message = FIRST_NON_PREDEFINED_COMMAND) and (last_command_sent_was_CMD55 = '1') and (i_command_ID = ACOMMAND_41_SEND_OP_CONDITION)) or
(i_predefined_message = "0010")
) else
"110" when -- Wait for type 6 response when
(((i_predefined_message = FIRST_NON_PREDEFINED_COMMAND) and (i_command_ID = COMMAND_3_SEND_RCA)) or
(i_predefined_message = "0100"))
else "000"; -- Otherwise there is no response pending.
-- Define circuit outputs
o_message_done <= message_done;
o_response_type <= response_type_reg;
o_valid <= command_valid;
o_dataout <= bit_to_send;
o_returning_ocr <= returning_ocr_reg;
o_returning_cid <= returning_cid_reg;
o_returning_rca <= returning_rca_reg;
o_returning_csd <= returning_csd_reg;
o_returning_status <= returning_status_reg;
o_data_read <= '1' when (last_command_id = COMMAND_17_READ_BLOCK) else '0';
o_data_write <= '1' when (last_command_id = COMMAND_24_WRITE_BLOCK) else '0';
o_last_cmd_was_55 <= last_command_sent_was_CMD55;
o_wait_cmd_busy <= '1' when (
(last_command_id = COMMAND_7_SELECT_CARD) or
(last_command_id = COMMAND_12_STOP_TRANSMISSION) or
(last_command_id = COMMAND_28_SET_WRITE_PROTECT) or
(last_command_id = COMMAND_29_CLEAR_WRITE_PROTECT) or
(last_command_id = COMMAND_38_ERASE_SELECTED_GROUPS))
else '0';
end rtl; | gpl-2.0 | 3bbd38374aec6b1da667b0007e03ffd6 | 0.619468 | 3.125711 | false | false | false | false |
impedimentToProgress/UCI-BlueChip | AttackFiles/Attacks/privEsc/lib/grlib/sparc/cpu_disas.vhd | 2 | 4,248 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Package: cpu_disas
-- File: cpu_disas.vhd
-- Author: Jiri Gaisler, Gaisler Research
-- Description: SPARC disassembler according to SPARC V8 manual
------------------------------------------------------------------------------
-- pragma translate_off
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.stdlib.all;
use grlib.sparc.all;
use grlib.sparc_disas.all;
entity cpu_disas is
port (
clk : in std_ulogic;
rstn : in std_ulogic;
dummy : out std_ulogic;
inst : in std_logic_vector(31 downto 0);
pc : in std_logic_vector(31 downto 2);
result: in std_logic_vector(31 downto 0);
index : in std_logic_vector(3 downto 0);
wreg : in std_ulogic;
annul : in std_ulogic;
holdn : in std_ulogic;
pv : in std_ulogic;
trap : in std_ulogic;
disas : in std_ulogic);
end;
architecture behav of cpu_disas is
begin
dummy <= '1';
trc : process(clk)
variable valid : boolean;
variable op : std_logic_vector(1 downto 0);
variable op3 : std_logic_vector(5 downto 0);
variable fpins, fpld : boolean;
variable iindex : integer;
begin
iindex := conv_integer(index);
op := inst(31 downto 30); op3 := inst(24 downto 19);
fpins := (op = FMT3) and ((op3 = FPOP1) or (op3 = FPOP2));
fpld := (op = LDST) and ((op3 = LDF) or (op3 = LDDF) or (op3 = LDFSR));
valid := (((not annul) and pv) = '1') and (not ((fpins or fpld) and (trap = '0')));
valid := valid and (holdn = '1');
if rising_edge(clk) and (rstn = '1') then
print_insn (iindex, pc(31 downto 2) & "00", inst,
result, valid, trap = '1', wreg = '1', false);
end if;
end process;
end;
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.stdlib.all;
use grlib.sparc.all;
use grlib.sparc_disas.all;
entity fpu_disas is
port (
clk : in std_ulogic;
rstn : in std_ulogic;
dummy : out std_ulogic;
wr2inst : in std_logic_vector(31 downto 0);
wr2pc : in std_logic_vector(31 downto 2);
divinst : in std_logic_vector(31 downto 0);
divpc : in std_logic_vector(31 downto 2);
dbg_wrdata: in std_logic_vector(63 downto 0);
index : in std_logic_vector(3 downto 0);
dbg_wren : in std_logic_vector(1 downto 0);
resv : in std_ulogic;
ld : in std_ulogic;
rdwr : in std_ulogic;
ccwr : in std_ulogic;
rdd : in std_ulogic;
div_valid : in std_ulogic;
holdn : in std_ulogic;
disas : in std_ulogic);
end;
architecture behav of fpu_disas is
begin
dummy <= '1';
trc : process(clk)
variable valid : boolean;
variable op : std_logic_vector(1 downto 0);
variable op3 : std_logic_vector(5 downto 0);
variable fpins, fpld : boolean;
variable iindex : integer;
begin
iindex := conv_integer(index);
if rising_edge(clk) and (rstn = '1') then
valid := ((((rdwr and not ld) or ccwr or (ld and resv)) and holdn) = '1');
print_fpinsn(0, wr2pc(31 downto 2) & "00", wr2inst, dbg_wrdata,
(rdd = '1'), valid, false, (dbg_wren /= "00"));
print_fpinsn(0, divpc(31 downto 2) & "00", divinst, dbg_wrdata,
(rdd = '1'), (div_valid and holdn) = '1', false, (dbg_wren /= "00"));
end if;
end process;
end;
-- pragma translate_on
| mit | 30220fec7a160d36b562da3abfd894c6 | 0.602872 | 3.442464 | false | false | false | false |
impedimentToProgress/UCI-BlueChip | AttackFiles/Attacks/privEsc/lib/gaisler/leon3/mmulru.vhd | 2 | 5,263 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: mmulru
-- File: mmulru.vhd
-- Author: Konrad Eisele, Jiri Gaisler, Gaisler Research
-- Description: MMU LRU logic
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
library gaisler;
use gaisler.libiu.all;
use gaisler.libcache.all;
use gaisler.leon3.all;
use gaisler.mmuconfig.all;
use gaisler.mmuiface.all;
entity mmulru is
generic (
entries : integer := 8
);
port (
rst : in std_logic;
clk : in std_logic;
lrui : in mmulru_in_type;
lruo : out mmulru_out_type
);
end mmulru;
architecture rtl of mmulru is
constant entries_log : integer := log2(entries);
component mmulrue
generic (
position : integer;
entries : integer := 8
);
port (
rst : in std_logic;
clk : in std_logic;
lruei : in mmulrue_in_type;
lrueo : out mmulrue_out_type
);
end component;
type lru_rtype is record
bar : std_logic_vector(1 downto 0);
clear : std_logic_vector(M_ENT_MAX-1 downto 0);
-- pragma translate_off
reinit : std_logic;
pos : std_logic_vector(entries_log-1 downto 0);
-- pragma translate_on
end record;
signal c,r : lru_rtype;
signal lruei : mmulruei_a (entries-1 downto 0);
signal lrueo : mmulrueo_a (entries-1 downto 0);
begin
p0: process (rst, r, c, lrui, lrueo)
variable v : lru_rtype;
variable reinit : std_logic;
variable v_lruei_clk : std_logic;
variable pos : std_logic_vector(entries_log-1 downto 0);
variable touch : std_logic;
begin
v := r;
-- #init
reinit := '0';
v_lruei_clk := rst;
--# eather element in luri or element 0 to top
pos := lrui.pos(entries_log-1 downto 0);
touch := lrui.touch;
if (lrui.touchmin) = '1' then
pos := lrueo(0).pos(entries_log-1 downto 0);
touch := '1';
end if;
for i in entries-1 downto 0 loop
lruei(i).pos <= (others => '0'); -- this is really ugly ...
lruei(i).left <= (others => '0');
lruei(i).right <= (others => '0');
lruei(i).pos(entries_log-1 downto 0) <= pos;
lruei(i).touch <= touch;
lruei(i).clear <= r.clear((entries-1)-i); -- reverse order
lruei(i).flush <= lrui.flush;
end loop;
lruei(entries-1).fromleft <= '0';
lruei(entries-1).fromright <= lrueo(entries-2).movetop;
lruei(entries-1).right(entries_log-1 downto 0) <= lrueo(entries-2).pos(entries_log-1 downto 0);
for i in entries-2 downto 1 loop
lruei(i).left(entries_log-1 downto 0) <= lrueo(i+1).pos(entries_log-1 downto 0);
lruei(i).right(entries_log-1 downto 0) <= lrueo(i-1).pos(entries_log-1 downto 0);
lruei(i).fromleft <= lrueo(i+1).movetop;
lruei(i).fromright <= lrueo(i-1).movetop;
end loop;
lruei(0).fromleft <= lrueo(1).movetop;
lruei(0).fromright <= '0';
lruei(0).left(entries_log-1 downto 0) <= lrueo(1).pos(entries_log-1 downto 0);
if not (r.bar = lrui.mmctrl1.bar) then
reinit := '1';
end if;
-- pragma translate_off
-- pragma translate_on
if (rst) = '0' then
v.bar := lrui.mmctrl1.bar;
reinit := '1';
end if;
if (reinit) = '1' then
v.bar := lrui.mmctrl1.bar;
v.clear := (others => '0');
case lrui.mmctrl1.bar is
when "01" =>
v.clear(1 downto 0) := "11"; -- reverse order
when "10" =>
v.clear(2 downto 0) := "111"; -- reverse order
when "11" =>
v.clear(4 downto 0) := "11111"; -- reverse order
when others =>
v.clear(0) := '1';
end case;
end if;
--# drive signals
-- pragma translate_off
v.reinit := reinit;
v.pos := pos;
-- pragma translate_on
lruo.pos <= lrueo(0).pos;
c <= v;
end process p0;
p1: process (clk)
begin if rising_edge(clk) then r <= c; end if;
end process p1;
--# lru entries
lrue0: for i in entries-1 downto 0 generate
l1 : mmulrue
generic map ( position => i,
entries => entries )
port map (rst, clk, lruei(i), lrueo(i));
end generate lrue0;
end rtl;
| mit | 63199c525f2989e2e36cda1120cc9458 | 0.572677 | 3.503995 | false | false | false | false |
cafe-alpha/wascafe | v13/stm32_bup_test/r07c_de10_20200912/wasca/synthesis/submodules/abus_slave.vhd | 2 | 39,755 | -- abus_slave.vhd
library IEEE;
use IEEE.numeric_std.all;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity abus_slave is
port (
clock : in std_logic := '0'; -- clock.clk
-- Demuxed signals
-- Note : naming is Saturn-centered, ie readdata = read from Saturn = output from A-Bus side = input from demux side
demux_writeaddress : in std_logic_vector(27 downto 0) := (others => '0');
demux_writedata : in std_logic_vector(15 downto 0) := (others => '0');
demux_writepulse : in std_logic := '0';
demux_write_byteenable : in std_logic_vector( 1 downto 0) := (others => '0');
demux_readaddress : in std_logic_vector(27 downto 0) := (others => '0');
demux_readdata : out std_logic_vector(15 downto 0) := (others => '0');
demux_readpulse : in std_logic := '0';
demux_readdatavalid : out std_logic := '0';
avalon_read : out std_logic; -- avalon_master.read
avalon_write : out std_logic; -- .write
avalon_waitrequest : in std_logic := '0'; -- .waitrequest
avalon_address : out std_logic_vector(27 downto 0); -- .address
avalon_readdata : in std_logic_vector(15 downto 0) := (others => '0'); -- .readdata
avalon_writedata : out std_logic_vector(15 downto 0); -- .writedata
avalon_byteenable : out std_logic_vector( 1 downto 0); -- .byteenable
avalon_burstcount : out std_logic; -- .burstcount
avalon_readdatavalid : in std_logic := '0'; -- .readdatavalid
avalon_trace_read : out std_logic; -- avalon_trace.read
avalon_trace_write : out std_logic; -- .write
avalon_trace_waitrequest : in std_logic := '0'; -- .waitrequest
avalon_trace_address : out std_logic_vector(27 downto 0); -- .address
avalon_trace_readdata : in std_logic_vector(63 downto 0) := (others => '0'); -- .readdata
avalon_trace_writedata : out std_logic_vector(63 downto 0); -- .writedata
avalon_trace_byteenable : out std_logic_vector( 7 downto 0); -- .byteenable
avalon_trace_burstcount : out std_logic; -- .burstcount
avalon_trace_readdatavalid : in std_logic := '0'; -- .readdatavalid
avalon_nios_read : in std_logic := '0'; -- avalon_master.read
avalon_nios_write : in std_logic := '0'; -- .write
avalon_nios_waitrequest : out std_logic := '0'; -- .waitrequest
avalon_nios_address : in std_logic_vector( 7 downto 0) := (others => '0'); -- .address
avalon_nios_writedata : in std_logic_vector(31 downto 0) := (others => '0'); -- .writedata
avalon_nios_burstcount : in std_logic; -- .burstcount
avalon_nios_readdata : out std_logic_vector(31 downto 0) := (others => '0'); -- .readdata
avalon_nios_readdatavalid : out std_logic := '0'; -- .readdatavalid
reset : in std_logic := '0' -- reset.reset
);
end entity abus_slave;
architecture rtl of abus_slave is
-- Avalon/register selection
TYPE transaction_type IS (TYPE_REG, TYPE_AVALON);
SIGNAL my_transaction_type : transaction_type := TYPE_REG;
TYPE wasca_mode_type IS (MODE_INIT,
MODE_POWER_MEMORY_05M, MODE_POWER_MEMORY_1M, MODE_POWER_MEMORY_2M, MODE_POWER_MEMORY_4M,
MODE_RAM_1M, MODE_RAM_4M,
MODE_ROM_KOF95,
MODE_ROM_ULTRAMAN,
MODE_BOOT);
SIGNAL wasca_mode : wasca_mode_type := MODE_INIT;
signal avalon_readdatavalid_p1 : std_logic := '0';
signal demux_readdatavalid_p1 : std_logic := '0';
signal demux_readdata_p1 : std_logic_vector(15 downto 0) := (others => '0');
signal REG_PCNTR : std_logic_vector(15 downto 0) := (others => '0');
signal REG_STATUS : std_logic_vector(15 downto 0) := (others => '0');
signal REG_MODE : std_logic_vector(15 downto 0) := (others => '0');
signal REG_HWVER : std_logic_vector(15 downto 0) := X"0002";
signal REG_SWVER : std_logic_vector(15 downto 0) := (others => '0');
-- For Rd/Wr access debug
signal rd_access_cntr : std_logic_vector( 7 downto 0) := x"01";
signal wr_access_cntr : std_logic_vector( 7 downto 0) := x"01";
signal last_rd_addr : std_logic_vector(27 downto 0) := x"ABCDEF1"; -- Last avalon read addr
signal last_rd_addr1 : std_logic_vector(27 downto 0) := x"A1A1A11"; -- Demux read addr full 28 bits, last access
signal last_rd_addr2 : std_logic_vector(27 downto 0) := x"A2A2A22"; -- Demux read addr full 28 bits, last access - 1
signal last_rd_addr3 : std_logic_vector(27 downto 0) := x"A3A3A33"; -- Demux read addr full 28 bits, last access - 2
signal last_rd_addr4 : std_logic_vector(27 downto 0) := x"A4A4A44"; -- Demux read addr full 28 bits, last access - 3
signal last_wr_addr : std_logic_vector(27 downto 0) := x"0001231";
signal last_wr_data : std_logic_vector(15 downto 0) := x"5678";
-- Access test stuff, added 2019/11/04 vvv
signal rdwr_access_buff : std_logic_vector(127 downto 0) := x"CAFE0304050607080910111213141516";
-- Access test stuff, added 2019/11/04 ^^^
-- Rd/Wr access trace -->
signal trace_cntr : std_logic_vector(15 downto 0) := x"0000";
-- Rd/Wr access trace <--
begin
---------------------------------------------------------------------------------------
-- Rd/Wr access trace
process (clock)
begin
if rising_edge(clock) then
if demux_readpulse = '1' then
avalon_trace_write <= '1';
avalon_trace_writedata(27 downto 0) <= demux_writeaddress(27 downto 0);
avalon_trace_writedata(31 downto 28) <= "0000";
avalon_trace_writedata(47 downto 32) <= X"1234"; -- Dummy read data
avalon_trace_writedata(63 downto 48) <= X"5678"; -- Some extra information (example : counter from previous access etc)
trace_cntr <= trace_cntr + x"0001";
elsif demux_writepulse = '1' then
avalon_trace_write <= '1';
avalon_trace_writedata(27 downto 0) <= demux_readaddress(27 downto 0);
avalon_trace_writedata(31 downto 28) <= "0000";
avalon_trace_writedata(47 downto 32) <= demux_writedata(15 downto 0);
avalon_trace_writedata(63 downto 48) <= X"5678"; -- Some extra information (example : counter from previous access etc)
trace_cntr <= trace_cntr + x"0001";
else
avalon_trace_write <= '0';
end if;
avalon_trace_address <= "000000000000" & trace_cntr(15 downto 0);
avalon_trace_byteenable <= "11111111";
avalon_trace_burstcount <= '1';
end if;
end process;
---------------------------------------------------------------------------------------
-- T.B.D.
process (clock)
begin
if rising_edge(clock) then
avalon_readdatavalid_p1 <= avalon_readdatavalid;
demux_readdata_p1 <= avalon_readdata(7 downto 0) & avalon_readdata (15 downto 8);
end if;
end process;
process (clock)
begin
if rising_edge(clock) then
if demux_readdatavalid_p1 = '1' then
-- Indicate that data was valid on previous clock.
demux_readdatavalid <= '0';
demux_readdatavalid_p1 <= '0';
elsif((my_transaction_type = TYPE_AVALON) and (avalon_waitrequest = '0')) then
-- Terminate request to Avalon.
my_transaction_type <= TYPE_REG;
avalon_read <= '0';
avalon_write <= '0';
elsif((avalon_readdatavalid_p1 = '1') and (avalon_readdatavalid = '0')) then
-- Pass data read back from Avalon to A-Bus demultiplexer.
demux_readdata <= demux_readdata_p1;
demux_readdatavalid <= '1';
demux_readdatavalid_p1 <= '1';
elsif demux_readpulse = '1' then
-- Debug stuff around Rd/Wr access
--rd_access_cntr <= rd_access_cntr + x"01";
last_rd_addr1 <= demux_readaddress;
last_rd_addr2 <= last_rd_addr1;
last_rd_addr3 <= last_rd_addr2;
last_rd_addr4 <= last_rd_addr3;
if demux_readaddress(25 downto 24) = "00" then
--CS0 access
if demux_readaddress(23 downto 0) = X"FF0FFE" then
--wasca specific SD card control register
demux_readdata <= X"CDCD";
demux_readdatavalid <= '1';
demux_readdatavalid_p1 <= '1';
my_transaction_type <= TYPE_REG;
-- Access test stuff, added 2019/11/04 vvv
elsif demux_readaddress(23 downto 0) = X"FFFFD0" then -- 0x23FFFFA0
demux_readdata <= x"A" & last_rd_addr(27 downto 16);
demux_readdatavalid <= '1';
demux_readdatavalid_p1 <= '1';
my_transaction_type <= TYPE_REG;
elsif demux_readaddress(23 downto 0) = X"FFFFD1" then -- 0x23FFFFA2
demux_readdata <= last_rd_addr(15 downto 0);
demux_readdatavalid <= '1';
demux_readdatavalid_p1 <= '1';
my_transaction_type <= TYPE_REG;
elsif demux_readaddress(23 downto 0) = X"FFFFD8" then -- 0x23FFFFB0
demux_readdata <= x"0" & last_rd_addr1(27 downto 16);
demux_readdatavalid <= '1';
demux_readdatavalid_p1 <= '1';
my_transaction_type <= TYPE_REG;
elsif demux_readaddress(23 downto 0) = X"FFFFD9" then -- 0x23FFFFB2
demux_readdata <= last_rd_addr1(15 downto 0);
demux_readdatavalid <= '1';
demux_readdatavalid_p1 <= '1';
my_transaction_type <= TYPE_REG;
elsif demux_readaddress(23 downto 0) = X"FFFFDA" then -- 0x23FFFFB4
demux_readdata <= x"0" & last_rd_addr2(27 downto 16);
demux_readdatavalid <= '1';
demux_readdatavalid_p1 <= '1';
my_transaction_type <= TYPE_REG;
elsif demux_readaddress(23 downto 0) = X"FFFFDB" then -- 0x23FFFFB6
demux_readdata <= last_rd_addr2(15 downto 0);
demux_readdatavalid <= '1';
demux_readdatavalid_p1 <= '1';
my_transaction_type <= TYPE_REG;
elsif demux_readaddress(23 downto 0) = X"FFFFDC" then -- 0x23FFFFB8
demux_readdata <= x"0" & last_rd_addr3(27 downto 16);
demux_readdatavalid <= '1';
demux_readdatavalid_p1 <= '1';
my_transaction_type <= TYPE_REG;
elsif demux_readaddress(23 downto 0) = X"FFFFDD" then -- 0x23FFFFBA
demux_readdata <= last_rd_addr3(15 downto 0);
demux_readdatavalid <= '1';
demux_readdatavalid_p1 <= '1';
my_transaction_type <= TYPE_REG;
elsif demux_readaddress(23 downto 0) = X"FFFFDE" then -- 0x23FFFFBC
demux_readdata <= x"0" & last_rd_addr4(27 downto 16);
demux_readdatavalid <= '1';
demux_readdatavalid_p1 <= '1';
my_transaction_type <= TYPE_REG;
elsif demux_readaddress(23 downto 0) = X"FFFFDF" then -- 0x23FFFFBE
demux_readdata <= last_rd_addr4(15 downto 0);
demux_readdatavalid <= '1';
demux_readdatavalid_p1 <= '1';
my_transaction_type <= TYPE_REG;
elsif demux_readaddress(23 downto 0) = X"FFFFE0" then -- 0x23FFFFC0
demux_readdata <= rdwr_access_buff(127 downto 112);
demux_readdatavalid <= '1';
demux_readdatavalid_p1 <= '1';
my_transaction_type <= TYPE_REG;
elsif demux_readaddress(23 downto 0) = X"FFFFE1" then -- 0x23FFFFC2
demux_readdata <= rdwr_access_buff(111 downto 96);
demux_readdatavalid <= '1';
demux_readdatavalid_p1 <= '1';
my_transaction_type <= TYPE_REG;
elsif demux_readaddress(23 downto 0) = X"FFFFE2" then -- 0x23FFFFC4
demux_readdata <= rdwr_access_buff( 95 downto 80);
demux_readdatavalid <= '1';
demux_readdatavalid_p1 <= '1';
my_transaction_type <= TYPE_REG;
elsif demux_readaddress(23 downto 0) = X"FFFFE3" then -- 0x23FFFFC6
demux_readdata <= rdwr_access_buff( 79 downto 64);
demux_readdatavalid <= '1';
demux_readdatavalid_p1 <= '1';
my_transaction_type <= TYPE_REG;
elsif demux_readaddress(23 downto 0) = X"FFFFE4" then -- 0x23FFFFC8
demux_readdata <= rdwr_access_buff( 63 downto 48);
demux_readdatavalid <= '1';
demux_readdatavalid_p1 <= '1';
my_transaction_type <= TYPE_REG;
elsif demux_readaddress(23 downto 0) = X"FFFFE5" then -- 0x23FFFFCA
demux_readdata <= rdwr_access_buff( 47 downto 32);
demux_readdatavalid <= '1';
demux_readdatavalid_p1 <= '1';
my_transaction_type <= TYPE_REG;
elsif demux_readaddress(23 downto 0) = X"FFFFE6" then -- 0x23FFFFCC
demux_readdata <= rdwr_access_buff( 31 downto 16);
demux_readdatavalid <= '1';
demux_readdatavalid_p1 <= '1';
my_transaction_type <= TYPE_REG;
elsif demux_readaddress(23 downto 0) = X"FFFFE7" then -- 0x23FFFFCE
demux_readdata <= rdwr_access_buff( 15 downto 0);
demux_readdatavalid <= '1';
demux_readdatavalid_p1 <= '1';
my_transaction_type <= TYPE_REG;
elsif demux_readaddress(23 downto 0) = X"FFFFE8" then -- 0x23FFFFD0
demux_readdata <= x"5445"; -- "TE"
demux_readdatavalid <= '1';
demux_readdatavalid_p1 <= '1';
my_transaction_type <= TYPE_REG;
elsif demux_readaddress(23 downto 0) = X"FFFFE9" then -- 0x23FFFFD2
demux_readdata <= x"5354"; -- "ST"
demux_readdatavalid <= '1';
demux_readdatavalid_p1 <= '1';
my_transaction_type <= TYPE_REG;
elsif demux_readaddress(23 downto 0) = X"FFFFEA" then -- 0x23FFFFD4
demux_readdata <= X"FFFF";
demux_readdatavalid <= '1';
demux_readdatavalid_p1 <= '1';
my_transaction_type <= TYPE_REG;
elsif demux_readaddress(23 downto 0) = X"FFFFEB" then -- 0x23FFFFD6
demux_readdata <= X"5A5A";
demux_readdatavalid <= '1';
demux_readdatavalid_p1 <= '1';
my_transaction_type <= TYPE_REG;
elsif demux_readaddress(23 downto 0) = X"FFFFEC" then -- 0x23FFFFD8
demux_readdata <= X"FFFF";
demux_readdatavalid <= '1';
demux_readdatavalid_p1 <= '1';
my_transaction_type <= TYPE_REG;
elsif demux_readaddress(23 downto 0) = X"FFFFED" then -- 0x23FFFFDA
demux_readdata <= X"FFFF";
demux_readdatavalid <= '1';
demux_readdatavalid_p1 <= '1';
my_transaction_type <= TYPE_REG;
elsif demux_readaddress(23 downto 0) = X"FFFFEE" then -- 0x23FFFFDC
demux_readdata <= X"FFFF";
demux_readdatavalid <= '1';
demux_readdatavalid_p1 <= '1';
my_transaction_type <= TYPE_REG;
elsif demux_readaddress(23 downto 0) = X"FFFFEF" then -- 0x23FFFFDE
demux_readdata <= X"FFFF";
demux_readdatavalid <= '1';
demux_readdatavalid_p1 <= '1';
my_transaction_type <= TYPE_REG;
-- Access test stuff, added 2019/11/04 ^^^
elsif demux_readaddress(23 downto 0) = X"FFFFF0" then -- 0x23FFFFE0
demux_readdata <= X"FFFF"; -- Test for cartridge assembly
demux_readdatavalid <= '1';
demux_readdatavalid_p1 <= '1';
my_transaction_type <= TYPE_REG;
elsif demux_readaddress(23 downto 0) = X"FFFFF1" then -- 0x23FFFFE2
demux_readdata <= X"0000"; -- Test for cartridge assembly
demux_readdatavalid <= '1';
demux_readdatavalid_p1 <= '1';
my_transaction_type <= TYPE_REG;
elsif demux_readaddress(23 downto 0) = X"FFFFF2" then -- 0x23FFFFE4
demux_readdata <= X"A5A5"; -- Test for cartridge assembly
demux_readdatavalid <= '1';
demux_readdatavalid_p1 <= '1';
my_transaction_type <= TYPE_REG;
elsif demux_readaddress(23 downto 0) = X"FFFFF3" then -- 0x23FFFFE6
demux_readdata <= X"5A5A"; -- Test for cartridge assembly
demux_readdatavalid <= '1';
demux_readdatavalid_p1 <= '1';
my_transaction_type <= TYPE_REG;
elsif demux_readaddress(23 downto 0) = X"FFFFF4" then -- 0x23FFFFE8
demux_readdata <= x"CA" & rd_access_cntr;
demux_readdatavalid <= '1';
demux_readdatavalid_p1 <= '1';
my_transaction_type <= TYPE_REG;
elsif demux_readaddress(23 downto 0) = X"FFFFF5" then -- 0x23FFFFEA
demux_readdata <= x"AC" & rd_access_cntr;
demux_readdatavalid <= '1';
demux_readdatavalid_p1 <= '1';
my_transaction_type <= TYPE_REG;
elsif demux_readaddress(23 downto 0) = X"FFFFF6" then -- 0x23FFFFEC
demux_readdata <= x"FE" & wr_access_cntr;
demux_readdatavalid <= '1';
demux_readdatavalid_p1 <= '1';
my_transaction_type <= TYPE_REG;
elsif demux_readaddress(23 downto 0) = X"FFFFF7" then -- 0x23FFFFEE
demux_readdata <= x"EF" & wr_access_cntr;
demux_readdatavalid <= '1';
demux_readdatavalid_p1 <= '1';
my_transaction_type <= TYPE_REG;
elsif demux_readaddress(23 downto 0) = X"FFFFF8" then -- 0x23FFFFF0
--wasca prepare counter
demux_readdata <= REG_PCNTR;
demux_readdatavalid <= '1';
demux_readdatavalid_p1 <= '1';
my_transaction_type <= TYPE_REG;
elsif demux_readaddress(23 downto 0) = X"FFFFF9" then -- 0x23FFFFF2
--wasca status register
demux_readdata <= REG_STATUS;
demux_readdatavalid <= '1';
demux_readdatavalid_p1 <= '1';
my_transaction_type <= TYPE_REG;
elsif demux_readaddress(23 downto 0) = X"FFFFFA" then -- 0x23FFFFF4
--wasca mode register
demux_readdata <= REG_MODE;
demux_readdatavalid <= '1';
demux_readdatavalid_p1 <= '1';
my_transaction_type <= TYPE_REG;
elsif demux_readaddress(23 downto 0) = X"FFFFFB" then -- 0x23FFFFF6
--wasca hwver register
demux_readdata <= REG_HWVER;
demux_readdatavalid <= '1';
demux_readdatavalid_p1 <= '1';
my_transaction_type <= TYPE_REG;
elsif demux_readaddress(23 downto 0) = X"FFFFFC" then -- 0x23FFFFF8
--wasca swver register
demux_readdata <= REG_SWVER;
demux_readdatavalid <= '1';
demux_readdatavalid_p1 <= '1';
my_transaction_type <= TYPE_REG;
elsif demux_readaddress(23 downto 0) = X"FFFFFD" then -- 0x23FFFFFA
--wasca signature "wa"
demux_readdata <= X"7761";
demux_readdatavalid <= '1';
demux_readdatavalid_p1 <= '1';
my_transaction_type <= TYPE_REG;
elsif demux_readaddress(23 downto 0) = X"FFFFFE" then
--wasca signature "sc"
demux_readdata <= X"7363";
demux_readdatavalid <= '1';
demux_readdatavalid_p1 <= '1';
my_transaction_type <= TYPE_REG;
elsif demux_readaddress(23 downto 0) = X"FFFFFF" then
--wasca signature "a "
demux_readdata <= X"6120";
demux_readdatavalid <= '1';
demux_readdatavalid_p1 <= '1';
my_transaction_type <= TYPE_REG;
else
--normal CS0 read access
avalon_read <= '1';
--demux_readdata <= X"FF0A";
demux_readdatavalid <= '0';
my_transaction_type <= TYPE_AVALON;
avalon_address <= "1" & demux_readaddress(23) & "00" & demux_readaddress(22 downto 0) & "0"; -- SDRAM and OCRAM available from A-Bus
-- Set the data masks to read all bytes
avalon_byteenable <= "11";
rd_access_cntr <= rd_access_cntr + x"01";
last_rd_addr <= demux_readaddress;
-- case wasca_mode is
-- when MODE_INIT => demux_readdata <= avalon_readdata(7 downto 0) & avalon_readdata (15 downto 8) ;
-- when MODE_POWER_MEMORY_05M => demux_readdata <= X"FFFF";
-- when MODE_POWER_MEMORY_1M => demux_readdata <= X"FFFF";
-- when MODE_POWER_MEMORY_2M => demux_readdata <= X"FFFF";
-- when MODE_POWER_MEMORY_4M => demux_readdata <= X"FFFF";
-- when MODE_RAM_1M => demux_readdata <= avalon_readdata(7 downto 0) & avalon_readdata (15 downto 8) ;
-- when MODE_RAM_4M => demux_readdata <= avalon_readdata(7 downto 0) & avalon_readdata (15 downto 8) ;
-- when MODE_ROM_KOF95 => demux_readdata <= avalon_readdata(7 downto 0) & avalon_readdata (15 downto 8) ;
-- when MODE_ROM_ULTRAMAN => demux_readdata <= avalon_readdata(7 downto 0) & avalon_readdata (15 downto 8) ;
-- when MODE_BOOT => demux_readdata <= avalon_readdata(7 downto 0) & avalon_readdata (15 downto 8) ;
-- end case;
end if;
elsif demux_readaddress(25 downto 24) = "01" then
--CS1 access
if ( demux_readaddress(23 downto 0) = X"FFFFFF" or demux_readaddress(23 downto 0) = X"FFFFFD" ) then
--saturn cart id register
case wasca_mode is
when MODE_INIT => demux_readdata <= avalon_readdata(7 downto 0) & avalon_readdata (15 downto 8) ;
when MODE_POWER_MEMORY_05M => demux_readdata <= X"FF21";
when MODE_POWER_MEMORY_1M => demux_readdata <= X"FF22";
when MODE_POWER_MEMORY_2M => demux_readdata <= X"FF23";
when MODE_POWER_MEMORY_4M => demux_readdata <= X"FF24";
when MODE_RAM_1M => demux_readdata <= X"FF5A";
when MODE_RAM_4M => demux_readdata <= X"FF5C";
when MODE_ROM_KOF95 => demux_readdata <= X"FFFD";
when MODE_ROM_ULTRAMAN => demux_readdata <= X"FFFE";
when MODE_BOOT => demux_readdata <= X"FFAA";
end case;
demux_readdatavalid <= '1';
demux_readdatavalid_p1 <= '1';
my_transaction_type <= TYPE_REG;
else
--normal CS1 access
avalon_read <= '1';
--demux_readdata <= X"FF0A";
demux_readdatavalid <= '0';
my_transaction_type <= TYPE_AVALON;
avalon_address <= "1" & demux_readaddress(23) & "00" & demux_readaddress(22 downto 0) & "0"; -- SDRAM and OCRAM available from A-Bus
-- Set the data masks to read all bytes
avalon_byteenable <= "11";
rd_access_cntr <= rd_access_cntr + x"01";
last_rd_addr <= demux_readaddress;
-- case wasca_mode is
--
-- -- [DEBUG]Show which address is being accessed,
-- -- [DEBUG]in order to verify multiplexer wiring.
-- --when MODE_INIT => demux_readdata <= demux_readaddress(15 downto 0);
--
-- when MODE_INIT => demux_readdata <= avalon_readdata(7 downto 0) & avalon_readdata (15 downto 8) ;
-- when MODE_POWER_MEMORY_05M => demux_readdata <= avalon_readdata(7 downto 0) & avalon_readdata (15 downto 8) ;
-- when MODE_POWER_MEMORY_1M => demux_readdata <= avalon_readdata(7 downto 0) & avalon_readdata (15 downto 8) ;
-- when MODE_POWER_MEMORY_2M => demux_readdata <= avalon_readdata(7 downto 0) & avalon_readdata (15 downto 8) ;
-- when MODE_POWER_MEMORY_4M => demux_readdata <= avalon_readdata(7 downto 0) & avalon_readdata (15 downto 8) ;
-- when MODE_RAM_1M => demux_readdata <= X"FFF1";
-- when MODE_RAM_4M => demux_readdata <= X"FFF2";
-- when MODE_ROM_KOF95 => demux_readdata <= X"FFF3";
-- when MODE_ROM_ULTRAMAN => demux_readdata <= X"FFF4";
-- when MODE_BOOT => demux_readdata <= X"FFF5";
-- end case;
end if;
else
--CS2 access
demux_readdata <= X"EEEE";
demux_readdatavalid <= '1';
my_transaction_type <= TYPE_REG;
end if;
elsif demux_writepulse = '1' then
-- Debug stuff around Rd/Wr access
wr_access_cntr <= wr_access_cntr + x"01";
last_wr_addr <= demux_writeaddress;
last_wr_data <= demux_writedata;
--if demux_writeaddress(25 downto 24) = "00" then <-- Don't care about CS for now.
if demux_writeaddress(23 downto 0) = X"FFFFFA" then -- 0x23FFFFF4
--wasca mode register
REG_MODE <= demux_writedata;
case (demux_writedata (3 downto 0)) is
when X"1" => wasca_mode <= MODE_POWER_MEMORY_05M;
when X"2" => wasca_mode <= MODE_POWER_MEMORY_1M;
when X"3" => wasca_mode <= MODE_POWER_MEMORY_2M;
when X"4" => wasca_mode <= MODE_POWER_MEMORY_4M;
when others =>
case (demux_writedata (7 downto 4)) is
when X"1" => wasca_mode <= MODE_RAM_1M;
when X"2" => wasca_mode <= MODE_RAM_4M;
when others =>
case (demux_writedata (11 downto 8)) is
when X"1" => wasca_mode <= MODE_ROM_KOF95;
when X"2" => wasca_mode <= MODE_ROM_ULTRAMAN;
when others => null;-- wasca_mode <= MODE_INIT;
end case;
end case;
end case;
my_transaction_type <= TYPE_REG;
-- Access test stuff, added 2019/11/04 vvv
elsif demux_writeaddress(23 downto 0) = X"FFFFE0" then -- 0x23FFFFC0
if(demux_write_byteenable(1) = '1') then rdwr_access_buff(127 downto 120) <= demux_writedata(15 downto 8); end if;
if(demux_write_byteenable(0) = '1') then rdwr_access_buff(119 downto 112) <= demux_writedata( 7 downto 0); end if;
my_transaction_type <= TYPE_REG;
elsif demux_writeaddress(23 downto 0) = X"FFFFE1" then -- 0x23FFFFC2
if(demux_write_byteenable(1) = '1') then rdwr_access_buff(111 downto 104) <= demux_writedata(15 downto 8); end if;
if(demux_write_byteenable(0) = '1') then rdwr_access_buff(103 downto 96) <= demux_writedata( 7 downto 0); end if;
my_transaction_type <= TYPE_REG;
elsif demux_writeaddress(23 downto 0) = X"FFFFE2" then -- 0x23FFFFC4
if(demux_write_byteenable(1) = '1') then rdwr_access_buff( 95 downto 88) <= demux_writedata(15 downto 8); end if;
if(demux_write_byteenable(0) = '1') then rdwr_access_buff( 87 downto 80) <= demux_writedata( 7 downto 0); end if;
my_transaction_type <= TYPE_REG;
elsif demux_writeaddress(23 downto 0) = X"FFFFE3" then -- 0x23FFFFC6
if(demux_write_byteenable(1) = '1') then rdwr_access_buff( 79 downto 72) <= demux_writedata(15 downto 8); end if;
if(demux_write_byteenable(0) = '1') then rdwr_access_buff( 71 downto 64) <= demux_writedata( 7 downto 0); end if;
my_transaction_type <= TYPE_REG;
elsif demux_writeaddress(23 downto 0) = X"FFFFE4" then -- 0x23FFFFC8
if(demux_write_byteenable(1) = '1') then rdwr_access_buff( 63 downto 56) <= demux_writedata(15 downto 8); end if;
if(demux_write_byteenable(0) = '1') then rdwr_access_buff( 55 downto 48) <= demux_writedata( 7 downto 0); end if;
my_transaction_type <= TYPE_REG;
elsif demux_writeaddress(23 downto 0) = X"FFFFE5" then -- 0x23FFFFCA
if(demux_write_byteenable(1) = '1') then rdwr_access_buff( 47 downto 40) <= demux_writedata(15 downto 8); end if;
if(demux_write_byteenable(0) = '1') then rdwr_access_buff( 39 downto 32) <= demux_writedata( 7 downto 0); end if;
my_transaction_type <= TYPE_REG;
elsif demux_writeaddress(23 downto 0) = X"FFFFE6" then -- 0x23FFFFCC
if(demux_write_byteenable(1) = '1') then rdwr_access_buff( 31 downto 24) <= demux_writedata(15 downto 8); end if;
if(demux_write_byteenable(0) = '1') then rdwr_access_buff( 23 downto 16) <= demux_writedata( 7 downto 0); end if;
my_transaction_type <= TYPE_REG;
elsif demux_writeaddress(23 downto 0) = X"FFFFE7" then -- 0x23FFFFCE
if(demux_write_byteenable(1) = '1') then rdwr_access_buff( 15 downto 8) <= demux_writedata(15 downto 8); end if;
if(demux_write_byteenable(0) = '1') then rdwr_access_buff( 7 downto 0) <= demux_writedata( 7 downto 0); end if;
my_transaction_type <= TYPE_REG;
-- Access test stuff, added 2019/11/04 ^^^
else
-- avalon-to-abus mapping
-- SDRAM is mapped to both CS0 and CS1
--
-- Note about address : from NIOS side, SDRAM is mapped to 0x0800_0000,
-- | so that the prefix at upper bits of the address passed to avalon.
-- | And A-Bus data width is 16 bits so that lower address bit is zeroed.
--
-- Additionally, extra OCRAM is mapped to 0x0C00_0000 from NIOS side,
-- and is (temporarily) available from A-Bus' second half of CS0.
--avalon_address <= "010" & demux_writeaddress(23 downto 0) & "0"; -- SDRAM available from A-Bus (old mapping, just here for reference)
avalon_writedata <= demux_writedata(7 downto 0) & demux_writedata(15 downto 8);
avalon_byteenable(0) <= demux_write_byteenable(0);
avalon_byteenable(1) <= demux_write_byteenable(1);
avalon_burstcount <= '1';
avalon_write <= '1';
my_transaction_type <= TYPE_AVALON;
avalon_address <= "1" & demux_writeaddress(23) & "00" & demux_writeaddress(22 downto 0) & "0"; -- SDRAM and OCRAM available from A-Bus
end if;
end if;
end if;
end process;
---------------------------------------------------------------------------------------
--Nios II read interface
process (clock)
begin
if rising_edge(clock) then
if avalon_nios_read = '1' then
avalon_nios_readdatavalid <= '1';
case avalon_nios_address is
-- Debug stuff around Rd/Wr access
when X"00" =>
avalon_nios_readdata <= x"0" & last_rd_addr;
when X"02" =>
avalon_nios_readdata <= x"0" & last_rd_addr1;
when X"03" =>
avalon_nios_readdata <= x"0" & last_rd_addr2;
when X"04" =>
avalon_nios_readdata <= x"0" & last_rd_addr3;
when X"05" =>
avalon_nios_readdata <= x"0" & last_rd_addr4;
when X"08" =>
avalon_nios_readdata <= x"0000CA" & rd_access_cntr;
when X"09" =>
avalon_nios_readdata <= x"0000FE" & wr_access_cntr;
when X"10" =>
avalon_nios_readdata <= x"0" & last_wr_addr;
when X"11" =>
avalon_nios_readdata <= x"0000" & last_wr_data;
--when X"F0" =>
-- avalon_nios_readdata <= REG_PCNTR;
--when X"F2" =>
-- avalon_nios_readdata <= REG_STATUS;
--when X"F4" =>
-- avalon_nios_readdata <= REG_MODE;
--when X"F6" =>
-- avalon_nios_readdata <= REG_HWVER;
--when X"F8" =>
-- avalon_nios_readdata <= REG_SWVER;
when others =>
avalon_nios_readdata <= X"00000000";
end case;
else
avalon_nios_readdatavalid <= '0';
end if;
end if;
end process;
---------------------------------------------------------------------------------------
--Nios II write interface
process (clock)
begin
if rising_edge(clock) then
if avalon_nios_write= '1' then
case avalon_nios_address is
--when X"F0" =>
-- REG_PCNTR <= avalon_nios_writedata(15 downto 0);
--when X"F2" =>
-- REG_STATUS <= avalon_nios_writedata(15 downto 0);
--when X"F4" =>
-- null;
--when X"F6" =>
-- null;
--when X"F8" =>
-- REG_SWVER <= avalon_nios_writedata(15 downto 0);
when others =>
null;
end case;
end if;
end if;
end process;
--Nios system interface is only regs, so always ready to write.
avalon_nios_waitrequest <= '0';
end architecture rtl; -- of abus_slave
| gpl-2.0 | e8ad6da3a62e3132c728c9b7de4af744 | 0.460571 | 4.458338 | false | false | false | false |
impedimentToProgress/UCI-BlueChip | AttackFiles/Attacks/privEsc/lib/esa/pci/pci_arb.vhd | 2 | 18,123 |
----------------------------------------------------------------------------
-- This file is a part of the LEON VHDL model
-- Copyright (C) 1999 European Space Agency (ESA)
--
-- This library is free software; you can redistribute it and/or
-- modify it under the terms of the GNU Lesser General Public
-- License as published by the Free Software Foundation; either
-- version 2 of the License, or (at your option) any later version.
--
-- See the file COPYING.LGPL for the full details of the license.
--============================================================================--
-- Design unit : pci_arb
--
-- File name : pci_arb.vhd
--
-- Purpose : Arbiter for the PCI bus
-- - configurable size: 4, 8, 16, 32 agents
-- - nested round-robbing in two different priority levels
-- - priority assignment hard-coded or APB-programmable
--
-- Reference : PCI Local Bus Specification, Revision 2.1,
-- PCI Special Interest Group, 1st June 1995
-- (for information: http:
-- Reference : AMBA(TM) Specification (Rev 2.0), ARM IHI 0011A,
-- 13th May 1999, issue A, first release, ARM Limited
-- The document can be retrieved from http:
--
-- Note : Numbering for req_n, gnt_n, or priority levels is in
-- increasing order <0 = left> to <NUMBER-1 = right>.
-- APB data/address arrays are in the conventional order:
-- The least significant bit is located to the
-- right, carrying the lower index number (usually 0).
-- The arbiter considers strong signal levels ('1' and '0')
-- only. Weak levels ('H', 'L') are not considered. The
-- appropriate translation function (to_X01) must be applied
-- to the inputs. This is usually done by the pads,
-- and therefore not contained in this model.
--
-- Configuration: The arbiter can be configured to NB_AGENTS = 4, 8, 16 or 32.
-- A priority level (0 = high, 1 = low) is assigned to each device.
-- Exception is agent NB_AGENTS-1, which has always lowest priority.
--
-- a) The priority levels are hard-coded, when APB_PRIOS = false.
-- In this case, the APB ports (pbi/pbo) are unconnected.
-- The constant ARB_LVL_C must then be set to appropriate values.
--
-- b) When APB_PRIOS = true, the levels are programmable via the
-- APB-address 0x80 (allows to be ored with the PCI interface):
-- Bit 31 (leftmost) = master 31 . . bit 0 (rightmost) = master 0.
-- Bit NB_AGENTS-1 is dont care at write and reads 1.
-- Bits NB_AGENTS to 31, if existing, are dont care and read 0.
-- The constant ARB_LVL_C is then the reset value.
--
-- Algorithm : The algorithm is described in the implementation note of
-- section 3.4 of the PCI standard:
-- The bus is granted by two nested round-robbing loops.
-- An agent number and a priority level is assigned to each agent.
-- The agent number determines, the pair of req_n/gnt_n lines.
-- Agents are counted from 0 to NB_AGENTS-1.
-- All agents in one level have equal access to the bus
-- (round-robbing); all agents of level 1 as a group have access
-- equal to each agent of level 0.
-- Re-arbitration occurs, when frame_n is asserted, as soon
-- as any other master has requested the bus, but only
-- once per transaction.
--
-- b) With programmable priorities. The priority level of all
-- agents (except NB_AGENTS-1) is programmable via APB.
-- In a 256 byte APB address range, the priority level of
-- agent N is accessed via the address 0x80 + 4*N. The APB
-- slave returns 0 on all non-implemented addresses, the
-- address bits (1:0) are not decoded. Since only addresses
-- >= 0x80 are occupied, it can be used in parallel (ored
-- read data) with our PCI interface (uses <= 0x78).
-- The constant ARB_LVL_C in pci_arb_pkg is the reset value.
--
-- Timeout: The "broken master" timeout is another reason for
-- re-arbitration (section 3.4.1 of the standard). Grant is
-- removed from an agent, which has not started a cycle
-- within 16 cycles after request (and grant). Reporting of
-- such a 'broken' master is not implemented.
--
-- Turnover: A turnover cycle is required by the standard, when re-
-- arbitration occurs during idle state of the bus.
-- Notwithstanding to the standard, "idle state" is assumed,
-- when frame_n is high for more than 1 cycle.
--
-- Bus parking : The bus is parked to agent 0 after reset, it remains granted
-- to the last owner, if no other agent requests the bus.
-- When another request is asserted, re-arbitration occurs
-- after one turnover cycle.
--
-- Lock : Lock is defined as a resource lock by the PCI standard.
-- The optional bus lock mentioned in the standard is not
-- considered here and there are no special conditions to
-- handle when lock_n is active.
-- in arbitration.
--
-- Latency : Latency control in PCI is via the latency counters of each
-- agent. The arbiter does not perform any latency check and
-- a once granted agent continues its transaction until its
-- grant is removed AND its own latency counter has expired.
-- Even though, a bus re-arbitration occurs during a
-- transaction, the hand-over only becomes effective,
-- when the current owner deasserts frame_n.
--
-- Limitations : [add here known bugs and limitations]
--
-- Library : work
--
-- Dependencies : LEON config package
-- package amba, can be retrieved from:
-- http:
--
-- Author : Roland Weigand <[email protected]>
-- European Space Agency (ESA)
-- Microelectronics Section (TOS-ESM)
-- P.O. Box 299
-- NL-2200 AG Noordwijk ZH
-- The Netherlands
--
-- Contact : mailto:[email protected]
-- http:
-- Copyright (C): European Space Agency (ESA) 2002.
-- This source code is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
-- Public License as published by the Free Software Foundation;
-- either version 2 of the License, or (at your option) any
-- later version. For full details of the license see file
-- http:
--
-- It is recommended that any use of this VHDL source code is
-- reported to the European Space Agency. It is also recommended
-- that any use of the VHDL source code properly acknowledges the
-- European Space Agency as originator.
-- Disclaimer : All information is provided "as is", there is no warranty that
-- the information is correct or suitable for any purpose,
-- neither implicit nor explicit. This information does not
-- necessarily reflect the policy of the European Space Agency.
--
-- Simulator : Modelsim 5.5e on Linux RedHat 7.2
--
-- Synthesis : Synopsys Version 1999.10 on Sparc + Solaris 5.5.1
--
--------------------------------------------------------------------------------
-- Version Author Date Changes
--
-- 0.0 R. W. 2000/11/02 File created
-- 0.1 J.Gaisler 2001/04/10 Integrated in LEON
-- 0.2 R. Weigand 2001/04/25 Connect arb_lvl reg to AMBA clock/reset
-- 0.3 R. Weigand 2002/03/19 Default assignment to owneri in find_next
-- 1.0 RW. 2002/04/08 Implementation of TMR registers
-- Removed recursive function call
-- Fixed ARB_LEVELS = 2
-- 3.0 R. Weigand 2002/04/16 Released for leon2
-- 4.0 M. Isomaki 2004/10/19 Minor changes for GRLIB integration
-- 4.1 J.Gaisler 2004/11/17 Minor changes for GRLIB integration
--$Log$
-- Revision 3.1 2002/07/31 13:22:09 weigand
-- Bugfix for cases where no valid request in level 0 (level 1 was not rearbitrated)
--
-- Revision 3.0 2002/07/24 12:19:38 weigand
-- Installed RCS with version 3.0
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.stdlib.all;
library esa;
use esa.pci_arb_pkg.all;
entity pci_arb is
generic(NB_AGENTS : integer := 4;
ARB_SIZE : integer := 2;
APB_EN : integer := 1
);
port (clk : in clk_type; -- clock
rst_n : in std_logic; -- async reset active low
req_n : in std_logic_vector(0 to NB_AGENTS-1); -- bus request
frame_n : in std_logic;
gnt_n : out std_logic_vector(0 to NB_AGENTS-1); -- bus grant
pclk : in clk_type; -- APB clock
prst_n : in std_logic; -- APB reset
pbi : in EAPB_Slv_In_Type; -- APB inputs
pbo : out EAPB_Slv_Out_Type -- APB outputs
);
end pci_arb;
architecture rtl of pci_arb is
subtype agent_t is std_logic_vector(ARB_SIZE-1 downto 0);
subtype arb_lvl_t is std_logic_vector(NB_AGENTS-1 downto 0);
subtype agentno_t is integer range 0 to NB_AGENTS-1;
-- Note: the agent with the highest index (3, 7, 15, 31) is always in level 1
-- Example: x010 = prio 0 for agent 2 and 0, prio 1 for agent 3 and 1.
-- Default: start with all devices equal priority at level 1.
constant ARB_LVL_C : arb_lvl_t := (others => '1');
constant all_ones : std_logic_vector(0 to NB_AGENTS-1) := (others => '1');
--Necessary definitions from amba.vhd and iface.vhd
--added to pci_arb package with modified names to avoid
--name clashes in GRLIB
constant APB_PRIOS : boolean := APB_EN = 1;
signal owner0, owneri0 : agent_t; -- current owner in level 0
signal owner1, owneri1 : agent_t; -- current owner in level 1
signal cown, cowni : agent_t; -- current level
signal rearb, rearbi : std_logic; -- re-arbitration flag
signal tout, touti : std_logic_vector(3 downto 0); -- timeout counter
signal turn, turni : std_logic; -- turnaround cycle
signal arb_lvl, arb_lvli : arb_lvl_t := ARB_LVL_C; -- level registers
type nmstarr is array (0 to 3) of agentno_t;
type nvalarr is array (0 to 3) of boolean;
begin -- rtl
----------------------------------------------------------------------------
-- PCI ARBITER
----------------------------------------------------------------------------
-- purpose: Grants the bus depending on the request signals. All agents have
-- equal priority, if another request occurs during a transaction, the bus is
-- granted to the new agent. However, PCI protocol specifies that the master
-- can finish the current transaction within the limit of its latency timer.
arbiter : process(cown, owner0, owner1, req_n, rearb, tout, turn, frame_n,
arb_lvl, rst_n)
variable owner0v, owner1v : agentno_t; -- integer variables for current owner
variable new_request : agentno_t; -- detected request
variable nmst : nmstarr;
variable nvalid : nvalarr;
begin -- process arbiter
-- default assignments
rearbi <= rearb;
owneri0 <= owner0;
owneri1 <= owner1;
cowni <= cown;
touti <= tout;
turni <= '0'; -- no turnaround
-- re-arbitrate once during the transaction,
-- or when timeout counter expired (bus idle).
if (frame_n = '0' and rearb = '0') or turn = '1' then
owner0v := conv_integer(owner0);
owner1v := conv_integer(owner1);
new_request := conv_integer(cown);
nvalid(0 to 3) := (others => false);
nmst(0 to 3) := (others => 0);
-- Determine next request in both priority levels
rob : for i in NB_AGENTS-1 downto 0 loop
-- consider all masters with valid request
if req_n(i) = '0' then
-- next in prio level 0
if arb_lvl(i) = '0' then
if i > owner0v then
nmst(0) := i; nvalid(0) := true;
elsif i < owner0v then
nmst(1) := i; nvalid(1) := true;
end if;
-- next in prio level 1
elsif arb_lvl(i) = '1' then
if i > owner1v then
nmst(2) := i; nvalid(2) := true;
elsif i < owner1v then
nmst(3) := i; nvalid(3) := true;
end if;
end if; -- arb_lvl
end if; -- req_n
end loop rob;
-- select new master
if nvalid(0) then -- consider level 0 before wrap
new_request := nmst(0);
owner0v := nmst(0);
-- consider level 1 only once, except when no request in level 0
elsif owner0v /= NB_AGENTS-1 or not nvalid(1) then
if nvalid(2) then -- level 1 before wrap
new_request := nmst(2);
owner0v := NB_AGENTS-1;
owner1v := nmst(2);
elsif nvalid(3) then -- level 1 after wrap
new_request := nmst(3);
owner0v := NB_AGENTS-1;
owner1v := nmst(3);
end if;
elsif nvalid(1) then -- level 0 after wrap
new_request := nmst(1);
owner0v := nmst(1);
end if;
owneri0 <= conv_std_logic_vector(owner0v, ARB_SIZE);
owneri1 <= conv_std_logic_vector(owner1v, ARB_SIZE);
-- rearbitration if any request asserted & different from current owner
if conv_integer(cown) /= new_request then
-- if idle state: turnaround cycle required by PCI standard
cowni <= conv_std_logic_vector(new_request, ARB_SIZE);
touti <= "0000"; -- reset timeout counter
if turn = '0' then
rearbi <= '1'; -- only one re-arbitration
end if;
end if;
elsif frame_n = '1' then
rearbi <= '0';
end if;
-- if frame deasserted, but request asserted: count timeout
if req_n = all_ones then -- no request: prepare timeout counter
touti <= "1111";
elsif frame_n = '1' then -- request, but no transaction
if tout = "1111" then -- timeout expired, re-arbitrate
turni <= '1'; -- remove grant, turnaround cycle
touti <= "0000"; -- next cycle re-arbitrate
else
touti <= tout + 1;
end if;
end if;
grant : for i in 0 to NB_AGENTS-1 loop
if i = conv_integer(cown) and turn = '0' then
gnt_n(i) <= '0';
else
gnt_n(i) <= '1';
end if;
end loop grant;
-- synchronous reset
if rst_n = '0' then
touti <= "0000";
cowni <= (others => '0');
owneri0 <= (others => '0');
owneri1 <= (others => '0');
rearbi <= '0';
turni <= '0';
new_request := 0;
end if;
end process arbiter;
arb_lvl(NB_AGENTS-1) <= '1'; -- always prio 1.
fixed_prios : if not APB_PRIOS generate -- assign constant value
arb_lvl(NB_AGENTS-2 downto 0) <= ARB_LVL_C(NB_AGENTS-2 downto 0);
end generate fixed_prios;
-- Generate APB regs and APB slave
apbgen : if APB_PRIOS generate
-- purpose: APB read and write of arb_lvl configuration registers
-- type: memoryless
-- inputs: pbi, arb_lvl, prst_n
-- outputs: pbo, arb_lvli
config : process (pbi, arb_lvl, prst_n)
begin -- process config
arb_lvli <= arb_lvl;
pbo.PRDATA <= (others => '0'); -- default for unimplemented addresses
-- register select at (byte-) addresses 0x80
if pbi.PADDR(7 downto 0) = "10000000" and pbi.PSEL = '1' then -- address select
if (pbi.PWRITE and pbi.PENABLE) = '1' then -- APB write
arb_lvli <= pbi.PWDATA(NB_AGENTS-1 downto 0);
end if;
pbo.PRDATA(NB_AGENTS-1 downto 0) <= arb_lvl;
end if;
-- synchronous reset
if prst_n = '0' then
arb_lvli <= ARB_LVL_C; -- assign default value
end if;
end process config;
-- APB registers
apb_regs : process (pclk)
begin -- process regs
-- activities triggered by asynchronous reset (active low)
if pclk'event and pclk = '1' then -- '
arb_lvl(NB_AGENTS-2 downto 0) <= arb_lvli(NB_AGENTS-2 downto 0);
end if;
end process apb_regs;
end generate apbgen;
-- PCI registers
regs0 : process (clk)
begin -- process regs
if clk'event and clk = '1' then -- '
tout <= touti;
owner0 <= owneri0;
owner1 <= owneri1;
cown <= cowni;
rearb <= rearbi;
turn <= turni;
end if;
end process regs0;
end rtl;
| mit | 7c0c26a5f132f7aa423167358855312d | 0.540308 | 4.186417 | false | false | false | false |
impedimentToProgress/UCI-BlueChip | AttackFiles/Attacks/privEsc/lib/grlib/util/util.vhd | 2 | 1,711 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Package: util
-- File: util.vhd
-- Author: Jiri Gaisler, Gaisler Research
-- Description: Misc utilities
------------------------------------------------------------------------------
-- pragma translate_off
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.stdlib.all;
entity report_version is
generic (msg1, msg2, msg3, msg4 : string := ""; mdel : integer := 4);
end;
architecture beh of report_version is
begin
x : process
begin
wait for mdel * 1 ns;
if (msg1 /= "") then print(msg1); end if;
if (msg2 /= "") then print(msg2); end if;
if (msg3 /= "") then print(msg3); end if;
if (msg4 /= "") then print(msg4); end if;
wait;
end process;
end;
-- pragma translate_on
| mit | a2ad169ccda7b5ee9c2b3cbe424abaec | 0.597312 | 4.112981 | false | false | false | false |
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