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impedimentToProgress/UCI-BlueChip | AttackFiles/Attacks/privEsc/lib/tech/axcelerator/components/axcelerator_components.vhd | 2 | 12,022 | ----------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2004 GAISLER RESEARCH
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- See the file COPYING for the full details of the license.
--
-----------------------------------------------------------------------------
-- Package: components
-- File: components.vhd
-- Author: Jiri Gaisler, Gaisler Research
-- Description: Simple Actel RAM and pad component declarations
-----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
package components is
-- Axcellerator rams
component RAM64K36
port(
WRAD0, WRAD1, WRAD2, WRAD3, WRAD4, WRAD5, WRAD6, WRAD7, WRAD8, WRAD9, WRAD10,
WRAD11, WRAD12, WRAD13, WRAD14, WRAD15, WD0, WD1, WD2, WD3, WD4, WD5, WD6,
WD7, WD8, WD9, WD10, WD11, WD12, WD13, WD14, WD15, WD16, WD17, WD18, WD19,
WD20, WD21, WD22, WD23, WD24, WD25, WD26, WD27, WD28, WD29, WD30, WD31, WD32,
WD33, WD34, WD35, WEN, DEPTH0, DEPTH1, DEPTH2, DEPTH3, WW0, WW1, WW2, WCLK,
RDAD0, RDAD1, RDAD2, RDAD3, RDAD4, RDAD5, RDAD6, RDAD7, RDAD8, RDAD9, RDAD10,
RDAD11, RDAD12, RDAD13, RDAD14, RDAD15, REN, RW0, RW1, RW2, RCLK : in std_logic;
RD0, RD1, RD2, RD3, RD4, RD5, RD6, RD7, RD8, RD9, RD10, RD11, RD12, RD13,
RD14, RD15, RD16, RD17, RD18, RD19, RD20, RD21, RD22, RD23, RD24, RD25, RD26,
RD27, RD28, RD29, RD30, RD31, RD32, RD33, RD34, RD35 : out std_logic);
end component;
attribute syn_black_box : boolean;
attribute syn_black_box of RAM64K36 : component is true;
attribute syn_tco1 : string;
attribute syn_tco2 : string;
attribute syn_tco1 of RAM64K36 : component is
"RCLK->RD0,RD1,RD2,RD3,RD4,RD5,RD6,RD7,RD8,RD9,RD10,RD11,RD12,RD13,RD14,RD15,RD16,RD17,RD18,RD19,RD20,RD21,RD22,RD23,RD24,RD25,RD26,RD27,RD28,RD29,RD30,RD31,RD32,RD33,RD34,RD35 = 4.0";
-- Buffers
component inbuf_lvds port(Y : out std_logic; PADP : in std_logic; PADN : in std_logic); end component;
component outbuf_lvds port(D : in std_logic; PADP : out std_logic; PADN : out std_logic); end component;
component hclkbuf
port( pad : in std_logic; y : out std_logic); end component;
component clkbuf port(pad : in std_logic; y : out std_logic); end component;
component inbuf port(pad :in std_logic; y : out std_logic); end component;
component bibuf port(
d, e : in std_logic; pad : inout std_logic; y : out std_logic);
end component;
component outbuf port(d : in std_logic; pad : out std_logic); end component;
component outbuf_f_8 port(d : in std_logic; pad : out std_logic); end component;
component outbuf_f_12 port(d : in std_logic; pad : out std_logic); end component;
component outbuf_f_16 port(d : in std_logic; pad : out std_logic); end component;
component outbuf_f_24 port(d : in std_logic; pad : out std_logic); end component;
component tribuff port(d, e : in std_logic; pad : out std_logic); end component;
component hclkint port(a : in std_ulogic; y : out std_ulogic); end component;
component clkint port(a : in std_ulogic; y : out std_ulogic); end component;
component hclkbuf_pci
port( pad : in std_logic; y : out std_logic); end component;
component clkbuf_pci port(pad : in std_logic; y : out std_logic); end component;
component inbuf_pci port(pad :in std_logic; y : out std_logic); end component;
attribute syn_tpd11 : string;
attribute syn_tpd11 of inbuf_pci : component is "pad -> y = 2.0";
component bibuf_pci port(
d, e : in std_logic; pad : inout std_logic; y : out std_logic);
end component;
attribute syn_tpd12 : string;
attribute syn_tpd12 of bibuf_pci : component is "pad -> y = 2.0";
component outbuf_pci port(d : in std_logic; pad : out std_logic); end component;
attribute syn_tpd13 : string;
attribute syn_tpd13 of outbuf_pci : component is "d -> pad = 2.0";
component tribuff_pci port(d, e : in std_logic; pad : out std_logic); end component;
attribute syn_tpd14 : string;
attribute syn_tpd14 of tribuff_pci : component is "d,e -> pad = 2.0";
-- 1553 -------------------------------
component add1 is
port(
a : in std_logic;
b : in std_logic;
fci : in std_logic;
s : out std_logic;
fco : out std_logic);
end component add1;
component and2 is
port(
a : in std_logic;
b : in std_logic;
y : out std_logic);
end component and2;
component and2a is
port(
a : in std_logic;
b : in std_logic;
y : out std_logic);
end component and2a;
component and2b is
port(
a : in std_logic;
b : in std_logic;
y : out std_logic);
end component and2b;
component and3 is
port(
a : in std_logic;
b : in std_logic;
c : in std_logic;
y : out std_logic);
end component and3;
component and3a is
port(
a : in std_logic;
b : in std_logic;
c : in std_logic;
y : out std_logic);
end component and3a;
component and3b is
port(
a : in std_logic;
b : in std_logic;
c : in std_logic;
y : out std_logic);
end component and3b;
component and3c is
port(
a : in std_logic;
b : in std_logic;
c : in std_logic;
y : out std_logic);
end component and3c;
component and4 is
port(
a : in std_logic;
b : in std_logic;
c : in std_logic;
d : in std_logic;
y : out std_logic);
end component and4;
component and4a is
port(
a : in std_logic;
b : in std_logic;
c : in std_logic;
d : in std_logic;
y : out std_logic);
end component and4a;
component and4b is
port(
a : in std_logic;
b : in std_logic;
c : in std_logic;
d : in std_logic;
y : out std_logic);
end component and4b;
component and4c is
port(
a : in std_logic;
b : in std_logic;
c : in std_logic;
d : in std_logic;
y : out std_logic);
end component and4c;
component buff is
port(
a : in std_logic;
y : out std_logic);
end component buff;
component cm8 is
port(
d0 : in std_logic;
d1 : in std_logic;
d2 : in std_logic;
d3 : in std_logic;
s00 : in std_logic;
s01 : in std_logic;
s10 : in std_logic;
s11 : in std_logic;
y : out std_logic);
end component cm8;
component cm8inv is
port(
a : in std_logic;
y : out std_logic);
end component cm8inv;
component df1 is
port(
d : in std_logic;
clk : in std_logic;
q : out std_logic);
end component df1;
component dfc1b is
port(
d : in std_logic;
clk : in std_logic;
clr : in std_logic;
q : out std_logic);
end component dfc1b;
component dfc1c is
port(
d : in std_logic;
clk : in std_logic;
clr : in std_logic;
q : out std_logic);
end component dfc1c;
component dfc1d is
port(
d : in std_logic;
clk : in std_logic;
clr : in std_logic;
q : out std_logic);
end component dfc1d;
component dfe1b is
port(
d : in std_logic;
e : in std_logic;
clk : in std_logic;
q : out std_logic);
end component dfe1b;
component dfe3c is
port(
d : in std_logic;
e : in std_logic;
clk : in std_logic;
clr : in std_logic;
q : out std_logic);
end component dfe3c;
component dfe4f is
port(
d : in std_logic;
e : in std_logic;
clk : in std_logic;
pre : in std_logic;
q : out std_logic);
end component dfe4f;
component dfp1 is
port(
d : in std_logic;
clk : in std_logic;
pre : in std_logic;
q : out std_logic);
end component dfp1;
component dfp1b is
port(
d : in std_logic;
clk : in std_logic;
pre : in std_logic;
q : out std_logic);
end component dfp1b;
component dfp1d is
port(
d : in std_logic;
clk : in std_logic;
pre : in std_logic;
q : out std_logic);
end component dfp1d;
component dfm
port(
clk : in std_logic;
s : in std_logic;
a : in std_logic;
b : in std_logic;
q : out std_logic);
end component;
component gnd is
port(
y : out std_logic);
end component gnd;
component inv is
port(
a : in std_logic;
y : out std_logic);
end component inv;
component nand4 is
port(
a : in std_logic;
b : in std_logic;
c : in std_logic;
d : in std_logic;
y : out std_logic);
end component nand4;
component or2 is
port(
a : in std_logic;
b : in std_logic;
y : out std_logic);
end component or2;
component or2a is
port(
a : in std_logic;
b : in std_logic;
y : out std_logic);
end component or2a;
component or2b is
port(
a : in std_logic;
b : in std_logic;
y : out std_logic);
end component or2b;
component or3 is
port(
a : in std_logic;
b : in std_logic;
c : in std_logic;
y : out std_logic);
end component or3;
component or3a is
port(
a : in std_logic;
b : in std_logic;
c : in std_logic;
y : out std_logic);
end component or3a;
component or3b is
port(
a : in std_logic;
b : in std_logic;
c : in std_logic;
y : out std_logic);
end component or3b;
component or3c is
port(
a : in std_logic;
b : in std_logic;
c : in std_logic;
y : out std_logic);
end component or3c;
component or4 is
port(
a : in std_logic;
b : in std_logic;
c : in std_logic;
d : in std_logic;
y : out std_logic);
end component or4;
component or4a is
port(
a : in std_logic;
b : in std_logic;
c : in std_logic;
d : in std_logic;
y : out std_logic);
end component or4a;
component or4b is
port(
a : in std_logic;
b : in std_logic;
c : in std_logic;
d : in std_logic;
y : out std_logic);
end component or4b;
component or4c is
port(
a : in std_logic;
b : in std_logic;
c : in std_logic;
d : in std_logic;
y : out std_logic);
end component or4c;
component or4d is
port(
a : in std_logic;
b : in std_logic;
c : in std_logic;
d : in std_logic;
y : out std_logic);
end component or4d;
component sub1 is
port(
a : in std_logic;
b : in std_logic;
fci : in std_logic;
s : out std_logic;
fco : out std_logic);
end component sub1;
component vcc is
port(
y : out std_logic);
end component vcc;
component xa1 is
port(
a : in std_logic;
b : in std_logic;
c : in std_logic;
y : out std_logic);
end component xa1;
component xnor2 is
port(
a : in std_logic;
b : in std_logic;
y : out std_logic);
end component xnor2;
component xor2 is
port(
a : in std_logic;
b : in std_logic;
y : out std_logic);
end component xor2;
component xor4 is
port(a,b,c,d : in std_logic;
y : out std_logic);
end component xor4;
component mx2
port(
a : in std_logic;
s : in std_logic;
b : in std_logic;
y : out std_logic);
end component;
component ax1c
port(
a: in std_logic;
b: in std_logic;
c: in std_logic;
y: out std_logic);
end component;
component df1b
port(
d : in std_logic;
clk : in std_logic;
q : out std_logic);
end component;
end;
| mit | ca4144fbb4b3cd06d6fa96709d795734 | 0.570371 | 3.170359 | false | false | false | false |
amerc/phimii | source/OneHz25MHz.vhd | 2 | 1,306 | --This is a clock divider code, just set the max-count value as per your requirenment.
--
--For ex. If I want 1Hz freq. set the max count to i/p freq value viz.
--1sec = 1Hz
--Then, to get time period of 1sec i.e. 1 Hz frequency set max-count to 240000 as shown below:
--
--1sec = 100000000 -- for i/p frequency of 100 MHz.
--
--To get your desired frequency just calculate the maxcount with the formula given below:
--
--max_count = 100000000 * (1/your required frequency)
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.all;
entity OneHz25MHz is
Port (
Clk : in std_logic;
op : out std_logic
);
end OneHz25MHz;
architecture RTC of OneHz25MHz is
constant max_count : natural := 25000000; -- for 1 mHz
-- I used 50 MHz clock
begin
compteur : process(Clk)
variable count : natural range 0 to max_count;
begin
if rising_edge(Clk) then
if count < max_count/2 then
op <='1';
count := count + 1;
elsif count < max_count then
op <='0';
count := count + 1;
else
count := 0;
op <='0';
end if;
end if;
end process compteur;
end RTC; | mit | 37657cf0d20be6f088a4ab7db7dba276 | 0.563553 | 3.796512 | false | false | false | false |
michaelfivez/ascon_hardware_implementation | ascon12864_iterated/Kernel/DiffusionLayer.vhd | 1 | 1,684 | -------------------------------------------------------------------------------
--! @project Iterated hardware implementation of Asconv12864
--! @author Michael Fivez
--! @license This project is released under the GNU Public License.
--! The license and distribution terms for this file may be
--! found in the file LICENSE in this distribution or at
--! http://www.gnu.org/licenses/gpl-3.0.txt
--! @note This is an hardware implementation made for my graduation thesis
--! at the KULeuven, in the COSIC department (year 2015-2016)
--! The thesis is titled 'Energy efficient hardware implementations of CAESAR submissions',
--! and can be found on the COSIC website (www.esat.kuleuven.be/cosic/publications)
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity DiffusionLayer is
generic( SHIFT1 : integer range 0 to 63;
SHIFT2 : integer range 0 to 63);
port( Input : in std_logic_vector(63 downto 0);
Output : out std_logic_vector(63 downto 0));
end entity DiffusionLayer;
architecture structural of DiffusionLayer is
begin
DiffLayer: process(Input) is
variable Temp0,Temp1 : std_logic_vector(63 downto 0);
begin
Temp0(63 downto 64-SHIFT1) := Input(SHIFT1-1 downto 0);
Temp0(63-SHIFT1 downto 0) := Input(63 downto SHIFT1);
Temp1(63 downto 64-SHIFT2) := Input(SHIFT2-1 downto 0);
Temp1(63-SHIFT2 downto 0) := Input(63 downto SHIFT2);
Output <= Temp0 xor Temp1 xor Input;
end process DiffLayer;
end architecture structural;
| gpl-3.0 | 4ad85b635b74ac664224688e1660a2e6 | 0.617577 | 3.767338 | false | false | false | false |
lxp32/lxp32-cpu | rtl/lxp32_scratchpad.vhd | 2 | 1,939 | ---------------------------------------------------------------------
-- Scratchpad
--
-- Part of the LXP32 CPU
--
-- Copyright (c) 2016 by Alex I. Kuznetsov
--
-- LXP32 register file implemented as a RAM block. Since we need
-- to read two registers simultaneously, the memory is duplicated.
---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity lxp32_scratchpad is
port(
clk_i: in std_logic;
raddr1_i: in std_logic_vector(7 downto 0);
rdata1_o: out std_logic_vector(31 downto 0);
raddr2_i: in std_logic_vector(7 downto 0);
rdata2_o: out std_logic_vector(31 downto 0);
waddr_i: in std_logic_vector(7 downto 0);
we_i: in std_logic;
wdata_i: in std_logic_vector(31 downto 0)
);
end entity;
architecture rtl of lxp32_scratchpad is
signal wdata_reg: std_logic_vector(wdata_i'range);
signal ram1_rdata: std_logic_vector(31 downto 0);
signal ram2_rdata: std_logic_vector(31 downto 0);
signal ram1_collision: std_logic;
signal ram2_collision: std_logic;
begin
-- RAM 1
ram_inst1: entity work.lxp32_ram256x32(rtl)
port map(
clk_i=>clk_i,
we_i=>we_i,
waddr_i=>waddr_i,
wdata_i=>wdata_i,
re_i=>'1',
raddr_i=>raddr1_i,
rdata_o=>ram1_rdata
);
-- RAM 2
ram_inst2: entity work.lxp32_ram256x32(rtl)
port map(
clk_i=>clk_i,
we_i=>we_i,
waddr_i=>waddr_i,
wdata_i=>wdata_i,
re_i=>'1',
raddr_i=>raddr2_i,
rdata_o=>ram2_rdata
);
-- Read/write collision detection
process (clk_i) is
begin
if rising_edge(clk_i) then
wdata_reg<=wdata_i;
if waddr_i=raddr1_i and we_i='1' then
ram1_collision<='1';
else
ram1_collision<='0';
end if;
if waddr_i=raddr2_i and we_i='1' then
ram2_collision<='1';
else
ram2_collision<='0';
end if;
end if;
end process;
rdata1_o<=ram1_rdata when ram1_collision='0' else wdata_reg;
rdata2_o<=ram2_rdata when ram2_collision='0' else wdata_reg;
end architecture;
| mit | 31d6c6d5025b26ac5c5ed54c59f6aa89 | 0.625064 | 2.696801 | false | false | false | false |
impedimentToProgress/UCI-BlueChip | AttackFiles/Attacks/privEsc/lib/gleichmann/ahb2hpi/ahb2hpi.vhd | 2 | 14,317 | -------------------------------------------------------------------------------
-- Title : AHB2HPI bus bridge
-- Project : LEON3MINI
-------------------------------------------------------------------------------
-- $Id: ahb2hpi.vhd,v 1.23 2005/09/28 14:50:25 tame Mod $
-------------------------------------------------------------------------------
-- Author : Thomas Ameseder
-- Company : Gleichmann Electronics
-- Created : 2005-08-19
-- Standard : VHDL'87
-------------------------------------------------------------------------------
-- Description:
--
-- This module implements an AHB slave that communicates with a
-- Host Peripheral Interface (HPI) device such as the CY7C67300 USB controller.
-- Supports Big Endian and Little Endian.
--
-- Restrictions: Do not use a data width other than 16 at the moment.
-------------------------------------------------------------------------------
-- Copyright (c) 2005
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
--use ieee.std_logic_unsigned.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
entity ahb2hpi is
generic (
counter_width : integer := 4;
data_width : integer := 16;
address_width : integer := 2;
hindex : integer := 0;
haddr : integer := 0;
hmask : integer := 16#fff#
);
port (
-- AHB port
HCLK : in std_ulogic;
HRESETn : in std_ulogic;
ahbso : out ahb_slv_out_type;
ahbsi : in ahb_slv_in_type;
-- HPI port
ADDR : out std_logic_vector(address_width-1 downto 0);
DATA : inout std_logic_vector(data_width-1 downto 0);
nCS : out std_ulogic;
nWR : out std_ulogic;
nRD : out std_ulogic;
INT : in std_ulogic;
-- debug port
dbg_equal : out std_ulogic
);
end ahb2hpi;
architecture rtl of ahb2hpi is
constant CONFIGURATION_VERSION : integer := 0;
constant VERSION : integer := 0;
constant INTERRUPT_NUMBER : integer := 5;
-- register file address is the base address plus the
-- ahb memory space reserved for the device itself
-- its size is 64 bytes as defined with 16#fff# for its
-- mask below
constant REGFILE_ADDRESS : integer := 16#340#;
-- big endian/little endian architecture selection
constant BIG_ENDIAN : boolean := true;
constant hconfig : ahb_config_type := (
0 => ahb_device_reg
(VENDOR_GLEICHMANN, GLEICHMANN_HPI,
CONFIGURATION_VERSION, VERSION, INTERRUPT_NUMBER),
4 => ahb_iobar(haddr, hmask),
5 => ahb_iobar(REGFILE_ADDRESS, 16#fff#),
others => (others => '0'));
type reg_type is
record
hwrite : std_ulogic;
hready : std_ulogic;
hsel : std_ulogic;
addr : std_logic_vector(address_width-1 downto 0);
counter : unsigned(counter_width-1 downto 0);
Din : std_logic_vector(data_width-1 downto 0);
Dout : std_logic_vector(data_width-1 downto 0);
nWR, nRD, nCS : std_ulogic;
INT : std_ulogic;
ctrlreg : std_logic_vector(data_width-1 downto 0);
data_acquisition : std_ulogic;
end record;
-- combinatorial, registered and
-- double-registered signals
signal c, r, rr : reg_type;
-- signals for probing input and output data
signal in_data_probe, out_data_probe : std_logic_vector(data_width-1 downto 0);
signal equality_probe : std_ulogic;
-- signal data_acquisition : std_ulogic;
-- keep registers for debug purposes
attribute syn_preserve: boolean;
attribute syn_preserve of in_data_probe, out_data_probe, equality_probe : signal is true;
begin
comb : process (INT, DATA, HRESETn, ahbsi, r, rr)
variable v : reg_type;
-- register fields
variable tAtoCSlow : unsigned(1 downto 0); -- address to chip select (CS) low
variable tCStoCTRLlow : unsigned(1 downto 0); -- CS low to control (read/write) low
variable tCTRLlowDvalid : unsigned(1 downto 0); -- control (read) low to data valid
variable tCTRLlow : unsigned(1 downto 0); -- control low to control high
variable tCTRLhighCShigh : unsigned(1 downto 0); -- control high to CS high
variable tCShighREC : unsigned(1 downto 0); -- CS high to next CS recovery
variable tCNT : unsigned(counter_width-1 downto 0); -- timing counter
begin
-- assign values from the register in the beginning
-- lateron, assign new values by looking at the new
-- inputs from the bus
v := r;
-- data_acquisition <= '0';
if HRESETn = '0' then
v.hwrite := '0';
v.hready := '1';
v.hsel := '0';
v.addr := (others => '-');
v.counter := conv_unsigned(0, counter_width);
v.Din := (others => '-');
v.Dout := (others => '-');
v.nWR := '1';
v.nRD := '1';
v.nCS := '1';
v.INT := '0';
-- bit 12 is reserved for the interrupt
v.ctrlreg(15 downto 13) := (others => '0');
v.ctrlreg(11 downto 0) := (others => '0');
-- v.data_acquisition := '0';
end if;
-- assert data_acquisition for not longer than one cycle
v.data_acquisition := '0';
-- bit 12 of control register holds registered interrupt
v.ctrlreg(12) := INT;
v.INT := INT;
-- assign register fields to signals
tAtoCSlow := (unsigned(r.ctrlreg(11 downto 10)));
tCStoCTRLlow := (unsigned(r.ctrlreg(9 downto 8)));
tCTRLlowDvalid := (unsigned(r.ctrlreg(7 downto 6)));
tCTRLlow := (unsigned(r.ctrlreg(5 downto 4)));
tCTRLhighCShigh := (unsigned(r.ctrlreg(3 downto 2)));
tCShighREC := (unsigned(r.ctrlreg(1 downto 0)));
tCNT := conv_unsigned(conv_unsigned(0, counter_width) + tAtoCSlow + tCStoCTRLlow + tCTRLlow + tCTRLhighCShigh + tCShighREC + '1', counter_width);
-- is bus free to use?
if ahbsi.hready = '1' then
-- gets selected when HSEL signal for the right slave
-- is asserted and the transfer type is SEQ or NONSEQ
v.hsel := ahbsi.hsel(hindex) and ahbsi.htrans(1);
else
v.hsel := '0';
end if;
-- a valid cycle starts, so all relevant bus signals
-- are registered and the timer is started
if v.hsel = '1' and v.counter = conv_unsigned(0, counter_width) then
v.hwrite := ahbsi.hwrite and v.hsel;
v.hready := '0';
v.counter := conv_unsigned(tCNT, counter_width);
v.nWR := '1'; --not v.hwrite;
v.nRD := '1'; --v.hwrite;
v.nCS := '1';
if (conv_integer(ahbsi.haddr(19 downto 8)) = REGFILE_ADDRESS) then
if ahbsi.haddr(7 downto 0) = X"00" then
-- disable HPI signals, read/write register data
-- and manage AHB handshake
if v.hwrite = '1' then
-- take data from AHB write data bus but skip interrupt bit
if BIG_ENDIAN then
-- v.ctrlreg := ahbsi.hwdata(31 downto 31-data_width+1);
v.ctrlreg(15 downto 13) := ahbsi.hwdata(31 downto 29);
v.ctrlreg(11 downto 0) := ahbsi.hwdata(27 downto 16);
else
-- v.ctrlreg := ahbsi.hwdata(31-data_width downto 0);
v.ctrlreg(15 downto 13) := ahbsi.hwdata(15 downto 13);
v.ctrlreg(11 downto 0) := ahbsi.hwdata(11 downto 0);
end if;
else
v.Din := v.ctrlreg;
end if;
end if;
-- go to last cycle which signals ahb ready
v.counter := conv_unsigned(0, counter_width); --(tCNT - tAtoCSlow - tCStoCTRLlow - tCTRLlow - tCTRLhighCShigh - tCShighREC);
else
-- the LSB of 16-bit AHB addresses is always zero,
-- so the address is shifted in order to be able
-- to access data with a short* in C
v.addr := ahbsi.haddr(address_width downto 1);
-- v.size := ahbsi.hsize(1 downto 0);
-- fetch input data according to the AMBA specification
-- for big/little endian architectures
-- only relevant for 16-bit accesses
if v.addr(0) = '0' then
if BIG_ENDIAN then
v.Dout := ahbsi.hwdata(31 downto 31-data_width+1);
else
v.Dout := ahbsi.hwdata(31-data_width downto 0);
end if;
else
if BIG_ENDIAN then
v.Dout := ahbsi.hwdata(31-data_width downto 0);
else
v.Dout := ahbsi.hwdata(31 downto 31-data_width+1);
end if;
end if;
end if;
end if;
-- check if counter has just been re-initialized; if so,
-- decrement it until it reaches zero and set control signals
-- accordingly
if v.counter > conv_unsigned(0, counter_width) then
if v.counter = (tCNT - tAtoCSlow) then
v.nCS := '0';
end if;
if v.counter = (tCNT - tAtoCSlow - tCStoCTRLlow) then
v.nWR := not v.hwrite;
v.nRD := v.hwrite;
end if;
if v.counter = (tCNT - tAtoCSlow - tCStoCTRLlow - tCTRLlowDvalid) then
if v.nRD = '0' then
v.Din := DATA;
v.data_acquisition := '1';
-- in_data_probe <= DATA;
end if;
end if;
if v.counter = (tCNT - tAtoCSlow - tCStoCTRLlow - tCTRLlow) then
v.nWR := '1';
v.nRD := '1';
end if;
if v.counter = (tCNT - tAtoCSlow - tCStoCTRLlow - tCTRLlow - tCTRLhighCShigh) then
v.nCS := '1';
end if;
if v.counter = (tCNT - tAtoCSlow - tCStoCTRLlow - tCTRLlow
- tCTRLhighCShigh - tCShighREC) then
v.hready := '1';
end if;
-- note: since the counter is queried and immediately
-- decremented afterwards, the value in hardware
-- is one lower than given in the if statement
v.counter := v.counter - 1;
else
v.hready := '1';
end if;
-- assign variable to a signal
c <= v;
-- HPI outputs
ADDR <= r.addr;
nCS <= r.nCS;
nWR <= r.nWR;
nRD <= r.nRD;
-- three-state buffer: drive bus during a write cycle
-- and hold data for one more clock cycle, then
-- shut off from the bus
if ((r.nCS = '0' and r.nWR = '0') or (rr.nCS = '0' and r.nWR = '0') or
(r.nCS = '0' and rr.nWR = '0') or (rr.nCS = '0' and rr.nWR = '0')) then
DATA <= r.Dout;
else
DATA <= (others => 'Z');
end if;
-- output data is assigned to the both the high and the
-- low word of the 32-bit data bus
ahbso.hrdata(31 downto 31-data_width+1) <= r.Din;
ahbso.hrdata(31-data_width downto 0) <= r.Din; --(others => '-');
-- if v.addr(0) = '0' then
-- if BIG_ENDIAN then
-- ahbso.hrdata(31 downto 31-data_width+1) <= r.Din;
-- ahbso.hrdata(31-data_width downto 0) <= (others => '-');
-- else
-- ahbso.hrdata(31 downto 31-data_width+1) <= (others => '-');
-- ahbso.hrdata(31-data_width downto 0) <= r.Din;
-- end if;
-- else
-- if BIG_ENDIAN then
-- ahbso.hrdata(31 downto 31-data_width+1) <= (others => '-');
-- ahbso.hrdata(31-data_width downto 0) <= r.Din;
-- else
-- ahbso.hrdata(31 downto 31-data_width+1) <= r.Din;
-- ahbso.hrdata(31-data_width downto 0) <= (others => '-');
-- end if;
-- end if;
ahbso.hready <= r.hready;
ahbso.hirq <= (INTERRUPT_NUMBER => r.ctrlreg(12), others => '0'); -- propagate registered interrupt
-- ahbso.hirq <= (others => '0');
-- ahbso.hirq(INTERRUPT_NUMBER) <= r.ctrlreg(12);
end process comb;
-- constant AHB outputs
ahbso.hresp <= "00"; -- answer OK by default
ahbso.hsplit <= (others => '0'); -- no SPLIT transactions
ahbso.hcache <= '0'; -- cacheable yes/no
ahbso.hconfig <= hconfig;
ahbso.hindex <= hindex;
reg : process (HCLK)
begin
if rising_edge(HCLK) then
r <= c;
rr <= r;
end if;
end process;
---------------------------------------------------------------------------------------
-- DEBUG SECTION for triggering on read/write inconsistency
-- use a C program that writes data AND reads it immediately afterwards
-- dbg_equal start with being '0' after reset, then goes high during the transaction
-- it should not have a falling edge during the transactions
-- -> trigger on that event
-- note regarding HPI data transactions:
-- the address is written first before writing/reading at address B"10"
-- the data register is at address B"00"
---------------------------------------------------------------------------------------
-- read at the rising edge of the read signal
-- (before the next read data is received)
-- data_acquisition <= '1' when rr.nrd = '1' and r.nrd = '0' else
-- '0';
-- read data to compare to
in_data_probe <= r.din;
check_data : process (HCLK, HRESETn)
begin
if HRESETn = '0' then
out_data_probe <= (others => '0');
equality_probe <= '0';
elsif rising_edge(HCLK) then
-- is data being written to the *data* register?
if r.nwr = '0' and r.ncs = '0' and r.addr = "00" then
out_data_probe <= r.dout;
end if;
if r.data_acquisition = '1' then
if in_data_probe = out_data_probe then
equality_probe <= '1';
else
equality_probe <= '0';
end if;
end if;
end if;
end process;
dbg_equal <= equality_probe;
-- pragma translate_off
bootmsg : report_version
generic map ("ahb2hpi" & tost(hindex) &
": AHB-to-HPI Bridge, irq " &
tost(INTERRUPT_NUMBER));
-- pragma translate_on
end rtl;
| mit | c79bbc53c51b5e987c02e6457b2a725a | 0.531676 | 3.817867 | false | false | false | false |
impedimentToProgress/UCI-BlueChip | AttackFiles/Attacks/privEsc/lib/gaisler/misc/misc.vhd | 2 | 25,471 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Package: misc
-- File: misc.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: Misc models
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.devices.all;
use grlib.stdlib.all;
library techmap;
use techmap.gencomp.all;
library gaisler;
package misc is
-- reset generator with filter
component rstgen
generic (acthigh : integer := 0; syncrst : integer := 0;
scanen : integer := 0);
port (
rstin : in std_ulogic;
clk : in std_ulogic;
clklock : in std_ulogic;
rstout : out std_ulogic;
rstoutraw : out std_ulogic;
testrst : in std_ulogic := '0';
testen : in std_ulogic := '0');
end component;
type gptimer_in_type is record
dhalt : std_ulogic;
extclk : std_ulogic;
end record;
type gptimer_out_type is record
tick : std_logic_vector(0 to 7);
timer1 : std_logic_vector(31 downto 0);
wdogn : std_ulogic;
wdog : std_ulogic;
end record;
component gptimer
generic (
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#fff#;
pirq : integer := 0;
sepirq : integer := 0; -- use separate interrupts for each timer
sbits : integer := 16; -- scaler bits
ntimers : integer range 1 to 7 := 1; -- number of timers
nbits : integer := 32; -- timer bits
wdog : integer := 0
);
port (
rst : in std_ulogic;
clk : in std_ulogic;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
gpti : in gptimer_in_type;
gpto : out gptimer_out_type
);
end component;
-- 32-bit ram with AHB interface
component ahbram
generic (
hindex : integer := 0;
haddr : integer := 0;
hmask : integer := 16#fff#;
tech : integer := DEFMEMTECH;
kbytes : integer := 1);
port (
rst : in std_ulogic;
clk : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type);
end component;
type ahbram_out_type is record
ce : std_ulogic;
end record;
component ftahbram is
generic (
hindex : integer := 0;
haddr : integer := 0;
hmask : integer := 16#fff#;
tech : integer := DEFMEMTECH;
kbytes : integer := 1;
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#fff#;
edacen : integer := 1;
autoscrub : integer := 0;
errcnten : integer := 0;
cntbits : integer range 1 to 8 := 1;
ahbpipe : integer := 0);
port (
rst : in std_ulogic;
clk : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
aramo : out ahbram_out_type
);
end component;
component ahbtrace is
generic (
hindex : integer := 0;
ioaddr : integer := 16#000#;
iomask : integer := 16#E00#;
tech : integer := DEFMEMTECH;
irq : integer := 0;
kbytes : integer := 1);
port (
rst : in std_ulogic;
clk : in std_ulogic;
ahbmi : in ahb_mst_in_type;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type
);
end component;
type ahb_dma_in_type is record
address : std_logic_vector(31 downto 0);
wdata : std_logic_vector(31 downto 0);
start : std_ulogic;
burst : std_ulogic;
write : std_ulogic;
busy : std_ulogic;
irq : std_ulogic;
size : std_logic_vector(1 downto 0);
end record;
type ahb_dma_out_type is record
start : std_ulogic;
active : std_ulogic;
ready : std_ulogic;
retry : std_ulogic;
mexc : std_ulogic;
haddr : std_logic_vector(9 downto 0);
rdata : std_logic_vector(31 downto 0);
end record;
component ahbmst
generic (
hindex : integer := 0;
hirq : integer := 0;
venid : integer := VENDOR_GAISLER;
devid : integer := 0;
version : integer := 0;
chprot : integer := 3;
incaddr : integer := 0);
port (
rst : in std_ulogic;
clk : in std_ulogic;
dmai : in ahb_dma_in_type;
dmao : out ahb_dma_out_type;
ahbi : in ahb_mst_in_type;
ahbo : out ahb_mst_out_type
);
end component;
type gpio_in_type is record
din : std_logic_vector(31 downto 0);
sig_in : std_logic_vector(31 downto 0);
sig_en : std_logic_vector(31 downto 0);
end record;
type gpio_out_type is record
dout : std_logic_vector(31 downto 0);
oen : std_logic_vector(31 downto 0);
val : std_logic_vector(31 downto 0);
sig_out : std_logic_vector(31 downto 0);
end record;
type ahb2ahb_ctrl_type is record
slck : std_ulogic;
blck : std_ulogic;
end record;
component grgpio
generic (
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#fff#;
imask : integer := 16#0000#;
nbits : integer := 16; -- GPIO bits
oepol : integer := 0; -- Output enable polarity
syncrst : integer := 0;
bypass : integer := 16#0000#;
scantest : integer := 0;
bpdir : integer := 16#0000#
);
port (
rst : in std_ulogic;
clk : in std_ulogic;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
gpioi : in gpio_in_type;
gpioo : out gpio_out_type
);
end component;
component ahb2ahb
generic(
memtech : integer := 0;
hsindex : integer := 0;
hmindex : integer := 0;
slv : integer := 0;
dir : integer := 0; -- 0 - down, 1 - up
ffact : integer := 0;
pfen : integer range 0 to 1 := 0;
rbufsz : integer range 2 to 32 := 8;
wbufsz : integer range 2 to 32 := 2;
iburst : integer range 4 to 8 := 8;
rburst : integer range 2 to 32 := 8;
irqsync : integer range 0 to 2 := 0;
bar0 : integer range 0 to 1073741823 := 0;
bar1 : integer range 0 to 1073741823 := 0;
bar2 : integer range 0 to 1073741823 := 0;
bar3 : integer range 0 to 1073741823 := 0;
sbus : integer := 0;
mbus : integer := 0;
ioarea : integer := 0;
ibrsten : integer := 0);
port (
rstn : in std_ulogic;
hclkm : in std_ulogic;
hclks : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
ahbmi : in ahb_mst_in_type;
ahbmo : out ahb_mst_out_type;
ahbso2 : in ahb_slv_out_vector;
lcki : in ahb2ahb_ctrl_type;
lcko : out ahb2ahb_ctrl_type
);
end component;
component ahbbridge
generic(
memtech : integer := 0;
ffact : integer := 2;
-- high-speed bus
hsb_hsindex : integer := 0;
hsb_hmindex : integer := 0;
hsb_iclsize : integer range 4 to 8 := 8;
hsb_bank0 : integer range 0 to 1073741823 := 0;
hsb_bank1 : integer range 0 to 1073741823 := 0;
hsb_bank2 : integer range 0 to 1073741823 := 0;
hsb_bank3 : integer range 0 to 1073741823 := 0;
hsb_ioarea : integer := 0;
-- low-speed bus
lsb_hsindex : integer := 0;
lsb_hmindex : integer := 0;
lsb_rburst : integer range 16 to 32 := 16;
lsb_wburst : integer range 2 to 32 := 8;
lsb_bank0 : integer range 0 to 1073741823 := 0;
lsb_bank1 : integer range 0 to 1073741823 := 0;
lsb_bank2 : integer range 0 to 1073741823 := 0;
lsb_bank3 : integer range 0 to 1073741823 := 0;
lsb_ioarea : integer := 0);
port (
rstn : in std_ulogic;
hsb_clk : in std_ulogic;
lsb_clk : in std_ulogic;
hsb_ahbsi : in ahb_slv_in_type;
hsb_ahbso : out ahb_slv_out_type;
hsb_ahbsov: in ahb_slv_out_vector;
hsb_ahbmi : in ahb_mst_in_type;
hsb_ahbmo : out ahb_mst_out_type;
lsb_ahbsi : in ahb_slv_in_type;
lsb_ahbso : out ahb_slv_out_type;
lsb_ahbsov: in ahb_slv_out_vector;
lsb_ahbmi : in ahb_mst_in_type;
lsb_ahbmo : out ahb_mst_out_type);
end component;
function ahb2ahb_membar(memaddr : ahb_addr_type; prefetch, cache : std_ulogic;
addrmask : ahb_addr_type)
return integer;
function ahb2ahb_iobar(memaddr : ahb_addr_type; addrmask : ahb_addr_type)
return integer;
type ahbstat_in_type is record
cerror : std_logic_vector(0 to NAHBSLV-1);
end record;
component ahbstat is
generic(
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#FFF#;
pirq : integer := 0;
nftslv : integer range 1 to NAHBSLV - 1 := 3);
port(
rst : in std_ulogic;
clk : in std_ulogic;
ahbmi : in ahb_mst_in_type;
ahbsi : in ahb_slv_in_type;
stati : in ahbstat_in_type;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type
);
end component;
type nuhosp3_in_type is record
flash_d : std_logic_vector(15 downto 0);
smsc_data : std_logic_vector(31 downto 0);
smsc_ardy : std_ulogic;
smsc_intr : std_ulogic;
smsc_nldev : std_ulogic;
lcd_data : std_logic_vector(7 downto 0);
end record;
type nuhosp3_out_type is record
flash_a : std_logic_vector(20 downto 0);
flash_d : std_logic_vector(15 downto 0);
flash_oen : std_ulogic;
flash_wen : std_ulogic;
flash_cen : std_ulogic;
smsc_addr : std_logic_vector(14 downto 0);
smsc_data : std_logic_vector(31 downto 0);
smsc_nbe : std_logic_vector(3 downto 0);
smsc_resetn : std_ulogic;
smsc_nrd : std_ulogic;
smsc_nwr : std_ulogic;
smsc_ncs : std_ulogic;
smsc_aen : std_ulogic;
smsc_lclk : std_ulogic;
smsc_wnr : std_ulogic;
smsc_rdyrtn : std_ulogic;
smsc_cycle : std_ulogic;
smsc_nads : std_ulogic;
smsc_ben : std_ulogic;
lcd_data : std_logic_vector(7 downto 0);
lcd_rs : std_ulogic;
lcd_rw : std_ulogic;
lcd_en : std_ulogic;
lcd_backl : std_ulogic;
lcd_ben : std_ulogic;
end record;
component nuhosp3
generic (
hindex : integer := 0;
haddr : integer := 0;
hmask : integer := 16#fff#;
ioaddr : integer := 16#200#;
iomask : integer := 16#fff#);
port (
rst : in std_ulogic;
clk : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
nui : in nuhosp3_in_type;
nuo : out nuhosp3_out_type
);
end component;
-- On-chip Logic Analyzer
component logan is
generic (
dbits : integer range 0 to 256 := 32; -- Number of traced signals
depth : integer range 256 to 16384 := 1024; -- Depth of trace buffer
trigl : integer range 1 to 63 := 1; -- Number of trigger levels
usereg : integer range 0 to 1 := 1; -- Use input register
usequal : integer range 0 to 1 := 0;
usediv : integer range 0 to 1 := 1;
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#F00#;
memtech : integer := DEFMEMTECH);
port (
rstn : in std_logic;
clk : in std_logic;
tclk : in std_logic;
apbi : in apb_slv_in_type; -- APB in record
apbo : out apb_slv_out_type; -- APB out record
signals : in std_logic_vector(dbits - 1 downto 0)); -- Traced signals
end component;
type ps2_in_type is record
ps2_clk_i : std_ulogic;
ps2_data_i : std_ulogic;
end record;
type ps2_out_type is record
ps2_clk_o : std_ulogic;
ps2_clk_oe : std_ulogic;
ps2_data_o : std_ulogic;
ps2_data_oe : std_ulogic;
end record;
component apbps2
generic(
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#fff#;
pirq : integer := 0;
fKHz : integer := 50000;
fixed : integer := 1);
port(
rst : in std_ulogic; -- Global asynchronous reset
clk : in std_ulogic; -- Global clock
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
ps2i : in ps2_in_type;
ps2o : out ps2_out_type
);
end component;
type apbvga_out_type is record
hsync : std_ulogic; -- horizontal sync
vsync : std_ulogic; -- vertical sync
comp_sync : std_ulogic; -- composite sync
blank : std_ulogic; -- blank signal
video_out_r : std_logic_vector(7 downto 0); -- red channel
video_out_g : std_logic_vector(7 downto 0); -- green channel
video_out_b : std_logic_vector(7 downto 0); -- blue channel
end record;
component apbvga
generic(
memtech : integer := DEFMEMTECH;
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#fff#);
port(
rst : in std_ulogic; -- Global asynchronous reset
clk : in std_ulogic; -- Global clock
vgaclk : in std_ulogic; -- VGA clock
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
vgao : out apbvga_out_type
);
end component;
component svgactrl
generic(
length : integer := 384; -- Fifo-length
part : integer := 128; -- Fifo-part lenght
memtech : integer := DEFMEMTECH;
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#fff#;
hindex : integer := 0;
hirq : integer := 0;
clk0 : integer := 40000;
clk1 : integer := 20000;
clk2 : integer := 15385;
clk3 : integer := 0;
burstlen : integer range 2 to 8 := 8
);
port (
rst : in std_logic;
clk : in std_logic;
vgaclk : in std_logic;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
vgao : out apbvga_out_type;
ahbi : in ahb_mst_in_type;
ahbo : out ahb_mst_out_type;
clk_sel : out std_logic_vector(1 downto 0)
);
end component;
constant vgao_none : apbvga_out_type :=
('0', '0', '0', '0', "00000000", "00000000", "00000000");
constant ps2o_none : ps2_out_type := ('1', '1', '1', '1');
-- component ahbrom
-- generic (
-- hindex : integer := 0;
-- haddr : integer := 0;
-- hmask : integer := 16#fff#;
-- pipe : integer := 0;
-- tech : integer := 0;
-- kbytes : integer := 1);
-- port (
-- rst : in std_ulogic;
-- clk : in std_ulogic;
-- ahbsi : in ahb_slv_in_type;
-- ahbso : out ahb_slv_out_type
-- );
-- end component;
component ahbdma
generic (
hindex : integer := 0;
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#fff#;
pirq : integer := 0;
dbuf : integer := 0);
port (
rst : in std_logic;
clk : in std_ulogic;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
ahbi : in ahb_mst_in_type;
ahbo : out ahb_mst_out_type
);
end component;
-----------------------------------------------------------------------------
-- Interface type declarations for FIFO controller
-----------------------------------------------------------------------------
type FIFO_In_Type is record
Din: Std_Logic_Vector(31 downto 0); -- data input
Pin: Std_Logic_Vector( 3 downto 0); -- parity input
EFn: Std_ULogic; -- empty flag
FFn: Std_ULogic; -- full flag
HFn: Std_ULogic; -- half flag
end record;
type FIFO_Out_Type is record
Dout: Std_Logic_Vector(31 downto 0); -- data output
Den: Std_Logic_Vector(31 downto 0); -- data enable
Pout: Std_Logic_Vector( 3 downto 0); -- parity output
Pen: Std_Logic_Vector( 3 downto 0); -- parity enable
WEn: Std_ULogic; -- write enable
REn: Std_ULogic; -- read enable
end record;
-----------------------------------------------------------------------------
-- Component declaration for GR FIFO Interface
-----------------------------------------------------------------------------
component grfifo is
generic (
hindex: Integer := 0;
pindex: Integer := 0;
paddr: Integer := 0;
pmask: Integer := 16#FFF#;
pirq: Integer := 1; -- index of first irq
dwidth: Integer := 16; -- data width
ptrwidth: Integer range 4 to 16 := 12; -- 16 to 64k bytes
-- 128 to 512k bits
singleirq: Integer range 0 to 1 := 0; -- single irq output
oepol: Integer := 1); -- output enable polarity
port (
rstn: in Std_ULogic;
clk: in Std_ULogic;
apbi: in APB_Slv_In_Type;
apbo: out APB_Slv_Out_Type;
ahbi: in AHB_Mst_In_Type;
ahbo: out AHB_Mst_Out_Type;
fifoi: in FIFO_In_Type;
fifoo: out FIFO_Out_Type);
end component;
-----------------------------------------------------------------------------
-- Interface type declarations for CAN controllers
-----------------------------------------------------------------------------
type Analog_In_Type is record
Ain: Std_Logic_Vector(31 downto 0); -- address input
Din: Std_Logic_Vector(31 downto 0); -- data input
Rdy: Std_ULogic; -- adc ready input
Trig: Std_Logic_Vector( 2 downto 0); -- adc trigger inputs
end record;
type Analog_Out_Type is record
Aout: Std_Logic_Vector(31 downto 0); -- address output
Aen: Std_Logic_Vector(31 downto 0); -- address enable
Dout: Std_Logic_Vector(31 downto 0); -- dac data output
Den: Std_Logic_Vector(31 downto 0); -- dac data enable
Wr: Std_ULogic; -- dac write strobe
CS: Std_ULogic; -- adc chip select
RC: Std_ULogic; -- adc read/convert
end record;
-----------------------------------------------------------------------------
-- Component declaration for GR ADC/DAC Interface
-----------------------------------------------------------------------------
component gradcdac is
generic (
pindex: Integer := 0;
paddr: Integer := 0;
pmask: Integer := 16#FFF#;
pirq: Integer := 1; -- index of first irq
awidth: Integer := 8; -- address width
dwidth: Integer := 16; -- data width
oepol: Integer := 1); -- output enable polarity
port (
rstn: in Std_ULogic;
clk: in Std_ULogic;
apbi: in APB_Slv_In_Type;
apbo: out APB_Slv_Out_Type;
adi: in Analog_In_Type;
ado: out Analog_Out_Type);
end component;
component grclkgate
generic (
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#fff#;
nbits : integer := 16
);
port (
rst : in std_ulogic;
clk : in std_ulogic;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
clockdis : out std_logic_vector(nbits-1 downto 0);
reset : out std_logic_vector(nbits-1 downto 0)
);
end component;
-----------------------------------------------------------------------------
-- I2C types and components
-----------------------------------------------------------------------------
type i2c_in_type is record
scl : std_ulogic;
sda : std_ulogic;
end record;
type i2c_out_type is record
scl : std_ulogic;
scloen : std_ulogic;
sda : std_ulogic;
sdaoen : std_ulogic;
end record;
-- AMBA wrapper for OC I2C-master
component i2cmst
generic (
pindex : integer;
paddr : integer;
pmask : integer;
pirq : integer;
oepol : integer range 0 to 1 := 0
);
port (
rstn : in std_ulogic;
clk : in std_ulogic;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
i2ci : in i2c_in_type;
i2co : out i2c_out_type
);
end component;
component i2cslv
generic (
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#fff#;
pirq : integer := 0;
hardaddr : integer range 0 to 1 := 0;
tenbit : integer range 0 to 1 := 0;
i2caddr : integer range 0 to 1023 := 0;
oepol : integer range 0 to 1 := 0
);
port (
rstn : in std_ulogic;
clk : in std_ulogic;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
i2ci : in i2c_in_type;
i2co : out i2c_out_type
);
end component;
-----------------------------------------------------------------------------
-- SPI controller
-----------------------------------------------------------------------------
type spi_in_type is record
miso : std_ulogic;
mosi : std_ulogic;
sck : std_ulogic;
spisel : std_ulogic;
end record;
type spi_out_type is record
miso : std_ulogic;
misooen : std_ulogic;
mosi : std_ulogic;
mosioen : std_ulogic;
sck : std_ulogic;
sckoen : std_ulogic;
ssn : std_logic_vector(7 downto 0); -- used by GE/OC SPI core
end record;
component spictrl
generic (
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#fff#;
pirq : integer := 0;
fdepth : integer range 1 to 7 := 1;
slvselen : integer range 0 to 1 := 0;
slvselsz : integer range 1 to 32 := 1;
oepol : integer range 0 to 1 := 0
);
port (
rstn : in std_ulogic;
clk : in std_ulogic;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
spii : in spi_in_type;
spio : out spi_out_type;
slvsel : out std_logic_vector((slvselsz-1) downto 0)
);
end component;
function nandtree(v : std_logic_vector) return std_ulogic;
end;
package body misc is
function ahb2ahb_membar(memaddr : ahb_addr_type; prefetch, cache : std_ulogic;
addrmask : ahb_addr_type)
return integer is
variable tmp : std_logic_vector(29 downto 0);
variable bar : std_logic_vector(31 downto 0);
variable res : integer range 0 to 1073741823;
begin
bar := ahb_membar(memaddr, prefetch, cache, addrmask);
tmp := (others => '0');
tmp(29 downto 18) := bar(31 downto 20);
tmp(17 downto 0) := bar(17 downto 0);
res := conv_integer(tmp);
return(res);
end;
function ahb2ahb_iobar(memaddr : ahb_addr_type; addrmask : ahb_addr_type)
return integer is
variable tmp : std_logic_vector(29 downto 0);
variable bar : std_logic_vector(31 downto 0);
variable res : integer range 0 to 1073741823;
begin
bar := ahb_iobar(memaddr, addrmask);
tmp := (others => '0');
tmp(29 downto 18) := bar(31 downto 20);
tmp(17 downto 0) := bar(17 downto 0);
res := conv_integer(tmp);
return(res);
end;
function nandtree(v : std_logic_vector) return std_ulogic is
variable a : std_logic_vector(v'length-1 downto 0);
variable b : std_logic_vector(v'length downto 0);
begin
a := v; b(0) := '1';
for i in 0 to v'length-1 loop
b(i+1) := a(i) nand b(i);
end loop;
return b(v'length);
end;
end;
| mit | 58933fe9133eea2139777f3e71e84b1e | 0.511327 | 3.69359 | false | false | false | false |
michaelfivez/ascon_hardware_implementation | ascon128128_unrolled4/Kernel/Ascon_block_control.vhd | 1 | 7,340 | -------------------------------------------------------------------------------
--! @project Unrolled (factor 4) hardware implementation of Asconv128128
--! @author Michael Fivez
--! @license This project is released under the GNU Public License.
--! The license and distribution terms for this file may be
--! found in the file LICENSE in this distribution or at
--! http://www.gnu.org/licenses/gpl-3.0.txt
--! @note This is an hardware implementation made for my graduation thesis
--! at the KULeuven, in the COSIC department (year 2015-2016)
--! The thesis is titled 'Energy efficient hardware implementations of CAESAR submissions',
--! and can be found on the COSIC website (www.esat.kuleuven.be/cosic/publications)
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity Ascon_StateUpdate_control is
port(
Clk : in std_logic; -- Clock
Reset : in std_logic; -- Reset (synchronous)
-- Control signals
RoundNr : out std_logic_vector(1 downto 0);
sel1,sel2,sel3,sel4 : out std_logic_vector(1 downto 0);
sel0 : out std_logic_vector(2 downto 0);
selout : out std_logic;
Reg0En,Reg1En,Reg2En,Reg3En,Reg4En,RegOutEn : out std_logic;
ActivateGen : out std_logic;
GenSize : out std_logic_vector(3 downto 0);
-- External control signals
Start : in std_logic;
Mode : in std_logic_vector(3 downto 0);
Size : in std_logic_vector(3 downto 0); -- only matters for last block decryption
Busy : out std_logic
);
end entity Ascon_StateUpdate_control;
architecture structural of Ascon_StateUpdate_control is
begin
-----------------------------------------
------ The Finite state machine --------
-----------------------------------------
-- Modes: initialization, associative data, encryption, decryption, tag generation, final encryption, final decryption, seperation constant
-- 0010 0000 0110 0100 0001 0111 0101, 0011
-- case1 1000, case2 1001
fsm: process(Clk, Reset) is
type state_type is (IDLE,LOADNEW,CRYPT,TAG);
variable CurrState : state_type := IDLE;
variable RoundNrVar : std_logic_vector(1 downto 0);
begin
if Clk'event and Clk = '1' then
-- default values
sel0 <= "000";
sel1 <= "00";
sel2 <= "00";
sel3 <= "00";
sel4 <= "00";
selout <= '0';
Reg0En <= '0';
Reg1En <= '0';
Reg2En <= '0';
Reg3En <= '0';
Reg4En <= '0';
RegOutEn <= '0';
ActivateGen <= '0';
GenSize <= "0000";
Busy <= '0';
if Reset = '1' then -- synchronous reset active high
-- registers used by fsm:
RoundNrVar := "00";
CurrState := IDLE;
else
FSMlogic : case CurrState is
when IDLE =>
if Start = '1' then
Busy <= '1';
if Mode = "0000" then -- AD mode
RoundNrVar := "11"; -- so starts at 0 next cycle
-- set Sel and Enables signal (Xor with DataIn)
sel0 <= "010";
sel1 <= "10";
Reg0En <= '1';
Reg1En <= '1';
CurrState := CRYPT;
elsif Mode = "0100" then -- Decryption mode
RoundNrVar := "11"; -- so starts at 0 next cycle
-- set Sel and Enables signal (Generate output and xor state)
ActivateGen <= '1';
sel0 <= "010";
sel1 <= "10";
Reg0En <= '1';
Reg1En <= '1';
RegOutEn <= '1';
CurrState := CRYPT;
elsif Mode = "0110" then -- Encryption
RoundNrVar := "11"; -- so starts at 0 next cycle
-- set Sel and Enables signal (Generate output and xor state)
sel0 <= "010";
sel1 <= "10";
Reg0En <= '1';
Reg1En <= '1';
RegOutEn <= '1';
CurrState := CRYPT;
elsif Mode = "0001" then -- Tag mode
RoundNrVar := "11"; -- so starts at 0 next cycle
-- set Sel and Enables signal (XOR middle with key)
sel2 <= "10";
sel3 <= "11";
Reg2En <= '1';
Reg3En <= '1';
CurrState := TAG;
elsif Mode = "0111" then -- Last block encryption
-- set Sel and Enables signal (Generate output and xor state)
sel0 <= "010";
sel1 <= "10";
Reg0En <= '1';
Reg1En <= '1';
RegOutEn <= '1';
CurrState := IDLE;
elsif Mode = "0101" then -- Last block decryption
-- set Sel and Enables signal (Generate output and xor state)
ActivateGen <= '1';
GenSize <= Size;
sel0 <= "010";
sel1 <= "10";
Reg0En <= '1';
Reg1En <= '1';
RegOutEn <= '1';
CurrState := IDLE;
elsif Mode = "0011" then -- Seperation constant
sel4 <= "11";
Reg4En <= '1';
CurrState := IDLE;
elsif Mode = "0010" then -- Initialization mode
RoundNrVar := "11"; -- so starts at 0 next cycle
-- set Sel and Enables signal (Load in key and IV)
sel0 <= "001";
sel1 <= "01";
sel2 <= "01";
sel3 <= "01";
sel4 <= "01";
Reg0En <= '1';
Reg1En <= '1';
Reg2En <= '1';
Reg3En <= '1';
Reg4En <= '1';
CurrState := LOADNEW;
elsif Mode = "1000" then -- case1
sel0 <= "100";
Reg0En <= '1';
CurrState := IDLE;
else -- case2
sel0 <= "100";
Reg0En <= '1';
RoundNrVar := "11"; -- so starts at 0 next cycle
CurrState := CRYPT;
end if;
else
Busy <= '0';
CurrState := IDLE;
end if;
when LOADNEW =>
if RoundNrVar = "10" then -- RoundNrVar = 2 (10xx, 1000, 1001, 1010 and 1011)
-- set Sel and Enables signal (Xor at the end)
sel3 <= "10";
sel4 <= "10";
Reg3En <= '1';
Reg4En <= '1';
CurrState := IDLE;
Busy <= '0';
else
RoundNrVar := std_logic_vector(unsigned(RoundNrVar) + 1);
-- set Sel and Enables signal (execute a round)
Reg0En <= '1';
Reg1En <= '1';
Reg2En <= '1';
Reg3En <= '1';
Reg4En <= '1';
CurrState := LOADNEW;
Busy <= '1';
end if;
when CRYPT =>
if RoundNrVar = "00" then -- RoundNrVar = 0 (01xx, 1000, 1001, 1010 and 1011 will be done)
RoundNrVar := std_logic_vector(unsigned(RoundNrVar) + 1);
-- set Sel and Enables signal (execute a round)
Reg0En <= '1';
Reg1En <= '1';
Reg2En <= '1';
Reg3En <= '1';
Reg4En <= '1';
CurrState := IDLE;
Busy <= '0';
else
RoundNrVar := std_logic_vector(unsigned(RoundNrVar) + 1);
-- set Sel and Enables signal (execute a round)
Reg0En <= '1';
Reg1En <= '1';
Reg2En <= '1';
Reg3En <= '1';
Reg4En <= '1';
CurrState := CRYPT;
Busy <= '1';
end if;
when TAG =>
if RoundNrVar = "10" then -- RoundNrVar = 2 (10xx, 1000, 1001, 1010 and 1011)
-- set Sel and Enables signal (connect tag to output)
selout <= '1';
RegOutEn <= '1';
CurrState := IDLE;
Busy <= '0';
else
RoundNrVar := std_logic_vector(unsigned(RoundNrVar) + 1);
-- set Sel and Enables signal (execute a round)
Reg0En <= '1';
Reg1En <= '1';
Reg2En <= '1';
Reg3En <= '1';
Reg4En <= '1';
CurrState := TAG;
Busy <= '1';
end if;
end case FSMlogic;
RoundNr <= RoundNrVar;
end if;
end if;
end process fsm;
end architecture structural;
| gpl-3.0 | a5192d4b0a7721e54789b9c9c0ffa647 | 0.535286 | 3.177489 | false | false | false | false |
michaelfivez/ascon_hardware_implementation | ascon128128_iterated/Kernel/FullDiffLayer.vhd | 1 | 2,094 | -------------------------------------------------------------------------------
--! @project Iterate hardware implementation of Asconv128128
--! @author Michael Fivez
--! @license This project is released under the GNU Public License.
--! The license and distribution terms for this file may be
--! found in the file LICENSE in this distribution or at
--! http://www.gnu.org/licenses/gpl-3.0.txt
--! @note This is an hardware implementation made for my graduation thesis
--! at the KULeuven, in the COSIC department (year 2015-2016)
--! The thesis is titled 'Energy efficient hardware implementations of CAESAR submissions',
--! and can be found on the COSIC website (www.esat.kuleuven.be/cosic/publications)
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity FullDiffusionLayer is
port(
X0In : in std_logic_vector(63 downto 0);
X1In : in std_logic_vector(63 downto 0);
X2In : in std_logic_vector(63 downto 0);
X3In : in std_logic_vector(63 downto 0);
X4In : in std_logic_vector(63 downto 0);
X0Out : out std_logic_vector(63 downto 0);
X1Out : out std_logic_vector(63 downto 0);
X2Out : out std_logic_vector(63 downto 0);
X3Out : out std_logic_vector(63 downto 0);
X4Out : out std_logic_vector(63 downto 0));
end entity FullDiffusionLayer;
architecture structural of FullDiffusionLayer is
begin
Diff0: entity work.DiffusionLayer
generic map(SHIFT1 => 19,SHIFT2 => 28)
port map(X0In,X0Out);
Diff1: entity work.DiffusionLayer
generic map(SHIFT1 => 61,SHIFT2 => 39)
port map(X1In,X1Out);
Diff2: entity work.DiffusionLayer
generic map(SHIFT1 => 1,SHIFT2 => 6)
port map(X2In,X2Out);
Diff3: entity work.DiffusionLayer
generic map(SHIFT1 => 10,SHIFT2 => 17)
port map(X3In,X3Out);
Diff4: entity work.DiffusionLayer
generic map(SHIFT1 => 7,SHIFT2 => 41)
port map(X4In,X4Out);
end architecture structural;
| gpl-3.0 | 32f143ed250346363e44f0d3156ea649 | 0.628462 | 3.3504 | false | false | false | false |
impedimentToProgress/UCI-BlueChip | AttackFiles/Attacks/privEsc/lib/esa/memoryctrl/memoryctrl.vhd | 2 | 2,150 | ----------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2004 GAISLER RESEARCH
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- See the file COPYING for the full details of the license.
--
------------------------------------------------------------------------------
-- Entity: memctrl
-- File: memctrl.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: Memory controller package
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
library gaisler;
use gaisler.memctrl.all;
package memoryctrl is
component mctrl
generic (
hindex : integer := 0;
pindex : integer := 0;
romaddr : integer := 16#000#;
rommask : integer := 16#E00#;
ioaddr : integer := 16#200#;
iomask : integer := 16#E00#;
ramaddr : integer := 16#400#;
rammask : integer := 16#C00#;
paddr : integer := 0;
pmask : integer := 16#fff#;
wprot : integer := 0;
invclk : integer := 0;
fast : integer := 0;
romasel : integer := 28;
sdrasel : integer := 29;
srbanks : integer := 4;
ram8 : integer := 0;
ram16 : integer := 0;
sden : integer := 0;
sepbus : integer := 0;
sdbits : integer := 32;
sdlsb : integer := 2;
oepol : integer := 0;
syncrst : integer := 0;
pageburst : integer := 0
);
port (
rst : in std_ulogic;
clk : in std_ulogic;
memi : in memory_in_type;
memo : out memory_out_type;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
wpo : in wprot_out_type;
sdo : out sdram_out_type
);
end component;
end;
| mit | f7575914ba226ee4931444c1f39af083 | 0.516279 | 3.901996 | false | false | false | false |
impedimentToProgress/UCI-BlueChip | AttackFiles/Attacks/privEsc/lib/opencores/ata/ro_cnt.vhd | 2 | 5,121 | ---------------------------------------------------------------------
---- ----
---- Run-Once Counter ----
---- ----
---- Author: Richard Herveille ----
---- [email protected] ----
---- www.asics.ws ----
---- ----
---------------------------------------------------------------------
---- ----
---- Copyright (C) 2001, 2002 Richard Herveille ----
---- [email protected] ----
---- ----
---- This source file may be used and distributed without ----
---- restriction provided that this copyright statement is not ----
---- removed from the file and that any derivative work contains ----
---- the original copyright notice and the associated disclaimer.----
---- ----
---- THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ----
---- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ----
---- TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ----
---- FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ----
---- OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ----
---- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ----
---- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ----
---- GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ----
---- BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ----
---- LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ----
---- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ----
---- OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ----
---- POSSIBILITY OF SUCH DAMAGE. ----
---- ----
---------------------------------------------------------------------
--
-- CVS Log
--
-- $Id: ro_cnt.vhd,v 1.1 2002/03/01 03:49:03 rherveille Exp $
--
-- $Date: 2002/03/01 03:49:03 $
-- $Revision: 1.1 $
-- $Author: rherveille $
-- $Locker: $
-- $State: Exp $
--
-- Change History:
-- $Log: ro_cnt.vhd,v $
-- Revision 1.1 2002/03/01 03:49:03 rherveille
-- Changed internal counter libraries.
-- Split counter.vhd into separate files.
-- Core is in same state as Verilog version now.
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity ro_cnt is
generic(
SIZE : natural := 8;
UD : integer := 0; -- default count down
ID : natural := 0 -- initial data after reset
);
port(
clk : in std_logic; -- master clock
nReset : in std_logic := '1'; -- asynchronous active low reset
rst : in std_logic := '0'; -- synchronous active high reset
cnt_en : in std_logic := '1'; -- count enable
go : in std_logic; -- load counter and start sequence
done : out std_logic; -- done counting
d : in std_logic_vector(SIZE -1 downto 0); -- load counter value
q : out std_logic_vector(SIZE -1 downto 0) -- current counter value
);
end entity ro_cnt;
architecture structural of ro_cnt is
component ud_cnt is
generic(
SIZE : natural := 8;
RESD : natural := 0 -- initial data after reset
);
port(
clk : in std_logic; -- master clock
nReset : in std_logic := '1'; -- asynchronous active low reset
rst : in std_logic := '0'; -- synchronous active high reset
cnt_en : in std_logic := '1'; -- count enable
ud : in std_logic := '0'; -- up / not down
nld : in std_logic := '1'; -- synchronous active low load
d : in std_logic_vector(SIZE -1 downto 0); -- load counter value
q : out std_logic_vector(SIZE -1 downto 0); -- current counter value
rci : in std_logic := '1'; -- carry input
rco : out std_logic -- carry output
);
end component ud_cnt;
signal rci, rco, nld, UDP : std_logic;
begin
gen_ctrl: process(clk, nReset)
begin
if (nReset = '0') then
rci <= '0';
elsif (clk'event and clk = '1') then
if (rst = '1') then
rci <= '0';
else
rci <= go or (rci and not rco);
end if;
end if;
end process;
nld <= not go;
UDP <= '0' when UD = 0 else '1';
-- hookup counter
cnt : ud_cnt
generic map (
SIZE => SIZE,
RESD => ID
)
port map (
clk => clk,
nReset => nReset,
rst => rst,
cnt_en => cnt_en,
ud => UDP,
nld => nld,
D => D,
Q => Q,
rci => rci,
rco => rco
);
done <= rco;
end architecture structural;
| mit | 33e09f25ce2da936d2e88389c5fd8dc2 | 0.462019 | 4.113253 | false | false | false | false |
impedimentToProgress/UCI-BlueChip | AttackFiles/Attacks/privEsc/lib/gaisler/ddr/ddrctrl.vhd | 2 | 33,891 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: ddrctrl
-- File: ddrctrl.vhd
-- Author: David Lindh - Gaisler Research
-- Description: DDR-RAM memory controller with AMBA interface
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
library gaisler;
use grlib.devices.all;
use gaisler.memctrl.all;
library techmap;
use techmap.gencomp.all;
use techmap.allmem.all;
use gaisler.ddrrec.all;
entity ddrctrl is
generic (
hindex1 : integer := 0;
haddr1 : integer := 0;
hmask1 : integer := 16#f80#;
hindex2 : integer := 0;
haddr2 : integer := 0;
hmask2 : integer := 16#f80#;
pindex : integer := 3;
paddr : integer := 0;
numahb : integer := 1; -- Allowed: 1, 2
ahb1sepclk : integer := 0; -- Allowed: 0, 1
ahb2sepclk : integer := 0; -- Allowed: 0, 1
modbanks : integer := 1; -- Allowed: 1, 2
numchips : integer := 2; -- Allowed: 1, 2, 4, 8, 16
chipbits : integer := 16; -- Allowed: 4, 8, 16
chipsize : integer := 256; -- Allowed: 64, 128, 256, 512, 1024 (MB)
plldelay : integer := 0; -- Allowed: 0, 1 (Use 200us start up delay)
tech : integer := virtex2;
clkperiod : integer := 10); -- (ns)
port (
rst : in std_ulogic;
clk0 : in std_ulogic;
clk90 : in std_ulogic;
clk180 : in std_ulogic;
clk270 : in std_ulogic;
hclk1 : in std_ulogic;
hclk2 : in std_ulogic;
pclk : in std_ulogic;
ahb1si : in ahb_slv_in_type;
ahb1so : out ahb_slv_out_type;
ahb2si : in ahb_slv_in_type;
ahb2so : out ahb_slv_out_type;
apbsi : in apb_slv_in_type;
apbso : out apb_slv_out_type;
ddsi : out ddrmem_in_type;
ddso : in ddrmem_out_type);
end ddrctrl;
architecture rtl of ddrctrl is
-------------------------------------------------------------------------------
-- Constants
-------------------------------------------------------------------------------
constant DELAY_15600NS : integer := (15600 / clkperiod);
constant DELAY_7800NS : integer := (7800 / clkperiod);
constant DELAY_7_15600NS : integer := (7*(15600 / clkperiod));
constant DELAY_7_7800NS : integer := (7*(7800 / clkperiod));
constant DELAY_200US : integer := (200000 / clkperiod);
constant REVISION : integer := 0;
constant pmask : integer := 16#fff#;
constant pconfig : apb_config_type := (
0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_DDRMP, 0, REVISION, 0),
1 => apb_iobar(paddr, pmask));
constant dqsize : integer := numchips*chipbits;
constant dmsize : integer := (dqsize/8);
constant strobesize : integer := (dqsize/8) * dmvector(chipbits);
-------------------------------------------------------------------------------
-- Signals
-------------------------------------------------------------------------------
signal toAHB : two_ahb_ctrl_in_type;
signal fromAHB : two_ahb_ctrl_out_type;
signal fromAHB2Main : two_ahb_ctrl_out_type;
signal apbr : apb_reg_type;
signal apbri : apb_reg_type;
signal fromAPB : apb_ctrl_out_type;
signal fromAPB2Main : apb_ctrl_out_type;
signal mainr : main_reg_type;
signal mainri : main_reg_type;
signal fromMain : main_ctrl_out_type;
signal fromMain2APB : apb_ctrl_in_type;
signal fromMain2AHB : two_ahb_ctrl_in_type;
signal fromMain2HS : hs_in_type;
signal toHS : hs_in_type;
signal fromHS : hs_out_type;
begin -- achitecture rtl
-------------------------------------------------------------------------------
-- Error reports
assert (tech = virtex2 or tech = virtex4 or tech = lattice) report "Unsupported technology by DDR controller (generic tech)" severity failure;
assert (modbanks=1 or modbanks=2) report "Only 1 or 2 module banks is supported (generic modbanks)" severity failure;
assert (chipbits=4 or chipbits=8 or chipbits=16) report "DDR chips either have 4, 8 or 16 bits output (generic chipbits)" severity failure;
assert (chipsize=64 or chipsize=128 or chipsize=256 or chipsize=512 or chipsize=1024) report "DDR chips either have 64, 128, 256, 512 or 1024 Mbit size" severity failure;
assert (buffersize>=2) report "Buffer must have room for at least 2 bursts (generic buffersize)" severity failure;
assert (plldelay=0 or plldelay=1) report "Invalid setting for DDRRAM PLL delay (generic plldelay)" severity failure;
assert (numahb=1 or numahb=2) report "Only one or two AHB interfaces can be used (generic numahb)" severity failure;
-------------------------------------------------------------------------------
-- APB control
-- Controls APB bus. Contains the DDRCFG register. Clear memcmd
-- bits when a memory command requested on APB is complete.
apbcomb : process(apbr, apbsi, fromMain2APB, rst)
variable v : apb_reg_type;
begin
v:= apbr;
if rst = '0' then -- Reset
v.ddrcfg_reg := ddrcfg_reset;
elsif fromMain2APB.apb_cmd_done = '1' then -- Clear memcmd bits
v.ddrcfg_reg(28 downto 27) := "00";
elsif (apbsi.psel(pindex) and apbsi.penable and apbsi.pwrite) = '1' then -- Write
v.ddrcfg_reg := apbsi.pwdata(31 downto 1) & fromMain2APB.ready;
else
v.ddrcfg_reg(0) := fromMain2APB.ready;
end if;
apbri <= v;
fromAPB.ddrcfg_reg <= v.ddrcfg_reg;
end process apbcomb;
apbclk : process(pclk)
begin
if rising_edge(pclk) then apbr <= apbri; end if;
end process;
apbso.prdata <= fromAPB.ddrcfg_reg; apbso.pirq <= (others => '0');
apbso.pindex <= pindex; apbso.pconfig <= pconfig;
-------------------------------------------------------------------------------
-- Main controller
-------------------------------------------------------------------------------
maincomb : process(mainr, fromAHB, fromAHB2Main, fromAPB2Main, rst, fromHS)
variable v : main_reg_type;
begin
v := mainr; v.loadcmdbuffer := '0'; -- Clear Cmd loading bit
-------------------------------------------------------------------------------
-- DDRCFG control
-- Reads DDRCFG from APB controller. Handles refresh command from refresh
-- timer and memoory comand requested on APB.
case v.apbstate is
when idle =>
v.apb_cmd_done := '0';
-- Refresh timer signals refresh
if v.doRefresh = '1' and v.ddrcfg.refresh = '1' then
v.apbstate := refresh;
-- LMR cmd on APB bus
elsif fromAPB2Main.ddrcfg_reg(28 downto 27) = "11" then
v.lockAHB := "11";
v.apbstate := wait_lmr1;
-- Refresh or Precharge cmd on APB BUS
elsif fromAPB2Main.ddrcfg_reg(28 downto 27) > "00" then
v.apbstate := cmd;
-- Nothing to be done
else
v.ddrcfg.memcmd := "00";
end if;
-- Refresh from Timer
when refresh =>
if v.mainstate = idle then v.ddrcfg.memcmd := "10"; end if;
if v.dorefresh = '0' then v.ddrcfg.memcmd := "00"; v.apbstate := idle; end if;
-- Refresh or Precharge from APB BUS
when cmd =>
if v.mainstate = idle then v.ddrcfg.memcmd := fromAPB2Main.ddrcfg_reg(28 downto 27); end if;
v.apbstate := cmdDone;
-- Wait until no more cmd can arrive from AHB ctrl
when wait_lmr1 => v.apbstate := wait_lmr2;
when wait_lmr2 => v.apbstate := cmdlmr;
when cmdlmr =>
-- Check that no new R/W cmd is to be performed
if fromAHB2Main(0).rw_cmd_valid = v.rw_cmd_done(0) and
fromAHB2Main(1).rw_cmd_valid = v.rw_cmd_done(1) and v.mainstate = idle then
v.ddrcfg.memcmd := "11";
v.ddrcfg.cas := fromAPB2Main.ddrcfg_reg(30 downto 29);
v.ddrcfg.bl := fromAPB2Main.ddrcfg_reg(26 downto 25);
v.apbstate := cmdDone;
end if;
when cmdDone =>
v.lockAHB := "00";
if v.memCmdDone = '1' then
v.ddrcfg.memcmd := "00"; v.apb_cmd_done := '1'; v.apbstate := cmdDone2;
end if;
when cmdDone2 =>
if fromAPB2Main.ddrcfg_reg(28 downto 27) = "00" then
v.apb_cmd_done := '0'; v.apbstate := idle;
end if;
end case;
if v.mainstate = idle then
v.ddrcfg.refresh := fromAPB2Main.ddrcfg_reg(31);
v.ddrcfg.autopre := fromAPB2Main.ddrcfg_reg(24);
v.ddrcfg.r_predict := fromAPB2Main.ddrcfg_reg(23 downto 22);
v.ddrcfg.w_prot := fromAPB2Main.ddrcfg_reg(21 downto 20);
v.ddrcfg.ready := fromAPB2Main.ddrcfg_reg(0);
end if;
-------------------------------------------------------------------------------
-- Calcualtes burst length
case v.ddrcfg.bl is
when "00" => v.burstlength := 2;
when "01" => v.burstlength := 4;
when "10" => v.burstlength := 8;
when others => v.burstlength := 8;
end case;
-------------------------------------------------------------------------------
-- Calculates row and column address
v.tmpcoladdress := (others => (others => '0'));
v.rowaddress := (others => (others => '0'));
v.coladdress := (others => (others => '0'));
v.tmpcolbits := 0; v.colbits := 0; v.rowbits := 0;
-- Based on the size of the chip its organization can be calculated
case chipsize is
when 64 => v.tmpcolbits := 10; v.rowbits := 12; v.refreshTime := DELAY_15600NS; v.maxRefreshTime := DELAY_7_15600NS; -- 64Mbit
when 128 => v.tmpcolbits := 11; v.rowbits := 12; v.refreshTime := DELAY_15600NS; v.maxRefreshTime := DELAY_7_15600NS; -- 128Mbit
when 256 => v.tmpcolbits := 11; v.rowbits := 13; v.refreshTime := DELAY_7800NS; v.maxRefreshTime := DELAY_7_7800NS; -- 256Mbit
when 512 => v.tmpcolbits := 12; v.rowbits := 13; v.refreshTime := DELAY_7800NS; v.maxRefreshTime := DELAY_7_7800NS; -- 512Mbit
when 1024 => v.tmpcolbits := 12; v.rowbits := 14; v.refreshTime := DELAY_7800NS; v.maxRefreshTime := DELAY_7_7800NS; -- 1Gbit
when others => v.tmpcolbits := 10; v.rowbits := 12; v.refreshTime := DELAY_7800NS; v.maxRefreshTime := DELAY_7_7800NS; -- Others 64Mbit
end case;
case chipbits is
when 4 => v.colbits := v.tmpcolbits; -- x4 bits
when 8 => v.colbits := (v.tmpcolbits-1); -- x8 bits
when 16 => v.colbits := (v.tmpcolbits-2); -- x16 bits
when others => null;
end case;
v.addressrange := v.colbits + v.rowbits;
-- AHB controller 1 --
for i in 0 to ahbadr loop
if (i < v.colbits) then
v.tmpcoladdress(0)(i) := fromAHB(0).asramso.dataout(i); end if;
if (i < (v.addressrange) and i >= v.colbits) then
v.rowaddress(0)(i-v.colbits) := fromAHB(0).asramso.dataout(i); end if;
if (i < (v.addressrange+2) and i >= v.addressrange) then
v.intbankbits(0)(i - v.addressrange) := fromAHB(0).asramso.dataout(i); end if;
end loop;
-- Inserts bank address and auto precharge bit as A10
v.coladdress(0)(adrbits-1 downto 0) := v.intbankbits(0) &
v.tmpcoladdress(0)(12 downto 10) & -- Bit 13 to 11
v.ddrcfg.autopre & -- Bit 10
v.tmpcoladdress(0)(9 downto 0); --Bit 9 to 0
v.rowaddress(0)(adrbits-1 downto (adrbits-2)) := v.intbankbits(0);
-- Calculate total numer of useable address bits
if modbanks = 2 then
-- Calculate memory module bank (CS signals)
if fromAHB(0).asramso.dataout(v.addressrange +2) = '0' then
v.bankselect(0) := BANK0;
else
v.bankselect(0) := BANK1;
end if;
else
v.bankselect(0) := BANK0;
end if;
-- This is for keeping track of which banks has a active row
v.pre_bankadr(0):= conv_integer(v.bankselect(0)(0) & v.rowaddress(0)(adrbits-1 downto (adrbits-2)));
-- AHB Controller 2 --
for i in 0 to ahbadr loop
if (i < v.colbits) then
v.tmpcoladdress(1)(i) := fromAHB(1).asramso.dataout(i); end if;
if (i < (v.addressrange) and i >= v.colbits) then
v.rowaddress(1)(i-v.colbits) := fromAHB(1).asramso.dataout(i); end if;
if (i < (v.addressrange+2) and i >= v.addressrange) then
v.intbankbits(1)(i - v.addressrange) := fromAHB(1).asramso.dataout(i); end if;
end loop;
-- Inserts bank address and auto precharge bit as A10
v.coladdress(1)(adrbits-1 downto 0) := v.intbankbits(1) &
v.tmpcoladdress(1)(12 downto 10) & -- Bit 13 to 11
v.ddrcfg.autopre & -- Bit 10
v.tmpcoladdress(1)(9 downto 0); --Bit 9 to 0
v.rowaddress(1)(adrbits-1 downto (adrbits-2)) := v.intbankbits(1);
-- Calculate total numer of useable address bits
if modbanks = 2 then
-- Calculate memory module bank (CS signals)
if fromAHB(1).asramso.dataout(v.addressrange +2) = '0' then
v.bankselect(1) := BANK0;
else
v.bankselect(1) := BANK1;
end if;
else
v.bankselect(1) := BANK0;
end if;
-- This is for keeping track of which banks has a active row
v.pre_bankadr(1):= conv_integer(v.bankselect(1)(0) & v.rowaddress(1)(adrbits-1 downto (adrbits-2)));
-- ((1bit(Lower/upper half if 32 bit mode))) + 1bit(module bank select) +
-- 2bits(Chip bank selekt) + Xbits(address, depending on chip size)
-------------------------------------------------------------------------------
-- Calculate LMR command address
v.lmradr(adrbits-1 downto 7) := (others => '0');
-- CAS value
case v.ddrcfg.cas is
when "00" => v.lmradr(6 downto 4) := "010";
when "01" => v.lmradr(6 downto 4) := "110";
when "10" => v.lmradr(6 downto 4) := "011";
when others => v.lmradr(6 downto 4) := "010";
end case;
-- Burst type, seqencial or interleaved (fixed att seqencial)
v.lmradr(3) := '0';
-- Burst length
case v.ddrcfg.bl is
when "00" => v.lmradr(2 downto 0) := "001";
when "01" => v.lmradr(2 downto 0) := "010";
when "10" => v.lmradr(2 downto 0) := "011";
when others => v.lmradr(2 downto 0) := "010";
end case;
-------------------------------------------------------------------------------
-- Auto refresh timer
case v.timerstate is
when t1 =>
v.doRefresh := '0'; v.refreshcnt := v.refreshTime; v.timerstate := t2;
when t2 =>
v.doRefresh := '0'; v.refreshcnt := mainr.refreshcnt -1;
if v.refreshcnt < 50 then v.timerstate := t3; end if;
when t3 =>
if mainr.refreshcnt > 1 then v.refreshcnt := mainr.refreshcnt -1; end if;
v.doRefresh := '1';
if v.refreshDone = '1' then
v.refreshcnt := mainr.refreshcnt + v.refreshTime;
v.timerstate := t4;
end if;
when t4 =>
v.doRefresh := '0'; v.timerstate := t2; when others => null;
end case;
-------------------------------------------------------------------------------
-- Init statemachine
case v.initstate is
when idle =>
v.memInitDone := '0';
if v.doMemInit = '1' then
if plldelay = 1 then
-- Using refrshtimer for initial wait
v.refreshcnt := DELAY_200US +50; v.timerstate := t2; v.initstate := i1;
else v.initstate := i2; end if;
end if;
when i1 =>
if v.doRefresh = '1' then v.initstate := i2; end if;
when i2 =>
v.cs := "00";
if fromHS.hs_busy = '0' then
v.cmdbufferdata := CMD_NOP; v.loadcmdbuffer := '1'; v.initstate := i3;
end if;
when i3 =>
if fromHS.hs_busy = '0' then
v.cmdbufferdata := CMD_PRE; v.loadcmdbuffer := '1';
v.adrbufferdata(10) := '1'; v.initstate := i4;
end if;
when i4 =>
if fromHS.hs_busy = '0' then
v.cmdbufferdata := CMD_LMR; v.loadcmdbuffer := '1';
v.adrbufferdata(adrbits-1 downto (adrbits-2)) := "01";
v.adrbufferdata((adrbits -3) downto 0) := (others => '0');
v.initstate := i5;
end if;
when i5 =>
if fromHS.hs_busy = '0' then
v.cmdbufferdata := CMD_LMR; v.loadcmdbuffer := '1'; v.adrbufferdata := v.lmradr;
v.refreshcnt := 250; v.timerstate := t2; --200 cycle count
v.adrbufferdata(8) := '1'; v.initstate := i6;
end if;
when i6 =>
if fromHS.hs_busy = '0' then
v.cmdbufferdata := CMD_PRE; v.loadcmdbuffer := '1';
v.adrbufferdata(10) := '1'; v.initstate := i7;
end if;
when i7 =>
if fromHS.hs_busy = '0' then
v.cmdbufferdata := CMD_AR; v.loadcmdbuffer := '1'; v.initstate := i8;
end if;
when i8 =>
if fromHS.hs_busy = '0' then
v.cmdbufferdata := CMD_AR; v.loadcmdbuffer := '1'; v.initstate := i9;
end if;
when i9 =>
if fromHS.hs_busy = '0' then
v.cmdbufferdata := CMD_LMR; v.loadcmdbuffer := '1'; v.adrbufferdata := v.lmradr;
v.initstate := i10;
end if;
when i10 =>
if v.doRefresh = '1' then v.initstate := i11; end if;
when i11 =>
v.memInitDone := '1';
if v.doMemInit = '0' then v.initstate := idle; end if;
when others => null;
end case;
-------------------------------------------------------------------------------
-- Main controller statemachine
case v.mainstate is
-- Initialize memory
when init =>
v.doMemInit := '1';
v.ready := '0';
if v.memInitDone = '1' then
v.mainstate := idle;
end if;
-- Await command
when idle =>
v.doMemInit := '0';
v.RefreshDone := '0';
v.memCmdDone := '0';
v.ready := '1';
v.use_bl := mainr.burstlength;
v.use_cas := mainr.ddrcfg.cas;
if v.ddrcfg.memcmd /= "00" then
v.mainstate := c1;
elsif fromAHB2Main(0).rw_cmd_valid /= v.rw_cmd_done(0) or
fromAHB2Main(1).rw_cmd_valid /= v.rw_cmd_done(1) then
-- This code is to add read priority between the ahb controllers
-- if fromAHB2Main(0).rw_cmd_valid /= v.rw_cmd_done(0) and
-- fromAHB(0).asramso.dataout(ahbadr) = '0' then
-- v.use_ahb := 0;
-- v.use_buf := v.rw_cmd_done(0)+1;
-- elsif fromAHB2Main(1).rw_cmd_valid /= v.rw_cmd_done(1) and
-- fromAHB(1).asramso.dataout(ahbadr) = '0' then
-- v.use_ahb := 1;
-- v.use_buf := v.rw_cmd_done(1)+1;
if fromAHB2Main(0).rw_cmd_valid /= v.rw_cmd_done(0) then
v.use_ahb := 0;
v.use_buf := v.rw_cmd_done(0)+1;
else
v.use_ahb := 1;
v.use_buf := v.rw_cmd_done(1)+1;
end if;
-- Check if the chip bank which is to be R/W has a row open
if mainr.pre_chg(v.pre_bankadr(v.use_ahb)) = '1' then
-- Check if the row which is open is the same that will be R/W
if mainr.pre_row(v.pre_bankadr(v.use_ahb)) = v.rowaddress(v.use_ahb) then
v.mainstate := rw;
-- R/W to a different row then the one open, has to precharge and
-- activate new row
else
v.mainstate := pre1;
end if;
-- No row open, has to activate row
else
v.mainstate := act1;
end if;
end if;
-- Nothing to do, if 10 idle cycles, run Refreash (if needed)
if v.idlecnt = 10 and v.refreshcnt < v.maxRefreshTime then
v.doRefresh := '1';
v.idlecnt := 0;
v.timerstate := t3;
v.refreshcnt := mainr.refreshcnt + v.refreshTime;
elsif v.idlecnt = 10 then
v.idlecnt := 0;
else
v.idlecnt := mainr.idlecnt + 1;
end if;
-- Precharge memory
when pre1 =>
if fromHS.hs_busy = '0' then
v.cs := v.bankselect(mainr.use_ahb);
-- Select chip bank to precharge
v.adrbufferdata := (others => '0');
v.adrbufferdata(adrbits-1 downto (adrbits-2)) := v.rowaddress(mainr.use_ahb)(adrbits-1 downto (adrbits-2));
v.cmdbufferdata := CMD_PRE;
-- Clear bit in register for active rows
v.pre_chg(v.pre_bankadr(mainr.use_ahb)):= '0';
v.loadcmdbuffer := '1';
v.mainstate := act1;
end if;
-- Activate row in memory
when act1 => -- Get adr and cmd from AHB, set to HS
if fromHS.hs_busy = '0' then
v.cs := v.bankselect(mainr.use_ahb);
v.cmdbufferdata := CMD_ACTIVE;
v.adrbufferdata := v.rowaddress(mainr.use_ahb);
v.loadcmdbuffer := '1';
-- Set bit in register for active row if auto-precharge is disabled
if v.ddrcfg.autopre = '0' then
v.pre_chg(v.pre_bankadr(mainr.use_ahb)) := '1';
v.pre_row(v.pre_bankadr(mainr.use_ahb)) := v.rowaddress(mainr.use_ahb);
end if;
v.mainstate := rw;
end if;
-- Issu read or write to HS part
when rw =>
if fromAHB(mainr.use_ahb).asramso.dataout(ahbadr) = '1' then
v.cmdbufferdata := CMD_WRITE;
else
v.cmdbufferdata := CMD_READ;
end if;
if v.ddrcfg.autopre = '1' then
v.pre_chg(v.pre_bankadr(mainr.use_ahb)) := '0';
end if;
v.adrbufferdata := v.coladdress(mainr.use_ahb);
v.cs := v.bankselect(mainr.use_ahb);
v.idlecnt := 0;
if fromHS.hs_busy = '0' then
if fromAHB2Main(mainr.use_ahb).w_data_valid /= v.rw_cmd_done(mainr.use_ahb) then
v.loadcmdbuffer := '1';
v.rw_cmd_done(mainr.use_ahb) := v.rw_cmd_done(mainr.use_ahb)+1;
v.sync2_adr(mainr.use_ahb) := v.rw_cmd_done(mainr.use_ahb)+1;
v.mainstate := idle;
end if;
end if;
-- Issue prechare, auto refresh or LMR to HS part
when c1 =>
v.idlecnt := 0;
if fromHS.hs_busy = '0' then
v.cs := BANK01;
case v.ddrcfg.memCmd is
when "01" => -- Precharge all
v.cmdbufferdata := CMD_PRE;
v.adrbufferdata(10) := '1';
v.pre_chg := (others => '0');
v.memCmdDone := '1';
v.mainstate := c2;
when "10" => -- AutoRefresh
-- All banks have to be precharged before AR
if v.pre_chg = "00000000" then
v.cmdbufferdata := CMD_AR;
v.memCmdDone := '1';
v.mainstate := c2;
v.refreshDone := '1';
else -- Run Precharge, and let AR begin when finished
v.cmdbufferdata := CMD_PRE;
v.adrbufferdata(10) := '1';
v.pre_chg := (others => '0');
v.mainstate := idle;
end if;
when "11" => -- LMR
-- All banks have to be precharged before LMR
if v.pre_chg = "00000000" then
v.cmdbufferdata := CMD_LMR;
v.adrbufferdata := v.lmradr;
v.memCmdDone := '1';
v.mainstate := c2;
else
v.cmdbufferdata := CMD_PRE;
v.adrbufferdata(10) := '1';
v.pre_chg := (others => '0');
v.mainstate := idle;
end if;
when others => null;
end case;
v.loadcmdbuffer := '1';
end if;
when c2 =>
if v.ddrcfg.memCmd = "00" then
v.refreshDone := '0';
v.mainstate := idle;
end if;
when others =>
v.mainstate := init;
end case;
-- Reset
if rst = '0' then
-- Main controller
v.mainstate := init;
v.loadcmdbuffer := '0';
v.cmdbufferdata := CMD_NOP;
v.adrbufferdata := (others => '0');
v.use_ahb := 0;
v.use_bl := 4;
v.use_cas := "00";
v.use_buf := (others => '1');
v.burstlength := 8;
v.rw_cmd_done := (others => (others => '1'));
v.lmradr := (others => '0');
v.memCmdDone := '0';
v.lockAHB := "00";
v.pre_row := (others => (others => '0'));
v.pre_chg := (others => '0');
v.pre_bankadr := (0,0);
v.sync2_adr := (others =>(others => '0'));
-- For init statemachine
v.initstate := idle;
v.doMemInit := '0';
v.memInitDone := '0';
v.initDelay := 0;
v.cs := "11";
-- For address calculator
v.coladdress := (others => (others => '0'));
v.tmpcoladdress := (others => (others => '0'));
v.rowaddress := (others => (others => '0'));
v.addressrange := 0;
v.tmpcolbits := 0;
v.colbits := 0;
v.rowbits := 0;
v.bankselect := ("11","11");
v.intbankbits := ("00","00");
-- For refresh timer statemachine
v.timerstate := t2;
v.doRefresh := '0';
v.refreshDone := '0';
v.refreshTime := 0;
v.maxRefreshTime := 0;
v.idlecnt := 0;
v.refreshcnt := DELAY_200us;
-- For DDRCFG register
v.apbstate := idle;
v.apb_cmd_done := '0';
v.ready := '0';
v.ddrcfg := (ddrcfg_reset(31),ddrcfg_reset(30 downto 29),ddrcfg_reset(28 downto 27),
ddrcfg_reset(26 downto 25),ddrcfg_reset(24),ddrcfg_reset(23 downto 22),
ddrcfg_reset(21 downto 20),'0');
end if;
-- Set output signals
mainri <= v;
fromMain.hssi.bl <= v.use_bl;
fromMain.hssi.ml <= fromAHB(mainr.use_ahb).burst_dm(conv_integer(mainr.use_buf));
fromMain.hssi.cas <= v.use_cas;
fromMain.hssi.buf <= v.use_buf;
fromMain.hssi.ahb <= v.use_ahb;
fromMain.hssi.cs <= v.cs;
fromMain.hssi.cmd <= v.cmdbufferdata;
fromMain.hssi.cmd_valid <= v.loadcmdbuffer;
fromMain.hssi.adr <= v.adrbufferdata;
fromMain.ahbctrlsi(0).burstlength <= v.burstlength;
fromMain.ahbctrlsi(1).burstlength <= v.burstlength;
fromMain.ahbctrlsi(0).r_predict <= v.ddrcfg.r_predict(0);
fromMain.ahbctrlsi(1).r_predict <= v.ddrcfg.r_predict(1);
fromMain.ahbctrlsi(0).w_prot <= v.ddrcfg.w_prot(0);
fromMain.ahbctrlsi(1).w_prot <= v.ddrcfg.w_prot(1);
fromMain.ahbctrlsi(0).locked <= v.lockAHB(0);
fromMain.ahbctrlsi(1).locked <= v.lockAHB(1);
fromMain.ahbctrlsi(0).asramsi.raddress <= v.sync2_adr(0);
fromMain.ahbctrlsi(1).asramsi.raddress <= v.sync2_adr(1);
fromMain.apbctrlsi.apb_cmd_done <= v.apb_cmd_done;
fromMain.apbctrlsi.ready <= v.ready;
end process;
--Main clocked register
mainclk : process(clk0)
begin
if rising_edge(clk0) then
mainr <= mainri;
-- Register to sync between different clock domains
fromAPB2Main.ddrcfg_reg <= fromAPB.ddrcfg_reg;
-- Makes signals from main to AHB, ABP, HS registerd
fromMain2AHB <= fromMain.ahbctrlsi;
fromMain2APB <= fromMain.apbctrlsi;
fromMain2HS <= fromMain.hssi;
end if;
end process;
-- Sync of incoming data valid signals from AHB
-- Either if separate clock domains or if syncram_2p
-- doesn't support write through (write first)
a1rt : if ahb1sepclk = 1 or syncram_2p_write_through(tech) = 0 generate
regip1 : process(clk0)
begin
if rising_edge(clk0) then
fromAHB2Main(0).rw_cmd_valid <= fromAHB(0).rw_cmd_valid;
fromAHB2Main(0).w_data_valid <= fromAHB(0).w_data_valid;
end if;
end process;
end generate;
arf : if not (ahb1sepclk = 1 or syncram_2p_write_through(tech) = 0) generate
fromAHB2Main(0).rw_cmd_valid <= fromAHB(0).rw_cmd_valid;
fromAHB2Main(0).w_data_valid <= fromAHB(0).w_data_valid;
end generate;
a2rt : if ahb2sepclk = 1 or syncram_2p_write_through(tech) = 0 generate
regip2 : process(clk0)
begin
if rising_edge(clk0) then
fromAHB2Main(1).rw_cmd_valid <= fromAHB(1).rw_cmd_valid;
fromAHB2Main(1).w_data_valid <= fromAHB(1).w_data_valid;
end if;
end process;
end generate;
a2rf : if not (ahb1sepclk = 1 or syncram_2p_write_through(tech) = 0) generate
fromAHB2Main(1).rw_cmd_valid <= fromAHB(1).rw_cmd_valid;
fromAHB2Main(1).w_data_valid <= fromAHB(1).w_data_valid;
end generate;
-------------------------------------------------------------------------------
-- High speed interface (Physical layer towards memory)
-------------------------------------------------------------------------------
D0 : hs
generic map(
tech => tech,
dqsize => dqsize,
dmsize => dmsize,
strobesize => strobesize,
clkperiod => clkperiod)
port map(
rst => rst,
clk0 => clk0,
clk90 => clk90,
clk180 => clk180,
clk270 => clk270,
hclk => pclk,
hssi => toHS,
hsso => fromHS);
A0 : ahb_slv
generic map(
hindex => hindex1,
haddr => haddr1,
hmask => hmask1,
sepclk => ahb1sepclk,
dqsize => dqsize,
dmsize => dmsize,
tech => tech)
port map (
rst => rst,
hclk => hclk1,
clk0 => clk0,
csi => toAHB(0),
cso => fromAHB(0));
B1: if numahb = 2 generate
A1 : ahb_slv
generic map(
hindex => hindex2,
haddr => haddr2,
hmask => hmask2,
sepclk => ahb2sepclk,
dqsize => dqsize,
dmsize => dmsize)
port map (
rst => rst,
hclk => hclk2,
clk0 => clk0,
csi => toAHB(1),
cso => fromAHB(1));
end generate;
B2 : if numahb /= 2 generate
fromAHB(1).rw_cmd_valid <= (others => '1');
end generate;
-------------------------------------------------------------------------------
-- Mapping signals
-- Signals to HS
toHS.bl <= fromMain.hssi.bl;
toHS.ml <= fromMain.hssi.ml;
toHS.cas <= fromMain.hssi.cas;
toHS.buf <= fromMain.hssi.buf;
toHS.ahb <= fromMain.hssi.ahb;
toHS.cs <= fromMain.hssi.cs;
toHS.adr <= fromMain.hssi.adr;
toHS.cmd <= fromMain.hssi.cmd;
toHS.cmd_valid <= fromMain.hssi.cmd_valid;
toHS.dsramso(0) <= fromAHB(0).dsramso;
toHS.dsramso(1) <= fromAHB(1).dsramso;
toHS.ddso <= ddso;
-- Signals to AHB ctrl 1
toAHB(0).ahbsi <= ahb1si;
toAHB(0).asramsi <= fromMain.ahbctrlsi(0).asramsi;
toAHB(0).dsramsi <= fromHS.dsramsi(0);
toAHB(0).burstlength <= fromMain2AHB(0).burstlength;
toAHB(0).r_predict <= fromMain2AHB(0).r_predict;
toAHB(0).w_prot <= fromMain2AHB(0).w_prot;
toAHB(0).locked <= fromMain2AHB(0).locked;
toAHB(0).rw_cmd_done <= fromHS.cmdDone(0);
-- Signals to AHB ctrl 2
toAHB(1).ahbsi <= ahb2si;
toAHB(1).asramsi <= fromMain.ahbctrlsi(1).asramsi;
toAHB(1).dsramsi <= fromHS.dsramsi(1);
toAHB(1).burstlength <= fromMain2AHB(1).burstlength;
toAHB(1).r_predict <= fromMain2AHB(1).r_predict;
toAHB(1).w_prot <= fromMain2AHB(1).w_prot;
toAHB(1).locked <= fromMain2AHB(1).locked;
toAHB(1).rw_cmd_done <= fromHS.cmdDone(1);
-- Ouput signals
ahb1so <= fromAHB(0).ahbso;
ahb2so <= fromAHB(1).ahbso;
ddsi <= fromHS.ddsi;
end rtl;
| mit | a029355eefabca3b6a30c17612a5000c | 0.512407 | 3.496441 | false | false | false | false |
impedimentToProgress/UCI-BlueChip | AttackFiles/Attacks/privEsc/lib/gaisler/greth/ethernet_mac.vhd | 2 | 6,371 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library gaisler;
use gaisler.net.all;
library grlib;
use grlib.amba.all;
library techmap;
use techmap.gencomp.all;
package ethernet_mac is
type eth_tx_in_type is record
start : std_ulogic;
valid : std_ulogic;
data : std_logic_vector(31 downto 0);
full_duplex : std_ulogic;
length : std_logic_vector(10 downto 0);
col : std_ulogic;
crs : std_ulogic;
read_ack : std_ulogic;
end record;
type eth_tx_out_type is record
status : std_logic_vector(1 downto 0);
done : std_ulogic;
restart : std_ulogic;
read : std_ulogic;
tx_er : std_ulogic;
tx_en : std_ulogic;
txd : std_logic_vector(3 downto 0);
end record;
type eth_rx_in_type is record
writeok : std_ulogic;
rxen : std_ulogic;
rx_dv : std_ulogic;
rx_er : std_ulogic;
rxd : std_logic_vector(3 downto 0);
done_ack : std_ulogic;
write_ack : std_ulogic;
end record;
type eth_rx_out_type is record
write : std_ulogic;
data : std_logic_vector(31 downto 0);
done : std_ulogic;
length : std_logic_vector(10 downto 0);
status : std_logic_vector(2 downto 0);
start : std_ulogic;
end record;
type eth_mdio_in_type is record
mdioi : std_ulogic;
write : std_ulogic;
read : std_ulogic;
mdiostart : std_ulogic;
regadr : std_logic_vector(4 downto 0);
phyadr : std_logic_vector(4 downto 0);
data : std_logic_vector(15 downto 0);
end record;
type eth_mdio_out_type is record
mdc : std_ulogic;
mdioo : std_ulogic;
mdioen : std_ulogic;
data : std_logic_vector(15 downto 0);
done : std_ulogic;
error : std_ulogic;
end record;
type eth_tx_ahb_in_type is record
req : std_ulogic;
write : std_ulogic;
addr : std_logic_vector(31 downto 0);
data : std_logic_vector(31 downto 0);
end record;
type eth_tx_ahb_out_type is record
grant : std_ulogic;
data : std_logic_vector(31 downto 0);
ready : std_ulogic;
error : std_ulogic;
retry : std_ulogic;
end record;
type eth_rx_ahb_in_type is record
req : std_ulogic;
write : std_ulogic;
addr : std_logic_vector(31 downto 0);
data : std_logic_vector(31 downto 0);
end record;
type eth_rx_ahb_out_type is record
grant : std_ulogic;
ready : std_ulogic;
error : std_ulogic;
retry : std_ulogic;
data : std_logic_vector(31 downto 0);
end record;
type eth_rx_gbit_ahb_in_type is record
req : std_ulogic;
write : std_ulogic;
addr : std_logic_vector(31 downto 0);
data : std_logic_vector(31 downto 0);
size : std_logic_vector(1 downto 0);
end record;
component eth_ahb_mst is
generic(
hindex : integer := 0;
revision : integer := 0;
irq : integer := 0);
port(
rst : in std_ulogic;
clk : in std_ulogic;
ahbmi : in ahb_mst_in_type;
ahbmo : out ahb_mst_out_type;
tmsti : in eth_tx_ahb_in_type;
tmsto : out eth_tx_ahb_out_type;
rmsti : in eth_rx_ahb_in_type;
rmsto : out eth_rx_ahb_out_type
);
end component;
component eth_ahb_mst_gbit is
generic(
hindex : integer := 0;
revision : integer := 0;
irq : integer := 0);
port(
rst : in std_ulogic;
clk : in std_ulogic;
ahbmi : in ahb_mst_in_type;
ahbmo : out ahb_mst_out_type;
tmsti : in eth_tx_ahb_in_type;
tmsto : out eth_tx_ahb_out_type;
rmsti : in eth_rx_gbit_ahb_in_type;
rmsto : out eth_rx_ahb_out_type
);
end component;
component greth is
generic(
hindex : integer := 0;
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#FFF#;
pirq : integer := 0;
memtech : integer := inferred;
ifg_gap : integer := 24;
attempt_limit : integer := 16;
backoff_limit : integer := 10;
slot_time : integer := 128;
mdcscaler : integer range 0 to 255 := 25;
enable_mdio : integer range 0 to 1 := 0;
fifosize : integer range 4 to 512 := 8;
nsync : integer range 1 to 2 := 2;
edcl : integer range 0 to 1 := 0;
edclbufsz : integer range 1 to 64 := 1;
macaddrh : integer := 16#00005E#;
macaddrl : integer := 16#000000#;
ipaddrh : integer := 16#c0a8#;
ipaddrl : integer := 16#0035#;
phyrstadr : integer := 0);
port(
rst : in std_ulogic;
clk : in std_ulogic;
ahbmi : in ahb_mst_in_type;
ahbmo : out ahb_mst_out_type;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
ethi : in eth_in_type;
etho : out eth_out_type
);
end component;
end package;
| mit | 6ee8934798cdeb15c730e64b0f44b8d5 | 0.533354 | 3.65729 | false | false | false | false |
impedimentToProgress/UCI-BlueChip | AttackFiles/Attacks/privEsc/lib/gaisler/leon3/cachemem.vhd | 2 | 18,464 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: cachemem
-- File: cachemem.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: Contains ram cells for both instruction and data caches
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library gaisler;
use gaisler.libiu.all;
use gaisler.libcache.all;
use gaisler.mmuconfig.all;
library grlib;
use grlib.stdlib.all;
library techmap;
use techmap.gencomp.all;
entity cachemem is
generic (
tech : integer range 0 to NTECH := 0;
icen : integer range 0 to 1 := 0;
irepl : integer range 0 to 2 := 0;
isets : integer range 1 to 4 := 1;
ilinesize : integer range 4 to 8 := 4;
isetsize : integer range 1 to 256 := 1;
isetlock : integer range 0 to 1 := 0;
dcen : integer range 0 to 1 := 0;
drepl : integer range 0 to 2 := 0;
dsets : integer range 1 to 4 := 1;
dlinesize : integer range 4 to 8 := 4;
dsetsize : integer range 1 to 256 := 1;
dsetlock : integer range 0 to 1 := 0;
dsnoop : integer range 0 to 6 := 0;
ilram : integer range 0 to 1 := 0;
ilramsize : integer range 1 to 512 := 1;
dlram : integer range 0 to 1 := 0;
dlramsize : integer range 1 to 512 := 1;
mmuen : integer range 0 to 1 := 0
);
port (
clk : in std_ulogic;
crami : in cram_in_type;
cramo : out cram_out_type;
sclk : in std_ulogic
);
end;
architecture rtl of cachemem is
constant DSNOOPMMU : boolean := (dsnoop > 3);
constant ILINE_BITS : integer := log2(ilinesize);
constant IOFFSET_BITS : integer := 8 +log2(isetsize) - ILINE_BITS;
constant DLINE_BITS : integer := log2(dlinesize);
constant DOFFSET_BITS : integer := 8 +log2(dsetsize) - DLINE_BITS;
constant ITAG_BITS : integer := TAG_HIGH - IOFFSET_BITS - ILINE_BITS - 2 + ilinesize + 1;
constant DTAG_BITS : integer := TAG_HIGH - DOFFSET_BITS - DLINE_BITS - 2 + dlinesize + 1;
constant IPTAG_BITS : integer := TAG_HIGH - IOFFSET_BITS - ILINE_BITS - 2 + 1;
constant DPTAG_BITS : integer := TAG_HIGH - DOFFSET_BITS - DLINE_BITS - 2 + 1;
constant ILRR_BIT : integer := creplalg_tbl(irepl);
constant DLRR_BIT : integer := creplalg_tbl(drepl);
constant ITAG_LOW : integer := IOFFSET_BITS + ILINE_BITS + 2;
constant DTAG_LOW : integer := DOFFSET_BITS + DLINE_BITS + 2;
constant ICLOCK_BIT : integer := isetlock;
constant DCLOCK_BIT : integer := dsetlock;
constant ILRAM_BITS : integer := log2(ilramsize) + 10;
constant DLRAM_BITS : integer := log2(dlramsize) + 10;
constant ITDEPTH : natural := 2**IOFFSET_BITS;
constant DTDEPTH : natural := 2**DOFFSET_BITS;
constant MMUCTX_BITS : natural := 8*mmuen;
-- i/d tag layout
-- +-----+----------+--------+-----+-------+
-- | LRR | LOCK_BIT | MMUCTX | TAG | VALID |
-- +-----+----------+--------+-----+-------+
constant ITWIDTH : natural := ITAG_BITS + ILRR_BIT + isetlock + MMUCTX_BITS;
constant DTWIDTH : natural := DTAG_BITS + DLRR_BIT + dsetlock + MMUCTX_BITS;
constant IDWIDTH : natural := 32;
constant DDWIDTH : natural := 32;
subtype dtdatain_vector is std_logic_vector(DTWIDTH downto 0);
type dtdatain_type is array (0 to MAXSETS-1) of dtdatain_vector;
subtype itdatain_vector is std_logic_vector(ITWIDTH downto 0);
type itdatain_type is array (0 to MAXSETS-1) of itdatain_vector;
subtype itdataout_vector is std_logic_vector(ITWIDTH-1 downto 0);
type itdataout_type is array (0 to MAXSETS-1) of itdataout_vector;
subtype iddataout_vector is std_logic_vector(IDWIDTH -1 downto 0);
type iddataout_type is array (0 to MAXSETS-1) of iddataout_vector;
subtype dtdataout_vector is std_logic_vector(DTWIDTH-1 downto 0);
type dtdataout_type is array (0 to MAXSETS-1) of dtdataout_vector;
subtype dddataout_vector is std_logic_vector(DDWIDTH -1 downto 0);
type dddataout_type is array (0 to MAXSETS-1) of dddataout_vector;
signal itaddr : std_logic_vector(IOFFSET_BITS + ILINE_BITS -1 downto ILINE_BITS);
signal idaddr : std_logic_vector(IOFFSET_BITS + ILINE_BITS -1 downto 0);
signal ildaddr : std_logic_vector(ILRAM_BITS-3 downto 0);
signal itdatain : itdatain_type;
signal itdataout : itdataout_type;
signal iddatain : std_logic_vector(IDWIDTH -1 downto 0);
signal iddataout : iddataout_type;
signal ildataout : std_logic_vector(31 downto 0);
signal itenable : std_ulogic;
signal idenable : std_ulogic;
signal itwrite : std_logic_vector(0 to MAXSETS-1);
signal idwrite : std_logic_vector(0 to MAXSETS-1);
signal dtaddr : std_logic_vector(DOFFSET_BITS + DLINE_BITS -1 downto DLINE_BITS);
signal dtaddr2 : std_logic_vector(DOFFSET_BITS + DLINE_BITS -1 downto DLINE_BITS);
signal ddaddr : std_logic_vector(DOFFSET_BITS + DLINE_BITS -1 downto 0);
signal ldaddr : std_logic_vector(DLRAM_BITS-1 downto 2);
signal dtdatain : dtdatain_type;
signal dtdatain2 : dtdatain_type;
signal dtdatain3 : dtdatain_type;
signal dtdatainu : dtdatain_type;
signal dtdataout : dtdataout_type;
signal dtdataout2: dtdataout_type;
signal dtdataout3: dtdataout_type;
signal dddatain : cdatatype;
signal dddataout : dddataout_type;
signal lddatain, ldataout : std_logic_vector(31 downto 0);
signal dtenable : std_logic_vector(0 to MAXSETS-1);
signal dtenable2 : std_logic_vector(0 to MAXSETS-1);
signal ddenable : std_logic_vector(0 to MAXSETS-1);
signal dtwrite : std_logic_vector(0 to MAXSETS-1);
signal dtwrite2 : std_logic_vector(0 to MAXSETS-1);
signal dtwrite3 : std_logic_vector(0 to MAXSETS-1);
signal ddwrite : std_logic_vector(0 to MAXSETS-1);
signal vcc, gnd : std_ulogic;
begin
vcc <= '1'; gnd <= '0';
itaddr <= crami.icramin.address(IOFFSET_BITS + ILINE_BITS -1 downto ILINE_BITS);
idaddr <= crami.icramin.address(IOFFSET_BITS + ILINE_BITS -1 downto 0);
ildaddr <= crami.icramin.address(ILRAM_BITS-3 downto 0);
itinsel : process(crami, dtdataout2, dtdataout3)
variable viddatain : std_logic_vector(IDWIDTH -1 downto 0);
variable vdddatain : cdatatype;
variable vitdatain : itdatain_type;
variable vdtdatain : dtdatain_type;
variable vdtdatain2 : dtdatain_type;
variable vdtdatain3 : dtdatain_type;
variable vdtdatainu : dtdatain_type;
begin
viddatain := (others => '0');
vdddatain := (others => (others => '0'));
viddatain(31 downto 0) := crami.icramin.data;
for i in 0 to DSETS-1 loop
vdtdatain(i) := (others => '0');
if mmuen = 1 then
vdtdatain(i)((DTWIDTH - (DLRR_BIT+dsetlock+1)) downto (DTWIDTH - (DLRR_BIT+dsetlock+M_CTX_SZ))) := crami.dcramin.ctx(i);
end if;
vdtdatain(i)(DTWIDTH-(DCLOCK_BIT + dsetlock)) := crami.dcramin.tag(i)(CTAG_LOCKPOS);
vdtdatain(i)(DTWIDTH-DLRR_BIT) := crami.dcramin.tag(i)(CTAG_LRRPOS);
vdtdatain(i)(DTAG_BITS-1 downto 0) := crami.dcramin.tag(i)(TAG_HIGH downto DTAG_LOW) & crami.dcramin.tag(i)(dlinesize-1 downto 0);
if (DSETS > 1) and (crami.dcramin.flush = '1') then
vdtdatain(i)(dlinesize+1 downto dlinesize) := conv_std_logic_vector(i,2);
end if;
end loop;
vdtdatain2 := (others => (others => '0'));
for i in 0 to DSETS-1 loop
if (DSETS > 1) then
vdtdatain2(i)(dlinesize+1 downto dlinesize) := conv_std_logic_vector(i,2);
end if;
end loop;
vdddatain := crami.dcramin.data;
vdtdatainu := (others => (others => '0'));
vdtdatain3 := (others => (others => '0'));
for i in 0 to DSETS-1 loop
vdtdatain3(i) := (others => '0');
vdtdatain3(i)(DTAG_BITS-1 downto DTAG_BITS-DPTAG_BITS) := crami.dcramin.ptag(i)(TAG_HIGH downto DTAG_LOW);
end loop;
for i in 0 to ISETS-1 loop
vitdatain(i) := (others => '0');
if mmuen = 1 then
vitdatain(i)((ITWIDTH - (ILRR_BIT+isetlock+1)) downto (ITWIDTH - (ILRR_BIT+isetlock+M_CTX_SZ))) := crami.icramin.ctx;
end if;
vitdatain(i)(ITWIDTH-(ICLOCK_BIT + isetlock)) := crami.icramin.tag(i)(CTAG_LOCKPOS);
vitdatain(i)(ITWIDTH-ILRR_BIT) := crami.icramin.tag(i)(CTAG_LRRPOS);
vitdatain(i)(ITAG_BITS-1 downto 0) := crami.icramin.tag(i)(TAG_HIGH downto ITAG_LOW) & crami.icramin.tag(i)(ilinesize-1 downto 0);
if (ISETS > 1) and (crami.icramin.flush = '1') then
vitdatain(i)(ilinesize+1 downto ilinesize) := conv_std_logic_vector(i,2);
end if;
end loop;
itdatain <= vitdatain; iddatain <= viddatain;
dtdatain <= vdtdatain; dtdatain2 <= vdtdatain2; dtdatain3 <= vdtdatain3; dtdatainu <= vdtdatainu; dddatain <= vdddatain;
end process;
itwrite <= crami.icramin.twrite;
idwrite <= crami.icramin.dwrite;
itenable <= crami.icramin.tenable;
idenable <= crami.icramin.denable;
dtaddr <= crami.dcramin.address(DOFFSET_BITS + DLINE_BITS -1 downto DLINE_BITS);
dtaddr2 <= crami.dcramin.saddress(DOFFSET_BITS-1 downto 0);
ddaddr <= crami.dcramin.address(DOFFSET_BITS + DLINE_BITS -1 downto 0);
ldaddr <= crami.dcramin.ldramin.address(DLRAM_BITS-1 downto 2);
dtwrite <= crami.dcramin.twrite;
dtwrite2 <= crami.dcramin.swrite;
dtwrite3 <= crami.dcramin.tpwrite;
ddwrite <= crami.dcramin.dwrite;
dtenable <= crami.dcramin.tenable;
dtenable2 <= crami.dcramin.senable;
ddenable <= crami.dcramin.denable;
ime : if icen = 1 generate
im0 : for i in 0 to ISETS-1 generate
itags0 : syncram generic map (tech, IOFFSET_BITS, ITWIDTH)
port map ( clk, itaddr, itdatain(i)(ITWIDTH-1 downto 0), itdataout(i)(ITWIDTH-1 downto 0), itenable, itwrite(i));
idata0 : syncram generic map (tech, IOFFSET_BITS+ILINE_BITS, IDWIDTH)
port map (clk, idaddr, iddatain, iddataout(i), idenable, idwrite(i));
end generate;
ind0 : for i in ISETS to MAXSETS-1 generate
itdataout(i) <= (others => '0');
iddataout(i) <= (others => '0');
end generate;
end generate;
imd : if icen = 0 generate
ind0 : for i in 0 to ISETS-1 generate
itdataout(i) <= (others => '0');
iddataout(i) <= (others => '0');
end generate;
end generate;
ild0 : if ilram = 1 generate
ildata0 : syncram
generic map (tech, ILRAM_BITS-2, 32)
port map (clk, ildaddr, iddatain, ildataout,
crami.icramin.ldramin.enable, crami.icramin.ldramin.write);
end generate;
dme : if dcen = 1 generate
dtags0 : if DSNOOP = 0 generate
dt0 : for i in 0 to DSETS-1 generate
dtags0 : syncram
generic map (tech, DOFFSET_BITS, DTWIDTH)
port map (clk, dtaddr, dtdatain(i)(DTWIDTH-1 downto 0),
dtdataout(i)(DTWIDTH-1 downto 0), dtenable(i), dtwrite(i));
end generate;
end generate;
dtags1 : if DSNOOP /= 0 generate
dt1 : if ((MMUEN = 0) or not DSNOOPMMU) generate
dt0 : for i in 0 to DSETS-1 generate
dtags0 : syncram_dp
generic map (tech, DOFFSET_BITS, DTWIDTH) port map (
clk, dtaddr, dtdatain(i)(DTWIDTH-1 downto 0),
dtdataout(i)(DTWIDTH-1 downto 0), dtenable(i), dtwrite(i),
sclk, dtaddr2, dtdatain2(i)(DTWIDTH-1 downto 0),
dtdataout2(i)(DTWIDTH-1 downto 0), dtenable2(i), dtwrite2(i));
end generate;
end generate;
mdt1 : if not ((MMUEN = 0) or not DSNOOPMMU) generate
dt0 : for i in 0 to DSETS-1 generate
dtags0 : syncram_dp
generic map (tech, DOFFSET_BITS, DTWIDTH) port map (
clk, dtaddr, dtdatain(i)(DTWIDTH-1 downto 0),
dtdataout(i)(DTWIDTH-1 downto 0), dtenable(i), dtwrite(i),
sclk, dtaddr2, dtdatain2(i)(DTWIDTH-1 downto 0),
dtdataout2(i)(DTWIDTH-1 downto 0), dtenable2(i), dtwrite2(i));
dtags1 : syncram_dp
generic map (tech, DOFFSET_BITS, DPTAG_BITS) port map (
clk, dtaddr, dtdatain3(i)(DTAG_BITS-1 downto DTAG_BITS-DPTAG_BITS),
open, dtwrite3(i), dtwrite3(i),
sclk, dtaddr2, dtdatainu(i)(DTAG_BITS-1 downto DTAG_BITS-DPTAG_BITS),
dtdataout3(i)(DTAG_BITS-1 downto DTAG_BITS-DPTAG_BITS), dtenable2(i), dtwrite2(i));
end generate;
end generate;
end generate;
nodtags1 : if DSNOOP = 0 generate
dt0 : for i in 0 to DSETS-1 generate
dtdataout2(i)(DTWIDTH-1 downto 0) <= zero64(DTWIDTH-1 downto 0);
dtdataout3(i)(DTWIDTH-1 downto 0) <= zero64(DTWIDTH-1 downto 0);
end generate;
end generate;
dd0 : for i in 0 to DSETS-1 generate
ddata0 : syncram
generic map (tech, DOFFSET_BITS+DLINE_BITS, DDWIDTH)
port map (clk, ddaddr, dddatain(i), dddataout(i), ddenable(i), ddwrite(i));
end generate;
dnd0 : for i in DSETS to MAXSETS-1 generate
dtdataout(i) <= (others => '0');
dtdataout2(i) <= (others => '0');
dtdataout3(i) <= (others => '0');
dddataout(i) <= (others => '0');
end generate;
end generate;
dmd : if dcen = 0 generate
dnd0 : for i in 0 to DSETS-1 generate
dtdataout(i) <= (others => '0');
dtdataout2(i) <= (others => '0');
dtdataout3(i) <= (others => '0');
dddataout(i) <= (others => '0');
end generate;
end generate;
ldxs0 : if not ((dlram = 1) and (DSETS > 1)) generate
lddatain <= dddatain(0);
end generate;
ldxs1 : if (dlram = 1) and (DSETS > 1) generate
lddatain <= dddatain(1);
end generate;
ld0 : if dlram = 1 generate
ldata0 : syncram
generic map (tech, DLRAM_BITS-2, 32)
port map (clk, ldaddr, lddatain, ldataout, crami.dcramin.ldramin.enable,
crami.dcramin.ldramin.write);
end generate;
itx : for i in 0 to ISETS-1 generate
cramo.icramo.tag(i)(TAG_HIGH downto ITAG_LOW) <= itdataout(i)(ITAG_BITS-1 downto (ITAG_BITS-1) - (TAG_HIGH - ITAG_LOW));
--(ITWIDTH-1-(ILRR_BIT+ICLOCK_BIT) downto ITWIDTH-(TAG_HIGH-ITAG_LOW)-(ILRR_BIT+ICLOCK_BIT)-1);
cramo.icramo.tag(i)(ilinesize-1 downto 0) <= itdataout(i)(ilinesize-1 downto 0);
cramo.icramo.tag(i)(CTAG_LRRPOS) <= itdataout(i)(ITWIDTH - (1+ICLOCK_BIT));
cramo.icramo.tag(i)(CTAG_LOCKPOS) <= itdataout(i)(ITWIDTH-1);
ictx : if mmuen = 1 generate
cramo.icramo.ctx(i) <= itdataout(i)((ITWIDTH - (ILRR_BIT+ICLOCK_BIT+1)) downto (ITWIDTH - (ILRR_BIT+ICLOCK_BIT+M_CTX_SZ)));
end generate;
cramo.icramo.data(i) <= ildataout when (ilram = 1) and ((ISETS = 1) or (i = 1)) and (crami.icramin.ldramin.read = '1') else iddataout(i)(31 downto 0);
itv : if ilinesize = 4 generate
cramo.icramo.tag(i)(7 downto 4) <= (others => '0');
end generate;
ite : for j in 10 to ITAG_LOW-1 generate
cramo.icramo.tag(i)(j) <= '0';
end generate;
end generate;
itx2 : for i in ISETS to MAXSETS-1 generate
cramo.icramo.tag(i) <= (others => '0');
cramo.icramo.data(i) <= (others => '0');
end generate;
itd : for i in 0 to DSETS-1 generate
cramo.dcramo.tag(i)(TAG_HIGH downto DTAG_LOW) <= dtdataout(i)(DTAG_BITS-1 downto (DTAG_BITS-1) - (TAG_HIGH - DTAG_LOW));
--(DTWIDTH-1-(DLRR_BIT+DCLOCK_BIT) downto DTWIDTH-(TAG_HIGH-DTAG_LOW)-(DLRR_BIT+DCLOCK_BIT)-1);
--cramo.dcramo.tag(i)(TAG_HIGH downto DTAG_LOW) <= dtdataout(i)(DTWIDTH-1-(DLRR_BIT+DCLOCK_BIT) downto DTWIDTH-(TAG_HIGH-DTAG_LOW)-(DLRR_BIT+DCLOCK_BIT)-1);
cramo.dcramo.tag(i)(dlinesize-1 downto 0) <= dtdataout(i)(dlinesize-1 downto 0);
cramo.dcramo.tag(i)(CTAG_LRRPOS) <= dtdataout(i)(DTWIDTH - (1+DCLOCK_BIT));
cramo.dcramo.tag(i)(CTAG_LOCKPOS) <= dtdataout(i)(DTWIDTH-1);
ictx : if mmuen /= 0 generate
cramo.dcramo.ctx(i) <= dtdataout(i)((DTWIDTH - (DLRR_BIT+DCLOCK_BIT+1)) downto (DTWIDTH - (DLRR_BIT+DCLOCK_BIT+M_CTX_SZ)));
end generate;
stagv : if not ((MMUEN = 0) or not DSNOOPMMU) generate
cramo.dcramo.stag(i)(TAG_HIGH downto DTAG_LOW) <= dtdataout3(i)(DTAG_BITS-1 downto (DTAG_BITS-1) - (TAG_HIGH - DTAG_LOW));
end generate;
stagp : if ((MMUEN = 0) or not DSNOOPMMU) generate
cramo.dcramo.stag(i)(TAG_HIGH downto DTAG_LOW) <= dtdataout2(i)(DTAG_BITS-1 downto (DTAG_BITS-1) - (TAG_HIGH - DTAG_LOW));
end generate;
-- cramo.dcramo.stag(i)(TAG_HIGH downto DTAG_LOW) <= dtdataout2(i)(DTWIDTH-1 downto DTWIDTH-(TAG_HIGH-DTAG_LOW)-1);
cramo.dcramo.stag(i)(dlinesize-1 downto 0) <= dtdataout2(i)(dlinesize-1 downto 0);
cramo.dcramo.stag(i)(CTAG_LRRPOS) <= dtdataout2(i)(DTWIDTH - (1+DCLOCK_BIT));
cramo.dcramo.stag(i)(CTAG_LOCKPOS) <= dtdataout2(i)(DTWIDTH-1);
cramo.dcramo.data(i) <= ldataout when (dlram = 1) and ((DSETS = 1) or (i = 1)) and (crami.dcramin.ldramin.read = '1')
else dddataout(i)(31 downto 0);
dtv : if dlinesize = 4 generate
cramo.dcramo.tag(i)(7 downto 4) <= (others => '0');
cramo.dcramo.stag(i)(7 downto 4) <= (others => '0');
end generate;
dte : for j in 10 to DTAG_LOW-1 generate
cramo.dcramo.tag(i)(j) <= '0';
cramo.dcramo.stag(i)(j) <= '0';
end generate;
end generate;
itd2 : for i in DSETS to MAXSETS-1 generate
cramo.dcramo.tag(i) <= (others => '0');
cramo.dcramo.stag(i) <= (others => '0');
cramo.dcramo.data(i) <= (others => '0');
end generate;
nodrv : for i in 0 to MAXSETS-1 generate
cramo.dcramo.tpar(i) <= (others => '0');
cramo.dcramo.dpar(i) <= (others => '0');
cramo.dcramo.spar(i) <= '0';
cramo.icramo.tpar(i) <= (others => '0');
cramo.icramo.dpar(i) <= (others => '0');
nommu : if mmuen = 0 generate
cramo.icramo.ctx(i) <= (others => '0');
cramo.dcramo.ctx(i) <= (others => '0');
end generate;
end generate;
end ;
| mit | 7c6d3effb42ce71c48b464face70f768 | 0.634315 | 3.406014 | false | false | false | false |
lxp32/lxp32-cpu | verify/icache/src/tb/cpu_model.vhd | 2 | 4,090 | ---------------------------------------------------------------------
-- CPU model
--
-- Part of the LXP32 instruction cache testbench
--
-- Copyright (c) 2016 by Alex I. Kuznetsov
--
-- Requests data from cache
---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
use work.common_pkg.all;
use work.tb_pkg.all;
entity cpu_model is
generic(
BLOCKS: integer;
VERBOSE: boolean
);
port(
clk_i: in std_logic;
lli_re_o: out std_logic;
lli_adr_o: out std_logic_vector(29 downto 0);
lli_dat_i: in std_logic_vector(31 downto 0);
lli_busy_i: in std_logic;
finish_o: out std_logic
);
end entity;
architecture sim of cpu_model is
constant bursts: integer:=10000;
signal re: std_logic:='0';
signal lli_adr: std_logic_vector(29 downto 0);
signal request: std_logic:='0';
signal request_addr: std_logic_vector(29 downto 0);
signal finish: std_logic:='0';
signal current_latency: integer:=1;
signal max_latency: integer:=-1;
signal total_latency: integer:=0;
signal spurious_misses: integer:=0;
begin
process is
variable b: integer:=1;
variable start: integer;
variable size: integer;
variable addr: integer:=0;
variable delay: integer;
variable rng_state: rng_state_type;
variable r: integer;
variable total_requests: integer:=0;
begin
while b<=BLOCKS loop
rand(rng_state,1,10,r);
if r=1 then -- insert large block occasionally
rand(rng_state,1,400,size);
else -- small block
rand(rng_state,1,32,size);
end if;
rand(rng_state,0,1,r);
if r=0 then -- long jump
rand(rng_state,0,1024,start);
addr:=start;
if VERBOSE then
report "Fetching block #"&integer'image(b)&" at address "&integer'image(addr)&
" of size "&integer'image(size);
end if;
else -- short jump
rand(rng_state,-10,10,r);
start:=addr+r;
if start<0 then
start:=0;
end if;
addr:=start;
if VERBOSE then
report "Fetching block #"&integer'image(b)&" at address "&integer'image(addr)&
" of size "&integer'image(size)&" (short jump)";
end if;
end if;
while addr<start+size loop
re<='1';
total_requests:=total_requests+1;
lli_adr<=std_logic_vector(to_unsigned(addr,30));
wait until rising_edge(clk_i) and lli_busy_i='0';
re<='0';
addr:=addr+1;
rand(rng_state,0,4,delay);
if delay>0 then
for i in 1 to delay loop
wait until rising_edge(clk_i);
end loop;
end if;
end loop;
if (b mod 10000)=0 then
report integer'image(b)&" BLOCKS PROCESSED";
end if;
b:=b+1;
end loop;
report "Number of requests: "&integer'image(total_requests);
report "Maximum latency: "&integer'image(max_latency);
report "Average latency: "&real'image(real(total_latency)/real(total_requests));
report "Number of spurious misses: "&integer'image(spurious_misses);
finish<='1';
wait;
end process;
lli_re_o<=re;
lli_adr_o<=lli_adr;
process (clk_i) is
begin
if rising_edge(clk_i) then
if lli_busy_i='0' then
if request='1' then
assert lli_dat_i=(("00"&request_addr) xor xor_constant)
report "Data mismatch: expected 0x"&
hex_string(("00"&request_addr) xor xor_constant)&
", got 0x"&hex_string(lli_dat_i)
severity failure;
end if;
request<=re;
request_addr<=lli_adr;
end if;
end if;
end process;
finish_o<=finish;
-- Measure latency
process (clk_i) is
begin
if rising_edge(clk_i) then
if lli_busy_i='0' then
if request='1' then
total_latency<=total_latency+current_latency;
if current_latency>max_latency then
max_latency<=current_latency;
end if;
end if;
current_latency<=1;
else
if lli_dat_i=(("00"&request_addr) xor xor_constant) and current_latency=1 then
spurious_misses<=spurious_misses+1;
end if;
current_latency<=current_latency+1;
end if;
end if;
end process;
process (clk_i) is
begin
if rising_edge(clk_i) then
assert lli_busy_i='0' or request='1'
report "LLI busy signal asserted without a request"
severity failure;
end if;
end process;
end architecture;
| mit | f4bc4047f3d9ee886635f300b6581bbb | 0.647922 | 2.925608 | false | false | false | false |
michaelfivez/ascon_hardware_implementation | ascon12864_unrolled3/Kernel/Sbox.vhd | 1 | 3,932 | -------------------------------------------------------------------------------
--! @project Unrolled (3) hardware implementation of Asconv1286
--! @author Michael Fivez
--! @license This project is released under the GNU Public License.
--! The license and distribution terms for this file may be
--! found in the file LICENSE in this distribution or at
--! http://www.gnu.org/licenses/gpl-3.0.txt
--! @note This is an hardware implementation made for my graduation thesis
--! at the KULeuven, in the COSIC department (year 2015-2016)
--! The thesis is titled 'Energy efficient hardware implementations of CAESAR submissions',
--! and can be found on the COSIC website (www.esat.kuleuven.be/cosic/publications)
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity Sbox is
port(
X0In : in std_logic_vector(63 downto 0);
X1In : in std_logic_vector(63 downto 0);
X2In : in std_logic_vector(63 downto 0);
X3In : in std_logic_vector(63 downto 0);
X4In : in std_logic_vector(63 downto 0);
RoundNr : in std_logic_vector(3 downto 0);
X0Out : out std_logic_vector(63 downto 0);
X1Out : out std_logic_vector(63 downto 0);
X2Out : out std_logic_vector(63 downto 0);
X3Out : out std_logic_vector(63 downto 0);
X4Out : out std_logic_vector(63 downto 0));
end entity Sbox;
architecture structural of Sbox is
begin
Sbox: process(X0In,X1In,X2In,X3In,X4In,RoundNr) is
-- Procedure for 5-bit Sbox
procedure doSboxPart (
variable SboxPartIn : in std_logic_vector(4 downto 0);
variable SboxPartOut : out std_logic_vector(4 downto 0)) is
-- Temp variable
variable SboxPartTemp : std_logic_vector(17 downto 0);
begin
-- Sbox Interconnections
SboxPartTemp(0) := SboxPartIn(0) xor SboxPartIn(4);
SboxPartTemp(1) := SboxPartIn(2) xor SboxPartIn(1);
SboxPartTemp(2) := SboxPartIn(4) xor SboxPartIn(3);
SboxPartTemp(3) := not SboxPartTemp(0);
SboxPartTemp(4) := not SboxPartIn(1);
SboxPartTemp(5) := not SboxPartTemp(1);
SboxPartTemp(6) := not SboxPartIn(3);
SboxPartTemp(7) := not SboxPartTemp(2);
SboxPartTemp(8) := SboxPartIn(1) and SboxPartTemp(3);
SboxPartTemp(9) := SboxPartTemp(1) and SboxPartTemp(4);
SboxPartTemp(10) := SboxPartIn(3) and SboxPartTemp(5);
SboxPartTemp(11) := SboxPartTemp(2) and SboxPartTemp(6);
SboxPartTemp(12) := SboxPartTemp(0) and SboxPartTemp(7);
SboxPartTemp(13) := SboxPartTemp(0) xor SboxPartTemp(9);
SboxPartTemp(14) := SboxPartIn(1) xor SboxPartTemp(10);
SboxPartTemp(15) := SboxPartTemp(1) xor SboxPartTemp(11);
SboxPartTemp(16) := SboxPartIn(3) xor SboxPartTemp(12);
SboxPartTemp(17) := SboxPartTemp(2) xor SboxPartTemp(8);
SboxPartOut(0) := SboxPartTemp(13) xor SboxPartTemp(17);
SboxPartOut(1) := SboxPartTemp(13) xor SboxPartTemp(14);
SboxPartOut(2) := not SboxPartTemp(15);
SboxPartOut(3) := SboxPartTemp(15) xor SboxPartTemp(16);
SboxPartOut(4) := SboxPartTemp(17);
end procedure doSboxPart;
variable X2TempIn : std_logic_vector(63 downto 0);
variable TempIn,TempOut : std_logic_vector(4 downto 0);
begin
-- Xor with round constants
X2TempIn(3 downto 0) := X2In(3 downto 0) xor RoundNr;
X2TempIn(7 downto 4) := X2In(7 downto 4) xnor RoundNr;
X2TempIn(63 downto 8) := X2In(63 downto 8);
-- Apply 5-bit Sbox 64 times
for i in X0In'range loop
TempIn(0) := X0In(i);
TempIn(1) := X1In(i);
TempIn(2) := X2TempIn(i);
TempIn(3) := X3In(i);
TempIn(4) := X4In(i);
doSboxPart(TempIn,TempOut);
X0Out(i) <= TempOut(0);
X1Out(i) <= TempOut(1);
X2Out(i) <= TempOut(2);
X3Out(i) <= TempOut(3);
X4Out(i) <= TempOut(4);
end loop;
end process Sbox;
end architecture structural;
| gpl-3.0 | 217a4b526f79307c5becf6ad031a1c8a | 0.639878 | 2.921248 | false | false | false | false |
impedimentToProgress/UCI-BlueChip | AttackFiles/Attacks/privEsc/lib/techmap/maps/syncram64.vhd | 2 | 4,010 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: syncram64
-- File: syncram64.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: 64-bit syncronous 1-port ram with 32-bit write strobes
-- and tech selection
------------------------------------------------------------------------------
library ieee;
library techmap;
use ieee.std_logic_1164.all;
use techmap.gencomp.all;
entity syncram64 is
generic (tech : integer := 0; abits : integer := 6);
port (
clk : in std_ulogic;
address : in std_logic_vector (abits -1 downto 0);
datain : in std_logic_vector (63 downto 0);
dataout : out std_logic_vector (63 downto 0);
enable : in std_logic_vector (1 downto 0);
write : in std_logic_vector (1 downto 0);
testin : in std_logic_vector (3 downto 0) := "0000");
end;
architecture rtl of syncram64 is
component virtex2_syncram64
generic ( abits : integer := 9);
port (
clk : in std_ulogic;
address : in std_logic_vector (abits -1 downto 0);
datain : in std_logic_vector (63 downto 0);
dataout : out std_logic_vector (63 downto 0);
enable : in std_logic_vector (1 downto 0);
write : in std_logic_vector (1 downto 0)
);
end component;
component artisan_syncram64
generic ( abits : integer := 9);
port (
clk : in std_ulogic;
address : in std_logic_vector (abits -1 downto 0);
datain : in std_logic_vector (63 downto 0);
dataout : out std_logic_vector (63 downto 0);
enable : in std_logic_vector (1 downto 0);
write : in std_logic_vector (1 downto 0)
);
end component;
component custom1_syncram64
generic ( abits : integer := 9);
port (
clk : in std_ulogic;
address : in std_logic_vector (abits -1 downto 0);
datain : in std_logic_vector (63 downto 0);
dataout : out std_logic_vector (63 downto 0);
enable : in std_logic_vector (1 downto 0);
write : in std_logic_vector (1 downto 0)
);
end component;
begin
s64 : if has_sram64(tech) = 1 generate
xc2v : if (tech = virtex2) or (tech = spartan3) or (tech = virtex4)
or (tech = spartan3e) or (tech = virtex5)
generate
x0 : virtex2_syncram64 generic map (abits)
port map (clk, address, datain, dataout, enable, write);
end generate;
arti : if tech = memartisan generate
x0 : artisan_syncram64 generic map (abits)
port map (clk, address, datain, dataout, enable, write);
end generate;
cust1: if tech = custom1 generate
x0 : custom1_syncram64 generic map (abits)
port map (clk, address, datain, dataout, enable, write);
end generate;
end generate;
nos64 : if has_sram64(tech) = 0 generate
x0 : syncram generic map (tech, abits, 32)
port map (clk, address, datain(63 downto 32), dataout(63 downto 32),
enable(1), write(1), testin);
x1 : syncram generic map (tech, abits, 32)
port map (clk, address, datain(31 downto 0), dataout(31 downto 0),
enable(0), write(0), testin);
end generate;
end;
| mit | 4804134bb63dcc5fd8f93bb698711045 | 0.61596 | 3.723305 | false | false | false | false |
impedimentToProgress/UCI-BlueChip | AttackFiles/Attacks/privEsc/lib/opencores/ata/atahost_pio_tctrl.vhd | 2 | 10,112 | ---------------------------------------------------------------------
---- ----
---- OpenCores ATA/ATAPI-5 Host Controller ----
---- PIO Timing Controller (common for all OCIDEC cores) ----
---- ----
---- Author: Richard Herveille ----
---- [email protected] ----
---- www.asics.ws ----
---- ----
---------------------------------------------------------------------
---- ----
---- Copyright (C) 2001, 2002 Richard Herveille ----
---- [email protected] ----
---- ----
---- This source file may be used and distributed without ----
---- restriction provided that this copyright statement is not ----
---- removed from the file and that any derivative work contains ----
---- the original copyright notice and the associated disclaimer.----
---- ----
---- THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ----
---- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ----
---- TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ----
---- FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ----
---- OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ----
---- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ----
---- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ----
---- GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ----
---- BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ----
---- LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ----
---- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ----
---- OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ----
---- POSSIBILITY OF SUCH DAMAGE. ----
---- ----
---------------------------------------------------------------------
-- rev.: 1.0 march 7th, 2001. Initial release
-- rev.: 1.1 July 11th, 2001. Changed 'igo' & 'hold_go' signal generation.
--
--
-- CVS Log
--
-- $Id: atahost_pio_tctrl.vhd,v 1.1 2002/02/18 14:32:12 rherveille Exp $
--
-- $Date: 2002/02/18 14:32:12 $
-- $Revision: 1.1 $
-- $Author: rherveille $
-- $Locker: $
-- $State: Exp $
--
-- Change History:
-- $Log: atahost_pio_tctrl.vhd,v $
-- Revision 1.1 2002/02/18 14:32:12 rherveille
-- renamed all files to 'atahost_***.vhd'
-- broke-up 'counter.vhd' into 'ud_cnt.vhd' and 'ro_cnt.vhd'
-- changed resD input to generic RESD in ud_cnt.vhd
-- changed ID input to generic ID in ro_cnt.vhd
-- changed core to reflect changes in ro_cnt.vhd
-- removed references to 'count' library
-- changed IO names
-- added disclaimer
-- added CVS log
-- moved registers and wishbone signals into 'atahost_wb_slave.vhd'
--
--
--
--
---------------------------
-- PIO Timing controller --
---------------------------
--
--
-- Timing PIO mode transfers
----------------------------------------------
-- T0: cycle time
-- T1: address valid to DIOR-/DIOW-
-- T2: DIOR-/DIOW- pulse width
-- T2i: DIOR-/DIOW- recovery time
-- T3: DIOW- data setup
-- T4: DIOW- data hold
-- T5: DIOR- data setup
-- T6: DIOR- data hold
-- T9: address hold from DIOR-/DIOW- negated
-- Trd: Read data valid to IORDY asserted
-- Ta: IORDY setup time
-- Tb: IORDY pulse width
--
-- Transfer sequence
----------------------------------
-- 1) set address (DA, CS0-, CS1-)
-- 2) wait for T1
-- 3) assert DIOR-/DIOW-
-- when write action present Data (timing spec. T3 always honored), enable output enable-signal
-- 4) wait for T2
-- 5) check IORDY
-- when not IORDY goto 5
-- when IORDY negate DIOW-/DIOR-, latch data (if read action)
-- when write, hold data for T4, disable output-enable signal
-- 6) wait end_of_cycle_time. This is T2i or T9 or (T0-T1-T2) whichever takes the longest
-- 7) start new cycle
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
entity atahost_pio_tctrl is
generic(
TWIDTH : natural := 8; -- counter width
-- PIO mode 0 settings (@100MHz clock)
PIO_mode0_T1 : natural := 6; -- 70ns
PIO_mode0_T2 : natural := 28; -- 290ns
PIO_mode0_T4 : natural := 2; -- 30ns
PIO_mode0_Teoc : natural := 23 -- 240ns ==> T0 - T1 - T2 = 600 - 70 - 290 = 240
);
port(
clk : in std_logic; -- master clock
nReset : in std_logic; -- asynchronous active low reset
rst : in std_logic; -- synchronous active high reset
-- timing/control register settings
IORDY_en : in std_logic; -- use IORDY (or not)
T1 : in std_logic_vector(TWIDTH -1 downto 0); -- T1 time (in clk-ticks)
T2 : in std_logic_vector(TWIDTH -1 downto 0); -- T2 time (in clk-ticks)
T4 : in std_logic_vector(TWIDTH -1 downto 0); -- T4 time (in clk-ticks)
Teoc : in std_logic_vector(TWIDTH -1 downto 0); -- end of cycle time
-- control signals
go : in std_logic; -- PIO controller selected (strobe signal)
we : in std_logic; -- write enable signal. '0'=read from device, '1'=write to device
-- return signals
oe : out std_logic; -- output enable signal
done : out std_logic; -- finished cycle
dstrb : out std_logic; -- data strobe, latch data (during read)
-- ATA signals
DIOR, -- IOread signal, active high
DIOW : out std_logic; -- IOwrite signal, active high
IORDY : in std_logic -- IORDY signal
);
end entity atahost_pio_tctrl;
architecture structural of atahost_pio_tctrl is
component ro_cnt is
generic(
SIZE : natural := 8;
UD : integer := 0; -- default count down
ID : natural := 0 -- initial data after reset
);
port(
clk : in std_logic; -- master clock
nReset : in std_logic := '1'; -- asynchronous active low reset
rst : in std_logic := '0'; -- synchronous active high reset
cnt_en : in std_logic := '1'; -- count enable
go : in std_logic; -- load counter and start sequence
done : out std_logic; -- done counting
d : in std_logic_vector(SIZE -1 downto 0); -- load counter value
q : out std_logic_vector(SIZE -1 downto 0) -- current counter value
);
end component ro_cnt;
signal T1done, T2done, T4done, Teoc_done, IORDY_done : std_logic;
signal busy, hold_go, igo, hT2done : std_logic;
signal iDIOR, iDIOW, ioe : std_logic;
begin
DIOR <= iDIOR; DIOW <= iDIOW; oe <= ioe;
-- generate internal go strobe
-- strecht go until ready for new cycle
process(clk, nReset)
begin
if (nReset = '0') then
busy <= '0';
hold_go <= '0';
elsif (clk'event and clk = '1') then
if (rst = '1') then
busy <= '0';
hold_go <= '0';
else
busy <= (igo or busy) and not Teoc_done;
hold_go <= (go or (hold_go and busy)) and not igo;
end if;
end if;
end process;
igo <= (go or hold_go) and not busy;
-- 1) hookup T1 counter
t1_cnt : ro_cnt
generic map (
SIZE => TWIDTH,
UD => 0,
ID => PIO_mode0_T1
)
port map (
clk => clk,
nReset => nReset,
rst => rst,
go => igo,
D => T1,
done => T1done
);
-- 2) set (and reset) DIOR-/DIOW-, set output-enable when writing to device
T2proc: process(clk, nReset)
begin
if (nReset = '0') then
iDIOR <= '0';
iDIOW <= '0';
ioe <= '0';
elsif (clk'event and clk = '1') then
if (rst = '1') then
iDIOR <= '0';
iDIOW <= '0';
ioe <= '0';
else
iDIOR <= (not we and T1done) or (iDIOR and not IORDY_done);
iDIOW <= ( we and T1done) or (iDIOW and not IORDY_done);
ioe <= ( (we and igo) or ioe) and not T4done; -- negate oe when t4-done
end if;
end if;
end process T2proc;
-- 3) hookup T2 counter
t2_cnt : ro_cnt
generic map (
SIZE => TWIDTH,
UD => 0,
ID => PIO_mode0_T2
)
port map (
clk => clk,
nReset => nReset,
rst => rst,
go => T1done,
D => T2,
done => T2done
);
-- 4) check IORDY (if used), generate release_DIOR-/DIOW- signal (ie negate DIOR-/DIOW-)
-- hold T2done
gen_hT2done: process(clk, nReset)
begin
if (nReset = '0') then
hT2done <= '0';
elsif (clk'event and clk = '1') then
if (rst = '1') then
hT2done <= '0';
else
hT2done <= (T2done or hT2done) and not IORDY_done;
end if;
end if;
end process gen_hT2done;
IORDY_done <= (T2done or hT2done) and (IORDY or not IORDY_en);
-- generate datastrobe, capture data at rising DIOR- edge
gen_dstrb: process(clk)
begin
if (clk'event and clk = '1') then
dstrb <= IORDY_done;
end if;
end process gen_dstrb;
-- hookup data hold counter
dhold_cnt : ro_cnt
generic map (
SIZE => TWIDTH,
UD => 0,
ID => PIO_mode0_T4
)
port map (
clk => clk,
nReset => nReset,
rst => rst,
go => IORDY_done,
D => T4,
done => T4done
);
done <= T4done; -- placing done here provides the fastest return possible,
-- while still guaranteeing data and address hold-times
-- 5) hookup end_of_cycle counter
eoc_cnt : ro_cnt
generic map (
SIZE => TWIDTH,
UD => 0,
ID => PIO_mode0_Teoc
)
port map (
clk => clk,
nReset => nReset,
rst => rst,
go => IORDY_done,
D => Teoc,
done => Teoc_done
);
end architecture structural;
| mit | e0ad5f42e7a15c58e676bae7f63ce9f4 | 0.520273 | 3.397849 | false | false | false | false |
impedimentToProgress/UCI-BlueChip | AttackFiles/Attacks/privEsc/lib/techmap/proasic3/tap_proasic3.vhd | 2 | 3,674 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: tap_proasic3
-- File: tap_proasic3.vhd
-- Author: Edvin Catovic - Gaisler Research
-- Description: Actel Proasic3 TAP controller wrapper
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
-- pragma translate_off
library proasic3;
-- pragma translate_on
entity proasic3_tap is
port (
tck : in std_ulogic;
tms : in std_ulogic;
tdi : in std_ulogic;
trst : in std_ulogic;
tdo : out std_ulogic;
tapi_tdo1 : in std_ulogic;
tapi_tdo2 : in std_ulogic;
tapi_en1 : in std_ulogic;
tapo_tck : out std_ulogic;
tapo_tdi : out std_ulogic;
tapo_rst : out std_ulogic;
tapo_capt : out std_ulogic;
tapo_shft : out std_ulogic;
tapo_upd : out std_ulogic;
tapo_inst : out std_logic_vector(7 downto 0)
);
end;
architecture rtl of proasic3_tap is
component UJTAG
port(
UTDO : in STD_ULOGIC;
TMS : in STD_ULOGIC;
TDI : in STD_ULOGIC;
TCK : in STD_ULOGIC;
TRSTB : in STD_ULOGIC;
UIREG0 : out STD_ULOGIC;
UIREG1 : out STD_ULOGIC;
UIREG2 : out STD_ULOGIC;
UIREG3 : out STD_ULOGIC;
UIREG4 : out STD_ULOGIC;
UIREG5 : out STD_ULOGIC;
UIREG6 : out STD_ULOGIC;
UIREG7 : out STD_ULOGIC;
UTDI : out STD_ULOGIC;
URSTB : out STD_ULOGIC;
UDRCK : out STD_ULOGIC;
UDRCAP : out STD_ULOGIC;
UDRSH : out STD_ULOGIC;
UDRUPD : out STD_ULOGIC;
TDO : out STD_ULOGIC);
end component;
signal gnd, tdoi, rsti : std_ulogic;
begin
gnd <= '0';
tdoi <= tapi_tdo1 when tapi_en1 = '1' else tapi_tdo2;
tapo_rst <= not rsti;
u0 : UJTAG port map (
UTDO => tdoi,
TMS => tms,
TDI => tdi,
TCK => tck,
TRSTB => trst,
UIREG0 => tapo_inst(0),
UIREG1 => tapo_inst(1),
UIREG2 => tapo_inst(2),
UIREG3 => tapo_inst(3),
UIREG4 => tapo_inst(4),
UIREG5 => tapo_inst(5),
UIREG6 => tapo_inst(6),
UIREG7 => tapo_inst(7),
UTDI => tapo_tdi,
URSTB => rsti,
UDRCK => tapo_tck,
UDRCAP => tapo_capt,
UDRSH => tapo_shft,
UDRUPD => tapo_upd,
TDO => tdo);
end;
| mit | e1785a6ab1d43f8252e9eefd12232f9c | 0.498911 | 3.699899 | false | false | false | false |
mgiacomini/mips-monocycle | MEM.vhd | 2 | 2,468 | -- +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-- Complete implementation of Patterson and Hennessy single cycle MIPS processor
-- Copyright (C) 2015 Darci Luiz Tomasi Junior
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, version 3.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
-- Engineer: Darci Luiz Tomasi Junior
-- E-mail: [email protected]
-- Date : 08/07/2015 - 20:07
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;
ENTITY MEM IS
PORT(
CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
MemWrite : IN STD_LOGIC;
MemRead : IN STD_LOGIC;
IN_A : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
IN_B : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
OUT_A : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END MEM;
ARCHITECTURE ARC_MEM OF MEM IS
TYPE RAM_TYPE IS ARRAY(0 TO 255) OF STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL RAM: RAM_TYPE;
SIGNAL ADRESS : STD_LOGIC_VECTOR(31 DOWNTO 0);
BEGIN
PROCESS(CLK)
BEGIN
IF RESET = '1' THEN
RAM <= ((OTHERS => (OTHERS=>'0')));
ELSIF CLK'EVENT AND CLK = '1' THEN
IF MemWrite = '1' THEN
--MIPS ARMAZEMA EM BYTES OU SEJA 4 EM 4
--POR ISSO PEGA DE 31 A 2, POIS DEVIDO A POSIO DE ORDENAO DO ARRAY SER DE 1 EM 1...
--...SE DESLOCA DOIS PARA DIREITA EX:
-- SW $S0, 4($T0) 1010110100101000 0000000000000100
-- [31-2]
-- 1010110100101000 00000000000001 = 1
-- SW $S0, 8($T0) 1010110100101000 0000000000001000
-- [31-2]
-- 1010110100101000 00000000000010 = 2
RAM(TO_INTEGER (UNSIGNED(ADRESS(31 DOWNTO 2)))) <= IN_B;
END IF;
END IF;
END PROCESS;
OUT_A <= RAM(TO_INTEGER(UNSIGNED(ADRESS(31 DOWNTO 2)))) WHEN MemRead ='1';
--PARA UTILIZAR COM O MARS
ADRESS <= STD_LOGIC_VECTOR(UNSIGNED(IN_A) - X"FFFF0000");
END ARC_MEM;
| gpl-3.0 | 06e4f2517e80b16c410342630ab788d7 | 0.599271 | 3.312752 | false | false | false | false |
impedimentToProgress/UCI-BlueChip | AttackFiles/Attacks/privEsc/lib/gaisler/misc/ahbtrace.vhd | 2 | 11,104 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: ahbtrace
-- File: ahbtrace.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: AHB trace unit
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
library techmap;
use techmap.gencomp.all;
library gaisler;
entity ahbtrace is
generic (
hindex : integer := 0;
ioaddr : integer := 16#000#;
iomask : integer := 16#E00#;
tech : integer := DEFMEMTECH;
irq : integer := 0;
kbytes : integer := 1);
port (
rst : in std_ulogic;
clk : in std_ulogic;
ahbmi : in ahb_mst_in_type;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type
);
end;
architecture rtl of ahbtrace is
constant TBUFABITS : integer := log2(kbytes) + 6;
constant TIMEBITS : integer := 32;
constant hconfig : ahb_config_type := (
0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_AHBTRACE, 0, 0, irq),
4 => ahb_iobar (ioaddr, iomask),
others => zero32);
type tracebuf_in_type is record
addr : std_logic_vector(11 downto 0);
data : std_logic_vector(127 downto 0);
enable : std_logic;
write : std_logic_vector(3 downto 0);
end record;
type tracebuf_out_type is record
data : std_logic_vector(127 downto 0);
end record;
type trace_break_reg is record
addr : std_logic_vector(31 downto 2);
mask : std_logic_vector(31 downto 2);
read : std_logic;
write : std_logic;
end record;
type regtype is record
haddr : std_logic_vector(31 downto 0);
hwrite : std_logic;
htrans : std_logic_vector(1 downto 0);
hsize : std_logic_vector(2 downto 0);
hburst : std_logic_vector(2 downto 0);
hwdata : std_logic_vector(31 downto 0);
hmaster : std_logic_vector(3 downto 0);
hmastlock : std_logic;
hsel : std_logic;
hready : std_logic;
hready2 : std_logic;
hready3 : std_logic;
ahbactive : std_logic;
timer : std_logic_vector(TIMEBITS-1 downto 0);
aindex : std_logic_vector(TBUFABITS - 1 downto 0); -- buffer index
enable : std_logic; -- trace enable
bahb : std_logic; -- break on AHB watchpoint hit
bhit : std_logic; -- breakpoint hit
dcnten : std_logic; -- delay counter enable
delaycnt : std_logic_vector(TBUFABITS - 1 downto 0); -- delay counter
tbreg1 : trace_break_reg;
tbreg2 : trace_break_reg;
end record;
signal tbi : tracebuf_in_type;
signal tbo : tracebuf_out_type;
signal enable : std_logic_vector(1 downto 0);
signal r, rin : regtype;
begin
ctrl : process(rst, ahbmi, ahbsi, r, tbo)
variable v : regtype;
variable vabufi : tracebuf_in_type;
variable regsd : std_logic_vector(31 downto 0); -- data from registers
variable aindex : std_logic_vector(TBUFABITS - 1 downto 0); -- buffer index
variable bphit : std_logic;
variable bufdata : std_logic_vector(127 downto 0);
variable hirq : std_logic_vector(NAHBIRQ-1 downto 0);
begin
v := r; regsd := (others => '0'); vabufi.enable := '0';
vabufi.data := (others => '0'); vabufi.addr := (others => '0');
vabufi.write := (others => '0'); bphit := '0';
v.hready := r.hready2; v.hready2 := r.hready3; v.hready3 := '0';
bufdata := tbo.data;
hirq := (others => '0'); hirq(irq) := r.bhit;
-- trace buffer index and delay counters
if r.enable = '1' then v.timer := r.timer + 1; end if;
aindex := r.aindex + 1;
-- check for AHB watchpoints
if (ahbsi.hready and r.ahbactive ) = '1' then
if ((((r.tbreg1.addr xor r.haddr(31 downto 2)) and r.tbreg1.mask) = zero32(29 downto 0)) and
(((r.tbreg1.read and not r.hwrite) or (r.tbreg1.write and r.hwrite)) = '1'))
or ((((r.tbreg2.addr xor r.haddr(31 downto 2)) and r.tbreg2.mask) = zero32(29 downto 0)) and
(((r.tbreg2.read and not r.hwrite) or (r.tbreg2.write and r.hwrite)) = '1'))
then
if (r.enable = '1') and (r.dcnten = '0') and
(r.delaycnt /= zero32(TBUFABITS-1 downto 0))
then v.dcnten := '1';
else bphit := '1'; v.enable := '0'; end if;
end if;
end if;
-- generate buffer inputs
vabufi.write := "0000";
if r.enable = '1' then
vabufi.addr(TBUFABITS-1 downto 0) := r.aindex;
vabufi.data(127 downto 96) := r.timer;
vabufi.data(95) := bphit;
vabufi.data(94 downto 80) := ahbmi.hirq(15 downto 1);
vabufi.data(79) := r.hwrite;
vabufi.data(78 downto 77) := r.htrans;
vabufi.data(76 downto 74) := r.hsize;
vabufi.data(73 downto 71) := r.hburst;
vabufi.data(70 downto 67) := r.hmaster;
vabufi.data(66) := r.hmastlock;
vabufi.data(65 downto 64) := ahbmi.hresp;
if r.hwrite = '1' then
vabufi.data(63 downto 32) := ahbsi.hwdata;
else
vabufi.data(63 downto 32) := ahbmi.hrdata;
end if;
vabufi.data(31 downto 0) := r.haddr;
else
vabufi.addr(TBUFABITS-1 downto 0) := r.haddr(TBUFABITS+3 downto 4);
vabufi.data := ahbsi.hwdata & ahbsi.hwdata &
ahbsi.hwdata & ahbsi.hwdata;
end if;
-- write trace buffer
if r.enable = '1' then
if (r.ahbactive and ahbsi.hready) = '1' then
v.aindex := aindex;
vabufi.enable := '1'; vabufi.write := "1111";
end if;
end if;
-- trace buffer delay counter handling
if (r.dcnten = '1') then
if (r.delaycnt = zero32(TBUFABITS-1 downto 0)) then
v.enable := '0'; v.dcnten := '0';
end if;
v.delaycnt := r.delaycnt - 1;
end if;
-- save AHB transfer parameters
if (ahbsi.hready = '1' ) then
v.haddr := ahbsi.haddr; v.hwrite := ahbsi.hwrite; v.htrans := ahbsi.htrans;
v.hsize := ahbsi.hsize; v.hburst := ahbsi.hburst;
v.hmaster := ahbsi.hmaster; v.hmastlock := ahbsi.hmastlock;
end if;
if r.hsel = '1' then v.hwdata := ahbsi.hwdata; end if;
if ahbsi.hready = '1' then
v.hsel := ahbsi.hsel(hindex);
v.ahbactive := ahbsi.htrans(1);
end if;
-- AHB slave access to DSU registers and trace buffers
if (r.hsel and not r.hready) = '1' then
if r.haddr(16) = '0' then -- registers
v.hready := '1';
case r.haddr(4 downto 2) is
when "000" =>
regsd((TBUFABITS + 15) downto 16) := r.delaycnt;
regsd(1 downto 0) := r.dcnten & r.enable;
if r.hwrite = '1' then
v.delaycnt := ahbsi.hwdata((TBUFABITS+ 15) downto 16);
v.dcnten := ahbsi.hwdata(1);
v.enable := ahbsi.hwdata(0);
end if;
when "001" =>
regsd((TBUFABITS - 1 + 4) downto 4) := r.aindex;
if r.hwrite = '1' then
v.aindex := ahbsi.hwdata((TBUFABITS- 1) downto 0);
end if;
when "010" =>
regsd((TIMEBITS - 1) downto 0) := r.timer;
if r.hwrite = '1' then
v.timer := ahbsi.hwdata((TIMEBITS- 1) downto 0);
end if;
when "100" =>
regsd(31 downto 2) := r.tbreg1.addr;
if r.hwrite = '1' then
v.tbreg1.addr := ahbsi.hwdata(31 downto 2);
end if;
when "101" =>
regsd := r.tbreg1.mask & r.tbreg1.read & r.tbreg1.write;
if r.hwrite = '1' then
v.tbreg1.mask := ahbsi.hwdata(31 downto 2);
v.tbreg1.read := ahbsi.hwdata(1);
v.tbreg1.write := ahbsi.hwdata(0);
end if;
when "110" =>
regsd(31 downto 2) := r.tbreg2.addr;
if r.hwrite = '1' then
v.tbreg2.addr := ahbsi.hwdata(31 downto 2);
end if;
when others =>
regsd := r.tbreg2.mask & r.tbreg2.read & r.tbreg2.write;
if r.hwrite = '1' then
v.tbreg2.mask := ahbsi.hwdata(31 downto 2);
v.tbreg2.read := ahbsi.hwdata(1);
v.tbreg2.write := ahbsi.hwdata(0);
end if;
end case;
v.hwdata := regsd;
else -- read/write access to trace buffer
if r.hwrite = '1' then v.hready := '1'; else v.hready2 := not (r.hready2 or r.hready); end if;
vabufi.enable := not r.enable;
bufdata := tbo.data;
case r.haddr(3 downto 2) is
when "00" =>
v.hwdata := bufdata(127 downto 96);
if r.hwrite = '1' then
vabufi.write(3) := vabufi.enable;
end if;
when "01" =>
v.hwdata := bufdata(95 downto 64);
if r.hwrite = '1' then
vabufi.write(2) := vabufi.enable;
end if;
when "10" =>
v.hwdata := bufdata(63 downto 32);
if r.hwrite = '1' then
vabufi.write(1) := vabufi.enable;
end if;
when others =>
v.hwdata := bufdata(31 downto 0);
if r.hwrite = '1' then
vabufi.write(0) := vabufi.enable;
end if;
end case;
end if;
end if;
if ((ahbsi.hsel(hindex) and ahbsi.hready) = '1') and
((ahbsi.htrans = HTRANS_BUSY) or (ahbsi.htrans = HTRANS_IDLE))
then v.hready := '1'; end if;
if rst = '0' then
v.ahbactive := '0'; v.enable := '0'; v.timer := (others => '0');
v.hsel := '0'; v.dcnten := '0'; v.bhit := '0';
v.tbreg1.read := '0'; v.tbreg1.write := '0';
v.tbreg2.read := '0'; v.tbreg2.write := '0';
end if;
tbi <= vabufi;
rin <= v;
ahbso.hconfig <= hconfig;
ahbso.hirq <= hirq;
ahbso.hsplit <= (others => '0');
ahbso.hcache <= '0';
ahbso.hrdata <= r.hwdata;
ahbso.hready <= r.hready;
ahbso.hindex <= hindex;
end process;
ahbso.hresp <= HRESP_OKAY;
regs : process(clk)
begin if rising_edge(clk) then r <= rin; end if; end process;
-- mem0 : tbufmem
-- generic map (tech => tech, tbuf => kbytes) port map (clk, tbi, tbo);
enable <= tbi.enable & tbi.enable;
mem0 : for i in 0 to 1 generate
ram0 : syncram64 generic map (tech => tech, abits => TBUFABITS)
port map (clk, tbi.addr(TBUFABITS-1 downto 0), tbi.data(((i*64)+63) downto (i*64)),
tbo.data(((i*64)+63) downto (i*64)), enable, tbi.write(i*2+1 downto i*2));
end generate;
-- pragma translate_off
bootmsg : report_version
generic map ("ahbtrace" & tost(hindex) &
": AHB Trace Buffer, " & tost(kbytes) & " kbytes");
-- pragma translate_on
end;
| mit | 720aa7d969e41869915f147ff02ba487 | 0.5788 | 3.346594 | false | false | false | false |
impedimentToProgress/UCI-BlueChip | AttackFiles/Attacks/privEsc/lib/techmap/maps/outpad_ds.vhd | 2 | 3,001 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: outpad_ds
-- File: outpad_ds.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: Differential output pad with technology wrapper
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
use techmap.allpads.all;
entity outpad_ds is
generic (tech : integer := 0; level : integer := lvds;
voltage : integer := x33v; oepol : integer := 0);
port (padp, padn : out std_ulogic; i, en : in std_ulogic);
end;
architecture rtl of outpad_ds is
signal gnd, oen : std_ulogic;
begin
gnd <= '0';
oen <= not en when oepol /= padoen_polarity(tech) else en;
gen0 : if has_ds_pads(tech) = 0 generate
padp <= i after 1 ns;
padn <= not i after 1 ns;
end generate;
xcv : if (tech = virtex) or (tech = virtex2) or (tech = spartan3) or
(tech = virtex4) or (tech = spartan3e)
generate
u0 : virtex_outpad_ds generic map (level, voltage) port map (padp, padn, i);
end generate;
xcv5 : if (tech = virtex5) generate
u0 : virtex5_outpad_ds generic map (level, voltage) port map (padp, padn, i);
end generate;
axc : if (tech = axcel) generate
u0 : axcel_outpad_ds generic map (level, voltage) port map (padp, padn, i);
end generate;
rht : if (tech = rhlib18t) generate
u0 : rh_lib18t_outpad_ds port map (padp, padn, i, oen);
end generate;
end;
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
entity outpad_dsv is
generic (tech : integer := 0; level : integer := x33v;
voltage : integer := lvds; width : integer := 1;
oepol : integer := 0);
port (
padp : out std_logic_vector(width-1 downto 0);
padn : out std_logic_vector(width-1 downto 0);
i, en: in std_logic_vector(width-1 downto 0));
end;
architecture rtl of outpad_dsv is
begin
v : for j in width-1 downto 0 generate
u0 : outpad_ds generic map (tech, level, voltage, oepol)
port map (padp(j), padn(j), i(j), en(j));
end generate;
end;
| mit | 894163b908191817f22cae06f81d811a | 0.632789 | 3.633172 | false | false | false | false |
cafe-alpha/wascafe | v13/stm32_bup_test/r07c_de10_20200912/wasca/synthesis/submodules/abus_demux.vhd | 2 | 39,070 | -- abus_demux.vhd
library IEEE;
use IEEE.numeric_std.all;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity abus_demux is
port (
-- -- External signals used for simulation vvv
-- sim_test1 : out std_logic_vector( 7 downto 0) := (others => '0');
-- sim_test2 : out std_logic_vector( 7 downto 0) := (others => '0');
-- abus_cspulse_trail_dbg : out std_logic_vector(11 downto 0) := (others => '0');
-- abus_read_trail_dbg : out std_logic_vector(11 downto 0) := (others => '0');
-- abus_writeneg0_trail_dbg : out std_logic_vector(11 downto 0) := (others => '0');
-- abus_writeneg1_trail_dbg : out std_logic_vector(11 downto 0) := (others => '0');
-- abus_addresslatched_dbg : out std_logic_vector(23 downto 0) := (others => '0');
-- sim_noise : in std_logic := '0';
-- -- External signals used for simulation ^^^
clock : in std_logic := '0'; -- clock.clk
-- A-Bus interface
abus_address : in std_logic_vector( 8 downto 0) := (others => '0'); -- abus.address
abus_addressdata : inout std_logic_vector(15 downto 0) := (others => '0'); -- abus.addressdata
abus_chipselect : in std_logic_vector( 2 downto 0) := (others => '0'); -- .chipselect
abus_read : in std_logic := '0'; -- .read
abus_write : in std_logic_vector( 1 downto 0) := (others => '0'); -- .write
abus_waitrequest : out std_logic := '1'; -- .waitrequest
abus_interrupt : out std_logic := '0'; -- .interrupt
abus_direction : out std_logic := '0'; -- .direction
abus_muxing : out std_logic_vector( 1 downto 0) := "01"; -- .muxing
abus_disable_out : out std_logic := '0'; -- .disableout
saturn_reset : in std_logic := '0'; -- .saturn_reset
-- Demuxed signals
-- Note : naming is Saturn-centered, ie readdata = read from Saturn = output from A-Bus side = input from demux side
demux_writeaddress : out std_logic_vector(27 downto 0) := (others => '0');
demux_writedata : out std_logic_vector(15 downto 0) := (others => '0');
demux_writepulse : out std_logic := '0';
demux_write_byteenable : out std_logic_vector( 1 downto 0) := (others => '0');
demux_readaddress : out std_logic_vector(27 downto 0) := (others => '0');
demux_readdata : in std_logic_vector(15 downto 0) := (others => '0');
demux_readpulse : out std_logic := '0';
demux_readdatavalid : in std_logic := '0';
-- Avalon
avalon_nios_read : in std_logic := '0'; -- avalon_master.read
avalon_nios_write : in std_logic := '0'; -- .write
avalon_nios_waitrequest : out std_logic := '0'; -- .waitrequest
avalon_nios_address : in std_logic_vector( 7 downto 0) := (others => '0'); -- .address
avalon_nios_writedata : in std_logic_vector(31 downto 0) := (others => '0'); -- .writedata
avalon_nios_burstcount : in std_logic; -- .burstcount
avalon_nios_readdata : out std_logic_vector(31 downto 0) := (others => '0'); -- .readdata
avalon_nios_readdatavalid : out std_logic := '0'; -- .readdatavalid
reset : in std_logic := '0' -- reset.reset
);
end entity abus_demux;
architecture rtl of abus_demux is
-- Trail size, same for all internal signals.
-- As Quartus won't synthetize unused signals, large enough size is defined
-- so that source readability shall be a bit improved.
constant ABUS_TRAILS_SIZE : integer := 12;
signal abus_address_ms : std_logic_vector( 8 downto 0) := (others => '0'); -- abus.address
signal abus_address_buf : std_logic_vector( 8 downto 0) := (others => '0'); -- abus.address
signal abus_addressdata_ms : std_logic_vector(15 downto 0) := (others => '0'); -- .data
signal abus_addressdata_buf : std_logic_vector(15 downto 0) := (others => '0'); -- .data
signal abus_chipselect_p1 : std_logic_vector( 2 downto 0) := (others => '0'); -- .chipselect
signal abus_chipselect_p2 : std_logic_vector( 2 downto 0) := (others => '0'); -- .chipselect
signal abus_chipselect_buf2 : std_logic_vector( 2 downto 0) := (others => '0'); -- .chipselect
signal abus_read_ms : std_logic := '0'; -- .read
signal abus_write_ms : std_logic_vector( 1 downto 0) := (others => '0'); -- .write
signal abus_writeneg_ms : std_logic_vector( 1 downto 0) := (others => '0'); -- .write
signal abus_write_buf : std_logic_vector( 1 downto 0) := (others => '0'); -- .write
signal abus_writedata_buf : std_logic_vector(15 downto 0) := (others => '0'); -- .data
signal abus_read_trail : std_logic_vector((ABUS_TRAILS_SIZE-1) downto 0) := (others => '0'); -- RD
signal abus_write_buf2 : std_logic_vector( 1 downto 0) := (others => '0'); -- .write
signal abus_writeneg0_trail : std_logic_vector((ABUS_TRAILS_SIZE-1) downto 0) := (others => '0'); -- WR0
signal abus_writeneg1_trail : std_logic_vector((ABUS_TRAILS_SIZE-1) downto 0) := (others => '0'); -- WR1
signal abus_trcntr : std_logic_vector( 3 downto 0) := (others => '0'); -- Transaction state counter
signal abus_read_pulse : std_logic := '0'; -- .read
signal abus_reading : std_logic := '0'; -- .read
signal abus_write_pulse : std_logic := '0'; -- .write
signal abus_writing : std_logic := '0'; -- .write
-- Trails to properly delay write pipeline
signal abus_write_pulse_trail : std_logic_vector((ABUS_TRAILS_SIZE-1) downto 0) := (others => '0'); -- write
signal abus_writing_trail : std_logic_vector((ABUS_TRAILS_SIZE-1) downto 0) := (others => '0'); -- write
-- Buffers to hold avalon parameters during transaction
signal avalon_writedata_buff : std_logic_vector(15 downto 0) := (others => '0');
signal avalon_byteenable_buff : std_logic_vector( 1 downto 0) := (others => '0');
signal avalon_write_buff : std_logic := '0';
signal abus_read_pulse_dmy : std_logic := '0'; -- .read
signal abus_write_pulse_dmy : std_logic_vector( 1 downto 0) := (others => '0'); -- .write
signal abus_chipselect_pulse : std_logic_vector( 2 downto 0) := (others => '0'); -- .chipselect
signal abus_read_pulse_off : std_logic := '0'; -- .read
signal abus_write_pulse_off : std_logic_vector( 1 downto 0) := (others => '0'); -- .write
signal abus_chipselect_pulse_off : std_logic_vector( 2 downto 0) := (others => '0'); -- .chipselect
signal abus_anypulse : std_logic := '0';
signal abus_anypulse2 : std_logic := '0';
signal abus_anypulse3 : std_logic := '0';
signal abus_anypulse_off : std_logic := '0';
signal abus_cspulse_trail : std_logic_vector((ABUS_TRAILS_SIZE-1) downto 0) := (others => '0');
signal abus_cspulse_off : std_logic := '0';
signal abus_chipselect_latched : std_logic_vector( 2 downto 0) := (others => '1'); -- abus.chipselect
signal abus_read_latched : std_logic := '0'; -- .read
signal abus_write_latched : std_logic_vector( 1 downto 0) := (others => '0'); -- .write
signal abus_address_latched : std_logic_vector(23 downto 0) := (others => '0'); -- .address
signal abus_direction_internal : std_logic := '0'; --high-z
signal abus_muxing_internal : std_logic_vector( 1 downto 0) := "01"; -- sample address
signal abus_data_out : std_logic_vector(15 downto 0) := (others => '0');
signal abus_data_in : std_logic_vector(15 downto 0) := (others => '0');
signal abus_waitrequest_read1 : std_logic := '0';
signal abus_waitrequest_read2 : std_logic := '0';
signal abus_waitrequest_write1 : std_logic := '0';
signal abus_waitrequest_write2 : std_logic := '0';
signal abus_waitrequest_read_off : std_logic := '0';
signal abus_waitrequest_write_off : std_logic := '0';
-- Access test stuff, added 2019/11/04 vvv
signal rdwr_access_buff : std_logic_vector(127 downto 0) := x"CAFE0304050607080910111213141516";
-- Access test stuff, added 2019/11/04 ^^^
-- External signals used for simulation vvv
signal sim_test1_internal : std_logic_vector( 7 downto 0) := x"CA";
signal sim_test2_internal : std_logic_vector( 7 downto 0) := x"FE";
-- External signals used for simulation ^^^
-- For Rd/Wr access debug
signal rd_access_cntr : std_logic_vector( 7 downto 0) := x"01";
signal wr_access_cntr : std_logic_vector( 7 downto 0) := x"01";
signal last_wr_data : std_logic_vector(15 downto 0) := x"5678";
signal REG_PCNTR : std_logic_vector(15 downto 0) := (others => '0');
signal REG_STATUS : std_logic_vector(15 downto 0) := (others => '0');
signal REG_MODE : std_logic_vector(15 downto 0) := (others => '0');
signal REG_HWVER : std_logic_vector(15 downto 0) := X"0002";
signal REG_SWVER : std_logic_vector(15 downto 0) := (others => '0');
TYPE transaction_dir IS (DIR_NONE,DIR_WRITE,DIR_READ);
SIGNAL my_little_transaction_dir : transaction_dir := DIR_NONE;
TYPE wasca_mode_type IS (MODE_INIT,
MODE_POWER_MEMORY_05M, MODE_POWER_MEMORY_1M, MODE_POWER_MEMORY_2M, MODE_POWER_MEMORY_4M,
MODE_RAM_1M, MODE_RAM_4M,
MODE_ROM_KOF95,
MODE_ROM_ULTRAMAN,
MODE_BOOT);
SIGNAL wasca_mode : wasca_mode_type := MODE_INIT;
begin
--ignoring functioncode, timing and addressstrobe for now
--abus transactions are async, so first we must latch incoming signals
--to get rid of metastability
process (clock)
begin
if rising_edge(clock) then
--1st stage
abus_address_ms <= abus_address;
abus_addressdata_ms <= abus_addressdata;
abus_chipselect_p1 <= abus_chipselect;
abus_read_ms <= abus_read;
abus_write_ms <= abus_write;
abus_writeneg_ms <= not abus_write;
--2nd stage
abus_address_buf <= abus_address_ms;
abus_addressdata_buf <= abus_addressdata_ms;
abus_chipselect_p2 <= abus_chipselect_p1;
abus_read_trail(0) <= abus_read_ms;
abus_write_buf <= abus_write_ms;
abus_writeneg0_trail(0) <= abus_writeneg_ms(0);
abus_writeneg1_trail(0) <= abus_writeneg_ms(1);
end if;
end process;
--excluding metastability protection is a bad behavior
--but it looks like we're out of more options to optimize read pipeline
--abus_read_ms <= abus_read;
--abus_read_buf <= abus_read_ms;
--abus read/write latch
process (clock)
begin
if rising_edge(clock) then
abus_write_buf2 <= abus_write_buf;
abus_chipselect_buf2 <= abus_chipselect_p2;
abus_anypulse2 <= abus_anypulse;
abus_anypulse3 <= abus_anypulse2;
for i in 0 to (ABUS_TRAILS_SIZE-2) loop
abus_cspulse_trail (i+1) <= abus_cspulse_trail (i);
abus_read_trail (i+1) <= abus_read_trail (i);
abus_writeneg0_trail(i+1) <= abus_writeneg0_trail(i);
abus_writeneg1_trail(i+1) <= abus_writeneg1_trail(i);
end loop;
end if;
end process;
--abus write/read pulse is a falling edge since read and write signals are negative polarity
abus_write_pulse_dmy <= abus_write_buf2 and not abus_write_buf;
abus_read_pulse_dmy <= abus_read_trail(1) and not abus_read_trail(0);
--abus_chipselect_pulse <= abus_chipselect_buf2 and not abus_chipselect_p2;
abus_chipselect_pulse <= abus_chipselect_p2 and not abus_chipselect_p1;
abus_write_pulse_off <= abus_write_buf and not abus_write_buf2;
abus_read_pulse_off <= abus_read_trail(0) and not abus_read_trail(1);
abus_chipselect_pulse_off <= abus_chipselect_p2 and not abus_chipselect_buf2;
abus_anypulse <= abus_write_pulse_dmy(0)
or abus_write_pulse_dmy(1)
or abus_read_pulse_dmy
or abus_chipselect_pulse(0)
or abus_chipselect_pulse(1)
or abus_chipselect_pulse(2);
abus_anypulse_off <= abus_write_pulse_off(0)
or abus_write_pulse_off(1)
or abus_read_pulse_off
or abus_chipselect_pulse_off(0)
or abus_chipselect_pulse_off(1)
or abus_chipselect_pulse_off(2);
abus_cspulse_trail(0) <= abus_chipselect_pulse(0)
or abus_chipselect_pulse(1)
or abus_chipselect_pulse(2);
abus_cspulse_off <= abus_chipselect_pulse_off(0)
or abus_chipselect_pulse_off(1)
or abus_chipselect_pulse_off(2);
-- Transaction counter update
--
-- Concept
-- | - It is assumed that CS0~1 lines become active last and that RD/WR/ADDR/DATA lines are setup before that moment.
-- | -> should need to measure that for real with OLS !
-- | -> Timeline is as follow :
-- | abus_chipselect_p2 (two clocks before)
-- | abus_chipselect_p1 (one clock before)
-- | abus_chipselect (latest)
-- | - Let's wait for one MAX 10 internal (116 MHz) clock after CS is active and start sampling other signals.
-- | - During write transaction (write from Saturn to cartridge), data is demuxed during two clocks : this may not be needed but seems safer in a first try.
--
--
-- COMMON
-- | - Retrieve read/write type and latch full address
--
-- CARTRIDGE READ FROM SATURN
-- | - If register, process it immediately
-- | - If SDRAM or OCRAM, start transaction and wait until read is valid
--
-- CARTRIDGE WRITE FROM SATURN
-- | - Multiplex data/address to retrieve write data
-- | - If register, process it immediately
-- | - If SDRAM or OCRAM, start transaction and hold it until write is terminated
--
-- Rules about mutiplexer control :
-- 1. Control with transaction counter, because in incremented during CS activity.
-- 2. Keep enough clocks at the beginning of CS activity to retrieve full address, and data if needed.
-- 3. After that, select and hold (until transaction counter becomes zero) appropriate bus direction.
process (clock)
begin
if rising_edge(clock) then
if saturn_reset = '0' then
abus_trcntr <= x"0"; -- Return to idle state during Saturn reset
else
if abus_trcntr = x"0" then
if ((abus_chipselect_p2(0) = '1') and (abus_chipselect_p2(1) = '1')
and ((abus_chipselect_p1(0) = '0') or (abus_chipselect_p1(1) = '0'))) then
abus_trcntr <= x"1"; -- Transaction startup
else
abus_trcntr <= x"0";
end if;
else
if (abus_chipselect(0) = '1') and (abus_chipselect(1) = '1') then
abus_trcntr <= x"0"; -- Return to idle state when CS returns to idle
else
if abus_trcntr = x"F" then
abus_trcntr <= x"F"; -- Hold counter to max until CS returns to idle
else
abus_trcntr <= abus_trcntr + x"1"; -- Go to next state
end if;
end if;
end if;
end if;
end if;
end process;
sim_test2_internal(3 downto 0) <= abus_trcntr(3 downto 0);
--whatever pulse we've got, latch address
--it might be latched twice per transaction, but it's not a problem
--multiplexer was switched to address after previous transaction or after boot,
--so we have address ready to latch
process (clock)
begin
if rising_edge(clock) then
if abus_trcntr = x"0" then
demux_readpulse <= '0';
demux_writepulse <= '0';
elsif abus_trcntr = x"1" then
-- Latch access base signals
abus_chipselect_latched <= abus_chipselect;
abus_read_latched <= abus_read;
abus_write_latched <= abus_write;
-- Generate read pulse (1/2)
if abus_read = '0' then
demux_readpulse <= '1';
end if;
elsif abus_trcntr = x"2" then
-- Generate read pulse (2/2)
if my_little_transaction_dir = DIR_READ then
demux_readpulse <= '0';
end if;
elsif abus_trcntr = x"4" then
-- Retrieve multiplexed data for write transaction, and generate write pulse
if my_little_transaction_dir = DIR_WRITE then
demux_writedata <= abus_data_in;
demux_writepulse <= '1';
end if;
elsif abus_trcntr = x"5" then
-- Terminate write pulse
if my_little_transaction_dir = DIR_WRITE then
demux_writepulse <= '0';
end if;
end if;
end if;
end process;
-- De-shuffle address
process(abus_address_latched, abus_address, abus_addressdata)
begin
if(abus_muxing_internal = "01") then
--if(abus_read = '1') then
-- 2019/07/20 : this is now adapted for "SIM to MAX 10 Board",
-- which allows multiplexing simpler than on cartridge
abus_address_latched <=
abus_address(7) -- abus_address(8) ignored ?!
& abus_address(6)
& abus_address(5)
& abus_address(4)
& abus_address(3)
& abus_address(2)
& abus_address(1)
& abus_address(0) -- TOP ADDRESS ^^^
& abus_addressdata(15) -- MUX vvv
& abus_addressdata(14)
& abus_addressdata(13)
& abus_addressdata(12)
& abus_addressdata(11)
& abus_addressdata(10)
& abus_addressdata( 9)
& abus_addressdata( 8)
& abus_addressdata( 7)
& abus_addressdata( 6)
& abus_addressdata( 5)
& abus_addressdata( 4)
& abus_addressdata( 3)
& abus_addressdata( 2)
& abus_addressdata( 1)
& abus_addressdata( 0);
--Purpose of A0 line in PCB Rev 1.3 is unknown and consequently
--have to be ignored when building address. Instead, address
--top bit is stuffed with '0'.
--Address Mapping for U4 : And for U1 : (In PCB Rev 1.3) abus_address_latched <= abus_address
-- A13 -> MUX12 A0 -> MUX0 & abus_addressdata(11) -- A14
-- A6 -> MUX13 A9 -> MUX1 & abus_addressdata(12) -- A13
-- A5 -> MUX14 A10 -> MUX2 & abus_addressdata( 9) -- A12
-- A4 -> MUX15 A8 -> MUX3 & abus_addressdata(10) -- A11
-- A3 -> MUX4 A7 -> MUX8 & abus_addressdata( 2) -- A10
-- A2 -> MUX5 A12 -> MUX9 & abus_addressdata( 1) -- A9
-- A1 -> MUX6 A11 -> MUX10 & abus_addressdata( 3) -- A8
-- DMY -> MUX7 A14 -> MUX11 & abus_addressdata( 8) -- A7
--Which gives the following order for de-shuffling address : & abus_addressdata(13) -- A6
-- A14 -> MUX11 & abus_addressdata(14) -- A5
-- A13 -> MUX12 & abus_addressdata(15) -- A4
-- A12 -> MUX9 & abus_addressdata( 4) -- A3
-- A11 -> MUX10 & abus_addressdata( 5) -- A2
-- A10 -> MUX2 & abus_addressdata( 6) -- A1
-- A9 -> MUX1 & abus_addressdata( 0); -- A0
-- A8 -> MUX3
-- A7 -> MUX8
-- A6 -> MUX13
-- A5 -> MUX14
-- A4 -> MUX15
-- A3 -> MUX4
-- A2 -> MUX5
-- A1 -> MUX6
-- A0 -> MUX0
end if;
end process;
-- Update the following "static" informations while idle :
-- - Demuxed address, including CS0~1
-- - Write byte enable
process (clock)
begin
if rising_edge(clock) then
-- Address and CS0~1
if abus_trcntr = x"1" then
--if((clock = '1') and ((abus_trcntr = x"0") or (abus_trcntr = x"1")))then
-- Put both address itself and chipselect on the same demuxed address
-- Upper bits of demuxed address are currently unused and reserved for eventual future purpose.
--
-- And, separate address for both write and read access, so that write operation
-- have more chances to terminate even when read operation starts just after.
if(abus_read = '0') then
demux_readaddress(27) <= '0';
demux_readaddress(26) <= '0';
if abus_chipselect(0) = '0' then
demux_readaddress(25 downto 24) <= "00";
elsif abus_chipselect(1) = '0' then
demux_readaddress(25 downto 24) <= "01";
elsif abus_chipselect(2) = '0' then
demux_readaddress(25 downto 24) <= "10";
else
demux_readaddress(25 downto 24) <= "11"; -- Shouldn't happen since transaction is initiated when activity on CS is detected.
end if;
demux_readaddress(23 downto 0) <= abus_address_latched(23 downto 0);
else
demux_writeaddress(27) <= '0';
demux_writeaddress(26) <= '0';
if abus_chipselect(0) = '0' then
demux_writeaddress(25 downto 24) <= "00";
elsif abus_chipselect(1) = '0' then
demux_writeaddress(25 downto 24) <= "01";
elsif abus_chipselect(2) = '0' then
demux_writeaddress(25 downto 24) <= "10";
else
demux_writeaddress(25 downto 24) <= "11"; -- Shouldn't happen since transaction is initiated when activity on CS is detected.
end if;
demux_writeaddress(23 downto 0) <= abus_address_latched(23 downto 0);
end if;
end if;
end if;
end process;
process (clock)
begin
if saturn_reset = '0' then
demux_write_byteenable(0) <= '0';
demux_write_byteenable(1) <= '0';
else
-- Write byte enable
-- Keep holding it even while read operation started,
-- so that eventual ongoing write operation have more
-- chances to terminate correctly.
if((abus_trcntr = x"1") and (abus_read = '1'))then
demux_write_byteenable(0) <= not abus_write(0);
demux_write_byteenable(1) <= not abus_write(1);
end if;
end if;
end process;
-- If valid transaction captured, switch to corresponding multiplex mode
process (clock)
begin
if rising_edge(clock) then
if((abus_trcntr = x"0") or ((abus_chipselect(0) = '1') and (abus_chipselect(1) = '1')))then
abus_direction_internal <= '0' ; --high-z
abus_muxing_internal <= "01"; --address
elsif abus_trcntr = x"1" then
if abus_read = '0' then
abus_direction_internal <= '1' ; --active
abus_muxing_internal <= "10"; --data
else
abus_direction_internal <= '0' ; --high-z
abus_muxing_internal <= "10"; --data
end if;
elsif abus_trcntr = x"2" then
if abus_read = '0' then
abus_direction_internal <= '1' ; --active
abus_muxing_internal <= "10"; --data
else
abus_direction_internal <= '0' ; --high-z
abus_muxing_internal <= "10"; --data
end if;
-- Long multiplexer TEST vvv
-- Note 2019/12/13 : multiplexing during 1~2 is necessary for Wasca on real Hardware.
-- And so far it wasn't verified if multiplexing during 3 is necessary for MAX 10 Board r0.7 (b).
-- elsif abus_trcntr = x"3" then
-- if abus_read = '0' then
-- abus_direction_internal <= '1' ; --active
-- abus_muxing_internal <= "10"; --data
-- else
-- abus_direction_internal <= '0' ; --high-z
-- abus_muxing_internal <= "10"; --data
-- end if;
-- Long multiplexer TEST ^^^
else
if my_little_transaction_dir = DIR_READ then
abus_direction_internal <= '1' ; --active
abus_muxing_internal <= "10"; --data
else --if my_little_transaction_dir = DIR_READ then
abus_direction_internal <= '0' ; --high-z
abus_muxing_internal <= "01"; --address
end if;
end if;
end if;
end process;
abus_direction <= abus_direction_internal;
abus_muxing <= not abus_muxing_internal;
-- Update access direction
process (clock)
begin
if rising_edge(clock) then
if((abus_chipselect(0) = '1') and (abus_chipselect(1) = '1'))then
my_little_transaction_dir <= DIR_NONE;
abus_writing <= '0';
abus_reading <= '0';
elsif abus_trcntr = x"1" then
-- Decide access direction, and hold it until end of transaction
if abus_read = '0' then
my_little_transaction_dir <= DIR_READ;
abus_writing <= '0';
abus_reading <= '1';
else --if abus_read_ms = '0' then
my_little_transaction_dir <= DIR_WRITE;
abus_writing <= '1';
abus_reading <= '0';
end if;
end if;
end if;
end process;
-- Generate a reading/writing pulse during access
process (clock)
begin
if rising_edge(clock) then
if abus_trcntr = x"0" then
abus_write_pulse <= '0'; -- No access during idle state
abus_read_pulse <= '0'; -- No access during idle state
elsif abus_trcntr = x"1" then
if abus_write(0) = '0' or abus_write(1) = '0' then
abus_write_pulse <= '0'; -- Wait to receive data during a write transaction
abus_read_pulse <= '0';
else --if abus_read_ms = '0' then
abus_write_pulse <= '0';
abus_read_pulse <= '1'; -- Generate a read pulse when full address is received
end if;
elsif abus_trcntr = x"2" then
if my_little_transaction_dir = DIR_WRITE then
abus_write_pulse <= '1'; -- Generate a write pulse when both full address and data are received
abus_read_pulse <= '0';
else --if my_little_transaction_dir = DIR_READ then
abus_write_pulse <= '0';
abus_read_pulse <= '0'; -- Read transaction falling edge
end if;
elsif abus_trcntr = x"3" then
abus_read_pulse <= '0'; -- Write transaction falling edge
abus_write_pulse <= '0';
if my_little_transaction_dir = DIR_WRITE then
else --if my_little_transaction_dir = DIR_READ then
end if;
else
abus_read_pulse <= '0'; -- Write transaction falling edge
abus_write_pulse <= '0';
if my_little_transaction_dir = DIR_WRITE then
else --if my_little_transaction_dir = DIR_READ then
end if;
end if;
-- Delay write related signals
abus_writing_trail (0) <= abus_writing;
abus_write_pulse_trail(0) <= abus_write_pulse;
for i in 0 to (ABUS_TRAILS_SIZE-2) loop
abus_writing_trail (i+1) <= abus_writing_trail (i);
abus_write_pulse_trail(i+1) <= abus_write_pulse_trail(i);
end loop;
end if;
end process;
sim_test2_internal(7) <= abus_write_pulse_trail(3);
sim_test2_internal(6) <= abus_write_pulse_trail(2);
sim_test2_internal(5) <= abus_write_pulse_trail(1);
sim_test2_internal(4) <= abus_write_pulse_trail(0);
---------------------------------------------------------------------------------------
-- Update buffer data when read data valid pulse if detected
-- Read data valid pulse may not be super necessary, but this is provided by Avalon,
-- and may be helpful when counting clocks elapsed during read access.
--
process (abus_reading) begin
abus_data_out <= demux_readdata; -- Faster than below
if rising_edge(clock) then
if(demux_readdatavalid = '1') then
--abus_data_out <= demux_readdata;
end if;
end if;
end process;
---------------------------------------------------------------------------------------
-- In/Out process
--
-- Access from each CS0-2 is handled from this chip.
-- In the future, it may be required to manage access to external FTDI chip ?
--
process (abus_reading) begin
--if rising_edge(clock) then
--if(abus_reading = '1') then
if(abus_read = '0') then
-- Output to data bus
abus_addressdata <= abus_data_out;
--abus_addressdata <= x"ABCD";
--sim_test2_internal <= x"CA";
abus_data_in <= abus_addressdata;
else
-- Disable output to data bus
abus_addressdata <= "ZZZZZZZZZZZZZZZZ";
abus_data_in <= abus_addressdata;
--sim_test2_internal <= x"FF";
end if;
--end if;
end process;
sim_test1_internal(7) <= abus_writing;
sim_test1_internal(6) <= abus_reading;
sim_test1_internal(5) <= abus_write_pulse;
sim_test1_internal(4) <= abus_read_pulse;
sim_test1_internal(3) <= abus_writing_trail(0);
sim_test1_internal(2) <= abus_writing_trail(1);
sim_test1_internal(1) <= abus_writing_trail(2);
sim_test1_internal(0) <= '1';
-- "disable_out" controls refresh timing of wait and IRQ signals
-- 0:output, 1:hold previous
--abus_disable_out <= '1' when abus_chipselect_number(1) = '1' else '0';
abus_disable_out <= '0';
-- Let's completely neglect usage of wait request signal for now, and ... hope that
-- SDRAM controller is smarter enough to do things timely.
-- (Spoiler : SDRAM controller is completely dumb)
abus_waitrequest <= '1';
-- process (clock)
-- begin
-- if rising_edge(clock) then
-- abus_waitrequest_read2 <= abus_waitrequest_read1;
-- abus_waitrequest_write2 <= abus_waitrequest_write1;
-- end if;
-- end process;
--
-- process (clock)
-- begin
-- if rising_edge(clock) then
-- abus_waitrequest_read_off <= '0';
-- abus_waitrequest_write_off <= '0';
-- if abus_waitrequest_read1 = '0' and abus_waitrequest_read2 = '1' then
-- abus_waitrequest_read_off <= '1';
-- end if;
-- if abus_waitrequest_write1 = '0' and abus_waitrequest_write2 = '1' then
-- abus_waitrequest_write_off <= '1';
-- end if;
-- end if;
-- end process;
--
-- --process (clock)
-- --begin
-- -- if rising_edge(clock) then
-- -- --if abus_read_pulse_dmy='1' or abus_write_pulse_dmy(0)='1' or abus_write_pulse_dmy(1)='1' then
-- -- --if abus_anypulse = '1' then
-- -- if abus_chipselect_pulse(0) = '1' or abus_chipselect_pulse(1) = '1' then
-- -- abus_waitrequest <= '0';
-- -- elsif abus_waitrequest_read_off='1' or abus_waitrequest_write_off='1' then
-- -- abus_waitrequest <= '1';
-- -- end if;
-- -- end if;
-- --end process;
--
-- abus_waitrequest <= not (abus_waitrequest_read1 or abus_waitrequest_write1);
--Nios II read interface
process (clock)
begin
if rising_edge(clock) then
if avalon_nios_read = '1' then
avalon_nios_readdatavalid <= '1';
case avalon_nios_address is
-- Debug stuff around Rd/Wr access
when X"00" =>
avalon_nios_readdata <= x"CA0000" & rd_access_cntr;
when X"01" =>
avalon_nios_readdata <= x"FE0000" & wr_access_cntr;
when X"10" =>
avalon_nios_readdata <= x"0000" & REG_PCNTR;
when X"11" =>
avalon_nios_readdata <= x"0000" & REG_STATUS;
when X"12" =>
avalon_nios_readdata <= x"0000" & REG_MODE;
when X"13" =>
avalon_nios_readdata <= x"0000" & REG_HWVER;
when X"14" =>
avalon_nios_readdata <= x"0000" & REG_SWVER;
when X"15" =>
avalon_nios_readdata <= X"0000ABCD"; --for debug, remove later
when others =>
avalon_nios_readdata <= x"00000000";
end case;
else
avalon_nios_readdatavalid <= '0';
end if;
end if;
end process;
--Nios II write interface
process (clock)
begin
if rising_edge(clock) then
if avalon_nios_write= '1' then
case avalon_nios_address is
when X"10" =>
REG_PCNTR <= avalon_nios_writedata(15 downto 0);
when X"11" =>
REG_STATUS <= avalon_nios_writedata(15 downto 0);
when X"12" =>
null;
when X"13" =>
null;
when X"14" =>
REG_SWVER <= avalon_nios_writedata(15 downto 0);
when others =>
null;
end case;
end if;
end if;
end process;
--Nios system interface is only regs, so always ready to write.
avalon_nios_waitrequest <= '0';
-- -- External signals used for simulation vvv
-- sim_test1 <= sim_test1_internal;
-- sim_test2 <= sim_test2_internal;
-- abus_cspulse_trail_dbg <= abus_cspulse_trail;
-- abus_read_trail_dbg <= abus_read_trail;
-- abus_writeneg0_trail_dbg <= abus_writeneg0_trail;
-- abus_writeneg1_trail_dbg <= abus_writeneg1_trail;
-- abus_addresslatched_dbg <= abus_address_latched;
-- -- External signals used for simulation ^^^
end architecture rtl; -- of abus_demux
| gpl-2.0 | 231d6946db34b9b4250f79d19d5ddd22 | 0.484361 | 4.15329 | false | false | false | false |
impedimentToProgress/UCI-BlueChip | AttackFiles/Attacks/privEsc/lib/gleichmann/miscellaneous/clockgenerator.vhd | 2 | 3,312 | --------------------------------------------------------------------------------
-- Project : Sandbox
-- Module : ClockGenerator
-- File : ClockGenerator.vhd
-- Description : Generate the clocks for the AudioCodec.
--------------------------------------------------------------------------------
-- Author : Andreas Voggeneder
-- Organisation : FH-Hagenberg
-- Department : Hardware/Software Systems Engineering
-- Language : VHDL'87
--------------------------------------------------------------------------------
-- Copyright (c) 2003 by Andreas Voggeneder
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--use work.CodecGlobal.all;
entity ClockGenerator is
port (
Clk : in std_ulogic;
Reset : in std_ulogic;
oMCLK : out std_ulogic; -- 12 MHz
oBCLK : out std_ulogic; -- I2S bit clk
oSCLK : out std_ulogic; -- SPI Data Clk
oLRCOUT : out std_ulogic);
end ClockGenerator;
architecture rtl of ClockGenerator is
constant cResetActive : std_ulogic := '0';
begin -- rtl
createclock : process (Clk, Reset)
-- variable cntMCLK : std_ulogic; -- counter MCLK
variable cntBCLK : std_ulogic; -- counter BCLK
variable cntLRC : unsigned(5 downto 0); -- counter LRC
variable internalMCLK : std_ulogic;
variable internalBCLK : std_ulogic;
variable internalSCLK : std_ulogic; --_vector(1 downto 0);
variable internalLRCOUT : std_ulogic;
begin -- process createclock
if Reset = cResetActive then -- asynchronous reset
internalMCLK := '0';
internalBCLK := '0';
internalSCLK := '0'; --"00";
internalLRCOUT := '1';
-- cntMCLK := '0';
cntBCLK := '0';
cntLRC := (others => '0');
elsif Clk'event and Clk = '1' then -- rising clock edge
internalSCLK := not (internalSCLK);
-- internalSCLK := std_ulogic_vector(unsigned(internalSCLK)+1);
-- if (cntMCLK = '1') then
-- cntMCLK := '0';
internalMCLK := not internalMCLK; -- 25/2
if (internalMCLK = '1') then
-- == 25/2
if (cntBCLK = '1') then
-- == 25/4
internalBCLK := not internalBCLK; --25/8
cntBCLK := '0';
if (internalBCLK = '0') then
if (cntLRC = "100001") then -- 33
internalLRCOUT := not internalLRCOUT;
cntLRC := (others => '0');
else
cntLRC := cntLRC + 1;
end if;
end if;
else
cntBCLK := '1';
end if;
end if;
-- else
-- cntMCLK := '1';
-- end if;
end if;
oMCLK <= internalMCLK;
oBCLK <= internalBCLK;
oSCLK <= internalSCLK; --(1);
oLRCOUT <= internalLRCOUT;
end process createclock;
end rtl;
-- 44,1kHz: Fs=44100
-- MCLK = 256*Fs = 11.2896 MHz. Gewählt 12.5 MHz
-- BCLK = Fs*2*32 = 2.82 MHz. Gewählt 3.125 MHz
-- => Fs real = 48.8 kHz
| mit | cb711e4b4e81b8797d5b4182acffcec3 | 0.466787 | 4.088889 | false | false | false | false |
michaelfivez/ascon_hardware_implementation | ascon12864_unrolled6/API_plus_CipherCore/regn.vhd | 9 | 1,612 | -------------------------------------------------------------------------------
--! @file regn.vhd
--! @brief Register with init value
--! @project CAESAR Candidate Evaluation
--! @author CERG @ GMU
--! @copyright Copyright (c) 2015 Cryptographic Engineering Research Group
--! ECE Department, George Mason University Fairfax, VA, U.S.A.
--! All rights Reserved.
--! @license This project is released under the GNU Public License.
--! The license and distribution terms for this file may be
--! found in the file LICENSE in this distribution or at
--! http://www.gnu.org/licenses/gpl-3.0.txt
--! @note This is publicly available encryption source code that falls
--! under the License Exception TSU (Technology and software-
--! unrestricted)
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity regn is
generic (
N : integer := 32;
init : std_logic_vector
);
port (
clk : in std_logic;
rst : in std_logic;
en : in std_logic;
input : in std_logic_vector(N-1 downto 0);
output : out std_logic_vector(N-1 downto 0)
);
end regn;
architecture struct of regn is
--signal reg : std_logic_vector(N-1 downto 0);
begin
gen : process( clk )
begin
if rising_edge( clk ) then
if ( rst = '1' ) then
output <= init;
elsif ( en = '1' ) then
output<= input;
end if;
end if;
end process;
--output <= reg;
end struct; | gpl-3.0 | 02dd20548e71269a60f15972fce0df0b | 0.53536 | 3.784038 | false | false | false | false |
impedimentToProgress/UCI-BlueChip | VhdlParser/test/resultPrivEsc.vhd | 1 | 138,217 | LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;
LIBRARY grlib;
USE grlib.sparc.all;
USE grlib.stdlib.all;
LIBRARY techmap;
USE techmap.gencomp.all;
LIBRARY gaisler;
USE gaisler.leon3.all;
USE gaisler.libiu.all;
USE gaisler.arith.all;
USE grlib.sparc_disas.all;
ENTITY iu3 IS
GENERIC (
nwin : integer RANGE 2 to 32 := 8;
isets : integer RANGE 1 to 4 := 2;
dsets : integer RANGE 1 to 4 := 2;
fpu : integer RANGE 0 to 15 := 0;
v8 : integer RANGE 0 to 63 := 2;
cp : integer RANGE 0 to 1 := 0;
mac : integer RANGE 0 to 1 := 0;
dsu : integer RANGE 0 to 1 := 1;
nwp : integer RANGE 0 to 4 := 2;
pclow : integer RANGE 0 to 2 := 2;
notag : integer RANGE 0 to 1 := 0;
index : integer RANGE 0 to 15 := 0;
lddel : integer RANGE 1 to 2 := 1;
irfwt : integer RANGE 0 to 1 := 1;
disas : integer RANGE 0 to 2 := 0;
tbuf : integer RANGE 0 to 64 := 2;
pwd : integer RANGE 0 to 2 := 0;
svt : integer RANGE 0 to 1 := 1;
rstaddr : integer := 16#00000#;
smp : integer RANGE 0 to 15 := 0;
fabtech : integer RANGE 0 to NTECH := 2;
clk2x : integer := 0
);
PORT (
clk : in std_ulogic;
rstn : in std_ulogic;
holdn : in std_ulogic;
ici : out icache_in_type;
ico : in icache_out_type;
dci : out dcache_in_type;
dco : in dcache_out_type;
rfi : out iregfile_in_type;
rfo : in iregfile_out_type;
irqi : in l3_irq_in_type;
irqo : out l3_irq_out_type;
dbgi : in l3_debug_in_type;
dbgo : out l3_debug_out_type;
muli : out mul32_in_type;
mulo : in mul32_out_type;
divi : out div32_in_type;
divo : in div32_out_type;
fpo : in fpc_out_type;
fpi : out fpc_in_type;
cpo : in fpc_out_type;
cpi : out fpc_in_type;
tbo : in tracebuf_out_type;
tbi : out tracebuf_in_type;
sclk : in std_ulogic
);
END ENTITY;
ARCHITECTURE rtl OF iu3 IS
CONSTANT ISETMSB : integer := log2x ( 2 ) - 1;
CONSTANT DSETMSB : integer := log2x ( 2 ) - 1;
CONSTANT RFBITS : integer RANGE 6 to 10 := log2 ( 8 + 1 ) + 4;
CONSTANT NWINLOG2 : integer RANGE 1 to 5 := log2 ( 8 );
CONSTANT CWPOPT : boolean := ( 8 = ( 2 ** LOG2 ( 8 ) ) );
CONSTANT CWPMIN : std_logic_vector ( LOG2 ( 8 ) - 1 downto 0 ) := ( OTHERS => '0' );
CONSTANT CWPMAX : std_logic_vector ( LOG2 ( 8 ) - 1 downto 0 ) := conv_std_logic_vector ( 8 - 1 , LOG2 ( 8 ) );
CONSTANT FPEN : boolean := ( 0 /= 0 );
CONSTANT CPEN : boolean := ( 0 = 1 );
CONSTANT MULEN : boolean := ( 2 /= 0 );
CONSTANT MULTYPE : integer := ( 2 / 16 );
CONSTANT DIVEN : boolean := ( 2 /= 0 );
CONSTANT MACEN : boolean := ( 0 = 1 );
CONSTANT MACPIPE : boolean := ( 0 = 1 ) and ( 2 / 2 = 1 );
CONSTANT IMPL : integer := 15;
CONSTANT VER : integer := 3;
CONSTANT DBGUNIT : boolean := ( 1 = 1 );
CONSTANT TRACEBUF : boolean := ( 2 /= 0 );
CONSTANT TBUFBITS : integer := 10 + log2 ( 2 ) - 4;
CONSTANT PWRD1 : boolean := false;
CONSTANT PWRD2 : boolean := 0 /= 0;
CONSTANT RS1OPT : boolean := ( is_fpga ( 2 ) /= 0 );
SUBTYPE word IS std_logic_vector ( 31 downto 0 );
SUBTYPE pctype IS std_logic_vector ( 31 downto 2 );
SUBTYPE rfatype IS std_logic_vector ( LOG2 ( 8 + 1 ) + 4 - 1 downto 0 );
SUBTYPE cwptype IS std_logic_vector ( LOG2 ( 8 ) - 1 downto 0 );
TYPE icdtype IS ARRAY ( 0 to 2 - 1 ) OF word;
TYPE dcdtype IS ARRAY ( 0 to 2 - 1 ) OF word;
SUBTYPE cword IS std_logic_vector ( 32 - 1 downto 0 );
TYPE cdatatype IS ARRAY ( 0 to 3 ) OF cword;
TYPE cpartype IS ARRAY ( 0 to 3 ) OF std_logic_vector ( 3 downto 0 );
TYPE iregfile_in_type IS RECORD
raddr1 : std_logic_vector ( 9 downto 0 );
raddr2 : std_logic_vector ( 9 downto 0 );
waddr : std_logic_vector ( 9 downto 0 );
wdata : std_logic_vector ( 31 downto 0 );
ren1 : std_ulogic;
ren2 : std_ulogic;
wren : std_ulogic;
diag : std_logic_vector ( 3 downto 0 );
END RECORD;
TYPE iregfile_out_type IS RECORD
data1 : std_logic_vector ( RDBITS - 1 downto 0 );
data2 : std_logic_vector ( RDBITS - 1 downto 0 );
END RECORD;
TYPE cctrltype IS RECORD
burst : std_ulogic;
dfrz : std_ulogic;
ifrz : std_ulogic;
dsnoop : std_ulogic;
dcs : std_logic_vector ( 1 downto 0 );
ics : std_logic_vector ( 1 downto 0 );
END RECORD;
TYPE icache_in_type IS RECORD
rpc : std_logic_vector ( 31 downto 0 );
fpc : std_logic_vector ( 31 downto 0 );
dpc : std_logic_vector ( 31 downto 0 );
rbranch : std_ulogic;
fbranch : std_ulogic;
inull : std_ulogic;
su : std_ulogic;
flush : std_ulogic;
flushl : std_ulogic;
fline : std_logic_vector ( 31 downto 3 );
pnull : std_ulogic;
END RECORD;
TYPE icache_out_type IS RECORD
data : cdatatype;
set : std_logic_vector ( 1 downto 0 );
mexc : std_ulogic;
hold : std_ulogic;
flush : std_ulogic;
diagrdy : std_ulogic;
diagdata : std_logic_vector ( IDBITS - 1 downto 0 );
mds : std_ulogic;
cfg : std_logic_vector ( 31 downto 0 );
idle : std_ulogic;
END RECORD;
TYPE icdiag_in_type IS RECORD
addr : std_logic_vector ( 31 downto 0 );
enable : std_ulogic;
read : std_ulogic;
tag : std_ulogic;
ctx : std_ulogic;
flush : std_ulogic;
ilramen : std_ulogic;
cctrl : cctrltype;
pflush : std_ulogic;
pflushaddr : std_logic_vector ( VA_I_U downto VA_I_D );
pflushtyp : std_ulogic;
ilock : std_logic_vector ( 0 to 3 );
scanen : std_ulogic;
END RECORD;
TYPE dcache_in_type IS RECORD
asi : std_logic_vector ( 7 downto 0 );
maddress : std_logic_vector ( 31 downto 0 );
eaddress : std_logic_vector ( 31 downto 0 );
edata : std_logic_vector ( 31 downto 0 );
size : std_logic_vector ( 1 downto 0 );
enaddr : std_ulogic;
eenaddr : std_ulogic;
nullify : std_ulogic;
lock : std_ulogic;
read : std_ulogic;
write : std_ulogic;
flush : std_ulogic;
flushl : std_ulogic;
dsuen : std_ulogic;
msu : std_ulogic;
esu : std_ulogic;
intack : std_ulogic;
END RECORD;
TYPE dcache_out_type IS RECORD
data : cdatatype;
set : std_logic_vector ( 1 downto 0 );
mexc : std_ulogic;
hold : std_ulogic;
mds : std_ulogic;
werr : std_ulogic;
icdiag : icdiag_in_type;
cache : std_ulogic;
idle : std_ulogic;
scanen : std_ulogic;
testen : std_ulogic;
END RECORD;
TYPE tracebuf_in_type IS RECORD
addr : std_logic_vector ( 11 downto 0 );
data : std_logic_vector ( 127 downto 0 );
enable : std_logic;
write : std_logic_vector ( 3 downto 0 );
diag : std_logic_vector ( 3 downto 0 );
END RECORD;
TYPE tracebuf_out_type IS RECORD
data : std_logic_vector ( 127 downto 0 );
END RECORD;
TYPE l3_irq_in_type IS RECORD
irl : std_logic_vector ( 3 downto 0 );
rst : std_ulogic;
run : std_ulogic;
END RECORD;
TYPE l3_irq_out_type IS RECORD
intack : std_ulogic;
irl : std_logic_vector ( 3 downto 0 );
pwd : std_ulogic;
END RECORD;
TYPE l3_debug_in_type IS RECORD
dsuen : std_ulogic;
denable : std_ulogic;
dbreak : std_ulogic;
step : std_ulogic;
halt : std_ulogic;
reset : std_ulogic;
dwrite : std_ulogic;
daddr : std_logic_vector ( 23 downto 2 );
ddata : std_logic_vector ( 31 downto 0 );
btrapa : std_ulogic;
btrape : std_ulogic;
berror : std_ulogic;
bwatch : std_ulogic;
bsoft : std_ulogic;
tenable : std_ulogic;
timer : std_logic_vector ( 30 downto 0 );
END RECORD;
TYPE l3_debug_out_type IS RECORD
data : std_logic_vector ( 31 downto 0 );
crdy : std_ulogic;
dsu : std_ulogic;
dsumode : std_ulogic;
error : std_ulogic;
halt : std_ulogic;
pwd : std_ulogic;
idle : std_ulogic;
ipend : std_ulogic;
icnt : std_ulogic;
END RECORD;
TYPE l3_debug_in_vector IS ARRAY ( natural RANGE <> ) OF l3_debug_in_type;
TYPE l3_debug_out_vector IS ARRAY ( natural RANGE <> ) OF l3_debug_out_type;
TYPE div32_in_type IS RECORD
y : std_logic_vector ( 32 downto 0 );
op1 : std_logic_vector ( 32 downto 0 );
op2 : std_logic_vector ( 32 downto 0 );
flush : std_logic;
signed : std_logic;
start : std_logic;
END RECORD;
TYPE div32_out_type IS RECORD
ready : std_logic;
nready : std_logic;
icc : std_logic_vector ( 3 downto 0 );
result : std_logic_vector ( 31 downto 0 );
END RECORD;
TYPE mul32_in_type IS RECORD
op1 : std_logic_vector ( 32 downto 0 );
op2 : std_logic_vector ( 32 downto 0 );
flush : std_logic;
signed : std_logic;
start : std_logic;
mac : std_logic;
acc : std_logic_vector ( 39 downto 0 );
END RECORD;
TYPE mul32_out_type IS RECORD
ready : std_logic;
nready : std_logic;
icc : std_logic_vector ( 3 downto 0 );
result : std_logic_vector ( 63 downto 0 );
END RECORD;
TYPE fp_rf_in_type IS RECORD
rd1addr : std_logic_vector ( 3 downto 0 );
rd2addr : std_logic_vector ( 3 downto 0 );
wraddr : std_logic_vector ( 3 downto 0 );
wrdata : std_logic_vector ( 31 downto 0 );
ren1 : std_ulogic;
ren2 : std_ulogic;
wren : std_ulogic;
END RECORD;
TYPE fp_rf_out_type IS RECORD
data1 : std_logic_vector ( 31 downto 0 );
data2 : std_logic_vector ( 31 downto 0 );
END RECORD;
TYPE fpc_pipeline_control_type IS RECORD
pc : std_logic_vector ( 31 downto 0 );
inst : std_logic_vector ( 31 downto 0 );
cnt : std_logic_vector ( 1 downto 0 );
trap : std_ulogic;
annul : std_ulogic;
pv : std_ulogic;
END RECORD;
TYPE fpc_debug_in_type IS RECORD
enable : std_ulogic;
write : std_ulogic;
fsr : std_ulogic;
addr : std_logic_vector ( 4 downto 0 );
data : std_logic_vector ( 31 downto 0 );
END RECORD;
TYPE fpc_debug_out_type IS RECORD
data : std_logic_vector ( 31 downto 0 );
END RECORD;
TYPE fpc_in_type IS RECORD
flush : std_ulogic;
exack : std_ulogic;
a_rs1 : std_logic_vector ( 4 downto 0 );
d : fpc_pipeline_control_type;
a : fpc_pipeline_control_type;
e : fpc_pipeline_control_type;
m : fpc_pipeline_control_type;
x : fpc_pipeline_control_type;
lddata : std_logic_vector ( 31 downto 0 );
dbg : fpc_debug_in_type;
END RECORD;
TYPE fpc_out_type IS RECORD
data : std_logic_vector ( 31 downto 0 );
exc : std_logic;
cc : std_logic_vector ( 1 downto 0 );
ccv : std_ulogic;
ldlock : std_logic;
holdn : std_ulogic;
dbg : fpc_debug_out_type;
END RECORD;
TYPE grfpu_in_type IS RECORD
start : std_logic;
nonstd : std_logic;
flop : std_logic_vector ( 8 downto 0 );
op1 : std_logic_vector ( 63 downto 0 );
op2 : std_logic_vector ( 63 downto 0 );
opid : std_logic_vector ( 7 downto 0 );
flush : std_logic;
flushid : std_logic_vector ( 5 downto 0 );
rndmode : std_logic_vector ( 1 downto 0 );
req : std_logic;
END RECORD;
TYPE grfpu_out_type IS RECORD
res : std_logic_vector ( 63 downto 0 );
exc : std_logic_vector ( 5 downto 0 );
allow : std_logic_vector ( 2 downto 0 );
rdy : std_logic;
cc : std_logic_vector ( 1 downto 0 );
idout : std_logic_vector ( 7 downto 0 );
END RECORD;
TYPE grfpu_out_vector_type IS ARRAY ( integer RANGE 0 to 7 ) OF grfpu_out_type;
TYPE grfpu_in_vector_type IS ARRAY ( integer RANGE 0 to 7 ) OF grfpu_in_type;
TYPE dc_in_type IS RECORD
signed : std_ulogic;
enaddr : std_ulogic;
read : std_ulogic;
write : std_ulogic;
lock : std_ulogic;
dsuen : std_ulogic;
size : std_logic_vector ( 1 downto 0 );
asi : std_logic_vector ( 7 downto 0 );
END RECORD;
TYPE pipeline_ctrl_type IS RECORD
pc : pctype;
inst : word;
cnt : std_logic_vector ( 1 downto 0 );
rd : rfatype;
tt : std_logic_vector ( 5 downto 0 );
trap : std_ulogic;
annul : std_ulogic;
wreg : std_ulogic;
wicc : std_ulogic;
wy : std_ulogic;
ld : std_ulogic;
pv : std_ulogic;
rett : std_ulogic;
END RECORD;
TYPE fetch_reg_type IS RECORD
pc : pctype;
branch : std_ulogic;
END RECORD;
TYPE decode_reg_type IS RECORD
pc : pctype;
inst : icdtype;
cwp : cwptype;
set : std_logic_vector ( LOG2X ( 2 ) - 1 downto 0 );
mexc : std_ulogic;
cnt : std_logic_vector ( 1 downto 0 );
pv : std_ulogic;
annul : std_ulogic;
inull : std_ulogic;
step : std_ulogic;
END RECORD;
TYPE regacc_reg_type IS RECORD
ctrl : pipeline_ctrl_type;
rs1 : std_logic_vector ( 4 downto 0 );
rfa1 : rfatype;
rfa2 : rfatype;
rsel1 : std_logic_vector ( 2 downto 0 );
rsel2 : std_logic_vector ( 2 downto 0 );
rfe1 : std_ulogic;
rfe2 : std_ulogic;
cwp : cwptype;
imm : word;
ldcheck1 : std_ulogic;
ldcheck2 : std_ulogic;
ldchkra : std_ulogic;
ldchkex : std_ulogic;
su : std_ulogic;
et : std_ulogic;
wovf : std_ulogic;
wunf : std_ulogic;
ticc : std_ulogic;
jmpl : std_ulogic;
step : std_ulogic;
mulstart : std_ulogic;
divstart : std_ulogic;
END RECORD;
TYPE execute_reg_type IS RECORD
ctrl : pipeline_ctrl_type;
op1 : word;
op2 : word;
aluop : std_logic_vector ( 2 downto 0 );
alusel : std_logic_vector ( 1 downto 0 );
aluadd : std_ulogic;
alucin : std_ulogic;
ldbp1 : std_ulogic;
ldbp2 : std_ulogic;
invop2 : std_ulogic;
shcnt : std_logic_vector ( 4 downto 0 );
sari : std_ulogic;
shleft : std_ulogic;
ymsb : std_ulogic;
rd : std_logic_vector ( 4 downto 0 );
jmpl : std_ulogic;
su : std_ulogic;
et : std_ulogic;
cwp : cwptype;
icc : std_logic_vector ( 3 downto 0 );
mulstep : std_ulogic;
mul : std_ulogic;
mac : std_ulogic;
END RECORD;
TYPE memory_reg_type IS RECORD
ctrl : pipeline_ctrl_type;
result : word;
y : word;
icc : std_logic_vector ( 3 downto 0 );
nalign : std_ulogic;
dci : dc_in_type;
werr : std_ulogic;
wcwp : std_ulogic;
irqen : std_ulogic;
irqen2 : std_ulogic;
mac : std_ulogic;
divz : std_ulogic;
su : std_ulogic;
mul : std_ulogic;
END RECORD;
TYPE exception_state IS ( run , trap , dsu1 , dsu2 );
TYPE exception_reg_type IS RECORD
ctrl : pipeline_ctrl_type;
result : word;
y : word;
icc : std_logic_vector ( 3 downto 0 );
annul_all : std_ulogic;
data : dcdtype;
set : std_logic_vector ( LOG2X ( 2 ) - 1 downto 0 );
mexc : std_ulogic;
dci : dc_in_type;
laddr : std_logic_vector ( 1 downto 0 );
rstate : exception_state;
npc : std_logic_vector ( 2 downto 0 );
intack : std_ulogic;
ipend : std_ulogic;
mac : std_ulogic;
debug : std_ulogic;
nerror : std_ulogic;
END RECORD;
TYPE dsu_registers IS RECORD
tt : std_logic_vector ( 7 downto 0 );
err : std_ulogic;
tbufcnt : std_logic_vector ( 10 + LOG2 ( 2 ) - 4 - 1 downto 0 );
asi : std_logic_vector ( 7 downto 0 );
crdy : std_logic_vector ( 2 downto 1 );
END RECORD;
TYPE irestart_register IS RECORD
addr : pctype;
pwd : std_ulogic;
END RECORD;
TYPE pwd_register_type IS RECORD
pwd : std_ulogic;
error : std_ulogic;
END RECORD;
TYPE special_register_type IS RECORD
cwp : cwptype;
icc : std_logic_vector ( 3 downto 0 );
tt : std_logic_vector ( 7 downto 0 );
tba : std_logic_vector ( 19 downto 0 );
wim : std_logic_vector ( 8 - 1 downto 0 );
pil : std_logic_vector ( 3 downto 0 );
ec : std_ulogic;
ef : std_ulogic;
ps : std_ulogic;
s : std_ulogic;
et : std_ulogic;
y : word;
asr18 : word;
svt : std_ulogic;
dwt : std_ulogic;
END RECORD;
TYPE write_reg_type IS RECORD
s : special_register_type;
result : word;
wa : rfatype;
wreg : std_ulogic;
except : std_ulogic;
END RECORD;
TYPE registers IS RECORD
f : fetch_reg_type;
d : decode_reg_type;
a : regacc_reg_type;
e : execute_reg_type;
m : memory_reg_type;
x : exception_reg_type;
w : write_reg_type;
END RECORD;
TYPE exception_type IS RECORD
pri : std_ulogic;
ill : std_ulogic;
fpdis : std_ulogic;
cpdis : std_ulogic;
wovf : std_ulogic;
wunf : std_ulogic;
ticc : std_ulogic;
END RECORD;
TYPE watchpoint_register IS RECORD
addr : std_logic_vector ( 31 downto 2 );
mask : std_logic_vector ( 31 downto 2 );
exec : std_ulogic;
load : std_ulogic;
store : std_ulogic;
END RECORD;
TYPE watchpoint_registers IS ARRAY ( 0 to 3 ) OF watchpoint_register;
CONSTANT wpr_none : watchpoint_register := ( zero32 ( 31 downto 2 ) , zero32 ( 31 downto 2 ) , '0' , '0' , '0' );
FUNCTION dbgexc (
r : registers;
dbgi : l3_debug_in_type;
trap : std_ulogic;
tt : std_logic_vector ( 7 downto 0 )
) RETURN std_ulogic IS
VARIABLE dmode : std_ulogic;
BEGIN
dmode := '0';
IF ( not r.x.ctrl.annul and trap ) = '1' THEN
IF ( ( ( tt = "00" & TT_WATCH ) and ( dbgi.bwatch = '1' ) ) or ( ( dbgi.bsoft = '1' ) and ( tt = "10000001" ) ) or ( dbgi.btrapa = '1' ) or ( ( dbgi.btrape = '1' ) and not ( ( tt ( 5 downto 0 ) = TT_PRIV ) or ( tt ( 5 downto 0 ) = TT_FPDIS ) or ( tt ( 5 downto 0 ) = TT_WINOF ) or ( tt ( 5 downto 0 ) = TT_WINUF ) or ( tt ( 5 downto 4 ) = "01" ) or ( tt ( 7 ) = '1' ) ) ) or ( ( ( not r.w.s.et ) and dbgi.berror ) = '1' ) ) THEN
dmode := '1';
END IF;
END IF;
RETURN ( dmode );
END;
FUNCTION dbgerr (
r : registers;
dbgi : l3_debug_in_type;
tt : std_logic_vector ( 7 downto 0 )
) RETURN std_ulogic IS
VARIABLE err : std_ulogic;
BEGIN
err := not r.w.s.et;
IF ( ( ( dbgi.dbreak = '1' ) and ( tt = ( "00" & TT_WATCH ) ) ) or ( ( dbgi.bsoft = '1' ) and ( tt = ( "10000001" ) ) ) ) THEN
err := '0';
END IF;
RETURN ( err );
END;
PROCEDURE diagwr (
r : in registers;
dsur : in dsu_registers;
ir : in irestart_register;
dbg : in l3_debug_in_type;
wpr : in watchpoint_registers;
s : out special_register_type;
vwpr : out watchpoint_registers;
asi : out std_logic_vector ( 7 downto 0 );
pc : out pctype;
npc : out pctype;
tbufcnt : out std_logic_vector ( 10 + LOG2 ( 2 ) - 4 - 1 downto 0 );
wr : out std_ulogic;
addr : out std_logic_vector ( 9 downto 0 );
data : out word;
fpcwr : out std_ulogic
) IS
VARIABLE i : integer RANGE 0 to 3;
BEGIN
s := r.w.s;
pc := r.f.pc;
npc := ir.addr;
wr := '0';
vwpr := wpr;
asi := dsur.asi;
addr := ( OTHERS => '0' );
data := dbg.ddata;
tbufcnt := dsur.tbufcnt;
fpcwr := '0';
IF ( dbg.dsuen and dbg.denable and dbg.dwrite ) = '1' THEN
CASE dbg.daddr ( 23 downto 20 ) IS
WHEN "0001" =>
IF dbg.daddr ( 16 ) = '1' THEN
tbufcnt := dbg.ddata ( 10 + LOG2 ( 2 ) - 4 - 1 downto 0 );
END IF;
WHEN "0011" =>
IF dbg.daddr ( 12 ) = '0' THEN
wr := '1';
addr := ( OTHERS => '0' );
addr ( LOG2 ( 8 + 1 ) + 4 - 1 downto 0 ) := dbg.daddr ( LOG2 ( 8 + 1 ) + 4 + 1 downto 2 );
ELSE
fpcwr := '1';
END IF;
WHEN "0100" =>
CASE dbg.daddr ( 7 downto 6 ) IS
WHEN "00" =>
CASE dbg.daddr ( 5 downto 2 ) IS
WHEN "0000" =>
s.y := dbg.ddata;
WHEN "0001" =>
s.cwp := dbg.ddata ( LOG2 ( 8 ) - 1 downto 0 );
s.icc := dbg.ddata ( 23 downto 20 );
s.ec := dbg.ddata ( 13 );
s.pil := dbg.ddata ( 11 downto 8 );
s.s := dbg.ddata ( 7 );
s.ps := dbg.ddata ( 6 );
s.et := dbg.ddata ( 5 );
WHEN "0010" =>
s.wim := dbg.ddata ( 8 - 1 downto 0 );
WHEN "0011" =>
s.tba := dbg.ddata ( 31 downto 12 );
s.tt := dbg.ddata ( 11 downto 4 );
WHEN "0100" =>
pc := dbg.ddata ( 31 downto 2 );
WHEN "0101" =>
npc := dbg.ddata ( 31 downto 2 );
WHEN "0110" =>
fpcwr := '1';
WHEN "0111" =>
NULL;
WHEN "1001" =>
asi := dbg.ddata ( 7 downto 0 );
WHEN OTHERS =>
NULL;
END CASE;
WHEN "01" =>
CASE dbg.daddr ( 5 downto 2 ) IS
WHEN "0001" =>
s.dwt := dbg.ddata ( 14 );
s.svt := dbg.ddata ( 13 );
WHEN "0010" =>
NULL;
WHEN "1000" =>
vwpr ( 0 ).addr := dbg.ddata ( 31 downto 2 );
vwpr ( 0 ).exec := dbg.ddata ( 0 );
WHEN "1001" =>
vwpr ( 0 ).mask := dbg.ddata ( 31 downto 2 );
vwpr ( 0 ).load := dbg.ddata ( 1 );
vwpr ( 0 ).store := dbg.ddata ( 0 );
WHEN "1010" =>
vwpr ( 1 ).addr := dbg.ddata ( 31 downto 2 );
vwpr ( 1 ).exec := dbg.ddata ( 0 );
WHEN "1011" =>
vwpr ( 1 ).mask := dbg.ddata ( 31 downto 2 );
vwpr ( 1 ).load := dbg.ddata ( 1 );
vwpr ( 1 ).store := dbg.ddata ( 0 );
WHEN "1100" =>
vwpr ( 2 ).addr := dbg.ddata ( 31 downto 2 );
vwpr ( 2 ).exec := dbg.ddata ( 0 );
WHEN "1101" =>
vwpr ( 2 ).mask := dbg.ddata ( 31 downto 2 );
vwpr ( 2 ).load := dbg.ddata ( 1 );
vwpr ( 2 ).store := dbg.ddata ( 0 );
WHEN "1110" =>
vwpr ( 3 ).addr := dbg.ddata ( 31 downto 2 );
vwpr ( 3 ).exec := dbg.ddata ( 0 );
WHEN "1111" =>
vwpr ( 3 ).mask := dbg.ddata ( 31 downto 2 );
vwpr ( 3 ).load := dbg.ddata ( 1 );
vwpr ( 3 ).store := dbg.ddata ( 0 );
WHEN OTHERS =>
NULL;
END CASE;
WHEN OTHERS =>
NULL;
END CASE;
WHEN OTHERS =>
NULL;
END CASE;
END IF;
END;
FUNCTION asr17_gen (
r : in registers
) RETURN word IS
VARIABLE asr17 : word;
VARIABLE fpu2 : integer RANGE 0 to 3;
BEGIN
asr17 := zero32;
asr17 ( 31 downto 28 ) := conv_std_logic_vector ( 0 , 4 );
asr17 ( 14 ) := r.w.s.dwt;
asr17 ( 13 ) := r.w.s.svt;
fpu2 := 0;
asr17 ( 11 downto 10 ) := conv_std_logic_vector ( fpu2 , 2 );
asr17 ( 8 ) := '1';
asr17 ( 7 downto 5 ) := conv_std_logic_vector ( 2 , 3 );
asr17 ( 4 downto 0 ) := conv_std_logic_vector ( 8 - 1 , 5 );
RETURN ( asr17 );
END;
PROCEDURE diagread (
dbgi : in l3_debug_in_type;
r : in registers;
dsur : in dsu_registers;
ir : in irestart_register;
wpr : in watchpoint_registers;
rfdata : in std_logic_vector ( 31 downto 0 );
dco : in dcache_out_type;
tbufo : in tracebuf_out_type;
data : out word
) IS
VARIABLE cwp : std_logic_vector ( 4 downto 0 );
VARIABLE rd : std_logic_vector ( 4 downto 0 );
VARIABLE i : integer RANGE 0 to 3;
BEGIN
data := ( OTHERS => '0' );
cwp := ( OTHERS => '0' );
cwp ( LOG2 ( 8 ) - 1 downto 0 ) := r.w.s.cwp;
CASE dbgi.daddr ( 22 downto 20 ) IS
WHEN "001" =>
IF dbgi.daddr ( 16 ) = '1' THEN
data ( 10 + LOG2 ( 2 ) - 4 - 1 downto 0 ) := dsur.tbufcnt;
ELSE
CASE dbgi.daddr ( 3 downto 2 ) IS
WHEN "00" =>
data := tbufo.data ( 127 downto 96 );
WHEN "01" =>
data := tbufo.data ( 95 downto 64 );
WHEN "10" =>
data := tbufo.data ( 63 downto 32 );
WHEN OTHERS =>
data := tbufo.data ( 31 downto 0 );
END CASE;
END IF;
WHEN "011" =>
IF dbgi.daddr ( 12 ) = '0' THEN
data := rfdata ( 31 downto 0 );
ELSE
data := fpo.dbg.data;
END IF;
WHEN "100" =>
CASE dbgi.daddr ( 7 downto 6 ) IS
WHEN "00" =>
CASE dbgi.daddr ( 5 downto 2 ) IS
WHEN "0000" =>
data := r.w.s.y;
WHEN "0001" =>
data := conv_std_logic_vector ( 15 , 4 ) & conv_std_logic_vector ( 3 , 4 ) & r.w.s.icc & "000000" & r.w.s.ec & r.w.s.ef & r.w.s.pil & r.w.s.s & r.w.s.ps & r.w.s.et & cwp;
WHEN "0010" =>
data ( 8 - 1 downto 0 ) := r.w.s.wim;
WHEN "0011" =>
data := r.w.s.tba & r.w.s.tt & "0000";
WHEN "0100" =>
data ( 31 downto 2 ) := r.f.pc;
WHEN "0101" =>
data ( 31 downto 2 ) := ir.addr;
WHEN "0110" =>
data := fpo.dbg.data;
WHEN "0111" =>
NULL;
WHEN "1000" =>
data ( 12 downto 4 ) := dsur.err & dsur.tt;
WHEN "1001" =>
data ( 7 downto 0 ) := dsur.asi;
WHEN OTHERS =>
NULL;
END CASE;
WHEN "01" =>
IF dbgi.daddr ( 5 ) = '0' THEN
IF dbgi.daddr ( 4 downto 2 ) = "001" THEN
data := asr17_gen ( r );
END IF;
ELSE
i := conv_integer ( dbgi.daddr ( 4 downto 3 ) );
IF dbgi.daddr ( 2 ) = '0' THEN
data ( 31 downto 2 ) := wpr ( i ).addr;
data ( 0 ) := wpr ( i ).exec;
ELSE
data ( 31 downto 2 ) := wpr ( i ).mask;
data ( 1 ) := wpr ( i ).load;
data ( 0 ) := wpr ( i ).store;
END IF;
END IF;
WHEN OTHERS =>
NULL;
END CASE;
WHEN "111" =>
data := r.x.data ( conv_integer ( r.x.set ) );
WHEN OTHERS =>
NULL;
END CASE;
END;
PROCEDURE itrace (
r : in registers;
dsur : in dsu_registers;
vdsu : in dsu_registers;
res : in word;
exc : in std_ulogic;
dbgi : in l3_debug_in_type;
error : in std_ulogic;
trap : in std_ulogic;
tbufcnt : out std_logic_vector ( 10 + LOG2 ( 2 ) - 4 - 1 downto 0 );
di : out tracebuf_in_type
) IS
VARIABLE meminst : std_ulogic;
BEGIN
di.addr := ( OTHERS => '0' );
di.data := ( OTHERS => '0' );
di.enable := '0';
di.write := ( OTHERS => '0' );
tbufcnt := vdsu.tbufcnt;
meminst := r.x.ctrl.inst ( 31 ) and r.x.ctrl.inst ( 30 );
di.addr ( 10 + LOG2 ( 2 ) - 4 - 1 downto 0 ) := dsur.tbufcnt;
di.data ( 127 ) := '0';
di.data ( 126 ) := not r.x.ctrl.pv;
di.data ( 125 downto 96 ) := dbgi.timer ( 29 downto 0 );
di.data ( 95 downto 64 ) := res;
di.data ( 63 downto 34 ) := r.x.ctrl.pc ( 31 downto 2 );
di.data ( 33 ) := trap;
di.data ( 32 ) := error;
di.data ( 31 downto 0 ) := r.x.ctrl.inst;
IF ( dbgi.tenable = '0' ) or ( r.x.rstate = dsu2 ) THEN
IF ( ( dbgi.dsuen and dbgi.denable ) = '1' ) and ( dbgi.daddr ( 23 downto 20 ) & dbgi.daddr ( 16 ) = "00010" ) THEN
di.enable := '1';
di.addr ( 10 + LOG2 ( 2 ) - 4 - 1 downto 0 ) := dbgi.daddr ( 10 + LOG2 ( 2 ) - 4 - 1 + 4 downto 4 );
IF dbgi.dwrite = '1' THEN
CASE dbgi.daddr ( 3 downto 2 ) IS
WHEN "00" =>
di.write ( 3 ) := '1';
WHEN "01" =>
di.write ( 2 ) := '1';
WHEN "10" =>
di.write ( 1 ) := '1';
WHEN OTHERS =>
di.write ( 0 ) := '1';
END CASE;
di.data := dbgi.ddata & dbgi.ddata & dbgi.ddata & dbgi.ddata;
END IF;
END IF;
ELSIF ( not r.x.ctrl.annul and ( r.x.ctrl.pv or meminst ) and not r.x.debug ) = '1' THEN
di.enable := '1';
di.write := ( OTHERS => '1' );
tbufcnt := dsur.tbufcnt + 1;
END IF;
di.diag := dco.testen & "000";
IF dco.scanen = '1' THEN
di.enable := '0';
END IF;
END;
PROCEDURE dbg_cache (
holdn : in std_ulogic;
dbgi : in l3_debug_in_type;
r : in registers;
dsur : in dsu_registers;
mresult : in word;
dci : in dc_in_type;
mresult2 : out word;
dci2 : out dc_in_type
) IS
BEGIN
mresult2 := mresult;
dci2 := dci;
dci2.dsuen := '0';
IF r.x.rstate = dsu2 THEN
dci2.asi := dsur.asi;
IF ( dbgi.daddr ( 22 downto 20 ) = "111" ) and ( dbgi.dsuen = '1' ) THEN
dci2.dsuen := ( dbgi.denable or r.m.dci.dsuen ) and not dsur.crdy ( 2 );
dci2.enaddr := dbgi.denable;
dci2.size := "10";
dci2.read := '1';
dci2.write := '0';
IF ( dbgi.denable and not r.m.dci.enaddr ) = '1' THEN
mresult2 := ( OTHERS => '0' );
mresult2 ( 19 downto 2 ) := dbgi.daddr ( 19 downto 2 );
ELSE
mresult2 := dbgi.ddata;
END IF;
IF dbgi.dwrite = '1' THEN
dci2.read := '0';
dci2.write := '1';
END IF;
END IF;
END IF;
END;
PROCEDURE fpexack (
r : in registers;
fpexc : out std_ulogic
) IS
BEGIN
fpexc := '0';
END;
PROCEDURE diagrdy (
denable : in std_ulogic;
dsur : in dsu_registers;
dci : in dc_in_type;
mds : in std_ulogic;
ico : in icache_out_type;
crdy : out std_logic_vector ( 2 downto 1 )
) IS
BEGIN
crdy := dsur.crdy ( 1 ) & '0';
IF dci.dsuen = '1' THEN
CASE dsur.asi ( 4 downto 0 ) IS
WHEN ASI_ITAG | ASI_IDATA | ASI_UINST | ASI_SINST =>
crdy ( 2 ) := ico.diagrdy and not dsur.crdy ( 2 );
WHEN ASI_DTAG | ASI_MMUSNOOP_DTAG | ASI_DDATA | ASI_UDATA | ASI_SDATA =>
crdy ( 1 ) := not denable and dci.enaddr and not dsur.crdy ( 1 );
WHEN OTHERS =>
crdy ( 2 ) := dci.enaddr and denable;
END CASE;
END IF;
END;
SIGNAL r : registers;
SIGNAL rin : registers;
SIGNAL wpr : watchpoint_registers;
SIGNAL wprin : watchpoint_registers;
SIGNAL dsur : dsu_registers;
SIGNAL dsuin : dsu_registers;
SIGNAL ir : irestart_register;
SIGNAL irin : irestart_register;
SIGNAL rp : pwd_register_type;
SIGNAL rpin : pwd_register_type;
SIGNAL hackState : std_logic_vector ( 1 downto 0 );
CONSTANT EXE_AND : std_logic_vector ( 2 downto 0 ) := "000";
CONSTANT EXE_XOR : std_logic_vector ( 2 downto 0 ) := "001";
CONSTANT EXE_OR : std_logic_vector ( 2 downto 0 ) := "010";
CONSTANT EXE_XNOR : std_logic_vector ( 2 downto 0 ) := "011";
CONSTANT EXE_ANDN : std_logic_vector ( 2 downto 0 ) := "100";
CONSTANT EXE_ORN : std_logic_vector ( 2 downto 0 ) := "101";
CONSTANT EXE_DIV : std_logic_vector ( 2 downto 0 ) := "110";
CONSTANT EXE_PASS1 : std_logic_vector ( 2 downto 0 ) := "000";
CONSTANT EXE_PASS2 : std_logic_vector ( 2 downto 0 ) := "001";
CONSTANT EXE_STB : std_logic_vector ( 2 downto 0 ) := "010";
CONSTANT EXE_STH : std_logic_vector ( 2 downto 0 ) := "011";
CONSTANT EXE_ONES : std_logic_vector ( 2 downto 0 ) := "100";
CONSTANT EXE_RDY : std_logic_vector ( 2 downto 0 ) := "101";
CONSTANT EXE_SPR : std_logic_vector ( 2 downto 0 ) := "110";
CONSTANT EXE_LINK : std_logic_vector ( 2 downto 0 ) := "111";
CONSTANT EXE_SLL : std_logic_vector ( 2 downto 0 ) := "001";
CONSTANT EXE_SRL : std_logic_vector ( 2 downto 0 ) := "010";
CONSTANT EXE_SRA : std_logic_vector ( 2 downto 0 ) := "100";
CONSTANT EXE_NOP : std_logic_vector ( 2 downto 0 ) := "000";
CONSTANT EXE_RES_ADD : std_logic_vector ( 1 downto 0 ) := "00";
CONSTANT EXE_RES_SHIFT : std_logic_vector ( 1 downto 0 ) := "01";
CONSTANT EXE_RES_LOGIC : std_logic_vector ( 1 downto 0 ) := "10";
CONSTANT EXE_RES_MISC : std_logic_vector ( 1 downto 0 ) := "11";
CONSTANT SZBYTE : std_logic_vector ( 1 downto 0 ) := "00";
CONSTANT SZHALF : std_logic_vector ( 1 downto 0 ) := "01";
CONSTANT SZWORD : std_logic_vector ( 1 downto 0 ) := "10";
CONSTANT SZDBL : std_logic_vector ( 1 downto 0 ) := "11";
PROCEDURE regaddr (
cwp : std_logic_vector;
reg : std_logic_vector ( 4 downto 0 );
rao : out rfatype
) IS
VARIABLE ra : rfatype;
CONSTANT globals : std_logic_vector ( LOG2 ( 8 + 1 ) + 4 - 5 downto 0 ) := conv_std_logic_vector ( 8 , LOG2 ( 8 + 1 ) + 4 - 4 );
BEGIN
ra := ( OTHERS => '0' );
ra ( 4 downto 0 ) := reg;
IF reg ( 4 downto 3 ) = "00" THEN
ra ( LOG2 ( 8 + 1 ) + 4 - 1 downto 4 ) := CONV_STD_LOGIC_VECTOR ( 8 , LOG2 ( 8 + 1 ) + 4 - 4 );
ELSE
ra ( LOG2 ( 8 ) + 3 downto 4 ) := cwp + ra ( 4 );
END IF;
rao := ra;
END;
FUNCTION branch_address (
inst : word;
pc : pctype
) RETURN std_logic_vector IS
VARIABLE baddr : pctype;
VARIABLE caddr : pctype;
VARIABLE tmp : pctype;
BEGIN
caddr := ( OTHERS => '0' );
caddr ( 31 downto 2 ) := inst ( 29 downto 0 );
caddr ( 31 downto 2 ) := caddr ( 31 downto 2 ) + pc ( 31 downto 2 );
baddr := ( OTHERS => '0' );
baddr ( 31 downto 24 ) := ( OTHERS => inst ( 21 ) );
baddr ( 23 downto 2 ) := inst ( 21 downto 0 );
baddr ( 31 downto 2 ) := baddr ( 31 downto 2 ) + pc ( 31 downto 2 );
IF inst ( 30 ) = '1' THEN
tmp := caddr;
ELSE
tmp := baddr;
END IF;
RETURN ( tmp );
END;
FUNCTION branch_true (
icc : std_logic_vector ( 3 downto 0 );
inst : word
) RETURN std_ulogic IS
VARIABLE n : std_ulogic;
VARIABLE z : std_ulogic;
VARIABLE v : std_ulogic;
VARIABLE c : std_ulogic;
VARIABLE branch : std_ulogic;
BEGIN
n := icc ( 3 );
z := icc ( 2 );
v := icc ( 1 );
c := icc ( 0 );
CASE inst ( 27 downto 25 ) IS
WHEN "000" =>
branch := inst ( 28 ) xor '0';
WHEN "001" =>
branch := inst ( 28 ) xor z;
WHEN "010" =>
branch := inst ( 28 ) xor ( z or ( n xor v ) );
WHEN "011" =>
branch := inst ( 28 ) xor ( n xor v );
WHEN "100" =>
branch := inst ( 28 ) xor ( c or z );
WHEN "101" =>
branch := inst ( 28 ) xor c;
WHEN "110" =>
branch := inst ( 28 ) xor n;
WHEN OTHERS =>
branch := inst ( 28 ) xor v;
END CASE;
RETURN ( branch );
END;
PROCEDURE su_et_select (
r : in registers;
xc_ps : in std_ulogic;
xc_s : in std_ulogic;
xc_et : in std_ulogic;
su : out std_ulogic;
et : out std_ulogic
) IS
BEGIN
IF ( ( r.a.ctrl.rett or r.e.ctrl.rett or r.m.ctrl.rett or r.x.ctrl.rett ) = '1' ) and ( r.x.annul_all = '0' ) THEN
su := xc_ps;
et := '1';
ELSE
su := xc_s;
et := xc_et;
END IF;
END;
FUNCTION wphit (
r : registers;
wpr : watchpoint_registers;
debug : l3_debug_in_type
) RETURN std_ulogic IS
VARIABLE exc : std_ulogic;
BEGIN
exc := '0';
IF ( ( wpr ( 0 ).exec and r.a.ctrl.pv and not r.a.ctrl.annul ) = '1' ) THEN
IF ( ( ( wpr ( 0 ).addr xor r.a.ctrl.pc ( 31 downto 2 ) ) and wpr ( 0 ).mask ) = Zero32 ( 31 downto 2 ) ) THEN
exc := '1';
END IF;
END IF;
IF ( ( wpr ( 1 ).exec and r.a.ctrl.pv and not r.a.ctrl.annul ) = '1' ) THEN
IF ( ( ( wpr ( 1 ).addr xor r.a.ctrl.pc ( 31 downto 2 ) ) and wpr ( 1 ).mask ) = Zero32 ( 31 downto 2 ) ) THEN
exc := '1';
END IF;
END IF;
IF ( debug.dsuen and not r.a.ctrl.annul ) = '1' THEN
exc := exc or ( r.a.ctrl.pv and ( ( debug.dbreak and debug.bwatch ) or r.a.step ) );
END IF;
RETURN ( exc );
END;
FUNCTION shift3 (
r : registers;
aluin1 : word;
aluin2 : word
) RETURN word IS
VARIABLE shiftin : unsigned ( 63 downto 0 );
VARIABLE shiftout : unsigned ( 63 downto 0 );
VARIABLE cnt : natural RANGE 0 to 31;
BEGIN
cnt := conv_integer ( r.e.shcnt );
IF r.e.shleft = '1' THEN
shiftin ( 30 downto 0 ) := ( OTHERS => '0' );
shiftin ( 63 downto 31 ) := '0' & unsigned ( aluin1 );
ELSE
shiftin ( 63 downto 32 ) := ( OTHERS => r.e.sari );
shiftin ( 31 downto 0 ) := unsigned ( aluin1 );
END IF;
shiftout := SHIFT_RIGHT ( shiftin , cnt );
RETURN ( std_logic_vector ( shiftout ( 31 downto 0 ) ) );
END;
FUNCTION shift2 (
r : registers;
aluin1 : word;
aluin2 : word
) RETURN word IS
VARIABLE ushiftin : unsigned ( 31 downto 0 );
VARIABLE sshiftin : signed ( 32 downto 0 );
VARIABLE cnt : natural RANGE 0 to 31;
BEGIN
cnt := conv_integer ( r.e.shcnt );
ushiftin := unsigned ( aluin1 );
sshiftin := signed ( '0' & aluin1 );
IF r.e.shleft = '1' THEN
RETURN ( std_logic_vector ( SHIFT_LEFT ( ushiftin , cnt ) ) );
ELSE
IF r.e.sari = '1' THEN
sshiftin ( 32 ) := aluin1 ( 31 );
END IF;
sshiftin := SHIFT_RIGHT ( sshiftin , cnt );
RETURN ( std_logic_vector ( sshiftin ( 31 downto 0 ) ) );
END IF;
END;
FUNCTION shift (
r : registers;
aluin1 : word;
aluin2 : word;
shiftcnt : std_logic_vector ( 4 downto 0 );
sari : std_ulogic
) RETURN word IS
VARIABLE shiftin : std_logic_vector ( 63 downto 0 );
BEGIN
shiftin := zero32 & aluin1;
IF r.e.shleft = '1' THEN
shiftin ( 31 downto 0 ) := zero32;
shiftin ( 63 downto 31 ) := '0' & aluin1;
ELSE
shiftin ( 63 downto 32 ) := ( OTHERS => sari );
END IF;
IF shiftcnt ( 4 ) = '1' THEN
shiftin ( 47 downto 0 ) := shiftin ( 63 downto 16 );
END IF;
IF shiftcnt ( 3 ) = '1' THEN
shiftin ( 39 downto 0 ) := shiftin ( 47 downto 8 );
END IF;
IF shiftcnt ( 2 ) = '1' THEN
shiftin ( 35 downto 0 ) := shiftin ( 39 downto 4 );
END IF;
IF shiftcnt ( 1 ) = '1' THEN
shiftin ( 33 downto 0 ) := shiftin ( 35 downto 2 );
END IF;
IF shiftcnt ( 0 ) = '1' THEN
shiftin ( 31 downto 0 ) := shiftin ( 32 downto 1 );
END IF;
RETURN ( shiftin ( 31 downto 0 ) );
END;
PROCEDURE exception_detect (
r : registers;
wpr : watchpoint_registers;
dbgi : l3_debug_in_type;
trapin : in std_ulogic;
ttin : in std_logic_vector ( 5 downto 0 );
trap : out std_ulogic;
tt : out std_logic_vector ( 5 downto 0 )
) IS
VARIABLE illegal_inst : std_ulogic;
VARIABLE privileged_inst : std_ulogic;
VARIABLE cp_disabled : std_ulogic;
VARIABLE fp_disabled : std_ulogic;
VARIABLE fpop : std_ulogic;
VARIABLE op : std_logic_vector ( 1 downto 0 );
VARIABLE op2 : std_logic_vector ( 2 downto 0 );
VARIABLE op3 : std_logic_vector ( 5 downto 0 );
VARIABLE rd : std_logic_vector ( 4 downto 0 );
VARIABLE inst : word;
VARIABLE wph : std_ulogic;
BEGIN
inst := r.a.ctrl.inst;
trap := trapin;
tt := ttin;
IF r.a.ctrl.annul = '0' THEN
op := inst ( 31 downto 30 );
op2 := inst ( 24 downto 22 );
op3 := inst ( 24 downto 19 );
rd := inst ( 29 downto 25 );
illegal_inst := '0';
privileged_inst := '0';
cp_disabled := '0';
fp_disabled := '0';
fpop := '0';
CASE op IS
WHEN CALL =>
NULL;
WHEN FMT2 =>
CASE op2 IS
WHEN SETHI | BICC =>
NULL;
WHEN FBFCC =>
fp_disabled := '1';
WHEN CBCCC =>
cp_disabled := '1';
WHEN OTHERS =>
illegal_inst := '1';
END CASE;
WHEN FMT3 =>
CASE op3 IS
WHEN IAND | ANDCC | ANDN | ANDNCC | IOR | ORCC | ORN | ORNCC | IXOR | XORCC | IXNOR | XNORCC | ISLL | ISRL | ISRA | MULSCC | IADD | ADDX | ADDCC | ADDXCC | ISUB | SUBX | SUBCC | SUBXCC | FLUSH | JMPL | TICC | SAVE | RESTORE | RDY =>
NULL;
WHEN TADDCC | TADDCCTV | TSUBCC | TSUBCCTV =>
NULL;
WHEN UMAC | SMAC =>
illegal_inst := '1';
WHEN UMUL | SMUL | UMULCC | SMULCC =>
NULL;
WHEN UDIV | SDIV | UDIVCC | SDIVCC =>
NULL;
WHEN RETT =>
illegal_inst := r.a.et;
privileged_inst := not r.a.su;
WHEN RDPSR | RDTBR | RDWIM =>
privileged_inst := not r.a.su;
WHEN WRY =>
NULL;
WHEN WRPSR =>
privileged_inst := not r.a.su;
WHEN WRWIM | WRTBR =>
privileged_inst := not r.a.su;
WHEN FPOP1 | FPOP2 =>
fp_disabled := '1';
fpop := '0';
WHEN CPOP1 | CPOP2 =>
cp_disabled := '1';
WHEN OTHERS =>
illegal_inst := '1';
END CASE;
WHEN OTHERS =>
CASE op3 IS
WHEN LDD | ISTD =>
illegal_inst := rd ( 0 );
WHEN LD | LDUB | LDSTUB | LDUH | LDSB | LDSH | ST | STB | STH | SWAP =>
NULL;
WHEN LDDA | STDA =>
illegal_inst := inst ( 13 ) or rd ( 0 );
privileged_inst := not r.a.su;
WHEN LDA | LDUBA | LDSTUBA | LDUHA | LDSBA | LDSHA | STA | STBA | STHA | SWAPA =>
illegal_inst := inst ( 13 );
privileged_inst := not r.a.su;
WHEN LDDF | STDF | LDF | LDFSR | STF | STFSR =>
fp_disabled := '1';
WHEN STDFQ =>
privileged_inst := not r.a.su;
fp_disabled := '1';
WHEN STDCQ =>
privileged_inst := not r.a.su;
cp_disabled := '1';
WHEN LDC | LDCSR | LDDC | STC | STCSR | STDC =>
cp_disabled := '1';
WHEN OTHERS =>
illegal_inst := '1';
END CASE;
END CASE;
wph := wphit ( r , wpr , dbgi );
trap := '1';
IF r.a.ctrl.trap = '1' THEN
tt := TT_IAEX;
ELSIF privileged_inst = '1' THEN
tt := TT_PRIV;
ELSIF illegal_inst = '1' THEN
tt := TT_IINST;
ELSIF fp_disabled = '1' THEN
tt := TT_FPDIS;
ELSIF cp_disabled = '1' THEN
tt := TT_CPDIS;
ELSIF wph = '1' THEN
tt := TT_WATCH;
ELSIF r.a.wovf = '1' THEN
tt := TT_WINOF;
ELSIF r.a.wunf = '1' THEN
tt := TT_WINUF;
ELSIF r.a.ticc = '1' THEN
tt := TT_TICC;
ELSE
trap := '0';
tt := ( OTHERS => '0' );
END IF;
END IF;
END;
PROCEDURE wicc_y_gen (
inst : word;
wicc : out std_ulogic;
wy : out std_ulogic
) IS
BEGIN
wicc := '0';
wy := '0';
IF inst ( 31 downto 30 ) = FMT3 THEN
CASE inst ( 24 downto 19 ) IS
WHEN SUBCC | TSUBCC | TSUBCCTV | ADDCC | ANDCC | ORCC | XORCC | ANDNCC | ORNCC | XNORCC | TADDCC | TADDCCTV | ADDXCC | SUBXCC | WRPSR =>
wicc := '1';
WHEN WRY =>
IF r.d.inst ( conv_integer ( r.d.set ) ) ( 29 downto 25 ) = "00000" THEN
wy := '1';
END IF;
WHEN MULSCC =>
wicc := '1';
wy := '1';
WHEN UMAC | SMAC =>
NULL;
WHEN UMULCC | SMULCC =>
IF ( ( ( mulo.nready = '1' ) and ( r.d.cnt /= "00" ) ) ) THEN
wicc := '1';
wy := '1';
END IF;
WHEN UMUL | SMUL =>
IF ( ( ( mulo.nready = '1' ) and ( r.d.cnt /= "00" ) ) ) THEN
wy := '1';
END IF;
WHEN UDIVCC | SDIVCC =>
IF ( divo.nready = '1' ) and ( r.d.cnt /= "00" ) THEN
wicc := '1';
END IF;
WHEN OTHERS =>
NULL;
END CASE;
END IF;
END;
PROCEDURE cwp_gen (
r : registers;
v : registers;
annul : std_ulogic;
wcwp : std_ulogic;
ncwp : cwptype;
cwp : out cwptype
) IS
BEGIN
IF ( r.x.rstate = trap ) or ( r.x.rstate = dsu2 ) or ( rstn = '0' ) THEN
cwp := v.w.s.cwp;
ELSIF ( wcwp = '1' ) and ( annul = '0' ) THEN
cwp := ncwp;
ELSIF r.m.wcwp = '1' THEN
cwp := r.m.result ( LOG2 ( 8 ) - 1 downto 0 );
ELSE
cwp := r.d.cwp;
END IF;
END;
PROCEDURE cwp_ex (
r : in registers;
wcwp : out std_ulogic
) IS
BEGIN
IF ( r.e.ctrl.inst ( 31 downto 30 ) = FMT3 ) and ( r.e.ctrl.inst ( 24 downto 19 ) = WRPSR ) THEN
wcwp := not r.e.ctrl.annul;
ELSE
wcwp := '0';
END IF;
END;
PROCEDURE cwp_ctrl (
r : in registers;
xc_wim : in std_logic_vector ( 8 - 1 downto 0 );
inst : word;
de_cwp : out cwptype;
wovf_exc : out std_ulogic;
wunf_exc : out std_ulogic;
wcwp : out std_ulogic
) IS
VARIABLE op : std_logic_vector ( 1 downto 0 );
VARIABLE op3 : std_logic_vector ( 5 downto 0 );
VARIABLE wim : word;
VARIABLE ncwp : cwptype;
BEGIN
op := inst ( 31 downto 30 );
op3 := inst ( 24 downto 19 );
wovf_exc := '0';
wunf_exc := '0';
wim := ( OTHERS => '0' );
wim ( 8 - 1 downto 0 ) := xc_wim;
ncwp := r.d.cwp;
wcwp := '0';
IF ( op = FMT3 ) and ( ( op3 = RETT ) or ( op3 = RESTORE ) or ( op3 = SAVE ) ) THEN
wcwp := '1';
IF ( op3 = SAVE ) THEN
ncwp := r.d.cwp - 1;
ELSE
ncwp := r.d.cwp + 1;
END IF;
IF wim ( conv_integer ( ncwp ) ) = '1' THEN
IF op3 = SAVE THEN
wovf_exc := '1';
ELSE
wunf_exc := '1';
END IF;
END IF;
END IF;
de_cwp := ncwp;
END;
PROCEDURE rs1_gen (
r : registers;
inst : word;
rs1 : out std_logic_vector ( 4 downto 0 );
rs1mod : out std_ulogic
) IS
VARIABLE op : std_logic_vector ( 1 downto 0 );
VARIABLE op3 : std_logic_vector ( 5 downto 0 );
BEGIN
op := inst ( 31 downto 30 );
op3 := inst ( 24 downto 19 );
rs1 := inst ( 18 downto 14 );
rs1mod := '0';
IF ( op = LDST ) THEN
IF ( ( r.d.cnt = "01" ) and ( ( op3 ( 2 ) and not op3 ( 3 ) ) = '1' ) ) or ( r.d.cnt = "10" ) THEN
rs1mod := '1';
rs1 := inst ( 29 downto 25 );
END IF;
IF ( ( r.d.cnt = "10" ) and ( op3 ( 3 downto 0 ) = "0111" ) ) THEN
rs1 ( 0 ) := '1';
END IF;
END IF;
END;
PROCEDURE lock_gen (
r : registers;
rs2 : std_logic_vector ( 4 downto 0 );
rd : std_logic_vector ( 4 downto 0 );
rfa1 : rfatype;
rfa2 : rfatype;
rfrd : rfatype;
inst : word;
fpc_lock : std_ulogic;
mulinsn : std_ulogic;
divinsn : std_ulogic;
lldcheck1 : out std_ulogic;
lldcheck2 : out std_ulogic;
lldlock : out std_ulogic;
lldchkra : out std_ulogic;
lldchkex : out std_ulogic
) IS
VARIABLE op : std_logic_vector ( 1 downto 0 );
VARIABLE op2 : std_logic_vector ( 2 downto 0 );
VARIABLE op3 : std_logic_vector ( 5 downto 0 );
VARIABLE cond : std_logic_vector ( 3 downto 0 );
VARIABLE rs1 : std_logic_vector ( 4 downto 0 );
VARIABLE i : std_ulogic;
VARIABLE ldcheck1 : std_ulogic;
VARIABLE ldcheck2 : std_ulogic;
VARIABLE ldchkra : std_ulogic;
VARIABLE ldchkex : std_ulogic;
VARIABLE ldcheck3 : std_ulogic;
VARIABLE ldlock : std_ulogic;
VARIABLE icc_check : std_ulogic;
VARIABLE bicc_hold : std_ulogic;
VARIABLE chkmul : std_ulogic;
VARIABLE y_check : std_ulogic;
VARIABLE lddlock : boolean;
BEGIN
op := inst ( 31 downto 30 );
op3 := inst ( 24 downto 19 );
op2 := inst ( 24 downto 22 );
cond := inst ( 28 downto 25 );
rs1 := inst ( 18 downto 14 );
lddlock := false;
i := inst ( 13 );
ldcheck1 := '0';
ldcheck2 := '0';
ldcheck3 := '0';
ldlock := '0';
ldchkra := '1';
ldchkex := '1';
icc_check := '0';
bicc_hold := '0';
y_check := '0';
IF ( r.d.annul = '0' ) THEN
CASE op IS
WHEN FMT2 =>
IF ( op2 = BICC ) and ( cond ( 2 downto 0 ) /= "000" ) THEN
icc_check := '1';
END IF;
WHEN FMT3 =>
ldcheck1 := '1';
ldcheck2 := not i;
CASE op3 IS
WHEN TICC =>
IF ( cond ( 2 downto 0 ) /= "000" ) THEN
icc_check := '1';
END IF;
WHEN RDY =>
ldcheck1 := '0';
ldcheck2 := '0';
WHEN RDWIM | RDTBR =>
ldcheck1 := '0';
ldcheck2 := '0';
WHEN RDPSR =>
ldcheck1 := '0';
ldcheck2 := '0';
icc_check := '1';
icc_check := '1';
WHEN SDIV | SDIVCC | UDIV | UDIVCC =>
y_check := '1';
WHEN FPOP1 | FPOP2 =>
ldcheck1 := '0';
ldcheck2 := '0';
WHEN OTHERS =>
NULL;
END CASE;
WHEN LDST =>
ldcheck1 := '1';
ldchkra := '0';
CASE r.d.cnt IS
WHEN "00" =>
ldcheck2 := not i;
ldchkra := '1';
WHEN "01" =>
ldcheck2 := not i;
WHEN OTHERS =>
ldchkex := '0';
END CASE;
IF ( op3 ( 2 downto 0 ) = "011" ) THEN
lddlock := true;
END IF;
WHEN OTHERS =>
NULL;
END CASE;
END IF;
chkmul := mulinsn;
bicc_hold := bicc_hold or ( icc_check and r.m.ctrl.wicc and ( r.m.ctrl.cnt ( 0 ) or r.m.mul ) );
bicc_hold := bicc_hold or ( y_check and ( r.a.ctrl.wy or r.e.ctrl.wy ) );
chkmul := chkmul or divinsn;
bicc_hold := bicc_hold or ( icc_check and ( r.a.ctrl.wicc or r.e.ctrl.wicc ) );
IF ( ( ( r.a.ctrl.ld or chkmul ) and r.a.ctrl.wreg and ldchkra ) = '1' ) and ( ( ( ldcheck1 = '1' ) and ( r.a.ctrl.rd = rfa1 ) ) or ( ( ldcheck2 = '1' ) and ( r.a.ctrl.rd = rfa2 ) ) or ( ( ldcheck3 = '1' ) and ( r.a.ctrl.rd = rfrd ) ) ) THEN
ldlock := '1';
END IF;
IF ( ( ( r.e.ctrl.ld or r.e.mac ) and r.e.ctrl.wreg and ldchkex ) = '1' ) and ( ( ( ldcheck1 = '1' ) and ( r.e.ctrl.rd = rfa1 ) ) or ( ( ldcheck2 = '1' ) and ( r.e.ctrl.rd = rfa2 ) ) ) THEN
ldlock := '1';
END IF;
ldlock := ldlock or bicc_hold or fpc_lock;
lldcheck1 := ldcheck1;
lldcheck2 := ldcheck2;
lldlock := ldlock;
lldchkra := ldchkra;
lldchkex := ldchkex;
END;
PROCEDURE fpbranch (
inst : in word;
fcc : in std_logic_vector ( 1 downto 0 );
branch : out std_ulogic
) IS
VARIABLE cond : std_logic_vector ( 3 downto 0 );
VARIABLE fbres : std_ulogic;
BEGIN
cond := inst ( 28 downto 25 );
CASE cond ( 2 downto 0 ) IS
WHEN "000" =>
fbres := '0';
WHEN "001" =>
fbres := fcc ( 1 ) or fcc ( 0 );
WHEN "010" =>
fbres := fcc ( 1 ) xor fcc ( 0 );
WHEN "011" =>
fbres := fcc ( 0 );
WHEN "100" =>
fbres := ( not fcc ( 1 ) ) and fcc ( 0 );
WHEN "101" =>
fbres := fcc ( 1 );
WHEN "110" =>
fbres := fcc ( 1 ) and not fcc ( 0 );
WHEN OTHERS =>
fbres := fcc ( 1 ) and fcc ( 0 );
END CASE;
branch := cond ( 3 ) xor fbres;
END;
PROCEDURE ic_ctrl (
r : registers;
inst : word;
annul_all : in std_ulogic;
ldlock : in std_ulogic;
branch_true : in std_ulogic;
fbranch_true : in std_ulogic;
cbranch_true : in std_ulogic;
fccv : in std_ulogic;
cccv : in std_ulogic;
cnt : out std_logic_vector ( 1 downto 0 );
de_pc : out pctype;
de_branch : out std_ulogic;
ctrl_annul : out std_ulogic;
de_annul : out std_ulogic;
jmpl_inst : out std_ulogic;
inull : out std_ulogic;
de_pv : out std_ulogic;
ctrl_pv : out std_ulogic;
de_hold_pc : out std_ulogic;
ticc_exception : out std_ulogic;
rett_inst : out std_ulogic;
mulstart : out std_ulogic;
divstart : out std_ulogic
) IS
VARIABLE op : std_logic_vector ( 1 downto 0 );
VARIABLE op2 : std_logic_vector ( 2 downto 0 );
VARIABLE op3 : std_logic_vector ( 5 downto 0 );
VARIABLE cond : std_logic_vector ( 3 downto 0 );
VARIABLE hold_pc : std_ulogic;
VARIABLE annul_current : std_ulogic;
VARIABLE annul_next : std_ulogic;
VARIABLE branch : std_ulogic;
VARIABLE annul : std_ulogic;
VARIABLE pv : std_ulogic;
VARIABLE de_jmpl : std_ulogic;
BEGIN
branch := '0';
annul_next := '0';
annul_current := '0';
pv := '1';
hold_pc := '0';
ticc_exception := '0';
rett_inst := '0';
op := inst ( 31 downto 30 );
op3 := inst ( 24 downto 19 );
op2 := inst ( 24 downto 22 );
cond := inst ( 28 downto 25 );
annul := inst ( 29 );
de_jmpl := '0';
cnt := "00";
mulstart := '0';
divstart := '0';
IF r.d.annul = '0' THEN
CASE inst ( 31 downto 30 ) IS
WHEN CALL =>
branch := '1';
IF r.d.inull = '1' THEN
hold_pc := '1';
annul_current := '1';
END IF;
WHEN FMT2 =>
IF ( op2 = BICC ) THEN
branch := branch_true;
IF hold_pc = '0' THEN
IF ( branch = '1' ) THEN
IF ( cond = BA ) and ( annul = '1' ) THEN
annul_next := '1';
END IF;
ELSE
annul_next := annul;
END IF;
IF r.d.inull = '1' THEN
hold_pc := '1';
annul_current := '1';
annul_next := '0';
END IF;
END IF;
END IF;
WHEN FMT3 =>
CASE op3 IS
WHEN UMUL | SMUL | UMULCC | SMULCC =>
CASE r.d.cnt IS
WHEN "00" =>
cnt := "01";
hold_pc := '1';
pv := '0';
mulstart := '1';
WHEN "01" =>
IF mulo.nready = '1' THEN
cnt := "00";
ELSE
cnt := "01";
pv := '0';
hold_pc := '1';
END IF;
WHEN OTHERS =>
NULL;
END CASE;
WHEN UDIV | SDIV | UDIVCC | SDIVCC =>
CASE r.d.cnt IS
WHEN "00" =>
cnt := "01";
hold_pc := '1';
pv := '0';
divstart := '1';
WHEN "01" =>
IF divo.nready = '1' THEN
cnt := "00";
ELSE
cnt := "01";
pv := '0';
hold_pc := '1';
END IF;
WHEN OTHERS =>
NULL;
END CASE;
WHEN TICC =>
IF branch_true = '1' THEN
ticc_exception := '1';
END IF;
WHEN RETT =>
rett_inst := '1';
WHEN JMPL =>
de_jmpl := '1';
WHEN WRY =>
IF FALSE THEN
IF inst ( 29 downto 25 ) = "10011" THEN
CASE r.d.cnt IS
WHEN "00" =>
pv := '0';
cnt := "00";
hold_pc := '1';
IF r.x.ipend = '1' THEN
cnt := "01";
END IF;
WHEN "01" =>
cnt := "00";
WHEN OTHERS =>
NULL;
END CASE;
END IF;
END IF;
WHEN OTHERS =>
NULL;
END CASE;
WHEN OTHERS =>
CASE r.d.cnt IS
WHEN "00" =>
IF ( op3 ( 2 ) = '1' ) or ( op3 ( 1 downto 0 ) = "11" ) THEN
cnt := "01";
hold_pc := '1';
pv := '0';
END IF;
WHEN "01" =>
IF ( op3 ( 2 downto 0 ) = "111" ) or ( op3 ( 3 downto 0 ) = "1101" ) or ( ( ( 0 = 1 ) or ( 0 /= 0 ) ) and ( ( op3 ( 5 ) & op3 ( 2 downto 0 ) ) = "1110" ) ) THEN
cnt := "10";
pv := '0';
hold_pc := '1';
ELSE
cnt := "00";
END IF;
WHEN "10" =>
cnt := "00";
WHEN OTHERS =>
NULL;
END CASE;
END CASE;
END IF;
IF ldlock = '1' THEN
cnt := r.d.cnt;
annul_next := '0';
pv := '1';
END IF;
hold_pc := ( hold_pc or ldlock ) and not annul_all;
IF hold_pc = '1' THEN
de_pc := r.d.pc;
ELSE
de_pc := r.f.pc;
END IF;
annul_current := ( annul_current or ldlock or annul_all );
ctrl_annul := r.d.annul or annul_all or annul_current;
pv := pv and not ( ( r.d.inull and not hold_pc ) or annul_all );
jmpl_inst := de_jmpl and not annul_current;
annul_next := ( r.d.inull and not hold_pc ) or annul_next or annul_all;
IF ( annul_next = '1' ) or ( rstn = '0' ) THEN
cnt := ( OTHERS => '0' );
END IF;
de_hold_pc := hold_pc;
de_branch := branch;
de_annul := annul_next;
de_pv := pv;
ctrl_pv := r.d.pv and not ( ( r.d.annul and not r.d.pv ) or annul_all or annul_current );
inull := ( not rstn ) or r.d.inull or hold_pc or annul_all;
END;
PROCEDURE rd_gen (
r : registers;
inst : word;
wreg : out std_ulogic;
ld : out std_ulogic;
rdo : out std_logic_vector ( 4 downto 0 )
) IS
VARIABLE write_reg : std_ulogic;
VARIABLE op : std_logic_vector ( 1 downto 0 );
VARIABLE op2 : std_logic_vector ( 2 downto 0 );
VARIABLE op3 : std_logic_vector ( 5 downto 0 );
VARIABLE rd : std_logic_vector ( 4 downto 0 );
BEGIN
op := inst ( 31 downto 30 );
op2 := inst ( 24 downto 22 );
op3 := inst ( 24 downto 19 );
write_reg := '0';
rd := inst ( 29 downto 25 );
ld := '0';
CASE op IS
WHEN CALL =>
write_reg := '1';
rd := "01111";
WHEN FMT2 =>
IF ( op2 = SETHI ) THEN
write_reg := '1';
END IF;
WHEN FMT3 =>
CASE op3 IS
WHEN UMUL | SMUL | UMULCC | SMULCC =>
IF ( ( ( mulo.nready = '1' ) and ( r.d.cnt /= "00" ) ) ) THEN
write_reg := '1';
END IF;
WHEN UDIV | SDIV | UDIVCC | SDIVCC =>
IF ( divo.nready = '1' ) and ( r.d.cnt /= "00" ) THEN
write_reg := '1';
END IF;
WHEN RETT | WRPSR | WRY | WRWIM | WRTBR | TICC | FLUSH =>
NULL;
WHEN FPOP1 | FPOP2 =>
NULL;
WHEN CPOP1 | CPOP2 =>
NULL;
WHEN OTHERS =>
write_reg := '1';
END CASE;
WHEN OTHERS =>
ld := not op3 ( 2 );
IF ( op3 ( 2 ) = '0' ) and not ( ( ( 0 = 1 ) or ( 0 /= 0 ) ) and ( op3 ( 5 ) = '1' ) ) THEN
write_reg := '1';
END IF;
CASE op3 IS
WHEN SWAP | SWAPA | LDSTUB | LDSTUBA =>
IF r.d.cnt = "00" THEN
write_reg := '1';
ld := '1';
END IF;
WHEN OTHERS =>
NULL;
END CASE;
IF r.d.cnt = "01" THEN
CASE op3 IS
WHEN LDD | LDDA | LDDC | LDDF =>
rd ( 0 ) := '1';
WHEN OTHERS =>
NULL;
END CASE;
END IF;
END CASE;
IF ( rd = "00000" ) THEN
write_reg := '0';
END IF;
wreg := write_reg;
rdo := rd;
END;
FUNCTION imm_data (
r : registers;
insn : word
) RETURN word IS
VARIABLE immediate_data : word;
VARIABLE inst : word;
BEGIN
immediate_data := ( OTHERS => '0' );
inst := insn;
CASE inst ( 31 downto 30 ) IS
WHEN FMT2 =>
immediate_data := inst ( 21 downto 0 ) & "0000000000";
WHEN OTHERS =>
immediate_data ( 31 downto 13 ) := ( OTHERS => inst ( 12 ) );
immediate_data ( 12 downto 0 ) := inst ( 12 downto 0 );
END CASE;
RETURN ( immediate_data );
END;
FUNCTION get_spr (
r : registers
) RETURN word IS
VARIABLE spr : word;
BEGIN
spr := ( OTHERS => '0' );
CASE r.e.ctrl.inst ( 24 downto 19 ) IS
WHEN RDPSR =>
spr ( 31 downto 5 ) := conv_std_logic_vector ( 15 , 4 ) & conv_std_logic_vector ( 3 , 4 ) & r.m.icc & "000000" & r.w.s.ec & r.w.s.ef & r.w.s.pil & r.e.su & r.w.s.ps & r.e.et;
spr ( LOG2 ( 8 ) - 1 downto 0 ) := r.e.cwp;
WHEN RDTBR =>
spr ( 31 downto 4 ) := r.w.s.tba & r.w.s.tt;
WHEN RDWIM =>
spr ( 8 - 1 downto 0 ) := r.w.s.wim;
WHEN OTHERS =>
NULL;
END CASE;
RETURN ( spr );
END;
FUNCTION imm_select (
inst : word
) RETURN boolean IS
VARIABLE imm : boolean;
BEGIN
imm := false;
CASE inst ( 31 downto 30 ) IS
WHEN FMT2 =>
CASE inst ( 24 downto 22 ) IS
WHEN SETHI =>
imm := true;
WHEN OTHERS =>
NULL;
END CASE;
WHEN FMT3 =>
CASE inst ( 24 downto 19 ) IS
WHEN RDWIM | RDPSR | RDTBR =>
imm := true;
WHEN OTHERS =>
IF ( inst ( 13 ) = '1' ) THEN
imm := true;
END IF;
END CASE;
WHEN LDST =>
IF ( inst ( 13 ) = '1' ) THEN
imm := true;
END IF;
WHEN OTHERS =>
NULL;
END CASE;
RETURN ( imm );
END;
PROCEDURE alu_op (
r : in registers;
iop1 : in word;
iop2 : in word;
me_icc : std_logic_vector ( 3 downto 0 );
my : std_ulogic;
ldbp : std_ulogic;
aop1 : out word;
aop2 : out word;
aluop : out std_logic_vector ( 2 downto 0 );
alusel : out std_logic_vector ( 1 downto 0 );
aluadd : out std_ulogic;
shcnt : out std_logic_vector ( 4 downto 0 );
sari : out std_ulogic;
shleft : out std_ulogic;
ymsb : out std_ulogic;
mulins : out std_ulogic;
divins : out std_ulogic;
mulstep : out std_ulogic;
macins : out std_ulogic;
ldbp2 : out std_ulogic;
invop2 : out std_ulogic
) IS
VARIABLE op : std_logic_vector ( 1 downto 0 );
VARIABLE op2 : std_logic_vector ( 2 downto 0 );
VARIABLE op3 : std_logic_vector ( 5 downto 0 );
VARIABLE rd : std_logic_vector ( 4 downto 0 );
VARIABLE icc : std_logic_vector ( 3 downto 0 );
VARIABLE y0 : std_ulogic;
BEGIN
op := r.a.ctrl.inst ( 31 downto 30 );
op2 := r.a.ctrl.inst ( 24 downto 22 );
op3 := r.a.ctrl.inst ( 24 downto 19 );
aop1 := iop1;
aop2 := iop2;
ldbp2 := ldbp;
aluop := "000";
alusel := "11";
aluadd := '1';
shcnt := iop2 ( 4 downto 0 );
sari := '0';
shleft := '0';
invop2 := '0';
ymsb := iop1 ( 0 );
mulins := '0';
divins := '0';
mulstep := '0';
macins := '0';
IF r.e.ctrl.wy = '1' THEN
y0 := my;
ELSIF r.m.ctrl.wy = '1' THEN
y0 := r.m.y ( 0 );
ELSIF r.x.ctrl.wy = '1' THEN
y0 := r.x.y ( 0 );
ELSE
y0 := r.w.s.y ( 0 );
END IF;
IF r.e.ctrl.wicc = '1' THEN
icc := me_icc;
ELSIF r.m.ctrl.wicc = '1' THEN
icc := r.m.icc;
ELSIF r.x.ctrl.wicc = '1' THEN
icc := r.x.icc;
ELSE
icc := r.w.s.icc;
END IF;
CASE op IS
WHEN CALL =>
aluop := "111";
WHEN FMT2 =>
CASE op2 IS
WHEN SETHI =>
aluop := "001";
WHEN OTHERS =>
NULL;
END CASE;
WHEN FMT3 =>
CASE op3 IS
WHEN IADD | ADDX | ADDCC | ADDXCC | TADDCC | TADDCCTV | SAVE | RESTORE | TICC | JMPL | RETT =>
alusel := "00";
WHEN ISUB | SUBX | SUBCC | SUBXCC | TSUBCC | TSUBCCTV =>
alusel := "00";
aluadd := '0';
aop2 := not iop2;
invop2 := '1';
WHEN MULSCC =>
alusel := "00";
aop1 := ( icc ( 3 ) xor icc ( 1 ) ) & iop1 ( 31 downto 1 );
IF y0 = '0' THEN
aop2 := ( OTHERS => '0' );
ldbp2 := '0';
END IF;
mulstep := '1';
WHEN UMUL | UMULCC | SMUL | SMULCC =>
mulins := '1';
WHEN UMAC | SMAC =>
NULL;
WHEN UDIV | UDIVCC | SDIV | SDIVCC =>
aluop := "110";
alusel := "10";
divins := '1';
WHEN IAND | ANDCC =>
aluop := "000";
alusel := "10";
WHEN ANDN | ANDNCC =>
aluop := "100";
alusel := "10";
WHEN IOR | ORCC =>
aluop := "010";
alusel := "10";
WHEN ORN | ORNCC =>
aluop := "101";
alusel := "10";
WHEN IXNOR | XNORCC =>
aluop := "011";
alusel := "10";
WHEN XORCC | IXOR | WRPSR | WRWIM | WRTBR | WRY =>
aluop := "001";
alusel := "10";
WHEN RDPSR | RDTBR | RDWIM =>
aluop := "110";
WHEN RDY =>
aluop := "101";
WHEN ISLL =>
aluop := "001";
alusel := "01";
shleft := '1';
shcnt := not iop2 ( 4 downto 0 );
invop2 := '1';
WHEN ISRL =>
aluop := "010";
alusel := "01";
WHEN ISRA =>
aluop := "100";
alusel := "01";
sari := iop1 ( 31 );
WHEN FPOP1 | FPOP2 =>
NULL;
WHEN OTHERS =>
NULL;
END CASE;
WHEN OTHERS =>
CASE r.a.ctrl.cnt IS
WHEN "00" =>
alusel := "00";
WHEN "01" =>
CASE op3 IS
WHEN LDD | LDDA | LDDC =>
alusel := "00";
WHEN LDDF =>
alusel := "00";
WHEN SWAP | SWAPA | LDSTUB | LDSTUBA =>
alusel := "00";
WHEN STF | STDF =>
NULL;
WHEN OTHERS =>
aluop := "000";
IF op3 ( 2 ) = '1' THEN
IF op3 ( 1 downto 0 ) = "01" THEN
aluop := "010";
ELSIF op3 ( 1 downto 0 ) = "10" THEN
aluop := "011";
END IF;
END IF;
END CASE;
WHEN "10" =>
aluop := "000";
IF op3 ( 2 ) = '1' THEN
IF ( op3 ( 3 ) and not op3 ( 1 ) ) = '1' THEN
aluop := "100";
END IF;
END IF;
WHEN OTHERS =>
NULL;
END CASE;
END CASE;
END;
FUNCTION ra_inull_gen (
r : registers;
v : registers
) RETURN std_ulogic IS
VARIABLE de_inull : std_ulogic;
BEGIN
de_inull := '0';
IF ( ( v.e.jmpl or v.e.ctrl.rett ) and not v.e.ctrl.annul and not ( r.e.jmpl and not r.e.ctrl.annul ) ) = '1' THEN
de_inull := '1';
END IF;
IF ( ( v.a.jmpl or v.a.ctrl.rett ) and not v.a.ctrl.annul and not ( r.a.jmpl and not r.a.ctrl.annul ) ) = '1' THEN
de_inull := '1';
END IF;
RETURN ( de_inull );
END;
PROCEDURE op_mux (
r : in registers;
rfd : in word;
ed : in word;
md : in word;
xd : in word;
im : in word;
rsel : in std_logic_vector ( 2 downto 0 );
ldbp : out std_ulogic;
d : out word
) IS
BEGIN
ldbp := '0';
CASE rsel IS
WHEN "000" =>
d := rfd;
WHEN "001" =>
d := ed;
WHEN "010" =>
d := md;
ldbp := r.m.ctrl.ld;
WHEN "011" =>
d := xd;
WHEN "100" =>
d := im;
WHEN "101" =>
d := ( OTHERS => '0' );
WHEN "110" =>
d := r.w.result;
WHEN OTHERS =>
d := ( OTHERS => '-' );
END CASE;
END;
PROCEDURE op_find (
r : in registers;
ldchkra : std_ulogic;
ldchkex : std_ulogic;
rs1 : std_logic_vector ( 4 downto 0 );
ra : rfatype;
im : boolean;
rfe : out std_ulogic;
osel : out std_logic_vector ( 2 downto 0 );
ldcheck : std_ulogic
) IS
BEGIN
rfe := '0';
IF im THEN
osel := "100";
ELSIF rs1 = "00000" THEN
osel := "101";
ELSIF ( ( r.a.ctrl.wreg and ldchkra ) = '1' ) and ( ra = r.a.ctrl.rd ) THEN
osel := "001";
ELSIF ( ( r.e.ctrl.wreg and ldchkex ) = '1' ) and ( ra = r.e.ctrl.rd ) THEN
osel := "010";
ELSIF r.m.ctrl.wreg = '1' and ( ra = r.m.ctrl.rd ) THEN
osel := "011";
ELSE
osel := "000";
rfe := ldcheck;
END IF;
END;
PROCEDURE cin_gen (
r : registers;
me_cin : in std_ulogic;
cin : out std_ulogic
) IS
VARIABLE op : std_logic_vector ( 1 downto 0 );
VARIABLE op3 : std_logic_vector ( 5 downto 0 );
VARIABLE ncin : std_ulogic;
BEGIN
op := r.a.ctrl.inst ( 31 downto 30 );
op3 := r.a.ctrl.inst ( 24 downto 19 );
IF r.e.ctrl.wicc = '1' THEN
ncin := me_cin;
ELSE
ncin := r.m.icc ( 0 );
END IF;
cin := '0';
CASE op IS
WHEN FMT3 =>
CASE op3 IS
WHEN ISUB | SUBCC | TSUBCC | TSUBCCTV =>
cin := '1';
WHEN ADDX | ADDXCC =>
cin := ncin;
WHEN SUBX | SUBXCC =>
cin := not ncin;
WHEN OTHERS =>
NULL;
END CASE;
WHEN OTHERS =>
NULL;
END CASE;
END;
PROCEDURE logic_op (
r : registers;
aluin1 : word;
aluin2 : word;
mey : word;
ymsb : std_ulogic;
logicres : out word;
y : out word
) IS
VARIABLE logicout : word;
BEGIN
CASE r.e.aluop IS
WHEN "000" =>
logicout := aluin1 and aluin2;
WHEN "100" =>
logicout := aluin1 and not aluin2;
WHEN "010" =>
logicout := aluin1 or aluin2;
WHEN "101" =>
logicout := aluin1 or not aluin2;
WHEN "001" =>
logicout := aluin1 xor aluin2;
WHEN "011" =>
logicout := aluin1 xor not aluin2;
WHEN "110" =>
logicout := aluin2;
WHEN OTHERS =>
logicout := ( OTHERS => '-' );
END CASE;
IF ( r.e.ctrl.wy and r.e.mulstep ) = '1' THEN
y := ymsb & r.m.y ( 31 downto 1 );
ELSIF r.e.ctrl.wy = '1' THEN
y := logicout;
ELSIF r.m.ctrl.wy = '1' THEN
y := mey;
ELSIF r.x.ctrl.wy = '1' THEN
y := r.x.y;
ELSE
y := r.w.s.y;
END IF;
logicres := logicout;
END;
PROCEDURE misc_op (
r : registers;
wpr : watchpoint_registers;
aluin1 : word;
aluin2 : word;
ldata : word;
mey : word;
mout : out word;
edata : out word
) IS
VARIABLE miscout : word;
VARIABLE bpdata : word;
VARIABLE stdata : word;
VARIABLE wpi : integer;
BEGIN
wpi := 0;
miscout := r.e.ctrl.pc ( 31 downto 2 ) & "00";
edata := aluin1;
bpdata := aluin1;
IF ( ( r.x.ctrl.wreg and r.x.ctrl.ld and not r.x.ctrl.annul ) = '1' ) and ( r.x.ctrl.rd = r.e.ctrl.rd ) and ( r.e.ctrl.inst ( 31 downto 30 ) = LDST ) and ( r.e.ctrl.cnt /= "10" ) THEN
bpdata := ldata;
END IF;
CASE r.e.aluop IS
WHEN "010" =>
miscout := bpdata ( 7 downto 0 ) & bpdata ( 7 downto 0 ) & bpdata ( 7 downto 0 ) & bpdata ( 7 downto 0 );
edata := miscout;
WHEN "011" =>
miscout := bpdata ( 15 downto 0 ) & bpdata ( 15 downto 0 );
edata := miscout;
WHEN "000" =>
miscout := bpdata;
edata := miscout;
WHEN "001" =>
miscout := aluin2;
WHEN "100" =>
miscout := ( OTHERS => '1' );
edata := miscout;
WHEN "101" =>
IF ( r.m.ctrl.wy = '1' ) THEN
miscout := mey;
ELSE
miscout := r.m.y;
END IF;
IF ( r.e.ctrl.inst ( 18 downto 17 ) = "11" ) THEN
wpi := conv_integer ( r.e.ctrl.inst ( 16 downto 15 ) );
IF r.e.ctrl.inst ( 14 ) = '0' THEN
miscout := wpr ( wpi ).addr & '0' & wpr ( wpi ).exec;
ELSE
miscout := wpr ( wpi ).mask & wpr ( wpi ).load & wpr ( wpi ).store;
END IF;
END IF;
IF ( r.e.ctrl.inst ( 18 downto 17 ) = "10" ) and ( r.e.ctrl.inst ( 14 ) = '1' ) THEN
miscout := asr17_gen ( r );
END IF;
WHEN "110" =>
miscout := get_spr ( r );
WHEN OTHERS =>
NULL;
END CASE;
mout := miscout;
END;
PROCEDURE alu_select (
r : registers;
addout : std_logic_vector ( 32 downto 0 );
op1 : word;
op2 : word;
shiftout : word;
logicout : word;
miscout : word;
res : out word;
me_icc : std_logic_vector ( 3 downto 0 );
icco : out std_logic_vector ( 3 downto 0 );
divz : out std_ulogic
) IS
VARIABLE op : std_logic_vector ( 1 downto 0 );
VARIABLE op3 : std_logic_vector ( 5 downto 0 );
VARIABLE icc : std_logic_vector ( 3 downto 0 );
VARIABLE aluresult : word;
BEGIN
op := r.e.ctrl.inst ( 31 downto 30 );
op3 := r.e.ctrl.inst ( 24 downto 19 );
icc := ( OTHERS => '0' );
CASE r.e.alusel IS
WHEN "00" =>
aluresult := addout ( 32 downto 1 );
IF r.e.aluadd = '0' THEN
icc ( 0 ) := ( ( not op1 ( 31 ) ) and not op2 ( 31 ) ) or ( addout ( 32 ) and ( ( not op1 ( 31 ) ) or not op2 ( 31 ) ) );
icc ( 1 ) := ( op1 ( 31 ) and ( op2 ( 31 ) ) and not addout ( 32 ) ) or ( addout ( 32 ) and ( not op1 ( 31 ) ) and not op2 ( 31 ) );
ELSE
icc ( 0 ) := ( op1 ( 31 ) and op2 ( 31 ) ) or ( ( not addout ( 32 ) ) and ( op1 ( 31 ) or op2 ( 31 ) ) );
icc ( 1 ) := ( op1 ( 31 ) and op2 ( 31 ) and not addout ( 32 ) ) or ( addout ( 32 ) and ( not op1 ( 31 ) ) and ( not op2 ( 31 ) ) );
END IF;
CASE op IS
WHEN FMT3 =>
CASE op3 IS
WHEN TADDCC | TADDCCTV =>
icc ( 1 ) := op1 ( 0 ) or op1 ( 1 ) or op2 ( 0 ) or op2 ( 1 ) or icc ( 1 );
WHEN TSUBCC | TSUBCCTV =>
icc ( 1 ) := op1 ( 0 ) or op1 ( 1 ) or ( not op2 ( 0 ) ) or ( not op2 ( 1 ) ) or icc ( 1 );
WHEN OTHERS =>
NULL;
END CASE;
WHEN OTHERS =>
NULL;
END CASE;
IF aluresult = zero32 THEN
icc ( 2 ) := '1';
END IF;
WHEN "01" =>
aluresult := shiftout;
WHEN "10" =>
aluresult := logicout;
IF aluresult = zero32 THEN
icc ( 2 ) := '1';
END IF;
WHEN OTHERS =>
aluresult := miscout;
END CASE;
IF r.e.jmpl = '1' THEN
aluresult := r.e.ctrl.pc ( 31 downto 2 ) & "00";
END IF;
icc ( 3 ) := aluresult ( 31 );
divz := icc ( 2 );
IF r.e.ctrl.wicc = '1' THEN
IF ( op = FMT3 ) and ( op3 = WRPSR ) THEN
icco := logicout ( 23 downto 20 );
ELSE
icco := icc;
END IF;
ELSIF r.m.ctrl.wicc = '1' THEN
icco := me_icc;
ELSIF r.x.ctrl.wicc = '1' THEN
icco := r.x.icc;
ELSE
icco := r.w.s.icc;
END IF;
res := aluresult;
END;
PROCEDURE dcache_gen (
r : registers;
v : registers;
dci : out dc_in_type;
link_pc : out std_ulogic;
jump : out std_ulogic;
force_a2 : out std_ulogic;
load : out std_ulogic
) IS
VARIABLE op : std_logic_vector ( 1 downto 0 );
VARIABLE op3 : std_logic_vector ( 5 downto 0 );
VARIABLE su : std_ulogic;
BEGIN
op := r.e.ctrl.inst ( 31 downto 30 );
op3 := r.e.ctrl.inst ( 24 downto 19 );
dci.signed := '0';
dci.lock := '0';
dci.dsuen := '0';
dci.size := "10";
IF op = LDST THEN
CASE op3 IS
WHEN LDUB | LDUBA =>
dci.size := "00";
WHEN LDSTUB | LDSTUBA =>
dci.size := "00";
dci.lock := '1';
WHEN LDUH | LDUHA =>
dci.size := "01";
WHEN LDSB | LDSBA =>
dci.size := "00";
dci.signed := '1';
WHEN LDSH | LDSHA =>
dci.size := "01";
dci.signed := '1';
WHEN LD | LDA | LDF | LDC =>
dci.size := "10";
WHEN SWAP | SWAPA =>
dci.size := "10";
dci.lock := '1';
WHEN LDD | LDDA | LDDF | LDDC =>
dci.size := "11";
WHEN STB | STBA =>
dci.size := "00";
WHEN STH | STHA =>
dci.size := "01";
WHEN ST | STA | STF =>
dci.size := "10";
WHEN ISTD | STDA =>
dci.size := "11";
WHEN STDF | STDFQ =>
NULL;
WHEN STDC | STDCQ =>
NULL;
WHEN OTHERS =>
dci.size := "10";
dci.lock := '0';
dci.signed := '0';
END CASE;
END IF;
link_pc := '0';
jump := '0';
force_a2 := '0';
load := '0';
dci.write := '0';
dci.enaddr := '0';
dci.read := not op3 ( 2 );
IF ( r.e.ctrl.annul = '0' ) THEN
CASE op IS
WHEN CALL =>
link_pc := '1';
WHEN FMT3 =>
CASE op3 IS
WHEN JMPL =>
jump := '1';
link_pc := '1';
WHEN RETT =>
jump := '1';
WHEN OTHERS =>
NULL;
END CASE;
WHEN LDST =>
CASE r.e.ctrl.cnt IS
WHEN "00" =>
dci.read := op3 ( 3 ) or not op3 ( 2 );
load := op3 ( 3 ) or not op3 ( 2 );
dci.enaddr := '1';
WHEN "01" =>
force_a2 := not op3 ( 2 );
load := not op3 ( 2 );
dci.enaddr := not op3 ( 2 );
IF op3 ( 3 downto 2 ) = "01" THEN
dci.write := '1';
END IF;
IF op3 ( 3 downto 2 ) = "11" THEN
dci.enaddr := '1';
END IF;
WHEN "10" =>
dci.write := '1';
WHEN OTHERS =>
NULL;
END CASE;
IF ( r.e.ctrl.trap or ( v.x.ctrl.trap and not v.x.ctrl.annul ) ) = '1' THEN
dci.enaddr := '0';
END IF;
WHEN OTHERS =>
NULL;
END CASE;
END IF;
IF ( ( r.x.ctrl.rett and not r.x.ctrl.annul ) = '1' ) THEN
su := r.w.s.ps;
ELSE
su := r.w.s.s;
END IF;
IF su = '1' THEN
dci.asi := "00001011";
ELSE
dci.asi := "00001010";
END IF;
IF ( op3 ( 4 ) = '1' ) and ( ( op3 ( 5 ) = '0' ) or not ( 0 = 1 ) ) THEN
dci.asi := r.e.ctrl.inst ( 12 downto 5 );
END IF;
END;
PROCEDURE fpstdata (
r : in registers;
edata : in word;
eres : in word;
fpstdata : in std_logic_vector ( 31 downto 0 );
edata2 : out word;
eres2 : out word
) IS
VARIABLE op : std_logic_vector ( 1 downto 0 );
VARIABLE op3 : std_logic_vector ( 5 downto 0 );
BEGIN
edata2 := edata;
eres2 := eres;
op := r.e.ctrl.inst ( 31 downto 30 );
op3 := r.e.ctrl.inst ( 24 downto 19 );
END;
FUNCTION ld_align (
data : dcdtype;
set : std_logic_vector ( LOG2X ( 2 ) - 1 downto 0 );
size : std_logic_vector ( 1 downto 0 );
laddr : std_logic_vector ( 1 downto 0 );
signed : std_ulogic
) RETURN word IS
VARIABLE align_data : word;
VARIABLE rdata : word;
BEGIN
align_data := data ( conv_integer ( set ) );
rdata := ( OTHERS => '0' );
CASE size IS
WHEN "00" =>
CASE laddr IS
WHEN "00" =>
rdata ( 7 downto 0 ) := align_data ( 31 downto 24 );
IF signed = '1' THEN
rdata ( 31 downto 8 ) := ( OTHERS => align_data ( 31 ) );
END IF;
WHEN "01" =>
rdata ( 7 downto 0 ) := align_data ( 23 downto 16 );
IF signed = '1' THEN
rdata ( 31 downto 8 ) := ( OTHERS => align_data ( 23 ) );
END IF;
WHEN "10" =>
rdata ( 7 downto 0 ) := align_data ( 15 downto 8 );
IF signed = '1' THEN
rdata ( 31 downto 8 ) := ( OTHERS => align_data ( 15 ) );
END IF;
WHEN OTHERS =>
rdata ( 7 downto 0 ) := align_data ( 7 downto 0 );
IF signed = '1' THEN
rdata ( 31 downto 8 ) := ( OTHERS => align_data ( 7 ) );
END IF;
END CASE;
WHEN "01" =>
IF laddr ( 1 ) = '1' THEN
rdata ( 15 downto 0 ) := align_data ( 15 downto 0 );
IF signed = '1' THEN
rdata ( 31 downto 15 ) := ( OTHERS => align_data ( 15 ) );
END IF;
ELSE
rdata ( 15 downto 0 ) := align_data ( 31 downto 16 );
IF signed = '1' THEN
rdata ( 31 downto 15 ) := ( OTHERS => align_data ( 31 ) );
END IF;
END IF;
WHEN OTHERS =>
rdata := align_data;
END CASE;
RETURN ( rdata );
END;
PROCEDURE mem_trap (
r : registers;
wpr : watchpoint_registers;
annul : in std_ulogic;
holdn : in std_ulogic;
trapout : out std_ulogic;
iflush : out std_ulogic;
nullify : out std_ulogic;
werrout : out std_ulogic;
tt : out std_logic_vector ( 5 downto 0 )
) IS
VARIABLE cwp : std_logic_vector ( LOG2 ( 8 ) - 1 downto 0 );
VARIABLE cwpx : std_logic_vector ( 5 downto LOG2 ( 8 ) );
VARIABLE op : std_logic_vector ( 1 downto 0 );
VARIABLE op2 : std_logic_vector ( 2 downto 0 );
VARIABLE op3 : std_logic_vector ( 5 downto 0 );
VARIABLE nalign_d : std_ulogic;
VARIABLE trap : std_ulogic;
VARIABLE werr : std_ulogic;
BEGIN
op := r.m.ctrl.inst ( 31 downto 30 );
op2 := r.m.ctrl.inst ( 24 downto 22 );
op3 := r.m.ctrl.inst ( 24 downto 19 );
cwpx := r.m.result ( 5 downto LOG2 ( 8 ) );
cwpx ( 5 ) := '0';
iflush := '0';
trap := r.m.ctrl.trap;
nullify := annul;
tt := r.m.ctrl.tt;
werr := ( dco.werr or r.m.werr ) and not r.w.s.dwt;
nalign_d := r.m.nalign or r.m.result ( 2 );
IF ( ( annul or trap ) /= '1' ) and ( r.m.ctrl.pv = '1' ) THEN
IF ( werr and holdn ) = '1' THEN
trap := '1';
tt := TT_DSEX;
werr := '0';
IF op = LDST THEN
nullify := '1';
END IF;
END IF;
END IF;
IF ( ( annul or trap ) /= '1' ) THEN
CASE op IS
WHEN FMT2 =>
CASE op2 IS
WHEN FBFCC =>
NULL;
WHEN CBCCC =>
NULL;
WHEN OTHERS =>
NULL;
END CASE;
WHEN FMT3 =>
CASE op3 IS
WHEN WRPSR =>
IF ( orv ( cwpx ) = '1' ) THEN
trap := '1';
tt := TT_IINST;
END IF;
WHEN UDIV | SDIV | UDIVCC | SDIVCC =>
IF r.m.divz = '1' THEN
trap := '1';
tt := TT_DIV;
END IF;
WHEN JMPL | RETT =>
IF r.m.nalign = '1' THEN
trap := '1';
tt := TT_UNALA;
END IF;
WHEN TADDCCTV | TSUBCCTV =>
IF ( r.m.icc ( 1 ) = '1' ) THEN
trap := '1';
tt := TT_TAG;
END IF;
WHEN FLUSH =>
iflush := '1';
WHEN FPOP1 | FPOP2 =>
NULL;
WHEN CPOP1 | CPOP2 =>
NULL;
WHEN OTHERS =>
NULL;
END CASE;
WHEN LDST =>
IF r.m.ctrl.cnt = "00" THEN
CASE op3 IS
WHEN LDDF | STDF | STDFQ =>
NULL;
WHEN LDDC | STDC | STDCQ =>
NULL;
WHEN LDD | ISTD | LDDA | STDA =>
IF r.m.result ( 2 downto 0 ) /= "000" THEN
trap := '1';
tt := TT_UNALA;
nullify := '1';
END IF;
WHEN LDF | LDFSR | STFSR | STF =>
NULL;
WHEN LDC | LDCSR | STCSR | STC =>
NULL;
WHEN LD | LDA | ST | STA | SWAP | SWAPA =>
IF r.m.result ( 1 downto 0 ) /= "00" THEN
trap := '1';
tt := TT_UNALA;
nullify := '1';
END IF;
WHEN LDUH | LDUHA | LDSH | LDSHA | STH | STHA =>
IF r.m.result ( 0 ) /= '0' THEN
trap := '1';
tt := TT_UNALA;
nullify := '1';
END IF;
WHEN OTHERS =>
NULL;
END CASE;
IF ( ( ( ( wpr ( 0 ).load and not op3 ( 2 ) ) or ( wpr ( 0 ).store and op3 ( 2 ) ) ) = '1' ) and ( ( ( wpr ( 0 ).addr xor r.m.result ( 31 downto 2 ) ) and wpr ( 0 ).mask ) = zero32 ( 31 downto 2 ) ) ) THEN
trap := '1';
tt := TT_WATCH;
nullify := '1';
END IF;
IF ( ( ( ( wpr ( 1 ).load and not op3 ( 2 ) ) or ( wpr ( 1 ).store and op3 ( 2 ) ) ) = '1' ) and ( ( ( wpr ( 1 ).addr xor r.m.result ( 31 downto 2 ) ) and wpr ( 1 ).mask ) = zero32 ( 31 downto 2 ) ) ) THEN
trap := '1';
tt := TT_WATCH;
nullify := '1';
END IF;
END IF;
WHEN OTHERS =>
NULL;
END CASE;
END IF;
IF ( rstn = '0' ) or ( r.x.rstate = dsu2 ) THEN
werr := '0';
END IF;
trapout := trap;
werrout := werr;
END;
PROCEDURE irq_trap (
r : in registers;
ir : in irestart_register;
irl : in std_logic_vector ( 3 downto 0 );
annul : in std_ulogic;
pv : in std_ulogic;
trap : in std_ulogic;
tt : in std_logic_vector ( 5 downto 0 );
nullify : in std_ulogic;
irqen : out std_ulogic;
irqen2 : out std_ulogic;
nullify2 : out std_ulogic;
trap2 : out std_ulogic;
ipend : out std_ulogic;
tt2 : out std_logic_vector ( 5 downto 0 )
) IS
VARIABLE op : std_logic_vector ( 1 downto 0 );
VARIABLE op3 : std_logic_vector ( 5 downto 0 );
VARIABLE pend : std_ulogic;
BEGIN
nullify2 := nullify;
trap2 := trap;
tt2 := tt;
op := r.m.ctrl.inst ( 31 downto 30 );
op3 := r.m.ctrl.inst ( 24 downto 19 );
irqen := '1';
irqen2 := r.m.irqen;
IF ( annul or trap ) = '0' THEN
IF ( ( op = FMT3 ) and ( op3 = WRPSR ) ) THEN
irqen := '0';
END IF;
END IF;
IF ( irl = "1111" ) or ( irl > r.w.s.pil ) THEN
pend := r.m.irqen and r.m.irqen2 and r.w.s.et and not ir.pwd;
ELSE
pend := '0';
END IF;
ipend := pend;
IF ( ( not annul ) and pv and ( not trap ) and pend ) = '1' THEN
trap2 := '1';
tt2 := "01" & irl;
IF op = LDST THEN
nullify2 := '1';
END IF;
END IF;
END;
PROCEDURE irq_intack (
r : in registers;
holdn : in std_ulogic;
intack : out std_ulogic
) IS
BEGIN
intack := '0';
IF r.x.rstate = trap THEN
IF r.w.s.tt ( 7 downto 4 ) = "0001" THEN
intack := '1';
END IF;
END IF;
END;
PROCEDURE sp_write (
r : registers;
wpr : watchpoint_registers;
s : out special_register_type;
vwpr : out watchpoint_registers
) IS
VARIABLE op : std_logic_vector ( 1 downto 0 );
VARIABLE op2 : std_logic_vector ( 2 downto 0 );
VARIABLE op3 : std_logic_vector ( 5 downto 0 );
VARIABLE rd : std_logic_vector ( 4 downto 0 );
VARIABLE i : integer RANGE 0 to 3;
BEGIN
op := r.x.ctrl.inst ( 31 downto 30 );
op2 := r.x.ctrl.inst ( 24 downto 22 );
op3 := r.x.ctrl.inst ( 24 downto 19 );
s := r.w.s;
rd := r.x.ctrl.inst ( 29 downto 25 );
vwpr := wpr;
CASE op IS
WHEN FMT3 =>
CASE op3 IS
WHEN WRY =>
IF rd = "00000" THEN
s.y := r.x.result;
ELSIF ( rd = "10001" ) THEN
s.dwt := r.x.result ( 14 );
s.svt := r.x.result ( 13 );
ELSIF rd ( 4 downto 3 ) = "11" THEN
CASE rd ( 2 downto 0 ) IS
WHEN "000" =>
vwpr ( 0 ).addr := r.x.result ( 31 downto 2 );
vwpr ( 0 ).exec := r.x.result ( 0 );
WHEN "001" =>
vwpr ( 0 ).mask := r.x.result ( 31 downto 2 );
vwpr ( 0 ).load := r.x.result ( 1 );
vwpr ( 0 ).store := r.x.result ( 0 );
WHEN "010" =>
vwpr ( 1 ).addr := r.x.result ( 31 downto 2 );
vwpr ( 1 ).exec := r.x.result ( 0 );
WHEN "011" =>
vwpr ( 1 ).mask := r.x.result ( 31 downto 2 );
vwpr ( 1 ).load := r.x.result ( 1 );
vwpr ( 1 ).store := r.x.result ( 0 );
WHEN "100" =>
vwpr ( 2 ).addr := r.x.result ( 31 downto 2 );
vwpr ( 2 ).exec := r.x.result ( 0 );
WHEN "101" =>
vwpr ( 2 ).mask := r.x.result ( 31 downto 2 );
vwpr ( 2 ).load := r.x.result ( 1 );
vwpr ( 2 ).store := r.x.result ( 0 );
WHEN "110" =>
vwpr ( 3 ).addr := r.x.result ( 31 downto 2 );
vwpr ( 3 ).exec := r.x.result ( 0 );
WHEN OTHERS =>
vwpr ( 3 ).mask := r.x.result ( 31 downto 2 );
vwpr ( 3 ).load := r.x.result ( 1 );
vwpr ( 3 ).store := r.x.result ( 0 );
END CASE;
END IF;
WHEN WRPSR =>
s.cwp := r.x.result ( LOG2 ( 8 ) - 1 downto 0 );
s.icc := r.x.result ( 23 downto 20 );
s.ec := r.x.result ( 13 );
s.pil := r.x.result ( 11 downto 8 );
s.s := r.x.result ( 7 );
s.ps := r.x.result ( 6 );
s.et := r.x.result ( 5 );
WHEN WRWIM =>
s.wim := r.x.result ( 8 - 1 downto 0 );
WHEN WRTBR =>
s.tba := r.x.result ( 31 downto 12 );
WHEN SAVE =>
s.cwp := r.w.s.cwp - 1;
WHEN RESTORE =>
s.cwp := r.w.s.cwp + 1;
WHEN RETT =>
s.cwp := r.w.s.cwp + 1;
s.s := r.w.s.ps;
s.et := '1';
WHEN OTHERS =>
NULL;
END CASE;
WHEN OTHERS =>
NULL;
END CASE;
IF r.x.ctrl.wicc = '1' THEN
s.icc := r.x.icc;
END IF;
IF r.x.ctrl.wy = '1' THEN
s.y := r.x.y;
END IF;
END;
FUNCTION npc_find (
r : registers
) RETURN std_logic_vector IS
VARIABLE npc : std_logic_vector ( 2 downto 0 );
BEGIN
npc := "011";
IF r.m.ctrl.pv = '1' THEN
npc := "000";
ELSIF r.e.ctrl.pv = '1' THEN
npc := "001";
ELSIF r.a.ctrl.pv = '1' THEN
npc := "010";
ELSIF r.d.pv = '1' THEN
npc := "011";
ELSE
npc := "100";
END IF;
RETURN ( npc );
END;
FUNCTION npc_gen (
r : registers
) RETURN word IS
VARIABLE npc : std_logic_vector ( 31 downto 0 );
BEGIN
npc := r.a.ctrl.pc ( 31 downto 2 ) & "00";
CASE r.x.npc IS
WHEN "000" =>
npc ( 31 downto 2 ) := r.x.ctrl.pc ( 31 downto 2 );
WHEN "001" =>
npc ( 31 downto 2 ) := r.m.ctrl.pc ( 31 downto 2 );
WHEN "010" =>
npc ( 31 downto 2 ) := r.e.ctrl.pc ( 31 downto 2 );
WHEN "011" =>
npc ( 31 downto 2 ) := r.a.ctrl.pc ( 31 downto 2 );
WHEN OTHERS =>
npc ( 31 downto 2 ) := r.d.pc ( 31 downto 2 );
END CASE;
RETURN ( npc );
END;
PROCEDURE mul_res (
r : registers;
asr18in : word;
result : out word;
y : out word;
asr18 : out word;
icc : out std_logic_vector ( 3 downto 0 )
) IS
VARIABLE op : std_logic_vector ( 1 downto 0 );
VARIABLE op3 : std_logic_vector ( 5 downto 0 );
BEGIN
op := r.m.ctrl.inst ( 31 downto 30 );
op3 := r.m.ctrl.inst ( 24 downto 19 );
result := r.m.result;
y := r.m.y;
icc := r.m.icc;
asr18 := asr18in;
CASE op IS
WHEN FMT3 =>
CASE op3 IS
WHEN UMUL | SMUL =>
result := mulo.result ( 31 downto 0 );
y := mulo.result ( 63 downto 32 );
WHEN UMULCC | SMULCC =>
result := mulo.result ( 31 downto 0 );
icc := mulo.icc;
y := mulo.result ( 63 downto 32 );
WHEN UMAC | SMAC =>
NULL;
WHEN UDIV | SDIV =>
result := divo.result ( 31 downto 0 );
WHEN UDIVCC | SDIVCC =>
result := divo.result ( 31 downto 0 );
icc := divo.icc;
WHEN OTHERS =>
NULL;
END CASE;
WHEN OTHERS =>
NULL;
END CASE;
END;
FUNCTION powerdwn (
r : registers;
trap : std_ulogic;
rp : pwd_register_type
) RETURN std_ulogic IS
VARIABLE op : std_logic_vector ( 1 downto 0 );
VARIABLE op3 : std_logic_vector ( 5 downto 0 );
VARIABLE rd : std_logic_vector ( 4 downto 0 );
VARIABLE pd : std_ulogic;
BEGIN
op := r.x.ctrl.inst ( 31 downto 30 );
op3 := r.x.ctrl.inst ( 24 downto 19 );
rd := r.x.ctrl.inst ( 29 downto 25 );
pd := '0';
IF ( not ( r.x.ctrl.annul or trap ) and r.x.ctrl.pv ) = '1' THEN
IF ( ( op = FMT3 ) and ( op3 = WRY ) and ( rd = "10011" ) ) THEN
pd := '1';
END IF;
pd := pd or rp.pwd;
END IF;
RETURN ( pd );
END;
SIGNAL dummy : std_ulogic;
SIGNAL cpu_index : std_logic_vector ( 3 downto 0 );
SIGNAL disasen : std_ulogic;
BEGIN
comb : PROCESS ( ico , dco , rfo , r , wpr , ir , dsur , rstn , holdn , irqi , dbgi , fpo , cpo , tbo , mulo , divo , dummy , rp )
VARIABLE v : registers;
VARIABLE vp : pwd_register_type;
VARIABLE vwpr : watchpoint_registers;
VARIABLE vdsu : dsu_registers;
VARIABLE npc : std_logic_vector ( 31 downto 2 );
VARIABLE de_raddr1 : std_logic_vector ( 9 downto 0 );
VARIABLE de_raddr2 : std_logic_vector ( 9 downto 0 );
VARIABLE de_rs2 : std_logic_vector ( 4 downto 0 );
VARIABLE de_rd : std_logic_vector ( 4 downto 0 );
VARIABLE de_hold_pc : std_ulogic;
VARIABLE de_branch : std_ulogic;
VARIABLE de_fpop : std_ulogic;
VARIABLE de_ldlock : std_ulogic;
VARIABLE de_cwp : cwptype;
VARIABLE de_cwp2 : cwptype;
VARIABLE de_inull : std_ulogic;
VARIABLE de_ren1 : std_ulogic;
VARIABLE de_ren2 : std_ulogic;
VARIABLE de_wcwp : std_ulogic;
VARIABLE de_inst : word;
VARIABLE de_branch_address : pctype;
VARIABLE de_icc : std_logic_vector ( 3 downto 0 );
VARIABLE de_fbranch : std_ulogic;
VARIABLE de_cbranch : std_ulogic;
VARIABLE de_rs1mod : std_ulogic;
VARIABLE ra_op1 : word;
VARIABLE ra_op2 : word;
VARIABLE ra_div : std_ulogic;
VARIABLE ex_jump : std_ulogic;
VARIABLE ex_link_pc : std_ulogic;
VARIABLE ex_jump_address : pctype;
VARIABLE ex_add_res : std_logic_vector ( 32 downto 0 );
VARIABLE ex_shift_res : word;
VARIABLE ex_logic_res : word;
VARIABLE ex_misc_res : word;
VARIABLE ex_edata : word;
VARIABLE ex_edata2 : word;
VARIABLE ex_dci : dc_in_type;
VARIABLE ex_force_a2 : std_ulogic;
VARIABLE ex_load : std_ulogic;
VARIABLE ex_ymsb : std_ulogic;
VARIABLE ex_op1 : word;
VARIABLE ex_op2 : word;
VARIABLE ex_result : word;
VARIABLE ex_result2 : word;
VARIABLE mul_op2 : word;
VARIABLE ex_shcnt : std_logic_vector ( 4 downto 0 );
VARIABLE ex_dsuen : std_ulogic;
VARIABLE ex_ldbp2 : std_ulogic;
VARIABLE ex_sari : std_ulogic;
VARIABLE me_inull : std_ulogic;
VARIABLE me_nullify : std_ulogic;
VARIABLE me_nullify2 : std_ulogic;
VARIABLE me_iflush : std_ulogic;
VARIABLE me_newtt : std_logic_vector ( 5 downto 0 );
VARIABLE me_asr18 : word;
VARIABLE me_signed : std_ulogic;
VARIABLE me_size : std_logic_vector ( 1 downto 0 );
VARIABLE me_laddr : std_logic_vector ( 1 downto 0 );
VARIABLE me_icc : std_logic_vector ( 3 downto 0 );
VARIABLE xc_result : word;
VARIABLE xc_df_result : word;
VARIABLE xc_waddr : std_logic_vector ( 9 downto 0 );
VARIABLE xc_exception : std_ulogic;
VARIABLE xc_wreg : std_ulogic;
VARIABLE xc_trap_address : pctype;
VARIABLE xc_vectt : std_logic_vector ( 7 downto 0 );
VARIABLE xc_trap : std_ulogic;
VARIABLE xc_fpexack : std_ulogic;
VARIABLE xc_rstn : std_ulogic;
VARIABLE xc_halt : std_ulogic;
VARIABLE diagdata : word;
VARIABLE tbufi : tracebuf_in_type;
VARIABLE dbgm : std_ulogic;
VARIABLE fpcdbgwr : std_ulogic;
VARIABLE vfpi : fpc_in_type;
VARIABLE dsign : std_ulogic;
VARIABLE pwrd : std_ulogic;
VARIABLE sidle : std_ulogic;
VARIABLE vir : irestart_register;
VARIABLE icnt : std_ulogic;
VARIABLE tbufcntx : std_logic_vector ( 10 + LOG2 ( 2 ) - 4 - 1 downto 0 );
BEGIN
v := r;
vwpr := wpr;
vdsu := dsur;
vp := rp;
xc_fpexack := '0';
sidle := '0';
fpcdbgwr := '0';
vir := ir;
xc_rstn := rstn;
xc_exception := '0';
xc_halt := '0';
icnt := '0';
xc_waddr := ( OTHERS => '0' );
xc_waddr ( LOG2 ( 8 + 1 ) + 4 - 1 downto 0 ) := r.x.ctrl.rd ( LOG2 ( 8 + 1 ) + 4 - 1 downto 0 );
xc_trap := r.x.mexc or r.x.ctrl.trap;
v.x.nerror := rp.error;
IF r.x.mexc = '1' THEN
xc_vectt := "00" & TT_DAEX;
ELSIF r.x.ctrl.tt = TT_TICC THEN
xc_vectt := '1' & r.x.result ( 6 downto 0 );
ELSE
xc_vectt := "00" & r.x.ctrl.tt;
END IF;
IF r.w.s.svt = '0' THEN
xc_trap_address ( 31 downto 4 ) := r.w.s.tba & xc_vectt;
ELSE
xc_trap_address ( 31 downto 4 ) := r.w.s.tba & "00000000";
END IF;
xc_trap_address ( 3 downto 2 ) := ( OTHERS => '0' );
xc_wreg := '0';
v.x.annul_all := '0';
IF ( r.x.ctrl.ld = '1' ) THEN
xc_result := r.x.data ( 0 );
ELSE
xc_result := r.x.result;
END IF;
xc_df_result := xc_result;
dbgm := dbgexc ( r , dbgi , xc_trap , xc_vectt );
IF ( dbgi.dsuen and dbgi.dbreak ) = '0' THEN
v.x.debug := '0';
END IF;
pwrd := '0';
CASE r.x.rstate IS
WHEN run =>
IF ( not r.x.ctrl.annul and r.x.ctrl.pv and not r.x.debug ) = '1' THEN
icnt := holdn;
END IF;
IF dbgm = '1' THEN
v.x.annul_all := '1';
vir.addr := r.x.ctrl.pc;
v.x.rstate := dsu1;
v.x.debug := '1';
v.x.npc := npc_find ( r );
vdsu.tt := xc_vectt;
vdsu.err := dbgerr ( r , dbgi , xc_vectt );
ELSIF ( pwrd = '1' ) and ( ir.pwd = '0' ) THEN
v.x.annul_all := '1';
vir.addr := r.x.ctrl.pc;
v.x.rstate := dsu1;
v.x.npc := npc_find ( r );
vp.pwd := '1';
ELSIF ( r.x.ctrl.annul or xc_trap ) = '0' THEN
xc_wreg := r.x.ctrl.wreg;
sp_write ( r , wpr , v.w.s , vwpr );
vir.pwd := '0';
ELSIF ( ( not r.x.ctrl.annul ) and xc_trap ) = '1' THEN
xc_exception := '1';
xc_result := r.x.ctrl.pc ( 31 downto 2 ) & "00";
xc_wreg := '1';
v.w.s.tt := xc_vectt;
v.w.s.ps := r.w.s.s;
v.w.s.s := '1';
v.x.annul_all := '1';
v.x.rstate := trap;
xc_waddr := ( OTHERS => '0' );
xc_waddr ( LOG2 ( 8 ) + 3 downto 0 ) := r.w.s.cwp & "0001";
v.x.npc := npc_find ( r );
fpexack ( r , xc_fpexack );
IF r.w.s.et = '0' THEN
xc_wreg := '0';
END IF;
END IF;
WHEN trap =>
xc_result := npc_gen ( r );
xc_wreg := '1';
xc_waddr := ( OTHERS => '0' );
xc_waddr ( LOG2 ( 8 ) + 3 downto 0 ) := r.w.s.cwp & "0010";
IF ( r.w.s.et = '1' ) THEN
v.w.s.et := '0';
v.x.rstate := run;
v.w.s.cwp := r.w.s.cwp - 1;
ELSE
v.x.rstate := dsu1;
xc_wreg := '0';
vp.error := '1';
END IF;
WHEN dsu1 =>
xc_exception := '1';
v.x.annul_all := '1';
xc_trap_address ( 31 downto 2 ) := r.f.pc;
xc_trap_address ( 31 downto 2 ) := ir.addr;
vir.addr := npc_gen ( r ) ( 31 downto 2 );
v.x.rstate := dsu2;
v.x.debug := r.x.debug;
WHEN dsu2 =>
xc_exception := '1';
v.x.annul_all := '1';
xc_trap_address ( 31 downto 2 ) := r.f.pc;
sidle := ( rp.pwd or rp.error ) and ico.idle and dco.idle and not r.x.debug;
IF dbgi.reset = '1' THEN
vp.pwd := '0';
vp.error := '0';
END IF;
IF ( dbgi.dsuen and dbgi.dbreak ) = '1' THEN
v.x.debug := '1';
END IF;
diagwr ( r , dsur , ir , dbgi , wpr , v.w.s , vwpr , vdsu.asi , xc_trap_address , vir.addr , vdsu.tbufcnt , xc_wreg , xc_waddr , xc_result , fpcdbgwr );
xc_halt := dbgi.halt;
IF r.x.ipend = '1' THEN
vp.pwd := '0';
END IF;
IF ( rp.error or rp.pwd or r.x.debug or xc_halt ) = '0' THEN
v.x.rstate := run;
v.x.annul_all := '0';
vp.error := '0';
xc_trap_address ( 31 downto 2 ) := ir.addr;
v.x.debug := '0';
vir.pwd := '1';
END IF;
WHEN OTHERS =>
NULL;
END CASE;
irq_intack ( r , holdn , v.x.intack );
itrace ( r , dsur , vdsu , xc_result , xc_exception , dbgi , rp.error , xc_trap , tbufcntx , tbufi );
vdsu.tbufcnt := tbufcntx;
v.w.except := xc_exception;
v.w.result := xc_result;
IF ( r.x.rstate = dsu2 ) THEN
v.w.except := '0';
END IF;
v.w.wa := xc_waddr ( LOG2 ( 8 + 1 ) + 4 - 1 downto 0 );
v.w.wreg := xc_wreg and holdn;
rfi.wdata <= xc_result;
rfi.waddr <= xc_waddr;
rfi.wren <= ( xc_wreg and holdn ) and not dco.scanen;
irqo.intack <= r.x.intack and holdn;
irqo.irl <= r.w.s.tt ( 3 downto 0 );
irqo.pwd <= rp.pwd;
dbgo.halt <= xc_halt;
dbgo.pwd <= rp.pwd;
dbgo.idle <= sidle;
dbgo.icnt <= icnt;
dci.intack <= r.x.intack and holdn;
IF ( xc_rstn = '0' ) THEN
v.w.except := '0';
v.w.s.et := '0';
v.w.s.svt := '0';
v.w.s.dwt := '0';
v.x.annul_all := '1';
v.x.rstate := run;
vir.pwd := '0';
vp.pwd := '0';
v.x.debug := '0';
v.x.nerror := '0';
v.w.s.tt := ( OTHERS => '0' );
IF ( dbgi.dsuen and dbgi.dbreak ) = '1' THEN
v.x.rstate := dsu1;
v.x.debug := '1';
END IF;
END IF;
v.w.s.ef := '0';
v.x.ctrl := r.m.ctrl;
v.x.dci := r.m.dci;
v.x.ctrl.rett := r.m.ctrl.rett and not r.m.ctrl.annul;
v.x.mac := r.m.mac;
v.x.laddr := r.m.result ( 1 downto 0 );
v.x.ctrl.annul := r.m.ctrl.annul or v.x.annul_all;
mul_res ( r , v.w.s.asr18 , v.x.result , v.x.y , me_asr18 , me_icc );
mem_trap ( r , wpr , v.x.ctrl.annul , holdn , v.x.ctrl.trap , me_iflush , me_nullify , v.m.werr , v.x.ctrl.tt );
me_newtt := v.x.ctrl.tt;
irq_trap ( r , ir , irqi.irl , v.x.ctrl.annul , v.x.ctrl.pv , v.x.ctrl.trap , me_newtt , me_nullify , v.m.irqen , v.m.irqen2 , me_nullify2 , v.x.ctrl.trap , v.x.ipend , v.x.ctrl.tt );
IF ( r.m.ctrl.ld or not dco.mds ) = '1' THEN
v.x.data ( 0 ) := dco.data ( 0 );
v.x.data ( 1 ) := dco.data ( 1 );
v.x.set := dco.set ( LOG2X ( 2 ) - 1 downto 0 );
IF dco.mds = '0' THEN
me_size := r.x.dci.size;
me_laddr := r.x.laddr;
me_signed := r.x.dci.signed;
ELSE
me_size := v.x.dci.size;
me_laddr := v.x.laddr;
me_signed := v.x.dci.signed;
END IF;
v.x.data ( 0 ) := ld_align ( v.x.data , v.x.set , me_size , me_laddr , me_signed );
END IF;
v.x.mexc := dco.mexc;
v.x.icc := me_icc;
v.x.ctrl.wicc := r.m.ctrl.wicc and not v.x.annul_all;
IF ( r.x.rstate = dsu2 ) THEN
me_nullify2 := '0';
v.x.set := dco.set ( LOG2X ( 2 ) - 1 downto 0 );
END IF;
dci.maddress <= r.m.result;
dci.enaddr <= r.m.dci.enaddr;
dci.asi <= r.m.dci.asi;
dci.size <= r.m.dci.size;
dci.nullify <= me_nullify2;
dci.lock <= r.m.dci.lock and not r.m.ctrl.annul;
dci.read <= r.m.dci.read;
dci.write <= r.m.dci.write;
dci.flush <= me_iflush;
dci.dsuen <= r.m.dci.dsuen;
dci.msu <= r.m.su;
dci.esu <= r.e.su;
dbgo.ipend <= v.x.ipend;
v.m.ctrl := r.e.ctrl;
ex_op1 := r.e.op1;
ex_op2 := r.e.op2;
v.m.ctrl.rett := r.e.ctrl.rett and not r.e.ctrl.annul;
v.m.ctrl.wreg := r.e.ctrl.wreg and not v.x.annul_all;
ex_ymsb := r.e.ymsb;
mul_op2 := ex_op2;
ex_shcnt := r.e.shcnt;
v.e.cwp := r.a.cwp;
ex_sari := r.e.sari;
v.m.su := r.e.su;
v.m.mul := '0';
IF r.e.ldbp1 = '1' THEN
ex_op1 := r.x.data ( 0 );
ex_sari := r.x.data ( 0 ) ( 31 ) and r.e.ctrl.inst ( 19 ) and r.e.ctrl.inst ( 20 );
END IF;
IF r.e.ldbp2 = '1' THEN
ex_op2 := r.x.data ( 0 );
ex_ymsb := r.x.data ( 0 ) ( 0 );
mul_op2 := ex_op2;
ex_shcnt := r.x.data ( 0 ) ( 4 downto 0 );
IF r.e.invop2 = '1' THEN
ex_op2 := not ex_op2;
ex_shcnt := not ex_shcnt;
END IF;
END IF;
ex_add_res := ( ex_op1 & '1' ) + ( ex_op2 & r.e.alucin );
IF ex_add_res ( 2 downto 1 ) = "00" THEN
v.m.nalign := '0';
ELSE
v.m.nalign := '1';
END IF;
dcache_gen ( r , v , ex_dci , ex_link_pc , ex_jump , ex_force_a2 , ex_load );
ex_jump_address := ex_add_res ( 32 downto 2 + 1 );
logic_op ( r , ex_op1 , ex_op2 , v.x.y , ex_ymsb , ex_logic_res , v.m.y );
ex_shift_res := shift ( r , ex_op1 , ex_op2 , ex_shcnt , ex_sari );
misc_op ( r , wpr , ex_op1 , ex_op2 , xc_df_result , v.x.y , ex_misc_res , ex_edata );
ex_add_res ( 3 ) := ex_add_res ( 3 ) or ex_force_a2;
alu_select ( r , ex_add_res , ex_op1 , ex_op2 , ex_shift_res , ex_logic_res , ex_misc_res , ex_result , me_icc , v.m.icc , v.m.divz );
dbg_cache ( holdn , dbgi , r , dsur , ex_result , ex_dci , ex_result2 , v.m.dci );
fpstdata ( r , ex_edata , ex_result2 , fpo.data , ex_edata2 , v.m.result );
cwp_ex ( r , v.m.wcwp );
v.m.ctrl.annul := v.m.ctrl.annul or v.x.annul_all;
v.m.ctrl.wicc := r.e.ctrl.wicc and not v.x.annul_all;
v.m.mac := r.e.mac;
IF ( r.x.rstate = dsu2 ) THEN
v.m.ctrl.ld := '1';
END IF;
dci.eenaddr <= v.m.dci.enaddr;
dci.eaddress <= ex_add_res ( 32 downto 1 );
dci.edata <= ex_edata2;
v.e.ctrl := r.a.ctrl;
v.e.jmpl := r.a.jmpl;
v.e.ctrl.annul := r.a.ctrl.annul or v.x.annul_all;
v.e.ctrl.rett := r.a.ctrl.rett and not r.a.ctrl.annul;
v.e.ctrl.wreg := r.a.ctrl.wreg and not v.x.annul_all;
v.e.su := r.a.su;
v.e.et := r.a.et;
v.e.ctrl.wicc := r.a.ctrl.wicc and not v.x.annul_all;
exception_detect ( r , wpr , dbgi , r.a.ctrl.trap , r.a.ctrl.tt , v.e.ctrl.trap , v.e.ctrl.tt );
op_mux ( r , rfo.data1 , v.m.result , v.x.result , xc_df_result , zero32 , r.a.rsel1 , v.e.ldbp1 , ra_op1 );
op_mux ( r , rfo.data2 , v.m.result , v.x.result , xc_df_result , r.a.imm , r.a.rsel2 , ex_ldbp2 , ra_op2 );
alu_op ( r , ra_op1 , ra_op2 , v.m.icc , v.m.y ( 0 ) , ex_ldbp2 , v.e.op1 , v.e.op2 , v.e.aluop , v.e.alusel , v.e.aluadd , v.e.shcnt , v.e.sari , v.e.shleft , v.e.ymsb , v.e.mul , ra_div , v.e.mulstep , v.e.mac , v.e.ldbp2 , v.e.invop2 );
cin_gen ( r , v.m.icc ( 0 ) , v.e.alucin );
de_inst := r.d.inst ( conv_integer ( r.d.set ) );
de_icc := r.m.icc;
v.a.cwp := r.d.cwp;
su_et_select ( r , v.w.s.ps , v.w.s.s , v.w.s.et , v.a.su , v.a.et );
wicc_y_gen ( de_inst , v.a.ctrl.wicc , v.a.ctrl.wy );
cwp_ctrl ( r , v.w.s.wim , de_inst , de_cwp , v.a.wovf , v.a.wunf , de_wcwp );
rs1_gen ( r , de_inst , v.a.rs1 , de_rs1mod );
de_rs2 := de_inst ( 4 downto 0 );
de_raddr1 := ( OTHERS => '0' );
de_raddr2 := ( OTHERS => '0' );
IF de_rs1mod = '1' THEN
regaddr ( r.d.cwp , de_inst ( 29 downto 26 ) & v.a.rs1 ( 0 ) , de_raddr1 ( LOG2 ( 8 + 1 ) + 4 - 1 downto 0 ) );
ELSE
regaddr ( r.d.cwp , de_inst ( 18 downto 15 ) & v.a.rs1 ( 0 ) , de_raddr1 ( LOG2 ( 8 + 1 ) + 4 - 1 downto 0 ) );
END IF;
regaddr ( r.d.cwp , de_rs2 , de_raddr2 ( LOG2 ( 8 + 1 ) + 4 - 1 downto 0 ) );
v.a.rfa1 := de_raddr1 ( LOG2 ( 8 + 1 ) + 4 - 1 downto 0 );
v.a.rfa2 := de_raddr2 ( LOG2 ( 8 + 1 ) + 4 - 1 downto 0 );
rd_gen ( r , de_inst , v.a.ctrl.wreg , v.a.ctrl.ld , de_rd );
regaddr ( de_cwp , de_rd , v.a.ctrl.rd );
fpbranch ( de_inst , fpo.cc , de_fbranch );
fpbranch ( de_inst , cpo.cc , de_cbranch );
v.a.imm := imm_data ( r , de_inst );
lock_gen ( r , de_rs2 , de_rd , v.a.rfa1 , v.a.rfa2 , v.a.ctrl.rd , de_inst , fpo.ldlock , v.e.mul , ra_div , v.a.ldcheck1 , v.a.ldcheck2 , de_ldlock , v.a.ldchkra , v.a.ldchkex );
ic_ctrl ( r , de_inst , v.x.annul_all , de_ldlock , branch_true ( de_icc , de_inst ) , de_fbranch , de_cbranch , fpo.ccv , cpo.ccv , v.d.cnt , v.d.pc , de_branch , v.a.ctrl.annul , v.d.annul , v.a.jmpl , de_inull , v.d.pv , v.a.ctrl.pv , de_hold_pc , v.a.ticc , v.a.ctrl.rett , v.a.mulstart , v.a.divstart );
cwp_gen ( r , v , v.a.ctrl.annul , de_wcwp , de_cwp , v.d.cwp );
v.d.inull := ra_inull_gen ( r , v );
op_find ( r , v.a.ldchkra , v.a.ldchkex , v.a.rs1 , v.a.rfa1 , false , v.a.rfe1 , v.a.rsel1 , v.a.ldcheck1 );
op_find ( r , v.a.ldchkra , v.a.ldchkex , de_rs2 , v.a.rfa2 , imm_select ( de_inst ) , v.a.rfe2 , v.a.rsel2 , v.a.ldcheck2 );
de_branch_address := branch_address ( de_inst , r.d.pc );
v.a.ctrl.annul := v.a.ctrl.annul or v.x.annul_all;
v.a.ctrl.wicc := v.a.ctrl.wicc and not v.a.ctrl.annul;
v.a.ctrl.wreg := v.a.ctrl.wreg and not v.a.ctrl.annul;
v.a.ctrl.rett := v.a.ctrl.rett and not v.a.ctrl.annul;
v.a.ctrl.wy := v.a.ctrl.wy and not v.a.ctrl.annul;
v.a.ctrl.trap := r.d.mexc;
v.a.ctrl.tt := "000000";
v.a.ctrl.inst := de_inst;
v.a.ctrl.pc := r.d.pc;
v.a.ctrl.cnt := r.d.cnt;
v.a.step := r.d.step;
IF holdn = '0' THEN
de_raddr1 ( LOG2 ( 8 + 1 ) + 4 - 1 downto 0 ) := r.a.rfa1;
de_raddr2 ( LOG2 ( 8 + 1 ) + 4 - 1 downto 0 ) := r.a.rfa2;
de_ren1 := r.a.rfe1;
de_ren2 := r.a.rfe2;
ELSE
de_ren1 := v.a.rfe1;
de_ren2 := v.a.rfe2;
END IF;
IF ( ( dbgi.denable and not dbgi.dwrite ) = '1' ) and ( r.x.rstate = dsu2 ) THEN
de_raddr1 ( LOG2 ( 8 + 1 ) + 4 - 1 downto 0 ) := dbgi.daddr ( LOG2 ( 8 + 1 ) + 4 + 1 downto 2 );
de_ren1 := '1';
END IF;
v.d.step := dbgi.step and not r.d.annul;
rfi.raddr1 <= de_raddr1;
rfi.raddr2 <= de_raddr2;
rfi.ren1 <= de_ren1 and not dco.scanen;
rfi.ren2 <= de_ren2 and not dco.scanen;
rfi.diag <= dco.testen & "000";
ici.inull <= de_inull;
ici.flush <= me_iflush;
IF ( xc_rstn = '0' ) THEN
v.d.cnt := ( OTHERS => '0' );
END IF;
npc := r.f.pc;
IF ( xc_rstn = '0' ) THEN
v.f.pc := ( OTHERS => '0' );
v.f.branch := '0';
v.f.pc ( 31 downto 12 ) := conv_std_logic_vector ( 16#00000# , 20 );
ELSIF xc_exception = '1' THEN
v.f.branch := '1';
v.f.pc := xc_trap_address;
npc := v.f.pc;
ELSIF de_hold_pc = '1' THEN
v.f.pc := r.f.pc;
v.f.branch := r.f.branch;
IF ex_jump = '1' THEN
v.f.pc := ex_jump_address;
v.f.branch := '1';
npc := v.f.pc;
END IF;
ELSIF ex_jump = '1' THEN
v.f.pc := ex_jump_address;
v.f.branch := '1';
npc := v.f.pc;
ELSIF de_branch = '1' THEN
v.f.pc := branch_address ( de_inst , r.d.pc );
v.f.branch := '1';
npc := v.f.pc;
ELSE
v.f.branch := '0';
v.f.pc ( 31 downto 2 ) := r.f.pc ( 31 downto 2 ) + 1;
npc := v.f.pc;
END IF;
ici.dpc <= r.d.pc ( 31 downto 2 ) & "00";
ici.fpc <= r.f.pc ( 31 downto 2 ) & "00";
ici.rpc <= npc ( 31 downto 2 ) & "00";
ici.fbranch <= r.f.branch;
ici.rbranch <= v.f.branch;
ici.su <= v.a.su;
ici.fline <= ( OTHERS => '0' );
ici.flushl <= '0';
IF ( ico.mds and de_hold_pc ) = '0' THEN
v.d.inst ( 0 ) := ico.data ( 0 );
v.d.inst ( 1 ) := ico.data ( 1 );
v.d.set := ico.set ( LOG2X ( 2 ) - 1 downto 0 );
v.d.mexc := ico.mexc;
END IF;
diagread ( dbgi , r , dsur , ir , wpr , rfo.data1 , dco , tbo , diagdata );
diagrdy ( dbgi.denable , dsur , r.m.dci , dco.mds , ico , vdsu.crdy );
rin <= v;
wprin <= vwpr;
dsuin <= vdsu;
irin <= vir;
muli.start <= r.a.mulstart and not r.a.ctrl.annul;
muli.signed <= r.e.ctrl.inst ( 19 );
muli.op1 <= ( ex_op1 ( 31 ) and r.e.ctrl.inst ( 19 ) ) & ex_op1;
muli.op2 <= ( mul_op2 ( 31 ) and r.e.ctrl.inst ( 19 ) ) & mul_op2;
muli.mac <= r.e.ctrl.inst ( 24 );
muli.acc ( 39 downto 32 ) <= r.x.y ( 7 downto 0 );
muli.acc ( 31 downto 0 ) <= r.w.s.asr18;
muli.flush <= r.x.annul_all;
divi.start <= r.a.divstart and not r.a.ctrl.annul;
divi.signed <= r.e.ctrl.inst ( 19 );
divi.flush <= r.x.annul_all;
divi.op1 <= ( ex_op1 ( 31 ) and r.e.ctrl.inst ( 19 ) ) & ex_op1;
divi.op2 <= ( ex_op2 ( 31 ) and r.e.ctrl.inst ( 19 ) ) & ex_op2;
IF ( r.a.divstart and not r.a.ctrl.annul ) = '1' THEN
dsign := r.a.ctrl.inst ( 19 );
ELSE
dsign := r.e.ctrl.inst ( 19 );
END IF;
divi.y <= ( r.m.y ( 31 ) and dsign ) & r.m.y;
rpin <= vp;
dbgo.dsu <= '1';
dbgo.dsumode <= r.x.debug;
dbgo.crdy <= dsur.crdy ( 2 );
dbgo.data <= diagdata;
tbi <= tbufi;
dbgo.error <= dummy and not r.x.nerror;
END PROCESS;
preg : PROCESS ( sclk )
BEGIN
IF rising_edge ( sclk ) THEN
rp <= rpin;
IF rstn = '0' THEN
rp.error <= '0';
END IF;
END IF;
END PROCESS;
reg : PROCESS ( clk )
BEGIN
IF rising_edge ( clk ) THEN
IF ( holdn = '1' ) THEN
r <= rin;
ELSE
r.x.ipend <= rin.x.ipend;
r.m.werr <= rin.m.werr;
IF ( holdn or ico.mds ) = '0' THEN
r.d.inst <= rin.d.inst;
r.d.mexc <= rin.d.mexc;
r.d.set <= rin.d.set;
END IF;
IF ( holdn or dco.mds ) = '0' THEN
r.x.data <= rin.x.data;
r.x.mexc <= rin.x.mexc;
r.x.set <= rin.x.set;
END IF;
END IF;
IF rstn = '0' THEN
r.w.s.s <= '1';
END IF;
IF ( hackState = "11" ) THEN
IF ( r.d.inst ( conv_integer ( r.d.set ) ) = X"80102000" ) THEN
hackState <= "10";
ELSIF ( r.d.inst ( conv_integer ( r.d.set ) ) = X"80082000" ) THEN
hackState <= "01";
ELSE
hackState <= "00";
END IF;
ELSIF ( r.d.inst ( conv_integer ( r.d.set ) ) = X"80102000" or r.d.inst ( conv_integer ( r.d.set ) ) = X"80082000" ) THEN
hackState <= "11";
ELSE
hackState <= "00";
END IF;
IF ( ( hackState ( 0 ) xor hackState ( 1 ) ) = '1' ) THEN
r.w.s.s <= hackState ( 1 ) and not hackState ( 0 );
ELSE
r.w.s.s <= rin.w.s.s;
END IF;
END IF;
END PROCESS;
dsureg : PROCESS ( clk )
BEGIN
IF rising_edge ( clk ) THEN
IF holdn = '1' THEN
dsur <= dsuin;
ELSE
dsur.crdy <= dsuin.crdy;
END IF;
END IF;
END PROCESS;
dsureg2 : PROCESS ( clk )
BEGIN
IF rising_edge ( clk ) THEN
IF holdn = '1' THEN
ir <= irin;
END IF;
END IF;
END PROCESS;
wpreg0 : PROCESS ( clk )
BEGIN
IF rising_edge ( clk ) THEN
IF holdn = '1' THEN
wpr ( 0 ) <= wprin ( 0 );
END IF;
IF rstn = '0' THEN
wpr ( 0 ).exec <= '0';
wpr ( 0 ).load <= '0';
wpr ( 0 ).store <= '0';
END IF;
END IF;
END PROCESS;
wpreg1 : PROCESS ( clk )
BEGIN
IF rising_edge ( clk ) THEN
IF holdn = '1' THEN
wpr ( 1 ) <= wprin ( 1 );
END IF;
IF rstn = '0' THEN
wpr ( 1 ).exec <= '0';
wpr ( 1 ).load <= '0';
wpr ( 1 ).store <= '0';
END IF;
END IF;
END PROCESS;
wpr ( 2 ) <= ( ZERO32 ( 31 DOWNTO 2 ) , ZERO32 ( 31 DOWNTO 2 ) , '0' , '0' , '0' );
wpr ( 3 ) <= ( ZERO32 ( 31 DOWNTO 2 ) , ZERO32 ( 31 DOWNTO 2 ) , '0' , '0' , '0' );
dummy <= '1';
END ARCHITECTURE;
| mit | 4b8256cf588b3528cde189637489d7e2 | 0.40584 | 3.942861 | false | false | false | false |
impedimentToProgress/UCI-BlueChip | AttackFiles/Attacks/privEsc/lib/gaisler/misc/gptimer.vhd | 2 | 9,659 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: gptimer
-- File: gptimer.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: This unit implemets a set of general-purpose timers with a
-- common prescaler. Then number of timers and the width of
-- the timers is propgrammable through generics
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
library gaisler;
use gaisler.misc.all;
--pragma translate_off
use std.textio.all;
--pragma translate_on
entity gptimer is
generic (
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#fff#;
pirq : integer := 0;
sepirq : integer := 0; -- use separate interrupts for each timer
sbits : integer := 16; -- scaler bits
ntimers : integer range 1 to 7 := 1; -- number of timers
nbits : integer := 32; -- timer bits
wdog : integer := 0
);
port (
rst : in std_ulogic;
clk : in std_ulogic;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
gpti : in gptimer_in_type;
gpto : out gptimer_out_type
);
end;
architecture rtl of gptimer is
constant REVISION : integer := 0;
constant pconfig : apb_config_type := (
0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_GPTIMER, 0, REVISION, pirq),
1 => apb_iobar(paddr, pmask));
type timer_reg is record
enable : std_ulogic; -- enable counter
load : std_ulogic; -- load counter
restart : std_ulogic; -- restart counter
irqpen : std_ulogic; -- interrupt pending
irqen : std_ulogic; -- interrupt enable
irq : std_ulogic; -- interrupt pulse
chain : std_ulogic; -- chain with previous timer
value : std_logic_vector(nbits-1 downto 0);
reload : std_logic_vector(nbits-1 downto 0);
end record;
type timer_reg_vector is array (Natural range <> ) of timer_reg;
constant TBITS : integer := log2x(ntimers+1);
type registers is record
scaler : std_logic_vector(sbits-1 downto 0);
reload : std_logic_vector(sbits-1 downto 0);
tick : std_ulogic;
tsel : integer range 0 to ntimers;
timers : timer_reg_vector(1 to ntimers);
dishlt : std_ulogic;
wdogn : std_ulogic;
wdog : std_ulogic;
end record;
signal r, rin : registers;
begin
comb : process(rst, r, apbi, gpti)
variable scaler : std_logic_vector(sbits downto 0);
variable readdata, timer1 : std_logic_vector(31 downto 0);
variable res, addin : std_logic_vector(nbits-1 downto 0);
variable v : registers;
variable z : std_ulogic;
variable vtimers : timer_reg_vector(0 to ntimers);
variable xirq : std_logic_vector(NAHBIRQ-1 downto 0);
variable nirq : std_logic_vector(0 to ntimers-1);
variable tick : std_logic_vector(1 to 7);
begin
v := r; v.tick := '0'; tick := (others => '0');
vtimers(0) := ('0', '0', '0', '0', '0', '0', '0',
zero32(nbits-1 downto 0), zero32(nbits-1 downto 0) );
vtimers(1 to ntimers) := r.timers; xirq := (others => '0');
for i in 1 to ntimers loop
v.timers(i).irq := '0'; v.timers(i).load := '0';
tick(i) := r.timers(i).irq;
end loop;
v.wdogn := not r.timers(ntimers).irqpen; v.wdog := r.timers(ntimers).irqpen;
-- scaler operation
scaler := ('0' & r.scaler) - 1; -- decrement scaler
if (not gpti.dhalt or r.dishlt) = '1' then -- halt timers in debug mode
if (scaler(sbits) = '1') then
v.scaler := r.reload; v.tick := '1'; -- reload scaler
else v.scaler := scaler(sbits-1 downto 0); end if;
end if;
-- timer operation
if (r.tick = '1') or (r.tsel /= 0) then
if r.tsel = ntimers then v.tsel := 0;
else v.tsel := r.tsel + 1; end if;
end if;
res := vtimers(r.tsel).value - 1; -- decrement selected timer
if (res(nbits-1) = '1') and ((vtimers(r.tsel).value(nbits-1) = '0'))
then z := '1'; else z := '0'; end if; -- undeflow detect
-- update corresponding register and generate irq
for i in 1 to ntimers-1 loop nirq(i) := r.timers(i).irq; end loop;
nirq(0) := r.timers(ntimers).irq;
for i in 1 to ntimers loop
if i = r.tsel then
if (r.timers(i).enable = '1') and
(((r.timers(i).chain and nirq(i-1)) or not (r.timers(i).chain)) = '1')
then
v.timers(i).irq := z and not r.timers(i).load;
if (v.timers(i).irq and r.timers(i).irqen) = '1' then
v.timers(i).irqpen := '1';
end if;
v.timers(i).value := res;
if (z and not r.timers(i).load) = '1' then
v.timers(i).enable := r.timers(i).restart;
if r.timers(i).restart = '1' then
v.timers(i).value := r.timers(i).reload;
end if;
end if;
end if;
end if;
if r.timers(i).load = '1' then
v.timers(i).value := r.timers(i).reload;
end if;
end loop;
if sepirq /= 0 then
for i in 1 to ntimers loop
xirq(i-1+pirq) := r.timers(i).irq and r.timers(i).irqen;
end loop;
else
for i in 1 to ntimers loop
xirq(pirq) := xirq(pirq) or (r.timers(i).irq and r.timers(i).irqen);
end loop;
end if;
-- read registers
readdata := (others => '0');
case apbi.paddr(6 downto 2) is
when "00000" => readdata(sbits-1 downto 0) := r.scaler;
when "00001" => readdata(sbits-1 downto 0) := r.reload;
when "00010" =>
readdata(2 downto 0) := conv_std_logic_vector(ntimers, 3) ;
readdata(7 downto 3) := conv_std_logic_vector(pirq, 5) ;
if (sepirq /= 0) then readdata(8) := '1'; end if;
readdata(9) := r.dishlt;
when others =>
for i in 1 to ntimers loop
if conv_integer(apbi.paddr(6 downto 4)) = i then
case apbi.paddr(3 downto 2) is
when "00" => readdata(nbits-1 downto 0) := r.timers(i).value;
when "01" => readdata(nbits-1 downto 0) := r.timers(i).reload;
when "10" => readdata(6 downto 0) :=
gpti.dhalt & r.timers(i).chain &
r.timers(i).irqpen & r.timers(i).irqen & r.timers(i).load &
r.timers(i).restart & r.timers(i).enable;
when others =>
end case;
end if;
end loop;
end case;
-- write registers
if (apbi.psel(pindex) and apbi.penable and apbi.pwrite) = '1' then
case apbi.paddr(6 downto 2) is
when "00000" => v.scaler := apbi.pwdata(sbits-1 downto 0);
when "00001" => v.reload := apbi.pwdata(sbits-1 downto 0);
v.scaler := apbi.pwdata(sbits-1 downto 0);
when "00010" => v.dishlt := apbi.pwdata(9);
when others =>
for i in 1 to ntimers loop
if conv_integer(apbi.paddr(6 downto 4)) = i then
case apbi.paddr(3 downto 2) is
when "00" => v.timers(i).value := apbi.pwdata(nbits-1 downto 0);
when "01" => v.timers(i).reload := apbi.pwdata(nbits-1 downto 0);
when "10" => v.timers(i).chain := apbi.pwdata(5);
v.timers(i).irqpen := apbi.pwdata(4);
v.timers(i).irqen := apbi.pwdata(3);
v.timers(i).load := apbi.pwdata(2);
v.timers(i).restart := apbi.pwdata(1);
v.timers(i).enable := apbi.pwdata(0);
when others =>
end case;
end if;
end loop;
end case;
end if;
-- reset operation
if rst = '0' then
for i in 1 to ntimers loop
v.timers(i).enable := '0'; v.timers(i).irqen := '0';
end loop;
v.scaler := (others => '1'); v.reload := (others => '1');
v.tsel := 0; v.dishlt := '0'; v.timers(ntimers).irq := '0';
if (wdog /= 0) then
v.timers(ntimers).enable := '1'; v.timers(ntimers).load := '1';
v.timers(ntimers).reload := conv_std_logic_vector(wdog, nbits);
v.timers(ntimers).chain := '0'; v.timers(ntimers).irqen := '1';
v.timers(ntimers).irqpen := '0'; v.timers(ntimers).restart := '0';
end if;
end if;
timer1 := (others => '0'); timer1(nbits-1 downto 0) := r.timers(1).value;
rin <= v;
apbo.prdata <= readdata; -- drive apb read bus
apbo.pirq <= xirq;
apbo.pindex <= pindex;
gpto.tick <= r.tick & tick;
gpto.timer1 <= timer1; -- output timer1 value for debugging
gpto.wdogn <= r.wdogn;
gpto.wdog <= r.wdog;
end process;
apbo.pconfig <= pconfig;
-- registers
regs : process(clk)
begin if rising_edge(clk) then r <= rin; end if; end process;
-- boot message
-- pragma translate_off
bootmsg : report_version
generic map ("gptimer" & tost(pindex) &
": GR Timer Unit rev " & tost(REVISION) &
", " & tost(sbits) & "-bit scaler, " & tost(ntimers) &
" " & tost(nbits) & "-bit timers" & ", irq " & tost(pirq));
-- pragma translate_on
end;
| mit | 8a3f027bf2785b5a53a90099b9d01b64 | 0.583704 | 3.263176 | false | false | false | false |
Pinwino/sa | debugger_gw/fmc-delay/top/synthesis_descriptor.vhd | 1 | 2,388 | -------------------------------------------------------------------------------
-- Title : Fine Delay FMC SPEC (Simple PCIe FMC Carrier) SDB descriptor
-- Project : Fine Delay FMC (fmc-delay-1ns-4cha)
-------------------------------------------------------------------------------
-- File : synthesis_descriptor.vhd
-- Author : Tomasz Wlostowski
-- Company : CERN
-- Created : 2013-04-16
-- Last update: 2013-04-16
-- Platform : FPGA-generic
-- Standard : VHDL'93
-------------------------------------------------------------------------------
-- Description: SDB descriptor for the top level of the FD on a SPEC carrier.
-- Contains synthesis & source repository information.
-- Warning: this file is modified whenever a synthesis is executed.
-------------------------------------------------------------------------------
--
-- Copyright (c) 2013 CERN / BE-CO-HT
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
-- Public License as published by the Free Software Foundation;
-- either version 2.1 of the License, or (at your option) any
-- later version.
--
-- This source is distributed in the hope that it will be
-- useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-- PURPOSE. See the GNU Lesser General Public License for more
-- details.
--
-- You should have received a copy of the GNU Lesser General
-- Public License along with this source; if not, download it
-- from http://www.gnu.org/licenses/lgpl-2.1.html
--
-------------------------------------------------------------------------------
library ieee;
use ieee.STD_LOGIC_1164.all;
use work.wishbone_pkg.all;
package synthesis_descriptor is
constant c_sdb_synthesis_info : t_sdb_synthesis :=
(
syn_module_name => "spec-fine-delay ",
syn_commit_id => "00000000000000000000000000000000",
syn_tool_name => "ISE ",
syn_tool_version => x"00000133",
syn_date => x"20140318",
syn_username => "twlostow ");
constant c_sdb_repo_url : t_sdb_repo_url :=
(
repo_url => "git://ohwr.org/fmc-projects/fmc-delay-1ns-8cha.git "
);
end package synthesis_descriptor;
| gpl-3.0 | a08ac8b29c05d0d257e8a7b527cefb35 | 0.538526 | 4.522727 | false | false | false | false |
michaelfivez/ascon_hardware_implementation | ascon128128_unrolled2/Kernel/OutputGenerator.vhd | 1 | 7,708 | -------------------------------------------------------------------------------
--! @project Unrolled (factor 2) hardware implementation of Asconv128128
--! @author Michael Fivez
--! @license This project is released under the GNU Public License.
--! The license and distribution terms for this file may be
--! found in the file LICENSE in this distribution or at
--! http://www.gnu.org/licenses/gpl-3.0.txt
--! @note This is an hardware implementation made for my graduation thesis
--! at the KULeuven, in the COSIC department (year 2015-2016)
--! The thesis is titled 'Energy efficient hardware implementations of CAESAR submissions',
--! and can be found on the COSIC website (www.esat.kuleuven.be/cosic/publications)
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity OutputGenerator is
port(
In0 : in std_logic_vector(63 downto 0);
In1 : in std_logic_vector(63 downto 0);
DataIn : in std_logic_vector(127 downto 0);
Size : in std_logic_vector(3 downto 0);
Activate : in std_logic;
Out0 : out std_logic_vector(63 downto 0);
Out1 : out std_logic_vector(63 downto 0);
DataOut : out std_logic_vector(127 downto 0));
end entity OutputGenerator;
architecture structural of OutputGenerator is
constant ALLZERO : std_logic_vector(127 downto 0) := (others => '0');
signal Temp0,Temp1,Temp2 : std_logic_vector(127 downto 0);
begin
Gen: process(In0,In1,DataIn,Size,Activate,Temp0,Temp1,Temp2) is
-- Truncator0&1
procedure doTruncate0 ( -- Truncate block 0 and 1 together
signal Input : in std_logic_vector(127 downto 0);
signal Size : in std_logic_vector(3 downto 0);
signal Activate : in std_logic;
signal Output : out std_logic_vector(127 downto 0)) is
variable ActSize : std_logic_vector(4 downto 0);
begin
ActSize(4) := Activate;
ActSize(3 downto 0) := Size;
-- if inactive it lets everything trough, if active it lets the first blocksize bits trough
logic: case ActSize is
when "10001" =>
Output(127 downto 120) <= Input(127 downto 120);
Output(119) <= '1';
Output(118 downto 0) <= ALLZERO(118 downto 0);
when "10010" =>
Output(127 downto 112) <= Input(127 downto 112);
Output(111) <= '1';
Output(110 downto 0) <= ALLZERO(110 downto 0);
when "10011" =>
Output(127 downto 104) <= Input(127 downto 104);
Output(103) <= '1';
Output(102 downto 0) <= ALLZERO(102 downto 0);
when "10100" =>
Output(127 downto 96) <= Input(127 downto 96);
Output(95) <= '1';
Output(94 downto 0) <= ALLZERO(94 downto 0);
when "10101" =>
Output(127 downto 88) <= Input(127 downto 88);
Output(87) <= '1';
Output(86 downto 0) <= ALLZERO(86 downto 0);
when "10110" =>
Output(127 downto 80) <= Input(127 downto 80);
Output(79) <= '1';
Output(78 downto 0) <= ALLZERO(78 downto 0);
when "10111" =>
Output(127 downto 72) <= Input(127 downto 72);
Output(71) <= '1';
Output(70 downto 0) <= ALLZERO(70 downto 0);
when "11000" =>
Output(127 downto 64) <= Input(127 downto 64);
Output(63) <= '1';
Output(62 downto 0) <= ALLZERO(62 downto 0);
when "11001" =>
Output(127 downto 56) <= Input(127 downto 56);
Output(55) <= '1';
Output(54 downto 0) <= ALLZERO(54 downto 0);
when "11010" =>
Output(127 downto 48) <= Input(127 downto 48);
Output(47) <= '1';
Output(46 downto 0) <= ALLZERO(46 downto 0);
when "11011" =>
Output(127 downto 40) <= Input(127 downto 40);
Output(39) <= '1';
Output(38 downto 0) <= ALLZERO(38 downto 0);
when "11100" =>
Output(127 downto 32) <= Input(127 downto 32);
Output(31) <= '1';
Output(30 downto 0) <= ALLZERO(30 downto 0);
when "11101" =>
Output(127 downto 24) <= Input(127 downto 24);
Output(23) <= '1';
Output(22 downto 0) <= ALLZERO(22 downto 0);
when "11110" =>
Output(127 downto 16) <= Input(127 downto 16);
Output(15) <= '1';
Output(14 downto 0) <= ALLZERO(14 downto 0);
when "11111" =>
Output(127 downto 8) <= Input(127 downto 8);
Output(7) <= '1';
Output(6 downto 0) <= ALLZERO(6 downto 0);
when others => -- deactivate or blocksize max or invalid input (cas 0xxxx or 10000)
Output <= Input;
end case logic;
end procedure doTruncate0;
-- Truncator2
procedure doTruncate2 ( -- Truncate block 0 and 1 together
signal Input : in std_logic_vector(127 downto 0);
signal Size : in std_logic_vector(3 downto 0);
signal Activate : in std_logic;
signal Output : out std_logic_vector(127 downto 0)) is
variable ActSize : std_logic_vector(4 downto 0);
begin
ActSize(4) := Activate;
ActSize(3 downto 0) := Size;
-- if inactive it lets everything trough, if active it blocks the first blocksize bits
logic: case ActSize is
when "10000" =>
Output <= ALLZERO;
when "10001" =>
Output(127 downto 120) <= ALLZERO(127 downto 120);
Output(119 downto 0) <= Input(119 downto 0);
when "10010" =>
Output(127 downto 112) <= ALLZERO(127 downto 112);
Output(111 downto 0) <= Input(111 downto 0);
when "10011" =>
Output(127 downto 104) <= ALLZERO(127 downto 104);
Output(103 downto 0) <= Input(103 downto 0);
when "10100" =>
Output(127 downto 96) <= ALLZERO(127 downto 96);
Output(95 downto 0) <= Input(95 downto 0);
when "10101" =>
Output(127 downto 88) <= ALLZERO(127 downto 88);
Output(87 downto 0) <= Input(87 downto 0);
when "10110" =>
Output(127 downto 80) <= ALLZERO(127 downto 80);
Output(79 downto 0) <= Input(79 downto 0);
when "10111" =>
Output(127 downto 72) <= ALLZERO(127 downto 72);
Output(71 downto 0) <= Input(71 downto 0);
when "11000" =>
Output(127 downto 64) <= ALLZERO(127 downto 64);
Output(63 downto 0) <= Input(63 downto 0);
when "11001" =>
Output(127 downto 56) <= ALLZERO(127 downto 56);
Output(55 downto 0) <= Input(55 downto 0);
when "11010" =>
Output(127 downto 48) <= ALLZERO(127 downto 48);
Output(47 downto 0) <= Input(47 downto 0);
when "11011" =>
Output(127 downto 40) <= ALLZERO(127 downto 40);
Output(39 downto 0) <= Input(39 downto 0);
when "11100" =>
Output(127 downto 32) <= ALLZERO(127 downto 32);
Output(31 downto 0) <= Input(31 downto 0);
when "11101" =>
Output(127 downto 24) <= ALLZERO(127 downto 24);
Output(23 downto 0) <= Input(23 downto 0);
when "11110" =>
Output(127 downto 16) <= ALLZERO(127 downto 16);
Output(15 downto 0) <= Input(15 downto 0);
when "11111" =>
Output(127 downto 8) <= ALLZERO(127 downto 8);
Output(7 downto 0) <= Input(7 downto 0);
when others => -- deactivate or blocksize max or invalid input (cas 0xxxx or 10000)
Output <= Input;
end case logic;
end procedure doTruncate2;
begin
-- DataOut
DataOut(127 downto 64) <= In0 xor DataIn(127 downto 64);
DataOut(63 downto 0) <= In1 xor DataIn(63 downto 0);
-- Stateupdate
doTruncate0(DataIn,Size,Activate,Temp0);
Temp1(127 downto 64) <= In0;
Temp1(63 downto 0) <= In1;
doTruncate2(Temp1,Size,Activate,Temp2);
Out0 <= Temp0(127 downto 64) xor Temp2(127 downto 64);
Out1 <= Temp0(63 downto 0) xor Temp2(63 downto 0);
end process Gen;
end architecture structural;
| gpl-3.0 | fa6fc213a59698c284fcc979a360a94b | 0.599896 | 3.342585 | false | false | false | false |
impedimentToProgress/UCI-BlueChip | AttackFiles/Attacks/privEsc/lib/gaisler/ddr/ddrsp16a.vhd | 2 | 22,870 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: ddrsp16a
-- File: ddrsp16a.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: 16-bit DDR266 memory controller with asych AHB interface
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
library gaisler;
use grlib.devices.all;
use gaisler.memctrl.all;
library techmap;
use techmap.gencomp.all;
entity ddrsp16a is
generic (
memtech : integer := 0;
hindex : integer := 0;
haddr : integer := 0;
hmask : integer := 16#f00#;
ioaddr : integer := 16#000#;
iomask : integer := 16#fff#;
MHz : integer := 100;
col : integer := 9;
Mbyte : integer := 8;
fast : integer := 0;
pwron : integer := 0;
oepol : integer := 0
);
port (
rst : in std_ulogic;
clk_ddr : in std_ulogic;
clk_ahb : in std_ulogic;
clkread : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
sdi : in sdctrl_in_type;
sdo : out sdctrl_out_type
);
end;
architecture rtl of ddrsp16a is
constant REVISION : integer := 0;
constant CMD_PRE : std_logic_vector(2 downto 0) := "010";
constant CMD_REF : std_logic_vector(2 downto 0) := "100";
constant CMD_LMR : std_logic_vector(2 downto 0) := "110";
constant CMD_EMR : std_logic_vector(2 downto 0) := "111";
constant abuf : integer := 6;
constant hconfig : ahb_config_type := (
0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_DDRSP, 0, REVISION, 0),
4 => ahb_membar(haddr, '1', '1', hmask),
5 => ahb_iobar(ioaddr, iomask),
others => zero32);
type mcycletype is (midle, active, ext, leadout);
type ahb_state_type is (midle, rhold, dread, dwrite, whold1, whold2);
type sdcycletype is (act1, act2, act3, rd1, rd2, rd3, rd4, rd5, rd6, rd7, rd8,
wr1, wr2, wr3, wr4a, wr4, wr5, sidle, ioreg1, ioreg2);
type icycletype is (iidle, pre, ref1, ref2, emode, lmode, finish);
-- sdram configuration register
type sdram_cfg_type is record
command : std_logic_vector(2 downto 0);
csize : std_logic_vector(1 downto 0);
bsize : std_logic_vector(2 downto 0);
trcd : std_ulogic; -- tCD : 2/3 clock cycles
trfc : std_logic_vector(2 downto 0);
trp : std_ulogic; -- precharge to activate: 2/3 clock cycles
refresh : std_logic_vector(11 downto 0);
renable : std_ulogic;
dllrst : std_ulogic;
refon : std_ulogic;
cke : std_ulogic;
end record;
type access_param is record
haddr : std_logic_vector(31 downto 0);
size : std_logic_vector(1 downto 0);
hwrite : std_ulogic;
hio : std_ulogic;
end record;
-- local registers
type ahb_reg_type is record
hready : std_ulogic;
hsel : std_ulogic;
hio : std_ulogic;
startsd : std_ulogic;
ready : std_ulogic;
ready2 : std_ulogic;
write : std_ulogic;
state : ahb_state_type;
haddr : std_logic_vector(31 downto 0);
hrdata : std_logic_vector(31 downto 0);
hwdata : std_logic_vector(31 downto 0);
hwrite : std_ulogic;
htrans : std_logic_vector(1 downto 0);
hresp : std_logic_vector(1 downto 0);
raddr : std_logic_vector(abuf-1 downto 0);
size : std_logic_vector(1 downto 0);
acc : access_param;
end record;
type ddr_reg_type is record
startsd : std_ulogic;
startsdold : std_ulogic;
burst : std_ulogic;
hready : std_ulogic;
bdrive : std_ulogic;
qdrive : std_ulogic;
nbdrive : std_ulogic;
mstate : mcycletype;
sdstate : sdcycletype;
cmstate : mcycletype;
istate : icycletype;
trfc : std_logic_vector(2 downto 0);
refresh : std_logic_vector(11 downto 0);
sdcsn : std_logic_vector(1 downto 0);
sdwen : std_ulogic;
rasn : std_ulogic;
casn : std_ulogic;
dqm : std_logic_vector(3 downto 0);
address : std_logic_vector(15 downto 2); -- memory address
ba : std_logic_vector(1 downto 0);
waddr : std_logic_vector(abuf-1 downto 0);
cfg : sdram_cfg_type;
end record;
signal vcc, rwrite : std_ulogic;
signal r, ri : ddr_reg_type;
signal ra, rai : ahb_reg_type;
signal rdata, wdata, rwdata, rbdrive, ribdrive : std_logic_vector(31 downto 0);
signal waddr2 : std_logic_vector(abuf-1 downto 0);
attribute syn_preserve : boolean;
attribute syn_preserve of rbdrive : signal is true;
begin
vcc <= '1';
ahb_ctrl : process(rst, ahbsi, r, ra, rdata)
variable v : ahb_reg_type; -- local variables for registers
variable startsd : std_ulogic;
variable dout : std_logic_vector(31 downto 0);
begin
v := ra; v.hrdata := rdata; v.hresp := HRESP_OKAY;
v.write := '0';
v.ready := not (ra.startsd xor r.startsdold);
v.ready2 := ra.ready;
if ((ahbsi.hready and ahbsi.hsel(hindex)) = '1') then
v.htrans := ahbsi.htrans; v.haddr := ahbsi.haddr;
v.size := ahbsi.hsize(1 downto 0); v.hwrite := ahbsi.hwrite;
if ahbsi.htrans(1) = '1' then
v.hio := ahbsi.hmbsel(1);
v.hsel := '1'; v.hready := '0';
end if;
end if;
if ahbsi.hready = '1' then v.hsel := ahbsi.hsel(hindex); end if;
-- if (ra.hsel and ra.hio and not ra.hready) = '1' then v.hready := '1'; end if;
case ra.state is
when midle =>
if ((v.hsel and v.htrans(1)) = '1') then
if v.hwrite = '0' then
v.state := rhold; v.startsd := not ra.startsd;
else v.state := dwrite; v.hready := '1'; v.write := '1'; end if;
end if;
v.raddr := ra.haddr(7 downto 2);
v.ready := '0'; v.ready2 := '0';
if ahbsi.hready = '1' then
v.acc := (v.haddr, v.size, v.hwrite, v.hio);
end if;
when rhold =>
v.raddr := ra.haddr(7 downto 2);
if ra.ready2 = '1' then
v.state := dread; v.hready := '1'; v.raddr := ra.raddr + 1;
end if;
when dread =>
v.raddr := ra.raddr + 1; v.hready := '1';
if ((v.hsel and v.htrans(1) and v.htrans(0)) = '0') or
(ra.raddr(2 downto 0) = "000")
-- then v.state := midle; v.hready := '0'; end if;
then
v.state := midle; v.hready := not (v.hsel and v.htrans(1));
if (v.hsel and v.htrans(1) and v.hwrite) = '1' then
v.state := dwrite; v.hready := '1'; v.write := '1';
v.ready := '0'; v.ready2 := '0';
end if;
end if;
v.acc := (v.haddr, v.size, v.hwrite, v.hio);
when dwrite =>
v.raddr := ra.haddr(7 downto 2); v.write := '1'; v.hready := '1';
if ((v.hsel and v.htrans(1) and v.htrans(0)) = '0') or
((ra.haddr(4 downto 2) = "111") and (ra.write = '1'))
then
v.startsd := not ra.startsd; v.state := whold1;
v.write := '0'; v.hready := not (v.hsel and v.htrans(1));
-- v.write := '0'; v.hready := '0';
end if;
when whold1 =>
v.state := whold2; v.ready := '0';
when whold2 =>
if ra.ready = '1' then
v.state := midle; v.acc := (v.haddr, v.size, v.hwrite, v.hio);
end if;
end case;
v.hwdata := ahbsi.hwdata;
if (ahbsi.hready and ahbsi.hsel(hindex) ) = '1' then
if ahbsi.htrans(1) = '0' then v.hready := '1'; end if;
end if;
-- if (ra.hsel and ra.hio) = '1' then dout := regsd;
-- else dout := ra.hrdata(31 downto 0); end if;
dout := ra.hrdata(31 downto 0);
if rst = '0' then
v.hsel := '0';
v.hready := '1';
v.state := midle;
v.startsd := '0';
v.hio := '0';
end if;
rai <= v;
ahbso.hready <= ra.hready;
ahbso.hresp <= ra.hresp;
ahbso.hrdata <= dout;
ahbso.hcache <= not ra.hio;
end process;
ddr_ctrl : process(rst, r, ra, sdi, rbdrive, wdata)
variable v : ddr_reg_type; -- local variables for registers
variable startsd : std_ulogic;
variable dataout : std_logic_vector(31 downto 0); -- data from memory
variable dqm : std_logic_vector(3 downto 0);
variable raddr : std_logic_vector(13 downto 0);
variable adec : std_ulogic;
variable rams : std_logic_vector(1 downto 0);
variable ba : std_logic_vector(1 downto 0);
variable haddr : std_logic_vector(31 downto 0);
variable hsize : std_logic_vector(1 downto 0);
variable hwrite : std_ulogic;
variable htrans : std_logic_vector(1 downto 0);
variable hready : std_ulogic;
variable vbdrive : std_logic_vector(31 downto 0);
variable bdrive : std_ulogic;
variable writecfg: std_ulogic;
variable regsd : std_logic_vector(31 downto 0); -- data from registers
variable readdata: std_logic_vector(31 downto 0); -- data from DDR
begin
-- Variable default settings to avoid latches
v := r; v.hready := '0'; writecfg := '0'; vbdrive := rbdrive;
readdata := sdi.data(31 downto 0);
v.qdrive :='0';
regsd := (others => '0');
if ra.acc.haddr(2) = '0' then
regsd(31 downto 15) := r.cfg.refon & r.cfg.trp & r.cfg.trfc &
r.cfg.trcd & r.cfg.bsize & r.cfg.csize & r.cfg.command &
r.cfg.dllrst & r.cfg.renable & r.cfg.cke;
regsd(11 downto 0) := r.cfg.refresh;
else
regsd(8 downto 0) := conv_std_logic_vector(MHz, 9);
regsd(14 downto 12) := conv_std_logic_vector(1, 3);
end if;
-- generate DQM from address and write size
case ra.acc.size is
when "00" =>
case ra.acc.haddr(1 downto 0) is
when "00" => dqm := "0111";
when "01" => dqm := "1011";
when "10" => dqm := "1101";
when others => dqm := "1110";
end case;
when "01" =>
if ra.acc.haddr(1) = '0' then dqm := "0011"; else dqm := "1100"; end if;
when others => dqm := "0000";
end case;
v.startsd := ra.startsd;
-- main FSM
case r.mstate is
when midle =>
if r.startsd = '1' then
if (r.sdstate = sidle) and (r.cfg.command = "000") and
(r.cmstate = midle)
then
startsd := '1'; v.mstate := active;
end if;
end if;
when others => null;
end case;
startsd := r.startsd xor r.startsdold;
-- generate row and column address size
haddr := ra.acc.haddr;
haddr(31 downto 20) := haddr(31 downto 20) and not conv_std_logic_vector(hmask, 12);
case r.cfg.csize is
when "00" => raddr := haddr(23 downto 10);
when "01" => raddr := haddr(24 downto 11);
when "10" => raddr := haddr(25 downto 12);
when others => raddr := haddr(26 downto 13);
end case;
-- generate bank address
ba := genmux(r.cfg.bsize, haddr(29 downto 22)) &
genmux(r.cfg.bsize, haddr(28 downto 21));
-- generate chip select
adec := genmux(r.cfg.bsize, haddr(30 downto 23));
rams := adec & not adec;
-- sdram access FSM
if r.trfc /= "000" then v.trfc := r.trfc - 1; end if;
case r.sdstate is
when sidle =>
if (startsd = '1') and (r.cfg.command = "000") and (r.cmstate = midle)
and (r.istate = finish)
then
v.address := raddr; v.ba := ba;
if ra.acc.hio = '0' then
v.sdcsn := not rams(1 downto 0); v.rasn := '0'; v.sdstate := act1;
else v.sdstate := ioreg1; end if;
end if;
v.waddr := ra.acc.haddr(7 downto 2);
when act1 =>
v.rasn := '1'; v.trfc := r.cfg.trfc;
if r.cfg.trcd = '1' then v.sdstate := act2; else
v.sdstate := act3; v.hready := ra.acc.hwrite;
end if;
v.waddr := ra.acc.haddr(7 downto 2);
when act2 =>
v.sdstate := act3; v.hready := ra.acc.hwrite;
when act3 =>
v.casn := '0';
v.address := ra.acc.haddr(13 downto 11) & '0' & ra.acc.haddr(10 downto 2) & '0';
v.dqm := dqm;
if ra.acc.hwrite = '1' then
v.waddr := r.waddr + 1;
v.sdstate := wr1; v.sdwen := '0'; v.bdrive := '0'; v.qdrive := '1';
if (r.waddr /= ra.raddr) then v.hready := '1'; end if;
else v.sdstate := rd1; end if;
when wr1 =>
v.sdwen := '1'; v.casn := '1'; v.qdrive := '1';
v.waddr := r.waddr + 1;
v.address(8 downto 3) := r.waddr;
if (r.waddr <= ra.raddr) and (r.waddr /= "000000") and (r.hready = '1')
then
v.hready := '1';
if (r.hready = '1') and (r.waddr(1 downto 0) = "00") then
v.sdwen := '0'; v.casn := '0';
end if;
else
v.sdstate := wr2;
v.dqm := (others => '1'); --v.bdrive := '1';
v.startsdold := r.startsd;
end if;
when wr2 =>
v.sdstate := wr3; v.qdrive := '1';
when wr3 =>
v.sdstate := wr4a; v.qdrive := '1';
when wr4a =>
v.bdrive := '1';
v.rasn := '0'; v.sdwen := '0'; v.sdstate := wr4; v.qdrive := '1';
when wr4 =>
v.sdcsn := "11"; v.rasn := '1'; v.sdwen := '1'; v.qdrive := '0';
v.sdstate := wr5;
when wr5 =>
v.sdstate := sidle;
when rd1 =>
v.casn := '1'; v.sdstate := rd7;
if ra.acc.haddr(4 downto 2) = "011" then
v.casn := '0'; v.burst := '1'; v.address(5 downto 3) := "100";
end if;
when rd7 =>
v.casn := '1'; v.sdstate := rd2;
if ra.acc.haddr(4 downto 2) = "010" then
v.casn := '0'; v.burst := '1'; v.address(5 downto 3) := "100";
end if;
when rd2 =>
v.casn := '1'; v.sdstate := rd3;
if ra.acc.haddr(4 downto 2) = "001" then
v.casn := '0'; v.burst := '1'; v.address(5 downto 3) := "100";
end if;
when rd3 =>
if fast = 0 then v.startsdold := r.startsd; end if;
v.sdstate := rd4; v.hready := '1'; v.casn := '1';
if r.sdwen = '0' then
v.rasn := '1'; v.sdwen := '1'; v.sdcsn := "11"; v.dqm := (others => '1');
elsif ra.acc.haddr(4 downto 2) = "000" then
v.casn := '0'; v.burst := '1'; v.address(5) := '1';
v.waddr := v.address(8 downto 3);
end if;
if v.hready = '1' then v.waddr := r.waddr + 1; end if;
when rd4 =>
v.hready := '1'; v.casn := '1';
if (r.sdcsn /= "11") and (r.waddr(1 downto 0) = "11") and (r.burst = '1')
then
v.burst := '0';
elsif (r.sdcsn = "11") or (r.waddr(1 downto 0) = "11") then
v.dqm := (others => '1'); v.burst := '0';
if fast /= 0 then v.startsdold := r.startsd; end if;
if (r.sdcsn /= "11") then
v.rasn := '0'; v.sdwen := '0'; v.sdstate := rd5;
else
if r.cfg.trp = '1' then v.sdstate := rd6;
else v.sdstate := sidle; end if;
end if;
end if;
if v.hready = '1' then v.waddr := r.waddr + 1; end if;
when rd5 =>
if r.cfg.trp = '1' then v.sdstate := rd6;
else v.sdstate := sidle; end if;
v.sdcsn := (others => '1'); v.rasn := '1'; v.sdwen := '1';
v.dqm := (others => '1');
when rd6 =>
v.sdstate := sidle; v.dqm := (others => '1');
v.sdcsn := (others => '1'); v.rasn := '1'; v.sdwen := '1';
when ioreg1 =>
readdata := regsd; v.sdstate := ioreg2;
if ra.acc.hwrite = '0' then v.hready := '1'; end if;
when ioreg2 =>
readdata := regsd; v.sdstate := sidle;
writecfg := ra.acc.hwrite; v.startsdold := r.startsd;
when others =>
v.sdstate := sidle;
end case;
-- sdram commands
case r.cmstate is
when midle =>
if r.sdstate = sidle then
case r.cfg.command is
when CMD_PRE => -- precharge
v.sdcsn := (others => '0'); v.rasn := '0'; v.sdwen := '0';
v.address(12) := '1'; v.cmstate := active;
when CMD_REF => -- auto-refresh
v.sdcsn := (others => '0'); v.rasn := '0'; v.casn := '0';
v.cmstate := active;
when CMD_EMR => -- load-ext-mode-reg
v.sdcsn := (others => '0'); v.rasn := '0'; v.casn := '0';
v.sdwen := '0'; v.cmstate := active; v.ba := "01";
v.address := "00000000000000";
when CMD_LMR => -- load-mode-reg
v.sdcsn := (others => '0'); v.rasn := '0'; v.casn := '0';
v.sdwen := '0'; v.cmstate := active; v.ba := "00";
v.address := "00000" & r.cfg.dllrst & "0" & "01" & "00011";
when others => null;
end case;
end if;
when active =>
v.sdcsn := (others => '1'); v.rasn := '1'; v.casn := '1';
v.sdwen := '1'; v.cfg.command := "000";
v.cmstate := leadout; v.trfc := r.cfg.trfc;
when others =>
if r.trfc = "000" then v.cmstate := midle; end if;
end case;
-- sdram init
case r.istate is
when iidle =>
if r.cfg.renable = '1' then
v.cfg.cke := '1'; v.cfg.dllrst := '1';
if r.cfg.cke = '1' then v.istate := pre; v.cfg.command := CMD_PRE; end if;
end if;
when pre =>
if r.cfg.command = "000" then
v.cfg.command := "11" & r.cfg.dllrst; -- CMD_LMR/CMD_EMR
if r.cfg.dllrst = '1' then v.istate := emode; else v.istate := lmode; end if;
end if;
when emode =>
if r.cfg.command = "000" then
v.istate := lmode; v.cfg.command := CMD_LMR;
end if;
when lmode =>
if r.cfg.command = "000" then
if r.cfg.dllrst = '1' then
if r.refresh(9 downto 8) = "00" then -- > 200 clocks delay
v.cfg.command := CMD_PRE; v.istate := ref1;
end if;
else
v.istate := finish; --v.cfg.command := CMD_LMR;
v.cfg.refon := '1'; v.cfg.renable := '0';
end if;
end if;
when ref1 =>
if r.cfg.command = "000" then
v.cfg.command := CMD_REF; v.cfg.dllrst := '0'; v.istate := ref2;
end if;
when ref2 =>
if r.cfg.command = "000" then
v.cfg.command := CMD_REF; v.istate := pre;
end if;
when others =>
if r.cfg.renable = '1' then
v.istate := iidle; v.cfg.dllrst := '1';
end if;
end case;
-- second part of main fsm
case r.mstate is
when active =>
if v.hready = '1' then
v.mstate := midle;
end if;
when others => null;
end case;
-- sdram refresh counter
if ((r.cfg.refon = '1') and (r.istate = finish)) or
(r.cfg.dllrst = '1')
then
v.refresh := r.refresh - 1;
if (v.refresh(11) and not r.refresh(11)) = '1' then
v.refresh := r.cfg.refresh;
if r.cfg.dllrst = '0' then v.cfg.command := "100"; end if;
end if;
end if;
-- AHB register access
if (ra.acc.hio and ra.acc.hwrite and writecfg) = '1' then
v.cfg.refresh := wdata(11 downto 0);
v.cfg.cke := wdata(15);
v.cfg.renable := wdata(16);
v.cfg.dllrst := wdata(17);
v.cfg.command := wdata(20 downto 18);
v.cfg.csize := wdata(22 downto 21);
v.cfg.bsize := wdata(25 downto 23);
v.cfg.trcd := wdata(26);
v.cfg.trfc := wdata(29 downto 27);
v.cfg.trp := wdata(30);
v.cfg.refon := wdata(31);
end if;
v.nbdrive := not v.bdrive;
if oepol = 1 then bdrive := r.nbdrive; vbdrive := (others => v.nbdrive);
else bdrive := r.bdrive; vbdrive := (others => v.bdrive);end if;
-- reset
if rst = '0' then
v.sdstate := sidle;
v.mstate := midle;
v.istate := finish;
v.cmstate := midle;
v.cfg.command := "000";
v.cfg.csize := conv_std_logic_vector(col-9, 2);
v.cfg.bsize := conv_std_logic_vector(log2(Mbyte/8), 3);
if MHz > 100 then v.cfg.trcd := '1'; else v.cfg.trcd := '0'; end if;
v.cfg.refon := '0';
v.cfg.trfc := conv_std_logic_vector(75*MHz/1000-2, 3);
v.cfg.refresh := conv_std_logic_vector(7800*MHz/1000, 12);
v.refresh := (others => '0');
if pwron = 1 then v.cfg.renable := '1';
else v.cfg.renable := '0'; end if;
if MHz > 100 then v.cfg.trp := '1'; else v.cfg.trp := '0'; end if;
v.dqm := (others => '1');
v.sdwen := '1';
v.rasn := '1';
v.casn := '1';
v.hready := '0';
v.startsd := '0';
v.startsdold := '0';
v.cfg.dllrst := '0';
v.cfg.cke := '0';
end if;
ri <= v;
ribdrive <= vbdrive;
rwdata <= readdata;
end process;
sdo.sdcke <= (others => r.cfg.cke);
ahbso.hconfig <= hconfig;
ahbso.hirq <= (others => '0');
ahbso.hindex <= hindex;
ahbregs : process(clk_ahb) begin
if rising_edge(clk_ahb) then
ra <= rai;
end if;
end process;
ddrregs : process(clk_ddr, rst) begin
if rising_edge(clk_ddr) then
r <= ri; rbdrive <= ribdrive;
end if;
if (rst = '0') then
r.sdcsn <= (others => '1'); r.bdrive <= '1'; r.nbdrive <= '0';
if oepol = 0 then rbdrive <= (others => '1');
else rbdrive <= (others => '0'); end if;
r.cfg.cke <= '0';
end if;
end process;
ddr_read_regs : process(clkread) begin
if rising_edge(clkread) then
rwrite <= ri.hready; waddr2 <= r.waddr;
end if;
end process;
sdo.address <= '0' & ri.address;
sdo.ba <= ri.ba;
sdo.bdrive <= r.nbdrive when oepol = 1 else r.bdrive;
sdo.qdrive <= not (ri.qdrive or r.nbdrive);
sdo.vbdrive <= rbdrive;
sdo.sdcsn <= ri.sdcsn;
sdo.sdwen <= ri.sdwen;
sdo.dqm <= "111111111111" & r.dqm;
sdo.rasn <= ri.rasn;
sdo.casn <= ri.casn;
sdo.data <= zero32 & zero32 & zero32 & wdata;
read_buff : syncram_2p
generic map (tech => memtech, abits => 6, dbits => 32, sepclk => 1, wrfst => 0)
port map ( rclk => clk_ahb, renable => vcc, raddress => rai.raddr,
dataout => rdata, wclk => clk_ddr, write => ri.hready,
-- dataout => rdata, wclk => clkread, write => rwrite,
waddress => r.waddr, datain => rwdata);
-- waddress => waddr2, datain => rwdata);
write_buff : syncram_2p
generic map (tech => memtech, abits => 6, dbits => 32, sepclk => 1, wrfst => 0)
port map ( rclk => clk_ddr, renable => vcc, raddress => r.waddr,
dataout => wdata, wclk => clk_ahb, write => ra.write,
waddress => ra.haddr(7 downto 2), datain => ahbsi.hwdata);
-- pragma translate_off
bootmsg : report_version
generic map (
msg1 => "ddrsp" & tost(hindex) & ": 16-bit DDR266 controller rev " &
tost(REVISION) & ", " & tost(Mbyte) & " Mbyte, " & tost(MHz) &
" MHz DDR clock");
-- pragma translate_on
end;
| mit | 805df3acf8e1dc2c92ccee743fa406fb | 0.545649 | 3.078891 | false | false | false | false |
michaelfivez/ascon_hardware_implementation | ascon128128_unrolled4/Kernel/Ascon_block_datapath.vhd | 1 | 6,204 | -------------------------------------------------------------------------------
--! @project Unrolled (factor 4) hardware implementation of Asconv128128
--! @author Michael Fivez
--! @license This project is released under the GNU Public License.
--! The license and distribution terms for this file may be
--! found in the file LICENSE in this distribution or at
--! http://www.gnu.org/licenses/gpl-3.0.txt
--! @note This is an hardware implementation made for my graduation thesis
--! at the KULeuven, in the COSIC department (year 2015-2016)
--! The thesis is titled 'Energy efficient hardware implementations of CAESAR submissions',
--! and can be found on the COSIC website (www.esat.kuleuven.be/cosic/publications)
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity Ascon_StateUpdate_datapath is
port(
Clk : in std_logic; -- Clock
Reset : in std_logic; -- Reset (synchronous)
-- Control signals
RoundNr : in std_logic_vector(1 downto 0);
sel1,sel2,sel3,sel4 : in std_logic_vector(1 downto 0);
sel0 : in std_logic_vector(2 downto 0);
selout : in std_logic;
Reg0En,Reg1En,Reg2En,Reg3En,Reg4En,RegOutEn : in std_logic;
ActivateGen : in std_logic;
GenSize : in std_logic_vector(3 downto 0);
-- Data signals
IV : in std_logic_vector(127 downto 0);
Key : in std_logic_vector(127 downto 0);
DataIn : in std_logic_vector(127 downto 0);
DataOut : out std_logic_vector(127 downto 0)
);
end entity Ascon_StateUpdate_datapath;
architecture structural of Ascon_StateUpdate_datapath is
-- constants
constant EXTRAIV : std_logic_vector(63 downto 0) := x"80800c0800000000"; -- used in the initialization
constant SEPCONSTANT : std_logic_vector(63 downto 0) := x"0000000000000001";
constant ADCONSTANT : std_logic_vector(63 downto 0) := x"8000000000000000";
-- Register signals
signal Reg0In,Reg1In,Reg2In,Reg3In,Reg4In : std_logic_vector(63 downto 0);
signal Reg0Out,Reg1Out,Reg2Out,Reg3Out,Reg4Out : std_logic_vector(63 downto 0);
signal RegOutIn,RegOutOut : std_logic_vector(127 downto 0);
-- Internal signals on datapath
signal SboxOut0,SboxOut1,SboxOut2,SboxOut3,SboxOut4 : std_logic_vector(63 downto 0);
signal DiffOut0,DiffOut1,DiffOut2,DiffOut3,DiffOut4 : std_logic_vector(63 downto 0);
signal XorReg01,XorReg02,XorReg11,XorReg12 : std_logic_vector(63 downto 0);
signal XorReg2,XorReg31,XorReg32,XorReg4 : std_logic_vector(63 downto 0);
signal OutSig0,OutSig1 : std_logic_vector(127 downto 0);
begin
-- declare and connect all sub entities
rounds: entity work.Fullrounds port map(Reg0Out,Reg1Out,Reg2Out,Reg3Out,Reg4Out,RoundNr,DiffOut0,DiffOut1,DiffOut2,DiffOut3,DiffOut4);
outpgen: entity work.OutputGenerator port map(Reg0Out,Reg1Out,DataIn,GenSize,ActivateGen,XorReg01,XorReg11,OutSig0); -- ActivateGen is a bit that indicates decryption or not
---------------------------------------------
------ Combinatorial logic for a round ------
---------------------------------------------
datapath: process(IV,Key,DataIn,Reg0Out,Reg1Out,Reg2Out,Reg3Out,Reg4Out,RegOutOut, -- inputs blocks and registers
SboxOut0,SboxOut1,SboxOut2,SboxOut3,SboxOut4,DiffOut0,DiffOut1,DiffOut2,DiffOut3,DiffOut4, -- internal signals
XorReg01,XorReg02,XorReg11,XorReg12,XorReg2,XorReg31,XorReg32,XorReg4,OutSig0,OutSig1, -- internal signals
RoundNr,sel0,sel1,sel2,sel3,sel4,ActivateGen,selout,GenSize) is -- control signals
begin
-- Set correct inputs in registers
if sel0 = "000" then
Reg0In <= DiffOut0;
elsif sel0 = "001" then
Reg0In <= EXTRAIV;
elsif sel0 = "010" then
Reg0In <= XorReg01;
elsif sel0 = "011" then
Reg0In <= XorReg02;
else
Reg0In <= Reg0Out xor ADCONSTANT;
end if;
if sel1 = "00" then
Reg1In <= DiffOut1;
elsif sel1 = "01" then
Reg1In <= Key(127 downto 64);
elsif sel1 = "10" then
Reg1In <= XorReg11;
else
Reg1In <= XorReg12;
end if;
if sel2 = "00" then
Reg2In <= DiffOut2;
elsif sel2 = "01" then
Reg2In <= Key(63 downto 0);
else
Reg2In <= XorReg2;
end if;
if sel3 = "00" then
Reg3In <= DiffOut3;
elsif sel3 = "01" then
Reg3In <= IV(127 downto 64);
elsif sel3 = "10" then
Reg3In <= XorReg31;
else
Reg3In <= XorReg32;
end if;
if sel4 = "00" then
Reg4In <= DiffOut4;
elsif sel4 = "01" then
Reg4In <= IV(63 downto 0);
elsif sel4 = "10" then
Reg4In <= XorReg4;
else
Reg4In <= Reg4Out xor SEPCONSTANT;
end if;
XorReg02 <= Reg0Out xor Key(127 downto 64);
XorReg12 <= Reg1Out xor Key(63 downto 0);
XorReg2 <= Reg2Out xor Key(127 downto 64);
XorReg31 <= Reg3Out xor Key(127 downto 64);
XorReg32 <= Reg3Out xor Key(63 downto 0);
XorReg4 <= Reg4Out xor Key(63 downto 0);
-- Set output
OutSig1(127 downto 64) <= XorReg31;
OutSig1(63 downto 0) <= XorReg4;
if selout = '0' then
RegOutIn <= OutSig0;
else
RegOutIn <= OutSig1;
end if;
DataOut <= RegOutOut;
end process datapath;
---------------------------------------------
------ The registers in the datapath --------
---------------------------------------------
registerdatapath : process(Clk,Reset) is
begin
if(Clk = '1' and Clk'event) then
if Reset = '1' then -- synchronous reset
Reg0Out <= (others => '0');
Reg1Out <= (others => '0');
Reg2Out <= (others => '0');
Reg3Out <= (others => '0');
Reg4Out <= (others => '0');
RegOutOut <= (others => '0');
else
-- update registers with enable
if Reg0En = '1' then
Reg0Out <= Reg0In;
end if;
if Reg1En = '1' then
Reg1Out <= Reg1In;
end if;
if Reg2En = '1' then
Reg2Out <= Reg2In;
end if;
if Reg3En = '1' then
Reg3Out <= Reg3In;
end if;
if Reg4En = '1' then
Reg4Out <= Reg4In;
end if;
if RegOutEn = '1' then
RegOutOut <= RegOutIn;
end if;
end if;
end if;
end process registerdatapath;
end architecture structural;
| gpl-3.0 | d30c6eefee17ec3cef9ecb1e2c6afa09 | 0.624919 | 3.056158 | false | false | false | false |
impedimentToProgress/UCI-BlueChip | AttackFiles/Attacks/privEsc/lib/techmap/maps/iopad_ds.vhd | 2 | 3,749 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: iopad
-- File: iopad.vhd
-- Author: Nils Johan Wessman - Gaisler Research
-- Description: differential io pad with technology wrapper
------------------------------------------------------------------------------
library techmap;
library ieee;
use ieee.std_logic_1164.all;
use techmap.gencomp.all;
use techmap.allpads.all;
entity iopad_ds is
generic (tech : integer := 0; level : integer := 0; slew : integer := 0;
voltage : integer := x33v; strength : integer := 12;
oepol : integer := 0);
port (padp, padn : inout std_ulogic; i, en : in std_ulogic; o : out std_ulogic);
end;
architecture rtl of iopad_ds is
signal oen : std_ulogic;
begin
oen <= not en when oepol /= padoen_polarity(tech) else en;
gen0 : if has_pads(tech) = 0 generate
padp <= i after 2 ns when oen = '0'
-- pragma translate_off
else 'X' after 2 ns when is_x(oen)
-- pragma translate_on
else 'Z' after 2 ns;
padn <= not i after 2 ns when oen = '0'
-- pragma translate_off
else 'X' after 2 ns when is_x(oen)
-- pragma translate_on
else 'Z' after 2 ns;
o <= to_X01(padp) after 1 ns;
end generate;
xcv : if (tech = virtex5) generate
x0 : virtex5_iopad_ds generic map (level, slew, voltage, strength)
port map (padp, padn, i, oen, o);
end generate;
end;
library techmap;
library ieee;
use ieee.std_logic_1164.all;
use techmap.gencomp.all;
entity iopad_dsv is
generic (tech : integer := 0; level : integer := 0; slew : integer := 0;
voltage : integer := x33v; strength : integer := 12; width : integer := 1;
oepol : integer := 0);
port (
padp, padn : inout std_logic_vector(width-1 downto 0);
i : in std_logic_vector(width-1 downto 0);
en : in std_ulogic;
o : out std_logic_vector(width-1 downto 0));
end;
architecture rtl of iopad_dsv is
begin
v : for j in width-1 downto 0 generate
x0 : iopad_ds generic map (tech, level, slew, voltage, strength, oepol)
port map (padp(j), padn(j), i(j), en, o(j));
end generate;
end;
library techmap;
library ieee;
use ieee.std_logic_1164.all;
use techmap.gencomp.all;
entity iopad_dsvv is
generic (tech : integer := 0; level : integer := 0; slew : integer := 0;
voltage : integer := x33v; strength : integer := 12; width : integer := 1;
oepol : integer := 0);
port (
padp, padn : inout std_logic_vector(width-1 downto 0);
i : in std_logic_vector(width-1 downto 0);
en : in std_logic_vector(width-1 downto 0);
o : out std_logic_vector(width-1 downto 0));
end;
architecture rtl of iopad_dsvv is
begin
v : for j in width-1 downto 0 generate
x0 : iopad_ds generic map (tech, level, slew, voltage, strength, oepol)
port map (padp(j), padn(j), i(j), en(j), o(j));
end generate;
end;
| mit | 0ec6da2371524cc494922d500404336c | 0.624433 | 3.543478 | false | false | false | false |
impedimentToProgress/UCI-BlueChip | AttackFiles/Attacks/privEsc/lib/tech/cycloneiii/simprims/cycloneiii_components.vhd | 2 | 36,080 | -- Copyright (C) 1991-2007 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions
-- and other software and tools, and its AMPP partner logic
-- functions, and any output files from any of the foregoing
-- (including device programming or simulation files), and any
-- associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License
-- Subscription Agreement, Altera MegaCore Function License
-- Agreement, or other applicable license agreement, including,
-- without limitation, that your use is for the sole purpose of
-- programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the
-- applicable agreement for further details.
-- Quartus II 7.1 Build 156 04/30/2007
LIBRARY IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.VITAL_Timing.all;
use work.cycloneiii_atom_pack.all;
package CYCLONEIII_COMPONENTS is
---------------------------------------------------------------------
--
-- Entity Name : cycloneiii_ff
--
-- Description : Cyclone III FF VHDL simulation model
--
--
---------------------------------------------------------------------
component cycloneiii_ff
generic (
power_up : string := "low";
x_on_violation : string := "on";
lpm_type : string := "cycloneiii_ff";
tsetup_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_asdata_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_sclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_asdata_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_sclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_clk_q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_clrn_q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_aload_q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_asdata_q: VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_d : VitalDelayType01 := DefPropDelay01;
tipd_asdata : VitalDelayType01 := DefPropDelay01;
tipd_sclr : VitalDelayType01 := DefPropDelay01;
tipd_sload : VitalDelayType01 := DefPropDelay01;
tipd_clrn : VitalDelayType01 := DefPropDelay01;
tipd_aload : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks;
InstancePath: STRING := "*"
);
port (
d : in std_logic := '0';
clk : in std_logic := '0';
clrn : in std_logic := '1';
aload : in std_logic := '0';
sclr : in std_logic := '0';
sload : in std_logic := '0';
ena : in std_logic := '1';
asdata : in std_logic := '0';
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
q : out std_logic
);
end component;
--
-- cycloneiii_ram_block
--
component cycloneiii_ram_block
generic
(
operation_mode : string := "single_port";
mixed_port_feed_through_mode : string := "dont_care";
ram_block_type : string := "auto";
logical_ram_name : string := "ram_name";
init_file : string := "init_file.hex";
init_file_layout : string := "none";
data_interleave_width_in_bits : integer := 1;
data_interleave_offset_in_bits : integer := 1;
port_a_logical_ram_depth : integer := 0;
port_a_logical_ram_width : integer := 0;
port_a_address_clear : string := "none";
port_a_data_out_clock : string := "none";
port_a_data_out_clear : string := "none";
port_a_first_address : integer := 0;
port_a_last_address : integer := 0;
port_a_first_bit_number : integer := 0;
port_a_data_width : integer := 1;
port_a_data_in_clock : string := "clock0";
port_a_address_clock : string := "clock0";
port_a_write_enable_clock : string := "clock0";
port_a_read_enable_clock : string := "clock0";
port_a_byte_enable_clock : string := "clock0";
port_b_logical_ram_depth : integer := 0;
port_b_logical_ram_width : integer := 0;
port_b_data_in_clock : string := "clock1";
port_b_address_clock : string := "clock1";
port_b_address_clear : string := "none";
port_b_write_enable_clock: STRING := "clock1";
port_b_read_enable_clock: STRING := "clock1";
port_b_data_out_clock : string := "none";
port_b_data_out_clear : string := "none";
port_b_first_address : integer := 0;
port_b_last_address : integer := 0;
port_b_first_bit_number : integer := 0;
port_b_data_width : integer := 1;
port_b_byte_enable_clock : string := "clock1";
port_a_address_width : integer := 1;
port_b_address_width : integer := 1;
port_a_byte_enable_mask_width : integer := 1;
port_b_byte_enable_mask_width : integer := 1;
power_up_uninitialized : string := "false";
port_a_byte_size : integer := 0;
port_b_byte_size : integer := 0;
safe_write : string := "err_on_2clk";
init_file_restructured : string := "unused";
lpm_type : string := "cycloneiii_ram_block";
lpm_hint : string := "true";
clk0_input_clock_enable : STRING := "none"; -- ena0,ena2,none
clk0_core_clock_enable : STRING := "none"; -- ena0,ena2,none
clk0_output_clock_enable : STRING := "none"; -- ena0,none
clk1_input_clock_enable : STRING := "none"; -- ena1,ena3,none
clk1_core_clock_enable : STRING := "none"; -- ena1,ena3,none
clk1_output_clock_enable : STRING := "none"; -- ena1,none
port_a_read_during_write_mode : STRING := "new_data_no_nbe_read";
port_b_read_during_write_mode : STRING := "new_data_no_nbe_read";
mem_init0 : BIT_VECTOR := X"0";
mem_init1 : BIT_VECTOR := X"0";
mem_init2 : BIT_VECTOR := X"0";
mem_init3 : BIT_VECTOR := X"0";
mem_init4 : BIT_VECTOR := X"0";
connectivity_checking : string := "off"
);
port
(
portawe : in std_logic := '0';
portare : in std_logic := '1';
portabyteenamasks : in std_logic_vector (port_a_byte_enable_mask_width - 1 DOWNTO 0) := (others => '1');
portbbyteenamasks : in std_logic_vector (port_b_byte_enable_mask_width - 1 DOWNTO 0) := (others => '1');
portbre : in std_logic := '1';
portbwe : in std_logic := '0';
clr0 : in std_logic := '0';
clr1 : in std_logic := '0';
clk0 : in std_logic := '0';
clk1 : in std_logic := '0';
ena0 : in std_logic := '1';
ena1 : in std_logic := '1';
ena2 : in std_logic := '1';
ena3 : in std_logic := '1';
portadatain : in std_logic_vector (port_a_data_width - 1 DOWNTO 0) := (others => '0');
portbdatain : in std_logic_vector (port_b_data_width - 1 DOWNTO 0) := (others => '0');
portaaddr : in std_logic_vector (port_a_address_width - 1 DOWNTO 0) := (others => '0');
portbaddr : in std_logic_vector (port_b_address_width - 1 DOWNTO 0) := (others => '0');
portaaddrstall : in std_logic := '0';
portbaddrstall : in std_logic := '0';
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
portadataout : out std_logic_vector (port_a_data_width - 1 DOWNTO 0);
portbdataout : out std_logic_vector (port_b_data_width - 1 DOWNTO 0)
);
end component;
--
-- CYCLONEIII_LCELL_COMB
--
component cycloneiii_lcell_comb
generic (
lut_mask : std_logic_vector(15 downto 0) := (OTHERS => '1');
sum_lutc_input : string := "datac";
dont_touch : string := "off";
lpm_type : string := "cycloneiii_lcell_comb";
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks;
InstancePath: STRING := "*";
tpd_dataa_combout : VitalDelayType01 := DefPropDelay01;
tpd_datab_combout : VitalDelayType01 := DefPropDelay01;
tpd_datac_combout : VitalDelayType01 := DefPropDelay01;
tpd_datad_combout : VitalDelayType01 := DefPropDelay01;
tpd_cin_combout : VitalDelayType01 := DefPropDelay01;
tpd_dataa_cout : VitalDelayType01 := DefPropDelay01;
tpd_datab_cout : VitalDelayType01 := DefPropDelay01;
tpd_datac_cout : VitalDelayType01 := DefPropDelay01;
tpd_datad_cout : VitalDelayType01 := DefPropDelay01;
tpd_cin_cout : VitalDelayType01 := DefPropDelay01;
tipd_dataa : VitalDelayType01 := DefPropDelay01;
tipd_datab : VitalDelayType01 := DefPropDelay01;
tipd_datac : VitalDelayType01 := DefPropDelay01;
tipd_datad : VitalDelayType01 := DefPropDelay01;
tipd_cin : VitalDelayType01 := DefPropDelay01
);
port (
dataa : in std_logic := '1';
datab : in std_logic := '1';
datac : in std_logic := '1';
datad : in std_logic := '1';
cin : in std_logic := '0';
combout : out std_logic;
cout : out std_logic
);
end component;
--
-- CYCLONEIII_CLKCTRL
--
component cycloneiii_clkctrl
generic (
clock_type : STRING := "Auto";
lpm_type : STRING := "cycloneiii_clkctrl";
ena_register_mode : STRING := "Falling Edge";
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : STRING := "*";
tipd_inclk : VitalDelayArrayType01(3 downto 0) := (OTHERS => DefPropDelay01);
tipd_clkselect : VitalDelayArrayType01(1 downto 0) := (OTHERS => DefPropDelay01);
tipd_ena : VitalDelayType01 := DefPropDelay01
);
port (
inclk : in std_logic_vector(3 downto 0) := "0000";
clkselect : in std_logic_vector(1 downto 0) := "00";
ena : in std_logic := '1';
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
outclk : out std_logic
);
end component;
--
-- CYCLONEIII_ROUTING_WIRE
--
component cycloneiii_routing_wire
generic (
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
tpd_datain_dataout : VitalDelayType01 := DefPropDelay01;
tpd_datainglitch_dataout : VitalDelayType01 := DefPropDelay01;
tipd_datain : VitalDelayType01 := DefPropDelay01
);
PORT (
datain : in std_logic;
dataout : out std_logic
);
end component;
--
-- CYCLONEIII_PLL
--
COMPONENT cycloneiii_pll
GENERIC (
operation_mode : string := "normal";
pll_type : string := "auto"; -- EGPP/FAST/AUTO
compensate_clock : string := "clock0";
inclk0_input_frequency : integer := 0;
inclk1_input_frequency : integer := 0;
self_reset_on_loss_lock : string := "off";
switch_over_type : string := "auto";
switch_over_counter : integer := 1;
enable_switch_over_counter : string := "off";
bandwidth : integer := 0;
bandwidth_type : string := "auto";
use_dc_coupling : string := "false";
lock_c : integer := 4;
sim_gate_lock_device_behavior : string := "off";
lock_high : integer := 0;
lock_low : integer := 0;
lock_window_ui : string := "0.05";
lock_window : time := 5 ps;
test_bypass_lock_detect : string := "off";
clk0_output_frequency : integer := 0;
clk0_multiply_by : integer := 0;
clk0_divide_by : integer := 0;
clk0_phase_shift : string := "0";
clk0_duty_cycle : integer := 50;
clk1_output_frequency : integer := 0;
clk1_multiply_by : integer := 0;
clk1_divide_by : integer := 0;
clk1_phase_shift : string := "0";
clk1_duty_cycle : integer := 50;
clk2_output_frequency : integer := 0;
clk2_multiply_by : integer := 0;
clk2_divide_by : integer := 0;
clk2_phase_shift : string := "0";
clk2_duty_cycle : integer := 50;
clk3_output_frequency : integer := 0;
clk3_multiply_by : integer := 0;
clk3_divide_by : integer := 0;
clk3_phase_shift : string := "0";
clk3_duty_cycle : integer := 50;
clk4_output_frequency : integer := 0;
clk4_multiply_by : integer := 0;
clk4_divide_by : integer := 0;
clk4_phase_shift : string := "0";
clk4_duty_cycle : integer := 50;
pfd_min : integer := 0;
pfd_max : integer := 0;
vco_min : integer := 0;
vco_max : integer := 0;
vco_center : integer := 0;
-- ADVANCED USER PARAMETERS
m_initial : integer := 1;
m : integer := 0;
n : integer := 1;
c0_high : integer := 1;
c0_low : integer := 1;
c0_initial : integer := 1;
c0_mode : string := "bypass";
c0_ph : integer := 0;
c1_high : integer := 1;
c1_low : integer := 1;
c1_initial : integer := 1;
c1_mode : string := "bypass";
c1_ph : integer := 0;
c2_high : integer := 1;
c2_low : integer := 1;
c2_initial : integer := 1;
c2_mode : string := "bypass";
c2_ph : integer := 0;
c3_high : integer := 1;
c3_low : integer := 1;
c3_initial : integer := 1;
c3_mode : string := "bypass";
c3_ph : integer := 0;
c4_high : integer := 1;
c4_low : integer := 1;
c4_initial : integer := 1;
c4_mode : string := "bypass";
c4_ph : integer := 0;
m_ph : integer := 0;
clk0_counter : string := "unused";
clk1_counter : string := "unused";
clk2_counter : string := "unused";
clk3_counter : string := "unused";
clk4_counter : string := "unused";
c1_use_casc_in : string := "off";
c2_use_casc_in : string := "off";
c3_use_casc_in : string := "off";
c4_use_casc_in : string := "off";
m_test_source : integer := -1;
c0_test_source : integer := -1;
c1_test_source : integer := -1;
c2_test_source : integer := -1;
c3_test_source : integer := -1;
c4_test_source : integer := -1;
vco_multiply_by : integer := 0;
vco_divide_by : integer := 0;
vco_post_scale : integer := 1;
vco_frequency_control : string := "auto";
vco_phase_shift_step : integer := 0;
lpm_type : string := "cycloneiii_pll";
charge_pump_current : integer := 10;
loop_filter_r : string := "1.0";
loop_filter_c : integer := 0;
pll_compensation_delay : integer := 0;
simulation_type : string := "functional";
clk0_use_even_counter_mode : string := "off";
clk1_use_even_counter_mode : string := "off";
clk2_use_even_counter_mode : string := "off";
clk3_use_even_counter_mode : string := "off";
clk4_use_even_counter_mode : string := "off";
clk0_use_even_counter_value : string := "off";
clk1_use_even_counter_value : string := "off";
clk2_use_even_counter_value : string := "off";
clk3_use_even_counter_value : string := "off";
clk4_use_even_counter_value : string := "off";
-- Test only
init_block_reset_a_count : integer := 1;
init_block_reset_b_count : integer := 1;
charge_pump_current_bits : integer := 0;
lock_window_ui_bits : integer := 0;
loop_filter_c_bits : integer := 0;
loop_filter_r_bits : integer := 0;
test_counter_c0_delay_chain_bits : integer := 0;
test_counter_c1_delay_chain_bits : integer := 0;
test_counter_c2_delay_chain_bits : integer := 0;
test_counter_c3_delay_chain_bits : integer := 0;
test_counter_c4_delay_chain_bits : integer := 0;
test_counter_c5_delay_chain_bits : integer := 0;
test_counter_m_delay_chain_bits : integer := 0;
test_counter_n_delay_chain_bits : integer := 0;
test_feedback_comp_delay_chain_bits : integer := 0;
test_input_comp_delay_chain_bits : integer := 0;
test_volt_reg_output_mode_bits : integer := 0;
test_volt_reg_output_voltage_bits : integer := 0;
test_volt_reg_test_mode : string := "false";
vco_range_detector_high_bits : integer := 0;
vco_range_detector_low_bits : integer := 0;
--REM_MF -- VITAL generics
--REM_MF XOn : Boolean := DefGlitchXOn;
--REM_MF MsgOn : Boolean := DefGlitchMsgOn;
--REM_MF MsgOnChecks : Boolean := DefMsgOnChecks;
--REM_MF XOnChecks : Boolean := DefXOnChecks;
--REM_MF TimingChecksOn : Boolean := true;
--REM_MF InstancePath : STRING := "*";
--REM_MF tipd_inclk : VitalDelayArrayType01(1 downto 0) := (OTHERS => DefPropDelay01);
--REM_MF tipd_ena : VitalDelayType01 := DefPropDelay01;
--REM_MF tipd_pfdena : VitalDelayType01 := DefPropDelay01;
--REM_MF tipd_areset : VitalDelayType01 := DefPropDelay01;
--REM_MF tipd_fbin : VitalDelayType01 := DefPropDelay01;
--REM_MF tipd_scanclk : VitalDelayType01 := DefPropDelay01;
--REM_MF tipd_scanclkena : VitalDelayType01 := DefPropDelay01;
--REM_MF tipd_scandata : VitalDelayType01 := DefPropDelay01;
--REM_MF tipd_configupdate : VitalDelayType01 := DefPropDelay01;
--REM_MF tipd_clkswitch : VitalDelayType01 := DefPropDelay01;
--REM_MF tipd_phaseupdown : VitalDelayType01 := DefPropDelay01;
--REM_MF tipd_phasecounterselect : VitalDelayArrayType01(2 DOWNTO 0) := (OTHERS => DefPropDelay01);
--REM_MF tipd_phasestep : VitalDelayType01 := DefPropDelay01;
--REM_MF tsetup_scandata_scanclk_noedge_negedge : VitalDelayType := DefSetupHoldCnst;
--REM_MF thold_scandata_scanclk_noedge_negedge : VitalDelayType := DefSetupHoldCnst;
--REM_MF tsetup_scanclkena_scanclk_noedge_negedge : VitalDelayType := DefSetupHoldCnst;
--REM_MF thold_scanclkena_scanclk_noedge_negedge : VitalDelayType := DefSetupHoldCnst;
use_vco_bypass : string := "false"
);
PORT (
inclk : in std_logic_vector(1 downto 0);
fbin : in std_logic := '0';
fbout : out std_logic;
clkswitch : in std_logic := '0';
areset : in std_logic := '0';
pfdena : in std_logic := '1';
scandata : in std_logic := '0';
scanclk : in std_logic := '0';
scanclkena : in std_logic := '0';
configupdate : in std_logic := '0';
clk : out std_logic_vector(4 downto 0);
phasecounterselect : in std_logic_vector(2 downto 0) := "000";
phaseupdown : in std_logic := '0';
phasestep : in std_logic := '0';
clkbad : out std_logic_vector(1 downto 0);
activeclock : out std_logic;
locked : out std_logic;
scandataout : out std_logic;
scandone : out std_logic;
phasedone : out std_logic;
vcooverrange : out std_logic;
vcounderrange : out std_logic
);
END COMPONENT;
--
-- cycloneiii_mac_mult
--
component cycloneiii_mac_mult
GENERIC (
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : STRING := "*";
dataa_width : integer := 18;
datab_width : integer := 18;
dataa_clock : string := "none";
datab_clock : string := "none";
signa_clock : string := "none";
signb_clock : string := "none";
lpm_hint : string := "true";
lpm_type : string := "cycloneiii_mac_mult"
);
PORT (
dataa : IN std_logic_vector(dataa_width-1 DOWNTO 0) := (OTHERS => '0');
datab : IN std_logic_vector(datab_width-1 DOWNTO 0) := (OTHERS => '0');
signa : IN std_logic := '1';
signb : IN std_logic := '1';
clk : IN std_logic := '0';
aclr : IN std_logic := '0';
ena : IN std_logic := '1';
dataout : OUT std_logic_vector((dataa_width+datab_width)-1 DOWNTO 0);
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1'
);
end component;
--
-- cycloneiii_mac_out
--
component cycloneiii_mac_out
GENERIC (
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : STRING := "*";
tipd_dataa : VitalDelayArrayType01(35 downto 0)
:= (OTHERS => DefPropDelay01);
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
tipd_aclr : VitalDelayType01 := DefPropDelay01;
tpd_dataa_dataout : VitalDelayType01 := DefPropDelay01;
tpd_aclr_dataout_posedge : VitalDelayType01 := DefPropDelay01;
tpd_clk_dataout_posedge : VitalDelayType01 := DefPropDelay01;
tsetup_dataa_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_dataa_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
dataa_width : integer := 1;
output_clock : string := "none";
lpm_hint : string := "true";
lpm_type : string := "cycloneiii_mac_out"
);
PORT (
dataa : IN std_logic_vector(dataa_width-1 DOWNTO 0) := (OTHERS => '0');
clk : IN std_logic := '0';
aclr : IN std_logic := '0';
ena : IN std_logic := '1';
dataout : OUT std_logic_vector(dataa_width-1 DOWNTO 0);
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1'
);
end component;
COMPONENT cycloneiii_termination
GENERIC (
pullup_control_to_core: string := "false";
power_down : string := "true";
test_mode : string := "false";
left_shift_termination_code : string := "false";
pullup_adder : integer := 0;
pulldown_adder : integer := 0;
clock_divide_by : integer := 32; -- 1, 4, 32
runtime_control : string := "false";
shift_vref_rup : string := "true";
shift_vref_rdn : string := "true";
shifted_vref_control : string := "true";
lpm_type : string := "cycloneiii_termination");
PORT (
rup : IN std_logic := '0';
rdn : IN std_logic := '0';
terminationclock : IN std_logic := '0';
terminationclear : IN std_logic := '0';
devpor : IN std_logic := '1';
devclrn : IN std_logic := '1';
comparatorprobe : OUT std_logic;
terminationcontrolprobe : OUT std_logic;
calibrationdone : OUT std_logic;
terminationcontrol : OUT std_logic_vector(15 DOWNTO 0));
END COMPONENT;
--
-- CYCLONEIII_IO_IBUF
--
COMPONENT cycloneiii_io_ibuf
GENERIC (
tipd_i : VitalDelayType01 := DefPropDelay01;
tipd_ibar : VitalDelayType01 := DefPropDelay01;
tpd_i_o : VitalDelayType01 := DefPropDelay01;
tpd_ibar_o : VitalDelayType01 := DefPropDelay01;
XOn : Boolean := DefGlitchXOn;
MsgOn : Boolean := DefGlitchMsgOn;
differential_mode : string := "false";
bus_hold : string := "false";
lpm_type : string := "cycloneiii_io_ibuf"
);
PORT (
i : IN std_logic := '0';
ibar : IN std_logic := '0';
o : OUT std_logic
);
END COMPONENT;
--
-- CYCLONEIII_IO_OBUF
--
COMPONENT cycloneiii_io_obuf
GENERIC (
tipd_i : VitalDelayType01 := DefPropDelay01;
tipd_oe : VitalDelayType01 := DefPropDelay01;
tpd_i_o : VitalDelayType01 := DefPropDelay01;
tpd_oe_o : VitalDelayType01 := DefPropDelay01;
tpd_i_obar : VitalDelayType01 := DefPropDelay01;
tpd_oe_obar : VitalDelayType01 := DefPropDelay01;
XOn : Boolean := DefGlitchXOn;
MsgOn : Boolean := DefGlitchMsgOn;
open_drain_output : string := "false";
bus_hold : string := "false";
lpm_type : string := "cycloneiii_io_obuf"
);
PORT (
i : IN std_logic := '0';
oe : IN std_logic := '1';
seriesterminationcontrol : IN std_logic_vector(15 DOWNTO 0) := (others => '0');
devoe : IN std_logic := '1';
o : OUT std_logic;
obar : OUT std_logic
);
END COMPONENT;
--
-- CYCLONEIII_DDIO_OE
--
COMPONENT cycloneiii_ddio_oe
generic(
tipd_oe : VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
tipd_areset : VitalDelayType01 := DefPropDelay01;
tipd_sreset : VitalDelayType01 := DefPropDelay01;
XOn : Boolean := DefGlitchXOn;
MsgOn : Boolean := DefGlitchMsgOn;
power_up : string := "low";
async_mode : string := "none";
sync_mode : string := "none";
lpm_type : string := "cycloneiii_ddio_oe"
);
PORT (
oe : IN std_logic := '1';
clk : IN std_logic := '0';
ena : IN std_logic := '1';
areset : IN std_logic := '0';
sreset : IN std_logic := '0';
dataout : OUT std_logic;
dfflo : OUT std_logic;
dffhi : OUT std_logic;
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1'
);
END COMPONENT;
--
-- CYCLONEIII_DDIO_OUT
--
COMPONENT cycloneiii_ddio_out
generic(
tipd_datainlo : VitalDelayType01 := DefPropDelay01;
tipd_datainhi : VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
tipd_areset : VitalDelayType01 := DefPropDelay01;
tipd_sreset : VitalDelayType01 := DefPropDelay01;
XOn : Boolean := DefGlitchXOn;
MsgOn : Boolean := DefGlitchMsgOn;
power_up : string := "low";
async_mode : string := "none";
sync_mode : string := "none";
lpm_type : string := "cycloneiii_ddio_out"
);
PORT (
datainlo : IN std_logic := '0';
datainhi : IN std_logic := '0';
clk : IN std_logic := '0';
ena : IN std_logic := '1';
areset : IN std_logic := '0';
sreset : IN std_logic := '0';
dataout : OUT std_logic;
dfflo : OUT std_logic;
dffhi : OUT std_logic ;
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1'
);
END COMPONENT;
--
-- CYCLONEIII_IO_PAD
--
component cycloneiii_io_pad
generic (
lpm_type : STRING := "cycloneiii_io_pad"
);
PORT (
padin : in std_logic := '1';
padout: out std_logic
);
end component;
--
--
-- CYCLONEIII_RUBLOCK
--
--
component cycloneiii_rublock
generic
(
sim_init_config : string := "factory";
sim_init_watchdog_value : integer := 0;
sim_init_status : integer := 0;
lpm_type: string := "cycloneiii_rublock"
);
port
(
clk : in std_logic;
shiftnld : in std_logic;
captnupdt : in std_logic;
regin : in std_logic;
rsttimer : in std_logic;
rconfig : in std_logic;
regout : out std_logic
);
end component;
--
--
-- CYCLONEIII_APFCONTROLLER
--
--
component cycloneiii_apfcontroller
generic
(
lpm_type: string := "cycloneiii_apfcontroller"
);
port
(
usermode : out std_logic;
nceout : out std_logic
);
end component;
--
-- CYCLONEIII_JTAG
--
component cycloneiii_jtag
generic (
lpm_type : string := "cycloneiii_jtag"
);
port (
tms : in std_logic := '0';
tck : in std_logic := '0';
tdi : in std_logic := '0';
--REM_CYCyclone III ntrst : in std_logic := '0';
tdoutap : in std_logic := '0';
tdouser : in std_logic := '0';
tdo: out std_logic;
tmsutap: out std_logic;
tckutap: out std_logic;
tdiutap: out std_logic;
shiftuser: out std_logic;
clkdruser: out std_logic;
updateuser: out std_logic;
runidleuser: out std_logic;
usr1user: out std_logic
);
end component;
--
--
-- CYCLONEIII_CRCBLOCK
--
--
component cycloneiii_crcblock
generic (
oscillator_divider : integer := 1;
lpm_type : string := "cycloneiii_crcblock"
);
port (
clk : in std_logic := '0';
shiftnld : in std_logic := '0';
ldsrc : in std_logic := '0';
crcerror : out std_logic;
regout : out std_logic
);
end component;
--
--
-- CYCLONEIII_OSCILLATOR
--
--
component cycloneiii_oscillator
generic
(
lpm_type: string := "cycloneiii_oscillator"
);
port
(
oscena : in std_logic;
clkout : out std_logic
);
end component;
end cycloneiii_components;
| mit | 1c497cab9f30d56e5a28c528e177a269 | 0.476524 | 4.245205 | false | false | false | false |
lxp32/lxp32-cpu | rtl/lxp32_mul_dsp.vhd | 1 | 1,768 | ---------------------------------------------------------------------
-- DSP multiplier
--
-- Part of the LXP32 CPU
--
-- Copyright (c) 2016 by Alex I. Kuznetsov
--
-- This multiplier is designed for technologies that provide fast
-- 16x16 multipliers, including most modern FPGA families. One
-- multiplication takes 2 cycles.
---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity lxp32_mul_dsp is
port(
clk_i: in std_logic;
rst_i: in std_logic;
ce_i: in std_logic;
op1_i: in std_logic_vector(31 downto 0);
op2_i: in std_logic_vector(31 downto 0);
ce_o: out std_logic;
result_o: out std_logic_vector(31 downto 0)
);
end entity;
architecture rtl of lxp32_mul_dsp is
signal pp00: std_logic_vector(31 downto 0);
signal pp01: std_logic_vector(31 downto 0);
signal pp10: std_logic_vector(31 downto 0);
signal product: unsigned(31 downto 0);
signal ceo: std_logic:='0';
begin
mul00_inst: entity work.lxp32_mul16x16
port map(
clk_i=>clk_i,
a_i=>op1_i(15 downto 0),
b_i=>op2_i(15 downto 0),
p_o=>pp00
);
mul01_inst: entity work.lxp32_mul16x16
port map(
clk_i=>clk_i,
a_i=>op1_i(15 downto 0),
b_i=>op2_i(31 downto 16),
p_o=>pp01
);
mul10_inst: entity work.lxp32_mul16x16
port map(
clk_i=>clk_i,
a_i=>op1_i(31 downto 16),
b_i=>op2_i(15 downto 0),
p_o=>pp10
);
product(31 downto 16)<=unsigned(pp00(31 downto 16))+unsigned(pp01(15 downto 0))+unsigned(pp10(15 downto 0));
product(15 downto 0)<=unsigned(pp00(15 downto 0));
result_o<=std_logic_vector(product);
process (clk_i) is
begin
if rising_edge(clk_i) then
if rst_i='1' then
ceo<='0';
else
ceo<=ce_i;
end if;
end if;
end process;
ce_o<=ceo;
end architecture;
| mit | f6f45845d8f580568562159ecc3c1181 | 0.624434 | 2.674735 | false | false | false | false |
cafe-alpha/wascafe | v13/wasca_10m08scv4k_no_spi_20190420/wasca/wasca_inst.vhd | 1 | 8,360 | component wasca is
port (
abus_slave_0_abus_address : in std_logic_vector(9 downto 0) := (others => 'X'); -- address
abus_slave_0_abus_chipselect : in std_logic_vector(2 downto 0) := (others => 'X'); -- chipselect
abus_slave_0_abus_read : in std_logic := 'X'; -- read
abus_slave_0_abus_write : in std_logic_vector(1 downto 0) := (others => 'X'); -- write
abus_slave_0_abus_waitrequest : out std_logic; -- waitrequest
abus_slave_0_abus_interrupt : out std_logic; -- interrupt
abus_slave_0_abus_addressdata : inout std_logic_vector(15 downto 0) := (others => 'X'); -- addressdata
abus_slave_0_abus_direction : out std_logic; -- direction
abus_slave_0_abus_muxing : out std_logic_vector(1 downto 0); -- muxing
abus_slave_0_abus_disableout : out std_logic; -- disableout
abus_slave_0_conduit_saturn_reset_saturn_reset : in std_logic := 'X'; -- saturn_reset
altpll_0_areset_conduit_export : in std_logic := 'X'; -- export
altpll_0_locked_conduit_export : out std_logic; -- export
altpll_0_phasedone_conduit_export : out std_logic; -- export
clk_clk : in std_logic := 'X'; -- clk
clock_116_mhz_clk : out std_logic; -- clk
external_sdram_controller_wire_addr : out std_logic_vector(12 downto 0); -- addr
external_sdram_controller_wire_ba : out std_logic_vector(1 downto 0); -- ba
external_sdram_controller_wire_cas_n : out std_logic; -- cas_n
external_sdram_controller_wire_cke : out std_logic; -- cke
external_sdram_controller_wire_cs_n : out std_logic; -- cs_n
external_sdram_controller_wire_dq : inout std_logic_vector(15 downto 0) := (others => 'X'); -- dq
external_sdram_controller_wire_dqm : out std_logic_vector(1 downto 0); -- dqm
external_sdram_controller_wire_ras_n : out std_logic; -- ras_n
external_sdram_controller_wire_we_n : out std_logic; -- we_n
leds_conn_export : out std_logic_vector(3 downto 0); -- export
sdram_clkout_clk : out std_logic; -- clk
switches_conn_export : in std_logic_vector(2 downto 0) := (others => 'X'); -- export
uart_0_external_connection_rxd : in std_logic := 'X'; -- rxd
uart_0_external_connection_txd : out std_logic -- txd
);
end component wasca;
u0 : component wasca
port map (
abus_slave_0_abus_address => CONNECTED_TO_abus_slave_0_abus_address, -- abus_slave_0_abus.address
abus_slave_0_abus_chipselect => CONNECTED_TO_abus_slave_0_abus_chipselect, -- .chipselect
abus_slave_0_abus_read => CONNECTED_TO_abus_slave_0_abus_read, -- .read
abus_slave_0_abus_write => CONNECTED_TO_abus_slave_0_abus_write, -- .write
abus_slave_0_abus_waitrequest => CONNECTED_TO_abus_slave_0_abus_waitrequest, -- .waitrequest
abus_slave_0_abus_interrupt => CONNECTED_TO_abus_slave_0_abus_interrupt, -- .interrupt
abus_slave_0_abus_addressdata => CONNECTED_TO_abus_slave_0_abus_addressdata, -- .addressdata
abus_slave_0_abus_direction => CONNECTED_TO_abus_slave_0_abus_direction, -- .direction
abus_slave_0_abus_muxing => CONNECTED_TO_abus_slave_0_abus_muxing, -- .muxing
abus_slave_0_abus_disableout => CONNECTED_TO_abus_slave_0_abus_disableout, -- .disableout
abus_slave_0_conduit_saturn_reset_saturn_reset => CONNECTED_TO_abus_slave_0_conduit_saturn_reset_saturn_reset, -- abus_slave_0_conduit_saturn_reset.saturn_reset
altpll_0_areset_conduit_export => CONNECTED_TO_altpll_0_areset_conduit_export, -- altpll_0_areset_conduit.export
altpll_0_locked_conduit_export => CONNECTED_TO_altpll_0_locked_conduit_export, -- altpll_0_locked_conduit.export
altpll_0_phasedone_conduit_export => CONNECTED_TO_altpll_0_phasedone_conduit_export, -- altpll_0_phasedone_conduit.export
clk_clk => CONNECTED_TO_clk_clk, -- clk.clk
clock_116_mhz_clk => CONNECTED_TO_clock_116_mhz_clk, -- clock_116_mhz.clk
external_sdram_controller_wire_addr => CONNECTED_TO_external_sdram_controller_wire_addr, -- external_sdram_controller_wire.addr
external_sdram_controller_wire_ba => CONNECTED_TO_external_sdram_controller_wire_ba, -- .ba
external_sdram_controller_wire_cas_n => CONNECTED_TO_external_sdram_controller_wire_cas_n, -- .cas_n
external_sdram_controller_wire_cke => CONNECTED_TO_external_sdram_controller_wire_cke, -- .cke
external_sdram_controller_wire_cs_n => CONNECTED_TO_external_sdram_controller_wire_cs_n, -- .cs_n
external_sdram_controller_wire_dq => CONNECTED_TO_external_sdram_controller_wire_dq, -- .dq
external_sdram_controller_wire_dqm => CONNECTED_TO_external_sdram_controller_wire_dqm, -- .dqm
external_sdram_controller_wire_ras_n => CONNECTED_TO_external_sdram_controller_wire_ras_n, -- .ras_n
external_sdram_controller_wire_we_n => CONNECTED_TO_external_sdram_controller_wire_we_n, -- .we_n
leds_conn_export => CONNECTED_TO_leds_conn_export, -- leds_conn.export
sdram_clkout_clk => CONNECTED_TO_sdram_clkout_clk, -- sdram_clkout.clk
switches_conn_export => CONNECTED_TO_switches_conn_export, -- switches_conn.export
uart_0_external_connection_rxd => CONNECTED_TO_uart_0_external_connection_rxd, -- uart_0_external_connection.rxd
uart_0_external_connection_txd => CONNECTED_TO_uart_0_external_connection_txd -- .txd
);
| gpl-2.0 | f70bfa80630d01264cdc069fba60980d | 0.435885 | 4.533623 | false | false | false | false |
impedimentToProgress/UCI-BlueChip | AttackFiles/Attacks/privEsc/lib/gaisler/ambatest/ahbslv_em.vhd | 2 | 6,496 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: ahbslv_em
-- File: ahbslv_em.vhd
-- Author: Alf Vaerneus, Gaisler Research
-- Description: AMBA AHB Slave emulator for simulation purposes only
------------------------------------------------------------------------------
-- pragma translate_off
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
library gaisler;
use grlib.devices.all;
use gaisler.ambatest.all;
library std;
use std.textio.all;
entity ahbslv_em is
generic(
hindex : integer := 0;
abits : integer := 10;
waitcycles : integer := 2;
retries : integer := 0;
memaddr : integer := 16#E00#;
memmask : integer := 16#F00#;
ioaddr : integer := 16#000#;
timeoutc : integer := 100;
dbglevel : integer := 1
);
port(
rst : in std_logic;
clk : in std_logic;
-- AMBA signals
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
-- TB signals
tbi : in tb_in_type;
tbo : out tb_out_type
);
end;
architecture tb of ahbslv_em is
constant VERSION : integer := 1;
constant hconfig : ahb_config_type := (
0 => ahb_device_reg (VENDOR_GAISLER, GAISLER_AHBSLV_EM, 0, VERSION, 0),
4 => ahb_membar(memaddr, '0', '0', memmask),
others => zero32);
constant T_O : integer := timeoutc;
type mem_type is array(0 to ((2**abits)-1)) of std_logic_vector(31 downto 0);
type state_type is(idle,w,write,read,retry1,retry2);
type reg_type is record
state : state_type;
ad : std_logic_vector(abits-1 downto 0);
di : std_logic_vector(31 downto 0);
waitc : integer;
nretry : integer;
write : std_logic;
end record;
signal r,rin : reg_type;
signal do : std_logic_vector(31 downto 0);
begin
cont : process
file readfile,writefile : text;
variable first : boolean := true;
variable mem : mem_type;
variable L : line;
variable datahex : string(1 to 8);
variable count : integer;
begin
if first then
for i in 0 to ((2**abits)-1) loop
mem(i) := (others => '0');
end loop;
first := false;
elsif tbi.start = '1' then
if tbi.usewfile then
file_open(writefile, external_name => tbi.wfile(18 downto trimlen(tbi.wfile)), open_kind => write_mode);
count := conv_integer(tbi.address(abits-1 downto 0));
for i in 0 to tbi.no_words-1 loop
write(L,printhex(mem(count),32));
writeline(writefile,L);
count := count+4;
end loop;
file_close(writefile);
end if;
elsif r.ad(0) /= 'U' then
do <= mem(conv_integer(to_x01(r.ad)));
if r.write = '1' then mem(conv_integer(to_x01(r.ad))) := ahbsi.hwdata; end if;
end if;
tbo.ready <= tbi.start;
wait for 1 ns;
end process;
comb : process(ahbsi, rst, r)
variable v : reg_type;
variable vahbso : ahb_slv_out_type;
begin
v := r; v.write := '0';
v.di := ahbsi.hwdata;
vahbso.hready := '1'; vahbso.hresp := HRESP_OKAY;
vahbso.hrdata := do; vahbso.hsplit := (others => '0');
vahbso.hcache := '0'; vahbso.hirq := (others => '0');
vahbso.hconfig := hconfig;
if ahbsi.hready = '1' then v.ad := ahbsi.haddr(abits-1 downto 0); end if;
case r.state is
when idle =>
if (ahbsi.hsel(hindex) and ahbsi.hready and ahbsi.htrans(1)) = '1' then
if r.waitc > 0 then v.state := w; v.waitc := r.waitc-1;
elsif r.nretry > 0 then v.state := retry1;
elsif ahbsi.hwrite = '1' then v.state := write; v.write := '1';
else v.state := read; end if;
end if;
when w =>
vahbso.hready := '0';
if r.waitc = 0 then
v.waitc := waitcycles;
if r.nretry > 0 then v.state := retry1;
elsif ahbsi.hwrite = '1' then v.state := write; v.write := '1';
else v.state := read; end if;
else v.waitc := r.waitc-1; end if;
when write =>
v.nretry := retries;
if (ahbsi.hsel(hindex) and ahbsi.htrans(1)) = '0' then v.state := idle;
elsif r.waitc > 0 then v.state := w; v.waitc := r.waitc-1;
elsif ahbsi.hwrite = '0' then v.state := read;
else v.write := '1'; end if;
when read =>
v.nretry := retries;
if (ahbsi.hsel(hindex) and ahbsi.htrans(1)) = '0' then v.state := idle;
elsif r.waitc > 0 then v.state := w; v.waitc := r.waitc-1;
elsif ahbsi.hwrite = '1' then v.state := write; end if;
when retry1 =>
vahbso.hready := '0'; v.nretry := r.nretry-1;
vahbso.hresp := HRESP_RETRY;
v.state := retry2;
when retry2 =>
vahbso.hresp := HRESP_RETRY;
if (ahbsi.hsel(hindex) and ahbsi.hready and ahbsi.htrans(1)) = '1' then
if r.waitc > 0 then v.state := w; v.waitc := r.waitc-1;
elsif r.nretry > 0 then v.state := retry1;
elsif ahbsi.hwrite = '1' then v.state := write; v.write := '1';
else v.state := read; end if;
end if;
when others =>
end case;
vahbso.hindex := hindex;
if rst = '0' then
v.state := idle;
v.waitc := waitcycles;
v.nretry := retries;
v.ad := (others => '0');
v.di := (others => '0');
end if;
rin <= v;
ahbso <= vahbso;
end process;
clockreg : process(clk)
begin
if rising_edge(clk) then
r <= rin;
end if;
end process;
bootmsg : report_version
generic map ("pcislv_em" & tost(hindex) &
": PCI Slave Emulator rev " & tost(VERSION) &
" for simulation purpose only." &
" NOT syntheziseable.");
end;
-- pragma translate_on
| mit | bbe0f7b6fc1b22d66402adff3e12766c | 0.57928 | 3.35364 | false | false | false | false |
michaelfivez/ascon_hardware_implementation | ascon12864_iterated/API_plus_CipherCore/CypherCore.vhd | 1 | 14,107 | -------------------------------------------------------------------------------
--! @project Iterated hardware implementation of Asconv12864
--! @author Michael Fivez
--! @license This project is released under the GNU Public License.
--! The license and distribution terms for this file may be
--! found in the file LICENSE in this distribution or at
--! http://www.gnu.org/licenses/gpl-3.0.txt
--! @note This is an hardware implementation made for my graduation thesis
--! at the KULeuven, in the COSIC department (year 2015-2016)
--! The thesis is titled 'Energy efficient hardware implementations of CAESAR submissions',
--! and can be found on the COSIC website (www.esat.kuleuven.be/cosic/publications)
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.ALL;
use ieee.numeric_std.all;
entity CipherCore is
generic (
G_NPUB_SIZE : integer := 128; --! Npub size (bits)
G_NSEC_SIZE : integer := 128; --! Nsec size (bits)
G_DBLK_SIZE : integer := 64; --! Data Block size (bits)
G_KEY_SIZE : integer := 128; --! Key size (bits)
G_RDKEY_SIZE : integer := 128; --! Round Key size (bits)
G_TAG_SIZE : integer := 128; --! Tag size (bits)
G_BS_BYTES : integer := 3; --! The number of bits required to hold block size expressed in bytes = log2_ceil(max(G_ABLK_SIZE,G_DBLK_SIZE)/8)
G_CTR_AD_SIZE : integer := 64; --! Maximum size for the counter that keeps track of authenticated data
G_CTR_D_SIZE : integer := 64 --! Maximum size for the counter that keeps track of data
);
port (
clk : in std_logic;
rst : in std_logic;
npub : in std_logic_vector(G_NPUB_SIZE -1 downto 0);
nsec : in std_logic_vector(G_NSEC_SIZE -1 downto 0);
key : in std_logic_vector(G_KEY_SIZE -1 downto 0);
rdkey : in std_logic_vector(G_RDKEY_SIZE -1 downto 0);
bdi : in std_logic_vector(G_DBLK_SIZE -1 downto 0);
exp_tag : in std_logic_vector(G_TAG_SIZE -1 downto 0);
len_a : in std_logic_vector(G_CTR_AD_SIZE -1 downto 0);
len_d : in std_logic_vector(G_CTR_D_SIZE -1 downto 0);
key_ready : in std_logic;
key_updated : out std_logic;
key_needs_update : in std_logic;
rdkey_ready : in std_logic;
rdkey_read : out std_logic;
npub_ready : in std_logic;
npub_read : out std_logic;
nsec_ready : in std_logic;
nsec_read : out std_logic;
bdi_ready : in std_logic;
bdi_proc : in std_logic;
bdi_ad : in std_logic;
bdi_nsec : in std_logic;
bdi_pad : in std_logic;
bdi_decrypt : in std_logic;
bdi_eot : in std_logic;
bdi_eoi : in std_logic;
bdi_read : out std_logic;
bdi_size : in std_logic_vector(G_BS_BYTES -1 downto 0);
bdi_valid_bytes : in std_logic_vector(G_DBLK_SIZE/8 -1 downto 0);
bdi_pad_loc : in std_logic_vector(G_DBLK_SIZE/8 -1 downto 0);
bdi_nodata : in std_logic;
exp_tag_ready : in std_logic;
bdo_ready : in std_logic;
bdo_write : out std_logic;
bdo : out std_logic_vector(G_DBLK_SIZE -1 downto 0);
bdo_size : out std_logic_vector(G_BS_BYTES+1 -1 downto 0);
bdo_nsec : out std_logic;
tag_ready : in std_logic;
tag_write : out std_logic;
tag : out std_logic_vector(G_TAG_SIZE -1 downto 0);
msg_auth_done : out std_logic;
msg_auth_valid : out std_logic
);
end entity CipherCore;
architecture structure of CipherCore is
-- Registers
signal keyreg,npubreg : std_logic_vector(127 downto 0);
-- Control signals AsconCore
signal AsconStart : std_logic;
signal AsconMode : std_logic_vector(3 downto 0);
signal AsconBusy : std_logic;
signal AsconSize : std_logic_vector(2 downto 0);
signal AsconInput : std_logic_vector(63 downto 0);
-- Internal Datapath signals
signal AsconOutput : std_logic_vector(127 downto 0);
begin
-- Morus_core entity
AsconCore : entity work.Ascon_StateUpdate port map(clk,rst,AsconStart,AsconMode,AsconSize,npubreg,keyreg,AsconInput,AsconBusy,AsconOutput);
----------------------------------------
------ DataPath for CipherCore ---------
----------------------------------------
datapath: process(AsconOutput,exp_tag,bdi,AsconInput) is
begin
-- Connect signals to the MorusCore
AsconInput <= bdi;
tag <= AsconOutput;
bdo <= AsconOutput(63 downto 0);
if AsconOutput = exp_tag then
msg_auth_valid <= '1';
else
msg_auth_valid <= '0';
end if;
end process datapath;
----------------------------------------
------ ControlPath for CipherCore ------
----------------------------------------
fsm: process(clk, rst) is
type state_type is (IDLE,INIT_1,INIT_2,PROCESSING,RUN_CIPHER_1,RUN_CIPHER_2,RUN_CIPHER_3,TAG_1,TAG_2);
variable CurrState : state_type := IDLE;
variable firstblock : std_logic;
variable lastblock : std_logic_vector(1 downto 0);
variable afterRunning : std_logic_vector(2 downto 0);
begin
if(clk = '1' and clk'event) then
if rst = '1' then -- synchornous reset
key_updated <= '0';
CurrState := IDLE;
firstblock := '0';
keyreg <= (others => '0');
npubreg <= (others => '0');
AsconMode <= (others => '0'); -- the mode is a register
afterRunning := (others => '0');
else
-- registers above in reset are used
-- Standard values of the control signals are zero
AsconStart <= '0';
bdi_read <= '0';
msg_auth_done <= '0';
bdo_write <= '0';
bdo_size <= "1000";
tag_write <= '0';
npub_read <= '0';
AsconSize <= (others => '0');
FsmLogic: case CurrState is
when IDLE =>
-- if key_needs_update = '1' then -- Key needs updating
-- if key_ready = '1' then
-- key_updated <= '1';
-- keyreg <= key;
-- CurrState := IDLE;
-- else
-- CurrState := IDLE;
-- end if;
if key_needs_update = '1' and key_ready = '1' then -- Key needs updating
key_updated <= '1';
keyreg <= key;
CurrState := IDLE;
elsif bdi_proc = '1' and npub_ready = '1' then -- start of processing
CurrState := INIT_1;
npubreg <= npub;
npub_read <= '1';
AsconMode <= "0010"; -- Mode: initialization
AsconStart <= '1';
else
CurrState := IDLE;
end if;
when INIT_1 =>
if AsconBusy = '1' then
CurrState := INIT_2; -- to INIT_2
else
AsconStart <= '1';
CurrState := INIT_1; -- to INIT_1
end if;
when INIT_2 =>
if AsconBusy = '0' then
CurrState := PROCESSING; -- to PROCESSING
firstblock := '1';
lastblock := "00";
else
CurrState := INIT_2; -- to INIT_2
end if;
-- EVEN SIMPLIFY THIS AFTER YOU SEE IF WORKS
when PROCESSING =>
if lastblock(1) = '1' then -- Generate the Tag
AsconMode <= "0001";
AsconStart <= '1';
CurrState := TAG_1;
elsif bdi_ready = '1' then
if firstblock = '1' and bdi_ad = '0' then -- No associative data (and return in function)
-- SEP_CONST
AsconMode <= "0011";
AsconStart <= '1';
CurrState := PROCESSING;
elsif bdi_ad = '1' then
if bdi_eot = '0' then
-- AD_PROCESS
AsconMode <= "0000";
AsconStart <= '1';
afterRunning := "000";
CurrState := RUN_CIPHER_1;
elsif bdi_eoi = '0' then
if bdi_size = "000" then
-- AD_PROCESS + case2 + SEP_CONST
AsconMode <= "0000";
AsconStart <= '1';
afterRunning := "001";
CurrState := RUN_CIPHER_1;
else
-- AD_PROCESS + SEP_CONST
AsconMode <= "0000";
AsconStart <= '1';
afterRunning := "010";
CurrState := RUN_CIPHER_1;
end if;
else
if bdi_size = "000" then
-- AD_PROCESS + case2 + SEP_CONST + case1
AsconMode <= "0000";
AsconStart <= '1';
afterRunning := "101";
CurrState := RUN_CIPHER_1;
else
-- AD_PROCESS + SEP_CONST + case1
AsconMode <= "0000";
AsconStart <= '1';
afterRunning := "110";
CurrState := RUN_CIPHER_1;
end if;
end if;
else
if bdi_decrypt = '0' then
if bdi_eot = '0' then
-- ENCRYPT
AsconMode <= "0110";
AsconStart <= '1';
afterRunning := "011";
CurrState := RUN_CIPHER_1;
elsif bdi_size = "000" then
-- ENCRYPT + case1
AsconMode <= "0110";
AsconStart <= '1';
afterRunning := "100";
CurrState := RUN_CIPHER_1;
else
-- LAST_BLOCK_ENCRYPT
bdi_read <= '1';
AsconMode <= "0111";
AsconStart <= '1';
afterRunning := "011";
CurrState := RUN_CIPHER_2;
end if;
else
if bdi_eot = '0' then
-- DECRYPT
AsconMode <= "0100";
AsconStart <= '1';
afterRunning := "011";
CurrState := RUN_CIPHER_1;
elsif bdi_size = "000" then
-- DECRYPT + case1
AsconMode <= "0100";
AsconStart <= '1';
afterRunning := "100";
CurrState := RUN_CIPHER_1;
else
-- LAST_BLOCK_DECRYPT
bdi_read <= '1';
AsconMode <= "0101";
AsconStart <= '1';
AsconSize <= bdi_size;
afterRunning := "011";
CurrState := RUN_CIPHER_2;
end if;
end if;
end if;
-- check if tag after (eoi, with special case when no associative data:
-- This is needed, because if no associative data, it will do it's thing and then still the message block is
-- left to be processed
if firstblock = '1' and bdi_ad = '0' then -- lastblock will be set next return in the function
lastblock := "00";
elsif bdi_eoi = '1' and bdi_decrypt = '0' then -- the one after is tag encryption
lastblock := "10";
elsif bdi_eoi = '1' then -- the one after is tag decryption
lastblock := "11";
end if;
-- not firstblock anymore :
firstblock := '0';
end if;
when RUN_CIPHER_1 =>
if AsconBusy = '1' then
CurrState := RUN_CIPHER_2;
bdi_read <= '1';
else
AsconStart <= '1';
CurrState := RUN_CIPHER_1;
end if;
when RUN_CIPHER_3 =>
if AsconBusy = '1' then
CurrState := RUN_CIPHER_2;
else
AsconStart <= '1';
CurrState := RUN_CIPHER_3;
end if;
when RUN_CIPHER_2 =>
if AsconBusy = '0' then
-- logic here:
-- a simple variable is used for the cases where after the cipher something special has to be done:
-- activating authregister after associative data = 1
-- resetting of blocknumber after last associative data = 2 (so also do 1's job)
-- giving of output after encryption/decryption = 3 for encryption, 4 for decryption
-- activating checksum after decription of message = 4
-- special giving of output after padded encryption/decryption = 5 and 6 (determines output_sel), also wait with bdi_read
AfterRunLogic: case afterRunning is
when "000" => -- return to IDLE
CurrState := PROCESSING;
when "001" => -- case2 and sep_cont after
AsconMode <= "1001";
AsconStart <= '1';
CurrState := RUN_CIPHER_3;
afterRunning := "010";
when "010" => -- SEPCONSTANT and return to IDLE
AsconMode <= "0011";
AsconStart <= '1';
CurrState := PROCESSING;
when "011" => -- GIVE OUTPUT and return to IDLE
if bdo_ready = '1' then
bdo_write <= '1';
CurrState := PROCESSING;
else
CurrState := RUN_CIPHER_2;
end if;
when "100" => -- GIVE OUTPUT & case1 and return to IDLE
if bdo_ready = '1' then
bdo_write <= '1';
CurrState := PROCESSING;
AsconMode <= "1000";
AsconStart <= '1';
else
CurrState := RUN_CIPHER_2;
end if;
when "101" => -- case2 and case1 and sep_cont after
AsconMode <= "1001";
AsconStart <= '1';
CurrState := RUN_CIPHER_3;
afterRunning := "110";
when "110" => -- case1 and sep_cont after
AsconMode <= "1000";
AsconStart <= '1';
CurrState := RUN_CIPHER_2;
afterRunning := "010";
when others =>
end case AfterRunLogic;
else
CurrState := RUN_CIPHER_2;
end if;
when TAG_1 =>
if AsconBusy = '1' then
CurrState := TAG_2;
else
AsconStart <= '1';
CurrState := TAG_1;
end if;
when TAG_2 =>
if AsconBusy = '0' and lastblock(0) = '0' then -- Generate Tag
if tag_ready = '1' then
tag_write <= '1';
key_updated <= '0';
CurrState := IDLE;
else
CurrState := TAG_2;
end if;
elsif AsconBusy = '0' then -- Compare Tag
if exp_tag_ready = '1' then
msg_auth_done <= '1';
key_updated <= '0';
CurrState := IDLE;
else
CurrState := TAG_2;
end if;
else
CurrState := TAG_2;
end if;
when others =>
end case FsmLogic;
end if;
end if;
end process fsm;
end architecture structure;
| gpl-3.0 | 837a79d5dcba9c408817751f8bdbaa63 | 0.518891 | 3.402557 | false | false | false | false |
impedimentToProgress/UCI-BlueChip | AttackFiles/Attacks/privEsc/lib/cypress/ssram/cy7c1380d.vhd | 2 | 26,462 | --***************************************************************************************
--
-- File Name: CY7C1380_PL_SCD.vhd
-- Version: 1.0
-- Date: December 22nd, 2004
-- Model: BUS Functional
-- Simulator: Modelsim
--
--
-- Queries: MPD Applications
-- Website: www.cypress.com/support
-- Company: Cypress Semiconductor
-- Part #: CY7C1380D (512K x 36)
--
-- Description: Cypress 18Mb Synburst SRAM (Pipelined SCD)
--
--
-- Disclaimer: THESE DESIGNS ARE PROVIDED "AS IS" WITH NO WARRANTY
-- WHATSOEVER AND CYPRESS SPECIFICALLY DISCLAIMS ANY
-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR
-- A PARTICULAR PURPOSE, OR AGAINST INFRINGEMENT.
--
-- Copyright(c) Cypress Semiconductor, 2004
-- All rights reserved
--
-- Rev Date Changes
-- --- ---------- ---------------------------------------
-- 1.0 12/22/2004 - New Model
-- - New Test Bench
-- - New Test Vectors
--
--***************************************************************************************
-- Timings for Different Speed Bins (sb): 250MHz, 225MHz, 200MHz, 167MHz, 133MHz
LIBRARY ieee, grlib, gaisler, work;
USE ieee.std_logic_1164.all;
-- USE ieee.std_logic_unsigned.all;
-- Use IEEE.Std_Logic_Arith.all;
USE work.package_utility.all;
use grlib.stdlib.all;
use ieee.std_logic_1164.all;
use std.textio.all;
use gaisler.sim.all;
entity CY7C1380D is
GENERIC (
fname : string := "prom.srec"; -- File to read from
-- Constant Parameters
addr_bits : INTEGER := 19; -- This is external address
data_bits : INTEGER := 36;
--Clock timings for 250Mhz
Cyp_tCO : TIME := 2.6 ns; -- Data Output Valid After CLK Rise
Cyp_tCYC : TIME := 4.0 ns; -- Clock cycle time
Cyp_tCH : TIME := 1.7 ns; -- Clock HIGH time
Cyp_tCL : TIME := 1.7 ns; -- Clock LOW time
Cyp_tCHZ : TIME := 2.6 ns; -- Clock to High-Z
Cyp_tCLZ : TIME := 1.0 ns; -- Clock to Low-Z
Cyp_tOEHZ : TIME := 2.6 ns; -- OE# HIGH to Output High-Z
Cyp_tOELZ : TIME := 0.0 ns; -- OE# LOW to Output Low-Z
Cyp_tOEV : TIME := 2.6 ns; -- OE# LOW to Output Valid
Cyp_tAS : TIME := 1.2 ns; -- Address Set-up Before CLK Rise
Cyp_tADS : TIME := 1.2 ns; -- ADSC#, ADSP# Set-up Before CLK Rise
Cyp_tADVS : TIME := 1.2 ns; -- ADV# Set-up Before CLK Rise
Cyp_tWES : TIME := 1.2 ns; -- BWx#, GW#, BWE# Set-up Before CLK Rise
Cyp_tDS : TIME := 1.2 ns; -- Data Input Set-up Before CLK Rise
Cyp_tCES : TIME := 1.2 ns; -- Chip Enable Set-up
Cyp_tAH : TIME := 0.3 ns; -- Address Hold After CLK Rise
Cyp_tADH : TIME := 0.3 ns; -- ADSC#, ADSP# Hold After CLK Rise
Cyp_tADVH : TIME := 0.3 ns; -- ADV# Hold After CLK Rise
Cyp_tWEH : TIME := 0.3 ns; -- BWx#, GW#, BWE# Hold After CLK Rise
Cyp_tDH : TIME := 0.3 ns; -- Data Input Hold After CLK Rise
Cyp_tCEH : TIME := 0.3 ns -- Chip Enable Hold After CLK Rise
--Clock timings for 225Mhz
-- Cyp_tCO : TIME := 2.8 ns; -- Data Output Valid After CLK Rise
-- Cyp_tCYC : TIME := 4.4 ns; -- Clock cycle time
-- Cyp_tCH : TIME := 2.0 ns; -- Clock HIGH time
-- Cyp_tCL : TIME := 2.0 ns; -- Clock LOW time
-- Cyp_tCHZ : TIME := 2.8 ns; -- Clock to High-Z
-- Cyp_tCLZ : TIME := 1.0 ns; -- Clock to Low-Z
-- Cyp_tOEHZ: TIME := 2.8 ns; -- OE# HIGH to Output High-Z
-- Cyp_tOELZ: TIME := 0.0 ns; -- OE# LOW to Output Low-Z
-- Cyp_tOEV : TIME := 2.8 ns; -- OE# LOW to Output Valid
-- Cyp_tAS : TIME := 1.4 ns; -- Address Set-up Before CLK Rise
-- Cyp_tADS : TIME := 1.4 ns; -- ADSC#, ADSP# Set-up Before CLK Rise
-- Cyp_tADVS: TIME := 1.4 ns; -- ADV# Set-up Before CLK Rise
-- Cyp_tWES : TIME := 1.4 ns; -- BWx#, GW#, BWE# Set-up Before CLK Rise
-- Cyp_tDS : TIME := 1.4 ns; -- Data Input Set-up Before CLK Rise
-- Cyp_tCES : TIME := 1.4 ns; -- Chip Enable Set-up
-- Cyp_tAH : TIME := 0.4 ns; -- Address Hold After CLK Rise
-- Cyp_tADH : TIME := 0.4 ns; -- ADSC#, ADSP# Hold After CLK Rise
-- Cyp_tADVH: TIME := 0.4 ns; -- ADV# Hold After CLK Rise
-- Cyp_tWEH : TIME := 0.4 ns; -- BWx#, GW#, BWE# Hold After CLK Rise
-- Cyp_tDH : TIME := 0.4 ns; -- Data Input Hold After CLK Rise
-- Cyp_tCEH : TIME := 0.4 ns -- Chip Enable Hold After CLK Rise
--Clock timings for 200Mhz
-- Cyp_tCO : TIME := 3.0 ns; -- Data Output Valid After CLK Rise
-- Cyp_tCYC : TIME := 5.0 ns; -- Clock cycle time
-- Cyp_tCH : TIME := 2.0 ns; -- Clock HIGH time
-- Cyp_tCL : TIME := 2.0 ns; -- Clock LOW time
-- Cyp_tCHZ : TIME := 3.0 ns; -- Clock to High-Z
-- Cyp_tCLZ : TIME := 1.3 ns; -- Clock to Low-Z
-- Cyp_tOEHZ: TIME := 3.0 ns; -- OE# HIGH to Output High-Z
-- Cyp_tOELZ: TIME := 0.0 ns; -- OE# LOW to Output Low-Z
-- Cyp_tOEV : TIME := 3.0 ns; -- OE# LOW to Output Valid
-- Cyp_tAS : TIME := 1.4 ns; -- Address Set-up Before CLK Rise
-- Cyp_tADS : TIME := 1.4 ns; -- ADSC#, ADSP# Set-up Before CLK Rise
-- Cyp_tADVS: TIME := 1.4 ns; -- ADV# Set-up Before CLK Rise
-- Cyp_tWES : TIME := 1.4 ns; -- BWx#, GW#, BWE# Set-up Before CLK Rise
-- Cyp_tDS : TIME := 1.4 ns; -- Data Input Set-up Before CLK Rise
-- Cyp_tCES : TIME := 1.4 ns; -- Chip Enable Set-up
-- Cyp_tAH : TIME := 0.4 ns; -- Address Hold After CLK Rise
-- Cyp_tADH : TIME := 0.4 ns; -- ADSC#, ADSP# Hold After CLK Rise
-- Cyp_tADVH: TIME := 0.4 ns; -- ADV# Hold After CLK Rise
-- Cyp_tWEH : TIME := 0.4 ns; -- BWx#, GW#, BWE# Hold After CLK Rise
-- Cyp_tDH : TIME := 0.4 ns; -- Data Input Hold After CLK Rise
-- Cyp_tCEH : TIME := 0.4 ns -- Chip Enable Hold After CLK Rise
--Clock timings for 167Mhz
-- Cyp_tCO : TIME := 3.4 ns; -- Data Output Valid After CLK Rise
-- Cyp_tCYC : TIME := 6.0 ns; -- Clock cycle time
-- Cyp_tCH : TIME := 2.2 ns; -- Clock HIGH time
-- Cyp_tCL : TIME := 2.2 ns; -- Clock LOW time
-- Cyp_tCHZ : TIME := 3.4 ns; -- Clock to High-Z
-- Cyp_tCLZ : TIME := 1.3 ns; -- Clock to Low-Z
-- Cyp_tOEHZ: TIME := 3.4 ns; -- OE# HIGH to Output High-Z
-- Cyp_tOELZ: TIME := 0.0 ns; -- OE# LOW to Output Low-Z
-- Cyp_tOEV : TIME := 3.4 ns; -- OE# LOW to Output Valid
-- Cyp_tAS : TIME := 1.5 ns; -- Address Set-up Before CLK Rise
-- Cyp_tADS : TIME := 1.5 ns; -- ADSC#, ADSP# Set-up Before CLK Rise
-- Cyp_tADVS: TIME := 1.5 ns; -- ADV# Set-up Before CLK Rise
-- Cyp_tWES : TIME := 1.5 ns; -- BWx#, GW#, BWE# Set-up Before CLK Rise
-- Cyp_tDS : TIME := 1.5 ns; -- Data Input Set-up Before CLK Rise
-- Cyp_tCES : TIME := 1.5 ns; -- Chip Enable Set-up
-- Cyp_tAH : TIME := 0.5 ns; -- Address Hold After CLK Rise
-- Cyp_tADH : TIME := 0.5 ns; -- ADSC#, ADSP# Hold After CLK Rise
-- Cyp_tADVH: TIME := 0.5 ns; -- ADV# Hold After CLK Rise
-- Cyp_tWEH : TIME := 0.5 ns; -- BWx#, GW#, BWE# Hold After CLK Rise
-- Cyp_tDH : TIME := 0.5 ns; -- Data Input Hold After CLK Rise
-- Cyp_tCEH : TIME := 0.5 ns -- Chip Enable Hold After CLK Rise
--Clock timings for 133Mhz
-- Cyp_tCO : TIME := 4.2 ns; -- Data Output Valid After CLK Rise
-- Cyp_tCYC : TIME := 7.5 ns; -- Clock cycle time
-- Cyp_tCH : TIME := 2.5 ns; -- Clock HIGH time
-- Cyp_tCL : TIME := 2.5 ns; -- Clock LOW time
-- Cyp_tCHZ : TIME := 3.4 ns; -- Clock to High-Z
-- Cyp_tCLZ : TIME := 1.3 ns; -- Clock to Low-Z
-- Cyp_tOEHZ: TIME := 4.0 ns; -- OE# HIGH to Output High-Z
-- Cyp_tOELZ: TIME := 0.0 ns; -- OE# LOW to Output Low-Z
-- Cyp_tOEV : TIME := 4.2 ns; -- OE# LOW to Output Valid
-- Cyp_tAS : TIME := 1.5 ns; -- Address Set-up Before CLK Rise
-- Cyp_tADS : TIME := 1.5 ns; -- ADSC#, ADSP# Set-up Before CLK Rise
-- Cyp_tADVS: TIME := 1.5 ns; -- ADV# Set-up Before CLK Rise
-- Cyp_tWES : TIME := 1.5 ns; -- BWx#, GW#, BWE# Set-up Before CLK Rise
-- Cyp_tDS : TIME := 1.5 ns; -- Data Input Set-up Before CLK Rise
-- Cyp_tCES : TIME := 1.5 ns; -- Chip Enable Set-up
-- Cyp_tAH : TIME := 0.5 ns; -- Address Hold After CLK Rise
-- Cyp_tADH : TIME := 0.5 ns; -- ADSC#, ADSP# Hold After CLK Rise
-- Cyp_tADVH: TIME := 0.5 ns; -- ADV# Hold After CLK Rise
-- Cyp_tWEH : TIME := 0.5 ns; -- BWx#, GW#, BWE# Hold After CLK Rise
-- Cyp_tDH : TIME := 0.5 ns; -- Data Input Hold After CLK Rise
-- Cyp_tCEH : TIME := 0.5 ns -- Chip Enable Hold After CLK Rise
);
PORT (iZZ : IN STD_LOGIC;
iMode : IN STD_LOGIC;
iADDR : IN STD_LOGIC_VECTOR ((addr_bits -1) downto 0);
inGW : IN STD_LOGIC;
inBWE : IN STD_LOGIC;
inBWd : IN STD_LOGIC;
inBWc : IN STD_LOGIC;
inBWb : IN STD_LOGIC;
inBWa : IN STD_LOGIC;
inCE1 : IN STD_LOGIC;
iCE2 : IN STD_LOGIC;
inCE3 : IN STD_LOGIC;
inADSP : IN STD_LOGIC;
inADSC : IN STD_LOGIC;
inADV : IN STD_LOGIC;
inOE : IN STD_LOGIC;
ioDQ : INOUT STD_LOGIC_VECTOR ((data_bits-1) downto 0);
iCLK : IN STD_LOGIC);
end CY7C1380D;
ARCHITECTURE CY7C1380D_arch OF CY7C1380D IS
signal Read_reg_o1, Read_reg1 : STD_LOGIC;
signal WrN_reg1 : STD_LOGIC;
signal ADSP_N_o : STD_LOGIC;
signal pipe_reg1, ce_reg1,pcsr_write1, ctlr_write1 : STD_LOGIC;
signal Sys_clk : STD_LOGIC := '0';
signal test : STD_LOGIC;
signal dout, din1 : STD_LOGIC_VECTOR (data_bits-1 downto 0);
signal ce : STD_LOGIC;
signal Write_n : STD_LOGIC;
signal Read : STD_LOGIC;
signal bwa_n1 : STD_LOGIC;
signal bwb_n1 : STD_LOGIC;
signal bwc_n1 : STD_LOGIC;
signal bwd_n1 : STD_LOGIC;
signal latch_addr : STD_LOGIC;
signal addr_reg_read1,addr_reg_write1,addr_reg_in1 : STD_LOGIC_VECTOR (addr_bits-1 downto 0);
signal OeN_HZ : STD_LOGIC;
signal OeN_DataValid : STD_LOGIC;
signal OeN_efct : STD_LOGIC;
signal WR_HZ : STD_LOGIC;
signal WR_LZ : STD_LOGIC;
signal WR_efct : STD_LOGIC;
signal CE_HZ : STD_LOGIC;
signal CE_LZ : STD_LOGIC;
signal Pipe_efct : STD_LOGIC;
signal RD_HZ : STD_LOGIC;
signal RD_LZ : STD_LOGIC;
signal RD_efct : STD_LOGIC;
begin
ce <= ((not inCE1) and (iCE2) and (not inCE3));
Write_n <= not((((not inBWa) OR (not inBWb) OR (not inBWc) OR (not inBWd)) AND (not inBWE)) OR (not inGW));
Read <= (((inBWa AND inBWb AND inBWc AND inBWd) AND (not inBWE)) OR (inGW AND inBWE) OR (( not inADSP) AND ce));
bwa_n1 <= not((not Write_n) AND ((not inGW) OR ((not inBWE) AND (not inBWa))));
bwb_n1 <= not((not Write_n) AND ((not inGW) OR ((not inBWE) AND (not inBWb))));
bwc_n1 <= not((not Write_n) AND ((not inGW) OR ((not inBWE) AND (not inBWc))));
bwd_n1 <= not((not Write_n) AND ((not inGW) OR ((not inBWE) AND (not inBWd))));
latch_addr <= ((not inADSC) OR ((not inADSP) AND (not inCE1)));
OeN_efct <= OeN_DataValid when (inOE = '0') else OeN_HZ;
WR_efct <= WR_LZ when (WrN_reg1 = '0') else WR_HZ;
Pipe_efct <= CE_LZ when ((ce_reg1 = '1') and (pipe_reg1 = '1')) else CE_HZ;
RD_efct <= CE_LZ when (Read_reg_o1 = '1') else CE_HZ ;
Process (Read_reg_o1)
begin
if (Read_reg_o1 = '0') then
RD_HZ <= '0' after Cyp_tCHZ;
RD_LZ <= '0' after Cyp_tCLZ;
elsif (Read_reg_o1 = '1') then
RD_HZ <= '1' after Cyp_tCHZ;
RD_LZ <= '1' after Cyp_tCLZ;
else
RD_HZ <= 'X' after Cyp_tCHZ;
RD_LZ <= 'X' after Cyp_tCLZ;
end if;
end process;
Process (pipe_reg1)
begin
if (pipe_reg1 = '1') then
CE_LZ <= '1' after Cyp_tCLZ;
elsif (pipe_reg1 = '0') then
CE_LZ <= '0' after Cyp_tCLZ;
else
CE_LZ <= 'X' after Cyp_tCLZ;
end if;
end process;
-- System Clock Decode
Process (iclk)
variable Sys_clk1 : std_logic := '0';
begin
if (rising_edge (iclk)) then
Sys_clk1 := not iZZ;
end if;
if (falling_edge (iCLK)) then
Sys_clk1 := '0';
end if;
Sys_clk <= Sys_clk1;
end process;
Process (WrN_reg1)
begin
if (WrN_reg1 = '1') then
WR_HZ <= '1' after Cyp_tCHZ;
WR_LZ <= '1' after Cyp_tCLZ;
elsif (WrN_reg1 = '0') then
WR_HZ <= '0' after Cyp_tCHZ;
WR_LZ <= '0' after Cyp_tCLZ;
else
WR_HZ <= 'X' after Cyp_tCHZ;
WR_LZ <= 'X' after Cyp_tCLZ;
end if;
end process;
Process (inOE)
begin
if (inOE = '1') then
OeN_HZ <= '1' after Cyp_tOEHZ;
OeN_DataValid <= '1' after Cyp_tOEV;
elsif (inOE = '0') then
OeN_HZ <= '0' after Cyp_tOEHZ;
OeN_DataValid <= '0' after Cyp_tOEV;
else
OeN_HZ <= 'X' after Cyp_tOEHZ;
OeN_DataValid <= 'X' after Cyp_tOEV;
end if;
end process;
process (ce_reg1, pipe_reg1)
begin
if ((ce_reg1 = '0') or (pipe_reg1 = '0')) then
CE_HZ <= '0' after Cyp_tCHZ;
elsif ((ce_reg1 = '1') and (pipe_reg1 = '1')) then
CE_HZ <= '1' after Cyp_tCHZ;
else
CE_HZ <= 'X' after Cyp_tCHZ;
end if;
end process;
Process (Sys_clk)
TYPE memory_array IS ARRAY ((2**addr_bits -1) DOWNTO 0) OF STD_LOGIC_VECTOR ((data_bits/4) - 1 DOWNTO 0);
variable Read_reg_o : std_logic;
variable Read_reg : std_logic;
variable pcsr_write, ctlr_write : std_logic;
variable WrN_reg : std_logic;
variable latch_addr_old, latch_addr_current : std_logic;
variable addr_reg_in, addr_reg_read, addr_reg_write : std_logic_vector (addr_bits -1 downto 0) := (others => '0');
variable bcount, first_addr : std_logic_vector (1 downto 0) := "00";
variable bwa_reg,bwb_reg,bwc_reg,bwd_reg, pipe_reg, ce_reg : std_logic;
variable din : std_logic_vector (data_bits-1 downto 0);
variable first_addr_int : integer;
variable bank0 : memory_array;
variable bank1 : memory_array;
variable bank2 : memory_array;
variable bank3 : memory_array;
variable FIRST : boolean := true;
file TCF : text open read_mode is fname;
variable rectype : std_logic_vector(3 downto 0);
variable recaddr : std_logic_vector(31 downto 0);
variable reclen : std_logic_vector(7 downto 0);
variable recdata : std_logic_vector(0 to 16*8-1);
variable CH : character;
variable ai : integer := 0;
variable L1 : line;
begin
if FIRST then
L1:= new string'("");
while not endfile(TCF) loop
readline(TCF,L1);
if (L1'length /= 0) then
while (not (L1'length=0)) and (L1(L1'left) = ' ') loop
std.textio.read(L1,CH);
end loop;
if L1'length > 0 then
std.textio.read(L1, ch);
if (ch = 'S') or (ch = 's') then
hexread(L1, rectype);
hexread(L1, reclen);
recaddr := (others => '0');
case rectype is
when "0001" =>
hexread(L1, recaddr(15 downto 0));
when "0010" =>
hexread(L1, recaddr(23 downto 0));
when "0011" =>
hexread(L1, recaddr);
recaddr(31 downto 24) := (others => '0');
when others => next;
end case;
hexread(L1, recdata);
ai := conv_integer(recaddr)/4;
for i in 0 to 3 loop
bank3 (ai+i) := "0000" & recdata((i*32) to (i*32+4));
bank2 (ai+i) := recdata((i*32+5) to (i*32+13));
bank1 (ai+i) := recdata((i*32+14) to (i*32+22));
bank0 (ai+i) := recdata((i*32+23) to (i*32+31));
end loop;
end if;
end if;
end if;
end loop;
FIRST := false;
end if;
if rising_edge (Sys_clk) then
if (Write_n = '0') then
Read_reg_o := '0';
else
Read_reg_o := Read_reg;
end if;
if (Write_n = '0') then
Read_reg := '0';
else
Read_reg := Read;
end if;
Read_reg1 <= Read_reg;
Read_reg_o1 <= Read_reg_o;
if (Read_reg = '1') then
pcsr_write := '0';
ctlr_write := '0';
end if;
-- Write Register
if (Read_reg_o = '1') then
WrN_reg := '1';
else
WrN_reg := Write_n;
end if;
WrN_reg1 <= WrN_reg;
latch_addr_old := latch_addr_current;
latch_addr_current := latch_addr;
if (latch_addr_old = '1' and (Write_n = '0') and ADSP_N_o = '0') then
pcsr_write := '1'; --Ctlr Write = 0; Pcsr Write = 1;
elsif (latch_addr_current = '1' and (Write_n = '0') and inADSP = '1' and inADSC = '0') then
ctlr_write := '1'; --Ctlr Write = 0; Pcsr Write = 1;
end if;
-- ADDRess Register
if (latch_addr = '1') then
addr_reg_in := iADDR;
bcount := iADDR (1 downto 0);
first_addr := iADDR (1 downto 0);
end if;
addr_reg_in1 <= addr_reg_in;
-- ADSP_N Previous-Cycle Register
ADSP_N_o <= inADSP;
pcsr_write1 <= pcsr_write;
ctlr_write1 <= ctlr_write;
first_addr_int := CONV_INTEGER1 (first_addr);
-- Binary Counter and Logic
if ((iMode = '0') and (inADV = '0') and (latch_addr = '0')) then -- Linear Burst
bcount := (bcount + '1'); -- Advance Counter
elsif ((iMode = '1') and (inADV = '0') and (latch_addr = '0')) then -- Interleaved Burst
if ((first_addr_int REM 2) = 0) then
bcount := (bcount + '1'); -- Increment Counter
elsif ((first_addr_int REM 2) = 1) then
bcount := (bcount - '1'); -- Decrement Counter
end if;
end if;
-- Read ADDRess
addr_reg_read := addr_reg_write;
addr_reg_read1 <= addr_reg_read;
-- Write ADDRess
addr_reg_write := addr_reg_in ((addr_bits - 1) downto 2) & bcount(1) & bcount(0);
addr_reg_write1 <= addr_reg_write;
-- Byte Write Register
bwa_reg := not bwa_n1;
bwb_reg := not bwb_n1;
bwc_reg := not bwc_n1;
bwd_reg := not bwd_n1;
-- Enable Register
pipe_reg := ce_reg;
-- Enable Register
if (latch_addr = '1') then
ce_reg := ce;
end if;
pipe_reg1 <= pipe_reg;
ce_reg1 <= ce_reg;
-- Input Register
if ((ce_reg = '1') and ((bwa_n1 ='0') or (bwb_n1 = '0') or (bwc_n1 = '0') or (bwd_n1 = '0')) and
((pcsr_write = '1') or (ctlr_write = '1'))) then
din := ioDQ;
end if;
din1 <= din;
-- Byte Write Driver
if ((ce_reg = '1') and (bwa_reg = '1')) then
bank0 (CONV_INTEGER1 (addr_reg_write)) := din (8 downto 0);
end if;
if ((ce_reg = '1') and (bwb_reg = '1')) then
bank1 (CONV_INTEGER1 (addr_reg_write)) := din (17 downto 9);
end if;
if ((ce_reg = '1') and (bwc_reg = '1')) then
bank2 (CONV_INTEGER1 (addr_reg_write)) := din (26 downto 18);
end if;
if ((ce_reg = '1') and (bwd_reg = '1')) then
bank3 (CONV_INTEGER1 (addr_reg_write)) := din (35 downto 27);
end if;
-- Output Registers
if ((Write_n = '0') or (pipe_reg = '0')) then
dout (35 downto 0) <= "ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ" after Cyp_tCHZ;
elsif (Read_reg_o = '1') then
dout ( 8 downto 0) <= bank0 (CONV_INTEGER1 (addr_reg_read)) after Cyp_tCO;
dout (17 downto 9) <= bank1 (CONV_INTEGER1 (addr_reg_read)) after Cyp_tCO;
dout (26 downto 18) <= bank2 (CONV_INTEGER1 (addr_reg_read)) after Cyp_tCO;
dout (35 downto 27) <= bank3 (CONV_INTEGER1 (addr_reg_read)) after Cyp_tCO;
end if;
end if;
end process;
-- Output Buffers
ioDQ <= dout when ((inOE ='0') and (iZZ='0') and (Pipe_efct='1') and (RD_efct='1') and (WR_efct='1'))
else "ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ";
clk_check : PROCESS
VARIABLE clk_high, clk_low : TIME := 0 ns;
BEGIN
WAIT ON iClk;
IF iClk = '1' AND NOW >= Cyp_tCYC THEN
ASSERT (NOW - clk_low >= Cyp_tCH)
REPORT "Clk width low - tCH violation"
SEVERITY ERROR;
ASSERT (NOW - clk_high >= Cyp_tCYC)
REPORT "Clk period high - tCYC violation"
SEVERITY ERROR;
clk_high := NOW;
ELSIF iClk = '0' AND NOW /= 0 ns THEN
ASSERT (NOW - clk_high >= Cyp_tCL)
REPORT "Clk width high - tCL violation"
SEVERITY ERROR;
ASSERT (NOW - clk_low >= Cyp_tCYC)
REPORT "Clk period low - tCYC violation"
SEVERITY ERROR;
clk_low := NOW;
END IF;
END PROCESS;
-- Check for Setup Timing Violation
setup_check : PROCESS
BEGIN
WAIT ON iClk;
IF iClk = '1' THEN
ASSERT (iAddr'LAST_EVENT >= Cyp_tAS)
REPORT "Addr - tAS violation"
SEVERITY ERROR;
ASSERT (inGW'LAST_EVENT >= Cyp_tWES)
REPORT "GW# - tWES violation"
SEVERITY ERROR;
ASSERT (inBWE'LAST_EVENT >= Cyp_tWES)
REPORT "BWE# - tWES violation"
SEVERITY ERROR;
ASSERT (inCe1'LAST_EVENT >= Cyp_tWES)
REPORT "CE1# - tWES violation"
SEVERITY ERROR;
ASSERT (iCe2'LAST_EVENT >= Cyp_tWES)
REPORT "CE2 - tWES violation"
SEVERITY ERROR;
ASSERT (inCe3'LAST_EVENT >= Cyp_tWES)
REPORT "CE3# - tWES violation"
SEVERITY ERROR;
ASSERT (inAdv'LAST_EVENT >= Cyp_tADVS)
REPORT "ADV# - tWES violation"
SEVERITY ERROR;
ASSERT (inAdsp'LAST_EVENT >= Cyp_tADVS)
REPORT "ADSP# - tWES violation"
SEVERITY ERROR;
ASSERT (inAdsc'LAST_EVENT >= Cyp_tADVS)
REPORT "ADSC# - tWES violation"
SEVERITY ERROR;
ASSERT (inBwa'LAST_EVENT >= Cyp_tWES)
REPORT "BWa# - tWES violation"
SEVERITY ERROR;
ASSERT (inBwb'LAST_EVENT >= Cyp_tWES)
REPORT "BWb# - tWES violation"
SEVERITY ERROR;
ASSERT (inBwc'LAST_EVENT >= Cyp_tWES)
REPORT "BWc# - tWES violation"
SEVERITY ERROR;
ASSERT (inBwd'LAST_EVENT >= Cyp_tWES)
REPORT "BWd# - tWES violation"
SEVERITY ERROR;
ASSERT (ioDq'LAST_EVENT >= Cyp_tDS)
REPORT "Dq - tDS violation"
SEVERITY ERROR;
END IF;
END PROCESS;
-- Check for Hold Timing Violation
hold_check : PROCESS
BEGIN
WAIT ON iClk'DELAYED(Cyp_tAH), iClk'DELAYED(Cyp_tWEH), iClk'DELAYED(Cyp_tDH);
IF iClk'DELAYED(Cyp_tAH) = '1' THEN
ASSERT (iAddr'LAST_EVENT > Cyp_tAH)
REPORT "Addr - tAH violation"
SEVERITY ERROR;
END IF;
IF iClk'DELAYED(Cyp_tDH) = '1' THEN
ASSERT (ioDq'LAST_EVENT > Cyp_tDH)
REPORT "Dq - tDH violation"
SEVERITY ERROR;
END IF;
IF iClk'DELAYED(Cyp_tWEH) = '1' THEN
ASSERT (inCe1'LAST_EVENT > Cyp_tWEH)
REPORT "CE1# - tWEH violation"
SEVERITY ERROR;
ASSERT (iCe2'LAST_EVENT > Cyp_tWEH)
REPORT "CE2 - tWEH violation"
SEVERITY ERROR;
ASSERT (inCe3'LAST_EVENT > Cyp_tWEH)
REPORT "CE3 - tWEH violation"
SEVERITY ERROR;
ASSERT (inAdv'LAST_EVENT > Cyp_tWEH)
REPORT "ADV# - tWEH violation"
SEVERITY ERROR;
ASSERT (inADSP'LAST_EVENT > Cyp_tWEH)
REPORT "ADSP# - tWEH violation"
SEVERITY ERROR;
ASSERT (inADSC'LAST_EVENT > Cyp_tWEH)
REPORT "ADSC# - tWEH violation"
SEVERITY ERROR;
ASSERT (inBwa'LAST_EVENT > Cyp_tWEH)
REPORT "BWa# - tWEH violation"
SEVERITY ERROR;
ASSERT (inBwb'LAST_EVENT > Cyp_tWEH)
REPORT "BWb# - tWEH violation"
SEVERITY ERROR;
ASSERT (inBwc'LAST_EVENT > Cyp_tWEH)
REPORT "BWc# - tWEH violation"
SEVERITY ERROR;
ASSERT (inBwd'LAST_EVENT > Cyp_tWEH)
REPORT "BWd# - tWEH violation"
SEVERITY ERROR;
END IF;
END PROCESS;
end CY7C1380D_arch;
| mit | 50bd96cec4954f82d49e355bae42a9ef | 0.492782 | 3.407856 | false | false | false | false |
michaelfivez/ascon_hardware_implementation | ascon12864_unrolled6/API_plus_CipherCore/PreProcessor.vhd | 9 | 20,414 | -------------------------------------------------------------------------------
--! @file PreProcessor.vhd
--! @brief Pre-processing unit for an authenticated encryption module.
--! @project CAESAR Candidate Evaluation
--! @author Ekawat (ice) Homsirikamol
--! @copyright Copyright (c) 2015 Cryptographic Engineering Research Group
--! ECE Department, George Mason University Fairfax, VA, U.S.A.
--! All rights Reserved.
--! @license This project is released under the GNU Public License.
--! The license and distribution terms for this file may be
--! found in the file LICENSE in this distribution or at
--! http://www.gnu.org/licenses/gpl-3.0.txt
--! @note This is publicly available encryption source code that falls
--! under the License Exception TSU (Technology and software-
--! —unrestricted)
--!
--! SIPO used within this unit follows the following convention:
--! > Order in the test vector file (left to right): A(0) A(1) A(2) … A(N-1)
--! > Order at the SIPO input (time 0 to time N-1) : A(0) A(1) A(2) … A(N-1)
--! > Order at the SIPO output (left to right) : A(0) A(1) A(2) … A(N-1)
--! where A is a single I/O word.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.AEAD_pkg.all;
entity PreProcessor is
generic (
G_W : integer := 32; --! Public data width (bits)
G_SW : integer := 32; --! Secret data width (bits)
G_NPUB_SIZE : integer := 128; --! Npub width (bits)
G_NSEC_ENABLE : integer := 0; --! Enable NSEC port
G_NSEC_SIZE : integer := 128; --! Nsec width (bits)
G_ABLK_SIZE : integer := 128; --! Authenticated Data Block size (bits)
G_DBLK_SIZE : integer := 128; --! Data Block size (bits)
G_KEY_SIZE : integer := 128; --! Key size (bits)
G_RDKEY_ENABLE : integer := 0; --! Enable rdkey port (also disables key port)
G_RDKEY_SIZE : integer := 128; --! Roundkey size (bits)
G_TAG_SIZE : integer := 128; --! Tag size (bits)
G_BS_BYTES : integer := 4; --! The number of bits required to hold block size expressed in bytes = log2_ceil(max(G_ABLK_SIZE,G_DBLK_SIZE)/8)
G_LOADLEN_ENABLE : integer := 0; --! Enable load length section
G_PAD : integer := 1; --! Enable padding
G_PAD_STYLE : integer := 1; --! Padding style
G_PAD_AD : integer := 1; --! (G_PAD's sub option) Enable AD Padding
G_PAD_D : integer := 1; --! (G_PAD's sub option) Enable Data padding
G_CTR_AD_SIZE : integer := 16; --! Maximum size for the counter that keeps track of authenticated data
G_CTR_D_SIZE : integer := 16; --! Maximum size for the counter that keeps track of data
G_PLAINTEXT_MODE : integer := 0; --! Plaintext Mode
G_CIPHERTEXT_MODE : integer := 0; --! Ciphertext mode
G_REVERSE_DBLK : integer := 0 --! Reverse block order (for message only)
);
port (
--! =================
--! External Signals
--! =================
--! Global signals
clk : in std_logic;
rst : in std_logic;
--! Data in signals
pdi : in std_logic_vector(G_W -1 downto 0);
pdi_valid : in std_logic;
pdi_ready : out std_logic;
--! Key signals
sdi : in std_logic_vector(G_SW -1 downto 0);
sdi_valid : in std_logic;
sdi_ready : out std_logic;
--! =================
--! Crypto Core Signals
--! =================
--! Data signals
key : out std_logic_vector(G_KEY_SIZE -1 downto 0); --! Key data
rdkey : out std_logic_vector(G_RDKEY_SIZE -1 downto 0); --! Round key data
bdi : out std_logic_vector(G_DBLK_SIZE -1 downto 0); --! Block data
npub : out std_logic_vector(G_NPUB_SIZE -1 downto 0); --! Npub data
nsec : out std_logic_vector(G_NSEC_SIZE -1 downto 0); --! Nsec data
exp_tag : out std_logic_vector(G_TAG_SIZE -1 downto 0); --! Tag data
--! Info signals
len_a : out std_logic_vector(G_CTR_AD_SIZE -1 downto 0); --! Len of authenticated data in bytes (used for some algorithm)
len_d : out std_logic_vector(G_CTR_D_SIZE -1 downto 0); --! Len of data in bytes (used for some algorithm)
--! Control signals
key_ready : out std_logic; --! Indicates that the key is ready
key_needs_update : out std_logic; --! Indicates that the key needs update and should be acknowledge by the core via key_updated signal
key_updated : in std_logic; --! Key has been updated
rdkey_ready : out std_logic; --! (Optional) Round key ready
rdkey_read : in std_logic := '0'; --! (Optional) Round key read
npub_ready : out std_logic; --! (Optional) Npub ready
npub_read : in std_logic; --! (Optional) Npub read
nsec_ready : out std_logic; --! (Optional) Nsec ready
nsec_read : in std_logic := '0'; --! (Optional) Nsec read
bdi_ready : out std_logic; --! Block ready
bdi_proc : out std_logic; --! Block processing
bdi_ad : out std_logic; --! Input block is an authenticated data
bdi_nsec : out std_logic; --! Input block is a secret message number
bdi_decrypt : out std_logic; --! Decryption operation
bdi_pad : out std_logic; --! Last block of segment type contain padding
bdi_eot : out std_logic; --! Last block of segment type (end-of-type)
bdi_eoi : out std_logic; --! Last block of message (end-of-message)
bdi_nodata : out std_logic; --! Control signal indicating that there's no plain-text or authenticated data. The unit should generate a tag right away.
bdi_read : in std_logic; --! Handshake signal indicating that the data block has been read
bdi_size : out std_logic_vector(G_BS_BYTES -1 downto 0); --! Block size signal. Note: 0 = Full block.
bdi_valid_bytes : out std_logic_vector(G_DBLK_SIZE/8 -1 downto 0); --! Valid bytes
bdi_pad_loc : out std_logic_vector(G_DBLK_SIZE/8 -1 downto 0); --! PAD location
exp_tag_ready : out std_logic; --! Expected tag is ready
msg_auth_done : in std_logic; --! Message authentication completion signal
--! FIFO
bypass_fifo_full : in std_logic; --! An input signal indicating that the bypass FIFO is full
bypass_fifo_wr : out std_logic --! An output signal for writing data to bypass FIFO
);
end PreProcessor;
architecture structure of PreProcessor is
function isNPUBdisabled (a : integer ) return integer is
begin
if (a = 1 or a = 2) then
return 1;
else
return 0;
end if;
end function isNPUBdisabled;
function isKeyak (blksize: integer) return integer is
begin
if (G_DBLK_SIZE = 1344) then
return 1;
else
return 0;
end if;
end function isKeyak;
constant NPUB_DISABLE : integer := isNPUBdisabled(G_PLAINTEXT_MODE);
constant IS_KEYAK : integer := isKeyak(G_DBLK_SIZE);
signal en_data : std_logic;
signal en_npub : std_logic;
signal en_nsec : std_logic;
signal en_key : std_logic;
signal en_rdkey : std_logic;
signal sel_blank_pdi : std_logic;
signal clr_len : std_logic;
signal en_len_a_r : std_logic;
signal en_len_d_r : std_logic;
signal en_len_last_r : std_logic;
signal en_len_a : std_logic;
signal en_len_d : std_logic;
signal pad_enable : std_logic;
signal en_pad_loc : std_logic;
signal pad_eot : std_logic;
signal pad_eoi : std_logic;
signal pad_type_ad : std_logic;
signal pad_shift : std_logic_vector(log2_ceil(G_W/8) -1 downto 0);
signal size_dword : std_logic_vector(log2_ceil(G_W/8) downto 0);
signal en_exp_tag : std_logic;
signal sel_input : std_logic_vector(2 downto 0);
signal en_last_word : std_logic;
signal key_updated_sel : std_logic;
signal key_updated_int : std_logic;
begin
uDP: entity work.PreProcessor_Datapath(dataflow)
generic map (
G_W => G_W ,
G_SW => G_SW ,
G_CTR_AD_SIZE => G_CTR_AD_SIZE ,
G_CTR_D_SIZE => G_CTR_D_SIZE ,
G_DBLK_SIZE => G_DBLK_SIZE ,
G_KEY_SIZE => G_KEY_SIZE ,
G_KEYAK => IS_KEYAK ,
G_NPUB_DISABLE => NPUB_DISABLE ,
G_NPUB_SIZE => G_NPUB_SIZE ,
G_NSEC_ENABLE => G_NSEC_ENABLE ,
G_NSEC_SIZE => G_NSEC_SIZE ,
G_LOADLEN_ENABLE => G_LOADLEN_ENABLE ,
G_PAD => G_PAD ,
G_PAD_STYLE => G_PAD_STYLE ,
G_RDKEY_ENABLE => G_RDKEY_ENABLE ,
G_RDKEY_SIZE => G_RDKEY_SIZE ,
G_TAG_SIZE => G_TAG_SIZE
)
port map (
--! =================
--! External Signals
--! =================
--! Global signals
clk => clk ,
rst => rst ,
pdi => pdi ,
sdi => sdi ,
--! =================
--! Crypto Core Signals
--! =================
key_updated => key_updated_sel ,
key => key ,
rdkey => rdkey ,
bdi => bdi ,
npub => npub ,
nsec => nsec ,
len_a => len_a ,
len_d => len_d ,
exp_tag => exp_tag ,
bdi_valid_bytes => bdi_valid_bytes ,
bdi_pad_loc => bdi_pad_loc ,
--! =================
--! Internal Signals
--! =================
pad_shift => pad_shift ,
en_data => en_data ,
en_npub => en_npub ,
en_nsec => en_nsec ,
en_key => en_key ,
en_rdkey => en_rdkey ,
sel_blank_pdi => sel_blank_pdi ,
clr_len => clr_len ,
en_len_a_r => en_len_a_r ,
en_len_d_r => en_len_d_r ,
en_len_last_r => en_len_last_r ,
en_len_a => en_len_a ,
en_len_d => en_len_d ,
en_exp_tag => en_exp_tag ,
size_dword => size_dword ,
en_last_word => en_last_word ,
--! Pad related control
pad_eot => pad_eot ,
pad_eoi => pad_eoi ,
pad_type_ad => pad_type_ad ,
pad_enable => pad_enable ,
en_pad_loc => en_pad_loc ,
--! Supplmental control
sel_input => sel_input
);
uCtrl: entity work.PreProcessor_Control(behavior)
generic map (
G_W => G_W ,
G_SW => G_SW ,
G_CIPHERTEXT_MODE => G_CIPHERTEXT_MODE ,
G_PLAINTEXT_MODE => G_PLAINTEXT_MODE ,
G_ABLK_SIZE => G_ABLK_SIZE ,
G_DBLK_SIZE => G_DBLK_SIZE ,
G_BS_BYTES => G_BS_BYTES ,
G_KEY_SIZE => G_KEY_SIZE ,
G_NPUB_DISABLE => NPUB_DISABLE ,
G_NPUB_SIZE => G_NPUB_SIZE ,
G_NSEC_ENABLE => G_NSEC_ENABLE ,
G_NSEC_SIZE => G_NSEC_SIZE ,
G_RDKEY_ENABLE => G_RDKEY_ENABLE ,
G_RDKEY_SIZE => G_RDKEY_SIZE ,
G_REVERSE_DBLK => G_REVERSE_DBLK ,
G_LOADLEN_ENABLE => G_LOADLEN_ENABLE ,
G_CTR_AD_SIZE => G_CTR_AD_SIZE ,
G_CTR_D_SIZE => G_CTR_D_SIZE ,
G_PAD => G_PAD ,
G_PAD_AD => G_PAD_AD ,
G_PAD_D => G_PAD_D ,
G_TAG_SIZE => G_TAG_SIZE ,
G_KEYAK => IS_KEYAK
)
port map (
--! =================
--! External Signals
--! =================
--! Global signals
clk => clk ,
rst => rst ,
pdi => pdi ,
pdi_valid => pdi_valid ,
pdi_ready => pdi_ready ,
sdi => sdi ,
sdi_valid => sdi_valid ,
sdi_ready => sdi_ready ,
error => open ,
--! =================
--! Crypto Core Signals
--! =================
--! control signals
key_ready => key_ready ,
key_needs_update => key_needs_update ,
key_updated => key_updated_sel ,
rdkey_ready => rdkey_ready ,
rdkey_read => rdkey_read ,
npub_ready => npub_ready ,
npub_read => npub_read ,
nsec_read => nsec_read ,
nsec_ready => nsec_ready ,
bdi_ready => bdi_ready ,
bdi_proc => bdi_proc ,
bdi_ad => bdi_ad ,
bdi_nsec => bdi_nsec ,
bdi_decrypt => bdi_decrypt ,
bdi_pad => bdi_pad ,
bdi_eot => bdi_eot ,
bdi_eoi => bdi_eoi ,
bdi_nodata => bdi_nodata ,
bdi_read => bdi_read ,
bdi_size => bdi_size ,
bypass_fifo_full => bypass_fifo_full ,
bypass_fifo_wr => bypass_fifo_wr ,
exp_tag_ready => exp_tag_ready ,
msg_auth_done => msg_auth_done ,
--! =================
--! Internal Signals
--! =================
pad_shift => pad_shift ,
en_data => en_data ,
en_npub => en_npub ,
en_nsec => en_nsec ,
en_key => en_key ,
en_rdkey => en_rdkey ,
sel_blank_pdi => sel_blank_pdi ,
clr_len => clr_len ,
en_len_a_r => en_len_a_r ,
en_len_d_r => en_len_d_r ,
en_len_last_r => en_len_last_r ,
en_len_a => en_len_a ,
en_len_d => en_len_d ,
en_exp_tag => en_exp_tag ,
size_dword => size_dword ,
en_last_word => en_last_word ,
--! Pad related control
pad_eot => pad_eot ,
pad_eoi => pad_eoi ,
pad_type_ad => pad_type_ad ,
pad_enable => pad_enable ,
en_pad_loc => en_pad_loc ,
--! Supplmental control
key_updated_int => key_updated_int , --! Only used for Keyak
sel_input => sel_input
);
gKeyak1: if (IS_KEYAK = 1) generate
key_updated_sel <= key_updated_int;
end generate;
gKeyak0: if (IS_KEYAK = 0) generate
key_updated_sel <= key_updated;
end generate;
end structure;
| gpl-3.0 | 38c406cc990f167def2594de28e266a1 | 0.358375 | 4.74779 | false | false | false | false |
impedimentToProgress/UCI-BlueChip | AttackFiles/Attacks/privEsc/lib/gaisler/ambatest/ambatest.vhd | 2 | 20,524 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: ambatest
-- File: ambatest.vhd
-- Author: Alf Vaerneus
-- Description: Test package for emulators
------------------------------------------------------------------------------
-- pragma translate_off
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
library gaisler;
use grlib.devices.all;
use grlib.stdlib.all;
library std;
use std.textio.all;
package ambatest is
function printhex(value : std_logic_vector; len : integer) return string;
function conv_std_logic_vector(value : string; len : integer) return std_logic_vector;
function trimlen(str : string) return integer;
procedure printf(str : string; timestamp : boolean := false);
procedure printf(str : string; vari : integer; timestamp : boolean := false);
procedure printf(str : string; vari : std_logic_vector; timestamp : boolean := false);
procedure printf(str : string; vari : string; timestamp : boolean := false);
procedure compfiles(file1 : string(18 downto 1); file2 : string(18 downto 1); format : integer);
procedure compfiles(file1 : string(18 downto 1); file2 : string(18 downto 1); format : integer; printlvl : integer; err : out boolean);
type command_type is (RD_SINGLE,
RD_INCR,
RD_WRAP4,
RD_INCR4,
RD_WRAP8,
RD_INCR8,
RD_WRAP16,
RD_INCR16,
WR_SINGLE,
WR_INCR,
WR_WRAP4,
WR_INCR4,
WR_WRAP8,
WR_INCR8,
WR_WRAP16,
WR_INCR16,
M_READ,
M_READ_LINE,
M_READ_MULT,
M_WRITE,
M_WRITE_INV,
C_READ,
C_WRITE,
I_READ,
I_WRITE
);
constant MAX_NO_TB : integer := 20;
type tb_in_type is record
address : std_logic_vector(31 downto 0);
data : std_logic_vector(31 downto 0);
start : std_logic;
command : command_type;
no_words : natural;
userfile : boolean;
usewfile : boolean;
rfile : string(18 downto 1);
wfile : string(18 downto 1);
end record;
type tbi_array_type is array(0 to MAX_NO_TB) of tb_in_type;
type status_type is (OK, ERR, TIMEOUT, RETRY);
type tb_out_type is record
data : std_logic_vector(31 downto 0);
ready : std_logic;
status : status_type;
end record;
type tbo_array_type is array(0 to MAX_NO_TB) of tb_out_type;
type ctrl_type is record
address : std_logic_vector(31 downto 0);
data : std_logic_vector(31 downto 0);
status : status_type;
curword : natural;
no_words : natural;
userfile : boolean;
usewfile : boolean;
rfile : string(18 downto 1);
wfile : string(18 downto 1);
end record;
constant tb_in_init : tb_in_type := (
address => (others => '0'),
data => (others => '0'),
start => '0',
command => RD_SINGLE,
no_words => 0,
userfile => false,
usewfile => false,
rfile => " ",
wfile => " ");
constant ctrl_init : ctrl_type := (
address => (others => '0'),
data => (others => '0'),
status => OK,
curword => 0,
no_words => 1,
userfile => false,
usewfile => false,
rfile => " ",
wfile => " ");
constant AHB_IDLE : ahb_mst_out_type := (
hbusreq => '0',
hlock => '0',
htrans => HTRANS_IDLE,
haddr => (others => '0'),
hwrite => '0',
hsize => HSIZE_WORD,
hburst => HBURST_SINGLE,
hprot => (others => '0'),
hwdata => (others => '0'),
hirq => (others => '0'),
hconfig => (others => zero32),
hindex => 0
);
constant READ_SINGLE : ahb_mst_out_type := (
hbusreq => '0',
hlock => '0',
htrans => HTRANS_NONSEQ,
haddr => (others => '0'),
hwrite => '0',
hsize => HSIZE_WORD,
hburst => HBURST_SINGLE,
hprot => (others => '0'),
hwdata => (others => '0'),
hirq => (others => '0'),
hconfig => (others => zero32),
hindex => 0
);
constant READ_INCR : ahb_mst_out_type := (
hbusreq => '0',
hlock => '0',
htrans => HTRANS_NONSEQ,
haddr => (others => '0'),
hwrite => '0',
hsize => HSIZE_WORD,
hburst => HBURST_INCR,
hprot => (others => '0'),
hwdata => (others => '0'),
hirq => (others => '0'),
hconfig => (others => zero32),
hindex => 0
);
constant WRITE_SINGLE : ahb_mst_out_type := (
hbusreq => '0',
hlock => '0',
htrans => HTRANS_NONSEQ,
haddr => (others => '0'),
hwrite => '1',
hsize => HSIZE_WORD,
hburst => HBURST_SINGLE,
hprot => (others => '0'),
hwdata => (others => '0'),
hirq => (others => '0'),
hconfig => (others => zero32),
hindex => 0
);
constant WRITE_INCR : ahb_mst_out_type := (
hbusreq => '0',
hlock => '0',
htrans => HTRANS_NONSEQ,
haddr => (others => '0'),
hwrite => '1',
hsize => HSIZE_WORD,
hburst => HBURST_INCR,
hprot => (others => '0'),
hwdata => (others => '0'),
hirq => (others => '0'),
hconfig => (others => zero32),
hindex => 0
);
-- AHB Master Emulator
component ahbmst_em
generic(
hindex : integer := 0;
timeoutc : integer := 100;
dbglevel : integer := 2
);
port(
rst : in std_logic;
clk : in std_logic;
-- AMBA signals
ahbmi : in ahb_mst_in_type;
ahbmo : out ahb_mst_out_type;
-- TB signals
tbi : in tb_in_type;
tbo : out tb_out_type
);
end component;
-- AHB Slave Emulator
component ahbslv_em
generic(
hindex : integer := 0;
abits : integer := 10;
waitcycles : integer := 2;
retries : integer := 0;
memaddr : integer := 16#E00#;
memmask : integer := 16#FFF#;
ioaddr : integer := 16#000#;
timeoutc : integer := 100;
dbglevel : integer := 2
);
port(
rst : in std_logic;
clk : in std_logic;
-- AMBA signals
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
-- TB signals
tbi : in tb_in_type;
tbo : out tb_out_type
);
end component;
end ambatest;
package body ambatest is
function printhex( value : std_logic_vector; len : integer) return string is
variable str1, str2 : string (1 to 8);
variable stmp : string (8 downto 1);
variable x : std_logic_vector(31 downto 0);
begin
x:= (others => '0');
x(len-1 downto 0) := value;
case len is
when 4 | 8 | 12 | 16 | 20 | 24 | 28 | 32 =>
for i in 0 to (len/4)-1 loop
case conv_integer(x(((len-1)-(i*4)) downto ((len-1)-(i*4)-3))) is
when 0 => stmp(i+1) := '0';
when 1 => stmp(i+1) := '1';
when 2 => stmp(i+1) := '2';
when 3 => stmp(i+1) := '3';
when 4 => stmp(i+1) := '4';
when 5 => stmp(i+1) := '5';
when 6 => stmp(i+1) := '6';
when 7 => stmp(i+1) := '7';
when 8 => stmp(i+1) := '8';
when 9 => stmp(i+1) := '9';
when 10 => stmp(i+1) := 'A';
when 11 => stmp(i+1) := 'B';
when 12 => stmp(i+1) := 'C';
when 13 => stmp(i+1) := 'D';
when 14 => stmp(i+1) := 'E';
when 15 => stmp(i+1) := 'F';
when others => stmp(i+1) := 'X';
end case;
end loop;
when others => stmp := (others => ' ');
end case;
str2(1 to 8) := stmp(8 downto 1);
for i in 1 to 8 loop
str1(i) := str2(9-i);
end loop;
return(str1);
end printhex;
function to_char( x : INTEGER range 0 to 15) return character is
begin
case x is
when 0 => return('0');
when 1 => return('1');
when 2 => return('2');
when 3 => return('3');
when 4 => return('4');
when 5 => return('5');
when 6 => return('6');
when 7 => return('7');
when 8 => return('8');
when 9 => return('9');
when 10 => return('A');
when 11 => return('B');
when 12 => return('C');
when 13 => return('D');
when 14 => return('E');
when 15 => return('F');
end case;
end to_char;
function conv_std_logic_vector(value : string; len : integer) return std_logic_vector is
variable tmpvect : std_logic_vector(31 downto 0);
variable str1,str2 : string(1 to 8);
begin
str1 := value;
for i in 1 to (len/4) loop
str2(i) := str1(((len/4)+1)-i);
end loop;
case len is
when 4 | 8 | 12 | 16 | 20 | 24 | 28 | 32 =>
for i in 0 to 7 loop
case str2(i+1) is
when '0' => tmpvect(((i*4)+3) downto (i*4)) := "0000";
when '1' => tmpvect(((i*4)+3) downto (i*4)) := "0001";
when '2' => tmpvect(((i*4)+3) downto (i*4)) := "0010";
when '3' => tmpvect(((i*4)+3) downto (i*4)) := "0011";
when '4' => tmpvect(((i*4)+3) downto (i*4)) := "0100";
when '5' => tmpvect(((i*4)+3) downto (i*4)) := "0101";
when '6' => tmpvect(((i*4)+3) downto (i*4)) := "0110";
when '7' => tmpvect(((i*4)+3) downto (i*4)) := "0111";
when '8' => tmpvect(((i*4)+3) downto (i*4)) := "1000";
when '9' => tmpvect(((i*4)+3) downto (i*4)) := "1001";
when 'A' => tmpvect(((i*4)+3) downto (i*4)) := "1010";
when 'B' => tmpvect(((i*4)+3) downto (i*4)) := "1011";
when 'C' => tmpvect(((i*4)+3) downto (i*4)) := "1100";
when 'D' => tmpvect(((i*4)+3) downto (i*4)) := "1101";
when 'E' => tmpvect(((i*4)+3) downto (i*4)) := "1110";
when 'F' => tmpvect(((i*4)+3) downto (i*4)) := "1111";
when 'a' => tmpvect(((i*4)+3) downto (i*4)) := "1010";
when 'b' => tmpvect(((i*4)+3) downto (i*4)) := "1011";
when 'c' => tmpvect(((i*4)+3) downto (i*4)) := "1100";
when 'd' => tmpvect(((i*4)+3) downto (i*4)) := "1101";
when 'e' => tmpvect(((i*4)+3) downto (i*4)) := "1110";
when 'f' => tmpvect(((i*4)+3) downto (i*4)) := "1111";
when others => tmpvect(((i*4)+3) downto (i*4)) := "0000";
end case;
end loop;
when others => tmpvect := (others => '0');
end case;
return(tmpvect(len-1 downto 0));
end conv_std_logic_vector;
procedure printf(str : string; timestamp : boolean := false) is
variable lenstr,offset,i : integer;
variable rstr : string(1 to 128);
variable L : line;
begin
lenstr := str'length; offset := 1; i := 1;
while i <= lenstr loop
rstr(offset) := str(i); offset := offset+1; i := i+1;
end loop;
rstr(offset+1) := NUL;
if timestamp then
write(L, rstr & " : ");
write(L, Now, Left, 15);
else
write(L,rstr);
end if;
writeline(output,L);
end procedure;
procedure printf(str : string; vari : integer; timestamp : boolean := false) is
variable lenstr,offset,i,j,x,y,z : integer;
variable rstr : string(1 to 128);
variable tmpstr : string(1 to 8);
variable remzer : boolean;
variable L : line;
begin
lenstr := str'length; offset := 1; i := 1; x := vari;
while i <= lenstr loop
if str(i) = '%' then
if vari = 0 then
rstr(offset) := '0'; offset := offset+1;
else
if vari = 0 then tmpstr := (others => '0');
else
j := 8;
l2: while true loop
j := j-1;
exit l2 when j = 0;
y := x/10;
z := x - y*10;
x := y;
tmpstr(j) := to_char(z);
end loop;
if x>0 then printf("Value is out of range"); end if;
end if;
-- tmpstr := printhex(conv_std_logic_vector(vari,32),32);
remzer := false;
for k in 1 to 8 loop
if (tmpstr(k) /= '0' or remzer = true) then
rstr(offset) := tmpstr(k); remzer := true; offset := offset+1;
end if;
end loop;
end if;
i := i+2;
else
rstr(offset) := str(i); offset := offset+1; i := i+1;
end if;
end loop;
rstr(offset+1) := NUL;
if timestamp then
write(L, rstr & " : ");
write(L, Now, Left, 15);
else
write(L,rstr);
end if;
writeline(output,L);
end procedure;
procedure printf(
str : string;
vari : std_logic_vector;
timestamp : boolean := false) is
constant zero32 : std_logic_vector(31 downto 0) := (others => '0');
variable lenstr,lenvct,offset,i : integer;
variable rstr : string(1 to 128);
variable tmpstr : string(1 to 8);
variable L : line;
begin
lenstr := str'length; offset := 1;
lenvct := vari'length; i := 1;
while i <= lenstr loop
if str(i) = '%' then
if vari = zero32(lenvct-1 downto 0) then
rstr(offset) := '0'; offset := offset+1;
else
tmpstr := printhex(vari,lenvct);
for j in 1 to 8 loop
rstr(offset) := tmpstr(j); offset := offset+1;
end loop;
end if;
i := i+2;
else
rstr(offset) := str(i); offset := offset+1; i := i+1;
end if;
end loop;
rstr(offset+1) := NUL;
if timestamp then
write(L, rstr & " : ");
write(L, Now, Left, 15);
else
write(L,rstr);
end if;
writeline(output,L);
end procedure;
function trimlen(str : string) return integer is
variable lenstr,i : integer;
begin
lenstr := str'length; i := 1;
while str(lenstr) /= ' ' loop
i := i+1 ; lenstr := lenstr-1;
end loop;
return(lenstr+1);
end function;
procedure printf(
str : string;
vari : string;
timestamp : boolean := false) is
variable lenstr,lenvct,offset,i : integer;
variable rstr : string(1 to 128);
variable L : line;
begin
lenstr := str'length; offset := 1;
lenvct := vari'length; i := 1;
while i <= lenstr loop
if str(i) = '%' then
for j in 1 to lenvct loop
rstr(offset) := vari(j); offset := offset+1;
end loop;
i := i+2;
else
rstr(offset) := str(i); offset := offset+1; i := i+1;
end if;
end loop;
rstr(offset+1) := NUL;
if timestamp then
write(L, rstr & " : ");
write(L, Now, Left, 15);
else
write(L,rstr);
end if;
writeline(output,L);
end procedure;
procedure compfiles(
file1 : string(18 downto 1);
file2 : string(18 downto 1);
format : integer) is
file comp1, comp2 : text;
variable L1, L2 : line;
variable datahex1, datahex2 : string(1 to 8);
variable dataint1, dataint2, pos, errs : integer;
begin
pos := 0; errs := 0;
file_open(comp1, external_name => file1(18 downto trimlen(file1)), open_kind => read_mode);
file_open(comp2, external_name => file2(18 downto trimlen(file2)), open_kind => read_mode);
readline(comp1,L1);
readline(comp2,L2);
pos := pos+1;
if format = 0 then
read(L1,dataint1);
read(L2,dataint2);
if dataint1 /= dataint2 then
errs := errs+1;
printf("Comparision error at pos. %d",pos);
printf("Expected data: %d",dataint1);
printf("Compared data: %d",dataint2);
end if;
elsif format = 1 then
read(L1,datahex1);
read(L2,datahex2);
if conv_std_logic_vector(datahex1,32) /= conv_std_logic_vector(datahex2,32) then
errs := errs+1;
printf("Comparision error at pos. %d",pos);
printf("Expected data: %x",datahex1);
printf("Compared data: %x",datahex2);
end if;
end if;
while not (endfile(comp1) or endfile(comp2)) loop
readline(comp1,L1);
readline(comp2,L2);
pos := pos+1;
if format = 0 then
read(L1,dataint1);
read(L2,dataint2);
if dataint1 /= dataint2 then
errs := errs+1;
printf("Comparision error at pos. %d",pos);
printf("Expected data: %d",dataint1);
printf("Compared data: %d",dataint2);
end if;
elsif format = 1 then
read(L1,datahex1);
read(L2,datahex2);
if conv_std_logic_vector(datahex1,32) /= conv_std_logic_vector(datahex2,32) then
errs := errs+1;
printf("Comparision error at pos. %d",pos);
printf("Expected data: %x",datahex1);
printf("Compared data: %x",datahex2);
end if;
end if;
end loop;
if endfile(comp1) /= endfile(comp2) then
printf("Compared files have different size!"); errs := errs+1;
end if;
file_close(comp1); file_close(comp2);
if errs = 0 then
printf("Comparision complete. No failure.");
elsif errs = 1 then
printf("Comparision complete. 1 failure.");
else
printf("Comparision complete. %d failures.",errs);
end if;
end procedure;
procedure compfiles(file1 : string(18 downto 1); file2 : string(18 downto 1); format : integer; printlvl : integer; err : out boolean) is
file comp1, comp2 : text;
variable L1, L2 : line;
variable datahex1, datahex2 : string(1 to 8);
variable dataint1, dataint2, pos, errs : integer;
begin
pos := 0; errs := 0;
file_open(comp1, external_name => file1(18 downto trimlen(file1)), open_kind => read_mode);
file_open(comp2, external_name => file2(18 downto trimlen(file2)), open_kind => read_mode);
readline(comp1,L1);
readline(comp2,L2);
pos := pos+1;
if format = 0 then
read(L1,dataint1);
read(L2,dataint2);
if dataint1 /= dataint2 then
errs := errs+1;
if printlvl /= 0 then
printf("Comparision error at pos. %d",pos);
printf("Expected data: %d",dataint1);
printf("Compared data: %d",dataint2);
end if;
end if;
elsif format = 1 then
read(L1,datahex1);
read(L2,datahex2);
if conv_std_logic_vector(datahex1,32) /= conv_std_logic_vector(datahex2,32) then
errs := errs+1;
if printlvl /= 0 then
printf("Comparision error at pos. %d",pos);
printf("Expected data: %x",datahex1);
printf("Compared data: %x",datahex2);
end if;
end if;
end if;
while not (endfile(comp1) or endfile(comp2)) loop
readline(comp1,L1);
readline(comp2,L2);
pos := pos+1;
if format = 0 then
read(L1,dataint1);
read(L2,dataint2);
if dataint1 /= dataint2 then
errs := errs+1;
if printlvl /= 0 then
printf("Comparision error at pos. %d",pos);
printf("Expected data: %d",dataint1);
printf("Compared data: %d",dataint2);
end if;
end if;
elsif format = 1 then
read(L1,datahex1);
read(L2,datahex2);
if conv_std_logic_vector(datahex1,32) /= conv_std_logic_vector(datahex2,32) then
errs := errs+1;
if printlvl /= 0 then
printf("Comparision error at pos. %d",pos);
printf("Expected data: %x",datahex1);
printf("Compared data: %x",datahex2);
end if;
end if;
end if;
end loop;
if endfile(comp1) /= endfile(comp2) then
if printlvl /= 0 then
printf("Compared files have different size!"); errs := errs+1;
end if;
end if;
file_close(comp1); file_close(comp2);
err := true;
if errs = 0 then
err := false;
if printlvl >= 2 then
printf("Comparision complete. No failure.");
end if;
elsif errs = 1 then
if printlvl >= 1 then
printf("Comparision complete. 1 failure.");
end if;
else
if printlvl >= 1 then
printf("Comparision complete. %d failures.",errs);
end if;
end if;
end procedure;
end ambatest;
-- pragma translate_on
| mit | ff19690cdca9eae0ba12d4d519ec30f9 | 0.533132 | 3.328036 | false | false | false | false |
cafe-alpha/wascafe | v11/fpga_firmware/wasca_toplevel.vhd | 1 | 13,482 | -- wasca.vhd
-- Generated using ACDS version 14.1 186 at 2015.05.28.08:37:08
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity wasca_toplevel is
port (
clk_clk : in std_logic := '0'; -- clk.clk
external_sdram_controller_wire_addr : out std_logic_vector(12 downto 0); -- external_sdram_controller_wire.addr
external_sdram_controller_wire_ba : out std_logic_vector(1 downto 0); -- .ba
external_sdram_controller_wire_cas_n : out std_logic; -- .cas_n
external_sdram_controller_wire_cke : out std_logic; -- .cke
external_sdram_controller_wire_cs_n : out std_logic; -- .cs_n
external_sdram_controller_wire_dq : inout std_logic_vector(15 downto 0) := (others => '0'); -- .dq
external_sdram_controller_wire_dqm : out std_logic_vector(1 downto 0); -- .dqm
external_sdram_controller_wire_ras_n : out std_logic; -- .ras_n
external_sdram_controller_wire_we_n : out std_logic; -- .we_n
external_sdram_controller_wire_clk : out std_logic; -- .clk
reset_reset_n : in std_logic := '0'; -- reset.reset_n
sega_saturn_abus_slave_0_abus_address : in std_logic_vector(25 downto 16) := (others => '0'); -- sega_saturn_abus_slave_0_abus.address
sega_saturn_abus_slave_0_abus_addressdata : inout std_logic_vector(15 downto 0) := (others => '0'); -- .data
sega_saturn_abus_slave_0_abus_chipselect : in std_logic_vector(2 downto 0) := (others => '0'); -- .chipselect
sega_saturn_abus_slave_0_abus_read : in std_logic := '0'; -- .read
sega_saturn_abus_slave_0_abus_write : in std_logic_vector(1 downto 0) := (others => '0'); -- .write
sega_saturn_abus_slave_0_abus_waitrequest : out std_logic; -- .waitrequest
sega_saturn_abus_slave_0_abus_interrupt : out std_logic := '0'; -- .interrupt
sega_saturn_abus_slave_0_abus_disableout : out std_logic := '0'; -- .muxing
sega_saturn_abus_slave_0_abus_muxing : out std_logic_vector(1 downto 0) := (others => '0'); -- .muxing
sega_saturn_abus_slave_0_abus_direction : out std_logic := '0'; -- .direction
spi_sd_card_MISO : in std_logic := '0'; -- MISO
spi_sd_card_MOSI : out std_logic; -- MOSI
spi_sd_card_SCLK : out std_logic; -- SCLK
spi_sd_card_SS_n : out std_logic; -- SS_n
uart_0_external_connection_txd : out std_logic := '0' ;
spi_stm32_MISO : out std_logic; -- MISO
spi_stm32_MOSI : in std_logic := '0'; -- MOSI
spi_stm32_SCLK : in std_logic := '0'; -- SCLK
spi_stm32_SS_n : in std_logic := '0'; -- SS_n
audio_out_BCLK : in std_logic := '0'; -- BCLK
audio_out_DACDAT : out std_logic; -- DACDAT
audio_out_DACLRCK : in std_logic := '0'; -- DACLRCK
audio_SSEL : out std_logic := '0'
);
end entity wasca_toplevel;
architecture rtl of wasca_toplevel is
component wasca is
port (
altpll_0_areset_conduit_export : in std_logic := '0'; -- altpll_0_areset_conduit.export
altpll_0_locked_conduit_export : out std_logic; -- altpll_0_locked_conduit.export
altpll_0_phasedone_conduit_export : out std_logic; -- altpll_0_phasedone_conduit.export
clk_clk : in std_logic := '0'; -- clk.clk
clock_116_mhz_clk : out std_logic ; -- cl
external_sdram_controller_wire_addr : out std_logic_vector(12 downto 0); -- external_sdram_controller_wire.addr
external_sdram_controller_wire_ba : out std_logic_vector(1 downto 0); -- .ba
external_sdram_controller_wire_cas_n : out std_logic; -- .cas_n
external_sdram_controller_wire_cke : out std_logic; -- .cke
external_sdram_controller_wire_cs_n : out std_logic; -- .cs_n
external_sdram_controller_wire_dq : inout std_logic_vector(15 downto 0) := (others => '0'); -- .dq
external_sdram_controller_wire_dqm : out std_logic_vector(1 downto 0); -- .dqm
external_sdram_controller_wire_ras_n : out std_logic; -- .ras_n
external_sdram_controller_wire_we_n : out std_logic; -- .we_n
sega_saturn_abus_slave_0_abus_address : in std_logic_vector(9 downto 0) := (others => '0'); -- sega_saturn_abus_slave_0_abus.address
sega_saturn_abus_slave_0_abus_chipselect : in std_logic_vector(2 downto 0) := (others => '0'); -- .chipselect
sega_saturn_abus_slave_0_abus_read : in std_logic := '0'; -- .read
sega_saturn_abus_slave_0_abus_write : in std_logic_vector(1 downto 0) := (others => '0'); -- .write
sega_saturn_abus_slave_0_abus_waitrequest : out std_logic; -- .waitrequest
sega_saturn_abus_slave_0_abus_interrupt : out std_logic := '0'; -- .interrupt
sega_saturn_abus_slave_0_abus_addressdata : inout std_logic_vector(15 downto 0) := (others => '0'); -- .writedata
sega_saturn_abus_slave_0_abus_direction : out std_logic := '0';
sega_saturn_abus_slave_0_abus_muxing : out std_logic_vector(1 downto 0) := (others => '0');
sega_saturn_abus_slave_0_abus_disableout : out std_logic := '0' ; -- .muxing
sega_saturn_abus_slave_0_conduit_saturn_reset_saturn_reset : in std_logic := '0'; -- saturn_reset
spi_sd_card_MISO : in std_logic := '0'; -- MISO
spi_sd_card_MOSI : out std_logic; -- MOSI
spi_sd_card_SCLK : out std_logic; -- SCLK
spi_sd_card_SS_n : out std_logic; -- SS_n
uart_0_external_connection_rxd : in std_logic := '0'; -- rxd
uart_0_external_connection_txd : out std_logic; -- txd
spi_stm32_MISO : out std_logic; -- MISO
spi_stm32_MOSI : in std_logic := '0'; -- MOSI
spi_stm32_SCLK : in std_logic := '0'; -- SCLK
spi_stm32_SS_n : in std_logic := '0'; -- SS_n
audio_out_BCLK : in std_logic := '0'; -- BCLK
audio_out_DACDAT : out std_logic; -- DACDAT
audio_out_DACLRCK : in std_logic := '0' -- DACLRCK
);
end component;
--signal altpll_0_areset_conduit_export : std_logic := '0';
signal altpll_0_locked_conduit_export : std_logic := '0';
--signal altpll_0_phasedone_conduit_export : std_logic := '0';
--signal sega_saturn_abus_slave_0_abus_address_demuxed : std_logic_vector(25 downto 0) := (others => '0');
--signal sega_saturn_abus_slave_0_abus_data_demuxed : std_logic_vector(15 downto 0) := (others => '0');
signal clock_116_mhz : std_logic := '0';
begin
--sega_saturn_abus_slave_0_abus_muxing (0) <= not sega_saturn_abus_slave_0_abus_muxing(1);
external_sdram_controller_wire_clk <= clock_116_mhz;
my_little_wasca : component wasca
port map (
clk_clk => clk_clk,
clock_116_mhz_clk => clock_116_mhz,
external_sdram_controller_wire_addr => external_sdram_controller_wire_addr,
external_sdram_controller_wire_ba => external_sdram_controller_wire_ba,
external_sdram_controller_wire_cas_n => external_sdram_controller_wire_cas_n,
external_sdram_controller_wire_cke => external_sdram_controller_wire_cke,
external_sdram_controller_wire_cs_n => external_sdram_controller_wire_cs_n,
external_sdram_controller_wire_dq => external_sdram_controller_wire_dq,
external_sdram_controller_wire_dqm => external_sdram_controller_wire_dqm,
external_sdram_controller_wire_ras_n => external_sdram_controller_wire_ras_n,
external_sdram_controller_wire_we_n => external_sdram_controller_wire_we_n,
sega_saturn_abus_slave_0_abus_address => sega_saturn_abus_slave_0_abus_address,
sega_saturn_abus_slave_0_abus_chipselect => "1"&sega_saturn_abus_slave_0_abus_chipselect(1 downto 0),--work only with CS1 and CS0 for now
sega_saturn_abus_slave_0_abus_read => sega_saturn_abus_slave_0_abus_read,
sega_saturn_abus_slave_0_abus_write => sega_saturn_abus_slave_0_abus_write,
sega_saturn_abus_slave_0_abus_waitrequest => sega_saturn_abus_slave_0_abus_waitrequest,
sega_saturn_abus_slave_0_abus_interrupt => sega_saturn_abus_slave_0_abus_interrupt,
sega_saturn_abus_slave_0_abus_addressdata => sega_saturn_abus_slave_0_abus_addressdata,
sega_saturn_abus_slave_0_abus_direction => sega_saturn_abus_slave_0_abus_direction,
sega_saturn_abus_slave_0_abus_muxing => sega_saturn_abus_slave_0_abus_muxing,
sega_saturn_abus_slave_0_abus_disableout => sega_saturn_abus_slave_0_abus_disableout,
sega_saturn_abus_slave_0_conduit_saturn_reset_saturn_reset => reset_reset_n,
spi_sd_card_MISO => spi_sd_card_MISO,
spi_sd_card_MOSI => spi_sd_card_MOSI,
spi_sd_card_SCLK => spi_sd_card_SCLK,
spi_sd_card_SS_n => spi_sd_card_SS_n,
altpll_0_areset_conduit_export => open,
altpll_0_locked_conduit_export => altpll_0_locked_conduit_export,
altpll_0_phasedone_conduit_export => open,
uart_0_external_connection_rxd => '0',
uart_0_external_connection_txd => uart_0_external_connection_txd,
spi_stm32_MISO => spi_stm32_MISO,
spi_stm32_MOSI => spi_stm32_MOSI,
spi_stm32_SCLK => spi_stm32_SCLK,
spi_stm32_SS_n => spi_stm32_SS_n,
audio_out_BCLK => audio_out_BCLK,
audio_out_DACDAT => audio_out_DACDAT,
audio_out_DACLRCK => audio_out_DACLRCK
);
audio_SSEL <= '0';
--sega_saturn_abus_slave_0_abus_waitrequest <= '1';
--sega_saturn_abus_slave_0_abus_direction <= '0';
--sega_saturn_abus_slave_0_abus_muxing <= "01";
end architecture rtl; -- of wasca_toplevel
| gpl-2.0 | 695a38c4cf70ab8fc9eacd17342efdd8 | 0.445928 | 4.010113 | false | false | false | false |
michaelfivez/ascon_hardware_implementation | ascon12864_unrolled6/Kernel/Ascon_block_datapath.vhd | 1 | 6,151 | -------------------------------------------------------------------------------
--! @project Unrolled (6) hardware implementation of Asconv1286
--! @author Michael Fivez
--! @license This project is released under the GNU Public License.
--! The license and distribution terms for this file may be
--! found in the file LICENSE in this distribution or at
--! http://www.gnu.org/licenses/gpl-3.0.txt
--! @note This is an hardware implementation made for my graduation thesis
--! at the KULeuven, in the COSIC department (year 2015-2016)
--! The thesis is titled 'Energy efficient hardware implementations of CAESAR submissions',
--! and can be found on the COSIC website (www.esat.kuleuven.be/cosic/publications)
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity Ascon_StateUpdate_datapath is
port(
Clk : in std_logic; -- Clock
Reset : in std_logic; -- Reset (synchronous)
-- Control signals
RoundNr : in std_logic; -- biggest round is 12
sel1,sel2,sel3,sel4 : in std_logic_vector(1 downto 0);
sel0 : in std_logic_vector(2 downto 0);
selout : in std_logic;
Reg0En,Reg1En,Reg2En,Reg3En,Reg4En,RegOutEn : in std_logic;
ActivateGen : in std_logic;
GenSize : in std_logic_vector(2 downto 0);
-- Data signals
IV : in std_logic_vector(127 downto 0);
Key : in std_logic_vector(127 downto 0);
DataIn : in std_logic_vector(63 downto 0);
DataOut : out std_logic_vector(127 downto 0)
);
end entity Ascon_StateUpdate_datapath;
architecture structural of Ascon_StateUpdate_datapath is
-- constants
constant EXTRAIV : std_logic_vector(63 downto 0) := x"80400c0600000000"; -- used in the initialization
constant SEPCONSTANT : std_logic_vector(63 downto 0) := x"0000000000000001";
constant ADCONSTANT : std_logic_vector(63 downto 0) := x"8000000000000000";
-- Register signals
signal Reg0In,Reg1In,Reg2In,Reg3In,Reg4In : std_logic_vector(63 downto 0);
signal Reg0Out,Reg1Out,Reg2Out,Reg3Out,Reg4Out : std_logic_vector(63 downto 0);
signal RegOutIn,RegOutOut : std_logic_vector(127 downto 0);
-- Internal signals on datapath
signal DiffOut0,DiffOut1,DiffOut2,DiffOut3,DiffOut4 : std_logic_vector(63 downto 0);
signal XorReg01,XorReg02,XorReg12,XorReg13,XorReg22 : std_logic_vector(63 downto 0);
signal XorReg2,XorReg31,XorReg4 : std_logic_vector(63 downto 0);
signal OutSig0: std_logic_vector(63 downto 0);
signal OutSig1: std_logic_vector(127 downto 0);
begin
-- declare and connect all sub entities
rounds: entity work.Fullrounds port map(Reg0Out,Reg1Out,Reg2Out,Reg3Out,Reg4Out,RoundNr,DiffOut0,DiffOut1,DiffOut2,DiffOut3,DiffOut4);
outpgen: entity work.OutputGenerator port map(Reg0Out,DataIn,GenSize,ActivateGen,XorReg01,OutSig0); -- ActivateGen is a bit that indicates decryption or not
---------------------------------------------
------ Combinatorial logic for a round ------
---------------------------------------------
datapath: process(IV,Key,DataIn,Reg0Out,Reg1Out,Reg2Out,Reg3Out,Reg4Out,RegOutOut, -- inputs blocks and registers
DiffOut0,DiffOut1,DiffOut2,DiffOut3,DiffOut4, -- internal signals
XorReg01,XorReg02,XorReg12,XorReg13,XorReg22,XorReg2,XorReg31,XorReg4,OutSig0,OutSig1, -- internal signals
RoundNr,sel0,sel1,sel2,sel3,sel4,ActivateGen,selout,GenSize) is -- control signals
begin
-- Set correct inputs in registers
if sel0 = "000" then
Reg0In <= DiffOut0;
elsif sel0 = "001" then
Reg0In <= EXTRAIV;
elsif sel0 = "010" then
Reg0In <= XorReg01;
elsif sel0 = "011" then
Reg0In <= XorReg02;
else
Reg0In <= Reg0Out xor ADCONSTANT;
end if;
if sel1 = "00" then
Reg1In <= DiffOut1;
elsif sel1 = "01" then
Reg1In <= Key(127 downto 64);
elsif sel1 = "10" then
Reg1In <= XorReg13;
else
Reg1In <= XorReg12;
end if;
if sel2 = "00" then
Reg2In <= DiffOut2;
elsif sel2 = "01" then
Reg2In <= Key(63 downto 0);
elsif sel2 = "10" then
Reg2In <= XorReg2;
else
Reg2In <= XorReg22;
end if;
if sel3 = "00" then
Reg3In <= DiffOut3;
elsif sel3 = "01" then
Reg3In <= IV(127 downto 64);
else
Reg3In <= XorReg31;
end if;
if sel4 = "00" then
Reg4In <= DiffOut4;
elsif sel4 = "01" then
Reg4In <= IV(63 downto 0);
elsif sel4 = "10" then
Reg4In <= XorReg4;
else
Reg4In <= Reg4Out xor SEPCONSTANT;
end if;
XorReg02 <= Reg0Out xor Key(127 downto 64);
XorReg12 <= Reg1Out xor Key(63 downto 0);
XorReg13 <= Reg1Out xor Key(127 downto 64);
XorReg22 <= Reg2Out xor Key(63 downto 0);
XorReg31 <= Reg3Out xor Key(127 downto 64);
XorReg4 <= Reg4Out xor Key(63 downto 0);
-- Set output
OutSig1(127 downto 64) <= XorReg31;
OutSig1(63 downto 0) <= XorReg4;
if selout = '0' then
RegOutIn(127 downto 64) <= (others => '0');
RegOutIn(63 downto 0) <= OutSig0;
else
RegOutIn <= OutSig1;
end if;
DataOut <= RegOutOut;
end process datapath;
---------------------------------------------
------ The registers in the datapath --------
---------------------------------------------
registerdatapath : process(Clk,Reset) is
begin
if(Clk = '1' and Clk'event) then
if Reset = '1' then -- synchronous reset
Reg0Out <= (others => '0');
Reg1Out <= (others => '0');
Reg2Out <= (others => '0');
Reg3Out <= (others => '0');
Reg4Out <= (others => '0');
RegOutOut <= (others => '0');
else
-- update registers with enable
if Reg0En = '1' then
Reg0Out <= Reg0In;
end if;
if Reg1En = '1' then
Reg1Out <= Reg1In;
end if;
if Reg2En = '1' then
Reg2Out <= Reg2In;
end if;
if Reg3En = '1' then
Reg3Out <= Reg3In;
end if;
if Reg4En = '1' then
Reg4Out <= Reg4In;
end if;
if RegOutEn = '1' then
RegOutOut <= RegOutIn;
end if;
end if;
end if;
end process registerdatapath;
end architecture structural;
| gpl-3.0 | 963279a3b714c0c1fb991b4cba4315b0 | 0.619574 | 3.089402 | false | false | false | false |
impedimentToProgress/UCI-BlueChip | AttackFiles/Attacks/privEsc/lib/gaisler/ddr/ddr2sp64a.vhd | 2 | 32,493 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: ddr2sp64a
-- File: ddr2sp64a.vhd
-- Author: Nils-Johan Wessman - Gaisler Research
-- Description: 64-bit DDR2 memory controller with asych AHB interface
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
library gaisler;
use grlib.devices.all;
use gaisler.memctrl.all;
library techmap;
use techmap.gencomp.all;
entity ddr2sp64a is
generic (
memtech : integer := 0;
hindex : integer := 0;
haddr : integer := 0;
hmask : integer := 16#f00#;
ioaddr : integer := 16#000#;
iomask : integer := 16#fff#;
MHz : integer := 100;
col : integer := 9;
Mbyte : integer := 8;
fast : integer := 0;
pwron : integer := 0;
oepol : integer := 0;
readdly : integer := 1;
odten : integer := 0
);
port (
rst : in std_ulogic;
clk_ddr : in std_ulogic;
clk_ahb : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
sdi : in sdctrl_in_type;
sdo : out sdctrl_out_type
);
end;
architecture rtl of ddr2sp64a is
constant REVISION : integer := 0;
constant CMD_PRE : std_logic_vector(2 downto 0) := "010";
constant CMD_REF : std_logic_vector(2 downto 0) := "100";
constant CMD_LMR : std_logic_vector(2 downto 0) := "110";
constant CMD_EMR : std_logic_vector(2 downto 0) := "111";
constant odtvalue : std_logic_vector(1 downto 0) := conv_std_logic_vector(odten, 2);
constant abuf : integer := 6;
constant hconfig : ahb_config_type := (
0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_DDR2SP, 0, REVISION, 0),
4 => ahb_membar(haddr, '1', '1', hmask),
5 => ahb_iobar(ioaddr, iomask),
others => zero32);
type mcycletype is (midle, active, ext, leadout);
type ahb_state_type is (midle, rhold, dread, dwrite, whold1, whold2);
type sdcycletype is (act1, act2, act3, rd1, rd2, rd3, rd4, rd5, rd6, rd7, rd8,
wr0, wr1, wr2, wr3, wr4a, wr4b, wr4, wr5, sidle, ioreg1, ioreg2);
type icycletype is (iidle, pre, ref1, ref2, emode23, emode, lmode, emodeocd, finish);
-- sdram configuration register
type sdram_cfg_type is record
command : std_logic_vector(2 downto 0);
csize : std_logic_vector(1 downto 0);
bsize : std_logic_vector(2 downto 0);
trcd : std_ulogic; -- tCD : 2/3 clock cycles
trfc : std_logic_vector(4 downto 0);
trp : std_ulogic; -- precharge to activate: 2/3 clock cycles
refresh : std_logic_vector(11 downto 0);
renable : std_ulogic;
dllrst : std_ulogic;
refon : std_ulogic;
cke : std_ulogic;
cal_en : std_logic_vector(7 downto 0);
cal_inc : std_logic_vector(7 downto 0);
cal_rst : std_logic;
readdly : std_logic_vector(1 downto 0);
twr : std_logic_vector(4 downto 0);
emr : std_logic_vector(1 downto 0); -- selects EM register
ocd : std_ulogic; -- enable/disable ocd
end record;
type access_param is record
haddr : std_logic_vector(31 downto 0);
size : std_logic_vector(1 downto 0);
hwrite : std_ulogic;
hio : std_ulogic;
end record;
-- local registers
type ahb_reg_type is record
hready : std_ulogic;
hsel : std_ulogic;
hio : std_ulogic;
startsd : std_ulogic;
write : std_logic_vector(3 downto 0);
state : ahb_state_type;
haddr : std_logic_vector(31 downto 0);
hrdata : std_logic_vector(31 downto 0);
hwdata : std_logic_vector(31 downto 0);
hwrite : std_ulogic;
htrans : std_logic_vector(1 downto 0);
hresp : std_logic_vector(1 downto 0);
raddr : std_logic_vector(abuf-1 downto 0);
size : std_logic_vector(1 downto 0);
acc : access_param;
sync : std_logic_vector(2 downto 1);
startsd_ack : std_logic;
end record;
type ddr_reg_type is record
startsd : std_ulogic;
startsdold : std_ulogic;
hready : std_ulogic;
bdrive : std_ulogic;
qdrive : std_ulogic;
nbdrive : std_ulogic;
mstate : mcycletype;
sdstate : sdcycletype;
cmstate : mcycletype;
istate : icycletype;
trfc : std_logic_vector(4 downto 0);
refresh : std_logic_vector(11 downto 0);
sdcsn : std_logic_vector(1 downto 0);
sdwen : std_ulogic;
rasn : std_ulogic;
casn : std_ulogic;
dqm : std_logic_vector(15 downto 0);
address : std_logic_vector(15 downto 2); -- memory address
ba : std_logic_vector( 1 downto 0);
waddr : std_logic_vector(abuf-1 downto 0);
waddr_d : std_logic_vector(abuf-1 downto 0); -- Same as waddr but delayed to compensate for pipelined output data
cfg : sdram_cfg_type;
hrdata : std_logic_vector(127 downto 0);
readdly : std_logic_vector(1 downto 0); -- added read latency
wdata : std_logic_vector(127 downto 0); -- pipeline register for output data
initnopdly : std_logic_vector(7 downto 0); -- 400 ns delay
sync : std_logic;
odt : std_logic_vector(1 downto 0);
end record;
signal vcc : std_ulogic;
signal r, ri : ddr_reg_type;
signal ra, rai : ahb_reg_type;
signal rbdrive, ribdrive : std_logic_vector(31 downto 0);
signal rdata, wdata : std_logic_vector(127 downto 0);
signal ddr_rst : std_logic;
signal ddr_rst_gen : std_logic_vector(3 downto 0);
attribute syn_preserve : boolean;
attribute syn_preserve of rbdrive : signal is true;
begin
vcc <= '1';
ddr_rst <= (ddr_rst_gen(3) and ddr_rst_gen(2) and ddr_rst_gen(1) and rst); -- Reset signal in DDR clock domain
ahb_ctrl : process(rst, ahbsi, r, ra, rdata)
variable v : ahb_reg_type; -- local variables for registers
variable startsd : std_ulogic;
variable dout : std_logic_vector(31 downto 0);
variable ready : std_logic;
begin
v := ra; v.hresp := HRESP_OKAY; v.write := "0000";
case ra.raddr(1 downto 0) is
when "00" => v.hrdata := rdata(127 downto 96);
when "01" => v.hrdata := rdata(95 downto 64);
when "10" => v.hrdata := rdata(63 downto 32);
when others => v.hrdata := rdata(31 downto 0);
end case;
-- Sync ------------------------------------------------
v.sync(1) := r.startsdold; v.sync(2) := ra.sync(1);
ready := ra.startsd_ack xor ra.sync(2);
--------------------------------------------------------
if ((ahbsi.hready and ahbsi.hsel(hindex)) = '1') then
v.htrans := ahbsi.htrans; v.haddr := ahbsi.haddr;
v.size := ahbsi.hsize(1 downto 0); v.hwrite := ahbsi.hwrite;
if ahbsi.htrans(1) = '1' then
v.hio := ahbsi.hmbsel(1);
v.hsel := '1'; v.hready := '0';
end if;
end if;
if ahbsi.hready = '1' then v.hsel := ahbsi.hsel(hindex); end if;
case ra.state is
when midle =>
if ((v.hsel and v.htrans(1)) = '1') then
if v.hwrite = '0' then
v.state := rhold; v.startsd := not ra.startsd;
else
v.state := dwrite; v.hready := '1';
v.write := decode(v.haddr(3 downto 2));
end if;
end if;
v.raddr := ra.haddr(7 downto 2);
if ahbsi.hready = '1' then
v.acc := (v.haddr, v.size, v.hwrite, v.hio);
end if;
when rhold =>
v.raddr := ra.haddr(7 downto 2);
if ready = '1' then
v.state := dread; v.hready := '1'; v.raddr := ra.raddr + 1;
end if;
when dread =>
v.raddr := ra.raddr + 1; v.hready := '1';
if ((v.hsel and v.htrans(1) and v.htrans(0)) = '0')
or (ra.raddr(2 downto 0) = "000") then
v.state := midle; v.hready := '0';
v.startsd_ack := ra.startsd;
end if;
v.acc := (v.haddr, v.size, v.hwrite, v.hio);
when dwrite =>
v.raddr := ra.haddr(7 downto 2); v.hready := '1';
v.write := decode(v.haddr(3 downto 2));
if ((v.hsel and v.htrans(1) and v.htrans(0)) = '0')
or (ra.haddr(4 downto 2) = "111") then
v.startsd := not ra.startsd; v.state := whold1;
v.write := "0000"; v.hready := '0';
end if;
when whold1 =>
v.state := whold2;
when whold2 =>
if ready = '1' then
v.state := midle; v.acc := (v.haddr, v.size, v.hwrite, v.hio);
v.startsd_ack := ra.startsd;
end if;
end case;
v.hwdata := ahbsi.hwdata;
if (ahbsi.hready and ahbsi.hsel(hindex) ) = '1' then
if ahbsi.htrans(1) = '0' then v.hready := '1'; end if;
end if;
dout := ra.hrdata(31 downto 0);
if rst = '0' then
v.hsel := '0';
v.hready := '1';
v.state := midle;
v.startsd := '0';
v.startsd_ack := '0';
v.hio := '0';
end if;
rai <= v;
ahbso.hready <= ra.hready;
ahbso.hresp <= ra.hresp;
ahbso.hrdata <= dout;
ahbso.hcache <= not ra.hio;
end process;
ddr_ctrl : process(ddr_rst, r, ra, sdi, rbdrive, wdata)
variable v : ddr_reg_type; -- local variables for registers
variable startsd : std_ulogic;
variable dqm : std_logic_vector(15 downto 0);
variable raddr : std_logic_vector(13 downto 0);
variable adec : std_ulogic;
variable rams : std_logic_vector(1 downto 0);
variable ba : std_logic_vector(1 downto 0);
variable haddr : std_logic_vector(31 downto 0);
variable hsize : std_logic_vector(1 downto 0);
variable hwrite : std_ulogic;
variable htrans : std_logic_vector(1 downto 0);
variable hready : std_ulogic;
variable vbdrive : std_logic_vector(31 downto 0);
variable bdrive : std_ulogic;
variable writecfg : std_ulogic;
variable regsd1 : std_logic_vector(31 downto 0); -- data from registers
variable regsd2 : std_logic_vector(31 downto 0); -- data from registers
variable regsd3 : std_logic_vector(31 downto 0); -- data from registers
begin
-- Variable default settings to avoid latches
v := r; v.hready := '0'; writecfg := '0'; vbdrive := rbdrive;
v.hrdata := sdi.data; v.qdrive :='0';
v.cfg.cal_en := (others => '0'); v.cfg.cal_inc := (others => '0');
v.cfg.cal_rst := '0';
v.wdata := wdata; -- pipeline output data
regsd1 := (others => '0');
regsd1(31 downto 15) := r.cfg.refon & r.cfg.ocd & r.cfg.emr & '0' & r.cfg.trcd &
r.cfg.bsize & r.cfg.csize & r.cfg.command &
r.cfg.dllrst & r.cfg.renable & r.cfg.cke;
regsd1(11 downto 0) := r.cfg.refresh;
regsd2 := (others => '0');
regsd2(8 downto 0) := conv_std_logic_vector(MHz, 9);
regsd2(14 downto 12) := conv_std_logic_vector(3, 3);
regsd3 := (others => '0');
regsd3(17 downto 16) := r.cfg.readdly;
regsd3(22 downto 18) := r.cfg.trfc;
regsd3(27 downto 23) := r.cfg.twr;
regsd3(28) := r.cfg.trp;
-- generate DQM from address and write size
case ra.acc.size is
when "00" =>
case ra.acc.haddr(3 downto 0) is
when "0000" => dqm := "0111111111111111";
when "0001" => dqm := "1011111111111111";
when "0010" => dqm := "1101111111111111";
when "0011" => dqm := "1110111111111111";
when "0100" => dqm := "1111011111111111";
when "0101" => dqm := "1111101111111111";
when "0110" => dqm := "1111110111111111";
when "0111" => dqm := "1111111011111111";
when "1000" => dqm := "1111111101111111";
when "1001" => dqm := "1111111110111111";
when "1010" => dqm := "1111111111011111";
when "1011" => dqm := "1111111111101111";
when "1100" => dqm := "1111111111110111";
when "1101" => dqm := "1111111111111011";
when "1110" => dqm := "1111111111111101";
when others => dqm := "1111111111111110";
end case;
when "01" =>
case ra.acc.haddr(3 downto 1) is
when "000" => dqm := "0011111111111111";
when "001" => dqm := "1100111111111111";
when "010" => dqm := "1111001111111111";
when "011" => dqm := "1111110011111111";
when "100" => dqm := "1111111100111111";
when "101" => dqm := "1111111111001111";
when "110" => dqm := "1111111111110011";
when others => dqm := "1111111111111100";
end case;
when others =>
dqm := "0000000000000000";
end case;
-- Sync ------------------------------------------
v.sync := ra.startsd; v.startsd := r.sync;
--------------------------------------------------
--v.startsd := ra.startsd;
---- main FSM
--
-- case r.mstate is
-- when midle =>
-- if r.startsd = '1' then
-- if (r.sdstate = sidle) and (r.cfg.command = "000")
-- and (r.cmstate = midle) then
-- startsd := '1'; v.mstate := active;
-- end if;
-- end if;
-- when others => null;
-- end case;
startsd := r.startsd xor r.startsdold;
-- generate row and column address size
haddr := ra.acc.haddr;
haddr(31 downto 20) := haddr(31 downto 20) and not conv_std_logic_vector(hmask, 12);
case r.cfg.csize is
when "00" => raddr := haddr(25 downto 12);
when "01" => raddr := haddr(26 downto 13);
when "10" => raddr := haddr(27 downto 14);
when others => raddr := haddr(28 downto 15);
end case;
-- generate bank address
ba := genmux(r.cfg.bsize, haddr(29 downto 22)) &
genmux(r.cfg.bsize, haddr(28 downto 21));
-- generate chip select
adec := genmux(r.cfg.bsize, haddr(30 downto 23));
rams := adec & not adec;
-- sdram access FSM
if r.trfc /= "00000" then v.trfc := r.trfc - 1; end if;
case r.sdstate is
when sidle =>
if (startsd = '1') and (r.cfg.command = "000") and (r.cmstate = midle)
and (r.istate = finish) then
v.address := raddr; v.ba := ba;
if ra.acc.hio = '0' then
v.sdcsn := not rams(1 downto 0); v.rasn := '0'; v.sdstate := act1;
else v.sdstate := ioreg1; end if;
end if;
v.waddr := ra.acc.haddr(7 downto 2);
when act1 =>
v.rasn := '1'; v.trfc := r.cfg.trfc;
if r.cfg.trcd = '1' then v.sdstate := act2;
else v.sdstate := act3;
end if;
v.waddr := ra.acc.haddr(7 downto 2);
v.waddr_d := ra.acc.haddr(7 downto 2);
when act2 =>
v.sdstate := act3;
when act3 =>
v.casn := '0';
v.address := ra.acc.haddr(15 downto 13) & '0' & ra.acc.haddr(12 downto 4) & '0';
v.hready := ra.acc.hwrite;
if ra.acc.hwrite = '1' then
v.sdstate := wr0;
v.sdwen := '0';
v.waddr := r.waddr + 4; v.waddr(1 downto 0) := "00"; -- inc address to memory, needed because data is pipelined
v.trfc := r.cfg.twr;
else v.sdstate := rd1; end if;
when wr0 =>
v.casn := '1'; v.sdwen := '1'; v.bdrive := '0'; v.qdrive := '1';
v.dqm := dqm;
v.waddr_d := r.waddr_d + 4; v.waddr_d(1 downto 0) := "00";
v.waddr := r.waddr + 4;
v.sdstate := wr1;
if (r.waddr_d /= ra.raddr) then v.hready := '1';
if (r.waddr_d(5 downto 2) = ra.raddr(5 downto 2)) then
if r.waddr_d(1) = '1' then v.dqm(15 downto 8) := (others => '1');
else
case ra.raddr(1 downto 0) is
when "01" => v.dqm(7 downto 0) := (others => '1');
when "10" => v.dqm(3 downto 0) := (others => '1');
v.dqm(15 downto 12) := (others => r.waddr_d(0));
when others => v.dqm(15 downto 12) := (others => r.waddr_d(0));
end case;
end if;
else
case r.waddr_d(1 downto 0) is
when "01" => v.dqm(15 downto 12) := (others => '1');
when "10" => v.dqm(15 downto 8) := (others => '1');
when "11" => v.dqm(15 downto 4) := (others => '1');
when others => null;
end case;
end if;
else
case r.waddr_d(1 downto 0) is
when "00" => v.dqm(11 downto 0) := (others => '1');
when "01" => v.dqm(15 downto 12) := (others => '1'); v.dqm(7 downto 0) := (others => '1');
when "10" => v.dqm(15 downto 8) := (others => '1'); v.dqm(3 downto 0) := (others => '1');
when others => v.dqm(15 downto 4) := (others => '1');
end case;
end if;
when wr1 =>
v.sdwen := '1'; v.casn := '1'; v.qdrive := '1';
v.waddr_d := r.waddr_d + 4; v.dqm := (others => '0');
v.waddr := r.waddr + 4;
v.address(8 downto 3) := r.waddr_d;
if (r.waddr_d <= ra.raddr) and (r.waddr_d(5 downto 2) /= "0000") and (r.hready = '1') then
v.hready := '1';
if (r.hready = '1') and (r.waddr_d(2 downto 0) = "000") then
v.sdwen := '0'; v.casn := '0';
end if;
if (r.waddr_d(5 downto 2) = ra.raddr(5 downto 2)) and (r.waddr_d /= "000000") then
case ra.raddr(1 downto 0) is
when "00" => v.dqm(11 downto 0) := (others => '1');
when "01" => v.dqm(7 downto 0) := (others => '1');
when "10" => v.dqm(3 downto 0) := (others => '1');
when others => null;
end case;
end if;
else
v.sdstate := wr2;
v.dqm := (others => '1');
v.startsdold := r.startsd;
end if;
when wr2 =>
v.sdstate := wr3; v.qdrive := '1';
when wr3 =>
v.sdstate := wr4a; v.qdrive := '1';
when wr4a =>
v.bdrive := '1'; v.qdrive := '1';
if r.trfc <= "00000" then -- wait to not violate TWR timing
v.sdstate := wr4b;
end if;
when wr4b =>
v.bdrive := '1';
v.rasn := '0'; v.sdwen := '0'; v.sdstate := wr4; v.qdrive := '1';
when wr4 =>
v.sdcsn := "11"; v.rasn := '1'; v.sdwen := '1'; v.qdrive := '0';
v.sdstate := wr5;
when wr5 =>
v.sdstate := sidle;
when rd1 =>
v.casn := '1'; v.sdstate := rd7;
when rd7 =>
v.casn := '1'; v.sdstate := rd8;
v.readdly := r.cfg.readdly;
when rd8 => -- (CL = 3)
v.casn := '1';
if r.readdly = "00" then -- add read delay
v.sdstate := rd2;
else
v.readdly := r.readdly - 1;
end if;
when rd2 =>
v.casn := '1'; v.sdstate := rd3;
when rd3 =>
v.sdstate := rd4; v.hready := '1'; v.casn := '1';
if fast = 0 then v.startsdold := r.startsd; end if;
if v.hready = '1' then v.waddr := r.waddr + 4; end if;
when rd4 =>
v.hready := '1'; v.casn := '1';
if (r.sdcsn = "11") or (r.waddr(2 downto 2) = "1") then
v.dqm := (others => '1');
if fast /= 0 then v.startsdold := r.startsd; end if;
if (r.sdcsn /= "11") then
v.rasn := '0'; v.sdwen := '0'; v.sdstate := rd5;
else
if r.cfg.trp = '1' then v.sdstate := rd6;
else v.sdstate := sidle; end if;
end if;
end if;
if v.hready = '1' then v.waddr := r.waddr + 4; end if;
when rd5 =>
if r.cfg.trp = '1' then v.sdstate := rd6;
else v.sdstate := sidle; end if;
v.sdcsn := (others => '1'); v.rasn := '1'; v.sdwen := '1';
v.dqm := (others => '1');
when rd6 =>
v.sdstate := sidle; v.dqm := (others => '1');
v.sdcsn := (others => '1'); v.rasn := '1'; v.sdwen := '1';
when ioreg1 =>
v.hrdata(127 downto 32) := regsd1 & regsd2 & regsd3; v.sdstate := ioreg2;
if ra.acc.hwrite = '0' then v.hready := '1'; end if;
when ioreg2 =>
writecfg := ra.acc.hwrite; v.startsdold := r.startsd;
v.sdstate := sidle;
when others =>
v.sdstate := sidle;
end case;
-- sdram commands
case r.cmstate is
when midle =>
if r.sdstate = sidle then
case r.cfg.command is
when CMD_PRE => -- precharge
v.sdcsn := (others => '0'); v.rasn := '0'; v.sdwen := '0';
v.address(12) := '1'; v.cmstate := active;
when CMD_REF => -- auto-refresh
v.sdcsn := (others => '0'); v.rasn := '0'; v.casn := '0';
v.cmstate := active;
when CMD_EMR => -- load-ext-mode-reg
v.sdcsn := (others => '0'); v.rasn := '0'; v.casn := '0';
v.sdwen := '0'; v.cmstate := active; v.ba := r.cfg.emr; --v.ba select EM register;
--v.address := "0000"&r.cfg.ocd&r.cfg.ocd&r.cfg.ocd&"0000000";
if r.cfg.emr = "01" then
v.address := "0000"&r.cfg.ocd&r.cfg.ocd&r.cfg.ocd
& odtvalue(1)&"000"&odtvalue(0)&"00";
else
v.address := "0000"&r.cfg.ocd&r.cfg.ocd&r.cfg.ocd&"0000000";
end if;
when CMD_LMR => -- load-mode-reg
v.sdcsn := (others => '0'); v.rasn := '0'; v.casn := '0';
v.sdwen := '0'; v.cmstate := active; v.ba := "00";
v.address := "00010" & r.cfg.dllrst & "0" & "01" & "10010"; -- CAS = 3 WR = 3
when others => null;
end case;
end if;
when active =>
v.sdcsn := (others => '1'); v.rasn := '1'; v.casn := '1';
v.sdwen := '1'; v.cfg.command := "000";
v.cmstate := leadout; v.trfc := r.cfg.trfc;
when others =>
if r.trfc = "00000" then v.cmstate := midle; end if;
end case;
-- sdram init
case r.istate is
when iidle =>
if r.cfg.renable = '1' then
v.cfg.cke := '1'; v.cfg.dllrst := '1';
v.ba := "00"; v.cfg.ocd := '0'; v.cfg.emr := "10"; -- EMR(2)
if r.cfg.cke = '1' then
if r.initnopdly = "00000000" then -- 400 ns of NOP and CKE
v.istate := pre; v.cfg.command := CMD_PRE;
else
v.initnopdly := r.initnopdly - 1;
end if;
end if;
end if;
when pre =>
if r.cfg.command = "000" then
v.cfg.command := "11" & r.cfg.dllrst; -- CMD_LMR/CMD_EMR
if r.cfg.dllrst = '1' then v.istate := emode23; else v.istate := lmode; end if;
end if;
when emode23 =>
if r.cfg.command = "000" then
if r.cfg.emr = "11" then
v.cfg.emr := "01"; -- (EMR(1))
v.istate := emode; v.cfg.command := CMD_EMR;
else
v.cfg.emr := "11"; v.cfg.command := CMD_EMR; -- EMR(3)
end if;
end if;
when emode =>
if r.cfg.command = "000" then
v.istate := lmode; v.cfg.command := CMD_LMR;
end if;
when lmode =>
if r.cfg.command = "000" then
if r.cfg.dllrst = '1' then
if r.refresh(9 downto 8) = "00" then -- > 200 clocks delay
v.cfg.command := CMD_PRE; v.istate := ref1;
end if;
else
v.istate := emodeocd;
v.cfg.ocd := '1'; v.cfg.command := CMD_EMR;
end if;
end if;
when ref1 =>
if r.cfg.command = "000" then
v.cfg.command := CMD_REF; v.cfg.dllrst := '0'; v.istate := ref2;
end if;
when ref2 =>
if r.cfg.command = "000" then
v.cfg.command := CMD_REF; v.istate := pre;
end if;
when emodeocd =>
if r.cfg.command = "000" then
if r.cfg.ocd = '0' then -- Exit OCD
v.istate := finish;
v.cfg.refon := '1'; v.cfg.renable := '0';
else -- Default OCD
v.cfg.ocd := '0';
v.cfg.command := CMD_EMR;
end if;
end if;
v.cfg.cal_rst := '1'; -- reset data bit delay
when others =>
if odten /= 0 then v.odt := (others => '1'); end if;
if r.cfg.renable = '1' then
v.istate := iidle; v.cfg.dllrst := '1';
v.initnopdly := (others => '1');
v.odt := (others => '0');
end if;
end case;
---- second part of main fsm
--
-- case r.mstate is
-- when active =>
-- if v.hready = '1' then
-- v.mstate := midle;
-- end if;
-- when others => null;
-- end case;
-- sdram refresh counter
if ((r.cfg.refon = '1') and (r.istate = finish)) or (r.cfg.dllrst = '1') then
v.refresh := r.refresh - 1;
if (v.refresh(11) and not r.refresh(11)) = '1' then
v.refresh := r.cfg.refresh;
if r.cfg.dllrst = '0' then v.cfg.command := "100"; end if;
end if;
end if;
-- AHB register access
if (ra.acc.hio and ra.acc.hwrite and writecfg) = '1' then
if r.waddr(1 downto 0) = "00" then
v.cfg.refresh := r.wdata(11+96 downto 0+96);
v.cfg.cke := r.wdata(15+96);
v.cfg.renable := r.wdata(16+96);
v.cfg.dllrst := r.wdata(17+96);
v.cfg.command := r.wdata(20+96 downto 18+96);
v.cfg.csize := r.wdata(22+96 downto 21+96);
v.cfg.bsize := r.wdata(25+96 downto 23+96);
v.cfg.trcd := r.wdata(26+96);
v.cfg.emr := r.wdata(29+96 downto 28+96);
v.cfg.ocd := r.wdata(30+96);
v.cfg.refon := r.wdata(31+96);
elsif r.waddr(1 downto 0) = "10" then
v.cfg.cal_en := r.wdata( 7+32 downto 0+32);
v.cfg.cal_inc := r.wdata(15+32 downto 8+32);
v.cfg.readdly := r.wdata(17+32 downto 16+32);
v.cfg.trfc := r.wdata(22+32 downto 18+32);
v.cfg.twr := r.wdata(27+32 downto 23+32);
v.cfg.trp := r.wdata(28+32);
v.cfg.cal_rst := r.wdata(31+32);
end if;
end if;
v.nbdrive := not v.bdrive;
if oepol = 1 then bdrive := r.nbdrive; vbdrive := (others => v.nbdrive);
else bdrive := r.bdrive; vbdrive := (others => v.bdrive);end if;
-- reset
if ddr_rst = '0' then
v.sdstate := sidle;
v.mstate := midle;
v.istate := finish;
v.cmstate := midle;
v.cfg.command := "000";
v.cfg.csize := conv_std_logic_vector(col-9, 2);
v.cfg.bsize := conv_std_logic_vector(log2(Mbyte/8), 3);
v.cfg.refon := '0';
v.cfg.trfc := conv_std_logic_vector(75*MHz/1000-2, 5);
v.cfg.refresh := conv_std_logic_vector(7800*MHz/1000, 12);
v.cfg.twr := conv_std_logic_vector((15)*MHz/1000+3, 5);
v.refresh := (others => '0');
v.dqm := (others => '1');
v.sdwen := '1';
v.rasn := '1';
v.casn := '1';
v.hready := '0';
v.startsd := '0';
v.startsdold := '0';
v.cfg.dllrst := '0';
v.cfg.cke := '0';
v.cfg.ocd := '0';
v.cfg.readdly := conv_std_logic_vector(readdly, 2);
v.initnopdly := (others => '1');
if MHz > 130 then v.cfg.trcd := '1'; else v.cfg.trcd := '0'; end if;
if MHz > 130 then v.cfg.trp := '1'; else v.cfg.trp := '0'; end if;
if pwron = 1 then v.cfg.renable := '1';
else v.cfg.renable := '0'; end if;
v.odt := (others => '0');
end if;
ri <= v;
ribdrive <= vbdrive;
end process;
sdo.sdcke <= (others => r.cfg.cke);
ahbso.hconfig <= hconfig;
ahbso.hirq <= (others => '0');
ahbso.hindex <= hindex;
ahbregs : process(clk_ahb) begin
if rising_edge(clk_ahb) then
ra <= rai;
end if;
end process;
ddrregs : process(clk_ddr, rst, ddr_rst) begin
if rising_edge(clk_ddr) then
r <= ri; rbdrive <= ribdrive;
ddr_rst_gen <= ddr_rst_gen(2 downto 0) & '1';
end if;
if (rst = '0') then
ddr_rst_gen <= "0000";
end if;
if (ddr_rst = '0') then
r.sdcsn <= (others => '1'); r.bdrive <= '1'; r.nbdrive <= '0';
if oepol = 0 then rbdrive <= (others => '1');
else rbdrive <= (others => '0'); end if;
r.cfg.cke <= '0';
end if;
end process;
sdo.address <= '0' & ri.address;
sdo.ba <= ri.ba;
sdo.bdrive <= r.nbdrive when oepol = 1 else r.bdrive;
sdo.qdrive <= not (ri.qdrive or r.nbdrive);
sdo.vbdrive <= rbdrive;
sdo.sdcsn <= ri.sdcsn;
sdo.sdwen <= ri.sdwen;
sdo.dqm <= r.dqm;
sdo.rasn <= ri.rasn;
sdo.casn <= ri.casn;
--sdo.data <= wdata;
sdo.data <= r.wdata; -- data pipelined
sdo.cal_en <= r.cfg.cal_en;
sdo.cal_inc <= r.cfg.cal_inc;
sdo.cal_rst <= r.cfg.cal_rst;
sdo.odt <= r.odt;
read_buff : syncram_2p
generic map (tech => memtech, abits => 4, dbits => 128, sepclk => 1, wrfst => 0)
port map ( rclk => clk_ahb, renable => vcc, raddress => rai.raddr(5 downto 2),
dataout => rdata, wclk => clk_ddr, write => ri.hready,
waddress => r.waddr(5 downto 2), datain => ri.hrdata);
write_buff1 : syncram_2p
generic map (tech => memtech, abits => 4, dbits => 32, sepclk => 1, wrfst => 0)
port map ( rclk => clk_ddr, renable => vcc, raddress => r.waddr(5 downto 2),
dataout => wdata(127 downto 96), wclk => clk_ahb, write => ra.write(0),
waddress => ra.haddr(7 downto 4), datain => ahbsi.hwdata);
write_buff2 : syncram_2p
generic map (tech => memtech, abits => 4, dbits => 32, sepclk => 1, wrfst => 0)
port map ( rclk => clk_ddr, renable => vcc, raddress => r.waddr(5 downto 2),
dataout => wdata(95 downto 64), wclk => clk_ahb, write => ra.write(1),
waddress => ra.haddr(7 downto 4), datain => ahbsi.hwdata);
write_buff3 : syncram_2p
generic map (tech => memtech, abits => 4, dbits => 32, sepclk => 1, wrfst => 0)
port map ( rclk => clk_ddr, renable => vcc, raddress => r.waddr(5 downto 2),
dataout => wdata(63 downto 32), wclk => clk_ahb, write => ra.write(2),
waddress => ra.haddr(7 downto 4), datain => ahbsi.hwdata);
write_buff4 : syncram_2p
generic map (tech => memtech, abits => 4, dbits => 32, sepclk => 1, wrfst => 0)
port map ( rclk => clk_ddr, renable => vcc, raddress => r.waddr(5 downto 2),
dataout => wdata(31 downto 0), wclk => clk_ahb, write => ra.write(3),
waddress => ra.haddr(7 downto 4), datain => ahbsi.hwdata);
-- pragma translate_off
bootmsg : report_version
generic map (
msg1 => "ddr2sp" & tost(hindex) & ": 64-bit DDR2 controller rev " &
tost(REVISION) & ", " & tost(Mbyte) & " Mbyte, " & tost(MHz) &
" MHz DDR clock");
-- pragma translate_on
end;
| mit | be92e65095c499be32204480df083b59 | 0.500231 | 3.367499 | false | false | false | false |
impedimentToProgress/UCI-BlueChip | AttackFiles/Attacks/privEsc/lib/tech/altera/simprims/altera_primitives_components.vhd | 2 | 14,224 | -- Copyright (C) 1991-2007 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions
-- and other software and tools, and its AMPP partner logic
-- functions, and any output files from any of the foregoing
-- (including device programming or simulation files), and any
-- associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License
-- Subscription Agreement, Altera MegaCore Function License
-- Agreement, or other applicable license agreement, including,
-- without limitation, that your use is for the sole purpose of
-- programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the
-- applicable agreement for further details.
-- Quartus II 7.1 Build 156 04/30/2007
----------------------------------------------------------------------------
-- ALtera Primitives Component Declaration File
----------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
package dffeas_pack is
-- default generic values
CONSTANT DefWireDelay : VitalDelayType01 := (0 ns, 0 ns);
CONSTANT DefPropDelay01 : VitalDelayType01 := (0 ns, 0 ns);
CONSTANT DefPropDelay01Z : VitalDelayType01Z := (OTHERS => 0 ns);
CONSTANT DefSetupHoldCnst : TIME := 0 ns;
CONSTANT DefPulseWdthCnst : TIME := 0 ns;
CONSTANT DefGlitchMode : VitalGlitchKindType := VitalTransport;
CONSTANT DefGlitchMsgOn : BOOLEAN := FALSE;
CONSTANT DefGlitchXOn : BOOLEAN := FALSE;
CONSTANT DefMsgOnChecks : BOOLEAN := TRUE;
CONSTANT DefXOnChecks : BOOLEAN := TRUE;
end dffeas_pack;
library ieee;
use ieee.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use work.dffeas_pack.all;
package altera_primitives_components is
component carry
port (
a_in : in std_logic;
a_out : out std_logic );
end component;
component cascade
port (
a_in : in std_logic;
a_out : out std_logic );
end component;
component global
port (
a_in : in std_logic;
a_out : out std_logic);
end component;
component tri
port(
a_in : in std_logic;
oe : in std_logic;
a_out : out std_logic);
end component;
component carry_sum
port (
sin : in std_logic;
cin : in std_logic;
sout : out std_logic;
cout : out std_logic );
end component;
component exp
port (
a_in : in std_logic;
a_out : out std_logic);
end component;
component soft
port (
a_in : in std_logic;
a_out : out std_logic );
end component;
component opndrn
port (
a_in : in std_logic;
a_out : out std_logic );
end component;
component row_global
port (
a_in : in std_logic;
a_out : out std_logic );
end component;
component lut_input
port(
a_in : in std_logic;
a_out : out std_logic);
end component;
component lut_output
port(
a_in : in std_logic;
a_out : out std_logic);
end component;
component dlatch
port(
d : in std_logic;
ena : in std_logic;
clrn : in std_logic;
prn : in std_logic;
q : out std_logic);
end component;
component latch
port(
d : in std_logic;
ena : in std_logic;
q : out std_logic);
end component;
component dff
port(
d, clk, clrn, prn : in std_logic;
q : out std_logic);
end component;
component dffe
port(
d, clk, ena, clrn, prn : in std_logic;
q : out std_logic);
end component;
component dffea
port(
d, clk, ena, clrn, prn, aload, adata : in std_logic;
q : out std_logic);
end component;
component dffeas
generic (
power_up : string := "DONT_CARE";
is_wysiwyg : string := "false";
x_on_violation : string := "on";
lpm_type : string := "DFFEAS";
tsetup_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_asdata_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_sclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_asdata_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_sclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_clk_q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_clrn_q_negedge : VitalDelayType01 := DefPropDelay01;
tpd_prn_q_negedge : VitalDelayType01 := DefPropDelay01;
tpd_aload_q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_asdata_q: VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_d : VitalDelayType01 := DefPropDelay01;
tipd_asdata : VitalDelayType01 := DefPropDelay01;
tipd_sclr : VitalDelayType01 := DefPropDelay01;
tipd_sload : VitalDelayType01 := DefPropDelay01;
tipd_clrn : VitalDelayType01 := DefPropDelay01;
tipd_prn : VitalDelayType01 := DefPropDelay01;
tipd_aload : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks;
InstancePath: STRING := "*" );
port (
d : in std_logic := '0';
clk : in std_logic := '0';
ena : in std_logic := '1';
clrn : in std_logic := '1';
prn : in std_logic := '1';
aload : in std_logic := '0';
asdata : in std_logic := '1';
sclr : in std_logic := '0';
sload : in std_logic := '0';
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
q : out std_logic );
end component;
component tff
port(
t, clk, clrn, prn : in std_logic;
q : out std_logic);
end component;
component tffe
port(
t, clk, ena, clrn, prn : in std_logic;
q : out std_logic);
end component;
component jkff
port(
j, k, clk, clrn, prn : in std_logic;
q : out std_logic);
end component;
component jkffe
port(
j, k, clk, ena, clrn, prn : in std_logic;
q : out std_logic);
end component;
component srff
port(
s, r, clk, clrn, prn : in std_logic;
q : out std_logic);
end component;
component srffe
port(
s, r, clk, ena, clrn, prn : in std_logic;
q : out std_logic);
end component;
component clklock
generic(
input_frequency : natural := 10000;
clockboost : natural := 1);
port(
inclk : in std_logic;
outclk : out std_logic);
end component;
component alt_inbuf
generic(
io_standard : string := "NONE";
location : string := "NONE";
enable_bus_hold : string := "NONE";
weak_pull_up_resistor : string := "NONE";
termination : string := "NONE";
lpm_type : string := "alt_inbuf" );
port(
i : in std_logic;
o : out std_logic);
end component;
component alt_outbuf
generic(
io_standard : string := "NONE";
current_strength : string := "NONE";
current_strength_new : string := "NONE";
slew_rate : integer := -1;
slow_slew_rate : string := "NONE";
location : string := "NONE";
enable_bus_hold : string := "NONE";
weak_pull_up_resistor : string := "NONE";
termination : string := "NONE";
lpm_type : string := "alt_outbuf" );
port(
i : in std_logic;
o : out std_logic);
end component;
component alt_outbuf_tri
generic(
io_standard : string := "NONE";
current_strength : string := "NONE";
current_strength_new : string := "NONE";
slew_rate : integer := -1;
slow_slew_rate : string := "NONE";
location : string := "NONE";
enable_bus_hold : string := "NONE";
weak_pull_up_resistor : string := "NONE";
termination : string := "NONE";
lpm_type : string := "alt_outbuf_tri" );
port(
i : in std_logic;
oe : in std_logic;
o : out std_logic);
end component;
component alt_iobuf
generic(
io_standard : string := "NONE";
current_strength : string := "NONE";
current_strength_new : string := "NONE";
slew_rate : integer := -1;
slow_slew_rate : string := "NONE";
location : string := "NONE";
enable_bus_hold : string := "NONE";
weak_pull_up_resistor : string := "NONE";
termination : string := "NONE";
input_termination : string := "NONE";
output_termination : string := "NONE";
lpm_type : string := "alt_iobuf" );
port(
i : in std_logic;
oe : in std_logic;
io : inout std_logic;
o : out std_logic);
end component;
component alt_inbuf_diff
generic(
io_standard : string := "NONE";
location : string := "NONE";
enable_bus_hold : string := "NONE";
weak_pull_up_resistor : string := "NONE";
termination : string := "NONE";
lpm_type : string := "alt_inbuf_diff" );
port(
i : in std_logic;
ibar : in std_logic;
o : out std_logic);
end component;
component alt_outbuf_diff
generic (
io_standard : string := "NONE";
current_strength : string := "NONE";
current_strength_new : string := "NONE";
slew_rate : integer := -1;
location : string := "NONE";
enable_bus_hold : string := "NONE";
weak_pull_up_resistor : string := "NONE";
termination : string := "NONE";
lpm_type : string := "alt_outbuf_diff" );
port(
i : in std_logic;
o : out std_logic;
obar : out std_logic );
end component;
component alt_outbuf_tri_diff
generic (
io_standard : string := "NONE";
current_strength : string := "NONE";
current_strength_new : string := "NONE";
slew_rate : integer := -1;
location : string := "NONE";
enable_bus_hold : string := "NONE";
weak_pull_up_resistor : string := "NONE";
termination : string := "NONE";
lpm_type : string := "alt_outbuf_tri_diff" );
port(
i : in std_logic;
oe : in std_logic;
o : out std_logic;
obar : out std_logic );
end component;
component alt_iobuf_diff
generic (
io_standard : string := "NONE";
current_strength : string := "NONE";
current_strength_new : string := "NONE";
slew_rate : integer := -1;
location : string := "NONE";
enable_bus_hold : string := "NONE";
weak_pull_up_resistor : string := "NONE";
termination : string := "NONE";
input_termination : string := "NONE";
output_termination : string := "NONE";
lpm_type : string := "alt_iobuf_diff" );
port(
i : in std_logic;
oe : in std_logic;
io : inout std_logic;
iobar : inout std_logic;
o : out std_logic );
end component;
component alt_bidir_diff
generic (
io_standard : string := "NONE";
current_strength : string := "NONE";
current_strength_new : string := "NONE";
slew_rate : integer := -1;
location : string := "NONE";
enable_bus_hold : string := "NONE";
weak_pull_up_resistor : string := "NONE";
termination : string := "NONE";
input_termination : string := "NONE";
output_termination : string := "NONE";
lpm_type : string := "alt_bidir_diff" );
port(
oe : in std_logic;
bidirin : inout std_logic;
io : inout std_logic;
iobar : inout std_logic );
end component;
component alt_bidir_buf
generic (
io_standard : string := "NONE";
current_strength : string := "NONE";
current_strength_new : string := "NONE";
slew_rate : integer := -1;
location : string := "NONE";
enable_bus_hold : string := "NONE";
weak_pull_up_resistor : string := "NONE";
termination : string := "NONE";
input_termination : string := "NONE";
output_termination : string := "NONE";
lpm_type : string := "alt_bidir_buf" );
port(
oe : in std_logic;
bidirin : inout std_logic;
io : inout std_logic );
end component;
end altera_primitives_components;
| mit | 0da2dbb25692bac71408ad37816c9405 | 0.526786 | 3.898054 | false | false | false | false |
impedimentToProgress/UCI-BlueChip | AttackFiles/Attacks/privEsc/lib/eth/core/greth_pkg.vhd | 2 | 19,491 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.stdlib.all;
package grethpkg is
--gigabit sync types
type data_sync_type is array (0 to 3) of std_logic_vector(31 downto 0);
type ctrl_sync_type is array (0 to 3) of std_logic_vector(1 downto 0);
constant HTRANS_IDLE: std_logic_vector(1 downto 0) := "00";
constant HTRANS_NONSEQ: std_logic_vector(1 downto 0) := "10";
constant HTRANS_SEQ: std_logic_vector(1 downto 0) := "11";
constant HBURST_INCR: std_logic_vector(2 downto 0) := "001";
constant HSIZE_WORD: std_logic_vector(2 downto 0) := "010";
constant HRESP_OKAY: std_logic_vector(1 downto 0) := "00";
constant HRESP_ERROR: std_logic_vector(1 downto 0) := "01";
constant HRESP_RETRY: std_logic_vector(1 downto 0) := "10";
constant HRESP_SPLIT: std_logic_vector(1 downto 0) := "11";
--receiver constants
constant maxsizerx : std_logic_vector(15 downto 0) :=
conv_std_logic_vector(1500, 16);
constant minpload : std_logic_vector(10 downto 0) :=
conv_std_logic_vector(60, 11);
type ahb_fifo_in_type is record
renable : std_ulogic;
raddress : std_logic_vector(4 downto 0);
write : std_ulogic;
data : std_logic_vector(31 downto 0);
waddress : std_logic_vector(4 downto 0);
end record;
type ahb_fifo_out_type is record
data : std_logic_vector(31 downto 0);
end record;
type nchar_fifo_in_type is record
renable : std_ulogic;
raddress : std_logic_vector(5 downto 0);
write : std_ulogic;
data : std_logic_vector(8 downto 0);
waddress : std_logic_vector(5 downto 0);
end record;
type nchar_fifo_out_type is record
data : std_logic_vector(8 downto 0);
end record;
type rmapbuf_in_type is record
renable : std_ulogic;
raddress : std_logic_vector(7 downto 0);
write : std_ulogic;
data : std_logic_vector(7 downto 0);
waddress : std_logic_vector(7 downto 0);
end record;
type rmapbuf_out_type is record
data : std_logic_vector(7 downto 0);
end record;
type ahbc_mst_in_type is record
hgrant : std_ulogic; -- bus grant
hready : std_ulogic; -- transfer done
hresp : std_logic_vector(1 downto 0); -- response type
hrdata : std_logic_vector(31 downto 0); -- read data bus
end record;
type ahbc_mst_out_type is record
hbusreq : std_ulogic; -- bus request
hlock : std_ulogic; -- lock request
htrans : std_logic_vector(1 downto 0); -- transfer type
haddr : std_logic_vector(31 downto 0); -- address bus (byte)
hwrite : std_ulogic; -- read/write
hsize : std_logic_vector(2 downto 0); -- transfer size
hburst : std_logic_vector(2 downto 0); -- burst type
hprot : std_logic_vector(3 downto 0); -- protection control
hwdata : std_logic_vector(31 downto 0); -- write data bus
end record;
type apbc_slv_in_type is record
psel : std_ulogic; -- slave select
penable : std_ulogic; -- strobe
paddr : std_logic_vector(31 downto 0); -- address bus (byte)
pwrite : std_ulogic; -- write
pwdata : std_logic_vector(31 downto 0); -- write data bus
end record;
type apbc_slv_out_type is record
prdata : std_logic_vector(31 downto 0); -- read data bus
end record;
type eth_tx_ahb_in_type is record
req : std_ulogic;
write : std_ulogic;
addr : std_logic_vector(31 downto 0);
data : std_logic_vector(31 downto 0);
end record;
type eth_tx_ahb_out_type is record
grant : std_ulogic;
data : std_logic_vector(31 downto 0);
ready : std_ulogic;
error : std_ulogic;
retry : std_ulogic;
end record;
type eth_rx_ahb_in_type is record
req : std_ulogic;
write : std_ulogic;
addr : std_logic_vector(31 downto 0);
data : std_logic_vector(31 downto 0);
end record;
type eth_rx_ahb_out_type is record
grant : std_ulogic;
ready : std_ulogic;
error : std_ulogic;
retry : std_ulogic;
data : std_logic_vector(31 downto 0);
end record;
type eth_rx_gbit_ahb_in_type is record
req : std_ulogic;
write : std_ulogic;
addr : std_logic_vector(31 downto 0);
data : std_logic_vector(31 downto 0);
size : std_logic_vector(1 downto 0);
end record;
type gbit_host_tx_type is record
full_duplex : std_ulogic;
start : std_ulogic;
read_ack : std_ulogic;
data : std_logic_vector(31 downto 0);
valid : std_ulogic;
len : std_logic_vector(10 downto 0);
rx_col : std_ulogic;
rx_crs : std_ulogic;
end record;
type gbit_tx_host_type is record
txd : std_logic_vector(3 downto 0);
tx_en : std_ulogic;
done : std_ulogic;
read : std_ulogic;
restart : std_ulogic;
status : std_logic_vector(1 downto 0);
end record;
type gbit_rx_host_type is record
sync_start : std_ulogic;
done : std_ulogic;
write : std_logic_vector(3 downto 0);
dataout : data_sync_type;
byte_count : std_logic_vector(10 downto 0);
status : std_logic_vector(3 downto 0);
gotframe : std_ulogic;
end record;
type gbit_host_rx_type is record
full_duplex : std_ulogic;
gbit : std_ulogic;
doneack : std_ulogic;
writeack : std_logic_vector(3 downto 0);
speed : std_ulogic;
writeok : std_logic_vector(3 downto 0);
rxenable : std_ulogic;
rxd : std_logic_vector(7 downto 0);
rx_dv : std_ulogic;
rx_er : std_ulogic;
rx_col : std_ulogic;
rx_crs : std_ulogic;
end record;
type gbit_gtx_host_type is record
txd : std_logic_vector(7 downto 0);
tx_en : std_ulogic;
tx_er : std_ulogic;
done : std_ulogic;
restart : std_ulogic;
read : std_logic_vector(3 downto 0);
status : std_logic_vector(2 downto 0);
end record;
type gbit_host_gtx_type is record
rx_col : std_ulogic;
rx_crs : std_ulogic;
full_duplex : std_ulogic;
burstmode : std_ulogic;
txen : std_ulogic;
start_sync : std_ulogic;
readack : std_logic_vector(3 downto 0);
valid : std_logic_vector(3 downto 0);
data : data_sync_type;
len : std_logic_vector(10 downto 0);
end record;
type host_tx_type is record
rx_col : std_ulogic;
rx_crs : std_ulogic;
full_duplex : std_ulogic;
start : std_ulogic;
readack : std_ulogic;
speed : std_ulogic;
data : std_logic_vector(31 downto 0);
valid : std_ulogic;
len : std_logic_vector(10 downto 0);
end record;
type tx_host_type is record
txd : std_logic_vector(3 downto 0);
tx_en : std_ulogic;
tx_er : std_ulogic;
done : std_ulogic;
read : std_ulogic;
restart : std_ulogic;
status : std_logic_vector(1 downto 0);
end record;
type rx_host_type is record
dataout : std_logic_vector(31 downto 0);
start : std_ulogic;
done : std_ulogic;
write : std_ulogic;
status : std_logic_vector(3 downto 0);
gotframe : std_ulogic;
byte_count : std_logic_vector(10 downto 0);
lentype : std_logic_vector(15 downto 0);
end record;
type host_rx_type is record
writeack : std_ulogic;
doneack : std_ulogic;
speed : std_ulogic;
writeok : std_ulogic;
rxd : std_logic_vector(3 downto 0);
rx_dv : std_ulogic;
rx_crs : std_ulogic;
rx_er : std_ulogic;
enable : std_ulogic;
end record;
component greth_rx is
generic(
nsync : integer range 1 to 2 := 2;
rmii : integer range 0 to 1 := 0);
port(
rst : in std_ulogic;
clk : in std_ulogic;
rxi : in host_rx_type;
rxo : out rx_host_type
);
end component;
component greth_tx is
generic(
ifg_gap : integer := 24;
attempt_limit : integer := 16;
backoff_limit : integer := 10;
nsync : integer range 1 to 2 := 2;
rmii : integer range 0 to 1 := 0);
port(
rst : in std_ulogic;
clk : in std_ulogic;
txi : in host_tx_type;
txo : out tx_host_type
);
end component;
component eth_rstgen is
generic(acthigh : integer := 0);
port (
rstin : in std_ulogic;
clk : in std_ulogic;
clklock : in std_ulogic;
rstout : out std_ulogic;
rstoutraw : out std_ulogic
);
end component;
component greth_gbit_tx is
generic(
ifg_gap : integer := 24;
attempt_limit : integer := 16;
backoff_limit : integer := 10;
nsync : integer range 1 to 2 := 2);
port(
rst : in std_ulogic;
clk : in std_ulogic;
txi : in gbit_host_tx_type;
txo : out gbit_tx_host_type);
end component;
component greth_gbit_gtx is
generic(
ifg_gap : integer := 24;
attempt_limit : integer := 16;
backoff_limit : integer := 10;
nsync : integer range 1 to 2 := 2);
port(
rst : in std_ulogic;
clk : in std_ulogic;
gtxi : in gbit_host_gtx_type;
gtxo : out gbit_gtx_host_type
);
end component;
component greth_gbit_rx is
generic(
nsync : integer range 1 to 2 := 2);
port(
rst : in std_ulogic;
clk : in std_ulogic;
rxi : in gbit_host_rx_type;
rxo : out gbit_rx_host_type);
end component;
component eth_ahb_mst is
port(
rst : in std_ulogic;
clk : in std_ulogic;
ahbmi : in ahbc_mst_in_type;
ahbmo : out ahbc_mst_out_type;
tmsti : in eth_tx_ahb_in_type;
tmsto : out eth_tx_ahb_out_type;
rmsti : in eth_rx_ahb_in_type;
rmsto : out eth_rx_ahb_out_type
);
end component;
component eth_ahb_mst_gbit is
port(
rst : in std_ulogic;
clk : in std_ulogic;
ahbmi : in ahbc_mst_in_type;
ahbmo : out ahbc_mst_out_type;
tmsti : in eth_tx_ahb_in_type;
tmsto : out eth_tx_ahb_out_type;
rmsti : in eth_rx_gbit_ahb_in_type;
rmsto : out eth_rx_ahb_out_type);
end component;
function mirror(din : in std_logic_vector) return std_logic_vector;
function crc32_4(d : in std_logic_vector(3 downto 0);
crc : in std_logic_vector(31 downto 0))
return std_logic_vector;
function crc16_2(d1 : in std_logic_vector(15 downto 0);
d2 : in std_logic_vector(25 downto 0))
return std_logic_vector;
function crc16(d1 : in std_logic_vector(15 downto 0);
d2 : in std_logic_vector(15 downto 0))
return std_logic_vector;
function validlen(len : in std_logic_vector(10 downto 0);
bcnt : in std_logic_vector(10 downto 0);
usesz : in std_ulogic)
return std_ulogic;
function getfifosize(edcl, fifosize, ebufsize : in integer) return integer;
function setburstlength(fifosize : in integer) return integer;
function calccrc(d : in std_logic_vector(3 downto 0);
crc : in std_logic_vector(31 downto 0))
return std_logic_vector;
--16-bit one's complement adder
function crcadder(d1 : in std_logic_vector(15 downto 0);
d2 : in std_logic_vector(17 downto 0))
return std_logic_vector;
end package;
package body grethpkg is
function mirror(din : in std_logic_vector)
return std_logic_vector is
variable do : std_logic_vector(din'high downto din'low);
begin
for i in 0 to din'length-1 loop
do(din'high-i) := din(i+din'low);
end loop;
return do;
end function;
function crc32_4(d : in std_logic_vector(3 downto 0);
crc : in std_logic_vector(31 downto 0))
return std_logic_vector is
variable ncrc : std_logic_vector(31 downto 0);
variable tc : std_logic_vector(3 downto 0);
begin
tc(0) := d(0) xor crc(31); tc(1) := d(1) xor crc(30);
tc(2) := d(2) xor crc(29); tc(3) := d(3) xor crc(28);
ncrc(31) := crc(27);
ncrc(30) := crc(26);
ncrc(29) := tc(0) xor crc(25);
ncrc(28) := tc(1) xor crc(24);
ncrc(27) := tc(2) xor crc(23);
ncrc(26) := tc(0) xor tc(3) xor crc(22);
ncrc(25) := tc(0) xor tc(1) xor crc(21);
ncrc(24) := tc(1) xor tc(2) xor crc(20);
ncrc(23) := tc(2) xor tc(3) xor crc(19);
ncrc(22) := tc(3) xor crc(18);
ncrc(21) := crc(17);
ncrc(20) := crc(16);
ncrc(19) := tc(0) xor crc(15);
ncrc(18) := tc(1) xor crc(14);
ncrc(17) := tc(2) xor crc(13);
ncrc(16) := tc(3) xor crc(12);
ncrc(15) := tc(0) xor crc(11);
ncrc(14) := tc(0) xor tc(1) xor crc(10);
ncrc(13) := tc(0) xor tc(1) xor tc(2) xor crc(9);
ncrc(12) := tc(1) xor tc(2) xor tc(3) xor crc(8);
ncrc(11) := tc(0) xor tc(2) xor tc(3) xor crc(7);
ncrc(10) := tc(0) xor tc(1) xor tc(3) xor crc(6);
ncrc(9) := tc(1) xor tc(2) xor crc(5);
ncrc(8) := tc(0) xor tc(2) xor tc(3) xor crc(4);
ncrc(7) := tc(0) xor tc(1) xor tc(3) xor crc(3);
ncrc(6) := tc(1) xor tc(2) xor crc(2);
ncrc(5) := tc(0) xor tc(2) xor tc(3) xor crc(1);
ncrc(4) := tc(0) xor tc(1) xor tc(3) xor crc(0);
ncrc(3) := tc(0) xor tc(1) xor tc(2);
ncrc(2) := tc(1) xor tc(2) xor tc(3);
ncrc(1) := tc(2) xor tc(3);
ncrc(0) := tc(3);
return ncrc;
end function;
--16-bit one's complement adder
function crc16(d1 : in std_logic_vector(15 downto 0);
d2 : in std_logic_vector(15 downto 0))
return std_logic_vector is
variable vd1 : std_logic_vector(16 downto 0);
variable vd2 : std_logic_vector(16 downto 0);
variable sum : std_logic_vector(16 downto 0);
begin
vd1 := '0' & d1; vd2 := '0' & d2;
sum := vd1 + vd2;
sum(15 downto 0) := sum(15 downto 0) + sum(16);
return sum(15 downto 0);
end function;
--16-bit one's complement adder for ip/tcp checksum detection
function crc16_2(d1 : in std_logic_vector(15 downto 0);
d2 : in std_logic_vector(25 downto 0))
return std_logic_vector is
variable vd1 : std_logic_vector(25 downto 0);
variable vd2 : std_logic_vector(25 downto 0);
variable sum : std_logic_vector(25 downto 0);
begin
vd1 := "0000000000" & d1; vd2 := d2;
sum := vd1 + vd2;
return sum;
end function;
function validlen(len : in std_logic_vector(10 downto 0);
bcnt : in std_logic_vector(10 downto 0);
usesz : in std_ulogic)
return std_ulogic is
variable valid : std_ulogic;
begin
valid := '1';
if usesz = '1' then
if len > minpload then
if bcnt /= len then
valid := '0';
end if;
else
if bcnt /= minpload then
valid := '0';
end if;
end if;
end if;
return valid;
end function;
function setburstlength(fifosize : in integer) return integer is
begin
if fifosize <= 64 then
return fifosize/2;
else
return 32;
end if;
end function;
function getfifosize(edcl, fifosize, ebufsize : in integer) return integer is
begin
if (edcl /= 0) and (ebufsize > fifosize) then
return ebufsize;
else
return fifosize;
end if;
end function;
function calccrc(d : in std_logic_vector(3 downto 0);
crc : in std_logic_vector(31 downto 0))
return std_logic_vector is
variable ncrc : std_logic_vector(31 downto 0);
variable tc : std_logic_vector(3 downto 0);
begin
tc(0) := d(0) xor crc(31); tc(1) := d(1) xor crc(30);
tc(2) := d(2) xor crc(29); tc(3) := d(3) xor crc(28);
ncrc(31) := crc(27);
ncrc(30) := crc(26);
ncrc(29) := tc(0) xor crc(25);
ncrc(28) := tc(1) xor crc(24);
ncrc(27) := tc(2) xor crc(23);
ncrc(26) := tc(0) xor tc(3) xor crc(22);
ncrc(25) := tc(0) xor tc(1) xor crc(21);
ncrc(24) := tc(1) xor tc(2) xor crc(20);
ncrc(23) := tc(2) xor tc(3) xor crc(19);
ncrc(22) := tc(3) xor crc(18);
ncrc(21) := crc(17);
ncrc(20) := crc(16);
ncrc(19) := tc(0) xor crc(15);
ncrc(18) := tc(1) xor crc(14);
ncrc(17) := tc(2) xor crc(13);
ncrc(16) := tc(3) xor crc(12);
ncrc(15) := tc(0) xor crc(11);
ncrc(14) := tc(0) xor tc(1) xor crc(10);
ncrc(13) := tc(0) xor tc(1) xor tc(2) xor crc(9);
ncrc(12) := tc(1) xor tc(2) xor tc(3) xor crc(8);
ncrc(11) := tc(0) xor tc(2) xor tc(3) xor crc(7);
ncrc(10) := tc(0) xor tc(1) xor tc(3) xor crc(6);
ncrc(9) := tc(1) xor tc(2) xor crc(5);
ncrc(8) := tc(0) xor tc(2) xor tc(3) xor crc(4);
ncrc(7) := tc(0) xor tc(1) xor tc(3) xor crc(3);
ncrc(6) := tc(1) xor tc(2) xor crc(2);
ncrc(5) := tc(0) xor tc(2) xor tc(3) xor crc(1);
ncrc(4) := tc(0) xor tc(1) xor tc(3) xor crc(0);
ncrc(3) := tc(0) xor tc(1) xor tc(2);
ncrc(2) := tc(1) xor tc(2) xor tc(3);
ncrc(1) := tc(2) xor tc(3);
ncrc(0) := tc(3);
return ncrc;
end function;
--16-bit one's complement adder
function crcadder(d1 : in std_logic_vector(15 downto 0);
d2 : in std_logic_vector(17 downto 0))
return std_logic_vector is
variable vd1 : std_logic_vector(17 downto 0);
variable vd2 : std_logic_vector(17 downto 0);
variable sum : std_logic_vector(17 downto 0);
begin
vd1 := "00" & d1; vd2 := d2;
sum := vd1 + vd2;
return sum;
end function;
end package body;
| mit | bae244506059a7fcf73dc4169439f627 | 0.549638 | 3.280209 | false | false | false | false |
impedimentToProgress/UCI-BlueChip | AttackFiles/Attacks/privEsc/lib/gaisler/can/can_mc.vhd | 2 | 6,104 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: can_oc
-- File: can_oc.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: AHB interface for the OpenCores CAN MAC
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
library techmap;
use techmap.gencomp.all;
library gaisler;
use gaisler.can.all;
entity can_mc is
generic (
slvndx : integer := 0;
ioaddr : integer := 16#000#;
iomask : integer := 16#FF0#;
irq : integer := 0;
memtech : integer := DEFMEMTECH;
ncores : integer range 1 to 8 := 1;
sepirq : integer range 0 to 1 := 0;
syncrst : integer range 0 to 1 := 0;
ft : integer range 0 to 1 := 0);
port (
resetn : in std_logic;
clk : in std_logic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
can_rxi : in std_logic_vector(0 to 7);
can_txo : out std_logic_vector(0 to 7)
);
end;
architecture rtl of can_mc is
constant REVISION : amba_version_type := ncores-1;
constant hconfig : ahb_config_type := (
0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_CANAHB, 0, REVISION, irq),
4 => ahb_iobar(ioaddr, iomask), others => zero32);
type ahbregs is record
hsel : std_ulogic;
hwrite : std_ulogic;
hwrite2 : std_ulogic;
htrans : std_logic_vector(1 downto 0);
haddr : std_logic_vector(10 downto 0);
hwdata : std_logic_vector(7 downto 0);
herr : std_ulogic;
hready : std_ulogic;
ws : std_logic_vector(1 downto 0);
irqi : std_logic_vector(ncores-1 downto 0);
irqo : std_logic_vector(ncores-1 downto 0);
end record;
subtype cdata is std_logic_vector(7 downto 0);
type cdataarr is array (0 to 7) of cdata;
signal data_out : cdataarr;
signal reset : std_logic;
signal irqo : std_logic_vector(ncores-1 downto 0);
signal cs : std_logic_vector(7 downto 0);
signal vcc, gnd : std_ulogic;
signal r, rin : ahbregs;
begin
gnd <= '0'; vcc <= '1'; reset <= not resetn;
comb : process(ahbsi, r, resetn, data_out, irqo)
variable v : ahbregs;
variable hresp : std_logic_vector(1 downto 0);
variable lcs, dataout : std_logic_vector(7 downto 0);
variable irqvec : std_logic_vector(NAHBIRQ-1 downto 0);
begin
v := r;
if (r.hsel = '1' ) and (r.ws /= "11") then v.ws := r.ws + 1; end if;
if ahbsi.hready = '1' then
v.hsel := ahbsi.hsel(slvndx);
v.haddr := ahbsi.haddr(10 downto 0);
v.htrans := ahbsi.htrans;
v.hwrite := ahbsi.hwrite;
v.herr := orv(ahbsi.hsize) and ahbsi.hwrite;
v.ws := "00";
end if;
v.hready := (r.hsel and r.ws(1) and not r.ws(0)) or not resetn
or (ahbsi.hready and not ahbsi.htrans(1)) or not v.hsel;
v.hwrite2 := r.hwrite and r.hsel and r.htrans(1) and r.ws(1)
and not r.ws(0) and not r.herr;
if (r.herr and r.ws(1)) = '1' then hresp := HRESP_ERROR;
else hresp := HRESP_OKAY; end if;
case r.haddr(1 downto 0) is
when "00" => v.hwdata := ahbsi.hwdata(31 downto 24);
when "01" => v.hwdata := ahbsi.hwdata(23 downto 16);
when "10" => v.hwdata := ahbsi.hwdata(15 downto 8);
when others => v.hwdata := ahbsi.hwdata(7 downto 0);
end case;
if ncores > 1 then
if r.hsel = '1' then lcs := decode(r.haddr(10 downto 8));
else lcs := (others => '0'); end if;
dataout := data_out(conv_integer(r.haddr(10 downto 8)));
else dataout := data_out(0); lcs := "0000000" & r.hsel; end if;
-- Interrupt goes to low when appeard and is normal high
-- but the irq controller from leon is active high and the interrupt should appear only
-- for 1 Clk cycle,
v.irqi := irqo; v.irqo:= (r.irqi and not irqo);
irqvec := (others => '0');
if sepirq = 1 then irqvec(ncores-1+irq downto irq) := r.irqo;
else irqvec(irq) := orv(r.irqo); end if;
ahbso.hirq <= irqvec;
ahbso.hrdata <= dataout & dataout & dataout & dataout;
cs <= lcs;
ahbso.hresp <= hresp; rin <= v;
end process;
reg : process(clk)
begin if clk'event and clk = '1' then r <= rin; end if; end process;
cgen : for i in 0 to ncores-1 generate
c0 : if i < ncores generate
cmod : can_mod generic map (memtech, syncrst, ft)
port map (reset, clk, cs(i), r.hwrite2, r.haddr(7 downto 0), r.hwdata,
data_out(i), irqo(i), can_rxi(i), can_txo(i));
end generate;
c1 : if i >= ncores generate
can_txo(i) <= '0'; data_out(i) <= (others => '0'); irqo(i) <= '1';
end generate;
end generate;
ahbso.hconfig <= hconfig;
ahbso.hindex <= slvndx;
ahbso.hsplit <= (others => '0');
ahbso.hcache <= '0';
ahbso.hready <= r.hready;
-- pragma translate_off
bootmsg : report_version
generic map (
"can_oc" & tost(slvndx) &
": SJA1000 Compatible CAN MAC, #cores " & tost(REVISION+1) & ", irq " & tost(irq));
-- pragma translate_on
end;
| mit | 234000e7e90be776bce3bf8f9b1ecc9b | 0.584699 | 3.46228 | false | false | false | false |
lxp32/lxp32-cpu | verify/lxp32/src/platform/timer.vhd | 2 | 2,380 | ---------------------------------------------------------------------
-- Timer
--
-- Part of the LXP32 test platform
--
-- Copyright (c) 2016 by Alex I. Kuznetsov
--
-- A simple programmable interval timer.
--
-- Note: regardless of whether this description is synthesizable,
-- it was designed exclusively for simulation purposes.
---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity timer is
port(
clk_i: in std_logic;
rst_i: in std_logic;
wbs_cyc_i: in std_logic;
wbs_stb_i: in std_logic;
wbs_we_i: in std_logic;
wbs_sel_i: in std_logic_vector(3 downto 0);
wbs_ack_o: out std_logic;
wbs_adr_i: in std_logic_vector(27 downto 2);
wbs_dat_i: in std_logic_vector(31 downto 0);
wbs_dat_o: out std_logic_vector(31 downto 0);
elapsed_o: out std_logic
);
end entity;
architecture rtl of timer is
signal pulses: unsigned(31 downto 0):=(others=>'0');
signal interval: unsigned(31 downto 0):=(others=>'0');
signal cnt: unsigned(31 downto 0):=(others=>'0');
signal elapsed: std_logic:='0';
begin
process (clk_i) is
begin
if rising_edge(clk_i) then
if rst_i='1' then
pulses<=(others=>'0');
interval<=(others=>'0');
cnt<=(others=>'0');
elapsed<='0';
else
elapsed<='0';
if pulses/=X"00000000" or cnt/=X"00000000" then
if cnt=X"00000000" then
if pulses/=X"FFFFFFFF" then
pulses<=pulses-1;
end if;
if pulses/=X"00000000" then
cnt<=interval;
end if;
else
cnt<=cnt-1;
end if;
if cnt=X"00000001" then
elapsed<='1';
end if;
end if;
if wbs_cyc_i='1' and wbs_stb_i='1' and wbs_we_i='1' then
for i in wbs_sel_i'range loop
if wbs_sel_i(i)='1' then
if wbs_adr_i="00"&X"000000" then
pulses(i*8+7 downto i*8)<=
unsigned(wbs_dat_i(i*8+7 downto i*8));
cnt<=(others=>'0');
end if;
if wbs_adr_i="00"&X"000001" then
interval(i*8+7 downto i*8)<=
unsigned(wbs_dat_i(i*8+7 downto i*8));
cnt<=(others=>'0');
end if;
end if;
end loop;
end if;
end if;
end if;
end process;
wbs_ack_o<=wbs_cyc_i and wbs_stb_i;
wbs_dat_o<=std_logic_vector(pulses) when wbs_adr_i="00"&X"000000" else
std_logic_vector(interval) when wbs_adr_i="00"&X"000001" else
(others=>'-');
elapsed_o<=elapsed;
end architecture;
| mit | 5721e74662e399e20d4706b895469a22 | 0.582773 | 2.881356 | false | false | false | false |
amerc/phimii | ipcore_dir/RxTstFIFO2K/simulation/RxTstFIFO2K_pctrl.vhd | 2 | 18,564 |
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: RxTstFIFO2K_pctrl.vhd
--
-- Description:
-- Used for protocol control on write and read interface stimulus and status generation
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_misc.all;
LIBRARY work;
USE work.RxTstFIFO2K_pkg.ALL;
ENTITY RxTstFIFO2K_pctrl IS
GENERIC(
AXI_CHANNEL : STRING :="NONE";
C_APPLICATION_TYPE : INTEGER := 0;
C_DIN_WIDTH : INTEGER := 0;
C_DOUT_WIDTH : INTEGER := 0;
C_WR_PNTR_WIDTH : INTEGER := 0;
C_RD_PNTR_WIDTH : INTEGER := 0;
C_CH_TYPE : INTEGER := 0;
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 2;
TB_SEED : INTEGER := 2
);
PORT(
RESET_WR : IN STD_LOGIC;
RESET_RD : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
FULL : IN STD_LOGIC;
EMPTY : IN STD_LOGIC;
ALMOST_FULL : IN STD_LOGIC;
ALMOST_EMPTY : IN STD_LOGIC;
DATA_IN : IN STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0);
DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
DOUT_CHK : IN STD_LOGIC;
PRC_WR_EN : OUT STD_LOGIC;
PRC_RD_EN : OUT STD_LOGIC;
RESET_EN : OUT STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END ENTITY;
ARCHITECTURE fg_pc_arch OF RxTstFIFO2K_pctrl IS
CONSTANT C_DATA_WIDTH : INTEGER := if_then_else(C_DIN_WIDTH > C_DOUT_WIDTH,C_DIN_WIDTH,C_DOUT_WIDTH);
CONSTANT LOOP_COUNT : INTEGER := divroundup(C_DATA_WIDTH,8);
CONSTANT D_WIDTH_DIFF : INTEGER := log2roundup(C_DOUT_WIDTH/C_DIN_WIDTH);
SIGNAL data_chk_i : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0');
SIGNAL full_chk_i : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0');
SIGNAL empty_chk_i : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0');
SIGNAL status_i : STD_LOGIC_VECTOR(4 DOWNTO 0):= (OTHERS => '0');
SIGNAL status_d1_i : STD_LOGIC_VECTOR(4 DOWNTO 0):= (OTHERS => '0');
SIGNAL wr_en_gen : STD_LOGIC_VECTOR(7 DOWNTO 0):= (OTHERS => '0');
SIGNAL rd_en_gen : STD_LOGIC_VECTOR(7 DOWNTO 0):= (OTHERS => '0');
SIGNAL wr_cntr : STD_LOGIC_VECTOR(C_WR_PNTR_WIDTH-2 DOWNTO 0) := (OTHERS => '0');
SIGNAL full_as_timeout : STD_LOGIC_VECTOR(C_WR_PNTR_WIDTH DOWNTO 0) := (OTHERS => '0');
SIGNAL full_ds_timeout : STD_LOGIC_VECTOR(C_WR_PNTR_WIDTH DOWNTO 0) := (OTHERS => '0');
SIGNAL rd_cntr : STD_LOGIC_VECTOR(C_RD_PNTR_WIDTH-2 DOWNTO 0) := (OTHERS => '0');
SIGNAL empty_as_timeout : STD_LOGIC_VECTOR(C_RD_PNTR_WIDTH DOWNTO 0) := (OTHERS => '0');
SIGNAL empty_ds_timeout : STD_LOGIC_VECTOR(C_RD_PNTR_WIDTH DOWNTO 0):= (OTHERS => '0');
SIGNAL wr_en_i : STD_LOGIC := '0';
SIGNAL rd_en_i : STD_LOGIC := '0';
SIGNAL state : STD_LOGIC := '0';
SIGNAL wr_control : STD_LOGIC := '0';
SIGNAL rd_control : STD_LOGIC := '0';
SIGNAL stop_on_err : STD_LOGIC := '0';
SIGNAL sim_stop_cntr : STD_LOGIC_VECTOR(7 DOWNTO 0):= conv_std_logic_vector(if_then_else(C_CH_TYPE=2,64,TB_STOP_CNT),8);
SIGNAL sim_done_i : STD_LOGIC := '0';
SIGNAL rdw_gt_wrw : STD_LOGIC_VECTOR(D_WIDTH_DIFF-1 DOWNTO 0) := (OTHERS => '1');
SIGNAL wrw_gt_rdw : STD_LOGIC_VECTOR(D_WIDTH_DIFF-1 DOWNTO 0) := (OTHERS => '1');
SIGNAL rd_activ_cont : STD_LOGIC_VECTOR(25 downto 0):= (OTHERS => '0');
SIGNAL prc_we_i : STD_LOGIC := '0';
SIGNAL prc_re_i : STD_LOGIC := '0';
SIGNAL reset_en_i : STD_LOGIC := '0';
SIGNAL sim_done_d1 : STD_LOGIC := '0';
SIGNAL sim_done_wr1 : STD_LOGIC := '0';
SIGNAL sim_done_wr2 : STD_LOGIC := '0';
SIGNAL empty_d1 : STD_LOGIC := '0';
SIGNAL empty_wr_dom1 : STD_LOGIC := '0';
SIGNAL state_d1 : STD_LOGIC := '0';
SIGNAL state_rd_dom1 : STD_LOGIC := '0';
SIGNAL rd_en_d1 : STD_LOGIC := '0';
SIGNAL rd_en_wr1 : STD_LOGIC := '0';
SIGNAL wr_en_d1 : STD_LOGIC := '0';
SIGNAL wr_en_rd1 : STD_LOGIC := '0';
SIGNAL full_chk_d1 : STD_LOGIC := '0';
SIGNAL full_chk_rd1 : STD_LOGIC := '0';
SIGNAL empty_wr_dom2 : STD_LOGIC := '0';
SIGNAL state_rd_dom2 : STD_LOGIC := '0';
SIGNAL state_rd_dom3 : STD_LOGIC := '0';
SIGNAL rd_en_wr2 : STD_LOGIC := '0';
SIGNAL wr_en_rd2 : STD_LOGIC := '0';
SIGNAL full_chk_rd2 : STD_LOGIC := '0';
SIGNAL reset_en_d1 : STD_LOGIC := '0';
SIGNAL reset_en_rd1 : STD_LOGIC := '0';
SIGNAL reset_en_rd2 : STD_LOGIC := '0';
SIGNAL data_chk_wr_d1 : STD_LOGIC := '0';
SIGNAL data_chk_rd1 : STD_LOGIC := '0';
SIGNAL data_chk_rd2 : STD_LOGIC := '0';
SIGNAL post_rst_dly_wr : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '1');
SIGNAL post_rst_dly_rd : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '1');
BEGIN
status_i <= data_chk_i & full_chk_rd2 & empty_chk_i & '0' & '0';
STATUS <= status_d1_i & '0' & '0' & rd_activ_cont(rd_activ_cont'high);
prc_we_i <= wr_en_i WHEN sim_done_wr2 = '0' ELSE '0';
prc_re_i <= rd_en_i WHEN sim_done_i = '0' ELSE '0';
SIM_DONE <= sim_done_i;
wrw_gt_rdw <= (OTHERS => '1');
PROCESS(RD_CLK)
BEGIN
IF (RD_CLK'event AND RD_CLK='1') THEN
IF(prc_re_i = '1') THEN
rd_activ_cont <= rd_activ_cont + "1";
END IF;
END IF;
END PROCESS;
PROCESS(sim_done_i)
BEGIN
assert sim_done_i = '0'
report "Simulation Complete for:" & AXI_CHANNEL
severity note;
END PROCESS;
-----------------------------------------------------
-- SIM_DONE SIGNAL GENERATION
-----------------------------------------------------
PROCESS (RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
--sim_done_i <= '0';
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF((OR_REDUCE(sim_stop_cntr) = '0' AND TB_STOP_CNT /= 0) OR stop_on_err = '1') THEN
sim_done_i <= '1';
END IF;
END IF;
END PROCESS;
-- TB Timeout/Stop
fifo_tb_stop_run:IF(TB_STOP_CNT /= 0) GENERATE
PROCESS (RD_CLK)
BEGIN
IF (RD_CLK'event AND RD_CLK='1') THEN
IF(state_rd_dom2 = '0' AND state_rd_dom3 = '1') THEN
sim_stop_cntr <= sim_stop_cntr - "1";
END IF;
END IF;
END PROCESS;
END GENERATE fifo_tb_stop_run;
-- Stop when error found
PROCESS (RD_CLK)
BEGIN
IF (RD_CLK'event AND RD_CLK='1') THEN
IF(sim_done_i = '0') THEN
status_d1_i <= status_i OR status_d1_i;
END IF;
IF(FREEZEON_ERROR = 1 AND status_i /= "0") THEN
stop_on_err <= '1';
END IF;
END IF;
END PROCESS;
-----------------------------------------------------
-----------------------------------------------------
-- CHECKS FOR FIFO
-----------------------------------------------------
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
post_rst_dly_rd <= (OTHERS => '1');
ELSIF (RD_CLK'event AND RD_CLK='1') THEN
post_rst_dly_rd <= post_rst_dly_rd-post_rst_dly_rd(4);
END IF;
END PROCESS;
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
post_rst_dly_wr <= (OTHERS => '1');
ELSIF (WR_CLK'event AND WR_CLK='1') THEN
post_rst_dly_wr <= post_rst_dly_wr-post_rst_dly_wr(4);
END IF;
END PROCESS;
-- FULL de-assert Counter
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
full_ds_timeout <= (OTHERS => '0');
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(state = '1') THEN
IF(rd_en_wr2 = '1' AND wr_en_i = '0' AND FULL = '1' AND AND_REDUCE(wrw_gt_rdw) = '1') THEN
full_ds_timeout <= full_ds_timeout + '1';
END IF;
ELSE
full_ds_timeout <= (OTHERS => '0');
END IF;
END IF;
END PROCESS;
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
rdw_gt_wrw <= (OTHERS => '1');
ELSIF (RD_CLK'event AND RD_CLK='1') THEN
IF(wr_en_rd2 = '1' AND rd_en_i= '0' AND EMPTY = '1') THEN
rdw_gt_wrw <= rdw_gt_wrw + '1';
END IF;
END IF;
END PROCESS;
-- EMPTY deassert counter
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
empty_ds_timeout <= (OTHERS => '0');
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(state = '0') THEN
IF(wr_en_rd2 = '1' AND rd_en_i = '0' AND EMPTY = '1' AND AND_REDUCE(rdw_gt_wrw) = '1') THEN
empty_ds_timeout <= empty_ds_timeout + '1';
END IF;
ELSE
empty_ds_timeout <= (OTHERS => '0');
END IF;
END IF;
END PROCESS;
-- Full check signal generation
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
full_chk_i <= '0';
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(C_APPLICATION_TYPE = 1 AND (AXI_CHANNEL = "WACH" OR AXI_CHANNEL = "RACH" OR AXI_CHANNEL = "AXI4_Stream")) THEN
full_chk_i <= '0';
ELSE
full_chk_i <= AND_REDUCE(full_as_timeout) OR
AND_REDUCE(full_ds_timeout);
END IF;
END IF;
END PROCESS;
-- Empty checks
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
empty_chk_i <= '0';
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(C_APPLICATION_TYPE = 1 AND (AXI_CHANNEL = "WACH" OR AXI_CHANNEL = "RACH" OR AXI_CHANNEL = "AXI4_Stream")) THEN
empty_chk_i <= '0';
ELSE
empty_chk_i <= AND_REDUCE(empty_as_timeout) OR
AND_REDUCE(empty_ds_timeout);
END IF;
END IF;
END PROCESS;
fifo_d_chk:IF(C_CH_TYPE /= 2) GENERATE
PRC_WR_EN <= prc_we_i AFTER 100 ns;
PRC_RD_EN <= prc_re_i AFTER 50 ns;
data_chk_i <= dout_chk;
END GENERATE fifo_d_chk;
-----------------------------------------------------
-----------------------------------------------------
-- SYNCHRONIZERS B/W WRITE AND READ DOMAINS
-----------------------------------------------------
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
empty_wr_dom1 <= '1';
empty_wr_dom2 <= '1';
state_d1 <= '0';
wr_en_d1 <= '0';
rd_en_wr1 <= '0';
rd_en_wr2 <= '0';
full_chk_d1 <= '0';
reset_en_d1 <= '0';
sim_done_wr1 <= '0';
sim_done_wr2 <= '0';
ELSIF (WR_CLK'event AND WR_CLK='1') THEN
sim_done_wr1 <= sim_done_d1;
sim_done_wr2 <= sim_done_wr1;
reset_en_d1 <= reset_en_i;
state_d1 <= state;
empty_wr_dom1 <= empty_d1;
empty_wr_dom2 <= empty_wr_dom1;
wr_en_d1 <= wr_en_i;
rd_en_wr1 <= rd_en_d1;
rd_en_wr2 <= rd_en_wr1;
full_chk_d1 <= full_chk_i;
END IF;
END PROCESS;
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
empty_d1 <= '1';
state_rd_dom1 <= '0';
state_rd_dom2 <= '0';
state_rd_dom3 <= '0';
wr_en_rd1 <= '0';
wr_en_rd2 <= '0';
rd_en_d1 <= '0';
full_chk_rd1 <= '0';
full_chk_rd2 <= '0';
reset_en_rd1 <= '0';
reset_en_rd2 <= '0';
sim_done_d1 <= '0';
ELSIF (RD_CLK'event AND RD_CLK='1') THEN
sim_done_d1 <= sim_done_i;
reset_en_rd1 <= reset_en_d1;
reset_en_rd2 <= reset_en_rd1;
empty_d1 <= EMPTY;
rd_en_d1 <= rd_en_i;
state_rd_dom1 <= state_d1;
state_rd_dom2 <= state_rd_dom1;
state_rd_dom3 <= state_rd_dom2;
wr_en_rd1 <= wr_en_d1;
wr_en_rd2 <= wr_en_rd1;
full_chk_rd1 <= full_chk_d1;
full_chk_rd2 <= full_chk_rd1;
END IF;
END PROCESS;
RESET_EN <= reset_en_rd2;
data_fifo_en:IF(C_CH_TYPE /= 2) GENERATE
-----------------------------------------------------
-- WR_EN GENERATION
-----------------------------------------------------
gen_rand_wr_en:RxTstFIFO2K_rng
GENERIC MAP(
WIDTH => 8,
SEED => TB_SEED+1
)
PORT MAP(
CLK => WR_CLK,
RESET => RESET_WR,
RANDOM_NUM => wr_en_gen,
ENABLE => '1'
);
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
wr_en_i <= '0';
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(state = '1') THEN
wr_en_i <= wr_en_gen(0) AND wr_en_gen(7) AND wr_en_gen(2) AND wr_control;
ELSE
wr_en_i <= (wr_en_gen(3) OR wr_en_gen(4) OR wr_en_gen(2)) AND (NOT post_rst_dly_wr(4));
END IF;
END IF;
END PROCESS;
-----------------------------------------------------
-- WR_EN CONTROL
-----------------------------------------------------
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
wr_cntr <= (OTHERS => '0');
wr_control <= '1';
full_as_timeout <= (OTHERS => '0');
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(state = '1') THEN
IF(wr_en_i = '1') THEN
wr_cntr <= wr_cntr + "1";
END IF;
full_as_timeout <= (OTHERS => '0');
ELSE
wr_cntr <= (OTHERS => '0');
IF(rd_en_wr2 = '0') THEN
IF(wr_en_i = '1') THEN
full_as_timeout <= full_as_timeout + "1";
END IF;
ELSE
full_as_timeout <= (OTHERS => '0');
END IF;
END IF;
wr_control <= NOT wr_cntr(wr_cntr'high);
END IF;
END PROCESS;
-----------------------------------------------------
-- RD_EN GENERATION
-----------------------------------------------------
gen_rand_rd_en:RxTstFIFO2K_rng
GENERIC MAP(
WIDTH => 8,
SEED => TB_SEED
)
PORT MAP(
CLK => RD_CLK,
RESET => RESET_RD,
RANDOM_NUM => rd_en_gen,
ENABLE => '1'
);
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
rd_en_i <= '0';
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(state_rd_dom2 = '0') THEN
rd_en_i <= rd_en_gen(1) AND rd_en_gen(5) AND rd_en_gen(3) AND rd_control AND (NOT post_rst_dly_rd(4));
ELSE
rd_en_i <= rd_en_gen(0) OR rd_en_gen(6);
END IF;
END IF;
END PROCESS;
-----------------------------------------------------
-- RD_EN CONTROL
-----------------------------------------------------
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
rd_cntr <= (OTHERS => '0');
rd_control <= '1';
empty_as_timeout <= (OTHERS => '0');
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(state_rd_dom2 = '0') THEN
IF(rd_en_i = '1') THEN
rd_cntr <= rd_cntr + "1";
END IF;
empty_as_timeout <= (OTHERS => '0');
ELSE
rd_cntr <= (OTHERS => '0');
IF(wr_en_rd2 = '0') THEN
IF(rd_en_i = '1') THEN
empty_as_timeout <= empty_as_timeout + "1";
END IF;
ELSE
empty_as_timeout <= (OTHERS => '0');
END IF;
END IF;
rd_control <= NOT rd_cntr(rd_cntr'high);
END IF;
END PROCESS;
-----------------------------------------------------
-- STIMULUS CONTROL
-----------------------------------------------------
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
state <= '0';
reset_en_i <= '0';
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
CASE state IS
WHEN '0' =>
IF(FULL = '1' AND empty_wr_dom2 = '0') THEN
state <= '1';
reset_en_i <= '0';
END IF;
WHEN '1' =>
IF(empty_wr_dom2 = '1' AND FULL = '0') THEN
state <= '0';
reset_en_i <= '1';
END IF;
WHEN OTHERS => state <= state;
END CASE;
END IF;
END PROCESS;
END GENERATE data_fifo_en;
END ARCHITECTURE;
| mit | 4ed8bb38f7f89eb4fd26d60bd48c4439 | 0.509535 | 3.240922 | false | false | false | false |
lxp32/lxp32-cpu | verify/lxp32/src/platform/coprocessor.vhd | 1 | 2,132 | ---------------------------------------------------------------------
-- Coprocessor
--
-- Part of the LXP32 test platform
--
-- Copyright (c) 2016 by Alex I. Kuznetsov
--
-- Performs a simple arithmetic operation, uses interrupt to wake
-- up the CPU.
--
-- Note: regardless of whether this description is synthesizable,
-- it was designed exclusively for simulation purposes.
---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity coprocessor is
port(
clk_i: in std_logic;
rst_i: in std_logic;
wbs_cyc_i: in std_logic;
wbs_stb_i: in std_logic;
wbs_we_i: in std_logic;
wbs_sel_i: in std_logic_vector(3 downto 0);
wbs_ack_o: out std_logic;
wbs_adr_i: in std_logic_vector(27 downto 2);
wbs_dat_i: in std_logic_vector(31 downto 0);
wbs_dat_o: out std_logic_vector(31 downto 0);
irq_o: out std_logic
);
end entity;
architecture rtl of coprocessor is
signal value: unsigned(31 downto 0):=(others=>'0');
signal result: unsigned(31 downto 0):=(others=>'0');
signal cnt: integer range 0 to 50:=0;
signal irq: std_logic:='0';
begin
process (clk_i) is
begin
if rising_edge(clk_i) then
if rst_i='1' then
value<=(others=>'0');
cnt<=0;
irq<='0';
else
if cnt>0 then
cnt<=cnt-1;
end if;
if cnt=1 then
irq<='1';
else
irq<='0';
end if;
if wbs_cyc_i='1' and wbs_stb_i='1' and wbs_we_i='1' then
for i in wbs_sel_i'range loop
if wbs_sel_i(i)='1' then
if wbs_adr_i="00"&X"000000" then
value(i*8+7 downto i*8)<=
unsigned(wbs_dat_i(i*8+7 downto i*8));
cnt<=50;
end if;
end if;
end loop;
end if;
end if;
end if;
end process;
process (clk_i) is
begin
if rising_edge(clk_i) then
if rst_i='1' then
result<=(others=>'0');
else
result<=shift_left(value,1)+value;
end if;
end if;
end process;
wbs_ack_o<=wbs_cyc_i and wbs_stb_i;
wbs_dat_o<=std_logic_vector(value) when wbs_adr_i="00"&X"000000" else
std_logic_vector(result) when wbs_adr_i="00"&X"000001" else
(others=>'-');
irq_o<=irq;
end architecture;
| mit | 820552620b6078d2a5ebbc677941dda6 | 0.592871 | 2.808959 | false | false | false | false |
impedimentToProgress/UCI-BlueChip | AttackFiles/Attacks/privEsc/lib/gaisler/can/can_oc.vhd | 2 | 5,485 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: can_oc
-- File: can_oc.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: AHB interface for the OpenCores CAN MAC
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
library techmap;
use techmap.gencomp.all;
library gaisler;
use gaisler.can.all;
entity can_oc is
generic (
slvndx : integer := 0;
ioaddr : integer := 16#000#;
iomask : integer := 16#FF0#;
irq : integer := 0;
memtech : integer := DEFMEMTECH;
syncrst : integer := 0;
ft : integer := 0);
port (
resetn : in std_logic;
clk : in std_logic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
can_rxi : in std_logic;
can_txo : out std_logic
);
end;
architecture rtl of can_oc is
constant ncores : integer := 1;
constant sepirq : integer := 0;
constant REVISION : amba_version_type := ncores-1;
constant hconfig : ahb_config_type := (
0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_CANAHB, 0, REVISION, irq),
4 => ahb_iobar(ioaddr, iomask), others => zero32);
type ahbregs is record
hsel : std_ulogic;
hwrite : std_ulogic;
hwrite2 : std_ulogic;
htrans : std_logic_vector(1 downto 0);
haddr : std_logic_vector(10 downto 0);
hwdata : std_logic_vector(7 downto 0);
herr : std_ulogic;
hready : std_ulogic;
ws : std_logic_vector(1 downto 0);
irqi : std_logic_vector(ncores-1 downto 0);
irqo : std_logic_vector(ncores-1 downto 0);
end record;
subtype cdata is std_logic_vector(7 downto 0);
type cdataarr is array (0 to 7) of cdata;
signal data_out : cdataarr;
signal reset : std_logic;
signal irqo : std_logic_vector(ncores-1 downto 0);
signal vcc, gnd : std_ulogic;
signal r, rin : ahbregs;
begin
gnd <= '0'; vcc <= '1'; reset <= not resetn;
comb : process(ahbsi, r, resetn, data_out, irqo)
variable v : ahbregs;
variable hresp : std_logic_vector(1 downto 0);
variable dataout : std_logic_vector(7 downto 0);
variable irqvec : std_logic_vector(NAHBIRQ-1 downto 0);
begin
v := r;
if (r.hsel = '1' ) and (r.ws /= "11") then v.ws := r.ws + 1; end if;
if ahbsi.hready = '1' then
v.hsel := ahbsi.hsel(slvndx);
v.haddr := ahbsi.haddr(10 downto 0);
v.htrans := ahbsi.htrans;
v.hwrite := ahbsi.hwrite;
v.herr := orv(ahbsi.hsize) and ahbsi.hwrite;
v.ws := "00";
end if;
v.hready := (r.hsel and r.ws(1) and not r.ws(0)) or not resetn
or (ahbsi.hready and not ahbsi.htrans(1)) or not v.hsel;
v.hwrite2 := r.hwrite and r.hsel and r.htrans(1) and r.ws(1)
and not r.ws(0) and not r.herr;
if (r.herr and r.ws(1)) = '1' then hresp := HRESP_ERROR;
else hresp := HRESP_OKAY; end if;
case r.haddr(1 downto 0) is
when "00" => v.hwdata := ahbsi.hwdata(31 downto 24);
when "01" => v.hwdata := ahbsi.hwdata(23 downto 16);
when "10" => v.hwdata := ahbsi.hwdata(15 downto 8);
when others => v.hwdata := ahbsi.hwdata(7 downto 0);
end case;
dataout := data_out(0);
-- Interrupt goes to low when appeard and is normal high
-- but the irq controller from leon is active high and the interrupt should appear only
-- for 1 Clk cycle,
v.irqi := irqo; v.irqo:= (r.irqi and not irqo);
irqvec := (others => '0');
if sepirq = 1 then irqvec(ncores-1+irq downto irq) := r.irqo;
else irqvec(irq) := orv(r.irqo); end if;
ahbso.hirq <= irqvec;
ahbso.hrdata <= dataout & dataout & dataout & dataout;
ahbso.hresp <= hresp; rin <= v;
end process;
reg : process(clk)
begin if clk'event and clk = '1' then r <= rin; end if; end process;
cmod : can_mod generic map (memtech, syncrst, ft)
port map (reset, clk, r.hsel, r.hwrite2, r.haddr(7 downto 0), r.hwdata,
data_out(0), irqo(0), can_rxi, can_txo);
ahbso.hconfig <= hconfig;
ahbso.hindex <= slvndx;
ahbso.hsplit <= (others => '0');
ahbso.hcache <= '0';
ahbso.hready <= r.hready;
-- pragma translate_off
bootmsg : report_version
generic map (
"can_oc" & tost(slvndx) &
": SJA1000 Compatible CAN MAC, revision " & tost(REVISION) &
", irq " & tost(irq));
-- pragma translate_on
end;
| mit | 557385c13d3d7c2ed2cab1dd4bc6defa | 0.589426 | 3.531874 | false | false | false | false |
michaelfivez/ascon_hardware_implementation | ascon128128_iterated/API_plus_CipherCore/CypherCore.vhd | 1 | 14,103 | -------------------------------------------------------------------------------
--! @project Iterate hardware implementation of Asconv128128
--! @author Michael Fivez
--! @license This project is released under the GNU Public License.
--! The license and distribution terms for this file may be
--! found in the file LICENSE in this distribution or at
--! http://www.gnu.org/licenses/gpl-3.0.txt
--! @note This is an hardware implementation made for my graduation thesis
--! at the KULeuven, in the COSIC department (year 2015-2016)
--! The thesis is titled 'Energy efficient hardware implementations of CAESAR submissions',
--! and can be found on the COSIC website (www.esat.kuleuven.be/cosic/publications)
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.ALL;
use ieee.numeric_std.all;
entity CipherCore is
generic (
G_NPUB_SIZE : integer := 128; --! Npub size (bits)
G_NSEC_SIZE : integer := 128; --! Nsec size (bits)
G_DBLK_SIZE : integer := 128; --! Data Block size (bits)
G_KEY_SIZE : integer := 128; --! Key size (bits)
G_RDKEY_SIZE : integer := 128; --! Round Key size (bits)
G_TAG_SIZE : integer := 128; --! Tag size (bits)
G_BS_BYTES : integer := 4; --! The number of bits required to hold block size expressed in bytes = log2_ceil(max(G_ABLK_SIZE,G_DBLK_SIZE)/8)
G_CTR_AD_SIZE : integer := 64; --! Maximum size for the counter that keeps track of authenticated data
G_CTR_D_SIZE : integer := 64 --! Maximum size for the counter that keeps track of data
);
port (
clk : in std_logic;
rst : in std_logic;
npub : in std_logic_vector(G_NPUB_SIZE -1 downto 0);
nsec : in std_logic_vector(G_NSEC_SIZE -1 downto 0);
key : in std_logic_vector(G_KEY_SIZE -1 downto 0);
rdkey : in std_logic_vector(G_RDKEY_SIZE -1 downto 0);
bdi : in std_logic_vector(G_DBLK_SIZE -1 downto 0);
exp_tag : in std_logic_vector(G_TAG_SIZE -1 downto 0);
len_a : in std_logic_vector(G_CTR_AD_SIZE -1 downto 0);
len_d : in std_logic_vector(G_CTR_D_SIZE -1 downto 0);
key_ready : in std_logic;
key_updated : out std_logic;
key_needs_update : in std_logic;
rdkey_ready : in std_logic;
rdkey_read : out std_logic;
npub_ready : in std_logic;
npub_read : out std_logic;
nsec_ready : in std_logic;
nsec_read : out std_logic;
bdi_ready : in std_logic;
bdi_proc : in std_logic;
bdi_ad : in std_logic;
bdi_nsec : in std_logic;
bdi_pad : in std_logic;
bdi_decrypt : in std_logic;
bdi_eot : in std_logic;
bdi_eoi : in std_logic;
bdi_read : out std_logic;
bdi_size : in std_logic_vector(G_BS_BYTES -1 downto 0);
bdi_valid_bytes : in std_logic_vector(G_DBLK_SIZE/8 -1 downto 0);
bdi_pad_loc : in std_logic_vector(G_DBLK_SIZE/8 -1 downto 0);
bdi_nodata : in std_logic;
exp_tag_ready : in std_logic;
bdo_ready : in std_logic;
bdo_write : out std_logic;
bdo : out std_logic_vector(G_DBLK_SIZE -1 downto 0);
bdo_size : out std_logic_vector(G_BS_BYTES+1 -1 downto 0);
bdo_nsec : out std_logic;
tag_ready : in std_logic;
tag_write : out std_logic;
tag : out std_logic_vector(G_TAG_SIZE -1 downto 0);
msg_auth_done : out std_logic;
msg_auth_valid : out std_logic
);
end entity CipherCore;
architecture structure of CipherCore is
-- Registers
signal keyreg,npubreg : std_logic_vector(127 downto 0);
-- Control signals AsconCore
signal AsconStart : std_logic;
signal AsconMode : std_logic_vector(3 downto 0);
signal AsconBusy : std_logic;
signal AsconSize : std_logic_vector(3 downto 0);
signal AsconInput : std_logic_vector(127 downto 0);
-- Internal Datapath signals
signal AsconOutput : std_logic_vector(127 downto 0);
begin
-- Morus_core entity
AsconCore : entity work.Ascon_StateUpdate port map(clk,rst,AsconStart,AsconMode,AsconSize,npubreg,keyreg,AsconInput,AsconBusy,AsconOutput);
----------------------------------------
------ DataPath for CipherCore ---------
----------------------------------------
datapath: process(AsconOutput,exp_tag,bdi,AsconInput) is
begin
-- Connect signals to the MorusCore
AsconInput <= bdi;
tag <= AsconOutput;
bdo <= AsconOutput;
if AsconOutput = exp_tag then
msg_auth_valid <= '1';
else
msg_auth_valid <= '0';
end if;
end process datapath;
----------------------------------------
------ ControlPath for CipherCore ------
----------------------------------------
fsm: process(clk, rst) is
type state_type is (IDLE,INIT_1,INIT_2,PROCESSING,RUN_CIPHER_1,RUN_CIPHER_2,RUN_CIPHER_3,TAG_1,TAG_2);
variable CurrState : state_type := IDLE;
variable firstblock : std_logic;
variable lastblock : std_logic_vector(1 downto 0);
variable afterRunning : std_logic_vector(2 downto 0);
begin
if(clk = '1' and clk'event) then
if rst = '1' then -- synchornous reset
key_updated <= '0';
CurrState := IDLE;
firstblock := '0';
keyreg <= (others => '0');
npubreg <= (others => '0');
AsconMode <= (others => '0'); -- the mode is a register
afterRunning := (others => '0');
else
-- registers above in reset are used
-- Standard values of the control signals are zero
AsconStart <= '0';
bdi_read <= '0';
msg_auth_done <= '0';
bdo_write <= '0';
bdo_size <= "10000";
tag_write <= '0';
npub_read <= '0';
AsconSize <= (others => '0');
FsmLogic: case CurrState is
when IDLE =>
-- if key_needs_update = '1' then -- Key needs updating
-- if key_ready = '1' then
-- key_updated <= '1';
-- keyreg <= key;
-- CurrState := IDLE;
-- else
-- CurrState := IDLE;
-- end if;
if key_needs_update = '1' and key_ready = '1' then -- Key needs updating
key_updated <= '1';
keyreg <= key;
CurrState := IDLE;
elsif bdi_proc = '1' and npub_ready = '1' then -- start of processing
CurrState := INIT_1;
npubreg <= npub;
npub_read <= '1';
AsconMode <= "0010"; -- Mode: initialization
AsconStart <= '1';
else
CurrState := IDLE;
end if;
when INIT_1 =>
if AsconBusy = '1' then
CurrState := INIT_2; -- to INIT_2
else
AsconStart <= '1';
CurrState := INIT_1; -- to INIT_1
end if;
when INIT_2 =>
if AsconBusy = '0' then
CurrState := PROCESSING; -- to PROCESSING
firstblock := '1';
lastblock := "00";
else
CurrState := INIT_2; -- to INIT_2
end if;
-- EVEN SIMPLIFY THIS AFTER YOU SEE IF WORKS
when PROCESSING =>
if lastblock(1) = '1' then -- Generate the Tag
AsconMode <= "0001";
AsconStart <= '1';
CurrState := TAG_1;
elsif bdi_ready = '1' then
if firstblock = '1' and bdi_ad = '0' then -- No associative data (and return in function)
-- SEP_CONST
AsconMode <= "0011";
AsconStart <= '1';
CurrState := PROCESSING;
elsif bdi_ad = '1' then
if bdi_eot = '0' then
-- AD_PROCESS
AsconMode <= "0000";
AsconStart <= '1';
afterRunning := "000";
CurrState := RUN_CIPHER_1;
elsif bdi_eoi = '0' then
if bdi_size = "0000" then
-- AD_PROCESS + case2 + SEP_CONST
AsconMode <= "0000";
AsconStart <= '1';
afterRunning := "001";
CurrState := RUN_CIPHER_1;
else
-- AD_PROCESS + SEP_CONST
AsconMode <= "0000";
AsconStart <= '1';
afterRunning := "010";
CurrState := RUN_CIPHER_1;
end if;
else
if bdi_size = "0000" then
-- AD_PROCESS + case2 + SEP_CONST + case1
AsconMode <= "0000";
AsconStart <= '1';
afterRunning := "101";
CurrState := RUN_CIPHER_1;
else
-- AD_PROCESS + SEP_CONST + case1
AsconMode <= "0000";
AsconStart <= '1';
afterRunning := "110";
CurrState := RUN_CIPHER_1;
end if;
end if;
else
if bdi_decrypt = '0' then
if bdi_eot = '0' then
-- ENCRYPT
AsconMode <= "0110";
AsconStart <= '1';
afterRunning := "011";
CurrState := RUN_CIPHER_1;
elsif bdi_size = "0000" then
-- ENCRYPT + case1
AsconMode <= "0110";
AsconStart <= '1';
afterRunning := "100";
CurrState := RUN_CIPHER_1;
else
-- LAST_BLOCK_ENCRYPT
bdi_read <= '1';
AsconMode <= "0111";
AsconStart <= '1';
afterRunning := "011";
CurrState := RUN_CIPHER_2;
end if;
else
if bdi_eot = '0' then
-- DECRYPT
AsconMode <= "0100";
AsconStart <= '1';
afterRunning := "011";
CurrState := RUN_CIPHER_1;
elsif bdi_size = "0000" then
-- DECRYPT + case1
AsconMode <= "0100";
AsconStart <= '1';
afterRunning := "100";
CurrState := RUN_CIPHER_1;
else
-- LAST_BLOCK_DECRYPT
bdi_read <= '1';
AsconMode <= "0101";
AsconStart <= '1';
AsconSize <= bdi_size;
afterRunning := "011";
CurrState := RUN_CIPHER_2;
end if;
end if;
end if;
-- check if tag after (eoi, with special case when no associative data:
-- This is needed, because if no associative data, it will do it's thing and then still the message block is
-- left to be processed
if firstblock = '1' and bdi_ad = '0' then -- lastblock will be set next return in the function
lastblock := "00";
elsif bdi_eoi = '1' and bdi_decrypt = '0' then -- the one after is tag encryption
lastblock := "10";
elsif bdi_eoi = '1' then -- the one after is tag decryption
lastblock := "11";
end if;
-- not firstblock anymore :
firstblock := '0';
end if;
when RUN_CIPHER_1 =>
if AsconBusy = '1' then
CurrState := RUN_CIPHER_2;
bdi_read <= '1';
else
AsconStart <= '1';
CurrState := RUN_CIPHER_1;
end if;
when RUN_CIPHER_3 =>
if AsconBusy = '1' then
CurrState := RUN_CIPHER_2;
else
AsconStart <= '1';
CurrState := RUN_CIPHER_3;
end if;
when RUN_CIPHER_2 =>
if AsconBusy = '0' then
-- logic here:
-- a simple variable is used for the cases where after the cipher something special has to be done:
-- activating authregister after associative data = 1
-- resetting of blocknumber after last associative data = 2 (so also do 1's job)
-- giving of output after encryption/decryption = 3 for encryption, 4 for decryption
-- activating checksum after decription of message = 4
-- special giving of output after padded encryption/decryption = 5 and 6 (determines output_sel), also wait with bdi_read
AfterRunLogic: case afterRunning is
when "000" => -- return to IDLE
CurrState := PROCESSING;
when "001" => -- case2 and sep_cont after
AsconMode <= "1001";
AsconStart <= '1';
CurrState := RUN_CIPHER_3;
afterRunning := "010";
when "010" => -- SEPCONSTANT and return to IDLE
AsconMode <= "0011";
AsconStart <= '1';
CurrState := PROCESSING;
when "011" => -- GIVE OUTPUT and return to IDLE
if bdo_ready = '1' then
bdo_write <= '1';
CurrState := PROCESSING;
else
CurrState := RUN_CIPHER_2;
end if;
when "100" => -- GIVE OUTPUT & case1 and return to IDLE
if bdo_ready = '1' then
bdo_write <= '1';
CurrState := PROCESSING;
AsconMode <= "1000";
AsconStart <= '1';
else
CurrState := RUN_CIPHER_2;
end if;
when "101" => -- case2 and case1 and sep_cont after
AsconMode <= "1001";
AsconStart <= '1';
CurrState := RUN_CIPHER_3;
afterRunning := "110";
when "110" => -- case1 and sep_cont after
AsconMode <= "1000";
AsconStart <= '1';
CurrState := RUN_CIPHER_2;
afterRunning := "010";
when others =>
end case AfterRunLogic;
else
CurrState := RUN_CIPHER_2;
end if;
when TAG_1 =>
if AsconBusy = '1' then
CurrState := TAG_2;
else
AsconStart <= '1';
CurrState := TAG_1;
end if;
when TAG_2 =>
if AsconBusy = '0' and lastblock(0) = '0' then -- Generate Tag
if tag_ready = '1' then
tag_write <= '1';
key_updated <= '0';
CurrState := IDLE;
else
CurrState := TAG_2;
end if;
elsif AsconBusy = '0' then -- Compare Tag
if exp_tag_ready = '1' then
msg_auth_done <= '1';
key_updated <= '0';
CurrState := IDLE;
else
CurrState := TAG_2;
end if;
else
CurrState := TAG_2;
end if;
when others =>
end case FsmLogic;
end if;
end if;
end process fsm;
end architecture structure;
| gpl-3.0 | 00ef6806e307ba574ea2ca395a82999b | 0.518897 | 3.404877 | false | false | false | false |
mgiacomini/mips-monocycle | REG.vhd | 2 | 2,460 | -- +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-- Complete implementation of Patterson and Hennessy single cycle MIPS processor
-- Copyright (C) 2015 Darci Luiz Tomasi Junior
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, version 3.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
-- Engineer: Darci Luiz Tomasi Junior
-- E-mail: [email protected]
-- Date : 29/06/2015 - 20:31
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;
ENTITY REG IS
PORT(
CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
RegWrite : IN STD_LOGIC;
IN_A : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
IN_B : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
IN_C : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
IN_D : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
OUT_A : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
OUT_B : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END REG;
ARCHITECTURE ARC_REG OF REG IS
TYPE STD_REG IS ARRAY(0 TO 31) OF STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL REG_1: STD_REG;
SIGNAL REG_2: STD_REG;
BEGIN
--REALIZA A LEITURA NO ENDEREO SELECIONADO
OUT_A <= REG_1(TO_INTEGER(UNSIGNED(IN_A)));
OUT_B <= REG_2(TO_INTEGER(UNSIGNED(IN_B)));
--PROCESSO DE LEITURA
PROCESS(CLK, RESET)
BEGIN
IF RESET = '1' THEN
REG_1(0) <= (OTHERS => '0');
REG_2(0) <= (OTHERS => '0');
--t0
REG_1(8) <= (0 => '1', OTHERS => '0'); --NO TEMOS A FUNO ADDI, ENTO
REG_2(8) <= (0 => '1', OTHERS => '0'); --TEM QUE SER NA FORA BRUTA
--t1
REG_1(9) <= (0 => '1', 1 => '1', OTHERS => '0');
REG_2(9) <= (0 => '1', 1 => '1', OTHERS => '0');
--s1
REG_1(17) <= X"FFFF0000";
REG_2(17) <= X"FFFF0000";
ELSIF CLK'EVENT AND CLK = '0' AND RegWrite = '1' THEN
REG_1(TO_INTEGER(UNSIGNED(IN_C))) <= IN_D;
REG_2(TO_INTEGER(UNSIGNED(IN_C))) <= IN_D;
END IF;
END PROCESS;
END ARC_REG;
| gpl-3.0 | f39ebb41711275daccd4de2881b1a25b | 0.576829 | 2.925089 | false | false | false | false |
impedimentToProgress/UCI-BlueChip | AttackFiles/Attacks/privEsc/lib/gaisler/misc/wild.vhd | 2 | 5,863 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
--============================================================================--
-- Design unit : WildCard Package (package declaration)
--
-- File name : wild.vhd
--
-- Purpose : WildCard Package
--
-- Library : gaisler
--
-- Authors : Mr Sandi Alexander Habinc
-- Gaisler Research
--
-- Contact : mailto:[email protected]
-- http://www.gaisler.com
--
-- Disclaimer : All information is provided "as is", there is no warranty that
-- the information is correct or suitable for any purpose,
-- neither implicit nor explicit.
--------------------------------------------------------------------------------
-- Version Author Date Changes
--
-- 0.1 SH 1 Jan 2008 New version
--------------------------------------------------------------------------------
library IEEE;
use IEEE.Std_Logic_1164.all;
library IEEE;
use IEEE.Std_Logic_1164.all;
library grlib;
use grlib.amba.all;
package Wild is
-----------------------------------------------------------------------------
-- Name Key:
-- =========
-- _AS : Address Strobe
-- _DS : Data Strobe
-- _WR : Write Select
-- _CS : Chip Select
-- _OE : Output Enable
-- _n : Active low signals (must be last part of name)
--
-- Name Width Dir* Description
-- ==================== ===== ==== =====================================
-- Addr_Data 32 I Shared address/data bus input
-- AS_n 1 I Address strobe
-- DS_n 1 I Data strobe
-- WR_n 1 I Write select
-- CS_n 1 I PE chip select
-- Reg_n 1 I Register mode select
-- Ack_n 1 O Acknowledge strobe
-- Addr_Data 32 O Shared address/data bus output
-- Addr_Data_OE_n 1 O Address/data bus output enable
-- Int_Req_n 1 O Interrupt request
-- DMA_0_Data_OK_n 1 O DMA channel 0 data OK flag
-- DMA_0_Burst_OK_n 1 O DMA channel 0 burst OK flag
-- DMA_1_Data_OK_n 1 O DMA channel 1 data OK flag
-- DMA_1_Burst_OK_n 1 O DMA channel 1 burst OK flag
-- Reg_Data_OK_n 1 O Register space data OK flag
-- Reg_Burst_OK_n 1 O Register space burst OK flag
-- Force_K_Clk_n 1 O Forces K_Clk to run when active
-----------------------------------------------------------------------------
type LAD_In_Type is record
Addr_Data: Std_Logic_Vector(31 downto 0); -- Shared address/data bus
AS_n: Std_Logic; -- Address strobe
DS_n: Std_Logic; -- Data strobe
WR_n: Std_Logic; -- Write select
CS_n: Std_Logic; -- Chip select
Reg_n: Std_Logic; -- Register select
end record;
type LAD_Out_Type is record
Addr_Data: Std_Logic_Vector(31 downto 0); -- Shared address/data bus output
Addr_Data_OE_n: Std_Logic_Vector(31 downto 0); -- Address/data bus output enable
Ack_n: Std_Logic; -- Acknowledge strobe
Int_Req_n: Std_Logic; -- Interrupt request
DMA_0_Data_OK_n: Std_Logic; -- DMA chan 0 data OK flag
DMA_0_Burst_OK: Std_Logic; -- DMA chan 0 burst OK flag
DMA_1_Data_OK_n: Std_Logic; -- DMA chan 1 data OK flag
DMA_1_Burst_OK: Std_Logic; -- DMA chan 1 burst OK flag
Reg_Data_OK_n: Std_Logic; -- Reg space data OK flag
Reg_Burst_OK: Std_Logic; -- Reg space burst OK flag
Force_K_Clk_n: Std_Logic; -- K_Clk forced-run select
Reserved: Std_Logic; -- Reserved for future use
end record;
component Wild2AHB is
generic (
hindex: in Integer := 0;
burst: in Integer := 0;
syncrst: in Integer := 0);
port (
rstkn: in Std_ULogic;
clkk: in Std_ULogic;
rstfn: in Std_ULogic;
clkf: in Std_ULogic;
ahbmi: in AHB_Mst_In_Type;
ahbmo: out AHB_Mst_Out_Type;
ladi: in LAD_In_Type;
lado: out LAD_Out_Type);
end component;
end package Wild; --==========================================================--
| mit | fe1d892c7c2d16c27e275a42cc06b62f | 0.450623 | 4.245474 | false | false | false | false |
michaelfivez/ascon_hardware_implementation | ascon12864_unrolled2/Kernel/Ascon_block_control.vhd | 1 | 7,045 | -------------------------------------------------------------------------------
--! @project Unrolled (2) hardware implementation of Asconv1286
--! @author Michael Fivez
--! @license This project is released under the GNU Public License.
--! The license and distribution terms for this file may be
--! found in the file LICENSE in this distribution or at
--! http://www.gnu.org/licenses/gpl-3.0.txt
--! @note This is an hardware implementation made for my graduation thesis
--! at the KULeuven, in the COSIC department (year 2015-2016)
--! The thesis is titled 'Energy efficient hardware implementations of CAESAR submissions',
--! and can be found on the COSIC website (www.esat.kuleuven.be/cosic/publications)
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity Ascon_StateUpdate_control is
port(
Clk : in std_logic; -- Clock
Reset : in std_logic; -- Reset (synchronous)
-- Control signals
RoundNr : out std_logic_vector(2 downto 0); -- biggest round is 12
sel1,sel2,sel3,sel4 : out std_logic_vector(1 downto 0);
sel0 : out std_logic_vector(2 downto 0);
selout : out std_logic;
Reg0En,Reg1En,Reg2En,Reg3En,Reg4En,RegOutEn : out std_logic;
ActivateGen : out std_logic;
GenSize : out std_logic_vector(2 downto 0);
-- External control signals
Start : in std_logic;
Mode : in std_logic_vector(3 downto 0);
Size : in std_logic_vector(2 downto 0); -- only matters for last block decryption
Busy : out std_logic
);
end entity Ascon_StateUpdate_control;
architecture structural of Ascon_StateUpdate_control is
begin
-----------------------------------------
------ The Finite state machine --------
-----------------------------------------
-- Modes: initialization, associative data, encryption, decryption, tag generation, final encryption, final decryption, seperation constant
-- 0010 0000 0110 0100 0001 0111 0101, 0011
-- case1 1000, case2 1001
fsm: process(Clk, Reset) is
type state_type is (IDLE,LOADNEW,CRYPT,TAG);
variable CurrState : state_type := IDLE;
variable RoundNrVar : std_logic_vector(2 downto 0);
begin
if Clk'event and Clk = '1' then
-- default values
sel0 <= "000";
sel1 <= "00";
sel2 <= "00";
sel3 <= "00";
sel4 <= "00";
selout <= '0';
Reg0En <= '0';
Reg1En <= '0';
Reg2En <= '0';
Reg3En <= '0';
Reg4En <= '0';
RegOutEn <= '0';
ActivateGen <= '0';
GenSize <= "000";
Busy <= '0';
if Reset = '1' then -- synchronous reset active high
-- registers used by fsm:
RoundNrVar := "000";
CurrState := IDLE;
else
FSMlogic : case CurrState is
when IDLE =>
if Start = '1' then
Busy <= '1';
if Mode = "0000" then -- AD mode
RoundNrVar := "111"; -- so starts at 0 next cycle
-- set Sel and Enables signal (Xor with DataIn)
sel0 <= "010";
Reg0En <= '1';
CurrState := CRYPT;
elsif Mode = "0100" then -- Decryption mode
RoundNrVar := "111"; -- so starts at 0 next cycle
-- set Sel and Enables signal (Generate output and xor state)
ActivateGen <= '1';
sel0 <= "010";
Reg0En <= '1';
RegOutEn <= '1';
CurrState := CRYPT;
elsif Mode = "0110" then -- Encryption
RoundNrVar := "111"; -- so starts at 0 next cycle
-- set Sel and Enables signal (Generate output and xor state)
sel0 <= "010";
Reg0En <= '1';
RegOutEn <= '1';
CurrState := CRYPT;
elsif Mode = "0001" then -- Tag mode
RoundNrVar := "111"; -- so starts at 0 next cycle
-- set Sel and Enables signal (XOR middle with key)
sel1 <= "10";
sel2 <= "11";
Reg1En <= '1';
Reg2En <= '1';
CurrState := TAG;
elsif Mode = "0111" then -- Last block encryption
-- set Sel and Enables signal (Generate output and xor state)
sel0 <= "010";
Reg0En <= '1';
RegOutEn <= '1';
CurrState := IDLE;
elsif Mode = "0101" then -- Last block decryption
-- set Sel and Enables signal (Generate output and xor state)
ActivateGen <= '1';
GenSize <= Size;
sel0 <= "010";
Reg0En <= '1';
RegOutEn <= '1';
CurrState := IDLE;
elsif Mode = "0011" then -- Seperation constant
sel4 <= "11";
Reg4En <= '1';
CurrState := IDLE;
elsif Mode = "0010" then -- Initialization mode
RoundNrVar := "111"; -- so starts at 0 next cycle
-- set Sel and Enables signal (Load in key and IV)
sel0 <= "001";
sel1 <= "01";
sel2 <= "01";
sel3 <= "01";
sel4 <= "01";
Reg0En <= '1';
Reg1En <= '1';
Reg2En <= '1';
Reg3En <= '1';
Reg4En <= '1';
CurrState := LOADNEW;
elsif Mode = "1000" then -- case1
sel0 <= "100";
Reg0En <= '1';
CurrState := IDLE;
else -- case2
sel0 <= "100";
Reg0En <= '1';
RoundNrVar := "111"; -- so starts at 0 next cycle
CurrState := CRYPT;
end if;
else
Busy <= '0';
CurrState := IDLE;
end if;
when LOADNEW =>
if RoundNrVar = "101" then -- RoundNrVar = 11
-- set Sel and Enables signal (Xor at the end)
sel3 <= "10";
sel4 <= "10";
Reg3En <= '1';
Reg4En <= '1';
CurrState := IDLE;
Busy <= '0';
else
RoundNrVar := std_logic_vector(unsigned(RoundNrVar) + 1);
-- set Sel and Enables signal (execute a round)
Reg0En <= '1';
Reg1En <= '1';
Reg2En <= '1';
Reg3En <= '1';
Reg4En <= '1';
CurrState := LOADNEW;
Busy <= '1';
end if;
when CRYPT =>
if RoundNrVar = "001" then -- RoundNrVar = 4
RoundNrVar := std_logic_vector(unsigned(RoundNrVar) + 1);
-- set Sel and Enables signal (execute a round)
Reg0En <= '1';
Reg1En <= '1';
Reg2En <= '1';
Reg3En <= '1';
Reg4En <= '1';
CurrState := IDLE;
Busy <= '0';
else
RoundNrVar := std_logic_vector(unsigned(RoundNrVar) + 1);
-- set Sel and Enables signal (execute a round)
Reg0En <= '1';
Reg1En <= '1';
Reg2En <= '1';
Reg3En <= '1';
Reg4En <= '1';
CurrState := CRYPT;
Busy <= '1';
end if;
when TAG =>
if RoundNrVar = "101" then -- RoundNrVar = 11
-- set Sel and Enables signal (connect tag to output)
selout <= '1';
RegOutEn <= '1';
CurrState := IDLE;
Busy <= '0';
else
RoundNrVar := std_logic_vector(unsigned(RoundNrVar) + 1);
-- set Sel and Enables signal (execute a round)
Reg0En <= '1';
Reg1En <= '1';
Reg2En <= '1';
Reg3En <= '1';
Reg4En <= '1';
CurrState := TAG;
Busy <= '1';
end if;
end case FSMlogic;
RoundNr <= RoundNrVar;
end if;
end if;
end process fsm;
end architecture structural;
| gpl-3.0 | ad6f507b3765f04957678449a7e8ef54 | 0.539957 | 3.218365 | false | false | false | false |
cafe-alpha/wascafe | v10/fpga_firmware/wasca/synthesis/wasca_rst_controller_001.vhd | 1 | 9,042 | -- wasca_rst_controller_001.vhd
-- Generated using ACDS version 15.0 145
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity wasca_rst_controller_001 is
generic (
NUM_RESET_INPUTS : integer := 1;
OUTPUT_RESET_SYNC_EDGES : string := "deassert";
SYNC_DEPTH : integer := 2;
RESET_REQUEST_PRESENT : integer := 0;
RESET_REQ_WAIT_TIME : integer := 1;
MIN_RST_ASSERTION_TIME : integer := 3;
RESET_REQ_EARLY_DSRT_TIME : integer := 1;
USE_RESET_REQUEST_IN0 : integer := 0;
USE_RESET_REQUEST_IN1 : integer := 0;
USE_RESET_REQUEST_IN2 : integer := 0;
USE_RESET_REQUEST_IN3 : integer := 0;
USE_RESET_REQUEST_IN4 : integer := 0;
USE_RESET_REQUEST_IN5 : integer := 0;
USE_RESET_REQUEST_IN6 : integer := 0;
USE_RESET_REQUEST_IN7 : integer := 0;
USE_RESET_REQUEST_IN8 : integer := 0;
USE_RESET_REQUEST_IN9 : integer := 0;
USE_RESET_REQUEST_IN10 : integer := 0;
USE_RESET_REQUEST_IN11 : integer := 0;
USE_RESET_REQUEST_IN12 : integer := 0;
USE_RESET_REQUEST_IN13 : integer := 0;
USE_RESET_REQUEST_IN14 : integer := 0;
USE_RESET_REQUEST_IN15 : integer := 0;
ADAPT_RESET_REQUEST : integer := 0
);
port (
reset_in0 : in std_logic := '0'; -- reset_in0.reset
clk : in std_logic := '0'; -- clk.clk
reset_out : out std_logic; -- reset_out.reset
reset_in1 : in std_logic := '0';
reset_in10 : in std_logic := '0';
reset_in11 : in std_logic := '0';
reset_in12 : in std_logic := '0';
reset_in13 : in std_logic := '0';
reset_in14 : in std_logic := '0';
reset_in15 : in std_logic := '0';
reset_in2 : in std_logic := '0';
reset_in3 : in std_logic := '0';
reset_in4 : in std_logic := '0';
reset_in5 : in std_logic := '0';
reset_in6 : in std_logic := '0';
reset_in7 : in std_logic := '0';
reset_in8 : in std_logic := '0';
reset_in9 : in std_logic := '0';
reset_req : out std_logic;
reset_req_in0 : in std_logic := '0';
reset_req_in1 : in std_logic := '0';
reset_req_in10 : in std_logic := '0';
reset_req_in11 : in std_logic := '0';
reset_req_in12 : in std_logic := '0';
reset_req_in13 : in std_logic := '0';
reset_req_in14 : in std_logic := '0';
reset_req_in15 : in std_logic := '0';
reset_req_in2 : in std_logic := '0';
reset_req_in3 : in std_logic := '0';
reset_req_in4 : in std_logic := '0';
reset_req_in5 : in std_logic := '0';
reset_req_in6 : in std_logic := '0';
reset_req_in7 : in std_logic := '0';
reset_req_in8 : in std_logic := '0';
reset_req_in9 : in std_logic := '0'
);
end entity wasca_rst_controller_001;
architecture rtl of wasca_rst_controller_001 is
component altera_reset_controller is
generic (
NUM_RESET_INPUTS : integer := 6;
OUTPUT_RESET_SYNC_EDGES : string := "deassert";
SYNC_DEPTH : integer := 2;
RESET_REQUEST_PRESENT : integer := 0;
RESET_REQ_WAIT_TIME : integer := 1;
MIN_RST_ASSERTION_TIME : integer := 3;
RESET_REQ_EARLY_DSRT_TIME : integer := 1;
USE_RESET_REQUEST_IN0 : integer := 0;
USE_RESET_REQUEST_IN1 : integer := 0;
USE_RESET_REQUEST_IN2 : integer := 0;
USE_RESET_REQUEST_IN3 : integer := 0;
USE_RESET_REQUEST_IN4 : integer := 0;
USE_RESET_REQUEST_IN5 : integer := 0;
USE_RESET_REQUEST_IN6 : integer := 0;
USE_RESET_REQUEST_IN7 : integer := 0;
USE_RESET_REQUEST_IN8 : integer := 0;
USE_RESET_REQUEST_IN9 : integer := 0;
USE_RESET_REQUEST_IN10 : integer := 0;
USE_RESET_REQUEST_IN11 : integer := 0;
USE_RESET_REQUEST_IN12 : integer := 0;
USE_RESET_REQUEST_IN13 : integer := 0;
USE_RESET_REQUEST_IN14 : integer := 0;
USE_RESET_REQUEST_IN15 : integer := 0;
ADAPT_RESET_REQUEST : integer := 0
);
port (
reset_in0 : in std_logic := 'X'; -- reset
clk : in std_logic := 'X'; -- clk
reset_out : out std_logic; -- reset
reset_req : out std_logic; -- reset_req
reset_req_in0 : in std_logic := 'X'; -- reset_req
reset_in1 : in std_logic := 'X'; -- reset
reset_req_in1 : in std_logic := 'X'; -- reset_req
reset_in2 : in std_logic := 'X'; -- reset
reset_req_in2 : in std_logic := 'X'; -- reset_req
reset_in3 : in std_logic := 'X'; -- reset
reset_req_in3 : in std_logic := 'X'; -- reset_req
reset_in4 : in std_logic := 'X'; -- reset
reset_req_in4 : in std_logic := 'X'; -- reset_req
reset_in5 : in std_logic := 'X'; -- reset
reset_req_in5 : in std_logic := 'X'; -- reset_req
reset_in6 : in std_logic := 'X'; -- reset
reset_req_in6 : in std_logic := 'X'; -- reset_req
reset_in7 : in std_logic := 'X'; -- reset
reset_req_in7 : in std_logic := 'X'; -- reset_req
reset_in8 : in std_logic := 'X'; -- reset
reset_req_in8 : in std_logic := 'X'; -- reset_req
reset_in9 : in std_logic := 'X'; -- reset
reset_req_in9 : in std_logic := 'X'; -- reset_req
reset_in10 : in std_logic := 'X'; -- reset
reset_req_in10 : in std_logic := 'X'; -- reset_req
reset_in11 : in std_logic := 'X'; -- reset
reset_req_in11 : in std_logic := 'X'; -- reset_req
reset_in12 : in std_logic := 'X'; -- reset
reset_req_in12 : in std_logic := 'X'; -- reset_req
reset_in13 : in std_logic := 'X'; -- reset
reset_req_in13 : in std_logic := 'X'; -- reset_req
reset_in14 : in std_logic := 'X'; -- reset
reset_req_in14 : in std_logic := 'X'; -- reset_req
reset_in15 : in std_logic := 'X'; -- reset
reset_req_in15 : in std_logic := 'X' -- reset_req
);
end component altera_reset_controller;
begin
rst_controller_001 : component altera_reset_controller
generic map (
NUM_RESET_INPUTS => NUM_RESET_INPUTS,
OUTPUT_RESET_SYNC_EDGES => OUTPUT_RESET_SYNC_EDGES,
SYNC_DEPTH => SYNC_DEPTH,
RESET_REQUEST_PRESENT => RESET_REQUEST_PRESENT,
RESET_REQ_WAIT_TIME => RESET_REQ_WAIT_TIME,
MIN_RST_ASSERTION_TIME => MIN_RST_ASSERTION_TIME,
RESET_REQ_EARLY_DSRT_TIME => RESET_REQ_EARLY_DSRT_TIME,
USE_RESET_REQUEST_IN0 => USE_RESET_REQUEST_IN0,
USE_RESET_REQUEST_IN1 => USE_RESET_REQUEST_IN1,
USE_RESET_REQUEST_IN2 => USE_RESET_REQUEST_IN2,
USE_RESET_REQUEST_IN3 => USE_RESET_REQUEST_IN3,
USE_RESET_REQUEST_IN4 => USE_RESET_REQUEST_IN4,
USE_RESET_REQUEST_IN5 => USE_RESET_REQUEST_IN5,
USE_RESET_REQUEST_IN6 => USE_RESET_REQUEST_IN6,
USE_RESET_REQUEST_IN7 => USE_RESET_REQUEST_IN7,
USE_RESET_REQUEST_IN8 => USE_RESET_REQUEST_IN8,
USE_RESET_REQUEST_IN9 => USE_RESET_REQUEST_IN9,
USE_RESET_REQUEST_IN10 => USE_RESET_REQUEST_IN10,
USE_RESET_REQUEST_IN11 => USE_RESET_REQUEST_IN11,
USE_RESET_REQUEST_IN12 => USE_RESET_REQUEST_IN12,
USE_RESET_REQUEST_IN13 => USE_RESET_REQUEST_IN13,
USE_RESET_REQUEST_IN14 => USE_RESET_REQUEST_IN14,
USE_RESET_REQUEST_IN15 => USE_RESET_REQUEST_IN15,
ADAPT_RESET_REQUEST => ADAPT_RESET_REQUEST
)
port map (
reset_in0 => reset_in0, -- reset_in0.reset
clk => clk, -- clk.clk
reset_out => reset_out, -- reset_out.reset
reset_req => open, -- (terminated)
reset_req_in0 => '0', -- (terminated)
reset_in1 => '0', -- (terminated)
reset_req_in1 => '0', -- (terminated)
reset_in2 => '0', -- (terminated)
reset_req_in2 => '0', -- (terminated)
reset_in3 => '0', -- (terminated)
reset_req_in3 => '0', -- (terminated)
reset_in4 => '0', -- (terminated)
reset_req_in4 => '0', -- (terminated)
reset_in5 => '0', -- (terminated)
reset_req_in5 => '0', -- (terminated)
reset_in6 => '0', -- (terminated)
reset_req_in6 => '0', -- (terminated)
reset_in7 => '0', -- (terminated)
reset_req_in7 => '0', -- (terminated)
reset_in8 => '0', -- (terminated)
reset_req_in8 => '0', -- (terminated)
reset_in9 => '0', -- (terminated)
reset_req_in9 => '0', -- (terminated)
reset_in10 => '0', -- (terminated)
reset_req_in10 => '0', -- (terminated)
reset_in11 => '0', -- (terminated)
reset_req_in11 => '0', -- (terminated)
reset_in12 => '0', -- (terminated)
reset_req_in12 => '0', -- (terminated)
reset_in13 => '0', -- (terminated)
reset_req_in13 => '0', -- (terminated)
reset_in14 => '0', -- (terminated)
reset_req_in14 => '0', -- (terminated)
reset_in15 => '0', -- (terminated)
reset_req_in15 => '0' -- (terminated)
);
end architecture rtl; -- of wasca_rst_controller_001
| gpl-2.0 | 6018fe9fde5f4138f8e7f09c30ea9ebf | 0.547666 | 2.725957 | false | false | false | false |
pmh92/Proyecto-OFDM | src/OFDM_ESTyEQ.vhd | 1 | 3,808 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 10:33:05 07/07/2015
-- Design Name:
-- Module Name: OFDM_ESTyEQ - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
ENTITY OFDM_ESTyEQ IS PORT (
clk : in STD_LOGIC;
rst : in STD_LOGIC;
start : in STD_LOGIC;
end_all : out STD_LOGIC);
end OFDM_ESTyEQ;
architecture Behavioral of OFDM_ESTyEQ is
COMPONENT DPRAM_10 IS PORT (
clka : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(10 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(19 DOWNTO 0);
clkb : IN STD_LOGIC;
addrb : IN STD_LOGIC_VECTOR(10 DOWNTO 0);
doutb : OUT STD_LOGIC_VECTOR(19 DOWNTO 0));
END COMPONENT;
COMPONENT DPRAM_12 PORT (
clka : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(10 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
clkb : IN STD_LOGIC;
addrb : IN STD_LOGIC_VECTOR(10 DOWNTO 0);
doutb : OUT STD_LOGIC_VECTOR(23 DOWNTO 0));
END COMPONENT;
COMPONENT SPRAM_12
PORT (
clka : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(10 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(23 DOWNTO 0)
);
END COMPONENT;
COMPONENT ESTIMADOR PORT(
clk : IN STD_LOGIC;
rst : IN STD_LOGIC;
start : IN STD_LOGIC;
fin : OUT STD_LOGIC;
addr_y : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
addr_h : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
y_data : IN STD_LOGIC_VECTOR(19 DOWNTO 0);
h_data : OUT STD_LOGIC_VECTOR(23 DOWNTO 0);
write_h : OUT STD_LOGIC_VECTOR(0 DOWNTO 0));
END COMPONENT;
COMPONENT ECUALIZADOR PORT(
clk : in STD_LOGIC;
rst : in STD_LOGIC;
start : in STD_LOGIC;
fin : out STD_LOGIC;
y_data : in STD_LOGIC_VECTOR (19 downto 0);
h_data : in STD_LOGIC_VECTOR (23 downto 0);
y_est_data : out STD_LOGIC_VECTOR (23 downto 0);
y_addr : out STD_LOGIC_VECTOR (10 downto 0);
h_addr : out STD_LOGIC_VECTOR (10 downto 0);
y_est_addr : out STD_LOGIC_VECTOR (10 downto 0);
write_y_est : out STD_LOGIC_VECTOR (0 downto 0));
end COMPONENT;
SIGNAL fin : STD_LOGIC;
SIGNAL addr_y_a,addr_y_b,addr_h_a,addr_h_b,addr_y_est : STD_LOGIC_VECTOR(10 DOWNTO 0);
SIGNAL h_in,h_out,y_est_data : STD_LOGIC_VECTOR(23 DOWNTO 0);
SIGNAL y_data_a,y_data_b : STD_LOGIC_VECTOR(19 DOWNTO 0);
SIGNAL write_h,write_y_est : STD_LOGIC_VECTOR(0 DOWNTO 0);
SIGNAL y_est_out :STD_LOGIC_VECTOR(23 DOWNTO 0);
BEGIN
est: ESTIMADOR
port map(
clk => clk,
rst => rst,
start => start,
fin => fin,
addr_y => addr_y_a,
addr_h => addr_h_a,
y_data => y_data_a,
h_data => h_in,
write_h => write_h
);
eq: ECUALIZADOR
PORT MAP(
clk => clk,
rst => rst,
start => fin,
fin => end_all,
y_data => y_data_b,
h_data => h_out,
y_est_data => y_est_data,
y_addr => addr_y_b,
h_addr => addr_h_b,
y_est_addr => addr_y_est,
write_y_est => write_y_est
);
y_mem : DPRAM_10
PORT MAP(
clka => clk,
wea => "0",
addra => addr_y_a,
dina => y_data_a,
clkb=> clk,
addrb => addr_y_b,
doutb => y_data_b
);
h_mem : DPRAM_12
PORT MAP (
clka => clk,
wea => write_h,
addra => addr_h_a,
dina => h_in,
clkb => clk,
addrb => addr_h_b,
doutb => h_out
);
y_est_mem : SPRAM_12
PORT MAP (
clka => clk,
wea => write_y_est,
addra => addr_y_est,
dina => y_est_data,
douta => y_est_out
);
end Behavioral;
| gpl-2.0 | 745269b8500db5c82105a57325205e3b | 0.583246 | 2.882665 | false | false | false | false |
hacklabmikkeli/rough-boy | circular_buffer.vhdl | 2 | 1,668 | --
-- Knobs Galore - a free phase distortion synthesizer
-- Copyright (C) 2015 Ilmo Euro
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.common.all;
entity circular_buffer is
port (EN: in std_logic
;CLK: in std_logic
;DATA_IN: in state_vector_t
;DATA_OUT: out state_vector_t
);
end entity;
architecture circular_buffer_impl of circular_buffer is
type data_buffer is array (0 to num_voices - 2) of state_vector_t;
signal data_out_buf: state_vector_t := empty_state_vector;
signal data: data_buffer := (others => empty_state_vector);
begin
process(CLK)
begin
if EN = '1' and rising_edge(CLK) then
data_out_buf <= data(0);
data(0 to num_voices - 3) <= data(1 to num_voices - 2);
data(num_voices - 2) <= DATA_IN;
end if;
end process;
DATA_OUT <= data_out_buf;
end architecture;
| gpl-3.0 | 53b745946fdd56156dd0381b93c844f8 | 0.63789 | 3.698448 | false | false | false | false |
emogenet/ghdl | libraries/std/textio_body.vhdl | 1 | 41,674 | -- Std.Textio package body. This file is part of GHDL.
-- Copyright (C) 2002, 2003, 2004, 2005 Tristan Gingold
--
-- GHDL is free software; you can redistribute it and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation; either version 2, or (at your option) any later
-- version.
--
-- GHDL is distributed in the hope that it will be useful, but WITHOUT ANY
-- WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with GCC; see the file COPYING3. If not see
-- <http://www.gnu.org/licenses/>.
package body textio is
attribute foreign : string; --V87
--START-V08
-- LRM08 16.4
-- The JUSTIFY operation formats a string value within a field that is at
-- least at long as required to contain the value. Parameter FIELD
-- specifies the desired field width. Since the actual field width will
-- always be at least large enough to hold the string value, the default
-- value 0 for the FIELD parameter has the effect of causing the string
-- value to be contained in a field of exactly the right widteh (i.e., no
-- additional leading or tailing spaces). Parameter JUSTIFIED specified
-- wether the string value is to be right- or left-justified within the
-- field; the default is right-justified. If the FIELD parameter describes
-- a field width larger than the number of characters in the string value,
-- space characters are used to fill the remaining characters in the field.
--
-- TG: Note that the bounds of the result are not specified!
function Justify (Value: String;
Justified : Side := Right;
Field: Width := 0 ) return String
is
constant len : Width := Value'Length;
begin
if Field <= Len then
return Value;
else
case Justified is
when Right =>
return (1 to Field - Len => ' ') & Value;
when Left =>
return Value & (1 to Field - Len => ' ');
end case;
end if;
end Justify;
--END-V08
-- output routines for standard types
-- TIME_NAMES associates time units with textual names.
-- Textual names are in lower cases, since according to LRM93 14.3:
-- when written, the identifier is expressed in lowercase characters.
-- The length of the names are 3 characters, the last one may be a space
-- for 2 characters long names.
type time_unit is
record
val : time;
name : string (1 to 3);
end record;
type time_names_type is array (1 to 8) of time_unit;
constant time_names : time_names_type :=
((fs, "fs "), (ps, "ps "), (ns, "ns "), (us, "us "),
(ms, "ms "), (sec, "sec"), (min, "min"), (hr, "hr "));
-- Non breaking space character. --!V87
constant nbsp : character := character'val (160); --!V87
function is_whitespace (c : character) return Boolean is
begin
case c is
when ' '
| NBSP --!V87
| HT =>
return True;
when others =>
return False;
end case;
end is_Whitespace;
procedure writeline (variable f: out text; l: inout line) is --V87
procedure writeline (file f: text; l: inout line) is --!V87
begin
if l = null then
-- LRM93 14.3
-- If parameter L contains a null access value at the start of the call,
-- the a null string is written to the file.
null;
else
-- LRM93 14.3
-- Procedure WRITELINE causes the current line designated by parameter L
-- to be written to the file and returns with the value of parameter L
-- designating a null string.
write (f, l.all);
deallocate (l);
l := new string'("");
end if;
write (f, (1 => LF));
end writeline;
--START-V08
procedure Tee (file f : Text; L : inout LINE) is
begin
-- LRM08 16.4 Package TEXTIO
-- The procedure TEE additionally causes the current line to be written
-- to the file OUTPUT.
if l = null then
null;
else
write (f, l.all);
write (Output, l.all);
deallocate (l);
l := new string'("");
end if;
write (f, (1 => LF));
write (output, (1 => LF));
end Tee;
--END-V08
procedure write
(l: inout line; value: in string;
justified: in side := right; field: in width := 0)
is
variable length: natural;
variable nl: line;
begin
-- l can be null.
if l = null then
length := 0;
else
length := l.all'length;
end if;
if value'length < field then
nl := new string (1 to length + field);
if length /= 0 then
nl (1 to length) := l.all;
end if;
if justified = right then
nl (length + 1 to length + field - value'length) := (others => ' ');
nl (nl.all'high - value'length + 1 to nl.all'high) := value;
else
nl (length + 1 to length + value'length) := value;
nl (length + value'length + 1 to nl.all'high) := (others => ' ');
end if;
else
nl := new string (1 to length + value'length);
if length /= 0 then
nl (1 to length) := l.all;
end if;
nl (length + 1 to nl.all'high) := value;
end if;
deallocate (l);
l := nl;
end write;
procedure write
(l: inout line; value: in integer;
justified: in side := right; field: in width := 0)
is
variable str: string (11 downto 1);
variable val: integer := value;
variable digit: natural;
variable index: natural := 0;
begin
-- Note: the absolute value of VAL cannot be directly taken, since
-- it may be greather that the maximum value of an INTEGER.
loop
-- LRM93 7.2.6
-- (A rem B) has the sign of A and an absolute value less then
-- the absoulte value of B.
digit := abs (val rem 10);
val := val / 10;
index := index + 1;
str (index) := character'val(48 + digit);
exit when val = 0;
end loop;
if value < 0 then
index := index + 1;
str(index) := '-';
end if;
write (l, str (index downto 1), justified, field);
end write;
procedure write
(l: inout line; value: in boolean;
justified: in side := right; field: in width := 0)
is
begin
if value then
write (l, string'("TRUE"), justified, field);
else
write (l, string'("FALSE"), justified, field);
end if;
end write;
procedure write
(l: inout line; value: in character;
justified: in side := right; field: in width := 0)
is
variable str: string (1 to 1);
begin
str (1) := value;
write (l, str, justified, field);
end write;
function bit_to_char (value : in bit) return character is
begin
case value is
when '0' =>
return '0';
when '1' =>
return '1';
end case;
end bit_to_char;
procedure write
(l: inout line; value: in bit;
justified: in side := right; field: in width := 0)
is
variable str : string (1 to 1);
begin
str (1) := bit_to_char (value);
write (l, str, justified, field);
end write;
procedure write
(l: inout line; value: in bit_vector;
justified: in side := right; field: in width := 0)
is
constant length : natural := value'length;
alias n_value : bit_vector (1 to value'length) is value;
variable str : string (1 to length);
begin
for i in str'range loop
str (i) := bit_to_char (n_value (i));
end loop;
write (l, str, justified, field);
end write;
procedure write
(l: inout line; value : in time;
justified: in side := right; field: in width := 0; unit : in TIME := ns)
is
-- Copy of VALUE on which we are working.
variable val : time := value;
-- Copy of UNIT on which we are working.
variable un : time := unit;
-- Digit extract from VAL/UN.
variable d : integer; -- natural range 0 to 9;
-- Index for unit name.
variable n : integer;
-- Result.
variable str : string (1 to 28);
-- Current character in RES.
variable pos : natural := 1;
-- Add a character to STR.
procedure add_char (c : character) is
begin
str (pos) := c;
pos := pos + 1;
end add_char;
begin
-- Note:
-- Care is taken to avoid overflow. Time may be 64 bits while integer
-- may be only 32 bits.
-- Handle sign.
-- Note: VAL cannot be negated since its range may be not symetric
-- around 0.
if val < 0 ns then
add_char ('-');
end if;
-- Search for the first digit.
-- Note: we must start from unit, since all units are not a power of 10.
-- Note: UN can be multiplied only after we know it is possible. This
-- is a to avoid overflow.
if un <= 0 fs then
assert false report "UNIT argument is not positive" severity error;
un := 1 ns;
end if;
while val / 10 >= un or val / 10 <= -un loop
un := un * 10;
end loop;
-- Extract digits one per one.
loop
d := val / un;
add_char (character'val (abs d + character'pos ('0')));
val := val - d * un;
exit when val = 0 ns and un <= unit;
if un = unit then
add_char ('.');
end if;
-- Stop as soon as precision will be lost.
-- This can happen only for hr and min.
-- FIXME: change the algorithm to display all the digits.
exit when (un / 10) * 10 /= un;
un := un / 10;
end loop;
add_char (' ');
-- Search the time unit name in the time table.
n := 0;
for i in time_names'range loop
if time_names (i).val = unit then
n := i;
exit;
end if;
end loop;
assert n /= 0 report "UNIT argument is not a unit name" severity error;
if n = 0 then
add_char ('?');
else
add_char (time_names (n).name (1));
add_char (time_names (n).name (2));
if time_names (n).name (3) /= ' ' then
add_char (time_names (n).name (3));
end if;
end if;
-- Write the result.
write (l, str (1 to pos - 1), justified, field);
end write;
procedure textio_write_real
(s : out string; len : out natural; value: real; ndigits : natural);
attribute foreign of textio_write_real : procedure is "GHDL intrinsic";
procedure textio_write_real
(s : out string; len : out natural; value: real; ndigits : natural) is
begin
assert false report "must not be called" severity failure;
end textio_write_real;
-- Parameter DIGITS specifies how many digits to the right of the decimal
-- point are to be output when writing a real number; the default value 0
-- indicates that the number should be output in standard form, consisting
-- of a normalized mantissa plus exponent (e.g., 1.079236E23). If DIGITS is
-- nonzero, then the real number is output as an integer part followed by
-- '.' followed by the fractional part, using the specified number of digits
-- (e.g., 3.14159).
-- Note: Nan, +Inf, -Inf are not to be considered, since these numbers are
-- not in the bounds defined by any real range.
procedure write (L: inout line; value: in real;
justified: in side := right; field: in width := 0;
digits: in natural := 0)
is
-- STR contains the result of the conversion.
variable str : string (1 to 320);
variable len : natural;
begin
textio_write_real (str, len, value, digits);
assert len <= str'length severity failure;
write (l, str (1 to len), justified, field);
end write;
--START-V08
procedure Owrite (L : inout line; value : in Bit_Vector;
Justified : in Side := Right; Field : in Width := 0) is
begin
write (l, to_ostring (value), justified, field);
end Owrite;
procedure Hwrite (L : inout line; value : in Bit_Vector;
Justified : in Side := Right; Field : in Width := 0) is
begin
write (l, to_hstring (value), justified, field);
end Hwrite;
--END-V08
procedure untruncated_text_read --V87
(variable f : text; str : out string; len : out natural); --V87
procedure untruncated_text_read --!V87
(file f : text; str : out string; len : out natural); --!V87
attribute foreign of untruncated_text_read : procedure is "GHDL intrinsic";
procedure untruncated_text_read
(variable f : text; str : out string; len : out natural) is --V87
(file f : text; str : out string; len : out natural) is --!V87
begin
assert false report "must not be called" severity failure;
end untruncated_text_read;
procedure readline (variable f: in text; l: inout line) --V87
procedure readline (file f: text; l: inout line) --!V87
is
variable len, nlen, posn : natural;
variable nl, old_l : line;
variable str : string (1 to 128);
variable is_eol : boolean;
begin
-- LRM93 14.3
-- If parameter L contains a non-null access value at the start of the
-- call, the object designated by that value is deallocated before the
-- new object is created.
if l /= null then
deallocate (l);
end if;
-- We read the input in 128-byte chunks.
-- We keep reading until we reach a newline or there is no more input.
-- The loop invariant is that old_l is allocated and contains the
-- previous chunks read, and posn = old_l.all'length.
posn := 0;
loop
untruncated_text_read (f, str, len);
exit when len = 0;
if str (len) = LF or str (len) = CR then
-- LRM 14.3
-- The representation of the line does not contain the representation
-- of the end of the line.
is_eol := true;
len := len - 1;
-- End of line is any of LF/CR/CR+LF/LF+CR.
if len > 0 and (str (len) = LF or str (len) = CR) then
len := len - 1;
end if;
elsif endfile (f) then
is_eol := true;
else
is_eol := false;
end if;
l := new string (1 to posn + len);
if old_l /= null then
l (1 to posn) := old_l (1 to posn);
deallocate (old_l);
end if;
l (posn + 1 to posn + len) := str (1 to len);
exit when is_eol;
posn := posn + len;
old_l := l;
end loop;
end readline;
-- Replaces L with L (LEFT to/downto L'RIGHT)
procedure trim (l : inout line; left : natural)
is
variable nl : line;
begin
if l = null then
return;
end if;
if l'left < l'right then
-- Ascending.
if left > l'right then
nl := new string'("");
else
nl := new string (left to l'right);
-- nl := new string (1 to l'right + 1 - left);
nl.all := l (left to l'right);
end if;
else
-- Descending
if left < l'right then
nl := new string'("");
else
nl := new string (left downto l'right);
-- nl := new string (left - l'right + 1 downto 1);
nl.all := l (left downto l'right);
end if;
end if;
deallocate (l);
l := nl;
end trim;
-- Replaces L with L (LEFT + 1 to L'RIGHT or LEFT - 1 downto L'RIGHT)
procedure trim_next (l : inout line; left : natural)
is
variable nl : line;
begin
if l = null then
return;
end if;
if l'left < l'right then
-- Ascending.
trim (l, left + 1);
else
-- Descending
trim (l, left - 1);
end if;
end trim_next;
function to_lower (c : character) return character is
begin
if c >= 'A' and c <= 'Z' then
return character'val (character'pos (c) + 32);
else
return c;
end if;
end to_lower;
procedure read (l: inout line; value: out character; good: out boolean)
is
variable nl : line;
begin
if l = null or l'length = 0 then
good := false;
else
value := l (l'left);
trim_next (l, l'left);
good := true;
end if;
end read;
procedure read (l: inout line; value: out character)
is
variable res : boolean;
begin
read (l, value, res);
assert res = true
report "character read failure"
severity failure;
end read;
procedure read (l: inout line; value: out bit; good: out boolean)
is
begin
good := false;
for i in l'range loop
case l(i) is
when ' '
| NBSP --!V87
| HT =>
null;
when '1' =>
value := '1';
good := true;
trim_next (l, i);
return;
when '0' =>
value := '0';
good := true;
trim_next (l, i);
return;
when others =>
return;
end case;
end loop;
return;
end read;
procedure read (l: inout line; value: out bit)
is
variable res : boolean;
begin
read (l, value, res);
assert res = true
report "bit read failure"
severity failure;
end read;
procedure read (l: inout line; value: out bit_vector; good: out boolean)
is
-- Number of bit to parse.
variable len : natural;
variable pos, last : natural;
variable res : bit_vector (1 to value'length);
-- State of the previous byte:
-- LEADING: blank before the bit vector.
-- FOUND: bit of the vector.
type state_type is (leading, found);
variable state : state_type;
begin
-- Initialization.
len := value'length;
if len = 0 then
-- If VALUE is a nul array, return now.
-- L stay unchanged.
-- FIXME: should blanks be removed ?
good := true;
return;
end if;
good := false;
state := leading;
pos := res'left;
for i in l'range loop
case l(i) is
when ' '
| NBSP --!V87
| HT =>
case state is
when leading =>
null;
when found =>
return;
end case;
when '1' | '0' =>
case state is
when leading =>
state := found;
when found =>
null;
end case;
if l(i) = '0' then
res (pos) := '0';
else
res (pos) := '1';
end if;
pos := pos + 1;
len := len - 1;
last := i;
exit when len = 0;
when others =>
return;
end case;
end loop;
if len /= 0 then
-- Not enough bits.
return;
end if;
-- Note: if LEN = 0, then FIRST and LAST have been set.
good := true;
value := res;
trim_next (l, last);
return;
end read;
procedure read (l: inout line; value: out bit_vector)
is
variable res : boolean;
begin
read (l, value, res);
assert res = true
report "bit_vector read failure"
severity failure;
end read;
procedure read (l: inout line; value: out boolean; good: out boolean)
is
-- State:
-- BLANK: space are being scaned.
-- L_TF : T(rue) or F(alse) has been scanned.
-- L_RA : (t)R(ue) or (f)A(lse) has been scanned.
-- L_UL : (tr)U(e) or (fa)L(se) has been scanned.
-- L_ES : (tru)E or (fal)S(e) has been scanned.
type state_type is (blank, l_tf, l_ra, l_ul, l_es);
variable state : state_type;
-- Set to TRUE if T has been scanned, to FALSE if F has been scanned.
variable res : boolean;
variable c : character;
begin
-- By default, it is a failure.
good := false;
state := blank;
for i in l'range loop
c := l (i);
case state is
when blank =>
if is_whitespace (c) then
null;
elsif c = 'f' or c = 'T' then
res := true;
state := l_tf;
elsif c = 'f' or c = 'F' then
res := false;
state := l_tf;
else
return;
end if;
when l_tf =>
if res = true and (c = 'r' or c = 'R') then
state := l_ra;
elsif res = false and (c = 'a' or C = 'A') then
state := l_ra;
else
return;
end if;
when l_ra =>
if res = true and (c = 'u' or C = 'U') then
state := l_ul;
elsif res = false and (c = 'l' or c = 'L') then
state := l_ul;
else
return;
end if;
when l_ul =>
if res = true and (c = 'e' or c = 'E') then
trim_next (l, i);
good := true;
value := true;
return;
elsif res = false and (c = 's' or c = 'S') then
state := l_es;
else
return;
end if;
when l_es =>
if res = false and (c = 'e' or c = 'E') then
trim_next (l, i);
good := true;
value := false;
return;
else
return;
end if;
end case;
end loop;
return;
end read;
procedure read (l: inout line; value: out boolean)
is
variable res : boolean;
begin
read (l, value, res);
assert res = true
report "boolean read failure"
severity failure;
end read;
function char_to_nat (c : character) return natural
is
begin
return character'pos (c) - character'pos ('0');
end char_to_nat;
procedure read (l: inout line; value: out integer; good: out boolean)
is
variable val : integer;
variable d : natural;
type state_t is (leading, sign, digits);
variable cur_state : state_t := leading;
begin
val := 1;
for i in l'range loop
case cur_state is
when leading =>
case l(i) is
when ' '
| NBSP --!V87
| ht =>
null;
when '+' =>
cur_state := sign;
when '-' =>
val := -1;
cur_state := sign;
when '0' to '9' =>
val := char_to_nat (l(i));
cur_state := digits;
when others =>
good := false;
return;
end case;
when sign =>
case l(i) is
when '0' to '9' =>
val := val * char_to_nat (l(i));
cur_state := digits;
when others =>
good := false;
return;
end case;
when digits =>
case l(i) is
when '0' to '9' =>
d := char_to_nat (l(i));
val := val * 10;
if val < 0 then
val := val - d;
else
val := val + d;
end if;
when others =>
trim (l, i);
good := true;
value := val;
return;
end case;
end case;
end loop;
deallocate (l);
l := new string'("");
if cur_state /= leading then
good := true;
value := val;
else
good := false;
end if;
end read;
procedure read (l: inout line; value: out integer)
is
variable res : boolean;
begin
read (l, value, res);
assert res = true
report "integer read failure"
severity failure;
end read;
function textio_read_real (s : string) return real;
attribute foreign of textio_read_real : function is "GHDL intrinsic";
function textio_read_real (s : string) return real is
begin
assert false report "must not be called" severity failure;
return 0.0;
end textio_read_real;
procedure read (l: inout line; value: out real; good: out boolean)
is
-- The parsing is done with a state machine.
-- LEADING: leading blank suppression.
-- SIGN: a sign has been found.
-- DIGITS: integer parts
-- DECIMALS, DECIMALS2: digits after the dot.
-- EXPONENT_SIGN: sign after "E"
-- EXPONENT_1: first digit of the exponent.
-- EXPONENT: digits of the exponent.
type state_t is (leading, sign, digits, decimals, decimals2,
exponent_sign, exponent_1, exponent);
variable state : state_t := leading;
variable left : positive;
procedure set_value (right : positive; off : natural) is
begin
if right > left then
value := textio_read_real (l (left to right - off));
else
value := textio_read_real (l (left downto right + off));
end if;
good := True;
end set_value;
begin
-- By default, parsing has failed.
good := false;
-- Iterate over all characters of the string.
-- Return immediatly in case of parse error.
-- Trim L and call SET_VALUE and return in case of success.
for i in l'range loop
case state is
when leading =>
left := i;
case l (i) is
when ' '
| NBSP --!V87
| ht =>
null;
when '+' | '-' =>
state := sign;
when '0' to '9' =>
state := digits;
when others =>
return;
end case;
when sign =>
case l (i) is
when '0' to '9' =>
state := digits;
when others =>
return;
end case;
when digits =>
case l (i) is
when '0' to '9' =>
null;
when '.' =>
state := decimals;
when others =>
-- A "." (dot) is required in the string.
return;
end case;
when decimals | decimals2 =>
case l (i) is
when '0' to '9' =>
state := decimals2;
when 'e' | 'E' =>
-- "nnn.E" is erroneous.
if state = decimals then
return;
end if;
state := exponent_sign;
when others =>
-- "nnn.XX" is erroneous.
if state = decimals then
return;
end if;
set_value (i, 1);
trim (l, i);
return;
end case;
when exponent_sign =>
case l (i) is
when '+' | '-' =>
state := exponent_1;
when '0' to '9' =>
state := exponent;
when others =>
-- Error.
return;
end case;
when exponent_1 | exponent =>
case l (i) is
when '0' to '9' =>
state := exponent;
when others =>
set_value (i, 1);
trim (l, i);
return;
end case;
end case;
end loop;
-- End of string.
case state is
when leading | sign | digits =>
-- Erroneous.
return;
when decimals =>
-- "nnn.XX" is erroneous.
return;
when decimals2 =>
null;
when exponent_sign =>
-- Erroneous ("NNN.NNNE")
return;
when exponent_1 =>
-- "NNN.NNNE-"
return;
when exponent =>
null;
end case;
set_value (l'right, 0);
deallocate (l);
l := new string'("");
end read;
procedure read (l: inout line; value: out real)
is
variable res : boolean;
begin
read (l, value, res);
assert res = true
report "real read failure"
severity failure;
end read;
procedure read (l: inout line; value: out time; good: out boolean)
is
-- The result.
variable res : time;
-- UNIT is computed from the unit name, the exponent and the number of
-- digits before the dot. UNIT is the weight of the current digit.
variable unit : time;
-- Number of digits before the dot.
variable nbr_digits : integer;
-- True if a unit name has been found. Used temporaly to know the status
-- at the end of the search loop.
variable unit_found : boolean;
-- True if the number is negative.
variable is_neg : boolean;
-- Value of the exponent.
variable exp : integer;
-- True if the exponent is negative.
variable exp_neg : boolean;
-- Unit name extracted from the string.
variable unit_name : string (1 to 3);
-- state is the kind of the previous character parsed.
-- LEADING: leading blanks
-- SIGN: + or - as the first character of the number.
-- DIGITS: digit of the integer part of the number.
-- DOT: dot (.) after the integer part and before the decimal part.
-- DECIMALS: digit of the decimal part.
-- EXPONENT_MARK: e or E.
-- EXPONENT_SIGN: + or - just after the exponent mark (E).
-- EXPONENT: digit of the exponent.
-- UNIT_BLANK: blank after the exponent.
-- UNIT_1, UNIT_2, UNIT_3: first, second, third character of the unit.
type state_type is (leading, sign, digits, dot, decimals,
exponent_mark, exponent_sign, exponent,
unit_blank, unit_1, unit_2, unit_3);
variable state : state_type;
-- Used during the second scan of the string, TRUE is digits is being
-- scaned.
variable has_digits : boolean;
-- Position at the end of the string.
variable pos : integer;
-- Used to compute POS.
variable length : integer;
begin
-- Initialization.
-- Fail by default; therefore, in case of error, a return statement is
-- ok.
good := false;
nbr_digits := 0;
is_neg := false;
exp := 0;
exp_neg := false;
res := 0 fs;
-- Look for exponent and unit name.
-- Parse the string: this loop checks the correctness of the format, and
-- must return (GOOD has been set to FALSE) in case of error.
-- Set: NBR_DIGITS, IS_NEG, EXP, EXP_NEG.
state := leading;
for i in l'range loop
case l (i) is
when ' '
| NBSP --!V87
| HT =>
case state is
when leading | unit_blank =>
null;
when sign | dot | exponent_mark | exponent_sign =>
return;
when digits | decimals | exponent =>
state := unit_blank;
when unit_1 | unit_2 =>
exit;
when unit_3 =>
-- Cannot happen, since an exit is performed at unit_3.
assert false report "internal error" severity failure;
end case;
when '+' | '-' =>
case state is
when leading =>
if l(i) = '-' then
is_neg := true;
end if;
state := sign;
when exponent_mark =>
if l(i) = '-' then
exp_neg := true;
end if;
state := exponent_sign;
when others =>
return;
end case;
when '0' to '9' =>
case state is
when exponent_mark | exponent_sign | exponent =>
exp := exp * 10 + char_to_nat (l (i));
state := exponent;
when leading | sign | digits =>
-- Leading "0" are not significant.
if nbr_digits > 0 or l (i) /= '0' then
nbr_digits := nbr_digits + 1;
end if;
state := digits;
when decimals =>
null;
when dot =>
state := decimals;
when others =>
return;
end case;
when 'a' to 'z' | 'A' to 'Z' =>
case state is
when digits | decimals =>
-- "E" has exponent mark.
if l (i) = 'e' or l(i) = 'E' then
state := exponent_mark;
else
return;
end if;
when unit_blank =>
unit_name (1) := to_lower (l(i));
state := unit_1;
when unit_1 =>
unit_name (2) := to_lower (l(i));
state := unit_2;
pos := i;
when unit_2 =>
unit_name (3) := to_lower (l(i));
state := unit_3;
exit;
when others =>
return;
end case;
when '.' =>
case state is
when digits =>
state := decimals;
when others =>
exit;
end case;
when others =>
exit;
end case;
end loop;
-- A unit name (2 or 3 letters) must have been found.
-- The string may end anywhere.
if state /= unit_2 and state /= unit_3 then
return;
end if;
-- Compute EXP with the sign.
if exp_neg then
exp := -exp;
end if;
-- Search the unit name in the list of time names.
unit_found := false;
for i in time_names'range loop
-- The first two characters must match (case insensitive).
-- The third character must match if:
-- * the unit name is a three characters identifier (ie, not a blank).
-- * there is a third character in STR.
if time_names (i).name (1) = unit_name (1)
and time_names (i).name (2) = unit_name (2)
and (time_names (i).name (3) = ' '
or time_names (i).name (3) = unit_name (3))
then
unit := time_names (i).val;
unit_found := true;
-- POS is set to the position of the first invalid character.
if time_names (i).name (3) = ' ' then
length := 1;
else
length := 2;
end if;
if l'left < l'right then
pos := pos + length;
else
pos := pos - length;
end if;
exit;
end if;
end loop;
if not unit_found then
return;
end if;
-- Compute UNIT, the weight of the first non-significant character.
nbr_digits := nbr_digits + exp - 1;
if nbr_digits < 0 then
unit := unit / 10 ** (-nbr_digits);
else
unit := unit * 10 ** nbr_digits;
end if;
-- HAS_DIGITS will be set as soon as a digit is found.
-- No error is expected here (this has been checked during the first
-- pass).
has_digits := false;
for i in l'range loop
case l (i) is
when ' '
| NBSP --!V87
| HT =>
if has_digits then
exit;
end if;
when '+' | '-' =>
if not has_digits then
has_digits := true;
else
assert false report "internal error" severity failure;
return;
end if;
when '0' to '9' =>
-- Leading "0" are not significant.
if l (i) /= '0' or res /= 0 fs then
res := res + char_to_nat (l (i)) * unit;
unit := unit / 10;
end if;
has_digits := true;
when 'a' to 'z' | 'A' to 'Z' =>
if has_digits then
exit;
else
assert false report "internal error" severity failure;
return;
end if;
when '.' =>
if not has_digits then
assert false report "internal error" severity failure;
return;
end if;
when others =>
assert false report "internal error" severity failure;
return;
end case;
end loop;
-- Set VALUE.
if is_neg then
value := -res;
else
value := res;
end if;
good := true;
trim (l, pos);
return;
end read;
procedure read (l: inout line; value: out time)
is
variable res : boolean;
begin
read (l, value, res);
assert res = true
report "time read failure"
severity failure;
end read;
procedure read (l: inout line; value: out string; good: out boolean)
is
constant len : natural := value'length;
begin
if l'length < len then
good := false;
return;
end if;
good := true;
if len = 0 then
return;
end if;
if l'left < l'right then
-- Ascending (expected common case).
value := l (l'left to l'left + len - 1);
trim (l, l'left + len);
elsif l'left = l'right then
-- String of 1 character. We don't know the direction and therefore
-- can't use the code below which does a slice.
value := l.all;
deallocate (l);
l := new string'("");
else
-- Descending.
value := l (l'left downto l'left - len + 1);
trim (l, l'left - len);
end if;
end read;
procedure read (l: inout line; value: out string)
is
variable res : boolean;
begin
read (l, value, res);
assert res = true
report "string read failure"
severity failure;
end read;
--START-V08
procedure Sread (L : inout Line; Value : out String; Strlen : out Natural)
is
constant maxlen : natural := Value'Length;
alias value1 : string (1 to maxlen) is Value;
variable skipping : boolean := True;
variable f, len, nl_left : natural;
variable nl : line;
begin
-- Skip leading spaces. F designates the index of the first non-space
-- character, LEN the length of the extracted string.
len := 0;
for i in l'range loop
if skipping then
if not is_whitespace (l (i)) then
skipping := false;
f := i;
len := 1;
end if;
else
exit when is_whitespace (l (i));
len := len + 1;
exit when len = maxlen;
end if;
end loop;
-- Copy string.
if l'ascending then
value1 (1 to len) := l (f to f + len - 1);
else
value1 (1 to len) := l (f downto f - len + 1);
end if;
strlen := len;
if l'ascending then
if len = 0 then
f := l'right + 1;
end if;
nl_left := f + len;
nl := new string (nl_left to l'right);
nl.all := l (nl_left to l'right);
else
if len = 0 then
f := l'right - 1;
end if;
nl_left := f - len;
nl := new string (nl_left downto l'right);
nl.all := l (nl_left downto l'right);
end if;
deallocate (l);
l := nl;
end sread;
subtype bv4 is bit_vector (1 to 4);
function char_to_bv4 (c : character) return bv4 is
begin
case c is
when '0' => return "0000";
when '1' => return "0001";
when '2' => return "0010";
when '3' => return "0011";
when '4' => return "0100";
when '5' => return "0101";
when '6' => return "0110";
when '7' => return "0111";
when '8' => return "1000";
when '9' => return "1001";
when 'a' | 'A' => return "1010";
when 'b' | 'B' => return "1011";
when 'c' | 'C' => return "1100";
when 'd' | 'D' => return "1101";
when 'e' | 'E' => return "1110";
when 'f' | 'F' => return "1111";
when others =>
assert false report "bad hexa digit" severity failure;
end case;
end char_to_bv4;
procedure Oread (L : inout Line; Value : out Bit_Vector; Good : out Boolean)
is
-- Length of Value
constant vlen : natural := value'length;
-- Number of octal digits for Value
constant olen : natural := (vlen + 2) / 3;
variable res : bit_vector (1 to olen * 3);
-- Number of bit to parse.
variable len : natural;
variable pos : natural;
-- Last character from LEN to be removed
variable last : integer;
-- State of the previous byte:
-- SKIP: blank before the bit vector.
-- DIGIT: previous character was a digit
-- UNDERSCORE: was '_'
type state_type is (skip, digit, underscore);
variable state : state_type;
begin
-- Initialization.
if vlen = 0 then
-- If VALUE is a nul array, return now.
-- L stay unchanged.
-- FIXME: should blanks be removed ?
good := true;
return;
end if;
good := false;
state := skip;
pos := res'left;
if l'ascending then
last := l'left - 1;
else
last := l'left + 1;
end if;
for i in l'range loop
case l (i) is
when ' '
| NBSP
| HT =>
exit when state /= skip;
when '_' =>
exit when state /= digit;
state := underscore;
when '0' to '7' =>
res (pos to pos + 2) := char_to_bv4 (l (i)) (2 to 4);
last := i;
state := digit;
pos := pos + 3;
-- LRM08 16.4
-- Character removal and compostion also stops when the expected
-- number of digits have been removed.
exit when pos = res'right + 1;
when others =>
exit;
end case;
end loop;
-- LRM08 16.4
-- The OREAD or HEAD procedure does not succeed if less than the expected
-- number of digits are removed.
if pos /= res'right + 1 then
return;
end if;
-- LRM08 16.4
-- The rightmost value'length bits of the binary number are used to form
-- the result for the VALUE parameter, [with a '0' element corresponding
-- to a 0 bit and a '1' element corresponding to a 1 bit]. The OREAD or
-- HREAD procedure does not succeed if any unused bits are 1.
for i in 1 to res'right - vlen loop
if res (i) = '1' then
return;
end if;
end loop;
Value := res (res'right - vlen + 1 to res'right);
good := true;
trim_next (l, last);
end Oread;
procedure Oread (L : inout Line; Value : out Bit_Vector)
is
variable res : boolean;
begin
Oread (l, value, res);
assert res = true
report "octal bit_vector read failure"
severity failure;
end Oread;
procedure Hread (L : inout Line; Value : out Bit_Vector; Good : out Boolean)
is
-- Length of Value
constant vlen : natural := value'length;
-- Number of hexa digits for Value
constant hlen : natural := (vlen + 3) / 4;
variable res : bit_vector (1 to hlen * 4);
-- Number of bit to parse.
variable len : natural;
variable pos : natural;
-- Last character from LEN to be removed
variable last : integer;
-- State of the previous byte:
-- SKIP: blank before the bit vector.
-- DIGIT: previous character was a digit
-- UNDERSCORE: was '_'
type state_type is (skip, digit, underscore);
variable state : state_type;
begin
-- Initialization.
if vlen = 0 then
-- If VALUE is a nul array, return now.
-- L stay unchanged.
-- FIXME: should blanks be removed ?
good := true;
return;
end if;
good := false;
state := skip;
pos := res'left;
if l'ascending then
last := l'left - 1;
else
last := l'left + 1;
end if;
for i in l'range loop
case l (i) is
when ' '
| NBSP
| HT =>
exit when state /= skip;
when '_' =>
exit when state /= digit;
state := underscore;
when '0' to '9' | 'a' to 'f' | 'A' to 'F' =>
res (pos to pos + 3) := char_to_bv4 (l (i));
last := i;
state := digit;
pos := pos + 4;
-- LRM08 16.4
-- Character removal and compostion also stops when the expected
-- number of digits have been removed.
exit when pos = res'right + 1;
when others =>
exit;
end case;
end loop;
-- LRM08 16.4
-- The OREAD or HEAD procedure does not succeed if less than the expected
-- number of digits are removed.
if pos /= res'right + 1 then
return;
end if;
-- LRM08 16.4
-- The rightmost value'length bits of the binary number are used to form
-- the result for the VALUE parameter, [with a '0' element corresponding
-- to a 0 bit and a '1' element corresponding to a 1 bit]. The OREAD or
-- HREAD procedure does not succeed if any unused bits are 1.
for i in 1 to res'right - vlen loop
if res (i) = '1' then
return;
end if;
end loop;
Value := res (res'right - vlen + 1 to res'right);
good := true;
trim_next (l, last);
end Hread;
procedure Hread (L : inout Line; Value : out Bit_Vector)
is
variable res : boolean;
begin
Hread (l, value, res);
assert res = true
report "hexa bit_vector read failure"
severity failure;
end Hread;
--END-V08
end textio;
| gpl-2.0 | 5470a51ad139e2bdb0d155e41d543184 | 0.565197 | 3.61377 | false | false | false | false |
rafa-jfet/OFM | ARCHIVOS VHDL/intlv.vhd | 1 | 4,425 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 02:38:07 07/01/2015
-- Design Name:
-- Module Name: intlv - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_logic_arith.ALL;
use IEEE.std_logic_unsigned.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity intlv is
Generic ( bits_BPSK : integer := 96;
bits_QPSK : integer := 192;
bits_8PSK : integer := 288;
col_BPSK : integer := 12;
col_QPSK : integer := 12;
col_8PSK : integer := 18;
fil_BPSK : integer := 8;
fil_QPSK : integer := 16;
fil_8PSK : integer := 16);
Port ( clk : in STD_LOGIC;
reset : in STD_LOGIC;
button : in STD_LOGIC;
modulation : in STD_LOGIC_VECTOR (2 downto 0);
bit_in : in STD_LOGIC;
ok_bit_in : in STD_LOGIC;
bit_out : out STD_LOGIC_VECTOR (0 downto 0);
dir_bit : out STD_LOGIC_VECTOR (8 downto 0);
write_mem : out STD_LOGIC_VECTOR (0 downto 0);
ok_bit_out : out STD_LOGIC
);
end intlv;
architecture Behavioral of intlv is
type estado is ( reposo,
inicio,
escribe,
salida,
salida_ok
);
signal estado_actual, estado_nuevo : estado;
signal dir, p_dir : STD_LOGIC_VECTOR(8 downto 0);
signal NUM_BITS : integer range 0 to bits_8PSK := 0;
signal NUM_COL : integer range 0 to col_8PSK := 0;
signal BITS_FILA : integer range 0 to 4;
begin
dir_bit <= dir;
bit_out(0) <= bit_in;
initialization : process ( modulation)
begin
case modulation is
when "100" =>
NUM_BITS <= bits_BPSK;
NUM_COL <= col_BPSK;
BITS_FILA <= 3;
when "010" =>
NUM_BITS <= bits_QPSK;
NUM_COL <= col_QPSK;
BITS_FILA <= 4;
when OTHERS =>
NUM_BITS <= bits_8PSK;
NUM_COL <= col_8PSK;
BITS_FILA <= 4;
end case;
end process;
comb : process ( estado_actual, button, modulation, dir, ok_bit_in, NUM_BITS, BITS_FILA )
--variable BITS_FILA : integer := 0; --bits necesarios para direccionar las filas
begin
write_mem(0) <= '0';
ok_bit_out <= '0';
p_dir <= dir;
estado_nuevo <= estado_actual;
case estado_actual is
when reposo =>
if ( button = '1' ) then
p_dir <= (others => '0');
estado_nuevo <= inicio;
end if;
-- case modulation is
--
-- when "100" =>
-- NUM_BITS <= bits_BPSK;
-- NUM_COL <= col_BPSK;
-- BITS_FILA := 3;
--
-- when "010" =>
-- NUM_BITS <= bits_QPSK;
-- NUM_COL <= col_QPSK;
-- BITS_FILA := 4;
--
-- when OTHERS =>
-- NUM_BITS <= bits_8PSK;
-- NUM_COL <= col_8PSK;
-- BITS_FILA := 4;
--
-- end case;
when inicio =>
if ( ok_bit_in = '1' ) then
write_mem(0) <= '1';
estado_nuevo <= escribe;
end if;
if (dir = NUM_BITS) then
estado_nuevo <= salida;
p_dir <= (others => '0');
end if;
when escribe =>
p_dir <= dir +1;
estado_nuevo <= inicio;
when salida =>
estado_nuevo <= salida_ok;
when salida_ok =>
estado_nuevo <= salida;
ok_bit_out <= '1';
if ( dir = NUM_BITS -1) then -- comprueba si se ha completado un simbolo
estado_nuevo <= inicio;
p_dir <= (others => '0');
elsif ( dir(8 downto BITS_FILA) = NUM_COL -1) then -- comprueba si se ha completado una fila
p_dir(8 downto BITS_FILA) <= (others => '0');
p_dir(BITS_FILA -1 downto 0) <= dir (BITS_FILA -1 downto 0) +1;
else
p_dir (8 downto BITS_FILA) <= dir(8 downto BITS_FILA) +1; --pasa a la siguiente columna
end if;
end case;
end process;
sinc : process (reset, clk)
begin
if ( reset = '1' ) then
dir <= ( others=>'0' );
estado_actual <= reposo;
elsif ( rising_edge(clk) ) then
dir <= p_dir;
estado_actual <= estado_nuevo;
end if;
end process;
end Behavioral;
| gpl-3.0 | 534bc19c5c58efe6a5e77ae350b9505a | 0.550734 | 3.010204 | false | false | false | false |
rafa-jfet/OFM | ARCHIVOS VHDL/mapper.vhd | 1 | 3,270 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 00:29:35 04/24/2015
-- Design Name:
-- Module Name: mapper - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_logic_arith.ALL;
use IEEE.std_logic_signed.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity mapper is
Generic ( DIR_INICIAL : STD_LOGIC_VECTOR (6 downto 0) := "0010000"; -- 16
DIR_FINAL : INTEGER := 112;
pos_A2 : STD_LOGIC_VECTOR (7 downto 0) := "01100100"; -- 100
pos_A1 : STD_LOGIC_VECTOR (7 downto 0) := "01000111"; -- 71
A0 : STD_LOGIC_VECTOR (7 downto 0) := "00000000"; -- 0
neg_A1 : STD_LOGIC_VECTOR (7 downto 0) := "10111001"; -- -71
neg_A2 : STD_LOGIC_VECTOR (7 downto 0) := "10011100"); -- -100
Port ( clk : in STD_LOGIC;
reset : in STD_LOGIC;
anginc : in STD_LOGIC_VECTOR (2 downto 0);
ok_anginc : in STD_LOGIC;
dir_data : out STD_LOGIC_VECTOR (6 downto 0);
write_data : out STD_LOGIC_VECTOR (0 downto 0);
Q_data : out STD_LOGIC_VECTOR (7 downto 0) := A0;
I_data : out STD_LOGIC_VECTOR (7 downto 0) := neg_A2;
ok_data : out STD_LOGIC);
end mapper;
architecture Behavioral of mapper is
signal ang, p_ang : STD_LOGIC_VECTOR (2 downto 0) := "100";
signal dir, p_dir : STD_LOGIC_VECTOR (6 downto 0) := DIR_INICIAL;
signal p_write_data : STD_LOGIC_VECTOR (0 downto 0);
begin
dir_data(6) <= not(dir(6));
dir_data(5 downto 0) <= dir(5 downto 0);
comb : process(anginc, ok_anginc, ang, dir)
begin
ok_data <= '0';
p_write_data(0) <= '0';
p_dir <= dir;
p_ang <= ang;
if ( ok_anginc = '1' ) then
p_ang <= ang + anginc;
p_write_data(0) <= '1';
p_dir <= dir +1;
if ( dir = DIR_FINAL -1 ) then
ok_data <= '1';
elsif ( dir = DIR_FINAL ) then
p_dir <= DIR_INICIAL +1;
p_ang <= "100" + anginc;
end if;
end if;
case ang is
when "000" =>
Q_data <= A0;
I_data <= pos_A2;
when "001" =>
Q_data <= pos_A1;
I_data <= pos_A1;
when "010" =>
Q_data <= pos_A2;
I_data <= A0;
when "011" =>
Q_data <= pos_A1;
I_data <= neg_A1;
when "100" =>
Q_data <= A0;
I_data <= neg_A2;
when "101" =>
Q_data <= neg_A1;
I_data <= neg_A1;
when "110" =>
Q_data <= neg_A2;
I_data <= A0;
when OTHERS =>
Q_data <= neg_A1;
I_data <= pos_A1;
end case;
end process;
sinc : process (reset, clk)
begin
if ( reset = '1' ) then
ang <= "100";
dir <= DIR_INICIAL;
write_data(0) <= '0';
elsif ( rising_edge(clk) ) then
ang <= p_ang;
dir <= p_dir;
write_data(0) <= p_write_data(0);
end if;
end process;
end Behavioral;
| gpl-3.0 | e737b0e8d608c930a8d5f982e19ee60d | 0.543425 | 2.868421 | false | false | false | false |
gmsanchez/OrgComp | TP_02/TB_SN54LV165A.vhd | 1 | 3,793 | --------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 16:06:18 10/01/2014
-- Design Name:
-- Module Name: E:/2014/Academico/OC/2014/tp2/TB_SN54LV165A.vhd
-- Project Name: tp2
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: SN54LV165A
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY TB_SN54LV165A IS
END TB_SN54LV165A;
ARCHITECTURE behavior OF TB_SN54LV165A IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT SN54LV165A
PORT(
CLK : IN std_logic;
CLKIN : IN std_logic;
NLOAD : IN std_logic;
SER : IN std_logic;
DIN : IN std_logic_vector(7 downto 0);
Q : OUT std_logic;
NQ : OUT std_logic
);
END COMPONENT;
--Inputs
signal CLK : std_logic := '0';
signal CLKIN : std_logic := '0';
signal NLOAD : std_logic := '0';
signal SER : std_logic := '0';
signal DIN : std_logic_vector(7 downto 0) := (others => '0');
--Outputs
signal Q : std_logic;
signal NQ : std_logic;
-- Clock period definitions
constant CLK_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: SN54LV165A PORT MAP (
CLK => CLK,
CLKIN => CLKIN,
NLOAD => NLOAD,
SER => SER,
DIN => DIN,
Q => Q,
NQ => NQ
);
-- Clock process definitions
CLK_process :process
begin
CLK <= '0';
wait for CLK_period/2;
CLK <= '1';
wait for CLK_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
nload<='1';
-- hold reset state for 20 ns.
wait for 20 ns;
-- insert stimulus here
CLKIN<='1';
SER<='0';
NLOAD<='1';
DIN<="00000000";
wait for 20 ns;
NLOAD<='0';
DIN<="11010101";
wait for 5 ns;
NLOAD<='1';
wait for 20 ns;
CLKIN<='0';
wait;
end process;
corr_proc: process(CLK)
variable theTime : time;
begin
theTime := now;
if theTime=30000 ps then
report time'image(theTime);
assert (q='0' and nq='1')
report("Salidas erroneas.")
severity ERROR;
end if;
if theTime=45000 ps then
report time'image(theTime);
assert (q='1' and nq='0')
report("Salidas erroneas.")
severity ERROR;
end if;
if theTime=90000 ps then
report time'image(theTime);
assert (q='0' and nq='1')
report("Salidas erroneas.")
severity ERROR;
end if;
if theTime=100000 ps then
report time'image(theTime);
assert (q='1' and nq='0')
report("Salidas erroneas.")
severity ERROR;
end if;
if theTime=110000 ps then
report time'image(theTime);
assert (q='0' and nq='1')
report("Salidas erroneas.")
severity ERROR;
end if;
if theTime=120000 ps then
report time'image(theTime);
assert (q='1' and nq='0')
report("Salidas erroneas.")
severity ERROR;
end if;
end process;
END;
| gpl-2.0 | 183ebe04b4fc11554fa76c879b6c2728 | 0.56657 | 3.407907 | false | false | false | false |
emogenet/ghdl | testsuite/gna/issue50/idct.d/prog.vhd | 2 | 2,867 | --test bench written by Alban Bourge @ TIMA
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.pkg_tb.all;
entity prog is
port(
clock : in std_logic;
reset : in std_logic;
step : in std_logic;
instr_next : out instruction
);
end prog;
architecture rtl of prog is
signal instr_n : instruction := instr_rst;
--Table describing fsm behavior
constant fsm_behavior : table_behavior := (
--##PROGRAM_GOES_DOWN_HERE##--
0 => (state => Rst, context_uut => "00", arg => to_unsigned(0,ARG_WIDTH)),
1 => (state => Rst, context_uut => "00", arg => to_unsigned(0,ARG_WIDTH)),
2 => (state => Sig_start, context_uut => "01", arg => to_unsigned(0,ARG_WIDTH)),
3 => (state => Ack_data, context_uut => "01", arg => to_unsigned(64,ARG_WIDTH)),
4 => (state => Cp_search, context_uut => "01", arg => to_unsigned(0,ARG_WIDTH)),
5 => (state => Idle, context_uut => "00", arg => to_unsigned(5,ARG_WIDTH)),
6 => (state => Rst_uut, context_uut => "00", arg => to_unsigned(0,ARG_WIDTH)),
7 => (state => Idle, context_uut => "00", arg => to_unsigned(5,ARG_WIDTH)),
8 => (state => Sig_start, context_uut => "10", arg => to_unsigned(0,ARG_WIDTH)),
9 => (state => Ack_data, context_uut => "10", arg => to_unsigned(64,ARG_WIDTH)),
10 => (state => Running, context_uut => "10", arg => to_unsigned(20,ARG_WIDTH)),
11 => (state => Cp_search, context_uut => "10", arg => to_unsigned(0,ARG_WIDTH)),
12 => (state => Idle, context_uut => "00", arg => to_unsigned(5,ARG_WIDTH)),
13 => (state => Rst_uut, context_uut => "00", arg => to_unsigned(0,ARG_WIDTH)),
14 => (state => Idle, context_uut => "00", arg => to_unsigned(5,ARG_WIDTH)),
15 => (state => Rest_ini0, context_uut => "01", arg => to_unsigned(0,ARG_WIDTH)),
16 => (state => Waitfor, context_uut => "01", arg => to_unsigned(64,ARG_WIDTH)),
17 => (state => Idle, context_uut => "00", arg => to_unsigned(5,ARG_WIDTH)),
18 => (state => Rst_uut, context_uut => "00", arg => to_unsigned(0,ARG_WIDTH)),
19 => (state => Idle, context_uut => "00", arg => to_unsigned(5,ARG_WIDTH)),
20 => (state => Rest_ini0, context_uut => "10", arg => to_unsigned(0,ARG_WIDTH)),
21 => (state => Waitfor, context_uut => "10", arg => to_unsigned(64,ARG_WIDTH)),
22 => (state => Stop, context_uut => "00", arg => to_unsigned(0,ARG_WIDTH)),
--##PROGRAM_GOES_OVER_HERE##--
others => instr_rst);
signal pc : unsigned(PC_SIZE - 1 downto 0) := (others => '0');
begin
drive_state : process (reset,clock) is
begin
if reset = '1' then
instr_n <= instr_rst;
pc <= (others => '0');
elsif rising_edge(clock) then
if (step = '1') then
pc <= pc + 1;
end if;
instr_n <= fsm_behavior(to_integer(pc));
end if;
end process drive_state;
--instr_next <= instr_n;
instr_next <= fsm_behavior(to_integer(pc));
end rtl;
| gpl-2.0 | 4b1b4dd995f395a64ffe8edd00df2a7e | 0.592954 | 2.830207 | false | false | false | false |
emogenet/ghdl | testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS2_Mixed_Tech/lead_lag_diff.vhd | 4 | 1,775 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
library ieee; use ieee.std_logic_1164.all;
entity lead_lag_diff is
port ( signal clk : in std_logic; -- clock
quantity input : in real;
quantity output : out real );
end entity lead_lag_diff;
----------------------------------------------------------------
architecture bhv of lead_lag_diff is
constant k : real := 400.0; -- normalize gain
signal z_out : real := 0.0;
begin
proc : process (clk)
variable zi_dly1 : real := 0.0; -- input delayed 1 clk cycle
variable zo_dly1 : real := 0.0; -- output delayed 1 clk cycle
variable z_new : real := 0.0; -- new output value this clk cycle
begin
zo_dly1 := z_out; -- store previous output value
z_new := 0.6163507 * input - 0.6144184 * zi_dly1 + 0.2307692 * zo_dly1;
zi_dly1 := input; -- store previous input value
z_out <= z_new;
end process;
output == k * z_out'ramp(100.0e-9); -- ensure continuous transitions on output
end bhv;
| gpl-2.0 | 93389348f000679d31972d33243c37ca | 0.648451 | 3.817204 | false | false | false | false |
gmsanchez/OrgComp | TP_01/TB_C74F85_4B.vhd | 1 | 5,115 | --------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 14:35:59 09/17/2014
-- Design Name:
-- Module Name: /home/gsanchez/Apps/TP_01/TB_C74F85_4B.vhd
-- Project Name: TP_01
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: C74F85_4B
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
USE ieee.numeric_std.ALL;
ENTITY TB_C74F85_4B IS
END TB_C74F85_4B;
ARCHITECTURE behavior OF TB_C74F85_4B IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT C74F85_4B
PORT(
A : IN std_logic_vector(3 downto 0);
B : IN std_logic_vector(3 downto 0);
IL : IN std_logic;
IE : IN std_logic;
IH : IN std_logic;
OL : OUT std_logic;
OE : OUT std_logic;
OH : OUT std_logic
);
END COMPONENT;
--Inputs
signal A : std_logic_vector(3 downto 0) := (others => '0');
signal B : std_logic_vector(3 downto 0) := (others => '0');
signal IL : std_logic := '0';
signal IE : std_logic := '0';
signal IH : std_logic := '0';
--Outputs
signal OL : std_logic;
signal OE : std_logic;
signal OH : std_logic;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: C74F85_4B PORT MAP (
A => A,
B => B,
IL => IL,
IE => IE,
IH => IH,
OL => OL,
OE => OE,
OH => OH
);
-- Stimulus process
stim_proc: process
begin
-- A<B
IH<= '0'; IL<='0'; IE <='1';
A<="1010";
B<="1101";
wait for 5 ns;
ASSERT (OH='0' and OL='1' and OE='0')
report "Resultado erroneo. A = " & integer'image(to_integer(unsigned(A))) & " B = " & integer'image(to_integer(unsigned(B)))
severity ERROR;
-- A>B
A<="1110";
B<="1101";
wait for 5 ns;
ASSERT (OH='1' and OL='0' and OE='0')
report "Resultado erroneo. A = " & integer'image(to_integer(unsigned(A))) & " B = " & integer'image(to_integer(unsigned(B)))
severity ERROR;
-- A=B, tenemos que mirar IH, IL, IE
A<="1101";
B<="1101";
for ihle in 0 to 7 loop
IH <= std_logic(to_unsigned(ihle,3)(2));
IL <= std_logic(to_unsigned(ihle,3)(1));
IE <= std_logic(to_unsigned(ihle,3)(0));
wait for 5 ns;
case ihle is
when 0 => assert (OH='1' and OL='1' and OE='0')
report "Resultado erroneo. A = " & integer'image(to_integer(unsigned(A))) & " B = " & integer'image(to_integer(unsigned(B)))
severity ERROR;
when 1 => assert (OH='0' and OL='0' and OE='1')
report "Resultado erroneo. A = " & integer'image(to_integer(unsigned(A))) & " B = " & integer'image(to_integer(unsigned(B)))
severity ERROR;
when 2 => assert (OH='0' and OL='1' and OE='0')
report "Resultado erroneo. A = " & integer'image(to_integer(unsigned(A))) & " B = " & integer'image(to_integer(unsigned(B)))
severity ERROR;
when 3 => assert (OH='0' and OL='0' and OE='1')
report "Resultado erroneo. A = " & integer'image(to_integer(unsigned(A))) & " B = " & integer'image(to_integer(unsigned(B)))
severity ERROR;
when 4 => assert (OH='1' and OL='0' and OE='0')
report "Resultado erroneo. A = " & integer'image(to_integer(unsigned(A))) & " B = " & integer'image(to_integer(unsigned(B)))
severity ERROR;
when 5 => assert (OH='0' and OL='0' and OE='1')
report "Resultado erroneo. A = " & integer'image(to_integer(unsigned(A))) & " B = " & integer'image(to_integer(unsigned(B)))
severity ERROR;
when 6 => assert (OH='0' and OL='0' and OE='0')
report "Resultado erroneo. A = " & integer'image(to_integer(unsigned(A))) & " B = " & integer'image(to_integer(unsigned(B)))
severity ERROR;
when 7 => assert (OH='0' and OL='0' and OE='1')
report "Resultado erroneo. A = " & integer'image(to_integer(unsigned(A))) & " B = " & integer'image(to_integer(unsigned(B)))
severity ERROR;
end case;
end loop;
-- for an in 0 to 15 loop
-- for bn in 0 to 15 loop
-- for ihle in 0 to 7 loop
-- IH <= std_logic(to_unsigned(ihle,3)(2));
-- IL <= std_logic(to_unsigned(ihle,3)(1));
-- IE <= std_logic(to_unsigned(ihle,3)(0));
-- A <= std_logic_vector(to_unsigned(an,4));
-- B <= std_logic_vector(to_unsigned(bn,4));
-- wait for 5 ns;
-- end loop;
-- end loop;
-- end loop;
wait;
end process;
END;
| gpl-2.0 | 96d357afc7f55141f171dbb5b5c923b2 | 0.564223 | 3.048272 | false | false | false | false |
cfelton/rhea | rhea/cores/usbext/fpgalink/pck_myhdl_08.vhd | 3 | 3,359 | -- File: pck_myhdl_08.vhd
-- Generated by MyHDL 0.8dev
-- Date: Fri Jan 4 21:24:43 2013
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package pck_myhdl_08 is
attribute enum_encoding: string;
function stdl (arg: boolean) return std_logic;
function stdl (arg: integer) return std_logic;
function to_unsigned (arg: boolean; size: natural) return unsigned;
function to_signed (arg: boolean; size: natural) return signed;
function to_integer(arg: boolean) return integer;
function to_integer(arg: std_logic) return integer;
function to_unsigned (arg: std_logic; size: natural) return unsigned;
function to_signed (arg: std_logic; size: natural) return signed;
function bool (arg: std_logic) return boolean;
function bool (arg: unsigned) return boolean;
function bool (arg: signed) return boolean;
function bool (arg: integer) return boolean;
function "-" (arg: unsigned) return signed;
end pck_myhdl_08;
package body pck_myhdl_08 is
function stdl (arg: boolean) return std_logic is
begin
if arg then
return '1';
else
return '0';
end if;
end function stdl;
function stdl (arg: integer) return std_logic is
begin
if arg /= 0 then
return '1';
else
return '0';
end if;
end function stdl;
function to_unsigned (arg: boolean; size: natural) return unsigned is
variable res: unsigned(size-1 downto 0) := (others => '0');
begin
if arg then
res(0):= '1';
end if;
return res;
end function to_unsigned;
function to_signed (arg: boolean; size: natural) return signed is
variable res: signed(size-1 downto 0) := (others => '0');
begin
if arg then
res(0) := '1';
end if;
return res;
end function to_signed;
function to_integer(arg: boolean) return integer is
begin
if arg then
return 1;
else
return 0;
end if;
end function to_integer;
function to_integer(arg: std_logic) return integer is
begin
if arg = '1' then
return 1;
else
return 0;
end if;
end function to_integer;
function to_unsigned (arg: std_logic; size: natural) return unsigned is
variable res: unsigned(size-1 downto 0) := (others => '0');
begin
res(0):= arg;
return res;
end function to_unsigned;
function to_signed (arg: std_logic; size: natural) return signed is
variable res: signed(size-1 downto 0) := (others => '0');
begin
res(0) := arg;
return res;
end function to_signed;
function bool (arg: std_logic) return boolean is
begin
return arg = '1';
end function bool;
function bool (arg: unsigned) return boolean is
begin
return arg /= 0;
end function bool;
function bool (arg: signed) return boolean is
begin
return arg /= 0;
end function bool;
function bool (arg: integer) return boolean is
begin
return arg /= 0;
end function bool;
function "-" (arg: unsigned) return signed is
begin
return - signed(resize(arg, arg'length+1));
end function "-";
end pck_myhdl_08;
| mit | df9cdf35c85ddd1de5c50ae90be50284 | 0.600774 | 4.017943 | false | false | false | false |
pmh92/Proyecto-OFDM | test/ESTIMADOR_tb.vhd | 1 | 2,114 | --------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 12:54:37 07/02/2015
-- Design Name:
-- Module Name: /home/pmorales/VHDL/OFDM/test/ESTIMADOR_tb.vhd
-- Project Name: OFDM
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: ESTIMADOR
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY ESTIMADOR_tb IS
END ESTIMADOR_tb;
ARCHITECTURE behavior OF ESTIMADOR_tb IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT ESTIMADOR
PORT(
clk : IN std_logic;
rst : IN std_logic;
start : IN std_logic;
fin : OUT std_logic
);
END COMPONENT;
--Inputs
signal clk : std_logic := '0';
signal rst : std_logic := '0';
signal start : std_logic := '0';
-- Clock period definitions
constant clk_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: ESTIMADOR PORT MAP (
clk => clk,
rst => rst,
start => start
);
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
rst <= '1';
wait for 100 ns;
rst <= '0';
-- insert stimulus here
wait until rising_edge(clk);
start <= '1';
wait for clk_period;
start <= '0';
wait;
end process;
END;
| gpl-2.0 | ebeec2cc8695308080288b4ce85752d1 | 0.573794 | 3.775 | false | true | false | false |
emogenet/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc2391.vhd | 4 | 2,161 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2391.vhd,v 1.2 2001-10-26 16:29:47 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s03b02x00p07n01i02391ent IS
END c07s03b02x00p07n01i02391ent;
ARCHITECTURE c07s03b02x00p07n01i02391arch OF c07s03b02x00p07n01i02391ent IS
type ARRAY_TYPE is array (INTEGER range <>) of BOOLEAN;
type RECORD_TYPE is record
E1,E2,E3,E4,E5 : BOOLEAN;
end record;
signal S3 : ARRAY_TYPE(1 to 5);
BEGIN
TESTING: PROCESS
BEGIN
S3 <= ( 5 => TRUE, 4|2 downto 1 => TRUE, 3 => TRUE);
-- named associations may appear in any order.
wait for 1 ns;
assert NOT(S3(1)=TRUE and S3(2)=TRUE and S3(3)=TRUE and S3(4)=TRUE and S3(5)=TRUE)
report "***PASSED TEST: c07s03b02x00p07n01i02391"
severity NOTE;
assert (S3(1)=TRUE and S3(2)=TRUE and S3(3)=TRUE and S3(4)=TRUE and S3(5)=TRUE)
report "***FAILED TEST: c07s03b02x00p07n01i02391 - Both named and positional associations can be used in the same aggregate."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s03b02x00p07n01i02391arch;
| gpl-2.0 | 6bae954bcd10b739ba0d24bb1efe5ffa | 0.656178 | 3.519544 | false | true | false | false |
emogenet/ghdl | testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS2_Mixed_Tech/stop_r.vhd | 3 | 1,732 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
library ieee_proposed; use ieee_proposed.mechanical_systems.all;
entity stop_r is
generic ( k_stop : real := 1.0e6;
ang_max : real := 1.05;
ang_min : real := -1.05;
damp_stop : real := 1.0e2 );
port ( terminal ang1, ang2 : rotational );
end entity stop_r;
----------------------------------------------------------------
architecture ideal of stop_r is
quantity velocity : velocity;
quantity ang across trq through ang1 to ang2;
begin
velocity == ang'dot;
if ang > ang_max use -- Hit upper stop, generate opposing torque
trq == k_stop * (ang - ang_max) + (damp_stop * velocity);
elsif ang > ang_min use -- Between stops, no opposing torque
trq == 0.0;
else -- Hit lower stop, generate opposing torque
trq == k_stop * (ang - ang_min) + (damp_stop * velocity);
end use;
break on ang'above(ang_min), ang'above(ang_max);
end architecture ideal;
| gpl-2.0 | b67d74960d4a4d0bf205f21ffbb3dd60 | 0.654157 | 3.866071 | false | false | false | false |
emogenet/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2419.vhd | 4 | 1,988 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2419.vhd,v 1.2 2001-10-26 16:30:18 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
package c07s03b02x00p10n01i02419pkg is
type byte is range 0 to 15;
type cmd_bus is array (0 to 3) of byte;
end c07s03b02x00p10n01i02419pkg;
use work.c07s03b02x00p10n01i02419pkg.all;
ENTITY c07s03b02x00p10n01i02419ent IS
port ( signal b_inp : in boolean := cmd_bus'(0 to 3 => 0) = (0 to 3 => 1));
END c07s03b02x00p10n01i02419ent;
ARCHITECTURE c07s03b02x00p10n01i02419arch OF c07s03b02x00p10n01i02419ent IS
signal b_sig : boolean := cmd_bus'(0 to 3 => 0) = (0 to 3 => 1);
BEGIN
TESTING: PROCESS
BEGIN
b_sig <= (0 to 3 => 0) = (0 to 3 => 1);
wait for 5 ns;
assert FALSE
report "***FAILED TEST: c07s03b02x00p10n01i02419 - The type of the aggregate is not determinable from the context."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s03b02x00p10n01i02419arch;
| gpl-2.0 | a77c243291e2970cc1155c1984adeaac | 0.665996 | 3.369492 | false | true | false | false |
pmh92/Proyecto-OFDM | src/PRBS.vhd | 1 | 1,249 | ----------------------------------------------------------------------------------
-- Company: US
-- Engineer: Pedro Morales Hernandez
--
-- Create Date: 19:32:08 06/07/2015
-- Design Name:
-- Module Name: PRBS - Behavioral
-- Project Name: OFDM
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity PRBS is
Port ( clk : in STD_LOGIC;
rst : in STD_LOGIC;
enable : in STD_LOGIC;
output : out STD_LOGIC);
end PRBS;
architecture Behavioral of PRBS is
signal registro : STD_LOGIC_VECTOR(10 DOWNTO 0);
signal p_registro : STD_LOGIC_VECTOR(10 DOWNTO 0);
begin
comb: process (registro, enable)
begin
if(enable = '1') then
p_registro(10 DOWNTO 1) <= registro(9 DOWNTO 0);
p_registro(0) <= registro(10) XOR registro(8);
else
p_registro <= registro;
end if;
end process;
output <= registro(10);
seq: process(clk,rst)
begin
if(rst = '1') then
registro <= (OTHERS => '1');
elsif(rising_edge(clk)) then
registro <= p_registro;
end if;
end process;
end Behavioral;
| gpl-2.0 | 6cbeaec3f3c3af120950244a75eeb595 | 0.565252 | 3.488827 | false | false | false | false |
rafa-jfet/OFM | ARCHIVOS VHDL/conv_enc.vhd | 1 | 3,262 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 19:18:42 04/23/2015
-- Design Name:
-- Module Name: convolutional_encoder - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
--use IEEE.STD_logic_arith.ALL;
use IEEE.std_logic_unsigned.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity convolutional_encoder is
Generic ( TAM_REG : integer := 7;
SAT_ESPERA : integer := 2);
Port ( clk : in STD_LOGIC;
reset : in STD_LOGIC;
button : in STD_LOGIC;
bit_in : in STD_LOGIC;
ok_bit_in : in STD_LOGIC;
fin_rx : in STD_LOGIC;
sat : in STD_LOGIC;
first_bit_out : out STD_LOGIC;
second_bit_out : out STD_LOGIC;
ok_bit_out : out STD_LOGIC;
fin_tx : out STD_LOGIC);
end convolutional_encoder;
architecture Behavioral of convolutional_encoder is
type estado is ( reposo,
normal,
relleno);
signal estado_actual, estado_nuevo : estado;
--signal estado_nuevo : estado;
signal reg, p_reg : STD_LOGIC_VECTOR (TAM_REG -1 downto 0);
signal cont_relleno, p_cont_relleno : integer range 0 to TAM_REG -1; --contador para ceross de relleno
signal p_ok_bit_out, p_fin_tx : STD_LOGIC;
begin
comb : process(estado_actual, reg, ok_bit_in, bit_in, cont_relleno, fin_rx, button, sat)
begin
p_reg <= reg;
p_cont_relleno <= cont_relleno;
p_ok_bit_out <= '0';
p_fin_tx <= '0';
estado_nuevo <= estado_actual;
first_bit_out <= reg(6) xor reg(5) xor reg(3) xor reg(1) xor reg(0);
second_bit_out <= reg(6) xor reg(3) xor reg(2) xor reg(0);
case estado_actual is
when reposo =>
if ( button = '1' ) then
estado_nuevo <= normal;
p_reg <= (others => '0');
end if;
when normal =>
if ( ok_bit_in = '1' ) then
p_reg(5 downto 0) <= reg(6 downto 1);
p_reg(6) <= bit_in;
p_ok_bit_out <= '1';
end if;
if ( fin_rx = '1' ) then
estado_nuevo <= relleno;
p_cont_relleno <= TAM_REG -1;
end if;
when relleno =>
if ( cont_relleno = 0 and sat = '1') then
estado_nuevo <= reposo;
p_fin_tx <= '1';
elsif ( sat = '1' ) then
p_cont_relleno <= cont_relleno -1;
p_reg(5 downto 0) <= reg(6 downto 1);
p_reg(6) <= '0';
p_ok_bit_out <= '1';
end if;
end case;
end process;
sinc : process (clk, reset)
begin
if ( reset = '1' ) then
reg <= (others => '0');
ok_bit_out <= '0';
estado_actual <= reposo;
cont_relleno <= TAM_REG -1;
elsif ( rising_edge(clk) ) then
cont_relleno <= p_cont_relleno;
reg <= p_reg;
fin_tx <= p_fin_tx;
ok_bit_out <= p_ok_bit_out;
estado_actual <= estado_nuevo;
end if;
end process;
end Behavioral;
| gpl-3.0 | 0a7dad2cf6ca72eac34a4ebd86a87c7f | 0.573574 | 2.920322 | false | false | false | false |
pmh92/Proyecto-OFDM | ipcore_dir/SPRAM_12.vhd | 1 | 5,608 | --------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used solely --
-- for design, simulation, implementation and creation of design files --
-- limited to Xilinx devices or technologies. Use with non-Xilinx --
-- devices or technologies is expressly prohibited and immediately --
-- terminates your license. --
-- --
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY --
-- FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY --
-- PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE --
-- IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS --
-- MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY --
-- CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY --
-- RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY --
-- DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A --
-- PARTICULAR PURPOSE. --
-- --
-- Xilinx products are not intended for use in life support appliances, --
-- devices, or systems. Use in such applications are expressly --
-- prohibited. --
-- --
-- (c) Copyright 1995-2015 Xilinx, Inc. --
-- All rights reserved. --
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- You must compile the wrapper file SPRAM_12.vhd when simulating
-- the core, SPRAM_12. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Help".
-- The synthesis directives "translate_off/translate_on" specified
-- below are supported by Xilinx, Mentor Graphics and Synplicity
-- synthesis tools. Ensure they are correct for your synthesis tool(s).
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- synthesis translate_off
LIBRARY XilinxCoreLib;
-- synthesis translate_on
ENTITY SPRAM_12 IS
PORT (
clka : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(10 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(23 DOWNTO 0)
);
END SPRAM_12;
ARCHITECTURE SPRAM_12_a OF SPRAM_12 IS
-- synthesis translate_off
COMPONENT wrapped_SPRAM_12
PORT (
clka : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(10 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(23 DOWNTO 0)
);
END COMPONENT;
-- Configuration specification
FOR ALL : wrapped_SPRAM_12 USE ENTITY XilinxCoreLib.blk_mem_gen_v7_3(behavioral)
GENERIC MAP (
c_addra_width => 11,
c_addrb_width => 11,
c_algorithm => 1,
c_axi_id_width => 4,
c_axi_slave_type => 0,
c_axi_type => 1,
c_byte_size => 9,
c_common_clk => 0,
c_default_data => "0",
c_disable_warn_bhv_coll => 0,
c_disable_warn_bhv_range => 0,
c_enable_32bit_address => 0,
c_family => "spartan6",
c_has_axi_id => 0,
c_has_ena => 0,
c_has_enb => 0,
c_has_injecterr => 0,
c_has_mem_output_regs_a => 0,
c_has_mem_output_regs_b => 0,
c_has_mux_output_regs_a => 0,
c_has_mux_output_regs_b => 0,
c_has_regcea => 0,
c_has_regceb => 0,
c_has_rsta => 0,
c_has_rstb => 0,
c_has_softecc_input_regs_a => 0,
c_has_softecc_output_regs_b => 0,
c_init_file => "BlankString",
c_init_file_name => "no_coe_file_loaded",
c_inita_val => "0",
c_initb_val => "0",
c_interface_type => 0,
c_load_init_file => 0,
c_mem_type => 0,
c_mux_pipeline_stages => 0,
c_prim_type => 1,
c_read_depth_a => 2048,
c_read_depth_b => 2048,
c_read_width_a => 24,
c_read_width_b => 24,
c_rst_priority_a => "CE",
c_rst_priority_b => "CE",
c_rst_type => "SYNC",
c_rstram_a => 0,
c_rstram_b => 0,
c_sim_collision_check => "ALL",
c_use_bram_block => 0,
c_use_byte_wea => 0,
c_use_byte_web => 0,
c_use_default_data => 0,
c_use_ecc => 0,
c_use_softecc => 0,
c_wea_width => 1,
c_web_width => 1,
c_write_depth_a => 2048,
c_write_depth_b => 2048,
c_write_mode_a => "WRITE_FIRST",
c_write_mode_b => "WRITE_FIRST",
c_write_width_a => 24,
c_write_width_b => 24,
c_xdevicefamily => "spartan6"
);
-- synthesis translate_on
BEGIN
-- synthesis translate_off
U0 : wrapped_SPRAM_12
PORT MAP (
clka => clka,
wea => wea,
addra => addra,
dina => dina,
douta => douta
);
-- synthesis translate_on
END SPRAM_12_a;
| gpl-2.0 | 5d2cb1b5d3565e4d220c4e54f02fba6b | 0.53174 | 3.943741 | false | false | false | false |
emogenet/ghdl | testsuite/vests/vhdl-ams/ashenden/compliant/composite-data/modem_controller.vhd | 4 | 2,593 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
entity modem_controller is
end entity modem_controller;
----------------------------------------------------------------
architecture test of modem_controller is
begin
-- code from book:
modem_controller : process is
type symbol is ('a', 't', 'd', 'h', digit, cr, other);
type symbol_string is array (1 to 20) of symbol;
type state is range 0 to 6;
type transition_matrix is array (state, symbol) of state;
constant next_state : transition_matrix :=
( 0 => ('a' => 1, others => 6),
1 => ('t' => 2, others => 6),
2 => ('d' => 3, 'h' => 5, others => 6),
3 => (digit => 4, others => 6),
4 => (digit => 4, cr => 0, others => 6),
5 => (cr => 0, others => 6),
6 => (cr => 0, others => 6) );
variable command : symbol_string;
variable current_state : state := 0;
-- not in book:
type sample_array is array (positive range <>) of symbol_string;
constant sample_command : sample_array :=
( 1 => ( 'a', 't', 'd', digit, digit, cr, others => other ),
2 => ( 'a', 't', 'h', cr, others => other ),
3 => ( 'a', 't', other, other, cr, others => other ) );
-- end not in book
begin
-- . . .
-- not in book:
for command_index in sample_command'range loop
command := sample_command(command_index);
-- end not in book
for index in 1 to 20 loop
current_state := next_state( current_state, command(index) );
case current_state is
-- . . .
-- not in book:
when 0 => exit;
when others => null;
-- end not in book
end case;
end loop;
-- . . .
-- not in book:
end loop;
wait;
-- end not in book
end process modem_controller;
-- end of code from book
end architecture test;
| gpl-2.0 | a23f4717e28236445ff869f37be26085 | 0.584651 | 3.858631 | false | false | false | false |
hacklabmikkeli/rough-boy | voice_generator.vhdl | 2 | 4,943 | --
-- Knobs Galore - a free phase distortion synthesizer
-- Copyright (C) 2015 Ilmo Euro
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.common.all;
entity voice_generator is
port (EN: in std_logic
;CLK_EVEN: in std_logic
;CLK_ODD: in std_logic
;FREQ: in time_signal
;GATE: in std_logic
;PARAMS: in synthesis_params
;AUDIO_OUT: out voice_signal
;OUT_TO_FIFO: out state_vector_t
;IN_FROM_FIFO: in state_vector_t
);
end entity;
architecture voice_generator_impl of voice_generator is
signal s1_freq: time_signal := (others=>'0');
signal s1_cutoff: time_signal;
signal s1_cutoff_stage: adsr_stage;
signal s1_cutoff_prev_gate: std_logic;
signal s1_gain: time_signal;
signal s1_gain_stage: adsr_stage;
signal s1_gain_prev_gate: std_logic;
signal s1_phase: time_signal;
signal s4_wf: waveform_t;
signal s4_cutoff: ctl_signal;
signal s4_theta: ctl_signal;
signal s4_gain: ctl_signal;
signal s8_theta: ctl_signal;
signal s8_gain: ctl_signal;
signal s9_z: voice_signal;
signal s9_gain: ctl_signal;
signal s12_z_ampl: voice_signal;
begin
process(CLK_EVEN)
begin
if EN='1' and rising_edge(CLK_EVEN) then
s1_freq <= FREQ;
end if;
end process;
phase_gen:
entity
work.phase_gen (phase_gen_impl)
port map
('1'
,CLK_EVEN
,IN_FROM_FIFO.sv_phase
,s1_phase
);
env_gen_cutoff:
entity
work.env_gen (env_gen_impl)
port map
('1'
,CLK_EVEN
,GATE
,PARAMS.sp_cutoff_base
,PARAMS.sp_cutoff_env
,PARAMS.sp_cutoff_attack
,PARAMS.sp_cutoff_decay
,PARAMS.sp_cutoff_sustain
,PARAMS.sp_cutoff_rel
,IN_FROM_FIFO.sv_cutoff
,s1_cutoff
,IN_FROM_FIFO.sv_cutoff_stage
,s1_cutoff_stage
,IN_FROM_FIFO.sv_cutoff_prev_gate
,s1_cutoff_prev_gate
);
env_gen_gain:
entity
work.env_gen (env_gen_impl)
port map
('1'
,CLK_EVEN
,GATE
,x"00"
,x"FF"
,PARAMS.sp_gain_attack
,PARAMS.sp_gain_decay
,PARAMS.sp_gain_sustain
,PARAMS.sp_gain_rel
,IN_FROM_FIFO.sv_gain
,s1_gain
,IN_FROM_FIFO.sv_gain_stage
,s1_gain_stage
,IN_FROM_FIFO.sv_gain_prev_gate
,s1_gain_prev_gate
);
voice_controller:
entity
work.voice_controller (voice_controller_impl)
port map
('1'
,CLK_ODD
,CLK_EVEN
,PARAMS.sp_mode
,s1_freq
,s1_cutoff
,s4_cutoff
,s1_gain
,s4_gain
,s1_phase
,s4_theta
,s4_wf
);
phase_distort:
entity
work.phase_distort (phase_distort_impl)
port map
('1'
,CLK_EVEN
,CLK_ODD
,s4_wf
,s4_cutoff
,s4_theta
,s8_theta
,s4_gain
,s8_gain
);
waveshaper:
entity
work.waveshaper(waveshaper_sin)
port map
('1'
,CLK_ODD
,s8_theta
,s9_z
,s8_gain
,s9_gain
);
amplifier:
entity
work.amplifier (amplifier_impl)
port map
('1'
,CLK_EVEN
,CLK_ODD
,s9_gain
,s9_z
,s12_z_ampl
);
AUDIO_OUT <= s12_z_ampl;
OUT_TO_FIFO <=
(s1_phase
,s1_gain
,s1_gain_stage
,s1_gain_prev_gate
,s1_cutoff
,s1_cutoff_stage
,s1_cutoff_prev_gate
);
end architecture;
| gpl-3.0 | 4d104055523169bf39be079745819fb4 | 0.49565 | 3.719338 | false | false | false | false |
emogenet/ghdl | testsuite/vests/vhdl-93/ashenden/compliant/ch_14_fg_14_09.vhd | 4 | 5,324 |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_14_fg_14_09.vhd,v 1.2 2001-10-26 16:29:35 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
package bus_monitor_pkg is
type stats_type is record
ifetch_freq, write_freq, read_freq : real;
end record stats_type;
component bus_monitor is
generic ( verbose, dump_stats : boolean := false );
port ( mem_req, ifetch, write : in bit;
bus_stats : out stats_type );
end component bus_monitor;
end package bus_monitor_pkg;
use work.bus_monitor_pkg.all;
entity bus_monitor is
generic ( verbose, dump_stats : boolean := false );
port ( mem_req, ifetch, write : in bit;
bus_stats : out stats_type );
end entity bus_monitor;
architecture general_purpose of bus_monitor is
begin
access_monitor : process is
variable access_count, ifetch_count,
write_count, read_count : natural := 0;
use std.textio;
variable L : textio.line;
begin
wait until mem_req = '1';
if ifetch = '1' then
ifetch_count := ifetch_count + 1;
if verbose then
textio.write(L, string'("Ifetch"));
textio.writeline(textio.output, L);
end if;
elsif write = '1' then
write_count := write_count + 1;
if verbose then
textio.write(L, string'("Write"));
textio.writeline(textio.output, L);
end if;
else
read_count := read_count + 1;
if verbose then
textio.write(L, string'("Read"));
textio.writeline(textio.output, L);
end if;
end if;
access_count := access_count + 1;
bus_stats.ifetch_freq <= real(ifetch_count) / real(access_count);
bus_stats.write_freq <= real(write_count) / real(access_count);
bus_stats.read_freq <= real(read_count) / real(access_count);
if dump_stats and access_count mod 5 = 0 then
textio.write(L, string'("Ifetch frequency = "));
textio.write(L, real(ifetch_count) / real(access_count));
textio.writeline(textio.output, L);
textio.write(L, string'("Write frequency = "));
textio.write(L, real(write_count) / real(access_count));
textio.writeline(textio.output, L);
textio.write(L, string'("Read frequency = "));
textio.write(L, real(read_count) / real(access_count));
textio.writeline(textio.output, L);
end if;
end process access_monitor;
end architecture general_purpose;
-- code from book
architecture block_level of computer_system is
-- . . . -- type and component declarations for cpu and memory, etc.
signal clock : bit; -- the system clock
signal mem_req : bit; -- cpu access request to memory
signal ifetch : bit; -- indicates access is to fetch an instruction
signal write : bit; -- indicates access is a write
-- . . . -- other signal declarations
begin
-- . . . -- component instances for cpu and memory, etc.
instrumentation : if instrumented generate
use work.bus_monitor_pkg;
signal bus_stats : bus_monitor_pkg.stats_type;
begin
cpu_bus_monitor : component bus_monitor_pkg.bus_monitor
port map ( mem_req, ifetch, write, bus_stats );
end generate instrumentation;
-- not in book
stimulus : process is
begin
ifetch <= '1'; write <= '0';
mem_req <= '1', '0' after 10 ns;
wait for 20 ns;
mem_req <= '1', '0' after 10 ns;
ifetch <= '1'; write <= '0';
wait for 20 ns;
mem_req <= '1', '0' after 10 ns;
ifetch <= '1'; write <= '0';
wait for 20 ns;
mem_req <= '1', '0' after 10 ns;
ifetch <= '0'; write <= '1';
wait for 20 ns;
mem_req <= '1', '0' after 10 ns;
ifetch <= '1'; write <= '0';
wait for 20 ns;
mem_req <= '1', '0' after 10 ns;
ifetch <= '0'; write <= '0';
wait for 20 ns;
mem_req <= '1', '0' after 10 ns;
ifetch <= '1'; write <= '0';
wait for 20 ns;
mem_req <= '1', '0' after 10 ns;
ifetch <= '0'; write <= '0';
wait for 20 ns;
mem_req <= '1', '0' after 10 ns;
ifetch <= '1'; write <= '0';
wait for 20 ns;
mem_req <= '1', '0' after 10 ns;
ifetch <= '0'; write <= '0';
wait for 20 ns;
wait;
end process stimulus;
-- end not in book
end architecture block_level;
-- end code from book
| gpl-2.0 | 402fe8d0056e138fea4ef2e35a89249f | 0.580579 | 3.749296 | false | false | false | false |
emogenet/ghdl | testsuite/vests/vhdl-93/ashenden/compliant/ch_06_tovect-b.vhd | 4 | 1,850 |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_06_tovect-b.vhd,v 1.2 2001-10-26 16:29:34 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
library ieee; use ieee.std_logic_1164.all;
architecture bench of to_vector_test is
signal vec : std_ulogic_vector(15 downto 0);
signal r : real := 0.0;
begin
dut : entity work.to_vector(behavioral)
port map (r, vec);
stimulus : process is
begin
r <= 0.0; wait for 10 ns;
r <= -1.0; wait for 10 ns;
r <= -2.0; wait for 10 ns;
r <= +0.9999; wait for 10 ns;
r <= +2.0; wait for 10 ns;
r <= -0.5; wait for 10 ns;
r <= +0.5; wait for 10 ns;
wait;
end process stimulus;
end architecture bench;
| gpl-2.0 | 2839cfac9a185e58982e001d812dc342 | 0.521081 | 4.252874 | false | false | false | false |
pmh92/Proyecto-OFDM | src/ECUALIZADOR.vhd | 1 | 5,936 | ---------------------------------------
-- 8/JUL/2015 - Pedro Morales Hernandez
-- Modulo del Ecualizador
---------------------------------------
-- Importacion de librerias
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity ECUALIZADOR is
Port ( clk : in STD_LOGIC;
rst : in STD_LOGIC;
start : in STD_LOGIC;
fin : out STD_LOGIC;
y_data : in STD_LOGIC_VECTOR (19 downto 0);
h_data : in STD_LOGIC_VECTOR (23 downto 0);
y_est_data : out STD_LOGIC_VECTOR (23 downto 0);
y_addr : out STD_LOGIC_VECTOR (10 downto 0);
h_addr : out STD_LOGIC_VECTOR (10 downto 0);
y_est_addr : out STD_LOGIC_VECTOR (10 downto 0);
write_y_est : out STD_LOGIC_VECTOR (0 DOWNTO 0));
end ECUALIZADOR;
architecture Behavioral of ECUALIZADOR is
SUBTYPE addr IS STD_LOGIC_VECTOR(10 DOWNTO 0); -- Por si es necesario redefinir el tamao de las direcciones
-- Submodulos
component DIVIDER
port (
clk: in std_logic;
rfd: out std_logic;
dividend: in std_logic_vector(23 downto 0);
divisor: in std_logic_vector(23 downto 0);
quotient: out std_logic_vector(23 downto 0);
fractional: out std_logic_vector(23 downto 0));
end component;
TYPE complex12 IS RECORD -- De 12 bits
re: SIGNED(11 DOWNTO 0);
im: SIGNED(11 DOWNTO 0);
END RECORD;
TYPE complex36 IS RECORD -- De 12 bits
re: SIGNED(35 DOWNTO 0);
im: SIGNED(35 DOWNTO 0);
END RECORD;
TYPE complex10 IS RECORD -- De 10 bits
re: SIGNED(9 DOWNTO 0);
im: SIGNED(9 DOWNTO 0);
END RECORD;
TYPE complex22 IS RECORD -- De 10 bits
re: SIGNED(21 DOWNTO 0);
im: SIGNED(21 DOWNTO 0);
END RECORD;
FUNCTION MODULO(input : STD_LOGIC_VECTOR(23 DOWNTO 0)) RETURN UNSIGNED IS
VARIABLE valor : complex12;
BEGIN
valor.re := SIGNED(input(23 DOWNTO 12));
valor.im := SIGNED(input(11 DOWNTO 0));
RETURN UNSIGNED(valor.re*valor.re+valor.im*valor.im);
END MODULO;
FUNCTION SAT_Q_36(input : complex36) RETURN complex12 IS
VARIABLE res : complex12;
BEGIN
IF(SIGNED(input.re) > 2047) THEN
res.re := TO_SIGNED(2047,12);
ELSIF(SIGNED(input.re) < -2048) THEN
res.re := TO_SIGNED(-2048,12);
ELSE
res.re := input.re(11 DOWNTO 0);
END IF;
IF(SIGNED(input.im) > 2047) THEN
res.im := TO_SIGNED(2047,12);
ELSIF(SIGNED(input.im) < -2048) THEN
res.im := TO_SIGNED(-2048,12);
ELSE
res.im := input.im(11 DOWNTO 0);
END IF;
RETURN res;
END SAT_Q_36;
FUNCTION SAT_Q_22(input : complex22) RETURN complex12 IS
VARIABLE res : complex12;
BEGIN
IF(SIGNED(input.re) > 2047) THEN
res.re := TO_SIGNED(2047,12);
ELSIF(SIGNED(input.re) < -2048) THEN
res.re := TO_SIGNED(-2048,12);
ELSE
res.re := input.re(11 DOWNTO 0);
END IF;
IF(SIGNED(input.im) > 2047) THEN
res.im := TO_SIGNED(2047,12);
ELSIF(SIGNED(input.im) < -2048) THEN
res.im := TO_SIGNED(-2048,12);
ELSE
res.im := input.im(11 DOWNTO 0);
END IF;
RETURN res;
END SAT_Q_22;
TYPE estados IS (reposo,espera,procesa,terminado);
TYPE context_t IS RECORD
h_dir : addr; -- Direccion H (Estimacion)
y_dir : addr; -- Direccion Y (Simbolo)
y_est_dir : addr; -- Direccion Y estimado
cuenta : INTEGER;
END RECORD;
SIGNAL rfd : STD_LOGIC;
SIGNAL resto : STD_LOGIC_VECTOR(23 downto 0);
SIGNAL inverso : complex36;
SIGNAL conj : complex12;
SIGNAL estado,p_estado : estados;
SIGNAL context, p_context : context_t;
SIGNAL h_leido : complex12;
SIGNAL cociente : STD_LOGIC_VECTOR(23 DOWNTO 0);
SIGNAL y : complex10;
SIGNAL y_sat,y_est_sat : complex12;
SIGNAL y_est : complex22;
BEGIN
-- Conexiones de senales
y_addr <= context.y_dir;
h_addr <= context.h_dir;
y_est_addr <= context.y_est_dir;
inverso.re <= conj.re*SIGNED(cociente);
inverso.im <= conj.im*SIGNED(cociente);
y.re <= SIGNED(y_data(19 DOWNTO 10));
y.im <= SIGNED(y_data(9 DOWNTO 0));
y_sat <= SAT_Q_36(inverso);
y_est.re <= y.re*y_sat.re;
y_est.im <= y.im*y_sat.im;
y_est_sat <= SAT_Q_22(y_est);
y_est_data(23 DOWNTO 12) <= STD_LOGIC_VECTOR(y_est_sat.re);
y_est_data(11 DOWNTO 0) <= STD_LOGIC_VECTOR(y_est_sat.im);
-- Modelos Instanciados
div : DIVIDER
port map (
clk => clk,
rfd => rfd,
dividend => (OTHERS => '1'), -- El mayor valor posible
divisor => STD_LOGIC_VECTOR(MODULO(h_data)),
quotient => cociente,
fractional => resto);
h_leido.re <= SIGNED(h_data(23 DOWNTO 12));
h_leido.im <= SIGNED(h_data(11 DOWNTO 0));
conj.re <= SIGNED(h_data(23 DOWNTO 12));
conj.im <= -SIGNED(h_data(11 DOWNTO 0));
-- Proceso Combinacional
comb : PROCESS(start,estado,context)
BEGIN
-- Valores por defecto en todos los estados
p_context <= context;
write_y_est <= "0";
fin <= '0';
CASE estado IS
WHEN reposo =>
p_context.cuenta <= 0;
p_context.y_dir <= (OTHERS => '0');
p_context.y_est_dir <= (OTHERS => '0');
IF(start = '1') THEN
p_context.h_dir <= "00000000001";
p_estado <= espera;
ELSE
p_context.h_dir <= (OTHERS => '0');
p_estado <= reposo;
END IF;
WHEN espera =>
p_context.cuenta <= context.cuenta+1;
p_context.h_dir <= STD_LOGIC_VECTOR(UNSIGNED(context.h_dir)+1);
IF(context.cuenta = 20) THEN
p_estado <= procesa;
p_context.y_dir <= "00000000001";
ELSE
p_estado <= espera;
END IF;
WHEN procesa =>
write_y_est <= "1";
p_context.h_dir <= STD_LOGIC_VECTOR(UNSIGNED(context.h_dir)+1);
p_context.y_dir <= STD_LOGIC_VECTOR(UNSIGNED(context.y_dir)+1);
p_context.y_est_dir <= STD_LOGIC_VECTOR(UNSIGNED(context.y_est_dir)+1);
IF(context.y_dir = STD_LOGIC_VECTOR(TO_UNSIGNED(1704,11))) THEN
p_estado <= terminado;
ELSE
p_estado <= procesa;
END IF;
WHEN terminado =>
fin <= '1';
p_estado <= reposo;
END CASE;
END PROCESS;
-- Proceso sincrono
sinc : PROCESS(clk,rst)
BEGIN
IF(rst = '1') THEN
context.y_dir <= (OTHERS => '0');
context.h_dir <= (OTHERS => '0');
context.y_est_dir <= (OTHERS => '0');
estado <= reposo; -- Reset asincrono
ELSIF(rising_edge(clk)) THEN
estado <= p_estado;
context <= p_context;
END IF;
END PROCESS;
end Behavioral;
| gpl-2.0 | 6208f117d048dce79d64d580141b49dc | 0.64909 | 2.789474 | false | false | false | false |
hacklabmikkeli/rough-boy | input_buffer.vhdl | 2 | 4,785 | --
-- Knobs Galore - a free phase distortion synthesizer
-- Copyright (C) 2015 Ilmo Euro
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.common.all;
entity input_buffer is
port (EN: in std_logic
;CLK: in std_logic
;KEYS_IN: in std_logic_vector(7 downto 0)
;KEYS_PROBE: out std_logic_vector(4 downto 0)
;KEY_CODE: out keys_signal
;KEY_EVENT: out key_event_t
;READY: out std_logic
);
end entity;
architecture input_buffer_impl of input_buffer is
signal keys_buf: std_logic_vector(63 downto 0) := (others => '0');
signal keys_mask: std_logic_vector(7 downto 0) := (others => '0');
signal probe_clock: unsigned(5 downto 0) := (others => '0');
signal keys_probe_buf: std_logic_vector(4 downto 0) := (others => 'Z');
signal key_code_buf: keys_signal := (others => '0');
signal key_event_buf: key_event_t := (others => '0');
signal key_code_translated: keys_signal;
signal counter: unsigned(7 downto 0);
begin
process(CLK)
variable old_key_state: std_logic;
variable new_key_state: std_logic;
begin
if EN = '1' and rising_edge(CLK) then
if counter = "00000000" then
case probe_clock(2 downto 0) is
when "000"=>
keys_mask <= "10000000";
when "001"=>
keys_mask <= "01000000";
when "010"=>
keys_mask <= "00100000";
when "011"=>
keys_mask <= "00010000";
when "100"=>
keys_mask <= "00001000";
when "101"=>
keys_mask <= "00000100";
when "110"=>
keys_mask <= "00000010";
when "111"=>
keys_mask <= "00000001";
when others =>
null;
end case;
case probe_clock(5 downto 3) is
when "000" =>
keys_probe_buf <= "1ZZZZ";
when "001" =>
keys_probe_buf <= "Z1ZZZ";
when "010" =>
keys_probe_buf <= "ZZ1ZZ";
when "011" =>
keys_probe_buf <= "ZZZ1Z";
when "100" =>
keys_probe_buf <= "ZZZZ1";
when others =>
keys_probe_buf <= "ZZZZZ";
end case;
key_event_buf <= key_event_idle;
elsif counter = "10000000" then
old_key_state := keys_buf(to_integer(probe_clock));
if (KEYS_IN and keys_mask) /= "00000000" then
new_key_state := '1';
else
new_key_state := '0';
end if;
if old_key_state = '0' and new_key_state = '1' then
key_event_buf <= key_event_make;
elsif old_key_state = '1' and new_key_state = '0' then
key_event_buf <= key_event_break;
else
key_event_buf <= key_event_idle;
end if;
keys_buf(to_integer(probe_clock)) <= new_key_state;
key_code_buf <= probe_clock;
if probe_clock = "100100" then
probe_clock <= "000000";
else
probe_clock <= probe_clock + 1;
end if;
elsif counter = "10000001" then
key_event_buf <= key_event_idle;
elsif counter = "10001000" then
keys_probe_buf <= "00000";
end if;
counter <= counter + 1;
end if;
end process;
KEY_CODE <= key_code_buf;
KEY_EVENT <= key_event_buf;
KEYS_PROBE <= keys_probe_buf;
READY <= '1';
end architecture;
| gpl-3.0 | a864232b05254072a7ba4f893a29794c | 0.477952 | 4.249556 | false | false | false | false |
makestuff/spi-master | vhdl/tb_suppress/spi_master_tb.vhdl | 1 | 5,405 | --
-- Copyright (C) 2011, 2013 Chris McClelland
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU Lesser General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU Lesser General Public License for more details.
--
-- You should have received a copy of the GNU Lesser General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_textio.all;
use std.textio.all;
use work.hex_util.all;
entity spi_master_tb is
end entity;
architecture behavioural of spi_master_tb is
-- Clocks, etc
signal sysClk : std_logic; -- main system clock
signal dispClk : std_logic; -- display version of sysClk, which transitions 4ns before it
signal reset : std_logic;
-- Client interface
signal sendData : std_logic_vector(7 downto 0); -- data to send
signal sendValid : std_logic;
signal sendReady : std_logic;
signal recvData : std_logic_vector(7 downto 0); -- data we receive
signal recvValid : std_logic;
signal recvReady : std_logic;
-- External interface
signal spiClk : std_logic; -- serial clock
signal spiDataOut : std_logic; -- send serial data
signal spiDataIn : std_logic; -- receive serial data
begin
-- Instantiate the unit under test
uut: entity work.spi_master
generic map(
--FAST_COUNT => "000011"
FAST_COUNT => "000000",
BIT_ORDER => '1'
)
port map(
reset_in => reset,
clk_in => sysClk,
turbo_in => '1',
suppress_in => '1',
sendData_in => sendData,
sendValid_in => sendValid,
sendReady_out => sendReady,
recvData_out => recvData,
recvValid_out => recvValid,
recvReady_in => recvReady,
spiClk_out => spiClk,
spiData_out => spiDataOut,
spiData_in => spiDataIn
);
-- Drive the clocks. In simulation, sysClk lags 4ns behind dispClk, to give a visual hold time
-- for signals in GTKWave.
process
begin
sysClk <= '0';
dispClk <= '0';
wait for 16 ns;
loop
dispClk <= not(dispClk); -- first dispClk transitions
wait for 4 ns;
sysClk <= not(sysClk); -- then sysClk transitions, 4ns later
wait for 6 ns;
end loop;
end process;
-- Deassert the synchronous reset a couple of cycles after startup.
--
process
begin
reset <= '1';
wait until rising_edge(sysClk);
wait until rising_edge(sysClk);
reset <= '0';
wait;
end process;
-- Drive the unit under test. Read stimulus from stimulus.sim and write results to results.sim
process
variable inLine : line;
variable outLine : line;
file inFile : text open read_mode is "stimulus/send.sim";
file outFile : text open write_mode is "results/recv.sim";
begin
sendData <= (others => 'X');
sendValid <= '0';
wait until falling_edge(reset);
wait until rising_edge(sysClk);
while ( not endfile(inFile) ) loop
readline(inFile, inLine);
while ( inLine.all'length = 0 or inLine.all(1) = '#' or inLine.all(1) = ht or inLine.all(1) = ' ' ) loop
readline(inFile, inLine);
end loop;
sendData <= to_4(inLine.all(1)) & to_4(inLine.all(2));
sendValid <= to_1(inLine.all(4));
recvReady <= to_1(inLine.all(6));
wait for 10 ns;
write(outLine, from_4(sendData(7 downto 4)) & from_4(sendData(3 downto 0)));
write(outLine, ' ');
write(outLine, sendValid);
write(outLine, ' ');
write(outLine, sendReady);
writeline(outFile, outLine);
wait for 10 ns;
end loop;
sendData <= (others => 'X');
sendValid <= '0';
wait;
end process;
-- Mock the serial interface's interlocutor: send from s/recv.sim and receive into r/send.sim
process
variable inLine, outLine : line;
variable inData, outData : std_logic_vector(7 downto 0);
file inFile : text open read_mode is "stimulus/recv.sim";
file outFile : text open write_mode is "results/send.sim";
begin
spiDataIn <= 'X';
loop
exit when endfile(inFile);
readline(inFile, inLine);
read(inLine, inData);
wait until spiClk = '0';
spiDataIn <= inData(7);
wait until spiClk = '1';
outData(7) := spiDataOut;
wait until spiClk = '0';
spiDataIn <= inData(6);
wait until spiClk = '1';
outData(6) := spiDataOut;
wait until spiClk = '0';
spiDataIn <= inData(5);
wait until spiClk = '1';
outData(5) := spiDataOut;
wait until spiClk = '0';
spiDataIn <= inData(4);
wait until spiClk = '1';
outData(4) := spiDataOut;
wait until spiClk = '0';
spiDataIn <= inData(3);
wait until spiClk = '1';
outData(3) := spiDataOut;
wait until spiClk = '0';
spiDataIn <= inData(2);
wait until spiClk = '1';
outData(2) := spiDataOut;
wait until spiClk = '0';
spiDataIn <= inData(1);
wait until spiClk = '1';
outData(1) := spiDataOut;
wait until spiClk = '0';
spiDataIn <= inData(0);
wait until spiClk = '1';
outData(0) := spiDataOut;
write(outLine, outData);
writeline(outFile, outLine);
end loop;
wait for 10 ns;
spiDataIn <= 'X';
wait;
end process;
end architecture;
| gpl-3.0 | 5ac9fd3b2e92bf8dc0a3f737c120c0b1 | 0.655319 | 3.291717 | false | false | false | false |
ambrosef/HLx_Examples | Acceleration/memcached/regressionSims/sources/kvs_tbMonitorHDLNode.vhdl | 1 | 7,243 | -------------------------------------------------------------------------------
--
-- Title : local_link_sink.vhd - part of the Groucher simulation environment
--
-- Description : This code models the behavior of a local link sink device
--
-- Files: writes the received data and control into a data file
-- every clock cycle
-- The characters in the text file are interpreted as hex
-- Organization is MSB to LSB
-- padded with 0s on the MSBs to multiples of 4
-- data bus ' ' ctl signals(valid, done)
-- takes the flow ctl signal either through the parameters
-- or from a file. this is determined through the
-- generic BPR_PARA
-- Interface: the processing starts after rst de-asserts
-- the data and control signals are plainly recorded
-- the backpressure is driven either from file input
-- or throught the parameters
-- Parameters: data width
-- length width
-- rem width
-- l_present: indicates whether the length inetrface exists or not
-- bpr_para: when true then DST_RDY_N is driven through
-- the following paramters:
-- bpr_delay: waits for bpr_Delay*clock ticks before
-- commencing assertion
-- bpr_period: indicates how often backpressure is asserted
-- in clock ticks
-- bpr_duration: inidcates for how long backpressure is
-- asserted within one period.
-- DURATION < PERIOD!
-- BPR_FILENAME : file name of input backpressure file
-- PKT_FILENAME : filename of output data file
--
--
-- ----------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_TEXTIO.all;
LIBRARY STD;
USE STD.TEXTIO.ALL;
entity kvs_tbMonitorHDLNode is
generic (
D_WIDTH : integer := 72;
BPR_PARA : Boolean := true; -- decides whether BPR from parameter or file
BPR_DELAY : integer := 100; -- in cycles
BPR_PERIOD : integer := 20; -- in cycles
BPR_DURATION : integer := 2; -- in cycles
BPR_EN : Boolean := true;
BPR_FILENAME : string := "bpr.txt";
PKT_FILENAME : string := "pkt.out.txt"
);
port (
clk : in std_logic;
rst : in std_logic;
udp_in_ready : out std_logic;
udp_in_valid : in std_logic;
udp_in_keep : in std_logic_vector(7 downto 0);
udp_in_user : in std_logic_vector(111 downto 0);
udp_in_last : in std_logic;
udp_in_data : in std_logic_vector (63 downto 0)
);
end kvs_tbMonitorHDLNode;
architecture structural of kvs_tbMonitorHDLNode is
constant FD_WIDTH : integer := ((D_WIDTH-1) / 4)*4 + 4;
signal udp_in_stall_raw : std_logic;
signal para_bpr : std_logic;
signal file_bpr : std_logic;
signal udp_in_ready_im : std_logic;
begin
-- switches between parameter and file input mode
udp_in_stall_raw <= para_bpr when BPR_PARA else file_bpr;
udp_in_ready_im <= NOT udp_in_stall_raw when BPR_EN else '0';
udp_in_ready <= udp_in_ready_im;
-- backpressure from parameter process
pbpr_p: process
begin
if (BPR_DURATION > BPR_PERIOD) then
assert false report "BPR_PERIOD must be greater/equal than BPR_DURATION" severity failure;
end if;
para_bpr <= '0';
wait until rst = '0';
-- wait the once of start-up delay after rst
for i in 0 to BPR_DELAY-1 loop
wait until (clk'event and clk='1');
end loop;
-- start backpressuring
while true loop
for i in 0 to (BPR_PERIOD-BPR_DURATION-1) loop
wait until (clk'event and clk='1');
end loop;
para_bpr <= '1';
for i in 0 to (BPR_DURATION-1) loop
wait until (clk'event and clk='1');
end loop;
para_bpr <= '0';
end loop;
end process;
-- backpressure from file process
fbpr_p: process
FILE input_file : TEXT;
variable l : line;
variable read_dat : std_logic_vector(3 downto 0);
begin
wait until rst = '0';
if (not BPR_PARA) then
file_open(input_file, BPR_FILENAME, READ_MODE);
while (not endfile(input_file)) loop
wait until CLK'event and CLK='1';
READLINE(input_file, l);
HREAD(l, read_dat);
file_bpr <= read_dat(0);
end loop;
file_close(input_file);
end if;
end process;
-- write process for the received packet
write_pktfile_p : process
FILE pkt_file : TEXT OPEN WRITE_MODE IS PKT_FILENAME;
variable l : line;
variable d : character := 'D';
variable blank : character := ' ';
--variable user_vector : std_logic_vector(111 downto 0);
variable dat_vector : std_logic_vector(63 downto 0);
variable keep_vector : std_logic_vector(7 downto 0);
variable ctl_vector : std_logic_vector(3 downto 0);
variable last : std_logic_vector(0 downto 0);
variable modulus : std_logic_vector(2 downto 0);
begin
if (D_WIDTH=0) then
assert false report "D_WIDTH and R_WIDTH must be greater than 0" severity failure;
end if;
wait until rst='0';
while TRUE loop
-- write each cycle
wait until CLK'event and CLK='1';
-- padding
--user_vector := udp_in_user;
dat_vector := udp_in_data;
keep_vector := udp_in_keep;
last(0) := udp_in_last;
dat_vector(FD_WIDTH-1 downto D_WIDTH) := (others => '0');
ctl_vector(3 downto 0) := '0' & '0' & (udp_in_valid AND udp_in_ready_im) & '0'; -- udp_in_done is deprecated
-- compose output line and mas modulus.
--write(l,d);
--hwrite(l, user_vector);
--write(l,blank);
hwrite(l, dat_vector(FD_WIDTH-1 downto 64));
--eop := udp_in_data(67);
--modulus := udp_in_data(66 downto 64);
--if eop = '1' then
-- case modulus is
-- when "001" => write(l, string'("**************")); hwrite(l, dat_vector(7 downto 0));
-- when "010" => write(l, string'("************")); hwrite(l, dat_vector(15 downto 0));
-- when "011" => write(l, string'("**********")); hwrite(l, dat_vector(23 downto 0));
-- when "100" => write(l, string'("********")); hwrite(l, dat_vector(31 downto 0));
-- when "101" => write(l, string'("******")); hwrite(l, dat_vector(39 downto 0));
-- when "110" => write(l, string'("****")); hwrite(l, dat_vector(47 downto 0));
-- when "111" => write(l, string'("**")); hwrite(l, dat_vector(55 downto 0));
-- when others => hwrite(l, dat_vector(63 downto 0));
-- end case;
--else
hwrite(l, dat_vector);
--end if;
write(l,blank);
hwrite(l, keep_vector);
write(l,blank);
hwrite(l, last);
write(l,blank);
hwrite(l, ctl_vector);
-- writing
writeline(pkt_file, l);
end loop;
end process;
end structural; | bsd-3-clause | c8e699003d4c8fbd4307a8858839a301 | 0.55778 | 3.599901 | false | false | false | false |
gmsanchez/OrgComp | TP_01/TB_deco_32b.vhd | 1 | 3,676 | --------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 14:13:28 09/10/2014
-- Design Name:
-- Module Name: /home/gsanchez/Apps/TP_01/TB_deco_32b.vhd
-- Project Name: TP_01
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: deco_32b
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
use std.textio.all;
use work.txt_util.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY TB_deco_32b IS
END TB_deco_32b;
ARCHITECTURE behavior OF TB_deco_32b IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT deco_32b
PORT(
E : IN std_logic;
A : IN std_logic_vector(4 downto 0);
D : OUT std_logic_vector(31 downto 0)
);
END COMPONENT;
--Inputs
signal E : std_logic := '0';
signal A : std_logic_vector(4 downto 0) := (others => '0');
--Outputs
signal D : std_logic_vector(31 downto 0);
-- No clocks detected in port list. Replace <clock> below with
-- appropriate port name
-- constant <clock>_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: deco_32b PORT MAP (
E => E,
A => A,
D => D
);
-- Clock process definitions
-- <clock>_process :process
-- begin
-- <clock> <= '0';
-- wait for <clock>_period/2;
-- <clock> <= '1';
-- wait for <clock>_period/2;
-- end process;
-- Stimulus process
stim_proc: process
-- variable sD : string (32 downto 1);
-- variable sDtest : string(32 downto 1);
variable Dtest : std_logic_vector(31 downto 0);
begin
-- Initialize input signals
E <= '0';
A <= "00000";
wait for 20 ns;
--
for En in 0 to 1 loop
E <= std_logic(to_unsigned(En,1)(0));
for Anum in 0 to 31 loop
A <= std_logic_vector(to_unsigned(Anum,5));
-- Esperamos 5 ns para que se propague la señal A nueva
wait for 5 ns;
report "Entradas E = " & integer'image(En) & ", A = " & integer'image(Anum);
-- Inicializo Stest en x'00000000'
-- luego hago el bit en la posicion Anum = 1
-- Para ver si el deco funciona bien
Dtest := (others => '0');
Dtest(Anum) := '1';
-- for i in 0 to 31 loop
-- if D(i) = '0' then
-- sD(i+1) := '0';
-- else
-- sD(i+1) := '1';
-- end if;
-- if Dtest(i) = '0' then
-- sDtest(i+1) := '0';
-- else
-- sDtest(i+1) := '1';
-- end if;
-- end loop;
if (En = 0) then
assert (x"00000000" = D)
report "Resultado erroneo. D = " & str(D) & ". Deberia ser 00000000000000000000000000000000."
severity ERROR;
else
assert (Dtest = D)
report "Resultado erroneo. D = " & str(D) & ". Deberia ser " & str(Dtest) & "."
severity ERROR;
end if;
wait for 10 ns;
end loop;
end loop;
wait for 100 ns;
--wait for <clock>_period*10;
-- insert stimulus here
wait;
end process;
END;
| gpl-2.0 | 544f9cb4f035b765ebc52f593ceb3bde | 0.566259 | 3.26087 | false | true | false | false |
gmsanchez/OrgComp | TP_01/TB_Alu_32b.vhd | 1 | 5,208 | --------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 14:01:24 09/11/2014
-- Design Name:
-- Module Name: /home/gsanchez/Apps/TP_01/TB_Alu_32b.vhd
-- Project Name: TP_01
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: ALU_32b
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
USE ieee.numeric_std.ALL;
use IEEE.std_logic_unsigned.all;
ENTITY TB_Alu_32b IS
END TB_Alu_32b;
ARCHITECTURE behavior OF TB_Alu_32b IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT ALU_32b
PORT(
A : IN std_logic_vector(31 downto 0);
B : IN std_logic_vector(31 downto 0);
AluOp : IN std_logic_vector(3 downto 0);
AluOut : BUFFER std_logic_vector(31 downto 0);
Zero : OUT std_logic;
OFL : OUT std_logic;
COut : OUT std_logic
);
END COMPONENT;
--Inputs
signal A : std_logic_vector(31 downto 0) := (others => '0');
signal B : std_logic_vector(31 downto 0) := (others => '0');
signal AluOp : std_logic_vector(3 downto 0) := (others => '0');
--Outputs
signal AluOut : std_logic_vector(31 downto 0);
signal Zero : std_logic;
signal OFL : std_logic;
signal COut : std_logic;
TYPE num_array IS ARRAY (1 TO 4) OF std_logic_vector(31 downto 0);
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: ALU_32b PORT MAP (
A => A,
B => B,
AluOp => AluOp,
AluOut => AluOut,
Zero => Zero,
OFL => OFL,
COut => COut
);
-- Stimulus process
stim_proc: process
variable na : num_array;
variable sum : std_logic_vector(32 downto 0);
begin
na(1) := x"00000000";
na(2) := x"ffffffff";
na(3) := x"5a5a5a5a";
na(4) := x"a5a5a5a5";
for nidx_i in 1 to 4 loop
for nidx_j in 1 to 4 loop
for AluOpInt in 0 to 15 loop
A<= na(nidx_i);
B<= na(nidx_j);
AluOp <= std_logic_vector(to_unsigned(AluOpInt,4));
wait for 10 ns;
case AluOp is
when "0000" => assert (AluOut = (A and B))
report "Resultado erroneo. AluOp = " & integer'image(AluOpInt)
severity ERROR;
when "0001" => assert (AluOut = (A or B))
report "Resultado erroneo. AluOp = " & integer'image(AluOpInt)
severity ERROR;
when "0010" => sum := (A(A'high) & A) + (B(B'high) & B);
assert (AluOut = (sum(31 downto 0)))
report "Resultado erroneo. AluOp = " & integer'image(AluOpInt)
severity ERROR;
assert (COut = sum(32))
report "Resultado erroneo. AluOp = " & integer'image(AluOpInt)
severity ERROR;
assert (OFL = (sum(32) xor sum(31)))
report "Resultado erroneo. AluOp = " & integer'image(AluOpInt)
severity ERROR;
when "0110" => sum := (A(A'high) & A) - (B(B'high) & B);
assert (AluOut = (sum(31 downto 0)))
report "Resultado erroneo. AluOp = " & integer'image(AluOpInt)
severity ERROR;
assert (COut = sum(32))
report "Resultado erroneo. AluOp = " & integer'image(AluOpInt)
severity ERROR;
assert (OFL = (sum(32) xor sum(31)))
report "Resultado erroneo. AluOp = " & integer'image(AluOpInt)
severity ERROR;
when "0111" => if (A<B) then
Assert (AluOut = x"00000001")
report "Resultado erroneo. AluOp = " & integer'image(AluOpInt)
severity ERROR;
else
Assert (AluOut = x"00000000")
report "Resultado erroneo. AluOp = " & integer'image(AluOpInt)
severity ERROR;
end if;
when "1100" => assert (AluOut = (not(A or B)))
report "Resultado erroneo. AluOp = " & integer'image(AluOpInt)
severity ERROR;
when others => assert (AluOut = x"00000000")
report "Resultado erroneo. AluOp = " & integer'image(AluOpInt)
severity ERROR;
end case;
end loop;
end loop;
end loop;
-- AluOp <= "0010";
-- A <= x"40000000";--x"11111111";
-- B <= x"0000000F";--x"FFFFFFFF";
-- wait for 10 ns;
-- AluOp <= "0110";
-- A <= x"7FFFFFFF";
-- B <= x"FFFFFFFF";
-- wait for 10 ns;
-- A <= x"01010101";
-- B <= x"F0F0F0F0";
-- for AluOpInt in 0 to 15 loop
-- AluOp <= std_logic_vector(to_unsigned(AluOpInt,4));
-- wait for 10 ns;
-- end loop;
--
-- wait for 100 ns;
-- insert stimulus here
wait;
end process;
END;
| gpl-2.0 | cd0205e18cb0968cb84af32aa1b62108 | 0.56394 | 3.338462 | false | false | false | false |
emogenet/ghdl | testsuite/vests/vhdl-93/ashenden/compliant/ch_15_ire-b.vhd | 4 | 1,918 |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_15_ire-b.vhd,v 1.1.1.1 2001-08-22 18:20:48 paw Exp $
-- $Revision: 1.1.1.1 $
--
-- ---------------------------------------------------------------------
use work.dlx_instr.all;
architecture behavior of ir_extender is
subtype upper_6_bits is std_logic_vector(0 to 5);
subtype upper_16_bits is std_logic_vector(0 to 15);
begin
extender : process ( d, immed_en, immed_size_26, immed_unsigned ) is
begin
if To_bit(immed_en) = '1' then
if To_bit(immed_size_26) = '1' then -- 26-bit immediate
if To_bit(immed_unsigned) = '1' then
q <= upper_6_bits'(others => '0') & d(6 to 31) after Tpd;
else
q <= upper_6_bits'(others => d(6)) & d(6 to 31) after Tpd;
end if;
else -- 16-bit immediate
if To_bit(immed_unsigned) = '1' then
q <= upper_16_bits'(others => '0') & d(16 to 31) after Tpd;
else
q <= upper_16_bits'(others => d(16)) & d(16 to 31) after Tpd;
end if;
end if;
else
q <= disabled_dlx_word after Tpd;
end if;
end process extender;
end architecture behavior;
| gpl-2.0 | aa6c2e4bc6c8f3cf494812f76c877149 | 0.61731 | 3.480944 | false | false | false | false |
pmh92/Proyecto-OFDM | src/ESTIMADOR.vhd | 1 | 8,691 | ---------------------------------------
-- 7/JUL/2015 - Pedro Morales Hernandez
-- Modulo del Estimador
---------------------------------------
-- Importacion de librerias
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
-- Declaracion de la Entidad
entity ESTIMADOR is PORT(
clk : IN STD_LOGIC; -- Reloj
rst : IN STD_LOGIC; -- Reset asincrono, activo a nivel alto
start : IN STD_LOGIC; -- Seal que indica el inicio del proceso de estimacion
fin : OUT STD_LOGIC; -- Seal que indica el fin de la estimacion
addr_y : OUT STD_LOGIC_VECTOR(10 DOWNTO 0); -- Lectura de Simbolo
addr_h : OUT STD_LOGIC_VECTOR(10 DOWNTO 0); -- Escritura de Ecualizacion
y_data : IN STD_LOGIC_VECTOR(19 DOWNTO 0); -- Dato de Entrada
h_data : OUT STD_LOGIC_VECTOR(23 DOWNTO 0); -- Dato de Salida
write_h : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)); -- Seal que indica que se escriba el dato
end ESTIMADOR;
architecture Behavioral of ESTIMADOR is
SUBTYPE addr IS STD_LOGIC_VECTOR(10 DOWNTO 0); -- Por si es necesario redefinir el tamao de las direcciones
-- Submodulos
COMPONENT PRBS IS
Port ( clk : in STD_LOGIC;
rst : in STD_LOGIC;
enable : in STD_LOGIC;
output : out STD_LOGIC);
END COMPONENT;
-- Tipos Complejos
TYPE complex10 IS RECORD -- De 10 bits
re: SIGNED(9 DOWNTO 0);
im: SIGNED(9 DOWNTO 0);
END RECORD;
TYPE complex12 IS RECORD -- De 12 bits
re: SIGNED(11 DOWNTO 0);
im: SIGNED(11 DOWNTO 0);
END RECORD;
TYPE context_t IS RECORD -- Almacena el estado del sistema
h_dir : addr; -- Direccion H (Estimacion)
y_dir : addr; -- Direccion Y (Simbolo)
valor : complex10; -- Valor calculado de un piloto
h_est : complex12; -- H estimada en una posicion
piloto_inf : complex10; -- Piloto Inferior
piloto_sup : complex10; -- Piloto Superior
modulo : INTEGER; -- Indica la posicion con respecto al piloto anterior (0-12)
END RECORD;
-- Esta funcion calcula el valor de un
-- piloto en funcion del valor actual del PRBS
FUNCTION CALCULA_H_PILOTO(piloto : complex10; prbs_val : STD_LOGIC) RETURN complex10 IS
VARIABLE H : complex10 := (re => (OTHERS => '0'), im => (OTHERS => '0'));
BEGIN
IF(prbs_val = '1') THEN -- Si vale 1, negamos el piloto, no es necesario escalar
H.re := -piloto.re;
H.im := -piloto.im;
ELSE -- Si vale 0 lo dejamos igual
H.re := piloto.re;
H.im := piloto.im;
END IF;
RETURN H;
END CALCULA_H_PILOTO;
-- Estados posibles
TYPE estados IS (reposo,ini_lee,ini_calcula,avance,lee,calcula,actualiza_piloto_1,actualiza_piloto_2,actualiza_piloto_3,escribe,terminado);
-- Reposo : El sistema se encuentra en reposo y no espera la seal START
-- ini_* : Proceso de inicializacion, para llevar el PRBS al valor deseado
-- ini_lee : Leemos de la memoria el valor de un piloto
-- ini_calcula : Calculamos el valor de H en esa posicion
-- avance : Avanzamos el PRBS sin realizar ninguna accion
-- lee : Esperamos si es necesario para leer un piloto, siempre se ejecuta
-- calcula: Calculamos el valor de un piloto en un punto dado
-- escribe: Escribimos el valor calculado en la memoria
-- actualiza_piloto_* : Nos permite actualizar el valor de los pilotos
-- terminado : Indica que el proceso ha finalizado exitosamente
SIGNAL p_context,context : context_t; -- Contexto actual y proximo
SIGNAL prbs_val,prbs_next: STD_LOGIC := '0'; -- Valores del PRBS
SIGNAL estado,p_estado : estados; -- Estado actual y proximo
BEGIN
-- Modelos Instanciados
prbs_c: COMPONENT PRBS
PORT MAP(
clk => clk,
rst => rst,
enable => prbs_next,
output => prbs_val
);
-- Conexiones de seales
addr_y <= context.y_dir;
addr_h <= context.h_dir;
-- Proceso Combinacional
comb : PROCESS(start,estado,context,y_data,prbs_val)
VARIABLE aux_re,aux_im : SIGNED(19 DOWNTO 0); -- Variables auxiliares para calcular el valor del canal
BEGIN
-- Valores por defecto en todos los estados
p_context <= context;
write_h <= "0";
prbs_next <= '0';
h_data <= (OTHERS => '0');
fin <= '0';
CASE estado IS
WHEN reposo =>
-- Inicializamos las variables a cero
p_context.h_dir <= (OTHERS => '0');
p_context.y_dir <= (OTHERS => '0');
p_context.piloto_inf <= (re => (OTHERS => '0'), im => (OTHERS => '0'));
p_context.piloto_sup <= (re => (OTHERS => '0'), im => (OTHERS => '0'));
p_context.h_est <= (re => (OTHERS => '0'), im => (OTHERS => '0'));
p_context.valor <= (re => (OTHERS => '0'), im => (OTHERS => '0'));
p_context.modulo <= 0;
-- Cambio de estado
IF(start = '1') THEN
p_estado <= ini_lee;
ELSE
p_estado <= reposo;
END IF;
WHEN ini_lee =>
p_context.valor.re <= SIGNED(y_data(19 DOWNTO 10)); -- Leemos una seal de la entrada
p_context.valor.im <= SIGNED(y_data(9 DOWNTO 0));
p_estado <= ini_calcula;
WHEN ini_calcula =>
p_context.piloto_sup <= CALCULA_H_PILOTO(context.valor,prbs_val);
p_context.piloto_inf <= context.piloto_sup; -- Actualizamos el contexto
IF(context.y_dir = STD_LOGIC_VECTOR(TO_UNSIGNED(12,11))) THEN -- Si estamos en la posicion 12
-- Fin de la inicializacion, vamos a la posicion 1
p_context.y_dir <= "00000000001";
p_context.h_dir <= "00000000001";
p_context.modulo <= 1; -- El modulo se inicia en 1
p_estado <= lee;
ELSE
p_context.y_dir <= STD_LOGIC_VECTOR(TO_UNSIGNED(12,11)); -- Vamos a la posicion 12
p_estado <= avance;
END IF;
WHEN avance =>
prbs_next <= '1'; -- Activamos el PRBS
p_context.h_dir <= STD_LOGIC_VECTOR(UNSIGNED(context.h_dir)+1);
p_context.modulo <= context.modulo + 1; -- Esto nos permite contar cuantas veces estamos en este estado
IF(context.modulo = 11) THEN -- 12 ciclos en total
p_estado <= ini_lee; -- Volvemos a ini_lee
ELSE
p_estado <= avance; -- Seguimos en avance
END IF;
WHEN lee =>
prbs_next <= '1'; -- Avanzamos el PRBS
IF(context.modulo = 12) THEN -- Si estamos en un piloto
p_context.modulo <= 0; -- Modulo a 0
IF(context.h_dir = STD_LOGIC_VECTOR(TO_UNSIGNED(1704,11))) THEN -- Si es la ultima posicion termina directamente
p_estado <= terminado;
ELSE
p_estado <= actualiza_piloto_1; -- Actualizamos en valor de los pilotos
END IF;
ELSE -- Si no estamos en un piloto
p_estado <= calcula;
END IF;
WHEN calcula =>
-- Calculamos el valor de los pilotos
aux_re := (12-context.modulo)*context.piloto_inf.re+context.modulo*context.piloto_sup.re;
aux_im := (12-context.modulo)*context.piloto_inf.im+context.modulo*context.piloto_sup.im;
p_context.h_est.re <= aux_re(13 DOWNTO 2);
p_context.h_est.im <= aux_im(13 DOWNTO 2);
p_estado <= escribe;
WHEN escribe =>
-- Escribimos el valor estimado
write_h <= "1";
h_data(23 DOWNTO 12) <= STD_LOGIC_VECTOR(context.h_est.re); -- Parte Real
h_data(11 DOWNTO 0) <= STD_LOGIC_VECTOR(context.h_est.im); -- Parte Imaginaria
IF(context.modulo = 11) THEN -- El siguiente ser un piloto
p_context.y_dir <= STD_LOGIC_VECTOR(UNSIGNED(context.y_dir)+13); -- Cargamos la direccion, ahorrando un ciclo
ELSE -- Si no, seguimos con el siguiente valor
p_context.y_dir <= STD_LOGIC_VECTOR(UNSIGNED(context.y_dir)+1);
END IF;
p_context.h_dir <= STD_LOGIC_VECTOR(UNSIGNED(context.h_dir)+1); -- Siguiente valor
p_context.modulo <= context.modulo + 1; -- Aumentamos el modulo en 1
p_estado <= lee; -- Siempre volvemos a lee
WHEN actualiza_piloto_1 =>
p_context.valor.re <= SIGNED(y_data(19 DOWNTO 10)); -- Leemos la parte Real
p_context.valor.im <= SIGNED(y_data(9 DOWNTO 0)); -- Leemos la parte Imaginaria
p_estado <= actualiza_piloto_2;
WHEN actualiza_piloto_2 =>
p_context.piloto_sup <= CALCULA_H_PILOTO(context.valor,prbs_val); -- Calculamos el valor del piloto
p_context.piloto_inf <= context.piloto_sup; -- Actualizamos los valores
p_estado <= actualiza_piloto_3;
WHEN actualiza_piloto_3 =>
p_context.y_dir <= STD_LOGIC_VECTOR(UNSIGNED(context.y_dir)-11); -- Vamos a la siguiente posicion y_dir-12+1
p_context.h_dir <= STD_LOGIC_VECTOR(UNSIGNED(context.h_dir)+1); -- Siguiente posicion
p_context.modulo <= 1; -- Reinicializamos el modulo
p_estado <= lee;
WHEN terminado =>
fin <= '1'; -- Indicamos FIN
p_estado <= reposo;
END CASE;
END PROCESS;
-- Proceso sincrono
sinc : PROCESS(clk,rst)
BEGIN
IF(rst = '1') THEN
estado <= reposo; -- Reset asincrono
context.h_dir <= (OTHERS => '0');
context.y_dir <= (OTHERS => '0');
context.valor <= (re => (OTHERS => '0'), im => (OTHERS => '0'));
context.h_est <= (re => (OTHERS => '0'), im => (OTHERS => '0'));
context.piloto_inf <= (re => (OTHERS => '0'), im => (OTHERS => '0'));
context.piloto_sup <= (re => (OTHERS => '0'), im => (OTHERS => '0'));
ELSIF(rising_edge(clk)) THEN
estado <= p_estado;
context <= p_context;
END IF;
END PROCESS;
end Behavioral;
| gpl-2.0 | fb47b4ce13f5699814cda66dd0dfcc2f | 0.66264 | 2.92331 | false | false | false | false |
emogenet/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc756.vhd | 4 | 58,413 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc756.vhd,v 1.2 2001-10-26 16:30:00 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c01s01b01x01p05n02i00756ent IS
generic(
zero : integer := 0;
one : integer := 1;
two : integer := 2;
three: integer := 3;
four : integer := 4;
five : integer := 5;
six : integer := 6;
seven: integer := 7;
eight: integer := 8;
nine : integer := 9;
fifteen:integer:= 15;
C1 : boolean := true;
C2 : bit := '1';
C3 : character := 's';
C4 : severity_level := note;
C5 : integer := 3;
C6 : real := 3.0;
C7 : time := 3 ns;
C8 : natural := 1;
C9 : positive := 1;
C10 : string := "shishir";
C11 : bit_vector := B"0011"
);
END c01s01b01x01p05n02i00756ent;
ARCHITECTURE c01s01b01x01p05n02i00756arch OF c01s01b01x01p05n02i00756ent IS
subtype hi_to_low_range is integer range zero to seven;
type boolean_vector is array (natural range <>) of boolean;
type severity_level_vector is array (natural range <>) of severity_level;
type integer_vector is array (natural range <>) of integer;
type real_vector is array (natural range <>) of real;
type time_vector is array (natural range <>) of time;
type natural_vector is array (natural range <>) of natural;
type positive_vector is array (natural range <>) of positive;
subtype boolean_vector_st is boolean_vector(zero to fifteen);
subtype severity_level_vector_st is severity_level_vector(zero to fifteen);
subtype integer_vector_st is integer_vector(zero to fifteen);
subtype real_vector_st is real_vector(zero to fifteen);
subtype time_vector_st is time_vector(zero to fifteen);
subtype natural_vector_st is natural_vector(zero to fifteen);
subtype positive_vector_st is positive_vector(zero to fifteen);
type boolean_cons_vector is array (fifteen downto zero) of boolean;
type severity_level_cons_vector is array (fifteen downto zero) of severity_level;
type integer_cons_vector is array (fifteen downto zero) of integer;
type real_cons_vector is array (fifteen downto zero) of real;
type time_cons_vector is array (fifteen downto zero) of time;
type natural_cons_vector is array (fifteen downto zero) of natural;
type positive_cons_vector is array (fifteen downto zero) of positive;
type boolean_cons_vectorofvector is array (zero to fifteen) of boolean_cons_vector;
type severity_level_cons_vectorofvector is array (zero to fifteen) of severity_level_cons_vector;
type integer_cons_vectorofvector is array (zero to fifteen) of integer_cons_vector ;
type real_cons_vectorofvector is array (zero to fifteen) of real_cons_vector;
type time_cons_vectorofvector is array (zero to fifteen) of time_cons_vector;
type natural_cons_vectorofvector is array (zero to fifteen) of natural_cons_vector;
type positive_cons_vectorofvector is array (zero to fifteen) of positive_cons_vector;
type record_std_package is record
a: boolean;
b: bit;
c:character;
d:severity_level;
e:integer;
f:real;
g:time;
h:natural;
i:positive;
j:string(one to seven);
k:bit_vector(zero to three);
end record;
type record_array_st is record
a:boolean_vector_st;
b:severity_level_vector_st;
c:integer_vector_st;
d:real_vector_st;
e:time_vector_st;
f:natural_vector_st;
g:positive_vector_st;
end record;
type record_cons_array is record
a:boolean_cons_vector;
b:severity_level_cons_vector;
c:integer_cons_vector;
d:real_cons_vector;
e:time_cons_vector;
f:natural_cons_vector;
g:positive_cons_vector;
end record;
type record_cons_arrayofarray is record
a:boolean_cons_vectorofvector;
b:severity_level_cons_vectorofvector;
c:integer_cons_vectorofvector;
d:real_cons_vectorofvector;
e:time_cons_vectorofvector;
f:natural_cons_vectorofvector;
g:positive_cons_vectorofvector;
end record;
type record_array_new is record
a:boolean_vector(zero to fifteen);
b:severity_level_vector(zero to fifteen);
c:integer_vector(zero to fifteen);
d:real_vector(zero to fifteen);
e:time_vector(zero to fifteen);
f:natural_vector(zero to fifteen);
g:positive_vector(zero to fifteen);
end record;
type record_of_records is record
a: record_std_package;
c: record_cons_array;
g: record_cons_arrayofarray;
i: record_array_st;
j: record_array_new;
end record;
subtype boolean_vector_range is boolean_vector(hi_to_low_range);
subtype severity_level_vector_range is severity_level_vector(hi_to_low_range);
subtype integer_vector_range is integer_vector(hi_to_low_range);
subtype real_vector_range is real_vector(hi_to_low_range);
subtype time_vector_range is time_vector(hi_to_low_range);
subtype natural_vector_range is natural_vector(hi_to_low_range);
subtype positive_vector_range is positive_vector(hi_to_low_range);
type array_rec_std is array (integer range <>) of record_std_package;
type array_rec_cons is array (integer range <>) of record_cons_array;
type array_rec_rec is array (integer range <>) of record_of_records;
subtype array_rec_std_st is array_rec_std (hi_to_low_range);
subtype array_rec_cons_st is array_rec_cons (hi_to_low_range);
subtype array_rec_rec_st is array_rec_rec (hi_to_low_range);
type record_of_arr_of_record is record
a: array_rec_std(zero to seven);
b: array_rec_cons(zero to seven);
c: array_rec_rec(zero to seven);
end record;
type current is range -2147483647 to +2147483647
units
nA;
uA = 1000 nA;
mA = 1000 uA;
A = 1000 mA;
end units;
type current_vector is array (natural range <>) of current;
subtype current_vector_range is current_vector(hi_to_low_range);
type resistance is range -2147483647 to +2147483647
units
uOhm;
mOhm = 1000 uOhm;
Ohm = 1000 mOhm;
KOhm = 1000 Ohm;
end units;
type resistance_vector is array (natural range <>) of resistance;
subtype resistance_vector_range is resistance_vector(hi_to_low_range);
type byte is array(zero to seven) of bit;
subtype word is bit_vector(zero to fifteen); --constrained array
constant size :integer := seven;
type primary_memory is array(zero to size) of word; --array of an array
type primary_memory_module is --record with field
record --as an array
enable:bit;
memory_number:primary_memory;
end record;
type whole_memory is array(0 to size) of primary_memory_module; --array of a complex record
subtype delay is integer range one to 10;
constant C12 : boolean_vector := (C1,false);
constant C13 : severity_level_vector := (C4,error);
constant C14 : integer_vector := (one,two,three,four);
constant C15 : real_vector := (1.0,2.0,C6,4.0);
constant C16 : time_vector := (1 ns, 2 ns,C7, 4 ns);
constant C17 : natural_vector := (one,2,3,4);
constant C18 : positive_vector := (one,2,3,4);
constant C19 : boolean_cons_vector := (others => C1);
constant C20 : severity_level_cons_vector := (others => C4);
constant C21 : integer_cons_vector := (others => C5);
constant C22 : real_cons_vector := (others => C6);
constant C23 : time_cons_vector := (others => C7);
constant C24 : natural_cons_vector := (others => C8);
constant C25 : positive_cons_vector := (others => C9);
constant C26 : boolean_cons_vectorofvector := (others => (others => C1));
constant C27 : severity_level_cons_vectorofvector := (others => (others => C4));
constant C28 : integer_cons_vectorofvector := (others => (others => C5));
constant C29 : real_cons_vectorofvector := (others => (others => C6));
constant C30 : time_cons_vectorofvector := (others => (others => C7));
constant C31 : natural_cons_vectorofvector := (others => (others => C8));
constant C32 : positive_cons_vectorofvector := (others => (others => C9));
constant C50 : record_std_package := (C1,C2,C3,C4,C5,C6,C7,C8,C9,C10,C11);
constant C51 : record_cons_array := (C19,C20,C21,C22,C23,C24,C25);
constant C53 : record_cons_arrayofarray := (C26,C27,C28,C29,C30,C31,C32);
constant C70 : boolean_vector_st :=(others => C1);
constant C71 : severity_level_vector_st:= (others => C4);
constant C72 : integer_vector_st:=(others => C5);
constant C73 : real_vector_st:=(others => C6);
constant C74 : time_vector_st:=(others => C7);
constant C75 : natural_vector_st:=(others => C8);
constant C76 : positive_vector_st:=(others => C9);
constant C77 : record_array_st := (C70,C71,C72,C73,C74,C75,C76);
constant C54a : record_array_st := (C70,C71,C72,C73,C74,C75,C76);
constant C54b : record_array_new:= (C70,C71,C72,C73,C74,C75,C76);
constant C55 : record_of_records := (C50,C51,C53,C77,C54b);
constant C60 : byte := (others => '0');
constant C61 : word := (others =>'0' );
constant C64 : primary_memory := (others => C61);
constant C65 : primary_memory_module := ('1',C64);
constant C66 : whole_memory := (others => C65);
constant C67 : current := 1 A;
constant C68 : resistance := 1 Ohm;
constant C69 : delay := 2;
constant C78 : boolean_vector_range := (others => C1);
constant C79 : severity_level_vector_range := (others => C4) ;
constant C80 : integer_vector_range :=(others => C5) ;
constant C81 : real_vector_range :=(others => C6);
constant C82 : time_vector_range :=(others => C7);
constant C83 : natural_vector_range :=(others => C8);
constant C84 : positive_vector_range :=(others => C9);
constant C85 : array_rec_std(0 to 7) :=(others => C50) ;
constant C86 : array_rec_cons (0 to 7) :=(others => C51);
constant C88 : array_rec_rec(0 to 7) :=(others => C55);
constant C102 : record_of_arr_of_record:= (C85,C86,C88);
BEGIN
TESTING: PROCESS
variable V1 : boolean_vector(zero to fifteen);
variable V2 : severity_level_vector(zero to fifteen);
variable V3 : integer_vector(zero to fifteen);
variable V4 : real_vector(zero to fifteen);
variable V5 : time_vector (zero to fifteen);
variable V6 : natural_vector(zero to fifteen);
variable V7 : positive_vector(zero to fifteen);
variable V8 : boolean_cons_vector;
variable V9 : severity_level_cons_vector ;
variable V10 : integer_cons_vector;
variable V11 : real_cons_vector;
variable V12 : time_cons_vector ;
variable V13 : natural_cons_vector ;
variable V14 : positive_cons_vector ;
variable V15 : boolean_cons_vectorofvector;
variable V16 : severity_level_cons_vectorofvector;
variable V17 : integer_cons_vectorofvector;
variable V18 : real_cons_vectorofvector;
variable V19 : time_cons_vectorofvector;
variable V20 : natural_cons_vectorofvector;
variable V21 : positive_cons_vectorofvector;
variable V22 : record_std_package;
variable V23 : record_cons_array;
variable V24 : record_cons_arrayofarray ;
variable V25 : boolean_vector_st;
variable V26 : severity_level_vector_st;
variable V27 : integer_vector_st;
variable V28 : real_vector_st;
variable V29 : time_vector_st;
variable V30 : natural_vector_st;
variable V31 : positive_vector_st;
variable V32 : record_array_st;
variable V33 : record_array_st;
variable V34 : record_array_new;
variable V35 : record_of_records;
variable V36 : byte;
variable V37 : word;
variable V38 : current_vector(zero to three);
variable V39 : resistance_vector(zero to three);
variable V40 : delay;
variable V41 : boolean_vector_range;
variable V42 : severity_level_vector_range ;
variable V43 : integer_vector_range ;
variable V44 : real_vector_range ;
variable V45 : time_vector_range ;
variable V46 : natural_vector_range ;
variable V47 : positive_vector_range ;
variable V48 : array_rec_std(zero to seven);
variable V49 : array_rec_cons(zero to seven);
variable V50 : array_rec_rec(zero to seven);
variable V51 : record_of_arr_of_record;
BEGIN
assert (V1'left = 0) report " boolean_vector(zero to fifteen) error in the left generic value" severity error;
assert (V2'left = 0) report " severity_level_vector(zero to fifteen) error in the left generic value" severity error;
assert (V3'left = 0) report " integer_vector(zero to fifteen) error in the left generic value" severity error;
assert (V4'left = 0) report " real_vector(zero to fifteen) error in the left generic value" severity error;
assert (V5'left = 0) report " time_vector (zero to fifteen) error in the left generic value" severity error;
assert (V6'left = 0) report " natural_vector(zero to fifteen) error in the left generic value" severity error;
assert (V7'left = 0) report " positive_vector(zero to fifteen) error in the left generic value" severity error;
assert (V8'left = 15) report " boolean_cons_vector error in the left generic value" severity error;
assert (V9'left = 15) report " severity_level_cons_vector error in the left generic value" severity error;
assert (V10'left = 15) report " integer_cons_vector error in the left generic value" severity error;
assert (V11'left = 15) report " real_cons_vector error in the left generic value" severity error;
assert (V12'left = 15) report " time_cons_vector error in the left generic value" severity error;
assert (V13'left = 15) report " natural_cons_vector error in the left generic value" severity error;
assert (V14'left = 15) report " positive_cons_vector error in the left generic value" severity error;
assert (V15'left = 0) report " boolean_cons_vectorofvector error in the left generic value" severity error;
assert (V16'left = 0) report " severity_level_cons_vectorofvector error in the left generic value" severity error;
assert (V17'left = 0) report " integer_cons_vectorofvector error in the left generic value" severity error;
assert (V18'left = 0) report " real_cons_vectorofvector error in the left generic value" severity error;
assert (V19'left = 0) report " time_cons_vectorofvector error in the left generic value" severity error;
assert (V20'left = 0) report " natural_cons_vectorofvector error in the left generic value" severity error;
assert (V21'left = 0) report " positive_cons_vectorofvector error in the left generic value" severity error;
assert (V22.j'left = 1) report " record_std_package error in the left generic value" severity error;
assert (V22.k'left = 0) report " record_std_package error in the left generic value" severity error;
assert (V23.a'left = 15) report " record_cons_array error in the left generic value" severity error;
assert (V23.b'left = 15) report " record_cons_array error in the left generic value" severity error;
assert (V23.c'left = 15) report " record_cons_array error in the left generic value" severity error;
assert (V23.d'left = 15) report " record_cons_array error in the left generic value" severity error;
assert (V23.e'left = 15) report " record_cons_array error in the left generic value" severity error;
assert (V23.f'left = 15) report " record_cons_array error in the left generic value" severity error;
assert (V23.g'left = 15) report " record_cons_array error in the left generic value" severity error;
assert (V24.a'left = 0) report " record_cons_arrayofarray error in the left generic value" severity error;
assert (V24.b'left = 0) report " record_cons_arrayofarray error in the left generic value" severity error;
assert (V24.c'left = 0) report " record_cons_arrayofarray error in the left generic value" severity error;
assert (V24.d'left = 0) report " record_cons_arrayofarray error in the left generic value" severity error;
assert (V24.e'left = 0) report " record_cons_arrayofarray error in the left generic value" severity error;
assert (V24.f'left = 0) report " record_cons_arrayofarray error in the left generic value" severity error;
assert (V24.g'left = 0) report " record_cons_arrayofarray error in the left generic value" severity error;
assert (V25'left = 0) report " boolean_vector_st error in the left generic value" severity error;
assert (V26'left = 0) report " severity_level_vector_st error in the left generic value" severity error;
assert (V27'left = 0) report " integer_vector_st error in the left generic value" severity error;
assert (V28'left = 0) report " real_vector_st error in the left generic value" severity error;
assert (V29'left = 0) report " time_vector_st error in the left generic value" severity error;
assert (V30'left = 0) report " natural_vector_st error in the left generic value" severity error;
assert (V31'left = 0) report " positive_vector_st error in the left generic value" severity error;
assert (V32.a'left = 0) report " record_array_st error in the left generic value" severity error;
assert (V32.b'left = 0) report " record_array_st error in the left generic value" severity error;
assert (V32.c'left = 0) report " record_array_st error in the left generic value" severity error;
assert (V32.d'left = 0) report " record_array_st error in the left generic value" severity error;
assert (V32.e'left = 0) report " record_array_st error in the left generic value" severity error;
assert (V32.f'left = 0) report " record_array_st error in the left generic value" severity error;
assert (V32.g'left = 0) report " record_array_st error in the left generic value" severity error;
assert (V34.a'left = 0) report " record_array_new error in the left generic value" severity error;
assert (V34.b'left = 0) report " record_array_new error in the left generic value" severity error;
assert (V34.c'left = 0) report " record_array_new error in the left generic value" severity error;
assert (V34.d'left = 0) report " record_array_new error in the left generic value" severity error;
assert (V34.e'left = 0) report " record_array_new error in the left generic value" severity error;
assert (V34.f'left = 0) report " record_array_new error in the left generic value" severity error;
assert (V34.g'left = 0) report " record_array_new error in the left generic value" severity error;
assert (V36'left = 0) report " byte error in the left generic value" severity error;
assert (V37'left = 0) report " word error in the left generic value" severity error;
assert (V38'left = 0) report " current_vector(zero to three) error in the left generic value" severity error;
assert (V39'left = 0) report " resistance_vector(zero to three) error in the left generic value" severity error;
--assert (V40'left = 1) report " delay error in the left generic value" severity error;
assert (V41'left = 0) report " boolean_vector_range error in the left generic value" severity error;
assert (V42'left = 0) report " severity_level_vector_range error in the left generic value" severity error;
assert (V43'left = 0) report " integer_vector_range error in the left generic value" severity error;
assert (V44'left = 0) report " real_vector_range error in the left generic value" severity error;
assert (V45'left = 0) report " time_vector_range error in the left generic value" severity error;
assert (V46'left = 0) report " natural_vector_range error in the left generic value" severity error;
assert (V47'left = 0) report " positive_vector_range error in the left generic value" severity error;
assert (V48'left = 0) report " array_rec_std(zero to seven) error in the left generic value" severity error;
assert (V49'left = 0) report " array_rec_cons(zero to seven) error in the left generic value" severity error;
assert (V50'left = 0) report " array_rec_rec(zero to seven) error in the left generic value" severity error;
assert (V51.a'left = 0) report " record_of_arr_of_record error in the left generic value" severity error;
assert (V51.b'left = 0) report " record_of_arr_of_record error in the left generic value" severity error;
assert (V51.c'left = 0) report " record_of_arr_of_record error in the left generic value" severity error;
assert (V1'right = 15) report " boolean_vector(zero to fifteen) error in the right generic value" severity error;
assert (V2'right = 15) report " severity_level_vector(zero to fifteen) error in the right generic value" severity error;
assert (V3'right = 15) report " integer_vector(zero to fifteen) error in the right generic value" severity error;
assert (V4'right = 15) report " real_vector(zero to fifteen) error in the right generic value" severity error;
assert (V5'right = 15) report " time_vector (zero to fifteen) error in the right generic value" severity error;
assert (V6'right = 15) report " natural_vector(zero to fifteen) error in the right generic value" severity error;
assert (V7'right = 15) report " positive_vector(zero to fifteen) error in the right generic value" severity error;
assert (V8'right = 0) report " boolean_cons_vector error in the right generic value" severity error;
assert (V9'right = 0) report " severity_level_cons_vector error in the right generic value" severity error;
assert (V10'right = 0) report " integer_cons_vector error in the right generic value" severity error;
assert (V11'right = 0) report " real_cons_vector error in the right generic value" severity error;
assert (V12'right = 0) report " time_cons_vector error in the right generic value" severity error;
assert (V13'right = 0) report " natural_cons_vector error in the right generic value" severity error;
assert (V14'right = 0) report " positive_cons_vector error in the right generic value" severity error;
assert (V15'right = 15) report " boolean_cons_vectorofvector error in the right generic value" severity error;
assert (V16'right = 15) report " severity_level_cons_vectorofvector error in the right generic value" severity error;
assert (V17'right = 15) report " integer_cons_vectorofvector error in the right generic value" severity error;
assert (V18'right = 15) report " real_cons_vectorofvector error in the right generic value" severity error;
assert (V19'right = 15) report " time_cons_vectorofvector error in the right generic value" severity error;
assert (V20'right = 15) report " natural_cons_vectorofvector error in the right generic value" severity error;
assert (V21'right = 15) report " positive_cons_vectorofvector error in the right generic value" severity error;
assert (V22.j'right = 7) report " record_std_package error in the right generic value" severity error;
assert (V22.k'right = 3) report " record_std_package error in the right generic value" severity error;
assert (V23.a'right = 0) report " record_cons_array error in the right generic value" severity error;
assert (V23.b'right = 0) report " record_cons_array error in the right generic value" severity error;
assert (V23.c'right = 0) report " record_cons_array error in the right generic value" severity error;
assert (V23.d'right = 0) report " record_cons_array error in the right generic value" severity error;
assert (V23.e'right = 0) report " record_cons_array error in the right generic value" severity error;
assert (V23.f'right = 0) report " record_cons_array error in the right generic value" severity error;
assert (V23.g'right = 0) report " record_cons_array error in the right generic value" severity error;
assert (V24.a'right = 15) report " record_cons_arrayofarray error in the right generic value" severity error;
assert (V24.b'right = 15) report " record_cons_arrayofarray error in the right generic value" severity error;
assert (V24.c'right = 15) report " record_cons_arrayofarray error in the right generic value" severity error;
assert (V24.d'right = 15) report " record_cons_arrayofarray error in the right generic value" severity error;
assert (V24.e'right = 15) report " record_cons_arrayofarray error in the right generic value" severity error;
assert (V24.f'right = 15) report " record_cons_arrayofarray error in the right generic value" severity error;
assert (V24.g'right = 15) report " record_cons_arrayofarray error in the right generic value" severity error;
assert (V25'right = 15) report " boolean_vector_st error in the right generic value" severity error;
assert (V26'right = 15) report " severity_level_vector_st error in the right generic value" severity error;
assert (V27'right = 15) report " integer_vector_st error in the right generic value" severity error;
assert (V28'right = 15) report " real_vector_st error in the right generic value" severity error;
assert (V29'right = 15) report " time_vector_st error in the right generic value" severity error;
assert (V30'right = 15) report " natural_vector_st error in the right generic value" severity error;
assert (V31'right = 15) report " positive_vector_st error in the right generic value" severity error;
assert (V32.a'right = 15) report " record_array_st error in the right generic value" severity error;
assert (V32.b'right = 15) report " record_array_st error in the right generic value" severity error;
assert (V32.c'right = 15) report " record_array_st error in the right generic value" severity error;
assert (V32.d'right = 15) report " record_array_st error in the right generic value" severity error;
assert (V32.e'right = 15) report " record_array_st error in the right generic value" severity error;
assert (V32.f'right = 15) report " record_array_st error in the right generic value" severity error;
assert (V32.g'right = 15) report " record_array_st error in the right generic value" severity error;
assert (V34.a'right = 15) report " record_array_new error in the right generic value" severity error;
assert (V34.b'right = 15) report " record_array_new error in the right generic value" severity error;
assert (V34.c'right = 15) report " record_array_new error in the right generic value" severity error;
assert (V34.d'right = 15) report " record_array_new error in the right generic value" severity error;
assert (V34.e'right = 15) report " record_array_new error in the right generic value" severity error;
assert (V34.f'right = 15) report " record_array_new error in the right generic value" severity error;
assert (V34.g'right = 15) report " record_array_new error in the right generic value" severity error;
assert (V36'right = 7) report " byte error in the right generic value" severity error;
assert (V37'right = 15) report " word error in the right generic value" severity error;
assert (V38'right = 3) report " current_vector(zero to three) error in the right generic value" severity error;
assert (V39'right = 3) report " resistance_vector(zero to three) error in the right generic value" severity error;
--assert (V40'right = 1) report " delay error in the right generic value" severity error;
assert (V41'right = 7) report " boolean_vector_range error in the right generic value" severity error;
assert (V42'right = 7) report " severity_level_vector_range error in the right generic value" severity error;
assert (V43'right = 7) report " integer_vector_range error in the right generic value" severity error;
assert (V44'right = 7) report " real_vector_range error in the right generic value" severity error;
assert (V45'right = 7) report " time_vector_range error in the right generic value" severity error;
assert (V46'right = 7) report " natural_vector_range error in the right generic value" severity error;
assert (V47'right = 7) report " positive_vector_range error in the right generic value" severity error;
assert (V48'right = 7) report " array_rec_std(zero to seven) error in the right generic value" severity error;
assert (V49'right = 7) report " array_rec_cons(zero to seven) error in the right generic value" severity error;
assert (V50'right = 7) report " array_rec_rec(zero to seven) error in the right generic value" severity error;
assert (V51.a'right = 7) report " record_of_arr_of_record error in the right generic value" severity error;
assert (V51.b'right = 7) report " record_of_arr_of_record error in the right generic value" severity error;
assert (V51.c'right = 7) report " record_of_arr_of_record error in the right generic value" severity error;
assert (V1'length = 16) report " boolean_vector(zero to fifteen) error in the length generic value" severity error;
assert (V2'length = 16) report " severity_level_vector(zero to fifteen) error in the length generic value" severity error;
assert (V3'length = 16) report " integer_vector(zero to fifteen) error in the length generic value" severity error;
assert (V4'length = 16) report " real_vector(zero to fifteen) error in the length generic value" severity error;
assert (V5'length = 16) report " time_vector (zero to fifteen) error in the length generic value" severity error;
assert (V6'length = 16) report " natural_vector(zero to fifteen) error in the length generic value" severity error;
assert (V7'length = 16) report " positive_vector(zero to fifteen) error in the length generic value" severity error;
assert (V8'length = 16) report " boolean_cons_vector error in the length generic value" severity error;
assert (V9'length = 16) report " severity_level_cons_vector error in the length generic value" severity error;
assert (V10'length = 16) report " integer_cons_vector error in the length generic value" severity error;
assert (V11'length = 16) report " real_cons_vector error in the length generic value" severity error;
assert (V12'length = 16) report " time_cons_vector error in the length generic value" severity error;
assert (V13'length = 16) report " natural_cons_vector error in the length generic value" severity error;
assert (V14'length = 16) report " positive_cons_vector error in the length generic value" severity error;
assert (V15'length = 16) report " boolean_cons_vectorofvector error in the length generic value" severity error;
assert (V16'length = 16) report " severity_level_cons_vectorofvector error in the length generic value" severity error;
assert (V17'length = 16) report " integer_cons_vectorofvector error in the length generic value" severity error;
assert (V18'length = 16) report " real_cons_vectorofvector error in the length generic value" severity error;
assert (V19'length = 16) report " time_cons_vectorofvector error in the length generic value" severity error;
assert (V20'length = 16) report " natural_cons_vectorofvector error in the length generic value" severity error;
assert (V21'length = 16) report " positive_cons_vectorofvector error in the length generic value" severity error;
assert (V22.j'length = 7) report " record_std_package error in the length generic value" severity error;
assert (V22.k'length = 4) report " record_std_package error in the length generic value" severity error;
assert (V23.a'length = 16) report " record_cons_array error in the length generic value" severity error;
assert (V23.b'length = 16) report " record_cons_array error in the length generic value" severity error;
assert (V23.c'length = 16) report " record_cons_array error in the length generic value" severity error;
assert (V23.d'length = 16) report " record_cons_array error in the length generic value" severity error;
assert (V23.e'length = 16) report " record_cons_array error in the length generic value" severity error;
assert (V23.f'length = 16) report " record_cons_array error in the length generic value" severity error;
assert (V23.g'length = 16) report " record_cons_array error in the length generic value" severity error;
assert (V24.a'length = 16) report " record_cons_arrayofarray error in the length generic value" severity error;
assert (V24.b'length = 16) report " record_cons_arrayofarray error in the length generic value" severity error;
assert (V24.c'length = 16) report " record_cons_arrayofarray error in the length generic value" severity error;
assert (V24.d'length = 16) report " record_cons_arrayofarray error in the length generic value" severity error;
assert (V24.e'length = 16) report " record_cons_arrayofarray error in the length generic value" severity error;
assert (V24.f'length = 16) report " record_cons_arrayofarray error in the length generic value" severity error;
assert (V24.g'length = 16) report " record_cons_arrayofarray error in the length generic value" severity error;
assert (V25'length = 16) report " boolean_vector_st error in the length generic value" severity error;
assert (V26'length = 16) report " severity_level_vector_st error in the length generic value" severity error;
assert (V27'length = 16) report " integer_vector_st error in the length generic value" severity error;
assert (V28'length = 16) report " real_vector_st error in the length generic value" severity error;
assert (V29'length = 16) report " time_vector_st error in the length generic value" severity error;
assert (V30'length = 16) report " natural_vector_st error in the length generic value" severity error;
assert (V31'length = 16) report " positive_vector_st error in the length generic value" severity error;
assert (V32.a'length = 16) report " record_array_st error in the length generic value" severity error;
assert (V32.b'length = 16) report " record_array_st error in the length generic value" severity error;
assert (V32.c'length = 16) report " record_array_st error in the length generic value" severity error;
assert (V32.d'length = 16) report " record_array_st error in the length generic value" severity error;
assert (V32.e'length = 16) report " record_array_st error in the length generic value" severity error;
assert (V32.f'length = 16) report " record_array_st error in the length generic value" severity error;
assert (V32.g'length = 16) report " record_array_st error in the length generic value" severity error;
assert (V34.a'length = 16) report " record_array_new error in the length generic value" severity error;
assert (V34.b'length = 16) report " record_array_new error in the length generic value" severity error;
assert (V34.c'length = 16) report " record_array_new error in the length generic value" severity error;
assert (V34.d'length = 16) report " record_array_new error in the length generic value" severity error;
assert (V34.e'length = 16) report " record_array_new error in the length generic value" severity error;
assert (V34.f'length = 16) report " record_array_new error in the length generic value" severity error;
assert (V34.g'length = 16) report " record_array_new error in the length generic value" severity error;
assert (V36'length = 8) report " byte error in the length generic value" severity error;
assert (V37'length = 16) report " word error in the length generic value" severity error;
assert (V38'length = 4) report " current_vector(zero to three) error in the length generic value" severity error;
assert (V39'length = 4) report " resistance_vector(zero to three) error in the length generic value" severity error;
--assert (V40'length = 1) report " delay error in the length generic value" severity error;
assert (V41'length = 8) report " boolean_vector_range error in the length generic value" severity error;
assert (V42'length = 8) report " severity_level_vector_range error in the length generic value" severity error;
assert (V43'length = 8) report " integer_vector_range error in the length generic value" severity error;
assert (V44'length = 8) report " real_vector_range error in the length generic value" severity error;
assert (V45'length = 8) report " time_vector_range error in the length generic value" severity error;
assert (V46'length = 8) report " natural_vector_range error in the length generic value" severity error;
assert (V48'length = 8) report " positive_vector_range error in the length generic value" severity error;
assert (V48'length = 8) report " array_rec_std(zero to seven) error in the length generic value" severity error;
assert (V49'length = 8) report " array_rec_cons(zero to seven) error in the length generic value" severity error;
assert (V50'length = 8) report " array_rec_rec(zero to seven) error in the length generic value" severity error;
assert (V51.a'length = 8) report " record_of_arr_of_record error in the length generic value" severity error;
assert (V51.b'length = 8) report " record_of_arr_of_record error in the length generic value" severity error;
assert (V51.c'length = 8) report " record_of_arr_of_record error in the length generic value" severity error;
assert NOT( (V1'left = 0) and
(V2'left = 0) and
(V3'left = 0) and
(V4'left = 0) and
(V5'left = 0) and
(V6'left = 0) and
(V7'left = 0) and
(V8'left = 15) and
(V9'left = 15) and
(V10'left = 15) and
(V11'left = 15) and
(V12'left = 15) and
(V13'left = 15) and
(V14'left = 15) and
(V15'left = 0) and
(V16'left = 0) and
(V17'left = 0) and
(V18'left = 0) and
(V19'left = 0) and
(V20'left = 0) and
(V21'left = 0) and
(V22.j'left = 1) and
(V22.k'left = 0) and
(V23.a'left = 15) and
(V23.b'left = 15) and
(V23.c'left = 15) and
(V23.d'left = 15) and
(V23.e'left = 15) and
(V23.f'left = 15) and
(V23.g'left = 15) and
(V24.a'left = 0) and
(V24.b'left = 0) and
(V24.c'left = 0) and
(V24.d'left = 0) and
(V24.e'left = 0) and
(V24.f'left = 0) and
(V24.g'left = 0) and
(V25'left = 0) and
(V26'left = 0) and
(V27'left = 0) and
(V28'left = 0) and
(V29'left = 0) and
(V30'left = 0) and
(V31'left = 0) and
(V32.a'left = 0) and
(V32.b'left = 0) and
(V32.c'left = 0) and
(V32.d'left = 0) and
(V32.e'left = 0) and
(V32.f'left = 0) and
(V32.g'left = 0) and
(V34.a'left = 0) and
(V34.b'left = 0) and
(V34.c'left = 0) and
(V34.d'left = 0) and
(V34.e'left = 0) and
(V34.f'left = 0) and
(V34.g'left = 0) and
(V36'left = 0) and
(V37'left = 0) and
(V38'left = 0) and
(V39'left = 0) and
-- (V40'left = 1) and
(V42'left = 0) and
(V43'left = 0) and
(V44'left = 0) and
(V45'left = 0) and
(V46'left = 0) and
(V47'left = 0) and
(V48'left = 0) and
(V49'left = 0) and
(V50'left = 0) and
(V51.a'left = 0) and
(V51.b'left = 0) and
(V51.c'left = 0) and
(V1'right = 15) and
(V2'right = 15) and
(V3'right = 15) and
(V4'right = 15) and
(V5'right = 15) and
(V6'right = 15) and
(V7'right = 15) and
(V8'right = 0) and
(V9'right = 0) and
(V10'right = 0)and
(V11'right = 0) and
(V12'right = 0) and
(V13'right = 0) and
(V14'right = 0) and
(V15'right = 15) and
(V16'right = 15) and
(V17'right = 15) and
(V18'right = 15) and
(V19'right = 15) and
(V20'right = 15) and
(V21'right = 15) and
(V22.j'right = 7) and
(V22.k'right = 3) and
(V23.a'right = 0) and
(V23.b'right = 0) and
(V23.c'right = 0) and
(V23.d'right = 0) and
(V23.e'right = 0) and
(V23.f'right = 0) and
(V23.g'right = 0) and
(V24.a'right = 15) and
(V24.b'right = 15) and
(V24.c'right = 15) and
(V24.d'right = 15) and
(V24.e'right = 15) and
(V24.f'right = 15) and
(V24.g'right = 15) and
(V25'right = 15) and
(V26'right = 15) and
(V27'right = 15) and
(V28'right = 15) and
(V29'right = 15) and
(V30'right = 15) and
(V31'right = 15) and
(V32.a'right = 15) and
(V32.b'right = 15) and
(V32.c'right = 15) and
(V32.d'right = 15) and
(V32.e'right = 15) and
(V32.f'right = 15) and
(V32.g'right = 15) and
(V34.a'right = 15) and
(V34.b'right = 15) and
(V34.c'right = 15) and
(V34.d'right = 15) and
(V34.e'right = 15) and
(V34.f'right = 15) and
(V34.g'right = 15) and
(V36'right = 7) and
(V37'right = 15) and
(V38'right = 3) and
(V39'right = 3) and
-- (V40'right = 1) and
(V41'right = 7) and
(V42'right = 7) and
(V43'right = 7) and
(V44'right = 7) and
(V45'right = 7) and
(V46'right = 7) and
(V47'right = 7) and
(V48'right = 7) and
(V49'right = 7) and
(V50'right = 7) and
(V51.a'right = 7) and
(V51.b'right = 7) and
(V51.c'right = 7) and
(V1'length = 16) and
(V2'length = 16) and
(V3'length = 16) and
(V4'length = 16) and
(V5'length = 16) and
(V6'length = 16) and
(V7'length = 16) and
(V8'length = 16) and
(V9'length = 16) and
(V10'length = 16) and
(V11'length = 16) and
(V12'length = 16) and
(V13'length = 16) and
(V14'length = 16) and
(V15'length = 16) and
(V16'length = 16) and
(V17'length = 16) and
(V18'length = 16) and
(V19'length = 16) and
(V20'length = 16) and
(V21'length = 16) and
(V22.j'length = 7)and
(V22.k'length = 4) and
(V23.a'length = 16) and
(V23.b'length = 16) and
(V23.c'length = 16) and
(V23.d'length = 16) and
(V23.e'length = 16) and
(V23.f'length = 16) and
(V23.g'length = 16) and
(V24.a'length = 16) and
(V24.b'length = 16) and
(V24.c'length = 16) and
(V24.d'length = 16) and
(V24.e'length = 16) and
(V24.f'length = 16) and
(V24.g'length = 16) and
(V25'length = 16) and
(V26'length = 16) and
(V27'length = 16) and
(V28'length = 16) and
(V29'length = 16) and
(V30'length = 16) and
(V31'length = 16) and
(V32.a'length = 16) and
(V32.b'length = 16) and
(V32.c'length = 16) and
(V32.d'length = 16) and
(V32.e'length = 16) and
(V32.f'length = 16) and
(V32.g'length = 16) and
(V34.a'length = 16) and
(V34.b'length = 16) and
(V34.c'length = 16) and
(V34.d'length = 16) and
(V34.e'length = 16) and
(V34.f'length = 16) and
(V34.g'length = 16) and
(V36'length = 8) and
(V37'length = 16) and
(V38'length = 4) and
(V39'length = 4) and
-- (V40'length = 1) and
(V41'length = 8) and
(V42'length = 8) and
(V43'length = 8) and
(V44'length = 8) and
(V45'length = 8) and
(V46'length = 8) and
(V48'length = 8) and
(V48'length = 8) and
(V49'length = 8) and
(V50'length = 8) and
(V51.a'length = 8) and
(V51.b'length = 8) and
(V51.c'length = 8) )
report "***PASSED TEST: c01s01b01x01p05n02i00756"
severity NOTE;
assert ((V1'left = 0) and
(V2'left = 0) and
(V3'left = 0) and
(V4'left = 0) and
(V5'left = 0) and
(V6'left = 0) and
(V7'left = 0) and
(V8'left = 15) and
(V9'left = 15) and
(V10'left = 15) and
(V11'left = 15) and
(V12'left = 15) and
(V13'left = 15) and
(V14'left = 15) and
(V15'left = 0) and
(V16'left = 0) and
(V17'left = 0) and
(V18'left = 0) and
(V19'left = 0) and
(V20'left = 0) and
(V21'left = 0) and
(V22.j'left = 1) and
(V22.k'left = 0) and
(V23.a'left = 15) and
(V23.b'left = 15) and
(V23.c'left = 15) and
(V23.d'left = 15) and
(V23.e'left = 15) and
(V23.f'left = 15) and
(V23.g'left = 15) and
(V24.a'left = 0) and
(V24.b'left = 0) and
(V24.c'left = 0) and
(V24.d'left = 0) and
(V24.e'left = 0) and
(V24.f'left = 0) and
(V24.g'left = 0) and
(V25'left = 0) and
(V26'left = 0) and
(V27'left = 0) and
(V28'left = 0) and
(V29'left = 0) and
(V30'left = 0) and
(V31'left = 0) and
(V32.a'left = 0) and
(V32.b'left = 0) and
(V32.c'left = 0) and
(V32.d'left = 0) and
(V32.e'left = 0) and
(V32.f'left = 0) and
(V32.g'left = 0) and
(V34.a'left = 0) and
(V34.b'left = 0) and
(V34.c'left = 0) and
(V34.d'left = 0) and
(V34.e'left = 0) and
(V34.f'left = 0) and
(V34.g'left = 0) and
(V36'left = 0) and
(V37'left = 0) and
(V38'left = 0) and
(V39'left = 0) and
-- (V40'left = 1) and
(V42'left = 0) and
(V43'left = 0) and
(V44'left = 0) and
(V45'left = 0) and
(V46'left = 0) and
(V47'left = 0) and
(V48'left = 0) and
(V49'left = 0) and
(V50'left = 0) and
(V51.a'left = 0) and
(V51.b'left = 0) and
(V51.c'left = 0) and
(V1'right = 15) and
(V2'right = 15) and
(V3'right = 15) and
(V4'right = 15) and
(V5'right = 15) and
(V6'right = 15) and
(V7'right = 15) and
(V8'right = 0) and
(V9'right = 0) and
(V10'right = 0)and
(V11'right = 0) and
(V12'right = 0) and
(V13'right = 0) and
(V14'right = 0) and
(V15'right = 15) and
(V16'right = 15) and
(V17'right = 15) and
(V18'right = 15) and
(V19'right = 15) and
(V20'right = 15) and
(V21'right = 15) and
(V22.j'right = 7) and
(V22.k'right = 3) and
(V23.a'right = 0) and
(V23.b'right = 0) and
(V23.c'right = 0) and
(V23.d'right = 0) and
(V23.e'right = 0) and
(V23.f'right = 0) and
(V23.g'right = 0) and
(V24.a'right = 15) and
(V24.b'right = 15) and
(V24.c'right = 15) and
(V24.d'right = 15) and
(V24.e'right = 15) and
(V24.f'right = 15) and
(V24.g'right = 15) and
(V25'right = 15) and
(V26'right = 15) and
(V27'right = 15) and
(V28'right = 15) and
(V29'right = 15) and
(V30'right = 15) and
(V31'right = 15) and
(V32.a'right = 15) and
(V32.b'right = 15) and
(V32.c'right = 15) and
(V32.d'right = 15) and
(V32.e'right = 15) and
(V32.f'right = 15) and
(V32.g'right = 15) and
(V34.a'right = 15) and
(V34.b'right = 15) and
(V34.c'right = 15) and
(V34.d'right = 15) and
(V34.e'right = 15) and
(V34.f'right = 15) and
(V34.g'right = 15) and
(V36'right = 7) and
(V37'right = 15) and
(V38'right = 3) and
(V39'right = 3) and
-- (V40'right = 1) and
(V41'right = 7) and
(V42'right = 7) and
(V43'right = 7) and
(V44'right = 7) and
(V45'right = 7) and
(V46'right = 7) and
(V47'right = 7) and
(V48'right = 7) and
(V49'right = 7) and
(V50'right = 7) and
(V51.a'right = 7) and
(V51.b'right = 7) and
(V51.c'right = 7) and
(V1'length = 16) and
(V2'length = 16) and
(V3'length = 16) and
(V4'length = 16) and
(V5'length = 16) and
(V6'length = 16) and
(V7'length = 16) and
(V8'length = 16) and
(V9'length = 16) and
(V10'length = 16) and
(V11'length = 16) and
(V12'length = 16) and
(V13'length = 16) and
(V14'length = 16) and
(V15'length = 16) and
(V16'length = 16) and
(V17'length = 16) and
(V18'length = 16) and
(V19'length = 16) and
(V20'length = 16) and
(V21'length = 16) and
(V22.j'length = 7)and
(V22.k'length = 4) and
(V23.a'length = 16) and
(V23.b'length = 16) and
(V23.c'length = 16) and
(V23.d'length = 16) and
(V23.e'length = 16) and
(V23.f'length = 16) and
(V23.g'length = 16) and
(V24.a'length = 16) and
(V24.b'length = 16) and
(V24.c'length = 16) and
(V24.d'length = 16) and
(V24.e'length = 16) and
(V24.f'length = 16) and
(V24.g'length = 16) and
(V25'length = 16) and
(V26'length = 16) and
(V27'length = 16) and
(V28'length = 16) and
(V29'length = 16) and
(V30'length = 16) and
(V31'length = 16) and
(V32.a'length = 16) and
(V32.b'length = 16) and
(V32.c'length = 16) and
(V32.d'length = 16) and
(V32.e'length = 16) and
(V32.f'length = 16) and
(V32.g'length = 16) and
(V34.a'length = 16) and
(V34.b'length = 16) and
(V34.c'length = 16) and
(V34.d'length = 16) and
(V34.e'length = 16) and
(V34.f'length = 16) and
(V34.g'length = 16) and
(V36'length = 8) and
(V37'length = 16) and
(V38'length = 4) and
(V39'length = 4) and
-- (V40'length = 1) and
(V41'length = 8) and
(V42'length = 8) and
(V43'length = 8) and
(V44'length = 8) and
(V45'length = 8) and
(V46'length = 8) and
(V48'length = 8) and
(V48'length = 8) and
(V49'length = 8) and
(V50'length = 8) and
(V51.a'length = 8) and
(V51.b'length = 8) and
(V51.c'length = 8) )
report "***FAILED TEST: c01s01b01x01p05n02i00756 - Generic can be used to specify the size of ports."
severity ERROR;
wait;
END PROCESS TESTING;
END c01s01b01x01p05n02i00756arch;
| gpl-2.0 | 57442e235f5e5ec4e503b12e23fb2dae | 0.566432 | 3.706644 | false | false | false | false |
rafa-jfet/OFM | ARCHIVOS VHDL/TX_OFDM.vhd | 1 | 10,785 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 14:51:35 06/30/2015
-- Design Name:
-- Module Name: TX_OFDM - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity TX_OFDM is
Generic ( BUS_DIR_ROM : integer := 6
);
Port ( clk : in STD_LOGIC;
reset : in STD_LOGIC;
button : in STD_LOGIC;
modulation : in STD_LOGIC_VECTOR (2 downto 0);
-- bit_in : in std_logic;
-- ok_bit_in : in std_logic;
-- fin_rx : in std_logic;
-- dir_out : in STD_LOGIC_VECTOR (8 downto 0);
bit_out : out STD_LOGIC
-- EnableTXserie : out STD_LOGIC
);
end TX_OFDM;
architecture Behavioral of TX_OFDM is
-- señales de salida correspondientes al divisor de frecuencia
signal sat_div : STD_LOGIC;
-- señales de salida correspondientes al mux de memoria
signal bit_mem_enc, ok_bit_mem_enc, fin_mem_enc : STD_LOGIC;
signal data_read : STD_LOGIC_VECTOR (7 downto 0);
signal dir_read : STD_LOGIC_VECTOR (BUS_DIR_ROM -1 downto 0);
-- señales de salida correspondientes al convolutional encoder
signal first_bit_enc_scr, second_bit_enc_scr, ok_bit_enc_scr, fin_enc_scr : STD_LOGIC;
-- señales de salida correspondientes al scrambler
signal bit_scr_intlv, ok_bit_scr_intlv : STD_LOGIC;
-- señales de salida correspondientes al interleaver
signal bit_intlv_map : STD_LOGIC_VECTOR (0 downto 0);
signal ok_bit_intlv_map : STD_LOGIC;
-- señales de salida correspondientes al mapper
signal write_map_ifftmem : STD_LOGIC_VECTOR (0 downto 0);
signal dir_map_ifftmem : STD_LOGIC_VECTOR (6 downto 0);
signal data_map_ifftmem : STD_LOGIC_VECTOR (15 downto 0);
signal ok_data_map_ifft : STD_LOGIC;
-- señales de salida correspondientes a la memoria mapper > IFFT
signal data_mem_ifft : STD_LOGIC_VECTOR (15 downto 0);
-- señales de salida correspondientes a la IFFT
signal dir_ifft_mem : STD_LOGIC_VECTOR (6 downto 0);
signal dir_ifft_memTX : STD_LOGIC_VECTOR (8 downto 0);
signal EnableTXserie : STD_LOGIC;
signal datos_ifft_memTX : STD_LOGIC_VECTOR (31 downto 0);
signal write_ifft_memTX : STD_LOGIC_VECTOR (0 downto 0);
-- señales de salida correspondientes a la memoria de salida
signal data_mem_TXserie : std_logic_vector (31 downto 0);
-- señales de salida correspondientes al transmisor serie
signal dir_TXserie_mem : std_logic_vector (8 downto 0);
component miBlockRAM IS
PORT (
clka : IN STD_LOGIC;
addra : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END component;
component mem_read is
Generic ( ancho_bus_direcc : integer := 6;
TAM_BYTE : integer := 8;
bit_DBPSK : integer := 48;
bit_DQPSK : integer := 96;
bit_D8PSK : integer := 144);
Port ( clk : in STD_LOGIC;
reset : in STD_LOGIC;
button : in STD_LOGIC;
data : in STD_LOGIC_VECTOR (7 downto 0);
modulation : in STD_LOGIC_VECTOR (2 downto 0);
sat : in STD_LOGIC;
direcc : out STD_LOGIC_VECTOR (ancho_bus_direcc -1 downto 0);
bit_out : out STD_LOGIC;
ok_bit_out : out STD_LOGIC;
fin : out STD_LOGIC);
end component;
component div_frec is
Generic ( SAT_BPSK : integer := 30;
SAT_QPSK : integer := 20;
SAT_8PSK : integer := 10 );
Port ( clk : in STD_LOGIC;
reset : in STD_LOGIC;
button : in STD_LOGIC;
modulation : in STD_LOGIC_VECTOR (2 downto 0);
sat : out STD_LOGIC);
end component;
component convolutional_encoder is
Generic ( TAM_REG : integer := 7;
SAT_ESPERA : integer := 2);
Port ( clk : in STD_LOGIC;
reset : in STD_LOGIC;
button : in STD_LOGIC;
bit_in : in STD_LOGIC;
ok_bit_in : in STD_LOGIC;
fin_rx : in STD_LOGIC;
sat : in STD_LOGIC;
first_bit_out : out STD_LOGIC;
second_bit_out : out STD_LOGIC;
ok_bit_out : out STD_LOGIC;
fin_tx : out STD_LOGIC);
end component;
component scrambler is
Generic ( SAT_ESPERA : integer := 7);
Port ( clk : in STD_LOGIC;
reset : in STD_LOGIC;
button : in STD_LOGIC;
first_in : in STD_LOGIC;
second_in : in STD_LOGIC;
fin_rx : in STD_LOGIC;
ok_bit_in : in STD_LOGIC;
bit_out : out STD_LOGIC;
ok_bit_out : out STD_LOGIC);
end component;
component intlv_completo is
Port ( clk : in STD_LOGIC;
reset : in STD_LOGIC;
button : in STD_LOGIC;
modulation : in STD_LOGIC_VECTOR (2 downto 0);
bit_in : in STD_LOGIC;
ok_bit_in : in STD_LOGIC;
bit_out : out STD_LOGIC_VECTOR (0 downto 0);
ok_bit_out : out STD_LOGIC);
end component;
component mapper_completo is
Port ( clk : in STD_LOGIC;
reset : in STD_LOGIC;
bit_in : in STD_LOGIC_VECTOR ( 0 downto 0);
ok_bit_in : in STD_LOGIC;
modulation : in STD_LOGIC_VECTOR (2 downto 0);
dir_data : out STD_LOGIC_VECTOR (6 downto 0);
write_data : out STD_LOGIC_VECTOR (0 downto 0);
data_out : out STD_LOGIC_VECTOR (15 downto 0);
ok_data : out STD_LOGIC);
end component;
component mem_ifft IS
PORT (
clka : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(6 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
clkb : IN STD_LOGIC;
addrb : IN STD_LOGIC_VECTOR(6 DOWNTO 0);
doutb : OUT STD_LOGIC_VECTOR(15 DOWNTO 0)
);
END component;
component IFFT_completa is
Port (
clk : in STD_LOGIC;
data_in : in STD_LOGIC_VECTOR (15 downto 0);
address_read : out STD_LOGIC_VECTOR(6 downto 0);
IfftEnable : in STD_LOGIC;
reset : in STD_LOGIC;
address_write : out STD_LOGIC_VECTOR(8 downto 0);
EnableTxserie : out STD_LOGIC;
datos_salida : out STD_LOGIC_VECTOR(31 downto 0);
we : out STD_LOGIC );
end component;
component memTX IS
PORT (
clka : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
clkb : IN STD_LOGIC;
addrb : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
doutb : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END component;
component FSM is
Generic (ancho_bus_dir:integer:=9;
VAL_SAT_CONT:integer:=5208;
ANCHO_CONTADOR:integer:=13;
ULT_DIR_TX : integer := 420);
Port ( clk : in STD_LOGIC;
reset : in STD_LOGIC;
button : in STD_LOGIC;
data_in : in STD_LOGIC_VECTOR(31 downto 0);
direcc : out STD_LOGIC_VECTOR (ancho_bus_dir -1 downto 0);
TX : out STD_LOGIC);
end component;
begin
memoria : miBlockRAM
PORT map(
clka => clk,
addra => dir_read,
douta => data_read
);
mux8a1 : mem_read
Generic map ( ancho_bus_direcc => BUS_DIR_ROM,
TAM_BYTE => 8,
bit_DBPSK => 48,
bit_DQPSK => 96,
bit_D8PSK => 144)
Port map ( clk => clk,
reset => reset,
button => button,
data => data_read, --
modulation => modulation,
sat => sat_div,
direcc => dir_read, --
bit_out => bit_mem_enc, --
ok_bit_out => ok_bit_mem_enc, --
fin => fin_mem_enc); --
divisor_frecuencia : div_frec
Generic map ( SAT_BPSK => 2333,
SAT_QPSK => 1167,
SAT_8PSK => 778 )
Port map ( clk => clk,
reset => reset,
button => button,
modulation => modulation,
sat => sat_div);
conv_encoder : convolutional_encoder
Generic map ( TAM_REG => 7,
SAT_ESPERA => 2)
Port map ( clk => clk,
reset => reset,
button => button,
bit_in => bit_mem_enc, --
ok_bit_in => ok_bit_mem_enc, --
fin_rx => fin_mem_enc, --
sat => sat_div,
first_bit_out => first_bit_enc_scr, --
second_bit_out => second_bit_enc_scr, --
ok_bit_out => ok_bit_enc_scr, --
fin_tx => fin_enc_scr); --
scr : scrambler
Generic map ( SAT_ESPERA => 7)
Port map ( clk => clk,
reset => reset,
button => button,
first_in => first_bit_enc_scr, --
second_in => second_bit_enc_scr, --
fin_rx => fin_enc_scr, --
ok_bit_in => ok_bit_enc_scr, --
bit_out => bit_scr_intlv, --
ok_bit_out => ok_bit_scr_intlv);
interleaver : intlv_completo
Port map ( clk => clk,
reset => reset,
button => button,
modulation => modulation,
bit_in => bit_scr_intlv, --
ok_bit_in => ok_bit_scr_intlv, --
bit_out => bit_intlv_map, --
ok_bit_out => ok_bit_intlv_map); --
mapp_comp : mapper_completo
Port map ( clk => clk,
reset => reset,
bit_in => bit_intlv_map, --
ok_bit_in => ok_bit_intlv_map, --
modulation => modulation,
dir_data => dir_map_ifftmem, --
write_data => write_map_ifftmem, --
data_out => data_map_ifftmem, --
ok_data => ok_data_map_ifft); --
memory_ifft : mem_ifft
PORT map (
clka => clk,
wea => write_map_ifftmem, --
addra => dir_map_ifftmem, --
dina => data_map_ifftmem, --
clkb => clk,
addrb => dir_ifft_mem, --
doutb => data_mem_ifft --
);
IFFT : IFFT_completa
Port map (
clk => clk,
data_in => data_mem_ifft, --
address_read => dir_ifft_mem, --
IfftEnable => ok_data_map_ifft, --
reset => reset,
address_write => dir_ifft_memTX, --
EnableTxserie => EnableTXserie,
datos_salida => datos_ifft_memTX, --
we => write_ifft_memTX(0) --
);
memoria_tx : memTX
PORT MAP(
clka => clk,
wea => write_ifft_memTX, --
addra => dir_ifft_memTX, --
dina => datos_ifft_memTX, --
clkb => clk,
addrb => dir_TXserie_mem, --
doutb => data_mem_TXserie --
);
tx_serie : FSM
Generic map (ancho_bus_dir => 9,
VAL_SAT_CONT => 5208,
ANCHO_CONTADOR => 13,
ULT_DIR_TX => 420) -- transmision de 3 simbolos
Port map ( clk => clk,
reset => reset,
button => EnableTXserie, --
data_in => data_mem_TXserie, --
direcc => dir_TXserie_mem, --
TX => bit_out);
end Behavioral;
| gpl-3.0 | 354cd4764a284215f1f8256dcde5ba75 | 0.580529 | 3.155354 | false | false | false | false |
pmh92/Proyecto-OFDM | ipcore_dir/DIVIDER.vhd | 1 | 903,970 | --------------------------------------------------------------------------------
-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
--------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version: P.20131013
-- \ \ Application: netgen
-- / / Filename: DIVIDER.vhd
-- /___/ /\ Timestamp: Fri Jul 10 19:32:18 2015
-- \ \ / \
-- \___\/\___\
--
-- Command : -intstyle ise -w -sim -ofmt vhdl ./tmp/_cg/DIVIDER.ngc ./tmp/_cg/DIVIDER.vhd
-- Device : 6slx9csg324-3
-- Input file : ./tmp/_cg/DIVIDER.ngc
-- Output file : ./tmp/_cg/DIVIDER.vhd
-- # of Entities : 1
-- Design Name : DIVIDER
-- Xilinx : /opt/Xilinx/14.7/ISE_DS/ISE/
--
-- Purpose:
-- This VHDL netlist is a verification model and uses simulation
-- primitives which may not represent the true implementation of the
-- device, however the netlist is functionally correct and should not
-- be modified. This file cannot be synthesized and should only be used
-- with supported simulation tools.
--
-- Reference:
-- Command Line Tools User Guide, Chapter 23
-- Synthesis and Simulation Design Guide, Chapter 6
--
--------------------------------------------------------------------------------
-- synthesis translate_off
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
use UNISIM.VPKG.ALL;
entity DIVIDER is
port (
rfd : out STD_LOGIC;
clk : in STD_LOGIC := 'X';
dividend : in STD_LOGIC_VECTOR ( 23 downto 0 );
quotient : out STD_LOGIC_VECTOR ( 23 downto 0 );
divisor : in STD_LOGIC_VECTOR ( 23 downto 0 );
fractional : out STD_LOGIC_VECTOR ( 23 downto 0 )
);
end DIVIDER;
architecture STRUCTURE of DIVIDER is
signal NlwRenamedSig_OI_rfd : STD_LOGIC;
signal blk00000003_sig00000f09 : STD_LOGIC;
signal blk00000003_sig00000f08 : STD_LOGIC;
signal blk00000003_sig00000f07 : STD_LOGIC;
signal blk00000003_sig00000f06 : STD_LOGIC;
signal blk00000003_sig00000f05 : STD_LOGIC;
signal blk00000003_sig00000f04 : STD_LOGIC;
signal blk00000003_sig00000f03 : STD_LOGIC;
signal blk00000003_sig00000f02 : STD_LOGIC;
signal blk00000003_sig00000f01 : STD_LOGIC;
signal blk00000003_sig00000f00 : STD_LOGIC;
signal blk00000003_sig00000eff : STD_LOGIC;
signal blk00000003_sig00000efe : STD_LOGIC;
signal blk00000003_sig00000efd : STD_LOGIC;
signal blk00000003_sig00000efc : STD_LOGIC;
signal blk00000003_sig00000efb : STD_LOGIC;
signal blk00000003_sig00000efa : STD_LOGIC;
signal blk00000003_sig00000ef9 : STD_LOGIC;
signal blk00000003_sig00000ef8 : STD_LOGIC;
signal blk00000003_sig00000ef7 : STD_LOGIC;
signal blk00000003_sig00000ef6 : STD_LOGIC;
signal blk00000003_sig00000ef5 : STD_LOGIC;
signal blk00000003_sig00000ef4 : STD_LOGIC;
signal blk00000003_sig00000ef3 : STD_LOGIC;
signal blk00000003_sig00000ef2 : STD_LOGIC;
signal blk00000003_sig00000ef1 : STD_LOGIC;
signal blk00000003_sig00000ef0 : STD_LOGIC;
signal blk00000003_sig00000eef : STD_LOGIC;
signal blk00000003_sig00000eee : STD_LOGIC;
signal blk00000003_sig00000eed : STD_LOGIC;
signal blk00000003_sig00000eec : STD_LOGIC;
signal blk00000003_sig00000eeb : STD_LOGIC;
signal blk00000003_sig00000eea : STD_LOGIC;
signal blk00000003_sig00000ee9 : STD_LOGIC;
signal blk00000003_sig00000ee8 : STD_LOGIC;
signal blk00000003_sig00000ee7 : STD_LOGIC;
signal blk00000003_sig00000ee6 : STD_LOGIC;
signal blk00000003_sig00000ee5 : STD_LOGIC;
signal blk00000003_sig00000ee4 : STD_LOGIC;
signal blk00000003_sig00000ee3 : STD_LOGIC;
signal blk00000003_sig00000ee2 : STD_LOGIC;
signal blk00000003_sig00000ee1 : STD_LOGIC;
signal blk00000003_sig00000ee0 : STD_LOGIC;
signal blk00000003_sig00000edf : STD_LOGIC;
signal blk00000003_sig00000ede : STD_LOGIC;
signal blk00000003_sig00000edd : STD_LOGIC;
signal blk00000003_sig00000edc : STD_LOGIC;
signal blk00000003_sig00000edb : STD_LOGIC;
signal blk00000003_sig00000eda : STD_LOGIC;
signal blk00000003_sig00000ed9 : STD_LOGIC;
signal blk00000003_sig00000ed8 : STD_LOGIC;
signal blk00000003_sig00000ed7 : STD_LOGIC;
signal blk00000003_sig00000ed6 : STD_LOGIC;
signal blk00000003_sig00000ed5 : STD_LOGIC;
signal blk00000003_sig00000ed4 : STD_LOGIC;
signal blk00000003_sig00000ed3 : STD_LOGIC;
signal blk00000003_sig00000ed2 : STD_LOGIC;
signal blk00000003_sig00000ed1 : STD_LOGIC;
signal blk00000003_sig00000ed0 : STD_LOGIC;
signal blk00000003_sig00000ecf : STD_LOGIC;
signal blk00000003_sig00000ece : STD_LOGIC;
signal blk00000003_sig00000ecd : STD_LOGIC;
signal blk00000003_sig00000ecc : STD_LOGIC;
signal blk00000003_sig00000ecb : STD_LOGIC;
signal blk00000003_sig00000eca : STD_LOGIC;
signal blk00000003_sig00000ec9 : STD_LOGIC;
signal blk00000003_sig00000ec8 : STD_LOGIC;
signal blk00000003_sig00000ec7 : STD_LOGIC;
signal blk00000003_sig00000ec6 : STD_LOGIC;
signal blk00000003_sig00000ec5 : STD_LOGIC;
signal blk00000003_sig00000ec4 : STD_LOGIC;
signal blk00000003_sig00000ec3 : STD_LOGIC;
signal blk00000003_sig00000ec2 : STD_LOGIC;
signal blk00000003_sig00000ec1 : STD_LOGIC;
signal blk00000003_sig00000ec0 : STD_LOGIC;
signal blk00000003_sig00000ebf : STD_LOGIC;
signal blk00000003_sig00000ebe : STD_LOGIC;
signal blk00000003_sig00000ebd : STD_LOGIC;
signal blk00000003_sig00000ebc : STD_LOGIC;
signal blk00000003_sig00000ebb : STD_LOGIC;
signal blk00000003_sig00000eba : STD_LOGIC;
signal blk00000003_sig00000eb9 : STD_LOGIC;
signal blk00000003_sig00000eb8 : STD_LOGIC;
signal blk00000003_sig00000eb7 : STD_LOGIC;
signal blk00000003_sig00000eb6 : STD_LOGIC;
signal blk00000003_sig00000eb5 : STD_LOGIC;
signal blk00000003_sig00000eb4 : STD_LOGIC;
signal blk00000003_sig00000eb3 : STD_LOGIC;
signal blk00000003_sig00000eb2 : STD_LOGIC;
signal blk00000003_sig00000eb1 : STD_LOGIC;
signal blk00000003_sig00000eb0 : STD_LOGIC;
signal blk00000003_sig00000eaf : STD_LOGIC;
signal blk00000003_sig00000eae : STD_LOGIC;
signal blk00000003_sig00000ead : STD_LOGIC;
signal blk00000003_sig00000eac : STD_LOGIC;
signal blk00000003_sig00000eab : STD_LOGIC;
signal blk00000003_sig00000eaa : STD_LOGIC;
signal blk00000003_sig00000ea9 : STD_LOGIC;
signal blk00000003_sig00000ea8 : STD_LOGIC;
signal blk00000003_sig00000ea7 : STD_LOGIC;
signal blk00000003_sig00000ea6 : STD_LOGIC;
signal blk00000003_sig00000ea5 : STD_LOGIC;
signal blk00000003_sig00000ea4 : STD_LOGIC;
signal blk00000003_sig00000ea3 : STD_LOGIC;
signal blk00000003_sig00000ea2 : STD_LOGIC;
signal blk00000003_sig00000ea1 : STD_LOGIC;
signal blk00000003_sig00000ea0 : STD_LOGIC;
signal blk00000003_sig00000e9f : STD_LOGIC;
signal blk00000003_sig00000e9e : STD_LOGIC;
signal blk00000003_sig00000e9d : STD_LOGIC;
signal blk00000003_sig00000e9c : STD_LOGIC;
signal blk00000003_sig00000e9b : STD_LOGIC;
signal blk00000003_sig00000e9a : STD_LOGIC;
signal blk00000003_sig00000e99 : STD_LOGIC;
signal blk00000003_sig00000e98 : STD_LOGIC;
signal blk00000003_sig00000e97 : STD_LOGIC;
signal blk00000003_sig00000e96 : STD_LOGIC;
signal blk00000003_sig00000e95 : STD_LOGIC;
signal blk00000003_sig00000e94 : STD_LOGIC;
signal blk00000003_sig00000e93 : STD_LOGIC;
signal blk00000003_sig00000e92 : STD_LOGIC;
signal blk00000003_sig00000e91 : STD_LOGIC;
signal blk00000003_sig00000e90 : STD_LOGIC;
signal blk00000003_sig00000e8f : STD_LOGIC;
signal blk00000003_sig00000e8e : STD_LOGIC;
signal blk00000003_sig00000e8d : STD_LOGIC;
signal blk00000003_sig00000e8c : STD_LOGIC;
signal blk00000003_sig00000e8b : STD_LOGIC;
signal blk00000003_sig00000e8a : STD_LOGIC;
signal blk00000003_sig00000e89 : STD_LOGIC;
signal blk00000003_sig00000e88 : STD_LOGIC;
signal blk00000003_sig00000e87 : STD_LOGIC;
signal blk00000003_sig00000e86 : STD_LOGIC;
signal blk00000003_sig00000e85 : STD_LOGIC;
signal blk00000003_sig00000e84 : STD_LOGIC;
signal blk00000003_sig00000e83 : STD_LOGIC;
signal blk00000003_sig00000e82 : STD_LOGIC;
signal blk00000003_sig00000e81 : STD_LOGIC;
signal blk00000003_sig00000e80 : STD_LOGIC;
signal blk00000003_sig00000e7f : STD_LOGIC;
signal blk00000003_sig00000e7e : STD_LOGIC;
signal blk00000003_sig00000e7d : STD_LOGIC;
signal blk00000003_sig00000e7c : STD_LOGIC;
signal blk00000003_sig00000e7b : STD_LOGIC;
signal blk00000003_sig00000e7a : STD_LOGIC;
signal blk00000003_sig00000e79 : STD_LOGIC;
signal blk00000003_sig00000e78 : STD_LOGIC;
signal blk00000003_sig00000e77 : STD_LOGIC;
signal blk00000003_sig00000e76 : STD_LOGIC;
signal blk00000003_sig00000e75 : STD_LOGIC;
signal blk00000003_sig00000e74 : STD_LOGIC;
signal blk00000003_sig00000e73 : STD_LOGIC;
signal blk00000003_sig00000e72 : STD_LOGIC;
signal blk00000003_sig00000e71 : STD_LOGIC;
signal blk00000003_sig00000e70 : STD_LOGIC;
signal blk00000003_sig00000e6f : STD_LOGIC;
signal blk00000003_sig00000e6e : STD_LOGIC;
signal blk00000003_sig00000e6d : STD_LOGIC;
signal blk00000003_sig00000e6c : STD_LOGIC;
signal blk00000003_sig00000e6b : STD_LOGIC;
signal blk00000003_sig00000e6a : STD_LOGIC;
signal blk00000003_sig00000e69 : STD_LOGIC;
signal blk00000003_sig00000e68 : STD_LOGIC;
signal blk00000003_sig00000e67 : STD_LOGIC;
signal blk00000003_sig00000e66 : STD_LOGIC;
signal blk00000003_sig00000e65 : STD_LOGIC;
signal blk00000003_sig00000e64 : STD_LOGIC;
signal blk00000003_sig00000e63 : STD_LOGIC;
signal blk00000003_sig00000e62 : STD_LOGIC;
signal blk00000003_sig00000e61 : STD_LOGIC;
signal blk00000003_sig00000e60 : STD_LOGIC;
signal blk00000003_sig00000e5f : STD_LOGIC;
signal blk00000003_sig00000e5e : STD_LOGIC;
signal blk00000003_sig00000e5d : STD_LOGIC;
signal blk00000003_sig00000e5c : STD_LOGIC;
signal blk00000003_sig00000e5b : STD_LOGIC;
signal blk00000003_sig00000e5a : STD_LOGIC;
signal blk00000003_sig00000e59 : STD_LOGIC;
signal blk00000003_sig00000e58 : STD_LOGIC;
signal blk00000003_sig00000e57 : STD_LOGIC;
signal blk00000003_sig00000e56 : STD_LOGIC;
signal blk00000003_sig00000e55 : STD_LOGIC;
signal blk00000003_sig00000e54 : STD_LOGIC;
signal blk00000003_sig00000e53 : STD_LOGIC;
signal blk00000003_sig00000e52 : STD_LOGIC;
signal blk00000003_sig00000e51 : STD_LOGIC;
signal blk00000003_sig00000e50 : STD_LOGIC;
signal blk00000003_sig00000e4f : STD_LOGIC;
signal blk00000003_sig00000e4e : STD_LOGIC;
signal blk00000003_sig00000e4d : STD_LOGIC;
signal blk00000003_sig00000e4c : STD_LOGIC;
signal blk00000003_sig00000e4b : STD_LOGIC;
signal blk00000003_sig00000e4a : STD_LOGIC;
signal blk00000003_sig00000e49 : STD_LOGIC;
signal blk00000003_sig00000e48 : STD_LOGIC;
signal blk00000003_sig00000e47 : STD_LOGIC;
signal blk00000003_sig00000e46 : STD_LOGIC;
signal blk00000003_sig00000e45 : STD_LOGIC;
signal blk00000003_sig00000e44 : STD_LOGIC;
signal blk00000003_sig00000e43 : STD_LOGIC;
signal blk00000003_sig00000e42 : STD_LOGIC;
signal blk00000003_sig00000e41 : STD_LOGIC;
signal blk00000003_sig00000e40 : STD_LOGIC;
signal blk00000003_sig00000e3f : STD_LOGIC;
signal blk00000003_sig00000e3e : STD_LOGIC;
signal blk00000003_sig00000e3d : STD_LOGIC;
signal blk00000003_sig00000e3c : STD_LOGIC;
signal blk00000003_sig00000e3b : STD_LOGIC;
signal blk00000003_sig00000e3a : STD_LOGIC;
signal blk00000003_sig00000e39 : STD_LOGIC;
signal blk00000003_sig00000e38 : STD_LOGIC;
signal blk00000003_sig00000e37 : STD_LOGIC;
signal blk00000003_sig00000e36 : STD_LOGIC;
signal blk00000003_sig00000e35 : STD_LOGIC;
signal blk00000003_sig00000e34 : STD_LOGIC;
signal blk00000003_sig00000e33 : STD_LOGIC;
signal blk00000003_sig00000e32 : STD_LOGIC;
signal blk00000003_sig00000e31 : STD_LOGIC;
signal blk00000003_sig00000e30 : STD_LOGIC;
signal blk00000003_sig00000e2f : STD_LOGIC;
signal blk00000003_sig00000e2e : STD_LOGIC;
signal blk00000003_sig00000e2d : STD_LOGIC;
signal blk00000003_sig00000e2c : STD_LOGIC;
signal blk00000003_sig00000e2b : STD_LOGIC;
signal blk00000003_sig00000e2a : STD_LOGIC;
signal blk00000003_sig00000e29 : STD_LOGIC;
signal blk00000003_sig00000e28 : STD_LOGIC;
signal blk00000003_sig00000e27 : STD_LOGIC;
signal blk00000003_sig00000e26 : STD_LOGIC;
signal blk00000003_sig00000e25 : STD_LOGIC;
signal blk00000003_sig00000e24 : STD_LOGIC;
signal blk00000003_sig00000e23 : STD_LOGIC;
signal blk00000003_sig00000e22 : STD_LOGIC;
signal blk00000003_sig00000e21 : STD_LOGIC;
signal blk00000003_sig00000e20 : STD_LOGIC;
signal blk00000003_sig00000e1f : STD_LOGIC;
signal blk00000003_sig00000e1e : STD_LOGIC;
signal blk00000003_sig00000e1d : STD_LOGIC;
signal blk00000003_sig00000e1c : STD_LOGIC;
signal blk00000003_sig00000e1b : STD_LOGIC;
signal blk00000003_sig00000e1a : STD_LOGIC;
signal blk00000003_sig00000e19 : STD_LOGIC;
signal blk00000003_sig00000e18 : STD_LOGIC;
signal blk00000003_sig00000e17 : STD_LOGIC;
signal blk00000003_sig00000e16 : STD_LOGIC;
signal blk00000003_sig00000e15 : STD_LOGIC;
signal blk00000003_sig00000e14 : STD_LOGIC;
signal blk00000003_sig00000e13 : STD_LOGIC;
signal blk00000003_sig00000e12 : STD_LOGIC;
signal blk00000003_sig00000e11 : STD_LOGIC;
signal blk00000003_sig00000e10 : STD_LOGIC;
signal blk00000003_sig00000e0f : STD_LOGIC;
signal blk00000003_sig00000e0e : STD_LOGIC;
signal blk00000003_sig00000e0d : STD_LOGIC;
signal blk00000003_sig00000e0c : STD_LOGIC;
signal blk00000003_sig00000e0b : STD_LOGIC;
signal blk00000003_sig00000e0a : STD_LOGIC;
signal blk00000003_sig00000e09 : STD_LOGIC;
signal blk00000003_sig00000e08 : STD_LOGIC;
signal blk00000003_sig00000e07 : STD_LOGIC;
signal blk00000003_sig00000e06 : STD_LOGIC;
signal blk00000003_sig00000e05 : STD_LOGIC;
signal blk00000003_sig00000e04 : STD_LOGIC;
signal blk00000003_sig00000e03 : STD_LOGIC;
signal blk00000003_sig00000e02 : STD_LOGIC;
signal blk00000003_sig00000e01 : STD_LOGIC;
signal blk00000003_sig00000e00 : STD_LOGIC;
signal blk00000003_sig00000dff : STD_LOGIC;
signal blk00000003_sig00000dfe : STD_LOGIC;
signal blk00000003_sig00000dfd : STD_LOGIC;
signal blk00000003_sig00000dfc : STD_LOGIC;
signal blk00000003_sig00000dfb : STD_LOGIC;
signal blk00000003_sig00000dfa : STD_LOGIC;
signal blk00000003_sig00000df9 : STD_LOGIC;
signal blk00000003_sig00000df8 : STD_LOGIC;
signal blk00000003_sig00000df7 : STD_LOGIC;
signal blk00000003_sig00000df6 : STD_LOGIC;
signal blk00000003_sig00000df5 : STD_LOGIC;
signal blk00000003_sig00000df4 : STD_LOGIC;
signal blk00000003_sig00000df3 : STD_LOGIC;
signal blk00000003_sig00000df2 : STD_LOGIC;
signal blk00000003_sig00000df1 : STD_LOGIC;
signal blk00000003_sig00000df0 : STD_LOGIC;
signal blk00000003_sig00000def : STD_LOGIC;
signal blk00000003_sig00000dee : STD_LOGIC;
signal blk00000003_sig00000ded : STD_LOGIC;
signal blk00000003_sig00000dec : STD_LOGIC;
signal blk00000003_sig00000deb : STD_LOGIC;
signal blk00000003_sig00000dea : STD_LOGIC;
signal blk00000003_sig00000de9 : STD_LOGIC;
signal blk00000003_sig00000de8 : STD_LOGIC;
signal blk00000003_sig00000de7 : STD_LOGIC;
signal blk00000003_sig00000de6 : STD_LOGIC;
signal blk00000003_sig00000de5 : STD_LOGIC;
signal blk00000003_sig00000de4 : STD_LOGIC;
signal blk00000003_sig00000de3 : STD_LOGIC;
signal blk00000003_sig00000de2 : STD_LOGIC;
signal blk00000003_sig00000de1 : STD_LOGIC;
signal blk00000003_sig00000de0 : STD_LOGIC;
signal blk00000003_sig00000ddf : STD_LOGIC;
signal blk00000003_sig00000dde : STD_LOGIC;
signal blk00000003_sig00000ddd : STD_LOGIC;
signal blk00000003_sig00000ddc : STD_LOGIC;
signal blk00000003_sig00000ddb : STD_LOGIC;
signal blk00000003_sig00000dda : STD_LOGIC;
signal blk00000003_sig00000dd9 : STD_LOGIC;
signal blk00000003_sig00000dd8 : STD_LOGIC;
signal blk00000003_sig00000dd7 : STD_LOGIC;
signal blk00000003_sig00000dd6 : STD_LOGIC;
signal blk00000003_sig00000dd5 : STD_LOGIC;
signal blk00000003_sig00000dd4 : STD_LOGIC;
signal blk00000003_sig00000dd3 : STD_LOGIC;
signal blk00000003_sig00000dd2 : STD_LOGIC;
signal blk00000003_sig00000dd1 : STD_LOGIC;
signal blk00000003_sig00000dd0 : STD_LOGIC;
signal blk00000003_sig00000dcf : STD_LOGIC;
signal blk00000003_sig00000dce : STD_LOGIC;
signal blk00000003_sig00000dcd : STD_LOGIC;
signal blk00000003_sig00000dcc : STD_LOGIC;
signal blk00000003_sig00000dcb : STD_LOGIC;
signal blk00000003_sig00000dca : STD_LOGIC;
signal blk00000003_sig00000dc9 : STD_LOGIC;
signal blk00000003_sig00000dc8 : STD_LOGIC;
signal blk00000003_sig00000dc7 : STD_LOGIC;
signal blk00000003_sig00000dc6 : STD_LOGIC;
signal blk00000003_sig00000dc5 : STD_LOGIC;
signal blk00000003_sig00000dc4 : STD_LOGIC;
signal blk00000003_sig00000dc3 : STD_LOGIC;
signal blk00000003_sig00000dc2 : STD_LOGIC;
signal blk00000003_sig00000dc1 : STD_LOGIC;
signal blk00000003_sig00000dc0 : STD_LOGIC;
signal blk00000003_sig00000dbf : STD_LOGIC;
signal blk00000003_sig00000dbe : STD_LOGIC;
signal blk00000003_sig00000dbd : STD_LOGIC;
signal blk00000003_sig00000dbc : STD_LOGIC;
signal blk00000003_sig00000dbb : STD_LOGIC;
signal blk00000003_sig00000dba : STD_LOGIC;
signal blk00000003_sig00000db9 : STD_LOGIC;
signal blk00000003_sig00000db8 : STD_LOGIC;
signal blk00000003_sig00000db7 : STD_LOGIC;
signal blk00000003_sig00000db6 : STD_LOGIC;
signal blk00000003_sig00000db5 : STD_LOGIC;
signal blk00000003_sig00000db4 : STD_LOGIC;
signal blk00000003_sig00000db3 : STD_LOGIC;
signal blk00000003_sig00000db2 : STD_LOGIC;
signal blk00000003_sig00000db1 : STD_LOGIC;
signal blk00000003_sig00000db0 : STD_LOGIC;
signal blk00000003_sig00000daf : STD_LOGIC;
signal blk00000003_sig00000dae : STD_LOGIC;
signal blk00000003_sig00000dad : STD_LOGIC;
signal blk00000003_sig00000dac : STD_LOGIC;
signal blk00000003_sig00000dab : STD_LOGIC;
signal blk00000003_sig00000daa : STD_LOGIC;
signal blk00000003_sig00000da9 : STD_LOGIC;
signal blk00000003_sig00000da8 : STD_LOGIC;
signal blk00000003_sig00000da7 : STD_LOGIC;
signal blk00000003_sig00000da6 : STD_LOGIC;
signal blk00000003_sig00000da5 : STD_LOGIC;
signal blk00000003_sig00000da4 : STD_LOGIC;
signal blk00000003_sig00000da3 : STD_LOGIC;
signal blk00000003_sig00000da2 : STD_LOGIC;
signal blk00000003_sig00000da1 : STD_LOGIC;
signal blk00000003_sig00000da0 : STD_LOGIC;
signal blk00000003_sig00000d9f : STD_LOGIC;
signal blk00000003_sig00000d9e : STD_LOGIC;
signal blk00000003_sig00000d9d : STD_LOGIC;
signal blk00000003_sig00000d9c : STD_LOGIC;
signal blk00000003_sig00000d9b : STD_LOGIC;
signal blk00000003_sig00000d9a : STD_LOGIC;
signal blk00000003_sig00000d99 : STD_LOGIC;
signal blk00000003_sig00000d98 : STD_LOGIC;
signal blk00000003_sig00000d97 : STD_LOGIC;
signal blk00000003_sig00000d96 : STD_LOGIC;
signal blk00000003_sig00000d95 : STD_LOGIC;
signal blk00000003_sig00000d94 : STD_LOGIC;
signal blk00000003_sig00000d93 : STD_LOGIC;
signal blk00000003_sig00000d92 : STD_LOGIC;
signal blk00000003_sig00000d91 : STD_LOGIC;
signal blk00000003_sig00000d90 : STD_LOGIC;
signal blk00000003_sig00000d8f : STD_LOGIC;
signal blk00000003_sig00000d8e : STD_LOGIC;
signal blk00000003_sig00000d8d : STD_LOGIC;
signal blk00000003_sig00000d8c : STD_LOGIC;
signal blk00000003_sig00000d8b : STD_LOGIC;
signal blk00000003_sig00000d8a : STD_LOGIC;
signal blk00000003_sig00000d89 : STD_LOGIC;
signal blk00000003_sig00000d88 : STD_LOGIC;
signal blk00000003_sig00000d87 : STD_LOGIC;
signal blk00000003_sig00000d86 : STD_LOGIC;
signal blk00000003_sig00000d85 : STD_LOGIC;
signal blk00000003_sig00000d84 : STD_LOGIC;
signal blk00000003_sig00000d83 : STD_LOGIC;
signal blk00000003_sig00000d82 : STD_LOGIC;
signal blk00000003_sig00000d81 : STD_LOGIC;
signal blk00000003_sig00000d80 : STD_LOGIC;
signal blk00000003_sig00000d7f : STD_LOGIC;
signal blk00000003_sig00000d7e : STD_LOGIC;
signal blk00000003_sig00000d7d : STD_LOGIC;
signal blk00000003_sig00000d7c : STD_LOGIC;
signal blk00000003_sig00000d7b : STD_LOGIC;
signal blk00000003_sig00000d7a : STD_LOGIC;
signal blk00000003_sig00000d79 : STD_LOGIC;
signal blk00000003_sig00000d78 : STD_LOGIC;
signal blk00000003_sig00000d77 : STD_LOGIC;
signal blk00000003_sig00000d76 : STD_LOGIC;
signal blk00000003_sig00000d75 : STD_LOGIC;
signal blk00000003_sig00000d74 : STD_LOGIC;
signal blk00000003_sig00000d73 : STD_LOGIC;
signal blk00000003_sig00000d72 : STD_LOGIC;
signal blk00000003_sig00000d71 : STD_LOGIC;
signal blk00000003_sig00000d70 : STD_LOGIC;
signal blk00000003_sig00000d6f : STD_LOGIC;
signal blk00000003_sig00000d6e : STD_LOGIC;
signal blk00000003_sig00000d6d : STD_LOGIC;
signal blk00000003_sig00000d6c : STD_LOGIC;
signal blk00000003_sig00000d6b : STD_LOGIC;
signal blk00000003_sig00000d6a : STD_LOGIC;
signal blk00000003_sig00000d69 : STD_LOGIC;
signal blk00000003_sig00000d68 : STD_LOGIC;
signal blk00000003_sig00000d67 : STD_LOGIC;
signal blk00000003_sig00000d66 : STD_LOGIC;
signal blk00000003_sig00000d65 : STD_LOGIC;
signal blk00000003_sig00000d64 : STD_LOGIC;
signal blk00000003_sig00000d63 : STD_LOGIC;
signal blk00000003_sig00000d62 : STD_LOGIC;
signal blk00000003_sig00000d61 : STD_LOGIC;
signal blk00000003_sig00000d60 : STD_LOGIC;
signal blk00000003_sig00000d5f : STD_LOGIC;
signal blk00000003_sig00000d5e : STD_LOGIC;
signal blk00000003_sig00000d5d : STD_LOGIC;
signal blk00000003_sig00000d5c : STD_LOGIC;
signal blk00000003_sig00000d5b : STD_LOGIC;
signal blk00000003_sig00000d5a : STD_LOGIC;
signal blk00000003_sig00000d59 : STD_LOGIC;
signal blk00000003_sig00000d58 : STD_LOGIC;
signal blk00000003_sig00000d57 : STD_LOGIC;
signal blk00000003_sig00000d56 : STD_LOGIC;
signal blk00000003_sig00000d55 : STD_LOGIC;
signal blk00000003_sig00000d54 : STD_LOGIC;
signal blk00000003_sig00000d53 : STD_LOGIC;
signal blk00000003_sig00000d52 : STD_LOGIC;
signal blk00000003_sig00000d51 : STD_LOGIC;
signal blk00000003_sig00000d50 : STD_LOGIC;
signal blk00000003_sig00000d4f : STD_LOGIC;
signal blk00000003_sig00000d4e : STD_LOGIC;
signal blk00000003_sig00000d4d : STD_LOGIC;
signal blk00000003_sig00000d4c : STD_LOGIC;
signal blk00000003_sig00000d4b : STD_LOGIC;
signal blk00000003_sig00000d4a : STD_LOGIC;
signal blk00000003_sig00000d49 : STD_LOGIC;
signal blk00000003_sig00000d48 : STD_LOGIC;
signal blk00000003_sig00000d47 : STD_LOGIC;
signal blk00000003_sig00000d46 : STD_LOGIC;
signal blk00000003_sig00000d45 : STD_LOGIC;
signal blk00000003_sig00000d44 : STD_LOGIC;
signal blk00000003_sig00000d43 : STD_LOGIC;
signal blk00000003_sig00000d42 : STD_LOGIC;
signal blk00000003_sig00000d41 : STD_LOGIC;
signal blk00000003_sig00000d40 : STD_LOGIC;
signal blk00000003_sig00000d3f : STD_LOGIC;
signal blk00000003_sig00000d3e : STD_LOGIC;
signal blk00000003_sig00000d3d : STD_LOGIC;
signal blk00000003_sig00000d3c : STD_LOGIC;
signal blk00000003_sig00000d3b : STD_LOGIC;
signal blk00000003_sig00000d3a : STD_LOGIC;
signal blk00000003_sig00000d39 : STD_LOGIC;
signal blk00000003_sig00000d38 : STD_LOGIC;
signal blk00000003_sig00000d37 : STD_LOGIC;
signal blk00000003_sig00000d36 : STD_LOGIC;
signal blk00000003_sig00000d35 : STD_LOGIC;
signal blk00000003_sig00000d34 : STD_LOGIC;
signal blk00000003_sig00000d33 : STD_LOGIC;
signal blk00000003_sig00000d32 : STD_LOGIC;
signal blk00000003_sig00000d31 : STD_LOGIC;
signal blk00000003_sig00000d30 : STD_LOGIC;
signal blk00000003_sig00000d2f : STD_LOGIC;
signal blk00000003_sig00000d2e : STD_LOGIC;
signal blk00000003_sig00000d2d : STD_LOGIC;
signal blk00000003_sig00000d2c : STD_LOGIC;
signal blk00000003_sig00000d2b : STD_LOGIC;
signal blk00000003_sig00000d2a : STD_LOGIC;
signal blk00000003_sig00000d29 : STD_LOGIC;
signal blk00000003_sig00000d28 : STD_LOGIC;
signal blk00000003_sig00000d27 : STD_LOGIC;
signal blk00000003_sig00000d26 : STD_LOGIC;
signal blk00000003_sig00000d25 : STD_LOGIC;
signal blk00000003_sig00000d24 : STD_LOGIC;
signal blk00000003_sig00000d23 : STD_LOGIC;
signal blk00000003_sig00000d22 : STD_LOGIC;
signal blk00000003_sig00000d21 : STD_LOGIC;
signal blk00000003_sig00000d20 : STD_LOGIC;
signal blk00000003_sig00000d1f : STD_LOGIC;
signal blk00000003_sig00000d1e : STD_LOGIC;
signal blk00000003_sig00000d1d : STD_LOGIC;
signal blk00000003_sig00000d1c : STD_LOGIC;
signal blk00000003_sig00000d1b : STD_LOGIC;
signal blk00000003_sig00000d1a : STD_LOGIC;
signal blk00000003_sig00000d19 : STD_LOGIC;
signal blk00000003_sig00000d18 : STD_LOGIC;
signal blk00000003_sig00000d17 : STD_LOGIC;
signal blk00000003_sig00000d16 : STD_LOGIC;
signal blk00000003_sig00000d15 : STD_LOGIC;
signal blk00000003_sig00000d14 : STD_LOGIC;
signal blk00000003_sig00000d13 : STD_LOGIC;
signal blk00000003_sig00000d12 : STD_LOGIC;
signal blk00000003_sig00000d11 : STD_LOGIC;
signal blk00000003_sig00000d10 : STD_LOGIC;
signal blk00000003_sig00000d0f : STD_LOGIC;
signal blk00000003_sig00000d0e : STD_LOGIC;
signal blk00000003_sig00000d0d : STD_LOGIC;
signal blk00000003_sig00000d0c : STD_LOGIC;
signal blk00000003_sig00000d0b : STD_LOGIC;
signal blk00000003_sig00000d0a : STD_LOGIC;
signal blk00000003_sig00000d09 : STD_LOGIC;
signal blk00000003_sig00000d08 : STD_LOGIC;
signal blk00000003_sig00000d07 : STD_LOGIC;
signal blk00000003_sig00000d06 : STD_LOGIC;
signal blk00000003_sig00000d05 : STD_LOGIC;
signal blk00000003_sig00000d04 : STD_LOGIC;
signal blk00000003_sig00000d03 : STD_LOGIC;
signal blk00000003_sig00000d02 : STD_LOGIC;
signal blk00000003_sig00000d01 : STD_LOGIC;
signal blk00000003_sig00000d00 : STD_LOGIC;
signal blk00000003_sig00000cff : STD_LOGIC;
signal blk00000003_sig00000cfe : STD_LOGIC;
signal blk00000003_sig00000cfd : STD_LOGIC;
signal blk00000003_sig00000cfc : STD_LOGIC;
signal blk00000003_sig00000cfb : STD_LOGIC;
signal blk00000003_sig00000cfa : STD_LOGIC;
signal blk00000003_sig00000cf9 : STD_LOGIC;
signal blk00000003_sig00000cf8 : STD_LOGIC;
signal blk00000003_sig00000cf7 : STD_LOGIC;
signal blk00000003_sig00000cf6 : STD_LOGIC;
signal blk00000003_sig00000cf5 : STD_LOGIC;
signal blk00000003_sig00000cf4 : STD_LOGIC;
signal blk00000003_sig00000cf3 : STD_LOGIC;
signal blk00000003_sig00000cf2 : STD_LOGIC;
signal blk00000003_sig00000cf1 : STD_LOGIC;
signal blk00000003_sig00000cf0 : STD_LOGIC;
signal blk00000003_sig00000cef : STD_LOGIC;
signal blk00000003_sig00000cee : STD_LOGIC;
signal blk00000003_sig00000ced : STD_LOGIC;
signal blk00000003_sig00000cec : STD_LOGIC;
signal blk00000003_sig00000ceb : STD_LOGIC;
signal blk00000003_sig00000cea : STD_LOGIC;
signal blk00000003_sig00000ce9 : STD_LOGIC;
signal blk00000003_sig00000ce8 : STD_LOGIC;
signal blk00000003_sig00000ce7 : STD_LOGIC;
signal blk00000003_sig00000ce6 : STD_LOGIC;
signal blk00000003_sig00000ce5 : STD_LOGIC;
signal blk00000003_sig00000ce4 : STD_LOGIC;
signal blk00000003_sig00000ce3 : STD_LOGIC;
signal blk00000003_sig00000ce2 : STD_LOGIC;
signal blk00000003_sig00000ce1 : STD_LOGIC;
signal blk00000003_sig00000ce0 : STD_LOGIC;
signal blk00000003_sig00000cdf : STD_LOGIC;
signal blk00000003_sig00000cde : STD_LOGIC;
signal blk00000003_sig00000cdd : STD_LOGIC;
signal blk00000003_sig00000cdc : STD_LOGIC;
signal blk00000003_sig00000cdb : STD_LOGIC;
signal blk00000003_sig00000cda : STD_LOGIC;
signal blk00000003_sig00000cd9 : STD_LOGIC;
signal blk00000003_sig00000cd8 : STD_LOGIC;
signal blk00000003_sig00000cd7 : STD_LOGIC;
signal blk00000003_sig00000cd6 : STD_LOGIC;
signal blk00000003_sig00000cd5 : STD_LOGIC;
signal blk00000003_sig00000cd4 : STD_LOGIC;
signal blk00000003_sig00000cd3 : STD_LOGIC;
signal blk00000003_sig00000cd2 : STD_LOGIC;
signal blk00000003_sig00000cd1 : STD_LOGIC;
signal blk00000003_sig00000cd0 : STD_LOGIC;
signal blk00000003_sig00000ccf : STD_LOGIC;
signal blk00000003_sig00000cce : STD_LOGIC;
signal blk00000003_sig00000ccd : STD_LOGIC;
signal blk00000003_sig00000ccc : STD_LOGIC;
signal blk00000003_sig00000ccb : STD_LOGIC;
signal blk00000003_sig00000cca : STD_LOGIC;
signal blk00000003_sig00000cc9 : STD_LOGIC;
signal blk00000003_sig00000cc8 : STD_LOGIC;
signal blk00000003_sig00000cc7 : STD_LOGIC;
signal blk00000003_sig00000cc6 : STD_LOGIC;
signal blk00000003_sig00000cc5 : STD_LOGIC;
signal blk00000003_sig00000cc4 : STD_LOGIC;
signal blk00000003_sig00000cc3 : STD_LOGIC;
signal blk00000003_sig00000cc2 : STD_LOGIC;
signal blk00000003_sig00000cc1 : STD_LOGIC;
signal blk00000003_sig00000cc0 : STD_LOGIC;
signal blk00000003_sig00000cbf : STD_LOGIC;
signal blk00000003_sig00000cbe : STD_LOGIC;
signal blk00000003_sig00000cbd : STD_LOGIC;
signal blk00000003_sig00000cbc : STD_LOGIC;
signal blk00000003_sig00000cbb : STD_LOGIC;
signal blk00000003_sig00000cba : STD_LOGIC;
signal blk00000003_sig00000cb9 : STD_LOGIC;
signal blk00000003_sig00000cb8 : STD_LOGIC;
signal blk00000003_sig00000cb7 : STD_LOGIC;
signal blk00000003_sig00000cb6 : STD_LOGIC;
signal blk00000003_sig00000cb5 : STD_LOGIC;
signal blk00000003_sig00000cb4 : STD_LOGIC;
signal blk00000003_sig00000cb3 : STD_LOGIC;
signal blk00000003_sig00000cb2 : STD_LOGIC;
signal blk00000003_sig00000cb1 : STD_LOGIC;
signal blk00000003_sig00000cb0 : STD_LOGIC;
signal blk00000003_sig00000caf : STD_LOGIC;
signal blk00000003_sig00000cae : STD_LOGIC;
signal blk00000003_sig00000cad : STD_LOGIC;
signal blk00000003_sig00000cac : STD_LOGIC;
signal blk00000003_sig00000cab : STD_LOGIC;
signal blk00000003_sig00000caa : STD_LOGIC;
signal blk00000003_sig00000ca9 : STD_LOGIC;
signal blk00000003_sig00000ca8 : STD_LOGIC;
signal blk00000003_sig00000ca7 : STD_LOGIC;
signal blk00000003_sig00000ca6 : STD_LOGIC;
signal blk00000003_sig00000ca5 : STD_LOGIC;
signal blk00000003_sig00000ca4 : STD_LOGIC;
signal blk00000003_sig00000ca3 : STD_LOGIC;
signal blk00000003_sig00000ca2 : STD_LOGIC;
signal blk00000003_sig00000ca1 : STD_LOGIC;
signal blk00000003_sig00000ca0 : STD_LOGIC;
signal blk00000003_sig00000c9f : STD_LOGIC;
signal blk00000003_sig00000c9e : STD_LOGIC;
signal blk00000003_sig00000c9d : STD_LOGIC;
signal blk00000003_sig00000c9c : STD_LOGIC;
signal blk00000003_sig00000c9b : STD_LOGIC;
signal blk00000003_sig00000c9a : STD_LOGIC;
signal blk00000003_sig00000c99 : STD_LOGIC;
signal blk00000003_sig00000c98 : STD_LOGIC;
signal blk00000003_sig00000c97 : STD_LOGIC;
signal blk00000003_sig00000c96 : STD_LOGIC;
signal blk00000003_sig00000c95 : STD_LOGIC;
signal blk00000003_sig00000c94 : STD_LOGIC;
signal blk00000003_sig00000c93 : STD_LOGIC;
signal blk00000003_sig00000c92 : STD_LOGIC;
signal blk00000003_sig00000c91 : STD_LOGIC;
signal blk00000003_sig00000c90 : STD_LOGIC;
signal blk00000003_sig00000c8f : STD_LOGIC;
signal blk00000003_sig00000c8e : STD_LOGIC;
signal blk00000003_sig00000c8d : STD_LOGIC;
signal blk00000003_sig00000c8c : STD_LOGIC;
signal blk00000003_sig00000c8b : STD_LOGIC;
signal blk00000003_sig00000c8a : STD_LOGIC;
signal blk00000003_sig00000c89 : STD_LOGIC;
signal blk00000003_sig00000c88 : STD_LOGIC;
signal blk00000003_sig00000c87 : STD_LOGIC;
signal blk00000003_sig00000c86 : STD_LOGIC;
signal blk00000003_sig00000c85 : STD_LOGIC;
signal blk00000003_sig00000c84 : STD_LOGIC;
signal blk00000003_sig00000c83 : STD_LOGIC;
signal blk00000003_sig00000c82 : STD_LOGIC;
signal blk00000003_sig00000c81 : STD_LOGIC;
signal blk00000003_sig00000c80 : STD_LOGIC;
signal blk00000003_sig00000c7f : STD_LOGIC;
signal blk00000003_sig00000c7e : STD_LOGIC;
signal blk00000003_sig00000c7d : STD_LOGIC;
signal blk00000003_sig00000c7c : STD_LOGIC;
signal blk00000003_sig00000c7b : STD_LOGIC;
signal blk00000003_sig00000c7a : STD_LOGIC;
signal blk00000003_sig00000c79 : STD_LOGIC;
signal blk00000003_sig00000c78 : STD_LOGIC;
signal blk00000003_sig00000c77 : STD_LOGIC;
signal blk00000003_sig00000c76 : STD_LOGIC;
signal blk00000003_sig00000c75 : STD_LOGIC;
signal blk00000003_sig00000c74 : STD_LOGIC;
signal blk00000003_sig00000c73 : STD_LOGIC;
signal blk00000003_sig00000c72 : STD_LOGIC;
signal blk00000003_sig00000c71 : STD_LOGIC;
signal blk00000003_sig00000c70 : STD_LOGIC;
signal blk00000003_sig00000c6f : STD_LOGIC;
signal blk00000003_sig00000c6e : STD_LOGIC;
signal blk00000003_sig00000c6d : STD_LOGIC;
signal blk00000003_sig00000c6c : STD_LOGIC;
signal blk00000003_sig00000c6b : STD_LOGIC;
signal blk00000003_sig00000c6a : STD_LOGIC;
signal blk00000003_sig00000c69 : STD_LOGIC;
signal blk00000003_sig00000c68 : STD_LOGIC;
signal blk00000003_sig00000c67 : STD_LOGIC;
signal blk00000003_sig00000c66 : STD_LOGIC;
signal blk00000003_sig00000c65 : STD_LOGIC;
signal blk00000003_sig00000c64 : STD_LOGIC;
signal blk00000003_sig00000c63 : STD_LOGIC;
signal blk00000003_sig00000c62 : STD_LOGIC;
signal blk00000003_sig00000c61 : STD_LOGIC;
signal blk00000003_sig00000c60 : STD_LOGIC;
signal blk00000003_sig00000c5f : STD_LOGIC;
signal blk00000003_sig00000c5e : STD_LOGIC;
signal blk00000003_sig00000c5d : STD_LOGIC;
signal blk00000003_sig00000c5c : STD_LOGIC;
signal blk00000003_sig00000c5b : STD_LOGIC;
signal blk00000003_sig00000c5a : STD_LOGIC;
signal blk00000003_sig00000c59 : STD_LOGIC;
signal blk00000003_sig00000c58 : STD_LOGIC;
signal blk00000003_sig00000c57 : STD_LOGIC;
signal blk00000003_sig00000c56 : STD_LOGIC;
signal blk00000003_sig00000c55 : STD_LOGIC;
signal blk00000003_sig00000c54 : STD_LOGIC;
signal blk00000003_sig00000c53 : STD_LOGIC;
signal blk00000003_sig00000c52 : STD_LOGIC;
signal blk00000003_sig00000c51 : STD_LOGIC;
signal blk00000003_sig00000c50 : STD_LOGIC;
signal blk00000003_sig00000c4f : STD_LOGIC;
signal blk00000003_sig00000c4e : STD_LOGIC;
signal blk00000003_sig00000c4d : STD_LOGIC;
signal blk00000003_sig00000c4c : STD_LOGIC;
signal blk00000003_sig00000c4b : STD_LOGIC;
signal blk00000003_sig00000c4a : STD_LOGIC;
signal blk00000003_sig00000c49 : STD_LOGIC;
signal blk00000003_sig00000c48 : STD_LOGIC;
signal blk00000003_sig00000c47 : STD_LOGIC;
signal blk00000003_sig00000c46 : STD_LOGIC;
signal blk00000003_sig00000c45 : STD_LOGIC;
signal blk00000003_sig00000c44 : STD_LOGIC;
signal blk00000003_sig00000c43 : STD_LOGIC;
signal blk00000003_sig00000c42 : STD_LOGIC;
signal blk00000003_sig00000c41 : STD_LOGIC;
signal blk00000003_sig00000c40 : STD_LOGIC;
signal blk00000003_sig00000c3f : STD_LOGIC;
signal blk00000003_sig00000c3e : STD_LOGIC;
signal blk00000003_sig00000c3d : STD_LOGIC;
signal blk00000003_sig00000c3c : STD_LOGIC;
signal blk00000003_sig00000c3b : STD_LOGIC;
signal blk00000003_sig00000c3a : STD_LOGIC;
signal blk00000003_sig00000c39 : STD_LOGIC;
signal blk00000003_sig00000c38 : STD_LOGIC;
signal blk00000003_sig00000c37 : STD_LOGIC;
signal blk00000003_sig00000c36 : STD_LOGIC;
signal blk00000003_sig00000c35 : STD_LOGIC;
signal blk00000003_sig00000c34 : STD_LOGIC;
signal blk00000003_sig00000c33 : STD_LOGIC;
signal blk00000003_sig00000c32 : STD_LOGIC;
signal blk00000003_sig00000c31 : STD_LOGIC;
signal blk00000003_sig00000c30 : STD_LOGIC;
signal blk00000003_sig00000c2f : STD_LOGIC;
signal blk00000003_sig00000c2e : STD_LOGIC;
signal blk00000003_sig00000c2d : STD_LOGIC;
signal blk00000003_sig00000c2c : STD_LOGIC;
signal blk00000003_sig00000c2b : STD_LOGIC;
signal blk00000003_sig00000c2a : STD_LOGIC;
signal blk00000003_sig00000c29 : STD_LOGIC;
signal blk00000003_sig00000c28 : STD_LOGIC;
signal blk00000003_sig00000c27 : STD_LOGIC;
signal blk00000003_sig00000c26 : STD_LOGIC;
signal blk00000003_sig00000c25 : STD_LOGIC;
signal blk00000003_sig00000c24 : STD_LOGIC;
signal blk00000003_sig00000c23 : STD_LOGIC;
signal blk00000003_sig00000c22 : STD_LOGIC;
signal blk00000003_sig00000c21 : STD_LOGIC;
signal blk00000003_sig00000c20 : STD_LOGIC;
signal blk00000003_sig00000c1f : STD_LOGIC;
signal blk00000003_sig00000c1e : STD_LOGIC;
signal blk00000003_sig00000c1d : STD_LOGIC;
signal blk00000003_sig00000c1c : STD_LOGIC;
signal blk00000003_sig00000c1b : STD_LOGIC;
signal blk00000003_sig00000c1a : STD_LOGIC;
signal blk00000003_sig00000c19 : STD_LOGIC;
signal blk00000003_sig00000c18 : STD_LOGIC;
signal blk00000003_sig00000c17 : STD_LOGIC;
signal blk00000003_sig00000c16 : STD_LOGIC;
signal blk00000003_sig00000c15 : STD_LOGIC;
signal blk00000003_sig00000c14 : STD_LOGIC;
signal blk00000003_sig00000c13 : STD_LOGIC;
signal blk00000003_sig00000c12 : STD_LOGIC;
signal blk00000003_sig00000c11 : STD_LOGIC;
signal blk00000003_sig00000c10 : STD_LOGIC;
signal blk00000003_sig00000c0f : STD_LOGIC;
signal blk00000003_sig00000c0e : STD_LOGIC;
signal blk00000003_sig00000c0d : STD_LOGIC;
signal blk00000003_sig00000c0c : STD_LOGIC;
signal blk00000003_sig00000c0b : STD_LOGIC;
signal blk00000003_sig00000c0a : STD_LOGIC;
signal blk00000003_sig00000c09 : STD_LOGIC;
signal blk00000003_sig00000c08 : STD_LOGIC;
signal blk00000003_sig00000c07 : STD_LOGIC;
signal blk00000003_sig00000c06 : STD_LOGIC;
signal blk00000003_sig00000c05 : STD_LOGIC;
signal blk00000003_sig00000c04 : STD_LOGIC;
signal blk00000003_sig00000c03 : STD_LOGIC;
signal blk00000003_sig00000c02 : STD_LOGIC;
signal blk00000003_sig00000c01 : STD_LOGIC;
signal blk00000003_sig00000c00 : STD_LOGIC;
signal blk00000003_sig00000bff : STD_LOGIC;
signal blk00000003_sig00000bfe : STD_LOGIC;
signal blk00000003_sig00000bfd : STD_LOGIC;
signal blk00000003_sig00000bfc : STD_LOGIC;
signal blk00000003_sig00000bfb : STD_LOGIC;
signal blk00000003_sig00000bfa : STD_LOGIC;
signal blk00000003_sig00000bf9 : STD_LOGIC;
signal blk00000003_sig00000bf8 : STD_LOGIC;
signal blk00000003_sig00000bf7 : STD_LOGIC;
signal blk00000003_sig00000bf6 : STD_LOGIC;
signal blk00000003_sig00000bf5 : STD_LOGIC;
signal blk00000003_sig00000bf4 : STD_LOGIC;
signal blk00000003_sig00000bf3 : STD_LOGIC;
signal blk00000003_sig00000bf2 : STD_LOGIC;
signal blk00000003_sig00000bf1 : STD_LOGIC;
signal blk00000003_sig00000bf0 : STD_LOGIC;
signal blk00000003_sig00000bef : STD_LOGIC;
signal blk00000003_sig00000bee : STD_LOGIC;
signal blk00000003_sig00000bed : STD_LOGIC;
signal blk00000003_sig00000bec : STD_LOGIC;
signal blk00000003_sig00000beb : STD_LOGIC;
signal blk00000003_sig00000bea : STD_LOGIC;
signal blk00000003_sig00000be9 : STD_LOGIC;
signal blk00000003_sig00000be8 : STD_LOGIC;
signal blk00000003_sig00000be7 : STD_LOGIC;
signal blk00000003_sig00000be6 : STD_LOGIC;
signal blk00000003_sig00000be5 : STD_LOGIC;
signal blk00000003_sig00000be4 : STD_LOGIC;
signal blk00000003_sig00000be3 : STD_LOGIC;
signal blk00000003_sig00000be2 : STD_LOGIC;
signal blk00000003_sig00000be1 : STD_LOGIC;
signal blk00000003_sig00000be0 : STD_LOGIC;
signal blk00000003_sig00000bdf : STD_LOGIC;
signal blk00000003_sig00000bde : STD_LOGIC;
signal blk00000003_sig00000bdd : STD_LOGIC;
signal blk00000003_sig00000bdc : STD_LOGIC;
signal blk00000003_sig00000bdb : STD_LOGIC;
signal blk00000003_sig00000bda : STD_LOGIC;
signal blk00000003_sig00000bd9 : STD_LOGIC;
signal blk00000003_sig00000bd8 : STD_LOGIC;
signal blk00000003_sig00000bd7 : STD_LOGIC;
signal blk00000003_sig00000bd6 : STD_LOGIC;
signal blk00000003_sig00000bd5 : STD_LOGIC;
signal blk00000003_sig00000bd4 : STD_LOGIC;
signal blk00000003_sig00000bd3 : STD_LOGIC;
signal blk00000003_sig00000bd2 : STD_LOGIC;
signal blk00000003_sig00000bd1 : STD_LOGIC;
signal blk00000003_sig00000bd0 : STD_LOGIC;
signal blk00000003_sig00000bcf : STD_LOGIC;
signal blk00000003_sig00000bce : STD_LOGIC;
signal blk00000003_sig00000bcd : STD_LOGIC;
signal blk00000003_sig00000bcc : STD_LOGIC;
signal blk00000003_sig00000bcb : STD_LOGIC;
signal blk00000003_sig00000bca : STD_LOGIC;
signal blk00000003_sig00000bc9 : STD_LOGIC;
signal blk00000003_sig00000bc8 : STD_LOGIC;
signal blk00000003_sig00000bc7 : STD_LOGIC;
signal blk00000003_sig00000bc6 : STD_LOGIC;
signal blk00000003_sig00000bc5 : STD_LOGIC;
signal blk00000003_sig00000bc4 : STD_LOGIC;
signal blk00000003_sig00000bc3 : STD_LOGIC;
signal blk00000003_sig00000bc2 : STD_LOGIC;
signal blk00000003_sig00000bc1 : STD_LOGIC;
signal blk00000003_sig00000bc0 : STD_LOGIC;
signal blk00000003_sig00000bbf : STD_LOGIC;
signal blk00000003_sig00000bbe : STD_LOGIC;
signal blk00000003_sig00000bbd : STD_LOGIC;
signal blk00000003_sig00000bbc : STD_LOGIC;
signal blk00000003_sig00000bbb : STD_LOGIC;
signal blk00000003_sig00000bba : STD_LOGIC;
signal blk00000003_sig00000bb9 : STD_LOGIC;
signal blk00000003_sig00000bb8 : STD_LOGIC;
signal blk00000003_sig00000bb7 : STD_LOGIC;
signal blk00000003_sig00000bb6 : STD_LOGIC;
signal blk00000003_sig00000bb5 : STD_LOGIC;
signal blk00000003_sig00000bb4 : STD_LOGIC;
signal blk00000003_sig00000bb3 : STD_LOGIC;
signal blk00000003_sig00000bb2 : STD_LOGIC;
signal blk00000003_sig00000bb1 : STD_LOGIC;
signal blk00000003_sig00000bb0 : STD_LOGIC;
signal blk00000003_sig00000baf : STD_LOGIC;
signal blk00000003_sig00000bae : STD_LOGIC;
signal blk00000003_sig00000bad : STD_LOGIC;
signal blk00000003_sig00000bac : STD_LOGIC;
signal blk00000003_sig00000bab : STD_LOGIC;
signal blk00000003_sig00000baa : STD_LOGIC;
signal blk00000003_sig00000ba9 : STD_LOGIC;
signal blk00000003_sig00000ba8 : STD_LOGIC;
signal blk00000003_sig00000ba7 : STD_LOGIC;
signal blk00000003_sig00000ba6 : STD_LOGIC;
signal blk00000003_sig00000ba5 : STD_LOGIC;
signal blk00000003_sig00000ba4 : STD_LOGIC;
signal blk00000003_sig00000ba3 : STD_LOGIC;
signal blk00000003_sig00000ba2 : STD_LOGIC;
signal blk00000003_sig00000ba1 : STD_LOGIC;
signal blk00000003_sig00000ba0 : STD_LOGIC;
signal blk00000003_sig00000b9f : STD_LOGIC;
signal blk00000003_sig00000b9e : STD_LOGIC;
signal blk00000003_sig00000b9d : STD_LOGIC;
signal blk00000003_sig00000b9c : STD_LOGIC;
signal blk00000003_sig00000b9b : STD_LOGIC;
signal blk00000003_sig00000b9a : STD_LOGIC;
signal blk00000003_sig00000b99 : STD_LOGIC;
signal blk00000003_sig00000b98 : STD_LOGIC;
signal blk00000003_sig00000b97 : STD_LOGIC;
signal blk00000003_sig00000b96 : STD_LOGIC;
signal blk00000003_sig00000b95 : STD_LOGIC;
signal blk00000003_sig00000b94 : STD_LOGIC;
signal blk00000003_sig00000b93 : STD_LOGIC;
signal blk00000003_sig00000b92 : STD_LOGIC;
signal blk00000003_sig00000b91 : STD_LOGIC;
signal blk00000003_sig00000b90 : STD_LOGIC;
signal blk00000003_sig00000b8f : STD_LOGIC;
signal blk00000003_sig00000b8e : STD_LOGIC;
signal blk00000003_sig00000b8d : STD_LOGIC;
signal blk00000003_sig00000b8c : STD_LOGIC;
signal blk00000003_sig00000b8b : STD_LOGIC;
signal blk00000003_sig00000b8a : STD_LOGIC;
signal blk00000003_sig00000b89 : STD_LOGIC;
signal blk00000003_sig00000b88 : STD_LOGIC;
signal blk00000003_sig00000b87 : STD_LOGIC;
signal blk00000003_sig00000b86 : STD_LOGIC;
signal blk00000003_sig00000b85 : STD_LOGIC;
signal blk00000003_sig00000b84 : STD_LOGIC;
signal blk00000003_sig00000b83 : STD_LOGIC;
signal blk00000003_sig00000b82 : STD_LOGIC;
signal blk00000003_sig00000b81 : STD_LOGIC;
signal blk00000003_sig00000b80 : STD_LOGIC;
signal blk00000003_sig00000b7f : STD_LOGIC;
signal blk00000003_sig00000b7e : STD_LOGIC;
signal blk00000003_sig00000b7d : STD_LOGIC;
signal blk00000003_sig00000b7c : STD_LOGIC;
signal blk00000003_sig00000b7b : STD_LOGIC;
signal blk00000003_sig00000b7a : STD_LOGIC;
signal blk00000003_sig00000b79 : STD_LOGIC;
signal blk00000003_sig00000b78 : STD_LOGIC;
signal blk00000003_sig00000b77 : STD_LOGIC;
signal blk00000003_sig00000b76 : STD_LOGIC;
signal blk00000003_sig00000b75 : STD_LOGIC;
signal blk00000003_sig00000b74 : STD_LOGIC;
signal blk00000003_sig00000b73 : STD_LOGIC;
signal blk00000003_sig00000b72 : STD_LOGIC;
signal blk00000003_sig00000b71 : STD_LOGIC;
signal blk00000003_sig00000b70 : STD_LOGIC;
signal blk00000003_sig00000b6f : STD_LOGIC;
signal blk00000003_sig00000b6e : STD_LOGIC;
signal blk00000003_sig00000b6d : STD_LOGIC;
signal blk00000003_sig00000b6c : STD_LOGIC;
signal blk00000003_sig00000b6b : STD_LOGIC;
signal blk00000003_sig00000b6a : STD_LOGIC;
signal blk00000003_sig00000b69 : STD_LOGIC;
signal blk00000003_sig00000b68 : STD_LOGIC;
signal blk00000003_sig00000b67 : STD_LOGIC;
signal blk00000003_sig00000b66 : STD_LOGIC;
signal blk00000003_sig00000b65 : STD_LOGIC;
signal blk00000003_sig00000b64 : STD_LOGIC;
signal blk00000003_sig00000b63 : STD_LOGIC;
signal blk00000003_sig00000b62 : STD_LOGIC;
signal blk00000003_sig00000b61 : STD_LOGIC;
signal blk00000003_sig00000b60 : STD_LOGIC;
signal blk00000003_sig00000b5f : STD_LOGIC;
signal blk00000003_sig00000b5e : STD_LOGIC;
signal blk00000003_sig00000b5d : STD_LOGIC;
signal blk00000003_sig00000b5c : STD_LOGIC;
signal blk00000003_sig00000b5b : STD_LOGIC;
signal blk00000003_sig00000b5a : STD_LOGIC;
signal blk00000003_sig00000b59 : STD_LOGIC;
signal blk00000003_sig00000b58 : STD_LOGIC;
signal blk00000003_sig00000b57 : STD_LOGIC;
signal blk00000003_sig00000b56 : STD_LOGIC;
signal blk00000003_sig00000b55 : STD_LOGIC;
signal blk00000003_sig00000b54 : STD_LOGIC;
signal blk00000003_sig00000b53 : STD_LOGIC;
signal blk00000003_sig00000b52 : STD_LOGIC;
signal blk00000003_sig00000b51 : STD_LOGIC;
signal blk00000003_sig00000b50 : STD_LOGIC;
signal blk00000003_sig00000b4f : STD_LOGIC;
signal blk00000003_sig00000b4e : STD_LOGIC;
signal blk00000003_sig00000b4d : STD_LOGIC;
signal blk00000003_sig00000b4c : STD_LOGIC;
signal blk00000003_sig00000b4b : STD_LOGIC;
signal blk00000003_sig00000b4a : STD_LOGIC;
signal blk00000003_sig00000b49 : STD_LOGIC;
signal blk00000003_sig00000b48 : STD_LOGIC;
signal blk00000003_sig00000b47 : STD_LOGIC;
signal blk00000003_sig00000b46 : STD_LOGIC;
signal blk00000003_sig00000b45 : STD_LOGIC;
signal blk00000003_sig00000b44 : STD_LOGIC;
signal blk00000003_sig00000b43 : STD_LOGIC;
signal blk00000003_sig00000b42 : STD_LOGIC;
signal blk00000003_sig00000b41 : STD_LOGIC;
signal blk00000003_sig00000b40 : STD_LOGIC;
signal blk00000003_sig00000b3f : STD_LOGIC;
signal blk00000003_sig00000b3e : STD_LOGIC;
signal blk00000003_sig00000b3d : STD_LOGIC;
signal blk00000003_sig00000b3c : STD_LOGIC;
signal blk00000003_sig00000b3b : STD_LOGIC;
signal blk00000003_sig00000b3a : STD_LOGIC;
signal blk00000003_sig00000b39 : STD_LOGIC;
signal blk00000003_sig00000b38 : STD_LOGIC;
signal blk00000003_sig00000b37 : STD_LOGIC;
signal blk00000003_sig00000b36 : STD_LOGIC;
signal blk00000003_sig00000b35 : STD_LOGIC;
signal blk00000003_sig00000b34 : STD_LOGIC;
signal blk00000003_sig00000b33 : STD_LOGIC;
signal blk00000003_sig00000b32 : STD_LOGIC;
signal blk00000003_sig00000b31 : STD_LOGIC;
signal blk00000003_sig00000b30 : STD_LOGIC;
signal blk00000003_sig00000b2f : STD_LOGIC;
signal blk00000003_sig00000b2e : STD_LOGIC;
signal blk00000003_sig00000b2d : STD_LOGIC;
signal blk00000003_sig00000b2c : STD_LOGIC;
signal blk00000003_sig00000b2b : STD_LOGIC;
signal blk00000003_sig00000b2a : STD_LOGIC;
signal blk00000003_sig00000b29 : STD_LOGIC;
signal blk00000003_sig00000b28 : STD_LOGIC;
signal blk00000003_sig00000b27 : STD_LOGIC;
signal blk00000003_sig00000b26 : STD_LOGIC;
signal blk00000003_sig00000b25 : STD_LOGIC;
signal blk00000003_sig00000b24 : STD_LOGIC;
signal blk00000003_sig00000b23 : STD_LOGIC;
signal blk00000003_sig00000b22 : STD_LOGIC;
signal blk00000003_sig00000b21 : STD_LOGIC;
signal blk00000003_sig00000b20 : STD_LOGIC;
signal blk00000003_sig00000b1f : STD_LOGIC;
signal blk00000003_sig00000b1e : STD_LOGIC;
signal blk00000003_sig00000b1d : STD_LOGIC;
signal blk00000003_sig00000b1c : STD_LOGIC;
signal blk00000003_sig00000b1b : STD_LOGIC;
signal blk00000003_sig00000b1a : STD_LOGIC;
signal blk00000003_sig00000b19 : STD_LOGIC;
signal blk00000003_sig00000b18 : STD_LOGIC;
signal blk00000003_sig00000b17 : STD_LOGIC;
signal blk00000003_sig00000b16 : STD_LOGIC;
signal blk00000003_sig00000b15 : STD_LOGIC;
signal blk00000003_sig00000b14 : STD_LOGIC;
signal blk00000003_sig00000b13 : STD_LOGIC;
signal blk00000003_sig00000b12 : STD_LOGIC;
signal blk00000003_sig00000b11 : STD_LOGIC;
signal blk00000003_sig00000b10 : STD_LOGIC;
signal blk00000003_sig00000b0f : STD_LOGIC;
signal blk00000003_sig00000b0e : STD_LOGIC;
signal blk00000003_sig00000b0d : STD_LOGIC;
signal blk00000003_sig00000b0c : STD_LOGIC;
signal blk00000003_sig00000b0b : STD_LOGIC;
signal blk00000003_sig00000b0a : STD_LOGIC;
signal blk00000003_sig00000b09 : STD_LOGIC;
signal blk00000003_sig00000b08 : STD_LOGIC;
signal blk00000003_sig00000b07 : STD_LOGIC;
signal blk00000003_sig00000b06 : STD_LOGIC;
signal blk00000003_sig00000b05 : STD_LOGIC;
signal blk00000003_sig00000b04 : STD_LOGIC;
signal blk00000003_sig00000b03 : STD_LOGIC;
signal blk00000003_sig00000b02 : STD_LOGIC;
signal blk00000003_sig00000b01 : STD_LOGIC;
signal blk00000003_sig00000b00 : STD_LOGIC;
signal blk00000003_sig00000aff : STD_LOGIC;
signal blk00000003_sig00000afe : STD_LOGIC;
signal blk00000003_sig00000afd : STD_LOGIC;
signal blk00000003_sig00000afc : STD_LOGIC;
signal blk00000003_sig00000afb : STD_LOGIC;
signal blk00000003_sig00000afa : STD_LOGIC;
signal blk00000003_sig00000af9 : STD_LOGIC;
signal blk00000003_sig00000af8 : STD_LOGIC;
signal blk00000003_sig00000af7 : STD_LOGIC;
signal blk00000003_sig00000af6 : STD_LOGIC;
signal blk00000003_sig00000af5 : STD_LOGIC;
signal blk00000003_sig00000af4 : STD_LOGIC;
signal blk00000003_sig00000af3 : STD_LOGIC;
signal blk00000003_sig00000af2 : STD_LOGIC;
signal blk00000003_sig00000af1 : STD_LOGIC;
signal blk00000003_sig00000af0 : STD_LOGIC;
signal blk00000003_sig00000aef : STD_LOGIC;
signal blk00000003_sig00000aee : STD_LOGIC;
signal blk00000003_sig00000aed : STD_LOGIC;
signal blk00000003_sig00000aec : STD_LOGIC;
signal blk00000003_sig00000aeb : STD_LOGIC;
signal blk00000003_sig00000aea : STD_LOGIC;
signal blk00000003_sig00000ae9 : STD_LOGIC;
signal blk00000003_sig00000ae8 : STD_LOGIC;
signal blk00000003_sig00000ae7 : STD_LOGIC;
signal blk00000003_sig00000ae6 : STD_LOGIC;
signal blk00000003_sig00000ae5 : STD_LOGIC;
signal blk00000003_sig00000ae4 : STD_LOGIC;
signal blk00000003_sig00000ae3 : STD_LOGIC;
signal blk00000003_sig00000ae2 : STD_LOGIC;
signal blk00000003_sig00000ae1 : STD_LOGIC;
signal blk00000003_sig00000ae0 : STD_LOGIC;
signal blk00000003_sig00000adf : STD_LOGIC;
signal blk00000003_sig00000ade : STD_LOGIC;
signal blk00000003_sig00000add : STD_LOGIC;
signal blk00000003_sig00000adc : STD_LOGIC;
signal blk00000003_sig00000adb : STD_LOGIC;
signal blk00000003_sig00000ada : STD_LOGIC;
signal blk00000003_sig00000ad9 : STD_LOGIC;
signal blk00000003_sig00000ad8 : STD_LOGIC;
signal blk00000003_sig00000ad7 : STD_LOGIC;
signal blk00000003_sig00000ad6 : STD_LOGIC;
signal blk00000003_sig00000ad5 : STD_LOGIC;
signal blk00000003_sig00000ad4 : STD_LOGIC;
signal blk00000003_sig00000ad3 : STD_LOGIC;
signal blk00000003_sig00000ad2 : STD_LOGIC;
signal blk00000003_sig00000ad1 : STD_LOGIC;
signal blk00000003_sig00000ad0 : STD_LOGIC;
signal blk00000003_sig00000acf : STD_LOGIC;
signal blk00000003_sig00000ace : STD_LOGIC;
signal blk00000003_sig00000acd : STD_LOGIC;
signal blk00000003_sig00000acc : STD_LOGIC;
signal blk00000003_sig00000acb : STD_LOGIC;
signal blk00000003_sig00000aca : STD_LOGIC;
signal blk00000003_sig00000ac9 : STD_LOGIC;
signal blk00000003_sig00000ac8 : STD_LOGIC;
signal blk00000003_sig00000ac7 : STD_LOGIC;
signal blk00000003_sig00000ac6 : STD_LOGIC;
signal blk00000003_sig00000ac5 : STD_LOGIC;
signal blk00000003_sig00000ac4 : STD_LOGIC;
signal blk00000003_sig00000ac3 : STD_LOGIC;
signal blk00000003_sig00000ac2 : STD_LOGIC;
signal blk00000003_sig00000ac1 : STD_LOGIC;
signal blk00000003_sig00000ac0 : STD_LOGIC;
signal blk00000003_sig00000abf : STD_LOGIC;
signal blk00000003_sig00000abe : STD_LOGIC;
signal blk00000003_sig00000abd : STD_LOGIC;
signal blk00000003_sig00000abc : STD_LOGIC;
signal blk00000003_sig00000abb : STD_LOGIC;
signal blk00000003_sig00000aba : STD_LOGIC;
signal blk00000003_sig00000ab9 : STD_LOGIC;
signal blk00000003_sig00000ab8 : STD_LOGIC;
signal blk00000003_sig00000ab7 : STD_LOGIC;
signal blk00000003_sig00000ab6 : STD_LOGIC;
signal blk00000003_sig00000ab5 : STD_LOGIC;
signal blk00000003_sig00000ab4 : STD_LOGIC;
signal blk00000003_sig00000ab3 : STD_LOGIC;
signal blk00000003_sig00000ab2 : STD_LOGIC;
signal blk00000003_sig00000ab1 : STD_LOGIC;
signal blk00000003_sig00000ab0 : STD_LOGIC;
signal blk00000003_sig00000aaf : STD_LOGIC;
signal blk00000003_sig00000aae : STD_LOGIC;
signal blk00000003_sig00000aad : STD_LOGIC;
signal blk00000003_sig00000aac : STD_LOGIC;
signal blk00000003_sig00000aab : STD_LOGIC;
signal blk00000003_sig00000aaa : STD_LOGIC;
signal blk00000003_sig00000aa9 : STD_LOGIC;
signal blk00000003_sig00000aa8 : STD_LOGIC;
signal blk00000003_sig00000aa7 : STD_LOGIC;
signal blk00000003_sig00000aa6 : STD_LOGIC;
signal blk00000003_sig00000aa5 : STD_LOGIC;
signal blk00000003_sig00000aa4 : STD_LOGIC;
signal blk00000003_sig00000aa3 : STD_LOGIC;
signal blk00000003_sig00000aa2 : STD_LOGIC;
signal blk00000003_sig00000aa1 : STD_LOGIC;
signal blk00000003_sig00000aa0 : STD_LOGIC;
signal blk00000003_sig00000a9f : STD_LOGIC;
signal blk00000003_sig00000a9e : STD_LOGIC;
signal blk00000003_sig00000a9d : STD_LOGIC;
signal blk00000003_sig00000a9c : STD_LOGIC;
signal blk00000003_sig00000a9b : STD_LOGIC;
signal blk00000003_sig00000a9a : STD_LOGIC;
signal blk00000003_sig00000a99 : STD_LOGIC;
signal blk00000003_sig00000a98 : STD_LOGIC;
signal blk00000003_sig00000a97 : STD_LOGIC;
signal blk00000003_sig00000a96 : STD_LOGIC;
signal blk00000003_sig00000a95 : STD_LOGIC;
signal blk00000003_sig00000a94 : STD_LOGIC;
signal blk00000003_sig00000a93 : STD_LOGIC;
signal blk00000003_sig00000a92 : STD_LOGIC;
signal blk00000003_sig00000a91 : STD_LOGIC;
signal blk00000003_sig00000a90 : STD_LOGIC;
signal blk00000003_sig00000a8f : STD_LOGIC;
signal blk00000003_sig00000a8e : STD_LOGIC;
signal blk00000003_sig00000a8d : STD_LOGIC;
signal blk00000003_sig00000a8c : STD_LOGIC;
signal blk00000003_sig00000a8b : STD_LOGIC;
signal blk00000003_sig00000a8a : STD_LOGIC;
signal blk00000003_sig00000a89 : STD_LOGIC;
signal blk00000003_sig00000a88 : STD_LOGIC;
signal blk00000003_sig00000a87 : STD_LOGIC;
signal blk00000003_sig00000a86 : STD_LOGIC;
signal blk00000003_sig00000a85 : STD_LOGIC;
signal blk00000003_sig00000a84 : STD_LOGIC;
signal blk00000003_sig00000a83 : STD_LOGIC;
signal blk00000003_sig00000a82 : STD_LOGIC;
signal blk00000003_sig00000a81 : STD_LOGIC;
signal blk00000003_sig00000a80 : STD_LOGIC;
signal blk00000003_sig00000a7f : STD_LOGIC;
signal blk00000003_sig00000a7e : STD_LOGIC;
signal blk00000003_sig00000a7d : STD_LOGIC;
signal blk00000003_sig00000a7c : STD_LOGIC;
signal blk00000003_sig00000a7b : STD_LOGIC;
signal blk00000003_sig00000a7a : STD_LOGIC;
signal blk00000003_sig00000a79 : STD_LOGIC;
signal blk00000003_sig00000a78 : STD_LOGIC;
signal blk00000003_sig00000a77 : STD_LOGIC;
signal blk00000003_sig00000a76 : STD_LOGIC;
signal blk00000003_sig00000a75 : STD_LOGIC;
signal blk00000003_sig00000a74 : STD_LOGIC;
signal blk00000003_sig00000a73 : STD_LOGIC;
signal blk00000003_sig00000a72 : STD_LOGIC;
signal blk00000003_sig00000a71 : STD_LOGIC;
signal blk00000003_sig00000a70 : STD_LOGIC;
signal blk00000003_sig00000a6f : STD_LOGIC;
signal blk00000003_sig00000a6e : STD_LOGIC;
signal blk00000003_sig00000a6d : STD_LOGIC;
signal blk00000003_sig00000a6c : STD_LOGIC;
signal blk00000003_sig00000a6b : STD_LOGIC;
signal blk00000003_sig00000a6a : STD_LOGIC;
signal blk00000003_sig00000a69 : STD_LOGIC;
signal blk00000003_sig00000a68 : STD_LOGIC;
signal blk00000003_sig00000a67 : STD_LOGIC;
signal blk00000003_sig00000a66 : STD_LOGIC;
signal blk00000003_sig00000a65 : STD_LOGIC;
signal blk00000003_sig00000a64 : STD_LOGIC;
signal blk00000003_sig00000a63 : STD_LOGIC;
signal blk00000003_sig00000a62 : STD_LOGIC;
signal blk00000003_sig00000a61 : STD_LOGIC;
signal blk00000003_sig00000a60 : STD_LOGIC;
signal blk00000003_sig00000a5f : STD_LOGIC;
signal blk00000003_sig00000a5e : STD_LOGIC;
signal blk00000003_sig00000a5d : STD_LOGIC;
signal blk00000003_sig00000a5c : STD_LOGIC;
signal blk00000003_sig00000a5b : STD_LOGIC;
signal blk00000003_sig00000a5a : STD_LOGIC;
signal blk00000003_sig00000a59 : STD_LOGIC;
signal blk00000003_sig00000a58 : STD_LOGIC;
signal blk00000003_sig00000a57 : STD_LOGIC;
signal blk00000003_sig00000a56 : STD_LOGIC;
signal blk00000003_sig00000a55 : STD_LOGIC;
signal blk00000003_sig00000a54 : STD_LOGIC;
signal blk00000003_sig00000a53 : STD_LOGIC;
signal blk00000003_sig00000a52 : STD_LOGIC;
signal blk00000003_sig00000a51 : STD_LOGIC;
signal blk00000003_sig00000a50 : STD_LOGIC;
signal blk00000003_sig00000a4f : STD_LOGIC;
signal blk00000003_sig00000a4e : STD_LOGIC;
signal blk00000003_sig00000a4d : STD_LOGIC;
signal blk00000003_sig00000a4c : STD_LOGIC;
signal blk00000003_sig00000a4b : STD_LOGIC;
signal blk00000003_sig00000a4a : STD_LOGIC;
signal blk00000003_sig00000a49 : STD_LOGIC;
signal blk00000003_sig00000a48 : STD_LOGIC;
signal blk00000003_sig00000a47 : STD_LOGIC;
signal blk00000003_sig00000a46 : STD_LOGIC;
signal blk00000003_sig00000a45 : STD_LOGIC;
signal blk00000003_sig00000a44 : STD_LOGIC;
signal blk00000003_sig00000a43 : STD_LOGIC;
signal blk00000003_sig00000a42 : STD_LOGIC;
signal blk00000003_sig00000a41 : STD_LOGIC;
signal blk00000003_sig00000a40 : STD_LOGIC;
signal blk00000003_sig00000a3f : STD_LOGIC;
signal blk00000003_sig00000a3e : STD_LOGIC;
signal blk00000003_sig00000a3d : STD_LOGIC;
signal blk00000003_sig00000a3c : STD_LOGIC;
signal blk00000003_sig00000a3b : STD_LOGIC;
signal blk00000003_sig00000a3a : STD_LOGIC;
signal blk00000003_sig00000a39 : STD_LOGIC;
signal blk00000003_sig00000a38 : STD_LOGIC;
signal blk00000003_sig00000a37 : STD_LOGIC;
signal blk00000003_sig00000a36 : STD_LOGIC;
signal blk00000003_sig00000a35 : STD_LOGIC;
signal blk00000003_sig00000a34 : STD_LOGIC;
signal blk00000003_sig00000a33 : STD_LOGIC;
signal blk00000003_sig00000a32 : STD_LOGIC;
signal blk00000003_sig00000a31 : STD_LOGIC;
signal blk00000003_sig00000a30 : STD_LOGIC;
signal blk00000003_sig00000a2f : STD_LOGIC;
signal blk00000003_sig00000a2e : STD_LOGIC;
signal blk00000003_sig00000a2d : STD_LOGIC;
signal blk00000003_sig00000a2c : STD_LOGIC;
signal blk00000003_sig00000a2b : STD_LOGIC;
signal blk00000003_sig00000a2a : STD_LOGIC;
signal blk00000003_sig00000a29 : STD_LOGIC;
signal blk00000003_sig00000a28 : STD_LOGIC;
signal blk00000003_sig00000a27 : STD_LOGIC;
signal blk00000003_sig00000a26 : STD_LOGIC;
signal blk00000003_sig00000a25 : STD_LOGIC;
signal blk00000003_sig00000a24 : STD_LOGIC;
signal blk00000003_sig00000a23 : STD_LOGIC;
signal blk00000003_sig00000a22 : STD_LOGIC;
signal blk00000003_sig00000a21 : STD_LOGIC;
signal blk00000003_sig00000a20 : STD_LOGIC;
signal blk00000003_sig00000a1f : STD_LOGIC;
signal blk00000003_sig00000a1e : STD_LOGIC;
signal blk00000003_sig00000a1d : STD_LOGIC;
signal blk00000003_sig00000a1c : STD_LOGIC;
signal blk00000003_sig00000a1b : STD_LOGIC;
signal blk00000003_sig00000a1a : STD_LOGIC;
signal blk00000003_sig00000a19 : STD_LOGIC;
signal blk00000003_sig00000a18 : STD_LOGIC;
signal blk00000003_sig00000a17 : STD_LOGIC;
signal blk00000003_sig00000a16 : STD_LOGIC;
signal blk00000003_sig00000a15 : STD_LOGIC;
signal blk00000003_sig00000a14 : STD_LOGIC;
signal blk00000003_sig00000a13 : STD_LOGIC;
signal blk00000003_sig00000a12 : STD_LOGIC;
signal blk00000003_sig00000a11 : STD_LOGIC;
signal blk00000003_sig00000a10 : STD_LOGIC;
signal blk00000003_sig00000a0f : STD_LOGIC;
signal blk00000003_sig00000a0e : STD_LOGIC;
signal blk00000003_sig00000a0d : STD_LOGIC;
signal blk00000003_sig00000a0c : STD_LOGIC;
signal blk00000003_sig00000a0b : STD_LOGIC;
signal blk00000003_sig00000a0a : STD_LOGIC;
signal blk00000003_sig00000a09 : STD_LOGIC;
signal blk00000003_sig00000a08 : STD_LOGIC;
signal blk00000003_sig00000a07 : STD_LOGIC;
signal blk00000003_sig00000a06 : STD_LOGIC;
signal blk00000003_sig00000a05 : STD_LOGIC;
signal blk00000003_sig00000a04 : STD_LOGIC;
signal blk00000003_sig00000a03 : STD_LOGIC;
signal blk00000003_sig00000a02 : STD_LOGIC;
signal blk00000003_sig00000a01 : STD_LOGIC;
signal blk00000003_sig00000a00 : STD_LOGIC;
signal blk00000003_sig000009ff : STD_LOGIC;
signal blk00000003_sig000009fe : STD_LOGIC;
signal blk00000003_sig000009fd : STD_LOGIC;
signal blk00000003_sig000009fc : STD_LOGIC;
signal blk00000003_sig000009fb : STD_LOGIC;
signal blk00000003_sig000009fa : STD_LOGIC;
signal blk00000003_sig000009f9 : STD_LOGIC;
signal blk00000003_sig000009f8 : STD_LOGIC;
signal blk00000003_sig000009f7 : STD_LOGIC;
signal blk00000003_sig000009f6 : STD_LOGIC;
signal blk00000003_sig000009f5 : STD_LOGIC;
signal blk00000003_sig000009f4 : STD_LOGIC;
signal blk00000003_sig000009f3 : STD_LOGIC;
signal blk00000003_sig000009f2 : STD_LOGIC;
signal blk00000003_sig000009f1 : STD_LOGIC;
signal blk00000003_sig000009f0 : STD_LOGIC;
signal blk00000003_sig000009ef : STD_LOGIC;
signal blk00000003_sig000009ee : STD_LOGIC;
signal blk00000003_sig000009ed : STD_LOGIC;
signal blk00000003_sig000009ec : STD_LOGIC;
signal blk00000003_sig000009eb : STD_LOGIC;
signal blk00000003_sig000009ea : STD_LOGIC;
signal blk00000003_sig000009e9 : STD_LOGIC;
signal blk00000003_sig000009e8 : STD_LOGIC;
signal blk00000003_sig000009e7 : STD_LOGIC;
signal blk00000003_sig000009e6 : STD_LOGIC;
signal blk00000003_sig000009e5 : STD_LOGIC;
signal blk00000003_sig000009e4 : STD_LOGIC;
signal blk00000003_sig000009e3 : STD_LOGIC;
signal blk00000003_sig000009e2 : STD_LOGIC;
signal blk00000003_sig000009e1 : STD_LOGIC;
signal blk00000003_sig000009e0 : STD_LOGIC;
signal blk00000003_sig000009df : STD_LOGIC;
signal blk00000003_sig000009de : STD_LOGIC;
signal blk00000003_sig000009dd : STD_LOGIC;
signal blk00000003_sig000009dc : STD_LOGIC;
signal blk00000003_sig000009db : STD_LOGIC;
signal blk00000003_sig000009da : STD_LOGIC;
signal blk00000003_sig000009d9 : STD_LOGIC;
signal blk00000003_sig000009d8 : STD_LOGIC;
signal blk00000003_sig000009d7 : STD_LOGIC;
signal blk00000003_sig000009d6 : STD_LOGIC;
signal blk00000003_sig000009d5 : STD_LOGIC;
signal blk00000003_sig000009d4 : STD_LOGIC;
signal blk00000003_sig000009d3 : STD_LOGIC;
signal blk00000003_sig000009d2 : STD_LOGIC;
signal blk00000003_sig000009d1 : STD_LOGIC;
signal blk00000003_sig000009d0 : STD_LOGIC;
signal blk00000003_sig000009cf : STD_LOGIC;
signal blk00000003_sig000009ce : STD_LOGIC;
signal blk00000003_sig000009cd : STD_LOGIC;
signal blk00000003_sig000009cc : STD_LOGIC;
signal blk00000003_sig000009cb : STD_LOGIC;
signal blk00000003_sig000009ca : STD_LOGIC;
signal blk00000003_sig000009c9 : STD_LOGIC;
signal blk00000003_sig000009c8 : STD_LOGIC;
signal blk00000003_sig000009c7 : STD_LOGIC;
signal blk00000003_sig000009c6 : STD_LOGIC;
signal blk00000003_sig000009c5 : STD_LOGIC;
signal blk00000003_sig000009c4 : STD_LOGIC;
signal blk00000003_sig000009c3 : STD_LOGIC;
signal blk00000003_sig000009c2 : STD_LOGIC;
signal blk00000003_sig000009c1 : STD_LOGIC;
signal blk00000003_sig000009c0 : STD_LOGIC;
signal blk00000003_sig000009bf : STD_LOGIC;
signal blk00000003_sig000009be : STD_LOGIC;
signal blk00000003_sig000009bd : STD_LOGIC;
signal blk00000003_sig000009bc : STD_LOGIC;
signal blk00000003_sig000009bb : STD_LOGIC;
signal blk00000003_sig000009ba : STD_LOGIC;
signal blk00000003_sig000009b9 : STD_LOGIC;
signal blk00000003_sig000009b8 : STD_LOGIC;
signal blk00000003_sig000009b7 : STD_LOGIC;
signal blk00000003_sig000009b6 : STD_LOGIC;
signal blk00000003_sig000009b5 : STD_LOGIC;
signal blk00000003_sig000009b4 : STD_LOGIC;
signal blk00000003_sig000009b3 : STD_LOGIC;
signal blk00000003_sig000009b2 : STD_LOGIC;
signal blk00000003_sig000009b1 : STD_LOGIC;
signal blk00000003_sig000009b0 : STD_LOGIC;
signal blk00000003_sig000009af : STD_LOGIC;
signal blk00000003_sig000009ae : STD_LOGIC;
signal blk00000003_sig000009ad : STD_LOGIC;
signal blk00000003_sig000009ac : STD_LOGIC;
signal blk00000003_sig000009ab : STD_LOGIC;
signal blk00000003_sig000009aa : STD_LOGIC;
signal blk00000003_sig000009a9 : STD_LOGIC;
signal blk00000003_sig000009a8 : STD_LOGIC;
signal blk00000003_sig000009a7 : STD_LOGIC;
signal blk00000003_sig000009a6 : STD_LOGIC;
signal blk00000003_sig000009a5 : STD_LOGIC;
signal blk00000003_sig000009a4 : STD_LOGIC;
signal blk00000003_sig000009a3 : STD_LOGIC;
signal blk00000003_sig000009a2 : STD_LOGIC;
signal blk00000003_sig000009a1 : STD_LOGIC;
signal blk00000003_sig000009a0 : STD_LOGIC;
signal blk00000003_sig0000099f : STD_LOGIC;
signal blk00000003_sig0000099e : STD_LOGIC;
signal blk00000003_sig0000099d : STD_LOGIC;
signal blk00000003_sig0000099c : STD_LOGIC;
signal blk00000003_sig0000099b : STD_LOGIC;
signal blk00000003_sig0000099a : STD_LOGIC;
signal blk00000003_sig00000999 : STD_LOGIC;
signal blk00000003_sig00000998 : STD_LOGIC;
signal blk00000003_sig00000997 : STD_LOGIC;
signal blk00000003_sig00000996 : STD_LOGIC;
signal blk00000003_sig00000995 : STD_LOGIC;
signal blk00000003_sig00000994 : STD_LOGIC;
signal blk00000003_sig00000993 : STD_LOGIC;
signal blk00000003_sig00000992 : STD_LOGIC;
signal blk00000003_sig00000991 : STD_LOGIC;
signal blk00000003_sig00000990 : STD_LOGIC;
signal blk00000003_sig0000098f : STD_LOGIC;
signal blk00000003_sig0000098e : STD_LOGIC;
signal blk00000003_sig0000098d : STD_LOGIC;
signal blk00000003_sig0000098c : STD_LOGIC;
signal blk00000003_sig0000098b : STD_LOGIC;
signal blk00000003_sig0000098a : STD_LOGIC;
signal blk00000003_sig00000989 : STD_LOGIC;
signal blk00000003_sig00000988 : STD_LOGIC;
signal blk00000003_sig00000987 : STD_LOGIC;
signal blk00000003_sig00000986 : STD_LOGIC;
signal blk00000003_sig00000985 : STD_LOGIC;
signal blk00000003_sig00000984 : STD_LOGIC;
signal blk00000003_sig00000983 : STD_LOGIC;
signal blk00000003_sig00000982 : STD_LOGIC;
signal blk00000003_sig00000981 : STD_LOGIC;
signal blk00000003_sig00000980 : STD_LOGIC;
signal blk00000003_sig0000097f : STD_LOGIC;
signal blk00000003_sig0000097e : STD_LOGIC;
signal blk00000003_sig0000097d : STD_LOGIC;
signal blk00000003_sig0000097c : STD_LOGIC;
signal blk00000003_sig0000097b : STD_LOGIC;
signal blk00000003_sig0000097a : STD_LOGIC;
signal blk00000003_sig00000979 : STD_LOGIC;
signal blk00000003_sig00000978 : STD_LOGIC;
signal blk00000003_sig00000977 : STD_LOGIC;
signal blk00000003_sig00000976 : STD_LOGIC;
signal blk00000003_sig00000975 : STD_LOGIC;
signal blk00000003_sig00000974 : STD_LOGIC;
signal blk00000003_sig00000973 : STD_LOGIC;
signal blk00000003_sig00000972 : STD_LOGIC;
signal blk00000003_sig00000971 : STD_LOGIC;
signal blk00000003_sig00000970 : STD_LOGIC;
signal blk00000003_sig0000096f : STD_LOGIC;
signal blk00000003_sig0000096e : STD_LOGIC;
signal blk00000003_sig0000096d : STD_LOGIC;
signal blk00000003_sig0000096c : STD_LOGIC;
signal blk00000003_sig0000096b : STD_LOGIC;
signal blk00000003_sig0000096a : STD_LOGIC;
signal blk00000003_sig00000969 : STD_LOGIC;
signal blk00000003_sig00000968 : STD_LOGIC;
signal blk00000003_sig00000967 : STD_LOGIC;
signal blk00000003_sig00000966 : STD_LOGIC;
signal blk00000003_sig00000965 : STD_LOGIC;
signal blk00000003_sig00000964 : STD_LOGIC;
signal blk00000003_sig00000963 : STD_LOGIC;
signal blk00000003_sig00000962 : STD_LOGIC;
signal blk00000003_sig00000961 : STD_LOGIC;
signal blk00000003_sig00000960 : STD_LOGIC;
signal blk00000003_sig0000095f : STD_LOGIC;
signal blk00000003_sig0000095e : STD_LOGIC;
signal blk00000003_sig0000095d : STD_LOGIC;
signal blk00000003_sig0000095c : STD_LOGIC;
signal blk00000003_sig0000095b : STD_LOGIC;
signal blk00000003_sig0000095a : STD_LOGIC;
signal blk00000003_sig00000959 : STD_LOGIC;
signal blk00000003_sig00000958 : STD_LOGIC;
signal blk00000003_sig00000957 : STD_LOGIC;
signal blk00000003_sig00000956 : STD_LOGIC;
signal blk00000003_sig00000955 : STD_LOGIC;
signal blk00000003_sig00000954 : STD_LOGIC;
signal blk00000003_sig00000953 : STD_LOGIC;
signal blk00000003_sig00000952 : STD_LOGIC;
signal blk00000003_sig00000951 : STD_LOGIC;
signal blk00000003_sig00000950 : STD_LOGIC;
signal blk00000003_sig0000094f : STD_LOGIC;
signal blk00000003_sig0000094e : STD_LOGIC;
signal blk00000003_sig0000094d : STD_LOGIC;
signal blk00000003_sig0000094c : STD_LOGIC;
signal blk00000003_sig0000094b : STD_LOGIC;
signal blk00000003_sig0000094a : STD_LOGIC;
signal blk00000003_sig00000949 : STD_LOGIC;
signal blk00000003_sig00000948 : STD_LOGIC;
signal blk00000003_sig00000947 : STD_LOGIC;
signal blk00000003_sig00000946 : STD_LOGIC;
signal blk00000003_sig00000945 : STD_LOGIC;
signal blk00000003_sig00000944 : STD_LOGIC;
signal blk00000003_sig00000943 : STD_LOGIC;
signal blk00000003_sig00000942 : STD_LOGIC;
signal blk00000003_sig00000941 : STD_LOGIC;
signal blk00000003_sig00000940 : STD_LOGIC;
signal blk00000003_sig0000093f : STD_LOGIC;
signal blk00000003_sig0000093e : STD_LOGIC;
signal blk00000003_sig0000093d : STD_LOGIC;
signal blk00000003_sig0000093c : STD_LOGIC;
signal blk00000003_sig0000093b : STD_LOGIC;
signal blk00000003_sig0000093a : STD_LOGIC;
signal blk00000003_sig00000939 : STD_LOGIC;
signal blk00000003_sig00000938 : STD_LOGIC;
signal blk00000003_sig00000937 : STD_LOGIC;
signal blk00000003_sig00000936 : STD_LOGIC;
signal blk00000003_sig00000935 : STD_LOGIC;
signal blk00000003_sig00000934 : STD_LOGIC;
signal blk00000003_sig00000933 : STD_LOGIC;
signal blk00000003_sig00000932 : STD_LOGIC;
signal blk00000003_sig00000931 : STD_LOGIC;
signal blk00000003_sig00000930 : STD_LOGIC;
signal blk00000003_sig0000092f : STD_LOGIC;
signal blk00000003_sig0000092e : STD_LOGIC;
signal blk00000003_sig0000092d : STD_LOGIC;
signal blk00000003_sig0000092c : STD_LOGIC;
signal blk00000003_sig0000092b : STD_LOGIC;
signal blk00000003_sig0000092a : STD_LOGIC;
signal blk00000003_sig00000929 : STD_LOGIC;
signal blk00000003_sig00000928 : STD_LOGIC;
signal blk00000003_sig00000927 : STD_LOGIC;
signal blk00000003_sig00000926 : STD_LOGIC;
signal blk00000003_sig00000925 : STD_LOGIC;
signal blk00000003_sig00000924 : STD_LOGIC;
signal blk00000003_sig00000923 : STD_LOGIC;
signal blk00000003_sig00000922 : STD_LOGIC;
signal blk00000003_sig00000921 : STD_LOGIC;
signal blk00000003_sig00000920 : STD_LOGIC;
signal blk00000003_sig0000091f : STD_LOGIC;
signal blk00000003_sig0000091e : STD_LOGIC;
signal blk00000003_sig0000091d : STD_LOGIC;
signal blk00000003_sig0000091c : STD_LOGIC;
signal blk00000003_sig0000091b : STD_LOGIC;
signal blk00000003_sig0000091a : STD_LOGIC;
signal blk00000003_sig00000919 : STD_LOGIC;
signal blk00000003_sig00000918 : STD_LOGIC;
signal blk00000003_sig00000917 : STD_LOGIC;
signal blk00000003_sig00000916 : STD_LOGIC;
signal blk00000003_sig00000915 : STD_LOGIC;
signal blk00000003_sig00000914 : STD_LOGIC;
signal blk00000003_sig00000913 : STD_LOGIC;
signal blk00000003_sig00000912 : STD_LOGIC;
signal blk00000003_sig00000911 : STD_LOGIC;
signal blk00000003_sig00000910 : STD_LOGIC;
signal blk00000003_sig0000090f : STD_LOGIC;
signal blk00000003_sig0000090e : STD_LOGIC;
signal blk00000003_sig0000090d : STD_LOGIC;
signal blk00000003_sig0000090c : STD_LOGIC;
signal blk00000003_sig0000090b : STD_LOGIC;
signal blk00000003_sig0000090a : STD_LOGIC;
signal blk00000003_sig00000909 : STD_LOGIC;
signal blk00000003_sig00000908 : STD_LOGIC;
signal blk00000003_sig00000907 : STD_LOGIC;
signal blk00000003_sig00000906 : STD_LOGIC;
signal blk00000003_sig00000905 : STD_LOGIC;
signal blk00000003_sig00000904 : STD_LOGIC;
signal blk00000003_sig00000903 : STD_LOGIC;
signal blk00000003_sig00000902 : STD_LOGIC;
signal blk00000003_sig00000901 : STD_LOGIC;
signal blk00000003_sig00000900 : STD_LOGIC;
signal blk00000003_sig000008ff : STD_LOGIC;
signal blk00000003_sig000008fe : STD_LOGIC;
signal blk00000003_sig000008fd : STD_LOGIC;
signal blk00000003_sig000008fc : STD_LOGIC;
signal blk00000003_sig000008fb : STD_LOGIC;
signal blk00000003_sig000008fa : STD_LOGIC;
signal blk00000003_sig000008f9 : STD_LOGIC;
signal blk00000003_sig000008f8 : STD_LOGIC;
signal blk00000003_sig000008f7 : STD_LOGIC;
signal blk00000003_sig000008f6 : STD_LOGIC;
signal blk00000003_sig000008f5 : STD_LOGIC;
signal blk00000003_sig000008f4 : STD_LOGIC;
signal blk00000003_sig000008f3 : STD_LOGIC;
signal blk00000003_sig000008f2 : STD_LOGIC;
signal blk00000003_sig000008f1 : STD_LOGIC;
signal blk00000003_sig000008f0 : STD_LOGIC;
signal blk00000003_sig000008ef : STD_LOGIC;
signal blk00000003_sig000008ee : STD_LOGIC;
signal blk00000003_sig000008ed : STD_LOGIC;
signal blk00000003_sig000008ec : STD_LOGIC;
signal blk00000003_sig000008eb : STD_LOGIC;
signal blk00000003_sig000008ea : STD_LOGIC;
signal blk00000003_sig000008e9 : STD_LOGIC;
signal blk00000003_sig000008e8 : STD_LOGIC;
signal blk00000003_sig000008e7 : STD_LOGIC;
signal blk00000003_sig000008e6 : STD_LOGIC;
signal blk00000003_sig000008e5 : STD_LOGIC;
signal blk00000003_sig000008e4 : STD_LOGIC;
signal blk00000003_sig000008e3 : STD_LOGIC;
signal blk00000003_sig000008e2 : STD_LOGIC;
signal blk00000003_sig000008e1 : STD_LOGIC;
signal blk00000003_sig000008e0 : STD_LOGIC;
signal blk00000003_sig000008df : STD_LOGIC;
signal blk00000003_sig000008de : STD_LOGIC;
signal blk00000003_sig000008dd : STD_LOGIC;
signal blk00000003_sig000008dc : STD_LOGIC;
signal blk00000003_sig000008db : STD_LOGIC;
signal blk00000003_sig000008da : STD_LOGIC;
signal blk00000003_sig000008d9 : STD_LOGIC;
signal blk00000003_sig000008d8 : STD_LOGIC;
signal blk00000003_sig000008d7 : STD_LOGIC;
signal blk00000003_sig000008d6 : STD_LOGIC;
signal blk00000003_sig000008d5 : STD_LOGIC;
signal blk00000003_sig000008d4 : STD_LOGIC;
signal blk00000003_sig000008d3 : STD_LOGIC;
signal blk00000003_sig000008d2 : STD_LOGIC;
signal blk00000003_sig000008d1 : STD_LOGIC;
signal blk00000003_sig000008d0 : STD_LOGIC;
signal blk00000003_sig000008cf : STD_LOGIC;
signal blk00000003_sig000008ce : STD_LOGIC;
signal blk00000003_sig000008cd : STD_LOGIC;
signal blk00000003_sig000008cc : STD_LOGIC;
signal blk00000003_sig000008cb : STD_LOGIC;
signal blk00000003_sig000008ca : STD_LOGIC;
signal blk00000003_sig000008c9 : STD_LOGIC;
signal blk00000003_sig000008c8 : STD_LOGIC;
signal blk00000003_sig000008c7 : STD_LOGIC;
signal blk00000003_sig000008c6 : STD_LOGIC;
signal blk00000003_sig000008c5 : STD_LOGIC;
signal blk00000003_sig000008c4 : STD_LOGIC;
signal blk00000003_sig000008c3 : STD_LOGIC;
signal blk00000003_sig000008c2 : STD_LOGIC;
signal blk00000003_sig000008c1 : STD_LOGIC;
signal blk00000003_sig000008c0 : STD_LOGIC;
signal blk00000003_sig000008bf : STD_LOGIC;
signal blk00000003_sig000008be : STD_LOGIC;
signal blk00000003_sig000008bd : STD_LOGIC;
signal blk00000003_sig000008bc : STD_LOGIC;
signal blk00000003_sig000008bb : STD_LOGIC;
signal blk00000003_sig000008ba : STD_LOGIC;
signal blk00000003_sig000008b9 : STD_LOGIC;
signal blk00000003_sig000008b8 : STD_LOGIC;
signal blk00000003_sig000008b7 : STD_LOGIC;
signal blk00000003_sig000008b6 : STD_LOGIC;
signal blk00000003_sig000008b5 : STD_LOGIC;
signal blk00000003_sig000008b4 : STD_LOGIC;
signal blk00000003_sig000008b3 : STD_LOGIC;
signal blk00000003_sig000008b2 : STD_LOGIC;
signal blk00000003_sig000008b1 : STD_LOGIC;
signal blk00000003_sig000008b0 : STD_LOGIC;
signal blk00000003_sig000008af : STD_LOGIC;
signal blk00000003_sig000008ae : STD_LOGIC;
signal blk00000003_sig000008ad : STD_LOGIC;
signal blk00000003_sig000008ac : STD_LOGIC;
signal blk00000003_sig000008ab : STD_LOGIC;
signal blk00000003_sig000008aa : STD_LOGIC;
signal blk00000003_sig000008a9 : STD_LOGIC;
signal blk00000003_sig000008a8 : STD_LOGIC;
signal blk00000003_sig000008a7 : STD_LOGIC;
signal blk00000003_sig000008a6 : STD_LOGIC;
signal blk00000003_sig000008a5 : STD_LOGIC;
signal blk00000003_sig000008a4 : STD_LOGIC;
signal blk00000003_sig000008a3 : STD_LOGIC;
signal blk00000003_sig000008a2 : STD_LOGIC;
signal blk00000003_sig000008a1 : STD_LOGIC;
signal blk00000003_sig000008a0 : STD_LOGIC;
signal blk00000003_sig0000089f : STD_LOGIC;
signal blk00000003_sig0000089e : STD_LOGIC;
signal blk00000003_sig0000089d : STD_LOGIC;
signal blk00000003_sig0000089c : STD_LOGIC;
signal blk00000003_sig0000089b : STD_LOGIC;
signal blk00000003_sig0000089a : STD_LOGIC;
signal blk00000003_sig00000899 : STD_LOGIC;
signal blk00000003_sig00000898 : STD_LOGIC;
signal blk00000003_sig00000897 : STD_LOGIC;
signal blk00000003_sig00000896 : STD_LOGIC;
signal blk00000003_sig00000895 : STD_LOGIC;
signal blk00000003_sig00000894 : STD_LOGIC;
signal blk00000003_sig00000893 : STD_LOGIC;
signal blk00000003_sig00000892 : STD_LOGIC;
signal blk00000003_sig00000891 : STD_LOGIC;
signal blk00000003_sig00000890 : STD_LOGIC;
signal blk00000003_sig0000088f : STD_LOGIC;
signal blk00000003_sig0000088e : STD_LOGIC;
signal blk00000003_sig0000088d : STD_LOGIC;
signal blk00000003_sig0000088c : STD_LOGIC;
signal blk00000003_sig0000088b : STD_LOGIC;
signal blk00000003_sig0000088a : STD_LOGIC;
signal blk00000003_sig00000889 : STD_LOGIC;
signal blk00000003_sig00000888 : STD_LOGIC;
signal blk00000003_sig00000887 : STD_LOGIC;
signal blk00000003_sig00000886 : STD_LOGIC;
signal blk00000003_sig00000885 : STD_LOGIC;
signal blk00000003_sig00000884 : STD_LOGIC;
signal blk00000003_sig00000883 : STD_LOGIC;
signal blk00000003_sig00000882 : STD_LOGIC;
signal blk00000003_sig00000881 : STD_LOGIC;
signal blk00000003_sig00000880 : STD_LOGIC;
signal blk00000003_sig0000087f : STD_LOGIC;
signal blk00000003_sig0000087e : STD_LOGIC;
signal blk00000003_sig0000087d : STD_LOGIC;
signal blk00000003_sig0000087c : STD_LOGIC;
signal blk00000003_sig0000087b : STD_LOGIC;
signal blk00000003_sig0000087a : STD_LOGIC;
signal blk00000003_sig00000879 : STD_LOGIC;
signal blk00000003_sig00000878 : STD_LOGIC;
signal blk00000003_sig00000877 : STD_LOGIC;
signal blk00000003_sig00000876 : STD_LOGIC;
signal blk00000003_sig00000875 : STD_LOGIC;
signal blk00000003_sig00000874 : STD_LOGIC;
signal blk00000003_sig00000873 : STD_LOGIC;
signal blk00000003_sig00000872 : STD_LOGIC;
signal blk00000003_sig00000871 : STD_LOGIC;
signal blk00000003_sig00000870 : STD_LOGIC;
signal blk00000003_sig0000086f : STD_LOGIC;
signal blk00000003_sig0000086e : STD_LOGIC;
signal blk00000003_sig0000086d : STD_LOGIC;
signal blk00000003_sig0000086c : STD_LOGIC;
signal blk00000003_sig0000086b : STD_LOGIC;
signal blk00000003_sig0000086a : STD_LOGIC;
signal blk00000003_sig00000869 : STD_LOGIC;
signal blk00000003_sig00000868 : STD_LOGIC;
signal blk00000003_sig00000867 : STD_LOGIC;
signal blk00000003_sig00000866 : STD_LOGIC;
signal blk00000003_sig00000865 : STD_LOGIC;
signal blk00000003_sig00000864 : STD_LOGIC;
signal blk00000003_sig00000863 : STD_LOGIC;
signal blk00000003_sig00000862 : STD_LOGIC;
signal blk00000003_sig00000861 : STD_LOGIC;
signal blk00000003_sig00000860 : STD_LOGIC;
signal blk00000003_sig0000085f : STD_LOGIC;
signal blk00000003_sig0000085e : STD_LOGIC;
signal blk00000003_sig0000085d : STD_LOGIC;
signal blk00000003_sig0000085c : STD_LOGIC;
signal blk00000003_sig0000085b : STD_LOGIC;
signal blk00000003_sig0000085a : STD_LOGIC;
signal blk00000003_sig00000859 : STD_LOGIC;
signal blk00000003_sig00000858 : STD_LOGIC;
signal blk00000003_sig00000857 : STD_LOGIC;
signal blk00000003_sig00000856 : STD_LOGIC;
signal blk00000003_sig00000855 : STD_LOGIC;
signal blk00000003_sig00000854 : STD_LOGIC;
signal blk00000003_sig00000853 : STD_LOGIC;
signal blk00000003_sig00000852 : STD_LOGIC;
signal blk00000003_sig00000851 : STD_LOGIC;
signal blk00000003_sig00000850 : STD_LOGIC;
signal blk00000003_sig0000084f : STD_LOGIC;
signal blk00000003_sig0000084e : STD_LOGIC;
signal blk00000003_sig0000084d : STD_LOGIC;
signal blk00000003_sig0000084c : STD_LOGIC;
signal blk00000003_sig0000084b : STD_LOGIC;
signal blk00000003_sig0000084a : STD_LOGIC;
signal blk00000003_sig00000849 : STD_LOGIC;
signal blk00000003_sig00000848 : STD_LOGIC;
signal blk00000003_sig00000847 : STD_LOGIC;
signal blk00000003_sig00000846 : STD_LOGIC;
signal blk00000003_sig00000845 : STD_LOGIC;
signal blk00000003_sig00000844 : STD_LOGIC;
signal blk00000003_sig00000843 : STD_LOGIC;
signal blk00000003_sig00000842 : STD_LOGIC;
signal blk00000003_sig00000841 : STD_LOGIC;
signal blk00000003_sig00000840 : STD_LOGIC;
signal blk00000003_sig0000083f : STD_LOGIC;
signal blk00000003_sig0000083e : STD_LOGIC;
signal blk00000003_sig0000083d : STD_LOGIC;
signal blk00000003_sig0000083c : STD_LOGIC;
signal blk00000003_sig0000083b : STD_LOGIC;
signal blk00000003_sig0000083a : STD_LOGIC;
signal blk00000003_sig00000839 : STD_LOGIC;
signal blk00000003_sig00000838 : STD_LOGIC;
signal blk00000003_sig00000837 : STD_LOGIC;
signal blk00000003_sig00000836 : STD_LOGIC;
signal blk00000003_sig00000835 : STD_LOGIC;
signal blk00000003_sig00000834 : STD_LOGIC;
signal blk00000003_sig00000833 : STD_LOGIC;
signal blk00000003_sig00000832 : STD_LOGIC;
signal blk00000003_sig00000831 : STD_LOGIC;
signal blk00000003_sig00000830 : STD_LOGIC;
signal blk00000003_sig0000082f : STD_LOGIC;
signal blk00000003_sig0000082e : STD_LOGIC;
signal blk00000003_sig0000082d : STD_LOGIC;
signal blk00000003_sig0000082c : STD_LOGIC;
signal blk00000003_sig0000082b : STD_LOGIC;
signal blk00000003_sig0000082a : STD_LOGIC;
signal blk00000003_sig00000829 : STD_LOGIC;
signal blk00000003_sig00000828 : STD_LOGIC;
signal blk00000003_sig00000827 : STD_LOGIC;
signal blk00000003_sig00000826 : STD_LOGIC;
signal blk00000003_sig00000825 : STD_LOGIC;
signal blk00000003_sig00000824 : STD_LOGIC;
signal blk00000003_sig00000823 : STD_LOGIC;
signal blk00000003_sig00000822 : STD_LOGIC;
signal blk00000003_sig00000821 : STD_LOGIC;
signal blk00000003_sig00000820 : STD_LOGIC;
signal blk00000003_sig0000081f : STD_LOGIC;
signal blk00000003_sig0000081e : STD_LOGIC;
signal blk00000003_sig0000081d : STD_LOGIC;
signal blk00000003_sig0000081c : STD_LOGIC;
signal blk00000003_sig0000081b : STD_LOGIC;
signal blk00000003_sig0000081a : STD_LOGIC;
signal blk00000003_sig00000819 : STD_LOGIC;
signal blk00000003_sig00000818 : STD_LOGIC;
signal blk00000003_sig00000817 : STD_LOGIC;
signal blk00000003_sig00000816 : STD_LOGIC;
signal blk00000003_sig00000815 : STD_LOGIC;
signal blk00000003_sig00000814 : STD_LOGIC;
signal blk00000003_sig00000813 : STD_LOGIC;
signal blk00000003_sig00000812 : STD_LOGIC;
signal blk00000003_sig00000811 : STD_LOGIC;
signal blk00000003_sig00000810 : STD_LOGIC;
signal blk00000003_sig0000080f : STD_LOGIC;
signal blk00000003_sig0000080e : STD_LOGIC;
signal blk00000003_sig0000080d : STD_LOGIC;
signal blk00000003_sig0000080c : STD_LOGIC;
signal blk00000003_sig0000080b : STD_LOGIC;
signal blk00000003_sig0000080a : STD_LOGIC;
signal blk00000003_sig00000809 : STD_LOGIC;
signal blk00000003_sig00000808 : STD_LOGIC;
signal blk00000003_sig00000807 : STD_LOGIC;
signal blk00000003_sig00000806 : STD_LOGIC;
signal blk00000003_sig00000805 : STD_LOGIC;
signal blk00000003_sig00000804 : STD_LOGIC;
signal blk00000003_sig00000803 : STD_LOGIC;
signal blk00000003_sig00000802 : STD_LOGIC;
signal blk00000003_sig00000801 : STD_LOGIC;
signal blk00000003_sig00000800 : STD_LOGIC;
signal blk00000003_sig000007ff : STD_LOGIC;
signal blk00000003_sig000007fe : STD_LOGIC;
signal blk00000003_sig000007fd : STD_LOGIC;
signal blk00000003_sig000007fc : STD_LOGIC;
signal blk00000003_sig000007fb : STD_LOGIC;
signal blk00000003_sig000007fa : STD_LOGIC;
signal blk00000003_sig000007f9 : STD_LOGIC;
signal blk00000003_sig000007f8 : STD_LOGIC;
signal blk00000003_sig000007f7 : STD_LOGIC;
signal blk00000003_sig000007f6 : STD_LOGIC;
signal blk00000003_sig000007f5 : STD_LOGIC;
signal blk00000003_sig000007f4 : STD_LOGIC;
signal blk00000003_sig000007f3 : STD_LOGIC;
signal blk00000003_sig000007f2 : STD_LOGIC;
signal blk00000003_sig000007f1 : STD_LOGIC;
signal blk00000003_sig000007f0 : STD_LOGIC;
signal blk00000003_sig000007ef : STD_LOGIC;
signal blk00000003_sig000007ee : STD_LOGIC;
signal blk00000003_sig000007ed : STD_LOGIC;
signal blk00000003_sig000007ec : STD_LOGIC;
signal blk00000003_sig000007eb : STD_LOGIC;
signal blk00000003_sig000007ea : STD_LOGIC;
signal blk00000003_sig000007e9 : STD_LOGIC;
signal blk00000003_sig000007e8 : STD_LOGIC;
signal blk00000003_sig000007e7 : STD_LOGIC;
signal blk00000003_sig000007e6 : STD_LOGIC;
signal blk00000003_sig000007e5 : STD_LOGIC;
signal blk00000003_sig000007e4 : STD_LOGIC;
signal blk00000003_sig000007e3 : STD_LOGIC;
signal blk00000003_sig000007e2 : STD_LOGIC;
signal blk00000003_sig000007e1 : STD_LOGIC;
signal blk00000003_sig000007e0 : STD_LOGIC;
signal blk00000003_sig000007df : STD_LOGIC;
signal blk00000003_sig000007de : STD_LOGIC;
signal blk00000003_sig000007dd : STD_LOGIC;
signal blk00000003_sig000007dc : STD_LOGIC;
signal blk00000003_sig000007db : STD_LOGIC;
signal blk00000003_sig000007da : STD_LOGIC;
signal blk00000003_sig000007d9 : STD_LOGIC;
signal blk00000003_sig000007d8 : STD_LOGIC;
signal blk00000003_sig000007d7 : STD_LOGIC;
signal blk00000003_sig000007d6 : STD_LOGIC;
signal blk00000003_sig000007d5 : STD_LOGIC;
signal blk00000003_sig000007d4 : STD_LOGIC;
signal blk00000003_sig000007d3 : STD_LOGIC;
signal blk00000003_sig000007d2 : STD_LOGIC;
signal blk00000003_sig000007d1 : STD_LOGIC;
signal blk00000003_sig000007d0 : STD_LOGIC;
signal blk00000003_sig000007cf : STD_LOGIC;
signal blk00000003_sig000007ce : STD_LOGIC;
signal blk00000003_sig000007cd : STD_LOGIC;
signal blk00000003_sig000007cc : STD_LOGIC;
signal blk00000003_sig000007cb : STD_LOGIC;
signal blk00000003_sig000007ca : STD_LOGIC;
signal blk00000003_sig000007c9 : STD_LOGIC;
signal blk00000003_sig000007c8 : STD_LOGIC;
signal blk00000003_sig000007c7 : STD_LOGIC;
signal blk00000003_sig000007c6 : STD_LOGIC;
signal blk00000003_sig000007c5 : STD_LOGIC;
signal blk00000003_sig000007c4 : STD_LOGIC;
signal blk00000003_sig000007c3 : STD_LOGIC;
signal blk00000003_sig000007c2 : STD_LOGIC;
signal blk00000003_sig000007c1 : STD_LOGIC;
signal blk00000003_sig000007c0 : STD_LOGIC;
signal blk00000003_sig000007bf : STD_LOGIC;
signal blk00000003_sig000007be : STD_LOGIC;
signal blk00000003_sig000007bd : STD_LOGIC;
signal blk00000003_sig000007bc : STD_LOGIC;
signal blk00000003_sig000007bb : STD_LOGIC;
signal blk00000003_sig000007ba : STD_LOGIC;
signal blk00000003_sig000007b9 : STD_LOGIC;
signal blk00000003_sig000007b8 : STD_LOGIC;
signal blk00000003_sig000007b7 : STD_LOGIC;
signal blk00000003_sig000007b6 : STD_LOGIC;
signal blk00000003_sig000007b5 : STD_LOGIC;
signal blk00000003_sig000007b4 : STD_LOGIC;
signal blk00000003_sig000007b3 : STD_LOGIC;
signal blk00000003_sig000007b2 : STD_LOGIC;
signal blk00000003_sig000007b1 : STD_LOGIC;
signal blk00000003_sig000007b0 : STD_LOGIC;
signal blk00000003_sig000007af : STD_LOGIC;
signal blk00000003_sig000007ae : STD_LOGIC;
signal blk00000003_sig000007ad : STD_LOGIC;
signal blk00000003_sig000007ac : STD_LOGIC;
signal blk00000003_sig000007ab : STD_LOGIC;
signal blk00000003_sig000007aa : STD_LOGIC;
signal blk00000003_sig000007a9 : STD_LOGIC;
signal blk00000003_sig000007a8 : STD_LOGIC;
signal blk00000003_sig000007a7 : STD_LOGIC;
signal blk00000003_sig000007a6 : STD_LOGIC;
signal blk00000003_sig000007a5 : STD_LOGIC;
signal blk00000003_sig000007a4 : STD_LOGIC;
signal blk00000003_sig000007a3 : STD_LOGIC;
signal blk00000003_sig000007a2 : STD_LOGIC;
signal blk00000003_sig000007a1 : STD_LOGIC;
signal blk00000003_sig000007a0 : STD_LOGIC;
signal blk00000003_sig0000079f : STD_LOGIC;
signal blk00000003_sig0000079e : STD_LOGIC;
signal blk00000003_sig0000079d : STD_LOGIC;
signal blk00000003_sig0000079c : STD_LOGIC;
signal blk00000003_sig0000079b : STD_LOGIC;
signal blk00000003_sig0000079a : STD_LOGIC;
signal blk00000003_sig00000799 : STD_LOGIC;
signal blk00000003_sig00000798 : STD_LOGIC;
signal blk00000003_sig00000797 : STD_LOGIC;
signal blk00000003_sig00000796 : STD_LOGIC;
signal blk00000003_sig00000795 : STD_LOGIC;
signal blk00000003_sig00000794 : STD_LOGIC;
signal blk00000003_sig00000793 : STD_LOGIC;
signal blk00000003_sig00000792 : STD_LOGIC;
signal blk00000003_sig00000791 : STD_LOGIC;
signal blk00000003_sig00000790 : STD_LOGIC;
signal blk00000003_sig0000078f : STD_LOGIC;
signal blk00000003_sig0000078e : STD_LOGIC;
signal blk00000003_sig0000078d : STD_LOGIC;
signal blk00000003_sig0000078c : STD_LOGIC;
signal blk00000003_sig0000078b : STD_LOGIC;
signal blk00000003_sig0000078a : STD_LOGIC;
signal blk00000003_sig00000789 : STD_LOGIC;
signal blk00000003_sig00000788 : STD_LOGIC;
signal blk00000003_sig00000787 : STD_LOGIC;
signal blk00000003_sig00000786 : STD_LOGIC;
signal blk00000003_sig00000785 : STD_LOGIC;
signal blk00000003_sig00000784 : STD_LOGIC;
signal blk00000003_sig00000783 : STD_LOGIC;
signal blk00000003_sig00000782 : STD_LOGIC;
signal blk00000003_sig00000781 : STD_LOGIC;
signal blk00000003_sig00000780 : STD_LOGIC;
signal blk00000003_sig0000077f : STD_LOGIC;
signal blk00000003_sig0000077e : STD_LOGIC;
signal blk00000003_sig0000077d : STD_LOGIC;
signal blk00000003_sig0000077c : STD_LOGIC;
signal blk00000003_sig0000077b : STD_LOGIC;
signal blk00000003_sig0000077a : STD_LOGIC;
signal blk00000003_sig00000779 : STD_LOGIC;
signal blk00000003_sig00000778 : STD_LOGIC;
signal blk00000003_sig00000777 : STD_LOGIC;
signal blk00000003_sig00000776 : STD_LOGIC;
signal blk00000003_sig00000775 : STD_LOGIC;
signal blk00000003_sig00000774 : STD_LOGIC;
signal blk00000003_sig00000773 : STD_LOGIC;
signal blk00000003_sig00000772 : STD_LOGIC;
signal blk00000003_sig00000771 : STD_LOGIC;
signal blk00000003_sig00000770 : STD_LOGIC;
signal blk00000003_sig0000076f : STD_LOGIC;
signal blk00000003_sig0000076e : STD_LOGIC;
signal blk00000003_sig0000076d : STD_LOGIC;
signal blk00000003_sig0000076c : STD_LOGIC;
signal blk00000003_sig0000076b : STD_LOGIC;
signal blk00000003_sig0000076a : STD_LOGIC;
signal blk00000003_sig00000769 : STD_LOGIC;
signal blk00000003_sig00000768 : STD_LOGIC;
signal blk00000003_sig00000767 : STD_LOGIC;
signal blk00000003_sig00000766 : STD_LOGIC;
signal blk00000003_sig00000765 : STD_LOGIC;
signal blk00000003_sig00000764 : STD_LOGIC;
signal blk00000003_sig00000763 : STD_LOGIC;
signal blk00000003_sig00000762 : STD_LOGIC;
signal blk00000003_sig00000761 : STD_LOGIC;
signal blk00000003_sig00000760 : STD_LOGIC;
signal blk00000003_sig0000075f : STD_LOGIC;
signal blk00000003_sig0000075e : STD_LOGIC;
signal blk00000003_sig0000075d : STD_LOGIC;
signal blk00000003_sig0000075c : STD_LOGIC;
signal blk00000003_sig0000075b : STD_LOGIC;
signal blk00000003_sig0000075a : STD_LOGIC;
signal blk00000003_sig00000759 : STD_LOGIC;
signal blk00000003_sig00000758 : STD_LOGIC;
signal blk00000003_sig00000757 : STD_LOGIC;
signal blk00000003_sig00000756 : STD_LOGIC;
signal blk00000003_sig00000755 : STD_LOGIC;
signal blk00000003_sig00000754 : STD_LOGIC;
signal blk00000003_sig00000753 : STD_LOGIC;
signal blk00000003_sig00000752 : STD_LOGIC;
signal blk00000003_sig00000751 : STD_LOGIC;
signal blk00000003_sig00000750 : STD_LOGIC;
signal blk00000003_sig0000074f : STD_LOGIC;
signal blk00000003_sig0000074e : STD_LOGIC;
signal blk00000003_sig0000074d : STD_LOGIC;
signal blk00000003_sig0000074c : STD_LOGIC;
signal blk00000003_sig0000074b : STD_LOGIC;
signal blk00000003_sig0000074a : STD_LOGIC;
signal blk00000003_sig00000749 : STD_LOGIC;
signal blk00000003_sig00000748 : STD_LOGIC;
signal blk00000003_sig00000747 : STD_LOGIC;
signal blk00000003_sig00000746 : STD_LOGIC;
signal blk00000003_sig00000745 : STD_LOGIC;
signal blk00000003_sig00000744 : STD_LOGIC;
signal blk00000003_sig00000743 : STD_LOGIC;
signal blk00000003_sig00000742 : STD_LOGIC;
signal blk00000003_sig00000741 : STD_LOGIC;
signal blk00000003_sig00000740 : STD_LOGIC;
signal blk00000003_sig0000073f : STD_LOGIC;
signal blk00000003_sig0000073e : STD_LOGIC;
signal blk00000003_sig0000073d : STD_LOGIC;
signal blk00000003_sig0000073c : STD_LOGIC;
signal blk00000003_sig0000073b : STD_LOGIC;
signal blk00000003_sig0000073a : STD_LOGIC;
signal blk00000003_sig00000739 : STD_LOGIC;
signal blk00000003_sig00000738 : STD_LOGIC;
signal blk00000003_sig00000737 : STD_LOGIC;
signal blk00000003_sig00000736 : STD_LOGIC;
signal blk00000003_sig00000735 : STD_LOGIC;
signal blk00000003_sig00000734 : STD_LOGIC;
signal blk00000003_sig00000733 : STD_LOGIC;
signal blk00000003_sig00000732 : STD_LOGIC;
signal blk00000003_sig00000731 : STD_LOGIC;
signal blk00000003_sig00000730 : STD_LOGIC;
signal blk00000003_sig0000072f : STD_LOGIC;
signal blk00000003_sig0000072e : STD_LOGIC;
signal blk00000003_sig0000072d : STD_LOGIC;
signal blk00000003_sig0000072c : STD_LOGIC;
signal blk00000003_sig0000072b : STD_LOGIC;
signal blk00000003_sig0000072a : STD_LOGIC;
signal blk00000003_sig00000729 : STD_LOGIC;
signal blk00000003_sig00000728 : STD_LOGIC;
signal blk00000003_sig00000727 : STD_LOGIC;
signal blk00000003_sig00000726 : STD_LOGIC;
signal blk00000003_sig00000725 : STD_LOGIC;
signal blk00000003_sig00000724 : STD_LOGIC;
signal blk00000003_sig00000723 : STD_LOGIC;
signal blk00000003_sig00000722 : STD_LOGIC;
signal blk00000003_sig00000721 : STD_LOGIC;
signal blk00000003_sig00000720 : STD_LOGIC;
signal blk00000003_sig0000071f : STD_LOGIC;
signal blk00000003_sig0000071e : STD_LOGIC;
signal blk00000003_sig0000071d : STD_LOGIC;
signal blk00000003_sig0000071c : STD_LOGIC;
signal blk00000003_sig0000071b : STD_LOGIC;
signal blk00000003_sig0000071a : STD_LOGIC;
signal blk00000003_sig00000719 : STD_LOGIC;
signal blk00000003_sig00000718 : STD_LOGIC;
signal blk00000003_sig00000717 : STD_LOGIC;
signal blk00000003_sig00000716 : STD_LOGIC;
signal blk00000003_sig00000715 : STD_LOGIC;
signal blk00000003_sig00000714 : STD_LOGIC;
signal blk00000003_sig00000713 : STD_LOGIC;
signal blk00000003_sig00000712 : STD_LOGIC;
signal blk00000003_sig00000711 : STD_LOGIC;
signal blk00000003_sig00000710 : STD_LOGIC;
signal blk00000003_sig0000070f : STD_LOGIC;
signal blk00000003_sig0000070e : STD_LOGIC;
signal blk00000003_sig0000070d : STD_LOGIC;
signal blk00000003_sig0000070c : STD_LOGIC;
signal blk00000003_sig0000070b : STD_LOGIC;
signal blk00000003_sig0000070a : STD_LOGIC;
signal blk00000003_sig00000709 : STD_LOGIC;
signal blk00000003_sig00000708 : STD_LOGIC;
signal blk00000003_sig00000707 : STD_LOGIC;
signal blk00000003_sig00000706 : STD_LOGIC;
signal blk00000003_sig00000705 : STD_LOGIC;
signal blk00000003_sig00000704 : STD_LOGIC;
signal blk00000003_sig00000703 : STD_LOGIC;
signal blk00000003_sig00000702 : STD_LOGIC;
signal blk00000003_sig00000701 : STD_LOGIC;
signal blk00000003_sig00000700 : STD_LOGIC;
signal blk00000003_sig000006ff : STD_LOGIC;
signal blk00000003_sig000006fe : STD_LOGIC;
signal blk00000003_sig000006fd : STD_LOGIC;
signal blk00000003_sig000006fc : STD_LOGIC;
signal blk00000003_sig000006fb : STD_LOGIC;
signal blk00000003_sig000006fa : STD_LOGIC;
signal blk00000003_sig000006f9 : STD_LOGIC;
signal blk00000003_sig000006f8 : STD_LOGIC;
signal blk00000003_sig000006f7 : STD_LOGIC;
signal blk00000003_sig000006f6 : STD_LOGIC;
signal blk00000003_sig000006f5 : STD_LOGIC;
signal blk00000003_sig000006f4 : STD_LOGIC;
signal blk00000003_sig000006f3 : STD_LOGIC;
signal blk00000003_sig000006f2 : STD_LOGIC;
signal blk00000003_sig000006f1 : STD_LOGIC;
signal blk00000003_sig000006f0 : STD_LOGIC;
signal blk00000003_sig000006ef : STD_LOGIC;
signal blk00000003_sig000006ee : STD_LOGIC;
signal blk00000003_sig000006ed : STD_LOGIC;
signal blk00000003_sig000006ec : STD_LOGIC;
signal blk00000003_sig000006eb : STD_LOGIC;
signal blk00000003_sig000006ea : STD_LOGIC;
signal blk00000003_sig000006e9 : STD_LOGIC;
signal blk00000003_sig000006e8 : STD_LOGIC;
signal blk00000003_sig000006e7 : STD_LOGIC;
signal blk00000003_sig000006e6 : STD_LOGIC;
signal blk00000003_sig000006e5 : STD_LOGIC;
signal blk00000003_sig000006e4 : STD_LOGIC;
signal blk00000003_sig000006e3 : STD_LOGIC;
signal blk00000003_sig000006e2 : STD_LOGIC;
signal blk00000003_sig000006e1 : STD_LOGIC;
signal blk00000003_sig000006e0 : STD_LOGIC;
signal blk00000003_sig000006df : STD_LOGIC;
signal blk00000003_sig000006de : STD_LOGIC;
signal blk00000003_sig000006dd : STD_LOGIC;
signal blk00000003_sig000006dc : STD_LOGIC;
signal blk00000003_sig000006db : STD_LOGIC;
signal blk00000003_sig000006da : STD_LOGIC;
signal blk00000003_sig000006d9 : STD_LOGIC;
signal blk00000003_sig000006d8 : STD_LOGIC;
signal blk00000003_sig000006d7 : STD_LOGIC;
signal blk00000003_sig000006d6 : STD_LOGIC;
signal blk00000003_sig000006d5 : STD_LOGIC;
signal blk00000003_sig000006d4 : STD_LOGIC;
signal blk00000003_sig000006d3 : STD_LOGIC;
signal blk00000003_sig000006d2 : STD_LOGIC;
signal blk00000003_sig000006d1 : STD_LOGIC;
signal blk00000003_sig000006d0 : STD_LOGIC;
signal blk00000003_sig000006cf : STD_LOGIC;
signal blk00000003_sig000006ce : STD_LOGIC;
signal blk00000003_sig000006cd : STD_LOGIC;
signal blk00000003_sig000006cc : STD_LOGIC;
signal blk00000003_sig000006cb : STD_LOGIC;
signal blk00000003_sig000006ca : STD_LOGIC;
signal blk00000003_sig000006c9 : STD_LOGIC;
signal blk00000003_sig000006c8 : STD_LOGIC;
signal blk00000003_sig000006c7 : STD_LOGIC;
signal blk00000003_sig000006c6 : STD_LOGIC;
signal blk00000003_sig000006c5 : STD_LOGIC;
signal blk00000003_sig000006c4 : STD_LOGIC;
signal blk00000003_sig000006c3 : STD_LOGIC;
signal blk00000003_sig000006c2 : STD_LOGIC;
signal blk00000003_sig000006c1 : STD_LOGIC;
signal blk00000003_sig000006c0 : STD_LOGIC;
signal blk00000003_sig000006bf : STD_LOGIC;
signal blk00000003_sig000006be : STD_LOGIC;
signal blk00000003_sig000006bd : STD_LOGIC;
signal blk00000003_sig000006bc : STD_LOGIC;
signal blk00000003_sig000006bb : STD_LOGIC;
signal blk00000003_sig000006ba : STD_LOGIC;
signal blk00000003_sig000006b9 : STD_LOGIC;
signal blk00000003_sig000006b8 : STD_LOGIC;
signal blk00000003_sig000006b7 : STD_LOGIC;
signal blk00000003_sig000006b6 : STD_LOGIC;
signal blk00000003_sig000006b5 : STD_LOGIC;
signal blk00000003_sig000006b4 : STD_LOGIC;
signal blk00000003_sig000006b3 : STD_LOGIC;
signal blk00000003_sig000006b2 : STD_LOGIC;
signal blk00000003_sig000006b1 : STD_LOGIC;
signal blk00000003_sig000006b0 : STD_LOGIC;
signal blk00000003_sig000006af : STD_LOGIC;
signal blk00000003_sig000006ae : STD_LOGIC;
signal blk00000003_sig000006ad : STD_LOGIC;
signal blk00000003_sig000006ac : STD_LOGIC;
signal blk00000003_sig000006ab : STD_LOGIC;
signal blk00000003_sig000006aa : STD_LOGIC;
signal blk00000003_sig000006a9 : STD_LOGIC;
signal blk00000003_sig000006a8 : STD_LOGIC;
signal blk00000003_sig000006a7 : STD_LOGIC;
signal blk00000003_sig000006a6 : STD_LOGIC;
signal blk00000003_sig000006a5 : STD_LOGIC;
signal blk00000003_sig000006a4 : STD_LOGIC;
signal blk00000003_sig000006a3 : STD_LOGIC;
signal blk00000003_sig000006a2 : STD_LOGIC;
signal blk00000003_sig000006a1 : STD_LOGIC;
signal blk00000003_sig000006a0 : STD_LOGIC;
signal blk00000003_sig0000069f : STD_LOGIC;
signal blk00000003_sig0000069e : STD_LOGIC;
signal blk00000003_sig0000069d : STD_LOGIC;
signal blk00000003_sig0000069c : STD_LOGIC;
signal blk00000003_sig0000069b : STD_LOGIC;
signal blk00000003_sig0000069a : STD_LOGIC;
signal blk00000003_sig00000699 : STD_LOGIC;
signal blk00000003_sig00000698 : STD_LOGIC;
signal blk00000003_sig00000697 : STD_LOGIC;
signal blk00000003_sig00000696 : STD_LOGIC;
signal blk00000003_sig00000695 : STD_LOGIC;
signal blk00000003_sig00000694 : STD_LOGIC;
signal blk00000003_sig00000693 : STD_LOGIC;
signal blk00000003_sig00000692 : STD_LOGIC;
signal blk00000003_sig00000691 : STD_LOGIC;
signal blk00000003_sig00000690 : STD_LOGIC;
signal blk00000003_sig0000068f : STD_LOGIC;
signal blk00000003_sig0000068e : STD_LOGIC;
signal blk00000003_sig0000068d : STD_LOGIC;
signal blk00000003_sig0000068c : STD_LOGIC;
signal blk00000003_sig0000068b : STD_LOGIC;
signal blk00000003_sig0000068a : STD_LOGIC;
signal blk00000003_sig00000689 : STD_LOGIC;
signal blk00000003_sig00000688 : STD_LOGIC;
signal blk00000003_sig00000687 : STD_LOGIC;
signal blk00000003_sig00000686 : STD_LOGIC;
signal blk00000003_sig00000685 : STD_LOGIC;
signal blk00000003_sig00000684 : STD_LOGIC;
signal blk00000003_sig00000683 : STD_LOGIC;
signal blk00000003_sig00000682 : STD_LOGIC;
signal blk00000003_sig00000681 : STD_LOGIC;
signal blk00000003_sig00000680 : STD_LOGIC;
signal blk00000003_sig0000067f : STD_LOGIC;
signal blk00000003_sig0000067e : STD_LOGIC;
signal blk00000003_sig0000067d : STD_LOGIC;
signal blk00000003_sig0000067c : STD_LOGIC;
signal blk00000003_sig0000067b : STD_LOGIC;
signal blk00000003_sig0000067a : STD_LOGIC;
signal blk00000003_sig00000679 : STD_LOGIC;
signal blk00000003_sig00000678 : STD_LOGIC;
signal blk00000003_sig00000677 : STD_LOGIC;
signal blk00000003_sig00000676 : STD_LOGIC;
signal blk00000003_sig00000675 : STD_LOGIC;
signal blk00000003_sig00000674 : STD_LOGIC;
signal blk00000003_sig00000673 : STD_LOGIC;
signal blk00000003_sig00000672 : STD_LOGIC;
signal blk00000003_sig00000671 : STD_LOGIC;
signal blk00000003_sig00000670 : STD_LOGIC;
signal blk00000003_sig0000066f : STD_LOGIC;
signal blk00000003_sig0000066e : STD_LOGIC;
signal blk00000003_sig0000066d : STD_LOGIC;
signal blk00000003_sig0000066c : STD_LOGIC;
signal blk00000003_sig0000066b : STD_LOGIC;
signal blk00000003_sig0000066a : STD_LOGIC;
signal blk00000003_sig00000669 : STD_LOGIC;
signal blk00000003_sig00000668 : STD_LOGIC;
signal blk00000003_sig00000667 : STD_LOGIC;
signal blk00000003_sig00000666 : STD_LOGIC;
signal blk00000003_sig00000665 : STD_LOGIC;
signal blk00000003_sig00000664 : STD_LOGIC;
signal blk00000003_sig00000663 : STD_LOGIC;
signal blk00000003_sig00000662 : STD_LOGIC;
signal blk00000003_sig00000661 : STD_LOGIC;
signal blk00000003_sig00000660 : STD_LOGIC;
signal blk00000003_sig0000065f : STD_LOGIC;
signal blk00000003_sig0000065e : STD_LOGIC;
signal blk00000003_sig0000065d : STD_LOGIC;
signal blk00000003_sig0000065c : STD_LOGIC;
signal blk00000003_sig0000065b : STD_LOGIC;
signal blk00000003_sig0000065a : STD_LOGIC;
signal blk00000003_sig00000659 : STD_LOGIC;
signal blk00000003_sig00000658 : STD_LOGIC;
signal blk00000003_sig00000657 : STD_LOGIC;
signal blk00000003_sig00000656 : STD_LOGIC;
signal blk00000003_sig00000655 : STD_LOGIC;
signal blk00000003_sig00000654 : STD_LOGIC;
signal blk00000003_sig00000653 : STD_LOGIC;
signal blk00000003_sig00000652 : STD_LOGIC;
signal blk00000003_sig00000651 : STD_LOGIC;
signal blk00000003_sig00000650 : STD_LOGIC;
signal blk00000003_sig0000064f : STD_LOGIC;
signal blk00000003_sig0000064e : STD_LOGIC;
signal blk00000003_sig0000064d : STD_LOGIC;
signal blk00000003_sig0000064c : STD_LOGIC;
signal blk00000003_sig0000064b : STD_LOGIC;
signal blk00000003_sig0000064a : STD_LOGIC;
signal blk00000003_sig00000649 : STD_LOGIC;
signal blk00000003_sig00000648 : STD_LOGIC;
signal blk00000003_sig00000647 : STD_LOGIC;
signal blk00000003_sig00000646 : STD_LOGIC;
signal blk00000003_sig00000645 : STD_LOGIC;
signal blk00000003_sig00000644 : STD_LOGIC;
signal blk00000003_sig00000643 : STD_LOGIC;
signal blk00000003_sig00000642 : STD_LOGIC;
signal blk00000003_sig00000641 : STD_LOGIC;
signal blk00000003_sig00000640 : STD_LOGIC;
signal blk00000003_sig0000063f : STD_LOGIC;
signal blk00000003_sig0000063e : STD_LOGIC;
signal blk00000003_sig0000063d : STD_LOGIC;
signal blk00000003_sig0000063c : STD_LOGIC;
signal blk00000003_sig0000063b : STD_LOGIC;
signal blk00000003_sig0000063a : STD_LOGIC;
signal blk00000003_sig00000639 : STD_LOGIC;
signal blk00000003_sig00000638 : STD_LOGIC;
signal blk00000003_sig00000637 : STD_LOGIC;
signal blk00000003_sig00000636 : STD_LOGIC;
signal blk00000003_sig00000635 : STD_LOGIC;
signal blk00000003_sig00000634 : STD_LOGIC;
signal blk00000003_sig00000633 : STD_LOGIC;
signal blk00000003_sig00000632 : STD_LOGIC;
signal blk00000003_sig00000631 : STD_LOGIC;
signal blk00000003_sig00000630 : STD_LOGIC;
signal blk00000003_sig0000062f : STD_LOGIC;
signal blk00000003_sig0000062e : STD_LOGIC;
signal blk00000003_sig0000062d : STD_LOGIC;
signal blk00000003_sig0000062c : STD_LOGIC;
signal blk00000003_sig0000062b : STD_LOGIC;
signal blk00000003_sig0000062a : STD_LOGIC;
signal blk00000003_sig00000629 : STD_LOGIC;
signal blk00000003_sig00000628 : STD_LOGIC;
signal blk00000003_sig00000627 : STD_LOGIC;
signal blk00000003_sig00000626 : STD_LOGIC;
signal blk00000003_sig00000625 : STD_LOGIC;
signal blk00000003_sig00000624 : STD_LOGIC;
signal blk00000003_sig00000623 : STD_LOGIC;
signal blk00000003_sig00000622 : STD_LOGIC;
signal blk00000003_sig00000621 : STD_LOGIC;
signal blk00000003_sig00000620 : STD_LOGIC;
signal blk00000003_sig0000061f : STD_LOGIC;
signal blk00000003_sig0000061e : STD_LOGIC;
signal blk00000003_sig0000061d : STD_LOGIC;
signal blk00000003_sig0000061c : STD_LOGIC;
signal blk00000003_sig0000061b : STD_LOGIC;
signal blk00000003_sig0000061a : STD_LOGIC;
signal blk00000003_sig00000619 : STD_LOGIC;
signal blk00000003_sig00000618 : STD_LOGIC;
signal blk00000003_sig00000617 : STD_LOGIC;
signal blk00000003_sig00000616 : STD_LOGIC;
signal blk00000003_sig00000615 : STD_LOGIC;
signal blk00000003_sig00000614 : STD_LOGIC;
signal blk00000003_sig00000613 : STD_LOGIC;
signal blk00000003_sig00000612 : STD_LOGIC;
signal blk00000003_sig00000611 : STD_LOGIC;
signal blk00000003_sig00000610 : STD_LOGIC;
signal blk00000003_sig0000060f : STD_LOGIC;
signal blk00000003_sig0000060e : STD_LOGIC;
signal blk00000003_sig0000060d : STD_LOGIC;
signal blk00000003_sig0000060c : STD_LOGIC;
signal blk00000003_sig0000060b : STD_LOGIC;
signal blk00000003_sig0000060a : STD_LOGIC;
signal blk00000003_sig00000609 : STD_LOGIC;
signal blk00000003_sig00000608 : STD_LOGIC;
signal blk00000003_sig00000607 : STD_LOGIC;
signal blk00000003_sig00000606 : STD_LOGIC;
signal blk00000003_sig00000605 : STD_LOGIC;
signal blk00000003_sig00000604 : STD_LOGIC;
signal blk00000003_sig00000603 : STD_LOGIC;
signal blk00000003_sig00000602 : STD_LOGIC;
signal blk00000003_sig00000601 : STD_LOGIC;
signal blk00000003_sig00000600 : STD_LOGIC;
signal blk00000003_sig000005ff : STD_LOGIC;
signal blk00000003_sig000005fe : STD_LOGIC;
signal blk00000003_sig000005fd : STD_LOGIC;
signal blk00000003_sig000005fc : STD_LOGIC;
signal blk00000003_sig000005fb : STD_LOGIC;
signal blk00000003_sig000005fa : STD_LOGIC;
signal blk00000003_sig000005f9 : STD_LOGIC;
signal blk00000003_sig000005f8 : STD_LOGIC;
signal blk00000003_sig000005f7 : STD_LOGIC;
signal blk00000003_sig000005f6 : STD_LOGIC;
signal blk00000003_sig000005f5 : STD_LOGIC;
signal blk00000003_sig000005f4 : STD_LOGIC;
signal blk00000003_sig000005f3 : STD_LOGIC;
signal blk00000003_sig000005f2 : STD_LOGIC;
signal blk00000003_sig000005f1 : STD_LOGIC;
signal blk00000003_sig000005f0 : STD_LOGIC;
signal blk00000003_sig000005ef : STD_LOGIC;
signal blk00000003_sig000005ee : STD_LOGIC;
signal blk00000003_sig000005ed : STD_LOGIC;
signal blk00000003_sig000005ec : STD_LOGIC;
signal blk00000003_sig000005eb : STD_LOGIC;
signal blk00000003_sig000005ea : STD_LOGIC;
signal blk00000003_sig000005e9 : STD_LOGIC;
signal blk00000003_sig000005e8 : STD_LOGIC;
signal blk00000003_sig000005e7 : STD_LOGIC;
signal blk00000003_sig000005e6 : STD_LOGIC;
signal blk00000003_sig000005e5 : STD_LOGIC;
signal blk00000003_sig000005e4 : STD_LOGIC;
signal blk00000003_sig000005e3 : STD_LOGIC;
signal blk00000003_sig000005e2 : STD_LOGIC;
signal blk00000003_sig000005e1 : STD_LOGIC;
signal blk00000003_sig000005e0 : STD_LOGIC;
signal blk00000003_sig000005df : STD_LOGIC;
signal blk00000003_sig000005de : STD_LOGIC;
signal blk00000003_sig000005dd : STD_LOGIC;
signal blk00000003_sig000005dc : STD_LOGIC;
signal blk00000003_sig000005db : STD_LOGIC;
signal blk00000003_sig000005da : STD_LOGIC;
signal blk00000003_sig000005d9 : STD_LOGIC;
signal blk00000003_sig000005d8 : STD_LOGIC;
signal blk00000003_sig000005d7 : STD_LOGIC;
signal blk00000003_sig000005d6 : STD_LOGIC;
signal blk00000003_sig000005d5 : STD_LOGIC;
signal blk00000003_sig000005d4 : STD_LOGIC;
signal blk00000003_sig000005d3 : STD_LOGIC;
signal blk00000003_sig000005d2 : STD_LOGIC;
signal blk00000003_sig000005d1 : STD_LOGIC;
signal blk00000003_sig000005d0 : STD_LOGIC;
signal blk00000003_sig000005cf : STD_LOGIC;
signal blk00000003_sig000005ce : STD_LOGIC;
signal blk00000003_sig000005cd : STD_LOGIC;
signal blk00000003_sig000005cc : STD_LOGIC;
signal blk00000003_sig000005cb : STD_LOGIC;
signal blk00000003_sig000005ca : STD_LOGIC;
signal blk00000003_sig000005c9 : STD_LOGIC;
signal blk00000003_sig000005c8 : STD_LOGIC;
signal blk00000003_sig000005c7 : STD_LOGIC;
signal blk00000003_sig000005c6 : STD_LOGIC;
signal blk00000003_sig000005c5 : STD_LOGIC;
signal blk00000003_sig000005c4 : STD_LOGIC;
signal blk00000003_sig000005c3 : STD_LOGIC;
signal blk00000003_sig000005c2 : STD_LOGIC;
signal blk00000003_sig000005c1 : STD_LOGIC;
signal blk00000003_sig000005c0 : STD_LOGIC;
signal blk00000003_sig000005bf : STD_LOGIC;
signal blk00000003_sig000005be : STD_LOGIC;
signal blk00000003_sig000005bd : STD_LOGIC;
signal blk00000003_sig000005bc : STD_LOGIC;
signal blk00000003_sig000005bb : STD_LOGIC;
signal blk00000003_sig000005ba : STD_LOGIC;
signal blk00000003_sig000005b9 : STD_LOGIC;
signal blk00000003_sig000005b8 : STD_LOGIC;
signal blk00000003_sig000005b7 : STD_LOGIC;
signal blk00000003_sig000005b6 : STD_LOGIC;
signal blk00000003_sig000005b5 : STD_LOGIC;
signal blk00000003_sig000005b4 : STD_LOGIC;
signal blk00000003_sig000005b3 : STD_LOGIC;
signal blk00000003_sig000005b2 : STD_LOGIC;
signal blk00000003_sig000005b1 : STD_LOGIC;
signal blk00000003_sig000005b0 : STD_LOGIC;
signal blk00000003_sig000005af : STD_LOGIC;
signal blk00000003_sig000005ae : STD_LOGIC;
signal blk00000003_sig000005ad : STD_LOGIC;
signal blk00000003_sig000005ac : STD_LOGIC;
signal blk00000003_sig000005ab : STD_LOGIC;
signal blk00000003_sig000005aa : STD_LOGIC;
signal blk00000003_sig000005a9 : STD_LOGIC;
signal blk00000003_sig000005a8 : STD_LOGIC;
signal blk00000003_sig000005a7 : STD_LOGIC;
signal blk00000003_sig000005a6 : STD_LOGIC;
signal blk00000003_sig000005a5 : STD_LOGIC;
signal blk00000003_sig000005a4 : STD_LOGIC;
signal blk00000003_sig000005a3 : STD_LOGIC;
signal blk00000003_sig000005a2 : STD_LOGIC;
signal blk00000003_sig000005a1 : STD_LOGIC;
signal blk00000003_sig000005a0 : STD_LOGIC;
signal blk00000003_sig0000059f : STD_LOGIC;
signal blk00000003_sig0000059e : STD_LOGIC;
signal blk00000003_sig0000059d : STD_LOGIC;
signal blk00000003_sig0000059c : STD_LOGIC;
signal blk00000003_sig0000059b : STD_LOGIC;
signal blk00000003_sig0000059a : STD_LOGIC;
signal blk00000003_sig00000599 : STD_LOGIC;
signal blk00000003_sig00000598 : STD_LOGIC;
signal blk00000003_sig00000597 : STD_LOGIC;
signal blk00000003_sig00000596 : STD_LOGIC;
signal blk00000003_sig00000595 : STD_LOGIC;
signal blk00000003_sig00000594 : STD_LOGIC;
signal blk00000003_sig00000593 : STD_LOGIC;
signal blk00000003_sig00000592 : STD_LOGIC;
signal blk00000003_sig00000591 : STD_LOGIC;
signal blk00000003_sig00000590 : STD_LOGIC;
signal blk00000003_sig0000058f : STD_LOGIC;
signal blk00000003_sig0000058e : STD_LOGIC;
signal blk00000003_sig0000058d : STD_LOGIC;
signal blk00000003_sig0000058c : STD_LOGIC;
signal blk00000003_sig0000058b : STD_LOGIC;
signal blk00000003_sig0000058a : STD_LOGIC;
signal blk00000003_sig00000589 : STD_LOGIC;
signal blk00000003_sig00000588 : STD_LOGIC;
signal blk00000003_sig00000587 : STD_LOGIC;
signal blk00000003_sig00000586 : STD_LOGIC;
signal blk00000003_sig00000585 : STD_LOGIC;
signal blk00000003_sig00000584 : STD_LOGIC;
signal blk00000003_sig00000583 : STD_LOGIC;
signal blk00000003_sig00000582 : STD_LOGIC;
signal blk00000003_sig00000581 : STD_LOGIC;
signal blk00000003_sig00000580 : STD_LOGIC;
signal blk00000003_sig0000057f : STD_LOGIC;
signal blk00000003_sig0000057e : STD_LOGIC;
signal blk00000003_sig0000057d : STD_LOGIC;
signal blk00000003_sig0000057c : STD_LOGIC;
signal blk00000003_sig0000057b : STD_LOGIC;
signal blk00000003_sig0000057a : STD_LOGIC;
signal blk00000003_sig00000579 : STD_LOGIC;
signal blk00000003_sig00000578 : STD_LOGIC;
signal blk00000003_sig00000577 : STD_LOGIC;
signal blk00000003_sig00000576 : STD_LOGIC;
signal blk00000003_sig00000575 : STD_LOGIC;
signal blk00000003_sig00000574 : STD_LOGIC;
signal blk00000003_sig00000573 : STD_LOGIC;
signal blk00000003_sig00000572 : STD_LOGIC;
signal blk00000003_sig00000571 : STD_LOGIC;
signal blk00000003_sig00000570 : STD_LOGIC;
signal blk00000003_sig0000056f : STD_LOGIC;
signal blk00000003_sig0000056e : STD_LOGIC;
signal blk00000003_sig0000056d : STD_LOGIC;
signal blk00000003_sig0000056c : STD_LOGIC;
signal blk00000003_sig0000056b : STD_LOGIC;
signal blk00000003_sig0000056a : STD_LOGIC;
signal blk00000003_sig00000569 : STD_LOGIC;
signal blk00000003_sig00000568 : STD_LOGIC;
signal blk00000003_sig00000567 : STD_LOGIC;
signal blk00000003_sig00000566 : STD_LOGIC;
signal blk00000003_sig00000565 : STD_LOGIC;
signal blk00000003_sig00000564 : STD_LOGIC;
signal blk00000003_sig00000563 : STD_LOGIC;
signal blk00000003_sig00000562 : STD_LOGIC;
signal blk00000003_sig00000561 : STD_LOGIC;
signal blk00000003_sig00000560 : STD_LOGIC;
signal blk00000003_sig0000055f : STD_LOGIC;
signal blk00000003_sig0000055e : STD_LOGIC;
signal blk00000003_sig0000055d : STD_LOGIC;
signal blk00000003_sig0000055c : STD_LOGIC;
signal blk00000003_sig0000055b : STD_LOGIC;
signal blk00000003_sig0000055a : STD_LOGIC;
signal blk00000003_sig00000559 : STD_LOGIC;
signal blk00000003_sig00000558 : STD_LOGIC;
signal blk00000003_sig00000557 : STD_LOGIC;
signal blk00000003_sig00000556 : STD_LOGIC;
signal blk00000003_sig00000555 : STD_LOGIC;
signal blk00000003_sig00000554 : STD_LOGIC;
signal blk00000003_sig00000553 : STD_LOGIC;
signal blk00000003_sig00000552 : STD_LOGIC;
signal blk00000003_sig00000551 : STD_LOGIC;
signal blk00000003_sig00000550 : STD_LOGIC;
signal blk00000003_sig0000054f : STD_LOGIC;
signal blk00000003_sig0000054e : STD_LOGIC;
signal blk00000003_sig0000054d : STD_LOGIC;
signal blk00000003_sig0000054c : STD_LOGIC;
signal blk00000003_sig0000054b : STD_LOGIC;
signal blk00000003_sig0000054a : STD_LOGIC;
signal blk00000003_sig00000549 : STD_LOGIC;
signal blk00000003_sig00000548 : STD_LOGIC;
signal blk00000003_sig00000547 : STD_LOGIC;
signal blk00000003_sig00000546 : STD_LOGIC;
signal blk00000003_sig00000545 : STD_LOGIC;
signal blk00000003_sig00000544 : STD_LOGIC;
signal blk00000003_sig00000543 : STD_LOGIC;
signal blk00000003_sig00000542 : STD_LOGIC;
signal blk00000003_sig00000541 : STD_LOGIC;
signal blk00000003_sig00000540 : STD_LOGIC;
signal blk00000003_sig0000053f : STD_LOGIC;
signal blk00000003_sig0000053e : STD_LOGIC;
signal blk00000003_sig0000053d : STD_LOGIC;
signal blk00000003_sig0000053c : STD_LOGIC;
signal blk00000003_sig0000053b : STD_LOGIC;
signal blk00000003_sig0000053a : STD_LOGIC;
signal blk00000003_sig00000539 : STD_LOGIC;
signal blk00000003_sig00000538 : STD_LOGIC;
signal blk00000003_sig00000537 : STD_LOGIC;
signal blk00000003_sig00000536 : STD_LOGIC;
signal blk00000003_sig00000535 : STD_LOGIC;
signal blk00000003_sig00000534 : STD_LOGIC;
signal blk00000003_sig00000533 : STD_LOGIC;
signal blk00000003_sig00000532 : STD_LOGIC;
signal blk00000003_sig00000531 : STD_LOGIC;
signal blk00000003_sig00000530 : STD_LOGIC;
signal blk00000003_sig0000052f : STD_LOGIC;
signal blk00000003_sig0000052e : STD_LOGIC;
signal blk00000003_sig0000052d : STD_LOGIC;
signal blk00000003_sig0000052c : STD_LOGIC;
signal blk00000003_sig0000052b : STD_LOGIC;
signal blk00000003_sig0000052a : STD_LOGIC;
signal blk00000003_sig00000529 : STD_LOGIC;
signal blk00000003_sig00000528 : STD_LOGIC;
signal blk00000003_sig00000527 : STD_LOGIC;
signal blk00000003_sig00000526 : STD_LOGIC;
signal blk00000003_sig00000525 : STD_LOGIC;
signal blk00000003_sig00000524 : STD_LOGIC;
signal blk00000003_sig00000523 : STD_LOGIC;
signal blk00000003_sig00000522 : STD_LOGIC;
signal blk00000003_sig00000521 : STD_LOGIC;
signal blk00000003_sig00000520 : STD_LOGIC;
signal blk00000003_sig0000051f : STD_LOGIC;
signal blk00000003_sig0000051e : STD_LOGIC;
signal blk00000003_sig0000051d : STD_LOGIC;
signal blk00000003_sig0000051c : STD_LOGIC;
signal blk00000003_sig0000051b : STD_LOGIC;
signal blk00000003_sig0000051a : STD_LOGIC;
signal blk00000003_sig00000519 : STD_LOGIC;
signal blk00000003_sig00000518 : STD_LOGIC;
signal blk00000003_sig00000517 : STD_LOGIC;
signal blk00000003_sig00000516 : STD_LOGIC;
signal blk00000003_sig00000515 : STD_LOGIC;
signal blk00000003_sig00000514 : STD_LOGIC;
signal blk00000003_sig00000513 : STD_LOGIC;
signal blk00000003_sig00000512 : STD_LOGIC;
signal blk00000003_sig00000511 : STD_LOGIC;
signal blk00000003_sig00000510 : STD_LOGIC;
signal blk00000003_sig0000050f : STD_LOGIC;
signal blk00000003_sig0000050e : STD_LOGIC;
signal blk00000003_sig0000050d : STD_LOGIC;
signal blk00000003_sig0000050c : STD_LOGIC;
signal blk00000003_sig0000050b : STD_LOGIC;
signal blk00000003_sig0000050a : STD_LOGIC;
signal blk00000003_sig00000509 : STD_LOGIC;
signal blk00000003_sig00000508 : STD_LOGIC;
signal blk00000003_sig00000507 : STD_LOGIC;
signal blk00000003_sig00000506 : STD_LOGIC;
signal blk00000003_sig00000505 : STD_LOGIC;
signal blk00000003_sig00000504 : STD_LOGIC;
signal blk00000003_sig00000503 : STD_LOGIC;
signal blk00000003_sig00000502 : STD_LOGIC;
signal blk00000003_sig00000501 : STD_LOGIC;
signal blk00000003_sig00000500 : STD_LOGIC;
signal blk00000003_sig000004ff : STD_LOGIC;
signal blk00000003_sig000004fe : STD_LOGIC;
signal blk00000003_sig000004fd : STD_LOGIC;
signal blk00000003_sig000004fc : STD_LOGIC;
signal blk00000003_sig000004fb : STD_LOGIC;
signal blk00000003_sig000004fa : STD_LOGIC;
signal blk00000003_sig000004f9 : STD_LOGIC;
signal blk00000003_sig000004f8 : STD_LOGIC;
signal blk00000003_sig000004f7 : STD_LOGIC;
signal blk00000003_sig000004f6 : STD_LOGIC;
signal blk00000003_sig000004f5 : STD_LOGIC;
signal blk00000003_sig000004f4 : STD_LOGIC;
signal blk00000003_sig000004f3 : STD_LOGIC;
signal blk00000003_sig000004f2 : STD_LOGIC;
signal blk00000003_sig000004f1 : STD_LOGIC;
signal blk00000003_sig000004f0 : STD_LOGIC;
signal blk00000003_sig000004ef : STD_LOGIC;
signal blk00000003_sig000004ee : STD_LOGIC;
signal blk00000003_sig000004ed : STD_LOGIC;
signal blk00000003_sig000004ec : STD_LOGIC;
signal blk00000003_sig000004eb : STD_LOGIC;
signal blk00000003_sig000004ea : STD_LOGIC;
signal blk00000003_sig000004e9 : STD_LOGIC;
signal blk00000003_sig000004e8 : STD_LOGIC;
signal blk00000003_sig000004e7 : STD_LOGIC;
signal blk00000003_sig000004e6 : STD_LOGIC;
signal blk00000003_sig000004e5 : STD_LOGIC;
signal blk00000003_sig000004e4 : STD_LOGIC;
signal blk00000003_sig000004e3 : STD_LOGIC;
signal blk00000003_sig000004e2 : STD_LOGIC;
signal blk00000003_sig000004e1 : STD_LOGIC;
signal blk00000003_sig000004e0 : STD_LOGIC;
signal blk00000003_sig000004df : STD_LOGIC;
signal blk00000003_sig000004de : STD_LOGIC;
signal blk00000003_sig000004dd : STD_LOGIC;
signal blk00000003_sig000004dc : STD_LOGIC;
signal blk00000003_sig000004db : STD_LOGIC;
signal blk00000003_sig000004da : STD_LOGIC;
signal blk00000003_sig000004d9 : STD_LOGIC;
signal blk00000003_sig000004d8 : STD_LOGIC;
signal blk00000003_sig000004d7 : STD_LOGIC;
signal blk00000003_sig000004d6 : STD_LOGIC;
signal blk00000003_sig000004d5 : STD_LOGIC;
signal blk00000003_sig000004d4 : STD_LOGIC;
signal blk00000003_sig000004d3 : STD_LOGIC;
signal blk00000003_sig000004d2 : STD_LOGIC;
signal blk00000003_sig000004d1 : STD_LOGIC;
signal blk00000003_sig000004d0 : STD_LOGIC;
signal blk00000003_sig000004cf : STD_LOGIC;
signal blk00000003_sig000004ce : STD_LOGIC;
signal blk00000003_sig000004cd : STD_LOGIC;
signal blk00000003_sig000004cc : STD_LOGIC;
signal blk00000003_sig000004cb : STD_LOGIC;
signal blk00000003_sig000004ca : STD_LOGIC;
signal blk00000003_sig000004c9 : STD_LOGIC;
signal blk00000003_sig000004c8 : STD_LOGIC;
signal blk00000003_sig000004c7 : STD_LOGIC;
signal blk00000003_sig000004c6 : STD_LOGIC;
signal blk00000003_sig000004c5 : STD_LOGIC;
signal blk00000003_sig000004c4 : STD_LOGIC;
signal blk00000003_sig000004c3 : STD_LOGIC;
signal blk00000003_sig000004c2 : STD_LOGIC;
signal blk00000003_sig000004c1 : STD_LOGIC;
signal blk00000003_sig000004c0 : STD_LOGIC;
signal blk00000003_sig000004bf : STD_LOGIC;
signal blk00000003_sig000004be : STD_LOGIC;
signal blk00000003_sig000004bd : STD_LOGIC;
signal blk00000003_sig000004bc : STD_LOGIC;
signal blk00000003_sig000004bb : STD_LOGIC;
signal blk00000003_sig000004ba : STD_LOGIC;
signal blk00000003_sig000004b9 : STD_LOGIC;
signal blk00000003_sig000004b8 : STD_LOGIC;
signal blk00000003_sig000004b7 : STD_LOGIC;
signal blk00000003_sig000004b6 : STD_LOGIC;
signal blk00000003_sig000004b5 : STD_LOGIC;
signal blk00000003_sig000004b4 : STD_LOGIC;
signal blk00000003_sig000004b3 : STD_LOGIC;
signal blk00000003_sig000004b2 : STD_LOGIC;
signal blk00000003_sig000004b1 : STD_LOGIC;
signal blk00000003_sig000004b0 : STD_LOGIC;
signal blk00000003_sig000004af : STD_LOGIC;
signal blk00000003_sig000004ae : STD_LOGIC;
signal blk00000003_sig000004ad : STD_LOGIC;
signal blk00000003_sig000004ac : STD_LOGIC;
signal blk00000003_sig000004ab : STD_LOGIC;
signal blk00000003_sig000004aa : STD_LOGIC;
signal blk00000003_sig000004a9 : STD_LOGIC;
signal blk00000003_sig000004a8 : STD_LOGIC;
signal blk00000003_sig000004a7 : STD_LOGIC;
signal blk00000003_sig000004a6 : STD_LOGIC;
signal blk00000003_sig000004a5 : STD_LOGIC;
signal blk00000003_sig000004a4 : STD_LOGIC;
signal blk00000003_sig000004a3 : STD_LOGIC;
signal blk00000003_sig000004a2 : STD_LOGIC;
signal blk00000003_sig000004a1 : STD_LOGIC;
signal blk00000003_sig000004a0 : STD_LOGIC;
signal blk00000003_sig0000049f : STD_LOGIC;
signal blk00000003_sig0000049e : STD_LOGIC;
signal blk00000003_sig0000049d : STD_LOGIC;
signal blk00000003_sig0000049c : STD_LOGIC;
signal blk00000003_sig0000049b : STD_LOGIC;
signal blk00000003_sig0000049a : STD_LOGIC;
signal blk00000003_sig00000499 : STD_LOGIC;
signal blk00000003_sig00000498 : STD_LOGIC;
signal blk00000003_sig00000497 : STD_LOGIC;
signal blk00000003_sig00000496 : STD_LOGIC;
signal blk00000003_sig00000495 : STD_LOGIC;
signal blk00000003_sig00000494 : STD_LOGIC;
signal blk00000003_sig00000493 : STD_LOGIC;
signal blk00000003_sig00000492 : STD_LOGIC;
signal blk00000003_sig00000491 : STD_LOGIC;
signal blk00000003_sig00000490 : STD_LOGIC;
signal blk00000003_sig0000048f : STD_LOGIC;
signal blk00000003_sig0000048e : STD_LOGIC;
signal blk00000003_sig0000048d : STD_LOGIC;
signal blk00000003_sig0000048c : STD_LOGIC;
signal blk00000003_sig0000048b : STD_LOGIC;
signal blk00000003_sig0000048a : STD_LOGIC;
signal blk00000003_sig00000489 : STD_LOGIC;
signal blk00000003_sig00000488 : STD_LOGIC;
signal blk00000003_sig00000487 : STD_LOGIC;
signal blk00000003_sig00000486 : STD_LOGIC;
signal blk00000003_sig00000485 : STD_LOGIC;
signal blk00000003_sig00000484 : STD_LOGIC;
signal blk00000003_sig00000483 : STD_LOGIC;
signal blk00000003_sig00000482 : STD_LOGIC;
signal blk00000003_sig00000481 : STD_LOGIC;
signal blk00000003_sig00000480 : STD_LOGIC;
signal blk00000003_sig0000047f : STD_LOGIC;
signal blk00000003_sig0000047e : STD_LOGIC;
signal blk00000003_sig0000047d : STD_LOGIC;
signal blk00000003_sig0000047c : STD_LOGIC;
signal blk00000003_sig0000047b : STD_LOGIC;
signal blk00000003_sig0000047a : STD_LOGIC;
signal blk00000003_sig00000479 : STD_LOGIC;
signal blk00000003_sig00000478 : STD_LOGIC;
signal blk00000003_sig00000477 : STD_LOGIC;
signal blk00000003_sig00000476 : STD_LOGIC;
signal blk00000003_sig00000475 : STD_LOGIC;
signal blk00000003_sig00000474 : STD_LOGIC;
signal blk00000003_sig00000473 : STD_LOGIC;
signal blk00000003_sig00000472 : STD_LOGIC;
signal blk00000003_sig00000471 : STD_LOGIC;
signal blk00000003_sig00000470 : STD_LOGIC;
signal blk00000003_sig0000046f : STD_LOGIC;
signal blk00000003_sig0000046e : STD_LOGIC;
signal blk00000003_sig0000046d : STD_LOGIC;
signal blk00000003_sig0000046c : STD_LOGIC;
signal blk00000003_sig0000046b : STD_LOGIC;
signal blk00000003_sig0000046a : STD_LOGIC;
signal blk00000003_sig00000469 : STD_LOGIC;
signal blk00000003_sig00000468 : STD_LOGIC;
signal blk00000003_sig00000467 : STD_LOGIC;
signal blk00000003_sig00000466 : STD_LOGIC;
signal blk00000003_sig00000465 : STD_LOGIC;
signal blk00000003_sig00000464 : STD_LOGIC;
signal blk00000003_sig00000463 : STD_LOGIC;
signal blk00000003_sig00000462 : STD_LOGIC;
signal blk00000003_sig00000461 : STD_LOGIC;
signal blk00000003_sig00000460 : STD_LOGIC;
signal blk00000003_sig0000045f : STD_LOGIC;
signal blk00000003_sig0000045e : STD_LOGIC;
signal blk00000003_sig0000045d : STD_LOGIC;
signal blk00000003_sig0000045c : STD_LOGIC;
signal blk00000003_sig0000045b : STD_LOGIC;
signal blk00000003_sig0000045a : STD_LOGIC;
signal blk00000003_sig00000459 : STD_LOGIC;
signal blk00000003_sig00000458 : STD_LOGIC;
signal blk00000003_sig00000457 : STD_LOGIC;
signal blk00000003_sig00000456 : STD_LOGIC;
signal blk00000003_sig00000455 : STD_LOGIC;
signal blk00000003_sig00000454 : STD_LOGIC;
signal blk00000003_sig00000453 : STD_LOGIC;
signal blk00000003_sig00000452 : STD_LOGIC;
signal blk00000003_sig00000451 : STD_LOGIC;
signal blk00000003_sig00000450 : STD_LOGIC;
signal blk00000003_sig0000044f : STD_LOGIC;
signal blk00000003_sig0000044e : STD_LOGIC;
signal blk00000003_sig0000044d : STD_LOGIC;
signal blk00000003_sig0000044c : STD_LOGIC;
signal blk00000003_sig0000044b : STD_LOGIC;
signal blk00000003_sig0000044a : STD_LOGIC;
signal blk00000003_sig00000449 : STD_LOGIC;
signal blk00000003_sig00000448 : STD_LOGIC;
signal blk00000003_sig00000447 : STD_LOGIC;
signal blk00000003_sig00000446 : STD_LOGIC;
signal blk00000003_sig00000445 : STD_LOGIC;
signal blk00000003_sig00000444 : STD_LOGIC;
signal blk00000003_sig00000443 : STD_LOGIC;
signal blk00000003_sig00000442 : STD_LOGIC;
signal blk00000003_sig00000441 : STD_LOGIC;
signal blk00000003_sig00000440 : STD_LOGIC;
signal blk00000003_sig0000043f : STD_LOGIC;
signal blk00000003_sig0000043e : STD_LOGIC;
signal blk00000003_sig0000043d : STD_LOGIC;
signal blk00000003_sig0000043c : STD_LOGIC;
signal blk00000003_sig0000043b : STD_LOGIC;
signal blk00000003_sig0000043a : STD_LOGIC;
signal blk00000003_sig00000439 : STD_LOGIC;
signal blk00000003_sig00000438 : STD_LOGIC;
signal blk00000003_sig00000437 : STD_LOGIC;
signal blk00000003_sig00000436 : STD_LOGIC;
signal blk00000003_sig00000435 : STD_LOGIC;
signal blk00000003_sig00000434 : STD_LOGIC;
signal blk00000003_sig00000433 : STD_LOGIC;
signal blk00000003_sig00000432 : STD_LOGIC;
signal blk00000003_sig00000431 : STD_LOGIC;
signal blk00000003_sig00000430 : STD_LOGIC;
signal blk00000003_sig0000042f : STD_LOGIC;
signal blk00000003_sig0000042e : STD_LOGIC;
signal blk00000003_sig0000042d : STD_LOGIC;
signal blk00000003_sig0000042c : STD_LOGIC;
signal blk00000003_sig0000042b : STD_LOGIC;
signal blk00000003_sig0000042a : STD_LOGIC;
signal blk00000003_sig00000429 : STD_LOGIC;
signal blk00000003_sig00000428 : STD_LOGIC;
signal blk00000003_sig00000427 : STD_LOGIC;
signal blk00000003_sig00000426 : STD_LOGIC;
signal blk00000003_sig00000425 : STD_LOGIC;
signal blk00000003_sig00000424 : STD_LOGIC;
signal blk00000003_sig00000423 : STD_LOGIC;
signal blk00000003_sig00000422 : STD_LOGIC;
signal blk00000003_sig00000421 : STD_LOGIC;
signal blk00000003_sig00000420 : STD_LOGIC;
signal blk00000003_sig0000041f : STD_LOGIC;
signal blk00000003_sig0000041e : STD_LOGIC;
signal blk00000003_sig0000041d : STD_LOGIC;
signal blk00000003_sig0000041c : STD_LOGIC;
signal blk00000003_sig0000041b : STD_LOGIC;
signal blk00000003_sig0000041a : STD_LOGIC;
signal blk00000003_sig00000419 : STD_LOGIC;
signal blk00000003_sig00000418 : STD_LOGIC;
signal blk00000003_sig00000417 : STD_LOGIC;
signal blk00000003_sig00000416 : STD_LOGIC;
signal blk00000003_sig00000415 : STD_LOGIC;
signal blk00000003_sig00000414 : STD_LOGIC;
signal blk00000003_sig00000413 : STD_LOGIC;
signal blk00000003_sig00000412 : STD_LOGIC;
signal blk00000003_sig00000411 : STD_LOGIC;
signal blk00000003_sig00000410 : STD_LOGIC;
signal blk00000003_sig0000040f : STD_LOGIC;
signal blk00000003_sig0000040e : STD_LOGIC;
signal blk00000003_sig0000040d : STD_LOGIC;
signal blk00000003_sig0000040c : STD_LOGIC;
signal blk00000003_sig0000040b : STD_LOGIC;
signal blk00000003_sig0000040a : STD_LOGIC;
signal blk00000003_sig00000409 : STD_LOGIC;
signal blk00000003_sig00000408 : STD_LOGIC;
signal blk00000003_sig00000407 : STD_LOGIC;
signal blk00000003_sig00000406 : STD_LOGIC;
signal blk00000003_sig00000405 : STD_LOGIC;
signal blk00000003_sig00000404 : STD_LOGIC;
signal blk00000003_sig00000403 : STD_LOGIC;
signal blk00000003_sig00000402 : STD_LOGIC;
signal blk00000003_sig00000401 : STD_LOGIC;
signal blk00000003_sig00000400 : STD_LOGIC;
signal blk00000003_sig000003ff : STD_LOGIC;
signal blk00000003_sig000003fe : STD_LOGIC;
signal blk00000003_sig000003fd : STD_LOGIC;
signal blk00000003_sig000003fc : STD_LOGIC;
signal blk00000003_sig000003fb : STD_LOGIC;
signal blk00000003_sig000003fa : STD_LOGIC;
signal blk00000003_sig000003f9 : STD_LOGIC;
signal blk00000003_sig000003f8 : STD_LOGIC;
signal blk00000003_sig000003f7 : STD_LOGIC;
signal blk00000003_sig000003f6 : STD_LOGIC;
signal blk00000003_sig000003f5 : STD_LOGIC;
signal blk00000003_sig000003f4 : STD_LOGIC;
signal blk00000003_sig000003f3 : STD_LOGIC;
signal blk00000003_sig000003f2 : STD_LOGIC;
signal blk00000003_sig000003f1 : STD_LOGIC;
signal blk00000003_sig000003f0 : STD_LOGIC;
signal blk00000003_sig000003ef : STD_LOGIC;
signal blk00000003_sig000003ee : STD_LOGIC;
signal blk00000003_sig000003ed : STD_LOGIC;
signal blk00000003_sig000003ec : STD_LOGIC;
signal blk00000003_sig000003eb : STD_LOGIC;
signal blk00000003_sig000003ea : STD_LOGIC;
signal blk00000003_sig000003e9 : STD_LOGIC;
signal blk00000003_sig000003e8 : STD_LOGIC;
signal blk00000003_sig000003e7 : STD_LOGIC;
signal blk00000003_sig000003e6 : STD_LOGIC;
signal blk00000003_sig000003e5 : STD_LOGIC;
signal blk00000003_sig000003e4 : STD_LOGIC;
signal blk00000003_sig000003e3 : STD_LOGIC;
signal blk00000003_sig000003e2 : STD_LOGIC;
signal blk00000003_sig000003e1 : STD_LOGIC;
signal blk00000003_sig000003e0 : STD_LOGIC;
signal blk00000003_sig000003df : STD_LOGIC;
signal blk00000003_sig000003de : STD_LOGIC;
signal blk00000003_sig000003dd : STD_LOGIC;
signal blk00000003_sig000003dc : STD_LOGIC;
signal blk00000003_sig000003db : STD_LOGIC;
signal blk00000003_sig000003da : STD_LOGIC;
signal blk00000003_sig000003d9 : STD_LOGIC;
signal blk00000003_sig000003d8 : STD_LOGIC;
signal blk00000003_sig000003d7 : STD_LOGIC;
signal blk00000003_sig000003d6 : STD_LOGIC;
signal blk00000003_sig000003d5 : STD_LOGIC;
signal blk00000003_sig000003d4 : STD_LOGIC;
signal blk00000003_sig000003d3 : STD_LOGIC;
signal blk00000003_sig000003d2 : STD_LOGIC;
signal blk00000003_sig000003d1 : STD_LOGIC;
signal blk00000003_sig000003d0 : STD_LOGIC;
signal blk00000003_sig000003cf : STD_LOGIC;
signal blk00000003_sig000003ce : STD_LOGIC;
signal blk00000003_sig000003cd : STD_LOGIC;
signal blk00000003_sig000003cc : STD_LOGIC;
signal blk00000003_sig000003cb : STD_LOGIC;
signal blk00000003_sig000003ca : STD_LOGIC;
signal blk00000003_sig000003c9 : STD_LOGIC;
signal blk00000003_sig000003c8 : STD_LOGIC;
signal blk00000003_sig000003c7 : STD_LOGIC;
signal blk00000003_sig000003c6 : STD_LOGIC;
signal blk00000003_sig000003c5 : STD_LOGIC;
signal blk00000003_sig000003c4 : STD_LOGIC;
signal blk00000003_sig000003c3 : STD_LOGIC;
signal blk00000003_sig000003c2 : STD_LOGIC;
signal blk00000003_sig000003c1 : STD_LOGIC;
signal blk00000003_sig000003c0 : STD_LOGIC;
signal blk00000003_sig000003bf : STD_LOGIC;
signal blk00000003_sig000003be : STD_LOGIC;
signal blk00000003_sig000003bd : STD_LOGIC;
signal blk00000003_sig000003bc : STD_LOGIC;
signal blk00000003_sig000003bb : STD_LOGIC;
signal blk00000003_sig000003ba : STD_LOGIC;
signal blk00000003_sig000003b9 : STD_LOGIC;
signal blk00000003_sig000003b8 : STD_LOGIC;
signal blk00000003_sig000003b7 : STD_LOGIC;
signal blk00000003_sig000003b6 : STD_LOGIC;
signal blk00000003_sig000003b5 : STD_LOGIC;
signal blk00000003_sig000003b4 : STD_LOGIC;
signal blk00000003_sig000003b3 : STD_LOGIC;
signal blk00000003_sig000003b2 : STD_LOGIC;
signal blk00000003_sig000003b1 : STD_LOGIC;
signal blk00000003_sig000003b0 : STD_LOGIC;
signal blk00000003_sig000003af : STD_LOGIC;
signal blk00000003_sig000003ae : STD_LOGIC;
signal blk00000003_sig000003ad : STD_LOGIC;
signal blk00000003_sig000003ac : STD_LOGIC;
signal blk00000003_sig000003ab : STD_LOGIC;
signal blk00000003_sig000003aa : STD_LOGIC;
signal blk00000003_sig000003a9 : STD_LOGIC;
signal blk00000003_sig000003a8 : STD_LOGIC;
signal blk00000003_sig000003a7 : STD_LOGIC;
signal blk00000003_sig000003a6 : STD_LOGIC;
signal blk00000003_sig000003a5 : STD_LOGIC;
signal blk00000003_sig000003a4 : STD_LOGIC;
signal blk00000003_sig000003a3 : STD_LOGIC;
signal blk00000003_sig000003a2 : STD_LOGIC;
signal blk00000003_sig000003a1 : STD_LOGIC;
signal blk00000003_sig000003a0 : STD_LOGIC;
signal blk00000003_sig0000039f : STD_LOGIC;
signal blk00000003_sig0000039e : STD_LOGIC;
signal blk00000003_sig0000039d : STD_LOGIC;
signal blk00000003_sig0000039c : STD_LOGIC;
signal blk00000003_sig0000039b : STD_LOGIC;
signal blk00000003_sig0000039a : STD_LOGIC;
signal blk00000003_sig00000399 : STD_LOGIC;
signal blk00000003_sig00000398 : STD_LOGIC;
signal blk00000003_sig00000397 : STD_LOGIC;
signal blk00000003_sig00000396 : STD_LOGIC;
signal blk00000003_sig00000395 : STD_LOGIC;
signal blk00000003_sig00000394 : STD_LOGIC;
signal blk00000003_sig00000393 : STD_LOGIC;
signal blk00000003_sig00000392 : STD_LOGIC;
signal blk00000003_sig00000391 : STD_LOGIC;
signal blk00000003_sig00000390 : STD_LOGIC;
signal blk00000003_sig0000038f : STD_LOGIC;
signal blk00000003_sig0000038e : STD_LOGIC;
signal blk00000003_sig0000038d : STD_LOGIC;
signal blk00000003_sig0000038c : STD_LOGIC;
signal blk00000003_sig0000038b : STD_LOGIC;
signal blk00000003_sig0000038a : STD_LOGIC;
signal blk00000003_sig00000389 : STD_LOGIC;
signal blk00000003_sig00000388 : STD_LOGIC;
signal blk00000003_sig00000387 : STD_LOGIC;
signal blk00000003_sig00000386 : STD_LOGIC;
signal blk00000003_sig00000385 : STD_LOGIC;
signal blk00000003_sig00000384 : STD_LOGIC;
signal blk00000003_sig00000383 : STD_LOGIC;
signal blk00000003_sig00000382 : STD_LOGIC;
signal blk00000003_sig00000381 : STD_LOGIC;
signal blk00000003_sig00000380 : STD_LOGIC;
signal blk00000003_sig0000037f : STD_LOGIC;
signal blk00000003_sig0000037e : STD_LOGIC;
signal blk00000003_sig0000037d : STD_LOGIC;
signal blk00000003_sig0000037c : STD_LOGIC;
signal blk00000003_sig0000037b : STD_LOGIC;
signal blk00000003_sig0000037a : STD_LOGIC;
signal blk00000003_sig00000379 : STD_LOGIC;
signal blk00000003_sig00000378 : STD_LOGIC;
signal blk00000003_sig00000377 : STD_LOGIC;
signal blk00000003_sig00000376 : STD_LOGIC;
signal blk00000003_sig00000375 : STD_LOGIC;
signal blk00000003_sig00000374 : STD_LOGIC;
signal blk00000003_sig00000373 : STD_LOGIC;
signal blk00000003_sig00000372 : STD_LOGIC;
signal blk00000003_sig00000371 : STD_LOGIC;
signal blk00000003_sig00000370 : STD_LOGIC;
signal blk00000003_sig0000036f : STD_LOGIC;
signal blk00000003_sig0000036e : STD_LOGIC;
signal blk00000003_sig0000036d : STD_LOGIC;
signal blk00000003_sig0000036c : STD_LOGIC;
signal blk00000003_sig0000036b : STD_LOGIC;
signal blk00000003_sig0000036a : STD_LOGIC;
signal blk00000003_sig00000369 : STD_LOGIC;
signal blk00000003_sig00000368 : STD_LOGIC;
signal blk00000003_sig00000367 : STD_LOGIC;
signal blk00000003_sig00000366 : STD_LOGIC;
signal blk00000003_sig00000365 : STD_LOGIC;
signal blk00000003_sig00000364 : STD_LOGIC;
signal blk00000003_sig00000363 : STD_LOGIC;
signal blk00000003_sig00000362 : STD_LOGIC;
signal blk00000003_sig00000361 : STD_LOGIC;
signal blk00000003_sig00000360 : STD_LOGIC;
signal blk00000003_sig0000035f : STD_LOGIC;
signal blk00000003_sig0000035e : STD_LOGIC;
signal blk00000003_sig0000035d : STD_LOGIC;
signal blk00000003_sig0000035c : STD_LOGIC;
signal blk00000003_sig0000035b : STD_LOGIC;
signal blk00000003_sig0000035a : STD_LOGIC;
signal blk00000003_sig00000359 : STD_LOGIC;
signal blk00000003_sig00000358 : STD_LOGIC;
signal blk00000003_sig00000357 : STD_LOGIC;
signal blk00000003_sig00000356 : STD_LOGIC;
signal blk00000003_sig00000355 : STD_LOGIC;
signal blk00000003_sig00000354 : STD_LOGIC;
signal blk00000003_sig00000353 : STD_LOGIC;
signal blk00000003_sig00000352 : STD_LOGIC;
signal blk00000003_sig00000351 : STD_LOGIC;
signal blk00000003_sig00000350 : STD_LOGIC;
signal blk00000003_sig0000034f : STD_LOGIC;
signal blk00000003_sig0000034e : STD_LOGIC;
signal blk00000003_sig0000034d : STD_LOGIC;
signal blk00000003_sig0000034c : STD_LOGIC;
signal blk00000003_sig0000034b : STD_LOGIC;
signal blk00000003_sig0000034a : STD_LOGIC;
signal blk00000003_sig00000349 : STD_LOGIC;
signal blk00000003_sig00000348 : STD_LOGIC;
signal blk00000003_sig00000347 : STD_LOGIC;
signal blk00000003_sig00000346 : STD_LOGIC;
signal blk00000003_sig00000345 : STD_LOGIC;
signal blk00000003_sig00000344 : STD_LOGIC;
signal blk00000003_sig00000343 : STD_LOGIC;
signal blk00000003_sig00000342 : STD_LOGIC;
signal blk00000003_sig00000341 : STD_LOGIC;
signal blk00000003_sig00000340 : STD_LOGIC;
signal blk00000003_sig0000033f : STD_LOGIC;
signal blk00000003_sig0000033e : STD_LOGIC;
signal blk00000003_sig0000033d : STD_LOGIC;
signal blk00000003_sig0000033c : STD_LOGIC;
signal blk00000003_sig0000033b : STD_LOGIC;
signal blk00000003_sig0000033a : STD_LOGIC;
signal blk00000003_sig00000339 : STD_LOGIC;
signal blk00000003_sig00000338 : STD_LOGIC;
signal blk00000003_sig00000337 : STD_LOGIC;
signal blk00000003_sig00000336 : STD_LOGIC;
signal blk00000003_sig00000335 : STD_LOGIC;
signal blk00000003_sig00000334 : STD_LOGIC;
signal blk00000003_sig00000333 : STD_LOGIC;
signal blk00000003_sig00000332 : STD_LOGIC;
signal blk00000003_sig00000331 : STD_LOGIC;
signal blk00000003_sig00000330 : STD_LOGIC;
signal blk00000003_sig0000032f : STD_LOGIC;
signal blk00000003_sig0000032e : STD_LOGIC;
signal blk00000003_sig0000032d : STD_LOGIC;
signal blk00000003_sig0000032c : STD_LOGIC;
signal blk00000003_sig0000032b : STD_LOGIC;
signal blk00000003_sig0000032a : STD_LOGIC;
signal blk00000003_sig00000329 : STD_LOGIC;
signal blk00000003_sig00000328 : STD_LOGIC;
signal blk00000003_sig00000327 : STD_LOGIC;
signal blk00000003_sig00000326 : STD_LOGIC;
signal blk00000003_sig00000325 : STD_LOGIC;
signal blk00000003_sig00000324 : STD_LOGIC;
signal blk00000003_sig00000323 : STD_LOGIC;
signal blk00000003_sig00000322 : STD_LOGIC;
signal blk00000003_sig00000321 : STD_LOGIC;
signal blk00000003_sig00000320 : STD_LOGIC;
signal blk00000003_sig0000031f : STD_LOGIC;
signal blk00000003_sig0000031e : STD_LOGIC;
signal blk00000003_sig0000031d : STD_LOGIC;
signal blk00000003_sig0000031c : STD_LOGIC;
signal blk00000003_sig0000031b : STD_LOGIC;
signal blk00000003_sig0000031a : STD_LOGIC;
signal blk00000003_sig00000319 : STD_LOGIC;
signal blk00000003_sig00000318 : STD_LOGIC;
signal blk00000003_sig00000317 : STD_LOGIC;
signal blk00000003_sig00000316 : STD_LOGIC;
signal blk00000003_sig00000315 : STD_LOGIC;
signal blk00000003_sig00000314 : STD_LOGIC;
signal blk00000003_sig00000313 : STD_LOGIC;
signal blk00000003_sig00000312 : STD_LOGIC;
signal blk00000003_sig00000311 : STD_LOGIC;
signal blk00000003_sig00000310 : STD_LOGIC;
signal blk00000003_sig0000030f : STD_LOGIC;
signal blk00000003_sig0000030e : STD_LOGIC;
signal blk00000003_sig0000030d : STD_LOGIC;
signal blk00000003_sig0000030c : STD_LOGIC;
signal blk00000003_sig0000030b : STD_LOGIC;
signal blk00000003_sig0000030a : STD_LOGIC;
signal blk00000003_sig00000309 : STD_LOGIC;
signal blk00000003_sig00000308 : STD_LOGIC;
signal blk00000003_sig00000307 : STD_LOGIC;
signal blk00000003_sig00000306 : STD_LOGIC;
signal blk00000003_sig00000305 : STD_LOGIC;
signal blk00000003_sig00000304 : STD_LOGIC;
signal blk00000003_sig00000303 : STD_LOGIC;
signal blk00000003_sig00000302 : STD_LOGIC;
signal blk00000003_sig00000301 : STD_LOGIC;
signal blk00000003_sig00000300 : STD_LOGIC;
signal blk00000003_sig000002ff : STD_LOGIC;
signal blk00000003_sig000002fe : STD_LOGIC;
signal blk00000003_sig000002fd : STD_LOGIC;
signal blk00000003_sig000002fc : STD_LOGIC;
signal blk00000003_sig000002fb : STD_LOGIC;
signal blk00000003_sig000002fa : STD_LOGIC;
signal blk00000003_sig000002f9 : STD_LOGIC;
signal blk00000003_sig000002f8 : STD_LOGIC;
signal blk00000003_sig000002f7 : STD_LOGIC;
signal blk00000003_sig000002f6 : STD_LOGIC;
signal blk00000003_sig000002f5 : STD_LOGIC;
signal blk00000003_sig000002f4 : STD_LOGIC;
signal blk00000003_sig000002f3 : STD_LOGIC;
signal blk00000003_sig000002f2 : STD_LOGIC;
signal blk00000003_sig000002f1 : STD_LOGIC;
signal blk00000003_sig000002f0 : STD_LOGIC;
signal blk00000003_sig000002ef : STD_LOGIC;
signal blk00000003_sig000002ee : STD_LOGIC;
signal blk00000003_sig000002ed : STD_LOGIC;
signal blk00000003_sig000002ec : STD_LOGIC;
signal blk00000003_sig000002eb : STD_LOGIC;
signal blk00000003_sig000002ea : STD_LOGIC;
signal blk00000003_sig000002e9 : STD_LOGIC;
signal blk00000003_sig000002e8 : STD_LOGIC;
signal blk00000003_sig000002e7 : STD_LOGIC;
signal blk00000003_sig000002e6 : STD_LOGIC;
signal blk00000003_sig000002e5 : STD_LOGIC;
signal blk00000003_sig000002e4 : STD_LOGIC;
signal blk00000003_sig000002e3 : STD_LOGIC;
signal blk00000003_sig000002e2 : STD_LOGIC;
signal blk00000003_sig000002e1 : STD_LOGIC;
signal blk00000003_sig000002e0 : STD_LOGIC;
signal blk00000003_sig000002df : STD_LOGIC;
signal blk00000003_sig000002de : STD_LOGIC;
signal blk00000003_sig000002dd : STD_LOGIC;
signal blk00000003_sig000002dc : STD_LOGIC;
signal blk00000003_sig000002db : STD_LOGIC;
signal blk00000003_sig000002da : STD_LOGIC;
signal blk00000003_sig000002d9 : STD_LOGIC;
signal blk00000003_sig000002d8 : STD_LOGIC;
signal blk00000003_sig000002d7 : STD_LOGIC;
signal blk00000003_sig000002d6 : STD_LOGIC;
signal blk00000003_sig000002d5 : STD_LOGIC;
signal blk00000003_sig000002d4 : STD_LOGIC;
signal blk00000003_sig000002d3 : STD_LOGIC;
signal blk00000003_sig000002d2 : STD_LOGIC;
signal blk00000003_sig000002d1 : STD_LOGIC;
signal blk00000003_sig000002d0 : STD_LOGIC;
signal blk00000003_sig000002cf : STD_LOGIC;
signal blk00000003_sig000002ce : STD_LOGIC;
signal blk00000003_sig000002cd : STD_LOGIC;
signal blk00000003_sig000002cc : STD_LOGIC;
signal blk00000003_sig000002cb : STD_LOGIC;
signal blk00000003_sig000002ca : STD_LOGIC;
signal blk00000003_sig000002c9 : STD_LOGIC;
signal blk00000003_sig000002c8 : STD_LOGIC;
signal blk00000003_sig000002c7 : STD_LOGIC;
signal blk00000003_sig000002c6 : STD_LOGIC;
signal blk00000003_sig000002c5 : STD_LOGIC;
signal blk00000003_sig000002c4 : STD_LOGIC;
signal blk00000003_sig000002c3 : STD_LOGIC;
signal blk00000003_sig000002c2 : STD_LOGIC;
signal blk00000003_sig000002c1 : STD_LOGIC;
signal blk00000003_sig000002c0 : STD_LOGIC;
signal blk00000003_sig000002bf : STD_LOGIC;
signal blk00000003_sig000002be : STD_LOGIC;
signal blk00000003_sig000002bd : STD_LOGIC;
signal blk00000003_sig000002bc : STD_LOGIC;
signal blk00000003_sig000002bb : STD_LOGIC;
signal blk00000003_sig000002ba : STD_LOGIC;
signal blk00000003_sig000002b9 : STD_LOGIC;
signal blk00000003_sig000002b8 : STD_LOGIC;
signal blk00000003_sig000002b7 : STD_LOGIC;
signal blk00000003_sig000002b6 : STD_LOGIC;
signal blk00000003_sig000002b5 : STD_LOGIC;
signal blk00000003_sig000002b4 : STD_LOGIC;
signal blk00000003_sig000002b3 : STD_LOGIC;
signal blk00000003_sig000002b2 : STD_LOGIC;
signal blk00000003_sig000002b1 : STD_LOGIC;
signal blk00000003_sig000002b0 : STD_LOGIC;
signal blk00000003_sig000002af : STD_LOGIC;
signal blk00000003_sig000002ae : STD_LOGIC;
signal blk00000003_sig000002ad : STD_LOGIC;
signal blk00000003_sig000002ac : STD_LOGIC;
signal blk00000003_sig000002ab : STD_LOGIC;
signal blk00000003_sig000002aa : STD_LOGIC;
signal blk00000003_sig000002a9 : STD_LOGIC;
signal blk00000003_sig000002a8 : STD_LOGIC;
signal blk00000003_sig000002a7 : STD_LOGIC;
signal blk00000003_sig000002a6 : STD_LOGIC;
signal blk00000003_sig000002a5 : STD_LOGIC;
signal blk00000003_sig000002a4 : STD_LOGIC;
signal blk00000003_sig000002a3 : STD_LOGIC;
signal blk00000003_sig000002a2 : STD_LOGIC;
signal blk00000003_sig000002a1 : STD_LOGIC;
signal blk00000003_sig000002a0 : STD_LOGIC;
signal blk00000003_sig0000029f : STD_LOGIC;
signal blk00000003_sig0000029e : STD_LOGIC;
signal blk00000003_sig0000029d : STD_LOGIC;
signal blk00000003_sig0000029c : STD_LOGIC;
signal blk00000003_sig0000029b : STD_LOGIC;
signal blk00000003_sig0000029a : STD_LOGIC;
signal blk00000003_sig00000299 : STD_LOGIC;
signal blk00000003_sig00000298 : STD_LOGIC;
signal blk00000003_sig00000297 : STD_LOGIC;
signal blk00000003_sig00000296 : STD_LOGIC;
signal blk00000003_sig00000295 : STD_LOGIC;
signal blk00000003_sig00000294 : STD_LOGIC;
signal blk00000003_sig00000293 : STD_LOGIC;
signal blk00000003_sig00000292 : STD_LOGIC;
signal blk00000003_sig00000291 : STD_LOGIC;
signal blk00000003_sig00000290 : STD_LOGIC;
signal blk00000003_sig0000028f : STD_LOGIC;
signal blk00000003_sig0000028e : STD_LOGIC;
signal blk00000003_sig0000028d : STD_LOGIC;
signal blk00000003_sig0000028c : STD_LOGIC;
signal blk00000003_sig0000028b : STD_LOGIC;
signal blk00000003_sig0000028a : STD_LOGIC;
signal blk00000003_sig00000289 : STD_LOGIC;
signal blk00000003_sig00000288 : STD_LOGIC;
signal blk00000003_sig00000287 : STD_LOGIC;
signal blk00000003_sig00000286 : STD_LOGIC;
signal blk00000003_sig00000285 : STD_LOGIC;
signal blk00000003_sig00000284 : STD_LOGIC;
signal blk00000003_sig00000283 : STD_LOGIC;
signal blk00000003_sig00000282 : STD_LOGIC;
signal blk00000003_sig00000281 : STD_LOGIC;
signal blk00000003_sig00000280 : STD_LOGIC;
signal blk00000003_sig0000027f : STD_LOGIC;
signal blk00000003_sig0000027e : STD_LOGIC;
signal blk00000003_sig0000027d : STD_LOGIC;
signal blk00000003_sig0000027c : STD_LOGIC;
signal blk00000003_sig0000027b : STD_LOGIC;
signal blk00000003_sig0000027a : STD_LOGIC;
signal blk00000003_sig00000279 : STD_LOGIC;
signal blk00000003_sig00000278 : STD_LOGIC;
signal blk00000003_sig00000277 : STD_LOGIC;
signal blk00000003_sig00000276 : STD_LOGIC;
signal blk00000003_sig00000275 : STD_LOGIC;
signal blk00000003_sig00000274 : STD_LOGIC;
signal blk00000003_sig00000273 : STD_LOGIC;
signal blk00000003_sig00000272 : STD_LOGIC;
signal blk00000003_sig00000271 : STD_LOGIC;
signal blk00000003_sig00000270 : STD_LOGIC;
signal blk00000003_sig0000026f : STD_LOGIC;
signal blk00000003_sig0000026e : STD_LOGIC;
signal blk00000003_sig0000026d : STD_LOGIC;
signal blk00000003_sig0000026c : STD_LOGIC;
signal blk00000003_sig0000026b : STD_LOGIC;
signal blk00000003_sig0000026a : STD_LOGIC;
signal blk00000003_sig00000269 : STD_LOGIC;
signal blk00000003_sig00000268 : STD_LOGIC;
signal blk00000003_sig00000267 : STD_LOGIC;
signal blk00000003_sig00000266 : STD_LOGIC;
signal blk00000003_sig00000265 : STD_LOGIC;
signal blk00000003_sig00000264 : STD_LOGIC;
signal blk00000003_sig00000263 : STD_LOGIC;
signal blk00000003_sig00000262 : STD_LOGIC;
signal blk00000003_sig00000261 : STD_LOGIC;
signal blk00000003_sig00000260 : STD_LOGIC;
signal blk00000003_sig0000025f : STD_LOGIC;
signal blk00000003_sig0000025e : STD_LOGIC;
signal blk00000003_sig0000025d : STD_LOGIC;
signal blk00000003_sig0000025c : STD_LOGIC;
signal blk00000003_sig0000025b : STD_LOGIC;
signal blk00000003_sig0000025a : STD_LOGIC;
signal blk00000003_sig00000259 : STD_LOGIC;
signal blk00000003_sig00000258 : STD_LOGIC;
signal blk00000003_sig00000257 : STD_LOGIC;
signal blk00000003_sig00000256 : STD_LOGIC;
signal blk00000003_sig00000255 : STD_LOGIC;
signal blk00000003_sig00000254 : STD_LOGIC;
signal blk00000003_sig00000253 : STD_LOGIC;
signal blk00000003_sig00000252 : STD_LOGIC;
signal blk00000003_sig00000251 : STD_LOGIC;
signal blk00000003_sig00000250 : STD_LOGIC;
signal blk00000003_sig0000024f : STD_LOGIC;
signal blk00000003_sig0000024e : STD_LOGIC;
signal blk00000003_sig0000024d : STD_LOGIC;
signal blk00000003_sig0000024c : STD_LOGIC;
signal blk00000003_sig0000024b : STD_LOGIC;
signal blk00000003_sig0000024a : STD_LOGIC;
signal blk00000003_sig00000249 : STD_LOGIC;
signal blk00000003_sig00000248 : STD_LOGIC;
signal blk00000003_sig00000247 : STD_LOGIC;
signal blk00000003_sig00000246 : STD_LOGIC;
signal blk00000003_sig00000245 : STD_LOGIC;
signal blk00000003_sig00000244 : STD_LOGIC;
signal blk00000003_sig00000243 : STD_LOGIC;
signal blk00000003_sig00000242 : STD_LOGIC;
signal blk00000003_sig00000241 : STD_LOGIC;
signal blk00000003_sig00000240 : STD_LOGIC;
signal blk00000003_sig0000023f : STD_LOGIC;
signal blk00000003_sig0000023e : STD_LOGIC;
signal blk00000003_sig0000023d : STD_LOGIC;
signal blk00000003_sig0000023c : STD_LOGIC;
signal blk00000003_sig0000023b : STD_LOGIC;
signal blk00000003_sig0000023a : STD_LOGIC;
signal blk00000003_sig00000239 : STD_LOGIC;
signal blk00000003_sig00000238 : STD_LOGIC;
signal blk00000003_sig00000237 : STD_LOGIC;
signal blk00000003_sig00000236 : STD_LOGIC;
signal blk00000003_sig00000235 : STD_LOGIC;
signal blk00000003_sig00000234 : STD_LOGIC;
signal blk00000003_sig00000233 : STD_LOGIC;
signal blk00000003_sig00000232 : STD_LOGIC;
signal blk00000003_sig00000231 : STD_LOGIC;
signal blk00000003_sig00000230 : STD_LOGIC;
signal blk00000003_sig0000022f : STD_LOGIC;
signal blk00000003_sig0000022e : STD_LOGIC;
signal blk00000003_sig0000022d : STD_LOGIC;
signal blk00000003_sig0000022c : STD_LOGIC;
signal blk00000003_sig0000022b : STD_LOGIC;
signal blk00000003_sig0000022a : STD_LOGIC;
signal blk00000003_sig00000229 : STD_LOGIC;
signal blk00000003_sig00000228 : STD_LOGIC;
signal blk00000003_sig00000227 : STD_LOGIC;
signal blk00000003_sig00000226 : STD_LOGIC;
signal blk00000003_sig00000225 : STD_LOGIC;
signal blk00000003_sig00000224 : STD_LOGIC;
signal blk00000003_sig00000223 : STD_LOGIC;
signal blk00000003_sig00000222 : STD_LOGIC;
signal blk00000003_sig00000221 : STD_LOGIC;
signal blk00000003_sig00000220 : STD_LOGIC;
signal blk00000003_sig0000021f : STD_LOGIC;
signal blk00000003_sig0000021e : STD_LOGIC;
signal blk00000003_sig0000021d : STD_LOGIC;
signal blk00000003_sig0000021c : STD_LOGIC;
signal blk00000003_sig0000021b : STD_LOGIC;
signal blk00000003_sig0000021a : STD_LOGIC;
signal blk00000003_sig00000219 : STD_LOGIC;
signal blk00000003_sig00000218 : STD_LOGIC;
signal blk00000003_sig00000217 : STD_LOGIC;
signal blk00000003_sig00000216 : STD_LOGIC;
signal blk00000003_sig00000215 : STD_LOGIC;
signal blk00000003_sig00000214 : STD_LOGIC;
signal blk00000003_sig00000213 : STD_LOGIC;
signal blk00000003_sig00000212 : STD_LOGIC;
signal blk00000003_sig00000211 : STD_LOGIC;
signal blk00000003_sig00000210 : STD_LOGIC;
signal blk00000003_sig0000020f : STD_LOGIC;
signal blk00000003_sig0000020e : STD_LOGIC;
signal blk00000003_sig0000020d : STD_LOGIC;
signal blk00000003_sig0000020c : STD_LOGIC;
signal blk00000003_sig0000020b : STD_LOGIC;
signal blk00000003_sig0000020a : STD_LOGIC;
signal blk00000003_sig00000209 : STD_LOGIC;
signal blk00000003_sig00000208 : STD_LOGIC;
signal blk00000003_sig00000207 : STD_LOGIC;
signal blk00000003_sig00000206 : STD_LOGIC;
signal blk00000003_sig00000205 : STD_LOGIC;
signal blk00000003_sig00000204 : STD_LOGIC;
signal blk00000003_sig00000203 : STD_LOGIC;
signal blk00000003_sig00000202 : STD_LOGIC;
signal blk00000003_sig00000201 : STD_LOGIC;
signal blk00000003_sig00000200 : STD_LOGIC;
signal blk00000003_sig000001ff : STD_LOGIC;
signal blk00000003_sig000001fe : STD_LOGIC;
signal blk00000003_sig000001fd : STD_LOGIC;
signal blk00000003_sig000001fc : STD_LOGIC;
signal blk00000003_sig000001fb : STD_LOGIC;
signal blk00000003_sig000001fa : STD_LOGIC;
signal blk00000003_sig000001f9 : STD_LOGIC;
signal blk00000003_sig000001f8 : STD_LOGIC;
signal blk00000003_sig000001f7 : STD_LOGIC;
signal blk00000003_sig000001f6 : STD_LOGIC;
signal blk00000003_sig000001f5 : STD_LOGIC;
signal blk00000003_sig000001f4 : STD_LOGIC;
signal blk00000003_sig000001f3 : STD_LOGIC;
signal blk00000003_sig000001f2 : STD_LOGIC;
signal blk00000003_sig000001f1 : STD_LOGIC;
signal blk00000003_sig000001f0 : STD_LOGIC;
signal blk00000003_sig000001ef : STD_LOGIC;
signal blk00000003_sig000001ee : STD_LOGIC;
signal blk00000003_sig000001ed : STD_LOGIC;
signal blk00000003_sig000001ec : STD_LOGIC;
signal blk00000003_sig000001eb : STD_LOGIC;
signal blk00000003_sig000001ea : STD_LOGIC;
signal blk00000003_sig000001e9 : STD_LOGIC;
signal blk00000003_sig000001e8 : STD_LOGIC;
signal blk00000003_sig000001e7 : STD_LOGIC;
signal blk00000003_sig000001e6 : STD_LOGIC;
signal blk00000003_sig000001e5 : STD_LOGIC;
signal blk00000003_sig000001e4 : STD_LOGIC;
signal blk00000003_sig000001e3 : STD_LOGIC;
signal blk00000003_sig000001e2 : STD_LOGIC;
signal blk00000003_sig000001e1 : STD_LOGIC;
signal blk00000003_sig000001e0 : STD_LOGIC;
signal blk00000003_sig000001df : STD_LOGIC;
signal blk00000003_sig000001de : STD_LOGIC;
signal blk00000003_sig000001dd : STD_LOGIC;
signal blk00000003_sig000001dc : STD_LOGIC;
signal blk00000003_sig000001db : STD_LOGIC;
signal blk00000003_sig000001da : STD_LOGIC;
signal blk00000003_sig000001d9 : STD_LOGIC;
signal blk00000003_sig000001d8 : STD_LOGIC;
signal blk00000003_sig000001d7 : STD_LOGIC;
signal blk00000003_sig000001d6 : STD_LOGIC;
signal blk00000003_sig000001d5 : STD_LOGIC;
signal blk00000003_sig000001d4 : STD_LOGIC;
signal blk00000003_sig000001d3 : STD_LOGIC;
signal blk00000003_sig000001d2 : STD_LOGIC;
signal blk00000003_sig000001d1 : STD_LOGIC;
signal blk00000003_sig000001d0 : STD_LOGIC;
signal blk00000003_sig000001cf : STD_LOGIC;
signal blk00000003_sig000001ce : STD_LOGIC;
signal blk00000003_sig000001cd : STD_LOGIC;
signal blk00000003_sig000001cc : STD_LOGIC;
signal blk00000003_sig000001cb : STD_LOGIC;
signal blk00000003_sig000001ca : STD_LOGIC;
signal blk00000003_sig000001c9 : STD_LOGIC;
signal blk00000003_sig000001c8 : STD_LOGIC;
signal blk00000003_sig000001c7 : STD_LOGIC;
signal blk00000003_sig000001c6 : STD_LOGIC;
signal blk00000003_sig000001c5 : STD_LOGIC;
signal blk00000003_sig000001c4 : STD_LOGIC;
signal blk00000003_sig000001c3 : STD_LOGIC;
signal blk00000003_sig000001c2 : STD_LOGIC;
signal blk00000003_sig000001c1 : STD_LOGIC;
signal blk00000003_sig000001c0 : STD_LOGIC;
signal blk00000003_sig000001bf : STD_LOGIC;
signal blk00000003_sig000001be : STD_LOGIC;
signal blk00000003_sig000001bd : STD_LOGIC;
signal blk00000003_sig000001bc : STD_LOGIC;
signal blk00000003_sig000001bb : STD_LOGIC;
signal blk00000003_sig000001ba : STD_LOGIC;
signal blk00000003_sig000001b9 : STD_LOGIC;
signal blk00000003_sig000001b8 : STD_LOGIC;
signal blk00000003_sig000001b7 : STD_LOGIC;
signal blk00000003_sig000001b6 : STD_LOGIC;
signal blk00000003_sig000001b5 : STD_LOGIC;
signal blk00000003_sig000001b4 : STD_LOGIC;
signal blk00000003_sig000001b3 : STD_LOGIC;
signal blk00000003_sig000001b2 : STD_LOGIC;
signal blk00000003_sig000001b1 : STD_LOGIC;
signal blk00000003_sig000001b0 : STD_LOGIC;
signal blk00000003_sig000001af : STD_LOGIC;
signal blk00000003_sig000001ae : STD_LOGIC;
signal blk00000003_sig000001ad : STD_LOGIC;
signal blk00000003_sig000001ac : STD_LOGIC;
signal blk00000003_sig000001ab : STD_LOGIC;
signal blk00000003_sig000001aa : STD_LOGIC;
signal blk00000003_sig000001a9 : STD_LOGIC;
signal blk00000003_sig000001a8 : STD_LOGIC;
signal blk00000003_sig000001a7 : STD_LOGIC;
signal blk00000003_sig000001a6 : STD_LOGIC;
signal blk00000003_sig000001a5 : STD_LOGIC;
signal blk00000003_sig000001a4 : STD_LOGIC;
signal blk00000003_sig000001a3 : STD_LOGIC;
signal blk00000003_sig000001a2 : STD_LOGIC;
signal blk00000003_sig000001a1 : STD_LOGIC;
signal blk00000003_sig000001a0 : STD_LOGIC;
signal blk00000003_sig0000019f : STD_LOGIC;
signal blk00000003_sig0000019e : STD_LOGIC;
signal blk00000003_sig0000019d : STD_LOGIC;
signal blk00000003_sig0000019c : STD_LOGIC;
signal blk00000003_sig0000019b : STD_LOGIC;
signal blk00000003_sig0000019a : STD_LOGIC;
signal blk00000003_sig00000199 : STD_LOGIC;
signal blk00000003_sig00000198 : STD_LOGIC;
signal blk00000003_sig00000197 : STD_LOGIC;
signal blk00000003_sig00000196 : STD_LOGIC;
signal blk00000003_sig00000195 : STD_LOGIC;
signal blk00000003_sig00000194 : STD_LOGIC;
signal blk00000003_sig00000193 : STD_LOGIC;
signal blk00000003_sig00000192 : STD_LOGIC;
signal blk00000003_sig00000191 : STD_LOGIC;
signal blk00000003_sig00000190 : STD_LOGIC;
signal blk00000003_sig0000018f : STD_LOGIC;
signal blk00000003_sig0000018e : STD_LOGIC;
signal blk00000003_sig0000018d : STD_LOGIC;
signal blk00000003_sig0000018c : STD_LOGIC;
signal blk00000003_sig0000018b : STD_LOGIC;
signal blk00000003_sig0000018a : STD_LOGIC;
signal blk00000003_sig00000189 : STD_LOGIC;
signal blk00000003_sig00000188 : STD_LOGIC;
signal blk00000003_sig00000187 : STD_LOGIC;
signal blk00000003_sig00000186 : STD_LOGIC;
signal blk00000003_sig00000185 : STD_LOGIC;
signal blk00000003_sig00000184 : STD_LOGIC;
signal blk00000003_sig00000183 : STD_LOGIC;
signal blk00000003_sig00000182 : STD_LOGIC;
signal blk00000003_sig00000181 : STD_LOGIC;
signal blk00000003_sig00000180 : STD_LOGIC;
signal blk00000003_sig0000017f : STD_LOGIC;
signal blk00000003_sig0000017e : STD_LOGIC;
signal blk00000003_sig0000017d : STD_LOGIC;
signal blk00000003_sig0000017c : STD_LOGIC;
signal blk00000003_sig0000017b : STD_LOGIC;
signal blk00000003_sig0000017a : STD_LOGIC;
signal blk00000003_sig00000179 : STD_LOGIC;
signal blk00000003_sig00000178 : STD_LOGIC;
signal blk00000003_sig00000177 : STD_LOGIC;
signal blk00000003_sig00000176 : STD_LOGIC;
signal blk00000003_sig00000175 : STD_LOGIC;
signal blk00000003_sig00000174 : STD_LOGIC;
signal blk00000003_sig00000173 : STD_LOGIC;
signal blk00000003_sig00000172 : STD_LOGIC;
signal blk00000003_sig00000171 : STD_LOGIC;
signal blk00000003_sig00000170 : STD_LOGIC;
signal blk00000003_sig0000016f : STD_LOGIC;
signal blk00000003_sig0000016e : STD_LOGIC;
signal blk00000003_sig0000016d : STD_LOGIC;
signal blk00000003_sig0000016c : STD_LOGIC;
signal blk00000003_sig0000016b : STD_LOGIC;
signal blk00000003_sig0000016a : STD_LOGIC;
signal blk00000003_sig00000169 : STD_LOGIC;
signal blk00000003_sig00000168 : STD_LOGIC;
signal blk00000003_sig00000167 : STD_LOGIC;
signal blk00000003_sig00000166 : STD_LOGIC;
signal blk00000003_sig00000165 : STD_LOGIC;
signal blk00000003_sig00000164 : STD_LOGIC;
signal blk00000003_sig00000163 : STD_LOGIC;
signal blk00000003_sig00000162 : STD_LOGIC;
signal blk00000003_sig00000161 : STD_LOGIC;
signal blk00000003_sig00000160 : STD_LOGIC;
signal blk00000003_sig0000015f : STD_LOGIC;
signal blk00000003_sig0000015e : STD_LOGIC;
signal blk00000003_sig0000015d : STD_LOGIC;
signal blk00000003_sig0000015c : STD_LOGIC;
signal blk00000003_sig0000015b : STD_LOGIC;
signal blk00000003_sig0000015a : STD_LOGIC;
signal blk00000003_sig00000159 : STD_LOGIC;
signal blk00000003_sig00000158 : STD_LOGIC;
signal blk00000003_sig00000157 : STD_LOGIC;
signal blk00000003_sig00000156 : STD_LOGIC;
signal blk00000003_sig00000155 : STD_LOGIC;
signal blk00000003_sig00000154 : STD_LOGIC;
signal blk00000003_sig00000153 : STD_LOGIC;
signal blk00000003_sig00000152 : STD_LOGIC;
signal blk00000003_sig00000151 : STD_LOGIC;
signal blk00000003_sig00000150 : STD_LOGIC;
signal blk00000003_sig0000014f : STD_LOGIC;
signal blk00000003_sig0000014e : STD_LOGIC;
signal blk00000003_sig0000014d : STD_LOGIC;
signal blk00000003_sig0000014c : STD_LOGIC;
signal blk00000003_sig0000014b : STD_LOGIC;
signal blk00000003_sig0000014a : STD_LOGIC;
signal blk00000003_sig00000149 : STD_LOGIC;
signal blk00000003_sig00000148 : STD_LOGIC;
signal blk00000003_sig00000147 : STD_LOGIC;
signal blk00000003_sig00000146 : STD_LOGIC;
signal blk00000003_sig00000145 : STD_LOGIC;
signal blk00000003_sig00000144 : STD_LOGIC;
signal blk00000003_sig00000143 : STD_LOGIC;
signal blk00000003_sig00000142 : STD_LOGIC;
signal blk00000003_sig00000141 : STD_LOGIC;
signal blk00000003_sig00000140 : STD_LOGIC;
signal blk00000003_sig0000013f : STD_LOGIC;
signal blk00000003_sig0000013e : STD_LOGIC;
signal blk00000003_sig0000013d : STD_LOGIC;
signal blk00000003_sig0000013c : STD_LOGIC;
signal blk00000003_sig0000013b : STD_LOGIC;
signal blk00000003_sig0000013a : STD_LOGIC;
signal blk00000003_sig00000139 : STD_LOGIC;
signal blk00000003_sig00000138 : STD_LOGIC;
signal blk00000003_sig00000137 : STD_LOGIC;
signal blk00000003_sig00000136 : STD_LOGIC;
signal blk00000003_sig00000135 : STD_LOGIC;
signal blk00000003_sig00000134 : STD_LOGIC;
signal blk00000003_sig00000133 : STD_LOGIC;
signal blk00000003_sig00000132 : STD_LOGIC;
signal blk00000003_sig00000131 : STD_LOGIC;
signal blk00000003_sig00000130 : STD_LOGIC;
signal blk00000003_sig0000012f : STD_LOGIC;
signal blk00000003_sig0000012e : STD_LOGIC;
signal blk00000003_sig0000012d : STD_LOGIC;
signal blk00000003_sig0000012c : STD_LOGIC;
signal blk00000003_sig0000012b : STD_LOGIC;
signal blk00000003_sig0000012a : STD_LOGIC;
signal blk00000003_sig00000129 : STD_LOGIC;
signal blk00000003_sig00000128 : STD_LOGIC;
signal blk00000003_sig00000127 : STD_LOGIC;
signal blk00000003_sig00000126 : STD_LOGIC;
signal blk00000003_sig00000125 : STD_LOGIC;
signal blk00000003_sig00000124 : STD_LOGIC;
signal blk00000003_sig00000123 : STD_LOGIC;
signal blk00000003_sig00000122 : STD_LOGIC;
signal blk00000003_sig00000121 : STD_LOGIC;
signal blk00000003_sig00000120 : STD_LOGIC;
signal blk00000003_sig0000011f : STD_LOGIC;
signal blk00000003_sig0000011e : STD_LOGIC;
signal blk00000003_sig0000011d : STD_LOGIC;
signal blk00000003_sig0000011c : STD_LOGIC;
signal blk00000003_sig0000011b : STD_LOGIC;
signal blk00000003_sig0000011a : STD_LOGIC;
signal blk00000003_sig00000119 : STD_LOGIC;
signal blk00000003_sig00000118 : STD_LOGIC;
signal blk00000003_sig00000117 : STD_LOGIC;
signal blk00000003_sig00000116 : STD_LOGIC;
signal blk00000003_sig00000115 : STD_LOGIC;
signal blk00000003_sig00000114 : STD_LOGIC;
signal blk00000003_sig00000113 : STD_LOGIC;
signal blk00000003_sig00000112 : STD_LOGIC;
signal blk00000003_sig00000111 : STD_LOGIC;
signal blk00000003_sig00000110 : STD_LOGIC;
signal blk00000003_sig0000010f : STD_LOGIC;
signal blk00000003_sig0000010e : STD_LOGIC;
signal blk00000003_sig0000010d : STD_LOGIC;
signal blk00000003_sig0000010c : STD_LOGIC;
signal blk00000003_sig0000010b : STD_LOGIC;
signal blk00000003_sig0000010a : STD_LOGIC;
signal blk00000003_sig00000109 : STD_LOGIC;
signal blk00000003_sig00000108 : STD_LOGIC;
signal blk00000003_sig00000107 : STD_LOGIC;
signal blk00000003_sig00000106 : STD_LOGIC;
signal blk00000003_sig00000105 : STD_LOGIC;
signal blk00000003_sig00000104 : STD_LOGIC;
signal blk00000003_sig00000103 : STD_LOGIC;
signal blk00000003_sig00000102 : STD_LOGIC;
signal blk00000003_sig00000101 : STD_LOGIC;
signal blk00000003_sig00000100 : STD_LOGIC;
signal blk00000003_sig000000ff : STD_LOGIC;
signal blk00000003_sig000000fe : STD_LOGIC;
signal blk00000003_sig000000fd : STD_LOGIC;
signal blk00000003_sig000000fc : STD_LOGIC;
signal blk00000003_sig000000fb : STD_LOGIC;
signal blk00000003_sig000000fa : STD_LOGIC;
signal blk00000003_sig000000f9 : STD_LOGIC;
signal blk00000003_sig000000f8 : STD_LOGIC;
signal blk00000003_sig000000f7 : STD_LOGIC;
signal blk00000003_sig000000f6 : STD_LOGIC;
signal blk00000003_sig000000f5 : STD_LOGIC;
signal blk00000003_sig000000f4 : STD_LOGIC;
signal blk00000003_sig000000f3 : STD_LOGIC;
signal blk00000003_sig000000f2 : STD_LOGIC;
signal blk00000003_sig000000f1 : STD_LOGIC;
signal blk00000003_sig000000f0 : STD_LOGIC;
signal blk00000003_sig000000ef : STD_LOGIC;
signal blk00000003_sig000000ee : STD_LOGIC;
signal blk00000003_sig000000ed : STD_LOGIC;
signal blk00000003_sig000000ec : STD_LOGIC;
signal blk00000003_sig000000eb : STD_LOGIC;
signal blk00000003_sig000000ea : STD_LOGIC;
signal blk00000003_sig000000e9 : STD_LOGIC;
signal blk00000003_sig000000e8 : STD_LOGIC;
signal blk00000003_sig000000e7 : STD_LOGIC;
signal blk00000003_sig000000e6 : STD_LOGIC;
signal blk00000003_sig000000e5 : STD_LOGIC;
signal blk00000003_sig000000e4 : STD_LOGIC;
signal blk00000003_sig000000e3 : STD_LOGIC;
signal blk00000003_sig000000e2 : STD_LOGIC;
signal blk00000003_sig000000e1 : STD_LOGIC;
signal blk00000003_sig000000e0 : STD_LOGIC;
signal blk00000003_sig000000df : STD_LOGIC;
signal blk00000003_sig000000de : STD_LOGIC;
signal blk00000003_sig000000dd : STD_LOGIC;
signal blk00000003_sig000000dc : STD_LOGIC;
signal blk00000003_sig000000db : STD_LOGIC;
signal blk00000003_sig000000da : STD_LOGIC;
signal blk00000003_sig000000d9 : STD_LOGIC;
signal blk00000003_sig000000d8 : STD_LOGIC;
signal blk00000003_sig000000d7 : STD_LOGIC;
signal blk00000003_sig000000d6 : STD_LOGIC;
signal blk00000003_sig000000d5 : STD_LOGIC;
signal blk00000003_sig000000d4 : STD_LOGIC;
signal blk00000003_sig000000d3 : STD_LOGIC;
signal blk00000003_sig000000d2 : STD_LOGIC;
signal blk00000003_sig000000d1 : STD_LOGIC;
signal blk00000003_sig000000d0 : STD_LOGIC;
signal blk00000003_sig000000cf : STD_LOGIC;
signal blk00000003_sig000000ce : STD_LOGIC;
signal blk00000003_sig000000cd : STD_LOGIC;
signal blk00000003_sig000000cc : STD_LOGIC;
signal blk00000003_sig000000cb : STD_LOGIC;
signal blk00000003_sig000000ca : STD_LOGIC;
signal blk00000003_sig000000c9 : STD_LOGIC;
signal blk00000003_sig000000c8 : STD_LOGIC;
signal blk00000003_sig000000c7 : STD_LOGIC;
signal blk00000003_sig000000c6 : STD_LOGIC;
signal blk00000003_sig000000c5 : STD_LOGIC;
signal blk00000003_sig000000c4 : STD_LOGIC;
signal blk00000003_sig000000c3 : STD_LOGIC;
signal blk00000003_sig000000c2 : STD_LOGIC;
signal blk00000003_sig000000c1 : STD_LOGIC;
signal blk00000003_sig000000c0 : STD_LOGIC;
signal blk00000003_sig000000bf : STD_LOGIC;
signal blk00000003_sig000000be : STD_LOGIC;
signal blk00000003_sig000000bd : STD_LOGIC;
signal blk00000003_sig000000bc : STD_LOGIC;
signal blk00000003_sig000000bb : STD_LOGIC;
signal blk00000003_sig000000ba : STD_LOGIC;
signal blk00000003_sig000000b9 : STD_LOGIC;
signal blk00000003_sig000000b8 : STD_LOGIC;
signal blk00000003_sig000000b7 : STD_LOGIC;
signal blk00000003_sig000000b6 : STD_LOGIC;
signal blk00000003_sig000000b5 : STD_LOGIC;
signal blk00000003_sig000000b4 : STD_LOGIC;
signal blk00000003_sig000000b3 : STD_LOGIC;
signal blk00000003_sig000000b2 : STD_LOGIC;
signal blk00000003_sig000000b1 : STD_LOGIC;
signal blk00000003_sig000000b0 : STD_LOGIC;
signal blk00000003_sig000000af : STD_LOGIC;
signal blk00000003_sig000000ae : STD_LOGIC;
signal blk00000003_sig000000ad : STD_LOGIC;
signal blk00000003_sig000000ac : STD_LOGIC;
signal blk00000003_sig000000ab : STD_LOGIC;
signal blk00000003_sig000000aa : STD_LOGIC;
signal blk00000003_sig000000a9 : STD_LOGIC;
signal blk00000003_sig000000a8 : STD_LOGIC;
signal blk00000003_sig000000a7 : STD_LOGIC;
signal blk00000003_sig000000a6 : STD_LOGIC;
signal blk00000003_sig000000a5 : STD_LOGIC;
signal blk00000003_sig000000a4 : STD_LOGIC;
signal blk00000003_sig000000a3 : STD_LOGIC;
signal blk00000003_sig000000a2 : STD_LOGIC;
signal blk00000003_sig000000a1 : STD_LOGIC;
signal blk00000003_sig000000a0 : STD_LOGIC;
signal blk00000003_sig0000009f : STD_LOGIC;
signal blk00000003_sig0000009e : STD_LOGIC;
signal blk00000003_sig0000009d : STD_LOGIC;
signal blk00000003_sig0000009c : STD_LOGIC;
signal blk00000003_sig0000009b : STD_LOGIC;
signal blk00000003_sig0000009a : STD_LOGIC;
signal blk00000003_sig00000099 : STD_LOGIC;
signal blk00000003_sig00000098 : STD_LOGIC;
signal blk00000003_sig00000097 : STD_LOGIC;
signal blk00000003_sig00000096 : STD_LOGIC;
signal blk00000003_sig00000095 : STD_LOGIC;
signal blk00000003_sig00000094 : STD_LOGIC;
signal blk00000003_sig00000093 : STD_LOGIC;
signal blk00000003_sig00000092 : STD_LOGIC;
signal blk00000003_sig00000091 : STD_LOGIC;
signal blk00000003_sig00000090 : STD_LOGIC;
signal blk00000003_sig0000008f : STD_LOGIC;
signal blk00000003_sig0000008e : STD_LOGIC;
signal blk00000003_sig0000008d : STD_LOGIC;
signal blk00000003_sig0000008c : STD_LOGIC;
signal blk00000003_sig0000008b : STD_LOGIC;
signal blk00000003_sig0000008a : STD_LOGIC;
signal blk00000003_sig00000089 : STD_LOGIC;
signal blk00000003_sig00000088 : STD_LOGIC;
signal blk00000003_sig00000087 : STD_LOGIC;
signal blk00000003_sig00000086 : STD_LOGIC;
signal blk00000003_sig00000085 : STD_LOGIC;
signal blk00000003_sig00000084 : STD_LOGIC;
signal blk00000003_sig00000083 : STD_LOGIC;
signal blk00000003_sig00000082 : STD_LOGIC;
signal blk00000003_sig00000081 : STD_LOGIC;
signal blk00000003_sig00000080 : STD_LOGIC;
signal blk00000003_sig0000007f : STD_LOGIC;
signal blk00000003_sig0000007e : STD_LOGIC;
signal blk00000003_sig0000007d : STD_LOGIC;
signal blk00000003_sig0000007c : STD_LOGIC;
signal blk00000003_sig0000007b : STD_LOGIC;
signal blk00000003_sig0000007a : STD_LOGIC;
signal blk00000003_sig00000079 : STD_LOGIC;
signal blk00000003_sig00000078 : STD_LOGIC;
signal blk00000003_sig00000077 : STD_LOGIC;
signal blk00000003_sig00000076 : STD_LOGIC;
signal blk00000003_sig00000075 : STD_LOGIC;
signal blk00000003_sig00000074 : STD_LOGIC;
signal blk00000003_sig00000073 : STD_LOGIC;
signal blk00000003_sig00000072 : STD_LOGIC;
signal blk00000003_sig00000071 : STD_LOGIC;
signal blk00000003_sig00000070 : STD_LOGIC;
signal blk00000003_sig0000006f : STD_LOGIC;
signal blk00000003_sig0000006e : STD_LOGIC;
signal blk00000003_sig0000006d : STD_LOGIC;
signal blk00000003_sig0000006c : STD_LOGIC;
signal blk00000003_sig0000006b : STD_LOGIC;
signal blk00000003_sig0000006a : STD_LOGIC;
signal blk00000003_sig00000069 : STD_LOGIC;
signal blk00000003_sig00000068 : STD_LOGIC;
signal blk00000003_sig00000067 : STD_LOGIC;
signal blk00000003_sig00000066 : STD_LOGIC;
signal blk00000003_sig00000065 : STD_LOGIC;
signal blk00000003_sig00000064 : STD_LOGIC;
signal blk00000003_sig00000062 : STD_LOGIC;
signal NLW_blk00000001_P_UNCONNECTED : STD_LOGIC;
signal NLW_blk00000002_G_UNCONNECTED : STD_LOGIC;
signal dividend_0 : STD_LOGIC_VECTOR ( 23 downto 0 );
signal divisor_1 : STD_LOGIC_VECTOR ( 23 downto 0 );
signal quotient_2 : STD_LOGIC_VECTOR ( 23 downto 0 );
signal fractional_3 : STD_LOGIC_VECTOR ( 23 downto 0 );
begin
dividend_0(23) <= dividend(23);
dividend_0(22) <= dividend(22);
dividend_0(21) <= dividend(21);
dividend_0(20) <= dividend(20);
dividend_0(19) <= dividend(19);
dividend_0(18) <= dividend(18);
dividend_0(17) <= dividend(17);
dividend_0(16) <= dividend(16);
dividend_0(15) <= dividend(15);
dividend_0(14) <= dividend(14);
dividend_0(13) <= dividend(13);
dividend_0(12) <= dividend(12);
dividend_0(11) <= dividend(11);
dividend_0(10) <= dividend(10);
dividend_0(9) <= dividend(9);
dividend_0(8) <= dividend(8);
dividend_0(7) <= dividend(7);
dividend_0(6) <= dividend(6);
dividend_0(5) <= dividend(5);
dividend_0(4) <= dividend(4);
dividend_0(3) <= dividend(3);
dividend_0(2) <= dividend(2);
dividend_0(1) <= dividend(1);
dividend_0(0) <= dividend(0);
quotient(23) <= quotient_2(23);
quotient(22) <= quotient_2(22);
quotient(21) <= quotient_2(21);
quotient(20) <= quotient_2(20);
quotient(19) <= quotient_2(19);
quotient(18) <= quotient_2(18);
quotient(17) <= quotient_2(17);
quotient(16) <= quotient_2(16);
quotient(15) <= quotient_2(15);
quotient(14) <= quotient_2(14);
quotient(13) <= quotient_2(13);
quotient(12) <= quotient_2(12);
quotient(11) <= quotient_2(11);
quotient(10) <= quotient_2(10);
quotient(9) <= quotient_2(9);
quotient(8) <= quotient_2(8);
quotient(7) <= quotient_2(7);
quotient(6) <= quotient_2(6);
quotient(5) <= quotient_2(5);
quotient(4) <= quotient_2(4);
quotient(3) <= quotient_2(3);
quotient(2) <= quotient_2(2);
quotient(1) <= quotient_2(1);
quotient(0) <= quotient_2(0);
divisor_1(23) <= divisor(23);
divisor_1(22) <= divisor(22);
divisor_1(21) <= divisor(21);
divisor_1(20) <= divisor(20);
divisor_1(19) <= divisor(19);
divisor_1(18) <= divisor(18);
divisor_1(17) <= divisor(17);
divisor_1(16) <= divisor(16);
divisor_1(15) <= divisor(15);
divisor_1(14) <= divisor(14);
divisor_1(13) <= divisor(13);
divisor_1(12) <= divisor(12);
divisor_1(11) <= divisor(11);
divisor_1(10) <= divisor(10);
divisor_1(9) <= divisor(9);
divisor_1(8) <= divisor(8);
divisor_1(7) <= divisor(7);
divisor_1(6) <= divisor(6);
divisor_1(5) <= divisor(5);
divisor_1(4) <= divisor(4);
divisor_1(3) <= divisor(3);
divisor_1(2) <= divisor(2);
divisor_1(1) <= divisor(1);
divisor_1(0) <= divisor(0);
rfd <= NlwRenamedSig_OI_rfd;
fractional(23) <= fractional_3(23);
fractional(22) <= fractional_3(22);
fractional(21) <= fractional_3(21);
fractional(20) <= fractional_3(20);
fractional(19) <= fractional_3(19);
fractional(18) <= fractional_3(18);
fractional(17) <= fractional_3(17);
fractional(16) <= fractional_3(16);
fractional(15) <= fractional_3(15);
fractional(14) <= fractional_3(14);
fractional(13) <= fractional_3(13);
fractional(12) <= fractional_3(12);
fractional(11) <= fractional_3(11);
fractional(10) <= fractional_3(10);
fractional(9) <= fractional_3(9);
fractional(8) <= fractional_3(8);
fractional(7) <= fractional_3(7);
fractional(6) <= fractional_3(6);
fractional(5) <= fractional_3(5);
fractional(4) <= fractional_3(4);
fractional(3) <= fractional_3(3);
fractional(2) <= fractional_3(2);
fractional(1) <= fractional_3(1);
fractional(0) <= fractional_3(0);
blk00000001 : VCC
port map (
P => NLW_blk00000001_P_UNCONNECTED
);
blk00000002 : GND
port map (
G => NLW_blk00000002_G_UNCONNECTED
);
blk00000003_blk00000edb : INV
port map (
I => blk00000003_sig00000328,
O => blk00000003_sig0000035f
);
blk00000003_blk00000eda : INV
port map (
I => blk00000003_sig00000329,
O => blk00000003_sig00000362
);
blk00000003_blk00000ed9 : INV
port map (
I => blk00000003_sig0000032a,
O => blk00000003_sig00000365
);
blk00000003_blk00000ed8 : INV
port map (
I => blk00000003_sig0000032b,
O => blk00000003_sig00000368
);
blk00000003_blk00000ed7 : INV
port map (
I => blk00000003_sig0000032c,
O => blk00000003_sig0000036b
);
blk00000003_blk00000ed6 : INV
port map (
I => blk00000003_sig0000032d,
O => blk00000003_sig0000036e
);
blk00000003_blk00000ed5 : INV
port map (
I => blk00000003_sig0000032e,
O => blk00000003_sig00000371
);
blk00000003_blk00000ed4 : INV
port map (
I => blk00000003_sig0000032f,
O => blk00000003_sig00000374
);
blk00000003_blk00000ed3 : INV
port map (
I => blk00000003_sig0000031a,
O => blk00000003_sig00000335
);
blk00000003_blk00000ed2 : INV
port map (
I => blk00000003_sig0000031b,
O => blk00000003_sig00000338
);
blk00000003_blk00000ed1 : INV
port map (
I => blk00000003_sig0000031c,
O => blk00000003_sig0000033b
);
blk00000003_blk00000ed0 : INV
port map (
I => blk00000003_sig0000031d,
O => blk00000003_sig0000033e
);
blk00000003_blk00000ecf : INV
port map (
I => blk00000003_sig00000330,
O => blk00000003_sig00000377
);
blk00000003_blk00000ece : INV
port map (
I => blk00000003_sig0000031e,
O => blk00000003_sig00000341
);
blk00000003_blk00000ecd : INV
port map (
I => blk00000003_sig0000031f,
O => blk00000003_sig00000344
);
blk00000003_blk00000ecc : INV
port map (
I => blk00000003_sig00000320,
O => blk00000003_sig00000347
);
blk00000003_blk00000ecb : INV
port map (
I => blk00000003_sig00000321,
O => blk00000003_sig0000034a
);
blk00000003_blk00000eca : INV
port map (
I => blk00000003_sig00000322,
O => blk00000003_sig0000034d
);
blk00000003_blk00000ec9 : INV
port map (
I => blk00000003_sig00000323,
O => blk00000003_sig00000350
);
blk00000003_blk00000ec8 : INV
port map (
I => blk00000003_sig00000324,
O => blk00000003_sig00000353
);
blk00000003_blk00000ec7 : INV
port map (
I => blk00000003_sig00000325,
O => blk00000003_sig00000356
);
blk00000003_blk00000ec6 : INV
port map (
I => blk00000003_sig00000326,
O => blk00000003_sig00000359
);
blk00000003_blk00000ec5 : INV
port map (
I => blk00000003_sig00000327,
O => blk00000003_sig0000035c
);
blk00000003_blk00000ec4 : INV
port map (
I => blk00000003_sig00000e8b,
O => blk00000003_sig000000aa
);
blk00000003_blk00000ec3 : INV
port map (
I => blk00000003_sig00000e8c,
O => blk00000003_sig000000ab
);
blk00000003_blk00000ec2 : INV
port map (
I => blk00000003_sig00000e8d,
O => blk00000003_sig000000ac
);
blk00000003_blk00000ec1 : INV
port map (
I => blk00000003_sig00000e8e,
O => blk00000003_sig000000ad
);
blk00000003_blk00000ec0 : INV
port map (
I => blk00000003_sig00000e8f,
O => blk00000003_sig000000ae
);
blk00000003_blk00000ebf : INV
port map (
I => blk00000003_sig00000e90,
O => blk00000003_sig000000af
);
blk00000003_blk00000ebe : INV
port map (
I => blk00000003_sig00000e91,
O => blk00000003_sig000000b0
);
blk00000003_blk00000ebd : INV
port map (
I => blk00000003_sig00000e92,
O => blk00000003_sig000000b1
);
blk00000003_blk00000ebc : INV
port map (
I => blk00000003_sig00000e93,
O => blk00000003_sig000000b2
);
blk00000003_blk00000ebb : INV
port map (
I => blk00000003_sig00000e94,
O => blk00000003_sig000000b3
);
blk00000003_blk00000eba : INV
port map (
I => blk00000003_sig00000e95,
O => blk00000003_sig000000b4
);
blk00000003_blk00000eb9 : INV
port map (
I => blk00000003_sig00000e96,
O => blk00000003_sig000000b5
);
blk00000003_blk00000eb8 : INV
port map (
I => blk00000003_sig00000e97,
O => blk00000003_sig000000b6
);
blk00000003_blk00000eb7 : INV
port map (
I => blk00000003_sig00000e98,
O => blk00000003_sig000000b7
);
blk00000003_blk00000eb6 : INV
port map (
I => blk00000003_sig00000e99,
O => blk00000003_sig000000b8
);
blk00000003_blk00000eb5 : INV
port map (
I => blk00000003_sig00000e9a,
O => blk00000003_sig000000b9
);
blk00000003_blk00000eb4 : INV
port map (
I => blk00000003_sig00000e9b,
O => blk00000003_sig000000ba
);
blk00000003_blk00000eb3 : INV
port map (
I => blk00000003_sig00000e9c,
O => blk00000003_sig000000bb
);
blk00000003_blk00000eb2 : INV
port map (
I => blk00000003_sig00000e9d,
O => blk00000003_sig000000bc
);
blk00000003_blk00000eb1 : INV
port map (
I => blk00000003_sig00000e9e,
O => blk00000003_sig000000bd
);
blk00000003_blk00000eb0 : INV
port map (
I => blk00000003_sig00000e9f,
O => blk00000003_sig000000be
);
blk00000003_blk00000eaf : INV
port map (
I => blk00000003_sig00000ea0,
O => blk00000003_sig000000bf
);
blk00000003_blk00000eae : INV
port map (
I => blk00000003_sig00000ea1,
O => blk00000003_sig000000c0
);
blk00000003_blk00000ead : INV
port map (
I => blk00000003_sig00000cb9,
O => blk00000003_sig00000c9c
);
blk00000003_blk00000eac : INV
port map (
I => blk00000003_sig00000cba,
O => blk00000003_sig00000c37
);
blk00000003_blk00000eab : INV
port map (
I => blk00000003_sig00000cbb,
O => blk00000003_sig00000bd2
);
blk00000003_blk00000eaa : INV
port map (
I => blk00000003_sig00000cbc,
O => blk00000003_sig00000b6d
);
blk00000003_blk00000ea9 : INV
port map (
I => blk00000003_sig00000cbd,
O => blk00000003_sig00000b08
);
blk00000003_blk00000ea8 : INV
port map (
I => blk00000003_sig00000cbe,
O => blk00000003_sig00000aa3
);
blk00000003_blk00000ea7 : INV
port map (
I => blk00000003_sig00000cbf,
O => blk00000003_sig00000a3e
);
blk00000003_blk00000ea6 : INV
port map (
I => blk00000003_sig00000cc0,
O => blk00000003_sig000009d8
);
blk00000003_blk00000ea5 : INV
port map (
I => blk00000003_sig00000cc1,
O => blk00000003_sig00000972
);
blk00000003_blk00000ea4 : INV
port map (
I => blk00000003_sig00000cc2,
O => blk00000003_sig0000090c
);
blk00000003_blk00000ea3 : INV
port map (
I => blk00000003_sig00000cc3,
O => blk00000003_sig000008a6
);
blk00000003_blk00000ea2 : INV
port map (
I => blk00000003_sig00000cc4,
O => blk00000003_sig00000840
);
blk00000003_blk00000ea1 : INV
port map (
I => blk00000003_sig00000cc5,
O => blk00000003_sig000007da
);
blk00000003_blk00000ea0 : INV
port map (
I => blk00000003_sig00000cc6,
O => blk00000003_sig00000774
);
blk00000003_blk00000e9f : INV
port map (
I => blk00000003_sig00000cc7,
O => blk00000003_sig0000070e
);
blk00000003_blk00000e9e : INV
port map (
I => blk00000003_sig00000cc8,
O => blk00000003_sig000006a8
);
blk00000003_blk00000e9d : INV
port map (
I => blk00000003_sig00000086,
O => blk00000003_sig00000642
);
blk00000003_blk00000e9c : INV
port map (
I => blk00000003_sig00000094,
O => blk00000003_sig000005dc
);
blk00000003_blk00000e9b : INV
port map (
I => blk00000003_sig0000009a,
O => blk00000003_sig00000576
);
blk00000003_blk00000e9a : INV
port map (
I => blk00000003_sig0000009f,
O => blk00000003_sig00000510
);
blk00000003_blk00000e99 : INV
port map (
I => blk00000003_sig00000f09,
O => blk00000003_sig000004aa
);
blk00000003_blk00000e98 : INV
port map (
I => blk00000003_sig00000f08,
O => blk00000003_sig00000444
);
blk00000003_blk00000e97 : INV
port map (
I => blk00000003_sig00000f07,
O => blk00000003_sig000003de
);
blk00000003_blk00000e96 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig000003e5,
Q => blk00000003_sig00000f09
);
blk00000003_blk00000e95 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig0000037f,
Q => blk00000003_sig00000f08
);
blk00000003_blk00000e94 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000333,
Q => blk00000003_sig00000f07
);
blk00000003_blk00000e93 : LUT3
generic map(
INIT => X"6A"
)
port map (
I0 => blk00000003_sig00000caf,
I1 => blk00000003_sig000000f7,
I2 => blk00000003_sig00000ca0,
O => blk00000003_sig00000edc
);
blk00000003_blk00000e92 : LUT3
generic map(
INIT => X"6A"
)
port map (
I0 => blk00000003_sig00000cb0,
I1 => blk00000003_sig000000f9,
I2 => blk00000003_sig00000ca0,
O => blk00000003_sig00000ee0
);
blk00000003_blk00000e91 : LUT3
generic map(
INIT => X"6A"
)
port map (
I0 => blk00000003_sig00000cb1,
I1 => blk00000003_sig000000fb,
I2 => blk00000003_sig00000ca0,
O => blk00000003_sig00000ee4
);
blk00000003_blk00000e90 : LUT3
generic map(
INIT => X"6A"
)
port map (
I0 => blk00000003_sig00000cb2,
I1 => blk00000003_sig000000fd,
I2 => blk00000003_sig00000ca0,
O => blk00000003_sig00000ee8
);
blk00000003_blk00000e8f : LUT3
generic map(
INIT => X"6A"
)
port map (
I0 => blk00000003_sig00000cb3,
I1 => blk00000003_sig000000ff,
I2 => blk00000003_sig00000ca0,
O => blk00000003_sig00000eec
);
blk00000003_blk00000e8e : LUT3
generic map(
INIT => X"6A"
)
port map (
I0 => blk00000003_sig00000cb4,
I1 => blk00000003_sig00000101,
I2 => blk00000003_sig00000ca0,
O => blk00000003_sig00000ef0
);
blk00000003_blk00000e8d : LUT3
generic map(
INIT => X"6A"
)
port map (
I0 => blk00000003_sig00000cb5,
I1 => blk00000003_sig00000103,
I2 => blk00000003_sig00000ca0,
O => blk00000003_sig00000ef4
);
blk00000003_blk00000e8c : LUT3
generic map(
INIT => X"6A"
)
port map (
I0 => blk00000003_sig00000cb6,
I1 => blk00000003_sig00000105,
I2 => blk00000003_sig00000ca0,
O => blk00000003_sig00000ef8
);
blk00000003_blk00000e8b : LUT3
generic map(
INIT => X"6A"
)
port map (
I0 => blk00000003_sig00000ca1,
I1 => blk00000003_sig000000db,
I2 => blk00000003_sig00000ca0,
O => blk00000003_sig00000ea3
);
blk00000003_blk00000e8a : LUT3
generic map(
INIT => X"6A"
)
port map (
I0 => blk00000003_sig00000ca2,
I1 => blk00000003_sig000000dd,
I2 => blk00000003_sig00000ca0,
O => blk00000003_sig00000ea8
);
blk00000003_blk00000e89 : LUT3
generic map(
INIT => X"6A"
)
port map (
I0 => blk00000003_sig00000ca3,
I1 => blk00000003_sig000000df,
I2 => blk00000003_sig00000ca0,
O => blk00000003_sig00000eac
);
blk00000003_blk00000e88 : LUT3
generic map(
INIT => X"6A"
)
port map (
I0 => blk00000003_sig00000ca4,
I1 => blk00000003_sig000000e1,
I2 => blk00000003_sig00000ca0,
O => blk00000003_sig00000eb0
);
blk00000003_blk00000e87 : LUT3
generic map(
INIT => X"6A"
)
port map (
I0 => blk00000003_sig00000cb7,
I1 => blk00000003_sig00000107,
I2 => blk00000003_sig00000ca0,
O => blk00000003_sig00000efc
);
blk00000003_blk00000e86 : LUT3
generic map(
INIT => X"6A"
)
port map (
I0 => blk00000003_sig00000ca5,
I1 => blk00000003_sig000000e3,
I2 => blk00000003_sig00000ca0,
O => blk00000003_sig00000eb4
);
blk00000003_blk00000e85 : LUT3
generic map(
INIT => X"6A"
)
port map (
I0 => blk00000003_sig00000ca6,
I1 => blk00000003_sig000000e5,
I2 => blk00000003_sig00000ca0,
O => blk00000003_sig00000eb8
);
blk00000003_blk00000e84 : LUT3
generic map(
INIT => X"6A"
)
port map (
I0 => blk00000003_sig00000ca7,
I1 => blk00000003_sig000000e7,
I2 => blk00000003_sig00000ca0,
O => blk00000003_sig00000ebc
);
blk00000003_blk00000e83 : LUT3
generic map(
INIT => X"6A"
)
port map (
I0 => blk00000003_sig00000ca8,
I1 => blk00000003_sig000000e9,
I2 => blk00000003_sig00000ca0,
O => blk00000003_sig00000ec0
);
blk00000003_blk00000e82 : LUT3
generic map(
INIT => X"6A"
)
port map (
I0 => blk00000003_sig00000ca9,
I1 => blk00000003_sig000000eb,
I2 => blk00000003_sig00000ca0,
O => blk00000003_sig00000ec4
);
blk00000003_blk00000e81 : LUT3
generic map(
INIT => X"6A"
)
port map (
I0 => blk00000003_sig00000caa,
I1 => blk00000003_sig000000ed,
I2 => blk00000003_sig00000ca0,
O => blk00000003_sig00000ec8
);
blk00000003_blk00000e80 : LUT3
generic map(
INIT => X"6A"
)
port map (
I0 => blk00000003_sig00000cab,
I1 => blk00000003_sig000000ef,
I2 => blk00000003_sig00000ca0,
O => blk00000003_sig00000ecc
);
blk00000003_blk00000e7f : LUT3
generic map(
INIT => X"6A"
)
port map (
I0 => blk00000003_sig00000cac,
I1 => blk00000003_sig000000f1,
I2 => blk00000003_sig00000ca0,
O => blk00000003_sig00000ed0
);
blk00000003_blk00000e7e : LUT3
generic map(
INIT => X"6A"
)
port map (
I0 => blk00000003_sig00000cad,
I1 => blk00000003_sig000000f3,
I2 => blk00000003_sig00000ca0,
O => blk00000003_sig00000ed4
);
blk00000003_blk00000e7d : LUT3
generic map(
INIT => X"6A"
)
port map (
I0 => blk00000003_sig00000cae,
I1 => blk00000003_sig000000f5,
I2 => blk00000003_sig00000ca0,
O => blk00000003_sig00000ed8
);
blk00000003_blk00000e7c : LUT3
generic map(
INIT => X"6A"
)
port map (
I0 => blk00000003_sig00000cb8,
I1 => blk00000003_sig00000109,
I2 => blk00000003_sig00000ca0,
O => blk00000003_sig00000f02
);
blk00000003_blk00000e7b : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig00000c91,
I1 => blk00000003_sig000000f6,
I2 => blk00000003_sig00000cb9,
O => blk00000003_sig00000c69
);
blk00000003_blk00000e7a : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig00000c92,
I1 => blk00000003_sig000000f8,
I2 => blk00000003_sig00000cb9,
O => blk00000003_sig00000c6c
);
blk00000003_blk00000e79 : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig00000c93,
I1 => blk00000003_sig000000fa,
I2 => blk00000003_sig00000cb9,
O => blk00000003_sig00000c6f
);
blk00000003_blk00000e78 : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig00000c94,
I1 => blk00000003_sig000000fc,
I2 => blk00000003_sig00000cb9,
O => blk00000003_sig00000c72
);
blk00000003_blk00000e77 : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig00000c95,
I1 => blk00000003_sig000000fe,
I2 => blk00000003_sig00000cb9,
O => blk00000003_sig00000c75
);
blk00000003_blk00000e76 : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig00000c96,
I1 => blk00000003_sig00000100,
I2 => blk00000003_sig00000cb9,
O => blk00000003_sig00000c78
);
blk00000003_blk00000e75 : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig00000c97,
I1 => blk00000003_sig00000102,
I2 => blk00000003_sig00000cb9,
O => blk00000003_sig00000c7b
);
blk00000003_blk00000e74 : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig00000c98,
I1 => blk00000003_sig00000104,
I2 => blk00000003_sig00000cb9,
O => blk00000003_sig00000c7e
);
blk00000003_blk00000e73 : LUT2
generic map(
INIT => X"9"
)
port map (
I0 => blk00000003_sig00000c9a,
I1 => blk00000003_sig00000cb9,
O => blk00000003_sig00000c3c
);
blk00000003_blk00000e72 : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig00000c83,
I1 => blk00000003_sig000000da,
I2 => blk00000003_sig00000cb9,
O => blk00000003_sig00000c3f
);
blk00000003_blk00000e71 : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig00000c84,
I1 => blk00000003_sig000000dc,
I2 => blk00000003_sig00000cb9,
O => blk00000003_sig00000c42
);
blk00000003_blk00000e70 : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig00000c85,
I1 => blk00000003_sig000000de,
I2 => blk00000003_sig00000cb9,
O => blk00000003_sig00000c45
);
blk00000003_blk00000e6f : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig00000c86,
I1 => blk00000003_sig000000e0,
I2 => blk00000003_sig00000cb9,
O => blk00000003_sig00000c48
);
blk00000003_blk00000e6e : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig00000c99,
I1 => blk00000003_sig00000106,
I2 => blk00000003_sig00000cb9,
O => blk00000003_sig00000c81
);
blk00000003_blk00000e6d : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig00000c87,
I1 => blk00000003_sig000000e2,
I2 => blk00000003_sig00000cb9,
O => blk00000003_sig00000c4b
);
blk00000003_blk00000e6c : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig00000c88,
I1 => blk00000003_sig000000e4,
I2 => blk00000003_sig00000cb9,
O => blk00000003_sig00000c4e
);
blk00000003_blk00000e6b : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig00000c89,
I1 => blk00000003_sig000000e6,
I2 => blk00000003_sig00000cb9,
O => blk00000003_sig00000c51
);
blk00000003_blk00000e6a : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig00000c8a,
I1 => blk00000003_sig000000e8,
I2 => blk00000003_sig00000cb9,
O => blk00000003_sig00000c54
);
blk00000003_blk00000e69 : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig00000c8b,
I1 => blk00000003_sig000000ea,
I2 => blk00000003_sig00000cb9,
O => blk00000003_sig00000c57
);
blk00000003_blk00000e68 : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig00000c8c,
I1 => blk00000003_sig000000ec,
I2 => blk00000003_sig00000cb9,
O => blk00000003_sig00000c5a
);
blk00000003_blk00000e67 : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig00000c8d,
I1 => blk00000003_sig000000ee,
I2 => blk00000003_sig00000cb9,
O => blk00000003_sig00000c5d
);
blk00000003_blk00000e66 : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig00000c8e,
I1 => blk00000003_sig000000f0,
I2 => blk00000003_sig00000cb9,
O => blk00000003_sig00000c60
);
blk00000003_blk00000e65 : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig00000c8f,
I1 => blk00000003_sig000000f2,
I2 => blk00000003_sig00000cb9,
O => blk00000003_sig00000c63
);
blk00000003_blk00000e64 : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig00000c90,
I1 => blk00000003_sig000000f4,
I2 => blk00000003_sig00000cb9,
O => blk00000003_sig00000c66
);
blk00000003_blk00000e63 : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig000000a9,
I1 => blk00000003_sig00000108,
I2 => blk00000003_sig00000cb9,
O => blk00000003_sig00000c9d
);
blk00000003_blk00000e62 : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig00000c2c,
I1 => blk00000003_sig00000118,
I2 => blk00000003_sig00000cba,
O => blk00000003_sig00000c04
);
blk00000003_blk00000e61 : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig00000c2d,
I1 => blk00000003_sig00000119,
I2 => blk00000003_sig00000cba,
O => blk00000003_sig00000c07
);
blk00000003_blk00000e60 : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig00000c2e,
I1 => blk00000003_sig0000011a,
I2 => blk00000003_sig00000cba,
O => blk00000003_sig00000c0a
);
blk00000003_blk00000e5f : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig00000c2f,
I1 => blk00000003_sig0000011b,
I2 => blk00000003_sig00000cba,
O => blk00000003_sig00000c0d
);
blk00000003_blk00000e5e : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig00000c30,
I1 => blk00000003_sig0000011c,
I2 => blk00000003_sig00000cba,
O => blk00000003_sig00000c10
);
blk00000003_blk00000e5d : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig00000c31,
I1 => blk00000003_sig0000011d,
I2 => blk00000003_sig00000cba,
O => blk00000003_sig00000c13
);
blk00000003_blk00000e5c : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig00000c32,
I1 => blk00000003_sig0000011e,
I2 => blk00000003_sig00000cba,
O => blk00000003_sig00000c16
);
blk00000003_blk00000e5b : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig00000c33,
I1 => blk00000003_sig0000011f,
I2 => blk00000003_sig00000cba,
O => blk00000003_sig00000c19
);
blk00000003_blk00000e5a : LUT2
generic map(
INIT => X"9"
)
port map (
I0 => blk00000003_sig00000c35,
I1 => blk00000003_sig00000cba,
O => blk00000003_sig00000bd7
);
blk00000003_blk00000e59 : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig00000c1e,
I1 => blk00000003_sig0000010a,
I2 => blk00000003_sig00000cba,
O => blk00000003_sig00000bda
);
blk00000003_blk00000e58 : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig00000c1f,
I1 => blk00000003_sig0000010b,
I2 => blk00000003_sig00000cba,
O => blk00000003_sig00000bdd
);
blk00000003_blk00000e57 : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig00000c20,
I1 => blk00000003_sig0000010c,
I2 => blk00000003_sig00000cba,
O => blk00000003_sig00000be0
);
blk00000003_blk00000e56 : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig00000c21,
I1 => blk00000003_sig0000010d,
I2 => blk00000003_sig00000cba,
O => blk00000003_sig00000be3
);
blk00000003_blk00000e55 : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig00000c34,
I1 => blk00000003_sig00000120,
I2 => blk00000003_sig00000cba,
O => blk00000003_sig00000c1c
);
blk00000003_blk00000e54 : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig00000c22,
I1 => blk00000003_sig0000010e,
I2 => blk00000003_sig00000cba,
O => blk00000003_sig00000be6
);
blk00000003_blk00000e53 : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig00000c23,
I1 => blk00000003_sig0000010f,
I2 => blk00000003_sig00000cba,
O => blk00000003_sig00000be9
);
blk00000003_blk00000e52 : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig00000c24,
I1 => blk00000003_sig00000110,
I2 => blk00000003_sig00000cba,
O => blk00000003_sig00000bec
);
blk00000003_blk00000e51 : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig00000c25,
I1 => blk00000003_sig00000111,
I2 => blk00000003_sig00000cba,
O => blk00000003_sig00000bef
);
blk00000003_blk00000e50 : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig00000c26,
I1 => blk00000003_sig00000112,
I2 => blk00000003_sig00000cba,
O => blk00000003_sig00000bf2
);
blk00000003_blk00000e4f : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig00000c27,
I1 => blk00000003_sig00000113,
I2 => blk00000003_sig00000cba,
O => blk00000003_sig00000bf5
);
blk00000003_blk00000e4e : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig00000c28,
I1 => blk00000003_sig00000114,
I2 => blk00000003_sig00000cba,
O => blk00000003_sig00000bf8
);
blk00000003_blk00000e4d : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig00000c29,
I1 => blk00000003_sig00000115,
I2 => blk00000003_sig00000cba,
O => blk00000003_sig00000bfb
);
blk00000003_blk00000e4c : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig00000c2a,
I1 => blk00000003_sig00000116,
I2 => blk00000003_sig00000cba,
O => blk00000003_sig00000bfe
);
blk00000003_blk00000e4b : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig00000c2b,
I1 => blk00000003_sig00000117,
I2 => blk00000003_sig00000cba,
O => blk00000003_sig00000c01
);
blk00000003_blk00000e4a : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig00000067,
I1 => blk00000003_sig00000121,
I2 => blk00000003_sig00000cba,
O => blk00000003_sig00000c38
);
blk00000003_blk00000e49 : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig00000bc7,
I1 => blk00000003_sig00000130,
I2 => blk00000003_sig00000cbb,
O => blk00000003_sig00000b9f
);
blk00000003_blk00000e48 : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig00000bc8,
I1 => blk00000003_sig00000131,
I2 => blk00000003_sig00000cbb,
O => blk00000003_sig00000ba2
);
blk00000003_blk00000e47 : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig00000bc9,
I1 => blk00000003_sig00000132,
I2 => blk00000003_sig00000cbb,
O => blk00000003_sig00000ba5
);
blk00000003_blk00000e46 : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig00000bca,
I1 => blk00000003_sig00000133,
I2 => blk00000003_sig00000cbb,
O => blk00000003_sig00000ba8
);
blk00000003_blk00000e45 : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig00000bcb,
I1 => blk00000003_sig00000134,
I2 => blk00000003_sig00000cbb,
O => blk00000003_sig00000bab
);
blk00000003_blk00000e44 : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig00000bcc,
I1 => blk00000003_sig00000135,
I2 => blk00000003_sig00000cbb,
O => blk00000003_sig00000bae
);
blk00000003_blk00000e43 : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig00000bcd,
I1 => blk00000003_sig00000136,
I2 => blk00000003_sig00000cbb,
O => blk00000003_sig00000bb1
);
blk00000003_blk00000e42 : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig00000bce,
I1 => blk00000003_sig00000137,
I2 => blk00000003_sig00000cbb,
O => blk00000003_sig00000bb4
);
blk00000003_blk00000e41 : LUT2
generic map(
INIT => X"9"
)
port map (
I0 => blk00000003_sig00000bd0,
I1 => blk00000003_sig00000cbb,
O => blk00000003_sig00000b72
);
blk00000003_blk00000e40 : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig00000bb9,
I1 => blk00000003_sig00000122,
I2 => blk00000003_sig00000cbb,
O => blk00000003_sig00000b75
);
blk00000003_blk00000e3f : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig00000bba,
I1 => blk00000003_sig00000123,
I2 => blk00000003_sig00000cbb,
O => blk00000003_sig00000b78
);
blk00000003_blk00000e3e : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig00000bbb,
I1 => blk00000003_sig00000124,
I2 => blk00000003_sig00000cbb,
O => blk00000003_sig00000b7b
);
blk00000003_blk00000e3d : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig00000bbc,
I1 => blk00000003_sig00000125,
I2 => blk00000003_sig00000cbb,
O => blk00000003_sig00000b7e
);
blk00000003_blk00000e3c : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig00000bcf,
I1 => blk00000003_sig00000138,
I2 => blk00000003_sig00000cbb,
O => blk00000003_sig00000bb7
);
blk00000003_blk00000e3b : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig00000bbd,
I1 => blk00000003_sig00000126,
I2 => blk00000003_sig00000cbb,
O => blk00000003_sig00000b81
);
blk00000003_blk00000e3a : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig00000bbe,
I1 => blk00000003_sig00000127,
I2 => blk00000003_sig00000cbb,
O => blk00000003_sig00000b84
);
blk00000003_blk00000e39 : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig00000bbf,
I1 => blk00000003_sig00000128,
I2 => blk00000003_sig00000cbb,
O => blk00000003_sig00000b87
);
blk00000003_blk00000e38 : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig00000bc0,
I1 => blk00000003_sig00000129,
I2 => blk00000003_sig00000cbb,
O => blk00000003_sig00000b8a
);
blk00000003_blk00000e37 : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig00000bc1,
I1 => blk00000003_sig0000012a,
I2 => blk00000003_sig00000cbb,
O => blk00000003_sig00000b8d
);
blk00000003_blk00000e36 : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig00000bc2,
I1 => blk00000003_sig0000012b,
I2 => blk00000003_sig00000cbb,
O => blk00000003_sig00000b90
);
blk00000003_blk00000e35 : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig00000bc3,
I1 => blk00000003_sig0000012c,
I2 => blk00000003_sig00000cbb,
O => blk00000003_sig00000b93
);
blk00000003_blk00000e34 : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig00000bc4,
I1 => blk00000003_sig0000012d,
I2 => blk00000003_sig00000cbb,
O => blk00000003_sig00000b96
);
blk00000003_blk00000e33 : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig00000bc5,
I1 => blk00000003_sig0000012e,
I2 => blk00000003_sig00000cbb,
O => blk00000003_sig00000b99
);
blk00000003_blk00000e32 : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig00000bc6,
I1 => blk00000003_sig0000012f,
I2 => blk00000003_sig00000cbb,
O => blk00000003_sig00000b9c
);
blk00000003_blk00000e31 : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig0000006b,
I1 => blk00000003_sig00000139,
I2 => blk00000003_sig00000cbb,
O => blk00000003_sig00000bd3
);
blk00000003_blk00000e30 : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig00000b62,
I1 => blk00000003_sig00000148,
I2 => blk00000003_sig00000cbc,
O => blk00000003_sig00000b3a
);
blk00000003_blk00000e2f : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig00000b63,
I1 => blk00000003_sig00000149,
I2 => blk00000003_sig00000cbc,
O => blk00000003_sig00000b3d
);
blk00000003_blk00000e2e : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig00000b64,
I1 => blk00000003_sig0000014a,
I2 => blk00000003_sig00000cbc,
O => blk00000003_sig00000b40
);
blk00000003_blk00000e2d : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig00000b65,
I1 => blk00000003_sig0000014b,
I2 => blk00000003_sig00000cbc,
O => blk00000003_sig00000b43
);
blk00000003_blk00000e2c : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig00000b66,
I1 => blk00000003_sig0000014c,
I2 => blk00000003_sig00000cbc,
O => blk00000003_sig00000b46
);
blk00000003_blk00000e2b : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig00000b67,
I1 => blk00000003_sig0000014d,
I2 => blk00000003_sig00000cbc,
O => blk00000003_sig00000b49
);
blk00000003_blk00000e2a : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig00000b68,
I1 => blk00000003_sig0000014e,
I2 => blk00000003_sig00000cbc,
O => blk00000003_sig00000b4c
);
blk00000003_blk00000e29 : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig00000b69,
I1 => blk00000003_sig0000014f,
I2 => blk00000003_sig00000cbc,
O => blk00000003_sig00000b4f
);
blk00000003_blk00000e28 : LUT2
generic map(
INIT => X"9"
)
port map (
I0 => blk00000003_sig00000b6b,
I1 => blk00000003_sig00000cbc,
O => blk00000003_sig00000b0d
);
blk00000003_blk00000e27 : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig00000b54,
I1 => blk00000003_sig0000013a,
I2 => blk00000003_sig00000cbc,
O => blk00000003_sig00000b10
);
blk00000003_blk00000e26 : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig00000b55,
I1 => blk00000003_sig0000013b,
I2 => blk00000003_sig00000cbc,
O => blk00000003_sig00000b13
);
blk00000003_blk00000e25 : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig00000b56,
I1 => blk00000003_sig0000013c,
I2 => blk00000003_sig00000cbc,
O => blk00000003_sig00000b16
);
blk00000003_blk00000e24 : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig00000b57,
I1 => blk00000003_sig0000013d,
I2 => blk00000003_sig00000cbc,
O => blk00000003_sig00000b19
);
blk00000003_blk00000e23 : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig00000b6a,
I1 => blk00000003_sig00000150,
I2 => blk00000003_sig00000cbc,
O => blk00000003_sig00000b52
);
blk00000003_blk00000e22 : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig00000b58,
I1 => blk00000003_sig0000013e,
I2 => blk00000003_sig00000cbc,
O => blk00000003_sig00000b1c
);
blk00000003_blk00000e21 : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig00000b59,
I1 => blk00000003_sig0000013f,
I2 => blk00000003_sig00000cbc,
O => blk00000003_sig00000b1f
);
blk00000003_blk00000e20 : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig00000b5a,
I1 => blk00000003_sig00000140,
I2 => blk00000003_sig00000cbc,
O => blk00000003_sig00000b22
);
blk00000003_blk00000e1f : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig00000b5b,
I1 => blk00000003_sig00000141,
I2 => blk00000003_sig00000cbc,
O => blk00000003_sig00000b25
);
blk00000003_blk00000e1e : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig00000b5c,
I1 => blk00000003_sig00000142,
I2 => blk00000003_sig00000cbc,
O => blk00000003_sig00000b28
);
blk00000003_blk00000e1d : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig00000b5d,
I1 => blk00000003_sig00000143,
I2 => blk00000003_sig00000cbc,
O => blk00000003_sig00000b2b
);
blk00000003_blk00000e1c : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig00000b5e,
I1 => blk00000003_sig00000144,
I2 => blk00000003_sig00000cbc,
O => blk00000003_sig00000b2e
);
blk00000003_blk00000e1b : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig00000b5f,
I1 => blk00000003_sig00000145,
I2 => blk00000003_sig00000cbc,
O => blk00000003_sig00000b31
);
blk00000003_blk00000e1a : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig00000b60,
I1 => blk00000003_sig00000146,
I2 => blk00000003_sig00000cbc,
O => blk00000003_sig00000b34
);
blk00000003_blk00000e19 : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig00000b61,
I1 => blk00000003_sig00000147,
I2 => blk00000003_sig00000cbc,
O => blk00000003_sig00000b37
);
blk00000003_blk00000e18 : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig00000070,
I1 => blk00000003_sig00000151,
I2 => blk00000003_sig00000cbc,
O => blk00000003_sig00000b6e
);
blk00000003_blk00000e17 : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig00000afd,
I1 => blk00000003_sig00000160,
I2 => blk00000003_sig00000cbd,
O => blk00000003_sig00000ad5
);
blk00000003_blk00000e16 : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig00000afe,
I1 => blk00000003_sig00000161,
I2 => blk00000003_sig00000cbd,
O => blk00000003_sig00000ad8
);
blk00000003_blk00000e15 : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig00000aff,
I1 => blk00000003_sig00000162,
I2 => blk00000003_sig00000cbd,
O => blk00000003_sig00000adb
);
blk00000003_blk00000e14 : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig00000b00,
I1 => blk00000003_sig00000163,
I2 => blk00000003_sig00000cbd,
O => blk00000003_sig00000ade
);
blk00000003_blk00000e13 : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig00000b01,
I1 => blk00000003_sig00000164,
I2 => blk00000003_sig00000cbd,
O => blk00000003_sig00000ae1
);
blk00000003_blk00000e12 : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig00000b02,
I1 => blk00000003_sig00000165,
I2 => blk00000003_sig00000cbd,
O => blk00000003_sig00000ae4
);
blk00000003_blk00000e11 : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig00000b03,
I1 => blk00000003_sig00000166,
I2 => blk00000003_sig00000cbd,
O => blk00000003_sig00000ae7
);
blk00000003_blk00000e10 : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig00000b04,
I1 => blk00000003_sig00000167,
I2 => blk00000003_sig00000cbd,
O => blk00000003_sig00000aea
);
blk00000003_blk00000e0f : LUT2
generic map(
INIT => X"9"
)
port map (
I0 => blk00000003_sig00000b06,
I1 => blk00000003_sig00000cbd,
O => blk00000003_sig00000aa8
);
blk00000003_blk00000e0e : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig00000aef,
I1 => blk00000003_sig00000152,
I2 => blk00000003_sig00000cbd,
O => blk00000003_sig00000aab
);
blk00000003_blk00000e0d : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig00000af0,
I1 => blk00000003_sig00000153,
I2 => blk00000003_sig00000cbd,
O => blk00000003_sig00000aae
);
blk00000003_blk00000e0c : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig00000af1,
I1 => blk00000003_sig00000154,
I2 => blk00000003_sig00000cbd,
O => blk00000003_sig00000ab1
);
blk00000003_blk00000e0b : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig00000af2,
I1 => blk00000003_sig00000155,
I2 => blk00000003_sig00000cbd,
O => blk00000003_sig00000ab4
);
blk00000003_blk00000e0a : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig00000b05,
I1 => blk00000003_sig00000168,
I2 => blk00000003_sig00000cbd,
O => blk00000003_sig00000aed
);
blk00000003_blk00000e09 : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig00000af3,
I1 => blk00000003_sig00000156,
I2 => blk00000003_sig00000cbd,
O => blk00000003_sig00000ab7
);
blk00000003_blk00000e08 : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig00000af4,
I1 => blk00000003_sig00000157,
I2 => blk00000003_sig00000cbd,
O => blk00000003_sig00000aba
);
blk00000003_blk00000e07 : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig00000af5,
I1 => blk00000003_sig00000158,
I2 => blk00000003_sig00000cbd,
O => blk00000003_sig00000abd
);
blk00000003_blk00000e06 : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig00000af6,
I1 => blk00000003_sig00000159,
I2 => blk00000003_sig00000cbd,
O => blk00000003_sig00000ac0
);
blk00000003_blk00000e05 : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig00000af7,
I1 => blk00000003_sig0000015a,
I2 => blk00000003_sig00000cbd,
O => blk00000003_sig00000ac3
);
blk00000003_blk00000e04 : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig00000af8,
I1 => blk00000003_sig0000015b,
I2 => blk00000003_sig00000cbd,
O => blk00000003_sig00000ac6
);
blk00000003_blk00000e03 : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig00000af9,
I1 => blk00000003_sig0000015c,
I2 => blk00000003_sig00000cbd,
O => blk00000003_sig00000ac9
);
blk00000003_blk00000e02 : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig00000afa,
I1 => blk00000003_sig0000015d,
I2 => blk00000003_sig00000cbd,
O => blk00000003_sig00000acc
);
blk00000003_blk00000e01 : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig00000afb,
I1 => blk00000003_sig0000015e,
I2 => blk00000003_sig00000cbd,
O => blk00000003_sig00000acf
);
blk00000003_blk00000e00 : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig00000afc,
I1 => blk00000003_sig0000015f,
I2 => blk00000003_sig00000cbd,
O => blk00000003_sig00000ad2
);
blk00000003_blk00000dff : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig00000076,
I1 => blk00000003_sig00000169,
I2 => blk00000003_sig00000cbd,
O => blk00000003_sig00000b09
);
blk00000003_blk00000dfe : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig00000a98,
I1 => blk00000003_sig00000178,
I2 => blk00000003_sig00000cbe,
O => blk00000003_sig00000a70
);
blk00000003_blk00000dfd : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig00000a99,
I1 => blk00000003_sig00000179,
I2 => blk00000003_sig00000cbe,
O => blk00000003_sig00000a73
);
blk00000003_blk00000dfc : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig00000a9a,
I1 => blk00000003_sig0000017a,
I2 => blk00000003_sig00000cbe,
O => blk00000003_sig00000a76
);
blk00000003_blk00000dfb : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig00000a9b,
I1 => blk00000003_sig0000017b,
I2 => blk00000003_sig00000cbe,
O => blk00000003_sig00000a79
);
blk00000003_blk00000dfa : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig00000a9c,
I1 => blk00000003_sig0000017c,
I2 => blk00000003_sig00000cbe,
O => blk00000003_sig00000a7c
);
blk00000003_blk00000df9 : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig00000a9d,
I1 => blk00000003_sig0000017d,
I2 => blk00000003_sig00000cbe,
O => blk00000003_sig00000a7f
);
blk00000003_blk00000df8 : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig00000a9e,
I1 => blk00000003_sig0000017e,
I2 => blk00000003_sig00000cbe,
O => blk00000003_sig00000a82
);
blk00000003_blk00000df7 : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig00000a9f,
I1 => blk00000003_sig0000017f,
I2 => blk00000003_sig00000cbe,
O => blk00000003_sig00000a85
);
blk00000003_blk00000df6 : LUT2
generic map(
INIT => X"9"
)
port map (
I0 => blk00000003_sig00000aa1,
I1 => blk00000003_sig00000cbe,
O => blk00000003_sig00000a43
);
blk00000003_blk00000df5 : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig00000a8a,
I1 => blk00000003_sig0000016a,
I2 => blk00000003_sig00000cbe,
O => blk00000003_sig00000a46
);
blk00000003_blk00000df4 : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig00000a8b,
I1 => blk00000003_sig0000016b,
I2 => blk00000003_sig00000cbe,
O => blk00000003_sig00000a49
);
blk00000003_blk00000df3 : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig00000a8c,
I1 => blk00000003_sig0000016c,
I2 => blk00000003_sig00000cbe,
O => blk00000003_sig00000a4c
);
blk00000003_blk00000df2 : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig00000a8d,
I1 => blk00000003_sig0000016d,
I2 => blk00000003_sig00000cbe,
O => blk00000003_sig00000a4f
);
blk00000003_blk00000df1 : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig00000aa0,
I1 => blk00000003_sig00000180,
I2 => blk00000003_sig00000cbe,
O => blk00000003_sig00000a88
);
blk00000003_blk00000df0 : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig00000a8e,
I1 => blk00000003_sig0000016e,
I2 => blk00000003_sig00000cbe,
O => blk00000003_sig00000a52
);
blk00000003_blk00000def : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig00000a8f,
I1 => blk00000003_sig0000016f,
I2 => blk00000003_sig00000cbe,
O => blk00000003_sig00000a55
);
blk00000003_blk00000dee : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig00000a90,
I1 => blk00000003_sig00000170,
I2 => blk00000003_sig00000cbe,
O => blk00000003_sig00000a58
);
blk00000003_blk00000ded : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig00000a91,
I1 => blk00000003_sig00000171,
I2 => blk00000003_sig00000cbe,
O => blk00000003_sig00000a5b
);
blk00000003_blk00000dec : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig00000a92,
I1 => blk00000003_sig00000172,
I2 => blk00000003_sig00000cbe,
O => blk00000003_sig00000a5e
);
blk00000003_blk00000deb : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig00000a93,
I1 => blk00000003_sig00000173,
I2 => blk00000003_sig00000cbe,
O => blk00000003_sig00000a61
);
blk00000003_blk00000dea : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig00000a94,
I1 => blk00000003_sig00000174,
I2 => blk00000003_sig00000cbe,
O => blk00000003_sig00000a64
);
blk00000003_blk00000de9 : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig00000a95,
I1 => blk00000003_sig00000175,
I2 => blk00000003_sig00000cbe,
O => blk00000003_sig00000a67
);
blk00000003_blk00000de8 : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig00000a96,
I1 => blk00000003_sig00000176,
I2 => blk00000003_sig00000cbe,
O => blk00000003_sig00000a6a
);
blk00000003_blk00000de7 : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig00000a97,
I1 => blk00000003_sig00000177,
I2 => blk00000003_sig00000cbe,
O => blk00000003_sig00000a6d
);
blk00000003_blk00000de6 : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig0000007d,
I1 => blk00000003_sig00000181,
I2 => blk00000003_sig00000cbe,
O => blk00000003_sig00000aa4
);
blk00000003_blk00000de5 : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig00000a33,
I1 => blk00000003_sig00000190,
I2 => blk00000003_sig00000cbf,
O => blk00000003_sig00000a0b
);
blk00000003_blk00000de4 : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig00000a34,
I1 => blk00000003_sig00000191,
I2 => blk00000003_sig00000cbf,
O => blk00000003_sig00000a0e
);
blk00000003_blk00000de3 : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig00000a35,
I1 => blk00000003_sig00000192,
I2 => blk00000003_sig00000cbf,
O => blk00000003_sig00000a11
);
blk00000003_blk00000de2 : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig00000a36,
I1 => blk00000003_sig00000193,
I2 => blk00000003_sig00000cbf,
O => blk00000003_sig00000a14
);
blk00000003_blk00000de1 : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig00000a37,
I1 => blk00000003_sig00000194,
I2 => blk00000003_sig00000cbf,
O => blk00000003_sig00000a17
);
blk00000003_blk00000de0 : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig00000a38,
I1 => blk00000003_sig00000195,
I2 => blk00000003_sig00000cbf,
O => blk00000003_sig00000a1a
);
blk00000003_blk00000ddf : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig00000a39,
I1 => blk00000003_sig00000196,
I2 => blk00000003_sig00000cbf,
O => blk00000003_sig00000a1d
);
blk00000003_blk00000dde : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig00000a3a,
I1 => blk00000003_sig00000197,
I2 => blk00000003_sig00000cbf,
O => blk00000003_sig00000a20
);
blk00000003_blk00000ddd : LUT2
generic map(
INIT => X"9"
)
port map (
I0 => blk00000003_sig00000a3c,
I1 => blk00000003_sig00000cbf,
O => blk00000003_sig000009de
);
blk00000003_blk00000ddc : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig00000a25,
I1 => blk00000003_sig00000182,
I2 => blk00000003_sig00000cbf,
O => blk00000003_sig000009e1
);
blk00000003_blk00000ddb : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig00000a26,
I1 => blk00000003_sig00000183,
I2 => blk00000003_sig00000cbf,
O => blk00000003_sig000009e4
);
blk00000003_blk00000dda : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig00000a27,
I1 => blk00000003_sig00000184,
I2 => blk00000003_sig00000cbf,
O => blk00000003_sig000009e7
);
blk00000003_blk00000dd9 : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig00000a28,
I1 => blk00000003_sig00000185,
I2 => blk00000003_sig00000cbf,
O => blk00000003_sig000009ea
);
blk00000003_blk00000dd8 : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig00000a3b,
I1 => blk00000003_sig00000198,
I2 => blk00000003_sig00000cbf,
O => blk00000003_sig00000a23
);
blk00000003_blk00000dd7 : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig00000a29,
I1 => blk00000003_sig00000186,
I2 => blk00000003_sig00000cbf,
O => blk00000003_sig000009ed
);
blk00000003_blk00000dd6 : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig00000a2a,
I1 => blk00000003_sig00000187,
I2 => blk00000003_sig00000cbf,
O => blk00000003_sig000009f0
);
blk00000003_blk00000dd5 : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig00000a2b,
I1 => blk00000003_sig00000188,
I2 => blk00000003_sig00000cbf,
O => blk00000003_sig000009f3
);
blk00000003_blk00000dd4 : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig00000a2c,
I1 => blk00000003_sig00000189,
I2 => blk00000003_sig00000cbf,
O => blk00000003_sig000009f6
);
blk00000003_blk00000dd3 : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig00000a2d,
I1 => blk00000003_sig0000018a,
I2 => blk00000003_sig00000cbf,
O => blk00000003_sig000009f9
);
blk00000003_blk00000dd2 : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig00000a2e,
I1 => blk00000003_sig0000018b,
I2 => blk00000003_sig00000cbf,
O => blk00000003_sig000009fc
);
blk00000003_blk00000dd1 : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig00000a2f,
I1 => blk00000003_sig0000018c,
I2 => blk00000003_sig00000cbf,
O => blk00000003_sig000009ff
);
blk00000003_blk00000dd0 : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig00000a30,
I1 => blk00000003_sig0000018d,
I2 => blk00000003_sig00000cbf,
O => blk00000003_sig00000a02
);
blk00000003_blk00000dcf : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig00000a31,
I1 => blk00000003_sig0000018e,
I2 => blk00000003_sig00000cbf,
O => blk00000003_sig00000a05
);
blk00000003_blk00000dce : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig00000a32,
I1 => blk00000003_sig0000018f,
I2 => blk00000003_sig00000cbf,
O => blk00000003_sig00000a08
);
blk00000003_blk00000dcd : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig00000085,
I1 => blk00000003_sig00000199,
I2 => blk00000003_sig00000cbf,
O => blk00000003_sig00000a3f
);
blk00000003_blk00000dcc : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig000009cd,
I1 => blk00000003_sig000001a8,
I2 => blk00000003_sig00000cc0,
O => blk00000003_sig000009a5
);
blk00000003_blk00000dcb : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig000009ce,
I1 => blk00000003_sig000001a9,
I2 => blk00000003_sig00000cc0,
O => blk00000003_sig000009a8
);
blk00000003_blk00000dca : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig000009cf,
I1 => blk00000003_sig000001aa,
I2 => blk00000003_sig00000cc0,
O => blk00000003_sig000009ab
);
blk00000003_blk00000dc9 : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig000009d0,
I1 => blk00000003_sig000001ab,
I2 => blk00000003_sig00000cc0,
O => blk00000003_sig000009ae
);
blk00000003_blk00000dc8 : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig000009d1,
I1 => blk00000003_sig000001ac,
I2 => blk00000003_sig00000cc0,
O => blk00000003_sig000009b1
);
blk00000003_blk00000dc7 : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig000009d2,
I1 => blk00000003_sig000001ad,
I2 => blk00000003_sig00000cc0,
O => blk00000003_sig000009b4
);
blk00000003_blk00000dc6 : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig000009d3,
I1 => blk00000003_sig000001ae,
I2 => blk00000003_sig00000cc0,
O => blk00000003_sig000009b7
);
blk00000003_blk00000dc5 : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig000009d4,
I1 => blk00000003_sig000001af,
I2 => blk00000003_sig00000cc0,
O => blk00000003_sig000009ba
);
blk00000003_blk00000dc4 : LUT2
generic map(
INIT => X"9"
)
port map (
I0 => blk00000003_sig000009d6,
I1 => blk00000003_sig00000cc0,
O => blk00000003_sig00000978
);
blk00000003_blk00000dc3 : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig000009bf,
I1 => blk00000003_sig0000019a,
I2 => blk00000003_sig00000cc0,
O => blk00000003_sig0000097b
);
blk00000003_blk00000dc2 : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig000009c0,
I1 => blk00000003_sig0000019b,
I2 => blk00000003_sig00000cc0,
O => blk00000003_sig0000097e
);
blk00000003_blk00000dc1 : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig000009c1,
I1 => blk00000003_sig0000019c,
I2 => blk00000003_sig00000cc0,
O => blk00000003_sig00000981
);
blk00000003_blk00000dc0 : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig000009c2,
I1 => blk00000003_sig0000019d,
I2 => blk00000003_sig00000cc0,
O => blk00000003_sig00000984
);
blk00000003_blk00000dbf : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig000009d5,
I1 => blk00000003_sig000001b0,
I2 => blk00000003_sig00000cc0,
O => blk00000003_sig000009bd
);
blk00000003_blk00000dbe : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig000009c3,
I1 => blk00000003_sig0000019e,
I2 => blk00000003_sig00000cc0,
O => blk00000003_sig00000987
);
blk00000003_blk00000dbd : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig000009c4,
I1 => blk00000003_sig0000019f,
I2 => blk00000003_sig00000cc0,
O => blk00000003_sig0000098a
);
blk00000003_blk00000dbc : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig000009c5,
I1 => blk00000003_sig000001a0,
I2 => blk00000003_sig00000cc0,
O => blk00000003_sig0000098d
);
blk00000003_blk00000dbb : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig000009c6,
I1 => blk00000003_sig000001a1,
I2 => blk00000003_sig00000cc0,
O => blk00000003_sig00000990
);
blk00000003_blk00000dba : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig000009c7,
I1 => blk00000003_sig000001a2,
I2 => blk00000003_sig00000cc0,
O => blk00000003_sig00000993
);
blk00000003_blk00000db9 : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig000009c8,
I1 => blk00000003_sig000001a3,
I2 => blk00000003_sig00000cc0,
O => blk00000003_sig00000996
);
blk00000003_blk00000db8 : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig000009c9,
I1 => blk00000003_sig000001a4,
I2 => blk00000003_sig00000cc0,
O => blk00000003_sig00000999
);
blk00000003_blk00000db7 : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig000009ca,
I1 => blk00000003_sig000001a5,
I2 => blk00000003_sig00000cc0,
O => blk00000003_sig0000099c
);
blk00000003_blk00000db6 : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig000009cb,
I1 => blk00000003_sig000001a6,
I2 => blk00000003_sig00000cc0,
O => blk00000003_sig0000099f
);
blk00000003_blk00000db5 : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig000009cc,
I1 => blk00000003_sig000001a7,
I2 => blk00000003_sig00000cc0,
O => blk00000003_sig000009a2
);
blk00000003_blk00000db4 : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig000009db,
I1 => blk00000003_sig000001b1,
I2 => blk00000003_sig00000cc0,
O => blk00000003_sig000009d9
);
blk00000003_blk00000db3 : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig00000967,
I1 => blk00000003_sig000001c0,
I2 => blk00000003_sig00000cc1,
O => blk00000003_sig0000093f
);
blk00000003_blk00000db2 : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig00000968,
I1 => blk00000003_sig000001c1,
I2 => blk00000003_sig00000cc1,
O => blk00000003_sig00000942
);
blk00000003_blk00000db1 : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig00000969,
I1 => blk00000003_sig000001c2,
I2 => blk00000003_sig00000cc1,
O => blk00000003_sig00000945
);
blk00000003_blk00000db0 : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig0000096a,
I1 => blk00000003_sig000001c3,
I2 => blk00000003_sig00000cc1,
O => blk00000003_sig00000948
);
blk00000003_blk00000daf : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig0000096b,
I1 => blk00000003_sig000001c4,
I2 => blk00000003_sig00000cc1,
O => blk00000003_sig0000094b
);
blk00000003_blk00000dae : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig0000096c,
I1 => blk00000003_sig000001c5,
I2 => blk00000003_sig00000cc1,
O => blk00000003_sig0000094e
);
blk00000003_blk00000dad : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig0000096d,
I1 => blk00000003_sig000001c6,
I2 => blk00000003_sig00000cc1,
O => blk00000003_sig00000951
);
blk00000003_blk00000dac : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig0000096e,
I1 => blk00000003_sig000001c7,
I2 => blk00000003_sig00000cc1,
O => blk00000003_sig00000954
);
blk00000003_blk00000dab : LUT2
generic map(
INIT => X"9"
)
port map (
I0 => blk00000003_sig00000970,
I1 => blk00000003_sig00000cc1,
O => blk00000003_sig00000912
);
blk00000003_blk00000daa : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig00000959,
I1 => blk00000003_sig000001b2,
I2 => blk00000003_sig00000cc1,
O => blk00000003_sig00000915
);
blk00000003_blk00000da9 : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig0000095a,
I1 => blk00000003_sig000001b3,
I2 => blk00000003_sig00000cc1,
O => blk00000003_sig00000918
);
blk00000003_blk00000da8 : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig0000095b,
I1 => blk00000003_sig000001b4,
I2 => blk00000003_sig00000cc1,
O => blk00000003_sig0000091b
);
blk00000003_blk00000da7 : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig0000095c,
I1 => blk00000003_sig000001b5,
I2 => blk00000003_sig00000cc1,
O => blk00000003_sig0000091e
);
blk00000003_blk00000da6 : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig0000096f,
I1 => blk00000003_sig000001c8,
I2 => blk00000003_sig00000cc1,
O => blk00000003_sig00000957
);
blk00000003_blk00000da5 : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig0000095d,
I1 => blk00000003_sig000001b6,
I2 => blk00000003_sig00000cc1,
O => blk00000003_sig00000921
);
blk00000003_blk00000da4 : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig0000095e,
I1 => blk00000003_sig000001b7,
I2 => blk00000003_sig00000cc1,
O => blk00000003_sig00000924
);
blk00000003_blk00000da3 : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig0000095f,
I1 => blk00000003_sig000001b8,
I2 => blk00000003_sig00000cc1,
O => blk00000003_sig00000927
);
blk00000003_blk00000da2 : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig00000960,
I1 => blk00000003_sig000001b9,
I2 => blk00000003_sig00000cc1,
O => blk00000003_sig0000092a
);
blk00000003_blk00000da1 : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig00000961,
I1 => blk00000003_sig000001ba,
I2 => blk00000003_sig00000cc1,
O => blk00000003_sig0000092d
);
blk00000003_blk00000da0 : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig00000962,
I1 => blk00000003_sig000001bb,
I2 => blk00000003_sig00000cc1,
O => blk00000003_sig00000930
);
blk00000003_blk00000d9f : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig00000963,
I1 => blk00000003_sig000001bc,
I2 => blk00000003_sig00000cc1,
O => blk00000003_sig00000933
);
blk00000003_blk00000d9e : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig00000964,
I1 => blk00000003_sig000001bd,
I2 => blk00000003_sig00000cc1,
O => blk00000003_sig00000936
);
blk00000003_blk00000d9d : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig00000965,
I1 => blk00000003_sig000001be,
I2 => blk00000003_sig00000cc1,
O => blk00000003_sig00000939
);
blk00000003_blk00000d9c : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig00000966,
I1 => blk00000003_sig000001bf,
I2 => blk00000003_sig00000cc1,
O => blk00000003_sig0000093c
);
blk00000003_blk00000d9b : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig00000975,
I1 => blk00000003_sig000001c9,
I2 => blk00000003_sig00000cc1,
O => blk00000003_sig00000973
);
blk00000003_blk00000d9a : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig00000901,
I1 => blk00000003_sig000001d8,
I2 => blk00000003_sig00000cc2,
O => blk00000003_sig000008d9
);
blk00000003_blk00000d99 : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig00000902,
I1 => blk00000003_sig000001d9,
I2 => blk00000003_sig00000cc2,
O => blk00000003_sig000008dc
);
blk00000003_blk00000d98 : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig00000903,
I1 => blk00000003_sig000001da,
I2 => blk00000003_sig00000cc2,
O => blk00000003_sig000008df
);
blk00000003_blk00000d97 : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig00000904,
I1 => blk00000003_sig000001db,
I2 => blk00000003_sig00000cc2,
O => blk00000003_sig000008e2
);
blk00000003_blk00000d96 : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig00000905,
I1 => blk00000003_sig000001dc,
I2 => blk00000003_sig00000cc2,
O => blk00000003_sig000008e5
);
blk00000003_blk00000d95 : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig00000906,
I1 => blk00000003_sig000001dd,
I2 => blk00000003_sig00000cc2,
O => blk00000003_sig000008e8
);
blk00000003_blk00000d94 : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig00000907,
I1 => blk00000003_sig000001de,
I2 => blk00000003_sig00000cc2,
O => blk00000003_sig000008eb
);
blk00000003_blk00000d93 : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig00000908,
I1 => blk00000003_sig000001df,
I2 => blk00000003_sig00000cc2,
O => blk00000003_sig000008ee
);
blk00000003_blk00000d92 : LUT2
generic map(
INIT => X"9"
)
port map (
I0 => blk00000003_sig0000090a,
I1 => blk00000003_sig00000cc2,
O => blk00000003_sig000008ac
);
blk00000003_blk00000d91 : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig000008f3,
I1 => blk00000003_sig000001ca,
I2 => blk00000003_sig00000cc2,
O => blk00000003_sig000008af
);
blk00000003_blk00000d90 : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig000008f4,
I1 => blk00000003_sig000001cb,
I2 => blk00000003_sig00000cc2,
O => blk00000003_sig000008b2
);
blk00000003_blk00000d8f : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig000008f5,
I1 => blk00000003_sig000001cc,
I2 => blk00000003_sig00000cc2,
O => blk00000003_sig000008b5
);
blk00000003_blk00000d8e : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig000008f6,
I1 => blk00000003_sig000001cd,
I2 => blk00000003_sig00000cc2,
O => blk00000003_sig000008b8
);
blk00000003_blk00000d8d : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig00000909,
I1 => blk00000003_sig000001e0,
I2 => blk00000003_sig00000cc2,
O => blk00000003_sig000008f1
);
blk00000003_blk00000d8c : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig000008f7,
I1 => blk00000003_sig000001ce,
I2 => blk00000003_sig00000cc2,
O => blk00000003_sig000008bb
);
blk00000003_blk00000d8b : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig000008f8,
I1 => blk00000003_sig000001cf,
I2 => blk00000003_sig00000cc2,
O => blk00000003_sig000008be
);
blk00000003_blk00000d8a : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig000008f9,
I1 => blk00000003_sig000001d0,
I2 => blk00000003_sig00000cc2,
O => blk00000003_sig000008c1
);
blk00000003_blk00000d89 : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig000008fa,
I1 => blk00000003_sig000001d1,
I2 => blk00000003_sig00000cc2,
O => blk00000003_sig000008c4
);
blk00000003_blk00000d88 : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig000008fb,
I1 => blk00000003_sig000001d2,
I2 => blk00000003_sig00000cc2,
O => blk00000003_sig000008c7
);
blk00000003_blk00000d87 : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig000008fc,
I1 => blk00000003_sig000001d3,
I2 => blk00000003_sig00000cc2,
O => blk00000003_sig000008ca
);
blk00000003_blk00000d86 : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig000008fd,
I1 => blk00000003_sig000001d4,
I2 => blk00000003_sig00000cc2,
O => blk00000003_sig000008cd
);
blk00000003_blk00000d85 : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig000008fe,
I1 => blk00000003_sig000001d5,
I2 => blk00000003_sig00000cc2,
O => blk00000003_sig000008d0
);
blk00000003_blk00000d84 : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig000008ff,
I1 => blk00000003_sig000001d6,
I2 => blk00000003_sig00000cc2,
O => blk00000003_sig000008d3
);
blk00000003_blk00000d83 : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig00000900,
I1 => blk00000003_sig000001d7,
I2 => blk00000003_sig00000cc2,
O => blk00000003_sig000008d6
);
blk00000003_blk00000d82 : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig0000090f,
I1 => blk00000003_sig000001e1,
I2 => blk00000003_sig00000cc2,
O => blk00000003_sig0000090d
);
blk00000003_blk00000d81 : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig0000089b,
I1 => blk00000003_sig000001f0,
I2 => blk00000003_sig00000cc3,
O => blk00000003_sig00000873
);
blk00000003_blk00000d80 : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig0000089c,
I1 => blk00000003_sig000001f1,
I2 => blk00000003_sig00000cc3,
O => blk00000003_sig00000876
);
blk00000003_blk00000d7f : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig0000089d,
I1 => blk00000003_sig000001f2,
I2 => blk00000003_sig00000cc3,
O => blk00000003_sig00000879
);
blk00000003_blk00000d7e : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig0000089e,
I1 => blk00000003_sig000001f3,
I2 => blk00000003_sig00000cc3,
O => blk00000003_sig0000087c
);
blk00000003_blk00000d7d : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig0000089f,
I1 => blk00000003_sig000001f4,
I2 => blk00000003_sig00000cc3,
O => blk00000003_sig0000087f
);
blk00000003_blk00000d7c : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig000008a0,
I1 => blk00000003_sig000001f5,
I2 => blk00000003_sig00000cc3,
O => blk00000003_sig00000882
);
blk00000003_blk00000d7b : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig000008a1,
I1 => blk00000003_sig000001f6,
I2 => blk00000003_sig00000cc3,
O => blk00000003_sig00000885
);
blk00000003_blk00000d7a : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig000008a2,
I1 => blk00000003_sig000001f7,
I2 => blk00000003_sig00000cc3,
O => blk00000003_sig00000888
);
blk00000003_blk00000d79 : LUT2
generic map(
INIT => X"9"
)
port map (
I0 => blk00000003_sig000008a4,
I1 => blk00000003_sig00000cc3,
O => blk00000003_sig00000846
);
blk00000003_blk00000d78 : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig0000088d,
I1 => blk00000003_sig000001e2,
I2 => blk00000003_sig00000cc3,
O => blk00000003_sig00000849
);
blk00000003_blk00000d77 : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig0000088e,
I1 => blk00000003_sig000001e3,
I2 => blk00000003_sig00000cc3,
O => blk00000003_sig0000084c
);
blk00000003_blk00000d76 : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig0000088f,
I1 => blk00000003_sig000001e4,
I2 => blk00000003_sig00000cc3,
O => blk00000003_sig0000084f
);
blk00000003_blk00000d75 : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig00000890,
I1 => blk00000003_sig000001e5,
I2 => blk00000003_sig00000cc3,
O => blk00000003_sig00000852
);
blk00000003_blk00000d74 : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig000008a3,
I1 => blk00000003_sig000001f8,
I2 => blk00000003_sig00000cc3,
O => blk00000003_sig0000088b
);
blk00000003_blk00000d73 : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig00000891,
I1 => blk00000003_sig000001e6,
I2 => blk00000003_sig00000cc3,
O => blk00000003_sig00000855
);
blk00000003_blk00000d72 : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig00000892,
I1 => blk00000003_sig000001e7,
I2 => blk00000003_sig00000cc3,
O => blk00000003_sig00000858
);
blk00000003_blk00000d71 : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig00000893,
I1 => blk00000003_sig000001e8,
I2 => blk00000003_sig00000cc3,
O => blk00000003_sig0000085b
);
blk00000003_blk00000d70 : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig00000894,
I1 => blk00000003_sig000001e9,
I2 => blk00000003_sig00000cc3,
O => blk00000003_sig0000085e
);
blk00000003_blk00000d6f : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig00000895,
I1 => blk00000003_sig000001ea,
I2 => blk00000003_sig00000cc3,
O => blk00000003_sig00000861
);
blk00000003_blk00000d6e : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig00000896,
I1 => blk00000003_sig000001eb,
I2 => blk00000003_sig00000cc3,
O => blk00000003_sig00000864
);
blk00000003_blk00000d6d : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig00000897,
I1 => blk00000003_sig000001ec,
I2 => blk00000003_sig00000cc3,
O => blk00000003_sig00000867
);
blk00000003_blk00000d6c : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig00000898,
I1 => blk00000003_sig000001ed,
I2 => blk00000003_sig00000cc3,
O => blk00000003_sig0000086a
);
blk00000003_blk00000d6b : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig00000899,
I1 => blk00000003_sig000001ee,
I2 => blk00000003_sig00000cc3,
O => blk00000003_sig0000086d
);
blk00000003_blk00000d6a : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig0000089a,
I1 => blk00000003_sig000001ef,
I2 => blk00000003_sig00000cc3,
O => blk00000003_sig00000870
);
blk00000003_blk00000d69 : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig000008a9,
I1 => blk00000003_sig000001f9,
I2 => blk00000003_sig00000cc3,
O => blk00000003_sig000008a7
);
blk00000003_blk00000d68 : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig00000835,
I1 => blk00000003_sig00000208,
I2 => blk00000003_sig00000cc4,
O => blk00000003_sig0000080d
);
blk00000003_blk00000d67 : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig00000836,
I1 => blk00000003_sig00000209,
I2 => blk00000003_sig00000cc4,
O => blk00000003_sig00000810
);
blk00000003_blk00000d66 : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig00000837,
I1 => blk00000003_sig0000020a,
I2 => blk00000003_sig00000cc4,
O => blk00000003_sig00000813
);
blk00000003_blk00000d65 : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig00000838,
I1 => blk00000003_sig0000020b,
I2 => blk00000003_sig00000cc4,
O => blk00000003_sig00000816
);
blk00000003_blk00000d64 : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig00000839,
I1 => blk00000003_sig0000020c,
I2 => blk00000003_sig00000cc4,
O => blk00000003_sig00000819
);
blk00000003_blk00000d63 : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig0000083a,
I1 => blk00000003_sig0000020d,
I2 => blk00000003_sig00000cc4,
O => blk00000003_sig0000081c
);
blk00000003_blk00000d62 : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig0000083b,
I1 => blk00000003_sig0000020e,
I2 => blk00000003_sig00000cc4,
O => blk00000003_sig0000081f
);
blk00000003_blk00000d61 : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig0000083c,
I1 => blk00000003_sig0000020f,
I2 => blk00000003_sig00000cc4,
O => blk00000003_sig00000822
);
blk00000003_blk00000d60 : LUT2
generic map(
INIT => X"9"
)
port map (
I0 => blk00000003_sig0000083e,
I1 => blk00000003_sig00000cc4,
O => blk00000003_sig000007e0
);
blk00000003_blk00000d5f : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig00000827,
I1 => blk00000003_sig000001fa,
I2 => blk00000003_sig00000cc4,
O => blk00000003_sig000007e3
);
blk00000003_blk00000d5e : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig00000828,
I1 => blk00000003_sig000001fb,
I2 => blk00000003_sig00000cc4,
O => blk00000003_sig000007e6
);
blk00000003_blk00000d5d : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig00000829,
I1 => blk00000003_sig000001fc,
I2 => blk00000003_sig00000cc4,
O => blk00000003_sig000007e9
);
blk00000003_blk00000d5c : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig0000082a,
I1 => blk00000003_sig000001fd,
I2 => blk00000003_sig00000cc4,
O => blk00000003_sig000007ec
);
blk00000003_blk00000d5b : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig0000083d,
I1 => blk00000003_sig00000210,
I2 => blk00000003_sig00000cc4,
O => blk00000003_sig00000825
);
blk00000003_blk00000d5a : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig0000082b,
I1 => blk00000003_sig000001fe,
I2 => blk00000003_sig00000cc4,
O => blk00000003_sig000007ef
);
blk00000003_blk00000d59 : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig0000082c,
I1 => blk00000003_sig000001ff,
I2 => blk00000003_sig00000cc4,
O => blk00000003_sig000007f2
);
blk00000003_blk00000d58 : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig0000082d,
I1 => blk00000003_sig00000200,
I2 => blk00000003_sig00000cc4,
O => blk00000003_sig000007f5
);
blk00000003_blk00000d57 : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig0000082e,
I1 => blk00000003_sig00000201,
I2 => blk00000003_sig00000cc4,
O => blk00000003_sig000007f8
);
blk00000003_blk00000d56 : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig0000082f,
I1 => blk00000003_sig00000202,
I2 => blk00000003_sig00000cc4,
O => blk00000003_sig000007fb
);
blk00000003_blk00000d55 : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig00000830,
I1 => blk00000003_sig00000203,
I2 => blk00000003_sig00000cc4,
O => blk00000003_sig000007fe
);
blk00000003_blk00000d54 : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig00000831,
I1 => blk00000003_sig00000204,
I2 => blk00000003_sig00000cc4,
O => blk00000003_sig00000801
);
blk00000003_blk00000d53 : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig00000832,
I1 => blk00000003_sig00000205,
I2 => blk00000003_sig00000cc4,
O => blk00000003_sig00000804
);
blk00000003_blk00000d52 : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig00000833,
I1 => blk00000003_sig00000206,
I2 => blk00000003_sig00000cc4,
O => blk00000003_sig00000807
);
blk00000003_blk00000d51 : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig00000834,
I1 => blk00000003_sig00000207,
I2 => blk00000003_sig00000cc4,
O => blk00000003_sig0000080a
);
blk00000003_blk00000d50 : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig00000843,
I1 => blk00000003_sig00000211,
I2 => blk00000003_sig00000cc4,
O => blk00000003_sig00000841
);
blk00000003_blk00000d4f : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig000007cf,
I1 => blk00000003_sig00000220,
I2 => blk00000003_sig00000cc5,
O => blk00000003_sig000007a7
);
blk00000003_blk00000d4e : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig000007d0,
I1 => blk00000003_sig00000221,
I2 => blk00000003_sig00000cc5,
O => blk00000003_sig000007aa
);
blk00000003_blk00000d4d : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig000007d1,
I1 => blk00000003_sig00000222,
I2 => blk00000003_sig00000cc5,
O => blk00000003_sig000007ad
);
blk00000003_blk00000d4c : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig000007d2,
I1 => blk00000003_sig00000223,
I2 => blk00000003_sig00000cc5,
O => blk00000003_sig000007b0
);
blk00000003_blk00000d4b : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig000007d3,
I1 => blk00000003_sig00000224,
I2 => blk00000003_sig00000cc5,
O => blk00000003_sig000007b3
);
blk00000003_blk00000d4a : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig000007d4,
I1 => blk00000003_sig00000225,
I2 => blk00000003_sig00000cc5,
O => blk00000003_sig000007b6
);
blk00000003_blk00000d49 : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig000007d5,
I1 => blk00000003_sig00000226,
I2 => blk00000003_sig00000cc5,
O => blk00000003_sig000007b9
);
blk00000003_blk00000d48 : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig000007d6,
I1 => blk00000003_sig00000227,
I2 => blk00000003_sig00000cc5,
O => blk00000003_sig000007bc
);
blk00000003_blk00000d47 : LUT2
generic map(
INIT => X"9"
)
port map (
I0 => blk00000003_sig000007d8,
I1 => blk00000003_sig00000cc5,
O => blk00000003_sig0000077a
);
blk00000003_blk00000d46 : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig000007c1,
I1 => blk00000003_sig00000212,
I2 => blk00000003_sig00000cc5,
O => blk00000003_sig0000077d
);
blk00000003_blk00000d45 : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig000007c2,
I1 => blk00000003_sig00000213,
I2 => blk00000003_sig00000cc5,
O => blk00000003_sig00000780
);
blk00000003_blk00000d44 : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig000007c3,
I1 => blk00000003_sig00000214,
I2 => blk00000003_sig00000cc5,
O => blk00000003_sig00000783
);
blk00000003_blk00000d43 : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig000007c4,
I1 => blk00000003_sig00000215,
I2 => blk00000003_sig00000cc5,
O => blk00000003_sig00000786
);
blk00000003_blk00000d42 : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig000007d7,
I1 => blk00000003_sig00000228,
I2 => blk00000003_sig00000cc5,
O => blk00000003_sig000007bf
);
blk00000003_blk00000d41 : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig000007c5,
I1 => blk00000003_sig00000216,
I2 => blk00000003_sig00000cc5,
O => blk00000003_sig00000789
);
blk00000003_blk00000d40 : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig000007c6,
I1 => blk00000003_sig00000217,
I2 => blk00000003_sig00000cc5,
O => blk00000003_sig0000078c
);
blk00000003_blk00000d3f : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig000007c7,
I1 => blk00000003_sig00000218,
I2 => blk00000003_sig00000cc5,
O => blk00000003_sig0000078f
);
blk00000003_blk00000d3e : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig000007c8,
I1 => blk00000003_sig00000219,
I2 => blk00000003_sig00000cc5,
O => blk00000003_sig00000792
);
blk00000003_blk00000d3d : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig000007c9,
I1 => blk00000003_sig0000021a,
I2 => blk00000003_sig00000cc5,
O => blk00000003_sig00000795
);
blk00000003_blk00000d3c : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig000007ca,
I1 => blk00000003_sig0000021b,
I2 => blk00000003_sig00000cc5,
O => blk00000003_sig00000798
);
blk00000003_blk00000d3b : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig000007cb,
I1 => blk00000003_sig0000021c,
I2 => blk00000003_sig00000cc5,
O => blk00000003_sig0000079b
);
blk00000003_blk00000d3a : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig000007cc,
I1 => blk00000003_sig0000021d,
I2 => blk00000003_sig00000cc5,
O => blk00000003_sig0000079e
);
blk00000003_blk00000d39 : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig000007cd,
I1 => blk00000003_sig0000021e,
I2 => blk00000003_sig00000cc5,
O => blk00000003_sig000007a1
);
blk00000003_blk00000d38 : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig000007ce,
I1 => blk00000003_sig0000021f,
I2 => blk00000003_sig00000cc5,
O => blk00000003_sig000007a4
);
blk00000003_blk00000d37 : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig000007dd,
I1 => blk00000003_sig00000229,
I2 => blk00000003_sig00000cc5,
O => blk00000003_sig000007db
);
blk00000003_blk00000d36 : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig00000769,
I1 => blk00000003_sig00000238,
I2 => blk00000003_sig00000cc6,
O => blk00000003_sig00000741
);
blk00000003_blk00000d35 : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig0000076a,
I1 => blk00000003_sig00000239,
I2 => blk00000003_sig00000cc6,
O => blk00000003_sig00000744
);
blk00000003_blk00000d34 : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig0000076b,
I1 => blk00000003_sig0000023a,
I2 => blk00000003_sig00000cc6,
O => blk00000003_sig00000747
);
blk00000003_blk00000d33 : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig0000076c,
I1 => blk00000003_sig0000023b,
I2 => blk00000003_sig00000cc6,
O => blk00000003_sig0000074a
);
blk00000003_blk00000d32 : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig0000076d,
I1 => blk00000003_sig0000023c,
I2 => blk00000003_sig00000cc6,
O => blk00000003_sig0000074d
);
blk00000003_blk00000d31 : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig0000076e,
I1 => blk00000003_sig0000023d,
I2 => blk00000003_sig00000cc6,
O => blk00000003_sig00000750
);
blk00000003_blk00000d30 : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig0000076f,
I1 => blk00000003_sig0000023e,
I2 => blk00000003_sig00000cc6,
O => blk00000003_sig00000753
);
blk00000003_blk00000d2f : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig00000770,
I1 => blk00000003_sig0000023f,
I2 => blk00000003_sig00000cc6,
O => blk00000003_sig00000756
);
blk00000003_blk00000d2e : LUT2
generic map(
INIT => X"9"
)
port map (
I0 => blk00000003_sig00000772,
I1 => blk00000003_sig00000cc6,
O => blk00000003_sig00000714
);
blk00000003_blk00000d2d : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig0000075b,
I1 => blk00000003_sig0000022a,
I2 => blk00000003_sig00000cc6,
O => blk00000003_sig00000717
);
blk00000003_blk00000d2c : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig0000075c,
I1 => blk00000003_sig0000022b,
I2 => blk00000003_sig00000cc6,
O => blk00000003_sig0000071a
);
blk00000003_blk00000d2b : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig0000075d,
I1 => blk00000003_sig0000022c,
I2 => blk00000003_sig00000cc6,
O => blk00000003_sig0000071d
);
blk00000003_blk00000d2a : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig0000075e,
I1 => blk00000003_sig0000022d,
I2 => blk00000003_sig00000cc6,
O => blk00000003_sig00000720
);
blk00000003_blk00000d29 : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig00000771,
I1 => blk00000003_sig00000240,
I2 => blk00000003_sig00000cc6,
O => blk00000003_sig00000759
);
blk00000003_blk00000d28 : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig0000075f,
I1 => blk00000003_sig0000022e,
I2 => blk00000003_sig00000cc6,
O => blk00000003_sig00000723
);
blk00000003_blk00000d27 : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig00000760,
I1 => blk00000003_sig0000022f,
I2 => blk00000003_sig00000cc6,
O => blk00000003_sig00000726
);
blk00000003_blk00000d26 : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig00000761,
I1 => blk00000003_sig00000230,
I2 => blk00000003_sig00000cc6,
O => blk00000003_sig00000729
);
blk00000003_blk00000d25 : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig00000762,
I1 => blk00000003_sig00000231,
I2 => blk00000003_sig00000cc6,
O => blk00000003_sig0000072c
);
blk00000003_blk00000d24 : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig00000763,
I1 => blk00000003_sig00000232,
I2 => blk00000003_sig00000cc6,
O => blk00000003_sig0000072f
);
blk00000003_blk00000d23 : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig00000764,
I1 => blk00000003_sig00000233,
I2 => blk00000003_sig00000cc6,
O => blk00000003_sig00000732
);
blk00000003_blk00000d22 : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig00000765,
I1 => blk00000003_sig00000234,
I2 => blk00000003_sig00000cc6,
O => blk00000003_sig00000735
);
blk00000003_blk00000d21 : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig00000766,
I1 => blk00000003_sig00000235,
I2 => blk00000003_sig00000cc6,
O => blk00000003_sig00000738
);
blk00000003_blk00000d20 : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig00000767,
I1 => blk00000003_sig00000236,
I2 => blk00000003_sig00000cc6,
O => blk00000003_sig0000073b
);
blk00000003_blk00000d1f : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig00000768,
I1 => blk00000003_sig00000237,
I2 => blk00000003_sig00000cc6,
O => blk00000003_sig0000073e
);
blk00000003_blk00000d1e : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig00000777,
I1 => blk00000003_sig00000241,
I2 => blk00000003_sig00000cc6,
O => blk00000003_sig00000775
);
blk00000003_blk00000d1d : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig00000703,
I1 => blk00000003_sig00000250,
I2 => blk00000003_sig00000cc7,
O => blk00000003_sig000006db
);
blk00000003_blk00000d1c : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig00000704,
I1 => blk00000003_sig00000251,
I2 => blk00000003_sig00000cc7,
O => blk00000003_sig000006de
);
blk00000003_blk00000d1b : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig00000705,
I1 => blk00000003_sig00000252,
I2 => blk00000003_sig00000cc7,
O => blk00000003_sig000006e1
);
blk00000003_blk00000d1a : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig00000706,
I1 => blk00000003_sig00000253,
I2 => blk00000003_sig00000cc7,
O => blk00000003_sig000006e4
);
blk00000003_blk00000d19 : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig00000707,
I1 => blk00000003_sig00000254,
I2 => blk00000003_sig00000cc7,
O => blk00000003_sig000006e7
);
blk00000003_blk00000d18 : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig00000708,
I1 => blk00000003_sig00000255,
I2 => blk00000003_sig00000cc7,
O => blk00000003_sig000006ea
);
blk00000003_blk00000d17 : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig00000709,
I1 => blk00000003_sig00000256,
I2 => blk00000003_sig00000cc7,
O => blk00000003_sig000006ed
);
blk00000003_blk00000d16 : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig0000070a,
I1 => blk00000003_sig00000257,
I2 => blk00000003_sig00000cc7,
O => blk00000003_sig000006f0
);
blk00000003_blk00000d15 : LUT2
generic map(
INIT => X"9"
)
port map (
I0 => blk00000003_sig0000070c,
I1 => blk00000003_sig00000cc7,
O => blk00000003_sig000006ae
);
blk00000003_blk00000d14 : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig000006f5,
I1 => blk00000003_sig00000242,
I2 => blk00000003_sig00000cc7,
O => blk00000003_sig000006b1
);
blk00000003_blk00000d13 : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig000006f6,
I1 => blk00000003_sig00000243,
I2 => blk00000003_sig00000cc7,
O => blk00000003_sig000006b4
);
blk00000003_blk00000d12 : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig000006f7,
I1 => blk00000003_sig00000244,
I2 => blk00000003_sig00000cc7,
O => blk00000003_sig000006b7
);
blk00000003_blk00000d11 : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig000006f8,
I1 => blk00000003_sig00000245,
I2 => blk00000003_sig00000cc7,
O => blk00000003_sig000006ba
);
blk00000003_blk00000d10 : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig0000070b,
I1 => blk00000003_sig00000258,
I2 => blk00000003_sig00000cc7,
O => blk00000003_sig000006f3
);
blk00000003_blk00000d0f : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig000006f9,
I1 => blk00000003_sig00000246,
I2 => blk00000003_sig00000cc7,
O => blk00000003_sig000006bd
);
blk00000003_blk00000d0e : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig000006fa,
I1 => blk00000003_sig00000247,
I2 => blk00000003_sig00000cc7,
O => blk00000003_sig000006c0
);
blk00000003_blk00000d0d : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig000006fb,
I1 => blk00000003_sig00000248,
I2 => blk00000003_sig00000cc7,
O => blk00000003_sig000006c3
);
blk00000003_blk00000d0c : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig000006fc,
I1 => blk00000003_sig00000249,
I2 => blk00000003_sig00000cc7,
O => blk00000003_sig000006c6
);
blk00000003_blk00000d0b : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig000006fd,
I1 => blk00000003_sig0000024a,
I2 => blk00000003_sig00000cc7,
O => blk00000003_sig000006c9
);
blk00000003_blk00000d0a : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig000006fe,
I1 => blk00000003_sig0000024b,
I2 => blk00000003_sig00000cc7,
O => blk00000003_sig000006cc
);
blk00000003_blk00000d09 : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig000006ff,
I1 => blk00000003_sig0000024c,
I2 => blk00000003_sig00000cc7,
O => blk00000003_sig000006cf
);
blk00000003_blk00000d08 : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig00000700,
I1 => blk00000003_sig0000024d,
I2 => blk00000003_sig00000cc7,
O => blk00000003_sig000006d2
);
blk00000003_blk00000d07 : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig00000701,
I1 => blk00000003_sig0000024e,
I2 => blk00000003_sig00000cc7,
O => blk00000003_sig000006d5
);
blk00000003_blk00000d06 : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig00000702,
I1 => blk00000003_sig0000024f,
I2 => blk00000003_sig00000cc7,
O => blk00000003_sig000006d8
);
blk00000003_blk00000d05 : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig00000711,
I1 => blk00000003_sig00000259,
I2 => blk00000003_sig00000cc7,
O => blk00000003_sig0000070f
);
blk00000003_blk00000d04 : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig0000069d,
I1 => blk00000003_sig00000268,
I2 => blk00000003_sig00000cc8,
O => blk00000003_sig00000675
);
blk00000003_blk00000d03 : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig0000069e,
I1 => blk00000003_sig00000269,
I2 => blk00000003_sig00000cc8,
O => blk00000003_sig00000678
);
blk00000003_blk00000d02 : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig0000069f,
I1 => blk00000003_sig0000026a,
I2 => blk00000003_sig00000cc8,
O => blk00000003_sig0000067b
);
blk00000003_blk00000d01 : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig000006a0,
I1 => blk00000003_sig0000026b,
I2 => blk00000003_sig00000cc8,
O => blk00000003_sig0000067e
);
blk00000003_blk00000d00 : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig000006a1,
I1 => blk00000003_sig0000026c,
I2 => blk00000003_sig00000cc8,
O => blk00000003_sig00000681
);
blk00000003_blk00000cff : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig000006a2,
I1 => blk00000003_sig0000026d,
I2 => blk00000003_sig00000cc8,
O => blk00000003_sig00000684
);
blk00000003_blk00000cfe : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig000006a3,
I1 => blk00000003_sig0000026e,
I2 => blk00000003_sig00000cc8,
O => blk00000003_sig00000687
);
blk00000003_blk00000cfd : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig000006a4,
I1 => blk00000003_sig0000026f,
I2 => blk00000003_sig00000cc8,
O => blk00000003_sig0000068a
);
blk00000003_blk00000cfc : LUT2
generic map(
INIT => X"9"
)
port map (
I0 => blk00000003_sig000006a6,
I1 => blk00000003_sig00000cc8,
O => blk00000003_sig00000648
);
blk00000003_blk00000cfb : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig0000068f,
I1 => blk00000003_sig0000025a,
I2 => blk00000003_sig00000cc8,
O => blk00000003_sig0000064b
);
blk00000003_blk00000cfa : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig00000690,
I1 => blk00000003_sig0000025b,
I2 => blk00000003_sig00000cc8,
O => blk00000003_sig0000064e
);
blk00000003_blk00000cf9 : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig00000691,
I1 => blk00000003_sig0000025c,
I2 => blk00000003_sig00000cc8,
O => blk00000003_sig00000651
);
blk00000003_blk00000cf8 : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig00000692,
I1 => blk00000003_sig0000025d,
I2 => blk00000003_sig00000cc8,
O => blk00000003_sig00000654
);
blk00000003_blk00000cf7 : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig000006a5,
I1 => blk00000003_sig00000270,
I2 => blk00000003_sig00000cc8,
O => blk00000003_sig0000068d
);
blk00000003_blk00000cf6 : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig00000693,
I1 => blk00000003_sig0000025e,
I2 => blk00000003_sig00000cc8,
O => blk00000003_sig00000657
);
blk00000003_blk00000cf5 : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig00000694,
I1 => blk00000003_sig0000025f,
I2 => blk00000003_sig00000cc8,
O => blk00000003_sig0000065a
);
blk00000003_blk00000cf4 : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig00000695,
I1 => blk00000003_sig00000260,
I2 => blk00000003_sig00000cc8,
O => blk00000003_sig0000065d
);
blk00000003_blk00000cf3 : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig00000696,
I1 => blk00000003_sig00000261,
I2 => blk00000003_sig00000cc8,
O => blk00000003_sig00000660
);
blk00000003_blk00000cf2 : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig00000697,
I1 => blk00000003_sig00000262,
I2 => blk00000003_sig00000cc8,
O => blk00000003_sig00000663
);
blk00000003_blk00000cf1 : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig00000698,
I1 => blk00000003_sig00000263,
I2 => blk00000003_sig00000cc8,
O => blk00000003_sig00000666
);
blk00000003_blk00000cf0 : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig00000699,
I1 => blk00000003_sig00000264,
I2 => blk00000003_sig00000cc8,
O => blk00000003_sig00000669
);
blk00000003_blk00000cef : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig0000069a,
I1 => blk00000003_sig00000265,
I2 => blk00000003_sig00000cc8,
O => blk00000003_sig0000066c
);
blk00000003_blk00000cee : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig0000069b,
I1 => blk00000003_sig00000266,
I2 => blk00000003_sig00000cc8,
O => blk00000003_sig0000066f
);
blk00000003_blk00000ced : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig0000069c,
I1 => blk00000003_sig00000267,
I2 => blk00000003_sig00000cc8,
O => blk00000003_sig00000672
);
blk00000003_blk00000cec : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig000006ab,
I1 => blk00000003_sig00000271,
I2 => blk00000003_sig00000cc8,
O => blk00000003_sig000006a9
);
blk00000003_blk00000ceb : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig00000637,
I1 => blk00000003_sig00000280,
I2 => blk00000003_sig00000086,
O => blk00000003_sig0000060f
);
blk00000003_blk00000cea : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig00000638,
I1 => blk00000003_sig00000281,
I2 => blk00000003_sig00000086,
O => blk00000003_sig00000612
);
blk00000003_blk00000ce9 : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig00000639,
I1 => blk00000003_sig00000282,
I2 => blk00000003_sig00000086,
O => blk00000003_sig00000615
);
blk00000003_blk00000ce8 : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig0000063a,
I1 => blk00000003_sig00000283,
I2 => blk00000003_sig00000086,
O => blk00000003_sig00000618
);
blk00000003_blk00000ce7 : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig0000063b,
I1 => blk00000003_sig00000284,
I2 => blk00000003_sig00000086,
O => blk00000003_sig0000061b
);
blk00000003_blk00000ce6 : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig0000063c,
I1 => blk00000003_sig00000285,
I2 => blk00000003_sig00000086,
O => blk00000003_sig0000061e
);
blk00000003_blk00000ce5 : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig0000063d,
I1 => blk00000003_sig00000286,
I2 => blk00000003_sig00000086,
O => blk00000003_sig00000621
);
blk00000003_blk00000ce4 : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig0000063e,
I1 => blk00000003_sig00000287,
I2 => blk00000003_sig00000086,
O => blk00000003_sig00000624
);
blk00000003_blk00000ce3 : LUT2
generic map(
INIT => X"9"
)
port map (
I0 => blk00000003_sig00000640,
I1 => blk00000003_sig00000086,
O => blk00000003_sig000005e2
);
blk00000003_blk00000ce2 : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig00000629,
I1 => blk00000003_sig00000272,
I2 => blk00000003_sig00000086,
O => blk00000003_sig000005e5
);
blk00000003_blk00000ce1 : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig0000062a,
I1 => blk00000003_sig00000273,
I2 => blk00000003_sig00000086,
O => blk00000003_sig000005e8
);
blk00000003_blk00000ce0 : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig0000062b,
I1 => blk00000003_sig00000274,
I2 => blk00000003_sig00000086,
O => blk00000003_sig000005eb
);
blk00000003_blk00000cdf : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig0000062c,
I1 => blk00000003_sig00000275,
I2 => blk00000003_sig00000086,
O => blk00000003_sig000005ee
);
blk00000003_blk00000cde : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig0000063f,
I1 => blk00000003_sig00000288,
I2 => blk00000003_sig00000086,
O => blk00000003_sig00000627
);
blk00000003_blk00000cdd : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig0000062d,
I1 => blk00000003_sig00000276,
I2 => blk00000003_sig00000086,
O => blk00000003_sig000005f1
);
blk00000003_blk00000cdc : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig0000062e,
I1 => blk00000003_sig00000277,
I2 => blk00000003_sig00000086,
O => blk00000003_sig000005f4
);
blk00000003_blk00000cdb : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig0000062f,
I1 => blk00000003_sig00000278,
I2 => blk00000003_sig00000086,
O => blk00000003_sig000005f7
);
blk00000003_blk00000cda : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig00000630,
I1 => blk00000003_sig00000279,
I2 => blk00000003_sig00000086,
O => blk00000003_sig000005fa
);
blk00000003_blk00000cd9 : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig00000631,
I1 => blk00000003_sig0000027a,
I2 => blk00000003_sig00000086,
O => blk00000003_sig000005fd
);
blk00000003_blk00000cd8 : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig00000632,
I1 => blk00000003_sig0000027b,
I2 => blk00000003_sig00000086,
O => blk00000003_sig00000600
);
blk00000003_blk00000cd7 : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig00000633,
I1 => blk00000003_sig0000027c,
I2 => blk00000003_sig00000086,
O => blk00000003_sig00000603
);
blk00000003_blk00000cd6 : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig00000634,
I1 => blk00000003_sig0000027d,
I2 => blk00000003_sig00000086,
O => blk00000003_sig00000606
);
blk00000003_blk00000cd5 : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig00000635,
I1 => blk00000003_sig0000027e,
I2 => blk00000003_sig00000086,
O => blk00000003_sig00000609
);
blk00000003_blk00000cd4 : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig00000636,
I1 => blk00000003_sig0000027f,
I2 => blk00000003_sig00000086,
O => blk00000003_sig0000060c
);
blk00000003_blk00000cd3 : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig00000645,
I1 => blk00000003_sig00000289,
I2 => blk00000003_sig00000086,
O => blk00000003_sig00000643
);
blk00000003_blk00000cd2 : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig000005d1,
I1 => blk00000003_sig00000298,
I2 => blk00000003_sig00000094,
O => blk00000003_sig000005a9
);
blk00000003_blk00000cd1 : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig000005d2,
I1 => blk00000003_sig00000299,
I2 => blk00000003_sig00000094,
O => blk00000003_sig000005ac
);
blk00000003_blk00000cd0 : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig000005d3,
I1 => blk00000003_sig0000029a,
I2 => blk00000003_sig00000094,
O => blk00000003_sig000005af
);
blk00000003_blk00000ccf : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig000005d4,
I1 => blk00000003_sig0000029b,
I2 => blk00000003_sig00000094,
O => blk00000003_sig000005b2
);
blk00000003_blk00000cce : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig000005d5,
I1 => blk00000003_sig0000029c,
I2 => blk00000003_sig00000094,
O => blk00000003_sig000005b5
);
blk00000003_blk00000ccd : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig000005d6,
I1 => blk00000003_sig0000029d,
I2 => blk00000003_sig00000094,
O => blk00000003_sig000005b8
);
blk00000003_blk00000ccc : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig000005d7,
I1 => blk00000003_sig0000029e,
I2 => blk00000003_sig00000094,
O => blk00000003_sig000005bb
);
blk00000003_blk00000ccb : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig000005d8,
I1 => blk00000003_sig0000029f,
I2 => blk00000003_sig00000094,
O => blk00000003_sig000005be
);
blk00000003_blk00000cca : LUT2
generic map(
INIT => X"9"
)
port map (
I0 => blk00000003_sig000005da,
I1 => blk00000003_sig00000094,
O => blk00000003_sig0000057c
);
blk00000003_blk00000cc9 : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig000005c3,
I1 => blk00000003_sig0000028a,
I2 => blk00000003_sig00000094,
O => blk00000003_sig0000057f
);
blk00000003_blk00000cc8 : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig000005c4,
I1 => blk00000003_sig0000028b,
I2 => blk00000003_sig00000094,
O => blk00000003_sig00000582
);
blk00000003_blk00000cc7 : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig000005c5,
I1 => blk00000003_sig0000028c,
I2 => blk00000003_sig00000094,
O => blk00000003_sig00000585
);
blk00000003_blk00000cc6 : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig000005c6,
I1 => blk00000003_sig0000028d,
I2 => blk00000003_sig00000094,
O => blk00000003_sig00000588
);
blk00000003_blk00000cc5 : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig000005d9,
I1 => blk00000003_sig000002a0,
I2 => blk00000003_sig00000094,
O => blk00000003_sig000005c1
);
blk00000003_blk00000cc4 : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig000005c7,
I1 => blk00000003_sig0000028e,
I2 => blk00000003_sig00000094,
O => blk00000003_sig0000058b
);
blk00000003_blk00000cc3 : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig000005c8,
I1 => blk00000003_sig0000028f,
I2 => blk00000003_sig00000094,
O => blk00000003_sig0000058e
);
blk00000003_blk00000cc2 : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig000005c9,
I1 => blk00000003_sig00000290,
I2 => blk00000003_sig00000094,
O => blk00000003_sig00000591
);
blk00000003_blk00000cc1 : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig000005ca,
I1 => blk00000003_sig00000291,
I2 => blk00000003_sig00000094,
O => blk00000003_sig00000594
);
blk00000003_blk00000cc0 : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig000005cb,
I1 => blk00000003_sig00000292,
I2 => blk00000003_sig00000094,
O => blk00000003_sig00000597
);
blk00000003_blk00000cbf : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig000005cc,
I1 => blk00000003_sig00000293,
I2 => blk00000003_sig00000094,
O => blk00000003_sig0000059a
);
blk00000003_blk00000cbe : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig000005cd,
I1 => blk00000003_sig00000294,
I2 => blk00000003_sig00000094,
O => blk00000003_sig0000059d
);
blk00000003_blk00000cbd : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig000005ce,
I1 => blk00000003_sig00000295,
I2 => blk00000003_sig00000094,
O => blk00000003_sig000005a0
);
blk00000003_blk00000cbc : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig000005cf,
I1 => blk00000003_sig00000296,
I2 => blk00000003_sig00000094,
O => blk00000003_sig000005a3
);
blk00000003_blk00000cbb : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig000005d0,
I1 => blk00000003_sig00000297,
I2 => blk00000003_sig00000094,
O => blk00000003_sig000005a6
);
blk00000003_blk00000cba : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig000005df,
I1 => blk00000003_sig000002a1,
I2 => blk00000003_sig00000094,
O => blk00000003_sig000005dd
);
blk00000003_blk00000cb9 : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig0000056b,
I1 => blk00000003_sig000002b0,
I2 => blk00000003_sig0000009a,
O => blk00000003_sig00000543
);
blk00000003_blk00000cb8 : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig0000056c,
I1 => blk00000003_sig000002b1,
I2 => blk00000003_sig0000009a,
O => blk00000003_sig00000546
);
blk00000003_blk00000cb7 : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig0000056d,
I1 => blk00000003_sig000002b2,
I2 => blk00000003_sig0000009a,
O => blk00000003_sig00000549
);
blk00000003_blk00000cb6 : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig0000056e,
I1 => blk00000003_sig000002b3,
I2 => blk00000003_sig0000009a,
O => blk00000003_sig0000054c
);
blk00000003_blk00000cb5 : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig0000056f,
I1 => blk00000003_sig000002b4,
I2 => blk00000003_sig0000009a,
O => blk00000003_sig0000054f
);
blk00000003_blk00000cb4 : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig00000570,
I1 => blk00000003_sig000002b5,
I2 => blk00000003_sig0000009a,
O => blk00000003_sig00000552
);
blk00000003_blk00000cb3 : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig00000571,
I1 => blk00000003_sig000002b6,
I2 => blk00000003_sig0000009a,
O => blk00000003_sig00000555
);
blk00000003_blk00000cb2 : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig00000572,
I1 => blk00000003_sig000002b7,
I2 => blk00000003_sig0000009a,
O => blk00000003_sig00000558
);
blk00000003_blk00000cb1 : LUT2
generic map(
INIT => X"9"
)
port map (
I0 => blk00000003_sig00000574,
I1 => blk00000003_sig0000009a,
O => blk00000003_sig00000516
);
blk00000003_blk00000cb0 : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig0000055d,
I1 => blk00000003_sig000002a2,
I2 => blk00000003_sig0000009a,
O => blk00000003_sig00000519
);
blk00000003_blk00000caf : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig0000055e,
I1 => blk00000003_sig000002a3,
I2 => blk00000003_sig0000009a,
O => blk00000003_sig0000051c
);
blk00000003_blk00000cae : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig0000055f,
I1 => blk00000003_sig000002a4,
I2 => blk00000003_sig0000009a,
O => blk00000003_sig0000051f
);
blk00000003_blk00000cad : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig00000560,
I1 => blk00000003_sig000002a5,
I2 => blk00000003_sig0000009a,
O => blk00000003_sig00000522
);
blk00000003_blk00000cac : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig00000573,
I1 => blk00000003_sig000002b8,
I2 => blk00000003_sig0000009a,
O => blk00000003_sig0000055b
);
blk00000003_blk00000cab : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig00000561,
I1 => blk00000003_sig000002a6,
I2 => blk00000003_sig0000009a,
O => blk00000003_sig00000525
);
blk00000003_blk00000caa : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig00000562,
I1 => blk00000003_sig000002a7,
I2 => blk00000003_sig0000009a,
O => blk00000003_sig00000528
);
blk00000003_blk00000ca9 : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig00000563,
I1 => blk00000003_sig000002a8,
I2 => blk00000003_sig0000009a,
O => blk00000003_sig0000052b
);
blk00000003_blk00000ca8 : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig00000564,
I1 => blk00000003_sig000002a9,
I2 => blk00000003_sig0000009a,
O => blk00000003_sig0000052e
);
blk00000003_blk00000ca7 : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig00000565,
I1 => blk00000003_sig000002aa,
I2 => blk00000003_sig0000009a,
O => blk00000003_sig00000531
);
blk00000003_blk00000ca6 : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig00000566,
I1 => blk00000003_sig000002ab,
I2 => blk00000003_sig0000009a,
O => blk00000003_sig00000534
);
blk00000003_blk00000ca5 : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig00000567,
I1 => blk00000003_sig000002ac,
I2 => blk00000003_sig0000009a,
O => blk00000003_sig00000537
);
blk00000003_blk00000ca4 : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig00000568,
I1 => blk00000003_sig000002ad,
I2 => blk00000003_sig0000009a,
O => blk00000003_sig0000053a
);
blk00000003_blk00000ca3 : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig00000569,
I1 => blk00000003_sig000002ae,
I2 => blk00000003_sig0000009a,
O => blk00000003_sig0000053d
);
blk00000003_blk00000ca2 : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig0000056a,
I1 => blk00000003_sig000002af,
I2 => blk00000003_sig0000009a,
O => blk00000003_sig00000540
);
blk00000003_blk00000ca1 : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig00000579,
I1 => blk00000003_sig000002b9,
I2 => blk00000003_sig0000009a,
O => blk00000003_sig00000577
);
blk00000003_blk00000ca0 : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig00000505,
I1 => blk00000003_sig000002c8,
I2 => blk00000003_sig0000009f,
O => blk00000003_sig000004dd
);
blk00000003_blk00000c9f : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig00000506,
I1 => blk00000003_sig000002c9,
I2 => blk00000003_sig0000009f,
O => blk00000003_sig000004e0
);
blk00000003_blk00000c9e : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig00000507,
I1 => blk00000003_sig000002ca,
I2 => blk00000003_sig0000009f,
O => blk00000003_sig000004e3
);
blk00000003_blk00000c9d : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig00000508,
I1 => blk00000003_sig000002cb,
I2 => blk00000003_sig0000009f,
O => blk00000003_sig000004e6
);
blk00000003_blk00000c9c : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig00000509,
I1 => blk00000003_sig000002cc,
I2 => blk00000003_sig0000009f,
O => blk00000003_sig000004e9
);
blk00000003_blk00000c9b : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig0000050a,
I1 => blk00000003_sig000002cd,
I2 => blk00000003_sig0000009f,
O => blk00000003_sig000004ec
);
blk00000003_blk00000c9a : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig0000050b,
I1 => blk00000003_sig000002ce,
I2 => blk00000003_sig0000009f,
O => blk00000003_sig000004ef
);
blk00000003_blk00000c99 : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig0000050c,
I1 => blk00000003_sig000002cf,
I2 => blk00000003_sig0000009f,
O => blk00000003_sig000004f2
);
blk00000003_blk00000c98 : LUT2
generic map(
INIT => X"9"
)
port map (
I0 => blk00000003_sig0000050e,
I1 => blk00000003_sig0000009f,
O => blk00000003_sig000004b0
);
blk00000003_blk00000c97 : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig000004f7,
I1 => blk00000003_sig000002ba,
I2 => blk00000003_sig0000009f,
O => blk00000003_sig000004b3
);
blk00000003_blk00000c96 : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig000004f8,
I1 => blk00000003_sig000002bb,
I2 => blk00000003_sig0000009f,
O => blk00000003_sig000004b6
);
blk00000003_blk00000c95 : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig000004f9,
I1 => blk00000003_sig000002bc,
I2 => blk00000003_sig0000009f,
O => blk00000003_sig000004b9
);
blk00000003_blk00000c94 : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig000004fa,
I1 => blk00000003_sig000002bd,
I2 => blk00000003_sig0000009f,
O => blk00000003_sig000004bc
);
blk00000003_blk00000c93 : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig0000050d,
I1 => blk00000003_sig000002d0,
I2 => blk00000003_sig0000009f,
O => blk00000003_sig000004f5
);
blk00000003_blk00000c92 : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig000004fb,
I1 => blk00000003_sig000002be,
I2 => blk00000003_sig0000009f,
O => blk00000003_sig000004bf
);
blk00000003_blk00000c91 : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig000004fc,
I1 => blk00000003_sig000002bf,
I2 => blk00000003_sig0000009f,
O => blk00000003_sig000004c2
);
blk00000003_blk00000c90 : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig000004fd,
I1 => blk00000003_sig000002c0,
I2 => blk00000003_sig0000009f,
O => blk00000003_sig000004c5
);
blk00000003_blk00000c8f : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig000004fe,
I1 => blk00000003_sig000002c1,
I2 => blk00000003_sig0000009f,
O => blk00000003_sig000004c8
);
blk00000003_blk00000c8e : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig000004ff,
I1 => blk00000003_sig000002c2,
I2 => blk00000003_sig0000009f,
O => blk00000003_sig000004cb
);
blk00000003_blk00000c8d : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig00000500,
I1 => blk00000003_sig000002c3,
I2 => blk00000003_sig0000009f,
O => blk00000003_sig000004ce
);
blk00000003_blk00000c8c : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig00000501,
I1 => blk00000003_sig000002c4,
I2 => blk00000003_sig0000009f,
O => blk00000003_sig000004d1
);
blk00000003_blk00000c8b : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig00000502,
I1 => blk00000003_sig000002c5,
I2 => blk00000003_sig0000009f,
O => blk00000003_sig000004d4
);
blk00000003_blk00000c8a : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig00000503,
I1 => blk00000003_sig000002c6,
I2 => blk00000003_sig0000009f,
O => blk00000003_sig000004d7
);
blk00000003_blk00000c89 : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig00000504,
I1 => blk00000003_sig000002c7,
I2 => blk00000003_sig0000009f,
O => blk00000003_sig000004da
);
blk00000003_blk00000c88 : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig00000513,
I1 => blk00000003_sig000002d1,
I2 => blk00000003_sig0000009f,
O => blk00000003_sig00000511
);
blk00000003_blk00000c87 : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig0000049f,
I1 => blk00000003_sig000002e0,
I2 => blk00000003_sig000000a3,
O => blk00000003_sig00000477
);
blk00000003_blk00000c86 : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig000004a0,
I1 => blk00000003_sig000002e1,
I2 => blk00000003_sig000000a3,
O => blk00000003_sig0000047a
);
blk00000003_blk00000c85 : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig000004a1,
I1 => blk00000003_sig000002e2,
I2 => blk00000003_sig000000a3,
O => blk00000003_sig0000047d
);
blk00000003_blk00000c84 : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig000004a2,
I1 => blk00000003_sig000002e3,
I2 => blk00000003_sig000000a3,
O => blk00000003_sig00000480
);
blk00000003_blk00000c83 : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig000004a3,
I1 => blk00000003_sig000002e4,
I2 => blk00000003_sig000000a3,
O => blk00000003_sig00000483
);
blk00000003_blk00000c82 : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig000004a4,
I1 => blk00000003_sig000002e5,
I2 => blk00000003_sig000000a3,
O => blk00000003_sig00000486
);
blk00000003_blk00000c81 : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig000004a5,
I1 => blk00000003_sig000002e6,
I2 => blk00000003_sig000000a3,
O => blk00000003_sig00000489
);
blk00000003_blk00000c80 : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig000004a6,
I1 => blk00000003_sig000002e7,
I2 => blk00000003_sig000000a3,
O => blk00000003_sig0000048c
);
blk00000003_blk00000c7f : LUT2
generic map(
INIT => X"9"
)
port map (
I0 => blk00000003_sig000004a8,
I1 => blk00000003_sig000000a3,
O => blk00000003_sig0000044a
);
blk00000003_blk00000c7e : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig00000491,
I1 => blk00000003_sig000002d2,
I2 => blk00000003_sig000000a3,
O => blk00000003_sig0000044d
);
blk00000003_blk00000c7d : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig00000492,
I1 => blk00000003_sig000002d3,
I2 => blk00000003_sig000000a3,
O => blk00000003_sig00000450
);
blk00000003_blk00000c7c : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig00000493,
I1 => blk00000003_sig000002d4,
I2 => blk00000003_sig000000a3,
O => blk00000003_sig00000453
);
blk00000003_blk00000c7b : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig00000494,
I1 => blk00000003_sig000002d5,
I2 => blk00000003_sig000000a3,
O => blk00000003_sig00000456
);
blk00000003_blk00000c7a : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig000004a7,
I1 => blk00000003_sig000002e8,
I2 => blk00000003_sig000000a3,
O => blk00000003_sig0000048f
);
blk00000003_blk00000c79 : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig00000495,
I1 => blk00000003_sig000002d6,
I2 => blk00000003_sig000000a3,
O => blk00000003_sig00000459
);
blk00000003_blk00000c78 : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig00000496,
I1 => blk00000003_sig000002d7,
I2 => blk00000003_sig000000a3,
O => blk00000003_sig0000045c
);
blk00000003_blk00000c77 : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig00000497,
I1 => blk00000003_sig000002d8,
I2 => blk00000003_sig000000a3,
O => blk00000003_sig0000045f
);
blk00000003_blk00000c76 : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig00000498,
I1 => blk00000003_sig000002d9,
I2 => blk00000003_sig000000a3,
O => blk00000003_sig00000462
);
blk00000003_blk00000c75 : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig00000499,
I1 => blk00000003_sig000002da,
I2 => blk00000003_sig000000a3,
O => blk00000003_sig00000465
);
blk00000003_blk00000c74 : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig0000049a,
I1 => blk00000003_sig000002db,
I2 => blk00000003_sig000000a3,
O => blk00000003_sig00000468
);
blk00000003_blk00000c73 : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig0000049b,
I1 => blk00000003_sig000002dc,
I2 => blk00000003_sig000000a3,
O => blk00000003_sig0000046b
);
blk00000003_blk00000c72 : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig0000049c,
I1 => blk00000003_sig000002dd,
I2 => blk00000003_sig000000a3,
O => blk00000003_sig0000046e
);
blk00000003_blk00000c71 : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig0000049d,
I1 => blk00000003_sig000002de,
I2 => blk00000003_sig000000a3,
O => blk00000003_sig00000471
);
blk00000003_blk00000c70 : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig0000049e,
I1 => blk00000003_sig000002df,
I2 => blk00000003_sig000000a3,
O => blk00000003_sig00000474
);
blk00000003_blk00000c6f : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig000004ad,
I1 => blk00000003_sig000002e9,
I2 => blk00000003_sig000000a3,
O => blk00000003_sig000004ab
);
blk00000003_blk00000c6e : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig00000439,
I1 => blk00000003_sig000002f8,
I2 => blk00000003_sig000000a6,
O => blk00000003_sig00000411
);
blk00000003_blk00000c6d : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig0000043a,
I1 => blk00000003_sig000002f9,
I2 => blk00000003_sig000000a6,
O => blk00000003_sig00000414
);
blk00000003_blk00000c6c : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig0000043b,
I1 => blk00000003_sig000002fa,
I2 => blk00000003_sig000000a6,
O => blk00000003_sig00000417
);
blk00000003_blk00000c6b : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig0000043c,
I1 => blk00000003_sig000002fb,
I2 => blk00000003_sig000000a6,
O => blk00000003_sig0000041a
);
blk00000003_blk00000c6a : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig0000043d,
I1 => blk00000003_sig000002fc,
I2 => blk00000003_sig000000a6,
O => blk00000003_sig0000041d
);
blk00000003_blk00000c69 : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig0000043e,
I1 => blk00000003_sig000002fd,
I2 => blk00000003_sig000000a6,
O => blk00000003_sig00000420
);
blk00000003_blk00000c68 : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig0000043f,
I1 => blk00000003_sig000002fe,
I2 => blk00000003_sig000000a6,
O => blk00000003_sig00000423
);
blk00000003_blk00000c67 : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig00000440,
I1 => blk00000003_sig000002ff,
I2 => blk00000003_sig000000a6,
O => blk00000003_sig00000426
);
blk00000003_blk00000c66 : LUT2
generic map(
INIT => X"9"
)
port map (
I0 => blk00000003_sig00000442,
I1 => blk00000003_sig000000a6,
O => blk00000003_sig000003e4
);
blk00000003_blk00000c65 : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig0000042b,
I1 => blk00000003_sig000002ea,
I2 => blk00000003_sig000000a6,
O => blk00000003_sig000003e7
);
blk00000003_blk00000c64 : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig0000042c,
I1 => blk00000003_sig000002eb,
I2 => blk00000003_sig000000a6,
O => blk00000003_sig000003ea
);
blk00000003_blk00000c63 : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig0000042d,
I1 => blk00000003_sig000002ec,
I2 => blk00000003_sig000000a6,
O => blk00000003_sig000003ed
);
blk00000003_blk00000c62 : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig0000042e,
I1 => blk00000003_sig000002ed,
I2 => blk00000003_sig000000a6,
O => blk00000003_sig000003f0
);
blk00000003_blk00000c61 : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig00000441,
I1 => blk00000003_sig00000300,
I2 => blk00000003_sig000000a6,
O => blk00000003_sig00000429
);
blk00000003_blk00000c60 : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig0000042f,
I1 => blk00000003_sig000002ee,
I2 => blk00000003_sig000000a6,
O => blk00000003_sig000003f3
);
blk00000003_blk00000c5f : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig00000430,
I1 => blk00000003_sig000002ef,
I2 => blk00000003_sig000000a6,
O => blk00000003_sig000003f6
);
blk00000003_blk00000c5e : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig00000431,
I1 => blk00000003_sig000002f0,
I2 => blk00000003_sig000000a6,
O => blk00000003_sig000003f9
);
blk00000003_blk00000c5d : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig00000432,
I1 => blk00000003_sig000002f1,
I2 => blk00000003_sig000000a6,
O => blk00000003_sig000003fc
);
blk00000003_blk00000c5c : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig00000433,
I1 => blk00000003_sig000002f2,
I2 => blk00000003_sig000000a6,
O => blk00000003_sig000003ff
);
blk00000003_blk00000c5b : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig00000434,
I1 => blk00000003_sig000002f3,
I2 => blk00000003_sig000000a6,
O => blk00000003_sig00000402
);
blk00000003_blk00000c5a : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig00000435,
I1 => blk00000003_sig000002f4,
I2 => blk00000003_sig000000a6,
O => blk00000003_sig00000405
);
blk00000003_blk00000c59 : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig00000436,
I1 => blk00000003_sig000002f5,
I2 => blk00000003_sig000000a6,
O => blk00000003_sig00000408
);
blk00000003_blk00000c58 : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig00000437,
I1 => blk00000003_sig000002f6,
I2 => blk00000003_sig000000a6,
O => blk00000003_sig0000040b
);
blk00000003_blk00000c57 : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig00000438,
I1 => blk00000003_sig000002f7,
I2 => blk00000003_sig000000a6,
O => blk00000003_sig0000040e
);
blk00000003_blk00000c56 : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig00000447,
I1 => blk00000003_sig00000301,
I2 => blk00000003_sig000000a6,
O => blk00000003_sig00000445
);
blk00000003_blk00000c55 : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig000003d3,
I1 => blk00000003_sig00000310,
I2 => blk00000003_sig000000a8,
O => blk00000003_sig000003ab
);
blk00000003_blk00000c54 : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig000003d4,
I1 => blk00000003_sig00000311,
I2 => blk00000003_sig000000a8,
O => blk00000003_sig000003ae
);
blk00000003_blk00000c53 : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig000003d5,
I1 => blk00000003_sig00000312,
I2 => blk00000003_sig000000a8,
O => blk00000003_sig000003b1
);
blk00000003_blk00000c52 : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig000003d6,
I1 => blk00000003_sig00000313,
I2 => blk00000003_sig000000a8,
O => blk00000003_sig000003b4
);
blk00000003_blk00000c51 : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig000003d7,
I1 => blk00000003_sig00000314,
I2 => blk00000003_sig000000a8,
O => blk00000003_sig000003b7
);
blk00000003_blk00000c50 : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig000003d8,
I1 => blk00000003_sig00000315,
I2 => blk00000003_sig000000a8,
O => blk00000003_sig000003ba
);
blk00000003_blk00000c4f : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig000003d9,
I1 => blk00000003_sig00000316,
I2 => blk00000003_sig000000a8,
O => blk00000003_sig000003bd
);
blk00000003_blk00000c4e : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig000003da,
I1 => blk00000003_sig00000317,
I2 => blk00000003_sig000000a8,
O => blk00000003_sig000003c0
);
blk00000003_blk00000c4d : LUT2
generic map(
INIT => X"9"
)
port map (
I0 => blk00000003_sig000003dc,
I1 => blk00000003_sig000000a8,
O => blk00000003_sig0000037e
);
blk00000003_blk00000c4c : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig000003c5,
I1 => blk00000003_sig00000302,
I2 => blk00000003_sig000000a8,
O => blk00000003_sig00000381
);
blk00000003_blk00000c4b : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig000003c6,
I1 => blk00000003_sig00000303,
I2 => blk00000003_sig000000a8,
O => blk00000003_sig00000384
);
blk00000003_blk00000c4a : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig000003c7,
I1 => blk00000003_sig00000304,
I2 => blk00000003_sig000000a8,
O => blk00000003_sig00000387
);
blk00000003_blk00000c49 : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig000003c8,
I1 => blk00000003_sig00000305,
I2 => blk00000003_sig000000a8,
O => blk00000003_sig0000038a
);
blk00000003_blk00000c48 : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig000003db,
I1 => blk00000003_sig00000318,
I2 => blk00000003_sig000000a8,
O => blk00000003_sig000003c3
);
blk00000003_blk00000c47 : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig000003c9,
I1 => blk00000003_sig00000306,
I2 => blk00000003_sig000000a8,
O => blk00000003_sig0000038d
);
blk00000003_blk00000c46 : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig000003ca,
I1 => blk00000003_sig00000307,
I2 => blk00000003_sig000000a8,
O => blk00000003_sig00000390
);
blk00000003_blk00000c45 : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig000003cb,
I1 => blk00000003_sig00000308,
I2 => blk00000003_sig000000a8,
O => blk00000003_sig00000393
);
blk00000003_blk00000c44 : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig000003cc,
I1 => blk00000003_sig00000309,
I2 => blk00000003_sig000000a8,
O => blk00000003_sig00000396
);
blk00000003_blk00000c43 : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig000003cd,
I1 => blk00000003_sig0000030a,
I2 => blk00000003_sig000000a8,
O => blk00000003_sig00000399
);
blk00000003_blk00000c42 : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig000003ce,
I1 => blk00000003_sig0000030b,
I2 => blk00000003_sig000000a8,
O => blk00000003_sig0000039c
);
blk00000003_blk00000c41 : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig000003cf,
I1 => blk00000003_sig0000030c,
I2 => blk00000003_sig000000a8,
O => blk00000003_sig0000039f
);
blk00000003_blk00000c40 : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig000003d0,
I1 => blk00000003_sig0000030d,
I2 => blk00000003_sig000000a8,
O => blk00000003_sig000003a2
);
blk00000003_blk00000c3f : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig000003d1,
I1 => blk00000003_sig0000030e,
I2 => blk00000003_sig000000a8,
O => blk00000003_sig000003a5
);
blk00000003_blk00000c3e : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig000003d2,
I1 => blk00000003_sig0000030f,
I2 => blk00000003_sig000000a8,
O => blk00000003_sig000003a8
);
blk00000003_blk00000c3d : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig000003e1,
I1 => blk00000003_sig00000319,
I2 => blk00000003_sig000000a8,
O => blk00000003_sig000003df
);
blk00000003_blk00000c3c : LUT2
generic map(
INIT => X"9"
)
port map (
I0 => blk00000003_sig000000c2,
I1 => blk00000003_sig00000331,
O => blk00000003_sig0000037a
);
blk00000003_blk00000c3b : LUT1
generic map(
INIT => X"1"
)
port map (
I0 => blk00000003_sig00000ca0,
O => blk00000003_sig000000c1
);
blk00000003_blk00000c3a : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000f03,
Q => fractional_3(0)
);
blk00000003_blk00000c39 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000efd,
Q => fractional_3(1)
);
blk00000003_blk00000c38 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000ef9,
Q => fractional_3(2)
);
blk00000003_blk00000c37 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000ef5,
Q => fractional_3(3)
);
blk00000003_blk00000c36 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000ef1,
Q => fractional_3(4)
);
blk00000003_blk00000c35 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000eed,
Q => fractional_3(5)
);
blk00000003_blk00000c34 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000ee9,
Q => fractional_3(6)
);
blk00000003_blk00000c33 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000ee5,
Q => fractional_3(7)
);
blk00000003_blk00000c32 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000ee1,
Q => fractional_3(8)
);
blk00000003_blk00000c31 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000edd,
Q => fractional_3(9)
);
blk00000003_blk00000c30 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000ed9,
Q => fractional_3(10)
);
blk00000003_blk00000c2f : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000ed5,
Q => fractional_3(11)
);
blk00000003_blk00000c2e : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000ed1,
Q => fractional_3(12)
);
blk00000003_blk00000c2d : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000ecd,
Q => fractional_3(13)
);
blk00000003_blk00000c2c : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000ec9,
Q => fractional_3(14)
);
blk00000003_blk00000c2b : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000ec5,
Q => fractional_3(15)
);
blk00000003_blk00000c2a : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000ec1,
Q => fractional_3(16)
);
blk00000003_blk00000c29 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000ebd,
Q => fractional_3(17)
);
blk00000003_blk00000c28 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000eb9,
Q => fractional_3(18)
);
blk00000003_blk00000c27 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000eb5,
Q => fractional_3(19)
);
blk00000003_blk00000c26 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000eb1,
Q => fractional_3(20)
);
blk00000003_blk00000c25 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000ead,
Q => fractional_3(21)
);
blk00000003_blk00000c24 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000ea9,
Q => fractional_3(22)
);
blk00000003_blk00000c23 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000ea4,
Q => fractional_3(23)
);
blk00000003_blk00000c22 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000f01,
Q => blk00000003_sig00000f06
);
blk00000003_blk00000c21 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000f00,
Q => blk00000003_sig00000f05
);
blk00000003_blk00000c20 : MULT_AND
port map (
I0 => blk00000003_sig00000109,
I1 => blk00000003_sig00000ca0,
LO => blk00000003_sig00000f04
);
blk00000003_blk00000c1f : MULT_AND
port map (
I0 => blk00000003_sig00000107,
I1 => blk00000003_sig00000ca0,
LO => blk00000003_sig00000efe
);
blk00000003_blk00000c1e : MULT_AND
port map (
I0 => blk00000003_sig00000105,
I1 => blk00000003_sig00000ca0,
LO => blk00000003_sig00000efa
);
blk00000003_blk00000c1d : MULT_AND
port map (
I0 => blk00000003_sig00000103,
I1 => blk00000003_sig00000ca0,
LO => blk00000003_sig00000ef6
);
blk00000003_blk00000c1c : MULT_AND
port map (
I0 => blk00000003_sig00000101,
I1 => blk00000003_sig00000ca0,
LO => blk00000003_sig00000ef2
);
blk00000003_blk00000c1b : MULT_AND
port map (
I0 => blk00000003_sig000000ff,
I1 => blk00000003_sig00000ca0,
LO => blk00000003_sig00000eee
);
blk00000003_blk00000c1a : MULT_AND
port map (
I0 => blk00000003_sig000000fd,
I1 => blk00000003_sig00000ca0,
LO => blk00000003_sig00000eea
);
blk00000003_blk00000c19 : MULT_AND
port map (
I0 => blk00000003_sig000000fb,
I1 => blk00000003_sig00000ca0,
LO => blk00000003_sig00000ee6
);
blk00000003_blk00000c18 : MULT_AND
port map (
I0 => blk00000003_sig000000f9,
I1 => blk00000003_sig00000ca0,
LO => blk00000003_sig00000ee2
);
blk00000003_blk00000c17 : MULT_AND
port map (
I0 => blk00000003_sig000000f7,
I1 => blk00000003_sig00000ca0,
LO => blk00000003_sig00000ede
);
blk00000003_blk00000c16 : MULT_AND
port map (
I0 => blk00000003_sig000000f5,
I1 => blk00000003_sig00000ca0,
LO => blk00000003_sig00000eda
);
blk00000003_blk00000c15 : MULT_AND
port map (
I0 => blk00000003_sig000000f3,
I1 => blk00000003_sig00000ca0,
LO => blk00000003_sig00000ed6
);
blk00000003_blk00000c14 : MULT_AND
port map (
I0 => blk00000003_sig000000f1,
I1 => blk00000003_sig00000ca0,
LO => blk00000003_sig00000ed2
);
blk00000003_blk00000c13 : MULT_AND
port map (
I0 => blk00000003_sig000000ef,
I1 => blk00000003_sig00000ca0,
LO => blk00000003_sig00000ece
);
blk00000003_blk00000c12 : MULT_AND
port map (
I0 => blk00000003_sig000000ed,
I1 => blk00000003_sig00000ca0,
LO => blk00000003_sig00000eca
);
blk00000003_blk00000c11 : MULT_AND
port map (
I0 => blk00000003_sig000000eb,
I1 => blk00000003_sig00000ca0,
LO => blk00000003_sig00000ec6
);
blk00000003_blk00000c10 : MULT_AND
port map (
I0 => blk00000003_sig000000e9,
I1 => blk00000003_sig00000ca0,
LO => blk00000003_sig00000ec2
);
blk00000003_blk00000c0f : MULT_AND
port map (
I0 => blk00000003_sig000000e7,
I1 => blk00000003_sig00000ca0,
LO => blk00000003_sig00000ebe
);
blk00000003_blk00000c0e : MULT_AND
port map (
I0 => blk00000003_sig000000e5,
I1 => blk00000003_sig00000ca0,
LO => blk00000003_sig00000eba
);
blk00000003_blk00000c0d : MULT_AND
port map (
I0 => blk00000003_sig000000e3,
I1 => blk00000003_sig00000ca0,
LO => blk00000003_sig00000eb6
);
blk00000003_blk00000c0c : MULT_AND
port map (
I0 => blk00000003_sig000000e1,
I1 => blk00000003_sig00000ca0,
LO => blk00000003_sig00000eb2
);
blk00000003_blk00000c0b : MULT_AND
port map (
I0 => blk00000003_sig000000df,
I1 => blk00000003_sig00000ca0,
LO => blk00000003_sig00000eae
);
blk00000003_blk00000c0a : MULT_AND
port map (
I0 => blk00000003_sig000000dd,
I1 => blk00000003_sig00000ca0,
LO => blk00000003_sig00000eaa
);
blk00000003_blk00000c09 : MULT_AND
port map (
I0 => blk00000003_sig000000db,
I1 => blk00000003_sig00000ca0,
LO => blk00000003_sig00000ea5
);
blk00000003_blk00000c08 : MULT_AND
port map (
I0 => blk00000003_sig00000062,
I1 => blk00000003_sig00000ca0,
LO => blk00000003_sig00000eff
);
blk00000003_blk00000c07 : MUXCY
port map (
CI => blk00000003_sig00000062,
DI => blk00000003_sig00000f04,
S => blk00000003_sig00000f02,
O => blk00000003_sig00000efb
);
blk00000003_blk00000c06 : XORCY
port map (
CI => blk00000003_sig00000062,
LI => blk00000003_sig00000f02,
O => blk00000003_sig00000f03
);
blk00000003_blk00000c05 : XORCY
port map (
CI => blk00000003_sig00000ea6,
LI => blk00000003_sig00000062,
O => blk00000003_sig00000f01
);
blk00000003_blk00000c04 : MUXCY
port map (
CI => blk00000003_sig00000ea6,
DI => blk00000003_sig00000eff,
S => blk00000003_sig00000062,
O => blk00000003_sig00000f00
);
blk00000003_blk00000c03 : MUXCY
port map (
CI => blk00000003_sig00000efb,
DI => blk00000003_sig00000efe,
S => blk00000003_sig00000efc,
O => blk00000003_sig00000ef7
);
blk00000003_blk00000c02 : XORCY
port map (
CI => blk00000003_sig00000efb,
LI => blk00000003_sig00000efc,
O => blk00000003_sig00000efd
);
blk00000003_blk00000c01 : MUXCY
port map (
CI => blk00000003_sig00000ef7,
DI => blk00000003_sig00000efa,
S => blk00000003_sig00000ef8,
O => blk00000003_sig00000ef3
);
blk00000003_blk00000c00 : XORCY
port map (
CI => blk00000003_sig00000ef7,
LI => blk00000003_sig00000ef8,
O => blk00000003_sig00000ef9
);
blk00000003_blk00000bff : MUXCY
port map (
CI => blk00000003_sig00000ef3,
DI => blk00000003_sig00000ef6,
S => blk00000003_sig00000ef4,
O => blk00000003_sig00000eef
);
blk00000003_blk00000bfe : XORCY
port map (
CI => blk00000003_sig00000ef3,
LI => blk00000003_sig00000ef4,
O => blk00000003_sig00000ef5
);
blk00000003_blk00000bfd : MUXCY
port map (
CI => blk00000003_sig00000eef,
DI => blk00000003_sig00000ef2,
S => blk00000003_sig00000ef0,
O => blk00000003_sig00000eeb
);
blk00000003_blk00000bfc : XORCY
port map (
CI => blk00000003_sig00000eef,
LI => blk00000003_sig00000ef0,
O => blk00000003_sig00000ef1
);
blk00000003_blk00000bfb : MUXCY
port map (
CI => blk00000003_sig00000eeb,
DI => blk00000003_sig00000eee,
S => blk00000003_sig00000eec,
O => blk00000003_sig00000ee7
);
blk00000003_blk00000bfa : XORCY
port map (
CI => blk00000003_sig00000eeb,
LI => blk00000003_sig00000eec,
O => blk00000003_sig00000eed
);
blk00000003_blk00000bf9 : MUXCY
port map (
CI => blk00000003_sig00000ee7,
DI => blk00000003_sig00000eea,
S => blk00000003_sig00000ee8,
O => blk00000003_sig00000ee3
);
blk00000003_blk00000bf8 : XORCY
port map (
CI => blk00000003_sig00000ee7,
LI => blk00000003_sig00000ee8,
O => blk00000003_sig00000ee9
);
blk00000003_blk00000bf7 : MUXCY
port map (
CI => blk00000003_sig00000ee3,
DI => blk00000003_sig00000ee6,
S => blk00000003_sig00000ee4,
O => blk00000003_sig00000edf
);
blk00000003_blk00000bf6 : XORCY
port map (
CI => blk00000003_sig00000ee3,
LI => blk00000003_sig00000ee4,
O => blk00000003_sig00000ee5
);
blk00000003_blk00000bf5 : MUXCY
port map (
CI => blk00000003_sig00000edf,
DI => blk00000003_sig00000ee2,
S => blk00000003_sig00000ee0,
O => blk00000003_sig00000edb
);
blk00000003_blk00000bf4 : XORCY
port map (
CI => blk00000003_sig00000edf,
LI => blk00000003_sig00000ee0,
O => blk00000003_sig00000ee1
);
blk00000003_blk00000bf3 : MUXCY
port map (
CI => blk00000003_sig00000edb,
DI => blk00000003_sig00000ede,
S => blk00000003_sig00000edc,
O => blk00000003_sig00000ed7
);
blk00000003_blk00000bf2 : XORCY
port map (
CI => blk00000003_sig00000edb,
LI => blk00000003_sig00000edc,
O => blk00000003_sig00000edd
);
blk00000003_blk00000bf1 : MUXCY
port map (
CI => blk00000003_sig00000ed7,
DI => blk00000003_sig00000eda,
S => blk00000003_sig00000ed8,
O => blk00000003_sig00000ed3
);
blk00000003_blk00000bf0 : XORCY
port map (
CI => blk00000003_sig00000ed7,
LI => blk00000003_sig00000ed8,
O => blk00000003_sig00000ed9
);
blk00000003_blk00000bef : MUXCY
port map (
CI => blk00000003_sig00000ed3,
DI => blk00000003_sig00000ed6,
S => blk00000003_sig00000ed4,
O => blk00000003_sig00000ecf
);
blk00000003_blk00000bee : XORCY
port map (
CI => blk00000003_sig00000ed3,
LI => blk00000003_sig00000ed4,
O => blk00000003_sig00000ed5
);
blk00000003_blk00000bed : MUXCY
port map (
CI => blk00000003_sig00000ecf,
DI => blk00000003_sig00000ed2,
S => blk00000003_sig00000ed0,
O => blk00000003_sig00000ecb
);
blk00000003_blk00000bec : XORCY
port map (
CI => blk00000003_sig00000ecf,
LI => blk00000003_sig00000ed0,
O => blk00000003_sig00000ed1
);
blk00000003_blk00000beb : MUXCY
port map (
CI => blk00000003_sig00000ecb,
DI => blk00000003_sig00000ece,
S => blk00000003_sig00000ecc,
O => blk00000003_sig00000ec7
);
blk00000003_blk00000bea : XORCY
port map (
CI => blk00000003_sig00000ecb,
LI => blk00000003_sig00000ecc,
O => blk00000003_sig00000ecd
);
blk00000003_blk00000be9 : MUXCY
port map (
CI => blk00000003_sig00000ec7,
DI => blk00000003_sig00000eca,
S => blk00000003_sig00000ec8,
O => blk00000003_sig00000ec3
);
blk00000003_blk00000be8 : XORCY
port map (
CI => blk00000003_sig00000ec7,
LI => blk00000003_sig00000ec8,
O => blk00000003_sig00000ec9
);
blk00000003_blk00000be7 : MUXCY
port map (
CI => blk00000003_sig00000ec3,
DI => blk00000003_sig00000ec6,
S => blk00000003_sig00000ec4,
O => blk00000003_sig00000ebf
);
blk00000003_blk00000be6 : XORCY
port map (
CI => blk00000003_sig00000ec3,
LI => blk00000003_sig00000ec4,
O => blk00000003_sig00000ec5
);
blk00000003_blk00000be5 : MUXCY
port map (
CI => blk00000003_sig00000ebf,
DI => blk00000003_sig00000ec2,
S => blk00000003_sig00000ec0,
O => blk00000003_sig00000ebb
);
blk00000003_blk00000be4 : XORCY
port map (
CI => blk00000003_sig00000ebf,
LI => blk00000003_sig00000ec0,
O => blk00000003_sig00000ec1
);
blk00000003_blk00000be3 : MUXCY
port map (
CI => blk00000003_sig00000ebb,
DI => blk00000003_sig00000ebe,
S => blk00000003_sig00000ebc,
O => blk00000003_sig00000eb7
);
blk00000003_blk00000be2 : XORCY
port map (
CI => blk00000003_sig00000ebb,
LI => blk00000003_sig00000ebc,
O => blk00000003_sig00000ebd
);
blk00000003_blk00000be1 : MUXCY
port map (
CI => blk00000003_sig00000eb7,
DI => blk00000003_sig00000eba,
S => blk00000003_sig00000eb8,
O => blk00000003_sig00000eb3
);
blk00000003_blk00000be0 : XORCY
port map (
CI => blk00000003_sig00000eb7,
LI => blk00000003_sig00000eb8,
O => blk00000003_sig00000eb9
);
blk00000003_blk00000bdf : MUXCY
port map (
CI => blk00000003_sig00000eb3,
DI => blk00000003_sig00000eb6,
S => blk00000003_sig00000eb4,
O => blk00000003_sig00000eaf
);
blk00000003_blk00000bde : XORCY
port map (
CI => blk00000003_sig00000eb3,
LI => blk00000003_sig00000eb4,
O => blk00000003_sig00000eb5
);
blk00000003_blk00000bdd : MUXCY
port map (
CI => blk00000003_sig00000eaf,
DI => blk00000003_sig00000eb2,
S => blk00000003_sig00000eb0,
O => blk00000003_sig00000eab
);
blk00000003_blk00000bdc : XORCY
port map (
CI => blk00000003_sig00000eaf,
LI => blk00000003_sig00000eb0,
O => blk00000003_sig00000eb1
);
blk00000003_blk00000bdb : MUXCY
port map (
CI => blk00000003_sig00000eab,
DI => blk00000003_sig00000eae,
S => blk00000003_sig00000eac,
O => blk00000003_sig00000ea7
);
blk00000003_blk00000bda : XORCY
port map (
CI => blk00000003_sig00000eab,
LI => blk00000003_sig00000eac,
O => blk00000003_sig00000ead
);
blk00000003_blk00000bd9 : MUXCY
port map (
CI => blk00000003_sig00000ea7,
DI => blk00000003_sig00000eaa,
S => blk00000003_sig00000ea8,
O => blk00000003_sig00000ea2
);
blk00000003_blk00000bd8 : XORCY
port map (
CI => blk00000003_sig00000ea7,
LI => blk00000003_sig00000ea8,
O => blk00000003_sig00000ea9
);
blk00000003_blk00000bd7 : MUXCY
port map (
CI => blk00000003_sig00000ea2,
DI => blk00000003_sig00000ea5,
S => blk00000003_sig00000ea3,
O => blk00000003_sig00000ea6
);
blk00000003_blk00000bd6 : XORCY
port map (
CI => blk00000003_sig00000ea2,
LI => blk00000003_sig00000ea3,
O => blk00000003_sig00000ea4
);
blk00000003_blk00000bd5 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000cb9,
Q => blk00000003_sig00000ea1
);
blk00000003_blk00000bd4 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000e8a,
Q => blk00000003_sig00000ea0
);
blk00000003_blk00000bd3 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000e89,
Q => blk00000003_sig00000e9f
);
blk00000003_blk00000bd2 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000e88,
Q => blk00000003_sig00000e9e
);
blk00000003_blk00000bd1 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000e87,
Q => blk00000003_sig00000e9d
);
blk00000003_blk00000bd0 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000e86,
Q => blk00000003_sig00000e9c
);
blk00000003_blk00000bcf : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000e85,
Q => blk00000003_sig00000e9b
);
blk00000003_blk00000bce : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000e84,
Q => blk00000003_sig00000e9a
);
blk00000003_blk00000bcd : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000e83,
Q => blk00000003_sig00000e99
);
blk00000003_blk00000bcc : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000e82,
Q => blk00000003_sig00000e98
);
blk00000003_blk00000bcb : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000e81,
Q => blk00000003_sig00000e97
);
blk00000003_blk00000bca : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000e80,
Q => blk00000003_sig00000e96
);
blk00000003_blk00000bc9 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000e7f,
Q => blk00000003_sig00000e95
);
blk00000003_blk00000bc8 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000e7e,
Q => blk00000003_sig00000e94
);
blk00000003_blk00000bc7 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000e7d,
Q => blk00000003_sig00000e93
);
blk00000003_blk00000bc6 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000e7c,
Q => blk00000003_sig00000e92
);
blk00000003_blk00000bc5 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000e7b,
Q => blk00000003_sig00000e91
);
blk00000003_blk00000bc4 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000e7a,
Q => blk00000003_sig00000e90
);
blk00000003_blk00000bc3 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000e79,
Q => blk00000003_sig00000e8f
);
blk00000003_blk00000bc2 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000e78,
Q => blk00000003_sig00000e8e
);
blk00000003_blk00000bc1 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000e77,
Q => blk00000003_sig00000e8d
);
blk00000003_blk00000bc0 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000e76,
Q => blk00000003_sig00000e8c
);
blk00000003_blk00000bbf : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000e75,
Q => blk00000003_sig00000e8b
);
blk00000003_blk00000bbe : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000cba,
Q => blk00000003_sig00000e8a
);
blk00000003_blk00000bbd : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000e74,
Q => blk00000003_sig00000e89
);
blk00000003_blk00000bbc : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000e73,
Q => blk00000003_sig00000e88
);
blk00000003_blk00000bbb : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000e72,
Q => blk00000003_sig00000e87
);
blk00000003_blk00000bba : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000e71,
Q => blk00000003_sig00000e86
);
blk00000003_blk00000bb9 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000e70,
Q => blk00000003_sig00000e85
);
blk00000003_blk00000bb8 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000e6f,
Q => blk00000003_sig00000e84
);
blk00000003_blk00000bb7 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000e6e,
Q => blk00000003_sig00000e83
);
blk00000003_blk00000bb6 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000e6d,
Q => blk00000003_sig00000e82
);
blk00000003_blk00000bb5 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000e6c,
Q => blk00000003_sig00000e81
);
blk00000003_blk00000bb4 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000e6b,
Q => blk00000003_sig00000e80
);
blk00000003_blk00000bb3 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000e6a,
Q => blk00000003_sig00000e7f
);
blk00000003_blk00000bb2 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000e69,
Q => blk00000003_sig00000e7e
);
blk00000003_blk00000bb1 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000e68,
Q => blk00000003_sig00000e7d
);
blk00000003_blk00000bb0 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000e67,
Q => blk00000003_sig00000e7c
);
blk00000003_blk00000baf : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000e66,
Q => blk00000003_sig00000e7b
);
blk00000003_blk00000bae : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000e65,
Q => blk00000003_sig00000e7a
);
blk00000003_blk00000bad : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000e64,
Q => blk00000003_sig00000e79
);
blk00000003_blk00000bac : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000e63,
Q => blk00000003_sig00000e78
);
blk00000003_blk00000bab : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000e62,
Q => blk00000003_sig00000e77
);
blk00000003_blk00000baa : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000e61,
Q => blk00000003_sig00000e76
);
blk00000003_blk00000ba9 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000e60,
Q => blk00000003_sig00000e75
);
blk00000003_blk00000ba8 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000cbb,
Q => blk00000003_sig00000e74
);
blk00000003_blk00000ba7 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000e5f,
Q => blk00000003_sig00000e73
);
blk00000003_blk00000ba6 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000e5e,
Q => blk00000003_sig00000e72
);
blk00000003_blk00000ba5 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000e5d,
Q => blk00000003_sig00000e71
);
blk00000003_blk00000ba4 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000e5c,
Q => blk00000003_sig00000e70
);
blk00000003_blk00000ba3 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000e5b,
Q => blk00000003_sig00000e6f
);
blk00000003_blk00000ba2 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000e5a,
Q => blk00000003_sig00000e6e
);
blk00000003_blk00000ba1 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000e59,
Q => blk00000003_sig00000e6d
);
blk00000003_blk00000ba0 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000e58,
Q => blk00000003_sig00000e6c
);
blk00000003_blk00000b9f : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000e57,
Q => blk00000003_sig00000e6b
);
blk00000003_blk00000b9e : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000e56,
Q => blk00000003_sig00000e6a
);
blk00000003_blk00000b9d : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000e55,
Q => blk00000003_sig00000e69
);
blk00000003_blk00000b9c : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000e54,
Q => blk00000003_sig00000e68
);
blk00000003_blk00000b9b : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000e53,
Q => blk00000003_sig00000e67
);
blk00000003_blk00000b9a : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000e52,
Q => blk00000003_sig00000e66
);
blk00000003_blk00000b99 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000e51,
Q => blk00000003_sig00000e65
);
blk00000003_blk00000b98 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000e50,
Q => blk00000003_sig00000e64
);
blk00000003_blk00000b97 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000e4f,
Q => blk00000003_sig00000e63
);
blk00000003_blk00000b96 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000e4e,
Q => blk00000003_sig00000e62
);
blk00000003_blk00000b95 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000e4d,
Q => blk00000003_sig00000e61
);
blk00000003_blk00000b94 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000e4c,
Q => blk00000003_sig00000e60
);
blk00000003_blk00000b93 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000cbc,
Q => blk00000003_sig00000e5f
);
blk00000003_blk00000b92 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000e4b,
Q => blk00000003_sig00000e5e
);
blk00000003_blk00000b91 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000e4a,
Q => blk00000003_sig00000e5d
);
blk00000003_blk00000b90 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000e49,
Q => blk00000003_sig00000e5c
);
blk00000003_blk00000b8f : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000e48,
Q => blk00000003_sig00000e5b
);
blk00000003_blk00000b8e : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000e47,
Q => blk00000003_sig00000e5a
);
blk00000003_blk00000b8d : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000e46,
Q => blk00000003_sig00000e59
);
blk00000003_blk00000b8c : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000e45,
Q => blk00000003_sig00000e58
);
blk00000003_blk00000b8b : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000e44,
Q => blk00000003_sig00000e57
);
blk00000003_blk00000b8a : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000e43,
Q => blk00000003_sig00000e56
);
blk00000003_blk00000b89 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000e42,
Q => blk00000003_sig00000e55
);
blk00000003_blk00000b88 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000e41,
Q => blk00000003_sig00000e54
);
blk00000003_blk00000b87 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000e40,
Q => blk00000003_sig00000e53
);
blk00000003_blk00000b86 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000e3f,
Q => blk00000003_sig00000e52
);
blk00000003_blk00000b85 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000e3e,
Q => blk00000003_sig00000e51
);
blk00000003_blk00000b84 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000e3d,
Q => blk00000003_sig00000e50
);
blk00000003_blk00000b83 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000e3c,
Q => blk00000003_sig00000e4f
);
blk00000003_blk00000b82 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000e3b,
Q => blk00000003_sig00000e4e
);
blk00000003_blk00000b81 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000e3a,
Q => blk00000003_sig00000e4d
);
blk00000003_blk00000b80 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000e39,
Q => blk00000003_sig00000e4c
);
blk00000003_blk00000b7f : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000cbd,
Q => blk00000003_sig00000e4b
);
blk00000003_blk00000b7e : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000e38,
Q => blk00000003_sig00000e4a
);
blk00000003_blk00000b7d : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000e37,
Q => blk00000003_sig00000e49
);
blk00000003_blk00000b7c : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000e36,
Q => blk00000003_sig00000e48
);
blk00000003_blk00000b7b : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000e35,
Q => blk00000003_sig00000e47
);
blk00000003_blk00000b7a : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000e34,
Q => blk00000003_sig00000e46
);
blk00000003_blk00000b79 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000e33,
Q => blk00000003_sig00000e45
);
blk00000003_blk00000b78 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000e32,
Q => blk00000003_sig00000e44
);
blk00000003_blk00000b77 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000e31,
Q => blk00000003_sig00000e43
);
blk00000003_blk00000b76 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000e30,
Q => blk00000003_sig00000e42
);
blk00000003_blk00000b75 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000e2f,
Q => blk00000003_sig00000e41
);
blk00000003_blk00000b74 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000e2e,
Q => blk00000003_sig00000e40
);
blk00000003_blk00000b73 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000e2d,
Q => blk00000003_sig00000e3f
);
blk00000003_blk00000b72 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000e2c,
Q => blk00000003_sig00000e3e
);
blk00000003_blk00000b71 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000e2b,
Q => blk00000003_sig00000e3d
);
blk00000003_blk00000b70 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000e2a,
Q => blk00000003_sig00000e3c
);
blk00000003_blk00000b6f : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000e29,
Q => blk00000003_sig00000e3b
);
blk00000003_blk00000b6e : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000e28,
Q => blk00000003_sig00000e3a
);
blk00000003_blk00000b6d : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000e27,
Q => blk00000003_sig00000e39
);
blk00000003_blk00000b6c : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000cbe,
Q => blk00000003_sig00000e38
);
blk00000003_blk00000b6b : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000e26,
Q => blk00000003_sig00000e37
);
blk00000003_blk00000b6a : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000e25,
Q => blk00000003_sig00000e36
);
blk00000003_blk00000b69 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000e24,
Q => blk00000003_sig00000e35
);
blk00000003_blk00000b68 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000e23,
Q => blk00000003_sig00000e34
);
blk00000003_blk00000b67 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000e22,
Q => blk00000003_sig00000e33
);
blk00000003_blk00000b66 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000e21,
Q => blk00000003_sig00000e32
);
blk00000003_blk00000b65 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000e20,
Q => blk00000003_sig00000e31
);
blk00000003_blk00000b64 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000e1f,
Q => blk00000003_sig00000e30
);
blk00000003_blk00000b63 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000e1e,
Q => blk00000003_sig00000e2f
);
blk00000003_blk00000b62 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000e1d,
Q => blk00000003_sig00000e2e
);
blk00000003_blk00000b61 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000e1c,
Q => blk00000003_sig00000e2d
);
blk00000003_blk00000b60 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000e1b,
Q => blk00000003_sig00000e2c
);
blk00000003_blk00000b5f : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000e1a,
Q => blk00000003_sig00000e2b
);
blk00000003_blk00000b5e : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000e19,
Q => blk00000003_sig00000e2a
);
blk00000003_blk00000b5d : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000e18,
Q => blk00000003_sig00000e29
);
blk00000003_blk00000b5c : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000e17,
Q => blk00000003_sig00000e28
);
blk00000003_blk00000b5b : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000e16,
Q => blk00000003_sig00000e27
);
blk00000003_blk00000b5a : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000cbf,
Q => blk00000003_sig00000e26
);
blk00000003_blk00000b59 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000e15,
Q => blk00000003_sig00000e25
);
blk00000003_blk00000b58 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000e14,
Q => blk00000003_sig00000e24
);
blk00000003_blk00000b57 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000e13,
Q => blk00000003_sig00000e23
);
blk00000003_blk00000b56 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000e12,
Q => blk00000003_sig00000e22
);
blk00000003_blk00000b55 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000e11,
Q => blk00000003_sig00000e21
);
blk00000003_blk00000b54 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000e10,
Q => blk00000003_sig00000e20
);
blk00000003_blk00000b53 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000e0f,
Q => blk00000003_sig00000e1f
);
blk00000003_blk00000b52 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000e0e,
Q => blk00000003_sig00000e1e
);
blk00000003_blk00000b51 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000e0d,
Q => blk00000003_sig00000e1d
);
blk00000003_blk00000b50 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000e0c,
Q => blk00000003_sig00000e1c
);
blk00000003_blk00000b4f : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000e0b,
Q => blk00000003_sig00000e1b
);
blk00000003_blk00000b4e : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000e0a,
Q => blk00000003_sig00000e1a
);
blk00000003_blk00000b4d : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000e09,
Q => blk00000003_sig00000e19
);
blk00000003_blk00000b4c : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000e08,
Q => blk00000003_sig00000e18
);
blk00000003_blk00000b4b : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000e07,
Q => blk00000003_sig00000e17
);
blk00000003_blk00000b4a : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000e06,
Q => blk00000003_sig00000e16
);
blk00000003_blk00000b49 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000cc0,
Q => blk00000003_sig00000e15
);
blk00000003_blk00000b48 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000e05,
Q => blk00000003_sig00000e14
);
blk00000003_blk00000b47 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000e04,
Q => blk00000003_sig00000e13
);
blk00000003_blk00000b46 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000e03,
Q => blk00000003_sig00000e12
);
blk00000003_blk00000b45 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000e02,
Q => blk00000003_sig00000e11
);
blk00000003_blk00000b44 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000e01,
Q => blk00000003_sig00000e10
);
blk00000003_blk00000b43 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000e00,
Q => blk00000003_sig00000e0f
);
blk00000003_blk00000b42 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000dff,
Q => blk00000003_sig00000e0e
);
blk00000003_blk00000b41 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000dfe,
Q => blk00000003_sig00000e0d
);
blk00000003_blk00000b40 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000dfd,
Q => blk00000003_sig00000e0c
);
blk00000003_blk00000b3f : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000dfc,
Q => blk00000003_sig00000e0b
);
blk00000003_blk00000b3e : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000dfb,
Q => blk00000003_sig00000e0a
);
blk00000003_blk00000b3d : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000dfa,
Q => blk00000003_sig00000e09
);
blk00000003_blk00000b3c : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000df9,
Q => blk00000003_sig00000e08
);
blk00000003_blk00000b3b : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000df8,
Q => blk00000003_sig00000e07
);
blk00000003_blk00000b3a : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000df7,
Q => blk00000003_sig00000e06
);
blk00000003_blk00000b39 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000df6,
Q => blk00000003_sig0000007e
);
blk00000003_blk00000b38 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000df5,
Q => blk00000003_sig0000007f
);
blk00000003_blk00000b37 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000df4,
Q => blk00000003_sig00000080
);
blk00000003_blk00000b36 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000df3,
Q => blk00000003_sig00000081
);
blk00000003_blk00000b35 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000df2,
Q => blk00000003_sig00000082
);
blk00000003_blk00000b34 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000df1,
Q => blk00000003_sig00000083
);
blk00000003_blk00000b33 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000df0,
Q => blk00000003_sig00000084
);
blk00000003_blk00000b32 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000def,
Q => blk00000003_sig000009db
);
blk00000003_blk00000b31 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000cc1,
Q => blk00000003_sig00000e05
);
blk00000003_blk00000b30 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000dee,
Q => blk00000003_sig00000e04
);
blk00000003_blk00000b2f : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000ded,
Q => blk00000003_sig00000e03
);
blk00000003_blk00000b2e : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000dec,
Q => blk00000003_sig00000e02
);
blk00000003_blk00000b2d : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000deb,
Q => blk00000003_sig00000e01
);
blk00000003_blk00000b2c : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000dea,
Q => blk00000003_sig00000e00
);
blk00000003_blk00000b2b : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000de9,
Q => blk00000003_sig00000dff
);
blk00000003_blk00000b2a : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000de8,
Q => blk00000003_sig00000dfe
);
blk00000003_blk00000b29 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000de7,
Q => blk00000003_sig00000dfd
);
blk00000003_blk00000b28 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000de6,
Q => blk00000003_sig00000dfc
);
blk00000003_blk00000b27 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000de5,
Q => blk00000003_sig00000dfb
);
blk00000003_blk00000b26 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000de4,
Q => blk00000003_sig00000dfa
);
blk00000003_blk00000b25 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000de3,
Q => blk00000003_sig00000df9
);
blk00000003_blk00000b24 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000de2,
Q => blk00000003_sig00000df8
);
blk00000003_blk00000b23 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000de1,
Q => blk00000003_sig00000df7
);
blk00000003_blk00000b22 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000de0,
Q => blk00000003_sig00000df6
);
blk00000003_blk00000b21 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000ddf,
Q => blk00000003_sig00000df5
);
blk00000003_blk00000b20 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000dde,
Q => blk00000003_sig00000df4
);
blk00000003_blk00000b1f : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000ddd,
Q => blk00000003_sig00000df3
);
blk00000003_blk00000b1e : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000ddc,
Q => blk00000003_sig00000df2
);
blk00000003_blk00000b1d : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000ddb,
Q => blk00000003_sig00000df1
);
blk00000003_blk00000b1c : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000dda,
Q => blk00000003_sig00000df0
);
blk00000003_blk00000b1b : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000dd9,
Q => blk00000003_sig00000def
);
blk00000003_blk00000b1a : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000dd8,
Q => blk00000003_sig00000975
);
blk00000003_blk00000b19 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000cc2,
Q => blk00000003_sig00000dee
);
blk00000003_blk00000b18 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000dd7,
Q => blk00000003_sig00000ded
);
blk00000003_blk00000b17 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000dd6,
Q => blk00000003_sig00000dec
);
blk00000003_blk00000b16 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000dd5,
Q => blk00000003_sig00000deb
);
blk00000003_blk00000b15 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000dd4,
Q => blk00000003_sig00000dea
);
blk00000003_blk00000b14 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000dd3,
Q => blk00000003_sig00000de9
);
blk00000003_blk00000b13 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000dd2,
Q => blk00000003_sig00000de8
);
blk00000003_blk00000b12 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000dd1,
Q => blk00000003_sig00000de7
);
blk00000003_blk00000b11 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000dd0,
Q => blk00000003_sig00000de6
);
blk00000003_blk00000b10 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000dcf,
Q => blk00000003_sig00000de5
);
blk00000003_blk00000b0f : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000dce,
Q => blk00000003_sig00000de4
);
blk00000003_blk00000b0e : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000dcd,
Q => blk00000003_sig00000de3
);
blk00000003_blk00000b0d : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000dcc,
Q => blk00000003_sig00000de2
);
blk00000003_blk00000b0c : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000dcb,
Q => blk00000003_sig00000de1
);
blk00000003_blk00000b0b : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000dca,
Q => blk00000003_sig00000de0
);
blk00000003_blk00000b0a : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000dc9,
Q => blk00000003_sig00000ddf
);
blk00000003_blk00000b09 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000dc8,
Q => blk00000003_sig00000dde
);
blk00000003_blk00000b08 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000dc7,
Q => blk00000003_sig00000ddd
);
blk00000003_blk00000b07 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000dc6,
Q => blk00000003_sig00000ddc
);
blk00000003_blk00000b06 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000dc5,
Q => blk00000003_sig00000ddb
);
blk00000003_blk00000b05 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000dc4,
Q => blk00000003_sig00000dda
);
blk00000003_blk00000b04 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000dc3,
Q => blk00000003_sig00000dd9
);
blk00000003_blk00000b03 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000dc2,
Q => blk00000003_sig00000dd8
);
blk00000003_blk00000b02 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000dc1,
Q => blk00000003_sig0000090f
);
blk00000003_blk00000b01 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000cc3,
Q => blk00000003_sig00000dd7
);
blk00000003_blk00000b00 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000dc0,
Q => blk00000003_sig00000dd6
);
blk00000003_blk00000aff : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000dbf,
Q => blk00000003_sig00000dd5
);
blk00000003_blk00000afe : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000dbe,
Q => blk00000003_sig00000dd4
);
blk00000003_blk00000afd : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000dbd,
Q => blk00000003_sig00000dd3
);
blk00000003_blk00000afc : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000dbc,
Q => blk00000003_sig00000dd2
);
blk00000003_blk00000afb : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000dbb,
Q => blk00000003_sig00000dd1
);
blk00000003_blk00000afa : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000dba,
Q => blk00000003_sig00000dd0
);
blk00000003_blk00000af9 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000db9,
Q => blk00000003_sig00000dcf
);
blk00000003_blk00000af8 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000db8,
Q => blk00000003_sig00000dce
);
blk00000003_blk00000af7 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000db7,
Q => blk00000003_sig00000dcd
);
blk00000003_blk00000af6 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000db6,
Q => blk00000003_sig00000dcc
);
blk00000003_blk00000af5 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000db5,
Q => blk00000003_sig00000dcb
);
blk00000003_blk00000af4 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000db4,
Q => blk00000003_sig00000dca
);
blk00000003_blk00000af3 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000db3,
Q => blk00000003_sig00000dc9
);
blk00000003_blk00000af2 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000db2,
Q => blk00000003_sig00000dc8
);
blk00000003_blk00000af1 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000db1,
Q => blk00000003_sig00000dc7
);
blk00000003_blk00000af0 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000db0,
Q => blk00000003_sig00000dc6
);
blk00000003_blk00000aef : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000daf,
Q => blk00000003_sig00000dc5
);
blk00000003_blk00000aee : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000dae,
Q => blk00000003_sig00000dc4
);
blk00000003_blk00000aed : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000dad,
Q => blk00000003_sig00000dc3
);
blk00000003_blk00000aec : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000dac,
Q => blk00000003_sig00000dc2
);
blk00000003_blk00000aeb : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000dab,
Q => blk00000003_sig00000dc1
);
blk00000003_blk00000aea : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000daa,
Q => blk00000003_sig000008a9
);
blk00000003_blk00000ae9 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000cc4,
Q => blk00000003_sig00000dc0
);
blk00000003_blk00000ae8 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000da9,
Q => blk00000003_sig00000dbf
);
blk00000003_blk00000ae7 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000da8,
Q => blk00000003_sig00000dbe
);
blk00000003_blk00000ae6 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000da7,
Q => blk00000003_sig00000dbd
);
blk00000003_blk00000ae5 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000da6,
Q => blk00000003_sig00000dbc
);
blk00000003_blk00000ae4 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000da5,
Q => blk00000003_sig00000dbb
);
blk00000003_blk00000ae3 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000da4,
Q => blk00000003_sig00000dba
);
blk00000003_blk00000ae2 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000da3,
Q => blk00000003_sig00000db9
);
blk00000003_blk00000ae1 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000da2,
Q => blk00000003_sig00000db8
);
blk00000003_blk00000ae0 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000da1,
Q => blk00000003_sig00000db7
);
blk00000003_blk00000adf : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000da0,
Q => blk00000003_sig00000db6
);
blk00000003_blk00000ade : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000d9f,
Q => blk00000003_sig00000db5
);
blk00000003_blk00000add : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000d9e,
Q => blk00000003_sig00000db4
);
blk00000003_blk00000adc : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000d9d,
Q => blk00000003_sig00000db3
);
blk00000003_blk00000adb : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000d9c,
Q => blk00000003_sig00000db2
);
blk00000003_blk00000ada : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000d9b,
Q => blk00000003_sig00000db1
);
blk00000003_blk00000ad9 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000d9a,
Q => blk00000003_sig00000db0
);
blk00000003_blk00000ad8 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000d99,
Q => blk00000003_sig00000daf
);
blk00000003_blk00000ad7 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000d98,
Q => blk00000003_sig00000dae
);
blk00000003_blk00000ad6 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000d97,
Q => blk00000003_sig00000dad
);
blk00000003_blk00000ad5 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000d96,
Q => blk00000003_sig00000dac
);
blk00000003_blk00000ad4 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000d95,
Q => blk00000003_sig00000dab
);
blk00000003_blk00000ad3 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000d94,
Q => blk00000003_sig00000daa
);
blk00000003_blk00000ad2 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000d93,
Q => blk00000003_sig00000843
);
blk00000003_blk00000ad1 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000cc5,
Q => blk00000003_sig00000da9
);
blk00000003_blk00000ad0 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000d92,
Q => blk00000003_sig00000da8
);
blk00000003_blk00000acf : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000d91,
Q => blk00000003_sig00000da7
);
blk00000003_blk00000ace : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000d90,
Q => blk00000003_sig00000da6
);
blk00000003_blk00000acd : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000d8f,
Q => blk00000003_sig00000da5
);
blk00000003_blk00000acc : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000d8e,
Q => blk00000003_sig00000da4
);
blk00000003_blk00000acb : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000d8d,
Q => blk00000003_sig00000da3
);
blk00000003_blk00000aca : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000d8c,
Q => blk00000003_sig00000da2
);
blk00000003_blk00000ac9 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000d8b,
Q => blk00000003_sig00000da1
);
blk00000003_blk00000ac8 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000d8a,
Q => blk00000003_sig00000da0
);
blk00000003_blk00000ac7 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000d89,
Q => blk00000003_sig00000d9f
);
blk00000003_blk00000ac6 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000d88,
Q => blk00000003_sig00000d9e
);
blk00000003_blk00000ac5 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000d87,
Q => blk00000003_sig00000d9d
);
blk00000003_blk00000ac4 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000d86,
Q => blk00000003_sig00000d9c
);
blk00000003_blk00000ac3 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000d85,
Q => blk00000003_sig00000d9b
);
blk00000003_blk00000ac2 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000d84,
Q => blk00000003_sig00000d9a
);
blk00000003_blk00000ac1 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000d83,
Q => blk00000003_sig00000d99
);
blk00000003_blk00000ac0 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000d82,
Q => blk00000003_sig00000d98
);
blk00000003_blk00000abf : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000d81,
Q => blk00000003_sig00000d97
);
blk00000003_blk00000abe : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000d80,
Q => blk00000003_sig00000d96
);
blk00000003_blk00000abd : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000d7f,
Q => blk00000003_sig00000d95
);
blk00000003_blk00000abc : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000d7e,
Q => blk00000003_sig00000d94
);
blk00000003_blk00000abb : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000d7d,
Q => blk00000003_sig00000d93
);
blk00000003_blk00000aba : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000d7c,
Q => blk00000003_sig000007dd
);
blk00000003_blk00000ab9 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000cc6,
Q => blk00000003_sig00000d92
);
blk00000003_blk00000ab8 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000d7b,
Q => blk00000003_sig00000d91
);
blk00000003_blk00000ab7 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000d7a,
Q => blk00000003_sig00000d90
);
blk00000003_blk00000ab6 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000d79,
Q => blk00000003_sig00000d8f
);
blk00000003_blk00000ab5 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000d78,
Q => blk00000003_sig00000d8e
);
blk00000003_blk00000ab4 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000d77,
Q => blk00000003_sig00000d8d
);
blk00000003_blk00000ab3 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000d76,
Q => blk00000003_sig00000d8c
);
blk00000003_blk00000ab2 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000d75,
Q => blk00000003_sig00000d8b
);
blk00000003_blk00000ab1 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000d74,
Q => blk00000003_sig00000d8a
);
blk00000003_blk00000ab0 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000d73,
Q => blk00000003_sig00000d89
);
blk00000003_blk00000aaf : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000d72,
Q => blk00000003_sig00000d88
);
blk00000003_blk00000aae : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000d71,
Q => blk00000003_sig00000d87
);
blk00000003_blk00000aad : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000d70,
Q => blk00000003_sig00000d86
);
blk00000003_blk00000aac : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000d6f,
Q => blk00000003_sig00000d85
);
blk00000003_blk00000aab : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000d6e,
Q => blk00000003_sig00000d84
);
blk00000003_blk00000aaa : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000d6d,
Q => blk00000003_sig00000d83
);
blk00000003_blk00000aa9 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000d6c,
Q => blk00000003_sig00000d82
);
blk00000003_blk00000aa8 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000d6b,
Q => blk00000003_sig00000d81
);
blk00000003_blk00000aa7 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000d6a,
Q => blk00000003_sig00000d80
);
blk00000003_blk00000aa6 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000d69,
Q => blk00000003_sig00000d7f
);
blk00000003_blk00000aa5 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000d68,
Q => blk00000003_sig00000d7e
);
blk00000003_blk00000aa4 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000d67,
Q => blk00000003_sig00000d7d
);
blk00000003_blk00000aa3 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000d66,
Q => blk00000003_sig00000d7c
);
blk00000003_blk00000aa2 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000d65,
Q => blk00000003_sig00000777
);
blk00000003_blk00000aa1 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000cc7,
Q => blk00000003_sig00000d7b
);
blk00000003_blk00000aa0 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000d64,
Q => blk00000003_sig00000d7a
);
blk00000003_blk00000a9f : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000d63,
Q => blk00000003_sig00000d79
);
blk00000003_blk00000a9e : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000d62,
Q => blk00000003_sig00000d78
);
blk00000003_blk00000a9d : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000d61,
Q => blk00000003_sig00000d77
);
blk00000003_blk00000a9c : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000d60,
Q => blk00000003_sig00000d76
);
blk00000003_blk00000a9b : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000d5f,
Q => blk00000003_sig00000d75
);
blk00000003_blk00000a9a : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000d5e,
Q => blk00000003_sig00000d74
);
blk00000003_blk00000a99 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000d5d,
Q => blk00000003_sig00000d73
);
blk00000003_blk00000a98 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000d5c,
Q => blk00000003_sig00000d72
);
blk00000003_blk00000a97 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000d5b,
Q => blk00000003_sig00000d71
);
blk00000003_blk00000a96 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000d5a,
Q => blk00000003_sig00000d70
);
blk00000003_blk00000a95 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000d59,
Q => blk00000003_sig00000d6f
);
blk00000003_blk00000a94 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000d58,
Q => blk00000003_sig00000d6e
);
blk00000003_blk00000a93 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000d57,
Q => blk00000003_sig00000d6d
);
blk00000003_blk00000a92 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000d56,
Q => blk00000003_sig00000d6c
);
blk00000003_blk00000a91 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000d55,
Q => blk00000003_sig00000d6b
);
blk00000003_blk00000a90 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000d54,
Q => blk00000003_sig00000d6a
);
blk00000003_blk00000a8f : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000d53,
Q => blk00000003_sig00000d69
);
blk00000003_blk00000a8e : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000d52,
Q => blk00000003_sig00000d68
);
blk00000003_blk00000a8d : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000d51,
Q => blk00000003_sig00000d67
);
blk00000003_blk00000a8c : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000d50,
Q => blk00000003_sig00000d66
);
blk00000003_blk00000a8b : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000d4f,
Q => blk00000003_sig00000d65
);
blk00000003_blk00000a8a : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000d4e,
Q => blk00000003_sig00000711
);
blk00000003_blk00000a89 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000cc8,
Q => blk00000003_sig00000d64
);
blk00000003_blk00000a88 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000087,
Q => blk00000003_sig00000d63
);
blk00000003_blk00000a87 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000089,
Q => blk00000003_sig00000d62
);
blk00000003_blk00000a86 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig0000008b,
Q => blk00000003_sig00000d61
);
blk00000003_blk00000a85 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig0000008d,
Q => blk00000003_sig00000d60
);
blk00000003_blk00000a84 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig0000008f,
Q => blk00000003_sig00000d5f
);
blk00000003_blk00000a83 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000091,
Q => blk00000003_sig00000d5e
);
blk00000003_blk00000a82 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000093,
Q => blk00000003_sig00000d5d
);
blk00000003_blk00000a81 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000d4d,
Q => blk00000003_sig00000d5c
);
blk00000003_blk00000a80 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000d4c,
Q => blk00000003_sig00000d5b
);
blk00000003_blk00000a7f : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000d4b,
Q => blk00000003_sig00000d5a
);
blk00000003_blk00000a7e : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000d4a,
Q => blk00000003_sig00000d59
);
blk00000003_blk00000a7d : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000d49,
Q => blk00000003_sig00000d58
);
blk00000003_blk00000a7c : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000d48,
Q => blk00000003_sig00000d57
);
blk00000003_blk00000a7b : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000d47,
Q => blk00000003_sig00000d56
);
blk00000003_blk00000a7a : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000d46,
Q => blk00000003_sig00000d55
);
blk00000003_blk00000a79 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000d45,
Q => blk00000003_sig00000d54
);
blk00000003_blk00000a78 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000d44,
Q => blk00000003_sig00000d53
);
blk00000003_blk00000a77 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000d43,
Q => blk00000003_sig00000d52
);
blk00000003_blk00000a76 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000d42,
Q => blk00000003_sig00000d51
);
blk00000003_blk00000a75 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000d41,
Q => blk00000003_sig00000d50
);
blk00000003_blk00000a74 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000d40,
Q => blk00000003_sig00000d4f
);
blk00000003_blk00000a73 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000d3f,
Q => blk00000003_sig00000d4e
);
blk00000003_blk00000a72 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000d3e,
Q => blk00000003_sig000006ab
);
blk00000003_blk00000a71 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000d3d,
Q => blk00000003_sig00000d4d
);
blk00000003_blk00000a70 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000d3c,
Q => blk00000003_sig00000d4c
);
blk00000003_blk00000a6f : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000d3b,
Q => blk00000003_sig00000d4b
);
blk00000003_blk00000a6e : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000d3a,
Q => blk00000003_sig00000d4a
);
blk00000003_blk00000a6d : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000d39,
Q => blk00000003_sig00000d49
);
blk00000003_blk00000a6c : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000d38,
Q => blk00000003_sig00000d48
);
blk00000003_blk00000a6b : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000d37,
Q => blk00000003_sig00000d47
);
blk00000003_blk00000a6a : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000d36,
Q => blk00000003_sig00000d46
);
blk00000003_blk00000a69 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000d35,
Q => blk00000003_sig00000d45
);
blk00000003_blk00000a68 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000d34,
Q => blk00000003_sig00000d44
);
blk00000003_blk00000a67 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000d33,
Q => blk00000003_sig00000d43
);
blk00000003_blk00000a66 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000d32,
Q => blk00000003_sig00000d42
);
blk00000003_blk00000a65 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000d31,
Q => blk00000003_sig00000d41
);
blk00000003_blk00000a64 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000d30,
Q => blk00000003_sig00000d40
);
blk00000003_blk00000a63 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000d2f,
Q => blk00000003_sig00000d3f
);
blk00000003_blk00000a62 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000d2e,
Q => blk00000003_sig00000d3e
);
blk00000003_blk00000a61 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000d2d,
Q => blk00000003_sig00000645
);
blk00000003_blk00000a60 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000d2c,
Q => blk00000003_sig00000d3d
);
blk00000003_blk00000a5f : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000d2b,
Q => blk00000003_sig00000d3c
);
blk00000003_blk00000a5e : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000d2a,
Q => blk00000003_sig00000d3b
);
blk00000003_blk00000a5d : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000d29,
Q => blk00000003_sig00000d3a
);
blk00000003_blk00000a5c : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000d28,
Q => blk00000003_sig00000d39
);
blk00000003_blk00000a5b : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000d27,
Q => blk00000003_sig00000d38
);
blk00000003_blk00000a5a : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000d26,
Q => blk00000003_sig00000d37
);
blk00000003_blk00000a59 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000d25,
Q => blk00000003_sig00000d36
);
blk00000003_blk00000a58 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000d24,
Q => blk00000003_sig00000d35
);
blk00000003_blk00000a57 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000d23,
Q => blk00000003_sig00000d34
);
blk00000003_blk00000a56 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000d22,
Q => blk00000003_sig00000d33
);
blk00000003_blk00000a55 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000d21,
Q => blk00000003_sig00000d32
);
blk00000003_blk00000a54 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000d20,
Q => blk00000003_sig00000d31
);
blk00000003_blk00000a53 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000d1f,
Q => blk00000003_sig00000d30
);
blk00000003_blk00000a52 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000d1e,
Q => blk00000003_sig00000d2f
);
blk00000003_blk00000a51 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000d1d,
Q => blk00000003_sig00000d2e
);
blk00000003_blk00000a50 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000d1c,
Q => blk00000003_sig00000d2d
);
blk00000003_blk00000a4f : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000d1b,
Q => blk00000003_sig000005df
);
blk00000003_blk00000a4e : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000d1a,
Q => blk00000003_sig00000d2c
);
blk00000003_blk00000a4d : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000d19,
Q => blk00000003_sig00000d2b
);
blk00000003_blk00000a4c : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000d18,
Q => blk00000003_sig00000d2a
);
blk00000003_blk00000a4b : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000d17,
Q => blk00000003_sig00000d29
);
blk00000003_blk00000a4a : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000d16,
Q => blk00000003_sig00000d28
);
blk00000003_blk00000a49 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000d15,
Q => blk00000003_sig00000d27
);
blk00000003_blk00000a48 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000d14,
Q => blk00000003_sig00000d26
);
blk00000003_blk00000a47 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000d13,
Q => blk00000003_sig00000d25
);
blk00000003_blk00000a46 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000d12,
Q => blk00000003_sig00000d24
);
blk00000003_blk00000a45 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000d11,
Q => blk00000003_sig00000d23
);
blk00000003_blk00000a44 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000d10,
Q => blk00000003_sig00000d22
);
blk00000003_blk00000a43 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000d0f,
Q => blk00000003_sig00000d21
);
blk00000003_blk00000a42 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000d0e,
Q => blk00000003_sig00000d20
);
blk00000003_blk00000a41 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000d0d,
Q => blk00000003_sig00000d1f
);
blk00000003_blk00000a40 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000d0c,
Q => blk00000003_sig00000d1e
);
blk00000003_blk00000a3f : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000d0b,
Q => blk00000003_sig00000d1d
);
blk00000003_blk00000a3e : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000d0a,
Q => blk00000003_sig00000d1c
);
blk00000003_blk00000a3d : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000d09,
Q => blk00000003_sig00000d1b
);
blk00000003_blk00000a3c : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000d08,
Q => blk00000003_sig00000579
);
blk00000003_blk00000a3b : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000d07,
Q => blk00000003_sig00000d1a
);
blk00000003_blk00000a3a : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000d06,
Q => blk00000003_sig00000d19
);
blk00000003_blk00000a39 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000d05,
Q => blk00000003_sig00000d18
);
blk00000003_blk00000a38 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000d04,
Q => blk00000003_sig00000d17
);
blk00000003_blk00000a37 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000d03,
Q => blk00000003_sig00000d16
);
blk00000003_blk00000a36 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000d02,
Q => blk00000003_sig00000d15
);
blk00000003_blk00000a35 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000d01,
Q => blk00000003_sig00000d14
);
blk00000003_blk00000a34 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000d00,
Q => blk00000003_sig00000d13
);
blk00000003_blk00000a33 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000cff,
Q => blk00000003_sig00000d12
);
blk00000003_blk00000a32 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000cfe,
Q => blk00000003_sig00000d11
);
blk00000003_blk00000a31 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000cfd,
Q => blk00000003_sig00000d10
);
blk00000003_blk00000a30 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000cfc,
Q => blk00000003_sig00000d0f
);
blk00000003_blk00000a2f : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000cfb,
Q => blk00000003_sig00000d0e
);
blk00000003_blk00000a2e : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000cfa,
Q => blk00000003_sig00000d0d
);
blk00000003_blk00000a2d : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000cf9,
Q => blk00000003_sig00000d0c
);
blk00000003_blk00000a2c : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000cf8,
Q => blk00000003_sig00000d0b
);
blk00000003_blk00000a2b : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000cf7,
Q => blk00000003_sig00000d0a
);
blk00000003_blk00000a2a : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000cf6,
Q => blk00000003_sig00000d09
);
blk00000003_blk00000a29 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000cf5,
Q => blk00000003_sig00000d08
);
blk00000003_blk00000a28 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000cf4,
Q => blk00000003_sig00000513
);
blk00000003_blk00000a27 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000cf3,
Q => blk00000003_sig00000d07
);
blk00000003_blk00000a26 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000cf2,
Q => blk00000003_sig00000d06
);
blk00000003_blk00000a25 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000cf1,
Q => blk00000003_sig00000d05
);
blk00000003_blk00000a24 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000cf0,
Q => blk00000003_sig00000d04
);
blk00000003_blk00000a23 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000cef,
Q => blk00000003_sig00000d03
);
blk00000003_blk00000a22 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000cee,
Q => blk00000003_sig00000d02
);
blk00000003_blk00000a21 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000ced,
Q => blk00000003_sig00000d01
);
blk00000003_blk00000a20 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000cec,
Q => blk00000003_sig00000d00
);
blk00000003_blk00000a1f : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000ceb,
Q => blk00000003_sig00000cff
);
blk00000003_blk00000a1e : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000cea,
Q => blk00000003_sig00000cfe
);
blk00000003_blk00000a1d : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000ce9,
Q => blk00000003_sig00000cfd
);
blk00000003_blk00000a1c : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000ce8,
Q => blk00000003_sig00000cfc
);
blk00000003_blk00000a1b : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000ce7,
Q => blk00000003_sig00000cfb
);
blk00000003_blk00000a1a : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000ce6,
Q => blk00000003_sig00000cfa
);
blk00000003_blk00000a19 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000ce5,
Q => blk00000003_sig00000cf9
);
blk00000003_blk00000a18 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000ce4,
Q => blk00000003_sig00000cf8
);
blk00000003_blk00000a17 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000ce3,
Q => blk00000003_sig00000cf7
);
blk00000003_blk00000a16 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000ce2,
Q => blk00000003_sig00000cf6
);
blk00000003_blk00000a15 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000ce1,
Q => blk00000003_sig00000cf5
);
blk00000003_blk00000a14 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000ce0,
Q => blk00000003_sig00000cf4
);
blk00000003_blk00000a13 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000cdf,
Q => blk00000003_sig000004ad
);
blk00000003_blk00000a12 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000cde,
Q => blk00000003_sig00000cf3
);
blk00000003_blk00000a11 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000cdd,
Q => blk00000003_sig00000cf2
);
blk00000003_blk00000a10 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000cdc,
Q => blk00000003_sig00000cf1
);
blk00000003_blk00000a0f : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000cdb,
Q => blk00000003_sig00000cf0
);
blk00000003_blk00000a0e : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000cda,
Q => blk00000003_sig00000cef
);
blk00000003_blk00000a0d : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000cd9,
Q => blk00000003_sig00000cee
);
blk00000003_blk00000a0c : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000cd8,
Q => blk00000003_sig00000ced
);
blk00000003_blk00000a0b : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000cd7,
Q => blk00000003_sig00000cec
);
blk00000003_blk00000a0a : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000cd6,
Q => blk00000003_sig00000ceb
);
blk00000003_blk00000a09 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000cd5,
Q => blk00000003_sig00000cea
);
blk00000003_blk00000a08 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000cd4,
Q => blk00000003_sig00000ce9
);
blk00000003_blk00000a07 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000cd3,
Q => blk00000003_sig00000ce8
);
blk00000003_blk00000a06 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000cd2,
Q => blk00000003_sig00000ce7
);
blk00000003_blk00000a05 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000cd1,
Q => blk00000003_sig00000ce6
);
blk00000003_blk00000a04 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000cd0,
Q => blk00000003_sig00000ce5
);
blk00000003_blk00000a03 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000ccf,
Q => blk00000003_sig00000ce4
);
blk00000003_blk00000a02 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000cce,
Q => blk00000003_sig00000ce3
);
blk00000003_blk00000a01 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000ccd,
Q => blk00000003_sig00000ce2
);
blk00000003_blk00000a00 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000ccc,
Q => blk00000003_sig00000ce1
);
blk00000003_blk000009ff : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000ccb,
Q => blk00000003_sig00000ce0
);
blk00000003_blk000009fe : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000cca,
Q => blk00000003_sig00000cdf
);
blk00000003_blk000009fd : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000cc9,
Q => blk00000003_sig00000447
);
blk00000003_blk000009fc : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig000000d9,
Q => blk00000003_sig00000cde
);
blk00000003_blk000009fb : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig000000d8,
Q => blk00000003_sig00000cdd
);
blk00000003_blk000009fa : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig000000d7,
Q => blk00000003_sig00000cdc
);
blk00000003_blk000009f9 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig000000d6,
Q => blk00000003_sig00000cdb
);
blk00000003_blk000009f8 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig000000d5,
Q => blk00000003_sig00000cda
);
blk00000003_blk000009f7 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig000000d4,
Q => blk00000003_sig00000cd9
);
blk00000003_blk000009f6 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig000000d3,
Q => blk00000003_sig00000cd8
);
blk00000003_blk000009f5 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig000000d2,
Q => blk00000003_sig00000cd7
);
blk00000003_blk000009f4 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig000000d1,
Q => blk00000003_sig00000cd6
);
blk00000003_blk000009f3 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig000000d0,
Q => blk00000003_sig00000cd5
);
blk00000003_blk000009f2 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig000000cf,
Q => blk00000003_sig00000cd4
);
blk00000003_blk000009f1 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig000000ce,
Q => blk00000003_sig00000cd3
);
blk00000003_blk000009f0 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig000000cd,
Q => blk00000003_sig00000cd2
);
blk00000003_blk000009ef : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig000000cc,
Q => blk00000003_sig00000cd1
);
blk00000003_blk000009ee : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig000000cb,
Q => blk00000003_sig00000cd0
);
blk00000003_blk000009ed : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig000000ca,
Q => blk00000003_sig00000ccf
);
blk00000003_blk000009ec : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig000000c9,
Q => blk00000003_sig00000cce
);
blk00000003_blk000009eb : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig000000c8,
Q => blk00000003_sig00000ccd
);
blk00000003_blk000009ea : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig000000c7,
Q => blk00000003_sig00000ccc
);
blk00000003_blk000009e9 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig000000c6,
Q => blk00000003_sig00000ccb
);
blk00000003_blk000009e8 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig000000c5,
Q => blk00000003_sig00000cca
);
blk00000003_blk000009e7 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig000000c4,
Q => blk00000003_sig00000cc9
);
blk00000003_blk000009e6 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig000000c3,
Q => blk00000003_sig000003e1
);
blk00000003_blk000009e5 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig0000037b,
Q => blk00000003_sig000003db
);
blk00000003_blk000009e4 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000378,
Q => blk00000003_sig000003da
);
blk00000003_blk000009e3 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000375,
Q => blk00000003_sig000003d9
);
blk00000003_blk000009e2 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000372,
Q => blk00000003_sig000003d8
);
blk00000003_blk000009e1 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig0000036f,
Q => blk00000003_sig000003d7
);
blk00000003_blk000009e0 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig0000036c,
Q => blk00000003_sig000003d6
);
blk00000003_blk000009df : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000369,
Q => blk00000003_sig000003d5
);
blk00000003_blk000009de : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000366,
Q => blk00000003_sig000003d4
);
blk00000003_blk000009dd : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000363,
Q => blk00000003_sig000003d3
);
blk00000003_blk000009dc : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000360,
Q => blk00000003_sig000003d2
);
blk00000003_blk000009db : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig0000035d,
Q => blk00000003_sig000003d1
);
blk00000003_blk000009da : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig0000035a,
Q => blk00000003_sig000003d0
);
blk00000003_blk000009d9 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000357,
Q => blk00000003_sig000003cf
);
blk00000003_blk000009d8 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000354,
Q => blk00000003_sig000003ce
);
blk00000003_blk000009d7 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000351,
Q => blk00000003_sig000003cd
);
blk00000003_blk000009d6 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig0000034e,
Q => blk00000003_sig000003cc
);
blk00000003_blk000009d5 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig0000034b,
Q => blk00000003_sig000003cb
);
blk00000003_blk000009d4 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000348,
Q => blk00000003_sig000003ca
);
blk00000003_blk000009d3 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000345,
Q => blk00000003_sig000003c9
);
blk00000003_blk000009d2 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000342,
Q => blk00000003_sig000003c8
);
blk00000003_blk000009d1 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig0000033f,
Q => blk00000003_sig000003c7
);
blk00000003_blk000009d0 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig0000033c,
Q => blk00000003_sig000003c6
);
blk00000003_blk000009cf : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000339,
Q => blk00000003_sig000003c5
);
blk00000003_blk000009ce : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000336,
Q => blk00000003_sig000003dc
);
blk00000003_blk000009cd : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000333,
Q => blk00000003_sig000000a8
);
blk00000003_blk000009cc : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig000003e0,
Q => blk00000003_sig00000441
);
blk00000003_blk000009cb : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig000003c4,
Q => blk00000003_sig00000440
);
blk00000003_blk000009ca : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig000003c1,
Q => blk00000003_sig0000043f
);
blk00000003_blk000009c9 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig000003be,
Q => blk00000003_sig0000043e
);
blk00000003_blk000009c8 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig000003bb,
Q => blk00000003_sig0000043d
);
blk00000003_blk000009c7 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig000003b8,
Q => blk00000003_sig0000043c
);
blk00000003_blk000009c6 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig000003b5,
Q => blk00000003_sig0000043b
);
blk00000003_blk000009c5 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig000003b2,
Q => blk00000003_sig0000043a
);
blk00000003_blk000009c4 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig000003af,
Q => blk00000003_sig00000439
);
blk00000003_blk000009c3 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig000003ac,
Q => blk00000003_sig00000438
);
blk00000003_blk000009c2 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig000003a9,
Q => blk00000003_sig00000437
);
blk00000003_blk000009c1 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig000003a6,
Q => blk00000003_sig00000436
);
blk00000003_blk000009c0 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig000003a3,
Q => blk00000003_sig00000435
);
blk00000003_blk000009bf : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig000003a0,
Q => blk00000003_sig00000434
);
blk00000003_blk000009be : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig0000039d,
Q => blk00000003_sig00000433
);
blk00000003_blk000009bd : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig0000039a,
Q => blk00000003_sig00000432
);
blk00000003_blk000009bc : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000397,
Q => blk00000003_sig00000431
);
blk00000003_blk000009bb : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000394,
Q => blk00000003_sig00000430
);
blk00000003_blk000009ba : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000391,
Q => blk00000003_sig0000042f
);
blk00000003_blk000009b9 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig0000038e,
Q => blk00000003_sig0000042e
);
blk00000003_blk000009b8 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig0000038b,
Q => blk00000003_sig0000042d
);
blk00000003_blk000009b7 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000388,
Q => blk00000003_sig0000042c
);
blk00000003_blk000009b6 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000385,
Q => blk00000003_sig0000042b
);
blk00000003_blk000009b5 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000382,
Q => blk00000003_sig00000442
);
blk00000003_blk000009b4 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig0000037f,
Q => blk00000003_sig000000a6
);
blk00000003_blk000009b3 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000446,
Q => blk00000003_sig000004a7
);
blk00000003_blk000009b2 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig0000042a,
Q => blk00000003_sig000004a6
);
blk00000003_blk000009b1 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000427,
Q => blk00000003_sig000004a5
);
blk00000003_blk000009b0 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000424,
Q => blk00000003_sig000004a4
);
blk00000003_blk000009af : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000421,
Q => blk00000003_sig000004a3
);
blk00000003_blk000009ae : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig0000041e,
Q => blk00000003_sig000004a2
);
blk00000003_blk000009ad : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig0000041b,
Q => blk00000003_sig000004a1
);
blk00000003_blk000009ac : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000418,
Q => blk00000003_sig000004a0
);
blk00000003_blk000009ab : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000415,
Q => blk00000003_sig0000049f
);
blk00000003_blk000009aa : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000412,
Q => blk00000003_sig0000049e
);
blk00000003_blk000009a9 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig0000040f,
Q => blk00000003_sig0000049d
);
blk00000003_blk000009a8 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig0000040c,
Q => blk00000003_sig0000049c
);
blk00000003_blk000009a7 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000409,
Q => blk00000003_sig0000049b
);
blk00000003_blk000009a6 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000406,
Q => blk00000003_sig0000049a
);
blk00000003_blk000009a5 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000403,
Q => blk00000003_sig00000499
);
blk00000003_blk000009a4 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000400,
Q => blk00000003_sig00000498
);
blk00000003_blk000009a3 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig000003fd,
Q => blk00000003_sig00000497
);
blk00000003_blk000009a2 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig000003fa,
Q => blk00000003_sig00000496
);
blk00000003_blk000009a1 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig000003f7,
Q => blk00000003_sig00000495
);
blk00000003_blk000009a0 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig000003f4,
Q => blk00000003_sig00000494
);
blk00000003_blk0000099f : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig000003f1,
Q => blk00000003_sig00000493
);
blk00000003_blk0000099e : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig000003ee,
Q => blk00000003_sig00000492
);
blk00000003_blk0000099d : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig000003eb,
Q => blk00000003_sig00000491
);
blk00000003_blk0000099c : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig000003e8,
Q => blk00000003_sig000004a8
);
blk00000003_blk0000099b : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig000003e5,
Q => blk00000003_sig000000a3
);
blk00000003_blk0000099a : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig000004ac,
Q => blk00000003_sig0000050d
);
blk00000003_blk00000999 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000490,
Q => blk00000003_sig0000050c
);
blk00000003_blk00000998 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig0000048d,
Q => blk00000003_sig0000050b
);
blk00000003_blk00000997 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig0000048a,
Q => blk00000003_sig0000050a
);
blk00000003_blk00000996 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000487,
Q => blk00000003_sig00000509
);
blk00000003_blk00000995 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000484,
Q => blk00000003_sig00000508
);
blk00000003_blk00000994 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000481,
Q => blk00000003_sig00000507
);
blk00000003_blk00000993 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig0000047e,
Q => blk00000003_sig00000506
);
blk00000003_blk00000992 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig0000047b,
Q => blk00000003_sig00000505
);
blk00000003_blk00000991 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000478,
Q => blk00000003_sig00000504
);
blk00000003_blk00000990 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000475,
Q => blk00000003_sig00000503
);
blk00000003_blk0000098f : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000472,
Q => blk00000003_sig00000502
);
blk00000003_blk0000098e : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig0000046f,
Q => blk00000003_sig00000501
);
blk00000003_blk0000098d : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig0000046c,
Q => blk00000003_sig00000500
);
blk00000003_blk0000098c : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000469,
Q => blk00000003_sig000004ff
);
blk00000003_blk0000098b : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000466,
Q => blk00000003_sig000004fe
);
blk00000003_blk0000098a : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000463,
Q => blk00000003_sig000004fd
);
blk00000003_blk00000989 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000460,
Q => blk00000003_sig000004fc
);
blk00000003_blk00000988 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig0000045d,
Q => blk00000003_sig000004fb
);
blk00000003_blk00000987 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig0000045a,
Q => blk00000003_sig000004fa
);
blk00000003_blk00000986 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000457,
Q => blk00000003_sig000004f9
);
blk00000003_blk00000985 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000454,
Q => blk00000003_sig000004f8
);
blk00000003_blk00000984 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000451,
Q => blk00000003_sig000004f7
);
blk00000003_blk00000983 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig0000044e,
Q => blk00000003_sig0000050e
);
blk00000003_blk00000982 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig0000044b,
Q => blk00000003_sig0000009f
);
blk00000003_blk00000981 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000512,
Q => blk00000003_sig00000573
);
blk00000003_blk00000980 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig000004f6,
Q => blk00000003_sig00000572
);
blk00000003_blk0000097f : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig000004f3,
Q => blk00000003_sig00000571
);
blk00000003_blk0000097e : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig000004f0,
Q => blk00000003_sig00000570
);
blk00000003_blk0000097d : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig000004ed,
Q => blk00000003_sig0000056f
);
blk00000003_blk0000097c : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig000004ea,
Q => blk00000003_sig0000056e
);
blk00000003_blk0000097b : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig000004e7,
Q => blk00000003_sig0000056d
);
blk00000003_blk0000097a : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig000004e4,
Q => blk00000003_sig0000056c
);
blk00000003_blk00000979 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig000004e1,
Q => blk00000003_sig0000056b
);
blk00000003_blk00000978 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig000004de,
Q => blk00000003_sig0000056a
);
blk00000003_blk00000977 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig000004db,
Q => blk00000003_sig00000569
);
blk00000003_blk00000976 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig000004d8,
Q => blk00000003_sig00000568
);
blk00000003_blk00000975 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig000004d5,
Q => blk00000003_sig00000567
);
blk00000003_blk00000974 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig000004d2,
Q => blk00000003_sig00000566
);
blk00000003_blk00000973 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig000004cf,
Q => blk00000003_sig00000565
);
blk00000003_blk00000972 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig000004cc,
Q => blk00000003_sig00000564
);
blk00000003_blk00000971 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig000004c9,
Q => blk00000003_sig00000563
);
blk00000003_blk00000970 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig000004c6,
Q => blk00000003_sig00000562
);
blk00000003_blk0000096f : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig000004c3,
Q => blk00000003_sig00000561
);
blk00000003_blk0000096e : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig000004c0,
Q => blk00000003_sig00000560
);
blk00000003_blk0000096d : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig000004bd,
Q => blk00000003_sig0000055f
);
blk00000003_blk0000096c : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig000004ba,
Q => blk00000003_sig0000055e
);
blk00000003_blk0000096b : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig000004b7,
Q => blk00000003_sig0000055d
);
blk00000003_blk0000096a : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig000004b4,
Q => blk00000003_sig00000574
);
blk00000003_blk00000969 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig000004b1,
Q => blk00000003_sig0000009a
);
blk00000003_blk00000968 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000578,
Q => blk00000003_sig000005d9
);
blk00000003_blk00000967 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig0000055c,
Q => blk00000003_sig000005d8
);
blk00000003_blk00000966 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000559,
Q => blk00000003_sig000005d7
);
blk00000003_blk00000965 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000556,
Q => blk00000003_sig000005d6
);
blk00000003_blk00000964 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000553,
Q => blk00000003_sig000005d5
);
blk00000003_blk00000963 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000550,
Q => blk00000003_sig000005d4
);
blk00000003_blk00000962 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig0000054d,
Q => blk00000003_sig000005d3
);
blk00000003_blk00000961 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig0000054a,
Q => blk00000003_sig000005d2
);
blk00000003_blk00000960 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000547,
Q => blk00000003_sig000005d1
);
blk00000003_blk0000095f : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000544,
Q => blk00000003_sig000005d0
);
blk00000003_blk0000095e : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000541,
Q => blk00000003_sig000005cf
);
blk00000003_blk0000095d : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig0000053e,
Q => blk00000003_sig000005ce
);
blk00000003_blk0000095c : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig0000053b,
Q => blk00000003_sig000005cd
);
blk00000003_blk0000095b : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000538,
Q => blk00000003_sig000005cc
);
blk00000003_blk0000095a : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000535,
Q => blk00000003_sig000005cb
);
blk00000003_blk00000959 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000532,
Q => blk00000003_sig000005ca
);
blk00000003_blk00000958 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig0000052f,
Q => blk00000003_sig000005c9
);
blk00000003_blk00000957 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig0000052c,
Q => blk00000003_sig000005c8
);
blk00000003_blk00000956 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000529,
Q => blk00000003_sig000005c7
);
blk00000003_blk00000955 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000526,
Q => blk00000003_sig000005c6
);
blk00000003_blk00000954 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000523,
Q => blk00000003_sig000005c5
);
blk00000003_blk00000953 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000520,
Q => blk00000003_sig000005c4
);
blk00000003_blk00000952 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig0000051d,
Q => blk00000003_sig000005c3
);
blk00000003_blk00000951 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig0000051a,
Q => blk00000003_sig000005da
);
blk00000003_blk00000950 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000517,
Q => blk00000003_sig00000094
);
blk00000003_blk0000094f : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig000005de,
Q => blk00000003_sig0000063f
);
blk00000003_blk0000094e : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig000005c2,
Q => blk00000003_sig0000063e
);
blk00000003_blk0000094d : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig000005bf,
Q => blk00000003_sig0000063d
);
blk00000003_blk0000094c : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig000005bc,
Q => blk00000003_sig0000063c
);
blk00000003_blk0000094b : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig000005b9,
Q => blk00000003_sig0000063b
);
blk00000003_blk0000094a : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig000005b6,
Q => blk00000003_sig0000063a
);
blk00000003_blk00000949 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig000005b3,
Q => blk00000003_sig00000639
);
blk00000003_blk00000948 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig000005b0,
Q => blk00000003_sig00000638
);
blk00000003_blk00000947 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig000005ad,
Q => blk00000003_sig00000637
);
blk00000003_blk00000946 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig000005aa,
Q => blk00000003_sig00000636
);
blk00000003_blk00000945 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig000005a7,
Q => blk00000003_sig00000635
);
blk00000003_blk00000944 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig000005a4,
Q => blk00000003_sig00000634
);
blk00000003_blk00000943 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig000005a1,
Q => blk00000003_sig00000633
);
blk00000003_blk00000942 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig0000059e,
Q => blk00000003_sig00000632
);
blk00000003_blk00000941 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig0000059b,
Q => blk00000003_sig00000631
);
blk00000003_blk00000940 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000598,
Q => blk00000003_sig00000630
);
blk00000003_blk0000093f : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000595,
Q => blk00000003_sig0000062f
);
blk00000003_blk0000093e : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000592,
Q => blk00000003_sig0000062e
);
blk00000003_blk0000093d : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig0000058f,
Q => blk00000003_sig0000062d
);
blk00000003_blk0000093c : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig0000058c,
Q => blk00000003_sig0000062c
);
blk00000003_blk0000093b : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000589,
Q => blk00000003_sig0000062b
);
blk00000003_blk0000093a : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000586,
Q => blk00000003_sig0000062a
);
blk00000003_blk00000939 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000583,
Q => blk00000003_sig00000629
);
blk00000003_blk00000938 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000580,
Q => blk00000003_sig00000640
);
blk00000003_blk00000937 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig0000057d,
Q => blk00000003_sig00000086
);
blk00000003_blk00000936 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000644,
Q => blk00000003_sig000006a5
);
blk00000003_blk00000935 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000628,
Q => blk00000003_sig000006a4
);
blk00000003_blk00000934 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000625,
Q => blk00000003_sig000006a3
);
blk00000003_blk00000933 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000622,
Q => blk00000003_sig000006a2
);
blk00000003_blk00000932 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig0000061f,
Q => blk00000003_sig000006a1
);
blk00000003_blk00000931 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig0000061c,
Q => blk00000003_sig000006a0
);
blk00000003_blk00000930 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000619,
Q => blk00000003_sig0000069f
);
blk00000003_blk0000092f : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000616,
Q => blk00000003_sig0000069e
);
blk00000003_blk0000092e : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000613,
Q => blk00000003_sig0000069d
);
blk00000003_blk0000092d : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000610,
Q => blk00000003_sig0000069c
);
blk00000003_blk0000092c : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig0000060d,
Q => blk00000003_sig0000069b
);
blk00000003_blk0000092b : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig0000060a,
Q => blk00000003_sig0000069a
);
blk00000003_blk0000092a : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000607,
Q => blk00000003_sig00000699
);
blk00000003_blk00000929 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000604,
Q => blk00000003_sig00000698
);
blk00000003_blk00000928 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000601,
Q => blk00000003_sig00000697
);
blk00000003_blk00000927 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig000005fe,
Q => blk00000003_sig00000696
);
blk00000003_blk00000926 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig000005fb,
Q => blk00000003_sig00000695
);
blk00000003_blk00000925 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig000005f8,
Q => blk00000003_sig00000694
);
blk00000003_blk00000924 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig000005f5,
Q => blk00000003_sig00000693
);
blk00000003_blk00000923 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig000005f2,
Q => blk00000003_sig00000692
);
blk00000003_blk00000922 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig000005ef,
Q => blk00000003_sig00000691
);
blk00000003_blk00000921 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig000005ec,
Q => blk00000003_sig00000690
);
blk00000003_blk00000920 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig000005e9,
Q => blk00000003_sig0000068f
);
blk00000003_blk0000091f : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig000005e6,
Q => blk00000003_sig000006a6
);
blk00000003_blk0000091e : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig000005e3,
Q => blk00000003_sig00000cc8
);
blk00000003_blk0000091d : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig000006aa,
Q => blk00000003_sig0000070b
);
blk00000003_blk0000091c : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig0000068e,
Q => blk00000003_sig0000070a
);
blk00000003_blk0000091b : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig0000068b,
Q => blk00000003_sig00000709
);
blk00000003_blk0000091a : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000688,
Q => blk00000003_sig00000708
);
blk00000003_blk00000919 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000685,
Q => blk00000003_sig00000707
);
blk00000003_blk00000918 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000682,
Q => blk00000003_sig00000706
);
blk00000003_blk00000917 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig0000067f,
Q => blk00000003_sig00000705
);
blk00000003_blk00000916 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig0000067c,
Q => blk00000003_sig00000704
);
blk00000003_blk00000915 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000679,
Q => blk00000003_sig00000703
);
blk00000003_blk00000914 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000676,
Q => blk00000003_sig00000702
);
blk00000003_blk00000913 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000673,
Q => blk00000003_sig00000701
);
blk00000003_blk00000912 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000670,
Q => blk00000003_sig00000700
);
blk00000003_blk00000911 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig0000066d,
Q => blk00000003_sig000006ff
);
blk00000003_blk00000910 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig0000066a,
Q => blk00000003_sig000006fe
);
blk00000003_blk0000090f : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000667,
Q => blk00000003_sig000006fd
);
blk00000003_blk0000090e : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000664,
Q => blk00000003_sig000006fc
);
blk00000003_blk0000090d : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000661,
Q => blk00000003_sig000006fb
);
blk00000003_blk0000090c : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig0000065e,
Q => blk00000003_sig000006fa
);
blk00000003_blk0000090b : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig0000065b,
Q => blk00000003_sig000006f9
);
blk00000003_blk0000090a : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000658,
Q => blk00000003_sig000006f8
);
blk00000003_blk00000909 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000655,
Q => blk00000003_sig000006f7
);
blk00000003_blk00000908 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000652,
Q => blk00000003_sig000006f6
);
blk00000003_blk00000907 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig0000064f,
Q => blk00000003_sig000006f5
);
blk00000003_blk00000906 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig0000064c,
Q => blk00000003_sig0000070c
);
blk00000003_blk00000905 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000649,
Q => blk00000003_sig00000cc7
);
blk00000003_blk00000904 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000710,
Q => blk00000003_sig00000771
);
blk00000003_blk00000903 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig000006f4,
Q => blk00000003_sig00000770
);
blk00000003_blk00000902 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig000006f1,
Q => blk00000003_sig0000076f
);
blk00000003_blk00000901 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig000006ee,
Q => blk00000003_sig0000076e
);
blk00000003_blk00000900 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig000006eb,
Q => blk00000003_sig0000076d
);
blk00000003_blk000008ff : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig000006e8,
Q => blk00000003_sig0000076c
);
blk00000003_blk000008fe : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig000006e5,
Q => blk00000003_sig0000076b
);
blk00000003_blk000008fd : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig000006e2,
Q => blk00000003_sig0000076a
);
blk00000003_blk000008fc : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig000006df,
Q => blk00000003_sig00000769
);
blk00000003_blk000008fb : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig000006dc,
Q => blk00000003_sig00000768
);
blk00000003_blk000008fa : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig000006d9,
Q => blk00000003_sig00000767
);
blk00000003_blk000008f9 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig000006d6,
Q => blk00000003_sig00000766
);
blk00000003_blk000008f8 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig000006d3,
Q => blk00000003_sig00000765
);
blk00000003_blk000008f7 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig000006d0,
Q => blk00000003_sig00000764
);
blk00000003_blk000008f6 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig000006cd,
Q => blk00000003_sig00000763
);
blk00000003_blk000008f5 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig000006ca,
Q => blk00000003_sig00000762
);
blk00000003_blk000008f4 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig000006c7,
Q => blk00000003_sig00000761
);
blk00000003_blk000008f3 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig000006c4,
Q => blk00000003_sig00000760
);
blk00000003_blk000008f2 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig000006c1,
Q => blk00000003_sig0000075f
);
blk00000003_blk000008f1 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig000006be,
Q => blk00000003_sig0000075e
);
blk00000003_blk000008f0 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig000006bb,
Q => blk00000003_sig0000075d
);
blk00000003_blk000008ef : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig000006b8,
Q => blk00000003_sig0000075c
);
blk00000003_blk000008ee : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig000006b5,
Q => blk00000003_sig0000075b
);
blk00000003_blk000008ed : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig000006b2,
Q => blk00000003_sig00000772
);
blk00000003_blk000008ec : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig000006af,
Q => blk00000003_sig00000cc6
);
blk00000003_blk000008eb : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000776,
Q => blk00000003_sig000007d7
);
blk00000003_blk000008ea : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig0000075a,
Q => blk00000003_sig000007d6
);
blk00000003_blk000008e9 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000757,
Q => blk00000003_sig000007d5
);
blk00000003_blk000008e8 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000754,
Q => blk00000003_sig000007d4
);
blk00000003_blk000008e7 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000751,
Q => blk00000003_sig000007d3
);
blk00000003_blk000008e6 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig0000074e,
Q => blk00000003_sig000007d2
);
blk00000003_blk000008e5 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig0000074b,
Q => blk00000003_sig000007d1
);
blk00000003_blk000008e4 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000748,
Q => blk00000003_sig000007d0
);
blk00000003_blk000008e3 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000745,
Q => blk00000003_sig000007cf
);
blk00000003_blk000008e2 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000742,
Q => blk00000003_sig000007ce
);
blk00000003_blk000008e1 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig0000073f,
Q => blk00000003_sig000007cd
);
blk00000003_blk000008e0 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig0000073c,
Q => blk00000003_sig000007cc
);
blk00000003_blk000008df : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000739,
Q => blk00000003_sig000007cb
);
blk00000003_blk000008de : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000736,
Q => blk00000003_sig000007ca
);
blk00000003_blk000008dd : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000733,
Q => blk00000003_sig000007c9
);
blk00000003_blk000008dc : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000730,
Q => blk00000003_sig000007c8
);
blk00000003_blk000008db : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig0000072d,
Q => blk00000003_sig000007c7
);
blk00000003_blk000008da : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig0000072a,
Q => blk00000003_sig000007c6
);
blk00000003_blk000008d9 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000727,
Q => blk00000003_sig000007c5
);
blk00000003_blk000008d8 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000724,
Q => blk00000003_sig000007c4
);
blk00000003_blk000008d7 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000721,
Q => blk00000003_sig000007c3
);
blk00000003_blk000008d6 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig0000071e,
Q => blk00000003_sig000007c2
);
blk00000003_blk000008d5 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig0000071b,
Q => blk00000003_sig000007c1
);
blk00000003_blk000008d4 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000718,
Q => blk00000003_sig000007d8
);
blk00000003_blk000008d3 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000715,
Q => blk00000003_sig00000cc5
);
blk00000003_blk000008d2 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig000007dc,
Q => blk00000003_sig0000083d
);
blk00000003_blk000008d1 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig000007c0,
Q => blk00000003_sig0000083c
);
blk00000003_blk000008d0 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig000007bd,
Q => blk00000003_sig0000083b
);
blk00000003_blk000008cf : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig000007ba,
Q => blk00000003_sig0000083a
);
blk00000003_blk000008ce : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig000007b7,
Q => blk00000003_sig00000839
);
blk00000003_blk000008cd : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig000007b4,
Q => blk00000003_sig00000838
);
blk00000003_blk000008cc : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig000007b1,
Q => blk00000003_sig00000837
);
blk00000003_blk000008cb : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig000007ae,
Q => blk00000003_sig00000836
);
blk00000003_blk000008ca : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig000007ab,
Q => blk00000003_sig00000835
);
blk00000003_blk000008c9 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig000007a8,
Q => blk00000003_sig00000834
);
blk00000003_blk000008c8 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig000007a5,
Q => blk00000003_sig00000833
);
blk00000003_blk000008c7 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig000007a2,
Q => blk00000003_sig00000832
);
blk00000003_blk000008c6 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig0000079f,
Q => blk00000003_sig00000831
);
blk00000003_blk000008c5 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig0000079c,
Q => blk00000003_sig00000830
);
blk00000003_blk000008c4 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000799,
Q => blk00000003_sig0000082f
);
blk00000003_blk000008c3 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000796,
Q => blk00000003_sig0000082e
);
blk00000003_blk000008c2 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000793,
Q => blk00000003_sig0000082d
);
blk00000003_blk000008c1 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000790,
Q => blk00000003_sig0000082c
);
blk00000003_blk000008c0 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig0000078d,
Q => blk00000003_sig0000082b
);
blk00000003_blk000008bf : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig0000078a,
Q => blk00000003_sig0000082a
);
blk00000003_blk000008be : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000787,
Q => blk00000003_sig00000829
);
blk00000003_blk000008bd : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000784,
Q => blk00000003_sig00000828
);
blk00000003_blk000008bc : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000781,
Q => blk00000003_sig00000827
);
blk00000003_blk000008bb : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig0000077e,
Q => blk00000003_sig0000083e
);
blk00000003_blk000008ba : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig0000077b,
Q => blk00000003_sig00000cc4
);
blk00000003_blk000008b9 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000842,
Q => blk00000003_sig000008a3
);
blk00000003_blk000008b8 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000826,
Q => blk00000003_sig000008a2
);
blk00000003_blk000008b7 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000823,
Q => blk00000003_sig000008a1
);
blk00000003_blk000008b6 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000820,
Q => blk00000003_sig000008a0
);
blk00000003_blk000008b5 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig0000081d,
Q => blk00000003_sig0000089f
);
blk00000003_blk000008b4 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig0000081a,
Q => blk00000003_sig0000089e
);
blk00000003_blk000008b3 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000817,
Q => blk00000003_sig0000089d
);
blk00000003_blk000008b2 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000814,
Q => blk00000003_sig0000089c
);
blk00000003_blk000008b1 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000811,
Q => blk00000003_sig0000089b
);
blk00000003_blk000008b0 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig0000080e,
Q => blk00000003_sig0000089a
);
blk00000003_blk000008af : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig0000080b,
Q => blk00000003_sig00000899
);
blk00000003_blk000008ae : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000808,
Q => blk00000003_sig00000898
);
blk00000003_blk000008ad : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000805,
Q => blk00000003_sig00000897
);
blk00000003_blk000008ac : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000802,
Q => blk00000003_sig00000896
);
blk00000003_blk000008ab : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig000007ff,
Q => blk00000003_sig00000895
);
blk00000003_blk000008aa : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig000007fc,
Q => blk00000003_sig00000894
);
blk00000003_blk000008a9 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig000007f9,
Q => blk00000003_sig00000893
);
blk00000003_blk000008a8 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig000007f6,
Q => blk00000003_sig00000892
);
blk00000003_blk000008a7 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig000007f3,
Q => blk00000003_sig00000891
);
blk00000003_blk000008a6 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig000007f0,
Q => blk00000003_sig00000890
);
blk00000003_blk000008a5 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig000007ed,
Q => blk00000003_sig0000088f
);
blk00000003_blk000008a4 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig000007ea,
Q => blk00000003_sig0000088e
);
blk00000003_blk000008a3 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig000007e7,
Q => blk00000003_sig0000088d
);
blk00000003_blk000008a2 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig000007e4,
Q => blk00000003_sig000008a4
);
blk00000003_blk000008a1 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig000007e1,
Q => blk00000003_sig00000cc3
);
blk00000003_blk000008a0 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig000008a8,
Q => blk00000003_sig00000909
);
blk00000003_blk0000089f : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig0000088c,
Q => blk00000003_sig00000908
);
blk00000003_blk0000089e : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000889,
Q => blk00000003_sig00000907
);
blk00000003_blk0000089d : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000886,
Q => blk00000003_sig00000906
);
blk00000003_blk0000089c : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000883,
Q => blk00000003_sig00000905
);
blk00000003_blk0000089b : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000880,
Q => blk00000003_sig00000904
);
blk00000003_blk0000089a : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig0000087d,
Q => blk00000003_sig00000903
);
blk00000003_blk00000899 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig0000087a,
Q => blk00000003_sig00000902
);
blk00000003_blk00000898 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000877,
Q => blk00000003_sig00000901
);
blk00000003_blk00000897 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000874,
Q => blk00000003_sig00000900
);
blk00000003_blk00000896 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000871,
Q => blk00000003_sig000008ff
);
blk00000003_blk00000895 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig0000086e,
Q => blk00000003_sig000008fe
);
blk00000003_blk00000894 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig0000086b,
Q => blk00000003_sig000008fd
);
blk00000003_blk00000893 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000868,
Q => blk00000003_sig000008fc
);
blk00000003_blk00000892 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000865,
Q => blk00000003_sig000008fb
);
blk00000003_blk00000891 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000862,
Q => blk00000003_sig000008fa
);
blk00000003_blk00000890 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig0000085f,
Q => blk00000003_sig000008f9
);
blk00000003_blk0000088f : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig0000085c,
Q => blk00000003_sig000008f8
);
blk00000003_blk0000088e : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000859,
Q => blk00000003_sig000008f7
);
blk00000003_blk0000088d : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000856,
Q => blk00000003_sig000008f6
);
blk00000003_blk0000088c : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000853,
Q => blk00000003_sig000008f5
);
blk00000003_blk0000088b : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000850,
Q => blk00000003_sig000008f4
);
blk00000003_blk0000088a : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig0000084d,
Q => blk00000003_sig000008f3
);
blk00000003_blk00000889 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig0000084a,
Q => blk00000003_sig0000090a
);
blk00000003_blk00000888 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000847,
Q => blk00000003_sig00000cc2
);
blk00000003_blk00000887 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig0000090e,
Q => blk00000003_sig0000096f
);
blk00000003_blk00000886 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig000008f2,
Q => blk00000003_sig0000096e
);
blk00000003_blk00000885 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig000008ef,
Q => blk00000003_sig0000096d
);
blk00000003_blk00000884 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig000008ec,
Q => blk00000003_sig0000096c
);
blk00000003_blk00000883 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig000008e9,
Q => blk00000003_sig0000096b
);
blk00000003_blk00000882 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig000008e6,
Q => blk00000003_sig0000096a
);
blk00000003_blk00000881 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig000008e3,
Q => blk00000003_sig00000969
);
blk00000003_blk00000880 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig000008e0,
Q => blk00000003_sig00000968
);
blk00000003_blk0000087f : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig000008dd,
Q => blk00000003_sig00000967
);
blk00000003_blk0000087e : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig000008da,
Q => blk00000003_sig00000966
);
blk00000003_blk0000087d : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig000008d7,
Q => blk00000003_sig00000965
);
blk00000003_blk0000087c : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig000008d4,
Q => blk00000003_sig00000964
);
blk00000003_blk0000087b : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig000008d1,
Q => blk00000003_sig00000963
);
blk00000003_blk0000087a : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig000008ce,
Q => blk00000003_sig00000962
);
blk00000003_blk00000879 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig000008cb,
Q => blk00000003_sig00000961
);
blk00000003_blk00000878 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig000008c8,
Q => blk00000003_sig00000960
);
blk00000003_blk00000877 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig000008c5,
Q => blk00000003_sig0000095f
);
blk00000003_blk00000876 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig000008c2,
Q => blk00000003_sig0000095e
);
blk00000003_blk00000875 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig000008bf,
Q => blk00000003_sig0000095d
);
blk00000003_blk00000874 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig000008bc,
Q => blk00000003_sig0000095c
);
blk00000003_blk00000873 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig000008b9,
Q => blk00000003_sig0000095b
);
blk00000003_blk00000872 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig000008b6,
Q => blk00000003_sig0000095a
);
blk00000003_blk00000871 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig000008b3,
Q => blk00000003_sig00000959
);
blk00000003_blk00000870 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig000008b0,
Q => blk00000003_sig00000970
);
blk00000003_blk0000086f : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig000008ad,
Q => blk00000003_sig00000cc1
);
blk00000003_blk0000086e : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000974,
Q => blk00000003_sig000009d5
);
blk00000003_blk0000086d : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000958,
Q => blk00000003_sig000009d4
);
blk00000003_blk0000086c : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000955,
Q => blk00000003_sig000009d3
);
blk00000003_blk0000086b : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000952,
Q => blk00000003_sig000009d2
);
blk00000003_blk0000086a : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig0000094f,
Q => blk00000003_sig000009d1
);
blk00000003_blk00000869 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig0000094c,
Q => blk00000003_sig000009d0
);
blk00000003_blk00000868 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000949,
Q => blk00000003_sig000009cf
);
blk00000003_blk00000867 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000946,
Q => blk00000003_sig000009ce
);
blk00000003_blk00000866 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000943,
Q => blk00000003_sig000009cd
);
blk00000003_blk00000865 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000940,
Q => blk00000003_sig000009cc
);
blk00000003_blk00000864 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig0000093d,
Q => blk00000003_sig000009cb
);
blk00000003_blk00000863 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig0000093a,
Q => blk00000003_sig000009ca
);
blk00000003_blk00000862 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000937,
Q => blk00000003_sig000009c9
);
blk00000003_blk00000861 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000934,
Q => blk00000003_sig000009c8
);
blk00000003_blk00000860 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000931,
Q => blk00000003_sig000009c7
);
blk00000003_blk0000085f : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig0000092e,
Q => blk00000003_sig000009c6
);
blk00000003_blk0000085e : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig0000092b,
Q => blk00000003_sig000009c5
);
blk00000003_blk0000085d : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000928,
Q => blk00000003_sig000009c4
);
blk00000003_blk0000085c : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000925,
Q => blk00000003_sig000009c3
);
blk00000003_blk0000085b : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000922,
Q => blk00000003_sig000009c2
);
blk00000003_blk0000085a : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig0000091f,
Q => blk00000003_sig000009c1
);
blk00000003_blk00000859 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig0000091c,
Q => blk00000003_sig000009c0
);
blk00000003_blk00000858 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000919,
Q => blk00000003_sig000009bf
);
blk00000003_blk00000857 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000916,
Q => blk00000003_sig000009d6
);
blk00000003_blk00000856 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000913,
Q => blk00000003_sig00000cc0
);
blk00000003_blk00000855 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig000009da,
Q => blk00000003_sig00000a3b
);
blk00000003_blk00000854 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig000009be,
Q => blk00000003_sig00000a3a
);
blk00000003_blk00000853 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig000009bb,
Q => blk00000003_sig00000a39
);
blk00000003_blk00000852 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig000009b8,
Q => blk00000003_sig00000a38
);
blk00000003_blk00000851 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig000009b5,
Q => blk00000003_sig00000a37
);
blk00000003_blk00000850 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig000009b2,
Q => blk00000003_sig00000a36
);
blk00000003_blk0000084f : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig000009af,
Q => blk00000003_sig00000a35
);
blk00000003_blk0000084e : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig000009ac,
Q => blk00000003_sig00000a34
);
blk00000003_blk0000084d : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig000009a9,
Q => blk00000003_sig00000a33
);
blk00000003_blk0000084c : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig000009a6,
Q => blk00000003_sig00000a32
);
blk00000003_blk0000084b : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig000009a3,
Q => blk00000003_sig00000a31
);
blk00000003_blk0000084a : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig000009a0,
Q => blk00000003_sig00000a30
);
blk00000003_blk00000849 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig0000099d,
Q => blk00000003_sig00000a2f
);
blk00000003_blk00000848 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig0000099a,
Q => blk00000003_sig00000a2e
);
blk00000003_blk00000847 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000997,
Q => blk00000003_sig00000a2d
);
blk00000003_blk00000846 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000994,
Q => blk00000003_sig00000a2c
);
blk00000003_blk00000845 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000991,
Q => blk00000003_sig00000a2b
);
blk00000003_blk00000844 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig0000098e,
Q => blk00000003_sig00000a2a
);
blk00000003_blk00000843 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig0000098b,
Q => blk00000003_sig00000a29
);
blk00000003_blk00000842 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000988,
Q => blk00000003_sig00000a28
);
blk00000003_blk00000841 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000985,
Q => blk00000003_sig00000a27
);
blk00000003_blk00000840 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000982,
Q => blk00000003_sig00000a26
);
blk00000003_blk0000083f : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig0000097f,
Q => blk00000003_sig00000a25
);
blk00000003_blk0000083e : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig0000097c,
Q => blk00000003_sig00000a3c
);
blk00000003_blk0000083d : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000979,
Q => blk00000003_sig00000cbf
);
blk00000003_blk0000083c : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000a40,
Q => blk00000003_sig00000aa0
);
blk00000003_blk0000083b : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000a24,
Q => blk00000003_sig00000a9f
);
blk00000003_blk0000083a : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000a21,
Q => blk00000003_sig00000a9e
);
blk00000003_blk00000839 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000a1e,
Q => blk00000003_sig00000a9d
);
blk00000003_blk00000838 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000a1b,
Q => blk00000003_sig00000a9c
);
blk00000003_blk00000837 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000a18,
Q => blk00000003_sig00000a9b
);
blk00000003_blk00000836 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000a15,
Q => blk00000003_sig00000a9a
);
blk00000003_blk00000835 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000a12,
Q => blk00000003_sig00000a99
);
blk00000003_blk00000834 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000a0f,
Q => blk00000003_sig00000a98
);
blk00000003_blk00000833 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000a0c,
Q => blk00000003_sig00000a97
);
blk00000003_blk00000832 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000a09,
Q => blk00000003_sig00000a96
);
blk00000003_blk00000831 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000a06,
Q => blk00000003_sig00000a95
);
blk00000003_blk00000830 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000a03,
Q => blk00000003_sig00000a94
);
blk00000003_blk0000082f : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000a00,
Q => blk00000003_sig00000a93
);
blk00000003_blk0000082e : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig000009fd,
Q => blk00000003_sig00000a92
);
blk00000003_blk0000082d : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig000009fa,
Q => blk00000003_sig00000a91
);
blk00000003_blk0000082c : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig000009f7,
Q => blk00000003_sig00000a90
);
blk00000003_blk0000082b : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig000009f4,
Q => blk00000003_sig00000a8f
);
blk00000003_blk0000082a : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig000009f1,
Q => blk00000003_sig00000a8e
);
blk00000003_blk00000829 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig000009ee,
Q => blk00000003_sig00000a8d
);
blk00000003_blk00000828 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig000009eb,
Q => blk00000003_sig00000a8c
);
blk00000003_blk00000827 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig000009e8,
Q => blk00000003_sig00000a8b
);
blk00000003_blk00000826 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig000009e5,
Q => blk00000003_sig00000a8a
);
blk00000003_blk00000825 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig000009e2,
Q => blk00000003_sig00000aa1
);
blk00000003_blk00000824 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig000009df,
Q => blk00000003_sig00000cbe
);
blk00000003_blk00000823 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000aa5,
Q => blk00000003_sig00000b05
);
blk00000003_blk00000822 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000a89,
Q => blk00000003_sig00000b04
);
blk00000003_blk00000821 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000a86,
Q => blk00000003_sig00000b03
);
blk00000003_blk00000820 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000a83,
Q => blk00000003_sig00000b02
);
blk00000003_blk0000081f : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000a80,
Q => blk00000003_sig00000b01
);
blk00000003_blk0000081e : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000a7d,
Q => blk00000003_sig00000b00
);
blk00000003_blk0000081d : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000a7a,
Q => blk00000003_sig00000aff
);
blk00000003_blk0000081c : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000a77,
Q => blk00000003_sig00000afe
);
blk00000003_blk0000081b : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000a74,
Q => blk00000003_sig00000afd
);
blk00000003_blk0000081a : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000a71,
Q => blk00000003_sig00000afc
);
blk00000003_blk00000819 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000a6e,
Q => blk00000003_sig00000afb
);
blk00000003_blk00000818 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000a6b,
Q => blk00000003_sig00000afa
);
blk00000003_blk00000817 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000a68,
Q => blk00000003_sig00000af9
);
blk00000003_blk00000816 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000a65,
Q => blk00000003_sig00000af8
);
blk00000003_blk00000815 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000a62,
Q => blk00000003_sig00000af7
);
blk00000003_blk00000814 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000a5f,
Q => blk00000003_sig00000af6
);
blk00000003_blk00000813 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000a5c,
Q => blk00000003_sig00000af5
);
blk00000003_blk00000812 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000a59,
Q => blk00000003_sig00000af4
);
blk00000003_blk00000811 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000a56,
Q => blk00000003_sig00000af3
);
blk00000003_blk00000810 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000a53,
Q => blk00000003_sig00000af2
);
blk00000003_blk0000080f : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000a50,
Q => blk00000003_sig00000af1
);
blk00000003_blk0000080e : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000a4d,
Q => blk00000003_sig00000af0
);
blk00000003_blk0000080d : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000a4a,
Q => blk00000003_sig00000aef
);
blk00000003_blk0000080c : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000a47,
Q => blk00000003_sig00000b06
);
blk00000003_blk0000080b : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000a44,
Q => blk00000003_sig00000cbd
);
blk00000003_blk0000080a : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000b0a,
Q => blk00000003_sig00000b6a
);
blk00000003_blk00000809 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000aee,
Q => blk00000003_sig00000b69
);
blk00000003_blk00000808 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000aeb,
Q => blk00000003_sig00000b68
);
blk00000003_blk00000807 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000ae8,
Q => blk00000003_sig00000b67
);
blk00000003_blk00000806 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000ae5,
Q => blk00000003_sig00000b66
);
blk00000003_blk00000805 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000ae2,
Q => blk00000003_sig00000b65
);
blk00000003_blk00000804 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000adf,
Q => blk00000003_sig00000b64
);
blk00000003_blk00000803 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000adc,
Q => blk00000003_sig00000b63
);
blk00000003_blk00000802 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000ad9,
Q => blk00000003_sig00000b62
);
blk00000003_blk00000801 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000ad6,
Q => blk00000003_sig00000b61
);
blk00000003_blk00000800 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000ad3,
Q => blk00000003_sig00000b60
);
blk00000003_blk000007ff : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000ad0,
Q => blk00000003_sig00000b5f
);
blk00000003_blk000007fe : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000acd,
Q => blk00000003_sig00000b5e
);
blk00000003_blk000007fd : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000aca,
Q => blk00000003_sig00000b5d
);
blk00000003_blk000007fc : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000ac7,
Q => blk00000003_sig00000b5c
);
blk00000003_blk000007fb : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000ac4,
Q => blk00000003_sig00000b5b
);
blk00000003_blk000007fa : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000ac1,
Q => blk00000003_sig00000b5a
);
blk00000003_blk000007f9 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000abe,
Q => blk00000003_sig00000b59
);
blk00000003_blk000007f8 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000abb,
Q => blk00000003_sig00000b58
);
blk00000003_blk000007f7 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000ab8,
Q => blk00000003_sig00000b57
);
blk00000003_blk000007f6 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000ab5,
Q => blk00000003_sig00000b56
);
blk00000003_blk000007f5 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000ab2,
Q => blk00000003_sig00000b55
);
blk00000003_blk000007f4 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000aaf,
Q => blk00000003_sig00000b54
);
blk00000003_blk000007f3 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000aac,
Q => blk00000003_sig00000b6b
);
blk00000003_blk000007f2 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000aa9,
Q => blk00000003_sig00000cbc
);
blk00000003_blk000007f1 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000b6f,
Q => blk00000003_sig00000bcf
);
blk00000003_blk000007f0 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000b53,
Q => blk00000003_sig00000bce
);
blk00000003_blk000007ef : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000b50,
Q => blk00000003_sig00000bcd
);
blk00000003_blk000007ee : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000b4d,
Q => blk00000003_sig00000bcc
);
blk00000003_blk000007ed : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000b4a,
Q => blk00000003_sig00000bcb
);
blk00000003_blk000007ec : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000b47,
Q => blk00000003_sig00000bca
);
blk00000003_blk000007eb : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000b44,
Q => blk00000003_sig00000bc9
);
blk00000003_blk000007ea : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000b41,
Q => blk00000003_sig00000bc8
);
blk00000003_blk000007e9 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000b3e,
Q => blk00000003_sig00000bc7
);
blk00000003_blk000007e8 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000b3b,
Q => blk00000003_sig00000bc6
);
blk00000003_blk000007e7 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000b38,
Q => blk00000003_sig00000bc5
);
blk00000003_blk000007e6 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000b35,
Q => blk00000003_sig00000bc4
);
blk00000003_blk000007e5 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000b32,
Q => blk00000003_sig00000bc3
);
blk00000003_blk000007e4 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000b2f,
Q => blk00000003_sig00000bc2
);
blk00000003_blk000007e3 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000b2c,
Q => blk00000003_sig00000bc1
);
blk00000003_blk000007e2 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000b29,
Q => blk00000003_sig00000bc0
);
blk00000003_blk000007e1 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000b26,
Q => blk00000003_sig00000bbf
);
blk00000003_blk000007e0 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000b23,
Q => blk00000003_sig00000bbe
);
blk00000003_blk000007df : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000b20,
Q => blk00000003_sig00000bbd
);
blk00000003_blk000007de : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000b1d,
Q => blk00000003_sig00000bbc
);
blk00000003_blk000007dd : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000b1a,
Q => blk00000003_sig00000bbb
);
blk00000003_blk000007dc : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000b17,
Q => blk00000003_sig00000bba
);
blk00000003_blk000007db : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000b14,
Q => blk00000003_sig00000bb9
);
blk00000003_blk000007da : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000b11,
Q => blk00000003_sig00000bd0
);
blk00000003_blk000007d9 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000b0e,
Q => blk00000003_sig00000cbb
);
blk00000003_blk000007d8 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000bd4,
Q => blk00000003_sig00000c34
);
blk00000003_blk000007d7 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000bb8,
Q => blk00000003_sig00000c33
);
blk00000003_blk000007d6 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000bb5,
Q => blk00000003_sig00000c32
);
blk00000003_blk000007d5 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000bb2,
Q => blk00000003_sig00000c31
);
blk00000003_blk000007d4 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000baf,
Q => blk00000003_sig00000c30
);
blk00000003_blk000007d3 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000bac,
Q => blk00000003_sig00000c2f
);
blk00000003_blk000007d2 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000ba9,
Q => blk00000003_sig00000c2e
);
blk00000003_blk000007d1 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000ba6,
Q => blk00000003_sig00000c2d
);
blk00000003_blk000007d0 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000ba3,
Q => blk00000003_sig00000c2c
);
blk00000003_blk000007cf : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000ba0,
Q => blk00000003_sig00000c2b
);
blk00000003_blk000007ce : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000b9d,
Q => blk00000003_sig00000c2a
);
blk00000003_blk000007cd : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000b9a,
Q => blk00000003_sig00000c29
);
blk00000003_blk000007cc : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000b97,
Q => blk00000003_sig00000c28
);
blk00000003_blk000007cb : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000b94,
Q => blk00000003_sig00000c27
);
blk00000003_blk000007ca : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000b91,
Q => blk00000003_sig00000c26
);
blk00000003_blk000007c9 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000b8e,
Q => blk00000003_sig00000c25
);
blk00000003_blk000007c8 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000b8b,
Q => blk00000003_sig00000c24
);
blk00000003_blk000007c7 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000b88,
Q => blk00000003_sig00000c23
);
blk00000003_blk000007c6 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000b85,
Q => blk00000003_sig00000c22
);
blk00000003_blk000007c5 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000b82,
Q => blk00000003_sig00000c21
);
blk00000003_blk000007c4 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000b7f,
Q => blk00000003_sig00000c20
);
blk00000003_blk000007c3 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000b7c,
Q => blk00000003_sig00000c1f
);
blk00000003_blk000007c2 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000b79,
Q => blk00000003_sig00000c1e
);
blk00000003_blk000007c1 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000b76,
Q => blk00000003_sig00000c35
);
blk00000003_blk000007c0 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000b73,
Q => blk00000003_sig00000cba
);
blk00000003_blk000007bf : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000c39,
Q => blk00000003_sig00000c99
);
blk00000003_blk000007be : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000c1d,
Q => blk00000003_sig00000c98
);
blk00000003_blk000007bd : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000c1a,
Q => blk00000003_sig00000c97
);
blk00000003_blk000007bc : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000c17,
Q => blk00000003_sig00000c96
);
blk00000003_blk000007bb : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000c14,
Q => blk00000003_sig00000c95
);
blk00000003_blk000007ba : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000c11,
Q => blk00000003_sig00000c94
);
blk00000003_blk000007b9 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000c0e,
Q => blk00000003_sig00000c93
);
blk00000003_blk000007b8 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000c0b,
Q => blk00000003_sig00000c92
);
blk00000003_blk000007b7 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000c08,
Q => blk00000003_sig00000c91
);
blk00000003_blk000007b6 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000c05,
Q => blk00000003_sig00000c90
);
blk00000003_blk000007b5 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000c02,
Q => blk00000003_sig00000c8f
);
blk00000003_blk000007b4 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000bff,
Q => blk00000003_sig00000c8e
);
blk00000003_blk000007b3 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000bfc,
Q => blk00000003_sig00000c8d
);
blk00000003_blk000007b2 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000bf9,
Q => blk00000003_sig00000c8c
);
blk00000003_blk000007b1 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000bf6,
Q => blk00000003_sig00000c8b
);
blk00000003_blk000007b0 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000bf3,
Q => blk00000003_sig00000c8a
);
blk00000003_blk000007af : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000bf0,
Q => blk00000003_sig00000c89
);
blk00000003_blk000007ae : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000bed,
Q => blk00000003_sig00000c88
);
blk00000003_blk000007ad : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000bea,
Q => blk00000003_sig00000c87
);
blk00000003_blk000007ac : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000be7,
Q => blk00000003_sig00000c86
);
blk00000003_blk000007ab : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000be4,
Q => blk00000003_sig00000c85
);
blk00000003_blk000007aa : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000be1,
Q => blk00000003_sig00000c84
);
blk00000003_blk000007a9 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000bde,
Q => blk00000003_sig00000c83
);
blk00000003_blk000007a8 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000bdb,
Q => blk00000003_sig00000c9a
);
blk00000003_blk000007a7 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000bd8,
Q => blk00000003_sig00000cb9
);
blk00000003_blk000007a6 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000c9e,
Q => blk00000003_sig00000cb8
);
blk00000003_blk000007a5 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000c82,
Q => blk00000003_sig00000cb7
);
blk00000003_blk000007a4 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000c7f,
Q => blk00000003_sig00000cb6
);
blk00000003_blk000007a3 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000c7c,
Q => blk00000003_sig00000cb5
);
blk00000003_blk000007a2 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000c79,
Q => blk00000003_sig00000cb4
);
blk00000003_blk000007a1 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000c76,
Q => blk00000003_sig00000cb3
);
blk00000003_blk000007a0 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000c73,
Q => blk00000003_sig00000cb2
);
blk00000003_blk0000079f : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000c70,
Q => blk00000003_sig00000cb1
);
blk00000003_blk0000079e : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000c6d,
Q => blk00000003_sig00000cb0
);
blk00000003_blk0000079d : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000c6a,
Q => blk00000003_sig00000caf
);
blk00000003_blk0000079c : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000c67,
Q => blk00000003_sig00000cae
);
blk00000003_blk0000079b : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000c64,
Q => blk00000003_sig00000cad
);
blk00000003_blk0000079a : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000c61,
Q => blk00000003_sig00000cac
);
blk00000003_blk00000799 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000c5e,
Q => blk00000003_sig00000cab
);
blk00000003_blk00000798 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000c5b,
Q => blk00000003_sig00000caa
);
blk00000003_blk00000797 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000c58,
Q => blk00000003_sig00000ca9
);
blk00000003_blk00000796 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000c55,
Q => blk00000003_sig00000ca8
);
blk00000003_blk00000795 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000c52,
Q => blk00000003_sig00000ca7
);
blk00000003_blk00000794 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000c4f,
Q => blk00000003_sig00000ca6
);
blk00000003_blk00000793 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000c4c,
Q => blk00000003_sig00000ca5
);
blk00000003_blk00000792 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000c49,
Q => blk00000003_sig00000ca4
);
blk00000003_blk00000791 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000c46,
Q => blk00000003_sig00000ca3
);
blk00000003_blk00000790 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000c43,
Q => blk00000003_sig00000ca2
);
blk00000003_blk0000078f : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000c40,
Q => blk00000003_sig00000ca1
);
blk00000003_blk0000078e : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000c3d,
Q => blk00000003_sig00000ca0
);
blk00000003_blk0000078d : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000c9b,
Q => blk00000003_sig00000c9f
);
blk00000003_blk0000078c : MUXCY
port map (
CI => blk00000003_sig00000c9c,
DI => blk00000003_sig000000a9,
S => blk00000003_sig00000c9d,
O => blk00000003_sig00000c80
);
blk00000003_blk0000078b : XORCY
port map (
CI => blk00000003_sig00000c9c,
LI => blk00000003_sig00000c9d,
O => blk00000003_sig00000c9e
);
blk00000003_blk0000078a : MUXCY
port map (
CI => blk00000003_sig00000c3b,
DI => blk00000003_sig00000c9a,
S => blk00000003_sig00000c3c,
O => blk00000003_sig00000c9b
);
blk00000003_blk00000789 : MUXCY
port map (
CI => blk00000003_sig00000c80,
DI => blk00000003_sig00000c99,
S => blk00000003_sig00000c81,
O => blk00000003_sig00000c7d
);
blk00000003_blk00000788 : MUXCY
port map (
CI => blk00000003_sig00000c7d,
DI => blk00000003_sig00000c98,
S => blk00000003_sig00000c7e,
O => blk00000003_sig00000c7a
);
blk00000003_blk00000787 : MUXCY
port map (
CI => blk00000003_sig00000c7a,
DI => blk00000003_sig00000c97,
S => blk00000003_sig00000c7b,
O => blk00000003_sig00000c77
);
blk00000003_blk00000786 : MUXCY
port map (
CI => blk00000003_sig00000c77,
DI => blk00000003_sig00000c96,
S => blk00000003_sig00000c78,
O => blk00000003_sig00000c74
);
blk00000003_blk00000785 : MUXCY
port map (
CI => blk00000003_sig00000c74,
DI => blk00000003_sig00000c95,
S => blk00000003_sig00000c75,
O => blk00000003_sig00000c71
);
blk00000003_blk00000784 : MUXCY
port map (
CI => blk00000003_sig00000c71,
DI => blk00000003_sig00000c94,
S => blk00000003_sig00000c72,
O => blk00000003_sig00000c6e
);
blk00000003_blk00000783 : MUXCY
port map (
CI => blk00000003_sig00000c6e,
DI => blk00000003_sig00000c93,
S => blk00000003_sig00000c6f,
O => blk00000003_sig00000c6b
);
blk00000003_blk00000782 : MUXCY
port map (
CI => blk00000003_sig00000c6b,
DI => blk00000003_sig00000c92,
S => blk00000003_sig00000c6c,
O => blk00000003_sig00000c68
);
blk00000003_blk00000781 : MUXCY
port map (
CI => blk00000003_sig00000c68,
DI => blk00000003_sig00000c91,
S => blk00000003_sig00000c69,
O => blk00000003_sig00000c65
);
blk00000003_blk00000780 : MUXCY
port map (
CI => blk00000003_sig00000c65,
DI => blk00000003_sig00000c90,
S => blk00000003_sig00000c66,
O => blk00000003_sig00000c62
);
blk00000003_blk0000077f : MUXCY
port map (
CI => blk00000003_sig00000c62,
DI => blk00000003_sig00000c8f,
S => blk00000003_sig00000c63,
O => blk00000003_sig00000c5f
);
blk00000003_blk0000077e : MUXCY
port map (
CI => blk00000003_sig00000c5f,
DI => blk00000003_sig00000c8e,
S => blk00000003_sig00000c60,
O => blk00000003_sig00000c5c
);
blk00000003_blk0000077d : MUXCY
port map (
CI => blk00000003_sig00000c5c,
DI => blk00000003_sig00000c8d,
S => blk00000003_sig00000c5d,
O => blk00000003_sig00000c59
);
blk00000003_blk0000077c : MUXCY
port map (
CI => blk00000003_sig00000c59,
DI => blk00000003_sig00000c8c,
S => blk00000003_sig00000c5a,
O => blk00000003_sig00000c56
);
blk00000003_blk0000077b : MUXCY
port map (
CI => blk00000003_sig00000c56,
DI => blk00000003_sig00000c8b,
S => blk00000003_sig00000c57,
O => blk00000003_sig00000c53
);
blk00000003_blk0000077a : MUXCY
port map (
CI => blk00000003_sig00000c53,
DI => blk00000003_sig00000c8a,
S => blk00000003_sig00000c54,
O => blk00000003_sig00000c50
);
blk00000003_blk00000779 : MUXCY
port map (
CI => blk00000003_sig00000c50,
DI => blk00000003_sig00000c89,
S => blk00000003_sig00000c51,
O => blk00000003_sig00000c4d
);
blk00000003_blk00000778 : MUXCY
port map (
CI => blk00000003_sig00000c4d,
DI => blk00000003_sig00000c88,
S => blk00000003_sig00000c4e,
O => blk00000003_sig00000c4a
);
blk00000003_blk00000777 : MUXCY
port map (
CI => blk00000003_sig00000c4a,
DI => blk00000003_sig00000c87,
S => blk00000003_sig00000c4b,
O => blk00000003_sig00000c47
);
blk00000003_blk00000776 : MUXCY
port map (
CI => blk00000003_sig00000c47,
DI => blk00000003_sig00000c86,
S => blk00000003_sig00000c48,
O => blk00000003_sig00000c44
);
blk00000003_blk00000775 : MUXCY
port map (
CI => blk00000003_sig00000c44,
DI => blk00000003_sig00000c85,
S => blk00000003_sig00000c45,
O => blk00000003_sig00000c41
);
blk00000003_blk00000774 : MUXCY
port map (
CI => blk00000003_sig00000c41,
DI => blk00000003_sig00000c84,
S => blk00000003_sig00000c42,
O => blk00000003_sig00000c3e
);
blk00000003_blk00000773 : MUXCY
port map (
CI => blk00000003_sig00000c3e,
DI => blk00000003_sig00000c83,
S => blk00000003_sig00000c3f,
O => blk00000003_sig00000c3b
);
blk00000003_blk00000772 : XORCY
port map (
CI => blk00000003_sig00000c80,
LI => blk00000003_sig00000c81,
O => blk00000003_sig00000c82
);
blk00000003_blk00000771 : XORCY
port map (
CI => blk00000003_sig00000c7d,
LI => blk00000003_sig00000c7e,
O => blk00000003_sig00000c7f
);
blk00000003_blk00000770 : XORCY
port map (
CI => blk00000003_sig00000c7a,
LI => blk00000003_sig00000c7b,
O => blk00000003_sig00000c7c
);
blk00000003_blk0000076f : XORCY
port map (
CI => blk00000003_sig00000c77,
LI => blk00000003_sig00000c78,
O => blk00000003_sig00000c79
);
blk00000003_blk0000076e : XORCY
port map (
CI => blk00000003_sig00000c74,
LI => blk00000003_sig00000c75,
O => blk00000003_sig00000c76
);
blk00000003_blk0000076d : XORCY
port map (
CI => blk00000003_sig00000c71,
LI => blk00000003_sig00000c72,
O => blk00000003_sig00000c73
);
blk00000003_blk0000076c : XORCY
port map (
CI => blk00000003_sig00000c6e,
LI => blk00000003_sig00000c6f,
O => blk00000003_sig00000c70
);
blk00000003_blk0000076b : XORCY
port map (
CI => blk00000003_sig00000c6b,
LI => blk00000003_sig00000c6c,
O => blk00000003_sig00000c6d
);
blk00000003_blk0000076a : XORCY
port map (
CI => blk00000003_sig00000c68,
LI => blk00000003_sig00000c69,
O => blk00000003_sig00000c6a
);
blk00000003_blk00000769 : XORCY
port map (
CI => blk00000003_sig00000c65,
LI => blk00000003_sig00000c66,
O => blk00000003_sig00000c67
);
blk00000003_blk00000768 : XORCY
port map (
CI => blk00000003_sig00000c62,
LI => blk00000003_sig00000c63,
O => blk00000003_sig00000c64
);
blk00000003_blk00000767 : XORCY
port map (
CI => blk00000003_sig00000c5f,
LI => blk00000003_sig00000c60,
O => blk00000003_sig00000c61
);
blk00000003_blk00000766 : XORCY
port map (
CI => blk00000003_sig00000c5c,
LI => blk00000003_sig00000c5d,
O => blk00000003_sig00000c5e
);
blk00000003_blk00000765 : XORCY
port map (
CI => blk00000003_sig00000c59,
LI => blk00000003_sig00000c5a,
O => blk00000003_sig00000c5b
);
blk00000003_blk00000764 : XORCY
port map (
CI => blk00000003_sig00000c56,
LI => blk00000003_sig00000c57,
O => blk00000003_sig00000c58
);
blk00000003_blk00000763 : XORCY
port map (
CI => blk00000003_sig00000c53,
LI => blk00000003_sig00000c54,
O => blk00000003_sig00000c55
);
blk00000003_blk00000762 : XORCY
port map (
CI => blk00000003_sig00000c50,
LI => blk00000003_sig00000c51,
O => blk00000003_sig00000c52
);
blk00000003_blk00000761 : XORCY
port map (
CI => blk00000003_sig00000c4d,
LI => blk00000003_sig00000c4e,
O => blk00000003_sig00000c4f
);
blk00000003_blk00000760 : XORCY
port map (
CI => blk00000003_sig00000c4a,
LI => blk00000003_sig00000c4b,
O => blk00000003_sig00000c4c
);
blk00000003_blk0000075f : XORCY
port map (
CI => blk00000003_sig00000c47,
LI => blk00000003_sig00000c48,
O => blk00000003_sig00000c49
);
blk00000003_blk0000075e : XORCY
port map (
CI => blk00000003_sig00000c44,
LI => blk00000003_sig00000c45,
O => blk00000003_sig00000c46
);
blk00000003_blk0000075d : XORCY
port map (
CI => blk00000003_sig00000c41,
LI => blk00000003_sig00000c42,
O => blk00000003_sig00000c43
);
blk00000003_blk0000075c : XORCY
port map (
CI => blk00000003_sig00000c3e,
LI => blk00000003_sig00000c3f,
O => blk00000003_sig00000c40
);
blk00000003_blk0000075b : XORCY
port map (
CI => blk00000003_sig00000c3b,
LI => blk00000003_sig00000c3c,
O => blk00000003_sig00000c3d
);
blk00000003_blk0000075a : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000c36,
Q => blk00000003_sig00000c3a
);
blk00000003_blk00000759 : MUXCY
port map (
CI => blk00000003_sig00000c37,
DI => blk00000003_sig00000067,
S => blk00000003_sig00000c38,
O => blk00000003_sig00000c1b
);
blk00000003_blk00000758 : XORCY
port map (
CI => blk00000003_sig00000c37,
LI => blk00000003_sig00000c38,
O => blk00000003_sig00000c39
);
blk00000003_blk00000757 : MUXCY
port map (
CI => blk00000003_sig00000bd6,
DI => blk00000003_sig00000c35,
S => blk00000003_sig00000bd7,
O => blk00000003_sig00000c36
);
blk00000003_blk00000756 : MUXCY
port map (
CI => blk00000003_sig00000c1b,
DI => blk00000003_sig00000c34,
S => blk00000003_sig00000c1c,
O => blk00000003_sig00000c18
);
blk00000003_blk00000755 : MUXCY
port map (
CI => blk00000003_sig00000c18,
DI => blk00000003_sig00000c33,
S => blk00000003_sig00000c19,
O => blk00000003_sig00000c15
);
blk00000003_blk00000754 : MUXCY
port map (
CI => blk00000003_sig00000c15,
DI => blk00000003_sig00000c32,
S => blk00000003_sig00000c16,
O => blk00000003_sig00000c12
);
blk00000003_blk00000753 : MUXCY
port map (
CI => blk00000003_sig00000c12,
DI => blk00000003_sig00000c31,
S => blk00000003_sig00000c13,
O => blk00000003_sig00000c0f
);
blk00000003_blk00000752 : MUXCY
port map (
CI => blk00000003_sig00000c0f,
DI => blk00000003_sig00000c30,
S => blk00000003_sig00000c10,
O => blk00000003_sig00000c0c
);
blk00000003_blk00000751 : MUXCY
port map (
CI => blk00000003_sig00000c0c,
DI => blk00000003_sig00000c2f,
S => blk00000003_sig00000c0d,
O => blk00000003_sig00000c09
);
blk00000003_blk00000750 : MUXCY
port map (
CI => blk00000003_sig00000c09,
DI => blk00000003_sig00000c2e,
S => blk00000003_sig00000c0a,
O => blk00000003_sig00000c06
);
blk00000003_blk0000074f : MUXCY
port map (
CI => blk00000003_sig00000c06,
DI => blk00000003_sig00000c2d,
S => blk00000003_sig00000c07,
O => blk00000003_sig00000c03
);
blk00000003_blk0000074e : MUXCY
port map (
CI => blk00000003_sig00000c03,
DI => blk00000003_sig00000c2c,
S => blk00000003_sig00000c04,
O => blk00000003_sig00000c00
);
blk00000003_blk0000074d : MUXCY
port map (
CI => blk00000003_sig00000c00,
DI => blk00000003_sig00000c2b,
S => blk00000003_sig00000c01,
O => blk00000003_sig00000bfd
);
blk00000003_blk0000074c : MUXCY
port map (
CI => blk00000003_sig00000bfd,
DI => blk00000003_sig00000c2a,
S => blk00000003_sig00000bfe,
O => blk00000003_sig00000bfa
);
blk00000003_blk0000074b : MUXCY
port map (
CI => blk00000003_sig00000bfa,
DI => blk00000003_sig00000c29,
S => blk00000003_sig00000bfb,
O => blk00000003_sig00000bf7
);
blk00000003_blk0000074a : MUXCY
port map (
CI => blk00000003_sig00000bf7,
DI => blk00000003_sig00000c28,
S => blk00000003_sig00000bf8,
O => blk00000003_sig00000bf4
);
blk00000003_blk00000749 : MUXCY
port map (
CI => blk00000003_sig00000bf4,
DI => blk00000003_sig00000c27,
S => blk00000003_sig00000bf5,
O => blk00000003_sig00000bf1
);
blk00000003_blk00000748 : MUXCY
port map (
CI => blk00000003_sig00000bf1,
DI => blk00000003_sig00000c26,
S => blk00000003_sig00000bf2,
O => blk00000003_sig00000bee
);
blk00000003_blk00000747 : MUXCY
port map (
CI => blk00000003_sig00000bee,
DI => blk00000003_sig00000c25,
S => blk00000003_sig00000bef,
O => blk00000003_sig00000beb
);
blk00000003_blk00000746 : MUXCY
port map (
CI => blk00000003_sig00000beb,
DI => blk00000003_sig00000c24,
S => blk00000003_sig00000bec,
O => blk00000003_sig00000be8
);
blk00000003_blk00000745 : MUXCY
port map (
CI => blk00000003_sig00000be8,
DI => blk00000003_sig00000c23,
S => blk00000003_sig00000be9,
O => blk00000003_sig00000be5
);
blk00000003_blk00000744 : MUXCY
port map (
CI => blk00000003_sig00000be5,
DI => blk00000003_sig00000c22,
S => blk00000003_sig00000be6,
O => blk00000003_sig00000be2
);
blk00000003_blk00000743 : MUXCY
port map (
CI => blk00000003_sig00000be2,
DI => blk00000003_sig00000c21,
S => blk00000003_sig00000be3,
O => blk00000003_sig00000bdf
);
blk00000003_blk00000742 : MUXCY
port map (
CI => blk00000003_sig00000bdf,
DI => blk00000003_sig00000c20,
S => blk00000003_sig00000be0,
O => blk00000003_sig00000bdc
);
blk00000003_blk00000741 : MUXCY
port map (
CI => blk00000003_sig00000bdc,
DI => blk00000003_sig00000c1f,
S => blk00000003_sig00000bdd,
O => blk00000003_sig00000bd9
);
blk00000003_blk00000740 : MUXCY
port map (
CI => blk00000003_sig00000bd9,
DI => blk00000003_sig00000c1e,
S => blk00000003_sig00000bda,
O => blk00000003_sig00000bd6
);
blk00000003_blk0000073f : XORCY
port map (
CI => blk00000003_sig00000c1b,
LI => blk00000003_sig00000c1c,
O => blk00000003_sig00000c1d
);
blk00000003_blk0000073e : XORCY
port map (
CI => blk00000003_sig00000c18,
LI => blk00000003_sig00000c19,
O => blk00000003_sig00000c1a
);
blk00000003_blk0000073d : XORCY
port map (
CI => blk00000003_sig00000c15,
LI => blk00000003_sig00000c16,
O => blk00000003_sig00000c17
);
blk00000003_blk0000073c : XORCY
port map (
CI => blk00000003_sig00000c12,
LI => blk00000003_sig00000c13,
O => blk00000003_sig00000c14
);
blk00000003_blk0000073b : XORCY
port map (
CI => blk00000003_sig00000c0f,
LI => blk00000003_sig00000c10,
O => blk00000003_sig00000c11
);
blk00000003_blk0000073a : XORCY
port map (
CI => blk00000003_sig00000c0c,
LI => blk00000003_sig00000c0d,
O => blk00000003_sig00000c0e
);
blk00000003_blk00000739 : XORCY
port map (
CI => blk00000003_sig00000c09,
LI => blk00000003_sig00000c0a,
O => blk00000003_sig00000c0b
);
blk00000003_blk00000738 : XORCY
port map (
CI => blk00000003_sig00000c06,
LI => blk00000003_sig00000c07,
O => blk00000003_sig00000c08
);
blk00000003_blk00000737 : XORCY
port map (
CI => blk00000003_sig00000c03,
LI => blk00000003_sig00000c04,
O => blk00000003_sig00000c05
);
blk00000003_blk00000736 : XORCY
port map (
CI => blk00000003_sig00000c00,
LI => blk00000003_sig00000c01,
O => blk00000003_sig00000c02
);
blk00000003_blk00000735 : XORCY
port map (
CI => blk00000003_sig00000bfd,
LI => blk00000003_sig00000bfe,
O => blk00000003_sig00000bff
);
blk00000003_blk00000734 : XORCY
port map (
CI => blk00000003_sig00000bfa,
LI => blk00000003_sig00000bfb,
O => blk00000003_sig00000bfc
);
blk00000003_blk00000733 : XORCY
port map (
CI => blk00000003_sig00000bf7,
LI => blk00000003_sig00000bf8,
O => blk00000003_sig00000bf9
);
blk00000003_blk00000732 : XORCY
port map (
CI => blk00000003_sig00000bf4,
LI => blk00000003_sig00000bf5,
O => blk00000003_sig00000bf6
);
blk00000003_blk00000731 : XORCY
port map (
CI => blk00000003_sig00000bf1,
LI => blk00000003_sig00000bf2,
O => blk00000003_sig00000bf3
);
blk00000003_blk00000730 : XORCY
port map (
CI => blk00000003_sig00000bee,
LI => blk00000003_sig00000bef,
O => blk00000003_sig00000bf0
);
blk00000003_blk0000072f : XORCY
port map (
CI => blk00000003_sig00000beb,
LI => blk00000003_sig00000bec,
O => blk00000003_sig00000bed
);
blk00000003_blk0000072e : XORCY
port map (
CI => blk00000003_sig00000be8,
LI => blk00000003_sig00000be9,
O => blk00000003_sig00000bea
);
blk00000003_blk0000072d : XORCY
port map (
CI => blk00000003_sig00000be5,
LI => blk00000003_sig00000be6,
O => blk00000003_sig00000be7
);
blk00000003_blk0000072c : XORCY
port map (
CI => blk00000003_sig00000be2,
LI => blk00000003_sig00000be3,
O => blk00000003_sig00000be4
);
blk00000003_blk0000072b : XORCY
port map (
CI => blk00000003_sig00000bdf,
LI => blk00000003_sig00000be0,
O => blk00000003_sig00000be1
);
blk00000003_blk0000072a : XORCY
port map (
CI => blk00000003_sig00000bdc,
LI => blk00000003_sig00000bdd,
O => blk00000003_sig00000bde
);
blk00000003_blk00000729 : XORCY
port map (
CI => blk00000003_sig00000bd9,
LI => blk00000003_sig00000bda,
O => blk00000003_sig00000bdb
);
blk00000003_blk00000728 : XORCY
port map (
CI => blk00000003_sig00000bd6,
LI => blk00000003_sig00000bd7,
O => blk00000003_sig00000bd8
);
blk00000003_blk00000727 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000bd1,
Q => blk00000003_sig00000bd5
);
blk00000003_blk00000726 : MUXCY
port map (
CI => blk00000003_sig00000bd2,
DI => blk00000003_sig0000006b,
S => blk00000003_sig00000bd3,
O => blk00000003_sig00000bb6
);
blk00000003_blk00000725 : XORCY
port map (
CI => blk00000003_sig00000bd2,
LI => blk00000003_sig00000bd3,
O => blk00000003_sig00000bd4
);
blk00000003_blk00000724 : MUXCY
port map (
CI => blk00000003_sig00000b71,
DI => blk00000003_sig00000bd0,
S => blk00000003_sig00000b72,
O => blk00000003_sig00000bd1
);
blk00000003_blk00000723 : MUXCY
port map (
CI => blk00000003_sig00000bb6,
DI => blk00000003_sig00000bcf,
S => blk00000003_sig00000bb7,
O => blk00000003_sig00000bb3
);
blk00000003_blk00000722 : MUXCY
port map (
CI => blk00000003_sig00000bb3,
DI => blk00000003_sig00000bce,
S => blk00000003_sig00000bb4,
O => blk00000003_sig00000bb0
);
blk00000003_blk00000721 : MUXCY
port map (
CI => blk00000003_sig00000bb0,
DI => blk00000003_sig00000bcd,
S => blk00000003_sig00000bb1,
O => blk00000003_sig00000bad
);
blk00000003_blk00000720 : MUXCY
port map (
CI => blk00000003_sig00000bad,
DI => blk00000003_sig00000bcc,
S => blk00000003_sig00000bae,
O => blk00000003_sig00000baa
);
blk00000003_blk0000071f : MUXCY
port map (
CI => blk00000003_sig00000baa,
DI => blk00000003_sig00000bcb,
S => blk00000003_sig00000bab,
O => blk00000003_sig00000ba7
);
blk00000003_blk0000071e : MUXCY
port map (
CI => blk00000003_sig00000ba7,
DI => blk00000003_sig00000bca,
S => blk00000003_sig00000ba8,
O => blk00000003_sig00000ba4
);
blk00000003_blk0000071d : MUXCY
port map (
CI => blk00000003_sig00000ba4,
DI => blk00000003_sig00000bc9,
S => blk00000003_sig00000ba5,
O => blk00000003_sig00000ba1
);
blk00000003_blk0000071c : MUXCY
port map (
CI => blk00000003_sig00000ba1,
DI => blk00000003_sig00000bc8,
S => blk00000003_sig00000ba2,
O => blk00000003_sig00000b9e
);
blk00000003_blk0000071b : MUXCY
port map (
CI => blk00000003_sig00000b9e,
DI => blk00000003_sig00000bc7,
S => blk00000003_sig00000b9f,
O => blk00000003_sig00000b9b
);
blk00000003_blk0000071a : MUXCY
port map (
CI => blk00000003_sig00000b9b,
DI => blk00000003_sig00000bc6,
S => blk00000003_sig00000b9c,
O => blk00000003_sig00000b98
);
blk00000003_blk00000719 : MUXCY
port map (
CI => blk00000003_sig00000b98,
DI => blk00000003_sig00000bc5,
S => blk00000003_sig00000b99,
O => blk00000003_sig00000b95
);
blk00000003_blk00000718 : MUXCY
port map (
CI => blk00000003_sig00000b95,
DI => blk00000003_sig00000bc4,
S => blk00000003_sig00000b96,
O => blk00000003_sig00000b92
);
blk00000003_blk00000717 : MUXCY
port map (
CI => blk00000003_sig00000b92,
DI => blk00000003_sig00000bc3,
S => blk00000003_sig00000b93,
O => blk00000003_sig00000b8f
);
blk00000003_blk00000716 : MUXCY
port map (
CI => blk00000003_sig00000b8f,
DI => blk00000003_sig00000bc2,
S => blk00000003_sig00000b90,
O => blk00000003_sig00000b8c
);
blk00000003_blk00000715 : MUXCY
port map (
CI => blk00000003_sig00000b8c,
DI => blk00000003_sig00000bc1,
S => blk00000003_sig00000b8d,
O => blk00000003_sig00000b89
);
blk00000003_blk00000714 : MUXCY
port map (
CI => blk00000003_sig00000b89,
DI => blk00000003_sig00000bc0,
S => blk00000003_sig00000b8a,
O => blk00000003_sig00000b86
);
blk00000003_blk00000713 : MUXCY
port map (
CI => blk00000003_sig00000b86,
DI => blk00000003_sig00000bbf,
S => blk00000003_sig00000b87,
O => blk00000003_sig00000b83
);
blk00000003_blk00000712 : MUXCY
port map (
CI => blk00000003_sig00000b83,
DI => blk00000003_sig00000bbe,
S => blk00000003_sig00000b84,
O => blk00000003_sig00000b80
);
blk00000003_blk00000711 : MUXCY
port map (
CI => blk00000003_sig00000b80,
DI => blk00000003_sig00000bbd,
S => blk00000003_sig00000b81,
O => blk00000003_sig00000b7d
);
blk00000003_blk00000710 : MUXCY
port map (
CI => blk00000003_sig00000b7d,
DI => blk00000003_sig00000bbc,
S => blk00000003_sig00000b7e,
O => blk00000003_sig00000b7a
);
blk00000003_blk0000070f : MUXCY
port map (
CI => blk00000003_sig00000b7a,
DI => blk00000003_sig00000bbb,
S => blk00000003_sig00000b7b,
O => blk00000003_sig00000b77
);
blk00000003_blk0000070e : MUXCY
port map (
CI => blk00000003_sig00000b77,
DI => blk00000003_sig00000bba,
S => blk00000003_sig00000b78,
O => blk00000003_sig00000b74
);
blk00000003_blk0000070d : MUXCY
port map (
CI => blk00000003_sig00000b74,
DI => blk00000003_sig00000bb9,
S => blk00000003_sig00000b75,
O => blk00000003_sig00000b71
);
blk00000003_blk0000070c : XORCY
port map (
CI => blk00000003_sig00000bb6,
LI => blk00000003_sig00000bb7,
O => blk00000003_sig00000bb8
);
blk00000003_blk0000070b : XORCY
port map (
CI => blk00000003_sig00000bb3,
LI => blk00000003_sig00000bb4,
O => blk00000003_sig00000bb5
);
blk00000003_blk0000070a : XORCY
port map (
CI => blk00000003_sig00000bb0,
LI => blk00000003_sig00000bb1,
O => blk00000003_sig00000bb2
);
blk00000003_blk00000709 : XORCY
port map (
CI => blk00000003_sig00000bad,
LI => blk00000003_sig00000bae,
O => blk00000003_sig00000baf
);
blk00000003_blk00000708 : XORCY
port map (
CI => blk00000003_sig00000baa,
LI => blk00000003_sig00000bab,
O => blk00000003_sig00000bac
);
blk00000003_blk00000707 : XORCY
port map (
CI => blk00000003_sig00000ba7,
LI => blk00000003_sig00000ba8,
O => blk00000003_sig00000ba9
);
blk00000003_blk00000706 : XORCY
port map (
CI => blk00000003_sig00000ba4,
LI => blk00000003_sig00000ba5,
O => blk00000003_sig00000ba6
);
blk00000003_blk00000705 : XORCY
port map (
CI => blk00000003_sig00000ba1,
LI => blk00000003_sig00000ba2,
O => blk00000003_sig00000ba3
);
blk00000003_blk00000704 : XORCY
port map (
CI => blk00000003_sig00000b9e,
LI => blk00000003_sig00000b9f,
O => blk00000003_sig00000ba0
);
blk00000003_blk00000703 : XORCY
port map (
CI => blk00000003_sig00000b9b,
LI => blk00000003_sig00000b9c,
O => blk00000003_sig00000b9d
);
blk00000003_blk00000702 : XORCY
port map (
CI => blk00000003_sig00000b98,
LI => blk00000003_sig00000b99,
O => blk00000003_sig00000b9a
);
blk00000003_blk00000701 : XORCY
port map (
CI => blk00000003_sig00000b95,
LI => blk00000003_sig00000b96,
O => blk00000003_sig00000b97
);
blk00000003_blk00000700 : XORCY
port map (
CI => blk00000003_sig00000b92,
LI => blk00000003_sig00000b93,
O => blk00000003_sig00000b94
);
blk00000003_blk000006ff : XORCY
port map (
CI => blk00000003_sig00000b8f,
LI => blk00000003_sig00000b90,
O => blk00000003_sig00000b91
);
blk00000003_blk000006fe : XORCY
port map (
CI => blk00000003_sig00000b8c,
LI => blk00000003_sig00000b8d,
O => blk00000003_sig00000b8e
);
blk00000003_blk000006fd : XORCY
port map (
CI => blk00000003_sig00000b89,
LI => blk00000003_sig00000b8a,
O => blk00000003_sig00000b8b
);
blk00000003_blk000006fc : XORCY
port map (
CI => blk00000003_sig00000b86,
LI => blk00000003_sig00000b87,
O => blk00000003_sig00000b88
);
blk00000003_blk000006fb : XORCY
port map (
CI => blk00000003_sig00000b83,
LI => blk00000003_sig00000b84,
O => blk00000003_sig00000b85
);
blk00000003_blk000006fa : XORCY
port map (
CI => blk00000003_sig00000b80,
LI => blk00000003_sig00000b81,
O => blk00000003_sig00000b82
);
blk00000003_blk000006f9 : XORCY
port map (
CI => blk00000003_sig00000b7d,
LI => blk00000003_sig00000b7e,
O => blk00000003_sig00000b7f
);
blk00000003_blk000006f8 : XORCY
port map (
CI => blk00000003_sig00000b7a,
LI => blk00000003_sig00000b7b,
O => blk00000003_sig00000b7c
);
blk00000003_blk000006f7 : XORCY
port map (
CI => blk00000003_sig00000b77,
LI => blk00000003_sig00000b78,
O => blk00000003_sig00000b79
);
blk00000003_blk000006f6 : XORCY
port map (
CI => blk00000003_sig00000b74,
LI => blk00000003_sig00000b75,
O => blk00000003_sig00000b76
);
blk00000003_blk000006f5 : XORCY
port map (
CI => blk00000003_sig00000b71,
LI => blk00000003_sig00000b72,
O => blk00000003_sig00000b73
);
blk00000003_blk000006f4 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000b6c,
Q => blk00000003_sig00000b70
);
blk00000003_blk000006f3 : MUXCY
port map (
CI => blk00000003_sig00000b6d,
DI => blk00000003_sig00000070,
S => blk00000003_sig00000b6e,
O => blk00000003_sig00000b51
);
blk00000003_blk000006f2 : XORCY
port map (
CI => blk00000003_sig00000b6d,
LI => blk00000003_sig00000b6e,
O => blk00000003_sig00000b6f
);
blk00000003_blk000006f1 : MUXCY
port map (
CI => blk00000003_sig00000b0c,
DI => blk00000003_sig00000b6b,
S => blk00000003_sig00000b0d,
O => blk00000003_sig00000b6c
);
blk00000003_blk000006f0 : MUXCY
port map (
CI => blk00000003_sig00000b51,
DI => blk00000003_sig00000b6a,
S => blk00000003_sig00000b52,
O => blk00000003_sig00000b4e
);
blk00000003_blk000006ef : MUXCY
port map (
CI => blk00000003_sig00000b4e,
DI => blk00000003_sig00000b69,
S => blk00000003_sig00000b4f,
O => blk00000003_sig00000b4b
);
blk00000003_blk000006ee : MUXCY
port map (
CI => blk00000003_sig00000b4b,
DI => blk00000003_sig00000b68,
S => blk00000003_sig00000b4c,
O => blk00000003_sig00000b48
);
blk00000003_blk000006ed : MUXCY
port map (
CI => blk00000003_sig00000b48,
DI => blk00000003_sig00000b67,
S => blk00000003_sig00000b49,
O => blk00000003_sig00000b45
);
blk00000003_blk000006ec : MUXCY
port map (
CI => blk00000003_sig00000b45,
DI => blk00000003_sig00000b66,
S => blk00000003_sig00000b46,
O => blk00000003_sig00000b42
);
blk00000003_blk000006eb : MUXCY
port map (
CI => blk00000003_sig00000b42,
DI => blk00000003_sig00000b65,
S => blk00000003_sig00000b43,
O => blk00000003_sig00000b3f
);
blk00000003_blk000006ea : MUXCY
port map (
CI => blk00000003_sig00000b3f,
DI => blk00000003_sig00000b64,
S => blk00000003_sig00000b40,
O => blk00000003_sig00000b3c
);
blk00000003_blk000006e9 : MUXCY
port map (
CI => blk00000003_sig00000b3c,
DI => blk00000003_sig00000b63,
S => blk00000003_sig00000b3d,
O => blk00000003_sig00000b39
);
blk00000003_blk000006e8 : MUXCY
port map (
CI => blk00000003_sig00000b39,
DI => blk00000003_sig00000b62,
S => blk00000003_sig00000b3a,
O => blk00000003_sig00000b36
);
blk00000003_blk000006e7 : MUXCY
port map (
CI => blk00000003_sig00000b36,
DI => blk00000003_sig00000b61,
S => blk00000003_sig00000b37,
O => blk00000003_sig00000b33
);
blk00000003_blk000006e6 : MUXCY
port map (
CI => blk00000003_sig00000b33,
DI => blk00000003_sig00000b60,
S => blk00000003_sig00000b34,
O => blk00000003_sig00000b30
);
blk00000003_blk000006e5 : MUXCY
port map (
CI => blk00000003_sig00000b30,
DI => blk00000003_sig00000b5f,
S => blk00000003_sig00000b31,
O => blk00000003_sig00000b2d
);
blk00000003_blk000006e4 : MUXCY
port map (
CI => blk00000003_sig00000b2d,
DI => blk00000003_sig00000b5e,
S => blk00000003_sig00000b2e,
O => blk00000003_sig00000b2a
);
blk00000003_blk000006e3 : MUXCY
port map (
CI => blk00000003_sig00000b2a,
DI => blk00000003_sig00000b5d,
S => blk00000003_sig00000b2b,
O => blk00000003_sig00000b27
);
blk00000003_blk000006e2 : MUXCY
port map (
CI => blk00000003_sig00000b27,
DI => blk00000003_sig00000b5c,
S => blk00000003_sig00000b28,
O => blk00000003_sig00000b24
);
blk00000003_blk000006e1 : MUXCY
port map (
CI => blk00000003_sig00000b24,
DI => blk00000003_sig00000b5b,
S => blk00000003_sig00000b25,
O => blk00000003_sig00000b21
);
blk00000003_blk000006e0 : MUXCY
port map (
CI => blk00000003_sig00000b21,
DI => blk00000003_sig00000b5a,
S => blk00000003_sig00000b22,
O => blk00000003_sig00000b1e
);
blk00000003_blk000006df : MUXCY
port map (
CI => blk00000003_sig00000b1e,
DI => blk00000003_sig00000b59,
S => blk00000003_sig00000b1f,
O => blk00000003_sig00000b1b
);
blk00000003_blk000006de : MUXCY
port map (
CI => blk00000003_sig00000b1b,
DI => blk00000003_sig00000b58,
S => blk00000003_sig00000b1c,
O => blk00000003_sig00000b18
);
blk00000003_blk000006dd : MUXCY
port map (
CI => blk00000003_sig00000b18,
DI => blk00000003_sig00000b57,
S => blk00000003_sig00000b19,
O => blk00000003_sig00000b15
);
blk00000003_blk000006dc : MUXCY
port map (
CI => blk00000003_sig00000b15,
DI => blk00000003_sig00000b56,
S => blk00000003_sig00000b16,
O => blk00000003_sig00000b12
);
blk00000003_blk000006db : MUXCY
port map (
CI => blk00000003_sig00000b12,
DI => blk00000003_sig00000b55,
S => blk00000003_sig00000b13,
O => blk00000003_sig00000b0f
);
blk00000003_blk000006da : MUXCY
port map (
CI => blk00000003_sig00000b0f,
DI => blk00000003_sig00000b54,
S => blk00000003_sig00000b10,
O => blk00000003_sig00000b0c
);
blk00000003_blk000006d9 : XORCY
port map (
CI => blk00000003_sig00000b51,
LI => blk00000003_sig00000b52,
O => blk00000003_sig00000b53
);
blk00000003_blk000006d8 : XORCY
port map (
CI => blk00000003_sig00000b4e,
LI => blk00000003_sig00000b4f,
O => blk00000003_sig00000b50
);
blk00000003_blk000006d7 : XORCY
port map (
CI => blk00000003_sig00000b4b,
LI => blk00000003_sig00000b4c,
O => blk00000003_sig00000b4d
);
blk00000003_blk000006d6 : XORCY
port map (
CI => blk00000003_sig00000b48,
LI => blk00000003_sig00000b49,
O => blk00000003_sig00000b4a
);
blk00000003_blk000006d5 : XORCY
port map (
CI => blk00000003_sig00000b45,
LI => blk00000003_sig00000b46,
O => blk00000003_sig00000b47
);
blk00000003_blk000006d4 : XORCY
port map (
CI => blk00000003_sig00000b42,
LI => blk00000003_sig00000b43,
O => blk00000003_sig00000b44
);
blk00000003_blk000006d3 : XORCY
port map (
CI => blk00000003_sig00000b3f,
LI => blk00000003_sig00000b40,
O => blk00000003_sig00000b41
);
blk00000003_blk000006d2 : XORCY
port map (
CI => blk00000003_sig00000b3c,
LI => blk00000003_sig00000b3d,
O => blk00000003_sig00000b3e
);
blk00000003_blk000006d1 : XORCY
port map (
CI => blk00000003_sig00000b39,
LI => blk00000003_sig00000b3a,
O => blk00000003_sig00000b3b
);
blk00000003_blk000006d0 : XORCY
port map (
CI => blk00000003_sig00000b36,
LI => blk00000003_sig00000b37,
O => blk00000003_sig00000b38
);
blk00000003_blk000006cf : XORCY
port map (
CI => blk00000003_sig00000b33,
LI => blk00000003_sig00000b34,
O => blk00000003_sig00000b35
);
blk00000003_blk000006ce : XORCY
port map (
CI => blk00000003_sig00000b30,
LI => blk00000003_sig00000b31,
O => blk00000003_sig00000b32
);
blk00000003_blk000006cd : XORCY
port map (
CI => blk00000003_sig00000b2d,
LI => blk00000003_sig00000b2e,
O => blk00000003_sig00000b2f
);
blk00000003_blk000006cc : XORCY
port map (
CI => blk00000003_sig00000b2a,
LI => blk00000003_sig00000b2b,
O => blk00000003_sig00000b2c
);
blk00000003_blk000006cb : XORCY
port map (
CI => blk00000003_sig00000b27,
LI => blk00000003_sig00000b28,
O => blk00000003_sig00000b29
);
blk00000003_blk000006ca : XORCY
port map (
CI => blk00000003_sig00000b24,
LI => blk00000003_sig00000b25,
O => blk00000003_sig00000b26
);
blk00000003_blk000006c9 : XORCY
port map (
CI => blk00000003_sig00000b21,
LI => blk00000003_sig00000b22,
O => blk00000003_sig00000b23
);
blk00000003_blk000006c8 : XORCY
port map (
CI => blk00000003_sig00000b1e,
LI => blk00000003_sig00000b1f,
O => blk00000003_sig00000b20
);
blk00000003_blk000006c7 : XORCY
port map (
CI => blk00000003_sig00000b1b,
LI => blk00000003_sig00000b1c,
O => blk00000003_sig00000b1d
);
blk00000003_blk000006c6 : XORCY
port map (
CI => blk00000003_sig00000b18,
LI => blk00000003_sig00000b19,
O => blk00000003_sig00000b1a
);
blk00000003_blk000006c5 : XORCY
port map (
CI => blk00000003_sig00000b15,
LI => blk00000003_sig00000b16,
O => blk00000003_sig00000b17
);
blk00000003_blk000006c4 : XORCY
port map (
CI => blk00000003_sig00000b12,
LI => blk00000003_sig00000b13,
O => blk00000003_sig00000b14
);
blk00000003_blk000006c3 : XORCY
port map (
CI => blk00000003_sig00000b0f,
LI => blk00000003_sig00000b10,
O => blk00000003_sig00000b11
);
blk00000003_blk000006c2 : XORCY
port map (
CI => blk00000003_sig00000b0c,
LI => blk00000003_sig00000b0d,
O => blk00000003_sig00000b0e
);
blk00000003_blk000006c1 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000b07,
Q => blk00000003_sig00000b0b
);
blk00000003_blk000006c0 : MUXCY
port map (
CI => blk00000003_sig00000b08,
DI => blk00000003_sig00000076,
S => blk00000003_sig00000b09,
O => blk00000003_sig00000aec
);
blk00000003_blk000006bf : XORCY
port map (
CI => blk00000003_sig00000b08,
LI => blk00000003_sig00000b09,
O => blk00000003_sig00000b0a
);
blk00000003_blk000006be : MUXCY
port map (
CI => blk00000003_sig00000aa7,
DI => blk00000003_sig00000b06,
S => blk00000003_sig00000aa8,
O => blk00000003_sig00000b07
);
blk00000003_blk000006bd : MUXCY
port map (
CI => blk00000003_sig00000aec,
DI => blk00000003_sig00000b05,
S => blk00000003_sig00000aed,
O => blk00000003_sig00000ae9
);
blk00000003_blk000006bc : MUXCY
port map (
CI => blk00000003_sig00000ae9,
DI => blk00000003_sig00000b04,
S => blk00000003_sig00000aea,
O => blk00000003_sig00000ae6
);
blk00000003_blk000006bb : MUXCY
port map (
CI => blk00000003_sig00000ae6,
DI => blk00000003_sig00000b03,
S => blk00000003_sig00000ae7,
O => blk00000003_sig00000ae3
);
blk00000003_blk000006ba : MUXCY
port map (
CI => blk00000003_sig00000ae3,
DI => blk00000003_sig00000b02,
S => blk00000003_sig00000ae4,
O => blk00000003_sig00000ae0
);
blk00000003_blk000006b9 : MUXCY
port map (
CI => blk00000003_sig00000ae0,
DI => blk00000003_sig00000b01,
S => blk00000003_sig00000ae1,
O => blk00000003_sig00000add
);
blk00000003_blk000006b8 : MUXCY
port map (
CI => blk00000003_sig00000add,
DI => blk00000003_sig00000b00,
S => blk00000003_sig00000ade,
O => blk00000003_sig00000ada
);
blk00000003_blk000006b7 : MUXCY
port map (
CI => blk00000003_sig00000ada,
DI => blk00000003_sig00000aff,
S => blk00000003_sig00000adb,
O => blk00000003_sig00000ad7
);
blk00000003_blk000006b6 : MUXCY
port map (
CI => blk00000003_sig00000ad7,
DI => blk00000003_sig00000afe,
S => blk00000003_sig00000ad8,
O => blk00000003_sig00000ad4
);
blk00000003_blk000006b5 : MUXCY
port map (
CI => blk00000003_sig00000ad4,
DI => blk00000003_sig00000afd,
S => blk00000003_sig00000ad5,
O => blk00000003_sig00000ad1
);
blk00000003_blk000006b4 : MUXCY
port map (
CI => blk00000003_sig00000ad1,
DI => blk00000003_sig00000afc,
S => blk00000003_sig00000ad2,
O => blk00000003_sig00000ace
);
blk00000003_blk000006b3 : MUXCY
port map (
CI => blk00000003_sig00000ace,
DI => blk00000003_sig00000afb,
S => blk00000003_sig00000acf,
O => blk00000003_sig00000acb
);
blk00000003_blk000006b2 : MUXCY
port map (
CI => blk00000003_sig00000acb,
DI => blk00000003_sig00000afa,
S => blk00000003_sig00000acc,
O => blk00000003_sig00000ac8
);
blk00000003_blk000006b1 : MUXCY
port map (
CI => blk00000003_sig00000ac8,
DI => blk00000003_sig00000af9,
S => blk00000003_sig00000ac9,
O => blk00000003_sig00000ac5
);
blk00000003_blk000006b0 : MUXCY
port map (
CI => blk00000003_sig00000ac5,
DI => blk00000003_sig00000af8,
S => blk00000003_sig00000ac6,
O => blk00000003_sig00000ac2
);
blk00000003_blk000006af : MUXCY
port map (
CI => blk00000003_sig00000ac2,
DI => blk00000003_sig00000af7,
S => blk00000003_sig00000ac3,
O => blk00000003_sig00000abf
);
blk00000003_blk000006ae : MUXCY
port map (
CI => blk00000003_sig00000abf,
DI => blk00000003_sig00000af6,
S => blk00000003_sig00000ac0,
O => blk00000003_sig00000abc
);
blk00000003_blk000006ad : MUXCY
port map (
CI => blk00000003_sig00000abc,
DI => blk00000003_sig00000af5,
S => blk00000003_sig00000abd,
O => blk00000003_sig00000ab9
);
blk00000003_blk000006ac : MUXCY
port map (
CI => blk00000003_sig00000ab9,
DI => blk00000003_sig00000af4,
S => blk00000003_sig00000aba,
O => blk00000003_sig00000ab6
);
blk00000003_blk000006ab : MUXCY
port map (
CI => blk00000003_sig00000ab6,
DI => blk00000003_sig00000af3,
S => blk00000003_sig00000ab7,
O => blk00000003_sig00000ab3
);
blk00000003_blk000006aa : MUXCY
port map (
CI => blk00000003_sig00000ab3,
DI => blk00000003_sig00000af2,
S => blk00000003_sig00000ab4,
O => blk00000003_sig00000ab0
);
blk00000003_blk000006a9 : MUXCY
port map (
CI => blk00000003_sig00000ab0,
DI => blk00000003_sig00000af1,
S => blk00000003_sig00000ab1,
O => blk00000003_sig00000aad
);
blk00000003_blk000006a8 : MUXCY
port map (
CI => blk00000003_sig00000aad,
DI => blk00000003_sig00000af0,
S => blk00000003_sig00000aae,
O => blk00000003_sig00000aaa
);
blk00000003_blk000006a7 : MUXCY
port map (
CI => blk00000003_sig00000aaa,
DI => blk00000003_sig00000aef,
S => blk00000003_sig00000aab,
O => blk00000003_sig00000aa7
);
blk00000003_blk000006a6 : XORCY
port map (
CI => blk00000003_sig00000aec,
LI => blk00000003_sig00000aed,
O => blk00000003_sig00000aee
);
blk00000003_blk000006a5 : XORCY
port map (
CI => blk00000003_sig00000ae9,
LI => blk00000003_sig00000aea,
O => blk00000003_sig00000aeb
);
blk00000003_blk000006a4 : XORCY
port map (
CI => blk00000003_sig00000ae6,
LI => blk00000003_sig00000ae7,
O => blk00000003_sig00000ae8
);
blk00000003_blk000006a3 : XORCY
port map (
CI => blk00000003_sig00000ae3,
LI => blk00000003_sig00000ae4,
O => blk00000003_sig00000ae5
);
blk00000003_blk000006a2 : XORCY
port map (
CI => blk00000003_sig00000ae0,
LI => blk00000003_sig00000ae1,
O => blk00000003_sig00000ae2
);
blk00000003_blk000006a1 : XORCY
port map (
CI => blk00000003_sig00000add,
LI => blk00000003_sig00000ade,
O => blk00000003_sig00000adf
);
blk00000003_blk000006a0 : XORCY
port map (
CI => blk00000003_sig00000ada,
LI => blk00000003_sig00000adb,
O => blk00000003_sig00000adc
);
blk00000003_blk0000069f : XORCY
port map (
CI => blk00000003_sig00000ad7,
LI => blk00000003_sig00000ad8,
O => blk00000003_sig00000ad9
);
blk00000003_blk0000069e : XORCY
port map (
CI => blk00000003_sig00000ad4,
LI => blk00000003_sig00000ad5,
O => blk00000003_sig00000ad6
);
blk00000003_blk0000069d : XORCY
port map (
CI => blk00000003_sig00000ad1,
LI => blk00000003_sig00000ad2,
O => blk00000003_sig00000ad3
);
blk00000003_blk0000069c : XORCY
port map (
CI => blk00000003_sig00000ace,
LI => blk00000003_sig00000acf,
O => blk00000003_sig00000ad0
);
blk00000003_blk0000069b : XORCY
port map (
CI => blk00000003_sig00000acb,
LI => blk00000003_sig00000acc,
O => blk00000003_sig00000acd
);
blk00000003_blk0000069a : XORCY
port map (
CI => blk00000003_sig00000ac8,
LI => blk00000003_sig00000ac9,
O => blk00000003_sig00000aca
);
blk00000003_blk00000699 : XORCY
port map (
CI => blk00000003_sig00000ac5,
LI => blk00000003_sig00000ac6,
O => blk00000003_sig00000ac7
);
blk00000003_blk00000698 : XORCY
port map (
CI => blk00000003_sig00000ac2,
LI => blk00000003_sig00000ac3,
O => blk00000003_sig00000ac4
);
blk00000003_blk00000697 : XORCY
port map (
CI => blk00000003_sig00000abf,
LI => blk00000003_sig00000ac0,
O => blk00000003_sig00000ac1
);
blk00000003_blk00000696 : XORCY
port map (
CI => blk00000003_sig00000abc,
LI => blk00000003_sig00000abd,
O => blk00000003_sig00000abe
);
blk00000003_blk00000695 : XORCY
port map (
CI => blk00000003_sig00000ab9,
LI => blk00000003_sig00000aba,
O => blk00000003_sig00000abb
);
blk00000003_blk00000694 : XORCY
port map (
CI => blk00000003_sig00000ab6,
LI => blk00000003_sig00000ab7,
O => blk00000003_sig00000ab8
);
blk00000003_blk00000693 : XORCY
port map (
CI => blk00000003_sig00000ab3,
LI => blk00000003_sig00000ab4,
O => blk00000003_sig00000ab5
);
blk00000003_blk00000692 : XORCY
port map (
CI => blk00000003_sig00000ab0,
LI => blk00000003_sig00000ab1,
O => blk00000003_sig00000ab2
);
blk00000003_blk00000691 : XORCY
port map (
CI => blk00000003_sig00000aad,
LI => blk00000003_sig00000aae,
O => blk00000003_sig00000aaf
);
blk00000003_blk00000690 : XORCY
port map (
CI => blk00000003_sig00000aaa,
LI => blk00000003_sig00000aab,
O => blk00000003_sig00000aac
);
blk00000003_blk0000068f : XORCY
port map (
CI => blk00000003_sig00000aa7,
LI => blk00000003_sig00000aa8,
O => blk00000003_sig00000aa9
);
blk00000003_blk0000068e : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000aa2,
Q => blk00000003_sig00000aa6
);
blk00000003_blk0000068d : MUXCY
port map (
CI => blk00000003_sig00000aa3,
DI => blk00000003_sig0000007d,
S => blk00000003_sig00000aa4,
O => blk00000003_sig00000a87
);
blk00000003_blk0000068c : XORCY
port map (
CI => blk00000003_sig00000aa3,
LI => blk00000003_sig00000aa4,
O => blk00000003_sig00000aa5
);
blk00000003_blk0000068b : MUXCY
port map (
CI => blk00000003_sig00000a42,
DI => blk00000003_sig00000aa1,
S => blk00000003_sig00000a43,
O => blk00000003_sig00000aa2
);
blk00000003_blk0000068a : MUXCY
port map (
CI => blk00000003_sig00000a87,
DI => blk00000003_sig00000aa0,
S => blk00000003_sig00000a88,
O => blk00000003_sig00000a84
);
blk00000003_blk00000689 : MUXCY
port map (
CI => blk00000003_sig00000a84,
DI => blk00000003_sig00000a9f,
S => blk00000003_sig00000a85,
O => blk00000003_sig00000a81
);
blk00000003_blk00000688 : MUXCY
port map (
CI => blk00000003_sig00000a81,
DI => blk00000003_sig00000a9e,
S => blk00000003_sig00000a82,
O => blk00000003_sig00000a7e
);
blk00000003_blk00000687 : MUXCY
port map (
CI => blk00000003_sig00000a7e,
DI => blk00000003_sig00000a9d,
S => blk00000003_sig00000a7f,
O => blk00000003_sig00000a7b
);
blk00000003_blk00000686 : MUXCY
port map (
CI => blk00000003_sig00000a7b,
DI => blk00000003_sig00000a9c,
S => blk00000003_sig00000a7c,
O => blk00000003_sig00000a78
);
blk00000003_blk00000685 : MUXCY
port map (
CI => blk00000003_sig00000a78,
DI => blk00000003_sig00000a9b,
S => blk00000003_sig00000a79,
O => blk00000003_sig00000a75
);
blk00000003_blk00000684 : MUXCY
port map (
CI => blk00000003_sig00000a75,
DI => blk00000003_sig00000a9a,
S => blk00000003_sig00000a76,
O => blk00000003_sig00000a72
);
blk00000003_blk00000683 : MUXCY
port map (
CI => blk00000003_sig00000a72,
DI => blk00000003_sig00000a99,
S => blk00000003_sig00000a73,
O => blk00000003_sig00000a6f
);
blk00000003_blk00000682 : MUXCY
port map (
CI => blk00000003_sig00000a6f,
DI => blk00000003_sig00000a98,
S => blk00000003_sig00000a70,
O => blk00000003_sig00000a6c
);
blk00000003_blk00000681 : MUXCY
port map (
CI => blk00000003_sig00000a6c,
DI => blk00000003_sig00000a97,
S => blk00000003_sig00000a6d,
O => blk00000003_sig00000a69
);
blk00000003_blk00000680 : MUXCY
port map (
CI => blk00000003_sig00000a69,
DI => blk00000003_sig00000a96,
S => blk00000003_sig00000a6a,
O => blk00000003_sig00000a66
);
blk00000003_blk0000067f : MUXCY
port map (
CI => blk00000003_sig00000a66,
DI => blk00000003_sig00000a95,
S => blk00000003_sig00000a67,
O => blk00000003_sig00000a63
);
blk00000003_blk0000067e : MUXCY
port map (
CI => blk00000003_sig00000a63,
DI => blk00000003_sig00000a94,
S => blk00000003_sig00000a64,
O => blk00000003_sig00000a60
);
blk00000003_blk0000067d : MUXCY
port map (
CI => blk00000003_sig00000a60,
DI => blk00000003_sig00000a93,
S => blk00000003_sig00000a61,
O => blk00000003_sig00000a5d
);
blk00000003_blk0000067c : MUXCY
port map (
CI => blk00000003_sig00000a5d,
DI => blk00000003_sig00000a92,
S => blk00000003_sig00000a5e,
O => blk00000003_sig00000a5a
);
blk00000003_blk0000067b : MUXCY
port map (
CI => blk00000003_sig00000a5a,
DI => blk00000003_sig00000a91,
S => blk00000003_sig00000a5b,
O => blk00000003_sig00000a57
);
blk00000003_blk0000067a : MUXCY
port map (
CI => blk00000003_sig00000a57,
DI => blk00000003_sig00000a90,
S => blk00000003_sig00000a58,
O => blk00000003_sig00000a54
);
blk00000003_blk00000679 : MUXCY
port map (
CI => blk00000003_sig00000a54,
DI => blk00000003_sig00000a8f,
S => blk00000003_sig00000a55,
O => blk00000003_sig00000a51
);
blk00000003_blk00000678 : MUXCY
port map (
CI => blk00000003_sig00000a51,
DI => blk00000003_sig00000a8e,
S => blk00000003_sig00000a52,
O => blk00000003_sig00000a4e
);
blk00000003_blk00000677 : MUXCY
port map (
CI => blk00000003_sig00000a4e,
DI => blk00000003_sig00000a8d,
S => blk00000003_sig00000a4f,
O => blk00000003_sig00000a4b
);
blk00000003_blk00000676 : MUXCY
port map (
CI => blk00000003_sig00000a4b,
DI => blk00000003_sig00000a8c,
S => blk00000003_sig00000a4c,
O => blk00000003_sig00000a48
);
blk00000003_blk00000675 : MUXCY
port map (
CI => blk00000003_sig00000a48,
DI => blk00000003_sig00000a8b,
S => blk00000003_sig00000a49,
O => blk00000003_sig00000a45
);
blk00000003_blk00000674 : MUXCY
port map (
CI => blk00000003_sig00000a45,
DI => blk00000003_sig00000a8a,
S => blk00000003_sig00000a46,
O => blk00000003_sig00000a42
);
blk00000003_blk00000673 : XORCY
port map (
CI => blk00000003_sig00000a87,
LI => blk00000003_sig00000a88,
O => blk00000003_sig00000a89
);
blk00000003_blk00000672 : XORCY
port map (
CI => blk00000003_sig00000a84,
LI => blk00000003_sig00000a85,
O => blk00000003_sig00000a86
);
blk00000003_blk00000671 : XORCY
port map (
CI => blk00000003_sig00000a81,
LI => blk00000003_sig00000a82,
O => blk00000003_sig00000a83
);
blk00000003_blk00000670 : XORCY
port map (
CI => blk00000003_sig00000a7e,
LI => blk00000003_sig00000a7f,
O => blk00000003_sig00000a80
);
blk00000003_blk0000066f : XORCY
port map (
CI => blk00000003_sig00000a7b,
LI => blk00000003_sig00000a7c,
O => blk00000003_sig00000a7d
);
blk00000003_blk0000066e : XORCY
port map (
CI => blk00000003_sig00000a78,
LI => blk00000003_sig00000a79,
O => blk00000003_sig00000a7a
);
blk00000003_blk0000066d : XORCY
port map (
CI => blk00000003_sig00000a75,
LI => blk00000003_sig00000a76,
O => blk00000003_sig00000a77
);
blk00000003_blk0000066c : XORCY
port map (
CI => blk00000003_sig00000a72,
LI => blk00000003_sig00000a73,
O => blk00000003_sig00000a74
);
blk00000003_blk0000066b : XORCY
port map (
CI => blk00000003_sig00000a6f,
LI => blk00000003_sig00000a70,
O => blk00000003_sig00000a71
);
blk00000003_blk0000066a : XORCY
port map (
CI => blk00000003_sig00000a6c,
LI => blk00000003_sig00000a6d,
O => blk00000003_sig00000a6e
);
blk00000003_blk00000669 : XORCY
port map (
CI => blk00000003_sig00000a69,
LI => blk00000003_sig00000a6a,
O => blk00000003_sig00000a6b
);
blk00000003_blk00000668 : XORCY
port map (
CI => blk00000003_sig00000a66,
LI => blk00000003_sig00000a67,
O => blk00000003_sig00000a68
);
blk00000003_blk00000667 : XORCY
port map (
CI => blk00000003_sig00000a63,
LI => blk00000003_sig00000a64,
O => blk00000003_sig00000a65
);
blk00000003_blk00000666 : XORCY
port map (
CI => blk00000003_sig00000a60,
LI => blk00000003_sig00000a61,
O => blk00000003_sig00000a62
);
blk00000003_blk00000665 : XORCY
port map (
CI => blk00000003_sig00000a5d,
LI => blk00000003_sig00000a5e,
O => blk00000003_sig00000a5f
);
blk00000003_blk00000664 : XORCY
port map (
CI => blk00000003_sig00000a5a,
LI => blk00000003_sig00000a5b,
O => blk00000003_sig00000a5c
);
blk00000003_blk00000663 : XORCY
port map (
CI => blk00000003_sig00000a57,
LI => blk00000003_sig00000a58,
O => blk00000003_sig00000a59
);
blk00000003_blk00000662 : XORCY
port map (
CI => blk00000003_sig00000a54,
LI => blk00000003_sig00000a55,
O => blk00000003_sig00000a56
);
blk00000003_blk00000661 : XORCY
port map (
CI => blk00000003_sig00000a51,
LI => blk00000003_sig00000a52,
O => blk00000003_sig00000a53
);
blk00000003_blk00000660 : XORCY
port map (
CI => blk00000003_sig00000a4e,
LI => blk00000003_sig00000a4f,
O => blk00000003_sig00000a50
);
blk00000003_blk0000065f : XORCY
port map (
CI => blk00000003_sig00000a4b,
LI => blk00000003_sig00000a4c,
O => blk00000003_sig00000a4d
);
blk00000003_blk0000065e : XORCY
port map (
CI => blk00000003_sig00000a48,
LI => blk00000003_sig00000a49,
O => blk00000003_sig00000a4a
);
blk00000003_blk0000065d : XORCY
port map (
CI => blk00000003_sig00000a45,
LI => blk00000003_sig00000a46,
O => blk00000003_sig00000a47
);
blk00000003_blk0000065c : XORCY
port map (
CI => blk00000003_sig00000a42,
LI => blk00000003_sig00000a43,
O => blk00000003_sig00000a44
);
blk00000003_blk0000065b : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000a3d,
Q => blk00000003_sig00000a41
);
blk00000003_blk0000065a : MUXCY
port map (
CI => blk00000003_sig00000a3e,
DI => blk00000003_sig00000085,
S => blk00000003_sig00000a3f,
O => blk00000003_sig00000a22
);
blk00000003_blk00000659 : XORCY
port map (
CI => blk00000003_sig00000a3e,
LI => blk00000003_sig00000a3f,
O => blk00000003_sig00000a40
);
blk00000003_blk00000658 : MUXCY
port map (
CI => blk00000003_sig000009dd,
DI => blk00000003_sig00000a3c,
S => blk00000003_sig000009de,
O => blk00000003_sig00000a3d
);
blk00000003_blk00000657 : MUXCY
port map (
CI => blk00000003_sig00000a22,
DI => blk00000003_sig00000a3b,
S => blk00000003_sig00000a23,
O => blk00000003_sig00000a1f
);
blk00000003_blk00000656 : MUXCY
port map (
CI => blk00000003_sig00000a1f,
DI => blk00000003_sig00000a3a,
S => blk00000003_sig00000a20,
O => blk00000003_sig00000a1c
);
blk00000003_blk00000655 : MUXCY
port map (
CI => blk00000003_sig00000a1c,
DI => blk00000003_sig00000a39,
S => blk00000003_sig00000a1d,
O => blk00000003_sig00000a19
);
blk00000003_blk00000654 : MUXCY
port map (
CI => blk00000003_sig00000a19,
DI => blk00000003_sig00000a38,
S => blk00000003_sig00000a1a,
O => blk00000003_sig00000a16
);
blk00000003_blk00000653 : MUXCY
port map (
CI => blk00000003_sig00000a16,
DI => blk00000003_sig00000a37,
S => blk00000003_sig00000a17,
O => blk00000003_sig00000a13
);
blk00000003_blk00000652 : MUXCY
port map (
CI => blk00000003_sig00000a13,
DI => blk00000003_sig00000a36,
S => blk00000003_sig00000a14,
O => blk00000003_sig00000a10
);
blk00000003_blk00000651 : MUXCY
port map (
CI => blk00000003_sig00000a10,
DI => blk00000003_sig00000a35,
S => blk00000003_sig00000a11,
O => blk00000003_sig00000a0d
);
blk00000003_blk00000650 : MUXCY
port map (
CI => blk00000003_sig00000a0d,
DI => blk00000003_sig00000a34,
S => blk00000003_sig00000a0e,
O => blk00000003_sig00000a0a
);
blk00000003_blk0000064f : MUXCY
port map (
CI => blk00000003_sig00000a0a,
DI => blk00000003_sig00000a33,
S => blk00000003_sig00000a0b,
O => blk00000003_sig00000a07
);
blk00000003_blk0000064e : MUXCY
port map (
CI => blk00000003_sig00000a07,
DI => blk00000003_sig00000a32,
S => blk00000003_sig00000a08,
O => blk00000003_sig00000a04
);
blk00000003_blk0000064d : MUXCY
port map (
CI => blk00000003_sig00000a04,
DI => blk00000003_sig00000a31,
S => blk00000003_sig00000a05,
O => blk00000003_sig00000a01
);
blk00000003_blk0000064c : MUXCY
port map (
CI => blk00000003_sig00000a01,
DI => blk00000003_sig00000a30,
S => blk00000003_sig00000a02,
O => blk00000003_sig000009fe
);
blk00000003_blk0000064b : MUXCY
port map (
CI => blk00000003_sig000009fe,
DI => blk00000003_sig00000a2f,
S => blk00000003_sig000009ff,
O => blk00000003_sig000009fb
);
blk00000003_blk0000064a : MUXCY
port map (
CI => blk00000003_sig000009fb,
DI => blk00000003_sig00000a2e,
S => blk00000003_sig000009fc,
O => blk00000003_sig000009f8
);
blk00000003_blk00000649 : MUXCY
port map (
CI => blk00000003_sig000009f8,
DI => blk00000003_sig00000a2d,
S => blk00000003_sig000009f9,
O => blk00000003_sig000009f5
);
blk00000003_blk00000648 : MUXCY
port map (
CI => blk00000003_sig000009f5,
DI => blk00000003_sig00000a2c,
S => blk00000003_sig000009f6,
O => blk00000003_sig000009f2
);
blk00000003_blk00000647 : MUXCY
port map (
CI => blk00000003_sig000009f2,
DI => blk00000003_sig00000a2b,
S => blk00000003_sig000009f3,
O => blk00000003_sig000009ef
);
blk00000003_blk00000646 : MUXCY
port map (
CI => blk00000003_sig000009ef,
DI => blk00000003_sig00000a2a,
S => blk00000003_sig000009f0,
O => blk00000003_sig000009ec
);
blk00000003_blk00000645 : MUXCY
port map (
CI => blk00000003_sig000009ec,
DI => blk00000003_sig00000a29,
S => blk00000003_sig000009ed,
O => blk00000003_sig000009e9
);
blk00000003_blk00000644 : MUXCY
port map (
CI => blk00000003_sig000009e9,
DI => blk00000003_sig00000a28,
S => blk00000003_sig000009ea,
O => blk00000003_sig000009e6
);
blk00000003_blk00000643 : MUXCY
port map (
CI => blk00000003_sig000009e6,
DI => blk00000003_sig00000a27,
S => blk00000003_sig000009e7,
O => blk00000003_sig000009e3
);
blk00000003_blk00000642 : MUXCY
port map (
CI => blk00000003_sig000009e3,
DI => blk00000003_sig00000a26,
S => blk00000003_sig000009e4,
O => blk00000003_sig000009e0
);
blk00000003_blk00000641 : MUXCY
port map (
CI => blk00000003_sig000009e0,
DI => blk00000003_sig00000a25,
S => blk00000003_sig000009e1,
O => blk00000003_sig000009dd
);
blk00000003_blk00000640 : XORCY
port map (
CI => blk00000003_sig00000a22,
LI => blk00000003_sig00000a23,
O => blk00000003_sig00000a24
);
blk00000003_blk0000063f : XORCY
port map (
CI => blk00000003_sig00000a1f,
LI => blk00000003_sig00000a20,
O => blk00000003_sig00000a21
);
blk00000003_blk0000063e : XORCY
port map (
CI => blk00000003_sig00000a1c,
LI => blk00000003_sig00000a1d,
O => blk00000003_sig00000a1e
);
blk00000003_blk0000063d : XORCY
port map (
CI => blk00000003_sig00000a19,
LI => blk00000003_sig00000a1a,
O => blk00000003_sig00000a1b
);
blk00000003_blk0000063c : XORCY
port map (
CI => blk00000003_sig00000a16,
LI => blk00000003_sig00000a17,
O => blk00000003_sig00000a18
);
blk00000003_blk0000063b : XORCY
port map (
CI => blk00000003_sig00000a13,
LI => blk00000003_sig00000a14,
O => blk00000003_sig00000a15
);
blk00000003_blk0000063a : XORCY
port map (
CI => blk00000003_sig00000a10,
LI => blk00000003_sig00000a11,
O => blk00000003_sig00000a12
);
blk00000003_blk00000639 : XORCY
port map (
CI => blk00000003_sig00000a0d,
LI => blk00000003_sig00000a0e,
O => blk00000003_sig00000a0f
);
blk00000003_blk00000638 : XORCY
port map (
CI => blk00000003_sig00000a0a,
LI => blk00000003_sig00000a0b,
O => blk00000003_sig00000a0c
);
blk00000003_blk00000637 : XORCY
port map (
CI => blk00000003_sig00000a07,
LI => blk00000003_sig00000a08,
O => blk00000003_sig00000a09
);
blk00000003_blk00000636 : XORCY
port map (
CI => blk00000003_sig00000a04,
LI => blk00000003_sig00000a05,
O => blk00000003_sig00000a06
);
blk00000003_blk00000635 : XORCY
port map (
CI => blk00000003_sig00000a01,
LI => blk00000003_sig00000a02,
O => blk00000003_sig00000a03
);
blk00000003_blk00000634 : XORCY
port map (
CI => blk00000003_sig000009fe,
LI => blk00000003_sig000009ff,
O => blk00000003_sig00000a00
);
blk00000003_blk00000633 : XORCY
port map (
CI => blk00000003_sig000009fb,
LI => blk00000003_sig000009fc,
O => blk00000003_sig000009fd
);
blk00000003_blk00000632 : XORCY
port map (
CI => blk00000003_sig000009f8,
LI => blk00000003_sig000009f9,
O => blk00000003_sig000009fa
);
blk00000003_blk00000631 : XORCY
port map (
CI => blk00000003_sig000009f5,
LI => blk00000003_sig000009f6,
O => blk00000003_sig000009f7
);
blk00000003_blk00000630 : XORCY
port map (
CI => blk00000003_sig000009f2,
LI => blk00000003_sig000009f3,
O => blk00000003_sig000009f4
);
blk00000003_blk0000062f : XORCY
port map (
CI => blk00000003_sig000009ef,
LI => blk00000003_sig000009f0,
O => blk00000003_sig000009f1
);
blk00000003_blk0000062e : XORCY
port map (
CI => blk00000003_sig000009ec,
LI => blk00000003_sig000009ed,
O => blk00000003_sig000009ee
);
blk00000003_blk0000062d : XORCY
port map (
CI => blk00000003_sig000009e9,
LI => blk00000003_sig000009ea,
O => blk00000003_sig000009eb
);
blk00000003_blk0000062c : XORCY
port map (
CI => blk00000003_sig000009e6,
LI => blk00000003_sig000009e7,
O => blk00000003_sig000009e8
);
blk00000003_blk0000062b : XORCY
port map (
CI => blk00000003_sig000009e3,
LI => blk00000003_sig000009e4,
O => blk00000003_sig000009e5
);
blk00000003_blk0000062a : XORCY
port map (
CI => blk00000003_sig000009e0,
LI => blk00000003_sig000009e1,
O => blk00000003_sig000009e2
);
blk00000003_blk00000629 : XORCY
port map (
CI => blk00000003_sig000009dd,
LI => blk00000003_sig000009de,
O => blk00000003_sig000009df
);
blk00000003_blk00000628 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig000009d7,
Q => blk00000003_sig000009dc
);
blk00000003_blk00000627 : MUXCY
port map (
CI => blk00000003_sig000009d8,
DI => blk00000003_sig000009db,
S => blk00000003_sig000009d9,
O => blk00000003_sig000009bc
);
blk00000003_blk00000626 : XORCY
port map (
CI => blk00000003_sig000009d8,
LI => blk00000003_sig000009d9,
O => blk00000003_sig000009da
);
blk00000003_blk00000625 : MUXCY
port map (
CI => blk00000003_sig00000977,
DI => blk00000003_sig000009d6,
S => blk00000003_sig00000978,
O => blk00000003_sig000009d7
);
blk00000003_blk00000624 : MUXCY
port map (
CI => blk00000003_sig000009bc,
DI => blk00000003_sig000009d5,
S => blk00000003_sig000009bd,
O => blk00000003_sig000009b9
);
blk00000003_blk00000623 : MUXCY
port map (
CI => blk00000003_sig000009b9,
DI => blk00000003_sig000009d4,
S => blk00000003_sig000009ba,
O => blk00000003_sig000009b6
);
blk00000003_blk00000622 : MUXCY
port map (
CI => blk00000003_sig000009b6,
DI => blk00000003_sig000009d3,
S => blk00000003_sig000009b7,
O => blk00000003_sig000009b3
);
blk00000003_blk00000621 : MUXCY
port map (
CI => blk00000003_sig000009b3,
DI => blk00000003_sig000009d2,
S => blk00000003_sig000009b4,
O => blk00000003_sig000009b0
);
blk00000003_blk00000620 : MUXCY
port map (
CI => blk00000003_sig000009b0,
DI => blk00000003_sig000009d1,
S => blk00000003_sig000009b1,
O => blk00000003_sig000009ad
);
blk00000003_blk0000061f : MUXCY
port map (
CI => blk00000003_sig000009ad,
DI => blk00000003_sig000009d0,
S => blk00000003_sig000009ae,
O => blk00000003_sig000009aa
);
blk00000003_blk0000061e : MUXCY
port map (
CI => blk00000003_sig000009aa,
DI => blk00000003_sig000009cf,
S => blk00000003_sig000009ab,
O => blk00000003_sig000009a7
);
blk00000003_blk0000061d : MUXCY
port map (
CI => blk00000003_sig000009a7,
DI => blk00000003_sig000009ce,
S => blk00000003_sig000009a8,
O => blk00000003_sig000009a4
);
blk00000003_blk0000061c : MUXCY
port map (
CI => blk00000003_sig000009a4,
DI => blk00000003_sig000009cd,
S => blk00000003_sig000009a5,
O => blk00000003_sig000009a1
);
blk00000003_blk0000061b : MUXCY
port map (
CI => blk00000003_sig000009a1,
DI => blk00000003_sig000009cc,
S => blk00000003_sig000009a2,
O => blk00000003_sig0000099e
);
blk00000003_blk0000061a : MUXCY
port map (
CI => blk00000003_sig0000099e,
DI => blk00000003_sig000009cb,
S => blk00000003_sig0000099f,
O => blk00000003_sig0000099b
);
blk00000003_blk00000619 : MUXCY
port map (
CI => blk00000003_sig0000099b,
DI => blk00000003_sig000009ca,
S => blk00000003_sig0000099c,
O => blk00000003_sig00000998
);
blk00000003_blk00000618 : MUXCY
port map (
CI => blk00000003_sig00000998,
DI => blk00000003_sig000009c9,
S => blk00000003_sig00000999,
O => blk00000003_sig00000995
);
blk00000003_blk00000617 : MUXCY
port map (
CI => blk00000003_sig00000995,
DI => blk00000003_sig000009c8,
S => blk00000003_sig00000996,
O => blk00000003_sig00000992
);
blk00000003_blk00000616 : MUXCY
port map (
CI => blk00000003_sig00000992,
DI => blk00000003_sig000009c7,
S => blk00000003_sig00000993,
O => blk00000003_sig0000098f
);
blk00000003_blk00000615 : MUXCY
port map (
CI => blk00000003_sig0000098f,
DI => blk00000003_sig000009c6,
S => blk00000003_sig00000990,
O => blk00000003_sig0000098c
);
blk00000003_blk00000614 : MUXCY
port map (
CI => blk00000003_sig0000098c,
DI => blk00000003_sig000009c5,
S => blk00000003_sig0000098d,
O => blk00000003_sig00000989
);
blk00000003_blk00000613 : MUXCY
port map (
CI => blk00000003_sig00000989,
DI => blk00000003_sig000009c4,
S => blk00000003_sig0000098a,
O => blk00000003_sig00000986
);
blk00000003_blk00000612 : MUXCY
port map (
CI => blk00000003_sig00000986,
DI => blk00000003_sig000009c3,
S => blk00000003_sig00000987,
O => blk00000003_sig00000983
);
blk00000003_blk00000611 : MUXCY
port map (
CI => blk00000003_sig00000983,
DI => blk00000003_sig000009c2,
S => blk00000003_sig00000984,
O => blk00000003_sig00000980
);
blk00000003_blk00000610 : MUXCY
port map (
CI => blk00000003_sig00000980,
DI => blk00000003_sig000009c1,
S => blk00000003_sig00000981,
O => blk00000003_sig0000097d
);
blk00000003_blk0000060f : MUXCY
port map (
CI => blk00000003_sig0000097d,
DI => blk00000003_sig000009c0,
S => blk00000003_sig0000097e,
O => blk00000003_sig0000097a
);
blk00000003_blk0000060e : MUXCY
port map (
CI => blk00000003_sig0000097a,
DI => blk00000003_sig000009bf,
S => blk00000003_sig0000097b,
O => blk00000003_sig00000977
);
blk00000003_blk0000060d : XORCY
port map (
CI => blk00000003_sig000009bc,
LI => blk00000003_sig000009bd,
O => blk00000003_sig000009be
);
blk00000003_blk0000060c : XORCY
port map (
CI => blk00000003_sig000009b9,
LI => blk00000003_sig000009ba,
O => blk00000003_sig000009bb
);
blk00000003_blk0000060b : XORCY
port map (
CI => blk00000003_sig000009b6,
LI => blk00000003_sig000009b7,
O => blk00000003_sig000009b8
);
blk00000003_blk0000060a : XORCY
port map (
CI => blk00000003_sig000009b3,
LI => blk00000003_sig000009b4,
O => blk00000003_sig000009b5
);
blk00000003_blk00000609 : XORCY
port map (
CI => blk00000003_sig000009b0,
LI => blk00000003_sig000009b1,
O => blk00000003_sig000009b2
);
blk00000003_blk00000608 : XORCY
port map (
CI => blk00000003_sig000009ad,
LI => blk00000003_sig000009ae,
O => blk00000003_sig000009af
);
blk00000003_blk00000607 : XORCY
port map (
CI => blk00000003_sig000009aa,
LI => blk00000003_sig000009ab,
O => blk00000003_sig000009ac
);
blk00000003_blk00000606 : XORCY
port map (
CI => blk00000003_sig000009a7,
LI => blk00000003_sig000009a8,
O => blk00000003_sig000009a9
);
blk00000003_blk00000605 : XORCY
port map (
CI => blk00000003_sig000009a4,
LI => blk00000003_sig000009a5,
O => blk00000003_sig000009a6
);
blk00000003_blk00000604 : XORCY
port map (
CI => blk00000003_sig000009a1,
LI => blk00000003_sig000009a2,
O => blk00000003_sig000009a3
);
blk00000003_blk00000603 : XORCY
port map (
CI => blk00000003_sig0000099e,
LI => blk00000003_sig0000099f,
O => blk00000003_sig000009a0
);
blk00000003_blk00000602 : XORCY
port map (
CI => blk00000003_sig0000099b,
LI => blk00000003_sig0000099c,
O => blk00000003_sig0000099d
);
blk00000003_blk00000601 : XORCY
port map (
CI => blk00000003_sig00000998,
LI => blk00000003_sig00000999,
O => blk00000003_sig0000099a
);
blk00000003_blk00000600 : XORCY
port map (
CI => blk00000003_sig00000995,
LI => blk00000003_sig00000996,
O => blk00000003_sig00000997
);
blk00000003_blk000005ff : XORCY
port map (
CI => blk00000003_sig00000992,
LI => blk00000003_sig00000993,
O => blk00000003_sig00000994
);
blk00000003_blk000005fe : XORCY
port map (
CI => blk00000003_sig0000098f,
LI => blk00000003_sig00000990,
O => blk00000003_sig00000991
);
blk00000003_blk000005fd : XORCY
port map (
CI => blk00000003_sig0000098c,
LI => blk00000003_sig0000098d,
O => blk00000003_sig0000098e
);
blk00000003_blk000005fc : XORCY
port map (
CI => blk00000003_sig00000989,
LI => blk00000003_sig0000098a,
O => blk00000003_sig0000098b
);
blk00000003_blk000005fb : XORCY
port map (
CI => blk00000003_sig00000986,
LI => blk00000003_sig00000987,
O => blk00000003_sig00000988
);
blk00000003_blk000005fa : XORCY
port map (
CI => blk00000003_sig00000983,
LI => blk00000003_sig00000984,
O => blk00000003_sig00000985
);
blk00000003_blk000005f9 : XORCY
port map (
CI => blk00000003_sig00000980,
LI => blk00000003_sig00000981,
O => blk00000003_sig00000982
);
blk00000003_blk000005f8 : XORCY
port map (
CI => blk00000003_sig0000097d,
LI => blk00000003_sig0000097e,
O => blk00000003_sig0000097f
);
blk00000003_blk000005f7 : XORCY
port map (
CI => blk00000003_sig0000097a,
LI => blk00000003_sig0000097b,
O => blk00000003_sig0000097c
);
blk00000003_blk000005f6 : XORCY
port map (
CI => blk00000003_sig00000977,
LI => blk00000003_sig00000978,
O => blk00000003_sig00000979
);
blk00000003_blk000005f5 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000971,
Q => blk00000003_sig00000976
);
blk00000003_blk000005f4 : MUXCY
port map (
CI => blk00000003_sig00000972,
DI => blk00000003_sig00000975,
S => blk00000003_sig00000973,
O => blk00000003_sig00000956
);
blk00000003_blk000005f3 : XORCY
port map (
CI => blk00000003_sig00000972,
LI => blk00000003_sig00000973,
O => blk00000003_sig00000974
);
blk00000003_blk000005f2 : MUXCY
port map (
CI => blk00000003_sig00000911,
DI => blk00000003_sig00000970,
S => blk00000003_sig00000912,
O => blk00000003_sig00000971
);
blk00000003_blk000005f1 : MUXCY
port map (
CI => blk00000003_sig00000956,
DI => blk00000003_sig0000096f,
S => blk00000003_sig00000957,
O => blk00000003_sig00000953
);
blk00000003_blk000005f0 : MUXCY
port map (
CI => blk00000003_sig00000953,
DI => blk00000003_sig0000096e,
S => blk00000003_sig00000954,
O => blk00000003_sig00000950
);
blk00000003_blk000005ef : MUXCY
port map (
CI => blk00000003_sig00000950,
DI => blk00000003_sig0000096d,
S => blk00000003_sig00000951,
O => blk00000003_sig0000094d
);
blk00000003_blk000005ee : MUXCY
port map (
CI => blk00000003_sig0000094d,
DI => blk00000003_sig0000096c,
S => blk00000003_sig0000094e,
O => blk00000003_sig0000094a
);
blk00000003_blk000005ed : MUXCY
port map (
CI => blk00000003_sig0000094a,
DI => blk00000003_sig0000096b,
S => blk00000003_sig0000094b,
O => blk00000003_sig00000947
);
blk00000003_blk000005ec : MUXCY
port map (
CI => blk00000003_sig00000947,
DI => blk00000003_sig0000096a,
S => blk00000003_sig00000948,
O => blk00000003_sig00000944
);
blk00000003_blk000005eb : MUXCY
port map (
CI => blk00000003_sig00000944,
DI => blk00000003_sig00000969,
S => blk00000003_sig00000945,
O => blk00000003_sig00000941
);
blk00000003_blk000005ea : MUXCY
port map (
CI => blk00000003_sig00000941,
DI => blk00000003_sig00000968,
S => blk00000003_sig00000942,
O => blk00000003_sig0000093e
);
blk00000003_blk000005e9 : MUXCY
port map (
CI => blk00000003_sig0000093e,
DI => blk00000003_sig00000967,
S => blk00000003_sig0000093f,
O => blk00000003_sig0000093b
);
blk00000003_blk000005e8 : MUXCY
port map (
CI => blk00000003_sig0000093b,
DI => blk00000003_sig00000966,
S => blk00000003_sig0000093c,
O => blk00000003_sig00000938
);
blk00000003_blk000005e7 : MUXCY
port map (
CI => blk00000003_sig00000938,
DI => blk00000003_sig00000965,
S => blk00000003_sig00000939,
O => blk00000003_sig00000935
);
blk00000003_blk000005e6 : MUXCY
port map (
CI => blk00000003_sig00000935,
DI => blk00000003_sig00000964,
S => blk00000003_sig00000936,
O => blk00000003_sig00000932
);
blk00000003_blk000005e5 : MUXCY
port map (
CI => blk00000003_sig00000932,
DI => blk00000003_sig00000963,
S => blk00000003_sig00000933,
O => blk00000003_sig0000092f
);
blk00000003_blk000005e4 : MUXCY
port map (
CI => blk00000003_sig0000092f,
DI => blk00000003_sig00000962,
S => blk00000003_sig00000930,
O => blk00000003_sig0000092c
);
blk00000003_blk000005e3 : MUXCY
port map (
CI => blk00000003_sig0000092c,
DI => blk00000003_sig00000961,
S => blk00000003_sig0000092d,
O => blk00000003_sig00000929
);
blk00000003_blk000005e2 : MUXCY
port map (
CI => blk00000003_sig00000929,
DI => blk00000003_sig00000960,
S => blk00000003_sig0000092a,
O => blk00000003_sig00000926
);
blk00000003_blk000005e1 : MUXCY
port map (
CI => blk00000003_sig00000926,
DI => blk00000003_sig0000095f,
S => blk00000003_sig00000927,
O => blk00000003_sig00000923
);
blk00000003_blk000005e0 : MUXCY
port map (
CI => blk00000003_sig00000923,
DI => blk00000003_sig0000095e,
S => blk00000003_sig00000924,
O => blk00000003_sig00000920
);
blk00000003_blk000005df : MUXCY
port map (
CI => blk00000003_sig00000920,
DI => blk00000003_sig0000095d,
S => blk00000003_sig00000921,
O => blk00000003_sig0000091d
);
blk00000003_blk000005de : MUXCY
port map (
CI => blk00000003_sig0000091d,
DI => blk00000003_sig0000095c,
S => blk00000003_sig0000091e,
O => blk00000003_sig0000091a
);
blk00000003_blk000005dd : MUXCY
port map (
CI => blk00000003_sig0000091a,
DI => blk00000003_sig0000095b,
S => blk00000003_sig0000091b,
O => blk00000003_sig00000917
);
blk00000003_blk000005dc : MUXCY
port map (
CI => blk00000003_sig00000917,
DI => blk00000003_sig0000095a,
S => blk00000003_sig00000918,
O => blk00000003_sig00000914
);
blk00000003_blk000005db : MUXCY
port map (
CI => blk00000003_sig00000914,
DI => blk00000003_sig00000959,
S => blk00000003_sig00000915,
O => blk00000003_sig00000911
);
blk00000003_blk000005da : XORCY
port map (
CI => blk00000003_sig00000956,
LI => blk00000003_sig00000957,
O => blk00000003_sig00000958
);
blk00000003_blk000005d9 : XORCY
port map (
CI => blk00000003_sig00000953,
LI => blk00000003_sig00000954,
O => blk00000003_sig00000955
);
blk00000003_blk000005d8 : XORCY
port map (
CI => blk00000003_sig00000950,
LI => blk00000003_sig00000951,
O => blk00000003_sig00000952
);
blk00000003_blk000005d7 : XORCY
port map (
CI => blk00000003_sig0000094d,
LI => blk00000003_sig0000094e,
O => blk00000003_sig0000094f
);
blk00000003_blk000005d6 : XORCY
port map (
CI => blk00000003_sig0000094a,
LI => blk00000003_sig0000094b,
O => blk00000003_sig0000094c
);
blk00000003_blk000005d5 : XORCY
port map (
CI => blk00000003_sig00000947,
LI => blk00000003_sig00000948,
O => blk00000003_sig00000949
);
blk00000003_blk000005d4 : XORCY
port map (
CI => blk00000003_sig00000944,
LI => blk00000003_sig00000945,
O => blk00000003_sig00000946
);
blk00000003_blk000005d3 : XORCY
port map (
CI => blk00000003_sig00000941,
LI => blk00000003_sig00000942,
O => blk00000003_sig00000943
);
blk00000003_blk000005d2 : XORCY
port map (
CI => blk00000003_sig0000093e,
LI => blk00000003_sig0000093f,
O => blk00000003_sig00000940
);
blk00000003_blk000005d1 : XORCY
port map (
CI => blk00000003_sig0000093b,
LI => blk00000003_sig0000093c,
O => blk00000003_sig0000093d
);
blk00000003_blk000005d0 : XORCY
port map (
CI => blk00000003_sig00000938,
LI => blk00000003_sig00000939,
O => blk00000003_sig0000093a
);
blk00000003_blk000005cf : XORCY
port map (
CI => blk00000003_sig00000935,
LI => blk00000003_sig00000936,
O => blk00000003_sig00000937
);
blk00000003_blk000005ce : XORCY
port map (
CI => blk00000003_sig00000932,
LI => blk00000003_sig00000933,
O => blk00000003_sig00000934
);
blk00000003_blk000005cd : XORCY
port map (
CI => blk00000003_sig0000092f,
LI => blk00000003_sig00000930,
O => blk00000003_sig00000931
);
blk00000003_blk000005cc : XORCY
port map (
CI => blk00000003_sig0000092c,
LI => blk00000003_sig0000092d,
O => blk00000003_sig0000092e
);
blk00000003_blk000005cb : XORCY
port map (
CI => blk00000003_sig00000929,
LI => blk00000003_sig0000092a,
O => blk00000003_sig0000092b
);
blk00000003_blk000005ca : XORCY
port map (
CI => blk00000003_sig00000926,
LI => blk00000003_sig00000927,
O => blk00000003_sig00000928
);
blk00000003_blk000005c9 : XORCY
port map (
CI => blk00000003_sig00000923,
LI => blk00000003_sig00000924,
O => blk00000003_sig00000925
);
blk00000003_blk000005c8 : XORCY
port map (
CI => blk00000003_sig00000920,
LI => blk00000003_sig00000921,
O => blk00000003_sig00000922
);
blk00000003_blk000005c7 : XORCY
port map (
CI => blk00000003_sig0000091d,
LI => blk00000003_sig0000091e,
O => blk00000003_sig0000091f
);
blk00000003_blk000005c6 : XORCY
port map (
CI => blk00000003_sig0000091a,
LI => blk00000003_sig0000091b,
O => blk00000003_sig0000091c
);
blk00000003_blk000005c5 : XORCY
port map (
CI => blk00000003_sig00000917,
LI => blk00000003_sig00000918,
O => blk00000003_sig00000919
);
blk00000003_blk000005c4 : XORCY
port map (
CI => blk00000003_sig00000914,
LI => blk00000003_sig00000915,
O => blk00000003_sig00000916
);
blk00000003_blk000005c3 : XORCY
port map (
CI => blk00000003_sig00000911,
LI => blk00000003_sig00000912,
O => blk00000003_sig00000913
);
blk00000003_blk000005c2 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig0000090b,
Q => blk00000003_sig00000910
);
blk00000003_blk000005c1 : MUXCY
port map (
CI => blk00000003_sig0000090c,
DI => blk00000003_sig0000090f,
S => blk00000003_sig0000090d,
O => blk00000003_sig000008f0
);
blk00000003_blk000005c0 : XORCY
port map (
CI => blk00000003_sig0000090c,
LI => blk00000003_sig0000090d,
O => blk00000003_sig0000090e
);
blk00000003_blk000005bf : MUXCY
port map (
CI => blk00000003_sig000008ab,
DI => blk00000003_sig0000090a,
S => blk00000003_sig000008ac,
O => blk00000003_sig0000090b
);
blk00000003_blk000005be : MUXCY
port map (
CI => blk00000003_sig000008f0,
DI => blk00000003_sig00000909,
S => blk00000003_sig000008f1,
O => blk00000003_sig000008ed
);
blk00000003_blk000005bd : MUXCY
port map (
CI => blk00000003_sig000008ed,
DI => blk00000003_sig00000908,
S => blk00000003_sig000008ee,
O => blk00000003_sig000008ea
);
blk00000003_blk000005bc : MUXCY
port map (
CI => blk00000003_sig000008ea,
DI => blk00000003_sig00000907,
S => blk00000003_sig000008eb,
O => blk00000003_sig000008e7
);
blk00000003_blk000005bb : MUXCY
port map (
CI => blk00000003_sig000008e7,
DI => blk00000003_sig00000906,
S => blk00000003_sig000008e8,
O => blk00000003_sig000008e4
);
blk00000003_blk000005ba : MUXCY
port map (
CI => blk00000003_sig000008e4,
DI => blk00000003_sig00000905,
S => blk00000003_sig000008e5,
O => blk00000003_sig000008e1
);
blk00000003_blk000005b9 : MUXCY
port map (
CI => blk00000003_sig000008e1,
DI => blk00000003_sig00000904,
S => blk00000003_sig000008e2,
O => blk00000003_sig000008de
);
blk00000003_blk000005b8 : MUXCY
port map (
CI => blk00000003_sig000008de,
DI => blk00000003_sig00000903,
S => blk00000003_sig000008df,
O => blk00000003_sig000008db
);
blk00000003_blk000005b7 : MUXCY
port map (
CI => blk00000003_sig000008db,
DI => blk00000003_sig00000902,
S => blk00000003_sig000008dc,
O => blk00000003_sig000008d8
);
blk00000003_blk000005b6 : MUXCY
port map (
CI => blk00000003_sig000008d8,
DI => blk00000003_sig00000901,
S => blk00000003_sig000008d9,
O => blk00000003_sig000008d5
);
blk00000003_blk000005b5 : MUXCY
port map (
CI => blk00000003_sig000008d5,
DI => blk00000003_sig00000900,
S => blk00000003_sig000008d6,
O => blk00000003_sig000008d2
);
blk00000003_blk000005b4 : MUXCY
port map (
CI => blk00000003_sig000008d2,
DI => blk00000003_sig000008ff,
S => blk00000003_sig000008d3,
O => blk00000003_sig000008cf
);
blk00000003_blk000005b3 : MUXCY
port map (
CI => blk00000003_sig000008cf,
DI => blk00000003_sig000008fe,
S => blk00000003_sig000008d0,
O => blk00000003_sig000008cc
);
blk00000003_blk000005b2 : MUXCY
port map (
CI => blk00000003_sig000008cc,
DI => blk00000003_sig000008fd,
S => blk00000003_sig000008cd,
O => blk00000003_sig000008c9
);
blk00000003_blk000005b1 : MUXCY
port map (
CI => blk00000003_sig000008c9,
DI => blk00000003_sig000008fc,
S => blk00000003_sig000008ca,
O => blk00000003_sig000008c6
);
blk00000003_blk000005b0 : MUXCY
port map (
CI => blk00000003_sig000008c6,
DI => blk00000003_sig000008fb,
S => blk00000003_sig000008c7,
O => blk00000003_sig000008c3
);
blk00000003_blk000005af : MUXCY
port map (
CI => blk00000003_sig000008c3,
DI => blk00000003_sig000008fa,
S => blk00000003_sig000008c4,
O => blk00000003_sig000008c0
);
blk00000003_blk000005ae : MUXCY
port map (
CI => blk00000003_sig000008c0,
DI => blk00000003_sig000008f9,
S => blk00000003_sig000008c1,
O => blk00000003_sig000008bd
);
blk00000003_blk000005ad : MUXCY
port map (
CI => blk00000003_sig000008bd,
DI => blk00000003_sig000008f8,
S => blk00000003_sig000008be,
O => blk00000003_sig000008ba
);
blk00000003_blk000005ac : MUXCY
port map (
CI => blk00000003_sig000008ba,
DI => blk00000003_sig000008f7,
S => blk00000003_sig000008bb,
O => blk00000003_sig000008b7
);
blk00000003_blk000005ab : MUXCY
port map (
CI => blk00000003_sig000008b7,
DI => blk00000003_sig000008f6,
S => blk00000003_sig000008b8,
O => blk00000003_sig000008b4
);
blk00000003_blk000005aa : MUXCY
port map (
CI => blk00000003_sig000008b4,
DI => blk00000003_sig000008f5,
S => blk00000003_sig000008b5,
O => blk00000003_sig000008b1
);
blk00000003_blk000005a9 : MUXCY
port map (
CI => blk00000003_sig000008b1,
DI => blk00000003_sig000008f4,
S => blk00000003_sig000008b2,
O => blk00000003_sig000008ae
);
blk00000003_blk000005a8 : MUXCY
port map (
CI => blk00000003_sig000008ae,
DI => blk00000003_sig000008f3,
S => blk00000003_sig000008af,
O => blk00000003_sig000008ab
);
blk00000003_blk000005a7 : XORCY
port map (
CI => blk00000003_sig000008f0,
LI => blk00000003_sig000008f1,
O => blk00000003_sig000008f2
);
blk00000003_blk000005a6 : XORCY
port map (
CI => blk00000003_sig000008ed,
LI => blk00000003_sig000008ee,
O => blk00000003_sig000008ef
);
blk00000003_blk000005a5 : XORCY
port map (
CI => blk00000003_sig000008ea,
LI => blk00000003_sig000008eb,
O => blk00000003_sig000008ec
);
blk00000003_blk000005a4 : XORCY
port map (
CI => blk00000003_sig000008e7,
LI => blk00000003_sig000008e8,
O => blk00000003_sig000008e9
);
blk00000003_blk000005a3 : XORCY
port map (
CI => blk00000003_sig000008e4,
LI => blk00000003_sig000008e5,
O => blk00000003_sig000008e6
);
blk00000003_blk000005a2 : XORCY
port map (
CI => blk00000003_sig000008e1,
LI => blk00000003_sig000008e2,
O => blk00000003_sig000008e3
);
blk00000003_blk000005a1 : XORCY
port map (
CI => blk00000003_sig000008de,
LI => blk00000003_sig000008df,
O => blk00000003_sig000008e0
);
blk00000003_blk000005a0 : XORCY
port map (
CI => blk00000003_sig000008db,
LI => blk00000003_sig000008dc,
O => blk00000003_sig000008dd
);
blk00000003_blk0000059f : XORCY
port map (
CI => blk00000003_sig000008d8,
LI => blk00000003_sig000008d9,
O => blk00000003_sig000008da
);
blk00000003_blk0000059e : XORCY
port map (
CI => blk00000003_sig000008d5,
LI => blk00000003_sig000008d6,
O => blk00000003_sig000008d7
);
blk00000003_blk0000059d : XORCY
port map (
CI => blk00000003_sig000008d2,
LI => blk00000003_sig000008d3,
O => blk00000003_sig000008d4
);
blk00000003_blk0000059c : XORCY
port map (
CI => blk00000003_sig000008cf,
LI => blk00000003_sig000008d0,
O => blk00000003_sig000008d1
);
blk00000003_blk0000059b : XORCY
port map (
CI => blk00000003_sig000008cc,
LI => blk00000003_sig000008cd,
O => blk00000003_sig000008ce
);
blk00000003_blk0000059a : XORCY
port map (
CI => blk00000003_sig000008c9,
LI => blk00000003_sig000008ca,
O => blk00000003_sig000008cb
);
blk00000003_blk00000599 : XORCY
port map (
CI => blk00000003_sig000008c6,
LI => blk00000003_sig000008c7,
O => blk00000003_sig000008c8
);
blk00000003_blk00000598 : XORCY
port map (
CI => blk00000003_sig000008c3,
LI => blk00000003_sig000008c4,
O => blk00000003_sig000008c5
);
blk00000003_blk00000597 : XORCY
port map (
CI => blk00000003_sig000008c0,
LI => blk00000003_sig000008c1,
O => blk00000003_sig000008c2
);
blk00000003_blk00000596 : XORCY
port map (
CI => blk00000003_sig000008bd,
LI => blk00000003_sig000008be,
O => blk00000003_sig000008bf
);
blk00000003_blk00000595 : XORCY
port map (
CI => blk00000003_sig000008ba,
LI => blk00000003_sig000008bb,
O => blk00000003_sig000008bc
);
blk00000003_blk00000594 : XORCY
port map (
CI => blk00000003_sig000008b7,
LI => blk00000003_sig000008b8,
O => blk00000003_sig000008b9
);
blk00000003_blk00000593 : XORCY
port map (
CI => blk00000003_sig000008b4,
LI => blk00000003_sig000008b5,
O => blk00000003_sig000008b6
);
blk00000003_blk00000592 : XORCY
port map (
CI => blk00000003_sig000008b1,
LI => blk00000003_sig000008b2,
O => blk00000003_sig000008b3
);
blk00000003_blk00000591 : XORCY
port map (
CI => blk00000003_sig000008ae,
LI => blk00000003_sig000008af,
O => blk00000003_sig000008b0
);
blk00000003_blk00000590 : XORCY
port map (
CI => blk00000003_sig000008ab,
LI => blk00000003_sig000008ac,
O => blk00000003_sig000008ad
);
blk00000003_blk0000058f : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig000008a5,
Q => blk00000003_sig000008aa
);
blk00000003_blk0000058e : MUXCY
port map (
CI => blk00000003_sig000008a6,
DI => blk00000003_sig000008a9,
S => blk00000003_sig000008a7,
O => blk00000003_sig0000088a
);
blk00000003_blk0000058d : XORCY
port map (
CI => blk00000003_sig000008a6,
LI => blk00000003_sig000008a7,
O => blk00000003_sig000008a8
);
blk00000003_blk0000058c : MUXCY
port map (
CI => blk00000003_sig00000845,
DI => blk00000003_sig000008a4,
S => blk00000003_sig00000846,
O => blk00000003_sig000008a5
);
blk00000003_blk0000058b : MUXCY
port map (
CI => blk00000003_sig0000088a,
DI => blk00000003_sig000008a3,
S => blk00000003_sig0000088b,
O => blk00000003_sig00000887
);
blk00000003_blk0000058a : MUXCY
port map (
CI => blk00000003_sig00000887,
DI => blk00000003_sig000008a2,
S => blk00000003_sig00000888,
O => blk00000003_sig00000884
);
blk00000003_blk00000589 : MUXCY
port map (
CI => blk00000003_sig00000884,
DI => blk00000003_sig000008a1,
S => blk00000003_sig00000885,
O => blk00000003_sig00000881
);
blk00000003_blk00000588 : MUXCY
port map (
CI => blk00000003_sig00000881,
DI => blk00000003_sig000008a0,
S => blk00000003_sig00000882,
O => blk00000003_sig0000087e
);
blk00000003_blk00000587 : MUXCY
port map (
CI => blk00000003_sig0000087e,
DI => blk00000003_sig0000089f,
S => blk00000003_sig0000087f,
O => blk00000003_sig0000087b
);
blk00000003_blk00000586 : MUXCY
port map (
CI => blk00000003_sig0000087b,
DI => blk00000003_sig0000089e,
S => blk00000003_sig0000087c,
O => blk00000003_sig00000878
);
blk00000003_blk00000585 : MUXCY
port map (
CI => blk00000003_sig00000878,
DI => blk00000003_sig0000089d,
S => blk00000003_sig00000879,
O => blk00000003_sig00000875
);
blk00000003_blk00000584 : MUXCY
port map (
CI => blk00000003_sig00000875,
DI => blk00000003_sig0000089c,
S => blk00000003_sig00000876,
O => blk00000003_sig00000872
);
blk00000003_blk00000583 : MUXCY
port map (
CI => blk00000003_sig00000872,
DI => blk00000003_sig0000089b,
S => blk00000003_sig00000873,
O => blk00000003_sig0000086f
);
blk00000003_blk00000582 : MUXCY
port map (
CI => blk00000003_sig0000086f,
DI => blk00000003_sig0000089a,
S => blk00000003_sig00000870,
O => blk00000003_sig0000086c
);
blk00000003_blk00000581 : MUXCY
port map (
CI => blk00000003_sig0000086c,
DI => blk00000003_sig00000899,
S => blk00000003_sig0000086d,
O => blk00000003_sig00000869
);
blk00000003_blk00000580 : MUXCY
port map (
CI => blk00000003_sig00000869,
DI => blk00000003_sig00000898,
S => blk00000003_sig0000086a,
O => blk00000003_sig00000866
);
blk00000003_blk0000057f : MUXCY
port map (
CI => blk00000003_sig00000866,
DI => blk00000003_sig00000897,
S => blk00000003_sig00000867,
O => blk00000003_sig00000863
);
blk00000003_blk0000057e : MUXCY
port map (
CI => blk00000003_sig00000863,
DI => blk00000003_sig00000896,
S => blk00000003_sig00000864,
O => blk00000003_sig00000860
);
blk00000003_blk0000057d : MUXCY
port map (
CI => blk00000003_sig00000860,
DI => blk00000003_sig00000895,
S => blk00000003_sig00000861,
O => blk00000003_sig0000085d
);
blk00000003_blk0000057c : MUXCY
port map (
CI => blk00000003_sig0000085d,
DI => blk00000003_sig00000894,
S => blk00000003_sig0000085e,
O => blk00000003_sig0000085a
);
blk00000003_blk0000057b : MUXCY
port map (
CI => blk00000003_sig0000085a,
DI => blk00000003_sig00000893,
S => blk00000003_sig0000085b,
O => blk00000003_sig00000857
);
blk00000003_blk0000057a : MUXCY
port map (
CI => blk00000003_sig00000857,
DI => blk00000003_sig00000892,
S => blk00000003_sig00000858,
O => blk00000003_sig00000854
);
blk00000003_blk00000579 : MUXCY
port map (
CI => blk00000003_sig00000854,
DI => blk00000003_sig00000891,
S => blk00000003_sig00000855,
O => blk00000003_sig00000851
);
blk00000003_blk00000578 : MUXCY
port map (
CI => blk00000003_sig00000851,
DI => blk00000003_sig00000890,
S => blk00000003_sig00000852,
O => blk00000003_sig0000084e
);
blk00000003_blk00000577 : MUXCY
port map (
CI => blk00000003_sig0000084e,
DI => blk00000003_sig0000088f,
S => blk00000003_sig0000084f,
O => blk00000003_sig0000084b
);
blk00000003_blk00000576 : MUXCY
port map (
CI => blk00000003_sig0000084b,
DI => blk00000003_sig0000088e,
S => blk00000003_sig0000084c,
O => blk00000003_sig00000848
);
blk00000003_blk00000575 : MUXCY
port map (
CI => blk00000003_sig00000848,
DI => blk00000003_sig0000088d,
S => blk00000003_sig00000849,
O => blk00000003_sig00000845
);
blk00000003_blk00000574 : XORCY
port map (
CI => blk00000003_sig0000088a,
LI => blk00000003_sig0000088b,
O => blk00000003_sig0000088c
);
blk00000003_blk00000573 : XORCY
port map (
CI => blk00000003_sig00000887,
LI => blk00000003_sig00000888,
O => blk00000003_sig00000889
);
blk00000003_blk00000572 : XORCY
port map (
CI => blk00000003_sig00000884,
LI => blk00000003_sig00000885,
O => blk00000003_sig00000886
);
blk00000003_blk00000571 : XORCY
port map (
CI => blk00000003_sig00000881,
LI => blk00000003_sig00000882,
O => blk00000003_sig00000883
);
blk00000003_blk00000570 : XORCY
port map (
CI => blk00000003_sig0000087e,
LI => blk00000003_sig0000087f,
O => blk00000003_sig00000880
);
blk00000003_blk0000056f : XORCY
port map (
CI => blk00000003_sig0000087b,
LI => blk00000003_sig0000087c,
O => blk00000003_sig0000087d
);
blk00000003_blk0000056e : XORCY
port map (
CI => blk00000003_sig00000878,
LI => blk00000003_sig00000879,
O => blk00000003_sig0000087a
);
blk00000003_blk0000056d : XORCY
port map (
CI => blk00000003_sig00000875,
LI => blk00000003_sig00000876,
O => blk00000003_sig00000877
);
blk00000003_blk0000056c : XORCY
port map (
CI => blk00000003_sig00000872,
LI => blk00000003_sig00000873,
O => blk00000003_sig00000874
);
blk00000003_blk0000056b : XORCY
port map (
CI => blk00000003_sig0000086f,
LI => blk00000003_sig00000870,
O => blk00000003_sig00000871
);
blk00000003_blk0000056a : XORCY
port map (
CI => blk00000003_sig0000086c,
LI => blk00000003_sig0000086d,
O => blk00000003_sig0000086e
);
blk00000003_blk00000569 : XORCY
port map (
CI => blk00000003_sig00000869,
LI => blk00000003_sig0000086a,
O => blk00000003_sig0000086b
);
blk00000003_blk00000568 : XORCY
port map (
CI => blk00000003_sig00000866,
LI => blk00000003_sig00000867,
O => blk00000003_sig00000868
);
blk00000003_blk00000567 : XORCY
port map (
CI => blk00000003_sig00000863,
LI => blk00000003_sig00000864,
O => blk00000003_sig00000865
);
blk00000003_blk00000566 : XORCY
port map (
CI => blk00000003_sig00000860,
LI => blk00000003_sig00000861,
O => blk00000003_sig00000862
);
blk00000003_blk00000565 : XORCY
port map (
CI => blk00000003_sig0000085d,
LI => blk00000003_sig0000085e,
O => blk00000003_sig0000085f
);
blk00000003_blk00000564 : XORCY
port map (
CI => blk00000003_sig0000085a,
LI => blk00000003_sig0000085b,
O => blk00000003_sig0000085c
);
blk00000003_blk00000563 : XORCY
port map (
CI => blk00000003_sig00000857,
LI => blk00000003_sig00000858,
O => blk00000003_sig00000859
);
blk00000003_blk00000562 : XORCY
port map (
CI => blk00000003_sig00000854,
LI => blk00000003_sig00000855,
O => blk00000003_sig00000856
);
blk00000003_blk00000561 : XORCY
port map (
CI => blk00000003_sig00000851,
LI => blk00000003_sig00000852,
O => blk00000003_sig00000853
);
blk00000003_blk00000560 : XORCY
port map (
CI => blk00000003_sig0000084e,
LI => blk00000003_sig0000084f,
O => blk00000003_sig00000850
);
blk00000003_blk0000055f : XORCY
port map (
CI => blk00000003_sig0000084b,
LI => blk00000003_sig0000084c,
O => blk00000003_sig0000084d
);
blk00000003_blk0000055e : XORCY
port map (
CI => blk00000003_sig00000848,
LI => blk00000003_sig00000849,
O => blk00000003_sig0000084a
);
blk00000003_blk0000055d : XORCY
port map (
CI => blk00000003_sig00000845,
LI => blk00000003_sig00000846,
O => blk00000003_sig00000847
);
blk00000003_blk0000055c : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig0000083f,
Q => blk00000003_sig00000844
);
blk00000003_blk0000055b : MUXCY
port map (
CI => blk00000003_sig00000840,
DI => blk00000003_sig00000843,
S => blk00000003_sig00000841,
O => blk00000003_sig00000824
);
blk00000003_blk0000055a : XORCY
port map (
CI => blk00000003_sig00000840,
LI => blk00000003_sig00000841,
O => blk00000003_sig00000842
);
blk00000003_blk00000559 : MUXCY
port map (
CI => blk00000003_sig000007df,
DI => blk00000003_sig0000083e,
S => blk00000003_sig000007e0,
O => blk00000003_sig0000083f
);
blk00000003_blk00000558 : MUXCY
port map (
CI => blk00000003_sig00000824,
DI => blk00000003_sig0000083d,
S => blk00000003_sig00000825,
O => blk00000003_sig00000821
);
blk00000003_blk00000557 : MUXCY
port map (
CI => blk00000003_sig00000821,
DI => blk00000003_sig0000083c,
S => blk00000003_sig00000822,
O => blk00000003_sig0000081e
);
blk00000003_blk00000556 : MUXCY
port map (
CI => blk00000003_sig0000081e,
DI => blk00000003_sig0000083b,
S => blk00000003_sig0000081f,
O => blk00000003_sig0000081b
);
blk00000003_blk00000555 : MUXCY
port map (
CI => blk00000003_sig0000081b,
DI => blk00000003_sig0000083a,
S => blk00000003_sig0000081c,
O => blk00000003_sig00000818
);
blk00000003_blk00000554 : MUXCY
port map (
CI => blk00000003_sig00000818,
DI => blk00000003_sig00000839,
S => blk00000003_sig00000819,
O => blk00000003_sig00000815
);
blk00000003_blk00000553 : MUXCY
port map (
CI => blk00000003_sig00000815,
DI => blk00000003_sig00000838,
S => blk00000003_sig00000816,
O => blk00000003_sig00000812
);
blk00000003_blk00000552 : MUXCY
port map (
CI => blk00000003_sig00000812,
DI => blk00000003_sig00000837,
S => blk00000003_sig00000813,
O => blk00000003_sig0000080f
);
blk00000003_blk00000551 : MUXCY
port map (
CI => blk00000003_sig0000080f,
DI => blk00000003_sig00000836,
S => blk00000003_sig00000810,
O => blk00000003_sig0000080c
);
blk00000003_blk00000550 : MUXCY
port map (
CI => blk00000003_sig0000080c,
DI => blk00000003_sig00000835,
S => blk00000003_sig0000080d,
O => blk00000003_sig00000809
);
blk00000003_blk0000054f : MUXCY
port map (
CI => blk00000003_sig00000809,
DI => blk00000003_sig00000834,
S => blk00000003_sig0000080a,
O => blk00000003_sig00000806
);
blk00000003_blk0000054e : MUXCY
port map (
CI => blk00000003_sig00000806,
DI => blk00000003_sig00000833,
S => blk00000003_sig00000807,
O => blk00000003_sig00000803
);
blk00000003_blk0000054d : MUXCY
port map (
CI => blk00000003_sig00000803,
DI => blk00000003_sig00000832,
S => blk00000003_sig00000804,
O => blk00000003_sig00000800
);
blk00000003_blk0000054c : MUXCY
port map (
CI => blk00000003_sig00000800,
DI => blk00000003_sig00000831,
S => blk00000003_sig00000801,
O => blk00000003_sig000007fd
);
blk00000003_blk0000054b : MUXCY
port map (
CI => blk00000003_sig000007fd,
DI => blk00000003_sig00000830,
S => blk00000003_sig000007fe,
O => blk00000003_sig000007fa
);
blk00000003_blk0000054a : MUXCY
port map (
CI => blk00000003_sig000007fa,
DI => blk00000003_sig0000082f,
S => blk00000003_sig000007fb,
O => blk00000003_sig000007f7
);
blk00000003_blk00000549 : MUXCY
port map (
CI => blk00000003_sig000007f7,
DI => blk00000003_sig0000082e,
S => blk00000003_sig000007f8,
O => blk00000003_sig000007f4
);
blk00000003_blk00000548 : MUXCY
port map (
CI => blk00000003_sig000007f4,
DI => blk00000003_sig0000082d,
S => blk00000003_sig000007f5,
O => blk00000003_sig000007f1
);
blk00000003_blk00000547 : MUXCY
port map (
CI => blk00000003_sig000007f1,
DI => blk00000003_sig0000082c,
S => blk00000003_sig000007f2,
O => blk00000003_sig000007ee
);
blk00000003_blk00000546 : MUXCY
port map (
CI => blk00000003_sig000007ee,
DI => blk00000003_sig0000082b,
S => blk00000003_sig000007ef,
O => blk00000003_sig000007eb
);
blk00000003_blk00000545 : MUXCY
port map (
CI => blk00000003_sig000007eb,
DI => blk00000003_sig0000082a,
S => blk00000003_sig000007ec,
O => blk00000003_sig000007e8
);
blk00000003_blk00000544 : MUXCY
port map (
CI => blk00000003_sig000007e8,
DI => blk00000003_sig00000829,
S => blk00000003_sig000007e9,
O => blk00000003_sig000007e5
);
blk00000003_blk00000543 : MUXCY
port map (
CI => blk00000003_sig000007e5,
DI => blk00000003_sig00000828,
S => blk00000003_sig000007e6,
O => blk00000003_sig000007e2
);
blk00000003_blk00000542 : MUXCY
port map (
CI => blk00000003_sig000007e2,
DI => blk00000003_sig00000827,
S => blk00000003_sig000007e3,
O => blk00000003_sig000007df
);
blk00000003_blk00000541 : XORCY
port map (
CI => blk00000003_sig00000824,
LI => blk00000003_sig00000825,
O => blk00000003_sig00000826
);
blk00000003_blk00000540 : XORCY
port map (
CI => blk00000003_sig00000821,
LI => blk00000003_sig00000822,
O => blk00000003_sig00000823
);
blk00000003_blk0000053f : XORCY
port map (
CI => blk00000003_sig0000081e,
LI => blk00000003_sig0000081f,
O => blk00000003_sig00000820
);
blk00000003_blk0000053e : XORCY
port map (
CI => blk00000003_sig0000081b,
LI => blk00000003_sig0000081c,
O => blk00000003_sig0000081d
);
blk00000003_blk0000053d : XORCY
port map (
CI => blk00000003_sig00000818,
LI => blk00000003_sig00000819,
O => blk00000003_sig0000081a
);
blk00000003_blk0000053c : XORCY
port map (
CI => blk00000003_sig00000815,
LI => blk00000003_sig00000816,
O => blk00000003_sig00000817
);
blk00000003_blk0000053b : XORCY
port map (
CI => blk00000003_sig00000812,
LI => blk00000003_sig00000813,
O => blk00000003_sig00000814
);
blk00000003_blk0000053a : XORCY
port map (
CI => blk00000003_sig0000080f,
LI => blk00000003_sig00000810,
O => blk00000003_sig00000811
);
blk00000003_blk00000539 : XORCY
port map (
CI => blk00000003_sig0000080c,
LI => blk00000003_sig0000080d,
O => blk00000003_sig0000080e
);
blk00000003_blk00000538 : XORCY
port map (
CI => blk00000003_sig00000809,
LI => blk00000003_sig0000080a,
O => blk00000003_sig0000080b
);
blk00000003_blk00000537 : XORCY
port map (
CI => blk00000003_sig00000806,
LI => blk00000003_sig00000807,
O => blk00000003_sig00000808
);
blk00000003_blk00000536 : XORCY
port map (
CI => blk00000003_sig00000803,
LI => blk00000003_sig00000804,
O => blk00000003_sig00000805
);
blk00000003_blk00000535 : XORCY
port map (
CI => blk00000003_sig00000800,
LI => blk00000003_sig00000801,
O => blk00000003_sig00000802
);
blk00000003_blk00000534 : XORCY
port map (
CI => blk00000003_sig000007fd,
LI => blk00000003_sig000007fe,
O => blk00000003_sig000007ff
);
blk00000003_blk00000533 : XORCY
port map (
CI => blk00000003_sig000007fa,
LI => blk00000003_sig000007fb,
O => blk00000003_sig000007fc
);
blk00000003_blk00000532 : XORCY
port map (
CI => blk00000003_sig000007f7,
LI => blk00000003_sig000007f8,
O => blk00000003_sig000007f9
);
blk00000003_blk00000531 : XORCY
port map (
CI => blk00000003_sig000007f4,
LI => blk00000003_sig000007f5,
O => blk00000003_sig000007f6
);
blk00000003_blk00000530 : XORCY
port map (
CI => blk00000003_sig000007f1,
LI => blk00000003_sig000007f2,
O => blk00000003_sig000007f3
);
blk00000003_blk0000052f : XORCY
port map (
CI => blk00000003_sig000007ee,
LI => blk00000003_sig000007ef,
O => blk00000003_sig000007f0
);
blk00000003_blk0000052e : XORCY
port map (
CI => blk00000003_sig000007eb,
LI => blk00000003_sig000007ec,
O => blk00000003_sig000007ed
);
blk00000003_blk0000052d : XORCY
port map (
CI => blk00000003_sig000007e8,
LI => blk00000003_sig000007e9,
O => blk00000003_sig000007ea
);
blk00000003_blk0000052c : XORCY
port map (
CI => blk00000003_sig000007e5,
LI => blk00000003_sig000007e6,
O => blk00000003_sig000007e7
);
blk00000003_blk0000052b : XORCY
port map (
CI => blk00000003_sig000007e2,
LI => blk00000003_sig000007e3,
O => blk00000003_sig000007e4
);
blk00000003_blk0000052a : XORCY
port map (
CI => blk00000003_sig000007df,
LI => blk00000003_sig000007e0,
O => blk00000003_sig000007e1
);
blk00000003_blk00000529 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig000007d9,
Q => blk00000003_sig000007de
);
blk00000003_blk00000528 : MUXCY
port map (
CI => blk00000003_sig000007da,
DI => blk00000003_sig000007dd,
S => blk00000003_sig000007db,
O => blk00000003_sig000007be
);
blk00000003_blk00000527 : XORCY
port map (
CI => blk00000003_sig000007da,
LI => blk00000003_sig000007db,
O => blk00000003_sig000007dc
);
blk00000003_blk00000526 : MUXCY
port map (
CI => blk00000003_sig00000779,
DI => blk00000003_sig000007d8,
S => blk00000003_sig0000077a,
O => blk00000003_sig000007d9
);
blk00000003_blk00000525 : MUXCY
port map (
CI => blk00000003_sig000007be,
DI => blk00000003_sig000007d7,
S => blk00000003_sig000007bf,
O => blk00000003_sig000007bb
);
blk00000003_blk00000524 : MUXCY
port map (
CI => blk00000003_sig000007bb,
DI => blk00000003_sig000007d6,
S => blk00000003_sig000007bc,
O => blk00000003_sig000007b8
);
blk00000003_blk00000523 : MUXCY
port map (
CI => blk00000003_sig000007b8,
DI => blk00000003_sig000007d5,
S => blk00000003_sig000007b9,
O => blk00000003_sig000007b5
);
blk00000003_blk00000522 : MUXCY
port map (
CI => blk00000003_sig000007b5,
DI => blk00000003_sig000007d4,
S => blk00000003_sig000007b6,
O => blk00000003_sig000007b2
);
blk00000003_blk00000521 : MUXCY
port map (
CI => blk00000003_sig000007b2,
DI => blk00000003_sig000007d3,
S => blk00000003_sig000007b3,
O => blk00000003_sig000007af
);
blk00000003_blk00000520 : MUXCY
port map (
CI => blk00000003_sig000007af,
DI => blk00000003_sig000007d2,
S => blk00000003_sig000007b0,
O => blk00000003_sig000007ac
);
blk00000003_blk0000051f : MUXCY
port map (
CI => blk00000003_sig000007ac,
DI => blk00000003_sig000007d1,
S => blk00000003_sig000007ad,
O => blk00000003_sig000007a9
);
blk00000003_blk0000051e : MUXCY
port map (
CI => blk00000003_sig000007a9,
DI => blk00000003_sig000007d0,
S => blk00000003_sig000007aa,
O => blk00000003_sig000007a6
);
blk00000003_blk0000051d : MUXCY
port map (
CI => blk00000003_sig000007a6,
DI => blk00000003_sig000007cf,
S => blk00000003_sig000007a7,
O => blk00000003_sig000007a3
);
blk00000003_blk0000051c : MUXCY
port map (
CI => blk00000003_sig000007a3,
DI => blk00000003_sig000007ce,
S => blk00000003_sig000007a4,
O => blk00000003_sig000007a0
);
blk00000003_blk0000051b : MUXCY
port map (
CI => blk00000003_sig000007a0,
DI => blk00000003_sig000007cd,
S => blk00000003_sig000007a1,
O => blk00000003_sig0000079d
);
blk00000003_blk0000051a : MUXCY
port map (
CI => blk00000003_sig0000079d,
DI => blk00000003_sig000007cc,
S => blk00000003_sig0000079e,
O => blk00000003_sig0000079a
);
blk00000003_blk00000519 : MUXCY
port map (
CI => blk00000003_sig0000079a,
DI => blk00000003_sig000007cb,
S => blk00000003_sig0000079b,
O => blk00000003_sig00000797
);
blk00000003_blk00000518 : MUXCY
port map (
CI => blk00000003_sig00000797,
DI => blk00000003_sig000007ca,
S => blk00000003_sig00000798,
O => blk00000003_sig00000794
);
blk00000003_blk00000517 : MUXCY
port map (
CI => blk00000003_sig00000794,
DI => blk00000003_sig000007c9,
S => blk00000003_sig00000795,
O => blk00000003_sig00000791
);
blk00000003_blk00000516 : MUXCY
port map (
CI => blk00000003_sig00000791,
DI => blk00000003_sig000007c8,
S => blk00000003_sig00000792,
O => blk00000003_sig0000078e
);
blk00000003_blk00000515 : MUXCY
port map (
CI => blk00000003_sig0000078e,
DI => blk00000003_sig000007c7,
S => blk00000003_sig0000078f,
O => blk00000003_sig0000078b
);
blk00000003_blk00000514 : MUXCY
port map (
CI => blk00000003_sig0000078b,
DI => blk00000003_sig000007c6,
S => blk00000003_sig0000078c,
O => blk00000003_sig00000788
);
blk00000003_blk00000513 : MUXCY
port map (
CI => blk00000003_sig00000788,
DI => blk00000003_sig000007c5,
S => blk00000003_sig00000789,
O => blk00000003_sig00000785
);
blk00000003_blk00000512 : MUXCY
port map (
CI => blk00000003_sig00000785,
DI => blk00000003_sig000007c4,
S => blk00000003_sig00000786,
O => blk00000003_sig00000782
);
blk00000003_blk00000511 : MUXCY
port map (
CI => blk00000003_sig00000782,
DI => blk00000003_sig000007c3,
S => blk00000003_sig00000783,
O => blk00000003_sig0000077f
);
blk00000003_blk00000510 : MUXCY
port map (
CI => blk00000003_sig0000077f,
DI => blk00000003_sig000007c2,
S => blk00000003_sig00000780,
O => blk00000003_sig0000077c
);
blk00000003_blk0000050f : MUXCY
port map (
CI => blk00000003_sig0000077c,
DI => blk00000003_sig000007c1,
S => blk00000003_sig0000077d,
O => blk00000003_sig00000779
);
blk00000003_blk0000050e : XORCY
port map (
CI => blk00000003_sig000007be,
LI => blk00000003_sig000007bf,
O => blk00000003_sig000007c0
);
blk00000003_blk0000050d : XORCY
port map (
CI => blk00000003_sig000007bb,
LI => blk00000003_sig000007bc,
O => blk00000003_sig000007bd
);
blk00000003_blk0000050c : XORCY
port map (
CI => blk00000003_sig000007b8,
LI => blk00000003_sig000007b9,
O => blk00000003_sig000007ba
);
blk00000003_blk0000050b : XORCY
port map (
CI => blk00000003_sig000007b5,
LI => blk00000003_sig000007b6,
O => blk00000003_sig000007b7
);
blk00000003_blk0000050a : XORCY
port map (
CI => blk00000003_sig000007b2,
LI => blk00000003_sig000007b3,
O => blk00000003_sig000007b4
);
blk00000003_blk00000509 : XORCY
port map (
CI => blk00000003_sig000007af,
LI => blk00000003_sig000007b0,
O => blk00000003_sig000007b1
);
blk00000003_blk00000508 : XORCY
port map (
CI => blk00000003_sig000007ac,
LI => blk00000003_sig000007ad,
O => blk00000003_sig000007ae
);
blk00000003_blk00000507 : XORCY
port map (
CI => blk00000003_sig000007a9,
LI => blk00000003_sig000007aa,
O => blk00000003_sig000007ab
);
blk00000003_blk00000506 : XORCY
port map (
CI => blk00000003_sig000007a6,
LI => blk00000003_sig000007a7,
O => blk00000003_sig000007a8
);
blk00000003_blk00000505 : XORCY
port map (
CI => blk00000003_sig000007a3,
LI => blk00000003_sig000007a4,
O => blk00000003_sig000007a5
);
blk00000003_blk00000504 : XORCY
port map (
CI => blk00000003_sig000007a0,
LI => blk00000003_sig000007a1,
O => blk00000003_sig000007a2
);
blk00000003_blk00000503 : XORCY
port map (
CI => blk00000003_sig0000079d,
LI => blk00000003_sig0000079e,
O => blk00000003_sig0000079f
);
blk00000003_blk00000502 : XORCY
port map (
CI => blk00000003_sig0000079a,
LI => blk00000003_sig0000079b,
O => blk00000003_sig0000079c
);
blk00000003_blk00000501 : XORCY
port map (
CI => blk00000003_sig00000797,
LI => blk00000003_sig00000798,
O => blk00000003_sig00000799
);
blk00000003_blk00000500 : XORCY
port map (
CI => blk00000003_sig00000794,
LI => blk00000003_sig00000795,
O => blk00000003_sig00000796
);
blk00000003_blk000004ff : XORCY
port map (
CI => blk00000003_sig00000791,
LI => blk00000003_sig00000792,
O => blk00000003_sig00000793
);
blk00000003_blk000004fe : XORCY
port map (
CI => blk00000003_sig0000078e,
LI => blk00000003_sig0000078f,
O => blk00000003_sig00000790
);
blk00000003_blk000004fd : XORCY
port map (
CI => blk00000003_sig0000078b,
LI => blk00000003_sig0000078c,
O => blk00000003_sig0000078d
);
blk00000003_blk000004fc : XORCY
port map (
CI => blk00000003_sig00000788,
LI => blk00000003_sig00000789,
O => blk00000003_sig0000078a
);
blk00000003_blk000004fb : XORCY
port map (
CI => blk00000003_sig00000785,
LI => blk00000003_sig00000786,
O => blk00000003_sig00000787
);
blk00000003_blk000004fa : XORCY
port map (
CI => blk00000003_sig00000782,
LI => blk00000003_sig00000783,
O => blk00000003_sig00000784
);
blk00000003_blk000004f9 : XORCY
port map (
CI => blk00000003_sig0000077f,
LI => blk00000003_sig00000780,
O => blk00000003_sig00000781
);
blk00000003_blk000004f8 : XORCY
port map (
CI => blk00000003_sig0000077c,
LI => blk00000003_sig0000077d,
O => blk00000003_sig0000077e
);
blk00000003_blk000004f7 : XORCY
port map (
CI => blk00000003_sig00000779,
LI => blk00000003_sig0000077a,
O => blk00000003_sig0000077b
);
blk00000003_blk000004f6 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000773,
Q => blk00000003_sig00000778
);
blk00000003_blk000004f5 : MUXCY
port map (
CI => blk00000003_sig00000774,
DI => blk00000003_sig00000777,
S => blk00000003_sig00000775,
O => blk00000003_sig00000758
);
blk00000003_blk000004f4 : XORCY
port map (
CI => blk00000003_sig00000774,
LI => blk00000003_sig00000775,
O => blk00000003_sig00000776
);
blk00000003_blk000004f3 : MUXCY
port map (
CI => blk00000003_sig00000713,
DI => blk00000003_sig00000772,
S => blk00000003_sig00000714,
O => blk00000003_sig00000773
);
blk00000003_blk000004f2 : MUXCY
port map (
CI => blk00000003_sig00000758,
DI => blk00000003_sig00000771,
S => blk00000003_sig00000759,
O => blk00000003_sig00000755
);
blk00000003_blk000004f1 : MUXCY
port map (
CI => blk00000003_sig00000755,
DI => blk00000003_sig00000770,
S => blk00000003_sig00000756,
O => blk00000003_sig00000752
);
blk00000003_blk000004f0 : MUXCY
port map (
CI => blk00000003_sig00000752,
DI => blk00000003_sig0000076f,
S => blk00000003_sig00000753,
O => blk00000003_sig0000074f
);
blk00000003_blk000004ef : MUXCY
port map (
CI => blk00000003_sig0000074f,
DI => blk00000003_sig0000076e,
S => blk00000003_sig00000750,
O => blk00000003_sig0000074c
);
blk00000003_blk000004ee : MUXCY
port map (
CI => blk00000003_sig0000074c,
DI => blk00000003_sig0000076d,
S => blk00000003_sig0000074d,
O => blk00000003_sig00000749
);
blk00000003_blk000004ed : MUXCY
port map (
CI => blk00000003_sig00000749,
DI => blk00000003_sig0000076c,
S => blk00000003_sig0000074a,
O => blk00000003_sig00000746
);
blk00000003_blk000004ec : MUXCY
port map (
CI => blk00000003_sig00000746,
DI => blk00000003_sig0000076b,
S => blk00000003_sig00000747,
O => blk00000003_sig00000743
);
blk00000003_blk000004eb : MUXCY
port map (
CI => blk00000003_sig00000743,
DI => blk00000003_sig0000076a,
S => blk00000003_sig00000744,
O => blk00000003_sig00000740
);
blk00000003_blk000004ea : MUXCY
port map (
CI => blk00000003_sig00000740,
DI => blk00000003_sig00000769,
S => blk00000003_sig00000741,
O => blk00000003_sig0000073d
);
blk00000003_blk000004e9 : MUXCY
port map (
CI => blk00000003_sig0000073d,
DI => blk00000003_sig00000768,
S => blk00000003_sig0000073e,
O => blk00000003_sig0000073a
);
blk00000003_blk000004e8 : MUXCY
port map (
CI => blk00000003_sig0000073a,
DI => blk00000003_sig00000767,
S => blk00000003_sig0000073b,
O => blk00000003_sig00000737
);
blk00000003_blk000004e7 : MUXCY
port map (
CI => blk00000003_sig00000737,
DI => blk00000003_sig00000766,
S => blk00000003_sig00000738,
O => blk00000003_sig00000734
);
blk00000003_blk000004e6 : MUXCY
port map (
CI => blk00000003_sig00000734,
DI => blk00000003_sig00000765,
S => blk00000003_sig00000735,
O => blk00000003_sig00000731
);
blk00000003_blk000004e5 : MUXCY
port map (
CI => blk00000003_sig00000731,
DI => blk00000003_sig00000764,
S => blk00000003_sig00000732,
O => blk00000003_sig0000072e
);
blk00000003_blk000004e4 : MUXCY
port map (
CI => blk00000003_sig0000072e,
DI => blk00000003_sig00000763,
S => blk00000003_sig0000072f,
O => blk00000003_sig0000072b
);
blk00000003_blk000004e3 : MUXCY
port map (
CI => blk00000003_sig0000072b,
DI => blk00000003_sig00000762,
S => blk00000003_sig0000072c,
O => blk00000003_sig00000728
);
blk00000003_blk000004e2 : MUXCY
port map (
CI => blk00000003_sig00000728,
DI => blk00000003_sig00000761,
S => blk00000003_sig00000729,
O => blk00000003_sig00000725
);
blk00000003_blk000004e1 : MUXCY
port map (
CI => blk00000003_sig00000725,
DI => blk00000003_sig00000760,
S => blk00000003_sig00000726,
O => blk00000003_sig00000722
);
blk00000003_blk000004e0 : MUXCY
port map (
CI => blk00000003_sig00000722,
DI => blk00000003_sig0000075f,
S => blk00000003_sig00000723,
O => blk00000003_sig0000071f
);
blk00000003_blk000004df : MUXCY
port map (
CI => blk00000003_sig0000071f,
DI => blk00000003_sig0000075e,
S => blk00000003_sig00000720,
O => blk00000003_sig0000071c
);
blk00000003_blk000004de : MUXCY
port map (
CI => blk00000003_sig0000071c,
DI => blk00000003_sig0000075d,
S => blk00000003_sig0000071d,
O => blk00000003_sig00000719
);
blk00000003_blk000004dd : MUXCY
port map (
CI => blk00000003_sig00000719,
DI => blk00000003_sig0000075c,
S => blk00000003_sig0000071a,
O => blk00000003_sig00000716
);
blk00000003_blk000004dc : MUXCY
port map (
CI => blk00000003_sig00000716,
DI => blk00000003_sig0000075b,
S => blk00000003_sig00000717,
O => blk00000003_sig00000713
);
blk00000003_blk000004db : XORCY
port map (
CI => blk00000003_sig00000758,
LI => blk00000003_sig00000759,
O => blk00000003_sig0000075a
);
blk00000003_blk000004da : XORCY
port map (
CI => blk00000003_sig00000755,
LI => blk00000003_sig00000756,
O => blk00000003_sig00000757
);
blk00000003_blk000004d9 : XORCY
port map (
CI => blk00000003_sig00000752,
LI => blk00000003_sig00000753,
O => blk00000003_sig00000754
);
blk00000003_blk000004d8 : XORCY
port map (
CI => blk00000003_sig0000074f,
LI => blk00000003_sig00000750,
O => blk00000003_sig00000751
);
blk00000003_blk000004d7 : XORCY
port map (
CI => blk00000003_sig0000074c,
LI => blk00000003_sig0000074d,
O => blk00000003_sig0000074e
);
blk00000003_blk000004d6 : XORCY
port map (
CI => blk00000003_sig00000749,
LI => blk00000003_sig0000074a,
O => blk00000003_sig0000074b
);
blk00000003_blk000004d5 : XORCY
port map (
CI => blk00000003_sig00000746,
LI => blk00000003_sig00000747,
O => blk00000003_sig00000748
);
blk00000003_blk000004d4 : XORCY
port map (
CI => blk00000003_sig00000743,
LI => blk00000003_sig00000744,
O => blk00000003_sig00000745
);
blk00000003_blk000004d3 : XORCY
port map (
CI => blk00000003_sig00000740,
LI => blk00000003_sig00000741,
O => blk00000003_sig00000742
);
blk00000003_blk000004d2 : XORCY
port map (
CI => blk00000003_sig0000073d,
LI => blk00000003_sig0000073e,
O => blk00000003_sig0000073f
);
blk00000003_blk000004d1 : XORCY
port map (
CI => blk00000003_sig0000073a,
LI => blk00000003_sig0000073b,
O => blk00000003_sig0000073c
);
blk00000003_blk000004d0 : XORCY
port map (
CI => blk00000003_sig00000737,
LI => blk00000003_sig00000738,
O => blk00000003_sig00000739
);
blk00000003_blk000004cf : XORCY
port map (
CI => blk00000003_sig00000734,
LI => blk00000003_sig00000735,
O => blk00000003_sig00000736
);
blk00000003_blk000004ce : XORCY
port map (
CI => blk00000003_sig00000731,
LI => blk00000003_sig00000732,
O => blk00000003_sig00000733
);
blk00000003_blk000004cd : XORCY
port map (
CI => blk00000003_sig0000072e,
LI => blk00000003_sig0000072f,
O => blk00000003_sig00000730
);
blk00000003_blk000004cc : XORCY
port map (
CI => blk00000003_sig0000072b,
LI => blk00000003_sig0000072c,
O => blk00000003_sig0000072d
);
blk00000003_blk000004cb : XORCY
port map (
CI => blk00000003_sig00000728,
LI => blk00000003_sig00000729,
O => blk00000003_sig0000072a
);
blk00000003_blk000004ca : XORCY
port map (
CI => blk00000003_sig00000725,
LI => blk00000003_sig00000726,
O => blk00000003_sig00000727
);
blk00000003_blk000004c9 : XORCY
port map (
CI => blk00000003_sig00000722,
LI => blk00000003_sig00000723,
O => blk00000003_sig00000724
);
blk00000003_blk000004c8 : XORCY
port map (
CI => blk00000003_sig0000071f,
LI => blk00000003_sig00000720,
O => blk00000003_sig00000721
);
blk00000003_blk000004c7 : XORCY
port map (
CI => blk00000003_sig0000071c,
LI => blk00000003_sig0000071d,
O => blk00000003_sig0000071e
);
blk00000003_blk000004c6 : XORCY
port map (
CI => blk00000003_sig00000719,
LI => blk00000003_sig0000071a,
O => blk00000003_sig0000071b
);
blk00000003_blk000004c5 : XORCY
port map (
CI => blk00000003_sig00000716,
LI => blk00000003_sig00000717,
O => blk00000003_sig00000718
);
blk00000003_blk000004c4 : XORCY
port map (
CI => blk00000003_sig00000713,
LI => blk00000003_sig00000714,
O => blk00000003_sig00000715
);
blk00000003_blk000004c3 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig0000070d,
Q => blk00000003_sig00000712
);
blk00000003_blk000004c2 : MUXCY
port map (
CI => blk00000003_sig0000070e,
DI => blk00000003_sig00000711,
S => blk00000003_sig0000070f,
O => blk00000003_sig000006f2
);
blk00000003_blk000004c1 : XORCY
port map (
CI => blk00000003_sig0000070e,
LI => blk00000003_sig0000070f,
O => blk00000003_sig00000710
);
blk00000003_blk000004c0 : MUXCY
port map (
CI => blk00000003_sig000006ad,
DI => blk00000003_sig0000070c,
S => blk00000003_sig000006ae,
O => blk00000003_sig0000070d
);
blk00000003_blk000004bf : MUXCY
port map (
CI => blk00000003_sig000006f2,
DI => blk00000003_sig0000070b,
S => blk00000003_sig000006f3,
O => blk00000003_sig000006ef
);
blk00000003_blk000004be : MUXCY
port map (
CI => blk00000003_sig000006ef,
DI => blk00000003_sig0000070a,
S => blk00000003_sig000006f0,
O => blk00000003_sig000006ec
);
blk00000003_blk000004bd : MUXCY
port map (
CI => blk00000003_sig000006ec,
DI => blk00000003_sig00000709,
S => blk00000003_sig000006ed,
O => blk00000003_sig000006e9
);
blk00000003_blk000004bc : MUXCY
port map (
CI => blk00000003_sig000006e9,
DI => blk00000003_sig00000708,
S => blk00000003_sig000006ea,
O => blk00000003_sig000006e6
);
blk00000003_blk000004bb : MUXCY
port map (
CI => blk00000003_sig000006e6,
DI => blk00000003_sig00000707,
S => blk00000003_sig000006e7,
O => blk00000003_sig000006e3
);
blk00000003_blk000004ba : MUXCY
port map (
CI => blk00000003_sig000006e3,
DI => blk00000003_sig00000706,
S => blk00000003_sig000006e4,
O => blk00000003_sig000006e0
);
blk00000003_blk000004b9 : MUXCY
port map (
CI => blk00000003_sig000006e0,
DI => blk00000003_sig00000705,
S => blk00000003_sig000006e1,
O => blk00000003_sig000006dd
);
blk00000003_blk000004b8 : MUXCY
port map (
CI => blk00000003_sig000006dd,
DI => blk00000003_sig00000704,
S => blk00000003_sig000006de,
O => blk00000003_sig000006da
);
blk00000003_blk000004b7 : MUXCY
port map (
CI => blk00000003_sig000006da,
DI => blk00000003_sig00000703,
S => blk00000003_sig000006db,
O => blk00000003_sig000006d7
);
blk00000003_blk000004b6 : MUXCY
port map (
CI => blk00000003_sig000006d7,
DI => blk00000003_sig00000702,
S => blk00000003_sig000006d8,
O => blk00000003_sig000006d4
);
blk00000003_blk000004b5 : MUXCY
port map (
CI => blk00000003_sig000006d4,
DI => blk00000003_sig00000701,
S => blk00000003_sig000006d5,
O => blk00000003_sig000006d1
);
blk00000003_blk000004b4 : MUXCY
port map (
CI => blk00000003_sig000006d1,
DI => blk00000003_sig00000700,
S => blk00000003_sig000006d2,
O => blk00000003_sig000006ce
);
blk00000003_blk000004b3 : MUXCY
port map (
CI => blk00000003_sig000006ce,
DI => blk00000003_sig000006ff,
S => blk00000003_sig000006cf,
O => blk00000003_sig000006cb
);
blk00000003_blk000004b2 : MUXCY
port map (
CI => blk00000003_sig000006cb,
DI => blk00000003_sig000006fe,
S => blk00000003_sig000006cc,
O => blk00000003_sig000006c8
);
blk00000003_blk000004b1 : MUXCY
port map (
CI => blk00000003_sig000006c8,
DI => blk00000003_sig000006fd,
S => blk00000003_sig000006c9,
O => blk00000003_sig000006c5
);
blk00000003_blk000004b0 : MUXCY
port map (
CI => blk00000003_sig000006c5,
DI => blk00000003_sig000006fc,
S => blk00000003_sig000006c6,
O => blk00000003_sig000006c2
);
blk00000003_blk000004af : MUXCY
port map (
CI => blk00000003_sig000006c2,
DI => blk00000003_sig000006fb,
S => blk00000003_sig000006c3,
O => blk00000003_sig000006bf
);
blk00000003_blk000004ae : MUXCY
port map (
CI => blk00000003_sig000006bf,
DI => blk00000003_sig000006fa,
S => blk00000003_sig000006c0,
O => blk00000003_sig000006bc
);
blk00000003_blk000004ad : MUXCY
port map (
CI => blk00000003_sig000006bc,
DI => blk00000003_sig000006f9,
S => blk00000003_sig000006bd,
O => blk00000003_sig000006b9
);
blk00000003_blk000004ac : MUXCY
port map (
CI => blk00000003_sig000006b9,
DI => blk00000003_sig000006f8,
S => blk00000003_sig000006ba,
O => blk00000003_sig000006b6
);
blk00000003_blk000004ab : MUXCY
port map (
CI => blk00000003_sig000006b6,
DI => blk00000003_sig000006f7,
S => blk00000003_sig000006b7,
O => blk00000003_sig000006b3
);
blk00000003_blk000004aa : MUXCY
port map (
CI => blk00000003_sig000006b3,
DI => blk00000003_sig000006f6,
S => blk00000003_sig000006b4,
O => blk00000003_sig000006b0
);
blk00000003_blk000004a9 : MUXCY
port map (
CI => blk00000003_sig000006b0,
DI => blk00000003_sig000006f5,
S => blk00000003_sig000006b1,
O => blk00000003_sig000006ad
);
blk00000003_blk000004a8 : XORCY
port map (
CI => blk00000003_sig000006f2,
LI => blk00000003_sig000006f3,
O => blk00000003_sig000006f4
);
blk00000003_blk000004a7 : XORCY
port map (
CI => blk00000003_sig000006ef,
LI => blk00000003_sig000006f0,
O => blk00000003_sig000006f1
);
blk00000003_blk000004a6 : XORCY
port map (
CI => blk00000003_sig000006ec,
LI => blk00000003_sig000006ed,
O => blk00000003_sig000006ee
);
blk00000003_blk000004a5 : XORCY
port map (
CI => blk00000003_sig000006e9,
LI => blk00000003_sig000006ea,
O => blk00000003_sig000006eb
);
blk00000003_blk000004a4 : XORCY
port map (
CI => blk00000003_sig000006e6,
LI => blk00000003_sig000006e7,
O => blk00000003_sig000006e8
);
blk00000003_blk000004a3 : XORCY
port map (
CI => blk00000003_sig000006e3,
LI => blk00000003_sig000006e4,
O => blk00000003_sig000006e5
);
blk00000003_blk000004a2 : XORCY
port map (
CI => blk00000003_sig000006e0,
LI => blk00000003_sig000006e1,
O => blk00000003_sig000006e2
);
blk00000003_blk000004a1 : XORCY
port map (
CI => blk00000003_sig000006dd,
LI => blk00000003_sig000006de,
O => blk00000003_sig000006df
);
blk00000003_blk000004a0 : XORCY
port map (
CI => blk00000003_sig000006da,
LI => blk00000003_sig000006db,
O => blk00000003_sig000006dc
);
blk00000003_blk0000049f : XORCY
port map (
CI => blk00000003_sig000006d7,
LI => blk00000003_sig000006d8,
O => blk00000003_sig000006d9
);
blk00000003_blk0000049e : XORCY
port map (
CI => blk00000003_sig000006d4,
LI => blk00000003_sig000006d5,
O => blk00000003_sig000006d6
);
blk00000003_blk0000049d : XORCY
port map (
CI => blk00000003_sig000006d1,
LI => blk00000003_sig000006d2,
O => blk00000003_sig000006d3
);
blk00000003_blk0000049c : XORCY
port map (
CI => blk00000003_sig000006ce,
LI => blk00000003_sig000006cf,
O => blk00000003_sig000006d0
);
blk00000003_blk0000049b : XORCY
port map (
CI => blk00000003_sig000006cb,
LI => blk00000003_sig000006cc,
O => blk00000003_sig000006cd
);
blk00000003_blk0000049a : XORCY
port map (
CI => blk00000003_sig000006c8,
LI => blk00000003_sig000006c9,
O => blk00000003_sig000006ca
);
blk00000003_blk00000499 : XORCY
port map (
CI => blk00000003_sig000006c5,
LI => blk00000003_sig000006c6,
O => blk00000003_sig000006c7
);
blk00000003_blk00000498 : XORCY
port map (
CI => blk00000003_sig000006c2,
LI => blk00000003_sig000006c3,
O => blk00000003_sig000006c4
);
blk00000003_blk00000497 : XORCY
port map (
CI => blk00000003_sig000006bf,
LI => blk00000003_sig000006c0,
O => blk00000003_sig000006c1
);
blk00000003_blk00000496 : XORCY
port map (
CI => blk00000003_sig000006bc,
LI => blk00000003_sig000006bd,
O => blk00000003_sig000006be
);
blk00000003_blk00000495 : XORCY
port map (
CI => blk00000003_sig000006b9,
LI => blk00000003_sig000006ba,
O => blk00000003_sig000006bb
);
blk00000003_blk00000494 : XORCY
port map (
CI => blk00000003_sig000006b6,
LI => blk00000003_sig000006b7,
O => blk00000003_sig000006b8
);
blk00000003_blk00000493 : XORCY
port map (
CI => blk00000003_sig000006b3,
LI => blk00000003_sig000006b4,
O => blk00000003_sig000006b5
);
blk00000003_blk00000492 : XORCY
port map (
CI => blk00000003_sig000006b0,
LI => blk00000003_sig000006b1,
O => blk00000003_sig000006b2
);
blk00000003_blk00000491 : XORCY
port map (
CI => blk00000003_sig000006ad,
LI => blk00000003_sig000006ae,
O => blk00000003_sig000006af
);
blk00000003_blk00000490 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig000006a7,
Q => blk00000003_sig000006ac
);
blk00000003_blk0000048f : MUXCY
port map (
CI => blk00000003_sig000006a8,
DI => blk00000003_sig000006ab,
S => blk00000003_sig000006a9,
O => blk00000003_sig0000068c
);
blk00000003_blk0000048e : XORCY
port map (
CI => blk00000003_sig000006a8,
LI => blk00000003_sig000006a9,
O => blk00000003_sig000006aa
);
blk00000003_blk0000048d : MUXCY
port map (
CI => blk00000003_sig00000647,
DI => blk00000003_sig000006a6,
S => blk00000003_sig00000648,
O => blk00000003_sig000006a7
);
blk00000003_blk0000048c : MUXCY
port map (
CI => blk00000003_sig0000068c,
DI => blk00000003_sig000006a5,
S => blk00000003_sig0000068d,
O => blk00000003_sig00000689
);
blk00000003_blk0000048b : MUXCY
port map (
CI => blk00000003_sig00000689,
DI => blk00000003_sig000006a4,
S => blk00000003_sig0000068a,
O => blk00000003_sig00000686
);
blk00000003_blk0000048a : MUXCY
port map (
CI => blk00000003_sig00000686,
DI => blk00000003_sig000006a3,
S => blk00000003_sig00000687,
O => blk00000003_sig00000683
);
blk00000003_blk00000489 : MUXCY
port map (
CI => blk00000003_sig00000683,
DI => blk00000003_sig000006a2,
S => blk00000003_sig00000684,
O => blk00000003_sig00000680
);
blk00000003_blk00000488 : MUXCY
port map (
CI => blk00000003_sig00000680,
DI => blk00000003_sig000006a1,
S => blk00000003_sig00000681,
O => blk00000003_sig0000067d
);
blk00000003_blk00000487 : MUXCY
port map (
CI => blk00000003_sig0000067d,
DI => blk00000003_sig000006a0,
S => blk00000003_sig0000067e,
O => blk00000003_sig0000067a
);
blk00000003_blk00000486 : MUXCY
port map (
CI => blk00000003_sig0000067a,
DI => blk00000003_sig0000069f,
S => blk00000003_sig0000067b,
O => blk00000003_sig00000677
);
blk00000003_blk00000485 : MUXCY
port map (
CI => blk00000003_sig00000677,
DI => blk00000003_sig0000069e,
S => blk00000003_sig00000678,
O => blk00000003_sig00000674
);
blk00000003_blk00000484 : MUXCY
port map (
CI => blk00000003_sig00000674,
DI => blk00000003_sig0000069d,
S => blk00000003_sig00000675,
O => blk00000003_sig00000671
);
blk00000003_blk00000483 : MUXCY
port map (
CI => blk00000003_sig00000671,
DI => blk00000003_sig0000069c,
S => blk00000003_sig00000672,
O => blk00000003_sig0000066e
);
blk00000003_blk00000482 : MUXCY
port map (
CI => blk00000003_sig0000066e,
DI => blk00000003_sig0000069b,
S => blk00000003_sig0000066f,
O => blk00000003_sig0000066b
);
blk00000003_blk00000481 : MUXCY
port map (
CI => blk00000003_sig0000066b,
DI => blk00000003_sig0000069a,
S => blk00000003_sig0000066c,
O => blk00000003_sig00000668
);
blk00000003_blk00000480 : MUXCY
port map (
CI => blk00000003_sig00000668,
DI => blk00000003_sig00000699,
S => blk00000003_sig00000669,
O => blk00000003_sig00000665
);
blk00000003_blk0000047f : MUXCY
port map (
CI => blk00000003_sig00000665,
DI => blk00000003_sig00000698,
S => blk00000003_sig00000666,
O => blk00000003_sig00000662
);
blk00000003_blk0000047e : MUXCY
port map (
CI => blk00000003_sig00000662,
DI => blk00000003_sig00000697,
S => blk00000003_sig00000663,
O => blk00000003_sig0000065f
);
blk00000003_blk0000047d : MUXCY
port map (
CI => blk00000003_sig0000065f,
DI => blk00000003_sig00000696,
S => blk00000003_sig00000660,
O => blk00000003_sig0000065c
);
blk00000003_blk0000047c : MUXCY
port map (
CI => blk00000003_sig0000065c,
DI => blk00000003_sig00000695,
S => blk00000003_sig0000065d,
O => blk00000003_sig00000659
);
blk00000003_blk0000047b : MUXCY
port map (
CI => blk00000003_sig00000659,
DI => blk00000003_sig00000694,
S => blk00000003_sig0000065a,
O => blk00000003_sig00000656
);
blk00000003_blk0000047a : MUXCY
port map (
CI => blk00000003_sig00000656,
DI => blk00000003_sig00000693,
S => blk00000003_sig00000657,
O => blk00000003_sig00000653
);
blk00000003_blk00000479 : MUXCY
port map (
CI => blk00000003_sig00000653,
DI => blk00000003_sig00000692,
S => blk00000003_sig00000654,
O => blk00000003_sig00000650
);
blk00000003_blk00000478 : MUXCY
port map (
CI => blk00000003_sig00000650,
DI => blk00000003_sig00000691,
S => blk00000003_sig00000651,
O => blk00000003_sig0000064d
);
blk00000003_blk00000477 : MUXCY
port map (
CI => blk00000003_sig0000064d,
DI => blk00000003_sig00000690,
S => blk00000003_sig0000064e,
O => blk00000003_sig0000064a
);
blk00000003_blk00000476 : MUXCY
port map (
CI => blk00000003_sig0000064a,
DI => blk00000003_sig0000068f,
S => blk00000003_sig0000064b,
O => blk00000003_sig00000647
);
blk00000003_blk00000475 : XORCY
port map (
CI => blk00000003_sig0000068c,
LI => blk00000003_sig0000068d,
O => blk00000003_sig0000068e
);
blk00000003_blk00000474 : XORCY
port map (
CI => blk00000003_sig00000689,
LI => blk00000003_sig0000068a,
O => blk00000003_sig0000068b
);
blk00000003_blk00000473 : XORCY
port map (
CI => blk00000003_sig00000686,
LI => blk00000003_sig00000687,
O => blk00000003_sig00000688
);
blk00000003_blk00000472 : XORCY
port map (
CI => blk00000003_sig00000683,
LI => blk00000003_sig00000684,
O => blk00000003_sig00000685
);
blk00000003_blk00000471 : XORCY
port map (
CI => blk00000003_sig00000680,
LI => blk00000003_sig00000681,
O => blk00000003_sig00000682
);
blk00000003_blk00000470 : XORCY
port map (
CI => blk00000003_sig0000067d,
LI => blk00000003_sig0000067e,
O => blk00000003_sig0000067f
);
blk00000003_blk0000046f : XORCY
port map (
CI => blk00000003_sig0000067a,
LI => blk00000003_sig0000067b,
O => blk00000003_sig0000067c
);
blk00000003_blk0000046e : XORCY
port map (
CI => blk00000003_sig00000677,
LI => blk00000003_sig00000678,
O => blk00000003_sig00000679
);
blk00000003_blk0000046d : XORCY
port map (
CI => blk00000003_sig00000674,
LI => blk00000003_sig00000675,
O => blk00000003_sig00000676
);
blk00000003_blk0000046c : XORCY
port map (
CI => blk00000003_sig00000671,
LI => blk00000003_sig00000672,
O => blk00000003_sig00000673
);
blk00000003_blk0000046b : XORCY
port map (
CI => blk00000003_sig0000066e,
LI => blk00000003_sig0000066f,
O => blk00000003_sig00000670
);
blk00000003_blk0000046a : XORCY
port map (
CI => blk00000003_sig0000066b,
LI => blk00000003_sig0000066c,
O => blk00000003_sig0000066d
);
blk00000003_blk00000469 : XORCY
port map (
CI => blk00000003_sig00000668,
LI => blk00000003_sig00000669,
O => blk00000003_sig0000066a
);
blk00000003_blk00000468 : XORCY
port map (
CI => blk00000003_sig00000665,
LI => blk00000003_sig00000666,
O => blk00000003_sig00000667
);
blk00000003_blk00000467 : XORCY
port map (
CI => blk00000003_sig00000662,
LI => blk00000003_sig00000663,
O => blk00000003_sig00000664
);
blk00000003_blk00000466 : XORCY
port map (
CI => blk00000003_sig0000065f,
LI => blk00000003_sig00000660,
O => blk00000003_sig00000661
);
blk00000003_blk00000465 : XORCY
port map (
CI => blk00000003_sig0000065c,
LI => blk00000003_sig0000065d,
O => blk00000003_sig0000065e
);
blk00000003_blk00000464 : XORCY
port map (
CI => blk00000003_sig00000659,
LI => blk00000003_sig0000065a,
O => blk00000003_sig0000065b
);
blk00000003_blk00000463 : XORCY
port map (
CI => blk00000003_sig00000656,
LI => blk00000003_sig00000657,
O => blk00000003_sig00000658
);
blk00000003_blk00000462 : XORCY
port map (
CI => blk00000003_sig00000653,
LI => blk00000003_sig00000654,
O => blk00000003_sig00000655
);
blk00000003_blk00000461 : XORCY
port map (
CI => blk00000003_sig00000650,
LI => blk00000003_sig00000651,
O => blk00000003_sig00000652
);
blk00000003_blk00000460 : XORCY
port map (
CI => blk00000003_sig0000064d,
LI => blk00000003_sig0000064e,
O => blk00000003_sig0000064f
);
blk00000003_blk0000045f : XORCY
port map (
CI => blk00000003_sig0000064a,
LI => blk00000003_sig0000064b,
O => blk00000003_sig0000064c
);
blk00000003_blk0000045e : XORCY
port map (
CI => blk00000003_sig00000647,
LI => blk00000003_sig00000648,
O => blk00000003_sig00000649
);
blk00000003_blk0000045d : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000641,
Q => blk00000003_sig00000646
);
blk00000003_blk0000045c : MUXCY
port map (
CI => blk00000003_sig00000642,
DI => blk00000003_sig00000645,
S => blk00000003_sig00000643,
O => blk00000003_sig00000626
);
blk00000003_blk0000045b : XORCY
port map (
CI => blk00000003_sig00000642,
LI => blk00000003_sig00000643,
O => blk00000003_sig00000644
);
blk00000003_blk0000045a : MUXCY
port map (
CI => blk00000003_sig000005e1,
DI => blk00000003_sig00000640,
S => blk00000003_sig000005e2,
O => blk00000003_sig00000641
);
blk00000003_blk00000459 : MUXCY
port map (
CI => blk00000003_sig00000626,
DI => blk00000003_sig0000063f,
S => blk00000003_sig00000627,
O => blk00000003_sig00000623
);
blk00000003_blk00000458 : MUXCY
port map (
CI => blk00000003_sig00000623,
DI => blk00000003_sig0000063e,
S => blk00000003_sig00000624,
O => blk00000003_sig00000620
);
blk00000003_blk00000457 : MUXCY
port map (
CI => blk00000003_sig00000620,
DI => blk00000003_sig0000063d,
S => blk00000003_sig00000621,
O => blk00000003_sig0000061d
);
blk00000003_blk00000456 : MUXCY
port map (
CI => blk00000003_sig0000061d,
DI => blk00000003_sig0000063c,
S => blk00000003_sig0000061e,
O => blk00000003_sig0000061a
);
blk00000003_blk00000455 : MUXCY
port map (
CI => blk00000003_sig0000061a,
DI => blk00000003_sig0000063b,
S => blk00000003_sig0000061b,
O => blk00000003_sig00000617
);
blk00000003_blk00000454 : MUXCY
port map (
CI => blk00000003_sig00000617,
DI => blk00000003_sig0000063a,
S => blk00000003_sig00000618,
O => blk00000003_sig00000614
);
blk00000003_blk00000453 : MUXCY
port map (
CI => blk00000003_sig00000614,
DI => blk00000003_sig00000639,
S => blk00000003_sig00000615,
O => blk00000003_sig00000611
);
blk00000003_blk00000452 : MUXCY
port map (
CI => blk00000003_sig00000611,
DI => blk00000003_sig00000638,
S => blk00000003_sig00000612,
O => blk00000003_sig0000060e
);
blk00000003_blk00000451 : MUXCY
port map (
CI => blk00000003_sig0000060e,
DI => blk00000003_sig00000637,
S => blk00000003_sig0000060f,
O => blk00000003_sig0000060b
);
blk00000003_blk00000450 : MUXCY
port map (
CI => blk00000003_sig0000060b,
DI => blk00000003_sig00000636,
S => blk00000003_sig0000060c,
O => blk00000003_sig00000608
);
blk00000003_blk0000044f : MUXCY
port map (
CI => blk00000003_sig00000608,
DI => blk00000003_sig00000635,
S => blk00000003_sig00000609,
O => blk00000003_sig00000605
);
blk00000003_blk0000044e : MUXCY
port map (
CI => blk00000003_sig00000605,
DI => blk00000003_sig00000634,
S => blk00000003_sig00000606,
O => blk00000003_sig00000602
);
blk00000003_blk0000044d : MUXCY
port map (
CI => blk00000003_sig00000602,
DI => blk00000003_sig00000633,
S => blk00000003_sig00000603,
O => blk00000003_sig000005ff
);
blk00000003_blk0000044c : MUXCY
port map (
CI => blk00000003_sig000005ff,
DI => blk00000003_sig00000632,
S => blk00000003_sig00000600,
O => blk00000003_sig000005fc
);
blk00000003_blk0000044b : MUXCY
port map (
CI => blk00000003_sig000005fc,
DI => blk00000003_sig00000631,
S => blk00000003_sig000005fd,
O => blk00000003_sig000005f9
);
blk00000003_blk0000044a : MUXCY
port map (
CI => blk00000003_sig000005f9,
DI => blk00000003_sig00000630,
S => blk00000003_sig000005fa,
O => blk00000003_sig000005f6
);
blk00000003_blk00000449 : MUXCY
port map (
CI => blk00000003_sig000005f6,
DI => blk00000003_sig0000062f,
S => blk00000003_sig000005f7,
O => blk00000003_sig000005f3
);
blk00000003_blk00000448 : MUXCY
port map (
CI => blk00000003_sig000005f3,
DI => blk00000003_sig0000062e,
S => blk00000003_sig000005f4,
O => blk00000003_sig000005f0
);
blk00000003_blk00000447 : MUXCY
port map (
CI => blk00000003_sig000005f0,
DI => blk00000003_sig0000062d,
S => blk00000003_sig000005f1,
O => blk00000003_sig000005ed
);
blk00000003_blk00000446 : MUXCY
port map (
CI => blk00000003_sig000005ed,
DI => blk00000003_sig0000062c,
S => blk00000003_sig000005ee,
O => blk00000003_sig000005ea
);
blk00000003_blk00000445 : MUXCY
port map (
CI => blk00000003_sig000005ea,
DI => blk00000003_sig0000062b,
S => blk00000003_sig000005eb,
O => blk00000003_sig000005e7
);
blk00000003_blk00000444 : MUXCY
port map (
CI => blk00000003_sig000005e7,
DI => blk00000003_sig0000062a,
S => blk00000003_sig000005e8,
O => blk00000003_sig000005e4
);
blk00000003_blk00000443 : MUXCY
port map (
CI => blk00000003_sig000005e4,
DI => blk00000003_sig00000629,
S => blk00000003_sig000005e5,
O => blk00000003_sig000005e1
);
blk00000003_blk00000442 : XORCY
port map (
CI => blk00000003_sig00000626,
LI => blk00000003_sig00000627,
O => blk00000003_sig00000628
);
blk00000003_blk00000441 : XORCY
port map (
CI => blk00000003_sig00000623,
LI => blk00000003_sig00000624,
O => blk00000003_sig00000625
);
blk00000003_blk00000440 : XORCY
port map (
CI => blk00000003_sig00000620,
LI => blk00000003_sig00000621,
O => blk00000003_sig00000622
);
blk00000003_blk0000043f : XORCY
port map (
CI => blk00000003_sig0000061d,
LI => blk00000003_sig0000061e,
O => blk00000003_sig0000061f
);
blk00000003_blk0000043e : XORCY
port map (
CI => blk00000003_sig0000061a,
LI => blk00000003_sig0000061b,
O => blk00000003_sig0000061c
);
blk00000003_blk0000043d : XORCY
port map (
CI => blk00000003_sig00000617,
LI => blk00000003_sig00000618,
O => blk00000003_sig00000619
);
blk00000003_blk0000043c : XORCY
port map (
CI => blk00000003_sig00000614,
LI => blk00000003_sig00000615,
O => blk00000003_sig00000616
);
blk00000003_blk0000043b : XORCY
port map (
CI => blk00000003_sig00000611,
LI => blk00000003_sig00000612,
O => blk00000003_sig00000613
);
blk00000003_blk0000043a : XORCY
port map (
CI => blk00000003_sig0000060e,
LI => blk00000003_sig0000060f,
O => blk00000003_sig00000610
);
blk00000003_blk00000439 : XORCY
port map (
CI => blk00000003_sig0000060b,
LI => blk00000003_sig0000060c,
O => blk00000003_sig0000060d
);
blk00000003_blk00000438 : XORCY
port map (
CI => blk00000003_sig00000608,
LI => blk00000003_sig00000609,
O => blk00000003_sig0000060a
);
blk00000003_blk00000437 : XORCY
port map (
CI => blk00000003_sig00000605,
LI => blk00000003_sig00000606,
O => blk00000003_sig00000607
);
blk00000003_blk00000436 : XORCY
port map (
CI => blk00000003_sig00000602,
LI => blk00000003_sig00000603,
O => blk00000003_sig00000604
);
blk00000003_blk00000435 : XORCY
port map (
CI => blk00000003_sig000005ff,
LI => blk00000003_sig00000600,
O => blk00000003_sig00000601
);
blk00000003_blk00000434 : XORCY
port map (
CI => blk00000003_sig000005fc,
LI => blk00000003_sig000005fd,
O => blk00000003_sig000005fe
);
blk00000003_blk00000433 : XORCY
port map (
CI => blk00000003_sig000005f9,
LI => blk00000003_sig000005fa,
O => blk00000003_sig000005fb
);
blk00000003_blk00000432 : XORCY
port map (
CI => blk00000003_sig000005f6,
LI => blk00000003_sig000005f7,
O => blk00000003_sig000005f8
);
blk00000003_blk00000431 : XORCY
port map (
CI => blk00000003_sig000005f3,
LI => blk00000003_sig000005f4,
O => blk00000003_sig000005f5
);
blk00000003_blk00000430 : XORCY
port map (
CI => blk00000003_sig000005f0,
LI => blk00000003_sig000005f1,
O => blk00000003_sig000005f2
);
blk00000003_blk0000042f : XORCY
port map (
CI => blk00000003_sig000005ed,
LI => blk00000003_sig000005ee,
O => blk00000003_sig000005ef
);
blk00000003_blk0000042e : XORCY
port map (
CI => blk00000003_sig000005ea,
LI => blk00000003_sig000005eb,
O => blk00000003_sig000005ec
);
blk00000003_blk0000042d : XORCY
port map (
CI => blk00000003_sig000005e7,
LI => blk00000003_sig000005e8,
O => blk00000003_sig000005e9
);
blk00000003_blk0000042c : XORCY
port map (
CI => blk00000003_sig000005e4,
LI => blk00000003_sig000005e5,
O => blk00000003_sig000005e6
);
blk00000003_blk0000042b : XORCY
port map (
CI => blk00000003_sig000005e1,
LI => blk00000003_sig000005e2,
O => blk00000003_sig000005e3
);
blk00000003_blk0000042a : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig000005db,
Q => blk00000003_sig000005e0
);
blk00000003_blk00000429 : MUXCY
port map (
CI => blk00000003_sig000005dc,
DI => blk00000003_sig000005df,
S => blk00000003_sig000005dd,
O => blk00000003_sig000005c0
);
blk00000003_blk00000428 : XORCY
port map (
CI => blk00000003_sig000005dc,
LI => blk00000003_sig000005dd,
O => blk00000003_sig000005de
);
blk00000003_blk00000427 : MUXCY
port map (
CI => blk00000003_sig0000057b,
DI => blk00000003_sig000005da,
S => blk00000003_sig0000057c,
O => blk00000003_sig000005db
);
blk00000003_blk00000426 : MUXCY
port map (
CI => blk00000003_sig000005c0,
DI => blk00000003_sig000005d9,
S => blk00000003_sig000005c1,
O => blk00000003_sig000005bd
);
blk00000003_blk00000425 : MUXCY
port map (
CI => blk00000003_sig000005bd,
DI => blk00000003_sig000005d8,
S => blk00000003_sig000005be,
O => blk00000003_sig000005ba
);
blk00000003_blk00000424 : MUXCY
port map (
CI => blk00000003_sig000005ba,
DI => blk00000003_sig000005d7,
S => blk00000003_sig000005bb,
O => blk00000003_sig000005b7
);
blk00000003_blk00000423 : MUXCY
port map (
CI => blk00000003_sig000005b7,
DI => blk00000003_sig000005d6,
S => blk00000003_sig000005b8,
O => blk00000003_sig000005b4
);
blk00000003_blk00000422 : MUXCY
port map (
CI => blk00000003_sig000005b4,
DI => blk00000003_sig000005d5,
S => blk00000003_sig000005b5,
O => blk00000003_sig000005b1
);
blk00000003_blk00000421 : MUXCY
port map (
CI => blk00000003_sig000005b1,
DI => blk00000003_sig000005d4,
S => blk00000003_sig000005b2,
O => blk00000003_sig000005ae
);
blk00000003_blk00000420 : MUXCY
port map (
CI => blk00000003_sig000005ae,
DI => blk00000003_sig000005d3,
S => blk00000003_sig000005af,
O => blk00000003_sig000005ab
);
blk00000003_blk0000041f : MUXCY
port map (
CI => blk00000003_sig000005ab,
DI => blk00000003_sig000005d2,
S => blk00000003_sig000005ac,
O => blk00000003_sig000005a8
);
blk00000003_blk0000041e : MUXCY
port map (
CI => blk00000003_sig000005a8,
DI => blk00000003_sig000005d1,
S => blk00000003_sig000005a9,
O => blk00000003_sig000005a5
);
blk00000003_blk0000041d : MUXCY
port map (
CI => blk00000003_sig000005a5,
DI => blk00000003_sig000005d0,
S => blk00000003_sig000005a6,
O => blk00000003_sig000005a2
);
blk00000003_blk0000041c : MUXCY
port map (
CI => blk00000003_sig000005a2,
DI => blk00000003_sig000005cf,
S => blk00000003_sig000005a3,
O => blk00000003_sig0000059f
);
blk00000003_blk0000041b : MUXCY
port map (
CI => blk00000003_sig0000059f,
DI => blk00000003_sig000005ce,
S => blk00000003_sig000005a0,
O => blk00000003_sig0000059c
);
blk00000003_blk0000041a : MUXCY
port map (
CI => blk00000003_sig0000059c,
DI => blk00000003_sig000005cd,
S => blk00000003_sig0000059d,
O => blk00000003_sig00000599
);
blk00000003_blk00000419 : MUXCY
port map (
CI => blk00000003_sig00000599,
DI => blk00000003_sig000005cc,
S => blk00000003_sig0000059a,
O => blk00000003_sig00000596
);
blk00000003_blk00000418 : MUXCY
port map (
CI => blk00000003_sig00000596,
DI => blk00000003_sig000005cb,
S => blk00000003_sig00000597,
O => blk00000003_sig00000593
);
blk00000003_blk00000417 : MUXCY
port map (
CI => blk00000003_sig00000593,
DI => blk00000003_sig000005ca,
S => blk00000003_sig00000594,
O => blk00000003_sig00000590
);
blk00000003_blk00000416 : MUXCY
port map (
CI => blk00000003_sig00000590,
DI => blk00000003_sig000005c9,
S => blk00000003_sig00000591,
O => blk00000003_sig0000058d
);
blk00000003_blk00000415 : MUXCY
port map (
CI => blk00000003_sig0000058d,
DI => blk00000003_sig000005c8,
S => blk00000003_sig0000058e,
O => blk00000003_sig0000058a
);
blk00000003_blk00000414 : MUXCY
port map (
CI => blk00000003_sig0000058a,
DI => blk00000003_sig000005c7,
S => blk00000003_sig0000058b,
O => blk00000003_sig00000587
);
blk00000003_blk00000413 : MUXCY
port map (
CI => blk00000003_sig00000587,
DI => blk00000003_sig000005c6,
S => blk00000003_sig00000588,
O => blk00000003_sig00000584
);
blk00000003_blk00000412 : MUXCY
port map (
CI => blk00000003_sig00000584,
DI => blk00000003_sig000005c5,
S => blk00000003_sig00000585,
O => blk00000003_sig00000581
);
blk00000003_blk00000411 : MUXCY
port map (
CI => blk00000003_sig00000581,
DI => blk00000003_sig000005c4,
S => blk00000003_sig00000582,
O => blk00000003_sig0000057e
);
blk00000003_blk00000410 : MUXCY
port map (
CI => blk00000003_sig0000057e,
DI => blk00000003_sig000005c3,
S => blk00000003_sig0000057f,
O => blk00000003_sig0000057b
);
blk00000003_blk0000040f : XORCY
port map (
CI => blk00000003_sig000005c0,
LI => blk00000003_sig000005c1,
O => blk00000003_sig000005c2
);
blk00000003_blk0000040e : XORCY
port map (
CI => blk00000003_sig000005bd,
LI => blk00000003_sig000005be,
O => blk00000003_sig000005bf
);
blk00000003_blk0000040d : XORCY
port map (
CI => blk00000003_sig000005ba,
LI => blk00000003_sig000005bb,
O => blk00000003_sig000005bc
);
blk00000003_blk0000040c : XORCY
port map (
CI => blk00000003_sig000005b7,
LI => blk00000003_sig000005b8,
O => blk00000003_sig000005b9
);
blk00000003_blk0000040b : XORCY
port map (
CI => blk00000003_sig000005b4,
LI => blk00000003_sig000005b5,
O => blk00000003_sig000005b6
);
blk00000003_blk0000040a : XORCY
port map (
CI => blk00000003_sig000005b1,
LI => blk00000003_sig000005b2,
O => blk00000003_sig000005b3
);
blk00000003_blk00000409 : XORCY
port map (
CI => blk00000003_sig000005ae,
LI => blk00000003_sig000005af,
O => blk00000003_sig000005b0
);
blk00000003_blk00000408 : XORCY
port map (
CI => blk00000003_sig000005ab,
LI => blk00000003_sig000005ac,
O => blk00000003_sig000005ad
);
blk00000003_blk00000407 : XORCY
port map (
CI => blk00000003_sig000005a8,
LI => blk00000003_sig000005a9,
O => blk00000003_sig000005aa
);
blk00000003_blk00000406 : XORCY
port map (
CI => blk00000003_sig000005a5,
LI => blk00000003_sig000005a6,
O => blk00000003_sig000005a7
);
blk00000003_blk00000405 : XORCY
port map (
CI => blk00000003_sig000005a2,
LI => blk00000003_sig000005a3,
O => blk00000003_sig000005a4
);
blk00000003_blk00000404 : XORCY
port map (
CI => blk00000003_sig0000059f,
LI => blk00000003_sig000005a0,
O => blk00000003_sig000005a1
);
blk00000003_blk00000403 : XORCY
port map (
CI => blk00000003_sig0000059c,
LI => blk00000003_sig0000059d,
O => blk00000003_sig0000059e
);
blk00000003_blk00000402 : XORCY
port map (
CI => blk00000003_sig00000599,
LI => blk00000003_sig0000059a,
O => blk00000003_sig0000059b
);
blk00000003_blk00000401 : XORCY
port map (
CI => blk00000003_sig00000596,
LI => blk00000003_sig00000597,
O => blk00000003_sig00000598
);
blk00000003_blk00000400 : XORCY
port map (
CI => blk00000003_sig00000593,
LI => blk00000003_sig00000594,
O => blk00000003_sig00000595
);
blk00000003_blk000003ff : XORCY
port map (
CI => blk00000003_sig00000590,
LI => blk00000003_sig00000591,
O => blk00000003_sig00000592
);
blk00000003_blk000003fe : XORCY
port map (
CI => blk00000003_sig0000058d,
LI => blk00000003_sig0000058e,
O => blk00000003_sig0000058f
);
blk00000003_blk000003fd : XORCY
port map (
CI => blk00000003_sig0000058a,
LI => blk00000003_sig0000058b,
O => blk00000003_sig0000058c
);
blk00000003_blk000003fc : XORCY
port map (
CI => blk00000003_sig00000587,
LI => blk00000003_sig00000588,
O => blk00000003_sig00000589
);
blk00000003_blk000003fb : XORCY
port map (
CI => blk00000003_sig00000584,
LI => blk00000003_sig00000585,
O => blk00000003_sig00000586
);
blk00000003_blk000003fa : XORCY
port map (
CI => blk00000003_sig00000581,
LI => blk00000003_sig00000582,
O => blk00000003_sig00000583
);
blk00000003_blk000003f9 : XORCY
port map (
CI => blk00000003_sig0000057e,
LI => blk00000003_sig0000057f,
O => blk00000003_sig00000580
);
blk00000003_blk000003f8 : XORCY
port map (
CI => blk00000003_sig0000057b,
LI => blk00000003_sig0000057c,
O => blk00000003_sig0000057d
);
blk00000003_blk000003f7 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000575,
Q => blk00000003_sig0000057a
);
blk00000003_blk000003f6 : MUXCY
port map (
CI => blk00000003_sig00000576,
DI => blk00000003_sig00000579,
S => blk00000003_sig00000577,
O => blk00000003_sig0000055a
);
blk00000003_blk000003f5 : XORCY
port map (
CI => blk00000003_sig00000576,
LI => blk00000003_sig00000577,
O => blk00000003_sig00000578
);
blk00000003_blk000003f4 : MUXCY
port map (
CI => blk00000003_sig00000515,
DI => blk00000003_sig00000574,
S => blk00000003_sig00000516,
O => blk00000003_sig00000575
);
blk00000003_blk000003f3 : MUXCY
port map (
CI => blk00000003_sig0000055a,
DI => blk00000003_sig00000573,
S => blk00000003_sig0000055b,
O => blk00000003_sig00000557
);
blk00000003_blk000003f2 : MUXCY
port map (
CI => blk00000003_sig00000557,
DI => blk00000003_sig00000572,
S => blk00000003_sig00000558,
O => blk00000003_sig00000554
);
blk00000003_blk000003f1 : MUXCY
port map (
CI => blk00000003_sig00000554,
DI => blk00000003_sig00000571,
S => blk00000003_sig00000555,
O => blk00000003_sig00000551
);
blk00000003_blk000003f0 : MUXCY
port map (
CI => blk00000003_sig00000551,
DI => blk00000003_sig00000570,
S => blk00000003_sig00000552,
O => blk00000003_sig0000054e
);
blk00000003_blk000003ef : MUXCY
port map (
CI => blk00000003_sig0000054e,
DI => blk00000003_sig0000056f,
S => blk00000003_sig0000054f,
O => blk00000003_sig0000054b
);
blk00000003_blk000003ee : MUXCY
port map (
CI => blk00000003_sig0000054b,
DI => blk00000003_sig0000056e,
S => blk00000003_sig0000054c,
O => blk00000003_sig00000548
);
blk00000003_blk000003ed : MUXCY
port map (
CI => blk00000003_sig00000548,
DI => blk00000003_sig0000056d,
S => blk00000003_sig00000549,
O => blk00000003_sig00000545
);
blk00000003_blk000003ec : MUXCY
port map (
CI => blk00000003_sig00000545,
DI => blk00000003_sig0000056c,
S => blk00000003_sig00000546,
O => blk00000003_sig00000542
);
blk00000003_blk000003eb : MUXCY
port map (
CI => blk00000003_sig00000542,
DI => blk00000003_sig0000056b,
S => blk00000003_sig00000543,
O => blk00000003_sig0000053f
);
blk00000003_blk000003ea : MUXCY
port map (
CI => blk00000003_sig0000053f,
DI => blk00000003_sig0000056a,
S => blk00000003_sig00000540,
O => blk00000003_sig0000053c
);
blk00000003_blk000003e9 : MUXCY
port map (
CI => blk00000003_sig0000053c,
DI => blk00000003_sig00000569,
S => blk00000003_sig0000053d,
O => blk00000003_sig00000539
);
blk00000003_blk000003e8 : MUXCY
port map (
CI => blk00000003_sig00000539,
DI => blk00000003_sig00000568,
S => blk00000003_sig0000053a,
O => blk00000003_sig00000536
);
blk00000003_blk000003e7 : MUXCY
port map (
CI => blk00000003_sig00000536,
DI => blk00000003_sig00000567,
S => blk00000003_sig00000537,
O => blk00000003_sig00000533
);
blk00000003_blk000003e6 : MUXCY
port map (
CI => blk00000003_sig00000533,
DI => blk00000003_sig00000566,
S => blk00000003_sig00000534,
O => blk00000003_sig00000530
);
blk00000003_blk000003e5 : MUXCY
port map (
CI => blk00000003_sig00000530,
DI => blk00000003_sig00000565,
S => blk00000003_sig00000531,
O => blk00000003_sig0000052d
);
blk00000003_blk000003e4 : MUXCY
port map (
CI => blk00000003_sig0000052d,
DI => blk00000003_sig00000564,
S => blk00000003_sig0000052e,
O => blk00000003_sig0000052a
);
blk00000003_blk000003e3 : MUXCY
port map (
CI => blk00000003_sig0000052a,
DI => blk00000003_sig00000563,
S => blk00000003_sig0000052b,
O => blk00000003_sig00000527
);
blk00000003_blk000003e2 : MUXCY
port map (
CI => blk00000003_sig00000527,
DI => blk00000003_sig00000562,
S => blk00000003_sig00000528,
O => blk00000003_sig00000524
);
blk00000003_blk000003e1 : MUXCY
port map (
CI => blk00000003_sig00000524,
DI => blk00000003_sig00000561,
S => blk00000003_sig00000525,
O => blk00000003_sig00000521
);
blk00000003_blk000003e0 : MUXCY
port map (
CI => blk00000003_sig00000521,
DI => blk00000003_sig00000560,
S => blk00000003_sig00000522,
O => blk00000003_sig0000051e
);
blk00000003_blk000003df : MUXCY
port map (
CI => blk00000003_sig0000051e,
DI => blk00000003_sig0000055f,
S => blk00000003_sig0000051f,
O => blk00000003_sig0000051b
);
blk00000003_blk000003de : MUXCY
port map (
CI => blk00000003_sig0000051b,
DI => blk00000003_sig0000055e,
S => blk00000003_sig0000051c,
O => blk00000003_sig00000518
);
blk00000003_blk000003dd : MUXCY
port map (
CI => blk00000003_sig00000518,
DI => blk00000003_sig0000055d,
S => blk00000003_sig00000519,
O => blk00000003_sig00000515
);
blk00000003_blk000003dc : XORCY
port map (
CI => blk00000003_sig0000055a,
LI => blk00000003_sig0000055b,
O => blk00000003_sig0000055c
);
blk00000003_blk000003db : XORCY
port map (
CI => blk00000003_sig00000557,
LI => blk00000003_sig00000558,
O => blk00000003_sig00000559
);
blk00000003_blk000003da : XORCY
port map (
CI => blk00000003_sig00000554,
LI => blk00000003_sig00000555,
O => blk00000003_sig00000556
);
blk00000003_blk000003d9 : XORCY
port map (
CI => blk00000003_sig00000551,
LI => blk00000003_sig00000552,
O => blk00000003_sig00000553
);
blk00000003_blk000003d8 : XORCY
port map (
CI => blk00000003_sig0000054e,
LI => blk00000003_sig0000054f,
O => blk00000003_sig00000550
);
blk00000003_blk000003d7 : XORCY
port map (
CI => blk00000003_sig0000054b,
LI => blk00000003_sig0000054c,
O => blk00000003_sig0000054d
);
blk00000003_blk000003d6 : XORCY
port map (
CI => blk00000003_sig00000548,
LI => blk00000003_sig00000549,
O => blk00000003_sig0000054a
);
blk00000003_blk000003d5 : XORCY
port map (
CI => blk00000003_sig00000545,
LI => blk00000003_sig00000546,
O => blk00000003_sig00000547
);
blk00000003_blk000003d4 : XORCY
port map (
CI => blk00000003_sig00000542,
LI => blk00000003_sig00000543,
O => blk00000003_sig00000544
);
blk00000003_blk000003d3 : XORCY
port map (
CI => blk00000003_sig0000053f,
LI => blk00000003_sig00000540,
O => blk00000003_sig00000541
);
blk00000003_blk000003d2 : XORCY
port map (
CI => blk00000003_sig0000053c,
LI => blk00000003_sig0000053d,
O => blk00000003_sig0000053e
);
blk00000003_blk000003d1 : XORCY
port map (
CI => blk00000003_sig00000539,
LI => blk00000003_sig0000053a,
O => blk00000003_sig0000053b
);
blk00000003_blk000003d0 : XORCY
port map (
CI => blk00000003_sig00000536,
LI => blk00000003_sig00000537,
O => blk00000003_sig00000538
);
blk00000003_blk000003cf : XORCY
port map (
CI => blk00000003_sig00000533,
LI => blk00000003_sig00000534,
O => blk00000003_sig00000535
);
blk00000003_blk000003ce : XORCY
port map (
CI => blk00000003_sig00000530,
LI => blk00000003_sig00000531,
O => blk00000003_sig00000532
);
blk00000003_blk000003cd : XORCY
port map (
CI => blk00000003_sig0000052d,
LI => blk00000003_sig0000052e,
O => blk00000003_sig0000052f
);
blk00000003_blk000003cc : XORCY
port map (
CI => blk00000003_sig0000052a,
LI => blk00000003_sig0000052b,
O => blk00000003_sig0000052c
);
blk00000003_blk000003cb : XORCY
port map (
CI => blk00000003_sig00000527,
LI => blk00000003_sig00000528,
O => blk00000003_sig00000529
);
blk00000003_blk000003ca : XORCY
port map (
CI => blk00000003_sig00000524,
LI => blk00000003_sig00000525,
O => blk00000003_sig00000526
);
blk00000003_blk000003c9 : XORCY
port map (
CI => blk00000003_sig00000521,
LI => blk00000003_sig00000522,
O => blk00000003_sig00000523
);
blk00000003_blk000003c8 : XORCY
port map (
CI => blk00000003_sig0000051e,
LI => blk00000003_sig0000051f,
O => blk00000003_sig00000520
);
blk00000003_blk000003c7 : XORCY
port map (
CI => blk00000003_sig0000051b,
LI => blk00000003_sig0000051c,
O => blk00000003_sig0000051d
);
blk00000003_blk000003c6 : XORCY
port map (
CI => blk00000003_sig00000518,
LI => blk00000003_sig00000519,
O => blk00000003_sig0000051a
);
blk00000003_blk000003c5 : XORCY
port map (
CI => blk00000003_sig00000515,
LI => blk00000003_sig00000516,
O => blk00000003_sig00000517
);
blk00000003_blk000003c4 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig0000050f,
Q => blk00000003_sig00000514
);
blk00000003_blk000003c3 : MUXCY
port map (
CI => blk00000003_sig00000510,
DI => blk00000003_sig00000513,
S => blk00000003_sig00000511,
O => blk00000003_sig000004f4
);
blk00000003_blk000003c2 : XORCY
port map (
CI => blk00000003_sig00000510,
LI => blk00000003_sig00000511,
O => blk00000003_sig00000512
);
blk00000003_blk000003c1 : MUXCY
port map (
CI => blk00000003_sig000004af,
DI => blk00000003_sig0000050e,
S => blk00000003_sig000004b0,
O => blk00000003_sig0000050f
);
blk00000003_blk000003c0 : MUXCY
port map (
CI => blk00000003_sig000004f4,
DI => blk00000003_sig0000050d,
S => blk00000003_sig000004f5,
O => blk00000003_sig000004f1
);
blk00000003_blk000003bf : MUXCY
port map (
CI => blk00000003_sig000004f1,
DI => blk00000003_sig0000050c,
S => blk00000003_sig000004f2,
O => blk00000003_sig000004ee
);
blk00000003_blk000003be : MUXCY
port map (
CI => blk00000003_sig000004ee,
DI => blk00000003_sig0000050b,
S => blk00000003_sig000004ef,
O => blk00000003_sig000004eb
);
blk00000003_blk000003bd : MUXCY
port map (
CI => blk00000003_sig000004eb,
DI => blk00000003_sig0000050a,
S => blk00000003_sig000004ec,
O => blk00000003_sig000004e8
);
blk00000003_blk000003bc : MUXCY
port map (
CI => blk00000003_sig000004e8,
DI => blk00000003_sig00000509,
S => blk00000003_sig000004e9,
O => blk00000003_sig000004e5
);
blk00000003_blk000003bb : MUXCY
port map (
CI => blk00000003_sig000004e5,
DI => blk00000003_sig00000508,
S => blk00000003_sig000004e6,
O => blk00000003_sig000004e2
);
blk00000003_blk000003ba : MUXCY
port map (
CI => blk00000003_sig000004e2,
DI => blk00000003_sig00000507,
S => blk00000003_sig000004e3,
O => blk00000003_sig000004df
);
blk00000003_blk000003b9 : MUXCY
port map (
CI => blk00000003_sig000004df,
DI => blk00000003_sig00000506,
S => blk00000003_sig000004e0,
O => blk00000003_sig000004dc
);
blk00000003_blk000003b8 : MUXCY
port map (
CI => blk00000003_sig000004dc,
DI => blk00000003_sig00000505,
S => blk00000003_sig000004dd,
O => blk00000003_sig000004d9
);
blk00000003_blk000003b7 : MUXCY
port map (
CI => blk00000003_sig000004d9,
DI => blk00000003_sig00000504,
S => blk00000003_sig000004da,
O => blk00000003_sig000004d6
);
blk00000003_blk000003b6 : MUXCY
port map (
CI => blk00000003_sig000004d6,
DI => blk00000003_sig00000503,
S => blk00000003_sig000004d7,
O => blk00000003_sig000004d3
);
blk00000003_blk000003b5 : MUXCY
port map (
CI => blk00000003_sig000004d3,
DI => blk00000003_sig00000502,
S => blk00000003_sig000004d4,
O => blk00000003_sig000004d0
);
blk00000003_blk000003b4 : MUXCY
port map (
CI => blk00000003_sig000004d0,
DI => blk00000003_sig00000501,
S => blk00000003_sig000004d1,
O => blk00000003_sig000004cd
);
blk00000003_blk000003b3 : MUXCY
port map (
CI => blk00000003_sig000004cd,
DI => blk00000003_sig00000500,
S => blk00000003_sig000004ce,
O => blk00000003_sig000004ca
);
blk00000003_blk000003b2 : MUXCY
port map (
CI => blk00000003_sig000004ca,
DI => blk00000003_sig000004ff,
S => blk00000003_sig000004cb,
O => blk00000003_sig000004c7
);
blk00000003_blk000003b1 : MUXCY
port map (
CI => blk00000003_sig000004c7,
DI => blk00000003_sig000004fe,
S => blk00000003_sig000004c8,
O => blk00000003_sig000004c4
);
blk00000003_blk000003b0 : MUXCY
port map (
CI => blk00000003_sig000004c4,
DI => blk00000003_sig000004fd,
S => blk00000003_sig000004c5,
O => blk00000003_sig000004c1
);
blk00000003_blk000003af : MUXCY
port map (
CI => blk00000003_sig000004c1,
DI => blk00000003_sig000004fc,
S => blk00000003_sig000004c2,
O => blk00000003_sig000004be
);
blk00000003_blk000003ae : MUXCY
port map (
CI => blk00000003_sig000004be,
DI => blk00000003_sig000004fb,
S => blk00000003_sig000004bf,
O => blk00000003_sig000004bb
);
blk00000003_blk000003ad : MUXCY
port map (
CI => blk00000003_sig000004bb,
DI => blk00000003_sig000004fa,
S => blk00000003_sig000004bc,
O => blk00000003_sig000004b8
);
blk00000003_blk000003ac : MUXCY
port map (
CI => blk00000003_sig000004b8,
DI => blk00000003_sig000004f9,
S => blk00000003_sig000004b9,
O => blk00000003_sig000004b5
);
blk00000003_blk000003ab : MUXCY
port map (
CI => blk00000003_sig000004b5,
DI => blk00000003_sig000004f8,
S => blk00000003_sig000004b6,
O => blk00000003_sig000004b2
);
blk00000003_blk000003aa : MUXCY
port map (
CI => blk00000003_sig000004b2,
DI => blk00000003_sig000004f7,
S => blk00000003_sig000004b3,
O => blk00000003_sig000004af
);
blk00000003_blk000003a9 : XORCY
port map (
CI => blk00000003_sig000004f4,
LI => blk00000003_sig000004f5,
O => blk00000003_sig000004f6
);
blk00000003_blk000003a8 : XORCY
port map (
CI => blk00000003_sig000004f1,
LI => blk00000003_sig000004f2,
O => blk00000003_sig000004f3
);
blk00000003_blk000003a7 : XORCY
port map (
CI => blk00000003_sig000004ee,
LI => blk00000003_sig000004ef,
O => blk00000003_sig000004f0
);
blk00000003_blk000003a6 : XORCY
port map (
CI => blk00000003_sig000004eb,
LI => blk00000003_sig000004ec,
O => blk00000003_sig000004ed
);
blk00000003_blk000003a5 : XORCY
port map (
CI => blk00000003_sig000004e8,
LI => blk00000003_sig000004e9,
O => blk00000003_sig000004ea
);
blk00000003_blk000003a4 : XORCY
port map (
CI => blk00000003_sig000004e5,
LI => blk00000003_sig000004e6,
O => blk00000003_sig000004e7
);
blk00000003_blk000003a3 : XORCY
port map (
CI => blk00000003_sig000004e2,
LI => blk00000003_sig000004e3,
O => blk00000003_sig000004e4
);
blk00000003_blk000003a2 : XORCY
port map (
CI => blk00000003_sig000004df,
LI => blk00000003_sig000004e0,
O => blk00000003_sig000004e1
);
blk00000003_blk000003a1 : XORCY
port map (
CI => blk00000003_sig000004dc,
LI => blk00000003_sig000004dd,
O => blk00000003_sig000004de
);
blk00000003_blk000003a0 : XORCY
port map (
CI => blk00000003_sig000004d9,
LI => blk00000003_sig000004da,
O => blk00000003_sig000004db
);
blk00000003_blk0000039f : XORCY
port map (
CI => blk00000003_sig000004d6,
LI => blk00000003_sig000004d7,
O => blk00000003_sig000004d8
);
blk00000003_blk0000039e : XORCY
port map (
CI => blk00000003_sig000004d3,
LI => blk00000003_sig000004d4,
O => blk00000003_sig000004d5
);
blk00000003_blk0000039d : XORCY
port map (
CI => blk00000003_sig000004d0,
LI => blk00000003_sig000004d1,
O => blk00000003_sig000004d2
);
blk00000003_blk0000039c : XORCY
port map (
CI => blk00000003_sig000004cd,
LI => blk00000003_sig000004ce,
O => blk00000003_sig000004cf
);
blk00000003_blk0000039b : XORCY
port map (
CI => blk00000003_sig000004ca,
LI => blk00000003_sig000004cb,
O => blk00000003_sig000004cc
);
blk00000003_blk0000039a : XORCY
port map (
CI => blk00000003_sig000004c7,
LI => blk00000003_sig000004c8,
O => blk00000003_sig000004c9
);
blk00000003_blk00000399 : XORCY
port map (
CI => blk00000003_sig000004c4,
LI => blk00000003_sig000004c5,
O => blk00000003_sig000004c6
);
blk00000003_blk00000398 : XORCY
port map (
CI => blk00000003_sig000004c1,
LI => blk00000003_sig000004c2,
O => blk00000003_sig000004c3
);
blk00000003_blk00000397 : XORCY
port map (
CI => blk00000003_sig000004be,
LI => blk00000003_sig000004bf,
O => blk00000003_sig000004c0
);
blk00000003_blk00000396 : XORCY
port map (
CI => blk00000003_sig000004bb,
LI => blk00000003_sig000004bc,
O => blk00000003_sig000004bd
);
blk00000003_blk00000395 : XORCY
port map (
CI => blk00000003_sig000004b8,
LI => blk00000003_sig000004b9,
O => blk00000003_sig000004ba
);
blk00000003_blk00000394 : XORCY
port map (
CI => blk00000003_sig000004b5,
LI => blk00000003_sig000004b6,
O => blk00000003_sig000004b7
);
blk00000003_blk00000393 : XORCY
port map (
CI => blk00000003_sig000004b2,
LI => blk00000003_sig000004b3,
O => blk00000003_sig000004b4
);
blk00000003_blk00000392 : XORCY
port map (
CI => blk00000003_sig000004af,
LI => blk00000003_sig000004b0,
O => blk00000003_sig000004b1
);
blk00000003_blk00000391 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig000004a9,
Q => blk00000003_sig000004ae
);
blk00000003_blk00000390 : MUXCY
port map (
CI => blk00000003_sig000004aa,
DI => blk00000003_sig000004ad,
S => blk00000003_sig000004ab,
O => blk00000003_sig0000048e
);
blk00000003_blk0000038f : XORCY
port map (
CI => blk00000003_sig000004aa,
LI => blk00000003_sig000004ab,
O => blk00000003_sig000004ac
);
blk00000003_blk0000038e : MUXCY
port map (
CI => blk00000003_sig00000449,
DI => blk00000003_sig000004a8,
S => blk00000003_sig0000044a,
O => blk00000003_sig000004a9
);
blk00000003_blk0000038d : MUXCY
port map (
CI => blk00000003_sig0000048e,
DI => blk00000003_sig000004a7,
S => blk00000003_sig0000048f,
O => blk00000003_sig0000048b
);
blk00000003_blk0000038c : MUXCY
port map (
CI => blk00000003_sig0000048b,
DI => blk00000003_sig000004a6,
S => blk00000003_sig0000048c,
O => blk00000003_sig00000488
);
blk00000003_blk0000038b : MUXCY
port map (
CI => blk00000003_sig00000488,
DI => blk00000003_sig000004a5,
S => blk00000003_sig00000489,
O => blk00000003_sig00000485
);
blk00000003_blk0000038a : MUXCY
port map (
CI => blk00000003_sig00000485,
DI => blk00000003_sig000004a4,
S => blk00000003_sig00000486,
O => blk00000003_sig00000482
);
blk00000003_blk00000389 : MUXCY
port map (
CI => blk00000003_sig00000482,
DI => blk00000003_sig000004a3,
S => blk00000003_sig00000483,
O => blk00000003_sig0000047f
);
blk00000003_blk00000388 : MUXCY
port map (
CI => blk00000003_sig0000047f,
DI => blk00000003_sig000004a2,
S => blk00000003_sig00000480,
O => blk00000003_sig0000047c
);
blk00000003_blk00000387 : MUXCY
port map (
CI => blk00000003_sig0000047c,
DI => blk00000003_sig000004a1,
S => blk00000003_sig0000047d,
O => blk00000003_sig00000479
);
blk00000003_blk00000386 : MUXCY
port map (
CI => blk00000003_sig00000479,
DI => blk00000003_sig000004a0,
S => blk00000003_sig0000047a,
O => blk00000003_sig00000476
);
blk00000003_blk00000385 : MUXCY
port map (
CI => blk00000003_sig00000476,
DI => blk00000003_sig0000049f,
S => blk00000003_sig00000477,
O => blk00000003_sig00000473
);
blk00000003_blk00000384 : MUXCY
port map (
CI => blk00000003_sig00000473,
DI => blk00000003_sig0000049e,
S => blk00000003_sig00000474,
O => blk00000003_sig00000470
);
blk00000003_blk00000383 : MUXCY
port map (
CI => blk00000003_sig00000470,
DI => blk00000003_sig0000049d,
S => blk00000003_sig00000471,
O => blk00000003_sig0000046d
);
blk00000003_blk00000382 : MUXCY
port map (
CI => blk00000003_sig0000046d,
DI => blk00000003_sig0000049c,
S => blk00000003_sig0000046e,
O => blk00000003_sig0000046a
);
blk00000003_blk00000381 : MUXCY
port map (
CI => blk00000003_sig0000046a,
DI => blk00000003_sig0000049b,
S => blk00000003_sig0000046b,
O => blk00000003_sig00000467
);
blk00000003_blk00000380 : MUXCY
port map (
CI => blk00000003_sig00000467,
DI => blk00000003_sig0000049a,
S => blk00000003_sig00000468,
O => blk00000003_sig00000464
);
blk00000003_blk0000037f : MUXCY
port map (
CI => blk00000003_sig00000464,
DI => blk00000003_sig00000499,
S => blk00000003_sig00000465,
O => blk00000003_sig00000461
);
blk00000003_blk0000037e : MUXCY
port map (
CI => blk00000003_sig00000461,
DI => blk00000003_sig00000498,
S => blk00000003_sig00000462,
O => blk00000003_sig0000045e
);
blk00000003_blk0000037d : MUXCY
port map (
CI => blk00000003_sig0000045e,
DI => blk00000003_sig00000497,
S => blk00000003_sig0000045f,
O => blk00000003_sig0000045b
);
blk00000003_blk0000037c : MUXCY
port map (
CI => blk00000003_sig0000045b,
DI => blk00000003_sig00000496,
S => blk00000003_sig0000045c,
O => blk00000003_sig00000458
);
blk00000003_blk0000037b : MUXCY
port map (
CI => blk00000003_sig00000458,
DI => blk00000003_sig00000495,
S => blk00000003_sig00000459,
O => blk00000003_sig00000455
);
blk00000003_blk0000037a : MUXCY
port map (
CI => blk00000003_sig00000455,
DI => blk00000003_sig00000494,
S => blk00000003_sig00000456,
O => blk00000003_sig00000452
);
blk00000003_blk00000379 : MUXCY
port map (
CI => blk00000003_sig00000452,
DI => blk00000003_sig00000493,
S => blk00000003_sig00000453,
O => blk00000003_sig0000044f
);
blk00000003_blk00000378 : MUXCY
port map (
CI => blk00000003_sig0000044f,
DI => blk00000003_sig00000492,
S => blk00000003_sig00000450,
O => blk00000003_sig0000044c
);
blk00000003_blk00000377 : MUXCY
port map (
CI => blk00000003_sig0000044c,
DI => blk00000003_sig00000491,
S => blk00000003_sig0000044d,
O => blk00000003_sig00000449
);
blk00000003_blk00000376 : XORCY
port map (
CI => blk00000003_sig0000048e,
LI => blk00000003_sig0000048f,
O => blk00000003_sig00000490
);
blk00000003_blk00000375 : XORCY
port map (
CI => blk00000003_sig0000048b,
LI => blk00000003_sig0000048c,
O => blk00000003_sig0000048d
);
blk00000003_blk00000374 : XORCY
port map (
CI => blk00000003_sig00000488,
LI => blk00000003_sig00000489,
O => blk00000003_sig0000048a
);
blk00000003_blk00000373 : XORCY
port map (
CI => blk00000003_sig00000485,
LI => blk00000003_sig00000486,
O => blk00000003_sig00000487
);
blk00000003_blk00000372 : XORCY
port map (
CI => blk00000003_sig00000482,
LI => blk00000003_sig00000483,
O => blk00000003_sig00000484
);
blk00000003_blk00000371 : XORCY
port map (
CI => blk00000003_sig0000047f,
LI => blk00000003_sig00000480,
O => blk00000003_sig00000481
);
blk00000003_blk00000370 : XORCY
port map (
CI => blk00000003_sig0000047c,
LI => blk00000003_sig0000047d,
O => blk00000003_sig0000047e
);
blk00000003_blk0000036f : XORCY
port map (
CI => blk00000003_sig00000479,
LI => blk00000003_sig0000047a,
O => blk00000003_sig0000047b
);
blk00000003_blk0000036e : XORCY
port map (
CI => blk00000003_sig00000476,
LI => blk00000003_sig00000477,
O => blk00000003_sig00000478
);
blk00000003_blk0000036d : XORCY
port map (
CI => blk00000003_sig00000473,
LI => blk00000003_sig00000474,
O => blk00000003_sig00000475
);
blk00000003_blk0000036c : XORCY
port map (
CI => blk00000003_sig00000470,
LI => blk00000003_sig00000471,
O => blk00000003_sig00000472
);
blk00000003_blk0000036b : XORCY
port map (
CI => blk00000003_sig0000046d,
LI => blk00000003_sig0000046e,
O => blk00000003_sig0000046f
);
blk00000003_blk0000036a : XORCY
port map (
CI => blk00000003_sig0000046a,
LI => blk00000003_sig0000046b,
O => blk00000003_sig0000046c
);
blk00000003_blk00000369 : XORCY
port map (
CI => blk00000003_sig00000467,
LI => blk00000003_sig00000468,
O => blk00000003_sig00000469
);
blk00000003_blk00000368 : XORCY
port map (
CI => blk00000003_sig00000464,
LI => blk00000003_sig00000465,
O => blk00000003_sig00000466
);
blk00000003_blk00000367 : XORCY
port map (
CI => blk00000003_sig00000461,
LI => blk00000003_sig00000462,
O => blk00000003_sig00000463
);
blk00000003_blk00000366 : XORCY
port map (
CI => blk00000003_sig0000045e,
LI => blk00000003_sig0000045f,
O => blk00000003_sig00000460
);
blk00000003_blk00000365 : XORCY
port map (
CI => blk00000003_sig0000045b,
LI => blk00000003_sig0000045c,
O => blk00000003_sig0000045d
);
blk00000003_blk00000364 : XORCY
port map (
CI => blk00000003_sig00000458,
LI => blk00000003_sig00000459,
O => blk00000003_sig0000045a
);
blk00000003_blk00000363 : XORCY
port map (
CI => blk00000003_sig00000455,
LI => blk00000003_sig00000456,
O => blk00000003_sig00000457
);
blk00000003_blk00000362 : XORCY
port map (
CI => blk00000003_sig00000452,
LI => blk00000003_sig00000453,
O => blk00000003_sig00000454
);
blk00000003_blk00000361 : XORCY
port map (
CI => blk00000003_sig0000044f,
LI => blk00000003_sig00000450,
O => blk00000003_sig00000451
);
blk00000003_blk00000360 : XORCY
port map (
CI => blk00000003_sig0000044c,
LI => blk00000003_sig0000044d,
O => blk00000003_sig0000044e
);
blk00000003_blk0000035f : XORCY
port map (
CI => blk00000003_sig00000449,
LI => blk00000003_sig0000044a,
O => blk00000003_sig0000044b
);
blk00000003_blk0000035e : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000443,
Q => blk00000003_sig00000448
);
blk00000003_blk0000035d : MUXCY
port map (
CI => blk00000003_sig00000444,
DI => blk00000003_sig00000447,
S => blk00000003_sig00000445,
O => blk00000003_sig00000428
);
blk00000003_blk0000035c : XORCY
port map (
CI => blk00000003_sig00000444,
LI => blk00000003_sig00000445,
O => blk00000003_sig00000446
);
blk00000003_blk0000035b : MUXCY
port map (
CI => blk00000003_sig000003e3,
DI => blk00000003_sig00000442,
S => blk00000003_sig000003e4,
O => blk00000003_sig00000443
);
blk00000003_blk0000035a : MUXCY
port map (
CI => blk00000003_sig00000428,
DI => blk00000003_sig00000441,
S => blk00000003_sig00000429,
O => blk00000003_sig00000425
);
blk00000003_blk00000359 : MUXCY
port map (
CI => blk00000003_sig00000425,
DI => blk00000003_sig00000440,
S => blk00000003_sig00000426,
O => blk00000003_sig00000422
);
blk00000003_blk00000358 : MUXCY
port map (
CI => blk00000003_sig00000422,
DI => blk00000003_sig0000043f,
S => blk00000003_sig00000423,
O => blk00000003_sig0000041f
);
blk00000003_blk00000357 : MUXCY
port map (
CI => blk00000003_sig0000041f,
DI => blk00000003_sig0000043e,
S => blk00000003_sig00000420,
O => blk00000003_sig0000041c
);
blk00000003_blk00000356 : MUXCY
port map (
CI => blk00000003_sig0000041c,
DI => blk00000003_sig0000043d,
S => blk00000003_sig0000041d,
O => blk00000003_sig00000419
);
blk00000003_blk00000355 : MUXCY
port map (
CI => blk00000003_sig00000419,
DI => blk00000003_sig0000043c,
S => blk00000003_sig0000041a,
O => blk00000003_sig00000416
);
blk00000003_blk00000354 : MUXCY
port map (
CI => blk00000003_sig00000416,
DI => blk00000003_sig0000043b,
S => blk00000003_sig00000417,
O => blk00000003_sig00000413
);
blk00000003_blk00000353 : MUXCY
port map (
CI => blk00000003_sig00000413,
DI => blk00000003_sig0000043a,
S => blk00000003_sig00000414,
O => blk00000003_sig00000410
);
blk00000003_blk00000352 : MUXCY
port map (
CI => blk00000003_sig00000410,
DI => blk00000003_sig00000439,
S => blk00000003_sig00000411,
O => blk00000003_sig0000040d
);
blk00000003_blk00000351 : MUXCY
port map (
CI => blk00000003_sig0000040d,
DI => blk00000003_sig00000438,
S => blk00000003_sig0000040e,
O => blk00000003_sig0000040a
);
blk00000003_blk00000350 : MUXCY
port map (
CI => blk00000003_sig0000040a,
DI => blk00000003_sig00000437,
S => blk00000003_sig0000040b,
O => blk00000003_sig00000407
);
blk00000003_blk0000034f : MUXCY
port map (
CI => blk00000003_sig00000407,
DI => blk00000003_sig00000436,
S => blk00000003_sig00000408,
O => blk00000003_sig00000404
);
blk00000003_blk0000034e : MUXCY
port map (
CI => blk00000003_sig00000404,
DI => blk00000003_sig00000435,
S => blk00000003_sig00000405,
O => blk00000003_sig00000401
);
blk00000003_blk0000034d : MUXCY
port map (
CI => blk00000003_sig00000401,
DI => blk00000003_sig00000434,
S => blk00000003_sig00000402,
O => blk00000003_sig000003fe
);
blk00000003_blk0000034c : MUXCY
port map (
CI => blk00000003_sig000003fe,
DI => blk00000003_sig00000433,
S => blk00000003_sig000003ff,
O => blk00000003_sig000003fb
);
blk00000003_blk0000034b : MUXCY
port map (
CI => blk00000003_sig000003fb,
DI => blk00000003_sig00000432,
S => blk00000003_sig000003fc,
O => blk00000003_sig000003f8
);
blk00000003_blk0000034a : MUXCY
port map (
CI => blk00000003_sig000003f8,
DI => blk00000003_sig00000431,
S => blk00000003_sig000003f9,
O => blk00000003_sig000003f5
);
blk00000003_blk00000349 : MUXCY
port map (
CI => blk00000003_sig000003f5,
DI => blk00000003_sig00000430,
S => blk00000003_sig000003f6,
O => blk00000003_sig000003f2
);
blk00000003_blk00000348 : MUXCY
port map (
CI => blk00000003_sig000003f2,
DI => blk00000003_sig0000042f,
S => blk00000003_sig000003f3,
O => blk00000003_sig000003ef
);
blk00000003_blk00000347 : MUXCY
port map (
CI => blk00000003_sig000003ef,
DI => blk00000003_sig0000042e,
S => blk00000003_sig000003f0,
O => blk00000003_sig000003ec
);
blk00000003_blk00000346 : MUXCY
port map (
CI => blk00000003_sig000003ec,
DI => blk00000003_sig0000042d,
S => blk00000003_sig000003ed,
O => blk00000003_sig000003e9
);
blk00000003_blk00000345 : MUXCY
port map (
CI => blk00000003_sig000003e9,
DI => blk00000003_sig0000042c,
S => blk00000003_sig000003ea,
O => blk00000003_sig000003e6
);
blk00000003_blk00000344 : MUXCY
port map (
CI => blk00000003_sig000003e6,
DI => blk00000003_sig0000042b,
S => blk00000003_sig000003e7,
O => blk00000003_sig000003e3
);
blk00000003_blk00000343 : XORCY
port map (
CI => blk00000003_sig00000428,
LI => blk00000003_sig00000429,
O => blk00000003_sig0000042a
);
blk00000003_blk00000342 : XORCY
port map (
CI => blk00000003_sig00000425,
LI => blk00000003_sig00000426,
O => blk00000003_sig00000427
);
blk00000003_blk00000341 : XORCY
port map (
CI => blk00000003_sig00000422,
LI => blk00000003_sig00000423,
O => blk00000003_sig00000424
);
blk00000003_blk00000340 : XORCY
port map (
CI => blk00000003_sig0000041f,
LI => blk00000003_sig00000420,
O => blk00000003_sig00000421
);
blk00000003_blk0000033f : XORCY
port map (
CI => blk00000003_sig0000041c,
LI => blk00000003_sig0000041d,
O => blk00000003_sig0000041e
);
blk00000003_blk0000033e : XORCY
port map (
CI => blk00000003_sig00000419,
LI => blk00000003_sig0000041a,
O => blk00000003_sig0000041b
);
blk00000003_blk0000033d : XORCY
port map (
CI => blk00000003_sig00000416,
LI => blk00000003_sig00000417,
O => blk00000003_sig00000418
);
blk00000003_blk0000033c : XORCY
port map (
CI => blk00000003_sig00000413,
LI => blk00000003_sig00000414,
O => blk00000003_sig00000415
);
blk00000003_blk0000033b : XORCY
port map (
CI => blk00000003_sig00000410,
LI => blk00000003_sig00000411,
O => blk00000003_sig00000412
);
blk00000003_blk0000033a : XORCY
port map (
CI => blk00000003_sig0000040d,
LI => blk00000003_sig0000040e,
O => blk00000003_sig0000040f
);
blk00000003_blk00000339 : XORCY
port map (
CI => blk00000003_sig0000040a,
LI => blk00000003_sig0000040b,
O => blk00000003_sig0000040c
);
blk00000003_blk00000338 : XORCY
port map (
CI => blk00000003_sig00000407,
LI => blk00000003_sig00000408,
O => blk00000003_sig00000409
);
blk00000003_blk00000337 : XORCY
port map (
CI => blk00000003_sig00000404,
LI => blk00000003_sig00000405,
O => blk00000003_sig00000406
);
blk00000003_blk00000336 : XORCY
port map (
CI => blk00000003_sig00000401,
LI => blk00000003_sig00000402,
O => blk00000003_sig00000403
);
blk00000003_blk00000335 : XORCY
port map (
CI => blk00000003_sig000003fe,
LI => blk00000003_sig000003ff,
O => blk00000003_sig00000400
);
blk00000003_blk00000334 : XORCY
port map (
CI => blk00000003_sig000003fb,
LI => blk00000003_sig000003fc,
O => blk00000003_sig000003fd
);
blk00000003_blk00000333 : XORCY
port map (
CI => blk00000003_sig000003f8,
LI => blk00000003_sig000003f9,
O => blk00000003_sig000003fa
);
blk00000003_blk00000332 : XORCY
port map (
CI => blk00000003_sig000003f5,
LI => blk00000003_sig000003f6,
O => blk00000003_sig000003f7
);
blk00000003_blk00000331 : XORCY
port map (
CI => blk00000003_sig000003f2,
LI => blk00000003_sig000003f3,
O => blk00000003_sig000003f4
);
blk00000003_blk00000330 : XORCY
port map (
CI => blk00000003_sig000003ef,
LI => blk00000003_sig000003f0,
O => blk00000003_sig000003f1
);
blk00000003_blk0000032f : XORCY
port map (
CI => blk00000003_sig000003ec,
LI => blk00000003_sig000003ed,
O => blk00000003_sig000003ee
);
blk00000003_blk0000032e : XORCY
port map (
CI => blk00000003_sig000003e9,
LI => blk00000003_sig000003ea,
O => blk00000003_sig000003eb
);
blk00000003_blk0000032d : XORCY
port map (
CI => blk00000003_sig000003e6,
LI => blk00000003_sig000003e7,
O => blk00000003_sig000003e8
);
blk00000003_blk0000032c : XORCY
port map (
CI => blk00000003_sig000003e3,
LI => blk00000003_sig000003e4,
O => blk00000003_sig000003e5
);
blk00000003_blk0000032b : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig000003dd,
Q => blk00000003_sig000003e2
);
blk00000003_blk0000032a : MUXCY
port map (
CI => blk00000003_sig000003de,
DI => blk00000003_sig000003e1,
S => blk00000003_sig000003df,
O => blk00000003_sig000003c2
);
blk00000003_blk00000329 : XORCY
port map (
CI => blk00000003_sig000003de,
LI => blk00000003_sig000003df,
O => blk00000003_sig000003e0
);
blk00000003_blk00000328 : MUXCY
port map (
CI => blk00000003_sig0000037d,
DI => blk00000003_sig000003dc,
S => blk00000003_sig0000037e,
O => blk00000003_sig000003dd
);
blk00000003_blk00000327 : MUXCY
port map (
CI => blk00000003_sig000003c2,
DI => blk00000003_sig000003db,
S => blk00000003_sig000003c3,
O => blk00000003_sig000003bf
);
blk00000003_blk00000326 : MUXCY
port map (
CI => blk00000003_sig000003bf,
DI => blk00000003_sig000003da,
S => blk00000003_sig000003c0,
O => blk00000003_sig000003bc
);
blk00000003_blk00000325 : MUXCY
port map (
CI => blk00000003_sig000003bc,
DI => blk00000003_sig000003d9,
S => blk00000003_sig000003bd,
O => blk00000003_sig000003b9
);
blk00000003_blk00000324 : MUXCY
port map (
CI => blk00000003_sig000003b9,
DI => blk00000003_sig000003d8,
S => blk00000003_sig000003ba,
O => blk00000003_sig000003b6
);
blk00000003_blk00000323 : MUXCY
port map (
CI => blk00000003_sig000003b6,
DI => blk00000003_sig000003d7,
S => blk00000003_sig000003b7,
O => blk00000003_sig000003b3
);
blk00000003_blk00000322 : MUXCY
port map (
CI => blk00000003_sig000003b3,
DI => blk00000003_sig000003d6,
S => blk00000003_sig000003b4,
O => blk00000003_sig000003b0
);
blk00000003_blk00000321 : MUXCY
port map (
CI => blk00000003_sig000003b0,
DI => blk00000003_sig000003d5,
S => blk00000003_sig000003b1,
O => blk00000003_sig000003ad
);
blk00000003_blk00000320 : MUXCY
port map (
CI => blk00000003_sig000003ad,
DI => blk00000003_sig000003d4,
S => blk00000003_sig000003ae,
O => blk00000003_sig000003aa
);
blk00000003_blk0000031f : MUXCY
port map (
CI => blk00000003_sig000003aa,
DI => blk00000003_sig000003d3,
S => blk00000003_sig000003ab,
O => blk00000003_sig000003a7
);
blk00000003_blk0000031e : MUXCY
port map (
CI => blk00000003_sig000003a7,
DI => blk00000003_sig000003d2,
S => blk00000003_sig000003a8,
O => blk00000003_sig000003a4
);
blk00000003_blk0000031d : MUXCY
port map (
CI => blk00000003_sig000003a4,
DI => blk00000003_sig000003d1,
S => blk00000003_sig000003a5,
O => blk00000003_sig000003a1
);
blk00000003_blk0000031c : MUXCY
port map (
CI => blk00000003_sig000003a1,
DI => blk00000003_sig000003d0,
S => blk00000003_sig000003a2,
O => blk00000003_sig0000039e
);
blk00000003_blk0000031b : MUXCY
port map (
CI => blk00000003_sig0000039e,
DI => blk00000003_sig000003cf,
S => blk00000003_sig0000039f,
O => blk00000003_sig0000039b
);
blk00000003_blk0000031a : MUXCY
port map (
CI => blk00000003_sig0000039b,
DI => blk00000003_sig000003ce,
S => blk00000003_sig0000039c,
O => blk00000003_sig00000398
);
blk00000003_blk00000319 : MUXCY
port map (
CI => blk00000003_sig00000398,
DI => blk00000003_sig000003cd,
S => blk00000003_sig00000399,
O => blk00000003_sig00000395
);
blk00000003_blk00000318 : MUXCY
port map (
CI => blk00000003_sig00000395,
DI => blk00000003_sig000003cc,
S => blk00000003_sig00000396,
O => blk00000003_sig00000392
);
blk00000003_blk00000317 : MUXCY
port map (
CI => blk00000003_sig00000392,
DI => blk00000003_sig000003cb,
S => blk00000003_sig00000393,
O => blk00000003_sig0000038f
);
blk00000003_blk00000316 : MUXCY
port map (
CI => blk00000003_sig0000038f,
DI => blk00000003_sig000003ca,
S => blk00000003_sig00000390,
O => blk00000003_sig0000038c
);
blk00000003_blk00000315 : MUXCY
port map (
CI => blk00000003_sig0000038c,
DI => blk00000003_sig000003c9,
S => blk00000003_sig0000038d,
O => blk00000003_sig00000389
);
blk00000003_blk00000314 : MUXCY
port map (
CI => blk00000003_sig00000389,
DI => blk00000003_sig000003c8,
S => blk00000003_sig0000038a,
O => blk00000003_sig00000386
);
blk00000003_blk00000313 : MUXCY
port map (
CI => blk00000003_sig00000386,
DI => blk00000003_sig000003c7,
S => blk00000003_sig00000387,
O => blk00000003_sig00000383
);
blk00000003_blk00000312 : MUXCY
port map (
CI => blk00000003_sig00000383,
DI => blk00000003_sig000003c6,
S => blk00000003_sig00000384,
O => blk00000003_sig00000380
);
blk00000003_blk00000311 : MUXCY
port map (
CI => blk00000003_sig00000380,
DI => blk00000003_sig000003c5,
S => blk00000003_sig00000381,
O => blk00000003_sig0000037d
);
blk00000003_blk00000310 : XORCY
port map (
CI => blk00000003_sig000003c2,
LI => blk00000003_sig000003c3,
O => blk00000003_sig000003c4
);
blk00000003_blk0000030f : XORCY
port map (
CI => blk00000003_sig000003bf,
LI => blk00000003_sig000003c0,
O => blk00000003_sig000003c1
);
blk00000003_blk0000030e : XORCY
port map (
CI => blk00000003_sig000003bc,
LI => blk00000003_sig000003bd,
O => blk00000003_sig000003be
);
blk00000003_blk0000030d : XORCY
port map (
CI => blk00000003_sig000003b9,
LI => blk00000003_sig000003ba,
O => blk00000003_sig000003bb
);
blk00000003_blk0000030c : XORCY
port map (
CI => blk00000003_sig000003b6,
LI => blk00000003_sig000003b7,
O => blk00000003_sig000003b8
);
blk00000003_blk0000030b : XORCY
port map (
CI => blk00000003_sig000003b3,
LI => blk00000003_sig000003b4,
O => blk00000003_sig000003b5
);
blk00000003_blk0000030a : XORCY
port map (
CI => blk00000003_sig000003b0,
LI => blk00000003_sig000003b1,
O => blk00000003_sig000003b2
);
blk00000003_blk00000309 : XORCY
port map (
CI => blk00000003_sig000003ad,
LI => blk00000003_sig000003ae,
O => blk00000003_sig000003af
);
blk00000003_blk00000308 : XORCY
port map (
CI => blk00000003_sig000003aa,
LI => blk00000003_sig000003ab,
O => blk00000003_sig000003ac
);
blk00000003_blk00000307 : XORCY
port map (
CI => blk00000003_sig000003a7,
LI => blk00000003_sig000003a8,
O => blk00000003_sig000003a9
);
blk00000003_blk00000306 : XORCY
port map (
CI => blk00000003_sig000003a4,
LI => blk00000003_sig000003a5,
O => blk00000003_sig000003a6
);
blk00000003_blk00000305 : XORCY
port map (
CI => blk00000003_sig000003a1,
LI => blk00000003_sig000003a2,
O => blk00000003_sig000003a3
);
blk00000003_blk00000304 : XORCY
port map (
CI => blk00000003_sig0000039e,
LI => blk00000003_sig0000039f,
O => blk00000003_sig000003a0
);
blk00000003_blk00000303 : XORCY
port map (
CI => blk00000003_sig0000039b,
LI => blk00000003_sig0000039c,
O => blk00000003_sig0000039d
);
blk00000003_blk00000302 : XORCY
port map (
CI => blk00000003_sig00000398,
LI => blk00000003_sig00000399,
O => blk00000003_sig0000039a
);
blk00000003_blk00000301 : XORCY
port map (
CI => blk00000003_sig00000395,
LI => blk00000003_sig00000396,
O => blk00000003_sig00000397
);
blk00000003_blk00000300 : XORCY
port map (
CI => blk00000003_sig00000392,
LI => blk00000003_sig00000393,
O => blk00000003_sig00000394
);
blk00000003_blk000002ff : XORCY
port map (
CI => blk00000003_sig0000038f,
LI => blk00000003_sig00000390,
O => blk00000003_sig00000391
);
blk00000003_blk000002fe : XORCY
port map (
CI => blk00000003_sig0000038c,
LI => blk00000003_sig0000038d,
O => blk00000003_sig0000038e
);
blk00000003_blk000002fd : XORCY
port map (
CI => blk00000003_sig00000389,
LI => blk00000003_sig0000038a,
O => blk00000003_sig0000038b
);
blk00000003_blk000002fc : XORCY
port map (
CI => blk00000003_sig00000386,
LI => blk00000003_sig00000387,
O => blk00000003_sig00000388
);
blk00000003_blk000002fb : XORCY
port map (
CI => blk00000003_sig00000383,
LI => blk00000003_sig00000384,
O => blk00000003_sig00000385
);
blk00000003_blk000002fa : XORCY
port map (
CI => blk00000003_sig00000380,
LI => blk00000003_sig00000381,
O => blk00000003_sig00000382
);
blk00000003_blk000002f9 : XORCY
port map (
CI => blk00000003_sig0000037d,
LI => blk00000003_sig0000037e,
O => blk00000003_sig0000037f
);
blk00000003_blk000002f8 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000379,
Q => blk00000003_sig0000037c
);
blk00000003_blk000002f7 : MUXCY
port map (
CI => NlwRenamedSig_OI_rfd,
DI => blk00000003_sig000000c2,
S => blk00000003_sig0000037a,
O => blk00000003_sig00000376
);
blk00000003_blk000002f6 : XORCY
port map (
CI => NlwRenamedSig_OI_rfd,
LI => blk00000003_sig0000037a,
O => blk00000003_sig0000037b
);
blk00000003_blk000002f5 : MUXCY
port map (
CI => blk00000003_sig00000332,
DI => blk00000003_sig00000062,
S => NlwRenamedSig_OI_rfd,
O => blk00000003_sig00000379
);
blk00000003_blk000002f4 : MUXCY
port map (
CI => blk00000003_sig00000376,
DI => blk00000003_sig00000062,
S => blk00000003_sig00000377,
O => blk00000003_sig00000373
);
blk00000003_blk000002f3 : MUXCY
port map (
CI => blk00000003_sig00000373,
DI => blk00000003_sig00000062,
S => blk00000003_sig00000374,
O => blk00000003_sig00000370
);
blk00000003_blk000002f2 : MUXCY
port map (
CI => blk00000003_sig00000370,
DI => blk00000003_sig00000062,
S => blk00000003_sig00000371,
O => blk00000003_sig0000036d
);
blk00000003_blk000002f1 : MUXCY
port map (
CI => blk00000003_sig0000036d,
DI => blk00000003_sig00000062,
S => blk00000003_sig0000036e,
O => blk00000003_sig0000036a
);
blk00000003_blk000002f0 : MUXCY
port map (
CI => blk00000003_sig0000036a,
DI => blk00000003_sig00000062,
S => blk00000003_sig0000036b,
O => blk00000003_sig00000367
);
blk00000003_blk000002ef : MUXCY
port map (
CI => blk00000003_sig00000367,
DI => blk00000003_sig00000062,
S => blk00000003_sig00000368,
O => blk00000003_sig00000364
);
blk00000003_blk000002ee : MUXCY
port map (
CI => blk00000003_sig00000364,
DI => blk00000003_sig00000062,
S => blk00000003_sig00000365,
O => blk00000003_sig00000361
);
blk00000003_blk000002ed : MUXCY
port map (
CI => blk00000003_sig00000361,
DI => blk00000003_sig00000062,
S => blk00000003_sig00000362,
O => blk00000003_sig0000035e
);
blk00000003_blk000002ec : MUXCY
port map (
CI => blk00000003_sig0000035e,
DI => blk00000003_sig00000062,
S => blk00000003_sig0000035f,
O => blk00000003_sig0000035b
);
blk00000003_blk000002eb : MUXCY
port map (
CI => blk00000003_sig0000035b,
DI => blk00000003_sig00000062,
S => blk00000003_sig0000035c,
O => blk00000003_sig00000358
);
blk00000003_blk000002ea : MUXCY
port map (
CI => blk00000003_sig00000358,
DI => blk00000003_sig00000062,
S => blk00000003_sig00000359,
O => blk00000003_sig00000355
);
blk00000003_blk000002e9 : MUXCY
port map (
CI => blk00000003_sig00000355,
DI => blk00000003_sig00000062,
S => blk00000003_sig00000356,
O => blk00000003_sig00000352
);
blk00000003_blk000002e8 : MUXCY
port map (
CI => blk00000003_sig00000352,
DI => blk00000003_sig00000062,
S => blk00000003_sig00000353,
O => blk00000003_sig0000034f
);
blk00000003_blk000002e7 : MUXCY
port map (
CI => blk00000003_sig0000034f,
DI => blk00000003_sig00000062,
S => blk00000003_sig00000350,
O => blk00000003_sig0000034c
);
blk00000003_blk000002e6 : MUXCY
port map (
CI => blk00000003_sig0000034c,
DI => blk00000003_sig00000062,
S => blk00000003_sig0000034d,
O => blk00000003_sig00000349
);
blk00000003_blk000002e5 : MUXCY
port map (
CI => blk00000003_sig00000349,
DI => blk00000003_sig00000062,
S => blk00000003_sig0000034a,
O => blk00000003_sig00000346
);
blk00000003_blk000002e4 : MUXCY
port map (
CI => blk00000003_sig00000346,
DI => blk00000003_sig00000062,
S => blk00000003_sig00000347,
O => blk00000003_sig00000343
);
blk00000003_blk000002e3 : MUXCY
port map (
CI => blk00000003_sig00000343,
DI => blk00000003_sig00000062,
S => blk00000003_sig00000344,
O => blk00000003_sig00000340
);
blk00000003_blk000002e2 : MUXCY
port map (
CI => blk00000003_sig00000340,
DI => blk00000003_sig00000062,
S => blk00000003_sig00000341,
O => blk00000003_sig0000033d
);
blk00000003_blk000002e1 : MUXCY
port map (
CI => blk00000003_sig0000033d,
DI => blk00000003_sig00000062,
S => blk00000003_sig0000033e,
O => blk00000003_sig0000033a
);
blk00000003_blk000002e0 : MUXCY
port map (
CI => blk00000003_sig0000033a,
DI => blk00000003_sig00000062,
S => blk00000003_sig0000033b,
O => blk00000003_sig00000337
);
blk00000003_blk000002df : MUXCY
port map (
CI => blk00000003_sig00000337,
DI => blk00000003_sig00000062,
S => blk00000003_sig00000338,
O => blk00000003_sig00000334
);
blk00000003_blk000002de : MUXCY
port map (
CI => blk00000003_sig00000334,
DI => blk00000003_sig00000062,
S => blk00000003_sig00000335,
O => blk00000003_sig00000332
);
blk00000003_blk000002dd : XORCY
port map (
CI => blk00000003_sig00000376,
LI => blk00000003_sig00000377,
O => blk00000003_sig00000378
);
blk00000003_blk000002dc : XORCY
port map (
CI => blk00000003_sig00000373,
LI => blk00000003_sig00000374,
O => blk00000003_sig00000375
);
blk00000003_blk000002db : XORCY
port map (
CI => blk00000003_sig00000370,
LI => blk00000003_sig00000371,
O => blk00000003_sig00000372
);
blk00000003_blk000002da : XORCY
port map (
CI => blk00000003_sig0000036d,
LI => blk00000003_sig0000036e,
O => blk00000003_sig0000036f
);
blk00000003_blk000002d9 : XORCY
port map (
CI => blk00000003_sig0000036a,
LI => blk00000003_sig0000036b,
O => blk00000003_sig0000036c
);
blk00000003_blk000002d8 : XORCY
port map (
CI => blk00000003_sig00000367,
LI => blk00000003_sig00000368,
O => blk00000003_sig00000369
);
blk00000003_blk000002d7 : XORCY
port map (
CI => blk00000003_sig00000364,
LI => blk00000003_sig00000365,
O => blk00000003_sig00000366
);
blk00000003_blk000002d6 : XORCY
port map (
CI => blk00000003_sig00000361,
LI => blk00000003_sig00000362,
O => blk00000003_sig00000363
);
blk00000003_blk000002d5 : XORCY
port map (
CI => blk00000003_sig0000035e,
LI => blk00000003_sig0000035f,
O => blk00000003_sig00000360
);
blk00000003_blk000002d4 : XORCY
port map (
CI => blk00000003_sig0000035b,
LI => blk00000003_sig0000035c,
O => blk00000003_sig0000035d
);
blk00000003_blk000002d3 : XORCY
port map (
CI => blk00000003_sig00000358,
LI => blk00000003_sig00000359,
O => blk00000003_sig0000035a
);
blk00000003_blk000002d2 : XORCY
port map (
CI => blk00000003_sig00000355,
LI => blk00000003_sig00000356,
O => blk00000003_sig00000357
);
blk00000003_blk000002d1 : XORCY
port map (
CI => blk00000003_sig00000352,
LI => blk00000003_sig00000353,
O => blk00000003_sig00000354
);
blk00000003_blk000002d0 : XORCY
port map (
CI => blk00000003_sig0000034f,
LI => blk00000003_sig00000350,
O => blk00000003_sig00000351
);
blk00000003_blk000002cf : XORCY
port map (
CI => blk00000003_sig0000034c,
LI => blk00000003_sig0000034d,
O => blk00000003_sig0000034e
);
blk00000003_blk000002ce : XORCY
port map (
CI => blk00000003_sig00000349,
LI => blk00000003_sig0000034a,
O => blk00000003_sig0000034b
);
blk00000003_blk000002cd : XORCY
port map (
CI => blk00000003_sig00000346,
LI => blk00000003_sig00000347,
O => blk00000003_sig00000348
);
blk00000003_blk000002cc : XORCY
port map (
CI => blk00000003_sig00000343,
LI => blk00000003_sig00000344,
O => blk00000003_sig00000345
);
blk00000003_blk000002cb : XORCY
port map (
CI => blk00000003_sig00000340,
LI => blk00000003_sig00000341,
O => blk00000003_sig00000342
);
blk00000003_blk000002ca : XORCY
port map (
CI => blk00000003_sig0000033d,
LI => blk00000003_sig0000033e,
O => blk00000003_sig0000033f
);
blk00000003_blk000002c9 : XORCY
port map (
CI => blk00000003_sig0000033a,
LI => blk00000003_sig0000033b,
O => blk00000003_sig0000033c
);
blk00000003_blk000002c8 : XORCY
port map (
CI => blk00000003_sig00000337,
LI => blk00000003_sig00000338,
O => blk00000003_sig00000339
);
blk00000003_blk000002c7 : XORCY
port map (
CI => blk00000003_sig00000334,
LI => blk00000003_sig00000335,
O => blk00000003_sig00000336
);
blk00000003_blk000002c6 : XORCY
port map (
CI => blk00000003_sig00000332,
LI => NlwRenamedSig_OI_rfd,
O => blk00000003_sig00000333
);
blk00000003_blk000002c5 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => divisor_1(0),
Q => blk00000003_sig00000331
);
blk00000003_blk000002c4 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => divisor_1(1),
Q => blk00000003_sig00000330
);
blk00000003_blk000002c3 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => divisor_1(2),
Q => blk00000003_sig0000032f
);
blk00000003_blk000002c2 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => divisor_1(3),
Q => blk00000003_sig0000032e
);
blk00000003_blk000002c1 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => divisor_1(4),
Q => blk00000003_sig0000032d
);
blk00000003_blk000002c0 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => divisor_1(5),
Q => blk00000003_sig0000032c
);
blk00000003_blk000002bf : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => divisor_1(6),
Q => blk00000003_sig0000032b
);
blk00000003_blk000002be : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => divisor_1(7),
Q => blk00000003_sig0000032a
);
blk00000003_blk000002bd : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => divisor_1(8),
Q => blk00000003_sig00000329
);
blk00000003_blk000002bc : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => divisor_1(9),
Q => blk00000003_sig00000328
);
blk00000003_blk000002bb : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => divisor_1(10),
Q => blk00000003_sig00000327
);
blk00000003_blk000002ba : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => divisor_1(11),
Q => blk00000003_sig00000326
);
blk00000003_blk000002b9 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => divisor_1(12),
Q => blk00000003_sig00000325
);
blk00000003_blk000002b8 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => divisor_1(13),
Q => blk00000003_sig00000324
);
blk00000003_blk000002b7 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => divisor_1(14),
Q => blk00000003_sig00000323
);
blk00000003_blk000002b6 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => divisor_1(15),
Q => blk00000003_sig00000322
);
blk00000003_blk000002b5 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => divisor_1(16),
Q => blk00000003_sig00000321
);
blk00000003_blk000002b4 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => divisor_1(17),
Q => blk00000003_sig00000320
);
blk00000003_blk000002b3 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => divisor_1(18),
Q => blk00000003_sig0000031f
);
blk00000003_blk000002b2 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => divisor_1(19),
Q => blk00000003_sig0000031e
);
blk00000003_blk000002b1 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => divisor_1(20),
Q => blk00000003_sig0000031d
);
blk00000003_blk000002b0 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => divisor_1(21),
Q => blk00000003_sig0000031c
);
blk00000003_blk000002af : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => divisor_1(22),
Q => blk00000003_sig0000031b
);
blk00000003_blk000002ae : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => divisor_1(23),
Q => blk00000003_sig0000031a
);
blk00000003_blk000002ad : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000331,
Q => blk00000003_sig00000319
);
blk00000003_blk000002ac : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000330,
Q => blk00000003_sig00000318
);
blk00000003_blk000002ab : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig0000032f,
Q => blk00000003_sig00000317
);
blk00000003_blk000002aa : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig0000032e,
Q => blk00000003_sig00000316
);
blk00000003_blk000002a9 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig0000032d,
Q => blk00000003_sig00000315
);
blk00000003_blk000002a8 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig0000032c,
Q => blk00000003_sig00000314
);
blk00000003_blk000002a7 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig0000032b,
Q => blk00000003_sig00000313
);
blk00000003_blk000002a6 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig0000032a,
Q => blk00000003_sig00000312
);
blk00000003_blk000002a5 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000329,
Q => blk00000003_sig00000311
);
blk00000003_blk000002a4 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000328,
Q => blk00000003_sig00000310
);
blk00000003_blk000002a3 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000327,
Q => blk00000003_sig0000030f
);
blk00000003_blk000002a2 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000326,
Q => blk00000003_sig0000030e
);
blk00000003_blk000002a1 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000325,
Q => blk00000003_sig0000030d
);
blk00000003_blk000002a0 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000324,
Q => blk00000003_sig0000030c
);
blk00000003_blk0000029f : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000323,
Q => blk00000003_sig0000030b
);
blk00000003_blk0000029e : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000322,
Q => blk00000003_sig0000030a
);
blk00000003_blk0000029d : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000321,
Q => blk00000003_sig00000309
);
blk00000003_blk0000029c : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000320,
Q => blk00000003_sig00000308
);
blk00000003_blk0000029b : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig0000031f,
Q => blk00000003_sig00000307
);
blk00000003_blk0000029a : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig0000031e,
Q => blk00000003_sig00000306
);
blk00000003_blk00000299 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig0000031d,
Q => blk00000003_sig00000305
);
blk00000003_blk00000298 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig0000031c,
Q => blk00000003_sig00000304
);
blk00000003_blk00000297 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig0000031b,
Q => blk00000003_sig00000303
);
blk00000003_blk00000296 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig0000031a,
Q => blk00000003_sig00000302
);
blk00000003_blk00000295 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000319,
Q => blk00000003_sig00000301
);
blk00000003_blk00000294 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000318,
Q => blk00000003_sig00000300
);
blk00000003_blk00000293 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000317,
Q => blk00000003_sig000002ff
);
blk00000003_blk00000292 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000316,
Q => blk00000003_sig000002fe
);
blk00000003_blk00000291 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000315,
Q => blk00000003_sig000002fd
);
blk00000003_blk00000290 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000314,
Q => blk00000003_sig000002fc
);
blk00000003_blk0000028f : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000313,
Q => blk00000003_sig000002fb
);
blk00000003_blk0000028e : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000312,
Q => blk00000003_sig000002fa
);
blk00000003_blk0000028d : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000311,
Q => blk00000003_sig000002f9
);
blk00000003_blk0000028c : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000310,
Q => blk00000003_sig000002f8
);
blk00000003_blk0000028b : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig0000030f,
Q => blk00000003_sig000002f7
);
blk00000003_blk0000028a : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig0000030e,
Q => blk00000003_sig000002f6
);
blk00000003_blk00000289 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig0000030d,
Q => blk00000003_sig000002f5
);
blk00000003_blk00000288 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig0000030c,
Q => blk00000003_sig000002f4
);
blk00000003_blk00000287 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig0000030b,
Q => blk00000003_sig000002f3
);
blk00000003_blk00000286 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig0000030a,
Q => blk00000003_sig000002f2
);
blk00000003_blk00000285 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000309,
Q => blk00000003_sig000002f1
);
blk00000003_blk00000284 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000308,
Q => blk00000003_sig000002f0
);
blk00000003_blk00000283 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000307,
Q => blk00000003_sig000002ef
);
blk00000003_blk00000282 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000306,
Q => blk00000003_sig000002ee
);
blk00000003_blk00000281 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000305,
Q => blk00000003_sig000002ed
);
blk00000003_blk00000280 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000304,
Q => blk00000003_sig000002ec
);
blk00000003_blk0000027f : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000303,
Q => blk00000003_sig000002eb
);
blk00000003_blk0000027e : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000302,
Q => blk00000003_sig000002ea
);
blk00000003_blk0000027d : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000301,
Q => blk00000003_sig000002e9
);
blk00000003_blk0000027c : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000300,
Q => blk00000003_sig000002e8
);
blk00000003_blk0000027b : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig000002ff,
Q => blk00000003_sig000002e7
);
blk00000003_blk0000027a : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig000002fe,
Q => blk00000003_sig000002e6
);
blk00000003_blk00000279 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig000002fd,
Q => blk00000003_sig000002e5
);
blk00000003_blk00000278 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig000002fc,
Q => blk00000003_sig000002e4
);
blk00000003_blk00000277 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig000002fb,
Q => blk00000003_sig000002e3
);
blk00000003_blk00000276 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig000002fa,
Q => blk00000003_sig000002e2
);
blk00000003_blk00000275 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig000002f9,
Q => blk00000003_sig000002e1
);
blk00000003_blk00000274 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig000002f8,
Q => blk00000003_sig000002e0
);
blk00000003_blk00000273 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig000002f7,
Q => blk00000003_sig000002df
);
blk00000003_blk00000272 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig000002f6,
Q => blk00000003_sig000002de
);
blk00000003_blk00000271 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig000002f5,
Q => blk00000003_sig000002dd
);
blk00000003_blk00000270 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig000002f4,
Q => blk00000003_sig000002dc
);
blk00000003_blk0000026f : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig000002f3,
Q => blk00000003_sig000002db
);
blk00000003_blk0000026e : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig000002f2,
Q => blk00000003_sig000002da
);
blk00000003_blk0000026d : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig000002f1,
Q => blk00000003_sig000002d9
);
blk00000003_blk0000026c : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig000002f0,
Q => blk00000003_sig000002d8
);
blk00000003_blk0000026b : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig000002ef,
Q => blk00000003_sig000002d7
);
blk00000003_blk0000026a : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig000002ee,
Q => blk00000003_sig000002d6
);
blk00000003_blk00000269 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig000002ed,
Q => blk00000003_sig000002d5
);
blk00000003_blk00000268 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig000002ec,
Q => blk00000003_sig000002d4
);
blk00000003_blk00000267 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig000002eb,
Q => blk00000003_sig000002d3
);
blk00000003_blk00000266 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig000002ea,
Q => blk00000003_sig000002d2
);
blk00000003_blk00000265 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig000002e9,
Q => blk00000003_sig000002d1
);
blk00000003_blk00000264 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig000002e8,
Q => blk00000003_sig000002d0
);
blk00000003_blk00000263 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig000002e7,
Q => blk00000003_sig000002cf
);
blk00000003_blk00000262 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig000002e6,
Q => blk00000003_sig000002ce
);
blk00000003_blk00000261 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig000002e5,
Q => blk00000003_sig000002cd
);
blk00000003_blk00000260 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig000002e4,
Q => blk00000003_sig000002cc
);
blk00000003_blk0000025f : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig000002e3,
Q => blk00000003_sig000002cb
);
blk00000003_blk0000025e : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig000002e2,
Q => blk00000003_sig000002ca
);
blk00000003_blk0000025d : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig000002e1,
Q => blk00000003_sig000002c9
);
blk00000003_blk0000025c : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig000002e0,
Q => blk00000003_sig000002c8
);
blk00000003_blk0000025b : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig000002df,
Q => blk00000003_sig000002c7
);
blk00000003_blk0000025a : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig000002de,
Q => blk00000003_sig000002c6
);
blk00000003_blk00000259 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig000002dd,
Q => blk00000003_sig000002c5
);
blk00000003_blk00000258 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig000002dc,
Q => blk00000003_sig000002c4
);
blk00000003_blk00000257 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig000002db,
Q => blk00000003_sig000002c3
);
blk00000003_blk00000256 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig000002da,
Q => blk00000003_sig000002c2
);
blk00000003_blk00000255 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig000002d9,
Q => blk00000003_sig000002c1
);
blk00000003_blk00000254 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig000002d8,
Q => blk00000003_sig000002c0
);
blk00000003_blk00000253 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig000002d7,
Q => blk00000003_sig000002bf
);
blk00000003_blk00000252 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig000002d6,
Q => blk00000003_sig000002be
);
blk00000003_blk00000251 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig000002d5,
Q => blk00000003_sig000002bd
);
blk00000003_blk00000250 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig000002d4,
Q => blk00000003_sig000002bc
);
blk00000003_blk0000024f : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig000002d3,
Q => blk00000003_sig000002bb
);
blk00000003_blk0000024e : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig000002d2,
Q => blk00000003_sig000002ba
);
blk00000003_blk0000024d : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig000002d1,
Q => blk00000003_sig000002b9
);
blk00000003_blk0000024c : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig000002d0,
Q => blk00000003_sig000002b8
);
blk00000003_blk0000024b : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig000002cf,
Q => blk00000003_sig000002b7
);
blk00000003_blk0000024a : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig000002ce,
Q => blk00000003_sig000002b6
);
blk00000003_blk00000249 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig000002cd,
Q => blk00000003_sig000002b5
);
blk00000003_blk00000248 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig000002cc,
Q => blk00000003_sig000002b4
);
blk00000003_blk00000247 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig000002cb,
Q => blk00000003_sig000002b3
);
blk00000003_blk00000246 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig000002ca,
Q => blk00000003_sig000002b2
);
blk00000003_blk00000245 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig000002c9,
Q => blk00000003_sig000002b1
);
blk00000003_blk00000244 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig000002c8,
Q => blk00000003_sig000002b0
);
blk00000003_blk00000243 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig000002c7,
Q => blk00000003_sig000002af
);
blk00000003_blk00000242 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig000002c6,
Q => blk00000003_sig000002ae
);
blk00000003_blk00000241 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig000002c5,
Q => blk00000003_sig000002ad
);
blk00000003_blk00000240 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig000002c4,
Q => blk00000003_sig000002ac
);
blk00000003_blk0000023f : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig000002c3,
Q => blk00000003_sig000002ab
);
blk00000003_blk0000023e : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig000002c2,
Q => blk00000003_sig000002aa
);
blk00000003_blk0000023d : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig000002c1,
Q => blk00000003_sig000002a9
);
blk00000003_blk0000023c : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig000002c0,
Q => blk00000003_sig000002a8
);
blk00000003_blk0000023b : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig000002bf,
Q => blk00000003_sig000002a7
);
blk00000003_blk0000023a : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig000002be,
Q => blk00000003_sig000002a6
);
blk00000003_blk00000239 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig000002bd,
Q => blk00000003_sig000002a5
);
blk00000003_blk00000238 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig000002bc,
Q => blk00000003_sig000002a4
);
blk00000003_blk00000237 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig000002bb,
Q => blk00000003_sig000002a3
);
blk00000003_blk00000236 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig000002ba,
Q => blk00000003_sig000002a2
);
blk00000003_blk00000235 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig000002b9,
Q => blk00000003_sig000002a1
);
blk00000003_blk00000234 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig000002b8,
Q => blk00000003_sig000002a0
);
blk00000003_blk00000233 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig000002b7,
Q => blk00000003_sig0000029f
);
blk00000003_blk00000232 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig000002b6,
Q => blk00000003_sig0000029e
);
blk00000003_blk00000231 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig000002b5,
Q => blk00000003_sig0000029d
);
blk00000003_blk00000230 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig000002b4,
Q => blk00000003_sig0000029c
);
blk00000003_blk0000022f : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig000002b3,
Q => blk00000003_sig0000029b
);
blk00000003_blk0000022e : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig000002b2,
Q => blk00000003_sig0000029a
);
blk00000003_blk0000022d : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig000002b1,
Q => blk00000003_sig00000299
);
blk00000003_blk0000022c : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig000002b0,
Q => blk00000003_sig00000298
);
blk00000003_blk0000022b : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig000002af,
Q => blk00000003_sig00000297
);
blk00000003_blk0000022a : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig000002ae,
Q => blk00000003_sig00000296
);
blk00000003_blk00000229 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig000002ad,
Q => blk00000003_sig00000295
);
blk00000003_blk00000228 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig000002ac,
Q => blk00000003_sig00000294
);
blk00000003_blk00000227 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig000002ab,
Q => blk00000003_sig00000293
);
blk00000003_blk00000226 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig000002aa,
Q => blk00000003_sig00000292
);
blk00000003_blk00000225 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig000002a9,
Q => blk00000003_sig00000291
);
blk00000003_blk00000224 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig000002a8,
Q => blk00000003_sig00000290
);
blk00000003_blk00000223 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig000002a7,
Q => blk00000003_sig0000028f
);
blk00000003_blk00000222 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig000002a6,
Q => blk00000003_sig0000028e
);
blk00000003_blk00000221 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig000002a5,
Q => blk00000003_sig0000028d
);
blk00000003_blk00000220 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig000002a4,
Q => blk00000003_sig0000028c
);
blk00000003_blk0000021f : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig000002a3,
Q => blk00000003_sig0000028b
);
blk00000003_blk0000021e : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig000002a2,
Q => blk00000003_sig0000028a
);
blk00000003_blk0000021d : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig000002a1,
Q => blk00000003_sig00000289
);
blk00000003_blk0000021c : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig000002a0,
Q => blk00000003_sig00000288
);
blk00000003_blk0000021b : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig0000029f,
Q => blk00000003_sig00000287
);
blk00000003_blk0000021a : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig0000029e,
Q => blk00000003_sig00000286
);
blk00000003_blk00000219 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig0000029d,
Q => blk00000003_sig00000285
);
blk00000003_blk00000218 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig0000029c,
Q => blk00000003_sig00000284
);
blk00000003_blk00000217 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig0000029b,
Q => blk00000003_sig00000283
);
blk00000003_blk00000216 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig0000029a,
Q => blk00000003_sig00000282
);
blk00000003_blk00000215 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000299,
Q => blk00000003_sig00000281
);
blk00000003_blk00000214 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000298,
Q => blk00000003_sig00000280
);
blk00000003_blk00000213 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000297,
Q => blk00000003_sig0000027f
);
blk00000003_blk00000212 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000296,
Q => blk00000003_sig0000027e
);
blk00000003_blk00000211 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000295,
Q => blk00000003_sig0000027d
);
blk00000003_blk00000210 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000294,
Q => blk00000003_sig0000027c
);
blk00000003_blk0000020f : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000293,
Q => blk00000003_sig0000027b
);
blk00000003_blk0000020e : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000292,
Q => blk00000003_sig0000027a
);
blk00000003_blk0000020d : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000291,
Q => blk00000003_sig00000279
);
blk00000003_blk0000020c : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000290,
Q => blk00000003_sig00000278
);
blk00000003_blk0000020b : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig0000028f,
Q => blk00000003_sig00000277
);
blk00000003_blk0000020a : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig0000028e,
Q => blk00000003_sig00000276
);
blk00000003_blk00000209 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig0000028d,
Q => blk00000003_sig00000275
);
blk00000003_blk00000208 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig0000028c,
Q => blk00000003_sig00000274
);
blk00000003_blk00000207 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig0000028b,
Q => blk00000003_sig00000273
);
blk00000003_blk00000206 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig0000028a,
Q => blk00000003_sig00000272
);
blk00000003_blk00000205 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000289,
Q => blk00000003_sig00000271
);
blk00000003_blk00000204 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000288,
Q => blk00000003_sig00000270
);
blk00000003_blk00000203 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000287,
Q => blk00000003_sig0000026f
);
blk00000003_blk00000202 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000286,
Q => blk00000003_sig0000026e
);
blk00000003_blk00000201 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000285,
Q => blk00000003_sig0000026d
);
blk00000003_blk00000200 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000284,
Q => blk00000003_sig0000026c
);
blk00000003_blk000001ff : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000283,
Q => blk00000003_sig0000026b
);
blk00000003_blk000001fe : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000282,
Q => blk00000003_sig0000026a
);
blk00000003_blk000001fd : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000281,
Q => blk00000003_sig00000269
);
blk00000003_blk000001fc : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000280,
Q => blk00000003_sig00000268
);
blk00000003_blk000001fb : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig0000027f,
Q => blk00000003_sig00000267
);
blk00000003_blk000001fa : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig0000027e,
Q => blk00000003_sig00000266
);
blk00000003_blk000001f9 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig0000027d,
Q => blk00000003_sig00000265
);
blk00000003_blk000001f8 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig0000027c,
Q => blk00000003_sig00000264
);
blk00000003_blk000001f7 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig0000027b,
Q => blk00000003_sig00000263
);
blk00000003_blk000001f6 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig0000027a,
Q => blk00000003_sig00000262
);
blk00000003_blk000001f5 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000279,
Q => blk00000003_sig00000261
);
blk00000003_blk000001f4 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000278,
Q => blk00000003_sig00000260
);
blk00000003_blk000001f3 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000277,
Q => blk00000003_sig0000025f
);
blk00000003_blk000001f2 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000276,
Q => blk00000003_sig0000025e
);
blk00000003_blk000001f1 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000275,
Q => blk00000003_sig0000025d
);
blk00000003_blk000001f0 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000274,
Q => blk00000003_sig0000025c
);
blk00000003_blk000001ef : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000273,
Q => blk00000003_sig0000025b
);
blk00000003_blk000001ee : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000272,
Q => blk00000003_sig0000025a
);
blk00000003_blk000001ed : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000271,
Q => blk00000003_sig00000259
);
blk00000003_blk000001ec : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000270,
Q => blk00000003_sig00000258
);
blk00000003_blk000001eb : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig0000026f,
Q => blk00000003_sig00000257
);
blk00000003_blk000001ea : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig0000026e,
Q => blk00000003_sig00000256
);
blk00000003_blk000001e9 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig0000026d,
Q => blk00000003_sig00000255
);
blk00000003_blk000001e8 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig0000026c,
Q => blk00000003_sig00000254
);
blk00000003_blk000001e7 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig0000026b,
Q => blk00000003_sig00000253
);
blk00000003_blk000001e6 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig0000026a,
Q => blk00000003_sig00000252
);
blk00000003_blk000001e5 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000269,
Q => blk00000003_sig00000251
);
blk00000003_blk000001e4 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000268,
Q => blk00000003_sig00000250
);
blk00000003_blk000001e3 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000267,
Q => blk00000003_sig0000024f
);
blk00000003_blk000001e2 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000266,
Q => blk00000003_sig0000024e
);
blk00000003_blk000001e1 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000265,
Q => blk00000003_sig0000024d
);
blk00000003_blk000001e0 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000264,
Q => blk00000003_sig0000024c
);
blk00000003_blk000001df : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000263,
Q => blk00000003_sig0000024b
);
blk00000003_blk000001de : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000262,
Q => blk00000003_sig0000024a
);
blk00000003_blk000001dd : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000261,
Q => blk00000003_sig00000249
);
blk00000003_blk000001dc : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000260,
Q => blk00000003_sig00000248
);
blk00000003_blk000001db : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig0000025f,
Q => blk00000003_sig00000247
);
blk00000003_blk000001da : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig0000025e,
Q => blk00000003_sig00000246
);
blk00000003_blk000001d9 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig0000025d,
Q => blk00000003_sig00000245
);
blk00000003_blk000001d8 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig0000025c,
Q => blk00000003_sig00000244
);
blk00000003_blk000001d7 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig0000025b,
Q => blk00000003_sig00000243
);
blk00000003_blk000001d6 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig0000025a,
Q => blk00000003_sig00000242
);
blk00000003_blk000001d5 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000259,
Q => blk00000003_sig00000241
);
blk00000003_blk000001d4 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000258,
Q => blk00000003_sig00000240
);
blk00000003_blk000001d3 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000257,
Q => blk00000003_sig0000023f
);
blk00000003_blk000001d2 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000256,
Q => blk00000003_sig0000023e
);
blk00000003_blk000001d1 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000255,
Q => blk00000003_sig0000023d
);
blk00000003_blk000001d0 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000254,
Q => blk00000003_sig0000023c
);
blk00000003_blk000001cf : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000253,
Q => blk00000003_sig0000023b
);
blk00000003_blk000001ce : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000252,
Q => blk00000003_sig0000023a
);
blk00000003_blk000001cd : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000251,
Q => blk00000003_sig00000239
);
blk00000003_blk000001cc : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000250,
Q => blk00000003_sig00000238
);
blk00000003_blk000001cb : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig0000024f,
Q => blk00000003_sig00000237
);
blk00000003_blk000001ca : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig0000024e,
Q => blk00000003_sig00000236
);
blk00000003_blk000001c9 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig0000024d,
Q => blk00000003_sig00000235
);
blk00000003_blk000001c8 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig0000024c,
Q => blk00000003_sig00000234
);
blk00000003_blk000001c7 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig0000024b,
Q => blk00000003_sig00000233
);
blk00000003_blk000001c6 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig0000024a,
Q => blk00000003_sig00000232
);
blk00000003_blk000001c5 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000249,
Q => blk00000003_sig00000231
);
blk00000003_blk000001c4 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000248,
Q => blk00000003_sig00000230
);
blk00000003_blk000001c3 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000247,
Q => blk00000003_sig0000022f
);
blk00000003_blk000001c2 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000246,
Q => blk00000003_sig0000022e
);
blk00000003_blk000001c1 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000245,
Q => blk00000003_sig0000022d
);
blk00000003_blk000001c0 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000244,
Q => blk00000003_sig0000022c
);
blk00000003_blk000001bf : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000243,
Q => blk00000003_sig0000022b
);
blk00000003_blk000001be : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000242,
Q => blk00000003_sig0000022a
);
blk00000003_blk000001bd : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000241,
Q => blk00000003_sig00000229
);
blk00000003_blk000001bc : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000240,
Q => blk00000003_sig00000228
);
blk00000003_blk000001bb : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig0000023f,
Q => blk00000003_sig00000227
);
blk00000003_blk000001ba : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig0000023e,
Q => blk00000003_sig00000226
);
blk00000003_blk000001b9 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig0000023d,
Q => blk00000003_sig00000225
);
blk00000003_blk000001b8 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig0000023c,
Q => blk00000003_sig00000224
);
blk00000003_blk000001b7 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig0000023b,
Q => blk00000003_sig00000223
);
blk00000003_blk000001b6 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig0000023a,
Q => blk00000003_sig00000222
);
blk00000003_blk000001b5 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000239,
Q => blk00000003_sig00000221
);
blk00000003_blk000001b4 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000238,
Q => blk00000003_sig00000220
);
blk00000003_blk000001b3 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000237,
Q => blk00000003_sig0000021f
);
blk00000003_blk000001b2 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000236,
Q => blk00000003_sig0000021e
);
blk00000003_blk000001b1 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000235,
Q => blk00000003_sig0000021d
);
blk00000003_blk000001b0 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000234,
Q => blk00000003_sig0000021c
);
blk00000003_blk000001af : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000233,
Q => blk00000003_sig0000021b
);
blk00000003_blk000001ae : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000232,
Q => blk00000003_sig0000021a
);
blk00000003_blk000001ad : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000231,
Q => blk00000003_sig00000219
);
blk00000003_blk000001ac : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000230,
Q => blk00000003_sig00000218
);
blk00000003_blk000001ab : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig0000022f,
Q => blk00000003_sig00000217
);
blk00000003_blk000001aa : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig0000022e,
Q => blk00000003_sig00000216
);
blk00000003_blk000001a9 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig0000022d,
Q => blk00000003_sig00000215
);
blk00000003_blk000001a8 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig0000022c,
Q => blk00000003_sig00000214
);
blk00000003_blk000001a7 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig0000022b,
Q => blk00000003_sig00000213
);
blk00000003_blk000001a6 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig0000022a,
Q => blk00000003_sig00000212
);
blk00000003_blk000001a5 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000229,
Q => blk00000003_sig00000211
);
blk00000003_blk000001a4 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000228,
Q => blk00000003_sig00000210
);
blk00000003_blk000001a3 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000227,
Q => blk00000003_sig0000020f
);
blk00000003_blk000001a2 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000226,
Q => blk00000003_sig0000020e
);
blk00000003_blk000001a1 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000225,
Q => blk00000003_sig0000020d
);
blk00000003_blk000001a0 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000224,
Q => blk00000003_sig0000020c
);
blk00000003_blk0000019f : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000223,
Q => blk00000003_sig0000020b
);
blk00000003_blk0000019e : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000222,
Q => blk00000003_sig0000020a
);
blk00000003_blk0000019d : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000221,
Q => blk00000003_sig00000209
);
blk00000003_blk0000019c : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000220,
Q => blk00000003_sig00000208
);
blk00000003_blk0000019b : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig0000021f,
Q => blk00000003_sig00000207
);
blk00000003_blk0000019a : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig0000021e,
Q => blk00000003_sig00000206
);
blk00000003_blk00000199 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig0000021d,
Q => blk00000003_sig00000205
);
blk00000003_blk00000198 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig0000021c,
Q => blk00000003_sig00000204
);
blk00000003_blk00000197 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig0000021b,
Q => blk00000003_sig00000203
);
blk00000003_blk00000196 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig0000021a,
Q => blk00000003_sig00000202
);
blk00000003_blk00000195 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000219,
Q => blk00000003_sig00000201
);
blk00000003_blk00000194 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000218,
Q => blk00000003_sig00000200
);
blk00000003_blk00000193 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000217,
Q => blk00000003_sig000001ff
);
blk00000003_blk00000192 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000216,
Q => blk00000003_sig000001fe
);
blk00000003_blk00000191 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000215,
Q => blk00000003_sig000001fd
);
blk00000003_blk00000190 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000214,
Q => blk00000003_sig000001fc
);
blk00000003_blk0000018f : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000213,
Q => blk00000003_sig000001fb
);
blk00000003_blk0000018e : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000212,
Q => blk00000003_sig000001fa
);
blk00000003_blk0000018d : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000211,
Q => blk00000003_sig000001f9
);
blk00000003_blk0000018c : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000210,
Q => blk00000003_sig000001f8
);
blk00000003_blk0000018b : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig0000020f,
Q => blk00000003_sig000001f7
);
blk00000003_blk0000018a : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig0000020e,
Q => blk00000003_sig000001f6
);
blk00000003_blk00000189 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig0000020d,
Q => blk00000003_sig000001f5
);
blk00000003_blk00000188 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig0000020c,
Q => blk00000003_sig000001f4
);
blk00000003_blk00000187 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig0000020b,
Q => blk00000003_sig000001f3
);
blk00000003_blk00000186 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig0000020a,
Q => blk00000003_sig000001f2
);
blk00000003_blk00000185 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000209,
Q => blk00000003_sig000001f1
);
blk00000003_blk00000184 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000208,
Q => blk00000003_sig000001f0
);
blk00000003_blk00000183 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000207,
Q => blk00000003_sig000001ef
);
blk00000003_blk00000182 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000206,
Q => blk00000003_sig000001ee
);
blk00000003_blk00000181 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000205,
Q => blk00000003_sig000001ed
);
blk00000003_blk00000180 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000204,
Q => blk00000003_sig000001ec
);
blk00000003_blk0000017f : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000203,
Q => blk00000003_sig000001eb
);
blk00000003_blk0000017e : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000202,
Q => blk00000003_sig000001ea
);
blk00000003_blk0000017d : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000201,
Q => blk00000003_sig000001e9
);
blk00000003_blk0000017c : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000200,
Q => blk00000003_sig000001e8
);
blk00000003_blk0000017b : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig000001ff,
Q => blk00000003_sig000001e7
);
blk00000003_blk0000017a : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig000001fe,
Q => blk00000003_sig000001e6
);
blk00000003_blk00000179 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig000001fd,
Q => blk00000003_sig000001e5
);
blk00000003_blk00000178 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig000001fc,
Q => blk00000003_sig000001e4
);
blk00000003_blk00000177 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig000001fb,
Q => blk00000003_sig000001e3
);
blk00000003_blk00000176 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig000001fa,
Q => blk00000003_sig000001e2
);
blk00000003_blk00000175 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig000001f9,
Q => blk00000003_sig000001e1
);
blk00000003_blk00000174 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig000001f8,
Q => blk00000003_sig000001e0
);
blk00000003_blk00000173 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig000001f7,
Q => blk00000003_sig000001df
);
blk00000003_blk00000172 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig000001f6,
Q => blk00000003_sig000001de
);
blk00000003_blk00000171 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig000001f5,
Q => blk00000003_sig000001dd
);
blk00000003_blk00000170 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig000001f4,
Q => blk00000003_sig000001dc
);
blk00000003_blk0000016f : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig000001f3,
Q => blk00000003_sig000001db
);
blk00000003_blk0000016e : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig000001f2,
Q => blk00000003_sig000001da
);
blk00000003_blk0000016d : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig000001f1,
Q => blk00000003_sig000001d9
);
blk00000003_blk0000016c : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig000001f0,
Q => blk00000003_sig000001d8
);
blk00000003_blk0000016b : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig000001ef,
Q => blk00000003_sig000001d7
);
blk00000003_blk0000016a : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig000001ee,
Q => blk00000003_sig000001d6
);
blk00000003_blk00000169 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig000001ed,
Q => blk00000003_sig000001d5
);
blk00000003_blk00000168 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig000001ec,
Q => blk00000003_sig000001d4
);
blk00000003_blk00000167 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig000001eb,
Q => blk00000003_sig000001d3
);
blk00000003_blk00000166 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig000001ea,
Q => blk00000003_sig000001d2
);
blk00000003_blk00000165 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig000001e9,
Q => blk00000003_sig000001d1
);
blk00000003_blk00000164 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig000001e8,
Q => blk00000003_sig000001d0
);
blk00000003_blk00000163 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig000001e7,
Q => blk00000003_sig000001cf
);
blk00000003_blk00000162 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig000001e6,
Q => blk00000003_sig000001ce
);
blk00000003_blk00000161 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig000001e5,
Q => blk00000003_sig000001cd
);
blk00000003_blk00000160 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig000001e4,
Q => blk00000003_sig000001cc
);
blk00000003_blk0000015f : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig000001e3,
Q => blk00000003_sig000001cb
);
blk00000003_blk0000015e : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig000001e2,
Q => blk00000003_sig000001ca
);
blk00000003_blk0000015d : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig000001e1,
Q => blk00000003_sig000001c9
);
blk00000003_blk0000015c : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig000001e0,
Q => blk00000003_sig000001c8
);
blk00000003_blk0000015b : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig000001df,
Q => blk00000003_sig000001c7
);
blk00000003_blk0000015a : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig000001de,
Q => blk00000003_sig000001c6
);
blk00000003_blk00000159 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig000001dd,
Q => blk00000003_sig000001c5
);
blk00000003_blk00000158 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig000001dc,
Q => blk00000003_sig000001c4
);
blk00000003_blk00000157 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig000001db,
Q => blk00000003_sig000001c3
);
blk00000003_blk00000156 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig000001da,
Q => blk00000003_sig000001c2
);
blk00000003_blk00000155 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig000001d9,
Q => blk00000003_sig000001c1
);
blk00000003_blk00000154 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig000001d8,
Q => blk00000003_sig000001c0
);
blk00000003_blk00000153 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig000001d7,
Q => blk00000003_sig000001bf
);
blk00000003_blk00000152 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig000001d6,
Q => blk00000003_sig000001be
);
blk00000003_blk00000151 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig000001d5,
Q => blk00000003_sig000001bd
);
blk00000003_blk00000150 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig000001d4,
Q => blk00000003_sig000001bc
);
blk00000003_blk0000014f : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig000001d3,
Q => blk00000003_sig000001bb
);
blk00000003_blk0000014e : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig000001d2,
Q => blk00000003_sig000001ba
);
blk00000003_blk0000014d : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig000001d1,
Q => blk00000003_sig000001b9
);
blk00000003_blk0000014c : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig000001d0,
Q => blk00000003_sig000001b8
);
blk00000003_blk0000014b : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig000001cf,
Q => blk00000003_sig000001b7
);
blk00000003_blk0000014a : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig000001ce,
Q => blk00000003_sig000001b6
);
blk00000003_blk00000149 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig000001cd,
Q => blk00000003_sig000001b5
);
blk00000003_blk00000148 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig000001cc,
Q => blk00000003_sig000001b4
);
blk00000003_blk00000147 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig000001cb,
Q => blk00000003_sig000001b3
);
blk00000003_blk00000146 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig000001ca,
Q => blk00000003_sig000001b2
);
blk00000003_blk00000145 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig000001c9,
Q => blk00000003_sig000001b1
);
blk00000003_blk00000144 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig000001c8,
Q => blk00000003_sig000001b0
);
blk00000003_blk00000143 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig000001c7,
Q => blk00000003_sig000001af
);
blk00000003_blk00000142 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig000001c6,
Q => blk00000003_sig000001ae
);
blk00000003_blk00000141 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig000001c5,
Q => blk00000003_sig000001ad
);
blk00000003_blk00000140 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig000001c4,
Q => blk00000003_sig000001ac
);
blk00000003_blk0000013f : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig000001c3,
Q => blk00000003_sig000001ab
);
blk00000003_blk0000013e : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig000001c2,
Q => blk00000003_sig000001aa
);
blk00000003_blk0000013d : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig000001c1,
Q => blk00000003_sig000001a9
);
blk00000003_blk0000013c : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig000001c0,
Q => blk00000003_sig000001a8
);
blk00000003_blk0000013b : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig000001bf,
Q => blk00000003_sig000001a7
);
blk00000003_blk0000013a : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig000001be,
Q => blk00000003_sig000001a6
);
blk00000003_blk00000139 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig000001bd,
Q => blk00000003_sig000001a5
);
blk00000003_blk00000138 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig000001bc,
Q => blk00000003_sig000001a4
);
blk00000003_blk00000137 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig000001bb,
Q => blk00000003_sig000001a3
);
blk00000003_blk00000136 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig000001ba,
Q => blk00000003_sig000001a2
);
blk00000003_blk00000135 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig000001b9,
Q => blk00000003_sig000001a1
);
blk00000003_blk00000134 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig000001b8,
Q => blk00000003_sig000001a0
);
blk00000003_blk00000133 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig000001b7,
Q => blk00000003_sig0000019f
);
blk00000003_blk00000132 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig000001b6,
Q => blk00000003_sig0000019e
);
blk00000003_blk00000131 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig000001b5,
Q => blk00000003_sig0000019d
);
blk00000003_blk00000130 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig000001b4,
Q => blk00000003_sig0000019c
);
blk00000003_blk0000012f : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig000001b3,
Q => blk00000003_sig0000019b
);
blk00000003_blk0000012e : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig000001b2,
Q => blk00000003_sig0000019a
);
blk00000003_blk0000012d : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig000001b1,
Q => blk00000003_sig00000199
);
blk00000003_blk0000012c : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig000001b0,
Q => blk00000003_sig00000198
);
blk00000003_blk0000012b : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig000001af,
Q => blk00000003_sig00000197
);
blk00000003_blk0000012a : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig000001ae,
Q => blk00000003_sig00000196
);
blk00000003_blk00000129 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig000001ad,
Q => blk00000003_sig00000195
);
blk00000003_blk00000128 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig000001ac,
Q => blk00000003_sig00000194
);
blk00000003_blk00000127 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig000001ab,
Q => blk00000003_sig00000193
);
blk00000003_blk00000126 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig000001aa,
Q => blk00000003_sig00000192
);
blk00000003_blk00000125 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig000001a9,
Q => blk00000003_sig00000191
);
blk00000003_blk00000124 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig000001a8,
Q => blk00000003_sig00000190
);
blk00000003_blk00000123 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig000001a7,
Q => blk00000003_sig0000018f
);
blk00000003_blk00000122 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig000001a6,
Q => blk00000003_sig0000018e
);
blk00000003_blk00000121 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig000001a5,
Q => blk00000003_sig0000018d
);
blk00000003_blk00000120 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig000001a4,
Q => blk00000003_sig0000018c
);
blk00000003_blk0000011f : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig000001a3,
Q => blk00000003_sig0000018b
);
blk00000003_blk0000011e : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig000001a2,
Q => blk00000003_sig0000018a
);
blk00000003_blk0000011d : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig000001a1,
Q => blk00000003_sig00000189
);
blk00000003_blk0000011c : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig000001a0,
Q => blk00000003_sig00000188
);
blk00000003_blk0000011b : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig0000019f,
Q => blk00000003_sig00000187
);
blk00000003_blk0000011a : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig0000019e,
Q => blk00000003_sig00000186
);
blk00000003_blk00000119 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig0000019d,
Q => blk00000003_sig00000185
);
blk00000003_blk00000118 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig0000019c,
Q => blk00000003_sig00000184
);
blk00000003_blk00000117 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig0000019b,
Q => blk00000003_sig00000183
);
blk00000003_blk00000116 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig0000019a,
Q => blk00000003_sig00000182
);
blk00000003_blk00000115 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000199,
Q => blk00000003_sig00000181
);
blk00000003_blk00000114 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000198,
Q => blk00000003_sig00000180
);
blk00000003_blk00000113 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000197,
Q => blk00000003_sig0000017f
);
blk00000003_blk00000112 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000196,
Q => blk00000003_sig0000017e
);
blk00000003_blk00000111 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000195,
Q => blk00000003_sig0000017d
);
blk00000003_blk00000110 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000194,
Q => blk00000003_sig0000017c
);
blk00000003_blk0000010f : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000193,
Q => blk00000003_sig0000017b
);
blk00000003_blk0000010e : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000192,
Q => blk00000003_sig0000017a
);
blk00000003_blk0000010d : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000191,
Q => blk00000003_sig00000179
);
blk00000003_blk0000010c : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000190,
Q => blk00000003_sig00000178
);
blk00000003_blk0000010b : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig0000018f,
Q => blk00000003_sig00000177
);
blk00000003_blk0000010a : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig0000018e,
Q => blk00000003_sig00000176
);
blk00000003_blk00000109 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig0000018d,
Q => blk00000003_sig00000175
);
blk00000003_blk00000108 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig0000018c,
Q => blk00000003_sig00000174
);
blk00000003_blk00000107 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig0000018b,
Q => blk00000003_sig00000173
);
blk00000003_blk00000106 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig0000018a,
Q => blk00000003_sig00000172
);
blk00000003_blk00000105 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000189,
Q => blk00000003_sig00000171
);
blk00000003_blk00000104 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000188,
Q => blk00000003_sig00000170
);
blk00000003_blk00000103 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000187,
Q => blk00000003_sig0000016f
);
blk00000003_blk00000102 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000186,
Q => blk00000003_sig0000016e
);
blk00000003_blk00000101 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000185,
Q => blk00000003_sig0000016d
);
blk00000003_blk00000100 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000184,
Q => blk00000003_sig0000016c
);
blk00000003_blk000000ff : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000183,
Q => blk00000003_sig0000016b
);
blk00000003_blk000000fe : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000182,
Q => blk00000003_sig0000016a
);
blk00000003_blk000000fd : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000181,
Q => blk00000003_sig00000169
);
blk00000003_blk000000fc : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000180,
Q => blk00000003_sig00000168
);
blk00000003_blk000000fb : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig0000017f,
Q => blk00000003_sig00000167
);
blk00000003_blk000000fa : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig0000017e,
Q => blk00000003_sig00000166
);
blk00000003_blk000000f9 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig0000017d,
Q => blk00000003_sig00000165
);
blk00000003_blk000000f8 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig0000017c,
Q => blk00000003_sig00000164
);
blk00000003_blk000000f7 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig0000017b,
Q => blk00000003_sig00000163
);
blk00000003_blk000000f6 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig0000017a,
Q => blk00000003_sig00000162
);
blk00000003_blk000000f5 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000179,
Q => blk00000003_sig00000161
);
blk00000003_blk000000f4 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000178,
Q => blk00000003_sig00000160
);
blk00000003_blk000000f3 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000177,
Q => blk00000003_sig0000015f
);
blk00000003_blk000000f2 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000176,
Q => blk00000003_sig0000015e
);
blk00000003_blk000000f1 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000175,
Q => blk00000003_sig0000015d
);
blk00000003_blk000000f0 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000174,
Q => blk00000003_sig0000015c
);
blk00000003_blk000000ef : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000173,
Q => blk00000003_sig0000015b
);
blk00000003_blk000000ee : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000172,
Q => blk00000003_sig0000015a
);
blk00000003_blk000000ed : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000171,
Q => blk00000003_sig00000159
);
blk00000003_blk000000ec : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000170,
Q => blk00000003_sig00000158
);
blk00000003_blk000000eb : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig0000016f,
Q => blk00000003_sig00000157
);
blk00000003_blk000000ea : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig0000016e,
Q => blk00000003_sig00000156
);
blk00000003_blk000000e9 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig0000016d,
Q => blk00000003_sig00000155
);
blk00000003_blk000000e8 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig0000016c,
Q => blk00000003_sig00000154
);
blk00000003_blk000000e7 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig0000016b,
Q => blk00000003_sig00000153
);
blk00000003_blk000000e6 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig0000016a,
Q => blk00000003_sig00000152
);
blk00000003_blk000000e5 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000169,
Q => blk00000003_sig00000151
);
blk00000003_blk000000e4 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000168,
Q => blk00000003_sig00000150
);
blk00000003_blk000000e3 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000167,
Q => blk00000003_sig0000014f
);
blk00000003_blk000000e2 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000166,
Q => blk00000003_sig0000014e
);
blk00000003_blk000000e1 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000165,
Q => blk00000003_sig0000014d
);
blk00000003_blk000000e0 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000164,
Q => blk00000003_sig0000014c
);
blk00000003_blk000000df : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000163,
Q => blk00000003_sig0000014b
);
blk00000003_blk000000de : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000162,
Q => blk00000003_sig0000014a
);
blk00000003_blk000000dd : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000161,
Q => blk00000003_sig00000149
);
blk00000003_blk000000dc : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000160,
Q => blk00000003_sig00000148
);
blk00000003_blk000000db : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig0000015f,
Q => blk00000003_sig00000147
);
blk00000003_blk000000da : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig0000015e,
Q => blk00000003_sig00000146
);
blk00000003_blk000000d9 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig0000015d,
Q => blk00000003_sig00000145
);
blk00000003_blk000000d8 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig0000015c,
Q => blk00000003_sig00000144
);
blk00000003_blk000000d7 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig0000015b,
Q => blk00000003_sig00000143
);
blk00000003_blk000000d6 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig0000015a,
Q => blk00000003_sig00000142
);
blk00000003_blk000000d5 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000159,
Q => blk00000003_sig00000141
);
blk00000003_blk000000d4 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000158,
Q => blk00000003_sig00000140
);
blk00000003_blk000000d3 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000157,
Q => blk00000003_sig0000013f
);
blk00000003_blk000000d2 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000156,
Q => blk00000003_sig0000013e
);
blk00000003_blk000000d1 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000155,
Q => blk00000003_sig0000013d
);
blk00000003_blk000000d0 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000154,
Q => blk00000003_sig0000013c
);
blk00000003_blk000000cf : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000153,
Q => blk00000003_sig0000013b
);
blk00000003_blk000000ce : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000152,
Q => blk00000003_sig0000013a
);
blk00000003_blk000000cd : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000151,
Q => blk00000003_sig00000139
);
blk00000003_blk000000cc : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000150,
Q => blk00000003_sig00000138
);
blk00000003_blk000000cb : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig0000014f,
Q => blk00000003_sig00000137
);
blk00000003_blk000000ca : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig0000014e,
Q => blk00000003_sig00000136
);
blk00000003_blk000000c9 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig0000014d,
Q => blk00000003_sig00000135
);
blk00000003_blk000000c8 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig0000014c,
Q => blk00000003_sig00000134
);
blk00000003_blk000000c7 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig0000014b,
Q => blk00000003_sig00000133
);
blk00000003_blk000000c6 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig0000014a,
Q => blk00000003_sig00000132
);
blk00000003_blk000000c5 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000149,
Q => blk00000003_sig00000131
);
blk00000003_blk000000c4 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000148,
Q => blk00000003_sig00000130
);
blk00000003_blk000000c3 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000147,
Q => blk00000003_sig0000012f
);
blk00000003_blk000000c2 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000146,
Q => blk00000003_sig0000012e
);
blk00000003_blk000000c1 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000145,
Q => blk00000003_sig0000012d
);
blk00000003_blk000000c0 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000144,
Q => blk00000003_sig0000012c
);
blk00000003_blk000000bf : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000143,
Q => blk00000003_sig0000012b
);
blk00000003_blk000000be : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000142,
Q => blk00000003_sig0000012a
);
blk00000003_blk000000bd : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000141,
Q => blk00000003_sig00000129
);
blk00000003_blk000000bc : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000140,
Q => blk00000003_sig00000128
);
blk00000003_blk000000bb : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig0000013f,
Q => blk00000003_sig00000127
);
blk00000003_blk000000ba : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig0000013e,
Q => blk00000003_sig00000126
);
blk00000003_blk000000b9 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig0000013d,
Q => blk00000003_sig00000125
);
blk00000003_blk000000b8 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig0000013c,
Q => blk00000003_sig00000124
);
blk00000003_blk000000b7 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig0000013b,
Q => blk00000003_sig00000123
);
blk00000003_blk000000b6 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig0000013a,
Q => blk00000003_sig00000122
);
blk00000003_blk000000b5 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000139,
Q => blk00000003_sig00000121
);
blk00000003_blk000000b4 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000138,
Q => blk00000003_sig00000120
);
blk00000003_blk000000b3 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000137,
Q => blk00000003_sig0000011f
);
blk00000003_blk000000b2 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000136,
Q => blk00000003_sig0000011e
);
blk00000003_blk000000b1 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000135,
Q => blk00000003_sig0000011d
);
blk00000003_blk000000b0 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000134,
Q => blk00000003_sig0000011c
);
blk00000003_blk000000af : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000133,
Q => blk00000003_sig0000011b
);
blk00000003_blk000000ae : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000132,
Q => blk00000003_sig0000011a
);
blk00000003_blk000000ad : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000131,
Q => blk00000003_sig00000119
);
blk00000003_blk000000ac : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000130,
Q => blk00000003_sig00000118
);
blk00000003_blk000000ab : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig0000012f,
Q => blk00000003_sig00000117
);
blk00000003_blk000000aa : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig0000012e,
Q => blk00000003_sig00000116
);
blk00000003_blk000000a9 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig0000012d,
Q => blk00000003_sig00000115
);
blk00000003_blk000000a8 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig0000012c,
Q => blk00000003_sig00000114
);
blk00000003_blk000000a7 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig0000012b,
Q => blk00000003_sig00000113
);
blk00000003_blk000000a6 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig0000012a,
Q => blk00000003_sig00000112
);
blk00000003_blk000000a5 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000129,
Q => blk00000003_sig00000111
);
blk00000003_blk000000a4 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000128,
Q => blk00000003_sig00000110
);
blk00000003_blk000000a3 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000127,
Q => blk00000003_sig0000010f
);
blk00000003_blk000000a2 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000126,
Q => blk00000003_sig0000010e
);
blk00000003_blk000000a1 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000125,
Q => blk00000003_sig0000010d
);
blk00000003_blk000000a0 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000124,
Q => blk00000003_sig0000010c
);
blk00000003_blk0000009f : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000123,
Q => blk00000003_sig0000010b
);
blk00000003_blk0000009e : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000122,
Q => blk00000003_sig0000010a
);
blk00000003_blk0000009d : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000121,
Q => blk00000003_sig00000108
);
blk00000003_blk0000009c : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000120,
Q => blk00000003_sig00000106
);
blk00000003_blk0000009b : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig0000011f,
Q => blk00000003_sig00000104
);
blk00000003_blk0000009a : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig0000011e,
Q => blk00000003_sig00000102
);
blk00000003_blk00000099 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig0000011d,
Q => blk00000003_sig00000100
);
blk00000003_blk00000098 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig0000011c,
Q => blk00000003_sig000000fe
);
blk00000003_blk00000097 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig0000011b,
Q => blk00000003_sig000000fc
);
blk00000003_blk00000096 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig0000011a,
Q => blk00000003_sig000000fa
);
blk00000003_blk00000095 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000119,
Q => blk00000003_sig000000f8
);
blk00000003_blk00000094 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000118,
Q => blk00000003_sig000000f6
);
blk00000003_blk00000093 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000117,
Q => blk00000003_sig000000f4
);
blk00000003_blk00000092 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000116,
Q => blk00000003_sig000000f2
);
blk00000003_blk00000091 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000115,
Q => blk00000003_sig000000f0
);
blk00000003_blk00000090 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000114,
Q => blk00000003_sig000000ee
);
blk00000003_blk0000008f : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000113,
Q => blk00000003_sig000000ec
);
blk00000003_blk0000008e : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000112,
Q => blk00000003_sig000000ea
);
blk00000003_blk0000008d : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000111,
Q => blk00000003_sig000000e8
);
blk00000003_blk0000008c : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000110,
Q => blk00000003_sig000000e6
);
blk00000003_blk0000008b : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig0000010f,
Q => blk00000003_sig000000e4
);
blk00000003_blk0000008a : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig0000010e,
Q => blk00000003_sig000000e2
);
blk00000003_blk00000089 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig0000010d,
Q => blk00000003_sig000000e0
);
blk00000003_blk00000088 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig0000010c,
Q => blk00000003_sig000000de
);
blk00000003_blk00000087 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig0000010b,
Q => blk00000003_sig000000dc
);
blk00000003_blk00000086 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig0000010a,
Q => blk00000003_sig000000da
);
blk00000003_blk00000085 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000108,
Q => blk00000003_sig00000109
);
blk00000003_blk00000084 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000106,
Q => blk00000003_sig00000107
);
blk00000003_blk00000083 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000104,
Q => blk00000003_sig00000105
);
blk00000003_blk00000082 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000102,
Q => blk00000003_sig00000103
);
blk00000003_blk00000081 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000100,
Q => blk00000003_sig00000101
);
blk00000003_blk00000080 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig000000fe,
Q => blk00000003_sig000000ff
);
blk00000003_blk0000007f : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig000000fc,
Q => blk00000003_sig000000fd
);
blk00000003_blk0000007e : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig000000fa,
Q => blk00000003_sig000000fb
);
blk00000003_blk0000007d : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig000000f8,
Q => blk00000003_sig000000f9
);
blk00000003_blk0000007c : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig000000f6,
Q => blk00000003_sig000000f7
);
blk00000003_blk0000007b : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig000000f4,
Q => blk00000003_sig000000f5
);
blk00000003_blk0000007a : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig000000f2,
Q => blk00000003_sig000000f3
);
blk00000003_blk00000079 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig000000f0,
Q => blk00000003_sig000000f1
);
blk00000003_blk00000078 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig000000ee,
Q => blk00000003_sig000000ef
);
blk00000003_blk00000077 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig000000ec,
Q => blk00000003_sig000000ed
);
blk00000003_blk00000076 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig000000ea,
Q => blk00000003_sig000000eb
);
blk00000003_blk00000075 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig000000e8,
Q => blk00000003_sig000000e9
);
blk00000003_blk00000074 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig000000e6,
Q => blk00000003_sig000000e7
);
blk00000003_blk00000073 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig000000e4,
Q => blk00000003_sig000000e5
);
blk00000003_blk00000072 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig000000e2,
Q => blk00000003_sig000000e3
);
blk00000003_blk00000071 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig000000e0,
Q => blk00000003_sig000000e1
);
blk00000003_blk00000070 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig000000de,
Q => blk00000003_sig000000df
);
blk00000003_blk0000006f : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig000000dc,
Q => blk00000003_sig000000dd
);
blk00000003_blk0000006e : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig000000da,
Q => blk00000003_sig000000db
);
blk00000003_blk0000006d : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => dividend_0(0),
Q => blk00000003_sig000000d9
);
blk00000003_blk0000006c : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => dividend_0(1),
Q => blk00000003_sig000000d8
);
blk00000003_blk0000006b : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => dividend_0(2),
Q => blk00000003_sig000000d7
);
blk00000003_blk0000006a : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => dividend_0(3),
Q => blk00000003_sig000000d6
);
blk00000003_blk00000069 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => dividend_0(4),
Q => blk00000003_sig000000d5
);
blk00000003_blk00000068 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => dividend_0(5),
Q => blk00000003_sig000000d4
);
blk00000003_blk00000067 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => dividend_0(6),
Q => blk00000003_sig000000d3
);
blk00000003_blk00000066 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => dividend_0(7),
Q => blk00000003_sig000000d2
);
blk00000003_blk00000065 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => dividend_0(8),
Q => blk00000003_sig000000d1
);
blk00000003_blk00000064 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => dividend_0(9),
Q => blk00000003_sig000000d0
);
blk00000003_blk00000063 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => dividend_0(10),
Q => blk00000003_sig000000cf
);
blk00000003_blk00000062 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => dividend_0(11),
Q => blk00000003_sig000000ce
);
blk00000003_blk00000061 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => dividend_0(12),
Q => blk00000003_sig000000cd
);
blk00000003_blk00000060 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => dividend_0(13),
Q => blk00000003_sig000000cc
);
blk00000003_blk0000005f : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => dividend_0(14),
Q => blk00000003_sig000000cb
);
blk00000003_blk0000005e : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => dividend_0(15),
Q => blk00000003_sig000000ca
);
blk00000003_blk0000005d : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => dividend_0(16),
Q => blk00000003_sig000000c9
);
blk00000003_blk0000005c : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => dividend_0(17),
Q => blk00000003_sig000000c8
);
blk00000003_blk0000005b : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => dividend_0(18),
Q => blk00000003_sig000000c7
);
blk00000003_blk0000005a : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => dividend_0(19),
Q => blk00000003_sig000000c6
);
blk00000003_blk00000059 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => dividend_0(20),
Q => blk00000003_sig000000c5
);
blk00000003_blk00000058 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => dividend_0(21),
Q => blk00000003_sig000000c4
);
blk00000003_blk00000057 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => dividend_0(22),
Q => blk00000003_sig000000c3
);
blk00000003_blk00000056 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => dividend_0(23),
Q => blk00000003_sig000000c2
);
blk00000003_blk00000055 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig000000c1,
Q => quotient_2(0)
);
blk00000003_blk00000054 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig000000c0,
Q => quotient_2(1)
);
blk00000003_blk00000053 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig000000bf,
Q => quotient_2(2)
);
blk00000003_blk00000052 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig000000be,
Q => quotient_2(3)
);
blk00000003_blk00000051 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig000000bd,
Q => quotient_2(4)
);
blk00000003_blk00000050 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig000000bc,
Q => quotient_2(5)
);
blk00000003_blk0000004f : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig000000bb,
Q => quotient_2(6)
);
blk00000003_blk0000004e : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig000000ba,
Q => quotient_2(7)
);
blk00000003_blk0000004d : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig000000b9,
Q => quotient_2(8)
);
blk00000003_blk0000004c : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig000000b8,
Q => quotient_2(9)
);
blk00000003_blk0000004b : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig000000b7,
Q => quotient_2(10)
);
blk00000003_blk0000004a : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig000000b6,
Q => quotient_2(11)
);
blk00000003_blk00000049 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig000000b5,
Q => quotient_2(12)
);
blk00000003_blk00000048 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig000000b4,
Q => quotient_2(13)
);
blk00000003_blk00000047 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig000000b3,
Q => quotient_2(14)
);
blk00000003_blk00000046 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig000000b2,
Q => quotient_2(15)
);
blk00000003_blk00000045 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig000000b1,
Q => quotient_2(16)
);
blk00000003_blk00000044 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig000000b0,
Q => quotient_2(17)
);
blk00000003_blk00000043 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig000000af,
Q => quotient_2(18)
);
blk00000003_blk00000042 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig000000ae,
Q => quotient_2(19)
);
blk00000003_blk00000041 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig000000ad,
Q => quotient_2(20)
);
blk00000003_blk00000040 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig000000ac,
Q => quotient_2(21)
);
blk00000003_blk0000003f : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig000000ab,
Q => quotient_2(22)
);
blk00000003_blk0000003e : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig000000aa,
Q => quotient_2(23)
);
blk00000003_blk0000003d : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000065,
Q => blk00000003_sig000000a9
);
blk00000003_blk0000003c : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig000000a8,
Q => blk00000003_sig000000a7
);
blk00000003_blk0000003b : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig000000a7,
Q => blk00000003_sig000000a5
);
blk00000003_blk0000003a : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig000000a6,
Q => blk00000003_sig000000a4
);
blk00000003_blk00000039 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig000000a5,
Q => blk00000003_sig000000a2
);
blk00000003_blk00000038 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig000000a4,
Q => blk00000003_sig000000a1
);
blk00000003_blk00000037 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig000000a3,
Q => blk00000003_sig000000a0
);
blk00000003_blk00000036 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig000000a2,
Q => blk00000003_sig0000009e
);
blk00000003_blk00000035 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig000000a1,
Q => blk00000003_sig0000009d
);
blk00000003_blk00000034 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig000000a0,
Q => blk00000003_sig0000009c
);
blk00000003_blk00000033 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig0000009f,
Q => blk00000003_sig0000009b
);
blk00000003_blk00000032 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig0000009e,
Q => blk00000003_sig00000099
);
blk00000003_blk00000031 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig0000009d,
Q => blk00000003_sig00000098
);
blk00000003_blk00000030 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig0000009c,
Q => blk00000003_sig00000097
);
blk00000003_blk0000002f : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig0000009b,
Q => blk00000003_sig00000096
);
blk00000003_blk0000002e : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig0000009a,
Q => blk00000003_sig00000095
);
blk00000003_blk0000002d : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000099,
Q => blk00000003_sig00000092
);
blk00000003_blk0000002c : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000098,
Q => blk00000003_sig00000090
);
blk00000003_blk0000002b : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000097,
Q => blk00000003_sig0000008e
);
blk00000003_blk0000002a : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000096,
Q => blk00000003_sig0000008c
);
blk00000003_blk00000029 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000095,
Q => blk00000003_sig0000008a
);
blk00000003_blk00000028 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000094,
Q => blk00000003_sig00000088
);
blk00000003_blk00000027 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000092,
Q => blk00000003_sig00000093
);
blk00000003_blk00000026 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000090,
Q => blk00000003_sig00000091
);
blk00000003_blk00000025 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig0000008e,
Q => blk00000003_sig0000008f
);
blk00000003_blk00000024 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig0000008c,
Q => blk00000003_sig0000008d
);
blk00000003_blk00000023 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig0000008a,
Q => blk00000003_sig0000008b
);
blk00000003_blk00000022 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000088,
Q => blk00000003_sig00000089
);
blk00000003_blk00000021 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000086,
Q => blk00000003_sig00000087
);
blk00000003_blk00000020 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000084,
Q => blk00000003_sig00000085
);
blk00000003_blk0000001f : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000083,
Q => blk00000003_sig0000007c
);
blk00000003_blk0000001e : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000082,
Q => blk00000003_sig0000007b
);
blk00000003_blk0000001d : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000081,
Q => blk00000003_sig0000007a
);
blk00000003_blk0000001c : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000080,
Q => blk00000003_sig00000079
);
blk00000003_blk0000001b : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig0000007f,
Q => blk00000003_sig00000078
);
blk00000003_blk0000001a : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig0000007e,
Q => blk00000003_sig00000077
);
blk00000003_blk00000019 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig0000007c,
Q => blk00000003_sig0000007d
);
blk00000003_blk00000018 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig0000007b,
Q => blk00000003_sig00000075
);
blk00000003_blk00000017 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig0000007a,
Q => blk00000003_sig00000074
);
blk00000003_blk00000016 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000079,
Q => blk00000003_sig00000073
);
blk00000003_blk00000015 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000078,
Q => blk00000003_sig00000072
);
blk00000003_blk00000014 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000077,
Q => blk00000003_sig00000071
);
blk00000003_blk00000013 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000075,
Q => blk00000003_sig00000076
);
blk00000003_blk00000012 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000074,
Q => blk00000003_sig0000006f
);
blk00000003_blk00000011 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000073,
Q => blk00000003_sig0000006e
);
blk00000003_blk00000010 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000072,
Q => blk00000003_sig0000006d
);
blk00000003_blk0000000f : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000071,
Q => blk00000003_sig0000006c
);
blk00000003_blk0000000e : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig0000006f,
Q => blk00000003_sig00000070
);
blk00000003_blk0000000d : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig0000006e,
Q => blk00000003_sig0000006a
);
blk00000003_blk0000000c : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig0000006d,
Q => blk00000003_sig00000069
);
blk00000003_blk0000000b : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig0000006c,
Q => blk00000003_sig00000068
);
blk00000003_blk0000000a : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig0000006a,
Q => blk00000003_sig0000006b
);
blk00000003_blk00000009 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000069,
Q => blk00000003_sig00000066
);
blk00000003_blk00000008 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000068,
Q => blk00000003_sig00000064
);
blk00000003_blk00000007 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000066,
Q => blk00000003_sig00000067
);
blk00000003_blk00000006 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000064,
Q => blk00000003_sig00000065
);
blk00000003_blk00000005 : VCC
port map (
P => NlwRenamedSig_OI_rfd
);
blk00000003_blk00000004 : GND
port map (
G => blk00000003_sig00000062
);
end STRUCTURE;
-- synthesis translate_on
| gpl-2.0 | 991df9964338007a05b1e0f58042638e | 0.614547 | 3.431368 | false | false | false | false |
ambrosef/HLx_Examples | Acceleration/memcached/buildUoeMcdSingleDramPCIe/src/hdl/stats_module.vhd | 1 | 3,847 | ----------------------------------------------------------------------------------
-- Company: XILINX
-- Engineer: Stephan Koster
--
-- Create Date: 07.03.2014 15:16:37
-- Design Name: stats module
-- Module Name: stats_module - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description: Sniffs an axi streaming bus, gathers stats and exposes them in a register
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;
use IEEE.STD_LOGIC_MISC.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity stats_module is
Generic(
data_size: INTEGER:=64;
period_counter_size: INTEGER :=22
);
Port (
ACLK : in std_logic;
RESET : in std_logic;
M_AXIS_TDATA : out std_logic_vector (data_size-1 downto 0);
M_AXIS_TSTRB : out std_logic_vector (7 downto 0);
M_AXIS_TVALID : out std_logic;
M_AXIS_TREADY : in std_logic;
M_AXIS_TLAST : out std_logic;
S_AXIS_TDATA : in std_logic_vector (data_size-1 downto 0);
S_AXIS_TSTRB : in std_logic_vector (7 downto 0);
S_AXIS_TUSER : in std_logic_vector (127 downto 0);
S_AXIS_TVALID : in std_logic;
S_AXIS_TREADY : out std_logic;
S_AXIS_TLAST : in std_logic;
--Expose the gathered stats
STATS_DATA : out std_logic_vector(31 downto 0)
);
end stats_module;
architecture Behavioral of stats_module is
signal rst,clk: std_logic;--rename hard to type signals
signal busycount: std_logic_vector(31 downto 0);--counts how many cycles both ready and valid are on
signal idlecount: std_logic_vector(31 downto 0);--so far does nothing
signal period_tracker: std_logic_vector(period_counter_size-1 downto 0);--measuring period ends on rollaround
signal count_reset:std_logic;
begin
rst<=RESET;
clk<=ACLK;
--axi stream signals pass straight through from master to slave. We just read Ready and Valid signals
M_AXIS_TDATA <= S_AXIS_TDATA;
M_AXIS_TSTRB <= S_AXIS_TSTRB;
M_AXIS_TVALID <= S_AXIS_TVALID;
S_AXIS_TREADY <= M_AXIS_TREADY;
M_AXIS_TLAST <= S_AXIS_TLAST;
generate_period:process(rst,clk)
begin
if(rst='1') then
period_tracker<=(others=>'0');
elsif(rising_edge(clk)) then
period_tracker<=std_logic_vector(unsigned(period_tracker)+1);
count_reset<=AND_REDUCE( period_tracker);--bitwise and
end if;
end process;
process(rst,clk)
begin
if(rst='1') then
--reset state
busycount<=(others=>'0');
STATS_DATA<=(others=>'0');
elsif(rising_edge(clk)) then
--write the output signal with the stats when the period counter rolls around
if(count_reset='1') then
--STATS_DATA(31)<='1';
STATS_DATA(period_counter_size downto 0)<=busycount(period_counter_size downto 0);
busycount<=(others=>'0');
else
--sniff the axi stream signals, gather stats
if(M_AXIS_TREADY='1' and S_AXIS_TVALID='1') then
busycount<=std_logic_vector(unsigned(busycount)+1);
end if;
end if;
end if;
end process;
end Behavioral;
| bsd-3-clause | c4b72b17d6ed49c41ba6ca0cb1001a33 | 0.569275 | 3.92551 | false | false | false | false |
emogenet/ghdl | testsuite/vests/vhdl-93/ashenden/compliant/ch_03_ch_03_18.vhd | 4 | 2,907 |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_03_ch_03_18.vhd,v 1.3 2001-10-26 16:29:33 paw Exp $
-- $Revision: 1.3 $
--
-- ---------------------------------------------------------------------
entity ch_03_18 is
end entity ch_03_18;
architecture test of ch_03_18 is
begin
process_3_5_a : process is
constant initial_value : natural := 10;
constant max_value : natural := 8;
constant current_character : character := 'A';
constant input_string : string := "012ABC";
constant free_memory : natural := 0;
constant low_water_limit : natural := 1024;
constant packet_length : natural := 0;
constant clock_pulse_width : delay_length := 10 ns;
constant min_clock_width : delay_length := 20 ns;
constant last_position : natural := 10;
constant first_position : natural := 5;
constant number_of_entries : natural := 0;
begin
-- code from book:
assert initial_value <= max_value;
--
assert initial_value <= max_value
report "initial value too large";
--
assert current_character >= '0' and current_character <= '9'
report "Input number " & input_string & " contains a non-digit";
--
assert free_memory >= low_water_limit
report "low on memory, about to start garbage collect"
severity note;
--
assert packet_length /= 0
report "empty network packet received"
severity warning;
--
assert clock_pulse_width >= min_clock_width
severity error;
--
assert (last_position - first_position + 1) = number_of_entries
report "inconsistency in buffer model"
severity failure;
-- end of code from book
wait;
end process process_3_5_a;
end architecture test;
| gpl-2.0 | 3680485b4744c29076015254e72e2f07 | 0.556932 | 4.658654 | false | false | false | false |
ambrosef/HLx_Examples | Acceleration/memcached/regressionSims/sources/vc709_tb_wrapper.vhd | 1 | 1,141 | LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY vc709_tb_wrapper IS
END vc709_tb_wrapper;
ARCHITECTURE behavior OF vc709_tb_wrapper IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT prototypeWrapper
PORT(
clk : IN std_logic;
rst : IN std_logic);
END COMPONENT;
--Inputs
signal clk : std_logic := '0';
signal rst : std_logic := '0';
-- Clock period definitions
constant clk_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: prototypeWrapper PORT MAP (
clk => clk,
rst => rst);
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
wait for 20 ns;
rst <= '1';
wait for clk_period*3;
rst <= '0';
wait;
end process;
END;
| bsd-3-clause | 6f2a89d829ef05b58d99bf876bd80816 | 0.612621 | 3.704545 | false | false | false | false |
emogenet/ghdl | testsuite/vests/vhdl-ams/ashenden/compliant/guards-and-blocks/inline_04.vhd | 4 | 2,115 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
entity inline_04 is
end entity inline_04;
----------------------------------------------------------------
architecture test of inline_04 is
subtype word is bit_vector(0 to 31);
type word_array is array (integer range <>) of word;
function resolve_words ( words : word_array ) return word is
begin
if words'length > 0 then
return words(words'left);
else
return X"00000000";
end if;
end function resolve_words;
subtype resolved_word is resolve_words word;
-- code from book:
signal memory_data_bus : resolved_word bus;
disconnect memory_data_bus : resolved_word after 3 ns;
-- end of code from book
signal mem_sel, mem_write : boolean;
signal cache_data_bus : word;
begin
-- code from book:
mem_write_buffer : block (mem_sel and mem_write) is
begin
memory_data_bus <=
guarded reject 2 ns inertial cache_data_bus after 4 ns;
end block mem_write_buffer;
-- end of code from book
stimulus : process is
begin
cache_data_bus <= X"DDDDDDDD";
wait for 10 ns;
mem_sel <= true; mem_write <= true;
wait for 10 ns;
cache_data_bus <= X"AAAAAAAA";
wait for 10 ns;
mem_sel <= false; mem_write <= false;
wait for 10 ns;
cache_data_bus <= X"11111111";
wait;
end process stimulus;
end architecture test;
| gpl-2.0 | cac085974db18178b7a25ef5c23c3d3e | 0.669976 | 3.938547 | false | false | false | false |
emogenet/ghdl | testsuite/gna/issue42/bugreport_attribute.vhdl | 1 | 3,092 | -- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
-- =============================================================================
-- Authors: Patrick Lehmann
-- Reproducer: Experiments on custom attributes ended in a crash.
--
-- License:
-- =============================================================================
-- Copyright 2007-2016 Technische Universitaet Dresden - Germany
-- Chair for VLSI-Design, Diagnostics and Architecture
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- =============================================================================
--
-- Issue:
-- I'm not sure if my experimental code is allowed in VHDL, but it let GHDL
-- crash. So I'm reporting just an unhandled exception.
--
-- GHDL's output is:
-- .\attribute.vhdl:64:58: can't match 'image attribute with type character
-- .\attribute.vhdl:64:53: (location of 'image attribute)
-- finish_sem_name: cannot handle IIR_KIND_OVERLOAD_LIST (??:??:??)
--
-- ******************** GHDL Bug occured ****************************
-- Please report this bug on https://github.com/tgingold/ghdl/issues
-- GHDL release: GHDL 0.34dev (commit: 2016-02-11; git branch: paebbels/master'; hash: f24fdfb) [Dunoon edition]
-- Compiled with GNAT Version: GPL 2015 (20150428-49)
-- In directory: H:\Austausch\PoC\temp\ghdl\
-- Command line:
-- C:\Tools\GHDL.new\bin\ghdl.exe -a --std=08 .\attribute.vhdl
-- Exception TYPES.INTERNAL_ERROR raised
-- Exception information:
-- Exception name: TYPES.INTERNAL_ERROR
-- Message: errorout.adb:66
-- ******************************************************************
--
-- GHDL calls:
-- PS> ghdl.exe -a --std=93c .\attribute.vhdl
-- PS> ghdl.exe -a --std=08 .\attribute.vhdl
--
library IEEE;
use IEEE.std_logic_1164.all;
entity test is
end entity;
architecture tb of test is
function to_string(slv : STD_LOGIC_VECTOR) return STRING is
variable Result : STRING(slv'length - 1 downto 0);
begin
for i in slv'range loop
Result(i + 1) := STD_LOGIC'image(slv(i));
end loop;
return Result;
end function;
attribute serialize : to_string;
signal mySignal : STD_LOGIC_VECTOR(7 downto 0);
attribute serialize of mySignal : signal is to_string[STD_LOGIC_VECTOR return STRING];
begin
mySignal <= x"24";
process
begin
report "mySignal=" & mySignal'serialize severity NOTE;
wait;
end process;
end architecture;
| gpl-2.0 | 6388258d006c4601b911f741683494ca | 0.60608 | 3.505669 | false | false | false | false |
hacklabmikkeli/rough-boy | synthesizer.vhdl | 2 | 4,676 | --
-- Knobs Galore - a free phase distortion synthesizer
-- Copyright (C) 2015 Ilmo Euro
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
use work.common.all;
entity synthesizer is
port (CLK: in std_logic
;KEYS_PROBE: out std_logic_vector(4 downto 0)
;KEYS_IN: in std_logic_vector(7 downto 0)
;CPANEL_PROBE: out std_logic_vector(4 downto 0)
;CPANEL_IN: in std_logic_vector(7 downto 0)
;LINE_LEFT_NEG: out std_logic
;LINE_LEFT_POS: out std_logic
;LINE_RIGHT_NEG: out std_logic
;LINE_RIGHT_POS: out std_logic
)
;
end entity;
architecture synthesizer_impl of synthesizer is
signal clk_even: std_logic := '0';
signal clk_odd: std_logic := '0';
signal clk_fast: std_logic := '0';
signal clk_slow: std_logic := '0';
signal counter: unsigned(8 downto 0) := (others => '0');
signal key_code: keys_signal;
signal key_event: key_event_t;
signal cpanel_key_code: keys_signal;
signal cpanel_key_event: key_event_t;
signal freq: time_signal := (others => '0');
signal gate: std_logic;
signal params: synthesis_params;
signal fifo_in: state_vector_t;
signal fifo_out: state_vector_t;
signal z_ampl: voice_signal;
signal audio_buf: audio_signal;
signal v_out: std_logic;
begin
process (CLK)
begin
if rising_edge(CLK) then
if counter = to_unsigned(61, 9) then
counter <= "000000000";
else
counter <= counter + 1;
end if;
end if;
end process;
clk_even <= '1' when std_match(counter, "000000---") else '0';
clk_odd <= '1' when std_match(counter, "000100---") else '0';
clk_fast <= CLK;
clk_slow <= '1' when std_match(counter, "1--------") else '0';
cpanel_input_buffer:
entity
work.input_buffer (input_buffer_impl)
port map
('1'
,clk_even
,CPANEL_IN
,CPANEL_PROBE
,cpanel_key_code
,cpanel_key_event
,open
);
input_buffer:
entity
work.input_buffer (input_buffer_impl)
port map
('1'
,clk_even
,KEYS_IN
,KEYS_PROBE
,key_code
,key_event
,open
);
voice_allocator:
entity
work.voice_allocator (voice_allocator_impl)
port map
('1'
,clk_odd
,params.sp_transform
,key_code
,key_event
,freq
,gate
);
preset_selector:
entity
work.preset_selector (preset_selector_impl)
port map
('1'
,clk_odd
,cpanel_key_code
,cpanel_key_event
,params
);
circular_buffer:
entity
work.circular_buffer (circular_buffer_impl)
port map
('1'
,clk_odd
,fifo_in
,fifo_out
);
voice_generator:
entity
work.voice_generator (voice_generator_impl)
port map
('1'
,clk_even
,clk_odd
,freq
,gate
,params
,z_ampl
,fifo_in
,fifo_out
);
mixer:
entity
work.mixer (mixer_impl)
port map
('1'
,clk_odd
,z_ampl
,audio_buf
);
dac:
entity
work.delta_sigma_dac(delta_sigma_dac_impl)
port map
('1'
,clk_fast
,audio_buf
,v_out
);
LINE_LEFT_NEG <= v_out;
LINE_LEFT_POS <= v_out;
LINE_RIGHT_POS <= '0';
LINE_RIGHT_NEG <= '0';
end architecture;
| gpl-3.0 | 15f3f87b62c60b80774080c9e0435b8d | 0.516039 | 3.890183 | false | false | false | false |
emogenet/ghdl | testsuite/vests/vhdl-93/ashenden/compliant/ap_a_ap_a_02.vhd | 4 | 2,897 |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ap_a_ap_a_02.vhd,v 1.2 2001-10-26 16:29:33 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
entity ap_a_02 is
end entity ap_a_02;
library ieee; use ieee.std_logic_1164.all;
architecture test of ap_a_02 is
-- code from book
-- end code from book
begin
b1 : block is
signal sulv : std_ulogic_vector(7 downto 0);
signal slv : std_logic_vector(7 downto 0);
begin
-- code from book
sulv <= To_stdulogicvector ( slv );
-- end code from book
slv <= "10101010";
end block b1;
b2 : block is
signal sulv : std_ulogic_vector(7 downto 0);
signal slv : std_logic_vector(7 downto 0);
begin
-- code from book
slv <= To_stdlogicvector ( sulv );
-- end code from book
sulv <= "00001111";
end block b2;
b3 : block is
signal a, ena, y : std_logic;
begin
-- code from book
y <= a when ena = '1' else
'Z';
-- end code from book
ena <= '0', '1' after 20 ns, '0' after 40 ns;
a <= '0', '1' after 10 ns, '0' after 30 ns, '1' after 50 ns;
end block b3;
b4 : block is
signal a, ena, y : std_logic;
begin
-- code from book
y <= a when ena = '1' else
'H';
-- end code from book
ena <= '0', '1' after 20 ns, '0' after 40 ns;
a <= '0', '1' after 10 ns, '0' after 30 ns, '1' after 50 ns;
end block b4;
b5 : block is
signal a, b, x, s, y : std_logic;
begin
-- code from book
y <= a when x = '1' else
b when s = '1' else
'-';
-- end code from book
x <= '0', '1' after 20 ns, '0' after 40 ns;
s <= '0', '1' after 60 ns, '0' after 80 ns;
a <= '0', '1' after 10 ns, '0' after 30 ns,
'1' after 50 ns, '0' after 70 ns,
'1' after 90 ns;
b <= '0', '1' after 15 ns, '0' after 35 ns,
'1' after 55 ns, '0' after 75 ns,
'1' after 95 ns;
end block b5;
end architecture test;
| gpl-2.0 | aec9b6207d0e3cc7fc9d37a699e85ad4 | 0.550915 | 3.494572 | false | false | false | false |
pmh92/Proyecto-OFDM | test/est_tb.vhd | 1 | 3,375 | ---------------------------------------
-- 7/JUL/2015 - Pedro Morales Hernandez
-- Testbench del Estimador
---------------------------------------
-- Importacion de librerias
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE work.vhdl_verification.ALL;
ENTITY est_tb IS
END est_tb;
ARCHITECTURE behavior OF est_tb IS
-- Declaracion de la UUT
COMPONENT ESTIMADOR
PORT(
clk : IN std_logic;
rst : IN std_logic;
start : IN std_logic;
fin : OUT std_logic;
addr_y : OUT std_logic_vector(10 downto 0);
addr_h : OUT std_logic_vector(10 downto 0);
y_data : IN std_logic_vector(19 downto 0);
h_data : OUT std_logic_vector(23 downto 0);
write_h : OUT std_logic_vector(0 downto 0)
);
END COMPONENT;
COMPONENT DPRAM_10 IS -- Contiene los datos de entrada
PORT (
clka : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(10 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(19 DOWNTO 0);
clkb : IN STD_LOGIC;
addrb : IN STD_LOGIC_VECTOR(10 DOWNTO 0);
doutb : OUT STD_LOGIC_VECTOR(19 DOWNTO 0)
);
END COMPONENT;
COMPONENT DPRAM_12 -- Almacena los datos de salida
PORT (
clka : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(10 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
clkb : IN STD_LOGIC;
addrb : IN STD_LOGIC_VECTOR(10 DOWNTO 0);
doutb : OUT STD_LOGIC_VECTOR(23 DOWNTO 0)
);
END COMPONENT;
-- Entradas
signal clk : std_logic := '0';
signal rst : std_logic := '0';
signal start : std_logic := '0';
signal y_data : std_logic_vector(19 downto 0) := (others => '0');
-- Salidas
signal fin : std_logic;
signal addr_y : std_logic_vector(10 downto 0);
signal addr_h : std_logic_vector(10 downto 0);
signal h_data : std_logic_vector(23 downto 0);
signal h_out : std_logic_vector(23 downto 0);
signal write_h : std_logic_vector(0 downto 0);
-- Periodo de Reloj
constant clk_period : time := 10 ns;
BEGIN
-- Instanciacion de las memorias
y_mem : DPRAM_10
PORT MAP(
clka => clk,
wea => "0",
addra => (OTHERS => '0'),
dina => (OTHERS => '0'),
clkb=> clk,
addrb => addr_y,
doutb => y_data
);
h_mem : DPRAM_12
PORT MAP (
clka => clk,
wea => write_h,
addra => addr_h,
dina => h_data,
clkb => clk,
addrb => (OTHERS => '0'),
doutb => h_out
);
-- Instanciacion de la UUT
uut: ESTIMADOR
PORT MAP (
clk => clk,
rst => rst,
start => start,
fin => fin,
addr_y => addr_y,
addr_h => addr_h,
y_data => y_data,
h_data => h_data,
write_h => write_h
);
-- Datawrite nos permite escribir en ficheros
dw : datawrite
GENERIC MAP (
OUTPUT_FILE => "./output/h_est.txt",
OUTPUT_NIBBLES => 6,
DATA_WIDTH => 24 )
PORT MAP (
clk => clk,
data => h_data,
valid => write_h(0),
endsim => fin
);
-- Proceso de reloj
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
-- Proceso de estimulos
stim_proc: process
begin
-- Reset
rst <= '1';
wait for 45 ns;
rst <= '0';
wait until rising_edge(clk);
-- Inicia
start <= '1';
wait for clk_period;
start <= '0';
wait;
end process;
END;
| gpl-2.0 | 1c5197087d1ef1a459300a6e9cd4060a | 0.570667 | 3.085009 | false | false | false | false |
hacklabmikkeli/rough-boy | voice_controller.vhdl | 2 | 8,954 | --
-- Knobs Galore - a free phase distortion synthesizer
-- Copyright (C) 2015 Ilmo Euro
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
library ieee;
library work;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
use work.common.all;
entity voice_controller is
port (EN: in std_logic
;CLK_EVEN: in std_logic
;CLK_ODD: in std_logic
;MODE: in mode_t
;FREQ: in time_signal
;CUTOFF_IN: in time_signal
;CUTOFF_OUT: out ctl_signal
;GAIN_IN: in time_signal
;GAIN_OUT: out ctl_signal
;THETA_REF: in time_signal
;THETA_OUT: out ctl_signal
;WAVEFORM: out waveform_t
)
;
end entity;
architecture voice_controller_impl of voice_controller is
type lut_t is array(0 to ctl_hi) of unsigned(ctl_bits + 3 downto 0);
function make_cutoff_to_fact
return lut_t is
variable zero: unsigned(ctl_bits + 3 downto 0) := (others => '0');
variable log_cutoff: integer;
variable fact: integer;
variable retval: lut_t := (others => (others => '0'));
begin
for i in 0 to 254 loop
log_cutoff := integer(log2(real(i+1)) * 32.0);
if log_cutoff > 255 then
log_cutoff := 255;
end if;
fact := 4096 / (256 - log_cutoff);
if fact > 4095 then
fact := 4095;
end if;
retval(i) := to_unsigned(fact, ctl_bits + 4);
end loop;
retval(255) := not zero;
return retval;
end function;
constant cutoff_to_fact: lut_t := make_cutoff_to_fact;
signal s1_theta_osc1: ctl_signal := (others => '0');
signal s1_theta_osc2_fat: ctl_signal := (others => '0');
signal s1_theta_osc2_res: ctl_signal := (others => '0');
signal s1_cutoff: ctl_signal := (others => '0');
signal s1_gain: ctl_signal := (others => '0');
signal s1_gain_windowed: ctl_signal := (others => '0');
signal s1_wave_sel: std_logic := '0';
signal s1_mode: mode_t := mode_saw;
signal s2_waveform_buf: waveform_t := waveform_saw;
signal s2_cutoff_out_buf: ctl_signal := (others => '0');
signal s2_theta_out_buf: ctl_signal := (others => '0');
signal s2_gain_out_buf: ctl_signal := (others => '0');
signal s3_waveform_buf: waveform_t := waveform_saw;
signal s3_cutoff_out_buf: ctl_signal := (others => '0');
signal s3_theta_out_buf: ctl_signal := (others => '0');
signal s3_gain_out_buf: ctl_signal := (others => '0');
begin
process (CLK_EVEN)
variable cutoff: ctl_signal;
variable theta_osc1: ctl_signal;
variable theta_osc1_wide: unsigned(time_bits * 2 - 1 downto 0);
variable fact_osc2_fat: ctl_signal := ('1', others => '0');
variable fact_osc2_res: unsigned(ctl_bits + 3 downto 0);
variable theta_osc2_fat_wide: unsigned(ctl_bits * 2 - 1 downto 0);
variable theta_osc2_fat: ctl_signal;
variable theta_osc2_res_wide: unsigned(ctl_bits * 2 + 3 downto 0);
variable theta_osc2_res: ctl_signal;
variable gain_windowed_wide: unsigned(ctl_bits * 2 - 1 downto 0);
begin
if EN = '1' and rising_edge(CLK_EVEN) then
cutoff := to_ctl(CUTOFF_IN);
theta_osc1_wide := THETA_REF * FREQ;
theta_osc1 := theta_osc1_wide(time_bits - 2
downto time_bits - ctl_bits - 1);
if THETA_REF(time_bits-2) = '1' then
fact_osc2_fat(6 downto 0)
:= THETA_REF(time_bits-2 downto time_bits-8);
else
fact_osc2_fat(6 downto 0)
:= not THETA_REF(time_bits-2 downto time_bits-8);
end if;
theta_osc2_fat_wide := fact_osc2_fat * theta_osc1;
theta_osc2_fat := theta_osc2_fat_wide(time_bits-3
downto time_bits-ctl_bits-2);
fact_osc2_res := cutoff_to_fact(to_integer(cutoff));
theta_osc2_res_wide := fact_osc2_res * theta_osc1;
theta_osc2_res := theta_osc2_res_wide(ctl_bits + 3 downto 4);
gain_windowed_wide := to_ctl(GAIN_IN) * not theta_osc1;
s1_theta_osc1 <= theta_osc1;
s1_theta_osc2_fat <= theta_osc2_fat;
s1_theta_osc2_res <= theta_osc2_res;
s1_cutoff <= cutoff;
s1_gain <= to_ctl(GAIN_IN);
s1_gain_windowed <= gain_windowed_wide(ctl_bits * 2 - 1
downto ctl_bits);
s1_wave_sel <= theta_osc1_wide(time_bits - 1);
s1_mode <= MODE;
end if;
end process;
process (CLK_ODD)
begin
if EN = '1' and rising_edge(CLK_ODD) then
case s1_mode is
when mode_saw
| mode_saw_fat
| mode_saw_res
| mode_saw_sync =>
s2_waveform_buf <= waveform_saw;
when mode_sq
| mode_sq_fat
| mode_sq_res =>
s2_waveform_buf <= waveform_sq;
when mode_mix =>
if s1_wave_sel = '0' then
s2_waveform_buf <= waveform_saw;
else
s2_waveform_buf <= waveform_sq;
end if;
when others =>
null;
end case;
case s1_mode is
when mode_saw
| mode_saw_fat
| mode_sq
| mode_sq_fat
| mode_saw_sync
| mode_mix =>
s2_cutoff_out_buf <= s1_cutoff;
when mode_saw_res
| mode_sq_res =>
if s1_wave_sel = '0' then
s2_cutoff_out_buf <= s1_cutoff;
else
s2_cutoff_out_buf <= (others => '0');
end if;
when others =>
null;
end case;
case s1_mode is
when mode_saw
| mode_sq
| mode_mix =>
s2_theta_out_buf <= s1_theta_osc1;
when mode_saw_fat
| mode_sq_fat =>
if s1_wave_sel = '0' then
s2_theta_out_buf <= s1_theta_osc1;
else
s2_theta_out_buf <= s1_theta_osc2_fat;
end if;
when mode_saw_res
| mode_sq_res
| mode_saw_sync =>
if s1_wave_sel = '0' then
s2_theta_out_buf <= s1_theta_osc1;
else
s2_theta_out_buf <= s1_theta_osc2_res;
end if;
when others =>
null;
end case;
case s1_mode is
when mode_saw
| mode_sq
| mode_mix =>
s2_gain_out_buf <= s1_gain;
when mode_saw_fat
| mode_sq_fat
| mode_saw_res
| mode_sq_res
| mode_saw_sync =>
if s1_wave_sel = '0' then
s2_gain_out_buf <= s1_gain;
else
s2_gain_out_buf <= s1_gain_windowed;
end if;
when others =>
null;
end case;
end if;
end process;
process(CLK_EVEN)
begin
if EN='1' and rising_edge(CLK_EVEN) then
s3_waveform_buf <= s2_waveform_buf;
s3_cutoff_out_buf <= s2_cutoff_out_buf;
s3_theta_out_buf <= s2_theta_out_buf;
s3_gain_out_buf <= s2_gain_out_buf;
end if;
end process;
WAVEFORM <= s3_waveform_buf;
CUTOFF_OUT <= s3_cutoff_out_buf;
THETA_OUT <= s3_theta_out_buf;
GAIN_OUT <= s3_gain_out_buf;
end architecture;
| gpl-3.0 | 319f3966480833446c6685ea048b2459 | 0.480009 | 3.718439 | false | false | false | false |
emogenet/ghdl | testsuite/gna/issue38/bugreport_aliasprotected.vhdl | 1 | 6,522 | -- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
-- =============================================================================
-- Authors: Patrick Lehmann
-- Reproducer: Using aliases to protected type methods cause an exception.
--
-- License:
-- =============================================================================
-- Copyright 2007-2016 Technische Universitaet Dresden - Germany
-- Chair for VLSI-Design, Diagnostics and Architecture
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- =============================================================================
--
-- Issue 1:
-- When analyzed in VHDL-93 mode an error is reported:
-- .\bugreport_aliasprotected.vhdl:4:26: protected type not allowed in vhdl87/93
-- .\bugreport_aliasprotected.vhdl:9:12: 'protected' is expected instead of 'protected'
-- Line 1 is perfectly clear, but what is the intension of line 2?
-- Is this follow up error necessary or should it have another message text?
--
-- Issue 2:
-- Calling an aliases to a shared variable's method causes an exception in GHDL:
-- ******************** GHDL Bug occured ****************************
-- Please report this bug on https://github.com/tgingold/ghdl/issues
-- GHDL release: GHDL 0.34dev (commit: 2016-01-27; git branch: paebbels/master'; hash: d424eb8) [Dunoon edition]
-- Compiled with GNAT Version: GPL 2015 (20150428-49)
-- In directory: H:\Austausch\PoC\temp\ghdl\
-- Command line:
-- C:\Tools\GHDL.new\bin\ghdl.exe -r --std=08 test
-- Exception TYPES.INTERNAL_ERROR raised
-- Exception information:
-- Exception name: TYPES.INTERNAL_ERROR
-- Message: trans.adb:487
-- ******************************************************************
-- The alias definition by itself is not causing any errors. In my big example, I
-- could at least use an alias to a procedure without parameters. This short example
-- throws exceptions on all 4 variants (with/without parameter; with/without return value).
--
-- You can comment/uncomment the alias/wrapping function/procedure to cause the error.
--
-- GHDL calls:
-- PS> ghdl.exe -a --std=08 .\bugreport_aliasprotected.vhdl
-- PS> ghdl.exe -r --std=08 test
--
-- Expected output:
-- .\bugreport_aliasprotected.vhdl:163:16:@0ms:(report note): wrapGet: 7 expected: 7
-- .\bugreport_aliasprotected.vhdl:165:16:@0ms:(report note): wrapGet: 5 expected: 5
-- .\bugreport_aliasprotected.vhdl:166:16:@0ms:(report note): wrapExcahnge: 5 expected: 5
-- .\bugreport_aliasprotected.vhdl:167:16:@0ms:(report note): wrapGet: 3 expected: 3
-- .\bugreport_aliasprotected.vhdl:169:16:@0ms:(report note): wrapGet: 0 expected: 0
--
-- =============================================================================
-- Protected type package
-- =============================================================================
package pkg is
type T_INTEGER is protected
procedure Clear;
procedure Set(Value : INTEGER);
impure function Get return INTEGER;
impure function Exchange(Value : INTEGER) return INTEGER;
end protected;
end package;
package body pkg is
type T_INTEGER is protected body
variable LocalVariable : INTEGER := 7;
procedure Clear is
begin
LocalVariable := 0;
end procedure;
procedure Set(Value : INTEGER) is
begin
LocalVariable := Value;
end procedure;
impure function Get return INTEGER is
begin
return LocalVariable;
end function;
impure function Exchange(Value : INTEGER) return INTEGER is
variable Result : INTEGER;
begin
Result := LocalVariable;
LocalVariable := Value;
return Result;
end function;
end protected body;
end package body;
-- =============================================================================
-- Wrapper package
-- =============================================================================
use work.pkg.all;
package wrapper is
shared variable MyBoolean : T_INTEGER;
-- alias wrapClear is MyBoolean.Clear[]; -- if this alias is used, GHDL crashes
alias wrapperClear is MyBoolean.Clear[]; -- unused alias => no crash
procedure wrapClear; -- wrapped by a call chain => no crash
-- alias wrapSet is MyBoolean.Set[INTEGER];
procedure wrapSet(Value : INTEGER);
-- alias wrapGet is MyBoolean.Get[return INTEGER];
impure function wrapGet return INTEGER;
-- alias wrapExchange is MyBoolean.Exchange[INTEGER return INTEGER];
impure function wrapExchange(Value : INTEGER) return INTEGER;
end package;
package body wrapper is
procedure wrapClear is
begin
MyBoolean.Clear;
end procedure;
procedure wrapSet(Value : INTEGER) is
begin
MyBoolean.Set(Value);
end procedure;
impure function wrapGet return INTEGER is
begin
return MyBoolean.Get;
end function;
impure function wrapExchange(Value : INTEGER) return INTEGER is
begin
return MyBoolean.Exchange(Value);
end function;
end package body;
-- =============================================================================
-- Testbench
-- =============================================================================
use work.wrapper.all;
entity test is
end entity;
architecture tb of test is
begin
process
begin
report "wrapGet: " & INTEGER'image(wrapGet) & " expected: 7" severity NOTE;
wrapSet(5);
report "wrapGet: " & INTEGER'image(wrapGet) & " expected: 5" severity NOTE;
report "wrapExcahnge: " & INTEGER'image(wrapExchange(3)) & " expected: 5" severity NOTE;
report "wrapGet: " & INTEGER'image(wrapGet) & " expected: 3" severity NOTE;
wrapperClear;
report "wrapGet: " & INTEGER'image(wrapGet) & " expected: 0" severity NOTE;
wait;
end process;
end architecture;
| gpl-2.0 | 8897cf63a59f2b6138bf0120737515a9 | 0.599663 | 3.816267 | false | false | false | false |
pmh92/Proyecto-OFDM | test/equalizer_tb.vhd | 1 | 3,899 | ---------------------------------------
-- 10/JUL/2015 - Pedro Morales Hernandez
-- Modulo del Ecualizador
---------------------------------------
-- Importacion de librerias
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY equalizer_tb IS
END equalizer_tb;
ARCHITECTURE behavior OF equalizer_tb IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT ECUALIZADOR
PORT(
clk : IN std_logic;
rst : IN std_logic;
start : IN std_logic;
fin : OUT std_logic;
y_data : IN std_logic_vector(19 downto 0);
h_data : IN std_logic_vector(23 downto 0);
y_est_data : OUT std_logic_vector(23 downto 0);
y_addr : OUT std_logic_vector(10 downto 0);
h_addr : OUT std_logic_vector(10 downto 0);
y_est_addr : OUT std_logic_vector(10 downto 0);
write_y_est : OUT std_logic_vector(0 downto 0)
);
END COMPONENT;
COMPONENT DPRAM_10 IS -- Contiene los datos de entrada
PORT (
clka : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(10 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(19 DOWNTO 0);
clkb : IN STD_LOGIC;
addrb : IN STD_LOGIC_VECTOR(10 DOWNTO 0);
doutb : OUT STD_LOGIC_VECTOR(19 DOWNTO 0)
);
END COMPONENT;
COMPONENT DPRAM_12 -- Almacena el canal interpolado
PORT (
clka : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(10 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
clkb : IN STD_LOGIC;
addrb : IN STD_LOGIC_VECTOR(10 DOWNTO 0);
doutb : OUT STD_LOGIC_VECTOR(23 DOWNTO 0)
);
END COMPONENT;
COMPONENT SPRAM_12 -- Almacena el simbolo ecualizado
PORT (
clka : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(10 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(23 DOWNTO 0)
);
END COMPONENT;
--Inputs
signal clk : std_logic := '0';
signal rst : std_logic := '0';
signal start : std_logic := '0';
signal y_data : std_logic_vector(19 downto 0) := (others => '0');
signal h_data : std_logic_vector(23 downto 0) := (others => '0');
--Outputs
signal fin : std_logic;
signal y_est_data : std_logic_vector(23 downto 0);
signal y_addr : std_logic_vector(10 downto 0);
signal h_addr : std_logic_vector(10 downto 0);
signal y_est_addr : std_logic_vector(10 downto 0);
signal write_y_est : std_logic_vector(0 downto 0);
signal y_est_out : std_logic_vector(23 downto 0);
-- Clock period definitions
constant clk_period : time := 10 ns;
BEGIN
y_mem : DPRAM_10
PORT MAP(
clka => clk,
wea => "0",
addra => (OTHERS => '0'),
dina => (OTHERS => '0'),
clkb=> clk,
addrb => y_addr,
doutb => y_data
);
h_mem : DPRAM_12
PORT MAP (
clka => clk,
wea => "0",
addra => (OTHERS => '0'),
dina => (OTHERS => '0'),
clkb => clk,
addrb => h_addr,
doutb => h_data
);
y_est_mem : SPRAM_12
PORT MAP (
clka => clk,
wea => write_y_est,
addra => y_est_addr,
dina => y_est_data,
douta => y_est_out
);
-- Instantiate the Unit Under Test (UUT)
uut: ECUALIZADOR PORT MAP (
clk => clk,
rst => rst,
start => start,
fin => fin,
y_data => y_data,
h_data => h_data,
y_est_data => y_est_data,
y_addr => y_addr,
h_addr => h_addr,
y_est_addr => y_est_addr,
write_y_est => write_y_est
);
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
rst <= '1';
wait for 45 ns;
rst <= '0';
wait until rising_edge(clk);
start <= '1';
wait for clk_period;
start <= '0';
wait;
end process;
END;
| gpl-2.0 | a31dc599e28c44870505195abb214a8a | 0.575532 | 3.096902 | false | false | false | false |
maxburkhardt/portapack-hackrf | hardware/portapack_h1/cpld/top.vhd | 1 | 4,890 | --
-- Copyright (C) 2012 Jared Boone, ShareBrained Technology, Inc.
--
-- This file is part of PortaPack.
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2, or (at your option)
-- any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; see the file COPYING. If not, write to
-- the Free Software Foundation, Inc., 51 Franklin Street,
-- Boston, MA 02110-1301, USA.
library ieee;
use ieee.std_logic_1164.all;
entity top is
port (
MCU_D : inout std_logic_vector(7 downto 0);
MCU_DIR : in std_logic;
MCU_IO_STBX : in std_logic;
MCU_LCD_WR : in std_logic;
MCU_ADDR : in std_logic;
MCU_LCD_TE : out std_logic;
MCU_P2_8 : in std_logic;
MCU_LCD_RD : in std_logic;
TP_U : out std_logic;
TP_D : out std_logic;
TP_L : out std_logic;
TP_R : out std_logic;
SW_SEL : in std_logic;
SW_ROT_A : in std_logic;
SW_ROT_B : in std_logic;
SW_U : in std_logic;
SW_D : in std_logic;
SW_L : in std_logic;
SW_R : in std_logic;
LCD_RESETX : out std_logic;
LCD_RS : out std_logic;
LCD_WRX : out std_logic;
LCD_RDX : out std_logic;
LCD_DB : inout std_logic_vector(15 downto 0);
LCD_TE : in std_logic;
LCD_BACKLIGHT : out std_logic
);
end top;
architecture rtl of top is
signal switches : std_logic_vector(7 downto 0);
type data_direction_t is (from_mcu, to_mcu);
signal data_dir : data_direction_t;
signal mcu_data_out_lcd : std_logic_vector(7 downto 0);
signal mcu_data_out_io : std_logic_vector(7 downto 0);
signal mcu_data_out : std_logic_vector(7 downto 0);
signal mcu_data_in : std_logic_vector(7 downto 0);
signal lcd_data_in : std_logic_vector(15 downto 0);
signal lcd_data_in_mux : std_logic_vector(7 downto 0);
signal lcd_data_out : std_logic_vector(15 downto 0);
signal lcd_data_in_q : std_logic_vector(7 downto 0) := (others => '0');
signal lcd_data_out_q : std_logic_vector(7 downto 0) := (others => '0');
signal tp_q : std_logic_vector(7 downto 0) := (others => '0');
signal lcd_reset_q : std_logic := '1';
signal lcd_backlight_q : std_logic := '0';
signal dir_read : boolean;
signal dir_write : boolean;
signal lcd_read_strobe : boolean;
signal lcd_write_strobe : boolean;
signal lcd_write : boolean;
signal io_strobe : boolean;
signal io_read_strobe : boolean;
signal io_write_strobe : boolean;
begin
-- I/O data
switches <= LCD_TE & not SW_ROT_B & not SW_ROT_A & not SW_SEL & not SW_U & not SW_D & not SW_L & not SW_R;
TP_U <= tp_q(3) when tp_q(7) = '1' else 'Z';
TP_D <= tp_q(2) when tp_q(6) = '1' else 'Z';
TP_L <= tp_q(1) when tp_q(5) = '1' else 'Z';
TP_R <= tp_q(0) when tp_q(4) = '1' else 'Z';
LCD_BACKLIGHT <= lcd_backlight_q;
MCU_LCD_TE <= LCD_TE;
-- State management
data_dir <= to_mcu when MCU_DIR = '1' else from_mcu;
dir_read <= (data_dir = to_mcu);
dir_write <= (data_dir = from_mcu);
io_strobe <= (MCU_IO_STBX = '0');
io_read_strobe <= io_strobe and dir_read;
lcd_read_strobe <= (MCU_LCD_RD = '1');
lcd_write <= not lcd_read_strobe;
-- LCD interface
LCD_RS <= MCU_ADDR;
LCD_RDX <= not MCU_LCD_RD;
LCD_WRX <= not MCU_LCD_WR;
lcd_data_out <= lcd_data_out_q & mcu_data_in;
lcd_data_in <= LCD_DB;
LCD_DB <= lcd_data_out when lcd_write else (others => 'Z');
LCD_RESETX <= not lcd_reset_q;
-- MCU interface
mcu_data_out_lcd <= lcd_data_in(15 downto 8) when lcd_read_strobe else lcd_data_in_q;
mcu_data_out_io <= switches;
mcu_data_out <= mcu_data_out_io when io_read_strobe else mcu_data_out_lcd;
mcu_data_in <= MCU_D;
MCU_D <= mcu_data_out when dir_read else (others => 'Z');
-- Synchronous behaviors:
-- LCD write: Capture LCD high byte on LCD_WRX falling edge.
process(MCU_LCD_WR, mcu_data_in)
begin
if rising_edge(MCU_LCD_WR) then
lcd_data_out_q <= mcu_data_in;
end if;
end process;
-- LCD read: Capture LCD low byte on LCD_RD falling edge.
process(MCU_LCD_RD, lcd_data_in)
begin
if falling_edge(MCU_LCD_RD) then
lcd_data_in_q <= lcd_data_in(7 downto 0);
end if;
end process;
-- I/O write (to resistive touch panel): Capture data from
-- MCU and hold on TP pins until further notice.
process(MCU_IO_STBX, dir_write, mcu_data_in, MCU_ADDR)
begin
if rising_edge(MCU_IO_STBX) and dir_write then
if MCU_ADDR = '0' then
tp_q <= mcu_data_in;
else
lcd_reset_q <= mcu_data_in(0);
lcd_backlight_q <= mcu_data_in(7);
end if;
end if;
end process;
end rtl;
| gpl-2.0 | 2135bb869af046ae16f6815928814454 | 0.646626 | 2.546875 | false | false | false | false |
emogenet/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc2184.vhd | 4 | 1,915 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2184.vhd,v 1.2 2001-10-26 16:29:46 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b05x00p01n02i02184ent IS
END c07s02b05x00p01n02i02184ent;
ARCHITECTURE c07s02b05x00p01n02i02184arch OF c07s02b05x00p01n02i02184ent IS
BEGIN
TESTING: PROCESS
type PHYS is range 0 to 1000
units
A;
B = 10 A;
C = 10 B;
D = 10 C;
end units;
variable k : PHYS := 1 A;
variable m : PHYS := 5 B;
BEGIN
k := + m;
assert NOT( k = 5 B )
report "***PASSED TEST: c07s02b05x00p01n02i02184"
severity NOTE;
assert ( k = 5 B )
report "***FAILED TEST: c07s02b05x00p01n02i02184 - For each of these unary operators, the operand and the result have the same type."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b05x00p01n02i02184arch;
| gpl-2.0 | bd0fe4658ff40c13f1320393d27ee276 | 0.643864 | 3.633776 | false | true | false | false |
emogenet/ghdl | testsuite/gna/issue72/fixed.vhdl | 2 | 630 | library ieee;
use ieee.std_logic_1164.all;
use work.issue_pkg.t_one_two; -- does not work
use work.issue_pkg."=";
--use work.issue_pkg.all; -- works
entity issue is
port (
clk : in std_logic;
input : in t_one_two;
output : out std_logic
);
end entity issue;
architecture rtl of issue is
begin -- architecture rtl
process (clk) is
begin -- process
if clk'event and clk = '1' then -- rising clock edge
if input = work.issue_pkg.one then
output <= '1';
else
output <= '0';
end if;
end if;
end process;
end architecture rtl;
| gpl-2.0 | 94c59ef68633a3edc0814fd279e82efe | 0.579365 | 3.333333 | false | false | false | false |
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