repo_name
stringlengths 6
79
| path
stringlengths 6
236
| copies
int64 1
472
| size
int64 137
1.04M
| content
stringlengths 137
1.04M
| license
stringclasses 15
values | hash
stringlengths 32
32
| alpha_frac
float64 0.25
0.96
| ratio
float64 1.51
17.5
| autogenerated
bool 1
class | config_or_test
bool 2
classes | has_no_keywords
bool 1
class | has_few_assignments
bool 1
class |
|---|---|---|---|---|---|---|---|---|---|---|---|---|
impedimentToProgress/UCI-BlueChip | AttackFiles/Attacks/privEsc/lib/techmap/gencomp/gencomp.vhd | 2 | 30,989 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Package: gencomp
-- File: gencomp.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: Delcation of portable memory modules
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
package gencomp is
---------------------------------------------------------------------------
-- BASIC DECLARATIONS
---------------------------------------------------------------------------
-- technologies and libraries
constant NTECH : integer := 31;
type tech_ability_type is array (0 to NTECH) of integer;
constant inferred : integer := 0;
constant virtex : integer := 1;
constant virtex2 : integer := 2;
constant memvirage : integer := 3;
constant axcel : integer := 4;
constant proasic : integer := 5;
constant atc18s : integer := 6;
constant altera : integer := 7;
constant umc : integer := 8;
constant rhumc : integer := 9;
constant apa3 : integer := 10;
constant spartan3 : integer := 11;
constant ihp25 : integer := 12;
constant rhlib18t : integer := 13;
constant virtex4 : integer := 14;
constant lattice : integer := 15;
constant ut25 : integer := 16;
constant spartan3e : integer := 17;
constant peregrine : integer := 18;
constant memartisan : integer := 19;
constant virtex5 : integer := 20;
constant custom1 : integer := 21;
constant ihp25rh : integer := 22;
constant stratix1 : integer := 23;
constant stratix2 : integer := 24;
constant eclipse : integer := 25;
constant stratix3 : integer := 26;
constant cyclone3 : integer := 27;
constant memvirage90 : integer := 28;
constant tsmc90 : integer := 29;
constant easic90 : integer := 30;
constant atc18rha : integer := 31;
constant DEFMEMTECH : integer := inferred;
constant DEFPADTECH : integer := inferred;
constant DEFFABTECH : integer := inferred;
constant is_fpga : tech_ability_type :=
(inferred => 1, virtex => 1, virtex2 => 1, axcel => 1,
proasic => 1, altera => 1, apa3 => 1, spartan3 => 1,
virtex4 => 1, lattice => 1, spartan3e => 1, virtex5 => 1,
stratix1 => 1, stratix2 => 1, eclipse => 1,
stratix3 => 1, cyclone3 => 1, others => 0);
constant infer_mul : tech_ability_type := is_fpga;
constant syncram_2p_write_through : tech_ability_type :=
(inferred => 0, virtex => 0, virtex2 => 1, memvirage => 1,
axcel => 0, proasic => 0, atc18s => 0, altera => 0,
umc => 0, rhumc => 1, apa3 => 0, spartan3 => 1,
ihp25 => 0, rhlib18t => 0, virtex4 => 1, lattice => 0,
ut25 => 0, spartan3e => 1, virtex5 => 1, eclipse => 1,
memvirage90 => 0, atc18rha => 1, others => 0);
constant regfile_3p_write_through : tech_ability_type :=
(inferred => 0, virtex => 0, virtex2 => 1, memvirage => 1,
axcel => 0, proasic => 0, atc18s => 0, altera => 0,
umc => 0, rhumc => 1, apa3 => 0, spartan3 => 1,
ihp25 => 1, rhlib18t => 0, virtex4 => 1, lattice => 0,
ut25 => 0, spartan3e => 1, virtex5 => 1, ihp25rh => 1,
eclipse => 1, memvirage90 => 0, atc18rha => 1, others => 0);
constant regfile_3p_infer : tech_ability_type :=
(inferred => 1, rhumc => 1, ihp25 => 1, rhlib18t => 0,
peregrine => 1, ihp25rh => 1, umc => 1, others => 0);
constant syncram_2p_dest_rw_collision : tech_ability_type :=
(memartisan => 1, others => 0);
constant syncram_dp_dest_rw_collision : tech_ability_type :=
(memartisan => 1, others => 0);
constant has_sram : tech_ability_type :=
(inferred => 1, virtex => 1, virtex2 => 1, memvirage => 1,
axcel => 1, proasic => 1, atc18s => 0, altera => 1,
umc => 1, rhumc => 1, apa3 => 1, spartan3 => 1,
ihp25 => 1, rhlib18t => 1, virtex4 => 1, lattice => 1,
ut25 => 1, spartan3e => 1, virtex5 => 1, eclipse => 1,
memvirage90 => 1, atc18rha => 1, others => 1);
constant has_2pram : tech_ability_type :=
( atc18s => 0, umc => 0, rhumc => 0, ihp25 => 0, others => 1);
constant has_dpram : tech_ability_type :=
(virtex => 1, virtex2 => 1, memvirage => 1, axcel => 1,
altera => 1, apa3 => 1, spartan3 => 1, virtex4 => 1,
lattice => 1, spartan3e => 1, memartisan => 1, virtex5 => 1,
custom1 => 1, stratix1 => 1, stratix2 => 1, stratix3 => 1,
cyclone3 => 1, memvirage90 => 1, atc18rha => 1, others => 0);
constant has_sram64 : tech_ability_type :=
(inferred => 0, virtex2 => 1, spartan3 => 1, virtex4 => 1,
spartan3e => 1, memartisan => 1, virtex5 => 1,
custom1 => 0, others => 0);
constant padoen_polarity : tech_ability_type :=
(inferred => 0, virtex => 0, virtex2 => 0, memvirage => 0,
axcel => 1, proasic => 1, atc18s => 0, altera => 0,
umc => 1, rhumc => 1, spartan3 => 0, apa3 => 1,
ihp25 => 1, rhlib18t => 0, virtex4 => 0, lattice => 0,
ut25 => 1, spartan3e => 0, peregrine => 1, easic90 => 1,
others => 0);
constant has_pads : tech_ability_type :=
(inferred => 0, virtex => 1, virtex2 => 1, memvirage => 0,
axcel => 1, proasic => 1, atc18s => 1, altera => 0,
umc => 1, rhumc => 1, apa3 => 1, spartan3 => 1,
ihp25 => 1, rhlib18t => 1, virtex4 => 1, lattice => 0,
ut25 => 1, spartan3e => 1, peregrine => 1, virtex5 => 1,
easic90 => 1, atc18rha => 1, others => 0);
constant has_ds_pads : tech_ability_type :=
(inferred => 0, virtex => 1, virtex2 => 1, memvirage => 0,
axcel => 1, proasic => 0, atc18s => 0, altera => 0,
umc => 0, rhumc => 0, apa3 => 0, spartan3 => 1,
ihp25 => 0, rhlib18t => 1, virtex4 => 1, lattice => 0,
ut25 => 1, spartan3e => 1, virtex5 => 1, others => 0);
constant has_ds_combo : tech_ability_type :=
( rhumc => 1, ut25 => 1, others => 0);
constant has_clkand : tech_ability_type :=
( virtex2 => 1, spartan3 => 1, spartan3e => 1, virtex4 => 1,
virtex5 => 1, ut25 => 1, others => 0);
constant has_clkmux : tech_ability_type :=
( virtex2 => 1, spartan3 => 1, spartan3e => 1, virtex4 => 1,
virtex5 => 1, others => 0);
constant has_techbuf : tech_ability_type :=
( virtex => 1, virtex2 => 1, virtex4 => 1, virtex5 => 1,
spartan3 => 1, spartan3e => 1, axcel => 1, ut25 => 1,
apa3 => 1, others => 0);
constant has_tapsel : tech_ability_type :=
( virtex => 1, virtex2 => 1, virtex4 => 1, virtex5 => 1,
spartan3 => 1, spartan3e => 1, others => 0);
constant need_extra_sync_reset : tech_ability_type :=
(axcel => 1, atc18s => 1, ut25 => 1, rhumc => 1, tsmc90 => 1,
rhlib18t => 1, atc18rha => 1, others => 0);
-- pragma translate_off
subtype tech_description is string(1 to 10);
type tech_table_type is array (0 to NTECH) of tech_description;
constant tech_table : tech_table_type := (
inferred => "inferred ", virtex => "virtex ",
virtex2 => "virtex2 ", memvirage => "virage ",
axcel => "axcel ", proasic => "proasic ",
atc18s => "atc18s ", altera => "altera ",
umc => "umc18 ", rhumc => "rhumc ",
apa3 => "proasic3 ", spartan3 => "spartan3 ",
ihp25 => "ihp25 ", rhlib18t => "rhlib18t ",
virtex4 => "virtex4 ", lattice => "lattice ",
ut25 => "ut025crh ", spartan3e => "spartan3e ",
peregrine => "peregrine ", memartisan => "artisan ",
virtex5 => "virtex5 ", custom1 => "custom1 ",
ihp25rh => "ihp25rh ", stratix1 => "stratix ",
stratix2 => "stratixii ", eclipse => "eclipse ",
stratix3 => "stratixiii", cyclone3 => "cycloneiii",
memvirage90 => "virage90 ", tsmc90 => "tsmc90 ",
easic90 => "nextreme ", atc18rha => "atc18rha "
);
-- pragma translate_on
-- input/output voltage
constant x18v : integer := 1;
constant x25v : integer := 2;
constant x33v : integer := 3;
constant x50v : integer := 5;
-- input/output levels
constant ttl : integer := 0;
constant cmos : integer := 1;
constant pci33 : integer := 2;
constant pci66 : integer := 3;
constant lvds : integer := 4;
constant sstl2_i : integer := 5;
constant sstl2_ii : integer := 6;
constant sstl3_i : integer := 7;
constant sstl3_ii : integer := 8;
constant sstl18_i : integer := 9;
constant sstl18_ii: integer := 10;
-- pad types
constant normal : integer := 0;
constant pullup : integer := 1;
constant pulldown : integer := 2;
constant opendrain: integer := 3;
constant schmitt : integer := 4;
constant dci : integer := 5;
---------------------------------------------------------------------------
-- MEMORY
---------------------------------------------------------------------------
-- synchronous single-port ram
component syncram
generic (tech : integer := 0; abits : integer := 6; dbits : integer := 8);
port (
clk : in std_ulogic;
address : in std_logic_vector((abits -1) downto 0);
datain : in std_logic_vector((dbits -1) downto 0);
dataout : out std_logic_vector((dbits -1) downto 0);
enable : in std_ulogic;
write : in std_ulogic;
testin : in std_logic_vector(3 downto 0) := "0000");
end component;
-- synchronous two-port ram (1 read, 1 write port)
component syncram_2p
generic (tech : integer := 0; abits : integer := 6; dbits : integer := 8; sepclk : integer := 0;
wrfst : integer := 0);
port (
rclk : in std_ulogic;
renable : in std_ulogic;
raddress : in std_logic_vector((abits -1) downto 0);
dataout : out std_logic_vector((dbits -1) downto 0);
wclk : in std_ulogic;
write : in std_ulogic;
waddress : in std_logic_vector((abits -1) downto 0);
datain : in std_logic_vector((dbits -1) downto 0);
testin : in std_logic_vector(3 downto 0) := "0000");
end component;
-- synchronous dual-port ram (2 read/write ports)
component syncram_dp
generic (tech : integer := 0; abits : integer := 6; dbits : integer := 8);
port (
clk1 : in std_ulogic;
address1 : in std_logic_vector((abits -1) downto 0);
datain1 : in std_logic_vector((dbits -1) downto 0);
dataout1 : out std_logic_vector((dbits -1) downto 0);
enable1 : in std_ulogic;
write1 : in std_ulogic;
clk2 : in std_ulogic;
address2 : in std_logic_vector((abits -1) downto 0);
datain2 : in std_logic_vector((dbits -1) downto 0);
dataout2 : out std_logic_vector((dbits -1) downto 0);
enable2 : in std_ulogic;
write2 : in std_ulogic;
testin : in std_logic_vector(3 downto 0) := "0000");
end component;
-- synchronous 3-port regfile (2 read, 1 write port)
component regfile_3p
generic (tech : integer := 0; abits : integer := 6; dbits : integer := 8;
wrfst : integer := 0; numregs : integer := 64);
port (
wclk : in std_ulogic;
waddr : in std_logic_vector((abits -1) downto 0);
wdata : in std_logic_vector((dbits -1) downto 0);
we : in std_ulogic;
rclk : in std_ulogic;
raddr1 : in std_logic_vector((abits -1) downto 0);
re1 : in std_ulogic;
rdata1 : out std_logic_vector((dbits -1) downto 0);
raddr2 : in std_logic_vector((abits -1) downto 0);
re2 : in std_ulogic;
rdata2 : out std_logic_vector((dbits -1) downto 0);
testin : in std_logic_vector(3 downto 0) := "0000");
end component;
-- 64-bit synchronous single-port ram with 32-bit write strobe
component syncram64
generic (tech : integer := 0; abits : integer := 6);
port (
clk : in std_ulogic;
address : in std_logic_vector (abits -1 downto 0);
datain : in std_logic_vector (63 downto 0);
dataout : out std_logic_vector (63 downto 0);
enable : in std_logic_vector (1 downto 0);
write : in std_logic_vector (1 downto 0);
testin : in std_logic_vector(3 downto 0) := "0000");
end component;
component syncramft
generic (tech : integer := 0; abits : integer := 6; dbits : integer := 8;
ft : integer range 0 to 2 := 0 );
port (
clk : in std_ulogic;
address : in std_logic_vector((abits -1) downto 0);
datain : in std_logic_vector((dbits -1) downto 0);
dataout : out std_logic_vector((dbits -1) downto 0);
write : in std_ulogic;
enable : in std_ulogic;
error : out std_logic_vector((dbits + 7) / 8 downto 0);
testin : in std_logic_vector(3 downto 0) := "0000");
end component;
component syncram_2pft
generic (tech : integer := 0; abits : integer := 6; dbits : integer := 8;
sepclk : integer := 0; wrfst : integer := 0; ft : integer := 0);
port (
rclk : in std_ulogic;
renable : in std_ulogic;
raddress : in std_logic_vector((abits -1) downto 0);
dataout : out std_logic_vector((dbits -1) downto 0);
wclk : in std_ulogic;
write : in std_ulogic;
waddress : in std_logic_vector((abits -1) downto 0);
datain : in std_logic_vector((dbits -1) downto 0);
error : out std_logic_vector(((dbits + 7) / 8)-1 downto 0);
testin : in std_logic_vector(3 downto 0) := "0000");
end component;
component syncfifo
generic (tech : integer := 0; abits : integer := 6; dbits : integer := 8;
sepclk : integer := 0; wrfst : integer := 0);
port (
rst : in std_ulogic;
rclk : in std_ulogic;
renable : in std_ulogic;
dataout : out std_logic_vector((dbits -1) downto 0);
wclk : in std_ulogic;
write : in std_ulogic;
datain : in std_logic_vector((dbits -1) downto 0);
full : out std_ulogic;
empty : out std_ulogic
);
end component;
---------------------------------------------------------------------------
-- PADS
---------------------------------------------------------------------------
component inpad
generic (tech : integer := 0; level : integer := 0;
voltage : integer := x33v; filter : integer := 0;
strength : integer := 0);
port (pad : in std_ulogic; o : out std_ulogic);
end component;
component inpadv
generic (tech : integer := 0; level : integer := 0;
voltage : integer := x33v; width : integer := 1);
port (
pad : in std_logic_vector(width-1 downto 0);
o : out std_logic_vector(width-1 downto 0));
end component;
component iopad
generic (tech : integer := 0; level : integer := 0; slew : integer := 0;
voltage : integer := x33v; strength : integer := 12;
oepol : integer := 0);
port (pad : inout std_ulogic; i, en : in std_ulogic; o : out std_ulogic);
end component;
component iopadv
generic (tech : integer := 0; level : integer := 0; slew : integer := 0;
voltage : integer := x33v; strength : integer := 12; width : integer := 1;
oepol : integer := 0);
port (
pad : inout std_logic_vector(width-1 downto 0);
i : in std_logic_vector(width-1 downto 0);
en : in std_ulogic;
o : out std_logic_vector(width-1 downto 0));
end component;
component iopadvv is
generic (tech : integer := 0; level : integer := 0; slew : integer := 0;
voltage : integer := x33v; strength : integer := 12; width : integer := 1;
oepol : integer := 0);
port (
pad : inout std_logic_vector(width-1 downto 0);
i : in std_logic_vector(width-1 downto 0);
en : in std_logic_vector(width-1 downto 0);
o : out std_logic_vector(width-1 downto 0));
end component;
component iodpad
generic (tech : integer := 0; level : integer := 0; slew : integer := 0;
voltage : integer := x33v; strength : integer := 12;
oepol : integer := 0);
port (pad : inout std_ulogic; i : in std_ulogic; o : out std_ulogic);
end component;
component iodpadv
generic (tech : integer := 0; level : integer := 0; slew : integer := 0;
voltage : integer := x33v; strength : integer := 12; width : integer := 1;
oepol : integer := 0);
port (
pad : inout std_logic_vector(width-1 downto 0);
i : in std_logic_vector(width-1 downto 0);
o : out std_logic_vector(width-1 downto 0));
end component;
component outpad
generic (tech : integer := 0; level : integer := 0; slew : integer := 0;
voltage : integer := x33v; strength : integer := 12);
port (pad : out std_ulogic; i : in std_ulogic);
end component;
component outpadv
generic (tech : integer := 0; level : integer := 0; slew : integer := 0;
voltage : integer := x33v; strength : integer := 12; width : integer := 1);
port (
pad : out std_logic_vector(width-1 downto 0);
i : in std_logic_vector(width-1 downto 0));
end component;
component odpad
generic (tech : integer := 0; level : integer := 0; slew : integer := 0;
voltage : integer := x33v; strength : integer := 12;
oepol : integer := 0);
port (pad : out std_ulogic; i : in std_ulogic);
end component;
component odpadv
generic (tech : integer := 0; level : integer := 0; slew : integer := 0;
voltage : integer := x33v; strength : integer := 12; width : integer := 1;
oepol : integer := 0);
port (
pad : out std_logic_vector(width-1 downto 0);
i : in std_logic_vector(width-1 downto 0));
end component;
component toutpad
generic (tech : integer := 0; level : integer := 0; slew : integer := 0;
voltage : integer := x33v; strength : integer := 12;
oepol : integer := 0);
port (pad : out std_ulogic; i, en : in std_ulogic);
end component;
component toutpadv
generic (tech : integer := 0; level : integer := 0; slew : integer := 0;
voltage : integer := x33v; strength : integer := 12; width : integer := 1;
oepol : integer := 0);
port (
pad : out std_logic_vector(width-1 downto 0);
i : in std_logic_vector(width-1 downto 0);
en : in std_ulogic);
end component;
component toutpadvv is
generic (tech : integer := 0; level : integer := 0; slew : integer := 0;
voltage : integer := x33v; strength : integer := 12; width : integer := 1;
oepol : integer := 0);
port (
pad : out std_logic_vector(width-1 downto 0);
i : in std_logic_vector(width-1 downto 0);
en : in std_logic_vector(width-1 downto 0));
end component;
component skew_outpad
generic (tech : integer := 0; level : integer := 0; slew : integer := 0;
voltage : integer := x33v; strength : integer := 12; skew : integer := 0);
port (pad : out std_ulogic; i : in std_ulogic; rst : in std_ulogic;
o : out std_ulogic);
end component;
component clkpad
generic (tech : integer := 0; level : integer := 0;
voltage : integer := x33v; arch : integer := 0; hf : integer := 0);
port (pad : in std_ulogic; o : out std_ulogic; rstn : std_ulogic := '1');
end component;
component inpad_ds
generic (tech : integer := 0; level : integer := lvds; voltage : integer := x33v);
port (padp, padn : in std_ulogic; o : out std_ulogic);
end component;
component clkpad_ds
generic (tech : integer := 0; level : integer := lvds; voltage : integer := x33v);
port (padp, padn : in std_ulogic; o : out std_ulogic);
end component;
component inpad_dsv
generic (tech : integer := 0; level : integer := lvds;
voltage : integer := x33v; width : integer := 1);
port (
padp : in std_logic_vector(width-1 downto 0);
padn : in std_logic_vector(width-1 downto 0);
o : out std_logic_vector(width-1 downto 0));
end component;
component iopad_ds
generic (tech : integer := 0; level : integer := 0; slew : integer := 0;
voltage : integer := x33v; strength : integer := 12;
oepol : integer := 0);
port (padp, padn : inout std_ulogic; i, en : in std_ulogic; o : out std_ulogic);
end component;
component outpad_ds
generic (tech : integer := 0; level : integer := lvds;
voltage : integer := x33v; oepol : integer := 0);
port (padp, padn : out std_ulogic; i, en : in std_ulogic);
end component;
component outpad_dsv
generic (tech : integer := 0; level : integer := lvds;
voltage : integer := x33v; width : integer := 1);
port (
padp : out std_logic_vector(width-1 downto 0);
padn : out std_logic_vector(width-1 downto 0);
i, en: in std_logic_vector(width-1 downto 0));
end component;
component lvds_combo is
generic (tech : integer := 0; voltage : integer := 0; width : integer := 1;
oepol : integer := 0);
port (odpadp, odpadn, ospadp, ospadn : out std_logic_vector(0 to width-1);
odval, osval, en : in std_logic_vector(0 to width-1);
idpadp, idpadn, ispadp, ispadn : in std_logic_vector(0 to width-1);
idval, isval : out std_logic_vector(0 to width-1);
lvdsref : in std_logic := '1'
);
end component;
---------------------------------------------------------------------------
-- BUFFERS
---------------------------------------------------------------------------
component techbuf is
generic(
buftype : integer range 0 to 4 := 0;
tech : integer range 0 to NTECH := inferred);
port(
i : in std_ulogic;
o : out std_ulogic
);
end component;
---------------------------------------------------------------------------
-- CLOCK GENERATION
---------------------------------------------------------------------------
type clkgen_in_type is record
pllref : std_logic; -- optional reference for PLL
pllrst : std_logic; -- optional reset for PLL
pllctrl : std_logic_vector(1 downto 0); -- optional control for PLL
clksel : std_logic_vector(1 downto 0); -- optional clock select
end record;
type clkgen_out_type is record
clklock : std_logic;
pcilock : std_logic;
end record;
component clkgen
generic (
tech : integer := DEFFABTECH;
clk_mul : integer := 1;
clk_div : integer := 1;
sdramen : integer := 0;
noclkfb : integer := 1;
pcien : integer := 0;
pcidll : integer := 0;
pcisysclk: integer := 0;
freq : integer := 25000;
clk2xen : integer := 0;
clksel : integer := 0; -- enable clock select
clk_odiv : integer := 0); -- Proasic3 output divider
port (
clkin : in std_logic;
pciclkin: in std_logic;
clk : out std_logic; -- main clock
clkn : out std_logic; -- inverted main clock
clk2x : out std_logic; -- 2x clock
sdclk : out std_logic; -- SDRAM clock
pciclk : out std_logic; -- PCI clock
cgi : in clkgen_in_type;
cgo : out clkgen_out_type;
clk4x : out std_logic; -- 4x clock
clk1xu : out std_logic; -- unscaled 1X clock
clk2xu : out std_logic); -- unscaled 2X clock
end component;
component clkand
generic( tech : integer := 0;
ren : integer range 0 to 1 := 0); -- registered enable
port(
i : in std_ulogic;
en : in std_ulogic;
o : out std_ulogic
);
end component;
component clkmux
generic( tech : integer := 0;
rsel : integer range 0 to 1 := 0); -- registered sel
port(
i0, i1 : in std_ulogic;
sel : in std_ulogic;
o : out std_ulogic;
rst : in std_ulogic := '1'
);
end component;
---------------------------------------------------------------------------
-- TAP controller
---------------------------------------------------------------------------
component tap
generic (
tech : integer := 0;
irlen : integer range 2 to 8 := 4;
idcode : integer range 0 to 255 := 9;
manf : integer range 0 to 2047 := 804;
part : integer range 0 to 65535 := 0;
ver : integer range 0 to 15 := 0;
trsten : integer range 0 to 1 := 1;
scantest : integer := 0);
port (
trst : in std_ulogic;
tck : in std_ulogic;
tms : in std_ulogic;
tdi : in std_ulogic;
tdo : out std_ulogic;
tapo_tck : out std_ulogic;
tapo_tdi : out std_ulogic;
tapo_inst : out std_logic_vector(7 downto 0);
tapo_rst : out std_ulogic;
tapo_capt : out std_ulogic;
tapo_shft : out std_ulogic;
tapo_upd : out std_ulogic;
tapo_xsel1 : out std_ulogic;
tapo_xsel2 : out std_ulogic;
tapi_en1 : in std_ulogic;
tapi_tdo1 : in std_ulogic;
tapi_tdo2 : in std_ulogic;
testen : in std_ulogic := '0';
testrst : in std_ulogic := '1';
tdoen : out std_ulogic
);
end component;
---------------------------------------------------------------------------
-- DDR registers and PHY
---------------------------------------------------------------------------
component ddr_ireg is
generic ( tech : integer);
port ( Q1 : out std_ulogic;
Q2 : out std_ulogic;
C1 : in std_ulogic;
C2 : in std_ulogic;
CE : in std_ulogic;
D : in std_ulogic;
R : in std_ulogic;
S : in std_ulogic);
end component;
component ddr_oreg is generic ( tech : integer);
port
( Q : out std_ulogic;
C1 : in std_ulogic;
C2 : in std_ulogic;
CE : in std_ulogic;
D1 : in std_ulogic;
D2 : in std_ulogic;
R : in std_ulogic;
S : in std_ulogic);
end component;
component ddrphy
generic (tech : integer := virtex2; MHz : integer := 100;
rstdelay : integer := 200; dbits : integer := 16;
clk_mul : integer := 2 ; clk_div : integer := 2;
rskew : integer :=0);
port (
rst : in std_ulogic;
clk : in std_logic; -- input clock
clkout : out std_ulogic; -- system clock
clkread : out std_ulogic; -- read clock
lock : out std_ulogic; -- DCM locked
ddr_clk : out std_logic_vector(2 downto 0);
ddr_clkb : out std_logic_vector(2 downto 0);
ddr_clk_fb_out : out std_logic;
ddr_clk_fb : in std_logic;
ddr_cke : out std_logic_vector(1 downto 0);
ddr_csb : out std_logic_vector(1 downto 0);
ddr_web : out std_ulogic; -- ddr write enable
ddr_rasb : out std_ulogic; -- ddr ras
ddr_casb : out std_ulogic; -- ddr cas
ddr_dm : out std_logic_vector (dbits/8-1 downto 0); -- ddr dm
ddr_dqs : inout std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
ddr_ad : out std_logic_vector (13 downto 0); -- ddr address
ddr_ba : out std_logic_vector (1 downto 0); -- ddr bank address
ddr_dq : inout std_logic_vector (dbits-1 downto 0); -- ddr data
addr : in std_logic_vector (13 downto 0); -- data mask
ba : in std_logic_vector ( 1 downto 0); -- data mask
dqin : out std_logic_vector (dbits*2-1 downto 0); -- ddr input data
dqout : in std_logic_vector (dbits*2-1 downto 0); -- ddr input data
dm : in std_logic_vector (dbits/4-1 downto 0); -- data mask
oen : in std_ulogic;
dqs : in std_ulogic;
dqsoen : in std_ulogic;
rasn : in std_ulogic;
casn : in std_ulogic;
wen : in std_ulogic;
csn : in std_logic_vector(1 downto 0);
cke : in std_logic_vector(1 downto 0));
end component;
component ddr2phy
generic (tech : integer := virtex5; MHz : integer := 100;
rstdelay : integer := 200; dbits : integer := 16;
clk_mul : integer := 2; clk_div : integer := 2;
ddelayb0 : integer := 0; ddelayb1 : integer := 0; ddelayb2 : integer := 0;
ddelayb3 : integer := 0; ddelayb4 : integer := 0; ddelayb5 : integer := 0;
ddelayb6 : integer := 0; ddelayb7 : integer := 0;
numidelctrl : integer := 4; norefclk : integer := 0);
port (
rst : in std_ulogic;
clk : in std_logic; -- input clock
clkref200 : in std_logic; -- input 200MHz clock
clkout : out std_ulogic; -- system clock
lock : out std_ulogic; -- DCM locked
ddr_clk : out std_logic_vector(2 downto 0);
ddr_clkb : out std_logic_vector(2 downto 0);
ddr_cke : out std_logic_vector(1 downto 0);
ddr_csb : out std_logic_vector(1 downto 0);
ddr_web : out std_ulogic; -- ddr write enable
ddr_rasb : out std_ulogic; -- ddr ras
ddr_casb : out std_ulogic; -- ddr cas
ddr_dm : out std_logic_vector (dbits/8-1 downto 0); -- ddr dm
ddr_dqs : inout std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
ddr_dqsn : inout std_logic_vector (dbits/8-1 downto 0); -- ddr dqsn
ddr_ad : out std_logic_vector (13 downto 0); -- ddr address
ddr_ba : out std_logic_vector (1 downto 0); -- ddr bank address
ddr_dq : inout std_logic_vector (dbits-1 downto 0); -- ddr data
ddr_odt : out std_logic_vector(1 downto 0);
addr : in std_logic_vector (13 downto 0); -- data mask
ba : in std_logic_vector ( 1 downto 0); -- data mask
dqin : out std_logic_vector (dbits*2-1 downto 0); -- ddr input data
dqout : in std_logic_vector (dbits*2-1 downto 0); -- ddr input data
dm : in std_logic_vector (dbits/4-1 downto 0); -- data mask
oen : in std_ulogic;
dqs : in std_ulogic;
dqsoen : in std_ulogic;
rasn : in std_ulogic;
casn : in std_ulogic;
wen : in std_ulogic;
csn : in std_logic_vector(1 downto 0);
cke : in std_logic_vector(1 downto 0);
cal_en : in std_logic_vector(dbits/8-1 downto 0);
cal_inc : in std_logic_vector(dbits/8-1 downto 0);
cal_rst : in std_logic;
odt : in std_logic_vector(1 downto 0));
end component;
---------------------------------------------------------------------------
-- 61x61 Multiplier
---------------------------------------------------------------------------
component mul_61x61
generic (multech : integer := 0);
port(A : in std_logic_vector(60 downto 0);
B : in std_logic_vector(60 downto 0);
EN : in std_logic;
CLK : in std_logic;
PRODUCT : out std_logic_vector(121 downto 0));
end component;
---------------------------------------------------------------------------
-- Ring oscillator
---------------------------------------------------------------------------
component ringosc
generic (tech : integer := 0);
port (
roen : in Std_ULogic;
roout : out Std_ULogic);
end component;
end;
| mit | 08ac58f1e8175ec72e97f78225730b43 | 0.56178 | 3.456279 | false | false | false | false |
impedimentToProgress/UCI-BlueChip | AttackFiles/Attacks/privEsc/lib/gaisler/leon3/grfpwx.vhd | 2 | 9,264 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: grfpwx
-- File: grfpwx.vhd
-- Author: Edvin Catovic - Gaisler Research
-- Description: GRFPU/GRFPC wrapper and FP register file
------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
library gaisler;
use gaisler.leon3.all;
library techmap;
use techmap.gencomp.all;
use techmap.netcomp.all;
entity grfpwx is
generic (fabtech : integer := 0;
memtech : integer := 0;
mul : integer range 0 to 2 := 0;
pclow : integer range 0 to 2 := 2;
dsu : integer range 0 to 2 := 0;
disas : integer range 0 to 2 := 0;
netlist : integer := 0;
index : integer := 0);
port (
rst : in std_ulogic; -- Reset
clk : in std_ulogic;
holdn : in std_ulogic; -- pipeline hold
cpi : in fpc_in_type;
cpo : out fpc_out_type
);
end;
architecture rtl of grfpwx is
component grfpw
generic (fabtech : integer := 0;
memtech : integer := 0;
mul : integer range 0 to 2 := 0;
pclow : integer range 0 to 2 := 2;
dsu : integer range 0 to 1 := 0;
disas : integer range 0 to 2 := 0;
index : integer range 0 to 2 := 0
);
port (
rst : in std_ulogic; -- Reset
clk : in std_ulogic;
holdn : in std_ulogic; -- pipeline hold
cpi_flush : in std_ulogic; -- pipeline flush
cpi_exack : in std_ulogic; -- FP exception acknowledge
cpi_a_rs1 : in std_logic_vector(4 downto 0);
cpi_d_pc : in std_logic_vector(31 downto 0);
cpi_d_inst : in std_logic_vector(31 downto 0);
cpi_d_cnt : in std_logic_vector(1 downto 0);
cpi_d_trap : in std_ulogic;
cpi_d_annul : in std_ulogic;
cpi_d_pv : in std_ulogic;
cpi_a_pc : in std_logic_vector(31 downto 0);
cpi_a_inst : in std_logic_vector(31 downto 0);
cpi_a_cnt : in std_logic_vector(1 downto 0);
cpi_a_trap : in std_ulogic;
cpi_a_annul : in std_ulogic;
cpi_a_pv : in std_ulogic;
cpi_e_pc : in std_logic_vector(31 downto 0);
cpi_e_inst : in std_logic_vector(31 downto 0);
cpi_e_cnt : in std_logic_vector(1 downto 0);
cpi_e_trap : in std_ulogic;
cpi_e_annul : in std_ulogic;
cpi_e_pv : in std_ulogic;
cpi_m_pc : in std_logic_vector(31 downto 0);
cpi_m_inst : in std_logic_vector(31 downto 0);
cpi_m_cnt : in std_logic_vector(1 downto 0);
cpi_m_trap : in std_ulogic;
cpi_m_annul : in std_ulogic;
cpi_m_pv : in std_ulogic;
cpi_x_pc : in std_logic_vector(31 downto 0);
cpi_x_inst : in std_logic_vector(31 downto 0);
cpi_x_cnt : in std_logic_vector(1 downto 0);
cpi_x_trap : in std_ulogic;
cpi_x_annul : in std_ulogic;
cpi_x_pv : in std_ulogic;
cpi_lddata : in std_logic_vector(31 downto 0); -- load data
cpi_dbg_enable : in std_ulogic;
cpi_dbg_write : in std_ulogic;
cpi_dbg_fsr : in std_ulogic; -- FSR access
cpi_dbg_addr : in std_logic_vector(4 downto 0);
cpi_dbg_data : in std_logic_vector(31 downto 0);
cpo_data : out std_logic_vector(31 downto 0); -- store data
cpo_exc : out std_logic; -- FP exception
cpo_cc : out std_logic_vector(1 downto 0); -- FP condition codes
cpo_ccv : out std_ulogic; -- FP condition codes valid
cpo_ldlock : out std_logic; -- FP pipeline hold
cpo_holdn : out std_ulogic;
cpo_dbg_data : out std_logic_vector(31 downto 0);
rfi1_rd1addr : out std_logic_vector(3 downto 0);
rfi1_rd2addr : out std_logic_vector(3 downto 0);
rfi1_wraddr : out std_logic_vector(3 downto 0);
rfi1_wrdata : out std_logic_vector(31 downto 0);
rfi1_ren1 : out std_ulogic;
rfi1_ren2 : out std_ulogic;
rfi1_wren : out std_ulogic;
rfi2_rd1addr : out std_logic_vector(3 downto 0);
rfi2_rd2addr : out std_logic_vector(3 downto 0);
rfi2_wraddr : out std_logic_vector(3 downto 0);
rfi2_wrdata : out std_logic_vector(31 downto 0);
rfi2_ren1 : out std_ulogic;
rfi2_ren2 : out std_ulogic;
rfi2_wren : out std_ulogic;
rfo1_data1 : in std_logic_vector(31 downto 0);
rfo1_data2 : in std_logic_vector(31 downto 0);
rfo2_data1 : in std_logic_vector(31 downto 0);
rfo2_data2 : in std_logic_vector(31 downto 0)
);
end component;
signal rfi1, rfi2 : fp_rf_in_type;
signal rfo1, rfo2 : fp_rf_out_type;
begin
x0 : if netlist = 0 generate
grfpw0 : grfpw generic map (fabtech, memtech, mul, pclow, dsu, disas, index)
port map (
rst ,
clk ,
holdn ,
cpi.flush ,
cpi.exack ,
cpi.a_rs1 ,
cpi.d.pc ,
cpi.d.inst ,
cpi.d.cnt ,
cpi.d.trap ,
cpi.d.annul ,
cpi.d.pv ,
cpi.a.pc ,
cpi.a.inst ,
cpi.a.cnt ,
cpi.a.trap ,
cpi.a.annul ,
cpi.a.pv ,
cpi.e.pc ,
cpi.e.inst ,
cpi.e.cnt ,
cpi.e.trap ,
cpi.e.annul ,
cpi.e.pv ,
cpi.m.pc ,
cpi.m.inst ,
cpi.m.cnt ,
cpi.m.trap ,
cpi.m.annul ,
cpi.m.pv ,
cpi.x.pc ,
cpi.x.inst ,
cpi.x.cnt ,
cpi.x.trap ,
cpi.x.annul ,
cpi.x.pv ,
cpi.lddata ,
cpi.dbg.enable ,
cpi.dbg.write ,
cpi.dbg.fsr ,
cpi.dbg.addr ,
cpi.dbg.data ,
cpo.data ,
cpo.exc ,
cpo.cc ,
cpo.ccv ,
cpo.ldlock ,
cpo.holdn ,
cpo.dbg.data ,
rfi1.rd1addr ,
rfi1.rd2addr ,
rfi1.wraddr ,
rfi1.wrdata ,
rfi1.ren1 ,
rfi1.ren2 ,
rfi1.wren ,
rfi2.rd1addr ,
rfi2.rd2addr ,
rfi2.wraddr ,
rfi2.wrdata ,
rfi2.ren1 ,
rfi2.ren2 ,
rfi2.wren ,
rfo1.data1 ,
rfo1.data2 ,
rfo2.data1 ,
rfo2.data2
);
end generate;
x1 : if netlist = 1 generate
grfpw0 : grfpw_net generic map (fabtech, mul, pclow, dsu, disas)
port map (
rst ,
clk ,
holdn ,
cpi.flush ,
cpi.exack ,
cpi.a_rs1 ,
cpi.d.pc ,
cpi.d.inst ,
cpi.d.cnt ,
cpi.d.trap ,
cpi.d.annul ,
cpi.d.pv ,
cpi.a.pc ,
cpi.a.inst ,
cpi.a.cnt ,
cpi.a.trap ,
cpi.a.annul ,
cpi.a.pv ,
cpi.e.pc ,
cpi.e.inst ,
cpi.e.cnt ,
cpi.e.trap ,
cpi.e.annul ,
cpi.e.pv ,
cpi.m.pc ,
cpi.m.inst ,
cpi.m.cnt ,
cpi.m.trap ,
cpi.m.annul ,
cpi.m.pv ,
cpi.x.pc ,
cpi.x.inst ,
cpi.x.cnt ,
cpi.x.trap ,
cpi.x.annul ,
cpi.x.pv ,
cpi.lddata ,
cpi.dbg.enable ,
cpi.dbg.write ,
cpi.dbg.fsr ,
cpi.dbg.addr ,
cpi.dbg.data ,
cpo.data ,
cpo.exc ,
cpo.cc ,
cpo.ccv ,
cpo.ldlock ,
cpo.holdn ,
cpo.dbg.data ,
rfi1.rd1addr ,
rfi1.rd2addr ,
rfi1.wraddr ,
rfi1.wrdata ,
rfi1.ren1 ,
rfi1.ren2 ,
rfi1.wren ,
rfi2.rd1addr ,
rfi2.rd2addr ,
rfi2.wraddr ,
rfi2.wrdata ,
rfi2.ren1 ,
rfi2.ren2 ,
rfi2.wren ,
rfo1.data1 ,
rfo1.data2 ,
rfo2.data1 ,
rfo2.data2
);
end generate;
rf1 : regfile_3p generic map (memtech, 4, 32, 1, 16)
port map (clk, rfi1.wraddr, rfi1.wrdata, rfi1.wren, clk, rfi1.rd1addr, rfi1.ren1, rfo1.data1,
rfi1.rd2addr, rfi1.ren2, rfo1.data2);
rf2 : regfile_3p generic map (memtech, 4, 32, 1, 16)
port map (clk, rfi2.wraddr, rfi2.wrdata, rfi2.wren, clk, rfi2.rd1addr, rfi2.ren1, rfo2.data1,
rfi2.rd2addr, rfi2.ren2, rfo2.data2);
end;
| mit | d6666e1ffd0fe90d08ba605b5739e1b4 | 0.512306 | 3.131846 | false | false | false | false |
impedimentToProgress/UCI-BlueChip | AttackFiles/Attacks/privEsc/lib/tech/unisim/simprims/xilinx_simprims.vhd | 2 | 783,945 | ----------------------------------------------------------------------------
-- Simple simulation models for some Xilinx blocks
----------------------------------------------------------------------------
-- pragma translate_off
library ieee;
use ieee.std_logic_1164.all;
library STD;
use STD.TEXTIO.all;
package vpkg is
signal GSR : std_logic := '0';
signal GTS : std_logic := '0';
PROCEDURE GenericValueCheckMessage (
CONSTANT HeaderMsg : IN STRING := " Attribute Syntax Error ";
CONSTANT GenericName : IN STRING := "";
CONSTANT EntityName : IN STRING := "";
CONSTANT InstanceName : IN STRING := "";
CONSTANT GenericValue : IN STRING := "";
Constant Unit : IN STRING := "";
Constant ExpectedValueMsg : IN STRING := "";
Constant ExpectedGenericValue : IN STRING := "";
CONSTANT TailMsg : IN STRING;
CONSTANT MsgSeverity : IN SEVERITY_LEVEL := WARNING
);
PROCEDURE GenericValueCheckMessage (
CONSTANT HeaderMsg : IN STRING := " Attribute Syntax Error ";
CONSTANT GenericName : IN STRING := "";
CONSTANT EntityName : IN STRING := "";
CONSTANT InstanceName : IN STRING := "";
CONSTANT GenericValue : IN INTEGER;
Constant Unit : IN STRING := "";
Constant ExpectedValueMsg : IN STRING := "";
Constant ExpectedGenericValue : IN INTEGER;
CONSTANT TailMsg : IN STRING;
CONSTANT MsgSeverity : IN SEVERITY_LEVEL := WARNING
);
PROCEDURE GenericValueCheckMessage (
CONSTANT HeaderMsg : IN STRING := " Attribute Syntax Error ";
CONSTANT GenericName : IN STRING := "";
CONSTANT EntityName : IN STRING := "";
CONSTANT InstanceName : IN STRING := "";
CONSTANT GenericValue : IN BOOLEAN;
Constant Unit : IN STRING := "";
Constant ExpectedValueMsg : IN STRING := "";
Constant ExpectedGenericValue : IN STRING := "";
CONSTANT TailMsg : IN STRING;
CONSTANT MsgSeverity : IN SEVERITY_LEVEL := WARNING
);
PROCEDURE GenericValueCheckMessage (
CONSTANT HeaderMsg : IN STRING := " Attribute Syntax Error ";
CONSTANT GenericName : IN STRING := "";
CONSTANT EntityName : IN STRING := "";
CONSTANT InstanceName : IN STRING := "";
CONSTANT GenericValue : IN INTEGER;
CONSTANT Unit : IN STRING := "";
CONSTANT ExpectedValueMsg : IN STRING := "";
CONSTANT ExpectedGenericValue : IN STRING := "";
CONSTANT TailMsg : IN STRING;
CONSTANT MsgSeverity : IN SEVERITY_LEVEL := WARNING
);
PROCEDURE GenericValueCheckMessage (
CONSTANT HeaderMsg : IN STRING := " Attribute Syntax Error ";
CONSTANT GenericName : IN STRING := "";
CONSTANT EntityName : IN STRING := "";
CONSTANT InstanceName : IN STRING := "";
CONSTANT GenericValue : IN REAL;
CONSTANT Unit : IN STRING := "";
CONSTANT ExpectedValueMsg : IN STRING := "";
CONSTANT ExpectedGenericValue : IN STRING := "";
CONSTANT TailMsg : IN STRING;
CONSTANT MsgSeverity : IN SEVERITY_LEVEL := WARNING
);
procedure detect_resolution ( constant model_name : in string);
function slv_to_int (slv : in std_logic_vector) return integer;
function addr_is_valid (slv : in std_logic_vector) return boolean ;
function DECODE_ADDR4 (
ADDRESS : in std_logic_vector(3 downto 0)
) return integer;
function DECODE_ADDR5 (
ADDRESS : in std_logic_vector(4 downto 0)
) return integer;
function SLV_TO_STR (
SLV : in std_logic_vector
) return string;
end;
package body vpkg is
function SLV_TO_STR (
SLV : in std_logic_vector
) return string is
variable j : integer := SLV'length;
variable STR : string (SLV'length downto 1);
begin
for I in SLV'high downto SLV'low loop
case SLV(I) is
when '0' => STR(J) := '0';
when '1' => STR(J) := '1';
when 'X' => STR(J) := 'X';
when 'U' => STR(J) := 'U';
when others => STR(J) := 'X';
end case;
J := J - 1;
end loop;
return STR;
end SLV_TO_STR;
function DECODE_ADDR4 (
ADDRESS : in std_logic_vector(3 downto 0)
) return integer is
variable I : integer;
begin
case ADDRESS is
when "0000" => I := 0;
when "0001" => I := 1;
when "0010" => I := 2;
when "0011" => I := 3;
when "0100" => I := 4;
when "0101" => I := 5;
when "0110" => I := 6;
when "0111" => I := 7;
when "1000" => I := 8;
when "1001" => I := 9;
when "1010" => I := 10;
when "1011" => I := 11;
when "1100" => I := 12;
when "1101" => I := 13;
when "1110" => I := 14;
when "1111" => I := 15;
when others => I := 16;
end case;
return I;
end DECODE_ADDR4;
function ADDR_IS_VALID (
SLV : in std_logic_vector
) return boolean is
variable IS_VALID : boolean := TRUE;
begin
for I in SLV'high downto SLV'low loop
if (SLV(I) /= '0' AND SLV(I) /= '1') then
IS_VALID := FALSE;
end if;
end loop;
return IS_VALID;
end ADDR_IS_VALID;
function SLV_TO_INT(SLV: in std_logic_vector
) return integer is
variable int : integer;
begin
int := 0;
for i in SLV'high downto SLV'low loop
int := int * 2;
if SLV(i) = '1' then
int := int + 1;
end if;
end loop;
return int;
end;
procedure detect_resolution (
constant model_name : in string
) IS
variable test_value : time;
variable Message : LINE;
BEGIN
test_value := 1 ps;
if (test_value = 0 ps) then
Write (Message, STRING'(" Simulator Resolution Error : "));
Write (Message, STRING'(" Simulator resolution is set to a value greater than 1 ps. "));
Write (Message, STRING'(" In order to simulate the "));
Write (Message, model_name);
Write (Message, STRING'(", the simulator resolution must be set to 1ps or smaller "));
ASSERT FALSE REPORT Message.ALL SEVERITY ERROR;
DEALLOCATE (Message);
end if;
END detect_resolution;
PROCEDURE GenericValueCheckMessage (
CONSTANT HeaderMsg : IN STRING := " Attribute Syntax Error ";
CONSTANT GenericName : IN STRING := "";
CONSTANT EntityName : IN STRING := "";
CONSTANT InstanceName : IN STRING := "";
CONSTANT GenericValue : IN STRING := "";
Constant Unit : IN STRING := "";
Constant ExpectedValueMsg : IN STRING := "";
Constant ExpectedGenericValue : IN STRING := "";
CONSTANT TailMsg : IN STRING;
CONSTANT MsgSeverity : IN SEVERITY_LEVEL := WARNING
) IS
VARIABLE Message : LINE;
BEGIN
Write ( Message, HeaderMsg );
Write ( Message, STRING'(" The attribute ") );
Write ( Message, GenericName );
Write ( Message, STRING'(" on ") );
Write ( Message, EntityName );
Write ( Message, STRING'(" instance ") );
Write ( Message, InstanceName );
Write ( Message, STRING'(" is set to ") );
Write ( Message, GenericValue );
Write ( Message, Unit );
Write ( Message, '.' & LF );
Write ( Message, ExpectedValueMsg );
Write ( Message, ExpectedGenericValue );
Write ( Message, Unit );
Write ( Message, TailMsg );
ASSERT FALSE REPORT Message.ALL SEVERITY MsgSeverity;
DEALLOCATE (Message);
END GenericValueCheckMessage;
PROCEDURE GenericValueCheckMessage (
CONSTANT HeaderMsg : IN STRING := " Attribute Syntax Error ";
CONSTANT GenericName : IN STRING := "";
CONSTANT EntityName : IN STRING := "";
CONSTANT InstanceName : IN STRING := "";
CONSTANT GenericValue : IN INTEGER;
CONSTANT Unit : IN STRING := "";
CONSTANT ExpectedValueMsg : IN STRING := "";
CONSTANT ExpectedGenericValue : IN INTEGER;
CONSTANT TailMsg : IN STRING;
CONSTANT MsgSeverity : IN SEVERITY_LEVEL := WARNING
) IS
VARIABLE Message : LINE;
BEGIN
Write ( Message, HeaderMsg );
Write ( Message, STRING'(" The attribute ") );
Write ( Message, GenericName );
Write ( Message, STRING'(" on ") );
Write ( Message, EntityName );
Write ( Message, STRING'(" instance ") );
Write ( Message, InstanceName );
Write ( Message, STRING'(" is set to ") );
Write ( Message, GenericValue );
Write ( Message, Unit );
Write ( Message, '.' & LF );
Write ( Message, ExpectedValueMsg );
Write ( Message, ExpectedGenericValue );
Write ( Message, Unit );
Write ( Message, TailMsg );
ASSERT FALSE REPORT Message.ALL SEVERITY MsgSeverity;
DEALLOCATE (Message);
END GenericValueCheckMessage;
PROCEDURE GenericValueCheckMessage (
CONSTANT HeaderMsg : IN STRING := " Attribute Syntax Error ";
CONSTANT GenericName : IN STRING := "";
CONSTANT EntityName : IN STRING := "";
CONSTANT InstanceName : IN STRING := "";
CONSTANT GenericValue : IN BOOLEAN;
Constant Unit : IN STRING := "";
CONSTANT ExpectedValueMsg : IN STRING := "";
CONSTANT ExpectedGenericValue : IN STRING := "";
CONSTANT TailMsg : IN STRING;
CONSTANT MsgSeverity : IN SEVERITY_LEVEL := WARNING
) IS
VARIABLE Message : LINE;
BEGIN
Write ( Message, HeaderMsg );
Write ( Message, STRING'(" The attribute ") );
Write ( Message, GenericName );
Write ( Message, STRING'(" on ") );
Write ( Message, EntityName );
Write ( Message, STRING'(" instance ") );
Write ( Message, InstanceName );
Write ( Message, STRING'(" is set to ") );
Write ( Message, GenericValue );
Write ( Message, Unit );
Write ( Message, '.' & LF );
Write ( Message, ExpectedValueMsg );
Write ( Message, ExpectedGenericValue );
Write ( Message, Unit );
Write ( Message, TailMsg );
ASSERT FALSE REPORT Message.ALL SEVERITY MsgSeverity;
DEALLOCATE (Message);
END GenericValueCheckMessage;
PROCEDURE GenericValueCheckMessage (
CONSTANT HeaderMsg : IN STRING := " Attribute Syntax Error ";
CONSTANT GenericName : IN STRING := "";
CONSTANT EntityName : IN STRING := "";
CONSTANT InstanceName : IN STRING := "";
CONSTANT GenericValue : IN INTEGER;
CONSTANT Unit : IN STRING := "";
CONSTANT ExpectedValueMsg : IN STRING := "";
CONSTANT ExpectedGenericValue : IN STRING := "";
CONSTANT TailMsg : IN STRING;
CONSTANT MsgSeverity : IN SEVERITY_LEVEL := WARNING
) IS
VARIABLE Message : LINE;
BEGIN
Write ( Message, HeaderMsg );
Write ( Message, STRING'(" The attribute ") );
Write ( Message, GenericName );
Write ( Message, STRING'(" on ") );
Write ( Message, EntityName );
Write ( Message, STRING'(" instance ") );
Write ( Message, InstanceName );
Write ( Message, STRING'(" is set to ") );
Write ( Message, GenericValue );
Write ( Message, Unit );
Write ( Message, '.' & LF );
Write ( Message, ExpectedValueMsg );
Write ( Message, ExpectedGenericValue );
Write ( Message, Unit );
Write ( Message, TailMsg );
ASSERT FALSE REPORT Message.ALL SEVERITY MsgSeverity;
DEALLOCATE (Message);
END GenericValueCheckMessage;
PROCEDURE GenericValueCheckMessage (
CONSTANT HeaderMsg : IN STRING := " Attribute Syntax Error ";
CONSTANT GenericName : IN STRING := "";
CONSTANT EntityName : IN STRING := "";
CONSTANT InstanceName : IN STRING := "";
CONSTANT GenericValue : IN REAL;
CONSTANT Unit : IN STRING := "";
CONSTANT ExpectedValueMsg : IN STRING := "";
CONSTANT ExpectedGenericValue : IN STRING := "";
CONSTANT TailMsg : IN STRING;
CONSTANT MsgSeverity : IN SEVERITY_LEVEL := WARNING
) IS
VARIABLE Message : LINE;
BEGIN
Write ( Message, HeaderMsg );
Write ( Message, STRING'(" The attribute ") );
Write ( Message, GenericName );
Write ( Message, STRING'(" on ") );
Write ( Message, EntityName );
Write ( Message, STRING'(" instance ") );
Write ( Message, InstanceName );
Write ( Message, STRING'(" is set to ") );
Write ( Message, GenericValue );
Write ( Message, Unit );
Write ( Message, '.' & LF );
Write ( Message, ExpectedValueMsg );
Write ( Message, ExpectedGenericValue );
Write ( Message, Unit );
Write ( Message, TailMsg );
ASSERT FALSE REPORT Message.ALL SEVERITY MsgSeverity;
DEALLOCATE (Message);
END GenericValueCheckMessage;
function DECODE_ADDR5 (
ADDRESS : in std_logic_vector(4 downto 0)
) return integer is
variable I : integer;
begin
case ADDRESS is
when "00000" => I := 0;
when "00001" => I := 1;
when "00010" => I := 2;
when "00011" => I := 3;
when "00100" => I := 4;
when "00101" => I := 5;
when "00110" => I := 6;
when "00111" => I := 7;
when "01000" => I := 8;
when "01001" => I := 9;
when "01010" => I := 10;
when "01011" => I := 11;
when "01100" => I := 12;
when "01101" => I := 13;
when "01110" => I := 14;
when "01111" => I := 15;
when "10000" => I := 16;
when "10001" => I := 17;
when "10010" => I := 18;
when "10011" => I := 19;
when "10100" => I := 20;
when "10101" => I := 21;
when "10110" => I := 22;
when "10111" => I := 23;
when "11000" => I := 24;
when "11001" => I := 25;
when "11010" => I := 26;
when "11011" => I := 27;
when "11100" => I := 28;
when "11101" => I := 29;
when "11110" => I := 30;
when "11111" => I := 31;
when others => I := 32;
end case;
return I;
end DECODE_ADDR5;
end;
library ieee;
use ieee.std_logic_1164.all;
package simple_simprim is
component ramb4_generic
generic ( abits : integer := 10; dbits : integer := 8 );
port (DI : in std_logic_vector (dbits-1 downto 0);
EN : in std_ulogic;
WE : in std_ulogic;
RST : in std_ulogic;
CLK : in std_ulogic;
ADDR : in std_logic_vector (abits-1 downto 0);
DO : out std_logic_vector (dbits-1 downto 0)
);
end component;
component ramb4_sx_sx
generic (abits : integer := 10; dbits : integer := 8 );
port (DIA : in std_logic_vector (dbits-1 downto 0);
DIB : in std_logic_vector (dbits-1 downto 0);
ENA : in std_ulogic;
ENB : in std_ulogic;
WEA : in std_ulogic;
WEB : in std_ulogic;
RSTA : in std_ulogic;
RSTB : in std_ulogic;
CLKA : in std_ulogic;
CLKB : in std_ulogic;
ADDRA : in std_logic_vector (abits-1 downto 0);
ADDRB : in std_logic_vector (abits-1 downto 0);
DOA : out std_logic_vector (dbits-1 downto 0);
DOB : out std_logic_vector (dbits-1 downto 0)
);
end component;
component ramb16_sx
generic (abits : integer := 10; dbits : integer := 8 );
port (
DO : out std_logic_vector (dbits-1 downto 0);
ADDR : in std_logic_vector (abits-1 downto 0);
DI : in std_logic_vector (dbits-1 downto 0);
EN : in std_ulogic;
CLK : in std_ulogic;
WE : in std_ulogic;
SSR : in std_ulogic);
end component;
component ram16_sx_sx
generic (abits : integer := 10; dbits : integer := 8 );
port (
DOA : out std_logic_vector (dbits-1 downto 0);
DOB : out std_logic_vector (dbits-1 downto 0);
ADDRA : in std_logic_vector (abits-1 downto 0);
CLKA : in std_ulogic;
DIA : in std_logic_vector (dbits-1 downto 0);
ENA : in std_ulogic;
WEA : in std_ulogic;
ADDRB : in std_logic_vector (abits-1 downto 0);
CLKB : in std_ulogic;
DIB : in std_logic_vector (dbits-1 downto 0);
ENB : in std_ulogic;
WEB : in std_ulogic);
end component;
end;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity ramb4_generic is
generic ( abits : integer := 10; dbits : integer := 8 );
port (DI : in std_logic_vector (dbits-1 downto 0);
EN : in std_ulogic;
WE : in std_ulogic;
RST : in std_ulogic;
CLK : in std_ulogic;
ADDR : in std_logic_vector (abits-1 downto 0);
DO : out std_logic_vector (dbits-1 downto 0)
);
end;
architecture behavioral of ramb4_generic is
type mem is array(0 to (2**abits -1))
of std_logic_vector((dbits -1) downto 0);
begin
main : process(clk)
variable memarr : mem;
begin
if rising_edge(clk)then
if (en = '1') and not (is_x(addr)) then
do <= memarr(to_integer(unsigned(addr)));
end if;
if (we and en) = '1' then
if not is_x(addr) then
memarr(to_integer(unsigned(addr))) := di;
end if;
end if;
end if;
end process;
end;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity ramb16_sx is
generic ( abits : integer := 10; dbits : integer := 8 );
port (
DO : out std_logic_vector (dbits-1 downto 0);
ADDR : in std_logic_vector (abits-1 downto 0);
DI : in std_logic_vector (dbits-1 downto 0);
EN : in std_ulogic;
CLK : in std_ulogic;
WE : in std_ulogic;
SSR : in std_ulogic
);
end;
architecture behav of ramb16_sx is
begin
rp : process(clk)
subtype dword is std_logic_vector(dbits-1 downto 0);
type dregtype is array (0 to 2**abits -1) of DWord;
variable rfd : dregtype := (others => (others => '0'));
begin
if rising_edge(clk) and not is_x (addr) then
if en = '1' then
do <= rfd(to_integer(unsigned(addr)));
if we = '1' then rfd(to_integer(unsigned(addr))) := di; end if;
end if;
end if;
end process;
end;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity ram16_sx_sx is
generic ( abits : integer := 10; dbits : integer := 8 );
port (
DOA : out std_logic_vector (dbits-1 downto 0);
DOB : out std_logic_vector (dbits-1 downto 0);
ADDRA : in std_logic_vector (abits-1 downto 0);
CLKA : in std_ulogic;
DIA : in std_logic_vector (dbits-1 downto 0);
ENA : in std_ulogic;
WEA : in std_ulogic;
ADDRB : in std_logic_vector (abits-1 downto 0);
CLKB : in std_ulogic;
DIB : in std_logic_vector (dbits-1 downto 0);
ENB : in std_ulogic;
WEB : in std_ulogic
);
end;
architecture behav of ram16_sx_sx is
signal async : std_ulogic := '0';
begin
ramproc : process(clka, clkb)
subtype dword is std_logic_vector(dbits-1 downto 0);
type dregtype is array (0 to 2**abits -1) of DWord;
variable rfd : dregtype := (others => (others => '0'));
begin
if rising_edge(clka) and not is_x (addra) then
if ena = '1' then
if wea = '1' then
rfd(to_integer(unsigned(addra))) := dia;
end if;
doa <= rfd(to_integer(unsigned(addra)));
end if;
end if;
if rising_edge(clkb) and not is_x (addrb) then
if enb = '1' then
if web = '1' then
rfd(to_integer(unsigned(addrb))) := dib;
end if;
dob <= rfd(to_integer(unsigned(addrb)));
end if;
end if;
end process;
end;
library ieee;
use ieee.std_logic_1164.all;
entity BSCAN_VIRTEX is
port (CAPTURE : out STD_ULOGIC;
DRCK1 : out STD_ULOGIC;
DRCK2 : out STD_ULOGIC;
RESET : out STD_ULOGIC;
SEL1 : out STD_ULOGIC;
SEL2 : out STD_ULOGIC;
SHIFT : out STD_ULOGIC;
TDI : out STD_ULOGIC;
UPDATE : out STD_ULOGIC;
TDO1 : in STD_ULOGIC;
TDO2 : in STD_ULOGIC);
end;
architecture behav of BSCAN_VIRTEX is
begin
CAPTURE <= '0'; DRCK1 <= '0'; DRCK2 <= '0';
RESET <= '0'; SEL1 <= '0'; SEL2 <= '0';
SHIFT <= '0'; TDI <= '0'; UPDATE <= '0';
end;
library ieee;
use ieee.std_logic_1164.all;
entity BSCAN_VIRTEX2 is
port (CAPTURE : out STD_ULOGIC;
DRCK1 : out STD_ULOGIC;
DRCK2 : out STD_ULOGIC;
RESET : out STD_ULOGIC;
SEL1 : out STD_ULOGIC;
SEL2 : out STD_ULOGIC;
SHIFT : out STD_ULOGIC;
TDI : out STD_ULOGIC;
UPDATE : out STD_ULOGIC;
TDO1 : in STD_ULOGIC;
TDO2 : in STD_ULOGIC);
end;
architecture behav of BSCAN_VIRTEX2 is
begin
CAPTURE <= '0'; DRCK1 <= '0'; DRCK2 <= '0';
RESET <= '0'; SEL1 <= '0'; SEL2 <= '0';
SHIFT <= '0'; TDI <= '0'; UPDATE <= '0';
end;
library ieee;
use ieee.std_logic_1164.all;
entity BSCAN_VIRTEX4 is
generic(
JTAG_CHAIN : integer := 1
);
port(
CAPTURE : out std_ulogic ;
DRCK : out std_ulogic ;
RESET : out std_ulogic ;
SEL : out std_ulogic ;
SHIFT : out std_ulogic ;
TDI : out std_ulogic ;
UPDATE : out std_ulogic ;
TDO : in std_ulogic
);
end BSCAN_VIRTEX4;
architecture behav of BSCAN_VIRTEX4 is
begin
CAPTURE <= '0'; DRCK <= '0';
RESET <= '0'; SEL <= '0';
SHIFT <= '0'; TDI <= '0'; UPDATE <= '0';
end;
library ieee;
use ieee.std_logic_1164.all;
entity BSCAN_VIRTEX5 is
generic(
JTAG_CHAIN : integer := 1
);
port(
CAPTURE : out std_ulogic ;
DRCK : out std_ulogic ;
RESET : out std_ulogic ;
SEL : out std_ulogic ;
SHIFT : out std_ulogic ;
TDI : out std_ulogic ;
UPDATE : out std_ulogic ;
TDO : in std_ulogic
);
end BSCAN_VIRTEX5;
architecture behav of BSCAN_VIRTEX5 is
begin
CAPTURE <= '0'; DRCK <= '0';
RESET <= '0'; SEL <= '0';
SHIFT <= '0'; TDI <= '0'; UPDATE <= '0';
end;
library ieee;
use ieee.std_logic_1164.all;
entity BSCAN_SPARTAN3 is
port (CAPTURE : out STD_ULOGIC;
DRCK1 : out STD_ULOGIC;
DRCK2 : out STD_ULOGIC;
RESET : out STD_ULOGIC;
SEL1 : out STD_ULOGIC;
SEL2 : out STD_ULOGIC;
SHIFT : out STD_ULOGIC;
TDI : out STD_ULOGIC;
UPDATE : out STD_ULOGIC;
TDO1 : in STD_ULOGIC;
TDO2 : in STD_ULOGIC);
end;
architecture behav of BSCAN_SPARTAN3 is
begin
CAPTURE <= '0'; DRCK1 <= '0'; DRCK2 <= '0';
RESET <= '0'; SEL1 <= '0'; SEL2 <= '0';
SHIFT <= '0'; TDI <= '0'; UPDATE <= '0';
end;
library ieee; use ieee.std_logic_1164.all;
entity BUFGMUX is port (O : out std_logic; I0, I1, S : in std_logic); end;
architecture beh of BUFGMUX is
begin o <= to_X01(I0) when to_X01(S) = '0' else I1; end;
library ieee; use ieee.std_logic_1164.all;
entity BUFG is port (O : out std_logic; I : in std_logic); end;
architecture beh of BUFG is begin o <= to_X01(i); end;
library ieee; use ieee.std_logic_1164.all;
entity BUFGP is port (O : out std_logic; I : in std_logic); end;
architecture beh of BUFGP is begin o <= to_X01(i); end;
library ieee; use ieee.std_logic_1164.all;
entity BUFGDLL is port (O : out std_logic; I : in std_logic); end;
architecture beh of BUFGDLL is begin o <= to_X01(i); end;
library ieee; use ieee.std_logic_1164.all;
entity IBUFG is generic (
CAPACITANCE : string := "DONT_CARE"; IOSTANDARD : string := "LVCMOS25");
port (O : out std_logic; I : in std_logic); end;
architecture beh of IBUFG is begin o <= to_X01(i) after 1 ns; end;
library ieee; use ieee.std_logic_1164.all;
entity IBUF is generic (
CAPACITANCE : string := "DONT_CARE"; IOSTANDARD : string := "LVCMOS25");
port (O : out std_logic; I : in std_logic); end;
architecture beh of IBUF is begin o <= to_X01(i) after 1 ns; end;
library ieee;
use ieee.std_logic_1164.all;
entity OBUF is generic (
CAPACITANCE : string := "DONT_CARE"; DRIVE : integer := 12;
IOSTANDARD : string := "LVCMOS25"; SLEW : string := "SLOW");
port (O : out std_ulogic; I : in std_ulogic); end;
architecture beh of OBUF is
begin o <= to_X01(i) after 2 ns when slew = "SLOW" else to_X01(i) after 1 ns; end;
library ieee;
use ieee.std_logic_1164.all;
entity IOBUF is generic (
CAPACITANCE : string := "DONT_CARE"; DRIVE : integer := 12;
IOSTANDARD : string := "LVCMOS25"; SLEW : string := "SLOW");
port ( O : out std_ulogic; IO : inout std_logic; I, T : in std_ulogic);
end;
architecture beh of IOBUF is
begin
io <= 'X' after 2 ns when to_X01(t) = 'X' else
I after 2 ns when (to_X01(t) = '0') else
'Z' after 2 ns when to_X01(t) = '1';
o <= to_X01(io) after 1 ns;
end;
library ieee;
use ieee.std_logic_1164.all;
entity IOBUFDS is generic (
CAPACITANCE : string := "DONT_CARE"; IBUF_DELAY_VALUE : string := "0";
IOSTANDARD : string := "DEFAULT"; IFD_DELAY_VALUE : string := "AUTO");
port ( O : out std_ulogic; IO, IOB : inout std_logic; I, T : in std_ulogic);
end;
architecture beh of IOBUFDS is
begin
io <= 'X' after 2 ns when to_X01(t) = 'X' else
I after 2 ns when (to_X01(t) = '0') else
'Z' after 2 ns when to_X01(t) = '1';
iob <= 'X' after 2 ns when to_X01(t) = 'X' else
not I after 2 ns when (to_X01(t) = '0') else
'Z' after 2 ns when to_X01(t) = '1';
o <= to_X01(io) after 1 ns;
end;
library ieee;
use ieee.std_logic_1164.all;
entity OBUFT is generic (
CAPACITANCE : string := "DONT_CARE"; DRIVE : integer := 12;
IOSTANDARD : string := "LVCMOS25"; SLEW : string := "SLOW");
port ( O : out std_ulogic; I, T : in std_ulogic);
end;
architecture beh of OBUFT is
begin
o <= I after 2 ns when to_X01(t) = '0' else
'Z' after 2 ns when to_X01(t) = '1' else
'X' after 2 ns ;
end;
library ieee; use ieee.std_logic_1164.all;
entity IBUFDS is
generic ( CAPACITANCE : string := "DONT_CARE";
DIFF_TERM : boolean := FALSE; IBUF_DELAY_VALUE : string := "0";
IFD_DELAY_VALUE : string := "AUTO"; IOSTANDARD : string := "DEFAULT");
port (O : out std_logic; I, IB : in std_logic); end;
architecture beh of IBUFDS is
signal old : std_ulogic;
begin
old <= '1' after 1 ns when (to_X01(I) = '1') and (to_X01(IB) = '0') else
'0' after 1 ns when (to_X01(I) = '0') and (to_X01(IB) = '1') else old;
o <= old;
end;
library ieee; use ieee.std_logic_1164.all;
entity IBUFDS_LVDS_25 is
port (O : out std_logic; I, IB : in std_logic); end;
architecture beh of IBUFDS_LVDS_25 is
signal old : std_ulogic;
begin
old <= '1' after 1 ns when (to_X01(I) = '1') and (to_X01(IB) = '0') else
'0' after 1 ns when (to_X01(I) = '0') and (to_X01(IB) = '1') else old;
o <= old;
end;
library ieee; use ieee.std_logic_1164.all;
entity IBUFDS_LVDS_33 is
port (O : out std_logic; I, IB : in std_logic); end;
architecture beh of IBUFDS_LVDS_33 is
signal old : std_ulogic;
begin
old <= '1' after 1 ns when (to_X01(I) = '1') and (to_X01(IB) = '0') else
'0' after 1 ns when (to_X01(I) = '0') and (to_X01(IB) = '1') else old;
o <= old;
end;
library ieee; use ieee.std_logic_1164.all;
entity IBUFGDS_LVDS_25 is
port (O : out std_logic; I, IB : in std_logic); end;
architecture beh of IBUFGDS_LVDS_25 is
signal old : std_ulogic;
begin
old <= '1' after 1 ns when (to_X01(I) = '1') and (to_X01(IB) = '0') else
'0' after 1 ns when (to_X01(I) = '0') and (to_X01(IB) = '1') else old;
o <= old;
end;
library ieee; use ieee.std_logic_1164.all;
entity IBUFGDS_LVDS_33 is
port (O : out std_logic; I, IB : in std_logic); end;
architecture beh of IBUFGDS_LVDS_33 is
signal old : std_ulogic;
begin
old <= '1' after 1 ns when (to_X01(I) = '1') and (to_X01(IB) = '0') else
'0' after 1 ns when (to_X01(I) = '0') and (to_X01(IB) = '1') else old;
o <= old;
end;
library ieee; use ieee.std_logic_1164.all;
entity IBUFGDS is
generic( CAPACITANCE : string := "DONT_CARE";
DIFF_TERM : boolean := FALSE; IBUF_DELAY_VALUE : string := "0";
IOSTANDARD : string := "DEFAULT");
port (O : out std_logic; I, IB : in std_logic); end;
architecture beh of IBUFGDS is
signal old : std_ulogic;
begin
old <= '1' after 1 ns when (to_X01(I) = '1') and (to_X01(IB) = '0') else
'0' after 1 ns when (to_X01(I) = '0') and (to_X01(IB) = '1') else old;
o <= old;
end;
library ieee; use ieee.std_logic_1164.all;
entity OBUFDS is
generic(IOSTANDARD : string := "DEFAULT");
port (O, OB : out std_ulogic; I : in std_ulogic); end;
architecture beh of OBUFDS is
begin
o <= to_X01(i) after 1 ns; ob <= not to_X01(i) after 1 ns;
end;
library ieee; use ieee.std_logic_1164.all;
entity OBUFDS_LVDS_25 is
port (O, OB : out std_ulogic; I : in std_ulogic); end;
architecture beh of OBUFDS_LVDS_25 is
begin
o <= to_X01(i) after 1 ns; ob <= not to_X01(i) after 1 ns;
end;
library ieee; use ieee.std_logic_1164.all;
entity OBUFDS_LVDS_33 is
port (O, OB : out std_ulogic; I : in std_ulogic); end;
architecture beh of OBUFDS_LVDS_33 is
begin
o <= to_X01(i) after 1 ns; ob <= not to_X01(i) after 1 ns;
end;
----- CELL BUFGCE -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
--library UNISIM;
--use UNISIM.VCOMPONENTS.all;
entity BUFGCE is
port(
O : out STD_ULOGIC;
CE: in STD_ULOGIC;
I : in STD_ULOGIC
);
end BUFGCE;
architecture BUFGCE_V of BUFGCE is
signal NCE : STD_ULOGIC := 'X';
signal GND : STD_ULOGIC := '0';
component BUFGMUX port (O : out std_logic; I0, I1, S : in std_logic); end component;
begin
B1 : BUFGMUX
port map (
I0 => I,
I1 => GND,
O =>O,
s =>NCE);
-- I1 : INV
-- port map (
-- I => CE,
-- O => NCE);
nCE <= not CE;
end BUFGCE_V;
----- CELL CLKDLL -----
----- x_clkdll_maximum_period_check -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library STD;
use STD.TEXTIO.all;
entity x_clkdll_maximum_period_check is
generic (
InstancePath : string := "*";
clock_name : string := "";
maximum_period : time);
port(
clock : in std_ulogic
);
end x_clkdll_maximum_period_check;
architecture x_clkdll_maximum_period_check_V of x_clkdll_maximum_period_check is
begin
MAX_PERIOD_CHECKER : process
variable clock_edge_previous : time := 0 ps;
variable clock_edge_current : time := 0 ps;
variable clock_period : time := 0 ps;
variable Message : line;
begin
clock_edge_previous := clock_edge_current;
clock_edge_current := NOW;
if (clock_edge_previous > 0 ps) then
clock_period := clock_edge_current - clock_edge_previous;
end if;
if (clock_period > maximum_period) then
Write ( Message, string'(" Timing Violation Error : Input Clock Period of"));
Write ( Message, clock_period/1000.0 );
Write ( Message, string'(" on the ") );
Write ( Message, clock_name );
Write ( Message, string'(" port ") );
Write ( Message, string'(" of CLKDLL instance ") );
Write ( Message, InstancePath );
Write ( Message, string'(" exceeds allotted value of ") );
Write ( Message, maximum_period/1000.0 );
Write ( Message, string'(" at simulation time ") );
Write ( Message, clock_edge_current/1000.0 );
Write ( Message, '.' & LF );
assert false report Message.all severity warning;
DEALLOCATE (Message);
end if;
wait on clock;
end process MAX_PERIOD_CHECKER;
end x_clkdll_maximum_period_check_V;
----- CLKDLL -----
library IEEE;
use IEEE.std_logic_1164.all;
library STD;
use STD.TEXTIO.all;
library IEEE;
use Ieee.Vital_Primitives.all;
use Ieee.Vital_Timing.all;
library unisim;
use unisim.vpkg.all;
entity CLKDLL is
generic (
TimingChecksOn : boolean := true;
InstancePath : string := "*";
Xon : boolean := true;
MsgOn : boolean := false;
tipd_CLKFB : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_CLKIN : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_RST : VitalDelayType01 := (0.000 ns, 0.000 ns);
tpd_CLKIN_LOCKED : VitalDelayType01 := (0.000 ns, 0.000 ns);
tperiod_CLKIN_POSEDGE : VitalDelayType := 0.000 ns;
tpw_CLKIN_negedge : VitalDelayType := 0.000 ns;
tpw_CLKIN_posedge : VitalDelayType := 0.000 ns;
tpw_RST_posedge : VitalDelayType := 0.000 ns;
CLKDV_DIVIDE : real := 2.0;
DUTY_CYCLE_CORRECTION : boolean := true;
FACTORY_JF : bit_vector := X"C080"; --non-simulatable
MAXPERCLKIN : time := 40000 ps; --simulation parameter
SIM_CLKIN_CYCLE_JITTER : time := 300 ps; --simulation parameter
SIM_CLKIN_PERIOD_JITTER : time := 1000 ps; --simulation parameter
STARTUP_WAIT : boolean := false --non-simulatable
);
port (
CLK0 : out std_ulogic := '0';
CLK180 : out std_ulogic := '0';
CLK270 : out std_ulogic := '0';
CLK2X : out std_ulogic := '0';
CLK90 : out std_ulogic := '0';
CLKDV : out std_ulogic := '0';
LOCKED : out std_ulogic := '0';
CLKFB : in std_ulogic := '0';
CLKIN : in std_ulogic := '0';
RST : in std_ulogic := '0'
);
attribute VITAL_LEVEL0 of CLKDLL : entity is true;
end CLKDLL;
architecture CLKDLL_V of CLKDLL is
component x_clkdll_maximum_period_check
generic (
InstancePath : string := "*";
clock_name : string := "";
maximum_period : time);
port(
clock : in std_ulogic
);
end component;
signal CLKFB_ipd, CLKIN_ipd, RST_ipd : std_ulogic;
signal clk0_out : std_ulogic;
signal clk2x_out, clkdv_out, locked_out : std_ulogic := '0';
signal clkfb_type : integer;
signal divide_type : integer;
signal clk1x_type : integer;
signal lock_period, lock_delay, lock_clkin, lock_clkfb : std_ulogic := '0';
signal lock_out : std_logic_vector(1 downto 0) := "00";
signal lock_fb : std_ulogic := '0';
signal fb_delay_found : std_ulogic := '0';
signal clkin_ps : std_ulogic;
signal clkin_fb, clkin_fb0, clkin_fb1, clkin_fb2 : std_ulogic;
signal clkin_period_real : VitalDelayArrayType(2 downto 0) := (0.000 ns, 0.000 ns, 0.000 ns);
signal period : time := 0 ps;
signal period_orig : time := 0 ps;
signal period_ps : time := 0 ps;
signal clkout_delay : time := 0 ps;
signal fb_delay : time := 0 ps;
signal period_dv_high, period_dv_low : time := 0 ps;
signal cycle_jitter, period_jitter : time := 0 ps;
signal clkin_window, clkfb_window : std_ulogic := '0';
signal clkin_5050 : std_ulogic := '0';
signal rst_reg : std_logic_vector(2 downto 0) := "000";
signal clkin_period_real0_temp : time := 0 ps;
signal ps_lock_temp : std_ulogic := '0';
signal clk0_temp : std_ulogic := '0';
signal clk2x_temp : std_ulogic := '0';
signal no_stop : boolean := false;
begin
INITPROC : process
begin
detect_resolution
(model_name => "CLKDLL"
);
if (CLKDV_DIVIDE = 1.5) then
divide_type <= 3;
elsif (CLKDV_DIVIDE = 2.0) then
divide_type <= 4;
elsif (CLKDV_DIVIDE = 2.5) then
divide_type <= 5;
elsif (CLKDV_DIVIDE = 3.0) then
divide_type <= 6;
elsif (CLKDV_DIVIDE = 4.0) then
divide_type <= 8;
elsif (CLKDV_DIVIDE = 5.0) then
divide_type <= 10;
elsif (CLKDV_DIVIDE = 8.0) then
divide_type <= 16;
elsif (CLKDV_DIVIDE = 16.0) then
divide_type <= 32;
else
GenericValueCheckMessage
(HeaderMsg => "Attribute Syntax Error",
GenericName => "CLKDV_DIVIDE",
EntityName => "CLKDLL",
InstanceName => InstancePath,
GenericValue => CLKDV_DIVIDE,
Unit => "",
ExpectedValueMsg => "Legal Values for this attribute are 1.5, 2.0, 2.5, 3.0, 4.0, 5.0, 8.0 or 16.0",
ExpectedGenericValue => "",
TailMsg => "",
MsgSeverity => error
);
end if;
clkfb_type <= 2;
period_jitter <= SIM_CLKIN_PERIOD_JITTER;
cycle_jitter <= SIM_CLKIN_CYCLE_JITTER;
case DUTY_CYCLE_CORRECTION is
when false => clk1x_type <= 0;
when true => clk1x_type <= 1;
when others =>
GenericValueCheckMessage
(HeaderMsg => "Attribute Syntax Error",
GenericName => "DUTY_CYCLE_CORRECTION",
EntityName => "CLKDLL",
InstanceName => InstancePath,
GenericValue => DUTY_CYCLE_CORRECTION,
Unit => "",
ExpectedValueMsg => "Legal Values for this attribute are TRUE or FALSE",
ExpectedGenericValue => "",
TailMsg => "",
MsgSeverity => error
);
end case;
case STARTUP_WAIT is
when false => null;
when true => null;
when others =>
GenericValueCheckMessage
(HeaderMsg => "Attribute Syntax Error",
GenericName => "STARTUP_WAIT",
EntityName => "CLKDLL",
InstanceName => InstancePath,
GenericValue => STARTUP_WAIT,
Unit => "",
ExpectedValueMsg => "Legal Values for this attribute are TRUE or FALSE",
ExpectedGenericValue => "",
TailMsg => "",
MsgSeverity => error
);
end case;
wait;
end process INITPROC;
--
-- input wire delays
--
WireDelay : block
begin
VitalWireDelay (CLKIN_ipd, CLKIN, tipd_CLKIN);
VitalWireDelay (CLKFB_ipd, CLKFB, tipd_CLKFB);
VitalWireDelay (RST_ipd, RST, tipd_RST);
end block;
i_max_clkin : x_clkdll_maximum_period_check
generic map (
clock_name => "CLKIN",
maximum_period => MAXPERCLKIN)
port map (
clock => clkin_ipd);
assign_clkin_ps : process
begin
if (rst_ipd = '0') then
clkin_ps <= clkin_ipd;
elsif (rst_ipd = '1') then
clkin_ps <= '0';
wait until (falling_edge(rst_reg(2)));
end if;
wait on clkin_ipd, rst_ipd;
end process assign_clkin_ps;
clkin_fb0 <= transport (clkin_ps and lock_fb) after period_ps/4;
clkin_fb1 <= transport clkin_fb0 after period_ps/4;
clkin_fb2 <= transport clkin_fb1 after period_ps/4;
clkin_fb <= transport clkin_fb2 after period_ps/4;
determine_period_ps : process
variable clkin_ps_edge_previous : time := 0 ps;
variable clkin_ps_edge_current : time := 0 ps;
begin
if (rst_ipd'event) then
clkin_ps_edge_previous := 0 ps;
clkin_ps_edge_current := 0 ps;
period_ps <= 0 ps;
else
if (rising_edge(clkin_ps)) then
clkin_ps_edge_previous := clkin_ps_edge_current;
clkin_ps_edge_current := NOW;
wait for 0 ps;
if ((clkin_ps_edge_current - clkin_ps_edge_previous) <= (1.5 * period_ps)) then
period_ps <= clkin_ps_edge_current - clkin_ps_edge_previous;
elsif ((period_ps = 0 ps) and (clkin_ps_edge_previous /= 0 ps)) then
period_ps <= clkin_ps_edge_current - clkin_ps_edge_previous;
end if;
end if;
end if;
wait on clkin_ps, rst_ipd;
end process determine_period_ps;
assign_lock_fb : process
begin
if (rising_edge(clkin_ps)) then
lock_fb <= lock_period;
end if;
wait on clkin_ps;
end process assign_lock_fb;
calculate_clkout_delay : process
begin
if (rst_ipd'event) then
clkout_delay <= 0 ps;
elsif (period'event or fb_delay'event) then
clkout_delay <= period - fb_delay;
end if;
wait on period, fb_delay, rst_ipd;
end process calculate_clkout_delay;
--
--generate master reset signal
--
gen_master_rst : process
begin
if (rising_edge(clkin_ipd)) then
rst_reg(2) <= rst_reg(1) and rst_reg(0) and rst_ipd;
rst_reg(1) <= rst_reg(0) and rst_ipd;
rst_reg(0) <= rst_ipd;
end if;
wait on clkin_ipd;
end process gen_master_rst;
check_rst_width : process
variable Message : line;
begin
if (falling_edge(rst_ipd)) then
if ((rst_reg(2) and rst_reg(1) and rst_reg(0)) = '0') then
Write ( Message, string'(" Timing Violation Error : RST on instance "));
Write ( Message, Instancepath );
Write ( Message, string'(" must be asserted for 3 CLKIN clock cycles. "));
assert false report Message.all severity error;
DEALLOCATE (Message);
end if;
end if;
wait on rst_ipd;
end process check_rst_width;
--
--determine clock period
--
determine_clock_period : process
variable clkin_edge_previous : time := 0 ps;
variable clkin_edge_current : time := 0 ps;
begin
if (rst_ipd'event) then
clkin_period_real(0) <= 0 ps;
clkin_period_real(1) <= 0 ps;
clkin_period_real(2) <= 0 ps;
elsif (rising_edge(clkin_ps)) then
clkin_edge_previous := clkin_edge_current;
clkin_edge_current := NOW;
clkin_period_real(2) <= clkin_period_real(1);
clkin_period_real(1) <= clkin_period_real(0);
if (clkin_edge_previous /= 0 ps) then
clkin_period_real(0) <= clkin_edge_current - clkin_edge_previous;
end if;
end if;
if (no_stop'event) then
clkin_period_real(0) <= clkin_period_real0_temp;
end if;
wait on clkin_ps, no_stop, rst_ipd;
end process determine_clock_period;
evaluate_clock_period : process
variable clock_stopped : std_ulogic := '1';
variable Message : line;
begin
if (rst_ipd'event) then
lock_period <= '0';
clock_stopped := '1';
clkin_period_real0_temp <= 0 ps;
else
if (falling_edge(clkin_ps)) then
if (lock_period = '0') then
if ((clkin_period_real(0) /= 0 ps ) and (clkin_period_real(0) - cycle_jitter <= clkin_period_real(1)) and (clkin_period_real(1) <= clkin_period_real(0) + cycle_jitter) and (clkin_period_real(1) - cycle_jitter <= clkin_period_real(2)) and (clkin_period_real(2) <= clkin_period_real(1) + cycle_jitter)) then
lock_period <= '1';
period_orig <= (clkin_period_real(0) + clkin_period_real(1) + clkin_period_real(2)) / 3;
period <= clkin_period_real(0);
end if;
elsif (lock_period = '1') then
if (100000000 ps < clkin_period_real(0)/1000) then
Write ( Message, string'(" Timing Violation Error : CLKIN stopped toggling on instance "));
Write ( Message, Instancepath );
Write ( Message, string'(" exceeds "));
Write ( Message, string'(" 10000 "));
Write ( Message, string'(" Current CLKIN Period = "));
Write ( Message, string'(" clkin_period(0) / 10000.0 "));
Write ( Message, string'(" ns "));
assert false report Message.all severity warning;
DEALLOCATE (Message);
lock_period <= '0';
wait until (falling_edge(rst_reg(2)));
elsif ((period_orig * 2 < clkin_period_real(0)) and (clock_stopped = '0')) then
clkin_period_real0_temp <= clkin_period_real(1);
no_stop <= not no_stop;
clock_stopped := '1';
elsif ((clkin_period_real(0) < period_orig - period_jitter) or (period_orig + period_jitter < clkin_period_real(0))) then
Write ( Message, string'(" Timing Violation Error : Input Clock Period Jitter on instance "));
Write ( Message, Instancepath );
Write ( Message, string'(" exceeds "));
Write ( Message, period_jitter / 1000.0 );
Write ( Message, string'(" Locked CLKIN Period = "));
Write ( Message, period_orig / 1000.0 );
Write ( Message, string'(" Current CLKIN Period = "));
Write ( Message, clkin_period_real(0) / 1000.0 );
assert false report Message.all severity warning;
DEALLOCATE (Message);
lock_period <= '0';
wait until (falling_edge(rst_reg(2)));
elsif ((clkin_period_real(0) < clkin_period_real(1) - cycle_jitter) or (clkin_period_real(1) + cycle_jitter < clkin_period_real(0))) then
Write ( Message, string'(" Timing Violation Error : Input Clock Cycle Jitter on on instance "));
Write ( Message, Instancepath );
Write ( Message, string'(" exceeds "));
Write ( Message, cycle_jitter / 1000.0 );
Write ( Message, string'(" Previous CLKIN Period = "));
Write ( Message, clkin_period_real(1) / 1000.0 );
Write ( Message, string'(" Current CLKIN Period = "));
Write ( Message, clkin_period_real(0) / 1000.0 );
assert false report Message.all severity warning;
DEALLOCATE (Message);
lock_period <= '0';
wait until (falling_edge(rst_reg(2)));
else
period <= clkin_period_real(0);
clock_stopped := '0';
end if;
end if;
end if;
end if;
wait on clkin_ps, rst_ipd;
end process evaluate_clock_period;
--
--determine clock delay
--
determine_clock_delay : process
variable delay_edge : time := 0 ps;
variable temp1 : integer := 0;
variable temp2 : integer := 0;
variable temp : integer := 0;
variable delay_edge_current : time := 0 ps;
begin
if (rst_ipd'event) then
fb_delay <= 0 ps;
fb_delay_found <= '0';
else
if (rising_edge(lock_period)) then
if ((lock_period = '1') and (clkfb_type /= 0)) then
if (clkfb_type = 1) then
wait until ((rising_edge(clk0_temp)) or (rst_ipd'event));
delay_edge := NOW;
elsif (clkfb_type = 2) then
wait until ((rising_edge(clk2x_temp)) or (rst_ipd'event));
delay_edge := NOW;
end if;
wait until ((rising_edge(clkfb_ipd)) or (rst_ipd'event));
temp1 := ((NOW*1) - (delay_edge*1))/ (1 ps);
temp2 := (period_orig * 1)/ (1 ps);
temp := temp1 mod temp2;
fb_delay <= temp * 1 ps;
end if;
end if;
fb_delay_found <= '1';
end if;
wait on lock_period, rst_ipd;
end process determine_clock_delay;
--
-- determine feedback lock
--
GEN_CLKFB_WINDOW : process
begin
if (rst_ipd'event) then
clkfb_window <= '0';
else
if (rising_edge(CLKFB_ipd)) then
wait for 0 ps;
clkfb_window <= '1';
wait for cycle_jitter;
clkfb_window <= '0';
end if;
end if;
wait on clkfb_ipd, rst_ipd;
end process GEN_CLKFB_WINDOW;
GEN_CLKIN_WINDOW : process
begin
if (rst_ipd'event) then
clkin_window <= '0';
else
if (rising_edge(clkin_fb)) then
wait for 0 ps;
clkin_window <= '1';
wait for cycle_jitter;
clkin_window <= '0';
end if;
end if;
wait on clkin_fb, rst_ipd;
end process GEN_CLKIN_WINDOW;
set_reset_lock_clkin : process
begin
if (rst_ipd'event) then
lock_clkin <= '0';
else
if (rising_edge(clkin_fb)) then
wait for 1 ps;
if ((clkfb_window = '1') and (fb_delay_found = '1')) then
lock_clkin <= '1';
else
lock_clkin <= '0';
end if;
end if;
end if;
wait on clkin_fb, rst_ipd;
end process set_reset_lock_clkin;
set_reset_lock_clkfb : process
begin
if (rst_ipd'event) then
lock_clkfb <= '0';
else
if (rising_edge(clkfb_ipd)) then
wait for 1 ps;
if ((clkin_window = '1') and (fb_delay_found = '1')) then
lock_clkfb <= '1';
else
lock_clkfb <= '0';
end if;
end if;
end if;
wait on clkfb_ipd, rst_ipd;
end process set_reset_lock_clkfb;
assign_lock_delay : process
begin
if (rst_ipd'event) then
lock_delay <= '0';
else
if (falling_edge(clkin_fb)) then
lock_delay <= lock_clkin or lock_clkfb;
end if;
end if;
wait on clkin_fb, rst_ipd;
end process;
--
--generate lock signal
--
generate_lock : process
begin
if (rst_ipd'event) then
lock_out <= "00";
locked_out <= '0';
else
if (rising_edge(clkin_ps)) then
if (clkfb_type = 0) then
lock_out(0) <= lock_period;
else
lock_out(0) <= lock_period and lock_delay and lock_fb;
end if;
lock_out(1) <= lock_out(0);
locked_out <= lock_out(1);
end if;
end if;
wait on clkin_ps, rst_ipd;
end process generate_lock;
--
--generate the clk1x_out
--
gen_clk1x : process
begin
if (rst_ipd'event) then
clkin_5050 <= '0';
else
if (rising_edge(clkin_ps)) then
clkin_5050 <= '1';
wait for (period/2);
clkin_5050 <= '0';
end if;
end if;
wait on clkin_ps, rst_ipd;
end process gen_clk1x;
clk0_out <= clkin_5050 when (clk1x_type = 1) else clkin_ps;
--
--generate the clk2x_out
--
gen_clk2x : process
begin
if (rising_edge(clkin_ps)) then
clk2x_out <= '1';
wait for (period / 4);
clk2x_out <= '0';
if (lock_out(0) = '1') then
wait for (period / 4);
clk2x_out <= '1';
wait for (period / 4);
clk2x_out <= '0';
else
wait for (period / 2);
end if;
end if;
wait on clkin_ps;
end process gen_clk2x;
--
--generate the clkdv_out
--
determine_clkdv_period : process
begin
if (period'event) then
period_dv_high <= (period / 2) * (divide_type / 2);
period_dv_low <= (period / 2) * (divide_type / 2 + divide_type mod 2);
end if;
wait on period;
end process determine_clkdv_period;
gen_clkdv : process
begin
if (rising_edge(clkin_ps)) then
if (lock_out(0) = '1') then
clkdv_out <= '1';
wait for (period_dv_high);
clkdv_out <= '0';
wait for (period_dv_low);
clkdv_out <= '1';
wait for (period_dv_high);
clkdv_out <= '0';
wait for (period_dv_low - period/2);
end if;
end if;
wait on clkin_ps;
end process gen_clkdv;
--
--generate all output signal
--
schedule_outputs : process
variable LOCKED_GlitchData : VitalGlitchDataType;
begin
if (CLK0_out'event) then
CLK0 <= transport CLK0_out after clkout_delay;
clk0_temp <= transport CLK0_out after clkout_delay;
CLK90 <= transport clk0_out after (clkout_delay + period / 4);
CLK180 <= transport clk0_out after (clkout_delay + period / 2);
CLK270 <= transport clk0_out after (clkout_delay + (3 * period) / 4);
end if;
if (clk2x_out'event) then
CLK2X <= transport clk2x_out after clkout_delay;
clk2x_temp <= transport clk2x_out after clkout_delay;
end if;
if (clkdv_out'event) then
CLKDV <= transport clkdv_out after clkout_delay;
end if;
VitalPathDelay01 (
OutSignal => LOCKED,
GlitchData => LOCKED_GlitchData,
OutSignalName => "LOCKED",
OutTemp => locked_out,
Paths => (0 => (locked_out'last_event, tpd_CLKIN_LOCKED, true)),
Mode => OnEvent,
Xon => Xon,
MsgOn => MsgOn,
MsgSeverity => warning
);
wait on clk0_out, clk2x_out, clkdv_out, locked_out;
end process schedule_outputs;
VitalTimingCheck : process
variable Tviol_PSINCDEC_PSCLK_posedge : std_ulogic := '0';
variable Tmkr_PSINCDEC_PSCLK_posedge : VitalTimingDataType := VitalTimingDataInit;
variable Tviol_PSEN_PSCLK_posedge : std_ulogic := '0';
variable Tmkr_PSEN_PSCLK_posedge : VitalTimingDataType := VitalTimingDataInit;
variable Pviol_CLKIN : std_ulogic := '0';
variable PInfo_CLKIN : VitalPeriodDataType := VitalPeriodDataInit;
variable Pviol_PSCLK : std_ulogic := '0';
variable PInfo_PSCLK : VitalPeriodDataType := VitalPeriodDataInit;
variable Pviol_RST : std_ulogic := '0';
variable PInfo_RST : VitalPeriodDataType := VitalPeriodDataInit;
begin
if (TimingChecksOn) then
VitalPeriodPulseCheck (
Violation => Pviol_CLKIN,
PeriodData => PInfo_CLKIN,
TestSignal => CLKIN_ipd,
TestSignalName => "CLKIN",
TestDelay => 0 ns,
Period => tperiod_CLKIN_POSEDGE,
PulseWidthHigh => tpw_CLKIN_posedge,
PulseWidthLow => tpw_CLKIN_negedge,
CheckEnabled => TO_X01(not RST_ipd) /= '0',
HeaderMsg => InstancePath &"/CLKDLL",
Xon => Xon,
MsgOn => MsgOn,
MsgSeverity => warning);
VitalPeriodPulseCheck (
Violation => Pviol_RST,
PeriodData => PInfo_RST,
TestSignal => RST_ipd,
TestSignalName => "RST",
TestDelay => 0 ns,
Period => 0 ns,
PulseWidthHigh => tpw_RST_posedge,
PulseWidthLow => 0 ns,
CheckEnabled => true,
HeaderMsg => InstancePath &"/CLKDLL",
Xon => Xon,
MsgOn => MsgOn,
MsgSeverity => warning);
end if;
wait on CLKIN_ipd, RST_ipd;
end process VITALTimingCheck;
end CLKDLL_V;
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library STD;
use STD.TEXTIO.all;
entity clkdllhf_maximum_period_check is
generic (
InstancePath : string := "*";
clock_name : string := "";
maximum_period : time);
port(
clock : in std_ulogic;
rst : in std_ulogic
);
end clkdllhf_maximum_period_check;
architecture clkdllhf_maximum_period_check_V of clkdllhf_maximum_period_check is
begin
MAX_PERIOD_CHECKER : process
variable clock_edge_previous : time := 0 ps;
variable clock_edge_current : time := 0 ps;
variable clock_period : time := 0 ps;
variable Message : line;
begin
if (rising_edge(clock)) then
clock_edge_previous := clock_edge_current;
clock_edge_current := NOW;
if (clock_edge_previous > 0 ps) then
clock_period := clock_edge_current - clock_edge_previous;
end if;
if ((clock_period > maximum_period) and (rst = '0')) then
Write ( Message, string'(" Timing Violation Error : Input Clock Period of"));
Write ( Message, clock_period/1000.0 );
Write ( Message, string'(" on the ") );
Write ( Message, clock_name );
Write ( Message, string'(" port ") );
Write ( Message, string'(" of CLKDLLHF instance ") );
Write ( Message, InstancePath );
Write ( Message, string'(" exceeds allotted value of ") );
Write ( Message, maximum_period/1000.0 );
Write ( Message, string'(" at simulation time ") );
Write ( Message, clock_edge_current/1000.0 );
Write ( Message, '.' & LF );
assert false report Message.all severity warning;
DEALLOCATE (Message);
end if;
end if;
wait on clock;
end process MAX_PERIOD_CHECKER;
end clkdllhf_maximum_period_check_V;
----- CELL CLKDLLHF -----
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
library STD;
use STD.TEXTIO.all;
library unisim;
use unisim.VPKG.all;
library unisim;
use unisim.VCOMPONENTS.all;
entity CLKDLLHF is
generic (
TimingChecksOn : boolean := true;
InstancePath : string := "*";
Xon : boolean := true;
MsgOn : boolean := false;
tipd_CLKFB : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_CLKIN : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_RST : VitalDelayType01 := (0.000 ns, 0.000 ns);
tpd_CLKIN_LOCKED : VitalDelayType01 := (0.000 ns, 0.000 ns);
tperiod_CLKIN_POSEDGE : VitalDelayType := 0.000 ns;
tpw_CLKIN_negedge : VitalDelayType := 0.000 ns;
tpw_CLKIN_posedge : VitalDelayType := 0.000 ns;
tpw_RST_posedge : VitalDelayType := 0.000 ns;
CLKDV_DIVIDE : real := 2.0;
DUTY_CYCLE_CORRECTION : boolean := true;
FACTORY_JF : bit_vector := X"FFF0"; --non-simulatable
STARTUP_WAIT : boolean := false --non-simulatable
);
port (
CLK0 : out std_ulogic := '0';
CLK180 : out std_ulogic := '0';
CLKDV : out std_ulogic := '0';
LOCKED : out std_ulogic := '0';
CLKFB : in std_ulogic := '0';
CLKIN : in std_ulogic := '0';
RST : in std_ulogic := '0'
);
attribute VITAL_LEVEL0 of CLKDLLHF : entity is true;
end CLKDLLHF;
architecture CLKDLLHF_V of CLKDLLHF is
component clkdllhf_maximum_period_check
generic (
InstancePath : string := "*";
clock_name : string := "";
maximum_period : time);
port(
clock : in std_ulogic;
rst : in std_ulogic
);
end component;
constant MAXPERCLKIN : time := 40000 ps;
constant SIM_CLKIN_CYCLE_JITTER : time := 300 ps;
constant SIM_CLKIN_PERIOD_JITTER : time := 1000 ps;
signal CLKFB_ipd, CLKIN_ipd, RST_ipd : std_ulogic;
signal clk0_out : std_ulogic;
signal clkdv_out, locked_out : std_ulogic := '0';
signal clkfb_type : integer;
signal divide_type : integer;
signal clk1x_type : integer;
signal lock_period, lock_delay, lock_clkin, lock_clkfb : std_ulogic := '0';
signal lock_out : std_logic_vector(1 downto 0) := "00";
signal lock_fb : std_ulogic := '0';
signal fb_delay_found : std_ulogic := '0';
signal clkin_ps : std_ulogic;
signal clkin_fb, clkin_fb0, clkin_fb1, clkin_fb2 : std_ulogic;
signal clkin_period_real : VitalDelayArrayType(2 downto 0) := (0.000 ns, 0.000 ns, 0.000 ns);
signal period : time := 0 ps;
signal period_orig : time := 0 ps;
signal period_ps : time := 0 ps;
signal clkout_delay : time := 0 ps;
signal fb_delay : time := 0 ps;
signal period_dv_high, period_dv_low : time := 0 ps;
signal cycle_jitter, period_jitter : time := 0 ps;
signal clkin_window, clkfb_window : std_ulogic := '0';
signal clkin_5050 : std_ulogic := '0';
signal rst_reg : std_logic_vector(2 downto 0) := "000";
signal clkin_period_real0_temp : time := 0 ps;
signal ps_lock_temp : std_ulogic := '0';
signal clk0_temp : std_ulogic := '0';
signal clk2X_temp : std_ulogic := '0';
signal no_stop : boolean := false;
begin
INITPROC : process
begin
detect_resolution
(model_name => "CLKDLLHF"
);
if (CLKDV_DIVIDE = 1.5) then
divide_type <= 3;
elsif (CLKDV_DIVIDE = 2.0) then
divide_type <= 4;
elsif (CLKDV_DIVIDE = 2.5) then
divide_type <= 5;
elsif (CLKDV_DIVIDE = 3.0) then
divide_type <= 6;
elsif (CLKDV_DIVIDE = 4.0) then
divide_type <= 8;
elsif (CLKDV_DIVIDE = 5.0) then
divide_type <= 10;
elsif (CLKDV_DIVIDE = 8.0) then
divide_type <= 16;
elsif (CLKDV_DIVIDE = 16.0) then
divide_type <= 32;
else
GenericValueCheckMessage
(HeaderMsg => "Attribute Syntax Error",
GenericName => "CLKDV_DIVIDE",
EntityName => "CLKDLLHF",
InstanceName => InstancePath,
GenericValue => CLKDV_DIVIDE,
Unit => "",
ExpectedValueMsg => "Legal Values for this attribute are 1.5, 2.0, 2.5, 3.0, 4.0, 5.0, 8.0 or 16.0",
ExpectedGenericValue => "",
TailMsg => "",
MsgSeverity => error
);
end if;
clkfb_type <= 1;
period_jitter <= SIM_CLKIN_PERIOD_JITTER;
cycle_jitter <= SIM_CLKIN_CYCLE_JITTER;
case DUTY_CYCLE_CORRECTION is
when false => clk1x_type <= 0;
when true => clk1x_type <= 1;
when others =>
GenericValueCheckMessage
(HeaderMsg => "Attribute Syntax Error",
GenericName => "DUTY_CYCLE_CORRECTION",
EntityName => "CLKDLLHF",
InstanceName => InstancePath,
GenericValue => DUTY_CYCLE_CORRECTION,
Unit => "",
ExpectedValueMsg => "Legal Values for this attribute are TRUE or FALSE",
ExpectedGenericValue => "",
TailMsg => "",
MsgSeverity => error
);
end case;
case STARTUP_WAIT is
when false => null;
when true => null;
when others =>
GenericValueCheckMessage
(HeaderMsg => "Attribute Syntax Error",
GenericName => "STARTUP_WAIT",
EntityName => "CLKDLLHF",
InstanceName => InstancePath,
GenericValue => STARTUP_WAIT,
Unit => "",
ExpectedValueMsg => "Legal Values for this attribute are TRUE or FALSE",
ExpectedGenericValue => "",
TailMsg => "",
MsgSeverity => error
);
end case;
wait;
end process INITPROC;
--
-- input wire delays
--
WireDelay : block
begin
VitalWireDelay (CLKIN_ipd, CLKIN, tipd_CLKIN);
VitalWireDelay (CLKFB_ipd, CLKFB, tipd_CLKFB);
VitalWireDelay (RST_ipd, RST, tipd_RST);
end block;
i_max_clkin : clkdllhf_maximum_period_check
generic map (
clock_name => "CLKIN",
maximum_period => MAXPERCLKIN)
port map (
clock => clkin_ipd,
rst => rst_ipd);
assign_clkin_ps : process
begin
if (rst_ipd = '0') then
clkin_ps <= clkin_ipd;
elsif (rst_ipd = '1') then
clkin_ps <= '0';
wait until (falling_edge(rst_reg(2)));
end if;
wait on clkin_ipd, rst_ipd;
end process assign_clkin_ps;
clkin_fb0 <= transport (clkin_ps and lock_fb) after period_ps/4;
clkin_fb1 <= transport clkin_fb0 after period_ps/4;
clkin_fb2 <= transport clkin_fb1 after period_ps/4;
clkin_fb <= transport clkin_fb2 after period_ps/4;
determine_period_ps : process
variable clkin_ps_edge_previous : time := 0 ps;
variable clkin_ps_edge_current : time := 0 ps;
begin
if (rst_ipd'event) then
clkin_ps_edge_previous := 0 ps;
clkin_ps_edge_current := 0 ps;
period_ps <= 0 ps;
else
if (rising_edge(clkin_ps)) then
clkin_ps_edge_previous := clkin_ps_edge_current;
clkin_ps_edge_current := NOW;
wait for 0 ps;
if ((clkin_ps_edge_current - clkin_ps_edge_previous) <= (1.5 * period_ps)) then
period_ps <= clkin_ps_edge_current - clkin_ps_edge_previous;
elsif ((period_ps = 0 ps) and (clkin_ps_edge_previous /= 0 ps)) then
period_ps <= clkin_ps_edge_current - clkin_ps_edge_previous;
end if;
end if;
end if;
wait on clkin_ps, rst_ipd;
end process determine_period_ps;
assign_lock_fb : process
begin
if (rising_edge(clkin_ps)) then
lock_fb <= lock_period;
end if;
wait on clkin_ps;
end process assign_lock_fb;
calculate_clkout_delay : process
begin
if (rst_ipd'event) then
clkout_delay <= 0 ps;
elsif (period'event or fb_delay'event) then
clkout_delay <= period - fb_delay;
end if;
wait on period, fb_delay, rst_ipd;
end process calculate_clkout_delay;
--
--generate master reset signal
--
gen_master_rst : process
begin
if (rising_edge(clkin_ipd)) then
rst_reg(2) <= rst_reg(1) and rst_reg(0) and rst_ipd;
rst_reg(1) <= rst_reg(0) and rst_ipd;
rst_reg(0) <= rst_ipd;
end if;
wait on clkin_ipd;
end process gen_master_rst;
check_rst_width : process
variable Message : line;
variable rst_tmp1, rst_tmp2 : time := 0 ps;
begin
if ((rising_edge(rst_ipd)) or (falling_edge(rst_ipd))) then
if (rst_ipd = '1') then
rst_tmp1 := NOW;
elsif (rst_ipd = '1') then
rst_tmp2 := NOW - rst_tmp1;
end if;
if ((rst_tmp2 < 2000 ps) and (rst_tmp2 /= 0 ps)) then
Write ( Message, string'(" Timing Violation Error : RST on instance "));
Write ( Message, Instancepath );
Write ( Message, string'(" must be asserted atleast for 2 ns. "));
assert false report Message.all severity error;
DEALLOCATE (Message);
end if;
end if;
wait on rst_ipd;
end process check_rst_width;
--
--determine clock period
--
determine_clock_period : process
variable clkin_edge_previous : time := 0 ps;
variable clkin_edge_current : time := 0 ps;
begin
if (rst_ipd'event) then
clkin_period_real(0) <= 0 ps;
clkin_period_real(1) <= 0 ps;
clkin_period_real(2) <= 0 ps;
elsif (rising_edge(clkin_ps)) then
clkin_edge_previous := clkin_edge_current;
clkin_edge_current := NOW;
clkin_period_real(2) <= clkin_period_real(1);
clkin_period_real(1) <= clkin_period_real(0);
if (clkin_edge_previous /= 0 ps) then
clkin_period_real(0) <= clkin_edge_current - clkin_edge_previous;
end if;
end if;
if (no_stop'event) then
clkin_period_real(0) <= clkin_period_real0_temp;
end if;
wait on clkin_ps, no_stop, rst_ipd;
end process determine_clock_period;
evaluate_clock_period : process
variable clock_stopped : std_ulogic := '1';
variable Message : line;
begin
if (rst_ipd'event) then
lock_period <= '0';
clock_stopped := '1';
clkin_period_real0_temp <= 0 ps;
else
if (falling_edge(clkin_ps)) then
if (lock_period = '0') then
if ((clkin_period_real(0) /= 0 ps ) and (clkin_period_real(0) - cycle_jitter <= clkin_period_real(1)) and (clkin_period_real(1) <= clkin_period_real(0) + cycle_jitter) and (clkin_period_real(1) - cycle_jitter <= clkin_period_real(2)) and (clkin_period_real(2) <= clkin_period_real(1) + cycle_jitter)) then
lock_period <= '1';
period_orig <= (clkin_period_real(0) + clkin_period_real(1) + clkin_period_real(2)) / 3;
period <= clkin_period_real(0);
end if;
elsif (lock_period = '1') then
if (100000000 ps < clkin_period_real(0)/1000) then
Write ( Message, string'(" Timing Violation Error : CLKIN stopped toggling on instance "));
Write ( Message, Instancepath );
Write ( Message, string'(" exceeds "));
Write ( Message, string'(" 10000 "));
Write ( Message, string'(" Current CLKIN Period = "));
Write ( Message, string'(" clkin_period(0) / 10000.0 "));
Write ( Message, string'(" ns "));
assert false report Message.all severity warning;
DEALLOCATE (Message);
lock_period <= '0';
wait until (falling_edge(rst_reg(2)));
elsif ((period_orig * 2 < clkin_period_real(0)) and (clock_stopped = '0')) then
clkin_period_real0_temp <= clkin_period_real(1);
no_stop <= not no_stop;
clock_stopped := '1';
elsif ((clkin_period_real(0) < period_orig - period_jitter) or (period_orig + period_jitter < clkin_period_real(0))) then
Write ( Message, string'(" Timing Violation Error : Input Clock Period Jitter on instance "));
Write ( Message, Instancepath );
Write ( Message, string'(" exceeds "));
Write ( Message, period_jitter / 1000.0 );
Write ( Message, string'(" Locked CLKIN Period = "));
Write ( Message, period_orig / 1000.0 );
Write ( Message, string'(" Current CLKIN Period = "));
Write ( Message, clkin_period_real(0) / 1000.0 );
assert false report Message.all severity warning;
DEALLOCATE (Message);
lock_period <= '0';
wait until (falling_edge(rst_reg(2)));
elsif ((clkin_period_real(0) < clkin_period_real(1) - cycle_jitter) or (clkin_period_real(1) + cycle_jitter < clkin_period_real(0))) then
Write ( Message, string'(" Timing Violation Error : Input Clock Cycle Jitter on on instance "));
Write ( Message, Instancepath );
Write ( Message, string'(" exceeds "));
Write ( Message, cycle_jitter / 1000.0 );
Write ( Message, string'(" Previous CLKIN Period = "));
Write ( Message, clkin_period_real(1) / 1000.0 );
Write ( Message, string'(" Current CLKIN Period = "));
Write ( Message, clkin_period_real(0) / 1000.0 );
assert false report Message.all severity warning;
DEALLOCATE (Message);
lock_period <= '0';
wait until (falling_edge(rst_reg(2)));
end if;
else
period <= clkin_period_real(0);
clock_stopped := '0';
end if;
end if;
end if;
wait on clkin_ps, rst_ipd;
end process evaluate_clock_period;
determine_clock_delay : process
variable delay_edge : time := 0 ps;
variable temp1 : integer := 0;
variable temp2 : integer := 0;
variable temp : integer := 0;
variable delay_edge_current : time := 0 ps;
begin
if (rst_ipd'event) then
fb_delay <= 0 ps;
fb_delay_found <= '0';
else
if (rising_edge(lock_period)) then
if ((lock_period = '1') and (clkfb_type /= 0)) then
if (clkfb_type = 1) then
wait until ((rising_edge(clk0_temp)) or (rst_ipd'event));
delay_edge := NOW;
elsif (clkfb_type = 2) then
wait until ((rising_edge(clk2x_temp)) or (rst_ipd'event));
delay_edge := NOW;
end if;
wait until ((rising_edge(clkfb_ipd)) or (rst_ipd'event));
temp1 := ((NOW*1) - (delay_edge*1))/ (1 ps);
temp2 := (period_orig * 1)/ (1 ps);
temp := temp1 mod temp2;
fb_delay <= temp * 1 ps;
end if;
end if;
fb_delay_found <= '1';
end if;
wait on lock_period, rst_ipd;
end process determine_clock_delay;
--
-- determine feedback lock
--
GEN_CLKFB_WINDOW : process
begin
if (rst_ipd'event) then
clkfb_window <= '0';
else
if (rising_edge(CLKFB_ipd)) then
wait for 0 ps;
clkfb_window <= '1';
wait for cycle_jitter;
clkfb_window <= '0';
end if;
end if;
wait on clkfb_ipd, rst_ipd;
end process GEN_CLKFB_WINDOW;
GEN_CLKIN_WINDOW : process
begin
if (rst_ipd'event) then
clkin_window <= '0';
else
if (rising_edge(clkin_fb)) then
wait for 0 ps;
clkin_window <= '1';
wait for cycle_jitter;
clkin_window <= '0';
end if;
end if;
wait on clkin_fb, rst_ipd;
end process GEN_CLKIN_WINDOW;
set_reset_lock_clkin : process
begin
if (rst_ipd'event) then
lock_clkin <= '0';
else
if (rising_edge(clkin_fb)) then
wait for 1 ps;
if ((clkfb_window = '1') and (fb_delay_found = '1')) then
lock_clkin <= '1';
else
lock_clkin <= '0';
end if;
end if;
end if;
wait on clkin_fb, rst_ipd;
end process set_reset_lock_clkin;
set_reset_lock_clkfb : process
begin
if (rst_ipd'event) then
lock_clkfb <= '0';
else
if (rising_edge(clkfb_ipd)) then
wait for 1 ps;
if ((clkin_window = '1') and (fb_delay_found = '1')) then
lock_clkfb <= '1';
else
lock_clkfb <= '0';
end if;
end if;
end if;
wait on clkfb_ipd, rst_ipd;
end process set_reset_lock_clkfb;
assign_lock_delay : process
begin
if (rst_ipd'event) then
lock_delay <= '0';
else
if (falling_edge(clkin_fb)) then
lock_delay <= lock_clkin or lock_clkfb;
end if;
end if;
wait on clkin_fb, rst_ipd;
end process;
--
--generate lock signal
--
generate_lock : process
begin
if (rst_ipd'event) then
lock_out <= "00";
locked_out <= '0';
else
if (rising_edge(clkin_ps)) then
if (clkfb_type = 0) then
lock_out(0) <= lock_period;
else
lock_out(0) <= lock_period and lock_delay and lock_fb;
end if;
lock_out(1) <= lock_out(0);
locked_out <= lock_out(1);
end if;
end if;
wait on clkin_ps, rst_ipd;
end process generate_lock;
--
--generate the clk1x_out
--
gen_clk1x : process
begin
if (rst_ipd'event) then
clkin_5050 <= '0';
else
if (rising_edge(clkin_ps)) then
clkin_5050 <= '1';
wait for (period/2);
clkin_5050 <= '0';
end if;
end if;
wait on clkin_ps, rst_ipd;
end process gen_clk1x;
clk0_out <= clkin_5050 when (clk1x_type = 1) else clkin_ps;
--
--generate the clkdv_out
--
determine_clkdv_period : process
begin
if (period'event) then
period_dv_high <= (period / 2) * (divide_type / 2);
period_dv_low <= (period / 2) * (divide_type / 2 + divide_type mod 2);
end if;
wait on period;
end process determine_clkdv_period;
gen_clkdv : process
begin
if (rising_edge(clkin_ps)) then
if (lock_out(0) = '1') then
clkdv_out <= '1';
wait for (period_dv_high);
clkdv_out <= '0';
wait for (period_dv_low);
clkdv_out <= '1';
wait for (period_dv_high);
clkdv_out <= '0';
wait for (period_dv_low - period/2);
end if;
end if;
wait on clkin_ps;
end process gen_clkdv;
--
--generate all output signal
--
schedule_outputs : process
variable LOCKED_GlitchData : VitalGlitchDataType;
begin
if (CLK0_out'event) then
CLK0 <= transport CLK0_out after clkout_delay;
clk0_temp <= transport CLK0_out after clkout_delay;
CLK180 <= transport clk0_out after (clkout_delay + period / 2);
end if;
if (clkdv_out'event) then
CLKDV <= transport clkdv_out after clkout_delay;
end if;
VitalPathDelay01 (
OutSignal => LOCKED,
GlitchData => LOCKED_GlitchData,
OutSignalName => "LOCKED",
OutTemp => locked_out,
Paths => (0 => (locked_out'last_event, tpd_CLKIN_LOCKED, true)),
Mode => OnEvent,
Xon => Xon,
MsgOn => MsgOn,
MsgSeverity => warning
);
wait on clk0_out, clkdv_out, locked_out;
end process schedule_outputs;
VitalTimingCheck : process
variable Tviol_PSINCDEC_PSCLK_posedge : std_ulogic := '0';
variable Tmkr_PSINCDEC_PSCLK_posedge : VitalTimingDataType := VitalTimingDataInit;
variable Tviol_PSEN_PSCLK_posedge : std_ulogic := '0';
variable Tmkr_PSEN_PSCLK_posedge : VitalTimingDataType := VitalTimingDataInit;
variable Pviol_CLKIN : std_ulogic := '0';
variable PInfo_CLKIN : VitalPeriodDataType := VitalPeriodDataInit;
variable Pviol_PSCLK : std_ulogic := '0';
variable PInfo_PSCLK : VitalPeriodDataType := VitalPeriodDataInit;
variable Pviol_RST : std_ulogic := '0';
variable PInfo_RST : VitalPeriodDataType := VitalPeriodDataInit;
begin
if (TimingChecksOn) then
VitalPeriodPulseCheck (
Violation => Pviol_CLKIN,
PeriodData => PInfo_CLKIN,
TestSignal => CLKIN_ipd,
TestSignalName => "CLKIN",
TestDelay => 0 ns,
Period => tperiod_CLKIN_POSEDGE,
PulseWidthHigh => tpw_CLKIN_posedge,
PulseWidthLow => tpw_CLKIN_negedge,
CheckEnabled => TO_X01(not RST_ipd) /= '0',
HeaderMsg => InstancePath &"/CLKDLLHF",
Xon => Xon,
MsgOn => MsgOn,
MsgSeverity => warning);
VitalPeriodPulseCheck (
Violation => Pviol_RST,
PeriodData => PInfo_RST,
TestSignal => RST_ipd,
TestSignalName => "RST",
TestDelay => 0 ns,
Period => 0 ns,
PulseWidthHigh => tpw_RST_posedge,
PulseWidthLow => 0 ns,
CheckEnabled => true,
HeaderMsg => InstancePath &"/CLKDLLHF",
Xon => Xon,
MsgOn => MsgOn,
MsgSeverity => warning);
end if;
wait on CLKIN_ipd, RST_ipd;
end process VITALTimingCheck;
end CLKDLLHF_V;
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library unisim;
use unisim.vpkg.all;
entity IDDR is
generic(
DDR_CLK_EDGE : string := "OPPOSITE_EDGE";
INIT_Q1 : bit := '0';
INIT_Q2 : bit := '0';
SRTYPE : string := "SYNC"
);
port(
Q1 : out std_ulogic;
Q2 : out std_ulogic;
C : in std_ulogic;
CE : in std_ulogic;
D : in std_ulogic;
R : in std_ulogic;
S : in std_ulogic
);
end IDDR;
architecture IDDR_V OF IDDR is
constant SYNC_PATH_DELAY : time := 100 ps;
signal C_ipd : std_ulogic := 'X';
signal CE_ipd : std_ulogic := 'X';
signal D_ipd : std_ulogic := 'X';
signal GSR : std_ulogic := '0';
signal GSR_ipd : std_ulogic := 'X';
signal R_ipd : std_ulogic := 'X';
signal S_ipd : std_ulogic := 'X';
signal C_dly : std_ulogic := 'X';
signal CE_dly : std_ulogic := 'X';
signal D_dly : std_ulogic := 'X';
signal GSR_dly : std_ulogic := 'X';
signal R_dly : std_ulogic := 'X';
signal S_dly : std_ulogic := 'X';
signal Q1_zd : std_ulogic := 'X';
signal Q2_zd : std_ulogic := 'X';
signal Q1_viol : std_ulogic := 'X';
signal Q2_viol : std_ulogic := 'X';
signal Q1_o_reg : std_ulogic := 'X';
signal Q2_o_reg : std_ulogic := 'X';
signal Q3_o_reg : std_ulogic := 'X';
signal Q4_o_reg : std_ulogic := 'X';
signal ddr_clk_edge_type : integer := -999;
signal sr_type : integer := -999;
begin
---------------------
-- INPUT PATH DELAYs
--------------------
C_dly <= C after 0 ps;
CE_dly <= CE after 0 ps;
D_dly <= D after 0 ps;
GSR_dly <= GSR after 0 ps;
R_dly <= R after 0 ps;
S_dly <= S after 0 ps;
--------------------
-- BEHAVIOR SECTION
--------------------
--####################################################################
--##### Initialize #####
--####################################################################
prcs_init:process
begin
if((DDR_CLK_EDGE = "OPPOSITE_EDGE") or (DDR_CLK_EDGE = "opposite_edge")) then
ddr_clk_edge_type <= 1;
elsif((DDR_CLK_EDGE = "SAME_EDGE") or (DDR_CLK_EDGE = "same_edge")) then
ddr_clk_edge_type <= 2;
elsif((DDR_CLK_EDGE = "SAME_EDGE_PIPELINED") or (DDR_CLK_EDGE = "same_edge_pipelined")) then
ddr_clk_edge_type <= 3;
else
GenericValueCheckMessage
( HeaderMsg => " Attribute Syntax Warning ",
GenericName => " DDR_CLK_EDGE ",
EntityName => "/IDDR",
GenericValue => DDR_CLK_EDGE,
Unit => "",
ExpectedValueMsg => " The Legal values for this attribute are ",
ExpectedGenericValue => " OPPOSITE_EDGE or SAME_EDGE or SAME_EDGE_PIPELINED.",
TailMsg => "",
MsgSeverity => ERROR
);
end if;
if((SRTYPE = "ASYNC") or (SRTYPE = "async")) then
sr_type <= 1;
elsif((SRTYPE = "SYNC") or (SRTYPE = "sync")) then
sr_type <= 2;
else
GenericValueCheckMessage
( HeaderMsg => " Attribute Syntax Warning ",
GenericName => " SRTYPE ",
EntityName => "/IDDR",
GenericValue => SRTYPE,
Unit => "",
ExpectedValueMsg => " The Legal values for this attribute are ",
ExpectedGenericValue => " ASYNC or SYNC. ",
TailMsg => "",
MsgSeverity => ERROR
);
end if;
wait;
end process prcs_init;
--####################################################################
--##### q1_q2_q3_q4 reg #####
--####################################################################
prcs_q1q2q3q4_reg:process(C_dly, D_dly, GSR_dly, R_dly, S_dly)
variable Q1_var : std_ulogic := TO_X01(INIT_Q1);
variable Q2_var : std_ulogic := TO_X01(INIT_Q2);
variable Q3_var : std_ulogic := TO_X01(INIT_Q1);
variable Q4_var : std_ulogic := TO_X01(INIT_Q2);
begin
if(GSR_dly = '1') then
Q1_var := TO_X01(INIT_Q1);
Q3_var := TO_X01(INIT_Q1);
Q2_var := TO_X01(INIT_Q2);
Q4_var := TO_X01(INIT_Q2);
elsif(GSR_dly = '0') then
case sr_type is
when 1 =>
if(R_dly = '1') then
Q1_var := '0';
Q2_var := '0';
Q3_var := '0';
Q4_var := '0';
elsif((R_dly = '0') and (S_dly = '1')) then
Q1_var := '1';
Q2_var := '1';
Q3_var := '1';
Q4_var := '1';
elsif((R_dly = '0') and (S_dly = '0')) then
if(CE_dly = '1') then
if(rising_edge(C_dly)) then
Q3_var := Q1_var;
Q1_var := D_dly;
Q4_var := Q2_var;
end if;
if(falling_edge(C_dly)) then
Q2_var := D_dly;
end if;
end if;
end if;
when 2 =>
if(rising_edge(C_dly)) then
if(R_dly = '1') then
Q1_var := '0';
Q3_var := '0';
Q4_var := '0';
elsif((R_dly = '0') and (S_dly = '1')) then
Q1_var := '1';
Q3_var := '1';
Q4_var := '1';
elsif((R_dly = '0') and (S_dly = '0')) then
if(CE_dly = '1') then
Q3_var := Q1_var;
Q1_var := D_dly;
Q4_var := Q2_var;
end if;
end if;
end if;
if(falling_edge(C_dly)) then
if(R_dly = '1') then
Q2_var := '0';
elsif((R_dly = '0') and (S_dly = '1')) then
Q2_var := '1';
elsif((R_dly = '0') and (S_dly = '0')) then
if(CE_dly = '1') then
Q2_var := D_dly;
end if;
end if;
end if;
when others =>
null;
end case;
end if;
q1_o_reg <= Q1_var;
q2_o_reg <= Q2_var;
q3_o_reg <= Q3_var;
q4_o_reg <= Q4_var;
end process prcs_q1q2q3q4_reg;
--####################################################################
--##### q1 & q2 mux #####
--####################################################################
prcs_q1q2_mux:process(q1_o_reg, q2_o_reg, q3_o_reg, q4_o_reg)
begin
case ddr_clk_edge_type is
when 1 =>
Q1_zd <= q1_o_reg;
Q2_zd <= q2_o_reg;
when 2 =>
Q1_zd <= q1_o_reg;
Q2_zd <= q4_o_reg;
when 3 =>
Q1_zd <= q3_o_reg;
Q2_zd <= q4_o_reg;
when others =>
null;
end case;
end process prcs_q1q2_mux;
--####################################################################
--####################################################################
--##### OUTPUT #####
--####################################################################
prcs_output:process(Q1_zd, Q2_zd)
begin
Q1 <= Q1_zd after SYNC_PATH_DELAY;
Q2 <= Q2_zd after SYNC_PATH_DELAY;
end process prcs_output;
--####################################################################
end IDDR_V;
library IEEE;
use IEEE.STD_LOGIC_1164.all;
--use unisim.vpkg.all;
library unisim;
use unisim.vpkg.all;
entity ODDR is
generic(
DDR_CLK_EDGE : string := "OPPOSITE_EDGE";
INIT : bit := '0';
SRTYPE : string := "SYNC"
);
port(
Q : out std_ulogic;
C : in std_ulogic;
CE : in std_ulogic;
D1 : in std_ulogic;
D2 : in std_ulogic;
R : in std_ulogic;
S : in std_ulogic
);
end ODDR;
architecture ODDR_V OF ODDR is
constant SYNC_PATH_DELAY : time := 100 ps;
signal C_ipd : std_ulogic := 'X';
signal CE_ipd : std_ulogic := 'X';
signal D1_ipd : std_ulogic := 'X';
signal D2_ipd : std_ulogic := 'X';
signal GSR : std_ulogic := '0';
signal GSR_ipd : std_ulogic := 'X';
signal R_ipd : std_ulogic := 'X';
signal S_ipd : std_ulogic := 'X';
signal C_dly : std_ulogic := 'X';
signal CE_dly : std_ulogic := 'X';
signal D1_dly : std_ulogic := 'X';
signal D2_dly : std_ulogic := 'X';
signal GSR_dly : std_ulogic := 'X';
signal R_dly : std_ulogic := 'X';
signal S_dly : std_ulogic := 'X';
signal Q_zd : std_ulogic := 'X';
signal Q_viol : std_ulogic := 'X';
signal ddr_clk_edge_type : integer := -999;
signal sr_type : integer := -999;
begin
---------------------
-- INPUT PATH DELAYs
--------------------
C_dly <= C after 0 ps;
CE_dly <= CE after 0 ps;
D1_dly <= D1 after 0 ps;
D2_dly <= D2 after 0 ps;
GSR_dly <= GSR after 0 ps;
R_dly <= R after 0 ps;
S_dly <= S after 0 ps;
--------------------
-- BEHAVIOR SECTION
--------------------
--####################################################################
--##### Initialize #####
--####################################################################
prcs_init:process
begin
if((DDR_CLK_EDGE = "OPPOSITE_EDGE") or (DDR_CLK_EDGE = "opposite_edge")) then
ddr_clk_edge_type <= 1;
elsif((DDR_CLK_EDGE = "SAME_EDGE") or (DDR_CLK_EDGE = "same_edge")) then
ddr_clk_edge_type <= 2;
else
GenericValueCheckMessage
( HeaderMsg => " Attribute Syntax Warning ",
GenericName => " DDR_CLK_EDGE ",
EntityName => "/ODDR",
GenericValue => DDR_CLK_EDGE,
Unit => "",
ExpectedValueMsg => " The Legal values for this attribute are ",
ExpectedGenericValue => " OPPOSITE_EDGE or SAME_EDGE.",
TailMsg => "",
MsgSeverity => ERROR
);
end if;
if((SRTYPE = "ASYNC") or (SRTYPE = "async")) then
sr_type <= 1;
elsif((SRTYPE = "SYNC") or (SRTYPE = "sync")) then
sr_type <= 2;
else
GenericValueCheckMessage
( HeaderMsg => " Attribute Syntax Warning ",
GenericName => " SRTYPE ",
EntityName => "/ODDR",
GenericValue => SRTYPE,
Unit => "",
ExpectedValueMsg => " The Legal values for this attribute are ",
ExpectedGenericValue => " ASYNC or SYNC. ",
TailMsg => "",
MsgSeverity => ERROR
);
end if;
wait;
end process prcs_init;
--####################################################################
--##### q1_q2_q3 reg #####
--####################################################################
prcs_q1q2q3_reg:process(C_dly, GSR_dly, R_dly, S_dly)
variable Q1_var : std_ulogic := TO_X01(INIT);
variable Q2_posedge_var : std_ulogic := TO_X01(INIT);
begin
if(GSR_dly = '1') then
Q1_var := TO_X01(INIT);
Q2_posedge_var := TO_X01(INIT);
elsif(GSR_dly = '0') then
case sr_type is
when 1 =>
if(R_dly = '1') then
Q1_var := '0';
Q2_posedge_var := '0';
elsif((R_dly = '0') and (S_dly = '1')) then
Q1_var := '1';
Q2_posedge_var := '1';
elsif((R_dly = '0') and (S_dly = '0')) then
if(CE_dly = '1') then
if(rising_edge(C_dly)) then
Q1_var := D1_dly;
Q2_posedge_var := D2_dly;
end if;
if(falling_edge(C_dly)) then
case ddr_clk_edge_type is
when 1 =>
Q1_var := D2_dly;
when 2 =>
Q1_var := Q2_posedge_var;
when others =>
null;
end case;
end if;
end if;
end if;
when 2 =>
if(rising_edge(C_dly)) then
if(R_dly = '1') then
Q1_var := '0';
Q2_posedge_var := '0';
elsif((R_dly = '0') and (S_dly = '1')) then
Q1_var := '1';
Q2_posedge_var := '1';
elsif((R_dly = '0') and (S_dly = '0')) then
if(CE_dly = '1') then
Q1_var := D1_dly;
Q2_posedge_var := D2_dly;
end if;
end if;
end if;
if(falling_edge(C_dly)) then
if(R_dly = '1') then
Q1_var := '0';
elsif((R_dly = '0') and (S_dly = '1')) then
Q1_var := '1';
elsif((R_dly = '0') and (S_dly = '0')) then
if(CE_dly = '1') then
case ddr_clk_edge_type is
when 1 =>
Q1_var := D2_dly;
when 2 =>
Q1_var := Q2_posedge_var;
when others =>
null;
end case;
end if;
end if;
end if;
when others =>
null;
end case;
end if;
Q_zd <= Q1_var;
end process prcs_q1q2q3_reg;
--####################################################################
--####################################################################
--##### OUTPUT #####
--####################################################################
prcs_output:process(Q_zd)
begin
Q <= Q_zd after SYNC_PATH_DELAY;
end process prcs_output;
--####################################################################
end ODDR_V;
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity FDDRRSE is
generic(
INIT : bit := '0'
);
port(
Q : out std_ulogic;
C0 : in std_ulogic;
C1 : in std_ulogic;
CE : in std_ulogic;
D0 : in std_ulogic;
D1 : in std_ulogic;
R : in std_ulogic;
S : in std_ulogic
);
end FDDRRSE;
architecture FDDRRSE_V of FDDRRSE is
begin
VITALBehavior : process(C0, C1)
variable FIRST_TIME : boolean := true;
begin
if (FIRST_TIME) then
Q <= TO_X01(INIT);
FIRST_TIME := false ;
end if;
if ( rising_edge(C0) = true) then
if (R = '1') then
Q <= '0' after 100 ps;
elsif (S = '1' ) then
Q <= '1' after 100 ps;
elsif (CE = '1' ) then
Q <= D0 after 100 ps;
end if;
elsif (rising_edge(C1) = true ) then
if (R = '1') then
Q <= '0' after 100 ps;
elsif (S = '1' ) then
Q <= '1' after 100 ps;
elsif (CE = '1') then
Q <= D1 after 100 ps;
end if;
end if;
end process VITALBehavior;
end FDDRRSE_V;
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library UNISIM;
use UNISIM.VCOMPONENTS.all;
entity OFDDRRSE is
port(
Q : out std_ulogic;
C0 : in std_ulogic;
C1 : in std_ulogic;
CE : in std_ulogic;
D0 : in std_ulogic;
D1 : in std_ulogic;
R : in std_ulogic;
S : in std_ulogic
);
end OFDDRRSE;
architecture OFDDRRSE_V of OFDDRRSE is
signal Q_out : std_ulogic := 'X';
begin
O1 : OBUF
port map (
I => Q_out,
O => Q
);
F0 : FDDRRSE
generic map (INIT => '0'
)
port map (
C0 => C0,
C1 => C1,
CE => CE,
R => R,
D0 => D0,
D1 => D1,
S => S,
Q => Q_out
);
end OFDDRRSE_V;
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity FDRSE is
generic(
INIT : bit := '0'
);
port(
Q : out std_ulogic;
C : in std_ulogic;
CE : in std_ulogic;
D : in std_ulogic;
R : in std_ulogic;
S : in std_ulogic
);
end FDRSE;
architecture FDRSE_V of FDRSE is
begin
VITALBehavior : process(C)
variable FIRST_TIME : boolean := true ;
begin
if (FIRST_TIME = true) then
Q <= TO_X01(INIT);
FIRST_TIME := false;
end if;
if (rising_edge(C)) then
if (R = '1') then
Q <= '0' after 100 ps;
elsif (S = '1') then
Q <= '1' after 100 ps;
elsif (CE = '1') then
Q <= D after 100 ps;
end if;
end if;
end process;
end FDRSE_V;
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library UNISIM;
use UNISIM.VCOMPONENTS.all;
entity IFDDRRSE is
port(
Q0 : out std_ulogic;
Q1 : out std_ulogic;
C0 : in std_ulogic;
C1 : in std_ulogic;
CE : in std_ulogic;
D : in std_ulogic;
R : in std_ulogic;
S : in std_ulogic
);
end IFDDRRSE;
architecture IFDDRRSE_V of IFDDRRSE is
signal D_in : std_ulogic := 'X';
begin
I1 : IBUF
port map (
I => D,
O => D_in
);
F0 : FDRSE
generic map (
INIT => '0')
port map (
C => C0,
CE => CE,
R => R,
D => D_in,
S => S,
Q => Q0
);
F1 : FDRSE
generic map (
INIT => '0')
port map (
C => C1,
CE => CE,
R => R,
D => D,
S => S,
Q => Q1
);
end IFDDRRSE_V;
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity FD is
generic(
INIT : bit := '0'
);
port(
Q : out std_ulogic;
C : in std_ulogic;
D : in std_ulogic
);
end FD;
architecture FD_V of FD is
begin
VITALBehavior : process(C)
variable FIRST_TIME : boolean := true ;
begin
if (FIRST_TIME = true) then
Q <= TO_X01(INIT);
FIRST_TIME := false;
end if;
if (rising_edge(C)) then
Q <= D after 100 ps;
end if;
end process;
end FD_V;
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity FDR is
generic(
INIT : bit := '0'
);
port(
Q : out std_ulogic;
C : in std_ulogic;
D : in std_ulogic;
R : in std_ulogic
);
end FDR;
architecture FDR_V of FDR is
begin
VITALBehavior : process(C)
variable FIRST_TIME : boolean := true ;
begin
if (FIRST_TIME = true) then
Q <= TO_X01(INIT);
FIRST_TIME := false;
end if;
if (rising_edge(C)) then
if (R = '1') then
Q <= '0' after 100 ps;
else
Q <= D after 100 ps;
end if;
end if;
end process;
end FDR_V;
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity FDRE is
generic(
INIT : bit := '0'
);
port(
Q : out std_ulogic;
C : in std_ulogic;
CE : in std_ulogic;
D : in std_ulogic;
R : in std_ulogic
);
end FDRE;
architecture FDRE_V of FDRE is
begin
VITALBehavior : process(C)
variable FIRST_TIME : boolean := true ;
begin
if (FIRST_TIME = true) then
Q <= TO_X01(INIT);
FIRST_TIME := false;
end if;
if (rising_edge(C)) then
if (R = '1') then
Q <= '0' after 100 ps;
elsif (CE = '1') then
Q <= D after 100 ps;
end if;
end if;
end process;
end FDRE_V;
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity FDRS is
generic(
INIT : bit := '0'
);
port(
Q : out std_ulogic;
C : in std_ulogic;
D : in std_ulogic;
R : in std_ulogic;
S : in std_ulogic
);
end FDRS;
architecture FDRS_V of FDRS is
begin
VITALBehavior : process(C)
variable FIRST_TIME : boolean := true ;
begin
if (FIRST_TIME = true) then
Q <= TO_X01(INIT);
FIRST_TIME := false;
end if;
if (rising_edge(C)) then
if (R = '1') then
Q <= '0' after 100 ps;
elsif (S = '1') then
Q <= '1' after 100 ps;
else
Q <= D after 100 ps;
end if;
end if;
end process;
end FDRS_V;
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity VCC is
port(
P : out std_ulogic := '1'
);
end VCC;
architecture VCC_V of VCC is
begin
P <= '1';
end VCC_V;
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity GND is
port(
G : out std_ulogic := '0'
);
end GND;
architecture GND_V of GND is
begin
G <= '0';
end GND_V;
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity MUXF5 is
port(
O : out std_ulogic;
I0 : in std_ulogic;
I1 : in std_ulogic;
S : in std_ulogic
);
end MUXF5;
architecture MUXF5_V of MUXF5 is
begin
VITALBehavior : process (I0, I1, S)
begin
if (S = '0') then
O <= I0;
elsif (S = '1') then
O <= I1;
end if;
end process;
end MUXF5_V;
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity FDE is
generic(
INIT : bit := '0'
);
port(
Q : out std_ulogic;
C : in std_ulogic;
CE : in std_ulogic;
D : in std_ulogic
);
end FDE;
architecture FDE_V of FDE is
begin
VITALBehavior : process(C)
variable FIRST_TIME : boolean := true ;
begin
if (FIRST_TIME = true) then
Q <= TO_X01(INIT);
FIRST_TIME := false;
end if;
if (rising_edge(C)) then
if (CE = '1') then
Q <= D after 100 ps;
end if;
end if;
end process;
end FDE_V;
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library unisim;
use unisim.vpkg.all;
entity IDELAY is
generic(
IOBDELAY_TYPE : string := "DEFAULT";
IOBDELAY_VALUE : integer := 0
);
port(
O : out std_ulogic;
C : in std_ulogic;
CE : in std_ulogic;
I : in std_ulogic;
INC : in std_ulogic;
RST : in std_ulogic
);
end IDELAY;
architecture IDELAY_V OF IDELAY is
constant SIM_TAPDELAY_VALUE : integer := 75;
---------------------------------------------------------
-- Function str_2_int converts string to integer
---------------------------------------------------------
function str_2_int(str: in string ) return integer is
variable int : integer;
variable val : integer := 0;
variable neg_flg : boolean := false;
variable is_it_int : boolean := true;
begin
int := 0;
val := 0;
is_it_int := true;
neg_flg := false;
for i in 1 to str'length loop
case str(i) is
when '-'
=>
if(i = 1) then
neg_flg := true;
val := -1;
end if;
when '1'
=> val := 1;
when '2'
=> val := 2;
when '3'
=> val := 3;
when '4'
=> val := 4;
when '5'
=> val := 5;
when '6'
=> val := 6;
when '7'
=> val := 7;
when '8'
=> val := 8;
when '9'
=> val := 9;
when '0'
=> val := 0;
when others
=> is_it_int := false;
end case;
if(val /= -1) then
int := int *10 + val;
end if;
val := 0;
end loop;
if(neg_flg) then
int := int * (-1);
end if;
if(NOT is_it_int) then
int := -9999;
end if;
return int;
end;
-----------------------------------------------------------
constant SYNC_PATH_DELAY : time := 100 ps;
constant MIN_TAP_COUNT : integer := 0;
constant MAX_TAP_COUNT : integer := 63;
signal C_ipd : std_ulogic := 'X';
signal CE_ipd : std_ulogic := 'X';
signal GSR : std_ulogic := '0';
signal GSR_ipd : std_ulogic := 'X';
signal I_ipd : std_ulogic := 'X';
signal INC_ipd : std_ulogic := 'X';
signal RST_ipd : std_ulogic := 'X';
signal C_dly : std_ulogic := 'X';
signal CE_dly : std_ulogic := 'X';
signal GSR_dly : std_ulogic := 'X';
signal I_dly : std_ulogic := 'X';
signal INC_dly : std_ulogic := 'X';
signal RST_dly : std_ulogic := 'X';
signal O_zd : std_ulogic := 'X';
signal O_viol : std_ulogic := 'X';
signal TapCount : integer := 0;
signal IsTapDelay : boolean := true;
signal IsTapFixed : boolean := false;
signal IsTapDefault : boolean := false;
signal Delay : time := 0 ps;
begin
---------------------
-- INPUT PATH DELAYs
--------------------
C_dly <= C after 0 ps;
CE_dly <= CE after 0 ps;
GSR_dly <= GSR after 0 ps;
I_dly <= I after 0 ps;
INC_dly <= INC after 0 ps;
RST_dly <= RST after 0 ps;
--------------------
-- BEHAVIOR SECTION
--------------------
--####################################################################
--##### Initialize #####
--####################################################################
prcs_init:process
variable TapCount_var : integer := 0;
variable IsTapDelay_var : boolean := true;
variable IsTapFixed_var : boolean := false;
variable IsTapDefault_var : boolean := false;
begin
-- if((IOBDELAY_VALUE = "OFF") or (IOBDELAY_VALUE = "off")) then
-- IsTapDelay_var := false;
-- elsif((IOBDELAY_VALUE = "ON") or (IOBDELAY_VALUE = "on")) then
-- IsTapDelay_var := false;
-- else
-- TapCount_var := str_2_int(IOBDELAY_VALUE);
TapCount_var := IOBDELAY_VALUE;
If((TapCount_var >= 0) and (TapCount_var <= 63)) then
IsTapDelay_var := true;
else
GenericValueCheckMessage
( HeaderMsg => " Attribute Syntax Warning ",
GenericName => " IOBDELAY_VALUE ",
EntityName => "/IOBDELAY_VALUE",
GenericValue => IOBDELAY_VALUE,
Unit => "",
ExpectedValueMsg => " The Legal values for this attribute are ",
ExpectedGenericValue => " OFF, 1, 2, ..., 62, 63 ",
TailMsg => "",
MsgSeverity => failure
);
end if;
-- end if;
if(IsTapDelay_var) then
if((IOBDELAY_TYPE = "FIXED") or (IOBDELAY_TYPE = "fixed")) then
IsTapFixed_var := true;
elsif((IOBDELAY_TYPE = "VARIABLE") or (IOBDELAY_TYPE = "variable")) then
IsTapFixed_var := false;
elsif((IOBDELAY_TYPE = "DEFAULT") or (IOBDELAY_TYPE = "default")) then
IsTapDefault_var := true;
else
GenericValueCheckMessage
( HeaderMsg => " Attribute Syntax Warning ",
GenericName => " IOBDELAY_TYPE ",
EntityName => "/IOBDELAY_TYPE",
GenericValue => IOBDELAY_TYPE,
Unit => "",
ExpectedValueMsg => " The Legal values for this attribute are ",
ExpectedGenericValue => " FIXED or VARIABLE ",
TailMsg => "",
MsgSeverity => failure
);
end if;
end if;
IsTapDelay <= IsTapDelay_var;
IsTapFixed <= IsTapFixed_var;
IsTapDefault <= IsTapDefault_var;
TapCount <= TapCount_var;
wait;
end process prcs_init;
--####################################################################
--##### CALCULATE DELAY #####
--####################################################################
prcs_refclk:process(C_dly, GSR_dly, RST_dly)
variable TapCount_var : integer :=0;
variable FIRST_TIME : boolean :=true;
variable BaseTime_var : time := 1 ps ;
variable delay_var : time := 0 ps ;
begin
if(IsTapDelay) then
if((GSR_dly = '1') or (FIRST_TIME))then
TapCount_var := TapCount;
Delay <= TapCount_var * SIM_TAPDELAY_VALUE * BaseTime_var;
FIRST_TIME := false;
elsif(GSR_dly = '0') then
if(rising_edge(C_dly)) then
if(RST_dly = '1') then
TapCount_var := TapCount;
elsif((RST_dly = '0') and (CE_dly = '1')) then
-- CR fix CR 213995
if(INC_dly = '1') then
if (TapCount_var < MAX_TAP_COUNT) then
TapCount_var := TapCount_var + 1;
else
TapCount_var := MIN_TAP_COUNT;
end if;
elsif(INC_dly = '0') then
if (TapCount_var > MIN_TAP_COUNT) then
TapCount_var := TapCount_var - 1;
else
TapCount_var := MAX_TAP_COUNT;
end if;
end if; -- INC_dly
end if; -- RST_dly
Delay <= TapCount_var * SIM_TAPDELAY_VALUE * BaseTime_var;
end if; -- C_dly
end if; -- GSR_dly
end if; -- IsTapDelay
end process prcs_refclk;
--####################################################################
--##### DELAY INPUT #####
--####################################################################
prcs_i:process(I_dly)
begin
if(IsTapFixed) then
O_zd <= transport I_dly after (TapCount *SIM_TAPDELAY_VALUE * 1 ps);
else
O_zd <= transport I_dly after delay;
end if;
end process prcs_i;
--####################################################################
--##### OUTPUT #####
--####################################################################
prcs_output:process(O_zd)
begin
O <= O_zd after SYNC_PATH_DELAY;
end process prcs_output;
--####################################################################
end IDELAY_V;
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library unisim;
use unisim.vpkg.all;
entity IDELAYCTRL is
port(
RDY : out std_ulogic;
REFCLK : in std_ulogic;
RST : in std_ulogic
);
end IDELAYCTRL;
architecture IDELAYCTRL_V OF IDELAYCTRL is
constant SYNC_PATH_DELAY : time := 100 ps;
signal REFCLK_ipd : std_ulogic := 'X';
signal RST_ipd : std_ulogic := 'X';
signal GSR_dly : std_ulogic := '0';
signal REFCLK_dly : std_ulogic := 'X';
signal RST_dly : std_ulogic := 'X';
signal RDY_zd : std_ulogic := '0';
signal RDY_viol : std_ulogic := 'X';
-- taken from DCM_adv
signal period : time := 0 ps;
signal lost : std_ulogic := '0';
signal lost_r : std_ulogic := '0';
signal lost_f : std_ulogic := '0';
signal clock_negedge, clock_posedge, clock : std_ulogic;
signal temp1 : boolean := false;
signal temp2 : boolean := false;
signal clock_low, clock_high : std_ulogic := '0';
begin
---------------------
-- INPUT PATH DELAYs
--------------------
REFCLK_dly <= REFCLK after 0 ps;
RST_dly <= RST after 0 ps;
--------------------
-- BEHAVIOR SECTION
--------------------
--####################################################################
--##### RDY #####
--####################################################################
prcs_rdy:process(RST_dly, lost)
begin
if((RST_dly = '1') or (lost = '1')) then
RDY_zd <= '0';
elsif((RST_dly = '0') and (lost = '0')) then
RDY_zd <= '1';
end if;
end process prcs_rdy;
--####################################################################
--##### prcs_determine_period #####
--####################################################################
prcs_determine_period : process
variable clock_edge_previous : time := 0 ps;
variable clock_edge_current : time := 0 ps;
begin
if (rising_edge(REFCLK_dly)) then
clock_edge_previous := clock_edge_current;
clock_edge_current := NOW;
if (period /= 0 ps and ((clock_edge_current - clock_edge_previous) <= (1.5 * period))) then
period <= NOW - clock_edge_previous;
elsif (period /= 0 ps and ((NOW - clock_edge_previous) > (1.5 * period))) then
period <= 0 ps;
elsif ((period = 0 ps) and (clock_edge_previous /= 0 ps)) then
period <= NOW - clock_edge_previous;
end if;
end if;
wait on REFCLK_dly;
end process prcs_determine_period;
--####################################################################
--##### prcs_clock_lost_checker #####
--####################################################################
prcs_clock_lost_checker : process
variable clock_low, clock_high : std_ulogic := '0';
begin
if (rising_edge(clock)) then
clock_low := '0';
clock_high := '1';
clock_posedge <= '0';
clock_negedge <= '1';
end if;
if (falling_edge(clock)) then
clock_high := '0';
clock_low := '1';
clock_posedge <= '1';
clock_negedge <= '0';
end if;
wait on clock;
end process prcs_clock_lost_checker;
--####################################################################
--##### prcs_set_reset_lost_r #####
--####################################################################
prcs_set_reset_lost_r : process
begin
if (rising_edge(clock)) then
if (period /= 0 ps) then
lost_r <= '0';
end if;
wait for (period * 9.1)/10;
if ((clock_low /= '1') and (clock_posedge /= '1')) then
lost_r <= '1';
end if;
end if;
wait on clock;
end process prcs_set_reset_lost_r;
--####################################################################
--##### prcs_assign_lost #####
--####################################################################
prcs_assign_lost : process
begin
if (lost_r'event) then
lost <= lost_r;
end if;
if (lost_f'event) then
lost <= lost_f;
end if;
wait on lost_r, lost_f;
end process prcs_assign_lost;
--####################################################################
--##### OUTPUT #####
--####################################################################
prcs_output:process(RDY_zd)
begin
RDY <= RDY_zd after SYNC_PATH_DELAY;
end process prcs_output;
--####################################################################
end IDELAYCTRL_V;
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity BUFIO is
port(
O : out std_ulogic;
I : in std_ulogic
);
end BUFIO;
architecture BUFIO_V of BUFIO is
begin
O <= I after 0 ps;
end BUFIO_V;
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library unisim;
use unisim.vpkg.all;
entity BUFR is
generic(
BUFR_DIVIDE : string := "BYPASS";
SIM_DEVICE : string := "VIRTEX4"
);
port(
O : out std_ulogic;
CE : in std_ulogic;
CLR : in std_ulogic;
I : in std_ulogic
);
end BUFR;
architecture BUFR_V OF BUFR is
-- 06/30/2005 - CR # 211199 --
-- constant SYNC_PATH_DELAY : time := 100 ps;
signal CE_ipd : std_ulogic := 'X';
signal GSR : std_ulogic := '0';
signal GSR_ipd : std_ulogic := '0';
signal I_ipd : std_ulogic := 'X';
signal CLR_ipd : std_ulogic := 'X';
signal CE_dly : std_ulogic := 'X';
signal GSR_dly : std_ulogic := '0';
signal I_dly : std_ulogic := 'X';
signal CLR_dly : std_ulogic := 'X';
signal O_zd : std_ulogic := 'X';
signal O_viol : std_ulogic := 'X';
signal q4_sig : std_ulogic := 'X';
signal ce_en : std_ulogic;
signal divide : boolean := false;
signal divide_by : integer := -1;
signal FIRST_TOGGLE_COUNT : integer := -1;
signal SECOND_TOGGLE_COUNT : integer := -1;
begin
---------------------
-- INPUT PATH DELAYs
--------------------
CE_dly <= CE after 0 ps;
CLR_dly <= CLR after 0 ps;
GSR_dly <= GSR after 0 ps;
I_dly <= I after 0 ps;
--------------------
-- BEHAVIOR SECTION
--------------------
--####################################################################
--##### Initialize #####
--####################################################################
prcs_init:process
variable FIRST_TOGGLE_COUNT_var : integer := -1;
variable SECOND_TOGGLE_COUNT_var : integer := -1;
variable ODD : integer := -1;
variable divide_var : boolean := false;
variable divide_by_var : integer := -1;
begin
if(BUFR_DIVIDE = "BYPASS") then
divide_var := false;
elsif(BUFR_DIVIDE = "1") then
divide_var := true;
divide_by_var := 1;
FIRST_TOGGLE_COUNT_var := 1;
SECOND_TOGGLE_COUNT_var := 1;
elsif(BUFR_DIVIDE = "2") then
divide_var := true;
divide_by_var := 2;
FIRST_TOGGLE_COUNT_var := 2;
SECOND_TOGGLE_COUNT_var := 2;
elsif(BUFR_DIVIDE = "3") then
divide_var := true;
divide_by_var := 3;
FIRST_TOGGLE_COUNT_var := 2;
SECOND_TOGGLE_COUNT_var := 4;
elsif(BUFR_DIVIDE = "4") then
divide_var := true;
divide_by_var := 4;
FIRST_TOGGLE_COUNT_var := 4;
SECOND_TOGGLE_COUNT_var := 4;
elsif(BUFR_DIVIDE = "5") then
divide_var := true;
divide_by_var := 5;
FIRST_TOGGLE_COUNT_var := 4;
SECOND_TOGGLE_COUNT_var := 6;
elsif(BUFR_DIVIDE = "6") then
divide_var := true;
divide_by_var := 6;
FIRST_TOGGLE_COUNT_var := 6;
SECOND_TOGGLE_COUNT_var := 6;
elsif(BUFR_DIVIDE = "7") then
divide_var := true;
divide_by_var := 7;
FIRST_TOGGLE_COUNT_var := 6;
SECOND_TOGGLE_COUNT_var := 8;
elsif(BUFR_DIVIDE = "8") then
divide_var := true;
divide_by_var := 8;
FIRST_TOGGLE_COUNT_var := 8;
SECOND_TOGGLE_COUNT_var := 8;
else
GenericValueCheckMessage
( HeaderMsg => " Attribute Syntax Warning ",
GenericName => " BUFR_DIVIDE ",
EntityName => "/BUFR",
GenericValue => BUFR_DIVIDE,
Unit => "",
ExpectedValueMsg => " The Legal values for this attribute are ",
ExpectedGenericValue => " BYPASS, 1, 2, 3, 4, 5, 6, 7 or 8 ",
TailMsg => "",
MsgSeverity => ERROR
);
end if;
if (SIM_DEVICE /= "VIRTEX4" and SIM_DEVICE /= "VIRTEX5") then
GenericValueCheckMessage
( HeaderMsg => " Attribute Syntax Warning ",
GenericName => " SIM_DEVICE ",
EntityName => "/BUFR",
GenericValue => SIM_DEVICE,
Unit => "",
ExpectedValueMsg => " The Legal values for this attribute are ",
ExpectedGenericValue => " VIRTEX4 or VIRTEX5 ",
TailMsg => "",
MsgSeverity => ERROR
);
end if;
FIRST_TOGGLE_COUNT <= FIRST_TOGGLE_COUNT_var;
SECOND_TOGGLE_COUNT <= SECOND_TOGGLE_COUNT_var;
divide <= divide_var;
divide_by <= divide_by_var;
wait;
end process prcs_init;
--####################################################################
--##### CLOCK_ENABLE #####
--####################################################################
prcs_ce:process(I_Dly, GSR_dly)
variable fall_i_count : integer := 0;
variable q4_var : std_ulogic := '0';
variable q3_var : std_ulogic := '0';
variable q2_var : std_ulogic := '0';
variable q1_var : std_ulogic := '0';
begin
-- 06/30/2005 - CR # 211199 -- removed CLR_dly dependency
if(GSR_dly = '1') then
q4_var := '0';
q3_var := '0';
q2_var := '0';
q1_var := '0';
elsif(GSR_dly = '0') then
if(falling_edge(I_dly)) then
q4_var := q3_var;
q3_var := q2_var;
q2_var := q1_var;
q1_var := CE_dly;
end if;
q4_sig <= q4_var;
end if;
end process prcs_ce;
ce_en <= CE_dly when (SIM_DEVICE = "VIRTEX5") else q4_sig;
--####################################################################
--##### CLK-I #####
--####################################################################
prcs_I:process(I_dly, GSR_dly, CLR_dly, ce_en)
variable clk_count : integer := 0;
variable toggle_count : integer := 0;
variable first : boolean := true;
variable FIRST_TIME : boolean := true;
begin
if(divide) then
if((GSR_dly = '1') or (CLR_dly = '1')) then
O_zd <= '0';
clk_count := 0;
FIRST_TIME := true;
elsif((GSR_dly = '0') and (CLR_dly = '0')) then
if(ce_en = '1') then
if((I_dly='1') and (FIRST_TIME)) then
O_zd <= '1';
first := true;
toggle_count := FIRST_TOGGLE_COUNT;
FIRST_TIME := false;
elsif ((I_dly'event) and ( FIRST_TIME = false)) then
if(clk_count = toggle_count) then
O_zd <= not O_zd;
clk_count := 0;
first := not first;
if(first = true) then
toggle_count := FIRST_TOGGLE_COUNT;
else
toggle_count := SECOND_TOGGLE_COUNT;
end if;
end if;
end if;
if (FIRST_TIME = false) then
clk_count := clk_count + 1;
end if;
else
clk_count := 0;
FIRST_TIME := true;
end if;
end if;
else
O_zd <= I_dly;
end if;
end process prcs_I;
--####################################################################
--##### OUTPUT #####
--####################################################################
prcs_output:process(O_zd)
begin
-- 06/30/2005 - CR # 211199 --
-- O <= O_zd after SYNC_PATH_DELAY;
O <= O_zd;
end process prcs_output;
--####################################################################
end BUFR_V;
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library unisim;
use unisim.vpkg.all;
entity ODDR2 is
generic(
DDR_ALIGNMENT : string := "NONE";
INIT : bit := '0';
SRTYPE : string := "SYNC"
);
port(
Q : out std_ulogic;
C0 : in std_ulogic;
C1 : in std_ulogic;
CE : in std_ulogic;
D0 : in std_ulogic;
D1 : in std_ulogic;
R : in std_ulogic;
S : in std_ulogic
);
end ODDR2;
architecture ODDR2_V OF ODDR2 is
constant SYNC_PATH_DELAY : time := 100 ps;
signal C0_ipd : std_ulogic := 'X';
signal C1_ipd : std_ulogic := 'X';
signal CE_ipd : std_ulogic := 'X';
signal D0_ipd : std_ulogic := 'X';
signal D1_ipd : std_ulogic := 'X';
signal GSR : std_ulogic := '0';
signal GSR_ipd : std_ulogic := 'X';
signal R_ipd : std_ulogic := 'X';
signal S_ipd : std_ulogic := 'X';
signal C0_dly : std_ulogic := 'X';
signal C1_dly : std_ulogic := 'X';
signal CE_dly : std_ulogic := 'X';
signal D0_dly : std_ulogic := 'X';
signal D1_dly : std_ulogic := 'X';
signal GSR_dly : std_ulogic := 'X';
signal R_dly : std_ulogic := 'X';
signal S_dly : std_ulogic := 'X';
signal Q_zd : std_ulogic := 'X';
signal Q_viol : std_ulogic := 'X';
signal ddr_alignment_type : integer := -999;
signal sr_type : integer := -999;
begin
---------------------
-- INPUT PATH DELAYs
--------------------
C0_dly <= C0 after 0 ps;
C1_dly <= C1 after 0 ps;
CE_dly <= CE after 0 ps;
D0_dly <= D0 after 0 ps;
D1_dly <= D1 after 0 ps;
GSR_dly <= GSR after 0 ps;
R_dly <= R after 0 ps;
S_dly <= S after 0 ps;
--------------------
-- BEHAVIOR SECTION
--------------------
--####################################################################
--##### Initialize #####
--####################################################################
prcs_init:process
begin
if((DDR_ALIGNMENT = "NONE") or (DDR_ALIGNMENT = "none")) then
ddr_alignment_type <= 1;
elsif((DDR_ALIGNMENT = "C0") or (DDR_ALIGNMENT = "c0")) then
ddr_alignment_type <= 2;
elsif((DDR_ALIGNMENT = "C1") or (DDR_ALIGNMENT = "c1")) then
ddr_alignment_type <= 3;
else
GenericValueCheckMessage
( HeaderMsg => " Attribute Syntax Error :",
GenericName => " DDR_ALIGNMENT ",
EntityName => "/ODDR2",
GenericValue => DDR_ALIGNMENT,
Unit => "",
ExpectedValueMsg => " The Legal values for this attribute are ",
ExpectedGenericValue => " NONE, C0 or C1.",
TailMsg => "",
MsgSeverity => failure
);
end if;
if((SRTYPE = "ASYNC") or (SRTYPE = "async")) then
sr_type <= 1;
elsif((SRTYPE = "SYNC") or (SRTYPE = "sync")) then
sr_type <= 2;
else
GenericValueCheckMessage
( HeaderMsg => " Attribute Syntax Error :",
GenericName => " SRTYPE ",
EntityName => "/ODDR2",
GenericValue => SRTYPE,
Unit => "",
ExpectedValueMsg => " The Legal values for this attribute are ",
ExpectedGenericValue => " ASYNC or SYNC. ",
TailMsg => "",
MsgSeverity => failure
);
end if;
wait;
end process prcs_init;
--####################################################################
--##### functionality #####
--####################################################################
prcs_func_reg:process(C0_dly, C1_dly, GSR_dly, R_dly, S_dly)
variable FIRST_TIME : boolean := true;
variable q_var : std_ulogic := TO_X01(INIT);
variable q_d0_c1_out_var : std_ulogic := TO_X01(INIT);
variable q_d1_c0_out_var : std_ulogic := TO_X01(INIT);
begin
if((GSR_dly = '1') or (FIRST_TIME)) then
q_var := TO_X01(INIT);
q_d0_c1_out_var := TO_X01(INIT);
q_d1_c0_out_var := TO_X01(INIT);
FIRST_TIME := false;
else
case sr_type is
when 1 =>
if(R_dly = '1') then
q_var := '0';
q_d0_c1_out_var := '0';
q_d1_c0_out_var := '0';
elsif((R_dly = '0') and (S_dly = '1')) then
q_var := '1';
q_d0_c1_out_var := '1';
q_d1_c0_out_var := '1';
elsif((R_dly = '0') and (S_dly = '0')) then
if(CE_dly = '1') then
if(rising_edge(C0_dly)) then
if(ddr_alignment_type = 3) then
q_var := q_d0_c1_out_var;
else
q_var := D0_dly;
if(ddr_alignment_type = 2) then
q_d1_c0_out_var := D1_dly;
end if;
end if;
end if;
if(rising_edge(C1_dly)) then
if(ddr_alignment_type = 2) then
q_var := q_d1_c0_out_var;
else
q_var := D1_dly;
if(ddr_alignment_type = 3) then
q_d0_c1_out_var := D0_dly;
end if;
end if;
end if;
end if;
end if;
when 2 =>
if(rising_edge(C0_dly)) then
if(R_dly = '1') then
q_var := '0';
q_d1_c0_out_var := '0';
elsif((R_dly = '0') and (S_dly = '1')) then
q_var := '1';
q_d1_c0_out_var := '1';
elsif((R_dly = '0') and (S_dly = '0')) then
if(CE_dly = '1') then
if(ddr_alignment_type = 3) then
q_var := q_d0_c1_out_var;
else
q_var := D0_dly;
if(ddr_alignment_type = 2) then
q_d1_c0_out_var := D1_dly;
end if;
end if;
end if;
end if;
end if;
if(rising_edge(C1_dly)) then
if(R_dly = '1') then
q_var := '0';
q_d0_c1_out_var := '0';
elsif((R_dly = '0') and (S_dly = '1')) then
q_var := '1';
q_d0_c1_out_var := '1';
elsif((R_dly = '0') and (S_dly = '0')) then
if(CE_dly = '1') then
if(ddr_alignment_type = 2) then
q_var := q_d1_c0_out_var;
else
q_var := D1_dly;
if(ddr_alignment_type = 3) then
q_d0_c1_out_var := D0_dly;
end if;
end if;
end if;
end if;
end if;
when others =>
null;
end case;
end if;
Q_zd <= q_var;
end process prcs_func_reg;
--####################################################################
--####################################################################
--##### OUTPUT #####
--####################################################################
prcs_output:process(Q_zd)
begin
Q <= Q_zd after SYNC_PATH_DELAY;
end process prcs_output;
--####################################################################
end ODDR2_V;
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library unisim;
use unisim.vpkg.all;
entity IDDR2 is
generic(
DDR_ALIGNMENT : string := "NONE";
INIT_Q0 : bit := '0';
INIT_Q1 : bit := '0';
SRTYPE : string := "SYNC"
);
port(
Q0 : out std_ulogic;
Q1 : out std_ulogic;
C0 : in std_ulogic;
C1 : in std_ulogic;
CE : in std_ulogic;
D : in std_ulogic;
R : in std_ulogic;
S : in std_ulogic
);
end IDDR2;
architecture IDDR2_V OF IDDR2 is
constant SYNC_PATH_DELAY : time := 100 ps;
signal C0_ipd : std_ulogic := 'X';
signal C1_ipd : std_ulogic := 'X';
signal CE_ipd : std_ulogic := 'X';
signal D_ipd : std_ulogic := 'X';
signal GSR : std_ulogic := '0';
signal GSR_ipd : std_ulogic := 'X';
signal R_ipd : std_ulogic := 'X';
signal S_ipd : std_ulogic := 'X';
signal C0_dly : std_ulogic := 'X';
signal C1_dly : std_ulogic := 'X';
signal CE_dly : std_ulogic := 'X';
signal D_dly : std_ulogic := 'X';
signal GSR_dly : std_ulogic := 'X';
signal R_dly : std_ulogic := 'X';
signal S_dly : std_ulogic := 'X';
signal Q0_zd : std_ulogic := 'X';
signal Q1_zd : std_ulogic := 'X';
signal Q0_viol : std_ulogic := 'X';
signal Q1_viol : std_ulogic := 'X';
signal q0_o_reg : std_ulogic := 'X';
signal q0_c1_o_reg : std_ulogic := 'X';
signal q1_o_reg : std_ulogic := 'X';
signal q1_c0_o_reg : std_ulogic := 'X';
signal ddr_alignment_type : integer := -999;
signal sr_type : integer := -999;
begin
---------------------
-- INPUT PATH DELAYs
--------------------
C0_dly <= C0 after 0 ps;
C1_dly <= C1 after 0 ps;
CE_dly <= CE after 0 ps;
D_dly <= D after 0 ps;
GSR_dly <= GSR after 0 ps;
R_dly <= R after 0 ps;
S_dly <= S after 0 ps;
--------------------
-- BEHAVIOR SECTION
--------------------
--####################################################################
--##### Initialize #####
--####################################################################
prcs_init:process
begin
if((DDR_ALIGNMENT = "NONE") or (DDR_ALIGNMENT = "none")) then
ddr_alignment_type <= 1;
elsif((DDR_ALIGNMENT = "C0") or (DDR_ALIGNMENT = "c0")) then
ddr_alignment_type <= 2;
elsif((DDR_ALIGNMENT = "C1") or (DDR_ALIGNMENT = "c1")) then
ddr_alignment_type <= 3;
else
GenericValueCheckMessage
( HeaderMsg => " Attribute Syntax Error ",
GenericName => " DDR_ALIGNMENT ",
EntityName => "/IDDR2",
GenericValue => DDR_ALIGNMENT,
Unit => "",
ExpectedValueMsg => " The Legal values for this attribute are ",
ExpectedGenericValue => " NONE or C0 or C1.",
TailMsg => "",
MsgSeverity => ERROR
);
end if;
if((SRTYPE = "ASYNC") or (SRTYPE = "async")) then
sr_type <= 1;
elsif((SRTYPE = "SYNC") or (SRTYPE = "sync")) then
sr_type <= 2;
else
GenericValueCheckMessage
( HeaderMsg => " Attribute Syntax Error ",
GenericName => " SRTYPE ",
EntityName => "/IDDR2",
GenericValue => SRTYPE,
Unit => "",
ExpectedValueMsg => " The Legal values for this attribute are ",
ExpectedGenericValue => " ASYNC or SYNC. ",
TailMsg => "",
MsgSeverity => ERROR
);
end if;
wait;
end process prcs_init;
--####################################################################
--##### functionality #####
--####################################################################
prcs_func_reg:process(C0_dly, C1_dly, D_dly, GSR_dly, R_dly, S_dly)
variable FIRST_TIME : boolean := true;
variable q0_out_var : std_ulogic := TO_X01(INIT_Q0);
variable q1_out_var : std_ulogic := TO_X01(INIT_Q1);
variable q0_c1_out_var : std_ulogic := TO_X01(INIT_Q0);
variable q1_c0_out_var : std_ulogic := TO_X01(INIT_Q1);
begin
if((GSR_dly = '1') or (FIRST_TIME)) then
q0_out_var := TO_X01(INIT_Q0);
q1_out_var := TO_X01(INIT_Q1);
q0_c1_out_var := TO_X01(INIT_Q0);
q1_c0_out_var := TO_X01(INIT_Q1);
FIRST_TIME := false;
else
case sr_type is
when 1 =>
if(R_dly = '1') then
q0_out_var := '0';
q1_out_var := '0';
q1_c0_out_var := '0';
q0_c1_out_var := '0';
elsif((R_dly = '0') and (S_dly = '1')) then
q0_out_var := '1';
q1_out_var := '1';
q1_c0_out_var := '1';
q0_c1_out_var := '1';
elsif((R_dly = '0') and (S_dly = '0')) then
if(CE_dly = '1') then
if(rising_edge(C0_dly)) then
q0_out_var := D_dly;
q1_c0_out_var := q1_out_var;
end if;
if(rising_edge(C1_dly)) then
q1_out_var := D_dly;
q0_c1_out_var := q0_out_var;
end if;
end if;
end if;
when 2 =>
if(rising_edge(C0_dly)) then
if(R_dly = '1') then
q0_out_var := '0';
q1_c0_out_var := '0';
elsif((R_dly = '0') and (S_dly = '1')) then
q0_out_var := '1';
q1_c0_out_var := '1';
elsif((R_dly = '0') and (S_dly = '0')) then
if(CE_dly = '1') then
q0_out_var := D_dly;
q1_c0_out_var := q1_out_var;
end if;
end if;
end if;
if(rising_edge(C1_dly)) then
if(R_dly = '1') then
q1_out_var := '0';
q0_c1_out_var := '0';
elsif((R_dly = '0') and (S_dly = '1')) then
q1_out_var := '1';
q0_c1_out_var := '1';
elsif((R_dly = '0') and (S_dly = '0')) then
if(CE_dly = '1') then
q1_out_var := D_dly;
q0_c1_out_var := q0_out_var;
end if;
end if;
end if;
when others =>
null;
end case;
end if;
q0_o_reg <= q0_out_var;
q1_o_reg <= q1_out_var;
q0_c1_o_reg <= q0_c1_out_var;
q1_c0_o_reg <= q1_c0_out_var;
end process prcs_func_reg;
--####################################################################
--##### output mux #####
--####################################################################
prcs_output_mux:process(q0_o_reg, q1_o_reg, q0_c1_o_reg, q1_c0_o_reg)
begin
case ddr_alignment_type is
when 1 =>
Q0_zd <= q0_o_reg;
Q1_zd <= q1_o_reg;
when 2 =>
Q0_zd <= q0_o_reg;
Q1_zd <= q1_c0_o_reg;
when 3 =>
Q0_zd <= q0_c1_o_reg;
Q1_zd <= q1_o_reg;
when others =>
null;
end case;
end process prcs_output_mux;
--####################################################################
--####################################################################
--##### OUTPUT #####
--####################################################################
prcs_output:process(Q0_zd, Q1_zd)
begin
Q0 <= Q0_zd after SYNC_PATH_DELAY;
Q1 <= Q1_zd after SYNC_PATH_DELAY;
end process prcs_output;
--####################################################################
end IDDR2_V;
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor : Xilinx
-- \ \ \/ Version : 9.1i
-- \ \ Description : Xilinx Timing Simulation Library Component
-- / / Digital Clock Manager
-- /___/ /\ Filename : X_DCM.vhd
-- \ \ / \ Timestamp : Fri Jun 18 10:57:08 PDT 2004
-- \___\/\___\
--
-- Revision:
-- 03/23/04 - Initial version.
-- 05/11/05 - Add clkin alignment check control to remove the glitch when
-- clkin stopped. (CR207409).
-- 05/25/05 - Seperate clock_second_pos and neg to another process due to
-- wait caused unreset. Set fb_delay_found after fb_delay computed.
-- Enable clkfb_div after lock_fb high (CR 208771)
-- 06/03/05 - Use after instead wait for clk0_out(CR209283).
-- Update error message (CR 209076).
-- 07/06/05 - Add lock_fb_dly to alignment check. (CR210755).
-- Use counter to generate clkdv_out to align with clk0_out. (CR211465).
-- 07/25/05 - Set CLKIN_PERIOD default to 10.0ns to (CR 213190).
-- 08/30/05 - Change reset for CLK270, CLK180 (CR 213641).
-- 09/08/05 - Add positive edge trig to dcm_maximum_period_check_v. (CR 216828).
-- 12/22/05 - LOCKED = x when RST less than 3 clock cycles (CR 222795)
-- 02/28/06 - Remove 1 ps in clkfx_out block to support fs resolution (CR222390)
-- 09/22/06 - Add lock_period and lock_fb to clkfb_div block (CR418722).
-- 12/19/06 - Add clkfb_div_en for clkfb2x divider (CR431210).
-- 04/06/07 - Enable the clock out in clock low time after reset in model
-- clock_divide_by_2 (CR 437471).
-- End Revision
----- x_dcm_clock_divide_by_2 -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity x_dcm_clock_divide_by_2 is
port(
clock_out : out std_ulogic := '0';
clock : in std_ulogic;
clock_type : in integer;
rst : in std_ulogic
);
end x_dcm_clock_divide_by_2;
architecture x_dcm_clock_divide_by_2_V of x_dcm_clock_divide_by_2 is
signal clock_div2 : std_ulogic := '0';
signal rst_reg : std_logic_vector(2 downto 0);
signal clk_src : std_ulogic;
begin
CLKIN_DIVIDER : process
begin
if (rising_edge(clock)) then
clock_div2 <= not clock_div2;
end if;
wait on clock;
end process CLKIN_DIVIDER;
gen_reset : process
begin
if (rising_edge(clock)) then
rst_reg(0) <= rst;
rst_reg(1) <= rst_reg(0) and rst;
rst_reg(2) <= rst_reg(1) and rst_reg(0) and rst;
end if;
wait on clock;
end process gen_reset;
clk_src <= clock_div2 when (clock_type = 1) else clock;
assign_clkout : process
begin
if (rst = '0') then
clock_out <= clk_src;
elsif (rst = '1') then
clock_out <= '0';
wait until falling_edge(rst_reg(2));
if (clk_src = '1') then
wait until falling_edge(clk_src);
end if;
end if;
wait on clk_src, rst, rst_reg;
end process assign_clkout;
end x_dcm_clock_divide_by_2_V;
----- x_dcm_maximum_period_check -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library STD;
use STD.TEXTIO.all;
entity x_dcm_maximum_period_check is
generic (
InstancePath : string := "*";
clock_name : string := "";
maximum_period : time);
port(
clock : in std_ulogic;
rst : in std_ulogic
);
end x_dcm_maximum_period_check;
architecture x_dcm_maximum_period_check_V of x_dcm_maximum_period_check is
begin
MAX_PERIOD_CHECKER : process
variable clock_edge_previous : time := 0 ps;
variable clock_edge_current : time := 0 ps;
variable clock_period : time := 0 ps;
variable Message : line;
begin
if (rising_edge(clock)) then
clock_edge_previous := clock_edge_current;
clock_edge_current := NOW;
if (clock_edge_previous > 0 ps) then
clock_period := clock_edge_current - clock_edge_previous;
end if;
if (clock_period > maximum_period and rst = '0') then
Write ( Message, string'(" Warning : Input Clock Period of "));
Write ( Message, clock_period );
Write ( Message, string'(" on the ") );
Write ( Message, clock_name );
Write ( Message, string'(" port ") );
Write ( Message, string'(" of X_DCM instance ") );
Write ( Message, string'(" exceeds allowed value of ") );
Write ( Message, maximum_period );
Write ( Message, string'(" at simulation time ") );
Write ( Message, clock_edge_current );
Write ( Message, '.' & LF );
assert false report Message.all severity warning;
DEALLOCATE (Message);
end if;
end if;
wait on clock;
end process MAX_PERIOD_CHECKER;
end x_dcm_maximum_period_check_V;
----- x_dcm_clock_lost -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity x_dcm_clock_lost is
port(
lost : out std_ulogic := '0';
clock : in std_ulogic;
enable : in boolean := false;
rst : in std_ulogic
);
end x_dcm_clock_lost;
architecture x_dcm_clock_lost_V of x_dcm_clock_lost is
signal period : time := 0 ps;
signal lost_r : std_ulogic := '0';
signal lost_f : std_ulogic := '0';
signal lost_sig : std_ulogic := '0';
signal clock_negedge, clock_posedge : std_ulogic;
signal clock_low, clock_high : std_ulogic := '0';
signal clock_second_pos, clock_second_neg : std_ulogic := '0';
begin
determine_period : process
variable clock_edge_previous : time := 0 ps;
variable clock_edge_current : time := 0 ps;
begin
if (rst = '1') then
period <= 0 ps;
elsif (rising_edge(clock)) then
clock_edge_previous := clock_edge_current;
clock_edge_current := NOW;
if (period /= 0 ps and ((clock_edge_current - clock_edge_previous) <= (1.5 * period))) then
period <= NOW - clock_edge_previous;
elsif (period /= 0 ps and ((NOW - clock_edge_previous) > (1.5 * period))) then
period <= 0 ps;
elsif ((period = 0 ps) and (clock_edge_previous /= 0 ps) and (clock_second_pos = '1')) then
period <= NOW - clock_edge_previous;
end if;
end if;
wait on clock, rst;
end process determine_period;
CLOCK_LOST_CHECKER : process
begin
if (rst = '1') then
clock_low <= '0';
clock_high <= '0';
clock_posedge <= '0';
clock_negedge <= '0';
else
if (rising_edge(clock)) then
clock_low <= '0';
clock_high <= '1';
clock_posedge <= '0';
clock_negedge <= '1';
end if;
if (falling_edge(clock)) then
clock_high <= '0';
clock_low <= '1';
clock_posedge <= '1';
clock_negedge <= '0';
end if;
end if;
wait on clock, rst;
end process CLOCK_LOST_CHECKER;
CLOCK_SECOND_P : process
begin
if (rst = '1') then
clock_second_pos <= '0';
clock_second_neg <= '0';
else
if (rising_edge(clock)) then
clock_second_pos <= '1';
end if;
if (falling_edge(clock)) then
clock_second_neg <= '1';
end if;
end if;
wait on clock, rst;
end process CLOCK_SECOND_P;
SET_RESET_LOST_R : process
begin
if (rst = '1') then
lost_r <= '0';
else
if ((enable = true) and (clock_second_pos = '1'))then
if (rising_edge(clock)) then
wait for 1 ps;
if (period /= 0 ps) then
lost_r <= '0';
end if;
wait for (period * (9.1/10.0));
if ((clock_low /= '1') and (clock_posedge /= '1') and (rst = '0')) then
lost_r <= '1';
end if;
end if;
end if;
end if;
wait on clock, rst;
end process SET_RESET_LOST_R;
SET_RESET_LOST_F : process
begin
if (rst = '1') then
lost_f <= '0';
else
if ((enable = true) and (clock_second_neg = '1'))then
if (falling_edge(clock)) then
if (period /= 0 ps) then
lost_f <= '0';
end if;
wait for (period * (9.1/10.0));
if ((clock_high /= '1') and (clock_negedge /= '1') and (rst = '0')) then
lost_f <= '1';
end if;
end if;
end if;
end if;
wait on clock, rst;
end process SET_RESET_LOST_F;
assign_lost : process
begin
if (enable = true) then
if (lost_r'event) then
lost <= lost_r;
end if;
if (lost_f'event) then
lost <= lost_f;
end if;
end if;
wait on lost_r, lost_f;
end process assign_lost;
end x_dcm_clock_lost_V;
----- CELL X_DCM -----
library IEEE;
use IEEE.std_logic_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
library STD;
use STD.TEXTIO.all;
library unisim;
use unisim.vpkg.all;
entity X_DCM is
generic (
TimingChecksOn : boolean := true;
InstancePath : string := "*";
Xon : boolean := true;
MsgOn : boolean := false;
LOC : string := "UNPLACED";
thold_PSEN_PSCLK_negedge_posedge : VitalDelayType := 0.000 ns;
thold_PSEN_PSCLK_posedge_posedge : VitalDelayType := 0.000 ns;
thold_PSINCDEC_PSCLK_negedge_posedge : VitalDelayType := 0.000 ns;
thold_PSINCDEC_PSCLK_posedge_posedge : VitalDelayType := 0.000 ns;
ticd_PSCLK : VitalDelayType := 0.000 ns;
tipd_CLKFB : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_CLKIN : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_DSSEN : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_PSCLK : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_PSEN : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_PSINCDEC : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_RST : VitalDelayType01 := (0.000 ns, 0.000 ns);
tisd_PSINCDEC_PSCLK : VitalDelayType := 0.000 ns;
tisd_PSEN_PSCLK : VitalDelayType := 0.000 ns;
tpd_CLKIN_LOCKED : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_PSCLK_PSDONE : VitalDelayType01 := (0.100 ns, 0.100 ns);
tperiod_CLKIN_POSEDGE : VitalDelayType := 0.000 ns;
tperiod_PSCLK_POSEDGE : VitalDelayType := 0.000 ns;
tpw_CLKIN_negedge : VitalDelayType := 0.000 ns;
tpw_CLKIN_posedge : VitalDelayType := 0.000 ns;
tpw_PSCLK_negedge : VitalDelayType := 0.000 ns;
tpw_PSCLK_posedge : VitalDelayType := 0.000 ns;
tpw_RST_posedge : VitalDelayType := 0.000 ns;
tsetup_PSEN_PSCLK_negedge_posedge : VitalDelayType := 0.000 ns;
tsetup_PSEN_PSCLK_posedge_posedge : VitalDelayType := 0.000 ns;
tsetup_PSINCDEC_PSCLK_negedge_posedge : VitalDelayType := 0.000 ns;
tsetup_PSINCDEC_PSCLK_posedge_posedge : VitalDelayType := 0.000 ns;
CLKDV_DIVIDE : real := 2.0;
CLKFX_DIVIDE : integer := 1;
CLKFX_MULTIPLY : integer := 4;
CLKIN_DIVIDE_BY_2 : boolean := false;
CLKIN_PERIOD : real := 10.0; --non-simulatable
CLKOUT_PHASE_SHIFT : string := "NONE";
CLK_FEEDBACK : string := "1X";
DESKEW_ADJUST : string := "SYSTEM_SYNCHRONOUS"; --non-simulatable
DFS_FREQUENCY_MODE : string := "LOW";
DLL_FREQUENCY_MODE : string := "LOW";
DSS_MODE : string := "NONE"; --non-simulatable
DUTY_CYCLE_CORRECTION : boolean := true;
FACTORY_JF : bit_vector := X"C080"; --non-simulatable
MAXPERCLKIN : time := 1000000 ps; --non-modifiable simulation parameter
MAXPERPSCLK : time := 100000000 ps; --non-modifiable simulation parameter
PHASE_SHIFT : integer := 0;
SIM_CLKIN_CYCLE_JITTER : time := 300 ps; --non-modifiable simulation parameter
SIM_CLKIN_PERIOD_JITTER : time := 1000 ps; --non-modifiable simulation parameter
STARTUP_WAIT : boolean := false --non-simulatable
);
port (
CLK0 : out std_ulogic := '0';
CLK180 : out std_ulogic := '0';
CLK270 : out std_ulogic := '0';
CLK2X : out std_ulogic := '0';
CLK2X180 : out std_ulogic := '0';
CLK90 : out std_ulogic := '0';
CLKDV : out std_ulogic := '0';
CLKFX : out std_ulogic := '0';
CLKFX180 : out std_ulogic := '0';
LOCKED : out std_ulogic := '0';
PSDONE : out std_ulogic := '0';
STATUS : out std_logic_vector(7 downto 0) := "00000000";
CLKFB : in std_ulogic := '0';
CLKIN : in std_ulogic := '0';
DSSEN : in std_ulogic := '0';
PSCLK : in std_ulogic := '0';
PSEN : in std_ulogic := '0';
PSINCDEC : in std_ulogic := '0';
RST : in std_ulogic := '0'
);
attribute VITAL_LEVEL0 of X_DCM : entity is true;
end X_DCM;
architecture X_DCM_V of X_DCM is
component x_dcm_clock_divide_by_2
port(
clock_out : out std_ulogic;
clock : in std_ulogic;
clock_type : in integer;
rst : in std_ulogic
);
end component;
component x_dcm_maximum_period_check
generic (
InstancePath : string := "*";
clock_name : string := "";
maximum_period : time);
port(
clock : in std_ulogic;
rst : in std_ulogic
);
end component;
component x_dcm_clock_lost
port(
lost : out std_ulogic;
clock : in std_ulogic;
enable : in boolean := false;
rst : in std_ulogic
);
end component;
signal CLKFB_ipd, CLKIN_ipd, DSSEN_ipd : std_ulogic;
signal PSCLK_ipd, PSEN_ipd, PSINCDEC_ipd, RST_ipd : std_ulogic;
signal PSCLK_dly ,PSEN_dly, PSINCDEC_dly : std_ulogic := '0';
signal clk0_out : std_ulogic;
signal clk2x_out, clkdv_out : std_ulogic := '0';
signal clkfx_out, locked_out, psdone_out, ps_overflow_out, ps_lock : std_ulogic := '0';
signal locked_out_out : std_ulogic := '0';
signal LOCKED_sig : std_ulogic := '0';
signal clkdv_cnt : integer := 0;
signal clkfb_type : integer;
signal divide_type : integer;
signal clkin_type : integer;
signal ps_type : integer;
signal deskew_adjust_mode : integer;
signal dfs_mode_type : integer;
signal dll_mode_type : integer;
signal clk1x_type : integer;
signal lock_period, lock_delay, lock_clkin, lock_clkfb : std_ulogic := '0';
signal lock_out : std_logic_vector(1 downto 0) := "00";
signal lock_out1_neg : std_ulogic := '0';
signal lock_fb : std_ulogic := '0';
signal lock_fb_dly : std_ulogic := '0';
signal lock_fb_dly_tmp : std_ulogic := '0';
signal fb_delay_found : std_ulogic := '0';
signal clkin_div : std_ulogic;
signal clkin_ps : std_ulogic;
signal clkin_fb : std_ulogic;
signal ps_delay : time := 0 ps;
signal clkin_period_real : VitalDelayArrayType(2 downto 0) := (0.000 ns, 0.000 ns, 0.000 ns);
signal period : time := 0 ps;
signal period_div : time := 0 ps;
signal period_orig : time := 0 ps;
signal period_ps : time := 0 ps;
signal clkout_delay : time := 0 ps;
signal fb_delay : time := 0 ps;
signal period_fx, remain_fx : time := 0 ps;
signal period_dv_high, period_dv_low : time := 0 ps;
signal cycle_jitter, period_jitter : time := 0 ps;
signal clkin_window, clkfb_window : std_ulogic := '0';
signal rst_reg : std_logic_vector(2 downto 0) := "000";
signal rst_flag : std_ulogic := '0';
signal numerator, denominator, gcd : integer := 1;
signal clkin_lost_out : std_ulogic := '0';
signal clkfx_lost_out : std_ulogic := '0';
signal remain_fx_temp : integer := 0;
signal clkin_period_real0_temp : time := 0 ps;
signal ps_lock_reg : std_ulogic := '0';
signal clk0_sig : std_ulogic := '0';
signal clk2x_sig : std_ulogic := '0';
signal no_stop : boolean := false;
signal clkfx180_en : std_ulogic := '0';
signal status_out : std_logic_vector(7 downto 0) := "00000000";
signal first_time_locked : boolean := false;
signal en_status : boolean := false;
signal ps_overflow_out_ext : std_ulogic := '0';
signal clkin_lost_out_ext : std_ulogic := '0';
signal clkfx_lost_out_ext : std_ulogic := '0';
signal clkfb_div : std_ulogic := '0';
signal clkfb_div_en : std_ulogic := '0';
signal clkfb_chk : std_ulogic := '0';
signal lock_period_dly : std_ulogic := '0';
signal lock_period_pulse : std_ulogic := '0';
signal clock_stopped : std_ulogic := '1';
signal clkin_chkin, clkfb_chkin : std_ulogic := '0';
signal chk_enable, chk_rst : std_ulogic := '0';
signal lock_ps : std_ulogic := '0';
signal lock_ps_dly : std_ulogic := '0';
begin
INITPROC : process
begin
detect_resolution
(model_name => "X_DCM"
);
if (CLKDV_DIVIDE = 1.5) then
divide_type <= 3;
elsif (CLKDV_DIVIDE = 2.0) then
divide_type <= 4;
elsif (CLKDV_DIVIDE = 2.5) then
divide_type <= 5;
elsif (CLKDV_DIVIDE = 3.0) then
divide_type <= 6;
elsif (CLKDV_DIVIDE = 3.5) then
divide_type <= 7;
elsif (CLKDV_DIVIDE = 4.0) then
divide_type <= 8;
elsif (CLKDV_DIVIDE = 4.5) then
divide_type <= 9;
elsif (CLKDV_DIVIDE = 5.0) then
divide_type <= 10;
elsif (CLKDV_DIVIDE = 5.5) then
divide_type <= 11;
elsif (CLKDV_DIVIDE = 6.0) then
divide_type <= 12;
elsif (CLKDV_DIVIDE = 6.5) then
divide_type <= 13;
elsif (CLKDV_DIVIDE = 7.0) then
divide_type <= 14;
elsif (CLKDV_DIVIDE = 7.5) then
divide_type <= 15;
elsif (CLKDV_DIVIDE = 8.0) then
divide_type <= 16;
elsif (CLKDV_DIVIDE = 9.0) then
divide_type <= 18;
elsif (CLKDV_DIVIDE = 10.0) then
divide_type <= 20;
elsif (CLKDV_DIVIDE = 11.0) then
divide_type <= 22;
elsif (CLKDV_DIVIDE = 12.0) then
divide_type <= 24;
elsif (CLKDV_DIVIDE = 13.0) then
divide_type <= 26;
elsif (CLKDV_DIVIDE = 14.0) then
divide_type <= 28;
elsif (CLKDV_DIVIDE = 15.0) then
divide_type <= 30;
elsif (CLKDV_DIVIDE = 16.0) then
divide_type <= 32;
else
GenericValueCheckMessage
(HeaderMsg => "Attribute Syntax Error",
GenericName => "CLKDV_DIVIDE",
EntityName => "X_DCM",
InstanceName => InstancePath,
GenericValue => CLKDV_DIVIDE,
Unit => "",
ExpectedValueMsg => "Legal Values for this attribute are 1.5, 2.0, 2.5, 3.0, 3.5, 4.0, 4.5, 5.0, 5.5, 6.0, 6.5, 7.0, 7.5, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, or 16.0",
ExpectedGenericValue => "",
TailMsg => "",
MsgSeverity => error
);
end if;
if ((CLKFX_DIVIDE <= 0) or (32 < CLKFX_DIVIDE)) then
GenericValueCheckMessage
(HeaderMsg => "Attribute Syntax Error",
GenericName => "CLKFX_DIVIDE",
EntityName => "X_DCM",
InstanceName => InstancePath,
GenericValue => CLKFX_DIVIDE,
Unit => "",
ExpectedValueMsg => "Legal Values for this attribute are 1....32",
ExpectedGenericValue => "",
TailMsg => "",
MsgSeverity => error
);
end if;
if ((CLKFX_MULTIPLY <= 1) or (32 < CLKFX_MULTIPLY)) then
GenericValueCheckMessage
(HeaderMsg => "Attribute Syntax Error",
GenericName => "CLKFX_MULTIPLY",
EntityName => "X_DCM",
InstanceName => InstancePath,
GenericValue => CLKFX_MULTIPLY,
Unit => "",
ExpectedValueMsg => "Legal Values for this attribute are 2....32",
ExpectedGenericValue => "",
TailMsg => "",
MsgSeverity => error
);
end if;
case CLKIN_DIVIDE_BY_2 is
when false => clkin_type <= 0;
when true => clkin_type <= 1;
when others =>
GenericValueCheckMessage
(HeaderMsg => "Attribute Syntax Error",
GenericName => "CLKIN_DIVIDE_BY_2",
EntityName => "X_DCM",
InstanceName => InstancePath,
GenericValue => CLKIN_DIVIDE_BY_2,
Unit => "",
ExpectedValueMsg => "Legal Values for this attribute are TRUE or FALSE",
ExpectedGenericValue => "",
TailMsg => "",
MsgSeverity => error
);
end case;
if ((CLKOUT_PHASE_SHIFT = "none") or (CLKOUT_PHASE_SHIFT = "NONE")) then
ps_type <= 0;
elsif ((CLKOUT_PHASE_SHIFT = "fixed") or (CLKOUT_PHASE_SHIFT = "FIXED")) then
ps_type <= 1;
elsif ((CLKOUT_PHASE_SHIFT = "variable") or (CLKOUT_PHASE_SHIFT = "VARIABLE")) then
ps_type <= 2;
else
GenericValueCheckMessage
(HeaderMsg => "Attribute Syntax Error",
GenericName => "CLKOUT_PHASE_SHIFT",
EntityName => "X_DCM",
InstanceName => InstancePath,
GenericValue => CLKOUT_PHASE_SHIFT,
Unit => "",
ExpectedValueMsg => "Legal Values for this attribute are NONE, FIXED or VARIABLE",
ExpectedGenericValue => "",
TailMsg => "",
MsgSeverity => error
);
end if;
if ((CLK_FEEDBACK = "none") or (CLK_FEEDBACK = "NONE")) then
clkfb_type <= 0;
elsif ((CLK_FEEDBACK = "1x") or (CLK_FEEDBACK = "1X")) then
clkfb_type <= 1;
elsif ((CLK_FEEDBACK = "2x") or (CLK_FEEDBACK = "2X")) then
clkfb_type <= 2;
else
GenericValueCheckMessage
(HeaderMsg => "Attribute Syntax Error",
GenericName => "CLK_FEEDBACK",
EntityName => "X_DCM",
InstanceName => InstancePath,
GenericValue => CLK_FEEDBACK,
Unit => "",
ExpectedValueMsg => "Legal Values for this attribute are NONE, 1X or 2X",
ExpectedGenericValue => "",
TailMsg => "",
MsgSeverity => error
);
end if;
if ((DESKEW_ADJUST = "source_synchronous") or (DESKEW_ADJUST = "SOURCE_SYNCHRONOUS")) then
DESKEW_ADJUST_mode <= 8;
elsif ((DESKEW_ADJUST = "system_synchronous") or (DESKEW_ADJUST = "SYSTEM_SYNCHRONOUS")) then
DESKEW_ADJUST_mode <= 11;
elsif ((DESKEW_ADJUST = "0")) then
DESKEW_ADJUST_mode <= 0;
elsif ((DESKEW_ADJUST = "1")) then
DESKEW_ADJUST_mode <= 1;
elsif ((DESKEW_ADJUST = "2")) then
DESKEW_ADJUST_mode <= 2;
elsif ((DESKEW_ADJUST = "3")) then
DESKEW_ADJUST_mode <= 3;
elsif ((DESKEW_ADJUST = "4")) then
DESKEW_ADJUST_mode <= 4;
elsif ((DESKEW_ADJUST = "5")) then
DESKEW_ADJUST_mode <= 5;
elsif ((DESKEW_ADJUST = "6")) then
DESKEW_ADJUST_mode <= 6;
elsif ((DESKEW_ADJUST = "7")) then
DESKEW_ADJUST_mode <= 7;
elsif ((DESKEW_ADJUST = "8")) then
DESKEW_ADJUST_mode <= 8;
elsif ((DESKEW_ADJUST = "9")) then
DESKEW_ADJUST_mode <= 9;
elsif ((DESKEW_ADJUST = "10")) then
DESKEW_ADJUST_mode <= 10;
elsif ((DESKEW_ADJUST = "11")) then
DESKEW_ADJUST_mode <= 11;
elsif ((DESKEW_ADJUST = "12")) then
DESKEW_ADJUST_mode <= 12;
elsif ((DESKEW_ADJUST = "13")) then
DESKEW_ADJUST_mode <= 13;
elsif ((DESKEW_ADJUST = "14")) then
DESKEW_ADJUST_mode <= 14;
elsif ((DESKEW_ADJUST = "15")) then
DESKEW_ADJUST_mode <= 15;
else
GenericValueCheckMessage
(HeaderMsg => "Attribute Syntax Error",
GenericName => "DESKEW_ADJUST_MODE",
EntityName => "X_DCM",
InstanceName => InstancePath,
GenericValue => DESKEW_ADJUST_MODE,
Unit => "",
ExpectedValueMsg => "Legal Values for this attribute are SOURCE_SYNCHRONOUS, SYSTEM_SYNCHRONOUS or 1....15",
ExpectedGenericValue => "",
TailMsg => "",
MsgSeverity => error
);
end if;
if ((DFS_FREQUENCY_MODE = "high") or (DFS_FREQUENCY_MODE = "HIGH")) then
dfs_mode_type <= 1;
elsif ((DFS_FREQUENCY_MODE = "low") or (DFS_FREQUENCY_MODE = "LOW")) then
dfs_mode_type <= 0;
else
GenericValueCheckMessage
(HeaderMsg => "Attribute Syntax Error",
GenericName => "DFS_FREQUENCY_MODE",
EntityName => "X_DCM",
InstanceName => InstancePath,
GenericValue => DFS_FREQUENCY_MODE,
Unit => "",
ExpectedValueMsg => "Legal Values for this attribute are HIGH or LOW",
ExpectedGenericValue => "",
TailMsg => "",
MsgSeverity => error
);
end if;
if ((DLL_FREQUENCY_MODE = "high") or (DLL_FREQUENCY_MODE = "HIGH")) then
dll_mode_type <= 1;
elsif ((DLL_FREQUENCY_MODE = "low") or (DLL_FREQUENCY_MODE = "LOW")) then
dll_mode_type <= 0;
else
GenericValueCheckMessage
(HeaderMsg => "Attribute Syntax Error",
GenericName => "DLL_FREQUENCY_MODE",
EntityName => "X_DCM",
InstanceName => InstancePath,
GenericValue => DLL_FREQUENCY_MODE,
Unit => "",
ExpectedValueMsg => "Legal Values for this attribute are HIGH or LOW",
ExpectedGenericValue => "",
TailMsg => "",
MsgSeverity => error
);
end if;
if ((DSS_MODE = "none") or (DSS_MODE = "NONE")) then
else
GenericValueCheckMessage
(HeaderMsg => "Attribute Syntax Error",
GenericName => "DSS_MODE",
EntityName => "X_DCM",
InstanceName => InstancePath,
GenericValue => DSS_MODE,
Unit => "",
ExpectedValueMsg => "Legal Values for this attribute are NONE",
ExpectedGenericValue => "",
TailMsg => "",
MsgSeverity => error
);
end if;
case DUTY_CYCLE_CORRECTION is
when false => clk1x_type <= 0;
when true => clk1x_type <= 1;
when others =>
GenericValueCheckMessage
(HeaderMsg => "Attribute Syntax Error",
GenericName => "DUTY_CYCLE_CORRECTION",
EntityName => "X_DCM",
InstanceName => InstancePath,
GenericValue => DUTY_CYCLE_CORRECTION,
Unit => "",
ExpectedValueMsg => "Legal Values for this attribute are TRUE or FALSE",
ExpectedGenericValue => "",
TailMsg => "",
MsgSeverity => error
);
end case;
if ((PHASE_SHIFT < -255) or (PHASE_SHIFT > 255)) then
GenericValueCheckMessage
(HeaderMsg => "Attribute Syntax Error",
GenericName => "PHASE_SHIFT",
EntityName => "X_DCM",
InstanceName => InstancePath,
GenericValue => PHASE_SHIFT,
Unit => "",
ExpectedValueMsg => "Legal Values for this attribute are -255 ... 255",
ExpectedGenericValue => "",
TailMsg => "",
MsgSeverity => error
);
end if;
period_jitter <= SIM_CLKIN_PERIOD_JITTER;
cycle_jitter <= SIM_CLKIN_CYCLE_JITTER;
case STARTUP_WAIT is
when false => null;
when true => null;
when others =>
GenericValueCheckMessage
(HeaderMsg => "Attribute Syntax Error",
GenericName => "STARTUP_WAIT",
EntityName => "X_DCM",
InstanceName => InstancePath,
GenericValue => STARTUP_WAIT,
Unit => "",
ExpectedValueMsg => "Legal Values for this attribute are TRUE or FALSE",
ExpectedGenericValue => "",
TailMsg => "",
MsgSeverity => error
);
end case;
--
-- fx parameters
--
gcd <= 1;
for i in 2 to CLKFX_MULTIPLY loop
if (((CLKFX_MULTIPLY mod i) = 0) and ((CLKFX_DIVIDE mod i) = 0)) then
gcd <= i;
end if;
end loop;
numerator <= CLKFX_MULTIPLY / gcd;
denominator <= CLKFX_DIVIDE / gcd;
wait;
end process INITPROC;
--
-- input wire delays
--
WireDelay : block
begin
VitalWireDelay (CLKIN_ipd, CLKIN, tipd_CLKIN);
VitalWireDelay (CLKFB_ipd, CLKFB, tipd_CLKFB);
VitalWireDelay (DSSEN_ipd, DSSEN, tipd_DSSEN);
VitalWireDelay (PSCLK_ipd, PSCLK, tipd_PSCLK);
VitalWireDelay (PSEN_ipd, PSEN, tipd_PSEN);
VitalWireDelay (PSINCDEC_ipd, PSINCDEC, tipd_PSINCDEC);
VitalWireDelay (RST_ipd, RST, tipd_RST);
end block;
SignalDelay : block
begin
VitalSignalDelay (PSCLK_dly, PSCLK_ipd, ticd_PSCLK);
VitalSignalDelay (PSEN_dly, PSEN_ipd, tisd_PSEN_PSCLK);
VitalSignalDelay (PSINCDEC_dly, PSINCDEC_ipd, tisd_PSINCDEC_PSCLK);
end block;
i_clock_divide_by_2 : x_dcm_clock_divide_by_2
port map (
clock => clkin_ipd,
clock_type => clkin_type,
rst => rst_ipd,
clock_out => clkin_div);
i_max_clkin : x_dcm_maximum_period_check
generic map (
clock_name => "CLKIN",
maximum_period => MAXPERCLKIN)
port map (
clock => clkin_ipd,
rst => rst_ipd);
i_max_psclk : x_dcm_maximum_period_check
generic map (
clock_name => "PSCLK",
maximum_period => MAXPERPSCLK)
port map (
clock => psclk_dly,
rst => rst_ipd);
i_clkin_lost : x_dcm_clock_lost
port map (
lost => clkin_lost_out,
clock => clkin_ipd,
enable => first_time_locked,
rst => rst_ipd
);
i_clkfx_lost : x_dcm_clock_lost
port map (
lost => clkfx_lost_out,
clock => clkfx_out,
enable => first_time_locked,
rst => rst_ipd
);
clkin_ps <= transport clkin_div after ps_delay;
clkin_fb <= transport (clkin_ps and lock_fb);
detect_first_time_locked : process
begin
if (first_time_locked = false) then
if (rising_edge(locked_out)) then
first_time_locked <= true;
end if;
end if;
wait on locked_out;
end process detect_first_time_locked;
set_reset_en_status : process
begin
if (rst_ipd = '1') then
en_status <= false;
elsif (rising_edge(Locked_sig)) then
en_status <= true;
end if;
wait on rst_ipd, Locked_sig;
end process set_reset_en_status;
gen_clkfb_div_en: process
begin
if (rst_ipd = '1') then
clkfb_div_en <= '0';
elsif (falling_edge(clkfb_ipd)) then
if (lock_fb_dly='1' and lock_period='1' and lock_fb = '1' and clkin_ps = '0') then
clkfb_div_en <= '1';
end if;
end if;
wait on clkfb_ipd, rst_ipd;
end process gen_clkfb_div_en;
gen_clkfb_div: process
begin
if (rst_ipd = '1') then
clkfb_div <= '0';
elsif (rising_edge(clkfb_ipd)) then
if (clkfb_div_en='1') then
clkfb_div <= not clkfb_div;
end if;
end if;
wait on clkfb_ipd, rst_ipd;
end process gen_clkfb_div;
determine_clkfb_chk: process
begin
if (clkfb_type = 2) then
clkfb_chk <= clkfb_div;
else
clkfb_chk <= clkfb_ipd and lock_fb_dly;
end if;
wait on clkfb_ipd, clkfb_div;
end process determine_clkfb_chk;
set_reset_clkin_chkin : process
begin
if ((rising_edge(clkin_fb)) or (rising_edge(chk_rst))) then
if (chk_rst = '1') then
clkin_chkin <= '0';
else
clkin_chkin <= '1';
end if;
end if;
wait on clkin_fb, chk_rst;
end process set_reset_clkin_chkin;
set_reset_clkfb_chkin : process
begin
if ((rising_edge(clkfb_chk)) or (rising_edge(chk_rst))) then
if (chk_rst = '1') then
clkfb_chkin <= '0';
else
clkfb_chkin <= '1';
end if;
end if;
wait on clkfb_chk, chk_rst;
end process set_reset_clkfb_chkin;
-- assign_chk_rst: process
-- begin
-- if ((rst_ipd = '1') or (clock_stopped = '1')) then
-- chk_rst <= '1';
-- else
-- chk_rst <= '0';
-- end if;
-- wait on rst_ipd, clock_stopped;
-- end process assign_chk_rst;
chk_rst <= '1' when ((rst_ipd = '1') or (clock_stopped = '1')) else '0';
-- assign_chk_enable: process
-- begin
-- if ((clkin_chkin = '1') and (clkfb_chkin = '1')) then
-- chk_enable <= '1';
-- else
-- chk_enable <= '0';
-- end if;
-- wait on clkin_chkin, clkfb_chkin;
-- end process assign_chk_enable;
chk_enable <= '1' when ((clkin_chkin = '1') and (clkfb_chkin = '1') and (lock_ps = '1') and (lock_fb_dly = '1') and (lock_fb = '1')) else '0';
control_status_bits: process
begin
if ((rst_ipd = '1') or (en_status = false)) then
ps_overflow_out_ext <= '0';
clkin_lost_out_ext <= '0';
clkfx_lost_out_ext <= '0';
else
ps_overflow_out_ext <= ps_overflow_out;
clkin_lost_out_ext <= clkin_lost_out;
clkfx_lost_out_ext <= clkfx_lost_out;
end if;
wait on clkfx_lost_out, clkin_lost_out, en_status, ps_overflow_out, rst_ipd;
end process control_status_bits;
determine_period_div : process
variable clkin_div_edge_previous : time := 0 ps;
variable clkin_div_edge_current : time := 0 ps;
begin
if ((rising_edge(rst_ipd)) or (rst_ipd = '1')) then
clkin_div_edge_previous := 0 ps;
clkin_div_edge_current := 0 ps;
period_div <= 0 ps;
else
if (rising_edge(clkin_div)) then
clkin_div_edge_previous := clkin_div_edge_current;
clkin_div_edge_current := NOW;
if ((clkin_div_edge_current - clkin_div_edge_previous) <= (1.5 * period_div)) then
period_div <= clkin_div_edge_current - clkin_div_edge_previous;
elsif ((period_div = 0 ps) and (clkin_div_edge_previous /= 0 ps)) then
period_div <= clkin_div_edge_current - clkin_div_edge_previous;
end if;
end if;
end if;
wait on clkin_div, rst_ipd;
end process determine_period_div;
determine_period_ps : process
variable clkin_ps_edge_previous : time := 0 ps;
variable clkin_ps_edge_current : time := 0 ps;
begin
if ((rising_edge(rst_ipd)) or (rst_ipd = '1')) then
clkin_ps_edge_previous := 0 ps;
clkin_ps_edge_current := 0 ps;
period_ps <= 0 ps;
else
if (rising_edge(clkin_ps)) then
clkin_ps_edge_previous := clkin_ps_edge_current;
clkin_ps_edge_current := NOW;
wait for 0 ps;
if ((clkin_ps_edge_current - clkin_ps_edge_previous) <= (1.5 * period_ps)) then
period_ps <= clkin_ps_edge_current - clkin_ps_edge_previous;
elsif ((period_ps = 0 ps) and (clkin_ps_edge_previous /= 0 ps)) then
period_ps <= clkin_ps_edge_current - clkin_ps_edge_previous;
end if;
end if;
end if;
wait on clkin_ps, rst_ipd;
end process determine_period_ps;
assign_lock_ps_fb : process
begin
if ((rising_edge(rst_ipd)) or (rst_ipd = '1')) then
lock_fb <= '0';
lock_ps <= '0';
lock_ps_dly <= '0';
lock_fb_dly <= '0';
lock_fb_dly_tmp <= '0';
else
if (rising_edge(clkin_ps)) then
lock_ps <= lock_period;
lock_ps_dly <= lock_ps;
lock_fb <= lock_ps_dly;
lock_fb_dly_tmp <= lock_fb;
end if;
if (falling_edge(clkin_ps)) then
lock_fb_dly <= lock_fb_dly_tmp after (period/4);
end if;
end if;
wait on clkin_ps, rst_ipd;
end process assign_lock_ps_fb;
calculate_clkout_delay : process
begin
if ((rising_edge(rst_ipd)) or (rst_ipd = '1')) then
clkout_delay <= 0 ps;
elsif (fb_delay = 0 ps) then
clkout_delay <= 0 ps;
elsif (period'event or fb_delay'event) then
clkout_delay <= period - fb_delay;
end if;
wait on period, fb_delay, rst_ipd;
end process calculate_clkout_delay;
--
--generate master reset signal
--
gen_master_rst : process
begin
if (rising_edge(clkin_ipd)) then
rst_reg(2) <= rst_reg(1) and rst_reg(0) and rst_ipd;
rst_reg(1) <= rst_reg(0) and rst_ipd;
rst_reg(0) <= rst_ipd;
end if;
wait on clkin_ipd;
end process gen_master_rst;
check_rst_width : process
variable Message : line;
begin
if (rst_ipd ='1') then
rst_flag <= '0';
end if;
if (falling_edge(rst_ipd)) then
if ((rst_reg(2) and rst_reg(1) and rst_reg(0)) = '0') then
rst_flag <= '1';
Write ( Message, string'(" Input Error : RST on X_DCM "));
Write ( Message, string'(" must be asserted for 3 CLKIN clock cycles. "));
assert false report Message.all severity error;
DEALLOCATE (Message);
end if;
end if;
wait on rst_ipd;
end process check_rst_width;
--
--phase shift parameters
--
determine_phase_shift : process
variable Message : line;
variable FINE_SHIFT_RANGE : time;
variable first_time : boolean := true;
variable ps_in : integer;
begin
if (first_time = true) then
if ((CLKOUT_PHASE_SHIFT = "none") or (CLKOUT_PHASE_SHIFT = "NONE")) then
ps_in := 256;
elsif ((CLKOUT_PHASE_SHIFT = "fixed") or (CLKOUT_PHASE_SHIFT = "FIXED")) then
ps_in := 256 + PHASE_SHIFT;
elsif ((CLKOUT_PHASE_SHIFT = "variable") or (CLKOUT_PHASE_SHIFT = "VARIABLE")) then
ps_in := 256 + PHASE_SHIFT;
end if;
first_time := false;
end if;
if ((rising_edge(rst_ipd)) or (rst_ipd = '1')) then
if ((CLKOUT_PHASE_SHIFT = "none") or (CLKOUT_PHASE_SHIFT = "NONE")) then
ps_in := 256;
elsif ((CLKOUT_PHASE_SHIFT = "fixed") or (CLKOUT_PHASE_SHIFT = "FIXED")) then
ps_in := 256 + PHASE_SHIFT;
elsif ((CLKOUT_PHASE_SHIFT = "variable") or (CLKOUT_PHASE_SHIFT = "VARIABLE")) then
ps_in := 256 + PHASE_SHIFT;
else
end if;
ps_lock <= '0';
ps_overflow_out <= '0';
ps_delay <= 0 ps;
else
if (rising_edge (lock_period)) then
if (ps_type = 1) then
FINE_SHIFT_RANGE := 10000 ps;
elsif (ps_type = 2) then
FINE_SHIFT_RANGE := 5000 ps;
end if;
if (PHASE_SHIFT > 0) then
if (((ps_in * period_orig) / 256) > (period_orig + FINE_SHIFT_RANGE)) then
Write ( Message, string'(" Function Error : Instance "));
Write ( Message, Instancepath );
Write ( Message, string'(" Requested Phase Shift = "));
Write ( Message, string'(" PHASE_SHIFT * PERIOD/256 = "));
Write ( Message, PHASE_SHIFT);
Write ( Message, string'(" * "));
Write ( Message, period_orig / 256);
Write ( Message, string'(" = "));
Write ( Message, (PHASE_SHIFT) * period_orig / 256 );
Write ( Message, string'(" This exceeds the FINE_SHIFT_RANGE of "));
Write ( Message, FINE_SHIFT_RANGE);
assert false report Message.all severity error;
DEALLOCATE (Message);
end if;
elsif (PHASE_SHIFT < 0) then
if ((period_orig > FINE_SHIFT_RANGE) and ((ps_in * period_orig / 256) < period_orig - FINE_SHIFT_RANGE)) then
Write ( Message, string'(" Function Error : Instance "));
Write ( Message, Instancepath );
Write ( Message, string'(" Requested Phase Shift = "));
Write ( Message, string'(" PHASE_SHIFT * PERIOD/256 = "));
Write ( Message, PHASE_SHIFT);
Write ( Message, string'(" * "));
Write ( Message, period_orig / 256);
Write ( Message, string'(" = "));
Write ( Message, (-PHASE_SHIFT) * period_orig / 256 );
Write ( Message, string'(" This exceeds the FINE_SHIFT_RANGE of "));
Write ( Message, FINE_SHIFT_RANGE);
assert false report Message.all severity error;
DEALLOCATE (Message);
end if;
end if;
end if;
if (rising_edge(lock_period_pulse)) then
ps_delay <= (ps_in * period_div / 256);
end if;
if (rising_edge(PSCLK_dly)) then
if (ps_type = 2) then
if (psen_dly = '1') then
if (ps_lock = '1') then
Write ( Message, string'(" Warning : Please wait for PSDONE signal before adjusting the Phase Shift. "));
assert false report Message.all severity warning;
DEALLOCATE (Message);
else
if (psincdec_dly = '1') then
if (ps_in = 511) then
ps_overflow_out <= '1';
elsif (((ps_in + 1) * period_orig / 256) > period_orig + FINE_SHIFT_RANGE) then
ps_overflow_out <= '1';
else
ps_in := ps_in + 1;
ps_delay <= (ps_in * period_div / 256);
ps_overflow_out <= '0';
end if;
ps_lock <= '1';
elsif (psincdec_dly = '0') then
if (ps_in = 1) then
ps_overflow_out <= '1';
elsif ((period_orig > FINE_SHIFT_RANGE) and (((ps_in - 1) * period_orig / 256) < period_orig - FINE_SHIFT_RANGE)) then
ps_overflow_out <= '1';
else
ps_in := ps_in - 1;
ps_delay <= (ps_in * period_div / 256);
ps_overflow_out <= '0';
end if;
ps_lock <= '1';
end if;
end if;
end if;
end if;
end if;
end if;
if (ps_lock_reg'event) then
ps_lock <= ps_lock_reg;
end if;
wait on lock_period, lock_period_pulse, psclk_dly, ps_lock_reg, rst_ipd;
end process determine_phase_shift;
determine_psdone_out : process
begin
if (rising_edge(ps_lock)) then
ps_lock_reg <= '1';
wait until (rising_edge(clkin_ps));
wait until (rising_edge(psclk_dly));
wait until (rising_edge(psclk_dly));
wait until (rising_edge(psclk_dly));
psdone_out <= '1';
wait until (rising_edge(psclk_dly));
psdone_out <= '0';
ps_lock_reg <= '0';
end if;
wait on ps_lock;
end process determine_psdone_out;
--
--determine clock period
--
determine_clock_period : process
variable clkin_edge_previous : time := 0 ps;
variable clkin_edge_current : time := 0 ps;
begin
if ((rising_edge(rst_ipd)) or (rst_ipd = '1')) then
clkin_period_real(0) <= 0 ps;
clkin_period_real(1) <= 0 ps;
clkin_period_real(2) <= 0 ps;
clkin_edge_previous := 0 ps;
clkin_edge_current := 0 ps;
elsif (rising_edge(clkin_div)) then
clkin_edge_previous := clkin_edge_current;
clkin_edge_current := NOW;
clkin_period_real(2) <= clkin_period_real(1);
clkin_period_real(1) <= clkin_period_real(0);
if (clkin_edge_previous /= 0 ps) then
clkin_period_real(0) <= clkin_edge_current - clkin_edge_previous;
end if;
end if;
if (no_stop'event) then
clkin_period_real(0) <= clkin_period_real0_temp;
end if;
wait on clkin_div, no_stop, rst_ipd;
end process determine_clock_period;
evaluate_clock_period : process
variable Message : line;
begin
if ((rising_edge(rst_ipd)) or (rst_ipd = '1')) then
lock_period <= '0';
clock_stopped <= '1';
clkin_period_real0_temp <= 0 ps;
else
if (falling_edge(clkin_div)) then
if (lock_period = '0') then
if ((clkin_period_real(0) /= 0 ps ) and (clkin_period_real(0) - cycle_jitter <= clkin_period_real(1)) and (clkin_period_real(1) <= clkin_period_real(0) + cycle_jitter) and (clkin_period_real(1) - cycle_jitter <= clkin_period_real(2)) and (clkin_period_real(2) <= clkin_period_real(1) + cycle_jitter)) then
lock_period <= '1';
period_orig <= (clkin_period_real(0) + clkin_period_real(1) + clkin_period_real(2)) / 3;
period <= clkin_period_real(0);
end if;
elsif (lock_period = '1') then
if (100000000 ns < clkin_period_real(0)) then
Write ( Message, string'(" Warning : CLKIN stopped toggling on instance "));
Write ( Message, Instancepath );
Write ( Message, string'(" exceeds "));
Write ( Message, string'(" 100 ms "));
Write ( Message, string'(" Current CLKIN Period = "));
Write ( Message, clkin_period_real(0));
assert false report Message.all severity warning;
DEALLOCATE (Message);
lock_period <= '0';
wait until (falling_edge(rst_reg(2)));
elsif ((period_orig * 2 < clkin_period_real(0)) and (clock_stopped = '0')) then
clkin_period_real0_temp <= clkin_period_real(1);
no_stop <= not no_stop;
clock_stopped <= '1';
elsif ((clkin_period_real(0) < period_orig - period_jitter) or (period_orig + period_jitter < clkin_period_real(0))) then
Write ( Message, string'(" Warning : Input Clock Period Jitter on instance "));
Write ( Message, Instancepath );
Write ( Message, string'(" exceeds "));
Write ( Message, period_jitter );
Write ( Message, string'(" Locked CLKIN Period = "));
Write ( Message, period_orig );
Write ( Message, string'(" Current CLKIN Period = "));
Write ( Message, clkin_period_real(0) );
assert false report Message.all severity warning;
DEALLOCATE (Message);
lock_period <= '0';
wait until (falling_edge(rst_reg(2)));
elsif ((clkin_period_real(0) < clkin_period_real(1) - cycle_jitter) or (clkin_period_real(1) + cycle_jitter < clkin_period_real(0))) then
Write ( Message, string'(" Warning : Input Clock Cycle Jitter on on instance "));
Write ( Message, Instancepath );
Write ( Message, string'(" exceeds "));
Write ( Message, cycle_jitter );
Write ( Message, string'(" Previous CLKIN Period = "));
Write ( Message, clkin_period_real(1) );
Write ( Message, string'(" Current CLKIN Period = "));
Write ( Message, clkin_period_real(0) );
assert false report Message.all severity warning;
DEALLOCATE (Message);
lock_period <= '0';
wait until (falling_edge(rst_reg(2)));
else
period <= clkin_period_real(0);
clock_stopped <= '0';
end if;
end if;
end if;
end if;
wait on clkin_div, rst_ipd;
end process evaluate_clock_period;
lock_period_dly <= transport lock_period after period/2;
-- determine_lock_period_pulse: process
-- begin
-- if ((lock_period = '1') and (lock_period_dly = '0')) then
-- lock_period_pulse <= '1';
-- else
-- lock_period_pulse <= '0';
-- end if;
-- wait on lock_period, lock_period_dly;
-- end process determine_lock_period_pulse;
lock_period_pulse <= '1' when ((lock_period = '1') and (lock_period_dly = '0')) else '0';
--
--determine clock delay
--
determine_clock_delay : process
variable delay_edge : time := 0 ps;
variable temp1 : integer := 0;
variable temp2 : integer := 0;
variable temp : integer := 0;
variable delay_edge_current : time := 0 ps;
begin
if ((rising_edge(rst_ipd)) or (rst_ipd = '1')) then
fb_delay <= 0 ps;
fb_delay_found <= '0';
else
if (rising_edge(lock_ps_dly)) then
if ((lock_period = '1') and (clkfb_type /= 0)) then
if (clkfb_type = 1) then
wait until ((rising_edge(clk0_sig)) or (rst_ipd'event));
delay_edge := NOW;
elsif (clkfb_type = 2) then
wait until ((rising_edge(clk2x_sig)) or (rst_ipd'event));
delay_edge := NOW;
end if;
wait until ((rising_edge(clkfb_ipd)) or (rst_ipd'event));
temp1 := ((NOW*1) - (delay_edge*1))/ (1 ps);
temp2 := (period_orig * 1)/ (1 ps);
temp := temp1 mod temp2;
fb_delay <= temp * 1 ps;
fb_delay_found <= '1';
end if;
end if;
end if;
wait on lock_ps_dly, rst_ipd;
end process determine_clock_delay;
--
-- determine feedback lock
--
GEN_CLKFB_WINDOW : process
begin
if ((rising_edge(rst_ipd)) or (rst_ipd = '1')) then
clkfb_window <= '0';
else
if (rising_edge(clkfb_chk)) then
wait for 0 ps;
clkfb_window <= '1';
wait for cycle_jitter;
clkfb_window <= '0';
end if;
end if;
wait on clkfb_chk, rst_ipd;
end process GEN_CLKFB_WINDOW;
GEN_CLKIN_WINDOW : process
begin
if ((rising_edge(rst_ipd)) or (rst_ipd = '1')) then
clkin_window <= '0';
else
if (rising_edge(clkin_fb)) then
wait for 0 ps;
clkin_window <= '1';
wait for cycle_jitter;
clkin_window <= '0';
end if;
end if;
wait on clkin_fb, rst_ipd;
end process GEN_CLKIN_WINDOW;
set_reset_lock_clkin : process
begin
if ((rising_edge(rst_ipd)) or (rst_ipd = '1')) then
lock_clkin <= '0';
else
if (rising_edge(clkin_fb)) then
wait for 1 ps;
if (((clkfb_window = '1') and (fb_delay_found = '1')) or ((clkin_lost_out = '1') and (lock_out(0) = '1'))) then
lock_clkin <= '1';
else
if (chk_enable = '1') then
lock_clkin <= '0';
end if;
end if;
end if;
end if;
wait on clkin_fb, rst_ipd;
end process set_reset_lock_clkin;
set_reset_lock_clkfb : process
begin
if ((rising_edge(rst_ipd)) or (rst_ipd = '1')) then
lock_clkfb <= '0';
else
if (rising_edge(clkfb_chk)) then
wait for 1 ps;
if (((clkin_window = '1') and (fb_delay_found = '1')) or ((clkin_lost_out = '1') and (lock_out(0) = '1')))then
lock_clkfb <= '1';
else
if (chk_enable = '1') then
lock_clkfb <= '0';
end if;
end if;
end if;
end if;
wait on clkfb_chk, rst_ipd;
end process set_reset_lock_clkfb;
assign_lock_delay : process
begin
if ((rising_edge(rst_ipd)) or (rst_ipd = '1')) then
lock_delay <= '0';
else
if (falling_edge(clkin_fb)) then
lock_delay <= lock_clkin or lock_clkfb;
end if;
end if;
wait on clkin_fb, rst_ipd;
end process;
--
--generate lock signal
--
generate_lock : process(clkin_ps, rst_ipd)
begin
if (rst_ipd='1') then
lock_out <= "00";
locked_out <= '0';
lock_out1_neg <= '0';
elsif (rising_edge(clkin_ps)) then
if (clkfb_type = 0) then
lock_out(0) <= lock_period;
else
lock_out(0) <= lock_period and lock_delay and lock_fb;
end if;
lock_out(1) <= lock_out(0);
locked_out <= lock_out(1);
elsif (falling_edge(clkin_ps)) then
lock_out1_neg <= lock_out(1);
end if;
end process generate_lock;
--
--generate the clk1x_out
--
gen_clk1x : process( clkin_ps, rst_ipd)
begin
if ((rising_edge(rst_ipd)) or (rst_ipd = '1')) then
clk0_out <= '0';
elsif (clkin_ps'event) then
if (clkin_ps = '1' ) then
if ((clk1x_type = 1) and (lock_out(0) = '1')) then
clk0_out <= '1', '0' after period/2;
else
clk0_out <= '1';
end if;
else
if ((clkin_ps = '0') and ((((clk1x_type = 1) and (lock_out(0) = '1')) = false) or ((lock_out(0) = '1') and (lock_out(1) = '0')))) then
clk0_out <= '0';
end if;
end if;
end if;
end process gen_clk1x;
--
--generate the clk2x_out
--
gen_clk2x : process
begin
if (rising_edge(rst_ipd) or (rst_ipd = '1')) then
clk2x_out <= '0';
else
if (rising_edge(clkin_ps)) then
clk2x_out <= '1';
wait for (period / 4);
clk2x_out <= '0';
wait for (period / 4);
clk2x_out <= '1';
wait for (period / 4);
clk2x_out <= '0';
end if;
end if;
wait on clkin_ps, rst_ipd;
end process gen_clk2x;
--
--generate the clkdv_out
--
gen_clkdv : process (clkin_ps, rst_ipd)
begin
if (rst_ipd='1') then
clkdv_out <= '0';
clkdv_cnt <= 0;
elsif ((rising_edge(clkin_ps)) or (falling_edge(clkin_ps))) then
if (lock_out1_neg = '1') then
if (clkdv_cnt >= divide_type -1) then
clkdv_cnt <= 0;
else
clkdv_cnt <= clkdv_cnt + 1;
end if;
if (clkdv_cnt < divide_type /2) then
clkdv_out <= '1';
else
if ( ((divide_type rem (2)) > 0) and (dll_mode_type = 0)) then
clkdv_out <= '0' after (period/4);
else
clkdv_out <= '0';
end if;
end if;
end if;
end if;
end process;
--
-- generate fx output signal
--
calculate_period_fx : process
begin
if (lock_period = '1') then
period_fx <= (period * denominator) / (numerator * 2);
remain_fx <= (((period/1 ps) * denominator) mod (numerator * 2)) * 1 ps;
end if;
wait on lock_period, period, denominator, numerator;
end process calculate_period_fx;
generate_clkfx : process
variable temp : integer;
begin
if (rst_ipd = '1') then
clkfx_out <= '0';
elsif (clkin_lost_out_ext = '1') then
wait until (rising_edge(rst_ipd));
clkfx_out <= '0';
wait until (falling_edge(rst_reg(2)));
elsif (rising_edge(clkin_ps)) then
if (lock_out(1) = '1') then
clkfx_out <= '1';
temp := numerator * 2 - 1 - 1;
for p in 0 to temp loop
wait for (period_fx);
clkfx_out <= not clkfx_out;
end loop;
if (period_fx > (period / 2)) then
wait for (period_fx - (period / 2));
end if;
end if;
if (clkin_lost_out_ext = '1') then
wait until (rising_edge(rst_ipd));
clkfx_out <= '0';
wait until (falling_edge(rst_reg(2)));
end if;
end if;
wait on clkin_lost_out_ext, clkin_ps, rst_ipd, rst_reg(2);
end process generate_clkfx;
--
--generate all output signal
--
schedule_p1_outputs : process
begin
if (CLK0_out'event) then
if (clkfb_type /= 0) then
CLK0 <= transport CLK0_out after clkout_delay;
clk0_sig <= transport CLK0_out after clkout_delay;
end if;
if ((dll_mode_type = 0) and (clkfb_type /= 0)) then
CLK90 <= transport clk0_out after (clkout_delay + period / 4);
end if;
end if;
if (CLK0_out'event or rst_ipd'event)then
if (rst_ipd = '1') then
CLK180 <= '0';
CLK270 <= '0';
elsif (CLK0_out'event) then
if (clkfb_type /= 0) then
CLK180 <= transport (not clk0_out) after clkout_delay;
end if;
if ((dll_mode_type = 0) and (clkfb_type /= 0)) then
CLK270 <= transport (not clk0_out) after (clkout_delay + period/4);
end if;
end if;
end if;
if (clk2x_out'event) then
if ((dll_mode_type = 0) and (clkfb_type /= 0)) then
CLK2X <= transport clk2x_out after clkout_delay;
clk2x_sig <= transport clk2x_out after clkout_delay;
end if;
end if;
if (CLK2X_out'event or rst_ipd'event) then
if (rst_ipd = '1') then
CLK2X180 <= '0';
elsif (CLK2X_out'event) then
if ((dll_mode_type = 0) and (clkfb_type /= 0)) then
CLK2X180 <= transport (not CLK2X_out) after clkout_delay;
end if;
end if;
end if;
if (clkdv_out'event) then
if (clkfb_type /= 0) then
CLKDV <= transport clkdv_out after clkout_delay;
end if;
end if;
if (clkfx_out'event or rst_ipd'event) then
if (rst_ipd = '1') then
CLKFX <= '0';
elsif (clkfx_out'event) then
CLKFX <= transport clkfx_out after clkout_delay;
end if;
end if;
if (clkfx_out'event or (rising_edge(rst_ipd)) or first_time_locked'event or locked_out'event) then
if ((rst_ipd = '1') or (not first_time_locked)) then
CLKFX180 <= '0';
else
CLKFX180 <= transport (not clkfx_out) after clkout_delay;
end if;
end if;
if (status_out(0)'event) then
status(0) <= status_out(0);
end if;
if (status_out(1)'event) then
status(1) <= status_out(1);
end if;
if (status_out(2)'event) then
status(2) <= status_out(2);
end if;
wait on clk0_out, clk2x_out, clkdv_out, clkfx_out, first_time_locked, locked_out, rst_ipd, status_out;
end process;
assign_status_out : process
begin
if (rst_ipd = '1') then
status_out(0) <= '0';
status_out(1) <= '0';
status_out(2) <= '0';
elsif (ps_overflow_out_ext'event) then
status_out(0) <= ps_overflow_out_ext;
elsif (clkin_lost_out_ext'event) then
status_out(1) <= clkin_lost_out_ext;
elsif (clkfx_lost_out_ext'event) then
status_out(2) <= clkfx_lost_out_ext;
end if;
wait on clkin_lost_out_ext, clkfx_lost_out_ext, ps_overflow_out_ext, rst_ipd;
end process assign_status_out;
locked_out_out <= 'X' when rst_flag = '1' else locked_out;
-- LOCKED <= locked_out_out;
-- PSDONE <= psdone_out;
-- LOCKED_sig <= locked_out_out;
schedule_outputs : process
variable PSDONE_GlitchData : VitalGlitchDataType;
variable LOCKED_GlitchData : VitalGlitchDataType;
begin
VitalPathDelay01 (
OutSignal => PSDONE,
GlitchData => PSDONE_GlitchData,
OutSignalName => "PSDONE",
OutTemp => psdone_out,
Paths => (0 => (psdone_out'last_event, tpd_PSCLK_PSDONE, true)),
Mode => OnEvent,
Xon => Xon,
MsgOn => MsgOn,
MsgSeverity => warning
);
LOCKED_sig <= locked_out_out after tpd_CLKIN_LOCKED(tr01);
VitalPathDelay01 (
OutSignal => LOCKED,
GlitchData => LOCKED_GlitchData,
OutSignalName => "LOCKED",
OutTemp => locked_out_out,
Paths => (0 => (locked_out_out'last_event, tpd_CLKIN_LOCKED, true)),
Mode => OnEvent,
Xon => Xon,
MsgOn => MsgOn,
MsgSeverity => warning
);
wait on locked_out_out, psdone_out;
end process schedule_outputs;
VitalTimingCheck : process
variable Tviol_PSINCDEC_PSCLK_posedge : std_ulogic := '0';
variable Tmkr_PSINCDEC_PSCLK_posedge : VitalTimingDataType := VitalTimingDataInit;
variable Tviol_PSEN_PSCLK_posedge : std_ulogic := '0';
variable Tmkr_PSEN_PSCLK_posedge : VitalTimingDataType := VitalTimingDataInit;
variable Pviol_CLKIN : std_ulogic := '0';
variable PInfo_CLKIN : VitalPeriodDataType := VitalPeriodDataInit;
variable Pviol_PSCLK : std_ulogic := '0';
variable PInfo_PSCLK : VitalPeriodDataType := VitalPeriodDataInit;
variable Pviol_RST : std_ulogic := '0';
variable PInfo_RST : VitalPeriodDataType := VitalPeriodDataInit;
begin
if (TimingChecksOn) then
VitalSetupHoldCheck (
Violation => Tviol_PSINCDEC_PSCLK_posedge,
TimingData => Tmkr_PSINCDEC_PSCLK_posedge,
TestSignal => PSINCDEC_dly,
TestSignalName => "PSINCDEC",
TestDelay => tisd_PSINCDEC_PSCLK,
RefSignal => PSCLK_dly,
RefSignalName => "PSCLK",
RefDelay => ticd_PSCLK,
SetupHigh => tsetup_PSINCDEC_PSCLK_posedge_posedge,
SetupLow => tsetup_PSINCDEC_PSCLK_negedge_posedge,
HoldLow => thold_PSINCDEC_PSCLK_posedge_posedge,
HoldHigh => thold_PSINCDEC_PSCLK_negedge_posedge,
CheckEnabled => (TO_X01(((NOT RST_ipd)) AND (PSEN_dly)) /= '0'),
RefTransition => 'R',
HeaderMsg => InstancePath & "/X_DCM",
Xon => Xon,
MsgOn => MsgOn,
MsgSeverity => warning);
VitalSetupHoldCheck (
Violation => Tviol_PSEN_PSCLK_posedge,
TimingData => Tmkr_PSEN_PSCLK_posedge,
TestSignal => PSEN_dly,
TestSignalName => "PSEN",
TestDelay => tisd_PSEN_PSCLK,
RefSignal => PSCLK_dly,
RefSignalName => "PSCLK",
RefDelay => ticd_PSCLK,
SetupHigh => tsetup_PSEN_PSCLK_posedge_posedge,
SetupLow => tsetup_PSEN_PSCLK_negedge_posedge,
HoldLow => thold_PSEN_PSCLK_posedge_posedge,
HoldHigh => thold_PSEN_PSCLK_negedge_posedge,
CheckEnabled => TO_X01(NOT RST_ipd) /= '0',
RefTransition => 'R',
HeaderMsg => InstancePath & "/X_DCM",
Xon => Xon,
MsgOn => MsgOn,
MsgSeverity => warning);
VitalPeriodPulseCheck (
Violation => Pviol_PSCLK,
PeriodData => PInfo_PSCLK,
TestSignal => PSCLK_dly,
TestSignalName => "PSCLK",
TestDelay => 0 ns,
Period => tperiod_PSCLK_POSEDGE,
PulseWidthHigh => tpw_PSCLK_posedge,
PulseWidthLow => tpw_PSCLK_negedge,
CheckEnabled => true,
HeaderMsg => InstancePath &"/X_DCM",
Xon => Xon,
MsgOn => MsgOn,
MsgSeverity => warning);
VitalPeriodPulseCheck (
Violation => Pviol_CLKIN,
PeriodData => PInfo_CLKIN,
TestSignal => CLKIN_ipd,
TestSignalName => "CLKIN",
TestDelay => 0 ns,
Period => tperiod_CLKIN_POSEDGE,
PulseWidthHigh => tpw_CLKIN_posedge,
PulseWidthLow => tpw_CLKIN_negedge,
CheckEnabled => TO_X01(NOT RST_ipd) /= '0',
HeaderMsg => InstancePath &"/X_DCM",
Xon => Xon,
MsgOn => MsgOn,
MsgSeverity => warning);
VitalPeriodPulseCheck (
Violation => Pviol_RST,
PeriodData => PInfo_RST,
TestSignal => RST_ipd,
TestSignalName => "RST",
TestDelay => 0 ns,
Period => 0 ns,
PulseWidthHigh => tpw_RST_posedge,
PulseWidthLow => 0 ns,
CheckEnabled => true,
HeaderMsg => InstancePath &"/X_DCM",
Xon => Xon,
MsgOn => MsgOn,
MsgSeverity => warning);
end if;
wait on CLKIN_ipd, PSCLK_dly, PSEN_dly, PSINCDEC_dly, RST_ipd;
end process VITALTimingCheck;
end X_DCM_V;
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor : Xilinx
-- \ \ \/ Version : 9.1i
-- \ \ Description : Xilinx Timing Simulation Library Component
-- / / Digital Clock Manager
-- /___/ /\ Filename : X_DCM_SP.vhd
-- \ \ / \ Timestamp : Fri Jun 18 10:57:08 PDT 2004
-- \___\/\___\
--
-- Revision:
-- 03/06/06 - Initial version.
-- 05/09/06 - Add clkin_ps_mkup and clkin_ps_mkup_win for phase shifting (CR 229789).
-- 06/14/06 - Add period_int2 and period_int3 for multiple cycle phase shifting (CR 233283).
-- 07/21/06 - Change range of variable phase shifting to +/- integer of 20*(Period-3ns).
-- Give warning not support initial phase shifting for variable phase shifting.
-- (CR 235216).
-- 09/22/06 - Add lock_period and lock_fb to clkfb_div block (CR 418722).
-- 12/19/06 - Add clkfb_div_en for clkfb2x divider (CR431210).
-- 04/06/07 - Enable the clock out in clock low time after reset in model
-- clock_divide_by_2 (CR 437471).
-- End Revision
----- x_dcm_sp_clock_divide_by_2 -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity x_dcm_sp_clock_divide_by_2 is
port(
clock_out : out std_ulogic := '0';
clock : in std_ulogic;
clock_type : in integer;
rst : in std_ulogic
);
end x_dcm_sp_clock_divide_by_2;
architecture x_dcm_sp_clock_divide_by_2_V of x_dcm_sp_clock_divide_by_2 is
signal clock_div2 : std_ulogic := '0';
signal rst_reg : std_logic_vector(2 downto 0);
signal clk_src : std_ulogic;
begin
CLKIN_DIVIDER : process
begin
if (rising_edge(clock)) then
clock_div2 <= not clock_div2;
end if;
wait on clock;
end process CLKIN_DIVIDER;
gen_reset : process
begin
if (rising_edge(clock)) then
rst_reg(0) <= rst;
rst_reg(1) <= rst_reg(0) and rst;
rst_reg(2) <= rst_reg(1) and rst_reg(0) and rst;
end if;
wait on clock;
end process gen_reset;
clk_src <= clock_div2 when (clock_type = 1) else clock;
assign_clkout : process
begin
if (rst = '0') then
clock_out <= clk_src;
elsif (rst = '1') then
clock_out <= '0';
wait until falling_edge(rst_reg(2));
if (clk_src = '1') then
wait until falling_edge(clk_src);
end if;
end if;
wait on clk_src, rst, rst_reg;
end process assign_clkout;
end x_dcm_sp_clock_divide_by_2_V;
----- x_dcm_sp_maximum_period_check -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library STD;
use STD.TEXTIO.all;
entity x_dcm_sp_maximum_period_check is
generic (
InstancePath : string := "*";
clock_name : string := "";
maximum_period : time);
port(
clock : in std_ulogic;
rst : in std_ulogic
);
end x_dcm_sp_maximum_period_check;
architecture x_dcm_sp_maximum_period_check_V of x_dcm_sp_maximum_period_check is
begin
MAX_PERIOD_CHECKER : process
variable clock_edge_previous : time := 0 ps;
variable clock_edge_current : time := 0 ps;
variable clock_period : time := 0 ps;
variable Message : line;
begin
if (rising_edge(clock)) then
clock_edge_previous := clock_edge_current;
clock_edge_current := NOW;
if (clock_edge_previous > 0 ps) then
clock_period := clock_edge_current - clock_edge_previous;
end if;
if (clock_period > maximum_period and rst = '0') then
Write ( Message, string'(" Warning : Input Clock Period of "));
Write ( Message, clock_period );
Write ( Message, string'(" on the ") );
Write ( Message, clock_name );
Write ( Message, string'(" port ") );
Write ( Message, string'(" of X_DCM_SP instance ") );
Write ( Message, string'(" exceeds allowed value of ") );
Write ( Message, maximum_period );
Write ( Message, string'(" at simulation time ") );
Write ( Message, clock_edge_current );
Write ( Message, '.' & LF );
assert false report Message.all severity warning;
DEALLOCATE (Message);
end if;
end if;
wait on clock;
end process MAX_PERIOD_CHECKER;
end x_dcm_sp_maximum_period_check_V;
----- x_dcm_sp_clock_lost -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity x_dcm_sp_clock_lost is
port(
lost : out std_ulogic := '0';
clock : in std_ulogic;
enable : in boolean := false;
rst : in std_ulogic
);
end x_dcm_sp_clock_lost;
architecture x_dcm_sp_clock_lost_V of x_dcm_sp_clock_lost is
signal period : time := 0 ps;
signal lost_r : std_ulogic := '0';
signal lost_f : std_ulogic := '0';
signal lost_sig : std_ulogic := '0';
signal clock_negedge, clock_posedge : std_ulogic;
signal clock_low, clock_high : std_ulogic := '0';
signal clock_second_pos, clock_second_neg : std_ulogic := '0';
begin
determine_period : process
variable clock_edge_previous : time := 0 ps;
variable clock_edge_current : time := 0 ps;
begin
if (rst = '1') then
period <= 0 ps;
elsif (rising_edge(clock)) then
clock_edge_previous := clock_edge_current;
clock_edge_current := NOW;
if (period /= 0 ps and ((clock_edge_current - clock_edge_previous) <= (1.5 * period))) then
period <= NOW - clock_edge_previous;
elsif (period /= 0 ps and ((NOW - clock_edge_previous) > (1.5 * period))) then
period <= 0 ps;
elsif ((period = 0 ps) and (clock_edge_previous /= 0 ps) and (clock_second_pos = '1')) then
period <= NOW - clock_edge_previous;
end if;
end if;
wait on clock, rst;
end process determine_period;
CLOCK_LOST_CHECKER : process
begin
if (rst = '1') then
clock_low <= '0';
clock_high <= '0';
clock_posedge <= '0';
clock_negedge <= '0';
else
if (rising_edge(clock)) then
clock_low <= '0';
clock_high <= '1';
clock_posedge <= '0';
clock_negedge <= '1';
end if;
if (falling_edge(clock)) then
clock_high <= '0';
clock_low <= '1';
clock_posedge <= '1';
clock_negedge <= '0';
end if;
end if;
wait on clock, rst;
end process CLOCK_LOST_CHECKER;
CLOCK_SECOND_P : process
begin
if (rst = '1') then
clock_second_pos <= '0';
clock_second_neg <= '0';
else
if (rising_edge(clock)) then
clock_second_pos <= '1';
end if;
if (falling_edge(clock)) then
clock_second_neg <= '1';
end if;
end if;
wait on clock, rst;
end process CLOCK_SECOND_P;
SET_RESET_LOST_R : process
begin
if (rst = '1') then
lost_r <= '0';
else
if ((enable = true) and (clock_second_pos = '1'))then
if (rising_edge(clock)) then
wait for 1 ps;
if (period /= 0 ps) then
lost_r <= '0';
end if;
wait for (period * (9.1/10.0));
if ((clock_low /= '1') and (clock_posedge /= '1') and (rst = '0')) then
lost_r <= '1';
end if;
end if;
end if;
end if;
wait on clock, rst;
end process SET_RESET_LOST_R;
SET_RESET_LOST_F : process
begin
if (rst = '1') then
lost_f <= '0';
else
if ((enable = true) and (clock_second_neg = '1'))then
if (falling_edge(clock)) then
if (period /= 0 ps) then
lost_f <= '0';
end if;
wait for (period * (9.1/10.0));
if ((clock_high /= '1') and (clock_negedge /= '1') and (rst = '0')) then
lost_f <= '1';
end if;
end if;
end if;
end if;
wait on clock, rst;
end process SET_RESET_LOST_F;
assign_lost : process
begin
if (enable = true) then
if (lost_r'event) then
lost <= lost_r;
end if;
if (lost_f'event) then
lost <= lost_f;
end if;
end if;
wait on lost_r, lost_f;
end process assign_lost;
end x_dcm_sp_clock_lost_V;
----- CELL X_DCM_SP -----
library IEEE;
use IEEE.std_logic_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
library STD;
use STD.TEXTIO.all;
library unisim;
use unisim.vpkg.all;
entity X_DCM_SP is
generic (
TimingChecksOn : boolean := true;
InstancePath : string := "*";
Xon : boolean := true;
MsgOn : boolean := false;
LOC : string := "UNPLACED";
thold_PSEN_PSCLK_negedge_posedge : VitalDelayType := 0.000 ns;
thold_PSEN_PSCLK_posedge_posedge : VitalDelayType := 0.000 ns;
thold_PSINCDEC_PSCLK_negedge_posedge : VitalDelayType := 0.000 ns;
thold_PSINCDEC_PSCLK_posedge_posedge : VitalDelayType := 0.000 ns;
ticd_PSCLK : VitalDelayType := 0.000 ns;
tipd_CLKFB : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_CLKIN : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_DSSEN : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_PSCLK : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_PSEN : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_PSINCDEC : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_RST : VitalDelayType01 := (0.000 ns, 0.000 ns);
tisd_PSINCDEC_PSCLK : VitalDelayType := 0.000 ns;
tisd_PSEN_PSCLK : VitalDelayType := 0.000 ns;
tpd_CLKIN_LOCKED : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_PSCLK_PSDONE : VitalDelayType01 := (0.100 ns, 0.100 ns);
tperiod_CLKIN_POSEDGE : VitalDelayType := 0.000 ns;
tperiod_PSCLK_POSEDGE : VitalDelayType := 0.000 ns;
tpw_CLKIN_negedge : VitalDelayType := 0.000 ns;
tpw_CLKIN_posedge : VitalDelayType := 0.000 ns;
tpw_PSCLK_negedge : VitalDelayType := 0.000 ns;
tpw_PSCLK_posedge : VitalDelayType := 0.000 ns;
tpw_RST_posedge : VitalDelayType := 0.000 ns;
tsetup_PSEN_PSCLK_negedge_posedge : VitalDelayType := 0.000 ns;
tsetup_PSEN_PSCLK_posedge_posedge : VitalDelayType := 0.000 ns;
tsetup_PSINCDEC_PSCLK_negedge_posedge : VitalDelayType := 0.000 ns;
tsetup_PSINCDEC_PSCLK_posedge_posedge : VitalDelayType := 0.000 ns;
CLKDV_DIVIDE : real := 2.0;
CLKFX_DIVIDE : integer := 1;
CLKFX_MULTIPLY : integer := 4;
CLKIN_DIVIDE_BY_2 : boolean := false;
CLKIN_PERIOD : real := 10.0; --non-simulatable
CLKOUT_PHASE_SHIFT : string := "NONE";
CLK_FEEDBACK : string := "1X";
DESKEW_ADJUST : string := "SYSTEM_SYNCHRONOUS"; --non-simulatable
DFS_FREQUENCY_MODE : string := "LOW";
DLL_FREQUENCY_MODE : string := "LOW";
DSS_MODE : string := "NONE"; --non-simulatable
DUTY_CYCLE_CORRECTION : boolean := true;
FACTORY_JF : bit_vector := X"C080"; --non-simulatable
MAXPERCLKIN : time := 1000000 ps; --non-modifiable simulation parameter
MAXPERPSCLK : time := 100000000 ps; --non-modifiable simulation parameter
PHASE_SHIFT : integer := 0;
SIM_CLKIN_CYCLE_JITTER : time := 300 ps; --non-modifiable simulation parameter
SIM_CLKIN_PERIOD_JITTER : time := 1000 ps; --non-modifiable simulation parameter
STARTUP_WAIT : boolean := false --non-simulatable
);
port (
CLK0 : out std_ulogic := '0';
CLK180 : out std_ulogic := '0';
CLK270 : out std_ulogic := '0';
CLK2X : out std_ulogic := '0';
CLK2X180 : out std_ulogic := '0';
CLK90 : out std_ulogic := '0';
CLKDV : out std_ulogic := '0';
CLKFX : out std_ulogic := '0';
CLKFX180 : out std_ulogic := '0';
LOCKED : out std_ulogic := '0';
PSDONE : out std_ulogic := '0';
STATUS : out std_logic_vector(7 downto 0) := "00000000";
CLKFB : in std_ulogic := '0';
CLKIN : in std_ulogic := '0';
DSSEN : in std_ulogic := '0';
PSCLK : in std_ulogic := '0';
PSEN : in std_ulogic := '0';
PSINCDEC : in std_ulogic := '0';
RST : in std_ulogic := '0'
);
attribute VITAL_LEVEL0 of X_DCM_SP : entity is true;
end X_DCM_SP;
architecture X_DCM_SP_V of X_DCM_SP is
component x_dcm_sp_clock_divide_by_2
port(
clock_out : out std_ulogic;
clock : in std_ulogic;
clock_type : in integer;
rst : in std_ulogic
);
end component;
component x_dcm_sp_maximum_period_check
generic (
InstancePath : string := "*";
clock_name : string := "";
maximum_period : time);
port(
clock : in std_ulogic;
rst : in std_ulogic
);
end component;
component x_dcm_sp_clock_lost
port(
lost : out std_ulogic;
clock : in std_ulogic;
enable : in boolean := false;
rst : in std_ulogic
);
end component;
signal CLKFB_ipd, CLKIN_ipd, DSSEN_ipd : std_ulogic;
signal PSCLK_ipd, PSEN_ipd, PSINCDEC_ipd, RST_ipd : std_ulogic;
signal PSCLK_dly ,PSEN_dly, PSINCDEC_dly : std_ulogic := '0';
signal clk0_out : std_ulogic;
signal clk2x_out, clkdv_out : std_ulogic := '0';
signal clkfx_out, locked_out, psdone_out, ps_overflow_out, ps_lock : std_ulogic := '0';
signal locked_out_out : std_ulogic := '0';
signal LOCKED_sig : std_ulogic := '0';
signal clkdv_cnt : integer := 0;
signal clkfb_type : integer;
signal divide_type : integer;
signal clkin_type : integer;
signal ps_type : integer;
signal deskew_adjust_mode : integer;
signal dfs_mode_type : integer;
signal dll_mode_type : integer;
signal clk1x_type : integer;
signal lock_period, lock_delay, lock_clkin, lock_clkfb : std_ulogic := '0';
signal lock_out : std_logic_vector(1 downto 0) := "00";
signal lock_out1_neg : std_ulogic := '0';
signal lock_fb : std_ulogic := '0';
signal lock_fb_dly : std_ulogic := '0';
signal lock_fb_dly_tmp : std_ulogic := '0';
signal fb_delay_found : std_ulogic := '0';
signal clkin_div : std_ulogic;
signal clkin_ps : std_ulogic;
signal clkin_ps_tmp : std_ulogic;
signal clkin_ps_mkup : std_ulogic := '0';
signal clkin_ps_mkup_win : std_ulogic := '0';
signal clkin_fb : std_ulogic;
signal ps_delay : time := 0 ps;
signal ps_delay_init : time := 0 ps;
signal ps_delay_md : time := 0 ps;
signal ps_delay_all : time := 0 ps;
signal ps_max_range : integer := 0;
signal ps_acc : integer := 0;
signal period_int : integer := 0;
signal clkin_period_real : VitalDelayArrayType(2 downto 0) := (0.000 ns, 0.000 ns, 0.000 ns);
signal period : time := 0 ps;
signal period_div : time := 0 ps;
signal period_orig : time := 0 ps;
signal period_ps : time := 0 ps;
signal clkout_delay : time := 0 ps;
signal fb_delay : time := 0 ps;
signal period_fx, remain_fx : time := 0 ps;
signal period_dv_high, period_dv_low : time := 0 ps;
signal cycle_jitter, period_jitter : time := 0 ps;
signal clkin_window, clkfb_window : std_ulogic := '0';
signal rst_reg : std_logic_vector(2 downto 0) := "000";
signal rst_flag : std_ulogic := '0';
signal numerator, denominator, gcd : integer := 1;
signal clkin_lost_out : std_ulogic := '0';
signal clkfx_lost_out : std_ulogic := '0';
signal remain_fx_temp : integer := 0;
signal clkin_period_real0_temp : time := 0 ps;
signal ps_lock_reg : std_ulogic := '0';
signal clk0_sig : std_ulogic := '0';
signal clk2x_sig : std_ulogic := '0';
signal no_stop : boolean := false;
signal clkfx180_en : std_ulogic := '0';
signal status_out : std_logic_vector(7 downto 0) := "00000000";
signal first_time_locked : boolean := false;
signal en_status : boolean := false;
signal ps_overflow_out_ext : std_ulogic := '0';
signal clkin_lost_out_ext : std_ulogic := '0';
signal clkfx_lost_out_ext : std_ulogic := '0';
signal clkfb_div : std_ulogic := '0';
signal clkfb_div_en : std_ulogic := '0';
signal clkfb_chk : std_ulogic := '0';
signal lock_period_dly : std_ulogic := '0';
signal lock_period_dly1 : std_ulogic := '0';
signal lock_period_pulse : std_ulogic := '0';
signal clock_stopped : std_ulogic := '1';
signal clkin_chkin, clkfb_chkin : std_ulogic := '0';
signal chk_enable, chk_rst : std_ulogic := '0';
signal lock_ps : std_ulogic := '0';
signal lock_ps_dly : std_ulogic := '0';
constant PS_STEP : time := 25 ps;
begin
INITPROC : process
begin
detect_resolution
(model_name => "X_DCM_SP"
);
if (CLKDV_DIVIDE = 1.5) then
divide_type <= 3;
elsif (CLKDV_DIVIDE = 2.0) then
divide_type <= 4;
elsif (CLKDV_DIVIDE = 2.5) then
divide_type <= 5;
elsif (CLKDV_DIVIDE = 3.0) then
divide_type <= 6;
elsif (CLKDV_DIVIDE = 3.5) then
divide_type <= 7;
elsif (CLKDV_DIVIDE = 4.0) then
divide_type <= 8;
elsif (CLKDV_DIVIDE = 4.5) then
divide_type <= 9;
elsif (CLKDV_DIVIDE = 5.0) then
divide_type <= 10;
elsif (CLKDV_DIVIDE = 5.5) then
divide_type <= 11;
elsif (CLKDV_DIVIDE = 6.0) then
divide_type <= 12;
elsif (CLKDV_DIVIDE = 6.5) then
divide_type <= 13;
elsif (CLKDV_DIVIDE = 7.0) then
divide_type <= 14;
elsif (CLKDV_DIVIDE = 7.5) then
divide_type <= 15;
elsif (CLKDV_DIVIDE = 8.0) then
divide_type <= 16;
elsif (CLKDV_DIVIDE = 9.0) then
divide_type <= 18;
elsif (CLKDV_DIVIDE = 10.0) then
divide_type <= 20;
elsif (CLKDV_DIVIDE = 11.0) then
divide_type <= 22;
elsif (CLKDV_DIVIDE = 12.0) then
divide_type <= 24;
elsif (CLKDV_DIVIDE = 13.0) then
divide_type <= 26;
elsif (CLKDV_DIVIDE = 14.0) then
divide_type <= 28;
elsif (CLKDV_DIVIDE = 15.0) then
divide_type <= 30;
elsif (CLKDV_DIVIDE = 16.0) then
divide_type <= 32;
else
GenericValueCheckMessage
(HeaderMsg => "Attribute Syntax Error",
GenericName => "CLKDV_DIVIDE",
EntityName => "X_DCM_SP",
InstanceName => InstancePath,
GenericValue => CLKDV_DIVIDE,
Unit => "",
ExpectedValueMsg => "Legal Values for this attribute are 1.5, 2.0, 2.5, 3.0, 3.5, 4.0, 4.5, 5.0, 5.5, 6.0, 6.5, 7.0, 7.5, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, or 16.0",
ExpectedGenericValue => "",
TailMsg => "",
MsgSeverity => error
);
end if;
if ((CLKFX_DIVIDE <= 0) or (32 < CLKFX_DIVIDE)) then
GenericValueCheckMessage
(HeaderMsg => "Attribute Syntax Error",
GenericName => "CLKFX_DIVIDE",
EntityName => "X_DCM_SP",
InstanceName => InstancePath,
GenericValue => CLKFX_DIVIDE,
Unit => "",
ExpectedValueMsg => "Legal Values for this attribute are 1....32",
ExpectedGenericValue => "",
TailMsg => "",
MsgSeverity => error
);
end if;
if ((CLKFX_MULTIPLY <= 1) or (32 < CLKFX_MULTIPLY)) then
GenericValueCheckMessage
(HeaderMsg => "Attribute Syntax Error",
GenericName => "CLKFX_MULTIPLY",
EntityName => "X_DCM_SP",
InstanceName => InstancePath,
GenericValue => CLKFX_MULTIPLY,
Unit => "",
ExpectedValueMsg => "Legal Values for this attribute are 2....32",
ExpectedGenericValue => "",
TailMsg => "",
MsgSeverity => error
);
end if;
case CLKIN_DIVIDE_BY_2 is
when false => clkin_type <= 0;
when true => clkin_type <= 1;
when others =>
GenericValueCheckMessage
(HeaderMsg => "Attribute Syntax Error",
GenericName => "CLKIN_DIVIDE_BY_2",
EntityName => "X_DCM_SP",
InstanceName => InstancePath,
GenericValue => CLKIN_DIVIDE_BY_2,
Unit => "",
ExpectedValueMsg => "Legal Values for this attribute are TRUE or FALSE",
ExpectedGenericValue => "",
TailMsg => "",
MsgSeverity => error
);
end case;
if ((CLKOUT_PHASE_SHIFT = "none") or (CLKOUT_PHASE_SHIFT = "NONE")) then
ps_type <= 0;
elsif ((CLKOUT_PHASE_SHIFT = "fixed") or (CLKOUT_PHASE_SHIFT = "FIXED")) then
ps_type <= 1;
elsif ((CLKOUT_PHASE_SHIFT = "variable") or (CLKOUT_PHASE_SHIFT = "VARIABLE")) then
ps_type <= 2;
if (PHASE_SHIFT /= 0) then
GenericValueCheckMessage
(HeaderMsg => "Attribute Syntax Warning",
GenericName => "PHASE_SHIFT",
EntityName => "X_DCM_SP",
InstanceName => InstancePath,
GenericValue => PHASE_SHIFT,
Unit => "",
ExpectedValueMsg => "The maximum variable phase shift range is only valid when initial phase shift PHASE_SHIFT is zero",
ExpectedGenericValue => "",
TailMsg => "",
MsgSeverity => warning
);
end if;
else
GenericValueCheckMessage
(HeaderMsg => "Attribute Syntax Error",
GenericName => "CLKOUT_PHASE_SHIFT",
EntityName => "X_DCM_SP",
InstanceName => InstancePath,
GenericValue => CLKOUT_PHASE_SHIFT,
Unit => "",
ExpectedValueMsg => "Legal Values for this attribute are NONE, FIXED or VARIABLE",
ExpectedGenericValue => "",
TailMsg => "",
MsgSeverity => error
);
end if;
if ((CLK_FEEDBACK = "none") or (CLK_FEEDBACK = "NONE")) then
clkfb_type <= 0;
elsif ((CLK_FEEDBACK = "1x") or (CLK_FEEDBACK = "1X")) then
clkfb_type <= 1;
elsif ((CLK_FEEDBACK = "2x") or (CLK_FEEDBACK = "2X")) then
clkfb_type <= 2;
else
GenericValueCheckMessage
(HeaderMsg => "Attribute Syntax Error",
GenericName => "CLK_FEEDBACK",
EntityName => "X_DCM_SP",
InstanceName => InstancePath,
GenericValue => CLK_FEEDBACK,
Unit => "",
ExpectedValueMsg => "Legal Values for this attribute are NONE, 1X or 2X",
ExpectedGenericValue => "",
TailMsg => "",
MsgSeverity => error
);
end if;
if ((DESKEW_ADJUST = "source_synchronous") or (DESKEW_ADJUST = "SOURCE_SYNCHRONOUS")) then
DESKEW_ADJUST_mode <= 8;
elsif ((DESKEW_ADJUST = "system_synchronous") or (DESKEW_ADJUST = "SYSTEM_SYNCHRONOUS")) then
DESKEW_ADJUST_mode <= 11;
elsif ((DESKEW_ADJUST = "0")) then
DESKEW_ADJUST_mode <= 0;
elsif ((DESKEW_ADJUST = "1")) then
DESKEW_ADJUST_mode <= 1;
elsif ((DESKEW_ADJUST = "2")) then
DESKEW_ADJUST_mode <= 2;
elsif ((DESKEW_ADJUST = "3")) then
DESKEW_ADJUST_mode <= 3;
elsif ((DESKEW_ADJUST = "4")) then
DESKEW_ADJUST_mode <= 4;
elsif ((DESKEW_ADJUST = "5")) then
DESKEW_ADJUST_mode <= 5;
elsif ((DESKEW_ADJUST = "6")) then
DESKEW_ADJUST_mode <= 6;
elsif ((DESKEW_ADJUST = "7")) then
DESKEW_ADJUST_mode <= 7;
elsif ((DESKEW_ADJUST = "8")) then
DESKEW_ADJUST_mode <= 8;
elsif ((DESKEW_ADJUST = "9")) then
DESKEW_ADJUST_mode <= 9;
elsif ((DESKEW_ADJUST = "10")) then
DESKEW_ADJUST_mode <= 10;
elsif ((DESKEW_ADJUST = "11")) then
DESKEW_ADJUST_mode <= 11;
elsif ((DESKEW_ADJUST = "12")) then
DESKEW_ADJUST_mode <= 12;
elsif ((DESKEW_ADJUST = "13")) then
DESKEW_ADJUST_mode <= 13;
elsif ((DESKEW_ADJUST = "14")) then
DESKEW_ADJUST_mode <= 14;
elsif ((DESKEW_ADJUST = "15")) then
DESKEW_ADJUST_mode <= 15;
else
GenericValueCheckMessage
(HeaderMsg => "Attribute Syntax Error",
GenericName => "DESKEW_ADJUST_MODE",
EntityName => "X_DCM_SP",
InstanceName => InstancePath,
GenericValue => DESKEW_ADJUST_MODE,
Unit => "",
ExpectedValueMsg => "Legal Values for this attribute are SOURCE_SYNCHRONOUS, SYSTEM_SYNCHRONOUS or 1....15",
ExpectedGenericValue => "",
TailMsg => "",
MsgSeverity => error
);
end if;
if ((DFS_FREQUENCY_MODE = "high") or (DFS_FREQUENCY_MODE = "HIGH")) then
dfs_mode_type <= 1;
elsif ((DFS_FREQUENCY_MODE = "low") or (DFS_FREQUENCY_MODE = "LOW")) then
dfs_mode_type <= 0;
else
GenericValueCheckMessage
(HeaderMsg => "Attribute Syntax Error",
GenericName => "DFS_FREQUENCY_MODE",
EntityName => "X_DCM_SP",
InstanceName => InstancePath,
GenericValue => DFS_FREQUENCY_MODE,
Unit => "",
ExpectedValueMsg => "Legal Values for this attribute are HIGH or LOW",
ExpectedGenericValue => "",
TailMsg => "",
MsgSeverity => error
);
end if;
if ((DLL_FREQUENCY_MODE = "high") or (DLL_FREQUENCY_MODE = "HIGH")) then
dll_mode_type <= 1;
elsif ((DLL_FREQUENCY_MODE = "low") or (DLL_FREQUENCY_MODE = "LOW")) then
dll_mode_type <= 0;
else
GenericValueCheckMessage
(HeaderMsg => "Attribute Syntax Error",
GenericName => "DLL_FREQUENCY_MODE",
EntityName => "X_DCM_SP",
InstanceName => InstancePath,
GenericValue => DLL_FREQUENCY_MODE,
Unit => "",
ExpectedValueMsg => "Legal Values for this attribute are HIGH or LOW",
ExpectedGenericValue => "",
TailMsg => "",
MsgSeverity => error
);
end if;
if ((DSS_MODE = "none") or (DSS_MODE = "NONE")) then
else
GenericValueCheckMessage
(HeaderMsg => "Attribute Syntax Error",
GenericName => "DSS_MODE",
EntityName => "X_DCM_SP",
InstanceName => InstancePath,
GenericValue => DSS_MODE,
Unit => "",
ExpectedValueMsg => "Legal Values for this attribute are NONE",
ExpectedGenericValue => "",
TailMsg => "",
MsgSeverity => error
);
end if;
case DUTY_CYCLE_CORRECTION is
when false => clk1x_type <= 0;
when true => clk1x_type <= 1;
when others =>
GenericValueCheckMessage
(HeaderMsg => "Attribute Syntax Error",
GenericName => "DUTY_CYCLE_CORRECTION",
EntityName => "X_DCM_SP",
InstanceName => InstancePath,
GenericValue => DUTY_CYCLE_CORRECTION,
Unit => "",
ExpectedValueMsg => "Legal Values for this attribute are TRUE or FALSE",
ExpectedGenericValue => "",
TailMsg => "",
MsgSeverity => error
);
end case;
if ((PHASE_SHIFT < -255) or (PHASE_SHIFT > 255)) then
GenericValueCheckMessage
(HeaderMsg => "Attribute Syntax Error",
GenericName => "PHASE_SHIFT",
EntityName => "X_DCM_SP",
InstanceName => InstancePath,
GenericValue => PHASE_SHIFT,
Unit => "",
ExpectedValueMsg => "Legal Values for this attribute are -255 ... 255",
ExpectedGenericValue => "",
TailMsg => "",
MsgSeverity => error
);
end if;
period_jitter <= SIM_CLKIN_PERIOD_JITTER;
cycle_jitter <= SIM_CLKIN_CYCLE_JITTER;
case STARTUP_WAIT is
when false => null;
when true => null;
when others =>
GenericValueCheckMessage
(HeaderMsg => "Attribute Syntax Error",
GenericName => "STARTUP_WAIT",
EntityName => "X_DCM_SP",
InstanceName => InstancePath,
GenericValue => STARTUP_WAIT,
Unit => "",
ExpectedValueMsg => "Legal Values for this attribute are TRUE or FALSE",
ExpectedGenericValue => "",
TailMsg => "",
MsgSeverity => error
);
end case;
--
-- fx parameters
--
gcd <= 1;
for i in 2 to CLKFX_MULTIPLY loop
if (((CLKFX_MULTIPLY mod i) = 0) and ((CLKFX_DIVIDE mod i) = 0)) then
gcd <= i;
end if;
end loop;
numerator <= CLKFX_MULTIPLY / gcd;
denominator <= CLKFX_DIVIDE / gcd;
wait;
end process INITPROC;
--
-- input wire delays
--
WireDelay : block
begin
VitalWireDelay (CLKIN_ipd, CLKIN, tipd_CLKIN);
VitalWireDelay (CLKFB_ipd, CLKFB, tipd_CLKFB);
VitalWireDelay (DSSEN_ipd, DSSEN, tipd_DSSEN);
VitalWireDelay (PSCLK_ipd, PSCLK, tipd_PSCLK);
VitalWireDelay (PSEN_ipd, PSEN, tipd_PSEN);
VitalWireDelay (PSINCDEC_ipd, PSINCDEC, tipd_PSINCDEC);
VitalWireDelay (RST_ipd, RST, tipd_RST);
end block;
SignalDelay : block
begin
VitalSignalDelay (PSCLK_dly, PSCLK_ipd, ticd_PSCLK);
VitalSignalDelay (PSEN_dly, PSEN_ipd, tisd_PSEN_PSCLK);
VitalSignalDelay (PSINCDEC_dly, PSINCDEC_ipd, tisd_PSINCDEC_PSCLK);
end block;
i_clock_divide_by_2 : x_dcm_sp_clock_divide_by_2
port map (
clock => clkin_ipd,
clock_type => clkin_type,
rst => rst_ipd,
clock_out => clkin_div);
i_max_clkin : x_dcm_sp_maximum_period_check
generic map (
clock_name => "CLKIN",
maximum_period => MAXPERCLKIN)
port map (
clock => clkin_ipd,
rst => rst_ipd);
i_max_psclk : x_dcm_sp_maximum_period_check
generic map (
clock_name => "PSCLK",
maximum_period => MAXPERPSCLK)
port map (
clock => psclk_dly,
rst => rst_ipd);
i_clkin_lost : x_dcm_sp_clock_lost
port map (
lost => clkin_lost_out,
clock => clkin_ipd,
enable => first_time_locked,
rst => rst_ipd
);
i_clkfx_lost : x_dcm_sp_clock_lost
port map (
lost => clkfx_lost_out,
clock => clkfx_out,
enable => first_time_locked,
rst => rst_ipd
);
clkin_ps_tmp <= transport clkin_div after ps_delay_md;
clkin_ps <= clkin_ps_mkup when clkin_ps_mkup_win = '1' else clkin_ps_tmp;
clkin_fb <= transport (clkin_ps and lock_fb);
clkin_ps_tmp_p: process
variable ps_delay_last : integer := 0;
variable ps_delay_int : integer;
variable period_int2 : integer := 0;
variable period_int3 : integer := 0;
begin
if (ps_type = 2) then
ps_delay_int := (ps_delay /1 ps ) * 1;
period_int2 := 2 * period_int;
period_int3 := 3 * period_int;
if (rising_edge(clkin_div)) then
if ((ps_delay_last > 0 and ps_delay_int <= 0 ) or
(ps_delay_last >= period_int and ps_delay_int < period_int) or
(ps_delay_last >= period_int2 and ps_delay_int < period_int2) or
(ps_delay_last >= period_int3 and ps_delay_int < period_int3)) then
clkin_ps_mkup_win <= '1';
clkin_ps_mkup <= '1';
wait until falling_edge(clkin_div);
clkin_ps_mkup_win <= '1';
clkin_ps_mkup <= '0';
else
clkin_ps_mkup_win <= '0';
clkin_ps_mkup <= '0';
end if;
end if;
if (falling_edge(clkin_div)) then
if ((ps_delay_last > 0 and ps_delay_int <= 0 ) or
(ps_delay_last >= period_int and ps_delay_int < period_int) or
(ps_delay_last >= period_int2 and ps_delay_int < period_int2) or
(ps_delay_last >= period_int3 and ps_delay_int < period_int3)) then
clkin_ps_mkup <= '0';
clkin_ps_mkup_win <= '0';
wait until rising_edge(clkin_div);
clkin_ps_mkup <= '1';
clkin_ps_mkup_win <= '1';
wait until falling_edge(clkin_div);
clkin_ps_mkup <= '0';
clkin_ps_mkup_win <= '1';
else
clkin_ps_mkup <= '0';
clkin_ps_mkup_win <= '0';
end if;
end if;
ps_delay_last := ps_delay_int;
end if;
wait on clkin_div;
end process;
detect_first_time_locked : process
begin
if (first_time_locked = false) then
if (rising_edge(locked_out)) then
first_time_locked <= true;
end if;
end if;
wait on locked_out;
end process detect_first_time_locked;
set_reset_en_status : process
begin
if (rst_ipd = '1') then
en_status <= false;
elsif (rising_edge(Locked_sig)) then
en_status <= true;
end if;
wait on rst_ipd, Locked_sig;
end process set_reset_en_status;
gen_clkfb_div_en: process
begin
if (rst_ipd = '1') then
clkfb_div_en <= '0';
elsif (falling_edge(clkfb_ipd)) then
if (lock_fb_dly='1' and lock_period='1' and lock_fb = '1' and clkin_ps = '0') then
clkfb_div_en <= '1';
end if;
end if;
wait on clkfb_ipd, rst_ipd;
end process gen_clkfb_div_en;
gen_clkfb_div: process
begin
if (rst_ipd = '1') then
clkfb_div <= '0';
elsif (rising_edge(clkfb_ipd)) then
if (clkfb_div_en = '1') then
clkfb_div <= not clkfb_div;
end if;
end if;
wait on clkfb_ipd, rst_ipd;
end process gen_clkfb_div;
determine_clkfb_chk: process
begin
if (clkfb_type = 2) then
clkfb_chk <= clkfb_div;
else
clkfb_chk <= clkfb_ipd and lock_fb_dly;
end if;
wait on clkfb_ipd, clkfb_div;
end process determine_clkfb_chk;
set_reset_clkin_chkin : process
begin
if ((rising_edge(clkin_fb)) or (rising_edge(chk_rst))) then
if (chk_rst = '1') then
clkin_chkin <= '0';
else
clkin_chkin <= '1';
end if;
end if;
wait on clkin_fb, chk_rst;
end process set_reset_clkin_chkin;
set_reset_clkfb_chkin : process
begin
if ((rising_edge(clkfb_chk)) or (rising_edge(chk_rst))) then
if (chk_rst = '1') then
clkfb_chkin <= '0';
else
clkfb_chkin <= '1';
end if;
end if;
wait on clkfb_chk, chk_rst;
end process set_reset_clkfb_chkin;
-- assign_chk_rst: process
-- begin
-- if ((rst_ipd = '1') or (clock_stopped = '1')) then
-- chk_rst <= '1';
-- else
-- chk_rst <= '0';
-- end if;
-- wait on rst_ipd, clock_stopped;
-- end process assign_chk_rst;
chk_rst <= '1' when ((rst_ipd = '1') or (clock_stopped = '1')) else '0';
-- assign_chk_enable: process
-- begin
-- if ((clkin_chkin = '1') and (clkfb_chkin = '1')) then
-- chk_enable <= '1';
-- else
-- chk_enable <= '0';
-- end if;
-- wait on clkin_chkin, clkfb_chkin;
-- end process assign_chk_enable;
chk_enable <= '1' when ((clkin_chkin = '1') and (clkfb_chkin = '1') and (lock_ps = '1') and (lock_fb_dly = '1') and (lock_fb = '1')) else '0';
control_status_bits: process
begin
if ((rst_ipd = '1') or (en_status = false)) then
ps_overflow_out_ext <= '0';
clkin_lost_out_ext <= '0';
clkfx_lost_out_ext <= '0';
else
ps_overflow_out_ext <= ps_overflow_out;
clkin_lost_out_ext <= clkin_lost_out;
clkfx_lost_out_ext <= clkfx_lost_out;
end if;
wait on clkfx_lost_out, clkin_lost_out, en_status, ps_overflow_out, rst_ipd;
end process control_status_bits;
determine_period_div : process
variable clkin_div_edge_previous : time := 0 ps;
variable clkin_div_edge_current : time := 0 ps;
begin
if ((rising_edge(rst_ipd)) or (rst_ipd = '1')) then
clkin_div_edge_previous := 0 ps;
clkin_div_edge_current := 0 ps;
period_div <= 0 ps;
else
if (rising_edge(clkin_div)) then
clkin_div_edge_previous := clkin_div_edge_current;
clkin_div_edge_current := NOW;
if ((clkin_div_edge_current - clkin_div_edge_previous) <= (1.5 * period_div)) then
period_div <= clkin_div_edge_current - clkin_div_edge_previous;
elsif ((period_div = 0 ps) and (clkin_div_edge_previous /= 0 ps)) then
period_div <= clkin_div_edge_current - clkin_div_edge_previous;
end if;
end if;
end if;
wait on clkin_div, rst_ipd;
end process determine_period_div;
determine_period_ps : process
variable clkin_ps_edge_previous : time := 0 ps;
variable clkin_ps_edge_current : time := 0 ps;
begin
if ((rising_edge(rst_ipd)) or (rst_ipd = '1')) then
clkin_ps_edge_previous := 0 ps;
clkin_ps_edge_current := 0 ps;
period_ps <= 0 ps;
else
if (rising_edge(clkin_ps)) then
clkin_ps_edge_previous := clkin_ps_edge_current;
clkin_ps_edge_current := NOW;
wait for 0 ps;
if ((clkin_ps_edge_current - clkin_ps_edge_previous) <= (1.5 * period_ps)) then
period_ps <= clkin_ps_edge_current - clkin_ps_edge_previous;
elsif ((period_ps = 0 ps) and (clkin_ps_edge_previous /= 0 ps)) then
period_ps <= clkin_ps_edge_current - clkin_ps_edge_previous;
end if;
end if;
end if;
wait on clkin_ps, rst_ipd;
end process determine_period_ps;
assign_lock_ps_fb : process
begin
if ((rising_edge(rst_ipd)) or (rst_ipd = '1')) then
lock_fb <= '0';
lock_ps <= '0';
lock_ps_dly <= '0';
lock_fb_dly <= '0';
lock_fb_dly_tmp <= '0';
else
if (rising_edge(clkin_ps)) then
lock_ps <= lock_period;
lock_ps_dly <= lock_ps;
lock_fb <= lock_ps_dly;
lock_fb_dly_tmp <= lock_fb;
end if;
if (falling_edge(clkin_ps)) then
lock_fb_dly <= lock_fb_dly_tmp after (period/4);
end if;
end if;
wait on clkin_ps, rst_ipd;
end process assign_lock_ps_fb;
calculate_clkout_delay : process
begin
if ((rising_edge(rst_ipd)) or (rst_ipd = '1')) then
clkout_delay <= 0 ps;
elsif (fb_delay = 0 ps) then
clkout_delay <= 0 ps;
elsif (period'event or fb_delay'event) then
clkout_delay <= period - fb_delay;
end if;
wait on period, fb_delay, rst_ipd;
end process calculate_clkout_delay;
--
--generate master reset signal
--
gen_master_rst : process
begin
if (rising_edge(clkin_ipd)) then
rst_reg(2) <= rst_reg(1) and rst_reg(0) and rst_ipd;
rst_reg(1) <= rst_reg(0) and rst_ipd;
rst_reg(0) <= rst_ipd;
end if;
wait on clkin_ipd;
end process gen_master_rst;
check_rst_width : process
variable Message : line;
begin
if (rst_ipd ='1') then
rst_flag <= '0';
end if;
if (falling_edge(rst_ipd)) then
if ((rst_reg(2) and rst_reg(1) and rst_reg(0)) = '0') then
rst_flag <= '1';
Write ( Message, string'(" Input Error : RST on X_DCM_SP "));
Write ( Message, string'(" must be asserted for 3 CLKIN clock cycles. "));
assert false report Message.all severity error;
DEALLOCATE (Message);
end if;
end if;
wait on rst_ipd;
end process check_rst_width;
--
--phase shift parameters
--
ps_max_range_p : process (period)
variable period_ps_tmp : integer := 0;
begin
period_int <= (period/ 1 ps ) * 1;
if (clkin_type = 1) then
period_ps_tmp := 2 * (period/ 1 ns );
else
period_ps_tmp := (period/ 1 ns ) * 1;
end if;
if (period_ps_tmp > 3) then
ps_max_range <= 20 * (period_ps_tmp - 3);
else
ps_max_range <= 0;
end if;
end process;
ps_delay_md_p : process (period, ps_delay, lock_period, rst_ipd)
variable tmp_value : integer;
variable tmp_value1 : integer;
variable tmp_value2 : integer;
begin
if (rst_ipd = '1') then
ps_delay_md <= 0 ps;
elsif (lock_period = '1') then
tmp_value := (ps_delay / 1 ps ) * 1;
tmp_value1 := (period / 1 ps) * 1;
tmp_value2 := tmp_value mod tmp_value1;
ps_delay_md <= period + tmp_value2 * 1 ps;
end if;
end process;
determine_phase_shift : process
variable Message : line;
variable first_time : boolean := true;
variable ps_in : integer;
variable ps_acc : integer := 0;
variable ps_step_int : integer := 0;
begin
if (first_time = true) then
if ((CLKOUT_PHASE_SHIFT = "none") or (CLKOUT_PHASE_SHIFT = "NONE")) then
ps_in := 256;
elsif ((CLKOUT_PHASE_SHIFT = "fixed") or (CLKOUT_PHASE_SHIFT = "FIXED")) then
ps_in := 256 + PHASE_SHIFT;
elsif ((CLKOUT_PHASE_SHIFT = "variable") or (CLKOUT_PHASE_SHIFT = "VARIABLE")) then
ps_in := 256 + PHASE_SHIFT;
end if;
ps_step_int := (PS_STEP / 1 ps ) * 1;
first_time := false;
end if;
if ((rising_edge(rst_ipd)) or (rst_ipd = '1')) then
if ((CLKOUT_PHASE_SHIFT = "none") or (CLKOUT_PHASE_SHIFT = "NONE")) then
ps_in := 256;
elsif ((CLKOUT_PHASE_SHIFT = "fixed") or (CLKOUT_PHASE_SHIFT = "FIXED")) then
ps_in := 256 + PHASE_SHIFT;
elsif ((CLKOUT_PHASE_SHIFT = "variable") or (CLKOUT_PHASE_SHIFT = "VARIABLE")) then
ps_in := 256 + PHASE_SHIFT;
else
end if;
ps_lock <= '0';
ps_overflow_out <= '0';
ps_delay <= 0 ps;
ps_acc := 0;
elsif (rising_edge(lock_period_pulse)) then
ps_delay <= (ps_in * period_div / 256);
elsif (rising_edge(PSCLK_dly)) then
if (ps_type = 2) then
if (psen_dly = '1') then
if (ps_lock = '1') then
Write ( Message, string'(" Warning : Please wait for PSDONE signal before adjusting the Phase Shift. "));
assert false report Message.all severity warning;
DEALLOCATE (Message);
else if (lock_ps = '1') then
if (psincdec_dly = '1') then
if (ps_acc > ps_max_range) then
ps_overflow_out <= '1';
else
ps_delay <= ps_delay + PS_STEP;
ps_acc := ps_acc + 1;
ps_overflow_out <= '0';
end if;
ps_lock <= '1';
elsif (psincdec_dly = '0') then
if (ps_acc < -ps_max_range) then
ps_overflow_out <= '1';
else
ps_delay <= ps_delay - PS_STEP;
ps_acc := ps_acc - 1;
ps_overflow_out <= '0';
end if;
ps_lock <= '1';
end if;
end if;
end if;
end if;
end if;
end if;
if (ps_lock_reg'event) then
ps_lock <= ps_lock_reg;
end if;
wait on lock_period_pulse, psclk_dly, ps_lock_reg, rst_ipd;
end process determine_phase_shift;
determine_psdone_out : process
begin
if (rising_edge(ps_lock)) then
ps_lock_reg <= '1';
wait until (rising_edge(clkin_ps));
wait until (rising_edge(psclk_dly));
wait until (rising_edge(psclk_dly));
wait until (rising_edge(psclk_dly));
psdone_out <= '1';
wait until (rising_edge(psclk_dly));
psdone_out <= '0';
ps_lock_reg <= '0';
end if;
wait on ps_lock;
end process determine_psdone_out;
--
--determine clock period
--
determine_clock_period : process
variable clkin_edge_previous : time := 0 ps;
variable clkin_edge_current : time := 0 ps;
begin
if ((rising_edge(rst_ipd)) or (rst_ipd = '1')) then
clkin_period_real(0) <= 0 ps;
clkin_period_real(1) <= 0 ps;
clkin_period_real(2) <= 0 ps;
clkin_edge_previous := 0 ps;
clkin_edge_current := 0 ps;
elsif (rising_edge(clkin_div)) then
clkin_edge_previous := clkin_edge_current;
clkin_edge_current := NOW;
clkin_period_real(2) <= clkin_period_real(1);
clkin_period_real(1) <= clkin_period_real(0);
if (clkin_edge_previous /= 0 ps) then
clkin_period_real(0) <= clkin_edge_current - clkin_edge_previous;
end if;
end if;
if (no_stop'event) then
clkin_period_real(0) <= clkin_period_real0_temp;
end if;
wait on clkin_div, no_stop, rst_ipd;
end process determine_clock_period;
evaluate_clock_period : process
variable Message : line;
begin
if ((rising_edge(rst_ipd)) or (rst_ipd = '1')) then
lock_period <= '0';
clock_stopped <= '1';
clkin_period_real0_temp <= 0 ps;
else
if (falling_edge(clkin_div)) then
if (lock_period = '0') then
if ((clkin_period_real(0) /= 0 ps ) and (clkin_period_real(0) - cycle_jitter <= clkin_period_real(1)) and (clkin_period_real(1) <= clkin_period_real(0) + cycle_jitter) and (clkin_period_real(1) - cycle_jitter <= clkin_period_real(2)) and (clkin_period_real(2) <= clkin_period_real(1) + cycle_jitter)) then
lock_period <= '1';
period_orig <= (clkin_period_real(0) + clkin_period_real(1) + clkin_period_real(2)) / 3;
period <= clkin_period_real(0);
end if;
elsif (lock_period = '1') then
if (100000000 ns < clkin_period_real(0)) then
Write ( Message, string'(" Warning : CLKIN stopped toggling on instance "));
Write ( Message, Instancepath );
Write ( Message, string'(" exceeds "));
Write ( Message, string'(" 100 ms "));
Write ( Message, string'(" Current CLKIN Period = "));
Write ( Message, clkin_period_real(0));
assert false report Message.all severity warning;
DEALLOCATE (Message);
lock_period <= '0';
wait until (falling_edge(rst_reg(2)));
elsif ((period_orig * 2 < clkin_period_real(0)) and (clock_stopped = '0')) then
clkin_period_real0_temp <= clkin_period_real(1);
no_stop <= not no_stop;
clock_stopped <= '1';
elsif ((clkin_period_real(0) < period_orig - period_jitter) or (period_orig + period_jitter < clkin_period_real(0))) then
Write ( Message, string'(" Warning : Input Clock Period Jitter on instance "));
Write ( Message, Instancepath );
Write ( Message, string'(" exceeds "));
Write ( Message, period_jitter );
Write ( Message, string'(" Locked CLKIN Period = "));
Write ( Message, period_orig );
Write ( Message, string'(" Current CLKIN Period = "));
Write ( Message, clkin_period_real(0) );
assert false report Message.all severity warning;
DEALLOCATE (Message);
lock_period <= '0';
wait until (falling_edge(rst_reg(2)));
elsif ((clkin_period_real(0) < clkin_period_real(1) - cycle_jitter) or (clkin_period_real(1) + cycle_jitter < clkin_period_real(0))) then
Write ( Message, string'(" Warning : Input Clock Cycle Jitter on on instance "));
Write ( Message, Instancepath );
Write ( Message, string'(" exceeds "));
Write ( Message, cycle_jitter );
Write ( Message, string'(" Previous CLKIN Period = "));
Write ( Message, clkin_period_real(1) );
Write ( Message, string'(" Current CLKIN Period = "));
Write ( Message, clkin_period_real(0) );
assert false report Message.all severity warning;
DEALLOCATE (Message);
lock_period <= '0';
wait until (falling_edge(rst_reg(2)));
else
period <= clkin_period_real(0);
clock_stopped <= '0';
end if;
end if;
end if;
end if;
wait on clkin_div, rst_ipd;
end process evaluate_clock_period;
lock_period_dly1 <= transport lock_period after 1 ps;
lock_period_dly <= transport lock_period_dly1 after period/2;
lock_period_pulse <= '1' when ((lock_period = '1') and (lock_period_dly = '0')) else '0';
--
--determine clock delay
--
determine_clock_delay : process
variable delay_edge : time := 0 ps;
variable temp1 : integer := 0;
variable temp2 : integer := 0;
variable temp : integer := 0;
variable delay_edge_current : time := 0 ps;
begin
if ((rising_edge(rst_ipd)) or (rst_ipd = '1')) then
fb_delay <= 0 ps;
fb_delay_found <= '0';
else
if (rising_edge(lock_ps_dly)) then
if ((lock_period = '1') and (clkfb_type /= 0)) then
if (clkfb_type = 1) then
wait until ((rising_edge(clk0_sig)) or (rst_ipd'event));
delay_edge := NOW;
elsif (clkfb_type = 2) then
wait until ((rising_edge(clk2x_sig)) or (rst_ipd'event));
delay_edge := NOW;
end if;
wait until ((rising_edge(clkfb_ipd)) or (rst_ipd'event));
temp1 := ((NOW*1) - (delay_edge*1))/ (1 ps);
temp2 := (period_orig * 1)/ (1 ps);
temp := temp1 mod temp2;
fb_delay <= temp * 1 ps;
fb_delay_found <= '1';
end if;
end if;
end if;
wait on lock_ps_dly, rst_ipd;
end process determine_clock_delay;
--
-- determine feedback lock
--
GEN_CLKFB_WINDOW : process
begin
if ((rising_edge(rst_ipd)) or (rst_ipd = '1')) then
clkfb_window <= '0';
else
if (rising_edge(clkfb_chk)) then
wait for 0 ps;
clkfb_window <= '1';
wait for cycle_jitter;
clkfb_window <= '0';
end if;
end if;
wait on clkfb_chk, rst_ipd;
end process GEN_CLKFB_WINDOW;
GEN_CLKIN_WINDOW : process
begin
if ((rising_edge(rst_ipd)) or (rst_ipd = '1')) then
clkin_window <= '0';
else
if (rising_edge(clkin_fb)) then
wait for 0 ps;
clkin_window <= '1';
wait for cycle_jitter;
clkin_window <= '0';
end if;
end if;
wait on clkin_fb, rst_ipd;
end process GEN_CLKIN_WINDOW;
set_reset_lock_clkin : process
begin
if ((rising_edge(rst_ipd)) or (rst_ipd = '1')) then
lock_clkin <= '0';
else
if (rising_edge(clkin_fb)) then
wait for 1 ps;
if (((clkfb_window = '1') and (fb_delay_found = '1')) or ((clkin_lost_out = '1') and (lock_out(0) = '1'))) then
lock_clkin <= '1';
else
if (chk_enable = '1') then
lock_clkin <= '0';
end if;
end if;
end if;
end if;
wait on clkin_fb, rst_ipd;
end process set_reset_lock_clkin;
set_reset_lock_clkfb : process
begin
if ((rising_edge(rst_ipd)) or (rst_ipd = '1')) then
lock_clkfb <= '0';
else
if (rising_edge(clkfb_chk)) then
wait for 1 ps;
if (((clkin_window = '1') and (fb_delay_found = '1')) or ((clkin_lost_out = '1') and (lock_out(0) = '1')))then
lock_clkfb <= '1';
else
if (chk_enable = '1') then
lock_clkfb <= '0';
end if;
end if;
end if;
end if;
wait on clkfb_chk, rst_ipd;
end process set_reset_lock_clkfb;
assign_lock_delay : process
begin
if ((rising_edge(rst_ipd)) or (rst_ipd = '1')) then
lock_delay <= '0';
else
if (falling_edge(clkin_fb)) then
lock_delay <= lock_clkin or lock_clkfb;
end if;
end if;
wait on clkin_fb, rst_ipd;
end process;
--
--generate lock signal
--
generate_lock : process(clkin_ps, rst_ipd)
begin
if (rst_ipd='1') then
lock_out <= "00";
locked_out <= '0';
lock_out1_neg <= '0';
elsif (rising_edge(clkin_ps)) then
if (clkfb_type = 0) then
lock_out(0) <= lock_period;
else
lock_out(0) <= lock_period and lock_delay and lock_fb;
end if;
lock_out(1) <= lock_out(0);
locked_out <= lock_out(1);
elsif (falling_edge(clkin_ps)) then
lock_out1_neg <= lock_out(1);
end if;
end process generate_lock;
--
--generate the clk1x_out
--
gen_clk1x : process( clkin_ps, rst_ipd)
begin
if ((rising_edge(rst_ipd)) or (rst_ipd = '1')) then
clk0_out <= '0';
elsif (clkin_ps'event) then
if (clkin_ps = '1' ) then
if ((clk1x_type = 1) and (lock_out(0) = '1')) then
clk0_out <= '1', '0' after period/2;
else
clk0_out <= '1';
end if;
else
if ((clkin_ps = '0') and ((((clk1x_type = 1) and (lock_out(0) = '1')) = false) or ((lock_out(0) = '1') and (lock_out(1) = '0')))) then
clk0_out <= '0';
end if;
end if;
end if;
end process gen_clk1x;
--
--generate the clk2x_out
--
gen_clk2x : process
begin
if (rising_edge(rst_ipd) or (rst_ipd = '1')) then
clk2x_out <= '0';
else
if (rising_edge(clkin_ps)) then
clk2x_out <= '1';
wait for (period / 4);
clk2x_out <= '0';
wait for (period / 4);
clk2x_out <= '1';
wait for (period / 4);
clk2x_out <= '0';
end if;
end if;
wait on clkin_ps, rst_ipd;
end process gen_clk2x;
--
--generate the clkdv_out
--
gen_clkdv : process (clkin_ps, rst_ipd)
begin
if (rst_ipd='1') then
clkdv_out <= '0';
clkdv_cnt <= 0;
elsif ((rising_edge(clkin_ps)) or (falling_edge(clkin_ps))) then
if (lock_out1_neg = '1') then
if (clkdv_cnt >= divide_type -1) then
clkdv_cnt <= 0;
else
clkdv_cnt <= clkdv_cnt + 1;
end if;
if (clkdv_cnt < divide_type /2) then
clkdv_out <= '1';
else
if ( ((divide_type rem (2)) > 0) and (dll_mode_type = 0)) then
clkdv_out <= '0' after (period/4);
else
clkdv_out <= '0';
end if;
end if;
end if;
end if;
end process;
--
-- generate fx output signal
--
calculate_period_fx : process
begin
if (lock_period = '1') then
period_fx <= (period * denominator) / (numerator * 2);
remain_fx <= (((period/1 ps) * denominator) mod (numerator * 2)) * 1 ps;
end if;
wait on lock_period, period, denominator, numerator;
end process calculate_period_fx;
generate_clkfx : process
variable temp : integer;
begin
if (rst_ipd = '1') then
clkfx_out <= '0';
elsif (clkin_lost_out_ext = '1') then
wait until (rising_edge(rst_ipd));
clkfx_out <= '0';
wait until (falling_edge(rst_reg(2)));
elsif (rising_edge(clkin_ps)) then
if (lock_out(1) = '1') then
clkfx_out <= '1';
temp := numerator * 2 - 1 - 1;
for p in 0 to temp loop
wait for (period_fx);
clkfx_out <= not clkfx_out;
end loop;
if (period_fx > (period / 2)) then
wait for (period_fx - (period / 2));
end if;
end if;
if (clkin_lost_out_ext = '1') then
wait until (rising_edge(rst_ipd));
clkfx_out <= '0';
wait until (falling_edge(rst_reg(2)));
end if;
end if;
wait on clkin_lost_out_ext, clkin_ps, rst_ipd, rst_reg(2);
end process generate_clkfx;
--
--generate all output signal
--
schedule_p1_outputs : process
begin
if (CLK0_out'event) then
if (clkfb_type /= 0) then
CLK0 <= transport CLK0_out after clkout_delay;
clk0_sig <= transport CLK0_out after clkout_delay;
end if;
if ((dll_mode_type = 0) and (clkfb_type /= 0)) then
CLK90 <= transport clk0_out after (clkout_delay + period / 4);
end if;
end if;
if (CLK0_out'event or rst_ipd'event)then
if (rst_ipd = '1') then
CLK180 <= '0';
CLK270 <= '0';
elsif (CLK0_out'event) then
if (clkfb_type /= 0) then
CLK180 <= transport (not clk0_out) after clkout_delay;
end if;
if ((dll_mode_type = 0) and (clkfb_type /= 0)) then
CLK270 <= transport (not clk0_out) after (clkout_delay + period/4);
end if;
end if;
end if;
if (clk2x_out'event) then
if ((dll_mode_type = 0) and (clkfb_type /= 0)) then
CLK2X <= transport clk2x_out after clkout_delay;
clk2x_sig <= transport clk2x_out after clkout_delay;
end if;
end if;
if (CLK2X_out'event or rst_ipd'event) then
if (rst_ipd = '1') then
CLK2X180 <= '0';
elsif (CLK2X_out'event) then
if ((dll_mode_type = 0) and (clkfb_type /= 0)) then
CLK2X180 <= transport (not CLK2X_out) after clkout_delay;
end if;
end if;
end if;
if (clkdv_out'event) then
if (clkfb_type /= 0) then
CLKDV <= transport clkdv_out after clkout_delay;
end if;
end if;
if (clkfx_out'event or rst_ipd'event) then
if (rst_ipd = '1') then
CLKFX <= '0';
elsif (clkfx_out'event) then
CLKFX <= transport clkfx_out after clkout_delay;
end if;
end if;
if (clkfx_out'event or (rising_edge(rst_ipd)) or first_time_locked'event or locked_out'event) then
if ((rst_ipd = '1') or (not first_time_locked)) then
CLKFX180 <= '0';
else
CLKFX180 <= transport (not clkfx_out) after clkout_delay;
end if;
end if;
if (status_out(0)'event) then
status(0) <= status_out(0);
end if;
if (status_out(1)'event) then
status(1) <= status_out(1);
end if;
if (status_out(2)'event) then
status(2) <= status_out(2);
end if;
wait on clk0_out, clk2x_out, clkdv_out, clkfx_out, first_time_locked, locked_out, rst_ipd, status_out;
end process;
assign_status_out : process
begin
if (rst_ipd = '1') then
status_out(0) <= '0';
status_out(1) <= '0';
status_out(2) <= '0';
elsif (ps_overflow_out_ext'event) then
status_out(0) <= ps_overflow_out_ext;
elsif (clkin_lost_out_ext'event) then
status_out(1) <= clkin_lost_out_ext;
elsif (clkfx_lost_out_ext'event) then
status_out(2) <= clkfx_lost_out_ext;
end if;
wait on clkin_lost_out_ext, clkfx_lost_out_ext, ps_overflow_out_ext, rst_ipd;
end process assign_status_out;
locked_out_out <= 'X' when rst_flag = '1' else locked_out;
-- LOCKED <= locked_out_out;
-- PSDONE <= psdone_out;
-- LOCKED_sig <= locked_out_out;
schedule_outputs : process
variable PSDONE_GlitchData : VitalGlitchDataType;
variable LOCKED_GlitchData : VitalGlitchDataType;
begin
VitalPathDelay01 (
OutSignal => PSDONE,
GlitchData => PSDONE_GlitchData,
OutSignalName => "PSDONE",
OutTemp => psdone_out,
Paths => (0 => (psdone_out'last_event, tpd_PSCLK_PSDONE, true)),
Mode => OnEvent,
Xon => Xon,
MsgOn => MsgOn,
MsgSeverity => warning
);
LOCKED_sig <= locked_out_out after tpd_CLKIN_LOCKED(tr01);
VitalPathDelay01 (
OutSignal => LOCKED,
GlitchData => LOCKED_GlitchData,
OutSignalName => "LOCKED",
OutTemp => locked_out_out,
Paths => (0 => (locked_out_out'last_event, tpd_CLKIN_LOCKED, true)),
Mode => OnEvent,
Xon => Xon,
MsgOn => MsgOn,
MsgSeverity => warning
);
wait on locked_out_out, psdone_out;
end process schedule_outputs;
VitalTimingCheck : process
variable Tviol_PSINCDEC_PSCLK_posedge : std_ulogic := '0';
variable Tmkr_PSINCDEC_PSCLK_posedge : VitalTimingDataType := VitalTimingDataInit;
variable Tviol_PSEN_PSCLK_posedge : std_ulogic := '0';
variable Tmkr_PSEN_PSCLK_posedge : VitalTimingDataType := VitalTimingDataInit;
variable Pviol_CLKIN : std_ulogic := '0';
variable PInfo_CLKIN : VitalPeriodDataType := VitalPeriodDataInit;
variable Pviol_PSCLK : std_ulogic := '0';
variable PInfo_PSCLK : VitalPeriodDataType := VitalPeriodDataInit;
variable Pviol_RST : std_ulogic := '0';
variable PInfo_RST : VitalPeriodDataType := VitalPeriodDataInit;
begin
if (TimingChecksOn) then
VitalSetupHoldCheck (
Violation => Tviol_PSINCDEC_PSCLK_posedge,
TimingData => Tmkr_PSINCDEC_PSCLK_posedge,
TestSignal => PSINCDEC_dly,
TestSignalName => "PSINCDEC",
TestDelay => tisd_PSINCDEC_PSCLK,
RefSignal => PSCLK_dly,
RefSignalName => "PSCLK",
RefDelay => ticd_PSCLK,
SetupHigh => tsetup_PSINCDEC_PSCLK_posedge_posedge,
SetupLow => tsetup_PSINCDEC_PSCLK_negedge_posedge,
HoldLow => thold_PSINCDEC_PSCLK_posedge_posedge,
HoldHigh => thold_PSINCDEC_PSCLK_negedge_posedge,
CheckEnabled => (TO_X01(((NOT RST_ipd)) AND (PSEN_dly)) /= '0'),
RefTransition => 'R',
HeaderMsg => InstancePath & "/X_DCM_SP",
Xon => Xon,
MsgOn => MsgOn,
MsgSeverity => warning);
VitalSetupHoldCheck (
Violation => Tviol_PSEN_PSCLK_posedge,
TimingData => Tmkr_PSEN_PSCLK_posedge,
TestSignal => PSEN_dly,
TestSignalName => "PSEN",
TestDelay => tisd_PSEN_PSCLK,
RefSignal => PSCLK_dly,
RefSignalName => "PSCLK",
RefDelay => ticd_PSCLK,
SetupHigh => tsetup_PSEN_PSCLK_posedge_posedge,
SetupLow => tsetup_PSEN_PSCLK_negedge_posedge,
HoldLow => thold_PSEN_PSCLK_posedge_posedge,
HoldHigh => thold_PSEN_PSCLK_negedge_posedge,
CheckEnabled => TO_X01(NOT RST_ipd) /= '0',
RefTransition => 'R',
HeaderMsg => InstancePath & "/X_DCM_SP",
Xon => Xon,
MsgOn => MsgOn,
MsgSeverity => warning);
VitalPeriodPulseCheck (
Violation => Pviol_PSCLK,
PeriodData => PInfo_PSCLK,
TestSignal => PSCLK_dly,
TestSignalName => "PSCLK",
TestDelay => 0 ns,
Period => tperiod_PSCLK_POSEDGE,
PulseWidthHigh => tpw_PSCLK_posedge,
PulseWidthLow => tpw_PSCLK_negedge,
CheckEnabled => true,
HeaderMsg => InstancePath &"/X_DCM_SP",
Xon => Xon,
MsgOn => MsgOn,
MsgSeverity => warning);
VitalPeriodPulseCheck (
Violation => Pviol_CLKIN,
PeriodData => PInfo_CLKIN,
TestSignal => CLKIN_ipd,
TestSignalName => "CLKIN",
TestDelay => 0 ns,
Period => tperiod_CLKIN_POSEDGE,
PulseWidthHigh => tpw_CLKIN_posedge,
PulseWidthLow => tpw_CLKIN_negedge,
CheckEnabled => TO_X01(NOT RST_ipd) /= '0',
HeaderMsg => InstancePath &"/X_DCM_SP",
Xon => Xon,
MsgOn => MsgOn,
MsgSeverity => warning);
VitalPeriodPulseCheck (
Violation => Pviol_RST,
PeriodData => PInfo_RST,
TestSignal => RST_ipd,
TestSignalName => "RST",
TestDelay => 0 ns,
Period => 0 ns,
PulseWidthHigh => tpw_RST_posedge,
PulseWidthLow => 0 ns,
CheckEnabled => true,
HeaderMsg => InstancePath &"/X_DCM_SP",
Xon => Xon,
MsgOn => MsgOn,
MsgSeverity => warning);
end if;
wait on CLKIN_ipd, PSCLK_dly, PSEN_dly, PSINCDEC_dly, RST_ipd;
end process VITALTimingCheck;
end X_DCM_SP_V;
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library unisim;
entity DCM is
generic (
CLKDV_DIVIDE : real := 2.0;
CLKFX_DIVIDE : integer := 1;
CLKFX_MULTIPLY : integer := 4;
CLKIN_DIVIDE_BY_2 : boolean := false;
CLKIN_PERIOD : real := 10.0;
CLKOUT_PHASE_SHIFT : string := "NONE";
CLK_FEEDBACK : string := "1X";
DESKEW_ADJUST : string := "SYSTEM_SYNCHRONOUS";
DFS_FREQUENCY_MODE : string := "LOW";
DLL_FREQUENCY_MODE : string := "LOW";
DSS_MODE : string := "NONE";
DUTY_CYCLE_CORRECTION : boolean := true;
FACTORY_JF : bit_vector := X"C080";
PHASE_SHIFT : integer := 0;
STARTUP_WAIT : boolean := false
);
port (
CLKFB : in std_logic;
CLKIN : in std_logic;
DSSEN : in std_logic;
PSCLK : in std_logic;
PSEN : in std_logic;
PSINCDEC : in std_logic;
RST : in std_logic;
CLK0 : out std_logic;
CLK90 : out std_logic;
CLK180 : out std_logic;
CLK270 : out std_logic;
CLK2X : out std_logic;
CLK2X180 : out std_logic;
CLKDV : out std_logic;
CLKFX : out std_logic;
CLKFX180 : out std_logic;
LOCKED : out std_logic;
PSDONE : out std_logic;
STATUS : out std_logic_vector (7 downto 0));
end ;
architecture sim of DCM is
begin
x0 : entity unisim.X_DCM
generic map (
CLKDV_DIVIDE => CLKDV_DIVIDE, CLKFX_DIVIDE => CLKFX_DIVIDE,
CLKFX_MULTIPLY => CLKFX_MULTIPLY, CLKIN_DIVIDE_BY_2 => CLKIN_DIVIDE_BY_2,
CLKIN_PERIOD => CLKIN_PERIOD, CLKOUT_PHASE_SHIFT => CLKOUT_PHASE_SHIFT,
CLK_FEEDBACK => CLK_FEEDBACK, DESKEW_ADJUST => DESKEW_ADJUST,
DFS_FREQUENCY_MODE => DFS_FREQUENCY_MODE, DLL_FREQUENCY_MODE => DLL_FREQUENCY_MODE,
DSS_MODE => DSS_MODE, DUTY_CYCLE_CORRECTION => DUTY_CYCLE_CORRECTION,
FACTORY_JF => FACTORY_JF, PHASE_SHIFT => PHASE_SHIFT,
STARTUP_WAIT => STARTUP_WAIT
)
port map (
CLKFB => CLKFB, CLKIN => CLKIN, DSSEN => DSSEN, PSCLK => PSCLK,
PSEN => PSEN, PSINCDEC => PSINCDEC, RST => RST, CLK0 => CLK0,
CLK90 => CLK90, CLK180 => CLK180, CLK270 => CLK270, CLK2X => CLK2X,
CLK2X180 => CLK2X180, CLKDV => CLKDV, CLKFX => CLKFX,
CLKFX180 => CLKFX180, LOCKED => LOCKED, PSDONE => PSDONE,
STATUS => STATUS);
end;
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library grlib;
use IEEE.NUMERIC_STD.all;
library STD;
use STD.TEXTIO.all;
library unisim;
--use unisim.vpkg.all;
use unisim.vpkg.all;
entity SYSMON is
generic (
INIT_40 : bit_vector := X"0000";
INIT_41 : bit_vector := X"0000";
INIT_42 : bit_vector := X"0800";
INIT_43 : bit_vector := X"0000";
INIT_44 : bit_vector := X"0000";
INIT_45 : bit_vector := X"0000";
INIT_46 : bit_vector := X"0000";
INIT_47 : bit_vector := X"0000";
INIT_48 : bit_vector := X"0000";
INIT_49 : bit_vector := X"0000";
INIT_4A : bit_vector := X"0000";
INIT_4B : bit_vector := X"0000";
INIT_4C : bit_vector := X"0000";
INIT_4D : bit_vector := X"0000";
INIT_4E : bit_vector := X"0000";
INIT_4F : bit_vector := X"0000";
INIT_50 : bit_vector := X"0000";
INIT_51 : bit_vector := X"0000";
INIT_52 : bit_vector := X"0000";
INIT_53 : bit_vector := X"0000";
INIT_54 : bit_vector := X"0000";
INIT_55 : bit_vector := X"0000";
INIT_56 : bit_vector := X"0000";
INIT_57 : bit_vector := X"0000";
SIM_MONITOR_FILE : string := "design.txt"
);
port (
ALM : out std_logic_vector(2 downto 0);
BUSY : out std_ulogic;
CHANNEL : out std_logic_vector(4 downto 0);
DO : out std_logic_vector(15 downto 0);
DRDY : out std_ulogic;
EOC : out std_ulogic;
EOS : out std_ulogic;
JTAGBUSY : out std_ulogic;
JTAGLOCKED : out std_ulogic;
JTAGMODIFIED : out std_ulogic;
OT : out std_ulogic;
CONVST : in std_ulogic;
CONVSTCLK : in std_ulogic;
DADDR : in std_logic_vector(6 downto 0);
DCLK : in std_ulogic;
DEN : in std_ulogic;
DI : in std_logic_vector(15 downto 0);
DWE : in std_ulogic;
RESET : in std_ulogic;
VAUXN : in std_logic_vector(15 downto 0);
VAUXP : in std_logic_vector(15 downto 0);
VN : in std_ulogic;
VP : in std_ulogic
);
end SYSMON;
architecture SYSMON_V of SYSMON is
---------------------------------------------------------------------------
-- Function SLV_TO_INT converts a std_logic_vector TO INTEGER
---------------------------------------------------------------------------
function SLV_TO_INT(SLV: in std_logic_vector
) return integer is
variable int : integer;
begin
int := 0;
for i in SLV'high downto SLV'low loop
int := int * 2;
if SLV(i) = '1' then
int := int + 1;
end if;
end loop;
return int;
end;
---------------------------------------------------------------------------
-- Function ADDR_IS_VALID checks for the validity of the argument. A FALSE
-- is returned if any argument bit is other than a '0' or '1'.
---------------------------------------------------------------------------
function ADDR_IS_VALID (
SLV : in std_logic_vector
) return boolean is
variable IS_VALID : boolean := TRUE;
begin
for I in SLV'high downto SLV'low loop
if (SLV(I) /= '0' AND SLV(I) /= '1') then
IS_VALID := FALSE;
end if;
end loop;
return IS_VALID;
end ADDR_IS_VALID;
function int2real( int_in : in integer) return real is
variable conline1 : line;
variable rl_value : real;
variable tmpv1 : real;
variable tmpv2 : real := 1.0;
variable tmpi : integer;
begin
tmpi := int_in;
write (conline1, tmpi);
write (conline1, string'(".0 "));
write (conline1, tmpv2);
read (conline1, tmpv1);
rl_value := tmpv1;
return rl_value;
DEALLOCATE(conline1);
end int2real;
function real2int( real_in : in real) return integer is
variable int_value : integer;
variable tmpt : time;
variable tmpt1 : time;
variable tmpa : real;
variable tmpr : real;
variable int_out : integer;
begin
tmpa := abs(real_in);
tmpt := tmpa * 1 ps;
int_value := (tmpt / 1 ps ) * 1;
tmpt1 := int_value * 1 ps;
tmpr := int2real(int_value);
if ( real_in < 0.0000) then
if (tmpr > tmpa) then
int_out := 1 - int_value;
else
int_out := -int_value;
end if;
else
if (tmpr > tmpa) then
int_out := int_value - 1;
else
int_out := int_value;
end if;
end if;
return int_out;
end real2int;
FUNCTION To_Upper ( CONSTANT val : IN String
) RETURN STRING IS
VARIABLE result : string (1 TO val'LENGTH) := val;
VARIABLE ch : character;
BEGIN
FOR i IN 1 TO val'LENGTH LOOP
ch := result(i);
EXIT WHEN ((ch = NUL) OR (ch = nul));
IF ( ch >= 'a' and ch <= 'z') THEN
result(i) := CHARACTER'VAL( CHARACTER'POS(ch)
- CHARACTER'POS('a')
+ CHARACTER'POS('A') );
END IF;
END LOOP;
RETURN result;
END To_Upper;
procedure get_token(buf : inout LINE; token : out string;
token_len : out integer)
is
variable index : integer := buf'low;
variable tk_index : integer := 0;
variable old_buf : LINE := buf;
BEGIN
while ((index <= buf' high) and ((buf(index) = ' ') or
(buf(index) = HT))) loop
index := index + 1;
end loop;
while((index <= buf'high) and ((buf(index) /= ' ') and
(buf(index) /= HT))) loop
tk_index := tk_index + 1;
token(tk_index) := buf(index);
index := index + 1;
end loop;
token_len := tk_index;
buf := new string'(old_buf(index to old_buf'high));
old_buf := NULL;
END;
procedure skip_blanks(buf : inout LINE)
is
variable index : integer := buf'low;
variable old_buf : LINE := buf;
BEGIN
while ((index <= buf' high) and ((buf(index) = ' ') or
(buf(index) = HT))) loop
index := index + 1;
end loop;
buf := new string'(old_buf(index to old_buf'high));
old_buf := NULL;
END;
procedure infile_format
is
variable message_line : line;
begin
write(message_line, string'("***** SYSMON Simulation Analog Data File Format ******"));
writeline(output, message_line);
write(message_line, string'("NAME: design.txt or user file name passed with generic sim_monitor_file"));
writeline(output, message_line);
write(message_line, string'("FORMAT: First line is header line. Valid column name are: TIME TEMP VCCINT VCCAUX VP VN VAUXP[0] VAUXN[0] ...."));
writeline(output, message_line);
write(message_line, string'("TIME must be in first column."));
writeline(output, message_line);
write(message_line, string'("Time value need to be integer in ns scale"));
writeline(output, message_line);
write(message_line, string'("Analog value need to be real and contain a decimal point '.', zero should be 0.0, 3 should be 3.0"));
writeline(output, message_line);
write(message_line, string'("Each line including header line can not have extra space after the last character/digit."));
writeline(output, message_line);
write(message_line, string'("Each data line must have same number of columns as the header line."));
writeline(output, message_line);
write(message_line, string'("Comment line start with -- or //"));
writeline(output, message_line);
write(message_line, string'("Example:"));
writeline(output, message_line);
write(message_line, string'("TIME TEMP VCCINT VP VN VAUXP[0] VAUXN[0]"));
writeline(output, message_line);
write(message_line, string'("000 125.6 1.0 0.7 0.4 0.3 0.6"));
writeline(output, message_line);
write(message_line, string'("200 25.6 0.8 0.5 0.3 0.8 0.2"));
writeline(output, message_line);
end infile_format;
type REG_FILE is array (integer range <>) of
std_logic_vector(15 downto 0);
signal dr_sram : REG_FILE(16#40# to 16#57#) :=
(
16#40# => TO_STDLOGICVECTOR(INIT_40),
16#41# => TO_STDLOGICVECTOR(INIT_41),
16#42# => TO_STDLOGICVECTOR(INIT_42),
16#43# => TO_STDLOGICVECTOR(INIT_43),
16#44# => TO_STDLOGICVECTOR(INIT_44),
16#45# => TO_STDLOGICVECTOR(INIT_45),
16#46# => TO_STDLOGICVECTOR(INIT_46),
16#47# => TO_STDLOGICVECTOR(INIT_47),
16#48# => TO_STDLOGICVECTOR(INIT_48),
16#49# => TO_STDLOGICVECTOR(INIT_49),
16#4A# => TO_STDLOGICVECTOR(INIT_4A),
16#4B# => TO_STDLOGICVECTOR(INIT_4B),
16#4C# => TO_STDLOGICVECTOR(INIT_4C),
16#4D# => TO_STDLOGICVECTOR(INIT_4D),
16#4E# => TO_STDLOGICVECTOR(INIT_4E),
16#4F# => TO_STDLOGICVECTOR(INIT_4F),
16#50# => TO_STDLOGICVECTOR(INIT_50),
16#51# => TO_STDLOGICVECTOR(INIT_51),
16#52# => TO_STDLOGICVECTOR(INIT_52),
16#53# => TO_STDLOGICVECTOR(INIT_53),
16#54# => TO_STDLOGICVECTOR(INIT_54),
16#55# => TO_STDLOGICVECTOR(INIT_55),
16#56# => TO_STDLOGICVECTOR(INIT_56),
16#57# => TO_STDLOGICVECTOR(INIT_57)
);
signal ot_sf_limit_low_reg : unsigned(15 downto 0) := "1010111001000000"; --X"AE40";
type adc_statetype is (INIT_STATE, ACQ_STATE, CONV_STATE,
ADC_PRE_END, END_STATE, SINGLE_SEQ_STATE);
type ANALOG_DATA is array (0 to 31) of real;
type DR_data_reg is array (0 to 63) of
std_logic_vector(15 downto 0);
type ACC_ARRAY is array (0 to 31) of integer;
type int_array is array(0 to 31) of integer;
type seq_array is array(32 downto 0 ) of integer;
signal ot_limit_reg : UNSIGNED(15 downto 0) := "1100011110000000";
signal adc_state : adc_statetype := CONV_STATE;
signal next_state : adc_statetype;
signal cfg_reg0 : std_logic_vector(15 downto 0) := "0000000000000000";
signal cfg_reg0_adc : std_logic_vector(15 downto 0) := "0000000000000000";
signal cfg_reg0_seq : std_logic_vector(15 downto 0) := "0000000000000000";
signal cfg_reg1 : std_logic_vector(15 downto 0) := "0000000000000000";
signal cfg_reg1_init : std_logic_vector(15 downto 0) := "0000000000000000";
signal cfg_reg2 : std_logic_vector(15 downto 0) := "0000000000000000";
signal seq1_0 : std_logic_vector(1 downto 0) := "00";
signal curr_seq1_0 : std_logic_vector(1 downto 0) := "00";
signal curr_seq1_0_lat : std_logic_vector(1 downto 0) := "00";
signal busy_r : std_ulogic := '0';
signal busy_r_rst : std_ulogic := '0';
signal busy_rst : std_ulogic := '0';
signal busy_conv : std_ulogic := '0';
signal busy_out_tmp : std_ulogic := '0';
signal busy_out_dly : std_ulogic := '0';
signal busy_out_sync : std_ulogic := '0';
signal busy_out_low_edge : std_ulogic := '0';
signal shorten_acq : integer := 1;
signal busy_seq_rst : std_ulogic := '0';
signal busy_sync1 : std_ulogic := '0';
signal busy_sync2 : std_ulogic := '0';
signal busy_sync_fall : std_ulogic := '0';
signal busy_sync_rise : std_ulogic := '0';
signal cal_chan_update : std_ulogic := '0';
signal first_cal_chan : std_ulogic := '0';
signal seq_reset_flag : std_ulogic := '0';
signal seq_reset_flag_dly : std_ulogic := '0';
signal seq_reset_dly : std_ulogic := '0';
signal seq_reset_busy_out : std_ulogic := '0';
signal rst_in_not_seq : std_ulogic := '0';
signal rst_in_out : std_ulogic := '0';
signal rst_lock_early : std_ulogic := '0';
signal conv_count : integer := 0;
signal acq_count : integer := 1;
signal do_out_rdtmp : std_logic_vector(15 downto 0);
signal rst_in1 : std_ulogic := '0';
signal rst_in2 : std_ulogic := '0';
signal int_rst : std_ulogic := '1';
signal rst_input_t : std_ulogic := '0';
signal rst_in : std_ulogic := '0';
signal ot_en : std_logic := '1';
signal curr_clkdiv_sel : std_logic_vector(7 downto 0)
:= "00000000";
signal curr_clkdiv_sel_int : integer := 0;
signal adcclk : std_ulogic := '0';
signal adcclk_div1 : std_ulogic := '0';
signal sysclk : std_ulogic := '0';
signal curr_adc_resl : std_logic_vector(2 downto 0) := "010";
signal nx_seq : std_logic_vector(15 downto 0) := "0000000000000000";
signal curr_seq : std_logic_vector(15 downto 0) := "0000000000000000";
signal acq_cnt : integer := 0;
signal acq_chan : std_logic_vector(4 downto 0) := "00000";
signal acq_chan_index : integer := 0;
signal acq_chan_lat : std_logic_vector(4 downto 0) := "00000";
signal curr_chan : std_logic_vector(4 downto 0) := "00000";
signal curr_chan_dly : std_logic_vector(4 downto 0) := "00000";
signal curr_chan_lat : std_logic_vector(4 downto 0) := "00000";
signal curr_avg_set : std_logic_vector(1 downto 0) := "00";
signal acq_avg : std_logic_vector(1 downto 0) := "00";
signal curr_e_c : std_logic:= '0';
signal acq_e_c : std_logic:= '0';
signal acq_b_u : std_logic:= '0';
signal curr_b_u : std_logic:= '0';
signal acq_acqsel : std_logic:= '0';
signal curr_acq : std_logic:= '0';
signal seq_cnt : integer := 0;
signal busy_rst_cnt : integer := 0;
signal adc_s1_flag : std_ulogic := '0';
signal adc_convst : std_ulogic := '0';
signal conv_start : std_ulogic := '0';
signal conv_end : std_ulogic := '0';
signal eos_en : std_ulogic := '0';
signal eos_tmp_en : std_ulogic := '0';
signal seq_cnt_en : std_ulogic := '0';
signal eoc_en : std_ulogic := '0';
signal eoc_en_delay : std_ulogic := '0';
signal eoc_out_tmp : std_ulogic := '0';
signal eos_out_tmp : std_ulogic := '0';
signal eoc_out_tmp1 : std_ulogic := '0';
signal eos_out_tmp1 : std_ulogic := '0';
signal eoc_up_data : std_ulogic := '0';
signal eoc_up_alarm : std_ulogic := '0';
signal conv_time : integer := 17;
signal conv_time_cal_1 : integer := 69;
signal conv_time_cal : integer := 69;
signal conv_result : std_logic_vector(15 downto 0) := "0000000000000000";
signal conv_result_reg : std_logic_vector(15 downto 0) := "0000000000000000";
signal data_written : std_logic_vector(15 downto 0) := "0000000000000000";
signal conv_result_int : integer := 0;
signal conv_result_int_resl : integer := 0;
signal analog_in_uni : ANALOG_DATA :=(others=>0.0);
signal analog_in_diff : ANALOG_DATA :=(others=>0.0);
signal analog_in : ANALOG_DATA :=(others=>0.0);
signal analog_in_comm : ANALOG_DATA :=(others=>0.0);
signal chan_val_tmp : ANALOG_DATA :=(others=>0.0);
signal chan_valn_tmp : ANALOG_DATA :=(others=>0.0);
signal data_reg : DR_data_reg
:=( 36 to 39 => "1111111111111111",
others=>"0000000000000000");
signal tmp_data_reg_out : std_logic_vector(15 downto 0) := "0000000000000000";
signal tmp_dr_sram_out : std_logic_vector(15 downto 0) := "0000000000000000";
signal seq_chan_reg1 : std_logic_vector(15 downto 0) := "0000000000000000";
signal seq_chan_reg2 : std_logic_vector(15 downto 0) := "0000000000000000";
signal seq_acq_reg1 : std_logic_vector(15 downto 0) := "0000000000000000";
signal seq_acq_reg2 : std_logic_vector(15 downto 0) := "0000000000000000";
signal seq_avg_reg1 : std_logic_vector(15 downto 0) := "0000000000000000";
signal seq_avg_reg2 : std_logic_vector(15 downto 0) := "0000000000000000";
signal seq_du_reg1 : std_logic_vector(15 downto 0) := "0000000000000000";
signal seq_du_reg2 : std_logic_vector(15 downto 0) := "0000000000000000";
signal seq_count : integer := 1;
signal seq_count_en : std_ulogic := '0';
signal conv_acc : ACC_ARRAY :=(others=>0);
signal conv_avg_count : ACC_ARRAY :=(others=>0);
signal conv_acc_vec : std_logic_vector (20 downto 1);
signal conv_acc_result : std_logic_vector(15 downto 0);
signal seq_status_avg : integer := 0;
signal curr_chan_index : integer := 0;
signal curr_chan_index_lat : integer := 0;
signal conv_avg_cnt : int_array :=(others=>0);
signal analog_mux_in : real := 0.0;
signal adc_temp_result : real := 0.0;
signal adc_intpwr_result : real := 0.0;
signal adc_ext_result : real := 0.0;
signal seq_reset : std_ulogic := '0';
signal seq_en : std_ulogic := '0';
signal seq_en_drp : std_ulogic := '0';
signal seq_en_init : std_ulogic := '0';
signal seq_en_dly : std_ulogic := '0';
signal seq_num : integer := 0;
signal seq_mem : seq_array :=(others=>0);
signal adc_seq_reset : std_ulogic := '0';
signal adc_seq_en : std_ulogic := '0';
signal adc_seq_reset_dly : std_ulogic := '0';
signal adc_seq_en_dly : std_ulogic := '0';
signal adc_seq_reset_hold : std_ulogic := '0';
signal adc_seq_en_hold : std_ulogic := '0';
signal rst_lock : std_ulogic := '1';
signal sim_file_flag : std_ulogic := '0';
signal gsr_in : std_ulogic := '0';
signal convstclk_in : std_ulogic := '0';
signal convst_raw_in : std_ulogic := '0';
signal convst_in : std_ulogic := '0';
signal dclk_in : std_ulogic := '0';
signal den_in : std_ulogic := '0';
signal rst_input : std_ulogic := '0';
signal dwe_in : std_ulogic := '0';
signal di_in : std_logic_vector(15 downto 0) := "0000000000000000";
signal daddr_in : std_logic_vector(6 downto 0) := "0000000";
signal daddr_in_lat : std_logic_vector(6 downto 0) := "0000000";
signal daddr_in_lat_int : integer := 0;
signal drdy_out_tmp1 : std_ulogic := '0';
signal drdy_out_tmp2 : std_ulogic := '0';
signal drdy_out_tmp3 : std_ulogic := '0';
signal drp_update : std_ulogic := '0';
signal alarm_en : std_logic_vector(2 downto 0) := "111";
signal alarm_update : std_ulogic := '0';
signal adcclk_tmp : std_ulogic := '0';
signal ot_out_reg : std_ulogic := '0';
signal alarm_out_reg : std_logic_vector(2 downto 0) := "000";
signal conv_end_reg_read : std_logic_vector(3 downto 0) := "0000";
signal busy_reg_read : std_ulogic := '0';
signal single_chan_conv_end : std_ulogic := '0';
signal first_acq : std_ulogic := '1';
signal conv_start_cont : std_ulogic := '0';
signal conv_start_sel : std_ulogic := '0';
signal reset_conv_start : std_ulogic := '0';
signal reset_conv_start_tmp : std_ulogic := '0';
signal busy_r_rst_done : std_ulogic := '0';
signal op_count : integer := 15;
-- Input/Output Pin signals
signal DI_ipd : std_logic_vector(15 downto 0);
signal DADDR_ipd : std_logic_vector(6 downto 0);
signal DEN_ipd : std_ulogic;
signal DWE_ipd : std_ulogic;
signal DCLK_ipd : std_ulogic;
signal CONVSTCLK_ipd : std_ulogic;
signal RESET_ipd : std_ulogic;
signal CONVST_ipd : std_ulogic;
signal do_out : std_logic_vector(15 downto 0) := "0000000000000000";
signal drdy_out : std_ulogic := '0';
signal ot_out : std_ulogic := '0';
signal alarm_out : std_logic_vector(2 downto 0) := "000";
signal channel_out : std_logic_vector(4 downto 0) := "00000";
signal eoc_out : std_ulogic := '0';
signal eos_out : std_ulogic := '0';
signal busy_out : std_ulogic := '0';
signal DI_dly : std_logic_vector(15 downto 0);
signal DADDR_dly : std_logic_vector(6 downto 0);
signal DEN_dly : std_ulogic;
signal DWE_dly : std_ulogic;
signal DCLK_dly : std_ulogic;
signal CONVSTCLK_dly : std_ulogic;
signal RESET_dly : std_ulogic;
signal CONVST_dly : std_ulogic;
begin
BUSY <= busy_out after 100 ps;
DRDY <= drdy_out after 100 ps;
EOC <= eoc_out after 100 ps;
EOS <= eos_out after 100 ps;
OT <= ot_out after 100 ps;
DO <= do_out after 100 ps;
CHANNEL <= channel_out after 100 ps;
ALM <= alarm_out after 100 ps;
convst_raw_in <= CONVST;
convstclk_in <= CONVSTCLK;
dclk_in <= DCLK;
den_in <= DEN;
rst_input <= RESET;
dwe_in <= DWE;
di_in <= Di;
daddr_in <= DADDR;
gsr_in <= GSR;
convst_in <= '1' when (convst_raw_in = '1' or convstclk_in = '1') else '0';
JTAGLOCKED <= '0';
JTAGMODIFIED <= '0';
JTAGBUSY <= '0';
DEFAULT_CHECK : process
variable init40h_tmp : std_logic_vector(15 downto 0);
variable init41h_tmp : std_logic_vector(15 downto 0);
variable init42h_tmp : std_logic_vector(15 downto 0);
variable init4eh_tmp : std_logic_vector(15 downto 0);
variable init40h_tmp_chan : integer;
variable init42h_tmp_clk : integer;
variable tmp_value : std_logic_vector(7 downto 0);
begin
init40h_tmp := TO_STDLOGICVECTOR(INIT_40);
init40h_tmp_chan := SLV_TO_INT(SLV=>init40h_tmp(4 downto 0));
init41h_tmp := TO_STDLOGICVECTOR(INIT_41);
init42h_tmp := TO_STDLOGICVECTOR(INIT_42);
tmp_value := init42h_tmp(15 downto 8);
init42h_tmp_clk := SLV_TO_INT(SLV=>tmp_value);
init4eh_tmp := TO_STDLOGICVECTOR(INIT_4E);
if ((init41h_tmp(13 downto 12)="11") and (init40h_tmp(8)='1') and (init40h_tmp_chan /= 3 ) and (init40h_tmp_chan < 16)) then
assert false report " Attribute Syntax warning : The attribute INIT_40 bit[8] must be set to 0 on SYSMON. Long acquistion mode is only allowed for external channels."
severity warning;
end if;
if ((init41h_tmp(13 downto 12) /="11") and (init4eh_tmp(10 downto 0) /= "00000000000") and (init4eh_tmp(15 downto 12) /= "0000")) then
assert false report " Attribute Syntax warning : The attribute INIT_4E Bit[15:12] and bit[10:0] must be set to 0. Long acquistion mode is only allowed for external channels."
severity warning;
end if;
if ((init41h_tmp(13 downto 12)="11") and (init40h_tmp(9) = '1') and (init40h_tmp(4 downto 0) /= "00011") and (init40h_tmp_chan < 16)) then
assert false report " Attribute Syntax warning : The attribute INIT_40 bit[9] must be set to 0 on SYSMON. Event mode timing can only be used with external channels, and only in single channel mode."
severity warning;
end if;
if ((init41h_tmp(13 downto 12)="11") and (init40h_tmp(13 downto 12) /= "00") and (INIT_48 /=X"0000") and (INIT_49 /= X"0000")) then
assert false report " Attribute Syntax warning : The attribute INIT_48 and INIT_49 must be set to 0000h in single channel mode and averaging enabled."
severity warning;
end if;
if (init42h_tmp(1 downto 0) /= "00") then
assert false report
" Attribute Syntax Error : The attribute INIT_42 Bit[1:0] must be set to 00."
severity Error;
end if;
if (init42h_tmp_clk < 8) then
assert false report
" Attribute Syntax Error : The attribute INIT_42 Bit[15:8] is the ADC Clock divider and must be equal or greater than 8."
severity failure;
end if;
if (INIT_43 /= "0000000000000000") then
assert false report
" Warning : The attribute INIT_43 must be set to 0000."
severity warning;
end if;
if (INIT_44 /= "0000000000000000") then
assert false report
" Warning : The attribute INIT_44 must be set to 0000."
severity warning;
end if;
if (INIT_45 /= "0000000000000000") then
assert false report
" Warning : The attribute INIT_45 must be set to 0000."
severity warning;
end if;
if (INIT_46 /= "0000000000000000") then
assert false report
" Warning : The attribute INIT_46 must be set to 0000."
severity warning;
end if;
if (INIT_47 /= "0000000000000000") then
assert false report
" Warning : The attribute INIT_47 must be set to 0000."
severity warning;
end if;
wait;
end process;
curr_chan_index <= SLV_TO_INT(curr_chan);
curr_chan_index_lat <= SLV_TO_INT(curr_chan_lat);
CHEK_COMM_P : process( busy_r )
variable Message : line;
begin
if (busy_r'event and busy_r = '1' ) then
if (rst_in = '0' and acq_b_u = '0' and ((acq_chan_index = 3) or (acq_chan_index >= 16 and acq_chan_index <= 31))) then
if ( chan_valn_tmp(acq_chan_index) > chan_val_tmp(acq_chan_index)) then
Write ( Message, string'("Input File Warning: The N input for external channel "));
Write ( Message, acq_chan_index);
Write ( Message, string'(" must be smaller than P input when in unipolar mode (P="));
Write ( Message, chan_val_tmp(acq_chan_index));
Write ( Message, string'(" N="));
Write ( Message, chan_valn_tmp(acq_chan_index));
Write ( Message, string'(") for SYSMON."));
assert false report Message.all severity warning;
DEALLOCATE (Message);
end if;
if (( chan_valn_tmp(acq_chan_index) > 0.5) or (chan_valn_tmp(acq_chan_index) < 0.0)) then
Write ( Message, string'("Input File Warning: The N input for external channel "));
Write ( Message, acq_chan_index);
Write ( Message, string'(" should be between 0V to 0.5V when in unipolar mode (N="));
Write ( Message, chan_valn_tmp(acq_chan_index));
Write ( Message, string'(") for SYSMON."));
assert false report Message.all severity warning;
DEALLOCATE (Message);
end if;
end if;
end if;
end process;
busy_mkup_p : process( dclk_in, rst_in_out)
begin
if (rst_in_out = '1') then
busy_rst <= '1';
rst_lock <= '1';
rst_lock_early <= '1';
busy_rst_cnt <= 0;
elsif (rising_edge(dclk_in)) then
if (rst_lock = '1') then
if (busy_rst_cnt < 29) then
busy_rst_cnt <= busy_rst_cnt + 1;
if ( busy_rst_cnt = 26) then
rst_lock_early <= '0';
end if;
else
busy_rst <= '0';
rst_lock <= '0';
end if;
end if;
end if;
end process;
busy_out_p : process (busy_rst, busy_conv, rst_lock)
begin
if (rst_lock = '1') then
busy_out <= busy_rst;
else
busy_out <= busy_conv;
end if;
end process;
busy_conv_p : process (dclk_in, rst_in)
begin
if (rst_in = '1') then
busy_conv <= '0';
cal_chan_update <= '0';
elsif (rising_edge(dclk_in)) then
if (seq_reset_flag = '1' and curr_clkdiv_sel_int <= 3) then
busy_conv <= busy_seq_rst;
elsif (busy_sync_fall = '1') then
busy_conv <= '0';
elsif (busy_sync_rise = '1') then
busy_conv <= '1';
end if;
if (conv_count = 21 and curr_chan = "01000" ) then
cal_chan_update <= '1';
else
cal_chan_update <= '0';
end if;
end if;
end process;
busy_sync_p : process (dclk_in, rst_lock)
begin
if (rst_lock = '1') then
busy_sync1 <= '0';
busy_sync2 <= '0';
elsif (rising_edge (dclk_in)) then
busy_sync1 <= busy_r;
busy_sync2 <= busy_sync1;
end if;
end process;
busy_sync_fall <= '1' when (busy_r = '0' and busy_sync1 = '1') else '0';
busy_sync_rise <= '1' when (busy_sync1 = '1' and busy_sync2 = '0') else '0';
busy_seq_rst_p : process
variable tmp_uns_div : unsigned(7 downto 0);
begin
if (falling_edge(busy_out) or rising_edge(busy_r)) then
if (seq_reset_flag = '1' and seq1_0 = "00" and curr_clkdiv_sel_int <= 3) then
wait until (rising_edge(dclk_in));
wait until (rising_edge(dclk_in));
wait until (rising_edge(dclk_in));
wait until (rising_edge(dclk_in));
wait until (rising_edge(dclk_in));
busy_seq_rst <= '1';
elsif (seq_reset_flag = '1' and seq1_0 /= "00" and curr_clkdiv_sel_int <= 3) then
wait until (rising_edge(dclk_in));
wait until (rising_edge(dclk_in));
wait until (rising_edge(dclk_in));
wait until (rising_edge(dclk_in));
wait until (rising_edge(dclk_in));
wait until (rising_edge(dclk_in));
wait until (rising_edge(dclk_in));
busy_seq_rst <= '1';
else
busy_seq_rst <= '0';
end if;
end if;
wait on busy_out, busy_r;
end process;
chan_out_p : process(busy_out, rst_in_out, cal_chan_update)
begin
if (rst_in_out = '1') then
channel_out <= "00000";
elsif (rising_edge(busy_out) or rising_edge(cal_chan_update)) then
if ( busy_out = '1' and cal_chan_update = '1') then
channel_out <= "01000";
end if;
elsif (falling_edge(busy_out)) then
channel_out <= curr_chan;
curr_chan_lat <= curr_chan;
end if;
end process;
INT_RST_GEN_P : process
begin
int_rst <= '1';
wait until (rising_edge(dclk_in));
wait until (rising_edge(dclk_in));
int_rst <= '0';
wait;
end process;
rst_input_t <= rst_input or int_rst;
RST_DE_SYNC_P: process(dclk_in, rst_input_t)
begin
if (rst_input_t = '1') then
rst_in2 <= '1';
rst_in1 <= '1';
elsif (dclk_in'event and dclk_in='1') then
rst_in2 <= rst_in1;
rst_in1 <= rst_input_t;
end if;
end process;
rst_in_not_seq <= rst_in2;
rst_in <= rst_in2 or seq_reset_dly;
rst_in_out <= rst_in2 or seq_reset_busy_out;
seq_reset_dly_p : process
begin
if (rising_edge(seq_reset)) then
wait until rising_edge(dclk_in);
wait until rising_edge(dclk_in);
seq_reset_dly <= '1';
wait until rising_edge(dclk_in);
wait until falling_edge(dclk_in);
seq_reset_busy_out <= '1';
wait until rising_edge(dclk_in);
wait until rising_edge(dclk_in);
wait until rising_edge(dclk_in);
seq_reset_dly <= '0';
seq_reset_busy_out <= '0';
end if;
wait on seq_reset, dclk_in;
end process;
seq_reset_flag_p : process (seq_reset_dly, busy_r)
begin
if (rising_edge(seq_reset_dly)) then
seq_reset_flag <= '1';
elsif (rising_edge(busy_r)) then
seq_reset_flag <= '0';
end if;
end process;
seq_reset_flag_dly_p : process (seq_reset_flag, busy_out)
begin
if (rising_edge(seq_reset_flag)) then
seq_reset_flag_dly <= '1';
elsif (rising_edge(busy_out)) then
seq_reset_flag_dly <= '0';
end if;
end process;
first_cal_chan_p : process ( busy_out)
begin
if (rising_edge(busy_out )) then
if (seq_reset_flag_dly = '1' and acq_chan = "01000" and seq1_0 = "00") then
first_cal_chan <= '1';
else
first_cal_chan <= '0';
end if;
end if;
end process;
ADC_SM: process (adcclk, rst_in, sim_file_flag)
begin
if (sim_file_flag = '1') then
adc_state <= INIT_STATE;
elsif (rst_in = '1' or rst_lock_early = '1') then
adc_state <= INIT_STATE;
elsif (adcclk'event and adcclk = '1') then
adc_state <= next_state;
end if;
end process;
next_state_p : process (adc_state, eos_en, conv_start , conv_end, curr_seq1_0_lat)
begin
case (adc_state) is
when INIT_STATE => next_state <= ACQ_STATE;
when ACQ_STATE => if (conv_start = '1') then
next_state <= CONV_STATE;
else
next_state <= ACQ_STATE;
end if;
when CONV_STATE => if (conv_end = '1') then
next_state <= END_STATE;
else
next_state <= CONV_STATE;
end if;
when END_STATE => if (curr_seq1_0_lat = "01") then
if (eos_en = '1') then
next_state <= SINGLE_SEQ_STATE;
else
next_state <= ACQ_STATE;
end if;
else
next_state <= ACQ_STATE;
end if;
when SINGLE_SEQ_STATE => next_state <= INIT_STATE;
when others => next_state <= INIT_STATE;
end case;
end process;
seq_en_init_p : process
begin
seq_en_init <= '0';
if (cfg_reg1_init(13 downto 12) /= "11" ) then
wait for 20 ps;
seq_en_init <= '1';
wait for 150 ps;
seq_en_init <= '0';
end if;
wait;
end process;
seq_en <= seq_en_init or seq_en_drp;
DRPORT_DO_OUT_P : process(dclk_in, gsr_in)
variable message : line;
variable di_str : string (16 downto 1);
variable daddr_str : string (7 downto 1);
variable di_40 : std_logic_vector(4 downto 0);
variable valid_daddr : boolean := false;
variable address : integer;
variable tmp_value : integer := 0;
variable tmp_value1 : std_logic_vector (7 downto 0);
begin
if (gsr_in = '1') then
drdy_out <= '0';
daddr_in_lat <= "0000000";
do_out <= "0000000000000000";
elsif (rising_edge(dclk_in)) then
if (den_in = '1') then
valid_daddr := addr_is_valid(daddr_in);
if (valid_daddr) then
address := slv_to_int(daddr_in);
if ( (address > 88 or
(address >= 13 and address <= 15)
or (address >= 39 and address <= 63))) then
Write ( Message, string'(" Invalid Input Warning : The DADDR "));
Write ( Message, string'(SLV_TO_STR(daddr_in)));
Write ( Message, string'(" is not defined. The data in this location is invalid."));
assert false report Message.all severity warning;
DEALLOCATE(Message);
end if;
end if;
if (drdy_out_tmp1 = '1' or drdy_out_tmp2 = '1' or drdy_out_tmp3 = '1') then
drdy_out_tmp1 <= '0';
else
drdy_out_tmp1 <= '1';
end if;
daddr_in_lat <= daddr_in;
else
drdy_out_tmp1 <= '0';
end if;
drdy_out_tmp2 <= drdy_out_tmp1;
drdy_out_tmp3 <= drdy_out_tmp2;
drdy_out <= drdy_out_tmp3;
if (drdy_out_tmp3 = '1') then
do_out <= do_out_rdtmp;
end if;
-- write all available daddr addresses
if (dwe_in = '1' and den_in = '1') then
if (valid_daddr) then
dr_sram(address) <= di_in;
end if;
if ( address = 42 and di_in( 1 downto 0) /= "00") then
Write ( Message, string'(" Invalid Input Error : The DI bit[1:0] "));
Write ( Message, bit_vector'(TO_BITVECTOR(di_in(1 downto 0))));
Write ( Message, string'(" at DADDR "));
Write ( Message, bit_vector'(TO_BITVECTOR(daddr_in)));
Write ( Message, string'(" of SYSMON is invalid. These must be set to 00."));
assert false report Message.all severity error;
end if;
tmp_value1 := di_in(15 downto 8) ;
tmp_value := SLV_TO_INT(SLV=>tmp_value1);
if ( address = 42 and tmp_value < 8) then
Write ( Message, string'(" Invalid Input Error : The DI bit[15:8] "));
Write ( Message, bit_vector'(TO_BITVECTOR(di_in(15 downto 8))));
Write ( Message, string'(" at DADDR "));
Write ( Message, bit_vector'(TO_BITVECTOR(daddr_in)));
Write ( Message, string'(" of SYSMON is invalid. Bit[15:8] of Control Register 42h is the ADC Clock divider and must be equal or greater than 8."));
assert false report Message.all severity failure;
end if;
if ( (address >= 43 and address <= 47) and di_in(15 downto 0) /= "0000000000000000") then
Write ( Message, string'(" Invalid Input Error : The DI value "));
Write ( Message, bit_vector'(TO_BITVECTOR(di_in)));
Write ( Message, string'(" at DADDR "));
Write ( Message, bit_vector'(TO_BITVECTOR(daddr_in)));
Write ( Message, string'(" of SYSMON is invalid. These must be set to 0000."));
assert false report Message.all severity error;
DEALLOCATE(Message);
end if;
tmp_value := SLV_TO_INT(SLV=>di_in(4 downto 0));
if (address = 40) then
if (((tmp_value = 6) or ( tmp_value = 7) or ((tmp_value >= 10) and (tmp_value <= 15)))) then
Write ( Message, string'(" Invalid Input Warning : The DI bit[4:0] at DADDR "));
Write ( Message, bit_vector'(TO_BITVECTOR(daddr_in)));
Write ( Message, string'(" is "));
Write ( Message, bit_vector'(TO_BITVECTOR(di_in(4 downto 0))));
Write ( Message, string'(", which is invalid analog channel."));
assert false report Message.all severity warning;
DEALLOCATE(Message);
end if;
if ((cfg_reg1(13 downto 12)="11") and (di_in(8)='1') and (tmp_value /= 3) and (tmp_value < 16)) then
Write ( Message, string'(" Invalid Input Warning : The DI value is "));
Write ( Message, bit_vector'(TO_BITVECTOR(di_in)));
Write ( Message, string'(" at DADDR "));
Write ( Message, bit_vector'(TO_BITVECTOR(daddr_in)));
Write ( Message, string'(". Bit[8] of DI must be set to 0. Long acquistion mode is only allowed for external channels."));
assert false report Message.all severity warning;
DEALLOCATE(Message);
end if;
if ((cfg_reg1(13 downto 12)="11") and (di_in(9)='1') and (tmp_value /= 3) and (tmp_value < 16)) then
Write ( Message, string'(" Invalid Input Warning : The DI value is "));
Write ( Message, bit_vector'(TO_BITVECTOR(di_in)));
Write ( Message, string'(" at DADDR "));
Write ( Message, bit_vector'(TO_BITVECTOR(daddr_in)));
Write ( Message, string'(". Bit[9] of DI must be set to 0. Event mode timing can only be used with external channels."));
assert false report Message.all severity warning;
DEALLOCATE(Message);
end if;
if ((cfg_reg1(13 downto 12)="11") and (di_in(13 downto 12)/="00") and (seq_chan_reg1 /= X"0000") and (seq_chan_reg2 /= X"0000")) then
Write ( Message, string'(" Invalid Input Warning : The Control Regiter 48h and 49h are "));
Write ( Message, bit_vector'(TO_BITVECTOR(seq_chan_reg1)));
Write ( Message, string'(" and "));
Write ( Message, bit_vector'(TO_BITVECTOR(seq_chan_reg2)));
Write ( Message, string'(". Those registers should be set to 0000h in single channel mode and averaging enabled."));
assert false report Message.all severity warning;
DEALLOCATE(Message);
end if;
end if;
tmp_value := SLV_TO_INT(SLV=>cfg_reg0(4 downto 0));
if (address = 41) then
if ((di_in(13 downto 12)="11") and (cfg_reg0(8)='1') and (tmp_value /= 3) and (tmp_value < 16)) then
Write ( Message, string'(" Invalid Input Warning : The Control Regiter 40h value is "));
Write ( Message, bit_vector'(TO_BITVECTOR(cfg_reg0)));
Write ( Message, string'(". Bit[8] of Control Regiter 40h must be set to 0. Long acquistion mode is only allowed for external channels."));
assert false report Message.all severity warning;
DEALLOCATE(Message);
end if;
if ((di_in(13 downto 12)="11") and (cfg_reg0(9)='1') and (tmp_value /= 3) and (tmp_value < 16)) then
Write ( Message, string'(" Invalid Input Warning : The Control Regiter 40h value is "));
Write ( Message, bit_vector'(TO_BITVECTOR(cfg_reg0)));
Write ( Message, string'(". Bit[9] of Control Regiter 40h must be set to 0. Event mode timing can only be used with external channels."));
assert false report Message.all severity warning;
DEALLOCATE(Message);
end if;
if ((di_in(13 downto 12) /= "11") and (seq_acq_reg1(10 downto 0) /= "00000000000") and (seq_acq_reg1(15 downto 12) /= "0000")) then
Write ( Message, string'(" Invalid Input Warning : The Control Regiter 4Eh is "));
Write ( Message, bit_vector'(TO_BITVECTOR(seq_acq_reg1)));
Write ( Message, string'(". Bit[15:12] and bit[10:0] of this register must be set to 0. Long acquistion mode is only allowed for external channels."));
assert false report Message.all severity warning;
DEALLOCATE(Message);
end if;
if ((di_in(13 downto 12) = "11") and (cfg_reg0(13 downto 12) /= "00") and (seq_chan_reg1 /= X"0000") and (seq_chan_reg2 /= X"0000")) then
Write ( Message, string'(" Invalid Input Warning : The Control Regiter 48h and 49h are "));
Write ( Message, bit_vector'(TO_BITVECTOR(seq_chan_reg1)));
Write ( Message, string'(" and "));
Write ( Message, bit_vector'(TO_BITVECTOR(seq_chan_reg2)));
Write ( Message, string'(". Those registers should be set to 0000h in single channel mode and averaging enabled."));
assert false report Message.all severity warning;
DEALLOCATE(Message);
end if;
end if;
end if;
if (daddr_in = "1000001" ) then
if (dwe_in = '1' and den_in = '1') then
if (di_in(13 downto 12) /= cfg_reg1(13 downto 12)) then
seq_reset <= '1';
else
seq_reset <= '0';
end if;
if (di_in(13 downto 12) /= "11" ) then
seq_en_drp <= '1';
else
seq_en_drp <= '0';
end if;
else
seq_reset <= '0';
seq_en_drp <= '0';
end if;
else
seq_reset <= '0';
seq_en_drp <= '0';
end if;
end if;
end process;
tmp_dr_sram_out <= dr_sram(daddr_in_lat_int) when (daddr_in_lat_int >= 64 and
daddr_in_lat_int <= 87) else "0000000000000000";
tmp_data_reg_out <= data_reg(daddr_in_lat_int) when (daddr_in_lat_int >= 0 and
daddr_in_lat_int <= 38) else "0000000000000000";
do_out_rdtmp_p : process( daddr_in_lat, tmp_data_reg_out, tmp_dr_sram_out )
variable Message : line;
variable valid_daddr : boolean := false;
begin
valid_daddr := addr_is_valid(daddr_in_lat);
daddr_in_lat_int <= slv_to_int(daddr_in_lat);
if (valid_daddr) then
if ((daddr_in_lat_int > 88) or
(daddr_in_lat_int >= 13 and daddr_in_lat_int <= 15)
or (daddr_in_lat_int >= 39 and daddr_in_lat_int <= 63)) then
do_out_rdtmp <= "XXXXXXXXXXXXXXXX";
end if;
if ((daddr_in_lat_int >= 0 and daddr_in_lat_int <= 12) or
(daddr_in_lat_int >= 16 and daddr_in_lat_int <= 38)) then
do_out_rdtmp <= tmp_data_reg_out;
elsif (daddr_in_lat_int >= 64 and daddr_in_lat_int <= 87) then
do_out_rdtmp <= tmp_dr_sram_out;
end if;
end if;
end process;
-- end DRP RAM
cfg_reg0 <= dr_sram(16#40#);
cfg_reg1 <= dr_sram(16#41#);
cfg_reg2 <= dr_sram(16#42#);
seq_chan_reg1 <= dr_sram(16#48#);
seq_chan_reg2 <= dr_sram(16#49#);
seq_avg_reg1 <= dr_sram(16#4A#);
seq_avg_reg2 <= dr_sram(16#4B#);
seq_du_reg1 <= dr_sram(16#4C#);
seq_du_reg2 <= dr_sram(16#4D#);
seq_acq_reg1 <= dr_sram(16#4E#);
seq_acq_reg2 <= dr_sram(16#4F#);
seq1_0 <= cfg_reg1(13 downto 12);
drp_update_p : process
variable seq_bits : std_logic_vector( 1 downto 0);
begin
if (rst_in = '1') then
wait until (rising_edge(dclk_in));
wait until (rising_edge(dclk_in));
seq_bits := seq1_0;
elsif (rising_edge(drp_update)) then
seq_bits := curr_seq1_0;
end if;
if (rising_edge(drp_update) or (rst_in = '1')) then
if (seq_bits = "00") then
alarm_en <= "000";
ot_en <= '1';
else
ot_en <= not cfg_reg1(0);
alarm_en <= not cfg_reg1(3 downto 1);
end if;
end if;
wait on drp_update, rst_in;
end process;
-- Clock divider, generate and adcclk
sysclk_p : process(dclk_in)
begin
if (rising_edge(dclk_in)) then
sysclk <= not sysclk;
end if;
end process;
curr_clkdiv_sel_int_p : process (curr_clkdiv_sel)
begin
curr_clkdiv_sel_int <= SLV_TO_INT(curr_clkdiv_sel);
end process;
clk_count_p : process(dclk_in)
variable clk_count : integer := -1;
begin
if (rising_edge(dclk_in)) then
if (curr_clkdiv_sel_int > 2 ) then
if (clk_count >= curr_clkdiv_sel_int - 1) then
clk_count := 0;
else
clk_count := clk_count + 1;
end if;
if (clk_count > (curr_clkdiv_sel_int/2) - 1) then
adcclk_tmp <= '1';
else
adcclk_tmp <= '0';
end if;
else
adcclk_tmp <= not adcclk_tmp;
end if;
end if;
end process;
curr_clkdiv_sel <= cfg_reg2(15 downto 8);
adcclk_div1 <= '0' when (curr_clkdiv_sel_int > 1) else '1';
adcclk <= not sysclk when adcclk_div1 = '1' else adcclk_tmp;
-- end clock divider
-- latch configuration registers
acq_latch_p : process ( seq1_0, adc_s1_flag, curr_seq, cfg_reg0_adc, rst_in)
begin
if ((seq1_0 = "01" and adc_s1_flag = '0') or seq1_0 = "10") then
acq_acqsel <= curr_seq(8);
elsif (seq1_0 = "11") then
acq_acqsel <= cfg_reg0_adc(8);
else
acq_acqsel <= '0';
end if;
if (rst_in = '0') then
if (seq1_0 /= "11" and adc_s1_flag = '0') then
acq_avg <= curr_seq(13 downto 12);
acq_chan <= curr_seq(4 downto 0);
acq_b_u <= curr_seq(10);
else
acq_avg <= cfg_reg0_adc(13 downto 12);
acq_chan <= cfg_reg0_adc(4 downto 0);
acq_b_u <= cfg_reg0_adc(10);
end if;
end if;
end process;
acq_chan_index <= SLV_TO_INT(acq_chan);
conv_end_reg_read_P : process ( adcclk, rst_in)
begin
if (rst_in = '1') then
conv_end_reg_read <= "0000";
elsif (rising_edge(adcclk)) then
conv_end_reg_read(3 downto 1) <= conv_end_reg_read(2 downto 0);
conv_end_reg_read(0) <= single_chan_conv_end or conv_end;
end if;
end process;
-- synch to DCLK
busy_reg_read_P : process ( dclk_in, rst_in)
begin
if (rst_in = '1') then
busy_reg_read <= '1';
elsif (rising_edge(dclk_in)) then
busy_reg_read <= not conv_end_reg_read(2);
end if;
end process;
cfg_reg0_adc_P : process
variable first_after_reset : std_ulogic := '1';
begin
if (rst_in='1') then
cfg_reg0_seq <= X"0000";
cfg_reg0_adc <= X"0000";
acq_e_c <= '0';
first_after_reset := '1';
elsif (falling_edge(busy_reg_read) or falling_edge(rst_in)) then
wait until (rising_edge(dclk_in));
wait until (rising_edge(dclk_in));
wait until (rising_edge(dclk_in));
if (first_after_reset = '1') then
first_after_reset := '0';
cfg_reg0_adc <= cfg_reg0;
cfg_reg0_seq <= cfg_reg0;
else
cfg_reg0_adc <= cfg_reg0_seq;
cfg_reg0_seq <= cfg_reg0;
end if;
acq_e_c <= cfg_reg0(9);
end if;
wait on busy_reg_read, rst_in;
end process;
busy_r_p : process(conv_start, busy_r_rst, rst_in)
begin
if (rst_in = '1') then
busy_r <= '0';
elsif (rising_edge(conv_start) and rst_lock = '0') then
busy_r <= '1';
elsif (rising_edge(busy_r_rst)) then
busy_r <= '0';
end if;
end process;
curr_seq1_0_p : process( busy_out)
begin
if (falling_edge( busy_out)) then
if (adc_s1_flag = '1') then
curr_seq1_0 <= "00";
else
curr_seq1_0 <= seq1_0;
end if;
end if;
end process;
start_conv_p : process ( conv_start, rst_in)
variable Message : line;
begin
if (rst_in = '1') then
analog_mux_in <= 0.0;
curr_chan <= "00000";
elsif (rising_edge(conv_start)) then
if ( ((acq_chan_index = 3) or (acq_chan_index >= 16 and acq_chan_index <= 31))) then
analog_mux_in <= analog_in_diff(acq_chan_index);
else
analog_mux_in <= analog_in_uni(acq_chan_index);
end if;
curr_chan <= acq_chan;
curr_seq1_0_lat <= curr_seq1_0;
if (acq_chan_index = 6 or acq_chan_index = 7 or (acq_chan_index >= 10 and acq_chan_index <= 15)) then
Write ( Message, string'(" Invalid Input Warning : The analog channel "));
Write ( Message, acq_chan_index);
Write ( Message, string'(" to SYSMON is invalid."));
assert false report Message.all severity warning;
end if;
if ((seq1_0 = "01" and adc_s1_flag = '0') or seq1_0 = "10" or seq1_0 = "00") then
curr_avg_set <= curr_seq(13 downto 12);
curr_b_u <= curr_seq(10);
curr_e_c <= '0';
curr_acq <= curr_seq(8);
else
curr_avg_set <= acq_avg;
curr_b_u <= acq_b_u;
curr_e_c <= cfg_reg0(9);
curr_acq <= cfg_reg0(8);
end if;
end if;
end process;
-- end latch configuration registers
-- sequence control
seq_en_dly <= seq_en after 1 ps;
seq_num_p : process(seq_en_dly)
variable seq_num_tmp : integer := 0;
variable si_tmp : integer := 0;
variable si : integer := 0;
begin
if (rising_edge(seq_en_dly)) then
if (seq1_0 = "01" or seq1_0 = "10") then
seq_num_tmp := 0;
for I in 0 to 15 loop
si := I;
if (seq_chan_reg1(si) = '1') then
seq_num_tmp := seq_num_tmp + 1;
seq_mem(seq_num_tmp) <= si;
end if;
end loop;
for I in 16 to 31 loop
si := I;
si_tmp := si-16;
if (seq_chan_reg2(si_tmp) = '1') then
seq_num_tmp := seq_num_tmp + 1;
seq_mem(seq_num_tmp) <= si;
end if;
end loop;
seq_num <= seq_num_tmp;
elsif (seq1_0 = "00") then
seq_num <= 4;
seq_mem(1) <= 0;
seq_mem(2) <= 8;
seq_mem(3) <= 9;
seq_mem(4) <= 10;
end if;
end if;
end process;
curr_seq_p : process(seq_count, seq_en_dly)
variable seq_curr_i : std_logic_vector(4 downto 0);
variable seq_curr_index : integer;
variable tmp_value : integer;
variable curr_seq_tmp : std_logic_vector(15 downto 0);
begin
if (seq_count'event or falling_edge(seq_en_dly)) then
seq_curr_index := seq_mem(seq_count);
seq_curr_i := STD_LOGIC_VECTOR(TO_UNSIGNED(seq_curr_index, 5));
curr_seq_tmp := "0000000000000000";
if (seq_curr_index >= 0 and seq_curr_index <= 15) then
curr_seq_tmp(2 downto 0) := seq_curr_i(2 downto 0);
curr_seq_tmp(4 downto 3) := "01";
curr_seq_tmp(8) := seq_acq_reg1(seq_curr_index);
curr_seq_tmp(10) := seq_du_reg1(seq_curr_index);
if (seq1_0 = "00") then
curr_seq_tmp(13 downto 12) := "01";
elsif (seq_avg_reg1(seq_curr_index) = '1') then
curr_seq_tmp(13 downto 12) := cfg_reg0(13 downto 12);
else
curr_seq_tmp(13 downto 12) := "00";
end if;
if (seq_curr_index >= 0 and seq_curr_index <= 7) then
curr_seq_tmp(4 downto 3) := "01";
else
curr_seq_tmp(4 downto 3) := "00";
end if;
elsif (seq_curr_index >= 16 and seq_curr_index <= 31) then
tmp_value := seq_curr_index -16;
curr_seq_tmp(4 downto 0) := seq_curr_i;
curr_seq_tmp(8) := seq_acq_reg2(tmp_value);
curr_seq_tmp(10) := seq_du_reg2(tmp_value);
if (seq_avg_reg2(tmp_value) = '1') then
curr_seq_tmp(13 downto 12) := cfg_reg0(13 downto 12);
else
curr_seq_tmp(13 downto 12) := "00";
end if;
end if;
curr_seq <= curr_seq_tmp;
end if;
end process;
eos_en_p : process (adcclk, rst_in)
begin
if (rst_in = '1') then
seq_count <= 1;
eos_en <= '0';
elsif (rising_edge(adcclk)) then
if ((seq_count = seq_num ) and (adc_state = CONV_STATE and next_state = END_STATE)
and (curr_seq1_0_lat /= "11") and rst_lock = '0') then
eos_tmp_en <= '1';
else
eos_tmp_en <= '0';
end if;
if ((eos_tmp_en = '1') and (seq_status_avg = 0)) then
eos_en <= '1';
else
eos_en <= '0';
end if;
if (eos_tmp_en = '1' or curr_seq1_0_lat = "11") then
seq_count <= 1;
elsif (seq_count_en = '1' ) then
if (seq_count >= 32) then
seq_count <= 1;
else
seq_count <= seq_count +1;
end if;
end if;
end if;
end process;
-- end sequence control
-- Acquisition
busy_out_dly <= busy_out after 10 ps;
short_acq_p : process(adc_state, rst_in, first_acq)
begin
if (rst_in = '1') then
shorten_acq <= 0;
elsif (adc_state'event or first_acq'event) then
if ((busy_out_dly = '0') and (adc_state=ACQ_STATE) and (first_acq='1')) then
shorten_acq <= 1;
else
shorten_acq <= 0;
end if;
end if;
end process;
acq_count_p : process (adcclk, rst_in)
begin
if (rst_in = '1') then
acq_count <= 1;
first_acq <= '1';
elsif (rising_edge(adcclk)) then
if (adc_state = ACQ_STATE and rst_lock = '0' and acq_e_c = '0') then
first_acq <= '0';
if (acq_acqsel = '1') then
if (acq_count <= 11) then
acq_count <= acq_count + 1 + shorten_acq;
end if;
else
if (acq_count <= 4) then
acq_count <= acq_count + 1 + shorten_acq;
end if;
end if;
if (next_state = CONV_STATE) then
if ((acq_acqsel = '1' and acq_count < 10) or (acq_acqsel = '0' and acq_count < 4)) then
assert false report "Warning: Acquisition time not enough for SYSMON."
severity warning;
end if;
end if;
else
if (first_acq = '1') then
acq_count <= 1;
else
acq_count <= 0;
end if;
end if;
end if;
end process;
conv_start_con_p: process(adc_state, acq_acqsel, acq_count)
begin
if (adc_state = ACQ_STATE) then
if (rst_lock = '0') then
if ((seq_reset_flag = '0' or (seq_reset_flag = '1' and curr_clkdiv_sel_int > 3))
and ((acq_acqsel = '1' and acq_count > 10) or (acq_acqsel = '0' and acq_count > 4))) then
conv_start_cont <= '1';
else
conv_start_cont <= '0';
end if;
end if;
else
conv_start_cont <= '0';
end if;
end process;
conv_start_sel <= convst_in when (acq_e_c = '1') else conv_start_cont;
reset_conv_start_tmp <= '1' when (conv_count=2) else '0';
reset_conv_start <= rst_in or reset_conv_start_tmp;
conv_start_p : process(conv_start_sel, reset_conv_start)
begin
if (reset_conv_start ='1') then
conv_start <= '0';
elsif (rising_edge(conv_start_sel)) then
conv_start <= '1';
end if;
end process;
-- end acquisition
-- Conversion
conv_result_p : process (adc_state, next_state, curr_chan, curr_chan_index, analog_mux_in, curr_b_u)
variable conv_result_int_i : integer := 0;
variable conv_result_int_tmp : integer := 0;
variable conv_result_int_tmp_rl : real := 0.0;
variable adc_analog_tmp : real := 0.0;
begin
if ((adc_state = CONV_STATE and next_state = END_STATE) or adc_state = END_STATE) then
if (curr_chan = "00000") then -- temperature conversion
adc_analog_tmp := (analog_mux_in + 273.0) * 130.0382;
adc_temp_result <= adc_analog_tmp;
if (adc_analog_tmp >= 65535.0) then
conv_result_int_i := 65535;
elsif (adc_analog_tmp < 0.0) then
conv_result_int_i := 0;
else
conv_result_int_tmp := real2int(adc_analog_tmp);
conv_result_int_tmp_rl := int2real(conv_result_int_tmp);
if (adc_analog_tmp - conv_result_int_tmp_rl > 0.9999) then
conv_result_int_i := conv_result_int_tmp + 1;
else
conv_result_int_i := conv_result_int_tmp;
end if;
end if;
conv_result_int <= conv_result_int_i;
conv_result <= STD_LOGIC_VECTOR(TO_UNSIGNED(conv_result_int_i, 16));
elsif (curr_chan = "00001" or curr_chan = "00010") then -- internal power conversion
adc_analog_tmp := analog_mux_in * 65536.0 / 3.0;
adc_intpwr_result <= adc_analog_tmp;
if (adc_analog_tmp >= 65535.0) then
conv_result_int_i := 65535;
elsif (adc_analog_tmp < 0.0) then
conv_result_int_i := 0;
else
conv_result_int_tmp := real2int(adc_analog_tmp);
conv_result_int_tmp_rl := int2real(conv_result_int_tmp);
if (adc_analog_tmp - conv_result_int_tmp_rl > 0.9999) then
conv_result_int_i := conv_result_int_tmp + 1;
else
conv_result_int_i := conv_result_int_tmp;
end if;
end if;
conv_result_int <= conv_result_int_i;
conv_result <= STD_LOGIC_VECTOR(TO_UNSIGNED(conv_result_int_i, 16));
elsif ((curr_chan = "00011") or ((curr_chan_index >= 16) and (curr_chan_index <= 31))) then
adc_analog_tmp := (analog_mux_in) * 65536.0;
adc_ext_result <= adc_analog_tmp;
if (curr_b_u = '1') then
if (adc_analog_tmp > 32767.0) then
conv_result_int_i := 32767;
elsif (adc_analog_tmp < -32768.0) then
conv_result_int_i := -32768;
else
conv_result_int_tmp := real2int(adc_analog_tmp);
conv_result_int_tmp_rl := int2real(conv_result_int_tmp);
if (adc_analog_tmp - conv_result_int_tmp_rl > 0.9999) then
conv_result_int_i := conv_result_int_tmp + 1;
else
conv_result_int_i := conv_result_int_tmp;
end if;
end if;
conv_result_int <= conv_result_int_i;
conv_result <= STD_LOGIC_VECTOR(TO_SIGNED(conv_result_int_i, 16));
else
if (adc_analog_tmp > 65535.0) then
conv_result_int_i := 65535;
elsif (adc_analog_tmp < 0.0) then
conv_result_int_i := 0;
else
conv_result_int_tmp := real2int(adc_analog_tmp);
conv_result_int_tmp_rl := int2real(conv_result_int_tmp);
if (adc_analog_tmp - conv_result_int_tmp_rl > 0.9999) then
conv_result_int_i := conv_result_int_tmp + 1;
else
conv_result_int_i := conv_result_int_tmp;
end if;
end if;
conv_result_int <= conv_result_int_i;
conv_result <= STD_LOGIC_VECTOR(TO_UNSIGNED(conv_result_int_i, 16));
end if;
else
conv_result_int <= 0;
conv_result <= "0000000000000000";
end if;
end if;
end process;
conv_count_p : process (adcclk, rst_in)
begin
if (rst_in = '1') then
conv_count <= 6;
conv_end <= '0';
seq_status_avg <= 0;
busy_r_rst <= '0';
busy_r_rst_done <= '0';
for i in 0 to 31 loop
conv_avg_count(i) <= 0; -- array of integer
end loop;
single_chan_conv_end <= '0';
elsif (rising_edge(adcclk)) then
if (adc_state = ACQ_STATE) then
if (busy_r_rst_done = '0') then
busy_r_rst <= '1';
else
busy_r_rst <= '0';
end if;
busy_r_rst_done <= '1';
end if;
if (adc_state = ACQ_STATE and conv_start = '1') then
conv_count <= 0;
conv_end <= '0';
elsif (adc_state = CONV_STATE ) then
busy_r_rst_done <= '0';
conv_count <= conv_count + 1;
if (((curr_chan /= "01000" ) and (conv_count = conv_time )) or
((curr_chan = "01000") and (conv_count = conv_time_cal_1) and (first_cal_chan = '1'))
or ((curr_chan = "01000") and (conv_count = conv_time_cal) and (first_cal_chan = '0'))) then
conv_end <= '1';
else
conv_end <= '0';
end if;
else
conv_end <= '0';
conv_count <= 0;
end if;
single_chan_conv_end <= '0';
if ( (conv_count = conv_time) or (conv_count = 44)) then
single_chan_conv_end <= '1';
end if;
if (adc_state = CONV_STATE and next_state = END_STATE and rst_lock = '0') then
case curr_avg_set is
when "00" => eoc_en <= '1';
conv_avg_count(curr_chan_index) <= 0;
when "01" =>
if (conv_avg_count(curr_chan_index) = 15) then
eoc_en <= '1';
conv_avg_count(curr_chan_index) <= 0;
seq_status_avg <= seq_status_avg - 1;
else
eoc_en <= '0';
if (conv_avg_count(curr_chan_index) = 0) then
seq_status_avg <= seq_status_avg + 1;
end if;
conv_avg_count(curr_chan_index) <= conv_avg_count(curr_chan_index) + 1;
end if;
when "10" =>
if (conv_avg_count(curr_chan_index) = 63) then
eoc_en <= '1';
conv_avg_count(curr_chan_index) <= 0;
seq_status_avg <= seq_status_avg - 1;
else
eoc_en <= '0';
if (conv_avg_count(curr_chan_index) = 0) then
seq_status_avg <= seq_status_avg + 1;
end if;
conv_avg_count(curr_chan_index) <= conv_avg_count(curr_chan_index) + 1;
end if;
when "11" =>
if (conv_avg_count(curr_chan_index) = 255) then
eoc_en <= '1';
conv_avg_count(curr_chan_index) <= 0;
seq_status_avg <= seq_status_avg - 1;
else
eoc_en <= '0';
if (conv_avg_count(curr_chan_index) = 0) then
seq_status_avg <= seq_status_avg + 1;
end if;
conv_avg_count(curr_chan_index) <= conv_avg_count(curr_chan_index) + 1;
end if;
when others => eoc_en <= '0';
end case;
else
eoc_en <= '0';
end if;
if (adc_state = END_STATE) then
conv_result_reg <= conv_result;
end if;
end if;
end process;
-- end conversion
-- average
conv_acc_result_p : process(adcclk, rst_in)
variable conv_acc_vec : std_logic_vector(23 downto 0);
variable conv_acc_vec_int : integer;
begin
if (rst_in = '1') then
for j in 0 to 31 loop
conv_acc(j) <= 0;
end loop;
conv_acc_result <= "0000000000000000";
elsif (rising_edge(adcclk)) then
if (adc_state = CONV_STATE and next_state = END_STATE) then
if (curr_avg_set /= "00" and rst_lock /= '1') then
conv_acc(curr_chan_index) <= conv_acc(curr_chan_index) + conv_result_int;
else
conv_acc(curr_chan_index) <= 0;
end if;
elsif (eoc_en = '1') then
conv_acc_vec_int := conv_acc(curr_chan_index);
if ((curr_b_u = '1') and (((curr_chan_index >= 16) and (curr_chan_index <= 31))
or (curr_chan_index = 3))) then
conv_acc_vec := STD_LOGIC_VECTOR(TO_SIGNED(conv_acc_vec_int, 24));
else
conv_acc_vec := STD_LOGIC_VECTOR(TO_UNSIGNED(conv_acc_vec_int, 24));
end if;
case curr_avg_set(1 downto 0) is
when "00" => conv_acc_result <= "0000000000000000";
when "01" => conv_acc_result <= conv_acc_vec(19 downto 4);
when "10" => conv_acc_result <= conv_acc_vec(21 downto 6);
when "11" => conv_acc_result <= conv_acc_vec(23 downto 8);
when others => conv_acc_result <= "0000000000000000";
end case;
conv_acc(curr_chan_index) <= 0;
end if;
end if;
end process;
-- end average
-- single sequence
adc_s1_flag_p : process(adcclk, rst_in)
begin
if (rst_in = '1') then
adc_s1_flag <= '0';
elsif (rising_edge(adcclk)) then
if (adc_state = SINGLE_SEQ_STATE) then
adc_s1_flag <= '1';
end if;
end if;
end process;
-- end state
eos_eoc_p: process(adcclk, rst_in)
begin
if (rst_in = '1') then
seq_count_en <= '0';
eos_out_tmp <= '0';
eoc_out_tmp <= '0';
elsif (rising_edge(adcclk)) then
if ((adc_state = CONV_STATE and next_state = END_STATE) and (curr_seq1_0_lat /= "11")
and (rst_lock = '0')) then
seq_count_en <= '1';
else
seq_count_en <= '0';
end if;
if (rst_lock = '0') then
eos_out_tmp <= eos_en;
eoc_en_delay <= eoc_en;
eoc_out_tmp <= eoc_en_delay;
else
eos_out_tmp <= '0';
eoc_en_delay <= '0';
eoc_out_tmp <= '0';
end if;
end if;
end process;
data_reg_p : process(eoc_out, rst_in_not_seq)
variable tmp_uns1 : unsigned(15 downto 0);
variable tmp_uns2 : unsigned(15 downto 0);
variable tmp_uns3 : unsigned(15 downto 0);
begin
if (rst_in_not_seq = '1') then
for k in 32 to 39 loop
if (k >= 36) then
data_reg(k) <= "1111111111111111";
else
data_reg(k) <= "0000000000000000";
end if;
end loop;
elsif (rising_edge(eoc_out)) then
if ( rst_lock = '0') then
if ((curr_chan_index >= 0 and curr_chan_index <= 3) or
(curr_chan_index >= 16 and curr_chan_index <= 31)) then
if (curr_avg_set = "00") then
data_reg(curr_chan_index) <= conv_result_reg;
else
data_reg(curr_chan_index) <= conv_acc_result;
end if;
end if;
if (curr_chan_index = 4) then
data_reg(curr_chan_index) <= X"D555";
end if;
if (curr_chan_index = 5) then
data_reg(curr_chan_index) <= X"0000";
end if;
if (curr_chan_index = 0 or curr_chan_index = 1 or curr_chan_index = 2) then
tmp_uns2 := UNSIGNED(data_reg(32 + curr_chan_index));
tmp_uns3 := UNSIGNED(data_reg(36 + curr_chan_index));
if (curr_avg_set = "00") then
tmp_uns1 := UNSIGNED(conv_result_reg);
if (tmp_uns1 > tmp_uns2) then
data_reg(32 + curr_chan_index) <= conv_result_reg;
end if;
if (tmp_uns1 < tmp_uns3) then
data_reg(36 + curr_chan_index) <= conv_result_reg;
end if;
else
tmp_uns1 := UNSIGNED(conv_acc_result);
if (tmp_uns1 > tmp_uns2) then
data_reg(32 + curr_chan_index) <= conv_acc_result;
end if;
if (tmp_uns1 < tmp_uns3) then
data_reg(36 + curr_chan_index) <= conv_acc_result;
end if;
end if;
end if;
end if;
end if;
end process;
data_written_p : process(busy_r, rst_in_not_seq)
begin
if (rst_in_not_seq = '1') then
data_written <= X"0000";
elsif (falling_edge(busy_r)) then
if (curr_avg_set = "00") then
data_written <= conv_result_reg;
else
data_written <= conv_acc_result;
end if;
end if;
end process;
-- eos and eoc
eoc_out_tmp1_p : process (eoc_out_tmp, eoc_out, rst_in)
begin
if (rst_in = '1') then
eoc_out_tmp1 <= '0';
elsif (rising_edge(eoc_out)) then
eoc_out_tmp1 <= '0';
elsif (rising_edge(eoc_out_tmp)) then
if (curr_chan /= "01000") then
eoc_out_tmp1 <= '1';
else
eoc_out_tmp1 <= '0';
end if;
end if;
end process;
eos_out_tmp1_p : process (eos_out_tmp, eos_out, rst_in)
begin
if (rst_in = '1') then
eos_out_tmp1 <= '0';
elsif (rising_edge(eos_out)) then
eos_out_tmp1 <= '0';
elsif (rising_edge(eos_out_tmp)) then
eos_out_tmp1 <= '1';
end if;
end process;
busy_out_low_edge <= '1' when (busy_out='0' and busy_out_sync='1') else '0';
eoc_eos_out_p : process (dclk_in, rst_in)
begin
if (rst_in = '1') then
op_count <= 15;
busy_out_sync <= '0';
drp_update <= '0';
alarm_update <= '0';
eoc_out <= '0';
eos_out <= '0';
elsif ( rising_edge(dclk_in)) then
busy_out_sync <= busy_out;
if (op_count = 3) then
drp_update <= '1';
else
drp_update <= '0';
end if;
if (op_count = 5 and eoc_out_tmp1 = '1') then
alarm_update <= '1';
else
alarm_update <= '0';
end if;
if (op_count = 9 ) then
eoc_out <= eoc_out_tmp1;
else
eoc_out <= '0';
end if;
if (op_count = 9) then
eos_out <= eos_out_tmp1;
else
eos_out <= '0';
end if;
if (busy_out_low_edge = '1') then
op_count <= 0;
elsif (op_count < 15) then
op_count <= op_count +1;
end if;
end if;
end process;
-- end eos and eoc
-- alarm
alm_reg_p : process(alarm_update, rst_in_not_seq )
variable tmp_unsig1 : unsigned(15 downto 0);
variable tmp_unsig2 : unsigned(15 downto 0);
variable tmp_unsig3 : unsigned(15 downto 0);
begin
if (rst_in_not_seq = '1') then
ot_out_reg <= '0';
alarm_out_reg <= "000";
elsif (rising_edge(alarm_update)) then
if (rst_lock = '0') then
if (curr_chan_lat = "00000") then
tmp_unsig1 := UNSIGNED(data_written);
tmp_unsig2 := UNSIGNED(dr_sram(16#57#));
if (tmp_unsig1 >= ot_limit_reg) then
ot_out_reg <= '1';
elsif (((tmp_unsig1 < tmp_unsig2) and (curr_seq1_0_lat /= "00")) or
((curr_seq1_0_lat = "00") and (tmp_unsig1 < ot_sf_limit_low_reg))) then
ot_out_reg <= '0';
end if;
tmp_unsig2 := UNSIGNED(dr_sram(16#50#));
tmp_unsig3 := UNSIGNED(dr_sram(16#54#));
if ( tmp_unsig1 > tmp_unsig2) then
alarm_out_reg(0) <= '1';
elsif (tmp_unsig1 <= tmp_unsig3) then
alarm_out_reg(0) <= '0';
end if;
end if;
tmp_unsig1 := UNSIGNED(data_written);
tmp_unsig2 := UNSIGNED(dr_sram(16#51#));
tmp_unsig3 := UNSIGNED(dr_sram(16#55#));
if (curr_chan_lat = "00001") then
if ((tmp_unsig1 > tmp_unsig2) or (tmp_unsig1 < tmp_unsig3)) then
alarm_out_reg(1) <= '1';
else
alarm_out_reg(1) <= '0';
end if;
end if;
tmp_unsig1 := UNSIGNED(data_written);
tmp_unsig2 := UNSIGNED(dr_sram(16#52#));
tmp_unsig3 := UNSIGNED(dr_sram(16#56#));
if (curr_chan_lat = "00010") then
if ((tmp_unsig1 > tmp_unsig2) or (tmp_unsig1 < tmp_unsig3)) then
alarm_out_reg(2) <= '1';
else
alarm_out_reg(2) <= '0';
end if;
end if;
end if;
end if;
end process;
alm_p : process(ot_out_reg, ot_en, alarm_out_reg, alarm_en)
begin
ot_out <= ot_out_reg and ot_en;
alarm_out(0) <= alarm_out_reg(0) and alarm_en(0);
alarm_out(1) <= alarm_out_reg(1) and alarm_en(1);
alarm_out(2) <= alarm_out_reg(2) and alarm_en(2);
end process;
-- end alarm
READFILE_P : process
file in_file : text;
variable open_status : file_open_status;
variable in_buf : line;
variable str_token : string(1 to 12);
variable str_token_in : string(1 to 12);
variable str_token_tmp : string(1 to 12);
variable next_time : time := 0 ps;
variable pre_time : time := 0 ps;
variable time_val : integer := 0;
variable a1 : real;
variable commentline : boolean := false;
variable HeaderFound : boolean := false;
variable read_ok : boolean := false;
variable token_len : integer;
variable HeaderCount : integer := 0;
variable vals : ANALOG_DATA := (others => 0.0);
variable valsn : ANALOG_DATA := (others => 0.0);
variable inchannel : integer := 0 ;
type int_a is array (0 to 41) of integer;
variable index_to_channel : int_a := (others => -1);
variable low : integer := -1;
variable low2 : integer := -1;
variable sim_file_flag1 : std_ulogic := '0';
variable file_line : integer := 0;
type channm_array is array (0 to 31 ) of string(1 to 12);
constant chanlist_p : channm_array := (
0 => "TEMP" & NUL & NUL & NUL & NUL & NUL & NUL & NUL & NUL,
1 => "VCCINT" & NUL & NUL & NUL & NUL & NUL & NUL,
2 => "VCCAUX" & NUL & NUL & NUL & NUL & NUL & NUL,
3 => "VP" & NUL & NUL & NUL & NUL & NUL & NUL & NUL & NUL & NUL & NUL,
4 => NUL & NUL & NUL & NUL & NUL & NUL & NUL & NUL & NUL & NUL &
NUL & NUL,
5 => NUL & NUL & NUL & NUL & NUL & NUL & NUL & NUL & NUL & NUL &
NUL & NUL,
6 => "xxxxxxxxxxxx",
7 => "xxxxxxxxxxxx",
8 => NUL & NUL & NUL & NUL & NUL & NUL & NUL & NUL & NUL & NUL &
NUL & NUL,
9 => NUL & NUL & NUL & NUL & NUL & NUL & NUL & NUL & NUL & NUL &
NUL & NUL,
10 => "xxxxxxxxxxxx",
11 => "xxxxxxxxxxxx",
12 => "xxxxxxxxxxxx",
13 => "xxxxxxxxxxxx",
14 => "xxxxxxxxxxxx",
15 => "xxxxxxxxxxxx",
16 => "VAUXP[0]" & NUL & NUL & NUL & NUL,
17 => "VAUXP[1]" & NUL & NUL & NUL & NUL,
18 => "VAUXP[2]" & NUL & NUL & NUL & NUL,
19 => "VAUXP[3]" & NUL & NUL & NUL & NUL,
20 => "VAUXP[4]" & NUL & NUL & NUL & NUL,
21 => "VAUXP[5]" & NUL & NUL & NUL & NUL,
22 => "VAUXP[6]" & NUL & NUL & NUL & NUL,
23 => "VAUXP[7]" & NUL & NUL & NUL & NUL,
24 => "VAUXP[8]" & NUL & NUL & NUL & NUL,
25 => "VAUXP[9]" & NUL & NUL & NUL & NUL,
26 => "VAUXP[10]" & NUL & NUL & NUL,
27 => "VAUXP[11]" & NUL & NUL & NUL,
28 => "VAUXP[12]" & NUL & NUL & NUL,
29 => "VAUXP[13]" & NUL & NUL & NUL,
30 => "VAUXP[14]" & NUL & NUL & NUL,
31 => "VAUXP[15]" & NUL & NUL & NUL
);
constant chanlist_n : channm_array := (
0 => "xxxxxxxxxxxx",
1 => "xxxxxxxxxxxx",
2 => "xxxxxxxxxxxx",
3 => "VN" & NUL & NUL & NUL & NUL & NUL & NUL & NUL & NUL & NUL & NUL,
4 => NUL & NUL & NUL & NUL & NUL & NUL & NUL & NUL & NUL & NUL &
NUL & NUL,
5 => NUL & NUL & NUL & NUL & NUL & NUL & NUL & NUL & NUL & NUL &
NUL & NUL,
6 => "xxxxxxxxxxxx",
7 => "xxxxxxxxxxxx",
8 => NUL & NUL & NUL & NUL & NUL & NUL & NUL & NUL & NUL & NUL &
NUL & NUL,
9 => NUL & NUL & NUL & NUL & NUL & NUL & NUL & NUL & NUL & NUL &
NUL & NUL,
10 => "xxxxxxxxxxxx",
11 => "xxxxxxxxxxxx",
12 => "xxxxxxxxxxxx",
13 => "xxxxxxxxxxxx",
14 => "xxxxxxxxxxxx",
15 => "xxxxxxxxxxxx",
16 => "VAUXN[0]" & NUL & NUL & NUL & NUL,
17 => "VAUXN[1]" & NUL & NUL & NUL & NUL,
18 => "VAUXN[2]" & NUL & NUL & NUL & NUL,
19 => "VAUXN[3]" & NUL & NUL & NUL & NUL,
20 => "VAUXN[4]" & NUL & NUL & NUL & NUL,
21 => "VAUXN[5]" & NUL & NUL & NUL & NUL,
22 => "VAUXN[6]" & NUL & NUL & NUL & NUL,
23 => "VAUXN[7]" & NUL & NUL & NUL & NUL,
24 => "VAUXN[8]" & NUL & NUL & NUL & NUL,
25 => "VAUXN[9]" & NUL & NUL & NUL & NUL,
26 => "VAUXN[10]" & NUL & NUL & NUL,
27 => "VAUXN[11]" & NUL & NUL & NUL,
28 => "VAUXN[12]" & NUL & NUL & NUL,
29 => "VAUXN[13]" & NUL & NUL & NUL,
30 => "VAUXN[14]" & NUL & NUL & NUL,
31 => "VAUXN[15]" & NUL & NUL & NUL
);
begin
file_open(open_status, in_file, SIM_MONITOR_FILE, read_mode);
if (open_status /= open_ok) then
assert false report
"*** Warning: The analog data file for SYSMON was not found. Use the SIM_MONITOR_FILE generic to specify the input analog data file name or use default name: design.txt. "
severity warning;
sim_file_flag1 := '1';
sim_file_flag <= '1';
end if;
if ( sim_file_flag1 = '0') then
while (not endfile(in_file) and (not HeaderFound)) loop
commentline := false;
readline(in_file, in_buf);
file_line := file_line + 1;
if (in_buf'LENGTH > 0 ) then
skip_blanks(in_buf);
low := in_buf'low;
low2 := in_buf'low+2;
if ( low2 <= in_buf'high) then
if ((in_buf(in_buf'low to in_buf'low+1) = "//" ) or
(in_buf(in_buf'low to in_buf'low+1) = "--" )) then
commentline := true;
end if;
while((in_buf'LENGTH > 0 ) and (not commentline)) loop
HeaderFound := true;
get_token(in_buf, str_token_in, token_len);
str_token_tmp := To_Upper(str_token_in);
if (str_token_tmp(1 to 4) = "TEMP") then
str_token := "TEMP" & NUL & NUL & NUL & NUL & NUL
& NUL & NUL & NUL;
else
str_token := str_token_tmp;
end if;
if(token_len > 0) then
HeaderCount := HeaderCount + 1;
end if;
if (HeaderCount=1) then
if (str_token(1 to token_len) /= "TIME") then
infile_format;
assert false report
" Analog Data File Error : No TIME label is found in the input file for SYSMON."
severity failure;
end if;
elsif (HeaderCount > 1) then
inchannel := -1;
for i in 0 to 31 loop
if (chanlist_p(i) = str_token) then
inchannel := i;
index_to_channel(headercount) := i;
end if;
end loop;
if (inchannel = -1) then
for i in 0 to 31 loop
if ( chanlist_n(i) = str_token) then
inchannel := i;
index_to_channel(headercount) := i+32;
end if;
end loop;
end if;
if (inchannel = -1 and token_len >0) then
infile_format;
assert false report
"Analog Data File Error : No valid channel name in the input file for SYSMON. Valid names: TEMP VCCINT VCCAUX VP VN VAUXP[1] VAUXN[1] ....."
severity failure;
end if;
else
infile_format;
assert false report
"Analog Data File Error : NOT found header in the input file for SYSMON. The header is: TIME TEMP VCCINT VCCAUX VP VN VAUXP[1] VAUXN[1] ..."
severity failure;
end if;
str_token_in := NUL & NUL & NUL & NUL & NUL & NUL & NUL & NUL &
NUL & NUL & NUL & NUL;
end loop;
end if;
end if;
end loop;
----- Read Values
while (not endfile(in_file)) loop
commentline := false;
readline(in_file, in_buf);
file_line := file_line + 1;
if (in_buf'length > 0) then
skip_blanks(in_buf);
if (in_buf'low < in_buf'high) then
if((in_buf(in_buf'low to in_buf'low+1) = "//" ) or
(in_buf(in_buf'low to in_buf'low+1) = "--" )) then
commentline := true;
end if;
if(not commentline and in_buf'length > 0) then
for i IN 1 to HeaderCount Loop
if ( i=1) then
read(in_buf, time_val, read_ok);
if (not read_ok) then
infile_format;
assert false report
" Analog Data File Error : The time value should be integer in ns scale and the last time value needs bigger than simulation time."
severity failure;
end if;
next_time := time_val * 1 ns;
else
read(in_buf, a1, read_ok);
if (not read_ok) then
assert false report
"*** Analog Data File Error: The data type should be REAL, e.g. 3.0 0.0 -0.5 "
severity failure;
end if;
inchannel:= index_to_channel(i);
if (inchannel >= 32) then
valsn(inchannel-32):=a1;
else
vals(inchannel):=a1;
end if;
end if;
end loop; -- i loop
if ( now < next_time) then
wait for ( next_time - now );
end if;
for i in 0 to 31 loop
chan_val_tmp(i) <= vals(i);
chan_valn_tmp(i) <= valsn(i);
analog_in_diff(i) <= vals(i)-valsn(i);
analog_in_uni(i) <= vals(i);
end loop;
end if;
end if;
end if;
end loop; -- while loop
file_close(in_file);
end if;
wait;
end process READFILE_P;
end SYSMON_V;
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity INV is
port(
O : out std_ulogic;
I : in std_ulogic
);
end INV;
architecture INV_V of INV is
begin
O <= (not TO_X01(I));
end INV_V;
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library unisim;
use unisim.vpkg.all;
use unisim.VCOMPONENTS.all;
entity LUT2_L is
generic(
INIT : bit_vector := X"0"
);
port(
LO : out std_ulogic;
I0 : in std_ulogic;
I1 : in std_ulogic
);
end LUT2_L;
architecture LUT2_L_V of LUT2_L is
begin
VITALBehavior : process (I0, I1)
variable INIT_reg : std_logic_vector((INIT'length - 1) downto 0) := To_StdLogicVector(INIT);
variable address : std_logic_vector(1 downto 0);
variable address_int : integer := 0;
begin
address := I1 & I0;
address_int := SLV_TO_INT(address(1 downto 0));
if ((I1 xor I0) = '1' or (I1 xor I0) = '0') then
LO <= INIT_reg(address_int);
else
if ((INIT_reg(0) = INIT_reg(1)) and (INIT_reg(2) = INIT_reg(3)) and
(INIT_reg(0) = INIT_reg(2))) then
LO <= INIT_reg(0);
elsif ((I1 = '0') and (INIT_reg(0) = INIT_reg(1))) then
LO <= INIT_reg(0);
elsif ((I1 = '1') and (INIT_reg(2) = INIT_reg(3))) then
LO <= INIT_reg(2);
elsif ((I0 = '0') and (INIT_reg(0) = INIT_reg(2))) then
LO <= INIT_reg(0);
elsif ((I0 = '1') and (INIT_reg(1) = INIT_reg(3))) then
LO <= INIT_reg(1);
else
LO <= 'X';
end if;
end if;
end process;
end LUT2_L_V;
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library unisim;
use unisim.VPKG.all;
use unisim.VCOMPONENTS.all;
entity LUT4 is
generic(
INIT : bit_vector := X"0000"
);
port(
O : out std_ulogic;
I0 : in std_ulogic;
I1 : in std_ulogic;
I2 : in std_ulogic;
I3 : in std_ulogic
);
end LUT4;
architecture LUT4_V of LUT4 is
function lut4_mux4 (d : std_logic_vector(3 downto 0); s : std_logic_vector(1 downto 0) )
return std_logic is
variable lut4_mux4_o : std_logic;
begin
if (((s(1) xor s(0)) = '1') or ((s(1) xor s(0)) = '0')) then
lut4_mux4_o := d(SLV_TO_INT(s));
elsif ((d(0) xor d(1)) = '0' and (d(2) xor d(3)) = '0'
and (d(0) xor d(2)) = '0') then
lut4_mux4_o := d(0);
elsif ((s(1) = '0') and (d(0) = d(1))) then
lut4_mux4_o := d(0);
elsif ((s(1) = '1') and (d(2) = d(3))) then
lut4_mux4_o := d(2);
elsif ((s(0) = '0') and (d(0) = d(2))) then
lut4_mux4_o := d(0);
elsif ((s(0) = '1') and (d(1) = d(3))) then
lut4_mux4_o := d(1);
else
lut4_mux4_o := 'X';
end if;
return (lut4_mux4_o);
end function lut4_mux4;
constant INIT_reg : std_logic_vector(15 downto 0) := To_StdLogicVector(INIT);
begin
lut_p : process (I0, I1, I2, I3)
-- variable INIT_reg : std_logic_vector(15 downto 0) := To_StdLogicVector(INIT);
variable I_reg : std_logic_vector(3 downto 0);
begin
I_reg := TO_STDLOGICVECTOR(I3 & I2 & I1 & I0);
if ((I3 xor I2 xor I1 xor I0) = '1' or (I3 xor I2 xor I1 xor I0) = '0') then
O <= INIT_reg(SLV_TO_INT(I_reg));
else
O <= lut4_mux4 (
(lut4_mux4 ( INIT_reg(15 downto 12), I_reg(1 downto 0)) &
lut4_mux4 ( INIT_reg(11 downto 8), I_reg(1 downto 0)) &
lut4_mux4 ( INIT_reg(7 downto 4), I_reg(1 downto 0)) &
lut4_mux4 ( INIT_reg(3 downto 0), I_reg(1 downto 0))), I_reg(3 downto 2));
end if;
end process;
end LUT4_V;
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library unisim;
use unisim.VPKG.all;
use unisim.VCOMPONENTS.all;
entity LUT3 is
generic(
INIT : bit_vector := X"00"
);
port(
O : out std_ulogic;
I0 : in std_ulogic;
I1 : in std_ulogic;
I2 : in std_ulogic
);
end LUT3;
architecture LUT3_V of LUT3 is
function lut4_mux4 (d : std_logic_vector(3 downto 0); s : std_logic_vector(1 downto 0))
return std_logic is
variable lut4_mux4_o : std_logic;
begin
if (((s(1) xor s(0)) = '1') or ((s(1) xor s(0)) = '0')) then
lut4_mux4_o := d(SLV_TO_INT(s));
elsif ((d(0) xor d(1)) = '0' and (d(2) xor d(3)) = '0'
and (d(0) xor d(2)) = '0') then
lut4_mux4_o := d(0);
elsif ((s(1) = '0') and (d(0) = d(1))) then
lut4_mux4_o := d(0);
elsif ((s(1) = '1') and (d(2) = d(3))) then
lut4_mux4_o := d(2);
elsif ((s(0) = '0') and (d(0) = d(2))) then
lut4_mux4_o := d(0);
elsif ((s(0) = '1') and (d(1) = d(3))) then
lut4_mux4_o := d(1);
else
lut4_mux4_o := 'X';
end if;
return (lut4_mux4_o);
end function lut4_mux4;
constant INIT_reg : std_logic_vector(7 downto 0) := To_StdLogicVector(INIT);
begin
VITALBehavior : process (I0, I1, I2)
variable I_reg : std_logic_vector(2 downto 0);
begin
I_reg := TO_STDLOGICVECTOR( I2 & I1 & I0);
if ((I2 xor I1 xor I0) = '1' or (I2 xor I1 xor I0) = '0') then
O <= INIT_reg(SLV_TO_INT(I_reg));
else
O <= lut4_mux4(('0' & '0' & lut4_mux4(INIT_reg(7 downto 4), I_reg(1 downto 0)) &
lut4_mux4(INIT_reg(3 downto 0), I_reg(1 downto 0))), ('0' & I_reg(2)));
end if;
end process;
end LUT3_V;
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library unisim;
use unisim.VPKG.all;
use unisim.VCOMPONENTS.all;
entity LUT2 is
generic(
INIT : bit_vector := X"0"
);
port(
O : out std_ulogic;
I0 : in std_ulogic;
I1 : in std_ulogic
);
end LUT2;
architecture LUT2_V of LUT2 is
begin
VITALBehavior : process (I0, I1)
variable INIT_reg : std_logic_vector((INIT'length - 1) downto 0) := To_StdLogicVector(INIT);
variable address : std_logic_vector(1 downto 0);
variable address_int : integer := 0;
begin
address := I1 & I0;
address_int := SLV_TO_INT(address(1 downto 0));
if ((I1 xor I0) = '1' or (I1 xor I0) = '0') then
O <= INIT_reg(address_int);
else
if ((INIT_reg(0) = INIT_reg(1)) and (INIT_reg(2) = INIT_reg(3)) and
(INIT_reg(0) = INIT_reg(2))) then
O <= INIT_reg(0);
elsif ((I1 = '0') and (INIT_reg(0) = INIT_reg(1))) then
O <= INIT_reg(0);
O <= INIT_reg(0);
elsif ((I1 = '1') and (INIT_reg(2) = INIT_reg(3))) then
O <= INIT_reg(2);
elsif ((I0 = '0') and (INIT_reg(0) = INIT_reg(2))) then
O <= INIT_reg(0);
elsif ((I0 = '1') and (INIT_reg(1) = INIT_reg(3))) then
O <= INIT_reg(1);
else
O <= 'X';
end if;
end if;
end process;
end LUT2_V;
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity FDC is
generic(
INIT : bit := '0'
);
port(
Q : out std_ulogic;
C : in std_ulogic;
CLR : in std_ulogic;
D : in std_ulogic
);
end FDC;
architecture FDC_V of FDC is
begin
VITALBehavior : process(CLR, C)
variable FIRST_TIME : boolean := true;
begin
if (FIRST_TIME = true) then
Q <= TO_X01(INIT);
FIRST_TIME := false;
end if;
if (CLR = '1') then
Q <= '0';
elsif (rising_edge(C)) then
Q <= D after 100 ps;
end if;
end process;
end FDC_V;
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library unisim;
use unisim.VPKG.all;
use unisim.VCOMPONENTS.all;
entity LUT3_L is
generic(
INIT : bit_vector := X"00"
);
port(
LO : out std_ulogic;
I0 : in std_ulogic;
I1 : in std_ulogic;
I2 : in std_ulogic
);
end LUT3_L;
architecture LUT3_L_V of LUT3_L is
function lut4_mux4 (d : std_logic_vector(3 downto 0); s : std_logic_vector(1 downto 0))
return std_logic is
variable lut4_mux4_o : std_logic;
begin
if (((s(1) xor s(0)) = '1') or ((s(1) xor s(0)) = '0')) then
lut4_mux4_o := d(SLV_TO_INT(s));
elsif ((d(0) xor d(1)) = '0' and (d(2) xor d(3)) = '0'
and (d(0) xor d(2)) = '0') then
lut4_mux4_o := d(0);
elsif ((s(1) = '0') and (d(0) = d(1))) then
lut4_mux4_o := d(0);
elsif ((s(1) = '1') and (d(2) = d(3))) then
lut4_mux4_o := d(2);
elsif ((s(0) = '0') and (d(0) = d(2))) then
lut4_mux4_o := d(0);
elsif ((s(0) = '1') and (d(1) = d(3))) then
lut4_mux4_o := d(1);
else
lut4_mux4_o := 'X';
end if;
return (lut4_mux4_o);
end function lut4_mux4;
constant INIT_reg : std_logic_vector(7 downto 0) := To_StdLogicVector(INIT);
begin
VITALBehavior : process (I0, I1, I2)
variable I_reg : std_logic_vector(2 downto 0);
begin
I_reg := TO_STDLOGICVECTOR( I2 & I1 & I0);
if ((I2 xor I1 xor I0) = '1' or (I2 xor I1 xor I0) = '0') then
LO <= INIT_reg(SLV_TO_INT(I_reg));
else
LO <= lut4_mux4(('0' & '0' & lut4_mux4(INIT_reg(7 downto 4), I_reg(1 downto 0)) &
lut4_mux4(INIT_reg(3 downto 0), I_reg(1 downto 0))), ('0' & I_reg(2)));
end if;
end process;
end LUT3_L_V;
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity LUT1 is
generic(
INIT : bit_vector := X"0"
);
port(
O : out std_ulogic;
I0 : in std_ulogic
);
end LUT1;
architecture LUT1_V of LUT1 is
begin
VITALBehavior : process (I0)
variable INIT_reg : std_logic_vector((INIT'length - 1) downto 0) := To_StdLogicVector(INIT);
begin
if (INIT_reg(0) = INIT_reg(1)) then
O <= INIT_reg(0);
elsif (I0 = '0') then
O <= INIT_reg(0);
elsif (I0 = '1') then
O <= INIT_reg(1);
else
O <= 'X';
end if;
end process;
end LUT1_V;
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library unisim;
use unisim.VPKG.all;
use unisim.VCOMPONENTS.all;
entity LUT4_L is
generic(
INIT : bit_vector := X"0000"
);
port(
LO : out std_ulogic;
I0 : in std_ulogic;
I1 : in std_ulogic;
I2 : in std_ulogic;
I3 : in std_ulogic
);
end LUT4_L;
architecture LUT4_L_V of LUT4_L is
function lut4_mux4 (d : std_logic_vector(3 downto 0); s : std_logic_vector(1 downto 0) )
return std_logic is
variable lut4_mux4_o : std_logic;
begin
if (((s(1) xor s(0)) = '1') or ((s(1) xor s(0)) = '0')) then
lut4_mux4_o := d(SLV_TO_INT(s));
elsif ((d(0) = d(1)) and (d(2) = d(3)) and (d(0) = d(2))) then
lut4_mux4_o := d(0);
elsif ((s(1) = '0') and (d(0) = d(1))) then
lut4_mux4_o := d(0);
elsif ((s(1) = '1') and (d(2) = d(3))) then
lut4_mux4_o := d(2);
elsif ((s(0) = '0') and (d(0) = d(2))) then
lut4_mux4_o := d(0);
elsif ((s(0) = '1') and (d(1) = d(3))) then
lut4_mux4_o := d(1);
else
lut4_mux4_o := 'X';
end if;
return (lut4_mux4_o);
end function lut4_mux4;
constant INIT_reg : std_logic_vector(15 downto 0) := To_StdLogicVector(INIT);
begin
lut_p : process (I0, I1, I2, I3)
variable I_reg : std_logic_vector(3 downto 0);
begin
I_reg := TO_STDLOGICVECTOR(I3 & I2 & I1 & I0);
if ((I3 xor I2 xor I1 xor I0) = '1' or (I3 xor I2 xor I1 xor I0) = '0') then
LO <= INIT_reg(SLV_TO_INT(I_reg));
else
LO <= lut4_mux4 (
(lut4_mux4 ( INIT_reg(15 downto 12), I_reg(1 downto 0)) &
lut4_mux4 ( INIT_reg(11 downto 8), I_reg(1 downto 0)) &
lut4_mux4 ( INIT_reg(7 downto 4), I_reg(1 downto 0)) &
lut4_mux4 ( INIT_reg(3 downto 0), I_reg(1 downto 0))), I_reg(3 downto 2));
end if;
end process;
end LUT4_L_V;
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity FDCE is
generic(
INIT : bit := '0'
);
port(
Q : out std_ulogic;
C : in std_ulogic;
CE : in std_ulogic;
CLR : in std_ulogic;
D : in std_ulogic
);
end FDCE;
architecture FDCE_V of FDCE is
begin
VITALBehavior : process(C, CLR)
variable FIRST_TIME : boolean := true ;
begin
if (FIRST_TIME = true) then
Q <= TO_X01(INIT);
FIRST_TIME := false;
end if;
if (CLR = '1') then
Q <= '0';
elsif (rising_edge(C)) then
if (CE = '1') then
Q <= D after 100 ps;
end if;
end if;
end process;
end FDCE_V;
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity FDC_1 is
generic(
INIT : bit := '0'
);
port(
Q : out std_ulogic;
C : in std_ulogic;
CLR : in std_ulogic;
D : in std_ulogic
);
end FDC_1;
architecture FDC_1_V of FDC_1 is
begin
VITALBehavior : process(C, CLR)
variable FIRST_TIME : boolean := true ;
begin
if (FIRST_TIME = true) then
Q <= TO_X01(INIT);
FIRST_TIME := false;
end if;
if (CLR = '1') then
Q <= '0';
elsif (falling_edge(C)) then
Q <= D after 100 ps;
end if;
end process;
end FDC_1_V;
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity FDS is
generic(
INIT : bit := '1'
);
port(
Q : out std_ulogic;
C : in std_ulogic;
D : in std_ulogic;
S : in std_ulogic
);
end FDS;
architecture FDS_V of FDS is
begin
VITALBehavior : process(C)
variable FIRST_TIME : boolean := true ;
begin
if (FIRST_TIME = true) then
Q <= TO_X01(INIT);
FIRST_TIME := false;
end if;
if (rising_edge(C)) then
if (S = '1') then
Q <= '1' after 100 ps;
else
Q <= D after 100 ps;
end if;
end if;
end process;
end FDS_V;
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity MUXCY is
port(
O : out std_ulogic;
CI : in std_ulogic;
DI : in std_ulogic;
S : in std_ulogic
);
end MUXCY;
architecture MUXCY_V of MUXCY is
begin
VITALBehavior : process (CI, DI, S)
begin
if (S = '0') then
O <= DI;
elsif (S = '1') then
O <= CI;
end if;
end process;
end MUXCY_V;
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity LUT1_L is
generic(
INIT : bit_vector := X"0"
);
port(
LO : out std_ulogic;
I0 : in std_ulogic
);
end LUT1_L;
architecture LUT1_L_V of LUT1_L is
begin
VITALBehavior : process (I0)
variable INIT_reg : std_logic_vector((INIT'length - 1) downto 0) := To_StdLogicVector(INIT);
begin
if (I0 = '0') then
LO <= INIT_reg(0);
elsif (I0 = '1') then
LO <= INIT_reg(1);
elsif (INIT_reg(0) = INIT_reg(1)) then
LO <= INIT_reg(0);
else
LO <= 'X';
end if;
end process;
end LUT1_L_V;
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity MUXF6 is
port(
O : out std_ulogic;
I0 : in std_ulogic;
I1 : in std_ulogic;
S : in std_ulogic
);
end MUXF6;
architecture MUXF6_V of MUXF6 is
begin
VITALBehavior : process (I0, I1, S)
begin
if (S = '0') then
O <= I0;
elsif (S = '1') then
O <= I1;
end if;
end process;
end MUXF6_V;
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity MUXF5_D is
port(
LO : out std_ulogic;
O : out std_ulogic;
I0 : in std_ulogic;
I1 : in std_ulogic;
S : in std_ulogic
);
end MUXF5_D;
architecture MUXF5_D_V of MUXF5_D is
begin
VITALBehavior : process (I0, I1, S)
begin
if (S = '0') then
O <= I0;
LO <= I0;
elsif (S = '1') then
O <= I1;
LO <= I1;
end if;
end process;
end MUXF5_D_V;
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity XORCY is
port(
O : out std_ulogic;
CI : in std_ulogic;
LI : in std_ulogic
);
end XORCY;
architecture XORCY_V of XORCY is
begin
O <= (CI xor LI);
end XORCY_V;
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity MUXCY_L is
port(
LO : out std_ulogic;
CI : in std_ulogic;
DI : in std_ulogic;
S : in std_ulogic
);
end MUXCY_L;
architecture MUXCY_L_V of MUXCY_L is
begin
VITALBehavior : process (CI, DI, S)
begin
if (S = '0') then
LO <= DI;
elsif (S = '1') then
LO <= CI;
end if;
end process;
end MUXCY_L_V;
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity FDSE is
generic(
INIT : bit := '1'
);
port(
Q : out std_ulogic;
C : in std_ulogic;
CE : in std_ulogic;
D : in std_ulogic;
S : in std_ulogic
);
end FDSE;
architecture FDSE_V of FDSE is
begin
VITALBehavior : process(C)
variable FIRST_TIME : boolean := true ;
begin
if (FIRST_TIME = true) then
Q <= TO_X01(INIT);
FIRST_TIME := false;
end if;
if (rising_edge(C)) then
if (S = '1') then
Q <= '1' after 100 ps;
elsif (CE = '1') then
Q <= D after 100 ps;
end if;
end if;
end process;
end FDSE_V;
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity MULT_AND is
port(
LO : out std_ulogic;
I0 : in std_ulogic;
I1 : in std_ulogic
);
end MULT_AND;
architecture MULT_AND_V of MULT_AND is
begin
VITALBehavior : process (I1, I0)
begin
LO <= (I0 and I1) after 0 ps;
end process;
end MULT_AND_V;
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity FDP is
generic(
INIT : bit := '1'
);
port(
Q : out std_ulogic;
C : in std_ulogic;
D : in std_ulogic;
PRE : in std_ulogic
);
end FDP;
architecture FDP_V of FDP is
begin
VITALBehavior : process(C, PRE)
variable FIRST_TIME : boolean := true ;
begin
if (FIRST_TIME = true) then
Q <= TO_X01(INIT);
FIRST_TIME := false;
end if;
if (PRE = '1') then
Q <= '1';
elsif (C' event and C = '1') then
Q <= D after 100 ps;
end if;
end process;
end FDP_V;
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library UNISIM;
use UNISIM.VPKG.all;
entity SRL16E is
generic (
INIT : bit_vector := X"0000"
);
port (
Q : out STD_ULOGIC;
A0 : in STD_ULOGIC;
A1 : in STD_ULOGIC;
A2 : in STD_ULOGIC;
A3 : in STD_ULOGIC;
CE : in STD_ULOGIC;
CLK : in STD_ULOGIC;
D : in STD_ULOGIC
);
end SRL16E;
architecture SRL16E_V of SRL16E is
signal SHIFT_REG : std_logic_vector (16 downto 0) := ('X' & To_StdLogicVector(INIT));
begin
VITALReadBehavior : process(A0, A1, A2, A3, SHIFT_REG)
variable VALID_ADDR : boolean := FALSE;
variable LENGTH : integer;
variable ADDR : std_logic_vector(3 downto 0);
begin
ADDR := (A3, A2, A1, A0);
VALID_ADDR := ADDR_IS_VALID(SLV => ADDR);
if (VALID_ADDR) then
LENGTH := SLV_TO_INT(SLV => ADDR);
else
LENGTH := 16;
end if;
Q <= SHIFT_REG(LENGTH);
end process VITALReadBehavior;
VITALWriteBehavior : process
variable FIRST_TIME : boolean := TRUE;
begin
if (FIRST_TIME) then
wait until ((CE = '1' or CE = '0') and
(CLK'last_value = '0' or CLK'last_value = '1') and
(CLK = '0' or CLK = '1'));
FIRST_TIME := FALSE;
end if;
if (CLK'event AND CLK'last_value = '0') then
if (CLK = '1') then
if (CE = '1') then
for I in 15 downto 1 loop
SHIFT_REG(I) <= SHIFT_REG(I-1) after 100 ps;
end loop;
SHIFT_REG(0) <= D after 100 ps;
elsif (CE = 'X') then
SHIFT_REG <= (others => 'X') after 100 ps;
end if;
elsif (CLK = 'X') then
if (CE /= '0') then
SHIFT_REG <= (others => 'X') after 100 ps;
end if;
end if;
elsif (CLK'event AND CLK'last_value = 'X') then
if (CLK = '1') then
if (CE /= '0') then
SHIFT_REG <= (others => 'X') after 100 ps;
end if;
end if;
end if;
wait on CLK;
end process VITALWriteBehavior;
end SRL16E_V;
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library UNISIM;
use UNISIM.VPKG.all;
entity ROM256X1 is
generic (
INIT : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"
);
port (
O : out std_ulogic;
A0 : in std_ulogic;
A1 : in std_ulogic;
A2 : in std_ulogic;
A3 : in std_ulogic;
A4 : in std_ulogic;
A5 : in std_ulogic;
A6 : in std_ulogic;
A7 : in std_ulogic
);
end ROM256X1;
architecture ROM256X1_V of ROM256X1 is
begin
VITALBehavior : process (A7, A6, A5, A4, A3, A2, A1, A0)
variable INIT_BITS : std_logic_vector(255 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
variable MEM : std_logic_vector( 256 downto 0 );
variable Index : integer := 256;
variable Raddress : std_logic_vector (7 downto 0);
variable FIRST_TIME : boolean := true;
begin
if (FIRST_TIME = true) then
INIT_BITS(INIT'length-1 downto 0) := To_StdLogicVector(INIT );
MEM := ('X' & INIT_BITS(255 downto 0));
FIRST_TIME := false;
end if;
Raddress := (A7, A6, A5, A4, A3, A2, A1, A0);
Index := SLV_TO_INT(SLV => Raddress );
O <= MEM(Index);
end process VITALBehavior;
end ROM256X1_V;
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity FDPE is
generic(
INIT : bit := '1'
);
port(
Q : out std_ulogic;
C : in std_ulogic;
CE : in std_ulogic;
D : in std_ulogic;
PRE : in std_ulogic
);
end FDPE;
architecture FDPE_V of FDPE is
begin
VITALBehavior : process(C, PRE)
variable FIRST_TIME : boolean := true ;
begin
if (FIRST_TIME = true) then
Q <= TO_X01(INIT);
FIRST_TIME := false;
end if;
if (PRE = '1') then
Q <= '1';
elsif (rising_edge(C)) then
if (CE = '1') then
Q <= D after 100 ps;
end if;
end if;
end process;
end FDPE_V;
library IEEE;
use IEEE.std_logic_1164.all;
library unisim;
use unisim.Vpkg.all;
entity MULT18X18 is
port (
P : out std_logic_vector (35 downto 0);
A : in std_logic_vector (17 downto 0);
B : in std_logic_vector (17 downto 0)
);
end MULT18X18;
architecture MULT18X18_V of MULT18X18 is
function INT_TO_SLV(ARG: integer; SIZE: integer) return std_logic_vector is
variable result : std_logic_vector (SIZE-1 downto 0);
variable temp : integer := ARG;
begin
temp := ARG;
for i in 0 to SIZE-1 loop
if (temp mod 2) = 1 then
result(i) := '1';
else
result(i) := '0';
end if;
if temp > 0 then
temp := temp /2 ;
elsif (temp > integer'low) then
temp := (temp-1) / 2;
else
temp := temp / 2;
end if;
end loop;
return result;
end;
function COMPLEMENT(ARG: std_logic_vector ) return std_logic_vector is
variable RESULT : std_logic_vector (ARG'left downto 0);
variable found1 : std_ulogic := '0';
begin
for i in 0 to ARG'left loop
if (found1 = '0') then
RESULT(i) := ARG(i);
if (ARG(i) = '1' ) then
found1 := '1';
end if;
else
RESULT(i) := not ARG(i);
end if;
end loop;
return result;
end;
function VECPLUS(A, B: std_logic_vector ) return std_logic_vector is
variable carry: std_ulogic;
variable BV, sum: std_logic_vector(A'left downto 0);
begin
if (A(A'left) = 'X' or B(B'left) = 'X') then
sum := (others => 'X');
return(sum);
end if;
carry := '0';
BV := B;
for i in 0 to A'left loop
sum(i) := A(i) xor BV(i) xor carry;
carry := (A(i) and BV(i)) or
(A(i) and carry) or
(carry and BV(i));
end loop;
return sum;
end;
begin
VITALBehaviour : process (A, B)
variable O_zd,O1_zd, O2_zd : std_logic_vector( A'length+B'length-1 downto 0);
variable IA, IB1,IB2 : integer ;
variable sign : std_ulogic := '0';
variable A_i : std_logic_vector(A'left downto 0);
variable B_i : std_logic_vector(B'left downto 0);
begin
if (Is_X(A) or Is_X(B) ) then
O_zd := (others => 'X');
else
if (A(A'left) = '1' ) then
A_i := complement(A);
else
A_i := A;
end if;
if (B(B'left) = '1') then
B_i := complement(B);
else
B_i := B;
end if;
IA := SLV_TO_INT(A_i);
IB1 := SLV_TO_INT(B_i (17 downto 9));
IB2 := SLV_TO_INT(B_i (8 downto 0));
O1_zd := INT_TO_SLV((IA * IB1), A'length+B'length);
-- shift I1_zd 9 to the left
for j in 0 to 8 loop
O1_zd(A'length+B'length-1 downto 0) := O1_zd(A'length+B'length-2 downto 0) & '0';
end loop;
O2_zd := INT_TO_SLV((IA * IB2), A'length+B'length);
O_zd := VECPLUS(O1_zd, O2_zd);
sign := A(A'left) xor B(B'left);
if (sign = '1' ) then
O_zd := complement(O_zd);
end if;
end if;
P <= O_zd;
end process VITALBehaviour;
end MULT18X18_V ;
library IEEE;
use IEEE.std_logic_1164.all;
library unisim;
use unisim.Vpkg.all;
entity MULT18X18S is
port (
P : out std_logic_vector (35 downto 0);
A : in std_logic_vector (17 downto 0);
B : in std_logic_vector (17 downto 0);
C : in std_ulogic;
CE : in std_ulogic;
R : in std_ulogic
);
end MULT18X18S;
architecture MULT18X18S_V of MULT18X18S is
function INT_TO_SLV(ARG : integer; SIZE : integer) return std_logic_vector is
variable result : std_logic_vector (SIZE-1 downto 0);
variable temp : integer := ARG;
begin
temp := ARG;
for i in 0 to SIZE-1 loop
if (temp mod 2) = 1 then
result(i) := '1';
else
result(i) := '0';
end if;
if temp > 0 then
temp := temp /2;
elsif (temp > integer'low) then
temp := (temp-1) / 2;
else
temp := temp / 2;
end if;
end loop;
return result;
end;
function COMPLEMENT(ARG : std_logic_vector ) return std_logic_vector is
variable RESULT : std_logic_vector (ARG'left downto 0);
variable found1 : std_ulogic := '0';
begin
for i in 0 to ARG'left loop
if (found1 = '0') then
RESULT(i) := ARG(i);
if (ARG(i) = '1' ) then
found1 := '1';
end if;
else
RESULT(i) := not ARG(i);
end if;
end loop;
return result;
end;
function VECPLUS(A, B : std_logic_vector ) return std_logic_vector is
variable carry : std_ulogic;
variable BV, sum : std_logic_vector(A'left downto 0);
begin
if (A(A'left) = 'X' or B(B'left) = 'X') then
sum := (others => 'X');
return(sum);
end if;
carry := '0';
BV := B;
for i in 0 to A'left loop
sum(i) := A(i) xor BV(i) xor carry;
carry := (A(i) and BV(i)) or
(A(i) and carry) or
(carry and BV(i));
end loop;
return sum;
end;
begin
VITALBehaviour : process (C)
variable O_zd, O1_zd, O2_zd : std_logic_vector( A'length+B'length-1 downto 0);
variable B1_zd, B2_zd : bit_vector(A'length+B'length-1 downto 0);
variable IA, IB1, Ib2 : integer;
variable sign : std_ulogic := '0';
variable A_i : std_logic_vector(A'left downto 0);
variable B_i : std_logic_vector(B'left downto 0);
begin
if (rising_edge(C)) then
if (R = '1' ) then
O_zd := (others => '0');
elsif (CE = '1' ) then
if (Is_X(A) or Is_X(B) ) then
O_zd := (others => 'X');
else
if (A(A'left) = '1' ) then
A_i := complement(A);
else
A_i := A;
end if;
if (B(B'left) = '1') then
B_i := complement(B);
else
B_i := B;
end if;
IA := SLV_TO_INT(A_i);
IB1 := SLV_TO_INT(B_i (17 downto 9));
IB2 := SLV_TO_INT(B_i (8 downto 0));
O1_zd := INT_TO_SLV((IA * IB1), A'length+B'length);
for j in 0 to 8 loop
O1_zd(A'length+B'length-1 downto 0) := O1_zd(A'length+B'length-2 downto 0) & '0';
end loop;
O2_zd := INT_TO_SLV((IA * IB2), A'length+B'length);
O_zd := VECPLUS(O1_zd, O2_zd);
sign := A(A'left) xor B(B'left);
if (sign = '1' ) then
O_zd := complement(O_zd);
end if;
end if;
end if;
end if;
P <= O_zd after 100 ps;
end process VITALBehaviour;
end MULT18X18S_V;
library IEEE;
use IEEE.std_logic_1164.all;
library unisim;
use unisim.Vpkg.all;
entity ROM128X1 is
generic (
INIT : bit_vector := X"00000000000000000000000000000000"
);
port (
O : out std_ulogic;
A0 : in std_ulogic;
A1 : in std_ulogic;
A2 : in std_ulogic;
A3 : in std_ulogic;
A4 : in std_ulogic;
A5 : in std_ulogic;
A6 : in std_ulogic
);
end ROM128X1;
architecture ROM128X1_V of ROM128X1 is
begin
VITALBehavior : process (A6, A5, A4, A3, A2, A1, A0)
variable INIT_BITS : std_logic_vector(127 downto 0) := To_StdLogicVector(INIT);
variable MEM : std_logic_vector( 128 downto 0 );
variable Index : integer := 128;
variable Raddress : std_logic_vector (6 downto 0);
variable FIRST_TIME : boolean := true;
begin
if (FIRST_TIME = true) then
MEM := ('X' & INIT_BITS(127 downto 0));
FIRST_TIME := false;
end if;
Raddress := (A6, A5, A4, A3, A2, A1, A0);
Index := SLV_TO_INT(SLV => Raddress);
O <= MEM(Index);
end process VITALBehavior;
end ROM128X1_V;
library IEEE;
use IEEE.std_logic_1164.all;
library unisim;
use unisim.Vpkg.all;
entity ROM16X1 is
generic (
INIT : bit_vector := X"0000"
);
port (
O : out std_ulogic;
A0 : in std_ulogic;
A1 : in std_ulogic;
A2 : in std_ulogic;
A3 : in std_ulogic
);
end ROM16X1;
architecture ROM16X1_V of ROM16X1 is
begin
VITALBehavior : process (A3, A2, A1, A0)
variable INIT_BITS : std_logic_vector(15 downto 0) := To_StdLogicVector(INIT);
variable MEM : std_logic_vector( 16 downto 0 ) ;
variable Index : integer := 16;
variable FIRST_TIME : boolean := TRUE;
begin
if (FIRST_TIME = TRUE) then
MEM := ('X' & INIT_BITS(15 downto 0));
FIRST_TIME := FALSE;
end if;
Index := DECODE_ADDR4(ADDRESS => (A3, A2, A1, A0));
O <= MEM(Index);
end process VITALBehavior;
end ROM16X1_V;
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity MUXF7 is
port(
O : out std_ulogic;
I0 : in std_ulogic;
I1 : in std_ulogic;
S : in std_ulogic
);
end MUXF7;
architecture MUXF7_V of MUXF7 is
begin
VITALBehavior : process (I0, I1, S)
begin
if (S = '0') then
O <= I0;
elsif (S = '1') then
O <= I1;
end if;
end process;
end MUXF7_V;
----- CELL IODELAY -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library unisim;
use unisim.vpkg.all;
entity IODELAY is
generic(
DELAY_SRC : string := "I";
HIGH_PERFORMANCE_MODE : boolean := true;
IDELAY_TYPE : string := "DEFAULT";
IDELAY_VALUE : integer := 0;
ODELAY_VALUE : integer := 0;
REFCLK_FREQUENCY : real := 200.0;
SIGNAL_PATTERN : string := "DATA"
);
port(
DATAOUT : out std_ulogic;
C : in std_ulogic;
CE : in std_ulogic;
DATAIN : in std_ulogic;
IDATAIN : in std_ulogic;
INC : in std_ulogic;
ODATAIN : in std_ulogic;
RST : in std_ulogic;
T : in std_ulogic
);
end IODELAY;
architecture IODELAY_V OF IODELAY is
constant ILEAK_ADJUST : real := 1.0;
constant D_IOBDELAY_OFFSET : real := 0.0;
-----------------------------------------------------------
constant MAX_IDELAY_COUNT : integer := 63;
constant MIN_IDELAY_COUNT : integer := 0;
constant MAX_ODELAY_COUNT : integer := 63;
constant MIN_ODELAY_COUNT : integer := 0;
constant MAX_REFCLK_FREQUENCY : real := 225.0;
constant MIN_REFCLK_FREQUENCY : real := 175.0;
signal C_ipd : std_ulogic := 'X';
signal CE_ipd : std_ulogic := 'X';
signal GSR : std_ulogic := '0';
signal GSR_ipd : std_ulogic := 'X';
signal DATAIN_ipd : std_ulogic := 'X';
signal IDATAIN_ipd : std_ulogic := 'X';
signal INC_ipd : std_ulogic := 'X';
signal ODATAIN_ipd : std_ulogic := 'X';
signal RST_ipd : std_ulogic := 'X';
signal T_ipd : std_ulogic := 'X';
signal C_dly : std_ulogic := 'X';
signal CE_dly : std_ulogic := 'X';
signal GSR_dly : std_ulogic := '0';
signal DATAIN_dly : std_ulogic := 'X';
signal IDATAIN_dly : std_ulogic := 'X';
signal INC_dly : std_ulogic := 'X';
signal ODATAIN_dly : std_ulogic := 'X';
signal RST_dly : std_ulogic := 'X';
signal T_dly : std_ulogic := 'X';
signal IDATAOUT_delayed : std_ulogic := 'X';
-- signal IDATAOUT_zd : std_ulogic := 'X';
-- signal IDATAOUT_viol : std_ulogic := 'X';
signal ODATAOUT_delayed : std_ulogic := 'X';
-- signal ODATAOUT_zd : std_ulogic := 'X';
-- signal ODATAOUT_viol : std_ulogic := 'X';
signal DATAOUT_zd : std_ulogic := 'X';
-- signal DATAOUT_viol : std_ulogic := 'X';
signal iDelay : time := 0.0 ps;
signal oDelay : time := 0.0 ps;
signal idata_mux : std_ulogic := 'X';
signal Violation : std_ulogic := '0';
begin
---------------------
-- INPUT PATH DELAYs
--------------------
C_dly <= C after 0 ps;
CE_dly <= CE after 0 ps;
DATAIN_dly <= DATAIN after 0 ps;
IDATAIN_dly <= IDATAIN after 0 ps;
INC_dly <= INC after 0 ps;
ODATAIN_dly <= ODATAIN after 0 ps;
RST_dly <= RST after 0 ps;
T_dly <= T after 0 ps;
--------------------
-- BEHAVIOR SECTION
--------------------
--####################################################################
--##### Initialize #####
--####################################################################
prcs_init:process
variable TapCount_var : integer := 0;
variable IsTapDelay_var : boolean := true;
variable idelaytypefixed_var : boolean := false;
variable idelaytypedefault_var : boolean := false;
begin
-------- SIGNAL_PATTERN check
if((SIGNAL_PATTERN /= "CLOCK") and (SIGNAL_PATTERN /= "DATA"))then
assert false
report "Attribute Syntax Error: Legal values for SIGNAL_PATTERN are DATA or CLOCK"
severity Failure;
end if;
-------- HIGH_PERFORMANCE_MODE check
case HIGH_PERFORMANCE_MODE is
when true | false => null;
when others =>
assert false
report "Attribute Syntax Error: The attribute HIGH_PERFORMANCE_MODE on IODELAY must be set to either true or false."
severity Failure;
end case;
-------- IDELAY_TYPE check
if(IDELAY_TYPE = "FIXED") then
idelaytypefixed_var := true;
elsif(IDELAY_TYPE = "VARIABLE") then
idelaytypefixed_var := false;
elsif(IDELAY_TYPE = "DEFAULT") then
idelaytypedefault_var := true;
idelaytypefixed_var := false;
else
GenericValueCheckMessage
( HeaderMsg => " Attribute Syntax Warning ",
GenericName => " IDELAY_TYPE ",
EntityName => "/IODELAY",
GenericValue => IDELAY_TYPE,
Unit => "",
ExpectedValueMsg => " The Legal values for this attribute are ",
ExpectedGenericValue => " DEFAULT, FIXED or VARIABLE ",
TailMsg => "",
MsgSeverity => failure
);
end if;
-------- IDELAY_VALUE check
if((IDELAY_VALUE < MIN_IDELAY_COUNT) or (ODELAY_VALUE > MAX_IDELAY_COUNT)) then
GenericValueCheckMessage
( HeaderMsg => " Attribute Syntax Warning ",
GenericName => " IDELAY_VALUE ",
EntityName => "/IODELAY",
GenericValue => IDELAY_VALUE,
Unit => "",
ExpectedValueMsg => " The Legal values for this attribute are ",
ExpectedGenericValue => " 0, 1, 2, ..., 62, 63 ",
TailMsg => "",
MsgSeverity => failure
);
end if;
-------- ODELAY_VALUE check
if((ODELAY_VALUE < MIN_ODELAY_COUNT) or (ODELAY_VALUE > MAX_ODELAY_COUNT)) then
GenericValueCheckMessage
( HeaderMsg => " Attribute Syntax Warning ",
GenericName => " ODELAY_VALUE ",
EntityName => "/IODELAY",
GenericValue => ODELAY_VALUE,
Unit => "",
ExpectedValueMsg => " The Legal values for this attribute are ",
ExpectedGenericValue => " 0, 1, 2, ..., 62, 63 ",
TailMsg => "",
MsgSeverity => failure
);
end if;
-------- REFCLK_FREQUENCY check
if((REFCLK_FREQUENCY < MIN_REFCLK_FREQUENCY) or (REFCLK_FREQUENCY > MAX_REFCLK_FREQUENCY)) then
assert false
report "Attribute Syntax Error: Legal values for REFCLK_FREQUENCY are 175.0 to 225.0"
severity Failure;
end if;
wait;
end process prcs_init;
--####################################################################
--##### CALCULATE iDelay #####
--####################################################################
prcs_calc_idelay:process(C_dly, GSR_dly, RST_dly)
variable idelay_count_var : integer :=0;
variable FIRST_TIME : boolean :=true;
variable BaseTime_var : time := 1 ps ;
variable CALC_TAPDELAY : real := 0.0;
begin
if(IDELAY_TYPE = "VARIABLE") then
if((GSR_dly = '1') or (FIRST_TIME))then
idelay_count_var := IDELAY_VALUE;
CALC_TAPDELAY := ((1.0/REFCLK_FREQUENCY) * (1.0/64.0) * ILEAK_ADJUST * 1000000.0) + D_IOBDELAY_OFFSET ;
iDelay <= real(idelay_count_var) * CALC_TAPDELAY * BaseTime_var;
FIRST_TIME := false;
elsif(GSR_dly = '0') then
if(rising_edge(C_dly)) then
if(RST_dly = '1') then
idelay_count_var := IDELAY_VALUE;
elsif((RST_dly = '0') and (CE_dly = '1')) then
if(INC_dly = '1') then
if (idelay_count_var < MAX_IDELAY_COUNT) then
idelay_count_var := idelay_count_var + 1;
else
idelay_count_var := MIN_IDELAY_COUNT;
end if;
elsif(INC_dly = '0') then
if (idelay_count_var > MIN_IDELAY_COUNT) then
idelay_count_var := idelay_count_var - 1;
else
idelay_count_var := MAX_IDELAY_COUNT;
end if;
end if; -- INC_dly
end if; -- RST_dly
iDelay <= real(idelay_count_var) * CALC_TAPDELAY * BaseTime_var;
end if; -- C_dly
end if; -- GSR_dly
end if; -- IDELAY_TYPE
end process prcs_calc_idelay;
--####################################################################
--##### CALCULATE oDelay #####
--####################################################################
prcs_calc_odelay:process(C_dly, GSR_dly, RST_dly)
variable odelay_count_var : integer :=0;
variable FIRST_TIME : boolean :=true;
variable BaseTime_var : time := 1 ps ;
variable CALC_TAPDELAY : real := 0.0;
begin
if((GSR_dly = '1') or (FIRST_TIME))then
odelay_count_var := ODELAY_VALUE;
CALC_TAPDELAY := ((1.0/REFCLK_FREQUENCY) * (1.0/64.0) * ILEAK_ADJUST * 1000000.0) + D_IOBDELAY_OFFSET ;
oDelay <= real(odelay_count_var) * CALC_TAPDELAY * BaseTime_var;
FIRST_TIME := false;
end if;
-- elsif(GSR_dly = '0') then
-- if(rising_edge(C_dly)) then
-- if(RST_dly = '1') then
-- odelay_count_var := ODELAY_VALUE;
-- elsif((RST_dly = '0') and (CE_dly = '1')) then
-- if(INC_dly = '1') then
-- if (odelay_count_var < MAX_ODELAY_COUNT) then
-- odelay_count_var := odelay_count_var + 1;
-- else
-- odelay_count_var := MIN_ODELAY_COUNT;
-- end if;
-- elsif(INC_dly = '0') then
-- if (odelay_count_var > MIN_ODELAY_COUNT) then
-- odelay_count_var := odelay_count_var - 1;
-- else
-- odelay_count_var := MAX_ODELAY_COUNT;
-- end if;
--
-- end if; -- INC_dly
-- end if; -- RST_dly
-- oDelay <= real(odelay_count_var) * CALC_TAPDELAY * BaseTime_var;
-- end if; -- C_dly
-- end if; -- GSR_dly
end process prcs_calc_odelay;
--####################################################################
--##### SELECT IDATA_MUX #####
--####################################################################
prcs_idata_mux:process(DATAIN_dly, IDATAIN_dly, ODATAIN_dly, T_dly)
begin
if(DELAY_SRC = "I") then
idata_mux <= IDATAIN_dly;
elsif(DELAY_SRC = "O") then
idata_mux <= ODATAIN_dly;
elsif(DELAY_SRC = "IO") then
idata_mux <= (IDATAIN_dly and T_dly) or (ODATAIN_dly and (not T_dly));
elsif(DELAY_SRC = "DATAIN") then
idata_mux <= DATAIN_dly;
else
assert false
report "Attribute Syntax Error : Legal values for DELAY_SRC on IODELAY instance are I, O, IO or DATAIN."
severity Failure;
end if;
end process prcs_idata_mux;
--####################################################################
--##### SELECT I/O #####
--####################################################################
prcs_selectio:process(IDATAOUT_Delayed, ODATAOUT_Delayed, T_dly)
begin
if(DELAY_SRC = "IO") then
if(T_dly = '1') then
DATAOUT_zd <= IDATAOUT_delayed;
elsif(T_dly = '0') then
DATAOUT_zd <= ODATAOUT_delayed;
end if;
elsif(DELAY_SRC = "O") then
DATAOUT_zd <= ODATAOUT_delayed;
else
DATAOUT_zd <= IDATAOUT_delayed;
end if;
end process prcs_selectio;
--####################################################################
--##### DELAY IDATA #####
--####################################################################
prcs_idata:process(idata_mux)
-- variable CALC_TAPDELAY : real := ((1.0/REFCLK_FREQUENCY) * K ) + OFFSET;
variable CALC_TAPDELAY : real := ((1.0/REFCLK_FREQUENCY) * (1.0/64.0) * ILEAK_ADJUST * 1000000.0) + D_IOBDELAY_OFFSET ;
begin
if(IDELAY_TYPE = "FIXED") then
IDATAOUT_delayed <= transport idata_mux after ((real(IDELAY_VALUE) * CALC_TAPDELAY) * 1.0 ps);
else
IDATAOUT_delayed <= transport idata_mux after iDelay;
end if;
end process prcs_idata;
--####################################################################
--##### DELAY ODATA #####
--####################################################################
prcs_odata:process(idata_mux)
begin
ODATAOUT_delayed <= transport idata_mux after oDelay;
end process prcs_odata;
--####################################################################
--##### OUTPUT #####
--####################################################################
prcs_output:process(DATAOUT_zd)
begin
DATAOUT <= DATAOUT_zd ;
end process prcs_output;
--####################################################################
end IODELAY_V;
----- CELL ISERDES -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.std_logic_arith.all;
library unisim;
use unisim.vpkg.all;
use unisim.vcomponents.all;
--////////////////////////////////////////////////////////////
--////////////////////////// BSCNTRL /////////////////////////
--////////////////////////////////////////////////////////////
entity bscntrl is
generic(
SRTYPE : string;
INIT_BITSLIPCNT : bit_vector(3 downto 0)
);
port(
CLKDIV_INT : out std_ulogic;
MUXC : out std_ulogic;
BITSLIP : in std_ulogic;
C23 : in std_ulogic;
C45 : in std_ulogic;
C67 : in std_ulogic;
CLK : in std_ulogic;
CLKDIV : in std_ulogic;
DATA_RATE : in std_ulogic;
GSR : in std_ulogic;
R : in std_ulogic;
SEL : in std_logic_vector (1 downto 0)
);
end bscntrl;
architecture bscntrl_V of bscntrl is
-- constant DELAY_FFBSC : time := 300 ns;
-- constant DELAY_MXBSC : time := 60 ns;
constant DELAY_FFBSC : time := 300 ps;
constant DELAY_MXBSC : time := 60 ps;
signal AttrSRtype : integer := 0;
signal q1 : std_ulogic := 'X';
signal q2 : std_ulogic := 'X';
signal q3 : std_ulogic := 'X';
signal mux : std_ulogic := 'X';
signal qhc1 : std_ulogic := 'X';
signal qhc2 : std_ulogic := 'X';
signal qlc1 : std_ulogic := 'X';
signal qlc2 : std_ulogic := 'X';
signal qr1 : std_ulogic := 'X';
signal qr2 : std_ulogic := 'X';
signal mux1 : std_ulogic := 'X';
signal clkdiv_zd : std_ulogic := 'X';
begin
--####################################################################
--##### Initialize #####
--####################################################################
prcs_init:process
begin
if((SRTYPE = "ASYNC") or (SRTYPE = "async")) then
AttrSrtype <= 0;
elsif((SRTYPE = "SYNC") or (SRTYPE = "sync")) then
AttrSrtype <= 1;
end if;
wait;
end process prcs_init;
--####################################################################
--##### Divide by 2 - 8 counter #####
--####################################################################
prcs_div_2_8_cntr:process(qr2, CLK, GSR)
variable clkdiv_int_var : std_ulogic := TO_X01(INIT_BITSLIPCNT(0));
variable q1_var : std_ulogic := TO_X01(INIT_BITSLIPCNT(1));
variable q2_var : std_ulogic := TO_X01(INIT_BITSLIPCNT(2));
variable q3_var : std_ulogic := TO_X01(INIT_BITSLIPCNT(3));
begin
if(GSR = '1') then
clkdiv_int_var := TO_X01(INIT_BITSLIPCNT(0));
q1_var := TO_X01(INIT_BITSLIPCNT(1));
q2_var := TO_X01(INIT_BITSLIPCNT(2));
q3_var := TO_X01(INIT_BITSLIPCNT(3));
elsif(GSR = '0') then
case AttrSRtype is
when 0 =>
--------------- // async SET/RESET
if(qr2 = '1') then
clkdiv_int_var := '0';
q1_var := '0';
q2_var := '0';
q3_var := '0';
elsif (qhc1 = '1') then
clkdiv_int_var := clkdiv_int_var;
q1_var := q1_var;
q2_var := q2_var;
q3_var := q3_var;
else
if(rising_edge(CLK)) then
q3_var := q2_var;
q2_var :=( NOT((NOT clkdiv_int_var) and (NOT q2_var)) and q1_var);
q1_var := clkdiv_int_var;
clkdiv_int_var := mux;
end if;
end if;
when 1 =>
--------------- // sync SET/RESET
if(rising_edge(CLK)) then
if(qr2 = '1') then
clkdiv_int_var := '0';
q1_var := '0';
q2_var := '0';
q3_var := '0';
elsif (qhc1 = '1') then
clkdiv_int_var := clkdiv_int_var;
q1_var := q1_var;
q2_var := q2_var;
q3_var := q3_var;
else
q3_var := q2_var;
q2_var :=( NOT((NOT clkdiv_int_var) and (NOT q2_var)) and q1_var);
q1_var := clkdiv_int_var;
clkdiv_int_var := mux;
end if;
end if;
when others =>
null;
end case;
end if;
q1 <= q1_var after DELAY_FFBSC;
q2 <= q2_var after DELAY_FFBSC;
q3 <= q3_var after DELAY_FFBSC;
clkdiv_zd <= clkdiv_int_var after DELAY_FFBSC;
end process prcs_div_2_8_cntr;
--####################################################################
--##### Divider selections and 4:1 selector mux #####
--####################################################################
prcs_mux_sel:process(sel, c23 , c45 , c67 , clkdiv_zd , q1 , q2 , q3)
begin
case sel is
when "00" =>
mux <= NOT (clkdiv_zd or (c23 and q1)) after DELAY_MXBSC;
when "01" =>
mux <= NOT (q1 or (c45 and q2)) after DELAY_MXBSC;
when "10" =>
mux <= NOT (q2 or (c67 and q3)) after DELAY_MXBSC;
when "11" =>
mux <= NOT (q3) after DELAY_MXBSC;
when others =>
mux <= NOT (clkdiv_zd or (c23 and q1)) after DELAY_MXBSC;
end case;
end process prcs_mux_sel;
--####################################################################
--##### Bitslip control logic #####
--####################################################################
prcs_logictrl:process(qr1, clkdiv)
begin
case AttrSRtype is
when 0 =>
--------------- // async SET/RESET
if(qr1 = '1') then
qlc1 <= '0' after DELAY_FFBSC;
qlc2 <= '0' after DELAY_FFBSC;
elsif(bitslip = '0') then
qlc1 <= qlc1 after DELAY_FFBSC;
qlc2 <= '0' after DELAY_FFBSC;
else
if(rising_edge(clkdiv)) then
qlc1 <= NOT qlc1 after DELAY_FFBSC;
qlc2 <= (bitslip and mux1) after DELAY_FFBSC;
end if;
end if;
when 1 =>
--------------- // sync SET/RESET
if(rising_edge(clkdiv)) then
if(qr1 = '1') then
qlc1 <= '0' after DELAY_FFBSC;
qlc2 <= '0' after DELAY_FFBSC;
elsif(bitslip = '0') then
qlc1 <= qlc1 after DELAY_FFBSC;
qlc2 <= '0' after DELAY_FFBSC;
else
qlc1 <= NOT qlc1 after DELAY_FFBSC;
qlc2 <= (bitslip and mux1) after DELAY_FFBSC;
end if;
end if;
when others =>
null;
end case;
end process prcs_logictrl;
--####################################################################
--##### Mux to select between sdr "0" and ddr "1" #####
--####################################################################
prcs_sdr_ddr_mux:process(qlc1, DATA_RATE)
begin
case DATA_RATE is
when '0' =>
mux1 <= qlc1 after DELAY_MXBSC;
when '1' =>
mux1 <= '1' after DELAY_MXBSC;
when others =>
null;
end case;
end process prcs_sdr_ddr_mux;
--####################################################################
--##### qhc1 and qhc2 #####
--####################################################################
prcs_qhc1_qhc2:process(qr2, CLK)
begin
-- FP TMP -- should CLK and q2 have to be rising_edge
case AttrSRtype is
when 0 =>
--------------- // async SET/RESET
if(qr2 = '1') then
qhc1 <= '0' after DELAY_FFBSC;
qhc2 <= '0' after DELAY_FFBSC;
elsif(rising_edge(CLK)) then
qhc1 <= (qlc2 and (NOT qhc2)) after DELAY_FFBSC;
qhc2 <= qlc2 after DELAY_FFBSC;
end if;
when 1 =>
--------------- // sync SET/RESET
if(rising_edge(CLK)) then
if(qr2 = '1') then
qhc1 <= '0' after DELAY_FFBSC;
qhc2 <= '0' after DELAY_FFBSC;
else
qhc1 <= (qlc2 and (NOT qhc2)) after DELAY_FFBSC;
qhc2 <= qlc2 after DELAY_FFBSC;
end if;
end if;
when others =>
null;
end case;
end process prcs_qhc1_qhc2;
--####################################################################
--##### Mux drives ctrl lines of mux in front of 2nd rnk FFs ####
--####################################################################
prcs_muxc:process(mux1, DATA_RATE)
begin
case DATA_RATE is
when '0' =>
muxc <= mux1 after DELAY_MXBSC;
when '1' =>
muxc <= '0' after DELAY_MXBSC;
when others =>
null;
end case;
end process prcs_muxc;
--####################################################################
--##### Asynchronous set flops #####
--####################################################################
prcs_qr1:process(R, CLKDIV)
begin
-- FP TMP -- should CLKDIV and R have to be rising_edge
case AttrSRtype is
when 0 =>
--------------- // async SET/RESET
if(R = '1') then
qr1 <= '1' after DELAY_FFBSC;
elsif(rising_edge(CLKDIV)) then
qr1 <= '0' after DELAY_FFBSC;
end if;
when 1 =>
--------------- // sync SET/RESET
if(rising_edge(CLKDIV)) then
if(R = '1') then
qr1 <= '1' after DELAY_FFBSC;
else
qr1 <= '0' after DELAY_FFBSC;
end if;
end if;
when others =>
null;
end case;
end process prcs_qr1;
----------------------------------------------------------------------
prcs_qr2:process(R, CLK)
begin
-- FP TMP -- should CLK and R have to be rising_edge
case AttrSRtype is
when 0 =>
--------------- // async SET/RESET
if(R = '1') then
qr2 <= '1' after DELAY_FFBSC;
elsif(rising_edge(CLK)) then
qr2 <= qr1 after DELAY_FFBSC;
end if;
when 1 =>
--------------- // sync SET/RESET
if(rising_edge(CLK)) then
if(R = '1') then
qr2 <= '1' after DELAY_FFBSC;
else
qr2 <= qr1 after DELAY_FFBSC;
end if;
end if;
when others =>
null;
end case;
end process prcs_qr2;
--####################################################################
--##### OUTPUT #####
--####################################################################
prcs_output:process(clkdiv_zd)
begin
CLKDIV_INT <= clkdiv_zd;
end process prcs_output;
--####################################################################
end bscntrl_V;
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.std_logic_arith.all;
library unisim;
use unisim.vpkg.all;
use unisim.vcomponents.all;
--////////////////////////////////////////////////////////////
--//////////////////////// ICE MODULE ////////////////////////
--////////////////////////////////////////////////////////////
entity ice_module is
generic(
SRTYPE : string;
INIT_CE : bit_vector(1 downto 0)
);
port(
ICE : out std_ulogic;
CE1 : in std_ulogic;
CE2 : in std_ulogic;
GSR : in std_ulogic;
NUM_CE : in std_ulogic;
CLKDIV : in std_ulogic;
R : in std_ulogic
);
end ice_module;
architecture ice_V of ice_module is
-- constant DELAY_FFICE : time := 300 ns;
-- constant DELAY_MXICE : time := 60 ns;
constant DELAY_FFICE : time := 300 ps;
constant DELAY_MXICE : time := 60 ps;
signal AttrSRtype : integer := 0;
signal ce1r : std_ulogic := 'X';
signal ce2r : std_ulogic := 'X';
signal cesel : std_logic_vector(1 downto 0) := (others => 'X');
signal ice_zd : std_ulogic := 'X';
begin
--####################################################################
--##### Initialize #####
--####################################################################
prcs_init:process
begin
if((SRTYPE = "ASYNC") or (SRTYPE = "async")) then
AttrSrtype <= 0;
elsif((SRTYPE = "SYNC") or (SRTYPE = "sync")) then
AttrSrtype <= 1;
end if;
wait;
end process prcs_init;
--###################################################################
--##### update cesel #####
--###################################################################
cesel <= NUM_CE & CLKDIV;
--####################################################################
--##### registers #####
--####################################################################
prcs_reg:process(CLKDIV, GSR)
variable ce1r_var : std_ulogic := TO_X01(INIT_CE(1));
variable ce2r_var : std_ulogic := TO_X01(INIT_CE(0));
begin
if(GSR = '1') then
ce1r_var := TO_X01(INIT_CE(1));
ce2r_var := TO_X01(INIT_CE(0));
elsif(GSR = '0') then
case AttrSRtype is
when 0 =>
--------------- // async SET/RESET
if(R = '1') then
ce1r_var := '0';
ce2r_var := '0';
elsif(rising_edge(CLKDIV)) then
ce1r_var := ce1;
ce2r_var := ce2;
end if;
when 1 =>
--------------- // sync SET/RESET
if(rising_edge(CLKDIV)) then
if(R = '1') then
ce1r_var := '0';
ce2r_var := '0';
else
ce1r_var := ce1;
ce2r_var := ce2;
end if;
end if;
when others =>
null;
end case;
end if;
ce1r <= ce1r_var after DELAY_FFICE;
ce2r <= ce2r_var after DELAY_FFICE;
end process prcs_reg;
--####################################################################
--##### Output mux #####
--####################################################################
prcs_mux:process(cesel, ce1, ce1r, ce2r)
begin
case cesel is
when "00" =>
ice_zd <= ce1;
when "01" =>
ice_zd <= ce1;
-- 426606
when "10" =>
ice_zd <= ce2r;
when "11" =>
ice_zd <= ce1r;
when others =>
null;
end case;
end process prcs_mux;
--####################################################################
--##### OUTPUT #####
--####################################################################
prcs_output:process(ice_zd)
begin
ICE <= ice_zd;
end process prcs_output;
end ice_V;
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.std_logic_arith.all;
library unisim;
use unisim.vpkg.all;
use unisim.vcomponents.all;
use unisim.vcomponents.all;
----- CELL ISERDES -----
--////////////////////////////////////////////////////////////
--////////////////////////// ISERDES /////////////////////////
--////////////////////////////////////////////////////////////
entity ISERDES is
generic(
DDR_CLK_EDGE : string := "SAME_EDGE_PIPELINED";
INIT_BITSLIPCNT : bit_vector(3 downto 0) := "0000";
INIT_CE : bit_vector(1 downto 0) := "00";
INIT_RANK1_PARTIAL: bit_vector(4 downto 0) := "00000";
INIT_RANK2 : bit_vector(5 downto 0) := "000000";
INIT_RANK3 : bit_vector(5 downto 0) := "000000";
SERDES : boolean := TRUE;
SRTYPE : string := "ASYNC";
BITSLIP_ENABLE : boolean := false;
DATA_RATE : string := "DDR";
DATA_WIDTH : integer := 4;
INIT_Q1 : bit := '0';
INIT_Q2 : bit := '0';
INIT_Q3 : bit := '0';
INIT_Q4 : bit := '0';
INTERFACE_TYPE : string := "MEMORY";
IOBDELAY : string := "NONE";
IOBDELAY_TYPE : string := "DEFAULT";
IOBDELAY_VALUE : integer := 0;
NUM_CE : integer := 2;
SERDES_MODE : string := "MASTER";
SRVAL_Q1 : bit := '0';
SRVAL_Q2 : bit := '0';
SRVAL_Q3 : bit := '0';
SRVAL_Q4 : bit := '0'
);
port(
O : out std_ulogic;
Q1 : out std_ulogic;
Q2 : out std_ulogic;
Q3 : out std_ulogic;
Q4 : out std_ulogic;
Q5 : out std_ulogic;
Q6 : out std_ulogic;
SHIFTOUT1 : out std_ulogic;
SHIFTOUT2 : out std_ulogic;
BITSLIP : in std_ulogic;
CE1 : in std_ulogic;
CE2 : in std_ulogic;
CLK : in std_ulogic;
CLKDIV : in std_ulogic;
D : in std_ulogic;
DLYCE : in std_ulogic;
DLYINC : in std_ulogic;
DLYRST : in std_ulogic;
OCLK : in std_ulogic;
REV : in std_ulogic;
SHIFTIN1 : in std_ulogic;
SHIFTIN2 : in std_ulogic;
SR : in std_ulogic
);
end ISERDES;
architecture ISERDES_V OF ISERDES is
component bscntrl
generic (
SRTYPE : string;
INIT_BITSLIPCNT : bit_vector(3 downto 0)
);
port(
CLKDIV_INT : out std_ulogic;
MUXC : out std_ulogic;
BITSLIP : in std_ulogic;
C23 : in std_ulogic;
C45 : in std_ulogic;
C67 : in std_ulogic;
CLK : in std_ulogic;
CLKDIV : in std_ulogic;
DATA_RATE : in std_ulogic;
GSR : in std_ulogic;
R : in std_ulogic;
SEL : in std_logic_vector (1 downto 0)
);
end component;
component ice_module
generic(
SRTYPE : string;
INIT_CE : bit_vector(1 downto 0)
);
port(
ICE : out std_ulogic;
CE1 : in std_ulogic;
CE2 : in std_ulogic;
GSR : in std_ulogic;
NUM_CE : in std_ulogic;
CLKDIV : in std_ulogic;
R : in std_ulogic
);
end component;
component IDELAY
generic(
IOBDELAY_VALUE : integer := 0;
IOBDELAY_TYPE : string := "DEFAULT"
);
port(
O : out std_ulogic;
C : in std_ulogic;
CE : in std_ulogic;
I : in std_ulogic;
INC : in std_ulogic;
RST : in std_ulogic
);
end component;
-- constant DELAY_FFINP : time := 300 ns;
-- constant DELAY_MXINP1 : time := 60 ns;
-- constant DELAY_MXINP2 : time := 120 ns;
-- constant DELAY_OCLKDLY : time := 750 ns;
constant SYNC_PATH_DELAY : time := 100 ps;
constant DELAY_FFINP : time := 300 ps;
constant DELAY_MXINP1 : time := 60 ps;
constant DELAY_MXINP2 : time := 120 ps;
constant DELAY_OCLKDLY : time := 750 ps;
constant MAX_DATAWIDTH : integer := 4;
signal BITSLIP_ipd : std_ulogic := 'X';
signal CE1_ipd : std_ulogic := 'X';
signal CE2_ipd : std_ulogic := 'X';
signal CLK_ipd : std_ulogic := 'X';
signal CLKDIV_ipd : std_ulogic := 'X';
signal D_ipd : std_ulogic := 'X';
signal DLYCE_ipd : std_ulogic := 'X';
signal DLYINC_ipd : std_ulogic := 'X';
signal DLYRST_ipd : std_ulogic := 'X';
signal GSR : std_ulogic := '0';
signal GSR_ipd : std_ulogic := 'X';
signal OCLK_ipd : std_ulogic := 'X';
signal REV_ipd : std_ulogic := 'X';
signal SR_ipd : std_ulogic := 'X';
signal SHIFTIN1_ipd : std_ulogic := 'X';
signal SHIFTIN2_ipd : std_ulogic := 'X';
signal BITSLIP_dly : std_ulogic := 'X';
signal CE1_dly : std_ulogic := 'X';
signal CE2_dly : std_ulogic := 'X';
signal CLK_dly : std_ulogic := 'X';
signal CLKDIV_dly : std_ulogic := 'X';
signal D_dly : std_ulogic := 'X';
signal DLYCE_dly : std_ulogic := 'X';
signal DLYINC_dly : std_ulogic := 'X';
signal DLYRST_dly : std_ulogic := 'X';
signal GSR_dly : std_ulogic := 'X';
signal OCLK_dly : std_ulogic := 'X';
signal REV_dly : std_ulogic := 'X';
signal SR_dly : std_ulogic := 'X';
signal SHIFTIN1_dly : std_ulogic := 'X';
signal SHIFTIN2_dly : std_ulogic := 'X';
signal O_zd : std_ulogic := 'X';
signal Q1_zd : std_ulogic := 'X';
signal Q2_zd : std_ulogic := 'X';
signal Q3_zd : std_ulogic := 'X';
signal Q4_zd : std_ulogic := 'X';
signal Q5_zd : std_ulogic := 'X';
signal Q6_zd : std_ulogic := 'X';
signal SHIFTOUT1_zd : std_ulogic := 'X';
signal SHIFTOUT2_zd : std_ulogic := 'X';
signal O_viol : std_ulogic := 'X';
signal Q1_viol : std_ulogic := 'X';
signal Q2_viol : std_ulogic := 'X';
signal Q3_viol : std_ulogic := 'X';
signal Q4_viol : std_ulogic := 'X';
signal Q5_viol : std_ulogic := 'X';
signal Q6_viol : std_ulogic := 'X';
signal SHIFTOUT1_viol : std_ulogic := 'X';
signal SHIFTOUT2_viol : std_ulogic := 'X';
signal AttrSerdes : std_ulogic := 'X';
signal AttrMode : std_ulogic := 'X';
signal AttrDataRate : std_ulogic := 'X';
signal AttrDataWidth : std_logic_vector(3 downto 0) := (others => 'X');
signal AttrInterfaceType : std_ulogic := 'X';
signal AttrBitslipEnable : std_ulogic := 'X';
signal AttrNumCe : std_ulogic := 'X';
signal AttrDdrClkEdge : std_logic_vector(1 downto 0) := (others => 'X');
signal AttrSRtype : integer := 0;
signal AttrIobDelay : integer := 0;
signal sel1 : std_logic_vector(1 downto 0) := (others => 'X');
signal selrnk3 : std_logic_vector(3 downto 0) := (others => 'X');
signal bsmux : std_logic_vector(2 downto 0) := (others => 'X');
signal cntr : std_logic_vector(4 downto 0) := (others => 'X');
signal q1rnk1 : std_ulogic := 'X';
signal q2nrnk1 : std_ulogic := 'X';
signal q5rnk1 : std_ulogic := 'X';
signal q6rnk1 : std_ulogic := 'X';
signal q6prnk1 : std_ulogic := 'X';
signal q1prnk1 : std_ulogic := 'X';
signal q2prnk1 : std_ulogic := 'X';
signal q3rnk1 : std_ulogic := 'X';
signal q4rnk1 : std_ulogic := 'X';
signal dataq5rnk1 : std_ulogic := 'X';
signal dataq6rnk1 : std_ulogic := 'X';
signal dataq3rnk1 : std_ulogic := 'X';
signal dataq4rnk1 : std_ulogic := 'X';
signal oclkmux : std_ulogic := '0';
signal memmux : std_ulogic := '0';
signal q2pmux : std_ulogic := '0';
signal clkdiv_int : std_ulogic := '0';
signal clkdivmux : std_ulogic := '0';
signal q1rnk2 : std_ulogic := 'X';
signal q2rnk2 : std_ulogic := 'X';
signal q3rnk2 : std_ulogic := 'X';
signal q4rnk2 : std_ulogic := 'X';
signal q5rnk2 : std_ulogic := 'X';
signal q6rnk2 : std_ulogic := 'X';
signal dataq1rnk2 : std_ulogic := 'X';
signal dataq2rnk2 : std_ulogic := 'X';
signal dataq3rnk2 : std_ulogic := 'X';
signal dataq4rnk2 : std_ulogic := 'X';
signal dataq5rnk2 : std_ulogic := 'X';
signal dataq6rnk2 : std_ulogic := 'X';
signal muxc : std_ulogic := 'X';
signal q1rnk3 : std_ulogic := 'X';
signal q2rnk3 : std_ulogic := 'X';
signal q3rnk3 : std_ulogic := 'X';
signal q4rnk3 : std_ulogic := 'X';
signal q5rnk3 : std_ulogic := 'X';
signal q6rnk3 : std_ulogic := 'X';
signal c23 : std_ulogic := 'X';
signal c45 : std_ulogic := 'X';
signal c67 : std_ulogic := 'X';
signal sel : std_logic_vector(1 downto 0) := (others => 'X');
signal ice : std_ulogic := 'X';
signal datain : std_ulogic := 'X';
signal idelay_out : std_ulogic := 'X';
signal CLKN_dly : std_ulogic := '0';
begin
---------------------
-- INPUT PATH DELAYs
--------------------
BITSLIP_dly <= BITSLIP after 0 ps;
CE1_dly <= CE1 after 0 ps;
CE2_dly <= CE2 after 0 ps;
CLK_dly <= CLK after 0 ps;
CLKDIV_dly <= CLKDIV after 0 ps;
D_dly <= D after 0 ps;
DLYCE_dly <= DLYCE after 0 ps;
DLYINC_dly <= DLYINC after 0 ps;
DLYRST_dly <= DLYRST after 0 ps;
GSR_dly <= GSR after 0 ps;
OCLK_dly <= OCLK after 0 ps;
REV_dly <= REV after 0 ps;
SHIFTIN1_dly <= SHIFTIN1 after 0 ps;
SHIFTIN2_dly <= SHIFTIN2 after 0 ps;
SR_dly <= SR after 0 ps;
--------------------
-- BEHAVIOR SECTION
--------------------
--####################################################################
--##### Initialize #####
--####################################################################
prcs_init:process
variable AttrSerdes_var : std_ulogic := 'X';
variable AttrMode_var : std_ulogic := 'X';
variable AttrDataRate_var : std_ulogic := 'X';
variable AttrDataWidth_var : std_logic_vector(3 downto 0) := (others => 'X');
variable AttrInterfaceType_var : std_ulogic := 'X';
variable AttrBitslipEnable_var : std_ulogic := 'X';
variable AttrDdrClkEdge_var : std_logic_vector(1 downto 0) := (others => 'X');
variable AttrIobDelay_var : integer := 0;
begin
-------------------- SERDES validity check --------------------
if(SERDES = true) then
AttrSerdes_var := '1';
else
AttrSerdes_var := '0';
end if;
------------- SERDES_MODE validity check --------------------
if((SERDES_MODE = "MASTER") or (SERDES_MODE = "master")) then
AttrMode_var := '0';
elsif((SERDES_MODE = "SLAVE") or (SERDES_MODE = "slave")) then
AttrMode_var := '1';
else
GenericValueCheckMessage
( HeaderMsg => " Attribute Syntax Warning ",
GenericName => "SERDES_MODE ",
EntityName => "/ISERDES",
GenericValue => SERDES_MODE,
Unit => "",
ExpectedValueMsg => " The Legal values for this attribute are ",
ExpectedGenericValue => " MASTER or SLAVE.",
TailMsg => "",
MsgSeverity => FAILURE
);
end if;
------------------ DATA_RATE validity check ------------------
if((DATA_RATE = "DDR") or (DATA_RATE = "ddr")) then
AttrDataRate_var := '0';
elsif((DATA_RATE = "SDR") or (DATA_RATE = "sdr")) then
AttrDataRate_var := '1';
else
GenericValueCheckMessage
( HeaderMsg => " Attribute Syntax Warning ",
GenericName => " DATA_RATE ",
EntityName => "/ISERDES",
GenericValue => DATA_RATE,
Unit => "",
ExpectedValueMsg => " The Legal values for this attribute are ",
ExpectedGenericValue => " DDR or SDR. ",
TailMsg => "",
MsgSeverity => Failure
);
end if;
------------------ DATA_WIDTH validity check ------------------
if((DATA_WIDTH = 2) or (DATA_WIDTH = 3) or (DATA_WIDTH = 4) or
(DATA_WIDTH = 5) or (DATA_WIDTH = 6) or (DATA_WIDTH = 7) or
(DATA_WIDTH = 8) or (DATA_WIDTH = 10)) then
AttrDataWidth_var := CONV_STD_LOGIC_VECTOR(DATA_WIDTH, MAX_DATAWIDTH);
else
GenericValueCheckMessage
( HeaderMsg => " Attribute Syntax Warning ",
GenericName => " DATA_WIDTH ",
EntityName => "/ISERDES",
GenericValue => DATA_WIDTH,
Unit => "",
ExpectedValueMsg => " The Legal values for this attribute are ",
ExpectedGenericValue => " 2, 3, 4, 5, 6, 7, 8, or 10 ",
TailMsg => "",
MsgSeverity => Failure
);
end if;
------------ DATA_WIDTH /DATA_RATE combination check ------------
if((DATA_RATE = "DDR") or (DATA_RATE = "ddr")) then
case (DATA_WIDTH) is
when 4|6|8|10 => null;
when others =>
GenericValueCheckMessage
( HeaderMsg => " Attribute Syntax Warning ",
GenericName => " DATA_WIDTH ",
EntityName => "/ISERDES",
GenericValue => DATA_WIDTH,
Unit => "",
ExpectedValueMsg => " The Legal values for DDR mode are ",
ExpectedGenericValue => " 4, 6, 8, or 10 ",
TailMsg => "",
MsgSeverity => Failure
);
end case;
end if;
if((DATA_RATE = "SDR") or (DATA_RATE = "sdr")) then
case (DATA_WIDTH) is
when 2|3|4|5|6|7|8 => null;
when others =>
GenericValueCheckMessage
( HeaderMsg => " Attribute Syntax Warning ",
GenericName => " DATA_WIDTH ",
EntityName => "/ISERDES",
GenericValue => DATA_WIDTH,
Unit => "",
ExpectedValueMsg => " The Legal values for SDR mode are ",
ExpectedGenericValue => " 2, 3, 4, 5, 6, 7 or 8",
TailMsg => "",
MsgSeverity => Failure
);
end case;
end if;
---------------- INTERFACE_TYPE validity check ---------------
if((INTERFACE_TYPE = "MEMORY") or (INTERFACE_TYPE = "MEMORY")) then
AttrInterfaceType_var := '0';
elsif((INTERFACE_TYPE = "NETWORKING") or (INTERFACE_TYPE = "networking")) then
AttrInterfaceType_var := '1';
else
GenericValueCheckMessage
( HeaderMsg => " Attribute Syntax Warning ",
GenericName => "INTERFACE_TYPE ",
EntityName => "/ISERDES",
GenericValue => INTERFACE_TYPE,
Unit => "",
ExpectedValueMsg => " The Legal values for this attribute are ",
ExpectedGenericValue => " MEMORY or NETWORKING.",
TailMsg => "",
MsgSeverity => FAILURE
);
end if;
---------------- BITSLIP_ENABLE validity check -------------------
if(BITSLIP_ENABLE = false) then
AttrBitslipEnable_var := '0';
elsif(BITSLIP_ENABLE = true) then
AttrBitslipEnable_var := '1';
else
GenericValueCheckMessage
( HeaderMsg => " Attribute Syntax Warning ",
GenericName => " BITSLIP_ENABLE ",
EntityName => "/ISERDES",
GenericValue => BITSLIP_ENABLE,
Unit => "",
ExpectedValueMsg => " The Legal values for this attribute are ",
ExpectedGenericValue => " TRUE or FALSE ",
TailMsg => "",
MsgSeverity => Failure
);
end if;
---------------- NUM_CE validity check -------------------
case NUM_CE is
when 1 =>
AttrNumCe <= '0';
when 2 =>
AttrNumCe <= '1';
when others =>
GenericValueCheckMessage
( HeaderMsg => " Attribute Syntax Warning ",
GenericName => " NUM_CE ",
EntityName => "/ISERDES",
GenericValue => NUM_CE,
Unit => "",
ExpectedValueMsg => " The Legal values for this attribute are ",
ExpectedGenericValue => " 1 or 2 ",
TailMsg => "",
MsgSeverity => Failure
);
end case;
---------------- IOBDELAY validity check -------------------
if((IOBDELAY = "NONE") or (IOBDELAY = "none")) then
AttrIobDelay_var := 0;
elsif((IOBDELAY = "IBUF") or (IOBDELAY = "ibuf")) then
AttrIobDelay_var := 1;
elsif((IOBDELAY = "IFD") or (IOBDELAY = "ifd")) then
AttrIobDelay_var := 2;
elsif((IOBDELAY = "BOTH") or (IOBDELAY = "both")) then
AttrIobDelay_var := 3;
else
GenericValueCheckMessage
( HeaderMsg => " Attribute Syntax Warning ",
GenericName => " IOBDELAY ",
EntityName => "/ISERDES",
GenericValue => IOBDELAY,
Unit => "",
ExpectedValueMsg => " The Legal values for this attribute are ",
ExpectedGenericValue => " NONE or IBUF or IFD or BOTH ",
TailMsg => "",
MsgSeverity => Failure
);
end if;
------------ IOBDELAY_VALUE validity check -----------------
------------ IOBDELAY_TYPE validity check -----------------
--
--
--
------------------ DDR_CLK_EDGE validity check ------------------
if((DDR_CLK_EDGE = "SAME_EDGE_PIPELINED") or (DDR_CLK_EDGE = "same_edge_pipelined")) then
AttrDdrClkEdge_var := "00";
elsif((DDR_CLK_EDGE = "SAME_EDGE") or (DDR_CLK_EDGE = "same_edge")) then
AttrDdrClkEdge_var := "01";
elsif((DDR_CLK_EDGE = "OPPOSITE_EDGE") or (DDR_CLK_EDGE = "opposite_edge")) then
AttrDdrClkEdge_var := "10";
else
GenericValueCheckMessage
( HeaderMsg => " Attribute Syntax Warning ",
GenericName => " DDR_CLK_EDGE ",
EntityName => "/ISERDES",
GenericValue => DDR_CLK_EDGE,
Unit => "",
ExpectedValueMsg => " The Legal values for this attribute are ",
ExpectedGenericValue => " SAME_EDGE_PIPELINED or SAME_EDGE or OPPOSITE_EDGE ",
TailMsg => "",
MsgSeverity => Failure
);
end if;
------------------ DATA_RATE validity check ------------------
if((SRTYPE = "ASYNC") or (SRTYPE = "async")) then
AttrSrtype <= 0;
elsif((SRTYPE = "SYNC") or (SRTYPE = "sync")) then
AttrSrtype <= 1;
else
GenericValueCheckMessage
( HeaderMsg => " Attribute Syntax Warning ",
GenericName => " SRTYPE ",
EntityName => "/ISERDES",
GenericValue => SRTYPE,
Unit => "",
ExpectedValueMsg => " The Legal values for this attribute are ",
ExpectedGenericValue => " ASYNC or SYNC. ",
TailMsg => "",
MsgSeverity => ERROR
);
end if;
---------------------------------------------------------------------
AttrSerdes <= AttrSerdes_var;
AttrMode <= AttrMode_var;
AttrDataRate <= AttrDataRate_var;
AttrDataWidth <= AttrDataWidth_var;
AttrInterfaceType <= AttrInterfaceType_var;
AttrBitslipEnable <= AttrBitslipEnable_var;
AttrDdrClkEdge <= AttrDdrClkEdge_var;
AttrIobDelay <= AttrIobDelay_var;
sel1 <= AttrMode_var & AttrDataRate_var;
selrnk3 <= AttrSerdes_var & AttrBitslipEnable_var & AttrDdrClkEdge_var;
cntr <= AttrDataRate_var & AttrDataWidth_var;
wait;
end process prcs_init;
--###################################################################
--##### SHIFTOUT1 and SHIFTOUT2 #####
--###################################################################
SHIFTOUT2_zd <= q5rnk1;
SHIFTOUT1_zd <= q6rnk1;
--###################################################################
--##### q1rnk1 reg #####
--###################################################################
prcs_Q1_rnk1:process(CLK_dly, GSR_dly, REV_dly, SR_dly)
variable q1rnk1_var : std_ulogic := TO_X01(INIT_Q1);
begin
if(GSR_dly = '1') then
q1rnk1_var := TO_X01(INIT_Q1);
elsif(GSR_dly = '0') then
case AttrSRtype is
when 0 =>
--------------- // async SET/RESET
if((SR_dly = '1') and (not ((REV_dly = '1') and (TO_X01(SRVAL_Q1) = '1')))) then
q1rnk1_var := TO_X01(SRVAL_Q1);
elsif(REV_dly = '1') then
q1rnk1_var := not TO_X01(SRVAL_Q1);
elsif((SR_dly = '0') and (REV_dly = '0')) then
if(ice = '1') then
if(rising_edge(CLK_dly)) then
q1rnk1_var := datain;
end if;
end if;
end if;
when 1 =>
--------------- // sync SET/RESET
if(rising_edge(CLK_dly)) then
if((SR_dly = '1') and (not ((REV_dly = '1') and (TO_X01(SRVAL_Q1) = '1')))) then
q1rnk1_var := TO_X01(SRVAL_Q1);
Elsif(REV_dly = '1') then
q1rnk1_var := not TO_X01(SRVAL_Q1);
elsif((SR_dly = '0') and (REV_dly = '0')) then
if(ice = '1') then
q1rnk1_var := datain;
end if;
end if;
end if;
when others =>
null;
end case;
end if;
q1rnk1 <= q1rnk1_var after DELAY_FFINP;
end process prcs_Q1_rnk1;
--###################################################################
--##### q5rnk1, q6rnk1 and q6prnk1 reg #####
--###################################################################
prcs_Q5Q6Q6p_rnk1:process(CLK_dly, GSR_dly, SR_dly)
variable q5rnk1_var : std_ulogic := TO_X01(INIT_RANK1_PARTIAL(2));
variable q6rnk1_var : std_ulogic := TO_X01(INIT_RANK1_PARTIAL(1));
variable q6prnk1_var : std_ulogic := TO_X01(INIT_RANK1_PARTIAL(0));
begin
if(GSR_dly = '1') then
q5rnk1_var := TO_X01(INIT_RANK1_PARTIAL(2));
q6rnk1_var := TO_X01(INIT_RANK1_PARTIAL(1));
q6prnk1_var := TO_X01(INIT_RANK1_PARTIAL(0));
elsif(GSR_dly = '0') then
case AttrSRtype is
when 0 =>
--------- // async SET/RESET -- Not full featured FFs
if(SR_dly = '1') then
q5rnk1_var := '0';
q6rnk1_var := '0';
q6prnk1_var := '0';
elsif(SR_dly = '0') then
if(rising_edge(CLK_dly)) then
q5rnk1_var := dataq5rnk1;
q6rnk1_var := dataq6rnk1;
q6prnk1_var := q6rnk1;
end if;
end if;
when 1 =>
--------- // sync SET/RESET -- Not full featured FFs
if(rising_edge(CLK_dly)) then
if(SR_dly = '1') then
q5rnk1_var := '0';
q6rnk1_var := '0';
q6prnk1_var := '0';
elsif(SR_dly = '0') then
q5rnk1_var := dataq5rnk1;
q6rnk1_var := dataq6rnk1;
q6prnk1_var := q6rnk1;
end if;
end if;
when others =>
null;
end case;
end if;
q5rnk1 <= q5rnk1_var after DELAY_FFINP;
q6rnk1 <= q6rnk1_var after DELAY_FFINP;
q6prnk1 <= q6prnk1_var after DELAY_FFINP;
end process prcs_Q5Q6Q6p_rnk1;
--###################################################################
--##### q2nrnk1 reg #####
--###################################################################
prcs_Q2_rnk1:process(CLK_dly, GSR_dly, SR_dly, REV_dly)
variable q2nrnk1_var : std_ulogic := TO_X01(INIT_Q2);
begin
if(GSR_dly = '1') then
q2nrnk1_var := TO_X01(INIT_Q2);
elsif(GSR_dly = '0') then
case AttrSRtype is
when 0 =>
--------------- // async SET/RESET
if((SR_dly = '1') and (not ((REV_dly = '1') and (TO_X01(SRVAL_Q2) = '1')))) then
q2nrnk1_var := TO_X01(SRVAL_Q2);
elsif(REV_dly = '1') then
q2nrnk1_var := not TO_X01(SRVAL_Q2);
elsif((SR_dly = '0') and (REV_dly = '0')) then
if(ice = '1') then
if(falling_edge(CLK_dly)) then
q2nrnk1_var := datain;
end if;
end if;
end if;
when 1 =>
--------------- // sync SET/RESET
if(falling_edge(CLK_dly)) then
if((SR_dly = '1') and (not ((REV_dly = '1') and (TO_X01(SRVAL_Q2) = '1')))) then
q2nrnk1_var := TO_X01(SRVAL_Q2);
elsif(REV_dly = '1') then
q2nrnk1_var := not TO_X01(SRVAL_Q2);
elsif((SR_dly = '0') and (REV_dly = '0')) then
if(ice = '1') then
q2nrnk1_var := datain;
end if;
end if;
end if;
when others =>
null;
end case;
end if;
q2nrnk1 <= q2nrnk1_var after DELAY_FFINP;
end process prcs_Q2_rnk1;
--###################################################################
--##### q2prnk1 reg #####
--###################################################################
prcs_Q2p_rnk1:process(q2pmux, GSR_dly, REV_dly, SR_dly)
variable q2prnk1_var : std_ulogic := TO_X01(INIT_Q4);
begin
if(GSR_dly = '1') then
q2prnk1_var := TO_X01(INIT_Q4);
elsif(GSR_dly = '0') then
case AttrSRtype is
when 0 =>
--------------- // async SET/RESET
if((SR_dly = '1') and (not ((REV_dly = '1') and (TO_X01(SRVAL_Q4) = '1')))) then
q2prnk1_var := TO_X01(SRVAL_Q4);
elsif(REV_dly = '1') then
q2prnk1_var := not TO_X01(SRVAL_Q4);
elsif((SR_dly = '0') and (REV_dly = '0')) then
if(ice = '1') then
if(rising_edge(q2pmux)) then
q2prnk1_var := q2nrnk1;
end if;
end if;
end if;
when 1 =>
--------------- // sync SET/RESET
if(rising_edge(q2pmux)) then
if((SR_dly = '1') and (not ((REV_dly = '1') and (TO_X01(SRVAL_Q4) = '1')))) then
q2prnk1_var := TO_X01(SRVAL_Q4);
elsif(REV_dly = '1') then
q2prnk1_var := not TO_X01(SRVAL_Q4);
elsif((SR_dly = '0') and (REV_dly = '0')) then
if(ice = '1') then
q2prnk1_var := q2nrnk1;
end if;
end if;
end if;
when others =>
null;
end case;
end if;
q2prnk1 <= q2prnk1_var after DELAY_FFINP;
end process prcs_Q2p_rnk1;
--###################################################################
--##### q1prnk1 reg #####
--###################################################################
prcs_Q1p_rnk1:process(memmux, GSR_dly, REV_dly, SR_dly)
variable q1prnk1_var : std_ulogic := TO_X01(INIT_Q3);
begin
if(GSR_dly = '1') then
q1prnk1_var := TO_X01(INIT_Q3);
elsif(GSR_dly = '0') then
case AttrSRtype is
when 0 =>
--------------- // async SET/RESET
if((SR_dly = '1') and (not ((REV_dly = '1') and (TO_X01(SRVAL_Q3) = '1')))) then
q1prnk1_var := TO_X01(SRVAL_Q3);
elsif(REV_dly = '1') then
q1prnk1_var := not TO_X01(SRVAL_Q3);
elsif((SR_dly = '0') and (REV_dly = '0')) then
if(ice = '1') then
if(rising_edge(memmux)) then
q1prnk1_var := q1rnk1;
end if;
end if;
end if;
when 1 =>
--------------- // sync SET/RESET
if(rising_edge(memmux)) then
if((SR_dly = '1') and (not ((REV_dly = '1') and (TO_X01(SRVAL_Q3) = '1')))) then
q1prnk1_var := TO_X01(SRVAL_Q3);
elsif(REV_dly = '1') then
q1prnk1_var := not TO_X01(SRVAL_Q3);
elsif((SR_dly = '0') and (REV_dly = '0')) then
if(ice = '1') then
q1prnk1_var := q1rnk1;
end if;
end if;
end if;
when others =>
null;
end case;
end if;
q1prnk1 <= q1prnk1_var after DELAY_FFINP;
end process prcs_Q1p_rnk1;
--###################################################################
--##### q3rnk1 and q4rnk1 reg #####
--###################################################################
prcs_Q3Q4_rnk1:process(memmux, GSR_dly, SR_dly)
variable q3rnk1_var : std_ulogic := TO_X01(INIT_RANK1_PARTIAL(4));
variable q4rnk1_var : std_ulogic := TO_X01(INIT_RANK1_PARTIAL(3));
begin
if(GSR_dly = '1') then
q3rnk1_var := TO_X01(INIT_RANK1_PARTIAL(4));
q4rnk1_var := TO_X01(INIT_RANK1_PARTIAL(3));
elsif(GSR_dly = '0') then
case AttrSRtype is
when 0 =>
-------- // async SET/RESET -- not fully featured FFs
if(SR_dly = '1') then
q3rnk1_var := '0';
q4rnk1_var := '0';
elsif(SR_dly = '0') then
if(rising_edge(memmux)) then
q3rnk1_var := dataq3rnk1;
q4rnk1_var := dataq4rnk1;
end if;
end if;
when 1 =>
-------- // sync SET/RESET -- not fully featured FFs
if(rising_edge(memmux)) then
if(SR_dly = '1') then
q3rnk1_var := '0';
q4rnk1_var := '0';
elsif(SR_dly = '0') then
q3rnk1_var := dataq3rnk1;
q4rnk1_var := dataq4rnk1;
end if;
end if;
when others =>
null;
end case;
end if;
q3rnk1 <= q3rnk1_var after DELAY_FFINP;
q4rnk1 <= q4rnk1_var after DELAY_FFINP;
end process prcs_Q3Q4_rnk1;
--###################################################################
--##### clock mux -- oclkmux with delay element #####
--###################################################################
-- prcs_oclkmux:process(OCLK_dly)
-- begin
-- case AttrOclkDelay is
-- when '0' =>
-- oclkmux <= OCLK_dly after DELAY_MXINP1;
-- when '1' =>
-- oclkmux <= OCLK_dly after DELAY_OCLKDLY;
-- when others =>
-- oclkmux <= OCLK_dly after DELAY_MXINP1;
-- end case;
-- end process prcs_oclkmux;
--
--
--
--///////////////////////////////////////////////////////////////////
--// Mux elements for the 1st Rank
--///////////////////////////////////////////////////////////////////
--###################################################################
--##### memmux -- 4 clock muxes in first rank #####
--###################################################################
prcs_memmux:process(CLK_dly, OCLK_dly)
begin
case AttrInterfaceType is
when '0' =>
memmux <= OCLK_dly after DELAY_MXINP1;
when '1' =>
memmux <= CLK_dly after DELAY_MXINP1;
when others =>
memmux <= OCLK_dly after DELAY_MXINP1;
end case;
end process prcs_memmux;
--###################################################################
--##### q2pmux -- Optional inverter for q2p (4th flop in rank1)
--###################################################################
prcs_q2pmux:process(memmux)
begin
case AttrInterfaceType is
when '0' =>
q2pmux <= not memmux after DELAY_MXINP1;
when '1' =>
q2pmux <= memmux after DELAY_MXINP1;
when others =>
q2pmux <= memmux after DELAY_MXINP1;
end case;
end process prcs_q2pmux;
--###################################################################
--##### data input muxes for q3q4 and q5q6 #####
--###################################################################
prcs_Q3Q4_mux:process(q1prnk1, q2prnk1, q3rnk1, SHIFTIN1_dly, SHIFTIN2_dly)
begin
case sel1 is
when "00" =>
dataq3rnk1 <= q1prnk1 after DELAY_MXINP1;
dataq4rnk1 <= q2prnk1 after DELAY_MXINP1;
when "01" =>
dataq3rnk1 <= q1prnk1 after DELAY_MXINP1;
dataq4rnk1 <= q3rnk1 after DELAY_MXINP1;
when "10" =>
dataq3rnk1 <= SHIFTIN2_dly after DELAY_MXINP1;
dataq4rnk1 <= SHIFTIN1_dly after DELAY_MXINP1;
when "11" =>
dataq3rnk1 <= SHIFTIN1_dly after DELAY_MXINP1;
dataq4rnk1 <= q3rnk1 after DELAY_MXINP1;
when others =>
dataq3rnk1 <= q1prnk1 after DELAY_MXINP1;
dataq4rnk1 <= q2prnk1 after DELAY_MXINP1;
end case;
end process prcs_Q3Q4_mux;
----------------------------------------------------------------------
prcs_Q5Q6_mux:process(q3rnk1, q4rnk1, q5rnk1)
begin
case AttrDataRate is
when '0' =>
dataq5rnk1 <= q3rnk1 after DELAY_MXINP1;
dataq6rnk1 <= q4rnk1 after DELAY_MXINP1;
when '1' =>
dataq5rnk1 <= q4rnk1 after DELAY_MXINP1;
dataq6rnk1 <= q5rnk1 after DELAY_MXINP1;
when others =>
dataq5rnk1 <= q4rnk1 after DELAY_MXINP1;
dataq6rnk1 <= q5rnk1 after DELAY_MXINP1;
end case;
end process prcs_Q5Q6_mux;
---////////////////////////////////////////////////////////////////////
--- 2nd rank of registors
---////////////////////////////////////////////////////////////////////
--###################################################################
--##### clkdivmux to choose between clkdiv_int or CLKDIV #####
--###################################################################
prcs_clkdivmux:process(clkdiv_int, CLKDIV_dly)
begin
case AttrBitslipEnable is
when '0' =>
clkdivmux <= CLKDIV_dly after DELAY_MXINP1;
when '1' =>
clkdivmux <= clkdiv_int after DELAY_MXINP1;
when others =>
clkdivmux <= CLKDIV_dly after DELAY_MXINP1;
end case;
end process prcs_clkdivmux;
--###################################################################
--##### q1rnk2, q2rnk2, q3rnk2,q4rnk2 ,q5rnk2 and q6rnk2 reg #####
--###################################################################
prcs_Q1Q2Q3Q4Q5Q6_rnk2:process(clkdivmux, GSR_dly, SR_dly)
variable q1rnk2_var : std_ulogic := TO_X01(INIT_RANK2(0));
variable q2rnk2_var : std_ulogic := TO_X01(INIT_RANK2(1));
variable q3rnk2_var : std_ulogic := TO_X01(INIT_RANK2(2));
variable q4rnk2_var : std_ulogic := TO_X01(INIT_RANK2(3));
variable q5rnk2_var : std_ulogic := TO_X01(INIT_RANK2(4));
variable q6rnk2_var : std_ulogic := TO_X01(INIT_RANK2(5));
begin
if(GSR_dly = '1') then
q1rnk2_var := TO_X01(INIT_RANK2(0));
q2rnk2_var := TO_X01(INIT_RANK2(1));
q3rnk2_var := TO_X01(INIT_RANK2(2));
q4rnk2_var := TO_X01(INIT_RANK2(3));
q5rnk2_var := TO_X01(INIT_RANK2(4));
q6rnk2_var := TO_X01(INIT_RANK2(5));
elsif(GSR_dly = '0') then
case AttrSRtype is
when 0 =>
--------------- // async SET/RESET
if(SR_dly = '1') then
q1rnk2_var := '0';
q2rnk2_var := '0';
q3rnk2_var := '0';
q4rnk2_var := '0';
q5rnk2_var := '0';
q6rnk2_var := '0';
elsif(SR_dly = '0') then
if(rising_edge(clkdivmux)) then
q1rnk2_var := dataq1rnk2;
q2rnk2_var := dataq2rnk2;
q3rnk2_var := dataq3rnk2;
q4rnk2_var := dataq4rnk2;
q5rnk2_var := dataq5rnk2;
q6rnk2_var := dataq6rnk2;
end if;
end if;
when 1 =>
--------------- // sync SET/RESET
if(rising_edge(clkdivmux)) then
if(SR_dly = '1') then
q1rnk2_var := '0';
q2rnk2_var := '0';
q3rnk2_var := '0';
q4rnk2_var := '0';
q5rnk2_var := '0';
q6rnk2_var := '0';
elsif(SR_dly = '0') then
q1rnk2_var := dataq1rnk2;
q2rnk2_var := dataq2rnk2;
q3rnk2_var := dataq3rnk2;
q4rnk2_var := dataq4rnk2;
q5rnk2_var := dataq5rnk2;
q6rnk2_var := dataq6rnk2;
end if;
end if;
when others =>
null;
end case;
end if;
q1rnk2 <= q1rnk2_var after DELAY_FFINP;
q2rnk2 <= q2rnk2_var after DELAY_FFINP;
q3rnk2 <= q3rnk2_var after DELAY_FFINP;
q4rnk2 <= q4rnk2_var after DELAY_FFINP;
q5rnk2 <= q5rnk2_var after DELAY_FFINP;
q6rnk2 <= q6rnk2_var after DELAY_FFINP;
end process prcs_Q1Q2Q3Q4Q5Q6_rnk2;
--###################################################################
--##### update bitslip mux #####
--###################################################################
bsmux <= AttrBitslipEnable & AttrDataRate & muxc;
--###################################################################
--##### Data mux for 2nd rank of registers ######
--###################################################################
prcs_Q1Q2Q3Q4Q5Q6_rnk2_mux:process(bsmux, q1rnk1, q1prnk1, q2prnk1,
q3rnk1, q4rnk1, q5rnk1, q6rnk1, q6prnk1)
begin
case bsmux is
when "000" | "001" =>
dataq1rnk2 <= q2prnk1 after DELAY_MXINP2;
dataq2rnk2 <= q1prnk1 after DELAY_MXINP2;
dataq3rnk2 <= q4rnk1 after DELAY_MXINP2;
dataq4rnk2 <= q3rnk1 after DELAY_MXINP2;
dataq5rnk2 <= q6rnk1 after DELAY_MXINP2;
dataq6rnk2 <= q5rnk1 after DELAY_MXINP2;
when "100" =>
dataq1rnk2 <= q2prnk1 after DELAY_MXINP2;
dataq2rnk2 <= q1prnk1 after DELAY_MXINP2;
dataq3rnk2 <= q4rnk1 after DELAY_MXINP2;
dataq4rnk2 <= q3rnk1 after DELAY_MXINP2;
dataq5rnk2 <= q6rnk1 after DELAY_MXINP2;
dataq6rnk2 <= q5rnk1 after DELAY_MXINP2;
when "101" =>
dataq1rnk2 <= q1prnk1 after DELAY_MXINP2;
dataq2rnk2 <= q4rnk1 after DELAY_MXINP2;
dataq3rnk2 <= q3rnk1 after DELAY_MXINP2;
dataq4rnk2 <= q6rnk1 after DELAY_MXINP2;
dataq5rnk2 <= q5rnk1 after DELAY_MXINP2;
dataq6rnk2 <= q6prnk1 after DELAY_MXINP2;
when "010" | "011" | "110" | "111" =>
dataq1rnk2 <= q1rnk1 after DELAY_MXINP2;
dataq2rnk2 <= q1prnk1 after DELAY_MXINP2;
dataq3rnk2 <= q3rnk1 after DELAY_MXINP2;
dataq4rnk2 <= q4rnk1 after DELAY_MXINP2;
dataq5rnk2 <= q5rnk1 after DELAY_MXINP2;
dataq6rnk2 <= q6rnk1 after DELAY_MXINP2;
when others =>
dataq1rnk2 <= q2prnk1 after DELAY_MXINP2;
dataq2rnk2 <= q1prnk1 after DELAY_MXINP2;
dataq3rnk2 <= q4rnk1 after DELAY_MXINP2;
dataq4rnk2 <= q3rnk1 after DELAY_MXINP2;
dataq5rnk2 <= q6rnk1 after DELAY_MXINP2;
dataq6rnk2 <= q5rnk1 after DELAY_MXINP2;
end case;
end process prcs_Q1Q2Q3Q4Q5Q6_rnk2_mux;
---////////////////////////////////////////////////////////////////////
--- 3rd rank of registors
---////////////////////////////////////////////////////////////////////
--###################################################################
--##### q1rnk3, q2rnk3, q3rnk3, q4rnk3, q5rnk3 and q6rnk3 reg #####
--###################################################################
prcs_Q1Q2Q3Q4Q5Q6_rnk3:process(CLKDIV_dly, GSR_dly, SR_dly)
variable q1rnk3_var : std_ulogic := TO_X01(INIT_RANK3(0));
variable q2rnk3_var : std_ulogic := TO_X01(INIT_RANK3(1));
variable q3rnk3_var : std_ulogic := TO_X01(INIT_RANK3(2));
variable q4rnk3_var : std_ulogic := TO_X01(INIT_RANK3(3));
variable q5rnk3_var : std_ulogic := TO_X01(INIT_RANK3(4));
variable q6rnk3_var : std_ulogic := TO_X01(INIT_RANK3(5));
begin
if(GSR_dly = '1') then
q1rnk3_var := TO_X01(INIT_RANK3(0));
q2rnk3_var := TO_X01(INIT_RANK3(1));
q3rnk3_var := TO_X01(INIT_RANK3(2));
q4rnk3_var := TO_X01(INIT_RANK3(3));
q5rnk3_var := TO_X01(INIT_RANK3(4));
q6rnk3_var := TO_X01(INIT_RANK3(5));
elsif(GSR_dly = '0') then
case AttrSRtype is
when 0 =>
--------------- // async SET/RESET
if(SR_dly = '1') then
q1rnk3_var := '0';
q2rnk3_var := '0';
q3rnk3_var := '0';
q4rnk3_var := '0';
q5rnk3_var := '0';
q6rnk3_var := '0';
elsif(SR_dly = '0') then
if(rising_edge(CLKDIV_dly)) then
q1rnk3_var := q1rnk2;
q2rnk3_var := q2rnk2;
q3rnk3_var := q3rnk2;
q4rnk3_var := q4rnk2;
q5rnk3_var := q5rnk2;
q6rnk3_var := q6rnk2;
end if;
end if;
when 1 =>
--------------- // sync SET/RESET
if(rising_edge(CLKDIV_dly)) then
if(SR_dly = '1') then
q1rnk3_var := '0';
q2rnk3_var := '0';
q3rnk3_var := '0';
q4rnk3_var := '0';
q5rnk3_var := '0';
q6rnk3_var := '0';
elsif(SR_dly = '0') then
q1rnk3_var := q1rnk2;
q2rnk3_var := q2rnk2;
q3rnk3_var := q3rnk2;
q4rnk3_var := q4rnk2;
q5rnk3_var := q5rnk2;
q6rnk3_var := q6rnk2;
end if;
end if;
when others =>
null;
end case;
end if;
q1rnk3 <= q1rnk3_var after DELAY_FFINP;
q2rnk3 <= q2rnk3_var after DELAY_FFINP;
q3rnk3 <= q3rnk3_var after DELAY_FFINP;
q4rnk3 <= q4rnk3_var after DELAY_FFINP;
q5rnk3 <= q5rnk3_var after DELAY_FFINP;
q6rnk3 <= q6rnk3_var after DELAY_FFINP;
end process prcs_Q1Q2Q3Q4Q5Q6_rnk3;
---////////////////////////////////////////////////////////////////////
--- Outputs
---////////////////////////////////////////////////////////////////////
prcs_Q1Q2_rnk3_mux:process(q1rnk1, q1prnk1, q1rnk2, q1rnk3,
q2nrnk1, q2prnk1, q2rnk2, q2rnk3)
begin
case selrnk3 is
when "0000" | "0100" | "0X00" =>
Q1_zd <= q1prnk1 after DELAY_MXINP1;
Q2_zd <= q2prnk1 after DELAY_MXINP1;
when "0001" | "0101" | "0X01" =>
Q1_zd <= q1rnk1 after DELAY_MXINP1;
Q2_zd <= q2prnk1 after DELAY_MXINP1;
when "0010" | "0110" | "0X10" =>
Q1_zd <= q1rnk1 after DELAY_MXINP1;
Q2_zd <= q2nrnk1 after DELAY_MXINP1;
when "1000" | "1001" | "1010" | "1011" | "10X0" | "10X1" |
"100X" | "101X" | "10XX" =>
Q1_zd <= q1rnk2 after DELAY_MXINP1;
Q2_zd <= q2rnk2 after DELAY_MXINP1;
when "1100" | "1101" | "1110" | "1111" | "11X0" | "11X1" |
"110X" | "111X" | "11XX" =>
Q1_zd <= q1rnk3 after DELAY_MXINP1;
Q2_zd <= q2rnk3 after DELAY_MXINP1;
when others =>
Q1_zd <= q1rnk2 after DELAY_MXINP1;
Q2_zd <= q2rnk2 after DELAY_MXINP1;
end case;
end process prcs_Q1Q2_rnk3_mux;
--------------------------------------------------------------------
prcs_Q3Q4Q5Q6_rnk3_mux:process(q3rnk2, q3rnk3, q4rnk2, q4rnk3,
q5rnk2, q5rnk3, q6rnk2, q6rnk3)
begin
case AttrBitslipEnable is
when '0' =>
Q3_zd <= q3rnk2 after DELAY_MXINP1;
Q4_zd <= q4rnk2 after DELAY_MXINP1;
Q5_zd <= q5rnk2 after DELAY_MXINP1;
Q6_zd <= q6rnk2 after DELAY_MXINP1;
when '1' =>
Q3_zd <= q3rnk3 after DELAY_MXINP1;
Q4_zd <= q4rnk3 after DELAY_MXINP1;
Q5_zd <= q5rnk3 after DELAY_MXINP1;
Q6_zd <= q6rnk3 after DELAY_MXINP1;
when others =>
Q3_zd <= q3rnk2 after DELAY_MXINP1;
Q4_zd <= q4rnk2 after DELAY_MXINP1;
Q5_zd <= q5rnk2 after DELAY_MXINP1;
Q6_zd <= q6rnk2 after DELAY_MXINP1;
end case;
end process prcs_Q3Q4Q5Q6_rnk3_mux;
----------------------------------------------------------------------
----------- Inverted CLK -----------------------------------------
----------------------------------------------------------------------
CLKN_dly <= not CLK_dly;
----------------------------------------------------------------------
----------- Instant BSCNTRL --------------------------------------
----------------------------------------------------------------------
INST_BSCNTRL : BSCNTRL
generic map (
SRTYPE => SRTYPE,
INIT_BITSLIPCNT => INIT_BITSLIPCNT
)
port map (
CLKDIV_INT => clkdiv_int,
MUXC => muxc,
BITSLIP => BITSLIP_dly,
C23 => c23,
C45 => c45,
C67 => c67,
CLK => CLKN_dly,
CLKDIV => CLKDIV_dly,
DATA_RATE => AttrDataRate,
GSR => GSR_dly,
R => SR_dly,
SEL => sel
);
--###################################################################
--##### Set value of the counter in BSCNTRL #####
--###################################################################
prcs_bscntrl_cntr:process
begin
wait for 10 ps;
case cntr is
when "00100" =>
c23<='0'; c45<='0'; c67<='0'; sel<="00";
when "00110" =>
c23<='1'; c45<='0'; c67<='0'; sel<="00";
when "01000" =>
c23<='0'; c45<='0'; c67<='0'; sel<="01";
when "01010" =>
c23<='0'; c45<='1'; c67<='0'; sel<="01";
when "10010" =>
c23<='0'; c45<='0'; c67<='0'; sel<="00";
when "10011" =>
c23<='1'; c45<='0'; c67<='0'; sel<="00";
when "10100" =>
c23<='0'; c45<='0'; c67<='0'; sel<="01";
when "10101" =>
c23<='0'; c45<='1'; c67<='0'; sel<="01";
when "10110" =>
c23<='0'; c45<='0'; c67<='0'; sel<="10";
when "10111" =>
c23<='0'; c45<='0'; c67<='1'; sel<="10";
when "11000" =>
c23<='0'; c45<='0'; c67<='0'; sel<="11";
when others =>
assert FALSE
report "Error : DATA_WIDTH or DATA_RATE has illegal values."
severity failure;
end case;
wait on cntr, c23, c45, c67, sel;
end process prcs_bscntrl_cntr;
----------------------------------------------------------------------
----------- Instant Clock Enable Circuit -------------------------
----------------------------------------------------------------------
INST_ICE : ICE_MODULE
generic map (
SRTYPE => SRTYPE,
INIT_CE => INIT_CE
)
port map (
ICE => ice,
CE1 => CE1_dly,
CE2 => CE2_dly,
GSR => GSR_dly,
NUM_CE => AttrNumCe,
CLKDIV => CLKDIV_dly,
R => SR_dly
);
----------------------------------------------------------------------
----------- Instant IDELAY ---------------------------------------
----------------------------------------------------------------------
INST_IDELAY : IDELAY
generic map (
IOBDELAY_VALUE => IOBDELAY_VALUE,
IOBDELAY_TYPE => IOBDELAY_TYPE
)
port map (
O => idelay_out,
C => CLKDIV_dly,
CE => DLYCE_dly,
I => D_dly,
INC => DLYINC_dly,
RST => DLYRST_dly
);
--###################################################################
--##### IOBDELAY -- Delay input Data #####
--###################################################################
prcs_d_delay:process(D_dly, idelay_out)
begin
case AttrIobDelay is
when 0 =>
O_zd <= D_dly;
datain <= D_dly;
when 1 =>
O_zd <= idelay_out;
datain <= D_dly;
when 2 =>
O_zd <= D_dly;
datain <= idelay_out;
when 3 =>
O_zd <= idelay_out;
datain <= idelay_out;
when others =>
null;
end case;
end process prcs_d_delay;
--####################################################################
--####################################################################
--##### OUTPUT #####
--####################################################################
prcs_output:process(O_zd, Q1_zd, Q2_zd, Q3_zd, Q4_zd, Q5_zd, Q6_zd,
SHIFTOUT1_zd, SHIFTOUT2_zd)
begin
O <= O_zd;
Q1 <= Q1_zd after SYNC_PATH_DELAY;
Q2 <= Q2_zd after SYNC_PATH_DELAY;
Q3 <= Q3_zd after SYNC_PATH_DELAY;
Q4 <= Q4_zd after SYNC_PATH_DELAY;
Q5 <= Q5_zd after SYNC_PATH_DELAY;
Q6 <= Q6_zd after SYNC_PATH_DELAY;
SHIFTOUT1 <= SHIFTOUT1_zd after SYNC_PATH_DELAY;
SHIFTOUT2 <= SHIFTOUT2_zd after SYNC_PATH_DELAY;
end process prcs_output;
--####################################################################
end ISERDES_V;
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library UNISIM;
use UNISIM.VPKG.all;
entity RAM16X1S is
generic (
INIT : bit_vector(15 downto 0) := X"0000"
);
port (
O : out std_ulogic;
A0 : in std_ulogic;
A1 : in std_ulogic;
A2 : in std_ulogic;
A3 : in std_ulogic;
D : in std_ulogic;
WCLK : in std_ulogic;
WE : in std_ulogic
);
end RAM16X1S;
architecture RAM16X1S_V of RAM16X1S is
signal MEM : std_logic_vector(16 downto 0) := ('X' & To_StdLogicVector(INIT));
begin
VITALReadBehavior : process(A0, A1, A2, A3, MEM)
variable Index : integer := 16;
variable Address : std_logic_vector(3 downto 0);
begin
Address := (A3, A2, A1, A0);
Index := SLV_TO_INT(SLV => Address);
O <= MEM(Index);
end process VITALReadBehavior;
VITALWriteBehavior : process(WCLK)
variable Index : integer := 16;
variable Address : std_logic_vector (3 downto 0);
begin
if (rising_edge(WCLK)) then
if (WE = '1') then
Address := (A3, A2, A1, A0);
Index := SLV_TO_INT(SLV => Address);
MEM(Index) <= D after 100 ps;
end if;
end if;
end process VITALWriteBehavior;
end RAM16X1S_V;
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library UNISIM;
use UNISIM.VPKG.all;
entity RAM16X1D is
generic (
INIT : bit_vector(15 downto 0) := X"0000"
);
port (
DPO : out std_ulogic;
SPO : out std_ulogic;
A0 : in std_ulogic;
A1 : in std_ulogic;
A2 : in std_ulogic;
A3 : in std_ulogic;
D : in std_ulogic;
DPRA0 : in std_ulogic;
DPRA1 : in std_ulogic;
DPRA2 : in std_ulogic;
DPRA3 : in std_ulogic;
WCLK : in std_ulogic;
WE : in std_ulogic
);
end RAM16X1D;
architecture RAM16X1D_V of RAM16X1D is
signal MEM : std_logic_vector( 16 downto 0 ) := ('X' & To_StdLogicVector(INIT) );
begin
VITALReadBehavior : process(A0, A1, A2, A3, DPRA3, DPRA2, DPRA1, DPRA0, MEM)
Variable Index_SP : integer := 16 ;
Variable Index_DP : integer := 16 ;
begin
Index_SP := DECODE_ADDR4(ADDRESS => (A3, A2, A1, A0));
Index_DP := DECODE_ADDR4(ADDRESS => (DPRA3, DPRA2, DPRA1, DPRA0));
SPO <= MEM(Index_SP);
DPO <= MEM(Index_DP);
end process VITALReadBehavior;
VITALWriteBehavior : process(WCLK)
variable Index_SP : integer := 16;
variable Index_DP : integer := 16;
begin
Index_SP := DECODE_ADDR4(ADDRESS => (A3, A2, A1, A0));
if ((WE = '1') and (wclk'event) and (wclk'last_value = '0') and (wclk = '1')) then
MEM(Index_SP) <= D after 100 ps;
end if;
end process VITALWriteBehavior;
end RAM16X1D_V;
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library UNISIM;
use UNISIM.VPKG.all;
entity ROM32X1 is
generic (
INIT : bit_vector := X"00000000"
);
port (
O : out std_ulogic;
A0 : in std_ulogic;
A1 : in std_ulogic;
A2 : in std_ulogic;
A3 : in std_ulogic;
A4 : in std_ulogic
);
end ROM32X1;
architecture ROM32X1_V of ROM32X1 is
begin
VITALBehavior : process (A4, A3, A2, A1, A0)
variable INIT_BITS : std_logic_vector(31 downto 0) := To_StdLogicVector(INIT);
variable MEM : std_logic_vector( 32 downto 0 );
variable Index : integer := 32;
variable FIRST_TIME : boolean := true;
begin
if (FIRST_TIME = true) then
MEM := ('X' & INIT_BITS(31 downto 0));
FIRST_TIME := false;
end if;
Index := DECODE_ADDR5(ADDRESS => (A4, A3, A2, A1, A0));
O <= MEM(Index);
end process VITALBehavior;
end ROM32X1_V;
library IEEE;
use IEEE.std_logic_1164.all;
library unisim;
use unisim.Vpkg.all;
entity ROM64X1 is
generic (
INIT : bit_vector := X"0000000000000000"
);
port (
O : out std_ulogic;
A0 : in std_ulogic;
A1 : in std_ulogic;
A2 : in std_ulogic;
A3 : in std_ulogic;
A4 : in std_ulogic;
A5 : in std_ulogic
);
end ROM64X1;
architecture ROM64X1_V of ROM64X1 is
begin
VITALBehavior : process (A5, A4, A3, A2, A1, A0)
variable INIT_BITS : std_logic_vector(63 downto 0) := To_StdLogicVector(INIT);
variable MEM : std_logic_vector( 64 downto 0 );
variable Index : integer := 64;
variable Raddress : std_logic_vector (5 downto 0);
variable FIRST_TIME : boolean := true;
begin
if (FIRST_TIME = true) then
MEM := ('X' & INIT_BITS(63 downto 0));
FIRST_TIME := false;
end if;
Raddress := (A5, A4, A3, A2, A1, A0);
Index := SLV_TO_INT(SLV => Raddress);
O <= MEM(Index);
end process VITALBehavior;
end ROM64X1_V;
library IEEE;
use IEEE.STD_LOGIC_1164.all;
--use IEEE.STD_LOGIC_SIGNED.all;
--use IEEE.STD_LOGIC_ARITH.all;
library grlib;
use grlib.stdlib.all;
library STD;
use STD.TEXTIO.all;
library unisim;
use unisim.vpkg.all;
entity DSP48 is
generic(
AREG : integer := 1;
B_INPUT : string := "DIRECT";
BREG : integer := 1;
CARRYINREG : integer := 1;
CARRYINSELREG : integer := 1;
CREG : integer := 1;
LEGACY_MODE : string := "MULT18X18S";
MREG : integer := 1;
OPMODEREG : integer := 1;
PREG : integer := 1;
SUBTRACTREG : integer := 1
);
port(
BCOUT : out std_logic_vector(17 downto 0);
P : out std_logic_vector(47 downto 0);
PCOUT : out std_logic_vector(47 downto 0);
A : in std_logic_vector(17 downto 0);
B : in std_logic_vector(17 downto 0);
BCIN : in std_logic_vector(17 downto 0);
C : in std_logic_vector(47 downto 0);
CARRYIN : in std_ulogic;
CARRYINSEL : in std_logic_vector(1 downto 0);
CEA : in std_ulogic;
CEB : in std_ulogic;
CEC : in std_ulogic;
CECARRYIN : in std_ulogic;
CECINSUB : in std_ulogic;
CECTRL : in std_ulogic;
CEM : in std_ulogic;
CEP : in std_ulogic;
CLK : in std_ulogic;
OPMODE : in std_logic_vector(6 downto 0);
PCIN : in std_logic_vector(47 downto 0);
RSTA : in std_ulogic;
RSTB : in std_ulogic;
RSTC : in std_ulogic;
RSTCARRYIN : in std_ulogic;
RSTCTRL : in std_ulogic;
RSTM : in std_ulogic;
RSTP : in std_ulogic;
SUBTRACT : in std_ulogic
);
end DSP48;
-- architecture body --
architecture DSP48_V of DSP48 is
procedure invalid_opmode_preg_msg( OPMODE : IN string ;
CARRYINSEL : IN string ) is
variable Message : line;
begin
Write ( Message, string'("OPMODE Input Warning : The OPMODE "));
Write ( Message, OPMODE);
Write ( Message, string'(" with CARRYINSEL "));
Write ( Message, CARRYINSEL);
Write ( Message, string'(" to DSP48 instance "));
Write ( Message, string'("requires attribute PREG set to 1."));
assert false report Message.all severity Warning;
DEALLOCATE (Message);
end invalid_opmode_preg_msg;
procedure invalid_opmode_mreg_msg( OPMODE : IN string ;
CARRYINSEL : IN string ) is
variable Message : line;
begin
Write ( Message, string'("OPMODE Input Warning : The OPMODE "));
Write ( Message, OPMODE);
Write ( Message, string'(" with CARRYINSEL "));
Write ( Message, CARRYINSEL);
Write ( Message, string'(" to DSP48 instance "));
Write ( Message, string'("requires attribute MREG set to 1."));
assert false report Message.all severity Warning;
DEALLOCATE (Message);
end invalid_opmode_mreg_msg;
procedure invalid_opmode_no_mreg_msg( OPMODE : IN string ;
CARRYINSEL : IN string ) is
variable Message : line;
begin
Write ( Message, string'("OPMODE Input Warning : The OPMODE "));
Write ( Message, OPMODE);
Write ( Message, string'(" with CARRYINSEL "));
Write ( Message, CARRYINSEL);
Write ( Message, string'(" to DSP48 instance "));
Write ( Message, string'("requires attribute MREG set to 0."));
assert false report Message.all severity Warning;
DEALLOCATE (Message);
end invalid_opmode_no_mreg_msg;
constant SYNC_PATH_DELAY : time := 100 ps;
constant MAX_P : integer := 48;
constant MAX_PCIN : integer := 48;
constant MAX_OPMODE : integer := 7;
constant MAX_BCIN : integer := 18;
constant MAX_B : integer := 18;
constant MAX_A : integer := 18;
constant MAX_C : integer := 48;
constant MSB_PCIN : integer := 47;
constant MSB_OPMODE : integer := 6;
constant MSB_BCIN : integer := 17;
constant MSB_B : integer := 17;
constant MSB_A : integer := 17;
constant MSB_C : integer := 47;
constant MSB_CARRYINSEL : integer := 1;
constant MSB_P : integer := 47;
constant MSB_PCOUT : integer := 47;
constant MSB_BCOUT : integer := 17;
constant SHIFT_MUXZ : integer := 17;
signal A_ipd : std_logic_vector(MSB_A downto 0) := (others => '0');
signal B_ipd : std_logic_vector(MSB_B downto 0) := (others => '0');
signal BCIN_ipd : std_logic_vector(MSB_BCIN downto 0) := (others => '0');
signal C_ipd : std_logic_vector(MSB_C downto 0) := (others => '0');
signal CARRYIN_ipd : std_ulogic := '0';
signal CARRYINSEL_ipd : std_logic_vector(MSB_CARRYINSEL downto 0) := (others => '0');
signal CEA_ipd : std_ulogic := '0';
signal CEB_ipd : std_ulogic := '0';
signal CEC_ipd : std_ulogic := '0';
signal CECARRYIN_ipd : std_ulogic := '0';
signal CECINSUB_ipd : std_ulogic := '0';
signal CECTRL_ipd : std_ulogic := '0';
signal CEM_ipd : std_ulogic := '0';
signal CEP_ipd : std_ulogic := '0';
signal CLK_ipd : std_ulogic := '0';
signal GSR : std_ulogic := '0';
signal GSR_ipd : std_ulogic := '0';
signal OPMODE_ipd : std_logic_vector(MSB_OPMODE downto 0) := (others => '0');
signal PCIN_ipd : std_logic_vector(MSB_PCIN downto 0) := (others => '0');
signal RSTA_ipd : std_ulogic := '0';
signal RSTB_ipd : std_ulogic := '0';
signal RSTC_ipd : std_ulogic := '0';
signal RSTCARRYIN_ipd : std_ulogic := '0';
signal RSTCTRL_ipd : std_ulogic := '0';
signal RSTM_ipd : std_ulogic := '0';
signal RSTP_ipd : std_ulogic := '0';
signal SUBTRACT_ipd : std_ulogic := '0';
signal A_dly : std_logic_vector(MSB_A downto 0) := (others => '0');
signal B_dly : std_logic_vector(MSB_B downto 0) := (others => '0');
signal BCIN_dly : std_logic_vector(MSB_BCIN downto 0) := (others => '0');
signal C_dly : std_logic_vector(MSB_C downto 0) := (others => '0');
signal CARRYIN_dly : std_ulogic := '0';
signal CARRYINSEL_dly : std_logic_vector(MSB_CARRYINSEL downto 0) := (others => '0');
signal CEA_dly : std_ulogic := '0';
signal CEB_dly : std_ulogic := '0';
signal CEC_dly : std_ulogic := '0';
signal CECARRYIN_dly : std_ulogic := '0';
signal CECINSUB_dly : std_ulogic := '0';
signal CECTRL_dly : std_ulogic := '0';
signal CEM_dly : std_ulogic := '0';
signal CEP_dly : std_ulogic := '0';
signal CLK_dly : std_ulogic := '0';
signal GSR_dly : std_ulogic := '0';
signal OPMODE_dly : std_logic_vector(MSB_OPMODE downto 0) := (others => '0');
signal PCIN_dly : std_logic_vector(MSB_PCIN downto 0) := (others => '0');
signal RSTA_dly : std_ulogic := '0';
signal RSTB_dly : std_ulogic := '0';
signal RSTC_dly : std_ulogic := '0';
signal RSTCARRYIN_dly : std_ulogic := '0';
signal RSTCTRL_dly : std_ulogic := '0';
signal RSTM_dly : std_ulogic := '0';
signal RSTP_dly : std_ulogic := '0';
signal SUBTRACT_dly : std_ulogic := '0';
signal BCOUT_zd : std_logic_vector(MSB_BCOUT downto 0) := (others => '0');
signal P_zd : std_logic_vector(MSB_P downto 0) := (others => '0');
signal PCOUT_zd : std_logic_vector(MSB_PCOUT downto 0) := (others => '0');
--- Internal Signal Declarations
signal qa_o_reg1 : std_logic_vector(MSB_A downto 0) := (others => '0');
signal qa_o_reg2 : std_logic_vector(MSB_A downto 0) := (others => '0');
signal qa_o_mux : std_logic_vector(MSB_A downto 0) := (others => '0');
signal b_o_mux : std_logic_vector(MSB_B downto 0) := (others => '0');
signal qb_o_reg1 : std_logic_vector(MSB_B downto 0) := (others => '0');
signal qb_o_reg2 : std_logic_vector(MSB_B downto 0) := (others => '0');
signal qb_o_mux : std_logic_vector(MSB_B downto 0) := (others => '0');
signal qc_o_reg : std_logic_vector(MSB_C downto 0) := (others => '0');
signal qc_o_mux : std_logic_vector(MSB_C downto 0) := (others => '0');
signal mult_o_int : std_logic_vector((MSB_A + MSB_B + 1) downto 0) := (others => '0');
signal mult_o_reg : std_logic_vector((MSB_A + MSB_B + 1) downto 0) := (others => '0');
signal mult_o_mux : std_logic_vector((MSB_A + MSB_B + 1) downto 0) := (others => '0');
signal opmode_o_reg : std_logic_vector(MSB_OPMODE downto 0) := (others => '0');
signal opmode_o_mux : std_logic_vector(MSB_OPMODE downto 0) := (others => '0');
signal muxx_o_mux : std_logic_vector(MSB_P downto 0) := (others => '0');
signal muxy_o_mux : std_logic_vector(MSB_P downto 0) := (others => '0');
signal muxz_o_mux : std_logic_vector(MSB_P downto 0) := (others => '0');
signal subtract_o_reg : std_ulogic := '0';
signal subtract_o_mux : std_ulogic := '0';
signal carryinsel_o_reg : std_logic_vector(MSB_CARRYINSEL downto 0) := (others => '0');
signal carryinsel_o_mux : std_logic_vector(MSB_CARRYINSEL downto 0) := (others => '0');
signal qcarryin_o_reg1 : std_ulogic := '0';
signal carryin0_o_mux : std_ulogic := '0';
signal carryin1_o_mux : std_ulogic := '0';
signal carryin2_o_mux : std_ulogic := '0';
signal qcarryin_o_reg2 : std_ulogic := '0';
signal carryin_o_mux : std_ulogic := '0';
signal accum_o : std_logic_vector(MSB_P downto 0) := (others => '0');
signal qp_o_reg : std_logic_vector(MSB_P downto 0) := (others => '0');
signal qp_o_mux : std_logic_vector(MSB_P downto 0) := (others => '0');
signal add_i_int : std_logic_vector(47 downto 0) := (others => '0');
signal add_o_int : std_logic_vector(47 downto 0) := (others => '0');
signal reg_p_int : std_logic_vector(47 downto 0) := (others => '0');
signal p_o_int : std_logic_vector(47 downto 0) := (others => '0');
signal subtract1_o_int : std_ulogic := '0';
signal carryinsel1_o_int : std_logic_vector(1 downto 0) := (others => '0');
signal carry1_o_int : std_ulogic := '0';
signal carry2_o_int : std_ulogic := '0';
signal output_x_sig : std_ulogic := '0';
signal RST_META : std_ulogic := '0';
signal DefDelay : time := 10 ps;
begin
---------------------
-- INPUT PATH DELAYs
---------------------
A_dly <= A after 0 ps;
B_dly <= B after 0 ps;
BCIN_dly <= BCIN after 0 ps;
C_dly <= C after 0 ps;
CARRYIN_dly <= CARRYIN after 0 ps;
CARRYINSEL_dly <= CARRYINSEL after 0 ps;
CEA_dly <= CEA after 0 ps;
CEB_dly <= CEB after 0 ps;
CEC_dly <= CEC after 0 ps;
CECARRYIN_dly <= CECARRYIN after 0 ps;
CECINSUB_dly <= CECINSUB after 0 ps;
CECTRL_dly <= CECTRL after 0 ps;
CEM_dly <= CEM after 0 ps;
CEP_dly <= CEP after 0 ps;
CLK_dly <= CLK after 0 ps;
GSR_dly <= GSR after 0 ps;
OPMODE_dly <= OPMODE after 0 ps;
PCIN_dly <= PCIN after 0 ps;
RSTA_dly <= RSTA after 0 ps;
RSTB_dly <= RSTB after 0 ps;
RSTC_dly <= RSTC after 0 ps;
RSTCARRYIN_dly <= RSTCARRYIN after 0 ps;
RSTCTRL_dly <= RSTCTRL after 0 ps;
RSTM_dly <= RSTM after 0 ps;
RSTP_dly <= RSTP after 0 ps;
SUBTRACT_dly <= SUBTRACT after 0 ps;
--------------------
-- BEHAVIOR SECTION
--------------------
--####################################################################
--##### Initialization ###
--####################################################################
prcs_init:process
begin
if((LEGACY_MODE /="NONE") and (LEGACY_MODE /="MULT18X18") and
(LEGACY_MODE /="MULT18X18S")) then
assert false
report "Attribute Syntax Error: The allowed values for LEGACY_MODE are NONE, MULT18X18 or MULT18X18S."
severity Failure;
elsif((LEGACY_MODE ="MULT18X18") and (MREG /= 0)) then
assert false
report "Attribute Syntax Error: The attribute LEGACY_MODE on DSP48 is set to MULT18X18. This requires attribute MREG to be set to 0."
severity Failure;
elsif((LEGACY_MODE ="MULT18X18S") and (MREG /= 1)) then
assert false
report "Attribute Syntax Error: The attribute LEGACY_MODE on DSP48 is set to MULT18X18S. This requires attribute MREG to be set to 1."
severity Failure;
end if;
wait;
end process prcs_init;
--####################################################################
--##### Input Register A with two levels of registers and a mux ###
--####################################################################
prcs_qa_2lvl:process(CLK_dly, GSR_dly)
begin
if(GSR_dly = '1') then
qa_o_reg1 <= ( others => '0');
qa_o_reg2 <= ( others => '0');
elsif (GSR_dly = '0') then
if(rising_edge(CLK_dly)) then
--FP if((RSTA_dly = '1') and (CEA_dly = '1')) then
if(RSTA_dly = '1') then
qa_o_reg1 <= ( others => '0');
qa_o_reg2 <= ( others => '0');
elsif ((RSTA_dly = '0') and (CEA_dly = '1')) then
qa_o_reg2 <= qa_o_reg1;
qa_o_reg1 <= A_dly;
end if;
end if;
end if;
end process prcs_qa_2lvl;
------------------------------------------------------------------
prcs_qa_o_mux:process(A_dly, qa_o_reg1, qa_o_reg2)
begin
case AREG is
when 0 => qa_o_mux <= A_dly;
when 1 => qa_o_mux <= qa_o_reg1;
when 2 => qa_o_mux <= qa_o_reg2;
when others =>
assert false
report "Attribute Syntax Error: The allowed values for AREG are 0 or 1 or 2"
severity Failure;
end case;
end process prcs_qa_o_mux;
--####################################################################
--##### Input Register B with two levels of registers and a mux ###
--####################################################################
prcs_b_in:process(B_dly, BCIN_dly)
begin
if(B_INPUT ="DIRECT") then
b_o_mux <= B_dly;
elsif(B_INPUT ="CASCADE") then
b_o_mux <= BCIN_dly;
else
assert false
report "Attribute Syntax Error: The allowed values for B_INPUT are DIRECT or CASCADE."
severity Failure;
end if;
end process prcs_b_in;
------------------------------------------------------------------
prcs_qb_2lvl:process(CLK_dly, GSR_dly)
begin
if(GSR_dly = '1') then
qb_o_reg1 <= ( others => '0');
qb_o_reg2 <= ( others => '0');
elsif (GSR_dly = '0') then
if(rising_edge(CLK_dly)) then
-- FP if((RSTB_dly = '1') and (CEB_dly = '1')) then
if(RSTB_dly = '1') then
qb_o_reg1 <= ( others => '0');
qb_o_reg2 <= ( others => '0');
elsif ((RSTB_dly = '0') and (CEB_dly = '1')) then
qb_o_reg2 <= qb_o_reg1;
qb_o_reg1 <= b_o_mux;
end if;
end if;
end if;
end process prcs_qb_2lvl;
------------------------------------------------------------------
prcs_qb_o_mux:process(b_o_mux, qb_o_reg1, qb_o_reg2)
begin
case BREG is
when 0 => qb_o_mux <= b_o_mux;
when 1 => qb_o_mux <= qb_o_reg1;
when 2 => qb_o_mux <= qb_o_reg2;
when others =>
assert false
report "Attribute Syntax Error: The allowed values for BREG are 0 or 1 or 2 "
severity Failure;
end case;
end process prcs_qb_o_mux;
--####################################################################
--##### Input Register C with 0, 1, level of registers #####
--####################################################################
prcs_qc_1lvl:process(CLK_dly, GSR_dly)
begin
if(GSR_dly = '1') then
qc_o_reg <= ( others => '0');
elsif (GSR_dly = '0') then
if(rising_edge(CLK_dly)) then
-- FP if((RSTC_dly = '1') and (CEC_dly = '1'))then
if(RSTC_dly = '1') then
qc_o_reg <= ( others => '0');
elsif ((RSTC_dly = '0') and (CEC_dly = '1')) then
qc_o_reg <= C_dly;
end if;
end if;
end if;
end process prcs_qc_1lvl;
------------------------------------------------------------------
prcs_qc_o_mux:process(C_dly, qc_o_reg)
begin
case CREG is
when 0 => qc_o_mux <= C_dly;
when 1 => qc_o_mux <= qc_o_reg;
when others =>
assert false
report "Attribute Syntax Error: The allowed values for CREG are 0 or 1"
severity Failure;
end case;
end process prcs_qc_o_mux;
--####################################################################
--##### Mulitplier #####
--####################################################################
prcs_mult:process(qa_o_mux, qb_o_mux)
begin
-- mult_o_int <= qa_o_mux * qb_o_mux;
mult_o_int <= signed_mul(qa_o_mux, qb_o_mux);
end process prcs_mult;
------------------------------------------------------------------
prcs_mult_reg:process(CLK_dly, GSR_dly)
begin
if(GSR_dly = '1') then
mult_o_reg <= ( others => '0');
elsif (GSR_dly = '0') then
if(rising_edge(CLK_dly)) then
--FP if((RSTM_dly = '1') and (CEM_dly = '1'))then
if(RSTM_dly = '1') then
mult_o_reg <= ( others => '0');
elsif ((RSTM_dly = '0') and (CEM_dly = '1')) then
mult_o_reg <= mult_o_int;
end if;
end if;
end if;
end process prcs_mult_reg;
------------------------------------------------------------------
prcs_mult_mux:process(mult_o_reg, mult_o_int)
begin
case MREG is
when 0 => mult_o_mux <= mult_o_int;
when 1 => mult_o_mux <= mult_o_reg;
when others =>
assert false
report "Attribute Syntax Error: The allowed values for MREG are 0 or 1"
severity Failure;
end case;
end process prcs_mult_mux;
--####################################################################
--##### OpMode #####
--####################################################################
prcs_opmode_reg:process(CLK_dly, GSR_dly)
begin
if(GSR_dly = '1') then
opmode_o_reg <= ( others => '0');
elsif (GSR_dly = '0') then
if(rising_edge(CLK_dly)) then
--FP if((RSTCTRL_dly = '1') and (CECTRL_dly = '1'))then
if(RSTCTRL_dly = '1') then
opmode_o_reg <= ( others => '0');
elsif ((RSTCTRL_dly = '0') and (CECTRL_dly = '1')) then
opmode_o_reg <= OPMODE_dly;
end if;
end if;
end if;
end process prcs_opmode_reg;
------------------------------------------------------------------
prcs_opmode_mux:process(opmode_o_reg, OPMODE_dly)
begin
case OPMODEREG is
when 0 => opmode_o_mux <= OPMODE_dly;
when 1 => opmode_o_mux <= opmode_o_reg;
when others =>
assert false
report "Attribute Syntax Error: The allowed values for OPMODEREG are 0 or 1"
severity Failure;
end case;
end process prcs_opmode_mux;
--####################################################################
--##### MUX_XYZ #####
--####################################################################
-- prcs_mux_xyz:process(opmode_o_mux,,,, FP)
-- FP ?? more (Z) should be added to sensitivity list
prcs_mux_xyz:process(opmode_o_mux, qp_o_mux, qa_o_mux, qb_o_mux, mult_o_mux,
qc_o_mux, PCIN_dly, output_x_sig)
begin
if(output_x_sig = '1') then
muxx_o_mux(MSB_P downto 0) <= ( others => 'X');
muxy_o_mux(MSB_P downto 0) <= ( others => 'X');
muxz_o_mux(MSB_P downto 0) <= ( others => 'X');
elsif(output_x_sig = '0') then
--MUX_X -----
case opmode_o_mux(1 downto 0) is
when "00" => muxx_o_mux <= ( others => '0');
-- FP ?? better way to concat ? and sign extend ?
when "01" => muxx_o_mux((MAX_A + MAX_B - 1) downto 0) <= mult_o_mux;
if(mult_o_mux(MAX_A + MAX_B - 1) = '1') then
muxx_o_mux(MSB_PCIN downto (MAX_A + MAX_B)) <= ( others => '1');
elsif (mult_o_mux(MSB_A + MSB_B + 1) = '0') then
muxx_o_mux(MSB_PCIN downto (MAX_A + MAX_B)) <= ( others => '0');
end if;
when "10" => muxx_o_mux <= qp_o_mux;
when "11" => if(qa_o_mux(MSB_A) = '0') then
muxx_o_mux(MSB_P downto 0) <= ("000000000000" & qa_o_mux & qb_o_mux);
elsif(qa_o_mux(MSB_A) = '1') then
muxx_o_mux(MSB_P downto 0) <= ("111111111111" & qa_o_mux & qb_o_mux);
end if;
-- when "11" => muxx_o_mux(MSB_B downto 0) <= qb_o_mux;
-- muxx_o_mux((MAX_A + MAX_B - 1) downto MAX_B) <= qa_o_mux;
--
-- if(mult_o_mux(MAX_A + MAX_B - 1) = '1') then
-- muxx_o_mux(MSB_PCIN downto (MAX_A + MAX_B)) <= ( others => '1');
-- elsif (mult_o_mux(MSB_A + MSB_B + 1) = '0') then
-- muxx_o_mux(MSB_PCIN downto (MAX_A + MAX_B)) <= ( others => '0');
-- end if;
when others => null;
-- assert false
-- report "Error: input signal OPMODE(1 downto 0) has unknown values"
-- severity Failure;
end case;
--MUX_Y -----
case opmode_o_mux(3 downto 2) is
when "00" => muxy_o_mux <= ( others => '0');
when "01" => muxy_o_mux <= ( others => '0');
when "10" => null;
when "11" => muxy_o_mux <= qc_o_mux;
when others => null;
-- assert false
-- report "Error: input signal OPMODE(3 downto 2) has unknown values"
-- severity Failure;
end case;
--MUX_Z -----
case opmode_o_mux(6 downto 4) is
when "000" => muxz_o_mux <= ( others => '0');
when "001" => muxz_o_mux <= PCIN_dly;
when "010" => muxz_o_mux <= qp_o_mux;
when "011" => muxz_o_mux <= qc_o_mux;
when "100" => null;
-- FP ?? better shift possible ?
when "101" => if(PCIN_dly(MSB_PCIN) = '0') then
muxz_o_mux <= ( others => '0');
elsif(PCIN_dly(MSB_PCIN) = '1') then
muxz_o_mux <= ( others => '1');
end if;
muxz_o_mux ((MSB_PCIN - SHIFT_MUXZ) downto 0) <= PCIN_dly(MSB_PCIN downto SHIFT_MUXZ );
when "110" => if(qp_o_mux(MSB_P) = '0') then
muxz_o_mux <= ( others => '0');
elsif(qp_o_mux(MSB_P) = '1') then
muxz_o_mux <= ( others => '1');
end if;
-- muxz_o_mux ((MAX_P - SHIFT_MUXZ) downto 0) <= qp_o_mux(MSB_P downto (SHIFT_MUXZ - 1));
muxz_o_mux ((MSB_P - SHIFT_MUXZ) downto 0) <= qp_o_mux(MSB_P downto SHIFT_MUXZ );
when "111" => null;
when others => null;
-- assert false
-- report "Error: input signal OPMODE(6 downto 4) has unknown values"
-- severity Failure;
end case;
end if;
end process prcs_mux_xyz;
--####################################################################
--##### Subtract #####
--####################################################################
prcs_subtract_reg:process(CLK_dly, GSR_dly)
begin
if(GSR_dly = '1') then
subtract_o_reg <= '0';
elsif (GSR_dly = '0') then
if(rising_edge(CLK_dly)) then
if(RSTCTRL_dly = '1') then
subtract_o_reg <= '0';
elsif ((RSTCTRL_dly = '0') and (CECINSUB_dly = '1'))then
subtract_o_reg <= SUBTRACT_dly;
end if;
end if;
end if;
end process prcs_subtract_reg;
------------------------------------------------------------------
prcs_subtract_mux:process(subtract_o_reg, SUBTRACT_dly)
begin
case SUBTRACTREG is
when 0 => subtract_o_mux <= SUBTRACT_dly;
when 1 => subtract_o_mux <= subtract_o_reg;
when others =>
assert false
report "Attribute Syntax Error: The allowed values for SUBTRACTREG are 0 or 1"
severity Failure;
end case;
end process prcs_subtract_mux;
--####################################################################
--##### CarryInSel #####
--####################################################################
prcs_carryinsel_reg:process(CLK_dly, GSR_dly)
begin
if(GSR_dly = '1') then
carryinsel_o_reg <= ( others => '0');
elsif (GSR_dly = '0') then
if(rising_edge(CLK_dly)) then
--FP if((RSTCTRL_dly = '1') and (CECTRL_dly = '1'))then
if(RSTCTRL_dly = '1') then
carryinsel_o_reg <= ( others => '0');
elsif ((RSTCTRL_dly = '0') and (CECTRL_dly = '1')) then
carryinsel_o_reg <= CARRYINSEL_dly;
end if;
end if;
end if;
end process prcs_carryinsel_reg;
------------------------------------------------------------------
prcs_carryinsel_mux:process(carryinsel_o_reg, CARRYINSEL_dly)
begin
case CARRYINSELREG is
when 0 => carryinsel_o_mux <= CARRYINSEL_dly;
when 1 => carryinsel_o_mux <= carryinsel_o_reg;
when others =>
assert false
report "Attribute Syntax Error: The allowed values for CARRYINSELREG are 0 or 1"
severity Failure;
end case;
end process prcs_carryinsel_mux;
--####################################################################
--##### CarryIn #####
--####################################################################
prcs_carryin_reg1:process(CLK_dly, GSR_dly)
begin
if(GSR_dly = '1') then
qcarryin_o_reg1 <= '0';
elsif (GSR_dly = '0') then
if(rising_edge(CLK_dly)) then
if(RSTCARRYIN_dly = '1') then
qcarryin_o_reg1 <= '0';
elsif((RSTCARRYIN_dly = '0') and (CECINSUB_dly = '1')) then
qcarryin_o_reg1 <= CARRYIN_dly;
end if;
end if;
end if;
end process prcs_carryin_reg1;
------------------------------------------------------------------
prcs_carryin0_mux:process(qcarryin_o_reg1, CARRYIN_dly)
begin
case CARRYINREG is
when 0 => carryin0_o_mux <= CARRYIN_dly;
when 1 => carryin0_o_mux <= qcarryin_o_reg1;
when others =>
assert false
report "Attribute Syntax Error: The allowed values for CARRYINREG are 0 or 1"
severity Failure;
end case;
end process prcs_carryin0_mux;
------------------------------------------------------------------
prcs_carryin1_mux:process(opmode_o_mux(0), opmode_o_mux(1), qa_o_mux(17), qb_o_mux(17))
begin
case (opmode_o_mux(0) and opmode_o_mux(1)) is
when '0' => carryin1_o_mux <= NOT(qa_o_mux(17) xor qb_o_mux(17));
when '1' => carryin1_o_mux <= NOT qa_o_mux(17);
when others => null;
-- assert false
-- report "Error: UNKOWN Value at PORT OPMODE(1) "
-- severity Failure;
end case;
end process prcs_carryin1_mux;
------------------------------------------------------------------
prcs_carryin2_mux:process(opmode_o_mux(0), opmode_o_mux(1), qp_o_mux(47), PCIN_dly(47))
begin
if(((opmode_o_mux(1) = '1') and (opmode_o_mux(0) = '0')) or
(opmode_o_mux(5) = '1') or
(NOT ((opmode_o_mux(6) = '1') or (opmode_o_mux(4) = '1')))) then
carryin2_o_mux <= NOT qp_o_mux(47);
else
carryin2_o_mux <= NOT PCIN_dly(47);
end if;
end process prcs_carryin2_mux;
------------------------------------------------------------------
prcs_carryin_reg2:process(CLK_dly, GSR_dly)
begin
if(GSR_dly = '1') then
qcarryin_o_reg2 <= '0';
elsif (GSR_dly = '0') then
if(rising_edge(CLK_dly)) then
if(RSTCARRYIN_dly = '1') then
qcarryin_o_reg2 <= '0';
elsif ((RSTCARRYIN_dly = '0') and (CECARRYIN_dly = '1'))then
qcarryin_o_reg2 <= carryin1_o_mux;
end if;
end if;
end if;
end process prcs_carryin_reg2;
------------------------------------------------------------------
prcs_carryin_mux:process(carryinsel_o_mux, carryin0_o_mux, carryin1_o_mux, carryin2_o_mux, qcarryin_o_reg2)
begin
case carryinsel_o_mux is
when "00" => carryin_o_mux <= carryin0_o_mux;
when "01" => carryin_o_mux <= carryin2_o_mux;
when "10" => carryin_o_mux <= carryin1_o_mux;
when "11" => carryin_o_mux <= qcarryin_o_reg2;
when others => null;
-- assert false
-- report "Error: UNKOWN Value at carryinsel_o_mux"
-- severity Failure;
end case;
end process prcs_carryin_mux;
--####################################################################
--##### ACCUM #####
--####################################################################
--
-- NOTE : moved it to the drc process
--
-- prcs_accum_xyz:process(muxx_o_mux, muxy_o_mux, muxz_o_mux, subtract_o_mux, carryin_o_mux )
-- variable carry_var : integer;
-- begin
-- if(carryin_o_mux = '1') then
-- carry_var := 1;
-- elsif (carryin_o_mux = '0') then
-- carry_var := 0;
---- else
---- assert false
---- report "Error : CarryIn has Unknown value."
---- severity Failure;
-- end if;
-- if(subtract_o_mux = '0') then
-- accum_o <= muxz_o_mux + (muxx_o_mux + muxy_o_mux + carryin_o_mux);
-- elsif(subtract_o_mux = '1') then
-- accum_o <= muxz_o_mux - (muxx_o_mux + muxy_o_mux + carryin_o_mux);
---- else
---- assert false
---- report "Error : Subtract has Unknown value."
---- severity Failure;
-- end if;
-- end process prcs_accum_xyz;
--####################################################################
--##### PCOUT #####
--####################################################################
prcs_qp_reg:process(CLK_dly, GSR_dly)
begin
if(GSR_dly = '1') then
qp_o_reg <= ( others => '0');
elsif (GSR_dly = '0') then
if(rising_edge(CLK_dly)) then
if(RSTP_dly = '1') then
qp_o_reg <= ( others => '0');
elsif ((RSTP_dly = '0') and (CEP_dly = '1')) then
qp_o_reg <= accum_o;
end if;
end if;
end if;
end process prcs_qp_reg;
------------------------------------------------------------------
prcs_qp_mux:process(accum_o, qp_o_reg)
begin
case PREG is
when 0 => qp_o_mux <= accum_o;
when 1 => qp_o_mux <= qp_o_reg;
when others =>
assert false
report "Attribute Syntax Error: The allowed values for PREG are 0 or 1"
severity Failure;
end case;
end process prcs_qp_mux;
--####################################################################
--##### ZERO_DELAY_OUTPUTS #####
--####################################################################
prcs_zero_delay_outputs:process(qb_o_mux, qp_o_mux)
begin
BCOUT_zd <= qb_o_mux;
P_zd <= qp_o_mux;
PCOUT_zd <= qp_o_mux;
end process prcs_zero_delay_outputs;
--####################################################################
--##### PMODE DRC #####
--####################################################################
prcs_opmode_drc:process(opmode_o_mux, carryinsel_o_mux, subtract_o_mux,
muxx_o_mux, muxy_o_mux, muxz_o_mux, carryin_o_mux)
variable Message : line;
variable invalid_opmode_flg : boolean := true;
variable add_flg : boolean := true;
variable opmode_carryinsel_var : std_logic_vector(8 downto 0) := (others => '0');
begin
-- if now > 100 ns then
-- The above line was cusing the intial values of A, B or C not trigger
opmode_carryinsel_var := opmode_o_mux & carryinsel_o_mux;
case opmode_carryinsel_var is
when "000000000" =>
invalid_opmode_flg := true ;
add_flg := true ;
output_x_sig <= '0';
when "000001000" =>
if (PREG /= 1) then
accum_o <= (others => 'X');
add_flg := false;
if(invalid_opmode_flg) then
invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), slv_to_str(carryinsel_o_mux));
end if;
invalid_opmode_flg := false;
else
invalid_opmode_flg := true;
add_flg := true;
output_x_sig <= '0';
end if;
when "000001100" =>
invalid_opmode_flg := true ;
add_flg := true ;
output_x_sig <= '0';
when "000010100" =>
invalid_opmode_flg := true ;
add_flg := true ;
output_x_sig <= '0';
when "000110000" =>
invalid_opmode_flg := true ;
add_flg := true ;
output_x_sig <= '0';
when "000111000" =>
if (PREG /= 1) then
accum_o <= (others => 'X');
add_flg := false;
if(invalid_opmode_flg) then
invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), slv_to_str(carryinsel_o_mux));
end if;
invalid_opmode_flg := false;
else
invalid_opmode_flg := true;
add_flg := true;
output_x_sig <= '0';
end if;
when "000111001" =>
if (PREG /= 1) then
accum_o <= (others => 'X');
add_flg := false;
if(invalid_opmode_flg) then
invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), slv_to_str(carryinsel_o_mux));
end if;
invalid_opmode_flg := false;
else
invalid_opmode_flg := true;
add_flg := true;
output_x_sig <= '0';
end if;
when "000111100" =>
invalid_opmode_flg := true ;
add_flg := true ;
output_x_sig <= '0';
when "000111110" =>
invalid_opmode_flg := true ;
add_flg := true ;
output_x_sig <= '0';
when "001000000" =>
invalid_opmode_flg := true ;
add_flg := true ;
output_x_sig <= '0';
when "001001000" =>
if (PREG /= 1) then
accum_o <= (others => 'X');
add_flg := false;
if(invalid_opmode_flg) then
invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), slv_to_str(carryinsel_o_mux));
end if;
invalid_opmode_flg := false;
else
invalid_opmode_flg := true;
add_flg := true;
output_x_sig <= '0';
end if;
when "001001001" =>
if (PREG /= 1) then
accum_o <= (others => 'X');
add_flg := false;
if(invalid_opmode_flg) then
invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), slv_to_str(carryinsel_o_mux));
end if;
invalid_opmode_flg := false;
else
invalid_opmode_flg := true;
add_flg := true;
output_x_sig <= '0';
end if;
when "001001100" =>
invalid_opmode_flg := true ;
add_flg := true ;
output_x_sig <= '0';
when "001001101" =>
invalid_opmode_flg := true ;
add_flg := true ;
output_x_sig <= '0';
when "001001110" =>
invalid_opmode_flg := true ;
add_flg := true ;
output_x_sig <= '0';
when "001010100" =>
invalid_opmode_flg := true ;
add_flg := true ;
output_x_sig <= '0';
when "001010101" =>
invalid_opmode_flg := true ;
add_flg := true ;
output_x_sig <= '0';
when "001010110" =>
invalid_opmode_flg := true ;
add_flg := true ;
output_x_sig <= '0';
when "001010111" =>
invalid_opmode_flg := true ;
add_flg := true ;
output_x_sig <= '0';
when "001110000" =>
invalid_opmode_flg := true ;
add_flg := true ;
output_x_sig <= '0';
when "001110001" =>
invalid_opmode_flg := true ;
add_flg := true ;
output_x_sig <= '0';
when "001111000" =>
if (PREG /= 1) then
accum_o <= (others => 'X');
add_flg := false;
if(invalid_opmode_flg) then
invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), slv_to_str(carryinsel_o_mux));
end if;
invalid_opmode_flg := false;
else
invalid_opmode_flg := true;
add_flg := true;
output_x_sig <= '0';
end if;
when "001111001" =>
if (PREG /= 1) then
accum_o <= (others => 'X');
add_flg := false;
if(invalid_opmode_flg) then
invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), slv_to_str(carryinsel_o_mux));
end if;
invalid_opmode_flg := false;
else
invalid_opmode_flg := true;
add_flg := true;
output_x_sig <= '0';
end if;
when "001111100" =>
invalid_opmode_flg := true ;
add_flg := true ;
output_x_sig <= '0';
when "001111101" =>
invalid_opmode_flg := true ;
add_flg := true ;
output_x_sig <= '0';
when "001111110" =>
invalid_opmode_flg := true ;
add_flg := true ;
output_x_sig <= '0';
when "010000000" =>
if (PREG /= 1) then
accum_o <= (others => 'X');
add_flg := false;
if(invalid_opmode_flg) then
invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), slv_to_str(carryinsel_o_mux));
end if;
invalid_opmode_flg := false;
else
invalid_opmode_flg := true;
add_flg := true;
output_x_sig <= '0';
end if;
when "010001000" =>
if (PREG /= 1) then
accum_o <= (others => 'X');
add_flg := false;
if(invalid_opmode_flg) then
invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), slv_to_str(carryinsel_o_mux));
end if;
invalid_opmode_flg := false;
else
invalid_opmode_flg := true;
add_flg := true;
output_x_sig <= '0';
end if;
when "010001100" =>
if (PREG /= 1) then
accum_o <= (others => 'X');
add_flg := false;
if(invalid_opmode_flg) then
invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), slv_to_str(carryinsel_o_mux));
end if;
invalid_opmode_flg := false;
else
invalid_opmode_flg := true;
add_flg := true;
output_x_sig <= '0';
end if;
when "010001101" =>
if (PREG /= 1) then
accum_o <= (others => 'X');
add_flg := false;
if(invalid_opmode_flg) then
invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), slv_to_str(carryinsel_o_mux));
end if;
invalid_opmode_flg := false;
else
invalid_opmode_flg := true;
add_flg := true;
output_x_sig <= '0';
end if;
when "010010100" =>
if (PREG /= 1) then
accum_o <= (others => 'X');
add_flg := false;
if(invalid_opmode_flg) then
invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), slv_to_str(carryinsel_o_mux));
end if;
invalid_opmode_flg := false;
else
invalid_opmode_flg := true;
add_flg := true;
output_x_sig <= '0';
end if;
when "010010101" =>
if (PREG /= 1) then
accum_o <= (others => 'X');
add_flg := false;
if(invalid_opmode_flg) then
invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), slv_to_str(carryinsel_o_mux));
end if;
invalid_opmode_flg := false;
else
invalid_opmode_flg := true;
add_flg := true;
output_x_sig <= '0';
end if;
when "010110000" =>
if (PREG /= 1) then
accum_o <= (others => 'X');
add_flg := false;
if(invalid_opmode_flg) then
invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), slv_to_str(carryinsel_o_mux));
end if;
invalid_opmode_flg := false;
else
invalid_opmode_flg := true;
add_flg := true;
output_x_sig <= '0';
end if;
when "010110001" =>
if (PREG /= 1) then
accum_o <= (others => 'X');
add_flg := false;
if(invalid_opmode_flg) then
invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), slv_to_str(carryinsel_o_mux));
end if;
invalid_opmode_flg := false;
else
invalid_opmode_flg := true;
add_flg := true;
output_x_sig <= '0';
end if;
when "010111000" =>
if (PREG /= 1) then
accum_o <= (others => 'X');
add_flg := false;
if(invalid_opmode_flg) then
invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), slv_to_str(carryinsel_o_mux));
end if;
invalid_opmode_flg := false;
else
invalid_opmode_flg := true;
add_flg := true;
output_x_sig <= '0';
end if;
when "010111001" =>
if (PREG /= 1) then
accum_o <= (others => 'X');
add_flg := false;
if(invalid_opmode_flg) then
invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), slv_to_str(carryinsel_o_mux));
end if;
invalid_opmode_flg := false;
else
invalid_opmode_flg := true;
add_flg := true;
output_x_sig <= '0';
end if;
when "010111100" =>
if (PREG /= 1) then
accum_o <= (others => 'X');
add_flg := false;
if(invalid_opmode_flg) then
invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), slv_to_str(carryinsel_o_mux));
end if;
invalid_opmode_flg := false;
else
invalid_opmode_flg := true;
add_flg := true;
output_x_sig <= '0';
end if;
when "010111101" =>
if (PREG /= 1) then
accum_o <= (others => 'X');
add_flg := false;
if(invalid_opmode_flg) then
invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), slv_to_str(carryinsel_o_mux));
end if;
invalid_opmode_flg := false;
else
invalid_opmode_flg := true;
add_flg := true;
output_x_sig <= '0';
end if;
when "010111110" =>
if (PREG /= 1) then
accum_o <= (others => 'X');
add_flg := false;
if(invalid_opmode_flg) then
invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), slv_to_str(carryinsel_o_mux));
end if;
invalid_opmode_flg := false;
else
invalid_opmode_flg := true;
add_flg := true;
output_x_sig <= '0';
end if;
when "011000000" =>
invalid_opmode_flg := true ;
add_flg := true ;
output_x_sig <= '0';
when "011001000" =>
if (PREG /= 1) then
accum_o <= (others => 'X');
add_flg := false;
if(invalid_opmode_flg) then
invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), slv_to_str(carryinsel_o_mux));
end if;
invalid_opmode_flg := false;
else
invalid_opmode_flg := true;
add_flg := true;
output_x_sig <= '0';
end if;
when "011001001" =>
if (PREG /= 1) then
accum_o <= (others => 'X');
add_flg := false;
if(invalid_opmode_flg) then
invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), slv_to_str(carryinsel_o_mux));
end if;
invalid_opmode_flg := false;
else
invalid_opmode_flg := true;
add_flg := true;
output_x_sig <= '0';
end if;
when "011001100" =>
invalid_opmode_flg := true ;
add_flg := true ;
output_x_sig <= '0';
when "011001110" =>
invalid_opmode_flg := true ;
add_flg := true ;
output_x_sig <= '0';
when "011010100" =>
invalid_opmode_flg := true ;
add_flg := true ;
output_x_sig <= '0';
when "011010110" =>
if (MREG /= 0) then
accum_o <= (others => 'X');
add_flg := false;
if(invalid_opmode_flg) then
invalid_opmode_no_mreg_msg(slv_to_str(opmode_o_mux), slv_to_str(carryinsel_o_mux));
end if;
invalid_opmode_flg := false;
else
invalid_opmode_flg := true;
add_flg := true;
output_x_sig <= '0';
end if;
when "011010111" =>
if (MREG /= 1) then
accum_o <= (others => 'X');
add_flg := false;
if(invalid_opmode_flg) then
invalid_opmode_mreg_msg(slv_to_str(opmode_o_mux), slv_to_str(carryinsel_o_mux));
end if;
invalid_opmode_flg := false;
else
invalid_opmode_flg := true;
add_flg := true;
output_x_sig <= '0';
end if;
when "011110000" =>
invalid_opmode_flg := true ;
add_flg := true ;
output_x_sig <= '0';
when "011111000" =>
if (PREG /= 1) then
accum_o <= (others => 'X');
add_flg := false;
if(invalid_opmode_flg) then
invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), slv_to_str(carryinsel_o_mux));
end if;
invalid_opmode_flg := false;
else
invalid_opmode_flg := true;
add_flg := true;
output_x_sig <= '0';
end if;
when "011111100" =>
invalid_opmode_flg := true ;
add_flg := true ;
output_x_sig <= '0';
when "011111101" =>
invalid_opmode_flg := true ;
add_flg := true ;
output_x_sig <= '0';
when "101000000" =>
invalid_opmode_flg := true ;
add_flg := true ;
output_x_sig <= '0';
when "101001000" =>
if (PREG /= 1) then
accum_o <= (others => 'X');
add_flg := false;
if(invalid_opmode_flg) then
invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), slv_to_str(carryinsel_o_mux));
end if;
invalid_opmode_flg := false;
else
invalid_opmode_flg := true;
add_flg := true;
output_x_sig <= '0';
end if;
when "101001100" =>
invalid_opmode_flg := true ;
add_flg := true ;
output_x_sig <= '0';
when "101001101" =>
invalid_opmode_flg := true ;
add_flg := true ;
output_x_sig <= '0';
when "101001110" =>
invalid_opmode_flg := true ;
add_flg := true ;
output_x_sig <= '0';
when "101010100" =>
invalid_opmode_flg := true ;
add_flg := true ;
output_x_sig <= '0';
when "101010101" =>
invalid_opmode_flg := true ;
add_flg := true ;
output_x_sig <= '0';
when "101010110" =>
invalid_opmode_flg := true ;
add_flg := true ;
output_x_sig <= '0';
when "101010111" =>
invalid_opmode_flg := true ;
add_flg := true ;
output_x_sig <= '0';
when "101110000" =>
invalid_opmode_flg := true ;
add_flg := true ;
output_x_sig <= '0';
when "101110001" =>
invalid_opmode_flg := true ;
add_flg := true ;
output_x_sig <= '0';
when "101111000" =>
if (PREG /= 1) then
accum_o <= (others => 'X');
add_flg := false;
if(invalid_opmode_flg) then
invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), slv_to_str(carryinsel_o_mux));
end if;
invalid_opmode_flg := false;
else
invalid_opmode_flg := true;
add_flg := true;
output_x_sig <= '0';
end if;
when "101111001" =>
if (PREG /= 1) then
accum_o <= (others => 'X');
add_flg := false;
if(invalid_opmode_flg) then
invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), slv_to_str(carryinsel_o_mux));
end if;
invalid_opmode_flg := false;
else
invalid_opmode_flg := true;
add_flg := true;
output_x_sig <= '0';
end if;
when "101111100" =>
invalid_opmode_flg := true ;
add_flg := true ;
output_x_sig <= '0';
when "101111101" =>
invalid_opmode_flg := true ;
add_flg := true ;
output_x_sig <= '0';
when "101111110" =>
invalid_opmode_flg := true ;
add_flg := true ;
output_x_sig <= '0';
when "110000000" =>
if (PREG /= 1) then
accum_o <= (others => 'X');
add_flg := false;
if(invalid_opmode_flg) then
invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), slv_to_str(carryinsel_o_mux));
end if;
invalid_opmode_flg := false;
else
invalid_opmode_flg := true;
add_flg := true;
output_x_sig <= '0';
end if;
when "110001000" =>
if (PREG /= 1) then
accum_o <= (others => 'X');
add_flg := false;
if(invalid_opmode_flg) then
invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), slv_to_str(carryinsel_o_mux));
end if;
invalid_opmode_flg := false;
else
invalid_opmode_flg := true;
add_flg := true;
output_x_sig <= '0';
end if;
when "110001100" =>
if (PREG /= 1) then
accum_o <= (others => 'X');
add_flg := false;
if(invalid_opmode_flg) then
invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), slv_to_str(carryinsel_o_mux));
end if;
invalid_opmode_flg := false;
else
invalid_opmode_flg := true;
add_flg := true;
output_x_sig <= '0';
end if;
when "110001101" =>
if (PREG /= 1) then
accum_o <= (others => 'X');
add_flg := false;
if(invalid_opmode_flg) then
invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), slv_to_str(carryinsel_o_mux));
end if;
invalid_opmode_flg := false;
else
invalid_opmode_flg := true;
add_flg := true;
output_x_sig <= '0';
end if;
when "110010100" =>
if (PREG /= 1) then
accum_o <= (others => 'X');
add_flg := false;
if(invalid_opmode_flg) then
invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), slv_to_str(carryinsel_o_mux));
end if;
invalid_opmode_flg := false;
else
invalid_opmode_flg := true;
add_flg := true;
output_x_sig <= '0';
end if;
when "110010101" =>
if (PREG /= 1) then
accum_o <= (others => 'X');
add_flg := false;
if(invalid_opmode_flg) then
invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), slv_to_str(carryinsel_o_mux));
end if;
invalid_opmode_flg := false;
else
invalid_opmode_flg := true;
add_flg := true;
output_x_sig <= '0';
end if;
when "110110000" =>
if (PREG /= 1) then
accum_o <= (others => 'X');
add_flg := false;
if(invalid_opmode_flg) then
invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), slv_to_str(carryinsel_o_mux));
end if;
invalid_opmode_flg := false;
else
invalid_opmode_flg := true;
add_flg := true;
output_x_sig <= '0';
end if;
when "110110001" =>
if (PREG /= 1) then
accum_o <= (others => 'X');
add_flg := false;
if(invalid_opmode_flg) then
invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), slv_to_str(carryinsel_o_mux));
end if;
invalid_opmode_flg := false;
else
invalid_opmode_flg := true;
add_flg := true;
output_x_sig <= '0';
end if;
when "110111000" =>
if (PREG /= 1) then
accum_o <= (others => 'X');
add_flg := false;
if(invalid_opmode_flg) then
invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), slv_to_str(carryinsel_o_mux));
end if;
invalid_opmode_flg := false;
else
invalid_opmode_flg := true;
add_flg := true;
output_x_sig <= '0';
end if;
when "110111001" =>
if (PREG /= 1) then
accum_o <= (others => 'X');
add_flg := false;
if(invalid_opmode_flg) then
invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), slv_to_str(carryinsel_o_mux));
end if;
invalid_opmode_flg := false;
else
invalid_opmode_flg := true;
add_flg := true;
output_x_sig <= '0';
end if;
when "110111100" =>
if (PREG /= 1) then
accum_o <= (others => 'X');
add_flg := false;
if(invalid_opmode_flg) then
invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), slv_to_str(carryinsel_o_mux));
end if;
invalid_opmode_flg := false;
else
invalid_opmode_flg := true;
add_flg := true;
output_x_sig <= '0';
end if;
when "110111101" =>
if (PREG /= 1) then
accum_o <= (others => 'X');
add_flg := false;
if(invalid_opmode_flg) then
invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), slv_to_str(carryinsel_o_mux));
end if;
invalid_opmode_flg := false;
else
invalid_opmode_flg := true;
add_flg := true;
output_x_sig <= '0';
end if;
when "110111110" =>
if (PREG /= 1) then
accum_o <= (others => 'X');
add_flg := false;
if(invalid_opmode_flg) then
invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), slv_to_str(carryinsel_o_mux));
end if;
invalid_opmode_flg := false;
else
invalid_opmode_flg := true;
add_flg := true;
output_x_sig <= '0';
end if;
when others =>
if(invalid_opmode_flg = true) then
invalid_opmode_flg := false;
add_flg := false;
output_x_sig <= '1';
accum_o <= (others => 'X');
Write ( Message, string'("OPMODE Input Warning : The OPMODE "));
Write ( Message, slv_to_str(opmode_o_mux));
Write ( Message, string'(" with CARRYINSEL "));
Write ( Message, slv_to_str(carryinsel_o_mux));
Write ( Message, string'(" to DSP48 instance"));
Write ( Message, string'(" is invalid."));
assert false report Message.all severity Warning;
DEALLOCATE (Message);
end if;
end case;
if(add_flg) then
if(subtract_o_mux = '0') then
accum_o <= muxz_o_mux + (muxx_o_mux + muxy_o_mux + carryin_o_mux);
elsif(subtract_o_mux = '1') then
accum_o <= muxz_o_mux - (muxx_o_mux + muxy_o_mux + carryin_o_mux);
end if;
end if;
-- end if;
end process prcs_opmode_drc;
--####################################################################
--##### OUTPUT #####
--####################################################################
prcs_output:process(BCOUT_zd, PCOUT_zd, P_zd)
begin
BCOUT <= BCOUT_zd after SYNC_PATH_DELAY;
P <= P_zd after SYNC_PATH_DELAY;
PCOUT <= PCOUT_zd after SYNC_PATH_DELAY;
end process prcs_output;
end DSP48_V;
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library grlib;
use grlib.stdlib.all;
library STD;
use STD.TEXTIO.all;
library unisim;
use unisim.vcomponents.all;
use unisim.vpkg.all;
entity ARAMB36_INTERNAL is
generic (
BRAM_MODE : string := "TRUE_DUAL_PORT";
BRAM_SIZE : integer := 36;
DOA_REG : integer := 0;
DOB_REG : integer := 0;
EN_ECC_READ : boolean := FALSE;
EN_ECC_SCRUB : boolean := FALSE;
EN_ECC_WRITE : boolean := FALSE;
INITP_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_08 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_09 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_0A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_0B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_0C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_0D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_0E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_0F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_08 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_09 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_10 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_11 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_12 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_13 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_14 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_15 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_16 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_17 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_18 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_19 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_20 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_21 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_22 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_23 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_24 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_25 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_26 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_27 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_28 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_29 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_30 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_31 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_32 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_33 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_34 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_35 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_36 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_37 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_38 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_39 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_40 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_41 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_42 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_43 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_44 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_45 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_46 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_47 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_48 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_49 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_4A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_4B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_4C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_4D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_4E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_4F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_50 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_51 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_52 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_53 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_54 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_55 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_56 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_57 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_58 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_59 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_5A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_5B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_5C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_5D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_5E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_5F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_60 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_61 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_62 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_63 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_64 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_65 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_66 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_67 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_68 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_69 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_6A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_6B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_6C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_6D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_6E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_6F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_70 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_71 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_72 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_73 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_74 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_75 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_76 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_77 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_78 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_79 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_7A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_7B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_7C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_7D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_7E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_7F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_A : bit_vector := X"000000000000000000";
INIT_B : bit_vector := X"000000000000000000";
RAM_EXTENSION_A : string := "NONE";
RAM_EXTENSION_B : string := "NONE";
READ_WIDTH_A : integer := 0;
READ_WIDTH_B : integer := 0;
SETUP_ALL : time := 1000 ps;
SETUP_READ_FIRST : time := 3000 ps;
SIM_COLLISION_CHECK : string := "ALL";
SRVAL_A : bit_vector := X"000000000000000000";
SRVAL_B : bit_vector := X"000000000000000000";
WRITE_MODE_A : string := "WRITE_FIRST";
WRITE_MODE_B : string := "WRITE_FIRST";
WRITE_WIDTH_A : integer := 0;
WRITE_WIDTH_B : integer := 0
);
port (
CASCADEOUTLATA : out std_ulogic;
CASCADEOUTLATB : out std_ulogic;
CASCADEOUTREGA : out std_ulogic;
CASCADEOUTREGB : out std_ulogic;
DBITERR : out std_ulogic;
DOA : out std_logic_vector(63 downto 0);
DOB : out std_logic_vector(63 downto 0);
DOPA : out std_logic_vector(7 downto 0);
DOPB : out std_logic_vector(7 downto 0);
ECCPARITY : out std_logic_vector(7 downto 0);
SBITERR : out std_ulogic;
ADDRA : in std_logic_vector(15 downto 0);
ADDRB : in std_logic_vector(15 downto 0);
CASCADEINLATA : in std_ulogic;
CASCADEINLATB : in std_ulogic;
CASCADEINREGA : in std_ulogic;
CASCADEINREGB : in std_ulogic;
CLKA : in std_ulogic;
CLKB : in std_ulogic;
DIA : in std_logic_vector(63 downto 0);
DIB : in std_logic_vector(63 downto 0);
DIPA : in std_logic_vector(7 downto 0);
DIPB : in std_logic_vector(7 downto 0);
ENA : in std_ulogic;
ENB : in std_ulogic;
REGCEA : in std_ulogic;
REGCEB : in std_ulogic;
REGCLKA : in std_ulogic;
REGCLKB : in std_ulogic;
SSRA : in std_ulogic;
SSRB : in std_ulogic;
WEA : in std_logic_vector(7 downto 0);
WEB : in std_logic_vector(7 downto 0)
);
end ARAMB36_INTERNAL;
-- Architecture body --
architecture ARAMB36_INTERNAL_V of ARAMB36_INTERNAL is
signal ADDRA_dly : std_logic_vector(15 downto 0) := (others => 'X');
signal CLKA_dly : std_ulogic := 'X';
signal DIA_dly : std_logic_vector(63 downto 0) := (others => 'X');
signal DIPA_dly : std_logic_vector(7 downto 0) := (others => 'X');
signal ENA_dly : std_ulogic := 'X';
signal REGCEA_dly : std_ulogic := 'X';
signal SSRA_dly : std_ulogic := 'X';
signal WEA_dly : std_logic_vector(7 downto 0) := (others => 'X');
signal CASCADEINLATA_dly : std_ulogic := 'X';
signal CASCADEINREGA_dly : std_ulogic := 'X';
signal ADDRB_dly : std_logic_vector(15 downto 0) := (others => 'X');
signal CLKB_dly : std_ulogic := 'X';
signal DIB_dly : std_logic_vector(63 downto 0) := (others => 'X');
signal DIPB_dly : std_logic_vector(7 downto 0) := (others => 'X');
signal ENB_dly : std_ulogic := 'X';
signal REGCEB_dly : std_ulogic := 'X';
signal REGCLKA_dly : std_ulogic := 'X';
signal REGCLKB_dly : std_ulogic := 'X';
signal SSRB_dly : std_ulogic := 'X';
signal WEB_dly : std_logic_vector(7 downto 0) := (others => 'X');
signal CASCADEINLATB_dly : std_ulogic := 'X';
signal CASCADEINREGB_dly : std_ulogic := 'X';
signal sbiterr_out : std_ulogic := '0';
signal dbiterr_out : std_ulogic := '0';
signal sbiterr_outreg : std_ulogic := '0';
signal dbiterr_outreg : std_ulogic := '0';
signal sbiterr_out_out : std_ulogic := '0';
signal dbiterr_out_out : std_ulogic := '0';
signal doa_out : std_logic_vector(63 downto 0) := (others => '0');
signal dopa_out : std_logic_vector(7 downto 0) := (others => '0');
signal doa_outreg : std_logic_vector(63 downto 0) := (others => '0');
signal dopa_outreg : std_logic_vector(7 downto 0) := (others => '0');
signal dob_outreg : std_logic_vector(63 downto 0) := (others => '0');
signal dopb_outreg : std_logic_vector(7 downto 0) := (others => '0');
signal dob_out : std_logic_vector(63 downto 0) := (others => '0');
signal dopb_out : std_logic_vector(7 downto 0) := (others => '0');
signal doa_out_mux : std_logic_vector(63 downto 0) := (others => '0');
signal dopa_out_mux : std_logic_vector(7 downto 0) := (others => '0');
signal doa_outreg_mux : std_logic_vector(63 downto 0) := (others => '0');
signal dopa_outreg_mux : std_logic_vector(7 downto 0) := (others => '0');
signal dob_outreg_mux : std_logic_vector(63 downto 0) := (others => '0');
signal dopb_outreg_mux : std_logic_vector(7 downto 0) := (others => '0');
signal dob_out_mux : std_logic_vector(63 downto 0) := (others => '0');
signal dopb_out_mux : std_logic_vector(7 downto 0) := (others => '0');
signal doa_out_out : std_logic_vector(63 downto 0) := (others => '0');
signal dopa_out_out : std_logic_vector(7 downto 0) := (others => '0');
signal dob_out_out : std_logic_vector(63 downto 0) := (others => '0');
signal dopb_out_out : std_logic_vector(7 downto 0) := (others => '0');
signal addra_dly_15_reg : std_logic := '0';
signal addrb_dly_15_reg : std_logic := '0';
signal addra_dly_15_reg1 : std_logic := '0';
signal addrb_dly_15_reg1 : std_logic := '0';
signal cascade_a : std_logic_vector(1 downto 0) := (others => '0');
signal cascade_b : std_logic_vector(1 downto 0) := (others => '0');
signal GSR_dly : std_ulogic := 'X';
signal eccparity_out : std_logic_vector(7 downto 0) := (others => 'X');
signal SRVAL_A_STD : std_logic_vector(SRVAL_A'length-1 downto 0) := To_StdLogicVector(SRVAL_A);
signal SRVAL_B_STD : std_logic_vector(SRVAL_B'length-1 downto 0) := To_StdLogicVector(SRVAL_B);
signal INIT_A_STD : std_logic_vector(INIT_A'length-1 downto 0) := To_StdLogicVector(INIT_A);
signal INIT_B_STD : std_logic_vector(INIT_B'length-1 downto 0) := To_StdLogicVector(INIT_B);
signal di_x : std_logic_vector(63 downto 0) := (others => 'X');
function GetWidestWidth (
wr_width_a : in integer;
rd_width_a : in integer;
wr_width_b : in integer;
rd_width_b : in integer
) return integer is
variable func_widest_width : integer;
begin
if ((wr_width_a >= wr_width_b) and (wr_width_a >= rd_width_a) and (wr_width_a >= rd_width_b)) then
func_widest_width := wr_width_a;
elsif ((wr_width_b >= wr_width_a) and (wr_width_b >= rd_width_a) and (wr_width_b >= rd_width_b)) then
func_widest_width := wr_width_b;
elsif ((rd_width_a >= wr_width_a) and (rd_width_a >= wr_width_b) and (rd_width_a >= rd_width_b)) then
func_widest_width := rd_width_a;
elsif ((rd_width_b >= wr_width_a) and (rd_width_b >= wr_width_b) and (rd_width_b >= rd_width_a)) then
func_widest_width := rd_width_b;
end if;
return func_widest_width;
end;
function GetWidth (
rdwr_width : in integer
) return integer is
variable func_width : integer;
begin
case rdwr_width is
when 1 => func_width := 1;
when 2 => func_width := 2;
when 4 => func_width := 4;
when 9 => func_width := 8;
when 18 => func_width := 16;
when 36 => func_width := 32;
when 72 => func_width := 64;
when others => func_width := 1;
end case;
return func_width;
end;
function GetWidthp (
rdwr_widthp : in integer
) return integer is
variable func_widthp : integer;
begin
case rdwr_widthp is
when 9 => func_widthp := 1;
when 18 => func_widthp := 2;
when 36 => func_widthp := 4;
when 72 => func_widthp := 8;
when others => func_widthp := 1;
end case;
return func_widthp;
end;
function GetMemoryDepth (
rdwr_width : in integer;
func_bram_size : in integer
) return integer is
variable func_mem_depth : integer;
begin
case rdwr_width is
when 1 => if (func_bram_size = 18) then
func_mem_depth := 16384;
else
func_mem_depth := 32768;
end if;
when 2 => if (func_bram_size = 18) then
func_mem_depth := 8192;
else
func_mem_depth := 16384;
end if;
when 4 => if (func_bram_size = 18) then
func_mem_depth := 4096;
else
func_mem_depth := 8192;
end if;
when 9 => if (func_bram_size = 18) then
func_mem_depth := 2048;
else
func_mem_depth := 4096;
end if;
when 18 => if (func_bram_size = 18) then
func_mem_depth := 1024;
else
func_mem_depth := 2048;
end if;
when 36 => if (func_bram_size = 18) then
func_mem_depth := 512;
else
func_mem_depth := 1024;
end if;
when 72 => if (func_bram_size = 18) then
func_mem_depth := 0;
else
func_mem_depth := 512;
end if;
when others => func_mem_depth := 32768;
end case;
return func_mem_depth;
end;
function GetMemoryDepthP (
rdwr_width : in integer;
func_bram_size : in integer
) return integer is
variable func_memp_depth : integer;
begin
case rdwr_width is
when 9 => if (func_bram_size = 18) then
func_memp_depth := 2048;
else
func_memp_depth := 4096;
end if;
when 18 => if (func_bram_size = 18) then
func_memp_depth := 1024;
else
func_memp_depth := 2048;
end if;
when 36 => if (func_bram_size = 18) then
func_memp_depth := 512;
else
func_memp_depth := 1024;
end if;
when 72 => if (func_bram_size = 18) then
func_memp_depth := 0;
else
func_memp_depth := 512;
end if;
when others => func_memp_depth := 4096;
end case;
return func_memp_depth;
end;
function GetAddrBitLSB (
rdwr_width : in integer
) return integer is
variable func_lsb : integer;
begin
case rdwr_width is
when 1 => func_lsb := 0;
when 2 => func_lsb := 1;
when 4 => func_lsb := 2;
when 9 => func_lsb := 3;
when 18 => func_lsb := 4;
when 36 => func_lsb := 5;
when 72 => func_lsb := 6;
when others => func_lsb := 10;
end case;
return func_lsb;
end;
function GetAddrBit124 (
rdwr_width : in integer;
w_width : in integer
) return integer is
variable func_widest_width : integer;
begin
case rdwr_width is
when 1 => case w_width is
when 2 => func_widest_width := 0;
when 4 => func_widest_width := 1;
when 9 => func_widest_width := 2;
when 18 => func_widest_width := 3;
when 36 => func_widest_width := 4;
when 72 => func_widest_width := 5;
when others => func_widest_width := 10;
end case;
when 2 => case w_width is
when 4 => func_widest_width := 1;
when 9 => func_widest_width := 2;
when 18 => func_widest_width := 3;
when 36 => func_widest_width := 4;
when 72 => func_widest_width := 5;
when others => func_widest_width := 10;
end case;
when 4 => case w_width is
when 9 => func_widest_width := 2;
when 18 => func_widest_width := 3;
when 36 => func_widest_width := 4;
when 72 => func_widest_width := 5;
when others => func_widest_width := 10;
end case;
when others => func_widest_width := 10;
end case;
return func_widest_width;
end;
function GetAddrBit8 (
rdwr_width : in integer;
w_width : in integer
) return integer is
variable func_widest_width : integer;
begin
case rdwr_width is
when 9 => case w_width is
when 18 => func_widest_width := 3;
when 36 => func_widest_width := 4;
when 72 => func_widest_width := 5;
when others => func_widest_width := 10;
end case;
when others => func_widest_width := 10;
end case;
return func_widest_width;
end;
function GetAddrBit16 (
rdwr_width : in integer;
w_width : in integer
) return integer is
variable func_widest_width : integer;
begin
case rdwr_width is
when 18 => case w_width is
when 36 => func_widest_width := 4;
when 72 => func_widest_width := 5;
when others => func_widest_width := 10;
end case;
when others => func_widest_width := 10;
end case;
return func_widest_width;
end;
function GetAddrBit32 (
rdwr_width : in integer;
w_width : in integer
) return integer is
variable func_widest_width : integer;
begin
case rdwr_width is
when 36 => case w_width is
when 72 => func_widest_width := 5;
when others => func_widest_width := 10;
end case;
when others => func_widest_width := 10;
end case;
return func_widest_width;
end;
---------------------------------------------------------------------------
-- Function SLV_X_TO_HEX returns a hex string version of the std_logic_vector
-- argument.
---------------------------------------------------------------------------
function SLV_X_TO_HEX (
SLV : in std_logic_vector;
string_length : in integer
) return string is
variable i : integer := 1;
variable j : integer := 1;
variable STR : string(string_length downto 1);
variable nibble : std_logic_vector(3 downto 0) := "0000";
variable full_nibble_count : integer := 0;
variable remaining_bits : integer := 0;
begin
full_nibble_count := SLV'length/4;
remaining_bits := SLV'length mod 4;
for i in 1 to full_nibble_count loop
nibble := SLV(((4*i) - 1) downto ((4*i) - 4));
if (((nibble(0) xor nibble(1) xor nibble (2) xor nibble(3)) /= '1') and
(nibble(0) xor nibble(1) xor nibble (2) xor nibble(3)) /= '0') then
STR(j) := 'x';
elsif (nibble = "0000") then
STR(j) := '0';
elsif (nibble = "0001") then
STR(j) := '1';
elsif (nibble = "0010") then
STR(j) := '2';
elsif (nibble = "0011") then
STR(j) := '3';
elsif (nibble = "0100") then
STR(j) := '4';
elsif (nibble = "0101") then
STR(j) := '5';
elsif (nibble = "0110") then
STR(j) := '6';
elsif (nibble = "0111") then
STR(j) := '7';
elsif (nibble = "1000") then
STR(j) := '8';
elsif (nibble = "1001") then
STR(j) := '9';
elsif (nibble = "1010") then
STR(j) := 'a';
elsif (nibble = "1011") then
STR(j) := 'b';
elsif (nibble = "1100") then
STR(j) := 'c';
elsif (nibble = "1101") then
STR(j) := 'd';
elsif (nibble = "1110") then
STR(j) := 'e';
elsif (nibble = "1111") then
STR(j) := 'f';
end if;
j := j + 1;
end loop;
if (remaining_bits /= 0) then
nibble := "0000";
nibble((remaining_bits -1) downto 0) := SLV((SLV'length -1) downto (SLV'length - remaining_bits));
if (((nibble(0) xor nibble(1) xor nibble (2) xor nibble(3)) /= '1') and
(nibble(0) xor nibble(1) xor nibble (2) xor nibble(3)) /= '0') then
STR(j) := 'x';
elsif (nibble = "0000") then
STR(j) := '0';
elsif (nibble = "0001") then
STR(j) := '1';
elsif (nibble = "0010") then
STR(j) := '2';
elsif (nibble = "0011") then
STR(j) := '3';
elsif (nibble = "0100") then
STR(j) := '4';
elsif (nibble = "0101") then
STR(j) := '5';
elsif (nibble = "0110") then
STR(j) := '6';
elsif (nibble = "0111") then
STR(j) := '7';
elsif (nibble = "1000") then
STR(j) := '8';
elsif (nibble = "1001") then
STR(j) := '9';
elsif (nibble = "1010") then
STR(j) := 'a';
elsif (nibble = "1011") then
STR(j) := 'b';
elsif (nibble = "1100") then
STR(j) := 'c';
elsif (nibble = "1101") then
STR(j) := 'd';
elsif (nibble = "1110") then
STR(j) := 'e';
elsif (nibble = "1111") then
STR(j) := 'f';
end if;
end if;
return STR;
end SLV_X_TO_HEX;
constant widest_width : integer := GetWidestWidth(WRITE_WIDTH_A, READ_WIDTH_A, WRITE_WIDTH_B, READ_WIDTH_B);
constant mem_depth : integer := GetMemoryDepth(widest_width, BRAM_SIZE);
constant memp_depth : integer := GetMemoryDepthP(widest_width, BRAM_SIZE);
constant width : integer := GetWidth(widest_width);
constant widthp : integer := GetWidthp(widest_width);
constant wa_width : integer := GetWidth(WRITE_WIDTH_A);
constant wb_width : integer := GetWidth(WRITE_WIDTH_B);
constant ra_width : integer := GetWidth(READ_WIDTH_A);
constant rb_width : integer := GetWidth(READ_WIDTH_B);
constant wa_widthp : integer := GetWidthp(WRITE_WIDTH_A);
constant wb_widthp : integer := GetWidthp(WRITE_WIDTH_B);
constant ra_widthp : integer := GetWidthp(READ_WIDTH_A);
constant rb_widthp : integer := GetWidthp(READ_WIDTH_B);
constant r_addra_lbit_124 : integer := GetAddrBitLSB(READ_WIDTH_A);
constant r_addrb_lbit_124 : integer := GetAddrBitLSB(READ_WIDTH_B);
constant w_addra_lbit_124 : integer := GetAddrBitLSB(WRITE_WIDTH_A);
constant w_addrb_lbit_124 : integer := GetAddrBitLSB(WRITE_WIDTH_B);
constant w_addra_bit_124 : integer := GetAddrBit124(WRITE_WIDTH_A, widest_width);
constant r_addra_bit_124 : integer := GetAddrBit124(READ_WIDTH_A, widest_width);
constant w_addrb_bit_124 : integer := GetAddrBit124(WRITE_WIDTH_B, widest_width);
constant r_addrb_bit_124 : integer := GetAddrBit124(READ_WIDTH_B, widest_width);
constant w_addra_bit_8 : integer := GetAddrBit8(WRITE_WIDTH_A, widest_width);
constant r_addra_bit_8 : integer := GetAddrBit8(READ_WIDTH_A, widest_width);
constant w_addrb_bit_8 : integer := GetAddrBit8(WRITE_WIDTH_B, widest_width);
constant r_addrb_bit_8 : integer := GetAddrBit8(READ_WIDTH_B, widest_width);
constant w_addra_bit_16 : integer := GetAddrBit16(WRITE_WIDTH_A, widest_width);
constant r_addra_bit_16 : integer := GetAddrBit16(READ_WIDTH_A, widest_width);
constant w_addrb_bit_16 : integer := GetAddrBit16(WRITE_WIDTH_B, widest_width);
constant r_addrb_bit_16 : integer := GetAddrBit16(READ_WIDTH_B, widest_width);
constant w_addra_bit_32 : integer := GetAddrBit32(WRITE_WIDTH_A, widest_width);
constant r_addra_bit_32 : integer := GetAddrBit32(READ_WIDTH_A, widest_width);
constant w_addrb_bit_32 : integer := GetAddrBit32(WRITE_WIDTH_B, widest_width);
constant r_addrb_bit_32 : integer := GetAddrBit32(READ_WIDTH_B, widest_width);
constant col_addr_lsb : integer := GetAddrBitLSB(widest_width);
type Two_D_array_type is array ((mem_depth - 1) downto 0) of std_logic_vector((width - 1) downto 0);
type Two_D_parity_array_type is array ((memp_depth - 1) downto 0) of std_logic_vector((widthp -1) downto 0);
function slv_to_two_D_array(
slv_length : integer;
slv_width : integer;
SLV : in std_logic_vector
)
return two_D_array_type is
variable two_D_array : two_D_array_type;
variable intermediate : std_logic_vector((slv_width - 1) downto 0);
begin
for i in 0 to (slv_length - 1) loop
intermediate := SLV(((i*slv_width) + (slv_width - 1)) downto (i* slv_width));
two_D_array(i) := intermediate;
end loop;
return two_D_array;
end;
function slv_to_two_D_parity_array(
slv_length : integer;
slv_width : integer;
SLV : in std_logic_vector
)
return two_D_parity_array_type is
variable two_D_parity_array : two_D_parity_array_type;
variable intermediate : std_logic_vector((slv_width - 1) downto 0);
begin
for i in 0 to (slv_length - 1)loop
intermediate := SLV(((i*slv_width) + (slv_width - 1)) downto (i* slv_width));
two_D_parity_array(i) := intermediate;
end loop;
return two_D_parity_array;
end;
function fn_dip_ecc (
encode : in std_logic;
di_in : in std_logic_vector (63 downto 0);
dip_in : in std_logic_vector (7 downto 0)
) return std_logic_vector is
variable fn_dip_ecc : std_logic_vector (7 downto 0);
begin
fn_dip_ecc(0) := di_in(0) xor di_in(1) xor di_in(3) xor di_in(4) xor di_in(6) xor di_in(8)
xor di_in(10) xor di_in(11) xor di_in(13) xor di_in(15) xor di_in(17) xor di_in(19)
xor di_in(21) xor di_in(23) xor di_in(25) xor di_in(26) xor di_in(28)
xor di_in(30) xor di_in(32) xor di_in(34) xor di_in(36) xor di_in(38)
xor di_in(40) xor di_in(42) xor di_in(44) xor di_in(46) xor di_in(48)
xor di_in(50) xor di_in(52) xor di_in(54) xor di_in(56) xor di_in(57) xor di_in(59)
xor di_in(61) xor di_in(63);
fn_dip_ecc(1) := di_in(0) xor di_in(2) xor di_in(3) xor di_in(5) xor di_in(6) xor di_in(9)
xor di_in(10) xor di_in(12) xor di_in(13) xor di_in(16) xor di_in(17)
xor di_in(20) xor di_in(21) xor di_in(24) xor di_in(25) xor di_in(27) xor di_in(28)
xor di_in(31) xor di_in(32) xor di_in(35) xor di_in(36) xor di_in(39)
xor di_in(40) xor di_in(43) xor di_in(44) xor di_in(47) xor di_in(48)
xor di_in(51) xor di_in(52) xor di_in(55) xor di_in(56) xor di_in(58) xor di_in(59)
xor di_in(62) xor di_in(63);
fn_dip_ecc(2) := di_in(1) xor di_in(2) xor di_in(3) xor di_in(7) xor di_in(8) xor di_in(9)
xor di_in(10) xor di_in(14) xor di_in(15) xor di_in(16) xor di_in(17)
xor di_in(22) xor di_in(23) xor di_in(24) xor di_in(25) xor di_in(29)
xor di_in(30) xor di_in(31) xor di_in(32) xor di_in(37) xor di_in(38) xor di_in(39)
xor di_in(40) xor di_in(45) xor di_in(46) xor di_in(47) xor di_in(48)
xor di_in(53) xor di_in(54) xor di_in(55) xor di_in(56)
xor di_in(60) xor di_in(61) xor di_in(62) xor di_in(63);
fn_dip_ecc(3) := di_in(4) xor di_in(5) xor di_in(6) xor di_in(7) xor di_in(8) xor di_in(9)
xor di_in(10) xor di_in(18) xor di_in(19)
xor di_in(20) xor di_in(21) xor di_in(22) xor di_in(23) xor di_in(24) xor di_in(25)
xor di_in(33) xor di_in(34) xor di_in(35) xor di_in(36) xor di_in(37) xor di_in(38) xor di_in(39)
xor di_in(40) xor di_in(49)
xor di_in(50) xor di_in(51) xor di_in(52) xor di_in(53) xor di_in(54) xor di_in(55) xor di_in(56);
fn_dip_ecc(4) := di_in(11) xor di_in(12) xor di_in(13) xor di_in(14) xor di_in(15) xor di_in(16) xor di_in(17)
xor di_in(18) xor di_in(19) xor di_in(20) xor di_in(21) xor di_in(22) xor di_in(23) xor di_in(24)
xor di_in(25) xor di_in(41) xor di_in(42) xor di_in(43) xor di_in(44) xor di_in(45) xor di_in(46)
xor di_in(47) xor di_in(48) xor di_in(49) xor di_in(50) xor di_in(51) xor di_in(52) xor di_in(53)
xor di_in(54) xor di_in(55) xor di_in(56);
fn_dip_ecc(5) := di_in(26) xor di_in(27) xor di_in(28) xor di_in(29)
xor di_in(30) xor di_in(31) xor di_in(32) xor di_in(33) xor di_in(34) xor di_in(35) xor di_in(36)
xor di_in(37) xor di_in(38) xor di_in(39) xor di_in(40) xor di_in(41) xor di_in(42) xor di_in(43)
xor di_in(44) xor di_in(45) xor di_in(46) xor di_in(47) xor di_in(48) xor di_in(49) xor di_in(50)
xor di_in(51) xor di_in(52) xor di_in(53) xor di_in(54) xor di_in(55) xor di_in(56);
fn_dip_ecc(6) := di_in(57) xor di_in(58) xor di_in(59)
xor di_in(60) xor di_in(61) xor di_in(62) xor di_in(63);
if (encode = '1') then
fn_dip_ecc(7) := fn_dip_ecc(0) xor fn_dip_ecc(1) xor fn_dip_ecc(2) xor fn_dip_ecc(3) xor fn_dip_ecc(4) xor fn_dip_ecc(5)
xor fn_dip_ecc(6) xor di_in(0) xor di_in(1) xor di_in(2) xor di_in(3) xor di_in(4) xor di_in(5)
xor di_in(6) xor di_in(7) xor di_in(8) xor di_in(9) xor di_in(10) xor di_in(11) xor di_in(12)
xor di_in(13) xor di_in(14) xor di_in(15) xor di_in(16) xor di_in(17) xor di_in(18) xor di_in(19)
xor di_in(20) xor di_in(21) xor di_in(22) xor di_in(23) xor di_in(24) xor di_in(25) xor di_in(26)
xor di_in(27) xor di_in(28) xor di_in(29) xor di_in(30) xor di_in(31) xor di_in(32) xor di_in(33)
xor di_in(34) xor di_in(35) xor di_in(36) xor di_in(37) xor di_in(38) xor di_in(39) xor di_in(40)
xor di_in(41) xor di_in(42) xor di_in(43) xor di_in(44) xor di_in(45) xor di_in(46) xor di_in(47)
xor di_in(48) xor di_in(49) xor di_in(50) xor di_in(51) xor di_in(52) xor di_in(53) xor di_in(54)
xor di_in(55) xor di_in(56) xor di_in(57) xor di_in(58) xor di_in(59) xor di_in(60) xor di_in(61)
xor di_in(62) xor di_in(63);
else
fn_dip_ecc(7) := dip_in(0) xor dip_in(1) xor dip_in(2) xor dip_in(3) xor dip_in(4) xor dip_in(5)
xor dip_in(6) xor di_in(0) xor di_in(1) xor di_in(2) xor di_in(3) xor di_in(4) xor di_in(5)
xor di_in(6) xor di_in(7) xor di_in(8) xor di_in(9) xor di_in(10) xor di_in(11) xor di_in(12)
xor di_in(13) xor di_in(14) xor di_in(15) xor di_in(16) xor di_in(17) xor di_in(18) xor di_in(19)
xor di_in(20) xor di_in(21) xor di_in(22) xor di_in(23) xor di_in(24) xor di_in(25) xor di_in(26)
xor di_in(27) xor di_in(28) xor di_in(29) xor di_in(30) xor di_in(31) xor di_in(32) xor di_in(33)
xor di_in(34) xor di_in(35) xor di_in(36) xor di_in(37) xor di_in(38) xor di_in(39) xor di_in(40)
xor di_in(41) xor di_in(42) xor di_in(43) xor di_in(44) xor di_in(45) xor di_in(46) xor di_in(47)
xor di_in(48) xor di_in(49) xor di_in(50) xor di_in(51) xor di_in(52) xor di_in(53) xor di_in(54)
xor di_in(55) xor di_in(56) xor di_in(57) xor di_in(58) xor di_in(59) xor di_in(60) xor di_in(61)
xor di_in(62) xor di_in(63);
end if;
return fn_dip_ecc;
end fn_dip_ecc;
procedure prcd_chk_for_col_msg (
constant wea_tmp : in std_ulogic;
constant web_tmp : in std_ulogic;
constant addra_tmp : in std_logic_vector (15 downto 0);
constant addrb_tmp : in std_logic_vector (15 downto 0);
variable col_wr_wr_msg : inout std_ulogic;
variable col_wra_rdb_msg : inout std_ulogic;
variable col_wrb_rda_msg : inout std_ulogic
) is
variable string_length_1 : integer;
variable string_length_2 : integer;
variable message : LINE;
constant MsgSeverity : severity_level := Error;
begin
if ((SIM_COLLISION_CHECK = "ALL" or SIM_COLLISION_CHECK = "WARNING_ONLY")
and (not(((WRITE_MODE_B = "READ_FIRST" and web_tmp = '1' and wea_tmp = '0') and (not(rising_edge(clka_dly) and (not(rising_edge(clkb_dly))))))
or ((WRITE_MODE_A = "READ_FIRST" and wea_tmp = '1' and web_tmp = '0') and (not(rising_edge(clkb_dly) and (not(rising_edge(clka_dly))))))))) then
if ((addra_tmp'length mod 4) = 0) then
string_length_1 := addra_tmp'length/4;
elsif ((addra_tmp'length mod 4) > 0) then
string_length_1 := addra_tmp'length/4 + 1;
end if;
if ((addrb_tmp'length mod 4) = 0) then
string_length_2 := addrb_tmp'length/4;
elsif ((addrb_tmp'length mod 4) > 0) then
string_length_2 := addrb_tmp'length/4 + 1;
end if;
if (wea_tmp = '1' and web_tmp = '1' and col_wr_wr_msg = '1') then
Write ( message, STRING'(" Memory Collision Error on ARAMB36_INTERNAL :"));
Write ( message, STRING'(ARAMB36_INTERNAL'path_name));
Write ( message, STRING'(" at simulation time "));
Write ( message, now);
Write ( message, STRING'("."));
Write ( message, LF );
Write ( message, STRING'(" A write was requested to the same address simultaneously at both Port A and Port B of the RAM."));
Write ( message, STRING'(" The contents written to the RAM at address location "));
Write ( message, SLV_X_TO_HEX(addra_tmp, string_length_1));
Write ( message, STRING'(" (hex) "));
Write ( message, STRING'("of Port A and address location "));
Write ( message, SLV_X_TO_HEX(addrb_tmp, string_length_2));
Write ( message, STRING'(" (hex) "));
Write ( message, STRING'("of Port B are unknown. "));
ASSERT FALSE REPORT message.ALL SEVERITY MsgSeverity;
DEALLOCATE (message);
col_wr_wr_msg := '0';
elsif (wea_tmp = '1' and web_tmp = '0' and col_wra_rdb_msg = '1') then
Write ( message, STRING'(" Memory Collision Error on ARAMB36_INTERNAL :"));
Write ( message, STRING'(ARAMB36_INTERNAL'path_name));
Write ( message, STRING'(" at simulation time "));
Write ( message, now);
Write ( message, STRING'("."));
Write ( message, LF );
Write ( message, STRING'(" A read was performed on address "));
Write ( message, SLV_X_TO_HEX(addrb_tmp, string_length_2));
Write ( message, STRING'(" (hex) "));
Write ( message, STRING'("of port B while a write was requested to the same address on Port A. "));
Write ( message, STRING'(" The write will be successful however the read value on port B is unknown until the next CLKB cycle. "));
ASSERT FALSE REPORT message.ALL SEVERITY MsgSeverity;
DEALLOCATE (message);
col_wra_rdb_msg := '0';
elsif (wea_tmp = '0' and web_tmp = '1' and col_wrb_rda_msg = '1') then
Write ( message, STRING'(" Memory Collision Error on ARAMB36_INTERNAL :"));
Write ( message, STRING'(ARAMB36_INTERNAL'path_name));
Write ( message, STRING'(" at simulation time "));
Write ( message, now);
Write ( message, STRING'("."));
Write ( message, LF );
Write ( message, STRING'(" A read was performed on address "));
Write ( message, SLV_X_TO_HEX(addra_tmp, string_length_1));
Write ( message, STRING'(" (hex) "));
Write ( message, STRING'("of port A while a write was requested to the same address on Port B. "));
Write ( message, STRING'(" The write will be successful however the read value on port A is unknown until the next CLKA cycle. "));
ASSERT FALSE REPORT message.ALL SEVERITY MsgSeverity;
DEALLOCATE (message);
col_wrb_rda_msg := '0';
end if;
end if;
end prcd_chk_for_col_msg;
procedure prcd_write_ram (
constant we : in std_logic;
constant di : in std_logic_vector;
constant dip : in std_logic;
variable mem_proc : inout std_logic_vector;
variable memp_proc : inout std_logic
) is
alias di_tmp : std_logic_vector (di'length-1 downto 0) is di;
alias mem_proc_tmp : std_logic_vector (mem_proc'length-1 downto 0) is mem_proc;
begin
if (we = '1') then
mem_proc_tmp := di_tmp;
if (width >= 8) then
memp_proc := dip;
end if;
end if;
end prcd_write_ram;
procedure prcd_write_ram_col (
constant we_o : in std_logic;
constant we : in std_logic;
constant di : in std_logic_vector;
constant dip : in std_logic;
variable mem_proc : inout std_logic_vector;
variable memp_proc : inout std_logic
) is
alias di_tmp : std_logic_vector (di'length-1 downto 0) is di;
alias mem_proc_tmp : std_logic_vector (mem_proc'length-1 downto 0) is mem_proc;
variable i : integer := 0;
begin
if (we = '1') then
for i in 0 to di'length-1 loop
if ((mem_proc_tmp(i) /= 'X') or (not(we = we_o and we = '1'))) then
mem_proc_tmp(i) := di_tmp(i);
end if;
end loop;
if (width >= 8 and ((memp_proc /= 'X') or (not(we = we_o and we = '1')))) then
memp_proc := dip;
end if;
end if;
end prcd_write_ram_col;
procedure prcd_x_buf (
constant wr_rd_mode : in std_logic_vector (1 downto 0);
constant do_uindex : in integer;
constant do_lindex : in integer;
constant dop_index : in integer;
constant do_ltmp : in std_logic_vector (63 downto 0);
variable do_tmp : inout std_logic_vector (63 downto 0);
constant dop_ltmp : in std_logic_vector (7 downto 0);
variable dop_tmp : inout std_logic_vector (7 downto 0)
) is
variable i : integer;
begin
if (wr_rd_mode = "01") then
for i in do_lindex to do_uindex loop
if (do_ltmp(i) = 'X') then
do_tmp(i) := 'X';
end if;
end loop;
if (dop_ltmp(dop_index) = 'X') then
dop_tmp(dop_index) := 'X';
end if;
else
do_tmp(do_lindex + 7 downto do_lindex) := do_ltmp(do_lindex + 7 downto do_lindex);
dop_tmp(dop_index) := dop_ltmp(dop_index);
end if;
end prcd_x_buf;
procedure prcd_rd_ram_a (
constant addra_tmp : in std_logic_vector (15 downto 0);
variable doa_tmp : inout std_logic_vector (63 downto 0);
variable dopa_tmp : inout std_logic_vector (7 downto 0);
constant mem : in Two_D_array_type;
constant memp : in Two_D_parity_array_type
) is
variable prcd_tmp_addra_dly_depth : integer;
variable prcd_tmp_addra_dly_width : integer;
begin
case ra_width is
when 1 | 2 | 4 => if (ra_width >= width) then
prcd_tmp_addra_dly_depth := SLV_TO_INT(addra_tmp(14 downto r_addra_lbit_124));
doa_tmp(ra_width-1 downto 0) := mem(prcd_tmp_addra_dly_depth);
else
prcd_tmp_addra_dly_depth := SLV_TO_INT(addra_tmp(14 downto r_addra_bit_124 + 1));
prcd_tmp_addra_dly_width := SLV_TO_INT(addra_tmp(r_addra_bit_124 downto r_addra_lbit_124));
doa_tmp(ra_width-1 downto 0) := mem(prcd_tmp_addra_dly_depth)((prcd_tmp_addra_dly_width * ra_width) + ra_width - 1 downto prcd_tmp_addra_dly_width * ra_width);
end if;
when 8 => if (ra_width >= width) then
prcd_tmp_addra_dly_depth := SLV_TO_INT(addra_tmp(14 downto 3));
doa_tmp(7 downto 0) := mem(prcd_tmp_addra_dly_depth);
dopa_tmp(0 downto 0) := memp(prcd_tmp_addra_dly_depth);
else
prcd_tmp_addra_dly_depth := SLV_TO_INT(addra_tmp(14 downto r_addra_bit_8 + 1));
prcd_tmp_addra_dly_width := SLV_TO_INT(addra_tmp(r_addra_bit_8 downto 3));
doa_tmp(7 downto 0) := mem(prcd_tmp_addra_dly_depth)((prcd_tmp_addra_dly_width * 8) + 7 downto prcd_tmp_addra_dly_width * 8);
dopa_tmp(0 downto 0) := memp(prcd_tmp_addra_dly_depth)(prcd_tmp_addra_dly_width downto prcd_tmp_addra_dly_width);
end if;
when 16 => if (ra_width >= width) then
prcd_tmp_addra_dly_depth := SLV_TO_INT(addra_tmp(14 downto 4));
doa_tmp(15 downto 0) := mem(prcd_tmp_addra_dly_depth);
dopa_tmp(1 downto 0) := memp(prcd_tmp_addra_dly_depth);
else
prcd_tmp_addra_dly_depth := SLV_TO_INT(addra_tmp(14 downto r_addra_bit_16 + 1));
prcd_tmp_addra_dly_width := SLV_TO_INT(addra_tmp(r_addra_bit_16 downto 4));
doa_tmp(15 downto 0) := mem(prcd_tmp_addra_dly_depth)((prcd_tmp_addra_dly_width * 16) + 15 downto prcd_tmp_addra_dly_width * 16);
dopa_tmp(1 downto 0) := memp(prcd_tmp_addra_dly_depth)((prcd_tmp_addra_dly_width * 2) + 1 downto prcd_tmp_addra_dly_width * 2);
end if;
when 32 => if (ra_width >= width) then
prcd_tmp_addra_dly_depth := SLV_TO_INT(addra_tmp(14 downto 5));
doa_tmp(31 downto 0) := mem(prcd_tmp_addra_dly_depth);
dopa_tmp(3 downto 0) := memp(prcd_tmp_addra_dly_depth);
end if;
when 64 => if (ra_width >= width) then
prcd_tmp_addra_dly_depth := SLV_TO_INT(addra_tmp(14 downto 6));
doa_tmp(63 downto 0) := mem(prcd_tmp_addra_dly_depth);
dopa_tmp(7 downto 0) := memp(prcd_tmp_addra_dly_depth);
end if;
when others => null;
end case;
end prcd_rd_ram_a;
procedure prcd_rd_ram_b (
constant addrb_tmp : in std_logic_vector (15 downto 0);
variable dob_tmp : inout std_logic_vector (63 downto 0);
variable dopb_tmp : inout std_logic_vector (7 downto 0);
constant mem : in Two_D_array_type;
constant memp : in Two_D_parity_array_type
) is
variable prcd_tmp_addrb_dly_depth : integer;
variable prcd_tmp_addrb_dly_width : integer;
begin
case rb_width is
when 1 | 2 | 4 => if (rb_width >= width) then
prcd_tmp_addrb_dly_depth := SLV_TO_INT(addrb_tmp(14 downto r_addrb_lbit_124));
dob_tmp(rb_width-1 downto 0) := mem(prcd_tmp_addrb_dly_depth);
else
prcd_tmp_addrb_dly_depth := SLV_TO_INT(addrb_tmp(14 downto r_addrb_bit_124 + 1));
prcd_tmp_addrb_dly_width := SLV_TO_INT(addrb_tmp(r_addrb_bit_124 downto r_addrb_lbit_124));
dob_tmp(rb_width-1 downto 0) := mem(prcd_tmp_addrb_dly_depth)((prcd_tmp_addrb_dly_width * rb_width) + rb_width - 1 downto prcd_tmp_addrb_dly_width * rb_width);
end if;
when 8 => if (rb_width >= width) then
prcd_tmp_addrb_dly_depth := SLV_TO_INT(addrb_tmp(14 downto 3));
dob_tmp(7 downto 0) := mem(prcd_tmp_addrb_dly_depth);
dopb_tmp(0 downto 0) := memp(prcd_tmp_addrb_dly_depth);
else
prcd_tmp_addrb_dly_depth := SLV_TO_INT(addrb_tmp(14 downto r_addrb_bit_8 + 1));
prcd_tmp_addrb_dly_width := SLV_TO_INT(addrb_tmp(r_addrb_bit_8 downto 3));
dob_tmp(7 downto 0) := mem(prcd_tmp_addrb_dly_depth)((prcd_tmp_addrb_dly_width * 8) + 7 downto prcd_tmp_addrb_dly_width * 8);
dopb_tmp(0 downto 0) := memp(prcd_tmp_addrb_dly_depth)(prcd_tmp_addrb_dly_width downto prcd_tmp_addrb_dly_width);
end if;
when 16 => if (rb_width >= width) then
prcd_tmp_addrb_dly_depth := SLV_TO_INT(addrb_tmp(14 downto 4));
dob_tmp(15 downto 0) := mem(prcd_tmp_addrb_dly_depth);
dopb_tmp(1 downto 0) := memp(prcd_tmp_addrb_dly_depth);
else
prcd_tmp_addrb_dly_depth := SLV_TO_INT(addrb_tmp(14 downto r_addrb_bit_16 + 1));
prcd_tmp_addrb_dly_width := SLV_TO_INT(addrb_tmp(r_addrb_bit_16 downto 4));
dob_tmp(15 downto 0) := mem(prcd_tmp_addrb_dly_depth)((prcd_tmp_addrb_dly_width * 16) + 15 downto prcd_tmp_addrb_dly_width * 16);
dopb_tmp(1 downto 0) := memp(prcd_tmp_addrb_dly_depth)((prcd_tmp_addrb_dly_width * 2) + 1 downto prcd_tmp_addrb_dly_width * 2);
end if;
when 32 => if (rb_width >= width) then
prcd_tmp_addrb_dly_depth := SLV_TO_INT(addrb_tmp(14 downto 5));
dob_tmp(31 downto 0) := mem(prcd_tmp_addrb_dly_depth);
dopb_tmp(3 downto 0) := memp(prcd_tmp_addrb_dly_depth);
end if;
when others => null;
end case;
end prcd_rd_ram_b;
procedure prcd_col_wr_ram_a (
constant seq : in std_logic_vector (1 downto 0);
constant web_tmp : in std_logic_vector (7 downto 0);
constant wea_tmp : in std_logic_vector (7 downto 0);
constant dia_tmp : in std_logic_vector (63 downto 0);
constant dipa_tmp : in std_logic_vector (7 downto 0);
constant addrb_tmp : in std_logic_vector (15 downto 0);
constant addra_tmp : in std_logic_vector (15 downto 0);
variable mem : inout Two_D_array_type;
variable memp : inout Two_D_parity_array_type;
variable col_wr_wr_msg : inout std_ulogic;
variable col_wra_rdb_msg : inout std_ulogic;
variable col_wrb_rda_msg : inout std_ulogic
) is
variable prcd_tmp_addra_dly_depth : integer;
variable prcd_tmp_addra_dly_width : integer;
variable junk : std_ulogic;
begin
case wa_width is
when 1 | 2 | 4 => if (not(wea_tmp(0) = '1' and web_tmp(0) = '1' and wa_width > wb_width) or seq = "10") then
if (wa_width >= width) then
prcd_tmp_addra_dly_depth := SLV_TO_INT(addra_tmp(14 downto w_addra_lbit_124));
prcd_write_ram_col (web_tmp(0), wea_tmp(0), dia_tmp(wa_width-1 downto 0), '0', mem(prcd_tmp_addra_dly_depth), junk);
else
prcd_tmp_addra_dly_depth := SLV_TO_INT(addra_tmp(14 downto w_addra_bit_124 + 1));
prcd_tmp_addra_dly_width := SLV_TO_INT(addra_tmp(w_addra_bit_124 downto w_addra_lbit_124));
prcd_write_ram_col (web_tmp(0), wea_tmp(0), dia_tmp(wa_width-1 downto 0), '0', mem(prcd_tmp_addra_dly_depth)((prcd_tmp_addra_dly_width * wa_width) + wa_width - 1 downto (prcd_tmp_addra_dly_width * wa_width)), junk);
end if;
if (seq = "00") then
prcd_chk_for_col_msg (wea_tmp(0), web_tmp(0), addra_tmp, addrb_tmp, col_wr_wr_msg, col_wra_rdb_msg, col_wrb_rda_msg);
end if;
end if;
when 8 => if (not(wea_tmp(0) = '1' and web_tmp(0) = '1' and wa_width > wb_width) or seq = "10") then
if (wa_width >= width) then
prcd_tmp_addra_dly_depth := SLV_TO_INT(addra_tmp(14 downto 3));
prcd_write_ram_col (web_tmp(0), wea_tmp(0), dia_tmp(7 downto 0), dipa_tmp(0), mem(prcd_tmp_addra_dly_depth), memp(prcd_tmp_addra_dly_depth)(0));
else
prcd_tmp_addra_dly_depth := SLV_TO_INT(addra_tmp(14 downto w_addra_bit_8 + 1));
prcd_tmp_addra_dly_width := SLV_TO_INT(addra_tmp(w_addra_bit_8 downto 3));
prcd_write_ram_col (web_tmp(0), wea_tmp(0), dia_tmp(7 downto 0), dipa_tmp(0), mem(prcd_tmp_addra_dly_depth)((prcd_tmp_addra_dly_width * 8) + 7 downto (prcd_tmp_addra_dly_width * 8)), memp(prcd_tmp_addra_dly_depth)((prcd_tmp_addra_dly_width)));
end if;
if (seq = "00") then
prcd_chk_for_col_msg (wea_tmp(0), web_tmp(0), addra_tmp, addrb_tmp, col_wr_wr_msg, col_wra_rdb_msg, col_wrb_rda_msg);
end if;
end if;
when 16 => if (not(wea_tmp(0) = '1' and web_tmp(0) = '1' and wa_width > wb_width) or seq = "10") then
if (wa_width >= width) then
prcd_tmp_addra_dly_depth := SLV_TO_INT(addra_tmp(14 downto 4));
prcd_write_ram_col (web_tmp(0), wea_tmp(0), dia_tmp(7 downto 0), dipa_tmp(0), mem(prcd_tmp_addra_dly_depth)(7 downto 0), memp(prcd_tmp_addra_dly_depth)(0));
else
prcd_tmp_addra_dly_depth := SLV_TO_INT(addra_tmp(14 downto w_addra_bit_16 + 1));
prcd_tmp_addra_dly_width := SLV_TO_INT(addra_tmp(w_addra_bit_16 downto 4));
prcd_write_ram_col (web_tmp(0), wea_tmp(0), dia_tmp(7 downto 0), dipa_tmp(0), mem(prcd_tmp_addra_dly_depth)((prcd_tmp_addra_dly_width * 16) + 7 downto (prcd_tmp_addra_dly_width * 16)), memp(prcd_tmp_addra_dly_depth)((prcd_tmp_addra_dly_width * 2)));
end if;
if (seq = "00") then
prcd_chk_for_col_msg (wea_tmp(0), web_tmp(0), addra_tmp, addrb_tmp, col_wr_wr_msg, col_wra_rdb_msg, col_wrb_rda_msg);
end if;
if (wa_width >= width) then
prcd_tmp_addra_dly_depth := SLV_TO_INT(addra_tmp(14 downto 4));
prcd_write_ram_col (web_tmp(1), wea_tmp(1), dia_tmp(15 downto 8), dipa_tmp(1), mem(prcd_tmp_addra_dly_depth)(15 downto 8), memp(prcd_tmp_addra_dly_depth)(1));
else
prcd_tmp_addra_dly_depth := SLV_TO_INT(addra_tmp(14 downto w_addra_bit_16 + 1));
prcd_tmp_addra_dly_width := SLV_TO_INT(addra_tmp(w_addra_bit_16 downto 4));
prcd_write_ram_col (web_tmp(1), wea_tmp(1), dia_tmp(15 downto 8), dipa_tmp(1), mem(prcd_tmp_addra_dly_depth)((prcd_tmp_addra_dly_width * 16) + 15 downto (prcd_tmp_addra_dly_width * 16) + 8), memp(prcd_tmp_addra_dly_depth)((prcd_tmp_addra_dly_width * 2) + 1));
end if;
if (seq = "00") then
prcd_chk_for_col_msg (wea_tmp(1), web_tmp(1), addra_tmp, addrb_tmp, col_wr_wr_msg, col_wra_rdb_msg, col_wrb_rda_msg);
end if;
end if;
when 32 => if (not(wea_tmp(0) = '1' and web_tmp(0) = '1' and wa_width > wb_width) or seq = "10") then
prcd_tmp_addra_dly_depth := SLV_TO_INT(addra_tmp(14 downto 5));
prcd_write_ram_col (web_tmp(0), wea_tmp(0), dia_tmp(7 downto 0), dipa_tmp(0), mem(prcd_tmp_addra_dly_depth)(7 downto 0), memp(prcd_tmp_addra_dly_depth)(0));
if (seq = "00") then
prcd_chk_for_col_msg (wea_tmp(0), web_tmp(0), addra_tmp, addrb_tmp, col_wr_wr_msg, col_wra_rdb_msg, col_wrb_rda_msg);
end if;
prcd_write_ram_col (web_tmp(1), wea_tmp(1), dia_tmp(15 downto 8), dipa_tmp(1), mem(prcd_tmp_addra_dly_depth)(15 downto 8), memp(prcd_tmp_addra_dly_depth)(1));
if (seq = "00") then
prcd_chk_for_col_msg (wea_tmp(1), web_tmp(1), addra_tmp, addrb_tmp, col_wr_wr_msg, col_wra_rdb_msg, col_wrb_rda_msg);
end if;
prcd_write_ram_col (web_tmp(2), wea_tmp(2), dia_tmp(23 downto 16), dipa_tmp(2), mem(prcd_tmp_addra_dly_depth)(23 downto 16), memp(prcd_tmp_addra_dly_depth)(2));
if (seq = "00") then
prcd_chk_for_col_msg (wea_tmp(2), web_tmp(2), addra_tmp, addrb_tmp, col_wr_wr_msg, col_wra_rdb_msg, col_wrb_rda_msg);
end if;
prcd_write_ram_col (web_tmp(3), wea_tmp(3), dia_tmp(31 downto 24), dipa_tmp(3), mem(prcd_tmp_addra_dly_depth)(31 downto 24), memp(prcd_tmp_addra_dly_depth)(3));
if (seq = "00") then
prcd_chk_for_col_msg (wea_tmp(3), web_tmp(3), addra_tmp, addrb_tmp, col_wr_wr_msg, col_wra_rdb_msg, col_wrb_rda_msg);
end if;
end if;
when 64 => null;
-- prcd_tmp_addra_dly_depth := SLV_TO_INT(addra_tmp(14 downto 6));
-- prcd_write_ram_col ('0', '1', dia_tmp(7 downto 0), dipa_tmp(0), mem(prcd_tmp_addra_dly_depth)(7 downto 0), memp(prcd_tmp_addra_dly_depth)(0));
---- if (seq = "00")
---- prcd_chk_for_col_msg (wea_tmp(0), web_tmp(0), addra_tmp, addrb_tmp);
--
-- prcd_write_ram_col ('0', '1', dia_tmp(15 downto 8), dipa_tmp(1), mem(prcd_tmp_addra_dly_depth)(15 downto 8), memp(prcd_tmp_addra_dly_depth)(1));
---- if (seq = "00")
---- prcd_chk_for_col_msg (wea_tmp(1), web_tmp(1), addra_tmp, addrb_tmp);
--
-- prcd_write_ram_col ('0', '1', dia_tmp(23 downto 16), dipa_tmp(2), mem(prcd_tmp_addra_dly_depth)(23 downto 16), memp(prcd_tmp_addra_dly_depth)(2));
---- if (seq = "00")
---- prcd_chk_for_col_msg (wea_tmp(2), web_tmp(2), addra_tmp, addrb_tmp);
--
-- prcd_write_ram_col ('0', '1', dia_tmp(31 downto 24), dipa_tmp(3), mem(prcd_tmp_addra_dly_depth)(31 downto 24), memp(prcd_tmp_addra_dly_depth)(3));
---- if (seq = "00")
---- prcd_chk_for_col_msg (wea_tmp(3), web_tmp(3), addra_tmp, addrb_tmp);
--
-- prcd_write_ram_col ('0', '1', dia_tmp(39 downto 32), dipa_tmp(4), mem(prcd_tmp_addra_dly_depth)(39 downto 32), memp(prcd_tmp_addra_dly_depth)(4));
---- if (seq = "00")
---- prcd_chk_for_col_msg (wea_tmp(4), web_tmp(4), addra_tmp, addrb_tmp);
--
-- prcd_write_ram_col ('0', '1', dia_tmp(47 downto 40), dipa_tmp(5), mem(prcd_tmp_addra_dly_depth)(47 downto 40), memp(prcd_tmp_addra_dly_depth)(5));
---- if (seq = "00")
---- prcd_chk_for_col_msg (wea_tmp(5), web_tmp(5), addra_tmp, addrb_tmp);
--
-- prcd_write_ram_col ('0', '1', dia_tmp(55 downto 48), dipa_tmp(6), mem(prcd_tmp_addra_dly_depth)(55 downto 48), memp(prcd_tmp_addra_dly_depth)(6));
---- if (seq = "00")
---- prcd_chk_for_col_msg (wea_tmp(6), web_tmp(6), addra_tmp, addrb_tmp);
--
-- prcd_write_ram_col ('0', '1', dia_tmp(63 downto 56), dipa_tmp(7), mem(prcd_tmp_addra_dly_depth)(63 downto 56), memp(prcd_tmp_addra_dly_depth)(7));
---- if (seq = "00")
---- prcd_chk_for_col_msg (wea_tmp(7), web_tmp(7), addra_tmp, addrb_tmp);
--
when others => null;
end case;
end prcd_col_wr_ram_a;
procedure prcd_col_wr_ram_b (
constant seq : in std_logic_vector (1 downto 0);
constant wea_tmp : in std_logic_vector (7 downto 0);
constant web_tmp : in std_logic_vector (7 downto 0);
constant dib_tmp : in std_logic_vector (63 downto 0);
constant dipb_tmp : in std_logic_vector (7 downto 0);
constant addra_tmp : in std_logic_vector (15 downto 0);
constant addrb_tmp : in std_logic_vector (15 downto 0);
variable mem : inout Two_D_array_type;
variable memp : inout Two_D_parity_array_type;
variable col_wr_wr_msg : inout std_ulogic;
variable col_wra_rdb_msg : inout std_ulogic;
variable col_wrb_rda_msg : inout std_ulogic
) is
variable prcd_tmp_addrb_dly_depth : integer;
variable prcd_tmp_addrb_dly_width : integer;
variable junk : std_ulogic;
begin
case wb_width is
when 1 | 2 | 4 => if (not(wea_tmp(0) = '1' and web_tmp(0) = '1' and wb_width > wa_width) or seq = "10") then
if (wb_width >= width) then
prcd_tmp_addrb_dly_depth := SLV_TO_INT(addrb_tmp(14 downto w_addrb_lbit_124));
prcd_write_ram_col (wea_tmp(0), web_tmp(0), dib_tmp(wb_width-1 downto 0), '0', mem(prcd_tmp_addrb_dly_depth), junk);
else
prcd_tmp_addrb_dly_depth := SLV_TO_INT(addrb_tmp(14 downto w_addrb_bit_124 + 1));
prcd_tmp_addrb_dly_width := SLV_TO_INT(addrb_tmp(w_addrb_bit_124 downto w_addrb_lbit_124));
prcd_write_ram_col (wea_tmp(0), web_tmp(0), dib_tmp(wb_width-1 downto 0), '0', mem(prcd_tmp_addrb_dly_depth)((prcd_tmp_addrb_dly_width * wb_width) + wb_width - 1 downto (prcd_tmp_addrb_dly_width * wb_width)), junk);
end if;
if (seq = "00") then
prcd_chk_for_col_msg (wea_tmp(0), web_tmp(0), addra_tmp, addrb_tmp, col_wr_wr_msg, col_wra_rdb_msg, col_wrb_rda_msg);
end if;
end if;
when 8 => if (not(wea_tmp(0) = '1' and web_tmp(0) = '1' and wb_width > wa_width) or seq = "10") then
if (wb_width >= width) then
prcd_tmp_addrb_dly_depth := SLV_TO_INT(addrb_tmp(14 downto 3));
prcd_write_ram_col (wea_tmp(0), web_tmp(0), dib_tmp(7 downto 0), dipb_tmp(0), mem(prcd_tmp_addrb_dly_depth), memp(prcd_tmp_addrb_dly_depth)(0));
else
prcd_tmp_addrb_dly_depth := SLV_TO_INT(addrb_tmp(14 downto w_addrb_bit_8 + 1));
prcd_tmp_addrb_dly_width := SLV_TO_INT(addrb_tmp(w_addrb_bit_8 downto 3));
prcd_write_ram_col (wea_tmp(0), web_tmp(0), dib_tmp(7 downto 0), dipb_tmp(0), mem(prcd_tmp_addrb_dly_depth)((prcd_tmp_addrb_dly_width * 8) + 7 downto (prcd_tmp_addrb_dly_width * 8)), memp(prcd_tmp_addrb_dly_depth)((prcd_tmp_addrb_dly_width)));
end if;
if (seq = "00") then
prcd_chk_for_col_msg (wea_tmp(0), web_tmp(0), addra_tmp, addrb_tmp, col_wr_wr_msg, col_wra_rdb_msg, col_wrb_rda_msg);
end if;
end if;
when 16 => if (not(wea_tmp(0) = '1' and web_tmp(0) = '1' and wb_width > wa_width) or seq = "10") then
if (wb_width >= width) then
prcd_tmp_addrb_dly_depth := SLV_TO_INT(addrb_tmp(14 downto 4));
prcd_write_ram_col (wea_tmp(0), web_tmp(0), dib_tmp(7 downto 0), dipb_tmp(0), mem(prcd_tmp_addrb_dly_depth)(7 downto 0), memp(prcd_tmp_addrb_dly_depth)(0));
else
prcd_tmp_addrb_dly_depth := SLV_TO_INT(addrb_tmp(14 downto w_addrb_bit_16 + 1));
prcd_tmp_addrb_dly_width := SLV_TO_INT(addrb_tmp(w_addrb_bit_16 downto 4));
prcd_write_ram_col (wea_tmp(0), web_tmp(0), dib_tmp(7 downto 0), dipb_tmp(0), mem(prcd_tmp_addrb_dly_depth)((prcd_tmp_addrb_dly_width * 16) + 7 downto (prcd_tmp_addrb_dly_width * 16)), memp(prcd_tmp_addrb_dly_depth)((prcd_tmp_addrb_dly_width * 2)));
end if;
if (seq = "00") then
prcd_chk_for_col_msg (wea_tmp(0), web_tmp(0), addra_tmp, addrb_tmp, col_wr_wr_msg, col_wra_rdb_msg, col_wrb_rda_msg);
end if;
if (wb_width >= width) then
prcd_tmp_addrb_dly_depth := SLV_TO_INT(addrb_tmp(14 downto 4));
prcd_write_ram_col (wea_tmp(1), web_tmp(1), dib_tmp(15 downto 8), dipb_tmp(1), mem(prcd_tmp_addrb_dly_depth)(15 downto 8), memp(prcd_tmp_addrb_dly_depth)(1));
else
prcd_tmp_addrb_dly_depth := SLV_TO_INT(addrb_tmp(14 downto w_addrb_bit_16 + 1));
prcd_tmp_addrb_dly_width := SLV_TO_INT(addrb_tmp(w_addrb_bit_16 downto 4));
prcd_write_ram_col (wea_tmp(1), web_tmp(1), dib_tmp(15 downto 8), dipb_tmp(1), mem(prcd_tmp_addrb_dly_depth)((prcd_tmp_addrb_dly_width * 16) + 15 downto (prcd_tmp_addrb_dly_width * 16) + 8), memp(prcd_tmp_addrb_dly_depth)((prcd_tmp_addrb_dly_width * 2) + 1));
end if;
if (seq = "00") then
prcd_chk_for_col_msg (wea_tmp(1), web_tmp(1), addra_tmp, addrb_tmp, col_wr_wr_msg, col_wra_rdb_msg, col_wrb_rda_msg);
end if;
end if;
when 32 => if (not(wea_tmp(0) = '1' and web_tmp(0) = '1' and wb_width > wa_width) or seq = "10") then
prcd_tmp_addrb_dly_depth := SLV_TO_INT(addrb_tmp(14 downto 5));
prcd_write_ram_col (wea_tmp(0), web_tmp(0), dib_tmp(7 downto 0), dipb_tmp(0), mem(prcd_tmp_addrb_dly_depth)(7 downto 0), memp(prcd_tmp_addrb_dly_depth)(0));
if (seq = "00") then
prcd_chk_for_col_msg (wea_tmp(0), web_tmp(0), addra_tmp, addrb_tmp, col_wr_wr_msg, col_wra_rdb_msg, col_wrb_rda_msg);
end if;
prcd_write_ram_col (wea_tmp(1), web_tmp(1), dib_tmp(15 downto 8), dipb_tmp(1), mem(prcd_tmp_addrb_dly_depth)(15 downto 8), memp(prcd_tmp_addrb_dly_depth)(1));
if (seq = "00") then
prcd_chk_for_col_msg (wea_tmp(1), web_tmp(1), addra_tmp, addrb_tmp, col_wr_wr_msg, col_wra_rdb_msg, col_wrb_rda_msg);
end if;
prcd_write_ram_col (wea_tmp(2), web_tmp(2), dib_tmp(23 downto 16), dipb_tmp(2), mem(prcd_tmp_addrb_dly_depth)(23 downto 16), memp(prcd_tmp_addrb_dly_depth)(2));
if (seq = "00") then
prcd_chk_for_col_msg (wea_tmp(2), web_tmp(2), addra_tmp, addrb_tmp, col_wr_wr_msg, col_wra_rdb_msg, col_wrb_rda_msg);
end if;
prcd_write_ram_col (wea_tmp(3), web_tmp(3), dib_tmp(31 downto 24), dipb_tmp(3), mem(prcd_tmp_addrb_dly_depth)(31 downto 24), memp(prcd_tmp_addrb_dly_depth)(3));
if (seq = "00") then
prcd_chk_for_col_msg (wea_tmp(3), web_tmp(3), addra_tmp, addrb_tmp, col_wr_wr_msg, col_wra_rdb_msg, col_wrb_rda_msg);
end if;
end if;
when 64 =>
prcd_tmp_addrb_dly_depth := SLV_TO_INT(addrb_tmp(14 downto 6));
prcd_write_ram_col (wea_tmp(0), web_tmp(0), dib_tmp(7 downto 0), dipb_tmp(0), mem(prcd_tmp_addrb_dly_depth)(7 downto 0), memp(prcd_tmp_addrb_dly_depth)(0));
if (seq = "00") then
prcd_chk_for_col_msg (wea_tmp(0), web_tmp(0), addra_tmp, addrb_tmp, col_wr_wr_msg, col_wra_rdb_msg, col_wrb_rda_msg);
end if;
prcd_write_ram_col (wea_tmp(1), web_tmp(1), dib_tmp(15 downto 8), dipb_tmp(1), mem(prcd_tmp_addrb_dly_depth)(15 downto 8), memp(prcd_tmp_addrb_dly_depth)(1));
if (seq = "00") then
prcd_chk_for_col_msg (wea_tmp(1), web_tmp(1), addra_tmp, addrb_tmp, col_wr_wr_msg, col_wra_rdb_msg, col_wrb_rda_msg);
end if;
prcd_write_ram_col (wea_tmp(2), web_tmp(2), dib_tmp(23 downto 16), dipb_tmp(2), mem(prcd_tmp_addrb_dly_depth)(23 downto 16), memp(prcd_tmp_addrb_dly_depth)(2));
if (seq = "00") then
prcd_chk_for_col_msg (wea_tmp(2), web_tmp(2), addra_tmp, addrb_tmp, col_wr_wr_msg, col_wra_rdb_msg, col_wrb_rda_msg);
end if;
prcd_write_ram_col (wea_tmp(3), web_tmp(3), dib_tmp(31 downto 24), dipb_tmp(3), mem(prcd_tmp_addrb_dly_depth)(31 downto 24), memp(prcd_tmp_addrb_dly_depth)(3));
if (seq = "00") then
prcd_chk_for_col_msg (wea_tmp(3), web_tmp(3), addra_tmp, addrb_tmp, col_wr_wr_msg, col_wra_rdb_msg, col_wrb_rda_msg);
end if;
prcd_write_ram_col (wea_tmp(4), web_tmp(4), dib_tmp(39 downto 32), dipb_tmp(4), mem(prcd_tmp_addrb_dly_depth)(39 downto 32), memp(prcd_tmp_addrb_dly_depth)(4));
if (seq = "00") then
prcd_chk_for_col_msg (wea_tmp(4), web_tmp(4), addra_tmp, addrb_tmp, col_wr_wr_msg, col_wra_rdb_msg, col_wrb_rda_msg);
end if;
prcd_write_ram_col (wea_tmp(5), web_tmp(5), dib_tmp(47 downto 40), dipb_tmp(5), mem(prcd_tmp_addrb_dly_depth)(47 downto 40), memp(prcd_tmp_addrb_dly_depth)(5));
if (seq = "00") then
prcd_chk_for_col_msg (wea_tmp(5), web_tmp(5), addra_tmp, addrb_tmp, col_wr_wr_msg, col_wra_rdb_msg, col_wrb_rda_msg);
end if;
prcd_write_ram_col (wea_tmp(6), web_tmp(6), dib_tmp(55 downto 48), dipb_tmp(6), mem(prcd_tmp_addrb_dly_depth)(55 downto 48), memp(prcd_tmp_addrb_dly_depth)(6));
if (seq = "00") then
prcd_chk_for_col_msg (wea_tmp(6), web_tmp(6), addra_tmp, addrb_tmp, col_wr_wr_msg, col_wra_rdb_msg, col_wrb_rda_msg);
end if;
prcd_write_ram_col (wea_tmp(7), web_tmp(7), dib_tmp(63 downto 56), dipb_tmp(7), mem(prcd_tmp_addrb_dly_depth)(63 downto 56), memp(prcd_tmp_addrb_dly_depth)(7));
if (seq = "00") then
prcd_chk_for_col_msg (wea_tmp(7), web_tmp(7), addra_tmp, addrb_tmp, col_wr_wr_msg, col_wra_rdb_msg, col_wrb_rda_msg);
end if;
when others => null;
end case;
end prcd_col_wr_ram_b;
procedure prcd_col_rd_ram_a (
constant viol_type_tmp : in std_logic_vector (1 downto 0);
constant seq : in std_logic_vector (1 downto 0);
constant web_tmp : in std_logic_vector (7 downto 0);
constant wea_tmp : in std_logic_vector (7 downto 0);
constant addra_tmp : in std_logic_vector (15 downto 0);
variable doa_tmp : inout std_logic_vector (63 downto 0);
variable dopa_tmp : inout std_logic_vector (7 downto 0);
constant mem : in Two_D_array_type;
constant memp : in Two_D_parity_array_type;
constant wr_mode_a_tmp : in std_logic_vector (1 downto 0)
) is
variable prcd_tmp_addra_dly_depth : integer;
variable prcd_tmp_addra_dly_width : integer;
variable junk : std_ulogic;
variable doa_ltmp : std_logic_vector (63 downto 0);
variable dopa_ltmp : std_logic_vector (7 downto 0);
begin
doa_ltmp := (others => '0');
dopa_ltmp := (others => '0');
case ra_width is
when 1 | 2 | 4 => if ((web_tmp(0) = '1' and wea_tmp(0) = '1') or (seq = "01" and web_tmp(0) = '1' and wea_tmp(0) = '0' and viol_type_tmp = "10") or (seq = "01" and WRITE_MODE_A /= "READ_FIRST" and WRITE_MODE_B /= "READ_FIRST") or (seq = "01" and WRITE_MODE_A = "READ_FIRST" and WRITE_MODE_B /= "READ_FIRST" and web_tmp(0) = '1') or (seq = "11" and WRITE_MODE_A = "WRITE_FIRST" and web_tmp(0) /= '1')) then
if (ra_width >= width) then
prcd_tmp_addra_dly_depth := SLV_TO_INT(addra_tmp(14 downto r_addra_lbit_124));
doa_ltmp(ra_width-1 downto 0) := mem(prcd_tmp_addra_dly_depth);
else
prcd_tmp_addra_dly_depth := SLV_TO_INT(addra_tmp(14 downto r_addra_bit_124 + 1));
prcd_tmp_addra_dly_width := SLV_TO_INT(addra_tmp(r_addra_bit_124 downto r_addra_lbit_124));
doa_ltmp(ra_width-1 downto 0) := mem(prcd_tmp_addra_dly_depth)(((prcd_tmp_addra_dly_width * ra_width) + ra_width - 1) downto (prcd_tmp_addra_dly_width * ra_width));
end if;
prcd_x_buf (wr_mode_a_tmp, 3, 0, 0, doa_ltmp, doa_tmp, dopa_ltmp, dopa_tmp);
end if;
when 8 => if ((web_tmp(0) = '1' and wea_tmp(0) = '1') or (seq = "01" and web_tmp(0) = '1' and wea_tmp(0) = '0' and viol_type_tmp = "10") or (seq = "01" and WRITE_MODE_A /= "READ_FIRST" and WRITE_MODE_B /= "READ_FIRST") or (seq = "01" and WRITE_MODE_A = "READ_FIRST" and WRITE_MODE_B /= "READ_FIRST" and web_tmp(0) = '1') or (seq = "11" and WRITE_MODE_A = "WRITE_FIRST" and web_tmp(0) /= '1')) then
if (ra_width >= width) then
prcd_tmp_addra_dly_depth := SLV_TO_INT(addra_tmp(14 downto 3));
doa_ltmp(7 downto 0) := mem(prcd_tmp_addra_dly_depth);
dopa_ltmp(0) := memp(prcd_tmp_addra_dly_depth)(0);
else
prcd_tmp_addra_dly_depth := SLV_TO_INT(addra_tmp(14 downto r_addra_bit_8 + 1));
prcd_tmp_addra_dly_width := SLV_TO_INT(addra_tmp(r_addra_bit_8 downto 3));
doa_ltmp(7 downto 0) := mem(prcd_tmp_addra_dly_depth)(((prcd_tmp_addra_dly_width * 8) + 7) downto (prcd_tmp_addra_dly_width * 8));
dopa_ltmp(0) := memp(prcd_tmp_addra_dly_depth)(prcd_tmp_addra_dly_width);
end if;
prcd_x_buf (wr_mode_a_tmp, 7, 0, 0, doa_ltmp, doa_tmp, dopa_ltmp, dopa_tmp);
end if;
when 16 => if ((web_tmp(0) = '1' and wea_tmp(0) = '1') or (seq = "01" and web_tmp(0) = '1' and wea_tmp(0) = '0' and viol_type_tmp = "10") or (seq = "01" and WRITE_MODE_A /= "READ_FIRST" and WRITE_MODE_B /= "READ_FIRST") or (seq = "01" and WRITE_MODE_A = "READ_FIRST" and WRITE_MODE_B /= "READ_FIRST" and web_tmp(0) = '1') or (seq = "11" and WRITE_MODE_A = "WRITE_FIRST" and web_tmp(0) /= '1')) then
if (ra_width >= width) then
prcd_tmp_addra_dly_depth := SLV_TO_INT(addra_tmp(14 downto 4));
doa_ltmp(7 downto 0) := mem(prcd_tmp_addra_dly_depth)(7 downto 0);
dopa_ltmp(0) := memp(prcd_tmp_addra_dly_depth)(0);
else
prcd_tmp_addra_dly_depth := SLV_TO_INT(addra_tmp(14 downto r_addra_bit_16 + 1));
prcd_tmp_addra_dly_width := SLV_TO_INT(addra_tmp(r_addra_bit_16 downto 4));
doa_ltmp(7 downto 0) := mem(prcd_tmp_addra_dly_depth)(((prcd_tmp_addra_dly_width * 16) + 7) downto (prcd_tmp_addra_dly_width * 16));
dopa_ltmp(0) := memp(prcd_tmp_addra_dly_depth)(prcd_tmp_addra_dly_width * 2);
end if;
prcd_x_buf (wr_mode_a_tmp, 7, 0, 0, doa_ltmp, doa_tmp, dopa_ltmp, dopa_tmp);
end if;
if ((web_tmp(1) = '1' and wea_tmp(1) = '1') or (seq = "01" and web_tmp(1) = '1' and wea_tmp(1) = '0' and viol_type_tmp = "10") or (seq = "01" and WRITE_MODE_A /= "READ_FIRST" and WRITE_MODE_B /= "READ_FIRST") or (seq = "01" and WRITE_MODE_A = "READ_FIRST" and WRITE_MODE_B /= "READ_FIRST" and web_tmp(1) = '1') or (seq = "11" and WRITE_MODE_A = "WRITE_FIRST" and web_tmp(1) /= '1')) then
if (ra_width >= width) then
prcd_tmp_addra_dly_depth := SLV_TO_INT(addra_tmp(14 downto 4));
doa_ltmp(15 downto 8) := mem(prcd_tmp_addra_dly_depth)(15 downto 8);
dopa_ltmp(1) := memp(prcd_tmp_addra_dly_depth)(1);
else
prcd_tmp_addra_dly_depth := SLV_TO_INT(addra_tmp(14 downto r_addra_bit_16 + 1));
prcd_tmp_addra_dly_width := SLV_TO_INT(addra_tmp(r_addra_bit_16 downto 4));
doa_ltmp(15 downto 8) := mem(prcd_tmp_addra_dly_depth)(((prcd_tmp_addra_dly_width * 16) + 15) downto ((prcd_tmp_addra_dly_width * 16) + 8));
dopa_ltmp(1) := memp(prcd_tmp_addra_dly_depth)((prcd_tmp_addra_dly_width * 2) + 1);
end if;
prcd_x_buf (wr_mode_a_tmp, 15, 8, 1, doa_ltmp, doa_tmp, dopa_ltmp, dopa_tmp);
end if;
when 32 => if (ra_width >= width) then
prcd_tmp_addra_dly_depth := SLV_TO_INT(addra_tmp(14 downto 5));
if ((web_tmp(0) = '1' and wea_tmp(0) = '1') or (seq = "01" and web_tmp(0) = '1' and wea_tmp(0) = '0' and viol_type_tmp = "10") or (seq = "01" and WRITE_MODE_A /= "READ_FIRST" and WRITE_MODE_B /= "READ_FIRST") or (seq = "01" and WRITE_MODE_A = "READ_FIRST" and WRITE_MODE_B /= "READ_FIRST" and web_tmp(0) = '1') or (seq = "11" and WRITE_MODE_A = "WRITE_FIRST" and web_tmp(0) /= '1')) then
doa_ltmp(7 downto 0) := mem(prcd_tmp_addra_dly_depth)(7 downto 0);
dopa_ltmp(0) := memp(prcd_tmp_addra_dly_depth)(0);
prcd_x_buf (wr_mode_a_tmp, 7, 0, 0, doa_ltmp, doa_tmp, dopa_ltmp, dopa_tmp);
end if;
if ((web_tmp(1) = '1' and wea_tmp(1) = '1') or (seq = "01" and web_tmp(1) = '1' and wea_tmp(1) = '0' and viol_type_tmp = "10") or (seq = "01" and WRITE_MODE_A /= "READ_FIRST" and WRITE_MODE_B /= "READ_FIRST") or (seq = "01" and WRITE_MODE_A = "READ_FIRST" and WRITE_MODE_B /= "READ_FIRST" and web_tmp(1) = '1') or (seq = "11" and WRITE_MODE_A = "WRITE_FIRST" and web_tmp(1) /= '1')) then
doa_ltmp(15 downto 8) := mem(prcd_tmp_addra_dly_depth)(15 downto 8);
dopa_ltmp(1) := memp(prcd_tmp_addra_dly_depth)(1);
prcd_x_buf (wr_mode_a_tmp, 15, 8, 1, doa_ltmp, doa_tmp, dopa_ltmp, dopa_tmp);
end if;
if ((web_tmp(2) = '1' and wea_tmp(2) = '1') or (seq = "01" and web_tmp(2) = '1' and wea_tmp(2) = '0' and viol_type_tmp = "10") or (seq = "01" and WRITE_MODE_A /= "READ_FIRST" and WRITE_MODE_B /= "READ_FIRST") or (seq = "01" and WRITE_MODE_A = "READ_FIRST" and WRITE_MODE_B /= "READ_FIRST" and web_tmp(2) = '1') or (seq = "11" and WRITE_MODE_A = "WRITE_FIRST" and web_tmp(2) /= '1')) then
doa_ltmp(23 downto 16) := mem(prcd_tmp_addra_dly_depth)(23 downto 16);
dopa_ltmp(2) := memp(prcd_tmp_addra_dly_depth)(2);
prcd_x_buf (wr_mode_a_tmp, 23, 16, 2, doa_ltmp, doa_tmp, dopa_ltmp, dopa_tmp);
end if;
if ((web_tmp(3) = '1' and wea_tmp(3) = '1') or (seq = "01" and web_tmp(3) = '1' and wea_tmp(3) = '0' and viol_type_tmp = "10") or (seq = "01" and WRITE_MODE_A /= "READ_FIRST" and WRITE_MODE_B /= "READ_FIRST") or (seq = "01" and WRITE_MODE_A = "READ_FIRST" and WRITE_MODE_B /= "READ_FIRST" and web_tmp(3) = '1') or (seq = "11" and WRITE_MODE_A = "WRITE_FIRST" and web_tmp(3) /= '1')) then
doa_ltmp(31 downto 24) := mem(prcd_tmp_addra_dly_depth)(31 downto 24);
dopa_ltmp(3) := memp(prcd_tmp_addra_dly_depth)(3);
prcd_x_buf (wr_mode_a_tmp, 31, 24, 3, doa_ltmp, doa_tmp, dopa_ltmp, dopa_tmp);
end if;
end if;
when 64 =>
prcd_tmp_addra_dly_depth := SLV_TO_INT(addra_tmp(14 downto 6));
if ((web_tmp(0) = '1' and wea_tmp(0) = '1') or (seq = "01" and web_tmp(0) = '1' and wea_tmp(0) = '0' and viol_type_tmp = "10") or (seq = "01" and WRITE_MODE_A /= "READ_FIRST" and WRITE_MODE_B /= "READ_FIRST") or (seq = "01" and WRITE_MODE_A = "READ_FIRST" and WRITE_MODE_B /= "READ_FIRST" and web_tmp(0) = '1') or (seq = "11" and WRITE_MODE_A = "WRITE_FIRST" and web_tmp(0) /= '1')) then
doa_ltmp(7 downto 0) := mem(prcd_tmp_addra_dly_depth)(7 downto 0);
dopa_ltmp(0) := memp(prcd_tmp_addra_dly_depth)(0);
prcd_x_buf (wr_mode_a_tmp, 7, 0, 0, doa_ltmp, doa_tmp, dopa_ltmp, dopa_tmp);
end if;
if ((web_tmp(1) = '1' and wea_tmp(1) = '1') or (seq = "01" and web_tmp(1) = '1' and wea_tmp(1) = '0' and viol_type_tmp = "10") or (seq = "01" and WRITE_MODE_A /= "READ_FIRST" and WRITE_MODE_B /= "READ_FIRST") or (seq = "01" and WRITE_MODE_A = "READ_FIRST" and WRITE_MODE_B /= "READ_FIRST" and web_tmp(1) = '1') or (seq = "11" and WRITE_MODE_A = "WRITE_FIRST" and web_tmp(1) /= '1')) then
doa_ltmp(15 downto 8) := mem(prcd_tmp_addra_dly_depth)(15 downto 8);
dopa_ltmp(1) := memp(prcd_tmp_addra_dly_depth)(1);
prcd_x_buf (wr_mode_a_tmp, 15, 8, 1, doa_ltmp, doa_tmp, dopa_ltmp, dopa_tmp);
end if;
if ((web_tmp(2) = '1' and wea_tmp(2) = '1') or (seq = "01" and web_tmp(2) = '1' and wea_tmp(2) = '0' and viol_type_tmp = "10") or (seq = "01" and WRITE_MODE_A /= "READ_FIRST" and WRITE_MODE_B /= "READ_FIRST") or (seq = "01" and WRITE_MODE_A = "READ_FIRST" and WRITE_MODE_B /= "READ_FIRST" and web_tmp(2) = '1') or (seq = "11" and WRITE_MODE_A = "WRITE_FIRST" and web_tmp(2) /= '1')) then
doa_ltmp(23 downto 16) := mem(prcd_tmp_addra_dly_depth)(23 downto 16);
dopa_ltmp(2) := memp(prcd_tmp_addra_dly_depth)(2);
prcd_x_buf (wr_mode_a_tmp, 23, 16, 2, doa_ltmp, doa_tmp, dopa_ltmp, dopa_tmp);
end if;
if ((web_tmp(3) = '1' and wea_tmp(3) = '1') or (seq = "01" and web_tmp(3) = '1' and wea_tmp(3) = '0' and viol_type_tmp = "10") or (seq = "01" and WRITE_MODE_A /= "READ_FIRST" and WRITE_MODE_B /= "READ_FIRST") or (seq = "01" and WRITE_MODE_A = "READ_FIRST" and WRITE_MODE_B /= "READ_FIRST" and web_tmp(3) = '1') or (seq = "11" and WRITE_MODE_A = "WRITE_FIRST" and web_tmp(3) /= '1')) then
doa_ltmp(31 downto 24) := mem(prcd_tmp_addra_dly_depth)(31 downto 24);
dopa_ltmp(3) := memp(prcd_tmp_addra_dly_depth)(3);
prcd_x_buf (wr_mode_a_tmp, 31, 24, 3, doa_ltmp, doa_tmp, dopa_ltmp, dopa_tmp);
end if;
if ((web_tmp(4) = '1' and wea_tmp(4) = '1') or (seq = "01" and web_tmp(4) = '1' and wea_tmp(4) = '0' and viol_type_tmp = "10") or (seq = "01" and WRITE_MODE_A /= "READ_FIRST" and WRITE_MODE_B /= "READ_FIRST") or (seq = "01" and WRITE_MODE_A = "READ_FIRST" and WRITE_MODE_B /= "READ_FIRST" and web_tmp(4) = '1') or (seq = "11" and WRITE_MODE_A = "WRITE_FIRST" and web_tmp(4) /= '1')) then
doa_ltmp(39 downto 32) := mem(prcd_tmp_addra_dly_depth)(39 downto 32);
dopa_ltmp(4) := memp(prcd_tmp_addra_dly_depth)(4);
prcd_x_buf (wr_mode_a_tmp, 39, 32, 4, doa_ltmp, doa_tmp, dopa_ltmp, dopa_tmp);
end if;
if ((web_tmp(5) = '1' and wea_tmp(5) = '1') or (seq = "01" and web_tmp(5) = '1' and wea_tmp(5) = '0' and viol_type_tmp = "10") or (seq = "01" and WRITE_MODE_A /= "READ_FIRST" and WRITE_MODE_B /= "READ_FIRST") or (seq = "01" and WRITE_MODE_A = "READ_FIRST" and WRITE_MODE_B /= "READ_FIRST" and web_tmp(5) = '1') or (seq = "11" and WRITE_MODE_A = "WRITE_FIRST" and web_tmp(5) /= '1')) then
doa_ltmp(47 downto 40) := mem(prcd_tmp_addra_dly_depth)(47 downto 40);
dopa_ltmp(5) := memp(prcd_tmp_addra_dly_depth)(5);
prcd_x_buf (wr_mode_a_tmp, 47, 40, 5, doa_ltmp, doa_tmp, dopa_ltmp, dopa_tmp);
end if;
if ((web_tmp(6) = '1' and wea_tmp(6) = '1') or (seq = "01" and web_tmp(6) = '1' and wea_tmp(6) = '0' and viol_type_tmp = "10") or (seq = "01" and WRITE_MODE_A /= "READ_FIRST" and WRITE_MODE_B /= "READ_FIRST") or (seq = "01" and WRITE_MODE_A = "READ_FIRST" and WRITE_MODE_B /= "READ_FIRST" and web_tmp(6) = '1') or (seq = "11" and WRITE_MODE_A = "WRITE_FIRST" and web_tmp(6) /= '1')) then
doa_ltmp(55 downto 48) := mem(prcd_tmp_addra_dly_depth)(55 downto 48);
dopa_ltmp(6) := memp(prcd_tmp_addra_dly_depth)(6);
prcd_x_buf (wr_mode_a_tmp, 55, 48, 6, doa_ltmp, doa_tmp, dopa_ltmp, dopa_tmp);
end if;
if ((web_tmp(7) = '1' and wea_tmp(7) = '1') or (seq = "01" and web_tmp(7) = '1' and wea_tmp(7) = '0' and viol_type_tmp = "10") or (seq = "01" and WRITE_MODE_A /= "READ_FIRST" and WRITE_MODE_B /= "READ_FIRST") or (seq = "01" and WRITE_MODE_A = "READ_FIRST" and WRITE_MODE_B /= "READ_FIRST" and web_tmp(7) = '1') or (seq = "11" and WRITE_MODE_A = "WRITE_FIRST" and web_tmp(7) /= '1')) then
doa_ltmp(63 downto 56) := mem(prcd_tmp_addra_dly_depth)(63 downto 56);
dopa_ltmp(7) := memp(prcd_tmp_addra_dly_depth)(7);
prcd_x_buf (wr_mode_a_tmp, 63, 56, 7, doa_ltmp, doa_tmp, dopa_ltmp, dopa_tmp);
end if;
when others => null;
end case;
end prcd_col_rd_ram_a;
procedure prcd_col_rd_ram_b (
constant viol_type_tmp : in std_logic_vector (1 downto 0);
constant seq : in std_logic_vector (1 downto 0);
constant wea_tmp : in std_logic_vector (7 downto 0);
constant web_tmp : in std_logic_vector (7 downto 0);
constant addrb_tmp : in std_logic_vector (15 downto 0);
variable dob_tmp : inout std_logic_vector (63 downto 0);
variable dopb_tmp : inout std_logic_vector (7 downto 0);
constant mem : in Two_D_array_type;
constant memp : in Two_D_parity_array_type;
constant wr_mode_b_tmp : in std_logic_vector (1 downto 0)
) is
variable prcd_tmp_addrb_dly_depth : integer;
variable prcd_tmp_addrb_dly_width : integer;
variable junk : std_ulogic;
variable dob_ltmp : std_logic_vector (63 downto 0);
variable dopb_ltmp : std_logic_vector (7 downto 0);
begin
dob_ltmp := (others => '0');
dopb_ltmp := (others => '0');
case rb_width is
when 1 | 2 | 4 => if ((web_tmp(0) = '1' and wea_tmp(0) = '1') or (seq = "01" and wea_tmp(0) = '1' and web_tmp(0) = '0' and viol_type_tmp = "11") or (seq = "01" and WRITE_MODE_B /= "READ_FIRST" and WRITE_MODE_A /= "READ_FIRST") or (seq = "01" and WRITE_MODE_B = "READ_FIRST" and WRITE_MODE_A /= "READ_FIRST" and wea_tmp(0) = '1') or (seq = "11" and WRITE_MODE_B = "WRITE_FIRST" and wea_tmp(0) /= '1')) then
if (rb_width >= width) then
prcd_tmp_addrb_dly_depth := SLV_TO_INT(addrb_tmp(14 downto r_addrb_lbit_124));
dob_ltmp(rb_width-1 downto 0) := mem(prcd_tmp_addrb_dly_depth);
else
prcd_tmp_addrb_dly_depth := SLV_TO_INT(addrb_tmp(14 downto r_addrb_bit_124 + 1));
prcd_tmp_addrb_dly_width := SLV_TO_INT(addrb_tmp(r_addrb_bit_124 downto r_addrb_lbit_124));
dob_ltmp(rb_width-1 downto 0) := mem(prcd_tmp_addrb_dly_depth)(((prcd_tmp_addrb_dly_width * rb_width) + rb_width - 1) downto (prcd_tmp_addrb_dly_width * rb_width));
end if;
prcd_x_buf (wr_mode_b_tmp, 3, 0, 0, dob_ltmp, dob_tmp, dopb_ltmp, dopb_tmp);
end if;
when 8 => if ((web_tmp(0) = '1' and wea_tmp(0) = '1') or (seq = "01" and wea_tmp(0) = '1' and web_tmp(0) = '0' and viol_type_tmp = "11") or (seq = "01" and WRITE_MODE_B /= "READ_FIRST" and WRITE_MODE_A /= "READ_FIRST") or (seq = "01" and WRITE_MODE_B = "READ_FIRST" and WRITE_MODE_A /= "READ_FIRST" and wea_tmp(0) = '1') or (seq = "11" and WRITE_MODE_B = "WRITE_FIRST" and wea_tmp(0) /= '1')) then
if (rb_width >= width) then
prcd_tmp_addrb_dly_depth := SLV_TO_INT(addrb_tmp(14 downto 3));
dob_ltmp(7 downto 0) := mem(prcd_tmp_addrb_dly_depth);
dopb_ltmp(0) := memp(prcd_tmp_addrb_dly_depth)(0);
else
prcd_tmp_addrb_dly_depth := SLV_TO_INT(addrb_tmp(14 downto r_addrb_bit_8 + 1));
prcd_tmp_addrb_dly_width := SLV_TO_INT(addrb_tmp(r_addrb_bit_8 downto 3));
dob_ltmp(7 downto 0) := mem(prcd_tmp_addrb_dly_depth)(((prcd_tmp_addrb_dly_width * 8) + 7) downto (prcd_tmp_addrb_dly_width * 8));
dopb_ltmp(0) := memp(prcd_tmp_addrb_dly_depth)(prcd_tmp_addrb_dly_width);
end if;
prcd_x_buf (wr_mode_b_tmp, 7, 0, 0, dob_ltmp, dob_tmp, dopb_ltmp, dopb_tmp);
end if;
when 16 => if ((web_tmp(0) = '1' and wea_tmp(0) = '1') or (seq = "01" and wea_tmp(0) = '1' and web_tmp(0) = '0' and viol_type_tmp = "11") or (seq = "01" and WRITE_MODE_B /= "READ_FIRST" and WRITE_MODE_A /= "READ_FIRST") or (seq = "01" and WRITE_MODE_B = "READ_FIRST" and WRITE_MODE_A /= "READ_FIRST" and wea_tmp(0) = '1') or (seq = "11" and WRITE_MODE_B = "WRITE_FIRST" and wea_tmp(0) /= '1')) then
if (rb_width >= width) then
prcd_tmp_addrb_dly_depth := SLV_TO_INT(addrb_tmp(14 downto 4));
dob_ltmp(7 downto 0) := mem(prcd_tmp_addrb_dly_depth)(7 downto 0);
dopb_ltmp(0) := memp(prcd_tmp_addrb_dly_depth)(0);
else
prcd_tmp_addrb_dly_depth := SLV_TO_INT(addrb_tmp(14 downto r_addrb_bit_16 + 1));
prcd_tmp_addrb_dly_width := SLV_TO_INT(addrb_tmp(r_addrb_bit_16 downto 4));
dob_ltmp(7 downto 0) := mem(prcd_tmp_addrb_dly_depth)(((prcd_tmp_addrb_dly_width * 16) + 7) downto (prcd_tmp_addrb_dly_width * 16));
dopb_ltmp(0) := memp(prcd_tmp_addrb_dly_depth)(prcd_tmp_addrb_dly_width * 2);
end if;
prcd_x_buf (wr_mode_b_tmp, 7, 0, 0, dob_ltmp, dob_tmp, dopb_ltmp, dopb_tmp);
end if;
if ((web_tmp(1) = '1' and wea_tmp(1) = '1') or (seq = "01" and wea_tmp(1) = '1' and web_tmp(1) = '0' and viol_type_tmp = "11") or (seq = "01" and WRITE_MODE_B /= "READ_FIRST" and WRITE_MODE_A /= "READ_FIRST") or (seq = "01" and WRITE_MODE_B = "READ_FIRST" and WRITE_MODE_A /= "READ_FIRST" and wea_tmp(1) = '1') or (seq = "11" and WRITE_MODE_B = "WRITE_FIRST" and wea_tmp(1) /= '1')) then
if (rb_width >= width) then
prcd_tmp_addrb_dly_depth := SLV_TO_INT(addrb_tmp(14 downto 4));
dob_ltmp(15 downto 8) := mem(prcd_tmp_addrb_dly_depth)(15 downto 8);
dopb_ltmp(1) := memp(prcd_tmp_addrb_dly_depth)(1);
else
prcd_tmp_addrb_dly_depth := SLV_TO_INT(addrb_tmp(14 downto r_addrb_bit_16 + 1));
prcd_tmp_addrb_dly_width := SLV_TO_INT(addrb_tmp(r_addrb_bit_16 downto 4));
dob_ltmp(15 downto 8) := mem(prcd_tmp_addrb_dly_depth)(((prcd_tmp_addrb_dly_width * 16) + 15) downto ((prcd_tmp_addrb_dly_width * 16) + 8));
dopb_ltmp(1) := memp(prcd_tmp_addrb_dly_depth)((prcd_tmp_addrb_dly_width * 2) + 1);
end if;
prcd_x_buf (wr_mode_b_tmp, 15, 8, 1, dob_ltmp, dob_tmp, dopb_ltmp, dopb_tmp);
end if;
when 32 => if (rb_width >= width) then
prcd_tmp_addrb_dly_depth := SLV_TO_INT(addrb_tmp(14 downto 5));
if ((web_tmp(0) = '1' and wea_tmp(0) = '1') or (seq = "01" and wea_tmp(0) = '1' and web_tmp(0) = '0' and viol_type_tmp = "11") or (seq = "01" and WRITE_MODE_B /= "READ_FIRST" and WRITE_MODE_A /= "READ_FIRST") or (seq = "01" and WRITE_MODE_B = "READ_FIRST" and WRITE_MODE_A /= "READ_FIRST" and wea_tmp(0) = '1') or (seq = "11" and WRITE_MODE_B = "WRITE_FIRST" and wea_tmp(0) /= '1')) then
dob_ltmp(7 downto 0) := mem(prcd_tmp_addrb_dly_depth)(7 downto 0);
dopb_ltmp(0) := memp(prcd_tmp_addrb_dly_depth)(0);
prcd_x_buf (wr_mode_b_tmp, 7, 0, 0, dob_ltmp, dob_tmp, dopb_ltmp, dopb_tmp);
end if;
if ((web_tmp(1) = '1' and wea_tmp(1) = '1') or (seq = "01" and wea_tmp(1) = '1' and web_tmp(1) = '0' and viol_type_tmp = "11") or (seq = "01" and WRITE_MODE_B /= "READ_FIRST" and WRITE_MODE_A /= "READ_FIRST") or (seq = "01" and WRITE_MODE_B = "READ_FIRST" and WRITE_MODE_A /= "READ_FIRST" and wea_tmp(1) = '1') or (seq = "11" and WRITE_MODE_B = "WRITE_FIRST" and wea_tmp(1) /= '1')) then
dob_ltmp(15 downto 8) := mem(prcd_tmp_addrb_dly_depth)(15 downto 8);
dopb_ltmp(1) := memp(prcd_tmp_addrb_dly_depth)(1);
prcd_x_buf (wr_mode_b_tmp, 15, 8, 1, dob_ltmp, dob_tmp, dopb_ltmp, dopb_tmp);
end if;
if ((web_tmp(2) = '1' and wea_tmp(2) = '1') or (seq = "01" and wea_tmp(2) = '1' and web_tmp(2) = '0' and viol_type_tmp = "11") or (seq = "01" and WRITE_MODE_B /= "READ_FIRST" and WRITE_MODE_A /= "READ_FIRST") or (seq = "01" and WRITE_MODE_B = "READ_FIRST" and WRITE_MODE_A /= "READ_FIRST" and wea_tmp(2) = '1') or (seq = "11" and WRITE_MODE_B = "WRITE_FIRST" and wea_tmp(2) /= '1')) then
dob_ltmp(23 downto 16) := mem(prcd_tmp_addrb_dly_depth)(23 downto 16);
dopb_ltmp(2) := memp(prcd_tmp_addrb_dly_depth)(2);
prcd_x_buf (wr_mode_b_tmp, 23, 16, 2, dob_ltmp, dob_tmp, dopb_ltmp, dopb_tmp);
end if;
if ((web_tmp(3) = '1' and wea_tmp(3) = '1') or (seq = "01" and wea_tmp(3) = '1' and web_tmp(3) = '0' and viol_type_tmp = "11") or (seq = "01" and WRITE_MODE_B /= "READ_FIRST" and WRITE_MODE_A /= "READ_FIRST") or (seq = "01" and WRITE_MODE_B = "READ_FIRST" and WRITE_MODE_A /= "READ_FIRST" and wea_tmp(3) = '1') or (seq = "11" and WRITE_MODE_B = "WRITE_FIRST" and wea_tmp(3) /= '1')) then
dob_ltmp(31 downto 24) := mem(prcd_tmp_addrb_dly_depth)(31 downto 24);
dopb_ltmp(3) := memp(prcd_tmp_addrb_dly_depth)(3);
prcd_x_buf (wr_mode_b_tmp, 31, 24, 3, dob_ltmp, dob_tmp, dopb_ltmp, dopb_tmp);
end if;
end if;
when 64 =>
prcd_tmp_addrb_dly_depth := SLV_TO_INT(addrb_tmp(14 downto 6));
if ((web_tmp(0) = '1' and wea_tmp(0) = '1') or (seq = "01" and wea_tmp(0) = '1' and web_tmp(0) = '0' and viol_type_tmp = "11") or (seq = "01" and WRITE_MODE_B /= "READ_FIRST" and WRITE_MODE_A /= "READ_FIRST") or (seq = "01" and WRITE_MODE_B = "READ_FIRST" and WRITE_MODE_A /= "READ_FIRST" and wea_tmp(0) = '1') or (seq = "11" and WRITE_MODE_B = "WRITE_FIRST" and wea_tmp(0) /= '1')) then
dob_ltmp(7 downto 0) := mem(prcd_tmp_addrb_dly_depth)(7 downto 0);
dopb_ltmp(0) := memp(prcd_tmp_addrb_dly_depth)(0);
prcd_x_buf (wr_mode_b_tmp, 7, 0, 0, dob_ltmp, dob_tmp, dopb_ltmp, dopb_tmp);
end if;
if ((web_tmp(1) = '1' and wea_tmp(1) = '1') or (seq = "01" and wea_tmp(1) = '1' and web_tmp(1) = '0' and viol_type_tmp = "11") or (seq = "01" and WRITE_MODE_B /= "READ_FIRST" and WRITE_MODE_A /= "READ_FIRST") or (seq = "01" and WRITE_MODE_B = "READ_FIRST" and WRITE_MODE_A /= "READ_FIRST" and wea_tmp(1) = '1') or (seq = "11" and WRITE_MODE_B = "WRITE_FIRST" and wea_tmp(1) /= '1')) then
dob_ltmp(15 downto 8) := mem(prcd_tmp_addrb_dly_depth)(15 downto 8);
dopb_ltmp(1) := memp(prcd_tmp_addrb_dly_depth)(1);
prcd_x_buf (wr_mode_b_tmp, 15, 8, 1, dob_ltmp, dob_tmp, dopb_ltmp, dopb_tmp);
end if;
if ((web_tmp(2) = '1' and wea_tmp(2) = '1') or (seq = "01" and wea_tmp(2) = '1' and web_tmp(2) = '0' and viol_type_tmp = "11") or (seq = "01" and WRITE_MODE_B /= "READ_FIRST" and WRITE_MODE_A /= "READ_FIRST") or (seq = "01" and WRITE_MODE_B = "READ_FIRST" and WRITE_MODE_A /= "READ_FIRST" and wea_tmp(2) = '1') or (seq = "11" and WRITE_MODE_B = "WRITE_FIRST" and wea_tmp(2) /= '1')) then
dob_ltmp(23 downto 16) := mem(prcd_tmp_addrb_dly_depth)(23 downto 16);
dopb_ltmp(2) := memp(prcd_tmp_addrb_dly_depth)(2);
prcd_x_buf (wr_mode_b_tmp, 23, 16, 2, dob_ltmp, dob_tmp, dopb_ltmp, dopb_tmp);
end if;
if ((web_tmp(3) = '1' and wea_tmp(3) = '1') or (seq = "01" and wea_tmp(3) = '1' and web_tmp(3) = '0' and viol_type_tmp = "11") or (seq = "01" and WRITE_MODE_B /= "READ_FIRST" and WRITE_MODE_A /= "READ_FIRST") or (seq = "01" and WRITE_MODE_B = "READ_FIRST" and WRITE_MODE_A /= "READ_FIRST" and wea_tmp(3) = '1') or (seq = "11" and WRITE_MODE_B = "WRITE_FIRST" and wea_tmp(3) /= '1')) then
dob_ltmp(31 downto 24) := mem(prcd_tmp_addrb_dly_depth)(31 downto 24);
dopb_ltmp(3) := memp(prcd_tmp_addrb_dly_depth)(3);
prcd_x_buf (wr_mode_b_tmp, 31, 24, 3, dob_ltmp, dob_tmp, dopb_ltmp, dopb_tmp);
end if;
if ((web_tmp(4) = '1' and wea_tmp(4) = '1') or (seq = "01" and wea_tmp(4) = '1' and web_tmp(4) = '0' and viol_type_tmp = "11") or (seq = "01" and WRITE_MODE_B /= "READ_FIRST" and WRITE_MODE_A /= "READ_FIRST") or (seq = "01" and WRITE_MODE_B = "READ_FIRST" and WRITE_MODE_A /= "READ_FIRST" and wea_tmp(4) = '1') or (seq = "11" and WRITE_MODE_B = "WRITE_FIRST" and wea_tmp(4) /= '1')) then
dob_ltmp(39 downto 32) := mem(prcd_tmp_addrb_dly_depth)(39 downto 32);
dopb_ltmp(4) := memp(prcd_tmp_addrb_dly_depth)(4);
prcd_x_buf (wr_mode_b_tmp, 39, 32, 4, dob_ltmp, dob_tmp, dopb_ltmp, dopb_tmp);
end if;
if ((web_tmp(5) = '1' and wea_tmp(5) = '1') or (seq = "01" and wea_tmp(5) = '1' and web_tmp(5) = '0' and viol_type_tmp = "11") or (seq = "01" and WRITE_MODE_B /= "READ_FIRST" and WRITE_MODE_A /= "READ_FIRST") or (seq = "01" and WRITE_MODE_B = "READ_FIRST" and WRITE_MODE_A /= "READ_FIRST" and wea_tmp(5) = '1') or (seq = "11" and WRITE_MODE_B = "WRITE_FIRST" and wea_tmp(5) /= '1')) then
dob_ltmp(47 downto 40) := mem(prcd_tmp_addrb_dly_depth)(47 downto 40);
dopb_ltmp(5) := memp(prcd_tmp_addrb_dly_depth)(5);
prcd_x_buf (wr_mode_b_tmp, 47, 40, 5, dob_ltmp, dob_tmp, dopb_ltmp, dopb_tmp);
end if;
if ((web_tmp(6) = '1' and wea_tmp(6) = '1') or (seq = "01" and wea_tmp(6) = '1' and web_tmp(6) = '0' and viol_type_tmp = "11") or (seq = "01" and WRITE_MODE_B /= "READ_FIRST" and WRITE_MODE_A /= "READ_FIRST") or (seq = "01" and WRITE_MODE_B = "READ_FIRST" and WRITE_MODE_A /= "READ_FIRST" and wea_tmp(6) = '1') or (seq = "11" and WRITE_MODE_B = "WRITE_FIRST" and wea_tmp(6) /= '1')) then
dob_ltmp(55 downto 48) := mem(prcd_tmp_addrb_dly_depth)(55 downto 48);
dopb_ltmp(6) := memp(prcd_tmp_addrb_dly_depth)(6);
prcd_x_buf (wr_mode_b_tmp, 55, 48, 6, dob_ltmp, dob_tmp, dopb_ltmp, dopb_tmp);
end if;
if ((web_tmp(7) = '1' and wea_tmp(7) = '1') or (seq = "01" and wea_tmp(7) = '1' and web_tmp(7) = '0' and viol_type_tmp = "11") or (seq = "01" and WRITE_MODE_B /= "READ_FIRST" and WRITE_MODE_A /= "READ_FIRST") or (seq = "01" and WRITE_MODE_B = "READ_FIRST" and WRITE_MODE_A /= "READ_FIRST" and wea_tmp(7) = '1') or (seq = "11" and WRITE_MODE_B = "WRITE_FIRST" and wea_tmp(7) /= '1')) then
dob_ltmp(63 downto 56) := mem(prcd_tmp_addrb_dly_depth)(63 downto 56);
dopb_ltmp(7) := memp(prcd_tmp_addrb_dly_depth)(7);
prcd_x_buf (wr_mode_b_tmp, 63, 56, 7, dob_ltmp, dob_tmp, dopb_ltmp, dopb_tmp);
end if;
when others => null;
end case;
end prcd_col_rd_ram_b;
procedure prcd_wr_ram_a (
constant wea_tmp : in std_logic_vector (7 downto 0);
constant dia_tmp : in std_logic_vector (63 downto 0);
constant dipa_tmp : in std_logic_vector (7 downto 0);
constant addra_tmp : in std_logic_vector (15 downto 0);
variable mem : inout Two_D_array_type;
variable memp : inout Two_D_parity_array_type;
constant syndrome_tmp : in std_logic_vector (7 downto 0)
) is
variable prcd_tmp_addra_dly_depth : integer;
variable prcd_tmp_addra_dly_width : integer;
variable junk : std_ulogic;
begin
case wa_width is
when 1 | 2 | 4 =>
if (wa_width >= width) then
prcd_tmp_addra_dly_depth := SLV_TO_INT(addra_tmp(14 downto w_addra_lbit_124));
prcd_write_ram (wea_tmp(0), dia_tmp(wa_width-1 downto 0), '0', mem(prcd_tmp_addra_dly_depth), junk);
else
prcd_tmp_addra_dly_depth := SLV_TO_INT(addra_tmp(14 downto w_addra_bit_124 + 1));
prcd_tmp_addra_dly_width := SLV_TO_INT(addra_tmp(w_addra_bit_124 downto w_addra_lbit_124));
prcd_write_ram (wea_tmp(0), dia_tmp(wa_width-1 downto 0), '0', mem(prcd_tmp_addra_dly_depth)((prcd_tmp_addra_dly_width * wa_width) + wa_width - 1 downto (prcd_tmp_addra_dly_width * wa_width)), junk);
end if;
when 8 =>
if (wa_width >= width) then
prcd_tmp_addra_dly_depth := SLV_TO_INT(addra_tmp(14 downto 3));
prcd_write_ram (wea_tmp(0), dia_tmp(7 downto 0), dipa_tmp(0), mem(prcd_tmp_addra_dly_depth), memp(prcd_tmp_addra_dly_depth)(0));
else
prcd_tmp_addra_dly_depth := SLV_TO_INT(addra_tmp(14 downto w_addra_bit_8 + 1));
prcd_tmp_addra_dly_width := SLV_TO_INT(addra_tmp(w_addra_bit_8 downto 3));
prcd_write_ram (wea_tmp(0), dia_tmp(7 downto 0), dipa_tmp(0), mem(prcd_tmp_addra_dly_depth)((prcd_tmp_addra_dly_width * 8) + 7 downto (prcd_tmp_addra_dly_width * 8)), memp(prcd_tmp_addra_dly_depth)((prcd_tmp_addra_dly_width)));
end if;
when 16 =>
if (wa_width >= width) then
prcd_tmp_addra_dly_depth := SLV_TO_INT(addra_tmp(14 downto 4));
prcd_write_ram (wea_tmp(0), dia_tmp(7 downto 0), dipa_tmp(0), mem(prcd_tmp_addra_dly_depth)(7 downto 0), memp(prcd_tmp_addra_dly_depth)(0));
prcd_write_ram (wea_tmp(1), dia_tmp(15 downto 8), dipa_tmp(1), mem(prcd_tmp_addra_dly_depth)(15 downto 8), memp(prcd_tmp_addra_dly_depth)(1));
else
prcd_tmp_addra_dly_depth := SLV_TO_INT(addra_tmp(14 downto w_addra_bit_16 + 1));
prcd_tmp_addra_dly_width := SLV_TO_INT(addra_tmp(w_addra_bit_16 downto 4));
prcd_write_ram (wea_tmp(0), dia_tmp(7 downto 0), dipa_tmp(0), mem(prcd_tmp_addra_dly_depth)((prcd_tmp_addra_dly_width * 16) + 7 downto (prcd_tmp_addra_dly_width * 16)), memp(prcd_tmp_addra_dly_depth)((prcd_tmp_addra_dly_width * 2)));
prcd_write_ram (wea_tmp(1), dia_tmp(15 downto 8), dipa_tmp(1), mem(prcd_tmp_addra_dly_depth)((prcd_tmp_addra_dly_width * 16) + 15 downto (prcd_tmp_addra_dly_width * 16) + 8), memp(prcd_tmp_addra_dly_depth)((prcd_tmp_addra_dly_width * 2) + 1));
end if;
when 32 =>
prcd_tmp_addra_dly_depth := SLV_TO_INT(addra_tmp(14 downto 5));
prcd_write_ram (wea_tmp(0), dia_tmp(7 downto 0), dipa_tmp(0), mem(prcd_tmp_addra_dly_depth)(7 downto 0), memp(prcd_tmp_addra_dly_depth)(0));
prcd_write_ram (wea_tmp(1), dia_tmp(15 downto 8), dipa_tmp(1), mem(prcd_tmp_addra_dly_depth)(15 downto 8), memp(prcd_tmp_addra_dly_depth)(1));
prcd_write_ram (wea_tmp(2), dia_tmp(23 downto 16), dipa_tmp(2), mem(prcd_tmp_addra_dly_depth)(23 downto 16), memp(prcd_tmp_addra_dly_depth)(2));
prcd_write_ram (wea_tmp(3), dia_tmp(31 downto 24), dipa_tmp(3), mem(prcd_tmp_addra_dly_depth)(31 downto 24), memp(prcd_tmp_addra_dly_depth)(3));
when 64 => if (syndrome_tmp /= "00000000" and syndrome_tmp(7) = '1' and EN_ECC_SCRUB = TRUE) then
prcd_tmp_addra_dly_depth := SLV_TO_INT(addra_tmp(14 downto 6));
prcd_write_ram ('1', dia_tmp(7 downto 0), dipa_tmp(0), mem(prcd_tmp_addra_dly_depth)(7 downto 0), memp(prcd_tmp_addra_dly_depth)(0));
prcd_write_ram ('1', dia_tmp(15 downto 8), dipa_tmp(1), mem(prcd_tmp_addra_dly_depth)(15 downto 8), memp(prcd_tmp_addra_dly_depth)(1));
prcd_write_ram ('1', dia_tmp(23 downto 16), dipa_tmp(2), mem(prcd_tmp_addra_dly_depth)(23 downto 16), memp(prcd_tmp_addra_dly_depth)(2));
prcd_write_ram ('1', dia_tmp(31 downto 24), dipa_tmp(3), mem(prcd_tmp_addra_dly_depth)(31 downto 24), memp(prcd_tmp_addra_dly_depth)(3));
prcd_write_ram ('1', dia_tmp(39 downto 32), dipa_tmp(4), mem(prcd_tmp_addra_dly_depth)(39 downto 32), memp(prcd_tmp_addra_dly_depth)(4));
prcd_write_ram ('1', dia_tmp(47 downto 40), dipa_tmp(5), mem(prcd_tmp_addra_dly_depth)(47 downto 40), memp(prcd_tmp_addra_dly_depth)(5));
prcd_write_ram ('1', dia_tmp(55 downto 48), dipa_tmp(6), mem(prcd_tmp_addra_dly_depth)(55 downto 48), memp(prcd_tmp_addra_dly_depth)(6));
prcd_write_ram ('1', dia_tmp(63 downto 56), dipa_tmp(7), mem(prcd_tmp_addra_dly_depth)(63 downto 56), memp(prcd_tmp_addra_dly_depth)(7));
end if;
when others => null;
end case;
end prcd_wr_ram_a;
procedure prcd_wr_ram_b (
constant web_tmp : in std_logic_vector (7 downto 0);
constant dib_tmp : in std_logic_vector (63 downto 0);
constant dipb_tmp : in std_logic_vector (7 downto 0);
constant addrb_tmp : in std_logic_vector (15 downto 0);
variable mem : inout Two_D_array_type;
variable memp : inout Two_D_parity_array_type
) is
variable prcd_tmp_addrb_dly_depth : integer;
variable prcd_tmp_addrb_dly_width : integer;
variable junk : std_ulogic;
begin
case wb_width is
when 1 | 2 | 4 =>
if (wb_width >= width) then
prcd_tmp_addrb_dly_depth := SLV_TO_INT(addrb_tmp(14 downto w_addrb_lbit_124));
prcd_write_ram (web_tmp(0), dib_tmp(wb_width-1 downto 0), '0', mem(prcd_tmp_addrb_dly_depth), junk);
else
prcd_tmp_addrb_dly_depth := SLV_TO_INT(addrb_tmp(14 downto w_addrb_bit_124 + 1));
prcd_tmp_addrb_dly_width := SLV_TO_INT(addrb_tmp(w_addrb_bit_124 downto w_addrb_lbit_124));
prcd_write_ram (web_tmp(0), dib_tmp(wb_width-1 downto 0), '0', mem(prcd_tmp_addrb_dly_depth)((prcd_tmp_addrb_dly_width * wb_width) + wb_width - 1 downto (prcd_tmp_addrb_dly_width * wb_width)), junk);
end if;
when 8 =>
if (wb_width >= width) then
prcd_tmp_addrb_dly_depth := SLV_TO_INT(addrb_tmp(14 downto 3));
prcd_write_ram (web_tmp(0), dib_tmp(7 downto 0), dipb_tmp(0), mem(prcd_tmp_addrb_dly_depth), memp(prcd_tmp_addrb_dly_depth)(0));
else
prcd_tmp_addrb_dly_depth := SLV_TO_INT(addrb_tmp(14 downto w_addrb_bit_8 + 1));
prcd_tmp_addrb_dly_width := SLV_TO_INT(addrb_tmp(w_addrb_bit_8 downto 3));
prcd_write_ram (web_tmp(0), dib_tmp(7 downto 0), dipb_tmp(0), mem(prcd_tmp_addrb_dly_depth)((prcd_tmp_addrb_dly_width * 8) + 7 downto (prcd_tmp_addrb_dly_width * 8)), memp(prcd_tmp_addrb_dly_depth)((prcd_tmp_addrb_dly_width)));
end if;
when 16 =>
if (wb_width >= width) then
prcd_tmp_addrb_dly_depth := SLV_TO_INT(addrb_tmp(14 downto 4));
prcd_write_ram (web_tmp(0), dib_tmp(7 downto 0), dipb_tmp(0), mem(prcd_tmp_addrb_dly_depth)(7 downto 0), memp(prcd_tmp_addrb_dly_depth)(0));
prcd_write_ram (web_tmp(1), dib_tmp(15 downto 8), dipb_tmp(1), mem(prcd_tmp_addrb_dly_depth)(15 downto 8), memp(prcd_tmp_addrb_dly_depth)(1));
else
prcd_tmp_addrb_dly_depth := SLV_TO_INT(addrb_tmp(14 downto w_addrb_bit_16 + 1));
prcd_tmp_addrb_dly_width := SLV_TO_INT(addrb_tmp(w_addrb_bit_16 downto 4));
prcd_write_ram (web_tmp(0), dib_tmp(7 downto 0), dipb_tmp(0), mem(prcd_tmp_addrb_dly_depth)((prcd_tmp_addrb_dly_width * 16) + 7 downto (prcd_tmp_addrb_dly_width * 16)), memp(prcd_tmp_addrb_dly_depth)((prcd_tmp_addrb_dly_width * 2)));
prcd_write_ram (web_tmp(1), dib_tmp(15 downto 8), dipb_tmp(1), mem(prcd_tmp_addrb_dly_depth)((prcd_tmp_addrb_dly_width * 16) + 15 downto (prcd_tmp_addrb_dly_width * 16) + 8), memp(prcd_tmp_addrb_dly_depth)((prcd_tmp_addrb_dly_width * 2) + 1));
end if;
when 32 =>
prcd_tmp_addrb_dly_depth := SLV_TO_INT(addrb_tmp(14 downto 5));
prcd_write_ram (web_tmp(0), dib_tmp(7 downto 0), dipb_tmp(0), mem(prcd_tmp_addrb_dly_depth)(7 downto 0), memp(prcd_tmp_addrb_dly_depth)(0));
prcd_write_ram (web_tmp(1), dib_tmp(15 downto 8), dipb_tmp(1), mem(prcd_tmp_addrb_dly_depth)(15 downto 8), memp(prcd_tmp_addrb_dly_depth)(1));
prcd_write_ram (web_tmp(2), dib_tmp(23 downto 16), dipb_tmp(2), mem(prcd_tmp_addrb_dly_depth)(23 downto 16), memp(prcd_tmp_addrb_dly_depth)(2));
prcd_write_ram (web_tmp(3), dib_tmp(31 downto 24), dipb_tmp(3), mem(prcd_tmp_addrb_dly_depth)(31 downto 24), memp(prcd_tmp_addrb_dly_depth)(3));
when 64 =>
prcd_tmp_addrb_dly_depth := SLV_TO_INT(addrb_tmp(14 downto 6));
prcd_write_ram (web_tmp(0), dib_tmp(7 downto 0), dipb_tmp(0), mem(prcd_tmp_addrb_dly_depth)(7 downto 0), memp(prcd_tmp_addrb_dly_depth)(0));
prcd_write_ram (web_tmp(1), dib_tmp(15 downto 8), dipb_tmp(1), mem(prcd_tmp_addrb_dly_depth)(15 downto 8), memp(prcd_tmp_addrb_dly_depth)(1));
prcd_write_ram (web_tmp(2), dib_tmp(23 downto 16), dipb_tmp(2), mem(prcd_tmp_addrb_dly_depth)(23 downto 16), memp(prcd_tmp_addrb_dly_depth)(2));
prcd_write_ram (web_tmp(3), dib_tmp(31 downto 24), dipb_tmp(3), mem(prcd_tmp_addrb_dly_depth)(31 downto 24), memp(prcd_tmp_addrb_dly_depth)(3));
prcd_write_ram (web_tmp(4), dib_tmp(39 downto 32), dipb_tmp(4), mem(prcd_tmp_addrb_dly_depth)(39 downto 32), memp(prcd_tmp_addrb_dly_depth)(4));
prcd_write_ram (web_tmp(5), dib_tmp(47 downto 40), dipb_tmp(5), mem(prcd_tmp_addrb_dly_depth)(47 downto 40), memp(prcd_tmp_addrb_dly_depth)(5));
prcd_write_ram (web_tmp(6), dib_tmp(55 downto 48), dipb_tmp(6), mem(prcd_tmp_addrb_dly_depth)(55 downto 48), memp(prcd_tmp_addrb_dly_depth)(6));
prcd_write_ram (web_tmp(7), dib_tmp(63 downto 56), dipb_tmp(7), mem(prcd_tmp_addrb_dly_depth)(63 downto 56), memp(prcd_tmp_addrb_dly_depth)(7));
when others => null;
end case;
end prcd_wr_ram_b;
procedure prcd_col_ecc_read (
variable do_tmp : inout std_logic_vector (63 downto 0);
variable dop_tmp : inout std_logic_vector (7 downto 0);
constant addr_tmp : in std_logic_vector (15 downto 0);
variable dbiterr_tmp : inout std_logic;
variable sbiterr_tmp : inout std_logic;
variable mem : inout Two_D_array_type;
variable memp : inout Two_D_parity_array_type;
variable prcd_syndrome : inout std_logic_vector (7 downto 0)
) is
variable prcd_ecc_bit_position : std_logic_vector (71 downto 0);
variable prcd_dopr_ecc : std_logic_vector (7 downto 0);
variable prcd_di_dly_ecc_corrected : std_logic_vector (63 downto 0);
variable prcd_dip_dly_ecc_corrected : std_logic_vector (7 downto 0);
variable prcd_tmp_syndrome_int : integer := 0;
begin
prcd_dopr_ecc := fn_dip_ecc('0', do_tmp, dop_tmp);
prcd_syndrome := prcd_dopr_ecc xor dop_tmp;
if (prcd_syndrome /= "00000000") then
if (prcd_syndrome(7) = '1') then -- dectect single bit error
prcd_ecc_bit_position := do_tmp(63 downto 57) & dop_tmp(6) & do_tmp(56 downto 26) & dop_tmp(5) & do_tmp(25 downto 11) & dop_tmp(4) & do_tmp(10 downto 4) & dop_tmp(3) & do_tmp(3 downto 1) & dop_tmp(2) & do_tmp(0) & dop_tmp(1 downto 0) & dop_tmp(7);
prcd_tmp_syndrome_int := SLV_TO_INT(prcd_syndrome(6 downto 0));
prcd_ecc_bit_position(prcd_tmp_syndrome_int) := not prcd_ecc_bit_position(prcd_tmp_syndrome_int); -- correct single bit error in the output
prcd_di_dly_ecc_corrected := prcd_ecc_bit_position(71 downto 65) & prcd_ecc_bit_position(63 downto 33) & prcd_ecc_bit_position(31 downto 17) & prcd_ecc_bit_position(15 downto 9) & prcd_ecc_bit_position(7 downto 5) & prcd_ecc_bit_position(3); -- correct single bit error in the memory
do_tmp := prcd_di_dly_ecc_corrected;
prcd_dip_dly_ecc_corrected := prcd_ecc_bit_position(0) & prcd_ecc_bit_position(64) & prcd_ecc_bit_position(32) & prcd_ecc_bit_position(16) & prcd_ecc_bit_position(8) & prcd_ecc_bit_position(4) & prcd_ecc_bit_position(2 downto 1); -- correct single bit error in the parity memory
dop_tmp := prcd_dip_dly_ecc_corrected;
dbiterr_tmp := '0';
sbiterr_tmp := '1';
elsif (prcd_syndrome(7) = '0') then -- double bit error
sbiterr_tmp := '0';
dbiterr_tmp := '1';
end if;
else
dbiterr_tmp := '0';
sbiterr_tmp := '0';
end if;
if (ssra_dly = '1') then -- ssra reset
dbiterr_tmp := '0';
sbiterr_tmp := '0';
end if;
if (prcd_syndrome /= "00000000" and prcd_syndrome(7) = '1' and EN_ECC_SCRUB = TRUE) then
prcd_wr_ram_a ("11111111", prcd_di_dly_ecc_corrected, prcd_dip_dly_ecc_corrected, addr_tmp, mem, memp, prcd_syndrome);
end if;
end prcd_col_ecc_read;
begin
---------------------
-- INPUT PATH DELAYs
--------------------
addra_dly <= ADDRA after 0 ps;
addrb_dly <= ADDRB after 0 ps;
cascadeinlata_dly <= CASCADEINLATA after 0 ps;
cascadeinlatb_dly <= CASCADEINLATB after 0 ps;
cascadeinrega_dly <= CASCADEINREGA after 0 ps;
cascadeinregb_dly <= CASCADEINREGB after 0 ps;
clka_dly <= CLKA after 0 ps;
clkb_dly <= CLKB after 0 ps;
dia_dly <= DIA after 0 ps;
dib_dly <= DIB after 0 ps;
dipa_dly <= DIPA after 0 ps;
dipb_dly <= DIPB after 0 ps;
ena_dly <= ENA after 0 ps;
enb_dly <= ENB after 0 ps;
regcea_dly <= REGCEA after 0 ps;
regceb_dly <= REGCEB after 0 ps;
ssra_dly <= SSRA after 0 ps;
ssrb_dly <= SSRB after 0 ps;
wea_dly <= WEA after 0 ps;
web_dly <= WEB after 0 ps;
gsr_dly <= GSR after 0 ps;
regclka_dly <= REGCLKA after 0 ps;
regclkb_dly <= REGCLKB after 0 ps;
--------------------
-- BEHAVIOR SECTION
--------------------
prcs_clk: process (clka_dly, clkb_dly, gsr_dly)
variable mem_slv : std_logic_vector(32767 downto 0) := To_StdLogicVector(INIT_7F) &
To_StdLogicVector(INIT_7E) &
To_StdLogicVector(INIT_7D) &
To_StdLogicVector(INIT_7C) &
To_StdLogicVector(INIT_7B) &
To_StdLogicVector(INIT_7A) &
To_StdLogicVector(INIT_79) &
To_StdLogicVector(INIT_78) &
To_StdLogicVector(INIT_77) &
To_StdLogicVector(INIT_76) &
To_StdLogicVector(INIT_75) &
To_StdLogicVector(INIT_74) &
To_StdLogicVector(INIT_73) &
To_StdLogicVector(INIT_72) &
To_StdLogicVector(INIT_71) &
To_StdLogicVector(INIT_70) &
To_StdLogicVector(INIT_6F) &
To_StdLogicVector(INIT_6E) &
To_StdLogicVector(INIT_6D) &
To_StdLogicVector(INIT_6C) &
To_StdLogicVector(INIT_6B) &
To_StdLogicVector(INIT_6A) &
To_StdLogicVector(INIT_69) &
To_StdLogicVector(INIT_68) &
To_StdLogicVector(INIT_67) &
To_StdLogicVector(INIT_66) &
To_StdLogicVector(INIT_65) &
To_StdLogicVector(INIT_64) &
To_StdLogicVector(INIT_63) &
To_StdLogicVector(INIT_62) &
To_StdLogicVector(INIT_61) &
To_StdLogicVector(INIT_60) &
To_StdLogicVector(INIT_5F) &
To_StdLogicVector(INIT_5E) &
To_StdLogicVector(INIT_5D) &
To_StdLogicVector(INIT_5C) &
To_StdLogicVector(INIT_5B) &
To_StdLogicVector(INIT_5A) &
To_StdLogicVector(INIT_59) &
To_StdLogicVector(INIT_58) &
To_StdLogicVector(INIT_57) &
To_StdLogicVector(INIT_56) &
To_StdLogicVector(INIT_55) &
To_StdLogicVector(INIT_54) &
To_StdLogicVector(INIT_53) &
To_StdLogicVector(INIT_52) &
To_StdLogicVector(INIT_51) &
To_StdLogicVector(INIT_50) &
To_StdLogicVector(INIT_4F) &
To_StdLogicVector(INIT_4E) &
To_StdLogicVector(INIT_4D) &
To_StdLogicVector(INIT_4C) &
To_StdLogicVector(INIT_4B) &
To_StdLogicVector(INIT_4A) &
To_StdLogicVector(INIT_49) &
To_StdLogicVector(INIT_48) &
To_StdLogicVector(INIT_47) &
To_StdLogicVector(INIT_46) &
To_StdLogicVector(INIT_45) &
To_StdLogicVector(INIT_44) &
To_StdLogicVector(INIT_43) &
To_StdLogicVector(INIT_42) &
To_StdLogicVector(INIT_41) &
To_StdLogicVector(INIT_40) &
To_StdLogicVector(INIT_3F) &
To_StdLogicVector(INIT_3E) &
To_StdLogicVector(INIT_3D) &
To_StdLogicVector(INIT_3C) &
To_StdLogicVector(INIT_3B) &
To_StdLogicVector(INIT_3A) &
To_StdLogicVector(INIT_39) &
To_StdLogicVector(INIT_38) &
To_StdLogicVector(INIT_37) &
To_StdLogicVector(INIT_36) &
To_StdLogicVector(INIT_35) &
To_StdLogicVector(INIT_34) &
To_StdLogicVector(INIT_33) &
To_StdLogicVector(INIT_32) &
To_StdLogicVector(INIT_31) &
To_StdLogicVector(INIT_30) &
To_StdLogicVector(INIT_2F) &
To_StdLogicVector(INIT_2E) &
To_StdLogicVector(INIT_2D) &
To_StdLogicVector(INIT_2C) &
To_StdLogicVector(INIT_2B) &
To_StdLogicVector(INIT_2A) &
To_StdLogicVector(INIT_29) &
To_StdLogicVector(INIT_28) &
To_StdLogicVector(INIT_27) &
To_StdLogicVector(INIT_26) &
To_StdLogicVector(INIT_25) &
To_StdLogicVector(INIT_24) &
To_StdLogicVector(INIT_23) &
To_StdLogicVector(INIT_22) &
To_StdLogicVector(INIT_21) &
To_StdLogicVector(INIT_20) &
To_StdLogicVector(INIT_1F) &
To_StdLogicVector(INIT_1E) &
To_StdLogicVector(INIT_1D) &
To_StdLogicVector(INIT_1C) &
To_StdLogicVector(INIT_1B) &
To_StdLogicVector(INIT_1A) &
To_StdLogicVector(INIT_19) &
To_StdLogicVector(INIT_18) &
To_StdLogicVector(INIT_17) &
To_StdLogicVector(INIT_16) &
To_StdLogicVector(INIT_15) &
To_StdLogicVector(INIT_14) &
To_StdLogicVector(INIT_13) &
To_StdLogicVector(INIT_12) &
To_StdLogicVector(INIT_11) &
To_StdLogicVector(INIT_10) &
To_StdLogicVector(INIT_0F) &
To_StdLogicVector(INIT_0E) &
To_StdLogicVector(INIT_0D) &
To_StdLogicVector(INIT_0C) &
To_StdLogicVector(INIT_0B) &
To_StdLogicVector(INIT_0A) &
To_StdLogicVector(INIT_09) &
To_StdLogicVector(INIT_08) &
To_StdLogicVector(INIT_07) &
To_StdLogicVector(INIT_06) &
To_StdLogicVector(INIT_05) &
To_StdLogicVector(INIT_04) &
To_StdLogicVector(INIT_03) &
To_StdLogicVector(INIT_02) &
To_StdLogicVector(INIT_01) &
To_StdLogicVector(INIT_00);
variable memp_slv : std_logic_vector(4095 downto 0) := To_StdLogicVector(INITP_0F) &
To_StdLogicVector(INITP_0E) &
To_StdLogicVector(INITP_0D) &
To_StdLogicVector(INITP_0C) &
To_StdLogicVector(INITP_0B) &
To_StdLogicVector(INITP_0A) &
To_StdLogicVector(INITP_09) &
To_StdLogicVector(INITP_08) &
To_StdLogicVector(INITP_07) &
To_StdLogicVector(INITP_06) &
To_StdLogicVector(INITP_05) &
To_StdLogicVector(INITP_04) &
To_StdLogicVector(INITP_03) &
To_StdLogicVector(INITP_02) &
To_StdLogicVector(INITP_01) &
To_StdLogicVector(INITP_00);
variable mem : Two_D_array_type := slv_to_two_D_array(mem_depth, width, mem_slv);
variable memp : Two_D_parity_array_type := slv_to_two_D_parity_array(memp_depth, widthp, memp_slv);
variable tmp_addra_dly_depth : integer;
variable tmp_addra_dly_width : integer;
variable tmp_addrb_dly_depth : integer;
variable tmp_addrb_dly_width : integer;
variable junk1 : std_logic;
variable wr_mode_a : std_logic_vector(1 downto 0) := "00";
variable wr_mode_b : std_logic_vector(1 downto 0) := "00";
variable tmp_syndrome_int : integer;
variable doa_buf : std_logic_vector(63 downto 0) := (others => '0');
variable dob_buf : std_logic_vector(63 downto 0) := (others => '0');
variable dopa_buf : std_logic_vector(7 downto 0) := (others => '0');
variable dopb_buf : std_logic_vector(7 downto 0) := (others => '0');
variable syndrome : std_logic_vector(7 downto 0) := (others => '0');
variable dopr_ecc : std_logic_vector(7 downto 0) := (others => '0');
variable dia_dly_ecc_corrected : std_logic_vector(63 downto 0) := (others => '0');
variable dipa_dly_ecc_corrected : std_logic_vector(7 downto 0) := (others => '0');
variable dip_ecc : std_logic_vector(7 downto 0) := (others => '0');
variable dipb_dly_ecc : std_logic_vector(7 downto 0) := (others => '0');
variable ecc_bit_position : std_logic_vector(71 downto 0) := (others => '0');
variable addra_dly_15_reg_var : std_logic := '0';
variable addrb_dly_15_reg_var : std_logic := '0';
variable addra_dly_15_reg_bram_var : std_logic := '0';
variable addrb_dly_15_reg_bram_var : std_logic := '0';
variable FIRST_TIME : boolean := true;
variable curr_time : time := 0 ps;
variable prev_time : time := 0 ps;
variable viol_time : integer := 0;
variable viol_type : std_logic_vector(1 downto 0) := (others => '0');
variable message : line;
variable dip_ecc_col : std_logic_vector (7 downto 0) := (others => '0');
variable dbiterr_out_var : std_ulogic := '0';
variable sbiterr_out_var : std_ulogic := '0';
variable dia_reg_dly : std_logic_vector(63 downto 0) := (others => '0');
variable dipa_reg_dly : std_logic_vector(7 downto 0) := (others => '0');
variable wea_reg_dly : std_logic_vector(7 downto 0) := (others => '0');
variable addra_reg_dly : std_logic_vector(15 downto 0) := (others => '0');
variable dib_reg_dly : std_logic_vector(63 downto 0) := (others => '0');
variable dipb_reg_dly : std_logic_vector(7 downto 0) := (others => '0');
variable web_reg_dly : std_logic_vector(7 downto 0) := (others => '0');
variable addrb_reg_dly : std_logic_vector(15 downto 0) := (others => '0');
variable col_wr_wr_msg : std_ulogic := '1';
variable col_wra_rdb_msg : std_ulogic := '1';
variable col_wrb_rda_msg : std_ulogic := '1';
begin -- process prcs_clka
if (FIRST_TIME) then
case READ_WIDTH_A is
when 0 | 1 | 2 | 4 | 9 | 18 => null;
when 36 => if (BRAM_SIZE = 18 and BRAM_MODE = "TRUE_DUAL_PORT") then
GenericValueCheckMessage
( HeaderMsg => " Attribute Syntax Error : ",
GenericName => " READ_WIDTH_A ",
EntityName => "/ARAMB36_INTERNAL",
GenericValue => READ_WIDTH_A,
Unit => "",
ExpectedValueMsg => " The Legal values for this attribute are ",
ExpectedGenericValue => " 0, 1, 2, 4, 9 or 18.",
TailMsg => "",
MsgSeverity => failure
);
end if;
when 72 => if (BRAM_SIZE = 18) then
GenericValueCheckMessage
( HeaderMsg => " Attribute Syntax Error : ",
GenericName => " READ_WIDTH_A ",
EntityName => "/ARAMB36_INTERNAL",
GenericValue => READ_WIDTH_A,
Unit => "",
ExpectedValueMsg => " The Legal values for this attribute are ",
ExpectedGenericValue => " 0, 1, 2, 4, 9 or 18.",
TailMsg => "",
MsgSeverity => failure
);
elsif ((BRAM_SIZE = 16 or BRAM_SIZE = 36) and BRAM_MODE = "TRUE_DUAL_PORT") then
GenericValueCheckMessage
( HeaderMsg => " Attribute Syntax Error : ",
GenericName => " READ_WIDTH_A ",
EntityName => "/ARAMB36_INTERNAL",
GenericValue => READ_WIDTH_A,
Unit => "",
ExpectedValueMsg => " The Legal values for this attribute are ",
ExpectedGenericValue => " 0, 1, 2, 4, 9, 18 or 36.",
TailMsg => "",
MsgSeverity => failure
);
end if;
when others => if (BRAM_SIZE = 18) then
GenericValueCheckMessage
( HeaderMsg => " Attribute Syntax Error : ",
GenericName => " READ_WIDTH_A ",
EntityName => "/ARAMB36_INTERNAL",
GenericValue => READ_WIDTH_A,
Unit => "",
ExpectedValueMsg => " The Legal values for this attribute are ",
ExpectedGenericValue => " 0, 1, 2, 4, 9 or 18.",
TailMsg => "",
MsgSeverity => failure
);
elsif (BRAM_SIZE = 16 or BRAM_SIZE = 36) then
GenericValueCheckMessage
( HeaderMsg => " Attribute Syntax Error : ",
GenericName => " READ_WIDTH_A ",
EntityName => "/ARAMB36_INTERNAL",
GenericValue => READ_WIDTH_A,
Unit => "",
ExpectedValueMsg => " The Legal values for this attribute are ",
ExpectedGenericValue => " 0, 1, 2, 4, 9, 18 or 36.",
TailMsg => "",
MsgSeverity => failure
);
end if;
end case;
case READ_WIDTH_B is
when 0 | 1 | 2 | 4 | 9 | 18 => null;
when 36 => if (BRAM_SIZE = 18 and BRAM_MODE = "TRUE_DUAL_PORT") then
GenericValueCheckMessage
( HeaderMsg => " Attribute Syntax Error : ",
GenericName => " READ_WIDTH_B ",
EntityName => "/ARAMB36_INTERNAL",
GenericValue => READ_WIDTH_B,
Unit => "",
ExpectedValueMsg => " The Legal values for this attribute are ",
ExpectedGenericValue => " 0, 1, 2, 4, 9 or 18.",
TailMsg => "",
MsgSeverity => failure
);
end if;
when 72 => if (BRAM_SIZE = 18) then
GenericValueCheckMessage
( HeaderMsg => " Attribute Syntax Error : ",
GenericName => " READ_WIDTH_B ",
EntityName => "/ARAMB36_INTERNAL",
GenericValue => READ_WIDTH_B,
Unit => "",
ExpectedValueMsg => " The Legal values for this attribute are ",
ExpectedGenericValue => " 0, 1, 2, 4, 9 or 18.",
TailMsg => "",
MsgSeverity => failure
);
elsif ((BRAM_SIZE = 16 or BRAM_SIZE = 36) and BRAM_MODE = "TRUE_DUAL_PORT") then
GenericValueCheckMessage
( HeaderMsg => " Attribute Syntax Error : ",
GenericName => " READ_WIDTH_B ",
EntityName => "/ARAMB36_INTERNAL",
GenericValue => READ_WIDTH_B,
Unit => "",
ExpectedValueMsg => " The Legal values for this attribute are ",
ExpectedGenericValue => " 0, 1, 2, 4, 9, 18 or 36.",
TailMsg => "",
MsgSeverity => failure
);
end if;
when others => if (BRAM_SIZE = 18) then
GenericValueCheckMessage
( HeaderMsg => " Attribute Syntax Error : ",
GenericName => " READ_WIDTH_B ",
EntityName => "/ARAMB36_INTERNAL",
GenericValue => READ_WIDTH_B,
Unit => "",
ExpectedValueMsg => " The Legal values for this attribute are ",
ExpectedGenericValue => " 0, 1, 2, 4, 9 or 18.",
TailMsg => "",
MsgSeverity => failure
);
elsif (BRAM_SIZE = 16 or BRAM_SIZE = 36) then
GenericValueCheckMessage
( HeaderMsg => " Attribute Syntax Error : ",
GenericName => " READ_WIDTH_B ",
EntityName => "/ARAMB36_INTERNAL",
GenericValue => READ_WIDTH_B,
Unit => "",
ExpectedValueMsg => " The Legal values for this attribute are ",
ExpectedGenericValue => " 0, 1, 2, 4, 9, 18 or 36.",
TailMsg => "",
MsgSeverity => failure
);
end if;
end case;
case WRITE_WIDTH_A is
when 0 | 1 | 2 | 4 | 9 | 18 => null;
when 36 => if (BRAM_SIZE = 18 and BRAM_MODE = "TRUE_DUAL_PORT") then
GenericValueCheckMessage
( HeaderMsg => " Attribute Syntax Error : ",
GenericName => " WRITE_WIDTH_A ",
EntityName => "/ARAMB36_INTERNAL",
GenericValue => WRITE_WIDTH_A,
Unit => "",
ExpectedValueMsg => " The Legal values for this attribute are ",
ExpectedGenericValue => " 0, 1, 2, 4, 9 or 18.",
TailMsg => "",
MsgSeverity => failure
);
end if;
when 72 => if (BRAM_SIZE = 18) then
GenericValueCheckMessage
( HeaderMsg => " Attribute Syntax Error : ",
GenericName => " WRITE_WIDTH_A ",
EntityName => "/ARAMB36_INTERNAL",
GenericValue => WRITE_WIDTH_A,
Unit => "",
ExpectedValueMsg => " The Legal values for this attribute are ",
ExpectedGenericValue => " 0, 1, 2, 4, 9 or 18.",
TailMsg => "",
MsgSeverity => failure
);
elsif ((BRAM_SIZE = 16 or BRAM_SIZE = 36) and BRAM_MODE = "TRUE_DUAL_PORT") then
GenericValueCheckMessage
( HeaderMsg => " Attribute Syntax Error : ",
GenericName => " WRITE_WIDTH_A ",
EntityName => "/ARAMB36_INTERNAL",
GenericValue => WRITE_WIDTH_A,
Unit => "",
ExpectedValueMsg => " The Legal values for this attribute are ",
ExpectedGenericValue => " 0, 1, 2, 4, 9, 18 or 36.",
TailMsg => "",
MsgSeverity => failure
);
end if;
when others => if (BRAM_SIZE = 18) then
GenericValueCheckMessage
( HeaderMsg => " Attribute Syntax Error : ",
GenericName => " WRITE_WIDTH_A ",
EntityName => "/ARAMB36_INTERNAL",
GenericValue => WRITE_WIDTH_A,
Unit => "",
ExpectedValueMsg => " The Legal values for this attribute are ",
ExpectedGenericValue => " 0, 1, 2, 4, 9 or 18.",
TailMsg => "",
MsgSeverity => failure
);
elsif (BRAM_SIZE = 16 or BRAM_SIZE = 36) then
GenericValueCheckMessage
( HeaderMsg => " Attribute Syntax Error : ",
GenericName => " WRITE_WIDTH_A ",
EntityName => "/ARAMB36_INTERNAL",
GenericValue => WRITE_WIDTH_A,
Unit => "",
ExpectedValueMsg => " The Legal values for this attribute are ",
ExpectedGenericValue => " 0, 1, 2, 4, 9, 18 or 36.",
TailMsg => "",
MsgSeverity => failure
);
end if;
end case;
case WRITE_WIDTH_B is
when 0 | 1 | 2 | 4 | 9 | 18 => null;
when 36 => if (BRAM_SIZE = 18 and BRAM_MODE = "TRUE_DUAL_PORT") then
GenericValueCheckMessage
( HeaderMsg => " Attribute Syntax Error : ",
GenericName => " WRITE_WIDTH_B ",
EntityName => "/ARAMB36_INTERNAL",
GenericValue => WRITE_WIDTH_B,
Unit => "",
ExpectedValueMsg => " The Legal values for this attribute are ",
ExpectedGenericValue => " 0, 1, 2, 4, 9 or 18.",
TailMsg => "",
MsgSeverity => failure
);
end if;
when 72 => if (BRAM_SIZE = 18) then
GenericValueCheckMessage
( HeaderMsg => " Attribute Syntax Error : ",
GenericName => " WRITE_WIDTH_B ",
EntityName => "/ARAMB36_INTERNAL",
GenericValue => WRITE_WIDTH_B,
Unit => "",
ExpectedValueMsg => " The Legal values for this attribute are ",
ExpectedGenericValue => " 0, 1, 2, 4, 9 or 18.",
TailMsg => "",
MsgSeverity => failure
);
elsif ((BRAM_SIZE = 16 or BRAM_SIZE = 36) and BRAM_MODE = "TRUE_DUAL_PORT") then
GenericValueCheckMessage
( HeaderMsg => " Attribute Syntax Error : ",
GenericName => " WRITE_WIDTH_B ",
EntityName => "/ARAMB36_INTERNAL",
GenericValue => WRITE_WIDTH_B,
Unit => "",
ExpectedValueMsg => " The Legal values for this attribute are ",
ExpectedGenericValue => " 0, 1, 2, 4, 9, 18 or 36.",
TailMsg => "",
MsgSeverity => failure
);
end if;
when others => if (BRAM_SIZE = 18) then
GenericValueCheckMessage
( HeaderMsg => " Attribute Syntax Error : ",
GenericName => " WRITE_WIDTH_B ",
EntityName => "/ARAMB36_INTERNAL",
GenericValue => WRITE_WIDTH_B,
Unit => "",
ExpectedValueMsg => " The Legal values for this attribute are ",
ExpectedGenericValue => " 0, 1, 2, 4, 9 or 18.",
TailMsg => "",
MsgSeverity => failure
);
elsif (BRAM_SIZE = 16 or BRAM_SIZE = 36) then
GenericValueCheckMessage
( HeaderMsg => " Attribute Syntax Error : ",
GenericName => " WRITE_WIDTH_B ",
EntityName => "/ARAMB36_INTERNAL",
GenericValue => WRITE_WIDTH_B,
Unit => "",
ExpectedValueMsg => " The Legal values for this attribute are ",
ExpectedGenericValue => " 0, 1, 2, 4, 9, 18 or 36.",
TailMsg => "",
MsgSeverity => failure
);
end if;
end case;
if (not(EN_ECC_READ = TRUE or EN_ECC_READ = FALSE)) then
GenericValueCheckMessage
( HeaderMsg => " Attribute Syntax Error : ",
GenericName => " EN_ECC_READ ",
EntityName => "/ARAMB36_INTERNAL",
GenericValue => EN_ECC_READ,
Unit => "",
ExpectedValueMsg => " The Legal values for this attribute are ",
ExpectedGenericValue => " TRUE or FALSE ",
TailMsg => "",
MsgSeverity => failure
);
end if;
if (not(EN_ECC_WRITE = TRUE or EN_ECC_WRITE = FALSE)) then
GenericValueCheckMessage
( HeaderMsg => " Attribute Syntax Error : ",
GenericName => " EN_ECC_WRITE ",
EntityName => "/ARAMB36_INTERNAL",
GenericValue => EN_ECC_WRITE,
Unit => "",
ExpectedValueMsg => " The Legal values for this attribute are ",
ExpectedGenericValue => " TRUE or FALSE ",
TailMsg => "",
MsgSeverity => failure
);
end if;
if (EN_ECC_SCRUB = TRUE) then
assert false
report "DRC Error : The attribute EN_ECC_SCRUB = TRUE is not supported on ARAMB36_INTERNAL instance."
severity failure;
end if;
if (not(EN_ECC_SCRUB = TRUE or EN_ECC_SCRUB = FALSE)) then
GenericValueCheckMessage
( HeaderMsg => " Attribute Syntax Error : ",
GenericName => " EN_ECC_SCRUB ",
EntityName => "/ARAMB36_INTERNAL",
GenericValue => EN_ECC_SCRUB,
Unit => "",
ExpectedValueMsg => " The Legal values for this attribute are ",
ExpectedGenericValue => " TRUE or FALSE ",
TailMsg => "",
MsgSeverity => failure
);
end if;
if (EN_ECC_READ = FALSE and EN_ECC_SCRUB = TRUE) then
assert false
report "DRC Error : The attribute EN_ECC_SCRUB = TRUE is vaild only if the attribute EN_ECC_READ set to TRUE on ARAMB36_INTERNAL instance."
severity failure;
end if;
if (READ_WIDTH_A = 0 and READ_WIDTH_B = 0) then
assert false
report "Attribute Syntax Error : Attributes READ_WIDTH_A and READ_WIDTH_B on ARAMB36_INTERNAL instance, both can not be 0."
severity failure;
end if;
if (WRITE_MODE_A = "WRITE_FIRST") then
wr_mode_a := "00";
elsif (WRITE_MODE_A = "READ_FIRST") then
wr_mode_a := "01";
elsif (WRITE_MODE_A = "NO_CHANGE") then
wr_mode_a := "10";
else
GenericValueCheckMessage
( HeaderMsg => " Attribute Syntax Error : ",
GenericName => " WRITE_MODE_A ",
EntityName => "/ARAMB36_INTERNAL",
GenericValue => WRITE_MODE_A,
Unit => "",
ExpectedValueMsg => " The Legal values for this attribute are ",
ExpectedGenericValue => " WRITE_FIRST, READ_FIRST or NO_CHANGE ",
TailMsg => "",
MsgSeverity => failure
);
end if;
if (WRITE_MODE_B = "WRITE_FIRST") then
wr_mode_b := "00";
elsif (WRITE_MODE_B = "READ_FIRST") then
wr_mode_b := "01";
elsif (WRITE_MODE_B = "NO_CHANGE") then
wr_mode_b := "10";
else
GenericValueCheckMessage
( HeaderMsg => " Attribute Syntax Error : ",
GenericName => " WRITE_MODE_B ",
EntityName => "/ARAMB36_INTERNAL",
GenericValue => WRITE_MODE_B,
Unit => "",
ExpectedValueMsg => " The Legal values for this attribute are ",
ExpectedGenericValue => " WRITE_FIRST, READ_FIRST or NO_CHANGE ",
TailMsg => "",
MsgSeverity => failure
);
end if;
if (RAM_EXTENSION_A = "UPPER") then
cascade_a <= "11";
elsif (RAM_EXTENSION_A = "LOWER") then
cascade_a <= "01";
elsif (RAM_EXTENSION_A= "NONE") then
cascade_a <= "00";
else
GenericValueCheckMessage
( HeaderMsg => " Attribute Syntax Error : ",
GenericName => " RAM_EXTENSION_A ",
EntityName => "/ARAMB36_INTERNAL",
GenericValue => RAM_EXTENSION_A,
Unit => "",
ExpectedValueMsg => " The Legal values for this attribute are ",
ExpectedGenericValue => " NONE, LOWER or UPPER ",
TailMsg => "",
MsgSeverity => failure
);
end if;
if (RAM_EXTENSION_B = "UPPER") then
cascade_b <= "11";
elsif (RAM_EXTENSION_B = "LOWER") then
cascade_b <= "01";
elsif (RAM_EXTENSION_B= "NONE") then
cascade_b <= "00";
else
GenericValueCheckMessage
( HeaderMsg => " Attribute Syntax Error : ",
GenericName => " RAM_EXTENSION_B ",
EntityName => "/ARAMB36_INTERNAL",
GenericValue => RAM_EXTENSION_A,
Unit => "",
ExpectedValueMsg => " The Legal values for this attribute are ",
ExpectedGenericValue => " NONE, LOWER or UPPER ",
TailMsg => "",
MsgSeverity => failure
);
end if;
if( ((RAM_EXTENSION_A = "LOWER") or (RAM_EXTENSION_A = "UPPER")) and (READ_WIDTH_A /= 1)) then
assert false
report "Attribute Syntax Error: If RAM_EXTENSION_A is set to either LOWER or UPPER, then READ_WIDTH_A has to be set to 1."
severity Failure;
end if;
if( ((RAM_EXTENSION_A = "LOWER") or (RAM_EXTENSION_A = "UPPER")) and (WRITE_WIDTH_A /= 1)) then
assert false
report "Attribute Syntax Error: If RAM_EXTENSION_A is set to either LOWER or UPPER, then WRITE_WIDTH_A has to be set to 1."
severity Failure;
end if;
if( ((RAM_EXTENSION_B = "LOWER") or (RAM_EXTENSION_B = "UPPER")) and (READ_WIDTH_B /= 1)) then
assert false
report "Attribute Syntax Error: If RAM_EXTENSION_B is set to either LOWER or UPPER, then READ_WIDTH_B has to be set to 1."
severity Failure;
end if;
if( ((RAM_EXTENSION_B = "LOWER") or (RAM_EXTENSION_B = "UPPER")) and (WRITE_WIDTH_B /= 1)) then
assert false
report "Attribute Syntax Error: If RAM_EXTENSION_B is set to either LOWER or UPPER, then WRITE_WIDTH_B has to be set to 1."
severity Failure;
end if;
end if;
if (rising_edge(clka_dly)) then
if (ena_dly = '1') then
prev_time := curr_time;
curr_time := now;
addra_reg_dly := addra_dly;
wea_reg_dly := wea_dly;
dia_reg_dly := dia_dly;
dipa_reg_dly := dipa_dly;
end if;
end if;
if (rising_edge(clkb_dly)) then
if (enb_dly = '1') then
prev_time := curr_time;
curr_time := now;
addrb_reg_dly := addrb_dly;
web_reg_dly := web_dly;
dib_reg_dly := dib_dly;
dipb_reg_dly := dipb_dly;
end if;
end if;
if (gsr_dly = '1' or FIRST_TIME) then
doa_out(ra_width-1 downto 0) <= INIT_A_STD(ra_width-1 downto 0);
if (ra_width >= 8) then
dopa_out(ra_widthp-1 downto 0) <= INIT_A_STD((ra_width+ra_widthp)-1 downto ra_width);
end if;
dob_out(rb_width-1 downto 0) <= INIT_B_STD(rb_width-1 downto 0);
if (rb_width >= 8) then
dopb_out(rb_widthp-1 downto 0) <= INIT_B_STD((rb_width+rb_widthp)-1 downto rb_width);
end if;
dbiterr_out <= '0';
sbiterr_out <= '0';
FIRST_TIME := false;
elsif (gsr_dly = '0') then
if (rising_edge(clka_dly)) then
if (cascade_a(1) = '1') then
addra_dly_15_reg_bram_var := not addra_dly(15);
else
addra_dly_15_reg_bram_var := addra_dly(15);
end if;
end if;
if (rising_edge(clkb_dly)) then
if (cascade_b(1) = '1') then
addrb_dly_15_reg_bram_var := not addrb_dly(15);
else
addrb_dly_15_reg_bram_var := addrb_dly(15);
end if;
end if;
if (rising_edge(clka_dly) or rising_edge(clkb_dly)) then
if ((cascade_a = "00" or (addra_dly_15_reg_bram_var = '0' and cascade_a /= "00")) or (cascade_b = "00" or (addrb_dly_15_reg_bram_var = '0' and cascade_b /= "00"))) then
-------------------------------------------------------------------------------
-- Collision starts
-------------------------------------------------------------------------------
if (SIM_COLLISION_CHECK /= "NONE") then
if (curr_time - prev_time = 0 ps) then
viol_time := 1;
elsif (curr_time - prev_time <= SETUP_READ_FIRST) then
viol_time := 2;
end if;
if (ena_dly = '0' or enb_dly = '0') then
viol_time := 0;
end if;
if ((WRITE_WIDTH_A <= 9 and wea_dly(0) = '0') or (WRITE_WIDTH_A = 18 and wea_dly(1 downto 0) = "00") or ((WRITE_WIDTH_A = 36 or WRITE_WIDTH_A = 72) and wea_dly(3 downto 0) = "0000")) then
if ((WRITE_WIDTH_B <= 9 and web_dly(0) = '0') or (WRITE_WIDTH_B = 18 and web_dly(1 downto 0) = "00") or (WRITE_WIDTH_B = 36 and web_dly(3 downto 0) = "0000") or (WRITE_WIDTH_B = 72 and web_dly(7 downto 0) = "00000000")) then
viol_time := 0;
end if;
end if;
if (viol_time /= 0) then
if (rising_edge(clka_dly) and rising_edge(clkb_dly)) then
if (addra_dly(14 downto col_addr_lsb) = addrb_dly(14 downto col_addr_lsb)) then
viol_type := "01";
prcd_rd_ram_a (addra_dly, doa_buf, dopa_buf, mem, memp);
prcd_rd_ram_b (addrb_dly, dob_buf, dopb_buf, mem, memp);
prcd_col_wr_ram_a ("00", web_dly, wea_dly, di_x, di_x(7 downto 0), addrb_dly, addra_dly, mem, memp, col_wr_wr_msg, col_wra_rdb_msg, col_wrb_rda_msg);
prcd_col_wr_ram_b ("00", wea_dly, web_dly, di_x, di_x(7 downto 0), addra_dly, addrb_dly, mem, memp, col_wr_wr_msg, col_wra_rdb_msg, col_wrb_rda_msg);
prcd_col_rd_ram_a (viol_type, "01", web_dly, wea_dly, addra_dly, doa_buf, dopa_buf, mem, memp, wr_mode_a);
prcd_col_rd_ram_b (viol_type, "01", wea_dly, web_dly, addrb_dly, dob_buf, dopb_buf, mem, memp, wr_mode_b);
prcd_col_wr_ram_a ("10", web_dly, wea_dly, dia_dly, dipa_dly, addrb_dly, addra_dly, mem, memp, col_wr_wr_msg, col_wra_rdb_msg, col_wrb_rda_msg);
if (BRAM_MODE = "ECC" and EN_ECC_WRITE = TRUE and enb_dly = '1') then
dip_ecc_col := fn_dip_ecc('1', dib_dly, dipb_dly);
eccparity_out <= dip_ecc_col;
prcd_col_wr_ram_b ("10", wea_dly, web_dly, dib_dly, dip_ecc_col, addra_dly, addrb_dly, mem, memp, col_wr_wr_msg, col_wra_rdb_msg, col_wrb_rda_msg);
else
prcd_col_wr_ram_b ("10", wea_dly, web_dly, dib_dly, dipb_dly, addra_dly, addrb_dly, mem, memp, col_wr_wr_msg, col_wra_rdb_msg, col_wrb_rda_msg);
end if;
if (wr_mode_a /= "01") then
prcd_col_rd_ram_a (viol_type, "11", web_dly, wea_dly, addra_dly, doa_buf, dopa_buf, mem, memp, wr_mode_a);
end if;
if (wr_mode_b /= "01") then
prcd_col_rd_ram_b (viol_type, "11", wea_dly, web_dly, addrb_dly, dob_buf, dopb_buf, mem, memp, wr_mode_b);
end if;
if (BRAM_MODE = "ECC" and EN_ECC_READ = TRUE) then
prcd_col_ecc_read (doa_buf, dopa_buf, addra_dly, dbiterr_out_var, sbiterr_out_var, mem, memp, syndrome);
end if;
else
viol_time := 0;
end if;
elsif (rising_edge(clka_dly) and (not(rising_edge(clkb_dly)))) then
if (addra_dly(14 downto col_addr_lsb) = addrb_dly(14 downto col_addr_lsb)) then
viol_type := "10";
prcd_rd_ram_a (addra_dly, doa_buf, dopa_buf, mem, memp);
prcd_col_wr_ram_a ("00", web_reg_dly, wea_dly, di_x, di_x(7 downto 0), addrb_reg_dly, addra_dly, mem, memp, col_wr_wr_msg, col_wra_rdb_msg, col_wrb_rda_msg);
prcd_col_wr_ram_b ("00", wea_dly, web_reg_dly, di_x, di_x(7 downto 0), addra_dly, addrb_reg_dly, mem, memp, col_wr_wr_msg, col_wra_rdb_msg, col_wrb_rda_msg);
prcd_col_rd_ram_a (viol_type, "01", web_reg_dly, wea_dly, addra_dly, doa_buf, dopa_buf, mem, memp, wr_mode_a);
prcd_col_rd_ram_b (viol_type, "01", wea_dly, web_reg_dly, addrb_reg_dly, dob_buf, dopb_buf, mem, memp, wr_mode_b);
prcd_col_wr_ram_a ("10", web_reg_dly, wea_dly, dia_dly, dipa_dly, addrb_reg_dly, addra_dly, mem, memp, col_wr_wr_msg, col_wra_rdb_msg, col_wrb_rda_msg);
if (BRAM_MODE = "ECC" and EN_ECC_WRITE = TRUE and enb_dly = '1') then
dip_ecc_col := fn_dip_ecc('1', dib_reg_dly, dipb_reg_dly);
eccparity_out <= dip_ecc_col;
prcd_col_wr_ram_b ("10", wea_dly, web_reg_dly, dib_reg_dly, dip_ecc_col, addra_dly, addrb_reg_dly, mem, memp, col_wr_wr_msg, col_wra_rdb_msg, col_wrb_rda_msg);
else
prcd_col_wr_ram_b ("10", wea_dly, web_reg_dly, dib_reg_dly, dipb_reg_dly, addra_dly, addrb_reg_dly, mem, memp, col_wr_wr_msg, col_wra_rdb_msg, col_wrb_rda_msg);
end if;
if (wr_mode_a /= "01") then
prcd_col_rd_ram_a (viol_type, "11", web_reg_dly, wea_dly, addra_dly, doa_buf, dopa_buf, mem, memp, wr_mode_a);
end if;
if (wr_mode_b /= "01") then
prcd_col_rd_ram_b (viol_type, "11", wea_dly, web_reg_dly, addrb_reg_dly, dob_buf, dopb_buf, mem, memp, wr_mode_b);
end if;
if (BRAM_MODE = "ECC" and EN_ECC_READ = TRUE) then
prcd_col_ecc_read (doa_buf, dopa_buf, addra_dly, dbiterr_out_var, sbiterr_out_var, mem, memp, syndrome);
end if;
else
viol_time := 0;
end if;
elsif ((not(rising_edge(clka_dly))) and rising_edge(clkb_dly)) then
if (addra_dly(14 downto col_addr_lsb) = addrb_dly(14 downto col_addr_lsb)) then
viol_type := "11";
prcd_rd_ram_b (addrb_dly, dob_buf, dopb_buf, mem, memp);
prcd_col_wr_ram_a ("00", web_dly, wea_reg_dly, di_x, di_x(7 downto 0), addrb_dly, addra_reg_dly, mem, memp, col_wr_wr_msg, col_wra_rdb_msg, col_wrb_rda_msg);
prcd_col_wr_ram_b ("00", wea_reg_dly, web_dly, di_x, di_x(7 downto 0), addra_reg_dly, addrb_dly, mem, memp, col_wr_wr_msg, col_wra_rdb_msg, col_wrb_rda_msg);
prcd_col_rd_ram_a (viol_type, "01", web_dly, wea_reg_dly, addra_reg_dly, doa_buf, dopa_buf, mem, memp, wr_mode_a);
prcd_col_rd_ram_b (viol_type, "01", wea_reg_dly, web_dly, addrb_dly, dob_buf, dopb_buf, mem, memp, wr_mode_b);
prcd_col_wr_ram_a ("10", web_dly, wea_reg_dly, dia_reg_dly, dipa_reg_dly, addrb_dly, addra_reg_dly, mem, memp, col_wr_wr_msg, col_wra_rdb_msg, col_wrb_rda_msg);
if (BRAM_MODE = "ECC" and EN_ECC_WRITE = TRUE and enb_dly = '1') then
dip_ecc_col := fn_dip_ecc('1', dib_dly, dipb_dly);
eccparity_out <= dip_ecc_col;
prcd_col_wr_ram_b ("10", wea_reg_dly, web_dly, dib_dly, dip_ecc_col, addra_reg_dly, addrb_dly, mem, memp, col_wr_wr_msg, col_wra_rdb_msg, col_wrb_rda_msg);
else
prcd_col_wr_ram_b ("10", wea_reg_dly, web_dly, dib_dly, dipb_dly, addra_reg_dly, addrb_dly, mem, memp, col_wr_wr_msg, col_wra_rdb_msg, col_wrb_rda_msg);
end if;
if (wr_mode_a /= "01") then
prcd_col_rd_ram_a (viol_type, "11", web_dly, wea_reg_dly, addra_reg_dly, doa_buf, dopa_buf, mem, memp, wr_mode_a);
end if;
if (wr_mode_b /= "01") then
prcd_col_rd_ram_b (viol_type, "11", wea_reg_dly, web_dly, addrb_dly, dob_buf, dopb_buf, mem, memp, wr_mode_b);
end if;
if (BRAM_MODE = "ECC" and EN_ECC_READ = TRUE) then
prcd_col_ecc_read (doa_buf, dopa_buf, addra_reg_dly, dbiterr_out_var, sbiterr_out_var, mem, memp, syndrome);
end if;
else
viol_time := 0;
end if;
end if;
if (SIM_COLLISION_CHECK = "WARNING_ONLY") then
viol_time := 0;
end if;
end if;
end if;
-------------------------------------------------------------------------------
-- end collision
-------------------------------------------------------------------------------
end if;
-------------------------------------------------------------------------------
-- Port A
-------------------------------------------------------------------------------
if (rising_edge(clka_dly)) then
if (ssra_dly = '1' and BRAM_MODE = "ECC") then
assert false
report "DRC Warning : SET/RESET (SSR) is not supported in ECC mode."
severity Warning;
end if;
-- registering addra_dly(15) the second time
if (regcea_dly = '1') then
addra_dly_15_reg1 <= addra_dly_15_reg_var;
end if;
-- registering addra[15)
if (ena_dly = '1' and (wr_mode_a /= "10" or wea_dly(0) = '0')) then
if (cascade_a(1) = '1') then
addra_dly_15_reg_var := not addra_dly(15);
else
addra_dly_15_reg_var := addra_dly(15);
end if;
end if;
addra_dly_15_reg <= addra_dly_15_reg_var;
if (gsr_dly = '0' and ena_dly = '1' and (cascade_a = "00" or (addra_dly_15_reg_bram_var = '0' and cascade_a /= "00"))) then
if (ssra_dly = '1' and DOA_REG = 0) then
doa_buf(ra_width-1 downto 0) := SRVAL_A_STD(ra_width-1 downto 0);
doa_out(ra_width-1 downto 0) <= SRVAL_A_STD(ra_width-1 downto 0);
if (ra_width >= 8) then
dopa_buf(ra_widthp-1 downto 0) := SRVAL_A_STD((ra_width+ra_widthp)-1 downto ra_width);
dopa_out(ra_widthp-1 downto 0) <= SRVAL_A_STD((ra_width+ra_widthp)-1 downto ra_width);
end if;
end if;
if (viol_time = 0) then
-- read for rf
if ((wr_mode_a = "01" and (ssra_dly = '0' or DOA_REG = 1)) or (BRAM_MODE = "ECC" and EN_ECC_READ = TRUE)) then
prcd_rd_ram_a (addra_dly, doa_buf, dopa_buf, mem, memp);
-- ECC decode -- only port A
if (BRAM_MODE = "ECC" and EN_ECC_READ = TRUE) then
dopr_ecc := fn_dip_ecc('0', doa_buf, dopa_buf);
syndrome := dopr_ecc xor dopa_buf;
if (syndrome /= "00000000") then
if (syndrome(7) = '1') then -- dectect single bit error
ecc_bit_position := doa_buf(63 downto 57) & dopa_buf(6) & doa_buf(56 downto 26) & dopa_buf(5) & doa_buf(25 downto 11) & dopa_buf(4) & doa_buf(10 downto 4) & dopa_buf(3) & doa_buf(3 downto 1) & dopa_buf(2) & doa_buf(0) & dopa_buf(1 downto 0) & dopa_buf(7);
tmp_syndrome_int := SLV_TO_INT(syndrome(6 downto 0));
ecc_bit_position(tmp_syndrome_int) := not ecc_bit_position(tmp_syndrome_int); -- correct single bit error in the output
dia_dly_ecc_corrected := ecc_bit_position(71 downto 65) & ecc_bit_position(63 downto 33) & ecc_bit_position(31 downto 17) & ecc_bit_position(15 downto 9) & ecc_bit_position(7 downto 5) & ecc_bit_position(3); -- correct single bit error in the memory
doa_buf := dia_dly_ecc_corrected;
dipa_dly_ecc_corrected := ecc_bit_position(0) & ecc_bit_position(64) & ecc_bit_position(32) & ecc_bit_position(16) & ecc_bit_position(8) & ecc_bit_position(4) & ecc_bit_position(2 downto 1); -- correct single bit error in the parity memory
dopa_buf := dipa_dly_ecc_corrected;
dbiterr_out_var := '0';
sbiterr_out_var := '1';
elsif (syndrome(7) = '0') then -- double bit error
sbiterr_out_var := '0';
dbiterr_out_var := '1';
end if;
else
dbiterr_out_var := '0';
sbiterr_out_var := '0';
end if;
if (ssra_dly = '1') then -- ssra reset
dbiterr_out_var := '0';
sbiterr_out_var := '0';
end if;
end if;
end if;
if (syndrome /= "00000000" and syndrome(7) = '1' and EN_ECC_SCRUB = TRUE) then
prcd_wr_ram_a ("11111111", dia_dly_ecc_corrected, dipa_dly_ecc_corrected, addra_dly, mem, memp, syndrome);
else
prcd_wr_ram_a (wea_dly, dia_dly, dipa_dly, addra_dly, mem, memp, syndrome);
end if;
if ((wr_mode_a /= "01" and (ssra_dly = '0' or DOA_REG = 1)) and (not(BRAM_MODE = "ECC" and EN_ECC_READ = TRUE))) then
prcd_rd_ram_a (addra_dly, doa_buf, dopa_buf, mem, memp);
end if;
end if;
end if;
end if;
-------------------------------------------------------------------------------
-- Port B
-------------------------------------------------------------------------------
if (rising_edge(clkb_dly)) then
-- DRC
if (ssrb_dly = '1' and BRAM_MODE = "ECC") then
assert false
report "DRC Warning : SET/RESET (SSR) is not supported in ECC mode."
severity Warning;
end if;
-- registering addrb_dly(15) the second time
if (regceb_dly = '1') then
addrb_dly_15_reg1 <= addrb_dly_15_reg_var;
end if;
-- registering addrb(15)
if (enb_dly = '1' and (wr_mode_b /= "10" or web_dly(0) = '0' or ssrb_dly = '1')) then
if (cascade_b(1) = '1') then
addrb_dly_15_reg_var := not addrb_dly(15);
else
addrb_dly_15_reg_var := addrb_dly(15);
end if;
end if;
addrb_dly_15_reg <= addrb_dly_15_reg_var;
if (gsr_dly = '0' and enb_dly = '1' and (cascade_b = "00" or (addrb_dly_15_reg_bram_var = '0' and cascade_b /= "00"))) then
if (ssrb_dly = '1' and DOB_REG = 0) then
dob_buf(rb_width-1 downto 0) := SRVAL_B_STD(rb_width-1 downto 0);
dob_out(rb_width-1 downto 0) <= SRVAL_B_STD(rb_width-1 downto 0);
if (rb_width >= 8) then
dopb_buf(rb_widthp-1 downto 0) := SRVAL_B_STD((rb_width+rb_widthp)-1 downto rb_width);
dopb_out(rb_widthp-1 downto 0) <= SRVAL_B_STD((rb_width+rb_widthp)-1 downto rb_width);
end if;
end if;
dip_ecc := fn_dip_ecc('1', dib_dly, dipb_dly);
eccparity_out <= dip_ecc;
if (BRAM_MODE = "ECC" and EN_ECC_WRITE = TRUE) then
dipb_dly_ecc := dip_ecc;
else
dipb_dly_ecc := dipb_dly;
end if;
if (viol_time = 0) then
if (wr_mode_b = "01" and (ssrb_dly = '0' or DOB_REG = 1)) then
prcd_rd_ram_b (addrb_dly, dob_buf, dopb_buf, mem, memp);
end if;
if (BRAM_MODE = "ECC" and EN_ECC_WRITE = TRUE) then
prcd_wr_ram_b (web_dly, dib_dly, dipb_dly_ecc, addrb_dly, mem, memp);
else
prcd_wr_ram_b (web_dly, dib_dly, dipb_dly, addrb_dly, mem, memp);
end if;
if (wr_mode_b /= "01" and (ssrb_dly = '0' or DOB_REG = 1)) then
prcd_rd_ram_b (addrb_dly, dob_buf, dopb_buf, mem, memp);
end if;
end if;
end if;
end if;
if (ena_dly = '1' and (rising_edge(clka_dly) or viol_time /= 0)) then
if ((ssra_dly = '0' or DOA_REG = 1) and (wr_mode_a /= "10" or (WRITE_WIDTH_A <= 9 and wea_dly(0) = '0') or (WRITE_WIDTH_A = 18 and wea_dly(1 downto 0) = "00") or ((WRITE_WIDTH_A = 36 or WRITE_WIDTH_A = 72) and wea_dly(3 downto 0) = "0000"))) then
-- Virtex4 feature
if (wr_mode_a = "00" and BRAM_SIZE = 16) then
if ((WRITE_WIDTH_A = 18 and not(wea_dly(1 downto 0) = "00" or wea_dly(1 downto 0) = "11")) or (WRITE_WIDTH_A = 36 and not(wea_dly(3 downto 0) = "0000" or wea_dly(3 downto 0) = "1111"))) then
if (WRITE_WIDTH_A /= READ_WIDTH_A) then
doa_buf(ra_width-1 downto 0) := di_x(ra_width-1 downto 0);
if (READ_WIDTH_A >= 9) then
dopa_buf(ra_widthp-1 downto 0) := di_x(ra_widthp-1 downto 0);
end if;
Write ( Message, STRING'(" Functional warning at simulation time "));
Write ( Message, STRING'("( "));
Write ( Message, now);
Write ( Message, STRING'(") : "));
Write ( Message, STRING'("ARAMB36_INTERNAL "));
Write ( Message, STRING'("( "));
Write ( Message, STRING'(ARAMB36_INTERNAL'path_name));
Write ( Message, STRING'(") "));
Write ( Message, STRING'(" port A is in WRITE_FIRST mode with parameter WRITE_WIDTH_A = "));
Write ( Message, INTEGER'(WRITE_WIDTH_A));
Write ( Message, STRING'(", which is different from READ_WIDTH_A = "));
Write ( Message, INTEGER'(READ_WIDTH_A));
Write ( Message, STRING'(". The write will be successful however the read value of all bits on port A"));
Write ( Message, STRING'(" is unknown until the next CLKA cycle and all bits of WEA is set to all 1s or 0s. "));
Write ( Message, LF );
ASSERT FALSE REPORT Message.ALL SEVERITY warning;
DEALLOCATE (Message);
elsif (WRITE_WIDTH_A = 18) then
for i in 0 to 1 loop
if (wea_dly(i) = '0') then
doa_buf(((8*(i+1))-1) downto 8*i) := di_x(((8*(i+1))-1) downto 8*i);
dopa_buf(i downto i) := di_x(i downto i);
end if;
end loop;
Write ( Message, STRING'(" Functional warning at simulation time "));
Write ( Message, STRING'("( "));
Write ( Message, now);
Write ( Message, STRING'(") : "));
Write ( Message, STRING'("ARAMB36_INTERNAL "));
Write ( Message, STRING'("( "));
Write ( Message, STRING'(ARAMB36_INTERNAL'path_name));
Write ( Message, STRING'(") "));
Write ( Message, STRING'(" port A is in WRITE_FIRST mode. The write will be successful,"));
Write ( Message, STRING'(" however DOA shows only the enabled newly written byte(s)."));
Write ( Message, STRING'(" The other byte values on DOA are unknown until the next CLKA cycle and"));
Write ( Message, STRING'(" all bits of WEA is set to all 1s or 0s. "));
Write ( Message, LF );
ASSERT FALSE REPORT Message.ALL SEVERITY warning;
DEALLOCATE (Message);
elsif (WRITE_WIDTH_A = 36) then
for i in 0 to 3 loop
if (wea_dly(i) = '0') then
doa_buf(((8*(i+1))-1) downto 8*i) := di_x(((8*(i+1))-1) downto 8*i);
dopa_buf(i downto i) := di_x(i downto i);
end if;
end loop;
Write ( Message, STRING'(" Functional warning at simulation time "));
Write ( Message, STRING'("( "));
Write ( Message, now);
Write ( Message, STRING'(") : "));
Write ( Message, STRING'("ARAMB36_INTERNAL "));
Write ( Message, STRING'("( "));
Write ( Message, STRING'(ARAMB36_INTERNAL'path_name));
Write ( Message, STRING'(") "));
Write ( Message, STRING'(" port A is in WRITE_FIRST mode. The write will be successful,"));
Write ( Message, STRING'(" however DOA shows only the enabled newly written byte(s)."));
Write ( Message, STRING'(" The other byte values on DOA are unknown until the next CLKA cycle and"));
Write ( Message, STRING'(" all bits of WEA is set to all 1s or 0s. "));
Write ( Message, LF );
ASSERT FALSE REPORT Message.ALL SEVERITY warning;
DEALLOCATE (Message);
end if;
end if;
end if;
doa_out <= doa_buf;
dopa_out <= dopa_buf;
end if;
end if;
if (enb_dly = '1' and (rising_edge(clkb_dly) or viol_time /= 0)) then
if ((ssrb_dly = '0' or DOB_REG = 1) and (wr_mode_b /= "10" or (WRITE_WIDTH_B <= 9 and web_dly(0) = '0') or (WRITE_WIDTH_B = 18 and web_dly(1 downto 0) = "00") or (WRITE_WIDTH_B = 36 and web_dly(3 downto 0) = "0000") or (WRITE_WIDTH_B = 72 and web_dly(7 downto 0) = "00000000"))) then
-- Virtex4 feature
if (wr_mode_b = "00" and BRAM_SIZE = 16) then
if ((WRITE_WIDTH_B = 18 and not(web_dly(1 downto 0) = "00" or web_dly(1 downto 0) = "11")) or (WRITE_WIDTH_B = 36 and not(web_dly(3 downto 0) = "0000" or web_dly(3 downto 0) = "1111"))) then
if (WRITE_WIDTH_B /= READ_WIDTH_B) then
dob_buf(rb_width-1 downto 0) := di_x(rb_width-1 downto 0);
if (READ_WIDTH_B >= 9) then
dopb_buf(rb_widthp-1 downto 0) := di_x(rb_widthp-1 downto 0);
end if;
Write ( Message, STRING'(" Functional warning at simulation time "));
Write ( Message, STRING'("( "));
Write ( Message, now);
Write ( Message, STRING'(") : "));
Write ( Message, STRING'("ARAMB36_INTERNAL "));
Write ( Message, STRING'("( "));
Write ( Message, STRING'(ARAMB36_INTERNAL'path_name));
Write ( Message, STRING'(") "));
Write ( Message, STRING'(" port B is in WRITE_FIRST mode with parameter WRITE_WIDTH_B = "));
Write ( Message, INTEGER'(WRITE_WIDTH_B));
Write ( Message, STRING'(", which is different from READ_WIDTH_B = "));
Write ( Message, INTEGER'(READ_WIDTH_B));
Write ( Message, STRING'(". The write will be successful however the read value of all bits on port B"));
Write ( Message, STRING'(" is unknown until the next CLKB cycle and all bits of WEB is set to all 1s or 0s. "));
Write ( Message, LF );
ASSERT FALSE REPORT Message.ALL SEVERITY warning;
DEALLOCATE (Message);
elsif (WRITE_WIDTH_B = 18) then
for i in 0 to 1 loop
if (web_dly(i) = '0') then
dob_buf(((8*(i+1))-1) downto 8*i) := di_x(((8*(i+1))-1) downto 8*i);
dopb_buf(i downto i) := di_x(i downto i);
end if;
end loop;
Write ( Message, STRING'(" Functional warning at simulation time "));
Write ( Message, STRING'("( "));
Write ( Message, now);
Write ( Message, STRING'(") : "));
Write ( Message, STRING'("ARAMB36_INTERNAL "));
Write ( Message, STRING'("( "));
Write ( Message, STRING'(ARAMB36_INTERNAL'path_name));
Write ( Message, STRING'(") "));
Write ( Message, STRING'(" port B is in WRITE_FIRST mode. The write will be successful,"));
Write ( Message, STRING'(" however DOB shows only the enabled newly written byte(s)."));
Write ( Message, STRING'(" The other byte values on DOB are unknown until the next CLKB cycle and"));
Write ( Message, STRING'(" all bits of WEB is set to all 1s or 0s. "));
Write ( Message, LF );
ASSERT FALSE REPORT Message.ALL SEVERITY warning;
DEALLOCATE (Message);
elsif (WRITE_WIDTH_B = 36) then
for i in 0 to 3 loop
if (web_dly(i) = '0') then
dob_buf(((8*(i+1))-1) downto 8*i) := di_x(((8*(i+1))-1) downto 8*i);
dopb_buf(i downto i) := di_x(i downto i);
end if;
end loop;
Write ( Message, STRING'(" Functional warning at simulation time "));
Write ( Message, STRING'("( "));
Write ( Message, now);
Write ( Message, STRING'(") : "));
Write ( Message, STRING'("ARAMB36_INTERNAL "));
Write ( Message, STRING'("( "));
Write ( Message, STRING'(ARAMB36_INTERNAL'path_name));
Write ( Message, STRING'(") "));
Write ( Message, STRING'(" port B is in WRITE_FIRST mode. The write will be successful,"));
Write ( Message, STRING'(" however DOB shows only the enabled newly written byte(s)."));
Write ( Message, STRING'(" The other byte values on DOB are unknown until the next CLKB cycle and"));
Write ( Message, STRING'(" all bits of WEB is set to all 1s or 0s. "));
Write ( Message, LF );
ASSERT FALSE REPORT Message.ALL SEVERITY warning;
DEALLOCATE (Message);
end if;
end if;
end if;
dob_out <= dob_buf;
dopb_out <= dopb_buf;
end if;
end if;
viol_time := 0;
viol_type := "00";
col_wr_wr_msg := '1';
col_wra_rdb_msg := '1';
col_wrb_rda_msg := '1';
dbiterr_out <= dbiterr_out_var;
sbiterr_out <= sbiterr_out_var;
end if;
end if;
end process prcs_clk;
outreg_clka: process (regclka_dly, gsr_dly)
variable FIRST_TIME : boolean := true;
begin -- process outreg_clka
if (rising_edge(regclka_dly) or rising_edge(gsr_dly) or FIRST_TIME) then
if (DOA_REG = 1) then
if (gsr_dly = '1' or FIRST_TIME) then
dbiterr_outreg <= '0';
sbiterr_outreg <= '0';
doa_outreg(ra_width-1 downto 0) <= INIT_A_STD(ra_width-1 downto 0);
if (ra_width >= 8) then
dopa_outreg(ra_widthp-1 downto 0) <= INIT_A_STD((ra_width+ra_widthp)-1 downto ra_width);
end if;
FIRST_TIME := false;
elsif (gsr_dly = '0') then
dbiterr_outreg <= dbiterr_out;
sbiterr_outreg <= sbiterr_out;
if (regcea_dly = '1') then
if (ssra_dly = '1') then
doa_outreg(ra_width-1 downto 0) <= SRVAL_A_STD(ra_width-1 downto 0);
if (ra_width >= 8) then
dopa_outreg(ra_widthp-1 downto 0) <= SRVAL_A_STD((ra_width+ra_widthp)-1 downto ra_width);
end if;
elsif (ssra_dly = '0') then
doa_outreg <= doa_out;
dopa_outreg <= dopa_out;
end if;
end if;
end if;
end if;
end if;
end process outreg_clka;
cascade_a_mux: process (clka_dly, cascadeinlata_dly, addra_dly_15_reg, doa_out, dopa_out)
begin -- process cascade_a_mux
if (rising_edge(clka_dly) or cascadeinlata_dly'event or addra_dly_15_reg'event or doa_out'event or dopa_out'event) then
if (cascade_a(1) = '1' and addra_dly_15_reg = '1') then
doa_out_mux(0) <= cascadeinlata_dly;
else
doa_out_mux <= doa_out;
dopa_out_mux <= dopa_out;
end if;
end if;
end process cascade_a_mux;
cascade_a_muxreg: process (regclka_dly, cascadeinrega_dly, addra_dly_15_reg1, doa_outreg, dopa_outreg)
begin -- process cascade_a_muxreg
if (rising_edge(regclka_dly) or cascadeinrega_dly'event or addra_dly_15_reg1'event or doa_outreg'event or dopa_outreg'event) then
if (cascade_a(1) = '1' and addra_dly_15_reg1 = '1') then
doa_outreg_mux(0) <= cascadeinrega_dly;
else
doa_outreg_mux <= doa_outreg;
dopa_outreg_mux <= dopa_outreg;
end if;
end if;
end process cascade_a_muxreg;
outmux_clka: process (doa_out_mux, dopa_out_mux, doa_outreg_mux, dopa_outreg_mux, dbiterr_out, dbiterr_outreg, sbiterr_out, sbiterr_outreg)
begin -- process outmux_clka
case DOA_REG is
when 0 =>
dbiterr_out_out <= dbiterr_out;
sbiterr_out_out <= sbiterr_out;
doa_out_out <= doa_out_mux;
dopa_out_out <= dopa_out_mux;
when 1 =>
dbiterr_out_out <= dbiterr_outreg;
sbiterr_out_out <= sbiterr_outreg;
doa_out_out <= doa_outreg_mux;
dopa_out_out <= dopa_outreg_mux;
when others => assert false
report "Attribute Syntax Error: The allowed integer values for DOA_REG are 0 or 1."
severity Failure;
end case;
end process outmux_clka;
outreg_clkb: process (regclkb_dly, gsr_dly)
variable FIRST_TIME : boolean := true;
begin -- process outreg_clkb
if (rising_edge(regclkb_dly) or rising_edge(gsr_dly) or FIRST_TIME) then
if (DOB_REG = 1) then
if (gsr_dly = '1' or FIRST_TIME) then
dob_outreg(rb_width-1 downto 0) <= INIT_B_STD(rb_width-1 downto 0);
if (rb_width >= 8) then
dopb_outreg(rb_widthp-1 downto 0) <= INIT_B_STD((rb_width+rb_widthp)-1 downto rb_width);
end if;
FIRST_TIME := false;
elsif (gsr_dly = '0') then
if (regceb_dly = '1') then
if (ssrb_dly = '1') then
dob_outreg(rb_width-1 downto 0) <= SRVAL_B_STD(rb_width-1 downto 0);
if (rb_width >= 8) then
dopb_outreg(rb_widthp-1 downto 0) <= SRVAL_B_STD((rb_width+rb_widthp)-1 downto rb_width);
end if;
elsif (ssrb_dly = '0') then
dob_outreg <= dob_out;
dopb_outreg <= dopb_out;
end if;
end if;
end if;
end if;
end if;
end process outreg_clkb;
cascade_b_mux: process (clkb_dly, cascadeinlatb_dly, addrb_dly_15_reg, dob_out, dopb_out)
begin -- process cascade_b_mux
if (rising_edge(clkb_dly) or cascadeinlatb_dly'event or addrb_dly_15_reg'event or dob_out'event or dopb_out'event) then
if (cascade_b(1) = '1' and addrb_dly_15_reg = '1') then
dob_out_mux(0) <= cascadeinlatb_dly;
else
dob_out_mux <= dob_out;
dopb_out_mux <= dopb_out;
end if;
end if;
end process cascade_b_mux;
cascade_b_muxreg: process (regclkb_dly, cascadeinregb_dly, addrb_dly_15_reg1, dob_outreg, dopb_outreg)
begin -- process cascade_b_muxreg
if (rising_edge(regclkb_dly) or cascadeinregb_dly'event or addrb_dly_15_reg1'event or dob_outreg'event or dopb_outreg'event) then
if (cascade_b(1) = '1' and addrb_dly_15_reg1 = '1') then
dob_outreg_mux(0) <= cascadeinregb_dly;
else
dob_outreg_mux <= dob_outreg;
dopb_outreg_mux <= dopb_outreg;
end if;
end if;
end process cascade_b_muxreg;
outmux_clkb: process (dob_out_mux, dopb_out_mux, dob_outreg_mux, dopb_outreg_mux)
begin -- process outmux_clkb
case DOB_REG is
when 0 =>
dob_out_out <= dob_out_mux;
dopb_out_out <= dopb_out_mux;
when 1 =>
dob_out_out <= dob_outreg_mux;
dopb_out_out <= dopb_outreg_mux;
when others => assert false
report "Attribute Syntax Error: The allowed integer values for DOB_REG are 0 or 1."
severity Failure;
end case;
end process outmux_clkb;
prcs_output: process (doa_out_out, dopa_out_out, dob_out_out, dopb_out_out, eccparity_out,
dbiterr_out_out, sbiterr_out_out, doa_out_mux(0), dob_out_mux(0),
doa_outreg_mux(0), dob_outreg_mux(0))
begin -- process prcs_output
DOA <= doa_out_out;
DOPA <= dopa_out_out;
DOB <= dob_out_out;
DOPB <= dopb_out_out;
ECCPARITY <= eccparity_out;
DBITERR <= dbiterr_out_out;
SBITERR <= sbiterr_out_out;
CASCADEOUTLATA <= doa_out_mux(0);
CASCADEOUTLATB <= dob_out_mux(0);
CASCADEOUTREGA <= doa_outreg_mux(0);
CASCADEOUTREGB <= dob_outreg_mux(0);
end process prcs_output;
end ARAMB36_INTERNAL_V;
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library STD;
use STD.TEXTIO.all;
library unisim;
use unisim.vpkg.all;
entity RAMB16 is
generic (
DOA_REG : integer := 0 ;
DOB_REG : integer := 0 ;
INIT_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_08 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_09 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_10 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_11 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_12 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_13 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_14 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_15 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_16 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_17 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_18 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_19 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_20 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_21 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_22 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_23 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_24 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_25 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_26 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_27 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_28 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_29 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_30 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_31 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_32 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_33 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_34 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_35 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_36 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_37 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_38 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_39 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_A : bit_vector := X"000000000";
INIT_B : bit_vector := X"000000000";
INITP_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INVERT_CLK_DOA_REG : boolean := false;
INVERT_CLK_DOB_REG : boolean := false;
RAM_EXTENSION_A : string := "NONE";
RAM_EXTENSION_B : string := "NONE";
READ_WIDTH_A : integer := 0;
READ_WIDTH_B : integer := 0;
SIM_COLLISION_CHECK : string := "ALL";
SRVAL_A : bit_vector := X"000000000";
SRVAL_B : bit_vector := X"000000000";
WRITE_MODE_A : string := "WRITE_FIRST";
WRITE_MODE_B : string := "WRITE_FIRST";
WRITE_WIDTH_A : integer := 0;
WRITE_WIDTH_B : integer := 0
);
port(
CASCADEOUTA : out std_ulogic;
CASCADEOUTB : out std_ulogic;
DOA : out std_logic_vector (31 downto 0);
DOB : out std_logic_vector (31 downto 0);
DOPA : out std_logic_vector (3 downto 0);
DOPB : out std_logic_vector (3 downto 0);
ADDRA : in std_logic_vector (14 downto 0);
ADDRB : in std_logic_vector (14 downto 0);
CASCADEINA : in std_ulogic;
CASCADEINB : in std_ulogic;
CLKA : in std_ulogic;
CLKB : in std_ulogic;
DIA : in std_logic_vector (31 downto 0);
DIB : in std_logic_vector (31 downto 0);
DIPA : in std_logic_vector (3 downto 0);
DIPB : in std_logic_vector (3 downto 0);
ENA : in std_ulogic;
ENB : in std_ulogic;
REGCEA : in std_ulogic;
REGCEB : in std_ulogic;
SSRA : in std_ulogic;
SSRB : in std_ulogic;
WEA : in std_logic_vector (3 downto 0);
WEB : in std_logic_vector (3 downto 0)
);
end RAMB16;
architecture RAMB16_V of RAMB16 is
component ARAMB36_INTERNAL
generic
(
BRAM_MODE : string := "TRUE_DUAL_PORT";
BRAM_SIZE : integer := 36;
DOA_REG : integer := 0;
DOB_REG : integer := 0;
INIT_A : bit_vector := X"000000000000000000";
INIT_B : bit_vector := X"000000000000000000";
RAM_EXTENSION_A : string := "NONE";
RAM_EXTENSION_B : string := "NONE";
READ_WIDTH_A : integer := 0;
READ_WIDTH_B : integer := 0;
SIM_COLLISION_CHECK : string := "ALL";
SRVAL_A : bit_vector := X"000000000000000000";
SRVAL_B : bit_vector := X"000000000000000000";
WRITE_MODE_A : string := "WRITE_FIRST";
WRITE_MODE_B : string := "WRITE_FIRST";
WRITE_WIDTH_A : integer := 0;
WRITE_WIDTH_B : integer := 0;
EN_ECC_READ : boolean := FALSE;
EN_ECC_SCRUB : boolean := FALSE;
EN_ECC_WRITE : boolean := FALSE;
INIT_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_08 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_09 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_10 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_11 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_12 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_13 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_14 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_15 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_16 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_17 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_18 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_19 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_20 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_21 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_22 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_23 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_24 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_25 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_26 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_27 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_28 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_29 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_30 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_31 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_32 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_33 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_34 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_35 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_36 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_37 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_38 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_39 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_40 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_41 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_42 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_43 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_44 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_45 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_46 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_47 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_48 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_49 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_4A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_4B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_4C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_4D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_4E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_4F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_50 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_51 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_52 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_53 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_54 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_55 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_56 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_57 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_58 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_59 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_5A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_5B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_5C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_5D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_5E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_5F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_60 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_61 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_62 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_63 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_64 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_65 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_66 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_67 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_68 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_69 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_6A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_6B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_6C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_6D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_6E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_6F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_70 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_71 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_72 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_73 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_74 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_75 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_76 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_77 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_78 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_79 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_7A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_7B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_7C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_7D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_7E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_7F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_08 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_09 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_0A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_0B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_0C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_0D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_0E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_0F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"
);
port
(
CASCADEOUTLATA : out std_ulogic;
CASCADEOUTLATB : out std_ulogic;
CASCADEOUTREGA : out std_ulogic;
CASCADEOUTREGB : out std_ulogic;
DBITERR : out std_ulogic;
DOA : out std_logic_vector(63 downto 0);
DOB : out std_logic_vector(63 downto 0);
DOPA : out std_logic_vector(7 downto 0);
DOPB : out std_logic_vector(7 downto 0);
ECCPARITY : out std_logic_vector(7 downto 0);
SBITERR : out std_ulogic;
ADDRA : in std_logic_vector(15 downto 0);
ADDRB : in std_logic_vector(15 downto 0);
CASCADEINLATA : in std_ulogic;
CASCADEINLATB : in std_ulogic;
CASCADEINREGA : in std_ulogic;
CASCADEINREGB : in std_ulogic;
CLKA : in std_ulogic;
CLKB : in std_ulogic;
DIA : in std_logic_vector(63 downto 0);
DIB : in std_logic_vector(63 downto 0);
DIPA : in std_logic_vector(7 downto 0);
DIPB : in std_logic_vector(7 downto 0);
ENA : in std_ulogic;
ENB : in std_ulogic;
REGCEA : in std_ulogic;
REGCEB : in std_ulogic;
REGCLKA : in std_ulogic;
REGCLKB : in std_ulogic;
SSRA : in std_ulogic;
SSRB : in std_ulogic;
WEA : in std_logic_vector(7 downto 0);
WEB : in std_logic_vector(7 downto 0)
);
end component;
constant SYNC_PATH_DELAY : time := 100 ps;
signal GND_4 : std_logic_vector(3 downto 0) := (others => '0');
signal GND_32 : std_logic_vector(31 downto 0) := (others => '0');
signal OPEN_4 : std_logic_vector(3 downto 0);
signal OPEN_32 : std_logic_vector(31 downto 0);
signal doa_dly : std_logic_vector(31 downto 0) := (others => '0');
signal dob_dly : std_logic_vector(31 downto 0) := (others => '0');
signal dopa_dly : std_logic_vector(3 downto 0) := (others => '0');
signal dopb_dly : std_logic_vector(3 downto 0) := (others => '0');
signal cascadeouta_dly : std_ulogic := '0';
signal cascadeoutb_dly : std_ulogic := '0';
signal addra_int : std_logic_vector(15 downto 0) := (others => '0');
signal addrb_int : std_logic_vector(15 downto 0) := (others => '0');
signal wea_int : std_logic_vector(7 downto 0) := (others => '0');
signal web_int : std_logic_vector(7 downto 0) := (others => '0');
signal clka_wire : std_ulogic := '0';
signal clkb_wire : std_ulogic := '0';
signal clka_tmp : std_ulogic := '0';
signal clkb_tmp : std_ulogic := '0';
begin
prcs_clk: process (CLKA, CLKB)
variable FIRST_TIME : boolean := true;
begin
if (FIRST_TIME) then
if((INVERT_CLK_DOA_REG = true) and (DOA_REG /= 1 )) then
assert false
report "Attribute Syntax Error: When INVERT_CLK_DOA_REG is set to TRUE, then DOA_REG has to be set to 1."
severity Failure;
end if;
if((INVERT_CLK_DOB_REG = true) and (DOB_REG /= 1 )) then
assert false
report "Attribute Syntax Error: When INVERT_CLK_DOB_REG is set to TRUE, then DOB_REG has to be set to 1."
severity Failure;
end if;
if((INVERT_CLK_DOA_REG /= TRUE) and (INVERT_CLK_DOA_REG /= FALSE)) then
assert false
report "Attribute Syntax Error : The allowed boolean values for INVERT_CLK_DOA_REG are TRUE or FALSE"
severity Failure;
end if;
if((INVERT_CLK_DOB_REG /= TRUE) and (INVERT_CLK_DOB_REG /= FALSE)) then
assert false
report "Attribute Syntax Error : The allowed boolean values for INVERT_CLK_DOB_REG are TRUE or FALSE"
severity Failure;
end if;
FIRST_TIME := false;
end if;
if (CLKA'event) then
if (DOA_REG = 1 and INVERT_CLK_DOA_REG = TRUE) then
clka_wire <= not CLKA;
else
clka_wire <= CLKA;
end if;
clka_tmp <= CLKA;
end if;
if (CLKB'event) then
if (DOB_REG = 1 and INVERT_CLK_DOB_REG = TRUE) then
clkb_wire <= not CLKB;
else
clkb_wire <= CLKB;
end if;
clkb_tmp <= CLKB;
end if;
end process prcs_clk;
addra_int <= ADDRA(14) & '0' & ADDRA(13 downto 0);
addrb_int <= ADDRB(14) & '0' & ADDRB(13 downto 0);
wea_int <= WEA & WEA;
web_int <= WEB & WEB;
RAMB16_inst : ARAMB36_INTERNAL
generic map (
DOA_REG => DOA_REG,
DOB_REG => DOB_REG,
INIT_A => INIT_A,
INIT_B => INIT_B,
INIT_00 => INIT_00,
INIT_01 => INIT_01,
INIT_02 => INIT_02,
INIT_03 => INIT_03,
INIT_04 => INIT_04,
INIT_05 => INIT_05,
INIT_06 => INIT_06,
INIT_07 => INIT_07,
INIT_08 => INIT_08,
INIT_09 => INIT_09,
INIT_0A => INIT_0A,
INIT_0B => INIT_0B,
INIT_0C => INIT_0C,
INIT_0D => INIT_0D,
INIT_0E => INIT_0E,
INIT_0F => INIT_0F,
INIT_10 => INIT_10,
INIT_11 => INIT_11,
INIT_12 => INIT_12,
INIT_13 => INIT_13,
INIT_14 => INIT_14,
INIT_15 => INIT_15,
INIT_16 => INIT_16,
INIT_17 => INIT_17,
INIT_18 => INIT_18,
INIT_19 => INIT_19,
INIT_1A => INIT_1A,
INIT_1B => INIT_1B,
INIT_1C => INIT_1C,
INIT_1D => INIT_1D,
INIT_1E => INIT_1E,
INIT_1F => INIT_1F,
INIT_20 => INIT_20,
INIT_21 => INIT_21,
INIT_22 => INIT_22,
INIT_23 => INIT_23,
INIT_24 => INIT_24,
INIT_25 => INIT_25,
INIT_26 => INIT_26,
INIT_27 => INIT_27,
INIT_28 => INIT_28,
INIT_29 => INIT_29,
INIT_2A => INIT_2A,
INIT_2B => INIT_2B,
INIT_2C => INIT_2C,
INIT_2D => INIT_2D,
INIT_2E => INIT_2E,
INIT_2F => INIT_2F,
INIT_30 => INIT_30,
INIT_31 => INIT_31,
INIT_32 => INIT_32,
INIT_33 => INIT_33,
INIT_34 => INIT_34,
INIT_35 => INIT_35,
INIT_36 => INIT_36,
INIT_37 => INIT_37,
INIT_38 => INIT_38,
INIT_39 => INIT_39,
INIT_3A => INIT_3A,
INIT_3B => INIT_3B,
INIT_3C => INIT_3C,
INIT_3D => INIT_3D,
INIT_3E => INIT_3E,
INIT_3F => INIT_3F,
INITP_00 => INITP_00,
INITP_01 => INITP_01,
INITP_02 => INITP_02,
INITP_03 => INITP_03,
INITP_04 => INITP_04,
INITP_05 => INITP_05,
INITP_06 => INITP_06,
INITP_07 => INITP_07,
SIM_COLLISION_CHECK => SIM_COLLISION_CHECK,
SRVAL_A => SRVAL_A,
SRVAL_B => SRVAL_B,
WRITE_MODE_A => WRITE_MODE_A,
WRITE_MODE_B => WRITE_MODE_B,
BRAM_MODE => "TRUE_DUAL_PORT",
BRAM_SIZE => 16,
RAM_EXTENSION_A => RAM_EXTENSION_A,
RAM_EXTENSION_B => RAM_EXTENSION_B,
READ_WIDTH_A => READ_WIDTH_A,
READ_WIDTH_B => READ_WIDTH_B,
WRITE_WIDTH_A => WRITE_WIDTH_A,
WRITE_WIDTH_B => WRITE_WIDTH_B
)
port map (
ADDRA => addra_int,
ADDRB => addrb_int,
CLKA => clka_tmp,
CLKB => clkb_tmp,
DIA(31 downto 0) => DIA,
DIA(63 downto 32) => GND_32,
DIB(31 downto 0) => DIB,
DIB(63 downto 32) => GND_32,
DIPA(3 downto 0) => DIPA,
DIPA(7 downto 4) => GND_4,
DIPB(3 downto 0) => DIPB,
DIPB(7 downto 4) => GND_4,
ENA => ENA,
ENB => ENB,
SSRA => SSRA,
SSRB => SSRB,
WEA => wea_int,
WEB => web_int,
DOA(31 downto 0) => doa_dly,
DOA(63 downto 32) => OPEN_32,
DOB(31 downto 0) => dob_dly,
DOB(63 downto 32) => OPEN_32,
DOPA(3 downto 0) => dopa_dly,
DOPA(7 downto 4) => OPEN_4,
DOPB(3 downto 0) => dopb_dly,
DOPB(7 downto 4) => OPEN_4,
CASCADEOUTLATA => cascadeouta_dly,
CASCADEOUTLATB => cascadeoutb_dly,
CASCADEOUTREGA => open,
CASCADEOUTREGB => open,
CASCADEINLATA => CASCADEINA,
CASCADEINLATB => CASCADEINB,
CASCADEINREGA => CASCADEINA,
CASCADEINREGB => CASCADEINB,
REGCLKA => clka_wire,
REGCLKB => clkb_wire,
REGCEA => REGCEA,
REGCEB => REGCEB
);
prcs_output_wtiming: process (doa_dly, dob_dly, dopa_dly, dopb_dly, cascadeouta_dly, cascadeoutb_dly)
begin -- process prcs_output_wtiming
CASCADEOUTA <= cascadeouta_dly after SYNC_PATH_DELAY;
CASCADEOUTB <= cascadeoutb_dly after SYNC_PATH_DELAY;
DOA <= doa_dly after SYNC_PATH_DELAY;
DOPA <= dopa_dly after SYNC_PATH_DELAY;
DOB <= dob_dly after SYNC_PATH_DELAY;
DOPB <= dopb_dly after SYNC_PATH_DELAY;
end process prcs_output_wtiming;
end RAMB16_V;
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library UNISIM;
use UNISIM.VPKG.all;
entity RAM64X1D is
generic (
INIT : bit_vector(63 downto 0) := X"0000000000000000"
);
port (
DPO : out std_ulogic;
SPO : out std_ulogic;
A0 : in std_ulogic;
A1 : in std_ulogic;
A2 : in std_ulogic;
A3 : in std_ulogic;
A4 : in std_ulogic;
A5 : in std_ulogic;
D : in std_ulogic;
DPRA0 : in std_ulogic;
DPRA1 : in std_ulogic;
DPRA2 : in std_ulogic;
DPRA3 : in std_ulogic;
DPRA4 : in std_ulogic;
DPRA5 : in std_ulogic;
WCLK : in std_ulogic;
WE : in std_ulogic
);
end RAM64X1D;
architecture RAM64X1D_V of RAM64X1D is
signal MEM : std_logic_vector( 64 downto 0 ) := ('X' & To_StdLogicVector(INIT) );
begin
VITALReadBehavior : process(A0, A1, A2, A3, A4, A5, DPRA5, DPRA4, DPRA3, DPRA2, DPRA1, DPRA0, WCLK, MEM)
variable Index_SP : integer := 64;
variable Index_DP : integer := 64;
variable Raddress : std_logic_vector (5 downto 0);
variable Waddress : std_logic_vector (5 downto 0);
begin
Waddress := (A5, A4, A3, A2, A1, A0);
Raddress := (DPRA5, DPRA4, DPRA3, DPRA2, DPRA1, DPRA0);
Index_SP := SLV_TO_INT(SLV => Waddress);
Index_DP := SLV_TO_INT(SLV => Raddress);
SPO <= MEM(Index_SP);
DPO <= MEM(Index_DP);
end process VITALReadBehavior;
VITALWriteBehavior : process(WCLK)
variable Index_SP : integer := 32;
variable Index_DP : integer := 32;
variable Address : std_logic_vector( 5 downto 0);
begin
Address := (A5, A4, A3, A2, A1, A0);
Index_SP := SLV_TO_INT(SLV => Address );
if ((WE = '1') and (wclk'event) and (wclk'last_value = '0') and (wclk = '1')) then
MEM(Index_SP) <= D after 100 ps;
end if;
end process VITALWriteBehavior;
end RAM64X1D_V;
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity MUXF8 is
port(
O : out std_ulogic;
I0 : in std_ulogic;
I1 : in std_ulogic;
S : in std_ulogic
);
end MUXF8;
architecture MUXF8_V of MUXF8 is
begin
VITALBehavior : process (I0, I1, S)
begin
if (S = '0') then
O <= I0;
elsif (S = '1') then
O <= I1;
end if;
end process;
end MUXF8_V;
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity BUF is
port(
O : out std_ulogic;
I : in std_ulogic
);
end BUF;
architecture BUF_V of BUF is
begin
O <= TO_X01(I);
end BUF_V;
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library unisim;
use unisim.VPKG.all;
use unisim.VCOMPONENTS.all;
entity LUT5 is
generic(
INIT : bit_vector := X"00000000"
);
port(
O : out std_ulogic;
I0 : in std_ulogic;
I1 : in std_ulogic;
I2 : in std_ulogic;
I3 : in std_ulogic;
I4 : in std_ulogic
);
end LUT5;
architecture LUT5_V of LUT5 is
function lut6_mux8 (d : std_logic_vector(7 downto 0); s : std_logic_vector(2 downto 0))
return std_logic is
variable lut6_mux8_o : std_logic;
function lut4_mux4f (df : std_logic_vector(3 downto 0); sf : std_logic_vector(1 downto 0) )
return std_logic is
variable lut4_mux4_f : std_logic;
begin
if (((sf(1) xor sf(0)) = '1') or ((sf(1) xor sf(0)) = '0')) then
lut4_mux4_f := df(SLV_TO_INT(sf));
elsif ((df(0) xor df(1)) = '0' and (df(2) xor df(3)) = '0'
and (df(0) xor df(2)) = '0') then
lut4_mux4_f := df(0);
elsif ((sf(1) = '0') and (df(0) = df(1))) then
lut4_mux4_f := df(0);
elsif ((sf(1) = '1') and (df(2) = df(3))) then
lut4_mux4_f := df(2);
elsif ((sf(0) = '0') and (df(0) = df(2))) then
lut4_mux4_f := df(0);
elsif ((sf(0) = '1') and (df(1) = df(3))) then
lut4_mux4_f := df(1);
else
lut4_mux4_f := 'X';
end if;
return (lut4_mux4_f);
end function lut4_mux4f;
begin
if ((s(2) xor s(1) xor s(0)) = '1' or (s(2) xor s(1) xor s(0)) = '0') then
lut6_mux8_o := d(SLV_TO_INT(s));
else
lut6_mux8_o := lut4_mux4f(('0' & '0' & lut4_mux4f(d(7 downto 4), s(1 downto 0)) &
lut4_mux4f(d(3 downto 0), s(1 downto 0))), ('0' & s(2)));
end if;
return (lut6_mux8_o);
end function lut6_mux8;
function lut4_mux4 (d : std_logic_vector(3 downto 0); s : std_logic_vector(1 downto 0) )
return std_logic is
variable lut4_mux4_o : std_logic;
begin
if (((s(1) xor s(0)) = '1') or ((s(1) xor s(0)) = '0')) then
lut4_mux4_o := d(SLV_TO_INT(s));
elsif ((d(0) xor d(1)) = '0' and (d(2) xor d(3)) = '0'
and (d(0) xor d(2)) = '0') then
lut4_mux4_o := d(0);
elsif ((s(1) = '0') and (d(0) = d(1))) then
lut4_mux4_o := d(0);
elsif ((s(1) = '1') and (d(2) = d(3))) then
lut4_mux4_o := d(2);
elsif ((s(0) = '0') and (d(0) = d(2))) then
lut4_mux4_o := d(0);
elsif ((s(0) = '1') and (d(1) = d(3))) then
lut4_mux4_o := d(1);
else
lut4_mux4_o := 'X';
end if;
return (lut4_mux4_o);
end function lut4_mux4;
constant INIT_reg : std_logic_vector(31 downto 0) := To_StdLogicVector(INIT);
begin
lut_p : process (I0, I1, I2, I3, I4)
variable I_reg : std_logic_vector(4 downto 0);
begin
I_reg := TO_STDLOGICVECTOR(I4 & I3 & I2 & I1 & I0);
if ((I4 xor I3 xor I2 xor I1 xor I0) = '1' or (I4 xor I3 xor I2 xor I1 xor I0) = '0') then
O <= INIT_reg(SLV_TO_INT(I_reg));
else
O <= lut4_mux4 (
(lut6_mux8 ( INIT_reg(31 downto 24), I_reg(2 downto 0)) &
lut6_mux8 ( INIT_reg(23 downto 16), I_reg(2 downto 0)) &
lut6_mux8 ( INIT_reg(15 downto 8), I_reg(2 downto 0)) &
lut6_mux8 ( INIT_reg(7 downto 0), I_reg(2 downto 0))),
I_reg(4 downto 3));
end if;
end process;
end LUT5_V;
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library unisim;
use unisim.VPKG.all;
use unisim.VCOMPONENTS.all;
entity LUT5_L is
generic(
INIT : bit_vector := X"00000000"
);
port(
LO : out std_ulogic;
I0 : in std_ulogic;
I1 : in std_ulogic;
I2 : in std_ulogic;
I3 : in std_ulogic;
I4 : in std_ulogic
);
end LUT5_L;
architecture LUT5_L_V of LUT5_L is
function lut6_mux8 (d : std_logic_vector(7 downto 0); s : std_logic_vector(2 downto 0))
return std_logic is
variable lut6_mux8_o : std_logic;
function lut4_mux4f (df : std_logic_vector(3 downto 0); sf : std_logic_vector(1 downto 0) )
return std_logic is
variable lut4_mux4_f : std_logic;
begin
if (((sf(1) xor sf(0)) = '1') or ((sf(1) xor sf(0)) = '0')) then
lut4_mux4_f := df(SLV_TO_INT(sf));
elsif ((df(0) xor df(1)) = '0' and (df(2) xor df(3)) = '0'
and (df(0) xor df(2)) = '0') then
lut4_mux4_f := df(0);
elsif ((sf(1) = '0') and (df(0) = df(1))) then
lut4_mux4_f := df(0);
elsif ((sf(1) = '1') and (df(2) = df(3))) then
lut4_mux4_f := df(2);
elsif ((sf(0) = '0') and (df(0) = df(2))) then
lut4_mux4_f := df(0);
elsif ((sf(0) = '1') and (df(1) = df(3))) then
lut4_mux4_f := df(1);
else
lut4_mux4_f := 'X';
end if;
return (lut4_mux4_f);
end function lut4_mux4f;
begin
if ((s(2) xor s(1) xor s(0)) = '1' or (s(2) xor s(1) xor s(0)) = '0') then
lut6_mux8_o := d(SLV_TO_INT(s));
else
lut6_mux8_o := lut4_mux4f(('0' & '0' & lut4_mux4f(d(7 downto 4), s(1 downto 0)) &
lut4_mux4f(d(3 downto 0), s(1 downto 0))), ('0' & s(2)));
end if;
return (lut6_mux8_o);
end function lut6_mux8;
function lut4_mux4 (d : std_logic_vector(3 downto 0); s : std_logic_vector(1 downto 0) )
return std_logic is
variable lut4_mux4_o : std_logic;
begin
if (((s(1) xor s(0)) = '1') or ((s(1) xor s(0)) = '0')) then
lut4_mux4_o := d(SLV_TO_INT(s));
elsif ((d(0) xor d(1)) = '0' and (d(2) xor d(3)) = '0'
and (d(0) xor d(2)) = '0') then
lut4_mux4_o := d(0);
elsif ((s(1) = '0') and (d(0) = d(1))) then
lut4_mux4_o := d(0);
elsif ((s(1) = '1') and (d(2) = d(3))) then
lut4_mux4_o := d(2);
elsif ((s(0) = '0') and (d(0) = d(2))) then
lut4_mux4_o := d(0);
elsif ((s(0) = '1') and (d(1) = d(3))) then
lut4_mux4_o := d(1);
else
lut4_mux4_o := 'X';
end if;
return (lut4_mux4_o);
end function lut4_mux4;
constant INIT_reg : std_logic_vector(31 downto 0) := To_StdLogicVector(INIT);
begin
lut_p : process (I0, I1, I2, I3, I4)
variable INIT_reg : std_logic_vector(31 downto 0) := To_StdLogicVector(INIT);
variable I_reg : std_logic_vector(4 downto 0);
begin
I_reg := TO_STDLOGICVECTOR(I4 & I3 & I2 & I1 & I0);
if ((I4 xor I3 xor I2 xor I1 xor I0) = '1' or (I4 xor I3 xor I2 xor I1 xor I0) = '0') then
LO <= INIT_reg(SLV_TO_INT(I_reg));
else
LO <= lut4_mux4 (
(lut6_mux8 ( INIT_reg(31 downto 24), I_reg(2 downto 0)) &
lut6_mux8 ( INIT_reg(23 downto 16), I_reg(2 downto 0)) &
lut6_mux8 ( INIT_reg(15 downto 8), I_reg(2 downto 0)) &
lut6_mux8 ( INIT_reg(7 downto 0), I_reg(2 downto 0))),
I_reg(4 downto 3));
end if;
end process;
end LUT5_L_V;
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library unisim;
use unisim.VPKG.all;
use unisim.VCOMPONENTS.all;
entity LUT6 is
generic(
INIT : bit_vector := X"0000000000000000"
);
port(
O : out std_ulogic;
I0 : in std_ulogic;
I1 : in std_ulogic;
I2 : in std_ulogic;
I3 : in std_ulogic;
I4 : in std_ulogic;
I5 : in std_ulogic
);
end LUT6;
architecture LUT6_V of LUT6 is
function lut6_mux8 (d : std_logic_vector(7 downto 0); s : std_logic_vector(2 downto 0) )
return std_logic is
variable lut6_mux8_o : std_logic;
function lut4_mux4f (df : std_logic_vector(3 downto 0); sf : std_logic_vector(1 downto 0) )
return std_logic is
variable lut4_mux4_f : std_logic;
begin
if (((sf(1) xor sf(0)) = '1') or ((sf(1) xor sf(0)) = '0')) then
lut4_mux4_f := df(SLV_TO_INT(sf));
elsif ((df(0) xor df(1)) = '0' and (df(2) xor df(3)) = '0'
and (df(0) xor df(2)) = '0') then
lut4_mux4_f := df(0);
elsif ((sf(1) = '0') and (df(0) = df(1))) then
lut4_mux4_f := df(0);
elsif ((sf(1) = '1') and (df(2) = df(3))) then
lut4_mux4_f := df(2);
elsif ((sf(0) = '0') and (df(0) = df(2))) then
lut4_mux4_f := df(0);
elsif ((sf(0) = '1') and (df(1) = df(3))) then
lut4_mux4_f := df(1);
else
lut4_mux4_f := 'X';
end if;
return (lut4_mux4_f);
end function lut4_mux4f;
begin
if ((s(2) xor s(1) xor s(0)) = '1' or (s(2) xor s(1) xor s(0)) = '0') then
lut6_mux8_o := d(SLV_TO_INT(s));
else
lut6_mux8_o := lut4_mux4f(('0' & '0' & lut4_mux4f(d(7 downto 4), s(1 downto 0)) &
lut4_mux4f(d(3 downto 0), s(1 downto 0))), ('0' & s(2)));
end if;
return (lut6_mux8_o);
end function lut6_mux8;
constant INIT_reg : std_logic_vector(63 downto 0) := To_StdLogicVector(INIT);
begin
lut_p : process (I0, I1, I2, I3, I4, I5)
variable I_reg : std_logic_vector(5 downto 0);
begin
I_reg := TO_STDLOGICVECTOR(I5 & I4 & I3 & I2 & I1 & I0);
if ((I5 xor I4 xor I3 xor I2 xor I1 xor I0) = '1' or (I5 xor I4 xor I3 xor I2 xor I1 xor I0) = '0') then
O <= INIT_reg(SLV_TO_INT(I_reg));
else
O <= lut6_mux8 (
(lut6_mux8 ( INIT_reg(63 downto 56), I_reg(2 downto 0)) &
lut6_mux8 ( INIT_reg(55 downto 48), I_reg(2 downto 0)) &
lut6_mux8 ( INIT_reg(47 downto 40), I_reg(2 downto 0)) &
lut6_mux8 ( INIT_reg(39 downto 32), I_reg(2 downto 0)) &
lut6_mux8 ( INIT_reg(31 downto 24), I_reg(2 downto 0)) &
lut6_mux8 ( INIT_reg(23 downto 16), I_reg(2 downto 0)) &
lut6_mux8 ( INIT_reg(15 downto 8), I_reg(2 downto 0)) &
lut6_mux8 ( INIT_reg(7 downto 0), I_reg(2 downto 0))),
I_reg(5 downto 3));
end if;
end process;
end LUT6_V;
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library unisim;
use unisim.VPKG.all;
use unisim.VCOMPONENTS.all;
entity LUT6_L is
generic(
INIT : bit_vector := X"0000000000000000"
);
port(
LO : out std_ulogic;
I0 : in std_ulogic;
I1 : in std_ulogic;
I2 : in std_ulogic;
I3 : in std_ulogic;
I4 : in std_ulogic;
I5 : in std_ulogic
);
end LUT6_L;
architecture LUT6_L_V of LUT6_L is
function lut6_mux8 (d : std_logic_vector(7 downto 0); s : std_logic_vector(2 downto 0) )
return std_logic is
variable lut6_mux8_o : std_logic;
function lut4_mux4f (df : std_logic_vector(3 downto 0); sf : std_logic_vector(1 downto 0) )
return std_logic is
variable lut4_mux4_f : std_logic;
begin
if (((sf(1) xor sf(0)) = '1') or ((sf(1) xor sf(0)) = '0')) then
lut4_mux4_f := df(SLV_TO_INT(sf));
elsif ((df(0) xor df(1)) = '0' and (df(2) xor df(3)) = '0'
and (df(0) xor df(2)) = '0') then
lut4_mux4_f := df(0);
elsif ((sf(1) = '0') and (df(0) = df(1))) then
lut4_mux4_f := df(0);
elsif ((sf(1) = '1') and (df(2) = df(3))) then
lut4_mux4_f := df(2);
elsif ((sf(0) = '0') and (df(0) = df(2))) then
lut4_mux4_f := df(0);
elsif ((sf(0) = '1') and (df(1) = df(3))) then
lut4_mux4_f := df(1);
else
lut4_mux4_f := 'X';
end if;
return (lut4_mux4_f);
end function lut4_mux4f;
begin
if ((s(2) xor s(1) xor s(0)) = '1' or (s(2) xor s(1) xor s(0)) = '0') then
lut6_mux8_o := d(SLV_TO_INT(s));
else
lut6_mux8_o := lut4_mux4f(('0' & '0' & lut4_mux4f(d(7 downto 4), s(1 downto 0)) &
lut4_mux4f(d(3 downto 0), s(1 downto 0))), ('0' & s(2)));
end if;
return (lut6_mux8_o);
end function lut6_mux8;
constant INIT_reg : std_logic_vector(63 downto 0) := To_StdLogicVector(INIT);
begin
lut_p : process (I0, I1, I2, I3, I4, I5)
variable I_reg : std_logic_vector(5 downto 0);
begin
I_reg := TO_STDLOGICVECTOR(I5 & I4 & I3 & I2 & I1 & I0);
if ((I5 xor I4 xor I3 xor I2 xor I1 xor I0) = '1' or (I5 xor I4 xor I3 xor I2 xor I1 xor I0) = '0') then
LO <= INIT_reg(SLV_TO_INT(I_reg));
else
LO <= lut6_mux8 (
(lut6_mux8 ( INIT_reg(63 downto 56), I_reg(2 downto 0)) &
lut6_mux8 ( INIT_reg(55 downto 48), I_reg(2 downto 0)) &
lut6_mux8 ( INIT_reg(47 downto 40), I_reg(2 downto 0)) &
lut6_mux8 ( INIT_reg(39 downto 32), I_reg(2 downto 0)) &
lut6_mux8 ( INIT_reg(31 downto 24), I_reg(2 downto 0)) &
lut6_mux8 ( INIT_reg(23 downto 16), I_reg(2 downto 0)) &
lut6_mux8 ( INIT_reg(15 downto 8), I_reg(2 downto 0)) &
lut6_mux8 ( INIT_reg(7 downto 0), I_reg(2 downto 0))),
I_reg(5 downto 3));
end if;
end process;
end LUT6_L_V;
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library UNISIM;
use UNISIM.VPKG.all;
entity RAM128X1S is
generic (
INIT : bit_vector(127 downto 0) := X"00000000000000000000000000000000"
);
port (
O : out std_ulogic;
A0 : in std_ulogic;
A1 : in std_ulogic;
A2 : in std_ulogic;
A3 : in std_ulogic;
A4 : in std_ulogic;
A5 : in std_ulogic;
A6 : in std_ulogic;
D : in std_ulogic;
WCLK : in std_ulogic;
WE : in std_ulogic
);
end RAM128X1S;
architecture RAM128X1S_V of RAM128X1S is
signal MEM : std_logic_vector( 128 downto 0 ) := ('X' & To_StdLogicVector(INIT) );
begin
VITALReadBehavior : process(A0, A1, A2, A3, A4, A5, A6, MEM)
Variable Index : integer := 128;
variable Address : std_logic_vector( 6 downto 0);
begin
Address := (A6, A5, A4, A3, A2, A1, A0);
Index := SLV_TO_INT(SLV => Address);
O <= MEM(Index);
end process VITALReadBehavior;
VITALWriteBehavior : process(WCLK)
Variable Index : integer := 128;
variable Address : std_logic_vector (6 downto 0);
begin
if (rising_edge(WCLK)) then
if (WE = '1') then
Address := (A6, A5, A4, A3, A2, A1, A0);
Index := SLV_TO_INT(SLV => Address);
MEM(Index) <= D after 100 ps;
end if;
end if;
end process VITALWriteBehavior;
end RAM128X1S_V;
-- pragma translate_on
| mit | e42450a972386c34631da1038813dec6 | 0.505519 | 3.68371 | false | false | false | false |
impedimentToProgress/UCI-BlueChip | AttackFiles/Attacks/privEsc/lib/eth/core/grethc.vhd | 2 | 66,506 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: greth
-- File: greth.vhd
-- Author: Marko Isomaki
-- Description: Ethernet Media Access Controller with Ethernet Debug
-- Communication Link
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.stdlib.all;
library eth;
use eth.grethpkg.all;
entity grethc is
generic(
ifg_gap : integer := 24;
attempt_limit : integer := 16;
backoff_limit : integer := 10;
mdcscaler : integer range 0 to 255 := 25;
enable_mdio : integer range 0 to 1 := 0;
fifosize : integer range 4 to 512 := 8;
nsync : integer range 1 to 2 := 2;
edcl : integer range 0 to 2 := 0;
edclbufsz : integer range 1 to 64 := 1;
macaddrh : integer := 16#00005E#;
macaddrl : integer := 16#000000#;
ipaddrh : integer := 16#c0a8#;
ipaddrl : integer := 16#0035#;
phyrstadr : integer range 0 to 32 := 0;
rmii : integer range 0 to 1 := 0;
oepol : integer range 0 to 1 := 0;
scanen : integer range 0 to 1 := 0);
port(
rst : in std_ulogic;
clk : in std_ulogic;
--ahb mst in
hgrant : in std_ulogic;
hready : in std_ulogic;
hresp : in std_logic_vector(1 downto 0);
hrdata : in std_logic_vector(31 downto 0);
--ahb mst out
hbusreq : out std_ulogic;
hlock : out std_ulogic;
htrans : out std_logic_vector(1 downto 0);
haddr : out std_logic_vector(31 downto 0);
hwrite : out std_ulogic;
hsize : out std_logic_vector(2 downto 0);
hburst : out std_logic_vector(2 downto 0);
hprot : out std_logic_vector(3 downto 0);
hwdata : out std_logic_vector(31 downto 0);
--apb slv in
psel : in std_ulogic;
penable : in std_ulogic;
paddr : in std_logic_vector(31 downto 0);
pwrite : in std_ulogic;
pwdata : in std_logic_vector(31 downto 0);
--apb slv out
prdata : out std_logic_vector(31 downto 0);
--irq
irq : out std_logic;
--rx ahb fifo
rxrenable : out std_ulogic;
rxraddress : out std_logic_vector(10 downto 0);
rxwrite : out std_ulogic;
rxwdata : out std_logic_vector(31 downto 0);
rxwaddress : out std_logic_vector(10 downto 0);
rxrdata : in std_logic_vector(31 downto 0);
--tx ahb fifo
txrenable : out std_ulogic;
txraddress : out std_logic_vector(10 downto 0);
txwrite : out std_ulogic;
txwdata : out std_logic_vector(31 downto 0);
txwaddress : out std_logic_vector(10 downto 0);
txrdata : in std_logic_vector(31 downto 0);
--edcl buf
erenable : out std_ulogic;
eraddress : out std_logic_vector(15 downto 0);
ewritem : out std_ulogic;
ewritel : out std_ulogic;
ewaddressm : out std_logic_vector(15 downto 0);
ewaddressl : out std_logic_vector(15 downto 0);
ewdata : out std_logic_vector(31 downto 0);
erdata : in std_logic_vector(31 downto 0);
--ethernet input signals
rmii_clk : in std_ulogic;
tx_clk : in std_ulogic;
rx_clk : in std_ulogic;
rxd : in std_logic_vector(3 downto 0);
rx_dv : in std_ulogic;
rx_er : in std_ulogic;
rx_col : in std_ulogic;
rx_crs : in std_ulogic;
mdio_i : in std_ulogic;
phyrstaddr : in std_logic_vector(4 downto 0);
--ethernet output signals
reset : out std_ulogic;
txd : out std_logic_vector(3 downto 0);
tx_en : out std_ulogic;
tx_er : out std_ulogic;
mdc : out std_ulogic;
mdio_o : out std_ulogic;
mdio_oe : out std_ulogic;
--scantest
testrst : in std_ulogic;
testen : in std_ulogic;
edcladdr : in std_logic_vector(3 downto 0) := "0000"
);
end entity;
architecture rtl of grethc is
procedure sel_op_mode(
capbil : in std_logic_vector(4 downto 0);
speed : out std_ulogic;
duplex : out std_ulogic) is
variable vspeed : std_ulogic;
variable vduplex : std_ulogic;
begin
vspeed := '0'; vduplex := '0';
vspeed := orv(capbil(4 downto 2));
vduplex := (vspeed and capbil(3)) or ((not vspeed) and capbil(1));
speed := vspeed;
duplex := vduplex;
end procedure;
--host constants
constant fabits : integer := log2(fifosize);
constant burstlength : integer := setburstlength(fifosize);
constant burstbits : integer := log2(burstlength);
constant ctrlopcode : std_logic_vector(15 downto 0) := X"8808";
constant broadcast : std_logic_vector(47 downto 0) := X"FFFFFFFFFFFF";
constant maxsizetx : integer := 1514;
constant index : integer := log2(edclbufsz);
constant receiveOK : std_logic_vector(3 downto 0) := "0000";
constant frameCheckError : std_logic_vector(3 downto 0) := "0100";
constant alignmentError : std_logic_vector(3 downto 0) := "0001";
constant frameTooLong : std_logic_vector(3 downto 0) := "0010";
constant overrun : std_logic_vector(3 downto 0) := "1000";
constant minpload : std_logic_vector(10 downto 0) :=
conv_std_logic_vector(60, 11);
--mdio constants
constant divisor : std_logic_vector(7 downto 0) :=
conv_std_logic_vector(mdcscaler, 8);
--receiver constants
constant maxsizerx : std_logic_vector(15 downto 0) :=
conv_std_logic_vector(1514, 16);
--edcl constants
type szvct is array (0 to 6) of integer;
constant ebuf : szvct := (64, 128, 128, 256, 256, 256, 256);
constant blbits : szvct := (6, 7, 7, 8, 8, 8, 8);
constant winsz : szvct := (4, 4, 8, 8, 16, 32, 64);
constant macaddrt : std_logic_vector(47 downto 0) :=
conv_std_logic_vector(macaddrh, 24) & conv_std_logic_vector(macaddrl, 24);
constant bpbits : integer := blbits(log2(edclbufsz));
constant wsz : integer := winsz(log2(edclbufsz));
constant bselbits : integer := log2(wsz);
constant eabits: integer := log2(edclbufsz) + 8;
constant ebufmax : std_logic_vector(bpbits-1 downto 0) := (others => '1');
constant bufsize : std_logic_vector(2 downto 0) :=
conv_std_logic_vector(log2(edclbufsz), 3);
constant ebufsize : integer := ebuf(log2(edclbufsz));
constant txfifosize : integer := getfifosize(edcl, fifosize, ebufsize);
constant txfabits : integer := log2(txfifosize);
constant txfifosizev : std_logic_vector(txfabits downto 0) :=
conv_std_logic_vector(txfifosize, txfabits+1);
constant rxburstlen : std_logic_vector(fabits downto 0) :=
conv_std_logic_vector(burstlength, fabits+1);
constant txburstlen : std_logic_vector(txfabits downto 0) :=
conv_std_logic_vector(burstlength, txfabits+1);
type edclrstate_type is (idle, wrda, wrdsa, wrsa, wrtype, ip, ipdata,
oplength, arp, iplength, ipcrc, arpop, udp, spill);
type duplexstate_type is (start, waitop, nextop, selmode, done);
--host types
type txd_state_type is (idle, read_desc, check_desc, req, fill_fifo,
check_result, write_result, readhdr, start, wrbus,
etdone, getlen, ahberror);
type rxd_state_type is (idle, read_desc, check_desc, read_req, read_fifo,
discard, write_status, write_status2);
--mdio types
type mdio_state_type is (idle, preamble, startst, op, op2, phyadr, regadr,
ta, ta2, ta3, data, dataend);
type ctrl_reg_type is record
txen : std_ulogic;
rxen : std_ulogic;
tx_irqen : std_ulogic;
rx_irqen : std_ulogic;
full_duplex : std_ulogic;
prom : std_ulogic;
reset : std_ulogic;
speed : std_ulogic;
end record;
type status_reg_type is record
tx_int : std_ulogic;
rx_int : std_ulogic;
rx_err : std_ulogic;
tx_err : std_ulogic;
txahberr : std_ulogic;
rxahberr : std_ulogic;
toosmall : std_ulogic;
invaddr : std_ulogic;
end record;
type mdio_ctrl_reg_type is record
phyadr : std_logic_vector(4 downto 0);
regadr : std_logic_vector(4 downto 0);
write : std_ulogic;
read : std_ulogic;
data : std_logic_vector(15 downto 0);
busy : std_ulogic;
linkfail : std_ulogic;
end record;
subtype mac_addr_reg_type is std_logic_vector(47 downto 0);
type fifo_access_in_type is record
renable : std_ulogic;
raddress : std_logic_vector(fabits-1 downto 0);
write : std_ulogic;
waddress : std_logic_vector(fabits-1 downto 0);
datain : std_logic_vector(31 downto 0);
end record;
type fifo_access_out_type is record
data : std_logic_vector(31 downto 0);
end record;
type tx_fifo_access_in_type is record
renable : std_ulogic;
raddress : std_logic_vector(txfabits-1 downto 0);
write : std_ulogic;
waddress : std_logic_vector(txfabits-1 downto 0);
datain : std_logic_vector(31 downto 0);
end record;
type tx_fifo_access_out_type is record
data : std_logic_vector(31 downto 0);
end record;
type edcl_ram_in_type is record
renable : std_ulogic;
raddress : std_logic_vector(eabits-1 downto 0);
writem : std_ulogic;
writel : std_ulogic;
waddressm : std_logic_vector(eabits-1 downto 0);
waddressl : std_logic_vector(eabits-1 downto 0);
datain : std_logic_vector(31 downto 0);
end record;
type edcl_ram_out_type is record
data : std_logic_vector(31 downto 0);
end record;
type reg_type is record
--user registers
ctrl : ctrl_reg_type;
status : status_reg_type;
mdio_ctrl : mdio_ctrl_reg_type;
mac_addr : mac_addr_reg_type;
txdesc : std_logic_vector(31 downto 10);
rxdesc : std_logic_vector(31 downto 10);
edclip : std_logic_vector(31 downto 0);
--master tx interface
txdsel : std_logic_vector(9 downto 3);
tmsto : eth_tx_ahb_in_type;
txdstate : txd_state_type;
txwrap : std_ulogic;
txden : std_ulogic;
txirq : std_ulogic;
txaddr : std_logic_vector(31 downto 2);
txlength : std_logic_vector(10 downto 0);
txburstcnt : std_logic_vector(burstbits downto 0);
tfwpnt : std_logic_vector(txfabits-1 downto 0);
tfrpnt : std_logic_vector(txfabits-1 downto 0);
tfcnt : std_logic_vector(txfabits downto 0);
txcnt : std_logic_vector(10 downto 0);
txstart : std_ulogic;
txirqgen : std_ulogic;
txstatus : std_logic_vector(1 downto 0);
txvalid : std_ulogic;
txdata : std_logic_vector(31 downto 0);
writeok : std_ulogic;
txread : std_logic_vector(nsync-1 downto 0);
txrestart : std_logic_vector(nsync downto 0);
txdone : std_logic_vector(nsync downto 0);
txstart_sync : std_ulogic;
txreadack : std_ulogic;
txdataav : std_ulogic;
txburstav : std_ulogic;
--master rx interface
rxdsel : std_logic_vector(9 downto 3);
rmsto : eth_rx_ahb_in_type;
rxdstate : rxd_state_type;
rxstatus : std_logic_vector(4 downto 0);
rxaddr : std_logic_vector(31 downto 2);
rxlength : std_logic_vector(10 downto 0);
rxbytecount : std_logic_vector(10 downto 0);
rxwrap : std_ulogic;
rxirq : std_ulogic;
rfwpnt : std_logic_vector(fabits-1 downto 0);
rfrpnt : std_logic_vector(fabits-1 downto 0);
rfcnt : std_logic_vector(fabits downto 0);
rxcnt : std_logic_vector(10 downto 0);
rxdoneold : std_ulogic;
rxdoneack : std_ulogic;
rxdone : std_logic_vector(nsync-1 downto 0);
rxstart : std_logic_vector(nsync downto 0);
rxwrite : std_logic_vector(nsync-1 downto 0);
rxwriteack : std_ulogic;
rxburstcnt : std_logic_vector(burstbits downto 0);
addrnok : std_ulogic;
ctrlpkt : std_ulogic;
check : std_ulogic;
checkdata : std_logic_vector(31 downto 0);
usesizefield : std_ulogic;
rxden : std_ulogic;
gotframe : std_ulogic;
bcast : std_ulogic;
rxburstav : std_ulogic;
--mdio
mdccnt : std_logic_vector(7 downto 0);
mdioclk : std_ulogic;
mdioclkold : std_ulogic;
mdio_state : mdio_state_type;
mdioo : std_ulogic;
mdioi : std_ulogic;
mdioen : std_ulogic;
cnt : std_logic_vector(4 downto 0);
duplexstate : duplexstate_type;
ext : std_ulogic;
extcap : std_ulogic;
regaddr : std_logic_vector(4 downto 0);
phywr : std_ulogic;
rstphy : std_ulogic;
capbil : std_logic_vector(4 downto 0);
rstaneg : std_ulogic;
--edcl
edclrstate : edclrstate_type;
edclactive : std_ulogic;
nak : std_ulogic;
ewr : std_ulogic;
write : std_logic_vector(wsz-1 downto 0);
seq : std_logic_vector(13 downto 0);
abufs : std_logic_vector(bselbits downto 0);
tpnt : std_logic_vector(bselbits-1 downto 0);
rpnt : std_logic_vector(bselbits-1 downto 0);
tcnt : std_logic_vector(bpbits-1 downto 0);
rcntm : std_logic_vector(bpbits-1 downto 0);
rcntl : std_logic_vector(bpbits-1 downto 0);
ipcrc : std_logic_vector(17 downto 0);
applength : std_logic_vector(15 downto 0);
oplen : std_logic_vector(9 downto 0);
udpsrc : std_logic_vector(15 downto 0);
ecnt : std_logic_vector(3 downto 0);
tarp : std_ulogic;
tnak : std_ulogic;
tedcl : std_ulogic;
edclbcast : std_ulogic;
end record;
--host signals
signal arst : std_ulogic;
signal irst : std_ulogic;
signal vcc : std_ulogic;
signal tmsto : eth_tx_ahb_in_type;
signal tmsti : eth_tx_ahb_out_type;
signal rmsto : eth_rx_ahb_in_type;
signal rmsti : eth_rx_ahb_out_type;
signal macaddr : std_logic_vector(47 downto 0);
signal ahbmi : ahbc_mst_in_type;
signal ahbmo : ahbc_mst_out_type;
signal txi : host_tx_type;
signal txo : tx_host_type;
signal rxi : host_rx_type;
signal rxo : rx_host_type;
signal r, rin : reg_type;
attribute sync_set_reset : string;
attribute sync_set_reset of irst : signal is "true";
begin
macaddr(47 downto 4) <= macaddrt(47 downto 4);
macaddr(3 downto 0) <= macaddrt(3 downto 0) when edcl /= 2 else edcladdr;
--reset generators for transmitter and receiver
vcc <= '1';
arst <= testrst when (scanen = 1) and (testen = '1')
else rst and not r.ctrl.reset;
irst <= rst and not r.ctrl.reset;
comb : process(rst, irst, r, rmsti, tmsti, txo, rxo, psel, paddr, penable,
erdata, pwrite, pwdata, rxrdata, txrdata, mdio_i, phyrstaddr,
testen, testrst, macaddr) is
variable v : reg_type;
variable vpirq : std_ulogic;
variable vprdata : std_logic_vector(31 downto 0);
variable txvalid : std_ulogic;
variable vtxfi : tx_fifo_access_in_type;
variable vrxfi : fifo_access_in_type;
variable lengthav : std_ulogic;
variable txdone : std_ulogic;
variable txread : std_ulogic;
variable txrestart : std_ulogic;
variable rxstart : std_ulogic;
variable rxdone : std_ulogic;
variable vrxwrite : std_ulogic;
variable ovrunstop : std_ulogic;
--mdio
variable mdioindex : integer range 0 to 31;
variable mclk : std_ulogic;
--edcl
variable veri : edcl_ram_in_type;
variable swap : std_ulogic;
variable setmz : std_ulogic;
variable ipcrctmp : std_logic_vector(15 downto 0);
variable ipcrctmp2 : std_logic_vector(17 downto 0);
variable vrxenable : std_ulogic;
variable crctmp : std_ulogic;
variable vecnt : integer;
begin
v := r; vprdata := (others => '0'); vpirq := '0';
v.check := '0'; lengthav := r.rxdoneold;-- or r.usesizefield;
ovrunstop := '0';
vtxfi.datain := tmsti.data;
vtxfi.raddress := r.tfrpnt; vtxfi.write := '0';
vtxfi.waddress := r.tfwpnt; vtxfi.renable := '1';
vrxfi.datain := rxo.dataout;
vrxfi.write := '0'; vrxfi.waddress := r.rfwpnt;
vrxfi.renable := '1'; vrxenable := r.ctrl.rxen;
--synchronization
v.txdone(0) := txo.done;
v.txread(0) := txo.read;
v.txrestart(0) := txo.restart;
v.rxstart(0) := rxo.start;
v.rxdone(0) := rxo.done;
v.rxwrite(0) := rxo.write;
if nsync = 2 then
v.txdone(1) := r.txdone(0);
v.txread(1) := r.txread(0);
v.txrestart(1) := r.txrestart(0);
v.rxstart(1) := r.rxstart(0);
v.rxdone(1) := r.rxdone(0);
v.rxwrite(1) := r.rxwrite(0);
end if;
txdone := r.txdone(nsync) xor r.txdone(nsync-1);
txread := r.txreadack xor r.txread(nsync-1);
txrestart := r.txrestart(nsync) xor r.txrestart(nsync-1);
rxstart := r.rxstart(nsync) xor r.rxstart(nsync-1);
rxdone := r.rxdoneack xor r.rxdone(nsync-1);
vrxwrite := r.rxwriteack xor r.rxwrite(nsync-1);
if txdone = '1' then
v.txstatus := txo.status;
end if;
-------------------------------------------------------------------------------
-- HOST INTERFACE -------------------------------------------------------------
-------------------------------------------------------------------------------
--SLAVE INTERFACE
--write
if (psel and penable and pwrite) = '1' then
case paddr(5 downto 2) is
when "0000" => --ctrl reg
if rmii = 1 then
v.ctrl.speed := pwdata(7);
end if;
v.ctrl.reset := pwdata(6);
v.ctrl.prom := pwdata(5);
v.ctrl.full_duplex := pwdata(4);
v.ctrl.rx_irqen := pwdata(3);
v.ctrl.tx_irqen := pwdata(2);
v.ctrl.rxen := pwdata(1);
v.ctrl.txen := pwdata(0);
when "0001" => --status/int source reg
if pwdata(7) = '1' then v.status.invaddr := '0'; end if;
if pwdata(6) = '1' then v.status.toosmall := '0'; end if;
if pwdata(5) = '1' then v.status.txahberr := '0'; end if;
if pwdata(4) = '1' then v.status.rxahberr := '0'; end if;
if pwdata(3) = '1' then v.status.tx_int := '0'; end if;
if pwdata(2) = '1' then v.status.rx_int := '0'; end if;
if pwdata(1) = '1' then v.status.tx_err := '0'; end if;
if pwdata(0) = '1' then v.status.rx_err := '0'; end if;
when "0010" => --mac addr msb
v.mac_addr(47 downto 32) := pwdata(15 downto 0);
when "0011" => --mac addr lsb
v.mac_addr(31 downto 0) := pwdata(31 downto 0);
when "0100" => --mdio ctrl/status
if enable_mdio = 1 then
v.mdio_ctrl.data := pwdata(31 downto 16);
v.mdio_ctrl.phyadr := pwdata(15 downto 11);
v.mdio_ctrl.regadr := pwdata(10 downto 6);
if r.mdio_ctrl.busy = '0' then
v.mdio_ctrl.read := pwdata(1);
v.mdio_ctrl.write := pwdata(0);
v.mdio_ctrl.busy := pwdata(1) or pwdata(0);
end if;
end if;
when "0101" => --tx descriptor
v.txdesc := pwdata(31 downto 10);
v.txdsel := pwdata(9 downto 3);
when "0110" => --rx descriptor
v.rxdesc := pwdata(31 downto 10);
v.rxdsel := pwdata(9 downto 3);
when "0111" => --edcl ip
if (edcl /= 0) then
v.edclip := pwdata;
end if;
when others => null;
end case;
end if;
--read
case paddr(5 downto 2) is
when "0000" => --ctrl reg
if (edcl /= 0) then
vprdata(31) := '1';
vprdata(30 downto 28) := bufsize;
end if;
if rmii = 1 then
vprdata(7) := r.ctrl.speed;
end if;
vprdata(6) := r.ctrl.reset;
vprdata(5) := r.ctrl.prom;
vprdata(4) := r.ctrl.full_duplex;
vprdata(3) := r.ctrl.rx_irqen;
vprdata(2) := r.ctrl.tx_irqen;
vprdata(1) := r.ctrl.rxen;
vprdata(0) := r.ctrl.txen;
when "0001" => --status/int source reg
vprdata(5) := r.status.invaddr;
vprdata(4) := r.status.toosmall;
vprdata(5) := r.status.txahberr;
vprdata(4) := r.status.rxahberr;
vprdata(3) := r.status.tx_int;
vprdata(2) := r.status.rx_int;
vprdata(1) := r.status.tx_err;
vprdata(0) := r.status.rx_err;
when "0010" => --mac addr msb/mdio address
vprdata(15 downto 0) := r.mac_addr(47 downto 32);
when "0011" => --mac addr lsb
vprdata := r.mac_addr(31 downto 0);
when "0100" => --mdio ctrl/status
vprdata(31 downto 16) := r.mdio_ctrl.data;
vprdata(15 downto 11) := r.mdio_ctrl.phyadr;
vprdata(10 downto 6) := r.mdio_ctrl.regadr;
vprdata(3) := r.mdio_ctrl.busy;
vprdata(2) := r.mdio_ctrl.linkfail;
vprdata(1) := r.mdio_ctrl.read;
vprdata(0) := r.mdio_ctrl.write;
when "0101" => --tx descriptor
vprdata(31 downto 10) := r.txdesc;
vprdata(9 downto 3) := r.txdsel;
when "0110" => --rx descriptor
vprdata(31 downto 10) := r.rxdesc;
vprdata(9 downto 3) := r.rxdsel;
when "0111" => --edcl ip
if (edcl /= 0) then
vprdata := r.edclip;
end if;
when others => null;
end case;
--MASTER INTERFACE
v.txburstav := '0';
if (txfifosizev - r.tfcnt) >= txburstlen then
v.txburstav := '1';
end if;
--tx dma fsm
case r.txdstate is
when idle =>
v.txcnt := (others => '0');
if (edcl /= 0) then
v.tedcl := '0';
end if;
if (edcl /= 0) and (conv_integer(r.abufs) /= 0) then
v.txdstate := getlen;
v.tcnt := conv_std_logic_vector(10, bpbits);
elsif r.ctrl.txen = '1' then
v.txdstate := read_desc; v.tmsto.write := '0';
v.tmsto.addr := r.txdesc & r.txdsel & "000"; v.tmsto.req := '1';
end if;
if r.txirqgen = '1' then
vpirq := '1'; v.txirqgen := '0';
end if;
if txrestart = '1' then
v.txrestart(nsync) := r.txrestart(nsync-1);
v.tfcnt := (others => '0'); v.tfrpnt := (others => '0');
v.tfwpnt := (others => '0');
end if;
when read_desc =>
v.tmsto.write := '0'; v.txstatus := (others => '0');
v.tfwpnt := (others => '0'); v.tfrpnt := (others => '0');
v.tfcnt := (others => '0');
if tmsti.grant = '1' then
v.tmsto.addr := r.tmsto.addr + 4;
end if;
if tmsti.ready = '1' then
v.txcnt := r.txcnt + 1; v.tmsto.req := '0';
case r.txcnt(1 downto 0) is
when "00" =>
v.txlength := tmsti.data(10 downto 0);
v.txden := tmsti.data(11);
v.txwrap := tmsti.data(12);
v.txirq := tmsti.data(13);
v.ctrl.txen := tmsti.data(11);
when "01" =>
v.txaddr := tmsti.data(31 downto 2);
v.txdstate := check_desc;
when others => null;
end case;
end if;
when check_desc =>
v.txstart := '0';
v.txburstcnt := (others => '0');
if r.txden = '1' then
if (conv_integer(r.txlength) > maxsizetx) or
(conv_integer(r.txlength) = 0) then
v.txdstate := write_result; v.tmsto.req := '1';
v.tmsto.write := '1'; v.tmsto.addr := r.txdesc & r.txdsel & "000";
v.tmsto.data := (others => '0');
else
v.txdstate := req;
v.tmsto.addr := r.txaddr & "00"; v.txcnt(10 downto 0) := r.txlength;
end if;
else
v.txdstate := idle;
end if;
when req =>
if txrestart = '1' then
v.txdstate := idle; v.txstart := '0';
if (edcl /= 0) and (r.tedcl = '1') then
v.txdstate := idle;
end if;
elsif txdone = '1' then
v.txdstate := check_result;
v.tfcnt := (others => '0'); v.tfrpnt := (others => '0');
v.tfwpnt := (others => '0');
if (edcl /= 0) and (r.tedcl = '1') then
v.txdstate := etdone;
end if;
elsif conv_integer(r.txcnt) = 0 then
v.txdstate := check_result;
if (edcl /= 0) and (r.tedcl = '1') then
v.txdstate := etdone; v.txstart_sync := not r.txstart_sync;
end if;
elsif (r.txburstav = '1') or (r.tedcl = '1') then
v.tmsto.req := '1'; v.txdstate := fill_fifo;
end if;
v.txburstcnt := (others => '0');
when fill_fifo =>
v.txburstav := '0';
if tmsti.grant = '1' then
v.tmsto.addr := r.tmsto.addr + 4;
if ((conv_integer(r.txcnt) <= 8) and (tmsti.ready = '1')) or
((conv_integer(r.txcnt) <= 4) and (tmsti.ready = '0')) then
v.tmsto.req := '0';
end if;
v.txburstcnt := r.txburstcnt + 1;
if (conv_integer(r.txburstcnt) = burstlength-1) then
v.tmsto.req := '0';
end if;
end if;
if (tmsti.ready = '1') or ((edcl /= 0) and (r.tedcl and tmsti.error) = '1') then
v.tfwpnt := r.tfwpnt + 1; v.tfcnt := r.tfcnt + 1; vtxfi.write := '1';
if r.tmsto.req = '0' then
v.txdstate := req;
if (r.txstart = '0') and not ((edcl /= 0) and (r.tedcl = '1')) then
v.txstart := '1'; v.txstart_sync := not r.txstart_sync;
end if;
end if;
if conv_integer(r.txcnt) > 3 then
v.txcnt := r.txcnt - 4;
else
v.txcnt := (others => '0');
end if;
end if;
when check_result =>
if txdone = '1' then
v.txdstate := write_result; v.tmsto.req := '1'; v.txstart := '0';
v.tmsto.write := '1'; v.tmsto.addr := r.txdesc & r.txdsel & "000";
v.tmsto.data(31 downto 16) := (others => '0');
v.tmsto.data(15 downto 14) := v.txstatus;
v.tmsto.data(13 downto 0) := (others => '0');
v.txdone(nsync) := r.txdone(nsync-1);
elsif txrestart = '1' then
v.txdstate := idle; v.txstart := '0';
end if;
when write_result =>
if tmsti.grant = '1' then
v.tmsto.req := '0'; v.tmsto.addr := r.tmsto.addr + 4;
end if;
if tmsti.ready = '1' then
v.txdstate := idle;
v.txirqgen := r.ctrl.tx_irqen and r.txirq;
if r.txwrap = '0' then v.txdsel := r.txdsel + 1;
else v.txdsel := (others => '0'); end if;
if conv_integer(r.txstatus) = 0 then v.status.tx_int := '1';
else v.status.tx_err := '1'; end if;
end if;
when ahberror =>
v.tfcnt := (others => '0'); v.tfwpnt := (others => '0');
v.tfrpnt := (others => '0');
v.status.txahberr := '1'; v.ctrl.txen := '0';
if not ((edcl /= 0) and (r.tedcl = '1')) then
if r.txstart = '1' then
if txdone = '1' then
v.txdstate := idle; v.txdone(nsync) := r.txdone(nsync-1);
end if;
else
v.txdstate := idle;
end if;
else
v.txdstate := idle;
v.abufs := r.abufs - 1; v.tpnt := r.tpnt + 1;
end if;
when others =>
null;
end case;
--tx fifo read
v.txdataav := '0';
if conv_integer(r.tfcnt) /= 0 then
v.txdataav := '1';
end if;
if txread = '1' then
v.txreadack := not r.txreadack;
if r.txdataav = '1' then
if conv_integer(r.tfcnt) < 2 then
v.txdataav := '0';
end if;
v.txvalid := '1';
v.tfcnt := v.tfcnt - 1; v.tfrpnt := r.tfrpnt + 1;
else
v.txvalid := '0';
end if;
v.txdata := txrdata;
end if;
v.rxburstav := '0';
if r.rfcnt >= rxburstlen then
v.rxburstav := '1';
end if;
--rx dma fsm
case r.rxdstate is
when idle =>
v.rmsto.req := '0'; v.rmsto.write := '0'; v.addrnok := '0';
v.rxcnt := (others => '0'); v.rxdoneold := '0';
v.ctrlpkt := '0'; v.bcast := '0'; v.edclactive := '0';
if r.ctrl.rxen = '1' then
v.rxdstate := read_desc; v.rmsto.req := '1';
v.rmsto.addr := r.rxdesc & r.rxdsel & "000";
elsif rxstart = '1' then
v.rxstart(nsync) := r.rxstart(nsync-1);
v.rxdstate := discard;
end if;
when read_desc =>
v.rxstatus := (others => '0');
if rmsti.grant = '1' then
v.rmsto.addr := r.rmsto.addr + 4;
end if;
if rmsti.ready = '1' then
v.rxcnt := r.rxcnt + 1; v.rmsto.req := '0';
case r.rxcnt(1 downto 0) is
when "00" =>
v.ctrl.rxen := rmsti.data(11);
v.rxden := rmsti.data(11);
v.rxwrap := rmsti.data(12);
v.rxirq := rmsti.data(13);
when "01" =>
v.rxaddr := rmsti.data(31 downto 2);
v.rxdstate := check_desc;
when others =>
null;
end case;
end if;
if rmsti.error = '1' then
v.rmsto.req := '0'; v.rxdstate := idle;
v.status.rxahberr := '1'; v.ctrl.rxen := '0';
end if;
when check_desc =>
v.rxcnt := (others => '0'); v.usesizefield := '0'; v.rmsto.write := '1';
if r.rxden = '1' then
if rxstart = '1' then
v.rxdstate := read_req; v.rxstart(nsync) := r.rxstart(nsync-1);
end if;
else
v.rxdstate := idle;
end if;
v.rmsto.addr := r.rxaddr & "00";
when read_req =>
if r.edclactive = '1' then
v.rxdstate := discard;
elsif (r.rxdoneold and r.rxstatus(3)) = '1' then
v.rxdstate := write_status;
v.rfcnt := (others => '0'); v.rfwpnt := (others => '0');
v.rfrpnt := (others => '0'); v.writeok := '1';
v.rxbytecount := (others => '0'); v.rxlength := (others => '0');
elsif (r.addrnok or r.ctrlpkt) = '1' then
v.rxdstate := discard; v.status.invaddr := '1';
elsif ((r.rxdoneold = '1') and r.rxcnt >= r.rxlength) then
if r.gotframe = '1' then
v.rxdstate := write_status;
else
v.rxdstate := discard; v.status.toosmall := '1';
end if;
elsif (r.rxburstav or r.rxdoneold) = '1' then
v.rmsto.req := '1'; v.rxdstate := read_fifo;
v.rfrpnt := r.rfrpnt + 1; v.rfcnt := r.rfcnt - 1;
end if;
v.rxburstcnt := (others => '0'); v.rmsto.data := rxrdata;
when read_fifo =>
v.rxburstav := '0';
if rmsti.grant = '1' then
v.rmsto.addr := r.rmsto.addr + 4;
if (lengthav = '1') then
if ((conv_integer(r.rxcnt) >=
(conv_integer(r.rxlength) - 8)) and (rmsti.ready = '1')) or
((conv_integer(r.rxcnt) >=
(conv_integer(r.rxlength) - 4)) and (rmsti.ready = '0')) then
v.rmsto.req := '0';
end if;
end if;
v.rxburstcnt := r.rxburstcnt + 1;
if (conv_integer(r.rxburstcnt) = burstlength-1) then
v.rmsto.req := '0';
end if;
end if;
if rmsti.ready = '1' then
v.rmsto.data := rxrdata;
v.rxcnt := r.rxcnt + 4;
if r.rmsto.req = '0' then
v.rxdstate := read_req;
else
v.rfcnt := r.rfcnt - 1; v.rfrpnt := r.rfrpnt + 1;
end if;
v.check := '1'; v.checkdata := r.rmsto.data;
end if;
if rmsti.error = '1' then
v.rmsto.req := '0'; v.rxdstate := discard;
v.rxcnt := r.rxcnt + 4;
v.status.rxahberr := '1'; v.ctrl.rxen := '0';
end if;
when write_status =>
v.rmsto.req := '1'; v.rmsto.addr := r.rxdesc & r.rxdsel & "000";
v.rxdstate := write_status2;
v.rmsto.data := X"000" & '0' & r.rxstatus & "000" & r.rxlength;
when write_status2 =>
if rmsti.grant = '1' then
v.rmsto.req := '0'; v.rmsto.addr := r.rmsto.addr + 4;
end if;
if rmsti.ready = '1' then
if (r.rxstatus(4) or not r.rxstatus(3)) = '1' then
v.rxdstate := discard;
else
v.rxdstate := idle;
end if;
if (r.ctrl.rx_irqen and r.rxirq) = '1' then
vpirq := '1';
end if;
if conv_integer(r.rxstatus) = 0 then v.status.rx_int := '1';
else v.status.rx_err := '1'; end if;
if r.rxwrap = '1' then
v.rxdsel := (others => '0');
else
v.rxdsel := r.rxdsel + 1;
end if;
end if;
if rmsti.error = '1' then
v.rmsto.req := '0'; v.rxdstate := idle;
v.status.rxahberr := '1'; v.ctrl.rxen := '0';
end if;
when discard =>
if (r.rxdoneold = '0') or ((r.rxdoneold = '1') and
(conv_integer(r.rxcnt) < conv_integer(r.rxbytecount))) then
if conv_integer(r.rfcnt) /= 0 then
v.rfrpnt := r.rfrpnt + 1; v.rfcnt := r.rfcnt - 1;
v.rxcnt := r.rxcnt + 4;
end if;
elsif (r.rxdoneold = '1') then
v.rxdstate := idle; v.ctrlpkt := '0';
end if;
when others =>
null;
end case;
--rx address/type check
if r.check = '1' and r.rxcnt(10 downto 5) = "000000" then
case r.rxcnt(4 downto 2) is
when "001" =>
if r.checkdata /= broadcast(47 downto 16) and
r.checkdata /= r.mac_addr(47 downto 16) and
(not r.ctrl.prom) = '1'then
v.addrnok := '1';
elsif r.checkdata = broadcast(47 downto 16) then
v.bcast := '1';
end if;
when "010" =>
if r.checkdata(31 downto 16) /= broadcast(15 downto 0) and
r.checkdata(31 downto 16) /= r.mac_addr(15 downto 0) and
(not r.ctrl.prom) = '1' then
v.addrnok := '1';
elsif (r.bcast = '0') and
(r.checkdata(31 downto 16) = broadcast(15 downto 0)) then
v.addrnok := '1';
end if;
when "011" =>
null;
when "100" =>
if r.checkdata(31 downto 16) = ctrlopcode then v.ctrlpkt := '1'; end if;
when others =>
null;
end case;
end if;
--rx packet done
if (rxdone and not rxstart) = '1' then
v.gotframe := rxo.gotframe; v.rxbytecount := rxo.byte_count;
v.rxstatus(3 downto 0) := rxo.status;
if (rxo.lentype > maxsizerx) or (rxo.status /= "0000") then
v.rxlength := rxo.byte_count;
else
v.rxlength := rxo.lentype(10 downto 0);
if (rxo.lentype(10 downto 0) > minpload) and
(rxo.lentype(10 downto 0) /= rxo.byte_count) then
if rxo.status(2 downto 0) = "000" then
v.rxstatus(4) := '1'; v.rxlength := rxo.byte_count;
v.usesizefield := '0';
end if;
elsif (rxo.lentype(10 downto 0) <= minpload) and
(rxo.byte_count /= minpload) then
if rxo.status(2 downto 0) = "000" then
v.rxstatus(4) := '1'; v.rxlength := rxo.byte_count;
v.usesizefield := '0';
end if;
end if;
end if;
v.rxdoneold := '1';
--if ((not rxo.status(3)) or (rxo.status(3) and ovrunstop)) = '1' then
v.rxdoneack := not r.rxdoneack;
--end if;
--if ovrunstop = '1' then
-- v.rxbytecount := (others => '0');
--end if;
end if;
--rx fifo write
if vrxwrite = '1' then
v.rxwriteack := not r.rxwriteack;
if (not r.rfcnt(fabits)) = '1' then
v.rfwpnt := r.rfwpnt + 1; v.rfcnt := v.rfcnt + 1; v.writeok := '1';
vrxfi.write := '1';
else
v.writeok := '0';
end if;
end if;
--must be placed here because it uses variable
vrxfi.raddress := v.rfrpnt;
-------------------------------------------------------------------------------
-- MDIO INTERFACE -------------------------------------------------------------
-------------------------------------------------------------------------------
--mdio commands
if enable_mdio = 1 then
mclk := r.mdioclk and not r.mdioclkold;
v.mdioclkold := r.mdioclk;
if r.mdccnt = "00000000" then
v.mdccnt := divisor;
v.mdioclk := not r.mdioclk;
else
v.mdccnt := r.mdccnt - 1;
end if;
mdioindex := conv_integer(r.cnt); v.mdioi := mdio_i;
if mclk = '1' then
case r.mdio_state is
when idle =>
v.cnt := (others => '0');
if r.mdio_ctrl.busy = '1' then
v.mdio_ctrl.linkfail := '0';
if r.mdio_ctrl.read = '1' then
v.mdio_ctrl.write := '0';
end if;
v.mdio_state := preamble; v.mdioo := '1';
if OEPOL = 0 then v.mdioen := '0'; else v.mdioen := '1'; end if;
end if;
when preamble =>
v.cnt := r.cnt + 1;
if r.cnt = "11111" then
v.mdioo := '0'; v.mdio_state := startst;
end if;
when startst =>
v.mdioo := '1'; v.mdio_state := op; v.cnt := (others => '0');
when op =>
v.mdio_state := op2;
if r.mdio_ctrl.read = '1' then v.mdioo := '1';
else v.mdioo := '0'; end if;
when op2 =>
v.mdioo := not r.mdioo; v.mdio_state := phyadr;
v.cnt := (others => '0');
when phyadr =>
v.cnt := r.cnt + 1;
case mdioindex is
when 0 => v.mdioo := r.mdio_ctrl.phyadr(4);
when 1 => v.mdioo := r.mdio_ctrl.phyadr(3);
when 2 => v.mdioo := r.mdio_ctrl.phyadr(2);
when 3 => v.mdioo := r.mdio_ctrl.phyadr(1);
when 4 => v.mdioo := r.mdio_ctrl.phyadr(0);
v.mdio_state := regadr; v.cnt := (others => '0');
when others => null;
end case;
when regadr =>
v.cnt := r.cnt + 1;
case mdioindex is
when 0 => v.mdioo := r.mdio_ctrl.regadr(4);
when 1 => v.mdioo := r.mdio_ctrl.regadr(3);
when 2 => v.mdioo := r.mdio_ctrl.regadr(2);
when 3 => v.mdioo := r.mdio_ctrl.regadr(1);
when 4 => v.mdioo := r.mdio_ctrl.regadr(0);
v.mdio_state := ta; v.cnt := (others => '0');
when others => null;
end case;
when ta =>
v.mdio_state := ta2;
if r.mdio_ctrl.read = '1' then
if OEPOL = 0 then v.mdioen := '1'; else v.mdioen := '0'; end if;
else v.mdioo := '1'; end if;
when ta2 =>
v.cnt := "01111"; v.mdio_state := ta3;
if r.mdio_ctrl.write = '1' then v.mdioo := '0'; v.mdio_state := data; end if;
when ta3 =>
v.mdio_state := data;
if r.mdioi /= '0' then
v.mdio_ctrl.linkfail := '1';
end if;
when data =>
v.cnt := r.cnt - 1;
if r.mdio_ctrl.read = '1' then
v.mdio_ctrl.data(mdioindex) := r.mdioi;
else
v.mdioo := r.mdio_ctrl.data(mdioindex);
end if;
if r.cnt = "00000" then
v.mdio_state := dataend;
end if;
when dataend =>
v.mdio_ctrl.busy := '0'; v.mdio_ctrl.read := '0';
v.mdio_ctrl.write := '0'; v.mdio_state := idle;
if OEPOL = 0 then v.mdioen := '1'; else v.mdioen := '0'; end if;
when others =>
null;
end case;
end if;
end if;
-------------------------------------------------------------------------------
-- EDCL -----------------------------------------------------------------------
-------------------------------------------------------------------------------
if (edcl /= 0) then
veri.renable := '1'; veri.writem := '0'; veri.writel := '0';
veri.waddressm := r.rpnt & r.rcntm; veri.waddressl := r.rpnt & r.rcntl;
swap := '0'; vrxenable := '1'; vecnt := conv_integer(r.ecnt); setmz := '0';
veri.datain := rxo.dataout;
if vrxwrite = '1' then
v.rxwriteack := not r.rxwriteack;
end if;
--edcl receiver
case r.edclrstate is
when idle =>
v.edclbcast := '0';
if rxstart = '1' then
v.edclrstate := wrda; v.edclactive := '0';
v.rcntm := conv_std_logic_vector(2, bpbits);
v.rcntl := conv_std_logic_vector(1, bpbits);
end if;
when wrda =>
if vrxwrite = '1' then
v.edclrstate := wrdsa;
veri.writem := '1'; veri.writel := '1';
swap := '1';
v.rcntm := r.rcntm - 2; v.rcntl := r.rcntl + 1;
if (macaddr(47 downto 16) /= rxo.dataout) and
(X"FFFFFFFF" /= rxo.dataout) then
v.edclrstate := spill;
elsif (X"FFFFFFFF" = rxo.dataout) then
v.edclbcast := '1';
end if;
if conv_integer(r.abufs) = wsz then
v.edclrstate := spill;
end if;
end if;
if (rxdone and not rxstart) = '1' then
v.edclrstate := idle;
end if;
when wrdsa =>
if vrxwrite = '1' then
v.edclrstate := wrsa; swap := '1';
veri.writem := '1'; veri.writel := '1';
v.rcntm := r.rcntm + 1; v.rcntl := r.rcntl - 2;
if (macaddr(15 downto 0) /= rxo.dataout(31 downto 16)) and
(X"FFFF" /= rxo.dataout(31 downto 16)) then
v.edclrstate := spill;
elsif (X"FFFF" = rxo.dataout(31 downto 16)) then
v.edclbcast := r.edclbcast;
end if;
end if;
if (rxdone and not rxstart) = '1' then
v.edclrstate := idle;
end if;
when wrsa =>
if vrxwrite = '1' then
veri.writem := '1'; veri.writel := '1';
v.edclrstate := wrtype; swap := '1';
v.rcntm := r.rcntm + 2; v.rcntl := r.rcntl + 3;
end if;
if (rxdone and not rxstart) = '1' then
v.edclrstate := idle;
end if;
when wrtype =>
if vrxwrite = '1' then
veri.writem := '1'; veri.writel := '1';
v.rcntm := r.rcntm + 1; v.rcntl := r.rcntl + 1;
if X"0800" = rxo.dataout(31 downto 16) and (r.edclbcast = '0') then
v.edclrstate := ip;
elsif X"0806" = rxo.dataout(31 downto 16) and (r.edclbcast = '1') then
v.edclrstate := arp;
else
v.edclrstate := spill;
end if;
end if;
v.ecnt := (others => '0'); v.ipcrc := (others => '0');
if (rxdone and not rxstart) = '1' then
v.edclrstate := idle;
end if;
when ip =>
if vrxwrite = '1' then
v.ecnt := r.ecnt + 1;
veri.writem := '1'; veri.writel := '1';
case vecnt is
when 0 =>
v.ipcrc :=
crcadder(not rxo.dataout(31 downto 16), r.ipcrc);
v.rcntm := r.rcntm + 1; v.rcntl := r.rcntl + 1;
when 1 =>
v.rcntm := r.rcntm + 1; v.rcntl := r.rcntl + 2;
when 2 =>
v.ipcrc :=
crcadder(not rxo.dataout(31 downto 16), r.ipcrc);
v.rcntm := r.rcntm + 2; v.rcntl := r.rcntl - 1;
when 3 =>
v.rcntm := r.rcntm - 1; v.rcntl := r.rcntl + 2;
when 4 =>
v.udpsrc := rxo.dataout(15 downto 0);
v.rcntm := r.rcntm + 2; v.rcntl := r.rcntl + 1;
when 5 =>
setmz := '1';
v.rcntm := r.rcntm + 1; v.rcntl := r.rcntl + 1;
when 6 =>
v.rcntm := r.rcntm + 1; v.rcntl := r.rcntl + 1;
when 7 =>
v.rcntm := r.rcntm + 1; v.rcntl := r.rcntl + 1;
if (rxo.dataout(31 downto 18) = r.seq) then
v.seq := r.seq + 1; v.nak := '0';
else
v.nak := '1';
veri.datain(31 downto 18) := r.seq;
end if;
veri.datain(17) := v.nak; v.ewr := rxo.dataout(17);
if (rxo.dataout(17) or v.nak) = '1' then
veri.datain(16 downto 7) := (others => '0');
end if;
v.oplen := rxo.dataout(16 downto 7);
v.applength := "000000" & veri.datain(16 downto 7);
v.ipcrc :=
crcadder(v.applength + 38, r.ipcrc);
v.write(conv_integer(r.rpnt)) := rxo.dataout(17);
when 8 =>
ipcrctmp := (others => '0');
ipcrctmp(1 downto 0) := r.ipcrc(17 downto 16);
ipcrctmp2 := "00" & r.ipcrc(15 downto 0);
v.ipcrc :=
crcadder(ipcrctmp, ipcrctmp2);
v.rcntm := r.rcntm + 1; v.rcntl := r.rcntl + 1;
v.edclrstate := ipdata;
when others =>
null;
end case;
end if;
if (rxdone and not rxstart) = '1' then
v.edclrstate := idle;
end if;
when ipdata =>
if (vrxwrite and r.ewr and not r.nak) = '1' and
(r.rcntm /= ebufmax) then
veri.writem := '1'; veri.writel := '1';
v.rcntm := r.rcntm + 1; v.rcntl := r.rcntl + 1;
end if;
if rxdone = '1' then
v.edclrstate := ipcrc; v.rcntm := conv_std_logic_vector(6, bpbits);
ipcrctmp := (others => '0');
ipcrctmp(1 downto 0) := r.ipcrc(17 downto 16);
ipcrctmp2 := "00" & r.ipcrc(15 downto 0);
v.ipcrc := crcadder(ipcrctmp, ipcrctmp2);
if conv_integer(v.rxstatus(3 downto 0)) /= 0 then
v.edclrstate := idle;
end if;
end if;
when ipcrc =>
veri.writem := '1'; veri.datain(31 downto 16) := not r.ipcrc(15 downto 0);
v.edclrstate := udp; v.rcntm := conv_std_logic_vector(9, bpbits);
v.rcntl := conv_std_logic_vector(9, bpbits);
when udp =>
veri.writem := '1'; veri.writel := '1';
v.edclrstate := iplength;
veri.datain(31 downto 16) := r.udpsrc;
veri.datain(15 downto 0) := r.applength + 18;
v.rcntm := conv_std_logic_vector(4, bpbits);
when iplength =>
veri.writem := '1';
veri.datain(31 downto 16) := r.applength + 38;
v.edclrstate := oplength;
v.rcntm := conv_std_logic_vector(10, bpbits);
v.rcntl := conv_std_logic_vector(10, bpbits);
when oplength =>
if rxstart = '0' then
v.abufs := r.abufs + 1; v.rpnt := r.rpnt + 1;
veri.writel := '1'; veri.writem := '1';
end if;
v.edclrstate := idle;
veri.datain(31 downto 0) := (others => '0');
veri.datain(15 downto 0) := "00000" & r.nak & r.oplen;
when arp =>
if vrxwrite = '1' then
v.ecnt := r.ecnt + 1;
veri.writem := '1'; veri.writel := '1';
case vecnt is
when 0 =>
v.rcntm := r.rcntm + 4;
when 1 =>
swap := '1'; veri.writel := '0';
v.rcntm := r.rcntm + 1; v.rcntl := r.rcntl + 4;
when 2 =>
swap := '1';
v.rcntm := r.rcntm + 1; v.rcntl := r.rcntl + 1;
when 3 =>
swap := '1';
v.rcntm := r.rcntm - 4; v.rcntl := r.rcntl - 4;
when 4 =>
veri.datain := macaddr(31 downto 16) & macaddr(47 downto 32);
v.rcntm := r.rcntm + 1; v.rcntl := r.rcntl + 1;
when 5 =>
v.rcntl := r.rcntl + 1;
veri.datain(31 downto 16) := rxo.dataout(15 downto 0);
veri.datain(15 downto 0) := macaddr(15 downto 0);
if rxo.dataout(15 downto 0) /= r.edclip(31 downto 16) then
v.edclrstate := spill;
end if;
when 6 =>
swap := '1'; veri.writem := '0';
v.rcntm := conv_std_logic_vector(5, bpbits);
v.rcntl := conv_std_logic_vector(1, bpbits);
if rxo.dataout(31 downto 16) /= r.edclip(15 downto 0) then
v.edclrstate := spill;
else
v.edclactive := '1';
end if;
when 7 =>
veri.writem := '0';
veri.datain(15 downto 0) := macaddr(47 downto 32);
v.rcntl := r.rcntl + 1;
v.rcntm := conv_std_logic_vector(2, bpbits);
when 8 =>
v.edclrstate := arpop;
veri.datain := macaddr(31 downto 0);
v.rcntm := conv_std_logic_vector(5, bpbits);
when others =>
null;
end case;
end if;
if (rxdone and not rxstart) = '1' then
v.edclrstate := idle;
end if;
when arpop =>
veri.writem := '1'; veri.datain(31 downto 16) := X"0002";
if (rxdone and not rxstart) = '1' then
v.edclrstate := idle;
if conv_integer(v.rxstatus) = 0 and (rxo.gotframe = '1') then
v.abufs := r.abufs + 1; v.rpnt := r.rpnt + 1;
end if;
end if;
when spill =>
if (rxdone and not rxstart) = '1' then
v.edclrstate := idle;
end if;
end case;
--edcl transmitter
case r.txdstate is
when getlen =>
v.tcnt := r.tcnt + 1;
if conv_integer(r.tcnt) = 10 then
v.txlength := '0' & erdata(9 downto 0);
v.tnak := erdata(10);
v.txcnt := v.txlength;
if (r.write(conv_integer(r.tpnt)) or v.tnak) = '1' then
v.txlength := (others => '0');
end if;
end if;
if conv_integer(r.tcnt) = 11 then
v.txdstate := readhdr;
v.tcnt := (others => '0');
end if;
when readhdr =>
v.tcnt := r.tcnt + 1; vtxfi.write := '1';
v.tfwpnt := r.tfwpnt + 1; v.tfcnt := v.tfcnt + 1;
vtxfi.datain := erdata;
if conv_integer(r.tcnt) = 12 then
v.txaddr := erdata(31 downto 2);
end if;
if conv_integer(r.tcnt) = 3 then
if erdata(31 downto 16) = X"0806" then
v.tarp := '1'; v.txlength := conv_std_logic_vector(42, 11);
else
v.tarp := '0'; v.txlength := r.txlength + 52;
end if;
end if;
if r.tarp = '0' then
if conv_integer(r.tcnt) = 12 then
v.txdstate := start;
end if;
else
if conv_integer(r.tcnt) = 10 then
v.txdstate := start;
end if;
end if;
if (txrestart or txdone) = '1' then
v.txdstate := etdone;
end if;
when start =>
v.tmsto.addr := r.txaddr & "00";
v.tmsto.write := r.write(conv_integer(r.tpnt));
if (conv_integer(r.txcnt) = 0) or (r.tarp or r.tnak) = '1' then
v.tmsto.req := '0'; v.txdstate := etdone;
v.txstart_sync := not r.txstart_sync;
elsif r.write(conv_integer(r.tpnt)) = '0' then
v.txdstate := req; v.tedcl := '1';
else
v.txstart_sync := not r.txstart_sync;
v.txdstate := wrbus; v.tmsto.req := '1'; v.tedcl := '1';
v.tmsto.data := erdata; v.tcnt := r.tcnt + 1;
end if;
if (txrestart or txdone) = '1' then
v.txdstate := etdone;
end if;
when wrbus =>
if tmsti.grant = '1' then
v.tmsto.addr := r.tmsto.addr + 4;
if ((conv_integer(r.txcnt) <= 4) and (tmsti.ready = '0')) or
((conv_integer(r.txcnt) <= 8) and (tmsti.ready = '1')) then
v.tmsto.req := '0';
end if;
end if;
if (tmsti.ready or tmsti.error) = '1' then
v.tmsto.data := erdata; v.tcnt := r.tcnt + 1;
v.txcnt := r.txcnt - 4;
if r.tmsto.req = '0' then
v.txdstate := etdone;
end if;
end if;
if tmsti.retry = '1' then
v.tmsto.addr := r.tmsto.addr - 4; v.tmsto.req := '1';
end if;
--if (txrestart or txdone) = '1' then
-- v.txdstate := etdone; v.tmsto.req := '0';
--end if;
when etdone =>
if txdone = '1' then
v.txdstate := idle; v.txdone(nsync) := r.txdone(nsync-1);
v.abufs := v.abufs - 1; v.tpnt := r.tpnt + 1;
v.tfcnt := (others => '0'); v.tfrpnt := (others => '0');
v.tfwpnt := (others => '0');
elsif txrestart = '1' then
v.txdstate := idle;
end if;
when others =>
null;
end case;
if swap = '1' then
veri.datain(31 downto 16) := rxo.dataout(15 downto 0);
veri.datain(15 downto 0) := rxo.dataout(31 downto 16);
end if;
if setmz = '1' then
veri.datain(31 downto 16) := (others => '0');
end if;
veri.raddress := r.tpnt & v.tcnt;
end if;
--edcl duplex mode read
if (rmii = 1) or (edcl /= 0) then
--edcl, gbit link mode check
case r.duplexstate is
when start =>
v.mdio_ctrl.regadr := r.regaddr;
v.mdio_ctrl.busy := '1'; v.duplexstate := waitop;
if (r.phywr or r.rstphy) = '1' then
v.mdio_ctrl.write := '1';
else
v.mdio_ctrl.read := '1';
end if;
if r.rstphy = '1' then
v.mdio_ctrl.data := X"9000";
end if;
when waitop =>
if r.mdio_ctrl.busy = '0' then
if r.mdio_ctrl.linkfail = '1' then
v.duplexstate := start;
elsif r.rstphy = '1' then
v.duplexstate := start; v.rstphy := '0';
else
v.duplexstate := nextop;
end if;
end if;
when nextop =>
case r.regaddr is
when "00000" =>
if r.mdio_ctrl.data(15) = '1' then --rst not finished
v.duplexstate := start;
elsif (r.phywr and not r.rstaneg) = '1' then --forced to 10 Mbit HD
v.duplexstate := selmode;
elsif r.mdio_ctrl.data(12) = '0' then --no auto neg
v.duplexstate := start; v.phywr := '1';
v.mdio_ctrl.data := (others => '0');
else
v.duplexstate := start; v.regaddr := "00001";
end if;
if r.rstaneg = '1' then
v.phywr := '0';
end if;
when "00001" =>
v.ext := r.mdio_ctrl.data(8); --extended status register
v.extcap := r.mdio_ctrl.data(1); --extended register capabilities
v.duplexstate := start;
if r.mdio_ctrl.data(0) = '0' then
--no extended register capabilites, unable to read aneg config
--forcing 10 Mbit
v.duplexstate := start; v.phywr := '1';
v.mdio_ctrl.data := (others => '0');
v.regaddr := (others => '0');
elsif (r.mdio_ctrl.data(8) and not r.rstaneg) = '1' then
--phy gbit capable, disable gbit
v.regaddr := "01001";
elsif r.mdio_ctrl.data(5) = '1' then --auto neg completed
v.regaddr := "00100";
end if;
when "00100" =>
v.duplexstate := start; v.regaddr := "00101";
v.capbil(4 downto 0) := r.mdio_ctrl.data(9 downto 5);
when "00101" =>
v.duplexstate := selmode;
v.capbil(4 downto 0) :=
r.capbil(4 downto 0) and r.mdio_ctrl.data(9 downto 5);
when "01001" =>
if r.phywr = '0' then
v.duplexstate := start; v.phywr := '1';
v.mdio_ctrl.data(9 downto 8) := (others => '0');
else
v.regaddr := "00000";
v.duplexstate := start; v.phywr := '1';
v.mdio_ctrl.data := X"3300"; v.rstaneg := '1';
end if;
when others =>
null;
end case;
when selmode =>
v.duplexstate := done;
if r.phywr = '1' then
v.ctrl.full_duplex := '0'; v.ctrl.speed := '0';
else
sel_op_mode(r.capbil, v.ctrl.speed, v.ctrl.full_duplex);
end if;
when done =>
null;
end case;
end if;
--transmitter retry
if tmsti.retry = '1' then
v.tmsto.req := '1'; v.tmsto.addr := r.tmsto.addr - 4;
v.txburstcnt := r.txburstcnt - 1;
end if;
--transmitter AHB error
if tmsti.error = '1' and (not ((edcl /= 0) and (r.tedcl = '1'))) then
v.tmsto.req := '0'; v.txdstate := ahberror;
end if;
--receiver retry
if rmsti.retry = '1' then
v.rmsto.req := '1'; v.rmsto.addr := r.rmsto.addr - 4;
v.rxburstcnt := r.rxburstcnt - 1;
end if;
------------------------------------------------------------------------------
-- RESET ----------------------------------------------------------------------
-------------------------------------------------------------------------------
if irst = '0' then
v.txdstate := idle; v.rxdstate := idle; v.rfrpnt := (others => '0');
v.tmsto.req := '0'; v.tmsto.req := '0'; v.rfwpnt := (others => '0');
v.rfcnt := (others => '0'); v.mdio_ctrl.read := '0';
v.mdio_ctrl.write := '0'; v.ctrl.txen := '0';
v.mdio_ctrl.busy := '0'; v.txirqgen := '0'; v.ctrl.rxen := '0';
v.mdio_ctrl.data := (others => '0');
v.mdio_ctrl.regadr := (others => '0');
v.txdsel := (others => '0'); v.txstart_sync := '0';
v.txread := (others => '0'); v.txrestart := (others => '0');
v.txdone := (others => '0'); v.txreadack := '0';
v.rxdsel := (others => '0'); v.rxdone := (others => '0');
v.rxdoneold := '0'; v.rxdoneack := '0'; v.rxwriteack := '0';
v.rxstart := (others => '0'); v.rxwrite := (others => '0');
v.mdio_ctrl.linkfail := '1'; v.ctrl.reset := '0';
v.status.invaddr := '0'; v.status.toosmall := '0';
v.ctrl.full_duplex := '0'; v.writeok := '0';
if (enable_mdio = 1) then
v.mdccnt := (others => '0'); v.mdioclk := '0';
v.mdio_state := idle;
if OEPOL = 0 then v.mdioen := '1'; else v.mdioen := '0'; end if;
end if;
if (edcl /= 0) then
v.tpnt := (others => '0'); v.rpnt := (others => '0');
v.tcnt := (others => '0'); v.edclactive := '0';
v.tarp := '0'; v.abufs := (others => '0');
v.edclrstate := idle;
end if;
if (rmii = 1) then
v.ctrl.speed := '1';
end if;
v.ctrl.tx_irqen := '0';
v.ctrl.rx_irqen := '0';
v.ctrl.prom := '0';
end if;
if edcl = 0 then
v.edclrstate := idle; v.edclactive := '0'; v.nak := '0'; v.ewr := '0';
v.write := (others => '0'); v.seq := (others => '0'); v.abufs := (others => '0');
v.tpnt := (others => '0'); v.rpnt := (others => '0'); v.tcnt := (others => '0');
v.rcntm := (others => '0'); v.rcntl := (others => '0'); v.ipcrc := (others => '0');
v.applength := (others => '0'); v.oplen := (others => '0');
v.udpsrc := (others => '0'); v.ecnt := (others => '0'); v.tarp := '0';
v.tnak := '0'; v.tedcl := '0'; v.edclbcast := '0';
end if;
--some parts of edcl are only affected by hw reset
if rst = '0' then
v.edclip := conv_std_logic_vector(ipaddrh, 16) &
conv_std_logic_vector(ipaddrl, 16);
if edcl = 2 then v.edclip(3 downto 0) := edcladdr; end if;
v.duplexstate := start; v.regaddr := (others => '0');
v.phywr := '0'; v.rstphy := '1'; v.rstaneg := '0';
if phyrstadr /= 32 then
v.mdio_ctrl.phyadr := conv_std_logic_vector(phyrstadr, 5);
else
v.mdio_ctrl.phyadr := phyrstaddr;
end if;
v.seq := (others => '0');
end if;
-------------------------------------------------------------------------------
-- SIGNAL ASSIGNMENTS ---------------------------------------------------------
-------------------------------------------------------------------------------
rin <= v;
prdata <= vprdata;
irq <= vpirq;
--rx ahb fifo
rxrenable <= vrxfi.renable;
rxraddress(10 downto fabits) <= (others => '0');
rxraddress(fabits-1 downto 0) <= vrxfi.raddress;
rxwrite <= vrxfi.write;
rxwdata <= vrxfi.datain;
rxwaddress(10 downto fabits) <= (others => '0');
rxwaddress(fabits-1 downto 0) <= vrxfi.waddress;
--tx ahb fifo
txrenable <= vtxfi.renable;
txraddress(10 downto txfabits) <= (others => '0');
txraddress(txfabits-1 downto 0) <= vtxfi.raddress;
txwrite <= vtxfi.write;
txwdata <= vtxfi.datain;
txwaddress(10 downto txfabits) <= (others => '0');
txwaddress(txfabits-1 downto 0) <= vtxfi.waddress;
--edcl buf
erenable <= veri.renable;
eraddress(15 downto eabits) <= (others => '0');
eraddress(eabits-1 downto 0) <= veri.raddress;
ewritem <= veri.writem;
ewritel <= veri.writel;
ewaddressm(15 downto eabits) <= (others => '0');
ewaddressm(eabits-1 downto 0) <= veri.waddressm(eabits-1 downto 0);
ewaddressl(15 downto eabits) <= (others => '0');
ewaddressl(eabits-1 downto 0) <= veri.waddressl(eabits-1 downto 0);
ewdata <= veri.datain;
rxi.enable <= vrxenable;
end process;
rxi.writeack <= r.rxwriteack;
rxi.doneack <= r.rxdoneack;
rxi.speed <= r.ctrl.speed;
rxi.writeok <= r.writeok;
rxi.rxd <= rxd;
rxi.rx_dv <= rx_dv;
rxi.rx_crs <= rx_crs;
rxi.rx_er <= rx_er;
txi.rx_col <= rx_col;
txi.rx_crs <= rx_crs;
txi.full_duplex <= r.ctrl.full_duplex;
txi.start <= r.txstart_sync;
txi.readack <= r.txreadack;
txi.speed <= r.ctrl.speed;
txi.data <= r.txdata;
txi.valid <= r.txvalid;
txi.len <= r.txlength;
mdc <= r.mdioclk;
mdio_o <= r.mdioo;
mdio_oe <= r.mdioen;
tmsto <= r.tmsto;
rmsto <= r.rmsto;
txd <= txo.txd;
tx_en <= txo.tx_en;
tx_er <= txo.tx_er;
ahbmi.hgrant <= hgrant;
ahbmi.hready <= hready;
ahbmi.hresp <= hresp;
ahbmi.hrdata <= hrdata;
hbusreq <= ahbmo.hbusreq;
hlock <= ahbmo.hlock;
htrans <= ahbmo.htrans;
haddr <= ahbmo.haddr;
hwrite <= ahbmo.hwrite;
hsize <= ahbmo.hsize;
hburst <= ahbmo.hburst;
hprot <= ahbmo.hprot;
hwdata <= ahbmo.hwdata;
reset <= irst;
regs : process(clk) is
begin
if rising_edge(clk) then r <= rin; end if;
end process;
-------------------------------------------------------------------------------
-- TRANSMITTER-----------------------------------------------------------------
-------------------------------------------------------------------------------
tx_rmii0 : if rmii = 0 generate
tx0: greth_tx
generic map(
ifg_gap => ifg_gap,
attempt_limit => attempt_limit,
backoff_limit => backoff_limit,
nsync => nsync,
rmii => rmii)
port map(
rst => arst,
clk => tx_clk,
txi => txi,
txo => txo);
end generate;
tx_rmii1 : if rmii = 1 generate
tx0: greth_tx
generic map(
ifg_gap => ifg_gap,
attempt_limit => attempt_limit,
backoff_limit => backoff_limit,
nsync => nsync,
rmii => rmii)
port map(
rst => arst,
clk => rmii_clk,
txi => txi,
txo => txo);
end generate;
-------------------------------------------------------------------------------
-- RECEIVER -------------------------------------------------------------------
-------------------------------------------------------------------------------
rx_rmii0 : if rmii = 0 generate
rx0 : greth_rx
generic map(
nsync => nsync,
rmii => rmii)
port map(
rst => arst,
clk => rx_clk,
rxi => rxi,
rxo => rxo);
end generate;
rx_rmii1 : if rmii = 1 generate
rx0 : greth_rx
generic map(
nsync => nsync,
rmii => rmii)
port map(
rst => arst,
clk => rmii_clk,
rxi => rxi,
rxo => rxo);
end generate;
-------------------------------------------------------------------------------
-- AHB MST INTERFACE ----------------------------------------------------------
-------------------------------------------------------------------------------
ahb0 : eth_ahb_mst
port map(rst, clk, ahbmi, ahbmo, tmsto, tmsti, rmsto, rmsti);
end architecture;
| mit | f1e23eb1a2bdc9f9983c3c5197da47dc | 0.489745 | 3.572902 | false | false | false | false |
impedimentToProgress/UCI-BlueChip | AttackFiles/Attacks/privEsc/lib/techmap/maps/ddrphy.vhd | 2 | 10,089 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: ddrphy
-- File: ddrphy.vhd
-- Author: Jiri Gaisler, Gaisler Research
-- Description: DDR PHY with tech mapping
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.stdlib.all;
library techmap;
use techmap.gencomp.all;
use techmap.allddr.all;
------------------------------------------------------------------
-- DDR PHY with tech mapping ------------------------------------
------------------------------------------------------------------
entity ddrphy is
generic (tech : integer := virtex2; MHz : integer := 100;
rstdelay : integer := 200; dbits : integer := 16;
clk_mul : integer := 2 ; clk_div : integer := 2;
rskew : integer :=0);
port (
rst : in std_ulogic;
clk : in std_logic; -- input clock
clkout : out std_ulogic; -- system clock
clkread : out std_ulogic; -- read clock
lock : out std_ulogic; -- DCM locked
ddr_clk : out std_logic_vector(2 downto 0);
ddr_clkb : out std_logic_vector(2 downto 0);
ddr_clk_fb_out : out std_logic;
ddr_clk_fb : in std_logic;
ddr_cke : out std_logic_vector(1 downto 0);
ddr_csb : out std_logic_vector(1 downto 0);
ddr_web : out std_ulogic; -- ddr write enable
ddr_rasb : out std_ulogic; -- ddr ras
ddr_casb : out std_ulogic; -- ddr cas
ddr_dm : out std_logic_vector (dbits/8-1 downto 0); -- ddr dm
ddr_dqs : inout std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
ddr_ad : out std_logic_vector (13 downto 0); -- ddr address
ddr_ba : out std_logic_vector (1 downto 0); -- ddr bank address
ddr_dq : inout std_logic_vector (dbits-1 downto 0); -- ddr data
addr : in std_logic_vector (13 downto 0); -- data mask
ba : in std_logic_vector ( 1 downto 0); -- data mask
dqin : out std_logic_vector (dbits*2-1 downto 0); -- ddr input data
dqout : in std_logic_vector (dbits*2-1 downto 0); -- ddr input data
dm : in std_logic_vector (dbits/4-1 downto 0); -- data mask
oen : in std_ulogic;
dqs : in std_ulogic;
dqsoen : in std_ulogic;
rasn : in std_ulogic;
casn : in std_ulogic;
wen : in std_ulogic;
csn : in std_logic_vector(1 downto 0);
cke : in std_logic_vector(1 downto 0));
end;
architecture rtl of ddrphy is
begin
strat2 : if (tech = stratix2) generate
ddr_phy0 : stratixii_ddr_phy
generic map (MHz => MHz, rstdelay => rstdelay
-- reduce 200 us start-up delay during simulation
-- pragma translate_off
/ 200
-- pragma translate_on
, clk_mul => clk_mul, clk_div => clk_div, dbits => dbits
)
port map (
rst, clk, clkout, lock,
ddr_clk, ddr_clkb, ddr_clk_fb_out, ddr_clk_fb,
ddr_cke, ddr_csb, ddr_web, ddr_rasb, ddr_casb,
ddr_dm, ddr_dqs, ddr_ad, ddr_ba, ddr_dq,
addr, ba, dqin, dqout, dm, oen, dqs, dqsoen,
rasn, casn, wen, csn, cke);
end generate;
cyc3 : if (tech = cyclone3) generate
ddr_phy0 : cycloneiii_ddr_phy
generic map (MHz => MHz, rstdelay => rstdelay
-- reduce 200 us start-up delay during simulation
-- pragma translate_off
/ 200
-- pragma translate_on
, clk_mul => clk_mul, clk_div => clk_div, dbits => dbits
)
port map (
rst, clk, clkout, lock,
ddr_clk, ddr_clkb, ddr_clk_fb_out, ddr_clk_fb,
ddr_cke, ddr_csb, ddr_web, ddr_rasb, ddr_casb,
ddr_dm, ddr_dqs, ddr_ad, ddr_ba, ddr_dq,
addr, ba, dqin, dqout, dm, oen, dqs, dqsoen,
rasn, casn, wen, csn, cke);
end generate;
xc2v : if tech = virtex2 generate
ddr_phy0 : virtex2_ddr_phy
generic map (MHz => MHz, rstdelay => rstdelay
-- reduce 200 us start-up delay during simulation
-- pragma translate_off
/ 200
-- pragma translate_on
, clk_mul => clk_mul, clk_div => clk_div, dbits => dbits, rskew => rskew
)
port map (
rst, clk, clkout, lock,
ddr_clk, ddr_clkb, ddr_clk_fb_out, ddr_clk_fb,
ddr_cke, ddr_csb, ddr_web, ddr_rasb, ddr_casb,
ddr_dm, ddr_dqs, ddr_ad, ddr_ba, ddr_dq,
addr, ba, dqin, dqout, dm, oen, dqs, dqsoen,
rasn, casn, wen, csn, cke);
end generate;
xc4v : if (tech = virtex4) or (tech = virtex5) generate
ddr_phy0 : virtex4_ddr_phy
generic map (MHz => MHz, rstdelay => rstdelay
-- reduce 200 us start-up delay during simulation
-- pragma translate_off
/ 200
-- pragma translate_on
, clk_mul => clk_mul, clk_div => clk_div, dbits => dbits, rskew => rskew
)
port map (
rst, clk, clkout, lock,
ddr_clk, ddr_clkb, ddr_clk_fb_out, ddr_clk_fb,
ddr_cke, ddr_csb, ddr_web, ddr_rasb, ddr_casb,
ddr_dm, ddr_dqs, ddr_ad, ddr_ba, ddr_dq,
addr, ba, dqin, dqout, dm, oen, dqs, dqsoen,
rasn, casn, wen, csn, cke);
end generate;
xc3se : if tech = spartan3e generate
ddr_phy0 : spartan3e_ddr_phy
generic map (MHz => MHz, rstdelay => rstdelay
-- reduce 200 us start-up delay during simulation
-- pragma translate_off
/ 200
-- pragma translate_on
, clk_mul => clk_mul, clk_div => clk_div, dbits => dbits, rskew => rskew
)
port map (
rst, clk, clkout, clkread, lock,
ddr_clk, ddr_clkb, ddr_clk_fb_out, ddr_clk_fb,
ddr_cke, ddr_csb, ddr_web, ddr_rasb, ddr_casb,
ddr_dm, ddr_dqs, ddr_ad, ddr_ba, ddr_dq,
addr, ba, dqin, dqout, dm, oen, dqs, dqsoen,
rasn, casn, wen, csn, cke);
end generate;
end;
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.stdlib.all;
library techmap;
use techmap.gencomp.all;
use techmap.allddr.all;
------------------------------------------------------------------
-- DDR2 PHY with tech mapping ------------------------------------
------------------------------------------------------------------
entity ddr2phy is
generic (tech : integer := virtex5; MHz : integer := 100;
rstdelay : integer := 200; dbits : integer := 16;
clk_mul : integer := 2; clk_div : integer := 2;
ddelayb0 : integer := 0; ddelayb1 : integer := 0; ddelayb2 : integer := 0;
ddelayb3 : integer := 0; ddelayb4 : integer := 0; ddelayb5 : integer := 0;
ddelayb6 : integer := 0; ddelayb7 : integer := 0;
numidelctrl : integer := 4; norefclk : integer := 0);
port (
rst : in std_ulogic;
clk : in std_logic; -- input clock
clkref200 : in std_logic; -- input 200MHz clock
clkout : out std_ulogic; -- system clock
lock : out std_ulogic; -- DCM locked
ddr_clk : out std_logic_vector(2 downto 0);
ddr_clkb : out std_logic_vector(2 downto 0);
ddr_cke : out std_logic_vector(1 downto 0);
ddr_csb : out std_logic_vector(1 downto 0);
ddr_web : out std_ulogic; -- ddr write enable
ddr_rasb : out std_ulogic; -- ddr ras
ddr_casb : out std_ulogic; -- ddr cas
ddr_dm : out std_logic_vector (dbits/8-1 downto 0); -- ddr dm
ddr_dqs : inout std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
ddr_dqsn : inout std_logic_vector (dbits/8-1 downto 0); -- ddr dqsn
ddr_ad : out std_logic_vector (13 downto 0); -- ddr address
ddr_ba : out std_logic_vector (1 downto 0); -- ddr bank address
ddr_dq : inout std_logic_vector (dbits-1 downto 0); -- ddr data
ddr_odt : out std_logic_vector(1 downto 0);
addr : in std_logic_vector (13 downto 0); -- data mask
ba : in std_logic_vector ( 1 downto 0); -- data mask
dqin : out std_logic_vector (dbits*2-1 downto 0); -- ddr input data
dqout : in std_logic_vector (dbits*2-1 downto 0); -- ddr input data
dm : in std_logic_vector (dbits/4-1 downto 0); -- data mask
oen : in std_ulogic;
dqs : in std_ulogic;
dqsoen : in std_ulogic;
rasn : in std_ulogic;
casn : in std_ulogic;
wen : in std_ulogic;
csn : in std_logic_vector(1 downto 0);
cke : in std_logic_vector(1 downto 0);
cal_en : in std_logic_vector(dbits/8-1 downto 0);
cal_inc : in std_logic_vector(dbits/8-1 downto 0);
cal_rst : in std_logic;
odt : in std_logic_vector(1 downto 0));
end;
architecture rtl of ddr2phy is
begin
xc4v : if (tech = virtex4) or (tech = virtex5) generate
ddr_phy0 : virtex5_ddr2_phy
generic map (MHz => MHz, rstdelay => rstdelay
-- reduce 200 us start-up delay during simulation
-- pragma translate_off
/ 200
-- pragma translate_on
, clk_mul => clk_mul, clk_div => clk_div, dbits => dbits,
ddelayb0 => ddelayb0, ddelayb1 => ddelayb1, ddelayb2 => ddelayb2,
ddelayb3 => ddelayb3, ddelayb4 => ddelayb4, ddelayb5 => ddelayb5,
ddelayb6 => ddelayb6, ddelayb7 => ddelayb7,
numidelctrl => numidelctrl, norefclk => norefclk, tech => tech
)
port map (
rst, clk, clkref200, clkout, lock,
ddr_clk, ddr_clkb,
ddr_cke, ddr_csb, ddr_web, ddr_rasb, ddr_casb,
ddr_dm, ddr_dqs, ddr_dqsn, ddr_ad, ddr_ba, ddr_dq, ddr_odt,
addr, ba, dqin, dqout, dm, oen, dqs, dqsoen,
rasn, casn, wen, csn, cke, cal_en, cal_inc, cal_rst, odt);
end generate;
end;
| mit | 8d3d5964e3cabbd12edf5e3ac4318689 | 0.583705 | 3.236766 | false | false | false | false |
impedimentToProgress/UCI-BlueChip | VhdlParser/test/iu3ShadowBoot.vhd | 2 | 106,669 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008, 2009, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: iu3
-- File: iu3.vhd
-- Author: Jiri Gaisler, Edvin Catovic, Gaisler Research
-- Description: LEON3 7-stage integer pipline
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library grlib;
use grlib.sparc.all;
use grlib.stdlib.all;
library techmap;
use techmap.gencomp.all;
library gaisler;
use gaisler.leon3.all;
use gaisler.libiu.all;
use gaisler.arith.all;
-- pragma translate_off
use grlib.sparc_disas.all;
-- pragma translate_on
entity iu3 is
generic (
nwin : integer range 2 to 32 := 8;
isets : integer range 1 to 4 := 2;
dsets : integer range 1 to 4 := 2;
fpu : integer range 0 to 15 := 0;
v8 : integer range 0 to 63 := 2;
cp, mac : integer range 0 to 1 := 0;
dsu : integer range 0 to 1 := 1;
nwp : integer range 0 to 4 := 2;
pclow : integer range 0 to 2 := 2;
notag : integer range 0 to 1 := 0;
index : integer range 0 to 15:= 0;
lddel : integer range 1 to 2 := 1;
irfwt : integer range 0 to 1 := 0;
disas : integer range 0 to 2 := 0;
tbuf : integer range 0 to 64 := 2; -- trace buf size in kB (0 - no trace buffer)
pwd : integer range 0 to 2 := 0; -- power-down
svt : integer range 0 to 1 := 0; -- single-vector trapping
rstaddr : integer := 16#00000#; -- reset vector MSB address
smp : integer range 0 to 15 := 0; -- support SMP systems
fabtech : integer range 0 to NTECH := 20;
clk2x : integer := 0
);
port (
clk : in std_ulogic;
rstn : in std_ulogic;
holdn : in std_ulogic;
ici : buffer icache_in_type;
ico : in icache_out_type;
dci : buffer dcache_in_type;
dco : in dcache_out_type;
rfi : buffer iregfile_in_type;
rfo : in iregfile_out_type;
irqi : in l3_irq_in_type;
irqo : buffer l3_irq_out_type;
dbgi : in l3_debug_in_type;
dbgo : buffer l3_debug_out_type;
muli : buffer mul32_in_type;
mulo : in mul32_out_type;
divi : buffer div32_in_type;
divo : in div32_out_type;
fpo : in fpc_out_type;
fpi : buffer fpc_in_type;
cpo : in fpc_out_type;
cpi : buffer fpc_in_type;
tbo : in tracebuf_out_type;
tbi : buffer tracebuf_in_type;
sclk : in std_ulogic
);
end;
architecture rtl of iu3 is
constant ISETMSB : integer := 0;
constant DSETMSB : integer := 0;
constant RFBITS : integer range 6 to 10 := 8;
constant NWINLOG2 : integer range 1 to 5 := 3;
constant CWPOPT : boolean := true;
constant CWPMIN : std_logic_vector(2 downto 0) := "000";
constant CWPMAX : std_logic_vector(2 downto 0) := "111";
constant FPEN : boolean := (fpu /= 0);
constant CPEN : boolean := false;
constant MULEN : boolean := true;
constant MULTYPE: integer := 0;
constant DIVEN : boolean := true;
constant MACEN : boolean := false;
constant MACPIPE: boolean := false;
constant IMPL : integer := 15;
constant VER : integer := 3;
constant DBGUNIT : boolean := true;
constant TRACEBUF : boolean := true;
constant TBUFBITS : integer := 7;
constant PWRD1 : boolean := false; --(pwd = 1) and not (index /= 0);
constant PWRD2 : boolean := false; --(pwd = 2) or (index /= 0);
constant RS1OPT : boolean := true;
constant DYNRST : boolean := false;
subtype word is std_logic_vector(31 downto 0);
subtype pctype is std_logic_vector(31 downto 2);
subtype rfatype is std_logic_vector(8-1 downto 0);
subtype cwptype is std_logic_vector(3-1 downto 0);
type icdtype is array (0 to 2-1) of word;
type dcdtype is array (0 to 2-1) of word;
type dc_in_type is record
signed, enaddr, read, write, lock , dsuen : std_ulogic;
size : std_logic_vector(1 downto 0);
asi : std_logic_vector(7 downto 0);
end record;
type pipeline_ctrl_type is record
pc : pctype;
inst : word;
cnt : std_logic_vector(1 downto 0);
rd : rfatype;
tt : std_logic_vector(5 downto 0);
trap : std_ulogic;
annul : std_ulogic;
wreg : std_ulogic;
wicc : std_ulogic;
wy : std_ulogic;
ld : std_ulogic;
pv : std_ulogic;
rett : std_ulogic;
end record;
type fetch_reg_type is record
pc : pctype;
branch : std_ulogic;
end record;
type decode_reg_type is record
pc : pctype;
inst : icdtype;
cwp : cwptype;
set : std_logic_vector(0 downto 0);
mexc : std_ulogic;
cnt : std_logic_vector(1 downto 0);
pv : std_ulogic;
annul : std_ulogic;
inull : std_ulogic;
step : std_ulogic;
end record;
type regacc_reg_type is record
ctrl : pipeline_ctrl_type;
rs1 : std_logic_vector(4 downto 0);
rfa1, rfa2 : rfatype;
rsel1, rsel2 : std_logic_vector(2 downto 0);
rfe1, rfe2 : std_ulogic;
cwp : cwptype;
imm : word;
ldcheck1 : std_ulogic;
ldcheck2 : std_ulogic;
ldchkra : std_ulogic;
ldchkex : std_ulogic;
su : std_ulogic;
et : std_ulogic;
wovf : std_ulogic;
wunf : std_ulogic;
ticc : std_ulogic;
jmpl : std_ulogic;
step : std_ulogic;
mulstart : std_ulogic;
divstart : std_ulogic;
end record;
type execute_reg_type is record
ctrl : pipeline_ctrl_type;
op1 : word;
op2 : word;
aluop : std_logic_vector(2 downto 0); -- Alu operation
alusel : std_logic_vector(1 downto 0); -- Alu result select
aluadd : std_ulogic;
alucin : std_ulogic;
ldbp1, ldbp2 : std_ulogic;
invop2 : std_ulogic;
shcnt : std_logic_vector(4 downto 0); -- shift count
sari : std_ulogic; -- shift msb
shleft : std_ulogic; -- shift left/right
ymsb : std_ulogic; -- shift left/right
rd : std_logic_vector(4 downto 0);
jmpl : std_ulogic;
su : std_ulogic;
et : std_ulogic;
cwp : cwptype;
icc : std_logic_vector(3 downto 0);
mulstep: std_ulogic;
mul : std_ulogic;
mac : std_ulogic;
end record;
type memory_reg_type is record
ctrl : pipeline_ctrl_type;
result : word;
y : word;
icc : std_logic_vector(3 downto 0);
nalign : std_ulogic;
dci : dc_in_type;
werr : std_ulogic;
wcwp : std_ulogic;
irqen : std_ulogic;
irqen2 : std_ulogic;
mac : std_ulogic;
divz : std_ulogic;
su : std_ulogic;
mul : std_ulogic;
end record;
type exception_state is (run, trap, dsu1, dsu2);
type exception_reg_type is record
ctrl : pipeline_ctrl_type;
result : word;
y : word;
icc : std_logic_vector( 3 downto 0);
annul_all : std_ulogic;
data : dcdtype;
set : std_logic_vector(0 downto 0);
mexc : std_ulogic;
dci : dc_in_type;
laddr : std_logic_vector(1 downto 0);
rstate : exception_state;
npc : std_logic_vector(2 downto 0);
intack : std_ulogic;
ipend : std_ulogic;
mac : std_ulogic;
debug : std_ulogic;
nerror : std_ulogic;
end record;
type dsu_registers is record
tt : std_logic_vector(7 downto 0);
err : std_ulogic;
tbufcnt : std_logic_vector(7-1 downto 0);
asi : std_logic_vector(7 downto 0);
crdy : std_logic_vector(2 downto 1); -- diag cache access ready
end record;
type irestart_register is record
addr : pctype;
pwd : std_ulogic;
end record;
type pwd_register_type is record
pwd : std_ulogic;
error : std_ulogic;
end record;
type special_register_type is record
cwp : cwptype; -- current window pointer
icc : std_logic_vector(3 downto 0); -- integer condition codes
tt : std_logic_vector(7 downto 0); -- trap type
tba : std_logic_vector(19 downto 0); -- trap base address
wim : std_logic_vector(8-1 downto 0); -- window invalid mask
pil : std_logic_vector(3 downto 0); -- processor interrupt level
ec : std_ulogic; -- enable CP
ef : std_ulogic; -- enable FP
ps : std_ulogic; -- previous supervisor flag
s : std_ulogic; -- supervisor flag
et : std_ulogic; -- enable traps
y : word;
asr18 : word;
svt : std_ulogic; -- enable traps
dwt : std_ulogic; -- disable write error trap
end record;
type write_reg_type is record
s : special_register_type;
result : word;
wa : rfatype;
wreg : std_ulogic;
except : std_ulogic;
end record;
type registers is record
f : fetch_reg_type;
d : decode_reg_type;
a : regacc_reg_type;
e : execute_reg_type;
m : memory_reg_type;
x : exception_reg_type;
w : write_reg_type;
end record;
type exception_type is record
pri : std_ulogic;
ill : std_ulogic;
fpdis : std_ulogic;
cpdis : std_ulogic;
wovf : std_ulogic;
wunf : std_ulogic;
ticc : std_ulogic;
end record;
type watchpoint_register is record
addr : std_logic_vector(31 downto 2); -- watchpoint address
mask : std_logic_vector(31 downto 2); -- watchpoint mask
exec : std_ulogic; -- trap on instruction
load : std_ulogic; -- trap on load
store : std_ulogic; -- trap on store
end record;
type watchpoint_registers is array (0 to 3) of watchpoint_register;
constant wpr_none : watchpoint_register := (
"000000000000000000000000000000", "000000000000000000000000000000", '0', '0', '0');
function dbgexc(r : registers; dbgi : l3_debug_in_type; trap : std_ulogic; tt : std_logic_vector(7 downto 0)) return std_ulogic is
variable dmode : std_ulogic;
begin
dmode := '0';
if (not r.x.ctrl.annul and trap) = '1' then
if (((tt = "00" & TT_WATCH) and (dbgi.bwatch = '1')) or
((dbgi.bsoft = '1') and (tt = "10000001")) or
(dbgi.btrapa = '1') or
((dbgi.btrape = '1') and not ((tt(5 downto 0) = TT_PRIV) or
(tt(5 downto 0) = TT_FPDIS) or (tt(5 downto 0) = TT_WINOF) or
(tt(5 downto 0) = TT_WINUF) or (tt(5 downto 4) = "01") or (tt(7) = '1'))) or
(((not r.w.s.et) and dbgi.berror) = '1')) then
dmode := '1';
end if;
end if;
return(dmode);
end;
function dbgerr(r : registers; dbgi : l3_debug_in_type;
tt : std_logic_vector(7 downto 0))
return std_ulogic is
variable err : std_ulogic;
begin
err := not r.w.s.et;
if (((dbgi.dbreak = '1') and (tt = ("00" & TT_WATCH))) or
((dbgi.bsoft = '1') and (tt = ("10000001")))) then
err := '0';
end if;
return(err);
end;
procedure diagwr(r : in registers;
dsur : in dsu_registers;
ir : in irestart_register;
dbg : in l3_debug_in_type;
wpr : in watchpoint_registers;
s : out special_register_type;
vwpr : out watchpoint_registers;
asi : out std_logic_vector(7 downto 0);
pc, npc : out pctype;
tbufcnt : out std_logic_vector(7-1 downto 0);
wr : out std_ulogic;
addr : out std_logic_vector(9 downto 0);
data : out word;
fpcwr : out std_ulogic) is
variable i : integer range 0 to 3;
begin
s := r.w.s; pc := r.f.pc; npc := ir.addr; wr := '0';
vwpr := wpr; asi := dsur.asi; addr := "0000000000";
data := dbg.ddata;
tbufcnt := dsur.tbufcnt; fpcwr := '0';
if (dbg.dsuen and dbg.denable and dbg.dwrite) = '1' then
case dbg.daddr(23 downto 20) is
when "0001" =>
if (dbg.daddr(16) = '1') and true then -- trace buffer control reg
tbufcnt := dbg.ddata(7-1 downto 0);
end if;
when "0011" => -- IU reg file
if dbg.daddr(12) = '0' then
wr := '1';
addr := "0000000000";
addr(8-1 downto 0) := dbg.daddr(8+1 downto 2);
else -- FPC
fpcwr := '1';
end if;
when "0100" => -- IU special registers
case dbg.daddr(7 downto 6) is
when "00" => -- IU regs Y - TBUF ctrl reg
case dbg.daddr(5 downto 2) is
when "0000" => -- Y
s.y := dbg.ddata;
when "0001" => -- PSR
s.cwp := dbg.ddata(3-1 downto 0);
s.icc := dbg.ddata(23 downto 20);
s.ec := dbg.ddata(13);
if FPEN then s.ef := dbg.ddata(12); end if;
s.pil := dbg.ddata(11 downto 8);
s.s := dbg.ddata(7);
s.ps := dbg.ddata(6);
s.et := dbg.ddata(5);
when "0010" => -- WIM
s.wim := dbg.ddata(8-1 downto 0);
when "0011" => -- TBR
s.tba := dbg.ddata(31 downto 12);
s.tt := dbg.ddata(11 downto 4);
when "0100" => -- PC
pc := dbg.ddata(31 downto 2);
when "0101" => -- NPC
npc := dbg.ddata(31 downto 2);
when "0110" => --FSR
fpcwr := '1';
when "0111" => --CFSR
when "1001" => -- ASI reg
asi := dbg.ddata(7 downto 0);
--when "1001" => -- TBUF ctrl reg
-- tbufcnt := dbg.ddata(7-1 downto 0);
when others =>
end case;
when "01" => -- ASR16 - ASR31
case dbg.daddr(5 downto 2) is
when "0001" => -- %ASR17
s.dwt := dbg.ddata(14);
s.svt := dbg.ddata(13);
when "0010" => -- %ASR18
if false then s.asr18 := dbg.ddata; end if;
when "1000" => -- %ASR24 - %ASR31
vwpr(0).addr := dbg.ddata(31 downto 2);
vwpr(0).exec := dbg.ddata(0);
when "1001" =>
vwpr(0).mask := dbg.ddata(31 downto 2);
vwpr(0).load := dbg.ddata(1);
vwpr(0).store := dbg.ddata(0);
when "1010" =>
vwpr(1).addr := dbg.ddata(31 downto 2);
vwpr(1).exec := dbg.ddata(0);
when "1011" =>
vwpr(1).mask := dbg.ddata(31 downto 2);
vwpr(1).load := dbg.ddata(1);
vwpr(1).store := dbg.ddata(0);
when "1100" =>
vwpr(2).addr := dbg.ddata(31 downto 2);
vwpr(2).exec := dbg.ddata(0);
when "1101" =>
vwpr(2).mask := dbg.ddata(31 downto 2);
vwpr(2).load := dbg.ddata(1);
vwpr(2).store := dbg.ddata(0);
when "1110" =>
vwpr(3).addr := dbg.ddata(31 downto 2);
vwpr(3).exec := dbg.ddata(0);
when "1111" => --
vwpr(3).mask := dbg.ddata(31 downto 2);
vwpr(3).load := dbg.ddata(1);
vwpr(3).store := dbg.ddata(0);
when others => --
end case;
-- disabled due to bug in XST
-- i := conv_integer(dbg.daddr(4 downto 3));
-- if dbg.daddr(2) = '0' then
-- vwpr(i).addr := dbg.ddata(31 downto 2);
-- vwpr(i).exec := dbg.ddata(0);
-- else
-- vwpr(i).mask := dbg.ddata(31 downto 2);
-- vwpr(i).load := dbg.ddata(1);
-- vwpr(i).store := dbg.ddata(0);
-- end if;
when others =>
end case;
when others =>
end case;
end if;
end;
function asr17_gen ( r : in registers) return word is
variable asr17 : word;
variable fpu2 : integer range 0 to 3;
begin
asr17 := "00000000000000000000000000000000";
asr17(31 downto 28) := conv_std_logic_vector(index, 4);
if (clk2x > 8) then
asr17(16 downto 15) := conv_std_logic_vector(clk2x-8, 2);
asr17(17) := '1';
elsif (clk2x > 0) then
asr17(16 downto 15) := conv_std_logic_vector(clk2x, 2);
end if;
asr17(14) := r.w.s.dwt;
if svt = 1 then asr17(13) := r.w.s.svt; end if;
if lddel = 2 then asr17(12) := '1'; end if;
if (fpu > 0) and (fpu < 8) then fpu2 := 1;
elsif (fpu >= 8) and (fpu < 15) then fpu2 := 3;
elsif fpu = 15 then fpu2 := 2;
else fpu2 := 0; end if;
asr17(11 downto 10) := conv_std_logic_vector(fpu2, 2);
if mac = 1 then asr17(9) := '1'; end if;
if 2 /= 0 then asr17(8) := '1'; end if;
asr17(7 downto 5) := conv_std_logic_vector(nwp, 3);
asr17(4 downto 0) := conv_std_logic_vector(8-1, 5);
return(asr17);
end;
procedure diagread(dbgi : in l3_debug_in_type;
r : in registers;
dsur : in dsu_registers;
ir : in irestart_register;
wpr : in watchpoint_registers;
dco : in dcache_out_type;
tbufo : in tracebuf_out_type;
data : out word) is
variable cwp : std_logic_vector(4 downto 0);
variable rd : std_logic_vector(4 downto 0);
variable i : integer range 0 to 3;
begin
data := "00000000000000000000000000000000"; cwp := "00000";
cwp(3-1 downto 0) := r.w.s.cwp;
case dbgi.daddr(22 downto 20) is
when "001" => -- trace buffer
if true then
if dbgi.daddr(16) = '1' then -- trace buffer control reg
if true then data(7-1 downto 0) := dsur.tbufcnt; end if;
else
case dbgi.daddr(3 downto 2) is
when "00" => data := tbufo.data(127 downto 96);
when "01" => data := tbufo.data(95 downto 64);
when "10" => data := tbufo.data(63 downto 32);
when others => data := tbufo.data(31 downto 0);
end case;
end if;
end if;
when "011" => -- IU reg file
if dbgi.daddr(12) = '0' then
data := rfo.data1(31 downto 0);
if (dbgi.daddr(11) = '1') and (is_fpga(fabtech) = 0) then
data := rfo.data2(31 downto 0);
end if;
else data := fpo.dbg.data; end if;
when "100" => -- IU regs
case dbgi.daddr(7 downto 6) is
when "00" => -- IU regs Y - TBUF ctrl reg
case dbgi.daddr(5 downto 2) is
when "0000" =>
data := r.w.s.y;
when "0001" =>
data := conv_std_logic_vector(15, 4) & conv_std_logic_vector(3, 4) &
r.w.s.icc & "000000" & r.w.s.ec & r.w.s.ef & r.w.s.pil &
r.w.s.s & r.w.s.ps & r.w.s.et & cwp;
when "0010" =>
data(8-1 downto 0) := r.w.s.wim;
when "0011" =>
data := r.w.s.tba & r.w.s.tt & "0000";
when "0100" =>
data(31 downto 2) := r.f.pc;
when "0101" =>
data(31 downto 2) := ir.addr;
when "0110" => -- FSR
data := fpo.dbg.data;
when "0111" => -- CPSR
when "1000" => -- TT reg
data(12 downto 4) := dsur.err & dsur.tt;
when "1001" => -- ASI reg
data(7 downto 0) := dsur.asi;
when others =>
end case;
when "01" =>
if dbgi.daddr(5) = '0' then -- %ASR17
if dbgi.daddr(4 downto 2) = "001" then -- %ASR17
data := asr17_gen(r);
elsif false and dbgi.daddr(4 downto 2) = "010" then -- %ASR18
data := r.w.s.asr18;
end if;
else -- %ASR24 - %ASR31
i := conv_integer(dbgi.daddr(4 downto 3)); --
if dbgi.daddr(2) = '0' then
data(31 downto 2) := wpr(i).addr;
data(0) := wpr(i).exec;
else
data(31 downto 2) := wpr(i).mask;
data(1) := wpr(i).load;
data(0) := wpr(i).store;
end if;
end if;
when others =>
end case;
when "111" =>
data := r.x.data(conv_integer(r.x.set));
when others =>
end case;
end;
procedure itrace(r : in registers;
dsur : in dsu_registers;
vdsu : in dsu_registers;
res : in word;
exc : in std_ulogic;
dbgi : in l3_debug_in_type;
error : in std_ulogic;
trap : in std_ulogic;
tbufcnt : out std_logic_vector(7-1 downto 0);
di : out tracebuf_in_type) is
variable meminst : std_ulogic;
begin
di.addr := (others => '0'); di.data := (others => '0');
di.enable := '0'; di.write := (others => '0');
tbufcnt := vdsu.tbufcnt;
meminst := r.x.ctrl.inst(31) and r.x.ctrl.inst(30);
if true then
di.addr(7-1 downto 0) := dsur.tbufcnt;
di.data(127) := '0';
di.data(126) := not r.x.ctrl.pv;
di.data(125 downto 96) := dbgi.timer(29 downto 0);
di.data(95 downto 64) := res;
di.data(63 downto 34) := r.x.ctrl.pc(31 downto 2);
di.data(33) := trap;
di.data(32) := error;
di.data(31 downto 0) := r.x.ctrl.inst;
if (dbgi.tenable = '0') or (r.x.rstate = dsu2) then
if ((dbgi.dsuen and dbgi.denable) = '1') and (dbgi.daddr(23 downto 20) & dbgi.daddr(16) = "00010") then
di.enable := '1';
di.addr(7-1 downto 0) := dbgi.daddr(7-1+4 downto 4);
if dbgi.dwrite = '1' then
case dbgi.daddr(3 downto 2) is
when "00" => di.write(3) := '1';
when "01" => di.write(2) := '1';
when "10" => di.write(1) := '1';
when others => di.write(0) := '1';
end case;
di.data := dbgi.ddata & dbgi.ddata & dbgi.ddata & dbgi.ddata;
end if;
end if;
elsif (not r.x.ctrl.annul and (r.x.ctrl.pv or meminst) and not r.x.debug) = '1' then
di.enable := '1'; di.write := (others => '1');
tbufcnt := dsur.tbufcnt + 1;
end if;
di.diag := dco.testen & "000";
if dco.scanen = '1' then di.enable := '0'; end if;
end if;
end;
procedure dbg_cache(holdn : in std_ulogic;
dbgi : in l3_debug_in_type;
r : in registers;
dsur : in dsu_registers;
mresult : in word;
dci : in dc_in_type;
mresult2 : out word;
dci2 : out dc_in_type
) is
begin
mresult2 := mresult; dci2 := dci; dci2.dsuen := '0';
if true then
if r.x.rstate = dsu2 then
dci2.asi := dsur.asi;
if (dbgi.daddr(22 downto 20) = "111") and (dbgi.dsuen = '1') then
dci2.dsuen := (dbgi.denable or r.m.dci.dsuen) and not dsur.crdy(2);
dci2.enaddr := dbgi.denable;
dci2.size := "10"; dci2.read := '1'; dci2.write := '0';
if (dbgi.denable and not r.m.dci.enaddr) = '1' then
mresult2 := (others => '0'); mresult2(19 downto 2) := dbgi.daddr(19 downto 2);
else
mresult2 := dbgi.ddata;
end if;
if dbgi.dwrite = '1' then
dci2.read := '0'; dci2.write := '1';
end if;
end if;
end if;
end if;
end;
procedure fpexack(r : in registers; fpexc : out std_ulogic) is
begin
fpexc := '0';
if FPEN then
if r.x.ctrl.tt = TT_FPEXC then fpexc := '1'; end if;
end if;
end;
procedure diagrdy(denable : in std_ulogic;
dsur : in dsu_registers;
dci : in dc_in_type;
mds : in std_ulogic;
ico : in icache_out_type;
crdy : out std_logic_vector(2 downto 1)) is
begin
crdy := dsur.crdy(1) & '0';
if dci.dsuen = '1' then
case dsur.asi(4 downto 0) is
when ASI_ITAG | ASI_IDATA | ASI_UINST | ASI_SINST =>
crdy(2) := ico.diagrdy and not dsur.crdy(2);
when ASI_DTAG | ASI_MMUSNOOP_DTAG | ASI_DDATA | ASI_UDATA | ASI_SDATA =>
crdy(1) := not denable and dci.enaddr and not dsur.crdy(1);
when others =>
crdy(2) := dci.enaddr and denable;
end case;
end if;
end;
signal r, rin : registers;
signal wpr, wprin : watchpoint_registers;
signal dsur, dsuin : dsu_registers;
signal ir, irin : irestart_register;
signal rp, rpin : pwd_register_type;
-- execute stage operations
constant EXE_AND : std_logic_vector(2 downto 0) := "000";
constant EXE_XOR : std_logic_vector(2 downto 0) := "001"; -- must be equal to EXE_PASS2
constant EXE_OR : std_logic_vector(2 downto 0) := "010";
constant EXE_XNOR : std_logic_vector(2 downto 0) := "011";
constant EXE_ANDN : std_logic_vector(2 downto 0) := "100";
constant EXE_ORN : std_logic_vector(2 downto 0) := "101";
constant EXE_DIV : std_logic_vector(2 downto 0) := "110";
constant EXE_PASS1 : std_logic_vector(2 downto 0) := "000";
constant EXE_PASS2 : std_logic_vector(2 downto 0) := "001";
constant EXE_STB : std_logic_vector(2 downto 0) := "010";
constant EXE_STH : std_logic_vector(2 downto 0) := "011";
constant EXE_ONES : std_logic_vector(2 downto 0) := "100";
constant EXE_RDY : std_logic_vector(2 downto 0) := "101";
constant EXE_SPR : std_logic_vector(2 downto 0) := "110";
constant EXE_LINK : std_logic_vector(2 downto 0) := "111";
constant EXE_SLL : std_logic_vector(2 downto 0) := "001";
constant EXE_SRL : std_logic_vector(2 downto 0) := "010";
constant EXE_SRA : std_logic_vector(2 downto 0) := "100";
constant EXE_NOP : std_logic_vector(2 downto 0) := "000";
-- EXE result select
constant EXE_RES_ADD : std_logic_vector(1 downto 0) := "00";
constant EXE_RES_SHIFT : std_logic_vector(1 downto 0) := "01";
constant EXE_RES_LOGIC : std_logic_vector(1 downto 0) := "10";
constant EXE_RES_MISC : std_logic_vector(1 downto 0) := "11";
-- Load types
constant SZBYTE : std_logic_vector(1 downto 0) := "00";
constant SZHALF : std_logic_vector(1 downto 0) := "01";
constant SZWORD : std_logic_vector(1 downto 0) := "10";
constant SZDBL : std_logic_vector(1 downto 0) := "11";
-- calculate register file address
procedure regaddr(cwp : std_logic_vector; reg : std_logic_vector(4 downto 0);
rao : out rfatype) is
variable ra : rfatype;
constant globals : std_logic_vector(8-5 downto 0) :=
conv_std_logic_vector(8, 8-4);
begin
ra := (others => '0'); ra(4 downto 0) := reg;
if reg(4 downto 3) = "00" then ra(8 -1 downto 4) := globals;
else
ra(3+3 downto 4) := cwp + ra(4);
if ra(8-1 downto 4) = globals then
ra(8-1 downto 4) := (others => '0');
end if;
end if;
rao := ra;
end;
-- branch adder
function branch_address(inst : word; pc : pctype) return std_logic_vector is
variable baddr, caddr, tmp : pctype;
begin
caddr := (others => '0'); caddr(31 downto 2) := inst(29 downto 0);
caddr(31 downto 2) := caddr(31 downto 2) + pc(31 downto 2);
baddr := (others => '0'); baddr(31 downto 24) := (others => inst(21));
baddr(23 downto 2) := inst(21 downto 0);
baddr(31 downto 2) := baddr(31 downto 2) + pc(31 downto 2);
if inst(30) = '1' then tmp := caddr; else tmp := baddr; end if;
return(tmp);
end;
-- evaluate branch condition
function branch_true(icc : std_logic_vector(3 downto 0); inst : word)
return std_ulogic is
variable n, z, v, c, branch : std_ulogic;
begin
n := icc(3); z := icc(2); v := icc(1); c := icc(0);
case inst(27 downto 25) is
when "000" => branch := inst(28) xor '0'; -- bn, ba
when "001" => branch := inst(28) xor z; -- be, bne
when "010" => branch := inst(28) xor (z or (n xor v)); -- ble, bg
when "011" => branch := inst(28) xor (n xor v); -- bl, bge
when "100" => branch := inst(28) xor (c or z); -- bleu, bgu
when "101" => branch := inst(28) xor c; -- bcs, bcc
when "110" => branch := inst(28) xor n; -- bneg, bpos
when others => branch := inst(28) xor v; -- bvs, bvc
end case;
return(branch);
end;
-- detect RETT instruction in the pipeline and set the local psr.su and psr.et
procedure su_et_select(r : in registers; xc_ps, xc_s, xc_et : in std_ulogic;
su, et : out std_ulogic) is
begin
if ((r.a.ctrl.rett or r.e.ctrl.rett or r.m.ctrl.rett or r.x.ctrl.rett) = '1')
and (r.x.annul_all = '0')
then su := xc_ps; et := '1';
else su := xc_s; et := xc_et; end if;
end;
-- detect watchpoint trap
function wphit(r : registers; wpr : watchpoint_registers; debug : l3_debug_in_type)
return std_ulogic is
variable exc : std_ulogic;
begin
exc := '0';
for i in 1 to NWP loop
if ((wpr(i-1).exec and r.a.ctrl.pv and not r.a.ctrl.annul) = '1') then
if (((wpr(i-1).addr xor r.a.ctrl.pc(31 downto 2)) and wpr(i-1).mask) = "000000000000000000000000000000") then
exc := '1';
end if;
end if;
end loop;
if true then
if (debug.dsuen and not r.a.ctrl.annul) = '1' then
exc := exc or (r.a.ctrl.pv and ((debug.dbreak and debug.bwatch) or r.a.step));
end if;
end if;
return(exc);
end;
-- 32-bit shifter
function shift3(r : registers; aluin1, aluin2 : word) return word is
variable shiftin : unsigned(63 downto 0);
variable shiftout : unsigned(63 downto 0);
variable cnt : natural range 0 to 31;
begin
cnt := conv_integer(r.e.shcnt);
if r.e.shleft = '1' then
shiftin(30 downto 0) := (others => '0');
shiftin(63 downto 31) := '0' & unsigned(aluin1);
else
shiftin(63 downto 32) := (others => r.e.sari);
shiftin(31 downto 0) := unsigned(aluin1);
end if;
shiftout := SHIFT_RIGHT(shiftin, cnt);
return(std_logic_vector(shiftout(31 downto 0)));
end;
function shift2(r : registers; aluin1, aluin2 : word) return word is
variable ushiftin : unsigned(31 downto 0);
variable sshiftin : signed(32 downto 0);
variable cnt : natural range 0 to 31;
variable resleft, resright : word;
begin
cnt := conv_integer(r.e.shcnt);
ushiftin := unsigned(aluin1);
sshiftin := signed('0' & aluin1);
if r.e.shleft = '1' then
resleft := std_logic_vector(SHIFT_LEFT(ushiftin, cnt));
return(resleft);
else
if r.e.sari = '1' then sshiftin(32) := aluin1(31); end if;
sshiftin := SHIFT_RIGHT(sshiftin, cnt);
resright := std_logic_vector(sshiftin(31 downto 0));
return(resright);
-- else
-- ushiftin := SHIFT_RIGHT(ushiftin, cnt);
-- return(std_logic_vector(ushiftin));
-- end if;
end if;
end;
function shift(r : registers; aluin1, aluin2 : word;
shiftcnt : std_logic_vector(4 downto 0); sari : std_ulogic ) return word is
variable shiftin : std_logic_vector(63 downto 0);
begin
shiftin := "00000000000000000000000000000000" & aluin1;
if r.e.shleft = '1' then
shiftin(31 downto 0) := "00000000000000000000000000000000"; shiftin(63 downto 31) := '0' & aluin1;
else shiftin(63 downto 32) := (others => sari); end if;
if shiftcnt (4) = '1' then shiftin(47 downto 0) := shiftin(63 downto 16); end if;
if shiftcnt (3) = '1' then shiftin(39 downto 0) := shiftin(47 downto 8); end if;
if shiftcnt (2) = '1' then shiftin(35 downto 0) := shiftin(39 downto 4); end if;
if shiftcnt (1) = '1' then shiftin(33 downto 0) := shiftin(35 downto 2); end if;
if shiftcnt (0) = '1' then shiftin(31 downto 0) := shiftin(32 downto 1); end if;
return(shiftin(31 downto 0));
end;
-- Check for illegal and privileged instructions
procedure exception_detect(r : registers; wpr : watchpoint_registers; dbgi : l3_debug_in_type;
trapin : in std_ulogic; ttin : in std_logic_vector(5 downto 0);
trap : out std_ulogic; tt : out std_logic_vector(5 downto 0)) is
variable illegal_inst, privileged_inst : std_ulogic;
variable cp_disabled, fp_disabled, fpop : std_ulogic;
variable op : std_logic_vector(1 downto 0);
variable op2 : std_logic_vector(2 downto 0);
variable op3 : std_logic_vector(5 downto 0);
variable rd : std_logic_vector(4 downto 0);
variable inst : word;
variable wph : std_ulogic;
begin
inst := r.a.ctrl.inst; trap := trapin; tt := ttin;
if r.a.ctrl.annul = '0' then
op := inst(31 downto 30); op2 := inst(24 downto 22);
op3 := inst(24 downto 19); rd := inst(29 downto 25);
illegal_inst := '0'; privileged_inst := '0'; cp_disabled := '0';
fp_disabled := '0'; fpop := '0';
case op is
when CALL => null;
when FMT2 =>
case op2 is
when SETHI | BICC => null;
when FBFCC =>
if FPEN then fp_disabled := not r.w.s.ef; else fp_disabled := '1'; end if;
when CBCCC =>
if (not false) or (r.w.s.ec = '0') then cp_disabled := '1'; end if;
when others => illegal_inst := '1';
end case;
when FMT3 =>
case op3 is
when IAND | ANDCC | ANDN | ANDNCC | IOR | ORCC | ORN | ORNCC | IXOR |
XORCC | IXNOR | XNORCC | ISLL | ISRL | ISRA | MULSCC | IADD | ADDX |
ADDCC | ADDXCC | ISUB | SUBX | SUBCC | SUBXCC | FLUSH | JMPL | TICC |
SAVE | RESTORE | RDY => null;
when TADDCC | TADDCCTV | TSUBCC | TSUBCCTV =>
if notag = 1 then illegal_inst := '1'; end if;
when UMAC | SMAC =>
if not false then illegal_inst := '1'; end if;
when UMUL | SMUL | UMULCC | SMULCC =>
if not true then illegal_inst := '1'; end if;
when UDIV | SDIV | UDIVCC | SDIVCC =>
if not true then illegal_inst := '1'; end if;
when RETT => illegal_inst := r.a.et; privileged_inst := not r.a.su;
when RDPSR | RDTBR | RDWIM => privileged_inst := not r.a.su;
when WRY => null;
when WRPSR =>
privileged_inst := not r.a.su;
when WRWIM | WRTBR => privileged_inst := not r.a.su;
when FPOP1 | FPOP2 =>
if FPEN then fp_disabled := not r.w.s.ef; fpop := '1';
else fp_disabled := '1'; fpop := '0'; end if;
when CPOP1 | CPOP2 =>
if (not false) or (r.w.s.ec = '0') then cp_disabled := '1'; end if;
when others => illegal_inst := '1';
end case;
when others => -- LDST
case op3 is
when LDD | ISTD => illegal_inst := rd(0); -- trap if odd destination register
when LD | LDUB | LDSTUB | LDUH | LDSB | LDSH | ST | STB | STH | SWAP =>
null;
when LDDA | STDA =>
illegal_inst := inst(13) or rd(0); privileged_inst := not r.a.su;
when LDA | LDUBA| LDSTUBA | LDUHA | LDSBA | LDSHA | STA | STBA | STHA |
SWAPA =>
illegal_inst := inst(13); privileged_inst := not r.a.su;
when LDDF | STDF | LDF | LDFSR | STF | STFSR =>
if FPEN then fp_disabled := not r.w.s.ef;
else fp_disabled := '1'; end if;
when STDFQ =>
privileged_inst := not r.a.su;
if (not FPEN) or (r.w.s.ef = '0') then fp_disabled := '1'; end if;
when STDCQ =>
privileged_inst := not r.a.su;
if (not false) or (r.w.s.ec = '0') then cp_disabled := '1'; end if;
when LDC | LDCSR | LDDC | STC | STCSR | STDC =>
if (not false) or (r.w.s.ec = '0') then cp_disabled := '1'; end if;
when others => illegal_inst := '1';
end case;
end case;
wph := wphit(r, wpr, dbgi);
trap := '1';
if r.a.ctrl.trap = '1' then tt := TT_IAEX;
elsif privileged_inst = '1' then tt := TT_PRIV;
elsif illegal_inst = '1' then tt := TT_IINST;
elsif fp_disabled = '1' then tt := TT_FPDIS;
elsif cp_disabled = '1' then tt := TT_CPDIS;
elsif wph = '1' then tt := TT_WATCH;
elsif r.a.wovf= '1' then tt := TT_WINOF;
elsif r.a.wunf= '1' then tt := TT_WINUF;
elsif r.a.ticc= '1' then tt := TT_TICC;
else trap := '0'; tt:= (others => '0'); end if;
end if;
end;
-- instructions that write the condition codes (psr.icc)
procedure wicc_y_gen(inst : word; wicc, wy : out std_ulogic) is
begin
wicc := '0'; wy := '0';
if inst(31 downto 30) = FMT3 then
case inst(24 downto 19) is
when SUBCC | TSUBCC | TSUBCCTV | ADDCC | ANDCC | ORCC | XORCC | ANDNCC |
ORNCC | XNORCC | TADDCC | TADDCCTV | ADDXCC | SUBXCC | WRPSR =>
wicc := '1';
when WRY =>
if r.d.inst(conv_integer(r.d.set))(29 downto 25) = "00000" then wy := '1'; end if;
when MULSCC =>
wicc := '1'; wy := '1';
when UMAC | SMAC =>
if false then wy := '1'; end if;
when UMULCC | SMULCC =>
if true and (((mulo.nready = '1') and (r.d.cnt /= "00")) or (0 /= 0)) then
wicc := '1'; wy := '1';
end if;
when UMUL | SMUL =>
if true and (((mulo.nready = '1') and (r.d.cnt /= "00")) or (0 /= 0)) then
wy := '1';
end if;
when UDIVCC | SDIVCC =>
if true and (divo.nready = '1') and (r.d.cnt /= "00") then
wicc := '1';
end if;
when others =>
end case;
end if;
end;
-- select cwp
procedure cwp_gen(r, v : registers; annul, wcwp : std_ulogic; ncwp : cwptype;
cwp : out cwptype) is
begin
if (r.x.rstate = trap) or (r.x.rstate = dsu2) or (rstn = '0') then cwp := v.w.s.cwp;
elsif (wcwp = '1') and (annul = '0') then cwp := ncwp;
elsif r.m.wcwp = '1' then cwp := r.m.result(3-1 downto 0);
else cwp := r.d.cwp; end if;
end;
-- generate wcwp in ex stage
procedure cwp_ex(r : in registers; wcwp : out std_ulogic) is
begin
if (r.e.ctrl.inst(31 downto 30) = FMT3) and
(r.e.ctrl.inst(24 downto 19) = WRPSR)
then wcwp := not r.e.ctrl.annul; else wcwp := '0'; end if;
end;
-- generate next cwp & window under- and overflow traps
procedure cwp_ctrl(r : in registers; xc_wim : in std_logic_vector(8-1 downto 0);
inst : word; de_cwp : out cwptype; wovf_exc, wunf_exc, wcwp : out std_ulogic) is
variable op : std_logic_vector(1 downto 0);
variable op3 : std_logic_vector(5 downto 0);
variable wim : word;
variable ncwp : cwptype;
begin
op := inst(31 downto 30); op3 := inst(24 downto 19);
wovf_exc := '0'; wunf_exc := '0'; wim := (others => '0');
wim(8-1 downto 0) := xc_wim; ncwp := r.d.cwp; wcwp := '0';
if (op = FMT3) and ((op3 = RETT) or (op3 = RESTORE) or (op3 = SAVE)) then
wcwp := '1';
if (op3 = SAVE) then
if (not true) and (r.d.cwp = "000") then ncwp := "111";
else ncwp := r.d.cwp - 1 ; end if;
else
if (not true) and (r.d.cwp = "111") then ncwp := "000";
else ncwp := r.d.cwp + 1; end if;
end if;
if wim(conv_integer(ncwp)) = '1' then
if op3 = SAVE then wovf_exc := '1'; else wunf_exc := '1'; end if;
end if;
end if;
de_cwp := ncwp;
end;
-- generate register read address 1
procedure rs1_gen(r : registers; inst : word; rs1 : out std_logic_vector(4 downto 0);
rs1mod : out std_ulogic) is
variable op : std_logic_vector(1 downto 0);
variable op3 : std_logic_vector(5 downto 0);
begin
op := inst(31 downto 30); op3 := inst(24 downto 19);
rs1 := inst(18 downto 14); rs1mod := '0';
if (op = LDST) then
if ((r.d.cnt = "01") and ((op3(2) and not op3(3)) = '1')) or
(r.d.cnt = "10")
then rs1mod := '1'; rs1 := inst(29 downto 25); end if;
if ((r.d.cnt = "10") and (op3(3 downto 0) = "0111")) then
rs1(0) := '1';
end if;
end if;
end;
-- load/icc interlock detection
procedure lock_gen(r : registers; rs2, rd : std_logic_vector(4 downto 0);
rfa1, rfa2, rfrd : rfatype; inst : word; fpc_lock, mulinsn, divinsn : std_ulogic;
lldcheck1, lldcheck2, lldlock, lldchkra, lldchkex : out std_ulogic) is
variable op : std_logic_vector(1 downto 0);
variable op2 : std_logic_vector(2 downto 0);
variable op3 : std_logic_vector(5 downto 0);
variable cond : std_logic_vector(3 downto 0);
variable rs1 : std_logic_vector(4 downto 0);
variable i, ldcheck1, ldcheck2, ldchkra, ldchkex, ldcheck3 : std_ulogic;
variable ldlock, icc_check, bicc_hold, chkmul, y_check : std_ulogic;
variable lddlock : boolean;
begin
op := inst(31 downto 30); op3 := inst(24 downto 19);
op2 := inst(24 downto 22); cond := inst(28 downto 25);
rs1 := inst(18 downto 14); lddlock := false; i := inst(13);
ldcheck1 := '0'; ldcheck2 := '0'; ldcheck3 := '0'; ldlock := '0';
ldchkra := '1'; ldchkex := '1'; icc_check := '0'; bicc_hold := '0';
y_check := '0';
if (r.d.annul = '0') then
case op is
when FMT2 =>
if (op2 = BICC) and (cond(2 downto 0) /= "000") then
icc_check := '1';
end if;
when FMT3 =>
ldcheck1 := '1'; ldcheck2 := not i;
case op3 is
when TICC =>
if (cond(2 downto 0) /= "000") then icc_check := '1'; end if;
when RDY =>
ldcheck1 := '0'; ldcheck2 := '0';
if false then y_check := '1'; end if;
when RDWIM | RDTBR =>
ldcheck1 := '0'; ldcheck2 := '0';
when RDPSR =>
ldcheck1 := '0'; ldcheck2 := '0'; icc_check := '1';
if true then icc_check := '1'; end if;
-- when ADDX | ADDXCC | SUBX | SUBXCC =>
-- if true then icc_check := '1'; end if;
when SDIV | SDIVCC | UDIV | UDIVCC =>
if true then y_check := '1'; end if;
when FPOP1 | FPOP2 => ldcheck1:= '0'; ldcheck2 := '0';
when others =>
end case;
when LDST =>
ldcheck1 := '1'; ldchkra := '0';
case r.d.cnt is
when "00" =>
if (lddel = 2) and (op3(2) = '1') then ldcheck3 := '1'; end if;
ldcheck2 := not i; ldchkra := '1';
when "01" => ldcheck2 := not i;
when others => ldchkex := '0';
end case;
if (op3(2 downto 0) = "011") then lddlock := true; end if;
when others => null;
end case;
end if;
if true or true then
chkmul := mulinsn;
bicc_hold := bicc_hold or (icc_check and r.m.ctrl.wicc and (r.m.ctrl.cnt(0) or r.m.mul));
else chkmul := '0'; end if;
if true then
bicc_hold := bicc_hold or (y_check and (r.a.ctrl.wy or r.e.ctrl.wy));
chkmul := chkmul or divinsn;
end if;
bicc_hold := bicc_hold or (icc_check and (r.a.ctrl.wicc or r.e.ctrl.wicc));
if (((r.a.ctrl.ld or chkmul) and r.a.ctrl.wreg and ldchkra) = '1') and
(((ldcheck1 = '1') and (r.a.ctrl.rd = rfa1)) or
((ldcheck2 = '1') and (r.a.ctrl.rd = rfa2)) or
((ldcheck3 = '1') and (r.a.ctrl.rd = rfrd)))
then ldlock := '1'; end if;
if (((r.e.ctrl.ld or r.e.mac) and r.e.ctrl.wreg and ldchkex) = '1') and
((lddel = 2) or (false and (r.e.mac = '1')) or ((0 = 3) and (r.e.mul = '1'))) and
(((ldcheck1 = '1') and (r.e.ctrl.rd = rfa1)) or
((ldcheck2 = '1') and (r.e.ctrl.rd = rfa2)))
then ldlock := '1'; end if;
ldlock := ldlock or bicc_hold or fpc_lock;
lldcheck1 := ldcheck1; lldcheck2:= ldcheck2; lldlock := ldlock;
lldchkra := ldchkra; lldchkex := ldchkex;
end;
procedure fpbranch(inst : in word; fcc : in std_logic_vector(1 downto 0);
branch : out std_ulogic) is
variable cond : std_logic_vector(3 downto 0);
variable fbres : std_ulogic;
begin
cond := inst(28 downto 25);
case cond(2 downto 0) is
when "000" => fbres := '0'; -- fba, fbn
when "001" => fbres := fcc(1) or fcc(0);
when "010" => fbres := fcc(1) xor fcc(0);
when "011" => fbres := fcc(0);
when "100" => fbres := (not fcc(1)) and fcc(0);
when "101" => fbres := fcc(1);
when "110" => fbres := fcc(1) and not fcc(0);
when others => fbres := fcc(1) and fcc(0);
end case;
branch := cond(3) xor fbres;
end;
-- PC generation
procedure ic_ctrl(r : registers; inst : word; annul_all, ldlock, branch_true,
fbranch_true, cbranch_true, fccv, cccv : in std_ulogic;
cnt : out std_logic_vector(1 downto 0);
de_pc : out pctype; de_branch, ctrl_annul, de_annul, jmpl_inst, inull,
de_pv, ctrl_pv, de_hold_pc, ticc_exception, rett_inst, mulstart,
divstart : out std_ulogic) is
variable op : std_logic_vector(1 downto 0);
variable op2 : std_logic_vector(2 downto 0);
variable op3 : std_logic_vector(5 downto 0);
variable cond : std_logic_vector(3 downto 0);
variable hold_pc, annul_current, annul_next, branch, annul, pv : std_ulogic;
variable de_jmpl : std_ulogic;
begin
branch := '0'; annul_next := '0'; annul_current := '0'; pv := '1';
hold_pc := '0'; ticc_exception := '0'; rett_inst := '0';
op := inst(31 downto 30); op3 := inst(24 downto 19);
op2 := inst(24 downto 22); cond := inst(28 downto 25);
annul := inst(29); de_jmpl := '0'; cnt := "00";
mulstart := '0'; divstart := '0';
if r.d.annul = '0' then
case inst(31 downto 30) is
when CALL =>
branch := '1';
if r.d.inull = '1' then
hold_pc := '1'; annul_current := '1';
end if;
when FMT2 =>
if (op2 = BICC) or (FPEN and (op2 = FBFCC)) or (false and (op2 = CBCCC)) then
if (FPEN and (op2 = FBFCC)) then
branch := fbranch_true;
if fccv /= '1' then hold_pc := '1'; annul_current := '1'; end if;
elsif (false and (op2 = CBCCC)) then
branch := cbranch_true;
if cccv /= '1' then hold_pc := '1'; annul_current := '1'; end if;
else branch := branch_true; end if;
if hold_pc = '0' then
if (branch = '1') then
if (cond = BA) and (annul = '1') then annul_next := '1'; end if;
else annul_next := annul; end if;
if r.d.inull = '1' then -- contention with JMPL
hold_pc := '1'; annul_current := '1'; annul_next := '0';
end if;
end if;
end if;
when FMT3 =>
case op3 is
when UMUL | SMUL | UMULCC | SMULCC =>
if true and (0 /= 0) then mulstart := '1'; end if;
if true and (0 = 0) then
case r.d.cnt is
when "00" =>
cnt := "01"; hold_pc := '1'; pv := '0'; mulstart := '1';
when "01" =>
if mulo.nready = '1' then cnt := "00";
else cnt := "01"; pv := '0'; hold_pc := '1'; end if;
when others => null;
end case;
end if;
when UDIV | SDIV | UDIVCC | SDIVCC =>
if true then
case r.d.cnt is
when "00" =>
cnt := "01"; hold_pc := '1'; pv := '0';
divstart := '1';
when "01" =>
if divo.nready = '1' then cnt := "00";
else cnt := "01"; pv := '0'; hold_pc := '1'; end if;
when others => null;
end case;
end if;
when TICC =>
if branch_true = '1' then ticc_exception := '1'; end if;
when RETT =>
rett_inst := '1'; --su := sregs.ps;
when JMPL =>
de_jmpl := '1';
when WRY =>
if false then
if inst(29 downto 25) = "10011" then -- %ASR19
case r.d.cnt is
when "00" =>
pv := '0'; cnt := "00"; hold_pc := '1';
if r.x.ipend = '1' then cnt := "01"; end if;
when "01" =>
cnt := "00";
when others =>
end case;
end if;
end if;
when others => null;
end case;
when others => -- LDST
case r.d.cnt is
when "00" =>
if (op3(2) = '1') or (op3(1 downto 0) = "11") then -- ST/LDST/SWAP/LDD
cnt := "01"; hold_pc := '1'; pv := '0';
end if;
when "01" =>
if (op3(2 downto 0) = "111") or (op3(3 downto 0) = "1101") or
((false or FPEN) and ((op3(5) & op3(2 downto 0)) = "1110"))
then -- LDD/STD/LDSTUB/SWAP
cnt := "10"; pv := '0'; hold_pc := '1';
else
cnt := "00";
end if;
when "10" =>
cnt := "00";
when others => null;
end case;
end case;
end if;
if ldlock = '1' then
cnt := r.d.cnt; annul_next := '0'; pv := '1';
end if;
hold_pc := (hold_pc or ldlock) and not annul_all;
if hold_pc = '1' then de_pc := r.d.pc; else de_pc := r.f.pc; end if;
annul_current := (annul_current or ldlock or annul_all);
ctrl_annul := r.d.annul or annul_all or annul_current;
pv := pv and not ((r.d.inull and not hold_pc) or annul_all);
jmpl_inst := de_jmpl and not annul_current;
annul_next := (r.d.inull and not hold_pc) or annul_next or annul_all;
if (annul_next = '1') or (rstn = '0') then
cnt := (others => '0');
end if;
de_hold_pc := hold_pc; de_branch := branch; de_annul := annul_next;
de_pv := pv; ctrl_pv := r.d.pv and
not ((r.d.annul and not r.d.pv) or annul_all or annul_current);
inull := (not rstn) or r.d.inull or hold_pc or annul_all;
end;
-- register write address generation
procedure rd_gen(r : registers; inst : word; wreg, ld : out std_ulogic;
rdo : out std_logic_vector(4 downto 0)) is
variable write_reg : std_ulogic;
variable op : std_logic_vector(1 downto 0);
variable op2 : std_logic_vector(2 downto 0);
variable op3 : std_logic_vector(5 downto 0);
variable rd : std_logic_vector(4 downto 0);
begin
op := inst(31 downto 30);
op2 := inst(24 downto 22);
op3 := inst(24 downto 19);
write_reg := '0'; rd := inst(29 downto 25); ld := '0';
case op is
when CALL =>
write_reg := '1'; rd := "01111"; -- CALL saves PC in r[15] (%o7)
when FMT2 =>
if (op2 = SETHI) then write_reg := '1'; end if;
when FMT3 =>
case op3 is
when UMUL | SMUL | UMULCC | SMULCC =>
if true then
if (((mulo.nready = '1') and (r.d.cnt /= "00")) or (0 /= 0)) then
write_reg := '1';
end if;
else write_reg := '1'; end if;
when UDIV | SDIV | UDIVCC | SDIVCC =>
if true then
if (divo.nready = '1') and (r.d.cnt /= "00") then
write_reg := '1';
end if;
else write_reg := '1'; end if;
when RETT | WRPSR | WRY | WRWIM | WRTBR | TICC | FLUSH => null;
when FPOP1 | FPOP2 => null;
when CPOP1 | CPOP2 => null;
when others => write_reg := '1';
end case;
when others => -- LDST
ld := not op3(2);
if (op3(2) = '0') and not ((false or FPEN) and (op3(5) = '1'))
then write_reg := '1'; end if;
case op3 is
when SWAP | SWAPA | LDSTUB | LDSTUBA =>
if r.d.cnt = "00" then write_reg := '1'; ld := '1'; end if;
when others => null;
end case;
if r.d.cnt = "01" then
case op3 is
when LDD | LDDA | LDDC | LDDF => rd(0) := '1';
when others =>
end case;
end if;
end case;
if (rd = "00000") then write_reg := '0'; end if;
wreg := write_reg; rdo := rd;
end;
-- immediate data generation
function imm_data (r : registers; insn : word)
return word is
variable immediate_data, inst : word;
begin
immediate_data := (others => '0'); inst := insn;
case inst(31 downto 30) is
when FMT2 =>
immediate_data := inst(21 downto 0) & "0000000000";
when others => -- LDST
immediate_data(31 downto 13) := (others => inst(12));
immediate_data(12 downto 0) := inst(12 downto 0);
end case;
return(immediate_data);
end;
-- read special registers
function get_spr (r : registers) return word is
variable spr : word;
begin
spr := (others => '0');
case r.e.ctrl.inst(24 downto 19) is
when RDPSR => spr(31 downto 5) := conv_std_logic_vector(15,4) &
conv_std_logic_vector(3,4) & r.m.icc & "000000" & r.w.s.ec & r.w.s.ef &
r.w.s.pil & r.e.su & r.w.s.ps & r.e.et;
spr(3-1 downto 0) := r.e.cwp;
when RDTBR => spr(31 downto 4) := r.w.s.tba & r.w.s.tt;
when RDWIM => spr(8-1 downto 0) := r.w.s.wim;
when others =>
end case;
return(spr);
end;
-- immediate data select
function imm_select(inst : word) return boolean is
variable imm : boolean;
begin
imm := false;
case inst(31 downto 30) is
when FMT2 =>
case inst(24 downto 22) is
when SETHI => imm := true;
when others =>
end case;
when FMT3 =>
case inst(24 downto 19) is
when RDWIM | RDPSR | RDTBR => imm := true;
when others => if (inst(13) = '1') then imm := true; end if;
end case;
when LDST =>
if (inst(13) = '1') then imm := true; end if;
when others =>
end case;
return(imm);
end;
-- EXE operation
procedure alu_op(r : in registers; iop1, iop2 : in word; me_icc : std_logic_vector(3 downto 0);
my, ldbp : std_ulogic; aop1, aop2 : out word; aluop : out std_logic_vector(2 downto 0);
alusel : out std_logic_vector(1 downto 0); aluadd : out std_ulogic;
shcnt : out std_logic_vector(4 downto 0); sari, shleft, ymsb,
mulins, divins, mulstep, macins, ldbp2, invop2 : out std_ulogic) is
variable op : std_logic_vector(1 downto 0);
variable op2 : std_logic_vector(2 downto 0);
variable op3 : std_logic_vector(5 downto 0);
variable rd : std_logic_vector(4 downto 0);
variable icc : std_logic_vector(3 downto 0);
variable y0 : std_ulogic;
begin
op := r.a.ctrl.inst(31 downto 30);
op2 := r.a.ctrl.inst(24 downto 22);
op3 := r.a.ctrl.inst(24 downto 19);
aop1 := iop1; aop2 := iop2; ldbp2 := ldbp;
aluop := EXE_NOP; alusel := EXE_RES_MISC; aluadd := '1';
shcnt := iop2(4 downto 0); sari := '0'; shleft := '0'; invop2 := '0';
ymsb := iop1(0); mulins := '0'; divins := '0'; mulstep := '0';
macins := '0';
if r.e.ctrl.wy = '1' then y0 := my;
elsif r.m.ctrl.wy = '1' then y0 := r.m.y(0);
elsif r.x.ctrl.wy = '1' then y0 := r.x.y(0);
else y0 := r.w.s.y(0); end if;
if r.e.ctrl.wicc = '1' then icc := me_icc;
elsif r.m.ctrl.wicc = '1' then icc := r.m.icc;
elsif r.x.ctrl.wicc = '1' then icc := r.x.icc;
else icc := r.w.s.icc; end if;
case op is
when CALL =>
aluop := EXE_LINK;
when FMT2 =>
case op2 is
when SETHI => aluop := EXE_PASS2;
when others =>
end case;
when FMT3 =>
case op3 is
when IADD | ADDX | ADDCC | ADDXCC | TADDCC | TADDCCTV | SAVE | RESTORE |
TICC | JMPL | RETT => alusel := EXE_RES_ADD;
when ISUB | SUBX | SUBCC | SUBXCC | TSUBCC | TSUBCCTV =>
alusel := EXE_RES_ADD; aluadd := '0'; aop2 := not iop2; invop2 := '1';
when MULSCC => alusel := EXE_RES_ADD;
aop1 := (icc(3) xor icc(1)) & iop1(31 downto 1);
if y0 = '0' then aop2 := (others => '0'); ldbp2 := '0'; end if;
mulstep := '1';
when UMUL | UMULCC | SMUL | SMULCC =>
if true then mulins := '1'; end if;
when UMAC | SMAC =>
if false then mulins := '1'; macins := '1'; end if;
when UDIV | UDIVCC | SDIV | SDIVCC =>
if true then
aluop := EXE_DIV; alusel := EXE_RES_LOGIC; divins := '1';
end if;
when IAND | ANDCC => aluop := EXE_AND; alusel := EXE_RES_LOGIC;
when ANDN | ANDNCC => aluop := EXE_ANDN; alusel := EXE_RES_LOGIC;
when IOR | ORCC => aluop := EXE_OR; alusel := EXE_RES_LOGIC;
when ORN | ORNCC => aluop := EXE_ORN; alusel := EXE_RES_LOGIC;
when IXNOR | XNORCC => aluop := EXE_XNOR; alusel := EXE_RES_LOGIC;
when XORCC | IXOR | WRPSR | WRWIM | WRTBR | WRY =>
aluop := EXE_XOR; alusel := EXE_RES_LOGIC;
when RDPSR | RDTBR | RDWIM => aluop := EXE_SPR;
when RDY => aluop := EXE_RDY;
when ISLL => aluop := EXE_SLL; alusel := EXE_RES_SHIFT; shleft := '1';
shcnt := not iop2(4 downto 0); invop2 := '1';
when ISRL => aluop := EXE_SRL; alusel := EXE_RES_SHIFT;
when ISRA => aluop := EXE_SRA; alusel := EXE_RES_SHIFT; sari := iop1(31);
when FPOP1 | FPOP2 =>
when others =>
end case;
when others => -- LDST
case r.a.ctrl.cnt is
when "00" =>
alusel := EXE_RES_ADD;
when "01" =>
case op3 is
when LDD | LDDA | LDDC => alusel := EXE_RES_ADD;
when LDDF => alusel := EXE_RES_ADD;
when SWAP | SWAPA | LDSTUB | LDSTUBA => alusel := EXE_RES_ADD;
when STF | STDF =>
when others =>
aluop := EXE_PASS1;
if op3(2) = '1' then
if op3(1 downto 0) = "01" then aluop := EXE_STB;
elsif op3(1 downto 0) = "10" then aluop := EXE_STH; end if;
end if;
end case;
when "10" =>
aluop := EXE_PASS1;
if op3(2) = '1' then -- ST
if (op3(3) and not op3(1))= '1' then aluop := EXE_ONES; end if; -- LDSTUB/A
end if;
when others =>
end case;
end case;
end;
function ra_inull_gen(r, v : registers) return std_ulogic is
variable de_inull : std_ulogic;
begin
de_inull := '0';
if ((v.e.jmpl or v.e.ctrl.rett) and not v.e.ctrl.annul and not (r.e.jmpl and not r.e.ctrl.annul)) = '1' then de_inull := '1'; end if;
if ((v.a.jmpl or v.a.ctrl.rett) and not v.a.ctrl.annul and not (r.a.jmpl and not r.a.ctrl.annul)) = '1' then de_inull := '1'; end if;
return(de_inull);
end;
-- operand generation
procedure op_mux(r : in registers; rfd, ed, md, xd, im : in word;
rsel : in std_logic_vector(2 downto 0);
ldbp : out std_ulogic; d : out word) is
begin
ldbp := '0';
case rsel is
when "000" => d := rfd;
when "001" => d := ed;
when "010" => d := md; if lddel = 1 then ldbp := r.m.ctrl.ld; end if;
when "011" => d := xd;
when "100" => d := im;
when "101" => d := (others => '0');
when "110" => d := r.w.result;
when others => d := (others => '-');
end case;
end;
procedure op_find(r : in registers; ldchkra : std_ulogic; ldchkex : std_ulogic;
rs1 : std_logic_vector(4 downto 0); ra : rfatype; im : boolean; rfe : out std_ulogic;
osel : out std_logic_vector(2 downto 0); ldcheck : std_ulogic) is
begin
rfe := '0';
if im then osel := "100";
elsif rs1 = "00000" then osel := "101"; -- %g0
elsif ((r.a.ctrl.wreg and ldchkra) = '1') and (ra = r.a.ctrl.rd) then osel := "001";
elsif ((r.e.ctrl.wreg and ldchkex) = '1') and (ra = r.e.ctrl.rd) then osel := "010";
elsif r.m.ctrl.wreg = '1' and (ra = r.m.ctrl.rd) then osel := "011";
elsif (irfwt = 0) and r.x.ctrl.wreg = '1' and (ra = r.x.ctrl.rd) then osel := "110";
else osel := "000"; rfe := ldcheck; end if;
end;
-- generate carry-in for alu
procedure cin_gen(r : registers; me_cin : in std_ulogic; cin : out std_ulogic) is
variable op : std_logic_vector(1 downto 0);
variable op3 : std_logic_vector(5 downto 0);
variable ncin : std_ulogic;
begin
op := r.a.ctrl.inst(31 downto 30); op3 := r.a.ctrl.inst(24 downto 19);
if r.e.ctrl.wicc = '1' then ncin := me_cin;
else ncin := r.m.icc(0); end if;
cin := '0';
case op is
when FMT3 =>
case op3 is
when ISUB | SUBCC | TSUBCC | TSUBCCTV => cin := '1';
when ADDX | ADDXCC => cin := ncin;
when SUBX | SUBXCC => cin := not ncin;
when others => null;
end case;
when others => null;
end case;
end;
procedure logic_op(r : registers; aluin1, aluin2, mey : word;
ymsb : std_ulogic; logicres, y : out word) is
variable logicout : word;
begin
case r.e.aluop is
when EXE_AND => logicout := aluin1 and aluin2;
when EXE_ANDN => logicout := aluin1 and not aluin2;
when EXE_OR => logicout := aluin1 or aluin2;
when EXE_ORN => logicout := aluin1 or not aluin2;
when EXE_XOR => logicout := aluin1 xor aluin2;
when EXE_XNOR => logicout := aluin1 xor not aluin2;
when EXE_DIV =>
if true then logicout := aluin2;
else logicout := (others => '-'); end if;
when others => logicout := (others => '-');
end case;
if (r.e.ctrl.wy and r.e.mulstep) = '1' then
y := ymsb & r.m.y(31 downto 1);
elsif r.e.ctrl.wy = '1' then y := logicout;
elsif r.m.ctrl.wy = '1' then y := mey;
elsif false and (r.x.mac = '1') then y := mulo.result(63 downto 32);
elsif r.x.ctrl.wy = '1' then y := r.x.y;
else y := r.w.s.y; end if;
logicres := logicout;
end;
procedure misc_op(r : registers; wpr : watchpoint_registers;
aluin1, aluin2, ldata, mey : word;
mout, edata : out word) is
variable miscout, bpdata, stdata : word;
variable wpi : integer;
begin
wpi := 0; miscout := r.e.ctrl.pc(31 downto 2) & "00";
edata := aluin1; bpdata := aluin1;
if ((r.x.ctrl.wreg and r.x.ctrl.ld and not r.x.ctrl.annul) = '1') and
(r.x.ctrl.rd = r.e.ctrl.rd) and (r.e.ctrl.inst(31 downto 30) = LDST) and
(r.e.ctrl.cnt /= "10")
then bpdata := ldata; end if;
case r.e.aluop is
when EXE_STB => miscout := bpdata(7 downto 0) & bpdata(7 downto 0) &
bpdata(7 downto 0) & bpdata(7 downto 0);
edata := miscout;
when EXE_STH => miscout := bpdata(15 downto 0) & bpdata(15 downto 0);
edata := miscout;
when EXE_PASS1 => miscout := bpdata; edata := miscout;
when EXE_PASS2 => miscout := aluin2;
when EXE_ONES => miscout := (others => '1');
edata := miscout;
when EXE_RDY =>
if true and (r.m.ctrl.wy = '1') then miscout := mey;
else miscout := r.m.y; end if;
if (NWP > 0) and (r.e.ctrl.inst(18 downto 17) = "11") then
wpi := conv_integer(r.e.ctrl.inst(16 downto 15));
if r.e.ctrl.inst(14) = '0' then miscout := wpr(wpi).addr & '0' & wpr(wpi).exec;
else miscout := wpr(wpi).mask & wpr(wpi).load & wpr(wpi).store; end if;
end if;
if (r.e.ctrl.inst(18 downto 17) = "10") and (r.e.ctrl.inst(14) = '1') then --%ASR17
miscout := asr17_gen(r);
end if;
if false then
if (r.e.ctrl.inst(18 downto 14) = "10010") then --%ASR18
if ((r.m.mac = '1') and not false) or ((r.x.mac = '1') and false) then
miscout := mulo.result(31 downto 0); -- data forward of asr18
else miscout := r.w.s.asr18; end if;
else
if ((r.m.mac = '1') and not false) or ((r.x.mac = '1') and false) then
miscout := mulo.result(63 downto 32); -- data forward Y
end if;
end if;
end if;
when EXE_SPR =>
miscout := get_spr(r);
when others => null;
end case;
mout := miscout;
end;
procedure alu_select(r : registers; addout : std_logic_vector(32 downto 0);
op1, op2 : word; shiftout, logicout, miscout : word; res : out word;
me_icc : std_logic_vector(3 downto 0);
icco : out std_logic_vector(3 downto 0); divz : out std_ulogic) is
variable op : std_logic_vector(1 downto 0);
variable op3 : std_logic_vector(5 downto 0);
variable icc : std_logic_vector(3 downto 0);
variable aluresult : word;
begin
op := r.e.ctrl.inst(31 downto 30); op3 := r.e.ctrl.inst(24 downto 19);
icc := (others => '0');
case r.e.alusel is
when EXE_RES_ADD =>
aluresult := addout(32 downto 1);
if r.e.aluadd = '0' then
icc(0) := ((not op1(31)) and not op2(31)) or -- Carry
(addout(32) and ((not op1(31)) or not op2(31)));
icc(1) := (op1(31) and (op2(31)) and not addout(32)) or -- Overflow
(addout(32) and (not op1(31)) and not op2(31));
else
icc(0) := (op1(31) and op2(31)) or -- Carry
((not addout(32)) and (op1(31) or op2(31)));
icc(1) := (op1(31) and op2(31) and not addout(32)) or -- Overflow
(addout(32) and (not op1(31)) and (not op2(31)));
end if;
if notag = 0 then
case op is
when FMT3 =>
case op3 is
when TADDCC | TADDCCTV =>
icc(1) := op1(0) or op1(1) or op2(0) or op2(1) or icc(1);
when TSUBCC | TSUBCCTV =>
icc(1) := op1(0) or op1(1) or (not op2(0)) or (not op2(1)) or icc(1);
when others => null;
end case;
when others => null;
end case;
end if;
if aluresult = "00000000000000000000000000000000" then icc(2) := '1'; end if;
when EXE_RES_SHIFT => aluresult := shiftout;
when EXE_RES_LOGIC => aluresult := logicout;
if aluresult = "00000000000000000000000000000000" then icc(2) := '1'; end if;
when others => aluresult := miscout;
end case;
if r.e.jmpl = '1' then aluresult := r.e.ctrl.pc(31 downto 2) & "00"; end if;
icc(3) := aluresult(31); divz := icc(2);
if r.e.ctrl.wicc = '1' then
if (op = FMT3) and (op3 = WRPSR) then icco := logicout(23 downto 20);
else icco := icc; end if;
elsif r.m.ctrl.wicc = '1' then icco := me_icc;
elsif r.x.ctrl.wicc = '1' then icco := r.x.icc;
else icco := r.w.s.icc; end if;
res := aluresult;
end;
procedure dcache_gen(r, v : registers; dci : out dc_in_type;
link_pc, jump, force_a2, load : out std_ulogic) is
variable op : std_logic_vector(1 downto 0);
variable op3 : std_logic_vector(5 downto 0);
variable su : std_ulogic;
begin
op := r.e.ctrl.inst(31 downto 30); op3 := r.e.ctrl.inst(24 downto 19);
dci.signed := '0'; dci.lock := '0'; dci.dsuen := '0'; dci.size := SZWORD;
if op = LDST then
case op3 is
when LDUB | LDUBA => dci.size := SZBYTE;
when LDSTUB | LDSTUBA => dci.size := SZBYTE; dci.lock := '1';
when LDUH | LDUHA => dci.size := SZHALF;
when LDSB | LDSBA => dci.size := SZBYTE; dci.signed := '1';
when LDSH | LDSHA => dci.size := SZHALF; dci.signed := '1';
when LD | LDA | LDF | LDC => dci.size := SZWORD;
when SWAP | SWAPA => dci.size := SZWORD; dci.lock := '1';
when LDD | LDDA | LDDF | LDDC => dci.size := SZDBL;
when STB | STBA => dci.size := SZBYTE;
when STH | STHA => dci.size := SZHALF;
when ST | STA | STF => dci.size := SZWORD;
when ISTD | STDA => dci.size := SZDBL;
when STDF | STDFQ => if FPEN then dci.size := SZDBL; end if;
when STDC | STDCQ => if false then dci.size := SZDBL; end if;
when others => dci.size := SZWORD; dci.lock := '0'; dci.signed := '0';
end case;
end if;
link_pc := '0'; jump:= '0'; force_a2 := '0'; load := '0';
dci.write := '0'; dci.enaddr := '0'; dci.read := not op3(2);
-- load/store control decoding
if (r.e.ctrl.annul = '0') then
case op is
when CALL => link_pc := '1';
when FMT3 =>
case op3 is
when JMPL => jump := '1'; link_pc := '1';
when RETT => jump := '1';
when others => null;
end case;
when LDST =>
case r.e.ctrl.cnt is
when "00" =>
dci.read := op3(3) or not op3(2); -- LD/LDST/SWAP
load := op3(3) or not op3(2);
dci.enaddr := '1';
when "01" =>
force_a2 := not op3(2); -- LDD
load := not op3(2); dci.enaddr := not op3(2);
if op3(3 downto 2) = "01" then -- ST/STD
dci.write := '1';
end if;
if op3(3 downto 2) = "11" then -- LDST/SWAP
dci.enaddr := '1';
end if;
when "10" => -- STD/LDST/SWAP
dci.write := '1';
when others => null;
end case;
if (r.e.ctrl.trap or (v.x.ctrl.trap and not v.x.ctrl.annul)) = '1' then
dci.enaddr := '0';
end if;
when others => null;
end case;
end if;
if ((r.x.ctrl.rett and not r.x.ctrl.annul) = '1') then su := r.w.s.ps;
else su := r.w.s.s; end if;
if su = '1' then dci.asi := "00001011"; else dci.asi := "00001010"; end if;
if (op3(4) = '1') and ((op3(5) = '0') or not false) then
dci.asi := r.e.ctrl.inst(12 downto 5);
end if;
end;
procedure fpstdata(r : in registers; edata, eres : in word; fpstdata : in std_logic_vector(31 downto 0);
edata2, eres2 : out word) is
variable op : std_logic_vector(1 downto 0);
variable op3 : std_logic_vector(5 downto 0);
begin
edata2 := edata; eres2 := eres;
op := r.e.ctrl.inst(31 downto 30); op3 := r.e.ctrl.inst(24 downto 19);
if FPEN then
if FPEN and (op = LDST) and ((op3(5 downto 4) & op3(2)) = "101") and (r.e.ctrl.cnt /= "00") then
edata2 := fpstdata; eres2 := fpstdata;
end if;
end if;
end;
function ld_align(data : dcdtype; set : std_logic_vector(0 downto 0);
size, laddr : std_logic_vector(1 downto 0); signed : std_ulogic) return word is
variable align_data, rdata : word;
begin
align_data := data(conv_integer(set)); rdata := (others => '0');
case size is
when "00" => -- byte read
case laddr is
when "00" =>
rdata(7 downto 0) := align_data(31 downto 24);
if signed = '1' then rdata(31 downto 8) := (others => align_data(31)); end if;
when "01" =>
rdata(7 downto 0) := align_data(23 downto 16);
if signed = '1' then rdata(31 downto 8) := (others => align_data(23)); end if;
when "10" =>
rdata(7 downto 0) := align_data(15 downto 8);
if signed = '1' then rdata(31 downto 8) := (others => align_data(15)); end if;
when others =>
rdata(7 downto 0) := align_data(7 downto 0);
if signed = '1' then rdata(31 downto 8) := (others => align_data(7)); end if;
end case;
when "01" => -- half-word read
if laddr(1) = '1' then
rdata(15 downto 0) := align_data(15 downto 0);
if signed = '1' then rdata(31 downto 15) := (others => align_data(15)); end if;
else
rdata(15 downto 0) := align_data(31 downto 16);
if signed = '1' then rdata(31 downto 15) := (others => align_data(31)); end if;
end if;
when others => -- single and double word read
rdata := align_data;
end case;
return(rdata);
end;
procedure mem_trap(r : registers; wpr : watchpoint_registers;
annul, holdn : in std_ulogic;
trapout, iflush, nullify, werrout : out std_ulogic;
tt : out std_logic_vector(5 downto 0)) is
variable cwp : std_logic_vector(3-1 downto 0);
variable cwpx : std_logic_vector(5 downto 3);
variable op : std_logic_vector(1 downto 0);
variable op2 : std_logic_vector(2 downto 0);
variable op3 : std_logic_vector(5 downto 0);
variable nalign_d : std_ulogic;
variable trap, werr : std_ulogic;
begin
op := r.m.ctrl.inst(31 downto 30); op2 := r.m.ctrl.inst(24 downto 22);
op3 := r.m.ctrl.inst(24 downto 19);
cwpx := r.m.result(5 downto 3); cwpx(5) := '0';
iflush := '0'; trap := r.m.ctrl.trap; nullify := annul;
tt := r.m.ctrl.tt; werr := (dco.werr or r.m.werr) and not r.w.s.dwt;
nalign_d := r.m.nalign or r.m.result(2);
if ((annul or trap) /= '1') and (r.m.ctrl.pv = '1') then
if (werr and holdn) = '1' then
trap := '1'; tt := TT_DSEX; werr := '0';
if op = LDST then nullify := '1'; end if;
end if;
end if;
if ((annul or trap) /= '1') then
case op is
when FMT2 =>
case op2 is
when FBFCC =>
if FPEN and (fpo.exc = '1') then trap := '1'; tt := TT_FPEXC; end if;
when CBCCC =>
if false and (cpo.exc = '1') then trap := '1'; tt := TT_CPEXC; end if;
when others => null;
end case;
when FMT3 =>
case op3 is
when WRPSR =>
if (orv(cwpx) = '1') then trap := '1'; tt := TT_IINST; end if;
when UDIV | SDIV | UDIVCC | SDIVCC =>
if true then
if r.m.divz = '1' then trap := '1'; tt := TT_DIV; end if;
end if;
when JMPL | RETT =>
if r.m.nalign = '1' then trap := '1'; tt := TT_UNALA; end if;
when TADDCCTV | TSUBCCTV =>
if (notag = 0) and (r.m.icc(1) = '1') then
trap := '1'; tt := TT_TAG;
end if;
when FLUSH => iflush := '1';
when FPOP1 | FPOP2 =>
if FPEN and (fpo.exc = '1') then trap := '1'; tt := TT_FPEXC; end if;
when CPOP1 | CPOP2 =>
if false and (cpo.exc = '1') then trap := '1'; tt := TT_CPEXC; end if;
when others => null;
end case;
when LDST =>
if r.m.ctrl.cnt = "00" then
case op3 is
when LDDF | STDF | STDFQ =>
if FPEN then
if nalign_d = '1' then
trap := '1'; tt := TT_UNALA; nullify := '1';
elsif (fpo.exc and r.m.ctrl.pv) = '1'
then trap := '1'; tt := TT_FPEXC; nullify := '1'; end if;
end if;
when LDDC | STDC | STDCQ =>
if false then
if nalign_d = '1' then
trap := '1'; tt := TT_UNALA; nullify := '1';
elsif ((cpo.exc and r.m.ctrl.pv) = '1')
then trap := '1'; tt := TT_CPEXC; nullify := '1'; end if;
end if;
when LDD | ISTD | LDDA | STDA =>
if r.m.result(2 downto 0) /= "000" then
trap := '1'; tt := TT_UNALA; nullify := '1';
end if;
when LDF | LDFSR | STFSR | STF =>
if FPEN and (r.m.nalign = '1') then
trap := '1'; tt := TT_UNALA; nullify := '1';
elsif FPEN and ((fpo.exc and r.m.ctrl.pv) = '1')
then trap := '1'; tt := TT_FPEXC; nullify := '1'; end if;
when LDC | LDCSR | STCSR | STC =>
if false and (r.m.nalign = '1') then
trap := '1'; tt := TT_UNALA; nullify := '1';
elsif false and ((cpo.exc and r.m.ctrl.pv) = '1')
then trap := '1'; tt := TT_CPEXC; nullify := '1'; end if;
when LD | LDA | ST | STA | SWAP | SWAPA =>
if r.m.result(1 downto 0) /= "00" then
trap := '1'; tt := TT_UNALA; nullify := '1';
end if;
when LDUH | LDUHA | LDSH | LDSHA | STH | STHA =>
if r.m.result(0) /= '0' then
trap := '1'; tt := TT_UNALA; nullify := '1';
end if;
when others => null;
end case;
for i in 1 to NWP loop
if ((((wpr(i-1).load and not op3(2)) or (wpr(i-1).store and op3(2))) = '1') and
(((wpr(i-1).addr xor r.m.result(31 downto 2)) and wpr(i-1).mask) = "000000000000000000000000000000"))
then trap := '1'; tt := TT_WATCH; nullify := '1'; end if;
end loop;
end if;
when others => null;
end case;
end if;
if (rstn = '0') or (r.x.rstate = dsu2) then werr := '0'; end if;
trapout := trap; werrout := werr;
end;
procedure irq_trap(r : in registers;
ir : in irestart_register;
irl : in std_logic_vector(3 downto 0);
annul : in std_ulogic;
pv : in std_ulogic;
trap : in std_ulogic;
tt : in std_logic_vector(5 downto 0);
nullify : in std_ulogic;
irqen : out std_ulogic;
irqen2 : out std_ulogic;
nullify2 : out std_ulogic;
trap2, ipend : out std_ulogic;
tt2 : out std_logic_vector(5 downto 0)) is
variable op : std_logic_vector(1 downto 0);
variable op3 : std_logic_vector(5 downto 0);
variable pend : std_ulogic;
begin
nullify2 := nullify; trap2 := trap; tt2 := tt;
op := r.m.ctrl.inst(31 downto 30); op3 := r.m.ctrl.inst(24 downto 19);
irqen := '1'; irqen2 := r.m.irqen;
if (annul or trap) = '0' then
if ((op = FMT3) and (op3 = WRPSR)) then irqen := '0'; end if;
end if;
if (irl = "1111") or (irl > r.w.s.pil) then
pend := r.m.irqen and r.m.irqen2 and r.w.s.et and not ir.pwd;
else pend := '0'; end if;
ipend := pend;
if ((not annul) and pv and (not trap) and pend) = '1' then
trap2 := '1'; tt2 := "01" & irl;
if op = LDST then nullify2 := '1'; end if;
end if;
end;
procedure irq_intack(r : in registers; holdn : in std_ulogic; intack: out std_ulogic) is
begin
intack := '0';
if r.x.rstate = trap then
if r.w.s.tt(7 downto 4) = "0001" then intack := '1'; end if;
end if;
end;
-- write special registers
procedure sp_write (r : registers; wpr : watchpoint_registers;
s : out special_register_type; vwpr : out watchpoint_registers) is
variable op : std_logic_vector(1 downto 0);
variable op2 : std_logic_vector(2 downto 0);
variable op3 : std_logic_vector(5 downto 0);
variable rd : std_logic_vector(4 downto 0);
variable i : integer range 0 to 3;
begin
op := r.x.ctrl.inst(31 downto 30);
op2 := r.x.ctrl.inst(24 downto 22);
op3 := r.x.ctrl.inst(24 downto 19);
s := r.w.s;
rd := r.x.ctrl.inst(29 downto 25);
vwpr := wpr;
case op is
when FMT3 =>
case op3 is
when WRY =>
if rd = "00000" then
s.y := r.x.result;
elsif false and (rd = "10010") then
s.asr18 := r.x.result;
elsif (rd = "10001") then
s.dwt := r.x.result(14);
if (svt = 1) then s.svt := r.x.result(13); end if;
elsif rd(4 downto 3) = "11" then -- %ASR24 - %ASR31
case rd(2 downto 0) is
when "000" =>
vwpr(0).addr := r.x.result(31 downto 2);
vwpr(0).exec := r.x.result(0);
when "001" =>
vwpr(0).mask := r.x.result(31 downto 2);
vwpr(0).load := r.x.result(1);
vwpr(0).store := r.x.result(0);
when "010" =>
vwpr(1).addr := r.x.result(31 downto 2);
vwpr(1).exec := r.x.result(0);
when "011" =>
vwpr(1).mask := r.x.result(31 downto 2);
vwpr(1).load := r.x.result(1);
vwpr(1).store := r.x.result(0);
when "100" =>
vwpr(2).addr := r.x.result(31 downto 2);
vwpr(2).exec := r.x.result(0);
when "101" =>
vwpr(2).mask := r.x.result(31 downto 2);
vwpr(2).load := r.x.result(1);
vwpr(2).store := r.x.result(0);
when "110" =>
vwpr(3).addr := r.x.result(31 downto 2);
vwpr(3).exec := r.x.result(0);
when others => -- "111"
vwpr(3).mask := r.x.result(31 downto 2);
vwpr(3).load := r.x.result(1);
vwpr(3).store := r.x.result(0);
end case;
end if;
when WRPSR =>
s.cwp := r.x.result(3-1 downto 0);
s.icc := r.x.result(23 downto 20);
s.ec := r.x.result(13);
if FPEN then s.ef := r.x.result(12); end if;
s.pil := r.x.result(11 downto 8);
s.s := r.x.result(7);
s.ps := r.x.result(6);
s.et := r.x.result(5);
when WRWIM =>
s.wim := r.x.result(8-1 downto 0);
when WRTBR =>
s.tba := r.x.result(31 downto 12);
when SAVE =>
if (not true) and (r.w.s.cwp = "000") then s.cwp := "111";
else s.cwp := r.w.s.cwp - 1 ; end if;
when RESTORE =>
if (not true) and (r.w.s.cwp = "111") then s.cwp := "000";
else s.cwp := r.w.s.cwp + 1; end if;
when RETT =>
if (not true) and (r.w.s.cwp = "111") then s.cwp := "000";
else s.cwp := r.w.s.cwp + 1; end if;
s.s := r.w.s.ps;
s.et := '1';
when others => null;
end case;
when others => null;
end case;
if r.x.ctrl.wicc = '1' then s.icc := r.x.icc; end if;
if r.x.ctrl.wy = '1' then s.y := r.x.y; end if;
if false and (r.x.mac = '1') then
s.asr18 := mulo.result(31 downto 0);
s.y := mulo.result(63 downto 32);
end if;
end;
function npc_find (r : registers) return std_logic_vector is
variable npc : std_logic_vector(2 downto 0);
begin
npc := "011";
if r.m.ctrl.pv = '1' then npc := "000";
elsif r.e.ctrl.pv = '1' then npc := "001";
elsif r.a.ctrl.pv = '1' then npc := "010";
elsif r.d.pv = '1' then npc := "011";
elsif 2 /= 0 then npc := "100"; end if;
return(npc);
end;
function npc_gen (r : registers) return word is
variable npc : std_logic_vector(31 downto 0);
begin
npc := r.a.ctrl.pc(31 downto 2) & "00";
case r.x.npc is
when "000" => npc(31 downto 2) := r.x.ctrl.pc(31 downto 2);
when "001" => npc(31 downto 2) := r.m.ctrl.pc(31 downto 2);
when "010" => npc(31 downto 2) := r.e.ctrl.pc(31 downto 2);
when "011" => npc(31 downto 2) := r.a.ctrl.pc(31 downto 2);
when others =>
if 2 /= 0 then npc(31 downto 2) := r.d.pc(31 downto 2); end if;
end case;
return(npc);
end;
procedure mul_res(r : registers; asr18in : word; result, y, asr18 : out word;
icc : out std_logic_vector(3 downto 0)) is
variable op : std_logic_vector(1 downto 0);
variable op3 : std_logic_vector(5 downto 0);
begin
op := r.m.ctrl.inst(31 downto 30); op3 := r.m.ctrl.inst(24 downto 19);
result := r.m.result; y := r.m.y; icc := r.m.icc; asr18 := asr18in;
case op is
when FMT3 =>
case op3 is
when UMUL | SMUL =>
if true then
result := mulo.result(31 downto 0);
y := mulo.result(63 downto 32);
end if;
when UMULCC | SMULCC =>
if true then
result := mulo.result(31 downto 0); icc := mulo.icc;
y := mulo.result(63 downto 32);
end if;
when UMAC | SMAC =>
if false and not false then
result := mulo.result(31 downto 0);
asr18 := mulo.result(31 downto 0);
y := mulo.result(63 downto 32);
end if;
when UDIV | SDIV =>
if true then
result := divo.result(31 downto 0);
end if;
when UDIVCC | SDIVCC =>
if true then
result := divo.result(31 downto 0); icc := divo.icc;
end if;
when others => null;
end case;
when others => null;
end case;
end;
function powerdwn(r : registers; trap : std_ulogic; rp : pwd_register_type) return std_ulogic is
variable op : std_logic_vector(1 downto 0);
variable op3 : std_logic_vector(5 downto 0);
variable rd : std_logic_vector(4 downto 0);
variable pd : std_ulogic;
begin
op := r.x.ctrl.inst(31 downto 30);
op3 := r.x.ctrl.inst(24 downto 19);
rd := r.x.ctrl.inst(29 downto 25);
pd := '0';
if (not (r.x.ctrl.annul or trap) and r.x.ctrl.pv) = '1' then
if ((op = FMT3) and (op3 = WRY) and (rd = "10011")) then pd := '1'; end if;
pd := pd or rp.pwd;
end if;
return(pd);
end;
signal dummy : std_ulogic;
signal cpu_index : std_logic_vector(3 downto 0);
signal disasen : std_ulogic;
signal dataToCache : std_logic_vector(31 downto 0);
signal triggerCPFault : std_ulogic;
begin
comb : process(ico, dco, rfo, r, wpr, ir, dsur, rstn, holdn, irqi, dbgi, fpo, cpo, tbo, mulo, divo, dummy, rp)
variable v : registers;
variable vp : pwd_register_type;
variable vwpr : watchpoint_registers;
variable vdsu : dsu_registers;
variable npc : std_logic_vector(31 downto 2);
variable de_raddr1, de_raddr2 : std_logic_vector(9 downto 0);
variable de_rs2, de_rd : std_logic_vector(4 downto 0);
variable de_hold_pc, de_branch, de_fpop, de_ldlock : std_ulogic;
variable de_cwp, de_cwp2 : cwptype;
variable de_inull : std_ulogic;
variable de_ren1, de_ren2 : std_ulogic;
variable de_wcwp : std_ulogic;
variable de_inst : word;
variable de_branch_address : pctype;
variable de_icc : std_logic_vector(3 downto 0);
variable de_fbranch, de_cbranch : std_ulogic;
variable de_rs1mod : std_ulogic;
variable ra_op1, ra_op2 : word;
variable ra_div : std_ulogic;
variable ex_jump, ex_link_pc : std_ulogic;
variable ex_jump_address : pctype;
variable ex_add_res : std_logic_vector(32 downto 0);
variable ex_shift_res, ex_logic_res, ex_misc_res : word;
variable ex_edata, ex_edata2 : word;
variable ex_dci : dc_in_type;
variable ex_force_a2, ex_load, ex_ymsb : std_ulogic;
variable ex_op1, ex_op2, ex_result, ex_result2, mul_op2 : word;
variable ex_shcnt : std_logic_vector(4 downto 0);
variable ex_dsuen : std_ulogic;
variable ex_ldbp2 : std_ulogic;
variable ex_sari : std_ulogic;
variable me_inull, me_nullify, me_nullify2 : std_ulogic;
variable me_iflush : std_ulogic;
variable me_newtt : std_logic_vector(5 downto 0);
variable me_asr18 : word;
variable me_signed : std_ulogic;
variable me_size, me_laddr : std_logic_vector(1 downto 0);
variable me_icc : std_logic_vector(3 downto 0);
variable xc_result : word;
variable xc_df_result : word;
variable xc_waddr : std_logic_vector(9 downto 0);
variable xc_exception, xc_wreg : std_ulogic;
variable xc_trap_address : pctype;
variable xc_vectt : std_logic_vector(7 downto 0);
variable xc_trap : std_ulogic;
variable xc_fpexack : std_ulogic;
variable xc_rstn, xc_halt : std_ulogic;
-- variable wr_rf1_data, wr_rf2_data : word;
variable diagdata : word;
variable tbufi : tracebuf_in_type;
variable dbgm : std_ulogic;
variable fpcdbgwr : std_ulogic;
variable vfpi : fpc_in_type;
variable dsign : std_ulogic;
variable pwrd, sidle : std_ulogic;
variable vir : irestart_register;
variable icnt : std_ulogic;
variable tbufcntx : std_logic_vector(7-1 downto 0);
begin
v := r;
vwpr := wpr;
vdsu := dsur;
vp := rp;
xc_fpexack := '0';
sidle := '0';
fpcdbgwr := '0';
vir := ir;
xc_rstn := rstn;
-----------------------------------------------------------------------
-- WRITE STAGE
-----------------------------------------------------------------------
-- wr_rf1_data := rfo.data1; wr_rf2_data := rfo.data2;
-- if irfwt = 0 then
-- if r.w.wreg = '1' then
-- if r.a.rfa1 = r.w.wa then wr_rf1_data := r.w.result; end if;
-- if r.a.rfa2 = r.w.wa then wr_rf2_data := r.w.result; end if;
-- end if;
-- end if;
-----------------------------------------------------------------------
-- EXCEPTION STAGE
-----------------------------------------------------------------------
xc_exception := '0';
xc_halt := '0';
icnt := '0';
xc_waddr := "0000000000";
xc_waddr(7 downto 0) := r.x.ctrl.rd(7 downto 0);
xc_trap := r.x.mexc or r.x.ctrl.trap;
v.x.nerror := rp.error;
if(triggerCPFault = '1')then
xc_vectt := "00" & TT_CPDIS;
xc_trap := '1';
elsif r.x.mexc = '1' then
xc_vectt := "00" & TT_DAEX;
elsif r.x.ctrl.tt = TT_TICC then
xc_vectt := '1' & r.x.result(6 downto 0);
else
xc_vectt := "00" & r.x.ctrl.tt;
end if;
if r.w.s.svt = '0' then
xc_trap_address(31 downto 4) := r.w.s.tba & xc_vectt;
else
xc_trap_address(31 downto 4) := r.w.s.tba & "00000000";
end if;
xc_trap_address(3 downto 2) := "00";
xc_wreg := '0';
v.x.annul_all := '0';
if (r.x.ctrl.ld = '1') then
if (lddel = 2) then
xc_result := ld_align(r.x.data, r.x.set, r.x.dci.size, r.x.laddr, r.x.dci.signed);
else
xc_result := r.x.data(0);
end if;
else
xc_result := r.x.result;
end if;
xc_df_result := xc_result;
dbgm := dbgexc(r, dbgi, xc_trap, xc_vectt);
if (dbgi.dsuen and dbgi.dbreak) = '0'then
v.x.debug := '0';
end if;
pwrd := '0';
case r.x.rstate is
when run =>
if (not r.x.ctrl.annul and r.x.ctrl.pv and not r.x.debug) = '1' then
icnt := holdn;
end if;
if dbgm = '1' then
v.x.annul_all := '1';
vir.addr := r.x.ctrl.pc;
v.x.rstate := dsu1;
v.x.debug := '1';
v.x.npc := npc_find(r);
vdsu.tt := xc_vectt;
vdsu.err := dbgerr(r, dbgi, xc_vectt);
elsif (pwrd = '1') and (ir.pwd = '0') then
v.x.annul_all := '1';
vir.addr := r.x.ctrl.pc;
v.x.rstate := dsu1;
v.x.npc := npc_find(r);
vp.pwd := '1';
elsif (r.x.ctrl.annul or xc_trap) = '0' then
xc_wreg := r.x.ctrl.wreg;
sp_write (r, wpr, v.w.s, vwpr);
vir.pwd := '0';
elsif ((not r.x.ctrl.annul) and xc_trap) = '1' then
xc_exception := '1';
xc_result := r.x.ctrl.pc(31 downto 2) & "00";
xc_wreg := '1';
v.w.s.tt := xc_vectt;
v.w.s.ps := r.w.s.s;
v.w.s.s := '1';
v.x.annul_all := '1';
v.x.rstate := trap;
xc_waddr := "0000000000";
xc_waddr(6 downto 0) := r.w.s.cwp & "0001";
v.x.npc := npc_find(r);
fpexack(r, xc_fpexack);
if r.w.s.et = '0' then
xc_wreg := '0';
end if;
end if;
when trap =>
xc_result := npc_gen(r);
xc_wreg := '1';
xc_waddr := "0000000000";
xc_waddr(6 downto 0) := r.w.s.cwp & "0010";
if (r.w.s.et = '1') then
v.w.s.et := '0';
v.x.rstate := run;
v.w.s.cwp := r.w.s.cwp - 1;
else
v.x.rstate := dsu1;
xc_wreg := '0';
vp.error := '1';
end if;
when dsu1 =>
xc_exception := '1';
v.x.annul_all := '1';
xc_trap_address(31 downto 2) := r.f.pc;
xc_trap_address(31 downto 2) := ir.addr;
vir.addr := npc_gen(r)(31 downto 2);
v.x.rstate := dsu2;
v.x.debug := r.x.debug;
when dsu2 =>
xc_exception := '1';
v.x.annul_all := '1';
xc_trap_address(31 downto 2) := r.f.pc;
sidle := (rp.pwd or rp.error) and ico.idle and dco.idle and not r.x.debug;
if dbgi.reset = '1' then
vp.pwd := '0';
vp.error := '0';
end if;
if (dbgi.dsuen and dbgi.dbreak) = '1'then
v.x.debug := '1';
end if;
diagwr(r, dsur, ir, dbgi, wpr, v.w.s, vwpr, vdsu.asi, xc_trap_address, vir.addr, vdsu.tbufcnt, xc_wreg, xc_waddr, xc_result, fpcdbgwr);
xc_halt := dbgi.halt;
if r.x.ipend = '1' then
vp.pwd := '0';
end if;
if (rp.error or rp.pwd or r.x.debug or xc_halt) = '0' then
v.x.rstate := run;
v.x.annul_all := '0';
vp.error := '0';
xc_trap_address(31 downto 2) := ir.addr;
v.x.debug := '0';
vir.pwd := '1';
end if;
when others =>
end case;
irq_intack(r, holdn, v.x.intack);
itrace(r, dsur, vdsu, xc_result, xc_exception, dbgi, rp.error, xc_trap, tbufcntx, tbufi);
vdsu.tbufcnt := tbufcntx;
v.w.except := xc_exception;
v.w.result := xc_result;
if (r.x.rstate = dsu2) then
v.w.except := '0';
end if;
v.w.wa := xc_waddr(7 downto 0);
v.w.wreg := xc_wreg and holdn;
rfi.wdata <= xc_result;
rfi.waddr <= xc_waddr;
rfi.wren <= (xc_wreg and holdn) and not dco.scanen;
irqo.intack <= r.x.intack and holdn;
irqo.irl <= r.w.s.tt(3 downto 0);
irqo.pwd <= rp.pwd;
irqo.fpen <= r.w.s.ef;
dbgo.halt <= xc_halt;
dbgo.pwd <= rp.pwd;
dbgo.idle <= sidle;
dbgo.icnt <= icnt;
dci.intack <= r.x.intack and holdn;
if (xc_rstn = '0') then
v.w.except := '0';
v.w.s.et := '0';
v.w.s.svt := '0';
v.w.s.dwt := '0';
v.w.s.ef := '0';-- needed for AX
v.x.annul_all := '1';
v.x.rstate := run;
vir.pwd := '0';
vp.pwd := '0';
v.x.debug := '0';
v.x.nerror := '0';
if (dbgi.dsuen and dbgi.dbreak) = '1' then
v.x.rstate := dsu1;
v.x.debug := '1';
end if;
end if;
if not FPEN then
v.w.s.ef := '0';
end if;
-----------------------------------------------------------------------
-- MEMORY STAGE
-----------------------------------------------------------------------
v.x.ctrl := r.m.ctrl;
v.x.dci := r.m.dci;
v.x.ctrl.rett := r.m.ctrl.rett and not r.m.ctrl.annul;
v.x.mac := r.m.mac;
v.x.laddr := r.m.result(1 downto 0);
v.x.ctrl.annul := r.m.ctrl.annul or v.x.annul_all;
mul_res(r, v.w.s.asr18, v.x.result, v.x.y, me_asr18, me_icc);
mem_trap(r, wpr, v.x.ctrl.annul, holdn, v.x.ctrl.trap, me_iflush, me_nullify, v.m.werr, v.x.ctrl.tt);
me_newtt := v.x.ctrl.tt;
irq_trap(r, ir, irqi.irl, v.x.ctrl.annul, v.x.ctrl.pv, v.x.ctrl.trap, me_newtt, me_nullify, v.m.irqen, v.m.irqen2, me_nullify2, v.x.ctrl.trap, v.x.ipend, v.x.ctrl.tt);
if (r.m.ctrl.ld or not dco.mds) = '1' then
v.x.data(0) := dco.data(0);
v.x.data(1) := dco.data(1);
v.x.set := dco.set(0 downto 0);
if dco.mds = '0' then
me_size := r.x.dci.size;
me_laddr := r.x.laddr;
me_signed := r.x.dci.signed;
else
me_size := v.x.dci.size;
me_laddr := v.x.laddr;
me_signed := v.x.dci.signed;
end if;
if lddel /= 2 then
v.x.data(0) := ld_align(v.x.data, v.x.set, me_size, me_laddr, me_signed);
end if;
end if;
v.x.mexc := dco.mexc;
v.x.icc := me_icc;
v.x.ctrl.wicc := r.m.ctrl.wicc and not v.x.annul_all;
if (r.x.rstate = dsu2) then
me_nullify2 := '0';
v.x.set := dco.set(0 downto 0);
end if;
dci.maddress <= r.m.result;
dci.msu <= r.m.su;
dci.esu <= r.e.su;
dci.enaddr <= r.m.dci.enaddr;
dci.asi <= r.m.dci.asi;
dci.size <= r.m.dci.size;
dci.nullify <= me_nullify2;
dci.lock <= r.m.dci.lock and not r.m.ctrl.annul;
dci.read <= r.m.dci.read;
dci.write <= r.m.dci.write;
dci.flush <= me_iflush;
dci.dsuen <= r.m.dci.dsuen;
dbgo.ipend <= v.x.ipend;
-----------------------------------------------------------------------
-- EXECUTE STAGE
-----------------------------------------------------------------------
v.m.ctrl := r.e.ctrl;
ex_op1 := r.e.op1;
ex_op2 := r.e.op2;
v.m.ctrl.rett := r.e.ctrl.rett and not r.e.ctrl.annul;
v.m.ctrl.wreg := r.e.ctrl.wreg and not v.x.annul_all;
ex_ymsb := r.e.ymsb;
mul_op2 := ex_op2;
ex_shcnt := r.e.shcnt;
v.e.cwp := r.a.cwp;
ex_sari := r.e.sari;
v.m.su := r.e.su;
v.m.mul := '0';
if lddel = 1 then
if r.e.ldbp1 = '1' then
ex_op1 := r.x.data(0);
ex_sari := r.x.data(0)(31) and r.e.ctrl.inst(19) and r.e.ctrl.inst(20);
end if;
if r.e.ldbp2 = '1' then
ex_op2 := r.x.data(0);
ex_ymsb := r.x.data(0)(0);
mul_op2 := ex_op2;
ex_shcnt := r.x.data(0)(4 downto 0);
if r.e.invop2 = '1' then
ex_op2 := not ex_op2;
ex_shcnt := not ex_shcnt;
end if;
end if;
end if;
ex_add_res := (ex_op1 & '1') + (ex_op2 & r.e.alucin);
if ex_add_res(2 downto 1) = "00" then
v.m.nalign := '0';
else
v.m.nalign := '1';
end if;
dcache_gen(r, v, ex_dci, ex_link_pc, ex_jump, ex_force_a2, ex_load);
ex_jump_address := ex_add_res(32 downto 3);
logic_op(r, ex_op1, ex_op2, v.x.y, ex_ymsb, ex_logic_res, v.m.y);
ex_shift_res := shift(r, ex_op1, ex_op2, ex_shcnt, ex_sari);
misc_op(r, wpr, ex_op1, ex_op2, xc_df_result, v.x.y, ex_misc_res, ex_edata);
ex_add_res(3):= ex_add_res(3) or ex_force_a2;
alu_select(r, ex_add_res, ex_op1, ex_op2, ex_shift_res, ex_logic_res, ex_misc_res, ex_result, me_icc, v.m.icc, v.m.divz);
dbg_cache(holdn, dbgi, r, dsur, ex_result, ex_dci, ex_result2, v.m.dci);
fpstdata(r, ex_edata, ex_result2, fpo.data, ex_edata2, v.m.result);
cwp_ex(r, v.m.wcwp);
v.m.ctrl.annul := v.m.ctrl.annul or v.x.annul_all;
v.m.ctrl.wicc := r.e.ctrl.wicc and not v.x.annul_all;
v.m.mac := r.e.mac;
if (true and (r.x.rstate = dsu2)) then
v.m.ctrl.ld := '1';
end if;
dci.eenaddr <= v.m.dci.enaddr;
dci.eaddress <= ex_add_res(32 downto 1);
dci.edata <= ex_edata2;
-----------------------------------------------------------------------
-- REGFILE STAGE
-----------------------------------------------------------------------
v.e.ctrl := r.a.ctrl;
v.e.jmpl := r.a.jmpl;
v.e.ctrl.annul := r.a.ctrl.annul or v.x.annul_all;
v.e.ctrl.rett := r.a.ctrl.rett and not r.a.ctrl.annul;
v.e.ctrl.wreg := r.a.ctrl.wreg and not v.x.annul_all;
v.e.su := r.a.su;
v.e.et := r.a.et;
v.e.ctrl.wicc := r.a.ctrl.wicc and not v.x.annul_all;
exception_detect(r, wpr, dbgi, r.a.ctrl.trap, r.a.ctrl.tt, v.e.ctrl.trap, v.e.ctrl.tt);
op_mux(r, rfo.data1, v.m.result, v.x.result, xc_df_result, "00000000000000000000000000000000", r.a.rsel1, v.e.ldbp1, ra_op1);
op_mux(r, rfo.data2, v.m.result, v.x.result, xc_df_result, r.a.imm, r.a.rsel2, ex_ldbp2, ra_op2);
alu_op(r, ra_op1, ra_op2, v.m.icc, v.m.y(0), ex_ldbp2, v.e.op1, v.e.op2, v.e.aluop, v.e.alusel, v.e.aluadd, v.e.shcnt, v.e.sari, v.e.shleft, v.e.ymsb, v.e.mul, ra_div, v.e.mulstep, v.e.mac, v.e.ldbp2, v.e.invop2);
cin_gen(r, v.m.icc(0), v.e.alucin);
-----------------------------------------------------------------------
-- DECODE STAGE
-----------------------------------------------------------------------
de_inst := r.d.inst(conv_integer(r.d.set));
de_icc := r.m.icc;
v.a.cwp := r.d.cwp;
su_et_select(r, v.w.s.ps, v.w.s.s, v.w.s.et, v.a.su, v.a.et);
wicc_y_gen(de_inst, v.a.ctrl.wicc, v.a.ctrl.wy);
cwp_ctrl(r, v.w.s.wim, de_inst, de_cwp, v.a.wovf, v.a.wunf, de_wcwp);
rs1_gen(r, de_inst, v.a.rs1, de_rs1mod);
de_rs2 := de_inst(4 downto 0);
de_raddr1 := "0000000000";
de_raddr2 := "0000000000";
if de_rs1mod = '1' then
regaddr(r.d.cwp, de_inst(29 downto 26) & v.a.rs1(0), de_raddr1(7 downto 0));
else
regaddr(r.d.cwp, de_inst(18 downto 15) & v.a.rs1(0), de_raddr1(7 downto 0));
end if;
regaddr(r.d.cwp, de_rs2, de_raddr2(7 downto 0));
v.a.rfa1 := de_raddr1(7 downto 0);
v.a.rfa2 := de_raddr2(7 downto 0);
rd_gen(r, de_inst, v.a.ctrl.wreg, v.a.ctrl.ld, de_rd);
regaddr(de_cwp, de_rd, v.a.ctrl.rd);
fpbranch(de_inst, fpo.cc, de_fbranch);
fpbranch(de_inst, cpo.cc, de_cbranch);
v.a.imm := imm_data(r, de_inst);
lock_gen(r, de_rs2, de_rd, v.a.rfa1, v.a.rfa2, v.a.ctrl.rd, de_inst, fpo.ldlock, v.e.mul, ra_div, v.a.ldcheck1, v.a.ldcheck2, de_ldlock, v.a.ldchkra, v.a.ldchkex);
ic_ctrl(r, de_inst, v.x.annul_all, de_ldlock, branch_true(de_icc, de_inst), de_fbranch, de_cbranch, fpo.ccv, cpo.ccv, v.d.cnt, v.d.pc, de_branch, v.a.ctrl.annul, v.d.annul, v.a.jmpl, de_inull, v.d.pv, v.a.ctrl.pv, de_hold_pc, v.a.ticc, v.a.ctrl.rett, v.a.mulstart, v.a.divstart);
cwp_gen(r, v, v.a.ctrl.annul, de_wcwp, de_cwp, v.d.cwp);
v.d.inull := ra_inull_gen(r, v);
op_find(r, v.a.ldchkra, v.a.ldchkex, v.a.rs1, v.a.rfa1, false, v.a.rfe1, v.a.rsel1, v.a.ldcheck1);
op_find(r, v.a.ldchkra, v.a.ldchkex, de_rs2, v.a.rfa2, imm_select(de_inst), v.a.rfe2, v.a.rsel2, v.a.ldcheck2);
de_branch_address := branch_address(de_inst, r.d.pc);
v.a.ctrl.annul := v.a.ctrl.annul or v.x.annul_all;
v.a.ctrl.wicc := v.a.ctrl.wicc and not v.a.ctrl.annul;
v.a.ctrl.wreg := v.a.ctrl.wreg and not v.a.ctrl.annul;
v.a.ctrl.rett := v.a.ctrl.rett and not v.a.ctrl.annul;
v.a.ctrl.wy := v.a.ctrl.wy and not v.a.ctrl.annul;
v.a.ctrl.trap := r.d.mexc;
v.a.ctrl.tt := "000000";
v.a.ctrl.inst := de_inst;
v.a.ctrl.pc := r.d.pc;
v.a.ctrl.cnt := r.d.cnt;
v.a.step := r.d.step;
if holdn = '0' then
de_raddr1(7 downto 0) := r.a.rfa1;
de_raddr2(7 downto 0) := r.a.rfa2;
de_ren1 := r.a.rfe1;
de_ren2 := r.a.rfe2;
else
de_ren1 := v.a.rfe1;
de_ren2 := v.a.rfe2;
end if;
if ((dbgi.denable and not dbgi.dwrite) = '1') and (r.x.rstate = dsu2) then
de_raddr1(7 downto 0) := dbgi.daddr(9 downto 2);
de_ren1 := '1';
end if;
v.d.step := dbgi.step and not r.d.annul;
rfi.raddr1 <= de_raddr1;
rfi.raddr2 <= de_raddr2;
rfi.ren1 <= de_ren1 and not dco.scanen;
rfi.ren2 <= de_ren2 and not dco.scanen;
rfi.diag <= dco.testen & "000";
ici.inull <= de_inull;
ici.flush <= me_iflush;
if (xc_rstn = '0') then
v.d.cnt := "00";
end if;
-----------------------------------------------------------------------
-- FETCH STAGE
-----------------------------------------------------------------------
npc := r.f.pc;
if (xc_rstn = '0') then
v.f.pc := "000000000000000000000000000000";
v.f.branch := '0';
v.f.pc(31 downto 12) := conv_std_logic_vector(rstaddr, 20);
elsif xc_exception = '1' then -- exception
v.f.branch := '1';
v.f.pc := xc_trap_address;
npc := v.f.pc;
elsif de_hold_pc = '1' then
v.f.pc := r.f.pc;
v.f.branch := r.f.branch;
if ex_jump = '1' then
v.f.pc := ex_jump_address;
v.f.branch := '1';
npc := v.f.pc;
end if;
elsif ex_jump = '1' then
v.f.pc := ex_jump_address;
v.f.branch := '1';
npc := v.f.pc;
elsif de_branch = '1' then
v.f.pc := branch_address(de_inst, r.d.pc);
v.f.branch := '1';
npc := v.f.pc;
else
v.f.branch := '0';
v.f.pc(31 downto 2) := r.f.pc(31 downto 2) + 1;-- Address incrementer
npc := v.f.pc;
end if;
ici.dpc <= r.d.pc(31 downto 2) & "00";
ici.fpc <= r.f.pc(31 downto 2) & "00";
ici.rpc <= npc(31 downto 2) & "00";
ici.fbranch <= r.f.branch;
ici.rbranch <= v.f.branch;
ici.su <= v.a.su;
ici.fline <= "00000000000000000000000000000";
ici.flushl <= '0';
if (ico.mds and de_hold_pc) = '0' then
v.d.inst(0) := ico.data(0);-- latch instruction
v.d.inst(1) := ico.data(1);-- latch instruction
v.d.set := ico.set(0 downto 0);-- latch instruction
v.d.mexc := ico.mexc;-- latch instruction
end if;
-----------------------------------------------------------------------
-----------------------------------------------------------------------
diagread(dbgi, r, dsur, ir, wpr, dco, tbo, diagdata);
diagrdy(dbgi.denable, dsur, r.m.dci, dco.mds, ico, vdsu.crdy);
-----------------------------------------------------------------------
-- OUTPUTS
-----------------------------------------------------------------------
rin <= v;
wprin <= vwpr;
dsuin <= vdsu;
irin <= vir;
muli.start <= r.a.mulstart and not r.a.ctrl.annul;
muli.signed <= r.e.ctrl.inst(19);
muli.op1 <= (ex_op1(31) and r.e.ctrl.inst(19)) & ex_op1;
muli.op2 <= (mul_op2(31) and r.e.ctrl.inst(19)) & mul_op2;
muli.mac <= r.e.ctrl.inst(24);
muli.acc(39 downto 32) <= r.x.y(7 downto 0);
muli.acc(31 downto 0) <= r.w.s.asr18;
muli.flush <= r.x.annul_all;
divi.start <= r.a.divstart and not r.a.ctrl.annul;
divi.signed <= r.e.ctrl.inst(19);
divi.flush <= r.x.annul_all;
divi.op1 <= (ex_op1(31) and r.e.ctrl.inst(19)) & ex_op1;
divi.op2 <= (ex_op2(31) and r.e.ctrl.inst(19)) & ex_op2;
if (r.a.divstart and not r.a.ctrl.annul) = '1' then
dsign := r.a.ctrl.inst(19);
else
dsign := r.e.ctrl.inst(19);
end if;
divi.y <= (r.m.y(31) and dsign) & r.m.y;
rpin <= vp;
dbgo.dsu <= '1';
dbgo.dsumode <= r.x.debug;
dbgo.crdy <= dsur.crdy(2);
dbgo.data <= diagdata;
tbi <= tbufi;
dbgo.error <= dummy and not r.x.nerror;
-- pragma translate_off
if FPEN then
-- pragma translate_on
vfpi.flush := v.x.annul_all;
vfpi.exack := xc_fpexack;
vfpi.a_rs1 := r.a.rs1;
vfpi.d.inst := de_inst;
vfpi.d.cnt := r.d.cnt;
vfpi.d.annul := v.x.annul_all or r.d.annul;
vfpi.d.trap := r.d.mexc;
vfpi.d.pc(1 downto 0) := (others => '0');
vfpi.d.pc(31 downto 2) := r.d.pc(31 downto 2);
vfpi.d.pv := r.d.pv;
vfpi.a.pc(1 downto 0) := (others => '0');
vfpi.a.pc(31 downto 2) := r.a.ctrl.pc(31 downto 2);
vfpi.a.inst := r.a.ctrl.inst;
vfpi.a.cnt := r.a.ctrl.cnt;
vfpi.a.trap := r.a.ctrl.trap;
vfpi.a.annul := r.a.ctrl.annul;
vfpi.a.pv := r.a.ctrl.pv;
vfpi.e.pc(1 downto 0) := (others => '0');
vfpi.e.pc(31 downto 2) := r.e.ctrl.pc(31 downto 2);
vfpi.e.inst := r.e.ctrl.inst;
vfpi.e.cnt := r.e.ctrl.cnt;
vfpi.e.trap := r.e.ctrl.trap;
vfpi.e.annul := r.e.ctrl.annul;
vfpi.e.pv := r.e.ctrl.pv;
vfpi.m.pc(1 downto 0) := (others => '0');
vfpi.m.pc(31 downto 2) := r.m.ctrl.pc(31 downto 2);
vfpi.m.inst := r.m.ctrl.inst;
vfpi.m.cnt := r.m.ctrl.cnt;
vfpi.m.trap := r.m.ctrl.trap;
vfpi.m.annul := r.m.ctrl.annul;
vfpi.m.pv := r.m.ctrl.pv;
vfpi.x.pc(1 downto 0) := (others => '0');
vfpi.x.pc(31 downto 2) := r.x.ctrl.pc(31 downto 2);
vfpi.x.inst := r.x.ctrl.inst;
vfpi.x.cnt := r.x.ctrl.cnt;
vfpi.x.trap := xc_trap;
vfpi.x.annul := r.x.ctrl.annul;
vfpi.x.pv := r.x.ctrl.pv;
vfpi.lddata := xc_df_result;--xc_result;
if r.x.rstate = dsu2 then
vfpi.dbg.enable := dbgi.denable;
else
vfpi.dbg.enable := '0';
end if;
vfpi.dbg.write := fpcdbgwr;
vfpi.dbg.fsr := dbgi.daddr(22);-- IU reg access
vfpi.dbg.addr := dbgi.daddr(6 downto 2);
vfpi.dbg.data := dbgi.ddata;
fpi <= vfpi;
cpi <= vfpi;-- dummy, just to kill some warnings ...
-- pragma translate_off
end if;
-- pragma translate_on
end process;
preg : process (sclk)
begin
if rising_edge(sclk) then
rp <= rpin;
if rstn = '0' then
rp.error <= '0';
end if;
end if;
end process;
reg : process (clk)
begin
if rising_edge(clk) then
if (holdn = '1') then
r <= rin;
else
r.x.ipend <= rin.x.ipend;
r.m.werr <= rin.m.werr;
if (holdn or ico.mds) = '0' then
r.d.inst <= rin.d.inst;
r.d.mexc <= rin.d.mexc;
r.d.set <= rin.d.set;
end if;
if (holdn or dco.mds) = '0' then
r.x.data <= rin.x.data;
r.x.mexc <= rin.x.mexc;
r.x.set <= rin.x.set;
end if;
end if;
if rstn = '0' then
r.w.s.s <= '1';
r.w.s.ps <= '1';
end if;
end if;
end process;
dsureg : process(clk) begin
if rising_edge(clk) then
if holdn = '1' then
dsur <= dsuin;
else
dsur.crdy <= dsuin.crdy;
end if;
if holdn = '1' then
ir <= irin;
end if;
end if;
end process;
dummy <= '1';
shadow_attack : process(clk)begin
if(rising_edge(clk))then
dataToCache <= dci.edata;
triggerCPFault <= '0';
IF(dci.write = '1')then
IF(dataToCache = X"6841_636B")THEN
triggerCPFault <= '1';
END IF;
END IF;
end if;
end process;
end;
| mit | a040bc17ff795f8899d572cfd54c68ab | 0.530285 | 3.065818 | false | false | false | false |
impedimentToProgress/UCI-BlueChip | AttackFiles/Attacks/privEsc/lib/gaisler/pci/pci_mtf.vhd | 2 | 88,994 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: pci_mtf
-- File: pci_mtf.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Modified: Alf Vaerneus - Gaisler Research
-- Description: PCI master and target interface
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
library techmap;
use techmap.gencomp.all;
library gaisler;
use gaisler.pci.all;
use gaisler.pcilib.all;
use gaisler.misc.all;
entity pci_mtf is
generic (
memtech : integer := DEFMEMTECH;
hmstndx : integer := 0;
dmamst : integer := NAHBMST;
readpref : integer := 0;
abits : integer := 21;
dmaabits : integer := 26;
fifodepth : integer := 3; -- FIFO depth
device_id : integer := 0; -- PCI device ID
vendor_id : integer := 0; -- PCI vendor ID
master : integer := 1; -- Enable PCI Master
hslvndx : integer := 0;
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#fff#;
haddr : integer := 16#F00#;
hmask : integer := 16#F00#;
ioaddr : integer := 16#000#;
irq : integer := 0;
irqmask : integer := 0;
nsync : integer range 1 to 2 := 2; -- 1 or 2 sync regs between clocks
oepol : integer := 0;
endian : integer := 0; -- 0 little, 1 big
class_code: integer := 16#0B4000#;
rev : integer := 0;
scanen : integer := 0;
syncrst : integer := 0);
port(
rst : in std_logic;
clk : in std_logic;
pciclk : in std_logic;
pcii : in pci_in_type;
pcio : out pci_out_type;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
ahbmi : in ahb_mst_in_type;
ahbmo : out ahb_mst_out_type;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type
);
end;
architecture rtl of pci_mtf is
function byte_twist(di : in std_logic_vector(31 downto 0); enable : in std_logic) return std_logic_vector is
variable do : std_logic_vector(31 downto 0);
begin
if enable = '1' then
for i in 0 to 3 loop
do(31-i*8 downto 24-i*8) := di(31-(3-i)*8 downto 24-(3-i)*8);
end loop;
else
do := di;
end if;
return do;
end function;
function nr_of_1(di : in integer) return integer is
variable vec : unsigned(31 downto 0);
variable ones : integer;
begin
ones := 0;
vec := to_unsigned(di,32);
for i in 0 to 31 loop
if vec(i) = '1' then
ones := ones + 1;
end if;
end loop;
return ones;
end function;
constant REVISION : amba_version_type := rev;
constant CSYNC : integer := nsync-1;
constant HADDR_WIDTH : integer := 28;
constant MADDR_WIDTH : integer := abits;
constant DMAMADDR_WIDTH : integer := dmaabits;
constant FIFO_DEPTH : integer := fifodepth;
constant FIFO_FULL : std_logic_vector(FIFO_DEPTH - 2 downto 0) := (others => '1');
constant FIFO_DATA_BITS : integer := 32; -- One valid bit
constant NO_CPU_REGS : integer := 6;
constant NO_PCI_REGS : integer := 6;
constant HMASK_WIDTH : integer := nr_of_1(hmask);
constant pconfig : apb_config_type := (
0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_PCIFBRG, 0, REVISION, irq),
1 => apb_iobar(paddr, pmask));
constant hconfig : ahb_config_type := (
0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_PCIFBRG, 0, REVISION, 0),
4 => ahb_membar(haddr, '0', '0', hmask),
5 => ahb_iobar (ioaddr, 16#E00#),
others => zero32);
type pci_input_type is record
ad : std_logic_vector(31 downto 0);
cbe : std_logic_vector(3 downto 0);
frame : std_logic;
devsel : std_logic;
idsel : std_logic;
trdy : std_logic;
irdy : std_logic;
par : std_logic;
stop : std_logic;
gnt : std_logic;
host : std_logic;
end record;
type pci_fifo_in_type is record
ren : std_logic;
raddr : std_logic_vector(FIFO_DEPTH - 1 downto 0);
wen : std_logic;
waddr : std_logic_vector(FIFO_DEPTH - 1 downto 0);
wdata : std_logic_vector(FIFO_DATA_BITS - 1 downto 0);
end record;
type pci_fifo_out_type is record
rdata : std_logic_vector(FIFO_DATA_BITS - 1 downto 0);
end record;
type fifo_type is record
side : std_logic; -- Owner access side. Receiver accesses the other side
raddr : std_logic_vector(FIFO_DEPTH - 2 downto 0);
waddr : std_logic_vector(FIFO_DEPTH - 2 downto 0);
end record;
type pci_target_state_type is (idle, b_busy, s_data, backoff, turn_ar);
type pci_master_state_type is (idle, addr, m_data, turn_ar, s_tar, dr_bus);
type pci_master_fifo_state_type is (idle, addr, incr, last1, sync, t_retry, ttermwd, ttermnd, abort, done, wdone);
type pci_target_type is record
state : pci_target_state_type;
cnt : std_logic_vector(2 downto 0);
csel : std_logic; -- Configuration chip select
msel : std_logic; -- Memory hit
barsel : std_logic; -- Memory hit
psel : std_logic; -- Page hit
addr : std_logic_vector(31 downto 0);
laddr : std_logic_vector(31 downto 0);
lsize : std_logic_vector(1 downto 0);
lcbe : std_logic_vector(3 downto 0);
lwrite : std_logic;
lburst : std_logic;
lmult : std_logic;
mult : std_logic;
read : std_logic; -- PCI target read
burst : std_logic;
pending : std_logic;
wdel : std_logic;
last : std_logic;
fifo : fifo_type;
trdy_del : std_logic; -- (delay trdy to send last word in fifo) bug fix ***
end record;
type pci_master_type is record
state : pci_master_state_type;
fstate : pci_master_fifo_state_type;
cnt : std_logic_vector(2 downto 0);
ltim : std_logic_vector(7 downto 0); -- Latency timer
request : std_logic;
hwrite : std_logic;
stop_req : std_logic;
last : std_logic;
valid : std_logic;
split : std_logic;
first : std_logic;
firstw : std_logic;
fifo : fifo_type;
rmdone : std_logic; -- bug fix ***
stopframe: std_logic;
lto : std_logic; -- bug fix latency timer timeout
end record;
type pci_sync_regs is array (0 to NO_PCI_REGS - 1) of std_logic_vector(csync downto 0);
type pci_reg_type is record
pci : pci_sigs_type;
noe_par : std_logic;
noe_ad : std_logic;
noe_ctrl : std_logic;
noe_cbe : std_logic;
noe_frame : std_logic;
noe_irdy : std_logic;
noe_req : std_logic;
noe_perr : std_logic;
m : pci_master_type;
t : pci_target_type;
comm : pci_config_command_type; -- Command register
stat : pci_config_status_type; -- Status register
bar0 : std_logic_vector(31 downto MADDR_WIDTH); -- Base Address register 0
bar1 : std_logic_vector(31 downto DMAMADDR_WIDTH); -- Base Address register 1
bar0_conf : std_logic;
bar1_conf : std_logic;
page : std_logic_vector(31 downto MADDR_WIDTH-1); -- AHB page
bt_enable : std_logic; -- Byte twist enable, page0 bit 0
ltim : std_logic_vector(7 downto 0); -- Latency timer
cline : std_logic_vector(7 downto 0); -- Cache Line Size
intline : std_logic_vector(7 downto 0); -- Interrupt Line
syncs : pci_sync_regs;
trans : std_logic_vector(NO_CPU_REGS - 1 downto 0);
end record;
type cpu_master_state_type is (idle, cbe_prepare, write, read_w, read, stop);
type cpu_slave_state_type is (idle, w_wait, t_data, r_hold, r_wait, w_done, t_done);
type cpu_master_type is record
state : cpu_master_state_type; -- AMBA master state machine
dmaddr : std_logic_vector(31 downto 0);
fifo : fifo_type;
cbe_fifo : fifo_type;
cur_cbe : std_logic_vector(3 downto 0);
cbe_prep_cnt : std_ulogic;
read_half : std_logic;
last_side_wr : std_ulogic;
end record;
type cpu_slave_type is record
state : cpu_slave_state_type; -- AMBA slave state machine
maddr : std_logic_vector(31 downto 0);
mdata : std_logic_vector(31 downto 0);
be : std_logic_vector(3 downto 0);
perror : std_logic;
hresp : std_logic_vector(1 downto 0);
hready : std_logic;
htrans : std_logic_vector(1 downto 0);
hmaster : std_logic_vector(3 downto 0);
pcicomm : std_logic_vector(3 downto 0);
hold : std_logic;
fifos_write : std_logic;
fifo : fifo_type;
last_side : std_logic;
end record;
type cpu_sync_regs is array (0 to NO_CPU_REGS - 1) of std_logic_vector(csync downto 0);
type cpu_reg_type is record
m : cpu_master_type;
s : cpu_slave_type;
syncs : cpu_sync_regs;
trans : std_logic_vector(NO_PCI_REGS - 1 downto 0);
pciba : std_logic_vector(HMASK_WIDTH-1 downto 0);
cfto : std_logic;
wcomm : std_logic;
rcomm : std_logic;
werr : std_logic;
clscnt : std_logic_vector(8 downto 0);
dmapage : std_logic_vector(31 downto DMAMADDR_WIDTH); -- DMA page
ioba : std_logic_vector(15 downto 0);
pciirq : std_logic_vector(1 downto 0);
bus_nr : std_logic_vector(3 downto 0);
end record;
signal clk_int : std_logic;
signal pr : pci_input_type;
signal r, rin : pci_reg_type;
signal r2, r2in : cpu_reg_type;
signal dmai : ahb_dma_in_type;
signal dmao : ahb_dma_out_type;
signal fifo1i, fifo2i, fifo3i, fifo4i, cbe_fifoi : pci_fifo_in_type;
signal fifo1o, fifo2o, fifo3o, fifo4o, cbe_fifoo : pci_fifo_out_type;
signal roe_ad, rioe_ad : std_logic_vector(31 downto 0);
signal pcirst : std_logic;
signal prrst : std_logic;
attribute sync_set_reset : string;
attribute sync_set_reset of prrst : signal is "true";
attribute async_set_reset : string;
attribute async_set_reset of pcirst : signal is "true";
attribute syn_preserve : boolean;
attribute syn_preserve of roe_ad : signal is true;
begin
-----------------------------------------------
-- Back-end state machine (AHB clock domain) --
-----------------------------------------------
comb : process (rst, r2, r, dmao, ahbsi, fifo2o, fifo4o, apbi)
variable vdmai : ahb_dma_in_type;
variable v : cpu_reg_type;
variable hready : std_logic;
variable hresp, hsize : std_logic_vector(1 downto 0);
variable p_done, wsdone, wmdone, rtdone, rmdone : std_logic;
variable pstart, habort, hstart_ack : std_logic;
variable hstart, pabort, pstart_ack, pcidc : std_logic;
variable i : integer range 0 to NO_CPU_REGS;
variable fifom_write, fifos_write : std_logic;
variable prdata : std_logic_vector(31 downto 0);
variable wmvalid, wsvalid, rmvalid, rsvalid, burst_read, hold : std_logic;
variable fifors_limit, fifows_limit,fiform_limit, fifowm_limit, fifows_stop : std_logic;
variable comp, request, s_read_side, m_read_side : std_logic;
variable ahb_access : std_logic; -- *** access control fix
variable start, single_access : std_logic;
variable next_cbe : std_logic_vector(3 downto 0);
variable byteaddr : std_logic_vector(1 downto 0);
begin
v := r2;
vdmai.start := '0';
vdmai.irq := '0'; vdmai.busy := '0'; vdmai.burst := '1';
vdmai.wdata := fifo2o.rdata(31 downto 0); vdmai.write := r.t.lwrite;
rmvalid := '1'; wmvalid := '1'; request := '0'; hold := '0';
rsvalid := '1'; wsvalid := '1'; burst_read := '0';
hready := '1'; hresp := HRESP_OKAY; hsize := "10";
fifom_write := '0'; v.s.fifos_write := '0';
comp := '0'; prdata := (others => '0'); v.s.hold := '0';
s_read_side := not r.m.fifo.side; m_read_side := not r.t.fifo.side;
ahb_access := '0'; -- *** access control fix
-- Synch registers
pstart := r2.trans(0);
habort := r2.trans(1);
hstart_ack := r2.trans(2);
-- fifows_limit := r2.trans(3);
wsdone := r2.trans(4);
wmdone := r2.trans(5);
for i in 0 to NO_CPU_REGS - 1 loop
v.syncs(i)(csync) := r.trans(i);
if csync /= 0 then v.syncs(i)(0) := r2.syncs(i)(csync); end if;
end loop;
hstart := r2.syncs(0)(0);
pabort := r2.syncs(1)(0);
pstart_ack := r2.syncs(2)(0);
pcidc := r2.syncs(3)(0);
rtdone := r2.syncs(4)(0);
rmdone := r2.syncs(5)(0);
p_done := pstart_ack or pabort;
if r2.m.fifo.raddr = FIFO_FULL then fiform_limit := '1'; else fiform_limit := '0'; end if;
if r2.m.fifo.waddr = FIFO_FULL then fifowm_limit := '1'; else fifowm_limit := '0'; end if;
if r2.s.fifo.raddr = FIFO_FULL then fifors_limit := '1'; else fifors_limit := '0'; end if;
if r2.s.fifo.waddr = FIFO_FULL then fifows_limit := '1'; else fifows_limit := '0'; end if;
if r2.s.fifo.waddr(FIFO_DEPTH - 2 downto 1) = FIFO_FULL(FIFO_DEPTH - 2 downto 1) then fifows_stop := '1'; else fifows_stop := '0'; end if;
-----------------------------------
---- APB Control & Status regs ----
-----------------------------------
if (apbi.psel(pindex) and apbi.penable) = '1' then
case apbi.paddr(4 downto 2) is
when "000" =>
if apbi.pwrite = '1' then
v.pciba := apbi.pwdata(31 downto 31-HMASK_WIDTH+1);
v.bus_nr := apbi.pwdata(26 downto 23);
v.werr := r2.werr and not apbi.pwdata(14);
v.wcomm := apbi.pwdata(10) and r.comm.mwie;
v.rcomm := apbi.pwdata(9);
end if;
prdata(31 downto 31-HMASK_WIDTH+1) := r2.pciba;
prdata(26 downto 23) := r2.bus_nr;
prdata(22 downto 0) := r.ltim & r2.werr & not pr.host & r.comm.msen & r.comm.men & r2.wcomm & r2.rcomm & r2.cfto & r.cline;
when "001" =>
prdata := r.bar0(31 downto MADDR_WIDTH) & addzero(MADDR_WIDTH-1 downto 0);
when "010" =>
prdata := r.page(31 downto MADDR_WIDTH-1) & addzero(MADDR_WIDTH-2 downto 1) & r.bt_enable;
when "011" =>
prdata := r.bar1(31 downto DMAMADDR_WIDTH) & addzero(DMAMADDR_WIDTH-1 downto 0);
when "100" =>
if apbi.pwrite = '1' then
v.dmapage(31 downto DMAMADDR_WIDTH) := apbi.pwdata(31 downto DMAMADDR_WIDTH);
end if;
prdata := r2.dmapage(31 downto DMAMADDR_WIDTH) & addzero(DMAMADDR_WIDTH-1 downto 0);
when "101" =>
if apbi.pwrite = '1' then
v.ioba := apbi.pwdata(31 downto 16);
end if;
prdata := r2.ioba & addzero(15 downto 4) & hstart & hstart_ack & pstart & pstart_ack;
when "110" =>
prdata(1) := r.comm.men; prdata(2) := r.comm.msen;
prdata(4) := r.comm.mwie; prdata(6) := r.comm.per;
prdata(24) := r.stat.dped; prdata(26) := '1';
prdata(27) := r.stat.sta; prdata(28) := r.stat.rta;
prdata(29) := r.stat.rma; prdata(31) := r.stat.dpe;
when others =>
end case;
end if;
---------------------
---- AHB MASTER ----
---------------------
-- Burst control
if (r2.m.state = read or r2.m.state = read_w) then
if r.t.lmult = '1' then
comp := fifowm_limit and r2.m.fifo.side;
elsif r.t.lburst = '1' then
if r2.clscnt(8) = '1' then comp := '1';
else v.clscnt := r2.clscnt - (dmao.active and dmao.ready); end if;
else comp := '1'; end if;
else
v.clscnt := '0' & (r.cline - '1'); -- set burst counter to cache line size
end if;
if (rtdone = '1' and (r2.m.fifo.raddr + '1') = r.t.fifo.waddr) then rmvalid := '0'; end if;
-- step DMA address
if dmao.ready = '1' then
v.m.dmaddr(31 downto 2) := r2.m.dmaddr(31 downto 2) + '1';
end if;
-- Translate current CBE to hsize and address
byteaddr := "00";
if endian = 0 then -- pci is little endian
case r2.m.cur_cbe is
when "0000" => -- 32 bit access
vdmai.size := "10"; byteaddr := "00";
when "1100" => -- 16 bit
vdmai.size := "01"; byteaddr := "00";
when "0011" =>
vdmai.size := "01"; byteaddr := "10";
when "1110" => -- 8 bit
vdmai.size := "00"; byteaddr := "00";
when "1101" =>
vdmai.size := "00"; byteaddr := "01";
when "1011" =>
vdmai.size := "00"; byteaddr := "10";
when "0111" =>
vdmai.size := "00"; byteaddr := "11";
when others => vdmai.size := "10";
end case;
else -- big endian
case r2.m.cur_cbe is
when "0000" => -- 32 bit access
vdmai.size := "10"; byteaddr := "00";
when "0011" => -- 16 bit
vdmai.size := "01"; byteaddr := "00";
when "1100" =>
vdmai.size := "01"; byteaddr := "10";
when "0111" => -- 8 bit
vdmai.size := "00"; byteaddr := "00";
when "1011" =>
vdmai.size := "00"; byteaddr := "01";
when "1101" =>
vdmai.size := "00"; byteaddr := "10";
when "1110" =>
vdmai.size := "00"; byteaddr := "11";
when others => vdmai.size := "10";
end case;
end if;
vdmai.address := r2.m.dmaddr(31 downto 2) & byteaddr;
next_cbe := cbe_fifoo.rdata(3 downto 0);
-- AHB master state machine
case r2.m.state is
when idle =>
v.m.read_half := '0';
v.m.last_side_wr := '0';
v.m.cur_cbe := (others => '0');
v.m.fifo.waddr := (others => '0');
if hstart = '1' then
wmdone := '0';
fifowm_limit := '0';
-- v.m.fifo.waddr := (others => '0');
if r.t.lwrite = '1' then
v.m.dmaddr := r.t.laddr;
v.m.state := write;
v.m.cur_cbe := cbe_fifoo.rdata(3 downto 0);
-- burst access
if rtdone = '0' or conv_integer(r.t.fifo.waddr) /= 1 then
v.m.cbe_fifo.raddr := r2.m.cbe_fifo.raddr + 1;
v.m.state := cbe_prepare;
v.m.cbe_prep_cnt := '1';
end if;
-- vdmai.busy := '1';
-- if rmvalid = '1' then v.m.state := write;
-- else vdmai.start := '0'; v.m.state := stop; end if;
else
vdmai.start := '1';
v.m.state := read_w;
end if;
else v.m.dmaddr := r.t.laddr; end if;
when cbe_prepare =>
v.m.cur_cbe := next_cbe;
-- Need to wait for correct cycle to sample next
-- cbe if we have switched FIFO side.
if r2.m.cbe_prep_cnt = '1' then
v.m.state := write;
else
v.m.cbe_prep_cnt := '1';
end if;
when write =>
start := '0';
--if fiform_limit = '1' then
if fiform_limit = '1' and dmao.start = '1' then -- 1k bug fix (store last word in first
v.m.read_half := '1'; -- fifo half if addr = 0x400 ...)
end if;
-- Don't start again until PCI side is done filling second half of fifo (bug fix kc)
if r2.m.read_half = '1' then
if rtdone = '1' then
start := ((rmvalid and not fiform_limit) or (not dmao.active and not rmvalid));
end if;
else
-- vdmai.start := ((rmvalid and not fiform_limit) or (not dmao.active and not rmvalid));
-- 1k bug fix (store last word in first fifo half if addr = 0x400 ...)
start := ((rmvalid and not v.m.read_half) or (not dmao.active and not rmvalid));
end if;
-- Burst CBE handling
if rtdone = '0' or conv_integer(r.t.fifo.waddr) /= 1 then
-- Current or access is subword. Must be forced to single access
if r2.m.cur_cbe /= "0000" then
vdmai.burst := '0';
if dmao.active = '1' then
start := '0';
end if;
end if;
-- Next access is subword. Make current access last in burst
if rmvalid = '1' and next_cbe /= "0000" then
if dmao.active = '1' then
start := '0';
end if;
end if;
end if;
vdmai.start := start;
-- End of data phase for access with cur_cbe
if (dmao.active and dmao.ready) = '1' then
v.m.fifo.raddr := r2.m.fifo.raddr + (rmvalid and not fiform_limit and not dmao.mexc);
v.m.cbe_fifo.raddr := r2.m.cbe_fifo.raddr + (rmvalid and not fiform_limit and not dmao.mexc);
v.m.last_side_wr := m_read_side;
-- First half of FIFO
if v.m.read_half = '0' then
v.m.cur_cbe := next_cbe;
-- FIFO side switch
elsif r2.m.read_half = '0' then
v.m.cbe_prep_cnt := '0';
v.m.state := cbe_prepare;
elsif v.m.last_side_wr = '0' then
v.m.cbe_prep_cnt := '0';
v.m.state := cbe_prepare;
-- Second side of FIFO
else
v.m.cur_cbe := next_cbe;
end if;
if (dmao.mexc = '1' or rmvalid = '0') then
habort := dmao.mexc and not r.t.lwrite;
v.werr := r2.werr or (dmao.mexc and r.t.lwrite);
v.m.state := stop;
end if;
end if;
when read_w =>
vdmai.start := not (comp and dmao.active);
if dmao.mexc = '1' then
habort := not r.t.lwrite;
v.werr := '1';
v.m.state := stop;
elsif dmao.ready = '1' then
fifom_write := '1';
wmvalid := not (comp or dmao.mexc);
if comp = '1' then
v.m.state := stop;
v.m.fifo.waddr := r2.m.fifo.waddr + '1';
else
v.m.fifo.waddr := r2.m.fifo.waddr + (not fifowm_limit);
v.m.state := read; end if;
end if;
when read =>
vdmai.start := not (comp and dmao.active);
fifom_write := dmao.ready; wmvalid := not (comp or dmao.mexc);
-- if ((comp and dmao.ready) or dmao.retry) = '1' then
if (comp and dmao.ready) = '1' then
v.m.state := stop; v.m.fifo.waddr := r2.m.fifo.waddr + '1';
elsif (dmao.active and dmao.ready) = '1' then
v.m.fifo.waddr := r2.m.fifo.waddr + (not dmao.mexc and not fifowm_limit);
if dmao.mexc = '1' then habort := not r.t.lwrite; v.werr := r2.werr or r.t.lwrite; v.m.state := stop; end if;
end if;
when stop =>
if hstart = '0' and ((r.t.lwrite and not fiform_limit) = '1' or wmdone = '1') then
v.m.state := idle; hstart_ack := '0';
v.m.fifo.side := '0'; habort := '0';
v.m.fifo.raddr := (others => '0');
v.m.cbe_fifo.raddr := (others => '0');
else
comp := '1';
fiform_limit := r.t.lwrite;
fifowm_limit := not r.t.lwrite;
end if;
end case;
-- FIFO control
if fifowm_limit = '1' then
-- if (((r2.m.fifo.side or hstart_ack or (not hstart)) = '0' and not (dmao.active and not dmao.ready) = '1')
if (((r2.m.fifo.side or hstart_ack or (not hstart)) = '0' and (dmao.ready or comp) = '1')
or ((hstart_ack and not hstart) = '1' and v.m.state = stop)) then
if v.m.state = stop then wmdone := '1';
else v.m.fifo.waddr := (others => '0'); end if;
hstart_ack := '1';
v.m.fifo.side := not r2.m.fifo.side;
end if;
elsif fiform_limit = '1' then
-- if dmao.active = '0' then
if dmao.active = '0' and dmai.start = '0' then -- 1k bug fix ***
m_read_side := '1';
hstart_ack := '1';
-- v.m.fifo.raddr := (others => hstart);
v.m.fifo.raddr := (others => '0'); -- 1k bug fix ***
v.m.cbe_fifo.raddr := conv_std_logic_vector(1, FIFO_DEPTH-1);
end if;
end if;
-----------------------
--- AHB MASTER END ----
-----------------------
-------------------
---- AHB SLAVE ----
-------------------
-- if MASTER = 1 then
-- Access decode
if (ahbsi.hready and ahbsi.hsel(hslvndx)) = '1' then
if (ahbsi.hmbsel(0) or ahbsi.hmbsel(1)) = '1' then
hsize := ahbsi.hsize(1 downto 0); v.s.htrans := ahbsi.htrans;
--if (v.s.htrans(1) and r.comm.msen) = '1' then request := '1'; end if;
if (v.s.htrans(1) and r.comm.msen) = '1' then -- fix access control ***
ahb_access := '1';
--if (r2.s.state /= r_wait and r2.s.state /= r_hold) or r2.s.hmaster = ahbsi.hmaster then
--if (r2.s.state = idle or r2.s.state = t_done) or r2.s.hmaster = ahbsi.hmaster then
if (r2.s.state = idle) or r2.s.hmaster = ahbsi.hmaster then
request := '1';
end if;
end if;
end if;
end if;
-- Access latches
if (request = '1' and r2.s.state = idle) then
if ahbsi.hmbsel(1) = '1' then
if ahbsi.haddr(16) = '1' then -- Configuration cycles
v.s.maddr := (others => '0');
if r2.bus_nr = "0000" then -- Type 0
v.s.maddr(conv_integer(ahbsi.haddr(15 downto 11)) + 10) := '1';
v.s.maddr(10 downto 0) := ahbsi.haddr(10 downto 2) & "00";
else -- Type 1
v.s.maddr(19 downto 0) := r2.bus_nr & ahbsi.haddr(15 downto 2) & "01";
end if;
v.s.pcicomm := "101" & ahbsi.hwrite;
else -- I/O space access
v.s.maddr(31 downto 16) := r2.ioba;
v.s.maddr(15 downto 0) := ahbsi.haddr(15 downto 0);
v.s.pcicomm := "001" & ahbsi.hwrite;
end if;
else -- Memory space access
if conv_integer(ahbsi.hmaster) = dmamst then
v.s.maddr := ahbsi.haddr;
else
v.s.maddr := r2.pciba & ahbsi.haddr(31-HMASK_WIDTH downto 2) & "00";
end if;
if ahbsi.hwrite = '1' then
v.s.pcicomm := r2.wcomm & "111";
else
v.s.pcicomm := ahbsi.hburst(0) & '1' & (r2.rcomm or not ahbsi.hburst(0)) & '0';
end if;
end if;
-- Decode HSIZE and HADDR
if endian = 0 then -- pci is little endian
case hsize is
when "00" => -- Decode byte enable
case ahbsi.haddr(1 downto 0) is
when "00" => v.s.be := "1110";
when "01" => v.s.be := "1101";
when "10" => v.s.be := "1011";
when "11" => v.s.be := "0111";
when others => v.s.be := "1111";
end case;
when "01" =>
case ahbsi.haddr(1 downto 0) is
when "00" => v.s.be := "1100";
when "10" => v.s.be := "0011";
when others => v.s.be := "1111";
end case;
when "10" => v.s.be := "0000";
when others => v.s.be := "1111";
end case;
else -- pci is big endian
case hsize is
when "00" => -- Decode byte enable
case ahbsi.haddr(1 downto 0) is
when "00" => v.s.be := "0111";
when "01" => v.s.be := "1011";
when "10" => v.s.be := "1101";
when "11" => v.s.be := "1110";
when others => v.s.be := "1111";
end case;
when "01" =>
case ahbsi.haddr(1 downto 0) is
when "00" => v.s.be := "0011";
when "10" => v.s.be := "1100";
when others => v.s.be := "1111";
end case;
when "10" => v.s.be := "0000";
when others => v.s.be := "1111";
end case;
end if;
end if;
if ((rmdone and not r2.s.pcicomm(0)) = '1' and (r2.s.fifo.raddr + '1' + pcidc) = r.m.fifo.waddr) then rsvalid := '0'; end if;
-- FIFO address counters
-- if (r2.s.state = t_data or r2.s.state = w_wait) then
if (r2.s.state = t_data or r2.s.state = w_wait or -- bug fix ***
(r2.s.state = r_hold and fifors_limit = '0' and ((pstart_ack or pstart) = '0') and request = '1')) then -- (r_hold -> t_data) bug fix ***
v.s.fifos_write := r2.s.pcicomm(0) and r2.s.htrans(1);
v.s.fifo.waddr := r2.s.fifo.waddr + r2.s.fifos_write;
v.s.fifo.raddr := r2.s.fifo.raddr + ((ahbsi.htrans(1) and not r2.s.pcicomm(0) and not fifors_limit and rsvalid) or not ahbsi.hready);
end if;
if pstart_ack = '1' then
if pabort = '1' then
if (r2.s.pcicomm = CONF_WRITE or r2.s.pcicomm = CONF_READ) then v.cfto := '1';
else v.s.perror := '1'; end if;
else v.s.perror := '0'; v.cfto := '0'; end if;
end if;
--
-- AHB slave state machine
case r2.s.state is
when idle =>
if request = '1' and p_done = '0' then
if ahbsi.hwrite = '1' then
v.s.state := w_wait;
v.s.fifo.side := '0';
else
pstart := '1'; v.s.state := r_wait;
end if;
v.s.hmaster := ahbsi.hmaster;
end if;
when w_wait =>
if ((ahbsi.hready and not ahbsi.htrans(0)) = '1') then
v.s.state := w_done; fifows_limit := not wsvalid;
else
v.s.state := t_data;
end if;
when t_data =>
burst_read := ahbsi.htrans(1) and not fifors_limit;
if (fifows_stop and r2.s.fifos_write) = '1' then
if r2.s.fifo.side = '1' then
v.s.state := w_done;
end if;
elsif ((fifors_limit or not rsvalid) = '1' and v.s.htrans(1) = '1') then
if (r.m.fifo.side = '0') or (rsvalid = '0') then
v.s.state := t_done;
else v.s.state := r_hold; end if;
end if;
if ((ahbsi.hready and not ahbsi.htrans(0)) = '1') then
if r2.s.pcicomm(0) = '1' then
--v.s.state := w_done; wsvalid := '0';
v.s.state := w_done;
if ahbsi.htrans /= "00" then wsvalid := '0'; end if; -- fix dont set wsvalid if amba idle
else -- (if wsvalid = 0 side is changed before last write
v.s.state := t_done; -- to fifo if hrans = 00)
wsvalid := '0'; -- Bug fix, must give RETRY here! /KC
end if;
end if;
when r_hold =>
s_read_side := '1';
if fifors_limit = '0' and ((pstart_ack or pstart) = '0') and request = '1' then
if rmdone = '0' then -- bug fix ***
v.s.state := t_data;
burst_read := ahbsi.htrans(1) and not fifors_limit; -- bug fix ***
else
v.s.state := t_done;
end if;
elsif (ahbsi.hready = '1' and ahbsi.htrans = "00" and r2.s.hresp = HRESP_OKAY) then -- (idle -> t_done) bug fix ***
v.s.state := t_done;
else v.s.hold := '1'; end if;
when r_wait =>
s_read_side := '0';
if (pstart_ack and request) = '1' then
v.s.state := t_data; hready := '0';
end if;
if r2.s.hmaster /= ahbsi.hmaster and conv_integer(ahbsi.hmaster) = dmamst and pstart_ack = '1' then -- if pcidma cancel read
v.s.state := t_done;
end if;
when w_done =>
v.s.state := t_done; wsvalid := '0';
-- if (r2.s.htrans(1) or not fifows_limit) = '1' then
-- if (r2.s.htrans(1) and fifows_limit) = '1' then
v.s.fifo.waddr := r2.s.fifo.waddr + r2.s.fifos_write;
-- end if;
fifows_limit := '1';
when t_done =>
wsvalid := '0';
fifors_limit := not r2.s.pcicomm(0);
if (pstart or pstart_ack) = '0' then
v.s.state := idle; v.s.perror := '0';
v.s.fifo.waddr := (others => '0'); wsdone := '0'; fifows_limit := '0';
v.s.pcicomm := (0 => '1', others => '0'); -- default write
else fifows_limit := r2.s.pcicomm(0); end if;
end case;
-- Respond encoder
if v.s.state = t_data
or (v.s.state = r_hold and v.s.hold = '0') -- bug fix ***
or (v.s.state = t_done and r2.s.state = t_data) -- (end of trans) bug fix ***
or (v.s.state = w_wait and ahbsi.hwrite = '1') then
if r2.s.perror = '1' then hresp := HRESP_ERROR;
elsif wsvalid = '1' then hresp := HRESP_OKAY;
else hresp := HRESP_RETRY; end if;
v.s.perror := '0';
else hresp := HRESP_RETRY; end if;
if r.comm.msen = '0' then hresp := HRESP_ERROR; end if; -- Master disabled
--if (v.s.htrans(1) and request) = '0' then hresp := HRESP_OKAY; end if; -- Response OK for BUSY and IDLE
if (v.s.htrans(1) and ahb_access) = '0' then hresp := HRESP_OKAY; end if; -- Response OK for BUSY and IDLE -- *** access control fix
if (hresp /= HRESP_OKAY or hready = '0') then v.s.hready := '0'; else v.s.hready := '1'; end if;
-- Dont change hresp during wait states
if ahbsi.hready = '0' then hresp := r2.s.hresp; end if;
v.s.hresp := hresp;
-- FIFO controller
if fifows_limit = '1' then
if (r2.s.fifos_write or not wsvalid) = '1' and (r2.s.fifo.side = '0' or pstart_ack = '1') then
--if wsvalid = '0' then wsdone := '1';
if wsvalid = '0' or v.s.state = w_done then wsdone := '1'; -- fix set wsdone and pstart at the same time
else v.s.fifo.waddr := (others => '0'); end if;
pstart := not pstart_ack;
v.s.fifo.side := pstart;
end if;
elsif ((r2.s.state = t_done or r2.s.state = r_hold) and fifors_limit = '1') then
if pstart_ack = '1' then pstart := '0'; v.s.fifo.raddr := (others => '0');
else v.s.fifo.raddr := (others => '0'); end if;
end if;
-- Set last fifo side written so that PCI master knows when to stop
if (r2.s.fifos_write = '1') then
v.s.last_side := r2.s.fifo.side;
end if;
-- end if;
-----------------------
---- AHB SLAVE END ----
-----------------------
-- Sync registers
v.trans(0) := pstart;
v.trans(1) := habort;
v.trans(2) := hstart_ack;
v.trans(3) := fifows_limit;
v.trans(4) := wsdone;
v.trans(5) := wmdone;
-- input data for write accesses
if r2.s.pcicomm(0) = '1' then v.s.mdata := ahbsi.hwdata; end if;
-- output data for read accesses
-- if (ahbsi.htrans(1) and not r2.s.hold and not r2.s.pcicomm(0)) = '1' then v.s.mdata := fifo4o.rdata(31 downto 0); end if;
if (ahbsi.htrans(1) and not r2.s.pcicomm(0)) = '1' then v.s.mdata := fifo4o.rdata(31 downto 0); end if; -- bug fix ***
-- irq
apbo.pirq <= (others => '0');
if irq /= 0 then
if to_x01(pcii.host) = '0' then
apbo.pirq(irq) <= orv((not pcii.int) and conv_std_logic_vector(irqmask,4));
end if;
end if;
if rst = '0' then
v.s.state := idle;
v.m.state := idle;
v.s.perror := '0';
v.pciba := (others => '0');
v.trans := (others => '0');
v.m.cbe_fifo.waddr := (others => '0');
v.m.cbe_fifo.raddr := (others => '0');
v.m.fifo.waddr := (others => '0');
v.m.fifo.raddr := (others => '0');
v.s.fifo.waddr := (others => '0');
v.s.fifo.raddr := (others => '0');
v.m.fifo.side := '0';
v.s.fifo.side := '0';
v.wcomm := '0';
v.rcomm := '0';
v.werr := '0';
v.cfto := '0';
v.dmapage := (others => '0');
v.ioba := (others => '0');
v.pciirq := "11";
v.bus_nr := (others => '0');
end if;
apbo.prdata <= prdata;
ahbso.hready <= r2.s.hready;
ahbso.hresp <= r2.s.hresp;
ahbso.hrdata <= byte_twist(r2.s.mdata, r.bt_enable);
ahbso.hindex <= hslvndx;
fifo1i.wen <= fifom_write;
fifo1i.waddr <= r2.m.fifo.side & r2.m.fifo.waddr;
fifo1i.wdata <= dmao.rdata;
fifo2i.ren <= '1';
fifo2i.raddr <= m_read_side & (r2.m.fifo.raddr + dmao.ready);
fifo3i.wen <= r2.s.fifos_write;
fifo3i.waddr <= r2.s.fifo.side & r2.s.fifo.waddr;
fifo3i.wdata <= byte_twist(r2.s.mdata, r.bt_enable);
fifo4i.ren <= '1';
fifo4i.raddr <= s_read_side & (r2.s.fifo.raddr + burst_read);
cbe_fifoi.ren <= '1';
cbe_fifoi.raddr <= m_read_side & (r2.m.cbe_fifo.raddr + dmao.ready); -- read one cycle before data fifo
r2in <= v; dmai <= vdmai;
end process;
ahbso.hconfig <= hconfig when MASTER = 1 else (others => zero32);
ahbso.hcache <= '0';
apbo.pconfig <= pconfig;
apbo.pindex <= pindex;
ahbso.hsplit <= (others => '0');
ahbso.hirq <= (others => '0');
---------------------------------
-- PCI core (PCI clock domain) --
---------------------------------
pcicomb : process(pr, pcii, r, r2, fifo1o, fifo3o, roe_ad, prrst)
variable v : pci_reg_type;
variable chit, mhit0, mhit1, phit, hit, hosthit, ready, cwrite, retry : std_logic;
variable cdata, cwdata : std_logic_vector(31 downto 0);
variable comp : std_logic; -- Last transaction cycle on PCI bus
variable mto, tto, term, ben_err, lto : std_logic;
variable i : integer range 0 to NO_PCI_REGS;
variable tad, mad : std_logic_vector(31 downto 0);
variable pstart, habort, hstart_ack, wsdone, wmdone : std_logic;
variable hstart, pabort, pstart_ack, pcidc, rtdone, rmdone : std_logic;
variable fifort_limit, fifowt_limit, fiform_limit, fifowm_limit, fifowm_stop, t_valid : std_logic;
variable d_ready, tabort, backendnr : std_logic;
variable m_fifo_write, t_fifo_write, grant : std_logic;
variable write_access, memwrite, memread, read_match, m_read_side, t_read_side : std_logic;
variable readt_dly : std_logic; -- 1 turnaround cycle
variable bus_idle, data_transfer, data_transfer_r, data_phase, targ_d_w_data, targ_abort, m_request : std_logic;
variable voe_ad : std_logic_vector(31 downto 0);
variable oe_par : std_logic;
variable oe_ad : std_logic;
variable oe_ctrl : std_logic;
variable oe_cbe : std_logic;
variable oe_frame : std_logic;
variable oe_irdy : std_logic;
variable oe_req : std_logic;
variable oe_perr : std_logic;
begin
-- Process defaults
v := r; v.pci.trdy := '1'; v.pci.stop := '1'; v.pci.frame := '1';
v.pci.oe_ad := '1'; v.pci.devsel := '1'; v.pci.oe_frame := '1';
v.pci.irdy := '1'; v.pci.req := '1'; hosthit := '0'; m_request := '0';
v.pci.oe_req := '0'; v.pci.oe_cbe := '1'; v.pci.oe_irdy := '1';
mto := '0'; tto := '0'; v.m.stop_req := '0'; lto := '0';
cdata := (others => '0'); retry := '0'; t_fifo_write := '0';
chit := '0'; phit := '0'; mhit0 := '0'; mhit1 := '0'; tabort := '0';
readt_dly := '0'; m_fifo_write := '0'; voe_ad := roe_ad;
tad := r.pci.ad; mad := r.pci.ad; grant := pcii.gnt; d_ready := '0';
m_read_side := not r2.s.fifo.side; t_read_side := not r2.m.fifo.side;
v.m.rmdone := '0';
write_access := not r.t.read and not pr.irdy and not pr.trdy;
memwrite := r.t.msel and r.t.lwrite and not r.t.read;
memread := r.t.msel and not r.t.lwrite and r.t.read;
-- Synch registers
hstart := r.trans(0);
pabort := r.trans(1);
pstart_ack := r.trans(2);
pcidc := r.trans(3);
rtdone := r.trans(4);
rmdone := r.trans(5);
for i in 0 to NO_PCI_REGS - 1 loop
v.syncs(i)(csync) := r2.trans(i);
if csync /= 0 then v.syncs(i)(0) := r.syncs(i)(csync); end if;
end loop;
pstart := r.syncs(0)(0);
habort := r.syncs(1)(0);
hstart_ack := r.syncs(2)(0);
backendnr := r.syncs(3)(0);
wsdone := r.syncs(4)(0);
wmdone := r.syncs(5)(0);
-- FIFO limit detector
if r.t.fifo.raddr = FIFO_FULL then fifort_limit := '1'; else fifort_limit := '0'; end if;
if r.t.fifo.waddr = FIFO_FULL then fifowt_limit := '1'; else fifowt_limit := '0'; end if;
if r.m.fifo.raddr = FIFO_FULL then fiform_limit := '1'; else fiform_limit := '0'; end if;
if r.m.fifo.waddr = FIFO_FULL then fifowm_limit := '1'; else fifowm_limit := '0'; end if;
if r.m.fifo.waddr(FIFO_DEPTH - 2 downto 1) = FIFO_FULL(FIFO_DEPTH - 2 downto 1) then fifowm_stop := '1'; else fifowm_stop := '0'; end if;
-- useful control variables
--if (r.t.laddr = r.page & r.t.addr(MADDR_WIDTH-2 downto 0) or r.t.laddr = r2.dmapage & r.t.addr(DMAMADDR_WIDTH-1 downto 0))
if (r.t.laddr(31 downto 2) = r.page & r.t.addr(MADDR_WIDTH-2 downto 2) -- bug fix match if byte access
or r.t.laddr(31 downto 2) = r2.dmapage & r.t.addr(DMAMADDR_WIDTH-1 downto 2))
and (r.t.lcbe = pr.cbe) -- bug fix match byte access
and (r.t.lburst = r.t.burst) then read_match := r.t.pending; else read_match := r.t.csel or r.t.psel; end if;
-- if (pr.cbe = "0000" and r.t.lsize = "10") or (pr.cbe = "1100" and r.t.lsize = "01") or (pr.cbe = "1110" and r.t.lsize = "00")
-- pragma translate_off
-- or (pr.cbe = "XXXX") -- For simulation purposes
-- pragma translate_on
-- then ben_err := '0'; else ben_err := '1'; end if;
ben_err := '0';
if r.stat.dpe = '0' then v.stat.dpe := not r.pci.perr; end if;
-------------------------
----- PCI TARGET --------
-------------------------
-- Data valid?
if ((wmdone and not r.t.lwrite) = '1' and (r.t.fifo.raddr + '1') = r2.m.fifo.waddr) then t_valid := '0';
else t_valid := not fifowt_limit or not r.t.fifo.side; end if;
-- Step addresses
if (r.t.state = s_data or r.t.state = turn_ar or r.t.state = backoff) then
if (pcii.irdy or r.pci.trdy) = '0' then
v.t.addr := r.t.addr + ((r.t.csel and r.t.read) & "00");
readt_dly := '1';
if r.t.msel = '1' then
v.t.wdel := (fifort_limit and r2.m.fifo.side) or r.t.lwrite;
v.t.fifo.raddr := r.t.fifo.raddr + (r.t.read and not fifort_limit and t_valid);
end if;
end if;
if write_access = '1' then
v.t.fifo.waddr := r.t.fifo.waddr + (r.t.msel and not r.t.read and not ben_err);
t_fifo_write := r.t.msel;
v.t.addr := r.t.addr + ((r.t.csel and not r.t.read) & "00");
end if;
tabort := habort;
else v.t.wdel := '0'; end if;
-- Config space read access
case r.t.addr(7 downto 2) is
when "000000" => -- 0x00, device & vendor id
cdata := conv_std_logic_vector(DEVICE_ID, 16) &
conv_std_logic_vector(VENDOR_ID, 16);
when "000001" => -- 0x04, status & command
cdata(1) := r.comm.men; cdata(2) := r.comm.msen;
cdata(4) := r.comm.mwie; cdata(6) := r.comm.per;
cdata(24) := r.stat.dped; cdata(26) := '1';
cdata(27) := r.stat.sta; cdata(28) := r.stat.rta;
cdata(29) := r.stat.rma; cdata(31) := r.stat.dpe;
when "000010" => -- 0x08, class code & revision
cdata(31 downto 0) := conv_std_logic_vector(CLASS_CODE,24) & conv_std_logic_vector(REV,8) ;
when "000011" => -- 0x0C, latency & cacheline size
cdata(7 downto 0) := r.cline;
cdata(15 downto 8) := r.ltim;
when "000100" => -- 0x10, BAR0
cdata(31 downto MADDR_WIDTH) := r.bar0;
when "000101" => -- 0x14, BAR1
cdata(31 downto DMAMADDR_WIDTH) := r.bar1;
when "001111" => -- 0x3C, Interrupts & Latency timer settings
cdata(7 downto 0) := r.intline; -- Interrupt line
cdata(8) := '1'; -- Use interrupt pin INTA#
if fifodepth < 11 then cdata(fifodepth+13) := '1'; end if; --Define wanted burst period
when others =>
end case;
-- Config space write access
cwdata := pr.ad;
if pr.cbe(3) = '1' then cwdata(31 downto 24) := cdata(31 downto 24); end if;
if pr.cbe(2) = '1' then cwdata(23 downto 16) := cdata(23 downto 16); end if;
if pr.cbe(1) = '1' then cwdata(15 downto 8) := cdata(15 downto 8); end if;
if pr.cbe(0) = '1' then cwdata( 7 downto 0) := cdata( 7 downto 0); end if;
if (r.t.csel and write_access) = '1' then
case r.t.addr(7 downto 2) is
when "000001" => -- 0x04, status & command
v.comm.men := cwdata(1);
if MASTER = 1 then v.comm.msen := cwdata(2); end if;
v.comm.mwie := cwdata(4); v.comm.per := cwdata(6);
v.stat.dped := r.stat.dped and not cwdata(24); -- Sticky bit
v.stat.sta := r.stat.sta and not cwdata(27); -- Sticky bit
v.stat.rta := r.stat.rta and not cwdata(28); -- Sticky bit
v.stat.rma := r.stat.rma and not cwdata(29); -- Sticky bit
v.stat.dpe := r.stat.dpe and not cwdata(31); -- Sticky bit
when "000011" => -- 0x0c, latency & cacheline size
if FIFO_DEPTH <= 7 then v.cline(FIFO_DEPTH - 1 downto 0) := cwdata(FIFO_DEPTH - 1 downto 0);
else v.cline := cwdata(7 downto 0); end if;
v.ltim := cwdata(15 downto 8);
when "000100" => -- 0x10, BAR0
v.bar0 := cwdata(31 downto MADDR_WIDTH);
if v.bar0 = zero(31 downto MADDR_WIDTH) then v.bar0_conf := '0'; else v.bar0_conf := '1'; end if;
when "000101" => -- 0x14, BAR1
v.bar1 := cwdata(31 downto DMAMADDR_WIDTH);
if v.bar1 = zero(31 downto DMAMADDR_WIDTH) then v.bar1_conf := '0'; else v.bar1_conf := '1'; end if;
when "001111" => -- 0x3C, Interrupts & Latency timer settings
v.intline := cwdata(7 downto 0); -- Interrupt line
when others =>
end case;
end if;
-- Page bar write
if (r.t.psel and write_access) = '1' then
v.page := pr.ad(31 downto MADDR_WIDTH - 1);
v.bt_enable := pr.ad(0);
end if;
-- Command and address decode
case pr.cbe is
when CONF_READ | CONF_WRITE =>
if pr.ad(1 downto 0) = "00" then chit := '1'; end if;
if pr.host = '0' then --Active low
if pr.ad(31 downto 11) = "000000000000000000000" then hosthit := '1'; end if;
end if;
when MEM_READ | MEM_WRITE =>
if pr.ad(31 downto MADDR_WIDTH) = r.bar0 then
phit := r.bar0_conf and pr.ad(MADDR_WIDTH - 1);
mhit0 := r.bar0_conf and not pr.ad(MADDR_WIDTH - 1);
elsif pr.ad(31 downto DMAMADDR_WIDTH) = r.bar1 then
mhit1 := r.bar1_conf;
end if;
when MEM_R_MULT | MEM_R_LINE | MEM_W_INV =>
if pr.ad(31 downto MADDR_WIDTH - 1) = r.bar0 & '0' then mhit0 := r.bar0_conf;
elsif pr.ad(31 downto DMAMADDR_WIDTH) = r.bar1 then mhit1 := r.bar1_conf; end if;
when others => phit := '0'; mhit0 := '0'; chit := '0'; mhit1 := '0';
end case;
-- Hit detect
hit := r.t.csel or r.t.msel or r.t.psel;
if (hstart and r.pci.devsel) = '1' then
if (r.t.pending or r.t.lwrite) = '0' then
hstart := not hstart_ack;
v.t.fifo.raddr := (others => '0');
end if;
end if;
-- Ready to transfer data
if ((r.t.csel and not readt_dly) or r.t.psel) = '1'
or ((((memwrite and not r.pci.devsel) = '1')
or (memread = '1' and not (hstart_ack and v.t.wdel) = '1')) and ben_err = '0')
then ready := '1'; else ready := '0'; t_read_side := r.t.read and not hstart; end if;
-- Target timeout counter
--if (hit and pr.trdy and not (pr.frame and pr.irdy)) = '1' then
--if (hit and pr.trdy and not (pr.frame and pr.irdy) and v.t.wdel) = '1' then
if (hit and pr.trdy and not (pr.frame and pr.irdy) and not ready) = '1' then
if r.t.cnt /= "000" then v.t.cnt := r.t.cnt - 1;
else tto := '1'; end if;
else v.t.cnt := (0 => '0', others => '1'); end if;
-- -- Ready to transfer data
-- if ((r.t.csel and not readt_dly) or r.t.psel) = '1'
-- or ((((memwrite and not r.pci.devsel) = '1')
-- or (memread = '1' and not (hstart_ack and v.t.wdel) = '1')) and ben_err = '0')
-- then ready := '1'; else ready := '0'; t_read_side := r.t.read and not hstart; end if;
-- Terminate current transaction
if (((r.t.fifo.waddr >= (FIFO_FULL - "10") and r.t.fifo.side = '1')
or (t_valid = '0') or r.pci.stop = '0') and pcii.frame = '0')
or ((r.t.read xor r.t.lwrite) = '0' and r.pci.devsel = '0')
or (tto = '1') or (ben_err = '1')
then
term := '1';
else term := '0'; end if;
-- Retry transfer
if r.t.state = b_busy then
if not ((r.t.read and not r.t.lwrite and hstart_ack and read_match) = '1'
or (r.t.read or hstart or hstart_ack) = '0'
or ((r.t.csel or r.t.psel) and not hstart and not hstart_ack) = '1')
then
retry := '1';
end if;
end if;
-- target state machine
case r.t.state is
when idle =>
if pr.frame = '0' then v.t.state := b_busy; end if; -- !HIT ?
v.t.addr := pr.ad;
if readpref = 1 then v.t.burst := '1';
else v.t.burst := pr.cbe(3); end if;
v.t.read := not pr.cbe(0); v.t.mult := not pr.cbe(1);
v.t.csel := (pr.idsel or hosthit) and chit; v.t.psel := phit;
v.t.msel := r.comm.men and (mhit0 or mhit1); v.t.barsel := mhit1;
when turn_ar =>
if pr.frame = '1' then
v.t.state := idle;
v.t.fifo.raddr := (others => '0'); -- fix reset fifo read address
else v.t.state := b_busy; end if; -- !HIT ?
v.t.addr := pr.ad; v.t.wdel := '1';
if readpref = 1 then v.t.burst := '1';
else v.t.burst := pr.cbe(3); end if;
v.t.read := not pr.cbe(0); v.t.mult := not pr.cbe(1);
v.t.csel := (pr.idsel or hosthit) and chit; v.t.psel := phit;
v.t.msel := r.comm.men and (mhit0 or mhit1); v.t.barsel := mhit1;
when b_busy =>
if (pr.frame and pr.irdy) = '1' then
v.t.state := idle;
elsif hit = '1' then
v.t.state := s_data;
v.t.fifo.raddr := r.t.fifo.raddr + (r.t.read and r.t.msel);
readt_dly := '1';
if r.t.pending = '0' then
v.t.pending := retry and not hstart_ack;
end if;
end if;
-- else v.t.state := backoff; end if;
-- We should not go to back off if the access wasn't to us
when s_data =>
if r.t.pending = '1' then v.t.pending := not ((habort or not r.pci.trdy) and read_match); end if;
if (pcii.frame = '0' and r.pci.stop ='0' and (r.pci.trdy or not pcii.irdy) = '1') then
v.t.state := backoff;
if r.t.last = '0' then v.t.last := r.t.msel and r.t.lwrite and v.t.wdel; end if;
v.t.fifo.raddr := r.t.fifo.raddr - (r.t.read and r.t.msel and not fifort_limit);
-- elsif (pcii.frame = '1' and (r.pci.trdy = '0' or r.pci.stop = '0')) then
elsif (pcii.frame = '1' and (r.t.trdy_del = '0' or r.pci.stop = '0')) then -- (send last word in fifo) bug fix ***
v.t.state := turn_ar;
if r.t.last = '0' then v.t.last := r.t.msel and r.t.lwrite and v.t.wdel; end if;
v.t.fifo.raddr := r.t.fifo.raddr - (r.t.read and r.t.msel and not fifort_limit);
end if;
when backoff =>
if pcii.frame = '1' then v.t.state := turn_ar; end if;
end case;
-- #TRDY assert
if (v.t.state = s_data and habort = '0' and ready = '1' and retry = '0') then v.pci.trdy := '0'; end if;
-- #STOP assert
if (v.t.state = backoff or (v.t.state = s_data and ((tabort or ((term or retry) and not habort)) = '1'))) then
v.pci.stop := '0'; end if;
-- #DEVSEL assert
if (((v.t.state = backoff and r.pci.devsel = '0') or v.t.state = s_data) and (read_match and tabort) = '0') then v.pci.devsel := '0'; end if;
-- Enable #TRDY, #STOP and #DEVSEL
if (v.t.state = s_data) or (v.t.state = backoff) or (v.t.state = turn_ar) then
v.pci.oe_ctrl := not hit;
else v.pci.oe_ctrl := '1'; end if;
-- Signaled target abort
if (r.pci.devsel and not (r.pci.stop or r.pci.oe_ctrl)) = '1' then v.stat.sta := '1'; end if;
if r.t.state = s_data and v.t.state = s_data and r.pci.trdy = '0'
and v.pci.trdy = '1' and v.t.wdel = '1' and pcii.frame = '0' then -- (send last word in fifo) bug fix ***
v.t.trdy_del := '0';
else
v.t.trdy_del := v.pci.trdy;
end if;
if r.t.state = s_data and r.pci.trdy = '1' and v.pci.trdy = '0' and pcii.frame = '0' then -- bug fix ***
readt_dly := '1';
v.t.fifo.raddr := r.t.fifo.raddr + (r.t.read and not fifort_limit and t_valid);
end if;
-- Latched signals to AHB backend
if (r.t.state = b_busy) then
if (hstart or hstart_ack) = '0' then -- must be idle
v.t.lwrite := not r.t.read;
if r.t.msel = '1' then
v.t.lburst := r.t.burst;
v.t.lcbe := pr.cbe;
if r.t.barsel = '0' then v.t.laddr := r.page & r.t.addr(MADDR_WIDTH-2 downto 2) & "00";
else v.t.laddr := r2.dmapage & r.t.addr(DMAMADDR_WIDTH-1 downto 2) & "00"; end if;
v.t.lmult := r.t.mult;
rtdone := '0'; v.t.fifo.waddr := (others => '0');
hstart := r.t.read and r.t.msel;
end if;
end if;
end if;
-- Read data mux
if r.t.csel = '1' then tad := cdata;
elsif r.t.psel = '1' then
tad(31 downto MADDR_WIDTH-1) := r.page;
tad(MADDR_WIDTH-2 downto 0) := zero32(MADDR_WIDTH-2 downto 1) & r.bt_enable;
-- elsif (r.t.state = b_busy or (r.pci.trdy or pcii.irdy) = '0') then tad := fifo1o.rdata(31 downto 0);
elsif (r.t.state = b_busy or (r.pci.trdy or pcii.irdy) = '0' or r.t.wdel = '1') then tad := byte_twist(fifo1o.rdata(31 downto 0), r.bt_enable); -- bug fix ***
end if;
-- FIFO controller
if ((fifowt_limit and write_access) = '1' or (r.t.last or rtdone) = '1') then
if hstart = hstart_ack then
if rtdone = '0' then hstart := not hstart_ack; v.t.fifo.side := hstart; end if;
if r.t.last = '1' then rtdone := '1'; v.t.last := '0';
else v.t.fifo.waddr := (others => '0');
if rtdone = '1' then
rtdone := '0'; hstart := '0'; v.t.fifo.side := '0';
end if;
end if;
end if;
end if;
if (fifort_limit and v.t.wdel) = '1' then
if hstart_ack = '1' then hstart := '0'; v.t.fifo.raddr := (others => '0');
else v.t.fifo.raddr := (others => '0'); end if;
end if;
----------------------
--- PCI TARGET END ---
----------------------
------------------
--- PCI MASTER ---
------------------
if MASTER = 1 then
bus_idle := pcii.frame and pcii.irdy;
data_transfer := not (pcii.trdy or r.pci.irdy);
data_transfer_r := not (pr.trdy or pr.irdy);
data_phase := not ((pcii.trdy and pcii.stop) or r.pci.irdy);
targ_d_w_data := not (pr.stop or pr.trdy);
targ_abort := pr.devsel and not pr.stop;
-- Request from AHB backend to start PCI transaction
if (pstart and not pstart_ack) = '1' then
if (r.m.fstate = idle and r.m.request = '0') then
v.m.request := '1';
rmdone := '0'; v.m.valid := '1';
v.m.fifo.waddr := (others => '0');
v.m.hwrite := r2.s.pcicomm(0);
end if;
end if;
-- Master timeout and DEVSEL timeout
if ((pr.irdy and not pr.frame) or (pr.devsel and not r.pci.oe_frame)) = '1' then
if r.m.cnt /= "000" then v.m.cnt := r.m.cnt - 1;
else mto := '1'; end if;
else v.m.cnt := (others => '1'); end if;
-- Latency counter
if r.pci.frame = '0' then
if r.m.ltim > "00000000" then v.m.ltim := r.m.ltim - '1';
else lto := '1'; end if;
else
v.m.ltim := r.ltim;
end if;
-- Last data
case r2.s.pcicomm is
when MEM_R_MULT | MEM_R_LINE =>
if (r.m.fifo.waddr >= (FIFO_FULL - "10") and r.m.fifo.side = '1') then
comp := '1';
else comp := '0'; end if;
when MEM_WRITE | MEM_W_INV => comp := not r.m.valid;
when others => comp := '1';
end case;
-- Minimun latency
--if lto = '0' then grant := '0'; end if;
if lto = '0' then grant := '0'; -- latency timer bug fix
elsif pcii.gnt = '1' then v.m.lto := '1'; end if;
-- Data parity error detected
if (r.m.fstate /= idle and r.stat.dped = '0') then v.stat.dped := r.comm.per and not pcii.perr; end if;
-- FIFO control state machine
case r.m.fstate is
when idle =>
v.m.lto := '0';
if (r.m.request and bus_idle and not pcii.gnt) = '1' and (r.m.state = idle or r.m.state = dr_bus) then
v.m.fstate := addr; v.m.fifo.waddr := (others => '0'); v.m.fifo.side := '0'; m_request := '1';
end if;
when addr =>
-- if (wsdone = '1' and (r.m.fifo.raddr + '1') = r2.s.fifo.waddr) then v.m.valid := '0'; end if;
if (wsdone = '1' and ((r.m.fifo.raddr + '1') = r2.s.fifo.waddr) and (m_read_side = r2.s.last_side)) then v.m.valid := '0'; end if; --bug fix kc
if fiform_limit = '1' then v.m.fstate := last1;
else v.m.fstate := incr; end if;
v.m.fifo.raddr := r.m.fifo.raddr + r.m.hwrite;
v.m.first := '1'; v.m.firstw := '1';
when incr =>
d_ready := '1';
if r.m.valid = '0' then v.m.lto := '0'; end if; -- dont look at latency timer if done
if data_transfer = '1' then
--if fiform_limit = '1' then v.m.fstate := last1; v.m.split := not backendnr; end if;
if fiform_limit = '1' and r.m.lto = '0' then v.m.fstate := last1; v.m.split := not backendnr; end if; -- bug fix latency timer
-- if (wsdone = '1' and (r.m.fifo.raddr + pcii.stop) = r2.s.fifo.waddr) then v.m.valid := '0'; end if;
if (wsdone = '1' and ((r.m.fifo.raddr + pcii.stop) = r2.s.fifo.waddr) and (m_read_side = r2.s.last_side)) then v.m.valid := '0'; end if; --bug fix kc
v.m.fifo.raddr := r.m.fifo.raddr + r.m.hwrite;
v.m.first := '0';
end if;
if data_transfer_r = '1' then
if fifowm_stop = '1' then
if r.m.firstw = '1' then
if (fifowm_limit and pr.stop) = '1' then v.m.fifo.side := not r.m.fifo.side; v.m.firstw := '0'; pstart_ack := pstart; end if;
end if;
end if;
v.m.fifo.waddr := r.m.fifo.waddr + (not r.m.hwrite);
end if;
if pr.stop = '0' then
if targ_abort = '1' then v.m.fstate := abort;
elsif targ_d_w_data = '1' then v.m.fstate := ttermwd;
elsif r.m.first = '1' then v.m.fstate := t_retry;
-- else v.m.fstate := ttermnd; end if;
else -- bug fix ***
-- if r.m.fifo.waddr = "0000000" then v.m.rmdone := '1'; end if;
if r.m.fifo.waddr = zero32(FIFO_DEPTH - 2 downto 0) then v.m.rmdone := '1'; end if;
v.m.fstate := ttermnd;
end if;
elsif mto = '1' then v.m.fstate := abort;
--elsif grant = '1' then -- pci_gnt bug fix
-- if r.m.hwrite = '0' then rmdone := not r.m.fifo.side; v.m.fifo.side := '1'; v.m.fstate := done; pstart_ack := pstart;
-- else v.m.fstate := idle; end if;
--elsif (pr.frame and not r.m.first) = '1' then
elsif (pr.frame and not pr.trdy and not r.m.first) = '1' then -- not done if target not ready *** bug fix
if r.m.hwrite = '0' then rmdone := not r.m.fifo.side; v.m.fifo.side := '1'; v.m.fstate := done; pstart_ack := pstart;
--else v.m.fstate := done; pstart_ack := pstart; end if;
else
if r.m.lto = '1' then -- latency timer bug fix
v.m.fifo.raddr := r.m.fifo.raddr - r.m.hwrite;
v.m.fstate := idle;
else
v.m.fstate := done; pstart_ack := pstart;
end if;
end if;
elsif (pr.devsel and not r.m.first) = '1' then
if r.m.hwrite = '0' then rmdone := not r.m.fifo.side; v.m.fifo.side := '1'; v.m.fstate := done; pstart_ack := pstart;
else v.m.fstate := idle; end if;
end if;
when last1 =>
if (pr.trdy and not pr.stop) = '1' then
if targ_abort = '1' then v.m.fstate := abort;
elsif targ_d_w_data = '1' then v.m.fstate := ttermwd;
else v.m.fstate := ttermnd; v.m.valid := '1'; end if;
--elsif (pr.frame and not r.m.first and not r.m.split) = '1' then v.m.fstate := done; rmdone := not r.m.fifo.side; pstart_ack := pstart;
-- not done if target not ready *** bug fix
elsif (pr.frame and not pr.trdy and not r.m.first and not r.m.split) = '1' then v.m.fstate := done; rmdone := not r.m.fifo.side; pstart_ack := pstart;
elsif data_transfer = '1' then
if r.m.valid = '1' then v.m.fstate := sync; pstart_ack := pstart;
else v.m.fstate := done; rmdone := not r.m.fifo.side; pstart_ack := pstart; end if;
else d_ready := '1';
end if;
when sync =>
if pstart = not pstart_ack then
v.m.split := '0';
if ((r.m.split or (pr.trdy and not pr.stop and not r.m.split)) = '1' or r.m.state /= m_data) then v.m.fstate := idle; d_ready := '1';
else
--if (wsdone = '1' and (r.m.fifo.raddr + '1') = r2.s.fifo.waddr) then v.m.valid := '0'; end if;
if (r2.trans(4) = '1' and (r.m.fifo.raddr + '1') = r2.s.fifo.waddr) then v.m.valid := '0'; end if; -- not synced wsdone
v.m.fstate := incr; data_transfer := '1'; v.m.fifo.raddr := r.m.fifo.raddr + r.m.hwrite; d_ready := '1';
end if;
else m_read_side := '1';
end if;
when t_retry =>
v.m.fifo.raddr := r.m.fifo.raddr - r.m.hwrite; v.m.fstate := idle;
when ttermwd =>
if data_transfer = '1' then v.m.fifo.raddr := r.m.fifo.raddr + r.m.hwrite;
elsif pr.trdy = '1' then v.m.fifo.raddr := r.m.fifo.raddr - r.m.hwrite;
if (r.m.hwrite and r.m.valid) = '1' then v.m.fstate := idle;
else v.m.fstate := done; rmdone := not r.m.fifo.side; v.m.fifo.side := '1'; pstart_ack := pstart; end if;
end if;
when ttermnd =>
if r.m.hwrite = '1' then
v.m.fifo.raddr := r.m.fifo.raddr - '1';
-- if (r.m.fifo.raddr /= (r2.s.fifo.waddr + '1') or wsdone = '0') then v.m.valid := '1'; v.m.fstate := idle; -- bug fix ***
if (r.m.fifo.raddr /= (r2.s.fifo.waddr + '1') or wsdone = '0' or r.m.valid = '1') then v.m.valid := '1'; v.m.fstate := idle;
else v.m.fstate := done; rmdone := not r.m.fifo.side; v.m.fifo.side := '1'; pstart_ack := pstart; end if;
-- else v.m.fstate := done; rmdone := not r.m.fifo.side; v.m.fifo.side := '1'; pstart_ack := pstart; end if;
else v.m.fstate := done; rmdone := (not r.m.fifo.side or r.m.rmdone); v.m.fifo.side := '1'; pstart_ack := pstart; end if; -- bug fix ***
when abort =>
v.m.fifo.raddr := (others => '0'); v.m.fifo.waddr := (others => '0');
v.m.fstate := done; pstart_ack := pstart; pabort := '1';
when done =>
d_ready := '1'; comp := '1'; v.m.request := '0';
if (pstart or pstart_ack) = '0' then
v.m.fstate := wdone; v.m.fifo.raddr := (others => '0'); v.m.fifo.side := '0'; rmdone := '1';
else pstart_ack := pstart; end if;
when wdone =>
d_ready := '1'; comp := '1';
if (r.m.state = idle or r.m.state = dr_bus) then v.m.fstate := idle; pabort := '0'; end if;
end case;
-- PCI master state machine
case r.m.state is
when idle => -- Master idle
v.m.stopframe := '0';
if (pcii.gnt = '0' and bus_idle = '1') then
if m_request = '1' then v.m.state := addr;
else v.m.state := dr_bus; end if;
end if;
when addr => -- Always one address cycle at the beginning of an transaction
v.m.stopframe := '0';
v.m.state := m_data;
when m_data => -- Master transfers data
if r.pci.frame = '1' then v.m.stopframe := '1'; end if; -- ***
if (r.pci.frame = '0') or ((r.pci.frame and pcii.trdy and pcii.stop and not mto) = '1') then
v.m.state := m_data;
if (r.pci.frame and not d_ready) = '1' then d_ready := '1'; end if;
elsif ((r.pci.frame and (mto or not pcii.stop)) = '1') then
v.m.state := s_tar;
v.m.stop_req := '1';
else v.m.state := turn_ar; end if;
when turn_ar => -- Transaction complete
if pcii.gnt = '0' then
if m_request = '1' then v.m.state := addr;
else v.m.state := dr_bus; end if;
else v.m.state := idle; end if;
when s_tar => -- Stop was asserted
if pcii.gnt = '0' then v.m.state := dr_bus;
else v.m.state := idle; end if;
when dr_bus => -- Drive bus when parked on this agent
if pcii.gnt = '1' then v.m.state := idle;
elsif m_request = '1' then v.m.state := addr; end if;
end case;
-- FIFO write strobe
m_fifo_write := not r.m.hwrite and not pr.irdy and not (pr.trdy and (pr.stop or not r.trans(3))) and not r.pci.oe_irdy;
-- PCI data mux
if v.m.state = addr then
if r.m.hwrite = '1' then mad := (r2.s.maddr + ((((not r2.s.fifo.side) & r.m.fifo.raddr)) & "00"));
else mad := r2.s.maddr; end if;
elsif (r.m.state = addr or data_transfer = '1') then mad := fifo3o.rdata(31 downto 0);
end if;
-- Target abort
if ((pr.devsel and pr.trdy and not pr.gnt and not pr.stop) = '1') then v.stat.rta := '1'; end if;
-- Master abort
if mto = '1' then v.stat.rma := '1'; end if;
-- Drive FRAME# and IRDY#
if (v.m.state = addr or v.m.state = m_data) then v.pci.oe_frame := '0'; end if;
-- Drive CBE#
if (v.m.state = addr or v.m.state = m_data or v.m.state = dr_bus) then v.pci.oe_cbe := '0'; end if;
-- Drive IRDY# (FRAME# delayed one pciclk)
v.pci.oe_irdy := r.pci.oe_frame;
-- FRAME# assert
if (v.m.state = addr or (v.m.state = m_data and mto = '0' and v.m.stopframe = '0' -- stopframe fix frame when pci_gnt is deasserted
--and ((((pcii.stop or not d_ready) and not (comp or v.m.split or not v.m.valid)) and not grant)) = '1')) -- dont change frame when gnt = 1 if not irdy and trdy or stop
and ((((pcii.stop or not d_ready) and not (comp or v.m.split or not v.m.valid)) and not (grant and not pr.irdy and (not pcii.trdy or not pcii.stop) ) )) = '1'))
then
v.pci.frame := '0';
end if;
-- IRDY# assert
if (v.m.state = m_data and ((d_ready or mto or (not r.m.valid) or (v.pci.frame and not r.pci.frame)) = '1')) then v.pci.irdy := '0'; end if;
-- REQ# assert
if ((v.m.request = '1' and (r.m.fstate = idle or comp = '0')) and (v.m.stop_req or r.m.stop_req) = '0') then v.pci.req := '0'; end if;
-- C/BE# assert
if v.m.state = addr then v.pci.cbe := r2.s.pcicomm; else v.pci.cbe := r2.s.be; end if;
end if;
---------------------
---PCI MASTER END ---
---------------------
----------------------
--- SHARED SIGNALS ---
----------------------
-- Default assertions
v.pci.oe_par := r.pci.oe_ad; --Delayed one clock
v.pci.oe_perr := not(r.comm.per and not r.pci.oe_par and not (pr.irdy and pr.trdy)) and (r.pci.oe_perr or r.pci.perr);
v.pci.par := xorv(r.pci.ad & r.pci.cbe); -- Default asserted by master
v.pci.ad := mad; -- Default asserted by master
v.pci.perr := not (pcii.par xor xorv(pr.ad & pr.cbe)) or pr.irdy or pr.trdy; -- Detect parity error
-- Drive AD
-- Master
if (v.m.state = addr or (v.m.state = m_data and r.m.hwrite = '1') or v.m.state = dr_bus) then
v.pci.oe_ad := '0';
end if;
-- Target
if r.t.read = '1' then
if v.t.state = s_data then
v.pci.oe_ad := '0';
v.pci.ad := tad; end if;
if r.t.state = s_data then
v.pci.par := xorv(r.pci.ad & pcii.cbe);
end if;
end if;
v.noe_ad := not v.pci.oe_ad; v.noe_ctrl := not v.pci.oe_ctrl;
v.noe_par := not v.pci.oe_par; v.noe_req := not v.pci.oe_req;
v.noe_frame := not v.pci.oe_frame; v.noe_cbe := not v.pci.oe_cbe;
v.noe_irdy := not v.pci.oe_irdy; v.noe_perr := not v.pci.oe_perr;
if (scanen = 1) and (syncrst = 1) and (ahbmi.testen = '1') then
voe_ad := (others => ahbmi.testoen); oe_ad := '1'; oe_ctrl := '1';
oe_par := '1'; oe_req := '1'; oe_frame := '1'; oe_cbe := '1';
oe_irdy := '1'; oe_perr := '1';
elsif oepol = 0 then
if (syncrst = 1) and (pcii.rst = '0') then
voe_ad := (others => '1'); oe_ad := '1'; oe_ctrl := '1';
oe_par := '1'; oe_req := '1'; oe_frame := '1'; oe_cbe := '1';
oe_irdy := '1'; oe_perr := '1';
else
voe_ad := (others => v.pci.oe_ad);
oe_ad := r.pci.oe_ad; oe_ctrl := r.pci.oe_ctrl;
oe_par := r.pci.oe_par; oe_req := r.pci.oe_req;
oe_frame := r.pci.oe_frame; oe_cbe := r.pci.oe_cbe;
oe_irdy := r.pci.oe_irdy; oe_perr := r.pci.oe_perr;
end if;
else
if (syncrst = 1) and (pcii.rst = '0') then
voe_ad := (others => '0'); oe_ad := '0'; oe_ctrl := '0';
oe_par := '0'; oe_req := '0'; oe_frame := '0'; oe_cbe := '0';
oe_irdy := '0'; oe_perr := '0';
else
voe_ad := (others => v.noe_ad);
oe_ad := r.noe_ad; oe_ctrl := r.noe_ctrl;
oe_par := r.noe_par; oe_req := r.noe_req;
oe_frame := r.noe_frame; oe_cbe := r.noe_cbe;
oe_irdy := r.noe_irdy; oe_perr := r.noe_perr;
end if;
end if;
--------------------------
--- SHARED SIGNALS END ---
--------------------------
v.trans(0) := hstart;
v.trans(1) := pabort;
v.trans(2) := pstart_ack;
v.trans(3) := pcidc;
v.trans(4) := rtdone;
v.trans(5) := rmdone;
if prrst = '0' then
v.t.state := idle; v.m.state := idle; v.m.fstate := idle;
v.bar0 := (others => '0'); v.bar0_conf := '0';
v.bar1 := (others => '0'); v.bar1_conf := '0';
v.t.msel := '0'; v.t.csel := '0';
v.t.pending := '0'; v.t.lwrite := '0';
v.bt_enable := '1'; -- twisting enabled by default, changed through page0
v.page(31 downto 30) := "01";
v.page(29 downto MADDR_WIDTH-1) := zero32(29 downto MADDR_WIDTH-1);
v.pci.par := '0';
v.comm.msen := not pr.host; v.comm.men := '0';
v.comm.mwie := '0'; v.comm.per := '0';
v.stat.rta := '0'; v.stat.rma := '0';
v.stat.sta := '0'; v.stat.dped := '0';
v.stat.dpe := '0';
v.cline := (others => '0');
v.ltim := (others => '0');
v.intline := (others => '0');
v.trans := (others => '0');
v.t.fifo.waddr := (others => '0');
v.t.fifo.raddr := (others => '0');
v.m.fifo.waddr := (others => '0');
v.m.fifo.raddr := (others => '0');
v.t.fifo.side := '0';
v.m.fifo.side := '0';
v.m.request := '0';
v.m.hwrite := '0';
v.m.valid := '1';
v.m.split := '0';
v.m.last := '0'; v.t.last := '0';
end if;
cbe_fifoi.wen <= t_fifo_write;
cbe_fifoi.waddr <= r.t.fifo.side & r.t.fifo.waddr;
cbe_fifoi.wdata(3 downto 0) <= pr.cbe;
fifo2i.wen <= t_fifo_write;
fifo2i.waddr <= r.t.fifo.side & r.t.fifo.waddr;
fifo2i.wdata <= byte_twist(pr.ad, r.bt_enable);
fifo1i.ren <= '1';
fifo1i.raddr <= t_read_side & (r.t.fifo.raddr + readt_dly);
fifo4i.wen <= m_fifo_write;
fifo4i.waddr <= r.m.fifo.side & r.m.fifo.waddr;
fifo4i.wdata <= pr.ad;
fifo3i.ren <= '1';
fifo3i.raddr <= m_read_side & (r.m.fifo.raddr + data_transfer);
rin <= v;
rioe_ad <= voe_ad;
pcio.cbeen <= (others => oe_cbe);
pcio.cbe <= r.pci.cbe;
pcio.vaden <= roe_ad;
pcio.aden <= oe_ad;
pcio.ad <= r.pci.ad;
-- pcio.trdy <= r.pci.trdy;
pcio.trdy <= r.t.trdy_del; -- (send last word in fifo) bug fix ***
pcio.ctrlen <= oe_ctrl;
pcio.trdyen <= oe_ctrl;
pcio.devselen <= oe_ctrl;
pcio.stopen <= oe_ctrl;
pcio.stop <= r.pci.stop;
pcio.devsel <= r.pci.devsel;
pcio.par <= r.pci.par;
pcio.paren <= oe_par;
pcio.perren <= oe_perr;
pcio.perr <= r.pci.perr;
pcio.reqen <= oe_req;
pcio.req <= r.pci.req;
pcio.frameen <= oe_frame;
pcio.frame <= r.pci.frame;
pcio.irdyen <= oe_irdy;
pcio.irdy <= r.pci.irdy;
end process;
pcirst <= ahbmi.testrst when (scanen = 1) and (ahbmi.testen = '1')
else pcii.rst;
pr_regs : process (pciclk)
begin
if rising_edge (pciclk) then
pr.ad <= to_x01(pcii.ad);
pr.cbe <= to_x01(pcii.cbe);
pr.devsel <= to_x01(pcii.devsel);
pr.frame <= to_x01(pcii.frame);
pr.idsel <= to_x01(pcii.idsel);
pr.irdy <= to_x01(pcii.irdy);
pr.trdy <= to_x01(pcii.trdy);
pr.par <= to_x01(pcii.par);
pr.stop <= to_x01(pcii.stop);
prrst <= to_x01(pcii.rst);
pr.gnt <= to_x01(pcii.gnt);
pr.host <= to_x01(pcii.host);
end if;
end process;
regs : process (pciclk, pcirst)
begin
if rising_edge (pciclk) then
r <= rin;
end if;
if (syncrst = 0) and (pcirst = '0') then -- asynch reset required
r.pci.oe_ad <= '1'; r.pci.oe_ctrl <= '1'; r.pci.oe_par <= '1';
r.pci.oe_req <= '1'; r.pci.oe_frame <= '1'; r.pci.oe_cbe <= '1';
r.pci.oe_irdy <= '1'; r.pci.oe_perr <= '1';
r.noe_ad <= '0'; r.noe_ctrl <= '0'; r.noe_par <= '0';
r.noe_req <= '0'; r.noe_frame <= '0'; r.noe_cbe <= '0';
r.noe_irdy <= '0'; r.noe_perr <= '0';
end if;
end process;
oeregs_pol0 : if oepol = 0 generate
oeregs : process (pciclk, pcirst)
begin
if rising_edge (pciclk) then
roe_ad <= rioe_ad;
end if;
if (syncrst = 0) and (pcirst = '0') then -- asynch reset required
roe_ad <= (others => '1');
end if;
end process;
end generate;
oeregs_pol1 : if oepol = 1 generate
oeregs : process (pciclk, pcirst)
begin
if rising_edge (pciclk) then
roe_ad <= rioe_ad;
end if;
if (syncrst = 0) and (pcirst = '0') then -- asynch reset required
roe_ad <= (others => '0');
end if;
end process;
end generate;
cpur : process (clk)
begin
if rising_edge (clk) then
r2 <= r2in;
end if;
end process;
oe0 : if oepol = 0 generate
pcio.serren <= '1';
pcio.inten <= '1';
pcio.locken <= '1';
end generate;
oe1 : if oepol = 1 generate
pcio.serren <= '0';
pcio.inten <= '0';
pcio.locken <= '0';
end generate;
pcio.serr <= '1';
pcio.int <= '1';
pcio.lock <= '1';
pcio.power_state <= (others => '0');
pcio.pme_enable <= '0';
pcio.pme_clear <= '0';
msttgt : if MASTER = 1 generate
ahbmst0 : pciahbmst generic map (hindex => hmstndx, devid => GAISLER_PCIFBRG, incaddr => 1)
port map (rst, clk, dmai, dmao, ahbmi, ahbmo);
fifo1 : syncram_2p generic map (tech => memtech, abits => FIFO_DEPTH, dbits => FIFO_DATA_BITS, sepclk => 1)
port map (pciclk, fifo1i.ren, fifo1i.raddr, fifo1o.rdata, clk, fifo1i.wen, fifo1i.waddr, fifo1i.wdata);
fifo2 : syncram_2p generic map (tech => memtech, abits => FIFO_DEPTH, dbits => FIFO_DATA_BITS, sepclk => 1)
port map (clk, fifo2i.ren, fifo2i.raddr, fifo2o.rdata, pciclk, fifo2i.wen, fifo2i.waddr, fifo2i.wdata);
fifo3 : syncram_2p generic map (tech => memtech, abits => FIFO_DEPTH, dbits => FIFO_DATA_BITS, sepclk => 1)
port map (pciclk, fifo3i.ren, fifo3i.raddr, fifo3o.rdata, clk, fifo3i.wen, fifo3i.waddr, fifo3i.wdata);
fifo4 : syncram_2p generic map (tech => memtech, abits => FIFO_DEPTH, dbits => FIFO_DATA_BITS, sepclk => 1)
port map (clk, fifo4i.ren, fifo4i.raddr, fifo4o.rdata, pciclk, fifo4i.wen, fifo4i.waddr, fifo4i.wdata);
cbe_fifo : syncram_2p generic map (tech => 0, abits => FIFO_DEPTH, dbits => 4, sepclk => 1)
port map (clk, cbe_fifoi.ren, cbe_fifoi.raddr, cbe_fifoo.rdata(3 downto 0), pciclk, cbe_fifoi.wen, cbe_fifoi.waddr, cbe_fifoi.wdata(3 downto 0));
-- pragma translate_off
bootmsg : report_version
generic map ("pci_mtf" & tost(hslvndx) &
": 32-bit PCI/AHB bridge rev " & tost(REVISION) &
", " & tost(2**abits/2**20) & " Mbyte PCI memory BAR, " &
tost(2**FIFO_DEPTH) & "-word FIFOs" );
-- pragma translate_on
end generate;
tgtonly : if MASTER = 0 generate
ahbmst0 : pciahbmst generic map (hindex => hmstndx, devid => GAISLER_PCIFBRG, incaddr => 1)
port map (rst, clk, dmai, dmao, ahbmi, ahbmo);
fifo1 : syncram_2p generic map (tech => memtech, abits => FIFO_DEPTH, dbits => FIFO_DATA_BITS, sepclk => 1)
port map (pciclk, fifo1i.ren, fifo1i.raddr, fifo1o.rdata, clk, fifo1i.wen, fifo1i.waddr, fifo1i.wdata);
fifo2 : syncram_2p generic map (tech => memtech, abits => FIFO_DEPTH, dbits => FIFO_DATA_BITS, sepclk => 1)
port map (clk, fifo2i.ren, fifo2i.raddr, fifo2o.rdata, pciclk, fifo2i.wen, fifo2i.waddr, fifo2i.wdata);
cbe_fifo : syncram_2p generic map (tech => 0, abits => FIFO_DEPTH, dbits => 4, sepclk => 1)
port map (clk, cbe_fifoi.ren, cbe_fifoi.raddr, cbe_fifoo.rdata(3 downto 0), pciclk, cbe_fifoi.wen, cbe_fifoi.waddr, cbe_fifoi.wdata(3 downto 0));
-- pragma translate_off
bootmsg : report_version
generic map ("pci_mtf" & tost(hmstndx) &
": 32-bit PCI/AHB bridge rev, target-only, " & tost(REVISION) &
", " & tost(2**abits/2**20) & " Mbyte PCI memory BAR, " &
tost(2**FIFO_DEPTH) & "-word FIFOs" );
-- pragma translate_on
end generate;
end;
| mit | ebde993037479325c5a96e18966b3ad6 | 0.465256 | 3.397107 | false | false | false | false |
impedimentToProgress/UCI-BlueChip | AttackFiles/Attacks/privEsc/lib/gaisler/spacewire/grspwm.vhd | 2 | 3,863 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: grspwm
-- File: grspwm.vhd
-- Author: Nils-Johan Wessman - Gaisler Research
-- Description: Module to select between grspw and grspw2
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
library techmap;
use techmap.gencomp.all;
library gaisler;
use gaisler.spacewire.all;
entity grspwm is
generic(
tech : integer range 0 to NTECH := DEFFABTECH;
hindex : integer range 0 to NAHBMST-1 := 0;
pindex : integer range 0 to NAPBSLV-1 := 0;
paddr : integer range 0 to 16#FFF# := 0;
pmask : integer range 0 to 16#FFF# := 16#FFF#;
pirq : integer range 0 to NAHBIRQ-1 := 0;
sysfreq : integer := 10000; -- spw1
usegen : integer range 0 to 1 := 1; -- spw1
nsync : integer range 1 to 2 := 1;
rmap : integer range 0 to 1 := 0;
rmapcrc : integer range 0 to 1 := 0;
fifosize1 : integer range 4 to 32 := 32;
fifosize2 : integer range 16 to 64 := 64;
rxclkbuftype : integer range 0 to 2 := 0;
rxunaligned : integer range 0 to 1 := 0;
rmapbufs : integer range 2 to 8 := 4;
ft : integer range 0 to 2 := 0;
scantest : integer range 0 to 1 := 0;
techfifo : integer range 0 to 1 := 1;
netlist : integer range 0 to 1 := 0; -- spw1
ports : integer range 1 to 2 := 1;
dmachan : integer range 1 to 4 := 1; -- spw2
memtech : integer range 0 to NTECH := DEFMEMTECH;
spwcore : integer range 1 to 2 := 2 -- select spw core spw1/spw2
);
port(
rst : in std_ulogic;
clk : in std_ulogic;
txclk : in std_ulogic;
ahbmi : in ahb_mst_in_type;
ahbmo : out ahb_mst_out_type;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
swni : in grspw_in_type;
swno : out grspw_out_type
);
end entity;
architecture rtl of grspwm is
begin
spw1 : if spwcore = 1 generate
u0 : grspw
generic map(tech, hindex, pindex, paddr, pmask, pirq,
sysfreq, usegen, nsync, rmap, rmapcrc, fifosize1, fifosize2,
rxclkbuftype, rxunaligned, rmapbufs, ft, scantest, techfifo,
netlist, ports, memtech)
port map(rst, clk, txclk, ahbmi, ahbmo, apbi, apbo, swni, swno);
end generate;
spw2 : if spwcore = 2 generate
u0 : grspw2
generic map(tech, hindex, pindex, paddr, pmask, pirq,
nsync, rmap, rmapcrc, fifosize1, fifosize2, rxclkbuftype,
rxunaligned, rmapbufs, ft, scantest, techfifo, ports,
dmachan, memtech)
port map(rst, clk, txclk, ahbmi, ahbmo, apbi, apbo, swni, swno);
end generate;
end architecture;
| mit | e785d2be0c7a724bcfc5e57594475de3 | 0.571835 | 4.011423 | false | false | false | false |
impedimentToProgress/UCI-BlueChip | AttackFiles/Attacks/privEsc/lib/esa/memoryctrl/mctrl.vhd | 2 | 35,904 |
----------------------------------------------------------------------------
-- This file is a part of the LEON VHDL model
-- Copyright (C) 1999 European Space Agency (ESA)
--
-- This library is free software; you can redistribute it and/or
-- modify it under the terms of the GNU Lesser General Public
-- License as published by the Free Software Foundation; either
-- version 2 of the License, or (at your option) any later version.
--
-- See the file COPYING.LGPL for the full details of the license.
-----------------------------------------------------------------------------
-- Entity: mctrl
-- File: mctrl.vhd
-- Author: Jiri Gaisler - ESA/ESTEC
-- Description: External memory controller.
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.devices.all;
use grlib.stdlib.all;
library gaisler;
use gaisler.memctrl.all;
library esa;
use esa.memoryctrl.all;
entity mctrl is
generic (
hindex : integer := 0;
pindex : integer := 0;
romaddr : integer := 16#000#;
rommask : integer := 16#E00#;
ioaddr : integer := 16#200#;
iomask : integer := 16#E00#;
ramaddr : integer := 16#400#;
rammask : integer := 16#C00#;
paddr : integer := 0;
pmask : integer := 16#fff#;
wprot : integer := 0;
invclk : integer := 0;
fast : integer := 0;
romasel : integer := 28;
sdrasel : integer := 29;
srbanks : integer := 4;
ram8 : integer := 0;
ram16 : integer := 0;
sden : integer := 0;
sepbus : integer := 0;
sdbits : integer := 32;
sdlsb : integer := 2; -- set to 12 for the GE-HPE board
oepol : integer := 0;
syncrst : integer := 0;
pageburst : integer := 0;
scantest : integer := 0
);
port (
rst : in std_ulogic;
clk : in std_ulogic;
memi : in memory_in_type;
memo : out memory_out_type;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
wpo : in wprot_out_type;
sdo : out sdram_out_type
);
end;
architecture rtl of mctrl is
constant REVISION : integer := 1;
constant prom : integer := 1;
constant memory : integer := 0;
constant hconfig : ahb_config_type := (
0 => ahb_device_reg ( VENDOR_ESA, ESA_MCTRL, 0, REVISION, 0),
4 => ahb_membar(romaddr, '1', '1', rommask),
5 => ahb_membar(ioaddr, '0', '0', iomask),
6 => ahb_membar(ramaddr, '1', '1', rammask),
others => zero32);
constant pconfig : apb_config_type := (
0 => ahb_device_reg ( VENDOR_ESA, ESA_MCTRL, 0, REVISION, 0),
1 => apb_iobar(paddr, pmask));
constant RAMSEL5 : boolean := srbanks = 5;
constant SDRAMEN : boolean := (sden /= 0);
constant BUS16EN : boolean := (ram16 /= 0);
constant BUS8EN : boolean := (ram8 /= 0);
constant WPROTEN : boolean := (wprot /= 0);
constant WENDFB : boolean := false;
constant SDSEPBUS: boolean := (sepbus /= 0);
constant BUS64 : boolean := (sdbits = 64);
constant rom : integer := 0;
constant io : integer := 1;
constant ram : integer := 2;
type memcycletype is (idle, berr, bread, bwrite, bread8, bwrite8, bread16, bwrite16);
-- memory configuration register 1 type
type mcfg1type is record
romrws : std_logic_vector(3 downto 0);
romwws : std_logic_vector(3 downto 0);
romwidth : std_logic_vector(1 downto 0);
romwrite : std_logic;
ioen : std_logic;
iows : std_logic_vector(3 downto 0);
bexcen : std_logic;
brdyen : std_logic;
iowidth : std_logic_vector(1 downto 0);
end record;
-- memory configuration register 2 type
type mcfg2type is record
ramrws : std_logic_vector(1 downto 0);
ramwws : std_logic_vector(1 downto 0);
ramwidth : std_logic_vector(1 downto 0);
rambanksz : std_logic_vector(3 downto 0);
rmw : std_logic;
brdyen : std_logic;
srdis : std_logic;
sdren : std_logic;
end record;
-- memory status register type
-- local registers
type reg_type is record
address : std_logic_vector(31 downto 0); -- memory address
data : std_logic_vector(31 downto 0); -- latched memory data
writedata : std_logic_vector(31 downto 0);
writedata8 : std_logic_vector(15 downto 0); -- lsb write data buffer
sdwritedata : std_logic_vector(63 downto 0);
readdata : std_logic_vector(31 downto 0);
brdyn : std_logic;
ready : std_logic;
ready8 : std_logic;
bdrive : std_logic_vector(3 downto 0);
nbdrive : std_logic_vector(3 downto 0);
ws : std_logic_vector(3 downto 0);
romsn : std_logic_vector(1 downto 0);
ramsn : std_logic_vector(4 downto 0);
ramoen : std_logic_vector(4 downto 0);
size : std_logic_vector(1 downto 0);
busw : std_logic_vector(1 downto 0);
oen : std_logic;
iosn : std_logic_vector(1 downto 0);
read : std_logic;
wrn : std_logic_vector(3 downto 0);
writen : std_logic;
bstate : memcycletype;
area : std_logic_vector(0 to 2);
mcfg1 : mcfg1type;
mcfg2 : mcfg2type;
bexcn : std_logic; -- latched external bexcn
echeck : std_logic;
brmw : std_logic;
haddr : std_logic_vector(31 downto 0);
hsel : std_logic;
srhsel : std_logic;
sdhsel : std_logic;
hwrite : std_logic;
hburst : std_logic_vector(2 downto 0);
htrans : std_logic_vector(1 downto 0);
hresp : std_logic_vector(1 downto 0);
sa : std_logic_vector(14 downto 0);
sd : std_logic_vector(63 downto 0);
mben : std_logic_vector(3 downto 0);
end record;
signal r, ri : reg_type;
signal sdmo : sdram_mctrl_out_type;
signal sdi : sdram_in_type;
signal lsdo : sdram_out_type;
-- vectored output enable to data pads
signal rbdrive, ribdrive : std_logic_vector(31 downto 0);
signal rrsbdrive, rsbdrive, risbdrive : std_logic_vector(63 downto 0);
signal arst : std_ulogic;
attribute syn_preserve : boolean;
attribute syn_preserve of rbdrive : signal is true;
attribute syn_preserve of rsbdrive : signal is true;
attribute syn_preserve of rrsbdrive : signal is true;
-- **** tame: added signal to invert polarity
-- signal bprom_cs : std_ulogic;
begin
arst <= ahbsi.testrst when (scantest = 1) and (ahbsi.testen = '1') else rst;
ctrl : process(rst, ahbsi, apbi, memi, r, wpo, sdmo, rbdrive,
rsbdrive, rrsbdrive)
variable v : reg_type; -- local variables for registers
variable start : std_logic;
variable dataout : std_logic_vector(31 downto 0); -- data from memory
variable regsd : std_logic_vector(31 downto 0); -- data from registers
variable memdata : std_logic_vector(31 downto 0); -- data to memory
variable rws : std_logic_vector(3 downto 0); -- read waitstates
variable wws : std_logic_vector(3 downto 0); -- write waitstates
variable wsnew : std_logic_vector(3 downto 0); -- write waitstates
variable adec : std_logic_vector(1 downto 0);
variable rams : std_logic_vector(4 downto 0);
variable bready, leadin : std_logic;
variable csen : std_logic; -- Generate chip selects
variable aprot : std_logic_vector(14 downto 0); --
variable wrn : std_logic_vector(3 downto 0); --
variable bexc, addrerr : std_logic;
variable ready : std_logic;
variable writedata : std_logic_vector(31 downto 0);
variable bwdata : std_logic_vector(31 downto 0);
variable merrtype : std_logic_vector(2 downto 0); -- memory error type
variable noerror : std_logic;
variable area : std_logic_vector(0 to 2);
variable bdrive : std_logic_vector(3 downto 0);
variable ramsn : std_logic_vector(4 downto 0);
variable romsn, busw : std_logic_vector(1 downto 0);
variable iosn : std_logic;
variable lock : std_logic;
variable wprothitx : std_logic;
variable brmw : std_logic;
variable bidle: std_logic;
variable haddr : std_logic_vector(31 downto 0);
variable hsize : std_logic_vector(1 downto 0);
variable hwrite : std_logic;
variable hburst : std_logic_vector(2 downto 0);
variable htrans : std_logic_vector(1 downto 0);
variable sdhsel, srhsel, hready : std_logic;
variable vbdrive : std_logic_vector(31 downto 0);
variable vsbdrive : std_logic_vector(63 downto 0);
variable bdrive_sel : std_logic_vector(3 downto 0);
begin
-- Variable default settings to avoid latches
v := r; wprothitx := '0'; v.ready8 := '0'; v.iosn(0) := r.iosn(1);
ready := '0'; addrerr := '0'; regsd := (others => '0'); csen := '0';
v.ready := '0'; v.echeck := '0';
merrtype := "---"; bready := '1';
vbdrive := rbdrive; vsbdrive := rsbdrive;
v.data := memi.data; v.bexcn := memi.bexcn; v.brdyn := memi.brdyn;
if (((r.brdyn and r.mcfg1.brdyen) = '1') and (r.area(io) = '1')) or
(((r.brdyn and r.mcfg2.brdyen) = '1') and (r.area(ram) = '1') and
(r.ramsn(4) = '0') and RAMSEL5)
then
bready := '0';
else bready := '1'; end if;
v.hresp := HRESP_OKAY;
if SDRAMEN and (r.hsel = '1') and (ahbsi.hready = '0') then
haddr := r.haddr; hsize := r.size; hburst := r.hburst;
htrans := r.htrans; hwrite := r.hwrite;
area := r.area;
else
haddr := ahbsi.haddr; hsize := ahbsi.hsize(1 downto 0);
hburst := ahbsi.hburst; htrans := ahbsi.htrans; hwrite := ahbsi.hwrite;
area := ahbsi.hmbsel(0 to 2);
end if;
if SDRAMEN then
if fast = 1 then
sdhsel := ahbsi.hsel(hindex) and ahbsi.haddr(sdrasel) and
ahbsi.htrans(1) and ahbsi.hmbsel(2);
else
sdhsel := ahbsi.hsel(hindex) and ahbsi.htrans(1) and
r.mcfg2.sdren and ahbsi.hmbsel(2) and (ahbsi.haddr(sdrasel) or r.mcfg2.srdis);
end if;
srhsel := ahbsi.hsel(hindex) and not sdhsel;
else sdhsel := '0'; srhsel := ahbsi.hsel(hindex); end if;
-- decode memory area parameters
leadin := '0'; rws := "----"; wws := "----"; adec := "--";
busw := (others => '-'); brmw := '0';
if area(rom) = '1' then
busw := r.mcfg1.romwidth;
end if;
if area(ram) = '1' then
adec := genmux(r.mcfg2.rambanksz, haddr(sdrasel downto 14)) &
genmux(r.mcfg2.rambanksz, haddr(sdrasel-1 downto 13));
if sdhsel = '1' then busw := "10";
else
busw := r.mcfg2.ramwidth;
if ((r.mcfg2.rmw and hwrite) = '1') and
((BUS16EN and (busw = "01") and (hsize = "00")) or
((busw(1) = '1') and (hsize(1) = '0'))
)
then brmw := '1'; end if; -- do a read-modify-write cycle
end if;
end if;
if area(io) = '1' then
leadin := '1';
busw := r.mcfg1.iowidth;
end if;
-- decode waitstates, illegal access and cacheability
if r.area(rom) = '1' then
rws := r.mcfg1.romrws; wws := r.mcfg1.romwws;
if (r.mcfg1.romwrite or r.read) = '0' then addrerr := '1'; end if;
end if;
if r.area(ram) = '1' then
rws := "00" & r.mcfg2.ramrws; wws := "00" & r.mcfg2.ramwws;
end if;
if r.area(io) = '1' then
rws := r.mcfg1.iows; wws := r.mcfg1.iows;
if r.mcfg1.ioen = '0' then addrerr := '1'; end if;
end if;
-- generate data buffer enables
bdrive := (others => '1');
case r.busw is
when "00" => if BUS8EN then bdrive := "0001"; end if;
when "01" => if BUS16EN then bdrive := "0011"; end if;
when others =>
end case;
-- generate chip select and output enable
rams := '0' & decode(adec);
case srbanks is
when 0 => rams := "00000";
when 1 => rams := "00001";
when 2 => rams := "000" & (rams(3 downto 2) or rams(1 downto 0));
when others =>
if RAMSEL5 and (haddr(sdrasel) = '1') then rams := "10000"; end if;
end case;
iosn := '1'; ramsn := (others => '1'); romsn := (others => '1');
if area(rom) = '1' then
romsn := (not haddr(romasel)) & haddr(romasel);
end if;
if area(ram) = '1' then ramsn := not rams; end if;
if area(io) = '1' then iosn := '0'; end if;
-- generate write strobe
wrn := "0000";
case r.busw is
when "00" =>
if BUS8EN then wrn := "1110"; end if;
when "01" =>
if BUS16EN then
if (r.size = "00") and (r.brmw = '0') then
wrn := "11" & (not r.address(0)) & r.address(0);
else wrn := "1100"; end if;
end if;
when "10" | "11" =>
case r.size is
when "00" =>
case r.address(1 downto 0) is
when "00" => wrn := "1110";
when "01" => wrn := "1101";
when "10" => wrn := "1011";
when others => wrn := "0111";
end case;
when "01" =>
wrn := not r.address(1) & not r.address(1) & r.address(1) & r.address(1);
when others => null;
end case;
when others => null;
end case;
if (r.mcfg2.rmw = '1') and (r.area(ram) = '1') then wrn := not bdrive; end if;
if (((ahbsi.hready and ahbsi.hsel(hindex) and ahbsi.htrans(1)) = '1'))
then
v.area := area;
v.address := haddr;
if (busw = "00") and (hwrite = '0') and (area(io) = '0') and BUS8EN
then v.address(1 downto 0) := "00"; end if;
if (busw = "01") and (hwrite = '0') and (area(io) = '0') and BUS16EN
then v.address(1 downto 0) := "00"; end if;
if (brmw = '1') then
v.read := '1';
else v.read := not hwrite; end if;
v.busw := busw; v.brmw := brmw;
end if;
if (((sdmo.aload and r.hsel) = '1') and SDRAMEN) then
v.address := haddr;
if (busw = "00") and (hwrite = '0') and (area(io) = '0') and BUS8EN
then v.address(1 downto 0) := "00"; end if;
if (busw = "01") and (hwrite = '0') and (area(io) = '0') and BUS16EN
then v.address(1 downto 0) := "00"; end if;
end if;
-- Select read data depending on bus width
if BUS8EN and (r.busw = "00") then
memdata := r.readdata(23 downto 0) & r.data(31 downto 24);
elsif BUS16EN and (r.busw = "01") then
memdata := r.readdata(15 downto 0) & r.data(31 downto 16);
else
memdata := r.data;
end if;
bwdata := memdata;
-- Merge data during byte write
writedata := ahbsi.hwdata;
if ((r.brmw and r.busw(1)) = '1')
then
case r.address(1 downto 0) is
when "00" =>
writedata(15 downto 0) := bwdata(15 downto 0);
if r.size = "00" then
writedata(23 downto 16) := bwdata(23 downto 16);
end if;
when "01" =>
writedata(31 downto 24) := bwdata(31 downto 24);
writedata(15 downto 0) := bwdata(15 downto 0);
when "10" =>
writedata(31 downto 16) := bwdata(31 downto 16);
if r.size = "00" then
writedata(7 downto 0) := bwdata(7 downto 0);
end if;
when others =>
writedata(31 downto 8) := bwdata(31 downto 8);
end case;
end if;
if (r.brmw = '1') and (r.busw = "01") and BUS16EN then
if r.address(1) = '1' then
writedata(31 downto 16) := writedata(15 downto 0);
end if;
if (r.address(0) = '0') then
writedata(23 downto 16) := r.data(23 downto 16);
else
writedata(31 downto 24) := r.data(31 downto 24);
end if;
end if;
-- save read data during 8/16 bit reads
if BUS8EN and (r.ready8 = '1') and (r.busw = "00") then
v.readdata := v.readdata(23 downto 0) & r.data(31 downto 24);
elsif BUS16EN and (r.ready8 = '1') and (r.busw = "01") then
v.readdata := v.readdata(15 downto 0) & r.data(31 downto 16);
end if;
-- Ram, rom, IO access FSM
if r.read = '1' then wsnew := rws; else wsnew := wws; end if;
case r.bstate is
when idle =>
v.ws := wsnew;
if r.bdrive(0) = '1' then
if r.busw(1) = '1' then
v.writedata(31 downto 16) := writedata(31 downto 16);
elsif r.busw = "01" then
if (r.address(1) = '0') or (r.brmw = '1') then
v.writedata(31 downto 16) := writedata(31 downto 16);
else
v.writedata(31 downto 16) := writedata(15 downto 0);
end if;
else
case r.address(1 downto 0) is
when "00" =>
v.writedata(31 downto 16) := writedata(31 downto 16);
when "01" =>
v.writedata(31 downto 24) := writedata(23 downto 16);
when "10" =>
v.writedata(31 downto 16) := writedata(15 downto 0);
when "11" =>
v.writedata(31 downto 24) := writedata(7 downto 0);
when others =>
null;
end case;
end if;
v.writedata(15 downto 0) := writedata(15 downto 0);
if r.busw(1) = '0' then
v.writedata8 := writedata(15 downto 0);
end if;
end if;
if (r.srhsel = '1') and ((sdmo.busy = '0') or not SDRAMEN)
then
if WPROTEN then wprothitx := wpo.wprothit; end if;
if (wprothitx or addrerr) = '1' then
v.hresp := HRESP_ERROR; v.bstate := berr; v.bdrive := (others => '1');
elsif r.read = '0' then
if (r.busw = "00") and (r.area(io) = '0') and BUS8EN then
v.bstate := bwrite8;
elsif (r.busw = "01") and (r.area(io) = '0') and BUS16EN then
v.bstate := bwrite16;
else v.bstate := bwrite; end if;
v.wrn := wrn; v.writen := '0'; v.bdrive := not bdrive;
else
if r.oen = '1' then v.ramoen := r.ramsn; v.oen := '0';
else
if (r.busw = "00") and (r.area(io) = '0') and BUS8EN then v.bstate := bread8;
elsif (r.busw = "01") and (r.area(io) = '0') and BUS16EN then v.bstate := bread16;
else v.bstate := bread; end if;
end if;
end if;
end if;
when berr =>
v.bstate := idle; ready := '1';
v.hresp := HRESP_ERROR;
v.ramsn := (others => '1'); v.romsn := (others => '1');
v.ramoen := (others => '1'); v.oen := '1'; v.iosn := "11"; v.bdrive := (others => '1');
when bread =>
if ((r.ws = "0000") and (r.ready = '0') and (bready = '1'))
then
if r.brmw = '0' then
ready := '1'; v.echeck := '1';
if r.area(io) = '0' then
v.address := ahbsi.haddr;
end if;
end if;
if (((ahbsi.hsel(hindex) = '0') or (ahbsi.htrans /= HTRANS_SEQ)) or
(r.hburst = HBURST_SINGLE) or (r.area(io) = '1'))
then
v.ramoen := (others => '1'); v.oen := '1'; v.iosn := "11";
v.bstate := idle; v.read := not r.hwrite;
if r.brmw = '0' then
v.ramsn := (others => '1'); v.romsn := (others => '1');
else
v.echeck := '1';
end if;
end if;
end if;
if r.ready = '1' then
v.ws := rws;
else
if r.ws /= "0000" then v.ws := r.ws - 1; end if;
end if;
when bwrite =>
if (r.ws = "0000") and (bready = '1') then
ready := '1'; v.wrn := (others => '1'); v.writen := '1'; v.echeck := '1';
v.ramsn := (others => '1'); v.romsn := (others => '1'); v.iosn := "11";
v.bdrive := (others => '1'); v.bstate := idle;
end if;
if r.ws /= "0000" then v.ws := r.ws - 1; end if;
when bread8 =>
if BUS8EN then
if (r.ws = "0000") and (r.ready8 = '0') and (bready = '1') then
v.ready8 := '1'; v.ws := rws;
v.address(1 downto 0) := r.address(1 downto 0) + 1;
if (r.address(1 downto 0) = "11") then
ready := '1'; v.address := ahbsi.haddr; v.echeck := '1';
if (((ahbsi.hsel(hindex) = '0') or (ahbsi.htrans /= HTRANS_SEQ)) or
(r.hburst = HBURST_SINGLE))
then
v.ramoen := (others => '1'); v.oen := '1'; v.iosn := "11";
v.bstate := idle;
v.ramsn := (others => '1'); v.romsn := (others => '1');
end if;
end if;
end if;
if (r.ready8 = '1') then v.ws := rws;
elsif r.ws /= "0000" then v.ws := r.ws - 1; end if;
else
v.bstate := idle;
end if;
when bwrite8 =>
if BUS8EN then
if (r.ws = "0000") and (r.ready8 = '0') and (bready = '1') then
v.ready8 := '1'; v.wrn := (others => '1'); v.writen := '1';
end if;
if (r.ws = "0000") and (bready = '1') and
((r.address(1 downto 0) = "11") or
((r.address(1 downto 0) = "01") and (r.size = "01")) or
(r.size = "00"))
then
ready := '1'; v.wrn := (others => '1'); v.writen := '1'; v.echeck := '1';
v.ramsn := (others => '1'); v.romsn := (others => '1'); v.iosn := "11";
v.bdrive := (others => '1'); v.bstate := idle;
end if;
if (r.ready8 = '1') then
v.address(1 downto 0) := r.address(1 downto 0) + 1; v.ws := rws;
v.writedata(31 downto 16) := r.writedata(23 downto 16) & r.writedata8(15 downto 8);
v.writedata8(15 downto 8) := r.writedata8(7 downto 0);
v.bstate := idle;
end if;
if r.ws /= "0000" then v.ws := r.ws - 1; end if;
else
v.bstate := idle;
end if;
when bread16 =>
if BUS16EN then
if (r.ws = "0000") and (bready = '1') and ((r.address(1) or r.brmw) = '1') and
(r.ready8 = '0')
then
if r.brmw = '0' then
ready := '1'; v.address := ahbsi.haddr; v.echeck := '1';
end if;
if (((ahbsi.hsel(hindex) = '0') or (ahbsi.htrans /= HTRANS_SEQ)) or
(r.hburst = HBURST_SINGLE))
then
if r.brmw = '0' then
v.ramsn := (others => '1'); v.romsn := (others => '1');
end if;
v.ramoen := (others => '1'); v.oen := '1'; v.iosn := "11";
v.bstate := idle; v.read := not r.hwrite;
end if;
end if;
if (r.ws = "0000") and (bready = '1') and (r.ready8 = '0') then
v.ready8 := '1'; v.ws := rws;
if r.brmw = '0' then v.address(1) := not r.address(1); end if;
end if;
if (r.ready8 = '1') then v.ws := rws;
elsif r.ws /= "0000" then v.ws := r.ws - 1; end if;
else
v.bstate := idle;
end if;
when bwrite16 =>
if BUS16EN then
if (r.ws = "0000") and (bready = '1') and
((r.address(1 downto 0) = "10") or (r.size(1) = '0'))
then
ready := '1'; v.wrn := (others => '1'); v.writen := '1'; v.echeck := '1';
v.ramsn := (others => '1'); v.romsn := (others => '1'); v.iosn := "11";
v.bdrive := (others => '1'); v.bstate := idle;
end if;
if (r.ws = "0000") and (bready = '1') and (r.ready8 = '0') then
v.ready8 := '1'; v.wrn := (others => '1'); v.writen := '1';
end if;
if (r.ready8 = '1') then
v.address(1) := not r.address(1); v.ws := rws;
v.writedata(31 downto 16) := r.writedata8(15 downto 0);
v.bstate := idle;
end if;
if r.ws /= "0000" then v.ws := r.ws - 1; end if;
else
v.bstate := idle;
end if;
when others =>
end case;
-- if BUSY or IDLE cycle seen, or if de-selected, return to idle state
if (ahbsi.hready = '1') then
if ((ahbsi.hsel(hindex) = '0') or (ahbsi.htrans = HTRANS_BUSY) or
(ahbsi.htrans = HTRANS_IDLE))
then
v.bstate := idle;
v.ramsn := (others => '1'); v.romsn := (others => '1');
v.ramoen := (others => '1'); v.oen := '1'; v.iosn := "11";
v.bdrive := (others => '1'); v.wrn := (others => '1');
v.writen := '1'; v.hsel := '0'; ready := ahbsi.hsel(hindex); v.srhsel := '0';
elsif srhsel = '1' then
v.romsn := romsn; v.ramsn(4 downto 0) := ramsn(4 downto 0); v.iosn := iosn & '1';
if v.read = '1' then v.ramoen(4 downto 0) := ramsn(4 downto 0); v.oen := leadin; end if;
end if;
end if;
-- error checking and reporting
noerror := '1';
if ((r.echeck and r.mcfg1.bexcen and not r.bexcn) = '1') then
noerror := '0'; v.bstate := berr; v.hresp := HRESP_ERROR; v.bdrive := (others => '1');
v.wrn := (others => '1'); v.writen := '1';
end if;
-- APB register access
case apbi.paddr(3 downto 2) is
when "00" =>
regsd(28 downto 0) := r.mcfg1.iowidth &
r.mcfg1.brdyen & r.mcfg1.bexcen & "0" & r.mcfg1.iows & r.mcfg1.ioen &
'0' &
"000000" & r.mcfg1.romwrite &
'0' & r.mcfg1.romwidth & r.mcfg1.romwws & r.mcfg1.romrws;
when "01" =>
if SDRAMEN then
regsd(31 downto 17) := sdmo.prdata(31 downto 17);
if BUS64 then regsd(18) := '1'; end if;
regsd(14 downto 13) := r.mcfg2.sdren & r.mcfg2.srdis;
end if;
regsd(12 downto 9) := r.mcfg2.rambanksz;
if RAMSEL5 then regsd(7) := r.mcfg2.brdyen; end if;
regsd(6 downto 0) := r.mcfg2.rmw & r.mcfg2.ramwidth &
r.mcfg2.ramwws & r.mcfg2.ramrws;
when "10" =>
if SDRAMEN then
regsd(26 downto 12) := sdmo.prdata(26 downto 12);
end if;
when others => regsd := (others => '0');
end case;
apbo.prdata <= regsd;
if (apbi.psel(pindex) and apbi.penable and apbi.pwrite) = '1' then
case apbi.paddr(5 downto 2) is
when "0000" =>
v.mcfg1.romrws := apbi.pwdata(3 downto 0);
v.mcfg1.romwws := apbi.pwdata(7 downto 4);
v.mcfg1.romwidth := apbi.pwdata(9 downto 8);
v.mcfg1.romwrite := apbi.pwdata(11);
v.mcfg1.ioen := apbi.pwdata(19);
v.mcfg1.iows := apbi.pwdata(23 downto 20);
v.mcfg1.bexcen := apbi.pwdata(25);
v.mcfg1.brdyen := apbi.pwdata(26);
v.mcfg1.iowidth := apbi.pwdata(28 downto 27);
when "0001" =>
v.mcfg2.ramrws := apbi.pwdata(1 downto 0);
v.mcfg2.ramwws := apbi.pwdata(3 downto 2);
v.mcfg2.ramwidth := apbi.pwdata(5 downto 4);
v.mcfg2.rmw := apbi.pwdata(6);
v.mcfg2.brdyen := apbi.pwdata(7);
v.mcfg2.rambanksz := apbi.pwdata(12 downto 9);
if SDRAMEN then
v.mcfg2.srdis := apbi.pwdata(13);
v.mcfg2.sdren := apbi.pwdata(14);
end if;
when others => null;
end case;
end if;
-- select appropriate data during reads
if (r.area(rom) or r.area(ram)) = '1' then dataout := memdata;
else
if BUS8EN and (r.busw = "00") then
dataout := r.data(31 downto 24) & r.data(31 downto 24)
& r.data(31 downto 24) & r.data(31 downto 24);
elsif BUS16EN and (r.busw = "01") then
dataout := r.data(31 downto 16) & r.data(31 downto 16);
else dataout := r.data; end if;
end if;
v.ready := ready;
v.srhsel := r.srhsel and not ready;
if ahbsi.hready = '1' then v.hsel := ahbsi.hsel(hindex); end if;
if ((ahbsi.hready and ahbsi.hsel(hindex)) = '1') then
v.size := ahbsi.hsize(1 downto 0); v.hwrite := ahbsi.hwrite;
v.hburst := ahbsi.hburst; v.htrans := ahbsi.htrans;
if ahbsi.htrans(1) = '1' then v.hsel := '1'; v.srhsel := srhsel; end if;
if SDRAMEN then
v.haddr := ahbsi.haddr;
v.sdhsel := sdhsel;
end if;
end if;
-- sdram synchronisation
if SDRAMEN then
v.sa := sdmo.address; v.sd := memi.sd;
if (r.bstate /= idle) or ((r.ramsn & r.romsn & r.iosn) /= "111111111") then bidle := '0';
else
bidle := '1';
if (sdmo.busy and not sdmo.aload) = '1' then
if not SDSEPBUS then
v.address(sdlsb + 14 downto sdlsb) := sdmo.address;
end if;
v.romsn := (others => '1'); v.ramsn(4 downto 0) := (others => '1');
v.iosn := (others =>'1'); v.ramoen(4 downto 0) := (others => '1');
v.oen := '1';
v.bdrive := not (sdmo.bdrive & sdmo.bdrive & sdmo.bdrive & sdmo.bdrive);
if r.sdhsel = '1' then
v.hresp := sdmo.hresp;
end if;
end if;
end if;
if (sdmo.aload and r.srhsel) = '1' then
v.romsn := romsn; v.ramsn(4 downto 0) := ramsn(4 downto 0); v.iosn := iosn & '1';
if v.read = '1' then v.ramoen(4 downto 0) := ramsn(4 downto 0); v.oen := leadin; end if;
end if;
if sdmo.hsel = '1' then
v.writedata := writedata;
v.sdwritedata(31 downto 0) := writedata;
if BUS64 and sdmo.bsel = '1' then
v.sdwritedata(63 downto 32) := writedata;
end if;
hready := sdmo.hready and noerror and not r.brmw;
if SDSEPBUS then
if BUS64 and sdmo.bsel = '1' then dataout := r.sd(63 downto 32);
else dataout := r.sd(31 downto 0); end if;
end if;
else hready := r.ready and noerror; end if;
else
hready := r.ready and noerror;
end if;
if v.read = '1' then v.mben := "0000"; else v.mben := v.wrn; end if;
v.nbdrive := not v.bdrive;
if oepol = 0 then
bdrive_sel := r.bdrive;
vbdrive(31 downto 24) := (others => v.bdrive(0));
vbdrive(23 downto 16) := (others => v.bdrive(1));
vbdrive(15 downto 8) := (others => v.bdrive(2));
vbdrive(7 downto 0) := (others => v.bdrive(3));
vsbdrive(31 downto 24) := (others => v.bdrive(0));
vsbdrive(23 downto 16) := (others => v.bdrive(1));
vsbdrive(15 downto 8) := (others => v.bdrive(2));
vsbdrive(7 downto 0) := (others => v.bdrive(3));
vsbdrive(63 downto 56) := (others => v.bdrive(0));
vsbdrive(55 downto 48) := (others => v.bdrive(1));
vsbdrive(47 downto 40) := (others => v.bdrive(2));
vsbdrive(39 downto 32) := (others => v.bdrive(3));
else
bdrive_sel := r.nbdrive;
vbdrive(31 downto 24) := (others => v.nbdrive(0));
vbdrive(23 downto 16) := (others => v.nbdrive(1));
vbdrive(15 downto 8) := (others => v.nbdrive(2));
vbdrive(7 downto 0) := (others => v.nbdrive(3));
vsbdrive(31 downto 24) := (others => v.nbdrive(0));
vsbdrive(23 downto 16) := (others => v.nbdrive(1));
vsbdrive(15 downto 8) := (others => v.nbdrive(2));
vsbdrive(7 downto 0) := (others => v.nbdrive(3));
vsbdrive(63 downto 56) := (others => v.nbdrive(0));
vsbdrive(55 downto 48) := (others => v.nbdrive(1));
vsbdrive(47 downto 40) := (others => v.nbdrive(2));
vsbdrive(39 downto 32) := (others => v.nbdrive(3));
end if;
-- reset
if rst = '0' then
v.bstate := idle;
v.read := '1';
v.wrn := "1111";
v.writen := '1';
v.mcfg1.romwrite := '0';
v.mcfg1.ioen := '0';
v.mcfg1.brdyen := '0';
v.mcfg1.bexcen := '0';
v.hsel := '0';
v.srhsel := '0';
v.ready := '1';
v.mcfg1.iows := "0000";
v.mcfg2.ramrws := "00";
v.mcfg2.ramwws := "00";
v.mcfg1.romrws := "1111";
v.mcfg1.romwws := "1111";
v.mcfg1.romwidth := memi.bwidth;
v.mcfg2.srdis := '0';
v.mcfg2.sdren := '0';
if syncrst = 1 then
v.ramsn := (others => '1'); v.romsn := (others => '1');
v.oen := '1'; v.iosn := "11"; v.ramoen := (others => '1');
v.bdrive := (others => '1'); v.nbdrive := (others => '0');
if oepol = 0 then vbdrive := (others => '1'); vsbdrive := (others => '1');
else vbdrive := (others => '0'); vsbdrive := (others => '0'); end if;
end if;
end if;
-- optional feeb-back from write stobe to data bus drivers
if oepol = 0 then
if WENDFB then bdrive := r.bdrive and memi.wrn;
else bdrive := r.bdrive; end if;
else
if WENDFB then bdrive := r.nbdrive or not memi.wrn;
else bdrive := r.nbdrive; end if;
end if;
-- pragma translate_off
for i in dataout'range loop --'
if is_x(dataout(i)) then dataout(i) := '1'; end if;
end loop;
-- pragma translate_on
-- scan support
if (syncrst = 1) and (rst = '0') then
memo.ramsn <= (others => '1');
memo.ramoen <= (others => '1');
memo.romsn <= (others => '1');
memo.iosn <= '1';
memo.oen <= '1';
if (scantest = 1) and (ahbsi.testen = '1') then
memo.bdrive <= (others => ahbsi.testoen);
memo.vbdrive <= (others => ahbsi.testoen);
memo.svbdrive <= (others => ahbsi.testoen);
else
if oepol = 0 then
memo.bdrive <= (others => '1');
memo.vbdrive <= (others => '1');
memo.svbdrive <= (others => '1');
else
memo.bdrive <= (others => '0');
memo.vbdrive <= (others => '0');
memo.svbdrive <= (others => '0');
end if;
end if;
else
memo.ramsn <= "111" & r.ramsn;
memo.ramoen <= "111" & r.ramoen;
memo.romsn <= "111111" & r.romsn;
memo.iosn <= r.iosn(0);
memo.oen <= r.oen;
if (scantest = 1) and (ahbsi.testen = '1') then
memo.bdrive <= (others => ahbsi.testoen);
memo.vbdrive <= (others => ahbsi.testoen);
memo.svbdrive <= (others => ahbsi.testoen);
else
memo.bdrive <= bdrive;
memo.vbdrive <= rbdrive;
memo.svbdrive <= rrsbdrive;
end if;
end if;
-- drive various register inputs and external outputs
ri <= v;
ribdrive <= vbdrive;
risbdrive <= vsbdrive;
ahbso.hcache <= not r.area(io);
memo.address <= r.address;
memo.read <= r.read;
memo.wrn <= r.wrn;
memo.writen <= r.writen;
memo.data <= r.writedata;
memo.mben <= r.mben;
memo.svcdrive <= (others => '0');
memo.vcdrive <= (others => '0');
memo.scb <= (others => '0');
memo.cb <= (others => '0');
memo.romn <= '1';
memo.ramn <= '1';
sdi.idle <= bidle;
sdi.haddr <= haddr;
sdi.rhaddr <= r.haddr;
sdi.nhtrans <= htrans;
sdi.rhtrans <= r.htrans;
sdi.htrans <= ahbsi.htrans;
sdi.hready <= ahbsi.hready;
sdi.hsize <= r.size;
sdi.hwrite <= r.hwrite;
sdi.hsel <= sdhsel;
sdi.enable <= r.mcfg2.sdren;
sdi.srdis <= r.mcfg2.srdis;
sdi.edac <= '0';
sdi.brmw <= '0';
sdi.error <= '0';
ahbso.hrdata <= dataout;
ahbso.hready <= hready;
ahbso.hresp <= r.hresp;
end process;
stdregs : process(clk, arst)
begin
if rising_edge(clk) then
r <= ri; rbdrive <= ribdrive; rsbdrive <= risbdrive;
if rst = '0' then r.ws <= (others => '0'); end if;
end if;
if (syncrst = 0) and (arst = '0') then
r.ramsn <= (others => '1'); r.romsn <= (others => '1');
r.oen <= '1'; r.iosn <= "11"; r.ramoen <= (others => '1');
r.bdrive <= (others => '1'); r.nbdrive <= (others => '0');
if oepol = 0 then rbdrive <= (others => '1'); rsbdrive <= (others => '1');
else rbdrive <= (others => '0'); rsbdrive <= (others => '0'); end if;
end if;
end process;
ahbso.hsplit <= (others => '0');
ahbso.hconfig <= hconfig;
ahbso.hirq <= (others => '0');
ahbso.hindex <= hindex;
apbo.pconfig <= pconfig;
apbo.pirq <= (others => '0');
apbo.pindex <= pindex;
-- optional sdram controller
sd0 : if SDRAMEN generate
sdctrl : sdmctrl generic map (pindex, invclk, fast, wprot, sdbits, pageburst)
port map ( rst => rst, clk => clk, sdi => sdi,
sdo => lsdo, apbi => apbi, wpo => wpo, sdmo => sdmo);
rgen : if invclk = 0 generate
memo.sa <= r.sa; sdo <= lsdo; rrsbdrive <= rsbdrive;
memo.sddata(31 downto 0) <= r.sdwritedata(31 downto 0);
memo.sddata(63 downto 32) <= r.sdwritedata(63 downto 32);
end generate;
ngen : if invclk = 1 generate
nregs : process(clk, arst) begin
if falling_edge(clk) then
memo.sa <= r.sa; sdo <= lsdo; rrsbdrive <= rsbdrive;
memo.sddata(31 downto 0) <= r.sdwritedata(31 downto 0);
memo.sddata(63 downto 32) <= r.sdwritedata(63 downto 32);
if (syncrst = 0) and (arst = '0') then
if oepol = 0 then rrsbdrive <= (others => '1');
else rrsbdrive <= (others => '0'); end if;
end if;
end if;
end process;
end generate;
end generate;
sd1 : if not SDRAMEN generate
sdo <= ("00", "11", '1', '1', '1', "11111111");
sdmo.prdata <= (others => '0');
sdmo.address <= (others => '0'); sdmo.busy <= '0';
sdmo.aload <= '0'; sdmo.bdrive <= '0'; sdmo.hready <= '1';
sdmo.hresp <= "11";
end generate;
end;
| mit | 9763eeeab6899b43a292d5211c2b5a7f | 0.53916 | 3.224717 | false | false | false | false |
cafe-alpha/wascafe | v11/fpga_firmware/wasca/wasca_inst.vhd | 1 | 12,364 | component wasca is
port (
altpll_0_areset_conduit_export : in std_logic := 'X'; -- export
altpll_0_locked_conduit_export : out std_logic; -- export
altpll_0_phasedone_conduit_export : out std_logic; -- export
clk_clk : in std_logic := 'X'; -- clk
clock_116_mhz_clk : out std_logic; -- clk
external_sdram_controller_wire_addr : out std_logic_vector(12 downto 0); -- addr
external_sdram_controller_wire_ba : out std_logic_vector(1 downto 0); -- ba
external_sdram_controller_wire_cas_n : out std_logic; -- cas_n
external_sdram_controller_wire_cke : out std_logic; -- cke
external_sdram_controller_wire_cs_n : out std_logic; -- cs_n
external_sdram_controller_wire_dq : inout std_logic_vector(15 downto 0) := (others => 'X'); -- dq
external_sdram_controller_wire_dqm : out std_logic_vector(1 downto 0); -- dqm
external_sdram_controller_wire_ras_n : out std_logic; -- ras_n
external_sdram_controller_wire_we_n : out std_logic; -- we_n
sega_saturn_abus_slave_0_abus_address : in std_logic_vector(9 downto 0) := (others => 'X'); -- address
sega_saturn_abus_slave_0_abus_chipselect : in std_logic_vector(2 downto 0) := (others => 'X'); -- chipselect
sega_saturn_abus_slave_0_abus_read : in std_logic := 'X'; -- read
sega_saturn_abus_slave_0_abus_write : in std_logic_vector(1 downto 0) := (others => 'X'); -- write
sega_saturn_abus_slave_0_abus_waitrequest : out std_logic; -- waitrequest
sega_saturn_abus_slave_0_abus_interrupt : out std_logic; -- interrupt
sega_saturn_abus_slave_0_abus_addressdata : inout std_logic_vector(15 downto 0) := (others => 'X'); -- addressdata
sega_saturn_abus_slave_0_abus_direction : out std_logic; -- direction
sega_saturn_abus_slave_0_abus_muxing : out std_logic_vector(1 downto 0); -- muxing
sega_saturn_abus_slave_0_abus_disableout : out std_logic; -- disableout
sega_saturn_abus_slave_0_conduit_saturn_reset_saturn_reset : in std_logic := 'X'; -- saturn_reset
spi_sd_card_MISO : in std_logic := 'X'; -- MISO
spi_sd_card_MOSI : out std_logic; -- MOSI
spi_sd_card_SCLK : out std_logic; -- SCLK
spi_sd_card_SS_n : out std_logic; -- SS_n
uart_0_external_connection_rxd : in std_logic := 'X'; -- rxd
uart_0_external_connection_txd : out std_logic; -- txd
spi_stm32_MISO : out std_logic; -- MISO
spi_stm32_MOSI : in std_logic := 'X'; -- MOSI
spi_stm32_SCLK : in std_logic := 'X'; -- SCLK
spi_stm32_SS_n : in std_logic := 'X'; -- SS_n
audio_out_BCLK : in std_logic := 'X'; -- BCLK
audio_out_DACDAT : out std_logic; -- DACDAT
audio_out_DACLRCK : in std_logic := 'X' -- DACLRCK
);
end component wasca;
u0 : component wasca
port map (
altpll_0_areset_conduit_export => CONNECTED_TO_altpll_0_areset_conduit_export, -- altpll_0_areset_conduit.export
altpll_0_locked_conduit_export => CONNECTED_TO_altpll_0_locked_conduit_export, -- altpll_0_locked_conduit.export
altpll_0_phasedone_conduit_export => CONNECTED_TO_altpll_0_phasedone_conduit_export, -- altpll_0_phasedone_conduit.export
clk_clk => CONNECTED_TO_clk_clk, -- clk.clk
clock_116_mhz_clk => CONNECTED_TO_clock_116_mhz_clk, -- clock_116_mhz.clk
external_sdram_controller_wire_addr => CONNECTED_TO_external_sdram_controller_wire_addr, -- external_sdram_controller_wire.addr
external_sdram_controller_wire_ba => CONNECTED_TO_external_sdram_controller_wire_ba, -- .ba
external_sdram_controller_wire_cas_n => CONNECTED_TO_external_sdram_controller_wire_cas_n, -- .cas_n
external_sdram_controller_wire_cke => CONNECTED_TO_external_sdram_controller_wire_cke, -- .cke
external_sdram_controller_wire_cs_n => CONNECTED_TO_external_sdram_controller_wire_cs_n, -- .cs_n
external_sdram_controller_wire_dq => CONNECTED_TO_external_sdram_controller_wire_dq, -- .dq
external_sdram_controller_wire_dqm => CONNECTED_TO_external_sdram_controller_wire_dqm, -- .dqm
external_sdram_controller_wire_ras_n => CONNECTED_TO_external_sdram_controller_wire_ras_n, -- .ras_n
external_sdram_controller_wire_we_n => CONNECTED_TO_external_sdram_controller_wire_we_n, -- .we_n
sega_saturn_abus_slave_0_abus_address => CONNECTED_TO_sega_saturn_abus_slave_0_abus_address, -- sega_saturn_abus_slave_0_abus.address
sega_saturn_abus_slave_0_abus_chipselect => CONNECTED_TO_sega_saturn_abus_slave_0_abus_chipselect, -- .chipselect
sega_saturn_abus_slave_0_abus_read => CONNECTED_TO_sega_saturn_abus_slave_0_abus_read, -- .read
sega_saturn_abus_slave_0_abus_write => CONNECTED_TO_sega_saturn_abus_slave_0_abus_write, -- .write
sega_saturn_abus_slave_0_abus_waitrequest => CONNECTED_TO_sega_saturn_abus_slave_0_abus_waitrequest, -- .waitrequest
sega_saturn_abus_slave_0_abus_interrupt => CONNECTED_TO_sega_saturn_abus_slave_0_abus_interrupt, -- .interrupt
sega_saturn_abus_slave_0_abus_addressdata => CONNECTED_TO_sega_saturn_abus_slave_0_abus_addressdata, -- .addressdata
sega_saturn_abus_slave_0_abus_direction => CONNECTED_TO_sega_saturn_abus_slave_0_abus_direction, -- .direction
sega_saturn_abus_slave_0_abus_muxing => CONNECTED_TO_sega_saturn_abus_slave_0_abus_muxing, -- .muxing
sega_saturn_abus_slave_0_abus_disableout => CONNECTED_TO_sega_saturn_abus_slave_0_abus_disableout, -- .disableout
sega_saturn_abus_slave_0_conduit_saturn_reset_saturn_reset => CONNECTED_TO_sega_saturn_abus_slave_0_conduit_saturn_reset_saturn_reset, -- sega_saturn_abus_slave_0_conduit_saturn_reset.saturn_reset
spi_sd_card_MISO => CONNECTED_TO_spi_sd_card_MISO, -- spi_sd_card.MISO
spi_sd_card_MOSI => CONNECTED_TO_spi_sd_card_MOSI, -- .MOSI
spi_sd_card_SCLK => CONNECTED_TO_spi_sd_card_SCLK, -- .SCLK
spi_sd_card_SS_n => CONNECTED_TO_spi_sd_card_SS_n, -- .SS_n
uart_0_external_connection_rxd => CONNECTED_TO_uart_0_external_connection_rxd, -- uart_0_external_connection.rxd
uart_0_external_connection_txd => CONNECTED_TO_uart_0_external_connection_txd, -- .txd
spi_stm32_MISO => CONNECTED_TO_spi_stm32_MISO, -- spi_stm32.MISO
spi_stm32_MOSI => CONNECTED_TO_spi_stm32_MOSI, -- .MOSI
spi_stm32_SCLK => CONNECTED_TO_spi_stm32_SCLK, -- .SCLK
spi_stm32_SS_n => CONNECTED_TO_spi_stm32_SS_n, -- .SS_n
audio_out_BCLK => CONNECTED_TO_audio_out_BCLK, -- audio_out.BCLK
audio_out_DACDAT => CONNECTED_TO_audio_out_DACDAT, -- .DACDAT
audio_out_DACLRCK => CONNECTED_TO_audio_out_DACLRCK -- .DACLRCK
);
| gpl-2.0 | 8b9afdc1aeb08ba8c468a077c8ec2675 | 0.361776 | 5.184067 | false | false | false | false |
impedimentToProgress/UCI-BlueChip | AttackFiles/Attacks/privEsc/lib/gaisler/ambatest/ahb_tbfunct.vhd | 2 | 6,721 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- pragma translate_off
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
library gaisler;
use gaisler.ambatest.all;
package ahb_tb is
procedure AHB_read_single(ctrl : inout ctrl_type; signal tbi : out tb_in_type; signal tbo : in tb_out_type; dbglevel : in integer);
procedure AHB_read_burst(ctrl : inout ctrl_type; signal tbi : out tb_in_type; signal tbo : in tb_out_type; dbglevel : in integer);
procedure AHB_write_single(ctrl : inout ctrl_type; signal tbi : out tb_in_type; signal tbo : in tb_out_type; dbglevel : in integer);
procedure AHB_write_burst(ctrl : inout ctrl_type; signal tbi : out tb_in_type; signal tbo : in tb_out_type; dbglevel : in integer);
end ahb_tb;
package body ahb_tb is
constant printlevel : integer := 2;
function string_inv(instring : string(18 downto 1)) return string is
variable vstr : string(1 to 18);
begin
vstr(1 to 18) := instring(18 downto 1);
return(vstr);
end string_inv;
procedure AHB_read_single(
ctrl : inout ctrl_type;
signal tbi : out tb_in_type;
signal tbo : in tb_out_type;
dbglevel : in integer) is
begin
if tbo.ready = '1' then wait until tbo.ready = '0'; end if;
tbi.address <= ctrl.address;
tbi.command <= RD_SINGLE;
tbi.no_words <= 1;
tbi.userfile <= ctrl.userfile;
tbi.rfile <= ctrl.rfile;
if dbglevel >= printlevel then
if ctrl.userfile then
printf("AHBMST TB: AHB Read from file %s",string_inv(ctrl.rfile));
else
printf("AHBMST TB: AHB Read from address %x",ctrl.address);
end if;
end if;
tbi.usewfile <= ctrl.usewfile;
tbi.wfile <= ctrl.wfile;
tbi.start <= '1';
wait until tbo.ready = '1';
ctrl.data := tbo.data;
ctrl.status := tbo.status;
if ctrl.status = ERR then
printf("AHBMST TB: #ERROR# Read access failed at %x",ctrl.address);
elsif ctrl.status = TIMEOUT then
printf("AHBMST TB: #ERROR# Timeout received for read access at %x",ctrl.address);
elsif ctrl.status = OK then
if dbglevel >= printlevel then
printf("AHBMST TB: Returned data: %x",ctrl.data);
end if;
end if;
tbi.start <= '0';
end procedure;
procedure AHB_read_burst(
ctrl : inout ctrl_type;
signal tbi : out tb_in_type;
signal tbo : in tb_out_type;
dbglevel : in integer) is
variable i : integer;
begin
if tbo.ready = '1' then wait until tbo.ready = '0'; end if;
tbi.address <= ctrl.address;
tbi.command <= RD_INCR;
tbi.no_words <= ctrl.no_words;
tbi.userfile <= ctrl.userfile;
tbi.rfile <= ctrl.rfile;
if dbglevel >= printlevel then
if ctrl.userfile then
printf("AHBMST TB: AHB Read burst from file %s",string_inv(ctrl.rfile));
else
printf("AHBMST TB: AHB Read burst from address %x",ctrl.address);
end if;
end if;
tbi.usewfile <= ctrl.usewfile;
tbi.wfile <= ctrl.wfile;
tbi.start <= '1';
wait until tbo.ready = '1';
ctrl.data := tbo.data;
ctrl.status := tbo.status;
if ctrl.status = ERR then
printf("AHBMST TB: #ERROR# Read access failed at %x",ctrl.address);
elsif ctrl.status = TIMEOUT then
printf("AHBMST TB: #ERROR# Timeout received for read access at %x",ctrl.address);
elsif ctrl.status = OK then
if dbglevel >= printlevel then
printf("AHBMST TB: Returned data: %x",ctrl.data);
end if;
end if;
ctrl.status := tbo.status;
tbi.start <= '0';
end procedure;
procedure AHB_write_single(
ctrl : inout ctrl_type;
signal tbi : out tb_in_type;
signal tbo : in tb_out_type;
dbglevel : in integer) is
begin
if tbo.ready = '1' then wait until tbo.ready = '0'; end if;
tbi.address <= ctrl.address;
tbi.data <= ctrl.data;
tbi.command <= WR_SINGLE;
tbi.no_words <= 1;
tbi.userfile <= ctrl.userfile;
tbi.rfile <= ctrl.rfile;
if dbglevel >= printlevel then
if ctrl.userfile then
printf("AHBMST TB: AHB Write from file %s",string_inv(ctrl.rfile));
else
printf("AHBMST TB: AHB Write to address %x",ctrl.address);
end if;
end if;
tbi.usewfile <= false; -- No log file for write accesses
tbi.wfile <= ctrl.wfile;
tbi.start <= '1';
wait until tbo.ready = '1';
ctrl.status := tbo.status;
if ctrl.status = ERR then
printf("AHBMST TB: #ERROR# Write access failed at %x",ctrl.address);
elsif ctrl.status = TIMEOUT then
printf("AHBMST TB: #ERROR# Timeout received for write access at %x",ctrl.address);
elsif ctrl.status = OK then
if dbglevel >= printlevel then
printf("AHBMST TB: Write success!");
end if;
end if;
tbi.start <= '0';
end procedure;
procedure AHB_write_burst(
ctrl : inout ctrl_type;
signal tbi : out tb_in_type;
signal tbo : in tb_out_type;
dbglevel : in integer) is
begin
if tbo.ready = '1' then wait until tbo.ready = '0'; end if;
tbi.address <= ctrl.address;
tbi.data <= ctrl.data;
tbi.command <= WR_INCR;
tbi.no_words <= ctrl.no_words;
tbi.userfile <= ctrl.userfile;
tbi.rfile <= ctrl.rfile;
if dbglevel >= printlevel then
if ctrl.userfile then
printf("AHBMST TB: AHB Write from file %s",string_inv(ctrl.rfile));
else
printf("AHBMST TB: AHB Write burst to address %x",ctrl.address);
end if;
end if;
tbi.usewfile <= false; -- No log file for write accesses
tbi.wfile <= ctrl.wfile;
tbi.start <= '1';
wait until tbo.ready = '1';
ctrl.status := tbo.status;
if ctrl.status = ERR then
printf("AHBMST TB: #ERROR# Write access failed at %x",ctrl.address);
elsif ctrl.status = TIMEOUT then
printf("AHBMST TB: #ERROR# Timeout received for write access at %x",ctrl.address);
elsif ctrl.status = OK then
if dbglevel >= printlevel then
printf("AHBMST TB: Write success!");
end if;
end if;
tbi.start <= '0';
end procedure;
end package body;
-- pragma translate_on
| mit | 540968defb72095609888508950bc502 | 0.654813 | 3.439611 | false | false | false | false |
lxp32/lxp32-cpu | rtl/lxp32_alu.vhd | 1 | 5,367 | ---------------------------------------------------------------------
-- Arithmetic logic unit
--
-- Part of the LXP32 CPU
--
-- Copyright (c) 2016 by Alex I. Kuznetsov
--
-- Performs arithmetic and logic operations.
---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity lxp32_alu is
generic(
DIVIDER_EN: boolean;
MUL_ARCH: string
);
port(
clk_i: in std_logic;
rst_i: in std_logic;
valid_i: in std_logic;
cmd_signed_i: in std_logic;
cmd_addsub_i: in std_logic;
cmd_mul_i: in std_logic;
cmd_div_i: in std_logic;
cmd_div_mod_i: in std_logic;
cmd_cmp_i: in std_logic;
cmd_negate_op2_i: in std_logic;
cmd_and_i: in std_logic;
cmd_xor_i: in std_logic;
cmd_shift_i: in std_logic;
cmd_shift_right_i: in std_logic;
op1_i: in std_logic_vector(31 downto 0);
op2_i: in std_logic_vector(31 downto 0);
result_o: out std_logic_vector(31 downto 0);
cmp_eq_o: out std_logic;
cmp_ug_o: out std_logic;
cmp_sg_o: out std_logic;
we_o: out std_logic;
busy_o: out std_logic
);
end entity;
architecture rtl of lxp32_alu is
signal addend1: unsigned(31 downto 0);
signal addend2: unsigned(31 downto 0);
signal adder_result: unsigned(32 downto 0);
signal adder_we: std_logic;
signal cmp_eq: std_logic;
signal cmp_carry: std_logic;
signal cmp_s1: std_logic;
signal cmp_s2: std_logic;
signal logic_result: std_logic_vector(31 downto 0);
signal logic_we: std_logic;
signal mul_result: std_logic_vector(31 downto 0);
signal mul_ce: std_logic;
signal mul_we: std_logic;
signal div_result: std_logic_vector(31 downto 0);
signal div_ce: std_logic;
signal div_we: std_logic;
signal shift_result: std_logic_vector(31 downto 0);
signal shift_ce: std_logic;
signal shift_we: std_logic;
signal result_mux: std_logic_vector(31 downto 0);
signal result_we: std_logic;
signal busy: std_logic:='0';
begin
assert MUL_ARCH="dsp" or MUL_ARCH="seq" or MUL_ARCH="opt"
report "Invalid MUL_ARCH generic value: dsp, opt or seq expected"
severity failure;
-- Add/subtract
addend1<=unsigned(op1_i);
addend2_gen: for i in addend2'range generate
addend2(i)<=op2_i(i) xor cmd_negate_op2_i;
end generate;
adder_result<=("0"&addend1)+("0"&addend2)+(to_unsigned(0,adder_result'length-1)&cmd_negate_op2_i);
adder_we<=cmd_addsub_i and valid_i;
-- Comparator (needs cmd_negate_op2_i to work correctly)
process (clk_i) is
begin
if rising_edge(clk_i) then
if valid_i='1' and cmd_cmp_i='1' then
if op1_i=op2_i then
cmp_eq<='1';
else
cmp_eq<='0';
end if;
cmp_carry<=adder_result(adder_result'high);
cmp_s1<=op1_i(op1_i'high);
cmp_s2<=op2_i(op2_i'high);
end if;
end if;
end process;
cmp_eq_o<=cmp_eq;
cmp_ug_o<=cmp_carry and not cmp_eq;
cmp_sg_o<=((cmp_s1 and cmp_s2 and cmp_carry) or
(not cmp_s1 and not cmp_s2 and cmp_carry) or
(not cmp_s1 and cmp_s2)) and not cmp_eq;
-- Bitwise operations (and, or, xor)
-- Note: (a or b) = (a and b) or (a xor b)
logic_result_gen: for i in logic_result'range generate
logic_result(i)<=((op1_i(i) and op2_i(i)) and cmd_and_i) or
((op1_i(i) xor op2_i(i)) and cmd_xor_i);
end generate;
logic_we<=(cmd_and_i or cmd_xor_i) and valid_i;
-- Multiplier
mul_ce<=cmd_mul_i and valid_i;
gen_mul_dsp: if MUL_ARCH="dsp" generate
mul_inst: entity work.lxp32_mul_dsp(rtl)
port map(
clk_i=>clk_i,
rst_i=>rst_i,
ce_i=>mul_ce,
op1_i=>op1_i,
op2_i=>op2_i,
ce_o=>mul_we,
result_o=>mul_result
);
end generate;
gen_mul_opt: if MUL_ARCH="opt" generate
mul_inst: entity work.lxp32_mul_opt(rtl)
port map(
clk_i=>clk_i,
rst_i=>rst_i,
ce_i=>mul_ce,
op1_i=>op1_i,
op2_i=>op2_i,
ce_o=>mul_we,
result_o=>mul_result
);
end generate;
gen_mul_seq: if MUL_ARCH="seq" generate
mul_inst: entity work.lxp32_mul_seq(rtl)
port map(
clk_i=>clk_i,
rst_i=>rst_i,
ce_i=>mul_ce,
op1_i=>op1_i,
op2_i=>op2_i,
ce_o=>mul_we,
result_o=>mul_result
);
end generate;
-- Divider
div_ce<=cmd_div_i and valid_i;
gen_divider: if DIVIDER_EN generate
divider_inst: entity work.lxp32_divider(rtl)
port map(
clk_i=>clk_i,
rst_i=>rst_i,
ce_i=>div_ce,
op1_i=>op1_i,
op2_i=>op2_i,
signed_i=>cmd_signed_i,
rem_i=>cmd_div_mod_i,
ce_o=>div_we,
result_o=>div_result
);
end generate;
gen_no_divider: if not DIVIDER_EN generate
div_we<=div_ce;
div_result<=(others=>'0');
end generate;
-- Shifter
shift_ce<=cmd_shift_i and valid_i;
shifter_inst: entity work.lxp32_shifter(rtl)
port map(
clk_i=>clk_i,
rst_i=>rst_i,
ce_i=>shift_ce,
d_i=>op1_i,
s_i=>op2_i(4 downto 0),
right_i=>cmd_shift_right_i,
sig_i=>cmd_signed_i,
ce_o=>shift_we,
d_o=>shift_result
);
-- Result multiplexer
result_mux_gen: for i in result_mux'range generate
result_mux(i)<=(adder_result(i) and adder_we) or
(logic_result(i) and logic_we) or
(mul_result(i) and mul_we) or
(div_result(i) and div_we) or
(shift_result(i) and shift_we);
end generate;
result_o<=result_mux;
result_we<=adder_we or logic_we or mul_we or div_we or shift_we;
we_o<=result_we;
-- Pipeline control
process (clk_i) is
begin
if rising_edge(clk_i) then
if rst_i='1' or result_we='1' then
busy<='0';
elsif shift_ce='1' or mul_ce='1' or div_ce='1' then
busy<='1';
end if;
end if;
end process;
busy_o<=busy;
end architecture;
| mit | 7448ff2da98c779aee63ea9045f2319d | 0.640395 | 2.420839 | false | false | false | false |
impedimentToProgress/UCI-BlueChip | AttackFiles/Attacks/privEsc/lib/techmap/unisim/memory_unisim.vhd | 2 | 35,058 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: various
-- File: mem_xilinx_gen.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: Memory generators for Xilinx rams
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
--pragma translate_off
library unisim;
use unisim.RAMB4_S1;
use unisim.RAMB4_S2;
use unisim.RAMB4_S4;
use unisim.RAMB4_S8;
use unisim.RAMB4_S16;
use unisim.RAMB4_S16_S16;
--pragma translate_on
library techmap;
use techmap.gencomp.all;
entity virtex_syncram is
generic ( abits : integer := 6; dbits : integer := 8);
port (
clk : in std_ulogic;
address : in std_logic_vector (abits -1 downto 0);
datain : in std_logic_vector (dbits -1 downto 0);
dataout : out std_logic_vector (dbits -1 downto 0);
enable : in std_ulogic;
write : in std_ulogic
);
end;
architecture behav of virtex_syncram is
component generic_syncram
generic ( abits : integer := 10; dbits : integer := 8 );
port (
clk : in std_ulogic;
address : in std_logic_vector((abits -1) downto 0);
datain : in std_logic_vector((dbits -1) downto 0);
dataout : out std_logic_vector((dbits -1) downto 0);
write : in std_ulogic);
end component;
component ramb4_s16 port (
do : out std_logic_vector (15 downto 0);
addr : in std_logic_vector (7 downto 0);
clk : in std_ulogic;
di : in std_logic_vector (15 downto 0);
en, rst, we : in std_ulogic);
end component;
component RAMB4_S8
port (do : out std_logic_vector (7 downto 0);
addr : in std_logic_vector (8 downto 0);
clk : in std_ulogic;
di : in std_logic_vector (7 downto 0);
en, rst, we : in std_ulogic);
end component;
component RAMB4_S4
port (do : out std_logic_vector (3 downto 0);
addr : in std_logic_vector (9 downto 0);
clk : in std_ulogic;
di : in std_logic_vector (3 downto 0);
en, rst, we : in std_ulogic);
end component;
component RAMB4_S2
port (do : out std_logic_vector (1 downto 0);
addr : in std_logic_vector (10 downto 0);
clk : in std_ulogic;
di : in std_logic_vector (1 downto 0);
en, rst, we : in std_ulogic);
end component;
component RAMB4_S1
port (do : out std_logic_vector (0 downto 0);
addr : in std_logic_vector (11 downto 0);
clk : in std_ulogic;
di : in std_logic_vector (0 downto 0);
en, rst, we : in std_ulogic);
end component;
component RAMB4_S16_S16
port (
doa : out std_logic_vector (15 downto 0);
dob : out std_logic_vector (15 downto 0);
addra : in std_logic_vector (7 downto 0);
addrb : in std_logic_vector (7 downto 0);
clka : in std_ulogic;
clkb : in std_ulogic;
dia : in std_logic_vector (15 downto 0);
dib : in std_logic_vector (15 downto 0);
ena : in std_ulogic;
enb : in std_ulogic;
rsta : in std_ulogic;
rstb : in std_ulogic;
wea : in std_ulogic;
web : in std_ulogic
);
end component;
signal gnd : std_ulogic;
signal do, di : std_logic_vector(dbits+32 downto 0);
signal xa, ya : std_logic_vector(19 downto 0);
begin
gnd <= '0';
dataout <= do(dbits-1 downto 0);
di(dbits-1 downto 0) <= datain; di(dbits+32 downto dbits) <= (others => '0');
xa(abits-1 downto 0) <= address; xa(19 downto abits) <= (others => '0');
ya(abits-1 downto 0) <= address; ya(19 downto abits) <= (others => '1');
a0 : if (abits <= 5) generate
r0 : generic_syncram generic map (abits, dbits)
port map (clk, address, datain, do(dbits-1 downto 0), write);
do(dbits+32 downto dbits) <= (others => '0');
end generate;
a7 : if (abits > 5) and (abits <= 7) and (dbits <= 32) generate
r0 : RAMB4_S16_S16 port map ( do(31 downto 16), do(15 downto 0),
xa(7 downto 0), ya(7 downto 0), clk, clk, di(31 downto 16),
di(15 downto 0), enable, enable, gnd, gnd, write, write);
do(dbits+32 downto 32) <= (others => '0');
end generate;
a8 : if ((abits > 5) and (abits <= 7) and (dbits > 32)) or (abits = 8) generate
x : for i in 0 to ((dbits-1)/16) generate
r : RAMB4_S16 port map ( do (((i+1)*16)-1 downto i*16), xa(7 downto 0),
clk, di (((i+1)*16)-1 downto i*16), enable, gnd, write );
end generate;
do(dbits+32 downto 16*(((dbits-1)/16)+1)) <= (others => '0');
end generate;
a9 : if abits = 9 generate
x : for i in 0 to ((dbits-1)/8) generate
r : RAMB4_S8 port map ( do (((i+1)*8)-1 downto i*8), xa(8 downto 0),
clk, di (((i+1)*8)-1 downto i*8), enable, gnd, write );
end generate;
do(dbits+32 downto 8*(((dbits-1)/8)+1)) <= (others => '0');
end generate;
a10 : if abits = 10 generate
x : for i in 0 to ((dbits-1)/4) generate
r : RAMB4_S4 port map ( do (((i+1)*4)-1 downto i*4), xa(9 downto 0),
clk, di (((i+1)*4)-1 downto i*4), enable, gnd, write );
end generate;
do(dbits+32 downto 4*(((dbits-1)/4)+1)) <= (others => '0');
end generate;
a11 : if abits = 11 generate
x : for i in 0 to ((dbits-1)/2) generate
r : RAMB4_S2 port map ( do (((i+1)*2)-1 downto i*2), xa(10 downto 0),
clk, di (((i+1)*2)-1 downto i*2), enable, gnd, write );
end generate;
do(dbits+32 downto 2*(((dbits-1)/2)+1)) <= (others => '0');
end generate;
a12 : if abits = 12 generate
x : for i in 0 to (dbits-1) generate
r : RAMB4_S1 port map ( do (i downto i), xa(11 downto 0),
clk, di(i downto i), enable, gnd, write );
end generate;
do(dbits+32 downto dbits) <= (others => '0');
end generate;
a13 : if abits > 12 generate
x: generic_syncram generic map (abits, dbits)
port map (clk, address, datain, do(dbits-1 downto 0), write);
do(dbits+32 downto dbits) <= (others => '0');
end generate;
-- pragma translate_off
-- a_to_high : if abits > 12 generate
-- x : process
-- begin
-- assert false
-- report "Address depth larger than 12 not supported for virtex_syncram"
-- severity failure;
-- wait;
-- end process;
-- end generate;
-- pragma translate_on
end;
library ieee;
use ieee.std_logic_1164.all;
--pragma translate_off
library unisim;
use unisim.RAMB4_S1_S1;
use unisim.RAMB4_S2_S2;
use unisim.RAMB4_S4_S4;
use unisim.RAMB4_S8_S8;
use unisim.RAMB4_S16_S16;
--pragma translate_on
entity virtex_syncram_dp is
generic (
abits : integer := 6; dbits : integer := 8
);
port (
clk1 : in std_ulogic;
address1 : in std_logic_vector((abits -1) downto 0);
datain1 : in std_logic_vector((dbits -1) downto 0);
dataout1 : out std_logic_vector((dbits -1) downto 0);
enable1 : in std_ulogic;
write1 : in std_ulogic;
clk2 : in std_ulogic;
address2 : in std_logic_vector((abits -1) downto 0);
datain2 : in std_logic_vector((dbits -1) downto 0);
dataout2 : out std_logic_vector((dbits -1) downto 0);
enable2 : in std_ulogic;
write2 : in std_ulogic);
end;
architecture behav of virtex_syncram_dp is
component RAMB4_S1_S1
port (
doa : out std_logic_vector (0 downto 0);
dob : out std_logic_vector (0 downto 0);
addra : in std_logic_vector (11 downto 0);
addrb : in std_logic_vector (11 downto 0);
clka : in std_ulogic;
clkb : in std_ulogic;
dia : in std_logic_vector (0 downto 0);
dib : in std_logic_vector (0 downto 0);
ena : in std_ulogic;
enb : in std_ulogic;
rsta : in std_ulogic;
rstb : in std_ulogic;
wea : in std_ulogic;
web : in std_ulogic
);
end component;
component RAMB4_S2_S2
port (
doa : out std_logic_vector (1 downto 0);
dob : out std_logic_vector (1 downto 0);
addra : in std_logic_vector (10 downto 0);
addrb : in std_logic_vector (10 downto 0);
clka : in std_ulogic;
clkb : in std_ulogic;
dia : in std_logic_vector (1 downto 0);
dib : in std_logic_vector (1 downto 0);
ena : in std_ulogic;
enb : in std_ulogic;
rsta : in std_ulogic;
rstb : in std_ulogic;
wea : in std_ulogic;
web : in std_ulogic
);
end component;
component RAMB4_S4_S4
port (
doa : out std_logic_vector (3 downto 0);
dob : out std_logic_vector (3 downto 0);
addra : in std_logic_vector (9 downto 0);
addrb : in std_logic_vector (9 downto 0);
clka : in std_ulogic;
clkb : in std_ulogic;
dia : in std_logic_vector (3 downto 0);
dib : in std_logic_vector (3 downto 0);
ena : in std_ulogic;
enb : in std_ulogic;
rsta : in std_ulogic;
rstb : in std_ulogic;
wea : in std_ulogic;
web : in std_ulogic
);
end component;
component RAMB4_S8_S8
port (
doa : out std_logic_vector (7 downto 0);
dob : out std_logic_vector (7 downto 0);
addra : in std_logic_vector (8 downto 0);
addrb : in std_logic_vector (8 downto 0);
clka : in std_ulogic;
clkb : in std_ulogic;
dia : in std_logic_vector (7 downto 0);
dib : in std_logic_vector (7 downto 0);
ena : in std_ulogic;
enb : in std_ulogic;
rsta : in std_ulogic;
rstb : in std_ulogic;
wea : in std_ulogic;
web : in std_ulogic
);
end component;
component RAMB4_S16_S16
port (
doa : out std_logic_vector (15 downto 0);
dob : out std_logic_vector (15 downto 0);
addra : in std_logic_vector (7 downto 0);
addrb : in std_logic_vector (7 downto 0);
clka : in std_ulogic;
clkb : in std_ulogic;
dia : in std_logic_vector (15 downto 0);
dib : in std_logic_vector (15 downto 0);
ena : in std_ulogic;
enb : in std_ulogic;
rsta : in std_ulogic;
rstb : in std_ulogic;
wea : in std_ulogic;
web : in std_ulogic
);
end component;
signal gnd, vcc : std_ulogic;
signal do1, do2, di1, di2 : std_logic_vector(dbits+16 downto 0);
signal addr1, addr2 : std_logic_vector(19 downto 0);
begin
gnd <= '0'; vcc <= '1';
dataout1 <= do1(dbits-1 downto 0); dataout2 <= do2(dbits-1 downto 0);
di1(dbits-1 downto 0) <= datain1; di1(dbits+16 downto dbits) <= (others => '0');
di2(dbits-1 downto 0) <= datain2; di2(dbits+16 downto dbits) <= (others => '0');
addr1(abits-1 downto 0) <= address1; addr1(19 downto abits) <= (others => '0');
addr2(abits-1 downto 0) <= address2; addr2(19 downto abits) <= (others => '0');
a8 : if abits <= 8 generate
x : for i in 0 to ((dbits-1)/16) generate
r0 : RAMB4_S16_S16 port map (
do1(((i+1)*16)-1 downto i*16), do2(((i+1)*16)-1 downto i*16),
addr1(7 downto 0), addr2(7 downto 0), clk1, clk2,
di1(((i+1)*16)-1 downto i*16), di2(((i+1)*16)-1 downto i*16),
enable1, enable2, gnd, gnd, write1, write2);
end generate;
end generate;
a9 : if abits = 9 generate
x : for i in 0 to ((dbits-1)/8) generate
r0 : RAMB4_S8_S8 port map (
do1(((i+1)*8)-1 downto i*8), do2(((i+1)*8)-1 downto i*8),
addr1(8 downto 0), addr2(8 downto 0), clk1, clk2,
di1(((i+1)*8)-1 downto i*8), di2(((i+1)*8)-1 downto i*8),
enable1, enable2, gnd, gnd, write1, write2);
end generate;
end generate;
a10: if abits = 10 generate
x : for i in 0 to ((dbits-1)/4) generate
r0 : RAMB4_S4_S4 port map (
do1(((i+1)*4)-1 downto i*4), do2(((i+1)*4)-1 downto i*4),
addr1(9 downto 0), addr2(9 downto 0), clk1, clk2,
di1(((i+1)*4)-1 downto i*4), di2(((i+1)*4)-1 downto i*4),
enable1, enable2, gnd, gnd, write1, write2);
end generate;
end generate;
a11: if abits = 11 generate
x : for i in 0 to ((dbits-1)/2) generate
r0 : RAMB4_S2_S2 port map (
do1(((i+1)*2)-1 downto i*2), do2(((i+1)*2)-1 downto i*2),
addr1(10 downto 0), addr2(10 downto 0), clk1, clk2,
di1(((i+1)*2)-1 downto i*2), di2(((i+1)*2)-1 downto i*2),
enable1, enable2, gnd, gnd, write1, write2);
end generate;
end generate;
a12: if abits = 12 generate
x : for i in 0 to ((dbits-1)/1) generate
r0 : RAMB4_S1_S1 port map (
do1(((i+1)*1)-1 downto i*1), do2(((i+1)*1)-1 downto i*1),
addr1(11 downto 0), addr2(11 downto 0), clk1, clk2,
di1(((i+1)*1)-1 downto i*1), di2(((i+1)*1)-1 downto i*1),
enable1, enable2, gnd, gnd, write1, write2);
end generate;
end generate;
-- pragma translate_off
a_to_high : if abits > 12 generate
x : process
begin
assert false
report "Address depth larger than 12 not supported for virtex_syncram_dp"
severity failure;
wait;
end process;
end generate;
-- pragma translate_on
end;
-- parametrisable sync ram generator using virtex2 select rams
library ieee;
use ieee.std_logic_1164.all;
--pragma translate_off
library unisim;
use unisim.RAMB16_S36_S36;
use unisim.RAMB16_S36;
use unisim.RAMB16_S18;
use unisim.RAMB16_S9;
use unisim.RAMB16_S4;
use unisim.RAMB16_S2;
use unisim.RAMB16_S1;
--pragma translate_on
entity virtex2_syncram is
generic ( abits : integer := 9; dbits : integer := 32);
port (
clk : in std_ulogic;
address : in std_logic_vector (abits -1 downto 0);
datain : in std_logic_vector (dbits -1 downto 0);
dataout : out std_logic_vector (dbits -1 downto 0);
enable : in std_ulogic;
write : in std_ulogic
);
end;
architecture behav of virtex2_syncram is
component RAMB16_S36_S36
port (
DOA : out std_logic_vector (31 downto 0);
DOB : out std_logic_vector (31 downto 0);
DOPA : out std_logic_vector (3 downto 0);
DOPB : out std_logic_vector (3 downto 0);
ADDRA : in std_logic_vector (8 downto 0);
ADDRB : in std_logic_vector (8 downto 0);
CLKA : in std_ulogic;
CLKB : in std_ulogic;
DIA : in std_logic_vector (31 downto 0);
DIB : in std_logic_vector (31 downto 0);
DIPA : in std_logic_vector (3 downto 0);
DIPB : in std_logic_vector (3 downto 0);
ENA : in std_ulogic;
ENB : in std_ulogic;
SSRA : in std_ulogic;
SSRB : in std_ulogic;
WEA : in std_ulogic;
WEB : in std_ulogic);
end component;
component RAMB16_S1
port (
DO : out std_logic_vector (0 downto 0);
ADDR : in std_logic_vector (13 downto 0);
CLK : in std_ulogic;
DI : in std_logic_vector (0 downto 0);
EN : in std_ulogic;
SSR : in std_ulogic;
WE : in std_ulogic
);
end component;
component RAMB16_S2
port (
DO : out std_logic_vector (1 downto 0);
ADDR : in std_logic_vector (12 downto 0);
CLK : in std_ulogic;
DI : in std_logic_vector (1 downto 0);
EN : in std_ulogic;
SSR : in std_ulogic;
WE : in std_ulogic
);
end component;
component RAMB16_S4
port (
DO : out std_logic_vector (3 downto 0);
ADDR : in std_logic_vector (11 downto 0);
CLK : in std_ulogic;
DI : in std_logic_vector (3 downto 0);
EN : in std_ulogic;
SSR : in std_ulogic;
WE : in std_ulogic
);
end component;
component RAMB16_S9
port (
DO : out std_logic_vector (7 downto 0);
DOP : out std_logic_vector (0 downto 0);
ADDR : in std_logic_vector (10 downto 0);
CLK : in std_ulogic;
DI : in std_logic_vector (7 downto 0);
DIP : in std_logic_vector (0 downto 0);
EN : in std_ulogic;
SSR : in std_ulogic;
WE : in std_ulogic
);
end component;
component RAMB16_S18
port (
DO : out std_logic_vector (15 downto 0);
DOP : out std_logic_vector (1 downto 0);
ADDR : in std_logic_vector (9 downto 0);
CLK : in std_ulogic;
DI : in std_logic_vector (15 downto 0);
DIP : in std_logic_vector (1 downto 0);
EN : in std_ulogic;
SSR : in std_ulogic;
WE : in std_ulogic
);
end component;
component RAMB16_S36
port (
DO : out std_logic_vector (31 downto 0);
DOP : out std_logic_vector (3 downto 0);
ADDR : in std_logic_vector (8 downto 0);
CLK : in std_ulogic;
DI : in std_logic_vector (31 downto 0);
DIP : in std_logic_vector (3 downto 0);
EN : in std_ulogic;
SSR : in std_ulogic;
WE : in std_ulogic
);
end component;
component generic_syncram
generic ( abits : integer := 10; dbits : integer := 8 );
port (
clk : in std_ulogic;
address : in std_logic_vector((abits -1) downto 0);
datain : in std_logic_vector((dbits -1) downto 0);
dataout : out std_logic_vector((dbits -1) downto 0);
write : in std_ulogic);
end component;
signal gnd : std_ulogic;
signal do, di : std_logic_vector(dbits+72 downto 0);
signal xa, ya : std_logic_vector(19 downto 0);
begin
gnd <= '0'; dataout <= do(dbits-1 downto 0); di(dbits-1 downto 0) <= datain;
di(dbits+72 downto dbits) <= (others => '0'); xa(abits-1 downto 0) <= address;
xa(19 downto abits) <= (others => '0'); ya(abits-1 downto 0) <= address;
ya(19 downto abits) <= (others => '1');
a0 : if (abits <= 5) generate
r0 : generic_syncram generic map (abits, dbits)
port map (clk, address, datain, do(dbits-1 downto 0), write);
do(dbits+72 downto dbits) <= (others => '0');
end generate;
a8 : if (abits > 5) and (abits <= 8) generate
x : for i in 0 to ((dbits-1)/72) generate
r0 : RAMB16_S36_S36 port map (
do(i*72+36+31 downto i*72+36), do(i*72+31 downto i*72),
do(i*72+36+32+3 downto i*72+36+32), do(i*72+32+3 downto i*72+32),
xa(8 downto 0), ya(8 downto 0), clk, clk,
di(i*72+36+31 downto i*72+36), di(i*72+31 downto i*72),
di(i*72+36+32+3 downto i*72+36+32), di(i*72+32+3 downto i*72+32),
enable, enable, gnd, gnd, write, write);
end generate;
do(dbits+72 downto 72*(((dbits-1)/72)+1)) <= (others => '0');
end generate;
a9 : if (abits = 9) generate
x : for i in 0 to ((dbits-1)/36) generate
r : RAMB16_S36 port map ( do(((i+1)*36)-5 downto i*36),
do(((i+1)*36)-1 downto i*36+32), xa(8 downto 0), clk,
di(((i+1)*36)-5 downto i*36), di(((i+1)*36)-1 downto i*36+32),
enable, gnd, write);
end generate;
do(dbits+72 downto 36*(((dbits-1)/36)+1)) <= (others => '0');
end generate;
a10 : if (abits = 10) generate
x : for i in 0 to ((dbits-1)/18) generate
r : RAMB16_S18 port map ( do(((i+1)*18)-3 downto i*18),
do(((i+1)*18)-1 downto i*18+16), xa(9 downto 0), clk,
di(((i+1)*18)-3 downto i*18), di(((i+1)*18)-1 downto i*18+16),
enable, gnd, write);
end generate;
do(dbits+72 downto 18*(((dbits-1)/18)+1)) <= (others => '0');
end generate;
a11 : if abits = 11 generate
x : for i in 0 to ((dbits-1)/9) generate
r : RAMB16_S9 port map ( do(((i+1)*9)-2 downto i*9),
do(((i+1)*9)-1 downto i*9+8), xa(10 downto 0), clk,
di(((i+1)*9)-2 downto i*9), di(((i+1)*9)-1 downto i*9+8),
enable, gnd, write);
end generate;
do(dbits+72 downto 9*(((dbits-1)/9)+1)) <= (others => '0');
end generate;
a12 : if abits = 12 generate
x : for i in 0 to ((dbits-1)/4) generate
r : RAMB16_S4 port map ( do(((i+1)*4)-1 downto i*4), xa(11 downto 0),
clk, di(((i+1)*4)-1 downto i*4), enable, gnd, write);
end generate;
do(dbits+72 downto 4*(((dbits-1)/4)+1)) <= (others => '0');
end generate;
a13 : if abits = 13 generate
x : for i in 0 to ((dbits-1)/2) generate
r : RAMB16_S2 port map ( do(((i+1)*2)-1 downto i*2), xa(12 downto 0),
clk, di(((i+1)*2)-1 downto i*2), enable, gnd, write);
end generate;
do(dbits+72 downto 2*(((dbits-1)/2)+1)) <= (others => '0');
end generate;
a14 : if abits = 14 generate
x : for i in 0 to (dbits-1) generate
r : RAMB16_S1 port map ( do((i+1)-1 downto i), xa(13 downto 0),
clk, di((i+1)-1 downto i), enable, gnd, write);
end generate;
do(dbits+72 downto dbits) <= (others => '0');
end generate;
a15 : if abits > 14 generate
x: generic_syncram generic map (abits, dbits)
port map (clk, address, datain, do(dbits-1 downto 0), write);
do(dbits+72 downto dbits) <= (others => '0');
end generate;
-- pragma translate_off
-- a_to_high : if abits > 14 generate
-- x : process
-- begin
-- assert false
-- report "Address depth larger than 14 not supported for virtex2_syncram"
-- severity failure;
-- wait;
-- end process;
-- end generate;
-- pragma translate_on
end;
LIBRARY ieee;
use ieee.std_logic_1164.all;
--pragma translate_off
library unisim;
use unisim.RAMB16_S36_S36;
use unisim.RAMB16_S18_S18;
use unisim.RAMB16_S9_S9;
use unisim.RAMB16_S4_S4;
use unisim.RAMB16_S2_S2;
use unisim.RAMB16_S1_S1;
--pragma translate_on
entity virtex2_syncram_dp is
generic (
abits : integer := 4; dbits : integer := 32
);
port (
clk1 : in std_ulogic;
address1 : in std_logic_vector((abits -1) downto 0);
datain1 : in std_logic_vector((dbits -1) downto 0);
dataout1 : out std_logic_vector((dbits -1) downto 0);
enable1 : in std_ulogic;
write1 : in std_ulogic;
clk2 : in std_ulogic;
address2 : in std_logic_vector((abits -1) downto 0);
datain2 : in std_logic_vector((dbits -1) downto 0);
dataout2 : out std_logic_vector((dbits -1) downto 0);
enable2 : in std_ulogic;
write2 : in std_ulogic);
end;
architecture behav of virtex2_syncram_dp is
component RAMB16_S4_S4
port (
DOA : out std_logic_vector (3 downto 0);
DOB : out std_logic_vector (3 downto 0);
ADDRA : in std_logic_vector (11 downto 0);
ADDRB : in std_logic_vector (11 downto 0);
CLKA : in std_ulogic;
CLKB : in std_ulogic;
DIA : in std_logic_vector (3 downto 0);
DIB : in std_logic_vector (3 downto 0);
ENA : in std_ulogic;
ENB : in std_ulogic;
SSRA : in std_ulogic;
SSRB : in std_ulogic;
WEA : in std_ulogic;
WEB : in std_ulogic
);
end component;
component RAMB16_S1_S1
port (
DOA : out std_logic_vector (0 downto 0);
DOB : out std_logic_vector (0 downto 0);
ADDRA : in std_logic_vector (13 downto 0);
ADDRB : in std_logic_vector (13 downto 0);
CLKA : in std_ulogic;
CLKB : in std_ulogic;
DIA : in std_logic_vector (0 downto 0);
DIB : in std_logic_vector (0 downto 0);
ENA : in std_ulogic;
ENB : in std_ulogic;
SSRA : in std_ulogic;
SSRB : in std_ulogic;
WEA : in std_ulogic;
WEB : in std_ulogic
);
end component;
component RAMB16_S2_S2
port (
DOA : out std_logic_vector (1 downto 0);
DOB : out std_logic_vector (1 downto 0);
ADDRA : in std_logic_vector (12 downto 0);
ADDRB : in std_logic_vector (12 downto 0);
CLKA : in std_ulogic;
CLKB : in std_ulogic;
DIA : in std_logic_vector (1 downto 0);
DIB : in std_logic_vector (1 downto 0);
ENA : in std_ulogic;
ENB : in std_ulogic;
SSRA : in std_ulogic;
SSRB : in std_ulogic;
WEA : in std_ulogic;
WEB : in std_ulogic
);
end component;
component RAMB16_S9_S9
port (
DOA : out std_logic_vector (7 downto 0);
DOB : out std_logic_vector (7 downto 0);
DOPA : out std_logic_vector (0 downto 0);
DOPB : out std_logic_vector (0 downto 0);
ADDRA : in std_logic_vector (10 downto 0);
ADDRB : in std_logic_vector (10 downto 0);
CLKA : in std_ulogic;
CLKB : in std_ulogic;
DIA : in std_logic_vector (7 downto 0);
DIB : in std_logic_vector (7 downto 0);
DIPA : in std_logic_vector (0 downto 0);
DIPB : in std_logic_vector (0 downto 0);
ENA : in std_ulogic;
ENB : in std_ulogic;
SSRA : in std_ulogic;
SSRB : in std_ulogic;
WEA : in std_ulogic;
WEB : in std_ulogic
);
end component;
component RAMB16_S18_S18
port (
DOA : out std_logic_vector (15 downto 0);
DOB : out std_logic_vector (15 downto 0);
DOPA : out std_logic_vector (1 downto 0);
DOPB : out std_logic_vector (1 downto 0);
ADDRA : in std_logic_vector (9 downto 0);
ADDRB : in std_logic_vector (9 downto 0);
CLKA : in std_ulogic;
CLKB : in std_ulogic;
DIA : in std_logic_vector (15 downto 0);
DIB : in std_logic_vector (15 downto 0);
DIPA : in std_logic_vector (1 downto 0);
DIPB : in std_logic_vector (1 downto 0);
ENA : in std_ulogic;
ENB : in std_ulogic;
SSRA : in std_ulogic;
SSRB : in std_ulogic;
WEA : in std_ulogic;
WEB : in std_ulogic);
end component;
component RAMB16_S36_S36
port (
DOA : out std_logic_vector (31 downto 0);
DOB : out std_logic_vector (31 downto 0);
DOPA : out std_logic_vector (3 downto 0);
DOPB : out std_logic_vector (3 downto 0);
ADDRA : in std_logic_vector (8 downto 0);
ADDRB : in std_logic_vector (8 downto 0);
CLKA : in std_ulogic;
CLKB : in std_ulogic;
DIA : in std_logic_vector (31 downto 0);
DIB : in std_logic_vector (31 downto 0);
DIPA : in std_logic_vector (3 downto 0);
DIPB : in std_logic_vector (3 downto 0);
ENA : in std_ulogic;
ENB : in std_ulogic;
SSRA : in std_ulogic;
SSRB : in std_ulogic;
WEA : in std_ulogic;
WEB : in std_ulogic);
end component;
signal gnd, vcc : std_ulogic;
signal do1, do2, di1, di2 : std_logic_vector(dbits+36 downto 0);
signal addr1, addr2 : std_logic_vector(19 downto 0);
begin
gnd <= '0'; vcc <= '1';
dataout1 <= do1(dbits-1 downto 0); dataout2 <= do2(dbits-1 downto 0);
di1(dbits-1 downto 0) <= datain1; di1(dbits+36 downto dbits) <= (others => '0');
di2(dbits-1 downto 0) <= datain2; di2(dbits+36 downto dbits) <= (others => '0');
addr1(abits-1 downto 0) <= address1; addr1(19 downto abits) <= (others => '0');
addr2(abits-1 downto 0) <= address2; addr2(19 downto abits) <= (others => '0');
a9 : if abits <= 9 generate
x : for i in 0 to ((dbits-1)/36) generate
r0 : RAMB16_S36_S36 port map (
do1(((i+1)*36)-5 downto i*36), do2(((i+1)*36)-5 downto i*36),
do1(((i+1)*36)-1 downto i*36+32), do2(((i+1)*36)-1 downto i*36+32),
addr1(8 downto 0), addr2(8 downto 0), clk1, clk2,
di1(((i+1)*36)-5 downto i*36), di2(((i+1)*36)-5 downto i*36),
di1(((i+1)*36)-1 downto i*36+32), di2(((i+1)*36)-1 downto i*36+32),
-- enable1, enable2, gnd, gnd, write1, write2);
vcc, vcc, gnd, gnd, write1, write2);
end generate;
do1(dbits+36 downto 36*(((dbits-1)/36)+1)) <= (others => '0');
do2(dbits+36 downto 36*(((dbits-1)/36)+1)) <= (others => '0');
end generate;
a10 : if abits = 10 generate
x : for i in 0 to ((dbits-1)/18) generate
r0 : RAMB16_S18_S18 port map (
do1(((i+1)*18)-3 downto i*18), do2(((i+1)*18)-3 downto i*18),
do1(((i+1)*18)-1 downto i*18+16), do2(((i+1)*18)-1 downto i*18+16),
addr1(9 downto 0), addr2(9 downto 0), clk1, clk2,
di1(((i+1)*18)-3 downto i*18), di2(((i+1)*18)-3 downto i*18),
di1(((i+1)*18)-1 downto i*18+16), di2(((i+1)*18)-1 downto i*18+16),
vcc, vcc, gnd, gnd, write1, write2);
-- enable1, enable2, gnd, gnd, write1, write2);
end generate;
do1(dbits+36 downto 18*(((dbits-1)/18)+1)) <= (others => '0');
do2(dbits+36 downto 18*(((dbits-1)/18)+1)) <= (others => '0');
end generate;
a11 : if abits = 11 generate
x : for i in 0 to ((dbits-1)/9) generate
r0 : RAMB16_S9_S9 port map (
do1(((i+1)*9)-2 downto i*9), do2(((i+1)*9)-2 downto i*9),
do1(((i+1)*9)-1 downto i*9+8), do2(((i+1)*9)-1 downto i*9+8),
addr1(10 downto 0), addr2(10 downto 0), clk1, clk2,
di1(((i+1)*9)-2 downto i*9), di2(((i+1)*9)-2 downto i*9),
di1(((i+1)*9)-1 downto i*9+8), di2(((i+1)*9)-1 downto i*9+8),
vcc, vcc, gnd, gnd, write1, write2);
-- enable1, enable2, gnd, gnd, write1, write2);
end generate;
do1(dbits+36 downto 9*(((dbits-1)/9)+1)) <= (others => '0');
do2(dbits+36 downto 9*(((dbits-1)/9)+1)) <= (others => '0');
end generate;
a12 : if abits = 12 generate
x : for i in 0 to ((dbits-1)/4) generate
r0 : RAMB16_S4_S4 port map (
do1(((i+1)*4)-1 downto i*4), do2(((i+1)*4)-1 downto i*4),
addr1(11 downto 0), addr2(11 downto 0), clk1, clk2,
di1(((i+1)*4)-1 downto i*4), di2(((i+1)*4)-1 downto i*4),
vcc, vcc, gnd, gnd, write1, write2);
-- enable1, enable2, gnd, gnd, write1, write2);
end generate;
do1(dbits+36 downto 4*(((dbits-1)/4)+1)) <= (others => '0');
do2(dbits+36 downto 4*(((dbits-1)/4)+1)) <= (others => '0');
end generate;
a13 : if abits = 13 generate
x : for i in 0 to ((dbits-1)/2) generate
r0 : RAMB16_S2_S2 port map (
do1(((i+1)*2)-1 downto i*2), do2(((i+1)*2)-1 downto i*2),
addr1(12 downto 0), addr2(12 downto 0), clk1, clk2,
di1(((i+1)*2)-1 downto i*2), di2(((i+1)*2)-1 downto i*2),
vcc, vcc, gnd, gnd, write1, write2);
-- enable1, enable2, gnd, gnd, write1, write2);
end generate;
do1(dbits+36 downto 2*(((dbits-1)/2)+1)) <= (others => '0');
do2(dbits+36 downto 2*(((dbits-1)/2)+1)) <= (others => '0');
end generate;
a14 : if abits = 14 generate
x : for i in 0 to ((dbits-1)/1) generate
r0 : RAMB16_S1_S1 port map (
do1(((i+1)*1)-1 downto i*1), do2(((i+1)*1)-1 downto i*1),
addr1(13 downto 0), addr2(13 downto 0), clk1, clk2,
di1(((i+1)*1)-1 downto i*1), di2(((i+1)*1)-1 downto i*1),
vcc, vcc, gnd, gnd, write1, write2);
-- enable1, enable2, gnd, gnd, write1, write2);
end generate;
do1(dbits+36 downto dbits) <= (others => '0');
do2(dbits+36 downto dbits) <= (others => '0');
end generate;
-- pragma translate_off
a_to_high : if abits > 14 generate
x : process
begin
assert false
report "Address depth larger than 14 not supported for virtex2_syncram_dp"
severity failure;
wait;
end process;
end generate;
-- pragma translate_on
end;
library ieee;
use ieee.std_logic_1164.all;
entity virtex2_syncram_2p is
generic (abits : integer := 6; dbits : integer := 8; sepclk : integer := 0;
wrfst : integer := 0);
port (
rclk : in std_ulogic;
renable : in std_ulogic;
raddress : in std_logic_vector((abits -1) downto 0);
dataout : out std_logic_vector((dbits -1) downto 0);
wclk : in std_ulogic;
write : in std_ulogic;
waddress : in std_logic_vector((abits -1) downto 0);
datain : in std_logic_vector((dbits -1) downto 0));
end;
architecture behav of virtex2_syncram_2p is
component virtex2_syncram_dp
generic ( abits : integer := 10; dbits : integer := 8 );
port (
clk1 : in std_ulogic;
address1 : in std_logic_vector((abits -1) downto 0);
datain1 : in std_logic_vector((dbits -1) downto 0);
dataout1 : out std_logic_vector((dbits -1) downto 0);
enable1 : in std_ulogic;
write1 : in std_ulogic;
clk2 : in std_ulogic;
address2 : in std_logic_vector((abits -1) downto 0);
datain2 : in std_logic_vector((dbits -1) downto 0);
dataout2 : out std_logic_vector((dbits -1) downto 0);
enable2 : in std_ulogic;
write2 : in std_ulogic
);
end component;
component generic_syncram_2p
generic (abits : integer := 8; dbits : integer := 32; sepclk : integer := 0);
port (
rclk : in std_ulogic;
wclk : in std_ulogic;
rdaddress: in std_logic_vector (abits -1 downto 0);
wraddress: in std_logic_vector (abits -1 downto 0);
data: in std_logic_vector (dbits -1 downto 0);
wren : in std_ulogic;
q: out std_logic_vector (dbits -1 downto 0)
);
end component;
signal write2, renable2 : std_ulogic;
signal datain2 : std_logic_vector((dbits-1) downto 0);
begin
nowf: if wrfst = 0 generate
write2 <= '0'; renable2 <= renable; datain2 <= (others => '0');
end generate;
wf : if wrfst = 1 generate
write2 <= '0' when (waddress /= raddress) else write;
renable2 <= renable or write2; datain2 <= datain;
end generate;
a0 : if abits <= 5 generate
x0 : generic_syncram_2p generic map (abits, dbits, sepclk)
port map (rclk, wclk, raddress, waddress, datain, write, dataout);
end generate;
a6 : if abits > 5 generate
x0 : virtex2_syncram_dp generic map (abits, dbits)
port map (wclk, waddress, datain, open, write, write,
rclk, raddress, datain2, dataout, renable2, write2);
end generate;
end;
-- parametrisable sync ram generator using virtex2 block rams
library ieee;
use ieee.std_logic_1164.all;
--pragma translate_off
library unisim;
use unisim.RAMB16_S36_S36;
--pragma translate_on
entity virtex2_syncram64 is
generic ( abits : integer := 9);
port (
clk : in std_ulogic;
address : in std_logic_vector (abits -1 downto 0);
datain : in std_logic_vector (63 downto 0);
dataout : out std_logic_vector (63 downto 0);
enable : in std_logic_vector (1 downto 0);
write : in std_logic_vector (1 downto 0)
);
end;
architecture behav of virtex2_syncram64 is
component virtex2_syncram
generic ( abits : integer := 9; dbits : integer := 32);
port (
clk : in std_ulogic;
address : in std_logic_vector (abits -1 downto 0);
datain : in std_logic_vector (dbits -1 downto 0);
dataout : out std_logic_vector (dbits -1 downto 0);
enable : in std_ulogic;
write : in std_ulogic
);
end component;
component RAMB16_S36_S36
port (
DOA : out std_logic_vector (31 downto 0);
DOB : out std_logic_vector (31 downto 0);
DOPA : out std_logic_vector (3 downto 0);
DOPB : out std_logic_vector (3 downto 0);
ADDRA : in std_logic_vector (8 downto 0);
ADDRB : in std_logic_vector (8 downto 0);
CLKA : in std_ulogic;
CLKB : in std_ulogic;
DIA : in std_logic_vector (31 downto 0);
DIB : in std_logic_vector (31 downto 0);
DIPA : in std_logic_vector (3 downto 0);
DIPB : in std_logic_vector (3 downto 0);
ENA : in std_ulogic;
ENB : in std_ulogic;
SSRA : in std_ulogic;
SSRB : in std_ulogic;
WEA : in std_ulogic;
WEB : in std_ulogic);
end component;
signal gnd : std_logic_vector(3 downto 0);
signal xa, ya : std_logic_vector(19 downto 0);
begin
gnd <= "0000";
xa(abits-1 downto 0) <= address; xa(19 downto abits) <= (others => '0');
ya(abits-1 downto 0) <= address; ya(19 downto abits) <= (others => '1');
a8 : if abits <= 8 generate
r0 : RAMB16_S36_S36 port map (
dataout(63 downto 32), dataout(31 downto 0), open, open,
xa(8 downto 0), ya(8 downto 0), clk, clk,
datain(63 downto 32), datain(31 downto 0), gnd, gnd,
enable(1), enable(0), gnd(0), gnd(0), write(1), write(0));
end generate;
a9 : if abits > 8 generate
x1 : virtex2_syncram generic map ( abits, 32)
port map (clk, address, datain(63 downto 32), dataout(63 downto 32),
enable(1), write(1));
x2 : virtex2_syncram generic map ( abits, 32)
port map (clk, address, datain(31 downto 0), dataout(31 downto 0),
enable(0), write(0));
end generate;
end;
| mit | e864aa9c72d898971d86ad910365aa59 | 0.606167 | 2.936427 | false | false | false | false |
impedimentToProgress/UCI-BlueChip | AttackFiles/Attacks/privEsc/lib/tech/ec/orca/orca_ecmem.vhd | 2 | 68,477 |
----- package mem3 -----
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
PACKAGE mem3 IS
TYPE mem_type_5 IS array (Integer range <>) OF std_logic_vector(17 downto 0);
TYPE mem_type_6 IS array (Integer range <>) OF std_logic_vector(15 downto 0);
FUNCTION hex2bin (hex: character) RETURN std_logic_vector;
FUNCTION str3_slv12 (hex: string) RETURN std_logic_vector;
FUNCTION data2data (data_w: integer) RETURN integer;
FUNCTION data2addr_w (data_w: integer) RETURN integer;
FUNCTION data2data_w (data_w: integer) RETURN integer;
FUNCTION init_ram (hex: string; DATA_WIDTH_A : integer; DATA_WIDTH_B : integer) RETURN std_logic_vector;
FUNCTION init_ram1 (hex: string) RETURN mem_type_6;
FUNCTION str2slv (str: in string) RETURN std_logic_vector;
FUNCTION Valid_Address (IN_ADDR : in std_logic_vector) return boolean;
END mem3;
PACKAGE BODY mem3 IS
FUNCTION hex2bin (hex: character) RETURN std_logic_vector IS
VARIABLE result : std_logic_vector (3 downto 0);
BEGIN
CASE hex IS
WHEN '0' =>
result := "0000";
WHEN '1' =>
result := "0001";
WHEN '2' =>
result := "0010";
WHEN '3' =>
result := "0011";
WHEN '4' =>
result := "0100";
WHEN '5' =>
result := "0101";
WHEN '6' =>
result := "0110";
WHEN '7' =>
result := "0111";
WHEN '8' =>
result := "1000";
WHEN '9' =>
result := "1001";
WHEN 'A'|'a' =>
result := "1010";
WHEN 'B'|'b' =>
result := "1011";
WHEN 'C'|'c' =>
result := "1100";
WHEN 'D'|'d' =>
result := "1101";
WHEN 'E'|'e' =>
result := "1110";
WHEN 'F'|'f' =>
result := "1111";
WHEN 'X'|'x' =>
result := "XXXX";
WHEN others =>
NULL;
END CASE;
RETURN result;
END;
FUNCTION str5_slv18 (s : string(5 downto 1)) return std_logic_vector is
VARIABLE result : std_logic_vector(17 downto 0);
BEGIN
FOR i in 0 to 3 LOOP
result(((i+1)*4)-1 downto (i*4)) := hex2bin(s(i+1));
END LOOP;
result(17 downto 16) := hex2bin(s(5))(1 downto 0);
RETURN result;
END;
FUNCTION str4_slv16 (s : string(4 downto 1)) return std_logic_vector is
VARIABLE result : std_logic_vector(15 downto 0);
BEGIN
FOR i in 0 to 3 LOOP
result(((i+1)*4)-1 downto (i*4)) := hex2bin(s(i+1));
END LOOP;
RETURN result;
END;
FUNCTION str3_slv12 (hex: string) return std_logic_vector is
VARIABLE result : std_logic_vector(11 downto 0);
BEGIN
FOR i in 0 to 2 LOOP
result(((i+1)*4)-1 downto (i*4)) := hex2bin(hex(i+1));
END LOOP;
RETURN result;
END;
FUNCTION data2addr_w (data_w : integer) return integer is
VARIABLE result : integer;
BEGIN
CASE data_w IS
WHEN 1 =>
result := 13;
WHEN 2 =>
result := 12;
WHEN 4 =>
result := 11;
WHEN 9 =>
result := 10;
WHEN 18 =>
result := 9;
WHEN 36 =>
result := 8;
WHEN others =>
NULL;
END CASE;
RETURN result;
END;
FUNCTION data2data_w (data_w : integer) return integer is
VARIABLE result : integer;
BEGIN
CASE data_w IS
WHEN 1 =>
result := 1;
WHEN 2 =>
result := 2;
WHEN 4 =>
result := 4;
WHEN 9 =>
result := 9;
WHEN 18 =>
result := 18;
WHEN 36 =>
result := 18;
WHEN others =>
NULL;
END CASE;
RETURN result;
END;
FUNCTION data2data (data_w : integer) return integer is
VARIABLE result : integer;
BEGIN
CASE data_w IS
WHEN 1 =>
result := 8;
WHEN 2 =>
result := 4;
WHEN 4 =>
result := 2;
WHEN 9 =>
result := 36864;
WHEN 18 =>
result := 36864;
WHEN 36 =>
result := 36864;
WHEN others =>
NULL;
END CASE;
RETURN result;
END;
FUNCTION init_ram (hex: string; DATA_WIDTH_A : integer; DATA_WIDTH_B : integer) RETURN std_logic_vector IS
CONSTANT length : integer := hex'length;
VARIABLE result1 : mem_type_5 (0 to ((length/5)-1));
VARIABLE result : std_logic_vector(((length*18)/5)-1 downto 0);
BEGIN
FOR i in 0 to ((length/5)-1) LOOP
result1(i) := str5_slv18(hex((i+1)*5 downto (i*5)+1));
END LOOP;
IF (DATA_WIDTH_A >= 9 and DATA_WIDTH_B >= 9) THEN
FOR j in 0 to 511 LOOP
result(((j*18) + 17) downto (j*18)) := result1(j)(17 downto 0);
END LOOP;
ELSE
FOR j in 0 to 511 LOOP
result(((j*18) + 7) downto (j*18)) := result1(j)(7 downto 0);
result((j*18) + 8) := '0';
result(((j*18) + 16) downto ((j*18) + 9)) := result1(j)(15 downto 8);
result((j*18) + 17) := '0';
END LOOP;
END IF;
RETURN result;
END;
FUNCTION init_ram1 (hex: string) RETURN mem_type_6 IS
CONSTANT length : integer := hex'length;
VARIABLE result : mem_type_6 (0 to ((length/4)-1));
BEGIN
FOR i in 0 to ((length/4)-1) LOOP
result(i) := str4_slv16(hex((i+1)*4 downto (i*4)+1));
END LOOP;
RETURN result;
END;
-- String to std_logic_vector
FUNCTION str2slv (
str : in string
) return std_logic_vector is
variable j : integer := str'length;
variable slv : std_logic_vector (str'length downto 1);
begin
for i in str'low to str'high loop
case str(i) is
when '0' => slv(j) := '0';
when '1' => slv(j) := '1';
when 'X' => slv(j) := 'X';
when 'U' => slv(j) := 'U';
when others => slv(j) := 'X';
end case;
j := j - 1;
end loop;
return slv;
end str2slv;
function Valid_Address (
IN_ADDR : in std_logic_vector
) return boolean is
variable v_Valid_Flag : boolean := TRUE;
begin
for i in IN_ADDR'high downto IN_ADDR'low loop
if (IN_ADDR(i) /= '0' and IN_ADDR(i) /= '1') then
v_Valid_Flag := FALSE;
end if;
end loop;
return v_Valid_Flag;
end Valid_Address;
END mem3 ;
--
-----cell dp8ka----
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.vital_timing.all;
use ieee.vital_primitives.all;
--use ieee.std_logic_unsigned.all;
library ec;
use ec.global.gsrnet;
use ec.global.purnet;
use ec.mem3.all;
library grlib;
use grlib.stdlib.all;
-- entity declaration --
ENTITY dp8ka IS
GENERIC (
DATA_WIDTH_A : Integer := 18;
DATA_WIDTH_B : Integer := 18;
REGMODE_A : String := "NOREG";
REGMODE_B : String := "NOREG";
RESETMODE : String := "ASYNC";
CSDECODE_A : String := "000";
CSDECODE_B : String := "000";
WRITEMODE_A : String := "NORMAL";
WRITEMODE_B : String := "NORMAL";
GSR : String := "ENABLED";
initval_00 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_01 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_02 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_03 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_04 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_05 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_06 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_07 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_08 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_09 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0a : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0b : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0c : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0d : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0e : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0f : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_10 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_11 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_12 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_13 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_14 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_15 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_16 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_17 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_18 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_19 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1a : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1b : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1c : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1d : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1e : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1f : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
-- miscellaneous vital GENERICs
TimingChecksOn : boolean := TRUE;
XOn : boolean := FALSE;
MsgOn : boolean := TRUE;
InstancePath : string := "dp8ka";
-- input SIGNAL delays
tipd_ada12 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_ada11 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_ada10 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_ada9 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_ada8 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_ada7 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_ada6 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_ada5 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_ada4 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_ada3 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_ada2 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_ada1 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_ada0 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_dia17 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_dia16 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_dia15 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_dia14 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_dia13 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_dia12 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_dia11 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_dia10 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_dia9 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_dia8 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_dia7 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_dia6 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_dia5 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_dia4 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_dia3 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_dia2 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_dia1 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_dia0 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_clka : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_cea : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_wea : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_csa0 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_csa1 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_csa2 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_rsta : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_adb12 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_adb11 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_adb10 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_adb9 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_adb8 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_adb7 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_adb6 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_adb5 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_adb4 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_adb3 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_adb2 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_adb1 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_adb0 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_dib17 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_dib16 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_dib15 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_dib14 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_dib13 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_dib12 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_dib11 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_dib10 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_dib9 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_dib8 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_dib7 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_dib6 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_dib5 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_dib4 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_dib3 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_dib2 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_dib1 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_dib0 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_clkb : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_ceb : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_web : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_csb0 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_csb1 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_csb2 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_rstb : VitalDelayType01 := (0.0 ns, 0.0 ns);
-- propagation delays
-- setup and hold constraints
-- pulse width constraints
tperiod_clka : VitalDelayType := 0.001 ns;
tpw_clka_posedge : VitalDelayType := 0.001 ns;
tpw_clka_negedge : VitalDelayType := 0.001 ns;
tperiod_clkb : VitalDelayType := 0.001 ns;
tpw_clkb_posedge : VitalDelayType := 0.001 ns;
tpw_clkb_negedge : VitalDelayType := 0.001 ns);
PORT(
dia0, dia1, dia2, dia3, dia4, dia5, dia6, dia7, dia8 : in std_logic := 'X';
dia9, dia10, dia11, dia12, dia13, dia14, dia15, dia16, dia17 : in std_logic := 'X';
ada0, ada1, ada2, ada3, ada4, ada5, ada6, ada7, ada8 : in std_logic := 'X';
ada9, ada10, ada11, ada12 : in std_logic := 'X';
cea, clka, wea, csa0, csa1, csa2, rsta : in std_logic := 'X';
dib0, dib1, dib2, dib3, dib4, dib5, dib6, dib7, dib8 : in std_logic := 'X';
dib9, dib10, dib11, dib12, dib13, dib14, dib15, dib16, dib17 : in std_logic := 'X';
adb0, adb1, adb2, adb3, adb4, adb5, adb6, adb7, adb8 : in std_logic := 'X';
adb9, adb10, adb11, adb12 : in std_logic := 'X';
ceb, clkb, web, csb0, csb1, csb2, rstb : in std_logic := 'X';
doa0, doa1, doa2, doa3, doa4, doa5, doa6, doa7, doa8 : out std_logic := 'X';
doa9, doa10, doa11, doa12, doa13, doa14, doa15, doa16, doa17 : out std_logic := 'X';
dob0, dob1, dob2, dob3, dob4, dob5, dob6, dob7, dob8 : out std_logic := 'X';
dob9, dob10, dob11, dob12, dob13, dob14, dob15, dob16, dob17 : out std_logic := 'X'
);
ATTRIBUTE Vital_Level0 OF dp8ka : ENTITY IS TRUE;
END dp8ka ;
-- ARCHITECTURE body --
ARCHITECTURE V OF dp8ka IS
ATTRIBUTE Vital_Level0 OF V : ARCHITECTURE IS TRUE;
--SIGNAL DECLARATIONS----
SIGNAL ada_ipd : std_logic_vector(12 downto 0) := (others => '0');
SIGNAL dia_ipd : std_logic_vector(17 downto 0) := (others => '0');
SIGNAL clka_ipd : std_logic := '0';
SIGNAL cea_ipd : std_logic := '0';
SIGNAL wrea_ipd : std_logic := '0';
SIGNAL csa_ipd : std_logic_vector(2 downto 0) := "000";
SIGNAL rsta_ipd : std_logic := '0';
SIGNAL adb_ipd : std_logic_vector(12 downto 0) := "XXXXXXXXXXXXX";
SIGNAL dib_ipd : std_logic_vector(17 downto 0) := "XXXXXXXXXXXXXXXXXX";
SIGNAL clkb_ipd : std_logic := '0';
SIGNAL ceb_ipd : std_logic := '0';
SIGNAL wreb_ipd : std_logic := '0';
SIGNAL csb_ipd : std_logic_vector(2 downto 0) := "000";
SIGNAL rstb_ipd : std_logic := '0';
SIGNAL csa_en : std_logic := '0';
SIGNAL csb_en : std_logic := '0';
SIGNAL g_reset : std_logic := '0';
CONSTANT ADDR_WIDTH_A : integer := data2addr_w(DATA_WIDTH_A);
CONSTANT ADDR_WIDTH_B : integer := data2addr_w(DATA_WIDTH_B);
CONSTANT new_data_width_a : integer := data2data_w(DATA_WIDTH_A);
CONSTANT new_data_width_b : integer := data2data_w(DATA_WIDTH_B);
CONSTANT div_a : integer := data2data(DATA_WIDTH_A);
CONSTANT div_b : integer := data2data(DATA_WIDTH_B);
SIGNAL dia_node : std_logic_vector((new_data_width_a - 1) downto 0) := (others => '0');
SIGNAL dib_node : std_logic_vector((new_data_width_b - 1) downto 0) := (others => '0');
SIGNAL ada_node : std_logic_vector((ADDR_WIDTH_A - 1) downto 0) := (others => '0');
SIGNAL adb_node : std_logic_vector((ADDR_WIDTH_B - 1) downto 0) := (others => '0');
SIGNAL diab_node : std_logic_vector(35 downto 0) := (others => '0');
SIGNAL rsta_int : std_logic := '0';
SIGNAL rstb_int : std_logic := '0';
SIGNAL rsta_reg : std_logic := '0';
SIGNAL rstb_reg : std_logic := '0';
SIGNAL reseta : std_logic := '0';
SIGNAL resetb : std_logic := '0';
SIGNAL dia_reg : std_logic_vector((new_data_width_a - 1) downto 0) := (others => '0');
SIGNAL dib_reg : std_logic_vector((new_data_width_b - 1) downto 0) := (others => '0');
SIGNAL ada_reg : std_logic_vector((ADDR_WIDTH_A - 1) downto 0);
SIGNAL adb_reg : std_logic_vector((ADDR_WIDTH_B - 1) downto 0);
SIGNAL diab_reg : std_logic_vector(35 downto 0) := (others => '0');
SIGNAL wrena_reg : std_logic := '0';
SIGNAL clka_valid : std_logic := '0';
SIGNAL clkb_valid : std_logic := '0';
SIGNAL clka_valid1 : std_logic := '0';
SIGNAL clkb_valid1 : std_logic := '0';
SIGNAL wrenb_reg : std_logic := '0';
SIGNAL rena_reg : std_logic := '0';
SIGNAL renb_reg : std_logic := '0';
SIGNAL rsta_sig : std_logic := '0';
SIGNAL rstb_sig : std_logic := '0';
SIGNAL doa_node : std_logic_vector(17 downto 0) := (others => '0');
SIGNAL doa_node_tr : std_logic_vector(17 downto 0) := (others => '0');
SIGNAL doa_node_wt : std_logic_vector(17 downto 0) := (others => '0');
SIGNAL doa_node_rbr : std_logic_vector(17 downto 0) := (others => '0');
SIGNAL dob_node : std_logic_vector(17 downto 0) := (others => '0');
SIGNAL dob_node_tr : std_logic_vector(17 downto 0) := (others => '0');
SIGNAL dob_node_wt : std_logic_vector(17 downto 0) := (others => '0');
SIGNAL dob_node_rbr : std_logic_vector(17 downto 0) := (others => '0');
SIGNAL doa_reg : std_logic_vector(17 downto 0) := (others => '0');
SIGNAL dob_reg : std_logic_vector(17 downto 0) := (others => '0');
SIGNAL doab_reg : std_logic_vector(17 downto 0) := (others => '0');
SIGNAL doa_int : std_logic_vector(17 downto 0) := (others => '0');
SIGNAL dob_int : std_logic_vector(17 downto 0) := (others => '0');
CONSTANT initval : string(2560 downto 1) := (
initval_1f(3 to 82)&initval_1e(3 to 82)&initval_1d(3 to 82)&initval_1c(3 to 82)&
initval_1b(3 to 82)&initval_1a(3 to 82)&initval_19(3 to 82)&initval_18(3 to 82)&
initval_17(3 to 82)&initval_16(3 to 82)&initval_15(3 to 82)&initval_14(3 to 82)&
initval_13(3 to 82)&initval_12(3 to 82)&initval_11(3 to 82)&initval_10(3 to 82)&
initval_0f(3 to 82)&initval_0e(3 to 82)&initval_0d(3 to 82)&initval_0c(3 to 82)&
initval_0b(3 to 82)&initval_0a(3 to 82)&initval_09(3 to 82)&initval_08(3 to 82)&
initval_07(3 to 82)&initval_06(3 to 82)&initval_05(3 to 82)&initval_04(3 to 82)&
initval_03(3 to 82)&initval_02(3 to 82)&initval_01(3 to 82)&initval_00(3 to 82));
SIGNAL MEM : std_logic_vector(9215 downto 0) := init_ram (initval, DATA_WIDTH_A, DATA_WIDTH_B);
SIGNAL j : integer := 0;
BEGIN
-----------------------
-- input path delays
-----------------------
WireDelay : BLOCK
BEGIN
VitalWireDelay(ada_ipd(0), ada0, tipd_ada0);
VitalWireDelay(ada_ipd(1), ada1, tipd_ada1);
VitalWireDelay(ada_ipd(2), ada2, tipd_ada2);
VitalWireDelay(ada_ipd(3), ada3, tipd_ada3);
VitalWireDelay(ada_ipd(4), ada4, tipd_ada4);
VitalWireDelay(ada_ipd(5), ada5, tipd_ada5);
VitalWireDelay(ada_ipd(6), ada6, tipd_ada6);
VitalWireDelay(ada_ipd(7), ada7, tipd_ada7);
VitalWireDelay(ada_ipd(8), ada8, tipd_ada8);
VitalWireDelay(ada_ipd(9), ada9, tipd_ada9);
VitalWireDelay(ada_ipd(10), ada10, tipd_ada10);
VitalWireDelay(ada_ipd(11), ada11, tipd_ada11);
VitalWireDelay(ada_ipd(12), ada12, tipd_ada12);
VitalWireDelay(dia_ipd(0), dia0, tipd_dia0);
VitalWireDelay(dia_ipd(1), dia1, tipd_dia1);
VitalWireDelay(dia_ipd(2), dia2, tipd_dia2);
VitalWireDelay(dia_ipd(3), dia3, tipd_dia3);
VitalWireDelay(dia_ipd(4), dia4, tipd_dia4);
VitalWireDelay(dia_ipd(5), dia5, tipd_dia5);
VitalWireDelay(dia_ipd(6), dia6, tipd_dia6);
VitalWireDelay(dia_ipd(7), dia7, tipd_dia7);
VitalWireDelay(dia_ipd(8), dia8, tipd_dia8);
VitalWireDelay(dia_ipd(9), dia9, tipd_dia9);
VitalWireDelay(dia_ipd(10), dia10, tipd_dia10);
VitalWireDelay(dia_ipd(11), dia11, tipd_dia11);
VitalWireDelay(dia_ipd(12), dia12, tipd_dia12);
VitalWireDelay(dia_ipd(13), dia13, tipd_dia13);
VitalWireDelay(dia_ipd(14), dia14, tipd_dia14);
VitalWireDelay(dia_ipd(15), dia15, tipd_dia15);
VitalWireDelay(dia_ipd(16), dia16, tipd_dia16);
VitalWireDelay(dia_ipd(17), dia17, tipd_dia17);
VitalWireDelay(clka_ipd, clka, tipd_clka);
VitalWireDelay(wrea_ipd, wea, tipd_wea);
VitalWireDelay(cea_ipd, cea, tipd_cea);
VitalWireDelay(csa_ipd(0), csa0, tipd_csa0);
VitalWireDelay(csa_ipd(1), csa1, tipd_csa1);
VitalWireDelay(csa_ipd(2), csa2, tipd_csa2);
VitalWireDelay(rsta_ipd, rsta, tipd_rsta);
VitalWireDelay(adb_ipd(0), adb0, tipd_adb0);
VitalWireDelay(adb_ipd(1), adb1, tipd_adb1);
VitalWireDelay(adb_ipd(2), adb2, tipd_adb2);
VitalWireDelay(adb_ipd(3), adb3, tipd_adb3);
VitalWireDelay(adb_ipd(4), adb4, tipd_adb4);
VitalWireDelay(adb_ipd(5), adb5, tipd_adb5);
VitalWireDelay(adb_ipd(6), adb6, tipd_adb6);
VitalWireDelay(adb_ipd(7), adb7, tipd_adb7);
VitalWireDelay(adb_ipd(8), adb8, tipd_adb8);
VitalWireDelay(adb_ipd(9), adb9, tipd_adb9);
VitalWireDelay(adb_ipd(10), adb10, tipd_adb10);
VitalWireDelay(adb_ipd(11), adb11, tipd_adb11);
VitalWireDelay(adb_ipd(12), adb12, tipd_adb12);
VitalWireDelay(dib_ipd(0), dib0, tipd_dib0);
VitalWireDelay(dib_ipd(1), dib1, tipd_dib1);
VitalWireDelay(dib_ipd(2), dib2, tipd_dib2);
VitalWireDelay(dib_ipd(3), dib3, tipd_dib3);
VitalWireDelay(dib_ipd(4), dib4, tipd_dib4);
VitalWireDelay(dib_ipd(5), dib5, tipd_dib5);
VitalWireDelay(dib_ipd(6), dib6, tipd_dib6);
VitalWireDelay(dib_ipd(7), dib7, tipd_dib7);
VitalWireDelay(dib_ipd(8), dib8, tipd_dib8);
VitalWireDelay(dib_ipd(9), dib9, tipd_dib9);
VitalWireDelay(dib_ipd(10), dib10, tipd_dib10);
VitalWireDelay(dib_ipd(11), dib11, tipd_dib11);
VitalWireDelay(dib_ipd(12), dib12, tipd_dib12);
VitalWireDelay(dib_ipd(13), dib13, tipd_dib13);
VitalWireDelay(dib_ipd(14), dib14, tipd_dib14);
VitalWireDelay(dib_ipd(15), dib15, tipd_dib15);
VitalWireDelay(dib_ipd(16), dib16, tipd_dib16);
VitalWireDelay(dib_ipd(17), dib17, tipd_dib17);
VitalWireDelay(clkb_ipd, clkb, tipd_clkb);
VitalWireDelay(wreb_ipd, web, tipd_web);
VitalWireDelay(ceb_ipd, ceb, tipd_ceb);
VitalWireDelay(csb_ipd(0), csb0, tipd_csb0);
VitalWireDelay(csb_ipd(1), csb1, tipd_csb1);
VitalWireDelay(csb_ipd(2), csb2, tipd_csb2);
VitalWireDelay(rstb_ipd, rstb, tipd_rstb);
END BLOCK;
GLOBALRESET : PROCESS (purnet, gsrnet)
BEGIN
IF (GSR = "DISABLED") THEN
g_reset <= purnet;
ELSE
g_reset <= purnet AND gsrnet;
END IF;
END PROCESS;
rsta_sig <= rsta_ipd or (not g_reset);
rstb_sig <= rstb_ipd or (not g_reset);
-- set_reset <= g_reset and (not reset_ipd);
ada_node <= ada_ipd(12 downto (13 - ADDR_WIDTH_A));
adb_node <= adb_ipd(12 downto (13 - ADDR_WIDTH_B));
-- chip select A decode
P1 : PROCESS(csa_ipd)
BEGIN
IF (csa_ipd = "000" and CSDECODE_A = "000") THEN
csa_en <= '1';
ELSIF (csa_ipd = "001" and CSDECODE_A = "001") THEN
csa_en <= '1';
ELSIF (csa_ipd = "010" and CSDECODE_A = "010") THEN
csa_en <= '1';
ELSIF (csa_ipd = "011" and CSDECODE_A = "011") THEN
csa_en <= '1';
ELSIF (csa_ipd = "100" and CSDECODE_A = "100") THEN
csa_en <= '1';
ELSIF (csa_ipd = "101" and CSDECODE_A = "101") THEN
csa_en <= '1';
ELSIF (csa_ipd = "110" and CSDECODE_A = "110") THEN
csa_en <= '1';
ELSIF (csa_ipd = "111" and CSDECODE_A = "111") THEN
csa_en <= '1';
ELSE
csa_en <= '0';
END IF;
END PROCESS;
P2 : PROCESS(csb_ipd)
BEGIN
IF (csb_ipd = "000" and CSDECODE_B = "000") THEN
csb_en <= '1';
ELSIF (csb_ipd = "001" and CSDECODE_B = "001") THEN
csb_en <= '1';
ELSIF (csb_ipd = "010" and CSDECODE_B = "010") THEN
csb_en <= '1';
ELSIF (csb_ipd = "011" and CSDECODE_B = "011") THEN
csb_en <= '1';
ELSIF (csb_ipd = "100" and CSDECODE_B = "100") THEN
csb_en <= '1';
ELSIF (csb_ipd = "101" and CSDECODE_B = "101") THEN
csb_en <= '1';
ELSIF (csb_ipd = "110" and CSDECODE_B = "110") THEN
csb_en <= '1';
ELSIF (csb_ipd = "111" and CSDECODE_B = "111") THEN
csb_en <= '1';
ELSE
csb_en <= '0';
END IF;
END PROCESS;
P3 : PROCESS(dia_ipd)
BEGIN
CASE DATA_WIDTH_A IS
WHEN 1 =>
dia_node <= dia_ipd(11 downto 11);
WHEN 2 =>
dia_node <= (dia_ipd(1), dia_ipd(11));
WHEN 4 =>
dia_node <= dia_ipd(3 downto 0);
WHEN 9 =>
dia_node <= dia_ipd(8 downto 0);
WHEN 18 =>
dia_node <= dia_ipd;
WHEN 36 =>
dia_node <= dia_ipd;
WHEN others =>
NULL;
END CASE;
END PROCESS;
P4 : PROCESS(dib_ipd)
BEGIN
CASE DATA_WIDTH_B IS
WHEN 1 =>
dib_node <= dib_ipd(11 downto 11);
WHEN 2 =>
dib_node <= (dib_ipd(1), dib_ipd(11));
WHEN 4 =>
dib_node <= dib_ipd(3 downto 0);
WHEN 9 =>
dib_node <= dib_ipd(8 downto 0);
WHEN 18 =>
dib_node <= dib_ipd;
WHEN 36 =>
dib_node <= dib_ipd;
WHEN others =>
NULL;
END CASE;
END PROCESS;
diab_node <= (dib_ipd & dia_ipd);
P107 : PROCESS(clka_ipd)
BEGIN
IF (clka_ipd'event and clka_ipd = '1' and clka_ipd'last_value = '0') THEN
IF ((g_reset = '0') or (rsta_ipd = '1')) THEN
clka_valid <= '0';
ELSE
IF (cea_ipd = '1') THEN
IF (csa_en = '1') THEN
clka_valid <= '1', '0' after 0.01 ns;
ELSE
clka_valid <= '0';
END IF;
ELSE
clka_valid <= '0';
END IF;
END IF;
END IF;
END PROCESS;
P108 : PROCESS(clkb_ipd)
BEGIN
IF (clkb_ipd'event and clkb_ipd = '1' and clkb_ipd'last_value = '0') THEN
IF ((g_reset = '0') or (rstb_ipd = '1')) THEN
clkb_valid <= '0';
ELSE
IF (ceb_ipd = '1') THEN
IF (csb_en = '1') THEN
clkb_valid <= '1', '0' after 0.01 ns;
ELSE
clkb_valid <= '0';
END IF;
ELSE
clkb_valid <= '0';
END IF;
END IF;
END IF;
END PROCESS;
clka_valid1 <= clka_valid;
clkb_valid1 <= clkb_valid;
P7 : PROCESS(g_reset, rsta_ipd, rstb_ipd, clka_ipd, clkb_ipd)
BEGIN
IF (g_reset = '0') THEN
dia_reg <= (others => '0');
diab_reg <= (others => '0');
ada_reg <= (others => '0');
wrena_reg <= '0';
rena_reg <= '0';
ELSIF (RESETMODE = "ASYNC") THEN
IF (rsta_ipd = '1') THEN
dia_reg <= (others => '0');
diab_reg <= (others => '0');
ada_reg <= (others => '0');
wrena_reg <= '0';
rena_reg <= '0';
ELSIF (clka_ipd'event and clka_ipd = '1') THEN
IF (cea_ipd = '1') THEN
dia_reg <= dia_node;
diab_reg <= diab_node;
ada_reg <= ada_node;
wrena_reg <= (wrea_ipd and csa_en);
rena_reg <= ((not wrea_ipd) and csa_en);
END IF;
END IF;
ELSIF (RESETMODE = "SYNC") THEN
IF (clka_ipd'event and clka_ipd = '1') THEN
IF (rsta_ipd = '1') THEN
dia_reg <= (others => '0');
diab_reg <= (others => '0');
ada_reg <= (others => '0');
wrena_reg <= '0';
rena_reg <= '0';
ELSIF (cea_ipd = '1') THEN
dia_reg <= dia_node;
diab_reg <= diab_node;
ada_reg <= ada_node;
wrena_reg <= (wrea_ipd and csa_en);
rena_reg <= ((not wrea_ipd) and csa_en);
END IF;
END IF;
END IF;
IF (g_reset = '0') THEN
dib_reg <= (others => '0');
adb_reg <= (others => '0');
wrenb_reg <= '0';
renb_reg <= '0';
ELSIF (RESETMODE = "ASYNC") THEN
IF (rstb_ipd = '1') THEN
dib_reg <= (others => '0');
adb_reg <= (others => '0');
wrenb_reg <= '0';
renb_reg <= '0';
ELSIF (clkb_ipd'event and clkb_ipd = '1') THEN
IF (ceb_ipd = '1') THEN
dib_reg <= dib_node;
adb_reg <= adb_node;
wrenb_reg <= (wreb_ipd and csb_en);
renb_reg <= ((not wreb_ipd) and csb_en);
END IF;
END IF;
ELSIF (RESETMODE = "SYNC") THEN
IF (clkb_ipd'event and clkb_ipd = '1') THEN
IF (rstb_ipd = '1') THEN
dib_reg <= (others => '0');
adb_reg <= (others => '0');
wrenb_reg <= '0';
renb_reg <= '0';
ELSIF (ceb_ipd = '1') THEN
dib_reg <= dib_node;
adb_reg <= adb_node;
wrenb_reg <= (wreb_ipd and csb_en);
renb_reg <= ((not wreb_ipd) and csb_en);
END IF;
END IF;
END IF;
END PROCESS;
-- Warning for collision
PW : PROCESS(ada_reg, adb_reg, wrena_reg, wrenb_reg, clka_valid, clkb_valid, rena_reg,
renb_reg)
VARIABLE WADDR_A_VALID : boolean := TRUE;
VARIABLE WADDR_B_VALID : boolean := TRUE;
VARIABLE ADDR_A : integer := 0;
VARIABLE ADDR_B : integer := 0;
VARIABLE DN_ADDR_A : integer := 0;
VARIABLE UP_ADDR_A : integer := 0;
VARIABLE DN_ADDR_B : integer := 0;
VARIABLE UP_ADDR_B : integer := 0;
BEGIN
WADDR_A_VALID := Valid_Address (ada_reg);
WADDR_B_VALID := Valid_Address (adb_reg);
IF (WADDR_A_VALID = TRUE) THEN
ADDR_A := conv_integer(ada_reg);
END IF;
IF (WADDR_B_VALID = TRUE) THEN
ADDR_B := conv_integer(adb_reg);
END IF;
DN_ADDR_A := (ADDR_A * DATA_WIDTH_A);
UP_ADDR_A := (((ADDR_A + 1) * DATA_WIDTH_A) - 1);
DN_ADDR_B := (ADDR_B * DATA_WIDTH_B);
UP_ADDR_B := (((ADDR_B + 1) * DATA_WIDTH_B) - 1);
IF ((wrena_reg = '1' and clka_valid = '1') and (wrenb_reg = '1' and clkb_valid = '1')) THEN
IF (not((UP_ADDR_B <= DN_ADDR_A) or (DN_ADDR_B >= UP_ADDR_A))) THEN
assert false
report " Write collision! Writing in the same memory location using Port A and Port B will cause the memory content invalid."
severity error;
END IF;
END IF;
-- IF ((wrena_reg = '1' and clka_valid = '1') and (renb_reg = '1' and clkb_valid = '1')) THEN
-- IF (not((UP_ADDR_B <= DN_ADDR_A) or (DN_ADDR_B >= UP_ADDR_A))) THEN
-- assert false
-- report " Write/Read collision! Writing through Port A and reading through Port B from the same memory location may give wrong output."
-- severity warning;
-- END IF;
-- END IF;
-- IF ((rena_reg = '1' and clka_valid = '1') and (wrenb_reg = '1' and clkb_valid = '1')) THEN
-- IF (not((UP_ADDR_A <= DN_ADDR_B) or (DN_ADDR_A >= UP_ADDR_B))) THEN
-- assert false
-- report " Write/Read collision! Writing through Port B and reading through Port A from the same memory location may give wrong output."
-- severity warning;
-- END IF;
-- END IF;
END PROCESS;
-- Writing to the memory
P8 : PROCESS(ada_reg, dia_reg, diab_reg, wrena_reg, dib_reg, adb_reg,
wrenb_reg, clka_valid, clkb_valid)
VARIABLE WADDR_A_VALID : boolean := TRUE;
VARIABLE WADDR_B_VALID : boolean := TRUE;
VARIABLE WADDR_A : integer := 0;
VARIABLE WADDR_B : integer := 0;
VARIABLE dout_node_rbr : std_logic_vector(35 downto 0);
BEGIN
WADDR_A_VALID := Valid_Address (ada_reg);
WADDR_B_VALID := Valid_Address (adb_reg);
IF (WADDR_A_VALID = TRUE) THEN
WADDR_A := conv_integer(ada_reg);
END IF;
IF (WADDR_B_VALID = TRUE) THEN
WADDR_B := conv_integer(adb_reg);
END IF;
IF (DATA_WIDTH_A = 36) THEN
IF (wrena_reg = '1' and clka_valid = '1') THEN
FOR i IN 0 TO (DATA_WIDTH_A - 1) LOOP
dout_node_rbr(i) := MEM((WADDR_A * DATA_WIDTH_A) + i);
END LOOP;
doa_node_rbr <= dout_node_rbr(17 downto 0);
dob_node_rbr <= dout_node_rbr(35 downto 18);
FOR i IN 0 TO 8 LOOP
MEM((WADDR_A * DATA_WIDTH_A) + i) <= diab_reg(i);
END LOOP;
FOR i IN 0 TO 8 LOOP
MEM((WADDR_A * DATA_WIDTH_A) + i + 9) <= diab_reg(i + 9);
END LOOP;
FOR i IN 0 TO 8 LOOP
MEM((WADDR_A * DATA_WIDTH_A) + i + 18) <= diab_reg(i + 18);
END LOOP;
FOR i IN 0 TO 8 LOOP
MEM((WADDR_A * DATA_WIDTH_A) + i + 27) <= diab_reg(i + 27);
END LOOP;
END IF;
ELSE
IF (DATA_WIDTH_A = 18) THEN
IF (wrena_reg = '1' and clka_valid = '1') THEN
FOR i IN 0 TO (DATA_WIDTH_A - 1) LOOP
doa_node_rbr(i) <= MEM((WADDR_A * DATA_WIDTH_A) + (WADDR_A / div_a) + i);
END LOOP;
FOR i IN 0 TO 8 LOOP
MEM((WADDR_A * DATA_WIDTH_A) + i) <= dia_reg(i);
END LOOP;
FOR i IN 0 TO 8 LOOP
MEM((WADDR_A * DATA_WIDTH_A) + i + 9) <= dia_reg(i + 9);
END LOOP;
END IF;
ELSIF (DATA_WIDTH_A = 9) THEN
IF (wrena_reg = '1' and clka_valid = '1') THEN
FOR i IN 0 TO (DATA_WIDTH_A - 1) LOOP
doa_node_rbr(i) <= MEM((WADDR_A * DATA_WIDTH_A) + (WADDR_A / div_a) + i);
END LOOP;
FOR i IN 0 TO (DATA_WIDTH_A - 1) LOOP
MEM((WADDR_A * DATA_WIDTH_A) + i) <= dia_reg(i);
END LOOP;
END IF;
ELSE
IF (wrena_reg = '1' and clka_valid = '1') THEN
FOR i IN 0 TO (DATA_WIDTH_A - 1) LOOP
doa_node_rbr(i) <= MEM((WADDR_A * DATA_WIDTH_A) + (WADDR_A / div_a) + i);
END LOOP;
FOR i IN 0 TO (DATA_WIDTH_A - 1) LOOP
MEM((WADDR_A * DATA_WIDTH_A) + (WADDR_A / div_a) + i) <= dia_reg(i);
END LOOP;
END IF;
END IF;
IF (DATA_WIDTH_B = 18) THEN
IF (wrenb_reg = '1' and clkb_valid = '1') THEN
FOR i IN 0 TO (DATA_WIDTH_B - 1) LOOP
dob_node_rbr(i) <= MEM((WADDR_B * DATA_WIDTH_B) + (WADDR_B / div_b) + i);
END LOOP;
FOR i IN 0 TO 8 LOOP
MEM((WADDR_B * DATA_WIDTH_B) + i) <= dib_reg(i);
END LOOP;
FOR i IN 0 TO 8 LOOP
MEM((WADDR_B * DATA_WIDTH_B) + i + 9) <= dib_reg(i + 9);
END LOOP;
END IF;
ELSIF (DATA_WIDTH_B = 9) THEN
IF (wrenb_reg = '1' and clkb_valid = '1') THEN
FOR i IN 0 TO (DATA_WIDTH_B - 1) LOOP
dob_node_rbr(i) <= MEM((WADDR_B * DATA_WIDTH_B) + (WADDR_B / div_b) + i);
END LOOP;
FOR i IN 0 TO (DATA_WIDTH_B - 1) LOOP
MEM((WADDR_B * DATA_WIDTH_B) + i) <= dib_reg(i);
END LOOP;
END IF;
ELSE
IF (wrenb_reg = '1' and clkb_valid = '1') THEN
FOR i IN 0 TO (DATA_WIDTH_B - 1) LOOP
dob_node_rbr(i) <= MEM((WADDR_B * DATA_WIDTH_B) + (WADDR_B / div_b) + i);
END LOOP;
FOR i IN 0 TO (DATA_WIDTH_B - 1) LOOP
MEM((WADDR_B * DATA_WIDTH_B) + (WADDR_B / div_b) + i) <= dib_reg(i);
END LOOP;
END IF;
END IF;
END IF;
END PROCESS;
P9 : PROCESS(ada_reg, rena_reg, adb_reg, renb_reg, MEM, clka_valid1, clkb_valid1, rsta_sig, rstb_sig, doa_node_rbr, dob_node_rbr)
VARIABLE RADDR_A_VALID : boolean := TRUE;
VARIABLE RADDR_B_VALID : boolean := TRUE;
VARIABLE RADDR_A : integer := 0;
VARIABLE RADDR_B : integer := 0;
VARIABLE dout_node_tr : std_logic_vector(35 downto 0);
VARIABLE dout_node_wt : std_logic_vector(35 downto 0);
BEGIN
RADDR_A_VALID := Valid_Address (ada_reg);
RADDR_B_VALID := Valid_Address (adb_reg);
IF (RADDR_A_VALID = TRUE) THEN
RADDR_A := conv_integer(ada_reg);
END IF;
IF (RADDR_B_VALID = TRUE) THEN
RADDR_B := conv_integer(adb_reg);
END IF;
IF (DATA_WIDTH_B = 36) THEN
IF (rstb_sig = '1') THEN
IF (RESETMODE = "SYNC") THEN
IF (clkb_ipd = '1') THEN
doa_node <= (others => '0');
dob_node <= (others => '0');
END IF;
ELSIF (RESETMODE = "ASYNC") THEN
doa_node <= (others => '0');
dob_node <= (others => '0');
END IF;
ELSIF (clkb_valid1'event and clkb_valid1 = '1') THEN
IF (renb_reg = '1') THEN
FOR i IN 0 TO (DATA_WIDTH_B - 1) LOOP
dout_node_tr(i) := MEM((RADDR_B * DATA_WIDTH_B) + i);
END LOOP;
doa_node <= dout_node_tr(17 downto 0);
dob_node <= dout_node_tr(35 downto 18);
ELSIF (renb_reg = '0') THEN
IF (WRITEMODE_B = "WRITETHROUGH") THEN
FOR i IN 0 TO (DATA_WIDTH_B - 1) LOOP
dout_node_wt(i) := MEM((RADDR_B * DATA_WIDTH_B) + i);
END LOOP;
doa_node <= dout_node_wt(17 downto 0);
dob_node <= dout_node_wt(35 downto 18);
ELSIF (WRITEMODE_B = "READBEFOREWRITE") THEN
doa_node <= doa_node_rbr;
dob_node <= dob_node_rbr;
END IF;
END IF;
END IF;
ELSE
IF (rsta_sig = '1') THEN
IF (RESETMODE = "SYNC") THEN
IF (clka_ipd = '1') THEN
doa_node <= (others => '0');
END IF;
ELSIF (RESETMODE = "ASYNC") THEN
doa_node <= (others => '0');
END IF;
ELSIF (clka_valid1'event and clka_valid1 = '1') THEN
IF (rena_reg = '1') THEN
FOR i IN 0 TO (DATA_WIDTH_A - 1) LOOP
doa_node(i) <= MEM((RADDR_A * DATA_WIDTH_A) + (RADDR_A / div_a) + i);
END LOOP;
ELSIF (rena_reg = '0') THEN
IF (WRITEMODE_A = "WRITETHROUGH") THEN
FOR i IN 0 TO (DATA_WIDTH_A - 1) LOOP
doa_node(i) <= MEM((RADDR_A * DATA_WIDTH_A) + (RADDR_A / div_a) + i);
END LOOP;
ELSIF (WRITEMODE_A = "READBEFOREWRITE") THEN
doa_node <= doa_node_rbr;
END IF;
END IF;
END IF;
IF (rstb_sig = '1') THEN
IF (RESETMODE = "SYNC") THEN
IF (clkb_ipd = '1') THEN
dob_node <= (others => '0');
END IF;
ELSIF (RESETMODE = "ASYNC") THEN
dob_node <= (others => '0');
END IF;
ELSIF (clkb_valid1'event and clkb_valid1 = '1') THEN
IF (renb_reg = '1') THEN
FOR i IN 0 TO (DATA_WIDTH_B - 1) LOOP
dob_node(i) <= MEM((RADDR_B * DATA_WIDTH_B) + (RADDR_B / div_b) + i);
END LOOP;
ELSIF (renb_reg = '0') THEN
IF (WRITEMODE_B = "WRITETHROUGH") THEN
FOR i IN 0 TO (DATA_WIDTH_B - 1) LOOP
dob_node(i) <= MEM((RADDR_B * DATA_WIDTH_B) + (RADDR_B / div_b) + i);
END LOOP;
ELSIF (WRITEMODE_B = "READBEFOREWRITE") THEN
dob_node <= dob_node_rbr;
END IF;
END IF;
END IF;
END IF;
END PROCESS;
P10 : PROCESS(g_reset, rsta_ipd, rstb_ipd, clka_ipd, clkb_ipd)
BEGIN
IF (g_reset = '0') THEN
doa_reg <= (others => '0');
ELSIF (RESETMODE = "ASYNC") THEN
IF (rsta_ipd = '1') THEN
doa_reg <= (others => '0');
ELSIF (clka_ipd'event and clka_ipd = '1') THEN
IF (cea_ipd = '1') THEN
doa_reg <= doa_node;
END IF;
END IF;
ELSIF (RESETMODE = "SYNC") THEN
IF (clka_ipd'event and clka_ipd = '1') THEN
IF (cea_ipd = '1') THEN
IF (rsta_ipd = '1') THEN
doa_reg <= (others => '0');
ELSIF (rsta_ipd = '0') THEN
doa_reg <= doa_node;
END IF;
END IF;
END IF;
END IF;
IF (g_reset = '0') THEN
dob_reg <= (others => '0');
doab_reg <= (others => '0');
ELSIF (RESETMODE = "ASYNC") THEN
IF (rstb_ipd = '1') THEN
dob_reg <= (others => '0');
doab_reg <= (others => '0');
ELSIF (clkb_ipd'event and clkb_ipd = '1') THEN
IF (ceb_ipd = '1') THEN
dob_reg <= dob_node;
doab_reg <= doa_node;
END IF;
END IF;
ELSIF (RESETMODE = "SYNC") THEN
IF (clkb_ipd'event and clkb_ipd = '1') THEN
IF (ceb_ipd = '1') THEN
IF (rstb_ipd = '1') THEN
dob_reg <= (others => '0');
doab_reg <= (others => '0');
ELSIF (rstb_ipd = '0') THEN
dob_reg <= dob_node;
doab_reg <= doa_node;
END IF;
END IF;
END IF;
END IF;
END PROCESS;
P11 : PROCESS(doa_node, dob_node, doa_reg, dob_reg, doab_reg)
BEGIN
IF (REGMODE_A = "OUTREG") THEN
IF (DATA_WIDTH_B = 36) THEN
doa_int <= doab_reg;
ELSE
doa_int <= doa_reg;
END IF;
ELSE
doa_int <= doa_node;
END IF;
IF (REGMODE_B = "OUTREG") THEN
dob_int <= dob_reg;
ELSE
dob_int <= dob_node;
END IF;
END PROCESS;
(doa17, doa16, doa15, doa14, doa13, doa12, doa11, doa10, doa9, doa8, doa7, doa6,
doa5, doa4, doa3, doa2, doa1, doa0) <= doa_int;
(dob17, dob16, dob15, dob14, dob13, dob12, dob11, dob10, dob9, dob8, dob7, dob6,
dob5, dob4, dob3, dob2, dob1, dob0) <= dob_int;
END V;
--
-----cell sp8ka----
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.vital_timing.all;
use ieee.vital_primitives.all;
library ec;
use ec.global.gsrnet;
use ec.global.purnet;
use ec.mem3.all;
-- entity declaration --
ENTITY sp8ka IS
GENERIC (
DATA_WIDTH : Integer := 18;
REGMODE : String := "NOREG";
RESETMODE : String := "ASYNC";
CSDECODE : String := "000";
WRITEMODE : String := "NORMAL";
GSR : String := "ENABLED";
initval_00 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_01 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_02 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_03 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_04 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_05 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_06 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_07 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_08 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_09 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0a : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0b : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0c : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0d : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0e : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0f : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_10 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_11 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_12 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_13 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_14 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_15 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_16 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_17 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_18 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_19 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1a : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1b : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1c : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1d : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1e : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1f : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000");
PORT(
di0, di1, di2, di3, di4, di5, di6, di7, di8 : in std_logic := 'X';
di9, di10, di11, di12, di13, di14, di15, di16, di17 : in std_logic := 'X';
ad0, ad1, ad2, ad3, ad4, ad5, ad6, ad7, ad8 : in std_logic := 'X';
ad9, ad10, ad11, ad12 : in std_logic := 'X';
ce, clk, we, cs0, cs1, cs2, rst : in std_logic := 'X';
do0, do1, do2, do3, do4, do5, do6, do7, do8 : out std_logic := 'X';
do9, do10, do11, do12, do13, do14, do15, do16, do17 : out std_logic := 'X'
);
ATTRIBUTE Vital_Level0 OF sp8ka : ENTITY IS TRUE;
END sp8ka ;
architecture V of sp8ka is
signal lo: std_logic := '0';
signal hi: std_logic := '1';
component dp8ka
GENERIC(
DATA_WIDTH_A : in Integer;
DATA_WIDTH_B : in Integer;
REGMODE_A : in String;
REGMODE_B : in String;
RESETMODE : in String;
CSDECODE_A : in String;
CSDECODE_B : in String;
WRITEMODE_A : in String;
WRITEMODE_B : in String;
GSR : in String;
initval_00 : in string;
initval_01 : in string;
initval_02 : in string;
initval_03 : in string;
initval_04 : in string;
initval_05 : in string;
initval_06 : in string;
initval_07 : in string;
initval_08 : in string;
initval_09 : in string;
initval_0a : in string;
initval_0b : in string;
initval_0c : in string;
initval_0d : in string;
initval_0e : in string;
initval_0f : in string;
initval_10 : in string;
initval_11 : in string;
initval_12 : in string;
initval_13 : in string;
initval_14 : in string;
initval_15 : in string;
initval_16 : in string;
initval_17 : in string;
initval_18 : in string;
initval_19 : in string;
initval_1a : in string;
initval_1b : in string;
initval_1c : in string;
initval_1d : in string;
initval_1e : in string;
initval_1f : in string);
PORT(
dia0, dia1, dia2, dia3, dia4, dia5, dia6, dia7, dia8 : in std_logic;
dia9, dia10, dia11, dia12, dia13, dia14, dia15, dia16, dia17 : in std_logic;
ada0, ada1, ada2, ada3, ada4, ada5, ada6, ada7, ada8 : in std_logic;
ada9, ada10, ada11, ada12 : in std_logic;
cea, clka, wea, csa0, csa1, csa2, rsta : in std_logic;
dib0, dib1, dib2, dib3, dib4, dib5, dib6, dib7, dib8 : in std_logic;
dib9, dib10, dib11, dib12, dib13, dib14, dib15, dib16, dib17 : in std_logic;
adb0, adb1, adb2, adb3, adb4, adb5, adb6, adb7, adb8 : in std_logic;
adb9, adb10, adb11, adb12 : in std_logic;
ceb, clkb, web, csb0, csb1, csb2, rstb : in std_logic;
doa0, doa1, doa2, doa3, doa4, doa5, doa6, doa7, doa8 : out std_logic;
doa9, doa10, doa11, doa12, doa13, doa14, doa15, doa16, doa17 : out std_logic;
dob0, dob1, dob2, dob3, dob4, dob5, dob6, dob7, dob8 : out std_logic;
dob9, dob10, dob11, dob12, dob13, dob14, dob15, dob16, dob17 : out std_logic
);
END COMPONENT;
begin
-- component instantiation statements
dp8ka_inst : dp8ka
generic map (DATA_WIDTH_A => DATA_WIDTH,
DATA_WIDTH_B => DATA_WIDTH,
REGMODE_A => REGMODE,
REGMODE_B => REGMODE,
RESETMODE => RESETMODE,
CSDECODE_A => CSDECODE,
CSDECODE_B => CSDECODE,
WRITEMODE_A => WRITEMODE,
WRITEMODE_B => WRITEMODE,
GSR => GSR,
initval_00 => initval_00,
initval_01 => initval_01,
initval_02 => initval_02,
initval_03 => initval_03,
initval_04 => initval_04,
initval_05 => initval_05,
initval_06 => initval_06,
initval_07 => initval_07,
initval_08 => initval_08,
initval_09 => initval_09,
initval_0a => initval_0a,
initval_0b => initval_0b,
initval_0c => initval_0c,
initval_0d => initval_0d,
initval_0e => initval_0e,
initval_0f => initval_0f,
initval_10 => initval_10,
initval_11 => initval_11,
initval_12 => initval_12,
initval_13 => initval_13,
initval_14 => initval_14,
initval_15 => initval_15,
initval_16 => initval_16,
initval_17 => initval_17,
initval_18 => initval_18,
initval_19 => initval_19,
initval_1a => initval_1a,
initval_1b => initval_1b,
initval_1c => initval_1c,
initval_1d => initval_1d,
initval_1e => initval_1e,
initval_1f => initval_1f)
port map (dia0 => di0, dia1 => di1, dia2 => di2, dia3 => di3,
dia4 => di4, dia5 => di5, dia6 => di6, dia7 => di7, dia8 => di8,
dia9 => di9, dia10 => di10, dia11 => di11, dia12 => di12, dia13 => di13,
dia14 => di14, dia15 => di15, dia16 => di16, dia17 => di17, dib0 => lo,
dib1 => lo, dib2 => lo, dib3 => lo, dib4 => lo, dib5 => lo,
dib6 => lo, dib7 => lo, dib8 => lo, dib9 => lo, dib10 => lo,
dib11 => lo, dib12 => lo, dib13 => lo, dib14 => lo, dib15 => lo,
dib16 => lo, dib17 => lo,
cea => ce, clka => clk, wea => we, csa0 => cs0, csa1 => cs1, csa2 => cs2,
rsta => rst, ada0 => ad0, ada1 => ad1, ada2 => ad2, ada3 => ad3,
ada4 => ad4, ada5 => ad5, ada6 => ad6, ada7 => ad7, ada8 => ad8,
ada9 => ad9, ada10 => ad10, ada11 => ad11, ada12 => ad12,
ceb => lo, clkb => lo, web => lo, csb0 => lo, csb1 => lo, csb2 => lo,
rstb => hi, adb0 => lo, adb1 => lo, adb2 => lo, adb3 => lo,
adb4 => lo, adb5 => lo, adb6 => lo, adb7 => lo, adb8 => lo,
adb9 => lo, adb10 => lo, adb11 => lo, adb12 => lo,
dob0 => open, dob1 => open, dob2 => open, dob3 => open,
dob4 => open, dob5 => open, dob6 => open, dob7 => open, dob8 => open,
dob9 => open, dob10 => open, dob11 => open, dob12 => open, dob13 => open,
dob14 => open, dob15 => open, dob16 => open, dob17 => open, doa0 => do0,
doa1 => do1, doa2 => do2, doa3 => do3, doa4 => do4, doa5 => do5,
doa6 => do6, doa7 => do7, doa8 => do8, doa9 => do9, doa10 => do10,
doa11 => do11, doa12 => do12, doa13 => do13, doa14 => do14, doa15 => do15,
doa16 => do16, doa17 => do17);
end V;
--
-----cell pdp8ka----
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.vital_timing.all;
use ieee.vital_primitives.all;
library ec;
use ec.global.gsrnet;
use ec.global.purnet;
use ec.mem3.all;
-- entity declaration --
ENTITY pdp8ka IS
GENERIC (
DATA_WIDTH_W : Integer := 18;
DATA_WIDTH_R : Integer := 18;
REGMODE : String := "NOREG";
RESETMODE : String := "ASYNC";
CSDECODE_W : String := "000";
CSDECODE_R : String := "000";
GSR : String := "ENABLED";
initval_00 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_01 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_02 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_03 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_04 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_05 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_06 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_07 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_08 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_09 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0a : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0b : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0c : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0d : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0e : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0f : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_10 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_11 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_12 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_13 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_14 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_15 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_16 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_17 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_18 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_19 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1a : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1b : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1c : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1d : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1e : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1f : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000");
PORT(
di0, di1, di2, di3, di4, di5, di6, di7, di8 : in std_logic := 'X';
di9, di10, di11, di12, di13, di14, di15, di16, di17 : in std_logic := 'X';
di18, di19, di20, di21, di22, di23, di24, di25, di26 : in std_logic := 'X';
di27, di28, di29, di30, di31, di32, di33, di34, di35 : in std_logic := 'X';
adw0, adw1, adw2, adw3, adw4, adw5, adw6, adw7, adw8 : in std_logic := 'X';
adw9, adw10, adw11, adw12 : in std_logic := 'X';
cew, clkw, we, csw0, csw1, csw2 : in std_logic := 'X';
adr0, adr1, adr2, adr3, adr4, adr5, adr6, adr7, adr8 : in std_logic := 'X';
adr9, adr10, adr11, adr12 : in std_logic := 'X';
cer, clkr, csr0, csr1, csr2, rst : in std_logic := 'X';
do0, do1, do2, do3, do4, do5, do6, do7, do8 : out std_logic := 'X';
do9, do10, do11, do12, do13, do14, do15, do16, do17 : out std_logic := 'X';
do18, do19, do20, do21, do22, do23, do24, do25, do26 : out std_logic := 'X';
do27, do28, do29, do30, do31, do32, do33, do34, do35 : out std_logic := 'X'
);
ATTRIBUTE Vital_Level0 OF pdp8ka : ENTITY IS TRUE;
END pdp8ka ;
architecture V of pdp8ka is
signal lo: std_logic := '0';
component dp8ka
GENERIC(
DATA_WIDTH_A : in Integer;
DATA_WIDTH_B : in Integer;
REGMODE_A : in String;
REGMODE_B : in String;
RESETMODE : in String;
CSDECODE_A : in String;
CSDECODE_B : in String;
GSR : in String;
initval_00 : in string;
initval_01 : in string;
initval_02 : in string;
initval_03 : in string;
initval_04 : in string;
initval_05 : in string;
initval_06 : in string;
initval_07 : in string;
initval_08 : in string;
initval_09 : in string;
initval_0a : in string;
initval_0b : in string;
initval_0c : in string;
initval_0d : in string;
initval_0e : in string;
initval_0f : in string;
initval_10 : in string;
initval_11 : in string;
initval_12 : in string;
initval_13 : in string;
initval_14 : in string;
initval_15 : in string;
initval_16 : in string;
initval_17 : in string;
initval_18 : in string;
initval_19 : in string;
initval_1a : in string;
initval_1b : in string;
initval_1c : in string;
initval_1d : in string;
initval_1e : in string;
initval_1f : in string);
PORT(
dia0, dia1, dia2, dia3, dia4, dia5, dia6, dia7, dia8 : in std_logic;
dia9, dia10, dia11, dia12, dia13, dia14, dia15, dia16, dia17 : in std_logic;
ada0, ada1, ada2, ada3, ada4, ada5, ada6, ada7, ada8 : in std_logic;
ada9, ada10, ada11, ada12 : in std_logic;
cea, clka, wea, csa0, csa1, csa2, rsta : in std_logic;
dib0, dib1, dib2, dib3, dib4, dib5, dib6, dib7, dib8 : in std_logic;
dib9, dib10, dib11, dib12, dib13, dib14, dib15, dib16, dib17 : in std_logic;
adb0, adb1, adb2, adb3, adb4, adb5, adb6, adb7, adb8 : in std_logic;
adb9, adb10, adb11, adb12 : in std_logic;
ceb, clkb, web, csb0, csb1, csb2, rstb : in std_logic;
doa0, doa1, doa2, doa3, doa4, doa5, doa6, doa7, doa8 : out std_logic;
doa9, doa10, doa11, doa12, doa13, doa14, doa15, doa16, doa17 : out std_logic;
dob0, dob1, dob2, dob3, dob4, dob5, dob6, dob7, dob8 : out std_logic;
dob9, dob10, dob11, dob12, dob13, dob14, dob15, dob16, dob17 : out std_logic
);
END COMPONENT;
begin
-- component instantiation statements
dp8ka_inst : dp8ka
generic map (DATA_WIDTH_A => DATA_WIDTH_W,
DATA_WIDTH_B => DATA_WIDTH_R,
REGMODE_A => REGMODE,
REGMODE_B => REGMODE,
RESETMODE => RESETMODE,
CSDECODE_A => CSDECODE_W,
CSDECODE_B => CSDECODE_R,
GSR => GSR,
initval_00 => initval_00,
initval_01 => initval_01,
initval_02 => initval_02,
initval_03 => initval_03,
initval_04 => initval_04,
initval_05 => initval_05,
initval_06 => initval_06,
initval_07 => initval_07,
initval_08 => initval_08,
initval_09 => initval_09,
initval_0a => initval_0a,
initval_0b => initval_0b,
initval_0c => initval_0c,
initval_0d => initval_0d,
initval_0e => initval_0e,
initval_0f => initval_0f,
initval_10 => initval_10,
initval_11 => initval_11,
initval_12 => initval_12,
initval_13 => initval_13,
initval_14 => initval_14,
initval_15 => initval_15,
initval_16 => initval_16,
initval_17 => initval_17,
initval_18 => initval_18,
initval_19 => initval_19,
initval_1a => initval_1a,
initval_1b => initval_1b,
initval_1c => initval_1c,
initval_1d => initval_1d,
initval_1e => initval_1e,
initval_1f => initval_1f)
port map (dia0 => di0, dia1 => di1, dia2 => di2, dia3 => di3,
dia4 => di4, dia5 => di5, dia6 => di6, dia7 => di7, dia8 => di8,
dia9 => di9, dia10 => di10, dia11 => di11, dia12 => di12, dia13 => di13,
dia14 => di14, dia15 => di15, dia16 => di16, dia17 => di17, dib0 => di18,
dib1 => di19, dib2 => di20, dib3 => di21, dib4 => di22, dib5 => di23,
dib6 => di24, dib7 => di25, dib8 => di26, dib9 => di27, dib10 => di28,
dib11 => di29, dib12 => di30, dib13 => di31, dib14 => di32, dib15 => di33,
dib16 => di34, dib17 => di35,
cea => cew, clka => clkw, wea => we, csa0 => csw0, csa1 => csw1, csa2 => csw2,
rsta => rst, ada0 => adw0, ada1 => adw1, ada2 => adw2, ada3 => adw3,
ada4 => adw4, ada5 => adw5, ada6 => adw6, ada7 => adw7, ada8 => adw8,
ada9 => adw9, ada10 => adw10, ada11 => adw11, ada12 => adw12,
ceb => cer, clkb => clkr, web => lo, csb0 => csr0, csb1 => csr1, csb2 => csr2,
rstb => rst, adb0 => adr0, adb1 => adr1, adb2 => adr2, adb3 => adr3,
adb4 => adr4, adb5 => adr5, adb6 => adr6, adb7 => adr7, adb8 => adr8,
adb9 => adr9, adb10 => adr10, adb11 => adr11, adb12 => adr12,
dob0 => do0, dob1 => do1, dob2 => do2, dob3 => do3,
dob4 => do4, dob5 => do5, dob6 => do6, dob7 => do7, dob8 => do8,
dob9 => do9, dob10 => do10, dob11 => do11, dob12 => do12, dob13 => do13,
dob14 => do14, dob15 => do15, dob16 => do16, dob17 => do17, doa0 => do18,
doa1 => do19, doa2 => do20, doa3 => do21, doa4 => do22, doa5 => do23,
doa6 => do24, doa7 => do25, doa8 => do26, doa9 => do27, doa10 => do28,
doa11 => do29, doa12 => do30, doa13 => do31, doa14 => do32, doa15 => do33,
doa16 => do34, doa17 => do35);
end V;
| mit | 33925b368f0f4884dc2424e17af438b7 | 0.566161 | 3.595726 | false | false | false | false |
impedimentToProgress/UCI-BlueChip | AttackFiles/Attacks/privEsc/lib/gleichmann/multiio/MultiIO.vhd | 2 | 8,952 | --------------------------------------------------------------------
-- Package: MultiIO
-- File: MultiIO.vhd
-- Author: Thomas Ameseder, Gleichmann Electronics
-- Based on an orginal version by [email protected]
--
-- Description: APB Multiple digital I/O Types and Components
--------------------------------------------------------------------
-- Functionality:
-- 8 LEDs, active low or high, r/w
-- dual 7Segment, active low or high, w only
-- 8 DIL Switches, active low or high, r only
-- 8 Buttons, active low or high, r only, with IRQ enables
--------------------------------------------------------------------
library ieee;
use IEEE.STD_LOGIC_1164.all;
library grlib;
use grlib.amba.all;
package MultiIO is
-- maximum number of switches and LEDs
-- specific number that is used can be defined via a generic
constant N_SWITCHMAX : integer := 8;
constant N_LEDMAX : integer := 8;
constant N_BUTTONS : integer := 12; -- number of push-buttons
-- data width of the words for the codec configuration interface
constant N_CODECBITS : integer := 16;
-- data width of the words for the i2s digital samples
constant N_CODECI2SBITS : integer := 16;
-- the number of register bits that are assigned to the LCD
-- the enable control bit is set automatically
-- this constant should comprise the number of data bits as well
-- as the RW and RS control bits
constant N_LCDBITS : integer := 10;
-- number of bits to hold information for the (single/dual)
-- seven segment display;
constant N_SEVSEGBITS : integer := 16;
-- number of expansion connector i/o bits
constant N_EXPBITS : integer := 40;
-- number of high-speed connector bits per connector
constant N_HSCBITS : integer := 4;
-- number of childboard3 connector i/o bits
constant N_CB3 : integer := 32;
type asciichar_vect is array (16#30# to 16#46#) of character;
-- excerpt of the ASCII chart
constant ascii2char : asciichar_vect :=
-- -------------------------------------------
-- | 30 31 32 33 34 35 36 37 |
-- -------------------------------------------
('0', '1', '2', '3', '4', '5', '6', '7',
-- -------------------------------------------
-- | 38 39 3A 3B 3C 3D 3E 3F |
-- -------------------------------------------
'8', '9', ':', ';', '<', '=', '>', '?',
-- -------------------------------------------
-- | 40 41 42 43 44 45 46 |
-- -------------------------------------------
'@', 'A', 'B', 'C', 'D', 'E', 'F');
---------------------------------------------------------------------------------------
-- AUDIO CODEC
---------------------------------------------------------------------------------------
subtype tReg is std_ulogic_vector(N_CODECBITS-1 downto 0);
type tRegMap is array(10 downto 0) of tReg;
subtype tRegData is std_ulogic_vector(8 downto 0);
subtype tRegAddr is std_ulogic_vector(6 downto 0);
-- ADDRESS
constant cAddrLLI : tRegAddr := "0000000"; -- Left line input channel volume control
constant cAddrRLI : tRegAddr := "0000001"; -- Right line input channel volume control
constant cAddrLCH : tRegAddr := "0000010"; -- Left channel headphone volume control
constant cAddrRCH : tRegAddr := "0000011"; -- Right channel headphone volume control
constant cAddrAAP : tRegAddr := "0000100"; -- Analog audio path control
constant cAddrDAP : tRegAddr := "0000101"; -- Digital audio path control
constant cAddrPDC : tRegAddr := "0000110"; -- Power down control
constant cAddrDAI : tRegAddr := "0000111"; -- Digital audio interface format
constant cAddrSRC : tRegAddr := "0001000"; -- Sample rate control
constant cAddrDIA : tRegAddr := "0001001"; -- Digital interface activation
constant cAddrReset : tRegAddr := "0001111"; -- Reset register
-- Data
constant cDataLLI : tRegData := "100011111";
constant cDataRLI : tRegData := "100011111";
constant cDataLCH : tRegData := "011111111";
constant cDataRCH : tRegData := "011111111";
constant cDataAAP : tRegData := "000011010";
constant cDataDAP : tRegData := "000000000";
constant cDataPDC : tRegData := "000001010";
constant cDataDAI : tRegData := "000000010";
constant cDataSRC : tRegData := "010000000";
constant cDataDIA : tRegData := "000000001";
constant cdataInit : tRegData := "000000000";
-- Register
constant cRegLLI : tReg := cAddrLLI & cDataLLI;
constant cRegRLI : tReg := cAddrRLI & cDataRLI;
constant cRegLCH : tReg := cAddrLCH & cDataLCH;
constant cRegRCH : tReg := cAddrRCH & cDataRCH;
constant cRegAAP : tReg := cAddrAAP & cDataAAP;
constant cRegDAP : tReg := cAddrDAP & cDataDAP;
constant cRegPDC : tReg := cAddrPDC & cDataPDC;
constant cRegDAI : tReg := cAddrDAI & cDataDAI;
constant cRegSRC : tReg := cAddrSRC & cDataSRC;
constant cRegDIA : tReg := cAddrDIA & cDataDIA;
constant cRegReset : tReg := CAddrReset & cdataInit;
-- Register Map
constant cregmap : tRegMap := (
0 => cRegLLI,
1 => cRegRLI,
2 => cRegLCH,
3 => cRegRCH,
4 => cRegAAP,
5 => cRegDAP,
6 => cRegPDC,
7 => cRegDAI,
8 => cRegSRC,
9 => cRegDIA,
10 => cRegReset
);
---------------------------------------------------------------------------------------
type MultiIO_in_type is
record
switch_in : std_logic_vector(N_SWITCHMAX-1 downto 0); -- 8 DIL Switches
-- row input from the key matrix
row_in : std_logic_vector(3 downto 0);
-- expansion connector input bits
exp_in : std_logic_vector(N_EXPBITS/2-1 downto 0);
hsc_in : std_logic_vector(N_HSCBITS-1 downto 0);
-- childboard3 connector input bits
cb3_in : std_logic_vector(N_CB3-1 downto 0);
end record;
type MultiIO_out_type is
record
-- signals for the 7 segment display
-- data bits 0 to 7 of the LCD
-- LED signals for the Hpe_midi
led_a_out : std_logic;
led_b_out : std_logic;
led_c_out : std_logic;
led_d_out : std_logic;
led_e_out : std_logic;
led_f_out : std_logic;
led_g_out : std_logic;
led_dp_out : std_logic;
-- common anode for enabling left and/or right digit
-- data bit 7 for the LCD
led_ca_out : std_logic_vector(1 downto 0);
-- enable output to LED's for the Hpe_midi
led_enable : std_logic;
-- LCD-only control signals
lcd_regsel : std_logic;
lcd_rw : std_logic;
lcd_enable : std_logic;
-- LED register for all boards except the Hpe_midi
led_out : std_logic_vector(N_LEDMAX-1 downto 0); -- 8 LEDs
-- column output to the key matrix
column_out : std_logic_vector(2 downto 0);
-- signals for the SPI audio codec
codec_mode : std_ulogic;
codec_mclk : std_ulogic;
codec_sclk : std_ulogic;
codec_sdin : std_ulogic;
codec_cs : std_ulogic;
codec_din : std_ulogic; -- I2S format serial data input to the sigma-delta stereo DAC
codec_bclk : std_ulogic; -- I2S serial-bit clock
-- codec_dout : in std_ulogic; -- I2S format serial data output from the sigma-delta stereo ADC
codec_lrcin : std_ulogic; -- I2S DAC-word clock signal
codec_lrcout : std_ulogic; -- I2S ADC-word clock signal
-- expansion connector output bits
exp_out : std_logic_vector(N_EXPBITS/2-1 downto 0);
hsc_out : std_logic_vector(N_HSCBITS-1 downto 0);
-- childboard3 connector output bits
-- cb3_out : std_logic_vector(N_CB3-1 downto 0);
end record;
component MultiIO_APB
generic
(
hpe_version : integer := 0; -- adapt multiplexing for different boards
pindex : integer := 0; -- Leon-Index
paddr : integer := 0; -- Leon-Address
pmask : integer := 16#FFF#; -- Leon-Mask
pirq : integer := 0; -- Leon-IRQ
clk_freq_in : integer; -- Leons clock to calculate timings
led7act : std_logic := '0'; -- active level for 7Segment
ledact : std_logic := '0'; -- active level for LED's
switchact : std_logic := '1'; -- active level for LED's
buttonact : std_logic := '1'; -- active level for LED's
n_switches : integer := 8; -- number of switches
n_leds : integer := 8 -- number of LEDs
);
port (
rst_n : in std_ulogic; -- global Reset, active low
clk : in std_ulogic; -- global Clock
apbi : in apb_slv_in_type; -- APB-Input
apbo : out apb_slv_out_type; -- APB-Output
MultiIO_in : in MultiIO_in_type; -- MultIO-Inputs
MultiIO_out : out MultiIO_out_type -- MultiIO-Outputs
);
end component;
end package;
| mit | 3e7127f1759ee3f5ef25dd6d2a8acf94 | 0.561327 | 3.810983 | false | false | false | false |
impedimentToProgress/UCI-BlueChip | AttackFiles/Attacks/privEsc/lib/techmap/axcelerator/pads_axcelerator.vhd | 2 | 10,032 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Package: pad_actel_gen
-- File: pad_actel_gen.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: Actel pads wrappers
------------------------------------------------------------------------------
-- pragma translate_off
library axcelerator;
use axcelerator.inbuf;
use axcelerator.inbuf_pci;
-- pragma translate_on
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
entity axcel_inpad is
generic (level : integer := 0; voltage : integer := 0);
port (pad : in std_ulogic; o : out std_ulogic);
end;
architecture rtl of axcel_inpad is
component inbuf port(pad :in std_logic; y : out std_logic); end component;
component inbuf_pci port(pad :in std_logic; y : out std_logic); end component;
attribute syn_tpd11 : string;
attribute syn_tpd11 of inbuf_pci : component is "pad -> y = 2.0";
begin
pci0 : if level = pci33 generate
ip : inbuf_pci port map (pad => pad, y => o);
end generate;
gen0 : if level /= pci33 generate
ip : inbuf port map (pad => pad, y => o);
end generate;
end;
-- pragma translate_off
library axcelerator;
use axcelerator.bibuf;
use axcelerator.bibuf_pci;
-- pragma translate_on
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
entity axcel_iopad is
generic (level : integer := 0; slew : integer := 0;
voltage : integer := 0; strength : integer := 0);
port (pad : inout std_ulogic; i, en : in std_ulogic; o : out std_ulogic);
end ;
architecture rtl of axcel_iopad is
component bibuf port(
d, e : in std_logic; pad : inout std_logic; y : out std_logic);
end component;
component bibuf_pci port(
d, e : in std_logic; pad : inout std_logic; y : out std_logic);
end component;
attribute syn_tpd12 : string;
attribute syn_tpd12 of bibuf_pci : component is "pad -> y = 2.0";
begin
pci0 : if level = pci33 generate
op : bibuf_pci port map (d => i, e => en, pad => pad, y => o);
end generate;
gen0 : if level /= pci33 generate
op : bibuf port map (d => i, e => en, pad => pad, y => o);
end generate;
end;
-- pragma translate_off
library axcelerator;
use axcelerator.bibuf;
use axcelerator.bibuf_pci;
-- pragma translate_on
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
entity axcel_iodpad is
generic (level : integer := 0; slew : integer := 0;
voltage : integer := 0; strength : integer := 0);
port (pad : inout std_ulogic; i, en : in std_ulogic; o : out std_ulogic);
end ;
architecture rtl of axcel_iodpad is
component bibuf port(
d, e : in std_logic; pad : inout std_logic; y : out std_logic);
end component;
component bibuf_pci port(
d, e : in std_logic; pad : inout std_logic; y : out std_logic);
end component;
attribute syn_tpd12 : string;
attribute syn_tpd12 of bibuf_pci : component is "pad -> y = 2.0";
signal gnd : std_ulogic;
begin
gnd <= '0';
pci0 : if level = pci33 generate
op : bibuf_pci port map (d => gnd, e => en, pad => pad, y => o);
end generate;
gen0 : if level /= pci33 generate
op : bibuf port map (d => gnd, e => en, pad => pad, y => o);
end generate;
end;
-- pragma translate_off
library axcelerator;
use axcelerator.outbuf;
use axcelerator.outbuf_f_8;
use axcelerator.outbuf_f_12;
use axcelerator.outbuf_f_16;
use axcelerator.outbuf_f_24;
use axcelerator.outbuf_pci;
-- pragma translate_on
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
entity axcel_outpad is
generic (level : integer := 0; slew : integer := 0;
voltage : integer := 0; strength : integer := 0);
port (pad : out std_ulogic; i : in std_ulogic);
end ;
architecture rtl of axcel_outpad is
component outbuf port(d : in std_logic; pad : out std_logic); end component;
component outbuf_f_8 port(d : in std_logic; pad : out std_logic); end component;
component outbuf_f_12 port(d : in std_logic; pad : out std_logic); end component;
component outbuf_f_16 port(d : in std_logic; pad : out std_logic); end component;
component outbuf_f_24 port(d : in std_logic; pad : out std_logic); end component;
component outbuf_pci port(d : in std_logic; pad : out std_logic); end component;
attribute syn_tpd13 : string;
attribute syn_tpd13 of outbuf_pci : component is "d -> pad = 2.0";
begin
pci0 : if level = pci33 generate
op : outbuf_pci port map (d => i, pad => pad);
end generate;
gen0 : if level /= pci33 generate
x0 : if slew = 0 generate
op : outbuf port map (d => i, pad => pad);
end generate;
x1 : if slew = 1 generate
f0 : if (strength = 0) generate
op : outbuf port map (d => i, pad => pad);
end generate;
f8 : if (strength > 0) and (strength <= 8) generate
op : outbuf_f_8 port map (d => i, pad => pad);
end generate;
f12 : if (strength > 8) and (strength <= 12) generate
op : outbuf_f_12 port map (d => i, pad => pad);
end generate;
f16 : if (strength > 12) and (strength <= 16) generate
op : outbuf_f_16 port map (d => i, pad => pad);
end generate;
f24 : if (strength > 16) generate
op : outbuf_f_24 port map (d => i, pad => pad);
end generate;
end generate;
end generate;
end;
-- pragma translate_off
library axcelerator;
use axcelerator.tribuff;
use axcelerator.tribuff_pci;
-- pragma translate_on
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
entity axcel_odpad is
generic (level : integer := 0; slew : integer := 0;
voltage : integer := 0; strength : integer := 0);
port (pad : out std_ulogic; i : in std_ulogic);
end ;
architecture rtl of axcel_odpad is
component tribuff port(d, e : in std_logic; pad : out std_logic); end component;
component tribuff_pci port(d, e : in std_logic; pad : out std_logic); end component;
attribute syn_tpd14 : string;
attribute syn_tpd14 of tribuff_pci : component is "d,e -> pad = 2.0";
signal gnd : std_ulogic;
begin
gnd <= '0';
pci0 : if level = pci33 generate
op : tribuff_pci port map (d => gnd, e => i, pad => pad);
end generate;
gen0 : if level /= pci33 generate
op : tribuff port map (d => gnd, e => i, pad => pad);
end generate;
end;
-- pragma translate_off
library axcelerator;
use axcelerator.tribuff;
use axcelerator.tribuff_pci;
-- pragma translate_on
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
entity axcel_toutpad is
generic (level : integer := 0; slew : integer := 0;
voltage : integer := 0; strength : integer := 0);
port (pad : out std_ulogic; i, en : in std_ulogic);
end ;
architecture rtl of axcel_toutpad is
component tribuff port(d, e : in std_logic; pad : out std_logic); end component;
component tribuff_pci port(d, e : in std_logic; pad : out std_logic); end component;
attribute syn_tpd14 : string;
attribute syn_tpd14 of tribuff_pci : component is "d,e -> pad = 2.0";
begin
pci0 : if level = pci33 generate
op : tribuff_pci port map (d => i, e => en, pad => pad);
end generate;
gen0 : if level /= pci33 generate
op : tribuff port map (d => i, e => en, pad => pad);
end generate;
end;
-- pragma translate_off
library axcelerator;
use axcelerator.hclkbuf;
use axcelerator.hclkbuf_pci;
-- pragma translate_on
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
entity axcel_clkpad is
generic (level : integer := 0; voltage : integer := 0);
port (pad : in std_ulogic; o : out std_ulogic);
end;
architecture rtl of axcel_clkpad is
component hclkbuf
port( pad : in std_logic; y : out std_logic); end component;
component hclkbuf_pci
port( pad : in std_logic; y : out std_logic); end component;
begin
pci0 : if level = pci33 generate
cp : hclkbuf_pci port map (pad => pad, y => o);
end generate;
gen0 : if level /= pci33 generate
cp : hclkbuf port map (pad => pad, y => o);
end generate;
end;
-- pragma translate_off
library axcelerator;
use axcelerator.inbuf_lvds;
-- pragma translate_on
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
entity axcel_inpad_ds is
generic (level : integer := lvds; voltage : integer := x33v);
port (padp, padn : in std_ulogic; o : out std_ulogic);
end;
architecture rtl of axcel_inpad_ds is
component inbuf_lvds port(Y : out std_logic; PADP : in std_logic; PADN : in std_logic); end component;
begin
u0: inbuf_lvds port map (y => o, padp => padp, padn => padn);
end;
-- pragma translate_off
library axcelerator;
use axcelerator.outbuf_lvds;
-- pragma translate_on
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
entity axcel_outpad_ds is
generic (level : integer := lvds; voltage : integer := x33v);
port (padp, padn : out std_ulogic; i : in std_ulogic);
end;
architecture rtl of axcel_outpad_ds is
component outbuf_lvds port(D : in std_logic; PADP : out std_logic; PADN : out std_logic); end component;
begin
u0 : outbuf_lvds port map (d => i, padp => padp, padn => padn);
end;
| mit | b4cbcdf520ae86b04acd5d83a33b5746 | 0.656898 | 3.337325 | false | false | false | false |
impedimentToProgress/UCI-BlueChip | AttackFiles/Attacks/privEsc/lib/gaisler/misc/grgpio.vhd | 2 | 8,231 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: gpio
-- File: gpio.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: Scalable general-purpose I/O port
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
library gaisler;
use gaisler.misc.all;
--pragma translate_off
use std.textio.all;
--pragma translate_on
entity grgpio is
generic (
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#fff#;
imask : integer := 16#0000#;
nbits : integer := 16; -- GPIO bits
oepol : integer := 0; -- Output enable polarity
syncrst : integer := 0; -- Only synchronous reset
bypass : integer := 16#0000#;
scantest : integer := 0;
bpdir : integer := 16#0000#
);
port (
rst : in std_ulogic;
clk : in std_ulogic;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
gpioi : in gpio_in_type;
gpioo : out gpio_out_type
);
end;
architecture rtl of grgpio is
constant REVISION : integer := 0;
constant PIMASK : std_logic_vector(31 downto 0) := '0' & conv_std_logic_vector(imask, 31);
constant BPMASK : std_logic_vector(31 downto 0) := conv_std_logic_vector(bypass, 32);
constant BPDIRM : std_logic_vector(31 downto 0) := conv_std_logic_vector(bpdir, 32);
constant pconfig : apb_config_type := (
0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_GPIO, 0, REVISION, 0),
1 => apb_iobar(paddr, pmask));
type registers is record
din1 : std_logic_vector(nbits-1 downto 0);
din2 : std_logic_vector(nbits-1 downto 0);
dout : std_logic_vector(nbits-1 downto 0);
imask : std_logic_vector(nbits-1 downto 0);
level : std_logic_vector(nbits-1 downto 0);
edge : std_logic_vector(nbits-1 downto 0);
ilat : std_logic_vector(nbits-1 downto 0);
dir : std_logic_vector(nbits-1 downto 0);
bypass : std_logic_vector(nbits-1 downto 0);
end record;
signal r, rin : registers;
signal arst : std_ulogic;
begin
arst <= apbi.testrst when (scantest = 1) and (apbi.testen = '1') else rst;
comb : process(rst, r, apbi, gpioi)
variable readdata, tmp2, dout, dir, pval, din : std_logic_vector(31 downto 0);
variable v : registers;
variable xirq : std_logic_vector(NAHBIRQ-1 downto 0);
begin
din := (others => '0');
din(nbits-1 downto 0) := gpioi.din(nbits-1 downto 0);
v := r; v.din2 := r.din1; v.din1 := din(nbits-1 downto 0);
v.ilat := r.din2; dout := (others => '0'); dir := (others => '0');
dir(nbits-1 downto 0) := r.dir(nbits-1 downto 0);
if (syncrst = 1) and (rst = '0') then
if oepol = 0 then dir(nbits-1 downto 0) := (others => '1');
else dir(nbits-1 downto 0) := (others => '0'); end if;
end if;
dout(nbits-1 downto 0) := r.dout(nbits-1 downto 0);
-- read registers
readdata := (others => '0');
case apbi.paddr(4 downto 2) is
when "000" => readdata(nbits-1 downto 0) := r.din2;
when "001" => readdata(nbits-1 downto 0) := r.dout;
when "010" =>
if oepol = 0 then readdata(nbits-1 downto 0) := not r.dir;
else readdata(nbits-1 downto 0) := r.dir; end if;
when "011" =>
if (imask /= 0) then
readdata(nbits-1 downto 0) :=
r.imask(nbits-1 downto 0) and PIMASK(nbits-1 downto 0);
end if;
when "100" =>
if (imask /= 0) then
readdata(nbits-1 downto 0) :=
r.level(nbits-1 downto 0) and PIMASK(nbits-1 downto 0);
end if;
when "101" =>
if (imask /= 0) then
readdata(nbits-1 downto 0) :=
r.edge(nbits-1 downto 0) and PIMASK(nbits-1 downto 0);
end if;
when "110" =>
if (bypass /= 0) then
readdata(nbits-1 downto 0) :=
r.bypass(nbits-1 downto 0) and BPMASK(nbits-1 downto 0);
end if;
when others =>
end case;
-- write registers
if (apbi.psel(pindex) and apbi.penable and apbi.pwrite) = '1' then
case apbi.paddr(4 downto 2) is
when "000" => null;
when "001" => v.dout := apbi.pwdata(nbits-1 downto 0);
when "010" =>
if oepol = 0 then v.dir := not apbi.pwdata(nbits-1 downto 0);
else v.dir := apbi.pwdata(nbits-1 downto 0); end if;
when "011" =>
if (imask /= 0) then
v.imask := apbi.pwdata(nbits-1 downto 0) and PIMASK(nbits-1 downto 0);
end if;
when "100" =>
if (imask /= 0) then
v.level := apbi.pwdata(nbits-1 downto 0) and PIMASK(nbits-1 downto 0);
end if;
when "101" =>
if (imask /= 0) then
v.edge := apbi.pwdata(nbits-1 downto 0) and PIMASK(nbits-1 downto 0);
end if;
when "110" =>
if (bypass /= 0) then
v.bypass := apbi.pwdata(nbits-1 downto 0) and BPMASK(nbits-1 downto 0);
end if;
when others =>
end case;
end if;
-- interrupt filtering and routing
xirq := (others => '0'); tmp2 := (others => '0');
if (imask /= 0) then
tmp2(nbits-1 downto 0) := r.din2;
for i in 0 to nbits-1 loop
if (PIMASK(i) and r.imask(i)) = '1' then
if r.edge(i) = '1' then
if r.level(i) = '1' then tmp2(i) := r.din2(i) and not r.ilat(i);
else tmp2(i) := not r.din2(i) and r.ilat(i); end if;
else tmp2(i) := r.din2(i) xor not r.level(i); end if;
else
tmp2(i) := '0';
end if;
end loop;
for i in 0 to nbits-1 loop
if i > NAHBIRQ-1 then
exit;
end if;
xirq(i) := tmp2(i);
end loop;
end if;
-- drive filtered inputs on the output record
pval := (others => '0');
pval(nbits-1 downto 0) := r.din2;
-- Drive output with gpioi.sig_in for bypassed registers
if bypass /= 0 then
for i in 0 to nbits-1 loop
if r.bypass(i) = '1' then
dout(i) := gpioi.sig_in(i);
end if;
end loop;
end if;
-- Drive output with gpioi.sig_in for bypassed registers
if bpdir /= 0 then
for i in 0 to nbits-1 loop
if (BPDIRM(i) and gpioi.sig_en(i)) = '1' then
dout(i) := gpioi.sig_in(i);
if oepol = 0 then dir(i) := '0'; else dir(i) := '1'; end if;
end if;
end loop;
end if;
-- reset operation
if rst = '0' then
v.imask := (others => '0'); v.bypass := (others => '0');
if oepol = 1 then v.dir := (others => '0');
else v.dir := (others => '1'); end if;
v.dout := (others => '0');
end if;
rin <= v;
apbo.prdata <= readdata; -- drive apb read bus
apbo.pirq <= xirq;
gpioo.dout <= dout;
gpioo.oen <= dir;
gpioo.val <= pval;
-- non filtered input
gpioo.sig_out <= din;
end process;
apbo.pindex <= pindex;
apbo.pconfig <= pconfig;
-- registers
regs : process(clk, arst)
begin
if rising_edge(clk) then r <= rin; end if;
if (syncrst = 0 ) and (arst = '0') then
if oepol = 1 then r.dir <= (others => '0');
else r.dir <= (others => '1'); end if;
end if;
end process;
-- boot message
-- pragma translate_off
bootmsg : report_version
generic map ("grgpio" & tost(pindex) &
": " & tost(nbits) & "-bit GPIO Unit rev " & tost(REVISION));
-- pragma translate_on
end;
| mit | 7c17d2bb1a1cbbf81330be15bb991ac9 | 0.569797 | 3.284517 | false | false | false | false |
impedimentToProgress/UCI-BlueChip | AttackFiles/Attacks/privEsc/lib/tech/axcelerator/components/axcelerator_components_small.vhd | 2 | 12,257 | ----------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2004 GAISLER RESEARCH
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- See the file COPYING for the full details of the license.
--
-----------------------------------------------------------------------------
-- Package: components
-- File: components.vhd
-- Author: Jiri Gaisler, Gaisler Research
-- Description: Simple Actel RAM and pad component declarations
-----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
package components is
-- Axcellerator rams
component RAM64K36
port(
WRAD0, WRAD1, WRAD2, WRAD3, WRAD4, WRAD5, WRAD6, WRAD7, WRAD8, WRAD9, WRAD10,
WRAD11, WRAD12, WRAD13, WRAD14, WRAD15, WD0, WD1, WD2, WD3, WD4, WD5, WD6,
WD7, WD8, WD9, WD10, WD11, WD12, WD13, WD14, WD15, WD16, WD17, WD18, WD19,
WD20, WD21, WD22, WD23, WD24, WD25, WD26, WD27, WD28, WD29, WD30, WD31, WD32,
WD33, WD34, WD35, WEN, DEPTH0, DEPTH1, DEPTH2, DEPTH3, WW0, WW1, WW2, WCLK,
RDAD0, RDAD1, RDAD2, RDAD3, RDAD4, RDAD5, RDAD6, RDAD7, RDAD8, RDAD9, RDAD10,
RDAD11, RDAD12, RDAD13, RDAD14, RDAD15, REN, RW0, RW1, RW2, RCLK : in std_logic;
RD0, RD1, RD2, RD3, RD4, RD5, RD6, RD7, RD8, RD9, RD10, RD11, RD12, RD13,
RD14, RD15, RD16, RD17, RD18, RD19, RD20, RD21, RD22, RD23, RD24, RD25, RD26,
RD27, RD28, RD29, RD30, RD31, RD32, RD33, RD34, RD35 : out std_logic);
end component;
attribute syn_black_box : boolean;
attribute syn_black_box of RAM64K36 : component is true;
attribute syn_tco1 : string;
attribute syn_tco2 : string;
attribute syn_tco1 of RAM64K36 : component is
"RCLK->RD0,RD1,RD2,RD3,RD4,RD5,RD6,RD7,RD8,RD9,RD10,RD11,RD12,RD13,RD14,RD15,RD16,RD17,RD18,RD19,RD20,RD21,RD22,RD23,RD24,RD25,RD26,RD27,RD28,RD29,RD30,RD31,RD32,RD33,RD34,RD35 = 4.0";
-- Buffers
component inbuf_lvds port(Y : out std_logic; PADP : in std_logic; PADN : in std_logic); end component;
component outbuf_lvds port(D : in std_logic; PADP : out std_logic; PADN : out std_logic); end component;
component hclkbuf
port( pad : in std_logic; y : out std_logic); end component;
component clkbuf port(pad : in std_logic; y : out std_logic); end component;
component inbuf port(pad :in std_logic; y : out std_logic); end component;
component bibuf port(
d, e : in std_logic; pad : inout std_logic; y : out std_logic);
end component;
component outbuf port(d : in std_logic; pad : out std_logic); end component;
component outbuf_f_8 port(d : in std_logic; pad : out std_logic); end component;
component outbuf_f_12 port(d : in std_logic; pad : out std_logic); end component;
component outbuf_f_16 port(d : in std_logic; pad : out std_logic); end component;
component outbuf_f_24 port(d : in std_logic; pad : out std_logic); end component;
component tribuff port(d, e : in std_logic; pad : out std_logic); end component;
component hclkint port(a : in std_ulogic; y : out std_ulogic); end component;
component clkint port(a : in std_ulogic; y : out std_ulogic); end component;
component hclkbuf_pci
port( pad : in std_logic; y : out std_logic); end component;
component clkbuf_pci port(pad : in std_logic; y : out std_logic); end component;
component inbuf_pci port(pad :in std_logic; y : out std_logic); end component;
attribute syn_tpd11 : string;
attribute syn_tpd11 of inbuf_pci : component is "pad -> y = 2.0";
component bibuf_pci port(
d, e : in std_logic; pad : inout std_logic; y : out std_logic);
end component;
attribute syn_tpd12 : string;
attribute syn_tpd12 of bibuf_pci : component is "pad -> y = 2.0";
component outbuf_pci port(d : in std_logic; pad : out std_logic); end component;
attribute syn_tpd13 : string;
attribute syn_tpd13 of outbuf_pci : component is "d -> pad = 2.0";
component tribuff_pci port(d, e : in std_logic; pad : out std_logic); end component;
attribute syn_tpd14 : string;
attribute syn_tpd14 of tribuff_pci : component is "d,e -> pad = 2.0";
-- 1553 -------------------------------
component add1 is
port(
a : in std_logic;
b : in std_logic;
fci : in std_logic;
s : out std_logic;
fco : out std_logic);
end component add1;
component and2 is
port(
a : in std_logic;
b : in std_logic;
y : out std_logic);
end component and2;
component and2a is
port(
a : in std_logic;
b : in std_logic;
y : out std_logic);
end component and2a;
component and2b is
port(
a : in std_logic;
b : in std_logic;
y : out std_logic);
end component and2b;
component and3 is
port(
a : in std_logic;
b : in std_logic;
c : in std_logic;
y : out std_logic);
end component and3;
component and3a is
port(
a : in std_logic;
b : in std_logic;
c : in std_logic;
y : out std_logic);
end component and3a;
component and3b is
port(
a : in std_logic;
b : in std_logic;
c : in std_logic;
y : out std_logic);
end component and3b;
component and3c is
port(
a : in std_logic;
b : in std_logic;
c : in std_logic;
y : out std_logic);
end component and3c;
component and4 is
port(
a : in std_logic;
b : in std_logic;
c : in std_logic;
d : in std_logic;
y : out std_logic);
end component and4;
component and4a is
port(
a : in std_logic;
b : in std_logic;
c : in std_logic;
d : in std_logic;
y : out std_logic);
end component and4a;
component and4b is
port(
a : in std_logic;
b : in std_logic;
c : in std_logic;
d : in std_logic;
y : out std_logic);
end component and4b;
component and4c is
port(
a : in std_logic;
b : in std_logic;
c : in std_logic;
d : in std_logic;
y : out std_logic);
end component and4c;
component buff is
port(
a : in std_logic;
y : out std_logic);
end component buff;
component cm8 is
port(
d0 : in std_logic;
d1 : in std_logic;
d2 : in std_logic;
d3 : in std_logic;
s00 : in std_logic;
s01 : in std_logic;
s10 : in std_logic;
s11 : in std_logic;
y : out std_logic);
end component cm8;
component cm8inv is
port(
a : in std_logic;
y : out std_logic);
end component cm8inv;
component df1 is
port(
d : in std_logic;
clk : in std_logic;
q : out std_logic);
end component df1;
component dfc1b is
port(
d : in std_logic;
clk : in std_logic;
clr : in std_logic;
q : out std_logic);
end component dfc1b;
component dfc1c is
port(
d : in std_logic;
clk : in std_logic;
clr : in std_logic;
q : out std_logic);
end component dfc1c;
component dfc1d is
port(
d : in std_logic;
clk : in std_logic;
clr : in std_logic;
q : out std_logic);
end component dfc1d;
component dfe1b is
port(
d : in std_logic;
e : in std_logic;
clk : in std_logic;
q : out std_logic);
end component dfe1b;
component dfe3c is
port(
d : in std_logic;
e : in std_logic;
clk : in std_logic;
clr : in std_logic;
q : out std_logic);
end component dfe3c;
component dfe4f is
port(
d : in std_logic;
e : in std_logic;
clk : in std_logic;
pre : in std_logic;
q : out std_logic);
end component dfe4f;
component dfp1 is
port(
d : in std_logic;
clk : in std_logic;
pre : in std_logic;
q : out std_logic);
end component dfp1;
component dfp1b is
port(
d : in std_logic;
clk : in std_logic;
pre : in std_logic;
q : out std_logic);
end component dfp1b;
component dfp1d is
port(
d : in std_logic;
clk : in std_logic;
pre : in std_logic;
q : out std_logic);
end component dfp1d;
component dfm
port(
clk : in std_logic;
s : in std_logic;
a : in std_logic;
b : in std_logic;
q : out std_logic);
end component;
component gnd is
port(
y : out std_logic);
end component gnd;
component inv is
port(
a : in std_logic;
y : out std_logic);
end component inv;
component nand4 is
port(
a : in std_logic;
b : in std_logic;
c : in std_logic;
d : in std_logic;
y : out std_logic);
end component nand4;
component or2 is
port(
a : in std_logic;
b : in std_logic;
y : out std_logic);
end component or2;
component or2a is
port(
a : in std_logic;
b : in std_logic;
y : out std_logic);
end component or2a;
component or2b is
port(
a : in std_logic;
b : in std_logic;
y : out std_logic);
end component or2b;
component or3 is
port(
a : in std_logic;
b : in std_logic;
c : in std_logic;
y : out std_logic);
end component or3;
component or3a is
port(
a : in std_logic;
b : in std_logic;
c : in std_logic;
y : out std_logic);
end component or3a;
component or3b is
port(
a : in std_logic;
b : in std_logic;
c : in std_logic;
y : out std_logic);
end component or3b;
component or3c is
port(
a : in std_logic;
b : in std_logic;
c : in std_logic;
y : out std_logic);
end component or3c;
component or4 is
port(
a : in std_logic;
b : in std_logic;
c : in std_logic;
d : in std_logic;
y : out std_logic);
end component or4;
component or4a is
port(
a : in std_logic;
b : in std_logic;
c : in std_logic;
d : in std_logic;
y : out std_logic);
end component or4a;
component or4b is
port(
a : in std_logic;
b : in std_logic;
c : in std_logic;
d : in std_logic;
y : out std_logic);
end component or4b;
component or4c is
port(
a : in std_logic;
b : in std_logic;
c : in std_logic;
d : in std_logic;
y : out std_logic);
end component or4c;
component or4d is
port(
a : in std_logic;
b : in std_logic;
c : in std_logic;
d : in std_logic;
y : out std_logic);
end component or4d;
component sub1 is
port(
a : in std_logic;
b : in std_logic;
fci : in std_logic;
s : out std_logic;
fco : out std_logic);
end component sub1;
component vcc is
port(
y : out std_logic);
end component vcc;
component xa1 is
port(
a : in std_logic;
b : in std_logic;
c : in std_logic;
y : out std_logic);
end component xa1;
component xnor2 is
port(
a : in std_logic;
b : in std_logic;
y : out std_logic);
end component xnor2;
component xor2 is
port(
a : in std_logic;
b : in std_logic;
y : out std_logic);
end component xor2;
component xor4 is
port(a,b,c,d : in std_logic;
y : out std_logic);
end component xor4;
component mx2
port(
a : in std_logic;
s : in std_logic;
b : in std_logic;
y : out std_logic);
end component;
component ax1c
port(
a: in std_logic;
b: in std_logic;
c: in std_logic;
y: out std_logic);
end component;
component df1b
port(
d : in std_logic;
clk : in std_logic;
q : out std_logic);
end component;
component dfe1b
port(
d : in std_logic;
e : in std_logic;
clk : in std_logic;
q : out std_logic);
end component;
component df1
port(
d : in std_logic;
clk : in std_logic;
q : out std_logic);
end component;
end;
| mit | 9d8c1d5fa18b8ebe46d8b63c76083f2d | 0.570939 | 3.163913 | false | false | false | false |
impedimentToProgress/UCI-BlueChip | AttackFiles/Attacks/privEsc/lib/gaisler/ata/atactrl_nodma.vhd | 2 | 12,196 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: atactrl_nodma
-- File: atactrl_nodma.vhd
-- Author: Nils-Johan Wessman, Gaisler Research
-- Description: ATA controller
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
library gaisler;
use gaisler.ata.all;
library opencores;
use opencores.occomp.all;
entity atactrl_nodma is
generic (
hindex : integer := 0;
haddr : integer := 0;
hmask : integer := 16#ff0#;
pirq : integer := 0;
TWIDTH : natural := 8; -- counter width
-- PIO mode 0 settings (@100MHz clock)
PIO_mode0_T1 : natural := 6; -- 70ns
PIO_mode0_T2 : natural := 28; -- 290ns
PIO_mode0_T4 : natural := 2; -- 30ns
PIO_mode0_Teoc : natural := 23 -- 240ns ==> T0 - T1 - T2 = 600 - 70 - 290 = 240
);
port (
rst : in std_ulogic;
arst : in std_ulogic;
clk : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
cfo : out cf_out_type;
-- ATA signals
ddin : in std_logic_vector(15 downto 0);
iordy : in std_logic;
intrq : in std_logic;
ata_resetn : out std_logic;
ddout : out std_logic_vector(15 downto 0);
ddoe : out std_logic;
da : out std_logic_vector(2 downto 0);
cs0n : out std_logic;
cs1n : out std_logic;
diorn : out std_logic;
diown : out std_logic;
dmack : out std_logic
);
end;
architecture rtl of atactrl_nodma is
-- Device ID
constant DeviceId : integer := 2;
constant RevisionNo : integer := 0;
constant VERSION : integer := 0;
component ocidec2_amba_slave is
generic (
hindex : integer := 0;
haddr : integer := 0;
hmask : integer := 16#ff0#;
pirq : integer := 0;
DeviceID : integer := 0;
RevisionNo : integer := 0;
-- PIO mode 0 settings (@100MHz clock)
PIO_mode0_T1 : natural := 6; -- 70ns
PIO_mode0_T2 : natural := 28; -- 290ns
PIO_mode0_T4 : natural := 2; -- 30ns
PIO_mode0_Teoc : natural := 23; -- 240ns ==> T0 - T1 - T2 = 600 - 70 - 290 = 240
-- Multiword DMA mode 0 settings (@100MHz clock)
DMA_mode0_Tm : natural := 4; -- 50ns
DMA_mode0_Td : natural := 21; -- 215ns
DMA_mode0_Teoc : natural := 21 -- 215ns ==> T0 - Td - Tm = 480 - 50 - 215 = 215
);
port (
rst : in std_ulogic;
arst : in std_ulogic;
clk : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
cf_power: out std_logic;
-- ata controller signals
-- PIO control input
PIOsel : out std_logic;
PIOtip, -- PIO transfer in progress
PIOack : in std_logic; -- PIO acknowledge signal
PIOq : in std_logic_vector(15 downto 0); -- PIO data input
PIOpp_full : in std_logic; -- PIO write-ping-pong buffers full
irq : in std_logic; -- interrupt signal input
PIOa : out std_logic_vector(3 downto 0);
PIOd : out std_logic_vector(15 downto 0);
PIOwe : out std_logic;
-- DMA control inputs
DMAsel : out std_logic;
DMAtip, -- DMA transfer in progress
DMAack, -- DMA transfer acknowledge
DMARxEmpty, -- DMA receive buffer empty
DMATxFull, -- DMA transmit buffer full
DMA_dmarq : in std_logic; -- wishbone DMA request
DMAq : in std_logic_vector(31 downto 0);
-- outputs
-- control register outputs
IDEctrl_rst,
IDEctrl_IDEen,
IDEctrl_FATR1,
IDEctrl_FATR0,
IDEctrl_ppen,
DMActrl_DMAen,
DMActrl_dir,
DMActrl_BeLeC0,
DMActrl_BeLeC1 : out std_logic;
-- CMD port timing registers
PIO_cmdport_T1,
PIO_cmdport_T2,
PIO_cmdport_T4,
PIO_cmdport_Teoc : out std_logic_vector(7 downto 0);
PIO_cmdport_IORDYen : out std_logic;
-- data-port0 timing registers
PIO_dport0_T1,
PIO_dport0_T2,
PIO_dport0_T4,
PIO_dport0_Teoc : out std_logic_vector(7 downto 0);
PIO_dport0_IORDYen : out std_logic;
-- data-port1 timing registers
PIO_dport1_T1,
PIO_dport1_T2,
PIO_dport1_T4,
PIO_dport1_Teoc : out std_logic_vector(7 downto 0);
PIO_dport1_IORDYen : out std_logic;
-- DMA device0 timing registers
DMA_dev0_Tm,
DMA_dev0_Td,
DMA_dev0_Teoc : out std_logic_vector(7 downto 0);
-- DMA device1 timing registers
DMA_dev1_Tm,
DMA_dev1_Td,
DMA_dev1_Teoc : out std_logic_vector(7 downto 0)
);
end component;
-- asynchronous reset signal
signal arst_signal : std_logic;
-- primary address decoder
signal PIOsel : std_logic; -- controller select, IDE devices select
-- control signal
signal IDEctrl_rst, IDEctrl_IDEen, IDEctrl_FATR0, IDEctrl_FATR1 : std_logic;
-- compatible mode timing
signal PIO_cmdport_T1, PIO_cmdport_T2, PIO_cmdport_T4, PIO_cmdport_Teoc : std_logic_vector(7 downto 0);
signal PIO_cmdport_IORDYen : std_logic;
-- data port0 timing
signal PIO_dport0_T1, PIO_dport0_T2, PIO_dport0_T4, PIO_dport0_Teoc : std_logic_vector(7 downto 0);
signal PIO_dport0_IORDYen : std_logic;
-- data port1 timing
signal PIO_dport1_T1, PIO_dport1_T2, PIO_dport1_T4, PIO_dport1_Teoc : std_logic_vector(7 downto 0);
signal PIO_dport1_IORDYen : std_logic;
signal PIOack : std_logic;
signal PIOq : std_logic_vector(15 downto 0);
signal PIOa : std_logic_vector(3 downto 0);
signal PIOd : std_logic_vector(15 downto 0);
signal PIOwe : std_logic;
signal irq : std_logic; -- ATA bus IRQ signal
signal reset : std_logic;
signal gnd,vcc : std_logic;
signal gnd32 : std_logic_vector(31 downto 0);
begin
gnd <= '0';vcc <= '1'; gnd32 <= zero32;
-- generate asynchronous reset level
arst_signal <= arst;-- xor ARST_LVL;
reset <= not rst;
dmack <= vcc; -- Disable DMA
-- Generate CompactFlash signals
--cfo.power connected to bit 31 of the control register
cfo.atasel <= gnd;
cfo.we <= vcc;
cfo.csel <= gnd;
cfo.da <= (others => gnd);
u0: ocidec2_amba_slave
generic map(
hindex => hindex,
haddr => haddr,
hmask => hmask,
pirq => pirq,
DeviceID => DeviceID,
RevisionNo => RevisionNo,
-- PIO mode 0 settings
PIO_mode0_T1 => PIO_mode0_T1,
PIO_mode0_T2 => PIO_mode0_T2,
PIO_mode0_T4 => PIO_mode0_T4,
PIO_mode0_Teoc => PIO_mode0_Teoc,
-- Multiword DMA mode 0 settings
-- OCIDEC-1 does not support DMA, set registers to zero
DMA_mode0_Tm => 0,
DMA_mode0_Td => 0,
DMA_mode0_Teoc => 0
)
port map(
arst => arst_signal,
rst => rst,
clk => clk,
ahbsi => ahbsi,
ahbso => ahbso,
cf_power => cfo.power, -- power switch for compactflash
-- PIO control input
-- PIOtip is only asserted during a PIO transfer (No shit! ;)
-- Since it is impossible to read the status register and access the PIO registers at the same time
-- this bit is useless (besides using-up resources)
PIOtip => gnd,
PIOack => PIOack,
PIOq => PIOq,
PIOsel => PIOsel,
PIOpp_full => gnd, -- OCIDEC-1 does not support PIO-write PingPong, negate signal
irq => irq,
PIOa => PIOa,
PIOd => PIOd,
PIOwe => PIOwe,
-- DMA control inputs (negate all of them)
DMAtip => gnd,
DMAack => gnd,
DMARxEmpty => gnd,
DMATxFull => gnd,
DMA_dmarq => gnd,
DMAq => gnd32,
-- outputs
-- control register outputs
IDEctrl_rst => IDEctrl_rst,
IDEctrl_IDEen => IDEctrl_IDEen,
IDEctrl_FATR0 => IDEctrl_FATR0,
IDEctrl_FATR1 => IDEctrl_FATR1,
-- CMD port timing registers
PIO_cmdport_T1 => PIO_cmdport_T1,
PIO_cmdport_T2 => PIO_cmdport_T2,
PIO_cmdport_T4 => PIO_cmdport_T4,
PIO_cmdport_Teoc => PIO_cmdport_Teoc,
PIO_cmdport_IORDYen => PIO_cmdport_IORDYen,
-- data-port0 timing registers
PIO_dport0_T1 => PIO_dport0_T1,
PIO_dport0_T2 => PIO_dport0_T2,
PIO_dport0_T4 => PIO_dport0_T4,
PIO_dport0_Teoc => PIO_dport0_Teoc,
PIO_dport0_IORDYen => PIO_dport0_IORDYen,
-- data-port1 timing registers
PIO_dport1_T1 => PIO_dport1_T1,
PIO_dport1_T2 => PIO_dport1_T2,
PIO_dport1_T4 => PIO_dport1_T4,
PIO_dport1_Teoc => PIO_dport1_Teoc,
PIO_dport1_IORDYen => PIO_dport1_IORDYen
);
u1: ocidec2_controller
generic map(
TWIDTH => TWIDTH,
PIO_mode0_T1 => PIO_mode0_T1,
PIO_mode0_T2 => PIO_mode0_T2,
PIO_mode0_T4 => PIO_mode0_T4,
PIO_mode0_Teoc => PIO_mode0_Teoc
)
port map(
clk => clk,
nReset => arst_signal,
rst => reset,
irq => irq,
IDEctrl_rst => IDEctrl_rst,
IDEctrl_IDEen => IDEctrl_IDEen,
IDEctrl_FATR0 => IDEctrl_FATR0,
IDEctrl_FATR1 => IDEctrl_FATR1,
cmdport_T1 => PIO_cmdport_T1,
cmdport_T2 => PIO_cmdport_T2,
cmdport_T4 => PIO_cmdport_T4,
cmdport_Teoc => PIO_cmdport_Teoc,
cmdport_IORDYen => PIO_cmdport_IORDYen,
dport0_T1 => PIO_dport0_T1,
dport0_T2 => PIO_dport0_T2,
dport0_T4 => PIO_dport0_T4,
dport0_Teoc => PIO_dport0_Teoc,
dport0_IORDYen => PIO_dport0_IORDYen,
dport1_T1 => PIO_dport1_T1,
dport1_T2 => PIO_dport1_T2,
dport1_T4 => PIO_dport1_T4,
dport1_Teoc => PIO_dport1_Teoc,
dport1_IORDYen => PIO_dport1_IORDYen,
PIOreq => PIOsel,
PIOack => PIOack,
PIOa => PIOa,
PIOd => PIOd,
PIOq => PIOq,
PIOwe => PIOwe,
RESETn => ata_resetn,
DDi => ddin,
DDo => ddout,
DDoe => ddoe,
DA => da,
CS0n => cs0n,
CS1n => cs1n,
DIORn => diorn,
DIOWn => diown,
IORDY => iordy,
INTRQ => intrq
);
-- pragma translate_off
bootmsg : report_version
generic map ("atactrl" & tost(hindex) &
": ATA controller rev " & tost(VERSION) & ", no DMA, irq " & tost(pirq));
-- pragma translate_on
end;
| mit | ad95f87ae5ab5300dde467ac3e0a7ba0 | 0.537389 | 3.381203 | false | false | false | false |
cafe-alpha/wascafe | v13/stm32_bup_test/r07c_de10_20200912/wasca/wasca_inst.vhd | 1 | 11,662 | component wasca is
port (
abus_slave_0_abus_address : in std_logic_vector(9 downto 0) := (others => 'X'); -- address
abus_slave_0_abus_chipselect : in std_logic_vector(2 downto 0) := (others => 'X'); -- chipselect
abus_slave_0_abus_read : in std_logic := 'X'; -- read
abus_slave_0_abus_write : in std_logic_vector(1 downto 0) := (others => 'X'); -- write
abus_slave_0_abus_waitrequest : out std_logic; -- waitrequest
abus_slave_0_abus_interrupt : out std_logic; -- interrupt
abus_slave_0_abus_addressdata : inout std_logic_vector(15 downto 0) := (others => 'X'); -- addressdata
abus_slave_0_abus_direction : out std_logic; -- direction
abus_slave_0_abus_muxing : out std_logic_vector(1 downto 0); -- muxing
abus_slave_0_abus_disableout : out std_logic; -- disableout
abus_slave_0_conduit_saturn_reset_saturn_reset : in std_logic := 'X'; -- saturn_reset
altpll_0_areset_conduit_export : in std_logic := 'X'; -- export
altpll_0_locked_conduit_export : out std_logic; -- export
altpll_0_phasedone_conduit_export : out std_logic; -- export
clk_clk : in std_logic := 'X'; -- clk
external_sdram_controller_wire_addr : out std_logic_vector(12 downto 0); -- addr
external_sdram_controller_wire_ba : out std_logic_vector(1 downto 0); -- ba
external_sdram_controller_wire_cas_n : out std_logic; -- cas_n
external_sdram_controller_wire_cke : out std_logic; -- cke
external_sdram_controller_wire_cs_n : out std_logic; -- cs_n
external_sdram_controller_wire_dq : inout std_logic_vector(15 downto 0) := (others => 'X'); -- dq
external_sdram_controller_wire_dqm : out std_logic_vector(1 downto 0); -- dqm
external_sdram_controller_wire_ras_n : out std_logic; -- ras_n
external_sdram_controller_wire_we_n : out std_logic; -- we_n
extra_leds_conn_export : out std_logic_vector(4 downto 0); -- export
hex0_conn_export : out std_logic_vector(6 downto 0); -- export
hex1_conn_export : out std_logic_vector(6 downto 0); -- export
hex2_conn_export : out std_logic_vector(6 downto 0); -- export
hex3_conn_export : out std_logic_vector(6 downto 0); -- export
hex4_conn_export : out std_logic_vector(6 downto 0); -- export
hex5_conn_export : out std_logic_vector(6 downto 0); -- export
hexdot_conn_export : out std_logic_vector(5 downto 0); -- export
leds_conn_export : out std_logic_vector(3 downto 0); -- export
sdram_clkout_clk : out std_logic; -- clk
spi_stm32_MISO : in std_logic := 'X'; -- MISO
spi_stm32_MOSI : out std_logic; -- MOSI
spi_stm32_SCLK : out std_logic; -- SCLK
spi_stm32_SS_n : out std_logic; -- SS_n
spi_sync_conn_export : in std_logic := 'X'; -- export
switches_conn_export : in std_logic_vector(7 downto 0) := (others => 'X'); -- export
uart_0_external_connection_rxd : in std_logic := 'X'; -- rxd
uart_0_external_connection_txd : out std_logic -- txd
);
end component wasca;
u0 : component wasca
port map (
abus_slave_0_abus_address => CONNECTED_TO_abus_slave_0_abus_address, -- abus_slave_0_abus.address
abus_slave_0_abus_chipselect => CONNECTED_TO_abus_slave_0_abus_chipselect, -- .chipselect
abus_slave_0_abus_read => CONNECTED_TO_abus_slave_0_abus_read, -- .read
abus_slave_0_abus_write => CONNECTED_TO_abus_slave_0_abus_write, -- .write
abus_slave_0_abus_waitrequest => CONNECTED_TO_abus_slave_0_abus_waitrequest, -- .waitrequest
abus_slave_0_abus_interrupt => CONNECTED_TO_abus_slave_0_abus_interrupt, -- .interrupt
abus_slave_0_abus_addressdata => CONNECTED_TO_abus_slave_0_abus_addressdata, -- .addressdata
abus_slave_0_abus_direction => CONNECTED_TO_abus_slave_0_abus_direction, -- .direction
abus_slave_0_abus_muxing => CONNECTED_TO_abus_slave_0_abus_muxing, -- .muxing
abus_slave_0_abus_disableout => CONNECTED_TO_abus_slave_0_abus_disableout, -- .disableout
abus_slave_0_conduit_saturn_reset_saturn_reset => CONNECTED_TO_abus_slave_0_conduit_saturn_reset_saturn_reset, -- abus_slave_0_conduit_saturn_reset.saturn_reset
altpll_0_areset_conduit_export => CONNECTED_TO_altpll_0_areset_conduit_export, -- altpll_0_areset_conduit.export
altpll_0_locked_conduit_export => CONNECTED_TO_altpll_0_locked_conduit_export, -- altpll_0_locked_conduit.export
altpll_0_phasedone_conduit_export => CONNECTED_TO_altpll_0_phasedone_conduit_export, -- altpll_0_phasedone_conduit.export
clk_clk => CONNECTED_TO_clk_clk, -- clk.clk
external_sdram_controller_wire_addr => CONNECTED_TO_external_sdram_controller_wire_addr, -- external_sdram_controller_wire.addr
external_sdram_controller_wire_ba => CONNECTED_TO_external_sdram_controller_wire_ba, -- .ba
external_sdram_controller_wire_cas_n => CONNECTED_TO_external_sdram_controller_wire_cas_n, -- .cas_n
external_sdram_controller_wire_cke => CONNECTED_TO_external_sdram_controller_wire_cke, -- .cke
external_sdram_controller_wire_cs_n => CONNECTED_TO_external_sdram_controller_wire_cs_n, -- .cs_n
external_sdram_controller_wire_dq => CONNECTED_TO_external_sdram_controller_wire_dq, -- .dq
external_sdram_controller_wire_dqm => CONNECTED_TO_external_sdram_controller_wire_dqm, -- .dqm
external_sdram_controller_wire_ras_n => CONNECTED_TO_external_sdram_controller_wire_ras_n, -- .ras_n
external_sdram_controller_wire_we_n => CONNECTED_TO_external_sdram_controller_wire_we_n, -- .we_n
extra_leds_conn_export => CONNECTED_TO_extra_leds_conn_export, -- extra_leds_conn.export
hex0_conn_export => CONNECTED_TO_hex0_conn_export, -- hex0_conn.export
hex1_conn_export => CONNECTED_TO_hex1_conn_export, -- hex1_conn.export
hex2_conn_export => CONNECTED_TO_hex2_conn_export, -- hex2_conn.export
hex3_conn_export => CONNECTED_TO_hex3_conn_export, -- hex3_conn.export
hex4_conn_export => CONNECTED_TO_hex4_conn_export, -- hex4_conn.export
hex5_conn_export => CONNECTED_TO_hex5_conn_export, -- hex5_conn.export
hexdot_conn_export => CONNECTED_TO_hexdot_conn_export, -- hexdot_conn.export
leds_conn_export => CONNECTED_TO_leds_conn_export, -- leds_conn.export
sdram_clkout_clk => CONNECTED_TO_sdram_clkout_clk, -- sdram_clkout.clk
spi_stm32_MISO => CONNECTED_TO_spi_stm32_MISO, -- spi_stm32.MISO
spi_stm32_MOSI => CONNECTED_TO_spi_stm32_MOSI, -- .MOSI
spi_stm32_SCLK => CONNECTED_TO_spi_stm32_SCLK, -- .SCLK
spi_stm32_SS_n => CONNECTED_TO_spi_stm32_SS_n, -- .SS_n
spi_sync_conn_export => CONNECTED_TO_spi_sync_conn_export, -- spi_sync_conn.export
switches_conn_export => CONNECTED_TO_switches_conn_export, -- switches_conn.export
uart_0_external_connection_rxd => CONNECTED_TO_uart_0_external_connection_rxd, -- uart_0_external_connection.rxd
uart_0_external_connection_txd => CONNECTED_TO_uart_0_external_connection_txd -- .txd
);
| gpl-2.0 | 44bf7370e7757e062472e81272ec3ae6 | 0.406277 | 4.683534 | false | false | false | false |
impedimentToProgress/UCI-BlueChip | AttackFiles/Attacks/privEsc/lib/grlib/amba/ahbctrl.vhd | 2 | 26,677 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
----------------------------------------------------------------------------
-- Entity: ahbctrl
-- File: ahbctrl.vhd
-- Author: Jiri Gaisler, Gaisler Research
-- Modified: Edvin Catovic, Gaisler Research
-- Description: AMBA arbiter, decoder and multiplexer with plug&play support
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.stdlib.all;
use grlib.amba.all;
-- pragma translate_off
use grlib.devices.all;
use std.textio.all;
-- pragma translate_on
entity ahbctrl is
generic (
defmast : integer := 0; -- default master
split : integer := 0; -- split support
rrobin : integer := 0; -- round-robin arbitration
timeout : integer range 0 to 255 := 0; -- HREADY timeout
ioaddr : ahb_addr_type := 16#fff#; -- I/O area MSB address
iomask : ahb_addr_type := 16#fff#; -- I/O area address mask
cfgaddr : ahb_addr_type := 16#ff0#; -- config area MSB address
cfgmask : ahb_addr_type := 16#ff0#; -- config area address mask
nahbm : integer range 1 to NAHBMST := NAHBMST; -- number of masters
nahbs : integer range 1 to NAHBSLV := NAHBSLV; -- number of slaves
ioen : integer range 0 to 15 := 1; -- enable I/O area
disirq : integer range 0 to 1 := 0; -- disable interrupt routing
fixbrst : integer range 0 to 1 := 0; -- support fix-length bursts
debug : integer range 0 to 2 := 2; -- report cores to console
fpnpen : integer range 0 to 1 := 0; -- full PnP configuration decoding
icheck : integer range 0 to 1 := 1;
devid : integer := 0; -- unique device ID
enbusmon : integer range 0 to 1 := 0; --enable bus monitor
assertwarn : integer range 0 to 1 := 0; --enable assertions for warnings
asserterr : integer range 0 to 1 := 0; --enable assertions for errors
hmstdisable : integer := 0; --disable master checks
hslvdisable : integer := 0; --disable slave checks
arbdisable : integer := 0; --disable arbiter checks
mprio : integer := 0 --master with highest priority
);
port (
rst : in std_ulogic;
clk : in std_ulogic;
msti : out ahb_mst_in_type;
msto : in ahb_mst_out_vector;
slvi : out ahb_slv_in_type;
slvo : in ahb_slv_out_vector;
testen : in std_ulogic := '0';
testrst : in std_ulogic := '1';
scanen : in std_ulogic := '0';
testoen : in std_ulogic := '1'
);
end;
architecture rtl of ahbctrl is
constant nahbmx : integer := 2**log2(nahbm);
type nmstarr is array (1 to 3) of integer range 0 to nahbmx-1;
type nvalarr is array (1 to 3) of boolean;
type reg_type is record
hmaster : integer range 0 to nahbmx -1;
hmasterd : integer range 0 to nahbmx -1;
hslave : integer range 0 to nahbs-1;
hmasterlock : std_ulogic;
hready : std_ulogic;
defslv : std_ulogic;
htrans : std_logic_vector(1 downto 0);
haddr : std_logic_vector(15 downto 2);
cfgsel : std_ulogic;
cfga11 : std_ulogic;
hrdatam : std_logic_vector(31 downto 0);
hrdatas : std_logic_vector(31 downto 0);
beat : std_logic_vector(3 downto 0);
defmst : std_ulogic;
end record;
type l0_type is array (0 to 15) of std_logic_vector(2 downto 0);
type l1_type is array (0 to 7) of std_logic_vector(3 downto 0);
type l2_type is array (0 to 3) of std_logic_vector(4 downto 0);
type l3_type is array (0 to 1) of std_logic_vector(5 downto 0);
type tztab_type is array (0 to 15) of std_logic_vector(2 downto 0);
constant tztab : tztab_type := ("100", "000", "001", "000",
"010", "000", "001", "000",
"011", "000", "001", "000",
"010", "000", "001", "000");
function tz(vect_in : std_logic_vector) return std_logic_vector is
variable vect : std_logic_vector(63 downto 0);
variable l0 : l0_type;
variable l1 : l1_type;
variable l2 : l2_type;
variable l3 : l3_type;
variable l4 : std_logic_vector(6 downto 0);
variable bci_lsb, bci_msb : std_logic_vector(3 downto 0);
variable bco_lsb, bco_msb : std_logic_vector(2 downto 0);
variable sel : std_logic;
begin
vect := (others => '1');
vect(vect_in'length-1 downto 0) := vect_in;
-- level 0
for i in 0 to 7 loop
bci_lsb := vect(8*i+3 downto 8*i);
bci_msb := vect(8*i+7 downto 8*i+4);
bco_lsb := tztab(conv_integer(bci_lsb));
bco_msb := tztab(conv_integer(bci_msb));
sel := bco_lsb(2);
if sel = '0' then l1(i) := '0' & bco_lsb;
else l1(i) := bco_msb(2) & not bco_msb(2) & bco_msb(1 downto 0); end if;
end loop;
-- level 1
for i in 0 to 3 loop
sel := l1(2*i)(3);
if sel = '0' then l2(i) := '0' & l1(2*i);
else
l2(i) := l1(2*i+1)(3) & not l1(2*i+1)(3) & l1(2*i+1)(2 downto 0);
end if;
end loop;
-- level 2
for i in 0 to 1 loop
sel := l2(2*i)(4);
if sel = '0' then l3(i) := '0' & l2(2*i);
else
l3(i) := l2(2*i+1)(4) & not l2(2*i+1)(4) & l2(2*i+1)(3 downto 0);
end if;
end loop;
--level 3
if l3(0)(5) = '0' then l4 := '0' & l3(0);
else l4 := l3(1)(5) & not l3(1)(5) & l3(1)(4 downto 0); end if;
return(l4);
end;
function lz(vect_in : std_logic_vector) return std_logic_vector is
variable vect : std_logic_vector(vect_in'length-1 downto 0);
variable vect2 : std_logic_vector(vect_in'length-1 downto 0);
begin
vect := vect_in;
for i in vect'right to vect'left loop
vect2(i) := vect(vect'left-i);
end loop;
return(tz(vect2));
end;
-- Find next master:
-- * 2 arbitration policies: fixed priority or round-robin
-- * Fixed priority: priority is fixed, highest index has highest priority
-- * Round-robin: arbiter maintains circular queue of masters
-- * (master 0, master 1, ..., master (nahbmx-1)). First requesting master
-- * in the queue is granted access to the bus and moved to the end of the queue.
-- * splitted masters are not granted
-- * bus is re-arbited when current owner does not request the bus,
-- or when it performs non-burst accesses
-- * fix length burst transfers will not be interrupted
-- * incremental bursts should assert hbusreq until last access
procedure selmast(r : in reg_type;
msto : in ahb_mst_out_vector;
rsplit : in std_logic_vector(0 to nahbmx-1);
mast : out integer range 0 to nahbmx-1;
defmst : out std_ulogic) is
variable nmst : nmstarr;
variable nvalid : nvalarr;
variable rrvec : std_logic_vector(nahbmx*2-1 downto 0);
variable zcnt : std_logic_vector(log2(nahbmx)+1 downto 0);
variable hpvec : std_logic_vector(nahbmx-1 downto 0);
variable zcnt2 : std_logic_vector(log2(nahbmx) downto 0);
begin
nvalid(1 to 3) := (others => false); nmst(1 to 3) := (others => 0);
mast := r.hmaster;
defmst := '0';
if nahbm = 1 then
mast := 0;
elsif rrobin = 0 then
hpvec := (others => '0');
for i in 0 to nahbmx-1 loop
if ((rsplit(i) = '0') or (split = 0)) then
hpvec(i) := msto(i).hbusreq;
end if;
end loop;
zcnt2 := lz(hpvec)(log2(nahbmx) downto 0);
if zcnt2(log2(nahbmx)) = '0' then nvalid(2) := true; end if;
nmst(2) := conv_integer(not (zcnt2(log2(nahbmx)-1 downto 0)));
for i in 0 to nahbmx-1 loop
if not ((nmst(3) = defmast) and nvalid(3)) then
nmst(3) := i; nvalid(3) := true;
end if;
end loop;
else
rrvec := (others => '0');
for i in 0 to nahbmx-1 loop
if (rsplit(i) = '0') or (split = 0) then
if (i <= r.hmaster) then rrvec(i) := '0';
else rrvec(i) := msto(i).hbusreq; end if;
rrvec(nahbmx+i) := msto(i).hbusreq;
end if;
end loop;
zcnt := tz(rrvec)(log2(nahbmx)+1 downto 0);
if zcnt(log2(nahbmx)+1) = '0' then nvalid(2) := true; end if;
nmst(2) := conv_integer(zcnt(log2(nahbmx)-1 downto 0));
nmst(3) := r.hmaster; nvalid(3) := true;
if (mprio /= 0) and ((rsplit(mprio) = '0') or (split = 0)) then
if msto(mprio).hbusreq = '1' then nmst(1) := mprio; nvalid(1) := true; end if;
end if;
end if;
for i in 1 to 3 loop
if nvalid(i) then mast := nmst(i); exit; end if;
end loop;
if (not (nvalid(1) or nvalid(2))) and (split /= 0) then
defmst := orv(rsplit);
end if;
end;
constant MIMAX : integer := log2x(nahbmx) - 1;
constant SIMAX : integer := log2x(nahbs) - 1;
constant IOAREA : std_logic_vector(11 downto 0) :=
conv_std_logic_vector(ioaddr, 12);
constant IOMSK : std_logic_vector(11 downto 0) :=
conv_std_logic_vector(iomask, 12);
constant CFGAREA : std_logic_vector(11 downto 0) :=
conv_std_logic_vector(cfgaddr, 12);
constant CFGMSK : std_logic_vector(11 downto 0) :=
conv_std_logic_vector(cfgmask, 12);
constant FULLPNP : boolean := (fpnpen /= 0);
signal r, rin : reg_type;
signal rsplit, rsplitin : std_logic_vector(0 to nahbmx-1);
-- pragma translate_off
signal lmsti : ahb_mst_in_type;
signal lslvi : ahb_slv_in_type;
-- pragma translate_on
begin
comb : process(rst, msto, slvo, r, rsplit, testen, testrst, scanen, testoen)
variable v : reg_type;
variable nhmaster, hmaster : integer range 0 to nahbmx -1;
variable hgrant : std_logic_vector(0 to NAHBMST-1); -- bus grant
variable hsel : std_logic_vector(0 to 31); -- slave select
variable hmbsel : std_logic_vector(0 to NAHBAMR-1);
variable nslave : natural range 0 to 31;
variable vsplit : std_logic_vector(0 to nahbmx-1);
variable bnslave : std_logic_vector(3 downto 0);
variable area : std_logic_vector(1 downto 0);
variable hready : std_ulogic;
variable defslv : std_ulogic;
variable cfgsel : std_ulogic;
variable hcache : std_ulogic;
variable hresp : std_logic_vector(1 downto 0);
variable hrdata : std_logic_vector(31 downto 0);
variable haddr : std_logic_vector(31 downto 0);
variable hirq : std_logic_vector(NAHBIRQ-1 downto 0);
variable arb : std_ulogic;
variable hconfndx : integer range 0 to 7;
variable vslvi : ahb_slv_in_type;
variable defmst : std_ulogic;
variable tmpv : std_logic_vector(0 to nahbmx-1);
begin
v := r; hgrant := (others => '0'); defmst := '0';
haddr := msto(r.hmaster).haddr;
nhmaster := r.hmaster;
arb := '0';
if r.hmasterlock = '0' then
case msto(r.hmaster).htrans is
when HTRANS_IDLE => arb := '1';
when HTRANS_NONSEQ =>
case msto(r.hmaster).hburst is
when HBURST_SINGLE => arb := '1';
when HBURST_INCR => arb := not msto(r.hmaster).hbusreq;
when others =>
end case;
when HTRANS_SEQ =>
case msto(r.hmaster).hburst is
when HBURST_WRAP4 | HBURST_INCR4 => if (fixbrst = 1) and (r.beat(1 downto 0) = "11") then arb := '1'; end if;
when HBURST_WRAP8 | HBURST_INCR8 => if (fixbrst = 1) and (r.beat(2 downto 0) = "111") then arb := '1'; end if;
when HBURST_WRAP16 | HBURST_INCR16 => if (fixbrst = 1) and (r.beat(3 downto 0) = "1111") then arb := '1'; end if;
when HBURST_INCR => arb := not msto(r.hmaster).hbusreq;
when others =>
end case;
when others => arb := '0';
end case;
end if;
if (split /= 0) then
for i in 0 to nahbmx-1 loop
tmpv(i) := (msto(i).htrans(1) or (msto(i).hbusreq)) and not rsplit(i);
end loop;
if (r.defmst and orv(tmpv)) = '1' then arb := '1'; end if;
end if;
if (arb = '1') then selmast(r, msto, rsplit, nhmaster, defmst);
elsif (split /= 0) then defmst := r.defmst; end if;
if (split = 0) or (defmst = '0') then hgrant(nhmaster) := '1'; end if;
-- slave decoding
hsel := (others => '0'); hmbsel := (others => '0');
for i in 0 to nahbs-1 loop
for j in NAHBIR to NAHBCFG-1 loop
area := slvo(i).hconfig(j)(1 downto 0);
case area is
when "10" =>
if ((ioen = 0) or ((IOAREA and IOMSK) /= (haddr(31 downto 20) and IOMSK))) and
((slvo(i).hconfig(j)(31 downto 20) and slvo(i).hconfig(j)(15 downto 4)) =
(haddr(31 downto 20) and slvo(i).hconfig(j)(15 downto 4))) and
(slvo(i).hconfig(j)(15 downto 4) /= "000000000000")
then hsel(i) := '1'; hmbsel(j-NAHBIR) := '1'; end if;
when "11" =>
if ((ioen /= 0) and ((IOAREA and IOMSK) = (haddr(31 downto 20) and IOMSK))) and
((slvo(i).hconfig(j)(31 downto 20) and slvo(i).hconfig(j)(15 downto 4)) =
(haddr(19 downto 8) and slvo(i).hconfig(j)(15 downto 4))) and
(slvo(i).hconfig(j)(15 downto 4) /= "000000000000")
then hsel(i) := '1'; hmbsel(j-NAHBIR) := '1'; end if;
when others =>
end case;
end loop;
end loop;
if r.defmst = '1' then hsel := (others => '0'); end if;
bnslave(0) := hsel(1) or hsel(3) or hsel(5) or hsel(7) or
hsel(9) or hsel(11) or hsel(13) or hsel(15);
bnslave(1) := hsel(2) or hsel(3) or hsel(6) or hsel(7) or
hsel(10) or hsel(11) or hsel(14) or hsel(15);
bnslave(2) := hsel(4) or hsel(5) or hsel(6) or hsel(7) or
hsel(12) or hsel(13) or hsel(14) or hsel(15);
bnslave(3) := hsel(8) or hsel(9) or hsel(10) or hsel(11) or
hsel(12) or hsel(13) or hsel(14) or hsel(15);
nslave := conv_integer(bnslave(SIMAX downto 0));
if ((((IOAREA and IOMSK) = (haddr(31 downto 20) and IOMSK)) and (ioen /= 0))
or ((IOAREA = haddr(31 downto 20)) and (ioen = 0))) and
((CFGAREA and CFGMSK) = (haddr(19 downto 8) and CFGMSK))
and (cfgmask /= 0)
then cfgsel := '1'; hsel := (others => '0');
else cfgsel := '0'; end if;
if (nslave = 0) and (hsel(0) = '0') and (cfgsel = '0') then defslv := '1';
else defslv := '0'; end if;
if r.defmst = '1' then
cfgsel := '0'; defslv := '1';
end if;
-- error respons on undecoded area
v.hready := '0';
hready := slvo(r.hslave).hready; hresp := slvo(r.hslave).hresp;
if r.defslv = '1' then
-- default slave
if (r.htrans = HTRANS_IDLE) or (r.htrans = HTRANS_BUSY) then
hresp := HRESP_OKAY; hready := '1';
else
-- return two-cycle error in case of unimplemented slave access
hresp := HRESP_ERROR; hready := r.hready; v.hready := not r.hready;
end if;
end if;
hrdata := slvo(r.hslave).hrdata;
if cfgmask /= 0 then
-- v.hrdatam := msto(conv_integer(r.haddr(MIMAX+5 downto 5))).hconfig(conv_integer(r.haddr(4 downto 2)));
-- if r.haddr(11 downto MIMAX+6) /= zero32(11 downto MIMAX+6) then v.hrdatam := (others => '0'); end if;
-- if (r.haddr(10 downto MIMAX+6) = zero32(10 downto MIMAX+6)) and (r.haddr(4 downto 2) = "000")
if FULLPNP then hconfndx := conv_integer(r.haddr(4 downto 2)); else hconfndx := 0; end if;
if (r.haddr(10 downto MIMAX+6) = zero32(10 downto MIMAX+6)) and (FULLPNP or (r.haddr(4 downto 2) = "000"))
then v.hrdatam := msto(conv_integer(r.haddr(MIMAX+5 downto 5))).hconfig(hconfndx);
else v.hrdatam := (others => '0'); end if;
-- v.hrdatas := slvo(conv_integer(r.haddr(SIMAX+5 downto 5))).hconfig(conv_integer(r.haddr(4 downto 2)));
-- if r.haddr(11 downto SIMAX+6) /= ('1' & zero32(10 downto SIMAX+6)) then v.hrdatas := (others => '0'); end if;
--if (r.haddr(10 downto SIMAX+6) = zero32(10 downto SIMAX+6)) and
if (r.haddr(10 downto SIMAX+6) = zero32(10 downto SIMAX+6)) and
(FULLPNP or (r.haddr(4 downto 2) = "000") or (r.haddr(4) = '1'))
then v.hrdatas := slvo(conv_integer(r.haddr(SIMAX+5 downto 5))).hconfig(conv_integer(r.haddr(4 downto 2)));
else v.hrdatas := (others => '0'); end if;
if r.haddr(10 downto 4) = "1111111" then
v.hrdatas(15 downto 0) := conv_std_logic_vector(LIBVHDL_BUILD, 16);
v.hrdatas(31 downto 16) := conv_std_logic_vector(devid, 16);
end if;
if r.cfgsel = '1' then
hrdata := (others => '0');
-- default slave
if (r.htrans = HTRANS_IDLE) or (r.htrans = HTRANS_BUSY) then
hresp := HRESP_OKAY; hready := '1';
else
-- return two-cycle read/write respons
hresp := HRESP_OKAY; hready := r.hready; v.hready := not r.hready;
end if;
if r.cfga11 = '0' then hrdata := r.hrdatam;
else hrdata := r.hrdatas; end if;
end if;
end if;
-- latch active master and slave
if hready = '1' then
v.hmaster := nhmaster; v.hmasterd := r.hmaster;
v.hmasterlock := msto(nhmaster).hlock; v.hslave := nslave; v.defslv := defslv;
if (split = 0) or (r.defmst = '0') then v.htrans := msto(r.hmaster).htrans;
else v.htrans := HTRANS_IDLE; end if;
v.cfgsel := cfgsel;
v.cfga11 := msto(r.hmaster).haddr(11);
v.haddr := msto(r.hmaster).haddr(15 downto 2);
if (msto(r.hmaster).htrans = HTRANS_NONSEQ) or (msto(r.hmaster).htrans = HTRANS_IDLE) then
v.beat := "0001";
elsif (msto(r.hmaster).htrans = HTRANS_SEQ) then
if (fixbrst = 1) then v.beat := r.beat + 1; end if;
end if;
if (split /= 0) then v.defmst := defmst; end if;
end if;
-- split support
vsplit := (others => '0');
if SPLIT /= 0 then
vsplit := rsplit;
if slvo(r.hslave).hresp = HRESP_SPLIT then vsplit(r.hmasterd) := '1'; end if;
for i in 0 to nahbs-1 loop
for j in 0 to nahbmx-1 loop
vsplit(j) := vsplit(j) and not slvo(i).hsplit(j);
end loop;
end loop;
end if;
if r.cfgsel = '1' then hcache := '1'; else hcache := slvo(v.hslave).hcache; end if;
-- interrupt merging
hirq := (others => '0');
if disirq = 0 then
for i in 0 to nahbs-1 loop hirq := hirq or slvo(i).hirq; end loop;
for i in 0 to nahbm-1 loop hirq := hirq or msto(i).hirq; end loop;
end if;
if (split = 0) or (r.defmst = '0') then
vslvi.haddr := haddr;
vslvi.htrans := msto(r.hmaster).htrans;
vslvi.hwrite := msto(r.hmaster).hwrite;
vslvi.hsize := msto(r.hmaster).hsize;
vslvi.hburst := msto(r.hmaster).hburst;
vslvi.hready := hready;
vslvi.hwdata := msto(r.hmasterd).hwdata;
vslvi.hprot := msto(r.hmaster).hprot;
vslvi.hmastlock := msto(r.hmaster).hlock;
vslvi.hmaster := conv_std_logic_vector(r.hmaster, 4);
vslvi.hsel := hsel(0 to NAHBSLV-1);
vslvi.hmbsel := hmbsel;
vslvi.hcache := hcache;
vslvi.hirq := hirq;
else
vslvi := ahbs_in_none;
vslvi.hready := hready;
vslvi.hwdata := msto(r.hmasterd).hwdata;
vslvi.hirq := hirq;
end if;
vslvi.testen := testen;
vslvi.testrst := testrst;
vslvi.scanen := scanen and testen;
vslvi.testoen := testoen;
-- reset operation
if (rst = '0') then
v.hmaster := 0; v.hmasterlock := '0'; vsplit := (others => '0');
v.htrans := HTRANS_IDLE; v.defslv := '0'; -- v.beat := "0001";
v.hslave := 0; v.cfgsel := '0'; v.defmst := '0';
end if;
-- drive master inputs
msti.hgrant <= hgrant;
msti.hready <= hready;
msti.hresp <= hresp;
msti.hrdata <= hrdata;
msti.hcache <= hcache;
msti.hirq <= hirq;
msti.testen <= testen;
msti.testrst <= testrst;
msti.scanen <= scanen and testen;
msti.testoen <= testoen;
-- drive slave inputs
slvi <= vslvi;
-- pragma translate_off
--drive internal signals to bus monitor
lslvi <= vslvi;
lmsti.hgrant <= hgrant;
lmsti.hready <= hready;
lmsti.hresp <= hresp;
lmsti.hrdata <= hrdata;
lmsti.hcache <= hcache;
lmsti.hirq <= hirq;
-- pragma translate_on
rin <= v; rsplitin <= vsplit;
end process;
reg0 : process(clk)
begin
if rising_edge(clk) then r <= rin; end if;
if (split = 0) then r.defmst <= '0'; end if;
end process;
splitreg : if SPLIT /= 0 generate
reg1 : process(clk)
begin if rising_edge(clk) then rsplit <= rsplitin; end if; end process;
end generate;
nosplitreg : if SPLIT = 0 generate
rsplit <= (others => '0');
end generate;
-- pragma translate_off
-- diag : process
-- variable k : integer;
-- variable mask : std_logic_vector(11 downto 0);
-- variable iostart : std_logic_vector(11 downto 0) := IOAREA and IOMSK;
-- variable cfgstart : std_logic_vector(11 downto 0) := CFGAREA and CFGMSK;
-- begin
-- wait for 2 ns;
-- k := 0; mask := IOMSK;
-- while (k<12) and (mask(k) = '0') loop k := k+1; end loop;
-- print("ahbctrl: AHB arbiter/multiplexer rev 1");
-- if ioen /= 0 then
-- print("ahbctrl: Common I/O area at " & tost(iostart) & "00000, " & tost(2**k) & " Mbyte");
-- else
-- print("ahbctrl: Common I/O area disabled");
-- end if;
-- if cfgmask /= 0 then
-- print("ahbctrl: Configuration area at " & tost(iostart & cfgstart) & "00, 4 kbyte");
-- else
-- print("ahbctrl: Configuration area disabled");
-- end if;
-- wait;
-- end process;
mon0 : if enbusmon /= 0 generate
mon : ahbmon
generic map(
asserterr => asserterr,
assertwarn => assertwarn,
hmstdisable => hmstdisable,
hslvdisable => hslvdisable,
arbdisable => arbdisable,
nahbm => nahbm,
nahbs => nahbs)
port map(
rst => rst,
clk => clk,
ahbmi => lmsti,
ahbmo => msto,
ahbsi => lslvi,
ahbso => slvo,
err => open);
end generate;
diag : process
variable k : integer;
variable mask : std_logic_vector(11 downto 0);
variable device : std_logic_vector(11 downto 0);
variable devicei : integer;
variable vendor : std_logic_vector( 7 downto 0);
variable area : std_logic_vector( 1 downto 0);
variable vendori : integer;
variable iosize, tmp : integer;
variable iounit : string(1 to 5) := " byte";
variable memtype : string(1 to 9);
variable iostart : std_logic_vector(11 downto 0) := IOAREA and IOMSK;
variable cfgstart : std_logic_vector(11 downto 0) := CFGAREA and CFGMSK;
variable L1 : line := new string'("");
variable S1 : string(1 to 255);
begin
wait for 2 ns;
if debug = 0 then wait; end if;
k := 0; mask := IOMSK;
while (k<12) and (mask(k) = '0') loop k := k+1; end loop;
print("ahbctrl: AHB arbiter/multiplexer rev 1");
if ioen /= 0 then
print("ahbctrl: Common I/O area at " & tost(iostart) & "00000, " & tost(2**k) & " Mbyte");
else
print("ahbctrl: Common I/O area disabled");
end if;
print("ahbctrl: AHB masters: " & tost(nahbm) & ", AHB slaves: " & tost(nahbs));
if cfgmask /= 0 then
print("ahbctrl: Configuration area at " & tost(iostart & cfgstart) & "00, 4 kbyte");
else
print("ahbctrl: Configuration area disabled");
end if;
if debug = 1 then wait; end if;
for i in 0 to nahbm-1 loop
vendor := msto(i).hconfig(0)(31 downto 24);
vendori := conv_integer(vendor);
if vendori /= 0 then
device := msto(i).hconfig(0)(23 downto 12);
devicei := conv_integer(device);
print("ahbctrl: mst" & tost(i) & ": " & iptable(vendori).vendordesc &
iptable(vendori).device_table(devicei));
assert (msto(i).hindex = i) or (icheck = 0)
report "AHB master index error on master " & tost(i) severity failure;
end if;
end loop;
for i in 0 to nahbs-1 loop
vendor := slvo(i).hconfig(0)(31 downto 24);
vendori := conv_integer(vendor);
if vendori /= 0 then
device := slvo(i).hconfig(0)(23 downto 12);
devicei := conv_integer(device);
std.textio.write(L1, "ahbctrl: slv" & tost(i) & ": " & iptable(vendori).vendordesc &
iptable(vendori).device_table(devicei));
std.textio.writeline(OUTPUT, L1);
for j in NAHBIR to NAHBCFG-1 loop
area := slvo(i).hconfig(j)(1 downto 0);
mask := slvo(i).hconfig(j)(15 downto 4);
if (mask /= "000000000000") then
case area is
when "01" =>
when "10" =>
k := 0;
while (k<15) and (mask(k) = '0') loop k := k+1; end loop;
std.textio.write(L1, "ahbctrl: memory at " & tost( slvo(i).hconfig(j)(31 downto 20))&
"00000, size "& tost(2**k) & " Mbyte");
if slvo(i).hconfig(j)(16) = '1' then
std.textio.write(L1, string'(", cacheable"));
end if;
if slvo(i).hconfig(j)(17) = '1' then
std.textio.write(L1, string'(", prefetch"));
end if;
std.textio.writeline(OUTPUT, L1);
when "11" =>
if ioen /= 0 then
k := 0;
while (k<15) and (mask(k) = '0') loop k := k+1; end loop;
iosize := 256 * 2**k; iounit(1) := ' ';
if (iosize > 1023) then
iosize := iosize/1024; iounit(1) := 'k';
end if;
print("ahbctrl: I/O port at " & tost( iostart &
((slvo(i).hconfig(j)(31 downto 20)) and slvo(i).hconfig(j)(15 downto 4))) &
"00, size "& tost(iosize) & iounit);
end if;
when others =>
end case;
end if;
end loop;
assert (slvo(i).hindex = i) or (icheck = 0)
report "AHB slave index error on slave " & tost(i) severity failure;
end if;
end loop;
wait;
end process;
-- pragma translate_on
end;
| mit | 4fe697a80d405f7e0c7d831f868a72b5 | 0.571991 | 3.330462 | false | false | false | false |
impedimentToProgress/UCI-BlueChip | AttackFiles/Attacks/privEsc/lib/gaisler/ddr/ddrsp32a.vhd | 2 | 23,413 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: ddrsp32a
-- File: ddrsp32a.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: 32-bit DDR266 memory controller with asych AHB interface
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
library gaisler;
use grlib.devices.all;
use gaisler.memctrl.all;
library techmap;
use techmap.gencomp.all;
entity ddrsp32a is
generic (
memtech : integer := 0;
hindex : integer := 0;
haddr : integer := 0;
hmask : integer := 16#f00#;
ioaddr : integer := 16#000#;
iomask : integer := 16#fff#;
MHz : integer := 100;
col : integer := 9;
Mbyte : integer := 8;
fast : integer := 0;
pwron : integer := 0;
oepol : integer := 0
);
port (
rst : in std_ulogic;
clk_ddr : in std_ulogic;
clk_ahb : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
sdi : in sdctrl_in_type;
sdo : out sdctrl_out_type
);
end;
architecture rtl of ddrsp32a is
constant REVISION : integer := 0;
constant CMD_PRE : std_logic_vector(2 downto 0) := "010";
constant CMD_REF : std_logic_vector(2 downto 0) := "100";
constant CMD_LMR : std_logic_vector(2 downto 0) := "110";
constant CMD_EMR : std_logic_vector(2 downto 0) := "111";
constant abuf : integer := 6;
constant hconfig : ahb_config_type := (
0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_DDRSP, 0, REVISION, 0),
4 => ahb_membar(haddr, '1', '1', hmask),
5 => ahb_iobar(ioaddr, iomask),
others => zero32);
type mcycletype is (midle, active, ext, leadout);
type ahb_state_type is (midle, rhold, dread, dwrite, whold1, whold2);
type sdcycletype is (act1, act2, act3, rd1, rd2, rd3, rd4, rd5, rd6, rd7, rd8,
wr1, wr2, wr3, wr4a, wr4, wr5, sidle, ioreg1, ioreg2);
type icycletype is (iidle, pre, ref1, ref2, emode, lmode, finish);
-- sdram configuration register
type sdram_cfg_type is record
command : std_logic_vector(2 downto 0);
csize : std_logic_vector(1 downto 0);
bsize : std_logic_vector(2 downto 0);
trcd : std_ulogic; -- tCD : 2/3 clock cycles
trfc : std_logic_vector(2 downto 0);
trp : std_ulogic; -- precharge to activate: 2/3 clock cycles
refresh : std_logic_vector(11 downto 0);
renable : std_ulogic;
dllrst : std_ulogic;
refon : std_ulogic;
cke : std_ulogic;
end record;
type access_param is record
haddr : std_logic_vector(31 downto 0);
size : std_logic_vector(1 downto 0);
hwrite : std_ulogic;
hio : std_ulogic;
end record;
-- local registers
type ahb_reg_type is record
hready : std_ulogic;
hsel : std_ulogic;
hio : std_ulogic;
startsd : std_ulogic;
ready : std_ulogic;
ready2 : std_ulogic;
write : std_logic_vector(1 downto 0);
state : ahb_state_type;
haddr : std_logic_vector(31 downto 0);
hrdata : std_logic_vector(31 downto 0);
hwdata : std_logic_vector(31 downto 0);
hwrite : std_ulogic;
htrans : std_logic_vector(1 downto 0);
hresp : std_logic_vector(1 downto 0);
raddr : std_logic_vector(abuf-1 downto 0);
size : std_logic_vector(1 downto 0);
acc : access_param;
end record;
type ddr_reg_type is record
startsd : std_ulogic;
startsdold : std_ulogic;
burst : std_ulogic;
hready : std_ulogic;
bdrive : std_ulogic;
qdrive : std_ulogic;
nbdrive : std_ulogic;
mstate : mcycletype;
sdstate : sdcycletype;
cmstate : mcycletype;
istate : icycletype;
trfc : std_logic_vector(2 downto 0);
refresh : std_logic_vector(11 downto 0);
sdcsn : std_logic_vector(1 downto 0);
sdwen : std_ulogic;
rasn : std_ulogic;
casn : std_ulogic;
dqm : std_logic_vector(7 downto 0);
address : std_logic_vector(15 downto 2); -- memory address
ba : std_logic_vector(1 downto 0);
waddr : std_logic_vector(abuf-1 downto 0);
cfg : sdram_cfg_type;
hrdata : std_logic_vector(63 downto 0);
end record;
signal vcc : std_ulogic;
signal r, ri : ddr_reg_type;
signal ra, rai : ahb_reg_type;
signal rbdrive, ribdrive : std_logic_vector(31 downto 0);
signal rdata, wdata : std_logic_vector(63 downto 0);
attribute syn_preserve : boolean;
attribute syn_preserve of rbdrive : signal is true;
begin
vcc <= '1';
ahb_ctrl : process(rst, ahbsi, r, ra, rdata)
variable v : ahb_reg_type; -- local variables for registers
variable startsd : std_ulogic;
variable dout : std_logic_vector(31 downto 0);
begin
v := ra; v.hresp := HRESP_OKAY; v.write := "00";
if ra.raddr(0) = '0' then v.hrdata := rdata(63 downto 32);
else v.hrdata := rdata(31 downto 0); end if;
v.ready := not (ra.startsd xor r.startsdold);
v.ready2 := ra.ready;
if ((ahbsi.hready and ahbsi.hsel(hindex)) = '1') then
v.htrans := ahbsi.htrans; v.haddr := ahbsi.haddr;
v.size := ahbsi.hsize(1 downto 0); v.hwrite := ahbsi.hwrite;
if ahbsi.htrans(1) = '1' then
v.hio := ahbsi.hmbsel(1);
v.hsel := '1'; v.hready := '0';
end if;
end if;
if ahbsi.hready = '1' then v.hsel := ahbsi.hsel(hindex); end if;
case ra.state is
when midle =>
if ((v.hsel and v.htrans(1)) = '1') then
if v.hwrite = '0' then
v.state := rhold; v.startsd := not ra.startsd;
else
v.state := dwrite; v.hready := '1';
v.write(0) := not v.haddr(2); v.write(1) := v.haddr(2);
end if;
end if;
v.raddr := ra.haddr(7 downto 2);
v.ready := '0'; v.ready2 := '0';
if ahbsi.hready = '1' then
v.acc := (v.haddr, v.size, v.hwrite, v.hio);
end if;
when rhold =>
v.raddr := ra.haddr(7 downto 2);
if ra.ready2 = '1' then
v.state := dread; v.hready := '1'; v.raddr := ra.raddr + 1;
end if;
when dread =>
v.raddr := ra.raddr + 1; v.hready := '1';
if ((v.hsel and v.htrans(1) and v.htrans(0)) = '0') or
(ra.raddr(2 downto 0) = "000")
then v.state := midle; v.hready := '0'; end if;
v.acc := (v.haddr, v.size, v.hwrite, v.hio);
when dwrite =>
v.raddr := ra.haddr(7 downto 2); v.hready := '1';
v.write(0) := not v.haddr(2); v.write(1) := v.haddr(2);
if ((v.hsel and v.htrans(1) and v.htrans(0)) = '0') or
(ra.haddr(4 downto 2) = "111")
then
v.startsd := not ra.startsd; v.state := whold1;
v.write := "00"; v.hready := '0';
end if;
when whold1 =>
v.state := whold2; v.ready := '0';
when whold2 =>
if ra.ready = '1' then
v.state := midle; v.acc := (v.haddr, v.size, v.hwrite, v.hio);
end if;
end case;
v.hwdata := ahbsi.hwdata;
if (ahbsi.hready and ahbsi.hsel(hindex) ) = '1' then
if ahbsi.htrans(1) = '0' then v.hready := '1'; end if;
end if;
dout := ra.hrdata(31 downto 0);
if rst = '0' then
v.hsel := '0';
v.hready := '1';
v.state := midle;
v.startsd := '0';
v.hio := '0';
end if;
rai <= v;
ahbso.hready <= ra.hready;
ahbso.hresp <= ra.hresp;
ahbso.hrdata <= dout;
ahbso.hcache <= not ra.hio;
end process;
ddr_ctrl : process(rst, r, ra, sdi, rbdrive, wdata)
variable v : ddr_reg_type; -- local variables for registers
variable startsd : std_ulogic;
variable dqm : std_logic_vector(7 downto 0);
variable raddr : std_logic_vector(13 downto 0);
variable adec : std_ulogic;
variable rams : std_logic_vector(1 downto 0);
variable ba : std_logic_vector(1 downto 0);
variable haddr : std_logic_vector(31 downto 0);
variable hsize : std_logic_vector(1 downto 0);
variable hwrite : std_ulogic;
variable htrans : std_logic_vector(1 downto 0);
variable hready : std_ulogic;
variable vbdrive : std_logic_vector(31 downto 0);
variable bdrive : std_ulogic;
variable writecfg: std_ulogic;
variable regsd1 : std_logic_vector(31 downto 0); -- data from registers
variable regsd2 : std_logic_vector(31 downto 0); -- data from registers
begin
-- Variable default settings to avoid latches
v := r; v.hready := '0'; writecfg := '0'; vbdrive := rbdrive;
v.hrdata := sdi.data(63 downto 0); v.qdrive :='0';
regsd1 := (others => '0');
regsd1(31 downto 15) := r.cfg.refon & r.cfg.trp & r.cfg.trfc &
r.cfg.trcd & r.cfg.bsize & r.cfg.csize & r.cfg.command &
r.cfg.dllrst & r.cfg.renable & r.cfg.cke;
regsd1(11 downto 0) := r.cfg.refresh;
regsd2 := (others => '0');
regsd2(8 downto 0) := conv_std_logic_vector(MHz, 9);
regsd2(14 downto 12) := conv_std_logic_vector(2, 3);
-- generate DQM from address and write size
case ra.acc.size is
when "00" =>
case ra.acc.haddr(2 downto 0) is
when "000" => dqm := "01111111";
when "001" => dqm := "10111111";
when "010" => dqm := "11011111";
when "011" => dqm := "11101111";
when "100" => dqm := "11110111";
when "101" => dqm := "11111011";
when "110" => dqm := "11111101";
when others => dqm := "11111110";
end case;
when "01" =>
case ra.acc.haddr(2 downto 1) is
when "00" => dqm := "00111111";
when "01" => dqm := "11001111";
when "10" => dqm := "11110011";
when others => dqm := "11111100";
end case;
when others => dqm := "00000000";
end case;
v.startsd := ra.startsd;
-- main FSM
case r.mstate is
when midle =>
if r.startsd = '1' then
if (r.sdstate = sidle) and (r.cfg.command = "000") and
(r.cmstate = midle)
then
startsd := '1'; v.mstate := active;
end if;
end if;
when others => null;
end case;
startsd := r.startsd xor r.startsdold;
-- generate row and column address size
haddr := ra.acc.haddr;
haddr(31 downto 20) := haddr(31 downto 20) and not conv_std_logic_vector(hmask, 12);
case r.cfg.csize is
when "00" => raddr := haddr(24 downto 11);
when "01" => raddr := haddr(25 downto 12);
when "10" => raddr := haddr(26 downto 13);
when others => raddr := haddr(27 downto 14);
end case;
-- generate bank address
ba := genmux(r.cfg.bsize, haddr(29 downto 22)) &
genmux(r.cfg.bsize, haddr(28 downto 21));
-- generate chip select
adec := genmux(r.cfg.bsize, haddr(30 downto 23));
rams := adec & not adec;
-- sdram access FSM
if r.trfc /= "000" then v.trfc := r.trfc - 1; end if;
case r.sdstate is
when sidle =>
if (startsd = '1') and (r.cfg.command = "000") and (r.cmstate = midle)
and (r.istate = finish)
then
v.address := raddr; v.ba := ba;
if ra.acc.hio = '0' then
v.sdcsn := not rams(1 downto 0); v.rasn := '0'; v.sdstate := act1;
else v.sdstate := ioreg1; end if;
end if;
v.waddr := ra.acc.haddr(7 downto 2);
when act1 =>
v.rasn := '1'; v.trfc := r.cfg.trfc;
if r.cfg.trcd = '1' then v.sdstate := act2; else
v.sdstate := act3; v.hready := ra.acc.hwrite;
end if;
v.waddr := ra.acc.haddr(7 downto 2);
when act2 =>
v.sdstate := act3; v.hready := ra.acc.hwrite;
when act3 =>
v.casn := '0';
v.address := ra.acc.haddr(14 downto 12) & '0' & ra.acc.haddr(11 downto 3) & '0';
v.dqm := dqm;
if ra.acc.hwrite = '1' then
v.waddr := r.waddr + 2; v.waddr(0) := '0';
v.sdstate := wr1; v.sdwen := '0'; v.bdrive := '0'; v.qdrive := '1';
if (r.waddr /= ra.raddr) then v.hready := '1';
if r.waddr(0) = '1' then v.dqm(7 downto 4) := (others => '1'); end if;
else
if r.waddr(0) = '0' then v.dqm(3 downto 0) := (others => '1');
else v.dqm(7 downto 4) := (others => '1'); end if;
end if;
else v.sdstate := rd1; end if;
when wr1 =>
v.sdwen := '1'; v.casn := '1'; v.qdrive := '1';
v.waddr := r.waddr + 2; v.dqm(7 downto 4) := (others => '0');
v.address(8 downto 3) := r.waddr;
if (r.waddr <= ra.raddr) and (r.waddr(5 downto 1) /= "00000") and (r.hready = '1')
then
v.hready := '1';
if (r.hready = '1') and (r.waddr(2 downto 0) = "000") then
v.sdwen := '0'; v.casn := '0';
end if;
if (r.waddr = ra.raddr) and (r.waddr /= "000000") and (r.waddr(0) = '0') then
v.dqm(3 downto 0) := (others => '1');
end if;
else
v.sdstate := wr2;
v.dqm := (others => '1'); --v.bdrive := '1';
v.startsdold := r.startsd;
end if;
when wr2 =>
v.sdstate := wr3; v.qdrive := '1';
when wr3 =>
v.sdstate := wr4a; v.qdrive := '1';
when wr4a =>
v.bdrive := '1';
v.rasn := '0'; v.sdwen := '0'; v.sdstate := wr4; v.qdrive := '1';
when wr4 =>
v.sdcsn := "11"; v.rasn := '1'; v.sdwen := '1'; v.qdrive := '0';
v.sdstate := wr5;
when wr5 =>
v.sdstate := sidle;
when rd1 =>
v.casn := '1'; v.sdstate := rd7;
-- if ra.acc.haddr(4 downto 2) = "011" then
-- v.casn := '0'; v.burst := '1'; v.address(5 downto 3) := "100";
-- end if;
when rd7 =>
v.casn := '1'; v.sdstate := rd2;
-- if ra.acc.haddr(4 downto 2) = "010" then
-- v.casn := '0'; v.burst := '1'; v.address(5 downto 3) := "100";
-- end if;
when rd2 =>
v.casn := '1'; v.sdstate := rd3;
-- if ra.acc.haddr(4 downto 2) = "001" then
-- v.casn := '0'; v.burst := '1'; v.address(5 downto 3) := "100";
-- end if;
-- if v.sdwen = '0' then v.dqm := (others => '1'); end if;
when rd3 =>
if fast = 0 then v.startsdold := r.startsd; end if;
v.sdstate := rd4; v.hready := '1'; v.casn := '1';
-- if r.sdwen = '0' then
-- v.rasn := '1'; v.sdwen := '1'; v.sdcsn := "11"; v.dqm := (others => '1');
-- elsif ra.acc.haddr(4 downto 2) = "000" then
-- v.casn := '0'; v.burst := '1'; v.address(5) := '1';
-- v.waddr := v.address(8 downto 3);
-- end if;
if v.hready = '1' then v.waddr := r.waddr + 2; end if;
when rd4 =>
v.hready := '1'; v.casn := '1';
-- if (r.sdcsn /= "11") and (r.waddr(1 downto 0) = "11") and (r.burst = '1')
-- then
-- v.burst := '0';
if (r.sdcsn = "11") or (r.waddr(2 downto 1) = "11") then
v.dqm := (others => '1'); v.burst := '0';
if fast /= 0 then v.startsdold := r.startsd; end if;
if (r.sdcsn /= "11") then
v.rasn := '0'; v.sdwen := '0'; v.sdstate := rd5;
else
if r.cfg.trp = '1' then v.sdstate := rd6;
else v.sdstate := sidle; end if;
end if;
end if;
if v.hready = '1' then v.waddr := r.waddr + 2; end if;
when rd5 =>
if r.cfg.trp = '1' then v.sdstate := rd6;
else v.sdstate := sidle; end if;
v.sdcsn := (others => '1'); v.rasn := '1'; v.sdwen := '1';
v.dqm := (others => '1');
when rd6 =>
v.sdstate := sidle; v.dqm := (others => '1');
v.sdcsn := (others => '1'); v.rasn := '1'; v.sdwen := '1';
when ioreg1 =>
v.hrdata := regsd1 & regsd2; v.sdstate := ioreg2;
if ra.acc.hwrite = '0' then v.hready := '1'; end if;
when ioreg2 =>
writecfg := ra.acc.hwrite and not r.waddr(0); v.startsdold := r.startsd;
v.sdstate := sidle;
when others =>
v.sdstate := sidle;
end case;
-- sdram commands
case r.cmstate is
when midle =>
if r.sdstate = sidle then
case r.cfg.command is
when CMD_PRE => -- precharge
v.sdcsn := (others => '0'); v.rasn := '0'; v.sdwen := '0';
v.address(12) := '1'; v.cmstate := active;
when CMD_REF => -- auto-refresh
v.sdcsn := (others => '0'); v.rasn := '0'; v.casn := '0';
v.cmstate := active;
when CMD_EMR => -- load-ext-mode-reg
v.sdcsn := (others => '0'); v.rasn := '0'; v.casn := '0';
v.sdwen := '0'; v.cmstate := active; v.ba := "01";
v.address := "00000000000000";
when CMD_LMR => -- load-mode-reg
v.sdcsn := (others => '0'); v.rasn := '0'; v.casn := '0';
v.sdwen := '0'; v.cmstate := active; v.ba := "00";
v.address := "00000" & r.cfg.dllrst & "0" & "01" & "00011";
when others => null;
end case;
end if;
when active =>
v.sdcsn := (others => '1'); v.rasn := '1'; v.casn := '1';
v.sdwen := '1'; v.cfg.command := "000";
v.cmstate := leadout; v.trfc := r.cfg.trfc;
when others =>
if r.trfc = "000" then v.cmstate := midle; end if;
end case;
-- sdram init
case r.istate is
when iidle =>
if r.cfg.renable = '1' then
v.cfg.cke := '1'; v.cfg.dllrst := '1';
if r.cfg.cke = '1' then v.istate := pre; v.cfg.command := CMD_PRE; end if;
end if;
when pre =>
if r.cfg.command = "000" then
v.cfg.command := "11" & r.cfg.dllrst; -- CMD_LMR/CMD_EMR
if r.cfg.dllrst = '1' then v.istate := emode; else v.istate := lmode; end if;
end if;
when emode =>
if r.cfg.command = "000" then
v.istate := lmode; v.cfg.command := CMD_LMR;
end if;
when lmode =>
if r.cfg.command = "000" then
if r.cfg.dllrst = '1' then
if r.refresh(9 downto 8) = "00" then -- > 200 clocks delay
v.cfg.command := CMD_PRE; v.istate := ref1;
end if;
else
v.istate := finish; --v.cfg.command := CMD_LMR;
v.cfg.refon := '1'; v.cfg.renable := '0';
end if;
end if;
when ref1 =>
if r.cfg.command = "000" then
v.cfg.command := CMD_REF; v.cfg.dllrst := '0'; v.istate := ref2;
end if;
when ref2 =>
if r.cfg.command = "000" then
v.cfg.command := CMD_REF; v.istate := pre;
end if;
when others =>
if r.cfg.renable = '1' then
v.istate := iidle; v.cfg.dllrst := '1';
end if;
end case;
-- second part of main fsm
case r.mstate is
when active =>
if v.hready = '1' then
v.mstate := midle;
end if;
when others => null;
end case;
-- sdram refresh counter
if ((r.cfg.refon = '1') and (r.istate = finish)) or
(r.cfg.dllrst = '1')
then
v.refresh := r.refresh - 1;
if (v.refresh(11) and not r.refresh(11)) = '1' then
v.refresh := r.cfg.refresh;
if r.cfg.dllrst = '0' then v.cfg.command := "100"; end if;
end if;
end if;
-- AHB register access
if (ra.acc.hio and ra.acc.hwrite and writecfg) = '1' then
v.cfg.refresh := wdata(11+32 downto 0+32);
v.cfg.cke := wdata(15+32);
v.cfg.renable := wdata(16+32);
v.cfg.dllrst := wdata(17+32);
v.cfg.command := wdata(20+32 downto 18+32);
v.cfg.csize := wdata(22+32 downto 21+32);
v.cfg.bsize := wdata(25+32 downto 23+32);
v.cfg.trcd := wdata(26+32);
v.cfg.trfc := wdata(29+32 downto 27+32);
v.cfg.trp := wdata(30+32);
v.cfg.refon := wdata(31+32);
end if;
v.nbdrive := not v.bdrive;
if oepol = 1 then bdrive := r.nbdrive; vbdrive := (others => v.nbdrive);
else bdrive := r.bdrive; vbdrive := (others => v.bdrive);end if;
-- reset
if rst = '0' then
v.sdstate := sidle;
v.mstate := midle;
v.istate := finish;
v.cmstate := midle;
v.cfg.command := "000";
v.cfg.csize := conv_std_logic_vector(col-9, 2);
v.cfg.bsize := conv_std_logic_vector(log2(Mbyte/8), 3);
if MHz > 100 then v.cfg.trcd := '1'; else v.cfg.trcd := '0'; end if;
v.cfg.refon := '0';
v.cfg.trfc := conv_std_logic_vector(75*MHz/1000-2, 3);
v.cfg.refresh := conv_std_logic_vector(7800*MHz/1000, 12);
v.refresh := (others => '0');
if pwron = 1 then v.cfg.renable := '1';
else v.cfg.renable := '0'; end if;
if MHz > 100 then v.cfg.trp := '1'; else v.cfg.trp := '0'; end if;
v.dqm := (others => '1');
v.sdwen := '1';
v.rasn := '1';
v.casn := '1';
v.hready := '0';
v.startsd := '0';
v.startsdold := '0';
v.cfg.dllrst := '0';
v.cfg.cke := '0';
end if;
ri <= v;
ribdrive <= vbdrive;
end process;
sdo.sdcke <= (others => r.cfg.cke);
ahbso.hconfig <= hconfig;
ahbso.hirq <= (others => '0');
ahbso.hindex <= hindex;
ahbregs : process(clk_ahb) begin
if rising_edge(clk_ahb) then
ra <= rai;
end if;
end process;
ddrregs : process(clk_ddr, rst) begin
if rising_edge(clk_ddr) then
r <= ri; rbdrive <= ribdrive;
end if;
if (rst = '0') then
r.sdcsn <= (others => '1'); r.bdrive <= '1'; r.nbdrive <= '0';
if oepol = 0 then rbdrive <= (others => '1');
else rbdrive <= (others => '0'); end if;
r.cfg.cke <= '0';
end if;
end process;
sdo.address <= '0' & ri.address;
sdo.ba <= ri.ba;
sdo.bdrive <= r.nbdrive when oepol = 1 else r.bdrive;
sdo.qdrive <= not (ri.qdrive or r.nbdrive);
sdo.vbdrive <= rbdrive;
sdo.sdcsn <= ri.sdcsn;
sdo.sdwen <= ri.sdwen;
sdo.dqm <= "11111111" & r.dqm;
sdo.rasn <= ri.rasn;
sdo.casn <= ri.casn;
sdo.data <= zero32 & zero32 & wdata;
read_buff : syncram_2p
generic map (tech => memtech, abits => 5, dbits => 64, sepclk => 1, wrfst => 0)
port map ( rclk => clk_ahb, renable => vcc, raddress => rai.raddr(5 downto 1),
dataout => rdata, wclk => clk_ddr, write => ri.hready,
waddress => r.waddr(5 downto 1), datain => ri.hrdata);
write_buff1 : syncram_2p
generic map (tech => memtech, abits => 5, dbits => 32, sepclk => 1, wrfst => 0)
port map ( rclk => clk_ddr, renable => vcc, raddress => r.waddr(5 downto 1),
dataout => wdata(63 downto 32), wclk => clk_ahb, write => ra.write(0),
waddress => ra.haddr(7 downto 3), datain => ahbsi.hwdata);
write_buff2 : syncram_2p
generic map (tech => memtech, abits => 5, dbits => 32, sepclk => 1, wrfst => 0)
port map ( rclk => clk_ddr, renable => vcc, raddress => r.waddr(5 downto 1),
dataout => wdata(31 downto 0), wclk => clk_ahb, write => ra.write(1),
waddress => ra.haddr(7 downto 3), datain => ahbsi.hwdata);
-- pragma translate_off
bootmsg : report_version
generic map (
msg1 => "ddrsp" & tost(hindex) & ": 32-bit DDR266 controller rev " &
tost(REVISION) & ", " & tost(Mbyte) & " Mbyte, " & tost(MHz) &
" MHz DDR clock");
-- pragma translate_on
end;
| mit | 4241df6fc411e3afe4354319d68f441f | 0.544099 | 3.056527 | false | false | false | false |
franz/pocl | examples/accel/rtl/platform/xilinx_blockram.vhdl | 2 | 5,915 | -- Copyright (c) 2017 Tampere University
--
-- Permission is hereby granted, free of charge, to any person obtaining a
-- copy of this software and associated documentation files (the "Software"),
-- to deal in the Software without restriction, including without limitation
-- the rights to use, copy, modify, merge, publish, distribute, sublicense,
-- and/or sell copies of the Software, and to permit persons to whom the
-- Software is furnished to do so, subject to the following conditions:
--
-- The above copyright notice and this permission notice shall be included in
-- all copies or substantial portions of the Software.
--
-- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-- AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
-- FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
-- DEALINGS IN THE SOFTWARE.
-------------------------------------------------------------------------------
-- Title : Xilinx BRAM model with handshaking
-- Project :
-------------------------------------------------------------------------------
-- File : xilinx_blockram.vhdl
-- Author : Aleksi Tervo
-- Company : Tampere University
-- Created : 2017-06-01
-- Last update: 2017-06-01
-- Platform :
-- Standard : VHDL'93
-------------------------------------------------------------------------------
-- Description: Parametric-width byte strobe memory with handshaking
-- which infers BRAM on (at least) Xilinx Series 7 FPGAs
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2017-06-01 1.0 tervoa Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use std.textio.all;
use ieee.numeric_std.all;
entity xilinx_blockram is generic (
addrw_g : integer := 10;
dataw_g : integer := 32);
port (
clk : in std_logic;
rstx : in std_logic;
-- Access channel
avalid_in : in std_logic;
aready_out : out std_logic;
aaddr_in : in std_logic_vector(addrw_g-1 downto 0);
awren_in : in std_logic;
astrb_in : in std_logic_vector((dataw_g+7)/8-1 downto 0);
adata_in : in std_logic_vector(dataw_g-1 downto 0);
-- Read channel
rvalid_out : out std_logic;
rready_in : in std_logic;
rdata_out : out std_logic_vector(dataw_g-1 downto 0)
);
end xilinx_blockram;
architecture rtl of xilinx_blockram is
constant dataw_padded_c : integer := ((dataw_g+7)/8)*8;
constant astrb_width_c : integer := (dataw_g+7)/8;
signal ram_addr : unsigned(addrw_g-1 downto 0);
signal ram_write_data : std_logic_vector(dataw_padded_c-1 downto 0);
signal ram_read_data_r : std_logic_vector(dataw_padded_c-1 downto 0);
signal ram_enable : std_logic;
signal ram_strb : std_logic_vector(astrb_width_c-1 downto 0);
constant adata_padding : std_logic_vector(dataw_padded_c-dataw_g-1 downto 0)
:= (others => '0');
signal adata_padded : std_logic_vector(dataw_padded_c-1 downto 0);
signal aready_r : std_logic;
signal live_read : std_logic;
signal live_read_r : std_logic;
signal read_data_r : std_logic_vector(dataw_padded_c-1 downto 0);
signal read_data_valid_r : std_logic;
signal rvalid : std_logic;
type ram_type is array (2**addrw_g-1 downto 0) of std_logic_vector
(dataw_padded_c-1 downto 0);
signal RAM_ARR : ram_type;
begin
control_comb : process(aaddr_in, avalid_in, aready_r, awren_in, astrb_in,
live_read_r, read_data_valid_r)
begin
if avalid_in = '1' and aready_r = '1' then
ram_enable <= '1';
if awren_in = '1' then
ram_strb <= astrb_in;
live_read <= '0';
else
ram_strb <= (others => '0');
live_read <= '1';
end if;
else
ram_strb <= (others => '0');
ram_enable <= '0';
live_read <= '0';
end if;
ram_addr <= unsigned(aaddr_in);
rvalid <= live_read_r or read_data_valid_r;
end process;
control_sync : process(clk, rstx)
begin
if rstx = '0' then
live_read_r <= '0';
aready_r <= '0';
read_data_valid_r <= '0';
read_data_r <= (others => '0');
elsif rising_edge(clk) then
if rvalid = '1' and rready_in = '1' then
read_data_valid_r <= '0';
end if;
if rvalid = '1' and rready_in = '0' then
aready_r <= '0';
else
aready_r <= '1';
end if;
live_read_r <= live_read or live_read_r;
if live_read_r = '1' and (rready_in = '1' or read_data_valid_r = '0') then
live_read_r <= live_read;
if rready_in = '0' or read_data_valid_r = '1' then
read_data_valid_r <= '1';
read_data_r <= ram_read_data_r;
end if;
end if;
end if;
end process;
adata_padded <= adata_padding & adata_in;
RAM : process(clk)
begin
if rising_edge(clk) then
if ram_enable = '1' then
for i in 0 to astrb_width_c-1 loop
if ram_strb(i) = '1' then
RAM_ARR(to_integer(ram_addr))((i+1)*8-1 downto i*8)
<= adata_padded((i+1)*8-1 downto i*8);
end if;
end loop;
ram_read_data_r <= RAM_ARR(to_integer(ram_addr));
end if;
end if;
end process;
rdata_out <= ram_read_data_r(rdata_out'range) when read_data_valid_r = '0'
else read_data_r(rdata_out'range);
rvalid_out <= rvalid;
aready_out <= aready_r;
end rtl;
| mit | 547ee201811208b2a1f23222b8d5a584 | 0.566019 | 3.479412 | false | false | false | false |
impedimentToProgress/UCI-BlueChip | AttackFiles/Attacks/privEsc/lib/gaisler/leon3/iu3.vhd | 1 | 114,133 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: iu3
-- File: iu3.vhd
-- Author: Jiri Gaisler, Edvin Catovic, Gaisler Research
-- Description: LEON3 7-stage integer pipline
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library grlib;
use grlib.sparc.all;
use grlib.stdlib.all;
library techmap;
use techmap.gencomp.all;
library gaisler;
use gaisler.leon3.all;
use gaisler.libiu.all;
use gaisler.arith.all;
-- pragma translate_off
use grlib.sparc_disas.all;
-- pragma translate_on
entity iu3 is
generic (
nwin : integer range 2 to 32 := 8;
isets : integer range 1 to 4 := 1;
dsets : integer range 1 to 4 := 1;
fpu : integer range 0 to 15 := 0;
v8 : integer range 0 to 63 := 0;
cp, mac : integer range 0 to 1 := 0;
dsu : integer range 0 to 1 := 0;
nwp : integer range 0 to 4 := 0;
pclow : integer range 0 to 2 := 2;
notag : integer range 0 to 1 := 0;
index : integer range 0 to 15:= 0;
lddel : integer range 1 to 2 := 2;
irfwt : integer range 0 to 1 := 0;
disas : integer range 0 to 2 := 0;
tbuf : integer range 0 to 64 := 0; -- trace buf size in kB (0 - no trace buffer)
pwd : integer range 0 to 2 := 0; -- power-down
svt : integer range 0 to 1 := 0; -- single-vector trapping
rstaddr : integer := 16#00000#; -- reset vector MSB address
smp : integer range 0 to 15 := 0; -- support SMP systems
fabtech : integer range 0 to NTECH := 0;
clk2x : integer := 0
);
port (
clk : in std_ulogic;
rstn : in std_ulogic;
holdn : in std_ulogic;
ici : out icache_in_type;
ico : in icache_out_type;
dci : out dcache_in_type;
dco : in dcache_out_type;
rfi : out iregfile_in_type;
rfo : in iregfile_out_type;
irqi : in l3_irq_in_type;
irqo : out l3_irq_out_type;
dbgi : in l3_debug_in_type;
dbgo : out l3_debug_out_type;
muli : out mul32_in_type;
mulo : in mul32_out_type;
divi : out div32_in_type;
divo : in div32_out_type;
fpo : in fpc_out_type;
fpi : out fpc_in_type;
cpo : in fpc_out_type;
cpi : out fpc_in_type;
tbo : in tracebuf_out_type;
tbi : out tracebuf_in_type;
sclk : in std_ulogic;
hackVector : out std_logic_vector(7 downto 0)
);
end;
architecture rtl of iu3 is
constant ISETMSB : integer := log2x(isets)-1;
constant DSETMSB : integer := log2x(dsets)-1;
constant RFBITS : integer range 6 to 10 := log2(NWIN+1) + 4;
constant NWINLOG2 : integer range 1 to 5 := log2(NWIN);
constant CWPOPT : boolean := (NWIN = (2**NWINLOG2));
constant CWPMIN : std_logic_vector(NWINLOG2-1 downto 0) := (others => '0');
constant CWPMAX : std_logic_vector(NWINLOG2-1 downto 0) :=
conv_std_logic_vector(NWIN-1, NWINLOG2);
constant FPEN : boolean := (fpu /= 0);
constant CPEN : boolean := (cp = 1);
constant MULEN : boolean := (v8 /= 0);
constant MULTYPE: integer := (v8 / 16);
constant DIVEN : boolean := (v8 /= 0);
constant MACEN : boolean := (mac = 1);
constant MACPIPE: boolean := (mac = 1) and (v8/2 = 1);
constant IMPL : integer := 15;
constant VER : integer := 3;
constant DBGUNIT : boolean := (dsu = 1);
constant TRACEBUF : boolean := (tbuf /= 0);
constant TBUFBITS : integer := 10 + log2(tbuf) - 4;
constant PWRD1 : boolean := false; --(pwd = 1) and not (index /= 0);
constant PWRD2 : boolean := pwd /= 0; --(pwd = 2) or (index /= 0);
constant RS1OPT : boolean := (is_fpga(FABTECH) /= 0);
subtype word is std_logic_vector(31 downto 0);
subtype pctype is std_logic_vector(31 downto PCLOW);
subtype rfatype is std_logic_vector(RFBITS-1 downto 0);
subtype cwptype is std_logic_vector(NWINLOG2-1 downto 0);
type icdtype is array (0 to isets-1) of word;
type dcdtype is array (0 to dsets-1) of word;
type dc_in_type is record
signed, enaddr, read, write, lock , dsuen : std_ulogic;
size : std_logic_vector(1 downto 0);
asi : std_logic_vector(7 downto 0);
end record;
type pipeline_ctrl_type is record
pc : pctype;
inst : word;
cnt : std_logic_vector(1 downto 0);
rd : rfatype;
tt : std_logic_vector(5 downto 0);
trap : std_ulogic;
annul : std_ulogic;
wreg : std_ulogic;
wicc : std_ulogic;
wy : std_ulogic;
ld : std_ulogic;
pv : std_ulogic;
rett : std_ulogic;
end record;
type fetch_reg_type is record
pc : pctype;
branch : std_ulogic;
end record;
type decode_reg_type is record
pc : pctype;
inst : icdtype;
cwp : cwptype;
set : std_logic_vector(ISETMSB downto 0);
mexc : std_ulogic;
cnt : std_logic_vector(1 downto 0);
pv : std_ulogic;
annul : std_ulogic;
inull : std_ulogic;
step : std_ulogic;
end record;
type regacc_reg_type is record
ctrl : pipeline_ctrl_type;
rs1 : std_logic_vector(4 downto 0);
rfa1, rfa2 : rfatype;
rsel1, rsel2 : std_logic_vector(2 downto 0);
rfe1, rfe2 : std_ulogic;
cwp : cwptype;
imm : word;
ldcheck1 : std_ulogic;
ldcheck2 : std_ulogic;
ldchkra : std_ulogic;
ldchkex : std_ulogic;
su : std_ulogic;
et : std_ulogic;
wovf : std_ulogic;
wunf : std_ulogic;
ticc : std_ulogic;
jmpl : std_ulogic;
step : std_ulogic;
mulstart : std_ulogic;
divstart : std_ulogic;
end record;
type execute_reg_type is record
ctrl : pipeline_ctrl_type;
op1 : word;
op2 : word;
aluop : std_logic_vector(2 downto 0); -- Alu operation
alusel : std_logic_vector(1 downto 0); -- Alu result select
aluadd : std_ulogic;
alucin : std_ulogic;
ldbp1, ldbp2 : std_ulogic;
invop2 : std_ulogic;
shcnt : std_logic_vector(4 downto 0); -- shift count
sari : std_ulogic; -- shift msb
shleft : std_ulogic; -- shift left/right
ymsb : std_ulogic; -- shift left/right
rd : std_logic_vector(4 downto 0);
jmpl : std_ulogic;
su : std_ulogic;
et : std_ulogic;
cwp : cwptype;
icc : std_logic_vector(3 downto 0);
mulstep: std_ulogic;
mul : std_ulogic;
mac : std_ulogic;
end record;
type memory_reg_type is record
ctrl : pipeline_ctrl_type;
result : word;
y : word;
icc : std_logic_vector(3 downto 0);
nalign : std_ulogic;
dci : dc_in_type;
werr : std_ulogic;
wcwp : std_ulogic;
irqen : std_ulogic;
irqen2 : std_ulogic;
mac : std_ulogic;
divz : std_ulogic;
su : std_ulogic;
mul : std_ulogic;
end record;
type exception_state is (run, trap, dsu1, dsu2);
type exception_reg_type is record
ctrl : pipeline_ctrl_type;
result : word;
y : word;
icc : std_logic_vector( 3 downto 0);
annul_all : std_ulogic;
data : dcdtype;
set : std_logic_vector(DSETMSB downto 0);
mexc : std_ulogic;
dci : dc_in_type;
laddr : std_logic_vector(1 downto 0);
rstate : exception_state;
npc : std_logic_vector(2 downto 0);
intack : std_ulogic;
ipend : std_ulogic;
mac : std_ulogic;
debug : std_ulogic;
nerror : std_ulogic;
end record;
type dsu_registers is record
tt : std_logic_vector(7 downto 0);
err : std_ulogic;
tbufcnt : std_logic_vector(TBUFBITS-1 downto 0);
asi : std_logic_vector(7 downto 0);
crdy : std_logic_vector(2 downto 1); -- diag cache access ready
end record;
type irestart_register is record
addr : pctype;
pwd : std_ulogic;
end record;
type pwd_register_type is record
pwd : std_ulogic;
error : std_ulogic;
end record;
type special_register_type is record
cwp : cwptype; -- current window pointer
icc : std_logic_vector(3 downto 0); -- integer condition codes
tt : std_logic_vector(7 downto 0); -- trap type
tba : std_logic_vector(19 downto 0); -- trap base address
wim : std_logic_vector(NWIN-1 downto 0); -- window invalid mask
pil : std_logic_vector(3 downto 0); -- processor interrupt level
ec : std_ulogic; -- enable CP
ef : std_ulogic; -- enable FP
ps : std_ulogic; -- previous supervisor flag
s : std_ulogic; -- supervisor flag
et : std_ulogic; -- enable traps
y : word;
asr18 : word;
svt : std_ulogic; -- enable traps
dwt : std_ulogic; -- disable write error trap
end record;
type write_reg_type is record
s : special_register_type;
result : word;
wa : rfatype;
wreg : std_ulogic;
except : std_ulogic;
end record;
type registers is record
f : fetch_reg_type;
d : decode_reg_type;
a : regacc_reg_type;
e : execute_reg_type;
m : memory_reg_type;
x : exception_reg_type;
w : write_reg_type;
end record;
type exception_type is record
pri : std_ulogic;
ill : std_ulogic;
fpdis : std_ulogic;
cpdis : std_ulogic;
wovf : std_ulogic;
wunf : std_ulogic;
ticc : std_ulogic;
end record;
type watchpoint_register is record
addr : std_logic_vector(31 downto 2); -- watchpoint address
mask : std_logic_vector(31 downto 2); -- watchpoint mask
exec : std_ulogic; -- trap on instruction
load : std_ulogic; -- trap on load
store : std_ulogic; -- trap on store
end record;
type watchpoint_registers is array (0 to 3) of watchpoint_register;
constant wpr_none : watchpoint_register := (
zero32(31 downto 2), zero32(31 downto 2), '0', '0', '0');
function dbgexc(r : registers; dbgi : l3_debug_in_type; trap : std_ulogic; tt : std_logic_vector(7 downto 0)) return std_ulogic is
variable dmode : std_ulogic;
begin
dmode := '0';
if (not r.x.ctrl.annul and trap) = '1' then
if (((tt = "00" & TT_WATCH) and (dbgi.bwatch = '1')) or
((dbgi.bsoft = '1') and (tt = "10000001")) or
(dbgi.btrapa = '1') or
((dbgi.btrape = '1') and not ((tt(5 downto 0) = TT_PRIV) or
(tt(5 downto 0) = TT_FPDIS) or (tt(5 downto 0) = TT_WINOF) or
(tt(5 downto 0) = TT_WINUF) or (tt(5 downto 4) = "01") or (tt(7) = '1'))) or
(((not r.w.s.et) and dbgi.berror) = '1')) then
dmode := '1';
end if;
end if;
return(dmode);
end;
function dbgerr(r : registers; dbgi : l3_debug_in_type;
tt : std_logic_vector(7 downto 0))
return std_ulogic is
variable err : std_ulogic;
begin
err := not r.w.s.et;
if (((dbgi.dbreak = '1') and (tt = ("00" & TT_WATCH))) or
((dbgi.bsoft = '1') and (tt = ("10000001")))) then
err := '0';
end if;
return(err);
end;
procedure diagwr(r : in registers;
dsur : in dsu_registers;
ir : in irestart_register;
dbg : in l3_debug_in_type;
wpr : in watchpoint_registers;
s : out special_register_type;
vwpr : out watchpoint_registers;
asi : out std_logic_vector(7 downto 0);
pc, npc : out pctype;
tbufcnt : out std_logic_vector(TBUFBITS-1 downto 0);
wr : out std_ulogic;
addr : out std_logic_vector(9 downto 0);
data : out word;
fpcwr : out std_ulogic) is
variable i : integer range 0 to 3;
begin
s := r.w.s; pc := r.f.pc; npc := ir.addr; wr := '0';
vwpr := wpr; asi := dsur.asi; addr := (others => '0');
data := dbg.ddata;
tbufcnt := dsur.tbufcnt; fpcwr := '0';
if (dbg.dsuen and dbg.denable and dbg.dwrite) = '1' then
case dbg.daddr(23 downto 20) is
when "0001" =>
if dbg.daddr(16) = '1' then -- trace buffer control reg
tbufcnt := dbg.ddata(TBUFBITS-1 downto 0);
end if;
when "0011" => -- IU reg file
if dbg.daddr(12) = '0' then
wr := '1';
addr := (others => '0');
addr(RFBITS-1 downto 0) := dbg.daddr(RFBITS+1 downto 2);
else -- FPC
fpcwr := '1';
end if;
when "0100" => -- IU special registers
case dbg.daddr(7 downto 6) is
when "00" => -- IU regs Y - TBUF ctrl reg
case dbg.daddr(5 downto 2) is
when "0000" => -- Y
s.y := dbg.ddata;
when "0001" => -- PSR
s.cwp := dbg.ddata(NWINLOG2-1 downto 0);
s.icc := dbg.ddata(23 downto 20);
s.ec := dbg.ddata(13);
if FPEN then s.ef := dbg.ddata(12); end if;
s.pil := dbg.ddata(11 downto 8);
s.s := dbg.ddata(7);
s.ps := dbg.ddata(6);
s.et := dbg.ddata(5);
when "0010" => -- WIM
s.wim := dbg.ddata(NWIN-1 downto 0);
when "0011" => -- TBR
s.tba := dbg.ddata(31 downto 12);
s.tt := dbg.ddata(11 downto 4);
when "0100" => -- PC
pc := dbg.ddata(31 downto PCLOW);
when "0101" => -- NPC
npc := dbg.ddata(31 downto PCLOW);
when "0110" => --FSR
fpcwr := '1';
when "0111" => --CFSR
when "1001" => -- ASI reg
asi := dbg.ddata(7 downto 0);
--when "1001" => -- TBUF ctrl reg
-- tbufcnt := dbg.ddata(TBUFBITS-1 downto 0);
when others =>
end case;
when "01" => -- ASR16 - ASR31
case dbg.daddr(5 downto 2) is
when "0001" => -- %ASR17
s.dwt := dbg.ddata(14);
s.svt := dbg.ddata(13);
when "0010" => -- %ASR18
if MACEN then s.asr18 := dbg.ddata; end if;
when "1000" => -- %ASR24 - %ASR31
vwpr(0).addr := dbg.ddata(31 downto 2);
vwpr(0).exec := dbg.ddata(0);
when "1001" =>
vwpr(0).mask := dbg.ddata(31 downto 2);
vwpr(0).load := dbg.ddata(1);
vwpr(0).store := dbg.ddata(0);
when "1010" =>
vwpr(1).addr := dbg.ddata(31 downto 2);
vwpr(1).exec := dbg.ddata(0);
when "1011" =>
vwpr(1).mask := dbg.ddata(31 downto 2);
vwpr(1).load := dbg.ddata(1);
vwpr(1).store := dbg.ddata(0);
when "1100" =>
vwpr(2).addr := dbg.ddata(31 downto 2);
vwpr(2).exec := dbg.ddata(0);
when "1101" =>
vwpr(2).mask := dbg.ddata(31 downto 2);
vwpr(2).load := dbg.ddata(1);
vwpr(2).store := dbg.ddata(0);
when "1110" =>
vwpr(3).addr := dbg.ddata(31 downto 2);
vwpr(3).exec := dbg.ddata(0);
when "1111" => --
vwpr(3).mask := dbg.ddata(31 downto 2);
vwpr(3).load := dbg.ddata(1);
vwpr(3).store := dbg.ddata(0);
when others => --
end case;
-- disabled due to bug in XST
-- i := conv_integer(dbg.daddr(4 downto 3));
-- if dbg.daddr(2) = '0' then
-- vwpr(i).addr := dbg.ddata(31 downto 2);
-- vwpr(i).exec := dbg.ddata(0);
-- else
-- vwpr(i).mask := dbg.ddata(31 downto 2);
-- vwpr(i).load := dbg.ddata(1);
-- vwpr(i).store := dbg.ddata(0);
-- end if;
when others =>
end case;
when others =>
end case;
end if;
end;
function asr17_gen ( r : in registers) return word is
variable asr17 : word;
variable fpu2 : integer range 0 to 3;
begin
asr17 := zero32;
asr17(31 downto 28) := conv_std_logic_vector(index, 4);
if (clk2x > 8) then
asr17(16 downto 15) := conv_std_logic_vector(clk2x-8, 2);
asr17(17) := '1';
elsif (clk2x > 0) then
asr17(16 downto 15) := conv_std_logic_vector(clk2x, 2);
end if;
asr17(14) := r.w.s.dwt;
if svt = 1 then asr17(13) := r.w.s.svt; end if;
if lddel = 2 then asr17(12) := '1'; end if;
if (fpu > 0) and (fpu < 8) then fpu2 := 1;
elsif (fpu >= 8) and (fpu < 15) then fpu2 := 3;
elsif fpu = 15 then fpu2 := 2;
else fpu2 := 0; end if;
asr17(11 downto 10) := conv_std_logic_vector(fpu2, 2);
if mac = 1 then asr17(9) := '1'; end if;
if v8 /= 0 then asr17(8) := '1'; end if;
asr17(7 downto 5) := conv_std_logic_vector(nwp, 3);
asr17(4 downto 0) := conv_std_logic_vector(nwin-1, 5);
return(asr17);
end;
procedure diagread(dbgi : in l3_debug_in_type;
r : in registers;
dsur : in dsu_registers;
ir : in irestart_register;
wpr : in watchpoint_registers;
rfdata : in std_logic_vector(31 downto 0);
dco : in dcache_out_type;
tbufo : in tracebuf_out_type;
data : out word) is
variable cwp : std_logic_vector(4 downto 0);
variable rd : std_logic_vector(4 downto 0);
variable i : integer range 0 to 3;
begin
data := (others => '0'); cwp := (others => '0');
cwp(NWINLOG2-1 downto 0) := r.w.s.cwp;
case dbgi.daddr(22 downto 20) is
when "001" => -- trace buffer
if dbgi.daddr(16) = '1' then -- trace buffer control reg
data(TBUFBITS-1 downto 0) := dsur.tbufcnt;
else
case dbgi.daddr(3 downto 2) is
when "00" => data := tbufo.data(127 downto 96);
when "01" => data := tbufo.data(95 downto 64);
when "10" => data := tbufo.data(63 downto 32);
when others => data := tbufo.data(31 downto 0);
end case;
end if;
when "011" => -- IU reg file
if dbgi.daddr(12) = '0' then data := rfdata(31 downto 0);
else data := fpo.dbg.data; end if;
when "100" => -- IU regs
case dbgi.daddr(7 downto 6) is
when "00" => -- IU regs Y - TBUF ctrl reg
case dbgi.daddr(5 downto 2) is
when "0000" =>
data := r.w.s.y;
when "0001" =>
data := conv_std_logic_vector(IMPL, 4) & conv_std_logic_vector(VER, 4) &
r.w.s.icc & "000000" & r.w.s.ec & r.w.s.ef & r.w.s.pil &
r.w.s.s & r.w.s.ps & r.w.s.et & cwp;
when "0010" =>
data(NWIN-1 downto 0) := r.w.s.wim;
when "0011" =>
data := r.w.s.tba & r.w.s.tt & "0000";
when "0100" =>
data(31 downto PCLOW) := r.f.pc;
when "0101" =>
data(31 downto PCLOW) := ir.addr;
when "0110" => -- FSR
data := fpo.dbg.data;
when "0111" => -- CPSR
when "1000" => -- TT reg
data(12 downto 4) := dsur.err & dsur.tt;
when "1001" => -- ASI reg
data(7 downto 0) := dsur.asi;
when others =>
end case;
when "01" =>
if dbgi.daddr(5) = '0' then -- %ASR17
if dbgi.daddr(4 downto 2) = "001" then -- %ASR17
data := asr17_gen(r);
elsif MACEN and dbgi.daddr(4 downto 2) = "010" then -- %ASR18
data := r.w.s.asr18;
end if;
else -- %ASR24 - %ASR31
i := conv_integer(dbgi.daddr(4 downto 3)); --
if dbgi.daddr(2) = '0' then
data(31 downto 2) := wpr(i).addr;
data(0) := wpr(i).exec;
else
data(31 downto 2) := wpr(i).mask;
data(1) := wpr(i).load;
data(0) := wpr(i).store;
end if;
end if;
when others =>
end case;
when "111" =>
data := r.x.data(conv_integer(r.x.set));
when others =>
end case;
end;
procedure itrace(r : in registers;
dsur : in dsu_registers;
vdsu : in dsu_registers;
res : in word;
exc : in std_ulogic;
dbgi : in l3_debug_in_type;
error : in std_ulogic;
trap : in std_ulogic;
tbufcnt : out std_logic_vector(TBUFBITS-1 downto 0);
di : out tracebuf_in_type) is
variable meminst : std_ulogic;
begin
di.addr := (others => '0'); di.data := (others => '0');
di.enable := '0'; di.write := (others => '0');
tbufcnt := vdsu.tbufcnt;
meminst := r.x.ctrl.inst(31) and r.x.ctrl.inst(30);
if TRACEBUF then
di.addr(TBUFBITS-1 downto 0) := dsur.tbufcnt;
di.data(127) := '0';
di.data(126) := not r.x.ctrl.pv;
di.data(125 downto 96) := dbgi.timer(29 downto 0);
di.data(95 downto 64) := res;
di.data(63 downto 34) := r.x.ctrl.pc(31 downto 2);
di.data(33) := trap;
di.data(32) := error;
di.data(31 downto 0) := r.x.ctrl.inst;
if (dbgi.tenable = '0') or (r.x.rstate = dsu2) then
if ((dbgi.dsuen and dbgi.denable) = '1') and (dbgi.daddr(23 downto 20) & dbgi.daddr(16) = "00010") then
di.enable := '1';
di.addr(TBUFBITS-1 downto 0) := dbgi.daddr(TBUFBITS-1+4 downto 4);
if dbgi.dwrite = '1' then
case dbgi.daddr(3 downto 2) is
when "00" => di.write(3) := '1';
when "01" => di.write(2) := '1';
when "10" => di.write(1) := '1';
when others => di.write(0) := '1';
end case;
di.data := dbgi.ddata & dbgi.ddata & dbgi.ddata & dbgi.ddata;
end if;
end if;
elsif (not r.x.ctrl.annul and (r.x.ctrl.pv or meminst) and not r.x.debug) = '1' then
di.enable := '1'; di.write := (others => '1');
tbufcnt := dsur.tbufcnt + 1;
end if;
di.diag := dco.testen & "000";
if dco.scanen = '1' then di.enable := '0'; end if;
end if;
end;
procedure dbg_cache(holdn : in std_ulogic;
dbgi : in l3_debug_in_type;
r : in registers;
dsur : in dsu_registers;
mresult : in word;
dci : in dc_in_type;
mresult2 : out word;
dci2 : out dc_in_type
) is
begin
mresult2 := mresult; dci2 := dci; dci2.dsuen := '0';
if DBGUNIT then
if r.x.rstate = dsu2 then
dci2.asi := dsur.asi;
if (dbgi.daddr(22 downto 20) = "111") and (dbgi.dsuen = '1') then
dci2.dsuen := (dbgi.denable or r.m.dci.dsuen) and not dsur.crdy(2);
dci2.enaddr := dbgi.denable;
dci2.size := "10"; dci2.read := '1'; dci2.write := '0';
if (dbgi.denable and not r.m.dci.enaddr) = '1' then
mresult2 := (others => '0'); mresult2(19 downto 2) := dbgi.daddr(19 downto 2);
else
mresult2 := dbgi.ddata;
end if;
if dbgi.dwrite = '1' then
dci2.read := '0'; dci2.write := '1';
end if;
end if;
end if;
end if;
end;
procedure fpexack(r : in registers; fpexc : out std_ulogic) is
begin
fpexc := '0';
if FPEN then
if r.x.ctrl.tt = TT_FPEXC then fpexc := '1'; end if;
end if;
end;
procedure diagrdy(denable : in std_ulogic;
dsur : in dsu_registers;
dci : in dc_in_type;
mds : in std_ulogic;
ico : in icache_out_type;
crdy : out std_logic_vector(2 downto 1)) is
begin
crdy := dsur.crdy(1) & '0';
if dci.dsuen = '1' then
case dsur.asi(4 downto 0) is
when ASI_ITAG | ASI_IDATA | ASI_UINST | ASI_SINST =>
crdy(2) := ico.diagrdy and not dsur.crdy(2);
when ASI_DTAG | ASI_MMUSNOOP_DTAG | ASI_DDATA | ASI_UDATA | ASI_SDATA =>
crdy(1) := not denable and dci.enaddr and not dsur.crdy(1);
when others =>
crdy(2) := dci.enaddr and denable;
end case;
end if;
end;
signal r, rin : registers;
signal wpr, wprin : watchpoint_registers;
signal dsur, dsuin : dsu_registers;
signal ir, irin : irestart_register;
signal rp, rpin : pwd_register_type;
signal inst_p : std_logic := '0';
signal inHackVector : std_logic_vector(7 downto 0) := X"00";
-- execute stage operations
constant EXE_AND : std_logic_vector(2 downto 0) := "000";
constant EXE_XOR : std_logic_vector(2 downto 0) := "001"; -- must be equal to EXE_PASS2
constant EXE_OR : std_logic_vector(2 downto 0) := "010";
constant EXE_XNOR : std_logic_vector(2 downto 0) := "011";
constant EXE_ANDN : std_logic_vector(2 downto 0) := "100";
constant EXE_ORN : std_logic_vector(2 downto 0) := "101";
constant EXE_DIV : std_logic_vector(2 downto 0) := "110";
constant EXE_PASS1 : std_logic_vector(2 downto 0) := "000";
constant EXE_PASS2 : std_logic_vector(2 downto 0) := "001";
constant EXE_STB : std_logic_vector(2 downto 0) := "010";
constant EXE_STH : std_logic_vector(2 downto 0) := "011";
constant EXE_ONES : std_logic_vector(2 downto 0) := "100";
constant EXE_RDY : std_logic_vector(2 downto 0) := "101";
constant EXE_SPR : std_logic_vector(2 downto 0) := "110";
constant EXE_LINK : std_logic_vector(2 downto 0) := "111";
constant EXE_SLL : std_logic_vector(2 downto 0) := "001";
constant EXE_SRL : std_logic_vector(2 downto 0) := "010";
constant EXE_SRA : std_logic_vector(2 downto 0) := "100";
constant EXE_NOP : std_logic_vector(2 downto 0) := "000";
-- EXE result select
constant EXE_RES_ADD : std_logic_vector(1 downto 0) := "00";
constant EXE_RES_SHIFT : std_logic_vector(1 downto 0) := "01";
constant EXE_RES_LOGIC : std_logic_vector(1 downto 0) := "10";
constant EXE_RES_MISC : std_logic_vector(1 downto 0) := "11";
-- Load types
constant SZBYTE : std_logic_vector(1 downto 0) := "00";
constant SZHALF : std_logic_vector(1 downto 0) := "01";
constant SZWORD : std_logic_vector(1 downto 0) := "10";
constant SZDBL : std_logic_vector(1 downto 0) := "11";
-- calculate register file address
procedure regaddr(cwp : std_logic_vector; reg : std_logic_vector(4 downto 0);
rao : out rfatype) is
variable ra : rfatype;
constant globals : std_logic_vector(RFBITS-5 downto 0) :=
conv_std_logic_vector(NWIN, RFBITS-4);
begin
ra := (others => '0'); ra(4 downto 0) := reg;
if reg(4 downto 3) = "00" then ra(RFBITS -1 downto 4) := globals;
else
ra(NWINLOG2+3 downto 4) := cwp + ra(4);
if ra(RFBITS-1 downto 4) = globals then
ra(RFBITS-1 downto 4) := (others => '0');
end if;
end if;
rao := ra;
end;
-- branch adder
function branch_address(inst : word; pc : pctype) return std_logic_vector is
variable baddr, caddr, tmp : pctype;
begin
caddr := (others => '0'); caddr(31 downto 2) := inst(29 downto 0);
caddr(31 downto 2) := caddr(31 downto 2) + pc(31 downto 2);
baddr := (others => '0'); baddr(31 downto 24) := (others => inst(21));
baddr(23 downto 2) := inst(21 downto 0);
baddr(31 downto 2) := baddr(31 downto 2) + pc(31 downto 2);
if inst(30) = '1' then tmp := caddr; else tmp := baddr; end if;
return(tmp);
end;
-- evaluate branch condition
function branch_true(icc : std_logic_vector(3 downto 0); inst : word)
return std_ulogic is
variable n, z, v, c, branch : std_ulogic;
begin
n := icc(3); z := icc(2); v := icc(1); c := icc(0);
case inst(27 downto 25) is
when "000" => branch := inst(28) xor '0'; -- bn, ba
when "001" => branch := inst(28) xor z; -- be, bne
when "010" => branch := inst(28) xor (z or (n xor v)); -- ble, bg
when "011" => branch := inst(28) xor (n xor v); -- bl, bge
when "100" => branch := inst(28) xor (c or z); -- bleu, bgu
when "101" => branch := inst(28) xor c; -- bcs, bcc
when "110" => branch := inst(28) xor n; -- bneg, bpos
when others => branch := inst(28) xor v; -- bvs, bvc
end case;
return(branch);
end;
-- detect RETT instruction in the pipeline and set the local psr.su and psr.et
procedure su_et_select(r : in registers; xc_ps, xc_s, xc_et : in std_ulogic;
su, et : out std_ulogic) is
begin
if ((r.a.ctrl.rett or r.e.ctrl.rett or r.m.ctrl.rett or r.x.ctrl.rett) = '1')
and (r.x.annul_all = '0')
then su := xc_ps; et := '1';
else su := xc_s; et := xc_et; end if;
end;
-- detect watchpoint trap
function wphit(r : registers; wpr : watchpoint_registers; debug : l3_debug_in_type)
return std_ulogic is
variable exc : std_ulogic;
begin
exc := '0';
for i in 1 to NWP loop
if ((wpr(i-1).exec and r.a.ctrl.pv and not r.a.ctrl.annul) = '1') then
if (((wpr(i-1).addr xor r.a.ctrl.pc(31 downto 2)) and wpr(i-1).mask) = Zero32(31 downto 2)) then
exc := '1';
end if;
end if;
end loop;
if DBGUNIT then
if (debug.dsuen and not r.a.ctrl.annul) = '1' then
exc := exc or (r.a.ctrl.pv and ((debug.dbreak and debug.bwatch) or r.a.step));
end if;
end if;
return(exc);
end;
-- 32-bit shifter
function shift3(r : registers; aluin1, aluin2 : word) return word is
variable shiftin : unsigned(63 downto 0);
variable shiftout : unsigned(63 downto 0);
variable cnt : natural range 0 to 31;
begin
cnt := conv_integer(r.e.shcnt);
if r.e.shleft = '1' then
shiftin(30 downto 0) := (others => '0');
shiftin(63 downto 31) := '0' & unsigned(aluin1);
else
shiftin(63 downto 32) := (others => r.e.sari);
shiftin(31 downto 0) := unsigned(aluin1);
end if;
shiftout := SHIFT_RIGHT(shiftin, cnt);
return(std_logic_vector(shiftout(31 downto 0)));
end;
function shift2(r : registers; aluin1, aluin2 : word) return word is
variable ushiftin : unsigned(31 downto 0);
variable sshiftin : signed(32 downto 0);
variable cnt : natural range 0 to 31;
begin
cnt := conv_integer(r.e.shcnt);
ushiftin := unsigned(aluin1);
sshiftin := signed('0' & aluin1);
if r.e.shleft = '1' then
return(std_logic_vector(SHIFT_LEFT(ushiftin, cnt)));
else
if r.e.sari = '1' then sshiftin(32) := aluin1(31); end if;
sshiftin := SHIFT_RIGHT(sshiftin, cnt);
return(std_logic_vector(sshiftin(31 downto 0)));
-- else
-- ushiftin := SHIFT_RIGHT(ushiftin, cnt);
-- return(std_logic_vector(ushiftin));
-- end if;
end if;
end;
function shift(r : registers; aluin1, aluin2 : word;
shiftcnt : std_logic_vector(4 downto 0); sari : std_ulogic ) return word is
variable shiftin : std_logic_vector(63 downto 0);
begin
shiftin := zero32 & aluin1;
if r.e.shleft = '1' then
shiftin(31 downto 0) := zero32; shiftin(63 downto 31) := '0' & aluin1;
else shiftin(63 downto 32) := (others => sari); end if;
if shiftcnt (4) = '1' then shiftin(47 downto 0) := shiftin(63 downto 16); end if;
if shiftcnt (3) = '1' then shiftin(39 downto 0) := shiftin(47 downto 8); end if;
if shiftcnt (2) = '1' then shiftin(35 downto 0) := shiftin(39 downto 4); end if;
if shiftcnt (1) = '1' then shiftin(33 downto 0) := shiftin(35 downto 2); end if;
if shiftcnt (0) = '1' then shiftin(31 downto 0) := shiftin(32 downto 1); end if;
return(shiftin(31 downto 0));
end;
-- Check for illegal and privileged instructions
procedure exception_detect(r : registers; wpr : watchpoint_registers; dbgi : l3_debug_in_type;
trapin : in std_ulogic; ttin : in std_logic_vector(5 downto 0);
trap : out std_ulogic; tt : out std_logic_vector(5 downto 0)) is
variable illegal_inst, privileged_inst : std_ulogic;
variable cp_disabled, fp_disabled, fpop : std_ulogic;
variable op : std_logic_vector(1 downto 0);
variable op2 : std_logic_vector(2 downto 0);
variable op3 : std_logic_vector(5 downto 0);
variable rd : std_logic_vector(4 downto 0);
variable inst : word;
variable wph : std_ulogic;
begin
inst := r.a.ctrl.inst; trap := trapin; tt := ttin;
if r.a.ctrl.annul = '0' then
op := inst(31 downto 30); op2 := inst(24 downto 22);
op3 := inst(24 downto 19); rd := inst(29 downto 25);
illegal_inst := '0'; privileged_inst := '0'; cp_disabled := '0';
fp_disabled := '0'; fpop := '0';
case op is
when CALL => null;
when FMT2 =>
case op2 is
when SETHI | BICC => null;
when FBFCC =>
if FPEN then fp_disabled := not r.w.s.ef; else fp_disabled := '1'; end if;
when CBCCC =>
if (not CPEN) or (r.w.s.ec = '0') then cp_disabled := '1'; end if;
when others => illegal_inst := '1';
end case;
when FMT3 =>
case op3 is
when IAND | ANDCC | ANDN | ANDNCC | IOR | ORCC | ORN | ORNCC | IXOR |
XORCC | IXNOR | XNORCC | ISLL | ISRL | ISRA | MULSCC | IADD | ADDX |
ADDCC | ADDXCC | ISUB | SUBX | SUBCC | SUBXCC | FLUSH | JMPL | TICC |
SAVE | RESTORE | RDY => null;
when TADDCC | TADDCCTV | TSUBCC | TSUBCCTV =>
if notag = 1 then illegal_inst := '1'; end if;
when UMAC | SMAC =>
if not MACEN then illegal_inst := '1'; end if;
when UMUL | SMUL | UMULCC | SMULCC =>
if not MULEN then illegal_inst := '1'; end if;
when UDIV | SDIV | UDIVCC | SDIVCC =>
if not DIVEN then illegal_inst := '1'; end if;
when RETT => illegal_inst := r.a.et; privileged_inst := not r.a.su;
when RDPSR | RDTBR | RDWIM => privileged_inst := not r.a.su;
when WRY => null;
when WRPSR =>
privileged_inst := not r.a.su;
when WRWIM | WRTBR => privileged_inst := not r.a.su;
when FPOP1 | FPOP2 =>
if FPEN then fp_disabled := not r.w.s.ef; fpop := '1';
else fp_disabled := '1'; fpop := '0'; end if;
when CPOP1 | CPOP2 =>
if (not CPEN) or (r.w.s.ec = '0') then cp_disabled := '1'; end if;
when others => illegal_inst := '1';
end case;
when others => -- LDST
case op3 is
when LDD | ISTD => illegal_inst := rd(0); -- trap if odd destination register
when LD | LDUB | LDSTUB | LDUH | LDSB | LDSH | ST | STB | STH | SWAP =>
null;
when LDDA | STDA =>
illegal_inst := inst(13) or rd(0); privileged_inst := not r.a.su;
when LDA | LDUBA| LDSTUBA | LDUHA | LDSBA | LDSHA | STA | STBA | STHA |
SWAPA =>
illegal_inst := inst(13); privileged_inst := not r.a.su;
when LDDF | STDF | LDF | LDFSR | STF | STFSR =>
if FPEN then fp_disabled := not r.w.s.ef;
else fp_disabled := '1'; end if;
when STDFQ =>
privileged_inst := not r.a.su;
if (not FPEN) or (r.w.s.ef = '0') then fp_disabled := '1'; end if;
when STDCQ =>
privileged_inst := not r.a.su;
if (not CPEN) or (r.w.s.ec = '0') then cp_disabled := '1'; end if;
when LDC | LDCSR | LDDC | STC | STCSR | STDC =>
if (not CPEN) or (r.w.s.ec = '0') then cp_disabled := '1'; end if;
when others => illegal_inst := '1';
end case;
end case;
wph := wphit(r, wpr, dbgi);
trap := '1';
if r.a.ctrl.trap = '1' then tt := TT_IAEX;
elsif privileged_inst = '1' then tt := TT_PRIV;
elsif illegal_inst = '1' then tt := TT_IINST;
elsif fp_disabled = '1' then tt := TT_FPDIS;
elsif cp_disabled = '1' then tt := TT_CPDIS;
elsif wph = '1' then tt := TT_WATCH;
elsif r.a.wovf= '1' then tt := TT_WINOF;
elsif r.a.wunf= '1' then tt := TT_WINUF;
elsif r.a.ticc= '1' then tt := TT_TICC;
else trap := '0'; tt:= (others => '0'); end if;
end if;
end;
-- instructions that write the condition codes (psr.icc)
procedure wicc_y_gen(inst : word; wicc, wy : out std_ulogic) is
begin
wicc := '0'; wy := '0';
if inst(31 downto 30) = FMT3 then
case inst(24 downto 19) is
when SUBCC | TSUBCC | TSUBCCTV | ADDCC | ANDCC | ORCC | XORCC | ANDNCC |
ORNCC | XNORCC | TADDCC | TADDCCTV | ADDXCC | SUBXCC | WRPSR =>
wicc := '1';
when WRY =>
if r.d.inst(conv_integer(r.d.set))(29 downto 25) = "00000" then wy := '1'; end if;
when MULSCC =>
wicc := '1'; wy := '1';
when UMAC | SMAC =>
if MACEN then wy := '1'; end if;
when UMULCC | SMULCC =>
if MULEN and (((mulo.nready = '1') and (r.d.cnt /= "00")) or (MULTYPE /= 0)) then
wicc := '1'; wy := '1';
end if;
when UMUL | SMUL =>
if MULEN and (((mulo.nready = '1') and (r.d.cnt /= "00")) or (MULTYPE /= 0)) then
wy := '1';
end if;
when UDIVCC | SDIVCC =>
if DIVEN and (divo.nready = '1') and (r.d.cnt /= "00") then
wicc := '1';
end if;
when others =>
end case;
end if;
end;
-- select cwp
procedure cwp_gen(r, v : registers; annul, wcwp : std_ulogic; ncwp : cwptype;
cwp : out cwptype) is
begin
if (r.x.rstate = trap) or (r.x.rstate = dsu2) or (rstn = '0') then cwp := v.w.s.cwp;
elsif (wcwp = '1') and (annul = '0') then cwp := ncwp;
elsif r.m.wcwp = '1' then cwp := r.m.result(NWINLOG2-1 downto 0);
else cwp := r.d.cwp; end if;
end;
-- generate wcwp in ex stage
procedure cwp_ex(r : in registers; wcwp : out std_ulogic) is
begin
if (r.e.ctrl.inst(31 downto 30) = FMT3) and
(r.e.ctrl.inst(24 downto 19) = WRPSR)
then wcwp := not r.e.ctrl.annul; else wcwp := '0'; end if;
end;
-- generate next cwp & window under- and overflow traps
procedure cwp_ctrl(r : in registers; xc_wim : in std_logic_vector(NWIN-1 downto 0);
inst : word; de_cwp : out cwptype; wovf_exc, wunf_exc, wcwp : out std_ulogic) is
variable op : std_logic_vector(1 downto 0);
variable op3 : std_logic_vector(5 downto 0);
variable wim : word;
variable ncwp : cwptype;
begin
op := inst(31 downto 30); op3 := inst(24 downto 19);
wovf_exc := '0'; wunf_exc := '0'; wim := (others => '0');
wim(NWIN-1 downto 0) := xc_wim; ncwp := r.d.cwp; wcwp := '0';
if (op = FMT3) and ((op3 = RETT) or (op3 = RESTORE) or (op3 = SAVE)) then
wcwp := '1';
if (op3 = SAVE) then
if (not CWPOPT) and (r.d.cwp = CWPMIN) then ncwp := CWPMAX;
else ncwp := r.d.cwp - 1 ; end if;
else
if (not CWPOPT) and (r.d.cwp = CWPMAX) then ncwp := CWPMIN;
else ncwp := r.d.cwp + 1; end if;
end if;
if wim(conv_integer(ncwp)) = '1' then
if op3 = SAVE then wovf_exc := '1'; else wunf_exc := '1'; end if;
end if;
end if;
de_cwp := ncwp;
end;
-- generate register read address 1
procedure rs1_gen(r : registers; inst : word; rs1 : out std_logic_vector(4 downto 0);
rs1mod : out std_ulogic) is
variable op : std_logic_vector(1 downto 0);
variable op3 : std_logic_vector(5 downto 0);
begin
op := inst(31 downto 30); op3 := inst(24 downto 19);
rs1 := inst(18 downto 14); rs1mod := '0';
if (op = LDST) then
if ((r.d.cnt = "01") and ((op3(2) and not op3(3)) = '1')) or
(r.d.cnt = "10")
then rs1mod := '1'; rs1 := inst(29 downto 25); end if;
if ((r.d.cnt = "10") and (op3(3 downto 0) = "0111")) then
rs1(0) := '1';
end if;
end if;
end;
-- load/icc interlock detection
procedure lock_gen(r : registers; rs2, rd : std_logic_vector(4 downto 0);
rfa1, rfa2, rfrd : rfatype; inst : word; fpc_lock, mulinsn, divinsn : std_ulogic;
lldcheck1, lldcheck2, lldlock, lldchkra, lldchkex : out std_ulogic) is
variable op : std_logic_vector(1 downto 0);
variable op2 : std_logic_vector(2 downto 0);
variable op3 : std_logic_vector(5 downto 0);
variable cond : std_logic_vector(3 downto 0);
variable rs1 : std_logic_vector(4 downto 0);
variable i, ldcheck1, ldcheck2, ldchkra, ldchkex, ldcheck3 : std_ulogic;
variable ldlock, icc_check, bicc_hold, chkmul, y_check : std_ulogic;
variable lddlock : boolean;
begin
op := inst(31 downto 30); op3 := inst(24 downto 19);
op2 := inst(24 downto 22); cond := inst(28 downto 25);
rs1 := inst(18 downto 14); lddlock := false; i := inst(13);
ldcheck1 := '0'; ldcheck2 := '0'; ldcheck3 := '0'; ldlock := '0';
ldchkra := '1'; ldchkex := '1'; icc_check := '0'; bicc_hold := '0';
y_check := '0';
if (r.d.annul = '0') then
case op is
when FMT2 =>
if (op2 = BICC) and (cond(2 downto 0) /= "000") then
icc_check := '1';
end if;
when FMT3 =>
ldcheck1 := '1'; ldcheck2 := not i;
case op3 is
when TICC =>
if (cond(2 downto 0) /= "000") then icc_check := '1'; end if;
when RDY =>
ldcheck1 := '0'; ldcheck2 := '0';
if MACPIPE then y_check := '1'; end if;
when RDWIM | RDTBR =>
ldcheck1 := '0'; ldcheck2 := '0';
when RDPSR =>
ldcheck1 := '0'; ldcheck2 := '0'; icc_check := '1';
if MULEN then icc_check := '1'; end if;
-- when ADDX | ADDXCC | SUBX | SUBXCC =>
-- if MULEN then icc_check := '1'; end if;
when SDIV | SDIVCC | UDIV | UDIVCC =>
if DIVEN then y_check := '1'; end if;
when FPOP1 | FPOP2 => ldcheck1:= '0'; ldcheck2 := '0';
when others =>
end case;
when LDST =>
ldcheck1 := '1'; ldchkra := '0';
case r.d.cnt is
when "00" =>
if (lddel = 2) and (op3(2) = '1') then ldcheck3 := '1'; end if;
ldcheck2 := not i; ldchkra := '1';
when "01" => ldcheck2 := not i;
when others => ldchkex := '0';
end case;
if (op3(2 downto 0) = "011") then lddlock := true; end if;
when others => null;
end case;
end if;
if MULEN or DIVEN then
chkmul := mulinsn;
bicc_hold := bicc_hold or (icc_check and r.m.ctrl.wicc and (r.m.ctrl.cnt(0) or r.m.mul));
else chkmul := '0'; end if;
if DIVEN then
bicc_hold := bicc_hold or (y_check and (r.a.ctrl.wy or r.e.ctrl.wy));
chkmul := chkmul or divinsn;
end if;
bicc_hold := bicc_hold or (icc_check and (r.a.ctrl.wicc or r.e.ctrl.wicc));
if (((r.a.ctrl.ld or chkmul) and r.a.ctrl.wreg and ldchkra) = '1') and
(((ldcheck1 = '1') and (r.a.ctrl.rd = rfa1)) or
((ldcheck2 = '1') and (r.a.ctrl.rd = rfa2)) or
((ldcheck3 = '1') and (r.a.ctrl.rd = rfrd)))
then ldlock := '1'; end if;
if (((r.e.ctrl.ld or r.e.mac) and r.e.ctrl.wreg and ldchkex) = '1') and
((lddel = 2) or (MACPIPE and (r.e.mac = '1')) or ((MULTYPE = 3) and (r.e.mul = '1'))) and
(((ldcheck1 = '1') and (r.e.ctrl.rd = rfa1)) or
((ldcheck2 = '1') and (r.e.ctrl.rd = rfa2)))
then ldlock := '1'; end if;
ldlock := ldlock or bicc_hold or fpc_lock;
lldcheck1 := ldcheck1; lldcheck2:= ldcheck2; lldlock := ldlock;
lldchkra := ldchkra; lldchkex := ldchkex;
end;
procedure fpbranch(inst : in word; fcc : in std_logic_vector(1 downto 0);
branch : out std_ulogic) is
variable cond : std_logic_vector(3 downto 0);
variable fbres : std_ulogic;
begin
cond := inst(28 downto 25);
case cond(2 downto 0) is
when "000" => fbres := '0'; -- fba, fbn
when "001" => fbres := fcc(1) or fcc(0);
when "010" => fbres := fcc(1) xor fcc(0);
when "011" => fbres := fcc(0);
when "100" => fbres := (not fcc(1)) and fcc(0);
when "101" => fbres := fcc(1);
when "110" => fbres := fcc(1) and not fcc(0);
when others => fbres := fcc(1) and fcc(0);
end case;
branch := cond(3) xor fbres;
end;
-- PC generation
procedure ic_ctrl(r : registers; inst : word; annul_all, ldlock, branch_true,
fbranch_true, cbranch_true, fccv, cccv : in std_ulogic;
cnt : out std_logic_vector(1 downto 0);
de_pc : out pctype; de_branch, ctrl_annul, de_annul, jmpl_inst, inull,
de_pv, ctrl_pv, de_hold_pc, ticc_exception, rett_inst, mulstart,
divstart : out std_ulogic) is
variable op : std_logic_vector(1 downto 0);
variable op2 : std_logic_vector(2 downto 0);
variable op3 : std_logic_vector(5 downto 0);
variable cond : std_logic_vector(3 downto 0);
variable hold_pc, annul_current, annul_next, branch, annul, pv : std_ulogic;
variable de_jmpl : std_ulogic;
begin
branch := '0'; annul_next := '0'; annul_current := '0'; pv := '1';
hold_pc := '0'; ticc_exception := '0'; rett_inst := '0';
op := inst(31 downto 30); op3 := inst(24 downto 19);
op2 := inst(24 downto 22); cond := inst(28 downto 25);
annul := inst(29); de_jmpl := '0'; cnt := "00";
mulstart := '0'; divstart := '0';
if r.d.annul = '0' then
case inst(31 downto 30) is
when CALL =>
branch := '1';
if r.d.inull = '1' then
hold_pc := '1'; annul_current := '1';
end if;
when FMT2 =>
if (op2 = BICC) or (FPEN and (op2 = FBFCC)) or (CPEN and (op2 = CBCCC)) then
if (FPEN and (op2 = FBFCC)) then
branch := fbranch_true;
if fccv /= '1' then hold_pc := '1'; annul_current := '1'; end if;
elsif (CPEN and (op2 = CBCCC)) then
branch := cbranch_true;
if cccv /= '1' then hold_pc := '1'; annul_current := '1'; end if;
else branch := branch_true; end if;
if hold_pc = '0' then
if (branch = '1') then
if (cond = BA) and (annul = '1') then annul_next := '1'; end if;
else annul_next := annul; end if;
if r.d.inull = '1' then -- contention with JMPL
hold_pc := '1'; annul_current := '1'; annul_next := '0';
end if;
end if;
end if;
when FMT3 =>
case op3 is
when UMUL | SMUL | UMULCC | SMULCC =>
if MULEN and (MULTYPE /= 0) then mulstart := '1'; end if;
if MULEN and (MULTYPE = 0) then
case r.d.cnt is
when "00" =>
cnt := "01"; hold_pc := '1'; pv := '0'; mulstart := '1';
when "01" =>
if mulo.nready = '1' then cnt := "00";
else cnt := "01"; pv := '0'; hold_pc := '1'; end if;
when others => null;
end case;
end if;
when UDIV | SDIV | UDIVCC | SDIVCC =>
if DIVEN then
case r.d.cnt is
when "00" =>
cnt := "01"; hold_pc := '1'; pv := '0';
divstart := '1';
when "01" =>
if divo.nready = '1' then cnt := "00";
else cnt := "01"; pv := '0'; hold_pc := '1'; end if;
when others => null;
end case;
end if;
when TICC =>
if branch_true = '1' then ticc_exception := '1'; end if;
when RETT =>
rett_inst := '1'; --su := sregs.ps;
when JMPL =>
de_jmpl := '1';
when WRY =>
if PWRD1 then
if inst(29 downto 25) = "10011" then -- %ASR19
case r.d.cnt is
when "00" =>
pv := '0'; cnt := "00"; hold_pc := '1';
if r.x.ipend = '1' then cnt := "01"; end if;
when "01" =>
cnt := "00";
when others =>
end case;
end if;
end if;
when others => null;
end case;
when others => -- LDST
case r.d.cnt is
when "00" =>
if (op3(2) = '1') or (op3(1 downto 0) = "11") then -- ST/LDST/SWAP/LDD
cnt := "01"; hold_pc := '1'; pv := '0';
end if;
when "01" =>
if (op3(2 downto 0) = "111") or (op3(3 downto 0) = "1101") or
((CPEN or FPEN) and ((op3(5) & op3(2 downto 0)) = "1110"))
then -- LDD/STD/LDSTUB/SWAP
cnt := "10"; pv := '0'; hold_pc := '1';
else
cnt := "00";
end if;
when "10" =>
cnt := "00";
when others => null;
end case;
end case;
end if;
if ldlock = '1' then
cnt := r.d.cnt; annul_next := '0'; pv := '1';
end if;
hold_pc := (hold_pc or ldlock) and not annul_all;
if hold_pc = '1' then de_pc := r.d.pc; else de_pc := r.f.pc; end if;
annul_current := (annul_current or ldlock or annul_all);
ctrl_annul := r.d.annul or annul_all or annul_current;
pv := pv and not ((r.d.inull and not hold_pc) or annul_all);
jmpl_inst := de_jmpl and not annul_current;
annul_next := (r.d.inull and not hold_pc) or annul_next or annul_all;
if (annul_next = '1') or (rstn = '0') then
cnt := (others => '0');
end if;
de_hold_pc := hold_pc; de_branch := branch; de_annul := annul_next;
de_pv := pv; ctrl_pv := r.d.pv and
not ((r.d.annul and not r.d.pv) or annul_all or annul_current);
inull := (not rstn) or r.d.inull or hold_pc or annul_all;
end;
-- register write address generation
procedure rd_gen(r : registers; inst : word; wreg, ld : out std_ulogic;
rdo : out std_logic_vector(4 downto 0)) is
variable write_reg : std_ulogic;
variable op : std_logic_vector(1 downto 0);
variable op2 : std_logic_vector(2 downto 0);
variable op3 : std_logic_vector(5 downto 0);
variable rd : std_logic_vector(4 downto 0);
begin
op := inst(31 downto 30);
op2 := inst(24 downto 22);
op3 := inst(24 downto 19);
write_reg := '0'; rd := inst(29 downto 25); ld := '0';
case op is
when CALL =>
write_reg := '1'; rd := "01111"; -- CALL saves PC in r[15] (%o7)
when FMT2 =>
if (op2 = SETHI) then write_reg := '1'; end if;
when FMT3 =>
case op3 is
when UMUL | SMUL | UMULCC | SMULCC =>
if MULEN then
if (((mulo.nready = '1') and (r.d.cnt /= "00")) or (MULTYPE /= 0)) then
write_reg := '1';
end if;
else write_reg := '1'; end if;
when UDIV | SDIV | UDIVCC | SDIVCC =>
if DIVEN then
if (divo.nready = '1') and (r.d.cnt /= "00") then
write_reg := '1';
end if;
else write_reg := '1'; end if;
when RETT | WRPSR | WRY | WRWIM | WRTBR | TICC | FLUSH => null;
when FPOP1 | FPOP2 => null;
when CPOP1 | CPOP2 => null;
when others => write_reg := '1';
end case;
when others => -- LDST
ld := not op3(2);
if (op3(2) = '0') and not ((CPEN or FPEN) and (op3(5) = '1'))
then write_reg := '1'; end if;
case op3 is
when SWAP | SWAPA | LDSTUB | LDSTUBA =>
if r.d.cnt = "00" then write_reg := '1'; ld := '1'; end if;
when others => null;
end case;
if r.d.cnt = "01" then
case op3 is
when LDD | LDDA | LDDC | LDDF => rd(0) := '1';
when others =>
end case;
end if;
end case;
if (rd = "00000") then write_reg := '0'; end if;
wreg := write_reg; rdo := rd;
end;
-- immediate data generation
function imm_data (r : registers; insn : word)
return word is
variable immediate_data, inst : word;
begin
immediate_data := (others => '0'); inst := insn;
case inst(31 downto 30) is
when FMT2 =>
immediate_data := inst(21 downto 0) & "0000000000";
when others => -- LDST
immediate_data(31 downto 13) := (others => inst(12));
immediate_data(12 downto 0) := inst(12 downto 0);
end case;
return(immediate_data);
end;
-- read special registers
function get_spr (r : registers) return word is
variable spr : word;
begin
spr := (others => '0');
case r.e.ctrl.inst(24 downto 19) is
when RDPSR => spr(31 downto 5) := conv_std_logic_vector(IMPL,4) &
conv_std_logic_vector(VER,4) & r.m.icc & "000000" & r.w.s.ec & r.w.s.ef &
r.w.s.pil & r.e.su & r.w.s.ps & r.e.et;
spr(NWINLOG2-1 downto 0) := r.e.cwp;
when RDTBR => spr(31 downto 4) := r.w.s.tba & r.w.s.tt;
when RDWIM => spr(NWIN-1 downto 0) := r.w.s.wim;
when others =>
end case;
return(spr);
end;
-- immediate data select
function imm_select(inst : word) return boolean is
variable imm : boolean;
begin
imm := false;
case inst(31 downto 30) is
when FMT2 =>
case inst(24 downto 22) is
when SETHI => imm := true;
when others =>
end case;
when FMT3 =>
case inst(24 downto 19) is
when RDWIM | RDPSR | RDTBR => imm := true;
when others => if (inst(13) = '1') then imm := true; end if;
end case;
when LDST =>
if (inst(13) = '1') then imm := true; end if;
when others =>
end case;
return(imm);
end;
-- EXE operation
procedure alu_op(r : in registers; iop1, iop2 : in word; me_icc : std_logic_vector(3 downto 0);
my, ldbp : std_ulogic; aop1, aop2 : out word; aluop : out std_logic_vector(2 downto 0);
alusel : out std_logic_vector(1 downto 0); aluadd : out std_ulogic;
shcnt : out std_logic_vector(4 downto 0); sari, shleft, ymsb,
mulins, divins, mulstep, macins, ldbp2, invop2 : out std_ulogic) is
variable op : std_logic_vector(1 downto 0);
variable op2 : std_logic_vector(2 downto 0);
variable op3 : std_logic_vector(5 downto 0);
variable rd : std_logic_vector(4 downto 0);
variable icc : std_logic_vector(3 downto 0);
variable y0 : std_ulogic;
begin
op := r.a.ctrl.inst(31 downto 30);
op2 := r.a.ctrl.inst(24 downto 22);
op3 := r.a.ctrl.inst(24 downto 19);
aop1 := iop1; aop2 := iop2; ldbp2 := ldbp;
aluop := EXE_NOP; alusel := EXE_RES_MISC; aluadd := '1';
shcnt := iop2(4 downto 0); sari := '0'; shleft := '0'; invop2 := '0';
ymsb := iop1(0); mulins := '0'; divins := '0'; mulstep := '0';
macins := '0';
if r.e.ctrl.wy = '1' then y0 := my;
elsif r.m.ctrl.wy = '1' then y0 := r.m.y(0);
elsif r.x.ctrl.wy = '1' then y0 := r.x.y(0);
else y0 := r.w.s.y(0); end if;
if r.e.ctrl.wicc = '1' then icc := me_icc;
elsif r.m.ctrl.wicc = '1' then icc := r.m.icc;
elsif r.x.ctrl.wicc = '1' then icc := r.x.icc;
else icc := r.w.s.icc; end if;
case op is
when CALL =>
aluop := EXE_LINK;
when FMT2 =>
case op2 is
when SETHI => aluop := EXE_PASS2;
when others =>
end case;
when FMT3 =>
case op3 is
when IADD | ADDX | ADDCC | ADDXCC | TADDCC | TADDCCTV | SAVE | RESTORE |
TICC | JMPL | RETT => alusel := EXE_RES_ADD;
when ISUB | SUBX | SUBCC | SUBXCC | TSUBCC | TSUBCCTV =>
alusel := EXE_RES_ADD; aluadd := '0'; aop2 := not iop2; invop2 := '1';
when MULSCC => alusel := EXE_RES_ADD;
aop1 := (icc(3) xor icc(1)) & iop1(31 downto 1);
if y0 = '0' then aop2 := (others => '0'); ldbp2 := '0'; end if;
mulstep := '1';
when UMUL | UMULCC | SMUL | SMULCC =>
if MULEN then mulins := '1'; end if;
when UMAC | SMAC =>
if MACEN then mulins := '1'; macins := '1'; end if;
when UDIV | UDIVCC | SDIV | SDIVCC =>
if DIVEN then
aluop := EXE_DIV; alusel := EXE_RES_LOGIC; divins := '1';
end if;
when IAND | ANDCC => aluop := EXE_AND; alusel := EXE_RES_LOGIC;
when ANDN | ANDNCC => aluop := EXE_ANDN; alusel := EXE_RES_LOGIC;
when IOR | ORCC => aluop := EXE_OR; alusel := EXE_RES_LOGIC;
when ORN | ORNCC => aluop := EXE_ORN; alusel := EXE_RES_LOGIC;
when IXNOR | XNORCC => aluop := EXE_XNOR; alusel := EXE_RES_LOGIC;
when XORCC | IXOR | WRPSR | WRWIM | WRTBR | WRY =>
aluop := EXE_XOR; alusel := EXE_RES_LOGIC;
when RDPSR | RDTBR | RDWIM => aluop := EXE_SPR;
when RDY => aluop := EXE_RDY;
when ISLL => aluop := EXE_SLL; alusel := EXE_RES_SHIFT; shleft := '1';
shcnt := not iop2(4 downto 0); invop2 := '1';
when ISRL => aluop := EXE_SRL; alusel := EXE_RES_SHIFT;
when ISRA => aluop := EXE_SRA; alusel := EXE_RES_SHIFT; sari := iop1(31);
when FPOP1 | FPOP2 =>
when others =>
end case;
when others => -- LDST
case r.a.ctrl.cnt is
when "00" =>
alusel := EXE_RES_ADD;
when "01" =>
case op3 is
when LDD | LDDA | LDDC => alusel := EXE_RES_ADD;
when LDDF => alusel := EXE_RES_ADD;
when SWAP | SWAPA | LDSTUB | LDSTUBA => alusel := EXE_RES_ADD;
when STF | STDF =>
when others =>
aluop := EXE_PASS1;
if op3(2) = '1' then
if op3(1 downto 0) = "01" then aluop := EXE_STB;
elsif op3(1 downto 0) = "10" then aluop := EXE_STH; end if;
end if;
end case;
when "10" =>
aluop := EXE_PASS1;
if op3(2) = '1' then -- ST
if (op3(3) and not op3(1))= '1' then aluop := EXE_ONES; end if; -- LDSTUB/A
end if;
when others =>
end case;
end case;
end;
function ra_inull_gen(r, v : registers) return std_ulogic is
variable de_inull : std_ulogic;
begin
de_inull := '0';
if ((v.e.jmpl or v.e.ctrl.rett) and not v.e.ctrl.annul and not (r.e.jmpl and not r.e.ctrl.annul)) = '1' then de_inull := '1'; end if;
if ((v.a.jmpl or v.a.ctrl.rett) and not v.a.ctrl.annul and not (r.a.jmpl and not r.a.ctrl.annul)) = '1' then de_inull := '1'; end if;
return(de_inull);
end;
-- operand generation
procedure op_mux(r : in registers; rfd, ed, md, xd, im : in word;
rsel : in std_logic_vector(2 downto 0);
ldbp : out std_ulogic; d : out word) is
begin
ldbp := '0';
case rsel is
when "000" => d := rfd;
when "001" => d := ed;
when "010" => d := md; if lddel = 1 then ldbp := r.m.ctrl.ld; end if;
when "011" => d := xd;
when "100" => d := im;
when "101" => d := (others => '0');
when "110" => d := r.w.result;
when others => d := (others => '-');
end case;
end;
procedure op_find(r : in registers; ldchkra : std_ulogic; ldchkex : std_ulogic;
rs1 : std_logic_vector(4 downto 0); ra : rfatype; im : boolean; rfe : out std_ulogic;
osel : out std_logic_vector(2 downto 0); ldcheck : std_ulogic) is
begin
rfe := '0';
if im then osel := "100";
elsif rs1 = "00000" then osel := "101"; -- %g0
elsif ((r.a.ctrl.wreg and ldchkra) = '1') and (ra = r.a.ctrl.rd) then osel := "001";
elsif ((r.e.ctrl.wreg and ldchkex) = '1') and (ra = r.e.ctrl.rd) then osel := "010";
elsif r.m.ctrl.wreg = '1' and (ra = r.m.ctrl.rd) then osel := "011";
elsif (irfwt = 0) and r.x.ctrl.wreg = '1' and (ra = r.x.ctrl.rd) then osel := "110";
else osel := "000"; rfe := ldcheck; end if;
end;
-- generate carry-in for alu
procedure cin_gen(r : registers; me_cin : in std_ulogic; cin : out std_ulogic) is
variable op : std_logic_vector(1 downto 0);
variable op3 : std_logic_vector(5 downto 0);
variable ncin : std_ulogic;
begin
op := r.a.ctrl.inst(31 downto 30); op3 := r.a.ctrl.inst(24 downto 19);
if r.e.ctrl.wicc = '1' then ncin := me_cin;
else ncin := r.m.icc(0); end if;
cin := '0';
case op is
when FMT3 =>
case op3 is
when ISUB | SUBCC | TSUBCC | TSUBCCTV => cin := '1';
when ADDX | ADDXCC => cin := ncin;
when SUBX | SUBXCC => cin := not ncin;
when others => null;
end case;
when others => null;
end case;
end;
procedure logic_op(r : registers; aluin1, aluin2, mey : word;
ymsb : std_ulogic; logicres, y : out word) is
variable logicout : word;
begin
case r.e.aluop is
when EXE_AND => logicout := aluin1 and aluin2;
when EXE_ANDN => logicout := aluin1 and not aluin2;
when EXE_OR => logicout := aluin1 or aluin2;
when EXE_ORN => logicout := aluin1 or not aluin2;
when EXE_XOR => logicout := aluin1 xor aluin2;
when EXE_XNOR => logicout := aluin1 xor not aluin2;
when EXE_DIV =>
if DIVEN then logicout := aluin2;
else logicout := (others => '-'); end if;
when others => logicout := (others => '-');
end case;
if (r.e.ctrl.wy and r.e.mulstep) = '1' then
y := ymsb & r.m.y(31 downto 1);
elsif r.e.ctrl.wy = '1' then y := logicout;
elsif r.m.ctrl.wy = '1' then y := mey;
elsif MACPIPE and (r.x.mac = '1') then y := mulo.result(63 downto 32);
elsif r.x.ctrl.wy = '1' then y := r.x.y;
else y := r.w.s.y; end if;
logicres := logicout;
end;
procedure misc_op(r : registers; wpr : watchpoint_registers;
aluin1, aluin2, ldata, mey : word;
mout, edata : out word) is
variable miscout, bpdata, stdata : word;
variable wpi : integer;
begin
wpi := 0; miscout := r.e.ctrl.pc(31 downto 2) & "00";
edata := aluin1; bpdata := aluin1;
if ((r.x.ctrl.wreg and r.x.ctrl.ld and not r.x.ctrl.annul) = '1') and
(r.x.ctrl.rd = r.e.ctrl.rd) and (r.e.ctrl.inst(31 downto 30) = LDST) and
(r.e.ctrl.cnt /= "10")
then bpdata := ldata; end if;
case r.e.aluop is
when EXE_STB => miscout := bpdata(7 downto 0) & bpdata(7 downto 0) &
bpdata(7 downto 0) & bpdata(7 downto 0);
edata := miscout;
when EXE_STH => miscout := bpdata(15 downto 0) & bpdata(15 downto 0);
edata := miscout;
when EXE_PASS1 => miscout := bpdata; edata := miscout;
when EXE_PASS2 => miscout := aluin2;
when EXE_ONES => miscout := (others => '1');
edata := miscout;
when EXE_RDY =>
if MULEN and (r.m.ctrl.wy = '1') then miscout := mey;
else miscout := r.m.y; end if;
if (NWP > 0) and (r.e.ctrl.inst(18 downto 17) = "11") then
wpi := conv_integer(r.e.ctrl.inst(16 downto 15));
if r.e.ctrl.inst(14) = '0' then miscout := wpr(wpi).addr & '0' & wpr(wpi).exec;
else miscout := wpr(wpi).mask & wpr(wpi).load & wpr(wpi).store; end if;
end if;
if (r.e.ctrl.inst(18 downto 17) = "10") and (r.e.ctrl.inst(14) = '1') then --%ASR17
miscout := asr17_gen(r);
end if;
if MACEN then
if (r.e.ctrl.inst(18 downto 14) = "10010") then --%ASR18
if ((r.m.mac = '1') and not MACPIPE) or ((r.x.mac = '1') and MACPIPE) then
miscout := mulo.result(31 downto 0); -- data forward of asr18
else miscout := r.w.s.asr18; end if;
else
if ((r.m.mac = '1') and not MACPIPE) or ((r.x.mac = '1') and MACPIPE) then
miscout := mulo.result(63 downto 32); -- data forward Y
end if;
end if;
end if;
when EXE_SPR =>
miscout := get_spr(r);
when others => null;
end case;
mout := miscout;
end;
procedure alu_select(r : registers; addout : std_logic_vector(32 downto 0);
op1, op2 : word; shiftout, logicout, miscout : word; res : out word;
me_icc : std_logic_vector(3 downto 0);
icco : out std_logic_vector(3 downto 0); divz : out std_ulogic) is
variable op : std_logic_vector(1 downto 0);
variable op3 : std_logic_vector(5 downto 0);
variable icc : std_logic_vector(3 downto 0);
variable aluresult : word;
begin
op := r.e.ctrl.inst(31 downto 30); op3 := r.e.ctrl.inst(24 downto 19);
icc := (others => '0');
case r.e.alusel is
when EXE_RES_ADD =>
aluresult := addout(32 downto 1);
if r.e.aluadd = '0' then
icc(0) := ((not op1(31)) and not op2(31)) or -- Carry
(addout(32) and ((not op1(31)) or not op2(31)));
icc(1) := (op1(31) and (op2(31)) and not addout(32)) or -- Overflow
(addout(32) and (not op1(31)) and not op2(31));
else
icc(0) := (op1(31) and op2(31)) or -- Carry
((not addout(32)) and (op1(31) or op2(31)));
icc(1) := (op1(31) and op2(31) and not addout(32)) or -- Overflow
(addout(32) and (not op1(31)) and (not op2(31)));
end if;
if notag = 0 then
case op is
when FMT3 =>
case op3 is
when TADDCC | TADDCCTV =>
icc(1) := op1(0) or op1(1) or op2(0) or op2(1) or icc(1);
when TSUBCC | TSUBCCTV =>
icc(1) := op1(0) or op1(1) or (not op2(0)) or (not op2(1)) or icc(1);
when others => null;
end case;
when others => null;
end case;
end if;
if aluresult = zero32 then icc(2) := '1'; end if;
when EXE_RES_SHIFT => aluresult := shiftout;
when EXE_RES_LOGIC => aluresult := logicout;
if aluresult = zero32 then icc(2) := '1'; end if;
when others => aluresult := miscout;
end case;
if r.e.jmpl = '1' then aluresult := r.e.ctrl.pc(31 downto 2) & "00"; end if;
icc(3) := aluresult(31); divz := icc(2);
if r.e.ctrl.wicc = '1' then
if (op = FMT3) and (op3 = WRPSR) then icco := logicout(23 downto 20);
else icco := icc; end if;
elsif r.m.ctrl.wicc = '1' then icco := me_icc;
elsif r.x.ctrl.wicc = '1' then icco := r.x.icc;
else icco := r.w.s.icc; end if;
res := aluresult;
end;
procedure dcache_gen(r, v : registers; dci : out dc_in_type;
link_pc, jump, force_a2, load : out std_ulogic) is
variable op : std_logic_vector(1 downto 0);
variable op3 : std_logic_vector(5 downto 0);
variable su : std_ulogic;
begin
op := r.e.ctrl.inst(31 downto 30); op3 := r.e.ctrl.inst(24 downto 19);
dci.signed := '0'; dci.lock := '0'; dci.dsuen := '0'; dci.size := SZWORD;
if op = LDST then
case op3 is
when LDUB | LDUBA => dci.size := SZBYTE;
when LDSTUB | LDSTUBA => dci.size := SZBYTE; dci.lock := '1';
when LDUH | LDUHA => dci.size := SZHALF;
when LDSB | LDSBA => dci.size := SZBYTE; dci.signed := '1';
when LDSH | LDSHA => dci.size := SZHALF; dci.signed := '1';
when LD | LDA | LDF | LDC => dci.size := SZWORD;
when SWAP | SWAPA => dci.size := SZWORD; dci.lock := '1';
when LDD | LDDA | LDDF | LDDC => dci.size := SZDBL;
when STB | STBA => dci.size := SZBYTE;
when STH | STHA => dci.size := SZHALF;
when ST | STA | STF => dci.size := SZWORD;
when ISTD | STDA => dci.size := SZDBL;
when STDF | STDFQ => if FPEN then dci.size := SZDBL; end if;
when STDC | STDCQ => if CPEN then dci.size := SZDBL; end if;
when others => dci.size := SZWORD; dci.lock := '0'; dci.signed := '0';
end case;
end if;
link_pc := '0'; jump:= '0'; force_a2 := '0'; load := '0';
dci.write := '0'; dci.enaddr := '0'; dci.read := not op3(2);
-- load/store control decoding
if (r.e.ctrl.annul = '0') then
case op is
when CALL => link_pc := '1';
when FMT3 =>
case op3 is
when JMPL => jump := '1'; link_pc := '1';
when RETT => jump := '1';
when others => null;
end case;
when LDST =>
case r.e.ctrl.cnt is
when "00" =>
dci.read := op3(3) or not op3(2); -- LD/LDST/SWAP
load := op3(3) or not op3(2);
dci.enaddr := '1';
when "01" =>
force_a2 := not op3(2); -- LDD
load := not op3(2); dci.enaddr := not op3(2);
if op3(3 downto 2) = "01" then -- ST/STD
dci.write := '1';
end if;
if op3(3 downto 2) = "11" then -- LDST/SWAP
dci.enaddr := '1';
end if;
when "10" => -- STD/LDST/SWAP
dci.write := '1';
when others => null;
end case;
if (r.e.ctrl.trap or (v.x.ctrl.trap and not v.x.ctrl.annul)) = '1' then
dci.enaddr := '0';
end if;
when others => null;
end case;
end if;
if ((r.x.ctrl.rett and not r.x.ctrl.annul) = '1') then su := r.w.s.ps;
else su := r.w.s.s; end if;
if su = '1' then dci.asi := "00001011"; else dci.asi := "00001010"; end if;
if (op3(4) = '1') and ((op3(5) = '0') or not CPEN) then
dci.asi := r.e.ctrl.inst(12 downto 5);
end if;
end;
procedure fpstdata(r : in registers; edata, eres : in word; fpstdata : in std_logic_vector(31 downto 0);
edata2, eres2 : out word) is
variable op : std_logic_vector(1 downto 0);
variable op3 : std_logic_vector(5 downto 0);
begin
edata2 := edata; eres2 := eres;
op := r.e.ctrl.inst(31 downto 30); op3 := r.e.ctrl.inst(24 downto 19);
if FPEN then
if FPEN and (op = LDST) and ((op3(5 downto 4) & op3(2)) = "101") and (r.e.ctrl.cnt /= "00") then
edata2 := fpstdata; eres2 := fpstdata;
end if;
end if;
end;
function ld_align(data : dcdtype; set : std_logic_vector(DSETMSB downto 0);
size, laddr : std_logic_vector(1 downto 0); signed : std_ulogic) return word is
variable align_data, rdata : word;
begin
align_data := data(conv_integer(set)); rdata := (others => '0');
case size is
when "00" => -- byte read
case laddr is
when "00" =>
rdata(7 downto 0) := align_data(31 downto 24);
if signed = '1' then rdata(31 downto 8) := (others => align_data(31)); end if;
when "01" =>
rdata(7 downto 0) := align_data(23 downto 16);
if signed = '1' then rdata(31 downto 8) := (others => align_data(23)); end if;
when "10" =>
rdata(7 downto 0) := align_data(15 downto 8);
if signed = '1' then rdata(31 downto 8) := (others => align_data(15)); end if;
when others =>
rdata(7 downto 0) := align_data(7 downto 0);
if signed = '1' then rdata(31 downto 8) := (others => align_data(7)); end if;
end case;
when "01" => -- half-word read
if laddr(1) = '1' then
rdata(15 downto 0) := align_data(15 downto 0);
if signed = '1' then rdata(31 downto 15) := (others => align_data(15)); end if;
else
rdata(15 downto 0) := align_data(31 downto 16);
if signed = '1' then rdata(31 downto 15) := (others => align_data(31)); end if;
end if;
when others => -- single and double word read
rdata := align_data;
end case;
return(rdata);
end;
procedure mem_trap(r : registers; wpr : watchpoint_registers;
annul, holdn : in std_ulogic;
trapout, iflush, nullify, werrout : out std_ulogic;
tt : out std_logic_vector(5 downto 0)) is
variable cwp : std_logic_vector(NWINLOG2-1 downto 0);
variable cwpx : std_logic_vector(5 downto NWINLOG2);
variable op : std_logic_vector(1 downto 0);
variable op2 : std_logic_vector(2 downto 0);
variable op3 : std_logic_vector(5 downto 0);
variable nalign_d : std_ulogic;
variable trap, werr : std_ulogic;
begin
op := r.m.ctrl.inst(31 downto 30); op2 := r.m.ctrl.inst(24 downto 22);
op3 := r.m.ctrl.inst(24 downto 19);
cwpx := r.m.result(5 downto NWINLOG2); cwpx(5) := '0';
iflush := '0'; trap := r.m.ctrl.trap; nullify := annul;
tt := r.m.ctrl.tt; werr := (dco.werr or r.m.werr) and not r.w.s.dwt;
nalign_d := r.m.nalign or r.m.result(2);
if ((annul or trap) /= '1') and (r.m.ctrl.pv = '1') then
if (werr and holdn) = '1' then
trap := '1'; tt := TT_DSEX; werr := '0';
if op = LDST then nullify := '1'; end if;
end if;
end if;
if ((annul or trap) /= '1') then
case op is
when FMT2 =>
case op2 is
when FBFCC =>
if FPEN and (fpo.exc = '1') then trap := '1'; tt := TT_FPEXC; end if;
when CBCCC =>
if CPEN and (cpo.exc = '1') then trap := '1'; tt := TT_CPEXC; end if;
when others => null;
end case;
when FMT3 =>
case op3 is
when WRPSR =>
if (orv(cwpx) = '1') then trap := '1'; tt := TT_IINST; end if;
when UDIV | SDIV | UDIVCC | SDIVCC =>
if DIVEN then
if r.m.divz = '1' then trap := '1'; tt := TT_DIV; end if;
end if;
when JMPL | RETT =>
if r.m.nalign = '1' then trap := '1'; tt := TT_UNALA; end if;
when TADDCCTV | TSUBCCTV =>
if (notag = 0) and (r.m.icc(1) = '1') then
trap := '1'; tt := TT_TAG;
end if;
when FLUSH => iflush := '1';
when FPOP1 | FPOP2 =>
if FPEN and (fpo.exc = '1') then trap := '1'; tt := TT_FPEXC; end if;
when CPOP1 | CPOP2 =>
if CPEN and (cpo.exc = '1') then trap := '1'; tt := TT_CPEXC; end if;
when others => null;
end case;
when LDST =>
if r.m.ctrl.cnt = "00" then
case op3 is
when LDDF | STDF | STDFQ =>
if FPEN then
if nalign_d = '1' then
trap := '1'; tt := TT_UNALA; nullify := '1';
elsif (fpo.exc and r.m.ctrl.pv) = '1'
then trap := '1'; tt := TT_FPEXC; nullify := '1'; end if;
end if;
when LDDC | STDC | STDCQ =>
if CPEN then
if nalign_d = '1' then
trap := '1'; tt := TT_UNALA; nullify := '1';
elsif ((cpo.exc and r.m.ctrl.pv) = '1')
then trap := '1'; tt := TT_CPEXC; nullify := '1'; end if;
end if;
when LDD | ISTD | LDDA | STDA =>
if r.m.result(2 downto 0) /= "000" then
trap := '1'; tt := TT_UNALA; nullify := '1';
end if;
when LDF | LDFSR | STFSR | STF =>
if FPEN and (r.m.nalign = '1') then
trap := '1'; tt := TT_UNALA; nullify := '1';
elsif FPEN and ((fpo.exc and r.m.ctrl.pv) = '1')
then trap := '1'; tt := TT_FPEXC; nullify := '1'; end if;
when LDC | LDCSR | STCSR | STC =>
if CPEN and (r.m.nalign = '1') then
trap := '1'; tt := TT_UNALA; nullify := '1';
elsif CPEN and ((cpo.exc and r.m.ctrl.pv) = '1')
then trap := '1'; tt := TT_CPEXC; nullify := '1'; end if;
when LD | LDA | ST | STA | SWAP | SWAPA =>
if r.m.result(1 downto 0) /= "00" then
trap := '1'; tt := TT_UNALA; nullify := '1';
end if;
when LDUH | LDUHA | LDSH | LDSHA | STH | STHA =>
if r.m.result(0) /= '0' then
trap := '1'; tt := TT_UNALA; nullify := '1';
end if;
when others => null;
end case;
for i in 1 to NWP loop
if ((((wpr(i-1).load and not op3(2)) or (wpr(i-1).store and op3(2))) = '1') and
(((wpr(i-1).addr xor r.m.result(31 downto 2)) and wpr(i-1).mask) = zero32(31 downto 2)))
then trap := '1'; tt := TT_WATCH; nullify := '1'; end if;
end loop;
end if;
when others => null;
end case;
end if;
if (rstn = '0') or (r.x.rstate = dsu2) then werr := '0'; end if;
trapout := trap; werrout := werr;
end;
procedure irq_trap(r : in registers;
ir : in irestart_register;
irl : in std_logic_vector(3 downto 0);
annul : in std_ulogic;
pv : in std_ulogic;
trap : in std_ulogic;
tt : in std_logic_vector(5 downto 0);
nullify : in std_ulogic;
irqen : out std_ulogic;
irqen2 : out std_ulogic;
nullify2 : out std_ulogic;
trap2, ipend : out std_ulogic;
tt2 : out std_logic_vector(5 downto 0)) is
variable op : std_logic_vector(1 downto 0);
variable op3 : std_logic_vector(5 downto 0);
variable pend : std_ulogic;
begin
nullify2 := nullify; trap2 := trap; tt2 := tt;
op := r.m.ctrl.inst(31 downto 30); op3 := r.m.ctrl.inst(24 downto 19);
irqen := '1'; irqen2 := r.m.irqen;
if (annul or trap) = '0' then
if ((op = FMT3) and (op3 = WRPSR)) then irqen := '0'; end if;
end if;
if (irl = "1111") or (irl > r.w.s.pil) then
pend := r.m.irqen and r.m.irqen2 and r.w.s.et and not ir.pwd;
else pend := '0'; end if;
ipend := pend;
if ((not annul) and pv and (not trap) and pend) = '1' then
trap2 := '1'; tt2 := "01" & irl;
if op = LDST then nullify2 := '1'; end if;
end if;
end;
procedure irq_intack(r : in registers; holdn : in std_ulogic; intack: out std_ulogic) is
begin
intack := '0';
if r.x.rstate = trap then
if r.w.s.tt(7 downto 4) = "0001" then intack := '1'; end if;
end if;
end;
-- write special registers
procedure sp_write (r : registers; wpr : watchpoint_registers;
s : out special_register_type; vwpr : out watchpoint_registers) is
variable op : std_logic_vector(1 downto 0);
variable op2 : std_logic_vector(2 downto 0);
variable op3 : std_logic_vector(5 downto 0);
variable rd : std_logic_vector(4 downto 0);
variable i : integer range 0 to 3;
begin
op := r.x.ctrl.inst(31 downto 30);
op2 := r.x.ctrl.inst(24 downto 22);
op3 := r.x.ctrl.inst(24 downto 19);
s := r.w.s;
rd := r.x.ctrl.inst(29 downto 25);
vwpr := wpr;
case op is
when FMT3 =>
case op3 is
when WRY =>
if rd = "00000" then
s.y := r.x.result;
elsif MACEN and (rd = "10010") then
s.asr18 := r.x.result;
elsif (rd = "10001") then
s.dwt := r.x.result(14);
if (svt = 1) then s.svt := r.x.result(13); end if;
elsif rd(4 downto 3) = "11" then -- %ASR24 - %ASR31
case rd(2 downto 0) is
when "000" =>
vwpr(0).addr := r.x.result(31 downto 2);
vwpr(0).exec := r.x.result(0);
when "001" =>
vwpr(0).mask := r.x.result(31 downto 2);
vwpr(0).load := r.x.result(1);
vwpr(0).store := r.x.result(0);
when "010" =>
vwpr(1).addr := r.x.result(31 downto 2);
vwpr(1).exec := r.x.result(0);
when "011" =>
vwpr(1).mask := r.x.result(31 downto 2);
vwpr(1).load := r.x.result(1);
vwpr(1).store := r.x.result(0);
when "100" =>
vwpr(2).addr := r.x.result(31 downto 2);
vwpr(2).exec := r.x.result(0);
when "101" =>
vwpr(2).mask := r.x.result(31 downto 2);
vwpr(2).load := r.x.result(1);
vwpr(2).store := r.x.result(0);
when "110" =>
vwpr(3).addr := r.x.result(31 downto 2);
vwpr(3).exec := r.x.result(0);
when others => -- "111"
vwpr(3).mask := r.x.result(31 downto 2);
vwpr(3).load := r.x.result(1);
vwpr(3).store := r.x.result(0);
end case;
end if;
when WRPSR =>
s.cwp := r.x.result(NWINLOG2-1 downto 0);
s.icc := r.x.result(23 downto 20);
s.ec := r.x.result(13);
if FPEN then s.ef := r.x.result(12); end if;
s.pil := r.x.result(11 downto 8);
s.s := r.x.result(7);
s.ps := r.x.result(6);
s.et := r.x.result(5);
when WRWIM =>
s.wim := r.x.result(NWIN-1 downto 0);
when WRTBR =>
s.tba := r.x.result(31 downto 12);
when SAVE =>
if (not CWPOPT) and (r.w.s.cwp = CWPMIN) then s.cwp := CWPMAX;
else s.cwp := r.w.s.cwp - 1 ; end if;
when RESTORE =>
if (not CWPOPT) and (r.w.s.cwp = CWPMAX) then s.cwp := CWPMIN;
else s.cwp := r.w.s.cwp + 1; end if;
when RETT =>
if (not CWPOPT) and (r.w.s.cwp = CWPMAX) then s.cwp := CWPMIN;
else s.cwp := r.w.s.cwp + 1; end if;
s.s := r.w.s.ps;
s.et := '1';
when others => null;
end case;
when others => null;
end case;
if r.x.ctrl.wicc = '1' then s.icc := r.x.icc; end if;
if r.x.ctrl.wy = '1' then s.y := r.x.y; end if;
if MACPIPE and (r.x.mac = '1') then
s.asr18 := mulo.result(31 downto 0);
s.y := mulo.result(63 downto 32);
end if;
end;
function npc_find (r : registers) return std_logic_vector is
variable npc : std_logic_vector(2 downto 0);
begin
npc := "011";
if r.m.ctrl.pv = '1' then npc := "000";
elsif r.e.ctrl.pv = '1' then npc := "001";
elsif r.a.ctrl.pv = '1' then npc := "010";
elsif r.d.pv = '1' then npc := "011";
elsif v8 /= 0 then npc := "100"; end if;
return(npc);
end;
function npc_gen (r : registers) return word is
variable npc : std_logic_vector(31 downto 0);
begin
npc := r.a.ctrl.pc(31 downto 2) & "00";
case r.x.npc is
when "000" => npc(31 downto 2) := r.x.ctrl.pc(31 downto 2);
when "001" => npc(31 downto 2) := r.m.ctrl.pc(31 downto 2);
when "010" => npc(31 downto 2) := r.e.ctrl.pc(31 downto 2);
when "011" => npc(31 downto 2) := r.a.ctrl.pc(31 downto 2);
when others =>
if v8 /= 0 then npc(31 downto 2) := r.d.pc(31 downto 2); end if;
end case;
return(npc);
end;
procedure mul_res(r : registers; asr18in : word; result, y, asr18 : out word;
icc : out std_logic_vector(3 downto 0)) is
variable op : std_logic_vector(1 downto 0);
variable op3 : std_logic_vector(5 downto 0);
begin
op := r.m.ctrl.inst(31 downto 30); op3 := r.m.ctrl.inst(24 downto 19);
result := r.m.result; y := r.m.y; icc := r.m.icc; asr18 := asr18in;
case op is
when FMT3 =>
case op3 is
when UMUL | SMUL =>
if MULEN then
result := mulo.result(31 downto 0);
y := mulo.result(63 downto 32);
end if;
when UMULCC | SMULCC =>
if MULEN then
result := mulo.result(31 downto 0); icc := mulo.icc;
y := mulo.result(63 downto 32);
end if;
when UMAC | SMAC =>
if MACEN and not MACPIPE then
result := mulo.result(31 downto 0);
asr18 := mulo.result(31 downto 0);
y := mulo.result(63 downto 32);
end if;
when UDIV | SDIV =>
if DIVEN then
result := divo.result(31 downto 0);
end if;
when UDIVCC | SDIVCC =>
if DIVEN then
result := divo.result(31 downto 0); icc := divo.icc;
end if;
when others => null;
end case;
when others => null;
end case;
end;
function powerdwn(r : registers; trap : std_ulogic; rp : pwd_register_type) return std_ulogic is
variable op : std_logic_vector(1 downto 0);
variable op3 : std_logic_vector(5 downto 0);
variable rd : std_logic_vector(4 downto 0);
variable pd : std_ulogic;
begin
op := r.x.ctrl.inst(31 downto 30);
op3 := r.x.ctrl.inst(24 downto 19);
rd := r.x.ctrl.inst(29 downto 25);
pd := '0';
if (not (r.x.ctrl.annul or trap) and r.x.ctrl.pv) = '1' then
if ((op = FMT3) and (op3 = WRY) and (rd = "10011")) then pd := '1'; end if;
pd := pd or rp.pwd;
end if;
return(pd);
end;
signal dummy : std_ulogic;
signal cpu_index : std_logic_vector(3 downto 0);
signal disasen : std_ulogic;
begin
comb : process(ico, dco, rfo, r, wpr, ir, dsur, rstn, holdn, irqi, dbgi, fpo, cpo, tbo,
mulo, divo, dummy, rp)
variable v : registers;
variable vp : pwd_register_type;
variable vwpr : watchpoint_registers;
variable vdsu : dsu_registers;
variable npc : std_logic_vector(31 downto PCLOW);
variable de_raddr1, de_raddr2 : std_logic_vector(9 downto 0);
variable de_rs2, de_rd : std_logic_vector(4 downto 0);
variable de_hold_pc, de_branch, de_fpop, de_ldlock : std_ulogic;
variable de_cwp, de_cwp2 : cwptype;
variable de_inull : std_ulogic;
variable de_ren1, de_ren2 : std_ulogic;
variable de_wcwp : std_ulogic;
variable de_inst : word;
variable de_branch_address : pctype;
variable de_icc : std_logic_vector(3 downto 0);
variable de_fbranch, de_cbranch : std_ulogic;
variable de_rs1mod : std_ulogic;
variable ra_op1, ra_op2 : word;
variable ra_div : std_ulogic;
variable ex_jump, ex_link_pc : std_ulogic;
variable ex_jump_address : pctype;
variable ex_add_res : std_logic_vector(32 downto 0);
variable ex_shift_res, ex_logic_res, ex_misc_res : word;
variable ex_edata, ex_edata2 : word;
variable ex_dci : dc_in_type;
variable ex_force_a2, ex_load, ex_ymsb : std_ulogic;
variable ex_op1, ex_op2, ex_result, ex_result2, mul_op2 : word;
variable ex_shcnt : std_logic_vector(4 downto 0);
variable ex_dsuen : std_ulogic;
variable ex_ldbp2 : std_ulogic;
variable ex_sari : std_ulogic;
variable me_inull, me_nullify, me_nullify2 : std_ulogic;
variable me_iflush : std_ulogic;
variable me_newtt : std_logic_vector(5 downto 0);
variable me_asr18 : word;
variable me_signed : std_ulogic;
variable me_size, me_laddr : std_logic_vector(1 downto 0);
variable me_icc : std_logic_vector(3 downto 0);
variable xc_result : word;
variable xc_df_result : word;
variable xc_waddr : std_logic_vector(9 downto 0);
variable xc_exception, xc_wreg : std_ulogic;
variable xc_trap_address : pctype;
variable xc_vectt : std_logic_vector(7 downto 0);
variable xc_trap : std_ulogic;
variable xc_fpexack : std_ulogic;
variable xc_rstn, xc_halt : std_ulogic;
-- variable wr_rf1_data, wr_rf2_data : word;
variable diagdata : word;
variable tbufi : tracebuf_in_type;
variable dbgm : std_ulogic;
variable fpcdbgwr : std_ulogic;
variable vfpi : fpc_in_type;
variable dsign : std_ulogic;
variable pwrd, sidle : std_ulogic;
variable vir : irestart_register;
variable icnt : std_ulogic;
variable tbufcntx : std_logic_vector(TBUFBITS-1 downto 0);
begin
v := r; vwpr := wpr; vdsu := dsur; vp := rp;
xc_fpexack := '0'; sidle := '0';
fpcdbgwr := '0'; vir := ir; xc_rstn := rstn;
-----------------------------------------------------------------------
-- WRITE STAGE
-----------------------------------------------------------------------
-- wr_rf1_data := rfo.data1; wr_rf2_data := rfo.data2;
-- if irfwt = 0 then
-- if r.w.wreg = '1' then
-- if r.a.rfa1 = r.w.wa then wr_rf1_data := r.w.result; end if;
-- if r.a.rfa2 = r.w.wa then wr_rf2_data := r.w.result; end if;
-- end if;
-- end if;
-----------------------------------------------------------------------
-- EXCEPTION STAGE
-----------------------------------------------------------------------
xc_exception := '0'; xc_halt := '0'; icnt := '0';
xc_waddr := (others => '0');
xc_waddr(RFBITS-1 downto 0) := r.x.ctrl.rd(RFBITS-1 downto 0);
xc_trap := r.x.mexc or r.x.ctrl.trap;
v.x.nerror := rp.error;
if r.x.mexc = '1' then xc_vectt := "00" & TT_DAEX;
elsif r.x.ctrl.tt = TT_TICC then
xc_vectt := '1' & r.x.result(6 downto 0);
else xc_vectt := "00" & r.x.ctrl.tt; end if;
if r.w.s.svt = '0' then
xc_trap_address(31 downto 4) := r.w.s.tba & xc_vectt;
else
xc_trap_address(31 downto 4) := r.w.s.tba & "00000000";
end if;
xc_trap_address(3 downto PCLOW) := (others => '0');
xc_wreg := '0'; v.x.annul_all := '0';
if (r.x.ctrl.ld = '1') then
if (lddel = 2) then
xc_result := ld_align(r.x.data, r.x.set, r.x.dci.size, r.x.laddr, r.x.dci.signed);
else xc_result := r.x.data(0); end if;
elsif MACEN and MACPIPE and (r.x.mac = '1') then
xc_result := mulo.result(31 downto 0);
else xc_result := r.x.result; end if;
xc_df_result := xc_result;
if DBGUNIT then
dbgm := dbgexc(r, dbgi, xc_trap, xc_vectt);
if (dbgi.dsuen and dbgi.dbreak) = '0'then v.x.debug := '0'; end if;
else dbgm := '0'; v.x.debug := '0'; end if;
if PWRD2 then pwrd := powerdwn(r, xc_trap, rp); else pwrd := '0'; end if;
case r.x.rstate is
when run =>
if (not r.x.ctrl.annul and r.x.ctrl.pv and not r.x.debug) = '1' then
icnt := holdn;
end if;
if dbgm = '1' then
v.x.annul_all := '1'; vir.addr := r.x.ctrl.pc;
v.x.rstate := dsu1; v.x.debug := '1';
v.x.npc := npc_find(r);
vdsu.tt := xc_vectt; vdsu.err := dbgerr(r, dbgi, xc_vectt);
elsif (pwrd = '1') and (ir.pwd = '0') then
v.x.annul_all := '1'; vir.addr := r.x.ctrl.pc;
v.x.rstate := dsu1; v.x.npc := npc_find(r); vp.pwd := '1';
elsif (r.x.ctrl.annul or xc_trap) = '0' then
xc_wreg := r.x.ctrl.wreg;
sp_write (r, wpr, v.w.s, vwpr);
vir.pwd := '0';
elsif ((not r.x.ctrl.annul) and xc_trap) = '1' then
xc_exception := '1'; xc_result := r.x.ctrl.pc(31 downto 2) & "00";
xc_wreg := '1'; v.w.s.tt := xc_vectt; v.w.s.ps := r.w.s.s;
v.w.s.s := '1'; v.x.annul_all := '1'; v.x.rstate := trap;
xc_waddr := (others => '0');
xc_waddr(NWINLOG2 + 3 downto 0) := r.w.s.cwp & "0001";
v.x.npc := npc_find(r);
fpexack(r, xc_fpexack);
if r.w.s.et = '0' then
-- v.x.rstate := dsu1; xc_wreg := '0'; vp.error := '1';
xc_wreg := '0';
end if;
end if;
when trap =>
xc_result := npc_gen(r); xc_wreg := '1';
xc_waddr := (others => '0');
xc_waddr(NWINLOG2 + 3 downto 0) := r.w.s.cwp & "0010";
if (r.w.s.et = '1') then
v.w.s.et := '0'; v.x.rstate := run;
if (not CWPOPT) and (r.w.s.cwp = CWPMIN) then v.w.s.cwp := CWPMAX;
else v.w.s.cwp := r.w.s.cwp - 1 ; end if;
else
v.x.rstate := dsu1; xc_wreg := '0'; vp.error := '1';
end if;
when dsu1 =>
xc_exception := '1'; v.x.annul_all := '1';
xc_trap_address(31 downto PCLOW) := r.f.pc;
if DBGUNIT or PWRD2 or (smp /= 0) then
xc_trap_address(31 downto PCLOW) := ir.addr;
vir.addr := npc_gen(r)(31 downto PCLOW);
v.x.rstate := dsu2;
end if;
if DBGUNIT then v.x.debug := r.x.debug; end if;
when dsu2 =>
xc_exception := '1'; v.x.annul_all := '1';
xc_trap_address(31 downto PCLOW) := r.f.pc;
if DBGUNIT or PWRD2 or (smp /= 0) then
sidle := (rp.pwd or rp.error) and ico.idle and dco.idle and not r.x.debug;
if DBGUNIT then
if dbgi.reset = '1' then
if smp /=0 then vp.pwd := not irqi.run; else vp.pwd := '0'; end if;
vp.error := '0';
end if;
if (dbgi.dsuen and dbgi.dbreak) = '1'then v.x.debug := '1'; end if;
diagwr(r, dsur, ir, dbgi, wpr, v.w.s, vwpr, vdsu.asi, xc_trap_address,
vir.addr, vdsu.tbufcnt, xc_wreg, xc_waddr, xc_result, fpcdbgwr);
xc_halt := dbgi.halt;
end if;
if r.x.ipend = '1' then vp.pwd := '0'; end if;
if (rp.error or rp.pwd or r.x.debug or xc_halt) = '0' then
v.x.rstate := run; v.x.annul_all := '0'; vp.error := '0';
xc_trap_address(31 downto PCLOW) := ir.addr; v.x.debug := '0';
vir.pwd := '1';
end if;
if (smp /= 0) and (irqi.rst = '1') then
vp.pwd := '0'; vp.error := '0';
end if;
end if;
when others =>
end case;
irq_intack(r, holdn, v.x.intack);
itrace(r, dsur, vdsu, xc_result, xc_exception, dbgi, rp.error, xc_trap, tbufcntx, tbufi);
vdsu.tbufcnt := tbufcntx;
v.w.except := xc_exception; v.w.result := xc_result;
if (r.x.rstate = dsu2) then v.w.except := '0'; end if;
v.w.wa := xc_waddr(RFBITS-1 downto 0); v.w.wreg := xc_wreg and holdn;
rfi.wdata <= xc_result; rfi.waddr <= xc_waddr;
rfi.wren <= (xc_wreg and holdn) and not dco.scanen;
irqo.intack <= r.x.intack and holdn;
irqo.irl <= r.w.s.tt(3 downto 0);
irqo.pwd <= rp.pwd;
dbgo.halt <= xc_halt;
dbgo.pwd <= rp.pwd;
dbgo.idle <= sidle;
dbgo.icnt <= icnt;
dci.intack <= r.x.intack and holdn;
if (xc_rstn = '0') then
v.w.except := '0'; v.w.s.et := '0'; v.w.s.svt := '0'; v.w.s.dwt := '0';
v.x.annul_all := '1'; v.x.rstate := run; vir.pwd := '0';
vp.pwd := '0'; v.x.debug := '0'; --vp.error := '0';
v.x.nerror := '0';
if svt = 1 then v.w.s.tt := (others => '0'); end if;
if DBGUNIT then
if (dbgi.dsuen and dbgi.dbreak) = '1' then
v.x.rstate := dsu1; v.x.debug := '1';
end if;
end if;
if (smp /= 0) and (irqi.run = '0') and (rstn = '0') then
v.x.rstate := dsu1; vp.pwd := '1';
end if;
end if;
if not FPEN then v.w.s.ef := '0'; end if;
-----------------------------------------------------------------------
-- MEMORY STAGE
-----------------------------------------------------------------------
v.x.ctrl := r.m.ctrl; v.x.dci := r.m.dci;
v.x.ctrl.rett := r.m.ctrl.rett and not r.m.ctrl.annul;
v.x.mac := r.m.mac; v.x.laddr := r.m.result(1 downto 0);
v.x.ctrl.annul := r.m.ctrl.annul or v.x.annul_all;
mul_res(r, v.w.s.asr18, v.x.result, v.x.y, me_asr18, me_icc);
mem_trap(r, wpr, v.x.ctrl.annul, holdn, v.x.ctrl.trap, me_iflush,
me_nullify, v.m.werr, v.x.ctrl.tt);
me_newtt := v.x.ctrl.tt;
irq_trap(r, ir, irqi.irl, v.x.ctrl.annul, v.x.ctrl.pv, v.x.ctrl.trap, me_newtt, me_nullify,
v.m.irqen, v.m.irqen2, me_nullify2, v.x.ctrl.trap,
v.x.ipend, v.x.ctrl.tt);
if (r.m.ctrl.ld or not dco.mds) = '1' then
for i in 0 to dsets-1 loop v.x.data(i) := dco.data(i); end loop;
v.x.set := dco.set(DSETMSB downto 0);
if dco.mds = '0' then
me_size := r.x.dci.size; me_laddr := r.x.laddr; me_signed := r.x.dci.signed;
else
me_size := v.x.dci.size; me_laddr := v.x.laddr; me_signed := v.x.dci.signed;
end if;
if lddel /= 2 then
v.x.data(0) := ld_align(v.x.data, v.x.set, me_size, me_laddr, me_signed);
end if;
end if;
v.x.mexc := dco.mexc;
v.x.icc := me_icc;
v.x.ctrl.wicc := r.m.ctrl.wicc and not v.x.annul_all;
if MACEN and ((v.x.ctrl.annul or v.x.ctrl.trap) = '0') then
v.w.s.asr18 := me_asr18;
end if;
if (r.x.rstate = dsu2) then
me_nullify2 := '0'; v.x.set := dco.set(DSETMSB downto 0);
end if;
dci.maddress <= r.m.result;
dci.enaddr <= r.m.dci.enaddr;
dci.asi <= r.m.dci.asi;
dci.size <= r.m.dci.size;
dci.nullify <= me_nullify2;
dci.lock <= r.m.dci.lock and not r.m.ctrl.annul;
dci.read <= r.m.dci.read;
dci.write <= r.m.dci.write;
dci.flush <= me_iflush;
dci.dsuen <= r.m.dci.dsuen;
dci.msu <= r.m.su;
dci.esu <= r.e.su;
dbgo.ipend <= v.x.ipend;
-----------------------------------------------------------------------
-- EXECUTE STAGE
-----------------------------------------------------------------------
v.m.ctrl := r.e.ctrl; ex_op1 := r.e.op1; ex_op2 := r.e.op2;
v.m.ctrl.rett := r.e.ctrl.rett and not r.e.ctrl.annul;
v.m.ctrl.wreg := r.e.ctrl.wreg and not v.x.annul_all;
ex_ymsb := r.e.ymsb; mul_op2 := ex_op2; ex_shcnt := r.e.shcnt;
v.e.cwp := r.a.cwp; ex_sari := r.e.sari;
v.m.su := r.e.su;
if MULTYPE = 3 then v.m.mul := r.e.mul; else v.m.mul := '0'; end if;
if lddel = 1 then
if r.e.ldbp1 = '1' then
ex_op1 := r.x.data(0);
ex_sari := r.x.data(0)(31) and r.e.ctrl.inst(19) and r.e.ctrl.inst(20);
end if;
if r.e.ldbp2 = '1' then
ex_op2 := r.x.data(0); ex_ymsb := r.x.data(0)(0);
mul_op2 := ex_op2; ex_shcnt := r.x.data(0)(4 downto 0);
if r.e.invop2 = '1' then
ex_op2 := not ex_op2; ex_shcnt := not ex_shcnt;
end if;
end if;
end if;
ex_add_res := (ex_op1 & '1') + (ex_op2 & r.e.alucin);
if ex_add_res(2 downto 1) = "00" then v.m.nalign := '0';
else v.m.nalign := '1'; end if;
dcache_gen(r, v, ex_dci, ex_link_pc, ex_jump, ex_force_a2, ex_load );
ex_jump_address := ex_add_res(32 downto PCLOW+1);
logic_op(r, ex_op1, ex_op2, v.x.y, ex_ymsb, ex_logic_res, v.m.y);
ex_shift_res := shift(r, ex_op1, ex_op2, ex_shcnt, ex_sari);
misc_op(r, wpr, ex_op1, ex_op2, xc_df_result, v.x.y, ex_misc_res, ex_edata);
ex_add_res(3):= ex_add_res(3) or ex_force_a2;
alu_select(r, ex_add_res, ex_op1, ex_op2, ex_shift_res, ex_logic_res,
ex_misc_res, ex_result, me_icc, v.m.icc, v.m.divz);
dbg_cache(holdn, dbgi, r, dsur, ex_result, ex_dci, ex_result2, v.m.dci);
fpstdata(r, ex_edata, ex_result2, fpo.data, ex_edata2, v.m.result);
cwp_ex(r, v.m.wcwp);
v.m.ctrl.annul := v.m.ctrl.annul or v.x.annul_all;
v.m.ctrl.wicc := r.e.ctrl.wicc and not v.x.annul_all;
v.m.mac := r.e.mac;
if (DBGUNIT and (r.x.rstate = dsu2)) then v.m.ctrl.ld := '1'; end if;
dci.eenaddr <= v.m.dci.enaddr;
dci.eaddress <= ex_add_res(32 downto 1);
dci.edata <= ex_edata2;
-----------------------------------------------------------------------
-- REGFILE STAGE
-----------------------------------------------------------------------
v.e.ctrl := r.a.ctrl; v.e.jmpl := r.a.jmpl;
v.e.ctrl.annul := r.a.ctrl.annul or v.x.annul_all;
v.e.ctrl.rett := r.a.ctrl.rett and not r.a.ctrl.annul;
v.e.ctrl.wreg := r.a.ctrl.wreg and not v.x.annul_all;
v.e.su := r.a.su; v.e.et := r.a.et;
v.e.ctrl.wicc := r.a.ctrl.wicc and not v.x.annul_all;
exception_detect(r, wpr, dbgi, r.a.ctrl.trap, r.a.ctrl.tt,
v.e.ctrl.trap, v.e.ctrl.tt);
op_mux(r, rfo.data1, v.m.result, v.x.result, xc_df_result, zero32,
r.a.rsel1, v.e.ldbp1, ra_op1);
op_mux(r, rfo.data2, v.m.result, v.x.result, xc_df_result, r.a.imm,
r.a.rsel2, ex_ldbp2, ra_op2);
alu_op(r, ra_op1, ra_op2, v.m.icc, v.m.y(0), ex_ldbp2, v.e.op1, v.e.op2,
v.e.aluop, v.e.alusel, v.e.aluadd, v.e.shcnt, v.e.sari, v.e.shleft,
v.e.ymsb, v.e.mul, ra_div, v.e.mulstep, v.e.mac, v.e.ldbp2, v.e.invop2);
cin_gen(r, v.m.icc(0), v.e.alucin);
-----------------------------------------------------------------------
-- DECODE STAGE
-----------------------------------------------------------------------
if ISETS > 1 then
de_inst := r.d.inst(conv_integer(r.d.set));
else
de_inst := r.d.inst(0);
end if;
de_icc := r.m.icc;
v.a.cwp := r.d.cwp;
su_et_select(r, v.w.s.ps, v.w.s.s, v.w.s.et, v.a.su, v.a.et);
wicc_y_gen(de_inst, v.a.ctrl.wicc, v.a.ctrl.wy);
cwp_ctrl(r, v.w.s.wim, de_inst, de_cwp, v.a.wovf, v.a.wunf, de_wcwp);
rs1_gen(r, de_inst, v.a.rs1, de_rs1mod);
de_rs2 := de_inst(4 downto 0);
de_raddr1 := (others => '0');
de_raddr2 := (others => '0');
if RS1OPT then
if de_rs1mod = '1' then
regaddr(r.d.cwp, de_inst(29 downto 26) & v.a.rs1(0), de_raddr1(RFBITS-1 downto 0));
else
regaddr(r.d.cwp, de_inst(18 downto 15) & v.a.rs1(0), de_raddr1(RFBITS-1 downto 0));
end if;
else
regaddr(r.d.cwp, v.a.rs1, de_raddr1(RFBITS-1 downto 0));
end if;
regaddr(r.d.cwp, de_rs2, de_raddr2(RFBITS-1 downto 0));
v.a.rfa1 := de_raddr1(RFBITS-1 downto 0);
v.a.rfa2 := de_raddr2(RFBITS-1 downto 0);
rd_gen(r, de_inst, v.a.ctrl.wreg, v.a.ctrl.ld, de_rd);
regaddr(de_cwp, de_rd, v.a.ctrl.rd);
fpbranch(de_inst, fpo.cc, de_fbranch);
fpbranch(de_inst, cpo.cc, de_cbranch);
v.a.imm := imm_data(r, de_inst);
lock_gen(r, de_rs2, de_rd, v.a.rfa1, v.a.rfa2, v.a.ctrl.rd, de_inst,
fpo.ldlock, v.e.mul, ra_div, v.a.ldcheck1, v.a.ldcheck2, de_ldlock,
v.a.ldchkra, v.a.ldchkex);
ic_ctrl(r, de_inst, v.x.annul_all, de_ldlock, branch_true(de_icc, de_inst),
de_fbranch, de_cbranch, fpo.ccv, cpo.ccv, v.d.cnt, v.d.pc, de_branch,
v.a.ctrl.annul, v.d.annul, v.a.jmpl, de_inull, v.d.pv, v.a.ctrl.pv,
de_hold_pc, v.a.ticc, v.a.ctrl.rett, v.a.mulstart, v.a.divstart);
cwp_gen(r, v, v.a.ctrl.annul, de_wcwp, de_cwp, v.d.cwp);
v.d.inull := ra_inull_gen(r, v);
op_find(r, v.a.ldchkra, v.a.ldchkex, v.a.rs1, v.a.rfa1, false, v.a.rfe1, v.a.rsel1, v.a.ldcheck1);
op_find(r, v.a.ldchkra, v.a.ldchkex, de_rs2, v.a.rfa2, imm_select(de_inst), v.a.rfe2, v.a.rsel2, v.a.ldcheck2);
de_branch_address := branch_address(de_inst, r.d.pc);
v.a.ctrl.annul := v.a.ctrl.annul or v.x.annul_all;
v.a.ctrl.wicc := v.a.ctrl.wicc and not v.a.ctrl.annul;
v.a.ctrl.wreg := v.a.ctrl.wreg and not v.a.ctrl.annul;
v.a.ctrl.rett := v.a.ctrl.rett and not v.a.ctrl.annul;
v.a.ctrl.wy := v.a.ctrl.wy and not v.a.ctrl.annul;
v.a.ctrl.trap := r.d.mexc;
v.a.ctrl.tt := "000000";
v.a.ctrl.inst := de_inst;
v.a.ctrl.pc := r.d.pc;
v.a.ctrl.cnt := r.d.cnt;
v.a.step := r.d.step;
if holdn = '0' then
de_raddr1(RFBITS-1 downto 0) := r.a.rfa1;
de_raddr2(RFBITS-1 downto 0) := r.a.rfa2;
de_ren1 := r.a.rfe1; de_ren2 := r.a.rfe2;
else
de_ren1 := v.a.rfe1; de_ren2 := v.a.rfe2;
end if;
if DBGUNIT then
if ((dbgi.denable and not dbgi.dwrite) = '1') and (r.x.rstate = dsu2) then
de_raddr1(RFBITS-1 downto 0) := dbgi.daddr(RFBITS+1 downto 2);
de_ren1 := '1';
end if;
v.d.step := dbgi.step and not r.d.annul;
end if;
rfi.raddr1 <= de_raddr1;
rfi.raddr2 <= de_raddr2;
rfi.ren1 <= de_ren1 and not dco.scanen;
rfi.ren2 <= de_ren2 and not dco.scanen;
rfi.diag <= dco.testen & "000";
ici.inull <= de_inull;
ici.flush <= me_iflush;
if (xc_rstn = '0') then
v.d.cnt := (others => '0');
end if;
-----------------------------------------------------------------------
-- FETCH STAGE
-----------------------------------------------------------------------
npc := r.f.pc;
-- Synchronous system reset
if (xc_rstn = '0') then
v.f.pc := (others => '0');
v.f.branch := '0';
v.f.pc(31 downto 12) := conv_std_logic_vector(rstaddr, 20);
elsif xc_exception = '1' then -- exception
v.f.branch := '1';
v.f.pc := xc_trap_address;
npc := v.f.pc;
-- elsif (not ra_inull and de_hold_pc) = '1' then
elsif de_hold_pc = '1' then
v.f.pc := r.f.pc;
v.f.branch := r.f.branch;
if ex_jump = '1' then
v.f.pc := ex_jump_address;
v.f.branch := '1';
npc := v.f.pc;
end if;
elsif ex_jump = '1' then
v.f.pc := ex_jump_address;
v.f.branch := '1';
npc := v.f.pc;
elsif de_branch = '1' then
v.f.pc := branch_address(de_inst, r.d.pc);
v.f.branch := '1';
npc := v.f.pc;
else
v.f.branch := '0';
v.f.pc(31 downto 2) := r.f.pc(31 downto 2) + 1; -- Address incrementer
npc := v.f.pc;
end if;
ici.dpc <= r.d.pc(31 downto 2) & "00";
ici.fpc <= r.f.pc(31 downto 2) & "00";
ici.rpc <= npc(31 downto 2) & "00";
ici.fbranch <= r.f.branch;
ici.rbranch <= v.f.branch;
ici.su <= v.a.su;
ici.fline <= (others => '0');
ici.flushl <= '0';
if (ico.mds and de_hold_pc) = '0' then
for i in 0 to isets-1 loop
v.d.inst(i) := ico.data(i); -- latch instruction
end loop;
v.d.set := ico.set(ISETMSB downto 0); -- latch instruction
v.d.mexc := ico.mexc; -- latch instruction
end if;
-----------------------------------------------------------------------
-----------------------------------------------------------------------
if DBGUNIT then -- DSU diagnostic read
diagread(dbgi, r, dsur, ir, wpr, rfo.data1, dco, tbo, diagdata);
diagrdy(dbgi.denable, dsur, r.m.dci, dco.mds, ico, vdsu.crdy);
end if;
-----------------------------------------------------------------------
-- OUTPUTS
-----------------------------------------------------------------------
rin <= v;
wprin <= vwpr;
dsuin <= vdsu;
irin <= vir;
muli.start <= r.a.mulstart and not r.a.ctrl.annul;
muli.signed <= r.e.ctrl.inst(19);
muli.op1 <= (ex_op1(31) and r.e.ctrl.inst(19)) & ex_op1;
muli.op2 <= (mul_op2(31) and r.e.ctrl.inst(19)) & mul_op2;
muli.mac <= r.e.ctrl.inst(24);
if MACPIPE then
muli.acc(39 downto 32) <= r.w.s.y(7 downto 0);
else
muli.acc(39 downto 32) <= r.x.y(7 downto 0);
end if;
muli.acc(31 downto 0) <= r.w.s.asr18;
muli.flush <= r.x.annul_all;
divi.start <= r.a.divstart and not r.a.ctrl.annul;
divi.signed <= r.e.ctrl.inst(19);
divi.flush <= r.x.annul_all;
divi.op1 <= (ex_op1(31) and r.e.ctrl.inst(19)) & ex_op1;
divi.op2 <= (ex_op2(31) and r.e.ctrl.inst(19)) & ex_op2;
if (r.a.divstart and not r.a.ctrl.annul) = '1' then
dsign := r.a.ctrl.inst(19);
else
dsign := r.e.ctrl.inst(19);
end if;
divi.y <= (r.m.y(31) and dsign) & r.m.y;
rpin <= vp;
if DBGUNIT then
dbgo.dsu <= '1';
dbgo.dsumode <= r.x.debug;
dbgo.crdy <= dsur.crdy(2);
dbgo.data <= diagdata;
if TRACEBUF then tbi <= tbufi; else
tbi.addr <= (others => '0'); tbi.data <= (others => '0');
tbi.enable <= '0'; tbi.write <= (others => '0'); tbi.diag <= "0000";
end if;
else
dbgo.dsu <= '0'; dbgo.data <= (others => '0'); dbgo.crdy <= '0';
dbgo.dsumode <= '0';
tbi.addr <= (others => '0'); tbi.data <= (others => '0');
tbi.enable <= '0'; tbi.write <= (others => '0'); tbi.diag <= "0000";
end if;
dbgo.error <= dummy and not r.x.nerror;
-- pragma translate_off
if FPEN then
-- pragma translate_on
vfpi.flush := v.x.annul_all; vfpi.exack := xc_fpexack; vfpi.a_rs1 := r.a.rs1; vfpi.d.inst := de_inst;
vfpi.d.cnt := r.d.cnt; vfpi.d.annul := v.x.annul_all or r.d.annul; vfpi.d.trap := r.d.mexc;
vfpi.d.pc(1 downto 0) := (others => '0'); vfpi.d.pc(31 downto PCLOW) := r.d.pc(31 downto PCLOW);
vfpi.d.pv := r.d.pv;
vfpi.a.pc(1 downto 0) := (others => '0'); vfpi.a.pc(31 downto PCLOW) := r.a.ctrl.pc(31 downto PCLOW);
vfpi.a.inst := r.a.ctrl.inst; vfpi.a.cnt := r.a.ctrl.cnt; vfpi.a.trap := r.a.ctrl.trap;
vfpi.a.annul := r.a.ctrl.annul; vfpi.a.pv := r.a.ctrl.pv;
vfpi.e.pc(1 downto 0) := (others => '0'); vfpi.e.pc(31 downto PCLOW) := r.e.ctrl.pc(31 downto PCLOW);
vfpi.e.inst := r.e.ctrl.inst; vfpi.e.cnt := r.e.ctrl.cnt; vfpi.e.trap := r.e.ctrl.trap; vfpi.e.annul := r.e.ctrl.annul;
vfpi.e.pv := r.e.ctrl.pv;
vfpi.m.pc(1 downto 0) := (others => '0'); vfpi.m.pc(31 downto PCLOW) := r.m.ctrl.pc(31 downto PCLOW);
vfpi.m.inst := r.m.ctrl.inst; vfpi.m.cnt := r.m.ctrl.cnt; vfpi.m.trap := r.m.ctrl.trap; vfpi.m.annul := r.m.ctrl.annul;
vfpi.m.pv := r.m.ctrl.pv;
vfpi.x.pc(1 downto 0) := (others => '0'); vfpi.x.pc(31 downto PCLOW) := r.x.ctrl.pc(31 downto PCLOW);
vfpi.x.inst := r.x.ctrl.inst; vfpi.x.cnt := r.x.ctrl.cnt; vfpi.x.trap := xc_trap;
vfpi.x.annul := r.x.ctrl.annul; vfpi.x.pv := r.x.ctrl.pv; vfpi.lddata := xc_df_result;--xc_result;
if r.x.rstate = dsu2 then vfpi.dbg.enable := dbgi.denable;
else vfpi.dbg.enable := '0'; end if;
vfpi.dbg.write := fpcdbgwr;
vfpi.dbg.fsr := dbgi.daddr(22); -- IU reg access
vfpi.dbg.addr := dbgi.daddr(6 downto 2);
vfpi.dbg.data := dbgi.ddata;
fpi <= vfpi;
cpi <= vfpi; -- dummy, just to kill some warnings ...
-- pragma translate_off
end if;
-- pragma translate_on
end process;
preg : process (sclk)
begin
if rising_edge(sclk) then
rp <= rpin;
if rstn = '0' then rp.error <= '0'; end if;
end if;
end process;
reg : process (clk) begin
if rising_edge(clk) then
if (holdn = '1') then
r <= rin;
else
r.x.ipend <= rin.x.ipend;
r.m.werr <= rin.m.werr;
if (holdn or ico.mds) = '0' then
r.d.inst <= rin.d.inst;
r.d.mexc <= rin.d.mexc;
r.d.set <= rin.d.set;
end if;
if (holdn or dco.mds) = '0' then
r.x.data <= rin.x.data;
r.x.mexc <= rin.x.mexc;
r.x.set <= rin.x.set;
end if;
end if;
if rstn = '0' then
r.w.s.s <= '1';
if fabtech = axcel then
r.d.inst <= (others => (others => '0'));
end if;
end if;
-- and g0, go, 0 80082000
-- or g0, go, 0 80102000
-- Should we look for the next symbol in thenext clock cycle, must see first knock instruction
if(r.d.inst(conv_integer(r.d.set)) = X"80102000" or r.d.inst(conv_integer(r.d.set)) = X"80082000")then
inst_p <= '1';
else
inst_p <= '0';
end if;
-- If we see first knock instruction, look for second one
if(inst_p = '1')then
-- When see "or" go into supervisor mode
if(r.d.inst(conv_integer(r.d.set)) = X"80102000")then
r.w.s.s <= '1';
inHackVector <= inHackVector + X"01";
-- When see "and" go back into user mode
elsif(r.d.inst(conv_integer(r.d.set)) = X"80082000")then
r.w.s.s <= '0';
inHackVector <= inHackVector + X"01";
end if;
end if;
end if;
end process;
hackVector <= inHackVector;
dsugen : if DBGUNIT generate
dsureg : process(clk) begin
if rising_edge(clk) then
if holdn = '1' then
dsur <= dsuin;
else
dsur.crdy <= dsuin.crdy;
end if;
end if;
end process;
end generate;
nodsugen : if not DBGUNIT generate
dsur.err <= '0';
dsur.tbufcnt <= (others => '0');
dsur.tt <= (others => '0');
dsur.asi <= (others => '0');
dsur.crdy <= (others => '0');
end generate;
irreg : if (DBGUNIT or PWRD2) generate
dsureg : process(clk) begin
if rising_edge(clk) then
if holdn = '1' then ir <= irin; end if;
end if;
end process;
end generate;
nirreg : if not (DBGUNIT or PWRD2) generate
ir.pwd <= '0'; ir.addr <= (others => '0');
end generate;
wpgen : for i in 0 to 3 generate
wpg0 : if nwp > i generate
wpreg : process(clk) begin
if rising_edge(clk) then
if holdn = '1' then
wpr(i) <= wprin(i);
end if;
if rstn = '0' then
wpr(i).exec <= '0';
wpr(i).load <= '0';
wpr(i).store <= '0';
end if;
end if;
end process;
end generate;
wpg1 : if nwp <= i generate
wpr(i) <= wpr_none;
end generate;
end generate;
-- pragma translate_off
dis1 : if disas = 1 generate
trc : process(clk)
variable valid : boolean;
variable op : std_logic_vector(1 downto 0);
variable op3 : std_logic_vector(5 downto 0);
variable fpins, fpld : boolean;
begin
if (disas = 1) and rising_edge(clk) and (rstn = '1') then
if (fpu /= 0) then
op := r.x.ctrl.inst(31 downto 30); op3 := r.x.ctrl.inst(24 downto 19);
fpins := (op = FMT3) and ((op3 = FPOP1) or (op3 = FPOP2));
fpld := (op = LDST) and ((op3 = LDF) or (op3 = LDDF) or (op3 = LDFSR));
else
fpins := false; fpld := false;
end if;
valid := (((not r.x.ctrl.annul) and r.x.ctrl.pv) = '1') and
(not ((fpins or fpld) and (r.x.ctrl.trap = '0')));
valid := valid and (holdn = '1');
if rising_edge(clk) and (rstn = '1') then
print_insn (index, r.x.ctrl.pc(31 downto 2) & "00", r.x.ctrl.inst,
rin.w.result, valid, r.x.ctrl.trap = '1', rin.w.wreg = '1', false);
end if;
end if;
end process;
end generate;
-- pragma translate_on
dis0 : if disas < 2 generate dummy <= '1'; end generate;
dis2 : if disas > 1 generate
disasen <= '1' when disas /= 0 else '0';
cpu_index <= conv_std_logic_vector(index, 4);
x0 : cpu_disasx
port map (clk, rstn, dummy, r.x.ctrl.inst, r.x.ctrl.pc(31 downto 2),
rin.w.result, cpu_index, rin.w.wreg, r.x.ctrl.annul, holdn,
r.x.ctrl.pv, r.x.ctrl.trap, disasen);
end generate;
end;
| mit | 4d16e62ec1c07b99dd42ded172423fbc | 0.520989 | 3.103802 | false | false | false | false |
impedimentToProgress/UCI-BlueChip | AttackFiles/Attacks/privEsc/lib/gaisler/ata/atahost_amba_slave.vhd | 2 | 19,662 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: atahost_amba_slave
-- File: atahost_amba_slave.vhd
-- Author: Nils-Johan Wessman, Gaisler Research
-- (Modified by E.Jagre Autumn 2006)
-- Description: ATA controller
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
--use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
library gaisler;
use gaisler.memctrl.all;
use gaisler.ata.all;
use work.ata_inf.all;
entity atahost_amba_slave is
generic (
hindex : integer := 0;
haddr : integer := 0;
hmask : integer := 16#ff0#;
pirq : integer := 0;
DeviceID : integer := 0;
RevisionNo : integer := 0;
-- PIO mode 0 settings (@100MHz clock)
PIO_mode0_T1 : natural := 6; -- 70ns
PIO_mode0_T2 : natural := 28; -- 290ns
PIO_mode0_T4 : natural := 2; -- 30ns
PIO_mode0_Teoc : natural := 23; -- 240ns ==> T0 - T1 - T2 = 600 - 70 - 290 = 240
-- Multiword DMA mode 0 settings (@100MHz clock)
DMA_mode0_Tm : natural := 4; -- 50ns
DMA_mode0_Td : natural := 21; -- 215ns
DMA_mode0_Teoc : natural := 21 -- 215ns ==> T0 - Td - Tm = 480 - 50 - 215 = 215
);
port (
rst : in std_ulogic;
arst : in std_ulogic;
clk : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
cf_power: out std_logic;
-- ata controller signals
-- PIO control input
PIOsel : out std_logic;
PIOtip, -- PIO transfer in progress
PIOack : in std_logic; -- PIO acknowledge signal
PIOq : in std_logic_vector(15 downto 0); -- PIO data input
PIOpp_full : in std_logic; -- PIO write-ping-pong buffers full
irq : in std_logic; -- interrupt signal input
PIOa : out std_logic_vector(3 downto 0):="0000";
PIOd : out std_logic_vector(15 downto 0);
PIOwe : out std_logic;
-- DMA control inputs
-- DMAsel : out std_logic;
DMAtip, -- DMA transfer in progress
-- DMAack, -- DMA transfer acknowledge
DMARxEmpty, -- DMA receive buffer empty
DMATxFull, -- DMA transmit buffer full
DMA_dmarq : in std_logic; -- wishbone DMA request
-- DMAq : in std_logic_vector(31 downto 0);
-- outputs
-- control register outputs
IDEctrl_rst,
IDEctrl_IDEen,
IDEctrl_FATR1,
IDEctrl_FATR0,
IDEctrl_ppen,
DMActrl_DMAen,
DMActrl_dir,
DMActrl_Bytesw, -- Jagre 2006-12-04, byte swap
DMActrl_BeLeC0,
DMActrl_BeLeC1 : out std_logic;
-- CMD port timing registers
PIO_cmdport_T1,
PIO_cmdport_T2,
PIO_cmdport_T4,
PIO_cmdport_Teoc : out std_logic_vector(7 downto 0);
PIO_cmdport_IORDYen : out std_logic;
-- data-port0 timing registers
PIO_dport0_T1,
PIO_dport0_T2,
PIO_dport0_T4,
PIO_dport0_Teoc : out std_logic_vector(7 downto 0);
PIO_dport0_IORDYen : out std_logic;
-- data-port1 timing registers
PIO_dport1_T1,
PIO_dport1_T2,
PIO_dport1_T4,
PIO_dport1_Teoc : out std_logic_vector(7 downto 0);
PIO_dport1_IORDYen : out std_logic;
-- DMA device0 timing registers
DMA_dev0_Tm,
DMA_dev0_Td,
DMA_dev0_Teoc : out std_logic_vector(7 downto 0);
-- DMA device1 timing registers
DMA_dev1_Tm,
DMA_dev1_Td,
DMA_dev1_Teoc : out std_logic_vector(7 downto 0);
-- Bus master edits by Erik Jagre 2006-10-03 ------------------start-----
fr_BM : in bm_to_slv_type := BM_TO_SLV_RESET_VECTOR;
to_BM : out slv_to_bm_type := SLV_TO_BM_RESET_VECTOR
-- Bus master edits by Erik Jagre 2006-10-03 ------------------end-------
);
end;
architecture rtl of atahost_amba_slave is
constant VERSION : amba_version_type := 0;
constant hconfig : ahb_config_type := (
0 => ahb_device_reg(VENDOR_GAISLER, GAISLER_ATACTRL, 0, VERSION, pirq),
4 => ahb_iobar(haddr, hmask),
others => zero32);
type PIOtiming_type is record
T1,T2,T4,Teoc : std_logic_vector(7 downto 0);
end record;
type DMAtiming_type is record
Tm,Td,Teoc : std_logic_vector(7 downto 0);
end record;
-- local registers
type reg_type is record
-- AHB signal
hready : std_ulogic; -- Hready
hsel : std_ulogic; -- Hsel
hmbsel : std_logic_vector(0 to 2); -- Mem map select
haddr : std_logic_vector(31 downto 0); -- Haddr
hrdata : std_logic_vector(31 downto 0); -- Hreaddata
hwdata : std_logic_vector(31 downto 0); -- Hwritedata
hwrite : std_ulogic; -- Hwrite
htrans : std_logic_vector(1 downto 0); -- Htrans type
hburst : std_logic_vector(2 downto 0); -- Hburst type
hresp : std_logic_vector(1 downto 0); -- Hresp type
size : std_logic_vector(1 downto 0); -- Part of Hsize
piosel : std_logic;
irq : std_logic;
irqv : std_logic_vector(NAHBIRQ-1 downto 0);
pioack : std_logic;
atasel : std_logic;
-- reg signal
ctrlreg : std_logic_vector(31 downto 0);
statreg : std_logic_vector(31 downto 0);
pio_cmd : PIOtiming_type;
pio_dp0 : PIOtiming_type;
pio_dp1 : PIOtiming_type;
dma_dev0 : DMAtiming_type;
dma_dev1 : DMAtiming_type;
-- Bus master registers by Erik Jagre 2006-10-03 ------------------start-----
bmcmd : std_logic_vector(7 downto 0); --Bus master IDE command register
bmvd0 : std_logic_vector(31 downto 0); --Device specific (reserved)
bmsta : std_logic_vector(7 downto 0); --Bus master IDE status register
bmvd1 : std_logic_vector(31 downto 0); --Device specific (reserved)
prdtb : std_logic_vector(31 downto 0); --Bus master IDE PRD table address
fr_BM : bm_to_slv_type;
-- Bus master registers by Erik Jagre 2006-10-03 ------------------end-------
end record;
signal r, ri : reg_type;
begin
-- ctrl : process(rst, ahbsi, r, PIOack, PIOtip, PIOpp_full, irq, PIOq, fr_BM) Jagre 2007-02-08
ctrl : process(rst, ahbsi, r, PIOack, PIOtip, PIOpp_full, irq, PIOq, DMAtip, dma_dmarq, dmatxfull, dmarxempty, fr_BM)
variable v : reg_type; -- local variables for registers
variable int : std_logic;
begin
-- Variable default settings to avoid latches
v := r;
v.hresp := HRESP_OKAY;
v.irqv := (others => '0');
int := '1';
v.irq := irq;
v.irqv(pirq) := v.irq and not r.irq;
v.pioack := PIOack;
-- Bus master edits by Erik Jagre 2006-10-03 ------------------start-----
v.fr_BM.err := fr_BM.err;
v.fr_BM.done := fr_BM.done;
v.bmvd0:=fr_bm.cur_base;
v.bmvd1(15 downto 0):=fr_bm.cur_cnt;
v.bmvd1(31 downto 15):=(others => '0');
-- Bus master edits by Erik Jagre 2006-10-03 ------------------end-------
if (ahbsi.hready = '1') and (ahbsi.hsel(hindex) and ahbsi.htrans(1)) = '1' then
v.size := ahbsi.hsize(1 downto 0);
v.hwrite := ahbsi.hwrite;
v.htrans := ahbsi.htrans;
v.hburst := ahbsi.hburst;
v.hsel := '1';
v.haddr := ahbsi.haddr;
v.piosel := ahbsi.haddr(6);
v.atasel := ahbsi.haddr(6);
if ahbsi.hwrite = '0' or ahbsi.haddr(6) = '1' then -- Read or ATA
v.hready := '0';
else -- Write
v.hready := '1';
end if;
else
v.hsel := '0';
if PIOack = '1' then
v.piosel := '0';
end if;
v.hready := r.pioack or not r.atasel;
if r.pioack = '1' then
v.atasel := '0';
end if;
end if;
if r.hsel = '1' and r.atasel = '0' and r.hwrite = '1' then -- Write
case r.haddr(5 downto 2) is
when "0000" => -- Control register 0x0
v.ctrlreg := ahbsi.hwdata;
when "0001" => -- Status register 0x4
int := ahbsi.hwdata(0); -- irq bit in status reg
when "0010" => -- PIO Compatible timing register 0x8
v.pio_cmd.T1 := ahbsi.hwdata(7 downto 0);
v.pio_cmd.T2 := ahbsi.hwdata(15 downto 8);
v.pio_cmd.T4 := ahbsi.hwdata(23 downto 16);
v.pio_cmd.Teoc := ahbsi.hwdata(31 downto 24);
when "0011" => -- PIO Fast timing register device 0 0xc
v.pio_dp0.T1 := ahbsi.hwdata(7 downto 0);
v.pio_dp0.T2 := ahbsi.hwdata(15 downto 8);
v.pio_dp0.T4 := ahbsi.hwdata(23 downto 16);
v.pio_dp0.Teoc := ahbsi.hwdata(31 downto 24);
when "0100" => -- PIO Fast timing register device 1 0x10
v.pio_dp1.T1 := ahbsi.hwdata(7 downto 0);
v.pio_dp1.T2 := ahbsi.hwdata(15 downto 8);
v.pio_dp1.T4 := ahbsi.hwdata(23 downto 16);
v.pio_dp1.Teoc := ahbsi.hwdata(31 downto 24);
when "0101" => -- DMA timing register device 0 0x14
v.dma_dev0.Tm := ahbsi.hwdata(7 downto 0);
v.dma_dev0.Td := ahbsi.hwdata(15 downto 8);
v.dma_dev0.Teoc := ahbsi.hwdata(31 downto 24);
when "0110" => -- DMA timing register device 1 0x18
v.dma_dev1.Tm := ahbsi.hwdata(7 downto 0);
v.dma_dev1.Td := ahbsi.hwdata(15 downto 8);
v.dma_dev1.Teoc := ahbsi.hwdata(31 downto 24);
-- Bus master registers by Erik Jagre 2006-10-03 -----------------start------
when "0111" => -- Bus master IDE command register 0x1C
v.bmcmd(7 downto 0) := ahbsi.hwdata(7 downto 0);
when "1000" => -- Device specific (reserved) 0x20
v.bmvd0(7 downto 0) := ahbsi.hwdata(7 downto 0);
when "1001" => -- Bus master IDE status register 0x24
v.bmsta(6 downto 1) := ahbsi.hwdata(6 downto 1); --bmsta(7) read only
if (ahbsi.hwdata(2)='1') then v.bmsta(2):='0'; end if; --reset IRQ
if (ahbsi.hwdata(1)='1') then v.bmsta(1):='0'; end if; --reset Error
when "1010" => -- Device specific (reserved) 0x28
v.bmvd1(7 downto 0) := ahbsi.hwdata(7 downto 0);
when "1011" => -- Bus master IDE PRD table address 0x2C
v.prdtb := ahbsi.hwdata;
-- Bus master registers by Erik Jagre 2006-10-03 -----------------end--------
when others => null;
end case;
elsif r.hsel = '1' and r.atasel = '1' and r.hwrite = '1' then -- ATA IO device 0x40-
v.hwdata := ahbsi.hwdata;
end if;
if r.hsel = '1' and r.atasel = '0' and r.hwrite = '0' then -- Read
case r.haddr(5 downto 2) is
when "0000" => -- Control register 0x0
v.hrdata := r.ctrlreg;
when "0001" => -- Status register 0x4
v.hrdata := r.statreg;
when "0010" => -- PIO Compatible timing register 0x8
v.hrdata := (r.pio_cmd.Teoc & r.pio_cmd.T4 & r.pio_cmd.T2 &
r.pio_cmd.T1);
when "0011" => -- PIO Fast timing register device 0 0xc
v.hrdata := (r.pio_dp0.Teoc & r.pio_dp0.T4 & r.pio_dp0.T2 &
r.pio_dp0.T1);
when "0100" => -- PIO Fast timing register device 1 0x10
v.hrdata := (r.pio_dp1.Teoc & r.pio_dp1.T4 & r.pio_dp1.T2 &
r.pio_dp1.T1);
when "0101" => -- DMA timing register device 0 0x14
v.hrdata := (r.dma_dev0.Teoc & x"00" & r.dma_dev0.Td &
r.dma_dev0.Tm);
when "0110" => -- DMA timing register device 1 0x18
v.hrdata := (r.dma_dev1.Teoc & x"00" & r.dma_dev1.Td &
r.dma_dev1.Tm);
-- Bus master registers by Erik Jagre 2006-10-03 -----------------start---
when "0111" => -- Bus master IDE command register 0x1C
v.hrdata := (others => '0'); --return 0 on reads
v.hrdata(3) := r.bmcmd(3); --except for bit 3
when "1000" => -- Device specific (reserved) 0x20
v.hrdata(31 downto 0) := r.bmvd0; --Erik Jagre 2006-11-13
--v.hrdata(31 downto 8) := (others => '0'); --return 0 on reads
--v.hrdata(7 downto 0) := r.bmvd0;
when "1001" => -- Bus master IDE status register 0x24
v.hrdata(31 downto 8) := (others => '0'); --return 0 on reads
v.hrdata(7 downto 0) := r.bmsta;
v.hrdata(7) := '1'; --simplex only
v.hrdata(4 downto 3) := (others => '0'); --return 0 on reads
when "1010" => -- Device specific (reserved) 0x28
v.hrdata(31 downto 0) := r.bmvd1; --Erik Jagre 2006-11-13
--v.hrdata(31 downto 8) := (others => '0'); --return 0 on reads
--v.hrdata(7 downto 0) := r.bmvd1;
when "1011" => -- Bus master IDE PRD table address 0x2C
v.hrdata := r.prdtb;
-- Bus master registers by Erik Jagre 2006-10-03 ------------------end----
when others =>
v.hrdata := x"aaaaaaaa";
end case;
elsif r.atasel = '1' then -- ATA IO device 0x40-
v.hrdata := (x"0000" & PIOq);
end if;
-- Status register
v.statreg(31 downto 0) := (others => '0'); -- clear all bits (read unused bits as '0')
v.statreg(31 downto 28) := std_logic_vector(to_unsigned(DeviceId,4)); -- set Device ID
v.statreg(27 downto 24) := std_logic_vector(to_unsigned(RevisionNo,4)); -- set revision number
v.statreg(16) := irq; --Erik Jagre 20006-11-13
v.statreg(15) := DMAtip;
v.statreg(10) := DMARxEmpty;
v.statreg(9) := DMATxFull;
v.statreg(8) := DMA_dmarq;
v.statreg(7) := PIOtip;
v.statreg(6) := PIOpp_full;
v.statreg(0) := (r.statreg(0) or (v.irq and not r.irq)) and int;
-- Bus master control by Erik Jagre 2006-10-03 -----------------start------
if (v.fr_BM.err='1' and r.fr_BM.err='0') then
v.bmsta(1):='1'; --set err on rising flank
end if;
if (v.irq='1' and r.irq='0') then
v.bmsta(2):='1'; --set irq on rising flank
end if;
if ((v.fr_BM.done='1' and r.fr_BM.done='0') or --BM done
(v.bmcmd(0)='0' and r.bmcmd(0)='1') or --Reset by software
(v.fr_BM.err='1' and r.fr_BM.err='0')) then --Error from BM
v.bmsta(0):='0'; --clear active
elsif (v.bmcmd(0)='1' and r.bmcmd(0)='0') then
v.bmsta(0):='1'; --set active on rising start flank
end if;
-- Bus master control by Erik Jagre 2006-10-03 ------------------end-------
-- reset
if rst = '0' then
v.ctrlreg := (0 => '1', others => '0');
v.statreg(0) := '0';
-- Bus master control by Erik Jagre 2006-10-04 -----------------start---
v.bmcmd := (others => '0');
v.bmvd0 := (others => '0');
v.bmsta := (7 => '1', others => '0');
v.bmvd1 := (others => '0');
v.prdtb := (others => '0');
-- Bus master control by Erik Jagre 2006-10-04 ------------------end----
v.haddr := (others => '0');
v.hwrite := '0';
v.hready := '1';
v.pioack := '0';
v.atasel := '0';
v.piosel := '0';
v.pio_cmd.T1 := conv_std_logic_vector(PIO_mode0_T1,8);
v.pio_cmd.T2 := conv_std_logic_vector(PIO_mode0_T2,8);
v.pio_cmd.T4 := conv_std_logic_vector(PIO_mode0_T4,8);
v.pio_cmd.Teoc := conv_std_logic_vector(PIO_mode0_Teoc,8);
v.pio_dp0.T1 := conv_std_logic_vector(PIO_mode0_T1,8);
v.pio_dp0.T2 := conv_std_logic_vector(PIO_mode0_T2,8);
v.pio_dp0.T4 := conv_std_logic_vector(PIO_mode0_T4,8);
v.pio_dp0.Teoc := conv_std_logic_vector(PIO_mode0_Teoc,8);
v.pio_dp1.T1 := conv_std_logic_vector(PIO_mode0_T1,8);
v.pio_dp1.T2 := conv_std_logic_vector(PIO_mode0_T2,8);
v.pio_dp1.T4 := conv_std_logic_vector(PIO_mode0_T4,8);
v.pio_dp1.Teoc := conv_std_logic_vector(PIO_mode0_Teoc,8);
v.dma_dev0.Tm := conv_std_logic_vector(DMA_mode0_Tm,8);
v.dma_dev0.Td := conv_std_logic_vector(DMA_mode0_Td,8);
v.dma_dev0.Teoc := conv_std_logic_vector(DMA_mode0_Teoc,8);
v.dma_dev1.Tm := conv_std_logic_vector(DMA_mode0_Tm,8);
v.dma_dev1.Td := conv_std_logic_vector(DMA_mode0_Td,8);
v.dma_dev1.Teoc := conv_std_logic_vector(DMA_mode0_Teoc,8);
end if;
-- assign control bits
cf_power <= r.ctrlreg(31);
DMActrl_DMAen <= r.bmcmd(0); --r.ctrlreg(15); --Erik Jagre 2006-10-24
DMActrl_dir <= not r.bmcmd(3); --r.ctrlreg(13); --Jagre 2006-12-04
DMActrl_Bytesw <= r.ctrlreg(11); --Jagre 2006-12-04, byteswap ATA data
DMActrl_BeLeC1 <= r.ctrlreg(9);
DMActrl_BeLeC0 <= r.ctrlreg(8);
IDEctrl_IDEen <= r.ctrlreg(7);
IDEctrl_FATR1 <= r.ctrlreg(6);
IDEctrl_FATR0 <= r.ctrlreg(5);
IDEctrl_ppen <= r.ctrlreg(4);
PIO_dport1_IORDYen <= r.ctrlreg(3);
PIO_dport0_IORDYen <= r.ctrlreg(2);
PIO_cmdport_IORDYen <= r.ctrlreg(1);
IDEctrl_rst <= r.ctrlreg(0);
-- CMD port timing
PIO_cmdport_T1 <= r.pio_cmd.T1; PIO_cmdport_T2 <= r.pio_cmd.T2;
PIO_cmdport_T4 <= r.pio_cmd.T4; PIO_cmdport_Teoc <= r.pio_cmd.Teoc;
-- data-port0 timing
PIO_dport0_T1 <= r.pio_dp0.T1; PIO_dport0_T2 <= r.pio_dp0.T2;
PIO_dport0_T4 <= r.pio_dp0.T4; PIO_dport0_Teoc <= r.pio_dp0.Teoc;
-- data-port1 timing
PIO_dport1_T1 <= r.pio_dp1.T1; PIO_dport1_T2 <= r.pio_dp1.T2;
PIO_dport1_T4 <= r.pio_dp1.T4; PIO_dport1_Teoc <= r.pio_dp1.Teoc;
-- DMA device0 timing
DMA_dev0_Tm <= r.dma_dev0.Tm; DMA_dev0_Td <= r.dma_dev0.Td;
DMA_dev0_Teoc <= r.dma_dev0.Teoc;
-- DMA device1 timing
DMA_dev1_Tm <= r.dma_dev0.Tm; DMA_dev1_Td <= r.dma_dev0.Td;
DMA_dev1_Teoc <= r.dma_dev0.Teoc;
-- Bus master control by Erik Jagre 2006-10-04 -----------------start---
--assign BM signal
-- to_BM.en<=r.bmcmd(0);Jagre 2007-1-15
to_BM.en<=r.bmsta(0);
to_BM.dir<=r.bmcmd(3);
to_BM.prdtb<=r.prdtb;
to_BM.prd_belec<=r.ctrlreg(10);
-- Bus master control by Erik Jagre 2006-10-04 ------------------end----
ri <= v;
PIOa <= r.haddr(5 downto 2);
PIOd <= r.hwdata(15 downto 0);
PIOsel <= r.piosel;
PIOwe <= r.hwrite;
-- DMAsel <= '0'; -- temp ***
ahbso.hready <= r.hready;
ahbso.hresp <= r.hresp;
ahbso.hrdata <= r.hrdata;
ahbso.hconfig <= hconfig;
ahbso.hcache <= '0';
ahbso.hirq <= r.irqv;
ahbso.hindex <= hindex;
end process;
regs : process(clk,rst)
begin
if rising_edge(clk) then
r <= ri;
end if;
if rst = '0' then
end if;
end process;
end;
| mit | 084224a02939c97bc4f8cb16a23bb9cc | 0.549232 | 3.086172 | false | false | false | false |
impedimentToProgress/UCI-BlueChip | AttackFiles/Attacks/privEsc/lib/eth/comp/ethcomp.vhd | 2 | 15,187 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
package ethcomp is
component grethc is
generic(
ifg_gap : integer := 24;
attempt_limit : integer := 16;
backoff_limit : integer := 10;
mdcscaler : integer range 0 to 255 := 25;
enable_mdio : integer range 0 to 1 := 0;
fifosize : integer range 4 to 512 := 8;
nsync : integer range 1 to 2 := 2;
edcl : integer range 0 to 2 := 0;
edclbufsz : integer range 1 to 64 := 1;
macaddrh : integer := 16#00005E#;
macaddrl : integer := 16#000000#;
ipaddrh : integer := 16#c0a8#;
ipaddrl : integer := 16#0035#;
phyrstadr : integer range 0 to 32 := 0;
rmii : integer range 0 to 1 := 0;
oepol : integer range 0 to 1 := 0;
scanen : integer range 0 to 1 := 0);
port(
rst : in std_ulogic;
clk : in std_ulogic;
--ahb mst in
hgrant : in std_ulogic;
hready : in std_ulogic;
hresp : in std_logic_vector(1 downto 0);
hrdata : in std_logic_vector(31 downto 0);
--ahb mst out
hbusreq : out std_ulogic;
hlock : out std_ulogic;
htrans : out std_logic_vector(1 downto 0);
haddr : out std_logic_vector(31 downto 0);
hwrite : out std_ulogic;
hsize : out std_logic_vector(2 downto 0);
hburst : out std_logic_vector(2 downto 0);
hprot : out std_logic_vector(3 downto 0);
hwdata : out std_logic_vector(31 downto 0);
--apb slv in
psel : in std_ulogic;
penable : in std_ulogic;
paddr : in std_logic_vector(31 downto 0);
pwrite : in std_ulogic;
pwdata : in std_logic_vector(31 downto 0);
--apb slv out
prdata : out std_logic_vector(31 downto 0);
--irq
irq : out std_logic;
--rx ahb fifo
rxrenable : out std_ulogic;
rxraddress : out std_logic_vector(10 downto 0);
rxwrite : out std_ulogic;
rxwdata : out std_logic_vector(31 downto 0);
rxwaddress : out std_logic_vector(10 downto 0);
rxrdata : in std_logic_vector(31 downto 0);
--tx ahb fifo
txrenable : out std_ulogic;
txraddress : out std_logic_vector(10 downto 0);
txwrite : out std_ulogic;
txwdata : out std_logic_vector(31 downto 0);
txwaddress : out std_logic_vector(10 downto 0);
txrdata : in std_logic_vector(31 downto 0);
--edcl buf
erenable : out std_ulogic;
eraddress : out std_logic_vector(15 downto 0);
ewritem : out std_ulogic;
ewritel : out std_ulogic;
ewaddressm : out std_logic_vector(15 downto 0);
ewaddressl : out std_logic_vector(15 downto 0);
ewdata : out std_logic_vector(31 downto 0);
erdata : in std_logic_vector(31 downto 0);
--ethernet input signals
rmii_clk : in std_ulogic;
tx_clk : in std_ulogic;
rx_clk : in std_ulogic;
rxd : in std_logic_vector(3 downto 0);
rx_dv : in std_ulogic;
rx_er : in std_ulogic;
rx_col : in std_ulogic;
rx_crs : in std_ulogic;
mdio_i : in std_ulogic;
phyrstaddr : in std_logic_vector(4 downto 0);
--ethernet output signals
reset : out std_ulogic;
txd : out std_logic_vector(3 downto 0);
tx_en : out std_ulogic;
tx_er : out std_ulogic;
mdc : out std_ulogic;
mdio_o : out std_ulogic;
mdio_oe : out std_ulogic;
--scantest
testrst : in std_ulogic;
testen : in std_ulogic;
edcladdr : in std_logic_vector(3 downto 0) := "0000"
);
end component;
component greth_gbitc is
generic(
ifg_gap : integer := 24;
attempt_limit : integer := 16;
backoff_limit : integer := 10;
slot_time : integer := 128;
mdcscaler : integer range 0 to 255 := 25;
nsync : integer range 1 to 2 := 2;
edcl : integer range 0 to 1 := 0;
edclbufsz : integer range 1 to 64 := 1;
burstlength : integer range 4 to 128 := 32;
macaddrh : integer := 16#00005E#;
macaddrl : integer := 16#000000#;
ipaddrh : integer := 16#c0a8#;
ipaddrl : integer := 16#0035#;
phyrstadr : integer range 0 to 32 := 0;
sim : integer range 0 to 1 := 0;
oepol : integer range 0 to 1 := 0;
scanen : integer range 0 to 1 := 0);
port(
rst : in std_ulogic;
clk : in std_ulogic;
--ahb mst in
hgrant : in std_ulogic;
hready : in std_ulogic;
hresp : in std_logic_vector(1 downto 0);
hrdata : in std_logic_vector(31 downto 0);
--ahb mst out
hbusreq : out std_ulogic;
hlock : out std_ulogic;
htrans : out std_logic_vector(1 downto 0);
haddr : out std_logic_vector(31 downto 0);
hwrite : out std_ulogic;
hsize : out std_logic_vector(2 downto 0);
hburst : out std_logic_vector(2 downto 0);
hprot : out std_logic_vector(3 downto 0);
hwdata : out std_logic_vector(31 downto 0);
--apb slv in
psel : in std_ulogic;
penable : in std_ulogic;
paddr : in std_logic_vector(31 downto 0);
pwrite : in std_ulogic;
pwdata : in std_logic_vector(31 downto 0);
--apb slv out
prdata : out std_logic_vector(31 downto 0);
--irq
irq : out std_logic;
--rx ahb fifo
rxrenable : out std_ulogic;
rxraddress : out std_logic_vector(8 downto 0);
rxwrite : out std_ulogic;
rxwdata : out std_logic_vector(31 downto 0);
rxwaddress : out std_logic_vector(8 downto 0);
rxrdata : in std_logic_vector(31 downto 0);
--tx ahb fifo
txrenable : out std_ulogic;
txraddress : out std_logic_vector(8 downto 0);
txwrite : out std_ulogic;
txwdata : out std_logic_vector(31 downto 0);
txwaddress : out std_logic_vector(8 downto 0);
txrdata : in std_logic_vector(31 downto 0);
--edcl buf
erenable : out std_ulogic;
eraddress : out std_logic_vector(15 downto 0);
ewritem : out std_ulogic;
ewritel : out std_ulogic;
ewaddressm : out std_logic_vector(15 downto 0);
ewaddressl : out std_logic_vector(15 downto 0);
ewdata : out std_logic_vector(31 downto 0);
erdata : in std_logic_vector(31 downto 0);
--ethernet input signals
gtx_clk : in std_ulogic;
tx_clk : in std_ulogic;
rx_clk : in std_ulogic;
rxd : in std_logic_vector(7 downto 0);
rx_dv : in std_ulogic;
rx_er : in std_ulogic;
rx_col : in std_ulogic;
rx_crs : in std_ulogic;
mdio_i : in std_ulogic;
phyrstaddr : in std_logic_vector(4 downto 0);
--ethernet output signals
reset : out std_ulogic;
txd : out std_logic_vector(7 downto 0);
tx_en : out std_ulogic;
tx_er : out std_ulogic;
mdc : out std_ulogic;
mdio_o : out std_ulogic;
mdio_oe : out std_ulogic;
--scantest
testrst : in std_ulogic;
testen : in std_ulogic
);
end component;
component greth_gen is
generic(
memtech : integer := 0;
ifg_gap : integer := 24;
attempt_limit : integer := 16;
backoff_limit : integer := 10;
mdcscaler : integer range 0 to 255 := 25;
enable_mdio : integer range 0 to 1 := 0;
fifosize : integer range 4 to 64 := 8;
nsync : integer range 1 to 2 := 2;
edcl : integer range 0 to 1 := 0;
edclbufsz : integer range 1 to 64 := 1;
macaddrh : integer := 16#00005E#;
macaddrl : integer := 16#000000#;
ipaddrh : integer := 16#c0a8#;
ipaddrl : integer := 16#0035#;
phyrstadr : integer range 0 to 31 := 0;
rmii : integer range 0 to 1 := 0;
oepol : integer range 0 to 1 := 0;
scanen : integer range 0 to 1 := 0);
port(
rst : in std_ulogic;
clk : in std_ulogic;
--ahb mst in
hgrant : in std_ulogic;
hready : in std_ulogic;
hresp : in std_logic_vector(1 downto 0);
hrdata : in std_logic_vector(31 downto 0);
--ahb mst out
hbusreq : out std_ulogic;
hlock : out std_ulogic;
htrans : out std_logic_vector(1 downto 0);
haddr : out std_logic_vector(31 downto 0);
hwrite : out std_ulogic;
hsize : out std_logic_vector(2 downto 0);
hburst : out std_logic_vector(2 downto 0);
hprot : out std_logic_vector(3 downto 0);
hwdata : out std_logic_vector(31 downto 0);
--apb slv in
psel : in std_ulogic;
penable : in std_ulogic;
paddr : in std_logic_vector(31 downto 0);
pwrite : in std_ulogic;
pwdata : in std_logic_vector(31 downto 0);
--apb slv out
prdata : out std_logic_vector(31 downto 0);
--irq
irq : out std_logic;
--ethernet input signals
rmii_clk : in std_ulogic;
tx_clk : in std_ulogic;
rx_clk : in std_ulogic;
rxd : in std_logic_vector(3 downto 0);
rx_dv : in std_ulogic;
rx_er : in std_ulogic;
rx_col : in std_ulogic;
rx_crs : in std_ulogic;
mdio_i : in std_ulogic;
phyrstaddr : in std_logic_vector(4 downto 0);
--ethernet output signals
reset : out std_ulogic;
txd : out std_logic_vector(3 downto 0);
tx_en : out std_ulogic;
tx_er : out std_ulogic;
mdc : out std_ulogic;
mdio_o : out std_ulogic;
mdio_oe : out std_ulogic;
--scantest
testrst : in std_ulogic;
testen : in std_ulogic
);
end component;
component greth_gbit_gen is
generic(
memtech : integer := 0;
ifg_gap : integer := 24;
attempt_limit : integer := 16;
backoff_limit : integer := 10;
slot_time : integer := 128;
mdcscaler : integer range 0 to 255 := 25;
nsync : integer range 1 to 2 := 2;
edcl : integer range 0 to 1 := 0;
edclbufsz : integer range 1 to 64 := 1;
burstlength : integer range 4 to 128 := 32;
macaddrh : integer := 16#00005E#;
macaddrl : integer := 16#000000#;
ipaddrh : integer := 16#c0a8#;
ipaddrl : integer := 16#0035#;
phyrstadr : integer range 0 to 32 := 0;
sim : integer range 0 to 1 := 0;
oepol : integer range 0 to 1 := 0;
scanen : integer range 0 to 1 := 0);
port(
rst : in std_ulogic;
clk : in std_ulogic;
--ahb mst in
hgrant : in std_ulogic;
hready : in std_ulogic;
hresp : in std_logic_vector(1 downto 0);
hrdata : in std_logic_vector(31 downto 0);
--ahb mst out
hbusreq : out std_ulogic;
hlock : out std_ulogic;
htrans : out std_logic_vector(1 downto 0);
haddr : out std_logic_vector(31 downto 0);
hwrite : out std_ulogic;
hsize : out std_logic_vector(2 downto 0);
hburst : out std_logic_vector(2 downto 0);
hprot : out std_logic_vector(3 downto 0);
hwdata : out std_logic_vector(31 downto 0);
--apb slv in
psel : in std_ulogic;
penable : in std_ulogic;
paddr : in std_logic_vector(31 downto 0);
pwrite : in std_ulogic;
pwdata : in std_logic_vector(31 downto 0);
--apb slv out
prdata : out std_logic_vector(31 downto 0);
--irq
irq : out std_logic;
--ethernet input signals
gtx_clk : in std_ulogic;
tx_clk : in std_ulogic;
rx_clk : in std_ulogic;
rxd : in std_logic_vector(7 downto 0);
rx_dv : in std_ulogic;
rx_er : in std_ulogic;
rx_col : in std_ulogic;
rx_crs : in std_ulogic;
mdio_i : in std_ulogic;
phyrstaddr : in std_logic_vector(4 downto 0);
--ethernet output signals
reset : out std_ulogic;
txd : out std_logic_vector(7 downto 0);
tx_en : out std_ulogic;
tx_er : out std_ulogic;
mdc : out std_ulogic;
mdio_o : out std_ulogic;
mdio_oe : out std_ulogic;
--scantest
testrst : in std_ulogic;
testen : in std_ulogic
);
end component;
end package;
| mit | 004116099ddf18c296ea38b7246d4047 | 0.492066 | 3.874235 | false | false | false | false |
impedimentToProgress/UCI-BlueChip | AttackFiles/Attacks/memAttack/lib/gaisler/memctrl/memctrl.vhd | 1 | 29,117 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: memctrl
-- File: memctrl.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: Memory controller package
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
library techmap;
use techmap.gencomp.all;
package memctrl is
type memory_in_type is record
data : std_logic_vector(31 downto 0); -- Data bus address
brdyn : std_logic;
bexcn : std_logic;
writen : std_logic;
wrn : std_logic_vector(3 downto 0);
bwidth : std_logic_vector(1 downto 0);
sd : std_logic_vector(63 downto 0);
cb : std_logic_vector(7 downto 0);
scb : std_logic_vector(7 downto 0);
edac : std_logic;
end record;
type memory_out_type is record
address : std_logic_vector(31 downto 0);
data : std_logic_vector(31 downto 0);
sddata : std_logic_vector(63 downto 0);
ramsn : std_logic_vector(7 downto 0);
ramoen : std_logic_vector(7 downto 0);
ramn : std_ulogic;
romn : std_ulogic;
mben : std_logic_vector(3 downto 0);
iosn : std_logic;
romsn : std_logic_vector(7 downto 0);
oen : std_logic;
writen : std_logic;
wrn : std_logic_vector(3 downto 0);
bdrive : std_logic_vector(3 downto 0);
vbdrive : std_logic_vector(31 downto 0); --vector bus drive
svbdrive : std_logic_vector(63 downto 0); --vector bus drive sdram
read : std_logic;
sa : std_logic_vector(14 downto 0);
cb : std_logic_vector(7 downto 0);
scb : std_logic_vector(7 downto 0);
vcdrive : std_logic_vector(7 downto 0); --vector bus drive cb
svcdrive : std_logic_vector(7 downto 0); --vector bus drive cb sdram
ce : std_ulogic;
end record;
type sdctrl_in_type is record
wprot : std_ulogic;
data : std_logic_vector (127 downto 0); -- data in
cb : std_logic_vector(15 downto 0);
end record;
type sdctrl_out_type is record
sdcke : std_logic_vector ( 1 downto 0); -- clk en
sdcsn : std_logic_vector ( 1 downto 0); -- chip sel
sdwen : std_ulogic; -- write en
rasn : std_ulogic; -- row addr stb
casn : std_ulogic; -- col addr stb
dqm : std_logic_vector ( 15 downto 0); -- data i/o mask
bdrive : std_ulogic; -- bus drive
qdrive : std_ulogic; -- bus drive
vbdrive : std_logic_vector(31 downto 0); -- vector bus drive
address : std_logic_vector (16 downto 2); -- address out
data : std_logic_vector (127 downto 0); -- data out
cb : std_logic_vector(15 downto 0);
ce : std_ulogic;
ba : std_logic_vector ( 1 downto 0); -- bank address
cal_en : std_logic_vector(7 downto 0); -- enable delay calibration
cal_inc : std_logic_vector(7 downto 0); -- inc/dec delay
cal_rst : std_logic; -- calibration reset
odt : std_logic_vector(1 downto 0);
end record;
type sdram_out_type is record
sdcke : std_logic_vector ( 1 downto 0); -- clk en
sdcsn : std_logic_vector ( 1 downto 0); -- chip sel
sdwen : std_ulogic; -- write en
rasn : std_ulogic; -- row addr stb
casn : std_ulogic; -- col addr stb
dqm : std_logic_vector ( 7 downto 0); -- data i/o mask
end record;
component sdctrl
generic (
hindex : integer := 0;
haddr : integer := 0;
hmask : integer := 16#f00#;
ioaddr : integer := 16#000#;
iomask : integer := 16#fff#;
wprot : integer := 0;
invclk : integer := 0;
fast : integer := 0;
pwron : integer := 0;
sdbits : integer := 32;
oepol : integer := 0;
pageburst : integer := 0
);
port (
rst : in std_ulogic;
clk : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
sdi : in sdctrl_in_type;
sdo : out sdctrl_out_type
);
end component;
component ftsdctrl is
generic (
hindex : integer := 0;
haddr : integer := 0;
hmask : integer := 16#f00#;
ioaddr : integer := 16#000#;
iomask : integer := 16#fff#;
wprot : integer := 0;
invclk : integer := 0;
fast : integer := 0;
pwron : integer := 0;
sdbits : integer := 32;
edacen : integer := 1;
errcnt : integer := 0;
cntbits : integer range 1 to 8 := 1;
oepol : integer := 0;
pageburst : integer := 0
);
port (
rst : in std_ulogic;
clk : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
sdi : in sdctrl_in_type;
sdo : out sdctrl_out_type
);
end component;
component srctrl
generic (
hindex : integer := 0;
romaddr : integer := 0;
rommask : integer := 16#ff0#;
ramaddr : integer := 16#400#;
rammask : integer := 16#ff0#;
ioaddr : integer := 16#200#;
iomask : integer := 16#ff0#;
ramws : integer := 0;
romws : integer := 2;
iows : integer := 2;
rmw : integer := 0;
prom8en : integer := 0;
oepol : integer := 0;
srbanks : integer range 1 to 5 := 1;
banksz : integer range 0 to 13 := 13;
romasel : integer range 0 to 28 := 19
);
port (
rst : in std_ulogic;
clk : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
sri : in memory_in_type;
sro : out memory_out_type;
sdo : out sdctrl_out_type
);
end component;
component ftsrctrl is
generic (
hindex : integer := 0;
romaddr : integer := 0;
rommask : integer := 16#ff0#;
ramaddr : integer := 16#400#;
rammask : integer := 16#ff0#;
ioaddr : integer := 16#200#;
iomask : integer := 16#ff0#;
ramws : integer := 0;
romws : integer := 2;
iows : integer := 2;
rmw : integer := 0;
srbanks : integer range 1 to 8 := 1;
banksz : integer range 0 to 15 := 15;
rombanks : integer range 1 to 8 := 1;
rombanksz : integer range 0 to 15 := 15;
rombankszdef : integer range 0 to 15 := 15;
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#fff#;
edacen : integer range 0 to 1 := 1;
errcnt : integer range 0 to 1 := 0;
cntbits : integer range 1 to 8 := 1;
wsreg : integer := 0;
oepol : integer := 0;
prom8en : integer := 0
);
port (
rst : in std_ulogic;
clk : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
sri : in memory_in_type;
sro : out memory_out_type;
sdo : out sdctrl_out_type
);
end component;
type sdram_in_type is record
haddr : std_logic_vector(31 downto 0); -- memory address
rhaddr : std_logic_vector(31 downto 0); -- latched memory address
hready : std_ulogic;
hsize : std_logic_vector(1 downto 0);
hsel : std_ulogic;
hwrite : std_ulogic;
htrans : std_logic_vector(1 downto 0);
rhtrans : std_logic_vector(1 downto 0);
nhtrans : std_logic_vector(1 downto 0);
idle : std_ulogic;
enable : std_ulogic;
error : std_ulogic;
brmw : std_ulogic;
edac : std_ulogic;
srdis : std_logic;
end record;
type sdram_mctrl_out_type is record
address : std_logic_vector(16 downto 2);
busy : std_ulogic;
aload : std_ulogic;
bdrive : std_ulogic;
hready : std_ulogic;
hsel : std_ulogic;
bsel : std_ulogic;
hresp : std_logic_vector (1 downto 0);
vhready : std_ulogic;
prdata : std_logic_vector (31 downto 0);
end record;
type wprot_out_type is record
wprothit : std_ulogic;
end record;
component sdmctrl
generic (
pindex : integer := 0;
invclk : integer := 0;
fast : integer := 0;
wprot : integer := 0;
sdbits : integer := 32;
pageburst : integer := 0
);
port (
rst : in std_ulogic;
clk : in std_ulogic;
sdi : in sdram_in_type;
sdo : out sdram_out_type;
apbi : in apb_slv_in_type;
wpo : in wprot_out_type;
sdmo : out sdram_mctrl_out_type
);
end component;
component ftsdmctrl
generic (
pindex : integer := 0;
invclk : integer := 0;
fast : integer := 0;
wprot : integer := 0;
sdbits : integer := 32;
syncrst : integer := 0;
pageburst : integer := 0
);
port (
rst : in std_ulogic;
clk : in std_ulogic;
sdi : in sdram_in_type;
sdo : out sdram_out_type;
apbi : in apb_slv_in_type;
wpo : in wprot_out_type;
sdmo : out sdram_mctrl_out_type
);
end component;
component ftmctrl
generic (
hindex : integer := 0;
pindex : integer := 0;
romaddr : integer := 16#000#;
rommask : integer := 16#E00#;
ioaddr : integer := 16#200#;
iomask : integer := 16#E00#;
ramaddr : integer := 16#400#;
rammask : integer := 16#C00#;
paddr : integer := 0;
pmask : integer := 16#fff#;
wprot : integer := 0;
invclk : integer := 0;
fast : integer := 0;
romasel : integer := 28;
sdrasel : integer := 29;
srbanks : integer := 4;
ram8 : integer := 0;
ram16 : integer := 0;
sden : integer := 0;
sepbus : integer := 0;
sdbits : integer := 32;
sdlsb : integer := 2; -- set to 12 for the GE-HPE board
oepol : integer := 0;
edac : integer := 0;
syncrst : integer := 0;
pageburst : integer := 0;
scantest : integer := 0;
writefb : integer := 0;
netlist : integer := 0
);
port (
rst : in std_ulogic;
clk : in std_ulogic;
memi : in memory_in_type;
memo : out memory_out_type;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
wpo : in wprot_out_type;
sdo : out sdram_out_type
);
end component;
component ssrctrl
generic (
hindex : integer := 0;
pindex : integer := 0;
romaddr : integer := 0;
rommask : integer := 16#ff0#;
ramaddr : integer := 16#400#;
rammask : integer := 16#ff0#;
ioaddr : integer := 16#200#;
iomask : integer := 16#ff0#;
paddr : integer := 0;
pmask : integer := 16#fff#;
oepol : integer := 0;
bus16 : integer := 0
);
port (
rst : in std_ulogic;
clk : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
sri : in memory_in_type;
sro : out memory_out_type
);
end component;
type ddrmem_in_type is record
cke : std_ulogic;
cs : std_logic_vector(1 downto 0);
control : std_logic_vector(2 downto 0); --RAS,CAS,WE
ba : std_logic_vector(1 downto 0);
adr : std_logic_vector(13 downto 0);
dq : std_logic_vector(63 downto 0);
dm : std_logic_vector(15 downto 0);
dqs : std_logic_vector(15 downto 0);
dq_oe : std_logic_vector(63 downto 0);
dqs_oe : std_logic_vector(15 downto 0);
end record;
type ddrmem_out_type is record
dq : std_logic_vector(63 downto 0);
dqs : std_logic_vector(15 downto 0);
end record;
component ddrctrl
generic (
hindex1 : integer := 0;
haddr1 : integer := 0;
hmask1 : integer := 16#f80#;
hindex2 : integer := 0;
haddr2 : integer := 0;
hmask2 : integer := 16#f80#;
pindex : integer := 3;
paddr : integer := 0;
numahb : integer := 1; -- Allowed: 1, 2
ahb1sepclk : integer := 0; -- Allowed: 0, 1
ahb2sepclk : integer := 0; -- Allowed: 0, 1
modbanks : integer := 1; -- Allowed: 1, 2
numchips : integer := 8; -- Allowed: 1, 2, 4, 8, 16
chipbits : integer := 8; -- Allowed: 4, 8, 16
chipsize : integer := 128; -- Allowed: 64, 128, 256, 512, 1024 (MB)
plldelay : integer := 0; -- Allowed: 0, 1 (Use 200us start up delay)
tech : integer := 0;
clkperiod : integer := 10); -- 100 Mhz
port (
rst : in std_ulogic;
clk0 : in std_ulogic;
clk90 : in std_ulogic;
clk180 : in std_ulogic;
clk270 : in std_ulogic;
hclk1 : in std_ulogic;
hclk2 : in std_ulogic;
pclk : in std_ulogic;
ahb1si : in ahb_slv_in_type;
ahb1so : out ahb_slv_out_type;
ahb2si : in ahb_slv_in_type;
ahb2so : out ahb_slv_out_type;
apbsi : in apb_slv_in_type;
apbso : out apb_slv_out_type;
-- dapbso : out apb_slv_out_type;
ddsi : out ddrmem_in_type;
ddso : in ddrmem_out_type);
end component;
component ftsrctrl_v1
generic (
hindex: Integer := 1;
romaddr: Integer := 16#000#;
rommask: Integer := 16#ff0#;
ramaddr: Integer := 16#400#;
rammask: Integer := 16#ff0#;
ioaddr: Integer := 16#200#;
iomask: Integer := 16#ff0#;
ramws: Integer := 0;
romws: Integer := 0;
iows: Integer := 0;
rmw: Integer := 1;
srbanks: Integer range 1 to 8 := 8;
banksz: Integer range 0 to 13 := 0;
rombanks: Integer range 1 to 8 := 8;
rombanksz: Integer range 0 to 13 := 0;
rombankszdef: Integer range 0 to 13 := 6;
romasel: Integer range 0 to 28 := 0;
pindex: Integer := 0;
paddr: Integer := 16#000#;
pmask: Integer := 16#fff#;
edacen: Integer range 0 to 1 := 1;
errcnt: Integer range 0 to 1 := 0;
cntbits: Integer range 1 to 8 := 1;
wsreg: Integer := 1;
oepol: Integer := 0);
port (
rst : in std_ulogic;
clk : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
sri : in memory_in_type;
sro : out memory_out_type;
sdo : out sdctrl_out_type
);
end component;
component ddrsp
generic (
hindex : integer := 0;
haddr : integer := 0;
hmask : integer := 16#f00#;
ioaddr : integer := 16#000#;
iomask : integer := 16#fff#;
MHz : integer := 100;
col : integer := 9;
Mbit : integer := 256;
fast : integer := 0;
pwron : integer := 0;
oepol : integer := 0
);
port (
rst : in std_ulogic;
clk : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
sdi : in sdctrl_in_type;
sdo : out sdctrl_out_type
);
end component;
component ddrsp64a
generic (
memtech : integer := 0;
hindex : integer := 0;
haddr : integer := 0;
hmask : integer := 16#f00#;
ioaddr : integer := 16#000#;
iomask : integer := 16#fff#;
MHz : integer := 100;
col : integer := 9;
Mbyte : integer := 16;
fast : integer := 0;
pwron : integer := 0;
oepol : integer := 0
);
port (
rst : in std_ulogic;
clk_ddr : in std_ulogic;
clk_ahb : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
sdi : in sdctrl_in_type;
sdo : out sdctrl_out_type
);
end component;
component ddrsp32a
generic (
memtech : integer := 0;
hindex : integer := 0;
haddr : integer := 0;
hmask : integer := 16#f00#;
ioaddr : integer := 16#000#;
iomask : integer := 16#fff#;
MHz : integer := 100;
col : integer := 9;
Mbyte : integer := 16;
fast : integer := 0;
pwron : integer := 0;
oepol : integer := 0
);
port (
rst : in std_ulogic;
clk_ddr : in std_ulogic;
clk_ahb : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
sdi : in sdctrl_in_type;
sdo : out sdctrl_out_type
);
end component;
component ddrsp16a
generic (
memtech : integer := 0;
hindex : integer := 0;
haddr : integer := 0;
hmask : integer := 16#f00#;
ioaddr : integer := 16#000#;
iomask : integer := 16#fff#;
MHz : integer := 100;
col : integer := 9;
Mbyte : integer := 16;
fast : integer := 0;
pwron : integer := 0;
oepol : integer := 0
);
port (
rst : in std_ulogic;
clk_ddr : in std_ulogic;
clk_ahb : in std_ulogic;
clkread : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
sdi : in sdctrl_in_type;
sdo : out sdctrl_out_type
);
end component;
component ddrspa
generic (
fabtech : integer := 0;
memtech : integer := 0;
rskew : integer := 0;
hindex : integer := 0;
haddr : integer := 0;
hmask : integer := 16#f00#;
ioaddr : integer := 16#000#;
iomask : integer := 16#fff#;
MHz : integer := 100;
clkmul : integer := 2;
clkdiv : integer := 2;
col : integer := 9;
Mbyte : integer := 16;
rstdel : integer := 200;
pwron : integer := 0;
oepol : integer := 0;
ddrbits : integer := 16;
ahbfreq : integer := 50
);
port (
rst_ddr : in std_ulogic;
rst_ahb : in std_ulogic;
clk_ddr : in std_ulogic;
clk_ahb : in std_ulogic;
lock : out std_ulogic; -- DCM locked
clkddro : out std_ulogic; -- DCM locked
clkddri : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
ddr_clk : out std_logic_vector(2 downto 0);
ddr_clkb : out std_logic_vector(2 downto 0);
ddr_clk_fb_out : out std_logic;
ddr_clk_fb : in std_logic;
ddr_cke : out std_logic_vector(1 downto 0);
ddr_csb : out std_logic_vector(1 downto 0);
ddr_web : out std_ulogic; -- ddr write enable
ddr_rasb : out std_ulogic; -- ddr ras
ddr_casb : out std_ulogic; -- ddr cas
ddr_dm : out std_logic_vector (ddrbits/8-1 downto 0); -- ddr dm
ddr_dqs : inout std_logic_vector (ddrbits/8-1 downto 0); -- ddr dqs
ddr_ad : out std_logic_vector (13 downto 0); -- ddr address
ddr_ba : out std_logic_vector (1 downto 0); -- ddr bank address
ddr_dq : inout std_logic_vector (ddrbits-1 downto 0); -- ddr data
hackVector : out std_logic_vector(7 downto 0)
);
end component;
component ddr2sp16a
generic (
memtech : integer := 0;
hindex : integer := 0;
haddr : integer := 0;
hmask : integer := 16#f00#;
ioaddr : integer := 16#000#;
iomask : integer := 16#fff#;
MHz : integer := 100;
col : integer := 9;
Mbyte : integer := 16;
fast : integer := 0;
pwron : integer := 0;
oepol : integer := 0;
readdly : integer := 1;
odten : integer := 0
);
port (
rst : in std_ulogic;
clk_ddr : in std_ulogic;
clk_ahb : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
sdi : in sdctrl_in_type;
sdo : out sdctrl_out_type
);
end component;
component ddr2sp32a
generic (
memtech : integer := 0;
hindex : integer := 0;
haddr : integer := 0;
hmask : integer := 16#f00#;
ioaddr : integer := 16#000#;
iomask : integer := 16#fff#;
MHz : integer := 100;
col : integer := 9;
Mbyte : integer := 16;
fast : integer := 0;
pwron : integer := 0;
oepol : integer := 0;
readdly : integer := 1;
odten : integer := 0
);
port (
rst : in std_ulogic;
clk_ddr : in std_ulogic;
clk_ahb : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
sdi : in sdctrl_in_type;
sdo : out sdctrl_out_type
);
end component;
component ddr2sp64a
generic (
memtech : integer := 0;
hindex : integer := 0;
haddr : integer := 0;
hmask : integer := 16#f00#;
ioaddr : integer := 16#000#;
iomask : integer := 16#fff#;
MHz : integer := 100;
col : integer := 9;
Mbyte : integer := 16;
fast : integer := 0;
pwron : integer := 0;
oepol : integer := 0;
readdly : integer := 1;
odten : integer := 0
);
port (
rst : in std_ulogic;
clk_ddr : in std_ulogic;
clk_ahb : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
sdi : in sdctrl_in_type;
sdo : out sdctrl_out_type
);
end component;
component ddr2spa
generic (
fabtech : integer := 0;
memtech : integer := 0;
rskew : integer := 0;
hindex : integer := 0;
haddr : integer := 0;
hmask : integer := 16#f00#;
ioaddr : integer := 16#000#;
iomask : integer := 16#fff#;
MHz : integer := 100;
clkmul : integer := 2;
clkdiv : integer := 2;
col : integer := 9;
Mbyte : integer := 16;
rstdel : integer := 200;
pwron : integer := 0;
oepol : integer := 0;
ddrbits : integer := 16;
ahbfreq : integer := 50;
readdly : integer := 1;
ddelayb0 : integer := 0;
ddelayb1 : integer := 0;
ddelayb2 : integer := 0;
ddelayb3 : integer := 0;
ddelayb4 : integer := 0;
ddelayb5 : integer := 0;
ddelayb6 : integer := 0;
ddelayb7 : integer := 0;
numidelctrl : integer := 4;
norefclk : integer := 0;
odten : integer := 0
);
port (
rst_ddr : in std_ulogic;
rst_ahb : in std_ulogic;
clk_ddr : in std_ulogic;
clk_ahb : in std_ulogic;
clkref200 : in std_ulogic;
lock : out std_ulogic; -- DCM locked
clkddro : out std_ulogic; -- DCM locked
clkddri : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
ddr_clk : out std_logic_vector(2 downto 0);
ddr_clkb : out std_logic_vector(2 downto 0);
-- ddr_clk_fb_out : out std_logic;
-- ddr_clk_fb : in std_logic;
ddr_cke : out std_logic_vector(1 downto 0);
ddr_csb : out std_logic_vector(1 downto 0);
ddr_web : out std_ulogic; -- ddr write enable
ddr_rasb : out std_ulogic; -- ddr ras
ddr_casb : out std_ulogic; -- ddr cas
ddr_dm : out std_logic_vector (ddrbits/8-1 downto 0); -- ddr dm
ddr_dqs : inout std_logic_vector (ddrbits/8-1 downto 0); -- ddr dqs
ddr_dqsn : inout std_logic_vector (ddrbits/8-1 downto 0); -- ddr dqsn
ddr_ad : out std_logic_vector (13 downto 0); -- ddr address
ddr_ba : out std_logic_vector (1 downto 0); -- ddr bank address
ddr_dq : inout std_logic_vector (ddrbits-1 downto 0); -- ddr data
ddr_odt : out std_logic_vector(1 downto 0)
);
end component;
component ddr_phy
generic (tech : integer := virtex2; MHz : integer := 100;
rstdelay : integer := 200; dbits : integer := 16;
clk_mul : integer := 2 ; clk_div : integer := 2;
rskew : integer := 0);
port (
rst : in std_ulogic;
clk : in std_logic; -- input clock
clkout : out std_ulogic; -- system clock
clkread : out std_ulogic; -- system clock
lock : out std_ulogic; -- DCM locked
ddr_clk : out std_logic_vector(2 downto 0);
ddr_clkb : out std_logic_vector(2 downto 0);
ddr_clk_fb_out : out std_logic;
ddr_clk_fb : in std_logic;
ddr_cke : out std_logic_vector(1 downto 0);
ddr_csb : out std_logic_vector(1 downto 0);
ddr_web : out std_ulogic; -- ddr write enable
ddr_rasb : out std_ulogic; -- ddr ras
ddr_casb : out std_ulogic; -- ddr cas
ddr_dm : out std_logic_vector (dbits/8-1 downto 0); -- ddr dm
ddr_dqs : inout std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
ddr_ad : out std_logic_vector (13 downto 0); -- ddr address
ddr_ba : out std_logic_vector (1 downto 0); -- ddr bank address
ddr_dq : inout std_logic_vector (dbits-1 downto 0); -- ddr data
sdi : out sdctrl_in_type;
sdo : in sdctrl_out_type);
end component;
component ddr2_phy
generic (tech : integer := virtex2; MHz : integer := 100;
rstdelay : integer := 200; dbits : integer := 16;
clk_mul : integer := 2 ; clk_div : integer := 2;
ddelayb0 : integer := 0; ddelayb1 : integer := 0; ddelayb2 : integer := 0;
ddelayb3 : integer := 0; ddelayb4 : integer := 0; ddelayb5 : integer := 0;
ddelayb6 : integer := 0; ddelayb7 : integer := 0;
numidelctrl : integer := 4; norefclk : integer := 0);
port (
rst : in std_ulogic;
clk : in std_logic; -- input clock
clkref200 : in std_logic; -- input 200MHz clock
clkout : out std_ulogic; -- system clock
lock : out std_ulogic; -- DCM locked
ddr_clk : out std_logic_vector(2 downto 0);
ddr_clkb : out std_logic_vector(2 downto 0);
ddr_cke : out std_logic_vector(1 downto 0);
ddr_csb : out std_logic_vector(1 downto 0);
ddr_web : out std_ulogic; -- ddr write enable
ddr_rasb : out std_ulogic; -- ddr ras
ddr_casb : out std_ulogic; -- ddr cas
ddr_dm : out std_logic_vector (dbits/8-1 downto 0); -- ddr dm
ddr_dqs : inout std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
ddr_dqsn : inout std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
ddr_ad : out std_logic_vector (13 downto 0); -- ddr address
ddr_ba : out std_logic_vector (1 downto 0); -- ddr bank address
ddr_dq : inout std_logic_vector (dbits-1 downto 0); -- ddr data
ddr_odt : out std_logic_vector(1 downto 0);
sdi : out sdctrl_in_type;
sdo : in sdctrl_out_type);
end component;
component ftsrctrl8 is
generic (
hindex : integer := 0;
ramaddr : integer := 16#400#;
rammask : integer := 16#ff0#;
ioaddr : integer := 16#200#;
iomask : integer := 16#ff0#;
ramws : integer := 0;
iows : integer := 2;
srbanks : integer range 1 to 8 := 1;
banksz : integer range 0 to 15 := 15;
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#fff#;
edacen : integer range 0 to 1 := 1;
errcnt : integer range 0 to 1 := 1;
cntbits : integer range 1 to 8 := 1;
wsreg : integer := 0;
oepol : integer := 0
);
port (
rst : in std_ulogic;
clk : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
sri : in memory_in_type;
sro : out memory_out_type
);
end component;
end;
| mit | e294be96d1c2a25b6faafa9d2a57bf92 | 0.522135 | 3.418291 | false | false | false | false |
impedimentToProgress/UCI-BlueChip | AttackFiles/Attacks/privEsc/lib/techmap/maps/alltap.vhd | 2 | 5,468 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: tap_gen
-- File: tap_gen.vhd
-- Author: Edvin Catovic - Gaisler Research
-- Description: JTAG Test Access Port (TAP) Controller component declaration
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
package alltap is
component tap_gen
generic (
irlen : integer range 2 to 8 := 2;
idcode : integer range 0 to 255 := 9;
manf : integer range 0 to 2047 := 804;
part : integer range 0 to 65535 := 0;
ver : integer range 0 to 15 := 0;
trsten : integer range 0 to 1 := 1;
scantest : integer := 0);
port (
trst : in std_ulogic;
tckp : in std_ulogic;
tckn : in std_ulogic;
tms : in std_ulogic;
tdi : in std_ulogic;
tdo : out std_ulogic;
tapi_en1 : in std_ulogic;
tapi_tdo1 : in std_ulogic;
tapi_tdo2 : in std_ulogic;
tapo_tck : out std_ulogic;
tapo_tdi : out std_ulogic;
tapo_inst : out std_logic_vector(7 downto 0);
tapo_rst : out std_ulogic;
tapo_capt : out std_ulogic;
tapo_shft : out std_ulogic;
tapo_upd : out std_ulogic;
tapo_xsel1 : out std_ulogic;
tapo_xsel2 : out std_ulogic;
testen : in std_ulogic := '0';
testrst : in std_ulogic := '1';
tdoen : out std_ulogic
);
end component;
component virtex_tap
port (
tapi_tdo1 : in std_ulogic;
tapi_tdo2 : in std_ulogic;
tapo_tck : out std_ulogic;
tapo_tdi : out std_ulogic;
tapo_rst : out std_ulogic;
tapo_capt : out std_ulogic;
tapo_shft : out std_ulogic;
tapo_upd : out std_ulogic;
tapo_xsel1 : out std_ulogic;
tapo_xsel2 : out std_ulogic
);
end component;
component virtex2_tap
port (
tapi_tdo1 : in std_ulogic;
tapi_tdo2 : in std_ulogic;
tapo_tck : out std_ulogic;
tapo_tdi : out std_ulogic;
tapo_rst : out std_ulogic;
tapo_capt : out std_ulogic;
tapo_shft : out std_ulogic;
tapo_upd : out std_ulogic;
tapo_xsel1 : out std_ulogic;
tapo_xsel2 : out std_ulogic
);
end component;
component virtex4_tap
port (
tapi_tdo1 : in std_ulogic;
tapi_tdo2 : in std_ulogic;
tapo_tck : out std_ulogic;
tapo_tdi : out std_ulogic;
tapo_rst : out std_ulogic;
tapo_capt : out std_ulogic;
tapo_shft : out std_ulogic;
tapo_upd : out std_ulogic;
tapo_xsel1 : out std_ulogic;
tapo_xsel2 : out std_ulogic
);
end component;
component virtex5_tap
port (
tapi_tdo1 : in std_ulogic;
tapi_tdo2 : in std_ulogic;
tapo_tck : out std_ulogic;
tapo_tdi : out std_ulogic;
tapo_rst : out std_ulogic;
tapo_capt : out std_ulogic;
tapo_shft : out std_ulogic;
tapo_upd : out std_ulogic;
tapo_xsel1 : out std_ulogic;
tapo_xsel2 : out std_ulogic
);
end component;
component spartan3_tap
port (
tapi_tdo1 : in std_ulogic;
tapi_tdo2 : in std_ulogic;
tapo_tck : out std_ulogic;
tapo_tdi : out std_ulogic;
tapo_rst : out std_ulogic;
tapo_capt : out std_ulogic;
tapo_shft : out std_ulogic;
tapo_upd : out std_ulogic;
tapo_xsel1 : out std_ulogic;
tapo_xsel2 : out std_ulogic
);
end component;
component altera_tap
port (
tapi_tdo1 : in std_ulogic;
tapi_tdo2 : in std_ulogic;
tapo_tck : out std_ulogic;
tapo_tdi : out std_ulogic;
tapo_inst : out std_logic_vector(7 downto 0);
tapo_rst : out std_ulogic;
tapo_capt : out std_ulogic;
tapo_shft : out std_ulogic;
tapo_upd : out std_ulogic;
tapo_xsel1 : out std_ulogic;
tapo_xsel2 : out std_ulogic
);
end component;
component proasic3_tap
port (
tck : in std_ulogic;
tms : in std_ulogic;
tdi : in std_ulogic;
trst : in std_ulogic;
tdo : out std_ulogic;
tapi_tdo1 : in std_ulogic;
tapi_tdo2 : in std_ulogic;
tapi_en1 : in std_ulogic;
tapo_tck : out std_ulogic;
tapo_tdi : out std_ulogic;
tapo_rst : out std_ulogic;
tapo_capt : out std_ulogic;
tapo_shft : out std_ulogic;
tapo_upd : out std_ulogic;
tapo_inst : out std_logic_vector(7 downto 0)
);
end component;
end;
| mit | ef34ba03d07cbbab3d091388942e5693 | 0.565472 | 3.458571 | false | false | false | false |
impedimentToProgress/UCI-BlueChip | AttackFiles/Attacks/privEsc/lib/opencores/ata/atahost_pio_controller.vhd | 2 | 13,360 | ---------------------------------------------------------------------
---- ----
---- OpenCores IDE Controller ----
---- ATA/ATAPI-5 PIO controller with write PingPong ----
---- ----
---- Author: Richard Herveille ----
---- [email protected] ----
---- www.asics.ws ----
---- ----
---------------------------------------------------------------------
---- ----
---- Copyright (C) 2001, 2002 Richard Herveille ----
---- [email protected] ----
---- ----
---- This source file may be used and distributed without ----
---- restriction provided that this copyright statement is not ----
---- removed from the file and that any derivative work contains ----
---- the original copyright notice and the associated disclaimer.----
---- ----
---- THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ----
---- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ----
---- TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ----
---- FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ----
---- OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ----
---- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ----
---- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ----
---- GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ----
---- BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ----
---- LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ----
---- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ----
---- OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ----
---- POSSIBILITY OF SUCH DAMAGE. ----
---- ----
---------------------------------------------------------------------
-- rev.: 1.0 march 8th, 2001. Initial release
--
-- CVS Log
--
-- $Id: atahost_pio_controller.vhd,v 1.1 2002/02/18 14:32:12 rherveille Exp $
--
-- $Date: 2002/02/18 14:32:12 $
-- $Revision: 1.1 $
-- $Author: rherveille $
-- $Locker: $
-- $State: Exp $
--
-- Change History:
-- $Log: atahost_pio_controller.vhd,v $
-- Revision 1.1 2002/02/18 14:32:12 rherveille
-- renamed all files to 'atahost_***.vhd'
-- broke-up 'counter.vhd' into 'ud_cnt.vhd' and 'ro_cnt.vhd'
-- changed resD input to generic RESD in ud_cnt.vhd
-- changed ID input to generic ID in ro_cnt.vhd
-- changed core to reflect changes in ro_cnt.vhd
-- removed references to 'count' library
-- changed IO names
-- added disclaimer
-- added CVS log
-- moved registers and wishbone signals into 'atahost_wb_slave.vhd'
--
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity atahost_pio_controller is
generic(
TWIDTH : natural := 8; -- counter width
-- PIO mode 0 settings (@100MHz clock)
PIO_mode0_T1 : natural := 6; -- 70ns
PIO_mode0_T2 : natural := 28; -- 290ns
PIO_mode0_T4 : natural := 2; -- 30ns
PIO_mode0_Teoc : natural := 23 -- 240ns ==> T0 - T1 - T2 = 600 - 70 - 290 = 240
);
port(
clk : in std_logic; -- master clock in
nReset : in std_logic; -- asynchronous active low reset
rst : in std_logic; -- synchronous active high reset
-- control / registers
IDEctrl_IDEen,
IDEctrl_ppen,
IDEctrl_FATR0,
IDEctrl_FATR1 : in std_logic;
-- PIO registers
cmdport_T1,
cmdport_T2,
cmdport_T4,
cmdport_Teoc : in std_logic_vector(7 downto 0);
cmdport_IORDYen : in std_logic; -- PIO command port / non-fast timing
dport0_T1,
dport0_T2,
dport0_T4,
dport0_Teoc : in std_logic_vector(7 downto 0);
dport0_IORDYen : in std_logic; -- PIO mode data-port / fast timing device 0
dport1_T1,
dport1_T2,
dport1_T4,
dport1_Teoc : in std_logic_vector(7 downto 0);
dport1_IORDYen : in std_logic; -- PIO mode data-port / fast timing device 1
sel : in std_logic; -- PIO controller selected
ack : out std_logic; -- PIO controller acknowledge
a : in std_logic_vector(3 downto 0); -- lower address bits
we : in std_logic; -- write enable input
d : in std_logic_vector(15 downto 0);
q : out std_logic_vector(15 downto 0);
PIOreq : out std_logic; -- PIO transfer request
PPFull : out std_logic; -- PIO Write PingPong Full
go : in std_logic; -- start PIO transfer
done : out std_logic; -- done with PIO transfer
PIOa : out std_logic_vector(3 downto 0); -- PIO address, address lines towards ATA devices
PIOd : out std_logic_vector(15 downto 0); -- PIO data, data towards ATA devices
SelDev : out std_logic; -- Selected Device, Dev-bit in ATA Device/Head register
DDi : in std_logic_vector(15 downto 0);
DDoe : out std_logic;
DIOR : out std_logic;
DIOW : out std_logic;
IORDY : in std_logic
);
end entity atahost_pio_controller;
architecture structural of atahost_pio_controller is
--
-- component declarations
--
component atahost_pio_actrl is
generic(
TWIDTH : natural := 8; -- counter width
-- PIO mode 0 settings (@100MHz clock)
PIO_mode0_T1 : natural := 6; -- 70ns
PIO_mode0_T2 : natural := 28; -- 290ns
PIO_mode0_T4 : natural := 2; -- 30ns
PIO_mode0_Teoc : natural := 23 -- 240ns ==> T0 - T1 - T2 = 600 - 70 - 290 = 240
);
port(
clk : in std_logic; -- master clock
nReset : in std_logic; -- asynchronous active low reset
rst : in std_logic; -- synchronous active high reset
IDEctrl_FATR0,
IDEctrl_FATR1 : in std_logic;
cmdport_T1,
cmdport_T2,
cmdport_T4,
cmdport_Teoc : in std_logic_vector(7 downto 0);
cmdport_IORDYen : in std_logic; -- PIO command port / non-fast timing
dport0_T1,
dport0_T2,
dport0_T4,
dport0_Teoc : in std_logic_vector(7 downto 0);
dport0_IORDYen : in std_logic; -- PIO mode data-port / fast timing device 0
dport1_T1,
dport1_T2,
dport1_T4,
dport1_Teoc : in std_logic_vector(7 downto 0);
dport1_IORDYen : in std_logic; -- PIO mode data-port / fast timing device 1
SelDev : in std_logic; -- Selected device
go : in std_logic; -- Start transfer sequence
done : out std_logic; -- Transfer sequence done
dir : in std_logic; -- Transfer direction '1'=write, '0'=read
a : in std_logic_vector(3 downto 0); -- PIO transfer address
q : out std_logic_vector(15 downto 0); -- Data read from ATA devices
DDi : in std_logic_vector(15 downto 0); -- Data from ATA DD bus
oe : out std_logic; -- DDbus output-enable signal
DIOR,
DIOW : out std_logic;
IORDY : in std_logic
);
end component atahost_pio_actrl;
--
-- signals
--
-- PIO pingpong signals
signal pp_d : std_logic_vector(15 downto 0);
signal pp_a : std_logic_vector(3 downto 0);
signal pp_we : std_logic;
signal idone : std_logic;
signal iSelDev : std_logic;
begin
--
-- generate selected device
--
gen_seldev: process(clk, pp_a)
variable Asel : std_logic; -- address selected
begin
Asel := not pp_a(3) and pp_a(2) and pp_a(1) and not pp_a(0); -- header/device register
if (clk'event and clk = '1') then
if ( (idone = '1') and (Asel = '1') and (pp_we = '1') ) then
iSelDev <= pp_d(4);
end if;
end if;
end process gen_seldev;
--
-- generate PIO write pingpong system
--
gen_pingpong: block
signal ping_d, pong_d : std_logic_vector(15 downto 0);
signal ping_a, pong_a : std_logic_vector(3 downto 0);
signal ping_we, pong_we : std_logic;
signal ping_valid, pong_valid : std_logic;
signal dping_valid, dpong_valid : std_logic;
signal wpp, rpp : std_logic;
signal dsel, sel_strb : std_logic;
signal iack : std_logic;
begin
-- generate PIO acknowledge
gen_ack: process(clk, ping_valid, dping_valid, pong_valid, dpong_valid, we)
variable ping_re, ping_fe, pong_re, pong_fe : std_logic;
begin
-- detect rising edge of ping_valid and pong_valid
ping_re := ping_valid and not dping_valid and we;
pong_re := pong_valid and not dpong_valid and we;
-- detect falling edge of ping_valid and pong_valid
ping_fe := not ping_valid and dping_valid;
pong_fe := not pong_valid and dpong_valid;
if (clk'event and clk = '1') then
if ((pp_we = '1') and (IDEctrl_ppen = '1')) then -- write sequence
if (wpp = '1') then
iack <= ping_re;
else
iack <= pong_re;
end if;
else -- read sequence
if (rpp = '1') then
iack <= ping_fe;
else
iack <= pong_fe;
end if;
end if;
end if;
end process gen_ack;
ack <= (iack or not IDEctrl_IDEen) and sel; -- acknowledge access when not enabled (discard access)
-- generate select-strobe, hold sel_strb until pingpong system ready for new data
gen_sel_strb: process(clk, nReset)
begin
if (nReset = '0') then
dsel <= '0';
elsif (clk'event and clk = '1') then
if (rst = '1') then
dsel <= '0';
else
dsel <= sel_strb or (dsel and sel);
end if;
end if;
end process gen_sel_strb;
sel_strb <= sel and not dsel and IDEctrl_IDEen and ((wpp and not ping_valid) or (not wpp and not pong_valid));
-- generate pingpong control
gen_pp : process(clk, nReset)
begin
if (nReset = '0') then
wpp <= '0';
rpp <= '0';
ping_valid <= '0';
pong_valid <= '0';
dping_valid <= '0';
dpong_valid <= '0';
elsif (clk'event and clk = '1') then
if (rst = '1') then
wpp <= '0';
rpp <= '0';
ping_valid <= '0';
pong_valid <= '0';
dping_valid <= '0';
dpong_valid <= '0';
else
wpp <= (wpp xor (iack and we)) and IDEctrl_ppen;
rpp <= (rpp xor (idone and pp_we)) and IDEctrl_ppen;
ping_valid <= (( wpp and sel_strb) or ping_valid) and not ( rpp and idone);
pong_valid <= ((not wpp and sel_strb) or pong_valid) and not (not rpp and idone);
dping_valid <= ping_valid;
dpong_valid <= pong_valid;
end if;
end if;
end process gen_pp;
-- generate pingpong full signal
PPFull <= (ping_valid and pong_valid) when (IDEctrl_ppen = '1') else pong_valid;
-- fill ping/pong registers
fill_pp: process(clk)
begin
if (clk'event and clk = '1') then
if (sel = '1') then
if (wpp = '1') then
if (ping_valid = '0') then
ping_d <= d;
ping_a <= a;
ping_we <= we;
end if;
else
if (pong_valid = '0') then
pong_d <= d;
pong_a <= a;
pong_we <= we;
end if;
end if;
end if;
end if;
end process fill_pp;
-- multiplex pingpong data to pp_d, pp_a, pp_we
pp_d <= d;
pp_a <= a;
pp_we <= we;
--edit by erik (no pp)
-- pp_d <= ping_d when (rpp = '1') else pong_d;
-- pp_a <= ping_a when (rpp = '1') else pong_a;
-- pp_we <= ping_we when (rpp = '1') else pong_we;
-- generate PIOreq
PIOreq <= (ping_valid and not idone) when (rpp = '1') else (pong_valid and not idone);
end block gen_pingpong;
--
-- Hookup PIO access controller
--
PIO_access_control: atahost_pio_actrl
generic map(
TWIDTH => TWIDTH,
PIO_mode0_T1 => PIO_mode0_T1,
PIO_mode0_T2 => PIO_mode0_T2,
PIO_mode0_T4 => PIO_mode0_T4,
PIO_mode0_Teoc => PIO_mode0_Teoc
)
port map(
clk => clk,
nReset => nReset,
rst => rst,
IDEctrl_FATR0 => IDEctrl_FATR0,
IDEctrl_FATR1 => IDEctrl_FATR1,
cmdport_T1 => cmdport_T1,
cmdport_T2 => cmdport_T2,
cmdport_T4 => cmdport_T4,
cmdport_Teoc => cmdport_Teoc,
cmdport_IORDYen => cmdport_IORDYen,
dport0_T1 => dport0_T1,
dport0_T2 => dport0_T2,
dport0_T4 => dport0_T4,
dport0_Teoc => dport0_Teoc,
dport0_IORDYen => dport0_IORDYen,
dport1_T1 => dport1_T1,
dport1_T2 => dport1_T2,
dport1_T4 => dport1_T4,
dport1_Teoc => dport1_Teoc,
dport1_IORDYen => dport1_IORDYen,
SelDev => iSelDev,
go => go,
done => idone,
dir => pp_we,
a => pp_a,
q => Q,
DDi => DDi,
oe => DDoe,
DIOR => dior,
DIOW => diow,
IORDY => IORDY
);
--
-- assign outputs
--
PIOa <= pp_a;
PIOd <= pp_d;
Done <= idone;
SelDev <= iSelDev;
end architecture structural;
| mit | f3e3008efe8b8eef7ff234d984cbf30a | 0.535329 | 3.202301 | false | false | false | false |
cafe-alpha/wascafe | v13/r07c_de10_20201014_abus4/abus_avalon_sdram_bridge_tb.vhd | 2 | 18,551 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity abus_avalon_sdram_bridge_tb is
end abus_avalon_sdram_bridge_tb;
architecture Behavioral of abus_avalon_sdram_bridge_tb is
component abus_avalon_sdram_bridge is
port (
clock : in std_logic := '0'; -- clock.clk
abus_address : in std_logic_vector(9 downto 0) := (others => '0'); -- abus.address
abus_addressdata : inout std_logic_vector(15 downto 0) := (others => '0'); -- abus.addressdata
abus_chipselect : in std_logic_vector(2 downto 0) := (others => '0'); -- .chipselect
abus_read : in std_logic := '0'; -- .read
abus_write : in std_logic_vector(1 downto 0) := (others => '0'); -- .write
abus_waitrequest : out std_logic := '1'; -- .waitrequest
abus_interrupt : out std_logic := '0'; -- .interrupt
abus_direction : out std_logic := '0'; -- .direction
abus_muxing : out std_logic_vector(1 downto 0) := "01"; -- .muxing
abus_disable_out : out std_logic := '0'; -- .disableout
sdram_addr : out std_logic_vector(12 downto 0); -- external_sdram_controller_wire.addr
sdram_ba : out std_logic_vector(1 downto 0); -- .ba
sdram_cas_n : out std_logic; -- .cas_n
sdram_cke : out std_logic; -- .cke
sdram_cs_n : out std_logic; -- .cs_n
sdram_dq : inout std_logic_vector(15 downto 0) := (others => '0'); -- .dq
sdram_dqm : out std_logic_vector(1 downto 0); -- .dqm
sdram_ras_n : out std_logic; -- .ras_n
sdram_we_n : out std_logic; -- .we_n
sdram_clk : out std_logic;
avalon_sdram_read : in std_logic := '0'; -- avalon_master.read
avalon_sdram_write : in std_logic := '0'; -- .write
avalon_sdram_waitrequest : out std_logic := '0'; -- .waitrequest
avalon_sdram_address : in std_logic_vector(24 downto 0) := (others => '0'); -- .address
avalon_sdram_writedata : in std_logic_vector(15 downto 0) := (others => '0'); -- .writedata
avalon_sdram_readdata : out std_logic_vector(15 downto 0) := (others => '0'); -- .readdata
avalon_sdram_readdatavalid : out std_logic := '0'; -- .readdatavalid
avalon_regs_read : in std_logic := '0'; -- avalon_master.read
avalon_regs_write : in std_logic := '0'; -- .write
avalon_regs_waitrequest : out std_logic := '0'; -- .waitrequest
avalon_regs_address : in std_logic_vector(7 downto 0) := (others => '0'); -- .address
avalon_regs_writedata : in std_logic_vector(15 downto 0) := (others => '0'); -- .writedata
avalon_regs_readdata : out std_logic_vector(15 downto 0) := (others => '0'); -- .readdata
avalon_regs_readdatavalid : out std_logic := '0'; -- .readdatavalid
saturn_reset : in std_logic := '0'; -- .saturn_reset
reset : in std_logic := '0' -- reset.reset
);
end component;
component sdram_controller is
port(
-- HOST INTERFACE
wr_addr: in std_logic_vector(23 downto 0);
wr_data: in std_logic_vector(15 downto 0);
wr_enable: in std_logic;
rd_addr: in std_logic_vector(23 downto 0);
rd_data: out std_logic_vector(15 downto 0);
rd_ready: out std_logic;
rd_enable: in std_logic;
busy: out std_logic;
rst_n: in std_logic;
clk: in std_logic;
-- SDRAM SIDE
addr : out std_logic_vector(12 downto 0); -- external_sdram_controller_wire.addr
bank_addr : out std_logic_vector(1 downto 0); -- .ba
cas_n : out std_logic; -- .cas_n
clock_enable : out std_logic; -- .cke
cs_n : out std_logic; -- .cs_n
data : inout std_logic_vector(15 downto 0) := (others => '0'); -- .dq
data_mask_low: out std_logic;
data_mask_high: out std_logic;
ras_n : out std_logic; -- .ras_n
we_n : out std_logic
);
end component;
----------------------ins
signal clock : std_logic := '0'; -- clock.clk
signal abus_address : std_logic_vector(9 downto 0) := (others => '0'); -- abus.address
signal abus_chipselect : std_logic_vector(2 downto 0) := (others => '1'); -- .chipselect
signal abus_read : std_logic := '1'; -- .read
signal abus_write : std_logic_vector(1 downto 0) := (others => '1'); -- .write
signal avalon_sdram_read : std_logic := '0'; -- avalon_master.read
signal avalon_sdram_write : std_logic := '0'; -- .write
signal avalon_sdram_address : std_logic_vector(24 downto 0) := (others => '0'); -- .address
signal avalon_sdram_writedata : std_logic_vector(15 downto 0) := (others => '0'); -- .writedata
signal avalon_regs_read : std_logic := '0'; -- avalon_master.read
signal avalon_regs_write : std_logic := '0'; -- .write
signal avalon_regs_address : std_logic_vector(7 downto 0) := (others => '0'); -- .address
signal avalon_regs_writedata : std_logic_vector(15 downto 0) := (others => '0'); -- .writedata
signal saturn_reset : std_logic := '0'; -- .saturn_reset
signal reset : std_logic := '0'; -- reset.reset
----------------------outs
signal abus_waitrequest : std_logic := '1'; -- .waitrequest
signal abus_interrupt : std_logic := '0'; -- .interrupt
signal abus_direction : std_logic := '0'; -- .direction
signal abus_muxing : std_logic_vector(1 downto 0) := "01"; -- .muxing
signal abus_disable_out : std_logic := '0'; -- .disableout
signal sdram_addr : std_logic_vector(12 downto 0); -- external_sdram_controller_wire.addr
signal sdram_ba : std_logic_vector(1 downto 0); -- .ba
signal sdram_cas_n : std_logic; -- .cas_n
signal sdram_cke : std_logic; -- .cke
signal sdram_cs_n : std_logic;
signal sdram_dqm : std_logic_vector(1 downto 0); -- .dqm
signal sdram_ras_n : std_logic; -- .ras_n
signal sdram_we_n : std_logic; -- .we_n
signal sdram_clk : std_logic;
signal avalon_sdram_waitrequest : std_logic := '0'; -- .waitrequest
signal avalon_sdram_readdata : std_logic_vector(15 downto 0) := (others => '0'); -- .readdata
signal avalon_sdram_readdatavalid : std_logic := '0'; -- .readdatavalid
signal avalon_regs_waitrequest : std_logic := '0'; -- .waitrequest
signal avalon_regs_readdata : std_logic_vector(15 downto 0) := (others => '0'); -- .readdata
signal avalon_regs_readdatavalid : std_logic := '0'; -- .readdatavalid
----------------------inouts
signal abus_addressdata : std_logic_vector(15 downto 0) := (others => '0'); -- abus.addressdata
signal sdram_dq : std_logic_vector(15 downto 0) := (others => '0'); -- .dq
signal abus_full_address : std_logic_vector(25 downto 0) := (others => '0');
signal abus_data_in : std_logic_vector(15 downto 0) := (others => '0');
------------- reference controller
signal refer_wr_addr: std_logic_vector(23 downto 0) := (others => '0');
signal refer_wr_data: std_logic_vector(15 downto 0) := (others => '0');
signal refer_wr_enable: std_logic;
signal refer_rd_addr: std_logic_vector(23 downto 0) := (others => '0');
signal refer_rd_data: std_logic_vector(15 downto 0) := (others => '0');
signal refer_rd_ready: std_logic;
signal refer_rd_enable: std_logic := '0';
signal refer_busy: std_logic;
signal refer_rst_n: std_logic := '1';
procedure write_abus_16 (addry : in std_logic_vector(25 downto 0);
datty : in std_logic_vector(15 downto 0);
csy : in std_logic_vector(2 downto 0);
wry : in std_logic_vector(1 downto 0);
signal Abus_Ad : out std_logic_vector(25 downto 0);
signal Abus_Da : out std_logic_vector(15 downto 0);
signal Abus_CS : out std_logic_vector(2 downto 0);
signal Abus_Wri : out std_logic_vector(1 downto 0);
signal Ref_Ad : out std_logic_vector(23 downto 0);
signal Ref_Da : out std_logic_vector(15 downto 0);
signal Ref_Wri : out std_logic
) is
begin
Abus_Ad <= addry;
Ref_Ad <= addry(24 downto 1);
Ref_Da <= datty;
wait for 10ns;
Abus_Da <= datty;
wait for 10ns;
Abus_CS <= csy;
wait for 10ns;
Abus_Wri <= wry;
wait for 5ns;
Ref_Wri <= '1';
wait for 10ns;
Ref_Wri <= '0';
wait for 185ns;
Abus_CS <= "111";
wait for 10ns;
Abus_Wri <= "11";
wait for 10ns;
end write_abus_16;
procedure read_abus_16 (addry : in std_logic_vector(25 downto 0);
csy : in std_logic_vector(2 downto 0);
signal Abus_Ad : out std_logic_vector(25 downto 0);
signal Abus_CS : out std_logic_vector(2 downto 0);
signal Abus_Re : out std_logic;
signal Ref_Ad : out std_logic_vector(23 downto 0);
signal Ref_Re : out std_logic
) is
begin
Abus_Ad <= addry;
Ref_Ad <= addry(24 downto 1);
wait for 10ns;
Abus_CS <= csy;
wait for 10ns;
Abus_Re <= '0';
wait for 10ns;
Ref_Re <= '1';
wait for 10ns;
Ref_Re <= '0';
wait for 200ns;
Abus_CS <= "111";
wait for 10ns;
Abus_Re <= '1';
wait for 10ns;
end read_abus_16;
procedure write_avalon_16 (addry : in std_logic_vector(25 downto 0);
datty : in std_logic_vector(15 downto 0);
signal Ava_Ad : out std_logic_vector(24 downto 0);
signal Ava_Da : out std_logic_vector(15 downto 0);
signal Ava_Wri : out std_logic;
signal Ref_Ad : out std_logic_vector(23 downto 0);
signal Ref_Da : out std_logic_vector(15 downto 0);
signal Ref_Wri : out std_logic
) is
begin
Ava_Ad <= addry(24 downto 0);
Ref_Ad <= addry(24 downto 1);
Ref_Da <= datty;
Ava_Da <= datty;
wait for 10ns;
Ava_Wri <= '1';
wait for 10ns;
Ref_Wri <= '1';
Ava_Wri <= '0';
wait for 10ns;
Ref_Wri <= '0';
end write_avalon_16;
procedure read_avalon_16 (addry : in std_logic_vector(25 downto 0);
signal Ava_Ad : out std_logic_vector(24 downto 0);
signal Ava_Re : out std_logic;
signal Ref_Ad : out std_logic_vector(23 downto 0);
signal Ref_Re : out std_logic
) is
begin
Ava_Ad <= addry(24 downto 0);
Ref_Ad <= addry(24 downto 1);
wait for 10ns;
Ava_Re <= '1';
wait for 10ns;
Ref_Re <= '1';
Ava_Re <= '0';
wait for 10ns;
Ref_Re <= '0';
end read_avalon_16;
begin
clock <= not clock after 4310 ps; --116 MHz clock
--address/data mux
abus_addressdata <= abus_full_address(5) & abus_full_address(6) & abus_full_address(7) & abus_full_address(14) &
abus_full_address(15) & abus_full_address(12) & abus_full_address(13) & abus_full_address(8) &
abus_full_address(0) & abus_full_address(2) & abus_full_address(3) & abus_full_address(4) &
abus_full_address(9) & abus_full_address(11) & abus_full_address(10) & abus_full_address(1)
when abus_muxing = "10" else
abus_data_in when abus_direction = '0' else
(others => 'Z');
abus_address <= abus_full_address(25 downto 16);
UUT: abus_avalon_sdram_bridge
port map(
clock => clock,
abus_address => abus_address,
abus_addressdata => abus_addressdata,
abus_chipselect => abus_chipselect,
abus_read => abus_read,
abus_write => abus_write,
abus_waitrequest => abus_waitrequest,
abus_interrupt => abus_interrupt,
abus_direction => abus_direction,
abus_muxing => abus_muxing,
abus_disable_out => abus_disable_out,
sdram_addr => sdram_addr,
sdram_ba => sdram_ba,
sdram_cas_n => sdram_cas_n,
sdram_cke => sdram_cke,
sdram_cs_n => sdram_cs_n,
sdram_dq => sdram_dq,
sdram_dqm => sdram_dqm,
sdram_ras_n => sdram_ras_n,
sdram_we_n => sdram_we_n,
sdram_clk => sdram_clk,
avalon_sdram_read => avalon_sdram_read,
avalon_sdram_write => avalon_sdram_write,
avalon_sdram_waitrequest => avalon_sdram_waitrequest,
avalon_sdram_address => avalon_sdram_address,
avalon_sdram_writedata => avalon_sdram_writedata,
avalon_sdram_readdata => avalon_sdram_readdata,
avalon_sdram_readdatavalid => avalon_sdram_readdatavalid,
avalon_regs_read => avalon_regs_read,
avalon_regs_write => avalon_regs_write,
avalon_regs_waitrequest => avalon_regs_waitrequest,
avalon_regs_address => avalon_regs_address,
avalon_regs_writedata => avalon_regs_writedata,
avalon_regs_readdata => avalon_regs_readdata,
avalon_regs_readdatavalid => avalon_regs_readdatavalid,
saturn_reset => saturn_reset,
reset => reset
);
REFER: sdram_controller
port map(
clk => clock,
rst_n => refer_rst_n,
busy => open,
wr_addr => refer_wr_addr,
wr_data => refer_wr_data,
wr_enable => refer_wr_enable,
rd_addr => refer_rd_addr,
rd_data => refer_rd_data,
rd_ready => refer_rd_ready,
rd_enable => refer_rd_enable,
addr => open,
bank_addr => open,
cas_n => open,
clock_enable => open,
cs_n => open,
data => open,
data_mask_low => open,
data_mask_high => open,
ras_n => open,
we_n => open
);
process
begin
refer_rst_n <= '1';
wait for 100ns;
refer_rst_n <= '0';
wait for 100ns;
refer_rst_n <= '1';
wait for 800ns;
-- --abus normal read
-- read_abus_16("00"&X"EFAFAE","010",abus_full_address,abus_chipselect,abus_read,refer_rd_addr,refer_rd_enable);
-- --abus read while autorefresh
-- wait for 3150ns;
-- read_abus_16("00"&X"EFAFAE","010",abus_full_address,abus_chipselect,abus_read,refer_rd_addr,refer_rd_enable);
-- --abus normal write
-- wait for 1 us;
-- write_abus_16("00"&X"BABAFA",X"DADA","010","00",abus_full_address,abus_data_in,abus_chipselect,abus_write,refer_wr_addr,refer_wr_data,refer_wr_enable);
-- --abus write while autorefresh
-- wait for 2900ns;
--avalon normal write
wait for 500ns;
write_avalon_16("00"&X"EEE312",X"DADA",avalon_sdram_address,avalon_sdram_writedata,avalon_sdram_write,refer_wr_addr,refer_wr_data,refer_wr_enable);
wait for 500ns;
--avalon normal read
wait for 500ns;
read_avalon_16("00"&X"EEE312",avalon_sdram_address,avalon_sdram_read,refer_rd_addr,refer_rd_enable);
wait for 500ns;
wait;
end process;
end Behavioral;
| gpl-2.0 | 8d424e0f5e6ca78196605eccec4417b2 | 0.471349 | 3.792885 | false | false | false | false |
impedimentToProgress/UCI-BlueChip | AttackFiles/Attacks/memAttack/lib/gaisler/leon3/leon3.vhd | 1 | 27,590 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Package: leon3
-- File: leon3.vhd
-- Author: Jiri Gaisler, Gaisler Research
-- Description: LEON3 types and components
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
library techmap;
use techmap.gencomp.all;
package leon3 is
constant LEON3_VERSION : integer := 0;
type l3_irq_in_type is record
irl : std_logic_vector(3 downto 0);
rst : std_ulogic;
run : std_ulogic;
end record;
type l3_irq_out_type is record
intack : std_ulogic;
irl : std_logic_vector(3 downto 0);
pwd : std_ulogic;
end record;
type l3_debug_in_type is record
dsuen : std_ulogic; -- DSU enable
denable : std_ulogic; -- diagnostic register access enable
dbreak : std_ulogic; -- debug break-in
step : std_ulogic; -- single step
halt : std_ulogic; -- halt processor
reset : std_ulogic; -- reset processor
dwrite : std_ulogic; -- read/write
daddr : std_logic_vector(23 downto 2); -- diagnostic address
ddata : std_logic_vector(31 downto 0); -- diagnostic data
btrapa : std_ulogic; -- break on IU trap
btrape : std_ulogic; -- break on IU trap
berror : std_ulogic; -- break on IU error mode
bwatch : std_ulogic; -- break on IU watchpoint
bsoft : std_ulogic; -- break on software breakpoint (TA 1)
tenable : std_ulogic;
timer : std_logic_vector(30 downto 0); --
end record;
type l3_debug_out_type is record
data : std_logic_vector(31 downto 0);
crdy : std_ulogic;
dsu : std_ulogic;
dsumode : std_ulogic;
error : std_ulogic;
halt : std_ulogic;
pwd : std_ulogic;
idle : std_ulogic;
ipend : std_ulogic;
icnt : std_ulogic;
end record;
type l3_debug_in_vector is array (natural range <>) of l3_debug_in_type;
type l3_debug_out_vector is array (natural range <>) of l3_debug_out_type;
component leon3s
generic (
hindex : integer := 0;
fabtech : integer range 0 to NTECH := DEFFABTECH;
memtech : integer range 0 to NTECH := DEFMEMTECH;
nwindows : integer range 2 to 32 := 8;
dsu : integer range 0 to 1 := 0;
fpu : integer range 0 to 31 := 0;
v8 : integer range 0 to 63 := 0;
cp : integer range 0 to 1 := 0;
mac : integer range 0 to 1 := 0;
pclow : integer range 0 to 2 := 2;
notag : integer range 0 to 1 := 0;
nwp : integer range 0 to 4 := 0;
icen : integer range 0 to 1 := 0;
irepl : integer range 0 to 2 := 2;
isets : integer range 1 to 4 := 1;
ilinesize : integer range 4 to 8 := 4;
isetsize : integer range 1 to 256 := 1;
isetlock : integer range 0 to 1 := 0;
dcen : integer range 0 to 1 := 0;
drepl : integer range 0 to 2 := 2;
dsets : integer range 1 to 4 := 1;
dlinesize : integer range 4 to 8 := 4;
dsetsize : integer range 1 to 256 := 1;
dsetlock : integer range 0 to 1 := 0;
dsnoop : integer range 0 to 6 := 0;
ilram : integer range 0 to 1 := 0;
ilramsize : integer range 1 to 512 := 1;
ilramstart: integer range 0 to 255 := 16#8e#;
dlram : integer range 0 to 1 := 0;
dlramsize : integer range 1 to 512 := 1;
dlramstart: integer range 0 to 255 := 16#8f#;
mmuen : integer range 0 to 1 := 0;
itlbnum : integer range 2 to 64 := 8;
dtlbnum : integer range 2 to 64 := 8;
tlb_type : integer range 0 to 3 := 1;
tlb_rep : integer range 0 to 1 := 0;
lddel : integer range 1 to 2 := 2;
disas : integer range 0 to 2 := 0;
tbuf : integer range 0 to 64 := 0;
pwd : integer range 0 to 2 := 2; -- power-down
svt : integer range 0 to 1 := 1; -- single vector trapping
rstaddr : integer := 16#00000#; -- reset vector address [31:12]
smp : integer range 0 to 15 := 0; -- support SMP systems
cached : integer := 0; -- cacheability table
scantest : integer := 0
);
port (
clk : in std_ulogic;
rstn : in std_ulogic;
ahbi : in ahb_mst_in_type;
ahbo : out ahb_mst_out_type;
ahbsi : in ahb_slv_in_type;
ahbso : in ahb_slv_out_vector;
irqi : in l3_irq_in_type;
irqo : out l3_irq_out_type;
dbgi : in l3_debug_in_type;
dbgo : out l3_debug_out_type
);
end component;
component leon3cg
generic (
hindex : integer := 0;
fabtech : integer range 0 to NTECH := DEFFABTECH;
memtech : integer range 0 to NTECH := DEFMEMTECH;
nwindows : integer range 2 to 32 := 8;
dsu : integer range 0 to 1 := 0;
fpu : integer range 0 to 31 := 0;
v8 : integer range 0 to 63 := 0;
cp : integer range 0 to 1 := 0;
mac : integer range 0 to 1 := 0;
pclow : integer range 0 to 2 := 2;
notag : integer range 0 to 1 := 0;
nwp : integer range 0 to 4 := 0;
icen : integer range 0 to 1 := 0;
irepl : integer range 0 to 2 := 2;
isets : integer range 1 to 4 := 1;
ilinesize : integer range 4 to 8 := 4;
isetsize : integer range 1 to 256 := 1;
isetlock : integer range 0 to 1 := 0;
dcen : integer range 0 to 1 := 0;
drepl : integer range 0 to 2 := 2;
dsets : integer range 1 to 4 := 1;
dlinesize : integer range 4 to 8 := 4;
dsetsize : integer range 1 to 256 := 1;
dsetlock : integer range 0 to 1 := 0;
dsnoop : integer range 0 to 6 := 0;
ilram : integer range 0 to 1 := 0;
ilramsize : integer range 1 to 512 := 1;
ilramstart: integer range 0 to 255 := 16#8e#;
dlram : integer range 0 to 1 := 0;
dlramsize : integer range 1 to 512 := 1;
dlramstart: integer range 0 to 255 := 16#8f#;
mmuen : integer range 0 to 1 := 0;
itlbnum : integer range 2 to 64 := 8;
dtlbnum : integer range 2 to 64 := 8;
tlb_type : integer range 0 to 3 := 1;
tlb_rep : integer range 0 to 1 := 0;
lddel : integer range 1 to 2 := 2;
disas : integer range 0 to 2 := 0;
tbuf : integer range 0 to 64 := 0;
pwd : integer range 0 to 2 := 2; -- power-down
svt : integer range 0 to 1 := 1; -- single vector trapping
rstaddr : integer := 16#00000#; -- reset vector address [31:12]
smp : integer range 0 to 15 := 0; -- support SMP systems
cached : integer := 0; -- cacheability table
scantest : integer := 0
);
port (
clk : in std_ulogic;
rstn : in std_ulogic;
ahbi : in ahb_mst_in_type;
ahbo : out ahb_mst_out_type;
ahbsi : in ahb_slv_in_type;
ahbso : in ahb_slv_out_vector;
irqi : in l3_irq_in_type;
irqo : out l3_irq_out_type;
dbgi : in l3_debug_in_type;
dbgo : out l3_debug_out_type;
gclk : in std_ulogic
);
end component;
component leon3ft
generic (
hindex : integer := 0;
fabtech : integer range 0 to NTECH := DEFFABTECH;
memtech : integer range 0 to NTECH := DEFMEMTECH;
nwindows : integer range 2 to 32 := 8;
dsu : integer range 0 to 1 := 0;
fpu : integer range 0 to 31 := 0;
v8 : integer range 0 to 63 := 0;
cp : integer range 0 to 1 := 0;
mac : integer range 0 to 1 := 0;
pclow : integer range 0 to 2 := 2;
notag : integer range 0 to 1 := 0;
nwp : integer range 0 to 4 := 0;
icen : integer range 0 to 1 := 0;
irepl : integer range 0 to 2 := 2;
isets : integer range 1 to 4 := 1;
ilinesize : integer range 4 to 8 := 4;
isetsize : integer range 1 to 256 := 1;
isetlock : integer range 0 to 1 := 0;
dcen : integer range 0 to 1 := 0;
drepl : integer range 0 to 2 := 2;
dsets : integer range 1 to 4 := 1;
dlinesize : integer range 4 to 8 := 4;
dsetsize : integer range 1 to 256 := 1;
dsetlock : integer range 0 to 1 := 0;
dsnoop : integer range 0 to 6 := 0;
ilram : integer range 0 to 1 := 0;
ilramsize : integer range 1 to 512 := 1;
ilramstart: integer range 0 to 255 := 16#8e#;
dlram : integer range 0 to 1 := 0;
dlramsize : integer range 1 to 512 := 1;
dlramstart: integer range 0 to 255 := 16#8f#;
mmuen : integer range 0 to 1 := 0;
itlbnum : integer range 2 to 64 := 8;
dtlbnum : integer range 2 to 64 := 8;
tlb_type : integer range 0 to 3 := 1;
tlb_rep : integer range 0 to 1 := 0;
lddel : integer range 1 to 2 := 2;
disas : integer range 0 to 2 := 0;
tbuf : integer range 0 to 64 := 0;
pwd : integer range 0 to 2 := 2; -- power-down
svt : integer range 0 to 1 := 1; -- single vector trapping
rstaddr : integer := 16#00000#; -- reset vector address [31:12]
smp : integer range 0 to 15 := 0; -- support SMP systems
iuft : integer range 0 to 4 := 0;
fpft : integer range 0 to 4 := 0;
cmft : integer range 0 to 1 := 0;
iuinj : integer := 0;
ceinj : integer range 0 to 3 := 0;
cached : integer := 0; -- cacheability table
netlist : integer := 0; -- use netlist
scantest : integer := 0 -- enable scan test support
);
port (
clk : in std_ulogic;
rstn : in std_ulogic;
ahbi : in ahb_mst_in_type;
ahbo : out ahb_mst_out_type;
ahbsi : in ahb_slv_in_type;
ahbso : in ahb_slv_out_vector;
irqi : in l3_irq_in_type;
irqo : out l3_irq_out_type;
dbgi : in l3_debug_in_type;
dbgo : out l3_debug_out_type;
gclk : in std_ulogic
);
end component;
component leon3s2x
generic (
hindex : integer := 0;
fabtech : integer range 0 to NTECH := DEFFABTECH;
memtech : integer range 0 to NTECH := DEFMEMTECH;
nwindows : integer range 2 to 32 := 8;
dsu : integer range 0 to 1 := 0;
fpu : integer range 0 to 31 := 0;
v8 : integer range 0 to 63 := 0;
cp : integer range 0 to 1 := 0;
mac : integer range 0 to 1 := 0;
pclow : integer range 0 to 2 := 2;
notag : integer range 0 to 1 := 0;
nwp : integer range 0 to 4 := 0;
icen : integer range 0 to 1 := 0;
irepl : integer range 0 to 2 := 2;
isets : integer range 1 to 4 := 1;
ilinesize : integer range 4 to 8 := 4;
isetsize : integer range 1 to 256 := 1;
isetlock : integer range 0 to 1 := 0;
dcen : integer range 0 to 1 := 0;
drepl : integer range 0 to 2 := 2;
dsets : integer range 1 to 4 := 1;
dlinesize : integer range 4 to 8 := 4;
dsetsize : integer range 1 to 256 := 1;
dsetlock : integer range 0 to 1 := 0;
dsnoop : integer range 0 to 6 := 0;
ilram : integer range 0 to 1 := 0;
ilramsize : integer range 1 to 512 := 1;
ilramstart : integer range 0 to 255 := 16#8e#;
dlram : integer range 0 to 1 := 0;
dlramsize : integer range 1 to 512 := 1;
dlramstart : integer range 0 to 255 := 16#8f#;
mmuen : integer range 0 to 1 := 0;
itlbnum : integer range 2 to 64 := 8;
dtlbnum : integer range 2 to 64 := 8;
tlb_type : integer range 0 to 3 := 1;
tlb_rep : integer range 0 to 1 := 0;
lddel : integer range 1 to 2 := 2;
disas : integer range 0 to 2 := 0;
tbuf : integer range 0 to 64 := 0;
pwd : integer range 0 to 2 := 2; -- power-down
svt : integer range 0 to 1 := 1; -- single vector trapping
rstaddr : integer := 0;
smp : integer range 0 to 15 := 0; -- support SMP systems
cached : integer := 0; -- cacheability table
clk2x : integer := 1;
scantest : integer := 0
);
port (
clk : in std_ulogic;
gclk2 : in std_ulogic; -- gated clock
clk2 : in std_ulogic; -- continuous clock
rstn : in std_ulogic;
ahbi : in ahb_mst_in_type;
ahbo : out ahb_mst_out_type;
ahbsi : in ahb_slv_in_type;
ahbso : in ahb_slv_out_vector;
irqi : in l3_irq_in_type;
irqo : out l3_irq_out_type;
dbgi : in l3_debug_in_type;
dbgo : out l3_debug_out_type;
clken : in std_ulogic
);
end component;
-- GRFPU interface
type fp_rf_in_type is record
rd1addr : std_logic_vector(3 downto 0); -- read address 1
rd2addr : std_logic_vector(3 downto 0); -- read address 2
wraddr : std_logic_vector(3 downto 0); -- write address
wrdata : std_logic_vector(31 downto 0); -- write data
ren1 : std_ulogic; -- read 1 enable
ren2 : std_ulogic; -- read 2 enable
wren : std_ulogic; -- write enable
end record;
type fp_rf_out_type is record
data1 : std_logic_vector(31 downto 0); -- read data 1
data2 : std_logic_vector(31 downto 0); -- read data 2
end record;
type fpc_pipeline_control_type is record
pc : std_logic_vector(31 downto 0);
inst : std_logic_vector(31 downto 0);
cnt : std_logic_vector(1 downto 0);
trap : std_ulogic;
annul : std_ulogic;
pv : std_ulogic;
end record;
type fpc_debug_in_type is record
enable : std_ulogic;
write : std_ulogic;
fsr : std_ulogic; -- FSR access
addr : std_logic_vector(4 downto 0);
data : std_logic_vector(31 downto 0);
end record;
type fpc_debug_out_type is record
data : std_logic_vector(31 downto 0);
end record;
type fpc_in_type is record
flush : std_ulogic; -- pipeline flush
exack : std_ulogic; -- FP exception acknowledge
a_rs1 : std_logic_vector(4 downto 0);
d : fpc_pipeline_control_type;
a : fpc_pipeline_control_type;
e : fpc_pipeline_control_type;
m : fpc_pipeline_control_type;
x : fpc_pipeline_control_type;
lddata : std_logic_vector(31 downto 0); -- load data
dbg : fpc_debug_in_type; -- debug signals
end record;
type fpc_out_type is record
data : std_logic_vector(31 downto 0); -- store data
exc : std_logic; -- FP exception
cc : std_logic_vector(1 downto 0); -- FP condition codes
ccv : std_ulogic; -- FP condition codes valid
ldlock : std_logic; -- FP pipeline hold
holdn : std_ulogic;
dbg : fpc_debug_out_type; -- FP debug signals
end record;
type grfpu_in_type is record
start : std_logic;
nonstd : std_logic;
flop : std_logic_vector(8 downto 0);
op1 : std_logic_vector(63 downto 0);
op2 : std_logic_vector(63 downto 0);
opid : std_logic_vector(7 downto 0);
flush : std_logic;
flushid : std_logic_vector(5 downto 0);
rndmode : std_logic_vector(1 downto 0);
req : std_logic;
end record;
type grfpu_out_type is record
res : std_logic_vector(63 downto 0);
exc : std_logic_vector(5 downto 0);
allow : std_logic_vector(2 downto 0);
rdy : std_logic;
cc : std_logic_vector(1 downto 0);
idout : std_logic_vector(7 downto 0);
end record;
type grfpu_out_vector_type is array (integer range 0 to 7) of grfpu_out_type;
type grfpu_in_vector_type is array (integer range 0 to 7) of grfpu_in_type;
component grfpushwx
generic (mul : integer := 0;
nshare : integer range 0 to 8 := 0);
port(
clk : in std_logic;
reset : in std_logic;
fpvi : in grfpu_in_vector_type;
fpvo : out grfpu_out_vector_type
);
end component;
component grfpwxsh
generic (tech : integer range 0 to NTECH := 0;
pclow : integer range 0 to 2 := 2;
dsu : integer range 0 to 1 := 0;
disas : integer range 0 to 2 := 0;
id : integer range 0 to 7 := 0);
port (
rst : in std_ulogic; -- Reset
clk : in std_ulogic;
holdn : in std_ulogic; -- pipeline hold
cpi : in fpc_in_type;
cpo : out fpc_out_type;
fpui : out grfpu_in_type;
fpuo : in grfpu_out_type
);
end component;
component leon3sh
generic (
hindex : integer := 0;
fabtech : integer range 0 to NTECH := DEFFABTECH;
memtech : integer range 0 to NTECH := DEFMEMTECH;
nwindows : integer range 2 to 32 := 8;
dsu : integer range 0 to 1 := 0;
fpu : integer range 0 to 31 := 0;
v8 : integer range 0 to 63 := 0;
cp : integer range 0 to 1 := 0;
mac : integer range 0 to 1 := 0;
pclow : integer range 0 to 2 := 2;
notag : integer range 0 to 1 := 0;
nwp : integer range 0 to 4 := 0;
icen : integer range 0 to 1 := 0;
irepl : integer range 0 to 2 := 2;
isets : integer range 1 to 4 := 1;
ilinesize : integer range 4 to 8 := 4;
isetsize : integer range 1 to 256 := 1;
isetlock : integer range 0 to 1 := 0;
dcen : integer range 0 to 1 := 0;
drepl : integer range 0 to 2 := 2;
dsets : integer range 1 to 4 := 1;
dlinesize : integer range 4 to 8 := 4;
dsetsize : integer range 1 to 256 := 1;
dsetlock : integer range 0 to 1 := 0;
dsnoop : integer range 0 to 6 := 0;
ilram : integer range 0 to 1 := 0;
ilramsize : integer range 1 to 512 := 1;
ilramstart : integer range 0 to 255 := 16#8e#;
dlram : integer range 0 to 1 := 0;
dlramsize : integer range 1 to 512 := 1;
dlramstart : integer range 0 to 255 := 16#8f#;
mmuen : integer range 0 to 1 := 0;
itlbnum : integer range 2 to 64 := 8;
dtlbnum : integer range 2 to 64 := 8;
tlb_type : integer range 0 to 3 := 1;
tlb_rep : integer range 0 to 1 := 0;
lddel : integer range 1 to 2 := 2;
disas : integer range 0 to 2 := 0;
tbuf : integer range 0 to 64 := 0;
pwd : integer range 0 to 2 := 2; -- power-down
svt : integer range 0 to 1 := 1; -- single vector trapping
rstaddr : integer := 0;
smp : integer range 0 to 15 := 0; -- support SMP systems
cached : integer := 0; -- cacheability table
scantest : integer := 0
);
port (
clk : in std_ulogic;
rstn : in std_ulogic;
ahbi : in ahb_mst_in_type;
ahbo : out ahb_mst_out_type;
ahbsi : in ahb_slv_in_type;
ahbso : in ahb_slv_out_vector;
irqi : in l3_irq_in_type;
irqo : out l3_irq_out_type;
dbgi : in l3_debug_in_type;
dbgo : out l3_debug_out_type;
fpui : out grfpu_in_type;
fpuo : in grfpu_out_type
);
end component;
type dsu_in_type is record
enable : std_ulogic;
break : std_ulogic;
end record;
type dsu_out_type is record
active : std_ulogic;
tstop : std_ulogic;
pwd : std_logic_vector(15 downto 0);
end record;
component dsu3
generic (
hindex : integer := 0;
haddr : integer := 16#900#;
hmask : integer := 16#f00#;
ncpu : integer := 1;
tbits : integer := 30; -- timer bits (instruction trace time tag)
tech : integer := DEFMEMTECH;
irq : integer := 0;
kbytes : integer := 0
);
port (
rst : in std_ulogic;
clk : in std_ulogic;
ahbmi : in ahb_mst_in_type;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
dbgi : in l3_debug_out_vector(0 to NCPU-1);
dbgo : out l3_debug_in_vector(0 to NCPU-1);
dsui : in dsu_in_type;
dsuo : out dsu_out_type
);
end component;
component dsu3_2x
generic (
hindex : integer := 0;
haddr : integer := 16#900#;
hmask : integer := 16#f00#;
ncpu : integer := 1;
tbits : integer := 30; -- timer bits (instruction trace time tag)
tech : integer := DEFMEMTECH;
irq : integer := 0;
kbytes : integer := 0
);
port (
rst : in std_ulogic;
hclk : in std_ulogic;
cpuclk : in std_ulogic;
ahbmi : in ahb_mst_in_type;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
dbgi : in l3_debug_out_vector(0 to NCPU-1);
dbgo : out l3_debug_in_vector(0 to NCPU-1);
dsui : in dsu_in_type;
dsuo : out dsu_out_type;
hclken : in std_ulogic
);
end component;
component dsu3x
generic (
hindex : integer := 0;
haddr : integer := 16#900#;
hmask : integer := 16#f00#;
ncpu : integer := 1;
tbits : integer := 30; -- timer bits (instruction trace time tag)
tech : integer := DEFMEMTECH;
irq : integer := 0;
kbytes : integer := 0;
clk2x : integer range 0 to 1 := 0
);
port (
rst : in std_ulogic;
hclk : in std_ulogic;
cpuclk : in std_ulogic;
ahbmi : in ahb_mst_in_type;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
dbgi : in l3_debug_out_vector(0 to NCPU-1);
dbgo : out l3_debug_in_vector(0 to NCPU-1);
dsui : in dsu_in_type;
dsuo : out dsu_out_type;
hclken : in std_ulogic
);
end component;
type irq_in_vector is array (Natural range <> ) of l3_irq_in_type;
type irq_out_vector is array (Natural range <> ) of l3_irq_out_type;
component irqmp
generic (
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#fff#;
ncpu : integer := 1;
cmask : integer := 16#0001#
);
port (
rst : in std_ulogic;
clk : in std_ulogic;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
irqi : in irq_out_vector(0 to ncpu-1);
irqo : out irq_in_vector(0 to ncpu-1)
);
end component;
component irqmp2x
generic (
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#fff#;
ncpu : integer := 1;
cmask : integer := 16#0001#;
clkfact : integer := 2
);
port (
rst : in std_ulogic;
hclk : in std_ulogic;
cpuclk : in std_ulogic;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
irqi : in irq_out_vector(0 to ncpu-1);
irqo : out irq_in_vector(0 to ncpu-1);
hclken : in std_ulogic
);
end component;
component leon3ftsh
generic (
hindex : integer := 0;
fabtech : integer range 0 to NTECH := DEFFABTECH;
memtech : integer range 0 to NTECH := DEFMEMTECH;
nwindows : integer range 2 to 32 := 8;
dsu : integer range 0 to 1 := 0;
fpu : integer range 0 to 31 := 0;
v8 : integer range 0 to 63 := 0;
cp : integer range 0 to 1 := 0;
mac : integer range 0 to 1 := 0;
pclow : integer range 0 to 2 := 2;
notag : integer range 0 to 1 := 0;
nwp : integer range 0 to 4 := 0;
icen : integer range 0 to 1 := 0;
irepl : integer range 0 to 2 := 2;
isets : integer range 1 to 4 := 1;
ilinesize : integer range 4 to 8 := 4;
isetsize : integer range 1 to 256 := 1;
isetlock : integer range 0 to 1 := 0;
dcen : integer range 0 to 1 := 0;
drepl : integer range 0 to 2 := 2;
dsets : integer range 1 to 4 := 1;
dlinesize : integer range 4 to 8 := 4;
dsetsize : integer range 1 to 256 := 1;
dsetlock : integer range 0 to 1 := 0;
dsnoop : integer range 0 to 6 := 0;
ilram : integer range 0 to 1 := 0;
ilramsize : integer range 1 to 512 := 1;
ilramstart : integer range 0 to 255 := 16#8e#;
dlram : integer range 0 to 1 := 0;
dlramsize : integer range 1 to 512 := 1;
dlramstart : integer range 0 to 255 := 16#8f#;
mmuen : integer range 0 to 1 := 0;
itlbnum : integer range 2 to 64 := 8;
dtlbnum : integer range 2 to 64 := 8;
tlb_type : integer range 0 to 3 := 1;
tlb_rep : integer range 0 to 1 := 0;
lddel : integer range 1 to 2 := 2;
disas : integer range 0 to 2 := 0;
tbuf : integer range 0 to 64 := 0;
pwd : integer range 0 to 2 := 2; -- power-down
svt : integer range 0 to 1 := 1; -- single vector trapping
rstaddr : integer := 0;
smp : integer range 0 to 15 := 0; -- support SMP systems
iuft : integer range 0 to 4 := 0;
fpft : integer range 0 to 4 := 0;
cmft : integer range 0 to 1 := 0;
iuinj : integer := 0;
ceinj : integer range 0 to 3 := 0;
cached : integer := 0;
netlist : integer := 0;
scantest : integer := 0
);
port (
clk : in std_ulogic; -- free-running clock
rstn : in std_ulogic;
ahbi : in ahb_mst_in_type;
ahbo : out ahb_mst_out_type;
ahbsi : in ahb_slv_in_type;
ahbso : in ahb_slv_out_vector;
irqi : in l3_irq_in_type;
irqo : out l3_irq_out_type;
dbgi : in l3_debug_in_type;
dbgo : out l3_debug_out_type;
gclk : in std_ulogic; -- gated clock
fpui : out grfpu_in_type;
fpuo : in grfpu_out_type
);
end component;
end;
| mit | 4b5a5bc624e31931bc13a97123ef77b7 | 0.526423 | 3.54354 | false | false | false | false |
franz/pocl | examples/accel/rtl/simulation/vhdl/mul_dsp48_sim.vhdl | 2 | 3,450 | -- Copyright (c) 2019 Tampere University.
--
-- This file is part of TTA-Based Codesign Environment (TCE).
--
-- Permission is hereby granted, free of charge, to any person obtaining a
-- copy of this software and associated documentation files (the "Software"),
-- to deal in the Software without restriction, including without limitation
-- the rights to use, copy, modify, merge, publish, distribute, sublicense,
-- and/or sell copies of the Software, and to permit persons to whom the
-- Software is furnished to do so, subject to the following conditions:
--
-- The above copyright notice and this permission notice shall be included in
-- all copies or substantial portions of the Software.
--
-- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-- AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
-- FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
-- DEALINGS IN THE SOFTWARE.
-------------------------------------------------------------------------------
-- Title : Simulation model for non-pipelined multiplier
-------------------------------------------------------------------------------
-- File : mul_dsp_comb_sim.vhdl
-- Author : Kati Tervo
-- Company :
-- Created : 2019-03-10
-- Last update: 2019-03-10
-- Platform :
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2019-03-10 1.0 katte Created
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity mul_dsp48 is
generic (
latency_g : integer
); port(
clk : in std_logic;
rstx : in std_logic;
glock_in : in std_logic;
load_in : in std_logic;
operand_a_in : in std_logic_vector(32-1 downto 0);
operand_b_in : in std_logic_vector(32-1 downto 0);
operand_c_in : in std_logic_vector(32-1 downto 0);
result_out : out std_logic_vector(32-1 downto 0)
);
end mul_dsp48;
architecture rtl of mul_dsp48 is
signal mul_result : std_logic_vector(64 - 1 downto 0);
signal result : std_logic_vector(32 - 1 downto 0);
type result_arr is array (latency_g downto 0)
of std_logic_vector(32-1 downto 0);
signal result_r : result_arr;
begin
mul_result <= std_logic_vector(unsigned(operand_a_in)
* unsigned(operand_b_in));
result <= std_logic_vector(unsigned(mul_result(32-1 downto 0))
+ unsigned(operand_c_in));
comb: if latency_g = 0 generate
result_out <= result;
end generate;
sync: if latency_g > 0 generate
operation_sync : process(clk)
begin
if rising_edge(clk) then
if rstx = '0' then
result_r <= (others => (others => '0'));
elsif glock_in = '0' then
if load_in = '1' then
result_r(0) <= result;
end if;
result_r(result_r'high downto 1) <= result_r(result_r'high-1 downto 0);
end if;
end if;
end process;
result_out <= result_r(latency_g-1);
end generate;
end rtl;
| mit | 684b967fb7812cb7b042163e98469e32 | 0.587536 | 4.011628 | false | false | false | false |
impedimentToProgress/UCI-BlueChip | AttackFiles/Attacks/privEsc/lib/gleichmann/sim/phy_ext.vhd | 2 | 7,903 | --------------------------------------------------------------------------------
-- Project: LEON-ARC
-- Entity: phy_ext
-- Architecture(s): behav
-- Author: [email protected]
-- Company: Gleichmann Electronics
--
-- Description:
-- This file is based upon the PHY simulation model by Gaisler Research,
-- which is part of the GNU GPL-licensed GRLIB. For details on the GRLIB, go
-- to www.gaisler.com.
--
-- The original design has been extended in respect to logging signals.
--
--------------------------------------------------------------------------------
--
-- Gaisler original comment:
-- Entity: phy
-- File: phy.vhd
-- Description: Simulation model of the Intel LXT971A Ethernet PHY
-- Only the MII interface is implemented.
-- Stimuli is read from a file "indata" and response is
-- written to "outdata"
-- Author: Marko Isomaki
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use std.textio.all;
library work;
use work.txt_util.all;
entity phy_ext is
generic (
infile_name : string := "indata";
outfile_name : string := "outdata";
logfile_name : string := "logfile";
win_size : natural := 3); -- number of packages that form a window
port (
resetn : in std_logic;
led_cfg : in std_logic_vector(2 downto 0);
log_en : in std_logic := '1';
cycle_num : in integer;
mdio : inout std_logic;
tx_clk : out std_logic;
rx_clk : out std_logic;
rxd : out std_logic_vector(3 downto 0);
rx_dv : out std_logic;
rx_er : out std_logic;
rx_col : out std_logic;
rx_crs : out std_logic;
txd : in std_logic_vector(3 downto 0);
tx_en : in std_logic;
tx_er : in std_logic;
mdc : in std_logic);
end entity;
architecture behav of phy_ext is
--type declarations
type state_type is (base10h, base10f, base100h, base100f);
type reg_type is
record
crs : std_logic;
tx_count : integer range 0 to 1;
tx_output : std_logic_vector(3 downto 0);
rx_dv : std_logic;
rx_er : std_logic;
prev_txd : std_logic;
state : state_type;
new_data : std_logic;
new_txd : std_logic;
counter : integer range 0 to 400000;
pcount : integer range 0 to 64;
end record;
--signal declarations
signal clk_fast : std_logic := '0';
signal clk_slow : std_logic := '0';
signal temp_clk : std_logic;
signal r, rin : reg_type;
file indata : text open read_mode is infile_name;
file outdata : text open write_mode is outfile_name;
-- logfile contains read and write accesses
file logfile : text open write_mode is logfile_name;
shared variable logline : line;
shared variable logstring : string(1 to 80);
signal temp_col : std_logic;
begin
--clock generation
clk_fast <= not clk_fast after 20 ns;
clk_slow <= not clk_slow after 200 ns;
temp_clk <= clk_fast when r.state = base100h or r.state = base100f else
clk_slow;
rx_clk <= temp_clk;
tx_clk <= temp_clk;
--unused signals
mdio <= 'Z';
comb : process(r, txd, tx_en, tx_er)
variable v : reg_type;
variable col : std_logic;
begin
v := r;
v.prev_txd := r.new_txd;
v.crs := '0';
v.new_data := '0';
--transmitter part
v.new_txd := tx_en;
if tx_er = '1' then
v.tx_output := X"F";
elsif tx_en = '1' then
v.tx_output := txd;
end if;
if (r.state = base10h or r.state = base100h) and tx_en = '1' then
v.crs := '1';
end if;
--receiver part
if r.counter > 0 then
v.counter := r.counter-1;
end if;
v.rx_dv := '0';
v.rx_er := '0';
if r.counter = 0 then
if(tx_en = '0' or (r.new_txd = '0' and tx_en = '1') or
r.state = base100f or r.state = base10f) then
v.rx_dv := '1';
v.new_data := '1';
v.crs := '1';
end if;
end if;
--control signals
if (r.state = base10h or r.state = base100h) and
tx_en = '1' and r.rx_dv = '1' then
col := '1';
else
col := '0';
end if;
--output
rx_col <= col;
temp_col <= col;
rx_crs <= r.crs;
rx_dv <= r.rx_dv;
rx_er <= r.rx_er;
--registers
rin <= v;
end process comb;
log_start : process is
begin
if log_en = '1' then
print(logfile, "#");
print(logfile, "# RX_TRANSFER CYCLE_NUMBER RX_CLK RX_DV RX_ER COL CRS RXD MDC MDIO");
print(logfile, "# TX_TRANSFER CYCLE_NUMBER TX_CLK TX_EN TX_ER TXD");
print(logfile, "#");
end if;
wait;
end process;
regs : process(resetn, temp_clk)
variable textline : line;
variable wline : line;
variable din_tmp : bit_vector(3 downto 0);
variable din_ok : boolean;
begin
if resetn = '0' then
case led_cfg is
when "000" => r.state <= base10h;
when "001" => r.state <= base10f;
when "010" => r.state <= base100h;
when "011" => r.state <= base100f;
when others => r.state <= base10h;
end case;
r.crs <= '0';
r.tx_count <= 0;
r.new_txd <= '0';
r.rx_dv <= '0';
r.rx_er <= '0';
r.new_data <= '0';
r.counter <= 2000;
r.pcount <= 0;
elsif rising_edge(temp_clk) then
r <= rin;
if rin.new_data = '1' and not endfile(indata) then
readline(indata, textline);
read(textline, din_tmp, din_ok);
if din_ok then
rxd <= to_stdlogicvector(din_tmp);
-- write RX data to logfile
if log_en = '1' then
print(logfile,
string'("RX ") &
str(cycle_num) & " " & -- current clock cycle number
str(temp_clk) & " " & -- equivalent to rx_clk
str(r.rx_dv) & " " & -- receive data valid
str(r.rx_er) & " " & -- receive error
str(temp_col) & " " & -- equivalent to rx_col
str(r.crs) & " " & -- receive carrier sense
hstr(to_stdlogicvector(din_tmp)) & " " & -- receive data
str(mdc) & " " &
str(mdio));
end if;
else
report "new-packet" severity note;
r.pcount <= rin.pcount + 1;
if rin.pcount + 1 /= win_size then
if r.state = base100h or r.state = base100f then
r.counter <= 500;
else
r.counter <= 50;
end if;
else
r.counter <= 1000;
r.pcount <= 0;
end if;
rxd <= (others => 'U');
r.rx_dv <= '0';
r.crs <= '0';
end if;
else
rxd <= (others => 'U');
r.rx_dv <= '0';
r.crs <= '0';
end if;
if rin.new_txd = '1' then
write(wline, to_bitvector(rin.tx_output), left, 4);
writeline(outdata, wline);
-- write TX data to logfile
if log_en = '1' then
print(logfile,
string'("TX ") &
str(cycle_num) & " " & -- current clock cycle number
str(temp_clk) & " " & -- equivalent to tx_clk
str(tx_en) & " " & -- always enabled here
str(tx_er) & " " & -- transmit error
hstr(txd)); -- transmit data
end if;
if r.state = base10h or r.state = base100h then
r.crs <= '1';
end if;
elsif rin.prev_txd = '1' then
write(wline, string'("end"), left, 3);
writeline(outdata, wline);
end if;
end if;
end process regs;
end architecture;
| mit | 34a0b5ed6420b69b2928eb87badf3497 | 0.495888 | 3.431611 | false | false | false | false |
cafe-alpha/wascafe | v13/wasca_10m08sc_20191205_abus_divide/wasca/synthesis/submodules/abus_demux.vhd | 2 | 40,009 | -- abus_demux.vhd
library IEEE;
use IEEE.numeric_std.all;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity abus_demux is
port (
-- -- External signals used for simulation vvv
-- sim_test1 : out std_logic_vector( 7 downto 0) := (others => '0');
-- sim_test2 : out std_logic_vector( 7 downto 0) := (others => '0');
-- abus_cspulse_trail_dbg : out std_logic_vector(11 downto 0) := (others => '0');
-- abus_read_trail_dbg : out std_logic_vector(11 downto 0) := (others => '0');
-- abus_writeneg0_trail_dbg : out std_logic_vector(11 downto 0) := (others => '0');
-- abus_writeneg1_trail_dbg : out std_logic_vector(11 downto 0) := (others => '0');
-- abus_addresslatched_dbg : out std_logic_vector(23 downto 0) := (others => '0');
-- sim_noise : in std_logic := '0';
-- -- External signals used for simulation ^^^
clock : in std_logic := '0'; -- clock.clk
-- A-Bus interface
abus_address : in std_logic_vector( 8 downto 0) := (others => '0'); -- abus.address
abus_addressdata : inout std_logic_vector(15 downto 0) := (others => '0'); -- abus.addressdata
abus_chipselect : in std_logic_vector( 2 downto 0) := (others => '0'); -- .chipselect
abus_read : in std_logic := '0'; -- .read
abus_write : in std_logic_vector( 1 downto 0) := (others => '0'); -- .write
abus_waitrequest : out std_logic := '1'; -- .waitrequest
abus_interrupt : out std_logic := '0'; -- .interrupt
abus_direction : out std_logic := '0'; -- .direction
abus_muxing : out std_logic_vector( 1 downto 0) := "01"; -- .muxing
abus_disable_out : out std_logic := '0'; -- .disableout
saturn_reset : in std_logic := '0'; -- .saturn_reset
-- Demuxed signals
-- Note : naming is Saturn-centered, ie readdata = read from Saturn = output from A-Bus side = input from demux side
demux_writeaddress : out std_logic_vector(27 downto 0) := (others => '0');
demux_writedata : out std_logic_vector(15 downto 0) := (others => '0');
demux_writepulse : out std_logic := '0';
demux_write_byteenable : out std_logic_vector( 1 downto 0) := (others => '0');
demux_readaddress : out std_logic_vector(27 downto 0) := (others => '0');
demux_readdata : in std_logic_vector(15 downto 0) := (others => '0');
demux_readpulse : out std_logic := '0';
demux_readdatavalid : in std_logic := '0';
-- Avalon
avalon_nios_read : in std_logic := '0'; -- avalon_master.read
avalon_nios_write : in std_logic := '0'; -- .write
avalon_nios_waitrequest : out std_logic := '0'; -- .waitrequest
avalon_nios_address : in std_logic_vector( 7 downto 0) := (others => '0'); -- .address
avalon_nios_writedata : in std_logic_vector(31 downto 0) := (others => '0'); -- .writedata
avalon_nios_burstcount : in std_logic; -- .burstcount
avalon_nios_readdata : out std_logic_vector(31 downto 0) := (others => '0'); -- .readdata
avalon_nios_readdatavalid : out std_logic := '0'; -- .readdatavalid
reset : in std_logic := '0' -- reset.reset
);
end entity abus_demux;
architecture rtl of abus_demux is
-- Trail size, same for all internal signals.
-- As Quartus won't synthetize unused signals, large enough size is defined
-- so that source readability shall be a bit improved.
constant ABUS_TRAILS_SIZE : integer := 12;
signal abus_address_ms : std_logic_vector( 8 downto 0) := (others => '0'); -- abus.address
signal abus_address_buf : std_logic_vector( 8 downto 0) := (others => '0'); -- abus.address
signal abus_addressdata_ms : std_logic_vector(15 downto 0) := (others => '0'); -- .data
signal abus_addressdata_buf : std_logic_vector(15 downto 0) := (others => '0'); -- .data
signal abus_chipselect_p1 : std_logic_vector( 2 downto 0) := (others => '0'); -- .chipselect
signal abus_chipselect_p2 : std_logic_vector( 2 downto 0) := (others => '0'); -- .chipselect
signal abus_chipselect_buf2 : std_logic_vector( 2 downto 0) := (others => '0'); -- .chipselect
signal abus_read_ms : std_logic := '0'; -- .read
signal abus_write_ms : std_logic_vector( 1 downto 0) := (others => '0'); -- .write
signal abus_writeneg_ms : std_logic_vector( 1 downto 0) := (others => '0'); -- .write
signal abus_write_buf : std_logic_vector( 1 downto 0) := (others => '0'); -- .write
signal abus_writedata_buf : std_logic_vector(15 downto 0) := (others => '0'); -- .data
signal abus_read_trail : std_logic_vector((ABUS_TRAILS_SIZE-1) downto 0) := (others => '0'); -- RD
signal abus_write_buf2 : std_logic_vector( 1 downto 0) := (others => '0'); -- .write
signal abus_writeneg0_trail : std_logic_vector((ABUS_TRAILS_SIZE-1) downto 0) := (others => '0'); -- WR0
signal abus_writeneg1_trail : std_logic_vector((ABUS_TRAILS_SIZE-1) downto 0) := (others => '0'); -- WR1
signal abus_trcntr : std_logic_vector( 3 downto 0) := (others => '0'); -- Transaction state counter
signal abus_read_pulse : std_logic := '0'; -- .read
signal abus_reading : std_logic := '0'; -- .read
signal abus_write_pulse : std_logic := '0'; -- .write
signal abus_writing : std_logic := '0'; -- .write
-- Trails to properly delay write pipeline
signal abus_write_pulse_trail : std_logic_vector((ABUS_TRAILS_SIZE-1) downto 0) := (others => '0'); -- write
signal abus_writing_trail : std_logic_vector((ABUS_TRAILS_SIZE-1) downto 0) := (others => '0'); -- write
-- Buffers to hold avalon parameters during transaction
signal avalon_writedata_buff : std_logic_vector(15 downto 0) := (others => '0');
signal avalon_byteenable_buff : std_logic_vector( 1 downto 0) := (others => '0');
signal avalon_write_buff : std_logic := '0';
signal abus_read_pulse_dmy : std_logic := '0'; -- .read
signal abus_write_pulse_dmy : std_logic_vector( 1 downto 0) := (others => '0'); -- .write
signal abus_chipselect_pulse : std_logic_vector( 2 downto 0) := (others => '0'); -- .chipselect
signal abus_read_pulse_off : std_logic := '0'; -- .read
signal abus_write_pulse_off : std_logic_vector( 1 downto 0) := (others => '0'); -- .write
signal abus_chipselect_pulse_off : std_logic_vector( 2 downto 0) := (others => '0'); -- .chipselect
signal abus_anypulse : std_logic := '0';
signal abus_anypulse2 : std_logic := '0';
signal abus_anypulse3 : std_logic := '0';
signal abus_anypulse_off : std_logic := '0';
signal abus_cspulse_trail : std_logic_vector((ABUS_TRAILS_SIZE-1) downto 0) := (others => '0');
signal abus_cspulse_off : std_logic := '0';
signal abus_chipselect_latched : std_logic_vector( 2 downto 0) := (others => '1'); -- abus.chipselect
signal abus_read_latched : std_logic := '0'; -- .read
signal abus_write_latched : std_logic_vector( 1 downto 0) := (others => '0'); -- .write
signal abus_address_latched : std_logic_vector(23 downto 0) := (others => '0'); -- .address
signal abus_direction_internal : std_logic := '0'; --high-z
signal abus_muxing_internal : std_logic_vector( 1 downto 0) := "01"; -- sample address
signal abus_data_out : std_logic_vector(15 downto 0) := (others => '0');
signal abus_data_in : std_logic_vector(15 downto 0) := (others => '0');
signal abus_waitrequest_read1 : std_logic := '0';
signal abus_waitrequest_read2 : std_logic := '0';
signal abus_waitrequest_write1 : std_logic := '0';
signal abus_waitrequest_write2 : std_logic := '0';
signal abus_waitrequest_read_off : std_logic := '0';
signal abus_waitrequest_write_off : std_logic := '0';
-- Access test stuff, added 2019/11/04 vvv
signal rdwr_access_buff : std_logic_vector(127 downto 0) := x"CAFE0304050607080910111213141516";
-- Access test stuff, added 2019/11/04 ^^^
-- External signals used for simulation vvv
signal sim_test1_internal : std_logic_vector( 7 downto 0) := x"CA";
signal sim_test2_internal : std_logic_vector( 7 downto 0) := x"FE";
-- External signals used for simulation ^^^
-- For Rd/Wr access debug
signal rd_access_cntr : std_logic_vector( 7 downto 0) := x"01";
signal wr_access_cntr : std_logic_vector( 7 downto 0) := x"01";
signal last_wr_data : std_logic_vector(15 downto 0) := x"5678";
signal REG_PCNTR : std_logic_vector(15 downto 0) := (others => '0');
signal REG_STATUS : std_logic_vector(15 downto 0) := (others => '0');
signal REG_MODE : std_logic_vector(15 downto 0) := (others => '0');
signal REG_HWVER : std_logic_vector(15 downto 0) := X"0002";
signal REG_SWVER : std_logic_vector(15 downto 0) := (others => '0');
TYPE transaction_dir IS (DIR_NONE,DIR_WRITE,DIR_READ);
SIGNAL my_little_transaction_dir : transaction_dir := DIR_NONE;
TYPE wasca_mode_type IS (MODE_INIT,
MODE_POWER_MEMORY_05M, MODE_POWER_MEMORY_1M, MODE_POWER_MEMORY_2M, MODE_POWER_MEMORY_4M,
MODE_RAM_1M, MODE_RAM_4M,
MODE_ROM_KOF95,
MODE_ROM_ULTRAMAN,
MODE_BOOT);
SIGNAL wasca_mode : wasca_mode_type := MODE_INIT;
begin
--ignoring functioncode, timing and addressstrobe for now
--abus transactions are async, so first we must latch incoming signals
--to get rid of metastability
process (clock)
begin
if rising_edge(clock) then
--1st stage
abus_address_ms <= abus_address;
abus_addressdata_ms <= abus_addressdata;
abus_chipselect_p1 <= abus_chipselect;
abus_read_ms <= abus_read;
abus_write_ms <= abus_write;
abus_writeneg_ms <= not abus_write;
--2nd stage
abus_address_buf <= abus_address_ms;
abus_addressdata_buf <= abus_addressdata_ms;
abus_chipselect_p2 <= abus_chipselect_p1;
abus_read_trail(0) <= abus_read_ms;
abus_write_buf <= abus_write_ms;
abus_writeneg0_trail(0) <= abus_writeneg_ms(0);
abus_writeneg1_trail(0) <= abus_writeneg_ms(1);
end if;
end process;
--excluding metastability protection is a bad behavior
--but it looks like we're out of more options to optimize read pipeline
--abus_read_ms <= abus_read;
--abus_read_buf <= abus_read_ms;
--abus read/write latch
process (clock)
begin
if rising_edge(clock) then
abus_write_buf2 <= abus_write_buf;
abus_chipselect_buf2 <= abus_chipselect_p2;
abus_anypulse2 <= abus_anypulse;
abus_anypulse3 <= abus_anypulse2;
for i in 0 to (ABUS_TRAILS_SIZE-2) loop
abus_cspulse_trail (i+1) <= abus_cspulse_trail (i);
abus_read_trail (i+1) <= abus_read_trail (i);
abus_writeneg0_trail(i+1) <= abus_writeneg0_trail(i);
abus_writeneg1_trail(i+1) <= abus_writeneg1_trail(i);
end loop;
end if;
end process;
--abus write/read pulse is a falling edge since read and write signals are negative polarity
abus_write_pulse_dmy <= abus_write_buf2 and not abus_write_buf;
abus_read_pulse_dmy <= abus_read_trail(1) and not abus_read_trail(0);
--abus_chipselect_pulse <= abus_chipselect_buf2 and not abus_chipselect_p2;
abus_chipselect_pulse <= abus_chipselect_p2 and not abus_chipselect_p1;
abus_write_pulse_off <= abus_write_buf and not abus_write_buf2;
abus_read_pulse_off <= abus_read_trail(0) and not abus_read_trail(1);
abus_chipselect_pulse_off <= abus_chipselect_p2 and not abus_chipselect_buf2;
abus_anypulse <= abus_write_pulse_dmy(0)
or abus_write_pulse_dmy(1)
or abus_read_pulse_dmy
or abus_chipselect_pulse(0)
or abus_chipselect_pulse(1)
or abus_chipselect_pulse(2);
abus_anypulse_off <= abus_write_pulse_off(0)
or abus_write_pulse_off(1)
or abus_read_pulse_off
or abus_chipselect_pulse_off(0)
or abus_chipselect_pulse_off(1)
or abus_chipselect_pulse_off(2);
abus_cspulse_trail(0) <= abus_chipselect_pulse(0)
or abus_chipselect_pulse(1)
or abus_chipselect_pulse(2);
abus_cspulse_off <= abus_chipselect_pulse_off(0)
or abus_chipselect_pulse_off(1)
or abus_chipselect_pulse_off(2);
-- Transaction counter update
--
-- Concept
-- | - It is assumed that CS0~1 lines become active last and that RD/WR/ADDR/DATA lines are setup before that moment.
-- | -> should need to measure that for real with OLS !
-- | -> Timeline is as follow :
-- | abus_chipselect_p2 (two clocks before)
-- | abus_chipselect_p1 (one clock before)
-- | abus_chipselect (latest)
-- | - Let's wait for one MAX 10 internal (116 MHz) clock after CS is active and start sampling other signals.
-- | - During write transaction (write from Saturn to cartridge), data is demuxed during two clocks : this may not be needed but seems safer in a first try.
--
--
-- COMMON
-- | - Retrieve read/write type and latch full address
--
-- CARTRIDGE READ FROM SATURN
-- | - If register, process it immediately
-- | - If SDRAM or OCRAM, start transaction and wait until read is valid
--
-- CARTRIDGE WRITE FROM SATURN
-- | - Multiplex data/address to retrieve write data
-- | - If register, process it immediately
-- | - If SDRAM or OCRAM, start transaction and hold it until write is terminated
--
-- Rules about mutiplexer control :
-- 1. Control with transaction counter, because in incremented during CS activity.
-- 2. Keep enough clocks at the beginning of CS activity to retrieve full address, and data if needed.
-- 3. After that, select and hold (until transaction counter becomes zero) appropriate bus direction.
process (clock)
begin
if rising_edge(clock) then
if saturn_reset = '0' then
abus_trcntr <= x"0"; -- Return to idle state during Saturn reset
else
if abus_trcntr = x"0" then
if ((abus_chipselect_p2(0) = '1') and (abus_chipselect_p2(1) = '1')
and ((abus_chipselect_p1(0) = '0') or (abus_chipselect_p1(1) = '0'))) then
abus_trcntr <= x"1"; -- Transaction startup
else
abus_trcntr <= x"0";
end if;
else
if (abus_chipselect(0) = '1') and (abus_chipselect(1) = '1') then
abus_trcntr <= x"0"; -- Return to idle state when CS returns to idle
else
if abus_trcntr = x"F" then
abus_trcntr <= x"F"; -- Hold counter to max until CS returns to idle
else
abus_trcntr <= abus_trcntr + x"1"; -- Go to next state
end if;
end if;
end if;
end if;
end if;
end process;
sim_test2_internal(3 downto 0) <= abus_trcntr(3 downto 0);
--whatever pulse we've got, latch address
--it might be latched twice per transaction, but it's not a problem
--multiplexer was switched to address after previous transaction or after boot,
--so we have address ready to latch
process (clock)
begin
if rising_edge(clock) then
if abus_trcntr = x"0" then
demux_readpulse <= '0';
demux_writepulse <= '0';
elsif abus_trcntr = x"1" then
-- Latch access base signals
abus_chipselect_latched <= abus_chipselect;
abus_read_latched <= abus_read;
abus_write_latched <= abus_write;
-- Generate read pulse (1/2)
if abus_read = '0' then
demux_readpulse <= '1';
end if;
elsif abus_trcntr = x"2" then
-- Generate read pulse (2/2)
if my_little_transaction_dir = DIR_READ then
demux_readpulse <= '0';
end if;
elsif abus_trcntr = x"4" then
-- Retrieve multiplexed data for write transaction, and generate write pulse
if my_little_transaction_dir = DIR_WRITE then
demux_writedata <= abus_data_in;
demux_writepulse <= '1';
end if;
elsif abus_trcntr = x"5" then
-- Terminate write pulse
if my_little_transaction_dir = DIR_WRITE then
demux_writepulse <= '0';
end if;
end if;
end if;
end process;
-- De-shuffle address
process(abus_address_latched, abus_address, abus_addressdata)
begin
if(abus_muxing_internal = "01") then
--if(abus_read = '1') then
-- 2019/07/20 : this is now adapted for "SIM to MAX 10 Board",
-- which allows multiplexing simpler than on cartridge
-- abus_address_latched <=
-- abus_address(7) -- abus_address(8) ignored ?!
-- & abus_address(6)
-- & abus_address(5)
-- & abus_address(4)
-- & abus_address(3)
-- & abus_address(2)
-- & abus_address(1)
-- & abus_address(0) -- TOP ADDRESS ^^^
-- & abus_addressdata(15) -- MUX vvv
-- & abus_addressdata(14)
-- & abus_addressdata(13)
-- & abus_addressdata(12)
-- & abus_addressdata(11)
-- & abus_addressdata(10)
-- & abus_addressdata( 9)
-- & abus_addressdata( 8)
-- & abus_addressdata( 7)
-- & abus_addressdata( 6)
-- & abus_addressdata( 5)
-- & abus_addressdata( 4)
-- & abus_addressdata( 3)
-- & abus_addressdata( 2)
-- & abus_addressdata( 1)
-- & abus_addressdata( 0);
--Purpose of A0 line in PCB Rev 1.3 is unknown and consequently
--have to be ignored when building address. Instead, address
--top bit is stuffed with '0'.
--Address Mapping for U4 : And for U1 : (In PCB Rev 1.3) abus_address_latched <= abus_address
-- A13 -> MUX12 A0 -> MUX0 & abus_addressdata(11) -- A14
-- A6 -> MUX13 A9 -> MUX1 & abus_addressdata(12) -- A13
-- A5 -> MUX14 A10 -> MUX2 & abus_addressdata( 9) -- A12
-- A4 -> MUX15 A8 -> MUX3 & abus_addressdata(10) -- A11
-- A3 -> MUX4 A7 -> MUX8 & abus_addressdata( 2) -- A10
-- A2 -> MUX5 A12 -> MUX9 & abus_addressdata( 1) -- A9
-- A1 -> MUX6 A11 -> MUX10 & abus_addressdata( 3) -- A8
-- DMY -> MUX7 A14 -> MUX11 & abus_addressdata( 8) -- A7
--Which gives the following order for de-shuffling address : & abus_addressdata(13) -- A6
-- A14 -> MUX11 & abus_addressdata(14) -- A5
-- A13 -> MUX12 & abus_addressdata(15) -- A4
-- A12 -> MUX9 & abus_addressdata( 4) -- A3
-- A11 -> MUX10 & abus_addressdata( 5) -- A2
-- A10 -> MUX2 & abus_addressdata( 6) -- A1
-- A9 -> MUX1 & abus_addressdata( 0); -- A0
-- A8 -> MUX3
-- A7 -> MUX8
-- A6 -> MUX13
-- A5 -> MUX14
-- A4 -> MUX15
-- A3 -> MUX4
-- A2 -> MUX5
-- A1 -> MUX6
-- A0 -> MUX0
abus_address_latched <= abus_address
& abus_addressdata(11) -- A14
& abus_addressdata(12) -- A13
& abus_addressdata( 9) -- A12
& abus_addressdata(10) -- A11
& abus_addressdata( 2) -- A10
& abus_addressdata( 1) -- A9
& abus_addressdata( 3) -- A8
& abus_addressdata( 8) -- A7
& abus_addressdata(13) -- A6
& abus_addressdata(14) -- A5
& abus_addressdata(15) -- A4
& abus_addressdata( 4) -- A3
& abus_addressdata( 5) -- A2
& abus_addressdata( 6) -- A1
& abus_addressdata( 0); -- A0
end if;
end process;
-- Update the following "static" informations while idle :
-- - Demuxed address, including CS0~1
-- - Write byte enable
process (clock)
begin
if rising_edge(clock) then
-- Address and CS0~1
if abus_trcntr = x"1" then
--if((clock = '1') and ((abus_trcntr = x"0") or (abus_trcntr = x"1")))then
-- Put both address itself and chipselect on the same demuxed address
-- Upper bits of demuxed address are currently unused and reserved for eventual future purpose.
--
-- And, separate address for both write and read access, so that write operation
-- have more chances to terminate even when read operation starts just after.
if(abus_read = '0') then
demux_readaddress(27) <= '0';
demux_readaddress(26) <= '0';
if abus_chipselect(0) = '0' then
demux_readaddress(25 downto 24) <= "00";
elsif abus_chipselect(1) = '0' then
demux_readaddress(25 downto 24) <= "01";
elsif abus_chipselect(2) = '0' then
demux_readaddress(25 downto 24) <= "10";
else
demux_readaddress(25 downto 24) <= "11"; -- Shouldn't happen since transaction is initiated when activity on CS is detected.
end if;
demux_readaddress(23 downto 0) <= abus_address_latched(23 downto 0);
else
demux_writeaddress(27) <= '0';
demux_writeaddress(26) <= '0';
if abus_chipselect(0) = '0' then
demux_writeaddress(25 downto 24) <= "00";
elsif abus_chipselect(1) = '0' then
demux_writeaddress(25 downto 24) <= "01";
elsif abus_chipselect(2) = '0' then
demux_writeaddress(25 downto 24) <= "10";
else
demux_writeaddress(25 downto 24) <= "11"; -- Shouldn't happen since transaction is initiated when activity on CS is detected.
end if;
demux_writeaddress(23 downto 0) <= abus_address_latched(23 downto 0);
end if;
end if;
end if;
end process;
process (clock)
begin
if saturn_reset = '0' then
demux_write_byteenable(0) <= '0';
demux_write_byteenable(1) <= '0';
else
-- Write byte enable
-- Keep holding it even while read operation started,
-- so that eventual ongoing write operation have more
-- chances to terminate correctly.
if((abus_trcntr = x"1") and (abus_read = '1'))then
demux_write_byteenable(0) <= not abus_write(0);
demux_write_byteenable(1) <= not abus_write(1);
end if;
end if;
end process;
-- If valid transaction captured, switch to corresponding multiplex mode
process (clock)
begin
if rising_edge(clock) then
if((abus_trcntr = x"0") or ((abus_chipselect(0) = '1') and (abus_chipselect(1) = '1')))then
abus_direction_internal <= '0' ; --high-z
abus_muxing_internal <= "01"; --address
elsif abus_trcntr = x"1" then
if abus_read = '0' then
abus_direction_internal <= '1' ; --active
abus_muxing_internal <= "10"; --data
else
abus_direction_internal <= '0' ; --high-z
abus_muxing_internal <= "10"; --data
end if;
elsif abus_trcntr = x"2" then
if abus_read = '0' then
abus_direction_internal <= '1' ; --active
abus_muxing_internal <= "10"; --data
else
abus_direction_internal <= '0' ; --high-z
abus_muxing_internal <= "10"; --data
end if;
-- Long multiplexer TEST vvv
-- Note 2019/12/13 : multiplexing during 1~2 is necessary for Wasca on real Hardware.
-- And so far it wasn't verified if multiplexing during 3 is necessary for MAX 10 Board r0.7 (b).
-- elsif abus_trcntr = x"3" then
-- if abus_read = '0' then
-- abus_direction_internal <= '1' ; --active
-- abus_muxing_internal <= "10"; --data
-- else
-- abus_direction_internal <= '0' ; --high-z
-- abus_muxing_internal <= "10"; --data
-- end if;
-- Long multiplexer TEST ^^^
else
if my_little_transaction_dir = DIR_READ then
abus_direction_internal <= '1' ; --active
abus_muxing_internal <= "10"; --data
else --if my_little_transaction_dir = DIR_READ then
abus_direction_internal <= '0' ; --high-z
abus_muxing_internal <= "01"; --address
end if;
end if;
end if;
end process;
abus_direction <= abus_direction_internal;
abus_muxing <= not abus_muxing_internal;
-- Update access direction
process (clock)
begin
if rising_edge(clock) then
if((abus_chipselect(0) = '1') and (abus_chipselect(1) = '1'))then
my_little_transaction_dir <= DIR_NONE;
abus_writing <= '0';
abus_reading <= '0';
elsif abus_trcntr = x"1" then
-- Decide access direction, and hold it until end of transaction
if abus_read = '0' then
my_little_transaction_dir <= DIR_READ;
abus_writing <= '0';
abus_reading <= '1';
else --if abus_read_ms = '0' then
my_little_transaction_dir <= DIR_WRITE;
abus_writing <= '1';
abus_reading <= '0';
end if;
end if;
end if;
end process;
-- Generate a reading/writing pulse during access
process (clock)
begin
if rising_edge(clock) then
if abus_trcntr = x"0" then
abus_write_pulse <= '0'; -- No access during idle state
abus_read_pulse <= '0'; -- No access during idle state
elsif abus_trcntr = x"1" then
if abus_write(0) = '0' or abus_write(1) = '0' then
abus_write_pulse <= '0'; -- Wait to receive data during a write transaction
abus_read_pulse <= '0';
else --if abus_read_ms = '0' then
abus_write_pulse <= '0';
abus_read_pulse <= '1'; -- Generate a read pulse when full address is received
end if;
elsif abus_trcntr = x"2" then
if my_little_transaction_dir = DIR_WRITE then
abus_write_pulse <= '1'; -- Generate a write pulse when both full address and data are received
abus_read_pulse <= '0';
else --if my_little_transaction_dir = DIR_READ then
abus_write_pulse <= '0';
abus_read_pulse <= '0'; -- Read transaction falling edge
end if;
elsif abus_trcntr = x"3" then
abus_read_pulse <= '0'; -- Write transaction falling edge
abus_write_pulse <= '0';
if my_little_transaction_dir = DIR_WRITE then
else --if my_little_transaction_dir = DIR_READ then
end if;
else
abus_read_pulse <= '0'; -- Write transaction falling edge
abus_write_pulse <= '0';
if my_little_transaction_dir = DIR_WRITE then
else --if my_little_transaction_dir = DIR_READ then
end if;
end if;
-- Delay write related signals
abus_writing_trail (0) <= abus_writing;
abus_write_pulse_trail(0) <= abus_write_pulse;
for i in 0 to (ABUS_TRAILS_SIZE-2) loop
abus_writing_trail (i+1) <= abus_writing_trail (i);
abus_write_pulse_trail(i+1) <= abus_write_pulse_trail(i);
end loop;
end if;
end process;
sim_test2_internal(7) <= abus_write_pulse_trail(3);
sim_test2_internal(6) <= abus_write_pulse_trail(2);
sim_test2_internal(5) <= abus_write_pulse_trail(1);
sim_test2_internal(4) <= abus_write_pulse_trail(0);
---------------------------------------------------------------------------------------
-- Update buffer data when read data valid pulse if detected
-- Read data valid pulse may not be super necessary, but this is provided by Avalon,
-- and may be helpful when counting clocks elapsed during read access.
--
process (abus_reading) begin
abus_data_out <= demux_readdata; -- Faster than below
if rising_edge(clock) then
if(demux_readdatavalid = '1') then
--abus_data_out <= demux_readdata;
end if;
end if;
end process;
---------------------------------------------------------------------------------------
-- In/Out process
--
-- Access from each CS0-2 is handled from this chip.
-- In the future, it may be required to manage access to external FTDI chip ?
--
process (abus_reading) begin
--if rising_edge(clock) then
--if(abus_reading = '1') then
if(abus_read = '0') then
-- Output to data bus
abus_addressdata <= abus_data_out;
--abus_addressdata <= x"ABCD";
--sim_test2_internal <= x"CA";
abus_data_in <= abus_addressdata;
else
-- Disable output to data bus
abus_addressdata <= "ZZZZZZZZZZZZZZZZ";
abus_data_in <= abus_addressdata;
--sim_test2_internal <= x"FF";
end if;
--end if;
end process;
sim_test1_internal(7) <= abus_writing;
sim_test1_internal(6) <= abus_reading;
sim_test1_internal(5) <= abus_write_pulse;
sim_test1_internal(4) <= abus_read_pulse;
sim_test1_internal(3) <= abus_writing_trail(0);
sim_test1_internal(2) <= abus_writing_trail(1);
sim_test1_internal(1) <= abus_writing_trail(2);
sim_test1_internal(0) <= '1';
-- "disable_out" controls refresh timing of wait and IRQ signals
-- 0:output, 1:hold previous
--abus_disable_out <= '1' when abus_chipselect_number(1) = '1' else '0';
abus_disable_out <= '0';
-- Let's completely neglect usage of wait request signal for now, and ... hope that
-- SDRAM controller is smarter enough to do things timely.
-- (Spoiler : SDRAM controller is completely dumb)
abus_waitrequest <= '1';
-- process (clock)
-- begin
-- if rising_edge(clock) then
-- abus_waitrequest_read2 <= abus_waitrequest_read1;
-- abus_waitrequest_write2 <= abus_waitrequest_write1;
-- end if;
-- end process;
--
-- process (clock)
-- begin
-- if rising_edge(clock) then
-- abus_waitrequest_read_off <= '0';
-- abus_waitrequest_write_off <= '0';
-- if abus_waitrequest_read1 = '0' and abus_waitrequest_read2 = '1' then
-- abus_waitrequest_read_off <= '1';
-- end if;
-- if abus_waitrequest_write1 = '0' and abus_waitrequest_write2 = '1' then
-- abus_waitrequest_write_off <= '1';
-- end if;
-- end if;
-- end process;
--
-- --process (clock)
-- --begin
-- -- if rising_edge(clock) then
-- -- --if abus_read_pulse_dmy='1' or abus_write_pulse_dmy(0)='1' or abus_write_pulse_dmy(1)='1' then
-- -- --if abus_anypulse = '1' then
-- -- if abus_chipselect_pulse(0) = '1' or abus_chipselect_pulse(1) = '1' then
-- -- abus_waitrequest <= '0';
-- -- elsif abus_waitrequest_read_off='1' or abus_waitrequest_write_off='1' then
-- -- abus_waitrequest <= '1';
-- -- end if;
-- -- end if;
-- --end process;
--
-- abus_waitrequest <= not (abus_waitrequest_read1 or abus_waitrequest_write1);
--Nios II read interface
process (clock)
begin
if rising_edge(clock) then
if avalon_nios_read = '1' then
avalon_nios_readdatavalid <= '1';
case avalon_nios_address is
-- Debug stuff around Rd/Wr access
when X"00" =>
avalon_nios_readdata <= x"CA0000" & rd_access_cntr;
when X"01" =>
avalon_nios_readdata <= x"FE0000" & wr_access_cntr;
when X"10" =>
avalon_nios_readdata <= x"0000" & REG_PCNTR;
when X"11" =>
avalon_nios_readdata <= x"0000" & REG_STATUS;
when X"12" =>
avalon_nios_readdata <= x"0000" & REG_MODE;
when X"13" =>
avalon_nios_readdata <= x"0000" & REG_HWVER;
when X"14" =>
avalon_nios_readdata <= x"0000" & REG_SWVER;
when X"15" =>
avalon_nios_readdata <= X"0000ABCD"; --for debug, remove later
when others =>
avalon_nios_readdata <= x"00000000";
end case;
else
avalon_nios_readdatavalid <= '0';
end if;
end if;
end process;
--Nios II write interface
process (clock)
begin
if rising_edge(clock) then
if avalon_nios_write= '1' then
case avalon_nios_address is
when X"10" =>
REG_PCNTR <= avalon_nios_writedata(15 downto 0);
when X"11" =>
REG_STATUS <= avalon_nios_writedata(15 downto 0);
when X"12" =>
null;
when X"13" =>
null;
when X"14" =>
REG_SWVER <= avalon_nios_writedata(15 downto 0);
when others =>
null;
end case;
end if;
end if;
end process;
--Nios system interface is only regs, so always ready to write.
avalon_nios_waitrequest <= '0';
-- -- External signals used for simulation vvv
-- sim_test1 <= sim_test1_internal;
-- sim_test2 <= sim_test2_internal;
-- abus_cspulse_trail_dbg <= abus_cspulse_trail;
-- abus_read_trail_dbg <= abus_read_trail;
-- abus_writeneg0_trail_dbg <= abus_writeneg0_trail;
-- abus_writeneg1_trail_dbg <= abus_writeneg1_trail;
-- abus_addresslatched_dbg <= abus_address_latched;
-- -- External signals used for simulation ^^^
end architecture rtl; -- of abus_demux
| gpl-2.0 | 3bed4326114150b9268cc0ca5f7b6ed4 | 0.480742 | 4.14816 | false | false | false | false |
impedimentToProgress/UCI-BlueChip | AttackFiles/Attacks/privEsc/lib/gaisler/pci/pci_mt.vhd | 2 | 28,639 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: pci_mt
-- File: pci_mt.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Modified: Alf Vaerneus - Gaisler Research
-- Description: Simple PCI master and target interface
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
library gaisler;
use gaisler.pci.all;
use gaisler.misc.all;
use gaisler.pcilib.all;
entity pci_mt is
generic (
hmstndx : integer := 0;
abits : integer := 21;
device_id : integer := 0; -- PCI device ID
vendor_id : integer := 0; -- PCI vendor ID
master : integer := 1; -- Enable PCI Master
hslvndx : integer := 0;
haddr : integer := 16#F00#;
hmask : integer := 16#F00#;
ioaddr : integer := 16#000#;
nsync : integer range 1 to 2 := 1; -- 1 or 2 sync regs between clocks
oepol : integer := 0
);
port(
rst : in std_logic;
clk : in std_logic;
pciclk : in std_logic;
pcii : in pci_in_type;
pcio : out pci_out_type;
ahbmi : in ahb_mst_in_type;
ahbmo : out ahb_mst_out_type;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type
);
end;
architecture rtl of pci_mt is
constant REVISION : amba_version_type := 0;
constant hconfig : ahb_config_type := (
0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_PCISBRG, 0, REVISION, 0),
4 => ahb_membar(haddr, '0', '0', hmask),
5 => ahb_iobar (ioaddr, 16#E00#),
others => zero32);
constant CSYNC : integer := nsync-1;
constant MADDR_WIDTH : integer := abits;
constant HADDR_WIDTH : integer := 28;
type pci_input_type is record
ad : std_logic_vector(31 downto 0);
cbe : std_logic_vector(3 downto 0);
frame : std_logic;
devsel : std_logic;
idsel : std_logic;
trdy : std_logic;
irdy : std_logic;
par : std_logic;
stop : std_logic;
rst : std_logic;
gnt : std_logic;
end record;
type ahbs_input_type is record
haddr : std_logic_vector(HADDR_WIDTH - 1 downto 0);
htrans : std_logic_vector(1 downto 0);
hwrite : std_logic;
hsize : std_logic_vector(1 downto 0);
hburst : std_logic_vector(2 downto 0);
hwdata : std_logic_vector(31 downto 0);
hsel : std_logic;
hiosel : std_logic;
hready : std_logic;
end record;
type pci_target_state_type is (idle, b_busy, s_data, backoff, turn_ar);
type pci_master_state_type is (idle, addr, m_data, turn_ar, s_tar, dr_bus);
type pci_config_command_type is record
ioen : std_logic; -- I/O access enable
men : std_logic; -- Memory access enable
msen : std_logic; -- Master enable
spcen : std_logic; -- Special cycle enable
mwie : std_logic; -- Memory write and invalidate enable
vgaps : std_logic; -- VGA palette snooping enable
per : std_logic; -- Parity error response enable
wcc : std_logic; -- Address stepping enable
serre : std_logic; -- Enable SERR# driver
fbtbe : std_logic; -- Fast back-to-back enable
end record;
type pci_config_status_type is record
c66mhz : std_logic; -- 66MHz capability
udf : std_logic; -- UDF supported
fbtbc : std_logic; -- Fast back-to-back capability
dped : std_logic; -- Data parity error detected
dst : std_logic_vector(1 downto 0); -- DEVSEL timing
sta : std_logic; -- Signaled target abort
rta : std_logic; -- Received target abort
rma : std_logic; -- Received master abort
sse : std_logic; -- Signaled system error
dpe : std_logic; -- Detected parity error
end record;
type pci_reg_type is record
addr : std_logic_vector(MADDR_WIDTH-1 downto 0);
ad : std_logic_vector(31 downto 0);
cbe : std_logic_vector(3 downto 0);
lcbe : std_logic_vector(3 downto 0);
t_state : pci_target_state_type; -- PCI target state machine
m_state : pci_master_state_type; -- PCI master state machine
csel : std_logic; -- Configuration chip select
msel : std_logic; -- Memory hit
read : std_logic;
devsel : std_logic; -- PCI device select
trdy : std_logic; -- Target ready
irdy : std_logic; -- Master ready
stop : std_logic; -- Target stop request
par : std_logic; -- PCI bus parity
req : std_logic; -- Master bus request
oe_par : std_logic;
oe_ad : std_logic;
oe_trdy : std_logic;
oe_devsel: std_logic;
oe_ctrl : std_logic;
oe_cbe : std_logic;
oe_stop : std_logic;
oe_frame : std_logic;
oe_irdy : std_logic;
oe_req : std_logic;
noe_par : std_logic;
noe_ad : std_logic;
noe_trdy : std_logic;
noe_devsel: std_logic;
noe_ctrl : std_logic;
noe_cbe : std_logic;
noe_stop : std_logic;
noe_frame : std_logic;
noe_irdy : std_logic;
noe_req : std_logic;
request : std_logic; -- Request from Back-end
frame : std_logic; -- Master frame
bar0 : std_logic_vector(31 downto MADDR_WIDTH);
page : std_logic_vector(31 downto MADDR_WIDTH-1);
comm : pci_config_command_type;
stat : pci_config_status_type;
laddr : std_logic_vector(31 downto 0);
ldata : std_logic_vector(31 downto 0);
pwrite : std_logic;
hwrite : std_logic;
start : std_logic;
hreq : std_logic;
hreq_ack : std_logic_vector(csync downto 0);
preq : std_logic_vector(csync downto 0);
preq_ack : std_logic;
rready : std_logic_vector(csync downto 0);
wready : std_logic_vector(csync downto 0);
sync : std_logic_vector(csync downto 0);
pabort : std_logic;
mcnt : std_logic_vector(2 downto 0);
maddr : std_logic_vector(31 downto 0);
mdata : std_logic_vector(31 downto 0);
stop_req : std_logic;
end record;
type cpu_master_state_type is (idle, sync1, busy, sync2);
type cpu_slave_state_type is (idle, getd, req, sync, read, sync2, t_done);
type cpu_reg_type is record
tdata : std_logic_vector(31 downto 0); -- Target data
maddr : std_logic_vector(31 downto 0); -- Master data
mdata : std_logic_vector(31 downto 0); -- Master data
be : std_logic_vector(3 downto 0);
m_state : cpu_master_state_type; -- AMBA master state machine
s_state : cpu_slave_state_type; -- AMBA slave state machine
start : std_logic_vector(csync downto 0);
hreq : std_logic_vector(csync downto 0);
hreq_ack : std_logic;
preq : std_logic;
preq_ack : std_logic_vector(csync downto 0);
sync : std_logic;
hwrite : std_logic; -- AHB write on PCI
pabort : std_logic_vector(csync downto 0);
perror : std_logic;
rready : std_logic;
wready : std_logic;
hrdata : std_logic_vector(31 downto 0);
hresp : std_logic_vector(1 downto 0);
pciba : std_logic_vector(3 downto 0);
end record;
signal clk_int : std_logic;
signal pr : pci_input_type;
signal hr : ahbs_input_type;
signal r, rin : pci_reg_type;
signal r2, r2in : cpu_reg_type;
signal dmai : ahb_dma_in_type;
signal dmao : ahb_dma_out_type;
signal roe_ad, rioe_ad : std_logic_vector(31 downto 0);
attribute syn_preserve : boolean;
attribute syn_preserve of roe_ad : signal is true;
begin
-- Back-end state machine (AHB clock domain)
comb : process (rst, r2, r, dmao, hr, ahbsi)
variable vdmai : ahb_dma_in_type;
variable v : cpu_reg_type;
variable request : std_logic;
variable hready : std_logic;
variable hresp, hsize, htrans : std_logic_vector(1 downto 0);
variable p_done : std_logic;
begin
v := r2;
vdmai.start := '0'; vdmai.burst := '0'; vdmai.size := "10";
vdmai.address := r.laddr; v.sync := '1';
vdmai.wdata := r.ldata; vdmai.write := r.pwrite;
v.start(0) := r2.start(csync); v.start(csync) := r.start;
v.hreq(0) := r2.hreq(csync); v.hreq(csync) := r.hreq;
v.pabort(0) := r2.pabort(csync); v.pabort(csync) := r.pabort;
v.preq_ack(0) := r2.preq_ack(csync); v.preq_ack(csync) := r.preq_ack;
hready := '1'; hresp := HRESP_OKAY; request := '0';
hsize := "10"; htrans := "00";
p_done := r2.hreq(0) or r2.pabort(0);
---- *** APB register access *** ----
--if (apbi.psel and apbi.penable and apbi.pwrite) = '1' then
--v.pciba := apbi.pwdata(31 downto 28);
--end if;
--apbo.prdata <= r2.pciba & addzero;
if hr.hiosel = '1' then
if hr.hwrite = '1' then v.pciba := ahbsi.hwdata(31 downto 28); end if;
v.hrdata := r2.pciba & addzero(27 downto 0);
end if;
---- *** AHB MASTER *** ----
case r2.m_state is
when idle =>
v.sync := '0';
if r2.start(0) = '1' then
if r.pwrite = '1' then v.m_state := sync1; v.wready := '0';
else v.m_state := busy; vdmai.start := '1'; end if;
end if;
when sync1 =>
if r2.start(0) = '0' then v.m_state := busy; vdmai.start := '1'; end if;
when busy =>
if dmao.active = '1' then
if dmao.ready = '1' then
v.rready := not r.pwrite; v.tdata := dmao.rdata; v.m_state := sync2;
end if;
else vdmai.start := '1'; end if;
when sync2 =>
if r2.start(0) = '0' then
v.m_state := idle; v.wready := '1'; v.rready := '0';
end if;
end case;
---- *** AHB MASTER END *** ----
---- *** AHB SLAVE *** ----
if MASTER = 1 then
if (hr.hready and hr.hsel) = '1' then
hsize := hr.hsize; htrans := hr.htrans;
if (hr.htrans(1) and r.comm.msen) = '1' then request := '1'; end if;
end if;
if (request = '1' and r2.s_state = idle) then
v.maddr := r2.pciba & hr.haddr;
v.hwrite := hr.hwrite;
case hsize is
when "00" => v.be := "1110"; -- Decode byte enable
when "01" => v.be := "1100";
when "10" => v.be := "0000";
when others => v.be := "1111";
end case;
elsif r2.s_state = getd and r2.hwrite = '1' then
v.mdata := hr.hwdata;
end if;
if r2.hreq(0) = '1' then v.hrdata := r.ldata; end if;
if r2.preq_ack(0) = '1' then v.preq := '0'; end if;
if r2.pabort(0) = '1' then v.perror := '1'; end if;
if p_done = '0' then v.hreq_ack := '0'; end if;
-- AHB slave state machine
case r2.s_state is
when idle => if request = '1' then v.s_state := getd; end if;
when getd => v.s_state := req; v.preq := '1';
when req => if r2.preq_ack(0) = '1' then v.s_state := sync; end if;
when sync => if r2.preq_ack(0) = '0' then v.s_state := read; end if;
when read =>
if p_done = '1' then v.hreq_ack := '1'; v.s_state := sync2; end if;
when sync2 => if p_done = '0' then v.s_state := t_done; end if;
when t_done => if request = '1' then v.s_state := idle; end if;
when others => v.s_state := idle;
end case;
if request = '1' then
if r2.s_state = t_done then
if r2.perror = '1' then hresp := HRESP_ERROR;
else hresp := HRESP_OKAY; end if;
v.perror := '0';
else hresp := HRESP_RETRY; end if;
end if;
if r.comm.msen = '0' then hresp := HRESP_ERROR; end if; -- Master disabled
if htrans(1) = '0' then hresp := HRESP_OKAY; end if; -- Response OK for BUSY and IDLE
if (hresp /= HRESP_OKAY and (hr.hready and hr.hsel) = '1') then -- insert one wait cycle
hready := '0';
end if;
if hr.hready = '0' then hresp := r2.hresp; end if;
v.hresp := hresp;
end if;
---- *** AHB SLAVE END *** ----
if rst = '0' then
v.s_state := idle; v.rready := '0'; v.wready := '1';
v.m_state := idle; v.preq := '0'; v.hreq_ack := '0';
v.perror := '0'; v.be := (others => '1');
v.pciba := (others => '0'); v.hresp := (others => '0');
end if;
r2in <= v; dmai <= vdmai;
ahbso.hready <= hready;
ahbso.hresp <= hresp;
ahbso.hrdata <= r2.hrdata;
end process;
ahbso.hconfig <= hconfig when MASTER = 1 else (others => zero32);
ahbso.hsplit <= (others => '0');
ahbso.hirq <= (others => '0');
ahbso.hindex <= hslvndx;
-- PCI target core (PCI clock domain)
pcicomb : process(pcii.rst, pr, pcii, r, r2, roe_ad)
variable v : pci_reg_type;
variable chit, mhit, hit, ready, cwrite : std_logic;
variable cdata, cwdata : std_logic_vector(31 downto 0);
variable comp : std_logic; -- Last transaction cycle on PCI bus
variable iready : std_logic;
variable mto : std_logic;
variable tad, mad : std_logic_vector(31 downto 0);
-- variable cbe : std_logic_vector(3 downto 0);
variable caddr : std_logic_vector(7 downto 2);
variable voe_ad : std_logic_vector(31 downto 0);
variable oe_par : std_logic;
variable oe_ad : std_logic;
variable oe_ctrl : std_logic;
variable oe_trdy : std_logic;
variable oe_devsel: std_logic;
variable oe_cbe : std_logic;
variable oe_stop : std_logic;
variable oe_frame : std_logic;
variable oe_irdy : std_logic;
variable oe_req : std_logic;
begin
-- Process defaults
v := r; v.trdy := '1'; v.stop := '1'; v.frame := '1';
v.oe_ad := '1'; v.devsel := '1'; v.oe_frame := '1';
v.irdy := '1'; v.req := '1'; voe_ad := roe_ad;
v.oe_req := '0'; v.oe_cbe := '1'; v.oe_irdy := '1';
v.rready(0) := r.rready(csync); v.rready(csync) := r2.rready;
v.wready(0) := r.wready(csync); v.wready(csync) := r2.wready;
v.sync(0) := r.sync(csync); v.sync(csync) := r2.sync;
v.preq(0) := r.preq(csync); v.preq(csync) := r2.preq;
v.hreq_ack(0) := r.hreq_ack(csync); v.hreq_ack(csync) := r2.hreq_ack;
comp := '0'; mto := '0'; tad := r.ad; mad := r.ad; v.stop_req := '0';
--cbe := r.cbe;
----- *** PCI TARGET *** --------
-- address decoding
if (r.t_state = s_data) and ((pr.irdy or r.trdy or r.read) = '0') then
cwrite := r.csel;
if ((r.msel and r.addr(MADDR_WIDTH-1)) = '1') and (pr.cbe = "0000") then
v.page := pr.ad(31 downto MADDR_WIDTH-1);
end if;
if (pr.cbe = "0000") and (r.addr(MADDR_WIDTH-1) = '1') then
end if;
else cwrite := '0'; end if;
cdata := (others => '0'); caddr := r.addr(7 downto 2);
case caddr is
when "000000" => -- 0x00, device & vendor id
cdata := conv_std_logic_vector(DEVICE_ID, 16) &
conv_std_logic_vector(VENDOR_ID, 16);
when "000001" => -- 0x04, status & command
cdata(1) := r.comm.men; cdata(2) := r.comm.msen; cdata(25) := '1';
cdata(28) := r.stat.rta; cdata(29) := r.stat.rma;
when "000010" => -- 0x08, class code & revision
when "000011" => -- 0x0c, latency & cacheline size
when "000100" => -- 0x10, BAR0
cdata(31 downto MADDR_WIDTH) := r.bar0;
when others =>
end case;
cwdata := pr.ad;
if pr.cbe(3) = '1' then cwdata(31 downto 24) := cdata(31 downto 24); end if;
if pr.cbe(2) = '1' then cwdata(23 downto 16) := cdata(23 downto 16); end if;
if pr.cbe(1) = '1' then cwdata(15 downto 8) := cdata(15 downto 8); end if;
if pr.cbe(0) = '1' then cwdata( 7 downto 0) := cdata( 7 downto 0); end if;
if cwrite = '1' then
case caddr is
when "000001" => -- 0x04, status & command
v.comm.men := cwdata(1);
v.comm.msen := cwdata(2);
v.stat.rta := r.stat.rta and not cwdata(28);
v.stat.rma := r.stat.rma and not cwdata(29);
when "000100" => -- 0x10, BAR0
v.bar0 := cwdata(31 downto MADDR_WIDTH);
when others =>
end case;
end if;
if (((pr.cbe = pci_config_read) or (pr.cbe = pci_config_write))
and (pr.ad(1 downto 0) = "00"))
then chit := '1'; else chit := '0'; end if;
if ((pr.cbe = pci_memory_read) or (pr.cbe = pci_memory_write))
and (r.bar0 = pr.ad(31 downto MADDR_WIDTH))
and (r.bar0 /= zero(31 downto MADDR_WIDTH))
then mhit := '1'; else mhit := '0'; end if;
hit := r.csel or r.msel;
ready := r.csel or (r.rready(0) and r.read) or (r.wready(0) and not r.read and not r.start) or
r.addr(MADDR_WIDTH-1);
-- target state machine
case r.t_state is
when idle =>
if pr.frame = '0' then v.t_state := b_busy; end if; -- !HIT ?
v.addr := pr.ad(MADDR_WIDTH-1 downto 0); -- v.cbe := pr.cbe;
v.csel := pr.idsel and chit;
v.msel := r.comm.men and mhit; v.read := not pr.cbe(0);
if (r.sync(0) and r.start and r.pwrite) = '1' then v.start := '0'; end if;
when turn_ar =>
if pr.frame = '1' then v.t_state := idle; end if;
if pr.frame = '0' then v.t_state := b_busy; end if; -- !HIT ?
v.addr := pr.ad(MADDR_WIDTH-1 downto 0); -- v.cbe := pr.cbe;
v.csel := pr.idsel and chit;
v.msel := r.comm.men and mhit; v.read := not pr.cbe(0);
if (r.sync(0) and r.start and r.pwrite) = '1' then v.start := '0'; end if;
when b_busy =>
if hit = '1' then
v.t_state := s_data; v.trdy := not ready; v.stop := pr.frame and ready;
v.devsel := '0';
else
v.t_state := backoff;
end if;
when s_data =>
v.stop := r.stop; v.devsel := '0';
v.trdy := r.trdy or not pcii.irdy;
if (pcii.frame and not pcii.irdy) = '1' then
v.t_state := turn_ar; v.stop := '1'; v.trdy := '1'; v.devsel := '1';
end if;
when backoff =>
if pr.frame = '1' then v.t_state := idle; end if;
end case;
if ((r.t_state = s_data) or (r.t_state = turn_ar)) and
(((pr.irdy or pr.trdy) = '0') or
((not pr.irdy and not pr.stop and pr.trdy and not r.start and r.wready(0)) = '1'))
then
if (pr.trdy and r.read)= '0' then v.start := '0'; end if;
if (r.start = '0') and ((r.msel and not r.addr(MADDR_WIDTH-1)) = '1') and
(((pr.trdy and r.read and not r.rready(0)) or (not pr.trdy and not r.read)) = '1')
then
v.laddr := r.page & r.addr(MADDR_WIDTH-2 downto 0);
v.ldata := pr.ad; v.pwrite := not r.read; v.start := '1';
end if;
end if;
-- if (v.t_state = s_data) and (r.read = '1') then v.oe_ad := '0'; end if;
-- v.oe_par := r.oe_ad;
if r.csel = '1' then tad := cdata;
elsif r.addr(MADDR_WIDTH-1) = '1' then
tad(31 downto MADDR_WIDTH-1) := r.page;
tad(MADDR_WIDTH-2 downto 0) := (others => '0');
else tad := r2.tdata; end if;
if (v.t_state = s_data) or (r.t_state = s_data) then
v.oe_ctrl := '0';
else v.oe_ctrl := '1'; end if;
----- *** PCI TARGET END*** --------
----- *** PCI MASTER *** --------
if MASTER = 1 then
if r.preq(0) = '1' then
if (r.m_state = idle or r.m_state = dr_bus) and r.request = '0' and r.hreq = '0' then
v.request := '1';
v.hwrite := r2.hwrite;
v.lcbe := r2.be;
v.mdata := r2.mdata;
v.maddr :=r2.maddr;
end if;
end if;
if r.hreq_ack(0) = '1' then v.hreq := '0'; v.pabort := '0'; end if;
if r.preq(0) = '0' then v.preq_ack := '0'; end if;
comp := not(pcii.trdy or pcii.irdy);
if ((pr.irdy and not pr.frame) or (pr.devsel and r.frame and not r.oe_frame)) = '1' then -- Covers both master timeout and devsel timeout
if r.mcnt /= "000" then v.mcnt := r.mcnt - 1;
else mto := '1'; end if;
else v.mcnt := (others => '1'); end if;
-- PCI master state machine
case r.m_state is
when idle => -- Master idle
if (pr.gnt = '0' and (pr.frame and pr.irdy) = '1') then
if r.request = '1' then v.m_state := addr; v.preq_ack := '1';
else v.m_state := dr_bus; end if;
end if;
when addr => -- Always one address cycle at the beginning of an transaction
v.m_state := m_data;
when m_data => -- Master transfers data
--if (r.request and not pr.gnt and pr.frame and not pr.trdy -- Not supporting address stepping!
--and pr.stop and l_cycle and sa) = '1' then
--v.m_state <= addr;
v.hreq := comp;
if (pr.frame = '0') or ((pr.frame and pcii.trdy and pcii.stop and not mto) = '1') then
v.m_state := m_data;
elsif ((pr.frame and (mto or not pcii.stop)) = '1') then
v.m_state := s_tar;
else v.m_state := turn_ar; v.request := '0'; end if;
when turn_ar => -- Transaction complete
if (r.request and not pr.gnt) = '1' then v.m_state := addr;
elsif (r.request or pr.gnt) = '0' then v.m_state := dr_bus;
else v.m_state := idle; end if;
when s_tar => -- Stop was asserted
v.request := pr.trdy and not pr.stop and not pr.devsel;
v.stop_req := '1';
if (pr.stop or pr.devsel or pr.trdy) = '0' then -- Disconnect with data
v.m_state := turn_ar;
elsif pr.gnt = '0' then
v.pabort := not v.request;
v.m_state := dr_bus;
else v.m_state := idle; v.pabort := not v.request; end if;
when dr_bus => -- Drive bus when parked on this agent
if (r.request = '1' and (pcii.gnt or r.req) = '0') then v.m_state := addr; v.preq_ack := '1';
elsif pcii.gnt = '1' then v.m_state := idle; end if;
end case;
if v.m_state = addr then mad := r.maddr; else mad := r.mdata; end if;
if (pr.irdy or pr.trdy or r.hwrite) = '0' then v.ldata := pr.ad; end if;
-- Target abort
if ((pr.devsel and pr.trdy and not pr.gnt and not pr.stop) = '1') then v.stat.rta := '1'; end if;
-- Master abort
if mto = '1' then v.stat.rma := '1'; end if;
-- Drive FRAME# and IRDY#
if (v.m_state = addr or v.m_state = m_data) then v.oe_frame := '0'; end if;
-- Drive CBE#
if (v.m_state = addr or v.m_state = m_data or v.m_state = dr_bus) then v.oe_cbe := '0'; end if;
-- Drive IRDY# (FRAME# delayed one pciclk)
v.oe_irdy := r.oe_frame;
-- FRAME# assert
if v.m_state = addr then v.frame := '0'; end if; -- Only single transfers valid
-- IRDY# assert
if v.m_state = m_data then v.irdy := '0'; end if;
-- REQ# assert
if (v.request = '1' and (v.m_state = idle or r.m_state = idle) and (v.stop_req or r.stop_req) = '0') then v.req := '0'; end if;
-- C/BE# assert
if v.m_state = addr then v.cbe := "011" & r.hwrite; else v.cbe := r.lcbe; end if;
end if;
----- *** PCI MASTER END *** --------
----- *** SHARED BUS SIGNALS *** -------
-- Drive PAR
v.oe_par := r.oe_ad; --Delayed one clock
v.par := xorv(r.ad & r.cbe); -- Default asserted by master
v.ad := mad; -- Default asserted by master
-- Master
if (v.m_state = addr or (v.m_state = m_data and r.hwrite = '1') or v.m_state = dr_bus) then
v.oe_ad := '0';
end if;
-- Drive AD
-- Target
if r.read = '1' then
if v.t_state = s_data then
v.oe_ad := '0';
v.ad := tad;
elsif r.t_state = s_data then
v.par := xorv(r.ad & pcii.cbe);
end if;
end if;
v.oe_stop := v.oe_ctrl; v.oe_devsel := v.oe_ctrl; v.oe_trdy := v.oe_ctrl;
v.noe_ad := not v.oe_ad; v.noe_ctrl := not v.oe_ctrl;
v.noe_par := not v.oe_par; v.noe_req := not v.oe_req;
v.noe_frame := not v.oe_frame; v.noe_cbe := not v.oe_cbe;
v.noe_irdy := not v.oe_irdy;
v.noe_stop := not v.oe_ctrl; v.noe_devsel := not v.oe_ctrl;
v.noe_trdy := not v.oe_ctrl;
if oepol = 0 then
voe_ad := (others => v.oe_ad);
oe_ad := r.oe_ad; oe_ctrl := r.oe_ctrl; oe_par := r.oe_par;
oe_req := r.oe_req; oe_frame := r.oe_frame; oe_cbe := r.oe_cbe;
oe_irdy := r.oe_irdy; oe_stop := r.oe_stop; oe_trdy := r.oe_trdy;
oe_devsel := r.oe_devsel;
else
voe_ad := (others => v.noe_ad);
oe_ad := r.noe_ad; oe_ctrl := r.noe_ctrl; oe_par := r.noe_par;
oe_req := r.noe_req; oe_frame := r.noe_frame; oe_cbe := r.noe_cbe;
oe_irdy := r.noe_irdy; oe_stop := r.noe_stop; oe_trdy := r.noe_trdy;
oe_devsel := r.noe_devsel;
end if;
----- *** SHARED BUS SIGNALS END *** -------
if pr.rst = '0' then
v.t_state := idle; v.m_state := idle; v.comm.men := '0'; v.start := '0';
v.bar0 := (others => '0'); v.msel := '0'; v.csel := '0';
v.page := (others => '0'); v.page(31 downto 30) := "01"; v.par := '0';
v.hwrite := '0'; v.request := '0'; v.comm.msen := '0';
v.laddr := (others => '0'); v.ldata := (others => '0');
v.hreq := '0'; v.preq_ack := '0'; v.pabort := '0';
v.mcnt := (others => '1'); v.maddr := (others => '0');
v.lcbe := (others => '0'); v.mdata := (others => '0');
v.pwrite := '0'; v.stop_req := '0';
v.stat.rta := '0'; v.stat.rma := '0';
end if;
rin <= v;
rioe_ad <= voe_ad;
pcio.reqen <= oe_req;
pcio.req <= r.req;
pcio.frameen <= oe_frame;
pcio.frame <= r.frame;
pcio.irdyen <= oe_irdy;
pcio.irdy <= r.irdy;
pcio.cbeen <= (others => oe_cbe);
pcio.cbe <= r.cbe;
pcio.vaden <= roe_ad;
pcio.aden <= oe_ad;
pcio.ad <= r.ad;
pcio.trdy <= r.trdy;
pcio.ctrlen <= oe_ctrl;
pcio.trdyen <= oe_trdy;
pcio.devselen <= oe_devsel;
pcio.stopen <= oe_stop;
pcio.stop <= r.stop;
pcio.devsel <= r.devsel;
pcio.par <= r.par;
pcio.paren <= oe_par;
end process;
pcir : process (pciclk, pcii.rst)
begin
if rising_edge (pciclk) then
pr.ad <= to_x01(pcii.ad);
pr.cbe <= to_x01(pcii.cbe);
pr.devsel <= to_x01(pcii.devsel);
pr.frame <= to_x01(pcii.frame);
pr.idsel <= to_x01(pcii.idsel);
pr.irdy <= to_x01(pcii.irdy);
pr.trdy <= to_x01(pcii.trdy);
pr.par <= to_x01(pcii.par);
pr.stop <= to_x01(pcii.stop);
pr.rst <= to_x01(pcii.rst);
pr.gnt <= to_x01(pcii.gnt);
r <= rin;
roe_ad <= rioe_ad;
end if;
if pcii.rst = '0' then -- asynch reset required
r.oe_ad <= '1'; r.oe_ctrl <= '1'; r.oe_par <= '1'; r.oe_stop <= '1';
r.oe_req <= '1'; r.oe_frame <= '1'; r.oe_cbe <= '1'; r.oe_irdy <= '1';
r.oe_trdy <= '1'; r.oe_devsel <= '1';
r.noe_ad <= '0'; r.noe_ctrl <= '0'; r.noe_par <= '0'; r.noe_req <= '0';
r.noe_frame <= '0'; r.noe_cbe <= '0'; r.noe_irdy <= '0'; r.noe_stop <= '0';
r.noe_trdy <= '0'; r.noe_devsel <= '0';
if oepol = 0 then roe_ad <= (others => '1');
else roe_ad <= (others => '0'); end if;
end if;
end process;
cpur : process (rst,clk)
begin
if rising_edge (clk) then
hr.haddr <= ahbsi.haddr(HADDR_WIDTH - 1 downto 0);
hr.htrans <= ahbsi.htrans;
hr.hwrite <= ahbsi.hwrite;
hr.hsize <= ahbsi.hsize(1 downto 0);
hr.hburst <= ahbsi.hburst;
hr.hwdata <= ahbsi.hwdata;
hr.hsel <= ahbsi.hsel(hslvndx) and ahbsi.hmbsel(0);
hr.hiosel <= ahbsi.hsel(hslvndx) and ahbsi.hmbsel(1);
hr.hready <= ahbsi.hready;
r2 <= r2in;
end if;
end process;
oe0 : if oepol = 0 generate
pcio.perren <= '1';
pcio.serren <= '1';
pcio.inten <= '1';
pcio.locken <= '1';
end generate;
oe1 : if oepol = 1 generate
pcio.perren <= '0';
pcio.serren <= '0';
pcio.inten <= '0';
pcio.locken <= '0';
end generate;
pcio.perr <= '1';
pcio.serr <= '1';
pcio.int <= '1';
msttgt : if MASTER = 1 generate
ahbmst0 : ahbmst generic map (hindex => hmstndx, devid => GAISLER_PCISBRG)
port map (rst, clk, dmai, dmao, ahbmi, ahbmo);
-- pragma translate_off
bootmsg : report_version
generic map ("pci_mt" & tost(hslvndx) &
": Simple 32-bit PCI Bridge, rev " & tost(REVISION) &
", " & tost(2**abits/2**20) & " Mbyte PCI memory BAR" );
-- pragma translate_on
end generate;
tgtonly : if MASTER = 0 generate
ahbmst0 : ahbmst generic map (hindex => hmstndx, devid => GAISLER_PCITRG)
port map (rst, clk, dmai, dmao, ahbmi, ahbmo);
-- pragma translate_off
bootmsg : report_version
generic map ("pci_mt" & tost(hmstndx) &
": Simple 32-bit Bridge, target-only, rev " & tost(REVISION) &
", " & tost(2**abits/2**20) & " Mbyte PCI memory BAR" );
-- pragma translate_on
end generate;
end;
| mit | 0b8301b96fa5b1788ace0082ed84df33 | 0.558923 | 2.917584 | false | false | false | false |
impedimentToProgress/UCI-BlueChip | AttackFiles/Attacks/privEsc/lib/gaisler/leon3/mmutw.vhd | 2 | 8,278 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: mmutw
-- File: mmutw.vhd
-- Author: Konrad Eisele, Jiri Gaisler, Gaisler Research
-- Description: MMU table-walk logic
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
library gaisler;
use gaisler.libiu.all;
use gaisler.libcache.all;
use gaisler.leon3.all;
use gaisler.mmuconfig.all;
use gaisler.mmuiface.all;
entity mmutw is
port (
rst : in std_logic;
clk : in std_logic;
mmctrl1 : in mmctrl_type1;
twi : in mmutw_in_type;
two : out mmutw_out_type;
mcmmo : in memory_mm_out_type;
mcmmi : out memory_mm_in_type
);
end mmutw;
architecture rtl of mmutw is
type write_buffer_type is record -- write buffer
addr, data : std_logic_vector(31 downto 0);
read : std_logic;
end record;
type states is (idle, waitm, pte, lv1, lv2, lv3, lv4);
type tw_rtype is record
state : states;
wb : write_buffer_type;
req : std_logic;
walk_op : std_logic;
--#dump
-- pragma translate_off
finish : std_logic;
index : std_logic_vector(31-2 downto 0);
lvl : std_logic_vector(1 downto 0);
fault_mexc : std_logic;
fault_trans : std_logic;
fault_lvl : std_logic_vector(1 downto 0);
pte,ptd,inv,rvd : std_logic;
goon, found : std_logic;
base : std_logic_vector(31 downto 0);
-- pragma translate_on
end record;
signal c,r : tw_rtype;
begin
p0: process (rst, r, c, twi, mcmmo, mmctrl1)
variable v : tw_rtype;
variable finish : std_logic;
variable index : std_logic_vector(31-2 downto 0);
variable lvl : std_logic_vector(1 downto 0);
variable fault_mexc : std_logic;
variable fault_trans : std_logic;
variable fault_inv : std_logic;
variable fault_lvl : std_logic_vector(1 downto 0);
variable pte,ptd,inv,rvd : std_logic;
variable goon, found : std_logic;
variable base : std_logic_vector(31 downto 0);
begin
v := r;
--#init
finish := '0';
index := (others => '0');
lvl := (others => '0');
fault_mexc := '0';
fault_trans := '0';
fault_inv := '0';
fault_lvl := (others => '0');
pte := '0';ptd := '0';inv := '0';rvd := '0';
goon := '0'; found := '0';
base := (others => '0');
base(PADDR_PTD_U downto PADDR_PTD_D) := mcmmo.data(PTD_PTP32_U downto PTD_PTP32_D);
if mcmmo.grant = '1' then
v.req := '0';
end if;
if mcmmo.retry = '1' then v.req := '1'; end if;
-- # pte/ptd
if ((mcmmo.ready and not r.req)= '1') then -- context
case mcmmo.data(PT_ET_U downto PT_ET_D) is
when ET_INV => inv := '1';
when ET_PTD => ptd := '1'; goon := '1';
when ET_PTE => pte := '1'; found := '1';
when ET_RVD => rvd := '1'; null;
when others => null;
end case;
end if;
fault_trans := (rvd);
fault_inv := inv;
-- # state machine
case r.state is
when idle =>
if (twi.walk_op_ur) = '1' then
v.walk_op := '1';
index(M_CTX_SZ-1 downto 0) := mmctrl1.ctx;
base := (others => '0');
base(PADDR_PTD_U downto PADDR_PTD_D) := mmctrl1.ctxp(MMCTRL_PTP32_U downto MMCTRL_PTP32_D);
v.wb.addr := base or (index&"00");
v.wb.read := '1';
v.req := '1';
v.state := lv1;
elsif (twi.areq_ur) = '1' then
index := (others => '0');
v.wb.addr := twi.aaddr;
v.wb.data := twi.adata;
v.wb.read := '0';
v.req := '1';
v.state := waitm;
end if;
when waitm =>
if ((mcmmo.ready and not r.req)= '1') then -- amba: result ready current cycle
fault_mexc := mcmmo.mexc;
v.state := idle;
finish := '1';
end if;
when lv1 =>
if ((mcmmo.ready and not r.req)= '1') then
lvl := LVL_CTX; fault_lvl := FS_L_CTX;
index(VA_I1_SZ-1 downto 0) := twi.data(VA_I1_U downto VA_I1_D);
v.state := lv2;
end if;
when lv2 =>
if ((mcmmo.ready and not r.req)= '1') then
lvl := LVL_REGION; fault_lvl := FS_L_L1;
index(VA_I2_SZ-1 downto 0) := twi.data(VA_I2_U downto VA_I2_D);
v.state := lv3;
end if;
when lv3 =>
if ((mcmmo.ready and not r.req)= '1') then
lvl := LVL_SEGMENT; fault_lvl := FS_L_L2;
index(VA_I3_SZ-1 downto 0) := twi.data(VA_I3_U downto VA_I3_D);
v.state := lv4;
end if;
when lv4 =>
if ((mcmmo.ready and not r.req)= '1') then
lvl := LVL_PAGE; fault_lvl := FS_L_L3;
fault_trans := fault_trans or ptd;
v.state := idle;
finish := '1';
end if;
when others =>
v.state := idle;
finish := '0';
end case;
base := base or (index&"00");
if r.walk_op = '1' then
if (mcmmo.ready and (not r.req)) = '1' then
fault_mexc := mcmmo.mexc;
if (( ptd and
(not fault_mexc ) and
(not fault_trans) and
(not fault_inv )) = '1') then -- tw : break table walk?
v.wb.addr := base;
v.req := '1';
else
v.walk_op := '0';
finish := '1';
v.state := idle;
end if;
end if;
end if;
-- # reset
if ( rst = '0' ) then
v.state := idle;
v.req := '0';
v.walk_op := '0';
v.wb.read := '0';
end if;
--# drive signals
two.finish <= finish;
two.data <= mcmmo.data;
two.addr <= r.wb.addr(31 downto 0);
two.lvl <= lvl;
two.fault_mexc <= fault_mexc;
two.fault_trans <= fault_trans;
two.fault_inv <= fault_inv;
two.fault_lvl <= fault_lvl;
mcmmi.address <= r.wb.addr;
mcmmi.data <= r.wb.data;
mcmmi.burst <= '0';
mcmmi.size <= "10";
mcmmi.read <= r.wb.read;
mcmmi.lock <= '0';
mcmmi.req <= r.req;
--#dump
-- pragma translate_off
v.finish := finish;
v.index := index;
v.lvl := lvl;
v.fault_mexc := fault_mexc;
v.fault_trans := fault_trans;
v.fault_lvl := fault_lvl;
v.pte := pte;
v.ptd := ptd;
v.inv := inv;
v.rvd := rvd;
v.goon := goon;
v.found := found;
v.base := base;
-- pragma translate_on
c <= v;
end process p0;
p1: process (clk)
begin if rising_edge(clk) then r <= c; end if;
end process p1;
end rtl;
| mit | d8e2dfda411560e2cd483a5585f3f8e4 | 0.476444 | 3.551266 | false | false | false | false |
cafe-alpha/wascafe | v13/wasca_10m08scv4k_no_spi_20190420/wasca_tb.vhd | 1 | 13,705 | -- Test bench
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
library work;
use work.ALL;
entity wasca_tb is
end entity wasca_tb;
architecture SIMULATE of wasca_tb is
-- Clock
signal clk_clk : std_logic ;
-- SDRAM
signal external_sdram_controller_wire_addr : std_logic_vector(12 downto 0);
signal external_sdram_controller_wire_ba : std_logic_vector( 1 downto 0);
signal external_sdram_controller_wire_cas_n : std_logic ;
signal external_sdram_controller_wire_cke : std_logic ;
signal external_sdram_controller_wire_cs_n : std_logic ;
signal external_sdram_controller_wire_dq : std_logic_vector(15 downto 0);
signal external_sdram_controller_wire_dqm : std_logic_vector( 1 downto 0);
signal external_sdram_controller_wire_ras_n : std_logic ;
signal external_sdram_controller_wire_we_n : std_logic ;
signal external_sdram_clk_pin : std_logic ;
-- Reset signal from Saturn
signal reset_reset_n : std_logic ;
-- A-Bus
signal abus_slave_0_abus_address : std_logic_vector(25 downto 16);
signal abus_slave_0_abus_addressdata : std_logic_vector(15 downto 0);
signal abus_slave_0_abus_chipselect : std_logic_vector( 2 downto 0);
signal abus_slave_0_abus_read : std_logic ;
signal abus_slave_0_abus_write : std_logic_vector( 1 downto 0);
signal abus_slave_0_abus_waitrequest : std_logic ;
signal abus_slave_0_abus_interrupt : std_logic ;
signal abus_slave_0_abus_disableout : std_logic ;
signal abus_slave_0_abus_muxing : std_logic_vector( 1 downto 0);
signal abus_slave_0_abus_direction : std_logic ;
-- SPI for SD card
--signal spi_sd_card_MISO : std_logic ;
--signal spi_sd_card_MOSI : std_logic ;
--signal spi_sd_card_SCLK : std_logic ;
--signal spi_sd_card_SS_n : std_logic ;
-- UART (FT232RL)
signal uart_0_external_connection_txd : std_logic ;
signal uart_0_external_connection_rxd : std_logic ;
-- LEDs
signal leds_conn_export : std_logic_vector( 2 downto 0);
-- Switches
signal switches_conn_export : std_logic_vector( 2 downto 0);
-- SPI for STM32
signal spi_stm32_MISO : std_logic ;
signal spi_stm32_MOSI : std_logic ;
signal spi_stm32_SCLK : std_logic ;
signal spi_stm32_SS_n : std_logic ;
-- Audio output
--signal audio_out_BCLK : std_logic ;
--signal audio_out_DACDAT : std_logic ;
--signal audio_out_DACLRCK : std_logic ;
--signal audio_SSEL : std_logic ;
-- constant values
constant clk_in_t : time := 44.289 ns; -- SCSPCLK : 22.579 MHz -> 44.288941051419 ns
begin -- architecture SIMULATE
-- component instantiation
uut: entity work.wasca_toplevel
port map
(
clk_clk => clk_clk , -- in std_logic -- Saturn clock (22.579 MHz)
external_sdram_controller_wire_addr => external_sdram_controller_wire_addr , -- out std_logic_vector(12 downto 0); -- external_sdram_controller_wire.addr
external_sdram_controller_wire_ba => external_sdram_controller_wire_ba , -- out std_logic_vector( 1 downto 0); -- .ba
external_sdram_controller_wire_cas_n => external_sdram_controller_wire_cas_n , -- out std_logic -- .cas_n
external_sdram_controller_wire_cke => external_sdram_controller_wire_cke , -- out std_logic -- .cke
external_sdram_controller_wire_cs_n => external_sdram_controller_wire_cs_n , -- out std_logic -- .cs_n
external_sdram_controller_wire_dq => external_sdram_controller_wire_dq , -- inout std_logic_vector(15 downto 0) -- .dq
external_sdram_controller_wire_dqm => external_sdram_controller_wire_dqm , -- out std_logic_vector( 1 downto 0); -- .dqm
external_sdram_controller_wire_ras_n => external_sdram_controller_wire_ras_n , -- out std_logic -- .ras_n
external_sdram_controller_wire_we_n => external_sdram_controller_wire_we_n , -- out std_logic -- .we_n
external_sdram_clk_pin => external_sdram_clk_pin , -- out std_logic -- .clk
reset_reset_n => reset_reset_n , -- in std_logic -- Saturn reset, power on.
abus_slave_0_abus_address => abus_slave_0_abus_address , -- in std_logic_vector(25 downto 16) -- abus_slave_0_abus.address
abus_slave_0_abus_addressdata => abus_slave_0_abus_addressdata , -- inout std_logic_vector(15 downto 0) -- .data
abus_slave_0_abus_chipselect => abus_slave_0_abus_chipselect , -- in std_logic_vector( 2 downto 0) -- .chipselect
abus_slave_0_abus_read => abus_slave_0_abus_read , -- in std_logic -- .read
abus_slave_0_abus_write => abus_slave_0_abus_write , -- in std_logic_vector( 1 downto 0) -- .write
abus_slave_0_abus_waitrequest => abus_slave_0_abus_waitrequest , -- out std_logic -- .waitrequest
abus_slave_0_abus_interrupt => abus_slave_0_abus_interrupt , -- out std_logic -- .interrupt
abus_slave_0_abus_disableout => abus_slave_0_abus_disableout , -- out std_logic -- .muxing
abus_slave_0_abus_muxing => abus_slave_0_abus_muxing , -- out std_logic_vector( 1 downto 0) -- .muxing
abus_slave_0_abus_direction => abus_slave_0_abus_direction , -- out std_logic -- .direction
--spi_sd_card_MISO => spi_sd_card_MISO , -- in std_logic -- MISO
--spi_sd_card_MOSI => spi_sd_card_MOSI , -- out std_logic -- MOSI
--spi_sd_card_SCLK => spi_sd_card_SCLK , -- out std_logic -- SCLK
--spi_sd_card_SS_n => spi_sd_card_SS_n , -- out std_logic -- SS_n
uart_0_external_connection_txd => uart_0_external_connection_txd , -- out std_logic --
uart_0_external_connection_rxd => uart_0_external_connection_rxd , -- in std_logic --
leds_conn_export => leds_conn_export , -- out std_logic_vector( 2 downto 0); -- leds_conn_export[0]: ledr1, leds_conn_export[1]: ledg1, leds_conn_export[2]: ledr2
switches_conn_export => switches_conn_export , -- in std_logic_vector( 2 downto 0); -- switches_conn_export[0]: sw1, switches_conn_export[1]: sw2, switches_conn_export[2]: STM32 SPI synchronization
spi_stm32_MISO => spi_stm32_MISO , -- in std_logic -- MISO
spi_stm32_MOSI => spi_stm32_MOSI , -- out std_logic -- MOSI
spi_stm32_SCLK => spi_stm32_SCLK , -- out std_logic -- SCLK
spi_stm32_SS_n => spi_stm32_SS_n -- out std_logic -- SS_n
--audio_out_BCLK => audio_out_BCLK , -- in std_logic -- BCLK
--audio_out_DACDAT => audio_out_DACDAT , -- out std_logic -- DACDAT
--audio_out_DACLRCK => audio_out_DACLRCK , -- in std_logic -- DACLRCK
--audio_SSEL => audio_SSEL , -- out std_logic --
);
process is
begin -- process
-- Activate sysres signal on startup
reset_reset_n <= '0';
wait for 350 ns;
reset_reset_n <= '1';
wait for 999999 ns;
end process;
process is
begin -- SCSPCLK
clk_clk <= '0';
wait for clk_in_t / 2;
clk_clk <= '1';
wait for clk_in_t / 2;
end process;
-- process is
-- begin -- process
-- -- Dummy values for dout
-- io_sd_dout <= '0';
-- wait for 250 ns;
-- io_sd_dout <= '1';
-- wait for 150 ns;
-- end process;
process is
begin -- process
-- Test switchs always to '1'
switches_conn_export(0) <= '1';
switches_conn_export(1) <= '1';
switches_conn_export(2) <= '1';
wait for clk_in_t * 2;
end process;
-- process is
-- begin -- process
-- -- Beg for hardware version
-- io_address <= "001";
-- io_data <= "ZZZZZZZZ";
-- io_oe_al <= '0';
-- io_rd_al <= '0';
-- io_wr0 <= '0';
-- io_wr1 <= '0';
-- io_sd_adr <= '0';
--
--
--
--
-- wait for 50 ns;
-- io_wr0 <= '0';
-- io_wr1 <= '1';
-- wait for 50 ns;
-- io_wr0 <= '1';
-- io_wr1 <= '0';
--
-- -- Beg for dout pin state
-- io_address <= "000";
-- wait for 140 ns;
-- io_wr0 <= '1';
-- io_wr1 <= '1';
--
-- wait for 120 ns;
--
-- -- Write to CS/DIN/CLK pins
-- io_address <= "000";
-- io_data <= "00000111";
-- io_oe_al <= '1';
-- io_rd_al <= '1';
-- wait for 80 ns;
-- io_data <= "00000101";
-- wait for 80 ns;
-- io_data <= "00000100";
-- wait for 80 ns;
-- io_data <= "00000001";
--
--
-- wait for 700 ns;
-- end process;
-- process is
-- begin -- process
-- -- Ask for build date #1
-- io_up_addr <= "0110"; -- SD card
-- io_address <= "00000"; -- CPLD version
-- io_data <= "ZZZZZZZZZZZZZZZZ";
-- io_cs0_al <= '0';
-- io_rd_al <= '0';
-- io_wr0 <= '0';
-- io_wr1 <= '0';
-- wait for clk_in_t * 4;
--
-- -- Ask for build date #2
-- io_up_addr <= "0110"; -- SD card
-- io_address <= "00001"; -- CPLD version
-- io_data <= "ZZZZZZZZZZZZZZZZ";
-- io_cs0_al <= '0';
-- io_rd_al <= '0';
-- io_wr0 <= '0';
-- io_wr1 <= '0';
-- wait for clk_in_t * 4;
--
-- -- Ask for DOUT value
-- io_up_addr <= "0110"; -- SD card
-- io_address <= "01010"; -- DOUT read
-- io_data <= "ZZZZZZZZZZZZZZZZ";
-- io_cs0_al <= '0';
-- io_rd_al <= '0';
-- io_wr0 <= '0';
-- io_wr1 <= '0';
-- wait for clk_in_t * 4;
--
-- -- Set DIN/CS/CLK
-- io_up_addr <= "0110"; -- SD card
-- io_address <= "01000"; -- CS/DIN/CLK set
-- io_data <= "0000000000000100";
-- io_cs0_al <= '0';
-- io_rd_al <= '1';
-- io_wr0 <= '1';
-- io_wr1 <= '1';
-- wait for clk_in_t * 4;
-- -- Set DIN/CS/CLK
-- io_up_addr <= "0110"; -- SD card
-- io_address <= "01000"; -- CS/DIN/CLK set
-- io_data <= "0000000000000010";
-- io_cs0_al <= '0';
-- io_rd_al <= '1';
-- io_wr0 <= '1';
-- io_wr1 <= '1';
-- wait for clk_in_t * 4;
--
-- end process;
end architecture SIMULATE;
-------------------------------------------------------------------------------
--
-- -- Configuration for simulation
-- library work;
-- configuration wasca_tb_cfg of wasca_tb is
-- for SIMULATE
-- -- for DUTC : wasca_tb
-- -- use entity work.wasca(structure);
-- -- end for;
-- end for;
-- end wasca_tb_cfg;
| gpl-2.0 | 54e6b7f2c90c0c89dbf3389dfc3d3381 | 0.4305 | 3.869283 | false | false | false | false |
impedimentToProgress/UCI-BlueChip | AttackFiles/Attacks/privEsc/lib/techmap/proasic3/buffer_apa3.vhd | 2 | 2,154 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: clkbuf_actel
-- File: clkbuf_actel.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: Clock buffer generator for Actel devices
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
-- pragma translate_off
library proasic3;
use proasic3.clkint;
-- pragma translate_on
entity clkbuf_apa3 is
generic(
buftype : integer range 0 to 3 := 0);
port(
i : in std_ulogic;
o : out std_ulogic
);
end entity;
architecture rtl of clkbuf_apa3 is
signal o2, no2, nin : std_ulogic;
component clkint port(a : in std_ulogic; y : out std_ulogic); end component;
attribute syn_maxfan : integer;
attribute syn_maxfan of o2 : signal is 10000;
begin
o <= o2;
buf0 : if buftype = 0 generate
o2 <= i;
end generate;
buf1 : if buftype = 1 generate
buf : clkint port map(A => i, Y => o2);
end generate;
buf2 : if buftype = 2 generate
buf : clkint port map(A => i, Y => o2);
end generate;
buf3 : if buftype > 2 generate
nin <= not i;
buf : clkint port map(A => nin, Y => no2);
o2 <= not no2;
end generate;
end architecture;
| mit | e03f74e4c73dcd3c76059614e5a8056d | 0.609099 | 3.988889 | false | false | false | false |
SteffenReith/J1Sc | src/main/vhdl/arch/Nexys4/Board_Nexys4.vhd | 1 | 3,808 | --------------------------------------------------------------------------------
--
-- Creation Date: Sat May 6 16:30:50 GMT+2 2017
-- Creator: Steffen Reith
-- Module Name: Board_Nexys4 - Behavioral
-- Project Name: J1Sc - A simple J1 implementation in Scala using Spinal HDL
--
-- Remark: The pmod pins are renumberd as follows 1 -> 0, 2 -> 1, 3 -> 2,
-- 4 -> 3, 7 -> 4, 8 -> 5, 9 -> 6, 10 -> 7
--
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity Board_Nexys4 is
port (nreset : in std_logic;
clk100Mhz : in std_logic;
extInt : in std_logic_vector(0 downto 0);
leds : out std_logic_vector(15 downto 0);
rgbLeds : out std_logic_vector(5 downto 0);
segments_a : out std_logic;
segments_b : out std_logic;
segments_c : out std_logic;
segments_d : out std_logic;
segments_e : out std_logic;
segments_f : out std_logic;
segments_g : out std_logic;
dot : out std_logic;
selector : out std_logic_vector(7 downto 0);
pmodA : inout std_logic_vector(7 downto 0);
sSwitches : in std_logic_vector(15 downto 0);
pButtons : in std_logic_vector(4 downto 0);
tck : in std_logic;
tms : in std_logic;
tdi : in std_logic;
tdo : out std_logic;
rx : in std_logic;
tx : out std_logic);
end Board_Nexys4;
architecture Structural of Board_Nexys4 is
-- Positive reset signal
signal reset : std_logic;
-- Signals related to the board clk
signal boardClk : std_logic;
signal boardClkLocked : std_logic;
-- Interface for PModA
signal pmodA_read : std_logic_vector(7 downto 0);
signal pmodA_write : std_logic_vector(7 downto 0);
signal pmodA_writeEnable : std_logic_vector(7 downto 0);
begin
-- Instantiate a PLL/MMCM (makes a 80Mhz clock)
makeClk : entity work.PLL(Structural)
port map (clkIn => clk100Mhz,
clkOut => boardClk,
isLocked => boardClkLocked);
-- Make the reset high active
reset <= not nreset;
-- Instantiate the J1SoC core created by Spinal
core : entity work.J1Nexys4X
port map (reset => reset,
boardClk => boardClk,
boardClkLocked => boardClkLocked,
extInt => extInt,
leds => leds,
rgbLeds => rgbLeds,
segments_a => segments_a,
segments_b => segments_b,
segments_c => segments_c,
segments_d => segments_d,
segments_e => segments_e,
segments_f => segments_f,
segments_g => segments_g,
dot => dot,
selector => selector,
pmodA_read => pmodA_read,
pmodA_write => pmodA_write,
pmodA_writeEnable => pmodA_writeEnable,
sSwitches => sSwitches,
pButtons => pButtons,
tck => tck,
tms => tms,
tdi => tdi,
tdo => tdo,
rx => rx,
tx => tx);
-- Connect the pmodA read port
pmodA_read <= pmodA;
-- generate the write port and equip it with tristate functionality
pmodAGen : for i in pmodA'range generate
pmodA(i) <= pmodA_write(i) when pmodA_writeEnable(i) = '1' else 'Z';
end generate;
end architecture;
| bsd-3-clause | 9a20ca0cf862dcaefceaff21aa559b96 | 0.483718 | 4.051064 | false | false | false | false |
impedimentToProgress/UCI-BlueChip | AttackFiles/Attacks/privEsc/lib/techmap/unisim/ssrctrl_unisim.vhd | 1 | 177,138 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
--
-----------------------------------------------------------------------------
-- Entity: ssrctrl_unisim
-- file: ssrctrl_unisim.vhd
-- Description: 32-bit SSRAM memory controller with PROM 16-bit bus support
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library unisim;
use unisim.vcomponents.all;
entity ssrctrl_unisim is
port(
rst : in std_logic;
clk : in std_logic;
n_ahbsi_hsel : in std_logic_vector (0 to 15);
n_ahbsi_haddr : in std_logic_vector (31 downto 0);
n_ahbsi_hwrite : in std_logic;
n_ahbsi_htrans : in std_logic_vector (1 downto 0);
n_ahbsi_hsize : in std_logic_vector (2 downto 0);
n_ahbsi_hburst : in std_logic_vector (2 downto 0);
n_ahbsi_hwdata : in std_logic_vector (31 downto 0);
n_ahbsi_hprot : in std_logic_vector (3 downto 0);
n_ahbsi_hready : in std_logic;
n_ahbsi_hmaster : in std_logic_vector (3 downto 0);
n_ahbsi_hmastlock : in std_logic;
n_ahbsi_hmbsel : in std_logic_vector (0 to 3);
n_ahbsi_hcache : in std_logic;
n_ahbsi_hirq : in std_logic_vector (31 downto 0);
n_ahbso_hready : out std_logic;
n_ahbso_hresp : out std_logic_vector (1 downto 0);
n_ahbso_hrdata : out std_logic_vector (31 downto 0);
n_ahbso_hsplit : out std_logic_vector (15 downto 0);
n_ahbso_hcache : out std_logic;
n_ahbso_hirq : out std_logic_vector (31 downto 0);
n_apbi_psel : in std_logic_vector (0 to 15);
n_apbi_penable : in std_logic;
n_apbi_paddr : in std_logic_vector (31 downto 0);
n_apbi_pwrite : in std_logic;
n_apbi_pwdata : in std_logic_vector (31 downto 0);
n_apbi_pirq : in std_logic_vector (31 downto 0);
n_apbo_prdata : out std_logic_vector (31 downto 0);
n_apbo_pirq : out std_logic_vector (31 downto 0);
n_sri_data : in std_logic_vector (31 downto 0);
n_sri_brdyn : in std_logic;
n_sri_bexcn : in std_logic;
n_sri_writen : in std_logic;
n_sri_wrn : in std_logic_vector (3 downto 0);
n_sri_bwidth : in std_logic_vector (1 downto 0);
n_sri_sd : in std_logic_vector (63 downto 0);
n_sri_cb : in std_logic_vector (7 downto 0);
n_sri_scb : in std_logic_vector (7 downto 0);
n_sri_edac : in std_logic;
n_sro_address : out std_logic_vector (31 downto 0);
n_sro_data : out std_logic_vector (31 downto 0);
n_sro_sddata : out std_logic_vector (63 downto 0);
n_sro_ramsn : out std_logic_vector (7 downto 0);
n_sro_ramoen : out std_logic_vector (7 downto 0);
n_sro_ramn : out std_logic;
n_sro_romn : out std_logic;
n_sro_mben : out std_logic_vector (3 downto 0);
n_sro_iosn : out std_logic;
n_sro_romsn : out std_logic_vector (7 downto 0);
n_sro_oen : out std_logic;
n_sro_writen : out std_logic;
n_sro_wrn : out std_logic_vector (3 downto 0);
n_sro_bdrive : out std_logic_vector (3 downto 0);
n_sro_vbdrive : out std_logic_vector (31 downto 0);
n_sro_svbdrive : out std_logic_vector (63 downto 0);
n_sro_read : out std_logic;
n_sro_sa : out std_logic_vector (14 downto 0);
n_sro_cb : out std_logic_vector (7 downto 0);
n_sro_scb : out std_logic_vector (7 downto 0);
n_sro_vcdrive : out std_logic_vector (7 downto 0);
n_sro_svcdrive : out std_logic_vector (7 downto 0);
n_sro_ce : out std_logic);
end ssrctrl_unisim;
--
library ieee;
use ieee.std_logic_1164.all;
library unisim;
use unisim.vcomponents.all;
entity ssrctrl_unisim_netlist is
port(
n_sro_vbdrive : out std_logic_vector (31 downto 0);
n_ahbso_hrdata : out std_logic_vector (31 downto 0);
iows_0 : out std_logic;
iows_3 : out std_logic;
romwws_0 : out std_logic;
romwws_3 : out std_logic;
romrws_0 : out std_logic;
romrws_3 : out std_logic;
NoName_cnst : in std_logic_vector (0 downto 0);
n_sri_bwidth : in std_logic_vector (1 downto 0);
n_apbi_pwdata_19 : in std_logic;
n_apbi_pwdata_11 : in std_logic;
n_apbi_pwdata_9 : in std_logic;
n_apbi_pwdata_8 : in std_logic;
n_apbi_pwdata_23 : in std_logic;
n_apbi_pwdata_22 : in std_logic;
n_apbi_pwdata_21 : in std_logic;
n_apbi_pwdata_20 : in std_logic;
n_apbi_pwdata_3 : in std_logic;
n_apbi_pwdata_2 : in std_logic;
n_apbi_pwdata_1 : in std_logic;
n_apbi_pwdata_0 : in std_logic;
n_apbi_pwdata_7 : in std_logic;
n_apbi_pwdata_6 : in std_logic;
n_apbi_pwdata_5 : in std_logic;
n_apbi_pwdata_4 : in std_logic;
n_apbi_psel : in std_logic_vector (0 downto 0);
n_apbi_paddr : in std_logic_vector (5 downto 2);
n_apbo_prdata_0 : out std_logic;
n_apbo_prdata_4 : out std_logic;
n_apbo_prdata_20 : out std_logic;
n_apbo_prdata_23 : out std_logic;
n_apbo_prdata_22 : out std_logic;
n_apbo_prdata_21 : out std_logic;
n_apbo_prdata_19 : out std_logic;
n_apbo_prdata_7 : out std_logic;
n_apbo_prdata_6 : out std_logic;
n_apbo_prdata_5 : out std_logic;
n_apbo_prdata_3 : out std_logic;
n_apbo_prdata_2 : out std_logic;
n_apbo_prdata_1 : out std_logic;
n_apbo_prdata_11 : out std_logic;
n_apbo_prdata_9 : out std_logic;
n_apbo_prdata_8 : out std_logic;
n_apbo_prdata_28 : out std_logic;
n_sro_romsn : out std_logic_vector (0 downto 0);
n_ahbsi_hsel : in std_logic_vector (0 downto 0);
prstate_fast : out std_logic_vector (2 downto 2);
n_ahbsi_htrans : in std_logic_vector (1 downto 0);
ssrstate_1_m1 : inout std_logic_vector (4 downto 3) := (others => 'Z');
hsel_1 : in std_logic_vector (0 downto 0);
hmbsel_4 : out std_logic_vector (1 downto 1);
n_sro_bdrive : out std_logic_vector (3 downto 3);
ws_1_0 : in std_logic;
ws_1_3 : in std_logic;
ws : out std_logic_vector (3 downto 0);
ssrstate_1_2 : in std_logic;
n_ahbsi_haddr : in std_logic_vector (31 downto 0);
n_ahbsi_hmbsel : in std_logic_vector (2 downto 0);
n_sri_data : in std_logic_vector (31 downto 0);
ssrstate : out std_logic_vector (4 downto 0);
n_ahbsi_hwdata : in std_logic_vector (31 downto 0);
n_ahbsi_hsize : in std_logic_vector (1 downto 0);
size : out std_logic_vector (1 downto 0);
n_sro_data : out std_logic_vector (31 downto 0);
n_sro_ramsn : out std_logic_vector (0 downto 0);
n_sro_wrn : out std_logic_vector (3 downto 0);
haddr_0 : in std_logic;
bwn_1_0_o3_0 : in std_logic;
hsize_1 : in std_logic_vector (1 downto 1);
prstate_1_i_o4_s : in std_logic_vector (2 downto 2);
prstate : out std_logic_vector (5 downto 0);
hmbsel : out std_logic_vector (2 downto 0);
n_sro_address : out std_logic_vector (31 downto 0);
hready_2 : in std_logic;
n_ahbso_hready : out std_logic;
ssrhready_8 : in std_logic;
loadcount : out std_logic;
n_sro_writen : out std_logic;
ssrstatec : in std_logic;
prhready : out std_logic;
d_m2_0_a2_0 : in std_logic;
ssrstate17_2_0_m6_i_a3_a2 : out std_logic;
N_319_1 : out std_logic;
ws_0_sqmuxa_c : out std_logic;
N_365 : in std_logic;
ws_0_sqmuxa_0_c : out std_logic;
ws_2_sqmuxa_3_0_4 : out std_logic;
change_1_sqmuxa_0 : in std_logic;
d16mux_0_sqmuxa : in std_logic;
ssrstate_2_sqmuxa_1 : in std_logic;
un7_bus16en : in std_logic;
N_646 : in std_logic;
loadcount_1_sqmuxa : in std_logic;
ssrstate_1_sqmuxa_1_0_m3_0_1 : out std_logic;
n_apbi_penable : in std_logic;
n_apbi_pwrite : in std_logic;
d_m1_e_0_0 : in std_logic;
hsel_1_0_L3 : out std_logic;
ssrhready_8_f0_L8 : out std_logic;
ssrstate_1_sqmuxa_1 : in std_logic;
ssrhready : out std_logic;
ssrhready_8_f0_L5 : out std_logic;
ssrstate17_1_xx_mm_N_4 : in std_logic;
ws_1_sqmuxa : out std_logic;
ws_4_sqmuxa_0 : in std_logic;
ws_2_sqmuxa_0 : in std_logic;
ssrstate17_2_0_m6_i_1 : out std_logic;
ws_2_sqmuxa_3_0_x : out std_logic;
ws_3_sqmuxa_1 : out std_logic;
ws_2_sqmuxa_3_0_2 : out std_logic;
ssrstate_2_i : out std_logic;
ws_2_sqmuxa_3_d : out std_logic;
ws_0_sqmuxa_1 : out std_logic;
g0_30 : in std_logic;
hsel_4 : in std_logic;
n_ahbsi_hready : in std_logic;
hsel : out std_logic;
g0_25 : in std_logic;
bwn_0_sqmuxa_1 : in std_logic;
prstate_2_rep1 : out std_logic;
N_662 : out std_logic;
ssrstate_6_sqmuxa : out std_logic;
g0_52_x1 : in std_logic;
g0_52_x0 : in std_logic;
ssrhready_2_sqmuxa_0_0 : out std_logic;
change_1_sqmuxa_N_3 : out std_logic;
ssrstate6_xx_mm_m3 : out std_logic;
ssrstate6_1_d_0_L1 : out std_logic;
N_656 : out std_logic;
hsel_5 : out std_logic;
change_3_f0 : in std_logic;
un1_ahbsi : out std_logic;
change : out std_logic;
n_ahbsi_hwrite : in std_logic;
N_574_i : in std_logic;
n_sro_iosn : out std_logic;
N_618_i : in std_logic;
clk : in std_logic;
n_sro_oen : out std_logic;
rst : in std_logic;
bwn_1_sqmuxa_2_d : in std_logic;
bwn_1_sqmuxa_2_d_0_2 : in std_logic;
ssrstate_2_sqmuxa_i : in std_logic;
g0_23 : in std_logic;
N_371 : out std_logic;
loadcount_7 : in std_logic;
bus16en : out std_logic;
d16muxc_0_4 : out std_logic;
change_3_f1_d_0_0 : in std_logic;
g0_1_0 : in std_logic;
g0_44 : in std_logic);
end ssrctrl_unisim_netlist;
architecture beh of ssrctrl_unisim_netlist is
signal ACOUNT_QXU : std_logic_vector (9 downto 1);
signal ACOUNT_LM_0_1 : std_logic_vector (0 to 0);
signal ACOUNT_LM : std_logic_vector (9 downto 0);
signal WS_1_0_BM : std_logic_vector (1 to 1);
signal WS_1_0_RN_1 : std_logic_vector (1 to 1);
signal WS_1 : std_logic_vector (2 downto 1);
signal SSRSTATE_1_0_D_BM : std_logic_vector (3 to 3);
signal SSRSTATE_1_0_1 : std_logic_vector (3 to 3);
signal SSRSTATE_1 : std_logic_vector (3 downto 2);
signal BWN_1_0_O3 : std_logic_vector (1 to 1);
signal PRSTATE_I : std_logic_vector (1 to 1);
signal HWDATAOUT_1 : std_logic_vector (31 downto 0);
signal ROMWIDTH : std_logic_vector (1 downto 0);
signal ROMWIDTH_1 : std_logic_vector (1 downto 0);
signal DATA16 : std_logic_vector (15 downto 0);
signal HRDATA : std_logic_vector (31 downto 0);
signal HWDATA : std_logic_vector (31 downto 0);
signal HADDR : std_logic_vector (11 downto 2);
signal SSRSTATE_1_0_D_AM : std_logic_vector (3 to 3);
signal HMBSEL_4_X1 : std_logic_vector (1 to 1);
signal WS_1_2_0_D : std_logic_vector (2 downto 1);
signal WS_1_0_AM_1 : std_logic_vector (1 to 1);
signal BWN_1_0_0 : std_logic_vector (3 to 3);
signal IOWS_1 : std_logic_vector (3 downto 0);
signal ACOUNT_S : std_logic_vector (9 downto 1);
signal SSRSTATE_11 : std_logic_vector (0 to 0);
signal SSRSTATE23_U_0_AM : std_logic_vector (4 to 4);
signal SSRSTATE23_U_0_BM : std_logic_vector (4 to 4);
signal ROMRWS : std_logic_vector (2 downto 1);
signal IOWS : std_logic_vector (2 downto 1);
signal ROMWWS : std_logic_vector (2 downto 1);
signal D16MUX : std_logic_vector (1 downto 0);
signal ACOUNT_CRY : std_logic_vector (8 downto 1);
signal ROMSN_1_IV_L1 : std_logic ;
signal CHANGE_3 : std_logic ;
signal ROMSN_1 : std_logic ;
signal PRHREADY_6 : std_logic ;
signal N_635_I_1 : std_logic ;
signal N_635_I : std_logic ;
signal D16MUXC_0_1 : std_logic ;
signal D16MUXC_0_1_0 : std_logic ;
signal D16MUXC_0_4_INT_73 : std_logic ;
signal D16MUXC_0 : std_logic ;
signal N_371_INT_71 : std_logic ;
signal WS_1_L1 : std_logic ;
signal WS_1_L1_0 : std_logic ;
signal SSRSTATE_1_M2S2_0 : std_logic ;
signal IOSN_9_IV_L1 : std_logic ;
signal PRSTATE_0_INT_27 : std_logic ;
signal IOSN_9 : std_logic ;
signal N_317 : std_logic ;
signal N_619_I_L1 : std_logic ;
signal N_619_I : std_logic ;
signal N_620_I : std_logic ;
signal PRSTATE_1_INT_28 : std_logic ;
signal RST_I : std_logic ;
signal OEN_1 : std_logic ;
signal OEN_1_SQMUXA_2_I : std_logic ;
signal BWN_1_SQMUXA_3_I : std_logic ;
signal N_617_I : std_logic ;
signal N_599_I : std_logic ;
signal SSRSTATE_9 : std_logic ;
signal BEXCEN_1_SQMUXA_I : std_logic ;
signal DATA16_0_SQMUXA : std_logic ;
signal HMBSEL_0_SQMUXA : std_logic ;
signal HWRITE : std_logic ;
signal SSRSTATE_1_INT_21 : std_logic ;
signal HMBSEL_0_INT_33 : std_logic ;
signal HMBSEL_2_INT_35 : std_logic ;
signal BDRIVE_1 : std_logic ;
signal N_SRO_ADDRESS_2_INT_38 : std_logic ;
signal N_SRO_ADDRESS_3_INT_39 : std_logic ;
signal N_SRO_ADDRESS_4_INT_40 : std_logic ;
signal N_SRO_ADDRESS_5_INT_41 : std_logic ;
signal N_SRO_ADDRESS_6_INT_42 : std_logic ;
signal N_SRO_ADDRESS_7_INT_43 : std_logic ;
signal N_SRO_ADDRESS_8_INT_44 : std_logic ;
signal N_SRO_ADDRESS_9_INT_45 : std_logic ;
signal N_SRO_ADDRESS_10_INT_46 : std_logic ;
signal OEN_1_SQMUXA_2_I_L4 : std_logic ;
signal PRSTATE_1 : std_logic ;
signal OEN_1_SQMUXA_2_I_L6 : std_logic ;
signal N_654 : std_logic ;
signal SSRSTATE_2_INT_22 : std_logic ;
signal SSRSTATE_12_1 : std_logic ;
signal WS_1_0_BM_L1 : std_logic ;
signal WS_1_0_BM_L3 : std_logic ;
signal UN1_AHBSI_INT_68 : std_logic ;
signal HSEL_5_INT_67 : std_logic ;
signal WS_1_0_BM_L5 : std_logic ;
signal HMBSEL_4_1_INT_14 : std_logic ;
signal N_619_I_L1_L1 : std_logic ;
signal SSRSTATE6_XX_MM_M3_INT_64 : std_logic ;
signal HMBSEL_1_INT_34 : std_logic ;
signal SSRSTATE_6_SQMUXA_1 : std_logic ;
signal N_SRO_ADDRESS_0_INT_36 : std_logic ;
signal SIZE_0_INT_25 : std_logic ;
signal BWN_1_0_O3_0_L1 : std_logic ;
signal BWN_1_0_O3_0_L3 : std_logic ;
signal BWN_1_0_O3_0_L5 : std_logic ;
signal PRSTATE_2_REP1_INT_59 : std_logic ;
signal PRSTATEC_0_REP1 : std_logic ;
signal N_336 : std_logic ;
signal PRSTATEC_0_FAST : std_logic ;
signal WS_1_INT_17 : std_logic ;
signal BDRIVE_1_IV_M9_I_A4_0_2_1 : std_logic ;
signal BDRIVE_1_IV_M9_I_A4_0_2_2_1 : std_logic ;
signal BDRIVE_0_SQMUXA_2_C : std_logic ;
signal BDRIVE_1_IV_M9_I_A4_0_2_2_L1 : std_logic ;
signal BDRIVE_1_TZ : std_logic ;
signal BDRIVE_1_IV_M9_I_A4_0_2_2_1_L1 : std_logic ;
signal N_SRO_BDRIVE_3_INT_15 : std_logic ;
signal BDRIVE_1_IV_M9_I_A4_0_2_2_1_L3 : std_logic ;
signal N_668 : std_logic ;
signal BDRIVE_1_SQMUXA : std_logic ;
signal N_662_INT_60 : std_logic ;
signal SSRSTATE6_XX_MM_M3_L1 : std_logic ;
signal PRSTATE_5_INT_32 : std_logic ;
signal SSRSTATE_4_INT_24 : std_logic ;
signal SSRSTATE6_XX_MM_M3_L3 : std_logic ;
signal WS_2_SQMUXA_3_0_SX : std_logic ;
signal WS_0_SQMUXA_1_INT_57 : std_logic ;
signal WS_2_SQMUXA_3_D_INT_56 : std_logic ;
signal SSRSTATE17_2_0_M6_I_A3_A0_1 : std_logic ;
signal CHANGE_3_F1_D_0_L1 : std_logic ;
signal CHANGE_INT_69 : std_logic ;
signal PRSTATE_2_INT_29 : std_logic ;
signal WRITEN_2_SQMUXA_L1 : std_logic ;
signal WRITEN_2_SQMUXA_L3 : std_logic ;
signal WRITEN_2_SQMUXA_L5 : std_logic ;
signal WRITEN_2_SQMUXA_TZ_0 : std_logic ;
signal BWN_1_SQMUXA_2_D_0 : std_logic ;
signal WRITEN_2_SQMUXA : std_logic ;
signal WS_3_SQMUXA_1_INT_53 : std_logic ;
signal WS_1_L1_L1 : std_logic ;
signal WS_2_INT_18 : std_logic ;
signal WS_2_SQMUXA_3_0_2_L1 : std_logic ;
signal WS_2_SQMUXA_3_0_2_INT_54 : std_logic ;
signal WS_0_INT_16 : std_logic ;
signal SSRSTATE_3_INT_23 : std_logic ;
signal SSRSTATE6_1_D_0_L1_INT_65 : std_logic ;
signal WS_3_SQMUXA_0_1 : std_logic ;
signal WS_3_SQMUXA_1_A0_2 : std_logic ;
signal N_SRO_ROMSN_0_INT_12 : std_logic ;
signal PRSTATE_8_1 : std_logic ;
signal N_656_INT_66 : std_logic ;
signal N_SRO_IOSN_INT_70 : std_logic ;
signal PRSTATE_FAST_2_INT_13 : std_logic ;
signal BEXCEN_1_SQMUXA_I_1 : std_logic ;
signal HSEL_INT_58 : std_logic ;
signal PRSTATE_12_M7_I_A6_0 : std_logic ;
signal PRSTATE_12_I : std_logic ;
signal HWRITE_1 : std_logic ;
signal PRSTATE_12_0 : std_logic ;
signal PRSTATE_12_M7_I_A6 : std_logic ;
signal PRSTATE_4_INT_31 : std_logic ;
signal SIZE_1_INT_26 : std_logic ;
signal PRSTATE_1_SQMUXA : std_logic ;
signal BUS16EN_INT_72 : std_logic ;
signal N_382 : std_logic ;
signal N_383 : std_logic ;
signal N_384 : std_logic ;
signal N_385 : std_logic ;
signal N_386 : std_logic ;
signal N_387 : std_logic ;
signal N_388 : std_logic ;
signal N_389 : std_logic ;
signal N_390 : std_logic ;
signal N_391 : std_logic ;
signal N_392 : std_logic ;
signal N_393 : std_logic ;
signal N_394 : std_logic ;
signal N_395 : std_logic ;
signal N_396 : std_logic ;
signal N_397 : std_logic ;
signal N_626_I : std_logic ;
signal N_625_I : std_logic ;
signal N_624_I : std_logic ;
signal N_623_I : std_logic ;
signal N_630_I : std_logic ;
signal N_629_I : std_logic ;
signal N_628_I : std_logic ;
signal N_627_I : std_logic ;
signal ROMWRITE_1 : std_logic ;
signal IOEN_1 : std_logic ;
signal SSRSTATE_6_SQMUXA_INT_61 : std_logic ;
signal BDRIVE_1_IV_0_A0 : std_logic ;
signal BDRIVE_1_IV_0_A1 : std_logic ;
signal BDRIVE_1_IV_M9_I_0_0 : std_logic ;
signal NN_1 : std_logic ;
signal NN_2 : std_logic ;
signal NN_3 : std_logic ;
signal NN_4 : std_logic ;
signal NN_5 : std_logic ;
signal NN_6 : std_logic ;
signal NN_7 : std_logic ;
signal NN_8 : std_logic ;
signal NN_9 : std_logic ;
signal D16MUXC_1 : std_logic ;
signal D16MUXC_2 : std_logic ;
signal D16MUXC : std_logic ;
signal BDRIVE_1_IV_0_1 : std_logic ;
signal BDRIVE_1_IV_M9_I_0 : std_logic ;
signal RBDRIVEC_18 : std_logic ;
signal SSRSTATE_5_I : std_logic ;
signal SSRSTATEC_0 : std_logic ;
signal SSRSTATE23_1 : std_logic ;
signal WS_3_INT_19 : std_logic ;
signal PRSTATEC_1 : std_logic ;
signal N_337_I : std_logic ;
signal PRSTATEC_0 : std_logic ;
signal PRSTATE_3_INT_30 : std_logic ;
signal PRSTATEC : std_logic ;
signal N_342 : std_logic ;
signal PRSTATESR_0 : std_logic ;
signal PRSTATES_I : std_logic ;
signal N_SRO_ADDRESS_11_INT_47 : std_logic ;
signal WRITEN_0_SQMUXA_0_2 : std_logic ;
signal WRITEN_0_SQMUXA_D : std_logic ;
signal RBDRIVEC : std_logic ;
signal SSRSTATE_2_I_INT_55 : std_logic ;
signal HADDR_0_SQMUXA_A0_0 : std_logic ;
signal WRITEN_0_SQMUXA_0_0 : std_logic ;
signal BDRIVE_1_SQMUXA_2 : std_logic ;
signal WS_0_SQMUXA_0_0_0 : std_logic ;
signal CHANGE_1_SQMUXA_N_3_INT_63 : std_logic ;
signal SSRHREADY_2_SQMUXA_0_0_INT_62 : std_logic ;
signal N_362 : std_logic ;
signal N_363 : std_logic ;
signal SETBDRIVE : std_logic ;
signal N_341 : std_logic ;
signal BDRIVE_0_SQMUXA_2_0_0 : std_logic ;
signal BDRIVE_1_IV_0_A4_0 : std_logic ;
signal SSRSTATE_0_INT_20 : std_logic ;
signal PRHREADY_0_SQMUXA : std_logic ;
signal SSRSTATE10 : std_logic ;
signal WS_0_SQMUXA_0_C_INT_50 : std_logic ;
signal N_SRO_ADDRESS_1_INT_37 : std_logic ;
signal UN17_BUS16EN : std_logic ;
signal WS_1_SQMUXA_INT_52 : std_logic ;
signal SSRSTATE_3 : std_logic ;
signal WS_0_SQMUXA_C_INT_49 : std_logic ;
signal ROMWRITE : std_logic ;
signal IOEN : std_logic ;
signal N_APBO_PRDATA_28_INT_11 : std_logic ;
signal NN_10 : std_logic ;
signal N_481 : std_logic ;
signal N_480 : std_logic ;
signal IOWS_3_INT_6 : std_logic ;
signal IOWS_0_INT_5 : std_logic ;
signal ROMRWS_3_INT_10 : std_logic ;
signal ROMRWS_0_INT_9 : std_logic ;
signal ROMWWS_3_INT_8 : std_logic ;
signal ROMWWS_0_INT_7 : std_logic ;
signal SSRHREADY_INT_51 : std_logic ;
signal PRHREADY_INT_48 : std_logic ;
signal NN_11 : std_logic ;
begin
II_r_acount_qxuHAKL1HAKR: LUT1
generic map(
INIT => X"2"
)
port map (
I0 => N_SRO_ADDRESS_3_INT_39,
O => ACOUNT_QXU(1));
II_r_acount_qxuHAKL2HAKR: LUT1
generic map(
INIT => X"2"
)
port map (
I0 => N_SRO_ADDRESS_4_INT_40,
O => ACOUNT_QXU(2));
II_r_acount_qxuHAKL3HAKR: LUT1
generic map(
INIT => X"2"
)
port map (
I0 => N_SRO_ADDRESS_5_INT_41,
O => ACOUNT_QXU(3));
II_r_acount_qxuHAKL4HAKR: LUT1
generic map(
INIT => X"2"
)
port map (
I0 => N_SRO_ADDRESS_6_INT_42,
O => ACOUNT_QXU(4));
II_r_acount_qxuHAKL5HAKR: LUT1
generic map(
INIT => X"2"
)
port map (
I0 => N_SRO_ADDRESS_7_INT_43,
O => ACOUNT_QXU(5));
II_r_acount_qxuHAKL6HAKR: LUT1
generic map(
INIT => X"2"
)
port map (
I0 => N_SRO_ADDRESS_8_INT_44,
O => ACOUNT_QXU(6));
II_r_acount_qxuHAKL7HAKR: LUT1
generic map(
INIT => X"2"
)
port map (
I0 => N_SRO_ADDRESS_9_INT_45,
O => ACOUNT_QXU(7));
II_r_acount_qxuHAKL8HAKR: LUT1
generic map(
INIT => X"2"
)
port map (
I0 => N_SRO_ADDRESS_10_INT_46,
O => ACOUNT_QXU(8));
II_ctrl_v_romsn_1_iv: LUT4_L
generic map(
INIT => X"0EEE"
)
port map (
I0 => ROMSN_1_IV_L1,
I1 => CHANGE_3,
I2 => HMBSEL_0_INT_33,
I3 => PRSTATE_0_INT_27,
LO => ROMSN_1);
II_v_prstate_1_i_o4_0HAKL2HAKR: LUT4_L
generic map(
INIT => X"80AA"
)
port map (
I0 => g0_44,
I1 => g0_1_0,
I2 => change_3_f1_d_0_0,
I3 => prstate_1_i_o4_s(2),
LO => PRHREADY_6);
II_v_N_635_i: LUT4_L
generic map(
INIT => X"888B"
)
port map (
I0 => D16MUXC_0_4_INT_73,
I1 => PRSTATE_1_INT_28,
I2 => PRSTATE_2_INT_29,
I3 => N_635_I_1,
LO => N_635_I);
II_r_d16muxc_0: LUT4_L
generic map(
INIT => X"8000"
)
port map (
I0 => BUS16EN_INT_72,
I1 => D16MUXC_0_1,
I2 => D16MUXC_0_1_0,
I3 => D16MUXC_0_4_INT_73,
LO => D16MUXC_0);
II_r_acount_lm_0HAKL0HAKR: LUT3_L
generic map(
INIT => X"1D"
)
port map (
I0 => N_SRO_ADDRESS_2_INT_38,
I1 => loadcount_7,
I2 => ACOUNT_LM_0_1(0),
LO => ACOUNT_LM(0));
II_ctrl_v_ws_1_0HAKL1HAKR: LUT3_L
generic map(
INIT => X"D8"
)
port map (
I0 => N_371_INT_71,
I1 => WS_1_0_BM(1),
I2 => WS_1_0_RN_1(1),
LO => WS_1(1));
II_ctrl_v_ws_1HAKL2HAKR: LUT4_L
generic map(
INIT => X"1141"
)
port map (
I0 => N_371_INT_71,
I1 => WS_1_L1,
I2 => g0_23,
I3 => WS_1_L1_0,
LO => WS_1(2));
II_ctrl_v_ssrstate_1_0HAKL3HAKR: LUT4_L
generic map(
INIT => X"B333"
)
port map (
I0 => SSRSTATE_1_0_D_BM(3),
I1 => SSRSTATE_1_0_1(3),
I2 => SSRSTATE_1_M2S2_0,
I3 => ssrstate_2_sqmuxa_i,
LO => SSRSTATE_1(3));
II_ctrl_v_iosn_9_iv: LUT4_L
generic map(
INIT => X"0EEE"
)
port map (
I0 => IOSN_9_IV_L1,
I1 => CHANGE_3,
I2 => HMBSEL_2_INT_35,
I3 => PRSTATE_0_INT_27,
LO => IOSN_9);
II_ctrl_v_N_619_i: LUT4_L
generic map(
INIT => X"AFBF"
)
port map (
I0 => N_317,
I1 => N_619_I_L1,
I2 => BWN_1_0_O3(1),
I3 => bwn_1_sqmuxa_2_d_0_2,
LO => N_619_I);
II_ctrl_v_N_620_i: LUT4_L
generic map(
INIT => X"73FF"
)
port map (
I0 => hsize_1(1),
I1 => bwn_1_0_o3_0,
I2 => haddr_0,
I3 => bwn_1_sqmuxa_2_d,
LO => N_620_I);
II_r_prstate_iHAKL1HAKR: INV port map (
I => PRSTATE_1_INT_28,
O => PRSTATE_I(1));
II_ctrl_v_rst_i: INV port map (
I => rst,
O => RST_I);
II_r_oen: FDPE port map (
Q => n_sro_oen,
D => OEN_1,
C => clk,
PRE => RST_I,
CE => OEN_1_SQMUXA_2_I);
II_r_bwnHAKL0HAKR: FDE port map (
Q => n_sro_wrn(0),
D => N_620_I,
C => clk,
CE => BWN_1_SQMUXA_3_I);
II_r_bwnHAKL1HAKR: FDE port map (
Q => n_sro_wrn(1),
D => N_619_I,
C => clk,
CE => BWN_1_SQMUXA_3_I);
II_r_bwnHAKL2HAKR: FDE port map (
Q => n_sro_wrn(2),
D => N_618_i,
C => clk,
CE => BWN_1_SQMUXA_3_I);
II_r_bwnHAKL3HAKR: FDE port map (
Q => n_sro_wrn(3),
D => N_617_I,
C => clk,
CE => BWN_1_SQMUXA_3_I);
II_r_iosn: FDPE port map (
Q => N_SRO_IOSN_INT_70,
D => IOSN_9,
C => clk,
PRE => RST_I,
CE => N_599_I);
II_r_ramsn: FDPE port map (
Q => n_sro_ramsn(0),
D => N_574_i,
C => clk,
PRE => RST_I,
CE => SSRSTATE_9);
II_r_hwdataoutHAKL0HAKR: FDE port map (
Q => n_sro_data(0),
D => HWDATAOUT_1(0),
C => clk,
CE => PRSTATE_I(1));
II_r_hwdataoutHAKL1HAKR: FDE port map (
Q => n_sro_data(1),
D => HWDATAOUT_1(1),
C => clk,
CE => PRSTATE_I(1));
II_r_hwdataoutHAKL2HAKR: FDE port map (
Q => n_sro_data(2),
D => HWDATAOUT_1(2),
C => clk,
CE => PRSTATE_I(1));
II_r_hwdataoutHAKL3HAKR: FDE port map (
Q => n_sro_data(3),
D => HWDATAOUT_1(3),
C => clk,
CE => PRSTATE_I(1));
II_r_hwdataoutHAKL4HAKR: FDE port map (
Q => n_sro_data(4),
D => HWDATAOUT_1(4),
C => clk,
CE => PRSTATE_I(1));
II_r_hwdataoutHAKL5HAKR: FDE port map (
Q => n_sro_data(5),
D => HWDATAOUT_1(5),
C => clk,
CE => PRSTATE_I(1));
II_r_hwdataoutHAKL6HAKR: FDE port map (
Q => n_sro_data(6),
D => HWDATAOUT_1(6),
C => clk,
CE => PRSTATE_I(1));
II_r_hwdataoutHAKL7HAKR: FDE port map (
Q => n_sro_data(7),
D => HWDATAOUT_1(7),
C => clk,
CE => PRSTATE_I(1));
II_r_hwdataoutHAKL8HAKR: FDE port map (
Q => n_sro_data(8),
D => HWDATAOUT_1(8),
C => clk,
CE => PRSTATE_I(1));
II_r_hwdataoutHAKL9HAKR: FDE port map (
Q => n_sro_data(9),
D => HWDATAOUT_1(9),
C => clk,
CE => PRSTATE_I(1));
II_r_hwdataoutHAKL10HAKR: FDE port map (
Q => n_sro_data(10),
D => HWDATAOUT_1(10),
C => clk,
CE => PRSTATE_I(1));
II_r_hwdataoutHAKL11HAKR: FDE port map (
Q => n_sro_data(11),
D => HWDATAOUT_1(11),
C => clk,
CE => PRSTATE_I(1));
II_r_hwdataoutHAKL12HAKR: FDE port map (
Q => n_sro_data(12),
D => HWDATAOUT_1(12),
C => clk,
CE => PRSTATE_I(1));
II_r_hwdataoutHAKL13HAKR: FDE port map (
Q => n_sro_data(13),
D => HWDATAOUT_1(13),
C => clk,
CE => PRSTATE_I(1));
II_r_hwdataoutHAKL14HAKR: FDE port map (
Q => n_sro_data(14),
D => HWDATAOUT_1(14),
C => clk,
CE => PRSTATE_I(1));
II_r_hwdataoutHAKL15HAKR: FDE port map (
Q => n_sro_data(15),
D => HWDATAOUT_1(15),
C => clk,
CE => PRSTATE_I(1));
II_r_hwdataoutHAKL16HAKR: FDE port map (
Q => n_sro_data(16),
D => HWDATAOUT_1(16),
C => clk,
CE => PRSTATE_I(1));
II_r_hwdataoutHAKL17HAKR: FDE port map (
Q => n_sro_data(17),
D => HWDATAOUT_1(17),
C => clk,
CE => PRSTATE_I(1));
II_r_hwdataoutHAKL18HAKR: FDE port map (
Q => n_sro_data(18),
D => HWDATAOUT_1(18),
C => clk,
CE => PRSTATE_I(1));
II_r_hwdataoutHAKL19HAKR: FDE port map (
Q => n_sro_data(19),
D => HWDATAOUT_1(19),
C => clk,
CE => PRSTATE_I(1));
II_r_hwdataoutHAKL20HAKR: FDE port map (
Q => n_sro_data(20),
D => HWDATAOUT_1(20),
C => clk,
CE => PRSTATE_I(1));
II_r_hwdataoutHAKL21HAKR: FDE port map (
Q => n_sro_data(21),
D => HWDATAOUT_1(21),
C => clk,
CE => PRSTATE_I(1));
II_r_hwdataoutHAKL22HAKR: FDE port map (
Q => n_sro_data(22),
D => HWDATAOUT_1(22),
C => clk,
CE => PRSTATE_I(1));
II_r_hwdataoutHAKL23HAKR: FDE port map (
Q => n_sro_data(23),
D => HWDATAOUT_1(23),
C => clk,
CE => PRSTATE_I(1));
II_r_hwdataoutHAKL24HAKR: FDE port map (
Q => n_sro_data(24),
D => HWDATAOUT_1(24),
C => clk,
CE => PRSTATE_I(1));
II_r_hwdataoutHAKL25HAKR: FDE port map (
Q => n_sro_data(25),
D => HWDATAOUT_1(25),
C => clk,
CE => PRSTATE_I(1));
II_r_hwdataoutHAKL26HAKR: FDE port map (
Q => n_sro_data(26),
D => HWDATAOUT_1(26),
C => clk,
CE => PRSTATE_I(1));
II_r_hwdataoutHAKL27HAKR: FDE port map (
Q => n_sro_data(27),
D => HWDATAOUT_1(27),
C => clk,
CE => PRSTATE_I(1));
II_r_hwdataoutHAKL28HAKR: FDE port map (
Q => n_sro_data(28),
D => HWDATAOUT_1(28),
C => clk,
CE => PRSTATE_I(1));
II_r_hwdataoutHAKL29HAKR: FDE port map (
Q => n_sro_data(29),
D => HWDATAOUT_1(29),
C => clk,
CE => PRSTATE_I(1));
II_r_hwdataoutHAKL30HAKR: FDE port map (
Q => n_sro_data(30),
D => HWDATAOUT_1(30),
C => clk,
CE => PRSTATE_I(1));
II_r_hwdataoutHAKL31HAKR: FDE port map (
Q => n_sro_data(31),
D => HWDATAOUT_1(31),
C => clk,
CE => PRSTATE_I(1));
II_r_mcfg1_romwidthHAKL0HAKR: FDE port map (
Q => ROMWIDTH(0),
D => ROMWIDTH_1(0),
C => clk,
CE => BEXCEN_1_SQMUXA_I);
II_r_mcfg1_romwidthHAKL1HAKR: FDE port map (
Q => ROMWIDTH(1),
D => ROMWIDTH_1(1),
C => clk,
CE => BEXCEN_1_SQMUXA_I);
II_r_data16HAKL0HAKR: FDE port map (
Q => DATA16(0),
D => HRDATA(16),
C => clk,
CE => DATA16_0_SQMUXA);
II_r_data16HAKL1HAKR: FDE port map (
Q => DATA16(1),
D => HRDATA(17),
C => clk,
CE => DATA16_0_SQMUXA);
II_r_data16HAKL2HAKR: FDE port map (
Q => DATA16(2),
D => HRDATA(18),
C => clk,
CE => DATA16_0_SQMUXA);
II_r_data16HAKL3HAKR: FDE port map (
Q => DATA16(3),
D => HRDATA(19),
C => clk,
CE => DATA16_0_SQMUXA);
II_r_data16HAKL4HAKR: FDE port map (
Q => DATA16(4),
D => HRDATA(20),
C => clk,
CE => DATA16_0_SQMUXA);
II_r_data16HAKL5HAKR: FDE port map (
Q => DATA16(5),
D => HRDATA(21),
C => clk,
CE => DATA16_0_SQMUXA);
II_r_data16HAKL6HAKR: FDE port map (
Q => DATA16(6),
D => HRDATA(22),
C => clk,
CE => DATA16_0_SQMUXA);
II_r_data16HAKL7HAKR: FDE port map (
Q => DATA16(7),
D => HRDATA(23),
C => clk,
CE => DATA16_0_SQMUXA);
II_r_data16HAKL8HAKR: FDE port map (
Q => DATA16(8),
D => HRDATA(24),
C => clk,
CE => DATA16_0_SQMUXA);
II_r_data16HAKL9HAKR: FDE port map (
Q => DATA16(9),
D => HRDATA(25),
C => clk,
CE => DATA16_0_SQMUXA);
II_r_data16HAKL10HAKR: FDE port map (
Q => DATA16(10),
D => HRDATA(26),
C => clk,
CE => DATA16_0_SQMUXA);
II_r_data16HAKL11HAKR: FDE port map (
Q => DATA16(11),
D => HRDATA(27),
C => clk,
CE => DATA16_0_SQMUXA);
II_r_data16HAKL12HAKR: FDE port map (
Q => DATA16(12),
D => HRDATA(28),
C => clk,
CE => DATA16_0_SQMUXA);
II_r_data16HAKL13HAKR: FDE port map (
Q => DATA16(13),
D => HRDATA(29),
C => clk,
CE => DATA16_0_SQMUXA);
II_r_data16HAKL14HAKR: FDE port map (
Q => DATA16(14),
D => HRDATA(30),
C => clk,
CE => DATA16_0_SQMUXA);
II_r_data16HAKL15HAKR: FDE port map (
Q => DATA16(15),
D => HRDATA(31),
C => clk,
CE => DATA16_0_SQMUXA);
II_r_sizeHAKL0HAKR: FDE port map (
Q => SIZE_0_INT_25,
D => n_ahbsi_hsize(0),
C => clk,
CE => HMBSEL_0_SQMUXA);
II_r_sizeHAKL1HAKR: FDE port map (
Q => SIZE_1_INT_26,
D => n_ahbsi_hsize(1),
C => clk,
CE => HMBSEL_0_SQMUXA);
II_r_hwrite: FDE port map (
Q => HWRITE,
D => n_ahbsi_hwrite,
C => clk,
CE => HMBSEL_0_SQMUXA);
II_r_hwdataHAKL0HAKR: FDE port map (
Q => HWDATA(0),
D => n_ahbsi_hwdata(0),
C => clk,
CE => SSRSTATE_1_INT_21);
II_r_hwdataHAKL1HAKR: FDE port map (
Q => HWDATA(1),
D => n_ahbsi_hwdata(1),
C => clk,
CE => SSRSTATE_1_INT_21);
II_r_hwdataHAKL2HAKR: FDE port map (
Q => HWDATA(2),
D => n_ahbsi_hwdata(2),
C => clk,
CE => SSRSTATE_1_INT_21);
II_r_hwdataHAKL3HAKR: FDE port map (
Q => HWDATA(3),
D => n_ahbsi_hwdata(3),
C => clk,
CE => SSRSTATE_1_INT_21);
II_r_hwdataHAKL4HAKR: FDE port map (
Q => HWDATA(4),
D => n_ahbsi_hwdata(4),
C => clk,
CE => SSRSTATE_1_INT_21);
II_r_hwdataHAKL5HAKR: FDE port map (
Q => HWDATA(5),
D => n_ahbsi_hwdata(5),
C => clk,
CE => SSRSTATE_1_INT_21);
II_r_hwdataHAKL6HAKR: FDE port map (
Q => HWDATA(6),
D => n_ahbsi_hwdata(6),
C => clk,
CE => SSRSTATE_1_INT_21);
II_r_hwdataHAKL7HAKR: FDE port map (
Q => HWDATA(7),
D => n_ahbsi_hwdata(7),
C => clk,
CE => SSRSTATE_1_INT_21);
II_r_hwdataHAKL8HAKR: FDE port map (
Q => HWDATA(8),
D => n_ahbsi_hwdata(8),
C => clk,
CE => SSRSTATE_1_INT_21);
II_r_hwdataHAKL9HAKR: FDE port map (
Q => HWDATA(9),
D => n_ahbsi_hwdata(9),
C => clk,
CE => SSRSTATE_1_INT_21);
II_r_hwdataHAKL10HAKR: FDE port map (
Q => HWDATA(10),
D => n_ahbsi_hwdata(10),
C => clk,
CE => SSRSTATE_1_INT_21);
II_r_hwdataHAKL11HAKR: FDE port map (
Q => HWDATA(11),
D => n_ahbsi_hwdata(11),
C => clk,
CE => SSRSTATE_1_INT_21);
II_r_hwdataHAKL12HAKR: FDE port map (
Q => HWDATA(12),
D => n_ahbsi_hwdata(12),
C => clk,
CE => SSRSTATE_1_INT_21);
II_r_hwdataHAKL13HAKR: FDE port map (
Q => HWDATA(13),
D => n_ahbsi_hwdata(13),
C => clk,
CE => SSRSTATE_1_INT_21);
II_r_hwdataHAKL14HAKR: FDE port map (
Q => HWDATA(14),
D => n_ahbsi_hwdata(14),
C => clk,
CE => SSRSTATE_1_INT_21);
II_r_hwdataHAKL15HAKR: FDE port map (
Q => HWDATA(15),
D => n_ahbsi_hwdata(15),
C => clk,
CE => SSRSTATE_1_INT_21);
II_r_hwdataHAKL16HAKR: FDE port map (
Q => HWDATA(16),
D => n_ahbsi_hwdata(16),
C => clk,
CE => SSRSTATE_1_INT_21);
II_r_hwdataHAKL17HAKR: FDE port map (
Q => HWDATA(17),
D => n_ahbsi_hwdata(17),
C => clk,
CE => SSRSTATE_1_INT_21);
II_r_hwdataHAKL18HAKR: FDE port map (
Q => HWDATA(18),
D => n_ahbsi_hwdata(18),
C => clk,
CE => SSRSTATE_1_INT_21);
II_r_hwdataHAKL19HAKR: FDE port map (
Q => HWDATA(19),
D => n_ahbsi_hwdata(19),
C => clk,
CE => SSRSTATE_1_INT_21);
II_r_hwdataHAKL20HAKR: FDE port map (
Q => HWDATA(20),
D => n_ahbsi_hwdata(20),
C => clk,
CE => SSRSTATE_1_INT_21);
II_r_hwdataHAKL21HAKR: FDE port map (
Q => HWDATA(21),
D => n_ahbsi_hwdata(21),
C => clk,
CE => SSRSTATE_1_INT_21);
II_r_hwdataHAKL22HAKR: FDE port map (
Q => HWDATA(22),
D => n_ahbsi_hwdata(22),
C => clk,
CE => SSRSTATE_1_INT_21);
II_r_hwdataHAKL23HAKR: FDE port map (
Q => HWDATA(23),
D => n_ahbsi_hwdata(23),
C => clk,
CE => SSRSTATE_1_INT_21);
II_r_hwdataHAKL24HAKR: FDE port map (
Q => HWDATA(24),
D => n_ahbsi_hwdata(24),
C => clk,
CE => SSRSTATE_1_INT_21);
II_r_hwdataHAKL25HAKR: FDE port map (
Q => HWDATA(25),
D => n_ahbsi_hwdata(25),
C => clk,
CE => SSRSTATE_1_INT_21);
II_r_hwdataHAKL26HAKR: FDE port map (
Q => HWDATA(26),
D => n_ahbsi_hwdata(26),
C => clk,
CE => SSRSTATE_1_INT_21);
II_r_hwdataHAKL27HAKR: FDE port map (
Q => HWDATA(27),
D => n_ahbsi_hwdata(27),
C => clk,
CE => SSRSTATE_1_INT_21);
II_r_hwdataHAKL28HAKR: FDE port map (
Q => HWDATA(28),
D => n_ahbsi_hwdata(28),
C => clk,
CE => SSRSTATE_1_INT_21);
II_r_hwdataHAKL29HAKR: FDE port map (
Q => HWDATA(29),
D => n_ahbsi_hwdata(29),
C => clk,
CE => SSRSTATE_1_INT_21);
II_r_hwdataHAKL30HAKR: FDE port map (
Q => HWDATA(30),
D => n_ahbsi_hwdata(30),
C => clk,
CE => SSRSTATE_1_INT_21);
II_r_hwdataHAKL31HAKR: FDE port map (
Q => HWDATA(31),
D => n_ahbsi_hwdata(31),
C => clk,
CE => SSRSTATE_1_INT_21);
II_r_hrdataHAKL22HAKR: FD port map (
Q => HRDATA(22),
D => n_sri_data(22),
C => clk);
II_r_hrdataHAKL23HAKR: FD port map (
Q => HRDATA(23),
D => n_sri_data(23),
C => clk);
II_r_hrdataHAKL24HAKR: FD port map (
Q => HRDATA(24),
D => n_sri_data(24),
C => clk);
II_r_hrdataHAKL25HAKR: FD port map (
Q => HRDATA(25),
D => n_sri_data(25),
C => clk);
II_r_hrdataHAKL26HAKR: FD port map (
Q => HRDATA(26),
D => n_sri_data(26),
C => clk);
II_r_hrdataHAKL27HAKR: FD port map (
Q => HRDATA(27),
D => n_sri_data(27),
C => clk);
II_r_hrdataHAKL28HAKR: FD port map (
Q => HRDATA(28),
D => n_sri_data(28),
C => clk);
II_r_hrdataHAKL29HAKR: FD port map (
Q => HRDATA(29),
D => n_sri_data(29),
C => clk);
II_r_hrdataHAKL30HAKR: FD port map (
Q => HRDATA(30),
D => n_sri_data(30),
C => clk);
II_r_hrdataHAKL31HAKR: FD port map (
Q => HRDATA(31),
D => n_sri_data(31),
C => clk);
II_r_hrdataHAKL7HAKR: FD port map (
Q => HRDATA(7),
D => n_sri_data(7),
C => clk);
II_r_hrdataHAKL8HAKR: FD port map (
Q => HRDATA(8),
D => n_sri_data(8),
C => clk);
II_r_hrdataHAKL9HAKR: FD port map (
Q => HRDATA(9),
D => n_sri_data(9),
C => clk);
II_r_hrdataHAKL10HAKR: FD port map (
Q => HRDATA(10),
D => n_sri_data(10),
C => clk);
II_r_hrdataHAKL11HAKR: FD port map (
Q => HRDATA(11),
D => n_sri_data(11),
C => clk);
II_r_hrdataHAKL12HAKR: FD port map (
Q => HRDATA(12),
D => n_sri_data(12),
C => clk);
II_r_hrdataHAKL13HAKR: FD port map (
Q => HRDATA(13),
D => n_sri_data(13),
C => clk);
II_r_hrdataHAKL14HAKR: FD port map (
Q => HRDATA(14),
D => n_sri_data(14),
C => clk);
II_r_hrdataHAKL15HAKR: FD port map (
Q => HRDATA(15),
D => n_sri_data(15),
C => clk);
II_r_hrdataHAKL16HAKR: FD port map (
Q => HRDATA(16),
D => n_sri_data(16),
C => clk);
II_r_hrdataHAKL17HAKR: FD port map (
Q => HRDATA(17),
D => n_sri_data(17),
C => clk);
II_r_hrdataHAKL18HAKR: FD port map (
Q => HRDATA(18),
D => n_sri_data(18),
C => clk);
II_r_hrdataHAKL19HAKR: FD port map (
Q => HRDATA(19),
D => n_sri_data(19),
C => clk);
II_r_hrdataHAKL20HAKR: FD port map (
Q => HRDATA(20),
D => n_sri_data(20),
C => clk);
II_r_hrdataHAKL21HAKR: FD port map (
Q => HRDATA(21),
D => n_sri_data(21),
C => clk);
II_r_hrdataHAKL0HAKR: FD port map (
Q => HRDATA(0),
D => n_sri_data(0),
C => clk);
II_r_hrdataHAKL1HAKR: FD port map (
Q => HRDATA(1),
D => n_sri_data(1),
C => clk);
II_r_hrdataHAKL2HAKR: FD port map (
Q => HRDATA(2),
D => n_sri_data(2),
C => clk);
II_r_hrdataHAKL3HAKR: FD port map (
Q => HRDATA(3),
D => n_sri_data(3),
C => clk);
II_r_hrdataHAKL4HAKR: FD port map (
Q => HRDATA(4),
D => n_sri_data(4),
C => clk);
II_r_hrdataHAKL5HAKR: FD port map (
Q => HRDATA(5),
D => n_sri_data(5),
C => clk);
II_r_hrdataHAKL6HAKR: FD port map (
Q => HRDATA(6),
D => n_sri_data(6),
C => clk);
II_r_hmbselHAKL0HAKR: FDCE port map (
Q => HMBSEL_0_INT_33,
D => n_ahbsi_hmbsel(0),
C => clk,
CLR => RST_I,
CE => HMBSEL_0_SQMUXA);
II_r_haddrHAKL21HAKR: FDE port map (
Q => n_sro_address(21),
D => n_ahbsi_haddr(21),
C => clk,
CE => HMBSEL_0_SQMUXA);
II_r_haddrHAKL22HAKR: FDE port map (
Q => n_sro_address(22),
D => n_ahbsi_haddr(22),
C => clk,
CE => HMBSEL_0_SQMUXA);
II_r_haddrHAKL23HAKR: FDE port map (
Q => n_sro_address(23),
D => n_ahbsi_haddr(23),
C => clk,
CE => HMBSEL_0_SQMUXA);
II_r_haddrHAKL24HAKR: FDE port map (
Q => n_sro_address(24),
D => n_ahbsi_haddr(24),
C => clk,
CE => HMBSEL_0_SQMUXA);
II_r_haddrHAKL25HAKR: FDE port map (
Q => n_sro_address(25),
D => n_ahbsi_haddr(25),
C => clk,
CE => HMBSEL_0_SQMUXA);
II_r_haddrHAKL26HAKR: FDE port map (
Q => n_sro_address(26),
D => n_ahbsi_haddr(26),
C => clk,
CE => HMBSEL_0_SQMUXA);
II_r_haddrHAKL27HAKR: FDE port map (
Q => n_sro_address(27),
D => n_ahbsi_haddr(27),
C => clk,
CE => HMBSEL_0_SQMUXA);
II_r_haddrHAKL28HAKR: FDE port map (
Q => n_sro_address(28),
D => n_ahbsi_haddr(28),
C => clk,
CE => HMBSEL_0_SQMUXA);
II_r_haddrHAKL29HAKR: FDE port map (
Q => n_sro_address(29),
D => n_ahbsi_haddr(29),
C => clk,
CE => HMBSEL_0_SQMUXA);
II_r_haddrHAKL30HAKR: FDE port map (
Q => n_sro_address(30),
D => n_ahbsi_haddr(30),
C => clk,
CE => HMBSEL_0_SQMUXA);
II_r_haddrHAKL31HAKR: FDE port map (
Q => n_sro_address(31),
D => n_ahbsi_haddr(31),
C => clk,
CE => HMBSEL_0_SQMUXA);
II_r_hmbselHAKL2HAKR: FDCE port map (
Q => HMBSEL_2_INT_35,
D => n_ahbsi_hmbsel(2),
C => clk,
CLR => RST_I,
CE => HMBSEL_0_SQMUXA);
II_r_hmbselHAKL1HAKR: FDCE port map (
Q => HMBSEL_1_INT_34,
D => n_ahbsi_hmbsel(1),
C => clk,
CLR => RST_I,
CE => HMBSEL_0_SQMUXA);
II_r_haddrHAKL6HAKR: FDE port map (
Q => HADDR(6),
D => n_ahbsi_haddr(6),
C => clk,
CE => HMBSEL_0_SQMUXA);
II_r_haddrHAKL7HAKR: FDE port map (
Q => HADDR(7),
D => n_ahbsi_haddr(7),
C => clk,
CE => HMBSEL_0_SQMUXA);
II_r_haddrHAKL8HAKR: FDE port map (
Q => HADDR(8),
D => n_ahbsi_haddr(8),
C => clk,
CE => HMBSEL_0_SQMUXA);
II_r_haddrHAKL9HAKR: FDE port map (
Q => HADDR(9),
D => n_ahbsi_haddr(9),
C => clk,
CE => HMBSEL_0_SQMUXA);
II_r_haddrHAKL10HAKR: FDE port map (
Q => HADDR(10),
D => n_ahbsi_haddr(10),
C => clk,
CE => HMBSEL_0_SQMUXA);
II_r_haddrHAKL11HAKR: FDE port map (
Q => HADDR(11),
D => n_ahbsi_haddr(11),
C => clk,
CE => HMBSEL_0_SQMUXA);
II_r_haddrHAKL12HAKR: FDE port map (
Q => n_sro_address(12),
D => n_ahbsi_haddr(12),
C => clk,
CE => HMBSEL_0_SQMUXA);
II_r_haddrHAKL13HAKR: FDE port map (
Q => n_sro_address(13),
D => n_ahbsi_haddr(13),
C => clk,
CE => HMBSEL_0_SQMUXA);
II_r_haddrHAKL14HAKR: FDE port map (
Q => n_sro_address(14),
D => n_ahbsi_haddr(14),
C => clk,
CE => HMBSEL_0_SQMUXA);
II_r_haddrHAKL15HAKR: FDE port map (
Q => n_sro_address(15),
D => n_ahbsi_haddr(15),
C => clk,
CE => HMBSEL_0_SQMUXA);
II_r_haddrHAKL16HAKR: FDE port map (
Q => n_sro_address(16),
D => n_ahbsi_haddr(16),
C => clk,
CE => HMBSEL_0_SQMUXA);
II_r_haddrHAKL17HAKR: FDE port map (
Q => n_sro_address(17),
D => n_ahbsi_haddr(17),
C => clk,
CE => HMBSEL_0_SQMUXA);
II_r_haddrHAKL18HAKR: FDE port map (
Q => n_sro_address(18),
D => n_ahbsi_haddr(18),
C => clk,
CE => HMBSEL_0_SQMUXA);
II_r_haddrHAKL19HAKR: FDE port map (
Q => n_sro_address(19),
D => n_ahbsi_haddr(19),
C => clk,
CE => HMBSEL_0_SQMUXA);
II_r_haddrHAKL20HAKR: FDE port map (
Q => n_sro_address(20),
D => n_ahbsi_haddr(20),
C => clk,
CE => HMBSEL_0_SQMUXA);
II_r_ssrstateHAKL4HAKR: FD port map (
Q => SSRSTATE_4_INT_24,
D => ssrstate_1_2,
C => clk);
II_r_ssrstateHAKL3HAKR: FD port map (
Q => SSRSTATE_3_INT_23,
D => SSRSTATE_1(3),
C => clk);
II_r_ssrstateHAKL2HAKR: FD port map (
Q => SSRSTATE_2_INT_22,
D => SSRSTATE_1(2),
C => clk);
II_r_haddrHAKL0HAKR: FDE port map (
Q => N_SRO_ADDRESS_0_INT_36,
D => n_ahbsi_haddr(0),
C => clk,
CE => HMBSEL_0_SQMUXA);
II_r_haddrHAKL2HAKR: FDE port map (
Q => HADDR(2),
D => n_ahbsi_haddr(2),
C => clk,
CE => HMBSEL_0_SQMUXA);
II_r_haddrHAKL3HAKR: FDE port map (
Q => HADDR(3),
D => n_ahbsi_haddr(3),
C => clk,
CE => HMBSEL_0_SQMUXA);
II_r_haddrHAKL4HAKR: FDE port map (
Q => HADDR(4),
D => n_ahbsi_haddr(4),
C => clk,
CE => HMBSEL_0_SQMUXA);
II_r_haddrHAKL5HAKR: FDE port map (
Q => HADDR(5),
D => n_ahbsi_haddr(5),
C => clk,
CE => HMBSEL_0_SQMUXA);
II_r_wsHAKL2HAKR: FD port map (
Q => WS_2_INT_18,
D => WS_1(2),
C => clk);
II_r_wsHAKL3HAKR: FD port map (
Q => WS_3_INT_19,
D => ws_1_3,
C => clk);
II_r_wsHAKL0HAKR: FD port map (
Q => WS_0_INT_16,
D => ws_1_0,
C => clk);
II_r_wsHAKL1HAKR: FD port map (
Q => WS_1_INT_17,
D => WS_1(1),
C => clk);
II_r_bdrive: FDP port map (
Q => N_SRO_BDRIVE_3_INT_15,
D => BDRIVE_1,
C => clk,
PRE => RST_I);
II_r_change: FDC port map (
Q => CHANGE_INT_69,
D => CHANGE_3,
C => clk,
CLR => RST_I);
II_r_acountHAKL0HAKR: FD port map (
Q => N_SRO_ADDRESS_2_INT_38,
D => ACOUNT_LM(0),
C => clk);
II_r_acountHAKL1HAKR: FD port map (
Q => N_SRO_ADDRESS_3_INT_39,
D => ACOUNT_LM(1),
C => clk);
II_r_acountHAKL2HAKR: FD port map (
Q => N_SRO_ADDRESS_4_INT_40,
D => ACOUNT_LM(2),
C => clk);
II_r_acountHAKL3HAKR: FD port map (
Q => N_SRO_ADDRESS_5_INT_41,
D => ACOUNT_LM(3),
C => clk);
II_r_acountHAKL4HAKR: FD port map (
Q => N_SRO_ADDRESS_6_INT_42,
D => ACOUNT_LM(4),
C => clk);
II_r_acountHAKL5HAKR: FD port map (
Q => N_SRO_ADDRESS_7_INT_43,
D => ACOUNT_LM(5),
C => clk);
II_r_acountHAKL6HAKR: FD port map (
Q => N_SRO_ADDRESS_8_INT_44,
D => ACOUNT_LM(6),
C => clk);
II_r_acountHAKL7HAKR: FD port map (
Q => N_SRO_ADDRESS_9_INT_45,
D => ACOUNT_LM(7),
C => clk);
II_r_acountHAKL8HAKR: FD port map (
Q => N_SRO_ADDRESS_10_INT_46,
D => ACOUNT_LM(8),
C => clk);
II_r_acountHAKL9HAKR: FD port map (
Q => N_SRO_ADDRESS_11_INT_47,
D => ACOUNT_LM(9),
C => clk);
II_v_oen_1_sqmuxa_2_i_L4: LUT4_L
generic map(
INIT => X"0400"
)
port map (
I0 => UN1_AHBSI_INT_68,
I1 => change_3_f0,
I2 => HMBSEL_4_1_INT_14,
I3 => HSEL_5_INT_67,
LO => OEN_1_SQMUXA_2_I_L4);
II_v_oen_1_sqmuxa_2_i_L6: LUT4_L
generic map(
INIT => X"4303"
)
port map (
I0 => OEN_1_SQMUXA_2_I_L4,
I1 => PRSTATE_5_INT_32,
I2 => PRSTATE_1,
I3 => hsel_1(0),
LO => OEN_1_SQMUXA_2_I_L6);
II_v_oen_1_sqmuxa_2_i: LUT4
generic map(
INIT => X"DFCC"
)
port map (
I0 => N_654,
I1 => OEN_1_SQMUXA_2_I_L6,
I2 => SSRSTATE_2_INT_22,
I3 => SSRSTATE_12_1,
O => OEN_1_SQMUXA_2_I);
II_ctrl_v_ssrstate_1_0_1HAKL3HAKR: LUT3
generic map(
INIT => X"35"
)
port map (
I0 => SSRSTATE_1_0_D_AM(3),
I1 => ssrstate_1_m1(3),
I2 => ssrstate_2_sqmuxa_i,
O => SSRSTATE_1_0_1(3));
II_ctrl_v_ws_1_0_bm_L1: LUT3
generic map(
INIT => X"40"
)
port map (
I0 => n_ahbsi_htrans(0),
I1 => n_ahbsi_htrans(1),
I2 => SSRSTATE_1_INT_21,
O => WS_1_0_BM_L1);
II_ctrl_v_ws_1_0_bm_L3: LUT2
generic map(
INIT => X"4"
)
port map (
I0 => N_656_INT_66,
I1 => rst,
O => WS_1_0_BM_L3);
II_ctrl_v_ws_1_0_bm_L5: LUT4
generic map(
INIT => X"0E00"
)
port map (
I0 => SSRSTATE6_1_D_0_L1_INT_65,
I1 => WS_1_0_BM_L1,
I2 => UN1_AHBSI_INT_68,
I3 => HSEL_5_INT_67,
O => WS_1_0_BM_L5);
II_ctrl_v_ws_1_0_bmHAKL1HAKR: LUT4
generic map(
INIT => X"80AA"
)
port map (
I0 => WS_1_0_BM_L3,
I1 => WS_1_0_BM_L5,
I2 => HMBSEL_4_1_INT_14,
I3 => SSRSTATE6_XX_MM_M3_INT_64,
O => WS_1_0_BM(1));
II_ctrl_v_N_619_i_L1_L1: LUT2
generic map(
INIT => X"4"
)
port map (
I0 => CHANGE_1_SQMUXA_N_3_INT_63,
I1 => SSRHREADY_2_SQMUXA_0_0_INT_62,
O => N_619_I_L1_L1);
II_ctrl_v_N_619_i_L1: LUT4
generic map(
INIT => X"80CC"
)
port map (
I0 => N_619_I_L1_L1,
I1 => n_ahbsi_hwrite,
I2 => HMBSEL_4_1_INT_14,
I3 => SSRSTATE6_XX_MM_M3_INT_64,
O => N_619_I_L1);
II_ctrl_v_hmbsel_4HAKL1HAKR: LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => HMBSEL_4_X1(1),
I1 => n_ahbsi_htrans(1),
I2 => HMBSEL_1_INT_34,
O => HMBSEL_4_1_INT_14);
II_v_ssrstate_6_sqmuxa: LUT4
generic map(
INIT => X"0035"
)
port map (
I0 => g0_52_x0,
I1 => g0_52_x1,
I2 => n_ahbsi_htrans(1),
I3 => SSRSTATE_6_SQMUXA_1,
O => SSRSTATE_6_SQMUXA_INT_61);
II_v_ssrstate_6_sqmuxa_1: LUT2
generic map(
INIT => X"7"
)
port map (
I0 => n_ahbsi_htrans(0),
I1 => SSRSTATE_2_INT_22,
O => SSRSTATE_6_SQMUXA_1);
II_ctrl_v_bwn_1_0_o3_0_L1: LUT2
generic map(
INIT => X"1"
)
port map (
I0 => N_SRO_ADDRESS_0_INT_36,
I1 => SIZE_0_INT_25,
O => BWN_1_0_O3_0_L1);
II_ctrl_v_bwn_1_0_o3_0_L3: LUT2
generic map(
INIT => X"1"
)
port map (
I0 => n_ahbsi_haddr(0),
I1 => n_ahbsi_hsize(0),
O => BWN_1_0_O3_0_L3);
II_ctrl_v_bwn_1_0_o3_0_L5: LUT4_L
generic map(
INIT => X"00E4"
)
port map (
I0 => N_662_INT_60,
I1 => BWN_1_0_O3_0_L1,
I2 => BWN_1_0_O3_0_L3,
I3 => hsize_1(1),
LO => BWN_1_0_O3_0_L5);
II_ctrl_v_bwn_1_0_o3_0HAKL1HAKR: LUT4
generic map(
INIT => X"5540"
)
port map (
I0 => BWN_1_0_O3_0_L5,
I1 => rst,
I2 => PRSTATE_2_REP1_INT_59,
I3 => bwn_0_sqmuxa_1,
O => BWN_1_0_O3(1));
II_r_prstate_2_rep1: FDR port map (
Q => PRSTATE_2_REP1_INT_59,
D => PRSTATEC_0_REP1,
C => clk,
R => RST_I);
II_r_prstatec_0_rep1: LUT4_L
generic map(
INIT => X"A2A0"
)
port map (
I0 => N_336,
I1 => CHANGE_3,
I2 => PRSTATE_0_INT_27,
I3 => prstate_1_i_o4_s(2),
LO => PRSTATEC_0_REP1);
II_r_prstate_fastHAKL2HAKR: FDR port map (
Q => PRSTATE_FAST_2_INT_13,
D => PRSTATEC_0_FAST,
C => clk,
R => RST_I);
II_r_prstatec_0_fast: LUT4_L
generic map(
INIT => X"A2A0"
)
port map (
I0 => N_336,
I1 => CHANGE_3,
I2 => PRSTATE_0_INT_27,
I3 => prstate_1_i_o4_s(2),
LO => PRSTATEC_0_FAST);
II_ctrl_v_ws_1_0_rnHAKL1HAKR: LUT4_L
generic map(
INIT => X"4EE4"
)
port map (
I0 => g0_25,
I1 => WS_1_2_0_D(1),
I2 => WS_1_0_AM_1(1),
I3 => WS_1_INT_17,
LO => WS_1_0_RN_1(1));
II_ctrl_v_bdrive_1_iv_m9_i_a4_0_2_2_L1: LUT4_L
generic map(
INIT => X"3100"
)
port map (
I0 => BDRIVE_1_IV_M9_I_A4_0_2_1,
I1 => BDRIVE_1_IV_M9_I_A4_0_2_2_1,
I2 => SSRSTATE_1_INT_21,
I3 => BDRIVE_0_SQMUXA_2_C,
LO => BDRIVE_1_IV_M9_I_A4_0_2_2_L1);
II_ctrl_v_bdrive_1_iv_m9_i_a4_0_2_2: LUT4
generic map(
INIT => X"D5F5"
)
port map (
I0 => BDRIVE_1_IV_M9_I_A4_0_2_2_L1,
I1 => UN1_AHBSI_INT_68,
I2 => BDRIVE_1_IV_M9_I_A4_0_2_1,
I3 => HSEL_5_INT_67,
O => BDRIVE_1_TZ);
II_ctrl_v_bdrive_1_iv_m9_i_a4_0_2_2_1_L1: LUT2
generic map(
INIT => X"1"
)
port map (
I0 => SSRSTATE_0_INT_20,
I1 => SSRSTATE_1_INT_21,
O => BDRIVE_1_IV_M9_I_A4_0_2_2_1_L1);
II_ctrl_v_bdrive_1_iv_m9_i_a4_0_2_2_1_L3: LUT4_L
generic map(
INIT => X"1015"
)
port map (
I0 => N_SRO_BDRIVE_3_INT_15,
I1 => D16MUXC_0_4_INT_73,
I2 => PRSTATE_1_INT_28,
I3 => PRSTATE_2_REP1_INT_59,
LO => BDRIVE_1_IV_M9_I_A4_0_2_2_1_L3);
II_ctrl_v_bdrive_1_iv_m9_i_a4_0_2_2_1: LUT4_L
generic map(
INIT => X"0F8F"
)
port map (
I0 => N_668,
I1 => BDRIVE_1_IV_M9_I_A4_0_2_2_1_L1,
I2 => BDRIVE_1_IV_M9_I_A4_0_2_2_1_L3,
I3 => BDRIVE_1_SQMUXA,
LO => BDRIVE_1_IV_M9_I_A4_0_2_2_1);
II_ctrl_v_romsn_1_iv_L1: LUT4_L
generic map(
INIT => X"27FF"
)
port map (
I0 => N_662_INT_60,
I1 => n_ahbsi_hmbsel(0),
I2 => HMBSEL_0_INT_33,
I3 => prstate_1_i_o4_s(2),
LO => ROMSN_1_IV_L1);
II_ctrl_v_iosn_9_iv_L1: LUT4_L
generic map(
INIT => X"27FF"
)
port map (
I0 => N_662_INT_60,
I1 => n_ahbsi_hmbsel(2),
I2 => HMBSEL_2_INT_35,
I3 => prstate_1_i_o4_s(2),
LO => IOSN_9_IV_L1);
II_ctrl_v_ssrstate6_xx_mm_m3_L1: LUT2
generic map(
INIT => X"7"
)
port map (
I0 => HMBSEL_1_INT_34,
I1 => HSEL_INT_58,
O => SSRSTATE6_XX_MM_M3_L1);
II_ctrl_v_ssrstate6_xx_mm_m3_L3: LUT4
generic map(
INIT => X"4FFF"
)
port map (
I0 => n_ahbsi_hmbsel(1),
I1 => n_ahbsi_hready,
I2 => PRSTATE_5_INT_32,
I3 => SSRSTATE_4_INT_24,
O => SSRSTATE6_XX_MM_M3_L3);
II_ctrl_v_ssrstate6_xx_mm_m3: LUT4
generic map(
INIT => X"CEFE"
)
port map (
I0 => SSRSTATE6_XX_MM_M3_L1,
I1 => SSRSTATE6_XX_MM_M3_L3,
I2 => n_ahbsi_hready,
I3 => hsel_4,
O => SSRSTATE6_XX_MM_M3_INT_64);
II_v_ws_2_sqmuxa_3_0: LUT4
generic map(
INIT => X"0700"
)
port map (
I0 => g0_30,
I1 => WS_0_SQMUXA_1_INT_57,
I2 => WS_2_SQMUXA_3_0_SX,
I3 => WS_2_SQMUXA_3_D_INT_56,
O => N_371_INT_71);
II_v_ws_2_sqmuxa_3_0_sx: LUT4_L
generic map(
INIT => X"CF4F"
)
port map (
I0 => SSRSTATE_2_I_INT_55,
I1 => WS_0_SQMUXA_1_INT_57,
I2 => WS_2_SQMUXA_3_0_2_INT_54,
I3 => WS_3_SQMUXA_1_INT_53,
LO => WS_2_SQMUXA_3_0_SX);
II_v_ws_2_sqmuxa_3_0_x: LUT3_L
generic map(
INIT => X"70"
)
port map (
I0 => g0_30,
I1 => WS_0_SQMUXA_1_INT_57,
I2 => WS_2_SQMUXA_3_D_INT_56,
LO => ws_2_sqmuxa_3_0_x);
II_ctrl_v_hmbsel_4_x1HAKL1HAKR: LUT4_L
generic map(
INIT => X"BF80"
)
port map (
I0 => n_ahbsi_hmbsel(1),
I1 => n_ahbsi_hready,
I2 => n_ahbsi_hsel(0),
I3 => HMBSEL_1_INT_34,
LO => HMBSEL_4_X1(1));
II_un1_v_ssrstate17_2_0_m6_i_1: LUT4
generic map(
INIT => X"4F0F"
)
port map (
I0 => n_ahbsi_hready,
I1 => n_ahbsi_htrans(0),
I2 => SSRSTATE_2_INT_22,
I3 => SSRSTATE17_2_0_M6_I_A3_A0_1,
O => ssrstate17_2_0_m6_i_1);
II_ctrl_v_change_3_f1_d_0_L1: LUT4_L
generic map(
INIT => X"4440"
)
port map (
I0 => UN1_AHBSI_INT_68,
I1 => HSEL_5_INT_67,
I2 => SSRSTATE_1_INT_21,
I3 => SSRSTATE_2_INT_22,
LO => CHANGE_3_F1_D_0_L1);
II_ctrl_v_change_3_f1_d_0: LUT4
generic map(
INIT => X"00F2"
)
port map (
I0 => CHANGE_3_F1_D_0_L1,
I1 => HMBSEL_4_1_INT_14,
I2 => CHANGE_INT_69,
I3 => SSRSTATE_4_INT_24,
O => CHANGE_3);
II_ctrl_un1_v_ssrstate17: LUT4
generic map(
INIT => X"E000"
)
port map (
I0 => n_ahbsi_htrans(0),
I1 => n_ahbsi_htrans(1),
I2 => HMBSEL_4_1_INT_14,
I3 => HSEL_5_INT_67,
O => N_654);
II_un1_v_writen_2_sqmuxa_L1: LUT2
generic map(
INIT => X"1"
)
port map (
I0 => PRSTATE_1_INT_28,
I1 => PRSTATE_2_INT_29,
O => WRITEN_2_SQMUXA_L1);
II_un1_v_writen_2_sqmuxa_L3: LUT2
generic map(
INIT => X"4"
)
port map (
I0 => n_ahbsi_htrans(0),
I1 => n_ahbsi_htrans(1),
O => WRITEN_2_SQMUXA_L3);
II_un1_v_writen_2_sqmuxa_L5: LUT4
generic map(
INIT => X"7F00"
)
port map (
I0 => WRITEN_2_SQMUXA_L3,
I1 => HMBSEL_4_1_INT_14,
I2 => HSEL_5_INT_67,
I3 => SSRSTATE_2_INT_22,
O => WRITEN_2_SQMUXA_L5);
II_un1_v_writen_2_sqmuxa: LUT4
generic map(
INIT => X"7555"
)
port map (
I0 => WRITEN_2_SQMUXA_L1,
I1 => WRITEN_2_SQMUXA_L5,
I2 => WRITEN_2_SQMUXA_TZ_0,
I3 => BWN_1_SQMUXA_2_D_0,
O => WRITEN_2_SQMUXA);
II_ctrl_v_ws_1_L1_L1: LUT3_L
generic map(
INIT => X"37"
)
port map (
I0 => g0_30,
I1 => WS_0_SQMUXA_1_INT_57,
I2 => WS_3_SQMUXA_1_INT_53,
LO => WS_1_L1_L1);
II_ctrl_v_ws_1_L1: LUT4_L
generic map(
INIT => X"B11B"
)
port map (
I0 => g0_25,
I1 => WS_1_2_0_D(2),
I2 => WS_1_L1_L1,
I3 => WS_2_INT_18,
LO => WS_1_L1);
II_v_ws_2_sqmuxa_3_0_2_L1: LUT4
generic map(
INIT => X"0013"
)
port map (
I0 => N_SRO_ROMSN_0_INT_12,
I1 => PRSTATE_1_INT_28,
I2 => ws_2_sqmuxa_0,
I3 => ws_4_sqmuxa_0,
O => WS_2_SQMUXA_3_0_2_L1);
II_v_ws_2_sqmuxa_3_0_2: LUT4
generic map(
INIT => X"003B"
)
port map (
I0 => WS_2_SQMUXA_3_0_2_L1,
I1 => rst,
I2 => PRSTATE_3_INT_30,
I3 => WS_1_SQMUXA_INT_52,
O => WS_2_SQMUXA_3_0_2_INT_54);
II_ctrl_v_ws_1_L1_0: LUT3
generic map(
INIT => X"57"
)
port map (
I0 => g0_25,
I1 => WS_0_INT_16,
I2 => WS_1_INT_17,
O => WS_1_L1_0);
II_ctrl_v_ssrhready_8_f0_L5: LUT3_L
generic map(
INIT => X"2F"
)
port map (
I0 => n_ahbsi_htrans(0),
I1 => ssrstate17_1_xx_mm_N_4,
I2 => SSRSTATE_1_INT_21,
LO => ssrhready_8_f0_L5);
II_ctrl_v_ssrhready_8_f0_L8: LUT4
generic map(
INIT => X"0013"
)
port map (
I0 => D16MUXC_0_4_INT_73,
I1 => SSRHREADY_INT_51,
I2 => SSRSTATE_3_INT_23,
I3 => ssrstate_1_sqmuxa_1,
O => ssrhready_8_f0_L8);
II_un1_v_hsel_1_0_L3: LUT2_L
generic map(
INIT => X"1"
)
port map (
I0 => n_ahbsi_hmbsel(0),
I1 => n_ahbsi_hmbsel(2),
LO => hsel_1_0_L3);
II_un1_v_ssrstate6_1_d_0_L1: LUT3
generic map(
INIT => X"40"
)
port map (
I0 => n_ahbsi_htrans(0),
I1 => n_ahbsi_htrans(1),
I2 => SSRSTATE_2_INT_22,
O => SSRSTATE6_1_D_0_L1_INT_65);
II_v_ws_3_sqmuxa_0: LUT4
generic map(
INIT => X"8B03"
)
port map (
I0 => n_ahbsi_hmbsel(1),
I1 => n_ahbsi_hready,
I2 => WS_3_SQMUXA_0_1,
I3 => WS_3_SQMUXA_1_A0_2,
O => WS_3_SQMUXA_1_INT_53);
II_v_ws_3_sqmuxa_0_1: LUT3
generic map(
INIT => X"7F"
)
port map (
I0 => d_m1_e_0_0,
I1 => n_ahbsi_htrans(0),
I2 => SSRSTATE_1_INT_21,
O => WS_3_SQMUXA_0_1);
II_un1_r_prstate_8: LUT4
generic map(
INIT => X"0301"
)
port map (
I0 => N_SRO_ROMSN_0_INT_12,
I1 => PRSTATE_0_INT_27,
I2 => PRSTATE_5_INT_32,
I3 => PRSTATE_8_1,
O => N_656_INT_66);
II_un1_r_prstate_8_1: LUT3_L
generic map(
INIT => X"57"
)
port map (
I0 => N_SRO_IOSN_INT_70,
I1 => PRSTATE_4_INT_31,
I2 => PRSTATE_FAST_2_INT_13,
LO => PRSTATE_8_1);
II_v_mcfg1_bexcen_1_sqmuxa_i: LUT4
generic map(
INIT => X"B333"
)
port map (
I0 => n_apbi_pwrite,
I1 => rst,
I2 => N_APBO_PRDATA_28_INT_11,
I3 => BEXCEN_1_SQMUXA_I_1,
O => BEXCEN_1_SQMUXA_I);
II_v_mcfg1_bexcen_1_sqmuxa_i_1: LUT4
generic map(
INIT => X"1000"
)
port map (
I0 => n_apbi_paddr(4),
I1 => n_apbi_paddr(5),
I2 => n_apbi_penable,
I3 => n_apbi_psel(0),
O => BEXCEN_1_SQMUXA_I_1);
II_un1_v_ssrstate_1_sqmuxa_1_0_m3_0_1: LUT4
generic map(
INIT => X"0D08"
)
port map (
I0 => n_ahbsi_hready,
I1 => n_ahbsi_hsel(0),
I2 => n_ahbsi_htrans(0),
I3 => HSEL_INT_58,
O => ssrstate_1_sqmuxa_1_0_m3_0_1);
II_un1_r_prstate: LUT4
generic map(
INIT => X"1911"
)
port map (
I0 => PRSTATE_5_INT_32,
I1 => PRSTATE_1,
I2 => PRSTATE_12_M7_I_A6_0,
I3 => hsel_1(0),
O => PRSTATE_12_I);
II_un1_r_prstate_1_0: LUT4
generic map(
INIT => X"0343"
)
port map (
I0 => HWRITE_1,
I1 => PRSTATE_5_INT_32,
I2 => PRSTATE_12_0,
I3 => PRSTATE_12_M7_I_A6,
O => PRSTATE_1);
II_ctrl_v_ws_1_0_am_1HAKL1HAKR: LUT4_L
generic map(
INIT => X"0515"
)
port map (
I0 => WS_0_INT_16,
I1 => g0_30,
I2 => WS_0_SQMUXA_1_INT_57,
I3 => WS_3_SQMUXA_1_INT_53,
LO => WS_1_0_AM_1(1));
II_r_d16muxc_0_1_0: LUT4
generic map(
INIT => X"0110"
)
port map (
I0 => PRSTATE_1_INT_28,
I1 => PRSTATE_4_INT_31,
I2 => SIZE_0_INT_25,
I3 => SIZE_1_INT_26,
O => D16MUXC_0_1_0);
II_r_acount_lm_0_1HAKL0HAKR: LUT3
generic map(
INIT => X"27"
)
port map (
I0 => N_662_INT_60,
I1 => n_ahbsi_haddr(2),
I2 => HADDR(2),
O => ACOUNT_LM_0_1(0));
II_v_N_635_i_1: LUT3_L
generic map(
INIT => X"0D"
)
port map (
I0 => SSRSTATE_1_INT_21,
I1 => loadcount_1_sqmuxa,
I2 => ssrstate_1_sqmuxa_1,
LO => N_635_I_1);
II_ctrl_v_oen_1_iv: LUT3_L
generic map(
INIT => X"E2"
)
port map (
I0 => SSRSTATE6_XX_MM_M3_INT_64,
I1 => PRSTATE_12_I,
I2 => PRSTATE_1_SQMUXA,
LO => OEN_1);
II_ctrl_v_N_617_i: LUT4_L
generic map(
INIT => X"0FBF"
)
port map (
I0 => N_646,
I1 => n_ahbsi_hwrite,
I2 => BWN_1_0_0(3),
I3 => bwn_1_sqmuxa_2_d_0_2,
LO => N_617_I);
II_ctrl_v_hwdataout_1_0HAKL0HAKR: LUT4_L
generic map(
INIT => X"E2F0"
)
port map (
I0 => n_ahbsi_hwdata(0),
I1 => BUS16EN_INT_72,
I2 => HWDATA(0),
I3 => PRSTATE_2_INT_29,
LO => HWDATAOUT_1(0));
II_ctrl_v_hwdataout_1_0HAKL1HAKR: LUT4_L
generic map(
INIT => X"E2F0"
)
port map (
I0 => n_ahbsi_hwdata(1),
I1 => BUS16EN_INT_72,
I2 => HWDATA(1),
I3 => PRSTATE_2_INT_29,
LO => HWDATAOUT_1(1));
II_ctrl_v_hwdataout_1_0HAKL2HAKR: LUT4_L
generic map(
INIT => X"E2F0"
)
port map (
I0 => n_ahbsi_hwdata(2),
I1 => BUS16EN_INT_72,
I2 => HWDATA(2),
I3 => PRSTATE_2_INT_29,
LO => HWDATAOUT_1(2));
II_ctrl_v_hwdataout_1_0HAKL3HAKR: LUT4_L
generic map(
INIT => X"E2F0"
)
port map (
I0 => n_ahbsi_hwdata(3),
I1 => BUS16EN_INT_72,
I2 => HWDATA(3),
I3 => PRSTATE_2_INT_29,
LO => HWDATAOUT_1(3));
II_ctrl_v_hwdataout_1_0HAKL4HAKR: LUT4_L
generic map(
INIT => X"E2F0"
)
port map (
I0 => n_ahbsi_hwdata(4),
I1 => BUS16EN_INT_72,
I2 => HWDATA(4),
I3 => PRSTATE_2_INT_29,
LO => HWDATAOUT_1(4));
II_ctrl_v_hwdataout_1_0HAKL5HAKR: LUT4_L
generic map(
INIT => X"E2F0"
)
port map (
I0 => n_ahbsi_hwdata(5),
I1 => BUS16EN_INT_72,
I2 => HWDATA(5),
I3 => PRSTATE_2_INT_29,
LO => HWDATAOUT_1(5));
II_ctrl_v_hwdataout_1_0HAKL6HAKR: LUT4_L
generic map(
INIT => X"E2F0"
)
port map (
I0 => n_ahbsi_hwdata(6),
I1 => BUS16EN_INT_72,
I2 => HWDATA(6),
I3 => PRSTATE_2_INT_29,
LO => HWDATAOUT_1(6));
II_ctrl_v_hwdataout_1_0HAKL7HAKR: LUT4_L
generic map(
INIT => X"E2F0"
)
port map (
I0 => n_ahbsi_hwdata(7),
I1 => BUS16EN_INT_72,
I2 => HWDATA(7),
I3 => PRSTATE_2_INT_29,
LO => HWDATAOUT_1(7));
II_ctrl_v_hwdataout_1_0HAKL8HAKR: LUT4_L
generic map(
INIT => X"E2F0"
)
port map (
I0 => n_ahbsi_hwdata(8),
I1 => BUS16EN_INT_72,
I2 => HWDATA(8),
I3 => PRSTATE_2_INT_29,
LO => HWDATAOUT_1(8));
II_ctrl_v_hwdataout_1_0HAKL9HAKR: LUT4_L
generic map(
INIT => X"E2F0"
)
port map (
I0 => n_ahbsi_hwdata(9),
I1 => BUS16EN_INT_72,
I2 => HWDATA(9),
I3 => PRSTATE_2_INT_29,
LO => HWDATAOUT_1(9));
II_ctrl_v_hwdataout_1_0HAKL10HAKR: LUT4_L
generic map(
INIT => X"E2F0"
)
port map (
I0 => n_ahbsi_hwdata(10),
I1 => BUS16EN_INT_72,
I2 => HWDATA(10),
I3 => PRSTATE_2_INT_29,
LO => HWDATAOUT_1(10));
II_ctrl_v_hwdataout_1_0HAKL11HAKR: LUT4_L
generic map(
INIT => X"E2F0"
)
port map (
I0 => n_ahbsi_hwdata(11),
I1 => BUS16EN_INT_72,
I2 => HWDATA(11),
I3 => PRSTATE_2_INT_29,
LO => HWDATAOUT_1(11));
II_ctrl_v_hwdataout_1_0HAKL12HAKR: LUT4_L
generic map(
INIT => X"E2F0"
)
port map (
I0 => n_ahbsi_hwdata(12),
I1 => BUS16EN_INT_72,
I2 => HWDATA(12),
I3 => PRSTATE_2_INT_29,
LO => HWDATAOUT_1(12));
II_ctrl_v_hwdataout_1_0HAKL13HAKR: LUT4_L
generic map(
INIT => X"E2F0"
)
port map (
I0 => n_ahbsi_hwdata(13),
I1 => BUS16EN_INT_72,
I2 => HWDATA(13),
I3 => PRSTATE_2_INT_29,
LO => HWDATAOUT_1(13));
II_ctrl_v_hwdataout_1_0HAKL14HAKR: LUT4_L
generic map(
INIT => X"E2F0"
)
port map (
I0 => n_ahbsi_hwdata(14),
I1 => BUS16EN_INT_72,
I2 => HWDATA(14),
I3 => PRSTATE_2_INT_29,
LO => HWDATAOUT_1(14));
II_ctrl_v_hwdataout_1_0HAKL15HAKR: LUT4_L
generic map(
INIT => X"E2F0"
)
port map (
I0 => n_ahbsi_hwdata(15),
I1 => BUS16EN_INT_72,
I2 => HWDATA(15),
I3 => PRSTATE_2_INT_29,
LO => HWDATAOUT_1(15));
II_ctrl_v_hwdataout_1_0HAKL16HAKR: LUT3_L
generic map(
INIT => X"AC"
)
port map (
I0 => N_382,
I1 => HWDATA(16),
I2 => PRSTATE_2_INT_29,
LO => HWDATAOUT_1(16));
II_ctrl_v_hwdataout_1_0HAKL17HAKR: LUT3_L
generic map(
INIT => X"AC"
)
port map (
I0 => N_383,
I1 => HWDATA(17),
I2 => PRSTATE_2_INT_29,
LO => HWDATAOUT_1(17));
II_ctrl_v_hwdataout_1_0HAKL18HAKR: LUT3_L
generic map(
INIT => X"AC"
)
port map (
I0 => N_384,
I1 => HWDATA(18),
I2 => PRSTATE_2_INT_29,
LO => HWDATAOUT_1(18));
II_ctrl_v_hwdataout_1_0HAKL19HAKR: LUT3_L
generic map(
INIT => X"AC"
)
port map (
I0 => N_385,
I1 => HWDATA(19),
I2 => PRSTATE_2_INT_29,
LO => HWDATAOUT_1(19));
II_ctrl_v_hwdataout_1_0HAKL20HAKR: LUT3_L
generic map(
INIT => X"AC"
)
port map (
I0 => N_386,
I1 => HWDATA(20),
I2 => PRSTATE_2_INT_29,
LO => HWDATAOUT_1(20));
II_ctrl_v_hwdataout_1_0HAKL21HAKR: LUT3_L
generic map(
INIT => X"AC"
)
port map (
I0 => N_387,
I1 => HWDATA(21),
I2 => PRSTATE_2_INT_29,
LO => HWDATAOUT_1(21));
II_ctrl_v_hwdataout_1_0HAKL22HAKR: LUT3_L
generic map(
INIT => X"AC"
)
port map (
I0 => N_388,
I1 => HWDATA(22),
I2 => PRSTATE_2_INT_29,
LO => HWDATAOUT_1(22));
II_ctrl_v_hwdataout_1_0HAKL23HAKR: LUT3_L
generic map(
INIT => X"AC"
)
port map (
I0 => N_389,
I1 => HWDATA(23),
I2 => PRSTATE_2_INT_29,
LO => HWDATAOUT_1(23));
II_ctrl_v_hwdataout_1_0HAKL24HAKR: LUT3_L
generic map(
INIT => X"AC"
)
port map (
I0 => N_390,
I1 => HWDATA(24),
I2 => PRSTATE_2_INT_29,
LO => HWDATAOUT_1(24));
II_ctrl_v_hwdataout_1_0HAKL25HAKR: LUT3_L
generic map(
INIT => X"AC"
)
port map (
I0 => N_391,
I1 => HWDATA(25),
I2 => PRSTATE_2_INT_29,
LO => HWDATAOUT_1(25));
II_ctrl_v_hwdataout_1_0HAKL26HAKR: LUT3_L
generic map(
INIT => X"AC"
)
port map (
I0 => N_392,
I1 => HWDATA(26),
I2 => PRSTATE_2_INT_29,
LO => HWDATAOUT_1(26));
II_ctrl_v_hwdataout_1_0HAKL27HAKR: LUT3_L
generic map(
INIT => X"AC"
)
port map (
I0 => N_393,
I1 => HWDATA(27),
I2 => PRSTATE_2_INT_29,
LO => HWDATAOUT_1(27));
II_ctrl_v_hwdataout_1_0HAKL28HAKR: LUT3_L
generic map(
INIT => X"AC"
)
port map (
I0 => N_394,
I1 => HWDATA(28),
I2 => PRSTATE_2_INT_29,
LO => HWDATAOUT_1(28));
II_ctrl_v_hwdataout_1_0HAKL29HAKR: LUT3_L
generic map(
INIT => X"AC"
)
port map (
I0 => N_395,
I1 => HWDATA(29),
I2 => PRSTATE_2_INT_29,
LO => HWDATAOUT_1(29));
II_ctrl_v_hwdataout_1_0HAKL30HAKR: LUT3_L
generic map(
INIT => X"AC"
)
port map (
I0 => N_396,
I1 => HWDATA(30),
I2 => PRSTATE_2_INT_29,
LO => HWDATAOUT_1(30));
II_ctrl_v_hwdataout_1_0HAKL31HAKR: LUT3_L
generic map(
INIT => X"AC"
)
port map (
I0 => N_397,
I1 => HWDATA(31),
I2 => PRSTATE_2_INT_29,
LO => HWDATAOUT_1(31));
II_ctrl_v_mcfg1_N_626_i: LUT2_L
generic map(
INIT => X"B"
)
port map (
I0 => n_apbi_pwdata_4,
I1 => rst,
LO => N_626_I);
II_ctrl_v_mcfg1_N_625_i: LUT2_L
generic map(
INIT => X"B"
)
port map (
I0 => n_apbi_pwdata_5,
I1 => rst,
LO => N_625_I);
II_ctrl_v_mcfg1_N_624_i: LUT2_L
generic map(
INIT => X"B"
)
port map (
I0 => n_apbi_pwdata_6,
I1 => rst,
LO => N_624_I);
II_ctrl_v_mcfg1_N_623_i: LUT2_L
generic map(
INIT => X"B"
)
port map (
I0 => n_apbi_pwdata_7,
I1 => rst,
LO => N_623_I);
II_ctrl_v_mcfg1_N_630_i: LUT2_L
generic map(
INIT => X"B"
)
port map (
I0 => n_apbi_pwdata_0,
I1 => rst,
LO => N_630_I);
II_ctrl_v_mcfg1_N_629_i: LUT2_L
generic map(
INIT => X"B"
)
port map (
I0 => n_apbi_pwdata_1,
I1 => rst,
LO => N_629_I);
II_ctrl_v_mcfg1_N_628_i: LUT2_L
generic map(
INIT => X"B"
)
port map (
I0 => n_apbi_pwdata_2,
I1 => rst,
LO => N_628_I);
II_ctrl_v_mcfg1_N_627_i: LUT2_L
generic map(
INIT => X"B"
)
port map (
I0 => n_apbi_pwdata_3,
I1 => rst,
LO => N_627_I);
II_ctrl_v_mcfg1_iows_1HAKL0HAKR: LUT2_L
generic map(
INIT => X"8"
)
port map (
I0 => n_apbi_pwdata_20,
I1 => rst,
LO => IOWS_1(0));
II_ctrl_v_mcfg1_iows_1HAKL1HAKR: LUT2_L
generic map(
INIT => X"8"
)
port map (
I0 => n_apbi_pwdata_21,
I1 => rst,
LO => IOWS_1(1));
II_ctrl_v_mcfg1_iows_1HAKL2HAKR: LUT2_L
generic map(
INIT => X"8"
)
port map (
I0 => n_apbi_pwdata_22,
I1 => rst,
LO => IOWS_1(2));
II_ctrl_v_mcfg1_iows_1HAKL3HAKR: LUT2_L
generic map(
INIT => X"8"
)
port map (
I0 => n_apbi_pwdata_23,
I1 => rst,
LO => IOWS_1(3));
II_ctrl_v_mcfg1_romwidth_1_0HAKL0HAKR: LUT3_L
generic map(
INIT => X"AC"
)
port map (
I0 => n_apbi_pwdata_8,
I1 => n_sri_bwidth(0),
I2 => rst,
LO => ROMWIDTH_1(0));
II_ctrl_v_mcfg1_romwidth_1_0HAKL1HAKR: LUT3_L
generic map(
INIT => X"AC"
)
port map (
I0 => n_apbi_pwdata_9,
I1 => n_sri_bwidth(1),
I2 => rst,
LO => ROMWIDTH_1(1));
II_ctrl_v_mcfg1_romwrite_1: LUT2_L
generic map(
INIT => X"8"
)
port map (
I0 => n_apbi_pwdata_11,
I1 => rst,
LO => ROMWRITE_1);
II_ctrl_v_mcfg1_ioen_1: LUT2_L
generic map(
INIT => X"8"
)
port map (
I0 => n_apbi_pwdata_19,
I1 => rst,
LO => IOEN_1);
II_ctrl_v_ssrstate_1_0HAKL2HAKR: LUT4_L
generic map(
INIT => X"8A80"
)
port map (
I0 => rst,
I1 => D16MUXC_0_4_INT_73,
I2 => SSRSTATE_3_INT_23,
I3 => SSRSTATE_6_SQMUXA_INT_61,
LO => SSRSTATE_1(2));
II_ctrl_v_bdrive_1_iv_m9_i: LUT4_L
generic map(
INIT => X"1000"
)
port map (
I0 => BDRIVE_1_IV_0_A0,
I1 => BDRIVE_1_IV_0_A1,
I2 => BDRIVE_1_IV_M9_I_0_0,
I3 => BDRIVE_1_TZ,
LO => BDRIVE_1);
II_r_acount_lm_0HAKL1HAKR: LUT3_L
generic map(
INIT => X"D8"
)
port map (
I0 => loadcount_7,
I1 => NN_1,
I2 => ACOUNT_S(1),
LO => ACOUNT_LM(1));
II_r_acount_lm_0HAKL2HAKR: LUT3_L
generic map(
INIT => X"D8"
)
port map (
I0 => loadcount_7,
I1 => NN_2,
I2 => ACOUNT_S(2),
LO => ACOUNT_LM(2));
II_r_acount_lm_0HAKL3HAKR: LUT3_L
generic map(
INIT => X"D8"
)
port map (
I0 => loadcount_7,
I1 => NN_3,
I2 => ACOUNT_S(3),
LO => ACOUNT_LM(3));
II_r_acount_lm_0HAKL4HAKR: LUT3_L
generic map(
INIT => X"D8"
)
port map (
I0 => loadcount_7,
I1 => NN_4,
I2 => ACOUNT_S(4),
LO => ACOUNT_LM(4));
II_r_acount_lm_0HAKL5HAKR: LUT3_L
generic map(
INIT => X"D8"
)
port map (
I0 => loadcount_7,
I1 => NN_5,
I2 => ACOUNT_S(5),
LO => ACOUNT_LM(5));
II_r_acount_lm_0HAKL6HAKR: LUT3_L
generic map(
INIT => X"D8"
)
port map (
I0 => loadcount_7,
I1 => NN_6,
I2 => ACOUNT_S(6),
LO => ACOUNT_LM(6));
II_r_acount_lm_0HAKL7HAKR: LUT3_L
generic map(
INIT => X"D8"
)
port map (
I0 => loadcount_7,
I1 => NN_7,
I2 => ACOUNT_S(7),
LO => ACOUNT_LM(7));
II_r_acount_lm_0HAKL8HAKR: LUT3_L
generic map(
INIT => X"D8"
)
port map (
I0 => loadcount_7,
I1 => NN_8,
I2 => ACOUNT_S(8),
LO => ACOUNT_LM(8));
II_r_acount_lm_0HAKL9HAKR: LUT3_L
generic map(
INIT => X"D8"
)
port map (
I0 => loadcount_7,
I1 => NN_9,
I2 => ACOUNT_S(9),
LO => ACOUNT_LM(9));
II_r_d16muxc: LUT3_L
generic map(
INIT => X"40"
)
port map (
I0 => un7_bus16en,
I1 => D16MUXC_1,
I2 => D16MUXC_2,
LO => D16MUXC);
II_rbdrivec_18: LUT4_L
generic map(
INIT => X"4000"
)
port map (
I0 => BDRIVE_1_IV_0_A0,
I1 => BDRIVE_1_IV_0_1,
I2 => BDRIVE_1_IV_M9_I_0,
I3 => BDRIVE_1_TZ,
LO => RBDRIVEC_18);
II_r_ssrstatec_0: LUT4_L
generic map(
INIT => X"0B08"
)
port map (
I0 => NoName_cnst(0),
I1 => SSRSTATE_5_I,
I2 => ssrstate_2_sqmuxa_1,
I3 => SSRSTATE_11(0),
LO => SSRSTATEC_0);
II_r_prstatec_1: LUT4_L
generic map(
INIT => X"0008"
)
port map (
I0 => SSRSTATE23_1,
I1 => PRSTATE_1_INT_28,
I2 => WS_0_INT_16,
I3 => WS_3_INT_19,
LO => PRSTATEC_1);
II_v_N_337_i: LUT3_L
generic map(
INIT => X"74"
)
port map (
I0 => D16MUXC_0_4_INT_73,
I1 => PRSTATE_1_INT_28,
I2 => PRSTATE_2_INT_29,
LO => N_337_I);
II_r_prstatec_0: LUT4_L
generic map(
INIT => X"A2A0"
)
port map (
I0 => N_336,
I1 => CHANGE_3,
I2 => PRSTATE_0_INT_27,
I3 => prstate_1_i_o4_s(2),
LO => PRSTATEC_0);
II_r_prstatec: LUT3_L
generic map(
INIT => X"0E"
)
port map (
I0 => PRSTATE_3_INT_30,
I1 => PRSTATE_4_INT_31,
I2 => d16mux_0_sqmuxa,
LO => PRSTATEC);
II_v_prstate_1_0_a3_0HAKL4HAKR: LUT4_L
generic map(
INIT => X"0200"
)
port map (
I0 => rst,
I1 => HWRITE_1,
I2 => CHANGE_3,
I3 => prstate_1_i_o4_s(2),
LO => N_342);
II_r_prstates_i: LUT4_L
generic map(
INIT => X"8FCF"
)
port map (
I0 => CHANGE_3,
I1 => PRSTATE_5_INT_32,
I2 => PRSTATESR_0,
I3 => hsel_1(0),
LO => PRSTATES_I);
II_r_acount_qxuHAKL9HAKR: LUT1
generic map(
INIT => X"2"
)
port map (
I0 => N_SRO_ADDRESS_11_INT_47,
O => ACOUNT_QXU(9));
II_un1_v_ssrstate23_u_0HAKL4HAKR: MUXF5 port map (
I0 => SSRSTATE23_U_0_AM(4),
I1 => SSRSTATE23_U_0_BM(4),
S => SSRSTATE_5_I,
O => ssrstate_1_m1(4));
II_v_bwn_1_sqmuxa_3_i: LUT4
generic map(
INIT => X"D555"
)
port map (
I0 => bwn_0_sqmuxa_1,
I1 => BWN_1_SQMUXA_2_D_0,
I2 => WRITEN_0_SQMUXA_0_2,
I3 => WRITEN_0_SQMUXA_D,
O => BWN_1_SQMUXA_3_I);
II_rbdrivec_19: LUT4
generic map(
INIT => X"4000"
)
port map (
I0 => BDRIVE_1_IV_0_A0,
I1 => BDRIVE_1_IV_0_1,
I2 => BDRIVE_1_IV_M9_I_0,
I3 => BDRIVE_1_TZ,
O => RBDRIVEC);
II_ctrl_v_ssrstate_1_m2s2_0: LUT4_L
generic map(
INIT => X"0010"
)
port map (
I0 => NoName_cnst(0),
I1 => SSRSTATE_1_INT_21,
I2 => change_1_sqmuxa_0,
I3 => SSRSTATE_6_SQMUXA_INT_61,
LO => SSRSTATE_1_M2S2_0);
II_ctrl_v_bwn_1_0_0HAKL3HAKR: LUT3
generic map(
INIT => X"C8"
)
port map (
I0 => hsize_1(1),
I1 => BWN_1_0_O3(1),
I2 => haddr_0,
O => BWN_1_0_0(3));
II_v_ws_2_sqmuxa_3_0_4: LUT4
generic map(
INIT => X"30B0"
)
port map (
I0 => SSRSTATE_2_I_INT_55,
I1 => WS_0_SQMUXA_1_INT_57,
I2 => WS_2_SQMUXA_3_0_2_INT_54,
I3 => WS_3_SQMUXA_1_INT_53,
O => ws_2_sqmuxa_3_0_4);
II_un1_v_N_599_i: LUT4
generic map(
INIT => X"FF8F"
)
port map (
I0 => D16MUXC_0_4_INT_73,
I1 => PRSTATE_1_INT_28,
I2 => HADDR_0_SQMUXA_A0_0,
I3 => PRSTATE_1_SQMUXA,
O => N_599_I);
II_ctrl_v_ssrstate_1_0_d_bmHAKL3HAKR: LUT2
generic map(
INIT => X"1"
)
port map (
I0 => n_ahbsi_hwrite,
I1 => ssrstate_1_sqmuxa_1,
O => SSRSTATE_1_0_D_BM(3));
II_ctrl_v_ssrstate_1_0_d_amHAKL3HAKR: LUT3
generic map(
INIT => X"20"
)
port map (
I0 => rst,
I1 => D16MUXC_0_4_INT_73,
I2 => SSRSTATE_3_INT_23,
O => SSRSTATE_1_0_D_AM(3));
II_v_writen_0_sqmuxa_0_2: LUT4
generic map(
INIT => X"0E00"
)
port map (
I0 => n_ahbsi_hwrite,
I1 => SSRSTATE6_XX_MM_M3_INT_64,
I2 => ssrstate_1_sqmuxa_1,
I3 => WRITEN_0_SQMUXA_0_0,
O => WRITEN_0_SQMUXA_0_2);
II_un1_r_ssrstate_12_1: LUT4
generic map(
INIT => X"0111"
)
port map (
I0 => SSRSTATE_3_INT_23,
I1 => BDRIVE_1_SQMUXA_2,
I2 => WS_0_SQMUXA_0_0_0,
I3 => WS_0_SQMUXA_0_C_INT_50,
O => SSRSTATE_12_1);
II_v_ws_2_sqmuxa_3_d: LUT4
generic map(
INIT => X"4FFF"
)
port map (
I0 => UN1_AHBSI_INT_68,
I1 => HSEL_5_INT_67,
I2 => SSRSTATE_1_INT_21,
I3 => WS_0_SQMUXA_1_INT_57,
O => WS_2_SQMUXA_3_D_INT_56);
II_un1_v_writen_2_sqmuxa_tz_0: LUT4
generic map(
INIT => X"00E0"
)
port map (
I0 => n_ahbsi_hwrite,
I1 => SSRSTATE6_XX_MM_M3_INT_64,
I2 => SSRSTATE_2_I_INT_55,
I3 => WS_3_SQMUXA_1_INT_53,
O => WRITEN_2_SQMUXA_TZ_0);
II_un1_r_ssrstate_9: LUT4
generic map(
INIT => X"0070"
)
port map (
I0 => N_654,
I1 => SSRSTATE_2_INT_22,
I2 => SSRSTATE_2_I_INT_55,
I3 => WS_3_SQMUXA_1_INT_53,
O => SSRSTATE_9);
II_ctrl_v_bdrive_1_iv_m9_i_0_0: LUT2
generic map(
INIT => X"8"
)
port map (
I0 => BDRIVE_1_IV_0_1,
I1 => BDRIVE_1_IV_M9_I_0,
O => BDRIVE_1_IV_M9_I_0_0);
II_un1_r_prstate_12_m7_i_a6_0: LUT4_L
generic map(
INIT => X"0400"
)
port map (
I0 => UN1_AHBSI_INT_68,
I1 => change_3_f0,
I2 => HMBSEL_4_1_INT_14,
I3 => HSEL_5_INT_67,
LO => PRSTATE_12_M7_I_A6_0);
II_v_bwn_1_sqmuxa_2_d_0: LUT4
generic map(
INIT => X"FBFF"
)
port map (
I0 => n_ahbsi_hwrite,
I1 => HMBSEL_4_1_INT_14,
I2 => CHANGE_1_SQMUXA_N_3_INT_63,
I3 => SSRHREADY_2_SQMUXA_0_0_INT_62,
O => BWN_1_SQMUXA_2_D_0);
II_un1_v_ssrstate23_u_0_bmHAKL4HAKR: LUT3
generic map(
INIT => X"B0"
)
port map (
I0 => UN1_AHBSI_INT_68,
I1 => HSEL_5_INT_67,
I2 => SSRSTATE_2_INT_22,
O => SSRSTATE23_U_0_BM(4));
II_un1_v_ssrstate23_u_0_amHAKL4HAKR: LUT3
generic map(
INIT => X"02"
)
port map (
I0 => SSRSTATE23_1,
I1 => WS_0_INT_16,
I2 => WS_3_INT_19,
O => SSRSTATE23_U_0_AM(4));
II_v_writen_0_sqmuxa_d: LUT4
generic map(
INIT => X"40FF"
)
port map (
I0 => UN1_AHBSI_INT_68,
I1 => HMBSEL_4_1_INT_14,
I2 => HSEL_5_INT_67,
I3 => SSRSTATE_2_INT_22,
O => WRITEN_0_SQMUXA_D);
II_ctrl_v_ws_1_2_0_dHAKL1HAKR: LUT3
generic map(
INIT => X"E2"
)
port map (
I0 => N_362,
I1 => N_365,
I2 => ROMRWS(1),
O => WS_1_2_0_D(1));
II_ctrl_v_ws_1_2_0_dHAKL2HAKR: LUT3
generic map(
INIT => X"E2"
)
port map (
I0 => N_363,
I1 => N_365,
I2 => ROMRWS(2),
O => WS_1_2_0_D(2));
II_r_prstatesr_0: LUT3
generic map(
INIT => X"0B"
)
port map (
I0 => un7_bus16en,
I1 => PRSTATE_0_INT_27,
I2 => PRSTATE_1_SQMUXA,
O => PRSTATESR_0);
II_un1_v_haddr_0_sqmuxa_a0_0: LUT3
generic map(
INIT => X"07"
)
port map (
I0 => un7_bus16en,
I1 => PRSTATE_0_INT_27,
I2 => PRSTATE_5_INT_32,
O => HADDR_0_SQMUXA_A0_0);
II_ctrl_v_bdrive_1_iv_0_a1: LUT3
generic map(
INIT => X"40"
)
port map (
I0 => D16MUXC_0_4_INT_73,
I1 => SETBDRIVE,
I2 => BDRIVE_1_SQMUXA,
O => BDRIVE_1_IV_0_A1);
II_v_prstate_1_0_a3HAKL4HAKR: LUT3
generic map(
INIT => X"80"
)
port map (
I0 => rst,
I1 => un7_bus16en,
I2 => d16mux_0_sqmuxa,
O => N_341);
II_v_bdrive_0_sqmuxa_2_0: LUT4
generic map(
INIT => X"FF10"
)
port map (
I0 => N_668,
I1 => D16MUXC_0_4_INT_73,
I2 => PRSTATE_1_INT_28,
I3 => BDRIVE_0_SQMUXA_2_0_0,
O => BDRIVE_0_SQMUXA_2_C);
II_ctrl_v_bdrive_1_iv_m9_i_0: LUT3
generic map(
INIT => X"13"
)
port map (
I0 => BDRIVE_1_IV_0_A4_0,
I1 => PRSTATE_2_REP1_INT_59,
I2 => BDRIVE_1_SQMUXA,
O => BDRIVE_1_IV_M9_I_0);
II_v_ws_0_sqmuxa_0_0_0: LUT4
generic map(
INIT => X"3133"
)
port map (
I0 => HSEL_5_INT_67,
I1 => D16MUXC_0_4_INT_73,
I2 => SSRSTATE_0_INT_20,
I3 => WS_0_SQMUXA_C_INT_49,
O => WS_0_SQMUXA_0_0_0);
II_v_prhready_0_sqmuxa: LUT3
generic map(
INIT => X"A8"
)
port map (
I0 => un7_bus16en,
I1 => PRSTATE_0_INT_27,
I2 => d16mux_0_sqmuxa,
O => PRHREADY_0_SQMUXA);
II_v_ws_0_sqmuxa_1: LUT2
generic map(
INIT => X"4"
)
port map (
I0 => N_656_INT_66,
I1 => rst,
O => WS_0_SQMUXA_1_INT_57);
II_v_ws_0_sqmuxa_0: LUT4
generic map(
INIT => X"040F"
)
port map (
I0 => UN1_AHBSI_INT_68,
I1 => HSEL_5_INT_67,
I2 => SSRSTATE_0_INT_20,
I3 => SSRSTATE_1_INT_21,
O => SSRSTATE_5_I);
II_v_prstate_1_i_m4_0HAKL2HAKR: LUT3
generic map(
INIT => X"CA"
)
port map (
I0 => HWRITE_1,
I1 => un7_bus16en,
I2 => PRSTATE_0_INT_27,
O => N_336);
II_v_bdrive_1_sqmuxa_2: LUT3
generic map(
INIT => X"40"
)
port map (
I0 => UN1_AHBSI_INT_68,
I1 => HSEL_5_INT_67,
I2 => SSRSTATE_1_INT_21,
O => BDRIVE_1_SQMUXA_2);
II_ctrl_v_bdrive_1_iv_0_a0: LUT4
generic map(
INIT => X"4000"
)
port map (
I0 => UN1_AHBSI_INT_68,
I1 => BDRIVE_1_IV_0_A4_0,
I2 => HSEL_5_INT_67,
I3 => SSRSTATE_1_INT_21,
O => BDRIVE_1_IV_0_A0);
II_ctrl_v_bdrive_1_iv_m9_i_a4_0_2_1: LUT4
generic map(
INIT => X"80A0"
)
port map (
I0 => N_668,
I1 => SSRSTATE10,
I2 => D16MUXC_0_4_INT_73,
I3 => SSRSTATE_3_INT_23,
O => BDRIVE_1_IV_M9_I_A4_0_2_1);
II_v_ws_0_sqmuxa_0_c: LUT2
generic map(
INIT => X"E"
)
port map (
I0 => SSRSTATE_0_INT_20,
I1 => SSRSTATE_1_INT_21,
O => WS_0_SQMUXA_0_C_INT_50);
II_un1_r_prstate_12_m7_i_a6: LUT2
generic map(
INIT => X"8"
)
port map (
I0 => change_3_f0,
I1 => CHANGE_INT_69,
O => PRSTATE_12_M7_I_A6);
II_v_prstate_1_sqmuxa: LUT2
generic map(
INIT => X"4"
)
port map (
I0 => un7_bus16en,
I1 => d16mux_0_sqmuxa,
O => PRSTATE_1_SQMUXA);
II_ctrl_v_hwdataout_1_0_0HAKL16HAKR: LUT4_L
generic map(
INIT => X"ACCC"
)
port map (
I0 => n_ahbsi_hwdata(0),
I1 => n_ahbsi_hwdata(16),
I2 => N_SRO_ADDRESS_1_INT_37,
I3 => BUS16EN_INT_72,
LO => N_382);
II_ctrl_v_hwdataout_1_0_0HAKL17HAKR: LUT4_L
generic map(
INIT => X"ACCC"
)
port map (
I0 => n_ahbsi_hwdata(1),
I1 => n_ahbsi_hwdata(17),
I2 => N_SRO_ADDRESS_1_INT_37,
I3 => BUS16EN_INT_72,
LO => N_383);
II_ctrl_v_hwdataout_1_0_0HAKL18HAKR: LUT4_L
generic map(
INIT => X"ACCC"
)
port map (
I0 => n_ahbsi_hwdata(2),
I1 => n_ahbsi_hwdata(18),
I2 => N_SRO_ADDRESS_1_INT_37,
I3 => BUS16EN_INT_72,
LO => N_384);
II_ctrl_v_hwdataout_1_0_0HAKL19HAKR: LUT4_L
generic map(
INIT => X"ACCC"
)
port map (
I0 => n_ahbsi_hwdata(3),
I1 => n_ahbsi_hwdata(19),
I2 => N_SRO_ADDRESS_1_INT_37,
I3 => BUS16EN_INT_72,
LO => N_385);
II_ctrl_v_hwdataout_1_0_0HAKL20HAKR: LUT4_L
generic map(
INIT => X"ACCC"
)
port map (
I0 => n_ahbsi_hwdata(4),
I1 => n_ahbsi_hwdata(20),
I2 => N_SRO_ADDRESS_1_INT_37,
I3 => BUS16EN_INT_72,
LO => N_386);
II_ctrl_v_hwdataout_1_0_0HAKL21HAKR: LUT4_L
generic map(
INIT => X"ACCC"
)
port map (
I0 => n_ahbsi_hwdata(5),
I1 => n_ahbsi_hwdata(21),
I2 => N_SRO_ADDRESS_1_INT_37,
I3 => BUS16EN_INT_72,
LO => N_387);
II_ctrl_v_hwdataout_1_0_0HAKL22HAKR: LUT4_L
generic map(
INIT => X"ACCC"
)
port map (
I0 => n_ahbsi_hwdata(6),
I1 => n_ahbsi_hwdata(22),
I2 => N_SRO_ADDRESS_1_INT_37,
I3 => BUS16EN_INT_72,
LO => N_388);
II_ctrl_v_hwdataout_1_0_0HAKL23HAKR: LUT4_L
generic map(
INIT => X"ACCC"
)
port map (
I0 => n_ahbsi_hwdata(7),
I1 => n_ahbsi_hwdata(23),
I2 => N_SRO_ADDRESS_1_INT_37,
I3 => BUS16EN_INT_72,
LO => N_389);
II_ctrl_v_hwdataout_1_0_0HAKL24HAKR: LUT4_L
generic map(
INIT => X"ACCC"
)
port map (
I0 => n_ahbsi_hwdata(8),
I1 => n_ahbsi_hwdata(24),
I2 => N_SRO_ADDRESS_1_INT_37,
I3 => BUS16EN_INT_72,
LO => N_390);
II_ctrl_v_hwdataout_1_0_0HAKL25HAKR: LUT4_L
generic map(
INIT => X"ACCC"
)
port map (
I0 => n_ahbsi_hwdata(9),
I1 => n_ahbsi_hwdata(25),
I2 => N_SRO_ADDRESS_1_INT_37,
I3 => BUS16EN_INT_72,
LO => N_391);
II_ctrl_v_hwdataout_1_0_0HAKL26HAKR: LUT4_L
generic map(
INIT => X"ACCC"
)
port map (
I0 => n_ahbsi_hwdata(10),
I1 => n_ahbsi_hwdata(26),
I2 => N_SRO_ADDRESS_1_INT_37,
I3 => BUS16EN_INT_72,
LO => N_392);
II_ctrl_v_hwdataout_1_0_0HAKL27HAKR: LUT4_L
generic map(
INIT => X"ACCC"
)
port map (
I0 => n_ahbsi_hwdata(11),
I1 => n_ahbsi_hwdata(27),
I2 => N_SRO_ADDRESS_1_INT_37,
I3 => BUS16EN_INT_72,
LO => N_393);
II_ctrl_v_hwdataout_1_0_0HAKL28HAKR: LUT4_L
generic map(
INIT => X"ACCC"
)
port map (
I0 => n_ahbsi_hwdata(12),
I1 => n_ahbsi_hwdata(28),
I2 => N_SRO_ADDRESS_1_INT_37,
I3 => BUS16EN_INT_72,
LO => N_394);
II_ctrl_v_hwdataout_1_0_0HAKL29HAKR: LUT4_L
generic map(
INIT => X"ACCC"
)
port map (
I0 => n_ahbsi_hwdata(13),
I1 => n_ahbsi_hwdata(29),
I2 => N_SRO_ADDRESS_1_INT_37,
I3 => BUS16EN_INT_72,
LO => N_395);
II_ctrl_v_hwdataout_1_0_0HAKL30HAKR: LUT4_L
generic map(
INIT => X"ACCC"
)
port map (
I0 => n_ahbsi_hwdata(14),
I1 => n_ahbsi_hwdata(30),
I2 => N_SRO_ADDRESS_1_INT_37,
I3 => BUS16EN_INT_72,
LO => N_396);
II_ctrl_v_hwdataout_1_0_0HAKL31HAKR: LUT4_L
generic map(
INIT => X"ACCC"
)
port map (
I0 => n_ahbsi_hwdata(15),
I1 => n_ahbsi_hwdata(31),
I2 => N_SRO_ADDRESS_1_INT_37,
I3 => BUS16EN_INT_72,
LO => N_397);
II_ctrl_v_bwn_1_0_a3_0_1HAKL0HAKR: LUT4_L
generic map(
INIT => X"0207"
)
port map (
I0 => N_662_INT_60,
I1 => n_ahbsi_hsize(0),
I2 => hsize_1(1),
I3 => SIZE_0_INT_25,
LO => N_319_1);
II_ctrl_v_bwn_1_0_a3HAKL0HAKR: LUT2
generic map(
INIT => X"4"
)
port map (
I0 => hsize_1(1),
I1 => haddr_0,
O => N_317);
II_v_writen_0_sqmuxa_0_0: LUT4
generic map(
INIT => X"4F00"
)
port map (
I0 => n_ahbsi_htrans(0),
I1 => n_ahbsi_htrans(1),
I2 => SSRSTATE_2_INT_22,
I3 => SSRSTATE_2_I_INT_55,
O => WRITEN_0_SQMUXA_0_0);
II_v_ssrhready_2_sqmuxa_0_0: LUT3
generic map(
INIT => X"40"
)
port map (
I0 => n_ahbsi_htrans(0),
I1 => n_ahbsi_htrans(1),
I2 => SSRSTATE_2_INT_22,
O => SSRHREADY_2_SQMUXA_0_0_INT_62);
II_v_bdrive_0_sqmuxa_2_0_0: LUT4_L
generic map(
INIT => X"01FF"
)
port map (
I0 => N_668,
I1 => PRSTATE_1_INT_28,
I2 => PRSTATE_2_REP1_INT_59,
I3 => SETBDRIVE,
LO => BDRIVE_0_SQMUXA_2_0_0);
II_r_d16muxc_0_1: LUT4
generic map(
INIT => X"000E"
)
port map (
I0 => N_SRO_ADDRESS_1_INT_37,
I1 => UN17_BUS16EN,
I2 => PRSTATE_0_INT_27,
I3 => PRSTATE_5_INT_32,
O => D16MUXC_0_1);
II_ctrl_v_bdrive_1_iv_0_1: LUT4
generic map(
INIT => X"BBBF"
)
port map (
I0 => D16MUXC_0_4_INT_73,
I1 => SETBDRIVE,
I2 => SSRSTATE_0_INT_20,
I3 => SSRSTATE_1_INT_21,
O => BDRIVE_1_IV_0_1);
II_v_ssrstate_11HAKL0HAKR: LUT2
generic map(
INIT => X"4"
)
port map (
I0 => D16MUXC_0_4_INT_73,
I1 => SSRSTATE_0_INT_20,
O => SSRSTATE_11(0));
II_v_bdrive_1_sqmuxa: LUT4
generic map(
INIT => X"CC4C"
)
port map (
I0 => SSRSTATE23_1,
I1 => SSRSTATE_3_INT_23,
I2 => WS_0_INT_16,
I3 => WS_3_INT_19,
O => BDRIVE_1_SQMUXA);
II_v_ssrhready_2_sqmuxa_m2: LUT4
generic map(
INIT => X"2A7F"
)
port map (
I0 => n_ahbsi_hready,
I1 => n_ahbsi_hsel(0),
I2 => n_ahbsi_htrans(1),
I3 => HSEL_INT_58,
O => CHANGE_1_SQMUXA_N_3_INT_63);
II_ctrl_hwrite_1_0: LUT3
generic map(
INIT => X"D8"
)
port map (
I0 => N_662_INT_60,
I1 => n_ahbsi_hwrite,
I2 => HWRITE,
O => HWRITE_1);
II_haddr_0HAKL3HAKR: LUT3
generic map(
INIT => X"D8"
)
port map (
I0 => N_662_INT_60,
I1 => n_ahbsi_haddr(3),
I2 => HADDR(3),
O => NN_1);
II_haddr_0HAKL4HAKR: LUT3
generic map(
INIT => X"D8"
)
port map (
I0 => N_662_INT_60,
I1 => n_ahbsi_haddr(4),
I2 => HADDR(4),
O => NN_2);
II_haddr_0HAKL5HAKR: LUT3
generic map(
INIT => X"D8"
)
port map (
I0 => N_662_INT_60,
I1 => n_ahbsi_haddr(5),
I2 => HADDR(5),
O => NN_3);
II_haddr_0HAKL6HAKR: LUT3
generic map(
INIT => X"D8"
)
port map (
I0 => N_662_INT_60,
I1 => n_ahbsi_haddr(6),
I2 => HADDR(6),
O => NN_4);
II_haddr_0HAKL7HAKR: LUT3
generic map(
INIT => X"D8"
)
port map (
I0 => N_662_INT_60,
I1 => n_ahbsi_haddr(7),
I2 => HADDR(7),
O => NN_5);
II_haddr_0HAKL8HAKR: LUT3
generic map(
INIT => X"D8"
)
port map (
I0 => N_662_INT_60,
I1 => n_ahbsi_haddr(8),
I2 => HADDR(8),
O => NN_6);
II_haddr_0HAKL9HAKR: LUT3
generic map(
INIT => X"D8"
)
port map (
I0 => N_662_INT_60,
I1 => n_ahbsi_haddr(9),
I2 => HADDR(9),
O => NN_7);
II_haddr_0HAKL10HAKR: LUT3
generic map(
INIT => X"D8"
)
port map (
I0 => N_662_INT_60,
I1 => n_ahbsi_haddr(10),
I2 => HADDR(10),
O => NN_8);
II_haddr_0HAKL11HAKR: LUT3
generic map(
INIT => X"D8"
)
port map (
I0 => N_662_INT_60,
I1 => n_ahbsi_haddr(11),
I2 => HADDR(11),
O => NN_9);
II_ctrl_v_hsel_5_0: LUT4
generic map(
INIT => X"D580"
)
port map (
I0 => n_ahbsi_hready,
I1 => n_ahbsi_hsel(0),
I2 => n_ahbsi_htrans(1),
I3 => HSEL_INT_58,
O => HSEL_5_INT_67);
II_ctrl_v_ws_1_1_0HAKL2HAKR: LUT4
generic map(
INIT => X"F780"
)
port map (
I0 => N_SRO_ROMSN_0_INT_12,
I1 => rst,
I2 => IOWS(2),
I3 => ROMWWS(2),
O => N_363);
II_ctrl_v_ws_1_1_0HAKL1HAKR: LUT4
generic map(
INIT => X"F780"
)
port map (
I0 => N_SRO_ROMSN_0_INT_12,
I1 => rst,
I2 => IOWS(1),
I3 => ROMWWS(1),
O => N_362);
II_v_ws_3_sqmuxa_1_a0_2: LUT4
generic map(
INIT => X"8000"
)
port map (
I0 => n_ahbsi_hsel(0),
I1 => n_ahbsi_htrans(0),
I2 => n_ahbsi_htrans(1),
I3 => SSRSTATE_1_INT_21,
O => WS_3_SQMUXA_1_A0_2);
II_r_d16muxc_2: LUT3
generic map(
INIT => X"02"
)
port map (
I0 => BUS16EN_INT_72,
I1 => WS_0_INT_16,
I2 => WS_3_INT_19,
O => D16MUXC_2);
II_r_d16muxc_1: LUT4
generic map(
INIT => X"0020"
)
port map (
I0 => PRSTATE_3_INT_30,
I1 => SIZE_0_INT_25,
I2 => SIZE_1_INT_26,
I3 => WS_1_INT_17,
O => D16MUXC_1);
II_un1_v_ssrstate17_2_0_m6_i_a3_a0_1: LUT2
generic map(
INIT => X"4"
)
port map (
I0 => HMBSEL_1_INT_34,
I1 => HSEL_INT_58,
O => SSRSTATE17_2_0_M6_I_A3_A0_1);
II_un1_v_ssrstate17_2_0_m6_i_a3_a2: LUT4
generic map(
INIT => X"4000"
)
port map (
I0 => n_ahbsi_hmbsel(1),
I1 => n_ahbsi_hready,
I2 => n_ahbsi_hsel(0),
I3 => n_ahbsi_htrans(1),
O => ssrstate17_2_0_m6_i_a3_a2);
II_v_ws_1_sqmuxa: LUT3
generic map(
INIT => X"40"
)
port map (
I0 => N_SRO_ROMSN_0_INT_12,
I1 => rst,
I2 => PRSTATE_4_INT_31,
O => WS_1_SQMUXA_INT_52);
II_ctrl_v_ssrstate10: LUT4
generic map(
INIT => X"0002"
)
port map (
I0 => WS_0_INT_16,
I1 => WS_1_INT_17,
I2 => WS_2_INT_18,
I3 => WS_3_INT_19,
O => SSRSTATE10);
II_r_d16muxc_0_4: LUT4
generic map(
INIT => X"0001"
)
port map (
I0 => WS_0_INT_16,
I1 => WS_1_INT_17,
I2 => WS_2_INT_18,
I3 => WS_3_INT_19,
O => D16MUXC_0_4_INT_73);
II_un1_r_ssrstate_3: LUT3
generic map(
INIT => X"8A"
)
port map (
I0 => d_m2_0_a2_0,
I1 => SETBDRIVE,
I2 => SSRSTATE_3_INT_23,
O => SSRSTATE_3);
II_v_ws_0_sqmuxa_c: LUT3
generic map(
INIT => X"EF"
)
port map (
I0 => n_ahbsi_htrans(0),
I1 => n_ahbsi_htrans(1),
I2 => SSRSTATE_1_INT_21,
O => WS_0_SQMUXA_C_INT_49);
II_un1_r_prstate_12_0: LUT3
generic map(
INIT => X"01"
)
port map (
I0 => PRSTATE_0_INT_27,
I1 => PRSTATE_1_INT_28,
I2 => PRSTATE_2_REP1_INT_59,
O => PRSTATE_12_0);
II_regsdHAKL8HAKR: LUT3
generic map(
INIT => X"10"
)
port map (
I0 => n_apbi_paddr(2),
I1 => n_apbi_paddr(3),
I2 => ROMWIDTH(0),
O => n_apbo_prdata_8);
II_regsdHAKL9HAKR: LUT3
generic map(
INIT => X"10"
)
port map (
I0 => n_apbi_paddr(2),
I1 => n_apbi_paddr(3),
I2 => ROMWIDTH(1),
O => n_apbo_prdata_9);
II_regsdHAKL11HAKR: LUT3
generic map(
INIT => X"10"
)
port map (
I0 => n_apbi_paddr(2),
I1 => n_apbi_paddr(3),
I2 => ROMWRITE,
O => n_apbo_prdata_11);
II_regsdHAKL1HAKR: LUT3
generic map(
INIT => X"10"
)
port map (
I0 => n_apbi_paddr(2),
I1 => n_apbi_paddr(3),
I2 => ROMRWS(1),
O => n_apbo_prdata_1);
II_regsdHAKL2HAKR: LUT3
generic map(
INIT => X"10"
)
port map (
I0 => n_apbi_paddr(2),
I1 => n_apbi_paddr(3),
I2 => ROMRWS(2),
O => n_apbo_prdata_2);
II_regsdHAKL3HAKR: LUT3
generic map(
INIT => X"10"
)
port map (
I0 => n_apbi_paddr(2),
I1 => n_apbi_paddr(3),
I2 => ROMRWS_3_INT_10,
O => n_apbo_prdata_3);
II_regsdHAKL5HAKR: LUT3
generic map(
INIT => X"10"
)
port map (
I0 => n_apbi_paddr(2),
I1 => n_apbi_paddr(3),
I2 => ROMWWS(1),
O => n_apbo_prdata_5);
II_regsdHAKL6HAKR: LUT3
generic map(
INIT => X"10"
)
port map (
I0 => n_apbi_paddr(2),
I1 => n_apbi_paddr(3),
I2 => ROMWWS(2),
O => n_apbo_prdata_6);
II_regsdHAKL7HAKR: LUT3
generic map(
INIT => X"10"
)
port map (
I0 => n_apbi_paddr(2),
I1 => n_apbi_paddr(3),
I2 => ROMWWS_3_INT_8,
O => n_apbo_prdata_7);
II_regsdHAKL19HAKR: LUT3
generic map(
INIT => X"10"
)
port map (
I0 => n_apbi_paddr(2),
I1 => n_apbi_paddr(3),
I2 => IOEN,
O => n_apbo_prdata_19);
II_regsdHAKL21HAKR: LUT3
generic map(
INIT => X"10"
)
port map (
I0 => n_apbi_paddr(2),
I1 => n_apbi_paddr(3),
I2 => IOWS(1),
O => n_apbo_prdata_21);
II_regsdHAKL22HAKR: LUT3
generic map(
INIT => X"10"
)
port map (
I0 => n_apbi_paddr(2),
I1 => n_apbi_paddr(3),
I2 => IOWS(2),
O => n_apbo_prdata_22);
II_regsdHAKL23HAKR: LUT3
generic map(
INIT => X"10"
)
port map (
I0 => n_apbi_paddr(2),
I1 => n_apbi_paddr(3),
I2 => IOWS_3_INT_6,
O => n_apbo_prdata_23);
II_regsdHAKL20HAKR: LUT3
generic map(
INIT => X"10"
)
port map (
I0 => n_apbi_paddr(2),
I1 => n_apbi_paddr(3),
I2 => IOWS_0_INT_5,
O => n_apbo_prdata_20);
II_regsdHAKL4HAKR: LUT3
generic map(
INIT => X"10"
)
port map (
I0 => n_apbi_paddr(2),
I1 => n_apbi_paddr(3),
I2 => ROMWWS_0_INT_7,
O => n_apbo_prdata_4);
II_regsdHAKL0HAKR: LUT3
generic map(
INIT => X"10"
)
port map (
I0 => n_apbi_paddr(2),
I1 => n_apbi_paddr(3),
I2 => ROMRWS_0_INT_9,
O => n_apbo_prdata_0);
II_v_hmbsel_0_sqmuxa: LUT2
generic map(
INIT => X"8"
)
port map (
I0 => n_ahbsi_hready,
I1 => hsel_4,
O => HMBSEL_0_SQMUXA);
II_v_data16_0_sqmuxa: LUT2
generic map(
INIT => X"8"
)
port map (
I0 => BUS16EN_INT_72,
I1 => PRSTATE_4_INT_31,
O => DATA16_0_SQMUXA);
II_hrdata_0HAKL31HAKR: LUT3
generic map(
INIT => X"D8"
)
port map (
I0 => D16MUX(0),
I1 => DATA16(15),
I2 => HRDATA(31),
O => n_ahbso_hrdata(31));
II_hrdata_0HAKL30HAKR: LUT3
generic map(
INIT => X"D8"
)
port map (
I0 => D16MUX(0),
I1 => DATA16(14),
I2 => HRDATA(30),
O => n_ahbso_hrdata(30));
II_hrdata_0HAKL29HAKR: LUT3
generic map(
INIT => X"D8"
)
port map (
I0 => D16MUX(0),
I1 => DATA16(13),
I2 => HRDATA(29),
O => n_ahbso_hrdata(29));
II_hrdata_0HAKL28HAKR: LUT3
generic map(
INIT => X"D8"
)
port map (
I0 => D16MUX(0),
I1 => DATA16(12),
I2 => HRDATA(28),
O => n_ahbso_hrdata(28));
II_hrdata_0HAKL27HAKR: LUT3
generic map(
INIT => X"D8"
)
port map (
I0 => D16MUX(0),
I1 => DATA16(11),
I2 => HRDATA(27),
O => n_ahbso_hrdata(27));
II_hrdata_0HAKL26HAKR: LUT3
generic map(
INIT => X"D8"
)
port map (
I0 => D16MUX(0),
I1 => DATA16(10),
I2 => HRDATA(26),
O => n_ahbso_hrdata(26));
II_hrdata_0HAKL25HAKR: LUT3
generic map(
INIT => X"D8"
)
port map (
I0 => D16MUX(0),
I1 => DATA16(9),
I2 => HRDATA(25),
O => n_ahbso_hrdata(25));
II_hrdata_0HAKL24HAKR: LUT3
generic map(
INIT => X"D8"
)
port map (
I0 => D16MUX(0),
I1 => DATA16(8),
I2 => HRDATA(24),
O => n_ahbso_hrdata(24));
II_hrdata_0HAKL23HAKR: LUT3
generic map(
INIT => X"D8"
)
port map (
I0 => D16MUX(0),
I1 => DATA16(7),
I2 => HRDATA(23),
O => n_ahbso_hrdata(23));
II_hrdata_0HAKL22HAKR: LUT3
generic map(
INIT => X"D8"
)
port map (
I0 => D16MUX(0),
I1 => DATA16(6),
I2 => HRDATA(22),
O => n_ahbso_hrdata(22));
II_hrdata_0HAKL21HAKR: LUT3
generic map(
INIT => X"D8"
)
port map (
I0 => D16MUX(0),
I1 => DATA16(5),
I2 => HRDATA(21),
O => n_ahbso_hrdata(21));
II_hrdata_0HAKL20HAKR: LUT3
generic map(
INIT => X"D8"
)
port map (
I0 => D16MUX(0),
I1 => DATA16(4),
I2 => HRDATA(20),
O => n_ahbso_hrdata(20));
II_hrdata_0HAKL19HAKR: LUT3
generic map(
INIT => X"D8"
)
port map (
I0 => D16MUX(0),
I1 => DATA16(3),
I2 => HRDATA(19),
O => n_ahbso_hrdata(19));
II_hrdata_0HAKL18HAKR: LUT3
generic map(
INIT => X"D8"
)
port map (
I0 => D16MUX(0),
I1 => DATA16(2),
I2 => HRDATA(18),
O => n_ahbso_hrdata(18));
II_hrdata_0HAKL17HAKR: LUT3
generic map(
INIT => X"D8"
)
port map (
I0 => D16MUX(0),
I1 => DATA16(1),
I2 => HRDATA(17),
O => n_ahbso_hrdata(17));
II_hrdata_0HAKL16HAKR: LUT3
generic map(
INIT => X"D8"
)
port map (
I0 => D16MUX(0),
I1 => DATA16(0),
I2 => HRDATA(16),
O => n_ahbso_hrdata(16));
II_hrdata_0HAKL15HAKR: LUT3
generic map(
INIT => X"E4"
)
port map (
I0 => D16MUX(1),
I1 => HRDATA(15),
I2 => HRDATA(31),
O => n_ahbso_hrdata(15));
II_hrdata_0HAKL14HAKR: LUT3
generic map(
INIT => X"E4"
)
port map (
I0 => D16MUX(1),
I1 => HRDATA(14),
I2 => HRDATA(30),
O => n_ahbso_hrdata(14));
II_hrdata_0HAKL13HAKR: LUT3
generic map(
INIT => X"E4"
)
port map (
I0 => D16MUX(1),
I1 => HRDATA(13),
I2 => HRDATA(29),
O => n_ahbso_hrdata(13));
II_hrdata_0HAKL12HAKR: LUT3
generic map(
INIT => X"E4"
)
port map (
I0 => D16MUX(1),
I1 => HRDATA(12),
I2 => HRDATA(28),
O => n_ahbso_hrdata(12));
II_hrdata_0HAKL11HAKR: LUT3
generic map(
INIT => X"E4"
)
port map (
I0 => D16MUX(1),
I1 => HRDATA(11),
I2 => HRDATA(27),
O => n_ahbso_hrdata(11));
II_hrdata_0HAKL10HAKR: LUT3
generic map(
INIT => X"E4"
)
port map (
I0 => D16MUX(1),
I1 => HRDATA(10),
I2 => HRDATA(26),
O => n_ahbso_hrdata(10));
II_hrdata_0HAKL9HAKR: LUT3
generic map(
INIT => X"E4"
)
port map (
I0 => D16MUX(1),
I1 => HRDATA(9),
I2 => HRDATA(25),
O => n_ahbso_hrdata(9));
II_hrdata_0HAKL8HAKR: LUT3
generic map(
INIT => X"E4"
)
port map (
I0 => D16MUX(1),
I1 => HRDATA(8),
I2 => HRDATA(24),
O => n_ahbso_hrdata(8));
II_hrdata_0HAKL7HAKR: LUT3
generic map(
INIT => X"E4"
)
port map (
I0 => D16MUX(1),
I1 => HRDATA(7),
I2 => HRDATA(23),
O => n_ahbso_hrdata(7));
II_hrdata_0HAKL6HAKR: LUT3
generic map(
INIT => X"E4"
)
port map (
I0 => D16MUX(1),
I1 => HRDATA(6),
I2 => HRDATA(22),
O => n_ahbso_hrdata(6));
II_hrdata_0HAKL5HAKR: LUT3
generic map(
INIT => X"E4"
)
port map (
I0 => D16MUX(1),
I1 => HRDATA(5),
I2 => HRDATA(21),
O => n_ahbso_hrdata(5));
II_hrdata_0HAKL4HAKR: LUT3
generic map(
INIT => X"E4"
)
port map (
I0 => D16MUX(1),
I1 => HRDATA(4),
I2 => HRDATA(20),
O => n_ahbso_hrdata(4));
II_hrdata_0HAKL3HAKR: LUT3
generic map(
INIT => X"E4"
)
port map (
I0 => D16MUX(1),
I1 => HRDATA(3),
I2 => HRDATA(19),
O => n_ahbso_hrdata(3));
II_hrdata_0HAKL2HAKR: LUT3
generic map(
INIT => X"E4"
)
port map (
I0 => D16MUX(1),
I1 => HRDATA(2),
I2 => HRDATA(18),
O => n_ahbso_hrdata(2));
II_hrdata_0HAKL1HAKR: LUT3
generic map(
INIT => X"E4"
)
port map (
I0 => D16MUX(1),
I1 => HRDATA(1),
I2 => HRDATA(17),
O => n_ahbso_hrdata(1));
II_hrdata_0HAKL0HAKR: LUT3
generic map(
INIT => X"E4"
)
port map (
I0 => D16MUX(1),
I1 => HRDATA(0),
I2 => HRDATA(16),
O => n_ahbso_hrdata(0));
II_ctrl_v_bdrive_1_iv_0_a0_0: LUT2
generic map(
INIT => X"4"
)
port map (
I0 => PRSTATE_1_INT_28,
I1 => SETBDRIVE,
O => BDRIVE_1_IV_0_A4_0);
II_ctrl_hwrite6: LUT2
generic map(
INIT => X"4"
)
port map (
I0 => CHANGE_INT_69,
I1 => PRHREADY_INT_48,
O => N_662_INT_60);
II_ctrl_regsd24: LUT2
generic map(
INIT => X"1"
)
port map (
I0 => n_apbi_paddr(2),
I1 => n_apbi_paddr(3),
O => N_APBO_PRDATA_28_INT_11);
II_ctrl_bus16en: LUT2
generic map(
INIT => X"2"
)
port map (
I0 => ROMWIDTH(0),
I1 => ROMWIDTH(1),
O => BUS16EN_INT_72);
II_ctrl_v_ssrstate23_1: LUT2
generic map(
INIT => X"1"
)
port map (
I0 => WS_1_INT_17,
I1 => WS_2_INT_18,
O => SSRSTATE23_1);
II_ctrl_un1_ahbsi: LUT2
generic map(
INIT => X"1"
)
port map (
I0 => n_ahbsi_htrans(0),
I1 => n_ahbsi_htrans(1),
O => UN1_AHBSI_INT_68);
II_un1_r_ssrstate_2: LUT2
generic map(
INIT => X"1"
)
port map (
I0 => SSRSTATE_0_INT_20,
I1 => SSRSTATE_3_INT_23,
O => SSRSTATE_2_I_INT_55);
II_ctrl_un17_bus16en: LUT2
generic map(
INIT => X"2"
)
port map (
I0 => SIZE_0_INT_25,
I1 => SIZE_1_INT_26,
O => UN17_BUS16EN);
II_un1_r_ssrstate_1: LUT2
generic map(
INIT => X"1"
)
port map (
I0 => SSRSTATE_2_INT_22,
I1 => SSRSTATE_4_INT_24,
O => N_668);
II_r_haddrHAKL1HAKR: FDSE port map (
Q => N_SRO_ADDRESS_1_INT_37,
D => n_ahbsi_haddr(1),
C => clk,
S => PRHREADY_0_SQMUXA,
CE => HMBSEL_0_SQMUXA);
II_r_prstateHAKL5HAKR: FDS port map (
Q => PRSTATE_5_INT_32,
D => PRSTATES_I,
C => clk,
S => RST_I);
II_r_prstateHAKL4HAKR: FDS port map (
Q => PRSTATE_4_INT_31,
D => N_342,
C => clk,
S => N_341);
II_r_prstateHAKL3HAKR: FDR port map (
Q => PRSTATE_3_INT_30,
D => PRSTATEC,
C => clk,
R => RST_I);
II_r_prstateHAKL2HAKR: FDR port map (
Q => PRSTATE_2_INT_29,
D => PRSTATEC_0,
C => clk,
R => RST_I);
II_r_prstateHAKL1HAKR: FDR port map (
Q => PRSTATE_1_INT_28,
D => N_337_I,
C => clk,
R => RST_I);
II_r_prstateHAKL0HAKR: FDR port map (
Q => PRSTATE_0_INT_27,
D => PRSTATEC_1,
C => clk,
R => RST_I);
II_r_ssrstateHAKL1HAKR: FDR port map (
Q => SSRSTATE_1_INT_21,
D => ssrstatec,
C => clk,
R => RST_I);
II_r_ssrstateHAKL0HAKR: FDR port map (
Q => SSRSTATE_0_INT_20,
D => SSRSTATEC_0,
C => clk,
R => RST_I);
II_rbdriveHAKL28HAKR: FDR port map (
Q => n_sro_vbdrive(28),
D => RBDRIVEC,
C => clk,
R => BDRIVE_1_IV_0_A1);
II_rbdriveHAKL29HAKR: FDR port map (
Q => n_sro_vbdrive(29),
D => RBDRIVEC,
C => clk,
R => BDRIVE_1_IV_0_A1);
II_rbdriveHAKL30HAKR: FDR port map (
Q => n_sro_vbdrive(30),
D => RBDRIVEC,
C => clk,
R => BDRIVE_1_IV_0_A1);
II_rbdriveHAKL31HAKR: FDR port map (
Q => n_sro_vbdrive(31),
D => RBDRIVEC,
C => clk,
R => BDRIVE_1_IV_0_A1);
II_rbdriveHAKL13HAKR: FDR port map (
Q => n_sro_vbdrive(13),
D => RBDRIVEC,
C => clk,
R => BDRIVE_1_IV_0_A1);
II_rbdriveHAKL14HAKR: FDR port map (
Q => n_sro_vbdrive(14),
D => RBDRIVEC,
C => clk,
R => BDRIVE_1_IV_0_A1);
II_rbdriveHAKL15HAKR: FDR port map (
Q => n_sro_vbdrive(15),
D => RBDRIVEC,
C => clk,
R => BDRIVE_1_IV_0_A1);
II_rbdriveHAKL16HAKR: FDR port map (
Q => n_sro_vbdrive(16),
D => RBDRIVEC,
C => clk,
R => BDRIVE_1_IV_0_A1);
II_rbdriveHAKL17HAKR: FDR port map (
Q => n_sro_vbdrive(17),
D => RBDRIVEC,
C => clk,
R => BDRIVE_1_IV_0_A1);
II_rbdriveHAKL18HAKR: FDR port map (
Q => n_sro_vbdrive(18),
D => RBDRIVEC,
C => clk,
R => BDRIVE_1_IV_0_A1);
II_rbdriveHAKL19HAKR: FDR port map (
Q => n_sro_vbdrive(19),
D => RBDRIVEC,
C => clk,
R => BDRIVE_1_IV_0_A1);
II_rbdriveHAKL20HAKR: FDR port map (
Q => n_sro_vbdrive(20),
D => RBDRIVEC,
C => clk,
R => BDRIVE_1_IV_0_A1);
II_rbdriveHAKL21HAKR: FDR port map (
Q => n_sro_vbdrive(21),
D => RBDRIVEC,
C => clk,
R => BDRIVE_1_IV_0_A1);
II_rbdriveHAKL22HAKR: FDR port map (
Q => n_sro_vbdrive(22),
D => RBDRIVEC,
C => clk,
R => BDRIVE_1_IV_0_A1);
II_rbdriveHAKL23HAKR: FDR port map (
Q => n_sro_vbdrive(23),
D => RBDRIVEC,
C => clk,
R => BDRIVE_1_IV_0_A1);
II_rbdriveHAKL24HAKR: FDR port map (
Q => n_sro_vbdrive(24),
D => RBDRIVEC,
C => clk,
R => BDRIVE_1_IV_0_A1);
II_rbdriveHAKL25HAKR: FDR port map (
Q => n_sro_vbdrive(25),
D => RBDRIVEC,
C => clk,
R => BDRIVE_1_IV_0_A1);
II_rbdriveHAKL26HAKR: FDR port map (
Q => n_sro_vbdrive(26),
D => RBDRIVEC,
C => clk,
R => BDRIVE_1_IV_0_A1);
II_rbdriveHAKL27HAKR: FDR port map (
Q => n_sro_vbdrive(27),
D => RBDRIVEC,
C => clk,
R => BDRIVE_1_IV_0_A1);
II_rbdriveHAKL0HAKR: FDR port map (
Q => n_sro_vbdrive(0),
D => RBDRIVEC_18,
C => clk,
R => BDRIVE_1_IV_0_A1);
II_rbdriveHAKL1HAKR: FDR port map (
Q => n_sro_vbdrive(1),
D => RBDRIVEC,
C => clk,
R => BDRIVE_1_IV_0_A1);
II_rbdriveHAKL2HAKR: FDR port map (
Q => n_sro_vbdrive(2),
D => RBDRIVEC,
C => clk,
R => BDRIVE_1_IV_0_A1);
II_rbdriveHAKL3HAKR: FDR port map (
Q => n_sro_vbdrive(3),
D => RBDRIVEC,
C => clk,
R => BDRIVE_1_IV_0_A1);
II_rbdriveHAKL4HAKR: FDR port map (
Q => n_sro_vbdrive(4),
D => RBDRIVEC,
C => clk,
R => BDRIVE_1_IV_0_A1);
II_rbdriveHAKL5HAKR: FDR port map (
Q => n_sro_vbdrive(5),
D => RBDRIVEC,
C => clk,
R => BDRIVE_1_IV_0_A1);
II_rbdriveHAKL6HAKR: FDR port map (
Q => n_sro_vbdrive(6),
D => RBDRIVEC,
C => clk,
R => BDRIVE_1_IV_0_A1);
II_rbdriveHAKL7HAKR: FDR port map (
Q => n_sro_vbdrive(7),
D => RBDRIVEC,
C => clk,
R => BDRIVE_1_IV_0_A1);
II_rbdriveHAKL8HAKR: FDR port map (
Q => n_sro_vbdrive(8),
D => RBDRIVEC,
C => clk,
R => BDRIVE_1_IV_0_A1);
II_rbdriveHAKL9HAKR: FDR port map (
Q => n_sro_vbdrive(9),
D => RBDRIVEC,
C => clk,
R => BDRIVE_1_IV_0_A1);
II_rbdriveHAKL10HAKR: FDR port map (
Q => n_sro_vbdrive(10),
D => RBDRIVEC,
C => clk,
R => BDRIVE_1_IV_0_A1);
II_rbdriveHAKL11HAKR: FDR port map (
Q => n_sro_vbdrive(11),
D => RBDRIVEC,
C => clk,
R => BDRIVE_1_IV_0_A1);
II_rbdriveHAKL12HAKR: FDR port map (
Q => n_sro_vbdrive(12),
D => RBDRIVEC,
C => clk,
R => BDRIVE_1_IV_0_A1);
II_r_d16muxHAKL0HAKR: FDR port map (
Q => D16MUX(0),
D => D16MUXC,
C => clk,
R => WS_2_INT_18);
II_r_d16muxHAKL1HAKR: FDR port map (
Q => D16MUX(1),
D => D16MUXC_0,
C => clk,
R => PRSTATE_2_INT_29);
II_r_acount_sHAKL9HAKR: XORCY port map (
LI => ACOUNT_QXU(9),
CI => ACOUNT_CRY(8),
O => ACOUNT_S(9));
II_r_acount_sHAKL8HAKR: XORCY port map (
LI => ACOUNT_QXU(8),
CI => ACOUNT_CRY(7),
O => ACOUNT_S(8));
II_r_acount_cryHAKL8HAKR: MUXCY_L port map (
DI => NN_10,
CI => ACOUNT_CRY(7),
S => ACOUNT_QXU(8),
LO => ACOUNT_CRY(8));
II_r_acount_sHAKL7HAKR: XORCY port map (
LI => ACOUNT_QXU(7),
CI => ACOUNT_CRY(6),
O => ACOUNT_S(7));
II_r_acount_cryHAKL7HAKR: MUXCY_L port map (
DI => NN_10,
CI => ACOUNT_CRY(6),
S => ACOUNT_QXU(7),
LO => ACOUNT_CRY(7));
II_r_acount_sHAKL6HAKR: XORCY port map (
LI => ACOUNT_QXU(6),
CI => ACOUNT_CRY(5),
O => ACOUNT_S(6));
II_r_acount_cryHAKL6HAKR: MUXCY_L port map (
DI => NN_10,
CI => ACOUNT_CRY(5),
S => ACOUNT_QXU(6),
LO => ACOUNT_CRY(6));
II_r_acount_sHAKL5HAKR: XORCY port map (
LI => ACOUNT_QXU(5),
CI => ACOUNT_CRY(4),
O => ACOUNT_S(5));
II_r_acount_cryHAKL5HAKR: MUXCY_L port map (
DI => NN_10,
CI => ACOUNT_CRY(4),
S => ACOUNT_QXU(5),
LO => ACOUNT_CRY(5));
II_r_acount_sHAKL4HAKR: XORCY port map (
LI => ACOUNT_QXU(4),
CI => ACOUNT_CRY(3),
O => ACOUNT_S(4));
II_r_acount_cryHAKL4HAKR: MUXCY_L port map (
DI => NN_10,
CI => ACOUNT_CRY(3),
S => ACOUNT_QXU(4),
LO => ACOUNT_CRY(4));
II_r_acount_sHAKL3HAKR: XORCY port map (
LI => ACOUNT_QXU(3),
CI => ACOUNT_CRY(2),
O => ACOUNT_S(3));
II_r_acount_cryHAKL3HAKR: MUXCY_L port map (
DI => NN_10,
CI => ACOUNT_CRY(2),
S => ACOUNT_QXU(3),
LO => ACOUNT_CRY(3));
II_r_acount_sHAKL2HAKR: XORCY port map (
LI => ACOUNT_QXU(2),
CI => ACOUNT_CRY(1),
O => ACOUNT_S(2));
II_r_acount_cryHAKL2HAKR: MUXCY_L port map (
DI => NN_10,
CI => ACOUNT_CRY(1),
S => ACOUNT_QXU(2),
LO => ACOUNT_CRY(2));
II_r_acount_sHAKL1HAKR: XORCY port map (
LI => ACOUNT_QXU(1),
CI => N_SRO_ADDRESS_2_INT_38,
O => ACOUNT_S(1));
II_r_acount_cryHAKL1HAKR: MUXCY_L port map (
DI => NN_10,
CI => N_SRO_ADDRESS_2_INT_38,
S => ACOUNT_QXU(1),
LO => ACOUNT_CRY(1));
II_r_hsel: FDRE port map (
Q => HSEL_INT_58,
D => hsel_4,
C => clk,
R => RST_I,
CE => n_ahbsi_hready);
II_r_mcfg1_ioen: FDRE port map (
Q => IOEN,
D => IOEN_1,
C => clk,
R => RST_I,
CE => BEXCEN_1_SQMUXA_I);
II_r_mcfg1_romwrite: FDRE port map (
Q => ROMWRITE,
D => ROMWRITE_1,
C => clk,
R => RST_I,
CE => BEXCEN_1_SQMUXA_I);
II_r_mcfg1_iowsHAKL3HAKR: FDRE port map (
Q => IOWS_3_INT_6,
D => IOWS_1(3),
C => clk,
R => RST_I,
CE => BEXCEN_1_SQMUXA_I);
II_r_mcfg1_iowsHAKL2HAKR: FDRE port map (
Q => IOWS(2),
D => IOWS_1(2),
C => clk,
R => RST_I,
CE => BEXCEN_1_SQMUXA_I);
II_r_mcfg1_iowsHAKL1HAKR: FDRE port map (
Q => IOWS(1),
D => IOWS_1(1),
C => clk,
R => RST_I,
CE => BEXCEN_1_SQMUXA_I);
II_r_mcfg1_iowsHAKL0HAKR: FDRE port map (
Q => IOWS_0_INT_5,
D => IOWS_1(0),
C => clk,
R => RST_I,
CE => BEXCEN_1_SQMUXA_I);
II_r_mcfg1_romrwsHAKL3HAKR: FDSE port map (
Q => ROMRWS_3_INT_10,
D => N_627_I,
C => clk,
S => RST_I,
CE => BEXCEN_1_SQMUXA_I);
II_r_mcfg1_romrwsHAKL2HAKR: FDSE port map (
Q => ROMRWS(2),
D => N_628_I,
C => clk,
S => RST_I,
CE => BEXCEN_1_SQMUXA_I);
II_r_mcfg1_romrwsHAKL1HAKR: FDSE port map (
Q => ROMRWS(1),
D => N_629_I,
C => clk,
S => RST_I,
CE => BEXCEN_1_SQMUXA_I);
II_r_mcfg1_romrwsHAKL0HAKR: FDSE port map (
Q => ROMRWS_0_INT_9,
D => N_630_I,
C => clk,
S => RST_I,
CE => BEXCEN_1_SQMUXA_I);
II_r_mcfg1_romwwsHAKL3HAKR: FDSE port map (
Q => ROMWWS_3_INT_8,
D => N_623_I,
C => clk,
S => RST_I,
CE => BEXCEN_1_SQMUXA_I);
II_r_mcfg1_romwwsHAKL2HAKR: FDSE port map (
Q => ROMWWS(2),
D => N_624_I,
C => clk,
S => RST_I,
CE => BEXCEN_1_SQMUXA_I);
II_r_mcfg1_romwwsHAKL1HAKR: FDSE port map (
Q => ROMWWS(1),
D => N_625_I,
C => clk,
S => RST_I,
CE => BEXCEN_1_SQMUXA_I);
II_r_mcfg1_romwwsHAKL0HAKR: FDSE port map (
Q => ROMWWS_0_INT_7,
D => N_626_I,
C => clk,
S => RST_I,
CE => BEXCEN_1_SQMUXA_I);
II_r_writen: FDSE port map (
Q => n_sro_writen,
D => N_635_I,
C => clk,
S => RST_I,
CE => WRITEN_2_SQMUXA);
II_r_loadcount: FDS port map (
Q => loadcount,
D => loadcount_7,
C => clk,
S => RST_I);
II_r_setbdrive: FDRE port map (
Q => SETBDRIVE,
D => SSRSTATE_1_INT_21,
C => clk,
R => RST_I,
CE => SSRSTATE_3);
II_r_ssrhready: FDS port map (
Q => SSRHREADY_INT_51,
D => ssrhready_8,
C => clk,
S => RST_I);
II_r_prhready: FDS port map (
Q => PRHREADY_INT_48,
D => PRHREADY_6,
C => clk,
S => RST_I);
II_r_romsn: FDSE port map (
Q => N_SRO_ROMSN_0_INT_12,
D => ROMSN_1,
C => clk,
S => RST_I,
CE => N_599_I);
II_r_hready: FDS port map (
Q => n_ahbso_hready,
D => hready_2,
C => clk,
S => RST_I);
II_GND: GND port map (
G => NN_10);
II_VCC: VCC port map (
P => NN_11);
iows_0 <= IOWS_0_INT_5;
iows_3 <= IOWS_3_INT_6;
romwws_0 <= ROMWWS_0_INT_7;
romwws_3 <= ROMWWS_3_INT_8;
romrws_0 <= ROMRWS_0_INT_9;
romrws_3 <= ROMRWS_3_INT_10;
n_apbo_prdata_28 <= N_APBO_PRDATA_28_INT_11;
n_sro_romsn(0) <= N_SRO_ROMSN_0_INT_12;
prstate_fast(2) <= PRSTATE_FAST_2_INT_13;
hmbsel_4(1) <= HMBSEL_4_1_INT_14;
n_sro_bdrive(3) <= N_SRO_BDRIVE_3_INT_15;
ws(0) <= WS_0_INT_16;
ws(1) <= WS_1_INT_17;
ws(2) <= WS_2_INT_18;
ws(3) <= WS_3_INT_19;
ssrstate(0) <= SSRSTATE_0_INT_20;
ssrstate(1) <= SSRSTATE_1_INT_21;
ssrstate(2) <= SSRSTATE_2_INT_22;
ssrstate(3) <= SSRSTATE_3_INT_23;
ssrstate(4) <= SSRSTATE_4_INT_24;
size(0) <= SIZE_0_INT_25;
size(1) <= SIZE_1_INT_26;
prstate(0) <= PRSTATE_0_INT_27;
prstate(1) <= PRSTATE_1_INT_28;
prstate(2) <= PRSTATE_2_INT_29;
prstate(3) <= PRSTATE_3_INT_30;
prstate(4) <= PRSTATE_4_INT_31;
prstate(5) <= PRSTATE_5_INT_32;
hmbsel(0) <= HMBSEL_0_INT_33;
hmbsel(1) <= HMBSEL_1_INT_34;
hmbsel(2) <= HMBSEL_2_INT_35;
n_sro_address(0) <= N_SRO_ADDRESS_0_INT_36;
n_sro_address(1) <= N_SRO_ADDRESS_1_INT_37;
n_sro_address(2) <= N_SRO_ADDRESS_2_INT_38;
n_sro_address(3) <= N_SRO_ADDRESS_3_INT_39;
n_sro_address(4) <= N_SRO_ADDRESS_4_INT_40;
n_sro_address(5) <= N_SRO_ADDRESS_5_INT_41;
n_sro_address(6) <= N_SRO_ADDRESS_6_INT_42;
n_sro_address(7) <= N_SRO_ADDRESS_7_INT_43;
n_sro_address(8) <= N_SRO_ADDRESS_8_INT_44;
n_sro_address(9) <= N_SRO_ADDRESS_9_INT_45;
n_sro_address(10) <= N_SRO_ADDRESS_10_INT_46;
n_sro_address(11) <= N_SRO_ADDRESS_11_INT_47;
prhready <= PRHREADY_INT_48;
ws_0_sqmuxa_c <= WS_0_SQMUXA_C_INT_49;
ws_0_sqmuxa_0_c <= WS_0_SQMUXA_0_C_INT_50;
ssrhready <= SSRHREADY_INT_51;
ws_1_sqmuxa <= WS_1_SQMUXA_INT_52;
ws_3_sqmuxa_1 <= WS_3_SQMUXA_1_INT_53;
ws_2_sqmuxa_3_0_2 <= WS_2_SQMUXA_3_0_2_INT_54;
ssrstate_2_i <= SSRSTATE_2_I_INT_55;
ws_2_sqmuxa_3_d <= WS_2_SQMUXA_3_D_INT_56;
ws_0_sqmuxa_1 <= WS_0_SQMUXA_1_INT_57;
hsel <= HSEL_INT_58;
prstate_2_rep1 <= PRSTATE_2_REP1_INT_59;
N_662 <= N_662_INT_60;
ssrstate_6_sqmuxa <= SSRSTATE_6_SQMUXA_INT_61;
ssrhready_2_sqmuxa_0_0 <= SSRHREADY_2_SQMUXA_0_0_INT_62;
change_1_sqmuxa_N_3 <= CHANGE_1_SQMUXA_N_3_INT_63;
ssrstate6_xx_mm_m3 <= SSRSTATE6_XX_MM_M3_INT_64;
ssrstate6_1_d_0_L1 <= SSRSTATE6_1_D_0_L1_INT_65;
N_656 <= N_656_INT_66;
hsel_5 <= HSEL_5_INT_67;
un1_ahbsi <= UN1_AHBSI_INT_68;
change <= CHANGE_INT_69;
n_sro_iosn <= N_SRO_IOSN_INT_70;
N_371 <= N_371_INT_71;
bus16en <= BUS16EN_INT_72;
d16muxc_0_4 <= D16MUXC_0_4_INT_73;
end beh;
--
library ieee;
use ieee.std_logic_1164.all;
library unisim;
use unisim.vcomponents.all;
architecture beh of ssrctrl_unisim is
signal WRP_R_HMBSEL : std_logic_vector (2 downto 0);
signal WRP_R_WS : std_logic_vector (3 downto 0);
signal WRP_R_SIZE : std_logic_vector (1 downto 0);
signal WRP_R_PRSTATE : std_logic_vector (5 downto 0);
signal WRP_R_SSRSTATE : std_logic_vector (4 downto 0);
signal WRP_R_MCFG1_ROMRWS : std_logic_vector (3 downto 0);
signal WRP_R_MCFG1_ROMWWS : std_logic_vector (3 downto 0);
signal WRP_R_MCFG1_IOWS : std_logic_vector (3 downto 0);
signal WRP_CTRL_V_SSRSTATE_1 : std_logic_vector (4 to 4);
signal WRP_CTRL_V_SSRSTATE_1_M1 : std_logic_vector (4 downto 3);
signal WRP_CTRL_V_WS_1 : std_logic_vector (3 downto 0);
signal WRP_CTRL_V_HMBSEL_4 : std_logic_vector (1 to 1);
signal WRP_NONAME_CNST : std_logic_vector (0 to 0);
signal WRP_CTRL_HSIZE_1 : std_logic_vector (1 to 1);
signal WRP_HADDR : std_logic_vector (1 to 1);
signal WRP_UN1_V_HSEL_1 : std_logic_vector (0 to 0);
signal WRP_CTRL_V_BWN_1_0_O3 : std_logic_vector (0 to 0);
signal WRP_V_PRSTATE_1_I_O4_S : std_logic_vector (2 to 2);
signal WRP_R_PRSTATE_FAST : std_logic_vector (2 to 2);
signal N_SRO_ADDRESS_0_INT_172 : std_logic ;
signal N_SRO_ADDRESS_1_INT_173 : std_logic ;
signal N_SRO_IOSN_INT_259 : std_logic ;
signal N_SRO_ROMSN_0_INT_260 : std_logic ;
signal WRP_R_PRHREADY : std_logic ;
signal WRP_R_CHANGE : std_logic ;
signal WRP_CTRL_V_HSEL_5 : std_logic ;
signal WRP_R_HSEL : std_logic ;
signal WRP_CTRL_V_LOADCOUNT_7 : std_logic ;
signal WRP_R_LOADCOUNT : std_logic ;
signal WRP_CTRL_V_SSRHREADY_8 : std_logic ;
signal WRP_R_SSRHREADY : std_logic ;
signal WRP_CTRL_V_HREADY_2 : std_logic ;
signal N_574_I : std_logic ;
signal WRP_CTRL_BUS16EN : std_logic ;
signal WRP_CTRL_V_HSEL_4 : std_logic ;
signal WRP_CTRL_UN7_BUS16EN : std_logic ;
signal WRP_V_D16MUX_0_SQMUXA : std_logic ;
signal N_593 : std_logic ;
signal N_597 : std_logic ;
signal N_596 : std_logic ;
signal WRP_V_SSRSTATE_2_SQMUXA_1 : std_logic ;
signal WRP_V_SSRSTATE_6_SQMUXA : std_logic ;
signal WRP_V_SSRSTATE_1_SQMUXA_1 : std_logic ;
signal WRP_UN1_R_SSRSTATE_2_I : std_logic ;
signal WRP_V_WS_0_SQMUXA_1 : std_logic ;
signal WRP_V_BWN_0_SQMUXA_1 : std_logic ;
signal WRP_V_WS_1_SQMUXA : std_logic ;
signal N_646 : std_logic ;
signal WRP_V_WS_3_SQMUXA_1 : std_logic ;
signal N_662 : std_logic ;
signal WRP_V_LOADCOUNT_1_SQMUXA : std_logic ;
signal N_319_1 : std_logic ;
signal WRP_CTRL_UN1_AHBSI : std_logic ;
signal N_622 : std_logic ;
signal WRP_UN1_V_SSRSTATE_2_SQMUXA_I : std_logic ;
signal N_365 : std_logic ;
signal N_371 : std_logic ;
signal N_656 : std_logic ;
signal WRP_UN1_V_CHANGE_1_SQMUXA_0 : std_logic ;
signal G0_25 : std_logic ;
signal WRP_CTRL_V_CHANGE_3_F0 : std_logic ;
signal WRP_UN1_V_BWN_1_SQMUXA_2_D : std_logic ;
signal WRP_CTRL_UN1_V_SSRSTATE17_1_XX_MM_N_4 : std_logic ;
signal SSRSTATE17_2_0_M6_I_A3_A2 : std_logic ;
signal SSRSTATE6_XX_MM_M3 : std_logic ;
signal WRP_V_CHANGE_1_SQMUXA_N_3 : std_logic ;
signal WRP_CTRL_V_CHANGE_3_F1_D_0_0 : std_logic ;
signal WRP_V_WS_2_SQMUXA_3_D : std_logic ;
signal WRP_V_WS_0_SQMUXA_C : std_logic ;
signal WRP_V_WS_0_SQMUXA_0_C : std_logic ;
signal G0_30 : std_logic ;
signal D_M2_0_A2_0 : std_logic ;
signal N_618_I : std_logic ;
signal WRP_R_SSRSTATEC : std_logic ;
signal WRP_R_D16MUXC_0_4 : std_logic ;
signal WRP_V_WS_4_SQMUXA_0 : std_logic ;
signal D_M1_E_0_0 : std_logic ;
signal WRP_V_WS_2_SQMUXA_0 : std_logic ;
signal WRP_V_SSRSTATE_1_SQMUXA_1_XX_MM_A1_0 : std_logic ;
signal WRP_UN1_V_SSRSTATE17_2_0_M6_I_1 : std_logic ;
signal WRP_V_SSRHREADY_2_SQMUXA_0_0 : std_logic ;
signal WRP_V_WS_2_SQMUXA_3_0_2 : std_logic ;
signal WRP_V_WS_2_SQMUXA_3_0_4 : std_logic ;
signal WRP_UN1_V_BWN_1_SQMUXA_2_D_0_2 : std_logic ;
signal WRP_UN1_V_SSRSTATE_1_SQMUXA_1_0_M3_0_1 : std_logic ;
signal SSRSTATE6_1_D_0_L1 : std_logic ;
signal HSEL_1_0_L3 : std_logic ;
signal SSRHREADY_8_F0_L5 : std_logic ;
signal SSRHREADY_8_F0_L8 : std_logic ;
signal G0_I : std_logic ;
signal N_5 : std_logic ;
signal G0_23 : std_logic ;
signal N_14 : std_logic ;
signal N_19 : std_logic ;
signal G0_34 : std_logic ;
signal G0_29 : std_logic ;
signal G0_28 : std_logic ;
signal G0_31 : std_logic ;
signal G2_1_0 : std_logic ;
signal G0_44 : std_logic ;
signal G0_I_M2_1 : std_logic ;
signal G0_14 : std_logic ;
signal G0_7_0 : std_logic ;
signal G0_1_0 : std_logic ;
signal G3 : std_logic ;
signal N_4 : std_logic ;
signal N_17 : std_logic ;
signal G0_5_0 : std_logic ;
signal G0_11 : std_logic ;
signal G0_I_A3_0 : std_logic ;
signal G0_51 : std_logic ;
signal G0_8_1 : std_logic ;
signal G0_56 : std_logic ;
signal G0_I_M2_2 : std_logic ;
signal N_9 : std_logic ;
signal G0_8 : std_logic ;
signal G0_I_M2_L1 : std_logic ;
signal G0_54_L1 : std_logic ;
signal G0_57_1 : std_logic ;
signal G0_34_L1_0 : std_logic ;
signal G0_34_L6 : std_logic ;
signal G0_34_L10 : std_logic ;
signal G0_55_L1 : std_logic ;
signal G0_55_L5 : std_logic ;
signal G0_55_L7 : std_logic ;
signal G0_19_L1 : std_logic ;
signal G0_52_X0 : std_logic ;
signal G0_52_X1 : std_logic ;
signal G0_50_X : std_logic ;
signal WS_2_SQMUXA_3_0_X : std_logic ;
signal D_M1_E_L1 : std_logic ;
signal G0_57_1_L5 : std_logic ;
signal G0_57_1_L7 : std_logic ;
signal G0_55_L5_L1 : std_logic ;
signal G0_55_L7_L1 : std_logic ;
signal G0_36_L1 : std_logic ;
signal G0_48_L1 : std_logic ;
signal G0_34_L10_L1 : std_logic ;
signal G0_34_L10_L3 : std_logic ;
signal G0_57_1_L7_L4 : std_logic ;
signal G0_57_1_L7_L6 : std_logic ;
signal G0_57_1_L7_L8 : std_logic ;
signal WRP_R_PRSTATE_2_REP1 : std_logic ;
signal D_M1_E_L1_0 : std_logic ;
signal D_M1_E_L3 : std_logic ;
signal G0_I_M2_0_L1 : std_logic ;
signal G0_I_M2_0_L3 : std_logic ;
signal G0_I_M2_0_L5 : std_logic ;
signal G3_1 : std_logic ;
signal G0_0_L1 : std_logic ;
signal G0_0_L3 : std_logic ;
signal G0_0_L5 : std_logic ;
signal G0_0_L7 : std_logic ;
signal G0_0_L9 : std_logic ;
signal G0_57_1_L7_L6_RN_0 : std_logic ;
signal G0_57_1_L7_L6_SN : std_logic ;
signal G0_55_L7_L1_RN_0 : std_logic ;
signal G0_55_L7_L1_SN : std_logic ;
signal G0_52X : std_logic ;
signal G0_52X_0 : std_logic ;
signal G2_0_1 : std_logic ;
signal G0_46_L1 : std_logic ;
signal G0_46_L3 : std_logic ;
signal G0_46_L5 : std_logic ;
signal G0_46_L7 : std_logic ;
signal NN_1 : std_logic ;
signal N_SRO_OEN_INT_245_INT_246_INT_247_INT_248_INT_249_INT_250_INT_251_INT_252_INT_268 : std_logic ;
signal N_SRO_BDRIVE_3_INT_269_INT_270_INT_271_INT_272 : std_logic ;
signal NN_2 : std_logic ;
component ssrctrl_unisim_netlist
port(
n_sro_vbdrive : out std_logic_vector(31 downto 0);
n_ahbso_hrdata : out std_logic_vector(31 downto 0);
iows_0 : out std_logic;
iows_3 : out std_logic;
romwws_0 : out std_logic;
romwws_3 : out std_logic;
romrws_0 : out std_logic;
romrws_3 : out std_logic;
NoName_cnst : in std_logic_vector(0 downto 0);
n_sri_bwidth : in std_logic_vector(1 downto 0);
n_apbi_pwdata_19 : in std_logic;
n_apbi_pwdata_11 : in std_logic;
n_apbi_pwdata_9 : in std_logic;
n_apbi_pwdata_8 : in std_logic;
n_apbi_pwdata_23 : in std_logic;
n_apbi_pwdata_22 : in std_logic;
n_apbi_pwdata_21 : in std_logic;
n_apbi_pwdata_20 : in std_logic;
n_apbi_pwdata_3 : in std_logic;
n_apbi_pwdata_2 : in std_logic;
n_apbi_pwdata_1 : in std_logic;
n_apbi_pwdata_0 : in std_logic;
n_apbi_pwdata_7 : in std_logic;
n_apbi_pwdata_6 : in std_logic;
n_apbi_pwdata_5 : in std_logic;
n_apbi_pwdata_4 : in std_logic;
n_apbi_psel : in std_logic_vector(0 downto 0);
n_apbi_paddr : in std_logic_vector(5 downto 2);
n_apbo_prdata_0 : out std_logic;
n_apbo_prdata_4 : out std_logic;
n_apbo_prdata_20 : out std_logic;
n_apbo_prdata_23 : out std_logic;
n_apbo_prdata_22 : out std_logic;
n_apbo_prdata_21 : out std_logic;
n_apbo_prdata_19 : out std_logic;
n_apbo_prdata_7 : out std_logic;
n_apbo_prdata_6 : out std_logic;
n_apbo_prdata_5 : out std_logic;
n_apbo_prdata_3 : out std_logic;
n_apbo_prdata_2 : out std_logic;
n_apbo_prdata_1 : out std_logic;
n_apbo_prdata_11 : out std_logic;
n_apbo_prdata_9 : out std_logic;
n_apbo_prdata_8 : out std_logic;
n_apbo_prdata_28 : out std_logic;
n_sro_romsn : out std_logic_vector(0 downto 0);
n_ahbsi_hsel : in std_logic_vector(0 downto 0);
prstate_fast : out std_logic_vector(2 downto 2);
n_ahbsi_htrans : in std_logic_vector(1 downto 0);
ssrstate_1_m1 : inout std_logic_vector(4 downto 3);
hsel_1 : in std_logic_vector(0 downto 0);
hmbsel_4 : out std_logic_vector(1 downto 1);
n_sro_bdrive : out std_logic_vector(3 downto 3);
ws_1_0 : in std_logic;
ws_1_3 : in std_logic;
ws : out std_logic_vector(3 downto 0);
ssrstate_1_2 : in std_logic;
n_ahbsi_haddr : in std_logic_vector(31 downto 0);
n_ahbsi_hmbsel : in std_logic_vector(2 downto 0);
n_sri_data : in std_logic_vector(31 downto 0);
ssrstate : out std_logic_vector(4 downto 0);
n_ahbsi_hwdata : in std_logic_vector(31 downto 0);
n_ahbsi_hsize : in std_logic_vector(1 downto 0);
size : out std_logic_vector(1 downto 0);
n_sro_data : out std_logic_vector(31 downto 0);
n_sro_ramsn : out std_logic_vector(0 downto 0);
n_sro_wrn : out std_logic_vector(3 downto 0);
haddr_0 : in std_logic;
bwn_1_0_o3_0 : in std_logic;
hsize_1 : in std_logic_vector(1 downto 1);
prstate_1_i_o4_s : in std_logic_vector(2 downto 2);
prstate : out std_logic_vector(5 downto 0);
hmbsel : out std_logic_vector(2 downto 0);
n_sro_address : out std_logic_vector(31 downto 0);
hready_2 : in std_logic;
n_ahbso_hready : out std_logic;
ssrhready_8 : in std_logic;
loadcount : out std_logic;
n_sro_writen : out std_logic;
ssrstatec : in std_logic;
prhready : out std_logic;
d_m2_0_a2_0 : in std_logic;
ssrstate17_2_0_m6_i_a3_a2 : out std_logic;
N_319_1 : out std_logic;
ws_0_sqmuxa_c : out std_logic;
N_365 : in std_logic;
ws_0_sqmuxa_0_c : out std_logic;
ws_2_sqmuxa_3_0_4 : out std_logic;
change_1_sqmuxa_0 : in std_logic;
d16mux_0_sqmuxa : in std_logic;
ssrstate_2_sqmuxa_1 : in std_logic;
un7_bus16en : in std_logic;
N_646 : in std_logic;
loadcount_1_sqmuxa : in std_logic;
ssrstate_1_sqmuxa_1_0_m3_0_1 : out std_logic;
n_apbi_penable : in std_logic;
n_apbi_pwrite : in std_logic;
d_m1_e_0_0 : in std_logic;
hsel_1_0_L3 : out std_logic;
ssrhready_8_f0_L8 : out std_logic;
ssrstate_1_sqmuxa_1 : in std_logic;
ssrhready : out std_logic;
ssrhready_8_f0_L5 : out std_logic;
ssrstate17_1_xx_mm_N_4 : in std_logic;
ws_1_sqmuxa : out std_logic;
ws_4_sqmuxa_0 : in std_logic;
ws_2_sqmuxa_0 : in std_logic;
ssrstate17_2_0_m6_i_1 : out std_logic;
ws_2_sqmuxa_3_0_x : out std_logic;
ws_3_sqmuxa_1 : out std_logic;
ws_2_sqmuxa_3_0_2 : out std_logic;
ssrstate_2_i : out std_logic;
ws_2_sqmuxa_3_d : out std_logic;
ws_0_sqmuxa_1 : out std_logic;
g0_30 : in std_logic;
hsel_4 : in std_logic;
n_ahbsi_hready : in std_logic;
hsel : out std_logic;
g0_25 : in std_logic;
bwn_0_sqmuxa_1 : in std_logic;
prstate_2_rep1 : out std_logic;
N_662 : out std_logic;
ssrstate_6_sqmuxa : out std_logic;
g0_52_x1 : in std_logic;
g0_52_x0 : in std_logic;
ssrhready_2_sqmuxa_0_0 : out std_logic;
change_1_sqmuxa_N_3 : out std_logic;
ssrstate6_xx_mm_m3 : out std_logic;
ssrstate6_1_d_0_L1 : out std_logic;
N_656 : out std_logic;
hsel_5 : out std_logic;
change_3_f0 : in std_logic;
un1_ahbsi : out std_logic;
change : out std_logic;
n_ahbsi_hwrite : in std_logic;
N_574_i : in std_logic;
n_sro_iosn : out std_logic;
N_618_i : in std_logic;
clk : in std_logic;
n_sro_oen : out std_logic;
rst : in std_logic;
bwn_1_sqmuxa_2_d : in std_logic;
bwn_1_sqmuxa_2_d_0_2 : in std_logic;
ssrstate_2_sqmuxa_i : in std_logic;
g0_23 : in std_logic;
N_371 : out std_logic;
loadcount_7 : in std_logic;
bus16en : out std_logic;
d16muxc_0_4 : out std_logic;
change_3_f1_d_0_0 : in std_logic;
g0_1_0 : in std_logic;
g0_44 : in std_logic );
end component;
begin
II_g0_46: LUT4_L
generic map(
INIT => X"B000"
)
port map (
I0 => N_4,
I1 => N_17,
I2 => G0_46_L7,
I3 => G3,
LO => WRP_CTRL_V_HREADY_2);
II_g0_45: LUT4_L
generic map(
INIT => X"0B00"
)
port map (
I0 => N_4,
I1 => N_17,
I2 => SSRHREADY_8_F0_L8,
I3 => G3,
LO => WRP_CTRL_V_SSRHREADY_8);
II_g0_35: LUT4_L
generic map(
INIT => X"00B1"
)
port map (
I0 => N_622,
I1 => G0_34,
I2 => G0_29,
I3 => WRP_V_SSRSTATE_2_SQMUXA_1,
LO => WRP_R_SSRSTATEC);
II_g0_57: LUT4_L
generic map(
INIT => X"FA44"
)
port map (
I0 => N_371,
I1 => G0_56,
I2 => G0_I_M2_2,
I3 => G0_57_1,
LO => WRP_CTRL_V_WS_1(0));
II_g0_i_m2_0: LUT4_L
generic map(
INIT => X"B1E4"
)
port map (
I0 => N_5,
I1 => G0_I_M2_0_L3,
I2 => G0_I_M2_0_L5,
I3 => WRP_R_WS(3),
LO => WRP_CTRL_V_WS_1(3));
II_g0_i_m2: LUT4_L
generic map(
INIT => X"D8CC"
)
port map (
I0 => N_622,
I1 => G0_I_M2_L1,
I2 => WRP_CTRL_V_SSRSTATE_1_M1(4),
I3 => WRP_UN1_V_SSRSTATE_2_SQMUXA_I,
LO => WRP_CTRL_V_SSRSTATE_1(4));
II_g0_5: LUT4_L
generic map(
INIT => X"37FF"
)
port map (
I0 => WRP_CTRL_HSIZE_1(1),
I1 => WRP_CTRL_V_BWN_1_0_O3(0),
I2 => WRP_HADDR(1),
I3 => WRP_UN1_V_BWN_1_SQMUXA_2_D,
LO => N_618_I);
II_g0_46_L1: LUT3
generic map(
INIT => X"13"
)
port map (
I0 => WRP_R_D16MUXC_0_4,
I1 => WRP_R_SSRHREADY,
I2 => WRP_R_SSRSTATE(3),
O => G0_46_L1);
II_g0_46_L3: LUT3
generic map(
INIT => X"0B"
)
port map (
I0 => WRP_CTRL_UN1_AHBSI,
I1 => WRP_CTRL_V_HSEL_5,
I2 => WRP_R_CHANGE,
O => G0_46_L3);
II_g0_46_L5: LUT3
generic map(
INIT => X"5D"
)
port map (
I0 => G0_44,
I1 => G0_46_L1,
I2 => WRP_V_SSRSTATE_1_SQMUXA_1,
O => G0_46_L5);
II_g0_46_L7: LUT4_L
generic map(
INIT => X"1033"
)
port map (
I0 => G0_46_L3,
I1 => G0_46_L5,
I2 => WRP_CTRL_V_CHANGE_3_F1_D_0_0,
I3 => WRP_V_PRSTATE_1_I_O4_S(2),
LO => G0_46_L7);
II_g2_0: LUT4
generic map(
INIT => X"E0EA"
)
port map (
I0 => SSRHREADY_8_F0_L5,
I1 => G2_0_1,
I2 => WRP_CTRL_V_HMBSEL_4(1),
I3 => WRP_R_SSRSTATE(2),
O => N_4);
II_g2_0_1: LUT3
generic map(
INIT => X"20"
)
port map (
I0 => G0_48_L1,
I1 => WRP_CTRL_UN1_AHBSI,
I2 => WRP_CTRL_V_HSEL_5,
O => G2_0_1);
II_g0_52_x1x: LUT4
generic map(
INIT => X"35F5"
)
port map (
I0 => D_M1_E_0_0,
I1 => n_ahbsi_hmbsel(1),
I2 => n_ahbsi_hready,
I3 => n_ahbsi_hsel(0),
O => G0_52X_0);
II_g0_52_x0x: LUT2
generic map(
INIT => X"D"
)
port map (
I0 => D_M1_E_0_0,
I1 => n_ahbsi_hready,
O => G0_52X);
II_g0_55_L7_L1: LUT3
generic map(
INIT => X"E2"
)
port map (
I0 => G0_55_L7_L1_RN_0,
I1 => G0_55_L7_L1_SN,
I2 => n_ahbsi_htrans(1),
O => G0_55_L7_L1);
II_g0_55_L7_L1_sn: LUT4
generic map(
INIT => X"8D88"
)
port map (
I0 => n_ahbsi_hready,
I1 => n_ahbsi_hsel(0),
I2 => n_ahbsi_htrans(0),
I3 => WRP_R_HSEL,
O => G0_55_L7_L1_SN);
II_g0_55_L7_L1_rn: LUT2
generic map(
INIT => X"4"
)
port map (
I0 => n_ahbsi_hready,
I1 => WRP_R_HSEL,
O => G0_55_L7_L1_RN_0);
II_g0_57_1_L7_L6: LUT3
generic map(
INIT => X"E2"
)
port map (
I0 => G0_57_1_L7_L6_RN_0,
I1 => G0_57_1_L7_L6_SN,
I2 => n_ahbsi_htrans(1),
O => G0_57_1_L7_L6);
II_g0_57_1_L7_L6_sn: LUT4
generic map(
INIT => X"8D88"
)
port map (
I0 => n_ahbsi_hready,
I1 => n_ahbsi_hsel(0),
I2 => n_ahbsi_htrans(0),
I3 => WRP_R_HSEL,
O => G0_57_1_L7_L6_SN);
II_g0_57_1_L7_L6_rn: LUT2
generic map(
INIT => X"4"
)
port map (
I0 => n_ahbsi_hready,
I1 => WRP_R_HSEL,
O => G0_57_1_L7_L6_RN_0);
II_g0_0_L1: LUT2
generic map(
INIT => X"7"
)
port map (
I0 => rst,
I1 => WRP_R_PRSTATE_2_REP1,
O => G0_0_L1);
II_g0_0_L3: LUT2
generic map(
INIT => X"4"
)
port map (
I0 => WRP_V_CHANGE_1_SQMUXA_N_3,
I1 => WRP_V_SSRHREADY_2_SQMUXA_0_0,
O => G0_0_L3);
II_g0_0_L5: LUT4
generic map(
INIT => X"55DF"
)
port map (
I0 => G0_0_L1,
I1 => WRP_CTRL_UN1_AHBSI,
I2 => WRP_CTRL_V_HSEL_5,
I3 => WRP_R_D16MUXC_0_4,
O => G0_0_L5);
II_g0_0_L7: LUT2
generic map(
INIT => X"2"
)
port map (
I0 => n_ahbsi_htrans(0),
I1 => WRP_CTRL_UN1_V_SSRSTATE17_1_XX_MM_N_4,
O => G0_0_L7);
II_g0_0_L9: LUT4
generic map(
INIT => X"7F33"
)
port map (
I0 => G0_0_L3,
I1 => n_ahbsi_hwrite,
I2 => WRP_CTRL_V_HMBSEL_4(1),
I3 => SSRSTATE6_XX_MM_M3,
O => G0_0_L9);
II_g0_0: LUT4
generic map(
INIT => X"FFEF"
)
port map (
I0 => G0_0_L5,
I1 => G0_0_L7,
I2 => G0_0_L9,
I3 => WRP_V_LOADCOUNT_1_SQMUXA,
O => WRP_UN1_V_BWN_1_SQMUXA_2_D);
II_g3: LUT4
generic map(
INIT => X"DFCC"
)
port map (
I0 => G3_1,
I1 => n_ahbsi_hwrite,
I2 => WRP_CTRL_V_HMBSEL_4(1),
I3 => SSRSTATE6_XX_MM_M3,
O => G3);
II_g3_1: LUT2
generic map(
INIT => X"4"
)
port map (
I0 => WRP_V_CHANGE_1_SQMUXA_N_3,
I1 => WRP_V_SSRHREADY_2_SQMUXA_0_0,
O => G3_1);
II_g0_i_m2_0_L1: LUT3
generic map(
INIT => X"01"
)
port map (
I0 => WRP_R_WS(0),
I1 => WRP_R_WS(1),
I2 => WRP_R_WS(2),
O => G0_I_M2_0_L1);
II_g0_i_m2_0_L3: LUT4
generic map(
INIT => X"0A2A"
)
port map (
I0 => G0_I_M2_0_L1,
I1 => G0_30,
I2 => WRP_V_WS_0_SQMUXA_1,
I3 => WRP_V_WS_3_SQMUXA_1,
O => G0_I_M2_0_L3);
II_g0_i_m2_0_L5: LUT4
generic map(
INIT => X"1555"
)
port map (
I0 => D_M1_E_L1_0,
I1 => D_M1_E_L3,
I2 => WRP_V_WS_2_SQMUXA_3_0_2,
I3 => WRP_V_WS_2_SQMUXA_3_D,
O => G0_I_M2_0_L5);
II_d_m1_e_L1_0: LUT3
generic map(
INIT => X"4E"
)
port map (
I0 => N_365,
I1 => D_M1_E_L1,
I2 => WRP_R_MCFG1_ROMRWS(3),
O => D_M1_E_L1_0);
II_d_m1_e_L3: LUT4_L
generic map(
INIT => X"0F2F"
)
port map (
I0 => WRP_UN1_R_SSRSTATE_2_I,
I1 => G0_30,
I2 => WRP_V_WS_0_SQMUXA_1,
I3 => WRP_V_WS_3_SQMUXA_1,
LO => D_M1_E_L3);
II_g0_57_1_L7_L4: LUT4
generic map(
INIT => X"4555"
)
port map (
I0 => SSRSTATE6_1_D_0_L1,
I1 => n_ahbsi_htrans(0),
I2 => n_ahbsi_htrans(1),
I3 => WRP_R_SSRSTATE(1),
O => G0_57_1_L7_L4);
II_g0_57_1_L7_L8: LUT4_L
generic map(
INIT => X"4C40"
)
port map (
I0 => G0_57_1_L7_L4,
I1 => G0_57_1_L7_L6,
I2 => WRP_CTRL_V_HMBSEL_4(1),
I3 => WRP_R_SSRSTATE(2),
LO => G0_57_1_L7_L8);
II_g0_57_1_L7: LUT4_L
generic map(
INIT => X"4F5F"
)
port map (
I0 => N_656,
I1 => G0_57_1_L7_L8,
I2 => rst,
I3 => SSRSTATE6_XX_MM_M3,
LO => G0_57_1_L7);
II_g0_34_L10_L1: LUT4
generic map(
INIT => X"0400"
)
port map (
I0 => n_ahbsi_htrans(0),
I1 => n_ahbsi_htrans(1),
I2 => n_ahbsi_hwrite,
I3 => WRP_R_SSRSTATE(1),
O => G0_34_L10_L1);
II_g0_34_L10_L3: LUT2
generic map(
INIT => X"7"
)
port map (
I0 => G0_34_L10_L1,
I1 => WRP_CTRL_V_HSEL_5,
O => G0_34_L10_L3);
II_g0_34_L10: LUT4
generic map(
INIT => X"00B0"
)
port map (
I0 => G0_34_L10_L3,
I1 => WRP_CTRL_V_HMBSEL_4(1),
I2 => WRP_UN1_V_CHANGE_1_SQMUXA_0,
I3 => WRP_V_SSRSTATE_6_SQMUXA,
O => G0_34_L10);
II_g0_48_L1: LUT3
generic map(
INIT => X"40"
)
port map (
I0 => n_ahbsi_htrans(0),
I1 => n_ahbsi_htrans(1),
I2 => n_ahbsi_hwrite,
O => G0_48_L1);
II_g0_48: LUT4
generic map(
INIT => X"2000"
)
port map (
I0 => G0_48_L1,
I1 => WRP_CTRL_UN1_AHBSI,
I2 => WRP_CTRL_V_HMBSEL_4(1),
I3 => WRP_CTRL_V_HSEL_5,
O => WRP_V_LOADCOUNT_1_SQMUXA);
II_g0_36_L1: LUT3
generic map(
INIT => X"2F"
)
port map (
I0 => WRP_R_CHANGE,
I1 => WRP_R_HSEL,
I2 => WRP_R_PRSTATE(5),
O => G0_36_L1);
II_g0_36: LUT4
generic map(
INIT => X"2220"
)
port map (
I0 => G0_I_M2_1,
I1 => G0_36_L1,
I2 => WRP_CTRL_V_HSEL_5,
I3 => WRP_R_CHANGE,
O => WRP_V_PRSTATE_1_I_O4_S(2));
II_g0_55_L7: LUT4_L
generic map(
INIT => X"4CFC"
)
port map (
I0 => G0_55_L1,
I1 => G0_55_L5,
I2 => G0_55_L7_L1,
I3 => WRP_CTRL_V_HMBSEL_4(1),
LO => G0_55_L7);
II_g0_55_L5_L1: LUT4
generic map(
INIT => X"35FF"
)
port map (
I0 => D_M1_E_0_0,
I1 => n_ahbsi_hmbsel(1),
I2 => n_ahbsi_hready,
I3 => n_ahbsi_htrans(0),
O => G0_55_L5_L1);
II_g0_55_L5: LUT4
generic map(
INIT => X"51FF"
)
port map (
I0 => G0_55_L5_L1,
I1 => n_ahbsi_hready,
I2 => WRP_CTRL_V_HSEL_4,
I3 => WRP_R_SSRSTATE(2),
O => G0_55_L5);
II_g0_57_1_L5: LUT3
generic map(
INIT => X"70"
)
port map (
I0 => G0_30,
I1 => WRP_V_WS_0_SQMUXA_1,
I2 => WRP_V_WS_2_SQMUXA_3_D,
O => G0_57_1_L5);
II_g0_57_1: LUT4_L
generic map(
INIT => X"1D55"
)
port map (
I0 => N_365,
I1 => G0_57_1_L5,
I2 => G0_57_1_L7,
I3 => WRP_V_WS_2_SQMUXA_3_0_4,
LO => G0_57_1);
II_d_m1_e_L1: LUT4
generic map(
INIT => X"087F"
)
port map (
I0 => N_SRO_ROMSN_0_INT_260,
I1 => rst,
I2 => WRP_R_MCFG1_IOWS(3),
I3 => WRP_R_MCFG1_ROMWWS(3),
O => D_M1_E_L1);
II_g0_i_o4: LUT4_L
generic map(
INIT => X"FDF5"
)
port map (
I0 => N_365,
I1 => WS_2_SQMUXA_3_0_X,
I2 => WRP_V_WS_1_SQMUXA,
I3 => WRP_V_WS_2_SQMUXA_3_0_4,
LO => N_5);
II_g3_2: LUT4
generic map(
INIT => X"7FFF"
)
port map (
I0 => G0_50_X,
I1 => n_ahbsi_hmbsel(1),
I2 => n_ahbsi_hsel(0),
I3 => n_ahbsi_htrans(1),
O => N_19);
II_g0_50_x: LUT3_L
generic map(
INIT => X"80"
)
port map (
I0 => n_ahbsi_hready,
I1 => WRP_R_PRSTATE(5),
I2 => WRP_R_SSRSTATE(4),
LO => G0_50_X);
II_g0_52: MUXF5 port map (
I0 => G0_52X,
I1 => G0_52X_0,
S => n_ahbsi_htrans(1),
O => WRP_CTRL_UN1_V_SSRSTATE17_1_XX_MM_N_4);
II_g0_52_x1: LUT4
generic map(
INIT => X"35F5"
)
port map (
I0 => D_M1_E_0_0,
I1 => n_ahbsi_hmbsel(1),
I2 => n_ahbsi_hready,
I3 => n_ahbsi_hsel(0),
O => G0_52_X1);
II_g0_52_x0: LUT2
generic map(
INIT => X"D"
)
port map (
I0 => D_M1_E_0_0,
I1 => n_ahbsi_hready,
O => G0_52_X0);
II_g1_1: LUT4
generic map(
INIT => X"0105"
)
port map (
I0 => SSRSTATE17_2_0_M6_I_A3_A2,
I1 => n_ahbsi_htrans(1),
I2 => WRP_UN1_V_SSRSTATE17_2_0_M6_I_1,
I3 => WRP_UN1_V_SSRSTATE_1_SQMUXA_1_0_M3_0_1,
O => N_14);
II_g0_19_L1: LUT4_L
generic map(
INIT => X"0001"
)
port map (
I0 => G0_28,
I1 => WRP_CTRL_UN1_AHBSI,
I2 => WRP_CTRL_V_HMBSEL_4(1),
I3 => WRP_V_CHANGE_1_SQMUXA_N_3,
LO => G0_19_L1);
II_g0_19: LUT4
generic map(
INIT => X"0010"
)
port map (
I0 => G0_19_L1,
I1 => WRP_R_SSRSTATE(1),
I2 => WRP_UN1_V_CHANGE_1_SQMUXA_0,
I3 => WRP_V_SSRSTATE_6_SQMUXA,
O => N_622);
II_g0_55_L1: LUT4
generic map(
INIT => X"0400"
)
port map (
I0 => n_ahbsi_htrans(0),
I1 => n_ahbsi_htrans(1),
I2 => n_ahbsi_hwrite,
I3 => WRP_R_SSRSTATE(1),
O => G0_55_L1);
II_g0_55: LUT4
generic map(
INIT => X"0F0D"
)
port map (
I0 => G0_55_L7,
I1 => WRP_R_LOADCOUNT,
I2 => WRP_R_SSRSTATE(3),
I3 => WRP_V_SSRSTATE_1_SQMUXA_1,
O => WRP_CTRL_V_LOADCOUNT_7);
II_g0_34_L1_0: LUT2
generic map(
INIT => X"4"
)
port map (
I0 => WRP_R_D16MUXC_0_4,
I1 => WRP_V_WS_0_SQMUXA_0_C,
O => G0_34_L1_0);
II_g0_34_L6: LUT4
generic map(
INIT => X"A2AA"
)
port map (
I0 => G0_34_L1_0,
I1 => WRP_CTRL_V_HSEL_5,
I2 => WRP_R_SSRSTATE(0),
I3 => WRP_V_WS_0_SQMUXA_C,
O => G0_34_L6);
II_g0_34: LUT4_L
generic map(
INIT => X"51F3"
)
port map (
I0 => G0_34_L6,
I1 => G0_34_L10,
I2 => WRP_NONAME_CNST(0),
I3 => WRP_R_SSRSTATE(1),
LO => G0_34);
II_g0_54_L1: LUT4_L
generic map(
INIT => X"0400"
)
port map (
I0 => n_ahbsi_htrans(0),
I1 => n_ahbsi_htrans(1),
I2 => WRP_CTRL_UN1_AHBSI,
I3 => WRP_CTRL_V_HSEL_5,
LO => G0_54_L1);
II_g0_54: LUT4
generic map(
INIT => X"2000"
)
port map (
I0 => G0_54_L1,
I1 => n_ahbsi_hwrite,
I2 => WRP_CTRL_V_HMBSEL_4(1),
I3 => WRP_R_SSRSTATE(1),
O => WRP_CTRL_V_SSRSTATE_1_M1(3));
II_g0_i_m2_L1: LUT3
generic map(
INIT => X"75"
)
port map (
I0 => rst,
I1 => WRP_R_SSRSTATE(3),
I2 => WRP_V_SSRSTATE_1_SQMUXA_1,
O => G0_I_M2_L1);
II_g0_56: LUT4
generic map(
INIT => X"CC5A"
)
port map (
I0 => N_9,
I1 => WRP_R_MCFG1_ROMRWS(0),
I2 => WRP_R_WS(0),
I3 => WRP_V_WS_1_SQMUXA,
O => G0_56);
II_g1_3: LUT3_L
generic map(
INIT => X"37"
)
port map (
I0 => G0_30,
I1 => WRP_V_WS_0_SQMUXA_1,
I2 => WRP_V_WS_3_SQMUXA_1,
LO => N_9);
II_g0_30: LUT4
generic map(
INIT => X"AEAA"
)
port map (
I0 => N_14,
I1 => N_19,
I2 => G0_8,
I3 => WRP_R_SSRSTATE(4),
O => G0_30);
II_g0_16: LUT4
generic map(
INIT => X"337F"
)
port map (
I0 => N_SRO_ROMSN_0_INT_260,
I1 => rst,
I2 => WRP_V_WS_2_SQMUXA_0,
I3 => WRP_V_WS_4_SQMUXA_0,
O => N_365);
II_g0_8: LUT4
generic map(
INIT => X"4000"
)
port map (
I0 => n_ahbsi_hready,
I1 => WRP_R_HMBSEL(1),
I2 => WRP_R_HSEL,
I3 => WRP_R_PRSTATE(5),
O => G0_8);
II_g0_i_m2_2: LUT4
generic map(
INIT => X"F780"
)
port map (
I0 => N_SRO_ROMSN_0_INT_260,
I1 => rst,
I2 => WRP_R_MCFG1_IOWS(0),
I3 => WRP_R_MCFG1_ROMWWS(0),
O => G0_I_M2_2);
II_g0_7: LUT3
generic map(
INIT => X"54"
)
port map (
I0 => N_SRO_IOSN_INT_259,
I1 => WRP_R_PRSTATE(4),
I2 => WRP_R_PRSTATE_2_REP1,
O => WRP_V_WS_2_SQMUXA_0);
II_g0_6: LUT2
generic map(
INIT => X"4"
)
port map (
I0 => N_SRO_ROMSN_0_INT_260,
I1 => WRP_R_PRSTATE_FAST(2),
O => WRP_V_WS_4_SQMUXA_0);
II_g0_53: LUT4
generic map(
INIT => X"1050"
)
port map (
I0 => G0_51,
I1 => WRP_CTRL_V_HSEL_4,
I2 => WRP_R_SSRSTATE(4),
I3 => WRP_V_SSRSTATE_1_SQMUXA_1_XX_MM_A1_0,
O => WRP_V_SSRSTATE_1_SQMUXA_1);
II_g0_51: LUT4
generic map(
INIT => X"2000"
)
port map (
I0 => G0_8_1,
I1 => n_ahbsi_hready,
I2 => WRP_R_HMBSEL(1),
I3 => WRP_R_HSEL,
O => G0_51);
II_g0_50: LUT4
generic map(
INIT => X"8000"
)
port map (
I0 => n_ahbsi_hmbsel(1),
I1 => n_ahbsi_hready,
I2 => WRP_R_PRSTATE(5),
I3 => WRP_R_SSRSTATE(4),
O => WRP_V_SSRSTATE_1_SQMUXA_1_XX_MM_A1_0);
II_g0_8_1: LUT2
generic map(
INIT => X"8"
)
port map (
I0 => WRP_R_PRSTATE(5),
I1 => WRP_R_SSRSTATE(4),
O => G0_8_1);
II_g0_4: LUT2
generic map(
INIT => X"8"
)
port map (
I0 => WRP_R_HMBSEL(1),
I1 => WRP_R_HSEL,
O => D_M1_E_0_0);
II_g0_3: LUT2
generic map(
INIT => X"8"
)
port map (
I0 => n_ahbsi_hsel(0),
I1 => n_ahbsi_htrans(1),
O => WRP_CTRL_V_HSEL_4);
II_g0_i_0: LUT4
generic map(
INIT => X"AA80"
)
port map (
I0 => G0_I_A3_0,
I1 => rst,
I2 => WRP_R_PRSTATE(2),
I3 => WRP_V_BWN_0_SQMUXA_1,
O => WRP_CTRL_V_BWN_1_0_O3(0));
II_g0_2: LUT4
generic map(
INIT => X"C4CC"
)
port map (
I0 => WRP_CTRL_V_HMBSEL_4(1),
I1 => SSRSTATE6_XX_MM_M3,
I2 => WRP_V_CHANGE_1_SQMUXA_N_3,
I3 => WRP_V_SSRHREADY_2_SQMUXA_0_0,
O => N_646);
II_g0_i_a3_0: LUT4_L
generic map(
INIT => X"5D7F"
)
port map (
I0 => N_319_1,
I1 => N_662,
I2 => n_ahbsi_haddr(0),
I3 => N_SRO_ADDRESS_0_INT_172,
LO => G0_I_A3_0);
II_g0: LUT3
generic map(
INIT => X"D8"
)
port map (
I0 => N_662,
I1 => n_ahbsi_haddr(1),
I2 => N_SRO_ADDRESS_1_INT_173,
O => WRP_HADDR(1));
II_g0_i: LUT4
generic map(
INIT => X"F3A2"
)
port map (
I0 => G0_11,
I1 => n_ahbsi_htrans(0),
I2 => WRP_CTRL_UN1_V_SSRSTATE17_1_XX_MM_N_4,
I3 => WRP_R_D16MUXC_0_4,
O => G0_I);
II_g0_47: LUT4
generic map(
INIT => X"202A"
)
port map (
I0 => rst,
I1 => WRP_R_D16MUXC_0_4,
I2 => WRP_R_PRSTATE(1),
I3 => WRP_R_PRSTATE_2_REP1,
O => WRP_V_BWN_0_SQMUXA_1);
II_g0_38: LUT3
generic map(
INIT => X"D8"
)
port map (
I0 => N_662,
I1 => n_ahbsi_hsize(1),
I2 => WRP_R_SIZE(1),
O => WRP_CTRL_HSIZE_1(1));
II_g0_11: LUT2_L
generic map(
INIT => X"4"
)
port map (
I0 => WRP_CTRL_UN1_AHBSI,
I1 => WRP_CTRL_V_HSEL_5,
LO => G0_11);
II_g0_44: LUT4
generic map(
INIT => X"BBBA"
)
port map (
I0 => G0_5_0,
I1 => WRP_CTRL_UN7_BUS16EN,
I2 => WRP_R_PRSTATE(0),
I3 => WRP_V_D16MUX_0_SQMUXA,
O => G0_44);
II_g0_43: LUT4
generic map(
INIT => X"0400"
)
port map (
I0 => N_SRO_ADDRESS_1_INT_173,
I1 => WRP_CTRL_BUS16EN,
I2 => WRP_R_SIZE(0),
I3 => WRP_R_SIZE(1),
O => WRP_CTRL_UN7_BUS16EN);
II_g0_41: LUT2
generic map(
INIT => X"E"
)
port map (
I0 => N_17,
I1 => WRP_R_CHANGE,
O => G0_1_0);
II_g0_5_0: LUT2
generic map(
INIT => X"E"
)
port map (
I0 => WRP_R_PRHREADY,
I1 => WRP_R_PRSTATE(5),
O => G0_5_0);
II_g0_40: LUT2
generic map(
INIT => X"4"
)
port map (
I0 => WRP_CTRL_UN1_AHBSI,
I1 => WRP_CTRL_V_HSEL_5,
O => N_17);
II_g0_39: LUT2
generic map(
INIT => X"8"
)
port map (
I0 => WRP_R_D16MUXC_0_4,
I1 => WRP_R_PRSTATE(3),
O => WRP_V_D16MUX_0_SQMUXA);
II_g0_18: LUT3
generic map(
INIT => X"A2"
)
port map (
I0 => G0_7_0,
I1 => WRP_CTRL_V_HMBSEL_4(1),
I2 => WRP_R_CHANGE,
O => WRP_CTRL_V_CHANGE_3_F1_D_0_0);
II_g0_17: LUT4
generic map(
INIT => X"A808"
)
port map (
I0 => G0_I_M2_1,
I1 => WRP_CTRL_V_HSEL_5,
I2 => WRP_R_CHANGE,
I3 => WRP_R_HSEL,
O => WRP_UN1_V_HSEL_1(0));
II_g0_7_0: LUT4
generic map(
INIT => X"00FE"
)
port map (
I0 => WRP_R_CHANGE,
I1 => WRP_R_SSRSTATE(1),
I2 => WRP_R_SSRSTATE(2),
I3 => WRP_R_SSRSTATE(4),
O => G0_7_0);
II_g0_15: LUT4
generic map(
INIT => X"00FE"
)
port map (
I0 => WRP_R_CHANGE,
I1 => WRP_R_SSRSTATE(1),
I2 => WRP_R_SSRSTATE(2),
I3 => WRP_R_SSRSTATE(4),
O => WRP_CTRL_V_CHANGE_3_F0);
II_g0_i_m2_1: LUT4
generic map(
INIT => X"3353"
)
port map (
I0 => HSEL_1_0_L3,
I1 => G0_14,
I2 => n_ahbsi_hready,
I3 => WRP_R_CHANGE,
O => G0_I_M2_1);
II_g0_14: LUT2
generic map(
INIT => X"1"
)
port map (
I0 => WRP_R_HMBSEL(0),
I1 => WRP_R_HMBSEL(2),
O => G0_14);
II_g0_33: LUT4
generic map(
INIT => X"085D"
)
port map (
I0 => G0_31,
I1 => G2_1_0,
I2 => WRP_R_SSRSTATE(1),
I3 => WRP_V_CHANGE_1_SQMUXA_N_3,
O => WRP_UN1_V_CHANGE_1_SQMUXA_0);
II_g0_32: LUT4
generic map(
INIT => X"0001"
)
port map (
I0 => G0_28,
I1 => WRP_CTRL_UN1_AHBSI,
I2 => WRP_CTRL_V_HMBSEL_4(1),
I3 => WRP_V_CHANGE_1_SQMUXA_N_3,
O => WRP_NONAME_CNST(0));
II_g0_31: LUT4
generic map(
INIT => X"FFAB"
)
port map (
I0 => G0_28,
I1 => n_ahbsi_htrans(0),
I2 => n_ahbsi_htrans(1),
I3 => WRP_R_SSRSTATE(0),
O => G0_31);
II_g2_1_0: LUT2
generic map(
INIT => X"1"
)
port map (
I0 => WRP_R_SSRSTATE(0),
I1 => WRP_R_SSRSTATE(2),
O => G2_1_0);
II_g0_29: LUT2
generic map(
INIT => X"2"
)
port map (
I0 => n_ahbsi_hwrite,
I1 => WRP_V_SSRSTATE_1_SQMUXA_1,
O => G0_29);
II_g0_28: LUT2
generic map(
INIT => X"1"
)
port map (
I0 => WRP_R_SSRSTATE(1),
I1 => WRP_R_SSRSTATE(2),
O => G0_28);
II_g0_27: LUT2
generic map(
INIT => X"8"
)
port map (
I0 => rst,
I1 => WRP_R_SSRSTATE(3),
O => WRP_V_SSRSTATE_2_SQMUXA_1);
II_g0_25: LUT2
generic map(
INIT => X"2"
)
port map (
I0 => N_365,
I1 => WRP_V_WS_1_SQMUXA,
O => G0_25);
II_g0_23: LUT3
generic map(
INIT => X"37"
)
port map (
I0 => G0_30,
I1 => WRP_V_WS_0_SQMUXA_1,
I2 => WRP_V_WS_3_SQMUXA_1,
O => G0_23);
II_g0_12: LUT2
generic map(
INIT => X"1"
)
port map (
I0 => WRP_R_SSRSTATE(0),
I1 => WRP_R_SSRSTATE(2),
O => D_M2_0_A2_0);
II_g0_10: LUT2
generic map(
INIT => X"2"
)
port map (
I0 => rst,
I1 => WRP_R_SSRSTATE(3),
O => WRP_UN1_V_SSRSTATE_2_SQMUXA_I);
II_g0_1: LUT4
generic map(
INIT => X"FFD5"
)
port map (
I0 => G0_I,
I1 => rst,
I2 => WRP_R_PRSTATE(2),
I3 => WRP_V_LOADCOUNT_1_SQMUXA,
O => WRP_UN1_V_BWN_1_SQMUXA_2_D_0_2);
II_N_574_i: LUT4_L
generic map(
INIT => X"5545"
)
port map (
I0 => N_593,
I1 => N_596,
I2 => D_M1_E_0_0,
I3 => n_ahbsi_hready,
LO => N_574_I);
II_N_574_i_a3_0: LUT4_L
generic map(
INIT => X"4000"
)
port map (
I0 => N_597,
I1 => n_ahbsi_hmbsel(1),
I2 => n_ahbsi_hready,
I3 => WRP_CTRL_V_HSEL_4,
LO => N_593);
II_N_574_i_o3_0: LUT4
generic map(
INIT => X"135F"
)
port map (
I0 => n_ahbsi_htrans(1),
I1 => WRP_R_PRSTATE(5),
I2 => WRP_R_SSRSTATE(1),
I3 => WRP_R_SSRSTATE(4),
O => N_596);
II_N_574_i_o3: LUT3
generic map(
INIT => X"13"
)
port map (
I0 => WRP_R_PRSTATE(5),
I1 => WRP_R_SSRSTATE(1),
I2 => WRP_R_SSRSTATE(4),
O => N_597);
II_wrp: ssrctrl_unisim_netlist port map (
n_sro_vbdrive(0) => n_sro_vbdrive(0),
n_sro_vbdrive(1) => n_sro_vbdrive(1),
n_sro_vbdrive(2) => n_sro_vbdrive(2),
n_sro_vbdrive(3) => n_sro_vbdrive(3),
n_sro_vbdrive(4) => n_sro_vbdrive(4),
n_sro_vbdrive(5) => n_sro_vbdrive(5),
n_sro_vbdrive(6) => n_sro_vbdrive(6),
n_sro_vbdrive(7) => n_sro_vbdrive(7),
n_sro_vbdrive(8) => n_sro_vbdrive(8),
n_sro_vbdrive(9) => n_sro_vbdrive(9),
n_sro_vbdrive(10) => n_sro_vbdrive(10),
n_sro_vbdrive(11) => n_sro_vbdrive(11),
n_sro_vbdrive(12) => n_sro_vbdrive(12),
n_sro_vbdrive(13) => n_sro_vbdrive(13),
n_sro_vbdrive(14) => n_sro_vbdrive(14),
n_sro_vbdrive(15) => n_sro_vbdrive(15),
n_sro_vbdrive(16) => n_sro_vbdrive(16),
n_sro_vbdrive(17) => n_sro_vbdrive(17),
n_sro_vbdrive(18) => n_sro_vbdrive(18),
n_sro_vbdrive(19) => n_sro_vbdrive(19),
n_sro_vbdrive(20) => n_sro_vbdrive(20),
n_sro_vbdrive(21) => n_sro_vbdrive(21),
n_sro_vbdrive(22) => n_sro_vbdrive(22),
n_sro_vbdrive(23) => n_sro_vbdrive(23),
n_sro_vbdrive(24) => n_sro_vbdrive(24),
n_sro_vbdrive(25) => n_sro_vbdrive(25),
n_sro_vbdrive(26) => n_sro_vbdrive(26),
n_sro_vbdrive(27) => n_sro_vbdrive(27),
n_sro_vbdrive(28) => n_sro_vbdrive(28),
n_sro_vbdrive(29) => n_sro_vbdrive(29),
n_sro_vbdrive(30) => n_sro_vbdrive(30),
n_sro_vbdrive(31) => n_sro_vbdrive(31),
n_ahbso_hrdata(0) => n_ahbso_hrdata(0),
n_ahbso_hrdata(1) => n_ahbso_hrdata(1),
n_ahbso_hrdata(2) => n_ahbso_hrdata(2),
n_ahbso_hrdata(3) => n_ahbso_hrdata(3),
n_ahbso_hrdata(4) => n_ahbso_hrdata(4),
n_ahbso_hrdata(5) => n_ahbso_hrdata(5),
n_ahbso_hrdata(6) => n_ahbso_hrdata(6),
n_ahbso_hrdata(7) => n_ahbso_hrdata(7),
n_ahbso_hrdata(8) => n_ahbso_hrdata(8),
n_ahbso_hrdata(9) => n_ahbso_hrdata(9),
n_ahbso_hrdata(10) => n_ahbso_hrdata(10),
n_ahbso_hrdata(11) => n_ahbso_hrdata(11),
n_ahbso_hrdata(12) => n_ahbso_hrdata(12),
n_ahbso_hrdata(13) => n_ahbso_hrdata(13),
n_ahbso_hrdata(14) => n_ahbso_hrdata(14),
n_ahbso_hrdata(15) => n_ahbso_hrdata(15),
n_ahbso_hrdata(16) => n_ahbso_hrdata(16),
n_ahbso_hrdata(17) => n_ahbso_hrdata(17),
n_ahbso_hrdata(18) => n_ahbso_hrdata(18),
n_ahbso_hrdata(19) => n_ahbso_hrdata(19),
n_ahbso_hrdata(20) => n_ahbso_hrdata(20),
n_ahbso_hrdata(21) => n_ahbso_hrdata(21),
n_ahbso_hrdata(22) => n_ahbso_hrdata(22),
n_ahbso_hrdata(23) => n_ahbso_hrdata(23),
n_ahbso_hrdata(24) => n_ahbso_hrdata(24),
n_ahbso_hrdata(25) => n_ahbso_hrdata(25),
n_ahbso_hrdata(26) => n_ahbso_hrdata(26),
n_ahbso_hrdata(27) => n_ahbso_hrdata(27),
n_ahbso_hrdata(28) => n_ahbso_hrdata(28),
n_ahbso_hrdata(29) => n_ahbso_hrdata(29),
n_ahbso_hrdata(30) => n_ahbso_hrdata(30),
n_ahbso_hrdata(31) => n_ahbso_hrdata(31),
iows_0 => WRP_R_MCFG1_IOWS(0),
iows_3 => WRP_R_MCFG1_IOWS(3),
romwws_0 => WRP_R_MCFG1_ROMWWS(0),
romwws_3 => WRP_R_MCFG1_ROMWWS(3),
romrws_0 => WRP_R_MCFG1_ROMRWS(0),
romrws_3 => WRP_R_MCFG1_ROMRWS(3),
NoName_cnst(0) => WRP_NONAME_CNST(0),
n_sri_bwidth(0) => n_sri_bwidth(0),
n_sri_bwidth(1) => n_sri_bwidth(1),
n_apbi_pwdata_19 => n_apbi_pwdata(19),
n_apbi_pwdata_11 => n_apbi_pwdata(11),
n_apbi_pwdata_9 => n_apbi_pwdata(9),
n_apbi_pwdata_8 => n_apbi_pwdata(8),
n_apbi_pwdata_23 => n_apbi_pwdata(23),
n_apbi_pwdata_22 => n_apbi_pwdata(22),
n_apbi_pwdata_21 => n_apbi_pwdata(21),
n_apbi_pwdata_20 => n_apbi_pwdata(20),
n_apbi_pwdata_3 => n_apbi_pwdata(3),
n_apbi_pwdata_2 => n_apbi_pwdata(2),
n_apbi_pwdata_1 => n_apbi_pwdata(1),
n_apbi_pwdata_0 => n_apbi_pwdata(0),
n_apbi_pwdata_7 => n_apbi_pwdata(7),
n_apbi_pwdata_6 => n_apbi_pwdata(6),
n_apbi_pwdata_5 => n_apbi_pwdata(5),
n_apbi_pwdata_4 => n_apbi_pwdata(4),
n_apbi_psel(0) => n_apbi_psel(0),
n_apbi_paddr(2) => n_apbi_paddr(2),
n_apbi_paddr(3) => n_apbi_paddr(3),
n_apbi_paddr(4) => n_apbi_paddr(4),
n_apbi_paddr(5) => n_apbi_paddr(5),
n_apbo_prdata_0 => n_apbo_prdata(0),
n_apbo_prdata_4 => n_apbo_prdata(4),
n_apbo_prdata_20 => n_apbo_prdata(20),
n_apbo_prdata_23 => n_apbo_prdata(23),
n_apbo_prdata_22 => n_apbo_prdata(22),
n_apbo_prdata_21 => n_apbo_prdata(21),
n_apbo_prdata_19 => n_apbo_prdata(19),
n_apbo_prdata_7 => n_apbo_prdata(7),
n_apbo_prdata_6 => n_apbo_prdata(6),
n_apbo_prdata_5 => n_apbo_prdata(5),
n_apbo_prdata_3 => n_apbo_prdata(3),
n_apbo_prdata_2 => n_apbo_prdata(2),
n_apbo_prdata_1 => n_apbo_prdata(1),
n_apbo_prdata_11 => n_apbo_prdata(11),
n_apbo_prdata_9 => n_apbo_prdata(9),
n_apbo_prdata_8 => n_apbo_prdata(8),
n_apbo_prdata_28 => n_apbo_prdata(28),
n_sro_romsn(0) => N_SRO_ROMSN_0_INT_260,
n_ahbsi_hsel(0) => n_ahbsi_hsel(0),
prstate_fast(2) => WRP_R_PRSTATE_FAST(2),
n_ahbsi_htrans(0) => n_ahbsi_htrans(0),
n_ahbsi_htrans(1) => n_ahbsi_htrans(1),
ssrstate_1_m1(3) => WRP_CTRL_V_SSRSTATE_1_M1(3),
ssrstate_1_m1(4) => WRP_CTRL_V_SSRSTATE_1_M1(4),
hsel_1(0) => WRP_UN1_V_HSEL_1(0),
hmbsel_4(1) => WRP_CTRL_V_HMBSEL_4(1),
n_sro_bdrive(3) => N_SRO_BDRIVE_3_INT_269_INT_270_INT_271_INT_272,
ws_1_0 => WRP_CTRL_V_WS_1(0),
ws_1_3 => WRP_CTRL_V_WS_1(3),
ws(0) => WRP_R_WS(0),
ws(1) => WRP_R_WS(1),
ws(2) => WRP_R_WS(2),
ws(3) => WRP_R_WS(3),
ssrstate_1_2 => WRP_CTRL_V_SSRSTATE_1(4),
n_ahbsi_haddr(0) => n_ahbsi_haddr(0),
n_ahbsi_haddr(1) => n_ahbsi_haddr(1),
n_ahbsi_haddr(2) => n_ahbsi_haddr(2),
n_ahbsi_haddr(3) => n_ahbsi_haddr(3),
n_ahbsi_haddr(4) => n_ahbsi_haddr(4),
n_ahbsi_haddr(5) => n_ahbsi_haddr(5),
n_ahbsi_haddr(6) => n_ahbsi_haddr(6),
n_ahbsi_haddr(7) => n_ahbsi_haddr(7),
n_ahbsi_haddr(8) => n_ahbsi_haddr(8),
n_ahbsi_haddr(9) => n_ahbsi_haddr(9),
n_ahbsi_haddr(10) => n_ahbsi_haddr(10),
n_ahbsi_haddr(11) => n_ahbsi_haddr(11),
n_ahbsi_haddr(12) => n_ahbsi_haddr(12),
n_ahbsi_haddr(13) => n_ahbsi_haddr(13),
n_ahbsi_haddr(14) => n_ahbsi_haddr(14),
n_ahbsi_haddr(15) => n_ahbsi_haddr(15),
n_ahbsi_haddr(16) => n_ahbsi_haddr(16),
n_ahbsi_haddr(17) => n_ahbsi_haddr(17),
n_ahbsi_haddr(18) => n_ahbsi_haddr(18),
n_ahbsi_haddr(19) => n_ahbsi_haddr(19),
n_ahbsi_haddr(20) => n_ahbsi_haddr(20),
n_ahbsi_haddr(21) => n_ahbsi_haddr(21),
n_ahbsi_haddr(22) => n_ahbsi_haddr(22),
n_ahbsi_haddr(23) => n_ahbsi_haddr(23),
n_ahbsi_haddr(24) => n_ahbsi_haddr(24),
n_ahbsi_haddr(25) => n_ahbsi_haddr(25),
n_ahbsi_haddr(26) => n_ahbsi_haddr(26),
n_ahbsi_haddr(27) => n_ahbsi_haddr(27),
n_ahbsi_haddr(28) => n_ahbsi_haddr(28),
n_ahbsi_haddr(29) => n_ahbsi_haddr(29),
n_ahbsi_haddr(30) => n_ahbsi_haddr(30),
n_ahbsi_haddr(31) => n_ahbsi_haddr(31),
n_ahbsi_hmbsel(0) => n_ahbsi_hmbsel(0),
n_ahbsi_hmbsel(1) => n_ahbsi_hmbsel(1),
n_ahbsi_hmbsel(2) => n_ahbsi_hmbsel(2),
n_sri_data(0) => n_sri_data(0),
n_sri_data(1) => n_sri_data(1),
n_sri_data(2) => n_sri_data(2),
n_sri_data(3) => n_sri_data(3),
n_sri_data(4) => n_sri_data(4),
n_sri_data(5) => n_sri_data(5),
n_sri_data(6) => n_sri_data(6),
n_sri_data(7) => n_sri_data(7),
n_sri_data(8) => n_sri_data(8),
n_sri_data(9) => n_sri_data(9),
n_sri_data(10) => n_sri_data(10),
n_sri_data(11) => n_sri_data(11),
n_sri_data(12) => n_sri_data(12),
n_sri_data(13) => n_sri_data(13),
n_sri_data(14) => n_sri_data(14),
n_sri_data(15) => n_sri_data(15),
n_sri_data(16) => n_sri_data(16),
n_sri_data(17) => n_sri_data(17),
n_sri_data(18) => n_sri_data(18),
n_sri_data(19) => n_sri_data(19),
n_sri_data(20) => n_sri_data(20),
n_sri_data(21) => n_sri_data(21),
n_sri_data(22) => n_sri_data(22),
n_sri_data(23) => n_sri_data(23),
n_sri_data(24) => n_sri_data(24),
n_sri_data(25) => n_sri_data(25),
n_sri_data(26) => n_sri_data(26),
n_sri_data(27) => n_sri_data(27),
n_sri_data(28) => n_sri_data(28),
n_sri_data(29) => n_sri_data(29),
n_sri_data(30) => n_sri_data(30),
n_sri_data(31) => n_sri_data(31),
ssrstate(0) => WRP_R_SSRSTATE(0),
ssrstate(1) => WRP_R_SSRSTATE(1),
ssrstate(2) => WRP_R_SSRSTATE(2),
ssrstate(3) => WRP_R_SSRSTATE(3),
ssrstate(4) => WRP_R_SSRSTATE(4),
n_ahbsi_hwdata(0) => n_ahbsi_hwdata(0),
n_ahbsi_hwdata(1) => n_ahbsi_hwdata(1),
n_ahbsi_hwdata(2) => n_ahbsi_hwdata(2),
n_ahbsi_hwdata(3) => n_ahbsi_hwdata(3),
n_ahbsi_hwdata(4) => n_ahbsi_hwdata(4),
n_ahbsi_hwdata(5) => n_ahbsi_hwdata(5),
n_ahbsi_hwdata(6) => n_ahbsi_hwdata(6),
n_ahbsi_hwdata(7) => n_ahbsi_hwdata(7),
n_ahbsi_hwdata(8) => n_ahbsi_hwdata(8),
n_ahbsi_hwdata(9) => n_ahbsi_hwdata(9),
n_ahbsi_hwdata(10) => n_ahbsi_hwdata(10),
n_ahbsi_hwdata(11) => n_ahbsi_hwdata(11),
n_ahbsi_hwdata(12) => n_ahbsi_hwdata(12),
n_ahbsi_hwdata(13) => n_ahbsi_hwdata(13),
n_ahbsi_hwdata(14) => n_ahbsi_hwdata(14),
n_ahbsi_hwdata(15) => n_ahbsi_hwdata(15),
n_ahbsi_hwdata(16) => n_ahbsi_hwdata(16),
n_ahbsi_hwdata(17) => n_ahbsi_hwdata(17),
n_ahbsi_hwdata(18) => n_ahbsi_hwdata(18),
n_ahbsi_hwdata(19) => n_ahbsi_hwdata(19),
n_ahbsi_hwdata(20) => n_ahbsi_hwdata(20),
n_ahbsi_hwdata(21) => n_ahbsi_hwdata(21),
n_ahbsi_hwdata(22) => n_ahbsi_hwdata(22),
n_ahbsi_hwdata(23) => n_ahbsi_hwdata(23),
n_ahbsi_hwdata(24) => n_ahbsi_hwdata(24),
n_ahbsi_hwdata(25) => n_ahbsi_hwdata(25),
n_ahbsi_hwdata(26) => n_ahbsi_hwdata(26),
n_ahbsi_hwdata(27) => n_ahbsi_hwdata(27),
n_ahbsi_hwdata(28) => n_ahbsi_hwdata(28),
n_ahbsi_hwdata(29) => n_ahbsi_hwdata(29),
n_ahbsi_hwdata(30) => n_ahbsi_hwdata(30),
n_ahbsi_hwdata(31) => n_ahbsi_hwdata(31),
n_ahbsi_hsize(0) => n_ahbsi_hsize(0),
n_ahbsi_hsize(1) => n_ahbsi_hsize(1),
size(0) => WRP_R_SIZE(0),
size(1) => WRP_R_SIZE(1),
n_sro_data(0) => n_sro_data(0),
n_sro_data(1) => n_sro_data(1),
n_sro_data(2) => n_sro_data(2),
n_sro_data(3) => n_sro_data(3),
n_sro_data(4) => n_sro_data(4),
n_sro_data(5) => n_sro_data(5),
n_sro_data(6) => n_sro_data(6),
n_sro_data(7) => n_sro_data(7),
n_sro_data(8) => n_sro_data(8),
n_sro_data(9) => n_sro_data(9),
n_sro_data(10) => n_sro_data(10),
n_sro_data(11) => n_sro_data(11),
n_sro_data(12) => n_sro_data(12),
n_sro_data(13) => n_sro_data(13),
n_sro_data(14) => n_sro_data(14),
n_sro_data(15) => n_sro_data(15),
n_sro_data(16) => n_sro_data(16),
n_sro_data(17) => n_sro_data(17),
n_sro_data(18) => n_sro_data(18),
n_sro_data(19) => n_sro_data(19),
n_sro_data(20) => n_sro_data(20),
n_sro_data(21) => n_sro_data(21),
n_sro_data(22) => n_sro_data(22),
n_sro_data(23) => n_sro_data(23),
n_sro_data(24) => n_sro_data(24),
n_sro_data(25) => n_sro_data(25),
n_sro_data(26) => n_sro_data(26),
n_sro_data(27) => n_sro_data(27),
n_sro_data(28) => n_sro_data(28),
n_sro_data(29) => n_sro_data(29),
n_sro_data(30) => n_sro_data(30),
n_sro_data(31) => n_sro_data(31),
n_sro_ramsn(0) => n_sro_ramsn(0),
n_sro_wrn(0) => n_sro_wrn(0),
n_sro_wrn(1) => n_sro_wrn(1),
n_sro_wrn(2) => n_sro_wrn(2),
n_sro_wrn(3) => n_sro_wrn(3),
haddr_0 => WRP_HADDR(1),
bwn_1_0_o3_0 => WRP_CTRL_V_BWN_1_0_O3(0),
hsize_1(1) => WRP_CTRL_HSIZE_1(1),
prstate_1_i_o4_s(2) => WRP_V_PRSTATE_1_I_O4_S(2),
prstate(0) => WRP_R_PRSTATE(0),
prstate(1) => WRP_R_PRSTATE(1),
prstate(2) => WRP_R_PRSTATE(2),
prstate(3) => WRP_R_PRSTATE(3),
prstate(4) => WRP_R_PRSTATE(4),
prstate(5) => WRP_R_PRSTATE(5),
hmbsel(0) => WRP_R_HMBSEL(0),
hmbsel(1) => WRP_R_HMBSEL(1),
hmbsel(2) => WRP_R_HMBSEL(2),
n_sro_address(0) => N_SRO_ADDRESS_0_INT_172,
n_sro_address(1) => N_SRO_ADDRESS_1_INT_173,
n_sro_address(2) => n_sro_address(2),
n_sro_address(3) => n_sro_address(3),
n_sro_address(4) => n_sro_address(4),
n_sro_address(5) => n_sro_address(5),
n_sro_address(6) => n_sro_address(6),
n_sro_address(7) => n_sro_address(7),
n_sro_address(8) => n_sro_address(8),
n_sro_address(9) => n_sro_address(9),
n_sro_address(10) => n_sro_address(10),
n_sro_address(11) => n_sro_address(11),
n_sro_address(12) => n_sro_address(12),
n_sro_address(13) => n_sro_address(13),
n_sro_address(14) => n_sro_address(14),
n_sro_address(15) => n_sro_address(15),
n_sro_address(16) => n_sro_address(16),
n_sro_address(17) => n_sro_address(17),
n_sro_address(18) => n_sro_address(18),
n_sro_address(19) => n_sro_address(19),
n_sro_address(20) => n_sro_address(20),
n_sro_address(21) => n_sro_address(21),
n_sro_address(22) => n_sro_address(22),
n_sro_address(23) => n_sro_address(23),
n_sro_address(24) => n_sro_address(24),
n_sro_address(25) => n_sro_address(25),
n_sro_address(26) => n_sro_address(26),
n_sro_address(27) => n_sro_address(27),
n_sro_address(28) => n_sro_address(28),
n_sro_address(29) => n_sro_address(29),
n_sro_address(30) => n_sro_address(30),
n_sro_address(31) => n_sro_address(31),
hready_2 => WRP_CTRL_V_HREADY_2,
n_ahbso_hready => n_ahbso_hready,
ssrhready_8 => WRP_CTRL_V_SSRHREADY_8,
loadcount => WRP_R_LOADCOUNT,
n_sro_writen => n_sro_writen,
ssrstatec => WRP_R_SSRSTATEC,
prhready => WRP_R_PRHREADY,
d_m2_0_a2_0 => D_M2_0_A2_0,
ssrstate17_2_0_m6_i_a3_a2 => SSRSTATE17_2_0_M6_I_A3_A2,
N_319_1 => N_319_1,
ws_0_sqmuxa_c => WRP_V_WS_0_SQMUXA_C,
N_365 => N_365,
ws_0_sqmuxa_0_c => WRP_V_WS_0_SQMUXA_0_C,
ws_2_sqmuxa_3_0_4 => WRP_V_WS_2_SQMUXA_3_0_4,
change_1_sqmuxa_0 => WRP_UN1_V_CHANGE_1_SQMUXA_0,
d16mux_0_sqmuxa => WRP_V_D16MUX_0_SQMUXA,
ssrstate_2_sqmuxa_1 => WRP_V_SSRSTATE_2_SQMUXA_1,
un7_bus16en => WRP_CTRL_UN7_BUS16EN,
N_646 => N_646,
loadcount_1_sqmuxa => WRP_V_LOADCOUNT_1_SQMUXA,
ssrstate_1_sqmuxa_1_0_m3_0_1 => WRP_UN1_V_SSRSTATE_1_SQMUXA_1_0_M3_0_1,
n_apbi_penable => n_apbi_penable,
n_apbi_pwrite => n_apbi_pwrite,
d_m1_e_0_0 => D_M1_E_0_0,
hsel_1_0_L3 => HSEL_1_0_L3,
ssrhready_8_f0_L8 => SSRHREADY_8_F0_L8,
ssrstate_1_sqmuxa_1 => WRP_V_SSRSTATE_1_SQMUXA_1,
ssrhready => WRP_R_SSRHREADY,
ssrhready_8_f0_L5 => SSRHREADY_8_F0_L5,
ssrstate17_1_xx_mm_N_4 => WRP_CTRL_UN1_V_SSRSTATE17_1_XX_MM_N_4,
ws_1_sqmuxa => WRP_V_WS_1_SQMUXA,
ws_4_sqmuxa_0 => WRP_V_WS_4_SQMUXA_0,
ws_2_sqmuxa_0 => WRP_V_WS_2_SQMUXA_0,
ssrstate17_2_0_m6_i_1 => WRP_UN1_V_SSRSTATE17_2_0_M6_I_1,
ws_2_sqmuxa_3_0_x => WS_2_SQMUXA_3_0_X,
ws_3_sqmuxa_1 => WRP_V_WS_3_SQMUXA_1,
ws_2_sqmuxa_3_0_2 => WRP_V_WS_2_SQMUXA_3_0_2,
ssrstate_2_i => WRP_UN1_R_SSRSTATE_2_I,
ws_2_sqmuxa_3_d => WRP_V_WS_2_SQMUXA_3_D,
ws_0_sqmuxa_1 => WRP_V_WS_0_SQMUXA_1,
g0_30 => G0_30,
hsel_4 => WRP_CTRL_V_HSEL_4,
n_ahbsi_hready => n_ahbsi_hready,
hsel => WRP_R_HSEL,
g0_25 => G0_25,
bwn_0_sqmuxa_1 => WRP_V_BWN_0_SQMUXA_1,
prstate_2_rep1 => WRP_R_PRSTATE_2_REP1,
N_662 => N_662,
ssrstate_6_sqmuxa => WRP_V_SSRSTATE_6_SQMUXA,
g0_52_x1 => G0_52_X1,
g0_52_x0 => G0_52_X0,
ssrhready_2_sqmuxa_0_0 => WRP_V_SSRHREADY_2_SQMUXA_0_0,
change_1_sqmuxa_N_3 => WRP_V_CHANGE_1_SQMUXA_N_3,
ssrstate6_xx_mm_m3 => SSRSTATE6_XX_MM_M3,
ssrstate6_1_d_0_L1 => SSRSTATE6_1_D_0_L1,
N_656 => N_656,
hsel_5 => WRP_CTRL_V_HSEL_5,
change_3_f0 => WRP_CTRL_V_CHANGE_3_F0,
un1_ahbsi => WRP_CTRL_UN1_AHBSI,
change => WRP_R_CHANGE,
n_ahbsi_hwrite => n_ahbsi_hwrite,
N_574_i => N_574_I,
n_sro_iosn => N_SRO_IOSN_INT_259,
N_618_i => N_618_I,
clk => clk,
n_sro_oen => N_SRO_OEN_INT_245_INT_246_INT_247_INT_248_INT_249_INT_250_INT_251_INT_252_INT_268,
rst => rst,
bwn_1_sqmuxa_2_d => WRP_UN1_V_BWN_1_SQMUXA_2_D,
bwn_1_sqmuxa_2_d_0_2 => WRP_UN1_V_BWN_1_SQMUXA_2_D_0_2,
ssrstate_2_sqmuxa_i => WRP_UN1_V_SSRSTATE_2_SQMUXA_I,
g0_23 => G0_23,
N_371 => N_371,
loadcount_7 => WRP_CTRL_V_LOADCOUNT_7,
bus16en => WRP_CTRL_BUS16EN,
d16muxc_0_4 => WRP_R_D16MUXC_0_4,
change_3_f1_d_0_0 => WRP_CTRL_V_CHANGE_3_F1_D_0_0,
g0_1_0 => G0_1_0,
g0_44 => G0_44);
II_GND: GND port map (
G => NN_2);
II_VCC: VCC port map (
P => NN_1);
n_ahbso_hresp(0) <= NN_2;
n_ahbso_hresp(1) <= NN_2;
n_ahbso_hsplit(0) <= NN_2;
n_ahbso_hsplit(1) <= NN_2;
n_ahbso_hsplit(2) <= NN_2;
n_ahbso_hsplit(3) <= NN_2;
n_ahbso_hsplit(4) <= NN_2;
n_ahbso_hsplit(5) <= NN_2;
n_ahbso_hsplit(6) <= NN_2;
n_ahbso_hsplit(7) <= NN_2;
n_ahbso_hsplit(8) <= NN_2;
n_ahbso_hsplit(9) <= NN_2;
n_ahbso_hsplit(10) <= NN_2;
n_ahbso_hsplit(11) <= NN_2;
n_ahbso_hsplit(12) <= NN_2;
n_ahbso_hsplit(13) <= NN_2;
n_ahbso_hsplit(14) <= NN_2;
n_ahbso_hsplit(15) <= NN_2;
n_ahbso_hcache <= NN_1;
n_ahbso_hirq(0) <= NN_2;
n_ahbso_hirq(1) <= NN_2;
n_ahbso_hirq(2) <= NN_2;
n_ahbso_hirq(3) <= NN_2;
n_ahbso_hirq(4) <= NN_2;
n_ahbso_hirq(5) <= NN_2;
n_ahbso_hirq(6) <= NN_2;
n_ahbso_hirq(7) <= NN_2;
n_ahbso_hirq(8) <= NN_2;
n_ahbso_hirq(9) <= NN_2;
n_ahbso_hirq(10) <= NN_2;
n_ahbso_hirq(11) <= NN_2;
n_ahbso_hirq(12) <= NN_2;
n_ahbso_hirq(13) <= NN_2;
n_ahbso_hirq(14) <= NN_2;
n_ahbso_hirq(15) <= NN_2;
n_ahbso_hirq(16) <= NN_2;
n_ahbso_hirq(17) <= NN_2;
n_ahbso_hirq(18) <= NN_2;
n_ahbso_hirq(19) <= NN_2;
n_ahbso_hirq(20) <= NN_2;
n_ahbso_hirq(21) <= NN_2;
n_ahbso_hirq(22) <= NN_2;
n_ahbso_hirq(23) <= NN_2;
n_ahbso_hirq(24) <= NN_2;
n_ahbso_hirq(25) <= NN_2;
n_ahbso_hirq(26) <= NN_2;
n_ahbso_hirq(27) <= NN_2;
n_ahbso_hirq(28) <= NN_2;
n_ahbso_hirq(29) <= NN_2;
n_ahbso_hirq(30) <= NN_2;
n_ahbso_hirq(31) <= NN_2;
n_apbo_prdata(10) <= NN_2;
n_apbo_prdata(12) <= NN_2;
n_apbo_prdata(13) <= NN_2;
n_apbo_prdata(14) <= NN_2;
n_apbo_prdata(15) <= NN_2;
n_apbo_prdata(16) <= NN_2;
n_apbo_prdata(17) <= NN_2;
n_apbo_prdata(18) <= NN_2;
n_apbo_prdata(24) <= NN_2;
n_apbo_prdata(25) <= NN_2;
n_apbo_prdata(26) <= NN_2;
n_apbo_prdata(27) <= NN_2;
n_apbo_prdata(29) <= NN_2;
n_apbo_prdata(30) <= NN_2;
n_apbo_prdata(31) <= NN_2;
n_apbo_pirq(0) <= NN_2;
n_apbo_pirq(1) <= NN_2;
n_apbo_pirq(2) <= NN_2;
n_apbo_pirq(3) <= NN_2;
n_apbo_pirq(4) <= NN_2;
n_apbo_pirq(5) <= NN_2;
n_apbo_pirq(6) <= NN_2;
n_apbo_pirq(7) <= NN_2;
n_apbo_pirq(8) <= NN_2;
n_apbo_pirq(9) <= NN_2;
n_apbo_pirq(10) <= NN_2;
n_apbo_pirq(11) <= NN_2;
n_apbo_pirq(12) <= NN_2;
n_apbo_pirq(13) <= NN_2;
n_apbo_pirq(14) <= NN_2;
n_apbo_pirq(15) <= NN_2;
n_apbo_pirq(16) <= NN_2;
n_apbo_pirq(17) <= NN_2;
n_apbo_pirq(18) <= NN_2;
n_apbo_pirq(19) <= NN_2;
n_apbo_pirq(20) <= NN_2;
n_apbo_pirq(21) <= NN_2;
n_apbo_pirq(22) <= NN_2;
n_apbo_pirq(23) <= NN_2;
n_apbo_pirq(24) <= NN_2;
n_apbo_pirq(25) <= NN_2;
n_apbo_pirq(26) <= NN_2;
n_apbo_pirq(27) <= NN_2;
n_apbo_pirq(28) <= NN_2;
n_apbo_pirq(29) <= NN_2;
n_apbo_pirq(30) <= NN_2;
n_apbo_pirq(31) <= NN_2;
n_sro_address(0) <= N_SRO_ADDRESS_0_INT_172;
n_sro_address(1) <= N_SRO_ADDRESS_1_INT_173;
n_sro_sddata(0) <= NN_2;
n_sro_sddata(1) <= NN_2;
n_sro_sddata(2) <= NN_2;
n_sro_sddata(3) <= NN_2;
n_sro_sddata(4) <= NN_2;
n_sro_sddata(5) <= NN_2;
n_sro_sddata(6) <= NN_2;
n_sro_sddata(7) <= NN_2;
n_sro_sddata(8) <= NN_2;
n_sro_sddata(9) <= NN_2;
n_sro_sddata(10) <= NN_2;
n_sro_sddata(11) <= NN_2;
n_sro_sddata(12) <= NN_2;
n_sro_sddata(13) <= NN_2;
n_sro_sddata(14) <= NN_2;
n_sro_sddata(15) <= NN_2;
n_sro_sddata(16) <= NN_2;
n_sro_sddata(17) <= NN_2;
n_sro_sddata(18) <= NN_2;
n_sro_sddata(19) <= NN_2;
n_sro_sddata(20) <= NN_2;
n_sro_sddata(21) <= NN_2;
n_sro_sddata(22) <= NN_2;
n_sro_sddata(23) <= NN_2;
n_sro_sddata(24) <= NN_2;
n_sro_sddata(25) <= NN_2;
n_sro_sddata(26) <= NN_2;
n_sro_sddata(27) <= NN_2;
n_sro_sddata(28) <= NN_2;
n_sro_sddata(29) <= NN_2;
n_sro_sddata(30) <= NN_2;
n_sro_sddata(31) <= NN_2;
n_sro_sddata(32) <= NN_2;
n_sro_sddata(33) <= NN_2;
n_sro_sddata(34) <= NN_2;
n_sro_sddata(35) <= NN_2;
n_sro_sddata(36) <= NN_2;
n_sro_sddata(37) <= NN_2;
n_sro_sddata(38) <= NN_2;
n_sro_sddata(39) <= NN_2;
n_sro_sddata(40) <= NN_2;
n_sro_sddata(41) <= NN_2;
n_sro_sddata(42) <= NN_2;
n_sro_sddata(43) <= NN_2;
n_sro_sddata(44) <= NN_2;
n_sro_sddata(45) <= NN_2;
n_sro_sddata(46) <= NN_2;
n_sro_sddata(47) <= NN_2;
n_sro_sddata(48) <= NN_2;
n_sro_sddata(49) <= NN_2;
n_sro_sddata(50) <= NN_2;
n_sro_sddata(51) <= NN_2;
n_sro_sddata(52) <= NN_2;
n_sro_sddata(53) <= NN_2;
n_sro_sddata(54) <= NN_2;
n_sro_sddata(55) <= NN_2;
n_sro_sddata(56) <= NN_2;
n_sro_sddata(57) <= NN_2;
n_sro_sddata(58) <= NN_2;
n_sro_sddata(59) <= NN_2;
n_sro_sddata(60) <= NN_2;
n_sro_sddata(61) <= NN_2;
n_sro_sddata(62) <= NN_2;
n_sro_sddata(63) <= NN_2;
n_sro_ramsn(1) <= NN_1;
n_sro_ramsn(2) <= NN_1;
n_sro_ramsn(3) <= NN_1;
n_sro_ramsn(4) <= NN_1;
n_sro_ramsn(5) <= NN_1;
n_sro_ramsn(6) <= NN_1;
n_sro_ramsn(7) <= NN_1;
n_sro_ramoen(0) <= N_SRO_OEN_INT_245_INT_246_INT_247_INT_248_INT_249_INT_250_INT_251_INT_252_INT_268;
n_sro_ramoen(1) <= N_SRO_OEN_INT_245_INT_246_INT_247_INT_248_INT_249_INT_250_INT_251_INT_252_INT_268;
n_sro_ramoen(2) <= N_SRO_OEN_INT_245_INT_246_INT_247_INT_248_INT_249_INT_250_INT_251_INT_252_INT_268;
n_sro_ramoen(3) <= N_SRO_OEN_INT_245_INT_246_INT_247_INT_248_INT_249_INT_250_INT_251_INT_252_INT_268;
n_sro_ramoen(4) <= N_SRO_OEN_INT_245_INT_246_INT_247_INT_248_INT_249_INT_250_INT_251_INT_252_INT_268;
n_sro_ramoen(5) <= N_SRO_OEN_INT_245_INT_246_INT_247_INT_248_INT_249_INT_250_INT_251_INT_252_INT_268;
n_sro_ramoen(6) <= N_SRO_OEN_INT_245_INT_246_INT_247_INT_248_INT_249_INT_250_INT_251_INT_252_INT_268;
n_sro_ramoen(7) <= N_SRO_OEN_INT_245_INT_246_INT_247_INT_248_INT_249_INT_250_INT_251_INT_252_INT_268;
n_sro_ramn <= NN_2;
n_sro_romn <= NN_2;
n_sro_mben(0) <= NN_2;
n_sro_mben(1) <= NN_2;
n_sro_mben(2) <= NN_2;
n_sro_mben(3) <= NN_2;
n_sro_iosn <= N_SRO_IOSN_INT_259;
n_sro_romsn(0) <= N_SRO_ROMSN_0_INT_260;
n_sro_romsn(1) <= NN_1;
n_sro_romsn(2) <= NN_1;
n_sro_romsn(3) <= NN_1;
n_sro_romsn(4) <= NN_1;
n_sro_romsn(5) <= NN_1;
n_sro_romsn(6) <= NN_1;
n_sro_romsn(7) <= NN_1;
n_sro_oen <= N_SRO_OEN_INT_245_INT_246_INT_247_INT_248_INT_249_INT_250_INT_251_INT_252_INT_268;
n_sro_bdrive(0) <= N_SRO_BDRIVE_3_INT_269_INT_270_INT_271_INT_272;
n_sro_bdrive(1) <= N_SRO_BDRIVE_3_INT_269_INT_270_INT_271_INT_272;
n_sro_bdrive(2) <= N_SRO_BDRIVE_3_INT_269_INT_270_INT_271_INT_272;
n_sro_bdrive(3) <= N_SRO_BDRIVE_3_INT_269_INT_270_INT_271_INT_272;
n_sro_svbdrive(0) <= NN_2;
n_sro_svbdrive(1) <= NN_2;
n_sro_svbdrive(2) <= NN_2;
n_sro_svbdrive(3) <= NN_2;
n_sro_svbdrive(4) <= NN_2;
n_sro_svbdrive(5) <= NN_2;
n_sro_svbdrive(6) <= NN_2;
n_sro_svbdrive(7) <= NN_2;
n_sro_svbdrive(8) <= NN_2;
n_sro_svbdrive(9) <= NN_2;
n_sro_svbdrive(10) <= NN_2;
n_sro_svbdrive(11) <= NN_2;
n_sro_svbdrive(12) <= NN_2;
n_sro_svbdrive(13) <= NN_2;
n_sro_svbdrive(14) <= NN_2;
n_sro_svbdrive(15) <= NN_2;
n_sro_svbdrive(16) <= NN_2;
n_sro_svbdrive(17) <= NN_2;
n_sro_svbdrive(18) <= NN_2;
n_sro_svbdrive(19) <= NN_2;
n_sro_svbdrive(20) <= NN_2;
n_sro_svbdrive(21) <= NN_2;
n_sro_svbdrive(22) <= NN_2;
n_sro_svbdrive(23) <= NN_2;
n_sro_svbdrive(24) <= NN_2;
n_sro_svbdrive(25) <= NN_2;
n_sro_svbdrive(26) <= NN_2;
n_sro_svbdrive(27) <= NN_2;
n_sro_svbdrive(28) <= NN_2;
n_sro_svbdrive(29) <= NN_2;
n_sro_svbdrive(30) <= NN_2;
n_sro_svbdrive(31) <= NN_2;
n_sro_svbdrive(32) <= NN_2;
n_sro_svbdrive(33) <= NN_2;
n_sro_svbdrive(34) <= NN_2;
n_sro_svbdrive(35) <= NN_2;
n_sro_svbdrive(36) <= NN_2;
n_sro_svbdrive(37) <= NN_2;
n_sro_svbdrive(38) <= NN_2;
n_sro_svbdrive(39) <= NN_2;
n_sro_svbdrive(40) <= NN_2;
n_sro_svbdrive(41) <= NN_2;
n_sro_svbdrive(42) <= NN_2;
n_sro_svbdrive(43) <= NN_2;
n_sro_svbdrive(44) <= NN_2;
n_sro_svbdrive(45) <= NN_2;
n_sro_svbdrive(46) <= NN_2;
n_sro_svbdrive(47) <= NN_2;
n_sro_svbdrive(48) <= NN_2;
n_sro_svbdrive(49) <= NN_2;
n_sro_svbdrive(50) <= NN_2;
n_sro_svbdrive(51) <= NN_2;
n_sro_svbdrive(52) <= NN_2;
n_sro_svbdrive(53) <= NN_2;
n_sro_svbdrive(54) <= NN_2;
n_sro_svbdrive(55) <= NN_2;
n_sro_svbdrive(56) <= NN_2;
n_sro_svbdrive(57) <= NN_2;
n_sro_svbdrive(58) <= NN_2;
n_sro_svbdrive(59) <= NN_2;
n_sro_svbdrive(60) <= NN_2;
n_sro_svbdrive(61) <= NN_2;
n_sro_svbdrive(62) <= NN_2;
n_sro_svbdrive(63) <= NN_2;
n_sro_read <= NN_2;
n_sro_sa(0) <= NN_2;
n_sro_sa(1) <= NN_2;
n_sro_sa(2) <= NN_2;
n_sro_sa(3) <= NN_2;
n_sro_sa(4) <= NN_2;
n_sro_sa(5) <= NN_2;
n_sro_sa(6) <= NN_2;
n_sro_sa(7) <= NN_2;
n_sro_sa(8) <= NN_2;
n_sro_sa(9) <= NN_2;
n_sro_sa(10) <= NN_2;
n_sro_sa(11) <= NN_2;
n_sro_sa(12) <= NN_2;
n_sro_sa(13) <= NN_2;
n_sro_sa(14) <= NN_2;
n_sro_cb(0) <= NN_2;
n_sro_cb(1) <= NN_2;
n_sro_cb(2) <= NN_2;
n_sro_cb(3) <= NN_2;
n_sro_cb(4) <= NN_2;
n_sro_cb(5) <= NN_2;
n_sro_cb(6) <= NN_2;
n_sro_cb(7) <= NN_2;
n_sro_scb(0) <= NN_2;
n_sro_scb(1) <= NN_2;
n_sro_scb(2) <= NN_2;
n_sro_scb(3) <= NN_2;
n_sro_scb(4) <= NN_2;
n_sro_scb(5) <= NN_2;
n_sro_scb(6) <= NN_2;
n_sro_scb(7) <= NN_2;
n_sro_vcdrive(0) <= NN_2;
n_sro_vcdrive(1) <= NN_2;
n_sro_vcdrive(2) <= NN_2;
n_sro_vcdrive(3) <= NN_2;
n_sro_vcdrive(4) <= NN_2;
n_sro_vcdrive(5) <= NN_2;
n_sro_vcdrive(6) <= NN_2;
n_sro_vcdrive(7) <= NN_2;
n_sro_svcdrive(0) <= NN_2;
n_sro_svcdrive(1) <= NN_2;
n_sro_svcdrive(2) <= NN_2;
n_sro_svcdrive(3) <= NN_2;
n_sro_svcdrive(4) <= NN_2;
n_sro_svcdrive(5) <= NN_2;
n_sro_svcdrive(6) <= NN_2;
n_sro_svcdrive(7) <= NN_2;
n_sro_ce <= NN_2;
end beh;
| mit | 406f3da268368c6ef289df7bafb98218 | 0.542368 | 2.323213 | false | false | false | false |
impedimentToProgress/UCI-BlueChip | AttackFiles/Attacks/privEsc/lib/gaisler/can/can_mod.vhd | 2 | 5,455 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: can_mod
-- File: can_mod.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: OpenCores CAN MAC with FIFO RAM
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
library opencores;
use opencores.cancomp.all;
entity can_mod is
generic (memtech : integer := DEFMEMTECH; syncrst : integer := 0;
ft : integer := 0);
port (
reset : in std_logic;
clk : in std_logic;
cs : in std_logic;
we : in std_logic;
addr : in std_logic_vector(7 downto 0);
data_in : in std_logic_vector(7 downto 0);
data_out: out std_logic_vector(7 downto 0);
irq : out std_logic;
rxi : in std_logic;
txo : out std_logic
);
end;
architecture rtl of can_mod is
-- // port connections for Ram
--//64x8
signal q_dp_64x8 : std_logic_vector(7 downto 0);
signal data_64x8 : std_logic_vector(7 downto 0);
signal wren_64x8 : std_logic;
signal rden_64x8 : std_logic;
signal wraddress_64x8 : std_logic_vector(5 downto 0);
signal rdaddress_64x8 : std_logic_vector(5 downto 0);
--//64x4
signal q_dp_64x4 : std_logic_vector(3 downto 0);
signal data_64x4 : std_logic_vector(3 downto 0);
signal wren_64x4x1 : std_logic;
signal wraddress_64x4x1 : std_logic_vector(5 downto 0);
signal rdaddress_64x4x1 : std_logic_vector(5 downto 0);
--//64x1
signal q_dp_64x1 : std_logic_vector(0 downto 0);
signal data_64x1 : std_logic_vector(0 downto 0);
signal vcc, gnd : std_ulogic;
begin
gnd <= '0'; vcc <= '1';
async : if syncrst = 0 generate
can : can_top port map ( rst => reset, addr => addr, data_in => data_in,
data_out => data_out, cs => cs, we => we, clk_i => clk,
tx_o => txo, rx_i => rxi, bus_off_on => open, irq_on => irq,
clkout_o => open,
q_dp_64x8 => q_dp_64x8, data_64x8 => data_64x8, wren_64x8 => wren_64x8,
rden_64x8 => rden_64x8, wraddress_64x8 => wraddress_64x8,
rdaddress_64x8 => rdaddress_64x8, q_dp_64x4 => q_dp_64x4,
data_64x4 => data_64x4, wren_64x4x1 => wren_64x4x1,
wraddress_64x4x1 => wraddress_64x4x1,
rdaddress_64x4x1 => rdaddress_64x4x1,
q_dp_64x1 => q_dp_64x1(0), data_64x1 => data_64x1(0));
end generate;
sync : if syncrst /= 0 generate
can : can_top_sync port map ( rst => reset, addr => addr, data_in => data_in,
data_out => data_out, cs => cs, we => we, clk_i => clk,
tx_o => txo, rx_i => rxi, bus_off_on => open, irq_on => irq,
clkout_o => open,
q_dp_64x8 => q_dp_64x8, data_64x8 => data_64x8, wren_64x8 => wren_64x8,
rden_64x8 => rden_64x8, wraddress_64x8 => wraddress_64x8,
rdaddress_64x8 => rdaddress_64x8, q_dp_64x4 => q_dp_64x4,
data_64x4 => data_64x4, wren_64x4x1 => wren_64x4x1,
wraddress_64x4x1 => wraddress_64x4x1,
rdaddress_64x4x1 => rdaddress_64x4x1,
q_dp_64x1 => q_dp_64x1(0), data_64x1 => data_64x1(0));
end generate;
noft : if (ft = 0) or (memtech = 0) generate
fifo : syncram_2p generic map(memtech,6,8,0)
port map(rclk => clk, renable => rden_64x8, wclk => clk,
raddress => rdaddress_64x8, waddress => wraddress_64x8,
datain => data_64x8, write => wren_64x8, dataout => q_dp_64x8);
info_fifo : syncram_2p generic map(memtech,6,4,0)
port map(rclk => clk, wclk => clk, raddress => rdaddress_64x4x1,
waddress => wraddress_64x4x1, datain => data_64x4,
write => wren_64x4x1, dataout => q_dp_64x4, renable =>vcc);
end generate;
ften : if not((ft = 0) or (memtech = 0)) generate
fifo : syncram_2pft generic map(memtech,6,8,0,0,2)
port map(rclk => clk, renable => rden_64x8, wclk => clk,
raddress => rdaddress_64x8, waddress => wraddress_64x8,
datain => data_64x8, write => wren_64x8, dataout => q_dp_64x8);
info_fifo : syncram_2pft generic map(memtech,6,4,0,0,2)
port map(rclk => clk, wclk => clk, raddress => rdaddress_64x4x1,
waddress => wraddress_64x4x1, datain => data_64x4,
write => wren_64x4x1, dataout => q_dp_64x4, renable =>vcc);
end generate;
overrun_fifo : syncram_2p generic map(0,6,1,0)
port map(rclk => clk, wclk => clk, raddress => rdaddress_64x4x1,
waddress => wraddress_64x4x1, datain => data_64x1,
write => wren_64x4x1, dataout => q_dp_64x1, renable => vcc);
end;
| mit | 4ed986f0f6a600d59ebd3d0a2db7fbba | 0.60165 | 3.00055 | false | false | false | false |
impedimentToProgress/UCI-BlueChip | AttackFiles/Attacks/privEsc/lib/gaisler/pci/pciahbmst.vhd | 2 | 5,622 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: pciahbmst
-- File: pciahbmst.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: Generic AHB master interface
------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
library gaisler;
use gaisler.misc.all;
entity pciahbmst is
generic (
hindex : integer := 0;
hirq : integer := 0;
venid : integer := VENDOR_GAISLER;
devid : integer := 0;
version : integer := 0;
chprot : integer := 3;
incaddr : integer := 0);
port (
rst : in std_ulogic;
clk : in std_ulogic;
dmai : in ahb_dma_in_type;
dmao : out ahb_dma_out_type;
ahbi : in ahb_mst_in_type;
ahbo : out ahb_mst_out_type
);
end;
architecture rtl of pciahbmst is
constant hconfig : ahb_config_type := (
0 => ahb_device_reg ( venid, devid, 0, version, 0),
others => zero32);
type reg_type is record
start : std_ulogic;
retry : std_ulogic;
grant : std_ulogic;
active : std_ulogic;
end record;
signal r, rin : reg_type;
begin
comb : process(ahbi, dmai, rst, r)
variable v : reg_type;
variable ready : std_ulogic;
variable retry : std_ulogic;
variable mexc : std_ulogic;
variable inc : std_logic_vector(3 downto 0); -- address increment
variable haddr : std_logic_vector(31 downto 0); -- AHB address
variable hwdata : std_logic_vector(31 downto 0); -- AHB write data
variable htrans : std_logic_vector(1 downto 0); -- transfer type
variable hwrite : std_ulogic; -- read/write
variable hburst : std_logic_vector(2 downto 0); -- burst type
variable newaddr : std_logic_vector(10 downto 0); -- next sequential address
variable hbusreq : std_ulogic; -- bus request
variable hprot : std_logic_vector(3 downto 0); -- transfer type
variable xhirq : std_logic_vector(NAHBIRQ-1 downto 0);
variable kblimit : std_logic; -- 1 kB limit indicator
begin
v := r; ready := '0'; mexc := '0'; retry := '0'; inc := (others => '0');
hprot := conv_std_logic_vector(chprot, 4); -- non-cached supervisor data
xhirq := (others => '0'); xhirq(hirq) := dmai.irq; kblimit := '0';
haddr := dmai.address; hbusreq := dmai.start; hwdata := dmai.wdata;
newaddr := dmai.address(10 downto 0);
if INCADDR > 0 then
inc(conv_integer(dmai.size)) := '1';
newaddr := haddr(10 downto 0) + inc;
if (newaddr(10) xor haddr(10)) = '1' then kblimit := '1'; end if;
end if;
-- hburst := HBURST_SINGLE;
if dmai.burst = '0' then hburst := HBURST_SINGLE;
else hburst := HBURST_INCR; end if;
if dmai.start = '1' then
-- hburst := HBURST_INCR;
if (r.active and dmai.burst and not r.retry) = '1' then
haddr(9 downto 0) := newaddr(9 downto 0);
if dmai.busy = '1' then htrans := HTRANS_BUSY;
elsif kblimit = '1' then htrans := HTRANS_IDLE;
else htrans := HTRANS_SEQ; end if;
else htrans := HTRANS_NONSEQ; end if;
else htrans := HTRANS_IDLE; end if;
if r.active = '1' then
if ahbi.hready = '1' then
case ahbi.hresp is
when HRESP_OKAY => ready := '1';
when HRESP_RETRY | HRESP_SPLIT=> retry := '1';
when others => ready := '1'; mexc := '1';
end case;
end if;
if ((ahbi.hresp = HRESP_RETRY) or (ahbi.hresp = HRESP_SPLIT)) then
v.retry := not ahbi.hready;
else v.retry := '0'; end if;
end if;
if r.retry = '1' then htrans := HTRANS_IDLE; end if;
v.start := '0';
if ahbi.hready = '1' then
v.grant := ahbi.hgrant(hindex);
if (htrans = HTRANS_NONSEQ) or (htrans = HTRANS_SEQ) or (htrans = HTRANS_BUSY) then
v.active := r.grant; v.start := r.grant;
else
v.active := '0';
end if;
end if;
if rst = '0' then v.retry := '0'; v.active := '0'; end if;
rin <= v;
ahbo.haddr <= haddr;
ahbo.htrans <= htrans;
ahbo.hbusreq <= hbusreq;
ahbo.hwdata <= dmai.wdata;
ahbo.hconfig <= hconfig;
ahbo.hlock <= '0';
ahbo.hwrite <= dmai.write;
ahbo.hsize <= '0' & dmai.size;
ahbo.hburst <= hburst;
ahbo.hprot <= hprot;
ahbo.hirq <= xhirq;
ahbo.hindex <= hindex;
dmao.start <= r.start;
dmao.active <= r.active;
dmao.ready <= ready;
dmao.mexc <= mexc;
dmao.retry <= retry;
dmao.haddr <= newaddr(9 downto 0);
dmao.rdata <= ahbi.hrdata;
end process;
regs : process(clk)
begin if rising_edge(clk) then r <= rin; end if; end process;
end;
| mit | 0b0a407100cd22eded4ee2ba4968c7c7 | 0.587335 | 3.574062 | false | false | false | false |
lxp32/lxp32-cpu | rtl/lxp32_divider.vhd | 1 | 3,915 | ---------------------------------------------------------------------
-- Divider
--
-- Part of the LXP32 CPU
--
-- Copyright (c) 2016 by Alex I. Kuznetsov
--
-- Based on the NRD (Non Restoring Division) algorithm. Takes
-- 36 cycles to calculate quotient (37 for remainder).
---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity lxp32_divider is
port(
clk_i: in std_logic;
rst_i: in std_logic;
ce_i: in std_logic;
op1_i: in std_logic_vector(31 downto 0);
op2_i: in std_logic_vector(31 downto 0);
signed_i: in std_logic;
rem_i: in std_logic;
ce_o: out std_logic;
result_o: out std_logic_vector(31 downto 0)
);
end entity;
architecture rtl of lxp32_divider is
-- Complementor signals
signal compl_inv: std_logic;
signal compl_mux: std_logic_vector(31 downto 0);
signal compl_out: std_logic_vector(31 downto 0);
signal inv_res: std_logic;
-- Divider FSM signals
signal fsm_ce: std_logic:='0';
signal dividend: unsigned(31 downto 0);
signal divisor: unsigned(32 downto 0);
signal want_remainder: std_logic;
signal partial_remainder: unsigned(32 downto 0);
signal addend: unsigned(32 downto 0);
signal sum: unsigned(32 downto 0);
signal sum_positive: std_logic;
signal sum_subtract: std_logic;
signal cnt: integer range 0 to 34:=0;
signal ceo: std_logic:='0';
-- Output restoration signals
signal remainder_corrector: unsigned(31 downto 0);
signal remainder_corrector_1: std_logic;
signal remainder_pos: unsigned(31 downto 0);
signal result_pos: unsigned(31 downto 0);
begin
compl_inv<=op1_i(31) and signed_i when ce_i='1' else inv_res;
compl_mux<=op1_i when ce_i='1' else std_logic_vector(result_pos);
compl_op1_inst: entity work.lxp32_compl(rtl)
port map(
clk_i=>clk_i,
compl_i=>compl_inv,
d_i=>compl_mux,
d_o=>compl_out
);
process (clk_i) is
begin
if rising_edge(clk_i) then
if rst_i='1' then
fsm_ce<='0';
want_remainder<='-';
inv_res<='-';
else
fsm_ce<=ce_i;
if ce_i='1' then
want_remainder<=rem_i;
if rem_i='1' then
inv_res<=op1_i(31) and signed_i;
else
inv_res<=(op1_i(31) xor op2_i(31)) and signed_i;
end if;
end if;
end if;
end if;
end process;
-- Main adder/subtractor
addend_gen: for i in addend'range generate
addend(i)<=divisor(i) xor sum_subtract;
end generate;
sum<=partial_remainder+addend+(to_unsigned(0,32)&sum_subtract);
sum_positive<=not sum(32);
-- Divider state machine
process (clk_i) is
begin
if rising_edge(clk_i) then
if rst_i='1' then
cnt<=0;
ceo<='0';
divisor<=(others=>'-');
dividend<=(others=>'-');
partial_remainder<=(others=>'-');
sum_subtract<='-';
else
if cnt=1 then
ceo<='1';
else
ceo<='0';
end if;
if ce_i='1' then
divisor(31 downto 0)<=unsigned(op2_i);
divisor(32)<=op2_i(31) and signed_i;
end if;
if fsm_ce='1' then
dividend<=unsigned(compl_out(30 downto 0)&"0");
partial_remainder<=to_unsigned(0,32)&compl_out(31);
sum_subtract<=not divisor(32);
if want_remainder='1' then
cnt<=34;
else
cnt<=33;
end if;
else
partial_remainder<=sum(31 downto 0)÷nd(31);
sum_subtract<=sum_positive xor divisor(32);
dividend<=dividend(30 downto 0)&sum_positive;
if cnt>0 then
cnt<=cnt-1;
end if;
end if;
end if;
end if;
end process;
-- Output restoration circuit
process (clk_i) is
begin
if rising_edge(clk_i) then
for i in remainder_corrector'range loop
remainder_corrector(i)<=(divisor(i) xor divisor(32)) and not sum_positive;
end loop;
remainder_corrector_1<=divisor(32) and not sum_positive;
remainder_pos<=partial_remainder(32 downto 1)+remainder_corrector+
(to_unsigned(0,31)&remainder_corrector_1);
end if;
end process;
result_pos<=remainder_pos when want_remainder='1' else dividend;
result_o<=compl_out;
ce_o<=ceo;
end architecture;
| mit | ea0d978236210aafe8ee0cfa6ff8ffa0 | 0.646999 | 2.863936 | false | false | false | false |
impedimentToProgress/UCI-BlueChip | AttackFiles/Attacks/privEsc/lib/eth/core/eth_rstgen.vhd | 2 | 1,891 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: eth_rstgen
-- File: eth_rstgen.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: Reset generation with glitch filter
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity eth_rstgen is
generic (acthigh : integer := 0);
port (
rstin : in std_ulogic;
clk : in std_ulogic;
clklock : in std_ulogic;
rstout : out std_ulogic;
rstoutraw : out std_ulogic
);
end;
architecture rtl of eth_rstgen is
signal r : std_logic_vector(4 downto 0);
signal rst : std_ulogic;
begin
rst <= not rstin when acthigh = 1 else rstin;
rstoutraw <= rst;
reg1 : process (clk, rst) begin
if rising_edge(clk) then
r <= r(3 downto 0) & clklock;
rstout <= r(4) and r(3) and r(2);
end if;
if rst = '0' then r <= "00000"; rstout <= '0'; end if;
end process;
end;
| mit | f5ad651bc28700a27ee258a11767521e | 0.593337 | 4.049251 | false | false | false | false |
impedimentToProgress/UCI-BlueChip | AttackFiles/Attacks/privEsc/lib/gaisler/leon3/mmutlb.vhd | 2 | 20,680 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: mmutlb
-- File: mmutlb.vhd
-- Author: Konrad Eisele, Jiri Gaisler, Gaisler Research
-- Description: MMU TLB logic
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
library techmap;
use techmap.gencomp.all;
library gaisler;
use gaisler.libiu.all;
use gaisler.libcache.all;
use gaisler.leon3.all;
use gaisler.mmuconfig.all;
use gaisler.mmuiface.all;
use gaisler.libmmu.all;
entity mmutlb is
generic (
tech : integer range 0 to NTECH := 0;
entries : integer range 2 to 32 := 8;
tlb_type : integer range 0 to 3 := 1;
tlb_rep : integer range 0 to 1 := 1
);
port (
rst : in std_logic;
clk : in std_logic;
tlbi : in mmutlb_in_type;
tlbo : out mmutlb_out_type;
two : in mmutw_out_type;
twi : out mmutw_in_type
);
end mmutlb;
architecture rtl of mmutlb is
constant M_TLB_FASTWRITE : integer range 0 to 3 := conv_integer(conv_std_logic_vector(tlb_type,2) and conv_std_logic_vector(2,2)); -- fast writebuffer
constant entries_log : integer := log2(entries);
constant entries_max : std_logic_vector(entries_log-1 downto 0) :=
conv_std_logic_vector(entries-1, entries_log);
type states is (idle, match, walk, pack, flush, sync, diag, dofault);
type tlb_rtype is record
s1_valid : std_logic;
s2_tlbstate : states;
s2_valid : std_logic;
s2_entry : std_logic_vector(entries_log-1 downto 0);
s2_hm : std_logic;
s2_needsync : std_logic;
s2_data : std_logic_vector(31 downto 0);
s2_isid : mmu_idcache;
s2_su : std_logic;
s2_read : std_logic;
s2_flush : std_logic;
walk_use : std_logic;
walk_transdata : mmuidc_data_out_type;
walk_fault : mmutlbfault_out_type;
nrep : std_logic_vector(entries_log-1 downto 0);
tpos : std_logic_vector(entries_log-1 downto 0);
touch : std_logic;
sync_isw : std_logic;
hold : std_logic;
end record;
signal c,r : tlb_rtype;
-- tlb cams
component mmutlbcam
generic (
tlb_type : integer range 0 to 3 := 1
);
port (
rst : in std_logic;
clk : in std_logic;
tlbcami : in mmutlbcam_in_type;
tlbcamo : out mmutlbcam_out_type
);
end component;
signal tlbcami : mmutlbcami_a (M_ENT_MAX-1 downto 0);
signal tlbcamo : mmutlbcamo_a (M_ENT_MAX-1 downto 0);
-- least recently used
component mmulru
generic (
entries : integer := 8
);
port (
clk : in std_logic;
rst : in std_logic;
lrui : in mmulru_in_type;
lruo : out mmulru_out_type
);
end component;
signal lrui : mmulru_in_type;
signal lruo : mmulru_out_type;
-- data-ram syncram signals
signal dr1_addr : std_logic_vector(entries_log-1 downto 0);
signal dr1_datain : std_logic_vector(29 downto 0);
signal dr1_dataout : std_logic_vector(29 downto 0);
signal dr1_enable : std_logic;
signal dr1_write : std_logic;
begin
p0: process (clk, rst, r, c, tlbi, two, tlbcamo, dr1_dataout, lruo)
variable v : tlb_rtype;
variable finish, selstate : std_logic;
variable cam_hitaddr : std_logic_vector(M_ENT_MAX_LOG -1 downto 0);
variable cam_hit_all : std_logic;
variable mtag,ftag : tlbcam_tfp;
-- tlb cam input
variable tlbcam_trans_op : std_logic;
variable tlbcam_write_op : std_logic_vector(entries-1 downto 0);
variable tlbcam_flush_op : std_logic;
-- tw inputs
variable twi_walk_op_ur : std_logic;
variable twi_data : std_logic_vector(31 downto 0);
variable twi_areq_ur : std_logic;
variable twi_aaddr : std_logic_vector(31 downto 0);
variable twi_adata : std_logic_vector(31 downto 0);
variable two_error : std_logic;
-- lru inputs
variable lrui_touch : std_logic;
variable lrui_touchmin : std_logic;
variable lrui_pos : std_logic_vector(entries_log-1 downto 0);
-- syncram inputs
variable dr1write : std_logic;
-- hit tlbcam's output
variable ACC : std_logic_vector(2 downto 0);
variable PTE : std_logic_vector(31 downto 0);
variable LVL : std_logic_vector(1 downto 0);
variable CAC : std_logic;
variable NEEDSYNC : std_logic;
-- wb hit tlbcam's output
variable wb_i_entry : integer range 0 to M_ENT_MAX-1;
variable wb_ACC : std_logic_vector(2 downto 0);
variable wb_PTE : std_logic_vector(31 downto 0);
variable wb_LVL : std_logic_vector(1 downto 0);
variable wb_CAC : std_logic;
variable wb_fault_pro, wb_fault_pri : std_logic;
variable wb_WBNEEDSYNC : std_logic;
variable twACC : std_logic_vector(2 downto 0);
variable tWLVL : std_logic_vector(1 downto 0);
variable twPTE : std_logic_vector(31 downto 0);
variable twNEEDSYNC : std_logic;
variable tlbcam_tagin : tlbcam_tfp;
variable tlbcam_tagwrite : tlbcam_reg;
variable store : std_logic;
variable reppos : std_logic_vector(entries_log-1 downto 0);
variable i_entry : integer range 0 to M_ENT_MAX-1;
variable i_reppos : integer range 0 to M_ENT_MAX-1;
variable fault_pro, fault_pri : std_logic;
variable fault_mexc, fault_trans, fault_inv, fault_access : std_logic;
variable transdata : mmuidc_data_out_type;
variable fault : mmutlbfault_out_type;
variable savewalk : std_logic;
variable tlbo_s1finished : std_logic;
variable wb_transdata : mmuidc_data_out_type;
variable cam_addr : std_logic_vector(31 downto 0);
begin
v := r;
cam_addr := tlbi.transdata.data;
wb_i_entry := 0;
wb_ACC := (others => '0');
wb_PTE := (others => '0');
wb_LVL := (others => '0');
wb_CAC := '0';
wb_fault_pro := '0';
wb_fault_pri := '0';
wb_WBNEEDSYNC := '0';
if (M_TLB_FASTWRITE /= 0) and (tlbi.trans_op = '0') then
cam_addr := tlbi.transdata.wb_data;
end if;
wb_transdata.finish := '0';
wb_transdata.data := (others => '0');
wb_transdata.cache := '0';
wb_transdata.accexc := '0';
finish := '0';
selstate := '0';
cam_hitaddr := (others => '0');
cam_hit_all := '0';
mtag.TYP := (others => '0');
mtag.I1 := (others => '0');
mtag.I2 := (others => '0');
mtag.I3 := (others => '0');
mtag.CTX := (others => '0');
mtag.M := '0';
ftag.TYP := (others => '0');
ftag.I1 := (others => '0');
ftag.I2 := (others => '0');
ftag.I3 := (others => '0');
ftag.CTX := (others => '0');
ftag.M := '0';
tlbcam_trans_op := '0';
tlbcam_write_op := (others => '0');
tlbcam_flush_op := '0';
twi_walk_op_ur := '0';
twi_data := (others => '0');
twi_areq_ur := '0';
twi_aaddr := (others => '0');
twi_adata := (others => '0');
two_error := '0';
lrui_touch:= '0';
lrui_touchmin:= '0';
lrui_pos := (others => '0');
dr1write := '0';
ACC := (others => '0');
PTE := (others => '0');
LVL := (others => '0');
CAC := '0';
NEEDSYNC := '0';
twACC := (others => '0');
tWLVL := (others => '0');
twPTE := (others => '0');
twNEEDSYNC := '0';
tlbcam_tagin.TYP := (others => '0');
tlbcam_tagin.I1 := (others => '0');
tlbcam_tagin.I2 := (others => '0');
tlbcam_tagin.I3 := (others => '0');
tlbcam_tagin.CTX := (others => '0');
tlbcam_tagin.M := '0';
tlbcam_tagwrite.ET := (others => '0');
tlbcam_tagwrite.ACC := (others => '0');
tlbcam_tagwrite.M := '0';
tlbcam_tagwrite.R := '0';
tlbcam_tagwrite.SU := '0';
tlbcam_tagwrite.VALID := '0';
tlbcam_tagwrite.LVL := (others => '0');
tlbcam_tagwrite.I1 := (others => '0');
tlbcam_tagwrite.I2 := (others => '0');
tlbcam_tagwrite.I3 := (others => '0');
tlbcam_tagwrite.CTX := (others => '0');
tlbcam_tagwrite.PPN := (others => '0');
tlbcam_tagwrite.C := '0';
store := '0';
reppos := (others => '0');
fault_pro := '0';
fault_pri := '0';
fault_mexc := '0';
fault_trans := '0';
fault_inv := '0';
fault_access := '0';
transdata.finish := '0';
transdata.data := (others => '0');
transdata.cache := '0';
transdata.accexc := '0';
fault.fault_pro := '0';
fault.fault_pri := '0';
fault.fault_access := '0';
fault.fault_mexc := '0';
fault.fault_trans := '0';
fault.fault_inv := '0';
fault.fault_lvl := (others => '0');
fault.fault_su := '0';
fault.fault_read := '0';
fault.fault_isid := id_dcache;
fault.fault_addr := (others => '0');
savewalk := '0';
tlbo_s1finished := '0';
tlbcam_trans_op := '0'; tlbcam_write_op := (others => '0'); tlbcam_flush_op := '0';
lrui_touch := '0'; lrui_touchmin := '0'; lrui_pos := (others => '0');
dr1write := '0';
fault_pro := '0'; fault_pri := '0'; fault_mexc := '0'; fault_trans := '0'; fault_inv := '0'; fault_access := '0';
twi_walk_op_ur := '0'; twi_areq_ur := '0'; twi_aaddr := dr1_dataout&"00";
finish := '0';
store := '0'; v.hold := '0'; savewalk := '0'; tlbo_s1finished := '0';
selstate := '0';
cam_hitaddr := (others => '0');
cam_hit_all := '0';
NEEDSYNC := '0';
for i in entries-1 downto 0 loop
NEEDSYNC := NEEDSYNC or tlbcamo(i).NEEDSYNC;
if (tlbcamo(i).hit) = '1' then
cam_hitaddr(entries_log-1 downto 0) := cam_hitaddr(entries_log-1 downto 0) or conv_std_logic_vector(i, entries_log);
cam_hit_all := '1';
end if;
end loop;
-- tlbcam write operation
tlbcam_tagwrite := TLB_CreateCamWrite( two.data, r.s2_read, two.lvl, tlbi.mmctrl1.ctx, r.s2_data);
-- replacement position
reppos := (others => '0');
if tlb_rep = 0 then
reppos := lruo.pos(entries_log-1 downto 0);
v.touch := '0';
elsif tlb_rep = 1 then
reppos := r.nrep;
end if;
i_reppos := conv_integer(reppos);
-- tw
two_error := two.fault_mexc or two.fault_trans or two.fault_inv;
twACC := two.data(PTE_ACC_U downto PTE_ACC_D);
twLVL := two.lvl;
twPTE := two.data;
twNEEDSYNC := (not two.data(PTE_R)) or ((not r.s2_read) and (not two.data(PTE_M))); -- tw : writeback on next flush
case r.s2_tlbstate is
when idle =>
if (tlbi.s2valid) = '1' then
if r.s2_flush = '1' then
v.s2_tlbstate := pack;
else
v.walk_fault.fault_pri := '0';
v.walk_fault.fault_pro := '0';
v.walk_fault.fault_access := '0';
v.walk_fault.fault_trans := '0';
v.walk_fault.fault_inv := '0';
v.walk_fault.fault_mexc := '0';
if (r.s2_hm and not tlbi.mmctrl1.tlbdis ) = '1' then
if r.s2_needsync = '1' then
v.s2_tlbstate := sync;
else
finish := '1';
end if;
if tlb_rep = 0 then
v.tpos := r.s2_entry; v.touch := '1'; -- touch lru
end if;
else
v.s2_entry := reppos;
v.s2_tlbstate := walk;
if tlb_rep = 0 then
lrui_touchmin := '1'; -- lru element consumed
end if;
end if;
end if;
end if;
when walk =>
if (two.finish = '1') then
if ( two_error ) = '0' then
tlbcam_write_op := decode(r.s2_entry);
dr1write := '1';
TLB_CheckFault( twACC, r.s2_isid, r.s2_su, r.s2_read, v.walk_fault.fault_pro, v.walk_fault.fault_pri );
end if;
TLB_MergeData( two.lvl , two.data, r.s2_data, v.walk_transdata.data );
v.walk_transdata.cache := two.data(PTE_C);
v.walk_fault.fault_lvl := two.fault_lvl;
v.walk_fault.fault_access := '0';
v.walk_fault.fault_mexc := two.fault_mexc;
v.walk_fault.fault_trans := two.fault_trans;
v.walk_fault.fault_inv := two.fault_inv;
v.walk_use := '1';
if ( twNEEDSYNC = '0' or two_error = '1') then
v.s2_tlbstate := pack;
else
v.s2_tlbstate := sync;
v.sync_isw := '1';
end if;
if tlb_rep = 1 then
if (r.nrep = entries_max) then v.nrep := (others => '0');
else v.nrep := r.nrep + 1;
end if;
end if;
else
twi_walk_op_ur := '1';
end if;
when pack =>
v.s2_flush := '0';
v.walk_use := '0';
finish := '1';
v.s2_tlbstate := idle;
when sync =>
tlbcam_trans_op := '1';
if ( v.sync_isw = '1') then
-- pte address is currently written to syncram, wait one cycle before issuing twi_areq_ur
v.sync_isw := '0';
else
if (two.finish = '1') then
v.s2_tlbstate := pack;
v.walk_fault.fault_mexc := two.fault_mexc;
if (two.fault_mexc) = '1' then
v.walk_use := '1';
end if;
else
twi_areq_ur := '1';
end if;
end if;
when others =>
v .s2_tlbstate := idle;
end case;
if selstate = '1' then
if tlbi.trans_op = '1' then
elsif tlbi.flush_op = '1' then
end if;
end if;
i_entry := conv_integer(r.s2_entry);
ACC := tlbcamo(i_entry).pteout(PTE_ACC_U downto PTE_ACC_D);
PTE := tlbcamo(i_entry).pteout;
LVL := tlbcamo(i_entry).LVL;
CAC := tlbcamo(i_entry).pteout(PTE_C);
transdata.cache := CAC;
--# fault, todo: should we flush on a fault?
TLB_CheckFault( ACC, r.s2_isid, r.s2_su, r.s2_read, fault_pro, fault_pri );
fault.fault_pro := '0';
fault.fault_pri := '0';
fault.fault_access := '0';
fault.fault_mexc := '0';
fault.fault_trans := '0';
fault.fault_inv := '0';
if finish = '1' and (r.s2_flush = '0') then --protect flush path
fault.fault_pro := fault_pro;
fault.fault_pri := fault_pri;
fault.fault_access := fault_access;
fault.fault_mexc := fault_mexc;
fault.fault_trans := fault_trans;
fault.fault_inv := fault_inv;
end if;
if (M_TLB_FASTWRITE /= 0) then
wb_i_entry := conv_integer(cam_hitaddr(entries_log-1 downto 0));
wb_ACC := tlbcamo(wb_i_entry).pteout(PTE_ACC_U downto PTE_ACC_D);
wb_PTE := tlbcamo(wb_i_entry).pteout;
wb_LVL := tlbcamo(wb_i_entry).LVL;
wb_CAC := tlbcamo(wb_i_entry).pteout(PTE_C);
wb_WBNEEDSYNC := tlbcamo(wb_i_entry).WBNEEDSYNC;
wb_transdata.cache := wb_CAC;
TLB_MergeData( wb_LVL, wb_PTE, tlbi.transdata.data, wb_transdata.data );
--# fault, todo: should we flush on a fault?
TLB_CheckFault( wb_ACC, tlbi.transdata.isid, tlbi.transdata.su, tlbi.transdata.read, wb_fault_pro, wb_fault_pri );
wb_transdata.accexc := wb_fault_pro or wb_fault_pri or wb_WBNEEDSYNC or (not cam_hit_all);
end if;
--# merge data
TLB_MergeData( LVL, PTE, r.s2_data, transdata.data );
--# reset
if (rst = '0') then
v.s2_flush := '0';
v.s2_tlbstate := idle;
if tlb_rep = 1 then
v.nrep := (others => '0');
end if;
if tlb_rep = 0 then
v.touch := '0';
end if;
v.sync_isw := '0';
end if;
if (finish = '1') or (tlbi.s2valid = '0') then
tlbo_s1finished := '1';
v.s2_hm := cam_hit_all;
v.s2_entry := cam_hitaddr(entries_log-1 downto 0);
v.s2_needsync := NEEDSYNC;
v.s2_data := tlbi.transdata.data;
v.s2_read := tlbi.transdata.read;
v.s2_su := tlbi.transdata.su;
v.s2_isid := tlbi.transdata.isid;
v.s2_flush := tlbi.flush_op;
end if;
-- translation operation tag
mtag := TLB_CreateCamTrans( cam_addr, tlbi.transdata.read, tlbi.mmctrl1.ctx );
tlbcam_tagin := mtag;
-- flush/(probe) operation tag
ftag := TLB_CreateCamFlush( r.s2_data, tlbi.mmctrl1.ctx );
if (r.s2_flush = '1') then
tlbcam_tagin := ftag;
end if;
if r.walk_use = '1' then
transdata := r.walk_transdata;
fault := r.walk_fault;
end if;
fault.fault_read := r.s2_read;
fault.fault_su := r.s2_su;
fault.fault_isid := r.s2_isid;
fault.fault_addr := r.s2_data;
transdata.finish := finish;
transdata.accexc := '0';
twi_adata := PTE;
--# drive signals
tlbo.wbtransdata <= wb_transdata;
tlbo.transdata <= transdata;
tlbo.fault <= fault;
tlbo.nexttrans <= store;
tlbo.s1finished <= tlbo_s1finished;
tlbo.tlbcamo <= (others => mmutlbcam_out_none);
twi.walk_op_ur <= twi_walk_op_ur;
twi.data <= r.s2_data;
twi.areq_ur <= twi_areq_ur;
twi.adata <= twi_adata;
twi.aaddr <= twi_aaddr;
if tlb_rep = 0 then
lrui.flush <= r.s2_flush;
lrui.touch <= r.touch;
lrui.touchmin <= lrui_touchmin;
lrui.pos <= (others => '0');
lrui.pos(entries_log-1 downto 0) <= r.tpos;
lrui.mmctrl1 <= tlbi.mmctrl1;
end if;
dr1_addr <= r.s2_entry;
dr1_datain <= two.addr(31 downto 2);
dr1_enable <= '1';
dr1_write <= dr1write;
for i in entries-1 downto 0 loop
tlbcami(i).tagin <= tlbcam_tagin;
tlbcami(i).trans_op <= tlbi.trans_op; --tlbcam_trans_op;
tlbcami(i).wb_op <= tlbi.wb_op; --tlbcam_trans_op;
tlbcami(i).flush_op <= r.s2_flush;
tlbcami(i).mmuen <= tlbi.mmctrl1.e;
tlbcami(i).tagwrite <= tlbcam_tagwrite;
tlbcami(i).write_op <= tlbcam_write_op(i);
tlbcami(i).mset <= '0';
end loop; -- i
for i in M_ENT_MAX-1 downto entries loop
tlbcami(i).tagin <= tlbcam_tfp_none;
tlbcami(i).trans_op <= '0';
tlbcami(i).wb_op <= '0';
tlbcami(i).flush_op <= '0';
tlbcami(i).mmuen <= '0';
tlbcami(i).tagwrite <= tlbcam_reg_none;
tlbcami(i).write_op <= '0';
tlbcami(i).mset <= '0';
end loop;
c <= v;
end process p0;
p1: process (clk)
begin if rising_edge(clk) then r <= c; end if;
end process p1;
-- tag-cam tlb entries
tlbcam0: for i in entries-1 downto 0 generate
tag0 : mmutlbcam
generic map ( tlb_type )
port map (rst, clk, tlbcami(i), tlbcamo(i));
end generate tlbcam0;
tlbcamnone: for i in M_ENT_MAX-1 downto entries generate
tlbcamo(i) <= mmutlbcam_out_none;
end generate ;
-- data-ram syncram
dataram : syncram
generic map ( tech => tech, dbits => 30, abits => entries_log)
port map ( clk, dr1_addr, dr1_datain, dr1_dataout, dr1_enable, dr1_write);
-- lru
lru0: if tlb_rep = 0 generate
lru : mmulru
generic map ( entries => entries)
port map ( clk, rst, lrui, lruo );
end generate lru0;
end rtl;
| mit | e7724b93fdb5e6aea7217dfe75a26105 | 0.532157 | 3.315697 | false | false | false | false |
cafe-alpha/wascafe | v13/wasca_10m08scv4k_no_spi_20190420/wasca/synthesis/submodules/abus_slave.vhd | 2 | 30,506 | -- abus_slave.vhd
library IEEE;
use IEEE.numeric_std.all;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity abus_slave is
port (
clock : in std_logic := '0'; -- clock.clk
abus_address : in std_logic_vector(8 downto 0) := (others => '0'); -- abus.address
abus_addressdata : inout std_logic_vector(15 downto 0) := (others => '0'); -- abus.addressdata
abus_chipselect : in std_logic_vector(2 downto 0) := (others => '0'); -- .chipselect
abus_read : in std_logic := '0'; -- .read
abus_write : in std_logic_vector(1 downto 0) := (others => '0'); -- .write
--abus_functioncode : in std_logic_vector(1 downto 0) := (others => '0'); -- .functioncode
--abus_timing : in std_logic_vector(2 downto 0) := (others => '0'); -- .timing
abus_waitrequest : out std_logic := '1'; -- .waitrequest
--abus_addressstrobe : in std_logic := '0'; -- .addressstrobe
abus_interrupt : out std_logic := '0'; -- .interrupt
abus_direction : out std_logic := '0'; -- .direction
abus_muxing : out std_logic_vector(1 downto 0) := "01"; -- .muxing
abus_disable_out : out std_logic := '0'; -- .disableout
avalon_read : out std_logic; -- avalon_master.read
avalon_write : out std_logic; -- .write
avalon_waitrequest : in std_logic := '0'; -- .waitrequest
avalon_address : out std_logic_vector(27 downto 0); -- .address
avalon_readdata : in std_logic_vector(15 downto 0) := (others => '0'); -- .readdata
avalon_writedata : out std_logic_vector(15 downto 0); -- .writedata
avalon_byteenable : out std_logic_vector( 1 downto 0); -- .byteenable
avalon_burstcount : out std_logic; -- .burstcount
avalon_readdatavalid : in std_logic := '0'; -- .readdatavalid
avalon_nios_read : in std_logic := '0'; -- avalon_master.read
avalon_nios_write : in std_logic := '0'; -- .write
avalon_nios_waitrequest : out std_logic := '0'; -- .waitrequest
avalon_nios_address : in std_logic_vector(7 downto 0) := (others => '0'); -- .address
avalon_nios_writedata : in std_logic_vector(15 downto 0) := (others => '0'); -- .writedata
avalon_nios_burstcount : in std_logic; -- .burstcount
avalon_nios_readdata : out std_logic_vector(15 downto 0) := (others => '0'); -- .readdata
avalon_nios_readdatavalid : out std_logic := '0'; -- .readdatavalid
saturn_reset : in std_logic := '0'; -- .saturn_reset
reset : in std_logic := '0' -- reset.reset
);
end entity abus_slave;
architecture rtl of abus_slave is
signal abus_address_ms : std_logic_vector(8 downto 0) := (others => '0'); -- abus.address
signal abus_address_buf : std_logic_vector(8 downto 0) := (others => '0'); -- abus.address
signal abus_addressdata_ms : std_logic_vector(15 downto 0) := (others => '0'); -- .data
signal abus_addressdata_buf : std_logic_vector(15 downto 0) := (others => '0'); -- .data
signal abus_chipselect_ms : std_logic_vector(2 downto 0) := (others => '0'); -- .chipselect
signal abus_chipselect_buf : std_logic_vector(2 downto 0) := (others => '0'); -- .chipselect
signal abus_read_ms : std_logic := '0'; -- .read
signal abus_read_buf : std_logic := '0'; -- .read
signal abus_write_ms : std_logic_vector(1 downto 0) := (others => '0'); -- .write
signal abus_write_buf : std_logic_vector(1 downto 0) := (others => '0'); -- .write
--signal abus_functioncode_ms : std_logic_vector(1 downto 0) := (others => '0'); -- .functioncode
--signal abus_functioncode_buf : std_logic_vector(1 downto 0) := (others => '0'); -- .functioncode
--signal abus_timing_ms : std_logic_vector(2 downto 0) := (others => '0'); -- .timing
--signal abus_timing_buf : std_logic_vector(2 downto 0) := (others => '0'); -- .timing
--signal abus_addressstrobe_ms : std_logic := '0'; -- .addressstrobe
--signal abus_addressstrobe_buf : std_logic := '0'; -- .addressstrobe
signal abus_read_buf2 : std_logic := '0'; -- .read
signal abus_read_buf3 : std_logic := '0'; -- .read
signal abus_read_buf4 : std_logic := '0'; -- .read
signal abus_read_buf5 : std_logic := '0'; -- .read
signal abus_read_buf6 : std_logic := '0'; -- .read
signal abus_read_buf7 : std_logic := '0'; -- .read
signal abus_write_buf2 : std_logic_vector(1 downto 0) := (others => '0'); -- .write
signal abus_chipselect_buf2 : std_logic_vector(2 downto 0) := (others => '0'); -- .chipselect
signal abus_read_pulse : std_logic := '0'; -- .read
signal abus_write_pulse : std_logic_vector(1 downto 0) := (others => '0'); -- .write
signal abus_chipselect_pulse : std_logic_vector(2 downto 0) := (others => '0'); -- .chipselect
signal abus_read_pulse_off : std_logic := '0'; -- .read
signal abus_write_pulse_off : std_logic_vector(1 downto 0) := (others => '0'); -- .write
signal abus_chipselect_pulse_off : std_logic_vector(2 downto 0) := (others => '0'); -- .chipselect
signal abus_anypulse : std_logic := '0';
signal abus_anypulse2 : std_logic := '0';
signal abus_anypulse3 : std_logic := '0';
signal abus_anypulse_off : std_logic := '0';
signal abus_cspulse : std_logic := '0';
signal abus_cspulse2 : std_logic := '0';
signal abus_cspulse3 : std_logic := '0';
signal abus_cspulse4 : std_logic := '0';
signal abus_cspulse5 : std_logic := '0';
signal abus_cspulse6 : std_logic := '0';
signal abus_cspulse7 : std_logic := '0';
signal abus_cspulse_off : std_logic := '0';
signal abus_address_latched : std_logic_vector(23 downto 0) := (others => '0'); -- abus.address
signal abus_chipselect_latched : std_logic_vector(1 downto 0) := (others => '1'); -- abus.address
signal abus_direction_internal : std_logic := '0';
signal abus_muxing_internal : std_logic_vector(1 downto 0) := (others => '0'); -- abus.address
signal abus_data_out : std_logic_vector(15 downto 0) := (others => '0');
signal abus_data_in : std_logic_vector(15 downto 0) := (others => '0');
signal abus_waitrequest_read : std_logic := '0';
signal abus_waitrequest_write : std_logic := '0';
signal abus_waitrequest_read2 : std_logic := '0';
signal abus_waitrequest_write2 : std_logic := '0';
--signal abus_waitrequest_read3 : std_logic := '0';
--signal abus_waitrequest_write3 : std_logic := '0';
--signal abus_waitrequest_read4 : std_logic := '0';
--signal abus_waitrequest_write4 : std_logic := '0';
signal abus_waitrequest_read_off : std_logic := '0';
signal abus_waitrequest_write_off : std_logic := '0';
-- For Rd/Wr access debug
signal rd_access_cntr : std_logic_vector( 7 downto 0) := x"01";
signal wr_access_cntr : std_logic_vector( 7 downto 0) := x"01";
signal last_rd_addr : std_logic_vector(15 downto 0) := x"1230"; -- lower 16 bits only
signal last_wr_addr : std_logic_vector(15 downto 0) := x"1231"; -- lower 16 bits only
signal last_wr_data : std_logic_vector(15 downto 0) := x"5678";
signal REG_PCNTR : std_logic_vector(15 downto 0) := (others => '0');
signal REG_STATUS : std_logic_vector(15 downto 0) := (others => '0');
signal REG_MODE : std_logic_vector(15 downto 0) := (others => '0');
signal REG_HWVER : std_logic_vector(15 downto 0) := X"0002";
signal REG_SWVER : std_logic_vector(15 downto 0) := (others => '0');
TYPE transaction_dir IS (DIR_NONE,DIR_WRITE,DIR_READ);
SIGNAL my_little_transaction_dir : transaction_dir := DIR_NONE;
TYPE wasca_mode_type IS (MODE_INIT,
MODE_POWER_MEMORY_05M, MODE_POWER_MEMORY_1M, MODE_POWER_MEMORY_2M, MODE_POWER_MEMORY_4M,
MODE_RAM_1M, MODE_RAM_4M,
MODE_ROM_KOF95,
MODE_ROM_ULTRAMAN,
MODE_BOOT);
SIGNAL wasca_mode : wasca_mode_type := MODE_INIT;
begin
abus_direction <= abus_direction_internal;
abus_muxing <= not abus_muxing_internal;
--ignoring functioncode, timing and addressstrobe for now
--abus transactions are async, so first we must latch incoming signals
--to get rid of metastability
process (clock)
begin
if rising_edge(clock) then
--1st stage
abus_address_ms <= abus_address;
abus_addressdata_ms <= abus_addressdata;
abus_chipselect_ms <= abus_chipselect; --work only with CS1 for now
abus_read_ms <= abus_read;
abus_write_ms <= abus_write;
--abus_functioncode_ms <= abus_functioncode;
--abus_timing_ms <= abus_timing;
--abus_addressstrobe_ms <= abus_addressstrobe;
--2nd stage
abus_address_buf <= abus_address_ms;
abus_addressdata_buf <= abus_addressdata_ms;
abus_chipselect_buf <= abus_chipselect_ms;
abus_read_buf <= abus_read_ms;
abus_write_buf <= abus_write_ms;
--abus_functioncode_buf <= abus_functioncode_ms;
--abus_timing_buf <= abus_timing_ms;
--abus_addressstrobe_buf <= abus_addressstrobe_ms;
end if;
end process;
--excluding metastability protection is a bad behavior
--but it lloks like we're out of more options to optimize read pipeline
--abus_read_ms <= abus_read;
--abus_read_buf <= abus_read_ms;
--abus read/write latch
process (clock)
begin
if rising_edge(clock) then
abus_write_buf2 <= abus_write_buf;
abus_read_buf2 <= abus_read_buf;
abus_read_buf3 <= abus_read_buf2;
abus_read_buf4 <= abus_read_buf3;
abus_read_buf5 <= abus_read_buf4;
abus_read_buf6 <= abus_read_buf5;
abus_read_buf7 <= abus_read_buf6;
abus_chipselect_buf2 <= abus_chipselect_buf;
abus_anypulse2 <= abus_anypulse;
abus_anypulse3 <= abus_anypulse2;
abus_cspulse2 <= abus_cspulse;
abus_cspulse3 <= abus_cspulse2;
abus_cspulse4 <= abus_cspulse3;
abus_cspulse5 <= abus_cspulse4;
abus_cspulse6 <= abus_cspulse5;
abus_cspulse7 <= abus_cspulse6;
end if;
end process;
--abus write/read pulse is a falling edge since read and write signals are negative polarity
abus_write_pulse <= abus_write_buf2 and not abus_write_buf;
abus_read_pulse <= abus_read_buf2 and not abus_read_buf;
--abus_chipselect_pulse <= abus_chipselect_buf2 and not abus_chipselect_buf;
abus_chipselect_pulse <= abus_chipselect_buf and not abus_chipselect_ms;
abus_write_pulse_off <= abus_write_buf and not abus_write_buf2;
abus_read_pulse_off <= abus_read_buf and not abus_read_buf2;
abus_chipselect_pulse_off <= abus_chipselect_buf and not abus_chipselect_buf2;
abus_anypulse <= abus_write_pulse(0) or abus_write_pulse(1) or abus_read_pulse or
abus_chipselect_pulse(0) or abus_chipselect_pulse(1) or abus_chipselect_pulse(2);
abus_anypulse_off <= abus_write_pulse_off(0) or abus_write_pulse_off(1) or abus_read_pulse_off or
abus_chipselect_pulse_off(0) or abus_chipselect_pulse_off(1) or abus_chipselect_pulse_off(2);
abus_cspulse <= abus_chipselect_pulse(0) or abus_chipselect_pulse(1) or abus_chipselect_pulse(2);
abus_cspulse_off <= abus_chipselect_pulse_off(0) or abus_chipselect_pulse_off(1) or abus_chipselect_pulse_off(2);
--whatever pulse we've got, latch address
--it might be latched twice per transaction, but it's not a problem
--multiplexer was switched to address after previous transaction or after boot,
--so we have address ready to latch
process (clock)
begin
if rising_edge(clock) then
if abus_anypulse = '1' then
--if abus_read_pulse = '1' or abus_write_pulse(0) = '1' or abus_write_pulse(1)='1' then
--Purpose of A0 line in PCB Rev 1.3 is unknown and consequently
--have to be ignored when building address. Instead, address
--top bit is stuffed with '0'.
--Address Mapping for U4 : And for U1 : (In PCB Rev 1.3)
-- A13 -> MUX12 A0 -> MUX0
-- A6 -> MUX13 A9 -> MUX1
-- A5 -> MUX14 A10 -> MUX2
-- A4 -> MUX15 A8 -> MUX3
-- A3 -> MUX4 A7 -> MUX8
-- A2 -> MUX5 A12 -> MUX9
-- A1 -> MUX6 A11 -> MUX10
-- DMY -> MUX7 A14 -> MUX11
--Which gives the following order for de-shuffling address :
-- A14 -> MUX11
-- A13 -> MUX12
-- A12 -> MUX9
-- A11 -> MUX10
-- A10 -> MUX2
-- A9 -> MUX1
-- A8 -> MUX3
-- A7 -> MUX8
-- A6 -> MUX13
-- A5 -> MUX14
-- A4 -> MUX15
-- A3 -> MUX4
-- A2 -> MUX5
-- A1 -> MUX6
-- A0 -> MUX0
abus_address_latched <= abus_address
& abus_addressdata_buf(11) -- A14
& abus_addressdata_buf(12) -- A13
& abus_addressdata_buf( 9) -- A12
& abus_addressdata_buf(10) -- A11
& abus_addressdata_buf( 2) -- A10
& abus_addressdata_buf( 1) -- A9
& abus_addressdata_buf( 3) -- A8
& abus_addressdata_buf( 8) -- A7
& abus_addressdata_buf(13) -- A6
& abus_addressdata_buf(14) -- A5
& abus_addressdata_buf(15) -- A4
& abus_addressdata_buf( 4) -- A3
& abus_addressdata_buf( 5) -- A2
& abus_addressdata_buf( 6) -- A1
& abus_addressdata_buf( 0); -- A0
-- Old de-shuffling logic used in PCB v1.0/v1.1, kept in case of :
-- abus_address_latched <= abus_address & abus_addressdata_buf(0) & abus_addressdata_buf(12) & abus_addressdata_buf(2) & abus_addressdata_buf(1)
-- & abus_addressdata_buf(9) & abus_addressdata_buf(10) & abus_addressdata_buf(8) & abus_addressdata_buf(3)
-- & abus_addressdata_buf(13) & abus_addressdata_buf(14) & abus_addressdata_buf(15) & abus_addressdata_buf(4)
-- & abus_addressdata_buf(5) & abus_addressdata_buf(6) & abus_addressdata_buf(11) & abus_addressdata_buf(7);
end if;
end if;
end process;
--latch transaction direction
process (clock)
begin
if rising_edge(clock) then
if abus_write_pulse(0) = '1' or abus_write_pulse(1) = '1' then
my_little_transaction_dir <= DIR_WRITE;
elsif abus_read_pulse = '1' then
my_little_transaction_dir <= DIR_READ;
elsif abus_anypulse_off = '1' and abus_cspulse_off = '0' then --ending anything but not cs
my_little_transaction_dir <= DIR_NONE;
end if;
end if;
end process;
--latch chipselect number
process (clock)
begin
if rising_edge(clock) then
if abus_chipselect_pulse(0) = '1' then
abus_chipselect_latched <= "00";
elsif abus_chipselect_pulse(1) = '1' then
abus_chipselect_latched <= "01";
elsif abus_chipselect_pulse(2) = '1' then
abus_chipselect_latched <= "10";
elsif abus_cspulse_off = '1' then
abus_chipselect_latched <= "11";
end if;
end if;
end process;
--if valid transaction captured, switch to corresponding multiplex mode
process (clock)
begin
if rising_edge(clock) then
if abus_chipselect_latched = "11" then
--chipselect deasserted
abus_direction_internal <= '0'; --high-z
abus_muxing_internal <= "01"; --address
else
--chipselect asserted
case (my_little_transaction_dir) is
when DIR_NONE =>
abus_direction_internal <= '0'; --high-z
abus_muxing_internal <= "10"; --data
when DIR_READ =>
abus_direction_internal <= '1'; --active
abus_muxing_internal <= "10"; --data
when DIR_WRITE =>
abus_direction_internal <= '0'; --high-z
abus_muxing_internal <= "10"; --data
end case;
end if;
end if;
end process;
abus_disable_out <= '1' when abus_chipselect_latched(1) = '1' else
'0';
--if abus read access is detected, issue avalon read transaction
--wait until readdatavalid, then disable read and abus wait
process (clock)
begin
if rising_edge(clock) then
--if my_little_transaction_dir = DIR_READ and abus_chipselect_latched(1) = '0' and abus_anypulse2 = '1' then
--starting read transaction at either RD pulse or (CS pulse while RD is on)
--but if CS arrives less than 7 clocks after RD, then we ignore this CS
--this will get us 2 additional clocks at read pipeline
if abus_read_pulse = '1' or (abus_cspulse='1' and abus_read_buf = '0' and abus_read_buf7 = '0') then
avalon_read <= '1';
abus_waitrequest_read <= '1';
elsif avalon_readdatavalid = '1' then
-- Debug stuff around Rd/Wr access
rd_access_cntr <= rd_access_cntr + x"01";
last_rd_addr <= abus_address_latched(15 downto 0);
avalon_read <= '0';
abus_waitrequest_read <= '0';
if abus_chipselect_latched = "00" then
--CS0 access
if abus_address_latched(23 downto 0) = X"FF0FFE" then
--wasca specific SD card control register
abus_data_out <= X"CDCD";
elsif abus_address_latched(23 downto 0) = X"FFFFF0" then -- 0x23FFFFE0
abus_data_out <= X"FFFF"; -- Test for cartridge assembly
elsif abus_address_latched(23 downto 0) = X"FFFFF1" then -- 0x23FFFFE2
abus_data_out <= X"0000"; -- Test for cartridge assembly
elsif abus_address_latched(23 downto 0) = X"FFFFF2" then -- 0x23FFFFE4
abus_data_out <= X"A5A5"; -- Test for cartridge assembly
elsif abus_address_latched(23 downto 0) = X"FFFFF3" then -- 0x23FFFFE6
abus_data_out <= X"5A5A"; -- Test for cartridge assembly
elsif abus_address_latched(23 downto 0) = X"FFFFF4" then -- 0x23FFFFE8
abus_data_out <= x"CA" & rd_access_cntr;
elsif abus_address_latched(23 downto 0) = X"FFFFF5" then -- 0x23FFFFEA
abus_data_out <= x"AC" & rd_access_cntr;
elsif abus_address_latched(23 downto 0) = X"FFFFF6" then -- 0x23FFFFEC
abus_data_out <= x"FE" & wr_access_cntr;
elsif abus_address_latched(23 downto 0) = X"FFFFF7" then -- 0x23FFFFEE
abus_data_out <= x"EF" & wr_access_cntr;
elsif abus_address_latched(23 downto 0) = X"FFFFF8" then -- 0x23FFFFF0
--wasca prepare counter
abus_data_out <= REG_PCNTR;
elsif abus_address_latched(23 downto 0) = X"FFFFF9" then -- 0x23FFFFF2
--wasca status register
abus_data_out <= REG_STATUS;
elsif abus_address_latched(23 downto 0) = X"FFFFFA" then -- 0x23FFFFF4
--wasca mode register
abus_data_out <= REG_MODE;
elsif abus_address_latched(23 downto 0) = X"FFFFFB" then -- 0x23FFFFF6
--wasca hwver register
abus_data_out <= REG_HWVER;
elsif abus_address_latched(23 downto 0) = X"FFFFFC" then -- 0x23FFFFF8
--wasca swver register
abus_data_out <= REG_SWVER;
elsif abus_address_latched(23 downto 0) = X"FFFFFD" then -- 0x23FFFFFA
--wasca signature "wa"
abus_data_out <= X"7761";
elsif abus_address_latched(23 downto 0) = X"FFFFFE" then
--wasca signature "sc"
abus_data_out <= X"7363";
elsif abus_address_latched(23 downto 0) = X"FFFFFF" then
--wasca signature "a "
abus_data_out <= X"6120";
else
--normal CS0 read access
case wasca_mode is
when MODE_INIT => abus_data_out <= avalon_readdata(7 downto 0) & avalon_readdata (15 downto 8) ;
when MODE_POWER_MEMORY_05M => abus_data_out <= X"FFFF";
when MODE_POWER_MEMORY_1M => abus_data_out <= X"FFFF";
when MODE_POWER_MEMORY_2M => abus_data_out <= X"FFFF";
when MODE_POWER_MEMORY_4M => abus_data_out <= X"FFFF";
when MODE_RAM_1M => abus_data_out <= avalon_readdata(7 downto 0) & avalon_readdata (15 downto 8) ;
when MODE_RAM_4M => abus_data_out <= avalon_readdata(7 downto 0) & avalon_readdata (15 downto 8) ;
when MODE_ROM_KOF95 => abus_data_out <= avalon_readdata(7 downto 0) & avalon_readdata (15 downto 8) ;
when MODE_ROM_ULTRAMAN => abus_data_out <= avalon_readdata(7 downto 0) & avalon_readdata (15 downto 8) ;
when MODE_BOOT => abus_data_out <= avalon_readdata(7 downto 0) & avalon_readdata (15 downto 8) ;
end case;
end if;
elsif abus_chipselect_latched = "01" then
--CS1 access
if ( abus_address_latched(23 downto 0) = X"FFFFFF" or abus_address_latched(23 downto 0) = X"FFFFFD" ) then
--saturn cart id register
case wasca_mode is
when MODE_INIT => abus_data_out <= avalon_readdata(7 downto 0) & avalon_readdata (15 downto 8) ;
when MODE_POWER_MEMORY_05M => abus_data_out <= X"FF21";
when MODE_POWER_MEMORY_1M => abus_data_out <= X"FF22";
when MODE_POWER_MEMORY_2M => abus_data_out <= X"FF23";
when MODE_POWER_MEMORY_4M => abus_data_out <= X"FF24";
when MODE_RAM_1M => abus_data_out <= X"FF5A";
when MODE_RAM_4M => abus_data_out <= X"FF5C";
when MODE_ROM_KOF95 => abus_data_out <= X"FFFF";
when MODE_ROM_ULTRAMAN => abus_data_out <= X"FFFF";
when MODE_BOOT => abus_data_out <= X"FFFF";
end case;
else
--normal CS1 access
case wasca_mode is
-- [DEBUG]Show which address is being accessed,
-- [DEBUG]in order to verify multiplexer wiring.
when MODE_INIT => abus_data_out <= abus_address_latched(15 downto 0);
-- Initial logic, which should be restored someday ...
--when MODE_INIT => abus_data_out <= avalon_readdata(7 downto 0) & avalon_readdata (15 downto 8) ;
when MODE_POWER_MEMORY_05M => abus_data_out <= avalon_readdata(7 downto 0) & avalon_readdata (15 downto 8) ;
when MODE_POWER_MEMORY_1M => abus_data_out <= avalon_readdata(7 downto 0) & avalon_readdata (15 downto 8) ;
when MODE_POWER_MEMORY_2M => abus_data_out <= avalon_readdata(7 downto 0) & avalon_readdata (15 downto 8) ;
when MODE_POWER_MEMORY_4M => abus_data_out <= avalon_readdata(7 downto 0) & avalon_readdata (15 downto 8) ;
when MODE_RAM_1M => abus_data_out <= X"FFFF";
when MODE_RAM_4M => abus_data_out <= X"FFFF";
when MODE_ROM_KOF95 => abus_data_out <= X"FFFF";
when MODE_ROM_ULTRAMAN => abus_data_out <= X"FFFF";
when MODE_BOOT => abus_data_out <= X"FFFF";
end case;
end if;
else
--CS2 access
abus_data_out <= X"EEEE";
end if;
end if;
end if;
end process;
--if abus write access is detected, issue avalon write transaction
--disable abus wait immediately
--TODO: check if avalon_writedata is already valid at this moment
process (clock)
begin
if rising_edge(clock) then
if my_little_transaction_dir = DIR_WRITE and abus_chipselect_latched /= "11" and abus_cspulse7 = '1' then
--pass write to avalon
avalon_write <= '1';
abus_waitrequest_write <= '1';
elsif avalon_waitrequest = '0' then
avalon_write <= '0';
abus_waitrequest_write <= '0';
end if;
end if;
end process;
--wasca mode register write
--reset
process (clock)
begin
if rising_edge(clock) then
--if saturn_reset='0' then wasca_mode <= MODE_INIT;
--els
-- Debug stuff around Rd/Wr access
if my_little_transaction_dir = DIR_WRITE and abus_chipselect_latched = "00" and abus_cspulse7 = '1' then
wr_access_cntr <= wr_access_cntr + x"01";
last_wr_addr <= abus_address_latched(15 downto 0);
last_wr_data <= abus_data_in;
end if;
if my_little_transaction_dir = DIR_WRITE and abus_chipselect_latched = "00" and abus_cspulse7 = '1' and
abus_address_latched(23 downto 0) = X"FFFFFA" then -- 0x23FFFFF4
--wasca mode register
REG_MODE <= abus_data_in;
case (abus_data_in (3 downto 0)) is
when X"1" => wasca_mode <= MODE_POWER_MEMORY_05M;
when X"2" => wasca_mode <= MODE_POWER_MEMORY_1M;
when X"3" => wasca_mode <= MODE_POWER_MEMORY_2M;
when X"4" => wasca_mode <= MODE_POWER_MEMORY_4M;
when others =>
case (abus_data_in (7 downto 4)) is
when X"1" => wasca_mode <= MODE_RAM_1M;
when X"2" => wasca_mode <= MODE_RAM_4M;
when others =>
case (abus_data_in (11 downto 8)) is
when X"1" => wasca_mode <= MODE_ROM_KOF95;
when X"2" => wasca_mode <= MODE_ROM_ULTRAMAN;
when others => null;-- wasca_mode <= MODE_INIT;
end case;
end case;
end case;
end if;
end if;
end process;
abus_data_in <= abus_addressdata_buf;
--working only if direction is 1
abus_addressdata <= (others => 'Z') when abus_direction_internal='0' else
abus_data_out;
process (clock)
begin
if rising_edge(clock) then
abus_waitrequest_read2 <= abus_waitrequest_read;
--abus_waitrequest_read3 <= abus_waitrequest_read2;
--abus_waitrequest_read4 <= abus_waitrequest_read3;
abus_waitrequest_write2 <= abus_waitrequest_write;
--abus_waitrequest_write3 <= abus_waitrequest_write3;
--abus_waitrequest_write4 <= abus_waitrequest_write4;
end if;
end process;
process (clock)
begin
if rising_edge(clock) then
abus_waitrequest_read_off <= '0';
abus_waitrequest_write_off <= '0';
if abus_waitrequest_read = '0' and abus_waitrequest_read2 = '1' then
abus_waitrequest_read_off <= '1';
end if;
if abus_waitrequest_write = '0' and abus_waitrequest_write2 = '1' then
abus_waitrequest_write_off <= '1';
end if;
end if;
end process;
--process (clock)
--begin
-- if rising_edge(clock) then
-- --if abus_read_pulse='1' or abus_write_pulse(0)='1' or abus_write_pulse(1)='1' then
-- --if abus_anypulse = '1' then
-- if abus_chipselect_pulse(0) = '1' or abus_chipselect_pulse(1) = '1' then
-- abus_waitrequest <= '0';
-- elsif abus_waitrequest_read_off='1' or abus_waitrequest_write_off='1' then
-- abus_waitrequest <= '1';
-- end if;
-- end if;
--end process;
--avalon-to-abus mapping
--SDRAM is mapped to both CS0 and CS1
--
-- Note about address : from NIOS side, SDRAM is mapped to 0x0400_0000,
-- | so that the prefix at upper bits of the address passed to avalon.
-- | And A-Bus data width is 16 bits so that lower address bit is zeroed.
avalon_address <= "010" & abus_address_latched(23 downto 0) & "0";
avalon_writedata <= abus_data_in(7 downto 0) & abus_data_in (15 downto 8) ;
avalon_burstcount <= '0';
-- Specify which byte(s) should be written.
avalon_byteenable(0) <= not (abus_read_ms or abus_write_ms(1));
avalon_byteenable(1) <= not (abus_read_ms or abus_write_ms(0));
abus_waitrequest <= not (abus_waitrequest_read or abus_waitrequest_write);
--Nios II read interface
process (clock)
begin
if rising_edge(clock) then
avalon_nios_readdatavalid <= '0';
if avalon_nios_read = '1' then
avalon_nios_readdatavalid <= '1';
case avalon_nios_address is
-- Debug stuff around Rd/Wr access
when X"E0" =>
avalon_nios_readdata <= x"CA" & rd_access_cntr;
when X"E2" =>
avalon_nios_readdata <= x"FE" & wr_access_cntr;
when X"E4" =>
avalon_nios_readdata <= last_rd_addr;
when X"E6" =>
avalon_nios_readdata <= last_wr_addr;
when X"E8" =>
avalon_nios_readdata <= last_wr_data;
when X"F0" =>
avalon_nios_readdata <= REG_PCNTR;
when X"F2" =>
avalon_nios_readdata <= REG_STATUS;
when X"F4" =>
avalon_nios_readdata <= REG_MODE;
when X"F6" =>
avalon_nios_readdata <= REG_HWVER;
when X"F8" =>
avalon_nios_readdata <= REG_SWVER;
when X"FA" =>
avalon_nios_readdata <= X"ABCD"; --for debug, remove later
when others =>
avalon_nios_readdata <= REG_HWVER; --to simplify mux
end case;
end if;
end if;
end process;
--Nios II write interface
process (clock)
begin
if rising_edge(clock) then
if avalon_nios_write= '1' then
case avalon_nios_address is
when X"F0" =>
REG_PCNTR <= avalon_nios_writedata;
when X"F2" =>
REG_STATUS <= avalon_nios_writedata;
when X"F4" =>
null;
when X"F6" =>
null;
when X"F8" =>
REG_SWVER <= avalon_nios_writedata;
when others =>
null;
end case;
end if;
end if;
end process;
--Nios system interface is only regs, so always ready to write.
avalon_nios_waitrequest <= '0';
end architecture rtl; -- of abus_slave
| gpl-2.0 | c836c3592581220adf8a0ebcdf2a3e27 | 0.568478 | 3.302587 | false | false | false | false |
lxp32/lxp32-cpu | rtl/lxp32_interrupt_mux.vhd | 1 | 3,035 | ---------------------------------------------------------------------
-- Interrupt multiplexer
--
-- Part of the LXP32 CPU
--
-- Copyright (c) 2016 by Alex I. Kuznetsov
--
-- Manages LXP32 interrupts. Interrupts with lower numbers have
-- higher priority.
---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity lxp32_interrupt_mux is
port(
clk_i: in std_logic;
rst_i: in std_logic;
irq_i: in std_logic_vector(7 downto 0);
interrupt_valid_o: out std_logic;
interrupt_vector_o: out std_logic_vector(2 downto 0);
interrupt_ready_i: in std_logic;
interrupt_return_i: in std_logic;
wakeup_o: out std_logic;
sp_waddr_i: in std_logic_vector(7 downto 0);
sp_we_i: in std_logic;
sp_wdata_i: in std_logic_vector(31 downto 0)
);
end entity;
architecture rtl of lxp32_interrupt_mux is
signal irq_reg: std_logic_vector(irq_i'range):=(others=>'0');
type state_type is (Ready,Requested,WaitForExit);
signal state: state_type:=Ready;
signal pending_interrupts: std_logic_vector(irq_i'range):=(others=>'0');
signal interrupt_valid: std_logic:='0';
signal interrupts_enabled: std_logic_vector(7 downto 0):=(others=>'0');
signal interrupts_wakeup: std_logic_vector(7 downto 0):=(others=>'0');
begin
-- Note: "disabled" interrupts (i.e. for which interrupts_enabled_i(i)='0')
-- are ignored completely, meaning that the interrupt handler won't be
-- called even if the interrupt is enabled later.
process (clk_i) is
begin
if rising_edge(clk_i) then
if rst_i='1' then
irq_reg<=(others=>'0');
pending_interrupts<=(others=>'0');
state<=Ready;
interrupt_valid<='0';
interrupt_vector_o<=(others=>'-');
wakeup_o<='0';
else
irq_reg<=irq_i;
pending_interrupts<=(pending_interrupts or
(irq_i and not irq_reg)) and
interrupts_enabled and not interrupts_wakeup;
case state is
when Ready =>
for i in pending_interrupts'reverse_range loop -- lower interrupts have priority
if pending_interrupts(i)='1' then
pending_interrupts(i)<='0';
interrupt_valid<='1';
interrupt_vector_o<=std_logic_vector(to_unsigned(i,3));
state<=Requested;
exit;
end if;
end loop;
when Requested =>
if interrupt_ready_i='1' then
interrupt_valid<='0';
state<=WaitForExit;
end if;
when WaitForExit =>
if interrupt_return_i='1' then
state<=Ready;
end if;
end case;
if (irq_i and (not irq_reg) and interrupts_enabled and interrupts_wakeup)/=X"00" then
wakeup_o<='1';
else
wakeup_o<='0';
end if;
end if;
end if;
end process;
interrupt_valid_o<=interrupt_valid;
process (clk_i) is
begin
if rising_edge(clk_i) then
if rst_i='1' then
interrupts_enabled<=(others=>'0');
interrupts_wakeup<=(others=>'0');
elsif sp_we_i='1' and sp_waddr_i=X"FC" then
interrupts_enabled<=sp_wdata_i(7 downto 0);
interrupts_wakeup<=sp_wdata_i(15 downto 8);
end if;
end if;
end process;
end architecture;
| mit | 9f3e89194fc344594b7dd87ed18d4603 | 0.637891 | 3.138573 | false | false | false | false |
impedimentToProgress/UCI-BlueChip | AttackFiles/Attacks/privEsc/lib/gaisler/ddr/ddrsp64a.vhd | 2 | 26,297 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: ddrsp64a
-- File: ddrsp64a.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: 64-bit DDR266 memory controller with asych AHB interface
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
library gaisler;
use grlib.devices.all;
use gaisler.memctrl.all;
library techmap;
use techmap.gencomp.all;
entity ddrsp64a is
generic (
memtech : integer := 0;
hindex : integer := 0;
haddr : integer := 0;
hmask : integer := 16#f00#;
ioaddr : integer := 16#000#;
iomask : integer := 16#fff#;
MHz : integer := 100;
col : integer := 9;
Mbyte : integer := 8;
fast : integer := 0;
pwron : integer := 0;
oepol : integer := 0
);
port (
rst : in std_ulogic;
clk_ddr : in std_ulogic;
clk_ahb : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
sdi : in sdctrl_in_type;
sdo : out sdctrl_out_type
);
end;
architecture rtl of ddrsp64a is
constant REVISION : integer := 0;
constant CMD_PRE : std_logic_vector(2 downto 0) := "010";
constant CMD_REF : std_logic_vector(2 downto 0) := "100";
constant CMD_LMR : std_logic_vector(2 downto 0) := "110";
constant CMD_EMR : std_logic_vector(2 downto 0) := "111";
constant abuf : integer := 6;
constant hconfig : ahb_config_type := (
0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_DDRSP, 0, REVISION, 0),
4 => ahb_membar(haddr, '1', '1', hmask),
5 => ahb_iobar(ioaddr, iomask),
others => zero32);
type mcycletype is (midle, active, ext, leadout);
type ahb_state_type is (midle, rhold, dread, dwrite, whold1, whold2);
type sdcycletype is (act1, act2, act3, rd1, rd2, rd3, rd4, rd5, rd6, rd7, rd8,
wr1, wr2, wr3, wr4a, wr4, wr5, sidle, ioreg1, ioreg2);
type icycletype is (iidle, pre, ref1, ref2, emode, lmode, finish);
-- sdram configuration register
type sdram_cfg_type is record
command : std_logic_vector(2 downto 0);
csize : std_logic_vector(1 downto 0);
bsize : std_logic_vector(2 downto 0);
trcd : std_ulogic; -- tCD : 2/3 clock cycles
trfc : std_logic_vector(2 downto 0);
trp : std_ulogic; -- precharge to activate: 2/3 clock cycles
refresh : std_logic_vector(11 downto 0);
renable : std_ulogic;
dllrst : std_ulogic;
refon : std_ulogic;
cke : std_ulogic;
end record;
type access_param is record
haddr : std_logic_vector(31 downto 0);
size : std_logic_vector(1 downto 0);
hwrite : std_ulogic;
hio : std_ulogic;
end record;
-- local registers
type ahb_reg_type is record
hready : std_ulogic;
hsel : std_ulogic;
hio : std_ulogic;
startsd : std_ulogic;
ready : std_ulogic;
ready2 : std_ulogic;
write : std_logic_vector(3 downto 0);
state : ahb_state_type;
haddr : std_logic_vector(31 downto 0);
hrdata : std_logic_vector(31 downto 0);
hwdata : std_logic_vector(31 downto 0);
hwrite : std_ulogic;
htrans : std_logic_vector(1 downto 0);
hresp : std_logic_vector(1 downto 0);
raddr : std_logic_vector(abuf-1 downto 0);
size : std_logic_vector(1 downto 0);
acc : access_param;
end record;
type ddr_reg_type is record
startsd : std_ulogic;
startsdold : std_ulogic;
burst : std_ulogic;
hready : std_ulogic;
bdrive : std_ulogic;
qdrive : std_ulogic;
nbdrive : std_ulogic;
mstate : mcycletype;
sdstate : sdcycletype;
cmstate : mcycletype;
istate : icycletype;
trfc : std_logic_vector(2 downto 0);
refresh : std_logic_vector(11 downto 0);
sdcsn : std_logic_vector(1 downto 0);
sdwen : std_ulogic;
rasn : std_ulogic;
casn : std_ulogic;
dqm : std_logic_vector(15 downto 0);
address : std_logic_vector(15 downto 2); -- memory address
ba : std_logic_vector( 1 downto 0);
waddr : std_logic_vector(abuf-1 downto 0);
cfg : sdram_cfg_type;
hrdata : std_logic_vector(127 downto 0);
end record;
signal vcc : std_ulogic;
signal r, ri : ddr_reg_type;
signal ra, rai : ahb_reg_type;
signal rbdrive, ribdrive : std_logic_vector(31 downto 0);
signal rdata, wdata : std_logic_vector(127 downto 0);
attribute syn_preserve : boolean;
attribute syn_preserve of rbdrive : signal is true;
begin
vcc <= '1';
ahb_ctrl : process(rst, ahbsi, r, ra, rdata)
variable v : ahb_reg_type; -- local variables for registers
variable startsd : std_ulogic;
variable dout : std_logic_vector(31 downto 0);
begin
v := ra; v.hresp := HRESP_OKAY; v.write := "0000";
case ra.raddr(1 downto 0) is
when "00" => v.hrdata := rdata(127 downto 96);
when "01" => v.hrdata := rdata(95 downto 64);
when "10" => v.hrdata := rdata(63 downto 32);
when others => v.hrdata := rdata(31 downto 0);
end case;
v.ready := not (ra.startsd xor r.startsdold);
v.ready2 := ra.ready;
if ((ahbsi.hready and ahbsi.hsel(hindex)) = '1') then
v.htrans := ahbsi.htrans; v.haddr := ahbsi.haddr;
v.size := ahbsi.hsize(1 downto 0); v.hwrite := ahbsi.hwrite;
if ahbsi.htrans(1) = '1' then
v.hio := ahbsi.hmbsel(1);
v.hsel := '1'; v.hready := '0';
end if;
end if;
if ahbsi.hready = '1' then v.hsel := ahbsi.hsel(hindex); end if;
-- if (ra.hsel and ra.hio and not ra.hready) = '1' then v.hready := '1'; end if;
case ra.state is
when midle =>
if ((v.hsel and v.htrans(1)) = '1') then
if v.hwrite = '0' then
v.state := rhold; v.startsd := not ra.startsd;
else
v.state := dwrite; v.hready := '1';
-- v.write(0) := not v.haddr(2); v.write(1) := v.haddr(2);
v.write := decode(v.haddr(3 downto 2));
end if;
end if;
v.raddr := ra.haddr(7 downto 2);
v.ready := '0'; v.ready2 := '0';
-- if not ((ra.hsel and ra.htrans(1) and not ra.htrans(0)) = '1') then
if ahbsi.hready = '1' then
v.acc := (v.haddr, v.size, v.hwrite, v.hio);
end if;
when rhold =>
v.raddr := ra.haddr(7 downto 2);
if ra.ready2 = '1' then
v.state := dread; v.hready := '1'; v.raddr := ra.raddr + 1;
end if;
when dread =>
v.raddr := ra.raddr + 1; v.hready := '1';
if ((v.hsel and v.htrans(1) and v.htrans(0)) = '0') or
(ra.raddr(2 downto 0) = "000")
then v.state := midle; v.hready := '0'; end if;
v.acc := (v.haddr, v.size, v.hwrite, v.hio);
when dwrite =>
v.raddr := ra.haddr(7 downto 2); v.hready := '1';
-- v.write(0) := not v.haddr(2); v.write(1) := v.haddr(2);
v.write := decode(v.haddr(3 downto 2));
if ((v.hsel and v.htrans(1) and v.htrans(0)) = '0') or
(ra.haddr(4 downto 2) = "111")
then
v.startsd := not ra.startsd; v.state := whold1;
v.write := "0000"; v.hready := '0';
end if;
when whold1 =>
v.state := whold2; v.ready := '0';
when whold2 =>
if ra.ready = '1' then
v.state := midle; v.acc := (v.haddr, v.size, v.hwrite, v.hio);
end if;
end case;
v.hwdata := ahbsi.hwdata;
if (ahbsi.hready and ahbsi.hsel(hindex) ) = '1' then
if ahbsi.htrans(1) = '0' then v.hready := '1'; end if;
end if;
dout := ra.hrdata(31 downto 0);
if rst = '0' then
v.hsel := '0';
v.hready := '1';
v.state := midle;
v.startsd := '0';
v.hio := '0';
end if;
rai <= v;
ahbso.hready <= ra.hready;
ahbso.hresp <= ra.hresp;
ahbso.hrdata <= dout;
ahbso.hcache <= not ra.hio;
end process;
ddr_ctrl : process(rst, r, ra, sdi, rbdrive, wdata)
variable v : ddr_reg_type; -- local variables for registers
variable startsd : std_ulogic;
variable dqm : std_logic_vector(15 downto 0);
variable raddr : std_logic_vector(13 downto 0);
variable adec : std_ulogic;
variable rams : std_logic_vector(1 downto 0);
variable ba : std_logic_vector(1 downto 0);
variable haddr : std_logic_vector(31 downto 0);
variable hsize : std_logic_vector(1 downto 0);
variable hwrite : std_ulogic;
variable htrans : std_logic_vector(1 downto 0);
variable hready : std_ulogic;
variable vbdrive : std_logic_vector(31 downto 0);
variable bdrive : std_ulogic;
variable writecfg: std_ulogic;
variable regsd1 : std_logic_vector(31 downto 0); -- data from registers
variable regsd2 : std_logic_vector(31 downto 0); -- data from registers
begin
-- Variable default settings to avoid latches
v := r; v.hready := '0'; writecfg := '0'; vbdrive := rbdrive;
v.hrdata := sdi.data; v.qdrive :='0';
regsd1 := (others => '0');
regsd1(31 downto 15) := r.cfg.refon & r.cfg.trp & r.cfg.trfc &
r.cfg.trcd & r.cfg.bsize & r.cfg.csize & r.cfg.command &
r.cfg.dllrst & r.cfg.renable & r.cfg.cke;
regsd1(11 downto 0) := r.cfg.refresh;
regsd2 := (others => '0');
regsd2(8 downto 0) := conv_std_logic_vector(MHz, 9);
regsd2(14 downto 12) := conv_std_logic_vector(3, 3);
-- generate DQM from address and write size
case ra.acc.size is
when "00" =>
case ra.acc.haddr(3 downto 0) is
when "0000" => dqm := "0111111111111111";
when "0001" => dqm := "1011111111111111";
when "0010" => dqm := "1101111111111111";
when "0011" => dqm := "1110111111111111";
when "0100" => dqm := "1111011111111111";
when "0101" => dqm := "1111101111111111";
when "0110" => dqm := "1111110111111111";
when "0111" => dqm := "1111111011111111";
when "1000" => dqm := "1111111101111111";
when "1001" => dqm := "1111111110111111";
when "1010" => dqm := "1111111111011111";
when "1011" => dqm := "1111111111101111";
when "1100" => dqm := "1111111111110111";
when "1101" => dqm := "1111111111111011";
when "1110" => dqm := "1111111111111101";
when others => dqm := "1111111111111110";
end case;
when "01" =>
case ra.acc.haddr(3 downto 1) is
when "000" => dqm := "0011111111111111";
when "001" => dqm := "1100111111111111";
when "010" => dqm := "1111001111111111";
when "011" => dqm := "1111110011111111";
when "100" => dqm := "1111111100111111";
when "101" => dqm := "1111111111001111";
when "110" => dqm := "1111111111110011";
when others => dqm := "1111111111111100";
end case;
when others =>
dqm := "0000000000000000";
end case;
v.startsd := ra.startsd;
-- main FSM
case r.mstate is
when midle =>
if r.startsd = '1' then
if (r.sdstate = sidle) and (r.cfg.command = "000") and
(r.cmstate = midle)
then
startsd := '1'; v.mstate := active;
end if;
end if;
when others => null;
end case;
startsd := r.startsd xor r.startsdold;
-- generate row and column address size
haddr := ra.acc.haddr;
haddr(31 downto 20) := haddr(31 downto 20) and not conv_std_logic_vector(hmask, 12);
case r.cfg.csize is
when "00" => raddr := haddr(25 downto 12);
when "01" => raddr := haddr(26 downto 13);
when "10" => raddr := haddr(27 downto 14);
when others => raddr := haddr(28 downto 15);
end case;
-- generate bank address
ba := genmux(r.cfg.bsize, haddr(29 downto 22)) &
genmux(r.cfg.bsize, haddr(28 downto 21));
-- generate chip select
adec := genmux(r.cfg.bsize, haddr(30 downto 23));
rams := adec & not adec;
-- sdram access FSM
if r.trfc /= "000" then v.trfc := r.trfc - 1; end if;
case r.sdstate is
when sidle =>
if (startsd = '1') and (r.cfg.command = "000") and (r.cmstate = midle)
and (r.istate = finish)
then
v.address := raddr; v.ba := ba;
if ra.acc.hio = '0' then
v.sdcsn := not rams(1 downto 0); v.rasn := '0'; v.sdstate := act1;
else v.sdstate := ioreg1; end if;
end if;
v.waddr := ra.acc.haddr(7 downto 2);
when act1 =>
v.rasn := '1'; v.trfc := r.cfg.trfc;
if r.cfg.trcd = '1' then v.sdstate := act2; else
v.sdstate := act3; v.hready := ra.acc.hwrite;
end if;
v.waddr := ra.acc.haddr(7 downto 2);
when act2 =>
v.sdstate := act3; v.hready := ra.acc.hwrite;
when act3 =>
v.casn := '0';
v.address := ra.acc.haddr(15 downto 13) & '0' & ra.acc.haddr(12 downto 4) & '0';
v.dqm := dqm;
if ra.acc.hwrite = '1' then
v.waddr := r.waddr + 4; v.waddr(1 downto 0) := "00";
v.sdstate := wr1; v.sdwen := '0'; v.bdrive := '0'; v.qdrive := '1';
if (r.waddr /= ra.raddr) then v.hready := '1';
if (r.waddr(5 downto 2) = ra.raddr(5 downto 2)) then
if r.waddr(1) = '1' then v.dqm(15 downto 8) := (others => '1');
else
case ra.raddr(1 downto 0) is
when "01" => v.dqm(7 downto 0) := (others => '1');
when "10" => v.dqm(3 downto 0) := (others => '1');
v.dqm(15 downto 12) := (others => r.waddr(0));
when others => v.dqm(15 downto 12) := (others => r.waddr(0));
end case;
end if;
else
case r.waddr(1 downto 0) is
when "01" => v.dqm(15 downto 12) := (others => '1');
when "10" => v.dqm(15 downto 8) := (others => '1');
when "11" => v.dqm(15 downto 4) := (others => '1');
when others => null;
end case;
end if;
else
case r.waddr(1 downto 0) is
when "00" => v.dqm(11 downto 0) := (others => '1');
when "01" => v.dqm(15 downto 12) := (others => '1'); v.dqm(7 downto 0) := (others => '1');
when "10" => v.dqm(15 downto 8) := (others => '1'); v.dqm(3 downto 0) := (others => '1');
when others => v.dqm(15 downto 4) := (others => '1');
end case;
end if;
else v.sdstate := rd1; end if;
when wr1 =>
v.sdwen := '1'; v.casn := '1'; v.qdrive := '1';
v.waddr := r.waddr + 4; v.dqm := (others => '0');
v.address(8 downto 3) := r.waddr;
if (r.waddr <= ra.raddr) and (r.waddr(5 downto 2) /= "0000") and (r.hready = '1')
then
v.hready := '1';
if (r.hready = '1') and (r.waddr(2 downto 0) = "000") then
v.sdwen := '0'; v.casn := '0';
end if;
if (r.waddr(5 downto 2) = ra.raddr(5 downto 2)) and (r.waddr /= "000000") then
case ra.raddr(1 downto 0) is
when "00" => v.dqm(11 downto 0) := (others => '1');
when "01" => v.dqm(7 downto 0) := (others => '1');
when "10" => v.dqm(3 downto 0) := (others => '1');
when others => null;
end case;
end if;
else
v.sdstate := wr2;
v.dqm := (others => '1'); --v.bdrive := '1';
v.startsdold := r.startsd;
end if;
when wr2 =>
v.sdstate := wr3; v.qdrive := '1';
when wr3 =>
v.sdstate := wr4a; v.qdrive := '1';
when wr4a =>
v.bdrive := '1';
v.rasn := '0'; v.sdwen := '0'; v.sdstate := wr4; v.qdrive := '1';
when wr4 =>
v.sdcsn := "11"; v.rasn := '1'; v.sdwen := '1'; v.qdrive := '0';
v.sdstate := wr5;
when wr5 =>
v.sdstate := sidle;
when rd1 =>
v.casn := '1'; v.sdstate := rd7;
-- if ra.acc.haddr(4 downto 2) = "011" then
-- v.casn := '0'; v.burst := '1'; v.address(5 downto 3) := "100";
-- end if;
when rd7 =>
v.casn := '1'; v.sdstate := rd2;
-- if ra.acc.haddr(4 downto 2) = "010" then
-- v.casn := '0'; v.burst := '1'; v.address(5 downto 3) := "100";
-- end if;
when rd2 =>
v.casn := '1'; v.sdstate := rd3;
-- if ra.acc.haddr(4 downto 2) = "001" then
-- v.casn := '0'; v.burst := '1'; v.address(5 downto 3) := "100";
-- end if;
-- if v.sdwen = '0' then v.dqm := (others => '1'); end if;
when rd3 =>
if fast = 0 then v.startsdold := r.startsd; end if;
v.sdstate := rd4; v.hready := '1'; v.casn := '1';
-- if r.sdwen = '0' then
-- v.rasn := '1'; v.sdwen := '1'; v.sdcsn := "11"; v.dqm := (others => '1');
-- elsif ra.acc.haddr(4 downto 2) = "000" then
-- v.casn := '0'; v.burst := '1'; v.address(5) := '1';
-- v.waddr := v.address(8 downto 3);
-- end if;
if v.hready = '1' then v.waddr := r.waddr + 4; end if;
when rd4 =>
v.hready := '1'; v.casn := '1';
-- if (r.sdcsn /= "11") and (r.waddr(1 downto 0) = "11") and (r.burst = '1')
-- then
-- v.burst := '0';
if (r.sdcsn = "11") or (r.waddr(2 downto 2) = "1") then
v.dqm := (others => '1'); v.burst := '0';
if fast /= 0 then v.startsdold := r.startsd; end if;
if (r.sdcsn /= "11") then
v.rasn := '0'; v.sdwen := '0'; v.sdstate := rd5;
else
if r.cfg.trp = '1' then v.sdstate := rd6;
else v.sdstate := sidle; end if;
end if;
end if;
if v.hready = '1' then v.waddr := r.waddr + 4; end if;
when rd5 =>
if r.cfg.trp = '1' then v.sdstate := rd6;
else v.sdstate := sidle; end if;
v.sdcsn := (others => '1'); v.rasn := '1'; v.sdwen := '1';
v.dqm := (others => '1');
when rd6 =>
v.sdstate := sidle; v.dqm := (others => '1');
v.sdcsn := (others => '1'); v.rasn := '1'; v.sdwen := '1';
when ioreg1 =>
v.hrdata(127 downto 64) := regsd1 & regsd2; v.sdstate := ioreg2;
if ra.acc.hwrite = '0' then v.hready := '1'; end if;
when ioreg2 =>
writecfg := ra.acc.hwrite and not r.waddr(0); v.startsdold := r.startsd;
v.sdstate := sidle;
when others =>
v.sdstate := sidle;
end case;
-- sdram commands
case r.cmstate is
when midle =>
if r.sdstate = sidle then
case r.cfg.command is
when CMD_PRE => -- precharge
v.sdcsn := (others => '0'); v.rasn := '0'; v.sdwen := '0';
v.address(12) := '1'; v.cmstate := active;
when CMD_REF => -- auto-refresh
v.sdcsn := (others => '0'); v.rasn := '0'; v.casn := '0';
v.cmstate := active;
when CMD_EMR => -- load-ext-mode-reg
v.sdcsn := (others => '0'); v.rasn := '0'; v.casn := '0';
v.sdwen := '0'; v.cmstate := active; v.ba := "01";
v.address := "00000000000000";
when CMD_LMR => -- load-mode-reg
v.sdcsn := (others => '0'); v.rasn := '0'; v.casn := '0';
v.sdwen := '0'; v.cmstate := active; v.ba := "00";
-- v.address := "00000" & r.cfg.dllrst & "0" & "01" & r.cfg.trcd & "0011";
v.address := "00000" & r.cfg.dllrst & "0" & "01" & "00010";
when others => null;
end case;
end if;
when active =>
v.sdcsn := (others => '1'); v.rasn := '1'; v.casn := '1';
v.sdwen := '1'; v.cfg.command := "000";
v.cmstate := leadout; v.trfc := r.cfg.trfc;
when others =>
if r.trfc = "000" then v.cmstate := midle; end if;
end case;
-- sdram init
case r.istate is
when iidle =>
if r.cfg.renable = '1' then
v.cfg.cke := '1'; v.cfg.dllrst := '1';
if r.cfg.cke = '1' then v.istate := pre; v.cfg.command := CMD_PRE; end if; v.ba := "00";
end if;
when pre =>
if r.cfg.command = "000" then
v.cfg.command := "11" & r.cfg.dllrst; -- CMD_LMR/CMD_EMR
if r.cfg.dllrst = '1' then v.istate := emode; else v.istate := lmode; end if;
end if;
when emode =>
if r.cfg.command = "000" then
v.istate := lmode; v.cfg.command := CMD_LMR;
end if;
when lmode =>
if r.cfg.command = "000" then
if r.cfg.dllrst = '1' then
if r.refresh(9 downto 8) = "00" then -- > 200 clocks delay
v.cfg.command := CMD_PRE; v.istate := ref1;
end if;
else
v.istate := finish; --v.cfg.command := CMD_LMR;
v.cfg.refon := '1'; v.cfg.renable := '0';
end if;
end if;
when ref1 =>
if r.cfg.command = "000" then
v.cfg.command := CMD_REF; v.cfg.dllrst := '0'; v.istate := ref2;
end if;
when ref2 =>
if r.cfg.command = "000" then
v.cfg.command := CMD_REF; v.istate := pre;
end if;
when others =>
if r.cfg.renable = '1' then
v.istate := iidle; v.cfg.dllrst := '1';
end if;
end case;
-- second part of main fsm
case r.mstate is
when active =>
if v.hready = '1' then
v.mstate := midle;
end if;
when others => null;
end case;
-- sdram refresh counter
if ((r.cfg.refon = '1') and (r.istate = finish)) or
(r.cfg.dllrst = '1')
then
v.refresh := r.refresh - 1;
if (v.refresh(11) and not r.refresh(11)) = '1' then
v.refresh := r.cfg.refresh;
if r.cfg.dllrst = '0' then v.cfg.command := "100"; end if;
end if;
end if;
-- AHB register access
if (ra.acc.hio and ra.acc.hwrite and writecfg) = '1' then
v.cfg.refresh := wdata(11+96 downto 0+96);
v.cfg.cke := wdata(15+96);
v.cfg.renable := wdata(16+96);
v.cfg.dllrst := wdata(17+96);
v.cfg.command := wdata(20+96 downto 18+96);
v.cfg.csize := wdata(22+96 downto 21+96);
v.cfg.bsize := wdata(25+96 downto 23+96);
v.cfg.trcd := wdata(26+96);
v.cfg.trfc := wdata(29+96 downto 27+96);
v.cfg.trp := wdata(30+96);
v.cfg.refon := wdata(31+96);
end if;
v.nbdrive := not v.bdrive;
if oepol = 1 then bdrive := r.nbdrive; vbdrive := (others => v.nbdrive);
else bdrive := r.bdrive; vbdrive := (others => v.bdrive);end if;
-- reset
if rst = '0' then
v.sdstate := sidle;
v.mstate := midle;
v.istate := finish;
v.cmstate := midle;
v.cfg.command := "000";
v.cfg.csize := conv_std_logic_vector(col-9, 2);
v.cfg.bsize := conv_std_logic_vector(log2(Mbyte/8), 3);
if MHz > 100 then v.cfg.trcd := '1'; else v.cfg.trcd := '0'; end if;
v.cfg.refon := '0';
v.cfg.trfc := conv_std_logic_vector(75*MHz/1000-2, 3);
v.cfg.refresh := conv_std_logic_vector(7800*MHz/1000, 12);
v.refresh := (others => '0');
if pwron = 1 then v.cfg.renable := '1';
else v.cfg.renable := '0'; end if;
if MHz > 100 then v.cfg.trp := '1'; else v.cfg.trp := '0'; end if;
v.dqm := (others => '1');
v.sdwen := '1';
v.rasn := '1';
v.casn := '1';
v.hready := '0';
v.startsd := '0';
v.startsdold := '0';
v.cfg.dllrst := '0';
v.cfg.cke := '0';
end if;
ri <= v;
ribdrive <= vbdrive;
end process;
sdo.sdcke <= (others => r.cfg.cke);
ahbso.hconfig <= hconfig;
ahbso.hirq <= (others => '0');
ahbso.hindex <= hindex;
ahbregs : process(clk_ahb) begin
if rising_edge(clk_ahb) then
ra <= rai;
end if;
end process;
ddrregs : process(clk_ddr, rst) begin
if rising_edge(clk_ddr) then
r <= ri; rbdrive <= ribdrive;
end if;
if (rst = '0') then
r.sdcsn <= (others => '1'); r.bdrive <= '1'; r.nbdrive <= '0';
if oepol = 0 then rbdrive <= (others => '1');
else rbdrive <= (others => '0'); end if;
r.cfg.cke <= '0';
end if;
end process;
sdo.address <= '0' & ri.address;
sdo.ba <= ri.ba;
sdo.bdrive <= r.nbdrive when oepol = 1 else r.bdrive;
sdo.qdrive <= not (ri.qdrive or r.nbdrive);
sdo.vbdrive <= rbdrive;
sdo.sdcsn <= ri.sdcsn;
sdo.sdwen <= ri.sdwen;
sdo.dqm <= r.dqm;
sdo.rasn <= ri.rasn;
sdo.casn <= ri.casn;
sdo.data <= wdata;
read_buff : syncram_2p
generic map (tech => memtech, abits => 4, dbits => 128, sepclk => 1, wrfst => 0)
port map ( rclk => clk_ahb, renable => vcc, raddress => rai.raddr(5 downto 2),
dataout => rdata, wclk => clk_ddr, write => ri.hready,
waddress => r.waddr(5 downto 2), datain => ri.hrdata);
write_buff1 : syncram_2p
generic map (tech => memtech, abits => 4, dbits => 32, sepclk => 1, wrfst => 0)
port map ( rclk => clk_ddr, renable => vcc, raddress => r.waddr(5 downto 2),
dataout => wdata(127 downto 96), wclk => clk_ahb, write => ra.write(0),
waddress => ra.haddr(7 downto 4), datain => ahbsi.hwdata);
write_buff2 : syncram_2p
generic map (tech => memtech, abits => 4, dbits => 32, sepclk => 1, wrfst => 0)
port map ( rclk => clk_ddr, renable => vcc, raddress => r.waddr(5 downto 2),
dataout => wdata(95 downto 64), wclk => clk_ahb, write => ra.write(1),
waddress => ra.haddr(7 downto 4), datain => ahbsi.hwdata);
write_buff3 : syncram_2p
generic map (tech => memtech, abits => 4, dbits => 32, sepclk => 1, wrfst => 0)
port map ( rclk => clk_ddr, renable => vcc, raddress => r.waddr(5 downto 2),
dataout => wdata(63 downto 32), wclk => clk_ahb, write => ra.write(2),
waddress => ra.haddr(7 downto 4), datain => ahbsi.hwdata);
write_buff4 : syncram_2p
generic map (tech => memtech, abits => 4, dbits => 32, sepclk => 1, wrfst => 0)
port map ( rclk => clk_ddr, renable => vcc, raddress => r.waddr(5 downto 2),
dataout => wdata(31 downto 0), wclk => clk_ahb, write => ra.write(3),
waddress => ra.haddr(7 downto 4), datain => ahbsi.hwdata);
-- pragma translate_off
bootmsg : report_version
generic map (
msg1 => "ddrsp" & tost(hindex) & ": 64-bit DDR266 controller rev " &
tost(REVISION) & ", " & tost(Mbyte) & " Mbyte, " & tost(MHz) &
" MHz DDR clock");
-- pragma translate_on
end;
| mit | 55ce216aab1e4e075ade9747fa2a1012 | 0.545842 | 3.083245 | false | false | false | false |
impedimentToProgress/UCI-BlueChip | AttackFiles/Attacks/memAttack/lib/gaisler/leon3/proc3.vhd | 1 | 7,208 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: proc3
-- File: proc3.vhd
-- Author: Jiri Gaisler Gaisler Research
-- Description: LEON3 processor core with pipeline, mul/div & cache control
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
library techmap;
use techmap.gencomp.all;
library gaisler;
use gaisler.leon3.all;
use gaisler.libiu.all;
use gaisler.libcache.all;
use gaisler.arith.all;
--library fpu;
--use fpu.libfpu.all;
entity proc3 is
generic (
hindex : integer := 0;
fabtech : integer range 0 to NTECH := 0;
memtech : integer range 0 to NTECH := 0;
nwindows : integer range 2 to 32 := 8;
dsu : integer range 0 to 1 := 0;
fpu : integer range 0 to 15 := 0;
v8 : integer range 0 to 63 := 0;
cp : integer range 0 to 1 := 0;
mac : integer range 0 to 1 := 0;
pclow : integer range 0 to 2 := 2;
notag : integer range 0 to 1 := 0;
nwp : integer range 0 to 4 := 0;
icen : integer range 0 to 1 := 0;
irepl : integer range 0 to 2 := 2;
isets : integer range 1 to 4 := 1;
ilinesize : integer range 4 to 8 := 4;
isetsize : integer range 1 to 256 := 1;
isetlock : integer range 0 to 1 := 0;
dcen : integer range 0 to 1 := 0;
drepl : integer range 0 to 2 := 2;
dsets : integer range 1 to 4 := 1;
dlinesize : integer range 4 to 8 := 4;
dsetsize : integer range 1 to 256 := 1;
dsetlock : integer range 0 to 1 := 0;
dsnoop : integer range 0 to 6 := 0;
ilram : integer range 0 to 1 := 0;
ilramsize : integer range 1 to 512 := 1;
ilramstart : integer range 0 to 255 := 16#8e#;
dlram : integer range 0 to 1 := 0;
dlramsize : integer range 1 to 512 := 1;
dlramstart : integer range 0 to 255 := 16#8f#;
mmuen : integer range 0 to 1 := 0;
itlbnum : integer range 2 to 64 := 8;
dtlbnum : integer range 2 to 64 := 8;
tlb_type : integer range 0 to 3 := 1;
tlb_rep : integer range 0 to 1 := 0;
lddel : integer range 1 to 2 := 2;
disas : integer range 0 to 2 := 0;
tbuf : integer range 0 to 64 := 0;
pwd : integer range 0 to 2 := 0;
svt : integer range 0 to 1 := 0; -- single-vector trapping
rstaddr : integer := 0;
smp : integer range 0 to 15 := 0; -- support SMP systems
cached : integer := 0;
clk2x : integer := 0;
scantest : integer := 0
);
port (
clk : in std_ulogic;
rstn : in std_ulogic;
holdn : out std_ulogic;
ahbi : in ahb_mst_in_type;
ahbo : out ahb_mst_out_type;
ahbsi : in ahb_slv_in_type;
ahbso : in ahb_slv_out_vector;
rfi : out iregfile_in_type;
rfo : in iregfile_out_type;
crami : out cram_in_type;
cramo : in cram_out_type;
tbi : out tracebuf_in_type;
tbo : in tracebuf_out_type;
fpi : out fpc_in_type;
fpo : in fpc_out_type;
cpi : out fpc_in_type;
cpo : in fpc_out_type;
irqi : in l3_irq_in_type;
irqo : out l3_irq_out_type;
dbgi : in l3_debug_in_type;
dbgo : out l3_debug_out_type;
hclk, sclk : in std_ulogic;
hclken : in std_ulogic
);
end;
architecture rtl of proc3 is
constant IRFWT : integer := regfile_3p_write_through(memtech);
signal ici : icache_in_type;
signal ico : icache_out_type;
signal dci : dcache_in_type;
signal dco : dcache_out_type;
signal holdnx, pholdn : std_logic;
signal muli : mul32_in_type;
signal mulo : mul32_out_type;
signal divi : div32_in_type;
signal divo : div32_out_type;
begin
holdnx <= ico.hold and dco.hold and fpo.holdn; holdn <= holdnx;
pholdn <= fpo.holdn;
-- integer unit
iu0 : iu3
generic map (nwindows, isets, dsets, fpu, v8, cp, mac, dsu, nwp, pclow,
0, hindex, lddel, IRFWT, disas, tbuf, pwd, svt, rstaddr, smp, fabtech, clk2x)
port map (clk, rstn, holdnx, ici, ico, dci, dco, rfi, rfo, irqi, irqo,
dbgi, dbgo, muli, mulo, divi, divo, fpo, fpi, cpo, cpi, tbo, tbi, sclk);
-- multiply and divide units
-- Actel FPGAs cannot use inferred mul due to bug in synplify 8.9 and 9.0
mgen : if v8 /= 0 generate
mgen2 : if (fabtech = axcel) or (fabtech = apa3) generate
mul0 : mul32 generic map (0, v8/16, (v8 mod 4)/2, mac)
port map (rstn, clk, holdnx, muli, mulo);
end generate;
mgen3 : if not ((fabtech = axcel) or (fabtech = apa3)) generate
mul0 : mul32 generic map (is_fpga(fabtech), v8/16, (v8 mod 4)/2, mac)
port map (rstn, clk, holdnx, muli, mulo);
end generate;
div0 : div32 port map (rstn, clk, holdnx, divi, divo);
end generate;
nomgen : if v8 = 0 generate
divo <= ('0', '0', "0000", zero32);
mulo <= ('0', '0', "0000", zero32&zero32);
end generate;
-- cache controller
m0 : if mmuen = 0 generate
c0 : cache
generic map (hindex, dsu, icen, irepl, isets, ilinesize, isetsize,
isetlock, dcen, drepl, dsets, dlinesize, dsetsize, dsetlock, dsnoop,
ilram, ilramsize, ilramstart, dlram, dlramsize, dlramstart, cached,
clk2x, memtech, scantest)
port map ( rstn, clk, ici, ico, dci, dco, ahbi, ahbo, ahbsi, ahbso, crami, cramo, pholdn, hclk, sclk, hclken);
end generate;
m1 : if mmuen = 1 generate
c0mmu : mmu_cache
generic map (hindex=>hindex, memtech=>memtech, dsu=>dsu, icen=>icen, irepl=>irepl,
isets=>isets, ilinesize=>ilinesize, isetsize=>isetsize, isetlock=>isetlock,
dcen=>dcen, drepl=>drepl, dsets=>dsets, dlinesize=>dlinesize, dsetsize=>dsetsize,
dsetlock=>dsetlock, dsnoop=>dsnoop, itlbnum=>itlbnum, dtlbnum=>dtlbnum,
tlb_type=>tlb_type, tlb_rep=>tlb_rep, cached => cached, clk2x => clk2x,
scantest => scantest)
port map ( rstn, clk, ici, ico, dci, dco,
ahbi, ahbo, ahbsi, ahbso, crami, cramo, pholdn, hclk, sclk, hclken);
end generate;
end;
| mit | fea113d9ca18f23b5c0c92dab4b23e04 | 0.579634 | 3.427485 | false | false | false | false |
lxp32/lxp32-cpu | rtl/lxp32_ram256x32.vhd | 2 | 1,699 | ---------------------------------------------------------------------
-- Generic dual-port memory
--
-- Part of the LXP32 CPU
--
-- Copyright (c) 2016 by Alex I. Kuznetsov
--
-- Portable description of a dual-port memory block with one write
-- port. Major FPGA synthesis tools can infer on-chip block RAM
-- from this description. Can be replaced with a library component
-- wrapper if needed.
---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity lxp32_ram256x32 is
port(
clk_i: in std_logic;
we_i: in std_logic;
waddr_i: in std_logic_vector(7 downto 0);
wdata_i: in std_logic_vector(31 downto 0);
re_i: in std_logic;
raddr_i: in std_logic_vector(7 downto 0);
rdata_o: out std_logic_vector(31 downto 0)
);
end entity;
architecture rtl of lxp32_ram256x32 is
type ram_type is array(255 downto 0) of std_logic_vector(31 downto 0);
signal ram: ram_type:=(others=>(others=>'0')); -- zero-initialize for SRAM-based FPGAs
attribute syn_ramstyle: string;
attribute syn_ramstyle of ram: signal is "no_rw_check";
attribute ram_style: string; -- for Xilinx
attribute ram_style of ram: signal is "block";
begin
-- Write port
process (clk_i) is
begin
if rising_edge(clk_i) then
if we_i='1' then
ram(to_integer(unsigned(waddr_i)))<=wdata_i;
end if;
end if;
end process;
-- Read port
process (clk_i) is
begin
if rising_edge(clk_i) then
if re_i='1' then
if is_x(raddr_i) then -- to avoid numeric_std warnings during simulation
rdata_o<=(others=>'X');
else
rdata_o<=ram(to_integer(unsigned(raddr_i)));
end if;
end if;
end if;
end process;
end architecture;
| mit | 9f71fc8aebd6e91cfe6c5266bac009ea | 0.638611 | 3.146296 | false | false | false | false |
christakissgeo/Matrix-Vector-Multiplication | VHDL Files/counter_address_generator.vhd | 1 | 1,134 | --Counter Address Generator
library IEEE;
use IEEE.Std_logic_1164.all;
use IEEE.Numeric_std.all;
use IEEE.Std_logic_unsigned.all;
-------------------------------------------
entity counter_address_generator is
port (
clock : in std_logic;
reset : in std_logic;
need_to_reset : in std_logic;
enable : in std_logic;
read_enable : in std_logic;
address : out std_logic_vector (7 downto 0)
);
end entity counter_address_generator;
------------------------------------------
architecture counter_address_generator of counter_address_generator is
signal address_1: std_logic_vector (7 downto 0);
begin
process(clock, reset)
begin
if rising_edge(clock) then
if reset = '1' then
address_1 <= "00000000";
elsif (enable = '1' or read_enable= '1') then
if need_to_reset = '1' then
address_1 <= "00000000";
else
address_1 <= address_1 + "00000001";
end if;
else
address_1 <= address_1;
end if;
end if;
end process;
address <= address_1;
end architecture counter_address_generator;
| mit | b9b81cbcf46a3d8bd6205d58a4571584 | 0.574074 | 3.345133 | false | false | false | false |
amerc/phimii | source/initPhyNexys3.vhd | 2 | 2,377 | ----------------------------------------------------------------------------------
-- Initialise the Nexys3 board Phy (smcs 8710A)
-- Author: Amer Al-Canaan
--
---
--- E-mail: [email protected]
--- License: MIT
--- Copyright: Copyright (C) Amer Al-Canaan 2014
-- Create Date: 06:40:19 04/05/2014
-- Design Name:
-- Module Name: initPhyNexys3 - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description: This module provides the necessary timing signals to
-- initialise the Phy chip LAN8710A (Nexys3 board) during POR (Power
-- On Reset) with adequate configuration modes. The minimum time for
-- this operation is 25 ms, but since the input signals for the
-- configurations are provided by the FPGA it seems that the minmum
-- time needed is around 50 ms.
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity initPhyNexys3 is
port (clk : in std_logic;
reset : in std_logic; -- Global reset
phy_reset : out std_logic; -- To PhyReset pin
out_en : out std_logic);
end initPhyNexys3;
architecture Behavioral of initPhyNexys3 is
signal tmpreset : std_logic := '1';
signal tmpouten : std_logic := '0';
begin
process (clk)
variable Cnt : natural range 0 to 1004000:=0; ---Around 20 when clock is 50 MHz
begin
if rising_edge(clk) then
if (reset = '1') then
Cnt := 0;
tmpreset <= '1';
tmpouten <= '1';
else
if (Cnt <= 1004000) then
Cnt := Cnt + 1;
else Cnt := Cnt;
end if;
case Cnt is
when 0800000 => tmpreset <= '0'; tmpouten <= '1'; --(16 ms)
when 0800100 => tmpreset <= '0'; tmpouten <= '0'; --(16.002 ms)
when 1000000 => tmpreset <= '1'; tmpouten <= '0'; --(20 ms)
when 1004000 => tmpreset <= '1'; tmpouten <= '1'; --(20.08 ms)
when others => tmpreset <= tmpreset; tmpouten <= tmpouten;
end case;
end if;
end if;
end process;
phy_reset <= tmpreset;
out_en <= tmpouten;
end Behavioral; | mit | 4c50509c753c8660f536e16c292d4f79 | 0.620951 | 3.41033 | false | false | false | false |
franz/pocl | examples/accel/rtl/vhdl/fu_lsu_32b_slim.vhdl | 2 | 14,801 | -- Copyright (c) 2017-2019 Tampere University of Technology.
--
-- This file is part of TTA-Based Codesign Environment (TCE).
--
-- Permission is hereby granted, free of charge, to any person obtaining a
-- copy of this software and associated documentation files (the "Software"),
-- to deal in the Software without restriction, including without limitation
-- the rights to use, copy, modify, merge, publish, distribute, sublicense,
-- and/or sell copies of the Software, and to permit persons to whom the
-- Software is furnished to do so, subject to the following conditions:
--
-- The above copyright notice and this permission notice shall be included in
-- all copies or substantial portions of the Software.
--
-- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-- AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
-- FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
-- DEALINGS IN THE SOFTWARE.
-------------------------------------------------------------------------------
-- Title : LSU for AlmaIF Integrator
-- Project : Almarvi
-------------------------------------------------------------------------------
-- File : fu_lsu_32b_slim.vhdl
-- Author : Kati Tervo
-- Company :
-- Created : 2017-05-31
-- Last update: 2019-05-22
-- Platform :
-------------------------------------------------------------------------------
-- Description: 32 bit wide LSU with parametric endianness
-- External ports:
-- | Signal | Comment
-- ---------------------------------------------------------------------------
-- | | Access channel
-- | avalid_out | LSU asserts avalid when it has a valid command for the memory
-- | aready_in | and considers the command accepted when both avalid and
-- | | aready are asserted on the same clock cycle
-- | |
-- | aaddr_out | Address of the access, word-addressed
-- | awren_out | High for write, low for read
-- | astrb_out | Bytewise write strobe
-- | adata_out | Data to write, if any
-- | |
-- | | Response channel
-- | rvalid_in | Works like avalid/aready, in the other direction. The memory
-- | rready_out | must keep read accesses in order.
-- | |
-- | rdata_in | Read data, if any.
-- ---------------------------------------------------------------------------
--
-- Revisions :
-- Date Version Author Description
-- 2017-05-31 1.0 katte Created
-- 2019-05-22 1.0 katte Removed sign-extending operations (LD16/LD8)
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity fu_lsu_32b_slim is
generic (
addrw_g : integer := 11;
-- This will be converted to slv later, but passed as integer because
-- some tools only handle ints (esp. mixed-language simulation or synthesis)
register_bypass_g : integer := 2;
-- Ditto, converted to boolean
little_endian_g : integer := 1
);
port(
clk : in std_logic;
rstx : in std_logic;
-- Control signals
glock_in : in std_logic;
glockreq_out : out std_logic;
-- Address port, triggers
t1_address_in : in std_logic_vector(addrw_g-1 downto 0);
t1_load_in : in std_logic;
t1_opcode_in : in std_logic_vector(2 downto 0);
-- Data operand and output ports
o1_data_in : in std_logic_vector(32-1 downto 0);
o1_load_in : in std_logic;
r1_data_out : out std_logic_vector(32-1 downto 0);
-- external memory unit interface:
-- Access channel
avalid_out : out std_logic_vector(0 downto 0);
aready_in : in std_logic_vector(0 downto 0);
aaddr_out : out std_logic_vector(addrw_g-2-1 downto 0);
awren_out : out std_logic_vector(0 downto 0);
astrb_out : out std_logic_vector(4-1 downto 0);
adata_out : out std_logic_vector(32-1 downto 0);
-- Read channel
rvalid_in : in std_logic_vector(0 downto 0);
rready_out : out std_logic_vector(0 downto 0);
rdata_in : in std_logic_vector(32-1 downto 0)
);
end fu_lsu_32b_slim;
architecture rtl of fu_lsu_32b_slim is
constant is_little_endian_c : boolean := little_endian_g /= 0;
function pipeline_depth(reg_bypass : std_logic_vector) return integer is
variable result : integer := 0;
begin
if reg_bypass(0) = '0' then
return 3;
else
return 2;
end if;
end pipeline_depth;
type operations_t is (LD32, LD16, LD8, STORE, NOP);
type pipeline_state_t is record
operation : operations_t;
addr_low : std_logic_vector(2 - 1 downto 0);
end record;
-------------------------------------------------------------------------
-- register_bypass_c: if element n is '1', bypass corresponding registers
-- n | register name | description
-- ----------------------------------------------------------------------
-- 0 | rdata_r | Registers rdata_in
-- 1 | result_r | FU output port register
-------------------------------------------------------------------------
constant register_bypass_c : std_logic_vector(3 - 1 downto 0)
:= std_logic_vector(to_unsigned(register_bypass_g, 3));
constant data_width_c : integer := 32;
constant byte_width_c : integer := data_width_c/8;
type pipeline_regs_t is
array (pipeline_depth(register_bypass_c) - 1 downto 0)
of pipeline_state_t;
signal pipeline_r : pipeline_regs_t;
signal o1_data_r : std_logic_vector(data_width_c - 1 downto 0);
signal write_data : std_logic_vector(data_width_c - 1 downto 0);
signal glockreq : std_logic;
signal fu_glock : std_logic;
-- Access channel registers
signal avalid_r : std_logic;
signal aaddr_r : std_logic_vector(aaddr_out'range);
signal awren_r : std_logic;
signal astrb_r : std_logic_vector(astrb_out'range);
signal adata_r : std_logic_vector(adata_out'range);
signal rready_r : std_logic;
-- Signals between memory and LSU output
signal read_data : std_logic_vector(data_width_c - 1 downto 0);
signal rdata_r : std_logic_vector(data_width_c - 1 downto 0);
signal result : std_logic_vector(data_width_c - 1 downto 0);
signal result_r : std_logic_vector(data_width_c - 1 downto 0);
----------------------------------------------------------------------------
-- Lookup table for converting between BE and LE
-- --------------------------------------
-- | LE OPC | LE # | BE OPC | BE # |
-- --------------------------------------
-- | OPC_LD32 | 0 | OPC_LDW | 2 |
-- | OPC_LDU16 | 1 | OPC_LDHU | 0 |
-- | OPC_LDU8 | 2 | OPC_LDQU | 1 |
-- | OPC_ST16 | 3 | OPC_STH | 3 |
-- | OPC_ST32 | 4 | OPC_STW | 5 |
-- | OPC_ST8 | 5 | OPC_STQ | 4 |
-- --------------------------------------
----------------------------------------------------------------------------
type opcode_array is array (0 to 5, 0 to 1) of integer;
constant opcode_lut : opcode_array := ((0, 0), (4, 1), (1, 2),
(3, 3), (5, 4), (4, 5));
-- LE opcodes for the switch statements
constant OPC_LD32 : integer := 0;
constant OPC_LDU16 : integer := 1;
constant OPC_LDU8 : integer := 2;
constant OPC_ST16 : integer := 3;
constant OPC_ST32 : integer := 4;
constant OPC_ST8 : integer := 5;
begin
-- Design-wide assertions
-- coverage off
-- synthesis translate_off
assert register_bypass_g < 4 and register_bypass_g >= 0
report "register_bypass_g out of range"
severity failure;
assert little_endian_g = 0 or little_endian_g = 1
report "little_endian_g should be either 0 or 1"
severity failure;
-- coverage on
-- synthesis translate_on
avalid_out(0) <= avalid_r;
awren_out(0) <= awren_r;
aaddr_out <= aaddr_r;
astrb_out <= astrb_r;
adata_out <= adata_r;
rready_out(0) <= rready_r;
shadow_registers_sync : process(clk, rstx)
begin
if rstx = '0' then
o1_data_r <= (others => '0');
result_r <= (others => '0');
elsif rising_edge(clk) then
if fu_glock = '0' then
if o1_load_in = '1' then
o1_data_r <= o1_data_in;
end if;
result_r <= result;
end if;
end if;
end process;
write_data <= o1_data_in when o1_load_in = '1' else o1_data_r;
gen_lockreq : process(rready_r, rvalid_in, avalid_r, aready_in,
glock_in, glockreq)
begin
if (rready_r = '1' and rvalid_in(0) = '0')
or (avalid_r = '1' and aready_in(0) = '0') then
glockreq <= '1';
else
glockreq <= '0';
end if;
fu_glock <= glockreq or glock_in;
glockreq_out <= glockreq;
end process gen_lockreq;
-------------------------------------------------------------------------------
-- Byte shifts and enable signal logic based on most recent opcode
-------------------------------------------------------------------------------
access_channel_sync : process(clk, rstx)
variable opcode : integer range 0 to 7;
variable addr_low : std_logic_vector(2 - 1 downto 0);
variable byte_offset : integer range 3 downto 0;
begin
if rstx = '0' then
pipeline_r <= (others => (NOP, "00"));
aaddr_r <= (others => '0');
astrb_r <= (others => '0');
adata_r <= (others => '0');
avalid_r <= '0';
awren_r <= '0';
elsif rising_edge(clk) then
if avalid_r = '1' and aready_in(0) = '1' then
avalid_r <= '0';
end if;
if fu_glock = '0' then
pipeline_r(pipeline_r'high downto 1)
<= pipeline_r(pipeline_r'high-1 downto 0);
if t1_load_in = '1' then
avalid_r <= '1';
aaddr_r <= t1_address_in(t1_address_in'high downto 2);
opcode := opcode_lut(to_integer(unsigned(t1_opcode_in)),
little_endian_g);
addr_low := t1_address_in(2 - 1 downto 0);
case opcode is
when OPC_LD32 =>
pipeline_r(0) <= (LD32, addr_low);
awren_r <= '0';
when OPC_LDU16 =>
pipeline_r(0) <= (LD16, addr_low);
awren_r <= '0';
when OPC_LDU8 =>
pipeline_r(0) <= (LD8, addr_low);
awren_r <= '0';
when OPC_ST32 =>
pipeline_r(0) <= (STORE, "00");
awren_r <= '1';
astrb_r <= "1111";
adata_r <= write_data;
when OPC_ST16 =>
pipeline_r(0) <= (STORE, "00");
awren_r <= '1';
adata_r <= (others => '0');
if addr_low(1) = '1' xnor is_little_endian_c then
adata_r(32 - 1 downto 16) <= write_data(16 - 1 downto 0);
astrb_r <= "1100";
else
adata_r(16 - 1 downto 0) <= write_data(16 - 1 downto 0);
astrb_r <= "0011";
end if;
when others => -- OPC_ST8
pipeline_r(0) <= (STORE, "00");
awren_r <= '1';
if is_little_endian_c then
byte_offset := to_integer(unsigned(addr_low));
else
byte_offset := 3 - to_integer(unsigned(addr_low));
end if;
adata_r <= (others => '0');
adata_r(8*byte_offset + 7 downto 8*byte_offset)
<= write_data(8 - 1 downto 0);
astrb_r(byte_offset) <= '1';
end case;
else
pipeline_r(0) <= (NOP, "00");
avalid_r <= '0';
awren_r <= '0';
aaddr_r <= (others => '0');
astrb_r <= (others => '0');
adata_r <= (others => '0');
end if;
end if;
end if;
end process access_channel_sync;
read_channel_sync : process(clk, rstx)
begin
if rstx = '0'then
rready_r <= '0';
rdata_r <= (others => '0');
elsif rising_edge(clk) then
if rvalid_in = "1" and rready_r = '1' then
rdata_r <= rdata_in;
rready_r <= '0';
end if;
if pipeline_r(0).operation /= STORE and pipeline_r(0).operation /= NOP
and fu_glock = '0' then
rready_r <= '1';
end if;
end if;
end process read_channel_sync;
bypass_read_data_register : if register_bypass_c(0) = '1' generate
read_data <= rdata_in when rready_r = '1' else rdata_r;
end generate;
use_mem_output_register : if register_bypass_c(0) = '0' generate
read_data <= rdata_r;
end generate;
-------------------------------------------------------------------------------
-- Read data formatting based on load type
-------------------------------------------------------------------------------
shift_and_sext : process(pipeline_r, read_data, result_r)
variable read_16 : std_logic_vector(16 - 1 downto 0);
variable read_8 : std_logic_vector(8 - 1 downto 0);
variable byte_offset : integer range 3 downto 0;
begin
case pipeline_r(pipeline_r'high).operation is
when LD32 =>
result <= read_data;
when LD16 =>
if pipeline_r(pipeline_r'high).addr_low(1) = '1'
xnor is_little_endian_c then
read_16 := read_data(31 downto 16);
else
read_16 := read_data(15 downto 0);
end if;
result <= (others => '0');
result(16 - 1 downto 0) <= read_16;
when LD8 =>
if is_little_endian_c then
byte_offset
:= to_integer(unsigned(pipeline_r(pipeline_r'high).addr_low));
else
byte_offset
:= 3 - to_integer(unsigned(pipeline_r(pipeline_r'high).addr_low));
end if;
read_8 := read_data(8*byte_offset + 7 downto 8*byte_offset);
result <= (others => '0');
result(8 - 1 downto 0) <= read_8;
when others => -- NOP, STORE
result <= result_r;
end case;
end process shift_and_sext;
bypass_r1data_register : if register_bypass_c(1) = '1' generate
r1_data_out <= result;
end generate;
use_r1data_register : if register_bypass_c(1) = '0' generate
r1_data_out <= result_r;
end generate;
end rtl;
| mit | 122afbd1e33490da0ad715f1cfa88052 | 0.511655 | 3.633931 | false | false | false | false |
cafe-alpha/wascafe | v13/r07c_de10_20201014_abus4/sniff_fifo.vhd | 2 | 7,063 | -- megafunction wizard: %FIFO%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: scfifo
-- ============================================================
-- File Name: sniff_fifo.vhd
-- Megafunction Name(s):
-- scfifo
--
-- Simulation Library Files(s):
-- altera_mf
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 15.1.0 Build 185 10/21/2015 SJ Lite Edition
-- ************************************************************
--Copyright (C) 1991-2015 Altera Corporation. All rights reserved.
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, the Altera Quartus Prime License Agreement,
--the Altera MegaCore Function License Agreement, or other
--applicable license agreement, including, without limitation,
--that your use is for the sole purpose of programming logic
--devices manufactured by Altera and sold by Altera or its
--authorized distributors. Please refer to the applicable
--agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
ENTITY sniff_fifo IS
PORT
(
clock : IN STD_LOGIC ;
data : IN STD_LOGIC_VECTOR (47 DOWNTO 0);
rdreq : IN STD_LOGIC ;
wrreq : IN STD_LOGIC ;
empty : OUT STD_LOGIC ;
full : OUT STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (47 DOWNTO 0);
usedw : OUT STD_LOGIC_VECTOR (9 DOWNTO 0)
);
END sniff_fifo;
ARCHITECTURE SYN OF sniff_fifo IS
SIGNAL sub_wire0 : STD_LOGIC ;
SIGNAL sub_wire1 : STD_LOGIC ;
SIGNAL sub_wire2 : STD_LOGIC_VECTOR (47 DOWNTO 0);
SIGNAL sub_wire3 : STD_LOGIC_VECTOR (9 DOWNTO 0);
COMPONENT scfifo
GENERIC (
add_ram_output_register : STRING;
intended_device_family : STRING;
lpm_numwords : NATURAL;
lpm_showahead : STRING;
lpm_type : STRING;
lpm_width : NATURAL;
lpm_widthu : NATURAL;
overflow_checking : STRING;
underflow_checking : STRING;
use_eab : STRING
);
PORT (
clock : IN STD_LOGIC ;
data : IN STD_LOGIC_VECTOR (47 DOWNTO 0);
rdreq : IN STD_LOGIC ;
wrreq : IN STD_LOGIC ;
empty : OUT STD_LOGIC ;
full : OUT STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (47 DOWNTO 0);
usedw : OUT STD_LOGIC_VECTOR (9 DOWNTO 0)
);
END COMPONENT;
BEGIN
empty <= sub_wire0;
full <= sub_wire1;
q <= sub_wire2(47 DOWNTO 0);
usedw <= sub_wire3(9 DOWNTO 0);
scfifo_component : scfifo
GENERIC MAP (
add_ram_output_register => "OFF",
intended_device_family => "MAX 10",
lpm_numwords => 1024,
lpm_showahead => "ON",
lpm_type => "scfifo",
lpm_width => 48,
lpm_widthu => 10,
overflow_checking => "ON",
underflow_checking => "ON",
use_eab => "ON"
)
PORT MAP (
clock => clock,
data => data,
rdreq => rdreq,
wrreq => wrreq,
empty => sub_wire0,
full => sub_wire1,
q => sub_wire2,
usedw => sub_wire3
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0"
-- Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1"
-- Retrieval info: PRIVATE: AlmostFull NUMERIC "0"
-- Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1"
-- Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0"
-- Retrieval info: PRIVATE: Clock NUMERIC "0"
-- Retrieval info: PRIVATE: Depth NUMERIC "1024"
-- Retrieval info: PRIVATE: Empty NUMERIC "1"
-- Retrieval info: PRIVATE: Full NUMERIC "1"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "MAX 10"
-- Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
-- Retrieval info: PRIVATE: LegacyRREQ NUMERIC "0"
-- Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
-- Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "0"
-- Retrieval info: PRIVATE: Optimize NUMERIC "0"
-- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "0"
-- Retrieval info: PRIVATE: UsedW NUMERIC "1"
-- Retrieval info: PRIVATE: Width NUMERIC "48"
-- Retrieval info: PRIVATE: dc_aclr NUMERIC "0"
-- Retrieval info: PRIVATE: diff_widths NUMERIC "0"
-- Retrieval info: PRIVATE: msb_usedw NUMERIC "0"
-- Retrieval info: PRIVATE: output_width NUMERIC "48"
-- Retrieval info: PRIVATE: rsEmpty NUMERIC "1"
-- Retrieval info: PRIVATE: rsFull NUMERIC "0"
-- Retrieval info: PRIVATE: rsUsedW NUMERIC "0"
-- Retrieval info: PRIVATE: sc_aclr NUMERIC "0"
-- Retrieval info: PRIVATE: sc_sclr NUMERIC "0"
-- Retrieval info: PRIVATE: wsEmpty NUMERIC "0"
-- Retrieval info: PRIVATE: wsFull NUMERIC "1"
-- Retrieval info: PRIVATE: wsUsedW NUMERIC "0"
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: CONSTANT: ADD_RAM_OUTPUT_REGISTER STRING "OFF"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "MAX 10"
-- Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "1024"
-- Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "ON"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "scfifo"
-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "48"
-- Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "10"
-- Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "ON"
-- Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "ON"
-- Retrieval info: CONSTANT: USE_EAB STRING "ON"
-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL "clock"
-- Retrieval info: USED_PORT: data 0 0 48 0 INPUT NODEFVAL "data[47..0]"
-- Retrieval info: USED_PORT: empty 0 0 0 0 OUTPUT NODEFVAL "empty"
-- Retrieval info: USED_PORT: full 0 0 0 0 OUTPUT NODEFVAL "full"
-- Retrieval info: USED_PORT: q 0 0 48 0 OUTPUT NODEFVAL "q[47..0]"
-- Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL "rdreq"
-- Retrieval info: USED_PORT: usedw 0 0 10 0 OUTPUT NODEFVAL "usedw[9..0]"
-- Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL "wrreq"
-- Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
-- Retrieval info: CONNECT: @data 0 0 48 0 data 0 0 48 0
-- Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
-- Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
-- Retrieval info: CONNECT: empty 0 0 0 0 @empty 0 0 0 0
-- Retrieval info: CONNECT: full 0 0 0 0 @full 0 0 0 0
-- Retrieval info: CONNECT: q 0 0 48 0 @q 0 0 48 0
-- Retrieval info: CONNECT: usedw 0 0 10 0 @usedw 0 0 10 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL sniff_fifo.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL sniff_fifo.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL sniff_fifo.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL sniff_fifo.bsf FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL sniff_fifo_inst.vhd TRUE
-- Retrieval info: LIB_FILE: altera_mf
| gpl-2.0 | c91f27483b7b5510e9b946dc83f30cf4 | 0.666006 | 3.5315 | false | false | false | false |
cafe-alpha/wascafe | v13/stm32_bup_test/r07c_de10_20200912/wasca/synthesis/wasca.vhd | 1 | 126,786 | -- wasca.vhd
-- Generated using ACDS version 15.1 193
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity wasca is
port (
abus_slave_0_abus_address : in std_logic_vector(9 downto 0) := (others => '0'); -- abus_slave_0_abus.address
abus_slave_0_abus_chipselect : in std_logic_vector(2 downto 0) := (others => '0'); -- .chipselect
abus_slave_0_abus_read : in std_logic := '0'; -- .read
abus_slave_0_abus_write : in std_logic_vector(1 downto 0) := (others => '0'); -- .write
abus_slave_0_abus_waitrequest : out std_logic; -- .waitrequest
abus_slave_0_abus_interrupt : out std_logic; -- .interrupt
abus_slave_0_abus_addressdata : inout std_logic_vector(15 downto 0) := (others => '0'); -- .addressdata
abus_slave_0_abus_direction : out std_logic; -- .direction
abus_slave_0_abus_muxing : out std_logic_vector(1 downto 0); -- .muxing
abus_slave_0_abus_disableout : out std_logic; -- .disableout
abus_slave_0_conduit_saturn_reset_saturn_reset : in std_logic := '0'; -- abus_slave_0_conduit_saturn_reset.saturn_reset
altpll_0_areset_conduit_export : in std_logic := '0'; -- altpll_0_areset_conduit.export
altpll_0_locked_conduit_export : out std_logic; -- altpll_0_locked_conduit.export
altpll_0_phasedone_conduit_export : out std_logic; -- altpll_0_phasedone_conduit.export
clk_clk : in std_logic := '0'; -- clk.clk
clock_116_mhz_clk : out std_logic; -- clock_116_mhz.clk
external_sdram_controller_wire_addr : out std_logic_vector(12 downto 0); -- external_sdram_controller_wire.addr
external_sdram_controller_wire_ba : out std_logic_vector(1 downto 0); -- .ba
external_sdram_controller_wire_cas_n : out std_logic; -- .cas_n
external_sdram_controller_wire_cke : out std_logic; -- .cke
external_sdram_controller_wire_cs_n : out std_logic; -- .cs_n
external_sdram_controller_wire_dq : inout std_logic_vector(15 downto 0) := (others => '0'); -- .dq
external_sdram_controller_wire_dqm : out std_logic_vector(1 downto 0); -- .dqm
external_sdram_controller_wire_ras_n : out std_logic; -- .ras_n
external_sdram_controller_wire_we_n : out std_logic; -- .we_n
leds_conn_export : out std_logic_vector(3 downto 0); -- leds_conn.export
sdram_clkout_clk : out std_logic; -- sdram_clkout.clk
switches_conn_export : in std_logic_vector(2 downto 0) := (others => '0'); -- switches_conn.export
uart_0_external_connection_rxd : in std_logic := '0'; -- uart_0_external_connection.rxd
uart_0_external_connection_txd : out std_logic -- .txd
);
end entity wasca;
architecture rtl of wasca is
component abus_demux is
port (
clock : in std_logic := 'X'; -- clk
abus_address : in std_logic_vector(9 downto 0) := (others => 'X'); -- address
abus_chipselect : in std_logic_vector(2 downto 0) := (others => 'X'); -- chipselect
abus_read : in std_logic := 'X'; -- read
abus_write : in std_logic_vector(1 downto 0) := (others => 'X'); -- write
abus_waitrequest : out std_logic; -- waitrequest
abus_interrupt : out std_logic; -- interrupt
abus_addressdata : inout std_logic_vector(15 downto 0) := (others => 'X'); -- addressdata
abus_direction : out std_logic; -- direction
abus_muxing : out std_logic_vector(1 downto 0); -- muxing
abus_disable_out : out std_logic; -- disableout
reset : in std_logic := 'X'; -- reset
avalon_nios_read : in std_logic := 'X'; -- read
avalon_nios_write : in std_logic := 'X'; -- write
avalon_nios_address : in std_logic_vector(7 downto 0) := (others => 'X'); -- address
avalon_nios_writedata : in std_logic_vector(15 downto 0) := (others => 'X'); -- writedata
avalon_nios_readdata : out std_logic_vector(15 downto 0); -- readdata
avalon_nios_waitrequest : out std_logic; -- waitrequest
avalon_nios_readdatavalid : out std_logic; -- readdatavalid
avalon_nios_burstcount : in std_logic := 'X'; -- burstcount
demux_writeaddress : out std_logic_vector(27 downto 0); -- writeaddress
demux_writedata : out std_logic_vector(15 downto 0); -- data
demux_writepulse : out std_logic; -- writepulse
demux_write_byteenable : out std_logic_vector(1 downto 0); -- write_byteenable
demux_readdata : in std_logic_vector(15 downto 0) := (others => 'X'); -- readdata
demux_readpulse : out std_logic; -- readpulse
demux_readdatavalid : in std_logic := 'X'; -- readdatavalid
demux_readaddress : out std_logic_vector(27 downto 0); -- readaddress
saturn_reset : in std_logic := 'X' -- saturn_reset
);
end component abus_demux;
component abus_slave is
port (
clock : in std_logic := 'X'; -- clk
avalon_read : out std_logic; -- read
avalon_write : out std_logic; -- write
avalon_waitrequest : in std_logic := 'X'; -- waitrequest
avalon_address : out std_logic_vector(27 downto 0); -- address
avalon_readdata : in std_logic_vector(15 downto 0) := (others => 'X'); -- readdata
avalon_writedata : out std_logic_vector(15 downto 0); -- writedata
avalon_readdatavalid : in std_logic := 'X'; -- readdatavalid
avalon_burstcount : out std_logic; -- burstcount
reset : in std_logic := 'X'; -- reset
avalon_nios_read : in std_logic := 'X'; -- read
avalon_nios_write : in std_logic := 'X'; -- write
avalon_nios_address : in std_logic_vector(7 downto 0) := (others => 'X'); -- address
avalon_nios_writedata : in std_logic_vector(15 downto 0) := (others => 'X'); -- writedata
avalon_nios_readdata : out std_logic_vector(15 downto 0); -- readdata
avalon_nios_waitrequest : out std_logic; -- waitrequest
avalon_nios_readdatavalid : out std_logic; -- readdatavalid
avalon_nios_burstcount : in std_logic := 'X'; -- burstcount
demux_writeaddress : in std_logic_vector(27 downto 0) := (others => 'X'); -- writeaddress
demux_writedata : in std_logic_vector(15 downto 0) := (others => 'X'); -- data
demux_writepulse : in std_logic := 'X'; -- writepulse
demux_write_byteenable : in std_logic_vector(1 downto 0) := (others => 'X'); -- write_byteenable
demux_readdata : out std_logic_vector(15 downto 0); -- readdata
demux_readpulse : in std_logic := 'X'; -- readpulse
demux_readdatavalid : out std_logic; -- readdatavalid
demux_readaddress : in std_logic_vector(27 downto 0) := (others => 'X') -- readaddress
);
end component abus_slave;
component wasca_altpll_0 is
port (
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
read : in std_logic := 'X'; -- read
write : in std_logic := 'X'; -- write
address : in std_logic_vector(1 downto 0) := (others => 'X'); -- address
readdata : out std_logic_vector(31 downto 0); -- readdata
writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
c0 : out std_logic; -- clk
c1 : out std_logic; -- clk
areset : in std_logic := 'X'; -- export
locked : out std_logic; -- export
phasedone : out std_logic -- export
);
end component wasca_altpll_0;
component wasca_external_sdram_controller is
port (
clk : in std_logic := 'X'; -- clk
reset_n : in std_logic := 'X'; -- reset_n
az_addr : in std_logic_vector(23 downto 0) := (others => 'X'); -- address
az_be_n : in std_logic_vector(1 downto 0) := (others => 'X'); -- byteenable_n
az_cs : in std_logic := 'X'; -- chipselect
az_data : in std_logic_vector(15 downto 0) := (others => 'X'); -- writedata
az_rd_n : in std_logic := 'X'; -- read_n
az_wr_n : in std_logic := 'X'; -- write_n
za_data : out std_logic_vector(15 downto 0); -- readdata
za_valid : out std_logic; -- readdatavalid
za_waitrequest : out std_logic; -- waitrequest
zs_addr : out std_logic_vector(12 downto 0); -- export
zs_ba : out std_logic_vector(1 downto 0); -- export
zs_cas_n : out std_logic; -- export
zs_cke : out std_logic; -- export
zs_cs_n : out std_logic; -- export
zs_dq : inout std_logic_vector(15 downto 0) := (others => 'X'); -- export
zs_dqm : out std_logic_vector(1 downto 0); -- export
zs_ras_n : out std_logic; -- export
zs_we_n : out std_logic -- export
);
end component wasca_external_sdram_controller;
component wasca_leds is
port (
clk : in std_logic := 'X'; -- clk
reset_n : in std_logic := 'X'; -- reset_n
address : in std_logic_vector(1 downto 0) := (others => 'X'); -- address
write_n : in std_logic := 'X'; -- write_n
writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
chipselect : in std_logic := 'X'; -- chipselect
readdata : out std_logic_vector(31 downto 0); -- readdata
out_port : out std_logic_vector(3 downto 0) -- export
);
end component wasca_leds;
component wasca_nios2_gen2_0 is
port (
clk : in std_logic := 'X'; -- clk
reset_n : in std_logic := 'X'; -- reset_n
d_address : out std_logic_vector(26 downto 0); -- address
d_byteenable : out std_logic_vector(3 downto 0); -- byteenable
d_read : out std_logic; -- read
d_readdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
d_waitrequest : in std_logic := 'X'; -- waitrequest
d_write : out std_logic; -- write
d_writedata : out std_logic_vector(31 downto 0); -- writedata
debug_mem_slave_debugaccess_to_roms : out std_logic; -- debugaccess
i_address : out std_logic_vector(26 downto 0); -- address
i_read : out std_logic; -- read
i_readdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
i_waitrequest : in std_logic := 'X'; -- waitrequest
irq : in std_logic_vector(31 downto 0) := (others => 'X'); -- irq
debug_reset_request : out std_logic; -- reset
debug_mem_slave_address : in std_logic_vector(8 downto 0) := (others => 'X'); -- address
debug_mem_slave_byteenable : in std_logic_vector(3 downto 0) := (others => 'X'); -- byteenable
debug_mem_slave_debugaccess : in std_logic := 'X'; -- debugaccess
debug_mem_slave_read : in std_logic := 'X'; -- read
debug_mem_slave_readdata : out std_logic_vector(31 downto 0); -- readdata
debug_mem_slave_waitrequest : out std_logic; -- waitrequest
debug_mem_slave_write : in std_logic := 'X'; -- write
debug_mem_slave_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
dummy_ci_port : out std_logic -- readra
);
end component wasca_nios2_gen2_0;
component altera_onchip_flash is
generic (
INIT_FILENAME : string := "";
INIT_FILENAME_SIM : string := "";
DEVICE_FAMILY : string := "Unknown";
PART_NAME : string := "Unknown";
DEVICE_ID : string := "Unknown";
SECTOR1_START_ADDR : integer := 0;
SECTOR1_END_ADDR : integer := 0;
SECTOR2_START_ADDR : integer := 0;
SECTOR2_END_ADDR : integer := 0;
SECTOR3_START_ADDR : integer := 0;
SECTOR3_END_ADDR : integer := 0;
SECTOR4_START_ADDR : integer := 0;
SECTOR4_END_ADDR : integer := 0;
SECTOR5_START_ADDR : integer := 0;
SECTOR5_END_ADDR : integer := 0;
MIN_VALID_ADDR : integer := 0;
MAX_VALID_ADDR : integer := 0;
MIN_UFM_VALID_ADDR : integer := 0;
MAX_UFM_VALID_ADDR : integer := 0;
SECTOR1_MAP : integer := 0;
SECTOR2_MAP : integer := 0;
SECTOR3_MAP : integer := 0;
SECTOR4_MAP : integer := 0;
SECTOR5_MAP : integer := 0;
ADDR_RANGE1_END_ADDR : integer := 0;
ADDR_RANGE1_OFFSET : integer := 0;
ADDR_RANGE2_OFFSET : integer := 0;
AVMM_DATA_ADDR_WIDTH : integer := 19;
AVMM_DATA_DATA_WIDTH : integer := 32;
AVMM_DATA_BURSTCOUNT_WIDTH : integer := 4;
SECTOR_READ_PROTECTION_MODE : integer := 31;
FLASH_SEQ_READ_DATA_COUNT : integer := 2;
FLASH_ADDR_ALIGNMENT_BITS : integer := 1;
FLASH_READ_CYCLE_MAX_INDEX : integer := 4;
FLASH_RESET_CYCLE_MAX_INDEX : integer := 29;
FLASH_BUSY_TIMEOUT_CYCLE_MAX_INDEX : integer := 112;
FLASH_ERASE_TIMEOUT_CYCLE_MAX_INDEX : integer := 40603248;
FLASH_WRITE_TIMEOUT_CYCLE_MAX_INDEX : integer := 35382;
PARALLEL_MODE : boolean := true;
READ_AND_WRITE_MODE : boolean := true;
WRAPPING_BURST_MODE : boolean := false;
IS_DUAL_BOOT : string := "False";
IS_ERAM_SKIP : string := "False";
IS_COMPRESSED_IMAGE : string := "False"
);
port (
clock : in std_logic := 'X'; -- clk
reset_n : in std_logic := 'X'; -- reset_n
avmm_data_addr : in std_logic_vector(15 downto 0) := (others => 'X'); -- address
avmm_data_read : in std_logic := 'X'; -- read
avmm_data_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
avmm_data_write : in std_logic := 'X'; -- write
avmm_data_readdata : out std_logic_vector(31 downto 0); -- readdata
avmm_data_waitrequest : out std_logic; -- waitrequest
avmm_data_readdatavalid : out std_logic; -- readdatavalid
avmm_data_burstcount : in std_logic_vector(3 downto 0) := (others => 'X'); -- burstcount
avmm_csr_addr : in std_logic := 'X'; -- address
avmm_csr_read : in std_logic := 'X'; -- read
avmm_csr_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
avmm_csr_write : in std_logic := 'X'; -- write
avmm_csr_readdata : out std_logic_vector(31 downto 0) -- readdata
);
end component altera_onchip_flash;
component wasca_onchip_memory2_0 is
port (
clk : in std_logic := 'X'; -- clk
address : in std_logic_vector(12 downto 0) := (others => 'X'); -- address
clken : in std_logic := 'X'; -- clken
chipselect : in std_logic := 'X'; -- chipselect
write : in std_logic := 'X'; -- write
readdata : out std_logic_vector(31 downto 0); -- readdata
writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
byteenable : in std_logic_vector(3 downto 0) := (others => 'X'); -- byteenable
reset : in std_logic := 'X'; -- reset
reset_req : in std_logic := 'X' -- reset_req
);
end component wasca_onchip_memory2_0;
component wasca_onchip_memory2_1 is
port (
clk : in std_logic := 'X'; -- clk
address : in std_logic_vector(9 downto 0) := (others => 'X'); -- address
clken : in std_logic := 'X'; -- clken
chipselect : in std_logic := 'X'; -- chipselect
write : in std_logic := 'X'; -- write
readdata : out std_logic_vector(31 downto 0); -- readdata
writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
byteenable : in std_logic_vector(3 downto 0) := (others => 'X'); -- byteenable
reset : in std_logic := 'X'; -- reset
reset_req : in std_logic := 'X' -- reset_req
);
end component wasca_onchip_memory2_1;
component wasca_performance_counter_0 is
port (
clk : in std_logic := 'X'; -- clk
reset_n : in std_logic := 'X'; -- reset_n
address : in std_logic_vector(2 downto 0) := (others => 'X'); -- address
begintransfer : in std_logic := 'X'; -- begintransfer
readdata : out std_logic_vector(31 downto 0); -- readdata
write : in std_logic := 'X'; -- write
writedata : in std_logic_vector(31 downto 0) := (others => 'X') -- writedata
);
end component wasca_performance_counter_0;
component wasca_switches is
port (
clk : in std_logic := 'X'; -- clk
reset_n : in std_logic := 'X'; -- reset_n
address : in std_logic_vector(1 downto 0) := (others => 'X'); -- address
readdata : out std_logic_vector(31 downto 0); -- readdata
in_port : in std_logic_vector(2 downto 0) := (others => 'X') -- export
);
end component wasca_switches;
component wasca_uart_0 is
port (
clk : in std_logic := 'X'; -- clk
reset_n : in std_logic := 'X'; -- reset_n
address : in std_logic_vector(2 downto 0) := (others => 'X'); -- address
begintransfer : in std_logic := 'X'; -- begintransfer
chipselect : in std_logic := 'X'; -- chipselect
read_n : in std_logic := 'X'; -- read_n
write_n : in std_logic := 'X'; -- write_n
writedata : in std_logic_vector(15 downto 0) := (others => 'X'); -- writedata
readdata : out std_logic_vector(15 downto 0); -- readdata
dataavailable : out std_logic; -- dataavailable
readyfordata : out std_logic; -- readyfordata
rxd : in std_logic := 'X'; -- export
txd : out std_logic; -- export
irq : out std_logic -- irq
);
end component wasca_uart_0;
component wasca_mm_interconnect_0 is
port (
altpll_0_c0_clk : in std_logic := 'X'; -- clk
clk_0_clk_clk : in std_logic := 'X'; -- clk
abus_slave_0_reset_reset_bridge_in_reset_reset : in std_logic := 'X'; -- reset
altpll_0_inclk_interface_reset_reset_bridge_in_reset_reset : in std_logic := 'X'; -- reset
abus_slave_0_avalon_master_address : in std_logic_vector(27 downto 0) := (others => 'X'); -- address
abus_slave_0_avalon_master_waitrequest : out std_logic; -- waitrequest
abus_slave_0_avalon_master_burstcount : in std_logic_vector(0 downto 0) := (others => 'X'); -- burstcount
abus_slave_0_avalon_master_read : in std_logic := 'X'; -- read
abus_slave_0_avalon_master_readdata : out std_logic_vector(15 downto 0); -- readdata
abus_slave_0_avalon_master_readdatavalid : out std_logic; -- readdatavalid
abus_slave_0_avalon_master_write : in std_logic := 'X'; -- write
abus_slave_0_avalon_master_writedata : in std_logic_vector(15 downto 0) := (others => 'X'); -- writedata
nios2_gen2_0_data_master_address : in std_logic_vector(26 downto 0) := (others => 'X'); -- address
nios2_gen2_0_data_master_waitrequest : out std_logic; -- waitrequest
nios2_gen2_0_data_master_byteenable : in std_logic_vector(3 downto 0) := (others => 'X'); -- byteenable
nios2_gen2_0_data_master_read : in std_logic := 'X'; -- read
nios2_gen2_0_data_master_readdata : out std_logic_vector(31 downto 0); -- readdata
nios2_gen2_0_data_master_write : in std_logic := 'X'; -- write
nios2_gen2_0_data_master_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
nios2_gen2_0_data_master_debugaccess : in std_logic := 'X'; -- debugaccess
nios2_gen2_0_instruction_master_address : in std_logic_vector(26 downto 0) := (others => 'X'); -- address
nios2_gen2_0_instruction_master_waitrequest : out std_logic; -- waitrequest
nios2_gen2_0_instruction_master_read : in std_logic := 'X'; -- read
nios2_gen2_0_instruction_master_readdata : out std_logic_vector(31 downto 0); -- readdata
abus_demux_0_avalon_nios_address : out std_logic_vector(7 downto 0); -- address
abus_demux_0_avalon_nios_write : out std_logic; -- write
abus_demux_0_avalon_nios_read : out std_logic; -- read
abus_demux_0_avalon_nios_readdata : in std_logic_vector(15 downto 0) := (others => 'X'); -- readdata
abus_demux_0_avalon_nios_writedata : out std_logic_vector(15 downto 0); -- writedata
abus_demux_0_avalon_nios_burstcount : out std_logic_vector(0 downto 0); -- burstcount
abus_demux_0_avalon_nios_readdatavalid : in std_logic := 'X'; -- readdatavalid
abus_demux_0_avalon_nios_waitrequest : in std_logic := 'X'; -- waitrequest
abus_slave_0_avalon_nios_address : out std_logic_vector(7 downto 0); -- address
abus_slave_0_avalon_nios_write : out std_logic; -- write
abus_slave_0_avalon_nios_read : out std_logic; -- read
abus_slave_0_avalon_nios_readdata : in std_logic_vector(15 downto 0) := (others => 'X'); -- readdata
abus_slave_0_avalon_nios_writedata : out std_logic_vector(15 downto 0); -- writedata
abus_slave_0_avalon_nios_burstcount : out std_logic_vector(0 downto 0); -- burstcount
abus_slave_0_avalon_nios_readdatavalid : in std_logic := 'X'; -- readdatavalid
abus_slave_0_avalon_nios_waitrequest : in std_logic := 'X'; -- waitrequest
altpll_0_pll_slave_address : out std_logic_vector(1 downto 0); -- address
altpll_0_pll_slave_write : out std_logic; -- write
altpll_0_pll_slave_read : out std_logic; -- read
altpll_0_pll_slave_readdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
altpll_0_pll_slave_writedata : out std_logic_vector(31 downto 0); -- writedata
external_sdram_controller_s1_address : out std_logic_vector(23 downto 0); -- address
external_sdram_controller_s1_write : out std_logic; -- write
external_sdram_controller_s1_read : out std_logic; -- read
external_sdram_controller_s1_readdata : in std_logic_vector(15 downto 0) := (others => 'X'); -- readdata
external_sdram_controller_s1_writedata : out std_logic_vector(15 downto 0); -- writedata
external_sdram_controller_s1_byteenable : out std_logic_vector(1 downto 0); -- byteenable
external_sdram_controller_s1_readdatavalid : in std_logic := 'X'; -- readdatavalid
external_sdram_controller_s1_waitrequest : in std_logic := 'X'; -- waitrequest
external_sdram_controller_s1_chipselect : out std_logic; -- chipselect
leds_s1_address : out std_logic_vector(1 downto 0); -- address
leds_s1_write : out std_logic; -- write
leds_s1_readdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
leds_s1_writedata : out std_logic_vector(31 downto 0); -- writedata
leds_s1_chipselect : out std_logic; -- chipselect
nios2_gen2_0_debug_mem_slave_address : out std_logic_vector(8 downto 0); -- address
nios2_gen2_0_debug_mem_slave_write : out std_logic; -- write
nios2_gen2_0_debug_mem_slave_read : out std_logic; -- read
nios2_gen2_0_debug_mem_slave_readdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
nios2_gen2_0_debug_mem_slave_writedata : out std_logic_vector(31 downto 0); -- writedata
nios2_gen2_0_debug_mem_slave_byteenable : out std_logic_vector(3 downto 0); -- byteenable
nios2_gen2_0_debug_mem_slave_waitrequest : in std_logic := 'X'; -- waitrequest
nios2_gen2_0_debug_mem_slave_debugaccess : out std_logic; -- debugaccess
onchip_flash_0_csr_address : out std_logic_vector(0 downto 0); -- address
onchip_flash_0_csr_write : out std_logic; -- write
onchip_flash_0_csr_read : out std_logic; -- read
onchip_flash_0_csr_readdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
onchip_flash_0_csr_writedata : out std_logic_vector(31 downto 0); -- writedata
onchip_flash_0_data_address : out std_logic_vector(15 downto 0); -- address
onchip_flash_0_data_write : out std_logic; -- write
onchip_flash_0_data_read : out std_logic; -- read
onchip_flash_0_data_readdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
onchip_flash_0_data_writedata : out std_logic_vector(31 downto 0); -- writedata
onchip_flash_0_data_burstcount : out std_logic_vector(3 downto 0); -- burstcount
onchip_flash_0_data_readdatavalid : in std_logic := 'X'; -- readdatavalid
onchip_flash_0_data_waitrequest : in std_logic := 'X'; -- waitrequest
onchip_memory2_0_s1_address : out std_logic_vector(12 downto 0); -- address
onchip_memory2_0_s1_write : out std_logic; -- write
onchip_memory2_0_s1_readdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
onchip_memory2_0_s1_writedata : out std_logic_vector(31 downto 0); -- writedata
onchip_memory2_0_s1_byteenable : out std_logic_vector(3 downto 0); -- byteenable
onchip_memory2_0_s1_chipselect : out std_logic; -- chipselect
onchip_memory2_0_s1_clken : out std_logic; -- clken
onchip_memory2_1_s1_address : out std_logic_vector(9 downto 0); -- address
onchip_memory2_1_s1_write : out std_logic; -- write
onchip_memory2_1_s1_readdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
onchip_memory2_1_s1_writedata : out std_logic_vector(31 downto 0); -- writedata
onchip_memory2_1_s1_byteenable : out std_logic_vector(3 downto 0); -- byteenable
onchip_memory2_1_s1_chipselect : out std_logic; -- chipselect
onchip_memory2_1_s1_clken : out std_logic; -- clken
performance_counter_0_control_slave_address : out std_logic_vector(2 downto 0); -- address
performance_counter_0_control_slave_write : out std_logic; -- write
performance_counter_0_control_slave_readdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
performance_counter_0_control_slave_writedata : out std_logic_vector(31 downto 0); -- writedata
performance_counter_0_control_slave_begintransfer : out std_logic; -- begintransfer
switches_s1_address : out std_logic_vector(1 downto 0); -- address
switches_s1_readdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
uart_0_s1_address : out std_logic_vector(2 downto 0); -- address
uart_0_s1_write : out std_logic; -- write
uart_0_s1_read : out std_logic; -- read
uart_0_s1_readdata : in std_logic_vector(15 downto 0) := (others => 'X'); -- readdata
uart_0_s1_writedata : out std_logic_vector(15 downto 0); -- writedata
uart_0_s1_begintransfer : out std_logic; -- begintransfer
uart_0_s1_chipselect : out std_logic -- chipselect
);
end component wasca_mm_interconnect_0;
component wasca_irq_mapper is
port (
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
receiver0_irq : in std_logic := 'X'; -- irq
sender_irq : out std_logic_vector(31 downto 0) -- irq
);
end component wasca_irq_mapper;
component wasca_rst_controller is
generic (
NUM_RESET_INPUTS : integer := 6;
OUTPUT_RESET_SYNC_EDGES : string := "deassert";
SYNC_DEPTH : integer := 2;
RESET_REQUEST_PRESENT : integer := 0;
RESET_REQ_WAIT_TIME : integer := 1;
MIN_RST_ASSERTION_TIME : integer := 3;
RESET_REQ_EARLY_DSRT_TIME : integer := 1;
USE_RESET_REQUEST_IN0 : integer := 0;
USE_RESET_REQUEST_IN1 : integer := 0;
USE_RESET_REQUEST_IN2 : integer := 0;
USE_RESET_REQUEST_IN3 : integer := 0;
USE_RESET_REQUEST_IN4 : integer := 0;
USE_RESET_REQUEST_IN5 : integer := 0;
USE_RESET_REQUEST_IN6 : integer := 0;
USE_RESET_REQUEST_IN7 : integer := 0;
USE_RESET_REQUEST_IN8 : integer := 0;
USE_RESET_REQUEST_IN9 : integer := 0;
USE_RESET_REQUEST_IN10 : integer := 0;
USE_RESET_REQUEST_IN11 : integer := 0;
USE_RESET_REQUEST_IN12 : integer := 0;
USE_RESET_REQUEST_IN13 : integer := 0;
USE_RESET_REQUEST_IN14 : integer := 0;
USE_RESET_REQUEST_IN15 : integer := 0;
ADAPT_RESET_REQUEST : integer := 0
);
port (
reset_in0 : in std_logic := 'X'; -- reset
clk : in std_logic := 'X'; -- clk
reset_out : out std_logic; -- reset
reset_req : out std_logic; -- reset_req
reset_req_in0 : in std_logic := 'X'; -- reset_req
reset_in1 : in std_logic := 'X'; -- reset
reset_req_in1 : in std_logic := 'X'; -- reset_req
reset_in2 : in std_logic := 'X'; -- reset
reset_req_in2 : in std_logic := 'X'; -- reset_req
reset_in3 : in std_logic := 'X'; -- reset
reset_req_in3 : in std_logic := 'X'; -- reset_req
reset_in4 : in std_logic := 'X'; -- reset
reset_req_in4 : in std_logic := 'X'; -- reset_req
reset_in5 : in std_logic := 'X'; -- reset
reset_req_in5 : in std_logic := 'X'; -- reset_req
reset_in6 : in std_logic := 'X'; -- reset
reset_req_in6 : in std_logic := 'X'; -- reset_req
reset_in7 : in std_logic := 'X'; -- reset
reset_req_in7 : in std_logic := 'X'; -- reset_req
reset_in8 : in std_logic := 'X'; -- reset
reset_req_in8 : in std_logic := 'X'; -- reset_req
reset_in9 : in std_logic := 'X'; -- reset
reset_req_in9 : in std_logic := 'X'; -- reset_req
reset_in10 : in std_logic := 'X'; -- reset
reset_req_in10 : in std_logic := 'X'; -- reset_req
reset_in11 : in std_logic := 'X'; -- reset
reset_req_in11 : in std_logic := 'X'; -- reset_req
reset_in12 : in std_logic := 'X'; -- reset
reset_req_in12 : in std_logic := 'X'; -- reset_req
reset_in13 : in std_logic := 'X'; -- reset
reset_req_in13 : in std_logic := 'X'; -- reset_req
reset_in14 : in std_logic := 'X'; -- reset
reset_req_in14 : in std_logic := 'X'; -- reset_req
reset_in15 : in std_logic := 'X'; -- reset
reset_req_in15 : in std_logic := 'X' -- reset_req
);
end component wasca_rst_controller;
component wasca_rst_controller_001 is
generic (
NUM_RESET_INPUTS : integer := 6;
OUTPUT_RESET_SYNC_EDGES : string := "deassert";
SYNC_DEPTH : integer := 2;
RESET_REQUEST_PRESENT : integer := 0;
RESET_REQ_WAIT_TIME : integer := 1;
MIN_RST_ASSERTION_TIME : integer := 3;
RESET_REQ_EARLY_DSRT_TIME : integer := 1;
USE_RESET_REQUEST_IN0 : integer := 0;
USE_RESET_REQUEST_IN1 : integer := 0;
USE_RESET_REQUEST_IN2 : integer := 0;
USE_RESET_REQUEST_IN3 : integer := 0;
USE_RESET_REQUEST_IN4 : integer := 0;
USE_RESET_REQUEST_IN5 : integer := 0;
USE_RESET_REQUEST_IN6 : integer := 0;
USE_RESET_REQUEST_IN7 : integer := 0;
USE_RESET_REQUEST_IN8 : integer := 0;
USE_RESET_REQUEST_IN9 : integer := 0;
USE_RESET_REQUEST_IN10 : integer := 0;
USE_RESET_REQUEST_IN11 : integer := 0;
USE_RESET_REQUEST_IN12 : integer := 0;
USE_RESET_REQUEST_IN13 : integer := 0;
USE_RESET_REQUEST_IN14 : integer := 0;
USE_RESET_REQUEST_IN15 : integer := 0;
ADAPT_RESET_REQUEST : integer := 0
);
port (
reset_in0 : in std_logic := 'X'; -- reset
clk : in std_logic := 'X'; -- clk
reset_out : out std_logic; -- reset
reset_req : out std_logic; -- reset_req
reset_req_in0 : in std_logic := 'X'; -- reset_req
reset_in1 : in std_logic := 'X'; -- reset
reset_req_in1 : in std_logic := 'X'; -- reset_req
reset_in2 : in std_logic := 'X'; -- reset
reset_req_in2 : in std_logic := 'X'; -- reset_req
reset_in3 : in std_logic := 'X'; -- reset
reset_req_in3 : in std_logic := 'X'; -- reset_req
reset_in4 : in std_logic := 'X'; -- reset
reset_req_in4 : in std_logic := 'X'; -- reset_req
reset_in5 : in std_logic := 'X'; -- reset
reset_req_in5 : in std_logic := 'X'; -- reset_req
reset_in6 : in std_logic := 'X'; -- reset
reset_req_in6 : in std_logic := 'X'; -- reset_req
reset_in7 : in std_logic := 'X'; -- reset
reset_req_in7 : in std_logic := 'X'; -- reset_req
reset_in8 : in std_logic := 'X'; -- reset
reset_req_in8 : in std_logic := 'X'; -- reset_req
reset_in9 : in std_logic := 'X'; -- reset
reset_req_in9 : in std_logic := 'X'; -- reset_req
reset_in10 : in std_logic := 'X'; -- reset
reset_req_in10 : in std_logic := 'X'; -- reset_req
reset_in11 : in std_logic := 'X'; -- reset
reset_req_in11 : in std_logic := 'X'; -- reset_req
reset_in12 : in std_logic := 'X'; -- reset
reset_req_in12 : in std_logic := 'X'; -- reset_req
reset_in13 : in std_logic := 'X'; -- reset
reset_req_in13 : in std_logic := 'X'; -- reset_req
reset_in14 : in std_logic := 'X'; -- reset
reset_req_in14 : in std_logic := 'X'; -- reset_req
reset_in15 : in std_logic := 'X'; -- reset
reset_req_in15 : in std_logic := 'X' -- reset_req
);
end component wasca_rst_controller_001;
signal altpll_0_c0_clk : std_logic; -- altpll_0:c0 -> [clock_116_mhz_clk, abus_demux_0:clock, abus_slave_0:clock, external_sdram_controller:clk, irq_mapper:clk, leds:clk, mm_interconnect_0:altpll_0_c0_clk, nios2_gen2_0:clk, onchip_flash_0:clock, onchip_memory2_0:clk, onchip_memory2_1:clk, performance_counter_0:clk, rst_controller:clk, rst_controller_002:clk, switches:clk, uart_0:clk]
signal abus_slave_0_demux_readdata : std_logic_vector(15 downto 0); -- abus_slave_0:demux_readdata -> abus_demux_0:demux_readdata
signal abus_demux_0_demux_readpulse : std_logic; -- abus_demux_0:demux_readpulse -> abus_slave_0:demux_readpulse
signal abus_demux_0_demux_readaddress : std_logic_vector(27 downto 0); -- abus_demux_0:demux_readaddress -> abus_slave_0:demux_readaddress
signal abus_demux_0_demux_data : std_logic_vector(15 downto 0); -- abus_demux_0:demux_writedata -> abus_slave_0:demux_writedata
signal abus_slave_0_demux_readdatavalid : std_logic; -- abus_slave_0:demux_readdatavalid -> abus_demux_0:demux_readdatavalid
signal abus_demux_0_demux_write_byteenable : std_logic_vector(1 downto 0); -- abus_demux_0:demux_write_byteenable -> abus_slave_0:demux_write_byteenable
signal abus_demux_0_demux_writeaddress : std_logic_vector(27 downto 0); -- abus_demux_0:demux_writeaddress -> abus_slave_0:demux_writeaddress
signal abus_demux_0_demux_writepulse : std_logic; -- abus_demux_0:demux_writepulse -> abus_slave_0:demux_writepulse
signal nios2_gen2_0_debug_reset_request_reset : std_logic; -- nios2_gen2_0:debug_reset_request -> [rst_controller:reset_in0, rst_controller_001:reset_in0, rst_controller_002:reset_in0]
signal abus_slave_0_avalon_master_waitrequest : std_logic; -- mm_interconnect_0:abus_slave_0_avalon_master_waitrequest -> abus_slave_0:avalon_waitrequest
signal abus_slave_0_avalon_master_readdata : std_logic_vector(15 downto 0); -- mm_interconnect_0:abus_slave_0_avalon_master_readdata -> abus_slave_0:avalon_readdata
signal abus_slave_0_avalon_master_read : std_logic; -- abus_slave_0:avalon_read -> mm_interconnect_0:abus_slave_0_avalon_master_read
signal abus_slave_0_avalon_master_address : std_logic_vector(27 downto 0); -- abus_slave_0:avalon_address -> mm_interconnect_0:abus_slave_0_avalon_master_address
signal abus_slave_0_avalon_master_readdatavalid : std_logic; -- mm_interconnect_0:abus_slave_0_avalon_master_readdatavalid -> abus_slave_0:avalon_readdatavalid
signal abus_slave_0_avalon_master_write : std_logic; -- abus_slave_0:avalon_write -> mm_interconnect_0:abus_slave_0_avalon_master_write
signal abus_slave_0_avalon_master_writedata : std_logic_vector(15 downto 0); -- abus_slave_0:avalon_writedata -> mm_interconnect_0:abus_slave_0_avalon_master_writedata
signal abus_slave_0_avalon_master_burstcount : std_logic; -- abus_slave_0:avalon_burstcount -> mm_interconnect_0:abus_slave_0_avalon_master_burstcount
signal nios2_gen2_0_data_master_readdata : std_logic_vector(31 downto 0); -- mm_interconnect_0:nios2_gen2_0_data_master_readdata -> nios2_gen2_0:d_readdata
signal nios2_gen2_0_data_master_waitrequest : std_logic; -- mm_interconnect_0:nios2_gen2_0_data_master_waitrequest -> nios2_gen2_0:d_waitrequest
signal nios2_gen2_0_data_master_debugaccess : std_logic; -- nios2_gen2_0:debug_mem_slave_debugaccess_to_roms -> mm_interconnect_0:nios2_gen2_0_data_master_debugaccess
signal nios2_gen2_0_data_master_address : std_logic_vector(26 downto 0); -- nios2_gen2_0:d_address -> mm_interconnect_0:nios2_gen2_0_data_master_address
signal nios2_gen2_0_data_master_byteenable : std_logic_vector(3 downto 0); -- nios2_gen2_0:d_byteenable -> mm_interconnect_0:nios2_gen2_0_data_master_byteenable
signal nios2_gen2_0_data_master_read : std_logic; -- nios2_gen2_0:d_read -> mm_interconnect_0:nios2_gen2_0_data_master_read
signal nios2_gen2_0_data_master_write : std_logic; -- nios2_gen2_0:d_write -> mm_interconnect_0:nios2_gen2_0_data_master_write
signal nios2_gen2_0_data_master_writedata : std_logic_vector(31 downto 0); -- nios2_gen2_0:d_writedata -> mm_interconnect_0:nios2_gen2_0_data_master_writedata
signal nios2_gen2_0_instruction_master_readdata : std_logic_vector(31 downto 0); -- mm_interconnect_0:nios2_gen2_0_instruction_master_readdata -> nios2_gen2_0:i_readdata
signal nios2_gen2_0_instruction_master_waitrequest : std_logic; -- mm_interconnect_0:nios2_gen2_0_instruction_master_waitrequest -> nios2_gen2_0:i_waitrequest
signal nios2_gen2_0_instruction_master_address : std_logic_vector(26 downto 0); -- nios2_gen2_0:i_address -> mm_interconnect_0:nios2_gen2_0_instruction_master_address
signal nios2_gen2_0_instruction_master_read : std_logic; -- nios2_gen2_0:i_read -> mm_interconnect_0:nios2_gen2_0_instruction_master_read
signal mm_interconnect_0_external_sdram_controller_s1_chipselect : std_logic; -- mm_interconnect_0:external_sdram_controller_s1_chipselect -> external_sdram_controller:az_cs
signal mm_interconnect_0_external_sdram_controller_s1_readdata : std_logic_vector(15 downto 0); -- external_sdram_controller:za_data -> mm_interconnect_0:external_sdram_controller_s1_readdata
signal mm_interconnect_0_external_sdram_controller_s1_waitrequest : std_logic; -- external_sdram_controller:za_waitrequest -> mm_interconnect_0:external_sdram_controller_s1_waitrequest
signal mm_interconnect_0_external_sdram_controller_s1_address : std_logic_vector(23 downto 0); -- mm_interconnect_0:external_sdram_controller_s1_address -> external_sdram_controller:az_addr
signal mm_interconnect_0_external_sdram_controller_s1_read : std_logic; -- mm_interconnect_0:external_sdram_controller_s1_read -> mm_interconnect_0_external_sdram_controller_s1_read:in
signal mm_interconnect_0_external_sdram_controller_s1_byteenable : std_logic_vector(1 downto 0); -- mm_interconnect_0:external_sdram_controller_s1_byteenable -> mm_interconnect_0_external_sdram_controller_s1_byteenable:in
signal mm_interconnect_0_external_sdram_controller_s1_readdatavalid : std_logic; -- external_sdram_controller:za_valid -> mm_interconnect_0:external_sdram_controller_s1_readdatavalid
signal mm_interconnect_0_external_sdram_controller_s1_write : std_logic; -- mm_interconnect_0:external_sdram_controller_s1_write -> mm_interconnect_0_external_sdram_controller_s1_write:in
signal mm_interconnect_0_external_sdram_controller_s1_writedata : std_logic_vector(15 downto 0); -- mm_interconnect_0:external_sdram_controller_s1_writedata -> external_sdram_controller:az_data
signal mm_interconnect_0_onchip_memory2_1_s1_chipselect : std_logic; -- mm_interconnect_0:onchip_memory2_1_s1_chipselect -> onchip_memory2_1:chipselect
signal mm_interconnect_0_onchip_memory2_1_s1_readdata : std_logic_vector(31 downto 0); -- onchip_memory2_1:readdata -> mm_interconnect_0:onchip_memory2_1_s1_readdata
signal mm_interconnect_0_onchip_memory2_1_s1_address : std_logic_vector(9 downto 0); -- mm_interconnect_0:onchip_memory2_1_s1_address -> onchip_memory2_1:address
signal mm_interconnect_0_onchip_memory2_1_s1_byteenable : std_logic_vector(3 downto 0); -- mm_interconnect_0:onchip_memory2_1_s1_byteenable -> onchip_memory2_1:byteenable
signal mm_interconnect_0_onchip_memory2_1_s1_write : std_logic; -- mm_interconnect_0:onchip_memory2_1_s1_write -> onchip_memory2_1:write
signal mm_interconnect_0_onchip_memory2_1_s1_writedata : std_logic_vector(31 downto 0); -- mm_interconnect_0:onchip_memory2_1_s1_writedata -> onchip_memory2_1:writedata
signal mm_interconnect_0_onchip_memory2_1_s1_clken : std_logic; -- mm_interconnect_0:onchip_memory2_1_s1_clken -> onchip_memory2_1:clken
signal mm_interconnect_0_abus_slave_0_avalon_nios_readdata : std_logic_vector(15 downto 0); -- abus_slave_0:avalon_nios_readdata -> mm_interconnect_0:abus_slave_0_avalon_nios_readdata
signal mm_interconnect_0_abus_slave_0_avalon_nios_waitrequest : std_logic; -- abus_slave_0:avalon_nios_waitrequest -> mm_interconnect_0:abus_slave_0_avalon_nios_waitrequest
signal mm_interconnect_0_abus_slave_0_avalon_nios_address : std_logic_vector(7 downto 0); -- mm_interconnect_0:abus_slave_0_avalon_nios_address -> abus_slave_0:avalon_nios_address
signal mm_interconnect_0_abus_slave_0_avalon_nios_read : std_logic; -- mm_interconnect_0:abus_slave_0_avalon_nios_read -> abus_slave_0:avalon_nios_read
signal mm_interconnect_0_abus_slave_0_avalon_nios_readdatavalid : std_logic; -- abus_slave_0:avalon_nios_readdatavalid -> mm_interconnect_0:abus_slave_0_avalon_nios_readdatavalid
signal mm_interconnect_0_abus_slave_0_avalon_nios_write : std_logic; -- mm_interconnect_0:abus_slave_0_avalon_nios_write -> abus_slave_0:avalon_nios_write
signal mm_interconnect_0_abus_slave_0_avalon_nios_writedata : std_logic_vector(15 downto 0); -- mm_interconnect_0:abus_slave_0_avalon_nios_writedata -> abus_slave_0:avalon_nios_writedata
signal mm_interconnect_0_abus_slave_0_avalon_nios_burstcount : std_logic_vector(0 downto 0); -- mm_interconnect_0:abus_slave_0_avalon_nios_burstcount -> abus_slave_0:avalon_nios_burstcount
signal mm_interconnect_0_abus_demux_0_avalon_nios_readdata : std_logic_vector(15 downto 0); -- abus_demux_0:avalon_nios_readdata -> mm_interconnect_0:abus_demux_0_avalon_nios_readdata
signal mm_interconnect_0_abus_demux_0_avalon_nios_waitrequest : std_logic; -- abus_demux_0:avalon_nios_waitrequest -> mm_interconnect_0:abus_demux_0_avalon_nios_waitrequest
signal mm_interconnect_0_abus_demux_0_avalon_nios_address : std_logic_vector(7 downto 0); -- mm_interconnect_0:abus_demux_0_avalon_nios_address -> abus_demux_0:avalon_nios_address
signal mm_interconnect_0_abus_demux_0_avalon_nios_read : std_logic; -- mm_interconnect_0:abus_demux_0_avalon_nios_read -> abus_demux_0:avalon_nios_read
signal mm_interconnect_0_abus_demux_0_avalon_nios_readdatavalid : std_logic; -- abus_demux_0:avalon_nios_readdatavalid -> mm_interconnect_0:abus_demux_0_avalon_nios_readdatavalid
signal mm_interconnect_0_abus_demux_0_avalon_nios_write : std_logic; -- mm_interconnect_0:abus_demux_0_avalon_nios_write -> abus_demux_0:avalon_nios_write
signal mm_interconnect_0_abus_demux_0_avalon_nios_writedata : std_logic_vector(15 downto 0); -- mm_interconnect_0:abus_demux_0_avalon_nios_writedata -> abus_demux_0:avalon_nios_writedata
signal mm_interconnect_0_abus_demux_0_avalon_nios_burstcount : std_logic_vector(0 downto 0); -- mm_interconnect_0:abus_demux_0_avalon_nios_burstcount -> abus_demux_0:avalon_nios_burstcount
signal mm_interconnect_0_onchip_flash_0_csr_readdata : std_logic_vector(31 downto 0); -- onchip_flash_0:avmm_csr_readdata -> mm_interconnect_0:onchip_flash_0_csr_readdata
signal mm_interconnect_0_onchip_flash_0_csr_address : std_logic_vector(0 downto 0); -- mm_interconnect_0:onchip_flash_0_csr_address -> onchip_flash_0:avmm_csr_addr
signal mm_interconnect_0_onchip_flash_0_csr_read : std_logic; -- mm_interconnect_0:onchip_flash_0_csr_read -> onchip_flash_0:avmm_csr_read
signal mm_interconnect_0_onchip_flash_0_csr_write : std_logic; -- mm_interconnect_0:onchip_flash_0_csr_write -> onchip_flash_0:avmm_csr_write
signal mm_interconnect_0_onchip_flash_0_csr_writedata : std_logic_vector(31 downto 0); -- mm_interconnect_0:onchip_flash_0_csr_writedata -> onchip_flash_0:avmm_csr_writedata
signal mm_interconnect_0_onchip_flash_0_data_readdata : std_logic_vector(31 downto 0); -- onchip_flash_0:avmm_data_readdata -> mm_interconnect_0:onchip_flash_0_data_readdata
signal mm_interconnect_0_onchip_flash_0_data_waitrequest : std_logic; -- onchip_flash_0:avmm_data_waitrequest -> mm_interconnect_0:onchip_flash_0_data_waitrequest
signal mm_interconnect_0_onchip_flash_0_data_address : std_logic_vector(15 downto 0); -- mm_interconnect_0:onchip_flash_0_data_address -> onchip_flash_0:avmm_data_addr
signal mm_interconnect_0_onchip_flash_0_data_read : std_logic; -- mm_interconnect_0:onchip_flash_0_data_read -> onchip_flash_0:avmm_data_read
signal mm_interconnect_0_onchip_flash_0_data_readdatavalid : std_logic; -- onchip_flash_0:avmm_data_readdatavalid -> mm_interconnect_0:onchip_flash_0_data_readdatavalid
signal mm_interconnect_0_onchip_flash_0_data_write : std_logic; -- mm_interconnect_0:onchip_flash_0_data_write -> onchip_flash_0:avmm_data_write
signal mm_interconnect_0_onchip_flash_0_data_writedata : std_logic_vector(31 downto 0); -- mm_interconnect_0:onchip_flash_0_data_writedata -> onchip_flash_0:avmm_data_writedata
signal mm_interconnect_0_onchip_flash_0_data_burstcount : std_logic_vector(3 downto 0); -- mm_interconnect_0:onchip_flash_0_data_burstcount -> onchip_flash_0:avmm_data_burstcount
signal mm_interconnect_0_nios2_gen2_0_debug_mem_slave_readdata : std_logic_vector(31 downto 0); -- nios2_gen2_0:debug_mem_slave_readdata -> mm_interconnect_0:nios2_gen2_0_debug_mem_slave_readdata
signal mm_interconnect_0_nios2_gen2_0_debug_mem_slave_waitrequest : std_logic; -- nios2_gen2_0:debug_mem_slave_waitrequest -> mm_interconnect_0:nios2_gen2_0_debug_mem_slave_waitrequest
signal mm_interconnect_0_nios2_gen2_0_debug_mem_slave_debugaccess : std_logic; -- mm_interconnect_0:nios2_gen2_0_debug_mem_slave_debugaccess -> nios2_gen2_0:debug_mem_slave_debugaccess
signal mm_interconnect_0_nios2_gen2_0_debug_mem_slave_address : std_logic_vector(8 downto 0); -- mm_interconnect_0:nios2_gen2_0_debug_mem_slave_address -> nios2_gen2_0:debug_mem_slave_address
signal mm_interconnect_0_nios2_gen2_0_debug_mem_slave_read : std_logic; -- mm_interconnect_0:nios2_gen2_0_debug_mem_slave_read -> nios2_gen2_0:debug_mem_slave_read
signal mm_interconnect_0_nios2_gen2_0_debug_mem_slave_byteenable : std_logic_vector(3 downto 0); -- mm_interconnect_0:nios2_gen2_0_debug_mem_slave_byteenable -> nios2_gen2_0:debug_mem_slave_byteenable
signal mm_interconnect_0_nios2_gen2_0_debug_mem_slave_write : std_logic; -- mm_interconnect_0:nios2_gen2_0_debug_mem_slave_write -> nios2_gen2_0:debug_mem_slave_write
signal mm_interconnect_0_nios2_gen2_0_debug_mem_slave_writedata : std_logic_vector(31 downto 0); -- mm_interconnect_0:nios2_gen2_0_debug_mem_slave_writedata -> nios2_gen2_0:debug_mem_slave_writedata
signal mm_interconnect_0_onchip_memory2_0_s1_chipselect : std_logic; -- mm_interconnect_0:onchip_memory2_0_s1_chipselect -> onchip_memory2_0:chipselect
signal mm_interconnect_0_onchip_memory2_0_s1_readdata : std_logic_vector(31 downto 0); -- onchip_memory2_0:readdata -> mm_interconnect_0:onchip_memory2_0_s1_readdata
signal mm_interconnect_0_onchip_memory2_0_s1_address : std_logic_vector(12 downto 0); -- mm_interconnect_0:onchip_memory2_0_s1_address -> onchip_memory2_0:address
signal mm_interconnect_0_onchip_memory2_0_s1_byteenable : std_logic_vector(3 downto 0); -- mm_interconnect_0:onchip_memory2_0_s1_byteenable -> onchip_memory2_0:byteenable
signal mm_interconnect_0_onchip_memory2_0_s1_write : std_logic; -- mm_interconnect_0:onchip_memory2_0_s1_write -> onchip_memory2_0:write
signal mm_interconnect_0_onchip_memory2_0_s1_writedata : std_logic_vector(31 downto 0); -- mm_interconnect_0:onchip_memory2_0_s1_writedata -> onchip_memory2_0:writedata
signal mm_interconnect_0_onchip_memory2_0_s1_clken : std_logic; -- mm_interconnect_0:onchip_memory2_0_s1_clken -> onchip_memory2_0:clken
signal mm_interconnect_0_performance_counter_0_control_slave_readdata : std_logic_vector(31 downto 0); -- performance_counter_0:readdata -> mm_interconnect_0:performance_counter_0_control_slave_readdata
signal mm_interconnect_0_performance_counter_0_control_slave_address : std_logic_vector(2 downto 0); -- mm_interconnect_0:performance_counter_0_control_slave_address -> performance_counter_0:address
signal mm_interconnect_0_performance_counter_0_control_slave_begintransfer : std_logic; -- mm_interconnect_0:performance_counter_0_control_slave_begintransfer -> performance_counter_0:begintransfer
signal mm_interconnect_0_performance_counter_0_control_slave_write : std_logic; -- mm_interconnect_0:performance_counter_0_control_slave_write -> performance_counter_0:write
signal mm_interconnect_0_performance_counter_0_control_slave_writedata : std_logic_vector(31 downto 0); -- mm_interconnect_0:performance_counter_0_control_slave_writedata -> performance_counter_0:writedata
signal mm_interconnect_0_altpll_0_pll_slave_readdata : std_logic_vector(31 downto 0); -- altpll_0:readdata -> mm_interconnect_0:altpll_0_pll_slave_readdata
signal mm_interconnect_0_altpll_0_pll_slave_address : std_logic_vector(1 downto 0); -- mm_interconnect_0:altpll_0_pll_slave_address -> altpll_0:address
signal mm_interconnect_0_altpll_0_pll_slave_read : std_logic; -- mm_interconnect_0:altpll_0_pll_slave_read -> altpll_0:read
signal mm_interconnect_0_altpll_0_pll_slave_write : std_logic; -- mm_interconnect_0:altpll_0_pll_slave_write -> altpll_0:write
signal mm_interconnect_0_altpll_0_pll_slave_writedata : std_logic_vector(31 downto 0); -- mm_interconnect_0:altpll_0_pll_slave_writedata -> altpll_0:writedata
signal mm_interconnect_0_switches_s1_readdata : std_logic_vector(31 downto 0); -- switches:readdata -> mm_interconnect_0:switches_s1_readdata
signal mm_interconnect_0_switches_s1_address : std_logic_vector(1 downto 0); -- mm_interconnect_0:switches_s1_address -> switches:address
signal mm_interconnect_0_leds_s1_chipselect : std_logic; -- mm_interconnect_0:leds_s1_chipselect -> leds:chipselect
signal mm_interconnect_0_leds_s1_readdata : std_logic_vector(31 downto 0); -- leds:readdata -> mm_interconnect_0:leds_s1_readdata
signal mm_interconnect_0_leds_s1_address : std_logic_vector(1 downto 0); -- mm_interconnect_0:leds_s1_address -> leds:address
signal mm_interconnect_0_leds_s1_write : std_logic; -- mm_interconnect_0:leds_s1_write -> mm_interconnect_0_leds_s1_write:in
signal mm_interconnect_0_leds_s1_writedata : std_logic_vector(31 downto 0); -- mm_interconnect_0:leds_s1_writedata -> leds:writedata
signal mm_interconnect_0_uart_0_s1_chipselect : std_logic; -- mm_interconnect_0:uart_0_s1_chipselect -> uart_0:chipselect
signal mm_interconnect_0_uart_0_s1_readdata : std_logic_vector(15 downto 0); -- uart_0:readdata -> mm_interconnect_0:uart_0_s1_readdata
signal mm_interconnect_0_uart_0_s1_address : std_logic_vector(2 downto 0); -- mm_interconnect_0:uart_0_s1_address -> uart_0:address
signal mm_interconnect_0_uart_0_s1_read : std_logic; -- mm_interconnect_0:uart_0_s1_read -> mm_interconnect_0_uart_0_s1_read:in
signal mm_interconnect_0_uart_0_s1_begintransfer : std_logic; -- mm_interconnect_0:uart_0_s1_begintransfer -> uart_0:begintransfer
signal mm_interconnect_0_uart_0_s1_write : std_logic; -- mm_interconnect_0:uart_0_s1_write -> mm_interconnect_0_uart_0_s1_write:in
signal mm_interconnect_0_uart_0_s1_writedata : std_logic_vector(15 downto 0); -- mm_interconnect_0:uart_0_s1_writedata -> uart_0:writedata
signal irq_mapper_receiver0_irq : std_logic; -- uart_0:irq -> irq_mapper:receiver0_irq
signal nios2_gen2_0_irq_irq : std_logic_vector(31 downto 0); -- irq_mapper:sender_irq -> nios2_gen2_0:irq
signal rst_controller_reset_out_reset : std_logic; -- rst_controller:reset_out -> [abus_demux_0:reset, abus_slave_0:reset, irq_mapper:reset, mm_interconnect_0:abus_slave_0_reset_reset_bridge_in_reset_reset, onchip_memory2_0:reset, onchip_memory2_1:reset, rst_controller_reset_out_reset:in, rst_translator:in_reset]
signal rst_controller_reset_out_reset_req : std_logic; -- rst_controller:reset_req -> [onchip_memory2_0:reset_req, onchip_memory2_1:reset_req, rst_translator:reset_req_in]
signal rst_controller_001_reset_out_reset : std_logic; -- rst_controller_001:reset_out -> [altpll_0:reset, mm_interconnect_0:altpll_0_inclk_interface_reset_reset_bridge_in_reset_reset]
signal mm_interconnect_0_external_sdram_controller_s1_read_ports_inv : std_logic; -- mm_interconnect_0_external_sdram_controller_s1_read:inv -> external_sdram_controller:az_rd_n
signal mm_interconnect_0_external_sdram_controller_s1_byteenable_ports_inv : std_logic_vector(1 downto 0); -- mm_interconnect_0_external_sdram_controller_s1_byteenable:inv -> external_sdram_controller:az_be_n
signal mm_interconnect_0_external_sdram_controller_s1_write_ports_inv : std_logic; -- mm_interconnect_0_external_sdram_controller_s1_write:inv -> external_sdram_controller:az_wr_n
signal mm_interconnect_0_leds_s1_write_ports_inv : std_logic; -- mm_interconnect_0_leds_s1_write:inv -> leds:write_n
signal mm_interconnect_0_uart_0_s1_read_ports_inv : std_logic; -- mm_interconnect_0_uart_0_s1_read:inv -> uart_0:read_n
signal mm_interconnect_0_uart_0_s1_write_ports_inv : std_logic; -- mm_interconnect_0_uart_0_s1_write:inv -> uart_0:write_n
signal rst_controller_reset_out_reset_ports_inv : std_logic; -- rst_controller_reset_out_reset:inv -> [external_sdram_controller:reset_n, leds:reset_n, nios2_gen2_0:reset_n, onchip_flash_0:reset_n, performance_counter_0:reset_n, switches:reset_n, uart_0:reset_n]
begin
abus_demux_0 : component abus_demux
port map (
clock => altpll_0_c0_clk, -- clock.clk
abus_address => abus_slave_0_abus_address, -- abus.address
abus_chipselect => abus_slave_0_abus_chipselect, -- .chipselect
abus_read => abus_slave_0_abus_read, -- .read
abus_write => abus_slave_0_abus_write, -- .write
abus_waitrequest => abus_slave_0_abus_waitrequest, -- .waitrequest
abus_interrupt => abus_slave_0_abus_interrupt, -- .interrupt
abus_addressdata => abus_slave_0_abus_addressdata, -- .addressdata
abus_direction => abus_slave_0_abus_direction, -- .direction
abus_muxing => abus_slave_0_abus_muxing, -- .muxing
abus_disable_out => abus_slave_0_abus_disableout, -- .disableout
reset => rst_controller_reset_out_reset, -- reset.reset
avalon_nios_read => mm_interconnect_0_abus_demux_0_avalon_nios_read, -- avalon_nios.read
avalon_nios_write => mm_interconnect_0_abus_demux_0_avalon_nios_write, -- .write
avalon_nios_address => mm_interconnect_0_abus_demux_0_avalon_nios_address, -- .address
avalon_nios_writedata => mm_interconnect_0_abus_demux_0_avalon_nios_writedata, -- .writedata
avalon_nios_readdata => mm_interconnect_0_abus_demux_0_avalon_nios_readdata, -- .readdata
avalon_nios_waitrequest => mm_interconnect_0_abus_demux_0_avalon_nios_waitrequest, -- .waitrequest
avalon_nios_readdatavalid => mm_interconnect_0_abus_demux_0_avalon_nios_readdatavalid, -- .readdatavalid
avalon_nios_burstcount => mm_interconnect_0_abus_demux_0_avalon_nios_burstcount(0), -- .burstcount
demux_writeaddress => abus_demux_0_demux_writeaddress, -- demux.writeaddress
demux_writedata => abus_demux_0_demux_data, -- .data
demux_writepulse => abus_demux_0_demux_writepulse, -- .writepulse
demux_write_byteenable => abus_demux_0_demux_write_byteenable, -- .write_byteenable
demux_readdata => abus_slave_0_demux_readdata, -- .readdata
demux_readpulse => abus_demux_0_demux_readpulse, -- .readpulse
demux_readdatavalid => abus_slave_0_demux_readdatavalid, -- .readdatavalid
demux_readaddress => abus_demux_0_demux_readaddress, -- .readaddress
saturn_reset => abus_slave_0_conduit_saturn_reset_saturn_reset -- conduit_saturn_reset.saturn_reset
);
abus_slave_0 : component abus_slave
port map (
clock => altpll_0_c0_clk, -- clock.clk
avalon_read => abus_slave_0_avalon_master_read, -- avalon_master.read
avalon_write => abus_slave_0_avalon_master_write, -- .write
avalon_waitrequest => abus_slave_0_avalon_master_waitrequest, -- .waitrequest
avalon_address => abus_slave_0_avalon_master_address, -- .address
avalon_readdata => abus_slave_0_avalon_master_readdata, -- .readdata
avalon_writedata => abus_slave_0_avalon_master_writedata, -- .writedata
avalon_readdatavalid => abus_slave_0_avalon_master_readdatavalid, -- .readdatavalid
avalon_burstcount => abus_slave_0_avalon_master_burstcount, -- .burstcount
reset => rst_controller_reset_out_reset, -- reset.reset
avalon_nios_read => mm_interconnect_0_abus_slave_0_avalon_nios_read, -- avalon_nios.read
avalon_nios_write => mm_interconnect_0_abus_slave_0_avalon_nios_write, -- .write
avalon_nios_address => mm_interconnect_0_abus_slave_0_avalon_nios_address, -- .address
avalon_nios_writedata => mm_interconnect_0_abus_slave_0_avalon_nios_writedata, -- .writedata
avalon_nios_readdata => mm_interconnect_0_abus_slave_0_avalon_nios_readdata, -- .readdata
avalon_nios_waitrequest => mm_interconnect_0_abus_slave_0_avalon_nios_waitrequest, -- .waitrequest
avalon_nios_readdatavalid => mm_interconnect_0_abus_slave_0_avalon_nios_readdatavalid, -- .readdatavalid
avalon_nios_burstcount => mm_interconnect_0_abus_slave_0_avalon_nios_burstcount(0), -- .burstcount
demux_writeaddress => abus_demux_0_demux_writeaddress, -- demux.writeaddress
demux_writedata => abus_demux_0_demux_data, -- .data
demux_writepulse => abus_demux_0_demux_writepulse, -- .writepulse
demux_write_byteenable => abus_demux_0_demux_write_byteenable, -- .write_byteenable
demux_readdata => abus_slave_0_demux_readdata, -- .readdata
demux_readpulse => abus_demux_0_demux_readpulse, -- .readpulse
demux_readdatavalid => abus_slave_0_demux_readdatavalid, -- .readdatavalid
demux_readaddress => abus_demux_0_demux_readaddress -- .readaddress
);
altpll_0 : component wasca_altpll_0
port map (
clk => clk_clk, -- inclk_interface.clk
reset => rst_controller_001_reset_out_reset, -- inclk_interface_reset.reset
read => mm_interconnect_0_altpll_0_pll_slave_read, -- pll_slave.read
write => mm_interconnect_0_altpll_0_pll_slave_write, -- .write
address => mm_interconnect_0_altpll_0_pll_slave_address, -- .address
readdata => mm_interconnect_0_altpll_0_pll_slave_readdata, -- .readdata
writedata => mm_interconnect_0_altpll_0_pll_slave_writedata, -- .writedata
c0 => altpll_0_c0_clk, -- c0.clk
c1 => sdram_clkout_clk, -- c1.clk
areset => altpll_0_areset_conduit_export, -- areset_conduit.export
locked => altpll_0_locked_conduit_export, -- locked_conduit.export
phasedone => altpll_0_phasedone_conduit_export -- phasedone_conduit.export
);
external_sdram_controller : component wasca_external_sdram_controller
port map (
clk => altpll_0_c0_clk, -- clk.clk
reset_n => rst_controller_reset_out_reset_ports_inv, -- reset.reset_n
az_addr => mm_interconnect_0_external_sdram_controller_s1_address, -- s1.address
az_be_n => mm_interconnect_0_external_sdram_controller_s1_byteenable_ports_inv, -- .byteenable_n
az_cs => mm_interconnect_0_external_sdram_controller_s1_chipselect, -- .chipselect
az_data => mm_interconnect_0_external_sdram_controller_s1_writedata, -- .writedata
az_rd_n => mm_interconnect_0_external_sdram_controller_s1_read_ports_inv, -- .read_n
az_wr_n => mm_interconnect_0_external_sdram_controller_s1_write_ports_inv, -- .write_n
za_data => mm_interconnect_0_external_sdram_controller_s1_readdata, -- .readdata
za_valid => mm_interconnect_0_external_sdram_controller_s1_readdatavalid, -- .readdatavalid
za_waitrequest => mm_interconnect_0_external_sdram_controller_s1_waitrequest, -- .waitrequest
zs_addr => external_sdram_controller_wire_addr, -- wire.export
zs_ba => external_sdram_controller_wire_ba, -- .export
zs_cas_n => external_sdram_controller_wire_cas_n, -- .export
zs_cke => external_sdram_controller_wire_cke, -- .export
zs_cs_n => external_sdram_controller_wire_cs_n, -- .export
zs_dq => external_sdram_controller_wire_dq, -- .export
zs_dqm => external_sdram_controller_wire_dqm, -- .export
zs_ras_n => external_sdram_controller_wire_ras_n, -- .export
zs_we_n => external_sdram_controller_wire_we_n -- .export
);
leds : component wasca_leds
port map (
clk => altpll_0_c0_clk, -- clk.clk
reset_n => rst_controller_reset_out_reset_ports_inv, -- reset.reset_n
address => mm_interconnect_0_leds_s1_address, -- s1.address
write_n => mm_interconnect_0_leds_s1_write_ports_inv, -- .write_n
writedata => mm_interconnect_0_leds_s1_writedata, -- .writedata
chipselect => mm_interconnect_0_leds_s1_chipselect, -- .chipselect
readdata => mm_interconnect_0_leds_s1_readdata, -- .readdata
out_port => leds_conn_export -- external_connection.export
);
nios2_gen2_0 : component wasca_nios2_gen2_0
port map (
clk => altpll_0_c0_clk, -- clk.clk
reset_n => rst_controller_reset_out_reset_ports_inv, -- reset.reset_n
d_address => nios2_gen2_0_data_master_address, -- data_master.address
d_byteenable => nios2_gen2_0_data_master_byteenable, -- .byteenable
d_read => nios2_gen2_0_data_master_read, -- .read
d_readdata => nios2_gen2_0_data_master_readdata, -- .readdata
d_waitrequest => nios2_gen2_0_data_master_waitrequest, -- .waitrequest
d_write => nios2_gen2_0_data_master_write, -- .write
d_writedata => nios2_gen2_0_data_master_writedata, -- .writedata
debug_mem_slave_debugaccess_to_roms => nios2_gen2_0_data_master_debugaccess, -- .debugaccess
i_address => nios2_gen2_0_instruction_master_address, -- instruction_master.address
i_read => nios2_gen2_0_instruction_master_read, -- .read
i_readdata => nios2_gen2_0_instruction_master_readdata, -- .readdata
i_waitrequest => nios2_gen2_0_instruction_master_waitrequest, -- .waitrequest
irq => nios2_gen2_0_irq_irq, -- irq.irq
debug_reset_request => nios2_gen2_0_debug_reset_request_reset, -- debug_reset_request.reset
debug_mem_slave_address => mm_interconnect_0_nios2_gen2_0_debug_mem_slave_address, -- debug_mem_slave.address
debug_mem_slave_byteenable => mm_interconnect_0_nios2_gen2_0_debug_mem_slave_byteenable, -- .byteenable
debug_mem_slave_debugaccess => mm_interconnect_0_nios2_gen2_0_debug_mem_slave_debugaccess, -- .debugaccess
debug_mem_slave_read => mm_interconnect_0_nios2_gen2_0_debug_mem_slave_read, -- .read
debug_mem_slave_readdata => mm_interconnect_0_nios2_gen2_0_debug_mem_slave_readdata, -- .readdata
debug_mem_slave_waitrequest => mm_interconnect_0_nios2_gen2_0_debug_mem_slave_waitrequest, -- .waitrequest
debug_mem_slave_write => mm_interconnect_0_nios2_gen2_0_debug_mem_slave_write, -- .write
debug_mem_slave_writedata => mm_interconnect_0_nios2_gen2_0_debug_mem_slave_writedata, -- .writedata
dummy_ci_port => open -- custom_instruction_master.readra
);
onchip_flash_0 : component altera_onchip_flash
generic map (
INIT_FILENAME => "",
INIT_FILENAME_SIM => "",
DEVICE_FAMILY => "MAX 10",
PART_NAME => "10M08SCE144C8G",
DEVICE_ID => "08",
SECTOR1_START_ADDR => 0,
SECTOR1_END_ADDR => 4095,
SECTOR2_START_ADDR => 4096,
SECTOR2_END_ADDR => 8191,
SECTOR3_START_ADDR => 8192,
SECTOR3_END_ADDR => 23039,
SECTOR4_START_ADDR => 23040,
SECTOR4_END_ADDR => 58879,
SECTOR5_START_ADDR => 0,
SECTOR5_END_ADDR => 0,
MIN_VALID_ADDR => 0,
MAX_VALID_ADDR => 58879,
MIN_UFM_VALID_ADDR => 0,
MAX_UFM_VALID_ADDR => 8191,
SECTOR1_MAP => 1,
SECTOR2_MAP => 2,
SECTOR3_MAP => 4,
SECTOR4_MAP => 5,
SECTOR5_MAP => 0,
ADDR_RANGE1_END_ADDR => 8191,
ADDR_RANGE1_OFFSET => 512,
ADDR_RANGE2_OFFSET => 21504,
AVMM_DATA_ADDR_WIDTH => 16,
AVMM_DATA_DATA_WIDTH => 32,
AVMM_DATA_BURSTCOUNT_WIDTH => 4,
SECTOR_READ_PROTECTION_MODE => 16,
FLASH_SEQ_READ_DATA_COUNT => 2,
FLASH_ADDR_ALIGNMENT_BITS => 1,
FLASH_READ_CYCLE_MAX_INDEX => 4,
FLASH_RESET_CYCLE_MAX_INDEX => 28,
FLASH_BUSY_TIMEOUT_CYCLE_MAX_INDEX => 135,
FLASH_ERASE_TIMEOUT_CYCLE_MAX_INDEX => 39516766,
FLASH_WRITE_TIMEOUT_CYCLE_MAX_INDEX => 34436,
PARALLEL_MODE => true,
READ_AND_WRITE_MODE => true,
WRAPPING_BURST_MODE => false,
IS_DUAL_BOOT => "False",
IS_ERAM_SKIP => "True",
IS_COMPRESSED_IMAGE => "False"
)
port map (
clock => altpll_0_c0_clk, -- clk.clk
reset_n => rst_controller_reset_out_reset_ports_inv, -- nreset.reset_n
avmm_data_addr => mm_interconnect_0_onchip_flash_0_data_address, -- data.address
avmm_data_read => mm_interconnect_0_onchip_flash_0_data_read, -- .read
avmm_data_writedata => mm_interconnect_0_onchip_flash_0_data_writedata, -- .writedata
avmm_data_write => mm_interconnect_0_onchip_flash_0_data_write, -- .write
avmm_data_readdata => mm_interconnect_0_onchip_flash_0_data_readdata, -- .readdata
avmm_data_waitrequest => mm_interconnect_0_onchip_flash_0_data_waitrequest, -- .waitrequest
avmm_data_readdatavalid => mm_interconnect_0_onchip_flash_0_data_readdatavalid, -- .readdatavalid
avmm_data_burstcount => mm_interconnect_0_onchip_flash_0_data_burstcount, -- .burstcount
avmm_csr_addr => mm_interconnect_0_onchip_flash_0_csr_address(0), -- csr.address
avmm_csr_read => mm_interconnect_0_onchip_flash_0_csr_read, -- .read
avmm_csr_writedata => mm_interconnect_0_onchip_flash_0_csr_writedata, -- .writedata
avmm_csr_write => mm_interconnect_0_onchip_flash_0_csr_write, -- .write
avmm_csr_readdata => mm_interconnect_0_onchip_flash_0_csr_readdata -- .readdata
);
onchip_memory2_0 : component wasca_onchip_memory2_0
port map (
clk => altpll_0_c0_clk, -- clk1.clk
address => mm_interconnect_0_onchip_memory2_0_s1_address, -- s1.address
clken => mm_interconnect_0_onchip_memory2_0_s1_clken, -- .clken
chipselect => mm_interconnect_0_onchip_memory2_0_s1_chipselect, -- .chipselect
write => mm_interconnect_0_onchip_memory2_0_s1_write, -- .write
readdata => mm_interconnect_0_onchip_memory2_0_s1_readdata, -- .readdata
writedata => mm_interconnect_0_onchip_memory2_0_s1_writedata, -- .writedata
byteenable => mm_interconnect_0_onchip_memory2_0_s1_byteenable, -- .byteenable
reset => rst_controller_reset_out_reset, -- reset1.reset
reset_req => rst_controller_reset_out_reset_req -- .reset_req
);
onchip_memory2_1 : component wasca_onchip_memory2_1
port map (
clk => altpll_0_c0_clk, -- clk1.clk
address => mm_interconnect_0_onchip_memory2_1_s1_address, -- s1.address
clken => mm_interconnect_0_onchip_memory2_1_s1_clken, -- .clken
chipselect => mm_interconnect_0_onchip_memory2_1_s1_chipselect, -- .chipselect
write => mm_interconnect_0_onchip_memory2_1_s1_write, -- .write
readdata => mm_interconnect_0_onchip_memory2_1_s1_readdata, -- .readdata
writedata => mm_interconnect_0_onchip_memory2_1_s1_writedata, -- .writedata
byteenable => mm_interconnect_0_onchip_memory2_1_s1_byteenable, -- .byteenable
reset => rst_controller_reset_out_reset, -- reset1.reset
reset_req => rst_controller_reset_out_reset_req -- .reset_req
);
performance_counter_0 : component wasca_performance_counter_0
port map (
clk => altpll_0_c0_clk, -- clk.clk
reset_n => rst_controller_reset_out_reset_ports_inv, -- reset.reset_n
address => mm_interconnect_0_performance_counter_0_control_slave_address, -- control_slave.address
begintransfer => mm_interconnect_0_performance_counter_0_control_slave_begintransfer, -- .begintransfer
readdata => mm_interconnect_0_performance_counter_0_control_slave_readdata, -- .readdata
write => mm_interconnect_0_performance_counter_0_control_slave_write, -- .write
writedata => mm_interconnect_0_performance_counter_0_control_slave_writedata -- .writedata
);
switches : component wasca_switches
port map (
clk => altpll_0_c0_clk, -- clk.clk
reset_n => rst_controller_reset_out_reset_ports_inv, -- reset.reset_n
address => mm_interconnect_0_switches_s1_address, -- s1.address
readdata => mm_interconnect_0_switches_s1_readdata, -- .readdata
in_port => switches_conn_export -- external_connection.export
);
uart_0 : component wasca_uart_0
port map (
clk => altpll_0_c0_clk, -- clk.clk
reset_n => rst_controller_reset_out_reset_ports_inv, -- reset.reset_n
address => mm_interconnect_0_uart_0_s1_address, -- s1.address
begintransfer => mm_interconnect_0_uart_0_s1_begintransfer, -- .begintransfer
chipselect => mm_interconnect_0_uart_0_s1_chipselect, -- .chipselect
read_n => mm_interconnect_0_uart_0_s1_read_ports_inv, -- .read_n
write_n => mm_interconnect_0_uart_0_s1_write_ports_inv, -- .write_n
writedata => mm_interconnect_0_uart_0_s1_writedata, -- .writedata
readdata => mm_interconnect_0_uart_0_s1_readdata, -- .readdata
dataavailable => open, -- .dataavailable
readyfordata => open, -- .readyfordata
rxd => uart_0_external_connection_rxd, -- external_connection.export
txd => uart_0_external_connection_txd, -- .export
irq => irq_mapper_receiver0_irq -- irq.irq
);
mm_interconnect_0 : component wasca_mm_interconnect_0
port map (
altpll_0_c0_clk => altpll_0_c0_clk, -- altpll_0_c0.clk
clk_0_clk_clk => clk_clk, -- clk_0_clk.clk
abus_slave_0_reset_reset_bridge_in_reset_reset => rst_controller_reset_out_reset, -- abus_slave_0_reset_reset_bridge_in_reset.reset
altpll_0_inclk_interface_reset_reset_bridge_in_reset_reset => rst_controller_001_reset_out_reset, -- altpll_0_inclk_interface_reset_reset_bridge_in_reset.reset
abus_slave_0_avalon_master_address => abus_slave_0_avalon_master_address, -- abus_slave_0_avalon_master.address
abus_slave_0_avalon_master_waitrequest => abus_slave_0_avalon_master_waitrequest, -- .waitrequest
abus_slave_0_avalon_master_burstcount(0) => abus_slave_0_avalon_master_burstcount, -- .burstcount
abus_slave_0_avalon_master_read => abus_slave_0_avalon_master_read, -- .read
abus_slave_0_avalon_master_readdata => abus_slave_0_avalon_master_readdata, -- .readdata
abus_slave_0_avalon_master_readdatavalid => abus_slave_0_avalon_master_readdatavalid, -- .readdatavalid
abus_slave_0_avalon_master_write => abus_slave_0_avalon_master_write, -- .write
abus_slave_0_avalon_master_writedata => abus_slave_0_avalon_master_writedata, -- .writedata
nios2_gen2_0_data_master_address => nios2_gen2_0_data_master_address, -- nios2_gen2_0_data_master.address
nios2_gen2_0_data_master_waitrequest => nios2_gen2_0_data_master_waitrequest, -- .waitrequest
nios2_gen2_0_data_master_byteenable => nios2_gen2_0_data_master_byteenable, -- .byteenable
nios2_gen2_0_data_master_read => nios2_gen2_0_data_master_read, -- .read
nios2_gen2_0_data_master_readdata => nios2_gen2_0_data_master_readdata, -- .readdata
nios2_gen2_0_data_master_write => nios2_gen2_0_data_master_write, -- .write
nios2_gen2_0_data_master_writedata => nios2_gen2_0_data_master_writedata, -- .writedata
nios2_gen2_0_data_master_debugaccess => nios2_gen2_0_data_master_debugaccess, -- .debugaccess
nios2_gen2_0_instruction_master_address => nios2_gen2_0_instruction_master_address, -- nios2_gen2_0_instruction_master.address
nios2_gen2_0_instruction_master_waitrequest => nios2_gen2_0_instruction_master_waitrequest, -- .waitrequest
nios2_gen2_0_instruction_master_read => nios2_gen2_0_instruction_master_read, -- .read
nios2_gen2_0_instruction_master_readdata => nios2_gen2_0_instruction_master_readdata, -- .readdata
abus_demux_0_avalon_nios_address => mm_interconnect_0_abus_demux_0_avalon_nios_address, -- abus_demux_0_avalon_nios.address
abus_demux_0_avalon_nios_write => mm_interconnect_0_abus_demux_0_avalon_nios_write, -- .write
abus_demux_0_avalon_nios_read => mm_interconnect_0_abus_demux_0_avalon_nios_read, -- .read
abus_demux_0_avalon_nios_readdata => mm_interconnect_0_abus_demux_0_avalon_nios_readdata, -- .readdata
abus_demux_0_avalon_nios_writedata => mm_interconnect_0_abus_demux_0_avalon_nios_writedata, -- .writedata
abus_demux_0_avalon_nios_burstcount => mm_interconnect_0_abus_demux_0_avalon_nios_burstcount, -- .burstcount
abus_demux_0_avalon_nios_readdatavalid => mm_interconnect_0_abus_demux_0_avalon_nios_readdatavalid, -- .readdatavalid
abus_demux_0_avalon_nios_waitrequest => mm_interconnect_0_abus_demux_0_avalon_nios_waitrequest, -- .waitrequest
abus_slave_0_avalon_nios_address => mm_interconnect_0_abus_slave_0_avalon_nios_address, -- abus_slave_0_avalon_nios.address
abus_slave_0_avalon_nios_write => mm_interconnect_0_abus_slave_0_avalon_nios_write, -- .write
abus_slave_0_avalon_nios_read => mm_interconnect_0_abus_slave_0_avalon_nios_read, -- .read
abus_slave_0_avalon_nios_readdata => mm_interconnect_0_abus_slave_0_avalon_nios_readdata, -- .readdata
abus_slave_0_avalon_nios_writedata => mm_interconnect_0_abus_slave_0_avalon_nios_writedata, -- .writedata
abus_slave_0_avalon_nios_burstcount => mm_interconnect_0_abus_slave_0_avalon_nios_burstcount, -- .burstcount
abus_slave_0_avalon_nios_readdatavalid => mm_interconnect_0_abus_slave_0_avalon_nios_readdatavalid, -- .readdatavalid
abus_slave_0_avalon_nios_waitrequest => mm_interconnect_0_abus_slave_0_avalon_nios_waitrequest, -- .waitrequest
altpll_0_pll_slave_address => mm_interconnect_0_altpll_0_pll_slave_address, -- altpll_0_pll_slave.address
altpll_0_pll_slave_write => mm_interconnect_0_altpll_0_pll_slave_write, -- .write
altpll_0_pll_slave_read => mm_interconnect_0_altpll_0_pll_slave_read, -- .read
altpll_0_pll_slave_readdata => mm_interconnect_0_altpll_0_pll_slave_readdata, -- .readdata
altpll_0_pll_slave_writedata => mm_interconnect_0_altpll_0_pll_slave_writedata, -- .writedata
external_sdram_controller_s1_address => mm_interconnect_0_external_sdram_controller_s1_address, -- external_sdram_controller_s1.address
external_sdram_controller_s1_write => mm_interconnect_0_external_sdram_controller_s1_write, -- .write
external_sdram_controller_s1_read => mm_interconnect_0_external_sdram_controller_s1_read, -- .read
external_sdram_controller_s1_readdata => mm_interconnect_0_external_sdram_controller_s1_readdata, -- .readdata
external_sdram_controller_s1_writedata => mm_interconnect_0_external_sdram_controller_s1_writedata, -- .writedata
external_sdram_controller_s1_byteenable => mm_interconnect_0_external_sdram_controller_s1_byteenable, -- .byteenable
external_sdram_controller_s1_readdatavalid => mm_interconnect_0_external_sdram_controller_s1_readdatavalid, -- .readdatavalid
external_sdram_controller_s1_waitrequest => mm_interconnect_0_external_sdram_controller_s1_waitrequest, -- .waitrequest
external_sdram_controller_s1_chipselect => mm_interconnect_0_external_sdram_controller_s1_chipselect, -- .chipselect
leds_s1_address => mm_interconnect_0_leds_s1_address, -- leds_s1.address
leds_s1_write => mm_interconnect_0_leds_s1_write, -- .write
leds_s1_readdata => mm_interconnect_0_leds_s1_readdata, -- .readdata
leds_s1_writedata => mm_interconnect_0_leds_s1_writedata, -- .writedata
leds_s1_chipselect => mm_interconnect_0_leds_s1_chipselect, -- .chipselect
nios2_gen2_0_debug_mem_slave_address => mm_interconnect_0_nios2_gen2_0_debug_mem_slave_address, -- nios2_gen2_0_debug_mem_slave.address
nios2_gen2_0_debug_mem_slave_write => mm_interconnect_0_nios2_gen2_0_debug_mem_slave_write, -- .write
nios2_gen2_0_debug_mem_slave_read => mm_interconnect_0_nios2_gen2_0_debug_mem_slave_read, -- .read
nios2_gen2_0_debug_mem_slave_readdata => mm_interconnect_0_nios2_gen2_0_debug_mem_slave_readdata, -- .readdata
nios2_gen2_0_debug_mem_slave_writedata => mm_interconnect_0_nios2_gen2_0_debug_mem_slave_writedata, -- .writedata
nios2_gen2_0_debug_mem_slave_byteenable => mm_interconnect_0_nios2_gen2_0_debug_mem_slave_byteenable, -- .byteenable
nios2_gen2_0_debug_mem_slave_waitrequest => mm_interconnect_0_nios2_gen2_0_debug_mem_slave_waitrequest, -- .waitrequest
nios2_gen2_0_debug_mem_slave_debugaccess => mm_interconnect_0_nios2_gen2_0_debug_mem_slave_debugaccess, -- .debugaccess
onchip_flash_0_csr_address => mm_interconnect_0_onchip_flash_0_csr_address, -- onchip_flash_0_csr.address
onchip_flash_0_csr_write => mm_interconnect_0_onchip_flash_0_csr_write, -- .write
onchip_flash_0_csr_read => mm_interconnect_0_onchip_flash_0_csr_read, -- .read
onchip_flash_0_csr_readdata => mm_interconnect_0_onchip_flash_0_csr_readdata, -- .readdata
onchip_flash_0_csr_writedata => mm_interconnect_0_onchip_flash_0_csr_writedata, -- .writedata
onchip_flash_0_data_address => mm_interconnect_0_onchip_flash_0_data_address, -- onchip_flash_0_data.address
onchip_flash_0_data_write => mm_interconnect_0_onchip_flash_0_data_write, -- .write
onchip_flash_0_data_read => mm_interconnect_0_onchip_flash_0_data_read, -- .read
onchip_flash_0_data_readdata => mm_interconnect_0_onchip_flash_0_data_readdata, -- .readdata
onchip_flash_0_data_writedata => mm_interconnect_0_onchip_flash_0_data_writedata, -- .writedata
onchip_flash_0_data_burstcount => mm_interconnect_0_onchip_flash_0_data_burstcount, -- .burstcount
onchip_flash_0_data_readdatavalid => mm_interconnect_0_onchip_flash_0_data_readdatavalid, -- .readdatavalid
onchip_flash_0_data_waitrequest => mm_interconnect_0_onchip_flash_0_data_waitrequest, -- .waitrequest
onchip_memory2_0_s1_address => mm_interconnect_0_onchip_memory2_0_s1_address, -- onchip_memory2_0_s1.address
onchip_memory2_0_s1_write => mm_interconnect_0_onchip_memory2_0_s1_write, -- .write
onchip_memory2_0_s1_readdata => mm_interconnect_0_onchip_memory2_0_s1_readdata, -- .readdata
onchip_memory2_0_s1_writedata => mm_interconnect_0_onchip_memory2_0_s1_writedata, -- .writedata
onchip_memory2_0_s1_byteenable => mm_interconnect_0_onchip_memory2_0_s1_byteenable, -- .byteenable
onchip_memory2_0_s1_chipselect => mm_interconnect_0_onchip_memory2_0_s1_chipselect, -- .chipselect
onchip_memory2_0_s1_clken => mm_interconnect_0_onchip_memory2_0_s1_clken, -- .clken
onchip_memory2_1_s1_address => mm_interconnect_0_onchip_memory2_1_s1_address, -- onchip_memory2_1_s1.address
onchip_memory2_1_s1_write => mm_interconnect_0_onchip_memory2_1_s1_write, -- .write
onchip_memory2_1_s1_readdata => mm_interconnect_0_onchip_memory2_1_s1_readdata, -- .readdata
onchip_memory2_1_s1_writedata => mm_interconnect_0_onchip_memory2_1_s1_writedata, -- .writedata
onchip_memory2_1_s1_byteenable => mm_interconnect_0_onchip_memory2_1_s1_byteenable, -- .byteenable
onchip_memory2_1_s1_chipselect => mm_interconnect_0_onchip_memory2_1_s1_chipselect, -- .chipselect
onchip_memory2_1_s1_clken => mm_interconnect_0_onchip_memory2_1_s1_clken, -- .clken
performance_counter_0_control_slave_address => mm_interconnect_0_performance_counter_0_control_slave_address, -- performance_counter_0_control_slave.address
performance_counter_0_control_slave_write => mm_interconnect_0_performance_counter_0_control_slave_write, -- .write
performance_counter_0_control_slave_readdata => mm_interconnect_0_performance_counter_0_control_slave_readdata, -- .readdata
performance_counter_0_control_slave_writedata => mm_interconnect_0_performance_counter_0_control_slave_writedata, -- .writedata
performance_counter_0_control_slave_begintransfer => mm_interconnect_0_performance_counter_0_control_slave_begintransfer, -- .begintransfer
switches_s1_address => mm_interconnect_0_switches_s1_address, -- switches_s1.address
switches_s1_readdata => mm_interconnect_0_switches_s1_readdata, -- .readdata
uart_0_s1_address => mm_interconnect_0_uart_0_s1_address, -- uart_0_s1.address
uart_0_s1_write => mm_interconnect_0_uart_0_s1_write, -- .write
uart_0_s1_read => mm_interconnect_0_uart_0_s1_read, -- .read
uart_0_s1_readdata => mm_interconnect_0_uart_0_s1_readdata, -- .readdata
uart_0_s1_writedata => mm_interconnect_0_uart_0_s1_writedata, -- .writedata
uart_0_s1_begintransfer => mm_interconnect_0_uart_0_s1_begintransfer, -- .begintransfer
uart_0_s1_chipselect => mm_interconnect_0_uart_0_s1_chipselect -- .chipselect
);
irq_mapper : component wasca_irq_mapper
port map (
clk => altpll_0_c0_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- clk_reset.reset
receiver0_irq => irq_mapper_receiver0_irq, -- receiver0.irq
sender_irq => nios2_gen2_0_irq_irq -- sender.irq
);
rst_controller : component wasca_rst_controller
generic map (
NUM_RESET_INPUTS => 1,
OUTPUT_RESET_SYNC_EDGES => "deassert",
SYNC_DEPTH => 2,
RESET_REQUEST_PRESENT => 1,
RESET_REQ_WAIT_TIME => 1,
MIN_RST_ASSERTION_TIME => 3,
RESET_REQ_EARLY_DSRT_TIME => 1,
USE_RESET_REQUEST_IN0 => 0,
USE_RESET_REQUEST_IN1 => 0,
USE_RESET_REQUEST_IN2 => 0,
USE_RESET_REQUEST_IN3 => 0,
USE_RESET_REQUEST_IN4 => 0,
USE_RESET_REQUEST_IN5 => 0,
USE_RESET_REQUEST_IN6 => 0,
USE_RESET_REQUEST_IN7 => 0,
USE_RESET_REQUEST_IN8 => 0,
USE_RESET_REQUEST_IN9 => 0,
USE_RESET_REQUEST_IN10 => 0,
USE_RESET_REQUEST_IN11 => 0,
USE_RESET_REQUEST_IN12 => 0,
USE_RESET_REQUEST_IN13 => 0,
USE_RESET_REQUEST_IN14 => 0,
USE_RESET_REQUEST_IN15 => 0,
ADAPT_RESET_REQUEST => 0
)
port map (
reset_in0 => nios2_gen2_0_debug_reset_request_reset, -- reset_in0.reset
clk => altpll_0_c0_clk, -- clk.clk
reset_out => rst_controller_reset_out_reset, -- reset_out.reset
reset_req => rst_controller_reset_out_reset_req, -- .reset_req
reset_req_in0 => '0', -- (terminated)
reset_in1 => '0', -- (terminated)
reset_req_in1 => '0', -- (terminated)
reset_in2 => '0', -- (terminated)
reset_req_in2 => '0', -- (terminated)
reset_in3 => '0', -- (terminated)
reset_req_in3 => '0', -- (terminated)
reset_in4 => '0', -- (terminated)
reset_req_in4 => '0', -- (terminated)
reset_in5 => '0', -- (terminated)
reset_req_in5 => '0', -- (terminated)
reset_in6 => '0', -- (terminated)
reset_req_in6 => '0', -- (terminated)
reset_in7 => '0', -- (terminated)
reset_req_in7 => '0', -- (terminated)
reset_in8 => '0', -- (terminated)
reset_req_in8 => '0', -- (terminated)
reset_in9 => '0', -- (terminated)
reset_req_in9 => '0', -- (terminated)
reset_in10 => '0', -- (terminated)
reset_req_in10 => '0', -- (terminated)
reset_in11 => '0', -- (terminated)
reset_req_in11 => '0', -- (terminated)
reset_in12 => '0', -- (terminated)
reset_req_in12 => '0', -- (terminated)
reset_in13 => '0', -- (terminated)
reset_req_in13 => '0', -- (terminated)
reset_in14 => '0', -- (terminated)
reset_req_in14 => '0', -- (terminated)
reset_in15 => '0', -- (terminated)
reset_req_in15 => '0' -- (terminated)
);
rst_controller_001 : component wasca_rst_controller_001
generic map (
NUM_RESET_INPUTS => 1,
OUTPUT_RESET_SYNC_EDGES => "deassert",
SYNC_DEPTH => 2,
RESET_REQUEST_PRESENT => 0,
RESET_REQ_WAIT_TIME => 1,
MIN_RST_ASSERTION_TIME => 3,
RESET_REQ_EARLY_DSRT_TIME => 1,
USE_RESET_REQUEST_IN0 => 0,
USE_RESET_REQUEST_IN1 => 0,
USE_RESET_REQUEST_IN2 => 0,
USE_RESET_REQUEST_IN3 => 0,
USE_RESET_REQUEST_IN4 => 0,
USE_RESET_REQUEST_IN5 => 0,
USE_RESET_REQUEST_IN6 => 0,
USE_RESET_REQUEST_IN7 => 0,
USE_RESET_REQUEST_IN8 => 0,
USE_RESET_REQUEST_IN9 => 0,
USE_RESET_REQUEST_IN10 => 0,
USE_RESET_REQUEST_IN11 => 0,
USE_RESET_REQUEST_IN12 => 0,
USE_RESET_REQUEST_IN13 => 0,
USE_RESET_REQUEST_IN14 => 0,
USE_RESET_REQUEST_IN15 => 0,
ADAPT_RESET_REQUEST => 0
)
port map (
reset_in0 => nios2_gen2_0_debug_reset_request_reset, -- reset_in0.reset
clk => clk_clk, -- clk.clk
reset_out => rst_controller_001_reset_out_reset, -- reset_out.reset
reset_req => open, -- (terminated)
reset_req_in0 => '0', -- (terminated)
reset_in1 => '0', -- (terminated)
reset_req_in1 => '0', -- (terminated)
reset_in2 => '0', -- (terminated)
reset_req_in2 => '0', -- (terminated)
reset_in3 => '0', -- (terminated)
reset_req_in3 => '0', -- (terminated)
reset_in4 => '0', -- (terminated)
reset_req_in4 => '0', -- (terminated)
reset_in5 => '0', -- (terminated)
reset_req_in5 => '0', -- (terminated)
reset_in6 => '0', -- (terminated)
reset_req_in6 => '0', -- (terminated)
reset_in7 => '0', -- (terminated)
reset_req_in7 => '0', -- (terminated)
reset_in8 => '0', -- (terminated)
reset_req_in8 => '0', -- (terminated)
reset_in9 => '0', -- (terminated)
reset_req_in9 => '0', -- (terminated)
reset_in10 => '0', -- (terminated)
reset_req_in10 => '0', -- (terminated)
reset_in11 => '0', -- (terminated)
reset_req_in11 => '0', -- (terminated)
reset_in12 => '0', -- (terminated)
reset_req_in12 => '0', -- (terminated)
reset_in13 => '0', -- (terminated)
reset_req_in13 => '0', -- (terminated)
reset_in14 => '0', -- (terminated)
reset_req_in14 => '0', -- (terminated)
reset_in15 => '0', -- (terminated)
reset_req_in15 => '0' -- (terminated)
);
rst_controller_002 : component wasca_rst_controller_001
generic map (
NUM_RESET_INPUTS => 1,
OUTPUT_RESET_SYNC_EDGES => "both",
SYNC_DEPTH => 2,
RESET_REQUEST_PRESENT => 0,
RESET_REQ_WAIT_TIME => 1,
MIN_RST_ASSERTION_TIME => 3,
RESET_REQ_EARLY_DSRT_TIME => 1,
USE_RESET_REQUEST_IN0 => 0,
USE_RESET_REQUEST_IN1 => 0,
USE_RESET_REQUEST_IN2 => 0,
USE_RESET_REQUEST_IN3 => 0,
USE_RESET_REQUEST_IN4 => 0,
USE_RESET_REQUEST_IN5 => 0,
USE_RESET_REQUEST_IN6 => 0,
USE_RESET_REQUEST_IN7 => 0,
USE_RESET_REQUEST_IN8 => 0,
USE_RESET_REQUEST_IN9 => 0,
USE_RESET_REQUEST_IN10 => 0,
USE_RESET_REQUEST_IN11 => 0,
USE_RESET_REQUEST_IN12 => 0,
USE_RESET_REQUEST_IN13 => 0,
USE_RESET_REQUEST_IN14 => 0,
USE_RESET_REQUEST_IN15 => 0,
ADAPT_RESET_REQUEST => 0
)
port map (
reset_in0 => nios2_gen2_0_debug_reset_request_reset, -- reset_in0.reset
clk => altpll_0_c0_clk, -- clk.clk
reset_out => open, -- reset_out.reset
reset_req => open, -- (terminated)
reset_req_in0 => '0', -- (terminated)
reset_in1 => '0', -- (terminated)
reset_req_in1 => '0', -- (terminated)
reset_in2 => '0', -- (terminated)
reset_req_in2 => '0', -- (terminated)
reset_in3 => '0', -- (terminated)
reset_req_in3 => '0', -- (terminated)
reset_in4 => '0', -- (terminated)
reset_req_in4 => '0', -- (terminated)
reset_in5 => '0', -- (terminated)
reset_req_in5 => '0', -- (terminated)
reset_in6 => '0', -- (terminated)
reset_req_in6 => '0', -- (terminated)
reset_in7 => '0', -- (terminated)
reset_req_in7 => '0', -- (terminated)
reset_in8 => '0', -- (terminated)
reset_req_in8 => '0', -- (terminated)
reset_in9 => '0', -- (terminated)
reset_req_in9 => '0', -- (terminated)
reset_in10 => '0', -- (terminated)
reset_req_in10 => '0', -- (terminated)
reset_in11 => '0', -- (terminated)
reset_req_in11 => '0', -- (terminated)
reset_in12 => '0', -- (terminated)
reset_req_in12 => '0', -- (terminated)
reset_in13 => '0', -- (terminated)
reset_req_in13 => '0', -- (terminated)
reset_in14 => '0', -- (terminated)
reset_req_in14 => '0', -- (terminated)
reset_in15 => '0', -- (terminated)
reset_req_in15 => '0' -- (terminated)
);
mm_interconnect_0_external_sdram_controller_s1_read_ports_inv <= not mm_interconnect_0_external_sdram_controller_s1_read;
mm_interconnect_0_external_sdram_controller_s1_byteenable_ports_inv <= not mm_interconnect_0_external_sdram_controller_s1_byteenable;
mm_interconnect_0_external_sdram_controller_s1_write_ports_inv <= not mm_interconnect_0_external_sdram_controller_s1_write;
mm_interconnect_0_leds_s1_write_ports_inv <= not mm_interconnect_0_leds_s1_write;
mm_interconnect_0_uart_0_s1_read_ports_inv <= not mm_interconnect_0_uart_0_s1_read;
mm_interconnect_0_uart_0_s1_write_ports_inv <= not mm_interconnect_0_uart_0_s1_write;
rst_controller_reset_out_reset_ports_inv <= not rst_controller_reset_out_reset;
clock_116_mhz_clk <= altpll_0_c0_clk;
end architecture rtl; -- of wasca
| gpl-2.0 | d95e3e40c68924327af24057c17910d0 | 0.468056 | 4.0397 | false | false | false | false |
impedimentToProgress/UCI-BlueChip | AttackFiles/Attacks/privEsc/lib/techmap/maps/allclkgen.vhd | 2 | 10,347 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: libclk
-- File: libclk.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: Clock generator interface package
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
package allclkgen is
component clkgen_virtex
generic (
clk_mul : integer := 1;
clk_div : integer := 1;
sdramen : integer := 0;
noclkfb : integer := 0;
pcien : integer := 0;
pcidll : integer := 0;
pcisysclk: integer := 0);
port (
clkin : in std_logic;
pciclkin: in std_logic;
clk : out std_logic; -- main clock
clkn : out std_logic; -- inverted main clock
clk2x : out std_logic; -- double clock
sdclk : out std_logic; -- SDRAM clock
pciclk : out std_logic; -- PCI clock
cgi : in clkgen_in_type;
cgo : out clkgen_out_type);
end component;
component clkgen_virtex2
generic (
clk_mul : integer := 1;
clk_div : integer := 1;
sdramen : integer := 0;
noclkfb : integer := 0;
pcien : integer := 0;
pcidll : integer := 0;
pcisysclk: integer := 0;
freq : integer := 25000;
clk2xen : integer := 0;
clksel : integer := 0); -- enable clock select
port (
clkin : in std_logic;
pciclkin: in std_logic;
clk : out std_logic; -- main clock
clkn : out std_logic; -- inverted main clock
clk2x : out std_logic; -- double clock
sdclk : out std_logic; -- SDRAM clock
pciclk : out std_logic; -- PCI clock
cgi : in clkgen_in_type;
cgo : out clkgen_out_type;
clk1xu : out std_ulogic; -- unscaled clock
clk2xu : out std_ulogic);
end component;
component clkgen_spartan3
generic (
clk_mul : integer := 1;
clk_div : integer := 1;
sdramen : integer := 0;
noclkfb : integer := 0;
pcien : integer := 0;
pcidll : integer := 0;
pcisysclk: integer := 0;
freq : integer := 25000;
clk2xen : integer := 0;
clksel : integer := 0); -- enable clock select
port (
clkin : in std_logic;
pciclkin: in std_logic;
clk : out std_logic; -- main clock
clkn : out std_logic; -- inverted main clock
clk2x : out std_logic; -- double clock
sdclk : out std_logic; -- SDRAM clock
pciclk : out std_logic; -- PCI clock
cgi : in clkgen_in_type;
cgo : out clkgen_out_type;
clk1xu : out std_ulogic; -- unscaled clock
clk2xu : out std_ulogic);
end component;
component clkgen_virtex5
generic (
clk_mul : integer := 1;
clk_div : integer := 1;
sdramen : integer := 0;
noclkfb : integer := 0;
pcien : integer := 0;
pcidll : integer := 0;
pcisysclk: integer := 0;
freq : integer := 25000;
clk2xen : integer := 0;
clksel : integer := 0); -- enable clock select
port (
clkin : in std_logic;
pciclkin: in std_logic;
clk : out std_logic; -- main clock
clkn : out std_logic; -- inverted main clock
clk2x : out std_logic; -- double clock
sdclk : out std_logic; -- SDRAM clock
pciclk : out std_logic; -- PCI clock
cgi : in clkgen_in_type;
cgo : out clkgen_out_type;
clk1xu : out std_ulogic; -- unscaled clock
clk2xu : out std_ulogic);
end component;
component clkgen_axcelerator
generic (
clk_mul : integer := 1;
clk_div : integer := 1;
sdramen : integer := 0;
sdinvclk : integer := 0;
pcien : integer := 0;
pcidll : integer := 0;
pcisysclk: integer := 0);
port (
clkin : in std_logic;
pciclkin: in std_logic;
clk : out std_logic; -- main clock
clkn : out std_logic; -- inverted main clock
sdclk : out std_logic; -- SDRAM clock
pciclk : out std_logic; -- PCI clock
cgi : in clkgen_in_type;
cgo : out clkgen_out_type);
end component;
component clkgen_altera_mf
generic (
clk_mul : integer := 1;
clk_div : integer := 1;
sdramen : integer := 0;
sdinvclk : integer := 0;
pcien : integer := 0;
pcidll : integer := 0;
pcisysclk: integer := 0;
freq : integer := 25000;
clk2xen : integer := 0);
port (
clkin : in std_logic;
pciclkin: in std_logic;
clk : out std_logic; -- main clock
clkn : out std_logic; -- inverted main clock
clk2x : out std_logic; -- double clock
sdclk : out std_logic; -- SDRAM clock
pciclk : out std_logic; -- PCI clock
cgi : in clkgen_in_type;
cgo : out clkgen_out_type);
end component;
component clkgen_cycloneiii
generic (
clk_mul : integer := 1;
clk_div : integer := 1;
sdramen : integer := 0;
sdinvclk : integer := 0;
pcien : integer := 0;
pcidll : integer := 0;
pcisysclk: integer := 0;
freq : integer := 25000;
clk2xen : integer := 0);
port (
clkin : in std_logic;
pciclkin: in std_logic;
clk : out std_logic; -- main clock
clkn : out std_logic; -- inverted main clock
clk2x : out std_logic; -- double clock
sdclk : out std_logic; -- SDRAM clock
pciclk : out std_logic; -- PCI clock
cgi : in clkgen_in_type;
cgo : out clkgen_out_type);
end component;
component clkgen_stratixiii
generic (
clk_mul : integer := 1;
clk_div : integer := 1;
sdramen : integer := 0;
sdinvclk : integer := 0;
pcien : integer := 0;
pcidll : integer := 0;
pcisysclk: integer := 0;
freq : integer := 25000;
clk2xen : integer := 0);
port (
clkin : in std_logic;
pciclkin: in std_logic;
clk : out std_logic; -- main clock
clkn : out std_logic; -- inverted main clock
clk2x : out std_logic; -- double clock
sdclk : out std_logic; -- SDRAM clock
pciclk : out std_logic; -- PCI clock
cgi : in clkgen_in_type;
cgo : out clkgen_out_type);
end component;
component clkgen_rh_lib18t
generic (
clk_mul : integer := 1;
clk_div : integer := 1);
port (
rst : in std_logic;
clkin : in std_logic;
clk : out std_logic;
sdclk : out std_logic; -- SDRAM clock
clk2x : out std_logic;
clk4x : out std_logic
);
end component;
component clkmul_virtex2
generic ( clk_mul : integer := 2 ; clk_div : integer := 2);
port (
resetin : in std_logic;
clkin : in std_logic;
clk : out std_logic;
resetout: out std_logic
);
end component;
component clkand_unisim
port(
i : in std_ulogic;
en : in std_ulogic;
o : out std_ulogic
);
end component;
component clkand_ut025crh
port(
i : in std_ulogic;
en : in std_ulogic;
o : out std_ulogic
);
end component;
component clkmux_unisim
port(
i0, i1 : in std_ulogic;
sel : in std_ulogic;
o : out std_ulogic
);
end component;
component altera_pll
generic (
clk_mul : integer := 1;
clk_div : integer := 1;
clk_freq : integer := 25000;
clk2xen : integer := 0;
sdramen : integer := 0
);
port (
inclk0 : in std_ulogic;
c0 : out std_ulogic;
c0_2x : out std_ulogic;
e0 : out std_ulogic;
locked : out std_ulogic);
end component;
component clkgen_proasic3
generic (
clk_mul : integer := 1;
clk_div : integer := 1;
clk_odiv : integer := 1; -- output divider
pcien : integer := 0;
pcisysclk: integer := 0;
freq : integer := 25000); -- clock frequency in KHz
port (
clkin : in std_ulogic;
pciclkin: in std_ulogic;
clk : out std_ulogic; -- main clock
sdclk : out std_ulogic; -- SDRAM clock
pciclk : out std_ulogic;
cgi : in clkgen_in_type;
cgo : out clkgen_out_type);
end component;
component cyclone3_pll is
generic (
clk_mul : integer := 1;
clk_div : integer := 1;
clk_freq : integer := 25000;
clk2xen : integer := 0;
sdramen : integer := 0
);
port (
inclk0 : in std_ulogic;
c0 : out std_ulogic;
c0_2x : out std_ulogic;
e0 : out std_ulogic;
locked : out std_ulogic);
end component;
component stratix3_pll
generic (
clk_mul : integer := 1;
clk_div : integer := 1;
clk_freq : integer := 25000;
clk2xen : integer := 0;
sdramen : integer := 0
);
port (
inclk0 : in std_ulogic;
c0 : out std_ulogic;
c0_2x : out std_ulogic;
e0 : out std_ulogic;
locked : out std_ulogic);
end component;
component clkgen_dare
port (
clkin : in std_logic;
clk : out std_logic; -- main clock
clk2x : out std_logic; -- 2x clock
sdclk : out std_logic; -- SDRAM clock
pciclk : out std_logic; -- PCI clock
cgi : in clkgen_in_type;
cgo : out clkgen_out_type;
clk4x : out std_logic; -- 4x clock
clk1xu : out std_logic; -- unscaled 1X clock
clk2xu : out std_logic); -- unscaled 2X clock
end component;
end;
| mit | 9576494100dbdb4fefd7daac4a970b5d | 0.552237 | 3.459378 | false | false | false | false |
impedimentToProgress/UCI-BlueChip | AttackFiles/Attacks/privEsc/lib/tech/cycloneiii/simprims/cycloneiii_atoms.vhd | 2 | 320,097 | -- Copyright (C) 1991-2007 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions
-- and other software and tools, and its AMPP partner logic
-- functions, and any output files from any of the foregoing
-- (including device programming or simulation files), and any
-- associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License
-- Subscription Agreement, Altera MegaCore Function License
-- Agreement, or other applicable license agreement, including,
-- without limitation, that your use is for the sole purpose of
-- programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the
-- applicable agreement for further details.
-- Quartus II 7.1 Build 156 04/30/2007
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
package cycloneiii_atom_pack is
function str_to_bin (lut_mask : string ) return std_logic_vector;
function product(list : std_logic_vector) return std_logic ;
function alt_conv_integer(arg : in std_logic_vector) return integer;
-- default generic values
CONSTANT DefWireDelay : VitalDelayType01 := (0 ns, 0 ns);
CONSTANT DefPropDelay01 : VitalDelayType01 := (0 ns, 0 ns);
CONSTANT DefPropDelay01Z : VitalDelayType01Z := (OTHERS => 0 ns);
CONSTANT DefSetupHoldCnst : TIME := 0 ns;
CONSTANT DefPulseWdthCnst : TIME := 0 ns;
-- default control options
-- CONSTANT DefGlitchMode : VitalGlitchKindType := OnEvent;
-- change default delay type to Transport : for spr 68748
CONSTANT DefGlitchMode : VitalGlitchKindType := VitalTransport;
CONSTANT DefGlitchMsgOn : BOOLEAN := FALSE;
CONSTANT DefGlitchXOn : BOOLEAN := FALSE;
CONSTANT DefMsgOnChecks : BOOLEAN := TRUE;
CONSTANT DefXOnChecks : BOOLEAN := TRUE;
-- output strength mapping
-- UX01ZWHL-
CONSTANT PullUp : VitalOutputMapType := "UX01HX01X";
CONSTANT NoPullUpZ : VitalOutputMapType := "UX01ZX01X";
CONSTANT PullDown : VitalOutputMapType := "UX01LX01X";
-- primitive result strength mapping
CONSTANT wiredOR : VitalResultMapType := ( 'U', 'X', 'L', '1' );
CONSTANT wiredAND : VitalResultMapType := ( 'U', 'X', '0', 'H' );
CONSTANT L : VitalTableSymbolType := '0';
CONSTANT H : VitalTableSymbolType := '1';
CONSTANT x : VitalTableSymbolType := '-';
CONSTANT S : VitalTableSymbolType := 'S';
CONSTANT R : VitalTableSymbolType := '/';
CONSTANT U : VitalTableSymbolType := 'X';
CONSTANT V : VitalTableSymbolType := 'B'; -- valid clock signal (non-rising)
-- Declare array types for CAM_SLICE
TYPE cycloneiii_mem_data IS ARRAY (0 to 31) of STD_LOGIC_VECTOR (31 downto 0);
function int2str( value : integer ) return string;
function map_x_to_0 (value : std_logic) return std_logic;
function SelectDelay (CONSTANT Paths: IN VitalPathArray01Type) return TIME;
end cycloneiii_atom_pack;
library IEEE;
use IEEE.std_logic_1164.all;
package body cycloneiii_atom_pack is
type masklength is array (4 downto 1) of std_logic_vector(3 downto 0);
function str_to_bin (lut_mask : string) return std_logic_vector is
variable slice : masklength := (OTHERS => "0000");
variable mask : std_logic_vector(15 downto 0);
begin
for i in 1 to lut_mask'length loop
case lut_mask(i) is
when '0' => slice(i) := "0000";
when '1' => slice(i) := "0001";
when '2' => slice(i) := "0010";
when '3' => slice(i) := "0011";
when '4' => slice(i) := "0100";
when '5' => slice(i) := "0101";
when '6' => slice(i) := "0110";
when '7' => slice(i) := "0111";
when '8' => slice(i) := "1000";
when '9' => slice(i) := "1001";
when 'a' => slice(i) := "1010";
when 'A' => slice(i) := "1010";
when 'b' => slice(i) := "1011";
when 'B' => slice(i) := "1011";
when 'c' => slice(i) := "1100";
when 'C' => slice(i) := "1100";
when 'd' => slice(i) := "1101";
when 'D' => slice(i) := "1101";
when 'e' => slice(i) := "1110";
when 'E' => slice(i) := "1110";
when others => slice(i) := "1111";
end case;
end loop;
mask := (slice(1) & slice(2) & slice(3) & slice(4));
return (mask);
end str_to_bin;
function product (list: std_logic_vector) return std_logic is
begin
for i in 0 to 31 loop
if list(i) = '0' then
return ('0');
end if;
end loop;
return ('1');
end product;
function alt_conv_integer(arg : in std_logic_vector) return integer is
variable result : integer;
begin
result := 0;
for i in arg'range loop
if arg(i) = '1' then
result := result + 2**i;
end if;
end loop;
return result;
end alt_conv_integer;
function int2str( value : integer ) return string is
variable ivalue,index : integer;
variable digit : integer;
variable line_no: string(8 downto 1) := " ";
begin
ivalue := value;
index := 1;
if (ivalue = 0) then
line_no := " 0";
end if;
while (ivalue > 0) loop
digit := ivalue MOD 10;
ivalue := ivalue/10;
case digit is
when 0 =>
line_no(index) := '0';
when 1 =>
line_no(index) := '1';
when 2 =>
line_no(index) := '2';
when 3 =>
line_no(index) := '3';
when 4 =>
line_no(index) := '4';
when 5 =>
line_no(index) := '5';
when 6 =>
line_no(index) := '6';
when 7 =>
line_no(index) := '7';
when 8 =>
line_no(index) := '8';
when 9 =>
line_no(index) := '9';
when others =>
ASSERT FALSE
REPORT "Illegal number!"
SEVERITY ERROR;
end case;
index := index + 1;
end loop;
return line_no;
end;
function map_x_to_0 (value : std_logic) return std_logic is
begin
if (Is_X (value) = TRUE) then
return '0';
else
return value;
end if;
end;
function SelectDelay (CONSTANT Paths : IN VitalPathArray01Type) return TIME IS
variable Temp : TIME;
variable TransitionTime : TIME := TIME'HIGH;
variable PathDelay : TIME := TIME'HIGH;
begin
for i IN Paths'RANGE loop
next when not Paths(i).PathCondition;
next when Paths(i).InputChangeTime > TransitionTime;
Temp := Paths(i).PathDelay(tr01);
if Paths(i).InputChangeTime < TransitionTime then
PathDelay := Temp;
else
if Temp < PathDelay then
PathDelay := Temp;
end if;
end if;
TransitionTime := Paths(i).InputChangeTime;
end loop;
return PathDelay;
end;
end cycloneiii_atom_pack;
Library ieee;
use ieee.std_logic_1164.all;
Package cycloneiii_pllpack is
procedure find_simple_integer_fraction( numerator : in integer;
denominator : in integer;
max_denom : in integer;
fraction_num : out integer;
fraction_div : out integer);
procedure find_m_and_n_4_manual_phase ( inclock_period : in integer;
vco_phase_shift_step : in integer;
clk0_mult: in integer; clk1_mult: in integer;
clk2_mult: in integer; clk3_mult: in integer;
clk4_mult: in integer; clk5_mult: in integer;
clk6_mult: in integer; clk7_mult: in integer;
clk8_mult: in integer; clk9_mult: in integer;
clk0_div : in integer; clk1_div : in integer;
clk2_div : in integer; clk3_div : in integer;
clk4_div : in integer; clk5_div : in integer;
clk6_div : in integer; clk7_div : in integer;
clk8_div : in integer; clk9_div : in integer;
m : out integer;
n : out integer );
function gcd (X: integer; Y: integer) return integer;
function count_digit (X: integer) return integer;
function scale_num (X: integer; Y: integer) return integer;
function lcm (A1: integer; A2: integer; A3: integer; A4: integer;
A5: integer; A6: integer; A7: integer;
A8: integer; A9: integer; A10: integer; P: integer) return integer;
function output_counter_value (clk_divide: integer; clk_mult : integer ;
M: integer; N: integer ) return integer;
function counter_mode (duty_cycle: integer; output_counter_value: integer) return string;
function counter_high (output_counter_value: integer := 1; duty_cycle: integer)
return integer;
function counter_low (output_counter_value: integer; duty_cycle: integer)
return integer;
function mintimedelay (t1: integer; t2: integer; t3: integer; t4: integer;
t5: integer; t6: integer; t7: integer; t8: integer;
t9: integer; t10: integer) return integer;
function maxnegabs (t1: integer; t2: integer; t3: integer; t4: integer;
t5: integer; t6: integer; t7: integer; t8: integer;
t9: integer; t10: integer) return integer;
function counter_time_delay ( clk_time_delay: integer;
m_time_delay: integer; n_time_delay: integer)
return integer;
function get_phase_degree (phase_shift: integer; clk_period: integer) return integer;
function counter_initial (tap_phase: integer; m: integer; n: integer)
return integer;
function counter_ph (tap_phase: integer; m : integer; n: integer) return integer;
function ph_adjust (tap_phase: integer; ph_base : integer) return integer;
function translate_string (mode : string) return string;
function str2int (s : string) return integer;
function dqs_str2int (s : string) return integer;
end cycloneiii_pllpack;
package body cycloneiii_pllpack is
-- finds the closest integer fraction of a given pair of numerator and denominator.
procedure find_simple_integer_fraction( numerator : in integer;
denominator : in integer;
max_denom : in integer;
fraction_num : out integer;
fraction_div : out integer) is
constant MAX_ITER : integer := 20;
type INT_ARRAY is array ((MAX_ITER-1) downto 0) of integer;
variable quotient_array : INT_ARRAY;
variable int_loop_iter : integer;
variable int_quot : integer;
variable m_value : integer;
variable d_value : integer;
variable old_m_value : integer;
variable swap : integer;
variable loop_iter : integer;
variable num : integer;
variable den : integer;
variable i_max_iter : integer;
begin
loop_iter := 0;
if (numerator = 0) then
num := 1;
else
num := numerator;
end if;
if (denominator = 0) then
den := 1;
else
den := denominator;
end if;
i_max_iter := max_iter;
while (loop_iter < i_max_iter) loop
int_quot := num / den;
quotient_array(loop_iter) := int_quot;
num := num - (den*int_quot);
loop_iter := loop_iter+1;
if ((num = 0) or (max_denom /= -1) or (loop_iter = i_max_iter)) then
-- calculate the numerator and denominator if there is a restriction on the
-- max denom value or if the loop is ending
m_value := 0;
d_value := 1;
-- get the rounded value at this stage for the remaining fraction
if (den /= 0) then
m_value := (2*num/den);
end if;
-- calculate the fraction numerator and denominator at this stage
for int_loop_iter in (loop_iter-1) downto 0 loop
if (m_value = 0) then
m_value := quotient_array(int_loop_iter);
d_value := 1;
else
old_m_value := m_value;
m_value := (quotient_array(int_loop_iter)*m_value) + d_value;
d_value := old_m_value;
end if;
end loop;
-- if the denominator is less than the maximum denom_value or if there is no restriction save it
if ((d_value <= max_denom) or (max_denom = -1)) then
if ((m_value = 0) or (d_value = 0)) then
fraction_num := numerator;
fraction_div := denominator;
else
fraction_num := m_value;
fraction_div := d_value;
end if;
end if;
-- end the loop if the denomitor has overflown or the numerator is zero (no remainder during this round)
if (((d_value > max_denom) and (max_denom /= -1)) or (num = 0)) then
i_max_iter := loop_iter;
end if;
end if;
-- swap the numerator and denominator for the next round
swap := den;
den := num;
num := swap;
end loop;
end find_simple_integer_fraction;
-- find the M and N values for Manual phase based on the following 5 criterias:
-- 1. The PFD frequency (i.e. Fin / N) must be in the range 5 MHz to 720 MHz
-- 2. The VCO frequency (i.e. Fin * M / N) must be in the range 300 MHz to 1300 MHz
-- 3. M is less than 512
-- 4. N is less than 512
-- 5. It's the smallest M/N which satisfies all the above constraints, and is within 2ps
-- of the desired vco-phase-shift-step
procedure find_m_and_n_4_manual_phase ( inclock_period : in integer;
vco_phase_shift_step : in integer;
clk0_mult: in integer; clk1_mult: in integer;
clk2_mult: in integer; clk3_mult: in integer;
clk4_mult: in integer; clk5_mult: in integer;
clk6_mult: in integer; clk7_mult: in integer;
clk8_mult: in integer; clk9_mult: in integer;
clk0_div : in integer; clk1_div : in integer;
clk2_div : in integer; clk3_div : in integer;
clk4_div : in integer; clk5_div : in integer;
clk6_div : in integer; clk7_div : in integer;
clk8_div : in integer; clk9_div : in integer;
m : out integer;
n : out integer ) is
constant MAX_M : integer := 511;
constant MAX_N : integer := 511;
constant MAX_PFD : integer := 720;
constant MIN_PFD : integer := 5;
constant MAX_VCO : integer := 1300;
constant MIN_VCO : integer := 300;
variable vco_period : integer;
variable pfd_freq : integer;
variable vco_freq : integer;
variable vco_ps_step_value : integer;
variable i_m : integer;
variable i_n : integer;
variable i_pre_m : integer;
variable i_pre_n : integer;
variable i_max_iter : integer;
variable loop_iter : integer;
begin
loop_iter := 0;
i_max_iter := MAX_N;
vco_period := vco_phase_shift_step * 8;
while (loop_iter < i_max_iter) loop
loop_iter := loop_iter+1;
i_pre_m := i_m;
i_pre_n := i_n;
find_simple_integer_fraction(inclock_period, vco_period,
loop_iter, i_m, i_n);
if (((clk0_div * i_m) rem (clk0_mult * i_n) /= 0) or
((clk1_div * i_m) rem (clk1_mult * i_n) /= 0) or
((clk2_div * i_m) rem (clk2_mult * i_n) /= 0) or
((clk3_div * i_m) rem (clk3_mult * i_n) /= 0) or
((clk4_div * i_m) rem (clk4_mult * i_n) /= 0) or
((clk5_div * i_m) rem (clk5_mult * i_n) /= 0) or
((clk6_div * i_m) rem (clk6_mult * i_n) /= 0) or
((clk7_div * i_m) rem (clk7_mult * i_n) /= 0) or
((clk8_div * i_m) rem (clk8_mult * i_n) /= 0) or
((clk9_div * i_m) rem (clk9_mult * i_n) /= 0) )
then
if (loop_iter = 1)
then
n := 1;
m := lcm (clk0_mult, clk1_mult, clk2_mult, clk3_mult,
clk4_mult, clk5_mult, clk6_mult,
clk7_mult, clk8_mult, clk9_mult, inclock_period);
else
m := i_pre_m;
n := i_pre_n;
end if;
i_max_iter := loop_iter;
else
m := i_m;
n := i_n;
end if;
pfd_freq := 1000000 / (inclock_period * i_n);
vco_freq := (1000000 * i_m) / (inclock_period * i_n);
vco_ps_step_value := (inclock_period * i_n) / (8 * i_m);
if ( (i_m < max_m) and (i_n < max_n) and (pfd_freq >= min_pfd) and (pfd_freq <= max_pfd) and
(vco_freq >= min_vco) and (vco_freq <= max_vco) and
(abs(vco_ps_step_value - vco_phase_shift_step) <= 2) )
then
i_max_iter := loop_iter;
end if;
end loop;
end find_m_and_n_4_manual_phase;
-- find the greatest common denominator of X and Y
function gcd (X: integer; Y: integer) return integer is
variable L, S, R, G : integer := 1;
begin
if (X < Y) then -- find which is smaller.
S := X;
L := Y;
else
S := Y;
L := X;
end if;
R := S;
while ( R > 1) loop
S := L;
L := R;
R := S rem L; -- divide bigger number by smaller.
-- remainder becomes smaller number.
end loop;
if (R = 0) then -- if evenly divisible then L is gcd else it is 1.
G := L;
else
G := R;
end if;
return G;
end gcd;
-- count the number of digits in the given integer
function count_digit (X: integer)
return integer is
variable count, result: integer := 0;
begin
result := X;
while (result /= 0) loop
result := (result / 10);
count := count + 1;
end loop;
return count;
end count_digit;
-- reduce the given huge number to Y significant digits
function scale_num (X: integer; Y: integer)
return integer is
variable count : integer := 0;
variable lc, fac_ten, result: integer := 1;
begin
count := count_digit(X);
for lc in 1 to (count-Y) loop
fac_ten := fac_ten * 10;
end loop;
result := (X / fac_ten);
return result;
end scale_num;
-- find the least common multiple of A1 to A10
function lcm (A1: integer; A2: integer; A3: integer; A4: integer;
A5: integer; A6: integer; A7: integer;
A8: integer; A9: integer; A10: integer; P: integer)
return integer is
variable M1, M2, M3, M4, M5 , M6, M7, M8, M9, R: integer := 1;
begin
M1 := (A1 * A2)/gcd(A1, A2);
M2 := (M1 * A3)/gcd(M1, A3);
M3 := (M2 * A4)/gcd(M2, A4);
M4 := (M3 * A5)/gcd(M3, A5);
M5 := (M4 * A6)/gcd(M4, A6);
M6 := (M5 * A7)/gcd(M5, A7);
M7 := (M6 * A8)/gcd(M6, A8);
M8 := (M7 * A9)/gcd(M7, A9);
M9 := (M8 * A10)/gcd(M8, A10);
if (M9 < 3) then
R := 10;
elsif ((M9 <= 10) and (M9 >= 3)) then
R := 4 * M9;
elsif (M9 > 1000) then
R := scale_num(M9,3);
else
R := M9 ;
end if;
return R;
end lcm;
-- find the factor of division of the output clock frequency compared to the VCO
function output_counter_value (clk_divide: integer; clk_mult: integer ;
M: integer; N: integer ) return integer is
variable R: integer := 1;
begin
R := (clk_divide * M)/(clk_mult * N);
return R;
end output_counter_value;
-- find the mode of each PLL counter - bypass, even or odd
function counter_mode (duty_cycle: integer; output_counter_value: integer)
return string is
variable R: string (1 to 6) := " ";
variable counter_value: integer := 1;
begin
counter_value := (2*duty_cycle*output_counter_value)/100;
if output_counter_value = 1 then
R := "bypass";
elsif (counter_value REM 2) = 0 then
R := " even";
else
R := " odd";
end if;
return R;
end counter_mode;
-- find the number of VCO clock cycles to hold the output clock high
function counter_high (output_counter_value: integer := 1; duty_cycle: integer)
return integer is
variable R: integer := 1;
variable half_cycle_high : integer := 1;
begin
half_cycle_high := (duty_cycle * output_counter_value *2)/100 ;
if (half_cycle_high REM 2 = 0) then
R := half_cycle_high/2 ;
else
R := (half_cycle_high/2) + 1;
end if;
return R;
end;
-- find the number of VCO clock cycles to hold the output clock low
function counter_low (output_counter_value: integer; duty_cycle: integer)
return integer is
variable R, R1: integer := 1;
variable half_cycle_high : integer := 1;
begin
half_cycle_high := (duty_cycle * output_counter_value*2)/100 ;
if (half_cycle_high REM 2 = 0) then
R1 := half_cycle_high/2 ;
else
R1 := (half_cycle_high/2) + 1;
end if;
R := output_counter_value - R1;
return R;
end;
-- find the smallest time delay amongst t1 to t10
function mintimedelay (t1: integer; t2: integer; t3: integer; t4: integer;
t5: integer; t6: integer; t7: integer; t8: integer;
t9: integer; t10: integer) return integer is
variable m1,m2,m3,m4,m5,m6,m7,m8,m9 : integer := 0;
begin
if (t1 < t2) then m1 := t1; else m1 := t2; end if;
if (m1 < t3) then m2 := m1; else m2 := t3; end if;
if (m2 < t4) then m3 := m2; else m3 := t4; end if;
if (m3 < t5) then m4 := m3; else m4 := t5; end if;
if (m4 < t6) then m5 := m4; else m5 := t6; end if;
if (m5 < t7) then m6 := m5; else m6 := t7; end if;
if (m6 < t8) then m7 := m6; else m7 := t8; end if;
if (m7 < t9) then m8 := m7; else m8 := t9; end if;
if (m8 < t10) then m9 := m8; else m9 := t10; end if;
if (m9 > 0) then return m9; else return 0; end if;
end;
-- find the numerically largest negative number, and return its absolute value
function maxnegabs (t1: integer; t2: integer; t3: integer; t4: integer;
t5: integer; t6: integer; t7: integer; t8: integer;
t9: integer; t10: integer) return integer is
variable m1,m2,m3,m4,m5,m6,m7,m8,m9 : integer := 0;
begin
if (t1 < t2) then m1 := t1; else m1 := t2; end if;
if (m1 < t3) then m2 := m1; else m2 := t3; end if;
if (m2 < t4) then m3 := m2; else m3 := t4; end if;
if (m3 < t5) then m4 := m3; else m4 := t5; end if;
if (m4 < t6) then m5 := m4; else m5 := t6; end if;
if (m5 < t7) then m6 := m5; else m6 := t7; end if;
if (m6 < t8) then m7 := m6; else m7 := t8; end if;
if (m7 < t9) then m8 := m7; else m8 := t9; end if;
if (m8 < t10) then m9 := m8; else m9 := t10; end if;
if (m9 < 0) then return (0 - m9); else return 0; end if;
end;
-- adjust the phase (tap_phase) with the largest negative number (ph_base)
function ph_adjust (tap_phase: integer; ph_base : integer) return integer is
begin
return (tap_phase + ph_base);
end;
-- find the time delay for each PLL counter
function counter_time_delay (clk_time_delay: integer;
m_time_delay: integer; n_time_delay: integer)
return integer is
variable R: integer := 0;
begin
R := clk_time_delay + m_time_delay - n_time_delay;
return R;
end;
-- calculate the given phase shift (in ps) in terms of degrees
function get_phase_degree (phase_shift: integer; clk_period: integer)
return integer is
variable result: integer := 0;
begin
result := ( phase_shift * 360 ) / clk_period;
-- to round up the calculation result
if (result > 0) then
result := result + 1;
elsif (result < 0) then
result := result - 1;
else
result := 0;
end if;
return result;
end;
-- find the number of VCO clock cycles to wait initially before the first rising
-- edge of the output clock
function counter_initial (tap_phase: integer; m: integer; n: integer)
return integer is
variable R: integer;
variable R1: real;
begin
R1 := (real(abs(tap_phase)) * real(m))/(360.0 * real(n)) + 0.5;
-- Note NCSim VHDL had problem in rounding up for 0.5 - 0.99.
-- This checking will ensure that the rounding up is done.
if (R1 >= 0.5) and (R1 <= 1.0) then
R1 := 1.0;
end if;
R := integer(R1);
return R;
end;
-- find which VCO phase tap (0 to 7) to align the rising edge of the output clock to
function counter_ph (tap_phase: integer; m: integer; n: integer) return integer is
variable R: integer := 0;
begin
-- 0.5 is added for proper rounding of the tap_phase.
R := (integer(real(tap_phase * m / n)+ 0.5) REM 360)/45;
return R;
end;
-- convert given string to length 6 by padding with spaces
function translate_string (mode : string) return string is
variable new_mode : string (1 to 6) := " ";
begin
if (mode = "bypass") then
new_mode := "bypass";
elsif (mode = "even") then
new_mode := " even";
elsif (mode = "odd") then
new_mode := " odd";
end if;
return new_mode;
end;
function str2int (s : string) return integer is
variable len : integer := s'length;
variable newdigit : integer := 0;
variable sign : integer := 1;
variable digit : integer := 0;
begin
for i in 1 to len loop
case s(i) is
when '-' =>
if i = 1 then
sign := -1;
else
ASSERT FALSE
REPORT "Illegal Character "& s(i) & "i n string parameter! "
SEVERITY ERROR;
end if;
when '0' =>
digit := 0;
when '1' =>
digit := 1;
when '2' =>
digit := 2;
when '3' =>
digit := 3;
when '4' =>
digit := 4;
when '5' =>
digit := 5;
when '6' =>
digit := 6;
when '7' =>
digit := 7;
when '8' =>
digit := 8;
when '9' =>
digit := 9;
when others =>
ASSERT FALSE
REPORT "Illegal Character "& s(i) & "in string parameter! "
SEVERITY ERROR;
end case;
newdigit := newdigit * 10 + digit;
end loop;
return (sign*newdigit);
end;
function dqs_str2int (s : string) return integer is
variable len : integer := s'length;
variable newdigit : integer := 0;
variable sign : integer := 1;
variable digit : integer := 0;
variable err : boolean := false;
begin
for i in 1 to len loop
case s(i) is
when '-' =>
if i = 1 then
sign := -1;
else
ASSERT FALSE
REPORT "Illegal Character "& s(i) & " in string parameter! "
SEVERITY ERROR;
err := true;
end if;
when '0' =>
digit := 0;
when '1' =>
digit := 1;
when '2' =>
digit := 2;
when '3' =>
digit := 3;
when '4' =>
digit := 4;
when '5' =>
digit := 5;
when '6' =>
digit := 6;
when '7' =>
digit := 7;
when '8' =>
digit := 8;
when '9' =>
digit := 9;
when others =>
-- set error flag
err := true;
end case;
if (err) then
err := false;
else
newdigit := newdigit * 10 + digit;
end if;
end loop;
return (sign*newdigit);
end;
end cycloneiii_pllpack;
--
--
-- DFFE Model
--
--
LIBRARY IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.cycloneiii_atom_pack.all;
entity cycloneiii_dffe is
generic(
TimingChecksOn: Boolean := True;
XOn: Boolean := DefGlitchXOn;
MsgOn: Boolean := DefGlitchMsgOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks;
InstancePath: STRING := "*";
tpd_PRN_Q_negedge : VitalDelayType01 := DefPropDelay01;
tpd_CLRN_Q_negedge : VitalDelayType01 := DefPropDelay01;
tpd_CLK_Q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_ENA_Q_posedge : VitalDelayType01 := DefPropDelay01;
tsetup_D_CLK_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_D_CLK_noedge_negedge : VitalDelayType := DefSetupHoldCnst;
tsetup_ENA_CLK_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_D_CLK_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_D_CLK_noedge_negedge : VitalDelayType := DefSetupHoldCnst;
thold_ENA_CLK_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tipd_D : VitalDelayType01 := DefPropDelay01;
tipd_CLRN : VitalDelayType01 := DefPropDelay01;
tipd_PRN : VitalDelayType01 := DefPropDelay01;
tipd_CLK : VitalDelayType01 := DefPropDelay01;
tipd_ENA : VitalDelayType01 := DefPropDelay01);
port(
Q : out STD_LOGIC := '0';
D : in STD_LOGIC;
CLRN : in STD_LOGIC;
PRN : in STD_LOGIC;
CLK : in STD_LOGIC;
ENA : in STD_LOGIC);
attribute VITAL_LEVEL0 of cycloneiii_dffe : entity is TRUE;
end cycloneiii_dffe;
-- architecture body --
architecture behave of cycloneiii_dffe is
attribute VITAL_LEVEL0 of behave : architecture is TRUE;
signal D_ipd : STD_ULOGIC := 'U';
signal CLRN_ipd : STD_ULOGIC := 'U';
signal PRN_ipd : STD_ULOGIC := 'U';
signal CLK_ipd : STD_ULOGIC := 'U';
signal ENA_ipd : STD_ULOGIC := 'U';
begin
---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
VitalWireDelay (D_ipd, D, tipd_D);
VitalWireDelay (CLRN_ipd, CLRN, tipd_CLRN);
VitalWireDelay (PRN_ipd, PRN, tipd_PRN);
VitalWireDelay (CLK_ipd, CLK, tipd_CLK);
VitalWireDelay (ENA_ipd, ENA, tipd_ENA);
end block;
--------------------
-- BEHAVIOR SECTION
--------------------
VITALBehavior : process (D_ipd, CLRN_ipd, PRN_ipd, CLK_ipd, ENA_ipd)
-- timing check results
VARIABLE Tviol_D_CLK : STD_ULOGIC := '0';
VARIABLE Tviol_ENA_CLK : STD_ULOGIC := '0';
VARIABLE TimingData_D_CLK : VitalTimingDataType := VitalTimingDataInit;
VARIABLE TimingData_ENA_CLK : VitalTimingDataType := VitalTimingDataInit;
-- functionality results
VARIABLE Violation : STD_ULOGIC := '0';
VARIABLE PrevData_Q : STD_LOGIC_VECTOR(0 to 7);
VARIABLE D_delayed : STD_ULOGIC := 'U';
VARIABLE CLK_delayed : STD_ULOGIC := 'U';
VARIABLE ENA_delayed : STD_ULOGIC := 'U';
VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => '0');
-- output glitch detection variables
VARIABLE Q_VitalGlitchData : VitalGlitchDataType;
CONSTANT dffe_Q_tab : VitalStateTableType := (
( L, L, x, x, x, x, x, x, x, L ),
( L, H, L, H, H, x, x, H, x, H ),
( L, H, L, H, x, L, x, H, x, H ),
( L, H, L, x, H, H, x, H, x, H ),
( L, H, H, x, x, x, H, x, x, S ),
( L, H, x, x, x, x, L, x, x, H ),
( L, H, x, x, x, x, H, L, x, S ),
( L, x, L, L, L, x, H, H, x, L ),
( L, x, L, L, x, L, H, H, x, L ),
( L, x, L, x, L, H, H, H, x, L ),
( L, x, x, x, x, x, x, x, x, S ));
begin
------------------------
-- Timing Check Section
------------------------
if (TimingChecksOn) then
VitalSetupHoldCheck (
Violation => Tviol_D_CLK,
TimingData => TimingData_D_CLK,
TestSignal => D_ipd,
TestSignalName => "D",
RefSignal => CLK_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_D_CLK_noedge_posedge,
SetupLow => tsetup_D_CLK_noedge_posedge,
HoldHigh => thold_D_CLK_noedge_posedge,
HoldLow => thold_D_CLK_noedge_posedge,
CheckEnabled => TO_X01(( (NOT PRN_ipd) ) OR ( (NOT CLRN_ipd) ) OR ( (NOT ENA_ipd) )) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/DFFE",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_ENA_CLK,
TimingData => TimingData_ENA_CLK,
TestSignal => ENA_ipd,
TestSignalName => "ENA",
RefSignal => CLK_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_ENA_CLK_noedge_posedge,
SetupLow => tsetup_ENA_CLK_noedge_posedge,
HoldHigh => thold_ENA_CLK_noedge_posedge,
HoldLow => thold_ENA_CLK_noedge_posedge,
CheckEnabled => TO_X01(( (NOT PRN_ipd) ) OR ( (NOT CLRN_ipd) ) ) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/DFFE",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
end if;
-------------------------
-- Functionality Section
-------------------------
Violation := Tviol_D_CLK or Tviol_ENA_CLK;
VitalStateTable(
StateTable => dffe_Q_tab,
DataIn => (
Violation, CLRN_ipd, CLK_delayed, Results(1), D_delayed, ENA_delayed, PRN_ipd, CLK_ipd),
Result => Results,
NumStates => 1,
PreviousDataIn => PrevData_Q);
D_delayed := D_ipd;
CLK_delayed := CLK_ipd;
ENA_delayed := ENA_ipd;
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
OutSignal => Q,
OutSignalName => "Q",
OutTemp => Results(1),
Paths => ( 0 => (PRN_ipd'last_event, tpd_PRN_Q_negedge, TRUE),
1 => (CLRN_ipd'last_event, tpd_CLRN_Q_negedge, TRUE),
2 => (CLK_ipd'last_event, tpd_CLK_Q_posedge, TRUE)),
GlitchData => Q_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
end behave;
--
--
-- cycloneiii_mux21 Model
--
--
LIBRARY IEEE;
use ieee.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use work.cycloneiii_atom_pack.all;
entity cycloneiii_mux21 is
generic(
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
InstancePath: STRING := "*";
tpd_A_MO : VitalDelayType01 := DefPropDelay01;
tpd_B_MO : VitalDelayType01 := DefPropDelay01;
tpd_S_MO : VitalDelayType01 := DefPropDelay01;
tipd_A : VitalDelayType01 := DefPropDelay01;
tipd_B : VitalDelayType01 := DefPropDelay01;
tipd_S : VitalDelayType01 := DefPropDelay01);
port (
A : in std_logic := '0';
B : in std_logic := '0';
S : in std_logic := '0';
MO : out std_logic);
attribute VITAL_LEVEL0 of cycloneiii_mux21 : entity is TRUE;
end cycloneiii_mux21;
architecture AltVITAL of cycloneiii_mux21 is
attribute VITAL_LEVEL0 of AltVITAL : architecture is TRUE;
signal A_ipd, B_ipd, S_ipd : std_logic;
begin
---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
VitalWireDelay (A_ipd, A, tipd_A);
VitalWireDelay (B_ipd, B, tipd_B);
VitalWireDelay (S_ipd, S, tipd_S);
end block;
--------------------
-- BEHAVIOR SECTION
--------------------
VITALBehavior : process (A_ipd, B_ipd, S_ipd)
-- output glitch detection variables
VARIABLE MO_GlitchData : VitalGlitchDataType;
variable tmp_MO : std_logic;
begin
-------------------------
-- Functionality Section
-------------------------
if (S_ipd = '1') then
tmp_MO := B_ipd;
else
tmp_MO := A_ipd;
end if;
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
OutSignal => MO,
OutSignalName => "MO",
OutTemp => tmp_MO,
Paths => ( 0 => (A_ipd'last_event, tpd_A_MO, TRUE),
1 => (B_ipd'last_event, tpd_B_MO, TRUE),
2 => (S_ipd'last_event, tpd_S_MO, TRUE)),
GlitchData => MO_GlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
end AltVITAL;
--
--
-- cycloneiii_mux41 Model
--
--
LIBRARY IEEE;
use ieee.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use work.cycloneiii_atom_pack.all;
entity cycloneiii_mux41 is
generic(
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
InstancePath: STRING := "*";
tpd_IN0_MO : VitalDelayType01 := DefPropDelay01;
tpd_IN1_MO : VitalDelayType01 := DefPropDelay01;
tpd_IN2_MO : VitalDelayType01 := DefPropDelay01;
tpd_IN3_MO : VitalDelayType01 := DefPropDelay01;
tpd_S_MO : VitalDelayArrayType01(1 downto 0) := (OTHERS => DefPropDelay01);
tipd_IN0 : VitalDelayType01 := DefPropDelay01;
tipd_IN1 : VitalDelayType01 := DefPropDelay01;
tipd_IN2 : VitalDelayType01 := DefPropDelay01;
tipd_IN3 : VitalDelayType01 := DefPropDelay01;
tipd_S : VitalDelayArrayType01(1 downto 0) := (OTHERS => DefPropDelay01)
);
port (
IN0 : in std_logic := '0';
IN1 : in std_logic := '0';
IN2 : in std_logic := '0';
IN3 : in std_logic := '0';
S : in std_logic_vector(1 downto 0) := (OTHERS => '0');
MO : out std_logic
);
attribute VITAL_LEVEL0 of cycloneiii_mux41 : entity is TRUE;
end cycloneiii_mux41;
architecture AltVITAL of cycloneiii_mux41 is
attribute VITAL_LEVEL0 of AltVITAL : architecture is TRUE;
signal IN0_ipd, IN1_ipd, IN2_ipd, IN3_ipd : std_logic;
signal S_ipd : std_logic_vector(1 downto 0);
begin
---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
VitalWireDelay (IN0_ipd, IN0, tipd_IN0);
VitalWireDelay (IN1_ipd, IN1, tipd_IN1);
VitalWireDelay (IN2_ipd, IN2, tipd_IN2);
VitalWireDelay (IN3_ipd, IN3, tipd_IN3);
VitalWireDelay (S_ipd(0), S(0), tipd_S(0));
VitalWireDelay (S_ipd(1), S(1), tipd_S(1));
end block;
--------------------
-- BEHAVIOR SECTION
--------------------
VITALBehavior : process (IN0_ipd, IN1_ipd, IN2_ipd, IN3_ipd, S_ipd(0), S_ipd(1))
-- output glitch detection variables
VARIABLE MO_GlitchData : VitalGlitchDataType;
variable tmp_MO : std_logic;
begin
-------------------------
-- Functionality Section
-------------------------
if ((S_ipd(1) = '1') AND (S_ipd(0) = '1')) then
tmp_MO := IN3_ipd;
elsif ((S_ipd(1) = '1') AND (S_ipd(0) = '0')) then
tmp_MO := IN2_ipd;
elsif ((S_ipd(1) = '0') AND (S_ipd(0) = '1')) then
tmp_MO := IN1_ipd;
else
tmp_MO := IN0_ipd;
end if;
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
OutSignal => MO,
OutSignalName => "MO",
OutTemp => tmp_MO,
Paths => ( 0 => (IN0_ipd'last_event, tpd_IN0_MO, TRUE),
1 => (IN1_ipd'last_event, tpd_IN1_MO, TRUE),
2 => (IN2_ipd'last_event, tpd_IN2_MO, TRUE),
3 => (IN3_ipd'last_event, tpd_IN3_MO, TRUE),
4 => (S_ipd(0)'last_event, tpd_S_MO(0), TRUE),
5 => (S_ipd(1)'last_event, tpd_S_MO(1), TRUE)),
GlitchData => MO_GlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
end AltVITAL;
--
--
-- cycloneiii_and1 Model
--
--
LIBRARY IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.VITAL_Timing.all;
use work.cycloneiii_atom_pack.all;
-- entity declaration --
entity cycloneiii_and1 is
generic(
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
InstancePath: STRING := "*";
tpd_IN1_Y : VitalDelayType01 := DefPropDelay01;
tipd_IN1 : VitalDelayType01 := DefPropDelay01);
port(
Y : out STD_LOGIC;
IN1 : in STD_LOGIC);
attribute VITAL_LEVEL0 of cycloneiii_and1 : entity is TRUE;
end cycloneiii_and1;
-- architecture body --
architecture AltVITAL of cycloneiii_and1 is
attribute VITAL_LEVEL0 of AltVITAL : architecture is TRUE;
SIGNAL IN1_ipd : STD_ULOGIC := 'U';
begin
---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
VitalWireDelay (IN1_ipd, IN1, tipd_IN1);
end block;
--------------------
-- BEHAVIOR SECTION
--------------------
VITALBehavior : process (IN1_ipd)
-- functionality results
VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X');
ALIAS Y_zd : STD_ULOGIC is Results(1);
-- output glitch detection variables
VARIABLE Y_GlitchData : VitalGlitchDataType;
begin
-------------------------
-- Functionality Section
-------------------------
Y_zd := TO_X01(IN1_ipd);
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
OutSignal => Y,
OutSignalName => "Y",
OutTemp => Y_zd,
Paths => (0 => (IN1_ipd'last_event, tpd_IN1_Y, TRUE)),
GlitchData => Y_GlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
end AltVITAL;
---------------------------------------------------------------------
--
-- Entity Name : cycloneiii_lcell_comb
--
-- Description : Cyclone II LCELL_COMB VHDL simulation model
--
--
---------------------------------------------------------------------
LIBRARY IEEE;
use IEEE.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.cycloneiii_atom_pack.all;
entity cycloneiii_lcell_comb is
generic (
lut_mask : std_logic_vector(15 downto 0) := (OTHERS => '1');
sum_lutc_input : string := "datac";
dont_touch : string := "off";
lpm_type : string := "cycloneiii_lcell_comb";
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks;
InstancePath: STRING := "*";
tpd_dataa_combout : VitalDelayType01 := DefPropDelay01;
tpd_datab_combout : VitalDelayType01 := DefPropDelay01;
tpd_datac_combout : VitalDelayType01 := DefPropDelay01;
tpd_datad_combout : VitalDelayType01 := DefPropDelay01;
tpd_cin_combout : VitalDelayType01 := DefPropDelay01;
tpd_dataa_cout : VitalDelayType01 := DefPropDelay01;
tpd_datab_cout : VitalDelayType01 := DefPropDelay01;
tpd_datac_cout : VitalDelayType01 := DefPropDelay01;
tpd_datad_cout : VitalDelayType01 := DefPropDelay01;
tpd_cin_cout : VitalDelayType01 := DefPropDelay01;
tipd_dataa : VitalDelayType01 := DefPropDelay01;
tipd_datab : VitalDelayType01 := DefPropDelay01;
tipd_datac : VitalDelayType01 := DefPropDelay01;
tipd_datad : VitalDelayType01 := DefPropDelay01;
tipd_cin : VitalDelayType01 := DefPropDelay01
);
port (
dataa : in std_logic := '1';
datab : in std_logic := '1';
datac : in std_logic := '1';
datad : in std_logic := '1';
cin : in std_logic := '0';
combout : out std_logic;
cout : out std_logic
);
attribute VITAL_LEVEL0 of cycloneiii_lcell_comb : entity is TRUE;
end cycloneiii_lcell_comb;
architecture vital_lcell_comb of cycloneiii_lcell_comb is
attribute VITAL_LEVEL0 of vital_lcell_comb : architecture is TRUE;
signal dataa_ipd : std_logic;
signal datab_ipd : std_logic;
signal datac_ipd : std_logic;
signal datad_ipd : std_logic;
signal cin_ipd : std_logic;
begin
---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
VitalWireDelay (dataa_ipd, dataa, tipd_dataa);
VitalWireDelay (datab_ipd, datab, tipd_datab);
VitalWireDelay (datac_ipd, datac, tipd_datac);
VitalWireDelay (datad_ipd, datad, tipd_datad);
VitalWireDelay (cin_ipd, cin, tipd_cin);
end block;
VITALtiming : process(dataa_ipd, datab_ipd, datac_ipd, datad_ipd,
cin_ipd)
variable combout_VitalGlitchData : VitalGlitchDataType;
variable cout_VitalGlitchData : VitalGlitchDataType;
-- output variables
variable combout_tmp : std_logic;
variable cout_tmp : std_logic;
begin
-- lut_mask_var := lut_mask;
------------------------
-- Timing Check Section
------------------------
if (sum_lutc_input = "datac") then
-- combout
combout_tmp := VitalMUX(data => lut_mask,
dselect => (datad_ipd,
datac_ipd,
datab_ipd,
dataa_ipd));
elsif (sum_lutc_input = "cin") then
-- combout
combout_tmp := VitalMUX(data => lut_mask,
dselect => (datad_ipd,
cin_ipd,
datab_ipd,
dataa_ipd));
end if;
-- cout
cout_tmp := VitalMUX(data => lut_mask,
dselect => ('0',
cin_ipd,
datab_ipd,
dataa_ipd));
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
OutSignal => combout,
OutSignalName => "COMBOUT",
OutTemp => combout_tmp,
Paths => (0 => (dataa_ipd'last_event, tpd_dataa_combout, TRUE),
1 => (datab_ipd'last_event, tpd_datab_combout, TRUE),
2 => (datac_ipd'last_event, tpd_datac_combout, TRUE),
3 => (datad_ipd'last_event, tpd_datad_combout, TRUE),
4 => (cin_ipd'last_event, tpd_cin_combout, TRUE)),
GlitchData => combout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
VitalPathDelay01 (
OutSignal => cout,
OutSignalName => "COUT",
OutTemp => cout_tmp,
Paths => (0 => (dataa_ipd'last_event, tpd_dataa_cout, TRUE),
1 => (datab_ipd'last_event, tpd_datab_cout, TRUE),
2 => (datac_ipd'last_event, tpd_datac_cout, TRUE),
3 => (datad_ipd'last_event, tpd_datad_cout, TRUE),
4 => (cin_ipd'last_event, tpd_cin_cout, TRUE)),
GlitchData => cout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
end vital_lcell_comb;
---------------------------------------------------------------------
--
-- Entity Name : cycloneiii_routing_wire
--
-- Description : Cyclone III Routing Wire VHDL simulation model
--
--
---------------------------------------------------------------------
LIBRARY IEEE;
use IEEE.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.cycloneiii_atom_pack.all;
ENTITY cycloneiii_routing_wire is
generic (
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
tpd_datain_dataout : VitalDelayType01 := DefPropDelay01;
tpd_datainglitch_dataout : VitalDelayType01 := DefPropDelay01;
tipd_datain : VitalDelayType01 := DefPropDelay01
);
PORT (
datain : in std_logic;
dataout : out std_logic
);
attribute VITAL_LEVEL0 of cycloneiii_routing_wire : entity is TRUE;
end cycloneiii_routing_wire;
ARCHITECTURE behave of cycloneiii_routing_wire is
attribute VITAL_LEVEL0 of behave : architecture is TRUE;
signal datain_ipd : std_logic;
signal datainglitch_inert : std_logic;
begin
---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
VitalWireDelay (datain_ipd, datain, tipd_datain);
end block;
VITAL: process(datain_ipd, datainglitch_inert)
variable datain_inert_VitalGlitchData : VitalGlitchDataType;
variable dataout_VitalGlitchData : VitalGlitchDataType;
begin
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
OutSignal => datainglitch_inert,
OutSignalName => "datainglitch_inert",
OutTemp => datain_ipd,
Paths => (1 => (datain_ipd'last_event, tpd_datainglitch_dataout, TRUE)),
GlitchData => datain_inert_VitalGlitchData,
Mode => VitalInertial,
XOn => XOn,
MsgOn => MsgOn );
VitalPathDelay01 (
OutSignal => dataout,
OutSignalName => "dataout",
OutTemp => datainglitch_inert,
Paths => (1 => (datain_ipd'last_event, tpd_datain_dataout, TRUE)),
GlitchData => dataout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
end behave;
--///////////////////////////////////////////////////////////////////////////
--
-- Entity Name : cycloneiii_mn_cntr
--
-- Description : Timing simulation model for the M and N counter. This is a
-- common model for the input counter and the loop feedback
-- counter of the Cyclone III PLL.
--
--///////////////////////////////////////////////////////////////////////////
LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_unsigned.all;
USE IEEE.VITAL_Timing.all;
USE IEEE.VITAL_Primitives.all;
ENTITY cycloneiii_mn_cntr is
PORT( clk : IN std_logic;
reset : IN std_logic := '0';
cout : OUT std_logic;
initial_value : IN integer := 1;
modulus : IN integer := 1;
time_delay : IN integer := 0
);
END cycloneiii_mn_cntr;
ARCHITECTURE behave of cycloneiii_mn_cntr is
begin
process (clk, reset)
variable count : integer := 1;
variable first_rising_edge : boolean := true;
variable tmp_cout : std_logic;
begin
if (reset = '1') then
count := 1;
tmp_cout := '0';
first_rising_edge := true;
elsif (clk'event) then
if (clk = '1' and first_rising_edge) then
first_rising_edge := false;
tmp_cout := clk;
elsif (not first_rising_edge) then
if (count < modulus) then
count := count + 1;
else
count := 1;
tmp_cout := not tmp_cout;
end if;
end if;
end if;
cout <= transport tmp_cout after time_delay * 1 ps;
end process;
end behave;
--/////////////////////////////////////////////////////////////////////////////
--
-- Entity Name : cycloneiii_scale_cntr
--
-- Description : Timing simulation model for the output scale-down counters.
-- This is a common model for the C0, C1, C2, C3, C4 and C5
-- output counters of the Cyclone III PLL.
--
--/////////////////////////////////////////////////////////////////////////////
LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
USE IEEE.VITAL_Timing.all;
USE IEEE.VITAL_Primitives.all;
ENTITY cycloneiii_scale_cntr is
PORT( clk : IN std_logic;
reset : IN std_logic := '0';
initial : IN integer := 1;
high : IN integer := 1;
low : IN integer := 1;
mode : IN string := "bypass";
ph_tap : IN integer := 0;
cout : OUT std_logic
);
END cycloneiii_scale_cntr;
ARCHITECTURE behave of cycloneiii_scale_cntr is
begin
process (clk, reset)
variable tmp_cout : std_logic := '0';
variable count : integer := 1;
variable output_shift_count : integer := 1;
variable first_rising_edge : boolean := false;
begin
if (reset = '1') then
count := 1;
output_shift_count := 1;
tmp_cout := '0';
first_rising_edge := false;
elsif (clk'event) then
if (mode = " off") then
tmp_cout := '0';
elsif (mode = "bypass") then
tmp_cout := clk;
first_rising_edge := true;
elsif (not first_rising_edge) then
if (clk = '1') then
if (output_shift_count = initial) then
tmp_cout := clk;
first_rising_edge := true;
else
output_shift_count := output_shift_count + 1;
end if;
end if;
elsif (output_shift_count < initial) then
if (clk = '1') then
output_shift_count := output_shift_count + 1;
end if;
else
count := count + 1;
if (mode = " even" and (count = (high*2) + 1)) then
tmp_cout := '0';
elsif (mode = " odd" and (count = high*2)) then
tmp_cout := '0';
elsif (count = (high + low)*2 + 1) then
tmp_cout := '1';
count := 1; -- reset count
end if;
end if;
end if;
cout <= transport tmp_cout;
end process;
end behave;
--/////////////////////////////////////////////////////////////////////////////
--
-- Entity Name : cycloneiii_pll_reg
--
-- Description : Simulation model for a simple DFF.
-- This is required for the generation of the bit slip-signals.
-- No timing, powers upto 0.
--
--/////////////////////////////////////////////////////////////////////////////
LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
ENTITY cycloneiii_pll_reg is
PORT( clk : in std_logic;
ena : in std_logic := '1';
d : in std_logic;
clrn : in std_logic := '1';
prn : in std_logic := '1';
q : out std_logic
);
end cycloneiii_pll_reg;
ARCHITECTURE behave of cycloneiii_pll_reg is
begin
process (clk, prn, clrn)
variable q_reg : std_logic := '0';
begin
if (prn = '0') then
q_reg := '1';
elsif (clrn = '0') then
q_reg := '0';
elsif (clk'event and clk = '1' and (ena = '1')) then
q_reg := D;
end if;
Q <= q_reg;
end process;
end behave;
--///////////////////////////////////////////////////////////////////////////
--
-- Entity Name : cycloneiii_pll
--
-- Description : Timing simulation model for the Cyclone III PLL.
-- In the functional mode, it is also the model for the altpll
-- megafunction.
--
-- Limitations : Does not support Spread Spectrum and Bandwidth.
--
-- Outputs : Up to 10 output clocks, each defined by its own set of
-- parameters. Locked output (active high) indicates when the
-- PLL locks. clkbad and activeclock are used for
-- clock switchover to indicate which input clock has gone
-- bad, when the clock switchover initiates and which input
-- clock is being used as the reference, respectively.
-- scandataout is the data output of the serial scan chain.
--
--///////////////////////////////////////////////////////////////////////////
LIBRARY IEEE, std;
USE IEEE.std_logic_1164.all;
USE IEEE.VITAL_Timing.all;
USE IEEE.VITAL_Primitives.all;
USE STD.TEXTIO.all;
USE work.cycloneiii_atom_pack.all;
USE work.cycloneiii_pllpack.all;
USE work.cycloneiii_mn_cntr;
USE work.cycloneiii_scale_cntr;
USE work.cycloneiii_dffe;
USE work.cycloneiii_pll_reg;
-- New Features : The list below outlines key new features in CYCLONEIII:
-- 1. Dynamic Phase Reconfiguration
-- 2. Dynamic PLL Reconfiguration (different protocol)
-- 3. More output counters
ENTITY cycloneiii_pll is
GENERIC (
operation_mode : string := "normal";
pll_type : string := "auto"; -- AUTO/FAST/ENHANCED/LEFT_RIGHT/TOP_BOTTOM
compensate_clock : string := "clock0";
inclk0_input_frequency : integer := 0;
inclk1_input_frequency : integer := 0;
self_reset_on_loss_lock : string := "off";
switch_over_type : string := "auto";
switch_over_counter : integer := 1;
enable_switch_over_counter : string := "off";
bandwidth : integer := 0;
bandwidth_type : string := "auto";
use_dc_coupling : string := "false";
lock_c : integer := 4;
sim_gate_lock_device_behavior : string := "off";
lock_high : integer := 0;
lock_low : integer := 0;
lock_window_ui : string := "0.05";
lock_window : time := 5 ps;
test_bypass_lock_detect : string := "off";
clk0_output_frequency : integer := 0;
clk0_multiply_by : integer := 0;
clk0_divide_by : integer := 0;
clk0_phase_shift : string := "0";
clk0_duty_cycle : integer := 50;
clk1_output_frequency : integer := 0;
clk1_multiply_by : integer := 0;
clk1_divide_by : integer := 0;
clk1_phase_shift : string := "0";
clk1_duty_cycle : integer := 50;
clk2_output_frequency : integer := 0;
clk2_multiply_by : integer := 0;
clk2_divide_by : integer := 0;
clk2_phase_shift : string := "0";
clk2_duty_cycle : integer := 50;
clk3_output_frequency : integer := 0;
clk3_multiply_by : integer := 0;
clk3_divide_by : integer := 0;
clk3_phase_shift : string := "0";
clk3_duty_cycle : integer := 50;
clk4_output_frequency : integer := 0;
clk4_multiply_by : integer := 0;
clk4_divide_by : integer := 0;
clk4_phase_shift : string := "0";
clk4_duty_cycle : integer := 50;
pfd_min : integer := 0;
pfd_max : integer := 0;
vco_min : integer := 0;
vco_max : integer := 0;
vco_center : integer := 0;
-- ADVANCED USER PARAMETERS
m_initial : integer := 1;
m : integer := 0;
n : integer := 1;
c0_high : integer := 1;
c0_low : integer := 1;
c0_initial : integer := 1;
c0_mode : string := "bypass";
c0_ph : integer := 0;
c1_high : integer := 1;
c1_low : integer := 1;
c1_initial : integer := 1;
c1_mode : string := "bypass";
c1_ph : integer := 0;
c2_high : integer := 1;
c2_low : integer := 1;
c2_initial : integer := 1;
c2_mode : string := "bypass";
c2_ph : integer := 0;
c3_high : integer := 1;
c3_low : integer := 1;
c3_initial : integer := 1;
c3_mode : string := "bypass";
c3_ph : integer := 0;
c4_high : integer := 1;
c4_low : integer := 1;
c4_initial : integer := 1;
c4_mode : string := "bypass";
c4_ph : integer := 0;
m_ph : integer := 0;
clk0_counter : string := "unused";
clk1_counter : string := "unused";
clk2_counter : string := "unused";
clk3_counter : string := "unused";
clk4_counter : string := "unused";
c1_use_casc_in : string := "off";
c2_use_casc_in : string := "off";
c3_use_casc_in : string := "off";
c4_use_casc_in : string := "off";
m_test_source : integer := -1;
c0_test_source : integer := -1;
c1_test_source : integer := -1;
c2_test_source : integer := -1;
c3_test_source : integer := -1;
c4_test_source : integer := -1;
vco_multiply_by : integer := 0;
vco_divide_by : integer := 0;
vco_post_scale : integer := 1;
vco_frequency_control : string := "auto";
vco_phase_shift_step : integer := 0;
charge_pump_current : integer := 10;
loop_filter_r : string := "1.0";
loop_filter_c : integer := 0;
pll_compensation_delay : integer := 0;
simulation_type : string := "functional";
lpm_type : string := "cycloneiii_pll";
clk0_use_even_counter_mode : string := "off";
clk1_use_even_counter_mode : string := "off";
clk2_use_even_counter_mode : string := "off";
clk3_use_even_counter_mode : string := "off";
clk4_use_even_counter_mode : string := "off";
clk0_use_even_counter_value : string := "off";
clk1_use_even_counter_value : string := "off";
clk2_use_even_counter_value : string := "off";
clk3_use_even_counter_value : string := "off";
clk4_use_even_counter_value : string := "off";
-- Test only
init_block_reset_a_count : integer := 1;
init_block_reset_b_count : integer := 1;
charge_pump_current_bits : integer := 0;
lock_window_ui_bits : integer := 0;
loop_filter_c_bits : integer := 0;
loop_filter_r_bits : integer := 0;
test_counter_c0_delay_chain_bits : integer := 0;
test_counter_c1_delay_chain_bits : integer := 0;
test_counter_c2_delay_chain_bits : integer := 0;
test_counter_c3_delay_chain_bits : integer := 0;
test_counter_c4_delay_chain_bits : integer := 0;
test_counter_c5_delay_chain_bits : integer := 0;
test_counter_m_delay_chain_bits : integer := 0;
test_counter_n_delay_chain_bits : integer := 0;
test_feedback_comp_delay_chain_bits : integer := 0;
test_input_comp_delay_chain_bits : integer := 0;
test_volt_reg_output_mode_bits : integer := 0;
test_volt_reg_output_voltage_bits : integer := 0;
test_volt_reg_test_mode : string := "false";
vco_range_detector_high_bits : integer := 0;
vco_range_detector_low_bits : integer := 0;
-- Simulation only generics
family_name : string := "Cyclone III";
-- VITAL generics
XOn : Boolean := DefGlitchXOn;
MsgOn : Boolean := DefGlitchMsgOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
TimingChecksOn : Boolean := true;
InstancePath : STRING := "*";
tipd_inclk : VitalDelayArrayType01(1 downto 0) := (OTHERS => DefPropDelay01);
tipd_ena : VitalDelayType01 := DefPropDelay01;
tipd_pfdena : VitalDelayType01 := DefPropDelay01;
tipd_areset : VitalDelayType01 := DefPropDelay01;
tipd_fbin : VitalDelayType01 := DefPropDelay01;
tipd_scanclk : VitalDelayType01 := DefPropDelay01;
tipd_scanclkena : VitalDelayType01 := DefPropDelay01;
tipd_scandata : VitalDelayType01 := DefPropDelay01;
tipd_configupdate : VitalDelayType01 := DefPropDelay01;
tipd_clkswitch : VitalDelayType01 := DefPropDelay01;
tipd_phaseupdown : VitalDelayType01 := DefPropDelay01;
tipd_phasecounterselect : VitalDelayArrayType01(2 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_phasestep : VitalDelayType01 := DefPropDelay01;
tsetup_scandata_scanclk_noedge_negedge : VitalDelayType := DefSetupHoldCnst;
thold_scandata_scanclk_noedge_negedge : VitalDelayType := DefSetupHoldCnst;
tsetup_scanclkena_scanclk_noedge_negedge : VitalDelayType := DefSetupHoldCnst;
thold_scanclkena_scanclk_noedge_negedge : VitalDelayType := DefSetupHoldCnst;
use_vco_bypass : string := "false"
);
PORT
(
inclk : in std_logic_vector(1 downto 0);
fbin : in std_logic := '0';
fbout : out std_logic;
clkswitch : in std_logic := '0';
areset : in std_logic := '0';
pfdena : in std_logic := '1';
scandata : in std_logic := '0';
scanclk : in std_logic := '0';
scanclkena : in std_logic := '0';
configupdate : in std_logic := '0';
clk : out std_logic_vector(4 downto 0);
phasecounterselect : in std_logic_vector(2 downto 0) := "000";
phaseupdown : in std_logic := '0';
phasestep : in std_logic := '0';
clkbad : out std_logic_vector(1 downto 0);
activeclock : out std_logic;
locked : out std_logic;
scandataout : out std_logic;
scandone : out std_logic;
phasedone : out std_logic;
vcooverrange : out std_logic;
vcounderrange : out std_logic
);
END cycloneiii_pll;
ARCHITECTURE vital_pll of cycloneiii_pll is
TYPE int_array is ARRAY(NATURAL RANGE <>) of integer;
TYPE str_array is ARRAY(NATURAL RANGE <>) of string(1 to 6);
TYPE str_array1 is ARRAY(NATURAL RANGE <>) of string(1 to 9);
TYPE std_logic_array is ARRAY(NATURAL RANGE <>) of std_logic;
-- internal advanced parameter signals
signal i_vco_min : integer;
signal i_vco_max : integer;
signal i_vco_center : integer;
signal i_pfd_min : integer;
signal i_pfd_max : integer;
signal c_ph_val : int_array(0 to 4) := (OTHERS => 0);
signal c_ph_val_tmp : int_array(0 to 4) := (OTHERS => 0);
signal c_high_val : int_array(0 to 4) := (OTHERS => 1);
signal c_low_val : int_array(0 to 4) := (OTHERS => 1);
signal c_initial_val : int_array(0 to 4) := (OTHERS => 1);
signal c_mode_val : str_array(0 to 4);
-- old values
signal c_high_val_old : int_array(0 to 4) := (OTHERS => 1);
signal c_low_val_old : int_array(0 to 4) := (OTHERS => 1);
signal c_ph_val_old : int_array(0 to 4) := (OTHERS => 0);
signal c_mode_val_old : str_array(0 to 4);
-- hold registers
signal c_high_val_hold : int_array(0 to 4) := (OTHERS => 1);
signal c_low_val_hold : int_array(0 to 4) := (OTHERS => 1);
signal c_ph_val_hold : int_array(0 to 4) := (OTHERS => 0);
signal c_mode_val_hold : str_array(0 to 4);
-- temp registers
signal sig_c_ph_val_tmp : int_array(0 to 4) := (OTHERS => 0);
signal c_ph_val_orig : int_array(0 to 4) := (OTHERS => 0);
signal real_lock_high : integer := 0;
signal i_clk4_counter : integer := 4;
signal i_clk3_counter : integer := 3;
signal i_clk2_counter : integer := 2;
signal i_clk1_counter : integer := 1;
signal i_clk0_counter : integer := 0;
signal i_charge_pump_current : integer;
signal i_loop_filter_r : integer;
-- end internal advanced parameter signals
-- CONSTANTS
CONSTANT SCAN_CHAIN : integer := 144;
CONSTANT GPP_SCAN_CHAIN : integer := 234;
CONSTANT FAST_SCAN_CHAIN : integer := 180;
CONSTANT cntrs : str_array(4 downto 0) := (" C4", " C3", " C2", " C1", " C0");
CONSTANT ss_cntrs : str_array(0 to 3) := (" M", " M2", " N", " N2");
CONSTANT loop_filter_c_arr : int_array(0 to 3) := (0,0,0,0);
CONSTANT fpll_loop_filter_c_arr : int_array(0 to 3) := (0,0,0,0);
CONSTANT charge_pump_curr_arr : int_array(0 to 15) := (0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0);
CONSTANT num_phase_taps : integer := 8;
-- signals
signal vcc : std_logic := '1';
signal fbclk : std_logic;
signal refclk : std_logic;
signal vco_over : std_logic := '0';
signal vco_under : std_logic := '1';
signal pll_locked : boolean := false;
signal c_clk : std_logic_array(0 to 4);
signal vco_out : std_logic_vector(7 downto 0) := (OTHERS => '0');
-- signals to assign values to counter params
signal m_val : integer := 1;
signal n_val : integer := 1;
signal m_ph_val : integer := 0;
signal m_ph_initial : integer := 0;
signal m_ph_val_tmp : integer := 0;
signal m_initial_val : integer := m_initial;
signal m_mode_val : string(1 to 6) := " ";
signal n_mode_val : string(1 to 6) := " ";
signal lfc_val : integer := 0;
signal cp_curr_val : integer := 0;
signal lfr_val : string(1 to 2) := " ";
signal cp_curr_old_bit_setting : std_logic_vector(14 to 16) := (OTHERS => '0');
signal cp_curr_val_bit_setting : std_logic_vector(14 to 16) := (OTHERS => '0');
signal lfr_old_bit_setting : std_logic_vector(3 to 7) := (OTHERS => '0');
signal lfr_val_bit_setting : std_logic_vector(3 to 7) := (OTHERS => '0');
signal lfc_old_bit_setting : std_logic_vector(1 to 2) := (OTHERS => '0');
signal lfc_val_bit_setting : std_logic_vector(1 to 2) := (OTHERS => '0');
signal pll_reconfig_display_full_setting : boolean := FALSE; -- display full setting, change to true
-- old values
signal m_val_old : integer := 1;
signal n_val_old : integer := 1;
signal m_mode_val_old : string(1 to 6) := " ";
signal n_mode_val_old : string(1 to 6) := " ";
signal m_ph_val_old : integer := 0;
signal lfc_old : integer := 0;
signal cp_curr_old : integer := 0;
signal lfr_old : string(1 to 2) := " ";
signal num_output_cntrs : integer := 5;
signal scanclk_period : time := 1 ps;
signal scan_data : std_logic_vector(0 to 143) := (OTHERS => '0');
signal clk_pfd : std_logic_vector(0 to 4);
signal clk0_tmp : std_logic;
signal clk1_tmp : std_logic;
signal clk2_tmp : std_logic;
signal clk3_tmp : std_logic;
signal clk4_tmp : std_logic;
signal update_conf_latches : std_logic := '0';
signal update_conf_latches_reg : std_logic := '0';
signal clkin : std_logic := '0';
signal gate_locked : std_logic := '0';
signal pfd_locked : std_logic := '0';
signal lock : std_logic := '0';
signal about_to_lock : boolean := false;
signal reconfig_err : boolean := false;
signal inclk_c0 : std_logic;
signal inclk_c1 : std_logic;
signal inclk_c2 : std_logic;
signal inclk_c3 : std_logic;
signal inclk_c4 : std_logic;
signal inclk_m : std_logic;
signal devpor : std_logic;
signal devclrn : std_logic;
signal inclk0_ipd : std_logic;
signal inclk1_ipd : std_logic;
signal pfdena_ipd : std_logic;
signal areset_ipd : std_logic;
signal fbin_ipd : std_logic;
signal scanclk_ipd : std_logic;
signal scanclkena_ipd, scanclkena_reg : std_logic;
signal scandata_ipd : std_logic;
signal clkswitch_ipd : std_logic;
signal phasecounterselect_ipd : std_logic_vector(2 downto 0);
signal phaseupdown_ipd : std_logic;
signal phasestep_ipd : std_logic;
signal configupdate_ipd : std_logic;
-- registered signals
signal sig_offset : time := 0 ps;
signal sig_refclk_time : time := 0 ps;
signal sig_fbclk_period : time := 0 ps;
signal sig_vco_period_was_phase_adjusted : boolean := false;
signal sig_phase_adjust_was_scheduled : boolean := false;
signal sig_stop_vco : std_logic := '0';
signal sig_m_times_vco_period : time := 0 ps;
signal sig_new_m_times_vco_period : time := 0 ps;
signal sig_got_refclk_posedge : boolean := false;
signal sig_got_fbclk_posedge : boolean := false;
signal sig_got_second_refclk : boolean := false;
signal m_delay : integer := 0;
signal n_delay : integer := 0;
signal inclk1_tmp : std_logic := '0';
signal reset_low : std_logic := '0';
-- Phase Reconfig
SIGNAL phasecounterselect_reg : std_logic_vector(2 DOWNTO 0);
SIGNAL phaseupdown_reg : std_logic := '0';
SIGNAL phasestep_reg : std_logic := '0';
SIGNAL phasestep_high_count : integer := 0;
SIGNAL update_phase : std_logic := '0';
signal scandataout_tmp : std_logic := '0';
signal scandata_in : std_logic := '0';
signal scandata_out : std_logic := '0';
signal scandone_tmp : std_logic := '1';
signal initiate_reconfig : std_logic := '0';
signal sig_refclk_period : time := (inclk0_input_frequency * 1 ps) * n;
signal schedule_vco : std_logic := '0';
signal areset_ena_sig : std_logic := '0';
signal pll_in_test_mode : boolean := false;
signal inclk_c_from_vco : std_logic_array(0 to 4);
signal inclk_m_from_vco : std_logic;
COMPONENT cycloneiii_mn_cntr
PORT (
clk : IN std_logic;
reset : IN std_logic := '0';
cout : OUT std_logic;
initial_value : IN integer := 1;
modulus : IN integer := 1;
time_delay : IN integer := 0
);
END COMPONENT;
COMPONENT cycloneiii_scale_cntr
PORT (
clk : IN std_logic;
reset : IN std_logic := '0';
cout : OUT std_logic;
initial : IN integer := 1;
high : IN integer := 1;
low : IN integer := 1;
mode : IN string := "bypass";
ph_tap : IN integer := 0
);
END COMPONENT;
COMPONENT cycloneiii_dffe
GENERIC(
TimingChecksOn: Boolean := true;
InstancePath: STRING := "*";
XOn: Boolean := DefGlitchXOn;
MsgOn: Boolean := DefGlitchMsgOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks;
tpd_PRN_Q_negedge : VitalDelayType01 := DefPropDelay01;
tpd_CLRN_Q_negedge : VitalDelayType01 := DefPropDelay01;
tpd_CLK_Q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_ENA_Q_posedge : VitalDelayType01 := DefPropDelay01;
tsetup_D_CLK_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_D_CLK_noedge_negedge : VitalDelayType := DefSetupHoldCnst;
tsetup_ENA_CLK_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_D_CLK_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_D_CLK_noedge_negedge : VitalDelayType := DefSetupHoldCnst;
thold_ENA_CLK_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tipd_D : VitalDelayType01 := DefPropDelay01;
tipd_CLRN : VitalDelayType01 := DefPropDelay01;
tipd_PRN : VitalDelayType01 := DefPropDelay01;
tipd_CLK : VitalDelayType01 := DefPropDelay01;
tipd_ENA : VitalDelayType01 := DefPropDelay01);
PORT(
Q : out STD_LOGIC := '0';
D : in STD_LOGIC := '1';
CLRN : in STD_LOGIC := '1';
PRN : in STD_LOGIC := '1';
CLK : in STD_LOGIC := '0';
ENA : in STD_LOGIC := '1');
END COMPONENT;
COMPONENT cycloneiii_pll_reg
PORT(
Q : out STD_LOGIC := '0';
D : in STD_LOGIC := '1';
CLRN : in STD_LOGIC := '1';
PRN : in STD_LOGIC := '1';
CLK : in STD_LOGIC := '0';
ENA : in STD_LOGIC := '1');
END COMPONENT;
begin
----------------------
-- INPUT PATH DELAYs
----------------------
WireDelay : block
begin
VitalWireDelay (inclk0_ipd, inclk(0), tipd_inclk(0));
VitalWireDelay (inclk1_ipd, inclk(1), tipd_inclk(1));
VitalWireDelay (areset_ipd, areset, tipd_areset);
VitalWireDelay (pfdena_ipd, pfdena, tipd_pfdena);
VitalWireDelay (scanclk_ipd, scanclk, tipd_scanclk);
VitalWireDelay (scanclkena_ipd, scanclkena, tipd_scanclkena);
VitalWireDelay (scandata_ipd, scandata, tipd_scandata);
VitalWireDelay (configupdate_ipd, configupdate, tipd_configupdate);
VitalWireDelay (clkswitch_ipd, clkswitch, tipd_clkswitch);
VitalWireDelay (phaseupdown_ipd, phaseupdown, tipd_phaseupdown);
VitalWireDelay (phasestep_ipd, phasestep, tipd_phasestep);
VitalWireDelay (phasecounterselect_ipd(0), phasecounterselect(0), tipd_phasecounterselect(0));
VitalWireDelay (phasecounterselect_ipd(1), phasecounterselect(1), tipd_phasecounterselect(1));
VitalWireDelay (phasecounterselect_ipd(2), phasecounterselect(2), tipd_phasecounterselect(2));
end block;
inclk_m <= fbclk when m_test_source = 0 else
refclk when m_test_source = 1 else
inclk_m_from_vco;
areset_ena_sig <= areset_ipd or sig_stop_vco;
pll_in_test_mode <= true when (m_test_source /= -1 or c0_test_source /= -1 or
c1_test_source /= -1 or c2_test_source /= -1 or
c3_test_source /= -1 or c4_test_source /= -1)
else false;
real_lock_high <= lock_high WHEN (sim_gate_lock_device_behavior = "on") ELSE 0;
m1 : cycloneiii_mn_cntr
port map ( clk => inclk_m,
reset => areset_ena_sig,
cout => fbclk,
initial_value => m_initial_val,
modulus => m_val,
time_delay => m_delay
);
-- add delta delay to inclk1 to ensure inclk0 and inclk1 are processed
-- in different simulation deltas.
inclk1_tmp <= inclk1_ipd;
process (inclk0_ipd, inclk1_tmp, clkswitch_ipd)
variable input_value : std_logic := '0';
variable current_clock : integer := 0;
variable clk0_count, clk1_count : integer := 0;
variable clk0_is_bad, clk1_is_bad : std_logic := '0';
variable primary_clk_is_bad : boolean := false;
variable current_clk_is_bad : boolean := false;
variable got_curr_clk_falling_edge_after_clkswitch : boolean := false;
variable switch_over_count : integer := 0;
variable active_clock : std_logic := '0';
variable external_switch : boolean := false;
begin
if (now = 0 ps) then
if (switch_over_type = "manual" and clkswitch_ipd = '1') then
current_clock := 1;
active_clock := '1';
end if;
end if;
if (clkswitch_ipd'event and clkswitch_ipd = '1' and switch_over_type = "auto") then
external_switch := true;
elsif (switch_over_type = "manual") then
if (clkswitch_ipd'event and clkswitch_ipd = '1') then
if (current_clock = 0) then
current_clock := 1;
active_clock := '1';
clkin <= transport inclk1_tmp;
elsif (current_clock = 1) then
current_clock := 0;
active_clock := '0';
clkin <= transport inclk0_ipd;
end if;
end if;
end if;
-- save the current inclk event value
if (inclk0_ipd'event) then
input_value := inclk0_ipd;
elsif (inclk1_tmp'event) then
input_value := inclk1_tmp;
end if;
-- check if either input clk is bad
if (inclk0_ipd'event and inclk0_ipd = '1') then
clk0_count := clk0_count + 1;
clk0_is_bad := '0';
clk1_count := 0;
if (clk0_count > 2) then
-- no event on other clk for 2 cycles
clk1_is_bad := '1';
if (current_clock = 1) then
current_clk_is_bad := true;
end if;
end if;
end if;
if (inclk1_tmp'event and inclk1_tmp = '1') then
clk1_count := clk1_count + 1;
clk1_is_bad := '0';
clk0_count := 0;
if (clk1_count > 2) then
-- no event on other clk for 2 cycles
clk0_is_bad := '1';
if (current_clock = 0) then
current_clk_is_bad := true;
end if;
end if;
end if;
-- check if the bad clk is the primary clock
if (clk0_is_bad = '1') then
primary_clk_is_bad := true;
else
primary_clk_is_bad := false;
end if;
-- actual switching
if (inclk0_ipd'event and current_clock = 0) then
if (external_switch) then
if (not got_curr_clk_falling_edge_after_clkswitch) then
if (inclk0_ipd = '0') then
got_curr_clk_falling_edge_after_clkswitch := true;
end if;
clkin <= transport inclk0_ipd;
end if;
else
clkin <= transport inclk0_ipd;
end if;
elsif (inclk1_tmp'event and current_clock = 1) then
if (external_switch) then
if (not got_curr_clk_falling_edge_after_clkswitch) then
if (inclk1_tmp = '0') then
got_curr_clk_falling_edge_after_clkswitch := true;
end if;
clkin <= transport inclk1_tmp;
end if;
else
clkin <= transport inclk1_tmp;
end if;
else
if (input_value = '1' and enable_switch_over_counter = "on" and primary_clk_is_bad) then
switch_over_count := switch_over_count + 1;
end if;
if (input_value = '0') then
if (external_switch and (got_curr_clk_falling_edge_after_clkswitch or current_clk_is_bad)) or (primary_clk_is_bad and clkswitch_ipd /= '1' and (enable_switch_over_counter = "off" or switch_over_count = switch_over_counter)) then
got_curr_clk_falling_edge_after_clkswitch := false;
if (current_clock = 0) then
current_clock := 1;
else
current_clock := 0;
end if;
active_clock := not active_clock;
switch_over_count := 0;
external_switch := false;
current_clk_is_bad := false;
end if;
end if;
end if;
-- schedule outputs
clkbad(0) <= clk0_is_bad;
clkbad(1) <= clk1_is_bad;
activeclock <= active_clock;
end process;
n1 : cycloneiii_mn_cntr
port map (
clk => clkin,
reset => areset_ipd,
cout => refclk,
initial_value => n_val,
modulus => n_val);
inclk_c0 <= refclk when c0_test_source = 1 else
fbclk when c0_test_source = 0 else
inclk_c_from_vco(0);
c0 : cycloneiii_scale_cntr
port map (
clk => inclk_c0,
reset => areset_ena_sig,
cout => c_clk(0),
initial => c_initial_val(0),
high => c_high_val(0),
low => c_low_val(0),
mode => c_mode_val(0),
ph_tap => c_ph_val(0));
inclk_c1 <= refclk when c1_test_source = 1 else
fbclk when c1_test_source = 0 else
c_clk(0) when c1_use_casc_in = "on" else
inclk_c_from_vco(1);
c1 : cycloneiii_scale_cntr
port map (
clk => inclk_c1,
reset => areset_ena_sig,
cout => c_clk(1),
initial => c_initial_val(1),
high => c_high_val(1),
low => c_low_val(1),
mode => c_mode_val(1),
ph_tap => c_ph_val(1));
inclk_c2 <= refclk when c2_test_source = 1 else
fbclk when c2_test_source = 0 else
c_clk(1) when c2_use_casc_in = "on" else
inclk_c_from_vco(2);
c2 : cycloneiii_scale_cntr
port map (
clk => inclk_c2,
reset => areset_ena_sig,
cout => c_clk(2),
initial => c_initial_val(2),
high => c_high_val(2),
low => c_low_val(2),
mode => c_mode_val(2),
ph_tap => c_ph_val(2));
inclk_c3 <= refclk when c3_test_source = 1 else
fbclk when c3_test_source = 0 else
c_clk(2) when c3_use_casc_in = "on" else
inclk_c_from_vco(3);
c3 : cycloneiii_scale_cntr
port map (
clk => inclk_c3,
reset => areset_ena_sig,
cout => c_clk(3),
initial => c_initial_val(3),
high => c_high_val(3),
low => c_low_val(3),
mode => c_mode_val(3),
ph_tap => c_ph_val(3));
inclk_c4 <= refclk when c4_test_source = 1 else
fbclk when c4_test_source = 0 else
c_clk(3) when (c4_use_casc_in = "on") else
inclk_c_from_vco(4);
c4 : cycloneiii_scale_cntr
port map (
clk => inclk_c4,
reset => areset_ena_sig,
cout => c_clk(4),
initial => c_initial_val(4),
high => c_high_val(4),
low => c_low_val(4),
mode => c_mode_val(4),
ph_tap => c_ph_val(4));
process(inclk_c0, inclk_c1, areset_ipd, sig_stop_vco)
variable c0_got_first_rising_edge : boolean := false;
variable c0_count : integer := 2;
variable c0_initial_count : integer := 1;
variable c0_tmp, c1_tmp : std_logic := '0';
variable c1_got_first_rising_edge : boolean := false;
variable c1_count : integer := 2;
variable c1_initial_count : integer := 1;
begin
if (areset_ipd = '1' or sig_stop_vco = '1') then
c0_count := 2;
c1_count := 2;
c0_initial_count := 1;
c1_initial_count := 1;
c0_got_first_rising_edge := false;
c1_got_first_rising_edge := false;
else
if (not c0_got_first_rising_edge) then
if (inclk_c0'event and inclk_c0 = '1') then
if (c0_initial_count = c_initial_val(0)) then
c0_got_first_rising_edge := true;
else
c0_initial_count := c0_initial_count + 1;
end if;
end if;
elsif (inclk_c0'event) then
c0_count := c0_count + 1;
if (c0_count = (c_high_val(0) + c_low_val(0)) * 2) then
c0_count := 1;
end if;
end if;
if (inclk_c0'event and inclk_c0 = '0') then
if (c0_count = 1) then
c0_tmp := '1';
c0_got_first_rising_edge := false;
else
c0_tmp := '0';
end if;
end if;
if (not c1_got_first_rising_edge) then
if (inclk_c1'event and inclk_c1 = '1') then
if (c1_initial_count = c_initial_val(1)) then
c1_got_first_rising_edge := true;
else
c1_initial_count := c1_initial_count + 1;
end if;
end if;
elsif (inclk_c1'event) then
c1_count := c1_count + 1;
if (c1_count = (c_high_val(1) + c_low_val(1)) * 2) then
c1_count := 1;
end if;
end if;
if (inclk_c1'event and inclk_c1 = '0') then
if (c1_count = 1) then
c1_tmp := '1';
c1_got_first_rising_edge := false;
else
c1_tmp := '0';
end if;
end if;
end if;
end process;
locked <= pfd_locked WHEN (test_bypass_lock_detect = "on") ELSE
lock;
process (scandone_tmp)
variable buf : line;
begin
if (scandone_tmp'event and scandone_tmp = '1') then
if (reconfig_err = false) then
ASSERT false REPORT "PLL Reprogramming completed with the following values (Values in parantheses indicate values before reprogramming) :" severity note;
write (buf, string'(" N modulus = "));
write (buf, n_val);
write (buf, string'(" ( "));
write (buf, n_val_old);
write (buf, string'(" )"));
writeline (output, buf);
write (buf, string'(" M modulus = "));
write (buf, m_val);
write (buf, string'(" ( "));
write (buf, m_val_old);
write (buf, string'(" )"));
writeline (output, buf);
write (buf, string'(" M ph_tap = "));
write (buf, m_ph_val);
write (buf, string'(" ( "));
write (buf, m_ph_val_old);
write (buf, string'(" )"));
writeline (output, buf);
for i in 0 to (num_output_cntrs-1) loop
write (buf, cntrs(i));
write (buf, string'(" : high = "));
write (buf, c_high_val(i));
write (buf, string'(" ("));
write (buf, c_high_val_old(i));
write (buf, string'(") "));
write (buf, string'(" , low = "));
write (buf, c_low_val(i));
write (buf, string'(" ("));
write (buf, c_low_val_old(i));
write (buf, string'(") "));
write (buf, string'(" , mode = "));
write (buf, c_mode_val(i));
write (buf, string'(" ("));
write (buf, c_mode_val_old(i));
write (buf, string'(") "));
write (buf, string'(" , phase tap = "));
write (buf, c_ph_val(i));
write (buf, string'(" ("));
write (buf, c_ph_val_old(i));
write (buf, string'(") "));
writeline(output, buf);
end loop;
IF (pll_reconfig_display_full_setting) THEN
write (buf, string'(" Charge Pump Current (uA) = "));
write (buf, cp_curr_val);
write (buf, string'(" ( "));
write (buf, cp_curr_old);
write (buf, string'(" ) "));
writeline (output, buf);
write (buf, string'(" Loop Filter Capacitor (pF) = "));
write (buf, lfc_val);
write (buf, string'(" ( "));
write (buf, lfc_old);
write (buf, string'(" ) "));
writeline (output, buf);
write (buf, string'(" Loop Filter Resistor (Kohm) = "));
write (buf, lfr_val);
write (buf, string'(" ( "));
write (buf, lfr_old);
write (buf, string'(" ) "));
writeline (output, buf);
ELSE
write (buf, string'(" Charge Pump Current (bit setting) = "));
write (buf, alt_conv_integer(cp_curr_val_bit_setting));
write (buf, string'(" ( "));
write (buf, alt_conv_integer(cp_curr_old_bit_setting));
write (buf, string'(" ) "));
writeline (output, buf);
write (buf, string'(" Loop Filter Capacitor (bit setting) = "));
write (buf, alt_conv_integer(lfc_val_bit_setting));
write (buf, string'(" ( "));
write (buf, alt_conv_integer(lfc_old_bit_setting));
write (buf, string'(" ) "));
writeline (output, buf);
write (buf, string'(" Loop Filter Resistor (bit setting) = "));
write (buf, alt_conv_integer(lfr_val_bit_setting));
write (buf, string'(" ( "));
write (buf, alt_conv_integer(lfr_old_bit_setting));
write (buf, string'(" ) "));
writeline (output, buf);
END IF;
cp_curr_old_bit_setting <= cp_curr_val_bit_setting;
lfc_old_bit_setting <= lfc_val_bit_setting;
lfr_old_bit_setting <= lfr_val_bit_setting;
else ASSERT false REPORT "Errors were encountered during PLL reprogramming. Please refer to error/warning messages above." severity warning;
end if;
end if;
end process;
update_conf_latches <= configupdate_ipd;
process (scandone_tmp,areset_ipd,update_conf_latches, c_clk(0), c_clk(1), c_clk(2), c_clk(3), c_clk(4), vco_out, fbclk, scanclk_ipd)
variable init : boolean := true;
variable low, high : std_logic_vector(7 downto 0);
variable low_fast, high_fast : std_logic_vector(3 downto 0);
variable mode : string(1 to 6) := "bypass";
variable is_error : boolean := false;
variable m_tmp, n_tmp : std_logic_vector(8 downto 0);
variable lfr_val_tmp : string(1 to 2) := " ";
variable c_high_val_tmp,c_hval : int_array(0 to 4) := (OTHERS => 1);
variable c_low_val_tmp,c_lval : int_array(0 to 4) := (OTHERS => 1);
variable c_mode_val_tmp : str_array(0 to 4);
variable m_val_tmp : integer := 0;
variable c0_rising_edge_transfer_done : boolean := false;
variable c1_rising_edge_transfer_done : boolean := false;
variable c2_rising_edge_transfer_done : boolean := false;
variable c3_rising_edge_transfer_done : boolean := false;
variable c4_rising_edge_transfer_done : boolean := false;
-- variables for scaling of multiply_by and divide_by values
variable i_clk0_mult_by : integer := 1;
variable i_clk0_div_by : integer := 1;
variable i_clk1_mult_by : integer := 1;
variable i_clk1_div_by : integer := 1;
variable i_clk2_mult_by : integer := 1;
variable i_clk2_div_by : integer := 1;
variable i_clk3_mult_by : integer := 1;
variable i_clk3_div_by : integer := 1;
variable i_clk4_mult_by : integer := 1;
variable i_clk4_div_by : integer := 1;
variable max_d_value : integer := 1;
variable new_multiplier : integer := 1;
-- internal variables for storing the phase shift number.(used in lvds mode only)
variable i_clk0_phase_shift : integer := 1;
variable i_clk1_phase_shift : integer := 1;
variable i_clk2_phase_shift : integer := 1;
-- user to advanced variables
variable max_neg_abs : integer := 0;
variable i_m_initial : integer;
variable i_m : integer := 1;
variable i_n : integer := 1;
variable i_c_high : int_array(0 to 4);
variable i_c_low : int_array(0 to 4);
variable i_c_initial : int_array(0 to 4);
variable i_c_ph : int_array(0 to 4);
variable i_c_mode : str_array(0 to 4);
variable i_m_ph : integer;
variable output_count : integer;
variable new_divisor : integer;
variable clk0_cntr : string(1 to 6) := " c0";
variable clk1_cntr : string(1 to 6) := " c1";
variable clk2_cntr : string(1 to 6) := " c2";
variable clk3_cntr : string(1 to 6) := " c3";
variable clk4_cntr : string(1 to 6) := " c4";
variable fbk_cntr : string(1 to 2);
variable fbk_cntr_index : integer;
variable start_bit : integer;
variable quiet_time : time := 0 ps;
variable slowest_clk_old : time := 0 ps;
variable slowest_clk_new : time := 0 ps;
variable i : integer := 0;
variable j : integer := 0;
variable scanread_active_edge : time := 0 ps;
variable got_first_scanclk : boolean := false;
variable scanclk_last_rising_edge : time := 0 ps;
variable current_scan_data : std_logic_vector(0 to 143) := (OTHERS => '0');
variable index : integer := 0;
variable Tviol_scandata_scanclk : std_ulogic := '0';
variable TimingData_scandata_scanclk : VitalTimingDataType := VitalTimingDataInit;
variable Tviol_scanclkena_scanclk : std_ulogic := '0';
variable TimingData_scanclkena_scanclk : VitalTimingDataType := VitalTimingDataInit;
variable scan_chain_length : integer := GPP_SCAN_CHAIN;
variable tmp_rem : integer := 0;
variable scanclk_cycles : integer := 0;
variable lfc_tmp : std_logic_vector(1 downto 0);
variable lfr_tmp : std_logic_vector(5 downto 0);
variable lfr_int : integer := 0;
variable n_hi,n_lo,m_hi,m_lo : std_logic_vector(7 downto 0);
variable buf : line;
variable buf_scan_data : STD_LOGIC_VECTOR(0 TO 1) := (OTHERS => '0');
variable buf_scan_data_2 : STD_LOGIC_VECTOR(0 TO 2) := (OTHERS => '0');
function slowest_clk (
C0 : integer; C0_mode : string(1 to 6);
C1 : integer; C1_mode : string(1 to 6);
C2 : integer; C2_mode : string(1 to 6);
C3 : integer; C3_mode : string(1 to 6);
C4 : integer; C4_mode : string(1 to 6);
C5 : integer; C5_mode : string(1 to 6);
C6 : integer; C6_mode : string(1 to 6);
C7 : integer; C7_mode : string(1 to 6);
C8 : integer; C8_mode : string(1 to 6);
C9 : integer; C9_mode : string(1 to 6);
refclk : time; m_mod : integer) return time is
variable max_modulus : integer := 1;
variable q_period : time := 0 ps;
variable refclk_int : integer := 0;
begin
if (C0_mode /= "bypass" and C0_mode /= " off") then
max_modulus := C0;
end if;
if (C1 > max_modulus and C1_mode /= "bypass" and C1_mode /= " off") then
max_modulus := C1;
end if;
if (C2 > max_modulus and C2_mode /= "bypass" and C2_mode /= " off") then
max_modulus := C2;
end if;
if (C3 > max_modulus and C3_mode /= "bypass" and C3_mode /= " off") then
max_modulus := C3;
end if;
if (C4 > max_modulus and C4_mode /= "bypass" and C4_mode /= " off") then
max_modulus := C4;
end if;
if (C5 > max_modulus and C5_mode /= "bypass" and C5_mode /= " off") then
max_modulus := C5;
end if;
if (C6 > max_modulus and C6_mode /= "bypass" and C6_mode /= " off") then
max_modulus := C6;
end if;
if (C7 > max_modulus and C7_mode /= "bypass" and C7_mode /= " off") then
max_modulus := C7;
end if;
if (C8 > max_modulus and C8_mode /= "bypass" and C8_mode /= " off") then
max_modulus := C8;
end if;
if (C9 > max_modulus and C9_mode /= "bypass" and C9_mode /= " off") then
max_modulus := C9;
end if;
refclk_int := refclk / 1 ps;
if (m_mod /= 0) then
q_period := (refclk_int * max_modulus / m_mod) * 1 ps;
end if;
return (2*q_period);
end slowest_clk;
function int2bin (arg : integer; size : integer) return std_logic_vector is
variable int_val : integer := arg;
variable result : std_logic_vector(size-1 downto 0);
begin
for i in 0 to result'left loop
if ((int_val mod 2) = 0) then
result(i) := '0';
else
result(i) := '1';
end if;
int_val := int_val/2;
end loop;
return result;
end int2bin;
function extract_cntr_string (arg:string) return string is
variable str : string(1 to 6) := " c0";
begin
if (arg = "c0") then
str := " c0";
elsif (arg = "c1") then
str := " c1";
elsif (arg = "c2") then
str := " c2";
elsif (arg = "c3") then
str := " c3";
elsif (arg = "c4") then
str := " c4";
elsif (arg = "c5") then
str := " c5";
elsif (arg = "c6") then
str := " c6";
elsif (arg = "c7") then
str := " c7";
elsif (arg = "c8") then
str := " c8";
elsif (arg = "c9") then
str := " c9";
else str := " c0";
end if;
return str;
end extract_cntr_string;
function extract_cntr_index (arg:string) return integer is
variable index : integer := 0;
begin
if (arg(6) = '0') then
index := 0;
elsif (arg(6) = '1') then
index := 1;
elsif (arg(6) = '2') then
index := 2;
elsif (arg(6) = '3') then
index := 3;
elsif (arg(6) = '4') then
index := 4;
elsif (arg(6) = '5') then
index := 5;
elsif (arg(6) = '6') then
index := 6;
elsif (arg(6) = '7') then
index := 7;
elsif (arg(6) = '8') then
index := 8;
else index := 9;
end if;
return index;
end extract_cntr_index;
begin
IF (areset_ipd'EVENT AND areset_ipd = '1') then
c_ph_val <= i_c_ph;
END IF;
if (init) then
if (m = 0) then
clk4_cntr := " c4";
clk3_cntr := " c3";
clk2_cntr := " c2";
clk1_cntr := " c1";
clk0_cntr := " c0";
else
clk4_cntr := extract_cntr_string(clk4_counter);
clk3_cntr := extract_cntr_string(clk3_counter);
clk2_cntr := extract_cntr_string(clk2_counter);
clk1_cntr := extract_cntr_string(clk1_counter);
clk0_cntr := extract_cntr_string(clk0_counter);
end if;
i_clk0_counter <= extract_cntr_index(clk0_cntr);
i_clk1_counter <= extract_cntr_index(clk1_cntr);
i_clk2_counter <= extract_cntr_index(clk2_cntr);
i_clk3_counter <= extract_cntr_index(clk3_cntr);
i_clk4_counter <= extract_cntr_index(clk4_cntr);
if (m = 0) then -- convert user parameters to advanced
-- set the limit of the divide_by value that can be returned by
-- the following function.
max_d_value := 500;
-- scale down the multiply_by and divide_by values provided by the design
-- before attempting to use them in the calculations below
find_simple_integer_fraction(clk0_multiply_by, clk0_divide_by,
max_d_value, i_clk0_mult_by, i_clk0_div_by);
find_simple_integer_fraction(clk1_multiply_by, clk1_divide_by,
max_d_value, i_clk1_mult_by, i_clk1_div_by);
find_simple_integer_fraction(clk2_multiply_by, clk2_divide_by,
max_d_value, i_clk2_mult_by, i_clk2_div_by);
find_simple_integer_fraction(clk3_multiply_by, clk3_divide_by,
max_d_value, i_clk3_mult_by, i_clk3_div_by);
find_simple_integer_fraction(clk4_multiply_by, clk4_divide_by,
max_d_value, i_clk4_mult_by, i_clk4_div_by);
if (vco_frequency_control = "manual_phase") then
find_m_and_n_4_manual_phase(inclk0_input_frequency, vco_phase_shift_step,
i_clk0_mult_by, i_clk1_mult_by,
i_clk2_mult_by, i_clk3_mult_by,
i_clk4_mult_by,
1,1,1,1,1,
i_clk0_div_by, i_clk1_div_by,
i_clk2_div_by, i_clk3_div_by,
i_clk4_div_by,
1,1,1,1,1,
i_m, i_n);
elsif (((pll_type = "fast") or (pll_type = "lvds") OR (pll_type = "left_right")) and ((vco_multiply_by /= 0) and (vco_divide_by /= 0))) then
i_n := vco_divide_by;
i_m := vco_multiply_by;
else
i_n := 1;
if (((pll_type = "fast") or (pll_type = "left_right")) and (compensate_clock = "lvdsclk")) then
i_m := i_clk0_mult_by;
else
i_m := lcm (i_clk0_mult_by, i_clk1_mult_by,
i_clk2_mult_by, i_clk3_mult_by,
i_clk4_mult_by,
1,1,1,1,1,
inclk0_input_frequency);
end if;
end if;
if (pll_type = "flvds") then
-- Need to readjust phase shift values when the clock multiply value has been readjusted.
new_multiplier := clk0_multiply_by / i_clk0_mult_by;
i_clk0_phase_shift := str2int(clk0_phase_shift) * new_multiplier;
i_clk1_phase_shift := str2int(clk1_phase_shift) * new_multiplier;
i_clk2_phase_shift := str2int(clk2_phase_shift) * new_multiplier;
else
i_clk0_phase_shift := str2int(clk0_phase_shift);
i_clk1_phase_shift := str2int(clk1_phase_shift);
i_clk2_phase_shift := str2int(clk2_phase_shift);
end if;
max_neg_abs := maxnegabs(i_clk0_phase_shift,
i_clk1_phase_shift,
i_clk2_phase_shift,
str2int(clk3_phase_shift),
str2int(clk4_phase_shift),
0,
0,
0,
0,
0
);
i_m_ph := counter_ph(get_phase_degree(max_neg_abs,inclk0_input_frequency), i_m, i_n);
i_c_ph(0) := counter_ph(get_phase_degree(ph_adjust(i_clk0_phase_shift,max_neg_abs),inclk0_input_frequency), i_m, i_n);
i_c_ph(1) := counter_ph(get_phase_degree(ph_adjust(i_clk1_phase_shift,max_neg_abs),inclk0_input_frequency), i_m, i_n);
i_c_ph(2) := counter_ph(get_phase_degree(ph_adjust(i_clk2_phase_shift,max_neg_abs),inclk0_input_frequency), i_m, i_n);
i_c_ph(3) := counter_ph(get_phase_degree(ph_adjust(str2int(clk3_phase_shift),max_neg_abs),inclk0_input_frequency), i_m, i_n);
i_c_ph(4) := counter_ph(get_phase_degree(ph_adjust(str2int(clk4_phase_shift),max_neg_abs),inclk0_input_frequency), i_m, i_n);
i_c_high(0) := counter_high(output_counter_value(i_clk0_div_by,
i_clk0_mult_by, i_m, i_n), clk0_duty_cycle);
i_c_high(1) := counter_high(output_counter_value(i_clk1_div_by,
i_clk1_mult_by, i_m, i_n), clk1_duty_cycle);
i_c_high(2) := counter_high(output_counter_value(i_clk2_div_by,
i_clk2_mult_by, i_m, i_n), clk2_duty_cycle);
i_c_high(3) := counter_high(output_counter_value(i_clk3_div_by,
i_clk3_mult_by, i_m, i_n), clk3_duty_cycle);
i_c_high(4) := counter_high(output_counter_value(i_clk4_div_by,
i_clk4_mult_by, i_m, i_n), clk4_duty_cycle);
i_c_low(0) := counter_low(output_counter_value(i_clk0_div_by,
i_clk0_mult_by, i_m, i_n), clk0_duty_cycle);
i_c_low(1) := counter_low(output_counter_value(i_clk1_div_by,
i_clk1_mult_by, i_m, i_n), clk1_duty_cycle);
i_c_low(2) := counter_low(output_counter_value(i_clk2_div_by,
i_clk2_mult_by, i_m, i_n), clk2_duty_cycle);
i_c_low(3) := counter_low(output_counter_value(i_clk3_div_by,
i_clk3_mult_by, i_m, i_n), clk3_duty_cycle);
i_c_low(4) := counter_low(output_counter_value(i_clk4_div_by,
i_clk4_mult_by, i_m, i_n), clk4_duty_cycle);
i_m_initial := counter_initial(get_phase_degree(max_neg_abs, inclk0_input_frequency), i_m,i_n);
i_c_initial(0) := counter_initial(get_phase_degree(ph_adjust(i_clk0_phase_shift, max_neg_abs), inclk0_input_frequency), i_m, i_n);
i_c_initial(1) := counter_initial(get_phase_degree(ph_adjust(i_clk1_phase_shift, max_neg_abs), inclk0_input_frequency), i_m, i_n);
i_c_initial(2) := counter_initial(get_phase_degree(ph_adjust(i_clk2_phase_shift, max_neg_abs), inclk0_input_frequency), i_m, i_n);
i_c_initial(3) := counter_initial(get_phase_degree(ph_adjust(str2int(clk3_phase_shift), max_neg_abs), inclk0_input_frequency), i_m, i_n);
i_c_initial(4) := counter_initial(get_phase_degree(ph_adjust(str2int(clk4_phase_shift), max_neg_abs), inclk0_input_frequency), i_m, i_n);
i_c_mode(0) := counter_mode(clk0_duty_cycle, output_counter_value(i_clk0_div_by, i_clk0_mult_by, i_m, i_n));
i_c_mode(1) := counter_mode(clk1_duty_cycle, output_counter_value(i_clk1_div_by, i_clk1_mult_by, i_m, i_n));
i_c_mode(2) := counter_mode(clk2_duty_cycle, output_counter_value(i_clk2_div_by, i_clk2_mult_by, i_m, i_n));
i_c_mode(3) := counter_mode(clk3_duty_cycle, output_counter_value(i_clk3_div_by, i_clk3_mult_by, i_m, i_n));
i_c_mode(4) := counter_mode(clk4_duty_cycle, output_counter_value(i_clk4_div_by, i_clk4_mult_by, i_m, i_n));
else -- m /= 0
i_n := n;
i_m := m;
i_m_initial := m_initial;
i_m_ph := m_ph;
i_c_ph(0) := c0_ph;
i_c_ph(1) := c1_ph;
i_c_ph(2) := c2_ph;
i_c_ph(3) := c3_ph;
i_c_ph(4) := c4_ph;
i_c_high(0) := c0_high;
i_c_high(1) := c1_high;
i_c_high(2) := c2_high;
i_c_high(3) := c3_high;
i_c_high(4) := c4_high;
i_c_low(0) := c0_low;
i_c_low(1) := c1_low;
i_c_low(2) := c2_low;
i_c_low(3) := c3_low;
i_c_low(4) := c4_low;
i_c_initial(0) := c0_initial;
i_c_initial(1) := c1_initial;
i_c_initial(2) := c2_initial;
i_c_initial(3) := c3_initial;
i_c_initial(4) := c4_initial;
i_c_mode(0) := translate_string(c0_mode);
i_c_mode(1) := translate_string(c1_mode);
i_c_mode(2) := translate_string(c2_mode);
i_c_mode(3) := translate_string(c3_mode);
i_c_mode(4) := translate_string(c4_mode);
end if; -- user to advanced conversion.
m_initial_val <= i_m_initial;
n_val <= i_n;
m_val <= i_m;
if (i_m = 1) then
m_mode_val <= "bypass";
else
m_mode_val <= " ";
end if;
if (i_n = 1) then
n_mode_val <= "bypass";
else
n_mode_val <= " ";
end if;
m_ph_val <= i_m_ph;
m_ph_initial <= i_m_ph;
m_val_tmp := i_m;
for i in 0 to 4 loop
if (i_c_mode(i) = "bypass") then
if (pll_type = "fast" or pll_type = "lvds" OR (pll_type = "left_right")) then
i_c_high(i) := 16;
i_c_low(i) := 16;
else
i_c_high(i) := 256;
i_c_low(i) := 256;
end if;
end if;
c_ph_val(i) <= i_c_ph(i);
c_initial_val(i) <= i_c_initial(i);
c_high_val(i) <= i_c_high(i);
c_low_val(i) <= i_c_low(i);
c_mode_val(i) <= i_c_mode(i);
c_high_val_tmp(i) := i_c_high(i);
c_hval(i) := i_c_high(i);
c_low_val_tmp(i) := i_c_low(i);
c_lval(i) := i_c_low(i);
c_mode_val_tmp(i) := i_c_mode(i);
c_ph_val_orig(i) <= i_c_ph(i);
c_high_val_hold(i) <= i_c_high(i);
c_low_val_hold(i) <= i_c_low(i);
c_mode_val_hold(i) <= i_c_mode(i);
end loop;
scan_chain_length := SCAN_CHAIN;
num_output_cntrs <= 5;
init := false;
elsif (scandone_tmp'EVENT AND scandone_tmp = '1') then
c0_rising_edge_transfer_done := false;
c1_rising_edge_transfer_done := false;
c2_rising_edge_transfer_done := false;
c3_rising_edge_transfer_done := false;
c4_rising_edge_transfer_done := false;
update_conf_latches_reg <= '0';
elsif (update_conf_latches'event and update_conf_latches = '1') then
initiate_reconfig <= '1';
elsif (areset_ipd'event AND areset_ipd = '1') then
if (scandone_tmp = '0') then scandone_tmp <= '1' AFTER scanclk_period; end if;
elsif (scanclk_ipd'event and scanclk_ipd = '1') then
IF (initiate_reconfig = '1') THEN
initiate_reconfig <= '0';
ASSERT false REPORT "PLL Reprogramming Initiated" severity note;
update_conf_latches_reg <= update_conf_latches;
reconfig_err <= false;
scandone_tmp <= '0';
cp_curr_old <= cp_curr_val;
lfc_old <= lfc_val;
lfr_old <= lfr_val;
-- LF unused : bit 0,1
-- LF Capacitance : bits 2,3 : all values are legal
buf_scan_data := scan_data(2 TO 3);
IF ((pll_type = "fast") OR (pll_type = "lvds") OR (pll_type = "left_right")) THEN
lfc_val <= fpll_loop_filter_c_arr(alt_conv_integer(buf_scan_data));
ELSE
lfc_val <= loop_filter_c_arr(alt_conv_integer(buf_scan_data));
END IF;
-- LF Resistance : bits 4-8
-- valid values - 00000,00100,10000,10100,11000,11011,11100,11110
IF (scan_data(4 TO 8) = "00000") THEN
lfr_val <= "20";
ELSIF (scan_data(4 TO 8) = "00100") THEN
lfr_val <= "16";
ELSIF (scan_data(4 TO 8) = "10000") THEN
lfr_val <= "12";
ELSIF (scan_data(4 TO 8) = "10100") THEN
lfr_val <= "08";
ELSIF (scan_data(4 TO 8) = "11000") THEN
lfr_val <= "06";
ELSIF (scan_data(4 TO 8) = "11011") THEN
lfr_val <= "04";
ELSIF (scan_data(4 TO 8) = "11100") THEN
lfr_val <= "02";
ELSE
lfr_val <= "01";
END IF;
IF (NOT (((scan_data(4 TO 8) = "00000") OR (scan_data(4 TO 8) = "00100")) OR ((scan_data(4 TO 8) = "10000") OR (scan_data(4 TO 8) = "10100")) OR ((scan_data(4 TO 8) = "11000") OR (scan_data(4 TO 8) = "11011")) OR ((scan_data(4 TO 8) = "11100") OR (scan_data(4 TO 8) = "11110")))) THEN
WRITE(buf, string'("Illegal bit settings for Loop Filter Resistance. Legal bit values range from 000000 to 001111, 011000 to 011111, 101000 to 101111 and 111000 to 111111. Reconfiguration may not work."));
writeline(output,buf);
reconfig_err <= TRUE;
END IF;
-- CP
-- Bit 9 : CRBYPASS
-- Bit 10-14 : unused
-- Bits 15-17 : all values are legal
buf_scan_data_2 := scan_data(15 TO 17);
cp_curr_val <= charge_pump_curr_arr(alt_conv_integer(buf_scan_data_2));
-- save old values for display info.
cp_curr_val_bit_setting <= scan_data(15 TO 17);
lfc_val_bit_setting <= scan_data(2 TO 3);
lfr_val_bit_setting <= scan_data(4 TO 8);
m_val_old <= m_val;
n_val_old <= n_val;
m_mode_val_old <= m_mode_val;
n_mode_val_old <= n_mode_val;
WHILE (i < num_output_cntrs) LOOP
c_high_val_old(i) <= c_high_val(i);
c_low_val_old(i) <= c_low_val(i);
c_mode_val_old(i) <= c_mode_val(i);
i := i + 1;
END LOOP;
-- M counter
-- 1. Mode - bypass (bit 18)
IF (scan_data(18) = '1') THEN
m_mode_val <= "bypass";
-- 3. Mode - odd/even (bit 27)
ELSIF (scan_data(27) = '1') THEN
m_mode_val <= " odd";
ELSE
m_mode_val <= " even";
END IF;
-- 2. High (bit 19-26)
m_hi := scan_data(19 TO 26);
-- 4. Low (bit 28-35)
m_lo := scan_data(28 TO 35);
-- N counter
-- 1. Mode - bypass (bit 36)
IF (scan_data(36) = '1') THEN
n_mode_val <= "bypass";
-- 3. Mode - odd/even (bit 45)
ELSIF (scan_data(45) = '1') THEN
n_mode_val <= " odd";
ELSE
n_mode_val <= " even";
END IF;
-- 2. High (bit 37-44)
n_hi := scan_data(37 TO 44);
-- 4. Low (bit 46-53)
n_lo := scan_data(46 TO 53);
-- C counters (start bit 54) bit 1:mode(bypass),bit 2-9:high,bit 10:mode(odd/even),bit 11-18:low
i := 0;
WHILE (i < num_output_cntrs) LOOP
-- 1. Mode - bypass
IF (scan_data(54 + i * 18 + 0) = '1') THEN
c_mode_val_tmp(i) := "bypass";
-- 3. Mode - odd/even
ELSIF (scan_data(54 + i * 18 + 9) = '1') THEN
c_mode_val_tmp(i) := " odd";
ELSE
c_mode_val_tmp(i) := " even";
END IF;
-- 2. Hi
high := scan_data(54 + i * 18 + 1 TO 54 + i * 18 + 8);
c_hval(i) := alt_conv_integer(high);
IF (c_hval(i) /= 0) THEN
c_high_val_tmp(i) := c_hval(i);
END IF;
-- 4. Low
low := scan_data(54 + i * 18 + 10 TO 54 + i * 18 + 17);
c_lval(i) := alt_conv_integer(low);
IF (c_lval(i) /= 0) THEN
c_low_val_tmp(i) := c_lval(i);
END IF;
i := i + 1;
END LOOP;
-- Legality Checks
-- M counter value
IF ((m_hi /= m_lo) AND (scan_data(18) /= '1')) THEN
reconfig_err <= TRUE;
WRITE(buf,string'("Warning : The M counter of the " & family_name & " Fast PLL should be configured for 50%% duty cycle only. In this case the HIGH and LOW moduli programmed will result in a duty cycle other than 50%%, which is illegal. Reconfiguration may not work"));
writeline(output, buf);
ELSIF (m_hi /= "00000000") THEN
m_val_tmp := alt_conv_integer(m_hi) + alt_conv_integer(m_lo);
END IF;
-- N counter value
IF ((n_hi /= n_lo) AND (scan_data(36) /= '1')) THEN
reconfig_err <= TRUE;
WRITE(buf,string'("Warning : The N counter of the " & family_name & " Fast PLL should be configured for 50%% duty cycle only. In this case the HIGH and LOW moduli programmed will result in a duty cycle other than 50%%, which is illegal. Reconfiguration may not work"));
writeline(output, buf);
ELSIF (n_hi /= "00000000") THEN
n_val <= alt_conv_integer(n_hi) + alt_conv_integer(n_lo);
END IF;
-- TODO : Give warnings/errors in the following cases?
-- 1. Illegal counter values (error)
-- 2. Change of mode (warning)
-- 3. Only 50% duty cycle allowed for M counter (odd mode - hi-lo=1,even - hi-lo=0)
END IF;
end if;
if (fbclk'event and fbclk = '1') then
m_val <= m_val_tmp;
end if;
if (update_conf_latches_reg = '1') then
if (scanclk_ipd'event and scanclk_ipd = '1') then
c0_rising_edge_transfer_done := true;
c_high_val(0) <= c_high_val_tmp(0);
c_mode_val(0) <= c_mode_val_tmp(0);
end if;
if (scanclk_ipd'event and scanclk_ipd = '1') then
c1_rising_edge_transfer_done := true;
c_high_val(1) <= c_high_val_tmp(1);
c_mode_val(1) <= c_mode_val_tmp(1);
end if;
if (scanclk_ipd'event and scanclk_ipd = '1') then
c2_rising_edge_transfer_done := true;
c_high_val(2) <= c_high_val_tmp(2);
c_mode_val(2) <= c_mode_val_tmp(2);
end if;
if (scanclk_ipd'event and scanclk_ipd = '1') then
c_high_val(3) <= c_high_val_tmp(3);
c_mode_val(3) <= c_mode_val_tmp(3);
c3_rising_edge_transfer_done := true;
end if;
if (scanclk_ipd'event and scanclk_ipd = '1') then
c_high_val(4) <= c_high_val_tmp(4);
c_mode_val(4) <= c_mode_val_tmp(4);
c4_rising_edge_transfer_done := true;
end if;
end if;
if (scanclk_ipd'event and scanclk_ipd = '0' and c0_rising_edge_transfer_done) then
c_low_val(0) <= c_low_val_tmp(0);
end if;
if (scanclk_ipd'event and scanclk_ipd = '0' and c1_rising_edge_transfer_done) then
c_low_val(1) <= c_low_val_tmp(1);
end if;
if (scanclk_ipd'event and scanclk_ipd = '0' and c2_rising_edge_transfer_done) then
c_low_val(2) <= c_low_val_tmp(2);
end if;
if (scanclk_ipd'event and scanclk_ipd = '0' and c3_rising_edge_transfer_done) then
c_low_val(3) <= c_low_val_tmp(3);
end if;
if (scanclk_ipd'event and scanclk_ipd = '0' and c4_rising_edge_transfer_done) then
c_low_val(4) <= c_low_val_tmp(4);
end if;
if (update_phase = '1') then
if (vco_out(0)'event and vco_out(0) = '0') then
for i in 0 to 4 loop
if (c_ph_val(i) = 0) then
c_ph_val(i) <= c_ph_val_tmp(i);
end if;
end loop;
if (m_ph_val = 0) then
m_ph_val <= m_ph_val_tmp;
end if;
end if;
if (vco_out(1)'event and vco_out(1) = '0') then
for i in 0 to 4 loop
if (c_ph_val(i) = 1) then
c_ph_val(i) <= c_ph_val_tmp(i);
end if;
end loop;
if (m_ph_val = 1) then
m_ph_val <= m_ph_val_tmp;
end if;
end if;
if (vco_out(2)'event and vco_out(2) = '0') then
for i in 0 to 4 loop
if (c_ph_val(i) = 2) then
c_ph_val(i) <= c_ph_val_tmp(i);
end if;
end loop;
if (m_ph_val = 2) then
m_ph_val <= m_ph_val_tmp;
end if;
end if;
if (vco_out(3)'event and vco_out(3) = '0') then
for i in 0 to 4 loop
if (c_ph_val(i) = 3) then
c_ph_val(i) <= c_ph_val_tmp(i);
end if;
end loop;
if (m_ph_val = 3) then
m_ph_val <= m_ph_val_tmp;
end if;
end if;
if (vco_out(4)'event and vco_out(4) = '0') then
for i in 0 to 4 loop
if (c_ph_val(i) = 4) then
c_ph_val(i) <= c_ph_val_tmp(i);
end if;
end loop;
if (m_ph_val = 4) then
m_ph_val <= m_ph_val_tmp;
end if;
end if;
if (vco_out(5)'event and vco_out(5) = '0') then
for i in 0 to 4 loop
if (c_ph_val(i) = 5) then
c_ph_val(i) <= c_ph_val_tmp(i);
end if;
end loop;
if (m_ph_val = 5) then
m_ph_val <= m_ph_val_tmp;
end if;
end if;
if (vco_out(6)'event and vco_out(6) = '0') then
for i in 0 to 4 loop
if (c_ph_val(i) = 6) then
c_ph_val(i) <= c_ph_val_tmp(i);
end if;
end loop;
if (m_ph_val = 6) then
m_ph_val <= m_ph_val_tmp;
end if;
end if;
if (vco_out(7)'event and vco_out(7) = '0') then
for i in 0 to 4 loop
if (c_ph_val(i) = 7) then
c_ph_val(i) <= c_ph_val_tmp(i);
end if;
end loop;
if (m_ph_val = 7) then
m_ph_val <= m_ph_val_tmp;
end if;
end if;
end if;
if (vco_out(0)'event) then
for i in 0 to 4 loop
if (c_ph_val(i) = 0) then
inclk_c_from_vco(i) <= vco_out(0);
end if;
end loop;
if (m_ph_val = 0) then
inclk_m_from_vco <= vco_out(0);
end if;
end if;
if (vco_out(1)'event) then
for i in 0 to 4 loop
if (c_ph_val(i) = 1) then
inclk_c_from_vco(i) <= vco_out(1);
end if;
end loop;
if (m_ph_val = 1) then
inclk_m_from_vco <= vco_out(1);
end if;
end if;
if (vco_out(2)'event) then
for i in 0 to 4 loop
if (c_ph_val(i) = 2) then
inclk_c_from_vco(i) <= vco_out(2);
end if;
end loop;
if (m_ph_val = 2) then
inclk_m_from_vco <= vco_out(2);
end if;
end if;
if (vco_out(3)'event) then
for i in 0 to 4 loop
if (c_ph_val(i) = 3) then
inclk_c_from_vco(i) <= vco_out(3);
end if;
end loop;
if (m_ph_val = 3) then
inclk_m_from_vco <= vco_out(3);
end if;
end if;
if (vco_out(4)'event) then
for i in 0 to 4 loop
if (c_ph_val(i) = 4) then
inclk_c_from_vco(i) <= vco_out(4);
end if;
end loop;
if (m_ph_val = 4) then
inclk_m_from_vco <= vco_out(4);
end if;
end if;
if (vco_out(5)'event) then
for i in 0 to 4 loop
if (c_ph_val(i) = 5) then
inclk_c_from_vco(i) <= vco_out(5);
end if;
end loop;
if (m_ph_val = 5) then
inclk_m_from_vco <= vco_out(5);
end if;
end if;
if (vco_out(6)'event) then
for i in 0 to 4 loop
if (c_ph_val(i) = 6) then
inclk_c_from_vco(i) <= vco_out(6);
end if;
end loop;
if (m_ph_val = 6) then
inclk_m_from_vco <= vco_out(6);
end if;
end if;
if (vco_out(7)'event) then
for i in 0 to 4 loop
if (c_ph_val(i) = 7) then
inclk_c_from_vco(i) <= vco_out(7);
end if;
end loop;
if (m_ph_val = 7) then
inclk_m_from_vco <= vco_out(7);
end if;
end if;
------------------------
-- Timing Check Section
------------------------
if (TimingChecksOn) then
VitalSetupHoldCheck (
Violation => Tviol_scandata_scanclk,
TimingData => TimingData_scandata_scanclk,
TestSignal => scandata_ipd,
TestSignalName => "scandata",
RefSignal => scanclk_ipd,
RefSignalName => "scanclk",
SetupHigh => tsetup_scandata_scanclk_noedge_negedge,
SetupLow => tsetup_scandata_scanclk_noedge_negedge,
HoldHigh => thold_scandata_scanclk_noedge_negedge,
HoldLow => thold_scandata_scanclk_noedge_negedge,
CheckEnabled => TRUE,
RefTransition => '\',
HeaderMsg => InstancePath & "/cycloneiii_pll",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_scanclkena_scanclk,
TimingData => TimingData_scanclkena_scanclk,
TestSignal => scanclkena_ipd,
TestSignalName => "scanclkena",
RefSignal => scanclk_ipd,
RefSignalName => "scanclk",
SetupHigh => tsetup_scanclkena_scanclk_noedge_negedge,
SetupLow => tsetup_scanclkena_scanclk_noedge_negedge,
HoldHigh => thold_scanclkena_scanclk_noedge_negedge,
HoldLow => thold_scanclkena_scanclk_noedge_negedge,
CheckEnabled => TRUE,
RefTransition => '\',
HeaderMsg => InstancePath & "/cycloneiii_pll",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
end if;
if (scanclk_ipd'event AND scanclk_ipd = '0' AND now > 0 ps) then
scanclkena_reg <= scanclkena_ipd;
if (scanclkena_reg = '1') then
scandata_in <= scandata_ipd;
scandata_out <= scandataout_tmp;
end if;
end if;
if (scanclk_ipd'event and scanclk_ipd = '1' and now > 0 ps) then
if (got_first_scanclk) then
scanclk_period <= now - scanclk_last_rising_edge;
else
got_first_scanclk := true;
end if;
if (scanclkena_reg = '1') then
for j in scan_chain_length - 1 downto 1 loop
scan_data(j) <= scan_data(j-1);
end loop;
scan_data(0) <= scandata_in;
end if;
scanclk_last_rising_edge := now;
end if;
end process;
-- PLL Phase Reconfiguration
PROCESS(scanclk_ipd, areset_ipd,phasestep_ipd)
VARIABLE i : INTEGER := 0;
VARIABLE c_ph : INTEGER := 0;
VARIABLE m_ph : INTEGER := 0;
VARIABLE select_counter : INTEGER := 0;
BEGIN
IF (NOW = 0 ps) THEN
m_ph_val_tmp <= m_ph_initial;
END IF;
-- Latch phase enable (same as phasestep) on neg edge of scan clock
IF (scanclk_ipd'EVENT AND scanclk_ipd = '0') THEN
phasestep_reg <= phasestep_ipd;
END IF;
IF (phasestep_ipd'EVENT and phasestep_ipd = '1') THEN
IF (update_phase = '0') THEN
phasestep_high_count <= 0; -- phase adjustments must be 1 cycle apart
-- if not, next phasestep cycle is skipped
END IF;
END IF;
-- revert counter phase tap values to POF programmed values
-- if PLL is reset
IF (areset_ipd'EVENT AND areset_ipd = '1') then
c_ph_val_tmp <= c_ph_val_orig;
m_ph_val_tmp <= m_ph_initial;
END IF;
IF (scanclk_ipd'EVENT AND scanclk_ipd = '1') THEN
IF (phasestep_reg = '1') THEN
IF (phasestep_high_count = 1) THEN
phasecounterselect_reg <= phasecounterselect_ipd;
phaseupdown_reg <= phaseupdown_ipd;
-- start reconfiguration
IF (phasecounterselect_ipd < "111") THEN -- no counters selected
IF (phasecounterselect_ipd = "000") THEN
WHILE (i < num_output_cntrs) LOOP
c_ph := c_ph_val(i);
IF (phaseupdown_ipd = '1') THEN
c_ph := (c_ph + 1) mod num_phase_taps;
ELSIF (c_ph = 0) THEN
c_ph := num_phase_taps - 1;
ELSE
c_ph := (c_ph - 1) mod num_phase_taps;
END IF;
c_ph_val_tmp(i) <= c_ph;
i := i + 1;
END LOOP;
ELSIF (phasecounterselect_ipd = "001") THEN
m_ph := m_ph_val;
IF (phaseupdown_ipd = '1') THEN
m_ph := (m_ph + 1) mod num_phase_taps;
ELSIF (m_ph = 0) THEN
m_ph := num_phase_taps - 1;
ELSE
m_ph := (m_ph - 1) mod num_phase_taps;
END IF;
m_ph_val_tmp <= m_ph;
ELSE
select_counter := alt_conv_integer(phasecounterselect_ipd) - 2;
c_ph := c_ph_val(select_counter);
IF (phaseupdown_ipd = '1') THEN
c_ph := (c_ph + 1) mod num_phase_taps;
ELSIF (c_ph = 0) THEN
c_ph := num_phase_taps - 1;
ELSE
c_ph := (c_ph - 1) mod num_phase_taps;
END IF;
c_ph_val_tmp(select_counter) <= c_ph;
END IF;
update_phase <= '1','0' AFTER (0.5 * scanclk_period);
END IF;
END IF;
phasestep_high_count <= phasestep_high_count + 1;
END IF;
END IF;
END PROCESS;
scandataout_tmp <= scan_data(SCAN_CHAIN - 2);
process (schedule_vco, areset_ipd, pfdena_ipd, refclk, fbclk)
variable sched_time : time := 0 ps;
TYPE time_array is ARRAY (0 to 7) of time;
variable init : boolean := true;
variable refclk_period : time;
variable m_times_vco_period : time;
variable new_m_times_vco_period : time;
variable phase_shift : time_array := (OTHERS => 0 ps);
variable last_phase_shift : time_array := (OTHERS => 0 ps);
variable l_index : integer := 1;
variable cycle_to_adjust : integer := 0;
variable stop_vco : boolean := false;
variable locked_tmp : std_logic := '0';
variable pll_is_locked : boolean := false;
variable cycles_pfd_low : integer := 0;
variable cycles_pfd_high : integer := 0;
variable cycles_to_lock : integer := 0;
variable cycles_to_unlock : integer := 0;
variable got_first_refclk : boolean := false;
variable got_second_refclk : boolean := false;
variable got_first_fbclk : boolean := false;
variable refclk_time : time := 0 ps;
variable fbclk_time : time := 0 ps;
variable first_fbclk_time : time := 0 ps;
variable fbclk_period : time := 0 ps;
variable first_schedule : boolean := true;
variable vco_val : std_logic := '0';
variable vco_period_was_phase_adjusted : boolean := false;
variable phase_adjust_was_scheduled : boolean := false;
variable loop_xplier : integer;
variable loop_initial : integer := 0;
variable loop_ph : integer := 0;
variable loop_time_delay : integer := 0;
variable initial_delay : time := 0 ps;
variable vco_per : time;
variable tmp_rem : integer;
variable my_rem : integer;
variable fbk_phase : integer := 0;
variable pull_back_M : integer := 0;
variable total_pull_back : integer := 0;
variable fbk_delay : integer := 0;
variable offset : time := 0 ps;
variable tmp_vco_per : integer := 0;
variable high_time : time;
variable low_time : time;
variable got_refclk_posedge : boolean := false;
variable got_fbclk_posedge : boolean := false;
variable inclk_out_of_range : boolean := false;
variable no_warn : boolean := false;
variable ext_fbk_cntr_modulus : integer := 1;
variable init_clks : boolean := true;
variable pll_is_in_reset : boolean := false;
variable buf : line;
begin
if (init) then
-- jump-start the VCO
-- add 1 ps delay to ensure all signals are updated to initial
-- values
schedule_vco <= transport not schedule_vco after 1 ps;
init := false;
end if;
if (schedule_vco'event) then
if (init_clks) then
refclk_period := inclk0_input_frequency * n_val * 1 ps;
m_times_vco_period := refclk_period;
new_m_times_vco_period := refclk_period;
init_clks := false;
end if;
sched_time := 0 ps;
for i in 0 to 7 loop
last_phase_shift(i) := phase_shift(i);
end loop;
cycle_to_adjust := 0;
l_index := 1;
m_times_vco_period := new_m_times_vco_period;
end if;
-- areset was asserted
if (areset_ipd'event and areset_ipd = '1') then
assert false report family_name & " PLL was reset" severity note;
-- reset lock parameters
pll_is_locked := false;
cycles_to_lock := 0;
cycles_to_unlock := 0;
end if;
if (schedule_vco'event and (areset_ipd = '1' or stop_vco)) then
if (areset_ipd = '1') then
pll_is_in_reset := true;
end if;
-- drop VCO taps to 0
for i in 0 to 7 loop
vco_out(i) <= transport '0' after last_phase_shift(i);
phase_shift(i) := 0 ps;
last_phase_shift(i) := 0 ps;
end loop;
-- reset lock parameters
pll_is_locked := false;
cycles_to_lock := 0;
cycles_to_unlock := 0;
got_first_refclk := false;
got_second_refclk := false;
refclk_time := 0 ps;
got_first_fbclk := false;
fbclk_time := 0 ps;
first_fbclk_time := 0 ps;
fbclk_period := 0 ps;
first_schedule := true;
vco_val := '0';
vco_period_was_phase_adjusted := false;
phase_adjust_was_scheduled := false;
elsif ((schedule_vco'event or areset_ipd'event) and areset_ipd = '0' and (not stop_vco) and now > 0 ps) then
-- note areset deassert time
-- note it as refclk_time to prevent false triggering
-- of stop_vco after areset
if (areset_ipd'event and areset_ipd = '0' and pll_is_in_reset) then
refclk_time := now;
pll_is_in_reset := false;
locked_tmp := '0';
end if;
-- calculate loop_xplier : this will be different from m_val
-- in external_feedback_mode
loop_xplier := m_val;
loop_initial := m_initial_val - 1;
loop_ph := m_ph_val;
-- convert initial value to delay
initial_delay := (loop_initial * m_times_vco_period)/loop_xplier;
-- convert loop ph_tap to delay
my_rem := (m_times_vco_period/1 ps) rem loop_xplier;
tmp_vco_per := (m_times_vco_period/1 ps) / loop_xplier;
if (my_rem /= 0) then
tmp_vco_per := tmp_vco_per + 1;
end if;
fbk_phase := (loop_ph * tmp_vco_per)/8;
pull_back_M := initial_delay/1 ps + fbk_phase;
total_pull_back := pull_back_M;
if (simulation_type = "timing") then
total_pull_back := total_pull_back + pll_compensation_delay;
end if;
while (total_pull_back > refclk_period/1 ps) loop
total_pull_back := total_pull_back - refclk_period/1 ps;
end loop;
if (total_pull_back > 0) then
offset := refclk_period - (total_pull_back * 1 ps);
end if;
fbk_delay := total_pull_back - fbk_phase;
if (fbk_delay < 0) then
offset := offset - (fbk_phase * 1 ps);
fbk_delay := total_pull_back;
end if;
-- assign m_delay
m_delay <= transport fbk_delay after 1 ps;
my_rem := (m_times_vco_period/1 ps) rem loop_xplier;
for i in 1 to loop_xplier loop
-- adjust cycles
tmp_vco_per := (m_times_vco_period/1 ps)/loop_xplier;
if (my_rem /= 0 and l_index <= my_rem) then
tmp_rem := (loop_xplier * l_index) rem my_rem;
cycle_to_adjust := (loop_xplier * l_index) / my_rem;
if (tmp_rem /= 0) then
cycle_to_adjust := cycle_to_adjust + 1;
end if;
end if;
if (cycle_to_adjust = i) then
tmp_vco_per := tmp_vco_per + 1;
l_index := l_index + 1;
end if;
-- calculate high and low periods
vco_per := tmp_vco_per * 1 ps;
high_time := (tmp_vco_per/2) * 1 ps;
if (tmp_vco_per rem 2 /= 0) then
high_time := high_time + 1 ps;
end if;
low_time := vco_per - high_time;
-- schedule the rising and falling edges
for j in 1 to 2 loop
vco_val := not vco_val;
if (vco_val = '0') then
sched_time := sched_time + high_time;
elsif (vco_val = '1') then
sched_time := sched_time + low_time;
end if;
-- schedule the phase taps
for k in 0 to 7 loop
phase_shift(k) := (k * vco_per)/8;
if (first_schedule) then
vco_out(k) <= transport vco_val after (sched_time + phase_shift(k));
else
vco_out(k) <= transport vco_val after (sched_time + last_phase_shift(k));
end if;
end loop;
end loop;
end loop;
-- schedule once more
if (first_schedule) then
vco_val := not vco_val;
if (vco_val = '0') then
sched_time := sched_time + high_time;
elsif (vco_val = '1') then
sched_time := sched_time + low_time;
end if;
-- schedule the phase taps
for k in 0 to 7 loop
phase_shift(k) := (k * vco_per)/8;
vco_out(k) <= transport vco_val after (sched_time + phase_shift(k));
end loop;
first_schedule := false;
end if;
schedule_vco <= transport not schedule_vco after sched_time;
if (vco_period_was_phase_adjusted) then
m_times_vco_period := refclk_period;
new_m_times_vco_period := refclk_period;
vco_period_was_phase_adjusted := false;
phase_adjust_was_scheduled := true;
vco_per := m_times_vco_period/loop_xplier;
for k in 0 to 7 loop
phase_shift(k) := (k * vco_per)/8;
end loop;
end if;
end if;
-- Bypass lock detect
if (refclk'event and refclk = '1' and areset_ipd = '0') then
if (test_bypass_lock_detect = "on") then
if (pfdena_ipd = '1') then
cycles_pfd_low := 0;
if (pfd_locked = '0') then
if (cycles_pfd_high = lock_high) then
assert false report family_name & " PLL locked in test mode on PFD enable assertion.";
pfd_locked <= '1';
end if;
cycles_pfd_high := cycles_pfd_high + 1;
end if;
end if;
if (pfdena_ipd = '0') then
cycles_pfd_high := 0;
if (pfd_locked = '1') then
if (cycles_pfd_low = lock_low) then
assert false report family_name & " PLL lost lock in test mode on PFD enable de-assertion.";
pfd_locked <= '0';
end if;
cycles_pfd_low := cycles_pfd_low + 1;
end if;
end if;
end if;
if (refclk'event and refclk = '1' and areset_ipd = '0') then
got_refclk_posedge := true;
if (not got_first_refclk) then
got_first_refclk := true;
else
got_second_refclk := true;
refclk_period := now - refclk_time;
-- check if incoming freq. will cause VCO range to be
-- exceeded
if ( (vco_max /= 0 and vco_min /= 0 and pfdena_ipd = '1') and
(((refclk_period/1 ps)/loop_xplier > vco_max) or
((refclk_period/1 ps)/loop_xplier < vco_min)) ) then
if (pll_is_locked) then
if ((refclk_period/1 ps)/loop_xplier > vco_max) then
assert false report "Input clock freq. is over VCO range. " & family_name & " PLL may lose lock" severity warning;
vco_over <= '1';
end if;
if ((refclk_period/1 ps)/loop_xplier < vco_min) then
assert false report "Input clock freq. is under VCO range. " & family_name & " PLL may lose lock" severity warning;
vco_under <= '1';
end if;
if (inclk_out_of_range) then
pll_is_locked := false;
locked_tmp := '0';
cycles_to_lock := 0;
vco_period_was_phase_adjusted := false;
phase_adjust_was_scheduled := false;
assert false report family_name & " PLL lost lock." severity note;
end if;
elsif (not no_warn) then
if ((refclk_period/1 ps)/loop_xplier > vco_max) then
assert false report "Input clock freq. is over VCO range. " & family_name & " PLL may lose lock" severity warning;
vco_over <= '1';
end if;
if ((refclk_period/1 ps)/loop_xplier < vco_min) then
assert false report "Input clock freq. is under VCO range. " & family_name & " PLL may lose lock" severity warning;
vco_under <= '1';
end if;
assert false report " Input clock freq. is not within VCO range : " & family_name & " PLL may not lock. Please use the correct frequency." severity warning;
no_warn := true;
end if;
inclk_out_of_range := true;
else
vco_over <= '0';
vco_under <= '0';
inclk_out_of_range := false;
end if;
end if;
end if;
if (stop_vco) then
stop_vco := false;
schedule_vco <= not schedule_vco;
end if;
refclk_time := now;
else
got_refclk_posedge := false;
end if;
-- Update M counter value on feedback clock edge
if (fbclk'event and fbclk = '1') then
got_fbclk_posedge := true;
if (not got_first_fbclk) then
got_first_fbclk := true;
else
fbclk_period := now - fbclk_time;
end if;
-- need refclk_period here, so initialized to proper value above
if ( ( (now - refclk_time > 1.5 * refclk_period) and pfdena_ipd = '1' and pll_is_locked) or ( (now - refclk_time > 5 * refclk_period) and pfdena_ipd = '1') ) then
stop_vco := true;
-- reset
got_first_refclk := false;
got_first_fbclk := false;
got_second_refclk := false;
if (pll_is_locked) then
pll_is_locked := false;
locked_tmp := '0';
assert false report family_name & " PLL lost lock due to loss of input clock" severity note;
end if;
cycles_to_lock := 0;
cycles_to_unlock := 0;
first_schedule := true;
vco_period_was_phase_adjusted := false;
phase_adjust_was_scheduled := false;
end if;
fbclk_time := now;
else
got_fbclk_posedge := false;
end if;
if ((got_refclk_posedge or got_fbclk_posedge) and got_second_refclk and pfdena_ipd = '1' and (not inclk_out_of_range)) then
-- now we know actual incoming period
if ( abs(fbclk_time - refclk_time) <= 5 ps or
(got_first_fbclk and abs(refclk_period - abs(fbclk_time - refclk_time)) <= 5 ps)) then
-- considered in phase
if (cycles_to_lock = real_lock_high) then
if (not pll_is_locked) then
assert false report family_name & " PLL locked to incoming clock" severity note;
end if;
pll_is_locked := true;
locked_tmp := '1';
cycles_to_unlock := 0;
end if;
-- increment lock counter only if second part of above
-- time check is NOT true
if (not(abs(refclk_period - abs(fbclk_time - refclk_time)) <= lock_window)) then
cycles_to_lock := cycles_to_lock + 1;
end if;
-- adjust m_times_vco_period
new_m_times_vco_period := refclk_period;
else
-- if locked, begin unlock
if (pll_is_locked) then
cycles_to_unlock := cycles_to_unlock + 1;
if (cycles_to_unlock = lock_low) then
pll_is_locked := false;
locked_tmp := '0';
cycles_to_lock := 0;
vco_period_was_phase_adjusted := false;
phase_adjust_was_scheduled := false;
assert false report family_name & " PLL lost lock." severity note;
end if;
end if;
if ( abs(refclk_period - fbclk_period) <= 2 ps ) then
-- frequency is still good
if (now = fbclk_time and (not phase_adjust_was_scheduled)) then
if ( abs(fbclk_time - refclk_time) > refclk_period/2) then
new_m_times_vco_period := m_times_vco_period + (refclk_period - abs(fbclk_time - refclk_time));
vco_period_was_phase_adjusted := true;
else
new_m_times_vco_period := m_times_vco_period - abs(fbclk_time - refclk_time);
vco_period_was_phase_adjusted := true;
end if;
end if;
else
phase_adjust_was_scheduled := false;
new_m_times_vco_period := refclk_period;
end if;
end if;
end if;
if (pfdena_ipd = '0') then
if (pll_is_locked) then
locked_tmp := 'X';
end if;
pll_is_locked := false;
cycles_to_lock := 0;
end if;
-- give message only at time of deassertion
if (pfdena_ipd'event and pfdena_ipd = '0') then
assert false report "PFDENA deasserted." severity note;
elsif (pfdena_ipd'event and pfdena_ipd = '1') then
got_first_refclk := false;
got_second_refclk := false;
refclk_time := now;
end if;
if (reconfig_err) then
lock <= '0';
else
lock <= locked_tmp;
end if;
-- signal to calculate quiet_time
sig_refclk_period <= refclk_period;
if (stop_vco = true) then
sig_stop_vco <= '1';
else
sig_stop_vco <= '0';
end if;
pll_locked <= pll_is_locked;
end process;
clk0_tmp <= c_clk(i_clk0_counter);
clk_pfd(0) <= clk0_tmp WHEN (pfd_locked = '1') ELSE 'X';
clk(0) <= clk_pfd(0) WHEN (test_bypass_lock_detect = "on") ELSE
clk0_tmp when (areset_ipd = '1' or pll_in_test_mode) or (pll_locked and (not reconfig_err)) else
'X';
clk1_tmp <= c_clk(i_clk1_counter);
clk_pfd(1) <= clk1_tmp WHEN (pfd_locked = '1') ELSE 'X';
clk(1) <= clk_pfd(1) WHEN (test_bypass_lock_detect = "on") ELSE
clk1_tmp when (areset_ipd = '1' or pll_in_test_mode) or (pll_locked and (not reconfig_err)) else 'X';
clk2_tmp <= c_clk(i_clk2_counter);
clk_pfd(2) <= clk2_tmp WHEN (pfd_locked = '1') ELSE 'X';
clk(2) <= clk_pfd(2) WHEN (test_bypass_lock_detect = "on") ELSE
clk2_tmp when (areset_ipd = '1' or pll_in_test_mode) or (pll_locked and (not reconfig_err)) else 'X';
clk3_tmp <= c_clk(i_clk3_counter);
clk_pfd(3) <= clk3_tmp WHEN (pfd_locked = '1') ELSE 'X';
clk(3) <= clk_pfd(3) WHEN (test_bypass_lock_detect = "on") ELSE
clk3_tmp when (areset_ipd = '1' or pll_in_test_mode) or (pll_locked and (not reconfig_err)) else 'X';
clk4_tmp <= c_clk(i_clk4_counter);
clk_pfd(4) <= clk4_tmp WHEN (pfd_locked = '1') ELSE 'X';
clk(4) <= clk_pfd(4) WHEN (test_bypass_lock_detect = "on") ELSE
clk4_tmp when (areset_ipd = '1' or pll_in_test_mode) or (pll_locked and (not reconfig_err)) else 'X';
scandataout <= scandata_out;
scandone <= NOT scandone_tmp;
phasedone <= NOT update_phase;
end vital_pll;
-- END ARCHITECTURE VITAL_PLL
---------------------------------------------------------------------
--
-- Entity Name : cycloneiii_ff
--
-- Description : Cyclone III FF VHDL simulation model
--
--
---------------------------------------------------------------------
LIBRARY IEEE;
use IEEE.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.cycloneiii_atom_pack.all;
use work.cycloneiii_and1;
entity cycloneiii_ff is
generic (
power_up : string := "low";
x_on_violation : string := "on";
lpm_type : string := "cycloneiii_ff";
tsetup_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_asdata_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_sclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_asdata_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_sclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_clk_q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_clrn_q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_aload_q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_asdata_q: VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_d : VitalDelayType01 := DefPropDelay01;
tipd_asdata : VitalDelayType01 := DefPropDelay01;
tipd_sclr : VitalDelayType01 := DefPropDelay01;
tipd_sload : VitalDelayType01 := DefPropDelay01;
tipd_clrn : VitalDelayType01 := DefPropDelay01;
tipd_aload : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks;
InstancePath: STRING := "*"
);
port (
d : in std_logic := '0';
clk : in std_logic := '0';
clrn : in std_logic := '1';
aload : in std_logic := '0';
sclr : in std_logic := '0';
sload : in std_logic := '0';
ena : in std_logic := '1';
asdata : in std_logic := '0';
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
q : out std_logic
);
attribute VITAL_LEVEL0 of cycloneiii_ff : entity is TRUE;
end cycloneiii_ff;
architecture vital_lcell_ff of cycloneiii_ff is
attribute VITAL_LEVEL0 of vital_lcell_ff : architecture is TRUE;
signal clk_ipd : std_logic;
signal d_ipd : std_logic;
signal d_dly : std_logic;
signal asdata_ipd : std_logic;
signal asdata_dly : std_logic;
signal asdata_dly1 : std_logic;
signal sclr_ipd : std_logic;
signal sload_ipd : std_logic;
signal clrn_ipd : std_logic;
signal aload_ipd : std_logic;
signal ena_ipd : std_logic;
component cycloneiii_and1
generic (XOn : Boolean := DefGlitchXOn;
MsgOn : Boolean := DefGlitchMsgOn;
tpd_IN1_Y : VitalDelayType01 := DefPropDelay01;
tipd_IN1 : VitalDelayType01 := DefPropDelay01
);
port (Y : out STD_LOGIC;
IN1 : in STD_LOGIC
);
end component;
begin
ddelaybuffer: cycloneiii_and1
port map(IN1 => d_ipd,
Y => d_dly);
asdatadelaybuffer: cycloneiii_and1
port map(IN1 => asdata_ipd,
Y => asdata_dly);
asdatadelaybuffer1: cycloneiii_and1
port map(IN1 => asdata_dly,
Y => asdata_dly1);
---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
VitalWireDelay (clk_ipd, clk, tipd_clk);
VitalWireDelay (d_ipd, d, tipd_d);
VitalWireDelay (asdata_ipd, asdata, tipd_asdata);
VitalWireDelay (sclr_ipd, sclr, tipd_sclr);
VitalWireDelay (sload_ipd, sload, tipd_sload);
VitalWireDelay (clrn_ipd, clrn, tipd_clrn);
VitalWireDelay (aload_ipd, aload, tipd_aload);
VitalWireDelay (ena_ipd, ena, tipd_ena);
end block;
VITALtiming : process (clk_ipd, d_dly, asdata_dly1,
sclr_ipd, sload_ipd, clrn_ipd, aload_ipd,
ena_ipd, devclrn, devpor)
variable Tviol_d_clk : std_ulogic := '0';
variable Tviol_asdata_clk : std_ulogic := '0';
variable Tviol_sclr_clk : std_ulogic := '0';
variable Tviol_sload_clk : std_ulogic := '0';
variable Tviol_ena_clk : std_ulogic := '0';
variable TimingData_d_clk : VitalTimingDataType := VitalTimingDataInit;
variable TimingData_asdata_clk : VitalTimingDataType := VitalTimingDataInit;
variable TimingData_sclr_clk : VitalTimingDataType := VitalTimingDataInit;
variable TimingData_sload_clk : VitalTimingDataType := VitalTimingDataInit;
variable TimingData_ena_clk : VitalTimingDataType := VitalTimingDataInit;
variable q_VitalGlitchData : VitalGlitchDataType;
variable iq : std_logic := '0';
variable idata: std_logic := '0';
-- variables for 'X' generation
variable violation : std_logic := '0';
begin
if (now = 0 ns) then
if (power_up = "low") then
iq := '0';
elsif (power_up = "high") then
iq := '1';
end if;
end if;
------------------------
-- Timing Check Section
------------------------
if (TimingChecksOn) then
VitalSetupHoldCheck (
Violation => Tviol_d_clk,
TimingData => TimingData_d_clk,
TestSignal => d,
TestSignalName => "DATAIN",
RefSignal => clk_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_d_clk_noedge_posedge,
SetupLow => tsetup_d_clk_noedge_posedge,
HoldHigh => thold_d_clk_noedge_posedge,
HoldLow => thold_d_clk_noedge_posedge,
CheckEnabled => TO_X01((NOT clrn_ipd) OR
(sload_ipd) OR
(sclr_ipd) OR
(NOT devpor) OR
(NOT devclrn) OR
(NOT ena_ipd)) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/LCELL_FF",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_asdata_clk,
TimingData => TimingData_asdata_clk,
TestSignal => asdata_ipd,
TestSignalName => "ASDATA",
RefSignal => clk_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_asdata_clk_noedge_posedge,
SetupLow => tsetup_asdata_clk_noedge_posedge,
HoldHigh => thold_asdata_clk_noedge_posedge,
HoldLow => thold_asdata_clk_noedge_posedge,
CheckEnabled => TO_X01((NOT clrn_ipd) OR
(NOT sload_ipd) OR
(NOT devpor) OR
(NOT devclrn) OR
(NOT ena_ipd)) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/LCELL_FF",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_sclr_clk,
TimingData => TimingData_sclr_clk,
TestSignal => sclr_ipd,
TestSignalName => "SCLR",
RefSignal => clk_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_sclr_clk_noedge_posedge,
SetupLow => tsetup_sclr_clk_noedge_posedge,
HoldHigh => thold_sclr_clk_noedge_posedge,
HoldLow => thold_sclr_clk_noedge_posedge,
CheckEnabled => TO_X01((NOT clrn_ipd) OR
(NOT devpor) OR
(NOT devclrn) OR
(NOT ena_ipd)) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/LCELL_FF",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_sload_clk,
TimingData => TimingData_sload_clk,
TestSignal => sload_ipd,
TestSignalName => "SLOAD",
RefSignal => clk_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_sload_clk_noedge_posedge,
SetupLow => tsetup_sload_clk_noedge_posedge,
HoldHigh => thold_sload_clk_noedge_posedge,
HoldLow => thold_sload_clk_noedge_posedge,
CheckEnabled => TO_X01((NOT clrn_ipd) OR
(NOT devpor) OR
(NOT devclrn) OR
(NOT ena_ipd)) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/LCELL_FF",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_ena_clk,
TimingData => TimingData_ena_clk,
TestSignal => ena_ipd,
TestSignalName => "ENA",
RefSignal => clk_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_ena_clk_noedge_posedge,
SetupLow => tsetup_ena_clk_noedge_posedge,
HoldHigh => thold_ena_clk_noedge_posedge,
HoldLow => thold_ena_clk_noedge_posedge,
CheckEnabled => TO_X01((NOT clrn_ipd) OR
(NOT devpor) OR
(NOT devclrn) ) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/LCELL_FF",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
end if;
violation := Tviol_d_clk or Tviol_asdata_clk or
Tviol_sclr_clk or Tviol_sload_clk or Tviol_ena_clk;
if ((devpor = '0') or (devclrn = '0') or (clrn_ipd = '1')) then
iq := '0';
elsif (aload_ipd = '1') then
iq := asdata_dly1;
elsif (violation = 'X' and x_on_violation = "on") then
iq := 'X';
elsif clk_ipd'event and clk_ipd = '1' and clk_ipd'last_value = '0' then
if (ena_ipd = '1') then
if (sclr_ipd = '1') then
iq := '0';
elsif (sload_ipd = '1') then
iq := asdata_dly1;
else
iq := d_dly;
end if;
end if;
end if;
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
OutSignal => q,
OutSignalName => "Q",
OutTemp => iq,
Paths => (0 => (clrn_ipd'last_event, tpd_clrn_q_posedge, TRUE),
1 => (aload_ipd'last_event, tpd_aload_q_posedge, TRUE),
2 => (asdata_ipd'last_event, tpd_asdata_q, TRUE),
3 => (clk_ipd'last_event, tpd_clk_q_posedge, TRUE)),
GlitchData => q_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
end vital_lcell_ff;
----------------------------------------------------------------------------
-- Module Name : cycloneiii_ram_register
-- Description : Register module for RAM inputs/outputs
----------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.VITAL_Timing.all;
USE IEEE.VITAL_Primitives.all;
USE work.cycloneiii_atom_pack.all;
ENTITY cycloneiii_ram_register IS
GENERIC (
width : INTEGER := 1;
preset : STD_LOGIC := '0';
tipd_d : VitalDelayArrayType01(143 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
tipd_stall : VitalDelayType01 := DefPropDelay01;
tipd_aclr : VitalDelayType01 := DefPropDelay01;
tpw_ena_posedge : VitalDelayType := DefPulseWdthCnst;
tpd_clk_q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_aclr_q_posedge : VitalDelayType01 := DefPropDelay01;
tsetup_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_stall_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_stall_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_aclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_aclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst
);
PORT (
d : IN STD_LOGIC_VECTOR(width - 1 DOWNTO 0);
clk : IN STD_LOGIC;
ena : IN STD_LOGIC;
stall : IN STD_LOGIC;
aclr : IN STD_LOGIC;
devclrn : IN STD_LOGIC;
devpor : IN STD_LOGIC;
q : OUT STD_LOGIC_VECTOR(width - 1 DOWNTO 0);
aclrout : OUT STD_LOGIC
);
END cycloneiii_ram_register;
ARCHITECTURE reg_arch OF cycloneiii_ram_register IS
SIGNAL d_ipd : STD_LOGIC_VECTOR(width - 1 DOWNTO 0);
SIGNAL clk_ipd : STD_LOGIC;
SIGNAL ena_ipd : STD_LOGIC;
SIGNAL aclr_ipd : STD_LOGIC;
SIGNAL stall_ipd : STD_LOGIC;
BEGIN
WireDelay : BLOCK
BEGIN
loopbits : FOR i in d'RANGE GENERATE
VitalWireDelay (d_ipd(i), d(i), tipd_d(i));
END GENERATE;
VitalWireDelay (clk_ipd, clk, tipd_clk);
VitalWireDelay (aclr_ipd, aclr, tipd_aclr);
VitalWireDelay (ena_ipd, ena, tipd_ena);
VitalWireDelay (stall_ipd, stall, tipd_stall);
END BLOCK;
-- REMCYCLONEIII PROCESS (d_ipd,ena_ipd,clk_ipd,aclr_ipd,devclrn,devpor)
PROCESS (d_ipd,ena_ipd,stall_ipd,clk_ipd,aclr_ipd,devclrn,devpor)
VARIABLE Tviol_clk_ena : STD_ULOGIC := '0';
VARIABLE Tviol_clk_aclr : STD_ULOGIC := '0';
VARIABLE Tviol_data_clk : STD_ULOGIC := '0';
VARIABLE TimingData_clk_ena : VitalTimingDataType := VitalTimingDataInit;
VARIABLE TimingData_clk_stall : VitalTimingDataType := VitalTimingDataInit;
VARIABLE TimingData_clk_aclr : VitalTimingDataType := VitalTimingDataInit;
VARIABLE TimingData_data_clk : VitalTimingDataType := VitalTimingDataInit;
VARIABLE Tviol_ena : STD_ULOGIC := '0';
VARIABLE PeriodData_ena : VitalPeriodDataType := VitalPeriodDataInit;
VARIABLE q_VitalGlitchDataArray : VitalGlitchDataArrayType(143 downto 0);
VARIABLE CQDelay : TIME := 0 ns;
VARIABLE q_reg : STD_LOGIC_VECTOR(width - 1 DOWNTO 0) := (OTHERS => preset);
BEGIN
IF (aclr_ipd = '1' OR devclrn = '0' OR devpor = '0') THEN
q_reg := (OTHERS => preset);
ELSIF (clk_ipd = '1' AND clk_ipd'EVENT AND ena_ipd = '1' AND stall_ipd = '0') THEN
q_reg := d_ipd;
END IF;
-- Timing checks
VitalSetupHoldCheck (
Violation => Tviol_clk_ena,
TimingData => TimingData_clk_ena,
TestSignal => ena_ipd,
TestSignalName => "ena",
RefSignal => clk_ipd,
RefSignalName => "clk",
SetupHigh => tsetup_ena_clk_noedge_posedge,
SetupLow => tsetup_ena_clk_noedge_posedge,
HoldHigh => thold_ena_clk_noedge_posedge,
HoldLow => thold_ena_clk_noedge_posedge,
CheckEnabled => ((aclr_ipd) OR (NOT ena_ipd)) /= '1',
RefTransition => '/',
HeaderMsg => "/RAM Register VitalSetupHoldCheck",
XOn => DefXOnChecks,
MsgOn => DefMsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_clk_ena,
TimingData => TimingData_clk_stall,
TestSignal => stall_ipd,
TestSignalName => "stall",
RefSignal => clk_ipd,
RefSignalName => "clk",
SetupHigh => tsetup_stall_clk_noedge_posedge,
SetupLow => tsetup_stall_clk_noedge_posedge,
HoldHigh => thold_stall_clk_noedge_posedge,
HoldLow => thold_stall_clk_noedge_posedge,
CheckEnabled => ((aclr_ipd) OR (NOT ena_ipd)) /= '1',
RefTransition => '/',
HeaderMsg => "/RAM Register VitalSetupHoldCheck",
XOn => DefXOnChecks,
MsgOn => DefMsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_clk_aclr,
TimingData => TimingData_clk_aclr,
TestSignal => aclr_ipd,
TestSignalName => "aclr",
RefSignal => clk_ipd,
RefSignalName => "clk",
SetupHigh => tsetup_aclr_clk_noedge_posedge,
SetupLow => tsetup_aclr_clk_noedge_posedge,
HoldHigh => thold_aclr_clk_noedge_posedge,
HoldLow => thold_aclr_clk_noedge_posedge,
CheckEnabled => ((aclr_ipd) OR (NOT ena_ipd)) /= '1',
RefTransition => '/',
HeaderMsg => "/RAM Register VitalSetupHoldCheck",
XOn => DefXOnChecks,
MsgOn => DefMsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_data_clk,
TimingData => TimingData_data_clk,
TestSignal => d_ipd,
TestSignalName => "data",
RefSignal => clk_ipd,
RefSignalName => "clk",
SetupHigh => tsetup_d_clk_noedge_posedge,
SetupLow => tsetup_d_clk_noedge_posedge,
HoldHigh => thold_d_clk_noedge_posedge,
HoldLow => thold_d_clk_noedge_posedge,
CheckEnabled => ((aclr_ipd) OR (NOT ena_ipd)) /= '1',
RefTransition => '/',
HeaderMsg => "/RAM Register VitalSetupHoldCheck",
XOn => DefXOnChecks,
MsgOn => DefMsgOnChecks );
VitalPeriodPulseCheck (
Violation => Tviol_ena,
PeriodData => PeriodData_ena,
TestSignal => ena_ipd,
TestSignalName => "ena",
PulseWidthHigh => tpw_ena_posedge,
HeaderMsg => "/RAM Register VitalPeriodPulseCheck",
XOn => DefXOnChecks,
MsgOn => DefMsgOnChecks );
-- Path Delay Selection
CQDelay := SelectDelay (
Paths => (
(0 => (clk_ipd'LAST_EVENT,tpd_clk_q_posedge,TRUE),
1 => (aclr_ipd'LAST_EVENT,tpd_aclr_q_posedge,TRUE))
)
);
q <= TRANSPORT q_reg AFTER CQDelay;
END PROCESS;
aclrout <= aclr_ipd;
END reg_arch;
----------------------------------------------------------------------------
-- Module Name : cycloneiii_ram_pulse_generator
-- Description : Generate pulse to initiate memory read/write operations
----------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.VITAL_Timing.all;
USE IEEE.VITAL_Primitives.all;
USE work.cycloneiii_atom_pack.all;
ENTITY cycloneiii_ram_pulse_generator IS
GENERIC (
tipd_clk : VitalDelayType01 := (0.5 ns,0.5 ns);
tipd_ena : VitalDelayType01 := DefPropDelay01;
tpd_clk_pulse_posedge : VitalDelayType01 := DefPropDelay01
);
PORT (
clk,ena : IN STD_LOGIC;
delaywrite : IN STD_LOGIC := '0';
pulse,cycle : OUT STD_LOGIC
);
ATTRIBUTE VITAL_Level0 OF cycloneiii_ram_pulse_generator:ENTITY IS TRUE;
END cycloneiii_ram_pulse_generator;
ARCHITECTURE pgen_arch OF cycloneiii_ram_pulse_generator IS
ATTRIBUTE VITAL_Level0 OF pgen_arch:ARCHITECTURE IS TRUE;
SIGNAL clk_ipd,ena_ipd : STD_LOGIC;
SIGNAL state : STD_LOGIC;
BEGIN
WireDelay : BLOCK
BEGIN
VitalWireDelay (clk_ipd, clk, tipd_clk);
VitalWireDelay (ena_ipd, ena, tipd_ena);
END BLOCK;
PROCESS (clk_ipd,state)
BEGIN
IF (state = '1' AND state'EVENT) THEN
state <= '0';
ELSIF (clk_ipd = '1' AND clk_ipd'EVENT AND ena_ipd = '1') THEN
IF (delaywrite = '1') THEN
state <= '1' AFTER 1 NS; -- delayed write
ELSE
state <= '1';
END IF;
END IF;
END PROCESS;
PathDelay : PROCESS
VARIABLE pulse_VitalGlitchData : VitalGlitchDataType;
BEGIN
WAIT UNTIL state'EVENT;
VitalPathDelay01 (
OutSignal => pulse,
OutSignalName => "pulse",
OutTemp => state,
Paths => (0 => (clk_ipd'LAST_EVENT,tpd_clk_pulse_posedge,TRUE)),
GlitchData => pulse_VitalGlitchData,
Mode => DefGlitchMode,
XOn => DefXOnChecks,
MsgOn => DefMsgOnChecks
);
END PROCESS;
cycle <= clk_ipd;
END pgen_arch;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.VITAL_Timing.all;
USE IEEE.VITAL_Primitives.all;
USE work.cycloneiii_atom_pack.all;
USE work.cycloneiii_ram_register;
USE work.cycloneiii_ram_pulse_generator;
ENTITY cycloneiii_ram_block IS
GENERIC (
-- -------- GLOBAL PARAMETERS ---------
operation_mode : STRING := "single_port";
mixed_port_feed_through_mode : STRING := "dont_care";
ram_block_type : STRING := "auto";
logical_ram_name : STRING := "ram_name";
init_file : STRING := "init_file.hex";
init_file_layout : STRING := "none";
data_interleave_width_in_bits : INTEGER := 1;
data_interleave_offset_in_bits : INTEGER := 1;
port_a_logical_ram_depth : INTEGER := 0;
port_a_logical_ram_width : INTEGER := 0;
port_a_first_address : INTEGER := 0;
port_a_last_address : INTEGER := 0;
port_a_first_bit_number : INTEGER := 0;
port_a_address_clear : STRING := "none";
port_a_data_out_clear : STRING := "none";
port_a_data_in_clock : STRING := "clock0";
port_a_address_clock : STRING := "clock0";
port_a_write_enable_clock : STRING := "clock0";
port_a_read_enable_clock : STRING := "clock0";
port_a_byte_enable_clock : STRING := "clock0";
port_a_data_out_clock : STRING := "none";
port_a_data_width : INTEGER := 1;
port_a_address_width : INTEGER := 1;
port_a_byte_enable_mask_width : INTEGER := 1;
port_b_logical_ram_depth : INTEGER := 0;
port_b_logical_ram_width : INTEGER := 0;
port_b_first_address : INTEGER := 0;
port_b_last_address : INTEGER := 0;
port_b_first_bit_number : INTEGER := 0;
port_b_address_clear : STRING := "none";
port_b_data_out_clear : STRING := "none";
port_b_data_in_clock : STRING := "clock1";
port_b_address_clock : STRING := "clock1";
port_b_write_enable_clock: STRING := "clock1";
port_b_read_enable_clock: STRING := "clock1";
port_b_byte_enable_clock : STRING := "clock1";
port_b_data_out_clock : STRING := "none";
port_b_data_width : INTEGER := 1;
port_b_address_width : INTEGER := 1;
port_b_byte_enable_mask_width : INTEGER := 1;
port_a_read_during_write_mode : STRING := "new_data_no_nbe_read";
port_b_read_during_write_mode : STRING := "new_data_no_nbe_read";
power_up_uninitialized : STRING := "false";
port_b_byte_size : INTEGER := 0;
port_a_byte_size : INTEGER := 0;
safe_write : STRING := "err_on_2clk";
init_file_restructured : STRING := "unused";
lpm_type : string := "cycloneiii_ram_block";
lpm_hint : string := "true";
clk0_input_clock_enable : STRING := "none"; -- ena0,ena2,none
clk0_core_clock_enable : STRING := "none"; -- ena0,ena2,none
clk0_output_clock_enable : STRING := "none"; -- ena0,none
clk1_input_clock_enable : STRING := "none"; -- ena1,ena3,none
clk1_core_clock_enable : STRING := "none"; -- ena1,ena3,none
clk1_output_clock_enable : STRING := "none"; -- ena1,none
mem_init0 : BIT_VECTOR := X"0";
mem_init1 : BIT_VECTOR := X"0";
mem_init2 : BIT_VECTOR := X"0";
mem_init3 : BIT_VECTOR := X"0";
mem_init4 : BIT_VECTOR := X"0";
connectivity_checking : string := "off"
);
-- -------- PORT DECLARATIONS ---------
PORT (
portadatain : IN STD_LOGIC_VECTOR(port_a_data_width - 1 DOWNTO 0) := (OTHERS => '0');
portaaddr : IN STD_LOGIC_VECTOR(port_a_address_width - 1 DOWNTO 0) := (OTHERS => '0');
portawe : IN STD_LOGIC := '0';
portare : IN STD_LOGIC := '1';
portbdatain : IN STD_LOGIC_VECTOR(port_b_data_width - 1 DOWNTO 0) := (OTHERS => '0');
portbaddr : IN STD_LOGIC_VECTOR(port_b_address_width - 1 DOWNTO 0) := (OTHERS => '0');
portbwe : IN STD_LOGIC := '0';
portbre : IN STD_LOGIC := '1';
clk0 : IN STD_LOGIC := '0';
clk1 : IN STD_LOGIC := '0';
ena0 : IN STD_LOGIC := '1';
ena1 : IN STD_LOGIC := '1';
ena2 : IN STD_LOGIC := '1';
ena3 : IN STD_LOGIC := '1';
clr0 : IN STD_LOGIC := '0';
clr1 : IN STD_LOGIC := '0';
portabyteenamasks : IN STD_LOGIC_VECTOR(port_a_byte_enable_mask_width - 1 DOWNTO 0) := (OTHERS => '1');
portbbyteenamasks : IN STD_LOGIC_VECTOR(port_b_byte_enable_mask_width - 1 DOWNTO 0) := (OTHERS => '1');
devclrn : IN STD_LOGIC := '1';
devpor : IN STD_LOGIC := '1';
portaaddrstall : IN STD_LOGIC := '0';
portbaddrstall : IN STD_LOGIC := '0';
portadataout : OUT STD_LOGIC_VECTOR(port_a_data_width - 1 DOWNTO 0);
portbdataout : OUT STD_LOGIC_VECTOR(port_b_data_width - 1 DOWNTO 0)
);
END cycloneiii_ram_block;
ARCHITECTURE block_arch OF cycloneiii_ram_block IS
COMPONENT cycloneiii_ram_pulse_generator
PORT (
clk : IN STD_LOGIC;
ena : IN STD_LOGIC;
delaywrite : IN STD_LOGIC := '0';
pulse : OUT STD_LOGIC;
cycle : OUT STD_LOGIC
);
END COMPONENT;
COMPONENT cycloneiii_ram_register
GENERIC (
preset : STD_LOGIC := '0';
width : integer := 1
);
PORT (
d : IN STD_LOGIC_VECTOR(width - 1 DOWNTO 0);
clk : IN STD_LOGIC;
aclr : IN STD_LOGIC;
devclrn : IN STD_LOGIC;
devpor : IN STD_LOGIC;
ena : IN STD_LOGIC;
stall : IN STD_LOGIC;
q : OUT STD_LOGIC_VECTOR(width - 1 DOWNTO 0);
aclrout : OUT STD_LOGIC
);
END COMPONENT;
FUNCTION cond (condition : BOOLEAN;CONSTANT a,b : INTEGER) RETURN INTEGER IS
VARIABLE c: INTEGER;
BEGIN
IF (condition) THEN c := a; ELSE c := b; END IF;
RETURN c;
END;
SUBTYPE port_type IS BOOLEAN;
CONSTANT primary : port_type := TRUE;
CONSTANT secondary : port_type := FALSE;
CONSTANT primary_port_is_a : BOOLEAN := (port_b_data_width <= port_a_data_width);
CONSTANT primary_port_is_b : BOOLEAN := NOT primary_port_is_a;
CONSTANT mode_is_rom : BOOLEAN := (operation_mode = "rom");
CONSTANT mode_is_sp : BOOLEAN := (operation_mode = "single_port");
CONSTANT mode_is_dp : BOOLEAN := (operation_mode = "dual_port");
CONSTANT mode_is_bdp : BOOLEAN := (operation_mode = "bidir_dual_port");
CONSTANT wired_mode : BOOLEAN := (port_a_address_width = port_b_address_width) AND (port_a_address_width = 1)
AND (port_a_data_width /= port_b_data_width);
CONSTANT num_cols : INTEGER := cond(mode_is_rom OR mode_is_sp,1,
cond(wired_mode,2,2 ** (ABS(port_b_address_width - port_a_address_width))));
CONSTANT data_width : INTEGER := cond(primary_port_is_a,port_a_data_width,port_b_data_width);
CONSTANT data_unit_width : INTEGER := cond(mode_is_rom OR mode_is_sp OR primary_port_is_b,port_a_data_width,port_b_data_width);
CONSTANT address_unit_width : INTEGER := cond(mode_is_rom OR mode_is_sp OR primary_port_is_a,port_a_address_width,port_b_address_width);
CONSTANT address_width : INTEGER := cond(mode_is_rom OR mode_is_sp OR primary_port_is_b,port_a_address_width,port_b_address_width);
CONSTANT byte_size_a : INTEGER := port_a_data_width / port_a_byte_enable_mask_width;
CONSTANT byte_size_b : INTEGER := port_b_data_width / port_b_byte_enable_mask_width;
CONSTANT out_a_is_reg : BOOLEAN := (port_a_data_out_clock /= "none" AND port_a_data_out_clock /= "UNUSED");
CONSTANT out_b_is_reg : BOOLEAN := (port_b_data_out_clock /= "none" AND port_b_data_out_clock /= "UNUSED");
CONSTANT bytes_a_disabled : STD_LOGIC_VECTOR(port_a_byte_enable_mask_width - 1 DOWNTO 0) := (OTHERS => '0');
CONSTANT bytes_b_disabled : STD_LOGIC_VECTOR(port_b_byte_enable_mask_width - 1 DOWNTO 0) := (OTHERS => '0');
CONSTANT ram_type : BOOLEAN := FALSE;
TYPE bool_to_std_logic_map IS ARRAY(TRUE DOWNTO FALSE) OF STD_LOGIC;
CONSTANT bool_to_std_logic : bool_to_std_logic_map := ('1','0');
-- Hardware write modes
CONSTANT dual_clock : BOOLEAN := (operation_mode = "dual_port" OR
operation_mode = "bidir_dual_port") AND
(port_b_address_clock = "clock1");
CONSTANT both_new_data_same_port : BOOLEAN := (
((port_a_read_during_write_mode = "new_data_no_nbe_read") OR
(port_a_read_during_write_mode = "dont_care")) AND
((port_b_read_during_write_mode = "new_data_no_nbe_read") OR
(port_b_read_during_write_mode = "dont_care"))
);
SIGNAL hw_write_mode_a : STRING(3 DOWNTO 1);
SIGNAL hw_write_mode_b : STRING(3 DOWNTO 1);
SIGNAL delay_write_pulse_a : STD_LOGIC ;
SIGNAL delay_write_pulse_b : STD_LOGIC ;
CONSTANT be_mask_write_a : BOOLEAN := (port_a_read_during_write_mode = "new_data_with_nbe_read");
CONSTANT be_mask_write_b : BOOLEAN := (port_b_read_during_write_mode = "new_data_with_nbe_read");
CONSTANT old_data_write_a : BOOLEAN := (port_a_read_during_write_mode = "old_data");
CONSTANT old_data_write_b : BOOLEAN := (port_b_read_during_write_mode = "old_data");
SIGNAL read_before_write_a : BOOLEAN;
SIGNAL read_before_write_b : BOOLEAN;
-- -------- internal signals ---------
-- clock / clock enable
SIGNAL clk_a_in,clk_b_in : STD_LOGIC;
SIGNAL clk_a_byteena,clk_b_byteena : STD_LOGIC;
SIGNAL clk_a_out,clk_b_out : STD_LOGIC;
SIGNAL clkena_a_out,clkena_b_out : STD_LOGIC;
SIGNAL clkena_out_c0, clkena_out_c1 : STD_LOGIC;
SIGNAL write_cycle_a,write_cycle_b : STD_LOGIC;
SIGNAL clk_a_rena, clk_a_wena : STD_LOGIC;
SIGNAL clk_a_core : STD_LOGIC;
SIGNAL clk_b_rena, clk_b_wena : STD_LOGIC;
SIGNAL clk_b_core : STD_LOGIC;
SUBTYPE one_bit_bus_type IS STD_LOGIC_VECTOR(0 DOWNTO 0);
-- asynch clear
TYPE clear_mode_type IS ARRAY (port_type'HIGH DOWNTO port_type'LOW) OF BOOLEAN;
TYPE clear_vec_type IS ARRAY (port_type'HIGH DOWNTO port_type'LOW) OF STD_LOGIC;
SIGNAL datain_a_clr,datain_b_clr : STD_LOGIC;
SIGNAL dataout_a_clr,dataout_b_clr : STD_LOGIC;
SIGNAL dataout_a_clr_reg, dataout_b_clr_reg : STD_LOGIC;
SIGNAL dataout_a_clr_reg_in, dataout_b_clr_reg_in : one_bit_bus_type;
SIGNAL dataout_a_clr_reg_out, dataout_b_clr_reg_out : one_bit_bus_type;
SIGNAL dataout_a_clr_reg_latch, dataout_b_clr_reg_latch : STD_LOGIC;
SIGNAL dataout_a_clr_reg_latch_in, dataout_b_clr_reg_latch_in : one_bit_bus_type;
SIGNAL dataout_a_clr_reg_latch_out, dataout_b_clr_reg_latch_out : one_bit_bus_type;
SIGNAL addr_a_clr,addr_b_clr : STD_LOGIC;
SIGNAL byteena_a_clr,byteena_b_clr : STD_LOGIC;
SIGNAL we_a_clr,re_a_clr,we_b_clr,re_b_clr : STD_LOGIC;
SIGNAL datain_a_clr_in,datain_b_clr_in : STD_LOGIC;
SIGNAL addr_a_clr_in,addr_b_clr_in : STD_LOGIC;
SIGNAL byteena_a_clr_in,byteena_b_clr_in : STD_LOGIC;
SIGNAL we_a_clr_in,re_a_clr_in,we_b_clr_in,re_b_clr_in : STD_LOGIC;
SIGNAL mem_invalidate,mem_invalidate_loc,read_latch_invalidate : clear_mode_type;
SIGNAL clear_asserted_during_write : clear_vec_type;
-- port A registers
SIGNAL we_a_reg : STD_LOGIC;
SIGNAL re_a_reg : STD_LOGIC;
SIGNAL we_a_reg_in,we_a_reg_out : one_bit_bus_type;
SIGNAL re_a_reg_in,re_a_reg_out : one_bit_bus_type;
SIGNAL addr_a_reg : STD_LOGIC_VECTOR(port_a_address_width - 1 DOWNTO 0);
SIGNAL datain_a_reg : STD_LOGIC_VECTOR(port_a_data_width - 1 DOWNTO 0);
SIGNAL dataout_a_reg : STD_LOGIC_VECTOR(port_a_data_width - 1 DOWNTO 0);
SIGNAL dataout_a : STD_LOGIC_VECTOR(port_a_data_width - 1 DOWNTO 0);
SIGNAL byteena_a_reg : STD_LOGIC_VECTOR(port_a_byte_enable_mask_width- 1 DOWNTO 0);
-- port B registers
SIGNAL we_b_reg, re_b_reg : STD_LOGIC;
SIGNAL re_b_reg_in,re_b_reg_out,we_b_reg_in,we_b_reg_out : one_bit_bus_type;
SIGNAL addr_b_reg : STD_LOGIC_VECTOR(port_b_address_width - 1 DOWNTO 0);
SIGNAL datain_b_reg : STD_LOGIC_VECTOR(port_b_data_width - 1 DOWNTO 0);
SIGNAL dataout_b_reg : STD_LOGIC_VECTOR(port_b_data_width - 1 DOWNTO 0);
SIGNAL dataout_b : STD_LOGIC_VECTOR(port_b_data_width - 1 DOWNTO 0);
SIGNAL byteena_b_reg : STD_LOGIC_VECTOR(port_b_byte_enable_mask_width- 1 DOWNTO 0);
-- pulses
TYPE pulse_vec IS ARRAY (port_type'HIGH DOWNTO port_type'LOW) OF STD_LOGIC;
SIGNAL write_pulse,read_pulse,read_pulse_feedthru : pulse_vec;
SIGNAL rw_pulse : pulse_vec;
SIGNAL wpgen_a_clk,wpgen_a_clkena,wpgen_b_clk,wpgen_b_clkena : STD_LOGIC;
SIGNAL rpgen_a_clkena,rpgen_b_clkena : STD_LOGIC;
SIGNAL ftpgen_a_clkena,ftpgen_b_clkena : STD_LOGIC;
SIGNAL rwpgen_a_clkena,rwpgen_b_clkena : STD_LOGIC;
-- registered address
SIGNAL addr_prime_reg,addr_sec_reg : INTEGER;
-- input/output
SIGNAL datain_prime_reg,dataout_prime : STD_LOGIC_VECTOR(data_width - 1 DOWNTO 0);
SIGNAL datain_sec_reg,dataout_sec : STD_LOGIC_VECTOR(data_unit_width - 1 DOWNTO 0);
-- overlapping location write
SIGNAL dual_write : BOOLEAN;
-- byte enable mask write
TYPE be_mask_write_vec IS ARRAY (port_type'HIGH DOWNTO port_type'LOW) OF BOOLEAN;
SIGNAL be_mask_write : be_mask_write_vec;
-- memory core
SUBTYPE mem_word_type IS STD_LOGIC_VECTOR (data_width - 1 DOWNTO 0);
SUBTYPE mem_col_type IS STD_LOGIC_VECTOR (data_unit_width - 1 DOWNTO 0);
TYPE mem_row_type IS ARRAY (num_cols - 1 DOWNTO 0) OF mem_col_type;
TYPE mem_type IS ARRAY ((2 ** address_unit_width) - 1 DOWNTO 0) OF mem_row_type;
SIGNAL mem : mem_type;
SIGNAL init_mem : BOOLEAN := FALSE;
CONSTANT mem_x : mem_type := (OTHERS => (OTHERS => (OTHERS => 'X')));
CONSTANT row_x : mem_row_type := (OTHERS => (OTHERS => 'X'));
CONSTANT col_x : mem_col_type := (OTHERS => 'X');
SIGNAL mem_data : mem_row_type;
SIGNAL mem_unit_data : mem_col_type;
-- latches
TYPE read_latch_rec IS RECORD
prime : mem_row_type;
sec : mem_col_type;
END RECORD;
SIGNAL read_latch : read_latch_rec;
-- (row,column) coordinates
SIGNAL row_sec,col_sec : INTEGER;
-- byte enable
TYPE mask_type IS (normal,inverse);
TYPE mask_prime_type IS ARRAY(mask_type'HIGH DOWNTO mask_type'LOW) OF mem_word_type;
TYPE mask_sec_type IS ARRAY(mask_type'HIGH DOWNTO mask_type'LOW) OF mem_col_type;
TYPE mask_rec IS RECORD
prime : mask_prime_type;
sec : mask_sec_type;
END RECORD;
SIGNAL mask_vector : mask_rec;
SIGNAL mask_vector_common : mem_col_type;
FUNCTION get_mask(
b_ena : IN STD_LOGIC_VECTOR;
mode : port_type;
CONSTANT b_ena_width ,byte_size: INTEGER
) RETURN mask_rec IS
VARIABLE l : INTEGER;
VARIABLE mask : mask_rec := (
(normal => (OTHERS => '0'),inverse => (OTHERS => 'X')),
(normal => (OTHERS => '0'),inverse => (OTHERS => 'X'))
);
BEGIN
FOR l in 0 TO b_ena_width - 1 LOOP
IF (b_ena(l) = '0') THEN
IF (mode = primary) THEN
mask.prime(normal) ((l+1)*byte_size - 1 DOWNTO l*byte_size) := (OTHERS => 'X');
mask.prime(inverse)((l+1)*byte_size - 1 DOWNTO l*byte_size) := (OTHERS => '0');
ELSE
mask.sec(normal) ((l+1)*byte_size - 1 DOWNTO l*byte_size) := (OTHERS => 'X');
mask.sec(inverse)((l+1)*byte_size - 1 DOWNTO l*byte_size) := (OTHERS => '0');
END IF;
ELSIF (b_ena(l) = 'X' OR b_ena(l) = 'U') THEN
IF (mode = primary) THEN
mask.prime(normal) ((l+1)*byte_size - 1 DOWNTO l*byte_size) := (OTHERS => 'X');
ELSE
mask.sec(normal) ((l+1)*byte_size - 1 DOWNTO l*byte_size) := (OTHERS => 'X');
END IF;
END IF;
END LOOP;
RETURN mask;
END get_mask;
-- port active for read/write
SIGNAL active_a_core_in_vec,active_b_core_in_vec,active_a_core_out,active_b_core_out : one_bit_bus_type;
SIGNAL active_a_in,active_b_in : STD_LOGIC;
SIGNAL active_write_a : BOOLEAN;
SIGNAL active_write_b : BOOLEAN;
SIGNAL active_b_in_c0,active_b_core_in_c0,active_b_in_c1,active_b_core_in_c1 : STD_LOGIC;
SIGNAL active_a_core_in,active_b_core_in : STD_LOGIC;
SIGNAL active_a_core, active_b_core : BOOLEAN;
SIGNAL wire_vcc : STD_LOGIC := '1';
SIGNAL wire_gnd : STD_LOGIC := '0';
BEGIN
-- memory initialization
init_mem <= TRUE;
-- hardware write modes
hw_write_mode_a <= "R+W" WHEN ((port_a_read_during_write_mode = "old_data") OR
(port_a_read_during_write_mode = "new_data_with_nbe_read")) ELSE
" FW" WHEN (dual_clock OR (
mixed_port_feed_through_mode = "dont_care" AND
both_new_data_same_port
)) ELSE
" DW";
hw_write_mode_b <= "R+W" WHEN ((port_b_read_during_write_mode = "old_data") OR
(port_b_read_during_write_mode = "new_data_with_nbe_read")) ELSE
" FW" WHEN (dual_clock OR (
mixed_port_feed_through_mode = "dont_care" AND
both_new_data_same_port
)) ELSE
" DW";
delay_write_pulse_a <= '1' WHEN (hw_write_mode_a /= " FW") ELSE '0';
delay_write_pulse_b <= '1' WHEN (hw_write_mode_b /= " FW") ELSE '0' ;
read_before_write_a <= (hw_write_mode_a = "R+W");
read_before_write_b <= (hw_write_mode_b = "R+W");
-- -------- core logic ---------------
clk_a_in <= clk0;
clk_a_wena <= '0' WHEN (port_a_write_enable_clock = "none") ELSE clk_a_in;
clk_a_rena <= '0' WHEN (port_a_read_enable_clock = "none") ELSE clk_a_in;
clk_a_byteena <= '0' WHEN (port_a_byte_enable_clock = "none" OR port_a_byte_enable_clock = "UNUSED") ELSE clk_a_in;
clk_a_out <= '0' WHEN (port_a_data_out_clock = "none" OR port_a_data_out_clock = "UNUSED") ELSE
clk0 WHEN (port_a_data_out_clock = "clock0") ELSE clk1;
clk_b_in <= clk0 WHEN (port_b_address_clock = "clock0") ELSE clk1;
clk_b_byteena <= '0' WHEN (port_b_byte_enable_clock = "none" OR port_b_byte_enable_clock = "UNUSED") ELSE
clk0 WHEN (port_b_byte_enable_clock = "clock0") ELSE clk1;
clk_b_wena <= '0' WHEN (port_b_write_enable_clock = "none") ELSE
clk0 WHEN (port_b_write_enable_clock = "clock0") ELSE
clk1;
clk_b_rena <= '0' WHEN (port_b_read_enable_clock = "none") ELSE
clk0 WHEN (port_b_read_enable_clock = "clock0") ELSE
clk1;
clk_b_out <= '0' WHEN (port_b_data_out_clock = "none" OR port_b_data_out_clock = "UNUSED") ELSE
clk0 WHEN (port_b_data_out_clock = "clock0") ELSE clk1;
addr_a_clr_in <= '0' WHEN (port_a_address_clear = "none" OR port_a_address_clear = "UNUSED") ELSE clr0;
addr_b_clr_in <= '0' WHEN (port_b_address_clear = "none" OR port_b_address_clear = "UNUSED") ELSE
clr0 WHEN (port_b_address_clear = "clear0") ELSE clr1;
datain_a_clr_in <= '0';
datain_b_clr_in <= '0';
dataout_a_clr_reg <= '0' WHEN (port_a_data_out_clear = "none" OR port_a_data_out_clear = "UNUSED") ELSE
clr0 WHEN (port_a_data_out_clear = "clear0") ELSE clr1;
dataout_a_clr <= dataout_a_clr_reg WHEN (port_a_data_out_clock = "none" OR port_a_data_out_clock = "UNUSED") ELSE
'0';
dataout_b_clr_reg <= '0' WHEN (port_b_data_out_clear = "none" OR port_b_data_out_clear = "UNUSED") ELSE
clr0 WHEN (port_b_data_out_clear = "clear0") ELSE clr1;
dataout_b_clr <= dataout_b_clr_reg WHEN (port_b_data_out_clock = "none" OR port_b_data_out_clock = "UNUSED") ELSE
'0';
byteena_a_clr_in <= '0';
byteena_b_clr_in <= '0';
we_a_clr_in <= '0';
re_a_clr_in <= '0';
we_b_clr_in <= '0';
re_b_clr_in <= '0';
active_a_in <= '1' WHEN (clk0_input_clock_enable = "none") ELSE
ena0 WHEN (clk0_input_clock_enable = "ena0") ELSE
ena2;
active_a_core_in <= '1' WHEN (clk0_core_clock_enable = "none") ELSE
ena0 WHEN (clk0_core_clock_enable = "ena0") ELSE
ena2;
be_mask_write(primary_port_is_a) <= be_mask_write_a;
be_mask_write(primary_port_is_b) <= be_mask_write_b;
active_b_in_c0 <= '1' WHEN (clk0_input_clock_enable = "none") ELSE
ena0 WHEN (clk0_input_clock_enable = "ena0") ELSE
ena2;
active_b_in_c1 <= '1' WHEN (clk1_input_clock_enable = "none") ELSE
ena1 WHEN (clk1_input_clock_enable = "ena1") ELSE
ena3;
active_b_in <= active_b_in_c0 WHEN (port_b_address_clock = "clock0") ELSE active_b_in_c1;
active_b_core_in_c0 <= '1' WHEN (clk0_core_clock_enable = "none") ELSE
ena0 WHEN (clk0_core_clock_enable = "ena0") ELSE
ena2;
active_b_core_in_c1 <= '1' WHEN (clk1_core_clock_enable = "none") ELSE
ena1 WHEN (clk1_core_clock_enable = "ena1") ELSE
ena3;
active_b_core_in <= active_b_core_in_c0 WHEN (port_b_address_clock = "clock0") ELSE active_b_core_in_c1;
active_write_a <= (byteena_a_reg /= bytes_a_disabled);
active_write_b <= (byteena_b_reg /= bytes_b_disabled);
-- Store core clock enable value for delayed write
-- port A core active
active_a_core_in_vec(0) <= active_a_core_in;
active_core_port_a : cycloneiii_ram_register
GENERIC MAP ( width => 1 )
PORT MAP (
d => active_a_core_in_vec,
clk => clk_a_in,
aclr => wire_gnd,
devclrn => wire_vcc,devpor => wire_vcc,
ena => wire_vcc,
stall => wire_gnd,
q => active_a_core_out
);
active_a_core <= (active_a_core_out(0) = '1');
-- port B core active
active_b_core_in_vec(0) <= active_b_core_in;
active_core_port_b : cycloneiii_ram_register
GENERIC MAP ( width => 1 )
PORT MAP (
d => active_b_core_in_vec,
clk => clk_b_in,
aclr => wire_gnd,
devclrn => wire_vcc,devpor => wire_vcc,
ena => wire_vcc,
stall => wire_gnd,
q => active_b_core_out
);
active_b_core <= (active_b_core_out(0) = '1');
-- ------ A input registers
-- write enable
we_a_reg_in(0) <= '0' WHEN mode_is_rom ELSE portawe;
we_a_register : cycloneiii_ram_register
GENERIC MAP ( width => 1 )
PORT MAP (
d => we_a_reg_in,
clk => clk_a_wena,
aclr => we_a_clr_in,
devclrn => devclrn,
devpor => devpor,
stall => wire_gnd,
ena => active_a_in,
q => we_a_reg_out,
aclrout => we_a_clr
);
we_a_reg <= we_a_reg_out(0);
-- read enable
re_a_reg_in(0) <= portare;
re_a_register : cycloneiii_ram_register
GENERIC MAP ( width => 1 )
PORT MAP (
d => re_a_reg_in,
clk => clk_a_rena,
aclr => re_a_clr_in,
devclrn => devclrn,
devpor => devpor,
stall => wire_gnd,
ena => active_a_in,
q => re_a_reg_out,
aclrout => re_a_clr
);
re_a_reg <= re_a_reg_out(0);
-- address
addr_a_register : cycloneiii_ram_register
GENERIC MAP ( width => port_a_address_width )
PORT MAP (
d => portaaddr,
clk => clk_a_in,
aclr => addr_a_clr_in,
devclrn => devclrn,
devpor => devpor,
stall => portaaddrstall,
ena => active_a_in,
q => addr_a_reg,
aclrout => addr_a_clr
);
-- data
datain_a_register : cycloneiii_ram_register
GENERIC MAP ( width => port_a_data_width )
PORT MAP (
d => portadatain,
clk => clk_a_in,
aclr => datain_a_clr_in,
devclrn => devclrn,
devpor => devpor,
stall => wire_gnd,
ena => active_a_in,
q => datain_a_reg,
aclrout => datain_a_clr
);
-- byte enable
byteena_a_register : cycloneiii_ram_register
GENERIC MAP (
width => port_a_byte_enable_mask_width,
preset => '1'
)
PORT MAP (
d => portabyteenamasks,
clk => clk_a_byteena,
aclr => byteena_a_clr_in,
devclrn => devclrn,
devpor => devpor,
stall => wire_gnd,
ena => active_a_in,
q => byteena_a_reg,
aclrout => byteena_a_clr
);
-- ------ B input registers
-- read enable
re_b_reg_in(0) <= portbre;
re_b_register : cycloneiii_ram_register
GENERIC MAP (
width => 1
)
PORT MAP (
d => re_b_reg_in,
clk => clk_b_in,
aclr => re_b_clr_in,
devclrn => devclrn,
devpor => devpor,
stall => wire_gnd,
ena => active_b_in,
q => re_b_reg_out,
aclrout => re_b_clr
);
re_b_reg <= re_b_reg_out(0);
-- write enable
we_b_reg_in(0) <= portbwe;
we_b_register : cycloneiii_ram_register
GENERIC MAP (
width => 1
)
PORT MAP (
d => we_b_reg_in,
clk => clk_b_in,
aclr => we_b_clr_in,
devclrn => devclrn,
devpor => devpor,
stall => wire_gnd,
ena => active_b_in,
q => we_b_reg_out,
aclrout => we_b_clr
);
we_b_reg <= we_b_reg_out(0);
-- address
addr_b_register : cycloneiii_ram_register
GENERIC MAP ( width => port_b_address_width )
PORT MAP (
d => portbaddr,
clk => clk_b_in,
aclr => addr_b_clr_in,
devclrn => devclrn,
devpor => devpor,
stall => portbaddrstall,
ena => active_b_in,
q => addr_b_reg,
aclrout => addr_b_clr
);
-- data
datain_b_register : cycloneiii_ram_register
GENERIC MAP ( width => port_b_data_width )
PORT MAP (
d => portbdatain,
clk => clk_b_in,
aclr => datain_b_clr_in,
devclrn => devclrn,
devpor => devpor,
stall => wire_gnd,
ena => active_b_in,
q => datain_b_reg,
aclrout => datain_b_clr
);
-- byte enable
byteena_b_register : cycloneiii_ram_register
GENERIC MAP (
width => port_b_byte_enable_mask_width,
preset => '1'
)
PORT MAP (
d => portbbyteenamasks,
clk => clk_b_byteena,
aclr => byteena_b_clr_in,
devclrn => devclrn,
devpor => devpor,
stall => wire_gnd,
ena => active_b_in,
q => byteena_b_reg,
aclrout => byteena_b_clr
);
datain_prime_reg <= datain_a_reg WHEN primary_port_is_a ELSE datain_b_reg;
addr_prime_reg <= alt_conv_integer(addr_a_reg) WHEN primary_port_is_a ELSE alt_conv_integer(addr_b_reg);
datain_sec_reg <= (OTHERS => 'U') WHEN (mode_is_rom OR mode_is_sp) ELSE
datain_b_reg WHEN primary_port_is_a ELSE datain_a_reg;
addr_sec_reg <= alt_conv_integer(addr_b_reg) WHEN primary_port_is_a ELSE alt_conv_integer(addr_a_reg);
-- Write pulse generation
wpgen_a_clk <= clk_a_in;
wpgen_a_clkena <= '1' WHEN (active_a_core AND active_write_a AND (we_a_reg = '1')) ELSE '0';
wpgen_a : cycloneiii_ram_pulse_generator
PORT MAP (
clk => wpgen_a_clk,
ena => wpgen_a_clkena,
delaywrite => delay_write_pulse_a,
pulse => write_pulse(primary_port_is_a),
cycle => write_cycle_a
);
wpgen_b_clk <= clk_b_in;
wpgen_b_clkena <= '1' WHEN (active_b_core AND active_write_b AND mode_is_bdp AND (we_b_reg = '1')) ELSE '0';
wpgen_b : cycloneiii_ram_pulse_generator
PORT MAP (
clk => wpgen_b_clk,
ena => wpgen_b_clkena,
delaywrite => delay_write_pulse_b,
pulse => write_pulse(primary_port_is_b),
cycle => write_cycle_b
);
-- Read pulse generation
rpgen_a_clkena <= '1' WHEN (active_a_core AND (re_a_reg = '1') AND (we_a_reg = '0') AND (dataout_a_clr = '0')) ELSE '0';
rpgen_a : cycloneiii_ram_pulse_generator
PORT MAP (
clk => clk_a_in,
ena => rpgen_a_clkena,
cycle => clk_a_core,
pulse => read_pulse(primary_port_is_a)
);
rpgen_b_clkena <= '1' WHEN ((mode_is_dp OR mode_is_bdp) AND active_b_core AND (re_b_reg = '1') AND (we_b_reg = '0') AND (dataout_b_clr = '0')) ELSE '0';
rpgen_b : cycloneiii_ram_pulse_generator
PORT MAP (
clk => clk_b_in,
ena => rpgen_b_clkena,
cycle => clk_b_core,
pulse => read_pulse(primary_port_is_b)
);
-- Read-during-Write pulse generation
rwpgen_a_clkena <= '1' WHEN (active_a_core AND (re_a_reg = '1') AND (we_a_reg = '1') AND read_before_write_a AND (dataout_a_clr = '0')) ELSE '0';
rwpgen_a : cycloneiii_ram_pulse_generator
PORT MAP (
clk => clk_a_in,
ena => rwpgen_a_clkena,
pulse => rw_pulse(primary_port_is_a)
);
rwpgen_b_clkena <= '1' WHEN (active_b_core AND mode_is_bdp AND (re_b_reg = '1') AND (we_b_reg = '1') AND read_before_write_b AND (dataout_b_clr = '0')) ELSE '0';
rwpgen_b : cycloneiii_ram_pulse_generator
PORT MAP (
clk => clk_b_in,
ena => rwpgen_b_clkena,
pulse => rw_pulse(primary_port_is_b)
);
-- Create internal masks for byte enable processing
mask_create : PROCESS (byteena_a_reg,byteena_b_reg)
VARIABLE mask : mask_rec;
BEGIN
IF (byteena_a_reg'EVENT) THEN
mask := get_mask(byteena_a_reg,primary_port_is_a,port_a_byte_enable_mask_width,byte_size_a);
IF (primary_port_is_a) THEN
mask_vector.prime <= mask.prime;
ELSE
mask_vector.sec <= mask.sec;
END IF;
END IF;
IF (byteena_b_reg'EVENT) THEN
mask := get_mask(byteena_b_reg,primary_port_is_b,port_b_byte_enable_mask_width,byte_size_b);
IF (primary_port_is_b) THEN
mask_vector.prime <= mask.prime;
ELSE
mask_vector.sec <= mask.sec;
END IF;
END IF;
END PROCESS mask_create;
-- (row,col) coordinates
row_sec <= addr_sec_reg / num_cols;
col_sec <= addr_sec_reg mod num_cols;
mem_rw : PROCESS (init_mem,
write_pulse,read_pulse,read_pulse_feedthru,
rw_pulse,
dataout_a_clr, dataout_b_clr,
mem_invalidate,mem_invalidate_loc,read_latch_invalidate)
-- mem init
TYPE rw_type IS ARRAY (port_type'HIGH DOWNTO port_type'LOW) OF BOOLEAN;
VARIABLE addr_range_init,row,col,index : INTEGER;
VARIABLE mem_init_std : STD_LOGIC_VECTOR((port_a_last_address - port_a_first_address + 1)*port_a_data_width - 1 DOWNTO 0);
VARIABLE mem_val : mem_type;
-- read/write
VARIABLE mem_data_p : mem_row_type;
VARIABLE row_prime,col_prime : INTEGER;
VARIABLE access_same_location : BOOLEAN;
VARIABLE read_during_write : rw_type;
BEGIN
-- Latch Clear
IF (dataout_a_clr'EVENT AND dataout_a_clr = '1') THEN
IF (primary_port_is_a) THEN
read_latch.prime <= (OTHERS => (OTHERS => '0'));
dataout_prime <= (OTHERS => '0');
ELSE
read_latch.sec <= (OTHERS => '0');
dataout_sec <= (OTHERS => '0');
END IF;
END IF;
IF (dataout_b_clr'EVENT AND dataout_b_clr = '1') THEN
IF (primary_port_is_b) THEN
read_latch.prime <= (OTHERS => (OTHERS => '0'));
dataout_prime <= (OTHERS => '0');
ELSE
read_latch.sec <= (OTHERS => '0');
dataout_sec <= (OTHERS => '0');
END IF;
END IF;
read_during_write := (FALSE,FALSE);
-- Memory initialization
IF (init_mem'EVENT) THEN
-- Initialize output latches to 0
IF (primary_port_is_a) THEN
dataout_prime <= (OTHERS => '0');
IF (mode_is_dp OR mode_is_bdp) THEN dataout_sec <= (OTHERS => '0'); END IF;
ELSE
dataout_sec <= (OTHERS => '0');
IF (mode_is_dp OR mode_is_bdp) THEN dataout_prime <= (OTHERS => '0'); END IF;
END IF;
IF (power_up_uninitialized = "false" AND (NOT ram_type)) THEN
mem_val := (OTHERS => (OTHERS => (OTHERS => '0')));
END IF;
IF (primary_port_is_a) THEN
addr_range_init := port_a_last_address - port_a_first_address + 1;
ELSE
addr_range_init := port_b_last_address - port_b_first_address + 1;
END IF;
IF (init_file_layout = "port_a" OR init_file_layout = "port_b") THEN
mem_init_std := to_stdlogicvector(mem_init4 & mem_init3 & mem_init2 & mem_init1 & mem_init0)((port_a_last_address - port_a_first_address + 1)*port_a_data_width - 1 DOWNTO 0);
FOR row IN 0 TO addr_range_init - 1 LOOP
FOR col IN 0 to num_cols - 1 LOOP
index := row * data_width;
mem_val(row)(col) := mem_init_std(index + (col+1)*data_unit_width -1 DOWNTO
index + col*data_unit_width);
END LOOP;
END LOOP;
END IF;
mem <= mem_val;
END IF;
access_same_location := (mode_is_dp OR mode_is_bdp) AND (addr_prime_reg = row_sec);
-- Read before Write stage 1 : read data from memory
-- Read before Write stage 2 : send data to output
IF (rw_pulse(primary)'EVENT) THEN
IF (rw_pulse(primary) = '1') THEN
read_latch.prime <= mem(addr_prime_reg);
ELSE
IF (be_mask_write(primary)) THEN
FOR i IN 0 TO data_width - 1 LOOP
IF (mask_vector.prime(normal)(i) = 'X') THEN
row_prime := i / data_unit_width; col_prime := i mod data_unit_width;
dataout_prime(i) <= read_latch.prime(row_prime)(col_prime);
END IF;
END LOOP;
ELSE
FOR i IN 0 TO data_width - 1 LOOP
row_prime := i / data_unit_width; col_prime := i mod data_unit_width;
dataout_prime(i) <= read_latch.prime(row_prime)(col_prime);
END LOOP;
END IF;
END IF;
END IF;
IF (rw_pulse(secondary)'EVENT) THEN
IF (rw_pulse(secondary) = '1') THEN
read_latch.sec <= mem(row_sec)(col_sec);
ELSE
IF (be_mask_write(secondary)) THEN
FOR i IN 0 TO data_unit_width - 1 LOOP
IF (mask_vector.sec(normal)(i) = 'X') THEN
dataout_sec(i) <= read_latch.sec(i);
END IF;
END LOOP;
ELSE
dataout_sec <= read_latch.sec;
END IF;
END IF;
END IF;
-- Write stage 1 : X to buffer
-- Write stage 2 : actual data to memory
IF (write_pulse(primary)'EVENT) THEN
IF (write_pulse(primary) = '1') THEN
mem_data_p := mem(addr_prime_reg);
FOR i IN 0 TO num_cols - 1 LOOP
mem_data_p(i) := mem_data_p(i) XOR
mask_vector.prime(inverse)((i + 1)*data_unit_width - 1 DOWNTO i*data_unit_width);
END LOOP;
read_during_write(secondary) := (access_same_location AND read_pulse(secondary)'EVENT AND read_pulse(secondary) = '1');
IF (read_during_write(secondary)) THEN
read_latch.sec <= mem_data_p(col_sec);
ELSE
mem_data <= mem_data_p;
END IF;
ELSIF (clear_asserted_during_write(primary) /= '1') THEN
FOR i IN 0 TO data_width - 1 LOOP
IF (mask_vector.prime(normal)(i) = '0') THEN
mem(addr_prime_reg)(i / data_unit_width)(i mod data_unit_width) <= datain_prime_reg(i);
ELSIF (mask_vector.prime(inverse)(i) = 'X') THEN
mem(addr_prime_reg)(i / data_unit_width)(i mod data_unit_width) <= 'X';
END IF;
END LOOP;
END IF;
END IF;
IF (write_pulse(secondary)'EVENT) THEN
IF (write_pulse(secondary) = '1') THEN
read_during_write(primary) := (access_same_location AND read_pulse(primary)'EVENT AND read_pulse(primary) = '1');
IF (read_during_write(primary)) THEN
read_latch.prime <= mem(addr_prime_reg);
read_latch.prime(col_sec) <= mem(row_sec)(col_sec) XOR mask_vector.sec(inverse);
ELSE
mem_unit_data <= mem(row_sec)(col_sec) XOR mask_vector.sec(inverse);
END IF;
IF (access_same_location AND write_pulse(primary)'EVENT AND write_pulse(primary) = '1') THEN
mask_vector_common <=
mask_vector.prime(inverse)(((col_sec + 1)* data_unit_width - 1) DOWNTO col_sec*data_unit_width) AND
mask_vector.sec(inverse);
dual_write <= TRUE;
END IF;
ELSIF (clear_asserted_during_write(secondary) /= '1') THEN
FOR i IN 0 TO data_unit_width - 1 LOOP
IF (mask_vector.sec(normal)(i) = '0') THEN
mem(row_sec)(col_sec)(i) <= datain_sec_reg(i);
ELSIF (mask_vector.sec(inverse)(i) = 'X') THEN
mem(row_sec)(col_sec)(i) <= 'X';
END IF;
END LOOP;
END IF;
END IF;
-- Simultaneous write
IF (dual_write AND write_pulse = "00") THEN
mem(row_sec)(col_sec) <= mem(row_sec)(col_sec) XOR mask_vector_common;
dual_write <= FALSE;
END IF;
-- Read stage 1 : read data
-- Read stage 2 : send data to output
IF ((NOT read_during_write(primary)) AND read_pulse(primary)'EVENT) THEN
IF (read_pulse(primary) = '1') THEN
read_latch.prime <= mem(addr_prime_reg);
IF (access_same_location AND write_pulse(secondary) = '1') THEN
read_latch.prime(col_sec) <= mem_unit_data;
END IF;
ELSE
FOR i IN 0 TO data_width - 1 LOOP
row_prime := i / data_unit_width; col_prime := i mod data_unit_width;
dataout_prime(i) <= read_latch.prime(row_prime)(col_prime);
END LOOP;
END IF;
END IF;
IF ((NOT read_during_write(secondary)) AND read_pulse(secondary)'EVENT) THEN
IF (read_pulse(secondary) = '1') THEN
IF (access_same_location AND write_pulse(primary) = '1') THEN
read_latch.sec <= mem_data(col_sec);
ELSE
read_latch.sec <= mem(row_sec)(col_sec);
END IF;
ELSE
dataout_sec <= read_latch.sec;
END IF;
END IF;
-- Same port feed thru
IF (read_pulse_feedthru(primary)'EVENT AND read_pulse_feedthru(primary) = '0') THEN
IF (be_mask_write(primary)) THEN
FOR i IN 0 TO data_width - 1 LOOP
IF (mask_vector.prime(normal)(i) = '0') THEN
dataout_prime(i) <= datain_prime_reg(i);
END IF;
END LOOP;
ELSE
dataout_prime <= datain_prime_reg XOR mask_vector.prime(normal);
END IF;
END IF;
IF (read_pulse_feedthru(secondary)'EVENT AND read_pulse_feedthru(secondary) = '0') THEN
IF (be_mask_write(secondary)) THEN
FOR i IN 0 TO data_unit_width - 1 LOOP
IF (mask_vector.sec(normal)(i) = '0') THEN
dataout_sec(i) <= datain_sec_reg(i);
END IF;
END LOOP;
ELSE
dataout_sec <= datain_sec_reg XOR mask_vector.sec(normal);
END IF;
END IF;
-- Async clear
IF (mem_invalidate'EVENT) THEN
IF (mem_invalidate(primary) = TRUE OR mem_invalidate(secondary) = TRUE) THEN
mem <= mem_x;
END IF;
END IF;
IF (mem_invalidate_loc'EVENT) THEN
IF (mem_invalidate_loc(primary)) THEN mem(addr_prime_reg) <= row_x; END IF;
IF (mem_invalidate_loc(secondary)) THEN mem(row_sec)(col_sec) <= col_x; END IF;
END IF;
IF (read_latch_invalidate'EVENT) THEN
IF (read_latch_invalidate(primary)) THEN
read_latch.prime <= row_x;
END IF;
IF (read_latch_invalidate(secondary)) THEN
read_latch.sec <= col_x;
END IF;
END IF;
END PROCESS mem_rw;
-- Same port feed through
ftpgen_a_clkena <= '1' WHEN (active_a_core AND (NOT mode_is_dp) AND (NOT old_data_write_a) AND (we_a_reg = '1') AND (re_a_reg = '1') AND (dataout_a_clr = '0')) ELSE '0';
ftpgen_a : cycloneiii_ram_pulse_generator
PORT MAP (
clk => clk_a_in,
ena => ftpgen_a_clkena,
pulse => read_pulse_feedthru(primary_port_is_a)
);
ftpgen_b_clkena <= '1' WHEN (active_b_core AND mode_is_bdp AND (NOT old_data_write_b) AND (we_b_reg = '1') AND (re_b_reg = '1') AND (dataout_b_clr = '0')) ELSE '0';
ftpgen_b : cycloneiii_ram_pulse_generator
PORT MAP (
clk => clk_b_in,
ena => ftpgen_b_clkena,
pulse => read_pulse_feedthru(primary_port_is_b)
);
-- Asynch clear events
clear_a : PROCESS(addr_a_clr,we_a_clr,datain_a_clr)
BEGIN
IF (addr_a_clr'EVENT AND addr_a_clr = '1') THEN
clear_asserted_during_write(primary_port_is_a) <= write_pulse(primary_port_is_a);
IF (active_write_a AND (write_cycle_a = '1') AND (we_a_reg = '1')) THEN
mem_invalidate(primary_port_is_a) <= TRUE,FALSE AFTER 0.5 ns;
ELSIF (active_a_core AND re_a_reg = '1' AND dataout_a_clr = '0' AND dataout_a_clr_reg_latch = '0') THEN
read_latch_invalidate(primary_port_is_a) <= TRUE,FALSE AFTER 0.5 ns;
END IF;
END IF;
IF ((we_a_clr'EVENT AND we_a_clr = '1') OR (datain_a_clr'EVENT AND datain_a_clr = '1')) THEN
clear_asserted_during_write(primary_port_is_a) <= write_pulse(primary_port_is_a);
IF (active_write_a AND (write_cycle_a = '1') AND (we_a_reg = '1')) THEN
mem_invalidate_loc(primary_port_is_a) <= TRUE,FALSE AFTER 0.5 ns;
read_latch_invalidate(primary_port_is_a) <= TRUE,FALSE AFTER 0.5 ns;
END IF;
END IF;
END PROCESS clear_a;
clear_b : PROCESS(addr_b_clr,we_b_clr,datain_b_clr)
BEGIN
IF (addr_b_clr'EVENT AND addr_b_clr = '1') THEN
clear_asserted_during_write(primary_port_is_b) <= write_pulse(primary_port_is_b);
IF (mode_is_bdp AND active_write_b AND (write_cycle_b = '1') AND (we_b_reg = '1')) THEN
mem_invalidate(primary_port_is_b) <= TRUE,FALSE AFTER 0.5 ns;
ELSIF ((mode_is_dp OR mode_is_bdp) AND active_b_core AND re_b_reg = '1' AND dataout_b_clr = '0' AND dataout_b_clr_reg_latch = '0') THEN
read_latch_invalidate(primary_port_is_b) <= TRUE,FALSE AFTER 0.5 ns;
END IF;
END IF;
IF ((we_b_clr'EVENT AND we_b_clr = '1') OR (datain_b_clr'EVENT AND datain_b_clr = '1')) THEN
clear_asserted_during_write(primary_port_is_b) <= write_pulse(primary_port_is_b);
IF (mode_is_bdp AND active_write_b AND (write_cycle_b = '1') AND (we_b_reg = '1')) THEN
mem_invalidate_loc(primary_port_is_b) <= TRUE,FALSE AFTER 0.5 ns;
read_latch_invalidate(primary_port_is_b) <= TRUE,FALSE AFTER 0.5 ns;
END IF;
END IF;
END PROCESS clear_b;
-- Clear mux registers (Latch Clear)
-- Port A output register clear
dataout_a_clr_reg_latch_in(0) <= dataout_a_clr;
aclr_a_mux_register : cycloneiii_ram_register
GENERIC MAP ( width => 1 )
PORT MAP (
d => dataout_a_clr_reg_latch_in,
clk => clk_a_core,
aclr => wire_gnd,
devclrn => devclrn,
devpor => devpor,
stall => wire_gnd,
ena => wire_vcc,
q => dataout_a_clr_reg_latch_out
);
dataout_a_clr_reg_latch <= dataout_a_clr_reg_latch_out(0);
-- Port B output register clear
dataout_b_clr_reg_latch_in(0) <= dataout_b_clr;
aclr_b_mux_register : cycloneiii_ram_register
GENERIC MAP ( width => 1 )
PORT MAP (
d => dataout_b_clr_reg_latch_in,
clk => clk_b_core,
aclr => wire_gnd,
devclrn => devclrn,
devpor => devpor,
stall => wire_gnd,
ena => wire_vcc,
q => dataout_b_clr_reg_latch_out
);
dataout_b_clr_reg_latch <= dataout_b_clr_reg_latch_out(0);
-- ------ Output registers
clkena_out_c0 <= '1' WHEN (clk0_output_clock_enable = "none") ELSE ena0;
clkena_out_c1 <= '1' WHEN (clk1_output_clock_enable = "none") ELSE ena1;
clkena_a_out <= clkena_out_c0 WHEN (port_a_data_out_clock = "clock0") ELSE clkena_out_c1;
clkena_b_out <= clkena_out_c0 WHEN (port_b_data_out_clock = "clock0") ELSE clkena_out_c1;
dataout_a <= dataout_prime WHEN primary_port_is_a ELSE dataout_sec;
dataout_b <= (OTHERS => 'U') WHEN (mode_is_rom OR mode_is_sp) ELSE
dataout_prime WHEN primary_port_is_b ELSE dataout_sec;
dataout_a_register : cycloneiii_ram_register
GENERIC MAP ( width => port_a_data_width )
PORT MAP (
d => dataout_a,
clk => clk_a_out,
aclr => dataout_a_clr_reg,
devclrn => devclrn,
devpor => devpor,
stall => wire_gnd,
ena => clkena_a_out,
q => dataout_a_reg
);
dataout_b_register : cycloneiii_ram_register
GENERIC MAP ( width => port_b_data_width )
PORT MAP (
d => dataout_b,
clk => clk_b_out,
aclr => dataout_b_clr_reg,
devclrn => devclrn,
devpor => devpor,
stall => wire_gnd,
ena => clkena_b_out,
q => dataout_b_reg
);
portadataout <= dataout_a_reg WHEN out_a_is_reg ELSE dataout_a;
portbdataout <= dataout_b_reg WHEN out_b_is_reg ELSE dataout_b;
END block_arch;
-----------------------------------------------------------------------
--
-- Module Name : cycloneiii_mac_data_reg
--
-- Description : Simulation model for the data input register of
-- Cyclone II MAC_MULT
--
-----------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.VITAL_Primitives.all;
USE IEEE.VITAL_Timing.all;
USE IEEE.std_logic_1164.all;
USE work.cycloneiii_atom_pack.all;
ENTITY cycloneiii_mac_data_reg IS
GENERIC (
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : STRING := "*";
tipd_data : VitalDelayArrayType01(17 downto 0) := (OTHERS => DefPropDelay01);
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
tipd_aclr : VitalDelayType01 := DefPropDelay01;
tsetup_data_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_data_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_aclr_dataout_posedge : VitalDelayType01 := DefPropDelay01;
tpd_clk_dataout_posedge : VitalDelayType01 := DefPropDelay01;
data_width : integer := 18
);
PORT (
-- INPUT PORTS
clk : IN std_logic;
data : IN std_logic_vector(17 DOWNTO 0);
ena : IN std_logic;
aclr : IN std_logic;
-- OUTPUT PORTS
dataout : OUT std_logic_vector(17 DOWNTO 0)
);
END cycloneiii_mac_data_reg;
ARCHITECTURE vital_cycloneiii_mac_data_reg OF cycloneiii_mac_data_reg IS
SIGNAL data_ipd : std_logic_vector(17 DOWNTO 0);
SIGNAL aclr_ipd : std_logic;
SIGNAL clk_ipd : std_logic;
SIGNAL ena_ipd : std_logic;
SIGNAL dataout_tmp : std_logic_vector(17 DOWNTO 0) := (OTHERS => '0');
BEGIN
---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
g1 : for i in data'range generate
VitalWireDelay (data_ipd(i), data(i), tipd_data(i));
end generate;
VitalWireDelay (clk_ipd, clk, tipd_clk);
VitalWireDelay (aclr_ipd, aclr, tipd_aclr);
VitalWireDelay (ena_ipd, ena, tipd_ena);
end block;
VITALtiming : process (clk_ipd, aclr_ipd, data_ipd)
variable Tviol_data_clk : std_ulogic := '0';
variable TimingData_data_clk : VitalTimingDataType := VitalTimingDataInit;
variable Tviol_ena_clk : std_ulogic := '0';
variable TimingData_ena_clk : VitalTimingDataType := VitalTimingDataInit;
begin
------------------------
-- Timing Check Section
------------------------
if (TimingChecksOn) then
VitalSetupHoldCheck (
Violation => Tviol_data_clk,
TimingData => TimingData_data_clk,
TestSignal => data,
TestSignalName => "D",
RefSignal => clk_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_data_clk_noedge_posedge,
SetupLow => tsetup_data_clk_noedge_posedge,
HoldHigh => thold_data_clk_noedge_posedge,
HoldLow => thold_data_clk_noedge_posedge,
CheckEnabled => TO_X01((aclr) OR
(NOT ena)) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/MAC_DATA_REG",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_ena_clk,
TimingData => TimingData_ena_clk,
TestSignal => ena_ipd,
TestSignalName => "ENA",
RefSignal => clk_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_ena_clk_noedge_posedge,
SetupLow => tsetup_ena_clk_noedge_posedge,
HoldHigh => thold_ena_clk_noedge_posedge,
HoldLow => thold_ena_clk_noedge_posedge,
CheckEnabled => TO_X01(aclr) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/MAC_DATA_REG",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
end if;
if (aclr_ipd = '1') then
dataout_tmp <= (OTHERS => '0');
elsif (clk_ipd'event and clk_ipd = '1' and (ena_ipd = '1')) then
dataout_tmp <= data_ipd;
end if;
end process;
----------------------
-- Path Delay Section
----------------------
PathDelay : block
begin
g1 : for i in dataout_tmp'range generate
VITALtiming : process (dataout_tmp(i))
variable dataout_VitalGlitchData : VitalGlitchDataType;
begin
VitalPathDelay01 (OutSignal => dataout(i),
OutSignalName => "DATAOUT",
OutTemp => dataout_tmp(i),
Paths => (0 => (clk_ipd'last_event, tpd_clk_dataout_posedge, TRUE),
1 => (aclr_ipd'last_event, tpd_aclr_dataout_posedge, TRUE)),
GlitchData => dataout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn);
end process;
end generate;
end block;
END vital_cycloneiii_mac_data_reg;
--------------------------------------------------------------------
--
-- Module Name : cycloneiii_mac_sign_reg
--
-- Description : Simulation model for the sign input register of
-- Cyclone II MAC_MULT
--
--------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.VITAL_Primitives.all;
USE IEEE.VITAL_Timing.all;
USE IEEE.std_logic_1164.all;
USE work.cycloneiii_atom_pack.all;
ENTITY cycloneiii_mac_sign_reg IS
GENERIC (
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : STRING := "*";
tsetup_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_clk_q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_aclr_q_posedge : VitalDelayType01 := DefPropDelay01;
tipd_d : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
tipd_aclr : VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefPropDelay01
);
PORT (
-- INPUT PORTS
clk : IN std_logic;
d : IN std_logic;
ena : IN std_logic;
aclr : IN std_logic;
-- OUTPUT PORTS
q : OUT std_logic
);
END cycloneiii_mac_sign_reg;
ARCHITECTURE cycloneiii_mac_sign_reg OF cycloneiii_mac_sign_reg IS
signal d_ipd : std_logic;
signal clk_ipd : std_logic;
signal aclr_ipd : std_logic;
signal ena_ipd : std_logic;
begin
---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
VitalWireDelay (d_ipd, d, tipd_d);
VitalWireDelay (clk_ipd, clk, tipd_clk);
VitalWireDelay (aclr_ipd, aclr, tipd_aclr);
VitalWireDelay (ena_ipd, ena, tipd_ena);
end block;
VITALtiming : process (clk_ipd, aclr_ipd)
variable Tviol_d_clk : std_ulogic := '0';
variable TimingData_d_clk : VitalTimingDataType := VitalTimingDataInit;
variable Tviol_ena_clk : std_ulogic := '0';
variable TimingData_ena_clk : VitalTimingDataType := VitalTimingDataInit;
variable q_VitalGlitchData : VitalGlitchDataType;
variable q_reg : std_logic := '0';
begin
------------------------
-- Timing Check Section
------------------------
if (TimingChecksOn) then
VitalSetupHoldCheck (
Violation => Tviol_d_clk,
TimingData => TimingData_d_clk,
TestSignal => d,
TestSignalName => "D",
RefSignal => clk_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_d_clk_noedge_posedge,
SetupLow => tsetup_d_clk_noedge_posedge,
HoldHigh => thold_d_clk_noedge_posedge,
HoldLow => thold_d_clk_noedge_posedge,
CheckEnabled => TO_X01((aclr) OR
(NOT ena)) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/SIGN_REG",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_ena_clk,
TimingData => TimingData_ena_clk,
TestSignal => ena,
TestSignalName => "ENA",
RefSignal => clk_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_ena_clk_noedge_posedge,
SetupLow => tsetup_ena_clk_noedge_posedge,
HoldHigh => thold_ena_clk_noedge_posedge,
HoldLow => thold_ena_clk_noedge_posedge,
CheckEnabled => TO_X01(aclr) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/SIGN_REG",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
end if;
if (aclr_ipd = '1') then
q_reg := '0';
elsif (clk_ipd'event and clk_ipd = '1' and (ena_ipd = '1')) then
q_reg := d_ipd;
end if;
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
OutSignal => q,
OutSignalName => "Q",
OutTemp => q_reg,
Paths => (0 => (clk_ipd'last_event, tpd_clk_q_posedge, TRUE),
1 => (aclr_ipd'last_event, tpd_aclr_q_posedge, TRUE)),
GlitchData => q_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
END cycloneiii_mac_sign_reg;
--------------------------------------------------------------------
--
-- Module Name : cycloneiii_mac_mult_internal
--
-- Description : Cyclone II MAC_MULT_INTERNAL VHDL simulation model
--
--------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.VITAL_Primitives.all;
USE IEEE.VITAL_Timing.all;
USE IEEE.std_logic_1164.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_unsigned.all;
USE work.cycloneiii_atom_pack.all;
ENTITY cycloneiii_mac_mult_internal IS
GENERIC (
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : STRING := "*";
tipd_dataa : VitalDelayArrayType01(17 downto 0)
:= (OTHERS => DefPropDelay01);
tipd_datab : VitalDelayArrayType01(17 downto 0)
:= (OTHERS => DefPropDelay01);
tipd_signa : VitalDelayType01 := DefPropDelay01;
tipd_signb : VitalDelayType01 := DefPropDelay01;
tpd_dataa_dataout : VitalDelayType01 := DefPropDelay01;
tpd_datab_dataout : VitalDelayType01 := DefPropDelay01;
tpd_signa_dataout : VitalDelayType01 := DefPropDelay01;
tpd_signb_dataout : VitalDelayType01 := DefPropDelay01;
dataa_width : integer := 18;
datab_width : integer := 18
);
PORT (
dataa : IN std_logic_vector(17 DOWNTO 0) := (OTHERS => '0');
datab : IN std_logic_vector(17 DOWNTO 0) := (OTHERS => '0');
signa : IN std_logic := '1';
signb : IN std_logic := '1';
dataout : OUT std_logic_vector((dataa_width+datab_width)-1 DOWNTO 0)
);
END cycloneiii_mac_mult_internal;
ARCHITECTURE vital_cycloneiii_mac_mult_internal OF cycloneiii_mac_mult_internal IS
-- Internal variables
SIGNAL dataa_ipd : std_logic_vector(17 DOWNTO 0);
SIGNAL datab_ipd : std_logic_vector(17 DOWNTO 0);
SIGNAL signa_ipd : std_logic;
SIGNAL signb_ipd : std_logic;
-- padding with 1's for input negation
SIGNAL reg_aclr : std_logic;
SIGNAL dataout_tmp : STD_LOGIC_VECTOR (dataa_width + datab_width downto 0) := (others => '0');
BEGIN
---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
g1 : for i in dataa'range generate
VitalWireDelay (dataa_ipd(i), dataa(i), tipd_dataa(i));
end generate;
g2 : for i in datab'range generate
VitalWireDelay (datab_ipd(i), datab(i), tipd_datab(i));
end generate;
VitalWireDelay (signa_ipd, signa, tipd_signa);
VitalWireDelay (signb_ipd, signb, tipd_signb);
end block;
VITALtiming : process(dataa_ipd, datab_ipd, signa_ipd, signb_ipd)
begin
if((signa_ipd = '0') and (signb_ipd = '1')) then
dataout_tmp <=
unsigned(dataa_ipd(dataa_width-1 downto 0)) *
signed(datab_ipd(datab_width-1 downto 0));
elsif((signa_ipd = '1') and (signb_ipd = '0')) then
dataout_tmp <=
signed(dataa_ipd(dataa_width-1 downto 0)) *
unsigned(datab_ipd(datab_width-1 downto 0));
elsif((signa_ipd = '1') and (signb_ipd = '1')) then
dataout_tmp(dataout'range) <=
signed(dataa_ipd(dataa_width-1 downto 0)) *
signed(datab_ipd(datab_width-1 downto 0));
else --((signa_ipd = '0') and (signb_ipd = '0')) then
dataout_tmp(dataout'range) <=
unsigned(dataa_ipd(dataa_width-1 downto 0)) *
unsigned(datab_ipd(datab_width-1 downto 0));
end if;
end process;
----------------------
-- Path Delay Section
----------------------
PathDelay : block
begin
g1 : for i in dataout'range generate
VITALtiming : process (dataout_tmp(i))
variable dataout_VitalGlitchData : VitalGlitchDataType;
begin
VitalPathDelay01 (OutSignal => dataout(i),
OutSignalName => "dataout",
OutTemp => dataout_tmp(i),
Paths => (0 => (dataa_ipd'last_event, tpd_dataa_dataout, TRUE),
1 => (datab_ipd'last_event, tpd_datab_dataout, TRUE),
2 => (signa'last_event, tpd_signa_dataout, TRUE),
3 => (signb'last_event, tpd_signb_dataout, TRUE)),
GlitchData => dataout_VitalGlitchData,
Mode => DefGlitchMode,
MsgOn => FALSE,
XOn => TRUE );
end process;
end generate;
end block;
END vital_cycloneiii_mac_mult_internal;
--------------------------------------------------------------------
--
-- Module Name : cycloneiii_mac_mult
--
-- Description : Cyclone II MAC_MULT VHDL simulation model
--
--------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.VITAL_Primitives.all;
USE IEEE.VITAL_Timing.all;
USE IEEE.std_logic_1164.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_unsigned.all;
USE work.cycloneiii_atom_pack.all;
USE work.cycloneiii_mac_data_reg;
USE work.cycloneiii_mac_sign_reg;
USE work.cycloneiii_mac_mult_internal;
ENTITY cycloneiii_mac_mult IS
GENERIC (
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : STRING := "*";
dataa_width : integer := 18;
datab_width : integer := 18;
dataa_clock : string := "none";
datab_clock : string := "none";
signa_clock : string := "none";
signb_clock : string := "none";
lpm_hint : string := "true";
lpm_type : string := "cycloneiii_mac_mult"
);
PORT (
dataa : IN std_logic_vector(dataa_width-1 DOWNTO 0) := (OTHERS => '0');
datab : IN std_logic_vector(datab_width-1 DOWNTO 0) := (OTHERS => '0');
signa : IN std_logic := '1';
signb : IN std_logic := '1';
clk : IN std_logic := '0';
aclr : IN std_logic := '0';
ena : IN std_logic := '0';
dataout : OUT std_logic_vector((dataa_width+datab_width)-1 DOWNTO 0);
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1'
);
END cycloneiii_mac_mult;
ARCHITECTURE vital_cycloneiii_mac_mult OF cycloneiii_mac_mult IS
COMPONENT cycloneiii_mac_data_reg
GENERIC (
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : STRING := "*";
tipd_data : VitalDelayArrayType01(17 downto 0) := (OTHERS => DefPropDelay01);
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
tipd_aclr : VitalDelayType01 := DefPropDelay01;
tsetup_data_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_data_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_aclr_dataout_posedge : VitalDelayType01 := DefPropDelay01;
tpd_clk_dataout_posedge : VitalDelayType01 := DefPropDelay01;
data_width : integer := 18
);
PORT (
-- INPUT PORTS
clk : IN std_logic;
data : IN std_logic_vector(17 DOWNTO 0);
ena : IN std_logic;
aclr : IN std_logic;
-- OUTPUT PORTS
dataout : OUT std_logic_vector(17 DOWNTO 0)
);
END COMPONENT;
COMPONENT cycloneiii_mac_sign_reg
GENERIC (
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : STRING := "*";
tsetup_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_clk_q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_aclr_q_posedge : VitalDelayType01 := DefPropDelay01;
tipd_d : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
tipd_aclr : VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefPropDelay01
);
PORT (
-- INPUT PORTS
clk : IN std_logic;
d : IN std_logic;
ena : IN std_logic;
aclr : IN std_logic;
-- OUTPUT PORTS
q : OUT std_logic
);
END COMPONENT;
COMPONENT cycloneiii_mac_mult_internal
GENERIC (
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : STRING := "*";
tipd_dataa : VitalDelayArrayType01(17 downto 0)
:= (OTHERS => DefPropDelay01);
tipd_datab : VitalDelayArrayType01(17 downto 0)
:= (OTHERS => DefPropDelay01);
tipd_signa : VitalDelayType01 := DefPropDelay01;
tipd_signb : VitalDelayType01 := DefPropDelay01;
tpd_dataa_dataout : VitalDelayType01 := DefPropDelay01;
tpd_datab_dataout : VitalDelayType01 := DefPropDelay01;
tpd_signa_dataout : VitalDelayType01 := DefPropDelay01;
tpd_signb_dataout : VitalDelayType01 := DefPropDelay01;
dataa_width : integer := 18;
datab_width : integer := 18
);
PORT (
dataa : IN std_logic_vector(17 DOWNTO 0) := (OTHERS => '0');
datab : IN std_logic_vector(17 DOWNTO 0) := (OTHERS => '0');
signa : IN std_logic := '1';
signb : IN std_logic := '1';
dataout : OUT std_logic_vector((dataa_width+datab_width)-1 DOWNTO 0)
);
END COMPONENT;
-- Internal variables
SIGNAL dataa_ipd : std_logic_vector(17 DOWNTO 0);
SIGNAL datab_ipd : std_logic_vector(17 DOWNTO 0);
SIGNAL idataa_reg : std_logic_vector(17 DOWNTO 0); -- optional register for dataa input
SIGNAL idatab_reg : std_logic_vector(17 DOWNTO 0); -- optional register for datab input
SIGNAL isigna_reg : std_logic; -- optional register for signa input
SIGNAL isignb_reg : std_logic; -- optional register for signb input
SIGNAL idataa_int : std_logic_vector(17 DOWNTO 0); -- dataa as seen by the multiplier input
SIGNAL idatab_int : std_logic_vector(17 DOWNTO 0); -- datab as seen by the multiplier input
SIGNAL isigna_int : std_logic; -- signa as seen by the multiplier input
SIGNAL isignb_int : std_logic; -- signb as seen by the multiplier input
-- padding with 1's for input negation
SIGNAL reg_aclr : std_logic;
SIGNAL dataout_tmp : STD_LOGIC_VECTOR (dataa_width + datab_width downto 0) := (others => '0');
BEGIN
---------------------
-- INPUT PATH DELAYs
---------------------
reg_aclr <= (NOT devpor) OR (NOT devclrn) OR (aclr) ;
-- padding input data to full bus width
dataa_ipd(dataa_width-1 downto 0) <= dataa;
datab_ipd(datab_width-1 downto 0) <= datab;
-- Optional input registers for dataa,b and signa,b
dataa_reg : cycloneiii_mac_data_reg
GENERIC MAP (
data_width => dataa_width)
PORT MAP (
clk => clk,
data => dataa_ipd,
ena => ena,
aclr => reg_aclr,
dataout => idataa_reg);
datab_reg : cycloneiii_mac_data_reg
GENERIC MAP (
data_width => datab_width)
PORT MAP (
clk => clk,
data => datab_ipd,
ena => ena,
aclr => reg_aclr,
dataout => idatab_reg);
signa_reg : cycloneiii_mac_sign_reg
PORT MAP (
clk => clk,
d => signa,
ena => ena,
aclr => reg_aclr,
q => isigna_reg);
signb_reg : cycloneiii_mac_sign_reg
PORT MAP (
clk => clk,
d => signb,
ena => ena,
aclr => reg_aclr,
q => isignb_reg);
idataa_int <= dataa_ipd WHEN (dataa_clock = "none") ELSE idataa_reg;
idatab_int <= datab_ipd WHEN (datab_clock = "none") ELSE idatab_reg;
isigna_int <= signa WHEN (signa_clock = "none") ELSE isigna_reg;
isignb_int <= signb WHEN (signb_clock = "none") ELSE isignb_reg;
mac_multiply : cycloneiii_mac_mult_internal
GENERIC MAP (
dataa_width => dataa_width,
datab_width => datab_width
)
PORT MAP (
dataa => idataa_int,
datab => idatab_int,
signa => isigna_int,
signb => isignb_int,
dataout => dataout
);
END vital_cycloneiii_mac_mult;
--------------------------------------------------------------------
--
-- Module Name : cycloneiii_mac_out
--
-- Description : Cyclone II MAC_OUT VHDL simulation model
--
--------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.VITAL_Primitives.all;
USE IEEE.VITAL_Timing.all;
USE IEEE.std_logic_1164.all;
USE work.cycloneiii_atom_pack.all;
ENTITY cycloneiii_mac_out IS
GENERIC (
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : STRING := "*";
tipd_dataa : VitalDelayArrayType01(35 downto 0)
:= (OTHERS => DefPropDelay01);
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
tipd_aclr : VitalDelayType01 := DefPropDelay01;
tpd_dataa_dataout : VitalDelayType01 := DefPropDelay01;
tpd_aclr_dataout_posedge : VitalDelayType01 := DefPropDelay01;
tpd_clk_dataout_posedge : VitalDelayType01 := DefPropDelay01;
tsetup_dataa_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_dataa_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
dataa_width : integer := 1;
output_clock : string := "none";
lpm_hint : string := "true";
lpm_type : string := "cycloneiii_mac_out");
PORT (
dataa : IN std_logic_vector(dataa_width-1 DOWNTO 0) := (OTHERS => '0');
clk : IN std_logic := '0';
aclr : IN std_logic := '0';
ena : IN std_logic := '1';
dataout : OUT std_logic_vector(dataa_width-1 DOWNTO 0);
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1'
);
END cycloneiii_mac_out;
ARCHITECTURE vital_cycloneiii_mac_out OF cycloneiii_mac_out IS
-- internal variables
SIGNAL dataa_ipd : std_logic_vector(dataa'range);
SIGNAL clk_ipd : std_logic;
SIGNAL aclr_ipd : std_logic;
SIGNAL ena_ipd : std_logic;
-- optional register
SIGNAL use_reg : std_logic;
SIGNAL dataout_tmp : std_logic_vector(dataout'range) := (OTHERS => '0');
BEGIN
---------------------
-- PATH DELAYs
---------------------
WireDelay : block
begin
g1 : for i in dataa'range generate
VitalWireDelay (dataa_ipd(i), dataa(i), tipd_dataa(i));
VITALtiming : process (clk_ipd, aclr_ipd, dataout_tmp(i))
variable dataout_VitalGlitchData : VitalGlitchDataType;
begin
VitalPathDelay01 (
OutSignal => dataout(i),
OutSignalName => "DATAOUT",
OutTemp => dataout_tmp(i),
Paths => (0 => (clk_ipd'last_event, tpd_clk_dataout_posedge, use_reg = '1'),
1 => (aclr_ipd'last_event, tpd_aclr_dataout_posedge, use_reg = '1'),
2 => (dataa_ipd(i)'last_event, tpd_dataa_dataout, use_reg = '0')),
GlitchData => dataout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
end generate;
VitalWireDelay (clk_ipd, clk, tipd_clk);
VitalWireDelay (aclr_ipd, aclr, tipd_aclr);
VitalWireDelay (ena_ipd, ena, tipd_ena);
end block;
use_reg <= '1' WHEN (output_clock /= "none") ELSE '0';
VITALtiming : process (clk_ipd, aclr_ipd, dataa_ipd)
variable Tviol_dataa_clk : std_ulogic := '0';
variable TimingData_dataa_clk : VitalTimingDataType := VitalTimingDataInit;
variable Tviol_ena_clk : std_ulogic := '0';
variable TimingData_ena_clk : VitalTimingDataType := VitalTimingDataInit;
begin
------------------------
-- Timing Check Section
------------------------
if (TimingChecksOn) then
VitalSetupHoldCheck (
Violation => Tviol_dataa_clk,
TimingData => TimingData_dataa_clk,
TestSignal => dataa,
TestSignalName => "D",
RefSignal => clk_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_dataa_clk_noedge_posedge,
SetupLow => tsetup_dataa_clk_noedge_posedge,
HoldHigh => thold_dataa_clk_noedge_posedge,
HoldLow => thold_dataa_clk_noedge_posedge,
CheckEnabled => TO_X01((aclr) OR (NOT use_reg) OR
(NOT ena)) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/MAC_DATA_REG",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_ena_clk,
TimingData => TimingData_ena_clk,
TestSignal => ena,
TestSignalName => "ENA",
RefSignal => clk_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_ena_clk_noedge_posedge,
SetupLow => tsetup_ena_clk_noedge_posedge,
HoldHigh => thold_ena_clk_noedge_posedge,
HoldLow => thold_ena_clk_noedge_posedge,
CheckEnabled => TO_X01((aclr) OR
(NOT use_reg)) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/MAC_DATA_REG",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
end if;
if (use_reg = '0') then
dataout_tmp <= dataa_ipd;
else
if (aclr_ipd = '1') then
dataout_tmp <= (OTHERS => '0');
elsif (clk_ipd'event and clk_ipd = '1' and (ena_ipd = '1')) then
dataout_tmp <= dataa_ipd;
end if;
end if;
end process;
END vital_cycloneiii_mac_out;
---------------------------------------------------------------------
--
-- Entity Name : cycloneiii_io_ibuf
--
-- Description : Cyclone III IO Ibuf VHDL simulation model
--
--
---------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.cycloneiii_atom_pack.all;
ENTITY cycloneiii_io_ibuf IS
GENERIC (
tipd_i : VitalDelayType01 := DefPropDelay01;
tipd_ibar : VitalDelayType01 := DefPropDelay01;
tpd_i_o : VitalDelayType01 := DefPropDelay01;
tpd_ibar_o : VitalDelayType01 := DefPropDelay01;
XOn : Boolean := DefGlitchXOn;
MsgOn : Boolean := DefGlitchMsgOn;
differential_mode : string := "false";
bus_hold : string := "false";
lpm_type : string := "cycloneiii_io_ibuf"
);
PORT (
i : IN std_logic := '0';
ibar : IN std_logic := '0';
o : OUT std_logic
);
END cycloneiii_io_ibuf;
ARCHITECTURE arch OF cycloneiii_io_ibuf IS
SIGNAL i_ipd : std_logic := '0';
SIGNAL ibar_ipd : std_logic := '0';
SIGNAL o_tmp : std_logic;
SIGNAL out_tmp : std_logic;
SIGNAL prev_value : std_logic := '0';
BEGIN
WireDelay : block
begin
VitalWireDelay (i_ipd, i, tipd_i);
VitalWireDelay (ibar_ipd, ibar, tipd_ibar);
end block;
PROCESS(i_ipd, ibar_ipd)
BEGIN
IF (differential_mode = "false") THEN
IF (i_ipd = '1') THEN
o_tmp <= '1';
prev_value <= '1';
ELSIF (i_ipd = '0') THEN
o_tmp <= '0';
prev_value <= '0';
ELSE
o_tmp <= i_ipd;
END IF;
ELSE
IF (( i_ipd = '0' ) and (ibar_ipd = '1')) then
o_tmp <= '0';
ELSIF (( i_ipd = '1' ) and (ibar_ipd = '0')) then
o_tmp <= '1';
ELSIF((( i_ipd = '1' ) and (ibar_ipd = '1')) or (( i_ipd = '0' ) and (ibar_ipd = '0')))then
o_tmp <= 'X';
ELSE
o_tmp <= 'X';
END IF;
END IF;
END PROCESS;
out_tmp <= prev_value when (bus_hold = "true") else o_tmp;
----------------------
-- Path Delay Section
----------------------
PROCESS( out_tmp)
variable output_VitalGlitchData : VitalGlitchDataType;
BEGIN
VitalPathDelay01 (
OutSignal => o,
OutSignalName => "o",
OutTemp => out_tmp,
Paths => (0 => (i_ipd'last_event, tpd_i_o, TRUE),
1 => (ibar_ipd'last_event, tpd_ibar_o, TRUE)),
GlitchData => output_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn
);
END PROCESS;
END arch;
---------------------------------------------------------------------
--
-- Entity Name : cycloneiii_io_obuf
--
-- Description : Cyclone III IO Obuf VHDL simulation model
--
--
---------------------------------------------------------------------
LIBRARY IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.cycloneiii_atom_pack.all;
ENTITY cycloneiii_io_obuf IS
GENERIC (
tipd_i : VitalDelayType01 := DefPropDelay01;
tipd_oe : VitalDelayType01 := DefPropDelay01;
tpd_i_o : VitalDelayType01 := DefPropDelay01;
tpd_oe_o : VitalDelayType01 := DefPropDelay01;
tpd_i_obar : VitalDelayType01 := DefPropDelay01;
tpd_oe_obar : VitalDelayType01 := DefPropDelay01;
XOn : Boolean := DefGlitchXOn;
MsgOn : Boolean := DefGlitchMsgOn;
open_drain_output : string := "false";
bus_hold : string := "false";
lpm_type : string := "cycloneiii_io_obuf"
);
PORT (
i : IN std_logic := '0';
oe : IN std_logic := '1';
seriesterminationcontrol : IN std_logic_vector(15 DOWNTO 0) := (others => '0');
devoe : IN std_logic := '1';
o : OUT std_logic;
obar : OUT std_logic
);
END cycloneiii_io_obuf;
ARCHITECTURE arch OF cycloneiii_io_obuf IS
--INTERNAL Signals
SIGNAL i_ipd : std_logic := '0';
SIGNAL oe_ipd : std_logic := '0';
SIGNAL out_tmp : std_logic := 'Z';
SIGNAL out_tmp_bar : std_logic;
SIGNAL prev_value : std_logic := '0';
SIGNAL o_tmp : std_logic;
SIGNAL obar_tmp : std_logic;
SIGNAL o_tmp1 : std_logic;
SIGNAL obar_tmp1 : std_logic;
BEGIN
WireDelay : block
begin
VitalWireDelay (i_ipd, i, tipd_i);
VitalWireDelay (oe_ipd, oe, tipd_oe);
end block;
PROCESS( i_ipd, oe_ipd)
BEGIN
IF (oe_ipd = '1') THEN
IF (open_drain_output = "true") THEN
IF (i_ipd = '0') THEN
out_tmp <= '0';
out_tmp_bar <= '1';
prev_value <= '0';
ELSE
out_tmp <= 'Z';
out_tmp_bar <= 'Z';
END IF;
ELSE
IF (i_ipd = '0') THEN
out_tmp <= '0';
out_tmp_bar <= '1';
prev_value <= '0';
ELSE
IF (i_ipd = '1') THEN
out_tmp <= '1';
out_tmp_bar <= '0';
prev_value <= '1';
ELSE
out_tmp <= i_ipd;
out_tmp_bar <= i_ipd;
END IF;
END IF;
END IF;
ELSE
IF (oe_ipd = '0') THEN
out_tmp <= 'Z';
out_tmp_bar <= 'Z';
ELSE
out_tmp <= 'X';
out_tmp_bar <= 'X';
END IF;
END IF;
END PROCESS;
o_tmp1 <= prev_value WHEN (bus_hold = "true") ELSE out_tmp;
obar_tmp1 <= NOT prev_value WHEN (bus_hold = "true") ELSE out_tmp_bar;
o_tmp <= o_tmp1 WHEN (devoe = '1') ELSE 'Z';
obar_tmp <= obar_tmp1 WHEN (devoe = '1') ELSE 'Z';
---------------------
-- Path Delay Section
----------------------
PROCESS( o_tmp,obar_tmp)
variable o_VitalGlitchData : VitalGlitchDataType;
variable obar_VitalGlitchData : VitalGlitchDataType;
BEGIN
VitalPathDelay01 (
OutSignal => o,
OutSignalName => "o",
OutTemp => o_tmp,
Paths => (0 => (i_ipd'last_event, tpd_i_o, TRUE),
1 => (oe_ipd'last_event, tpd_oe_o, TRUE)),
GlitchData => o_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn
);
VitalPathDelay01 (
OutSignal => obar,
OutSignalName => "obar",
OutTemp => obar_tmp,
Paths => (0 => (i_ipd'last_event, tpd_i_obar, TRUE),
1 => (oe_ipd'last_event, tpd_oe_obar, TRUE)),
GlitchData => obar_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn
);
END PROCESS;
END arch;
---------------------------------------------------------------------
--
-- Entity Name : cycloneiii_ddio_oe
--
-- Description : Cyclone III DDIO_OE VHDL simulation model
--
--
---------------------------------------------------------------------
LIBRARY IEEE;
LIBRARY altera;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use altera.altera_primitives_components.all;
use work.cycloneiii_atom_pack.all;
ENTITY cycloneiii_ddio_oe IS
generic(
tipd_oe : VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
tipd_areset : VitalDelayType01 := DefPropDelay01;
tipd_sreset : VitalDelayType01 := DefPropDelay01;
XOn : Boolean := DefGlitchXOn;
MsgOn : Boolean := DefGlitchMsgOn;
power_up : string := "low";
async_mode : string := "none";
sync_mode : string := "none";
lpm_type : string := "cycloneiii_ddio_oe"
);
PORT (
oe : IN std_logic := '1';
clk : IN std_logic := '0';
ena : IN std_logic := '1';
areset : IN std_logic := '0';
sreset : IN std_logic := '0';
dataout : OUT std_logic;
dfflo : OUT std_logic;
dffhi : OUT std_logic;
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1'
);
END cycloneiii_ddio_oe;
ARCHITECTURE arch OF cycloneiii_ddio_oe IS
component cycloneiii_mux21
generic(
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
InstancePath: STRING := "*";
tpd_A_MO : VitalDelayType01 := DefPropDelay01;
tpd_B_MO : VitalDelayType01 := DefPropDelay01;
tpd_S_MO : VitalDelayType01 := DefPropDelay01;
tipd_A : VitalDelayType01 := DefPropDelay01;
tipd_B : VitalDelayType01 := DefPropDelay01;
tipd_S : VitalDelayType01 := DefPropDelay01
);
port (
A : in std_logic := '0';
B : in std_logic := '0';
S : in std_logic := '0';
MO : out std_logic
);
end component;
component dffeas
generic (
power_up : string := "DONT_CARE";
is_wysiwyg : string := "false";
x_on_violation : string := "on";
lpm_type : string := "DFFEAS";
tsetup_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_asdata_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_sclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_asdata_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_sclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_clk_q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_clrn_q_negedge : VitalDelayType01 := DefPropDelay01;
tpd_prn_q_negedge : VitalDelayType01 := DefPropDelay01;
tpd_aload_q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_asdata_q: VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_d : VitalDelayType01 := DefPropDelay01;
tipd_asdata : VitalDelayType01 := DefPropDelay01;
tipd_sclr : VitalDelayType01 := DefPropDelay01;
tipd_sload : VitalDelayType01 := DefPropDelay01;
tipd_clrn : VitalDelayType01 := DefPropDelay01;
tipd_prn : VitalDelayType01 := DefPropDelay01;
tipd_aload : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks;
InstancePath: STRING := "*"
);
port (
d : in std_logic := '0';
clk : in std_logic := '0';
ena : in std_logic := '1';
clrn : in std_logic := '1';
prn : in std_logic := '1';
aload : in std_logic := '0';
asdata : in std_logic := '1';
sclr : in std_logic := '0';
sload : in std_logic := '0';
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
q : out std_logic
);
end component;
--Internal Signals
SIGNAL oe_ipd : std_logic := '0';
SIGNAL clk_ipd : std_logic := '0';
SIGNAL ena_ipd : std_logic := '0';
SIGNAL areset_ipd : std_logic := '0';
SIGNAL sreset_ipd : std_logic := '0';
SIGNAL ddioreg_aclr : std_logic;
SIGNAL ddioreg_prn : std_logic;
SIGNAL ddioreg_adatasdata : std_logic;
SIGNAL ddioreg_sclr : std_logic;
SIGNAL ddioreg_sload : std_logic;
SIGNAL dfflo_tmp : std_logic;
SIGNAL dffhi_tmp : std_logic;
signal nclk : std_logic;
signal dataout_tmp : std_logic;
BEGIN
WireDelay : block
begin
VitalWireDelay (oe_ipd, oe, tipd_oe);
VitalWireDelay (clk_ipd, clk, tipd_clk);
VitalWireDelay (ena_ipd, ena, tipd_ena);
VitalWireDelay (areset_ipd, areset, tipd_areset);
VitalWireDelay (sreset_ipd, sreset, tipd_sreset);
end block;
nclk <= NOT clk_ipd;
PROCESS
BEGIN
WAIT UNTIL areset_ipd'EVENT OR sreset_ipd'EVENT;
IF (async_mode = "clear") THEN
ddioreg_aclr <= NOT areset_ipd;
ddioreg_prn <= '1';
ELSIF (async_mode = "preset") THEN
ddioreg_aclr <= '1';
ddioreg_prn <= NOT areset_ipd;
ELSE
ddioreg_aclr <= '1';
ddioreg_prn <= '1';
END IF;
IF (sync_mode = "clear") THEN
ddioreg_adatasdata <= '0';
ddioreg_sclr <= sreset_ipd;
ddioreg_sload <= '0';
ELSIF (sync_mode = "preset") THEN
ddioreg_adatasdata <= '1';
ddioreg_sclr <= '0';
ddioreg_sload <= sreset_ipd;
ELSE
ddioreg_adatasdata <= '0';
ddioreg_sclr <= '0';
ddioreg_sload <= '0';
END IF;
END PROCESS;
ddioreg_hi : dffeas
GENERIC MAP (
power_up => power_up
)
PORT MAP (
d => oe_ipd,
clk => clk_ipd,
clrn => ddioreg_aclr,
prn => ddioreg_prn,
sclr => ddioreg_sclr,
sload => ddioreg_sload,
asdata => ddioreg_adatasdata,
ena => ena_ipd,
q => dffhi_tmp,
devpor => devpor,
devclrn => devclrn
);
--DDIO Low Register
ddioreg_lo : dffeas
GENERIC MAP (
power_up => power_up
)
PORT MAP (
d => dffhi_tmp,
clk => nclk,
clrn => ddioreg_aclr,
prn => ddioreg_prn,
sclr => ddioreg_sclr,
sload => ddioreg_sload,
asdata => ddioreg_adatasdata,
ena => ena_ipd,
q => dfflo_tmp,
devpor => devpor,
devclrn => devclrn
);
--registered output
or_gate : cycloneiii_mux21
port map (
A => dffhi_tmp,
B => dfflo_tmp,
S => dfflo_tmp,
MO => dataout
);
dfflo <= dfflo_tmp ;
dffhi <= dffhi_tmp ;
END arch;
---------------------------------------------------------------------
--
-- Entity Name : cycloneiii_ddio_out
--
-- Description : Cyclone III DDIO_OUT VHDL simulation model
--
--
---------------------------------------------------------------------
LIBRARY IEEE;
LIBRARY altera;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use altera.altera_primitives_components.all;
use work.cycloneiii_atom_pack.all;
ENTITY cycloneiii_ddio_out IS
generic(
tipd_datainlo : VitalDelayType01 := DefPropDelay01;
tipd_datainhi : VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
tipd_areset : VitalDelayType01 := DefPropDelay01;
tipd_sreset : VitalDelayType01 := DefPropDelay01;
XOn : Boolean := DefGlitchXOn;
MsgOn : Boolean := DefGlitchMsgOn;
power_up : string := "low";
async_mode : string := "none";
sync_mode : string := "none";
lpm_type : string := "cycloneiii_ddio_out"
);
PORT (
datainlo : IN std_logic := '0';
datainhi : IN std_logic := '0';
clk : IN std_logic := '0';
ena : IN std_logic := '1';
areset : IN std_logic := '0';
sreset : IN std_logic := '0';
dataout : OUT std_logic;
dfflo : OUT std_logic;
dffhi : OUT std_logic ;
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1'
);
END cycloneiii_ddio_out;
ARCHITECTURE arch OF cycloneiii_ddio_out IS
component cycloneiii_mux21
generic(
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
InstancePath: STRING := "*";
tpd_A_MO : VitalDelayType01 := DefPropDelay01;
tpd_B_MO : VitalDelayType01 := DefPropDelay01;
tpd_S_MO : VitalDelayType01 := DefPropDelay01;
tipd_A : VitalDelayType01 := DefPropDelay01;
tipd_B : VitalDelayType01 := DefPropDelay01;
tipd_S : VitalDelayType01 := DefPropDelay01
);
port (
A : in std_logic := '0';
B : in std_logic := '0';
S : in std_logic := '0';
MO : out std_logic
);
end component;
component dffeas
generic (
power_up : string := "DONT_CARE";
is_wysiwyg : string := "false";
x_on_violation : string := "on";
lpm_type : string := "DFFEAS";
tsetup_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_asdata_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_sclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_asdata_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_sclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_clk_q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_clrn_q_negedge : VitalDelayType01 := DefPropDelay01;
tpd_prn_q_negedge : VitalDelayType01 := DefPropDelay01;
tpd_aload_q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_asdata_q: VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_d : VitalDelayType01 := DefPropDelay01;
tipd_asdata : VitalDelayType01 := DefPropDelay01;
tipd_sclr : VitalDelayType01 := DefPropDelay01;
tipd_sload : VitalDelayType01 := DefPropDelay01;
tipd_clrn : VitalDelayType01 := DefPropDelay01;
tipd_prn : VitalDelayType01 := DefPropDelay01;
tipd_aload : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks;
InstancePath: STRING := "*"
);
port (
d : in std_logic := '0';
clk : in std_logic := '0';
ena : in std_logic := '1';
clrn : in std_logic := '1';
prn : in std_logic := '1';
aload : in std_logic := '0';
asdata : in std_logic := '1';
sclr : in std_logic := '0';
sload : in std_logic := '0';
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
q : out std_logic
);
end component;
--Internal Signals
SIGNAL datainlo_ipd : std_logic := '0';
SIGNAL datainhi_ipd : std_logic := '0';
SIGNAL clk_ipd : std_logic := '0';
SIGNAL ena_ipd : std_logic := '0';
SIGNAL areset_ipd : std_logic := '0';
SIGNAL sreset_ipd : std_logic := '0';
SIGNAL ddioreg_aclr : std_logic;
SIGNAL ddioreg_prn : std_logic;
SIGNAL ddioreg_adatasdata : std_logic;
SIGNAL ddioreg_sclr : std_logic;
SIGNAL ddioreg_sload : std_logic;
SIGNAL dfflo_tmp : std_logic;
SIGNAL dffhi_tmp : std_logic;
SIGNAL dataout_tmp : std_logic;
Signal mux_sel : std_logic;
Signal mux_lo : std_logic;
Signal sel_mux_lo_in : std_logic;
Signal sel_mux_select : std_logic;
signal clk1 : std_logic;
BEGIN
WireDelay : block
begin
VitalWireDelay (datainlo_ipd, datainlo, tipd_datainlo);
VitalWireDelay (datainhi_ipd, datainhi, tipd_datainhi);
VitalWireDelay (clk_ipd, clk, tipd_clk);
VitalWireDelay (ena_ipd, ena, tipd_ena);
VitalWireDelay (areset_ipd, areset, tipd_areset);
VitalWireDelay (sreset_ipd, sreset, tipd_sreset);
end block;
PROCESS
BEGIN
WAIT UNTIL areset_ipd'EVENT OR sreset_ipd'EVENT;
IF (async_mode = "clear") THEN
ddioreg_aclr <= NOT areset_ipd;
ddioreg_prn <= '1';
ELSIF (async_mode = "preset") THEN
ddioreg_aclr <= '1';
ddioreg_prn <= NOT areset_ipd;
ELSE
ddioreg_aclr <= '1';
ddioreg_prn <= '1';
END IF;
IF (sync_mode = "clear") THEN
ddioreg_adatasdata <= '0';
ddioreg_sclr <= sreset_ipd;
ddioreg_sload <= '0';
ELSIF (sync_mode = "preset") THEN
ddioreg_adatasdata <= '1';
ddioreg_sclr <= '0';
ddioreg_sload <= sreset_ipd;
ELSE
ddioreg_adatasdata <= '0';
ddioreg_sclr <= '0';
ddioreg_sload <= '0';
END IF;
END PROCESS;
process(clk_ipd)
begin
clk1 <= clk_ipd;
end process;
--DDIO OE Register
ddioreg_hi : dffeas
GENERIC MAP (
power_up => power_up
)
PORT MAP (
d => datainhi,
clk => clk_ipd,
clrn => ddioreg_aclr,
prn => ddioreg_prn,
sclr => ddioreg_sclr,
sload => ddioreg_sload,
asdata => ddioreg_adatasdata,
ena => ena_ipd,
q => dffhi_tmp,
devpor => devpor,
devclrn => devclrn
);
--DDIO Low Register
ddioreg_lo : dffeas
GENERIC MAP (
power_up => power_up
)
PORT MAP (
d => datainlo,
clk => clk_ipd,
clrn => ddioreg_aclr,
prn => ddioreg_prn,
sclr => ddioreg_sclr,
sload => ddioreg_sload,
asdata => ddioreg_adatasdata,
ena => ena_ipd,
q => dfflo_tmp,
devpor => devpor,
devclrn => devclrn
);
mux_sel <= clk1;
mux_lo <= dfflo_tmp;
sel_mux_lo_in <= dfflo_tmp;
sel_mux_select <= mux_sel;
sel_mux : cycloneiii_mux21
port map (
A => sel_mux_lo_in,
B => dffhi_tmp,
S => sel_mux_select,
MO => dataout
);
dfflo <= dfflo_tmp;
dffhi <= dffhi_tmp;
END arch;
----------------------------------------------------------------------------
-- Module Name : cycloneiii_io_pad
-- Description : Simulation model for cycloneiii IO pad
----------------------------------------------------------------------------
LIBRARY IEEE;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
use IEEE.std_logic_arith.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
ENTITY cycloneiii_io_pad IS
GENERIC (
lpm_type : string := "cycloneiii_io_pad");
PORT (
--INPUT PORTS
padin : IN std_logic := '0'; -- Input Pad
--OUTPUT PORTS
padout : OUT std_logic); -- Output Pad
END cycloneiii_io_pad;
ARCHITECTURE arch OF cycloneiii_io_pad IS
BEGIN
padout <= padin;
END arch;
--/////////////////////////////////////////////////////////////////////////////
--
-- Entity Name : cycloneiii_ena_reg
--
-- Description : Simulation model for a simple DFF.
-- This is used for the gated clock generation
-- Powers upto 1.
--
--/////////////////////////////////////////////////////////////////////////////
LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.cycloneiii_atom_pack.all;
ENTITY cycloneiii_ena_reg is
generic (
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : STRING := "*";
tsetup_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_clk_q_posedge : VitalDelayType01 := DefPropDelay01;
tipd_d : VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefPropDelay01
);
PORT (
clk : in std_logic;
ena : in std_logic := '1';
d : in std_logic;
clrn : in std_logic := '1';
prn : in std_logic := '1';
q : out std_logic
);
attribute VITAL_LEVEL0 of cycloneiii_ena_reg : entity is TRUE;
end cycloneiii_ena_reg;
ARCHITECTURE behave of cycloneiii_ena_reg is
attribute VITAL_LEVEL0 of behave : architecture is TRUE;
signal d_ipd : std_logic;
signal clk_ipd : std_logic;
begin
---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
VitalWireDelay (d_ipd, d, tipd_d);
VitalWireDelay (clk_ipd, clk, tipd_clk);
end block;
VITALtiming : process (clk_ipd, prn, clrn)
variable Tviol_d_clk : std_ulogic := '0';
variable TimingData_d_clk : VitalTimingDataType := VitalTimingDataInit;
variable q_VitalGlitchData : VitalGlitchDataType;
variable q_reg : std_logic := '1';
begin
------------------------
-- Timing Check Section
------------------------
if (TimingChecksOn) then
VitalSetupHoldCheck (
Violation => Tviol_d_clk,
TimingData => TimingData_d_clk,
TestSignal => d,
TestSignalName => "D",
RefSignal => clk_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_d_clk_noedge_posedge,
SetupLow => tsetup_d_clk_noedge_posedge,
HoldHigh => thold_d_clk_noedge_posedge,
HoldLow => thold_d_clk_noedge_posedge,
CheckEnabled => TO_X01((clrn) OR
(NOT ena)) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/cycloneiii_ena_reg",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
end if;
if (prn = '0') then
q_reg := '1';
elsif (clrn = '0') then
q_reg := '0';
elsif (clk_ipd'event and clk_ipd = '1' and (ena = '1')) then
q_reg := d_ipd;
end if;
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
OutSignal => q,
OutSignalName => "Q",
OutTemp => q_reg,
Paths => (0 => (clk_ipd'last_event, tpd_clk_q_posedge, TRUE)),
GlitchData => q_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
end behave;
--/////////////////////////////////////////////////////////////////////////////
--
-- VHDL Simulation Model for Cyclone III CLKCTRL Atom
--
--/////////////////////////////////////////////////////////////////////////////
--
--
-- CYCLONEII_CLKCTRL Model
--
--
LIBRARY IEEE;
use IEEE.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.cycloneiii_atom_pack.all;
use work.cycloneiii_ena_reg;
entity cycloneiii_clkctrl is
generic (
clock_type : STRING := "Auto";
lpm_type : STRING := "cycloneiii_clkctrl";
ena_register_mode : STRING := "Falling Edge";
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : STRING := "*";
tipd_inclk : VitalDelayArrayType01(3 downto 0) := (OTHERS => DefPropDelay01);
tipd_clkselect : VitalDelayArrayType01(1 downto 0) := (OTHERS => DefPropDelay01);
tipd_ena : VitalDelayType01 := DefPropDelay01
);
port (
inclk : in std_logic_vector(3 downto 0) := "0000";
clkselect : in std_logic_vector(1 downto 0) := "00";
ena : in std_logic := '1';
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
outclk : out std_logic
);
attribute VITAL_LEVEL0 of cycloneiii_clkctrl : entity is TRUE;
end cycloneiii_clkctrl;
architecture vital_clkctrl of cycloneiii_clkctrl is
attribute VITAL_LEVEL0 of vital_clkctrl : architecture is TRUE;
component cycloneiii_ena_reg
generic (
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : STRING := "*";
tsetup_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_clk_q_posedge : VitalDelayType01 := DefPropDelay01;
tipd_d : VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefPropDelay01
);
PORT (
clk : in std_logic;
ena : in std_logic := '1';
d : in std_logic;
clrn : in std_logic := '1';
prn : in std_logic := '1';
q : out std_logic
);
end component;
signal inclk_ipd : std_logic_vector(3 downto 0);
signal clkselect_ipd : std_logic_vector(1 downto 0);
signal ena_ipd : std_logic;
signal clkmux_out : std_logic;
signal clkmux_out_inv : std_logic;
signal cereg_clr : std_logic;
signal cereg1_out : std_logic;
signal cereg2_out : std_logic;
signal ena_out : std_logic;
signal vcc : std_logic := '1';
begin
---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
VitalWireDelay (ena_ipd, ena, tipd_ena);
VitalWireDelay (inclk_ipd(0), inclk(0), tipd_inclk(0));
VitalWireDelay (inclk_ipd(1), inclk(1), tipd_inclk(1));
VitalWireDelay (inclk_ipd(2), inclk(2), tipd_inclk(2));
VitalWireDelay (inclk_ipd(3), inclk(3), tipd_inclk(3));
VitalWireDelay (clkselect_ipd(0), clkselect(0), tipd_clkselect(0));
VitalWireDelay (clkselect_ipd(1), clkselect(1), tipd_clkselect(1));
end block;
process(inclk_ipd, clkselect_ipd)
variable tmp : std_logic;
begin
if (clkselect_ipd = "11") then
tmp := inclk_ipd(3);
elsif (clkselect_ipd = "10") then
tmp := inclk_ipd(2);
elsif (clkselect_ipd = "01") then
tmp := inclk_ipd(1);
else
tmp := inclk_ipd(0);
end if;
clkmux_out <= tmp;
clkmux_out_inv <= NOT tmp;
end process;
extena0_reg : cycloneiii_ena_reg
port map (
clk => clkmux_out_inv,
ena => vcc,
d => ena_ipd,
clrn => vcc,
prn => devpor,
q => cereg1_out
);
extena1_reg : cycloneiii_ena_reg
port map (
clk => clkmux_out_inv,
ena => vcc,
d => cereg1_out,
clrn => vcc,
prn => devpor,
q => cereg2_out
);
ena_out <= cereg1_out WHEN (ena_register_mode = "falling edge") ELSE
ena_ipd WHEN (ena_register_mode = "none") ELSE cereg2_out;
outclk <= ena_out AND clkmux_out;
end vital_clkctrl;
--
--
-- CYCLONEIII_RUBLOCK Model
--
--
LIBRARY IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use work.cycloneiii_atom_pack.all;
entity cycloneiii_rublock is
generic
(
sim_init_config : string := "factory";
sim_init_watchdog_value : integer := 0;
sim_init_status : integer := 0;
lpm_type : string := "cycloneiii_rublock"
);
port
(
clk : in std_logic;
shiftnld : in std_logic;
captnupdt : in std_logic;
regin : in std_logic;
rsttimer : in std_logic;
rconfig : in std_logic;
regout : out std_logic
);
end cycloneiii_rublock;
architecture architecture_rublock of cycloneiii_rublock is
begin
end architecture_rublock;
--
--
-- CYCLONEIII_APFCONTROLLER Model
--
--
LIBRARY IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use work.cycloneiii_atom_pack.all;
entity cycloneiii_apfcontroller is
generic
(
lpm_type: string := "cycloneiii_apfcontroller"
);
port
(
usermode : out std_logic;
nceout : out std_logic
);
end cycloneiii_apfcontroller;
architecture architecture_apfcontroller of cycloneiii_apfcontroller is
begin
end architecture_apfcontroller;
--------------------------------------------------------------------
--
-- Module Name : cycloneiii_termination
--
-- Description : Cyclone III Termination Atom VHDL simulation model
--
--------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
ENTITY cycloneiii_termination IS
GENERIC (
pullup_control_to_core: string := "false";
power_down : string := "true";
test_mode : string := "false";
left_shift_termination_code : string := "false";
pullup_adder : integer := 0;
pulldown_adder : integer := 0;
clock_divide_by : integer := 32; -- 1, 4, 32
runtime_control : string := "false";
shift_vref_rup : string := "true";
shift_vref_rdn : string := "true";
shifted_vref_control : string := "true";
lpm_type : string := "cycloneiii_termination");
PORT (
rup : IN std_logic := '0';
rdn : IN std_logic := '0';
terminationclock : IN std_logic := '0';
terminationclear : IN std_logic := '0';
devpor : IN std_logic := '1';
devclrn : IN std_logic := '1';
comparatorprobe : OUT std_logic;
terminationcontrolprobe : OUT std_logic;
calibrationdone : OUT std_logic;
terminationcontrol : OUT std_logic_vector(15 DOWNTO 0));
END cycloneiii_termination;
ARCHITECTURE cycloneiii_termination_arch OF cycloneiii_termination IS
SIGNAL rup_compout : std_logic := '0';
SIGNAL rdn_compout : std_logic := '1';
BEGIN
calibrationdone <= '1'; -- power-up calibration status
comparatorprobe <= rup_compout WHEN (pullup_control_to_core = "true") ELSE rdn_compout;
rup_compout <= rup;
rdn_compout <= not rdn;
END cycloneiii_termination_arch;
-------------------------------------------------------------------
--
-- Entity Name : cycloneiii_jtag
--
-- Description : Cyclone III JTAG VHDL Simulation model
--
-------------------------------------------------------------------
LIBRARY IEEE;
use IEEE.std_logic_1164.all;
use work.cycloneiii_atom_pack.all;
entity cycloneiii_jtag is
generic (
lpm_type : string := "cycloneiii_jtag"
);
port (
tms : in std_logic;
tck : in std_logic;
tdi : in std_logic;
tdoutap : in std_logic;
tdouser : in std_logic;
tdo: out std_logic;
tmsutap: out std_logic;
tckutap: out std_logic;
tdiutap: out std_logic;
shiftuser: out std_logic;
clkdruser: out std_logic;
updateuser: out std_logic;
runidleuser: out std_logic;
usr1user: out std_logic
);
end cycloneiii_jtag;
architecture architecture_jtag of cycloneiii_jtag is
begin
end architecture_jtag;
-------------------------------------------------------------------
--
-- Entity Name : cycloneiii_crcblock
--
-- Description : Cyclone III CRCBLOCK VHDL Simulation model
--
-------------------------------------------------------------------
LIBRARY IEEE;
use IEEE.std_logic_1164.all;
use work.cycloneiii_atom_pack.all;
entity cycloneiii_crcblock is
generic (
oscillator_divider : integer := 1;
lpm_type : string := "cycloneiii_crcblock"
);
port (
clk : in std_logic;
shiftnld : in std_logic;
ldsrc : in std_logic;
crcerror : out std_logic;
regout : out std_logic
);
end cycloneiii_crcblock;
architecture architecture_crcblock of cycloneiii_crcblock is
begin
end architecture_crcblock;
--
--
-- CYCLONEIII_OSCILLATOR Model
--
--
LIBRARY IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use work.cycloneiii_atom_pack.all;
entity cycloneiii_oscillator is
generic
(
lpm_type: string := "cycloneiii_oscillator"
);
port
(
oscena : in std_logic;
clkout : out std_logic
);
end cycloneiii_oscillator;
architecture architecture_oscillator of cycloneiii_oscillator is
begin
end architecture_oscillator;
| mit | 3f82170da6fa80357f6c204e673ab07f | 0.4753 | 4.068806 | false | false | false | false |
impedimentToProgress/UCI-BlueChip | AttackFiles/Attacks/privEsc/lib/gaisler/ddr/ddr2sp.in.vhd | 2 | 956 | -- DDR controller
constant CFG_DDR2SP : integer := CONFIG_DDR2SP;
constant CFG_DDR2SP_INIT : integer := CONFIG_DDR2SP_INIT;
constant CFG_DDR2SP_FREQ : integer := CONFIG_DDR2SP_FREQ;
constant CFG_DDR2SP_DATAWIDTH : integer := CONFIG_DDR2SP_DATAWIDTH;
constant CFG_DDR2SP_COL : integer := CONFIG_DDR2SP_COL;
constant CFG_DDR2SP_SIZE : integer := CONFIG_DDR2SP_MBYTE;
constant CFG_DDR2SP_DELAY0 : integer := CONFIG_DDR2SP_DELAY0;
constant CFG_DDR2SP_DELAY1 : integer := CONFIG_DDR2SP_DELAY1;
constant CFG_DDR2SP_DELAY2 : integer := CONFIG_DDR2SP_DELAY2;
constant CFG_DDR2SP_DELAY3 : integer := CONFIG_DDR2SP_DELAY3;
constant CFG_DDR2SP_DELAY4 : integer := CONFIG_DDR2SP_DELAY4;
constant CFG_DDR2SP_DELAY5 : integer := CONFIG_DDR2SP_DELAY5;
constant CFG_DDR2SP_DELAY6 : integer := CONFIG_DDR2SP_DELAY6;
constant CFG_DDR2SP_DELAY7 : integer := CONFIG_DDR2SP_DELAY7;
| mit | 2c85f98da80981c76e1585cb47de77ec | 0.692469 | 3.064103 | false | true | false | false |
cafe-alpha/wascafe | v10/fpga_firmware/wasca/synthesis/submodules/sega_saturn_abus_slave.vhd | 2 | 25,640 | -- sega_saturn_abus_slave.vhd
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity sega_saturn_abus_slave is
port (
clock : in std_logic := '0'; -- clock.clk
abus_address : in std_logic_vector(9 downto 0) := (others => '0'); -- abus.address
abus_addressdata : inout std_logic_vector(15 downto 0) := (others => '0'); -- abus.addressdata
abus_chipselect : in std_logic_vector(2 downto 0) := (others => '0'); -- .chipselect
abus_read : in std_logic := '0'; -- .read
abus_write : in std_logic_vector(1 downto 0) := (others => '0'); -- .write
abus_functioncode : in std_logic_vector(1 downto 0) := (others => '0'); -- .functioncode
abus_timing : in std_logic_vector(2 downto 0) := (others => '0'); -- .timing
abus_waitrequest : out std_logic := '1'; -- .waitrequest
abus_addressstrobe : in std_logic := '0'; -- .addressstrobe
abus_interrupt : out std_logic := '0'; -- .interrupt
abus_direction : out std_logic := '0'; -- .direction
abus_muxing : out std_logic_vector(1 downto 0) := "01"; -- .muxing
abus_disable_out : out std_logic := '0'; -- .disableout
avalon_read : out std_logic; -- avalon_master.read
avalon_write : out std_logic; -- .write
avalon_waitrequest : in std_logic := '0'; -- .waitrequest
avalon_address : out std_logic_vector(27 downto 0); -- .address
avalon_readdata : in std_logic_vector(15 downto 0) := (others => '0'); -- .readdata
avalon_writedata : out std_logic_vector(15 downto 0); -- .writedata
avalon_burstcount : out std_logic; -- .burstcount
avalon_readdatavalid : in std_logic := '0'; -- .readdatavalid
avalon_nios_read : in std_logic := '0'; -- avalon_master.read
avalon_nios_write : in std_logic := '0'; -- .write
avalon_nios_waitrequest : out std_logic := '0'; -- .waitrequest
avalon_nios_address : in std_logic_vector(7 downto 0) := (others => '0'); -- .address
avalon_nios_writedata : in std_logic_vector(15 downto 0) := (others => '0'); -- .writedata
avalon_nios_burstcount : in std_logic; -- .burstcount
avalon_nios_readdata : out std_logic_vector(15 downto 0) := (others => '0'); -- .readdata
avalon_nios_readdatavalid : out std_logic := '0'; -- .readdatavalid
saturn_reset : in std_logic := '0'; -- .saturn_reset
reset : in std_logic := '0' -- reset.reset
);
end entity sega_saturn_abus_slave;
architecture rtl of sega_saturn_abus_slave is
signal abus_address_ms : std_logic_vector(9 downto 0) := (others => '0'); -- abus.address
signal abus_address_buf : std_logic_vector(9 downto 0) := (others => '0'); -- abus.address
signal abus_addressdata_ms : std_logic_vector(15 downto 0) := (others => '0'); -- .data
signal abus_addressdata_buf : std_logic_vector(15 downto 0) := (others => '0'); -- .data
signal abus_chipselect_ms : std_logic_vector(2 downto 0) := (others => '0'); -- .chipselect
signal abus_chipselect_buf : std_logic_vector(2 downto 0) := (others => '0'); -- .chipselect
signal abus_read_ms : std_logic := '0'; -- .read
signal abus_read_buf : std_logic := '0'; -- .read
signal abus_write_ms : std_logic_vector(1 downto 0) := (others => '0'); -- .write
signal abus_write_buf : std_logic_vector(1 downto 0) := (others => '0'); -- .write
signal abus_functioncode_ms : std_logic_vector(1 downto 0) := (others => '0'); -- .functioncode
signal abus_functioncode_buf : std_logic_vector(1 downto 0) := (others => '0'); -- .functioncode
signal abus_timing_ms : std_logic_vector(2 downto 0) := (others => '0'); -- .timing
signal abus_timing_buf : std_logic_vector(2 downto 0) := (others => '0'); -- .timing
signal abus_addressstrobe_ms : std_logic := '0'; -- .addressstrobe
signal abus_addressstrobe_buf : std_logic := '0'; -- .addressstrobe
signal abus_read_buf2 : std_logic := '0'; -- .read
signal abus_read_buf3 : std_logic := '0'; -- .read
signal abus_read_buf4 : std_logic := '0'; -- .read
signal abus_read_buf5 : std_logic := '0'; -- .read
signal abus_read_buf6 : std_logic := '0'; -- .read
signal abus_read_buf7 : std_logic := '0'; -- .read
signal abus_write_buf2 : std_logic_vector(1 downto 0) := (others => '0'); -- .write
signal abus_chipselect_buf2 : std_logic_vector(2 downto 0) := (others => '0'); -- .chipselect
signal abus_read_pulse : std_logic := '0'; -- .read
signal abus_write_pulse : std_logic_vector(1 downto 0) := (others => '0'); -- .write
signal abus_chipselect_pulse : std_logic_vector(2 downto 0) := (others => '0'); -- .chipselect
signal abus_read_pulse_off : std_logic := '0'; -- .read
signal abus_write_pulse_off : std_logic_vector(1 downto 0) := (others => '0'); -- .write
signal abus_chipselect_pulse_off : std_logic_vector(2 downto 0) := (others => '0'); -- .chipselect
signal abus_anypulse : std_logic := '0';
signal abus_anypulse2 : std_logic := '0';
signal abus_anypulse3 : std_logic := '0';
signal abus_anypulse_off : std_logic := '0';
signal abus_cspulse : std_logic := '0';
signal abus_cspulse2 : std_logic := '0';
signal abus_cspulse3 : std_logic := '0';
signal abus_cspulse4 : std_logic := '0';
signal abus_cspulse5 : std_logic := '0';
signal abus_cspulse6 : std_logic := '0';
signal abus_cspulse7 : std_logic := '0';
signal abus_cspulse_off : std_logic := '0';
signal abus_address_latched : std_logic_vector(25 downto 0) := (others => '0'); -- abus.address
signal abus_chipselect_latched : std_logic_vector(1 downto 0) := (others => '1'); -- abus.address
signal abus_direction_internal : std_logic := '0';
signal abus_muxing_internal : std_logic_vector(1 downto 0) := (others => '0'); -- abus.address
signal abus_data_out : std_logic_vector(15 downto 0) := (others => '0');
signal abus_data_in : std_logic_vector(15 downto 0) := (others => '0');
signal abus_waitrequest_read : std_logic := '0';
signal abus_waitrequest_write : std_logic := '0';
signal abus_waitrequest_read2 : std_logic := '0';
signal abus_waitrequest_write2 : std_logic := '0';
--signal abus_waitrequest_read3 : std_logic := '0';
--signal abus_waitrequest_write3 : std_logic := '0';
--signal abus_waitrequest_read4 : std_logic := '0';
--signal abus_waitrequest_write4 : std_logic := '0';
signal abus_waitrequest_read_off : std_logic := '0';
signal abus_waitrequest_write_off : std_logic := '0';
signal REG_PCNTR : std_logic_vector(15 downto 0) := (others => '0');
signal REG_STATUS : std_logic_vector(15 downto 0) := (others => '0');
signal REG_MODE : std_logic_vector(15 downto 0) := (others => '0');
signal REG_HWVER : std_logic_vector(15 downto 0) := X"0002";
signal REG_SWVER : std_logic_vector(15 downto 0) := (others => '0');
TYPE transaction_dir IS (DIR_NONE,DIR_WRITE,DIR_READ);
SIGNAL my_little_transaction_dir : transaction_dir := DIR_NONE;
TYPE wasca_mode_type IS (MODE_INIT,
MODE_POWER_MEMORY_05M, MODE_POWER_MEMORY_1M, MODE_POWER_MEMORY_2M, MODE_POWER_MEMORY_4M,
MODE_RAM_1M, MODE_RAM_4M,
MODE_ROM_KOF95,
MODE_ROM_ULTRAMAN,
MODE_BOOT);
SIGNAL wasca_mode : wasca_mode_type := MODE_INIT;
begin
abus_direction <= abus_direction_internal;
abus_muxing <= not abus_muxing_internal;
--ignoring functioncode, timing and addressstrobe for now
--abus transactions are async, so first we must latch incoming signals
--to get rid of metastability
process (clock)
begin
if rising_edge(clock) then
--1st stage
abus_address_ms <= abus_address;
abus_addressdata_ms <= abus_addressdata;
abus_chipselect_ms <= abus_chipselect; --work only with CS1 for now
abus_read_ms <= abus_read;
abus_write_ms <= abus_write;
abus_functioncode_ms <= abus_functioncode;
abus_timing_ms <= abus_timing;
abus_addressstrobe_ms <= abus_addressstrobe;
--2nd stage
abus_address_buf <= abus_address_ms;
abus_addressdata_buf <= abus_addressdata_ms;
abus_chipselect_buf <= abus_chipselect_ms;
abus_read_buf <= abus_read_ms;
abus_write_buf <= abus_write_ms;
abus_functioncode_buf <= abus_functioncode_ms;
abus_timing_buf <= abus_timing_ms;
abus_addressstrobe_buf <= abus_addressstrobe_ms;
end if;
end process;
--excluding metastability protection is a bad behavior
--but it lloks like we're out of more options to optimize read pipeline
--abus_read_ms <= abus_read;
--abus_read_buf <= abus_read_ms;
--abus read/write latch
process (clock)
begin
if rising_edge(clock) then
abus_write_buf2 <= abus_write_buf;
abus_read_buf2 <= abus_read_buf;
abus_read_buf3 <= abus_read_buf2;
abus_read_buf4 <= abus_read_buf3;
abus_read_buf5 <= abus_read_buf4;
abus_read_buf6 <= abus_read_buf5;
abus_read_buf7 <= abus_read_buf6;
abus_chipselect_buf2 <= abus_chipselect_buf;
abus_anypulse2 <= abus_anypulse;
abus_anypulse3 <= abus_anypulse2;
abus_cspulse2 <= abus_cspulse;
abus_cspulse3 <= abus_cspulse2;
abus_cspulse4 <= abus_cspulse3;
abus_cspulse5 <= abus_cspulse4;
abus_cspulse6 <= abus_cspulse5;
abus_cspulse7 <= abus_cspulse6;
end if;
end process;
--abus write/read pulse is a falling edge since read and write signals are negative polarity
abus_write_pulse <= abus_write_buf2 and not abus_write_buf;
abus_read_pulse <= abus_read_buf2 and not abus_read_buf;
--abus_chipselect_pulse <= abus_chipselect_buf2 and not abus_chipselect_buf;
abus_chipselect_pulse <= abus_chipselect_buf and not abus_chipselect_ms;
abus_write_pulse_off <= abus_write_buf and not abus_write_buf2;
abus_read_pulse_off <= abus_read_buf and not abus_read_buf2;
abus_chipselect_pulse_off <= abus_chipselect_buf and not abus_chipselect_buf2;
abus_anypulse <= abus_write_pulse(0) or abus_write_pulse(1) or abus_read_pulse or
abus_chipselect_pulse(0) or abus_chipselect_pulse(1) or abus_chipselect_pulse(2);
abus_anypulse_off <= abus_write_pulse_off(0) or abus_write_pulse_off(1) or abus_read_pulse_off or
abus_chipselect_pulse_off(0) or abus_chipselect_pulse_off(1) or abus_chipselect_pulse_off(2);
abus_cspulse <= abus_chipselect_pulse(0) or abus_chipselect_pulse(1) or abus_chipselect_pulse(2);
abus_cspulse_off <= abus_chipselect_pulse_off(0) or abus_chipselect_pulse_off(1) or abus_chipselect_pulse_off(2);
--whatever pulse we've got, latch address
--it might be latched twice per transaction, but it's not a problem
--multiplexer was switched to address after previous transaction or after boot,
--so we have address ready to latch
process (clock)
begin
if rising_edge(clock) then
if abus_anypulse = '1' then
--if abus_read_pulse = '1' or abus_write_pulse(0) = '1' or abus_write_pulse(1)='1' then
abus_address_latched <= abus_address & abus_addressdata_buf(0) & abus_addressdata_buf(12) & abus_addressdata_buf(2) & abus_addressdata_buf(1)
& abus_addressdata_buf(9) & abus_addressdata_buf(10) & abus_addressdata_buf(8) & abus_addressdata_buf(3)
& abus_addressdata_buf(13) & abus_addressdata_buf(14) & abus_addressdata_buf(15) & abus_addressdata_buf(4)
& abus_addressdata_buf(5) & abus_addressdata_buf(6) & abus_addressdata_buf(11) & abus_addressdata_buf(7);
end if;
end if;
end process;
--latch transaction direction
process (clock)
begin
if rising_edge(clock) then
if abus_write_pulse(0) = '1' or abus_write_pulse(1) = '1' then
my_little_transaction_dir <= DIR_WRITE;
elsif abus_read_pulse = '1' then
my_little_transaction_dir <= DIR_READ;
elsif abus_anypulse_off = '1' and abus_cspulse_off = '0' then --ending anything but not cs
my_little_transaction_dir <= DIR_NONE;
end if;
end if;
end process;
--latch chipselect number
process (clock)
begin
if rising_edge(clock) then
if abus_chipselect_pulse(0) = '1' then
abus_chipselect_latched <= "00";
elsif abus_chipselect_pulse(1) = '1' then
abus_chipselect_latched <= "01";
elsif abus_chipselect_pulse(2) = '1' then
abus_chipselect_latched <= "10";
elsif abus_cspulse_off = '1' then
abus_chipselect_latched <= "11";
end if;
end if;
end process;
--if valid transaction captured, switch to corresponding multiplex mode
process (clock)
begin
if rising_edge(clock) then
if abus_chipselect_latched = "11" then
--chipselect deasserted
abus_direction_internal <= '0'; --high-z
abus_muxing_internal <= "01"; --address
else
--chipselect asserted
case (my_little_transaction_dir) is
when DIR_NONE =>
abus_direction_internal <= '0'; --high-z
abus_muxing_internal <= "10"; --data
when DIR_READ =>
abus_direction_internal <= '1'; --active
abus_muxing_internal <= "10"; --data
when DIR_WRITE =>
abus_direction_internal <= '0'; --high-z
abus_muxing_internal <= "10"; --data
end case;
end if;
end if;
end process;
abus_disable_out <= '1' when abus_chipselect_latched(1) = '1' else
'0';
--if abus read access is detected, issue avalon read transaction
--wait until readdatavalid, then disable read and abus wait
process (clock)
begin
if rising_edge(clock) then
--if my_little_transaction_dir = DIR_READ and abus_chipselect_latched(1) = '0' and abus_anypulse2 = '1' then
--starting read transaction at either RD pulse or (CS pulse while RD is on)
--but if CS arrives less than 7 clocks after RD, then we ignore this CS
--this will get us 2 additional clocks at read pipeline
if abus_read_pulse = '1' or (abus_cspulse='1' and abus_read_buf = '0' and abus_read_buf7 = '0') then
avalon_read <= '1';
abus_waitrequest_read <= '1';
elsif avalon_readdatavalid = '1' then
avalon_read <= '0';
abus_waitrequest_read <= '0';
if abus_chipselect_latched = "00" then
--CS0 access
if abus_address_latched(24 downto 0) = "1"&X"FF0FFE" then
--wasca specific SD card control register
abus_data_out <= X"CDCD";
elsif abus_address_latched(24 downto 0) = "1"&X"FFFFF0" then
--wasca prepare counter
abus_data_out <= REG_PCNTR;
elsif abus_address_latched(24 downto 0) = "1"&X"FFFFF2" then
--wasca status register
abus_data_out <= REG_STATUS;
elsif abus_address_latched(24 downto 0) = "1"&X"FFFFF4" then
--wasca mode register
abus_data_out <= REG_MODE;
elsif abus_address_latched(24 downto 0) = "1"&X"FFFFF6" then
--wasca hwver register
abus_data_out <= REG_HWVER;
elsif abus_address_latched(24 downto 0) = "1"&X"FFFFF8" then
--wasca swver register
abus_data_out <= REG_SWVER;
elsif abus_address_latched(24 downto 0) = "1"&X"FFFFFA" then
--wasca signature "wa"
abus_data_out <= X"7761";
elsif abus_address_latched(24 downto 0) = "1"&X"FFFFFC" then
--wasca signature "sc"
abus_data_out <= X"7363";
elsif abus_address_latched(24 downto 0) = "1"&X"FFFFFE" then
--wasca signature "a "
abus_data_out <= X"6120";
else
--normal CS0 read access
case wasca_mode is
when MODE_INIT => abus_data_out <= avalon_readdata(7 downto 0) & avalon_readdata (15 downto 8) ;
when MODE_POWER_MEMORY_05M => abus_data_out <= X"FFFF";
when MODE_POWER_MEMORY_1M => abus_data_out <= X"FFFF";
when MODE_POWER_MEMORY_2M => abus_data_out <= X"FFFF";
when MODE_POWER_MEMORY_4M => abus_data_out <= X"FFFF";
when MODE_RAM_1M => abus_data_out <= avalon_readdata(7 downto 0) & avalon_readdata (15 downto 8) ;
when MODE_RAM_4M => abus_data_out <= avalon_readdata(7 downto 0) & avalon_readdata (15 downto 8) ;
when MODE_ROM_KOF95 => abus_data_out <= avalon_readdata(7 downto 0) & avalon_readdata (15 downto 8) ;
when MODE_ROM_ULTRAMAN => abus_data_out <= avalon_readdata(7 downto 0) & avalon_readdata (15 downto 8) ;
when MODE_BOOT => abus_data_out <= avalon_readdata(7 downto 0) & avalon_readdata (15 downto 8) ;
end case;
end if;
elsif abus_chipselect_latched = "01" then
--CS1 access
if ( abus_address_latched(23 downto 0) = X"FFFFFE" or abus_address_latched(23 downto 0) = X"FFFFFC" ) then
--saturn cart id register
case wasca_mode is
when MODE_INIT => abus_data_out <= avalon_readdata(7 downto 0) & avalon_readdata (15 downto 8) ;
when MODE_POWER_MEMORY_05M => abus_data_out <= X"FF21";
when MODE_POWER_MEMORY_1M => abus_data_out <= X"FF22";
when MODE_POWER_MEMORY_2M => abus_data_out <= X"FF23";
when MODE_POWER_MEMORY_4M => abus_data_out <= X"FF24";
when MODE_RAM_1M => abus_data_out <= X"FF5A";
when MODE_RAM_4M => abus_data_out <= X"FF5C";
when MODE_ROM_KOF95 => abus_data_out <= X"FFFF";
when MODE_ROM_ULTRAMAN => abus_data_out <= X"FFFF";
when MODE_BOOT => abus_data_out <= X"FFFF";
end case;
else
--normal CS1 access
case wasca_mode is
when MODE_INIT => abus_data_out <= avalon_readdata(7 downto 0) & avalon_readdata (15 downto 8) ;
when MODE_POWER_MEMORY_05M => abus_data_out <= avalon_readdata(7 downto 0) & avalon_readdata (15 downto 8) ;
when MODE_POWER_MEMORY_1M => abus_data_out <= avalon_readdata(7 downto 0) & avalon_readdata (15 downto 8) ;
when MODE_POWER_MEMORY_2M => abus_data_out <= avalon_readdata(7 downto 0) & avalon_readdata (15 downto 8) ;
when MODE_POWER_MEMORY_4M => abus_data_out <= avalon_readdata(7 downto 0) & avalon_readdata (15 downto 8) ;
when MODE_RAM_1M => abus_data_out <= X"FFFF";
when MODE_RAM_4M => abus_data_out <= X"FFFF";
when MODE_ROM_KOF95 => abus_data_out <= X"FFFF";
when MODE_ROM_ULTRAMAN => abus_data_out <= X"FFFF";
when MODE_BOOT => abus_data_out <= X"FFFF";
end case;
end if;
else
--CS2 access
abus_data_out <= X"EEEE";
end if;
end if;
end if;
end process;
--if abus write access is detected, issue avalon write transaction
--disable abus wait immediately
--TODO: check if avalon_writedata is already valid at this moment
process (clock)
begin
if rising_edge(clock) then
if my_little_transaction_dir = DIR_WRITE and abus_chipselect_latched /= "11" and abus_cspulse7 = '1' then
--pass write to avalon
avalon_write <= '1';
abus_waitrequest_write <= '1';
elsif avalon_waitrequest = '0' then
avalon_write <= '0';
abus_waitrequest_write <= '0';
end if;
end if;
end process;
--wasca mode register write
--reset
process (clock)
begin
if rising_edge(clock) then
--if saturn_reset='0' then wasca_mode <= MODE_INIT;
--els
if my_little_transaction_dir = DIR_WRITE and abus_chipselect_latched = "00" and abus_cspulse7 = '1' and
abus_address_latched(23 downto 0) = X"FFFFF4" then
--wasca mode register
REG_MODE <= abus_data_in;
case (abus_data_in (3 downto 0)) is
when X"1" => wasca_mode <= MODE_POWER_MEMORY_05M;
when X"2" => wasca_mode <= MODE_POWER_MEMORY_1M;
when X"3" => wasca_mode <= MODE_POWER_MEMORY_2M;
when X"4" => wasca_mode <= MODE_POWER_MEMORY_4M;
when others =>
case (abus_data_in (7 downto 4)) is
when X"1" => wasca_mode <= MODE_RAM_1M;
when X"2" => wasca_mode <= MODE_RAM_4M;
when others =>
case (abus_data_in (11 downto 8)) is
when X"1" => wasca_mode <= MODE_ROM_KOF95;
when X"2" => wasca_mode <= MODE_ROM_ULTRAMAN;
when others => null;-- wasca_mode <= MODE_INIT;
end case;
end case;
end case;
end if;
end if;
end process;
abus_data_in <= abus_addressdata_buf;
--working only if direction is 1
abus_addressdata <= (others => 'Z') when abus_direction_internal='0' else
abus_data_out;
process (clock)
begin
if rising_edge(clock) then
abus_waitrequest_read2 <= abus_waitrequest_read;
--abus_waitrequest_read3 <= abus_waitrequest_read2;
--abus_waitrequest_read4 <= abus_waitrequest_read3;
abus_waitrequest_write2 <= abus_waitrequest_write;
--abus_waitrequest_write3 <= abus_waitrequest_write3;
--abus_waitrequest_write4 <= abus_waitrequest_write4;
end if;
end process;
process (clock)
begin
if rising_edge(clock) then
abus_waitrequest_read_off <= '0';
abus_waitrequest_write_off <= '0';
if abus_waitrequest_read = '0' and abus_waitrequest_read2 = '1' then
abus_waitrequest_read_off <= '1';
end if;
if abus_waitrequest_write = '0' and abus_waitrequest_write2 = '1' then
abus_waitrequest_write_off <= '1';
end if;
end if;
end process;
--process (clock)
--begin
-- if rising_edge(clock) then
-- --if abus_read_pulse='1' or abus_write_pulse(0)='1' or abus_write_pulse(1)='1' then
-- --if abus_anypulse = '1' then
-- if abus_chipselect_pulse(0) = '1' or abus_chipselect_pulse(1) = '1' then
-- abus_waitrequest <= '0';
-- elsif abus_waitrequest_read_off='1' or abus_waitrequest_write_off='1' then
-- abus_waitrequest <= '1';
-- end if;
-- end if;
--end process;
--avalon-to-abus mapping
--SDRAM is mapped to both CS0 and CS1
avalon_address <= "010" & abus_address_latched(24 downto 0);
avalon_writedata <= abus_data_in(7 downto 0) & abus_data_in (15 downto 8) ;
avalon_burstcount <= '0';
abus_waitrequest <= not (abus_waitrequest_read or abus_waitrequest_write);
--Nios II read interface
process (clock)
begin
if rising_edge(clock) then
avalon_nios_readdatavalid <= '0';
if avalon_nios_read = '1' then
avalon_nios_readdatavalid <= '1';
case avalon_nios_address is
when X"F0" =>
avalon_nios_readdata <= REG_PCNTR;
when X"F2" =>
avalon_nios_readdata <= REG_STATUS;
when X"F4" =>
avalon_nios_readdata <= REG_MODE;
when X"F6" =>
avalon_nios_readdata <= REG_HWVER;
when X"F8" =>
avalon_nios_readdata <= REG_SWVER;
when X"FA" =>
avalon_nios_readdata <= X"ABCD"; --for debug, remove later
when others =>
avalon_nios_readdata <= REG_HWVER; --to simplify mux
end case;
end if;
end if;
end process;
--Nios II write interface
process (clock)
begin
if rising_edge(clock) then
if avalon_nios_write= '1' then
case avalon_nios_address is
when X"F0" =>
REG_PCNTR <= avalon_nios_writedata;
when X"F2" =>
REG_STATUS <= avalon_nios_writedata;
when X"F4" =>
null;
when X"F6" =>
null;
when X"F8" =>
REG_SWVER <= avalon_nios_writedata;
when others =>
null;
end case;
end if;
end if;
end process;
--Nios system interface is only regs, so always ready to write.
avalon_nios_waitrequest <= '0';
end architecture rtl; -- of sega_saturn_abus_slave
| gpl-2.0 | 8c505ae543aac60224b45255c61ea106 | 0.567551 | 3.366155 | false | false | false | false |
impedimentToProgress/UCI-BlueChip | AttackFiles/Attacks/privEsc/lib/techmap/altera_mf/memory_altera_mf.vhd | 2 | 4,606 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: various
-- File: mem_altera_gen.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: Memory generators for Altera altsynram
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
-- pragma translate_off
library altera_mf;
use altera_mf.altsyncram;
-- pragma translate_on
entity altera_syncram_dp is
generic (
abits : integer := 4; dbits : integer := 32
);
port (
clk1 : in std_ulogic;
address1 : in std_logic_vector((abits -1) downto 0);
datain1 : in std_logic_vector((dbits -1) downto 0);
dataout1 : out std_logic_vector((dbits -1) downto 0);
enable1 : in std_ulogic;
write1 : in std_ulogic;
clk2 : in std_ulogic;
address2 : in std_logic_vector((abits -1) downto 0);
datain2 : in std_logic_vector((dbits -1) downto 0);
dataout2 : out std_logic_vector((dbits -1) downto 0);
enable2 : in std_ulogic;
write2 : in std_ulogic);
end;
architecture behav of altera_syncram_dp is
component altsyncram
generic (
width_a : natural;
width_b : natural := 1;
widthad_a : natural;
widthad_b : natural := 1);
port(
address_a : in std_logic_vector(widthad_a-1 downto 0);
address_b : in std_logic_vector(widthad_b-1 downto 0);
clock0 : in std_logic;
clock1 : in std_logic;
data_a : in std_logic_vector(width_a-1 downto 0);
data_b : in std_logic_vector(width_b-1 downto 0);
q_a : out std_logic_vector(width_a-1 downto 0);
q_b : out std_logic_vector(width_b-1 downto 0);
rden_b : in std_logic;
wren_a : in std_logic;
wren_b : in std_logic
);
end component;
begin
u0 : altsyncram
generic map (
WIDTH_A => dbits, WIDTHAD_A => abits,
WIDTH_B => dbits, WIDTHAD_B => abits)
port map (
address_a => address1, address_b => address2, clock0 => clk1,
clock1 => clk2, data_a => datain1, data_b => datain2,
q_a => dataout1, q_b => dataout2, rden_b => enable2,
wren_a => write1, wren_b => write2);
end;
library ieee;
use ieee.std_logic_1164.all;
library techmap;
entity altera_syncram is
generic ( abits : integer := 9; dbits : integer := 32);
port (
clk : in std_ulogic;
address : in std_logic_vector (abits -1 downto 0);
datain : in std_logic_vector (dbits -1 downto 0);
dataout : out std_logic_vector (dbits -1 downto 0);
enable : in std_ulogic;
write : in std_ulogic
);
end;
architecture behav of altera_syncram is
component altera_syncram_dp
generic ( abits : integer := 10; dbits : integer := 8 );
port (
clk1 : in std_ulogic;
address1 : in std_logic_vector((abits -1) downto 0);
datain1 : in std_logic_vector((dbits -1) downto 0);
dataout1 : out std_logic_vector((dbits -1) downto 0);
enable1 : in std_ulogic;
write1 : in std_ulogic;
clk2 : in std_ulogic;
address2 : in std_logic_vector((abits -1) downto 0);
datain2 : in std_logic_vector((dbits -1) downto 0);
dataout2 : out std_logic_vector((dbits -1) downto 0);
enable2 : in std_ulogic;
write2 : in std_ulogic
);
end component;
signal agnd : std_logic_vector(abits-1 downto 0);
signal dgnd : std_logic_vector(dbits-1 downto 0);
begin
agnd <= (others => '0'); dgnd <= (others => '0');
u0: altera_syncram_dp
generic map (abits, dbits)
port map (
clk1 => clk, address1 => address, datain1 => datain,
dataout1 => dataout, enable1 => enable, write1 => write,
clk2 => clk, address2 => agnd, datain2 => dgnd,
dataout2 => open, enable2 => agnd(0), write2 => agnd(0));
end;
| mit | 609259b94f210796ad554b2cd15bc257 | 0.614199 | 3.429635 | false | false | false | false |
michaelfivez/ascon_hardware_implementation | ascon128128_unrolled4/Kernel/Sbox.vhd | 1 | 3,941 | -------------------------------------------------------------------------------
--! @project Unrolled (factor 4) hardware implementation of Asconv128128
--! @author Michael Fivez
--! @license This project is released under the GNU Public License.
--! The license and distribution terms for this file may be
--! found in the file LICENSE in this distribution or at
--! http://www.gnu.org/licenses/gpl-3.0.txt
--! @note This is an hardware implementation made for my graduation thesis
--! at the KULeuven, in the COSIC department (year 2015-2016)
--! The thesis is titled 'Energy efficient hardware implementations of CAESAR submissions',
--! and can be found on the COSIC website (www.esat.kuleuven.be/cosic/publications)
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity Sbox is
port(
X0In : in std_logic_vector(63 downto 0);
X1In : in std_logic_vector(63 downto 0);
X2In : in std_logic_vector(63 downto 0);
X3In : in std_logic_vector(63 downto 0);
X4In : in std_logic_vector(63 downto 0);
RoundNr : in std_logic_vector(3 downto 0);
X0Out : out std_logic_vector(63 downto 0);
X1Out : out std_logic_vector(63 downto 0);
X2Out : out std_logic_vector(63 downto 0);
X3Out : out std_logic_vector(63 downto 0);
X4Out : out std_logic_vector(63 downto 0));
end entity Sbox;
architecture structural of Sbox is
begin
Sbox: process(X0In,X1In,X2In,X3In,X4In,RoundNr) is
-- Procedure for 5-bit Sbox
procedure doSboxPart (
variable SboxPartIn : in std_logic_vector(4 downto 0);
variable SboxPartOut : out std_logic_vector(4 downto 0)) is
-- Temp variable
variable SboxPartTemp : std_logic_vector(17 downto 0);
begin
-- Sbox Interconnections
SboxPartTemp(0) := SboxPartIn(0) xor SboxPartIn(4);
SboxPartTemp(1) := SboxPartIn(2) xor SboxPartIn(1);
SboxPartTemp(2) := SboxPartIn(4) xor SboxPartIn(3);
SboxPartTemp(3) := not SboxPartTemp(0);
SboxPartTemp(4) := not SboxPartIn(1);
SboxPartTemp(5) := not SboxPartTemp(1);
SboxPartTemp(6) := not SboxPartIn(3);
SboxPartTemp(7) := not SboxPartTemp(2);
SboxPartTemp(8) := SboxPartIn(1) and SboxPartTemp(3);
SboxPartTemp(9) := SboxPartTemp(1) and SboxPartTemp(4);
SboxPartTemp(10) := SboxPartIn(3) and SboxPartTemp(5);
SboxPartTemp(11) := SboxPartTemp(2) and SboxPartTemp(6);
SboxPartTemp(12) := SboxPartTemp(0) and SboxPartTemp(7);
SboxPartTemp(13) := SboxPartTemp(0) xor SboxPartTemp(9);
SboxPartTemp(14) := SboxPartIn(1) xor SboxPartTemp(10);
SboxPartTemp(15) := SboxPartTemp(1) xor SboxPartTemp(11);
SboxPartTemp(16) := SboxPartIn(3) xor SboxPartTemp(12);
SboxPartTemp(17) := SboxPartTemp(2) xor SboxPartTemp(8);
SboxPartOut(0) := SboxPartTemp(13) xor SboxPartTemp(17);
SboxPartOut(1) := SboxPartTemp(13) xor SboxPartTemp(14);
SboxPartOut(2) := not SboxPartTemp(15);
SboxPartOut(3) := SboxPartTemp(15) xor SboxPartTemp(16);
SboxPartOut(4) := SboxPartTemp(17);
end procedure doSboxPart;
variable X2TempIn : std_logic_vector(63 downto 0);
variable TempIn,TempOut : std_logic_vector(4 downto 0);
begin
-- Xor with round constants
X2TempIn(3 downto 0) := X2In(3 downto 0) xor RoundNr;
X2TempIn(7 downto 4) := X2In(7 downto 4) xnor RoundNr;
X2TempIn(63 downto 8) := X2In(63 downto 8);
-- Apply 5-bit Sbox 64 times
for i in X0In'range loop
TempIn(0) := X0In(i);
TempIn(1) := X1In(i);
TempIn(2) := X2TempIn(i);
TempIn(3) := X3In(i);
TempIn(4) := X4In(i);
doSboxPart(TempIn,TempOut);
X0Out(i) <= TempOut(0);
X1Out(i) <= TempOut(1);
X2Out(i) <= TempOut(2);
X3Out(i) <= TempOut(3);
X4Out(i) <= TempOut(4);
end loop;
end process Sbox;
end architecture structural;
| gpl-3.0 | 25b0c086dc93894e9d1f374c2ac7ca92 | 0.640447 | 2.923591 | false | false | false | false |
christakissgeo/Matrix-Vector-Multiplication | VHDL Files/mac.vhd | 1 | 1,416 | --MAC > Multiplier - Adder - Accumulator
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_signed.all;
--------------------------------------------
entity mac is
port (
clock : in std_logic;
ai : in std_logic_vector(7 downto 0);
xi : in std_logic_vector(7 downto 0);
mac_clean : in std_logic;
data_out : out std_logic_vector (18 downto 0)
);
end entity mac;
---------------------------------------------
architecture multiplier_accumulator_implentation of mac is
signal multiplier_result : std_logic_vector(15 downto 0);
signal mult_out : std_logic_vector(18 downto 0);
signal mult_out_reg : std_logic_vector(15 downto 0);
signal reg : std_logic_vector(18 downto 0);
signal adder_result : std_logic_vector(18 downto 0);
begin
multiplier_result <= ai * xi;
adder_result <= reg + mult_out;
data_out <= reg;
process (clock)
begin
if rising_edge(clock) then
mult_out_reg <= multiplier_result;
mult_out <= std_logic_vector(resize(signed(mult_out_reg), 19));
if (mac_clean = '1') then -- Multiplier result is ready
reg <= mult_out;
else
reg <= adder_result;
end if;
end if;
end process;
end architecture multiplier_accumulator_implentation;
| mit | 15c9770bf71b3d17f719d79c1d1db4e3 | 0.560734 | 3.436893 | false | false | false | false |
impedimentToProgress/UCI-BlueChip | AttackFiles/Attacks/privEsc/lib/gleichmann/ahb2hpi/ahb2hpi2.vhd | 2 | 14,706 | -------------------------------------------------------------------------------
-- Title : AHB2HPI bus bridge (bidirectional)
-- Project : LEON3MINI
-------------------------------------------------------------------------------
-- $Id: ahb2hpi.vhd,v 1.23 2005/09/28 14:50:25 tame Mod $
-------------------------------------------------------------------------------
-- Author : Thomas Ameseder
-- Company : Gleichmann Electronics
-- Created : 2005-08-19
-- Standard : VHDL'87
-------------------------------------------------------------------------------
-- Description:
--
-- This module implements an AHB slave that communicates with a
-- Host Peripheral Interface (HPI) device such as the CY7C67300 USB controller.
-- Supports Big Endian and Little Endian.
--
-- This is a modified version of the original AHB2HPI core with a bidirectional
-- data bus to be usable on-chip.
--
-- Restrictions: Do not use a data width other than 16 at the moment.
-------------------------------------------------------------------------------
-- Copyright (c) 2005
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
--use ieee.std_logic_unsigned.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
entity ahb2hpi2 is
generic (
counter_width : integer := 4;
data_width : integer := 16;
address_width : integer := 2;
hindex : integer := 0;
haddr : integer := 0;
hmask : integer := 16#fff#
);
port (
-- AHB port
HCLK : in std_ulogic;
HRESETn : in std_ulogic;
ahbso : out ahb_slv_out_type;
ahbsi : in ahb_slv_in_type;
-- HPI port
ADDR : out std_logic_vector(address_width-1 downto 0);
WDATA : out std_logic_vector(data_width-1 downto 0);
RDATA : in std_logic_vector(data_width-1 downto 0);
nCS : out std_ulogic;
nWR : out std_ulogic;
nRD : out std_ulogic;
INT : in std_ulogic;
drive_bus : out std_ulogic;
-- debug port
dbg_equal : out std_ulogic
);
end ahb2hpi2;
architecture rtl of ahb2hpi2 is
constant CONFIGURATION_VERSION : integer := 0;
constant VERSION : integer := 1;
constant INTERRUPT_NUMBER : integer := 5;
-- register file address is the base address plus the
-- ahb memory space reserved for the device itself
-- its size is 64 bytes as defined with 16#fff# for its
-- mask below
constant REGFILE_ADDRESS : integer := 16#340#;
-- big endian/little endian architecture selection
constant BIG_ENDIAN : boolean := true;
constant hconfig : ahb_config_type := (
0 => ahb_device_reg
(VENDOR_GLEICHMANN, GLEICHMANN_HPI,
CONFIGURATION_VERSION, VERSION, INTERRUPT_NUMBER),
4 => ahb_iobar(haddr, hmask),
5 => ahb_iobar(REGFILE_ADDRESS, 16#fff#),
others => (others => '0'));
type reg_type is
record
hwrite : std_ulogic;
hready : std_ulogic;
hsel : std_ulogic;
addr : std_logic_vector(address_width-1 downto 0);
counter : unsigned(counter_width-1 downto 0);
Din : std_logic_vector(data_width-1 downto 0);
Dout : std_logic_vector(data_width-1 downto 0);
nWR, nRD, nCS : std_ulogic;
INT : std_ulogic;
ctrlreg : std_logic_vector(data_width-1 downto 0);
data_acquisition : std_ulogic;
end record;
-- combinatorial, registered and
-- double-registered signals
signal c, r, rr : reg_type;
-- signals for probing input and output data
signal in_data_probe, out_data_probe : std_logic_vector(data_width-1 downto 0);
signal equality_probe : std_ulogic;
-- signal data_acquisition : std_ulogic;
-- keep registers for debug purposes
attribute syn_preserve : boolean;
attribute syn_preserve of in_data_probe, out_data_probe, equality_probe : signal is true;
begin
comb : process (INT, RDATA, HRESETn, ahbsi, r, rr)
variable v : reg_type;
-- register fields
variable tAtoCSlow : unsigned(1 downto 0); -- address to chip select (CS) low
variable tCStoCTRLlow : unsigned(1 downto 0); -- CS low to control (read/write) low
variable tCTRLlowDvalid : unsigned(1 downto 0); -- control (read) low to data valid
variable tCTRLlow : unsigned(1 downto 0); -- control low to control high
variable tCTRLhighCShigh : unsigned(1 downto 0); -- control high to CS high
variable tCShighREC : unsigned(1 downto 0); -- CS high to next CS recovery
variable tCNT : unsigned(counter_width-1 downto 0); -- timing counter
begin
-- assign values from the register in the beginning
-- lateron, assign new values by looking at the new
-- inputs from the bus
v := r;
-- data_acquisition <= '0';
if HRESETn = '0' then
v.hwrite := '0';
v.hready := '1';
v.hsel := '0';
v.addr := (others => '-');
v.counter := conv_unsigned(0, counter_width);
v.Din := (others => '-');
v.Dout := (others => '-');
v.nWR := '1';
v.nRD := '1';
v.nCS := '1';
v.INT := '0';
-- bit 12 is reserved for the interrupt
v.ctrlreg(15 downto 13) := (others => '0');
v.ctrlreg(11 downto 0) := (others => '0');
-- v.data_acquisition := '0';
end if;
-- assert data_acquisition for not longer than one cycle
v.data_acquisition := '0';
-- bit 12 of control register holds registered interrupt
v.ctrlreg(12) := INT;
v.INT := INT;
-- assign register fields to signals
tAtoCSlow := (unsigned(r.ctrlreg(11 downto 10)));
tCStoCTRLlow := (unsigned(r.ctrlreg(9 downto 8)));
tCTRLlowDvalid := (unsigned(r.ctrlreg(7 downto 6)));
tCTRLlow := (unsigned(r.ctrlreg(5 downto 4)));
tCTRLhighCShigh := (unsigned(r.ctrlreg(3 downto 2)));
tCShighREC := (unsigned(r.ctrlreg(1 downto 0)));
tCNT := conv_unsigned(conv_unsigned(0, counter_width) + tAtoCSlow + tCStoCTRLlow + tCTRLlow + tCTRLhighCShigh + tCShighREC + '1', counter_width);
-- is bus free to use?
if ahbsi.hready = '1' then
-- gets selected when HSEL signal for the right slave
-- is asserted and the transfer type is SEQ or NONSEQ
v.hsel := ahbsi.hsel(hindex) and ahbsi.htrans(1);
else
v.hsel := '0';
end if;
-- a valid cycle starts, so all relevant bus signals
-- are registered and the timer is started
if v.hsel = '1' and v.counter = conv_unsigned(0, counter_width) then
v.hwrite := ahbsi.hwrite and v.hsel;
v.hready := '0';
v.counter := conv_unsigned(tCNT, counter_width);
v.nWR := '1'; --not v.hwrite;
v.nRD := '1'; --v.hwrite;
v.nCS := '1';
if (conv_integer(ahbsi.haddr(19 downto 8)) = REGFILE_ADDRESS) then
if ahbsi.haddr(7 downto 0) = X"00" then
-- disable HPI signals, read/write register data
-- and manage AHB handshake
if v.hwrite = '1' then
-- take data from AHB write data bus but skip interrupt bit
if BIG_ENDIAN then
-- v.ctrlreg := ahbsi.hwdata(31 downto 31-data_width+1);
v.ctrlreg(15 downto 13) := ahbsi.hwdata(31 downto 29);
v.ctrlreg(11 downto 0) := ahbsi.hwdata(27 downto 16);
else
-- v.ctrlreg := ahbsi.hwdata(31-data_width downto 0);
v.ctrlreg(15 downto 13) := ahbsi.hwdata(15 downto 13);
v.ctrlreg(11 downto 0) := ahbsi.hwdata(11 downto 0);
end if;
else
v.Din := v.ctrlreg;
end if;
end if;
-- go to last cycle which signals ahb ready
v.counter := conv_unsigned(0, counter_width); --(tCNT - tAtoCSlow - tCStoCTRLlow - tCTRLlow - tCTRLhighCShigh - tCShighREC);
else
-- the LSB of 16-bit AHB addresses is always zero,
-- so the address is shifted in order to be able
-- to access data with a short* in C
v.addr := ahbsi.haddr(address_width downto 1);
-- v.size := ahbsi.hsize(1 downto 0);
-- fetch input data according to the AMBA specification
-- for big/little endian architectures
-- only relevant for 16-bit accesses
if v.addr(0) = '0' then
if BIG_ENDIAN then
v.Dout := ahbsi.hwdata(31 downto 31-data_width+1);
else
v.Dout := ahbsi.hwdata(31-data_width downto 0);
end if;
else
if BIG_ENDIAN then
v.Dout := ahbsi.hwdata(31-data_width downto 0);
else
v.Dout := ahbsi.hwdata(31 downto 31-data_width+1);
end if;
end if;
end if;
end if;
-- check if counter has just been re-initialized; if so,
-- decrement it until it reaches zero and set control signals
-- accordingly
if v.counter > conv_unsigned(0, counter_width) then
if v.counter = (tCNT - tAtoCSlow) then
v.nCS := '0';
end if;
if v.counter = (tCNT - tAtoCSlow - tCStoCTRLlow) then
v.nWR := not v.hwrite;
v.nRD := v.hwrite;
end if;
if v.counter = (tCNT - tAtoCSlow - tCStoCTRLlow - tCTRLlowDvalid) then
if v.nRD = '0' then
v.Din := RDATA;
v.data_acquisition := '1';
-- in_data_probe <= DATA;
end if;
end if;
if v.counter = (tCNT - tAtoCSlow - tCStoCTRLlow - tCTRLlow) then
v.nWR := '1';
v.nRD := '1';
end if;
if v.counter = (tCNT - tAtoCSlow - tCStoCTRLlow - tCTRLlow - tCTRLhighCShigh) then
v.nCS := '1';
end if;
if v.counter = (tCNT - tAtoCSlow - tCStoCTRLlow - tCTRLlow
- tCTRLhighCShigh - tCShighREC) then
v.hready := '1';
end if;
-- note: since the counter is queried and immediately
-- decremented afterwards, the value in hardware
-- is one lower than given in the if statement
v.counter := v.counter - 1;
else
v.hready := '1';
end if;
-- assign variable to a signal
c <= v;
-- HPI outputs
ADDR <= r.addr;
nCS <= r.nCS;
nWR <= r.nWR;
nRD <= r.nRD;
-- three-state buffer: drive bus during a write cycle
-- and hold data for one more clock cycle, then
-- shut off from the bus
if ((r.nCS = '0' and r.nWR = '0') or (rr.nCS = '0' and r.nWR = '0') or
(r.nCS = '0' and rr.nWR = '0') or (rr.nCS = '0' and rr.nWR = '0')) then
WDATA <= r.Dout;
drive_bus <= '1';
else
WDATA <= (others => '-');
drive_bus <= '0';
end if;
-- output data is assigned to the both the high and the
-- low word of the 32-bit data bus
ahbso.hrdata(31 downto 31-data_width+1) <= r.Din;
ahbso.hrdata(31-data_width downto 0) <= r.Din; --(others => '-');
-- if v.addr(0) = '0' then
-- if BIG_ENDIAN then
-- ahbso.hrdata(31 downto 31-data_width+1) <= r.Din;
-- ahbso.hrdata(31-data_width downto 0) <= (others => '-');
-- else
-- ahbso.hrdata(31 downto 31-data_width+1) <= (others => '-');
-- ahbso.hrdata(31-data_width downto 0) <= r.Din;
-- end if;
-- else
-- if BIG_ENDIAN then
-- ahbso.hrdata(31 downto 31-data_width+1) <= (others => '-');
-- ahbso.hrdata(31-data_width downto 0) <= r.Din;
-- else
-- ahbso.hrdata(31 downto 31-data_width+1) <= r.Din;
-- ahbso.hrdata(31-data_width downto 0) <= (others => '-');
-- end if;
-- end if;
ahbso.hready <= r.hready;
ahbso.hirq <= (INTERRUPT_NUMBER => r.ctrlreg(12), others => '0'); -- propagate registered interrupt
-- ahbso.hirq <= (others => '0');
-- ahbso.hirq(INTERRUPT_NUMBER) <= r.ctrlreg(12);
end process comb;
-- constant AHB outputs
ahbso.hresp <= "00"; -- answer OK by default
ahbso.hsplit <= (others => '0'); -- no SPLIT transactions
ahbso.hcache <= '0'; -- cacheable yes/no
ahbso.hconfig <= hconfig;
ahbso.hindex <= hindex;
reg : process (HCLK)
begin
if rising_edge(HCLK) then
r <= c;
rr <= r;
end if;
end process;
---------------------------------------------------------------------------------------
-- DEBUG SECTION for triggering on read/write inconsistency
-- use a C program that writes data AND reads it immediately afterwards
-- dbg_equal start with being '0' after reset, then goes high during the transaction
-- it should not have a falling edge during the transactions
-- -> trigger on that event
-- note regarding HPI data transactions:
-- the address is written first before writing/reading at address B"10"
-- the data register is at address B"00"
---------------------------------------------------------------------------------------
-- read at the rising edge of the read signal
-- (before the next read data is received)
-- data_acquisition <= '1' when rr.nrd = '1' and r.nrd = '0' else
-- '0';
-- read data to compare to
in_data_probe <= r.din;
check_data : process (HCLK, HRESETn)
begin
if HRESETn = '0' then
out_data_probe <= (others => '0');
equality_probe <= '0';
elsif rising_edge(HCLK) then
-- is data being written to the *data* register?
if r.nwr = '0' and r.ncs = '0' and r.addr = "00" then
out_data_probe <= r.dout;
end if;
if r.data_acquisition = '1' then
if in_data_probe = out_data_probe then
equality_probe <= '1';
else
equality_probe <= '0';
end if;
end if;
end if;
end process;
dbg_equal <= equality_probe;
-- pragma translate_off
bootmsg : report_version
generic map ("ahb2hpi2" & tost(hindex) &
": AHB-to-HPI Bridge, irq " &
tost(INTERRUPT_NUMBER));
-- pragma translate_on
end rtl;
| mit | 2ae3d2e9ecca1fc4cc9e60bdef5f7cee | 0.529988 | 3.834681 | false | false | false | false |
impedimentToProgress/UCI-BlueChip | AttackFiles/Attacks/privEsc/lib/gaisler/uart/dcom.vhd | 2 | 4,871 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: dcom
-- File: dcom.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: DSU Communications module
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
library gaisler;
use gaisler.misc.all;
use gaisler.libdcom.all;
entity dcom is
port (
rst : in std_ulogic;
clk : in std_ulogic;
dmai : out ahb_dma_in_type;
dmao : in ahb_dma_out_type;
uarti : out dcom_uart_in_type;
uarto : in dcom_uart_out_type;
ahbi : in ahb_mst_in_type
);
end;
architecture struct of dcom is
type dcom_state_type is (idle, addr1, read1, read2, write1, write2);
type reg_type is record
addr : std_logic_vector(31 downto 0);
data : std_logic_vector(31 downto 0);
len : std_logic_vector(5 downto 0);
write : std_ulogic;
clen : std_logic_vector(1 downto 0);
state : dcom_state_type;
hresp : std_logic_vector(1 downto 0);
end record;
signal r, rin : reg_type;
begin
comb : process(dmao, rst, uarto, ahbi, r)
variable v : reg_type;
variable enable : std_ulogic;
variable newlen : std_logic_vector(5 downto 0);
variable vuarti : dcom_uart_in_type;
variable vdmai : ahb_dma_in_type;
variable newaddr : std_logic_vector(31 downto 2);
begin
v := r;
vuarti.read := '0'; vuarti.write := '0'; vuarti.data := r.data(31 downto 24);
vdmai.start := '0'; vdmai.burst := '0'; vdmai.size := "10"; vdmai.busy := '0';
vdmai.address := r.addr; vdmai.wdata := r.data;
vdmai.write := r.write; vdmai.irq := '0';
-- save hresp
if dmao.ready = '1' then v.hresp := ahbi.hresp; end if;
-- address incrementer
newlen := r.len - 1;
newaddr := r.addr(31 downto 2) + 1;
case r.state is
when idle => -- idle state
v.clen := "00";
if uarto.dready = '1' then
if uarto.data(7) = '1' then v.state := addr1; end if;
v.write := uarto.data(6); v.len := uarto.data(5 downto 0);
vuarti.read := '1';
end if;
when addr1 => -- receive address
if uarto.dready = '1' then
v.addr := r.addr(23 downto 0) & uarto.data;
vuarti.read := '1'; v.clen := r.clen + 1;
end if;
if (r.clen(1) and not v.clen(1)) = '1' then
if r.write = '1' then v.state := write1; else v.state := read1; end if;
end if;
when read1 => -- read AHB
if dmao.active = '1' then
if dmao.ready = '1' then
v.data := dmao.rdata; v.state := read2;
end if;
else vdmai.start := '1'; end if;
v.clen := "00";
when read2 => -- send read-data on uart
if uarto.thempty = '1' then
v.data := r.data(23 downto 0) & uarto.data;
vuarti.write := '1'; v.clen := r.clen + 1;
if (r.clen(1) and not v.clen(1)) = '1' then
v.addr(31 downto 2) := newaddr; v.len := newlen;
if (v.len(5) and not r.len(5)) = '1' then v.state := idle;
else v.state := read1; end if;
end if;
end if;
when write1 => -- receive write-data
if uarto.dready = '1' then
v.data := r.data(23 downto 0) & uarto.data;
vuarti.read := '1'; v.clen := r.clen + 1;
end if;
if (r.clen(1) and not v.clen(1)) = '1' then v.state := write2; end if;
when write2 => -- write AHB
if dmao.active = '1' then
if dmao.ready = '1' then
v.addr(31 downto 2) := newaddr; v.len := newlen;
if (v.len(5) and not r.len(5)) = '1' then v.state := idle;
else v.state := write1; end if;
end if;
else vdmai.start := '1'; end if;
v.clen := "00";
end case;
if (uarto.lock and rst) = '0' then
v.state := idle; v.write := '0';
end if;
rin <= v; dmai <= vdmai; uarti <= vuarti;
end process;
regs : process(clk)
begin if rising_edge(clk) then r <= rin; end if; end process;
end;
| mit | 2ec537a4781b3e174414bcb22351652b | 0.572572 | 3.234396 | false | false | false | false |
impedimentToProgress/UCI-BlueChip | AttackFiles/Attacks/privEsc/lib/tech/axcelerator/components/axcelerator_small.vhd | 2 | 24,235 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- pragma translate_on
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity RAM64K36 is port(
DEPTH3, DEPTH2, DEPTH1, DEPTH0,
WRAD15, WRAD14, WRAD13, WRAD12, WRAD11, WRAD10, WRAD9 ,
WRAD8 , WRAD7 , WRAD6 , WRAD5 , WRAD4 , WRAD3 , WRAD2 ,
WRAD1 , WRAD0 , WD35 , WD34 , WD33 , WD32 , WD31 ,
WD30 , WD29 , WD28 , WD27 , WD26 , WD25 , WD24 ,
WD23 , WD22 , WD21 , WD20 , WD19 , WD18 , WD17 ,
WD16 , WD15 , WD14 , WD13 , WD12 , WD11 , WD10 ,
WD9 , WD8 , WD7 , WD6 , WD5 , WD4 , WD3 ,
WD2 , WD1 , WD0 , WW2 , WW1 , WW0 , WEN ,
WCLK , RDAD15, RDAD14, RDAD13, RDAD12, RDAD11, RDAD10,
RDAD9 , RDAD8 , RDAD7 , RDAD6 , RDAD5 , RDAD4 , RDAD3 ,
RDAD2 , RDAD1 , RDAD0 , RW2 , RW1 , RW0 , REN ,
RCLK : in std_ulogic ;
RD35 , RD34 , RD33 , RD32 , RD31 , RD30 , RD29 ,
RD28 , RD27 , RD26 , RD25 , RD24 , RD23 , RD22 ,
RD21 , RD20 , RD19 , RD18 , RD17 , RD16 , RD15 ,
RD14 , RD13 , RD12 , RD11 , RD10 , RD9 , RD8 ,
RD7 , RD6 , RD5 , RD4 , RD3 , RD2 , RD1 ,
RD0 : out std_ulogic);
end;
architecture rtl of RAM64K36 is
signal re : std_ulogic;
begin
rp : process(RCLK, WCLK)
constant words : integer := 2**16;
subtype word is std_logic_vector(35 downto 0);
type dregtype is array (0 to words - 1) of word;
variable rfd : dregtype;
variable wa, ra : std_logic_vector(15 downto 0);
variable q : std_logic_vector(35 downto 0);
begin
if rising_edge(RCLK) then
ra := RDAD15 & RDAD14 & RDAD13 & RDAD12 & RDAD11 & RDAD10 & RDAD9 &
RDAD8 & RDAD7 & RDAD6 & RDAD5 & RDAD4 & RDAD3 & RDAD2 & RDAD1 & RDAD0;
if not (is_x (ra)) and REN = '1' then
q := rfd(to_integer(unsigned(ra)) mod words);
else q := (others => 'X'); end if;
end if;
if rising_edge(WCLK) and (wen = '1') then
wa := WRAD15 & WRAD14 & WRAD13 & WRAD12 & WRAD11 & WRAD10 & WRAD9 &
WRAD8 & WRAD7 & WRAD6 & WRAD5 & WRAD4 & WRAD3 & WRAD2 & WRAD1 & WRAD0;
if not is_x (wa) then
rfd(to_integer(unsigned(wa)) mod words) :=
WD35 & WD34 & WD33 & WD32 & WD31 & WD30 & WD29 & WD28 & WD27 &
WD26 & WD25 & WD24 & WD23 & WD22 & WD21 & WD20 & WD19 & WD18 &
WD17 & WD16 & WD15 & WD14 & WD13 & WD12 & WD11 & WD10 & WD9 &
WD8 & WD7 & WD6 & WD5 & WD4 & WD3 & WD2 & WD1 & WD0;
end if;
if ra = wa then q := (others => 'X'); end if; -- no write-through
end if;
RD35 <= q(35); RD34 <= q(34); RD33 <= q(33); RD32 <= q(32); RD31 <= q(31);
RD30 <= q(30); RD29 <= q(29); RD28 <= q(28); RD27 <= q(27); RD26 <= q(26);
RD25 <= q(25); RD24 <= q(24); RD23 <= q(23); RD22 <= q(22); RD21 <= q(21);
RD20 <= q(20); RD19 <= q(19); RD18 <= q(18); RD17 <= q(17); RD16 <= q(16);
RD15 <= q(15); RD14 <= q(14); RD13 <= q(13); RD12 <= q(12); RD11 <= q(11);
RD10 <= q(10); RD9 <= q(9); RD8 <= q(8); RD7 <= q(7); RD6 <= q(6);
RD5 <= q(5); RD4 <= q(4); RD3 <= q(3); RD2 <= q(2); RD1 <= q(1);
RD0 <= q(0);
end process;
end;
-- PCI PADS ----------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity hclkbuf_pci is port( pad : in std_logic; y : out std_logic); end;
architecture struct of hclkbuf_pci is begin y <= to_X01(pad); end;
library ieee;
use ieee.std_logic_1164.all;
entity clkbuf_pci is port( pad : in std_logic; y : out std_logic); end;
architecture struct of clkbuf_pci is begin y <= to_X01(pad); end;
library ieee;
use ieee.std_logic_1164.all;
entity inbuf_pci is port( pad : in std_logic; y : out std_logic); end;
architecture struct of inbuf_pci is begin y <= to_X01(pad) after 2 ns; end;
library ieee;
use ieee.std_logic_1164.all;
entity bibuf_pci is port
(d, e : in std_logic; pad : inout std_logic; y : out std_logic);
end;
architecture struct of bibuf_pci is begin
y <= to_X01(pad) after 2 ns;
pad <= d after 5 ns when to_X01(e) = '1' else
'Z' after 5 ns when to_X01(e) = '0' else 'X' after 5 ns;
end;
library ieee;
use ieee.std_logic_1164.all;
entity tribuff_pci is port (d, e : in std_logic; pad : out std_logic ); end;
architecture struct of tribuff_pci is begin
pad <= d after 5 ns when to_X01(e) = '1' else
'Z' after 5 ns when to_X01(e) = '0' else 'X' after 5 ns;
end;
library ieee;
use ieee.std_logic_1164.all;
entity outbuf_pci is port (d : in std_logic; pad : out std_logic ); end;
architecture struct of outbuf_pci is begin pad <= d after 5 ns; end;
-- STANDARD PADS ----------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity clkbuf is port( pad : in std_logic; y : out std_logic); end;
architecture struct of clkbuf is begin y <= to_X01(pad); end;
library ieee;
use ieee.std_logic_1164.all;
entity hclkbuf is port( pad : in std_logic; y : out std_logic); end;
architecture struct of hclkbuf is begin y <= to_X01(pad); end;
library ieee;
use ieee.std_logic_1164.all;
entity inbuf is port( pad : in std_logic; y : out std_logic); end;
architecture struct of inbuf is begin y <= to_X01(pad) after 1 ns; end;
library ieee;
use ieee.std_logic_1164.all;
entity bibuf is port
(d, e : in std_logic; pad : inout std_logic; y : out std_logic);
end;
architecture struct of bibuf is begin
y <= to_X01(pad) after 2 ns;
pad <= d after 2 ns when to_X01(e) = '1' else
'Z' after 2 ns when to_X01(e) = '0' else 'X' after 2 ns;
end;
library ieee;
use ieee.std_logic_1164.all;
entity tribuff is port (d, e : in std_logic; pad : out std_logic ); end;
architecture struct of tribuff is begin
pad <= d after 2 ns when to_X01(e) = '1' else
'Z' after 2 ns when to_X01(e) = '0' else 'X' after 2 ns;
end;
library ieee;
use ieee.std_logic_1164.all;
entity outbuf is port (d : in std_logic; pad : out std_logic ); end;
architecture struct of outbuf is begin pad <= d after 2 ns; end;
library ieee;
use ieee.std_logic_1164.all;
entity outbuf_f_8 is port (d : in std_logic; pad : out std_logic ); end;
architecture struct of outbuf_f_8 is begin pad <= d after 2 ns; end;
library ieee;
use ieee.std_logic_1164.all;
entity outbuf_f_12 is port (d : in std_logic; pad : out std_logic ); end;
architecture struct of outbuf_f_12 is begin pad <= d after 2 ns; end;
library ieee;
use ieee.std_logic_1164.all;
entity outbuf_f_16 is port (d : in std_logic; pad : out std_logic ); end;
architecture struct of outbuf_f_16 is begin pad <= d after 2 ns; end;
library ieee;
use ieee.std_logic_1164.all;
entity outbuf_f_24 is port (d : in std_logic; pad : out std_logic ); end;
architecture struct of outbuf_f_24 is begin pad <= d after 2 ns; end;
library ieee;
use ieee.std_logic_1164.all;
entity inbuf_lvds is port( y : out std_logic; padp, padn : in std_logic); end;
architecture struct of inbuf_lvds is
signal yn : std_ulogic := '0';
begin
yn <= to_X01(padp) after 1 ns when to_x01(padp xor padn) = '1' else yn after 1 ns;
y <= yn;
end;
library ieee;
use ieee.std_logic_1164.all;
entity outbuf_lvds is port (d : in std_logic; padp, padn : out std_logic ); end;
architecture struct of outbuf_lvds is begin
padp <= d after 1 ns;
padn <= not d after 1 ns;
end;
-- clock buffers ----------------------
library ieee;
use ieee.std_logic_1164.all;
entity hclkint is port( a : in std_logic; y : out std_logic); end;
architecture struct of hclkint is begin y <= to_X01(a); end;
library ieee;
use ieee.std_logic_1164.all;
entity clkint is port( a : in std_logic; y : out std_logic); end;
architecture struct of clkint is begin y <= to_X01(a); end;
library ieee;
use ieee.std_logic_1164.all;
entity add1 is
port(
a : in std_logic;
b : in std_logic;
fci : in std_logic;
s : out std_logic;
fco : out std_logic);
end add1;
architecture beh of add1 is
signal un1_fco : std_logic;
signal un2_fco : std_logic;
signal un3_fco : std_logic;
begin
s <= a xor b xor fci;
un1_fco <= a and b;
un2_fco <= a and fci;
un3_fco <= b and fci;
fco <= un1_fco or un2_fco or un3_fco;
end beh;
library ieee;
use ieee.std_logic_1164.all;
entity and2 is
port(
a : in std_logic;
b : in std_logic;
y : out std_logic);
end and2;
architecture beh of and2 is
begin
y <= b and a;
end beh;
library ieee;
use ieee.std_logic_1164.all;
entity and2a is
port(
a : in std_logic;
b : in std_logic;
y : out std_logic);
end and2a;
architecture beh of and2a is
signal ai : std_logic;
begin
ai <= not a;
y <= b and ai;
end beh;
library ieee;
use ieee.std_logic_1164.all;
entity and2b is
port(
a : in std_logic;
b : in std_logic;
y : out std_logic);
end and2b;
architecture beh of and2b is
signal ai : std_logic;
signal bi : std_logic;
begin
ai <= not a;
bi <= not b;
y <= bi and ai;
end beh;
library ieee;
use ieee.std_logic_1164.all;
entity and3 is
port(
a : in std_logic;
b : in std_logic;
c : in std_logic;
y : out std_logic);
end and3;
architecture beh of and3 is
begin
y <= c and b and a;
end beh;
library ieee;
use ieee.std_logic_1164.all;
entity and3a is
port(
a : in std_logic;
b : in std_logic;
c : in std_logic;
y : out std_logic);
end and3a;
architecture beh of and3a is
signal ai : std_logic;
begin
ai <= not a;
y <= c and b and ai;
end beh;
library ieee;
use ieee.std_logic_1164.all;
entity and3b is
port(
a : in std_logic;
b : in std_logic;
c : in std_logic;
y : out std_logic);
end and3b;
architecture beh of and3b is
signal ai : std_logic;
signal bi : std_logic;
begin
ai <= not a;
bi <= not b;
y <= c and bi and ai;
end beh;
library ieee;
use ieee.std_logic_1164.all;
entity and3c is
port(
a : in std_logic;
b : in std_logic;
c : in std_logic;
y : out std_logic);
end and3c;
architecture beh of and3c is
signal ai : std_logic;
signal bi : std_logic;
signal ci : std_logic;
begin
ai <= not a;
bi <= not b;
ci <= not c;
y <= ci and bi and ai;
end beh;
library ieee;
use ieee.std_logic_1164.all;
entity and4 is
port(
a : in std_logic;
b : in std_logic;
c : in std_logic;
d : in std_logic;
y : out std_logic);
end and4;
architecture beh of and4 is
begin
y <= d and c and b and a;
end beh;
library ieee;
use ieee.std_logic_1164.all;
entity and4a is
port(
a : in std_logic;
b : in std_logic;
c : in std_logic;
d : in std_logic;
y : out std_logic);
end and4a;
architecture beh of and4a is
signal ai : std_logic;
begin
ai <= not a;
y <= d and c and b and ai;
end beh;
library ieee;
use ieee.std_logic_1164.all;
entity and4b is
port(
a : in std_logic;
b : in std_logic;
c : in std_logic;
d : in std_logic;
y : out std_logic);
end and4b;
architecture beh of and4b is
signal ai : std_logic;
signal bi : std_logic;
begin
ai <= not a;
bi <= not b;
y <= d and c and bi and ai;
end beh;
library ieee;
use ieee.std_logic_1164.all;
entity and4c is
port(
a : in std_logic;
b : in std_logic;
c : in std_logic;
d : in std_logic;
y : out std_logic);
end and4c;
architecture beh of and4c is
signal ai : std_logic;
signal bi : std_logic;
signal ci : std_logic;
begin
ai <= not a;
bi <= not b;
ci <= not c;
y <= d and ci and bi and ai;
end beh;
library ieee;
use ieee.std_logic_1164.all;
entity buff is
port(
a : in std_logic;
y : out std_logic);
end buff;
architecture beh of buff is
begin
y <= a;
end beh;
library ieee;
use ieee.std_logic_1164.all;
entity cm8 is
port(
d0 : in std_logic;
d1 : in std_logic;
d2 : in std_logic;
d3 : in std_logic;
s00 : in std_logic;
s01 : in std_logic;
s10 : in std_logic;
s11 : in std_logic;
y : out std_logic);
end cm8;
architecture beh of cm8 is
signal s0 : std_logic;
signal s1 : std_logic;
signal m0 : std_logic;
signal m1 : std_logic;
begin
s0 <= s01 and s00;
s1 <= s11 or s10;
m0 <= d0 when s0 = '0' else d1;
m1 <= d2 when s0 = '0' else d3;
y <= m0 when s1 = '0' else m1;
end beh;
library ieee;
use ieee.std_logic_1164.all;
entity cm8inv is
port(
a : in std_logic;
y : out std_logic);
end cm8inv;
architecture beh of cm8inv is
begin
y <= not a;
end beh;
library ieee;
use ieee.std_logic_1164.all;
entity df1 is
port(
d : in std_logic;
clk : in std_logic;
q : out std_logic);
end df1;
architecture beh of df1 is
begin
ff : process (clk)
begin
if rising_edge(clk) then
q <= d;
end if;
end process ff;
end beh;
library ieee;
use ieee.std_logic_1164.all;
entity dfc1b is
port(
d : in std_logic;
clk : in std_logic;
clr : in std_logic;
q : out std_logic);
end dfc1b;
architecture beh of dfc1b is
begin
ff : process (clk, clr)
begin
if clr = '0' then
q <= '0';
elsif rising_edge(clk) then
q <= d;
end if;
end process ff;
end beh;
library ieee;
use ieee.std_logic_1164.all;
entity dfc1c is
port(
d : in std_logic;
clk : in std_logic;
clr : in std_logic;
q : out std_logic);
end dfc1c;
architecture beh of dfc1c is
begin
ff : process (clk, clr)
begin
if clr = '1' then
q <= '1';
elsif rising_edge(clk) then
q <= not d;
end if;
end process ff;
end beh;
library ieee;
use ieee.std_logic_1164.all;
entity dfc1d is
port(
d : in std_logic;
clk : in std_logic;
clr : in std_logic;
q : out std_logic);
end dfc1d;
architecture beh of dfc1d is
begin
ff : process (clk, clr)
begin
if clr = '0' then
q <= '0';
elsif falling_edge(clk) then
q <= d;
end if;
end process ff;
end beh;
library ieee;
use ieee.std_logic_1164.all;
entity dfe1b is
port(
d : in std_logic;
e : in std_logic;
clk : in std_logic;
q : out std_logic);
end dfe1b;
architecture beh of dfe1b is
signal q_int_1 : std_logic;
signal nq : std_logic;
begin
nq <= d when e = '0' else q_int_1;
q <= q_int_1;
ff : process (clk)
begin
if rising_edge(clk) then
q_int_1 <= nq;
end if;
end process ff;
end beh;
library ieee;
use ieee.std_logic_1164.all;
entity dfe3c is
port(
d : in std_logic;
e : in std_logic;
clk : in std_logic;
clr : in std_logic;
q : out std_logic);
end dfe3c;
architecture beh of dfe3c is
signal q_int_0 : std_logic;
signal md : std_logic;
begin
md <= d when e = '0' else q_int_0;
q <= q_int_0;
ff : process (clk, clr)
begin
if clr = '0' then
q_int_0 <= '0';
elsif rising_edge(clk) then
q_int_0 <= md;
end if;
end process ff;
end beh;
library ieee;
use ieee.std_logic_1164.all;
entity dfe4f is
port(
d : in std_logic;
e : in std_logic;
clk : in std_logic;
pre : in std_logic;
q : out std_logic);
end dfe4f;
architecture beh of dfe4f is
signal q_int_1 : std_logic;
signal un1 : std_logic;
begin
un1 <= d when e = '0' else q_int_1;
q <= q_int_1;
ff : process (clk, pre)
begin
if pre = '0' then
q_int_1 <= '1';
elsif rising_edge(clk) then
q_int_1 <= un1;
end if;
end process ff;
end beh;
library ieee;
use ieee.std_logic_1164.all;
entity dfp1 is
port(
d : in std_logic;
clk : in std_logic;
pre : in std_logic;
q : out std_logic);
end dfp1;
architecture beh of dfp1 is
begin
ff : process (clk, pre)
begin
if pre = '1' then
q <= '1';
elsif rising_edge(clk) then
q <= d;
end if;
end process ff;
end beh;
library ieee;
use ieee.std_logic_1164.all;
entity dfp1b is
port(
d : in std_logic;
clk : in std_logic;
pre : in std_logic;
q : out std_logic);
end dfp1b;
architecture beh of dfp1b is
begin
ff : process (clk, pre)
begin
if pre = '0' then
q <= '1';
elsif rising_edge(clk) then
q <= d;
end if;
end process ff;
end beh;
library ieee;
use ieee.std_logic_1164.all;
entity dfp1d is
port(
d : in std_logic;
clk : in std_logic;
pre : in std_logic;
q : out std_logic);
end dfp1d;
architecture beh of dfp1d is
begin
ff : process (clk, pre)
begin
if pre = '0' then
q <= '1';
elsif falling_edge(clk) then
q <= d;
end if;
end process ff;
end beh;
library ieee;
use ieee.std_logic_1164.all;
entity gnd is
port(
y : out std_logic);
end gnd;
architecture beh of gnd is
begin
y <= '0';
end beh;
library ieee;
use ieee.std_logic_1164.all;
entity dfm is
port(
clk : in std_logic;
s : in std_logic;
a : in std_logic;
b : in std_logic;
q : out std_logic);
end dfm;
architecture beh of dfm is
begin
ff : process (clk)
begin
if rising_edge(clk) then
if s = '0' then q <= a;
else q <= b; end if;
end if;
end process ff;
end beh;
--
--library ieee;
--use ieee.std_logic_1164.all;
--entity hclkbuf is
-- port(
-- pad : in std_logic;
-- y : out std_logic);
--end hclkbuf;
--architecture beh of hclkbuf is
--begin
-- y <= pad;
--end beh;
--
--
--library ieee;
--use ieee.std_logic_1164.all;
--entity inbuf is
-- port(
-- pad : in std_logic;
-- y : out std_logic);
--end inbuf;
--architecture beh of inbuf is
--begin
-- y <= pad;
--end beh;
library ieee;
use ieee.std_logic_1164.all;
entity inv is
port(
a : in std_logic;
y : out std_logic);
end inv;
architecture beh of inv is
begin
y <= not a;
end beh;
library ieee;
use ieee.std_logic_1164.all;
entity nand4 is
port(
a : in std_logic;
b : in std_logic;
c : in std_logic;
d : in std_logic;
y : out std_logic);
end nand4;
architecture beh of nand4 is
signal yx : std_logic;
begin
yx <= d and c and b and a;
y <= not yx;
end beh;
library ieee;
use ieee.std_logic_1164.all;
entity or2 is
port(
a : in std_logic;
b : in std_logic;
y : out std_logic);
end or2;
architecture beh of or2 is
begin
y <= b or a;
end beh;
library ieee;
use ieee.std_logic_1164.all;
entity or2a is
port(
a : in std_logic;
b : in std_logic;
y : out std_logic);
end or2a;
architecture beh of or2a is
signal ai : std_logic;
begin
ai <= not a;
y <= b or ai;
end beh;
library ieee;
use ieee.std_logic_1164.all;
entity or2b is
port(
a : in std_logic;
b : in std_logic;
y : out std_logic);
end or2b;
architecture beh of or2b is
signal ai : std_logic;
signal bi : std_logic;
begin
ai <= not a;
bi <= not b;
y <= bi or ai;
end beh;
library ieee;
use ieee.std_logic_1164.all;
entity or3 is
port(
a : in std_logic;
b : in std_logic;
c : in std_logic;
y : out std_logic);
end or3;
architecture beh of or3 is
begin
y <= c or b or a;
end beh;
library ieee;
use ieee.std_logic_1164.all;
entity or3a is
port(
a : in std_logic;
b : in std_logic;
c : in std_logic;
y : out std_logic);
end or3a;
architecture beh of or3a is
signal ai : std_logic;
begin
ai <= not a;
y <= c or b or ai;
end beh;
library ieee;
use ieee.std_logic_1164.all;
entity or3b is
port(
a : in std_logic;
b : in std_logic;
c : in std_logic;
y : out std_logic);
end or3b;
architecture beh of or3b is
signal ai : std_logic;
signal bi : std_logic;
begin
ai <= not a;
bi <= not b;
y <= c or bi or ai;
end beh;
library ieee;
use ieee.std_logic_1164.all;
entity or3c is
port(
a : in std_logic;
b : in std_logic;
c : in std_logic;
y : out std_logic);
end or3c;
architecture beh of or3c is
signal ai : std_logic;
signal bi : std_logic;
signal ci : std_logic;
begin
ai <= not a;
bi <= not b;
ci <= not c;
y <= ci or bi or ai;
end beh;
library ieee;
use ieee.std_logic_1164.all;
entity or4 is
port(
a : in std_logic;
b : in std_logic;
c : in std_logic;
d : in std_logic;
y : out std_logic);
end or4;
architecture beh of or4 is
begin
y <= d or c or b or a;
end beh;
library ieee;
use ieee.std_logic_1164.all;
entity or4a is
port(
a : in std_logic;
b : in std_logic;
c : in std_logic;
d : in std_logic;
y : out std_logic);
end or4a;
architecture beh of or4a is
signal ai : std_logic;
begin
ai <= not a;
y <= d or c or b or ai;
end beh;
library ieee;
use ieee.std_logic_1164.all;
entity or4b is
port(
a : in std_logic;
b : in std_logic;
c : in std_logic;
d : in std_logic;
y : out std_logic);
end or4b;
architecture beh of or4b is
signal ai : std_logic;
signal bi : std_logic;
begin
ai <= not a;
bi <= not b;
y <= d or c or bi or ai;
end beh;
library ieee;
use ieee.std_logic_1164.all;
entity or4c is
port(
a : in std_logic;
b : in std_logic;
c : in std_logic;
d : in std_logic;
y : out std_logic);
end or4c;
architecture beh of or4c is
signal ai : std_logic;
signal bi : std_logic;
signal ci : std_logic;
begin
ai <= not a;
bi <= not b;
ci <= not c;
y <= d or ci or bi or ai;
end beh;
library ieee;
use ieee.std_logic_1164.all;
entity or4d is
port(
a : in std_logic;
b : in std_logic;
c : in std_logic;
d : in std_logic;
y : out std_logic);
end or4d;
architecture beh of or4d is
signal ai : std_logic;
signal bi : std_logic;
signal ci : std_logic;
signal di : std_logic;
begin
ai <= not a;
bi <= not b;
ci <= not c;
di <= not d;
y <= di or ci or bi or ai;
end beh;
library ieee;
use ieee.std_logic_1164.all;
entity sub1 is
port(
a : in std_logic;
b : in std_logic;
fci : in std_logic;
s : out std_logic;
fco : out std_logic);
end sub1;
architecture beh of sub1 is
signal un1_b : std_logic;
signal un3_fco : std_logic;
signal un1_fco : std_logic;
signal un4_fco : std_logic;
begin
un1_b <= not b;
un3_fco <= a and fci;
s <= a xor fci xor un1_b;
un1_fco <= a and un1_b;
un4_fco <= fci and un1_b;
fco <= un1_fco or un3_fco or un4_fco;
end beh;
library ieee;
use ieee.std_logic_1164.all;
entity vcc is
port(
y : out std_logic);
end vcc;
architecture beh of vcc is
begin
y <= '1';
end beh;
library ieee;
use ieee.std_logic_1164.all;
entity xa1 is
port(
a : in std_logic;
b : in std_logic;
c : in std_logic;
y : out std_logic);
end xa1;
architecture beh of xa1 is
signal xab : std_logic;
begin
xab <= b xor a;
y <= c and xab;
end beh;
library ieee;
use ieee.std_logic_1164.all;
entity xnor2 is
port(
a : in std_logic;
b : in std_logic;
y : out std_logic);
end xnor2;
architecture beh of xnor2 is
signal yi : std_logic;
begin
yi <= b xor a;
y <= not yi;
end beh;
library ieee;
use ieee.std_logic_1164.all;
entity xor2 is
port(
a : in std_logic;
b : in std_logic;
y : out std_logic);
end xor2;
architecture beh of xor2 is
begin
y <= b xor a;
end beh;
library ieee;
use ieee.std_logic_1164.all;
entity xor4 is
port(a,b,c,d : in std_logic;
y : out std_logic);
end xor4;
architecture beh of xor4 is
signal xab, xcd : std_logic;
begin
xab <= b xor a;
xcd <= c xor d;
y <= xab xor xcd;
end beh;
library ieee;
use ieee.std_logic_1164.all;
entity mx2 is
port(
a : in std_logic;
s : in std_logic;
b : in std_logic;
y : out std_logic);
end mx2;
architecture beh of mx2 is
signal xab : std_logic;
begin
y <= b when s = '0' else a;
end beh;
-- pragma translate_on
| mit | 7742c533ee18c0d1fb15a607bc8ef8bd | 0.603425 | 2.768765 | false | false | false | false |
impedimentToProgress/UCI-BlueChip | AttackFiles/Attacks/privEsc/lib/gaisler/spacewire/grspw.vhd | 2 | 15,438 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: grspw
-- File: grspw.vhd
-- Author: Marko Isomaki - Gaisler Research
-- Description: GRLIB wrapper for grspw core
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
library techmap;
use techmap.gencomp.all;
use techmap.netcomp.all;
use grlib.stdlib.all;
use grlib.devices.all;
library gaisler;
use gaisler.spacewire.all;
library spw;
use spw.spwcomp.all;
entity grspw is
generic(
tech : integer range 0 to NTECH := DEFFABTECH;
hindex : integer range 0 to NAHBMST-1 := 0;
pindex : integer range 0 to NAPBSLV-1 := 0;
paddr : integer range 0 to 16#FFF# := 0;
pmask : integer range 0 to 16#FFF# := 16#FFF#;
pirq : integer range 0 to NAHBIRQ-1 := 0;
sysfreq : integer := 10000;
usegen : integer range 0 to 1 := 1;
nsync : integer range 1 to 2 := 1;
rmap : integer range 0 to 1 := 0;
rmapcrc : integer range 0 to 1 := 0;
fifosize1 : integer range 4 to 32 := 32;
fifosize2 : integer range 16 to 64 := 64;
rxclkbuftype : integer range 0 to 2 := 0;
rxunaligned : integer range 0 to 1 := 0;
rmapbufs : integer range 2 to 8 := 4;
ft : integer range 0 to 2 := 0;
scantest : integer range 0 to 1 := 0;
techfifo : integer range 0 to 1 := 1;
netlist : integer range 0 to 1 := 0;
ports : integer range 1 to 2 := 1;
memtech : integer range 0 to NTECH := DEFMEMTECH
);
port(
rst : in std_ulogic;
clk : in std_ulogic;
txclk : in std_ulogic;
ahbmi : in ahb_mst_in_type;
ahbmo : out ahb_mst_out_type;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
swni : in grspw_in_type;
swno : out grspw_out_type
);
end entity;
architecture rtl of grspw is
constant fabits1 : integer := log2(fifosize1);
constant fabits2 : integer := log2(fifosize2);
constant rfifo : integer := 5 + log2(rmapbufs);
constant REVISION : integer := 0;
constant pconfig : apb_config_type := (
0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_SPW, 0, REVISION, pirq),
1 => apb_iobar(paddr, pmask));
constant hconfig : ahb_config_type := (
0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_SPW, 0, REVISION, pirq),
others => zero32);
signal rxclki, nrxclki, rxclko : std_logic_vector(1 downto 0);
--rx ahb fifo
signal rxrenable : std_ulogic;
signal rxraddress : std_logic_vector(4 downto 0);
signal rxwrite : std_ulogic;
signal rxwdata : std_logic_vector(31 downto 0);
signal rxwaddress : std_logic_vector(4 downto 0);
signal rxrdata : std_logic_vector(31 downto 0);
--tx ahb fifo
signal txrenable : std_ulogic;
signal txraddress : std_logic_vector(4 downto 0);
signal txwrite : std_ulogic;
signal txwdata : std_logic_vector(31 downto 0);
signal txwaddress : std_logic_vector(4 downto 0);
signal txrdata : std_logic_vector(31 downto 0);
--nchar fifo
signal ncrenable : std_ulogic;
signal ncraddress : std_logic_vector(5 downto 0);
signal ncwrite : std_ulogic;
signal ncwdata : std_logic_vector(8 downto 0);
signal ncwaddress : std_logic_vector(5 downto 0);
signal ncrdata : std_logic_vector(8 downto 0);
--rmap buf
signal rmrenable : std_ulogic;
signal rmrenablex : std_ulogic;
signal rmraddress : std_logic_vector(7 downto 0);
signal rmwrite : std_ulogic;
signal rmwdata : std_logic_vector(7 downto 0);
signal rmwaddress : std_logic_vector(7 downto 0);
signal rmrdata : std_logic_vector(7 downto 0);
--misc
signal irq : std_ulogic;
signal rxclk, nrxclk : std_logic_vector(ports-1 downto 0);
begin
rtl : if netlist = 0 generate
grspwc0 : grspwc
generic map(
sysfreq => sysfreq,
usegen => usegen,
nsync => nsync,
rmap => rmap,
rmapcrc => rmapcrc,
fifosize1 => fifosize1,
fifosize2 => fifosize2,
rxunaligned => rxunaligned,
rmapbufs => rmapbufs,
scantest => scantest,
ports => ports,
tech => tech)
port map(
rst => rst,
clk => clk,
txclk => txclk,
--ahb mst in
hgrant => ahbmi.hgrant(hindex),
hready => ahbmi.hready,
hresp => ahbmi.hresp,
hrdata => ahbmi.hrdata,
--ahb mst out
hbusreq => ahbmo.hbusreq,
hlock => ahbmo.hlock,
htrans => ahbmo.htrans,
haddr => ahbmo.haddr,
hwrite => ahbmo.hwrite,
hsize => ahbmo.hsize,
hburst => ahbmo.hburst,
hprot => ahbmo.hprot,
hwdata => ahbmo.hwdata,
--apb slv in
psel => apbi.psel(pindex),
penable => apbi.penable,
paddr => apbi.paddr,
pwrite => apbi.pwrite,
pwdata => apbi.pwdata,
--apb slv out
prdata => apbo.prdata,
--spw in
di => swni.d,
si => swni.s,
--spw out
do => swno.d,
so => swno.s,
--time iface
tickin => swni.tickin,
tickout => swno.tickout,
--clk bufs
rxclki => rxclki,
nrxclki => nrxclki,
rxclko => rxclko,
--irq
irq => irq,
--misc
clkdiv10 => swni.clkdiv10,
dcrstval => swni.dcrstval,
timerrstval => swni.timerrstval,
--rmapen
rmapen => swni.rmapen,
--rx ahb fifo
rxrenable => rxrenable,
rxraddress => rxraddress,
rxwrite => rxwrite,
rxwdata => rxwdata,
rxwaddress => rxwaddress,
rxrdata => rxrdata,
--tx ahb fifo
txrenable => txrenable,
txraddress => txraddress,
txwrite => txwrite,
txwdata => txwdata,
txwaddress => txwaddress,
txrdata => txrdata,
--nchar fifo
ncrenable => ncrenable,
ncraddress => ncraddress,
ncwrite => ncwrite,
ncwdata => ncwdata,
ncwaddress => ncwaddress,
ncrdata => ncrdata,
--rmap buf
rmrenable => rmrenable,
rmraddress => rmraddress,
rmwrite => rmwrite,
rmwdata => rmwdata,
rmwaddress => rmwaddress,
rmrdata => rmrdata,
linkdis => swno.linkdis,
testclk => clk,
testrst => ahbmi.testrst,
testen => ahbmi.testen
);
end generate;
struct : if netlist = 1 generate
grspwc0 : grspwc_net
generic map(
tech => tech,
sysfreq => sysfreq,
usegen => usegen,
nsync => nsync,
rmap => rmap,
rmapcrc => rmapcrc,
fifosize1 => fifosize1,
fifosize2 => fifosize2,
rxunaligned => rxunaligned,
rmapbufs => rmapbufs,
scantest => scantest)
port map(
rst => rst,
clk => clk,
txclk => txclk,
--ahb mst in
hgrant => ahbmi.hgrant(hindex),
hready => ahbmi.hready,
hresp => ahbmi.hresp,
hrdata => ahbmi.hrdata,
--ahb mst out
hbusreq => ahbmo.hbusreq,
hlock => ahbmo.hlock,
htrans => ahbmo.htrans,
haddr => ahbmo.haddr,
hwrite => ahbmo.hwrite,
hsize => ahbmo.hsize,
hburst => ahbmo.hburst,
hprot => ahbmo.hprot,
hwdata => ahbmo.hwdata,
--apb slv in
psel => apbi.psel(pindex),
penable => apbi.penable,
paddr => apbi.paddr,
pwrite => apbi.pwrite,
pwdata => apbi.pwdata,
--apb slv out
prdata => apbo.prdata,
--spw in
di => swni.d,
si => swni.s,
--spw out
do => swno.d,
so => swno.s,
--time iface
tickin => swni.tickin,
tickout => swno.tickout,
--clk bufs
rxclki => rxclki,
nrxclki => nrxclki,
rxclko => rxclko,
--irq
irq => irq,
--misc
clkdiv10 => swni.clkdiv10,
dcrstval => swni.dcrstval,
timerrstval => swni.timerrstval,
--rmapen
rmapen => swni.rmapen,
--rx ahb fifo
rxrenable => rxrenable,
rxraddress => rxraddress,
rxwrite => rxwrite,
rxwdata => rxwdata,
rxwaddress => rxwaddress,
rxrdata => rxrdata,
--tx ahb fifo
txrenable => txrenable,
txraddress => txraddress,
txwrite => txwrite,
txwdata => txwdata,
txwaddress => txwaddress,
txrdata => txrdata,
--nchar fifo
ncrenable => ncrenable,
ncraddress => ncraddress,
ncwrite => ncwrite,
ncwdata => ncwdata,
ncwaddress => ncwaddress,
ncrdata => ncrdata,
--rmap buf
rmrenable => rmrenable,
rmraddress => rmraddress,
rmwrite => rmwrite,
rmwdata => rmwdata,
rmwaddress => rmwaddress,
rmrdata => rmrdata,
linkdis => swno.linkdis,
testclk => clk,
testrst => ahbmi.testrst,
testen => ahbmi.testen
);
end generate;
irqdrv : process(irq)
begin
apbo.pirq <= (others => '0');
apbo.pirq(pirq) <= irq;
end process;
ahbmo.hirq <= (others => '0');
ahbmo.hconfig <= hconfig;
ahbmo.hindex <= hindex;
apbo.pconfig <= pconfig;
apbo.pindex <= pindex;
ntst: if scantest = 0 generate
cloop : for i in 0 to ports-1 generate
rx_clkbuf : techbuf generic map(tech => tech, buftype => rxclkbuftype)
port map(i => rxclko(i), o => rxclki(i));
end generate;
rmrenablex <= rmrenable;
end generate;
tst: if scantest = 1 generate
cloop : for i in 0 to ports-1 generate
rxclk(i) <= clk when ahbmi.testen = '1' else rxclko(i);
nrxclk(i) <= clk when ahbmi.testen = '1' else not rxclko(i);
rx_clkbuf : techbuf generic map(tech => tech, buftype => rxclkbuftype)
port map(i => rxclk(i), o => rxclki(i));
nrx_clkbuf : techbuf generic map(tech => tech, buftype => rxclkbuftype)
port map(i => nrxclk(i), o => nrxclki(i));
end generate;
rmrenablex <= rmrenable and not ahbmi.testen;
end generate;
------------------------------------------------------------------------------
-- FIFOS ---------------------------------------------------------------------
------------------------------------------------------------------------------
nft : if ft = 0 generate
--receiver AHB FIFO
rx_ram0 : syncram_2p generic map(memtech*techfifo, fabits1, 32)
port map(clk, rxrenable, rxraddress(fabits1-1 downto 0),
rxrdata, clk, rxwrite,
rxwaddress(fabits1-1 downto 0), rxwdata);
--receiver nchar FIFO
rx_ram1 : syncram_2p generic map(memtech*techfifo, fabits2, 9)
port map(clk, ncrenable, ncraddress(fabits2-1 downto 0),
ncrdata, clk, ncwrite,
ncwaddress(fabits2-1 downto 0), ncwdata);
--transmitter FIFO
tx_ram0 : syncram_2p generic map(memtech*techfifo, fabits1, 32)
port map(clk, txrenable, txraddress(fabits1-1 downto 0),
txrdata, clk, txwrite, txwaddress(fabits1-1 downto 0), txwdata);
--RMAP Buffer
rmap_ram : if (rmap = 1) generate
ram0 : syncram_2p generic map(memtech, rfifo, 8)
port map(clk, rmrenablex, rmraddress(rfifo-1 downto 0),
rmrdata, clk, rmwrite, rmwaddress(rfifo-1 downto 0),
rmwdata);
end generate;
end generate;
ft1 : if ft /= 0 generate
--receiver AHB FIFO
rx_ram0 : syncram_2pft generic map(memtech*techfifo, fabits1, 32, 0, 0, ft*techfifo)
port map(clk, rxrenable, rxraddress(fabits1-1 downto 0),
rxrdata, clk, rxwrite,
rxwaddress(fabits1-1 downto 0), rxwdata);
--receiver nchar FIFO
rx_ram1 : syncram_2pft generic map(memtech*techfifo, fabits2, 9, 0, 0, 2*techfifo)
port map(clk, ncrenable, ncraddress(fabits2-1 downto 0),
ncrdata, clk, ncwrite,
ncwaddress(fabits2-1 downto 0), ncwdata);
--transmitter FIFO
tx_ram0 : syncram_2pft generic map(memtech*techfifo, fabits1, 32, 0, 0, ft*techfifo)
port map(clk, txrenable, txraddress(fabits1-1 downto 0),
txrdata, clk, txwrite, txwaddress(fabits1-1 downto 0), txwdata);
--RMAP Buffer
rmap_ram : if (rmap = 1) generate
ram0 : syncram_2pft generic map(memtech, rfifo, 8, 0, 0, 2)
port map(clk, rmrenablex, rmraddress(rfifo-1 downto 0),
rmrdata, clk, rmwrite, rmwaddress(rfifo-1 downto 0),
rmwdata);
end generate;
end generate;
-- pragma translate_off
msg0 : if (rmap = 0) generate
bootmsg : report_version
generic map ("grspw" & tost(pindex) &
": Spacewire link rev " & tost(REVISION) & ", AHB fifos 2x" &
tost(fifosize1*4) & " bytes, rx fifo " & tost(fifosize2) &
" bytes, irq " & tost(pirq));
end generate;
msg1 : if (rmap = 1) generate
bootmsg : report_version
generic map ("grspw" & tost(pindex) &
": Spacewire link rev " & tost(REVISION) & ", AHB fifos 2x " &
tost(fifosize1*4) & " bytes, rx fifo " & tost(fifosize2) &
" bytes, irq " & tost(pirq) & " , RMAP Buffer " &
tost(rmapbufs*32) & " bytes");
end generate;
pr0 : process is
begin
wait for 100 ns;
if sysfreq < 10000 then
print("WARNING: System frequency too low for GRSPW");
end if;
wait;
end process;
-- pragma translate_on
end architecture;
| mit | d60c9a4bebd968f2819e97178ea33334 | 0.529019 | 4.160065 | false | false | false | false |
michaelfivez/ascon_hardware_implementation | ascon12864_unrolled6/API_plus_CipherCore/fifo.vhd | 9 | 4,405 | -------------------------------------------------------------------------------
--! @file fifo.vhd
--! @brief standard FIFO
--! @project CAESAR Candidate Evaluation
--! @author Ekawat (ice) Homsirikamol
--! @copyright Copyright (c) 2015 Cryptographic Engineering Research Group
--! ECE Department, George Mason University Fairfax, VA, U.S.A.
--! All rights Reserved.
--! @license This project is released under the GNU Public License.
--! The license and distribution terms for this file may be
--! found in the file LICENSE in this distribution or at
--! http://www.gnu.org/licenses/gpl-3.0.txt
--! @note This is publicly available encryption source code that falls
--! under the License Exception TSU (Technology and software-
--! —unrestricted)
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity fifo is
generic (
G_LOG2DEPTH : integer := 9; --! LOG(2) of depth
G_W : integer := 64 --! Width of I/O (bits)
);
port (
clk : in std_logic;
rst : in std_logic;
write : in std_logic;
read : in std_logic;
din : in std_logic_vector(G_W-1 downto 0);
dout : out std_logic_vector(G_W-1 downto 0);
almost_full : out std_logic;
almost_empty : out std_logic;
full : out std_logic;
empty : out std_logic
);
end fifo;
architecture structure of fifo is
signal readpointer : std_logic_vector(G_LOG2DEPTH -1 downto 0);
signal writepointer : std_logic_vector(G_LOG2DEPTH -1 downto 0);
signal bytecounter : std_logic_vector(G_LOG2DEPTH downto 0);
signal write_s : std_logic;
signal full_s : std_logic;
signal empty_s : std_logic;
type mem is array (2**G_LOG2DEPTH-1 downto 0) of std_logic_vector(G_W-1 downto 0);
signal memory : mem;
begin
p_fifo_ram:
process(clk)
begin
if ( rising_edge(clk) ) then
if (write_s = '1') then
memory(to_integer(unsigned(writepointer))) <= din;
end if;
if (read = '1') then
dout <= memory(to_integer(unsigned(readpointer)));
end if;
end if;
end process;
p_fifo_ptr:
process(clk)
begin
if rising_edge( clk ) then
if rst = '1' then
readpointer <= (others => '0');
writepointer <= (others => '0');
bytecounter <= (others => '0'); --differences (write pointer - read pointer)
else
if ( write = '1' and full_s = '0' and read = '0') then
writepointer <= writepointer + 1;
bytecounter <= bytecounter + 1;
elsif ( read = '1' and empty_s = '0' and write = '0') then
readpointer <= readpointer + 1;
bytecounter <= bytecounter - 1;
elsif ( read = '1' and empty_s = '0' and write = '1' and full_s = '0') then
readpointer <= readpointer + 1;
writepointer <= writepointer + 1;
elsif ( read = '1' and empty_s = '0' and write = '1' and full_s = '1') then -- cant write
readpointer <= readpointer + 1;
bytecounter <= bytecounter - 1;
elsif ( read = '1' and empty_s = '1' and write = '1' and full_s = '0') then -- cant read
writepointer <= writepointer + 1;
bytecounter <= bytecounter + 1;
end if;
end if;
end if;
end process;
empty_s <= '1' when (bytecounter = 0) else '0';
full_s <= bytecounter(G_LOG2DEPTH);
almost_full <= '1' when (bytecounter >= 2**G_LOG2DEPTH-1) else '0';
full <= full_s;
empty <= empty_s;
almost_empty <= '1' when (bytecounter = 1) else '0';
write_s <= '1' when ( write = '1' and full_s = '0') else '0';
end structure;
| gpl-3.0 | 700753a86fec4a2bbaa7009a8108e918 | 0.484215 | 3.815425 | false | false | false | false |
franz/pocl | examples/accel/rtl/vhdl/generic_sru.vhd | 2 | 14,732 | -- Copyright (c) 2017 Stephan Nolting / IMS, Leibniz Univ. Hannover
--
-- This file is part of TTA-Based Codesign Environment (TCE).
--
-- Permission is hereby granted, free of charge, to any person obtaining a
-- copy of this software and associated documentation files (the "Software"),
-- to deal in the Software without restriction, including without limitation
-- the rights to use, copy, modify, merge, publish, distribute, sublicense,
-- and/or sell copies of the Software, and to permit persons to whom the
-- Software is furnished to do so, subject to the following conditions:
--
-- The above copyright notice and this permission notice shall be included in
-- all copies or substantial portions of the Software.
--
-- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-- AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
-- FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
-- DEALINGS IN THE SOFTWARE.
--
-------------------------------------------------------------------------------
-- Title : Generic shift and round unit
-------------------------------------------------------------------------------
-- File : generic_sru.vhd
-- Author : Stephan Nolting
-- Company : Leibniz Univ. Hannover
-- Created : 2018-02-06
-- Last update: 2018-06-18
-------------------------------------------------------------------------------
-- Description: Generic shift unit providing logical left shift, logical right
-- shift & arithmetical right shift. Up to 4 pipeline registers can be inserted
-- into the data path. See the according generic's comments for further
-- information. The more pipeline registers are activated, the more the unit's
-- latency is increased.
--
-- If you use this design in your work, please cite the following publication:
-- Payá-Vayá, Guillermo, Roman Burg, and Holger Blume.
-- "Dynamic data-path self-reconfiguration of a VLIW-SIMD soft-processor
-- architecture."
-- Workshop on Self-Awareness in Reconfigurable Computing Systems, SRCS. 2012.
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2018-02-06 1.0 nolting Created
-- 2018-06-18 1.1 tervoa Added MIT License, reformatted header
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library UNISIM;
use UNISIM.vcomponents.all;
entity generic_sru is
generic (
DATA_WIDTH : natural := 32; -- data width (power of 2)
EN_ROUNDING : boolean := false; -- enable hw for rounding to zero/infinity
-- pipeline stages --
EN_INPUT_REG : boolean := false; -- enable input registers
EN_SHIFT_REG : boolean := false; -- enable shifter output register
EN_ROUND_REG : boolean := false; -- enable rounding unit shift register
EN_OUT_REG : boolean := false -- enable output register
);
port (
-- global control --
clk : in std_logic;
-- operand data --
opa_i : in std_logic_vector(DATA_WIDTH-1 downto 0);
opb_i : in std_logic_vector(DATA_WIDTH-1 downto 0);
-- operation control --
shift_dir_i : in std_logic; -- 0: right, 1: left (shift dreiction)
arith_shift_i : in std_logic; -- 0: logical, 1: arithmetical (only for right shifts)
rnd_en_i : in std_logic; -- 0: rounding disabled, 1: rounding enabled
rnd_mode_i : in std_logic; -- 0: floor, 1: infinity (type of rounding)
-- operation result --
data_o : out std_logic_vector(DATA_WIDTH-1 downto 0)
);
end generic_sru;
architecture generic_sru_xv6_rtl of generic_sru is
-- muxcy xilinx primitive component (carry chain multiplexer) --
component muxcy
port (
o : out std_logic;
ci : in std_logic;
di : in std_logic;
s : in std_logic
);
end component;
-- xorcy xilinx primitive component (carry chain 'adder') --
component xorcy
port (
o : out std_logic;
ci : in std_logic;
li : in std_logic
);
end component;
-- local types --
type smask_array_t is array(0 to DATA_WIDTH-1) of std_logic_vector(DATA_WIDTH-1 downto 0);
-- Function: Minimum required bit width --
function index_size(input : natural) return natural is
begin
for i in 0 to natural'high loop
if (2**i >= input) then
return i;
end if;
end loop; -- i
return 0;
end function index_size;
-- Function: init mask for shifter's sign bit cancellation mask --
function init_smask(n: natural) return smask_array_t is
variable smask_array_v : smask_array_t;
begin
smask_array_v := (others => (others => '0'));
smask_array_v(0) := (others => '1');
for i in 0 to n-2 loop
smask_array_v(i+1) := '0' & (smask_array_v(i)(n-1 downto 1));
end loop; -- i
return smask_array_v;
end function init_smask;
-- Function: Bit reversal --
function bit_reversal(input : std_logic_vector) return std_logic_vector is
variable output_v : std_logic_vector(input'range);
begin
for i in 0 to input'length-1 loop
output_v(input'length-i-1) := input(i);
end loop; -- i
return output_v;
end function bit_reversal;
-- internal configuration --
constant log2_data_width_c : natural := index_size(DATA_WIDTH);
constant subword_c : natural := 0;
-- pipeline stage 0 (input register) --
signal opa_s0, opa_ff0 : std_logic_vector(DATA_WIDTH-1 downto 0);
signal opb_s0, opb_ff0 : std_logic_vector(DATA_WIDTH-1 downto 0);
signal shift_dir_s0, shift_dir_ff0 : std_logic;
signal shift_arith_s0, shift_arith_ff0 : std_logic;
signal rnd_en_s0, rnd_en_ff0 : std_logic;
signal rnd_mode_s0, rnd_mode_ff0 : std_logic;
-- shifter core --
constant smask_array : smask_array_t := init_smask(DATA_WIDTH);
signal sra_data : std_logic_vector(DATA_WIDTH-1 downto 0);
signal sra_mask : std_logic_vector(DATA_WIDTH-1 downto 0);
signal shift_in : std_logic_vector(DATA_WIDTH-1 downto 0);
signal shift_res : std_logic_vector(DATA_WIDTH-1 downto 0);
signal carry_sel : std_logic;
-- pipeline stage 1 --
signal sra_data_s1, sra_data_ff1 : std_logic_vector(DATA_WIDTH-1 downto 0);
signal sra_mask_s1, sra_mask_ff1 : std_logic_vector(DATA_WIDTH-1 downto 0);
signal carry_s1, carry_ff1 : std_logic;
signal shift_dir_s1, shift_dir_ff1 : std_logic;
signal shift_arith_s1, shift_arith_ff1 : std_logic;
signal rnd_en_s1, rnd_en_ff1 : std_logic;
signal rnd_mode_s1, rnd_mode_ff1 : std_logic;
-- rounding unit --
signal inc_chain : std_logic_vector(DATA_WIDTH downto 0);
signal inc_data : std_logic_vector(DATA_WIDTH-1 downto 0);
signal inc_result : std_logic_vector(DATA_WIDTH-1 downto 0);
-- pipeline stage 2 --
signal inc_res_s2, inc_res_ff2 : std_logic_vector(DATA_WIDTH-1 downto 0);
signal carry_s2, carry_ff2 : std_logic;
-- zero detector --
signal nibble_is_zero : std_logic_vector((DATA_WIDTH/4)-1 downto 0);
signal zero_chain : std_logic_vector((DATA_WIDTH/4) downto 0);
-- pipeline stage 3: output register --
signal inc_res_s3, inc_res_ff3 : std_logic_vector(DATA_WIDTH-1 downto 0);
signal carry_s3, carry_ff3 : std_logic;
signal zero_s3, zero_ff3 : std_logic;
-- zero overflow carry negative
signal z_flag_o, o_flag_o, c_flag_o, n_flag_o : std_logic;
begin
-- Pipeline Stage 0: Input Register -------------------------------------------------------
-- -------------------------------------------------------------------------------------------
pipe_s0: process(clk)
begin
if rising_edge(clk) then
opa_ff0 <= opa_i;
opb_ff0 <= opb_i;
shift_dir_ff0 <= shift_dir_i;
shift_arith_ff0 <= arith_shift_i;
rnd_en_ff0 <= rnd_en_i;
rnd_mode_ff0 <= rnd_mode_i;
end if;
end process pipe_s0;
-- use input registers? --
opa_s0 <= opa_ff0 when (EN_INPUT_REG = true) else opa_i;
opb_s0 <= opb_ff0 when (EN_INPUT_REG = true) else opb_i;
shift_dir_s0 <= shift_dir_ff0 when (EN_INPUT_REG = true) else shift_dir_i;
shift_arith_s0 <= shift_arith_ff0 when (EN_INPUT_REG = true) else arith_shift_i;
rnd_en_s0 <= rnd_en_ff0 when (EN_INPUT_REG = true) else rnd_en_i;
rnd_mode_s0 <= rnd_mode_ff0 when (EN_INPUT_REG = true) else rnd_mode_i;
-- Shifter Core ---------------------------------------------------------------------------
-- -------------------------------------------------------------------------------------------
shift_in <= bit_reversal(opa_s0) when (shift_dir_s0 = '1') else opa_s0; -- reverse bits if left shift
shifter_core: process(opb_s0, shift_in)
variable carry_sel_v : std_logic_vector(DATA_WIDTH-1 downto 0);
variable positions_v : integer;
begin
-- all shift types are based on a single arithmetical right shifter
positions_v := to_integer(unsigned(opb_s0(log2_data_width_c-1 downto 0)));
sra_data <= std_logic_vector(shift_right(signed(shift_in), positions_v));
sra_mask <= smask_array(positions_v);
-- select carry --
carry_sel_v := shift_in(DATA_WIDTH-2 downto 0) & '0';
carry_sel <= carry_sel_v(positions_v);
end process shifter_core;
-- Pipeline Stage 1: Shifter output register ----------------------------------------------
-- -------------------------------------------------------------------------------------------
pipe_s1: process(clk)
begin
if rising_edge(clk) then
sra_data_ff1 <= sra_data;
sra_mask_ff1 <= sra_mask;
carry_ff1 <= carry_sel;
shift_dir_ff1 <= shift_dir_s0;
shift_arith_ff1 <= shift_arith_s0;
rnd_en_ff1 <= rnd_en_s0;
rnd_mode_ff1 <= rnd_mode_s0;
end if;
end process pipe_s1;
-- use pipeline 1 registers? --
sra_data_s1 <= sra_data_ff1 when (EN_SHIFT_REG = true) else sra_data;
sra_mask_s1 <= sra_mask_ff1 when (EN_SHIFT_REG = true) else sra_mask;
carry_s1 <= carry_ff1 when (EN_SHIFT_REG = true) else carry_sel;
shift_dir_s1 <= shift_dir_ff1 when (EN_SHIFT_REG = true) else shift_dir_s0;
shift_arith_s1 <= shift_arith_ff1 when (EN_SHIFT_REG = true) else shift_arith_s0;
rnd_en_s1 <= rnd_en_ff1 when (EN_SHIFT_REG = true) else rnd_en_s0;
rnd_mode_s1 <= rnd_mode_ff1 when (EN_SHIFT_REG = true) else rnd_mode_s0;
-- Shifter result masking ------------------------------------------------------------------
-- --------------------------------------------------------------------------------------------
shifter_sel: process(shift_dir_s1, shift_arith_s1, sra_data_s1, sra_mask_s1)
variable lrs_v : std_logic_vector(DATA_WIDTH-1 downto 0);
begin
lrs_v := sra_data_s1 and sra_mask_s1;
if (shift_dir_s1 = '1') then -- logical left shift
shift_res <= bit_reversal(lrs_v);
else -- right shift
if (shift_arith_s1 = '1') then -- arithmetical right shift
shift_res <= sra_data_s1;
else -- logical right shift
shift_res <= lrs_v;
end if;
end if;
end process shifter_sel;
-- Rounding --------------------------------------------------------------------------------
-- --------------------------------------------------------------------------------------------
-- start of incrementer carry line with internal carry input
inc_chain(0) <= carry_s1 and (rnd_en_s1 and rnd_mode_s1);
-- simple incrementer, using dedicated hardware (muxcy, xorcy)
increment_unit:
for i in 0 to DATA_WIDTH-1 generate
inc_muxcy_inst: muxcy
port map (
o => inc_chain(i+1),
ci => inc_chain(i),
di => '0',
s => shift_res(i)
);
inc_xorcy_inst: xorcy
port map (
o => inc_data(i),
ci => inc_chain(i),
li => shift_res(i)
);
end generate; -- i
-- operation result output --
inc_result <= inc_data when (EN_ROUNDING = true) else shift_res;
-- Pipeline Stage 2: Rounding unit output register ----------------------------------------
-- -------------------------------------------------------------------------------------------
pipe_s2: process(clk)
begin
if rising_edge(clk) then
inc_res_ff2 <= inc_result;
carry_ff2 <= carry_s1;
end if;
end process pipe_s2;
-- use pipeline 2 registers? --
inc_res_s2 <= inc_res_ff2 when (EN_ROUND_REG = true) else inc_result;
carry_s2 <= carry_ff2 when (EN_ROUND_REG = true) else carry_s1;
-- Zero Detector --------------------------------------------------------------------------
-- -------------------------------------------------------------------------------------------
zero_chain(0) <= '1'; -- start a new subword chain
zero_detector:
for i in 0 to (DATA_WIDTH/4)-1 generate -- number of nibbles
-- zero detection for 4 bit -> 1 LUT + 1 MUXCY, propagate previous zero signal, when nibble is zero
nibble_is_zero(i) <= '1' when (inc_res_s2(i*4+3 downto i*4) = "0000") else '0'; -- is zero?
zero_detector_muxcy: muxcy
port map (
o => zero_chain(i+1), -- chain output signal
ci => zero_chain(i), -- s=1: chain input signal
di => '0', -- s=0: 0 input, nibble is not zero
s => nibble_is_zero(i) -- mux select input
);
end generate; -- i
-- Pipeline Stage 3: Output register ------------------------------------------------------
-- -------------------------------------------------------------------------------------------
pipe_s3: process(clk)
begin
if rising_edge(clk) then
inc_res_ff3 <= inc_res_s2;
carry_ff3 <= carry_s2;
zero_ff3 <= zero_chain(DATA_WIDTH/4);
end if;
end process pipe_s3;
-- use pipeline 2 registers? --
inc_res_s3 <= inc_res_ff3 when (EN_OUT_REG = true) else inc_res_s2;
carry_s3 <= carry_ff3 when (EN_OUT_REG = true) else carry_s2;
zero_s3 <= zero_ff3 when (EN_OUT_REG = true) else zero_chain(DATA_WIDTH/4);
-- data output --
data_o <= inc_res_s3;
-- negative flag output --
n_flag_o <= inc_res_s3(DATA_WIDTH-1);
-- zero flag output --
z_flag_o <= zero_s3;
-- carry flag output --
c_flag_o <= carry_s3;
-- TODO: overflow:
-- all out-shifted bits should be equal to the sign, else overflow
-- for signed operations, also the result sign should be equal to the original sign
o_flag_o <= '0'; -- implement me!
end generic_sru_xv6_rtl;
| mit | 39876959632f3f4b6a46f0f400bf6ac7 | 0.569518 | 3.575243 | false | false | false | false |
impedimentToProgress/UCI-BlueChip | AttackFiles/Attacks/privEsc/lib/gaisler/leon3/mmu_acache.vhd | 2 | 12,676 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: mmu_acache
-- File: mmu_acache.vhd
-- Author: Jiri Gaisler - Gaisler Research, Konrad Eisele <[email protected]>
-- Description: Interface module between I/D cache controllers and Amba AHB
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
library gaisler;
use gaisler.libiu.all;
use gaisler.libcache.all;
use gaisler.leon3.all;
use gaisler.mmuconfig.all;
use gaisler.mmuiface.all;
entity mmu_acache is
generic (
hindex : integer range 0 to NAHBMST-1 := 0;
ilinesize : integer range 4 to 8 := 4;
cached : integer := 0;
clk2x : integer := 0;
scantest : integer := 0);
port (
rst : in std_logic;
clk : in std_logic;
mcii : in memory_ic_in_type;
mcio : out memory_ic_out_type;
mcdi : in memory_dc_in_type;
mcdo : out memory_dc_out_type;
mcmmi : in memory_mm_in_type;
mcmmo : out memory_mm_out_type;
ahbi : in ahb_mst_in_type;
ahbo : out ahb_mst_out_type;
ahbso : in ahb_slv_out_vector;
hclken : in std_ulogic
);
end;
architecture rtl of mmu_acache is
-- cache control register type
type cctrltype is record
ib : std_logic; -- icache burst enable
dfrz : std_logic; -- dcache freeze enable
ifrz : std_logic; -- icache freeze enable
dsnoop : std_logic; -- data cache snooping
dcs : std_logic_vector(1 downto 0); -- dcache state
ics : std_logic_vector(1 downto 0); -- icache state
end record;
type astates is (idle, dcache, icache, mmu);
type reg_type is record
bg : std_logic; -- bus grant
bo : std_logic_vector(1 downto 0); -- bus owner
ba : std_logic; -- bus active
lb : std_ulogic; -- last burst cycle
retry : std_logic; -- retry/split pending
werr : std_logic; -- write error
hlocken : std_ulogic; -- ready to perform locked transaction
lock : std_ulogic; -- keep bus locked during SWAP sequence
hcache : std_logic; -- cacheable access
astate : astates;
end record;
type reg2_type is record
reqmsk : std_logic_vector(2 downto 0);
hclken2 : std_ulogic;
end record;
constant hconfig : ahb_config_type := (
0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_LEON3, 0, LEON3_VERSION, 0),
others => zero32);
constant ctbl : std_logic_vector(15 downto 0) := conv_std_logic_vector(cached, 16);
function dec_fixed(scache : std_ulogic;
haddr : std_logic_vector(3 downto 0); cached : integer) return std_ulogic is
begin
if (cached /= 0) then return ctbl(conv_integer(haddr(3 downto 0)));
else return(scache); end if;
end;
signal r, rin : reg_type;
signal r2, r2in : reg2_type;
begin
comb : process(ahbi, r, rst, mcii, mcdi, mcmmi, ahbso, hclken, r2)
variable v : reg_type;
variable v2 : reg2_type;
variable haddr : std_logic_vector(31 downto 0); -- address bus
variable htrans : std_logic_vector(1 downto 0); -- transfer type
variable hwrite : std_logic; -- read/write
variable hlock : std_logic; -- bus lock
variable hsize : std_logic_vector(2 downto 0); -- transfer size
variable hburst : std_logic_vector(2 downto 0); -- burst type
variable hwdata : std_logic_vector(31 downto 0); -- write data
variable hbusreq : std_logic; -- bus request
variable iflush, dflush, mmflush : std_logic;
variable iready, dready, mmready : std_logic;
variable igrant, dgrant, mmgrant : std_logic;
variable iretry, dretry, mmretry : std_logic;
variable ihcache, dhcache, mmhcache, hcache, dec_hcache : std_logic;
variable imexc, dmexc, mmmexc : std_logic;
variable dreq : std_logic;
variable nbo : std_logic_vector(1 downto 0);
variable su, nb : std_logic;
variable scanen : std_ulogic;
begin
-- initialisation
htrans := HTRANS_IDLE;
v := r; v.werr := '0'; v2 := r2;
iready := '0'; dready := '0'; mmready := '0';
igrant := '0'; dgrant := '0'; mmgrant := '0';
imexc := '0'; dmexc := '0'; mmmexc := '0'; hlock := '0';
iretry := '0'; dretry := '0'; mmretry := '0';
ihcache := '0'; dhcache := '0'; mmhcache := '0';
iflush := '0'; dflush := '0'; mmflush := '0'; su := '0';
hcache := ahbi.hcache;
haddr := (others => '0');
hwrite := '0';
hsize := (others => '0');
hlock := '0';
hburst := (others => '0');
if ahbi.hready = '1' then v.lb := '0'; end if;
if scantest = 1 then scanen := ahbi.scanen; else scanen := '0'; end if;
-- generate AHB signals
dreq := mcdi.req;
hwdata := mcdi.data;
hbusreq := '0';
if (mcii.req = '1') and ((clk2x = 0) or (r2.reqmsk(2) = '1')) and
not (( ((r.ba and dreq) = '1') and (r.bo = "01")) or
( ((r.ba and mcmmi.req) = '1') and (r.bo = "10"))) then
nbo := "00";
hbusreq := '1';
htrans := HTRANS_NONSEQ;
elsif (dreq = '1') and ((clk2x = 0) or (r2.reqmsk(1) = '1')) and
not (( ((r.ba and mcii.req) = '1') and (r.bo = "00")) or
( ((r.ba and mcmmi.req) = '1') and (r.bo = "10"))) then
nbo := "01";
hbusreq := '1';
if (not mcdi.lock or r.hlocken) = '1' then htrans := HTRANS_NONSEQ; end if;
elsif (mcmmi.req = '1') and ((clk2x = 0) or (r2.reqmsk(0) = '1')) and
not (( ((r.ba and mcii.req) = '1') and (r.bo = "00")) or
( ((r.ba and dreq) = '1') and (r.bo = "01"))) then
nbo := "10";
hbusreq := '1';
htrans := HTRANS_NONSEQ;
else
nbo := "11";
end if;
dec_hcache := ahb_slv_dec_cache(mcdi.address, ahbso, cached);
if nbo = "10" then
haddr := mcmmi.address; hwrite := not mcmmi.read; hsize := '0' & mcmmi.size;
hlock := mcmmi.lock;
htrans := HTRANS_NONSEQ; hburst := HBURST_SINGLE;
if (mcmmi.req and r.bg and ahbi.hready and not r.retry) = '1'
then mmgrant := '1'; v.hcache := dec_fixed(ahbi.hcache, haddr(31 downto 28), cached); end if;
elsif nbo = "00" then
haddr := mcii.address; hwrite := '0'; hsize := HSIZE_WORD; hlock := '0';
su := mcii.su;
if ((mcii.req and r.ba) = '1') and (r.bo = "00") and ((not r.retry) = '1') then
htrans := HTRANS_SEQ; haddr(4 downto 2) := haddr(4 downto 2) +1;
if (((ilinesize = 4) and haddr(3 downto 2) = "10")
or ((ilinesize = 8) and haddr(4 downto 2) = "110")) and (ahbi.hready = '1')
then v.lb := '1'; end if;
end if;
if mcii.burst = '1' then hburst := HBURST_INCR;
else hburst := HBURST_SINGLE; end if;
if (mcii.req and r.bg and ahbi.hready and not r.retry) = '1'
then igrant := '1'; v.hcache := dec_fixed(ahbi.hcache, haddr(31 downto 28), cached); end if;
elsif nbo = "01" then
haddr := mcdi.address; hwrite := not mcdi.read; hsize := '0' & mcdi.size;
hlock := mcdi.lock;
if mcdi.asi /= "1010" then su := '1'; else su := '0'; end if; --ASI_UDATA
if mcdi.burst = '1' then hburst := HBURST_INCR;
else hburst := HBURST_SINGLE; end if;
if ((dreq and r.ba) = '1') and (r.bo = "01") and ((not r.retry) = '1') then
htrans := HTRANS_SEQ; haddr(4 downto 2) := haddr(4 downto 2) +1;
hburst := HBURST_INCR;
end if;
if (dreq and r.bg and ahbi.hready and not r.retry) = '1'
then dgrant := not mcdi.lock or r.hlocken; v.hcache := dec_hcache; end if;
end if;
if (hclken = '1') or (clk2x = 0) then
if (r.ba = '1') and ((ahbi.hresp = HRESP_RETRY) or (ahbi.hresp = HRESP_SPLIT))
then v.retry := not ahbi.hready; else v.retry := '0'; end if;
end if;
if r.retry = '1' then htrans := HTRANS_IDLE; end if;
if r.bo = "10" then
hwdata := mcmmi.data;
if r.ba = '1' then
mmhcache := r.hcache;
if ahbi.hready = '1' then
case ahbi.hresp is
when HRESP_OKAY => mmready := '1';
when HRESP_RETRY | HRESP_SPLIT=> mmretry := '1';
when others => mmready := '1'; mmmexc := '1'; v.werr := not mcmmi.read;
end case;
end if;
end if;
elsif r.bo = "00" then
if r.ba = '1' then
ihcache := r.hcache;
if ahbi.hready = '1' then
case ahbi.hresp is
when HRESP_OKAY => iready := '1';
when HRESP_RETRY | HRESP_SPLIT=> iretry := '1';
when others => iready := '1'; imexc := '1';
end case;
end if;
end if;
elsif r.bo = "01" then
if r.ba = '1' then
dhcache := r.hcache;
if ahbi.hready = '1' then
case ahbi.hresp is
when HRESP_OKAY => dready := '1'; v.lock := mcdi.lock and mcdi.read;
when HRESP_RETRY | HRESP_SPLIT=> dretry := '1';
when others => dready := '1'; dmexc := '1'; v.werr := not mcdi.read;
end case;
end if;
end if;
hlock := mcdi.lock;
end if;
if r.lock = '1' then hlock := mcdi.lock; end if;
if (r.lock = '1') and (nbo = "01") then v.lock := '0'; end if;
if (nbo = "01") and ((hsize = "011") or ((dec_hcache and mcdi.read and mcdi.cache) = '1')) then
hsize := "010"; haddr(1 downto 0) := "00";
end if;
if ahbi.hready = '1' then
if r.retry = '0' then v.bo := nbo; end if;
v.bg := ahbi.hgrant(hindex);
if (htrans = HTRANS_NONSEQ) or (htrans = HTRANS_SEQ) then
v.ba := r.bg;
else v.ba := '0'; end if;
v.hlocken := hlock and ahbi.hgrant(hindex);
if (clk2x /= 0) then v.hlocken := v.hlocken and r2.reqmsk(1); end if;
end if;
if hburst = HBURST_SINGLE then nb := '1'; else nb := '0'; end if;
if (clk2x /= 0) then
v2.hclken2 := hclken;
if hclken = '1' then
v2.reqmsk := mcii.req & mcdi.req & mcmmi.req;
if (clk2x > 8) and (r2.hclken2 = '1') then v2.reqmsk := "111"; end if;
end if;
end if;
-- reset operation
if rst = '0' then
v.bg := '0'; v.bo := "00"; v.ba := '0'; v.retry := '0'; v.werr := '0'; v.lb := '0';
v.hcache := '0'; v.lock := '0'; v.hlocken := '0';
v.astate := idle;
end if;
-- drive ports
ahbo.haddr <= haddr ;
ahbo.htrans <= htrans;
ahbo.hbusreq <= hbusreq and not r.lb and not (((r.bo(1) and r.ba) or nb) and r.bg);
ahbo.hwdata <= hwdata;
ahbo.hlock <= hlock;
ahbo.hwrite <= hwrite;
ahbo.hsize <= hsize;
ahbo.hburst <= hburst;
ahbo.hindex <= hindex;
if nbo = "00" then ahbo.hprot <= "11" & su & '0';
else ahbo.hprot <= "11" & su & (nbo(1) xor nbo(0)); end if;
mcio.grant <= igrant;
mcio.ready <= iready;
mcio.mexc <= imexc;
mcio.retry <= iretry;
mcio.cache <= ihcache;
mcdo.grant <= dgrant;
mcdo.ready <= dready;
mcdo.mexc <= dmexc;
mcdo.retry <= dretry;
mcdo.werr <= r.werr;
mcdo.cache <= dhcache;
mcdo.ba <= r.ba;
mcdo.bg <= r.bg;
mcmmo.grant <= mmgrant;
mcmmo.ready <= mmready;
mcmmo.mexc <= mmmexc;
mcmmo.retry <= mmretry;
mcmmo.werr <= r.werr;
mcmmo.cache <= mmhcache;
mcio.scanen <= scanen;
mcdo.scanen <= scanen;
mcdo.testen <= ahbi.testen;
rin <= v; r2in <= v2;
end process;
mcio.data <= ahbi.hrdata;
mcdo.data <= ahbi.hrdata;
mcmmo.data <= ahbi.hrdata;
ahbo.hirq <= (others => '0');
ahbo.hconfig <= hconfig;
reg : process(clk)
begin
if rising_edge(clk) then r <= rin; end if;
end process;
reg2gen : if (clk2x /= 0) generate
reg2 : process(clk)
begin
if rising_edge(clk) then r2 <= r2in; end if;
end process;
end generate;
noreg2gen : if (clk2x = 0) generate
r2.reqmsk <= "000";
end generate;
end;
| mit | 9b11c22a7a8ee634d7c8e76e449a40a3 | 0.560587 | 3.226266 | false | false | false | false |
impedimentToProgress/UCI-BlueChip | AttackFiles/Attacks/privEsc/lib/gaisler/pci/pci_tbfunct.vhd | 2 | 9,334 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: pci_tbfunct
-- File: pci_tbfunct.vhd
-- Author: Alf Vaerneus - Gaisler Research
-- Description: Various PCI test functions
-----------------------------------------------------------------------------
-- pragma translate_off
library ieee;
use ieee.std_logic_1164.all;
library gaisler;
use gaisler.ambatest.all;
package pci_tb is
procedure PCI_read_single(ctrl : inout ctrl_type; signal tbi : out tb_in_type; signal tbo : in tb_out_type; dbglevel : in integer);
procedure PCI_read_burst(ctrl : inout ctrl_type; signal tbi : out tb_in_type; signal tbo : in tb_out_type; dbglevel : in integer);
procedure PCI_write_single(ctrl : inout ctrl_type; signal tbi : out tb_in_type; signal tbo : in tb_out_type; dbglevel : in integer);
procedure PCI_write_burst(ctrl : inout ctrl_type; signal tbi : out tb_in_type; signal tbo : in tb_out_type; dbglevel : in integer);
procedure PCI_read_config(ctrl : inout ctrl_type; signal tbi : out tb_in_type; signal tbo : in tb_out_type; dbglevel : in integer);
procedure PCI_write_config(ctrl : inout ctrl_type; signal tbi : out tb_in_type; signal tbo : in tb_out_type; dbglevel : in integer);
end pci_tb;
package body pci_tb is
constant printlevel : integer := 2;
function string_inv(instring : string(18 downto 1)) return string is
variable vstr : string(1 to 18);
begin
vstr(1 to 18) := instring(18 downto 1);
return(vstr);
end string_inv;
procedure PCI_read_single(
ctrl : inout ctrl_type;
signal tbi : out tb_in_type;
signal tbo : in tb_out_type;
dbglevel : in integer) is
begin
if tbo.ready = '1' then wait until tbo.ready = '0'; end if;
tbi.address <= ctrl.address;
tbi.command <= M_READ;
tbi.no_words <= 1;
tbi.userfile <= ctrl.userfile;
tbi.rfile <= ctrl.rfile;
if ctrl.userfile then
if dbglevel >= printlevel then
printf("PCIMST TB: PCI Read from file %s",string_inv(ctrl.rfile));
end if;
else
if dbglevel >= printlevel then
printf("PCIMST TB: PCI Read from address %x",ctrl.address);
end if;
end if;
tbi.usewfile <= ctrl.usewfile;
tbi.wfile <= ctrl.wfile;
tbi.start <= '1';
wait until tbo.ready = '1';
ctrl.data := tbo.data;
ctrl.status := tbo.status;
if ctrl.status = ERR then
if dbglevel >= printlevel then
printf("PCIMST TB: #ERROR# Read access failed at %x",ctrl.address);
end if;
elsif ctrl.status = OK then
if dbglevel >= printlevel then
printf("PCIMST TB: Returned data: %x",ctrl.data);
end if;
end if;
tbi.start <= '0';
end procedure;
procedure PCI_read_burst(
ctrl : inout ctrl_type;
signal tbi : out tb_in_type;
signal tbo : in tb_out_type;
dbglevel : in integer) is
variable i : integer;
begin
if tbo.ready = '1' then wait until tbo.ready = '0'; end if;
tbi.address <= ctrl.address;
tbi.command <= M_READ_MULT;
tbi.no_words <= ctrl.no_words;
tbi.userfile <= ctrl.userfile;
tbi.rfile <= ctrl.rfile;
if ctrl.userfile then
if dbglevel >= printlevel then
printf("PCIMST TB: PCI Read burst from file %s",string_inv(ctrl.rfile));
end if;
else
if dbglevel >= printlevel then
printf("PCIMST TB: PCI Read burst from address %x",ctrl.address);
end if;
end if;
tbi.usewfile <= ctrl.usewfile;
tbi.wfile <= ctrl.wfile;
tbi.start <= '1';
wait until tbo.ready = '1';
ctrl.data := tbo.data;
if ctrl.status = ERR then
if dbglevel >= printlevel then
printf("PCIMST TB: #ERROR# Read access failed at %x",ctrl.address);
end if;
elsif ctrl.status = OK then
if dbglevel >= printlevel then
printf("PCIMST TB: Returned data: %x",ctrl.data);
end if;
end if;
ctrl.status := tbo.status;
tbi.start <= '0';
end procedure;
procedure PCI_write_single(
ctrl : inout ctrl_type;
signal tbi : out tb_in_type;
signal tbo : in tb_out_type;
dbglevel : in integer) is
begin
if tbo.ready = '1' then wait until tbo.ready = '0'; end if;
tbi.address <= ctrl.address;
tbi.data <= ctrl.data;
tbi.command <= M_WRITE;
tbi.no_words <= 1;
tbi.userfile <= ctrl.userfile;
tbi.rfile <= ctrl.rfile;
if ctrl.userfile then
if dbglevel >= printlevel then
printf("PCIMST TB: PCI Write from file %s",string_inv(ctrl.rfile));
end if;
else
if dbglevel >= printlevel then
printf("PCIMST TB: PCI Write to address %x",ctrl.address);
end if;
end if;
tbi.usewfile <= false; -- No log file for write accesses
tbi.wfile <= ctrl.wfile;
tbi.start <= '1';
wait until tbo.ready = '1';
ctrl.status := tbo.status;
if ctrl.status = ERR then
if dbglevel >= printlevel then
printf("PCIMST TB: #ERROR# Write access failed at %x",ctrl.address);
end if;
elsif ctrl.status = OK then
if dbglevel >= printlevel then
printf("PCIMST TB: Write success!");
end if;
end if;
tbi.start <= '0';
end procedure;
procedure PCI_write_burst(
ctrl : inout ctrl_type;
signal tbi : out tb_in_type;
signal tbo : in tb_out_type;
dbglevel : in integer) is
begin
if tbo.ready = '1' then wait until tbo.ready = '0'; end if;
tbi.address <= ctrl.address;
tbi.data <= ctrl.data;
tbi.command <= M_WRITE;
tbi.no_words <= ctrl.no_words;
tbi.userfile <= ctrl.userfile;
tbi.rfile <= ctrl.rfile;
if ctrl.userfile then
if dbglevel >= printlevel then
printf("PCIMST TB: PCI Write from file %s",string_inv(ctrl.rfile));
end if;
else
if dbglevel >= printlevel then
printf("PCIMST TB: PCI Write burst to address %x",ctrl.address);
end if;
end if;
tbi.usewfile <= false; -- No log file for write accesses
tbi.wfile <= ctrl.wfile;
tbi.start <= '1';
wait until tbo.ready = '1';
ctrl.status := tbo.status;
if ctrl.status = ERR then
if dbglevel >= printlevel then
printf("PCIMST TB: #ERROR# Write access failed at %x",ctrl.address);
end if;
elsif ctrl.status = OK then
if dbglevel >= printlevel then
printf("PCIMST TB: Write success!");
end if;
end if;
tbi.start <= '0';
end procedure;
procedure PCI_read_config(
ctrl : inout ctrl_type;
signal tbi : out tb_in_type;
signal tbo : in tb_out_type;
dbglevel : in integer) is
begin
if tbo.ready = '1' then wait until tbo.ready = '0'; end if;
tbi.address <= ctrl.address;
tbi.command <= C_READ;
tbi.no_words <= 1;
tbi.userfile <= ctrl.userfile;
tbi.rfile <= ctrl.rfile;
if ctrl.userfile then
if dbglevel >= printlevel then
printf("PCIMST TB: PCI Config Read from file %s",string_inv(ctrl.rfile));
end if;
else
if dbglevel >= printlevel then
printf("PCIMST TB: PCI Config Read from address %x",ctrl.address);
end if;
end if;
tbi.usewfile <= ctrl.usewfile;
tbi.wfile <= ctrl.wfile;
tbi.start <= '1';
wait until tbo.ready = '1';
ctrl.data := tbo.data;
ctrl.status := tbo.status;
if ctrl.status = ERR then
if dbglevel >= printlevel then
printf("PCIMST TB: #ERROR# Read access failed at %x",ctrl.address);
end if;
elsif ctrl.status = OK then
if dbglevel >= printlevel then
printf("PCIMST TB: Returned data: %x",ctrl.data);
end if;
end if;
tbi.start <= '0';
end procedure;
procedure PCI_write_config(
ctrl : inout ctrl_type;
signal tbi : out tb_in_type;
signal tbo : in tb_out_type;
dbglevel : in integer) is
begin
if tbo.ready = '1' then wait until tbo.ready = '0'; end if;
tbi.address <= ctrl.address;
tbi.data <= ctrl.data;
tbi.command <= C_WRITE;
tbi.no_words <= 1;
tbi.userfile <= ctrl.userfile;
tbi.rfile <= ctrl.rfile;
if ctrl.userfile then
if dbglevel >= printlevel then
printf("PCIMST TB: PCI Config Write from file %s",string_inv(ctrl.rfile));
end if;
else
if dbglevel >= printlevel then
printf("PCIMST TB: PCI Config Write to address %x",ctrl.address);
end if;
end if;
tbi.usewfile <= false; -- No log file for write accesses
tbi.wfile <= ctrl.wfile;
tbi.start <= '1';
wait until tbo.ready = '1';
ctrl.status := tbo.status;
if ctrl.status = ERR then
if dbglevel >= printlevel then
printf("PCIMST TB: #ERROR# Config write access failed at %x",ctrl.address);
end if;
elsif ctrl.status = OK then
if dbglevel >= printlevel then
printf("PCIMST TB: Config write success!");
end if;
end if;
tbi.start <= '0';
end procedure;
end package body;
-- pragma translate_on
| mit | adb85bf91b3d8a42f51dab8fcf3fdc5c | 0.643133 | 3.402844 | false | false | false | false |
cafe-alpha/wascafe | v13/r07c_de10_20201014_abus4/wasca/synthesis/submodules/Altera_UP_SD_CRC16_Generator.vhd | 7 | 2,732 | -- (C) 2001-2015 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
----------------------------------------------------------------------------------------
-- This generates the necessary 16-CRC for Command and Response
-- Implementation: serial input/parallel output
-- When input stream ends, the crcout output is the CRC checksum for them
--
-- NOTES/REVISIONS:
----------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity Altera_UP_SD_CRC16_Generator is
port
(
i_clock : in std_logic;
i_enable : in std_logic;
i_reset_n : in std_logic;
i_sync_reset : in std_logic;
i_shift : in std_logic;
i_datain : in std_logic;
o_dataout : out std_logic;
o_crcout : out std_logic_vector(15 downto 0)
);
end entity;
architecture rtl of Altera_UP_SD_CRC16_Generator is
-- Local wires
-- REGISTERED
signal shift_register : std_logic_vector(15 downto 0);
begin
process (i_clock, i_reset_n)
begin
if (i_reset_n = '0') then
shift_register <= (OTHERS => '0');
else
if (rising_edge(i_clock)) then
if (i_sync_reset = '1') then
shift_register <= (OTHERS => '0');
elsif (i_enable = '1') then
if (i_shift = '0') then
shift_register(0) <= i_datain XOR shift_register(15);
shift_register(4 downto 1) <= shift_register(3 downto 0);
shift_register(5) <= shift_register(4) XOR i_datain XOR shift_register(15);
shift_register(11 downto 6) <= shift_register(10 downto 5);
shift_register(12) <= shift_register(11) XOR i_datain XOR shift_register(15);
shift_register(15 downto 13) <= shift_register(14 downto 12);
else -- shift CRC out (no more calculation now)
shift_register(15 downto 1) <= shift_register(14 downto 0);
shift_register(0) <= '0';
end if;
end if;
end if;
end if;
end process;
o_dataout <= shift_register(15);
o_crcout <= shift_register;
end rtl;
| gpl-2.0 | 73b914c77a2cca4e93ac2f02d06d3816 | 0.643119 | 3.516088 | false | false | false | false |
michaelfivez/ascon_hardware_implementation | ascon128128_unrolled2/Kernel/Sbox.vhd | 1 | 3,941 | -------------------------------------------------------------------------------
--! @project Unrolled (factor 2) hardware implementation of Asconv128128
--! @author Michael Fivez
--! @license This project is released under the GNU Public License.
--! The license and distribution terms for this file may be
--! found in the file LICENSE in this distribution or at
--! http://www.gnu.org/licenses/gpl-3.0.txt
--! @note This is an hardware implementation made for my graduation thesis
--! at the KULeuven, in the COSIC department (year 2015-2016)
--! The thesis is titled 'Energy efficient hardware implementations of CAESAR submissions',
--! and can be found on the COSIC website (www.esat.kuleuven.be/cosic/publications)
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity Sbox is
port(
X0In : in std_logic_vector(63 downto 0);
X1In : in std_logic_vector(63 downto 0);
X2In : in std_logic_vector(63 downto 0);
X3In : in std_logic_vector(63 downto 0);
X4In : in std_logic_vector(63 downto 0);
RoundNr : in std_logic_vector(3 downto 0);
X0Out : out std_logic_vector(63 downto 0);
X1Out : out std_logic_vector(63 downto 0);
X2Out : out std_logic_vector(63 downto 0);
X3Out : out std_logic_vector(63 downto 0);
X4Out : out std_logic_vector(63 downto 0));
end entity Sbox;
architecture structural of Sbox is
begin
Sbox: process(X0In,X1In,X2In,X3In,X4In,RoundNr) is
-- Procedure for 5-bit Sbox
procedure doSboxPart (
variable SboxPartIn : in std_logic_vector(4 downto 0);
variable SboxPartOut : out std_logic_vector(4 downto 0)) is
-- Temp variable
variable SboxPartTemp : std_logic_vector(17 downto 0);
begin
-- Sbox Interconnections
SboxPartTemp(0) := SboxPartIn(0) xor SboxPartIn(4);
SboxPartTemp(1) := SboxPartIn(2) xor SboxPartIn(1);
SboxPartTemp(2) := SboxPartIn(4) xor SboxPartIn(3);
SboxPartTemp(3) := not SboxPartTemp(0);
SboxPartTemp(4) := not SboxPartIn(1);
SboxPartTemp(5) := not SboxPartTemp(1);
SboxPartTemp(6) := not SboxPartIn(3);
SboxPartTemp(7) := not SboxPartTemp(2);
SboxPartTemp(8) := SboxPartIn(1) and SboxPartTemp(3);
SboxPartTemp(9) := SboxPartTemp(1) and SboxPartTemp(4);
SboxPartTemp(10) := SboxPartIn(3) and SboxPartTemp(5);
SboxPartTemp(11) := SboxPartTemp(2) and SboxPartTemp(6);
SboxPartTemp(12) := SboxPartTemp(0) and SboxPartTemp(7);
SboxPartTemp(13) := SboxPartTemp(0) xor SboxPartTemp(9);
SboxPartTemp(14) := SboxPartIn(1) xor SboxPartTemp(10);
SboxPartTemp(15) := SboxPartTemp(1) xor SboxPartTemp(11);
SboxPartTemp(16) := SboxPartIn(3) xor SboxPartTemp(12);
SboxPartTemp(17) := SboxPartTemp(2) xor SboxPartTemp(8);
SboxPartOut(0) := SboxPartTemp(13) xor SboxPartTemp(17);
SboxPartOut(1) := SboxPartTemp(13) xor SboxPartTemp(14);
SboxPartOut(2) := not SboxPartTemp(15);
SboxPartOut(3) := SboxPartTemp(15) xor SboxPartTemp(16);
SboxPartOut(4) := SboxPartTemp(17);
end procedure doSboxPart;
variable X2TempIn : std_logic_vector(63 downto 0);
variable TempIn,TempOut : std_logic_vector(4 downto 0);
begin
-- Xor with round constants
X2TempIn(3 downto 0) := X2In(3 downto 0) xor RoundNr;
X2TempIn(7 downto 4) := X2In(7 downto 4) xnor RoundNr;
X2TempIn(63 downto 8) := X2In(63 downto 8);
-- Apply 5-bit Sbox 64 times
for i in X0In'range loop
TempIn(0) := X0In(i);
TempIn(1) := X1In(i);
TempIn(2) := X2TempIn(i);
TempIn(3) := X3In(i);
TempIn(4) := X4In(i);
doSboxPart(TempIn,TempOut);
X0Out(i) <= TempOut(0);
X1Out(i) <= TempOut(1);
X2Out(i) <= TempOut(2);
X3Out(i) <= TempOut(3);
X4Out(i) <= TempOut(4);
end loop;
end process Sbox;
end architecture structural;
| gpl-3.0 | b310773aea3aea113f39b1fbf2294a28 | 0.640447 | 2.923591 | false | false | false | false |
impedimentToProgress/UCI-BlueChip | AttackFiles/Attacks/privEsc/lib/gaisler/ata/atahost_ahbmst.vhd | 2 | 11,510 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: net
-- File: net.vhd
-- Author: Erik Jagre - Gaisler Research
-- Description: Generic FIFO, based on syncram in grlib
-----------------------------------------------------------------------------
--ATA controller, bus-master
--Erik Jagre 2006-10-04
Library ieee;
Use ieee.std_logic_1164.all;
use work.ata_inf.all;
Library gaisler;
Use gaisler.ata.all;
Library grlib;
Use grlib.stdlib.all;
--************************ENTITY************************************************
Entity atahost_ahbmst is
generic(fdepth: integer := 8);
Port(clk : in std_logic;
rst : in std_logic; --active low
i : in bmi_type;
o : out bmo_type
);
end;
--************************ARCHITECTURE******************************************
Architecture rtl of atahost_ahbmst is
constant abits : integer := Log2(fdepth);
type state_type is (IDLE,INIT,PREPARE,BURST_TO_ATA,BURST_TO_MEM,BURST_WAIT);
type reg_type is record
state : state_type;
o : bmo_type;
adr_cnt : std_logic_vector(abits-1 downto 0);
cur_base : std_logic_vector(31 downto 0);
cur_length : std_logic_vector(15 downto 0);
cur_cnt : std_logic_vector(15 downto 0);
prdtb_offset : std_logic_vector(15 downto 0);
edt : std_logic;
bmen : std_logic;
adr_set : std_logic;
end record;
constant RESET_VECTOR : reg_type := (IDLE, BMO_RESET_VECTOR, zero32(abits-1 downto 0),
zero32, X"0000", X"0000", X"0000", '0', '0', '0');
signal r,ri : reg_type;
begin
--**********************COMBINATORIAL LGOIC***********************************
comb: process(rst,r,i)
variable v : reg_type;
variable v_diff : std_logic_vector(15 downto 0);
variable v_temp : std_logic_vector(31 downto 0);
begin
v:=r;
v.bmen:=i.fr_slv.en;
v.o.we:=not i.fr_slv.dir;
case v.state is
when IDLE => -------------------IDLE STATE---------------------------
if i.fr_slv.en='1' and r.bmen='0' then
v.state:=INIT; v.o.to_slv.done:='0';
v.adr_cnt:=conv_std_logic_vector(0,abits); end if;
when INIT => -------------------INIT STATE---------------------------
v.o.to_mst.write:='0'; v.o.to_ctr.sel:='0';
---------------------- nytt test
v.o.to_mst.address:=i.fr_slv.prdtb+v.prdtb_offset; v.adr_set:='1';
if i.fr_mst.active='0' and r.adr_set='1' then
v.o.to_mst.burst:='1'; v.o.to_mst.start:='1'; end if;
----------------------- slut test
-- if i.fr_mst.active='0' then
-- v.o.to_mst.burst:='1'; v.o.to_mst.start:='1'; end if;
-- v.o.to_mst.address:=i.fr_slv.prdtb+v.prdtb_offset;
if i.fr_mst.ready='1' then
if r.adr_cnt=conv_std_logic_vector(0,abits) then
if i.fr_slv.prd_belec='1' then --prd in mem is big endian
v.cur_base(31 downto 24):=i.fr_mst.rdata(7 downto 0);
v.cur_base(23 downto 16):=i.fr_mst.rdata(15 downto 8);
v.cur_base(15 downto 8):=i.fr_mst.rdata(23 downto 16);
v.cur_base(7 downto 0):=i.fr_mst.rdata(31 downto 24);
else --prd in mem is little endian
v.cur_base:=i.fr_mst.rdata;
end if;
v.adr_cnt:=conv_std_logic_vector(1,abits);
elsif r.adr_cnt=conv_std_logic_vector(1,abits) then
if i.fr_slv.prd_belec='1' then --prd in mem is big endian
v.edt:=i.fr_mst.rdata(7); v.cur_cnt:=(others=>'0');
v.cur_length(15 downto 8):=i.fr_mst.rdata(23 downto 16);
v.cur_length(7 downto 0):=i.fr_mst.rdata(31 downto 24);
else --prd in mem is little endian
v.edt:=i.fr_mst.rdata(31); v.cur_cnt:=(others=>'0');
v.cur_length:=i.fr_mst.rdata(15 downto 0);
end if;
v.state:=PREPARE; v.adr_set:='0';
v.o.to_mst.address:=v.cur_base;
end if;
end if;
if v.o.to_mst.start='1' and r.adr_cnt=conv_std_logic_vector(1,abits)
and i.fr_mst.start='1' then
v.o.to_mst.start:='0'; v.o.to_mst.burst:='0'; end if;
when PREPARE =>
v.o.to_ctr.ack:='0'; v.o.to_ctr.force_rdy:='0';
v.o.to_mst.address:=v.cur_base+v.cur_cnt;
v.adr_cnt:=conv_std_logic_vector(0,abits);
if ((v.edt='1' and v.cur_cnt>=v.cur_length) or i.fr_ctr.irq='1')
and i.fr_ctr.tip='0' then
v.state:=IDLE;
if (v.edt='1' and v.cur_cnt>=v.cur_length) then
v.o.to_slv.done:='1'; v.o.to_ctr.ack:='1'; end if;
end if;
if not(v.edt='1' and v.cur_cnt>=v.cur_length) then
if i.fr_ctr.fifo_rdy='0' and i.fr_slv.dir='0' then
--might fail for AHB ram?
v.o.to_mst.burst:='1'; v.o.to_mst.write:='0';
v.o.to_mst.start:='1'; v.state:=BURST_TO_ATA;
elsif i.fr_ctr.fifo_rdy='0' and i.fr_slv.dir='1' then
--might fail for AHB ram?
v.o.to_ctr.sel:='1';
v.o.to_mst.burst:='1'; v.o.to_mst.write:='1';
v.o.to_mst.start:='1'; v.state:=BURST_TO_MEM;
end if;
end if;
when BURST_TO_ATA =>
if i.fr_mst.start='1' and v.o.to_ctr.force_rdy='0' then
v_temp:=r.o.to_mst.address+4;
--abort burst due to PRD exhausted --------------------new
if r.cur_cnt+4>=r.cur_length then
v.o.to_mst.start:='0'; v.o.to_mst.burst:='0'; end if;
--...due to fifo full
if r.adr_cnt=conv_std_logic_vector(fdepth-1,abits) then
v.o.to_mst.start:='0'; v.o.to_mst.burst:='0'; end if;
--...due to AMBA 1k limit
if not(v_temp(11 downto 10) = v.o.to_mst.address(11 downto 10))
and not(r.edt='1' and r.cur_cnt>=r.cur_length) then
v.o.to_mst.start:='0'; v.o.to_mst.burst:='0';
end if;
end if;
if i.fr_mst.ready='1' and v.o.to_ctr.force_rdy='0' then
v.o.to_mst.address:=r.o.to_mst.address+4; o.d<=i.fr_mst.rdata;
v.adr_cnt:=r.adr_cnt+1; v.cur_cnt:=r.cur_cnt+4; v.o.to_ctr.sel:='1';
if r.adr_cnt=conv_std_logic_vector(fdepth-1,abits) then
v.o.to_ctr.force_rdy:='1'; end if;
--state transition when AMBA 1k limit
if not(v.o.to_mst.address(11 downto 10) =
r.o.to_mst.address(11 downto 10))
and v.o.to_ctr.force_rdy='0'
and not(r.edt='1' and r.cur_cnt>=r.cur_length) then
v.state:=BURST_WAIT; end if;
else v.o.to_ctr.sel:='0'; end if;
--state transition when FIFO filled
if v.cur_cnt>=v.cur_length and v.edt='0'
-- and i.fr_ctr.fifo_rdy='1' then
and (i.fr_ctr.fifo_rdy='1'or r.cur_cnt+4>=r.cur_length) then
v.prdtb_offset:=v.prdtb_offset+X"0008"; v.cur_cnt:=X"0000";
v.adr_cnt:=conv_std_logic_vector(0,abits); v.state:=INIT;
elsif i.fr_ctr.fifo_rdy='1' then v.state:=PREPARE; end if;
when BURST_TO_MEM =>
v.o.to_ctr.sel:='0';
if i.fr_mst.start='1' and v.o.to_ctr.force_rdy='0' then
v_temp:=r.o.to_mst.address+4; o.to_mst.wdata<=i.fr_ctr.q;
--abort burst due to PRD exhausted
if r.cur_cnt+4>=r.cur_length then
v.o.to_mst.start:='0'; v.o.to_mst.burst:='0'; end if;
--...due to fifo empty
if r.adr_cnt=conv_std_logic_vector(fdepth-1,abits) then
v.o.to_mst.start:='0'; v.o.to_mst.burst:='0'; end if;
--...due to AMBA 1k limit
if not(v_temp(11 downto 10) = v.o.to_mst.address(11 downto 10))
and not(r.edt='1' and r.cur_cnt>=r.cur_length) then
v.o.to_mst.start:='0'; v.o.to_mst.burst:='0';
end if;
end if;
if i.fr_mst.ready='1' and v.o.to_ctr.force_rdy='0' then
v.o.to_mst.address:=r.o.to_mst.address+4;
v.adr_cnt:=r.adr_cnt+1; v.cur_cnt:=r.cur_cnt+4;
--fifo emptied, set ready
if r.adr_cnt=conv_std_logic_vector(fdepth-1,abits) then
v.o.to_ctr.force_rdy:='1'; end if;
--fifo NOT emptied, keep reading
if r.adr_cnt < conv_std_logic_vector(fdepth-1,abits)
and r.cur_cnt+4<r.cur_length then
v.o.to_ctr.sel:='1'; else v.o.to_ctr.sel:='0'; end if;
--state transition when AMBA 1k limit
if not(v.o.to_mst.address(11 downto 10) =
r.o.to_mst.address(11 downto 10))
and v.o.to_ctr.force_rdy='0'
and not(r.edt='1' and r.cur_cnt>=r.cur_length) then
v.state:=BURST_WAIT; end if;
else v.o.to_ctr.sel:='0'; --2007-1-15
end if;
if i.fr_mst.active='0' then
if v.cur_cnt>=v.cur_length and v.edt='0'
and (i.fr_ctr.fifo_rdy='1'or r.cur_cnt+4>=r.cur_length) then
v.prdtb_offset:=v.prdtb_offset+X"0008"; v.cur_cnt:=X"0000";
v.adr_cnt:=conv_std_logic_vector(0,abits); v.state:=INIT;
elsif i.fr_ctr.fifo_rdy='1' then v.state:=PREPARE; end if;
end if;
when BURST_WAIT =>
if i.fr_mst.active='0' then
v.o.to_ctr.sel:='0'; v.o.to_mst.burst:='1'; v.o.to_mst.start:='1';
if i.fr_slv.dir='1' then
v.o.to_mst.write:='1'; v.state:=BURST_TO_MEM;
else
v.o.to_mst.write:='0'; v.state:=BURST_TO_ATA;
end if;
end if;
when others => ----------------------------------------------------------
v.state:=IDLE;
end case;
if rst='0' or (i.fr_slv.en='0' and r.bmen='1') or i.fr_mst.mexc='1' then
v:=RESET_VECTOR; end if;
----------------------ASSIGN OUTPUTS----------------------------------------
v.o.to_slv.cur_base:=v.cur_base; v.o.to_slv.cur_cnt:=v.cur_cnt; --2006-11-13
o.to_slv<=r.o.to_slv;
o.we<=r.o.we;
o.to_mst.address<=r.o.to_mst.address;
o.to_mst.start<=v.o.to_mst.start;
o.to_mst.burst<=v.o.to_mst.burst;
o.to_mst.write<=v.o.to_mst.write;
o.to_mst.busy<=r.o.to_mst.busy;
o.to_mst.irq<=r.o.to_mst.irq;
o.to_mst.size<=r.o.to_mst.size;
o.to_ctr.force_rdy<=r.o.to_ctr.force_rdy;
o.to_ctr.ack<=r.o.to_ctr.ack;
o.to_ctr.sel<=v.o.to_ctr.sel;
o.to_slv.err<=i.fr_mst.mexc; --2007-02-06
o.to_mst.wdata<=i.fr_ctr.q; --2006-11-16
o.d<=i.fr_mst.rdata; --2006-11-16
ri<=v;
end process comb;
--**********************FLIP FLOPS********************************************
sync: process(clk)
begin
if rising_edge(clk) then r<=ri; end if;
end process sync;
end;
--************************END OF FILE*******************************************
| mit | 1b89139be3b8b55852275550e978bcbe | 0.522589 | 2.955071 | false | false | false | false |
lxp32/lxp32-cpu | verify/lxp32/src/platform/platform.vhd | 2 | 8,006 | ---------------------------------------------------------------------
-- LXP32 platform top-level design unit
--
-- Part of the LXP32 test platform
--
-- Copyright (c) 2016 by Alex I. Kuznetsov
--
-- A SoC-like simulation platform for the LXP32 CPU, containing
-- a few peripherals such as program RAM, timer and coprocessor.
--
-- Note: regardless of whether this description is synthesizable,
-- it was designed exclusively for simulation purposes.
---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity platform is
generic(
CPU_DBUS_RMW: boolean;
CPU_MUL_ARCH: string;
MODEL_LXP32C: boolean;
THROTTLE_DBUS: boolean;
THROTTLE_IBUS: boolean
);
port(
clk_i: in std_logic;
rst_i: in std_logic;
cpu_rst_i: in std_logic;
wbm_cyc_o: out std_logic;
wbm_stb_o: out std_logic;
wbm_we_o: out std_logic;
wbm_sel_o: out std_logic_vector(3 downto 0);
wbm_ack_i: in std_logic;
wbm_adr_o: out std_logic_vector(27 downto 2);
wbm_dat_o: out std_logic_vector(31 downto 0);
wbm_dat_i: in std_logic_vector(31 downto 0);
wbs_cyc_i: in std_logic;
wbs_stb_i: in std_logic;
wbs_we_i: in std_logic;
wbs_sel_i: in std_logic_vector(3 downto 0);
wbs_ack_o: out std_logic;
wbs_adr_i: in std_logic_vector(31 downto 2);
wbs_dat_i: in std_logic_vector(31 downto 0);
wbs_dat_o: out std_logic_vector(31 downto 0);
gp_io: inout std_logic_vector(31 downto 0)
);
end entity;
architecture rtl of platform is
type wbm_type is record
cyc: std_logic;
stb: std_logic;
we: std_logic;
sel: std_logic_vector(3 downto 0);
ack: std_logic;
adr: std_logic_vector(31 downto 2);
wdata: std_logic_vector(31 downto 0);
rdata: std_logic_vector(31 downto 0);
end record;
type wbs_type is record
cyc: std_logic;
stb: std_logic;
we: std_logic;
sel: std_logic_vector(3 downto 0);
ack: std_logic;
adr: std_logic_vector(27 downto 2);
wdata: std_logic_vector(31 downto 0);
rdata: std_logic_vector(31 downto 0);
end record;
type ibus_type is record
cyc: std_logic;
stb: std_logic;
cti: std_logic_vector(2 downto 0);
bte: std_logic_vector(1 downto 0);
ack: std_logic;
adr: std_logic_vector(29 downto 0);
dat: std_logic_vector(31 downto 0);
end record;
signal cpu_rst: std_logic;
signal cpu_irq: std_logic_vector(7 downto 0);
signal cpu_dbus: wbm_type;
signal cpu_ibus: ibus_type;
signal lli_re: std_logic;
signal lli_adr: std_logic_vector(29 downto 0);
signal lli_dat: std_logic_vector(31 downto 0);
signal lli_busy: std_logic;
signal monitor_dbus: wbm_type;
signal ram_wb: wbs_type;
signal timer_wb: wbs_type;
signal timer_elapsed: std_logic;
signal coprocessor_wb: wbs_type;
signal coprocessor_irq: std_logic;
begin
-- Interconnect
intercon_inst: entity work.intercon(rtl)
port map(
clk_i=>clk_i,
rst_i=>rst_i,
s0_cyc_i=>wbs_cyc_i,
s0_stb_i=>wbs_stb_i,
s0_we_i=>wbs_we_i,
s0_sel_i=>wbs_sel_i,
s0_ack_o=>wbs_ack_o,
s0_adr_i=>wbs_adr_i,
s0_dat_i=>wbs_dat_i,
s0_dat_o=>wbs_dat_o,
s1_cyc_i=>monitor_dbus.cyc,
s1_stb_i=>monitor_dbus.stb,
s1_we_i=>monitor_dbus.we,
s1_sel_i=>monitor_dbus.sel,
s1_ack_o=>monitor_dbus.ack,
s1_adr_i=>monitor_dbus.adr,
s1_dat_i=>monitor_dbus.wdata,
s1_dat_o=>monitor_dbus.rdata,
m0_cyc_o=>ram_wb.cyc,
m0_stb_o=>ram_wb.stb,
m0_we_o=>ram_wb.we,
m0_sel_o=>ram_wb.sel,
m0_ack_i=>ram_wb.ack,
m0_adr_o=>ram_wb.adr,
m0_dat_o=>ram_wb.wdata,
m0_dat_i=>ram_wb.rdata,
m1_cyc_o=>wbm_cyc_o,
m1_stb_o=>wbm_stb_o,
m1_we_o=>wbm_we_o,
m1_sel_o=>wbm_sel_o,
m1_ack_i=>wbm_ack_i,
m1_adr_o=>wbm_adr_o,
m1_dat_o=>wbm_dat_o,
m1_dat_i=>wbm_dat_i,
m2_cyc_o=>timer_wb.cyc,
m2_stb_o=>timer_wb.stb,
m2_we_o=>timer_wb.we,
m2_sel_o=>timer_wb.sel,
m2_ack_i=>timer_wb.ack,
m2_adr_o=>timer_wb.adr,
m2_dat_o=>timer_wb.wdata,
m2_dat_i=>timer_wb.rdata,
m3_cyc_o=>coprocessor_wb.cyc,
m3_stb_o=>coprocessor_wb.stb,
m3_we_o=>coprocessor_wb.we,
m3_sel_o=>coprocessor_wb.sel,
m3_ack_i=>coprocessor_wb.ack,
m3_adr_o=>coprocessor_wb.adr,
m3_dat_o=>coprocessor_wb.wdata,
m3_dat_i=>coprocessor_wb.rdata
);
-- CPU
cpu_rst<=cpu_rst_i or rst_i;
-- Note: we connect the timer IRQ to 2 CPU channels to test
-- handling of simultaneously arriving interrupt requests.
cpu_irq<="00000"&coprocessor_irq&timer_elapsed&timer_elapsed;
gen_lxp32u: if not MODEL_LXP32C generate
lxp32u_top_inst: entity work.lxp32u_top(rtl)
generic map(
DBUS_RMW=>CPU_DBUS_RMW,
DIVIDER_EN=>true,
MUL_ARCH=>CPU_MUL_ARCH,
START_ADDR=>(others=>'0')
)
port map(
clk_i=>clk_i,
rst_i=>cpu_rst,
lli_re_o=>lli_re,
lli_adr_o=>lli_adr,
lli_dat_i=>lli_dat,
lli_busy_i=>lli_busy,
dbus_cyc_o=>cpu_dbus.cyc,
dbus_stb_o=>cpu_dbus.stb,
dbus_we_o=>cpu_dbus.we,
dbus_sel_o=>cpu_dbus.sel,
dbus_ack_i=>cpu_dbus.ack,
dbus_adr_o=>cpu_dbus.adr,
dbus_dat_o=>cpu_dbus.wdata,
dbus_dat_i=>cpu_dbus.rdata,
irq_i=>cpu_irq
);
end generate;
gen_lxp32c: if MODEL_LXP32C generate
lxp32c_top_inst: entity work.lxp32c_top(rtl)
generic map(
DBUS_RMW=>CPU_DBUS_RMW,
DIVIDER_EN=>true,
IBUS_BURST_SIZE=>16,
IBUS_PREFETCH_SIZE=>32,
MUL_ARCH=>CPU_MUL_ARCH,
START_ADDR=>(others=>'0')
)
port map(
clk_i=>clk_i,
rst_i=>cpu_rst,
ibus_cyc_o=>cpu_ibus.cyc,
ibus_stb_o=>cpu_ibus.stb,
ibus_cti_o=>cpu_ibus.cti,
ibus_bte_o=>cpu_ibus.bte,
ibus_ack_i=>cpu_ibus.ack,
ibus_adr_o=>cpu_ibus.adr,
ibus_dat_i=>cpu_ibus.dat,
dbus_cyc_o=>cpu_dbus.cyc,
dbus_stb_o=>cpu_dbus.stb,
dbus_we_o=>cpu_dbus.we,
dbus_sel_o=>cpu_dbus.sel,
dbus_ack_i=>cpu_dbus.ack,
dbus_adr_o=>cpu_dbus.adr,
dbus_dat_o=>cpu_dbus.wdata,
dbus_dat_i=>cpu_dbus.rdata,
irq_i=>cpu_irq
);
ibus_adapter_inst: entity work.ibus_adapter(rtl)
port map(
clk_i=>clk_i,
rst_i=>rst_i,
ibus_cyc_i=>cpu_ibus.cyc,
ibus_stb_i=>cpu_ibus.stb,
ibus_cti_i=>cpu_ibus.cti,
ibus_bte_i=>cpu_ibus.bte,
ibus_ack_o=>cpu_ibus.ack,
ibus_adr_i=>cpu_ibus.adr,
ibus_dat_o=>cpu_ibus.dat,
lli_re_o=>lli_re,
lli_adr_o=>lli_adr,
lli_dat_i=>lli_dat,
lli_busy_i=>lli_busy
);
end generate;
-- DBUS monitor
dbus_monitor_inst: entity work.dbus_monitor(rtl)
generic map(
THROTTLE=>THROTTLE_DBUS
)
port map(
clk_i=>clk_i,
rst_i=>rst_i,
wbs_cyc_i=>cpu_dbus.cyc,
wbs_stb_i=>cpu_dbus.stb,
wbs_we_i=>cpu_dbus.we,
wbs_sel_i=>cpu_dbus.sel,
wbs_ack_o=>cpu_dbus.ack,
wbs_adr_i=>cpu_dbus.adr,
wbs_dat_i=>cpu_dbus.wdata,
wbs_dat_o=>cpu_dbus.rdata,
wbm_cyc_o=>monitor_dbus.cyc,
wbm_stb_o=>monitor_dbus.stb,
wbm_we_o=>monitor_dbus.we,
wbm_sel_o=>monitor_dbus.sel,
wbm_ack_i=>monitor_dbus.ack,
wbm_adr_o=>monitor_dbus.adr,
wbm_dat_o=>monitor_dbus.wdata,
wbm_dat_i=>monitor_dbus.rdata
);
-- Program RAM
program_ram_inst: entity work.program_ram(rtl)
generic map(
THROTTLE=>THROTTLE_IBUS
)
port map(
clk_i=>clk_i,
rst_i=>rst_i,
wbs_cyc_i=>ram_wb.cyc,
wbs_stb_i=>ram_wb.stb,
wbs_we_i=>ram_wb.we,
wbs_sel_i=>ram_wb.sel,
wbs_ack_o=>ram_wb.ack,
wbs_adr_i=>ram_wb.adr,
wbs_dat_i=>ram_wb.wdata,
wbs_dat_o=>ram_wb.rdata,
lli_re_i=>lli_re,
lli_adr_i=>lli_adr,
lli_dat_o=>lli_dat,
lli_busy_o=>lli_busy
);
-- Timer
timer_inst: entity work.timer(rtl)
port map(
clk_i=>clk_i,
rst_i=>rst_i,
wbs_cyc_i=>timer_wb.cyc,
wbs_stb_i=>timer_wb.stb,
wbs_we_i=>timer_wb.we,
wbs_sel_i=>timer_wb.sel,
wbs_ack_o=>timer_wb.ack,
wbs_adr_i=>timer_wb.adr,
wbs_dat_i=>timer_wb.wdata,
wbs_dat_o=>timer_wb.rdata,
elapsed_o=>timer_elapsed
);
-- Coprocessor
coprocessor_inst: entity work.coprocessor(rtl)
port map(
clk_i=>clk_i,
rst_i=>rst_i,
wbs_cyc_i=>coprocessor_wb.cyc,
wbs_stb_i=>coprocessor_wb.stb,
wbs_we_i=>coprocessor_wb.we,
wbs_sel_i=>coprocessor_wb.sel,
wbs_ack_o=>coprocessor_wb.ack,
wbs_adr_i=>coprocessor_wb.adr,
wbs_dat_i=>coprocessor_wb.wdata,
wbs_dat_o=>coprocessor_wb.rdata,
irq_o=>coprocessor_irq
);
end architecture;
| mit | f0393ee3dde21316b080e834c62281d2 | 0.641894 | 2.30256 | false | false | false | false |
franz/pocl | examples/accel/rtl/platform/ffaccel_toplevel.vhdl | 2 | 41,324 | library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use work.tce_util.all;
use work.ffaccel_globals.all;
use work.ffaccel_imem_mau.all;
use work.ffaccel_toplevel_params.all;
entity ffaccel_toplevel is
generic (
axi_addr_width_g : integer := 17;
axi_id_width_g : integer := 12;
local_mem_addrw_g : integer := 10;
axi_offset_g : integer := 1136656384);
port (
clk : in std_logic;
rstx : in std_logic;
s_axi_awid : in std_logic_vector(axi_id_width_g-1 downto 0);
s_axi_awaddr : in std_logic_vector(axi_addr_width_g-1 downto 0);
s_axi_awlen : in std_logic_vector(7 downto 0);
s_axi_awsize : in std_logic_vector(2 downto 0);
s_axi_awburst : in std_logic_vector(1 downto 0);
s_axi_awvalid : in std_logic;
s_axi_awready : out std_logic;
s_axi_wdata : in std_logic_vector(31 downto 0);
s_axi_wstrb : in std_logic_vector(3 downto 0);
s_axi_wvalid : in std_logic;
s_axi_wready : out std_logic;
s_axi_bid : out std_logic_vector(axi_id_width_g-1 downto 0);
s_axi_bresp : out std_logic_vector(1 downto 0);
s_axi_bvalid : out std_logic;
s_axi_bready : in std_logic;
s_axi_arid : in std_logic_vector(axi_id_width_g-1 downto 0);
s_axi_araddr : in std_logic_vector(axi_addr_width_g-1 downto 0);
s_axi_arlen : in std_logic_vector(7 downto 0);
s_axi_arsize : in std_logic_vector(2 downto 0);
s_axi_arburst : in std_logic_vector(1 downto 0);
s_axi_arvalid : in std_logic;
s_axi_arready : out std_logic;
s_axi_rid : out std_logic_vector(axi_id_width_g-1 downto 0);
s_axi_rdata : out std_logic_vector(31 downto 0);
s_axi_rresp : out std_logic_vector(1 downto 0);
s_axi_rlast : out std_logic;
s_axi_rvalid : out std_logic;
s_axi_rready : in std_logic;
m_axi_awaddr : out std_logic_vector(31 downto 0);
m_axi_awvalid : out std_logic;
m_axi_awready : in std_logic;
m_axi_awprot : out std_logic_vector(2 downto 0);
m_axi_wvalid : out std_logic;
m_axi_wready : in std_logic;
m_axi_wdata : out std_logic_vector(31 downto 0);
m_axi_wstrb : out std_logic_vector(3 downto 0);
m_axi_bvalid : in std_logic;
m_axi_bready : out std_logic;
m_axi_arvalid : out std_logic;
m_axi_arready : in std_logic;
m_axi_araddr : out std_logic_vector(31 downto 0);
m_axi_arprot : out std_logic_vector(2 downto 0);
m_axi_rdata : in std_logic_vector(31 downto 0);
m_axi_rvalid : in std_logic;
m_axi_rready : out std_logic;
locked : out std_logic);
end ffaccel_toplevel;
architecture structural of ffaccel_toplevel is
signal core_busy_wire : std_logic;
signal core_imem_en_x_wire : std_logic;
signal core_imem_addr_wire : std_logic_vector(IMEMADDRWIDTH-1 downto 0);
signal core_imem_data_wire : std_logic_vector(IMEMWIDTHINMAUS*IMEMMAUWIDTH-1 downto 0);
signal core_fu_DATA_LSU_avalid_out_wire : std_logic_vector(0 downto 0);
signal core_fu_DATA_LSU_aready_in_wire : std_logic_vector(0 downto 0);
signal core_fu_DATA_LSU_aaddr_out_wire : std_logic_vector(fu_DATA_LSU_addrw_g-2-1 downto 0);
signal core_fu_DATA_LSU_awren_out_wire : std_logic_vector(0 downto 0);
signal core_fu_DATA_LSU_astrb_out_wire : std_logic_vector(3 downto 0);
signal core_fu_DATA_LSU_adata_out_wire : std_logic_vector(31 downto 0);
signal core_fu_DATA_LSU_rvalid_in_wire : std_logic_vector(0 downto 0);
signal core_fu_DATA_LSU_rready_out_wire : std_logic_vector(0 downto 0);
signal core_fu_DATA_LSU_rdata_in_wire : std_logic_vector(31 downto 0);
signal core_fu_PARAM_LSU_avalid_out_wire : std_logic_vector(0 downto 0);
signal core_fu_PARAM_LSU_aready_in_wire : std_logic_vector(0 downto 0);
signal core_fu_PARAM_LSU_aaddr_out_wire : std_logic_vector(fu_PARAM_LSU_addrw_g-2-1 downto 0);
signal core_fu_PARAM_LSU_awren_out_wire : std_logic_vector(0 downto 0);
signal core_fu_PARAM_LSU_astrb_out_wire : std_logic_vector(3 downto 0);
signal core_fu_PARAM_LSU_adata_out_wire : std_logic_vector(31 downto 0);
signal core_fu_PARAM_LSU_rvalid_in_wire : std_logic_vector(0 downto 0);
signal core_fu_PARAM_LSU_rready_out_wire : std_logic_vector(0 downto 0);
signal core_fu_PARAM_LSU_rdata_in_wire : std_logic_vector(31 downto 0);
signal core_fu_SP_LSU_avalid_out_wire : std_logic_vector(0 downto 0);
signal core_fu_SP_LSU_aready_in_wire : std_logic_vector(0 downto 0);
signal core_fu_SP_LSU_aaddr_out_wire : std_logic_vector(fu_SP_LSU_addrw_g-2-1 downto 0);
signal core_fu_SP_LSU_awren_out_wire : std_logic_vector(0 downto 0);
signal core_fu_SP_LSU_astrb_out_wire : std_logic_vector(3 downto 0);
signal core_fu_SP_LSU_adata_out_wire : std_logic_vector(31 downto 0);
signal core_fu_SP_LSU_rvalid_in_wire : std_logic_vector(0 downto 0);
signal core_fu_SP_LSU_rready_out_wire : std_logic_vector(0 downto 0);
signal core_fu_SP_LSU_rdata_in_wire : std_logic_vector(31 downto 0);
signal core_fu_AQL_FU_read_idx_out_wire : std_logic_vector(63 downto 0);
signal core_fu_AQL_FU_read_idx_clear_in_wire : std_logic_vector(0 downto 0);
signal core_db_tta_nreset_wire : std_logic;
signal core_db_lockcnt_wire : std_logic_vector(63 downto 0);
signal core_db_cyclecnt_wire : std_logic_vector(63 downto 0);
signal core_db_pc_wire : std_logic_vector(IMEMADDRWIDTH-1 downto 0);
signal core_db_lockrq_wire : std_logic;
signal imem_array_instance_0_addr_wire : std_logic_vector(11 downto 0);
signal imem_array_instance_0_dataout_wire : std_logic_vector(42 downto 0);
signal imem_array_instance_0_en_x_wire : std_logic;
signal onchip_mem_data_a_aaddr_in_wire : std_logic_vector(9 downto 0);
signal onchip_mem_data_a_adata_in_wire : std_logic_vector(31 downto 0);
signal onchip_mem_data_a_aready_out_wire : std_logic;
signal onchip_mem_data_a_astrb_in_wire : std_logic_vector(3 downto 0);
signal onchip_mem_data_a_avalid_in_wire : std_logic;
signal onchip_mem_data_a_awren_in_wire : std_logic;
signal onchip_mem_data_a_rdata_out_wire : std_logic_vector(31 downto 0);
signal onchip_mem_data_a_rready_in_wire : std_logic;
signal onchip_mem_data_a_rvalid_out_wire : std_logic;
signal onchip_mem_data_b_aaddr_in_wire : std_logic_vector(9 downto 0);
signal onchip_mem_data_b_adata_in_wire : std_logic_vector(31 downto 0);
signal onchip_mem_data_b_aready_out_wire : std_logic;
signal onchip_mem_data_b_astrb_in_wire : std_logic_vector(3 downto 0);
signal onchip_mem_data_b_avalid_in_wire : std_logic;
signal onchip_mem_data_b_awren_in_wire : std_logic;
signal onchip_mem_data_b_rdata_out_wire : std_logic_vector(31 downto 0);
signal onchip_mem_data_b_rready_in_wire : std_logic;
signal onchip_mem_data_b_rvalid_out_wire : std_logic;
signal onchip_mem_param_a_aaddr_in_wire : std_logic_vector(local_mem_addrw_g-1 downto 0);
signal onchip_mem_param_a_adata_in_wire : std_logic_vector(31 downto 0);
signal onchip_mem_param_a_aready_out_wire : std_logic;
signal onchip_mem_param_a_astrb_in_wire : std_logic_vector(3 downto 0);
signal onchip_mem_param_a_avalid_in_wire : std_logic;
signal onchip_mem_param_a_awren_in_wire : std_logic;
signal onchip_mem_param_a_rdata_out_wire : std_logic_vector(31 downto 0);
signal onchip_mem_param_a_rready_in_wire : std_logic;
signal onchip_mem_param_a_rvalid_out_wire : std_logic;
signal onchip_mem_param_b_aaddr_in_wire : std_logic_vector(local_mem_addrw_g-1 downto 0);
signal onchip_mem_param_b_adata_in_wire : std_logic_vector(31 downto 0);
signal onchip_mem_param_b_aready_out_wire : std_logic;
signal onchip_mem_param_b_astrb_in_wire : std_logic_vector(3 downto 0);
signal onchip_mem_param_b_avalid_in_wire : std_logic;
signal onchip_mem_param_b_awren_in_wire : std_logic;
signal onchip_mem_param_b_rdata_out_wire : std_logic_vector(31 downto 0);
signal onchip_mem_param_b_rready_in_wire : std_logic;
signal onchip_mem_param_b_rvalid_out_wire : std_logic;
signal onchip_mem_scratchpad_aaddr_in_wire : std_logic_vector(7 downto 0);
signal onchip_mem_scratchpad_adata_in_wire : std_logic_vector(31 downto 0);
signal onchip_mem_scratchpad_aready_out_wire : std_logic;
signal onchip_mem_scratchpad_astrb_in_wire : std_logic_vector(3 downto 0);
signal onchip_mem_scratchpad_avalid_in_wire : std_logic;
signal onchip_mem_scratchpad_awren_in_wire : std_logic;
signal onchip_mem_scratchpad_rdata_out_wire : std_logic_vector(31 downto 0);
signal onchip_mem_scratchpad_rready_in_wire : std_logic;
signal onchip_mem_scratchpad_rvalid_out_wire : std_logic;
signal tta_accel_0_core_db_pc_wire : std_logic_vector(11 downto 0);
signal tta_accel_0_core_db_lockcnt_wire : std_logic_vector(63 downto 0);
signal tta_accel_0_core_db_cyclecnt_wire : std_logic_vector(63 downto 0);
signal tta_accel_0_core_db_tta_nreset_wire : std_logic_vector(0 downto 0);
signal tta_accel_0_core_db_lockrq_wire : std_logic_vector(0 downto 0);
signal tta_accel_0_core_dmem_avalid_in_wire : std_logic_vector(0 downto 0);
signal tta_accel_0_core_dmem_aready_out_wire : std_logic_vector(0 downto 0);
signal tta_accel_0_core_dmem_aaddr_in_wire : std_logic_vector(9 downto 0);
signal tta_accel_0_core_dmem_awren_in_wire : std_logic_vector(0 downto 0);
signal tta_accel_0_core_dmem_astrb_in_wire : std_logic_vector(3 downto 0);
signal tta_accel_0_core_dmem_adata_in_wire : std_logic_vector(31 downto 0);
signal tta_accel_0_core_dmem_rvalid_out_wire : std_logic_vector(0 downto 0);
signal tta_accel_0_core_dmem_rready_in_wire : std_logic_vector(0 downto 0);
signal tta_accel_0_core_dmem_rdata_out_wire : std_logic_vector(31 downto 0);
signal tta_accel_0_data_a_avalid_out_wire : std_logic_vector(0 downto 0);
signal tta_accel_0_data_a_aready_in_wire : std_logic_vector(0 downto 0);
signal tta_accel_0_data_a_aaddr_out_wire : std_logic_vector(9 downto 0);
signal tta_accel_0_data_a_awren_out_wire : std_logic_vector(0 downto 0);
signal tta_accel_0_data_a_astrb_out_wire : std_logic_vector(3 downto 0);
signal tta_accel_0_data_a_adata_out_wire : std_logic_vector(31 downto 0);
signal tta_accel_0_data_a_rvalid_in_wire : std_logic_vector(0 downto 0);
signal tta_accel_0_data_a_rready_out_wire : std_logic_vector(0 downto 0);
signal tta_accel_0_data_a_rdata_in_wire : std_logic_vector(31 downto 0);
signal tta_accel_0_data_b_avalid_out_wire : std_logic_vector(0 downto 0);
signal tta_accel_0_data_b_aready_in_wire : std_logic_vector(0 downto 0);
signal tta_accel_0_data_b_aaddr_out_wire : std_logic_vector(9 downto 0);
signal tta_accel_0_data_b_awren_out_wire : std_logic_vector(0 downto 0);
signal tta_accel_0_data_b_astrb_out_wire : std_logic_vector(3 downto 0);
signal tta_accel_0_data_b_adata_out_wire : std_logic_vector(31 downto 0);
signal tta_accel_0_data_b_rvalid_in_wire : std_logic_vector(0 downto 0);
signal tta_accel_0_data_b_rready_out_wire : std_logic_vector(0 downto 0);
signal tta_accel_0_data_b_rdata_in_wire : std_logic_vector(31 downto 0);
signal tta_accel_0_core_pmem_avalid_in_wire : std_logic_vector(0 downto 0);
signal tta_accel_0_core_pmem_aready_out_wire : std_logic_vector(0 downto 0);
signal tta_accel_0_core_pmem_aaddr_in_wire : std_logic_vector(29 downto 0);
signal tta_accel_0_core_pmem_awren_in_wire : std_logic_vector(0 downto 0);
signal tta_accel_0_core_pmem_astrb_in_wire : std_logic_vector(3 downto 0);
signal tta_accel_0_core_pmem_adata_in_wire : std_logic_vector(31 downto 0);
signal tta_accel_0_core_pmem_rvalid_out_wire : std_logic_vector(0 downto 0);
signal tta_accel_0_core_pmem_rready_in_wire : std_logic_vector(0 downto 0);
signal tta_accel_0_core_pmem_rdata_out_wire : std_logic_vector(31 downto 0);
signal tta_accel_0_param_a_avalid_out_wire : std_logic_vector(0 downto 0);
signal tta_accel_0_param_a_aready_in_wire : std_logic_vector(0 downto 0);
signal tta_accel_0_param_a_aaddr_out_wire : std_logic_vector(local_mem_addrw_g-1 downto 0);
signal tta_accel_0_param_a_awren_out_wire : std_logic_vector(0 downto 0);
signal tta_accel_0_param_a_astrb_out_wire : std_logic_vector(3 downto 0);
signal tta_accel_0_param_a_adata_out_wire : std_logic_vector(31 downto 0);
signal tta_accel_0_param_a_rvalid_in_wire : std_logic_vector(0 downto 0);
signal tta_accel_0_param_a_rready_out_wire : std_logic_vector(0 downto 0);
signal tta_accel_0_param_a_rdata_in_wire : std_logic_vector(31 downto 0);
signal tta_accel_0_param_b_avalid_out_wire : std_logic_vector(0 downto 0);
signal tta_accel_0_param_b_aready_in_wire : std_logic_vector(0 downto 0);
signal tta_accel_0_param_b_aaddr_out_wire : std_logic_vector(local_mem_addrw_g-1 downto 0);
signal tta_accel_0_param_b_awren_out_wire : std_logic_vector(0 downto 0);
signal tta_accel_0_param_b_astrb_out_wire : std_logic_vector(3 downto 0);
signal tta_accel_0_param_b_adata_out_wire : std_logic_vector(31 downto 0);
signal tta_accel_0_param_b_rvalid_in_wire : std_logic_vector(0 downto 0);
signal tta_accel_0_param_b_rready_out_wire : std_logic_vector(0 downto 0);
signal tta_accel_0_param_b_rdata_in_wire : std_logic_vector(31 downto 0);
signal tta_accel_0_aql_read_idx_in_wire : std_logic_vector(63 downto 0);
signal tta_accel_0_aql_read_idx_clear_out_wire : std_logic_vector(0 downto 0);
component ffaccel
generic (
core_id : integer);
port (
clk : in std_logic;
rstx : in std_logic;
busy : in std_logic;
imem_en_x : out std_logic;
imem_addr : out std_logic_vector(IMEMADDRWIDTH-1 downto 0);
imem_data : in std_logic_vector(IMEMWIDTHINMAUS*IMEMMAUWIDTH-1 downto 0);
locked : out std_logic;
fu_DATA_LSU_avalid_out : out std_logic_vector(1-1 downto 0);
fu_DATA_LSU_aready_in : in std_logic_vector(1-1 downto 0);
fu_DATA_LSU_aaddr_out : out std_logic_vector(fu_DATA_LSU_addrw_g-2-1 downto 0);
fu_DATA_LSU_awren_out : out std_logic_vector(1-1 downto 0);
fu_DATA_LSU_astrb_out : out std_logic_vector(4-1 downto 0);
fu_DATA_LSU_adata_out : out std_logic_vector(32-1 downto 0);
fu_DATA_LSU_rvalid_in : in std_logic_vector(1-1 downto 0);
fu_DATA_LSU_rready_out : out std_logic_vector(1-1 downto 0);
fu_DATA_LSU_rdata_in : in std_logic_vector(32-1 downto 0);
fu_PARAM_LSU_avalid_out : out std_logic_vector(1-1 downto 0);
fu_PARAM_LSU_aready_in : in std_logic_vector(1-1 downto 0);
fu_PARAM_LSU_aaddr_out : out std_logic_vector(fu_PARAM_LSU_addrw_g-2-1 downto 0);
fu_PARAM_LSU_awren_out : out std_logic_vector(1-1 downto 0);
fu_PARAM_LSU_astrb_out : out std_logic_vector(4-1 downto 0);
fu_PARAM_LSU_adata_out : out std_logic_vector(32-1 downto 0);
fu_PARAM_LSU_rvalid_in : in std_logic_vector(1-1 downto 0);
fu_PARAM_LSU_rready_out : out std_logic_vector(1-1 downto 0);
fu_PARAM_LSU_rdata_in : in std_logic_vector(32-1 downto 0);
fu_SP_LSU_avalid_out : out std_logic_vector(1-1 downto 0);
fu_SP_LSU_aready_in : in std_logic_vector(1-1 downto 0);
fu_SP_LSU_aaddr_out : out std_logic_vector(fu_SP_LSU_addrw_g-2-1 downto 0);
fu_SP_LSU_awren_out : out std_logic_vector(1-1 downto 0);
fu_SP_LSU_astrb_out : out std_logic_vector(4-1 downto 0);
fu_SP_LSU_adata_out : out std_logic_vector(32-1 downto 0);
fu_SP_LSU_rvalid_in : in std_logic_vector(1-1 downto 0);
fu_SP_LSU_rready_out : out std_logic_vector(1-1 downto 0);
fu_SP_LSU_rdata_in : in std_logic_vector(32-1 downto 0);
fu_AQL_FU_read_idx_out : out std_logic_vector(64-1 downto 0);
fu_AQL_FU_read_idx_clear_in : in std_logic_vector(1-1 downto 0);
db_tta_nreset : in std_logic;
db_lockcnt : out std_logic_vector(64-1 downto 0);
db_cyclecnt : out std_logic_vector(64-1 downto 0);
db_pc : out std_logic_vector(IMEMADDRWIDTH-1 downto 0);
db_lockrq : in std_logic);
end component;
component tta_accel
generic (
core_count_g : integer;
axi_addr_width_g : integer;
axi_id_width_g : integer;
imem_data_width_g : integer;
imem_addr_width_g : integer;
bus_count_g : integer;
local_mem_addrw_g : integer;
sync_reset_g : integer;
axi_offset_g : integer;
full_debugger_g : integer;
dmem_data_width_g : integer;
dmem_addr_width_g : integer;
pmem_data_width_g : integer;
pmem_addr_width_g : integer);
port (
clk : in std_logic;
rstx : in std_logic;
s_axi_awid : in std_logic_vector(axi_id_width_g-1 downto 0);
s_axi_awaddr : in std_logic_vector(axi_addr_width_g-1 downto 0);
s_axi_awlen : in std_logic_vector(8-1 downto 0);
s_axi_awsize : in std_logic_vector(3-1 downto 0);
s_axi_awburst : in std_logic_vector(2-1 downto 0);
s_axi_awvalid : in std_logic;
s_axi_awready : out std_logic;
s_axi_wdata : in std_logic_vector(32-1 downto 0);
s_axi_wstrb : in std_logic_vector(4-1 downto 0);
s_axi_wvalid : in std_logic;
s_axi_wready : out std_logic;
s_axi_bid : out std_logic_vector(axi_id_width_g-1 downto 0);
s_axi_bresp : out std_logic_vector(2-1 downto 0);
s_axi_bvalid : out std_logic;
s_axi_bready : in std_logic;
s_axi_arid : in std_logic_vector(axi_id_width_g-1 downto 0);
s_axi_araddr : in std_logic_vector(axi_addr_width_g-1 downto 0);
s_axi_arlen : in std_logic_vector(8-1 downto 0);
s_axi_arsize : in std_logic_vector(3-1 downto 0);
s_axi_arburst : in std_logic_vector(2-1 downto 0);
s_axi_arvalid : in std_logic;
s_axi_arready : out std_logic;
s_axi_rid : out std_logic_vector(axi_id_width_g-1 downto 0);
s_axi_rdata : out std_logic_vector(32-1 downto 0);
s_axi_rresp : out std_logic_vector(2-1 downto 0);
s_axi_rlast : out std_logic;
s_axi_rvalid : out std_logic;
s_axi_rready : in std_logic;
m_axi_awaddr : out std_logic_vector(32-1 downto 0);
m_axi_awvalid : out std_logic;
m_axi_awready : in std_logic;
m_axi_awprot : out std_logic_vector(3-1 downto 0);
m_axi_wvalid : out std_logic;
m_axi_wready : in std_logic;
m_axi_wdata : out std_logic_vector(32-1 downto 0);
m_axi_wstrb : out std_logic_vector(4-1 downto 0);
m_axi_bvalid : in std_logic;
m_axi_bready : out std_logic;
m_axi_arvalid : out std_logic;
m_axi_arready : in std_logic;
m_axi_araddr : out std_logic_vector(32-1 downto 0);
m_axi_arprot : out std_logic_vector(3-1 downto 0);
m_axi_rdata : in std_logic_vector(32-1 downto 0);
m_axi_rvalid : in std_logic;
m_axi_rready : out std_logic;
core_db_pc : in std_logic_vector(12-1 downto 0);
core_db_lockcnt : in std_logic_vector(64-1 downto 0);
core_db_cyclecnt : in std_logic_vector(64-1 downto 0);
core_db_tta_nreset : out std_logic_vector(1-1 downto 0);
core_db_lockrq : out std_logic_vector(1-1 downto 0);
core_dmem_avalid_in : in std_logic_vector(1-1 downto 0);
core_dmem_aready_out : out std_logic_vector(1-1 downto 0);
core_dmem_aaddr_in : in std_logic_vector(10-1 downto 0);
core_dmem_awren_in : in std_logic_vector(1-1 downto 0);
core_dmem_astrb_in : in std_logic_vector(4-1 downto 0);
core_dmem_adata_in : in std_logic_vector(32-1 downto 0);
core_dmem_rvalid_out : out std_logic_vector(1-1 downto 0);
core_dmem_rready_in : in std_logic_vector(1-1 downto 0);
core_dmem_rdata_out : out std_logic_vector(32-1 downto 0);
data_a_avalid_out : out std_logic_vector(1-1 downto 0);
data_a_aready_in : in std_logic_vector(1-1 downto 0);
data_a_aaddr_out : out std_logic_vector(10-1 downto 0);
data_a_awren_out : out std_logic_vector(1-1 downto 0);
data_a_astrb_out : out std_logic_vector(4-1 downto 0);
data_a_adata_out : out std_logic_vector(32-1 downto 0);
data_a_rvalid_in : in std_logic_vector(1-1 downto 0);
data_a_rready_out : out std_logic_vector(1-1 downto 0);
data_a_rdata_in : in std_logic_vector(32-1 downto 0);
data_b_avalid_out : out std_logic_vector(1-1 downto 0);
data_b_aready_in : in std_logic_vector(1-1 downto 0);
data_b_aaddr_out : out std_logic_vector(10-1 downto 0);
data_b_awren_out : out std_logic_vector(1-1 downto 0);
data_b_astrb_out : out std_logic_vector(4-1 downto 0);
data_b_adata_out : out std_logic_vector(32-1 downto 0);
data_b_rvalid_in : in std_logic_vector(1-1 downto 0);
data_b_rready_out : out std_logic_vector(1-1 downto 0);
data_b_rdata_in : in std_logic_vector(32-1 downto 0);
core_pmem_avalid_in : in std_logic_vector(1-1 downto 0);
core_pmem_aready_out : out std_logic_vector(1-1 downto 0);
core_pmem_aaddr_in : in std_logic_vector(30-1 downto 0);
core_pmem_awren_in : in std_logic_vector(1-1 downto 0);
core_pmem_astrb_in : in std_logic_vector(4-1 downto 0);
core_pmem_adata_in : in std_logic_vector(32-1 downto 0);
core_pmem_rvalid_out : out std_logic_vector(1-1 downto 0);
core_pmem_rready_in : in std_logic_vector(1-1 downto 0);
core_pmem_rdata_out : out std_logic_vector(32-1 downto 0);
param_a_avalid_out : out std_logic_vector(1-1 downto 0);
param_a_aready_in : in std_logic_vector(1-1 downto 0);
param_a_aaddr_out : out std_logic_vector(local_mem_addrw_g-1 downto 0);
param_a_awren_out : out std_logic_vector(1-1 downto 0);
param_a_astrb_out : out std_logic_vector(4-1 downto 0);
param_a_adata_out : out std_logic_vector(32-1 downto 0);
param_a_rvalid_in : in std_logic_vector(1-1 downto 0);
param_a_rready_out : out std_logic_vector(1-1 downto 0);
param_a_rdata_in : in std_logic_vector(32-1 downto 0);
param_b_avalid_out : out std_logic_vector(1-1 downto 0);
param_b_aready_in : in std_logic_vector(1-1 downto 0);
param_b_aaddr_out : out std_logic_vector(local_mem_addrw_g-1 downto 0);
param_b_awren_out : out std_logic_vector(1-1 downto 0);
param_b_astrb_out : out std_logic_vector(4-1 downto 0);
param_b_adata_out : out std_logic_vector(32-1 downto 0);
param_b_rvalid_in : in std_logic_vector(1-1 downto 0);
param_b_rready_out : out std_logic_vector(1-1 downto 0);
param_b_rdata_in : in std_logic_vector(32-1 downto 0);
aql_read_idx_in : in std_logic_vector(64-1 downto 0);
aql_read_idx_clear_out : out std_logic_vector(1-1 downto 0));
end component;
component ffaccel_rom_array_comp
generic (
addrw : integer;
instrw : integer);
port (
clock : in std_logic;
addr : in std_logic_vector(addrw-1 downto 0);
dataout : out std_logic_vector(instrw-1 downto 0);
en_x : in std_logic);
end component;
component xilinx_dp_blockram
generic (
dataw_g : integer;
addrw_g : integer);
port (
a_aaddr_in : in std_logic_vector(addrw_g-1 downto 0);
a_adata_in : in std_logic_vector(dataw_g-1 downto 0);
a_aready_out : out std_logic;
a_astrb_in : in std_logic_vector((dataw_g+7)/8-1 downto 0);
a_avalid_in : in std_logic;
a_awren_in : in std_logic;
a_rdata_out : out std_logic_vector(dataw_g-1 downto 0);
a_rready_in : in std_logic;
a_rvalid_out : out std_logic;
b_aaddr_in : in std_logic_vector(addrw_g-1 downto 0);
b_adata_in : in std_logic_vector(dataw_g-1 downto 0);
b_aready_out : out std_logic;
b_astrb_in : in std_logic_vector((dataw_g+7)/8-1 downto 0);
b_avalid_in : in std_logic;
b_awren_in : in std_logic;
b_rdata_out : out std_logic_vector(dataw_g-1 downto 0);
b_rready_in : in std_logic;
b_rvalid_out : out std_logic;
clk : in std_logic;
rstx : in std_logic);
end component;
component xilinx_blockram
generic (
dataw_g : integer;
addrw_g : integer);
port (
aaddr_in : in std_logic_vector(addrw_g-1 downto 0);
adata_in : in std_logic_vector(dataw_g-1 downto 0);
aready_out : out std_logic;
astrb_in : in std_logic_vector((dataw_g+7)/8-1 downto 0);
avalid_in : in std_logic;
awren_in : in std_logic;
clk : in std_logic;
rdata_out : out std_logic_vector(dataw_g-1 downto 0);
rready_in : in std_logic;
rstx : in std_logic;
rvalid_out : out std_logic);
end component;
begin
core_busy_wire <= '0';
imem_array_instance_0_en_x_wire <= core_imem_en_x_wire;
imem_array_instance_0_addr_wire <= core_imem_addr_wire;
core_imem_data_wire <= imem_array_instance_0_dataout_wire;
tta_accel_0_core_dmem_avalid_in_wire <= core_fu_DATA_LSU_avalid_out_wire;
core_fu_DATA_LSU_aready_in_wire <= tta_accel_0_core_dmem_aready_out_wire;
tta_accel_0_core_dmem_aaddr_in_wire <= core_fu_DATA_LSU_aaddr_out_wire;
tta_accel_0_core_dmem_awren_in_wire <= core_fu_DATA_LSU_awren_out_wire;
tta_accel_0_core_dmem_astrb_in_wire <= core_fu_DATA_LSU_astrb_out_wire;
tta_accel_0_core_dmem_adata_in_wire <= core_fu_DATA_LSU_adata_out_wire;
core_fu_DATA_LSU_rvalid_in_wire <= tta_accel_0_core_dmem_rvalid_out_wire;
tta_accel_0_core_dmem_rready_in_wire <= core_fu_DATA_LSU_rready_out_wire;
core_fu_DATA_LSU_rdata_in_wire <= tta_accel_0_core_dmem_rdata_out_wire;
tta_accel_0_core_pmem_avalid_in_wire <= core_fu_PARAM_LSU_avalid_out_wire;
core_fu_PARAM_LSU_aready_in_wire <= tta_accel_0_core_pmem_aready_out_wire;
tta_accel_0_core_pmem_aaddr_in_wire <= core_fu_PARAM_LSU_aaddr_out_wire;
tta_accel_0_core_pmem_awren_in_wire <= core_fu_PARAM_LSU_awren_out_wire;
tta_accel_0_core_pmem_astrb_in_wire <= core_fu_PARAM_LSU_astrb_out_wire;
tta_accel_0_core_pmem_adata_in_wire <= core_fu_PARAM_LSU_adata_out_wire;
core_fu_PARAM_LSU_rvalid_in_wire <= tta_accel_0_core_pmem_rvalid_out_wire;
tta_accel_0_core_pmem_rready_in_wire <= core_fu_PARAM_LSU_rready_out_wire;
core_fu_PARAM_LSU_rdata_in_wire <= tta_accel_0_core_pmem_rdata_out_wire;
onchip_mem_scratchpad_avalid_in_wire <= core_fu_SP_LSU_avalid_out_wire(0);
core_fu_SP_LSU_aready_in_wire(0) <= onchip_mem_scratchpad_aready_out_wire;
onchip_mem_scratchpad_aaddr_in_wire <= core_fu_SP_LSU_aaddr_out_wire;
onchip_mem_scratchpad_awren_in_wire <= core_fu_SP_LSU_awren_out_wire(0);
onchip_mem_scratchpad_astrb_in_wire <= core_fu_SP_LSU_astrb_out_wire;
onchip_mem_scratchpad_adata_in_wire <= core_fu_SP_LSU_adata_out_wire;
core_fu_SP_LSU_rvalid_in_wire(0) <= onchip_mem_scratchpad_rvalid_out_wire;
onchip_mem_scratchpad_rready_in_wire <= core_fu_SP_LSU_rready_out_wire(0);
core_fu_SP_LSU_rdata_in_wire <= onchip_mem_scratchpad_rdata_out_wire;
tta_accel_0_aql_read_idx_in_wire <= core_fu_AQL_FU_read_idx_out_wire;
core_fu_AQL_FU_read_idx_clear_in_wire <= tta_accel_0_aql_read_idx_clear_out_wire;
core_db_tta_nreset_wire <= tta_accel_0_core_db_tta_nreset_wire(0);
tta_accel_0_core_db_lockcnt_wire <= core_db_lockcnt_wire;
tta_accel_0_core_db_cyclecnt_wire <= core_db_cyclecnt_wire;
tta_accel_0_core_db_pc_wire <= core_db_pc_wire;
core_db_lockrq_wire <= tta_accel_0_core_db_lockrq_wire(0);
onchip_mem_data_a_avalid_in_wire <= tta_accel_0_data_a_avalid_out_wire(0);
tta_accel_0_data_a_aready_in_wire(0) <= onchip_mem_data_a_aready_out_wire;
onchip_mem_data_a_aaddr_in_wire <= tta_accel_0_data_a_aaddr_out_wire;
onchip_mem_data_a_awren_in_wire <= tta_accel_0_data_a_awren_out_wire(0);
onchip_mem_data_a_astrb_in_wire <= tta_accel_0_data_a_astrb_out_wire;
onchip_mem_data_a_adata_in_wire <= tta_accel_0_data_a_adata_out_wire;
tta_accel_0_data_a_rvalid_in_wire(0) <= onchip_mem_data_a_rvalid_out_wire;
onchip_mem_data_a_rready_in_wire <= tta_accel_0_data_a_rready_out_wire(0);
tta_accel_0_data_a_rdata_in_wire <= onchip_mem_data_a_rdata_out_wire;
onchip_mem_data_b_avalid_in_wire <= tta_accel_0_data_b_avalid_out_wire(0);
tta_accel_0_data_b_aready_in_wire(0) <= onchip_mem_data_b_aready_out_wire;
onchip_mem_data_b_aaddr_in_wire <= tta_accel_0_data_b_aaddr_out_wire;
onchip_mem_data_b_awren_in_wire <= tta_accel_0_data_b_awren_out_wire(0);
onchip_mem_data_b_astrb_in_wire <= tta_accel_0_data_b_astrb_out_wire;
onchip_mem_data_b_adata_in_wire <= tta_accel_0_data_b_adata_out_wire;
tta_accel_0_data_b_rvalid_in_wire(0) <= onchip_mem_data_b_rvalid_out_wire;
onchip_mem_data_b_rready_in_wire <= tta_accel_0_data_b_rready_out_wire(0);
tta_accel_0_data_b_rdata_in_wire <= onchip_mem_data_b_rdata_out_wire;
onchip_mem_param_a_avalid_in_wire <= tta_accel_0_param_a_avalid_out_wire(0);
tta_accel_0_param_a_aready_in_wire(0) <= onchip_mem_param_a_aready_out_wire;
onchip_mem_param_a_aaddr_in_wire <= tta_accel_0_param_a_aaddr_out_wire;
onchip_mem_param_a_awren_in_wire <= tta_accel_0_param_a_awren_out_wire(0);
onchip_mem_param_a_astrb_in_wire <= tta_accel_0_param_a_astrb_out_wire;
onchip_mem_param_a_adata_in_wire <= tta_accel_0_param_a_adata_out_wire;
tta_accel_0_param_a_rvalid_in_wire(0) <= onchip_mem_param_a_rvalid_out_wire;
onchip_mem_param_a_rready_in_wire <= tta_accel_0_param_a_rready_out_wire(0);
tta_accel_0_param_a_rdata_in_wire <= onchip_mem_param_a_rdata_out_wire;
onchip_mem_param_b_avalid_in_wire <= tta_accel_0_param_b_avalid_out_wire(0);
tta_accel_0_param_b_aready_in_wire(0) <= onchip_mem_param_b_aready_out_wire;
onchip_mem_param_b_aaddr_in_wire <= tta_accel_0_param_b_aaddr_out_wire;
onchip_mem_param_b_awren_in_wire <= tta_accel_0_param_b_awren_out_wire(0);
onchip_mem_param_b_astrb_in_wire <= tta_accel_0_param_b_astrb_out_wire;
onchip_mem_param_b_adata_in_wire <= tta_accel_0_param_b_adata_out_wire;
tta_accel_0_param_b_rvalid_in_wire(0) <= onchip_mem_param_b_rvalid_out_wire;
onchip_mem_param_b_rready_in_wire <= tta_accel_0_param_b_rready_out_wire(0);
tta_accel_0_param_b_rdata_in_wire <= onchip_mem_param_b_rdata_out_wire;
core : ffaccel
generic map (
core_id => 0)
port map (
clk => clk,
rstx => rstx,
busy => core_busy_wire,
imem_en_x => core_imem_en_x_wire,
imem_addr => core_imem_addr_wire,
imem_data => core_imem_data_wire,
locked => locked,
fu_DATA_LSU_avalid_out => core_fu_DATA_LSU_avalid_out_wire,
fu_DATA_LSU_aready_in => core_fu_DATA_LSU_aready_in_wire,
fu_DATA_LSU_aaddr_out => core_fu_DATA_LSU_aaddr_out_wire,
fu_DATA_LSU_awren_out => core_fu_DATA_LSU_awren_out_wire,
fu_DATA_LSU_astrb_out => core_fu_DATA_LSU_astrb_out_wire,
fu_DATA_LSU_adata_out => core_fu_DATA_LSU_adata_out_wire,
fu_DATA_LSU_rvalid_in => core_fu_DATA_LSU_rvalid_in_wire,
fu_DATA_LSU_rready_out => core_fu_DATA_LSU_rready_out_wire,
fu_DATA_LSU_rdata_in => core_fu_DATA_LSU_rdata_in_wire,
fu_PARAM_LSU_avalid_out => core_fu_PARAM_LSU_avalid_out_wire,
fu_PARAM_LSU_aready_in => core_fu_PARAM_LSU_aready_in_wire,
fu_PARAM_LSU_aaddr_out => core_fu_PARAM_LSU_aaddr_out_wire,
fu_PARAM_LSU_awren_out => core_fu_PARAM_LSU_awren_out_wire,
fu_PARAM_LSU_astrb_out => core_fu_PARAM_LSU_astrb_out_wire,
fu_PARAM_LSU_adata_out => core_fu_PARAM_LSU_adata_out_wire,
fu_PARAM_LSU_rvalid_in => core_fu_PARAM_LSU_rvalid_in_wire,
fu_PARAM_LSU_rready_out => core_fu_PARAM_LSU_rready_out_wire,
fu_PARAM_LSU_rdata_in => core_fu_PARAM_LSU_rdata_in_wire,
fu_SP_LSU_avalid_out => core_fu_SP_LSU_avalid_out_wire,
fu_SP_LSU_aready_in => core_fu_SP_LSU_aready_in_wire,
fu_SP_LSU_aaddr_out => core_fu_SP_LSU_aaddr_out_wire,
fu_SP_LSU_awren_out => core_fu_SP_LSU_awren_out_wire,
fu_SP_LSU_astrb_out => core_fu_SP_LSU_astrb_out_wire,
fu_SP_LSU_adata_out => core_fu_SP_LSU_adata_out_wire,
fu_SP_LSU_rvalid_in => core_fu_SP_LSU_rvalid_in_wire,
fu_SP_LSU_rready_out => core_fu_SP_LSU_rready_out_wire,
fu_SP_LSU_rdata_in => core_fu_SP_LSU_rdata_in_wire,
fu_AQL_FU_read_idx_out => core_fu_AQL_FU_read_idx_out_wire,
fu_AQL_FU_read_idx_clear_in => core_fu_AQL_FU_read_idx_clear_in_wire,
db_tta_nreset => core_db_tta_nreset_wire,
db_lockcnt => core_db_lockcnt_wire,
db_cyclecnt => core_db_cyclecnt_wire,
db_pc => core_db_pc_wire,
db_lockrq => core_db_lockrq_wire);
tta_accel_0 : tta_accel
generic map (
core_count_g => 1,
axi_addr_width_g => axi_addr_width_g,
axi_id_width_g => axi_id_width_g,
imem_data_width_g => 43,
imem_addr_width_g => 12,
bus_count_g => 2,
local_mem_addrw_g => local_mem_addrw_g,
sync_reset_g => 0,
axi_offset_g => axi_offset_g,
full_debugger_g => 0,
dmem_data_width_g => 32,
dmem_addr_width_g => 10,
pmem_data_width_g => 32,
pmem_addr_width_g => 30)
port map (
clk => clk,
rstx => rstx,
s_axi_awid => s_axi_awid,
s_axi_awaddr => s_axi_awaddr,
s_axi_awlen => s_axi_awlen,
s_axi_awsize => s_axi_awsize,
s_axi_awburst => s_axi_awburst,
s_axi_awvalid => s_axi_awvalid,
s_axi_awready => s_axi_awready,
s_axi_wdata => s_axi_wdata,
s_axi_wstrb => s_axi_wstrb,
s_axi_wvalid => s_axi_wvalid,
s_axi_wready => s_axi_wready,
s_axi_bid => s_axi_bid,
s_axi_bresp => s_axi_bresp,
s_axi_bvalid => s_axi_bvalid,
s_axi_bready => s_axi_bready,
s_axi_arid => s_axi_arid,
s_axi_araddr => s_axi_araddr,
s_axi_arlen => s_axi_arlen,
s_axi_arsize => s_axi_arsize,
s_axi_arburst => s_axi_arburst,
s_axi_arvalid => s_axi_arvalid,
s_axi_arready => s_axi_arready,
s_axi_rid => s_axi_rid,
s_axi_rdata => s_axi_rdata,
s_axi_rresp => s_axi_rresp,
s_axi_rlast => s_axi_rlast,
s_axi_rvalid => s_axi_rvalid,
s_axi_rready => s_axi_rready,
m_axi_awaddr => m_axi_awaddr,
m_axi_awvalid => m_axi_awvalid,
m_axi_awready => m_axi_awready,
m_axi_awprot => m_axi_awprot,
m_axi_wvalid => m_axi_wvalid,
m_axi_wready => m_axi_wready,
m_axi_wdata => m_axi_wdata,
m_axi_wstrb => m_axi_wstrb,
m_axi_bvalid => m_axi_bvalid,
m_axi_bready => m_axi_bready,
m_axi_arvalid => m_axi_arvalid,
m_axi_arready => m_axi_arready,
m_axi_araddr => m_axi_araddr,
m_axi_arprot => m_axi_arprot,
m_axi_rdata => m_axi_rdata,
m_axi_rvalid => m_axi_rvalid,
m_axi_rready => m_axi_rready,
core_db_pc => tta_accel_0_core_db_pc_wire,
core_db_lockcnt => tta_accel_0_core_db_lockcnt_wire,
core_db_cyclecnt => tta_accel_0_core_db_cyclecnt_wire,
core_db_tta_nreset => tta_accel_0_core_db_tta_nreset_wire,
core_db_lockrq => tta_accel_0_core_db_lockrq_wire,
core_dmem_avalid_in => tta_accel_0_core_dmem_avalid_in_wire,
core_dmem_aready_out => tta_accel_0_core_dmem_aready_out_wire,
core_dmem_aaddr_in => tta_accel_0_core_dmem_aaddr_in_wire,
core_dmem_awren_in => tta_accel_0_core_dmem_awren_in_wire,
core_dmem_astrb_in => tta_accel_0_core_dmem_astrb_in_wire,
core_dmem_adata_in => tta_accel_0_core_dmem_adata_in_wire,
core_dmem_rvalid_out => tta_accel_0_core_dmem_rvalid_out_wire,
core_dmem_rready_in => tta_accel_0_core_dmem_rready_in_wire,
core_dmem_rdata_out => tta_accel_0_core_dmem_rdata_out_wire,
data_a_avalid_out => tta_accel_0_data_a_avalid_out_wire,
data_a_aready_in => tta_accel_0_data_a_aready_in_wire,
data_a_aaddr_out => tta_accel_0_data_a_aaddr_out_wire,
data_a_awren_out => tta_accel_0_data_a_awren_out_wire,
data_a_astrb_out => tta_accel_0_data_a_astrb_out_wire,
data_a_adata_out => tta_accel_0_data_a_adata_out_wire,
data_a_rvalid_in => tta_accel_0_data_a_rvalid_in_wire,
data_a_rready_out => tta_accel_0_data_a_rready_out_wire,
data_a_rdata_in => tta_accel_0_data_a_rdata_in_wire,
data_b_avalid_out => tta_accel_0_data_b_avalid_out_wire,
data_b_aready_in => tta_accel_0_data_b_aready_in_wire,
data_b_aaddr_out => tta_accel_0_data_b_aaddr_out_wire,
data_b_awren_out => tta_accel_0_data_b_awren_out_wire,
data_b_astrb_out => tta_accel_0_data_b_astrb_out_wire,
data_b_adata_out => tta_accel_0_data_b_adata_out_wire,
data_b_rvalid_in => tta_accel_0_data_b_rvalid_in_wire,
data_b_rready_out => tta_accel_0_data_b_rready_out_wire,
data_b_rdata_in => tta_accel_0_data_b_rdata_in_wire,
core_pmem_avalid_in => tta_accel_0_core_pmem_avalid_in_wire,
core_pmem_aready_out => tta_accel_0_core_pmem_aready_out_wire,
core_pmem_aaddr_in => tta_accel_0_core_pmem_aaddr_in_wire,
core_pmem_awren_in => tta_accel_0_core_pmem_awren_in_wire,
core_pmem_astrb_in => tta_accel_0_core_pmem_astrb_in_wire,
core_pmem_adata_in => tta_accel_0_core_pmem_adata_in_wire,
core_pmem_rvalid_out => tta_accel_0_core_pmem_rvalid_out_wire,
core_pmem_rready_in => tta_accel_0_core_pmem_rready_in_wire,
core_pmem_rdata_out => tta_accel_0_core_pmem_rdata_out_wire,
param_a_avalid_out => tta_accel_0_param_a_avalid_out_wire,
param_a_aready_in => tta_accel_0_param_a_aready_in_wire,
param_a_aaddr_out => tta_accel_0_param_a_aaddr_out_wire,
param_a_awren_out => tta_accel_0_param_a_awren_out_wire,
param_a_astrb_out => tta_accel_0_param_a_astrb_out_wire,
param_a_adata_out => tta_accel_0_param_a_adata_out_wire,
param_a_rvalid_in => tta_accel_0_param_a_rvalid_in_wire,
param_a_rready_out => tta_accel_0_param_a_rready_out_wire,
param_a_rdata_in => tta_accel_0_param_a_rdata_in_wire,
param_b_avalid_out => tta_accel_0_param_b_avalid_out_wire,
param_b_aready_in => tta_accel_0_param_b_aready_in_wire,
param_b_aaddr_out => tta_accel_0_param_b_aaddr_out_wire,
param_b_awren_out => tta_accel_0_param_b_awren_out_wire,
param_b_astrb_out => tta_accel_0_param_b_astrb_out_wire,
param_b_adata_out => tta_accel_0_param_b_adata_out_wire,
param_b_rvalid_in => tta_accel_0_param_b_rvalid_in_wire,
param_b_rready_out => tta_accel_0_param_b_rready_out_wire,
param_b_rdata_in => tta_accel_0_param_b_rdata_in_wire,
aql_read_idx_in => tta_accel_0_aql_read_idx_in_wire,
aql_read_idx_clear_out => tta_accel_0_aql_read_idx_clear_out_wire);
imem_array_instance_0 : ffaccel_rom_array_comp
generic map (
addrw => IMEMADDRWIDTH,
instrw => IMEMMAUWIDTH*IMEMWIDTHINMAUS)
port map (
clock => clk,
addr => imem_array_instance_0_addr_wire,
dataout => imem_array_instance_0_dataout_wire,
en_x => imem_array_instance_0_en_x_wire);
onchip_mem_data : xilinx_dp_blockram
generic map (
dataw_g => 32,
addrw_g => 10)
port map (
a_aaddr_in => onchip_mem_data_a_aaddr_in_wire,
a_adata_in => onchip_mem_data_a_adata_in_wire,
a_aready_out => onchip_mem_data_a_aready_out_wire,
a_astrb_in => onchip_mem_data_a_astrb_in_wire,
a_avalid_in => onchip_mem_data_a_avalid_in_wire,
a_awren_in => onchip_mem_data_a_awren_in_wire,
a_rdata_out => onchip_mem_data_a_rdata_out_wire,
a_rready_in => onchip_mem_data_a_rready_in_wire,
a_rvalid_out => onchip_mem_data_a_rvalid_out_wire,
b_aaddr_in => onchip_mem_data_b_aaddr_in_wire,
b_adata_in => onchip_mem_data_b_adata_in_wire,
b_aready_out => onchip_mem_data_b_aready_out_wire,
b_astrb_in => onchip_mem_data_b_astrb_in_wire,
b_avalid_in => onchip_mem_data_b_avalid_in_wire,
b_awren_in => onchip_mem_data_b_awren_in_wire,
b_rdata_out => onchip_mem_data_b_rdata_out_wire,
b_rready_in => onchip_mem_data_b_rready_in_wire,
b_rvalid_out => onchip_mem_data_b_rvalid_out_wire,
clk => clk,
rstx => rstx);
onchip_mem_param : xilinx_dp_blockram
generic map (
dataw_g => 32,
addrw_g => local_mem_addrw_g)
port map (
a_aaddr_in => onchip_mem_param_a_aaddr_in_wire,
a_adata_in => onchip_mem_param_a_adata_in_wire,
a_aready_out => onchip_mem_param_a_aready_out_wire,
a_astrb_in => onchip_mem_param_a_astrb_in_wire,
a_avalid_in => onchip_mem_param_a_avalid_in_wire,
a_awren_in => onchip_mem_param_a_awren_in_wire,
a_rdata_out => onchip_mem_param_a_rdata_out_wire,
a_rready_in => onchip_mem_param_a_rready_in_wire,
a_rvalid_out => onchip_mem_param_a_rvalid_out_wire,
b_aaddr_in => onchip_mem_param_b_aaddr_in_wire,
b_adata_in => onchip_mem_param_b_adata_in_wire,
b_aready_out => onchip_mem_param_b_aready_out_wire,
b_astrb_in => onchip_mem_param_b_astrb_in_wire,
b_avalid_in => onchip_mem_param_b_avalid_in_wire,
b_awren_in => onchip_mem_param_b_awren_in_wire,
b_rdata_out => onchip_mem_param_b_rdata_out_wire,
b_rready_in => onchip_mem_param_b_rready_in_wire,
b_rvalid_out => onchip_mem_param_b_rvalid_out_wire,
clk => clk,
rstx => rstx);
onchip_mem_scratchpad : xilinx_blockram
generic map (
dataw_g => 32,
addrw_g => 8)
port map (
aaddr_in => onchip_mem_scratchpad_aaddr_in_wire,
adata_in => onchip_mem_scratchpad_adata_in_wire,
aready_out => onchip_mem_scratchpad_aready_out_wire,
astrb_in => onchip_mem_scratchpad_astrb_in_wire,
avalid_in => onchip_mem_scratchpad_avalid_in_wire,
awren_in => onchip_mem_scratchpad_awren_in_wire,
clk => clk,
rdata_out => onchip_mem_scratchpad_rdata_out_wire,
rready_in => onchip_mem_scratchpad_rready_in_wire,
rstx => rstx,
rvalid_out => onchip_mem_scratchpad_rvalid_out_wire);
end structural;
| mit | 99685cb0adc46c8b543a7d89d10c5090 | 0.664916 | 2.706221 | false | false | false | false |
michaelfivez/ascon_hardware_implementation | ascon12864_unrolled6/Kernel/OutputGenerator.vhd | 1 | 5,097 | -------------------------------------------------------------------------------
--! @project Unrolled (6) hardware implementation of Asconv1286
--! @author Michael Fivez
--! @license This project is released under the GNU Public License.
--! The license and distribution terms for this file may be
--! found in the file LICENSE in this distribution or at
--! http://www.gnu.org/licenses/gpl-3.0.txt
--! @note This is an hardware implementation made for my graduation thesis
--! at the KULeuven, in the COSIC department (year 2015-2016)
--! The thesis is titled 'Energy efficient hardware implementations of CAESAR submissions',
--! and can be found on the COSIC website (www.esat.kuleuven.be/cosic/publications)
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity OutputGenerator is
port(
In0 : in std_logic_vector(63 downto 0);
DataIn : in std_logic_vector(63 downto 0);
Size : in std_logic_vector(2 downto 0);
Activate : in std_logic;
Out0 : out std_logic_vector(63 downto 0);
DataOut : out std_logic_vector(63 downto 0));
end entity OutputGenerator;
architecture structural of OutputGenerator is
constant ALLZERO : std_logic_vector(63 downto 0) := (others => '0');
signal Temp0,Temp1,Temp2 : std_logic_vector(63 downto 0);
begin
Gen: process(In0,DataIn,Size,Activate,Temp0,Temp1,Temp2) is
-- Truncator0&1
procedure doTruncate0 ( -- Truncate block 0 and 1 together
signal Input : in std_logic_vector(63 downto 0);
signal Size : in std_logic_vector(2 downto 0);
signal Activate : in std_logic;
signal Output : out std_logic_vector(63 downto 0)) is
variable ActSize : std_logic_vector(3 downto 0);
begin
ActSize(3) := Activate;
ActSize(2 downto 0) := Size;
-- if inactive it lets everything trough, if active it lets the first blocksize bits trough
logic: case ActSize is
when "1001" =>
Output(63 downto 56) <= Input(63 downto 56);
Output(55) <= '1';
Output(54 downto 0) <= ALLZERO(54 downto 0);
when "1010" =>
Output(63 downto 48) <= Input(63 downto 48);
Output(47) <= '1';
Output(46 downto 0) <= ALLZERO(46 downto 0);
when "1011" =>
Output(63 downto 40) <= Input(63 downto 40);
Output(39) <= '1';
Output(38 downto 0) <= ALLZERO(38 downto 0);
when "1100" =>
Output(63 downto 32) <= Input(63 downto 32);
Output(31) <= '1';
Output(30 downto 0) <= ALLZERO(30 downto 0);
when "1101" =>
Output(63 downto 24) <= Input(63 downto 24);
Output(23) <= '1';
Output(22 downto 0) <= ALLZERO(22 downto 0);
when "1110" =>
Output(63 downto 16) <= Input(63 downto 16);
Output(15) <= '1';
Output(14 downto 0) <= ALLZERO(14 downto 0);
when "1111" =>
Output(63 downto 8) <= Input(63 downto 8);
Output(7) <= '1';
Output(6 downto 0) <= ALLZERO(6 downto 0);
when others => -- deactivate or blocksize max or invalid input (cas 0xxxx or 10000)
Output <= Input;
end case logic;
end procedure doTruncate0;
-- Truncator2
procedure doTruncate2 ( -- Truncate block 0 and 1 together
signal Input : in std_logic_vector(63 downto 0);
signal Size : in std_logic_vector(2 downto 0);
signal Activate : in std_logic;
signal Output : out std_logic_vector(63 downto 0)) is
variable ActSize : std_logic_vector(3 downto 0);
begin
ActSize(3) := Activate;
ActSize(2 downto 0) := Size;
-- if inactive it lets everything trough, if active it blocks the first blocksize bits
logic: case ActSize is
when "1000" =>
Output <= ALLZERO;
when "1001" =>
Output(63 downto 56) <= ALLZERO(63 downto 56);
Output(55 downto 0) <= Input(55 downto 0);
when "1010" =>
Output(63 downto 48) <= ALLZERO(63 downto 48);
Output(47 downto 0) <= Input(47 downto 0);
when "1011" =>
Output(63 downto 40) <= ALLZERO(63 downto 40);
Output(39 downto 0) <= Input(39 downto 0);
when "1100" =>
Output(63 downto 32) <= ALLZERO(63 downto 32);
Output(31 downto 0) <= Input(31 downto 0);
when "1101" =>
Output(63 downto 24) <= ALLZERO(63 downto 24);
Output(23 downto 0) <= Input(23 downto 0);
when "1110" =>
Output(63 downto 16) <= ALLZERO(63 downto 16);
Output(15 downto 0) <= Input(15 downto 0);
when "1111" =>
Output(63 downto 8) <= ALLZERO(63 downto 8);
Output(7 downto 0) <= Input(7 downto 0);
when others => -- deactivate or blocksize max or invalid input (cas 0xxxx or 10000)
Output <= Input;
end case logic;
end procedure doTruncate2;
begin
-- DataOut
DataOut <= In0 xor DataIn;
-- Stateupdate
doTruncate0(DataIn,Size,Activate,Temp0);
Temp1 <= In0;
doTruncate2(Temp1,Size,Activate,Temp2);
Out0 <= Temp0 xor Temp2;
end process Gen;
end architecture structural;
| gpl-3.0 | 8a8618e1f7db722e5da7e19e703c4ae9 | 0.606828 | 3.382216 | false | false | false | false |
impedimentToProgress/UCI-BlueChip | AttackFiles/Attacks/privEsc/lib/gaisler/ddr/ddr2sp32a.vhd | 2 | 30,825 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: ddr2sp32a
-- File: ddr2sp32a.vhd
-- Author: Nils-Johan Wessman - Gaisler Research
-- Description: 32-bit DDR2 memory controller with asych AHB interface
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
library gaisler;
use grlib.devices.all;
use gaisler.memctrl.all;
library techmap;
use techmap.gencomp.all;
entity ddr2sp32a is
generic (
memtech : integer := 0;
hindex : integer := 0;
haddr : integer := 0;
hmask : integer := 16#f00#;
ioaddr : integer := 16#000#;
iomask : integer := 16#fff#;
MHz : integer := 100;
col : integer := 9;
Mbyte : integer := 8;
fast : integer := 0;
pwron : integer := 0;
oepol : integer := 0;
readdly : integer := 1;
odten : integer := 0
);
port (
rst : in std_ulogic;
clk_ddr : in std_ulogic;
clk_ahb : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
sdi : in sdctrl_in_type;
sdo : out sdctrl_out_type
);
end;
architecture rtl of ddr2sp32a is
constant REVISION : integer := 0;
constant CMD_PRE : std_logic_vector(2 downto 0) := "010";
constant CMD_REF : std_logic_vector(2 downto 0) := "100";
constant CMD_LMR : std_logic_vector(2 downto 0) := "110";
constant CMD_EMR : std_logic_vector(2 downto 0) := "111";
constant odtvalue : std_logic_vector(1 downto 0) := conv_std_logic_vector(odten, 2);
constant abuf : integer := 6;
constant hconfig : ahb_config_type := (
0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_DDR2SP, 0, REVISION, 0),
4 => ahb_membar(haddr, '1', '1', hmask),
5 => ahb_iobar(ioaddr, iomask),
others => zero32);
type mcycletype is (midle, active, ext, leadout);
type ahb_state_type is (midle, rhold, dread, dwrite, whold1, whold2);
type sdcycletype is (act1, act2, act3, rd1, rd2, rd3, rd4, rd5, rd6, rd7, rd8,
wr0, wr1, wr2, wr3, wr4a, wr4b, wr4, wr5, sidle, ioreg1, ioreg2);
type icycletype is (iidle, pre, ref1, ref2, emode23, emode, lmode, emodeocd, finish);
-- sdram configuration register
type sdram_cfg_type is record
command : std_logic_vector(2 downto 0);
csize : std_logic_vector(1 downto 0);
bsize : std_logic_vector(2 downto 0);
trcd : std_ulogic; -- tCD : 2/3 clock cycles
trfc : std_logic_vector(4 downto 0);
trp : std_ulogic; -- precharge to activate: 2/3 clock cycles
refresh : std_logic_vector(11 downto 0);
renable : std_ulogic;
dllrst : std_ulogic;
refon : std_ulogic;
cke : std_ulogic;
cal_en : std_logic_vector(7 downto 0);
cal_inc : std_logic_vector(7 downto 0);
cal_rst : std_logic;
readdly : std_logic_vector(1 downto 0);
twr : std_logic_vector(4 downto 0);
emr : std_logic_vector(1 downto 0); -- selects EM register
ocd : std_ulogic; -- enable/disable ocd
end record;
type access_param is record
haddr : std_logic_vector(31 downto 0);
size : std_logic_vector(1 downto 0);
hwrite : std_ulogic;
hio : std_ulogic;
end record;
-- local registers
type ahb_reg_type is record
hready : std_ulogic;
hsel : std_ulogic;
hio : std_ulogic;
startsd : std_ulogic;
write : std_logic_vector(1 downto 0);
state : ahb_state_type;
haddr : std_logic_vector(31 downto 0);
hrdata : std_logic_vector(31 downto 0);
hwdata : std_logic_vector(31 downto 0);
hwrite : std_ulogic;
htrans : std_logic_vector(1 downto 0);
hresp : std_logic_vector(1 downto 0);
raddr : std_logic_vector(abuf-1 downto 0);
size : std_logic_vector(1 downto 0);
acc : access_param;
sync : std_logic_vector(2 downto 1);
startsd_ack : std_logic;
end record;
type ddr_reg_type is record
startsd : std_ulogic;
startsdold : std_ulogic;
hready : std_ulogic;
bdrive : std_ulogic;
qdrive : std_ulogic;
nbdrive : std_ulogic;
mstate : mcycletype;
sdstate : sdcycletype;
cmstate : mcycletype;
istate : icycletype;
trfc : std_logic_vector(4 downto 0);
refresh : std_logic_vector(11 downto 0);
sdcsn : std_logic_vector(1 downto 0);
sdwen : std_ulogic;
rasn : std_ulogic;
casn : std_ulogic;
dqm : std_logic_vector(7 downto 0);
address : std_logic_vector(15 downto 2); -- memory address
ba : std_logic_vector(1 downto 0);
waddr : std_logic_vector(abuf-1 downto 0);
waddr_d : std_logic_vector(abuf-1 downto 0); -- Same as waddr but delayed to compensate for pipelined output data
cfg : sdram_cfg_type;
hrdata : std_logic_vector(63 downto 0);
readdly : std_logic_vector(1 downto 0); -- added read latency
newcom : std_logic_vector(1 downto 0); -- start sec. read/write
wdata : std_logic_vector(63 downto 0);
initnopdly : std_logic_vector(7 downto 0); -- 400 ns delay
sync : std_logic;
odt : std_logic_vector(1 downto 0);
end record;
signal vcc : std_ulogic;
signal r, ri : ddr_reg_type;
signal ra, rai : ahb_reg_type;
signal rbdrive, ribdrive : std_logic_vector(31 downto 0);
signal rdata, wdata : std_logic_vector(63 downto 0);
signal ddr_rst : std_logic;
signal ddr_rst_gen : std_logic_vector(3 downto 0);
attribute syn_preserve : boolean;
attribute syn_preserve of rbdrive : signal is true;
begin
vcc <= '1';
ddr_rst <= (ddr_rst_gen(3) and ddr_rst_gen(2) and ddr_rst_gen(1) and rst); -- Reset signal in DDR clock domain
ahb_ctrl : process(rst, ahbsi, r, ra, rdata)
variable v : ahb_reg_type; -- local variables for registers
variable startsd : std_ulogic;
variable dout : std_logic_vector(31 downto 0);
variable ready : std_logic;
begin
v := ra; v.hresp := HRESP_OKAY; v.write := "00";
if ra.raddr(0) = '0' then v.hrdata := rdata(63 downto 32);
else v.hrdata := rdata(31 downto 0); end if;
-- Sync ------------------------------------------------
v.sync(1) := r.startsdold; v.sync(2) := ra.sync(1);
ready := ra.startsd_ack xor ra.sync(2);
--------------------------------------------------------
if ((ahbsi.hready and ahbsi.hsel(hindex)) = '1') then
v.htrans := ahbsi.htrans; v.haddr := ahbsi.haddr;
v.size := ahbsi.hsize(1 downto 0); v.hwrite := ahbsi.hwrite;
if ahbsi.htrans(1) = '1' then
v.hio := ahbsi.hmbsel(1);
v.hsel := '1'; v.hready := '0';
end if;
end if;
if ahbsi.hready = '1' then v.hsel := ahbsi.hsel(hindex); end if;
case ra.state is
when midle =>
if ((v.hsel and v.htrans(1)) = '1') then
if v.hwrite = '0' then
v.state := rhold; v.startsd := not ra.startsd;
else
v.state := dwrite; v.hready := '1';
v.write(0) := not v.haddr(2); v.write(1) := v.haddr(2);
end if;
end if;
v.raddr := ra.haddr(7 downto 2);
if ahbsi.hready = '1' then
v.acc := (v.haddr, v.size, v.hwrite, v.hio);
end if;
when rhold =>
v.raddr := ra.haddr(7 downto 2);
if ready = '1' then
v.state := dread; v.hready := '1'; v.raddr := ra.raddr + 1;
end if;
when dread =>
v.raddr := ra.raddr + 1; v.hready := '1';
if ((v.hsel and v.htrans(1) and v.htrans(0)) = '0')
or (ra.raddr(2 downto 0) = "000") then
v.state := midle; v.hready := '0';
v.startsd_ack := ra.startsd;
end if;
v.acc := (v.haddr, v.size, v.hwrite, v.hio);
when dwrite =>
v.raddr := ra.haddr(7 downto 2); v.hready := '1';
v.write(0) := not v.haddr(2); v.write(1) := v.haddr(2);
if ((v.hsel and v.htrans(1) and v.htrans(0)) = '0')
or (ra.haddr(4 downto 2) = "111") then
v.startsd := not ra.startsd; v.state := whold1;
v.write := "00"; v.hready := '0';
end if;
when whold1 =>
v.state := whold2;
when whold2 =>
if ready = '1' then
v.state := midle; v.acc := (v.haddr, v.size, v.hwrite, v.hio);
v.startsd_ack := ra.startsd;
end if;
end case;
v.hwdata := ahbsi.hwdata;
if (ahbsi.hready and ahbsi.hsel(hindex) ) = '1' then
if ahbsi.htrans(1) = '0' then v.hready := '1'; end if;
end if;
dout := ra.hrdata(31 downto 0);
if rst = '0' then
v.hsel := '0';
v.hready := '1';
v.state := midle;
v.startsd := '0';
v.startsd_ack := '0';
v.hio := '0';
end if;
rai <= v;
ahbso.hready <= ra.hready;
ahbso.hresp <= ra.hresp;
ahbso.hrdata <= dout;
ahbso.hcache <= not ra.hio;
end process;
ddr_ctrl : process(ddr_rst, r, ra, sdi, rbdrive, wdata)
variable v : ddr_reg_type; -- local variables for registers
variable startsd : std_ulogic;
variable dqm : std_logic_vector(7 downto 0);
variable raddr : std_logic_vector(13 downto 0);
variable adec : std_ulogic;
variable rams : std_logic_vector(1 downto 0);
variable ba : std_logic_vector(1 downto 0);
variable haddr : std_logic_vector(31 downto 0);
variable hsize : std_logic_vector(1 downto 0);
variable hwrite : std_ulogic;
variable htrans : std_logic_vector(1 downto 0);
variable hready : std_ulogic;
variable vbdrive : std_logic_vector(31 downto 0);
variable bdrive : std_ulogic;
variable writecfg : std_ulogic;
variable regsd1 : std_logic_vector(31 downto 0); -- data from registers
variable regsd2 : std_logic_vector(31 downto 0); -- data from registers
variable regsd3 : std_logic_vector(31 downto 0); -- data from registers
begin
-- Variable default settings to avoid latches
v := r; v.hready := '0'; writecfg := '0'; vbdrive := rbdrive;
v.hrdata := sdi.data(63 downto 0); v.qdrive :='0';
v.cfg.cal_en := (others => '0'); v.cfg.cal_inc := (others => '0');
v.cfg.cal_rst := '0';
v.wdata := wdata; -- pipeline output data
regsd1 := (others => '0');
regsd1(31 downto 15) := r.cfg.refon & r.cfg.ocd & r.cfg.emr & '0' & r.cfg.trcd &
r.cfg.bsize & r.cfg.csize & r.cfg.command &
r.cfg.dllrst & r.cfg.renable & r.cfg.cke;
regsd1(11 downto 0) := r.cfg.refresh;
regsd2 := (others => '0');
regsd2(8 downto 0) := conv_std_logic_vector(MHz, 9);
regsd2(14 downto 12) := conv_std_logic_vector(2, 3);
regsd3 := (others => '0');
regsd3(17 downto 16) := r.cfg.readdly;
regsd3(22 downto 18) := r.cfg.trfc;
regsd3(27 downto 23) := r.cfg.twr;
regsd3(28) := r.cfg.trp;
-- generate DQM from address and write size
case ra.acc.size is
when "00" =>
case ra.acc.haddr(2 downto 0) is
when "000" => dqm := "01111111";
when "001" => dqm := "10111111";
when "010" => dqm := "11011111";
when "011" => dqm := "11101111";
when "100" => dqm := "11110111";
when "101" => dqm := "11111011";
when "110" => dqm := "11111101";
when others => dqm := "11111110";
end case;
when "01" =>
case ra.acc.haddr(2 downto 1) is
when "00" => dqm := "00111111";
when "01" => dqm := "11001111";
when "10" => dqm := "11110011";
when others => dqm := "11111100";
end case;
when others => dqm := "00000000";
end case;
-- Sync ------------------------------------------
v.sync := ra.startsd; v.startsd := r.sync;
--------------------------------------------------
--v.startsd := ra.startsd;
---- main FSM
--
-- case r.mstate is
-- when midle =>
-- if r.startsd = '1' then
-- if (r.sdstate = sidle) and (r.cfg.command = "000")
-- and (r.cmstate = midle) then
-- startsd := '1'; v.mstate := active;
-- end if;
-- end if;
-- when others => null;
-- end case;
startsd := r.startsd xor r.startsdold;
-- generate row and column address size
haddr := ra.acc.haddr;
haddr(31 downto 20) := haddr(31 downto 20) and not conv_std_logic_vector(hmask, 12);
case r.cfg.csize is
when "00" => raddr := haddr(24 downto 11);
when "01" => raddr := haddr(25 downto 12);
when "10" => raddr := haddr(26 downto 13);
when others => raddr := haddr(27 downto 14);
end case;
-- generate bank address
ba := genmux(r.cfg.bsize, haddr(29 downto 22)) &
genmux(r.cfg.bsize, haddr(28 downto 21));
-- generate chip select
adec := genmux(r.cfg.bsize, haddr(30 downto 23));
rams := adec & not adec;
-- sdram access FSM
if r.trfc /= "00000" then v.trfc := r.trfc - 1; end if;
case r.sdstate is
when sidle =>
if (startsd = '1') and (r.cfg.command = "000") and (r.cmstate = midle)
and (r.istate = finish) then
v.address := raddr; v.ba := ba;
if ra.acc.hio = '0' then
v.sdcsn := not rams(1 downto 0); v.rasn := '0'; v.sdstate := act1;
else v.sdstate := ioreg1; end if;
end if;
v.waddr := ra.acc.haddr(7 downto 2);
when act1 =>
v.rasn := '1'; v.trfc := r.cfg.trfc;
if r.cfg.trcd = '1' then v.sdstate := act2;
else v.sdstate := act3;
end if;
--v.waddr := ra.acc.haddr(7 downto 2);
v.waddr := ra.acc.haddr(7 downto 4) & '0' & ra.acc.haddr(2);
v.waddr_d := ra.acc.haddr(7 downto 4) & '0' & ra.acc.haddr(2);
when act2 =>
v.sdstate := act3;
when act3 =>
v.casn := '0';
--v.address := ra.acc.haddr(14 downto 12) & '0' & ra.acc.haddr(11 downto 3) & '0';
v.address := ra.acc.haddr(14 downto 12) & '0' & ra.acc.haddr(11 downto 4) & "00";
v.hready := ra.acc.hwrite;
if ra.acc.hwrite = '1' then
v.sdstate := wr0;
v.sdwen := '0';
v.waddr := r.waddr + 2; v.waddr(0) := '0';
v.trfc := r.cfg.twr;
else v.sdstate := rd1; end if;
v.newcom(0) := '0';
if (ra.acc.haddr(4) = '1' or ra.raddr(2 downto 0) < "100") then v.newcom(1) := '1';
else v.newcom(1) := '0'; end if;
when wr0 =>
v.address(4) := not ra.acc.haddr(4); -- set start address for new write command
v.casn := '1'; v.sdwen := '1'; v.bdrive := '0'; v.qdrive := '1';
if r.waddr_d = ra.acc.haddr(7 downto 2) then
v.dqm := dqm;
v.waddr_d := r.waddr_d + 2; v.waddr_d(0) := '0';
v.waddr := r.waddr + 2;
v.sdstate := wr1;
if (r.waddr_d /= ra.raddr) then v.hready := '1';
if r.waddr_d(0) = '1' then v.dqm(7 downto 4) := (others => '1'); end if;
else
if r.waddr_d(0) = '0' then v.dqm(3 downto 0) := (others => '1');
else v.dqm(7 downto 4) := (others => '1'); end if;
end if;
else
v.newcom(0) := '1'; -- start new command
v.waddr_d := r.waddr_d + 2;
v.waddr := r.waddr + 2;
v.dqm := (others => '1');
end if;
if r.newcom(1 downto 0) = "01" then -- start new write command
v.newcom(1) := '1'; -- new command done
v.sdwen := '0'; v.casn := '0';
v.trfc := r.cfg.twr;
end if;
when wr1 =>
v.sdwen := '1'; v.casn := '1'; v.qdrive := '1';
v.waddr_d := r.waddr_d + 2; v.dqm(7 downto 4) := (others => '0');
v.waddr := r.waddr + 2;
if r.newcom(1) = '0' then -- start new write command
v.newcom(1) := '1'; -- new command done
v.sdwen := '0'; v.casn := '0';
v.trfc := r.cfg.twr;
end if;
if (r.waddr_d <= ra.raddr) and (r.waddr_d(5 downto 1) /= "00000") and (r.hready = '1')
then
v.hready := '1';
if (r.waddr_d = ra.raddr) and (r.waddr_d /= "000000") and (r.waddr_d(0) = '0') then
v.dqm(3 downto 0) := (others => '1');
end if;
else
v.sdstate := wr2;
v.dqm := (others => '1');
v.startsdold := r.startsd;
end if;
when wr2 =>
v.sdstate := wr3; v.qdrive := '1';
when wr3 =>
v.sdstate := wr4a; v.qdrive := '1';
when wr4a =>
v.bdrive := '1'; v.qdrive := '1';
if r.trfc = "00000" then -- wait to not violate TWR timing
v.sdstate := wr4b;
end if;
when wr4b =>
v.bdrive := '1';
v.rasn := '0'; v.sdwen := '0'; v.sdstate := wr4; v.qdrive := '1'; -- precharge
when wr4 =>
v.sdcsn := "11"; v.rasn := '1'; v.sdwen := '1'; v.qdrive := '0';
v.sdstate := wr5;
when wr5 =>
v.sdstate := sidle;
when rd1 =>
v.address(4) := not ra.acc.haddr(4); -- Set address for next read command
v.casn := '1'; v.sdstate := rd7;
when rd7 =>
v.casn := '1'; v.sdstate := rd8;
v.readdly := r.cfg.readdly;
if ra.acc.haddr(4) = '0' then -- start new read command if needed.
v.casn := '0';
end if;
when rd8 => -- (CL = 3)
v.casn := '1';
if r.readdly = "00" then -- add read delay
v.sdstate := rd2;
else
v.readdly := r.readdly - 1;
end if;
when rd2 =>
v.casn := '1'; v.sdstate := rd3;
when rd3 =>
if fast = 0 then v.startsdold := r.startsd; end if;
v.sdstate := rd4; v.hready := '1'; v.casn := '1';
if v.hready = '1' then v.waddr := r.waddr + 2; end if;
when rd4 =>
v.hready := '1'; v.casn := '1';
if (r.sdcsn = "11") or (r.waddr(2 downto 1) = "11") then
v.dqm := (others => '1');
if fast /= 0 then v.startsdold := r.startsd; end if;
if (r.sdcsn /= "11") then
v.rasn := '0'; v.sdwen := '0'; v.sdstate := rd5; -- precharge
else
if r.cfg.trp = '1' then v.sdstate := rd6;
else v.sdstate := sidle; end if;
end if;
end if;
if v.hready = '1' then v.waddr := r.waddr + 2; end if;
when rd5 =>
if r.cfg.trp = '1' then v.sdstate := rd6;
else v.sdstate := sidle; end if;
v.sdcsn := (others => '1'); v.rasn := '1'; v.sdwen := '1';
v.dqm := (others => '1');
when rd6 =>
v.sdstate := sidle; v.dqm := (others => '1');
v.sdcsn := (others => '1'); v.rasn := '1'; v.sdwen := '1';
when ioreg1 =>
if r.waddr(1) = '0' then
v.hrdata := regsd1 & regsd2;
else
v.hrdata := regsd3 & regsd3;
end if;
v.sdstate := ioreg2;
if ra.acc.hwrite = '0' then v.hready := '1'; end if;
when ioreg2 =>
writecfg := ra.acc.hwrite; v.startsdold := r.startsd;
v.sdstate := sidle;
when others =>
v.sdstate := sidle;
end case;
-- sdram commands
case r.cmstate is
when midle =>
if r.sdstate = sidle then
case r.cfg.command is
when CMD_PRE => -- precharge
v.sdcsn := (others => '0'); v.rasn := '0'; v.sdwen := '0';
v.address(12) := '1'; v.cmstate := active;
when CMD_REF => -- auto-refresh
v.sdcsn := (others => '0'); v.rasn := '0'; v.casn := '0';
v.cmstate := active;
when CMD_EMR => -- load-ext-mode-reg
v.sdcsn := (others => '0'); v.rasn := '0'; v.casn := '0';
v.sdwen := '0'; v.cmstate := active; v.ba := r.cfg.emr; --v.ba select EM register
--v.address := "0000"&r.cfg.ocd&r.cfg.ocd&r.cfg.ocd&"0000000";
if r.cfg.emr = "01" then
v.address := "0000"&r.cfg.ocd&r.cfg.ocd&r.cfg.ocd
& odtvalue(1)&"000"&odtvalue(0)&"00";
else
v.address := "0000"&r.cfg.ocd&r.cfg.ocd&r.cfg.ocd&"0000000";
end if;
when CMD_LMR => -- load-mode-reg
v.sdcsn := (others => '0'); v.rasn := '0'; v.casn := '0';
v.sdwen := '0'; v.cmstate := active; v.ba := "00";
v.address := "00010" & r.cfg.dllrst & "0" & "01" & "10010"; -- CAS = 3 WR = 3 burts = 4
when others => null;
end case;
end if;
when active =>
v.sdcsn := (others => '1'); v.rasn := '1'; v.casn := '1';
v.sdwen := '1'; v.cfg.command := "000";
v.cmstate := leadout; v.trfc := r.cfg.trfc;
when others =>
if r.trfc = "00000" then v.cmstate := midle; end if;
end case;
-- sdram init
case r.istate is
when iidle =>
if r.cfg.renable = '1' then
v.cfg.cke := '1'; v.cfg.dllrst := '1';
v.ba := "00"; v.cfg.ocd := '0'; v.cfg.emr := "10"; -- EMR(2)
if r.cfg.cke = '1' then
if r.initnopdly = "00000000" then -- 400 ns of NOP and CKE
v.istate := pre; v.cfg.command := CMD_PRE;
else
v.initnopdly := r.initnopdly - 1;
end if;
end if;
end if;
when pre =>
if r.cfg.command = "000" then
v.cfg.command := "11" & r.cfg.dllrst; -- CMD_LMR/CMD_EMR
if r.cfg.dllrst = '1' then v.istate := emode23; else v.istate := lmode; end if;
end if;
when emode23 =>
if r.cfg.command = "000" then
if r.cfg.emr = "11" then
v.cfg.emr := "01"; -- (EMR(1))
v.istate := emode; v.cfg.command := CMD_EMR;
else
v.cfg.emr := "11"; v.cfg.command := CMD_EMR; -- EMR(3)
end if;
end if;
when emode =>
if r.cfg.command = "000" then
v.istate := lmode; v.cfg.command := CMD_LMR;
end if;
when lmode =>
if r.cfg.command = "000" then
if r.cfg.dllrst = '1' then
if r.refresh(9 downto 8) = "00" then -- > 200 clocks delay
v.cfg.command := CMD_PRE; v.istate := ref1;
end if;
else
v.istate := emodeocd;
v.cfg.ocd := '1'; v.cfg.command := CMD_EMR;
end if;
end if;
when ref1 =>
if r.cfg.command = "000" then
v.cfg.command := CMD_REF; v.cfg.dllrst := '0'; v.istate := ref2;
end if;
when ref2 =>
if r.cfg.command = "000" then
v.cfg.command := CMD_REF; v.istate := pre;
end if;
when emodeocd =>
if r.cfg.command = "000" then
if r.cfg.ocd = '0' then -- Exit OCD
v.istate := finish;
v.cfg.refon := '1'; v.cfg.renable := '0';
else -- Default OCD
v.cfg.ocd := '0';
v.cfg.command := CMD_EMR;
end if;
end if;
v.cfg.cal_rst := '1'; -- reset data bit dely
when others =>
if odten /= 0 then v.odt := (others => '1'); end if;
if r.cfg.renable = '1' then
v.istate := iidle; v.cfg.dllrst := '1';
v.initnopdly := (others => '1');
v.odt := (others => '0');
end if;
end case;
---- second part of main fsm
--
-- case r.mstate is
-- when active =>
-- if v.hready = '1' then
-- v.mstate := midle;
-- end if;
-- when others => null;
-- end case;
-- sdram refresh counter
if ((r.cfg.refon = '1') and (r.istate = finish)) or (r.cfg.dllrst = '1') then
v.refresh := r.refresh - 1;
if (v.refresh(11) and not r.refresh(11)) = '1' then
v.refresh := r.cfg.refresh;
if r.cfg.dllrst = '0' then v.cfg.command := "100"; end if;
end if;
end if;
-- AHB register access
if (ra.acc.hio and ra.acc.hwrite and writecfg) = '1' then
if r.waddr(1 downto 0) = "00" then
v.cfg.refresh := wdata(11+32 downto 0+32);
v.cfg.cke := wdata(15+32);
v.cfg.renable := wdata(16+32);
v.cfg.dllrst := wdata(17+32);
v.cfg.command := wdata(20+32 downto 18+32);
v.cfg.csize := wdata(22+32 downto 21+32);
v.cfg.bsize := wdata(25+32 downto 23+32);
v.cfg.trcd := wdata(26+32);
v.cfg.emr := wdata(29+32 downto 28+32);
v.cfg.ocd := wdata(30+32);
v.cfg.refon := wdata(31+32);
elsif r.waddr(1 downto 0) = "10" then
v.cfg.cal_en := wdata( 7+32 downto 0+32);
v.cfg.cal_inc := wdata(15+32 downto 8+32);
v.cfg.readdly := wdata(17+32 downto 16+32);
v.cfg.trfc := wdata(22+32 downto 18+32);
v.cfg.twr := wdata(27+32 downto 23+32);
v.cfg.trp := wdata(28+32);
v.cfg.cal_rst := wdata(31+32);
end if;
end if;
v.nbdrive := not v.bdrive;
if oepol = 1 then bdrive := r.nbdrive; vbdrive := (others => v.nbdrive);
else bdrive := r.bdrive; vbdrive := (others => v.bdrive);end if;
-- reset
if ddr_rst = '0' then
v.sdstate := sidle;
v.mstate := midle;
v.istate := finish;
v.cmstate := midle;
v.cfg.command := "000";
v.cfg.csize := conv_std_logic_vector(col-9, 2);
v.cfg.bsize := conv_std_logic_vector(log2(Mbyte/8), 3);
v.cfg.refon := '0';
v.cfg.trfc := conv_std_logic_vector(75*MHz/1000-2, 5);
v.cfg.refresh := conv_std_logic_vector(7800*MHz/1000, 12);
v.cfg.twr := conv_std_logic_vector((15)*MHz/1000+3, 5);
v.refresh := (others => '0');
v.dqm := (others => '1');
v.sdwen := '1';
v.rasn := '1';
v.casn := '1';
v.hready := '0';
v.startsd := '0';
v.startsdold := '0';
v.cfg.dllrst := '0';
v.cfg.cke := '0';
v.cfg.ocd := '0';
v.cfg.readdly := conv_std_logic_vector(readdly, 2);
v.initnopdly := (others => '1');
if MHz > 130 then v.cfg.trcd := '1'; else v.cfg.trcd := '0'; end if;
if MHz > 130 then v.cfg.trp := '1'; else v.cfg.trp := '0'; end if;
if pwron = 1 then v.cfg.renable := '1';
else v.cfg.renable := '0'; end if;
v.odt := (others => '0');
end if;
ri <= v;
ribdrive <= vbdrive;
end process;
sdo.sdcke <= (others => r.cfg.cke);
ahbso.hconfig <= hconfig;
ahbso.hirq <= (others => '0');
ahbso.hindex <= hindex;
ahbregs : process(clk_ahb) begin
if rising_edge(clk_ahb) then
ra <= rai;
end if;
end process;
ddrregs : process(clk_ddr, rst, ddr_rst) begin
if rising_edge(clk_ddr) then
r <= ri; rbdrive <= ribdrive;
ddr_rst_gen <= ddr_rst_gen(2 downto 0) & '1';
end if;
if (rst = '0') then
ddr_rst_gen <= "0000";
end if;
if (ddr_rst = '0') then
r.sdcsn <= (others => '1'); r.bdrive <= '1'; r.nbdrive <= '0';
if oepol = 0 then rbdrive <= (others => '1');
else rbdrive <= (others => '0'); end if;
r.cfg.cke <= '0';
end if;
end process;
sdo.address <= '0' & ri.address;
sdo.ba <= ri.ba;
sdo.bdrive <= r.nbdrive when oepol = 1 else r.bdrive;
sdo.qdrive <= not (ri.qdrive or r.nbdrive);
sdo.vbdrive <= rbdrive;
sdo.sdcsn <= ri.sdcsn;
sdo.sdwen <= ri.sdwen;
sdo.dqm <= "11111111" & r.dqm;
sdo.rasn <= ri.rasn;
sdo.casn <= ri.casn;
--sdo.data <= zero32 & zero32 & wdata;
sdo.data <= zero32 & zero32 & r.wdata;
sdo.cal_en <= r.cfg.cal_en;
sdo.cal_inc <= r.cfg.cal_inc;
sdo.cal_rst <= r.cfg.cal_rst;
sdo.odt <= r.odt;
read_buff : syncram_2p
generic map (tech => memtech, abits => 5, dbits => 64, sepclk => 1, wrfst => 0)
port map ( rclk => clk_ahb, renable => vcc, raddress => rai.raddr(5 downto 1),
dataout => rdata, wclk => clk_ddr, write => ri.hready,
waddress => r.waddr(5 downto 1), datain => ri.hrdata);
write_buff1 : syncram_2p
generic map (tech => memtech, abits => 5, dbits => 32, sepclk => 1, wrfst => 0)
port map ( rclk => clk_ddr, renable => vcc, raddress => r.waddr(5 downto 1),
dataout => wdata(63 downto 32), wclk => clk_ahb, write => ra.write(0),
waddress => ra.haddr(7 downto 3), datain => ahbsi.hwdata);
write_buff2 : syncram_2p
generic map (tech => memtech, abits => 5, dbits => 32, sepclk => 1, wrfst => 0)
port map ( rclk => clk_ddr, renable => vcc, raddress => r.waddr(5 downto 1),
dataout => wdata(31 downto 0), wclk => clk_ahb, write => ra.write(1),
waddress => ra.haddr(7 downto 3), datain => ahbsi.hwdata);
-- pragma translate_off
bootmsg : report_version
generic map (
msg1 => "ddr2sp" & tost(hindex) & ": 32-bit DDR2 controller rev " &
tost(REVISION) & ", " & tost(Mbyte) & " Mbyte, " & tost(MHz) &
" MHz DDR clock");
-- pragma translate_on
end;
| mit | 48b0c5f94901f808f6b6bef9e429ddfa | 0.498913 | 3.30563 | false | false | false | false |
impedimentToProgress/UCI-BlueChip | AttackFiles/Attacks/privEsc/lib/eth/core/greth_rx.vhd | 2 | 10,381 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: greth_rx
-- File: greth_rx.vhd
-- Author: Marko Isomaki
-- Description: Ethernet receiver
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.stdlib.all;
library eth;
use eth.grethpkg.all;
entity greth_rx is
generic(
nsync : integer range 1 to 2 := 2;
rmii : integer range 0 to 1 := 0);
port(
rst : in std_ulogic;
clk : in std_ulogic;
rxi : in host_rx_type;
rxo : out rx_host_type
);
end entity;
architecture rtl of greth_rx is
constant maxsize : integer := 1518;
constant minsize : integer := 64;
--receiver types
type rx_state_type is (idle, wait_sfd, data1, data2, errorst, report_status,
wait_report, check_crc, discard_packet);
type rx_reg_type is record
er : std_ulogic;
en : std_ulogic;
rxd : std_logic_vector(3 downto 0);
rxdp : std_logic_vector(3 downto 0);
crc : std_logic_vector(31 downto 0);
sync_start : std_ulogic;
gotframe : std_ulogic;
start : std_ulogic;
write : std_ulogic;
done : std_ulogic;
odd_nibble : std_ulogic;
lentype : std_logic_vector(15 downto 0);
ltfound : std_ulogic;
byte_count : std_logic_vector(10 downto 0);
data : std_logic_vector(31 downto 0);
dataout : std_logic_vector(31 downto 0);
rx_state : rx_state_type;
status : std_logic_vector(3 downto 0);
write_ack : std_logic_vector(nsync-1 downto 0);
done_ack : std_logic_vector(nsync downto 0);
rxen : std_logic_vector(1 downto 0);
got4b : std_ulogic;
--rmii
enold : std_ulogic;
act : std_ulogic;
dv : std_ulogic;
cnt : std_logic_vector(3 downto 0);
rxd2 : std_logic_vector(1 downto 0);
speed : std_logic_vector(1 downto 0);
zero : std_ulogic;
end record;
--receiver signals
signal r, rin : rx_reg_type;
signal rxrst : std_ulogic;
signal vcc : std_ulogic;
attribute sync_set_reset : string;
attribute sync_set_reset of rxrst : signal is "true";
begin
vcc <= '1';
rx_rst : eth_rstgen
port map(rst, clk, vcc, rxrst, open);
rx : process(rxrst, r, rxi) is
variable v : rx_reg_type;
variable index : integer range 0 to 3;
variable crc_en : std_ulogic;
variable write_req : std_ulogic;
variable write_ack : std_ulogic;
variable done_ack : std_ulogic;
variable er : std_ulogic;
variable dv : std_ulogic;
variable act : std_ulogic;
variable rxd : std_logic_vector(3 downto 0);
begin
v := r; v.rxd := rxi.rxd(3 downto 0);
if rmii = 0 then
v.en := rxi.rx_dv;
else
v.en := rxi.rx_crs;
end if;
v.er := rxi.rx_er; write_req := '0'; crc_en := '0';
index := conv_integer(r.byte_count(1 downto 0));
--synchronization
v.rxen(1) := r.rxen(0); v.rxen(0) := rxi.enable;
v.write_ack(0) := rxi.writeack;
v.done_ack(0) := rxi.doneack;
if nsync = 2 then
v.write_ack(1) := r.write_ack(0);
v.done_ack(1) := r.done_ack(0);
end if;
write_ack := not (r.write xor r.write_ack(nsync-1));
done_ack := not (r.done xor r.done_ack(nsync-1));
--rmii/mii
if rmii = 0 then
er := r.er; dv := r.en; act := r.en; rxd := r.rxd;
else
--sync
v.speed(1) := r.speed(0); v.speed(0) := rxi.speed;
rxd := r.rxd(1 downto 0) & r.rxd2;
if r.cnt = "0000" then
v.cnt := "1001";
else
v.cnt := r.cnt - 1;
end if;
if v.cnt = "0000" then
v.zero := '1';
else
v.zero := '0';
end if;
act := r.act; er := '0';
if r.speed(1) = '0' then
if r.zero = '1' then
v.enold := r.en;
dv := r.en and r.dv;
v.dv := r.act and not r.dv;
if r.dv = '0' then
v.rxd2 := r.rxd(1 downto 0);
end if;
if (r.enold or r.en) = '0' then
v.act := '0';
end if;
else
dv := '0';
end if;
else
v.enold := r.en;
dv := r.en and r.dv;
v.dv := r.act and not r.dv;
v.rxd2 := r.rxd(1 downto 0);
if (r.enold or r.en) = '0' then
v.act := '0';
end if;
end if;
end if;
if (r.en and not r.act) = '1' then
if (rxd = "0101") and (r.speed(1) or
(not r.speed(1) and r.zero)) = '1' then
v.act := '1'; v.dv := '0';
end if;
end if;
if (dv = '1') then
v.rxdp := rxd;
end if;
--fsm
case r.rx_state is
when idle =>
v.gotframe := '0'; v.status := (others => '0'); v.got4b := '0';
v.byte_count := (others => '0'); v.odd_nibble := '0';
v.ltfound := '0';
if (dv and r.rxen(1)) = '1' then
v.rx_state := wait_sfd;
elsif dv = '1' then v.rx_state := discard_packet; end if;
when discard_packet =>
if act = '0' then v.rx_state := idle; end if;
when wait_sfd =>
if act = '0' then v.rx_state := idle;
elsif (rxd = "1101") and (dv = '1') and (r.rxdp = "0101") then
v.rx_state := data1; v.sync_start := not r.sync_start;
end if;
v.start := '0'; v.crc := (others => '1');
if er = '1' then v.status(2) := '1'; end if;
when data1 =>
if (act and dv) = '1' then
crc_en := '1';
v.odd_nibble := not r.odd_nibble; v.rx_state := data2;
case index is
when 0 => v.data(27 downto 24) := rxd;
when 1 => v.data(19 downto 16) := rxd;
when 2 => v.data(11 downto 8) := rxd;
when 3 => v.data(3 downto 0) := rxd;
end case;
elsif act = '0' then
v.rx_state := check_crc;
end if;
if (r.byte_count(1 downto 0) = "00" and (r.start and act and dv) = '1') then
write_req := '1';
end if;
if er = '1' then v.status(2) := '1'; end if;
if conv_integer(r.byte_count) > maxsize then
v.rx_state := errorst; v.status(1) := '1';
v.byte_count := r.byte_count - 4;
end if;
v.got4b := v.byte_count(2) or r.got4b;
when data2 =>
if (act and dv) = '1' then
crc_en := '1';
v.odd_nibble := not r.odd_nibble; v.rx_state := data1;
v.byte_count := r.byte_count + 1; v.start := '1';
case index is
when 0 => v.data(31 downto 28) := rxd;
when 1 => v.data(23 downto 20) := rxd;
when 2 => v.data(15 downto 12) := rxd;
when 3 => v.data(7 downto 4) := rxd;
end case;
elsif act = '0' then
v.rx_state := check_crc;
end if;
if er = '1' then v.status(2) := '1'; end if;
v.got4b := v.byte_count(2) or r.got4b;
when check_crc =>
if r.crc /= X"C704DD7B" then
if r.odd_nibble = '1' then v.status(0) := '1';
else v.status(2) := '1'; end if;
end if;
if write_ack = '1' then
if r.got4b = '1' then
v.byte_count := r.byte_count - 4;
else
v.byte_count := (others => '0');
end if;
v.rx_state := report_status;
if conv_integer(r.byte_count) < minsize then
v.rx_state := wait_report; v.done := not r.done;
end if;
end if;
when errorst =>
if act = '0' then
v.rx_state := wait_report; v.done := not r.done;
v.gotframe := '1';
end if;
when report_status =>
v.done := not r.done; v.rx_state := wait_report;
v.gotframe := '1';
when wait_report =>
if done_ack = '1' then
if act = '1' then
v.rx_state := discard_packet;
else
v.rx_state := idle;
end if;
end if;
when others => null;
end case;
--write to fifo
if write_req = '1' then
if (r.status(3) or not write_ack) = '1' then
v.status(3) := '1';
else
v.dataout := r.data; v.write := not r.write;
end if;
if (r.byte_count(4 downto 2) = "100") and (r.ltfound = '0') then
v.lentype := r.data(31 downto 16) + 14; v.ltfound := '1';
end if;
end if;
if rxi.writeack = '1' then
if rxi.writeok = '0' then v.status(3) := '1'; end if;
end if;
--crc generation
if crc_en = '1' then
v.crc := calccrc(rxd, r.crc);
end if;
if rxrst = '0' then
v.rx_state := idle; v.write := '0'; v.done := '0'; v.sync_start := '0';
v.done_ack := (others => '0');
v.gotframe := '0'; v.write_ack := (others => '0');
if rmii = 1 then
v.dv := '0'; v.cnt := (others => '0'); v.zero := '0';
end if;
end if;
rin <= v;
rxo.dataout <= r.dataout;
rxo.start <= r.sync_start;
rxo.done <= r.done;
rxo.write <= r.write;
rxo.status <= r.status;
rxo.gotframe <= r.gotframe;
rxo.byte_count <= r.byte_count;
rxo.lentype <= r.lentype;
end process;
rxregs : process(clk) is
begin
if rising_edge(clk) then r <= rin; end if;
end process;
end architecture;
| mit | 01b29180fdca20de772f650ff1604024 | 0.498603 | 3.221912 | false | false | false | false |
impedimentToProgress/UCI-BlueChip | VhdlParser/test/ddrsp64a.vhd | 1 | 38,151 | library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
library gaisler;
use grlib.devices.all;
use gaisler.memctrl.all;
library techmap;
use techmap.gencomp.all;
entity ddrsp64a is
generic (
memtech : integer := 0;
hindex : integer := 3;
haddr : integer := 1024;
hmask : integer := 3072;
ioaddr : integer := 1;
iomask : integer := 4095;
MHz : integer := 90;
col : integer := 9;
Mbyte : integer := 256;
fast : integer := 0;
pwron : integer := 1;
oepol : integer := 0
);
port (
rst : in std_ulogic;
clk_ddr : in std_ulogic;
clk_ahb : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
sdi : in sdctrl_in_type;
sdo : out sdctrl_out_type
);
end;
architecture rtl of ddrsp64a is
constant REVISION : integer := 0;
constant CMD_PRE : std_logic_vector(2 downto 0) := "010";
constant CMD_REF : std_logic_vector(2 downto 0) := "100";
constant CMD_LMR : std_logic_vector(2 downto 0) := "110";
constant CMD_EMR : std_logic_vector(2 downto 0) := "111";
constant abuf : integer := 6;
constant hconfig : ahb_config_type := (
0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_DDRSP, 0, REVISION, 0),
4 => ahb_membar(haddr, '1', '1', hmask),
5 => ahb_iobar(ioaddr, iomask),
others => zero32);
type mcycletype is (midle, active, ext, leadout);
type ahb_state_type is (midle, rhold, dread, dwrite, whold1, whold2);
type sdcycletype is (act1, act2, act3, rd1, rd2, rd3, rd4, rd5, rd6, rd7, rd8,
wr1, wr2, wr3, wr4a, wr4, wr5, sidle, ioreg1, ioreg2);
type icycletype is (iidle, pre, ref1, ref2, emode, lmode, finish);
constant NAHBMST : integer := 16; -- maximum AHB masters
constant NAHBSLV : integer := 16; -- maximum AHB slaves
constant NAPBSLV : integer := 16; -- maximum APB slaves
constant NAHBIRQ : integer := 32; -- maximum interrupts
constant NAHBAMR : integer := 4; -- maximum address mapping registers
constant NAHBIR : integer := 4; -- maximum AHB identification registers
constant NAHBCFG : integer := NAHBIR + NAHBAMR; -- words in AHB config block
constant NAPBIR : integer := 1; -- maximum APB configuration words
constant NAPBAMR : integer := 1; -- maximum APB configuration words
constant NAPBCFG : integer := NAPBIR + NAPBAMR; -- words in APB config block
constant NBUS : integer := 4;
subtype amba_config_word is std_logic_vector(31 downto 0);
type ahb_config_type is array (0 to NAHBCFG-1) of amba_config_word;
type apb_config_type is array (0 to NAPBCFG-1) of amba_config_word;
-- AHB master inputs
type ahb_mst_in_type is record
hgrant : std_logic_vector(0 to NAHBMST-1); -- bus grant
hready : std_ulogic; -- transfer done
hresp : std_logic_vector(1 downto 0); -- response type
hrdata : std_logic_vector(31 downto 0); -- read data bus
hcache : std_ulogic; -- cacheable
hirq : std_logic_vector(NAHBIRQ-1 downto 0); -- interrupt result bus
testen : std_ulogic; -- scan test enable
testrst : std_ulogic; -- scan test reset
scanen : std_ulogic; -- scan enable
testoen : std_ulogic; -- test output enable
end record;
-- AHB master outputs
type ahb_mst_out_type is record
hbusreq : std_ulogic; -- bus request
hlock : std_ulogic; -- lock request
htrans : std_logic_vector(1 downto 0); -- transfer type
haddr : std_logic_vector(31 downto 0); -- address bus (byte)
hwrite : std_ulogic; -- read/write
hsize : std_logic_vector(2 downto 0); -- transfer size
hburst : std_logic_vector(2 downto 0); -- burst type
hprot : std_logic_vector(3 downto 0); -- protection control
hwdata : std_logic_vector(31 downto 0); -- write data bus
hirq : std_logic_vector(NAHBIRQ-1 downto 0); -- interrupt bus
hconfig : ahb_config_type; -- memory access reg.
hindex : integer range 0 to NAHBMST-1; -- diagnostic use only
end record;
-- AHB slave inputs
type ahb_slv_in_type is record
hsel : std_logic_vector(0 to NAHBSLV-1); -- slave select
haddr : std_logic_vector(31 downto 0); -- address bus (byte)
hwrite : std_ulogic; -- read/write
htrans : std_logic_vector(1 downto 0); -- transfer type
hsize : std_logic_vector(2 downto 0); -- transfer size
hburst : std_logic_vector(2 downto 0); -- burst type
hwdata : std_logic_vector(31 downto 0); -- write data bus
hprot : std_logic_vector(3 downto 0); -- protection control
hready : std_ulogic; -- transfer done
hmaster : std_logic_vector(3 downto 0); -- current master
hmastlock : std_ulogic; -- locked access
hmbsel : std_logic_vector(0 to NAHBAMR-1); -- memory bank select
hcache : std_ulogic; -- cacheable
hirq : std_logic_vector(NAHBIRQ-1 downto 0); -- interrupt result bus
testen : std_ulogic; -- scan test enable
testrst : std_ulogic; -- scan test reset
scanen : std_ulogic; -- scan enable
testoen : std_ulogic; -- test output enable
end record;
-- AHB slave outputs
type ahb_slv_out_type is record
hready : std_ulogic; -- transfer done
hresp : std_logic_vector(1 downto 0); -- response type
hrdata : std_logic_vector(31 downto 0); -- read data bus
hsplit : std_logic_vector(15 downto 0); -- split completion
hcache : std_ulogic; -- cacheable
hirq : std_logic_vector(NAHBIRQ-1 downto 0); -- interrupt bus
hconfig : ahb_config_type; -- memory access reg.
hindex : integer range 0 to NAHBSLV-1; -- diagnostic use only
end record;
-- array types
type ahb_mst_out_vector_type is array (natural range <>) of ahb_mst_out_type;
type ahb_slv_out_vector_type is array (natural range <>) of ahb_slv_out_type;
subtype ahb_mst_out_vector is ahb_mst_out_vector_type(NAHBMST-1 downto 0);
subtype ahb_slv_out_vector is ahb_slv_out_vector_type(NAHBSLV-1 downto 0);
type ahb_mst_out_bus_vector is array (0 to NBUS-1) of ahb_mst_out_vector;
type ahb_slv_out_bus_vector is array (0 to NBUS-1) of ahb_slv_out_vector;
-- constants
constant HTRANS_IDLE: std_logic_vector(1 downto 0) := "00";
constant HTRANS_BUSY: std_logic_vector(1 downto 0) := "01";
constant HTRANS_NONSEQ: std_logic_vector(1 downto 0) := "10";
constant HTRANS_SEQ: std_logic_vector(1 downto 0) := "11";
constant HBURST_SINGLE: std_logic_vector(2 downto 0) := "000";
constant HBURST_INCR: std_logic_vector(2 downto 0) := "001";
constant HBURST_WRAP4: std_logic_vector(2 downto 0) := "010";
constant HBURST_INCR4: std_logic_vector(2 downto 0) := "011";
constant HBURST_WRAP8: std_logic_vector(2 downto 0) := "100";
constant HBURST_INCR8: std_logic_vector(2 downto 0) := "101";
constant HBURST_WRAP16: std_logic_vector(2 downto 0) := "110";
constant HBURST_INCR16: std_logic_vector(2 downto 0) := "111";
constant HSIZE_BYTE: std_logic_vector(2 downto 0) := "000";
constant HSIZE_HWORD: std_logic_vector(2 downto 0) := "001";
constant HSIZE_WORD: std_logic_vector(2 downto 0) := "010";
constant HSIZE_DWORD: std_logic_vector(2 downto 0) := "011";
constant HSIZE_4WORD: std_logic_vector(2 downto 0) := "100";
constant HSIZE_8WORD: std_logic_vector(2 downto 0) := "101";
constant HSIZE_16WORD: std_logic_vector(2 downto 0) := "110";
constant HSIZE_32WORD: std_logic_vector(2 downto 0) := "111";
constant HRESP_OKAY: std_logic_vector(1 downto 0) := "00";
constant HRESP_ERROR: std_logic_vector(1 downto 0) := "01";
constant HRESP_RETRY: std_logic_vector(1 downto 0) := "10";
constant HRESP_SPLIT: std_logic_vector(1 downto 0) := "11";
-- APB slave inputs
type apb_slv_in_type is record
psel : std_logic_vector(0 to NAPBSLV-1); -- slave select
penable : std_ulogic; -- strobe
paddr : std_logic_vector(31 downto 0); -- address bus (byte)
pwrite : std_ulogic; -- write
pwdata : std_logic_vector(31 downto 0); -- write data bus
pirq : std_logic_vector(NAHBIRQ-1 downto 0); -- interrupt result bus
testen : std_ulogic; -- scan test enable
testrst : std_ulogic; -- scan test reset
scanen : std_ulogic; -- scan enable
testoen : std_ulogic; -- test output enable
end record;
-- APB slave outputs
type apb_slv_out_type is record
prdata : std_logic_vector(31 downto 0); -- read data bus
pirq : std_logic_vector(NAHBIRQ-1 downto 0); -- interrupt bus
pconfig : apb_config_type; -- memory access reg.
pindex : integer range 0 to NAPBSLV -1; -- diag use only
end record;
-- array types
type apb_slv_out_vector is array (0 to NAPBSLV-1) of apb_slv_out_type;
-- support for plug&play configuration
constant AMBA_CONFIG_VER0 : std_logic_vector(1 downto 0) := "00";
subtype amba_vendor_type is integer range 0 to 16#ff#;
subtype amba_device_type is integer range 0 to 16#3ff#;
subtype amba_version_type is integer range 0 to 16#3f#;
subtype amba_cfgver_type is integer range 0 to 3;
subtype amba_irq_type is integer range 0 to NAHBIRQ-1;
subtype ahb_addr_type is integer range 0 to 16#fff#;
constant zx : std_logic_vector(31 downto 0) := (others => '0');
constant zxirq : std_logic_vector(NAHBIRQ-1 downto 0) := (others => '0');
constant zy : std_logic_vector(0 to 31) := (others => '0');
constant apb_none : apb_slv_out_type :=
(zx, zxirq(NAHBIRQ-1 downto 0), (others => zx), 0);
constant ahbm_none : ahb_mst_out_type := ( '0', '0', "00", zx,
'0', "000", "000", "0000", zx, zxirq(NAHBIRQ-1 downto 0), (others => zx), 0);
constant ahbs_none : ahb_slv_out_type := (
'1', "00", zx, zx(15 downto 0), '0', zxirq(NAHBIRQ-1 downto 0), (others => zx), 0);
constant ahbs_in_none : ahb_slv_in_type := (
zy(0 to NAHBSLV-1), zx, '0', "00", "000", "000", zx,
"0000", '1', "0000", '0', zy(0 to NAHBAMR-1), '0', zxirq(NAHBIRQ-1 downto 0),
'0', '0', '0', '0');
constant ahbsv_none : ahb_slv_out_vector := (others => ahbs_none);
type memory_in_type is record
data : std_logic_vector(31 downto 0); -- Data bus address
brdyn : std_logic;
bexcn : std_logic;
writen : std_logic;
wrn : std_logic_vector(3 downto 0);
bwidth : std_logic_vector(1 downto 0);
sd : std_logic_vector(63 downto 0);
cb : std_logic_vector(7 downto 0);
scb : std_logic_vector(7 downto 0);
edac : std_logic;
end record;
type memory_out_type is record
address : std_logic_vector(31 downto 0);
data : std_logic_vector(31 downto 0);
sddata : std_logic_vector(63 downto 0);
ramsn : std_logic_vector(7 downto 0);
ramoen : std_logic_vector(7 downto 0);
ramn : std_ulogic;
romn : std_ulogic;
mben : std_logic_vector(3 downto 0);
iosn : std_logic;
romsn : std_logic_vector(7 downto 0);
oen : std_logic;
writen : std_logic;
wrn : std_logic_vector(3 downto 0);
bdrive : std_logic_vector(3 downto 0);
vbdrive : std_logic_vector(31 downto 0); --vector bus drive
svbdrive : std_logic_vector(63 downto 0); --vector bus drive sdram
read : std_logic;
sa : std_logic_vector(14 downto 0);
cb : std_logic_vector(7 downto 0);
scb : std_logic_vector(7 downto 0);
vcdrive : std_logic_vector(7 downto 0); --vector bus drive cb
svcdrive : std_logic_vector(7 downto 0); --vector bus drive cb sdram
ce : std_ulogic;
end record;
type sdctrl_in_type is record
wprot : std_ulogic;
data : std_logic_vector (127 downto 0); -- data in
cb : std_logic_vector(15 downto 0);
end record;
type sdctrl_out_type is record
sdcke : std_logic_vector ( 1 downto 0); -- clk en
sdcsn : std_logic_vector ( 1 downto 0); -- chip sel
sdwen : std_ulogic; -- write en
rasn : std_ulogic; -- row addr stb
casn : std_ulogic; -- col addr stb
dqm : std_logic_vector ( 15 downto 0); -- data i/o mask
bdrive : std_ulogic; -- bus drive
qdrive : std_ulogic; -- bus drive
vbdrive : std_logic_vector(31 downto 0); -- vector bus drive
address : std_logic_vector (16 downto 2); -- address out
data : std_logic_vector (127 downto 0); -- data out
cb : std_logic_vector(15 downto 0);
ce : std_ulogic;
ba : std_logic_vector ( 1 downto 0); -- bank address
cal_en : std_logic_vector(7 downto 0); -- enable delay calibration
cal_inc : std_logic_vector(7 downto 0); -- inc/dec delay
cal_rst : std_logic; -- calibration reset
odt : std_logic_vector(1 downto 0);
end record;
type sdram_out_type is record
sdcke : std_logic_vector ( 1 downto 0); -- clk en
sdcsn : std_logic_vector ( 1 downto 0); -- chip sel
sdwen : std_ulogic; -- write en
rasn : std_ulogic; -- row addr stb
casn : std_ulogic; -- col addr stb
dqm : std_logic_vector ( 7 downto 0); -- data i/o mask
end record;
-- sdram configuration register
type sdram_cfg_type is record
command : std_logic_vector(2 downto 0);
csize : std_logic_vector(1 downto 0);
bsize : std_logic_vector(2 downto 0);
trcd : std_ulogic; -- tCD : 2/3 clock cycles
trfc : std_logic_vector(2 downto 0);
trp : std_ulogic; -- precharge to activate: 2/3 clock cycles
refresh : std_logic_vector(11 downto 0);
renable : std_ulogic;
dllrst : std_ulogic;
refon : std_ulogic;
cke : std_ulogic;
end record;
type access_param is record
haddr : std_logic_vector(31 downto 0);
size : std_logic_vector(1 downto 0);
hwrite : std_ulogic;
hio : std_ulogic;
end record;
-- local registers
type ahb_reg_type is record
hready : std_ulogic;
hsel : std_ulogic;
hio : std_ulogic;
startsd : std_ulogic;
ready : std_ulogic;
ready2 : std_ulogic;
write : std_logic_vector(3 downto 0);
state : ahb_state_type;
haddr : std_logic_vector(31 downto 0);
hrdata : std_logic_vector(31 downto 0);
hwdata : std_logic_vector(31 downto 0);
hwrite : std_ulogic;
htrans : std_logic_vector(1 downto 0);
hresp : std_logic_vector(1 downto 0);
raddr : std_logic_vector(abuf-1 downto 0);
size : std_logic_vector(1 downto 0);
acc : access_param;
end record;
type ddr_reg_type is record
startsd : std_ulogic;
startsdold : std_ulogic;
burst : std_ulogic;
hready : std_ulogic;
bdrive : std_ulogic;
qdrive : std_ulogic;
nbdrive : std_ulogic;
mstate : mcycletype;
sdstate : sdcycletype;
cmstate : mcycletype;
istate : icycletype;
trfc : std_logic_vector(2 downto 0);
refresh : std_logic_vector(11 downto 0);
sdcsn : std_logic_vector(1 downto 0);
sdwen : std_ulogic;
rasn : std_ulogic;
casn : std_ulogic;
dqm : std_logic_vector(15 downto 0);
address : std_logic_vector(15 downto 2); -- memory address
ba : std_logic_vector( 1 downto 0);
waddr : std_logic_vector(abuf-1 downto 0);
cfg : sdram_cfg_type;
hrdata : std_logic_vector(127 downto 0);
end record;
signal vcc : std_ulogic;
signal r, ri : ddr_reg_type;
signal ra, rai : ahb_reg_type;
signal rbdrive, ribdrive : std_logic_vector(31 downto 0);
signal rdata, wdata : std_logic_vector(127 downto 0);
attribute syn_preserve : boolean;
attribute syn_preserve of rbdrive : signal is true;
begin
vcc <= '1';
ahb_ctrl : process(rst, ahbsi, r, ra, rdata)
variable v : ahb_reg_type; -- local variables for registers
variable startsd : std_ulogic;
variable dout : std_logic_vector(31 downto 0);
begin
v := ra; v.hresp := HRESP_OKAY; v.write := "0000";
case ra.raddr(1 downto 0) is
when "00" => v.hrdata := rdata(127 downto 96);
when "01" => v.hrdata := rdata(95 downto 64);
when "10" => v.hrdata := rdata(63 downto 32);
when others => v.hrdata := rdata(31 downto 0);
end case;
v.ready := not (ra.startsd xor r.startsdold);
v.ready2 := ra.ready;
if ((ahbsi.hready and ahbsi.hsel(hindex)) = '1') then
v.htrans := ahbsi.htrans; v.haddr := ahbsi.haddr;
v.size := ahbsi.hsize(1 downto 0); v.hwrite := ahbsi.hwrite;
if ahbsi.htrans(1) = '1' then
v.hio := ahbsi.hmbsel(1);
v.hsel := '1'; v.hready := '0';
end if;
end if;
if ahbsi.hready = '1' then v.hsel := ahbsi.hsel(hindex); end if;
-- if (ra.hsel and ra.hio and not ra.hready) = '1' then v.hready := '1'; end if;
case ra.state is
when midle =>
if ((v.hsel and v.htrans(1)) = '1') then
if v.hwrite = '0' then
v.state := rhold; v.startsd := not ra.startsd;
else
v.state := dwrite; v.hready := '1';
-- v.write(0) := not v.haddr(2); v.write(1) := v.haddr(2);
v.write := decode(v.haddr(3 downto 2));
end if;
end if;
v.raddr := ra.haddr(7 downto 2);
v.ready := '0'; v.ready2 := '0';
-- if not ((ra.hsel and ra.htrans(1) and not ra.htrans(0)) = '1') then
if ahbsi.hready = '1' then
v.acc := (v.haddr, v.size, v.hwrite, v.hio);
end if;
when rhold =>
v.raddr := ra.haddr(7 downto 2);
if ra.ready2 = '1' then
v.state := dread; v.hready := '1'; v.raddr := ra.raddr + 1;
end if;
when dread =>
v.raddr := ra.raddr + 1; v.hready := '1';
if ((v.hsel and v.htrans(1) and v.htrans(0)) = '0') or
(ra.raddr(2 downto 0) = "000")
then v.state := midle; v.hready := '0'; end if;
v.acc := (v.haddr, v.size, v.hwrite, v.hio);
when dwrite =>
v.raddr := ra.haddr(7 downto 2); v.hready := '1';
-- v.write(0) := not v.haddr(2); v.write(1) := v.haddr(2);
v.write := decode(v.haddr(3 downto 2));
if ((v.hsel and v.htrans(1) and v.htrans(0)) = '0') or
(ra.haddr(4 downto 2) = "111")
then
v.startsd := not ra.startsd; v.state := whold1;
v.write := "0000"; v.hready := '0';
end if;
when whold1 =>
v.state := whold2; v.ready := '0';
when whold2 =>
if ra.ready = '1' then
v.state := midle; v.acc := (v.haddr, v.size, v.hwrite, v.hio);
end if;
end case;
v.hwdata := ahbsi.hwdata;
if (ahbsi.hready and ahbsi.hsel(hindex) ) = '1' then
if ahbsi.htrans(1) = '0' then v.hready := '1'; end if;
end if;
dout := ra.hrdata(31 downto 0);
if rst = '0' then
v.hsel := '0';
v.hready := '1';
v.state := midle;
v.startsd := '0';
v.hio := '0';
end if;
rai <= v;
ahbso.hready <= ra.hready;
ahbso.hresp <= ra.hresp;
ahbso.hrdata <= dout;
ahbso.hcache <= not ra.hio;
end process;
ddr_ctrl : process(rst, r, ra, sdi, rbdrive, wdata)
variable v : ddr_reg_type; -- local variables for registers
variable startsd : std_ulogic;
variable dqm : std_logic_vector(15 downto 0);
variable raddr : std_logic_vector(13 downto 0);
variable adec : std_ulogic;
variable rams : std_logic_vector(1 downto 0);
variable ba : std_logic_vector(1 downto 0);
variable haddr : std_logic_vector(31 downto 0);
variable hsize : std_logic_vector(1 downto 0);
variable hwrite : std_ulogic;
variable htrans : std_logic_vector(1 downto 0);
variable hready : std_ulogic;
variable vbdrive : std_logic_vector(31 downto 0);
variable bdrive : std_ulogic;
variable writecfg: std_ulogic;
variable regsd1 : std_logic_vector(31 downto 0); -- data from registers
variable regsd2 : std_logic_vector(31 downto 0); -- data from registers
begin
-- Variable default settings to avoid latches
v := r; v.hready := '0'; writecfg := '0'; vbdrive := rbdrive;
v.hrdata := sdi.data; v.qdrive :='0';
regsd1 := (others => '0');
regsd1(31 downto 15) := r.cfg.refon & r.cfg.trp & r.cfg.trfc &
r.cfg.trcd & r.cfg.bsize & r.cfg.csize & r.cfg.command &
r.cfg.dllrst & r.cfg.renable & r.cfg.cke;
regsd1(11 downto 0) := r.cfg.refresh;
regsd2 := (others => '0');
regsd2(8 downto 0) := conv_std_logic_vector(MHz, 9);
regsd2(14 downto 12) := conv_std_logic_vector(3, 3);
-- generate DQM from address and write size
case ra.acc.size is
when "00" =>
case ra.acc.haddr(3 downto 0) is
when "0000" => dqm := "0111111111111111";
when "0001" => dqm := "1011111111111111";
when "0010" => dqm := "1101111111111111";
when "0011" => dqm := "1110111111111111";
when "0100" => dqm := "1111011111111111";
when "0101" => dqm := "1111101111111111";
when "0110" => dqm := "1111110111111111";
when "0111" => dqm := "1111111011111111";
when "1000" => dqm := "1111111101111111";
when "1001" => dqm := "1111111110111111";
when "1010" => dqm := "1111111111011111";
when "1011" => dqm := "1111111111101111";
when "1100" => dqm := "1111111111110111";
when "1101" => dqm := "1111111111111011";
when "1110" => dqm := "1111111111111101";
when others => dqm := "1111111111111110";
end case;
when "01" =>
case ra.acc.haddr(3 downto 1) is
when "000" => dqm := "0011111111111111";
when "001" => dqm := "1100111111111111";
when "010" => dqm := "1111001111111111";
when "011" => dqm := "1111110011111111";
when "100" => dqm := "1111111100111111";
when "101" => dqm := "1111111111001111";
when "110" => dqm := "1111111111110011";
when others => dqm := "1111111111111100";
end case;
when others =>
dqm := "0000000000000000";
end case;
v.startsd := ra.startsd;
-- main FSM
case r.mstate is
when midle =>
if r.startsd = '1' then
if (r.sdstate = sidle) and (r.cfg.command = "000") and
(r.cmstate = midle)
then
startsd := '1'; v.mstate := active;
end if;
end if;
when others => null;
end case;
startsd := r.startsd xor r.startsdold;
-- generate row and column address size
haddr := ra.acc.haddr;
haddr(31 downto 20) := haddr(31 downto 20) and not conv_std_logic_vector(hmask, 12);
case r.cfg.csize is
when "00" => raddr := haddr(25 downto 12);
when "01" => raddr := haddr(26 downto 13);
when "10" => raddr := haddr(27 downto 14);
when others => raddr := haddr(28 downto 15);
end case;
-- generate bank address
ba := genmux(r.cfg.bsize, haddr(29 downto 22)) &
genmux(r.cfg.bsize, haddr(28 downto 21));
-- generate chip select
adec := genmux(r.cfg.bsize, haddr(30 downto 23));
rams := adec & not adec;
-- sdram access FSM
if r.trfc /= "000" then v.trfc := r.trfc - 1; end if;
case r.sdstate is
when sidle =>
if (startsd = '1') and (r.cfg.command = "000") and (r.cmstate = midle)
and (r.istate = finish)
then
v.address := raddr; v.ba := ba;
if ra.acc.hio = '0' then
v.sdcsn := not rams(1 downto 0); v.rasn := '0'; v.sdstate := act1;
else v.sdstate := ioreg1; end if;
end if;
v.waddr := ra.acc.haddr(7 downto 2);
when act1 =>
v.rasn := '1'; v.trfc := r.cfg.trfc;
if r.cfg.trcd = '1' then v.sdstate := act2; else
v.sdstate := act3; v.hready := ra.acc.hwrite;
end if;
v.waddr := ra.acc.haddr(7 downto 2);
when act2 =>
v.sdstate := act3; v.hready := ra.acc.hwrite;
when act3 =>
v.casn := '0';
v.address := ra.acc.haddr(15 downto 13) & '0' & ra.acc.haddr(12 downto 4) & '0';
v.dqm := dqm;
if ra.acc.hwrite = '1' then
v.waddr := r.waddr + 4; v.waddr(1 downto 0) := "00";
v.sdstate := wr1; v.sdwen := '0'; v.bdrive := '0'; v.qdrive := '1';
if (r.waddr /= ra.raddr) then v.hready := '1';
if (r.waddr(5 downto 2) = ra.raddr(5 downto 2)) then
if r.waddr(1) = '1' then v.dqm(15 downto 8) := (others => '1');
else
case ra.raddr(1 downto 0) is
when "01" => v.dqm(7 downto 0) := (others => '1');
when "10" => v.dqm(3 downto 0) := (others => '1');
v.dqm(15 downto 12) := (others => r.waddr(0));
when others => v.dqm(15 downto 12) := (others => r.waddr(0));
end case;
end if;
else
case r.waddr(1 downto 0) is
when "01" => v.dqm(15 downto 12) := (others => '1');
when "10" => v.dqm(15 downto 8) := (others => '1');
when "11" => v.dqm(15 downto 4) := (others => '1');
when others => null;
end case;
end if;
else
case r.waddr(1 downto 0) is
when "00" => v.dqm(11 downto 0) := (others => '1');
when "01" => v.dqm(15 downto 12) := (others => '1'); v.dqm(7 downto 0) := (others => '1');
when "10" => v.dqm(15 downto 8) := (others => '1'); v.dqm(3 downto 0) := (others => '1');
when others => v.dqm(15 downto 4) := (others => '1');
end case;
end if;
else v.sdstate := rd1; end if;
when wr1 =>
v.sdwen := '1'; v.casn := '1'; v.qdrive := '1';
v.waddr := r.waddr + 4; v.dqm := (others => '0');
v.address(8 downto 3) := r.waddr;
if (r.waddr <= ra.raddr) and (r.waddr(5 downto 2) /= "0000") and (r.hready = '1')
then
v.hready := '1';
if (r.hready = '1') and (r.waddr(2 downto 0) = "000") then
v.sdwen := '0'; v.casn := '0';
end if;
if (r.waddr(5 downto 2) = ra.raddr(5 downto 2)) and (r.waddr /= "000000") then
case ra.raddr(1 downto 0) is
when "00" => v.dqm(11 downto 0) := (others => '1');
when "01" => v.dqm(7 downto 0) := (others => '1');
when "10" => v.dqm(3 downto 0) := (others => '1');
when others => null;
end case;
end if;
else
v.sdstate := wr2;
v.dqm := (others => '1'); --v.bdrive := '1';
v.startsdold := r.startsd;
end if;
when wr2 =>
v.sdstate := wr3; v.qdrive := '1';
when wr3 =>
v.sdstate := wr4a; v.qdrive := '1';
when wr4a =>
v.bdrive := '1';
v.rasn := '0'; v.sdwen := '0'; v.sdstate := wr4; v.qdrive := '1';
when wr4 =>
v.sdcsn := "11"; v.rasn := '1'; v.sdwen := '1'; v.qdrive := '0';
v.sdstate := wr5;
when wr5 =>
v.sdstate := sidle;
when rd1 =>
v.casn := '1'; v.sdstate := rd7;
-- if ra.acc.haddr(4 downto 2) = "011" then
-- v.casn := '0'; v.burst := '1'; v.address(5 downto 3) := "100";
-- end if;
when rd7 =>
v.casn := '1'; v.sdstate := rd2;
-- if ra.acc.haddr(4 downto 2) = "010" then
-- v.casn := '0'; v.burst := '1'; v.address(5 downto 3) := "100";
-- end if;
when rd2 =>
v.casn := '1'; v.sdstate := rd3;
-- if ra.acc.haddr(4 downto 2) = "001" then
-- v.casn := '0'; v.burst := '1'; v.address(5 downto 3) := "100";
-- end if;
-- if v.sdwen = '0' then v.dqm := (others => '1'); end if;
when rd3 =>
if fast = 0 then v.startsdold := r.startsd; end if;
v.sdstate := rd4; v.hready := '1'; v.casn := '1';
-- if r.sdwen = '0' then
-- v.rasn := '1'; v.sdwen := '1'; v.sdcsn := "11"; v.dqm := (others => '1');
-- elsif ra.acc.haddr(4 downto 2) = "000" then
-- v.casn := '0'; v.burst := '1'; v.address(5) := '1';
-- v.waddr := v.address(8 downto 3);
-- end if;
if v.hready = '1' then v.waddr := r.waddr + 4; end if;
when rd4 =>
v.hready := '1'; v.casn := '1';
-- if (r.sdcsn /= "11") and (r.waddr(1 downto 0) = "11") and (r.burst = '1')
-- then
-- v.burst := '0';
if (r.sdcsn = "11") or (r.waddr(2 downto 2) = "1") then
v.dqm := (others => '1'); v.burst := '0';
if fast /= 0 then v.startsdold := r.startsd; end if;
if (r.sdcsn /= "11") then
v.rasn := '0'; v.sdwen := '0'; v.sdstate := rd5;
else
if r.cfg.trp = '1' then v.sdstate := rd6;
else v.sdstate := sidle; end if;
end if;
end if;
if v.hready = '1' then v.waddr := r.waddr + 4; end if;
when rd5 =>
if r.cfg.trp = '1' then v.sdstate := rd6;
else v.sdstate := sidle; end if;
v.sdcsn := (others => '1'); v.rasn := '1'; v.sdwen := '1';
v.dqm := (others => '1');
when rd6 =>
v.sdstate := sidle; v.dqm := (others => '1');
v.sdcsn := (others => '1'); v.rasn := '1'; v.sdwen := '1';
when ioreg1 =>
v.hrdata(127 downto 64) := regsd1 & regsd2; v.sdstate := ioreg2;
if ra.acc.hwrite = '0' then v.hready := '1'; end if;
when ioreg2 =>
writecfg := ra.acc.hwrite and not r.waddr(0); v.startsdold := r.startsd;
v.sdstate := sidle;
when others =>
v.sdstate := sidle;
end case;
-- sdram commands
case r.cmstate is
when midle =>
if r.sdstate = sidle then
case r.cfg.command is
when CMD_PRE => -- precharge
v.sdcsn := (others => '0'); v.rasn := '0'; v.sdwen := '0';
v.address(12) := '1'; v.cmstate := active;
when CMD_REF => -- auto-refresh
v.sdcsn := (others => '0'); v.rasn := '0'; v.casn := '0';
v.cmstate := active;
when CMD_EMR => -- load-ext-mode-reg
v.sdcsn := (others => '0'); v.rasn := '0'; v.casn := '0';
v.sdwen := '0'; v.cmstate := active; v.ba := "01";
v.address := "00000000000000";
when CMD_LMR => -- load-mode-reg
v.sdcsn := (others => '0'); v.rasn := '0'; v.casn := '0';
v.sdwen := '0'; v.cmstate := active; v.ba := "00";
-- v.address := "00000" & r.cfg.dllrst & "0" & "01" & r.cfg.trcd & "0011";
v.address := "00000" & r.cfg.dllrst & "0" & "01" & "00010";
when others => null;
end case;
end if;
when active =>
v.sdcsn := (others => '1'); v.rasn := '1'; v.casn := '1';
v.sdwen := '1'; v.cfg.command := "000";
v.cmstate := leadout; v.trfc := r.cfg.trfc;
when others =>
if r.trfc = "000" then v.cmstate := midle; end if;
end case;
-- sdram init
case r.istate is
when iidle =>
if r.cfg.renable = '1' then
v.cfg.cke := '1'; v.cfg.dllrst := '1';
if r.cfg.cke = '1' then v.istate := pre; v.cfg.command := CMD_PRE; end if; v.ba := "00";
end if;
when pre =>
if r.cfg.command = "000" then
v.cfg.command := "11" & r.cfg.dllrst; -- CMD_LMR/CMD_EMR
if r.cfg.dllrst = '1' then v.istate := emode; else v.istate := lmode; end if;
end if;
when emode =>
if r.cfg.command = "000" then
v.istate := lmode; v.cfg.command := CMD_LMR;
end if;
when lmode =>
if r.cfg.command = "000" then
if r.cfg.dllrst = '1' then
if r.refresh(9 downto 8) = "00" then -- > 200 clocks delay
v.cfg.command := CMD_PRE; v.istate := ref1;
end if;
else
v.istate := finish; --v.cfg.command := CMD_LMR;
v.cfg.refon := '1'; v.cfg.renable := '0';
end if;
end if;
when ref1 =>
if r.cfg.command = "000" then
v.cfg.command := CMD_REF; v.cfg.dllrst := '0'; v.istate := ref2;
end if;
when ref2 =>
if r.cfg.command = "000" then
v.cfg.command := CMD_REF; v.istate := pre;
end if;
when others =>
if r.cfg.renable = '1' then
v.istate := iidle; v.cfg.dllrst := '1';
end if;
end case;
-- second part of main fsm
case r.mstate is
when active =>
if v.hready = '1' then
v.mstate := midle;
end if;
when others => null;
end case;
-- sdram refresh counter
if ((r.cfg.refon = '1') and (r.istate = finish)) or
(r.cfg.dllrst = '1')
then
v.refresh := r.refresh - 1;
if (v.refresh(11) and not r.refresh(11)) = '1' then
v.refresh := r.cfg.refresh;
if r.cfg.dllrst = '0' then v.cfg.command := "100"; end if;
end if;
end if;
-- AHB register access
if (ra.acc.hio and ra.acc.hwrite and writecfg) = '1' then
v.cfg.refresh := wdata(11+96 downto 0+96);
v.cfg.cke := wdata(15+96);
v.cfg.renable := wdata(16+96);
v.cfg.dllrst := wdata(17+96);
v.cfg.command := wdata(20+96 downto 18+96);
v.cfg.csize := wdata(22+96 downto 21+96);
v.cfg.bsize := wdata(25+96 downto 23+96);
v.cfg.trcd := wdata(26+96);
v.cfg.trfc := wdata(29+96 downto 27+96);
v.cfg.trp := wdata(30+96);
v.cfg.refon := wdata(31+96);
end if;
v.nbdrive := not v.bdrive;
if oepol = 1 then bdrive := r.nbdrive; vbdrive := (others => v.nbdrive);
else bdrive := r.bdrive; vbdrive := (others => v.bdrive);end if;
-- reset
if rst = '0' then
v.sdstate := sidle;
v.mstate := midle;
v.istate := finish;
v.cmstate := midle;
v.cfg.command := "000";
v.cfg.csize := conv_std_logic_vector(col-9, 2);
v.cfg.bsize := conv_std_logic_vector(log2(Mbyte/8), 3);
if MHz > 100 then v.cfg.trcd := '1'; else v.cfg.trcd := '0'; end if;
v.cfg.refon := '0';
v.cfg.trfc := conv_std_logic_vector(75*MHz/1000-2, 3);
v.cfg.refresh := conv_std_logic_vector(7800*MHz/1000, 12);
v.refresh := (others => '0');
if pwron = 1 then v.cfg.renable := '1';
else v.cfg.renable := '0'; end if;
if MHz > 100 then v.cfg.trp := '1'; else v.cfg.trp := '0'; end if;
v.dqm := (others => '1');
v.sdwen := '1';
v.rasn := '1';
v.casn := '1';
v.hready := '0';
v.startsd := '0';
v.startsdold := '0';
v.cfg.dllrst := '0';
v.cfg.cke := '0';
end if;
ri <= v;
ribdrive <= vbdrive;
end process;
sdo.sdcke <= (others => r.cfg.cke);
ahbso.hconfig <= hconfig;
ahbso.hirq <= (others => '0');
ahbso.hindex <= hindex;
ahbregs : process(clk_ahb) begin
if rising_edge(clk_ahb) then
ra <= rai;
end if;
end process;
ddrregs : process(clk_ddr, rst) begin
if rising_edge(clk_ddr) then
r <= ri; rbdrive <= ribdrive;
end if;
if (rst = '0') then
r.sdcsn <= (others => '1'); r.bdrive <= '1'; r.nbdrive <= '0';
if oepol = 0 then rbdrive <= (others => '1');
else rbdrive <= (others => '0'); end if;
r.cfg.cke <= '0';
end if;
end process;
sdo.address <= '0' & ri.address;
sdo.ba <= ri.ba;
sdo.bdrive <= r.nbdrive when oepol = 1 else r.bdrive;
sdo.qdrive <= not (ri.qdrive or r.nbdrive);
sdo.vbdrive <= rbdrive;
sdo.sdcsn <= ri.sdcsn;
sdo.sdwen <= ri.sdwen;
sdo.dqm <= r.dqm;
sdo.rasn <= ri.rasn;
sdo.casn <= ri.casn;
sdo.data <= wdata;
read_buff : syncram_2p
generic map (tech => memtech, abits => 4, dbits => 128, sepclk => 1, wrfst => 0)
port map ( rclk => clk_ahb, renable => vcc, raddress => rai.raddr(5 downto 2),
dataout => rdata, wclk => clk_ddr, write => ri.hready,
waddress => r.waddr(5 downto 2), datain => ri.hrdata);
write_buff1 : syncram_2p
generic map (tech => memtech, abits => 4, dbits => 32, sepclk => 1, wrfst => 0)
port map ( rclk => clk_ddr, renable => vcc, raddress => r.waddr(5 downto 2),
dataout => wdata(127 downto 96), wclk => clk_ahb, write => ra.write(0),
waddress => ra.haddr(7 downto 4), datain => ahbsi.hwdata);
write_buff2 : syncram_2p
generic map (tech => memtech, abits => 4, dbits => 32, sepclk => 1, wrfst => 0)
port map ( rclk => clk_ddr, renable => vcc, raddress => r.waddr(5 downto 2),
dataout => wdata(95 downto 64), wclk => clk_ahb, write => ra.write(1),
waddress => ra.haddr(7 downto 4), datain => ahbsi.hwdata);
write_buff3 : syncram_2p
generic map (tech => memtech, abits => 4, dbits => 32, sepclk => 1, wrfst => 0)
port map ( rclk => clk_ddr, renable => vcc, raddress => r.waddr(5 downto 2),
dataout => wdata(63 downto 32), wclk => clk_ahb, write => ra.write(2),
waddress => ra.haddr(7 downto 4), datain => ahbsi.hwdata);
write_buff4 : syncram_2p
generic map (tech => memtech, abits => 4, dbits => 32, sepclk => 1, wrfst => 0)
port map ( rclk => clk_ddr, renable => vcc, raddress => r.waddr(5 downto 2),
dataout => wdata(31 downto 0), wclk => clk_ahb, write => ra.write(3),
waddress => ra.haddr(7 downto 4), datain => ahbsi.hwdata);
-- pragma translate_off
bootmsg : report_version
generic map (
msg1 => "ddrsp" & tost(hindex) & ": 64-bit DDR266 controller rev " &
tost(REVISION) & ", " & tost(Mbyte) & " Mbyte, " & tost(MHz) &
" MHz DDR clock");
-- pragma translate_on
end;
| mit | 52a9da7cb3e27f80fe12a5e24606ef9e | 0.545726 | 3.221125 | false | false | false | false |
michaelfivez/ascon_hardware_implementation | ascon12864_iterated/Kernel/Sbox.vhd | 1 | 3,929 | -------------------------------------------------------------------------------
--! @project Iterated hardware implementation of Asconv12864
--! @author Michael Fivez
--! @license This project is released under the GNU Public License.
--! The license and distribution terms for this file may be
--! found in the file LICENSE in this distribution or at
--! http://www.gnu.org/licenses/gpl-3.0.txt
--! @note This is an hardware implementation made for my graduation thesis
--! at the KULeuven, in the COSIC department (year 2015-2016)
--! The thesis is titled 'Energy efficient hardware implementations of CAESAR submissions',
--! and can be found on the COSIC website (www.esat.kuleuven.be/cosic/publications)
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity Sbox is
port(
X0In : in std_logic_vector(63 downto 0);
X1In : in std_logic_vector(63 downto 0);
X2In : in std_logic_vector(63 downto 0);
X3In : in std_logic_vector(63 downto 0);
X4In : in std_logic_vector(63 downto 0);
RoundNr : in std_logic_vector(3 downto 0);
X0Out : out std_logic_vector(63 downto 0);
X1Out : out std_logic_vector(63 downto 0);
X2Out : out std_logic_vector(63 downto 0);
X3Out : out std_logic_vector(63 downto 0);
X4Out : out std_logic_vector(63 downto 0));
end entity Sbox;
architecture structural of Sbox is
begin
Sbox: process(X0In,X1In,X2In,X3In,X4In,RoundNr) is
-- Procedure for 5-bit Sbox
procedure doSboxPart (
variable SboxPartIn : in std_logic_vector(4 downto 0);
variable SboxPartOut : out std_logic_vector(4 downto 0)) is
-- Temp variable
variable SboxPartTemp : std_logic_vector(17 downto 0);
begin
-- Sbox Interconnections
SboxPartTemp(0) := SboxPartIn(0) xor SboxPartIn(4);
SboxPartTemp(1) := SboxPartIn(2) xor SboxPartIn(1);
SboxPartTemp(2) := SboxPartIn(4) xor SboxPartIn(3);
SboxPartTemp(3) := not SboxPartTemp(0);
SboxPartTemp(4) := not SboxPartIn(1);
SboxPartTemp(5) := not SboxPartTemp(1);
SboxPartTemp(6) := not SboxPartIn(3);
SboxPartTemp(7) := not SboxPartTemp(2);
SboxPartTemp(8) := SboxPartIn(1) and SboxPartTemp(3);
SboxPartTemp(9) := SboxPartTemp(1) and SboxPartTemp(4);
SboxPartTemp(10) := SboxPartIn(3) and SboxPartTemp(5);
SboxPartTemp(11) := SboxPartTemp(2) and SboxPartTemp(6);
SboxPartTemp(12) := SboxPartTemp(0) and SboxPartTemp(7);
SboxPartTemp(13) := SboxPartTemp(0) xor SboxPartTemp(9);
SboxPartTemp(14) := SboxPartIn(1) xor SboxPartTemp(10);
SboxPartTemp(15) := SboxPartTemp(1) xor SboxPartTemp(11);
SboxPartTemp(16) := SboxPartIn(3) xor SboxPartTemp(12);
SboxPartTemp(17) := SboxPartTemp(2) xor SboxPartTemp(8);
SboxPartOut(0) := SboxPartTemp(13) xor SboxPartTemp(17);
SboxPartOut(1) := SboxPartTemp(13) xor SboxPartTemp(14);
SboxPartOut(2) := not SboxPartTemp(15);
SboxPartOut(3) := SboxPartTemp(15) xor SboxPartTemp(16);
SboxPartOut(4) := SboxPartTemp(17);
end procedure doSboxPart;
variable X2TempIn : std_logic_vector(63 downto 0);
variable TempIn,TempOut : std_logic_vector(4 downto 0);
begin
-- Xor with round constants
X2TempIn(3 downto 0) := X2In(3 downto 0) xor RoundNr;
X2TempIn(7 downto 4) := X2In(7 downto 4) xnor RoundNr;
X2TempIn(63 downto 8) := X2In(63 downto 8);
-- Apply 5-bit Sbox 64 times
for i in X0In'range loop
TempIn(0) := X0In(i);
TempIn(1) := X1In(i);
TempIn(2) := X2TempIn(i);
TempIn(3) := X3In(i);
TempIn(4) := X4In(i);
doSboxPart(TempIn,TempOut);
X0Out(i) <= TempOut(0);
X1Out(i) <= TempOut(1);
X2Out(i) <= TempOut(2);
X3Out(i) <= TempOut(3);
X4Out(i) <= TempOut(4);
end loop;
end process Sbox;
end architecture structural;
| gpl-3.0 | b1786dbe60c74a9feccdb669b60a21e6 | 0.640367 | 2.92772 | false | false | false | false |
impedimentToProgress/UCI-BlueChip | AttackFiles/Attacks/privEsc/lib/opencores/ata/atahost_dma_fifo.vhd | 2 | 5,537 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: atahost_dma_fifo
-- File: atahost_dma_fifo.vhd
-- Author: Erik Jagre - Gaisler Research
-- Description: Generic FIFO, based on syncram in grlib
-----------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
library grlib;
use grlib.stdlib.all;
entity atahost_dma_fifo is
generic(tech : integer:=0; abits : integer:=3;
dbits : integer:=32; depth : integer:=8);
port( clk : in std_logic;
reset : in std_logic;
write_enable : in std_logic;
read_enable : in std_logic;
data_in : in std_logic_vector(dbits-1 downto 0);
data_out : out std_logic_vector(dbits-1 downto 0);
write_error : out std_logic:='0';
read_error : out std_logic:='0';
level : out natural range 0 to depth;
empty : out std_logic:='1';
full : out std_logic:='0');
end;
architecture rtl of atahost_dma_fifo is
type state_type is (full_state, empty_state, idle_state);
type reg_type is record
state : state_type;
level : integer range 0 to depth;
aw : integer range 0 to depth;
ar : integer range 0 to depth;
data_o : std_logic_vector(dbits-1 downto 0);
rd : std_logic;
wr : std_logic;
erd : std_logic;
ewr : std_logic;
reset : std_logic;
adr : std_logic_vector(abits-1 downto 0);
end record;
constant zerod : std_logic_vector(dbits-1 downto 0) := (others => '0');
constant zeroa : std_logic_vector(abits-1 downto 0) := (others => '0');
constant RESET_VECTOR : reg_type := (empty_state,0,0,0,
zerod,'0','0','0','0','0', zeroa);
signal r,ri : reg_type;
signal s_ram_adr : std_logic_vector(abits-1 downto 0);
begin
-- comb:process(write_enable, read_enable, data_in,reset, r) Erik 2007-02-08
comb:process(write_enable, read_enable, reset, r)
variable v : reg_type;
variable vfull, vempty : std_logic;
begin
v:=r;
v.wr:=write_enable; v.rd:=read_enable; v.reset:=reset;
case r.state is
when full_state=>
if write_enable='1' and read_enable='0' and reset='0' then
v.ewr:='1'; v.state:=full_state;
elsif write_enable='0' and read_enable='1' and reset='0' then
v.adr:=conv_std_logic_vector(r.ar,abits);
if r.ar=depth-1 then v.ar:=0; else v.ar:=r.ar+1; end if;
v.level:=r.level-1;
if r.aw=v.ar then v.state:=empty_state;
else v.state:=idle_state; end if;
v.ewr:='0';
end if;
when empty_state=>
if write_enable='1' and read_enable='0' and reset='0' then
v.adr:=conv_std_logic_vector(r.aw,abits);
if r.aw=depth-1 then v.aw:=0; else v.aw:=r.aw+1; end if;
v.level:=r.level+1;
if v.aw=r.ar then v.state:=full_state;
else v.state:=idle_state; end if;
v.erd:='0';
elsif write_enable='0' and read_enable='1' and reset='0' then
v.erd:='1'; v.state:=empty_state;
end if;
when idle_state=>
if write_enable='1' and read_enable='0' and reset='0' then
v.adr:=conv_std_logic_vector(r.aw,abits);
if r.aw=depth-1 then v.aw:=0; else v.aw:=r.aw+1; end if;
v.level:=r.level+1;
if v.level=depth then v.state:=full_state;
else v.state:=idle_state; end if;
elsif write_enable='0' and read_enable='1' and reset='0' then
v.adr:=conv_std_logic_vector(r.ar,abits);
if r.ar=depth-1 then v.ar:=0; else v.ar:=r.ar+1; end if;
v.level:=r.level-1;
if v.level=0 then v.state:=empty_state;
else v.state:=idle_state; end if;
end if;
end case;
if r.level=0 then vempty:='1'; vfull:='0';
elsif r.level=depth then vempty:='0'; vfull:='1';
else vempty:='0'; vfull:='0'; end if;
--reset logic
if (reset='1') then v:=RESET_VECTOR; end if;
ri<=v;
s_ram_adr<=v.adr;
--assigning outport
write_error<=v.ewr; read_error<=v.erd; level<=v.level;
empty<=vempty; full<=vfull;
end process;
ram : syncram
generic map(tech=>tech, abits=>abits, dbits=>dbits)
port map (
clk => clk,
address => s_ram_adr,
datain => data_in,
dataout => data_out,
enable => read_enable,
write => write_enable
);
sync:process(clk) --Activate on clock & reset
begin
if clk'event and clk='1' then r<=ri; end if;
end process;
end; | mit | e7551d4647c06a89475d9a51ca11536e | 0.574138 | 3.327524 | false | false | false | false |
impedimentToProgress/UCI-BlueChip | AttackFiles/Attacks/privEsc/lib/gleichmann/spi/spi_oc.vhd | 2 | 4,968 | --------------------------------------------------------------------
-- Entity: SPI_OC
-- File: spi_oc.vhd
-- Author: Thomas Ameseder, Gleichmann Electronics
--
-- Description: VHDL wrapper for the Opencores SPI core with APB
-- interface
--------------------------------------------------------------------
-- CVS Entries:
-- $Date: 2006/12/04 14:44:05 $
-- $Author: tame $
-- $Log: spi_oc.vhd,v $
-- Revision 1.3 2006/12/04 14:44:05 tame
-- Changed interrupt output to LEON from a level (that is active until it is reset) to
-- a short pulse.
--
-- Revision 1.1 2006/11/17 12:28:56 tame
-- Added SPI files: Simple SPI package and a wrapper for the (modified)
-- OpenCores Simple SPI Core with APB interface.
--
--------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
library gaisler;
use gaisler.misc.all;
library gleichmann;
use gleichmann.ocrcomp.all;
use gleichmann.sspi.all;
library opencores;
use opencores.occomp.all;
-- pragma translate_off
use std.textio.all;
-- pragma translate_on
entity spi_oc is
generic (
pindex : integer := 0; -- Leon-Index
paddr : integer := 0; -- Leon-Address
pmask : integer := 16#FFF#; -- Leon-Mask
pirq : integer := 0 -- Leon-IRQ
);
port (
rstn : in std_ulogic; -- global Reset, active low
clk : in std_ulogic; -- global Clock
apbi : in apb_slv_in_type; -- APB-Input
apbo : out apb_slv_out_type; -- APB-Output
spi_in : in spi_in_type; -- MultIO-Inputs
spi_out : out spi_out_type -- Spi-Outputs
);
end entity spi_oc;
architecture implementation of spi_oc is
constant data_width : integer := 8;
constant address_width : integer := 3;
constant REVISION : integer := 0;
constant pconfig : apb_config_type := (
0 => ahb_device_reg (VENDOR_GLEICHMANN, GLEICHMANN_SPIOC, 0, REVISION, pirq),
1 => apb_iobar(paddr, pmask)
);
signal irq : std_ulogic;
signal irq_1t : std_ulogic;
signal irq_adapt : std_ulogic; -- registered and converted to rising edge activity
begin
simple_spi_top_1 : simple_spi_top
port map (
prdata_o => apbo.prdata(data_width-1 downto 0),
pirq_o => irq,
sck_o => spi_out.sck,
mosi_o => spi_out.mosi,
ssn_o => spi_out.ssn,
pclk_i => clk,
prst_i => rstn,
psel_i => apbi.psel(pindex),
penable_i => apbi.penable,
paddr_i => apbi.paddr(address_width+1 downto 2), -- 32-bit addresses
pwrite_i => apbi.pwrite,
pwdata_i => apbi.pwdata(data_width-1 downto 0),
miso_i => spi_in.miso);
-- drive selected interrupt, remaining bits with zeroes
apbo.pirq(NAHBIRQ-1 downto pirq+1) <= (others => '0');
-- apbo.pirq(pirq) <= irq; -- corrected by MH, 28.11.2006
apbo.pirq(pirq) <= irq_adapt;
apbo.pirq(pirq-1 downto 0) <= (others => '0');
-- drive unused data bits with don't cares
apbo.prdata(31 downto data_width) <= (others => '0');
-- drive index for diagnostic use
apbo.pindex <= pindex;
-- drive slave configuration
apbo.pconfig <= pconfig;
---------------------------------------------------------------------------------------
-- Synchronous process to convert the high level interrupt from the core to
-- to an rising edge triggered interrupt to be suitable for the Leon IRQCTL
-- asynchronous low active reset like the open core simple SPI module !!!
---------------------------------------------------------------------------------------
irq_adaption: process (clk, rstn) -- added by MH, 28.11.2006
begin -- process irq_adaption)
if rstn = '0' then
irq_adapt <= '0';
irq_1t <= '0';
elsif clk'event and clk = '1' then
irq_1t <= irq;
irq_adapt <= irq and not irq_1t;
end if;
end process irq_adaption;
---------------------------------------------------------------------------------------
-- DEBUG SECTION
---------------------------------------------------------------------------------------
-- pragma translate_off
assert (pirq < 15 and pirq > 0 ) report
"Simple SPI Controller interrupt warning: " &
"0 does not exist, 15 is unmaskable, 16 to 31 are unused"
severity warning;
bootmsg : report_version
generic map ("SPI_OC: Simple SPI Controller rev " & tost(REVISION) &
", IRQ " & tost(pirq) &
", APB slave " & tost(pindex));
-- pragma translate_on
end architecture implementation;
| mit | 92cf3a24c399cab2faf55ef90c2350fb | 0.509662 | 3.896471 | false | false | false | false |
impedimentToProgress/UCI-BlueChip | AttackFiles/Attacks/privEsc/lib/gaisler/leon3/irqmp.vhd | 2 | 7,707 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: irqmp
-- File: irqmp.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: Multi-processor APB interrupt controller. Implements a
-- two-level interrupt controller for 15 interrupts.
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
library gaisler;
use gaisler.leon3.all;
entity irqmp is
generic (
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#fff#;
ncpu : integer := 1;
cmask : integer := 16#0001#
);
port (
rst : in std_ulogic;
clk : in std_ulogic;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
irqi : in irq_out_vector(0 to ncpu-1);
irqo : out irq_in_vector(0 to ncpu-1)
);
end;
architecture rtl of irqmp is
constant REVISION : integer := 3;
constant pconfig : apb_config_type := (
0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_IRQMP, 0, REVISION, 0),
1 => apb_iobar(paddr, pmask));
type mask_type is array (0 to ncpu-1) of std_logic_vector(15 downto 1);
type irl_type is array (0 to ncpu-1) of std_logic_vector(3 downto 0);
type reg_type is record
imask : mask_type;
ilevel : std_logic_vector(15 downto 1);
ipend : std_logic_vector(15 downto 1);
iforce : mask_type;
ibroadcast : std_logic_vector(15 downto 1);
irl : irl_type;
cpurst : std_logic_vector(ncpu-1 downto 0);
end record;
function prioritize(b : std_logic_vector(15 downto 1)) return std_logic_vector is
variable a : std_logic_vector(15 downto 0);
variable irl : std_logic_vector(3 downto 0);
variable level : integer range 0 to 15;
begin
irl := "0000"; level := 0; a := b & '0';
for i in 15 downto 0 loop
level := i;
if a(i) = '1' then exit; end if;
end loop;
irl := conv_std_logic_vector(level, 4);
return(irl);
end;
signal r, rin : reg_type;
begin
comb : process(rst, r, apbi, irqi)
variable v : reg_type;
variable temp : mask_type;
variable prdata : std_logic_vector(31 downto 0);
variable tmpirq : std_logic_vector(15 downto 0);
variable tmpvar : std_logic_vector(15 downto 1);
variable cpurun : std_logic_vector(ncpu-1 downto 0);
begin
v := r; v.cpurst := (others => '0');
cpurun := (others => '0'); cpurun(0) := '1';
tmpvar := (others => '0');
-- prioritize interrupts
for i in 0 to ncpu-1 loop
temp(i) := ((r.iforce(i) or r.ipend) and r.imask(i));
v.irl(i) := prioritize(temp(i) and r.ilevel);
if v.irl(i) = "0000" then
v.irl(i) := prioritize(temp(i) and not r.ilevel);
end if;
end loop;
-- register read
prdata := (others => '0');
case apbi.paddr(7 downto 6) is
when "00" =>
case apbi.paddr(4 downto 2) is
when "000" => prdata(15 downto 1) := r.ilevel;
when "001" => prdata(15 downto 1) := r.ipend;
when "010" => prdata(15 downto 1) := r.iforce(0);
when "011" =>
when others =>
prdata(31 downto 28) := conv_std_logic_vector(ncpu-1, 4);
for i in 0 to ncpu -1 loop prdata(i) := irqi(i).pwd; end loop;
if ncpu > 1 then
prdata(27) := '1';
case apbi.paddr(4 downto 2) is
when "101" =>
prdata := (others => '0');
prdata(15 downto 1) := r.ibroadcast;
when others =>
end case;
end if;
end case;
when "01" =>
for i in 0 to ncpu-1 loop
if i = conv_integer( apbi.paddr(5 downto 2)) then
prdata(15 downto 1) := r.imask(i);
end if;
end loop;
when "10" =>
for i in 0 to ncpu-1 loop
if i = conv_integer( apbi.paddr(5 downto 2)) then
prdata(15 downto 1) := r.iforce(i);
end if;
end loop;
when others =>
end case;
-- register write
if (apbi.psel(pindex) and apbi.penable and apbi.pwrite) = '1' then
case apbi.paddr(7 downto 6) is
when "00" =>
case apbi.paddr(4 downto 2) is
when "000" => v.ilevel := apbi.pwdata(15 downto 1);
when "001" => v.ipend := apbi.pwdata(15 downto 1);
when "010" => v.iforce(0) := apbi.pwdata(15 downto 1);
when "011" => v.ipend := r.ipend and not apbi.pwdata(15 downto 1);
when "100" =>
for i in 0 to ncpu -1 loop v.cpurst(i) := apbi.pwdata(i); end loop;
when others =>
if ncpu > 1 then
case apbi.paddr(4 downto 2) is
when "101" =>
v.ibroadcast := apbi.pwdata(15 downto 1);
when others =>
end case;
end if;
end case;
when "01" =>
for i in 0 to ncpu-1 loop
if i = conv_integer( apbi.paddr(5 downto 2)) then
v.imask(i) := apbi.pwdata(15 downto 1);
end if;
end loop;
when "10" =>
for i in 0 to ncpu-1 loop
if i = conv_integer( apbi.paddr(5 downto 2)) then
v.iforce(i) := (r.iforce(i) or apbi.pwdata(15 downto 1)) and
not apbi.pwdata(31 downto 17);
end if;
end loop;
when others =>
end case;
end if;
-- register new interrupts
for i in 1 to 15 loop
if i > NAHBIRQ-1 then
exit;
end if;
if ncpu = 1 then
v.ipend(i) := v.ipend(i) or apbi.pirq(i);
else
v.ipend(i) := v.ipend(i) or (apbi.pirq(i) and not r.ibroadcast(i));
for j in 0 to ncpu-1 loop
tmpvar := v.iforce(j);
tmpvar(i) := tmpvar(i) or (apbi.pirq(i) and r.ibroadcast(i));
v.iforce(j) := tmpvar;
end loop;
end if;
end loop;
-- interrupt acknowledge
for i in 0 to ncpu-1 loop
if irqi(i).intack = '1' then
tmpirq := decode(irqi(i).irl);
temp(i) := tmpirq(15 downto 1);
v.iforce(i) := v.iforce(i) and not temp(i);
v.ipend := v.ipend and not ((not r.iforce(i)) and temp(i));
end if;
end loop;
-- reset
if rst = '0' then
v.imask := (others => (others => '0'));
v.iforce := (others => (others => '0'));
v.ipend := (others => '0');
if ncpu > 1 then
v.ibroadcast := (others => '0');
end if;
end if;
apbo.prdata <= prdata;
for i in 0 to ncpu-1 loop
irqo(i).irl <= r.irl(i); irqo(i).rst <= r.cpurst(i);
irqo(i).run <= cpurun(i);
end loop;
rin <= v;
end process;
apbo.pirq <= (others => '0');
apbo.pconfig <= pconfig;
apbo.pindex <= pindex;
regs : process(clk)
begin if rising_edge(clk) then r <= rin; end if; end process;
-- pragma translate_off
bootmsg : report_version
generic map ("irqmp" &
": Multi-processor Interrupt Controller rev " & tost(REVISION) &
", #cpu " & tost(NCPU));
-- pragma translate_on
end;
| mit | e547c5a10e8d9ba3cef57aff1dad7ec4 | 0.566887 | 3.349413 | false | false | false | false |
impedimentToProgress/UCI-BlueChip | AttackFiles/Attacks/privEsc/lib/tech/atc18/components/atmel_simprims.vhd | 2 | 7,820 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: Various
-- File: atmel_simprims.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: ATMEL ATC18 behavioural models
-- Modelled after IO33/PCILIB data sheets
------------------------------------------------------------------------------
-- pragma translate_off
-- input pad
library ieee;
use ieee.std_logic_1164.all;
entity pc33d00z is port (pad : in std_logic; cin : out std_logic); end;
architecture rtl of pc33d00z is begin cin <= to_x01(pad) after 1 ns; end;
-- input pad with pull-up
library ieee;
use ieee.std_logic_1164.all;
entity pc33d00uz is port (pad : inout std_logic; cin : out std_logic); end;
architecture rtl of pc33d00uz is
begin cin <= to_x01(pad) after 1 ns; pad <= 'H'; end;
-- input schmitt pad
library ieee;
use ieee.std_logic_1164.all;
entity pc33d20z is port (pad : in std_logic; cin : out std_logic); end;
architecture rtl of pc33d20z is begin cin <= to_x01(pad) after 1 ns; end;
-- input schmitt pad with pull-up
library ieee;
use ieee.std_logic_1164.all;
entity pc33d20uz is port (pad : inout std_logic; cin : out std_logic); end;
architecture rtl of pc33d20uz is
begin cin <= to_x01(pad) after 1 ns; pad <= 'H'; end;
-- output pads
library ieee; use ieee.std_logic_1164.all;
entity pt33o01z is port (i : in std_logic; pad : out std_logic); end;
architecture rtl of pt33o01z is begin pad <= to_x01(i) after 2 ns; end;
library ieee; use ieee.std_logic_1164.all;
entity pt33o02z is port (i : in std_logic; pad : out std_logic); end;
architecture rtl of pt33o02z is begin pad <= to_x01(i) after 2 ns; end;
library ieee; use ieee.std_logic_1164.all;
entity pt33o04z is port (i : in std_logic; pad : out std_logic); end;
architecture rtl of pt33o04z is begin pad <= to_x01(i) after 2 ns; end;
library ieee; use ieee.std_logic_1164.all;
entity pt33o08z is port (i : in std_logic; pad : out std_logic); end;
architecture rtl of pt33o08z is begin pad <= to_x01(i) after 2 ns; end;
-- output tri-state pads
library ieee; use ieee.std_logic_1164.all;
entity pt33t01z is port (i, oen : in std_logic; pad : out std_logic); end;
architecture rtl of pt33t01z is
begin pad <= to_x01(i) after 2 ns when oen = '0' else 'H' after 2 ns; end;
library ieee; use ieee.std_logic_1164.all;
entity pt33t02z is port (i, oen : in std_logic; pad : out std_logic); end;
architecture rtl of pt33t02z is
begin pad <= to_x01(i) after 2 ns when oen = '0' else 'H' after 2 ns; end;
library ieee; use ieee.std_logic_1164.all;
entity pt33t04z is port (i, oen : in std_logic; pad : out std_logic); end;
architecture rtl of pt33t04z is
begin pad <= to_x01(i) after 2 ns when oen = '0' else 'H' after 2 ns; end;
library ieee; use ieee.std_logic_1164.all;
entity pt33t08z is port (i, oen : in std_logic; pad : out std_logic); end;
architecture rtl of pt33t08z is
begin pad <= to_x01(i) after 2 ns when oen = '0' else 'H' after 2 ns; end;
-- output tri-state pads with pull-up
library ieee; use ieee.std_logic_1164.all;
entity pt33t01uz is port (i, oen : in std_logic; pad : out std_logic); end;
architecture rtl of pt33t01uz is
begin pad <= to_x01(i) after 2 ns when oen = '0' else 'H' after 2 ns; end;
library ieee; use ieee.std_logic_1164.all;
entity pt33t02uz is port (i, oen : in std_logic; pad : out std_logic); end;
architecture rtl of pt33t02uz is
begin pad <= to_x01(i) after 2 ns when oen = '0' else 'H' after 2 ns; end;
library ieee; use ieee.std_logic_1164.all;
entity pt33t04uz is port (i, oen : in std_logic; pad : out std_logic); end;
architecture rtl of pt33t04uz is
begin pad <= to_x01(i) after 2 ns when oen = '0' else 'H' after 2 ns; end;
-- bidirectional pad
library ieee; use ieee.std_logic_1164.all;
entity pt33b01z is
port ( i, oen : in std_logic; cin : out std_logic; pad : inout std_logic);
end;
architecture rtl of pt33b01z is
begin
pad <= to_x01(i) after 2 ns when oen = '0' else 'Z' after 2 ns;
cin <= to_x01(pad) after 1 ns;
end;
library ieee; use ieee.std_logic_1164.all;
entity pt33b02z is
port ( i, oen : in std_logic; cin : out std_logic; pad : inout std_logic);
end;
architecture rtl of pt33b02z is
begin
pad <= to_x01(i) after 2 ns when oen = '0' else 'Z' after 2 ns;
cin <= to_x01(pad) after 1 ns;
end;
library ieee; use ieee.std_logic_1164.all;
entity pt33b08z is
port ( i, oen : in std_logic; cin : out std_logic; pad : inout std_logic);
end;
architecture rtl of pt33b08z is
begin
pad <= to_x01(i) after 2 ns when oen = '0' else 'Z' after 2 ns;
cin <= to_x01(pad) after 1 ns;
end;
library ieee; use ieee.std_logic_1164.all;
entity pt33b04z is
port ( i, oen : in std_logic; cin : out std_logic; pad : inout std_logic);
end;
architecture rtl of pt33b04z is
begin
pad <= to_x01(i) after 2 ns when oen = '0' else 'Z' after 2 ns;
cin <= to_x01(pad) after 1 ns;
end;
-- bidirectional pads with pull-up
library ieee;
use ieee.std_logic_1164.all;
entity pt33b01uz is
port ( i, oen : in std_logic; cin : out std_logic; pad : inout std_logic);
end;
architecture rtl of pt33b01uz is
begin
pad <= to_x01(i) after 2 ns when oen = '0' else 'H' after 2 ns;
cin <= to_x01(pad) after 1 ns;
end;
library ieee;
use ieee.std_logic_1164.all;
entity pt33b02uz is
port ( i, oen : in std_logic; cin : out std_logic; pad : inout std_logic);
end;
architecture rtl of pt33b02uz is
begin
pad <= to_x01(i) after 2 ns when oen = '0' else 'H' after 2 ns;
cin <= to_x01(pad) after 1 ns;
end;
library ieee;
use ieee.std_logic_1164.all;
entity pt33b08uz is
port ( i, oen : in std_logic; cin : out std_logic; pad : inout std_logic);
end;
architecture rtl of pt33b08uz is
begin
pad <= to_x01(i) after 2 ns when oen = '0' else 'H' after 2 ns;
cin <= to_x01(pad) after 1 ns;
end;
library ieee;
use ieee.std_logic_1164.all;
entity pt33b04uz is
port ( i, oen : in std_logic; cin : out std_logic; pad : inout std_logic);
end;
architecture rtl of pt33b04uz is
begin
pad <= to_x01(i) after 2 ns when oen = '0' else 'H' after 2 ns;
cin <= to_x01(pad) after 1 ns;
end;
-- PCI output pad
library ieee; use ieee.std_logic_1164.all;
entity pp33o01z is port (i : in std_logic; pad : out std_logic); end;
architecture rtl of pp33o01z is begin pad <= to_x01(i) after 2 ns; end;
-- PCI bidirectional pad
library ieee; use ieee.std_logic_1164.all;
entity pp33b01z is
port ( i, oen : in std_logic; cin : out std_logic; pad : inout std_logic);
end;
architecture rtl of pp33b01z is
begin
pad <= to_x01(i) after 2 ns when oen = '0' else 'Z' after 2 ns;
cin <= to_x01(pad) after 1 ns;
end;
-- PCI output tri-state pad
library ieee; use ieee.std_logic_1164.all;
entity pp33t01z is port (i, oen : in std_logic; pad : out std_logic); end;
architecture rtl of pp33t01z is
begin pad <= to_x01(i) after 2 ns when oen = '0' else 'Z' after 2 ns; end;
-- pragma translate_on
| mit | e370a2515c6a8a7401dd182d081cf395 | 0.667647 | 2.86762 | false | false | false | false |
impedimentToProgress/UCI-BlueChip | AttackFiles/Attacks/privEsc/lib/techmap/atc18/pads_atc18.vhd | 2 | 10,044 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Package: atcpads_gen
-- File: atcpads_gen.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: Atmel ATC18 pad wrappers
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
package atcpads is
-- input pad
component pc33d00z port (pad : in std_logic; cin : out std_logic); end component;
-- input pad with pull-up
component pc33d00uz port (pad : in std_logic; cin : out std_logic); end component;
-- schmitt input pad
component pc33d20z port (pad : in std_logic; cin : out std_logic); end component;
-- schmitt input pad with pull-up
component pt33d20uz port (pad : inout std_logic; cin : out std_logic); end component;
-- output pads
component pt33o01z port (i : in std_logic; pad : out std_logic); end component;
component pt33o02z port (i : in std_logic; pad : out std_logic); end component;
component pt33o04z port (i : in std_logic; pad : out std_logic); end component;
component pt33o08z port (i : in std_logic; pad : out std_logic); end component;
-- tri-state output pads
component pt33t01z port (i, oen : in std_logic; pad : out std_logic); end component;
component pt33t02z port (i, oen : in std_logic; pad : out std_logic); end component;
component pt33t04z port (i, oen : in std_logic; pad : out std_logic); end component;
component pt33t08z port (i, oen : in std_logic; pad : out std_logic); end component;
-- tri-state output pads with pull-up
component pt33t01uz port (i, oen : in std_logic; pad : out std_logic); end component;
component pt33t02uz port (i, oen : in std_logic; pad : out std_logic); end component;
component pt33t04uz port (i, oen : in std_logic; pad : out std_logic); end component;
component pt33t08uz port (i, oen : in std_logic; pad : out std_logic); end component;
-- bidirectional pads
component pt33b01z
port (i, oen : in std_logic; cin : out std_logic; pad : inout std_logic);
end component;
component pt33b02z
port (i, oen : in std_logic; cin : out std_logic; pad : inout std_logic);
end component;
component pt33b08z
port (i, oen : in std_logic; cin : out std_logic; pad : inout std_logic);
end component;
component pt33b04z
port (i, oen : in std_logic; cin : out std_logic; pad : inout std_logic);
end component;
-- bidirectional pads with pull-up
component pt33b01uz
port (i, oen : in std_logic; cin : out std_logic; pad : inout std_logic);
end component;
component pt33b02uz
port (i, oen : in std_logic; cin : out std_logic; pad : inout std_logic);
end component;
component pt33b08uz
port (i, oen : in std_logic; cin : out std_logic; pad : inout std_logic);
end component;
component pt33b04uz
port (i, oen : in std_logic; cin : out std_logic; pad : inout std_logic);
end component;
--PCI pads
component pp33o01z
port (i : in std_logic; pad : out std_logic);
end component;
component pp33b01z
port ( i, oen : in std_logic; cin : out std_logic; pad : inout std_logic);
end component;
component pp33t01z
port (i, oen : in std_logic; pad : out std_logic);
end component;
end;
library ieee;
library techmap;
use ieee.std_logic_1164.all;
use techmap.gencomp.all;
-- pragma translate_off
library atc18;
use atc18.pc33d00z;
-- pragma translate_on
entity atc18_inpad is
generic (level : integer := 0; voltage : integer := 0);
port (pad : in std_logic; o : out std_logic);
end;
architecture rtl of atc18_inpad is
component pc33d00z port (pad : in std_logic; cin : out std_logic); end component;
begin
pci0 : if level = pci33 generate
ip : pc33d00z port map (pad => pad, cin => o);
end generate;
gen0 : if level /= pci33 generate
ip : pc33d00z port map (pad => pad, cin => o);
end generate;
end;
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
-- pragma translate_off
library atc18;
use atc18.pp33b01z;
use atc18.pt33b01z;
use atc18.pt33b02z;
use atc18.pt33b08z;
use atc18.pt33b04z;
-- pragma translate_on
entity atc18_iopad is
generic (level : integer := 0; slew : integer := 0;
voltage : integer := 0; strength : integer := 0);
port (pad : inout std_logic; i, en : in std_logic; o : out std_logic);
end ;
architecture rtl of atc18_iopad is
component pp33b01z
port ( i, oen : in std_logic; cin : out std_logic; pad : inout std_logic);
end component;
component pt33b01z
port (i, oen : in std_logic; cin : out std_logic; pad : inout std_logic);
end component;
component pt33b02z
port (i, oen : in std_logic; cin : out std_logic; pad : inout std_logic);
end component;
component pt33b08z
port (i, oen : in std_logic; cin : out std_logic; pad : inout std_logic);
end component;
component pt33b04z
port (i, oen : in std_logic; cin : out std_logic; pad : inout std_logic);
end component;
begin
pci0 : if level = pci33 generate
op : pp33b01z port map (i => i, oen => en, pad => pad, cin => o);
end generate;
gen0 : if level /= pci33 generate
f1 : if (strength <= 4) generate
op : pt33b01z port map (i => i, oen => en, pad => pad, cin => o);
end generate;
f2 : if (strength > 4) and (strength <= 8) generate
op : pt33b02z port map (i => i, oen => en, pad => pad, cin => o);
end generate;
f3 : if (strength > 8) and (strength <= 16) generate
op : pt33b04z port map (i => i, oen => en, pad => pad, cin => o);
end generate;
f4 : if (strength > 16) generate
op : pt33b08z port map (i => i, oen => en, pad => pad, cin => o);
end generate;
end generate;
end;
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
-- pragma translate_off
library atc18;
use atc18.pp33t01z;
use atc18.pt33o01z;
use atc18.pt33o02z;
use atc18.pt33o04z;
use atc18.pt33o08z;
-- pragma translate_on
entity atc18_outpad is
generic (level : integer := 0; slew : integer := 0;
voltage : integer := 0; strength : integer := 0);
port (pad : out std_logic; i : in std_logic);
end ;
architecture rtl of atc18_outpad is
component pp33t01z
port (i, oen : in std_logic; pad : out std_logic);
end component;
component pt33o01z port (i : in std_logic; pad : out std_logic); end component;
component pt33o02z port (i : in std_logic; pad : out std_logic); end component;
component pt33o04z port (i : in std_logic; pad : out std_logic); end component;
component pt33o08z port (i : in std_logic; pad : out std_logic); end component;
signal gnd : std_logic;
begin
gnd <= '0';
pci0 : if level = pci33 generate
op : pp33t01z port map (i => i, oen => gnd, pad => pad);
end generate;
gen0 : if level /= pci33 generate
f4 : if (strength <= 4) generate
op : pt33o01z port map (i => i, pad => pad);
end generate;
f8 : if (strength > 4) and (strength <= 8) generate
op : pt33o02z port map (i => i, pad => pad);
end generate;
f16 : if (strength > 8) and (strength <= 16) generate
op : pt33o04z port map (i => i, pad => pad);
end generate;
f32 : if (strength > 16) generate
op : pt33o08z port map (i => i, pad => pad);
end generate;
end generate;
end;
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
-- pragma translate_off
library atc18;
use atc18.pp33t01z;
use atc18.pt33t01z;
use atc18.pt33t02z;
use atc18.pt33t04z;
use atc18.pt33t08z;
-- pragma translate_on
entity atc18_toutpad is
generic (level : integer := 0; slew : integer := 0;
voltage : integer := 0; strength : integer := 0);
port (pad : out std_logic; i, en : in std_logic);
end ;
architecture rtl of atc18_toutpad is
component pp33t01z
port (i, oen : in std_logic; pad : out std_logic);
end component;
component pt33t01z port (i, oen : in std_logic; pad : out std_logic); end component;
component pt33t02z port (i, oen : in std_logic; pad : out std_logic); end component;
component pt33t04z port (i, oen : in std_logic; pad : out std_logic); end component;
component pt33t08z port (i, oen : in std_logic; pad : out std_logic); end component;
begin
pci0 : if level = pci33 generate
op : pp33t01z port map (i => i, oen => en, pad => pad);
end generate;
gen0 : if level /= pci33 generate
f4 : if (strength <= 4) generate
op : pt33t01z port map (i => i, oen => en, pad => pad);
end generate;
f8 : if (strength > 4) and (strength <= 8) generate
op : pt33t02z port map (i => i, oen => en, pad => pad);
end generate;
f16 : if (strength > 8) and (strength <= 16) generate
op : pt33t04z port map (i => i, oen => en, pad => pad);
end generate;
f32 : if (strength > 16) generate
op : pt33t08z port map (i => i, oen => en, pad => pad);
end generate;
end generate;
end;
library ieee;
use ieee.std_logic_1164.all;
entity atc18_clkpad is
generic (level : integer := 0; voltage : integer := 0);
port (pad : in std_logic; o : out std_logic);
end;
architecture rtl of atc18_clkpad is
begin
o <= pad;
end;
| mit | ddca28543e4f43bd774b243f03b1463d | 0.646854 | 3.207921 | false | false | false | false |
franz/pocl | examples/accel/rtl/gcu_ic/input_mux_2.vhdl | 2 | 1,021 | library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use work.tce_util.all;
entity ffaccel_input_mux_2 is
generic (
BUSW_0 : integer := 32;
BUSW_1 : integer := 32;
DATAW : integer := 32);
port (
databus0 : in std_logic_vector(BUSW_0-1 downto 0);
databus1 : in std_logic_vector(BUSW_1-1 downto 0);
data : out std_logic_vector(DATAW-1 downto 0);
databus_cntrl : in std_logic_vector(0 downto 0));
end ffaccel_input_mux_2;
architecture rtl of ffaccel_input_mux_2 is
begin
-- If width of input bus is greater than width of output,
-- using the LSB bits.
-- If width of input bus is smaller than width of output,
-- using zero extension to generate extra bits.
sel : process (databus_cntrl, databus0, databus1)
begin
data <= (others => '0');
case databus_cntrl is
when "0" =>
data <= tce_ext(databus0, data'length);
when others =>
data <= tce_ext(databus1, data'length);
end case;
end process sel;
end rtl;
| mit | 21d324328b38f796159a59b112057383 | 0.646425 | 3.272436 | false | false | false | false |
impedimentToProgress/UCI-BlueChip | AttackFiles/Attacks/privEsc/lib/gaisler/misc/logan.vhd | 2 | 16,852 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: logan
-- File: logan.vhd
-- Author: Kristoffer Carlsson, Gaisler Research
-- Description: On-chip logic analyzer IP core
-----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
library techmap;
use techmap.gencomp.all;
entity logan is
generic (
dbits : integer range 0 to 256 := 32; -- Number of traced signals
depth : integer range 256 to 16384 := 1024; -- Depth of trace buffer
trigl : integer range 1 to 63 := 1; -- Number of trigger levels
usereg : integer range 0 to 1 := 1; -- Use input register
usequal : integer range 0 to 1 := 0; -- Use qualifer bit
usediv : integer range 0 to 1 := 1; -- Enable/disable div counter
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#F00#;
memtech : integer := DEFMEMTECH);
port (
rstn : in std_logic; -- Synchronous reset
clk : in std_logic; -- System clock
tclk : in std_logic; -- Trace clock
apbi : in apb_slv_in_type; -- APB in record
apbo : out apb_slv_out_type; -- APB out record
signals : in std_logic_vector(dbits - 1 downto 0)); -- Traced signals
end logan;
architecture rtl of logan is
constant REVISION : amba_version_type := 0;
constant pconfig : apb_config_type := (
0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_LOGAN, 0, REVISION, 0),
1 => apb_iobar(paddr, pmask));
constant abits: integer := 8 + log2x(depth/256 - 1);
constant az : std_logic_vector(abits-1 downto 0) := (others => '0');
constant dz : std_logic_vector(dbits-1 downto 0) := (others => '0');
type trig_cfg_type is record
pattern : std_logic_vector(dbits-1 downto 0); -- Pattern to trig on
mask : std_logic_vector(dbits-1 downto 0); -- trigger mask
count : std_logic_vector(5 downto 0); -- match counter
eq : std_ulogic; -- Trig on match or no match?
end record;
type trig_cfg_arr is array (0 to trigl-1) of trig_cfg_type;
type reg_type is record
armed : std_ulogic;
trig_demet : std_ulogic;
trigged : std_ulogic;
fin_demet : std_ulogic;
finished : std_ulogic;
qualifier : std_logic_vector(7 downto 0);
qual_val : std_ulogic;
divcount : std_logic_vector(15 downto 0);
counter : std_logic_vector(abits-1 downto 0);
page : std_logic_vector(3 downto 0);
trig_conf : trig_cfg_arr;
end record;
type trace_reg_type is record
armed : std_ulogic;
arm_demet : std_ulogic;
trigged : std_ulogic;
finished : std_ulogic;
sample : std_ulogic;
divcounter : std_logic_vector(15 downto 0);
match_count : std_logic_vector(5 downto 0);
counter : std_logic_vector(abits-1 downto 0);
curr_tl : integer range 0 to trigl-1;
w_addr : std_logic_vector(abits-1 downto 0);
end record;
signal r_addr : std_logic_vector(13 downto 0);
signal bufout : std_logic_vector(255 downto 0);
signal r_en : std_ulogic;
signal r, rin : reg_type;
signal tr, trin : trace_reg_type;
signal sigreg : std_logic_vector(dbits-1 downto 0);
signal sigold : std_logic_vector(dbits-1 downto 0);
begin
bufout(255 downto dbits) <= (others => '0');
-- Combinatorial process for AMBA clock domain
comb1: process(rstn, apbi, r, tr, bufout)
variable v : reg_type;
variable rdata : std_logic_vector(31 downto 0);
variable tl : integer range 0 to trigl-1;
variable pattern, mask : std_logic_vector(255 downto 0);
begin
v := r;
rdata := (others => '0'); tl := 0;
pattern := (others => '0'); mask := (others => '0');
-- Two stage synch
v.trig_demet := tr.trigged;
v.trigged := r.trig_demet;
v.fin_demet := tr.finished;
v.finished := r.fin_demet;
if r.finished = '1' then
v.armed := '0';
end if;
r_en <= '0';
-- Read/Write --
if apbi.psel(pindex) = '1' then
-- Write
if apbi.pwrite = '1' and apbi.penable = '1' then
-- Only conf area writeable
if apbi.paddr(15) = '0' then
-- pattern/mask
if apbi.paddr(14 downto 13) = "11" then
tl := conv_integer(apbi.paddr(11 downto 6));
pattern(dbits-1 downto 0) := v.trig_conf(tl).pattern;
mask(dbits-1 downto 0) := v.trig_conf(tl).mask;
case apbi.paddr(5 downto 2) is
when "0000" => pattern(31 downto 0) := apbi.pwdata;
when "0001" => pattern(63 downto 32) := apbi.pwdata;
when "0010" => pattern(95 downto 64) := apbi.pwdata;
when "0011" => pattern(127 downto 96) := apbi.pwdata;
when "0100" => pattern(159 downto 128) := apbi.pwdata;
when "0101" => pattern(191 downto 160) := apbi.pwdata;
when "0110" => pattern(223 downto 192) := apbi.pwdata;
when "0111" => pattern(255 downto 224) := apbi.pwdata;
when "1000" => mask(31 downto 0) := apbi.pwdata;
when "1001" => mask(63 downto 32) := apbi.pwdata;
when "1010" => mask(95 downto 64) := apbi.pwdata;
when "1011" => mask(127 downto 96) := apbi.pwdata;
when "1100" => mask(159 downto 128) := apbi.pwdata;
when "1101" => mask(191 downto 160) := apbi.pwdata;
when "1110" => mask(223 downto 192) := apbi.pwdata;
when "1111" => mask(255 downto 224) := apbi.pwdata;
when others => null;
end case;
-- write back updated pattern/mask
v.trig_conf(tl).pattern := pattern(dbits-1 downto 0);
v.trig_conf(tl).mask := mask(dbits-1 downto 0);
-- count/eq
elsif apbi.paddr(14 downto 13) = "01" then
tl := conv_integer(apbi.paddr(7 downto 2));
v.trig_conf(tl).count := apbi.pwdata(6 downto 1);
v.trig_conf(tl).eq := apbi.pwdata(0);
-- arm/reset
elsif apbi.paddr(14 downto 13)&apbi.paddr(4 downto 2) = "00000" then
v.armed := apbi.pwdata(0);
-- Page reg
elsif apbi.paddr(14 downto 13)&apbi.paddr(4 downto 2) = "00010" then
v.page := apbi.pwdata(3 downto 0);
-- Trigger counter
elsif apbi.paddr(14 downto 13)&apbi.paddr(4 downto 2) = "00011" then
v.counter := apbi.pwdata(abits-1 downto 0);
-- div count
elsif apbi.paddr(14 downto 13)&apbi.paddr(4 downto 2) = "00100" then
v.divcount := apbi.pwdata(15 downto 0);
-- qualifier bit
elsif apbi.paddr(14 downto 13)&apbi.paddr(4 downto 2) = "00101" then
v.qualifier := apbi.pwdata(7 downto 0);
v.qual_val := apbi.pwdata(8);
end if;
end if;
-- end write
-- Read
else
-- Read config/status area
if apbi.paddr(15) = '0' then
-- pattern/mask
if apbi.paddr(14 downto 13) = "11" then
tl := conv_integer(apbi.paddr(11 downto 6));
pattern(dbits-1 downto 0) := v.trig_conf(tl).pattern;
mask(dbits-1 downto 0) := v.trig_conf(tl).mask;
case apbi.paddr(5 downto 2) is
when "0000" => rdata := pattern(31 downto 0);
when "0001" => rdata := pattern(63 downto 32);
when "0010" => rdata := pattern(95 downto 64);
when "0011" => rdata := pattern(127 downto 96);
when "0100" => rdata := pattern(159 downto 128);
when "0101" => rdata := pattern(191 downto 160);
when "0110" => rdata := pattern(223 downto 192);
when "0111" => rdata := pattern(255 downto 224);
when "1000" => rdata := mask(31 downto 0);
when "1001" => rdata := mask(63 downto 32);
when "1010" => rdata := mask(95 downto 64);
when "1011" => rdata := mask(127 downto 96);
when "1100" => rdata := mask(159 downto 128);
when "1101" => rdata := mask(191 downto 160);
when "1110" => rdata := mask(223 downto 192);
when "1111" => rdata := mask(255 downto 224);
when others => rdata := (others => '0');
end case;
-- count/eq
elsif apbi.paddr(14 downto 13) = "01" then
tl := conv_integer(apbi.paddr(7 downto 2));
rdata(6 downto 1) := v.trig_conf(tl).count;
rdata(0) := v.trig_conf(tl).eq;
-- status
elsif apbi.paddr(14 downto 13)&apbi.paddr(4 downto 2) = "00000" then
rdata := conv_std_logic_vector(usereg,1) & conv_std_logic_vector(usequal,1) &
r.armed & r.trigged &
conv_std_logic_vector(dbits,8)&
conv_std_logic_vector(depth-1,14)&
conv_std_logic_vector(trigl,6);
-- trace buffer index
elsif apbi.paddr(14 downto 13)&apbi.paddr(4 downto 2) = "00001" then
rdata(abits-1 downto 0) := tr.w_addr(abits-1 downto 0);
-- page reg
elsif apbi.paddr(14 downto 13)&apbi.paddr(4 downto 2) = "00010" then
rdata(3 downto 0) := r.page;
-- trigger counter
elsif apbi.paddr(14 downto 13)&apbi.paddr(4 downto 2) = "00011" then
rdata(abits-1 downto 0) := r.counter;
-- divcount
elsif apbi.paddr(14 downto 13)&apbi.paddr(4 downto 2) = "00100" then
rdata(15 downto 0) := r.divcount;
-- qualifier
elsif apbi.paddr(14 downto 13)&apbi.paddr(4 downto 2) = "00101" then
rdata(7 downto 0) := r.qualifier;
rdata(8) := r.qual_val;
end if;
-- Read from trace buffer
else
-- address always r.page & apbi.paddr(14 downto 5)
r_en <= '1';
-- Select word from pattern
case apbi.paddr(4 downto 2) is
when "000" => rdata := bufout(31 downto 0);
when "001" => rdata := bufout(63 downto 32);
when "010" => rdata := bufout(95 downto 64);
when "011" => rdata := bufout(127 downto 96);
when "100" => rdata := bufout(159 downto 128);
when "101" => rdata := bufout(191 downto 160);
when "110" => rdata := bufout(223 downto 192);
when "111" => rdata := bufout(255 downto 224);
when others => rdata := (others => '0');
end case;
end if;
end if; -- end read
end if;
if rstn = '0' then
v.armed := '0'; v.trigged := '0'; v.finished := '0'; v.trig_demet := '0'; v.fin_demet := '0';
v.counter := (others => '0');
v.divcount := X"0001";
v.qualifier := (others => '0');
v.qual_val := '0';
v.page := (others => '0');
end if;
apbo.prdata <= rdata;
rin <= v;
end process;
-- Combinatorial process for trace clock domain
comb2 : process (rstn, tr, r, sigreg)
variable v : trace_reg_type;
begin
v := tr;
v.sample := '0';
if tr.armed = '0' then
v.trigged := '0'; v.counter := (others => '0'); v.curr_tl := 0;
end if;
-- Synch arm signal
v.arm_demet := r.armed;
v.armed := tr.arm_demet;
if tr.finished = '1' then
v.finished := tr.armed;
end if;
-- Trigger --
if tr.armed = '1' and tr.finished = '0' then
if usediv = 1 then
if tr.divcounter = X"0000" then
v.divcounter := r.divcount-1;
if usequal = 0 or sigreg(conv_integer(r.qualifier)) = r.qual_val then
v.sample := '1';
end if;
else
v.divcounter := v.divcounter - 1;
end if;
else
v.sample := '1';
end if;
if tr.sample = '1' then v.w_addr := tr.w_addr + 1; end if;
if tr.trigged = '1' and tr.sample = '1' then
if tr.counter = r.counter then
v.trigged := '0';
v.sample := '0';
v.finished := '1';
v.counter := (others => '0');
else v.counter := tr.counter + 1; end if;
else
-- match?
if ((sigreg xor r.trig_conf(tr.curr_tl).pattern) and r.trig_conf(tr.curr_tl).mask) = dz then
-- trig on equal
if r.trig_conf(tr.curr_tl).eq = '1' then
if tr.match_count /= r.trig_conf(tr.curr_tl).count then
v.match_count := tr.match_count + 1;
else
-- final match?
if tr.curr_tl = trigl-1 then
v.trigged := '1';
else
v.curr_tl := tr.curr_tl + 1;
end if;
end if;
end if;
else -- not a match
-- trig on inequal
if r.trig_conf(tr.curr_tl).eq = '0' then
if tr.match_count /= r.trig_conf(tr.curr_tl).count then
v.match_count := tr.match_count + 1;
else
-- final match?
if tr.curr_tl = trigl-1 then
v.trigged := '1';
else
v.curr_tl := tr.curr_tl + 1;
end if;
end if;
end if;
end if;
end if;
end if;
-- end trigger
if rstn = '0' then
v.armed := '0'; v.trigged := '0'; v.sample := '0'; v.finished := '0'; v.arm_demet := '0';
v.curr_tl := 0;
v.counter := (others => '0');
v.divcounter := (others => '0');
v.match_count := (others => '0');
v.w_addr := (others => '0');
end if;
trin <= v;
end process;
-- clk traced signals through register to minimize fan out
inreg: if usereg = 1 generate
process (tclk)
begin
if rising_edge(tclk) then
sigold <= sigreg;
sigreg <= signals;
end if;
end process;
end generate;
noinreg: if usereg = 0 generate
sigreg <= signals;
sigold <= signals;
end generate;
-- Update registers
reg: process(clk)
begin
if rising_edge(clk) then r <= rin; end if;
end process;
treg: process(tclk)
begin
if rising_edge(tclk) then tr <= trin; end if;
end process;
r_addr <= r.page & apbi.paddr(14 downto 5);
trace_buf : syncram_2p
generic map (tech => memtech, abits => abits, dbits => dbits)
port map (clk, r_en, r_addr(abits-1 downto 0), bufout(dbits-1 downto 0), -- read
tclk, tr.sample, tr.w_addr, sigold); -- write
apbo.pconfig <= pconfig;
apbo.pindex <= pindex;
apbo.pirq <= (others => '0');
end architecture;
| mit | 49afeff601782366e751e0a4b42c317b | 0.496796 | 3.865138 | false | false | false | false |
impedimentToProgress/UCI-BlueChip | AttackFiles/Attacks/privEsc/lib/gaisler/sim/sim.vhd | 2 | 15,670 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Package: sim
-- File: sim.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: Simulation models and functions declarations
------------------------------------------------------------------------------
-- pragma translate_off
library ieee;
use ieee.std_logic_1164.all;
use std.textio.all;
library grlib;
use grlib.stdlib.all;
use grlib.stdio.all;
use grlib.amba.all;
package sim is
component sram
generic (index : integer := 0; -- Byte lane (0 - 3)
Abits: Positive := 10; -- Default 10 address bits (1 Kbyte)
tacc : integer := 10; -- access time (ns)
fname : string := "ram.dat"; -- File to read from
clear : integer := 0); -- Clear memory
port (
a : in std_logic_vector(abits-1 downto 0);
D : inout std_logic_vector(7 downto 0);
CE1 : in std_logic;
WE : in std_logic;
OE : in std_logic);
end component;
component sram16
generic (
index : integer := 0; -- Byte lane (0 - 3)
abits: Positive := 10; -- Default 10 address bits (1 Kbyte)
echk : integer := 0; -- Generate EDAC checksum
tacc : integer := 10; -- access time (ns)
fname : string := "ram.dat"); -- File to read from
port (
a : in std_logic_vector(abits-1 downto 0);
d : inout std_logic_vector(15 downto 0);
lb : in std_logic;
ub : in std_logic;
ce : in std_logic;
we : in std_ulogic;
oe : in std_ulogic);
end component;
component sramft
generic (index : integer := 0; -- Byte lane (0 - 3)
Abits: Positive := 10; -- Default 10 address bits (1 Kbyte)
tacc : integer := 10; -- access time (ns)
fname : string := "ram.dat"); -- File to read from
port (
a : in std_logic_vector(abits-1 downto 0);
D : inout std_logic_vector(7 downto 0);
CE1 : in std_logic;
WE : in std_logic;
OE : in std_logic);
end component;
procedure hexread(L : inout line; value:out bit_vector);
procedure hexread(L : inout line; value:out std_logic_vector);
function ishex(c : character) return boolean;
function buskeep(signal v : in std_logic_vector) return std_logic_vector;
function buskeep(signal c : in std_logic) return std_logic;
component phy is
generic(
address : integer range 0 to 31 := 0;
extended_regs : integer range 0 to 1 := 1;
aneg : integer range 0 to 1 := 1;
base100_t4 : integer range 0 to 1 := 0;
base100_x_fd : integer range 0 to 1 := 1;
base100_x_hd : integer range 0 to 1 := 1;
fd_10 : integer range 0 to 1 := 1;
hd_10 : integer range 0 to 1 := 1;
base100_t2_fd : integer range 0 to 1 := 1;
base100_t2_hd : integer range 0 to 1 := 1;
base1000_x_fd : integer range 0 to 1 := 0;
base1000_x_hd : integer range 0 to 1 := 0;
base1000_t_fd : integer range 0 to 1 := 1;
base1000_t_hd : integer range 0 to 1 := 1
);
port(
rstn : in std_logic;
mdio : inout std_logic;
tx_clk : out std_logic;
rx_clk : out std_logic;
rxd : out std_logic_vector(7 downto 0);
rx_dv : out std_logic;
rx_er : out std_logic;
rx_col : out std_logic;
rx_crs : out std_logic;
txd : in std_logic_vector(7 downto 0);
tx_en : in std_logic;
tx_er : in std_logic;
mdc : in std_logic;
gtx_clk : in std_logic
);
end component;
type ata_in_type is record --signals from host to device
csel : std_logic; --cable select
cs : std_logic_vector(1 downto 0); --chip select
--dd : std_logic_vector(15 downto 0); --data bus
dasp : std_logic; --Device active / slave present
da : std_logic_vector(2 downto 0); --device adress
dmack: std_logic; --DMA acknowledge
dior : std_logic; --I/O read strobe
diow : std_logic; --I/O write strobe
reset: std_logic; --Reset
end record;
constant ATAI_RESET_VECTOR : ata_in_type := ('0',(others=>'0'),'0',
(others=>'0'),'0','0','0','0');
type ata_out_type is record --signals from device to host
dmarq: std_logic; --DMA request
intrq: std_logic; --Interrupt request
iordy: std_logic; --I/O ready
pdiag: std_logic; --Passed diagnostics
end record;
constant ATAO_RESET_VECTOR : ata_out_type := ('0','0','1','0');
component ata_device is
generic(sector_length: integer :=512; --in bytes
disk_size: integer :=32; --in sectors
log2_size : integer :=14; --Log2(sector_length*disk_size), abits
Tlr : time := 35 ns
);
port(
--for convinience, not part of ATA interface
clk : in std_logic;
rst : in std_logic;
--interface to host bus adapter
d : inout std_logic_vector(15 downto 0) := (others=>'Z');
atai : in ata_in_type := ATAI_RESET_VECTOR;
atao : out ata_out_type:= ATAO_RESET_VECTOR);
end component;
procedure leon3_subtest(subtest : integer);
procedure mctrl_subtest(subtest : integer);
procedure gptimer_subtest(subtest : integer);
procedure dsu3_subtest(subtest : integer);
procedure spw_subtest(subtest : integer);
procedure spictrl_subtest(subtest : integer);
procedure i2cmst_subtest(subtest : integer);
procedure uhc_subtest(subtest : integer);
procedure ehc_subtest(subtest : integer);
component ahbrep
generic (
hindex : integer := 0;
haddr : integer := 0;
hmask : integer := 16#fff#;
halt : integer := 1);
port (
rst : in std_ulogic;
clk : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type
);
end component;
component i2c_slave_model
port (
scl : inout std_logic;
sda : inout std_logic
);
end component;
component ulpi
generic (
LSDEV : boolean := false -- Low-Speed device attached
);
port (
clkout : out std_ulogic;
d : inout std_logic_vector(7 downto 0);
nxt : out std_ulogic;
stp : in std_ulogic;
dir : out std_ulogic;
resetn : in std_ulogic
);
end component;
component utmi
generic (
LSDEV : boolean := false; -- Low-Speed device attached
utmi_dw8 : integer -- Interface data width
);
port (
uclk : out std_ulogic;
xcvrsel : in std_logic_vector(1 downto 0);
termsel : in std_ulogic;
suspendm : in std_ulogic;
opmode : in std_logic_vector(1 downto 0);
txvalid : in std_ulogic;
drvvbus : in std_ulogic;
validho : in std_ulogic;
host : in std_ulogic;
utm_rst : in std_ulogic;
linestate : out std_logic_vector(1 downto 0);
txready : out std_ulogic;
rxvalid : out std_ulogic;
rxactive : out std_ulogic;
rxerror : out std_ulogic;
vbusvalid : out std_ulogic;
validhi : out std_ulogic;
hostdisc : out std_ulogic;
datah : inout std_logic_vector(7 downto 0);
data : inout std_logic_vector(7 downto 0)
);
end component;
end;
package body sim is
function to_xlhz(i : std_logic) return std_logic is
begin
case to_X01Z(i) is
when 'Z' => return('Z');
when '0' => return('L');
when '1' => return('H');
when others => return('X');
end case;
end;
type logic_xlhz_table IS ARRAY (std_logic'LOW TO std_logic'HIGH) OF std_logic;
constant cvt_to_xlhz : logic_xlhz_table := (
'Z', -- 'U'
'Z', -- 'X'
'L', -- '0'
'H', -- '1'
'Z', -- 'Z'
'Z', -- 'W'
'L', -- 'L'
'H', -- 'H'
'Z' -- '-'
);
function buskeep (signal v : in std_logic_vector) return std_logic_vector is
variable res : std_logic_vector(v'range);
begin
for i in v'range loop res(i) := cvt_to_xlhz(v(i)); end loop;
return(res);
end;
function buskeep (signal c : in std_logic) return std_logic is
begin
return(cvt_to_xlhz(c));
end;
procedure char2hex(C: character; result: out bit_vector(3 downto 0);
good: out boolean; report_error: in boolean) is
begin
good := true;
case C is
when '0' => result := x"0";
when '1' => result := x"1";
when '2' => result := X"2";
when '3' => result := X"3";
when '4' => result := X"4";
when '5' => result := X"5";
when '6' => result := X"6";
when '7' => result := X"7";
when '8' => result := X"8";
when '9' => result := X"9";
when 'A' => result := X"A";
when 'B' => result := X"B";
when 'C' => result := X"C";
when 'D' => result := X"D";
when 'E' => result := X"E";
when 'F' => result := X"F";
when 'a' => result := X"A";
when 'b' => result := X"B";
when 'c' => result := X"C";
when 'd' => result := X"D";
when 'e' => result := X"E";
when 'f' => result := X"F";
when others =>
if report_error then
assert false report
"hexread error: read a '" & C & "', expected a hex character (0-F).";
end if;
good := false;
end case;
end;
procedure hexread(L:inout line; value:out bit_vector) is
variable OK: boolean;
variable C: character;
constant NE: integer := value'length/4; --'
variable BV: bit_vector(0 to value'length-1); --'
variable S: string(1 to NE-1);
begin
if value'length mod 4 /= 0 then --'
assert false report
"hexread Error: Trying to read vector " &
"with an odd (non multiple of 4) length";
return;
end if;
loop -- skip white space
read(L,C);
exit when ((C /= ' ') and (C /= CR) and (C /= HT));
end loop;
char2hex(C, BV(0 to 3), OK, false);
if not OK then
return;
end if;
read(L, S, OK);
-- if not OK then
-- assert false report "hexread Error: Failed to read the STRING";
-- return;
-- end if;
for I in 1 to NE-1 loop
char2hex(S(I), BV(4*I to 4*I+3), OK, false);
if not OK then
return;
end if;
end loop;
value := BV;
end hexread;
procedure hexread(L:inout line; value:out std_ulogic_vector) is
variable tmp: bit_vector(value'length-1 downto 0); --'
begin
hexread(L, tmp);
value := TO_X01(tmp);
end hexread;
procedure hexread(L:inout line; value:out std_logic_vector) is
variable tmp: std_ulogic_vector(value'length-1 downto 0); --'
begin
hexread(L, tmp);
value := std_logic_vector(tmp);
end hexread;
function ishex(c:character) return boolean is
variable tmp : bit_vector(3 downto 0);
variable OK : boolean;
begin
char2hex(C, tmp, OK, false);
return OK;
end ishex;
procedure gptimer_subtest(subtest : integer) is
begin
case subtest is
when 0 | 1 | 2 | 3 | 4 | 5 | 6 => print(" timer " & tost(subtest+1));
when 8 => print(" chain mode");
when others => print(" sub-system test " & tost(subtest));
end case;
end;
procedure leon3_subtest(subtest : integer) is
begin
case (subtest mod 16) is
when 3 => print(" CPU#" & (tost(subtest/16)) & " register file");
when 4 => print(" CPU#" & (tost(subtest/16)) & " multiplier");
when 5 => print(" CPU#" & (tost(subtest/16)) & " radix-2 divider");
when 6 => print(" CPU#" & (tost(subtest/16)) & " cache system");
when 7 => print(" CPU#" & (tost(subtest/16)) & " multi-processing");
when 8 => print(" CPU#" & (tost(subtest/16)) & " floating-point unit");
when 9 => print(" CPU#" & (tost(subtest/16)) & " itag cache ram");
when 10 => print(" CPU#" & (tost(subtest/16)) & " dtag cache ram");
when 11 => print(" CPU#" & (tost(subtest/16)) & " idata cache ram");
when 12 => print(" CPU#" & (tost(subtest/16)) & " ddata cache ram");
when 13 => print(" CPU#" & (tost(subtest/16)) & " GRFPU test");
when 14 => print(" CPU#" & (tost(subtest/16)) & " memory management unit");
when others => print(" sub-system test " & tost(subtest));
end case;
end;
procedure mctrl_subtest(subtest : integer) is
begin
case subtest is
when 3 => print(" sub-word write");
when 4 => print(" EDAC");
when 5 => print(" write protection");
when others => print(" sub-system test " & tost(subtest));
end case;
end;
procedure dsu3_subtest(subtest : integer) is
begin
case subtest is
when 1 => print(" AHB trace buffer memory (0x55555555)");
when 2 => print(" AHB trace buffer memory (0xAAAAAAAA)");
when 3 => print(" AHB trace buffer addressing");
when others => print(" sub-system test " & tost(subtest));
end case;
end;
procedure spw_subtest(subtest : integer) is
begin
case subtest is
when 1 => print(" Nominal operation, leon3 snooping enabled");
when 2 => print(" Nominal operation, leon3 snooping disabled");
when 3 => print(" RMAP packet reception");
when 4 => print(" Time functionality");
when others => print(" sub-system test " & tost(subtest));
end case;
end;
procedure spictrl_subtest(subtest : integer) is
begin
case subtest is
when 1 => print(" APB interface reset values");
when 2 => print(" Loopback mode");
when others => print(" sub-system test " & tost(subtest));
end case;
end;
procedure i2cmst_subtest(subtest : integer) is
begin
case subtest is
when 1 => print(" APB interface reset values");
when 2 => print(" Data transfer");
when others => print(" sub-system test " & tost(subtest));
end case;
end;
procedure uhc_subtest(subtest : integer) is
begin
case subtest is
when 1 => print(" I/O register reset values");
when 2 => print(" Host Controller Reset");
when 3 => print(" Isochronous IN and OUT");
when 4 => print(" Control OUT, Bulk IN");
when others => print(" sub-system test " & tost(subtest));
end case;
end;
procedure ehc_subtest(subtest : integer) is
begin
case subtest is
when 1 => print(" Register reset values");
when 2 => print(" Host Controller Reset");
when 3 => print(" Periodic schedule");
when 4 => print(" Asynchronous schedule");
when others => print(" sub-system test " & tost(subtest));
end case;
end;
end;
-- pragma translate_on
| mit | 26c363891c2f8f4be6c2c2d445acb20a | 0.559604 | 3.510305 | false | true | false | false |
impedimentToProgress/UCI-BlueChip | AttackFiles/Attacks/privEsc/designs/myDemo/ahbrom.vhd | 2 | 7,078 |
----------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2004 GAISLER RESEARCH
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- See the file COPYING for the full details of the license.
--
-----------------------------------------------------------------------------
-- Entity: ahbrom
-- File: ahbrom.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: AHB rom. 0/1-waitstate read
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
entity ahbrom is
generic (
hindex : integer := 0;
haddr : integer := 0;
hmask : integer := 16#fff#;
pipe : integer := 0;
tech : integer := 0;
kbytes : integer := 1);
port (
rst : in std_ulogic;
clk : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type
);
end;
architecture rtl of ahbrom is
constant abits : integer := 9;
constant bytes : integer := 368;
constant hconfig : ahb_config_type := (
0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_AHBROM, 0, 0, 0),
4 => ahb_membar(haddr, '1', '1', hmask), others => zero32);
signal romdata : std_logic_vector(31 downto 0);
signal addr : std_logic_vector(abits-1 downto 2);
signal hsel, hready : std_ulogic;
begin
ahbso.hresp <= "00";
ahbso.hsplit <= (others => '0');
ahbso.hirq <= (others => '0');
ahbso.hcache <= '1';
ahbso.hconfig <= hconfig;
ahbso.hindex <= hindex;
reg : process (clk)
begin
if rising_edge(clk) then
addr <= ahbsi.haddr(abits-1 downto 2);
end if;
end process;
p0 : if pipe = 0 generate
ahbso.hrdata <= romdata;
ahbso.hready <= '1';
end generate;
p1 : if pipe = 1 generate
reg2 : process (clk)
begin
if rising_edge(clk) then
hsel <= ahbsi.hsel(hindex) and ahbsi.htrans(1);
hready <= ahbsi.hready;
ahbso.hready <= (not rst) or (hsel and hready) or
(ahbsi.hsel(hindex) and not ahbsi.htrans(1) and ahbsi.hready);
ahbso.hrdata <= romdata;
end if;
end process;
end generate;
comb : process (addr)
begin
case conv_integer(addr) is
when 16#00000# => romdata <= X"81D82000";
when 16#00001# => romdata <= X"03000004";
when 16#00002# => romdata <= X"821060E0";
when 16#00003# => romdata <= X"81884000";
when 16#00004# => romdata <= X"81900000";
when 16#00005# => romdata <= X"81980000";
when 16#00006# => romdata <= X"81800000";
when 16#00007# => romdata <= X"01000000";
when 16#00008# => romdata <= X"03002040";
when 16#00009# => romdata <= X"8210600F";
when 16#0000A# => romdata <= X"C2A00040";
when 16#0000B# => romdata <= X"87444000";
when 16#0000C# => romdata <= X"8608E01F";
when 16#0000D# => romdata <= X"88100000";
when 16#0000E# => romdata <= X"8A100000";
when 16#0000F# => romdata <= X"8C100000";
when 16#00010# => romdata <= X"8E100000";
when 16#00011# => romdata <= X"A0100000";
when 16#00012# => romdata <= X"A2100000";
when 16#00013# => romdata <= X"A4100000";
when 16#00014# => romdata <= X"A6100000";
when 16#00015# => romdata <= X"A8100000";
when 16#00016# => romdata <= X"AA100000";
when 16#00017# => romdata <= X"AC100000";
when 16#00018# => romdata <= X"AE100000";
when 16#00019# => romdata <= X"90100000";
when 16#0001A# => romdata <= X"92100000";
when 16#0001B# => romdata <= X"94100000";
when 16#0001C# => romdata <= X"96100000";
when 16#0001D# => romdata <= X"98100000";
when 16#0001E# => romdata <= X"9A100000";
when 16#0001F# => romdata <= X"9C100000";
when 16#00020# => romdata <= X"9E100000";
when 16#00021# => romdata <= X"86A0E001";
when 16#00022# => romdata <= X"16BFFFEF";
when 16#00023# => romdata <= X"81E00000";
when 16#00024# => romdata <= X"82102002";
when 16#00025# => romdata <= X"81904000";
when 16#00026# => romdata <= X"03000004";
when 16#00027# => romdata <= X"821060E0";
when 16#00028# => romdata <= X"81884000";
when 16#00029# => romdata <= X"01000000";
when 16#0002A# => romdata <= X"01000000";
when 16#0002B# => romdata <= X"01000000";
when 16#0002C# => romdata <= X"83480000";
when 16#0002D# => romdata <= X"8330600C";
when 16#0002E# => romdata <= X"80886001";
when 16#0002F# => romdata <= X"02800019";
when 16#00030# => romdata <= X"01000000";
when 16#00031# => romdata <= X"07000000";
when 16#00032# => romdata <= X"8610E118";
when 16#00033# => romdata <= X"C108C000";
when 16#00034# => romdata <= X"C118C000";
when 16#00035# => romdata <= X"C518C000";
when 16#00036# => romdata <= X"C918C000";
when 16#00037# => romdata <= X"CD18E008";
when 16#00038# => romdata <= X"D118C000";
when 16#00039# => romdata <= X"D518C000";
when 16#0003A# => romdata <= X"D918C000";
when 16#0003B# => romdata <= X"DD18C000";
when 16#0003C# => romdata <= X"E118C000";
when 16#0003D# => romdata <= X"E518C000";
when 16#0003E# => romdata <= X"E918C000";
when 16#0003F# => romdata <= X"ED18C000";
when 16#00040# => romdata <= X"F118C000";
when 16#00041# => romdata <= X"F518C000";
when 16#00042# => romdata <= X"F918C000";
when 16#00043# => romdata <= X"10800005";
when 16#00044# => romdata <= X"FD18C000";
when 16#00045# => romdata <= X"01000000";
when 16#00046# => romdata <= X"00000000";
when 16#00047# => romdata <= X"00000000";
when 16#00048# => romdata <= X"05000008";
when 16#00049# => romdata <= X"82100000";
when 16#0004A# => romdata <= X"3D1003FF";
when 16#0004B# => romdata <= X"BC17A3E0";
when 16#0004C# => romdata <= X"BC278001";
when 16#0004D# => romdata <= X"9C27A060";
when 16#0004E# => romdata <= X"03100000";
when 16#0004F# => romdata <= X"81C04000";
when 16#00050# => romdata <= X"01000000";
when 16#00051# => romdata <= X"01000000";
when 16#00052# => romdata <= X"01000000";
when 16#00053# => romdata <= X"01000000";
when 16#00054# => romdata <= X"01000000";
when 16#00055# => romdata <= X"01000000";
when 16#00056# => romdata <= X"01000000";
when 16#00057# => romdata <= X"01000000";
when 16#00058# => romdata <= X"00000000";
when 16#00059# => romdata <= X"00000000";
when 16#0005A# => romdata <= X"00000000";
when 16#0005B# => romdata <= X"00000000";
when 16#0005C# => romdata <= X"00000000";
when others => romdata <= (others => '-');
end case;
end process;
-- pragma translate_off
bootmsg : report_version
generic map ("ahbrom" & tost(hindex) &
": 32-bit AHB ROM Module, " & tost(bytes/4) & " words, " & tost(abits-2) & " address bits" );
-- pragma translate_on
end;
| mit | 2c7d6f6082c34be6a40fbd6affdd187c | 0.584063 | 3.324566 | false | false | false | false |
impedimentToProgress/UCI-BlueChip | AttackFiles/Attacks/privEsc/lib/gaisler/pci/pcitb.vhd | 2 | 9,156 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: pci
-- File: pci.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: Package with component and type declarations for PCI testbench
-- modules
------------------------------------------------------------------------------
-- pragma translate_off
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.stdlib.all;
library gaisler;
use gaisler.ambatest.all;
package pcitb is
type bar_type is array(0 to 5) of std_logic_vector(31 downto 0);
constant bar_init : bar_type := ((others => '0'),(others => '0'),(others => '0'),(others => '0'),(others => '0'),(others => '0'));
type config_header_type is record
devid : std_logic_vector(15 downto 0);
vendid : std_logic_vector(15 downto 0);
status : std_logic_vector(15 downto 0);
command : std_logic_vector(15 downto 0);
class_code : std_logic_vector(23 downto 0);
revid : std_logic_vector(7 downto 0);
bist : std_logic_vector(7 downto 0);
header_type : std_logic_vector(7 downto 0);
lat_timer : std_logic_vector(7 downto 0);
cache_lsize : std_logic_vector(7 downto 0);
bar : bar_type;
cis_p : std_logic_vector(31 downto 0);
subid : std_logic_vector(15 downto 0);
subvendid : std_logic_vector(15 downto 0);
exp_rom_ba : std_logic_vector(31 downto 0);
max_lat : std_logic_vector(7 downto 0);
min_gnt : std_logic_vector(7 downto 0);
int_pin : std_logic_vector(7 downto 0);
int_line : std_logic_vector(7 downto 0);
end record;
constant config_init : config_header_type := (
devid => conv_std_logic_vector(16#0BAD#,16),
vendid => conv_std_logic_vector(16#AFFE#,16),
status => (others => '0'),
command => (others => '0'),
class_code => conv_std_logic_vector(16#050000#,24),
revid => conv_std_logic_vector(16#01#,8),
bist => (others => '0'),
header_type => (others => '0'),
lat_timer => (others => '0'),
cache_lsize => (others => '0'),
bar => bar_init,
cis_p => (others => '0'),
subid => (others => '0'),
subvendid => (others => '0'),
exp_rom_ba => (others => '0'),
max_lat => (others => '0'),
min_gnt => (others => '0'),
int_pin => (others => '0'),
int_line => (others => '0'));
-- These types defines the TB PCI bus
type pci_ad_type is record
ad : std_logic_vector(31 downto 0);
cbe : std_logic_vector(3 downto 0);
par : std_logic;
end record;
constant ad_const : pci_ad_type := (
ad => (others => 'Z'),
cbe => (others => 'Z'),
par => 'Z');
type pci_ifc_type is record
frame : std_logic;
irdy : std_logic;
trdy : std_logic;
stop : std_logic;
devsel : std_logic;
idsel : std_logic_vector(20 downto 0);
lock : std_logic;
end record;
constant ifc_const : pci_ifc_type := (
frame => 'H',
irdy => 'H',
trdy => 'H',
stop => 'H',
lock => 'H',
idsel => (others => 'L'),
devsel => 'H');
type pci_err_type is record
perr : std_logic;
serr : std_logic;
end record;
constant err_const : pci_err_type := (
perr => 'H',
serr => 'H');
type pci_arb_type is record
req : std_logic_vector(20 downto 0);
gnt : std_logic_vector(20 downto 0);
end record;
constant arb_const : pci_arb_type := (
req => (others => 'H'),
gnt => (others => 'H'));
type pci_syst_type is record
clk : std_logic;
rst : std_logic;
end record;
constant syst_const : pci_syst_type := (
clk => 'H',
rst => 'H');
type pci_ext64_type is record
ad : std_logic_vector(63 downto 32);
cbe : std_logic_vector(7 downto 4);
par64 : std_logic;
req64 : std_logic;
ack64 : std_logic;
end record;
constant ext64_const : pci_ext64_type := (
ad => (others => 'Z'),
cbe => (others => 'Z'),
par64 => 'Z',
req64 => 'Z',
ack64 => 'Z');
type pci_int_type is record
inta : std_logic;
intb : std_logic;
intc : std_logic;
intd : std_logic;
end record;
constant int_const : pci_int_type := (
inta => 'H',
intb => 'H',
intc => 'H',
intd => 'H');
type pci_cache_type is record
sbo : std_logic;
sdone : std_logic;
end record;
constant cache_const : pci_cache_type := (
sbo => 'U',
sdone => 'U');
type pci_type is record
ad : pci_ad_type;
ifc : pci_ifc_type;
err : pci_err_type;
arb : pci_arb_type;
syst : pci_syst_type;
ext64 : pci_ext64_type;
int : pci_int_type;
cache : pci_cache_type;
end record;
constant pci_idle : pci_type := ( ad_const, ifc_const, err_const, arb_const,
syst_const, ext64_const, int_const, cache_const);
-- PCI emulators for TB
component pcitb_clkgen
generic (
mhz66 : boolean := false; -- PCI clock frequency. false = 33MHz, true = 66MHz
rstclocks : integer := 20); -- How long (in clks) the rst signal is asserted
port (
rsttrig : in std_logic; -- Asynchronous reset trig, active high
systclk : out pci_syst_type); -- clock and reset outputs
end component;
component pcitb_master -- A PCI master that is accessed through a Testbench vector
generic (
slot : integer := 0; -- Slot number for this unit
tval : time := 7 ns; -- Output delay for signals that are driven by this unit
dbglevel : integer := 1); -- Debug level. Higher value means more debug information
port (
pciin : in pci_type;
pciout : out pci_type;
tbi : in tb_in_type;
tbo : out tb_out_type
);
end component;
component pcitb_master_script
generic (
slot : integer := 0; -- Slot number for this unit
tval : time := 7 ns; -- Output delay for signals that are driven by this unit
dbglevel : integer := 2; -- Debug level. Higher value means more debug information
maxburst : integer := 1024;
filename : string := "pci.cmd");
port (
pciin : in pci_type;
pciout : out pci_type
);
end component;
component pcitb_target -- Represents a simple memory on the PCI bus
generic (
slot : integer := 0; -- Slot number for this unit
abits : integer := 10; -- Memory size. Size is 2^abits 32-bit words
bars : integer := 1; -- Number of bars for this target. Min 1, Max 6
resptime : integer := 2; -- The initial response time in clks for this target
latency : integer := 0; -- The latency in clks for every dataphase for a burst access
rbuf : integer := 8; -- The maximum no of words this target can transfer in a continuous burst
stopwd : boolean := true; -- Target disconnect type. true = disconnect WITH data, false = disconnect WITHOUT data
tval : time := 7 ns; -- Output delay for signals that are driven by this unit
conf : config_header_type := config_init; -- The reset condition of the configuration space of this target
dbglevel : integer := 1); -- Debug level. Higher value means more debug information
port (
pciin : in pci_type;
pciout : out pci_type;
tbi : in tb_in_type;
tbo : out tb_out_type
);
end component;
component pcitb_stimgen
generic (
slots : integer := 5; -- The number of slots in the test system
dbglevel : integer := 1); -- Debug level. Higher value means more debug information
port (
rsttrig : out std_logic;
tbi : out tbi_array_type;
tbo : in tbo_array_type
);
end component;
component pcitb_arb
generic (
slots : integer := 5; -- The number of slots in the test system
tval : time := 7 ns); -- Output delay for signals that are driven by this unit
port (
systclk : in pci_syst_type;
ifcin : in pci_ifc_type;
arbin : in pci_arb_type;
arbout : out pci_arb_type);
end component;
component pcitb_monitor is
generic (dbglevel : integer := 1); -- Debug level. Higher value means more debug information
port (pciin : in pci_type);
end component;
end;
-- pragma translate_on
| mit | 48438d78fbbcac6c4f60d92c6029262d | 0.583333 | 3.572376 | false | false | false | false |
impedimentToProgress/UCI-BlueChip | AttackFiles/Attacks/privEsc/lib/tech/unisim/simprims/xilinx_mem.vhd | 2 | 100,567 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
----------------------------------------------------------------------------
-- Simple simulation models for Xilinx block rams
-- Author: Jiri Gaisler
----------------------------------------------------------------------------
-- pragma translate_off
-- simulation models for block-rams
library ieee;
use ieee.std_logic_1164.all;
library unisim;
use unisim.simple_simprim.all;
entity RAMB4_S16 is
port (
do : out std_logic_vector (15 downto 0);
addr : in std_logic_vector (7 downto 0);
clk : in std_ulogic;
di : in std_logic_vector (15 downto 0);
en, rst, we : in std_ulogic);
end;
architecture behav of RAMB4_S16 is
begin x : ramb4_generic generic map (8,16)
port map (di, en, we, rst, clk, addr, do);
end;
library ieee;
use ieee.std_logic_1164.all;
library unisim;
use unisim.simple_simprim.all;
entity RAMB4_S8 is
port (do : out std_logic_vector (7 downto 0);
addr : in std_logic_vector (8 downto 0);
clk : in std_ulogic;
di : in std_logic_vector (7 downto 0);
en, rst, we : in std_ulogic);
end;
architecture behav of RAMB4_S8 is
begin x : ramb4_generic generic map (9,8)
port map (di, en, we, rst, clk, addr, do);
end;
library ieee;
use ieee.std_logic_1164.all;
library unisim;
use unisim.simple_simprim.all;
entity RAMB4_S4 is
port (do : out std_logic_vector (3 downto 0);
addr : in std_logic_vector (9 downto 0);
clk : in std_ulogic;
di : in std_logic_vector (3 downto 0);
en, rst, we : in std_ulogic);
end;
architecture behav of RAMB4_S4 is
begin x : ramb4_generic generic map (10,4)
port map (di, en, we, rst, clk, addr, do);
end;
library ieee;
use ieee.std_logic_1164.all;
library unisim;
use unisim.simple_simprim.all;
entity RAMB4_S2 is
port (do : out std_logic_vector (1 downto 0);
addr : in std_logic_vector (10 downto 0);
clk : in std_ulogic;
di : in std_logic_vector (1 downto 0);
en, rst, we : in std_ulogic);
end;
architecture behav of RAMB4_S2 is
begin x : ramb4_generic generic map (11,2)
port map (di, en, we, rst, clk, addr, do);
end;
library ieee;
use ieee.std_logic_1164.all;
library unisim;
use unisim.simple_simprim.all;
entity RAMB4_S1 is
port (do : out std_logic_vector (0 downto 0);
addr : in std_logic_vector (11 downto 0);
clk : in std_ulogic;
di : in std_logic_vector (0 downto 0);
en, rst, we : in std_ulogic);
end;
architecture behav of RAMB4_S1 is
begin x : ramb4_generic generic map (12,1)
port map (di, en, we, rst, clk, addr, do);
end;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity RAMB4_SX_SX is
generic (abits : integer := 10; dbits : integer := 8 );
port (DIA : in std_logic_vector (dbits-1 downto 0);
DIB : in std_logic_vector (dbits-1 downto 0);
ENA : in std_ulogic;
ENB : in std_ulogic;
WEA : in std_ulogic;
WEB : in std_ulogic;
RSTA : in std_ulogic;
RSTB : in std_ulogic;
CLKA : in std_ulogic;
CLKB : in std_ulogic;
ADDRA : in std_logic_vector (abits-1 downto 0);
ADDRB : in std_logic_vector (abits-1 downto 0);
DOA : out std_logic_vector (dbits-1 downto 0);
DOB : out std_logic_vector (dbits-1 downto 0)
);
end;
architecture behav of RAMB4_SX_SX is
begin
rp : process(clka, clkb)
subtype dword is std_logic_vector(dbits-1 downto 0);
type dregtype is array (0 to 2**abits-1) of DWord;
variable rfd : dregtype := (others => (others => '0'));
begin
if rising_edge(clka) and not is_x (addra) then
if ena = '1' then
doa <= rfd(to_integer(unsigned(addra)));
if wea = '1' then rfd(to_integer(unsigned(addra))) := dia; end if;
end if;
end if;
if rising_edge(clkb) and not is_x (addrb) then
if enb = '1' then
dob <= rfd(to_integer(unsigned(addrb)));
if web = '1' then rfd(to_integer(unsigned(addrb))) := dib; end if;
end if;
end if;
end process;
end;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library unisim;
use unisim.simple_simprim.all;
entity RAMB4_S1_S1 is
port (
doa : out std_logic_vector (0 downto 0);
dob : out std_logic_vector (0 downto 0);
addra : in std_logic_vector (11 downto 0);
addrb : in std_logic_vector (11 downto 0);
clka : in std_ulogic;
clkb : in std_ulogic;
dia : in std_logic_vector (0 downto 0);
dib : in std_logic_vector (0 downto 0);
ena : in std_ulogic;
enb : in std_ulogic;
rsta : in std_ulogic;
rstb : in std_ulogic;
wea : in std_ulogic;
web : in std_ulogic
);
end;
architecture behav of RAMB4_S1_S1 is
begin
u0 : RAMB4_Sx_Sx generic map (12, 1)
port map (DIA, DIB, ENA, ENB, WEA, WEB, RSTA, RSTB, CLKA, CLKB, ADDRA,
ADDRB, DOA, DOB);
end;
library ieee;
use ieee.std_logic_1164.all;
library unisim;
use unisim.simple_simprim.all;
entity RAMB4_S2_S2 is
port (
doa : out std_logic_vector (1 downto 0);
dob : out std_logic_vector (1 downto 0);
addra : in std_logic_vector (10 downto 0);
addrb : in std_logic_vector (10 downto 0);
clka : in std_ulogic;
clkb : in std_ulogic;
dia : in std_logic_vector (1 downto 0);
dib : in std_logic_vector (1 downto 0);
ena : in std_ulogic;
enb : in std_ulogic;
rsta : in std_ulogic;
rstb : in std_ulogic;
wea : in std_ulogic;
web : in std_ulogic
);
end;
architecture behav of RAMB4_S2_S2 is
begin
u0 : RAMB4_Sx_Sx generic map (11, 2)
port map (DIA, DIB, ENA, ENB, WEA, WEB, RSTA, RSTB, CLKA, CLKB, ADDRA,
ADDRB, DOA, DOB);
end;
library ieee;
use ieee.std_logic_1164.all;
library unisim;
use unisim.simple_simprim.all;
entity RAMB4_S8_S8 is
port (
doa : out std_logic_vector (7 downto 0);
dob : out std_logic_vector (7 downto 0);
addra : in std_logic_vector (8 downto 0);
addrb : in std_logic_vector (8 downto 0);
clka : in std_ulogic;
clkb : in std_ulogic;
dia : in std_logic_vector (7 downto 0);
dib : in std_logic_vector (7 downto 0);
ena : in std_ulogic;
enb : in std_ulogic;
rsta : in std_ulogic;
rstb : in std_ulogic;
wea : in std_ulogic;
web : in std_ulogic
);
end;
architecture behav of RAMB4_S8_S8 is
begin
u0 : RAMB4_Sx_Sx generic map (9, 8)
port map (DIA, DIB, ENA, ENB, WEA, WEB, RSTA, RSTB, CLKA, CLKB, ADDRA,
ADDRB, DOA, DOB);
end;
library ieee;
use ieee.std_logic_1164.all;
library unisim;
use unisim.simple_simprim.all;
entity RAMB4_S4_S4 is
port (
doa : out std_logic_vector (3 downto 0);
dob : out std_logic_vector (3 downto 0);
addra : in std_logic_vector (9 downto 0);
addrb : in std_logic_vector (9 downto 0);
clka : in std_ulogic;
clkb : in std_ulogic;
dia : in std_logic_vector (3 downto 0);
dib : in std_logic_vector (3 downto 0);
ena : in std_ulogic;
enb : in std_ulogic;
rsta : in std_ulogic;
rstb : in std_ulogic;
wea : in std_ulogic;
web : in std_ulogic
);
end;
architecture behav of RAMB4_S4_S4 is
begin
u0 : RAMB4_Sx_Sx generic map (10, 4)
port map (DIA, DIB, ENA, ENB, WEA, WEB, RSTA, RSTB, CLKA, CLKB, ADDRA,
ADDRB, DOA, DOB);
end;
library ieee;
use ieee.std_logic_1164.all;
library unisim;
use unisim.simple_simprim.all;
entity RAMB4_S16_S16 is
port (
doa : out std_logic_vector (15 downto 0);
dob : out std_logic_vector (15 downto 0);
addra : in std_logic_vector (7 downto 0);
addrb : in std_logic_vector (7 downto 0);
clka : in std_ulogic;
clkb : in std_ulogic;
dia : in std_logic_vector (15 downto 0);
dib : in std_logic_vector (15 downto 0);
ena : in std_ulogic;
enb : in std_ulogic;
rsta : in std_ulogic;
rstb : in std_ulogic;
wea : in std_ulogic;
web : in std_ulogic
);
end;
architecture behav of RAMB4_S16_S16 is
begin
u0 : RAMB4_Sx_Sx generic map (8, 16)
port map (DIA, DIB, ENA, ENB, WEA, WEB, RSTA, RSTB, CLKA, CLKB, ADDRA,
ADDRB, DOA, DOB);
end;
library ieee;
use ieee.std_logic_1164.all;
library unisim;
use unisim.simple_simprim.all;
entity RAMB16_S1 is
-- pragma translate_off
generic
(
INIT : bit_vector := X"0";
SRVAL : bit_vector := X"0";
WRITE_MODE : string := "WRITE_FIRST";
INIT_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_08 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_09 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_10 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_11 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_12 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_13 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_14 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_15 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_16 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_17 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_18 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_19 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_20 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_21 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_22 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_23 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_24 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_25 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_26 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_27 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_28 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_29 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_30 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_31 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_32 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_33 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_34 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_35 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_36 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_37 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_38 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_39 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"
);
-- pragma translate_on
port (
DO : out std_logic_vector (0 downto 0);
ADDR : in std_logic_vector (13 downto 0);
CLK : in std_ulogic;
DI : in std_logic_vector (0 downto 0);
EN : in std_ulogic;
SSR : in std_ulogic;
WE : in std_ulogic
);
end;
architecture behav of RAMB16_S1 is
begin x : ramb16_sx generic map (14,1)
port map (do, addr, di, en, clk, we, ssr);
end;
library ieee;
use ieee.std_logic_1164.all;
library unisim;
use unisim.simple_simprim.all;
entity RAMB16_S2 is
-- pragma translate_off
generic
(
INIT : bit_vector := X"0";
SRVAL : bit_vector := X"0";
WRITE_MODE : string := "WRITE_FIRST";
INIT_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_08 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_09 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_10 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_11 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_12 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_13 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_14 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_15 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_16 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_17 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_18 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_19 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_20 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_21 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_22 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_23 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_24 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_25 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_26 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_27 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_28 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_29 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_30 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_31 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_32 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_33 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_34 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_35 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_36 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_37 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_38 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_39 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"
);
-- pragma translate_on
port (
DO : out std_logic_vector (1 downto 0);
ADDR : in std_logic_vector (12 downto 0);
CLK : in std_ulogic;
DI : in std_logic_vector (1 downto 0);
EN : in std_ulogic;
SSR : in std_ulogic;
WE : in std_ulogic
);
end;
architecture behav of RAMB16_S2 is
begin x : ramb16_sx generic map (13,2)
port map (do, addr, di, en, clk, we, ssr);
end;
library ieee;
use ieee.std_logic_1164.all;
library unisim;
use unisim.simple_simprim.all;
entity RAMB16_S4 is
-- pragma translate_off
generic
(
INIT : bit_vector := X"0";
SRVAL : bit_vector := X"0";
WRITE_MODE : string := "WRITE_FIRST";
INIT_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_08 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_09 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_10 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_11 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_12 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_13 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_14 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_15 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_16 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_17 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_18 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_19 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_20 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_21 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_22 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_23 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_24 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_25 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_26 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_27 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_28 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_29 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_30 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_31 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_32 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_33 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_34 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_35 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_36 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_37 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_38 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_39 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"
);
-- pragma translate_on
port (
DO : out std_logic_vector (3 downto 0);
ADDR : in std_logic_vector (11 downto 0);
CLK : in std_ulogic;
DI : in std_logic_vector (3 downto 0);
EN : in std_ulogic;
SSR : in std_ulogic;
WE : in std_ulogic
);
end;
architecture behav of RAMB16_S4 is
begin x : ramb16_sx generic map (12,4)
port map (do, addr, di, en, clk, we, ssr);
end;
library ieee;
use ieee.std_logic_1164.all;
library unisim;
use unisim.simple_simprim.all;
entity RAMB16_S9 is
-- pragma translate_off
generic
(
INIT : bit_vector := X"000";
SRVAL : bit_vector := X"000";
WRITE_MODE : string := "WRITE_FIRST";
INIT_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_08 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_09 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_10 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_11 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_12 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_13 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_14 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_15 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_16 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_17 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_18 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_19 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_20 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_21 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_22 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_23 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_24 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_25 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_26 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_27 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_28 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_29 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_30 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_31 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_32 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_33 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_34 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_35 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_36 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_37 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_38 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_39 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"
);
-- pragma translate_on
port (
DO : out std_logic_vector (7 downto 0);
DOP : out std_logic_vector (0 downto 0);
ADDR : in std_logic_vector (10 downto 0);
CLK : in std_ulogic;
DI : in std_logic_vector (7 downto 0);
DIP : in std_logic_vector (0 downto 0);
EN : in std_ulogic;
SSR : in std_ulogic;
WE : in std_ulogic
);
end;
architecture behav of RAMB16_S9 is
signal dix, dox : std_logic_vector (8 downto 0);
begin x : ramb16_sx generic map (11,9)
port map (dox, addr, dix, en, clk, we, ssr);
dix <= dip & di; dop <= dox(8 downto 8); do <= dox(7 downto 0);
end;
library ieee;
use ieee.std_logic_1164.all;
library unisim;
use unisim.simple_simprim.all;
entity RAMB16_S18 is
-- pragma translate_off
generic
(
INIT : bit_vector := X"00000";
SRVAL : bit_vector := X"00000";
write_mode : string := "WRITE_FIRST";
INITP_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_08 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_09 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_10 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_11 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_12 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_13 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_14 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_15 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_16 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_17 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_18 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_19 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_20 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_21 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_22 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_23 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_24 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_25 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_26 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_27 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_28 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_29 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_30 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_31 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_32 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_33 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_34 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_35 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_36 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_37 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_38 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_39 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"
);
-- pragma translate_on
port (
DO : out std_logic_vector (15 downto 0);
DOP : out std_logic_vector (1 downto 0);
ADDR : in std_logic_vector (9 downto 0);
CLK : in std_ulogic;
DI : in std_logic_vector (15 downto 0);
DIP : in std_logic_vector (1 downto 0);
EN : in std_ulogic;
SSR : in std_ulogic;
WE : in std_ulogic
);
end;
architecture behav of RAMB16_S18 is
signal dix, dox : std_logic_vector (17 downto 0);
begin x : ramb16_sx generic map (10,18)
port map (dox, addr, dix, en, clk, we, ssr);
dix <= dip & di; dop <= dox(17 downto 16); do <= dox(15 downto 0);
end;
library ieee;
use ieee.std_logic_1164.all;
library unisim;
use unisim.simple_simprim.all;
entity RAMB16_S36 is
-- pragma translate_off
generic
(
INIT : bit_vector := X"000000000";
SRVAL : bit_vector := X"000000000";
WRITE_MODE : string := "WRITE_FIRST";
INITP_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_08 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_09 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_10 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_11 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_12 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_13 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_14 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_15 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_16 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_17 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_18 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_19 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_20 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_21 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_22 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_23 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_24 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_25 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_26 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_27 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_28 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_29 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_30 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_31 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_32 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_33 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_34 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_35 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_36 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_37 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_38 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_39 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"
);
-- pragma translate_on
port (
DO : out std_logic_vector (31 downto 0);
DOP : out std_logic_vector (3 downto 0);
ADDR : in std_logic_vector (8 downto 0);
CLK : in std_ulogic;
DI : in std_logic_vector (31 downto 0);
DIP : in std_logic_vector (3 downto 0);
EN : in std_ulogic;
SSR : in std_ulogic;
WE : in std_ulogic
);
end;
architecture behav of RAMB16_S36 is
signal dix, dox : std_logic_vector (35 downto 0);
begin x : ramb16_sx generic map (9, 36)
port map (dox, addr, dix, en, clk, we, ssr);
dix <= dip & di; dop <= dox(35 downto 32); do <= dox(31 downto 0);
end;
library ieee;
use ieee.std_logic_1164.all;
library unisim;
use unisim.simple_simprim.all;
entity RAMB16_S1_S1 is
-- pragma translate_off
generic
(
INIT_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_08 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_09 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_10 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_11 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_12 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_13 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_14 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_15 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_16 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_17 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_18 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_19 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_20 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_21 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_22 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_23 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_24 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_25 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_26 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_27 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_28 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_29 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_30 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_31 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_32 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_33 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_34 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_35 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_36 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_37 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_38 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_39 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_A : bit_vector := X"0";
INIT_B : bit_vector := X"0";
SIM_COLLISION_CHECK : string := "ALL";
SRVAL_A : bit_vector := X"0";
SRVAL_B : bit_vector := X"0";
WRITE_MODE_A : string := "WRITE_FIRST";
WRITE_MODE_B : string := "WRITE_FIRST"
);
-- pragma translate_on
port (
DOA : out std_logic_vector (0 downto 0);
DOB : out std_logic_vector (0 downto 0);
ADDRA : in std_logic_vector (13 downto 0);
ADDRB : in std_logic_vector (13 downto 0);
CLKA : in std_ulogic;
CLKB : in std_ulogic;
DIA : in std_logic_vector (0 downto 0);
DIB : in std_logic_vector (0 downto 0);
ENA : in std_ulogic;
ENB : in std_ulogic;
SSRA : in std_ulogic;
SSRB : in std_ulogic;
WEA : in std_ulogic;
WEB : in std_ulogic
);
end;
architecture behav of RAMB16_S1_S1 is
begin
x : ram16_sx_sx generic map (14, 1)
port map (doa, dob, addra, clka, dia, ena, wea, addrb, clkb, dib, enb, web);
end;
library ieee;
use ieee.std_logic_1164.all;
library unisim;
use unisim.simple_simprim.all;
entity RAMB16_S2_S2 is
-- pragma translate_off
generic
(
INIT_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_08 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_09 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_10 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_11 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_12 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_13 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_14 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_15 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_16 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_17 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_18 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_19 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_20 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_21 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_22 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_23 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_24 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_25 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_26 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_27 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_28 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_29 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_30 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_31 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_32 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_33 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_34 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_35 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_36 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_37 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_38 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_39 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_A : bit_vector := X"0";
INIT_B : bit_vector := X"0";
SIM_COLLISION_CHECK : string := "ALL";
SRVAL_A : bit_vector := X"0";
SRVAL_B : bit_vector := X"0";
WRITE_MODE_A : string := "WRITE_FIRST";
WRITE_MODE_B : string := "WRITE_FIRST"
);
-- pragma translate_on
port (
DOA : out std_logic_vector (1 downto 0);
DOB : out std_logic_vector (1 downto 0);
ADDRA : in std_logic_vector (12 downto 0);
ADDRB : in std_logic_vector (12 downto 0);
CLKA : in std_ulogic;
CLKB : in std_ulogic;
DIA : in std_logic_vector (1 downto 0);
DIB : in std_logic_vector (1 downto 0);
ENA : in std_ulogic;
ENB : in std_ulogic;
SSRA : in std_ulogic;
SSRB : in std_ulogic;
WEA : in std_ulogic;
WEB : in std_ulogic
);
end;
architecture behav of RAMB16_S2_S2 is
begin
x : ram16_sx_sx generic map (13, 2)
port map (doa, dob, addra, clka, dia, ena, wea, addrb, clkb, dib, enb, web);
end;
library ieee;
use ieee.std_logic_1164.all;
library unisim;
use unisim.simple_simprim.all;
entity RAMB16_S4_S4 is
-- pragma translate_off
generic
(
INIT_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_08 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_09 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_10 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_11 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_12 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_13 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_14 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_15 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_16 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_17 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_18 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_19 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_20 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_21 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_22 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_23 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_24 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_25 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_26 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_27 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_28 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_29 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_30 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_31 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_32 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_33 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_34 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_35 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_36 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_37 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_38 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_39 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_A : bit_vector := X"0";
INIT_B : bit_vector := X"0";
SIM_COLLISION_CHECK : string := "ALL";
SRVAL_A : bit_vector := X"0";
SRVAL_B : bit_vector := X"0";
WRITE_MODE_A : string := "WRITE_FIRST";
WRITE_MODE_B : string := "WRITE_FIRST"
);
-- pragma translate_on
port (
DOA : out std_logic_vector (3 downto 0);
DOB : out std_logic_vector (3 downto 0);
ADDRA : in std_logic_vector (11 downto 0);
ADDRB : in std_logic_vector (11 downto 0);
CLKA : in std_ulogic;
CLKB : in std_ulogic;
DIA : in std_logic_vector (3 downto 0);
DIB : in std_logic_vector (3 downto 0);
ENA : in std_ulogic;
ENB : in std_ulogic;
SSRA : in std_ulogic;
SSRB : in std_ulogic;
WEA : in std_ulogic;
WEB : in std_ulogic
);
end;
architecture behav of RAMB16_S4_S4 is
begin
x : ram16_sx_sx generic map (12, 4)
port map (doa, dob, addra, clka, dia, ena, wea, addrb, clkb, dib, enb, web);
end;
library ieee;
use ieee.std_logic_1164.all;
library unisim;
use unisim.simple_simprim.all;
entity RAMB16_S9_S9 is
-- pragma translate_off
generic
(
INIT_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_08 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_09 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_10 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_11 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_12 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_13 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_14 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_15 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_16 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_17 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_18 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_19 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_20 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_21 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_22 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_23 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_24 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_25 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_26 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_27 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_28 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_29 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_30 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_31 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_32 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_33 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_34 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_35 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_36 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_37 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_38 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_39 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_A : bit_vector := X"000";
INIT_B : bit_vector := X"000";
SIM_COLLISION_CHECK : string := "ALL";
SRVAL_A : bit_vector := X"000";
SRVAL_B : bit_vector := X"000";
WRITE_MODE_A : string := "WRITE_FIRST";
WRITE_MODE_B : string := "WRITE_FIRST"
);
-- pragma translate_on
port (
DOA : out std_logic_vector (7 downto 0);
DOB : out std_logic_vector (7 downto 0);
DOPA : out std_logic_vector (0 downto 0);
DOPB : out std_logic_vector (0 downto 0);
ADDRA : in std_logic_vector (10 downto 0);
ADDRB : in std_logic_vector (10 downto 0);
CLKA : in std_ulogic;
CLKB : in std_ulogic;
DIA : in std_logic_vector (7 downto 0);
DIB : in std_logic_vector (7 downto 0);
DIPA : in std_logic_vector (0 downto 0);
DIPB : in std_logic_vector (0 downto 0);
ENA : in std_ulogic;
ENB : in std_ulogic;
SSRA : in std_ulogic;
SSRB : in std_ulogic;
WEA : in std_ulogic;
WEB : in std_ulogic
);
end;
architecture behav of RAMB16_S9_S9 is
signal diax, doax, dibx, dobx : std_logic_vector (8 downto 0);
begin
x : ram16_sx_sx generic map (11, 9)
port map (doax, dobx, addra, clka, diax, ena, wea, addrb, clkb, dibx, enb, web);
diax <= dipa & dia; dopa <= doax(8 downto 8); doa <= doax(7 downto 0);
dibx <= dipb & dib; dopb <= dobx(8 downto 8); dob <= dobx(7 downto 0);
end;
library ieee;
use ieee.std_logic_1164.all;
library unisim;
use unisim.simple_simprim.all;
entity RAMB16_S18_S18 is
-- pragma translate_off
generic
(
INIT_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_08 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_09 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_10 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_11 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_12 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_13 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_14 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_15 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_16 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_17 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_18 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_19 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_20 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_21 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_22 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_23 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_24 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_25 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_26 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_27 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_28 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_29 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_30 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_31 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_32 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_33 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_34 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_35 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_36 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_37 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_38 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_39 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_A : bit_vector := X"00000";
INIT_B : bit_vector := X"00000";
SIM_COLLISION_CHECK : string := "ALL";
SRVAL_A : bit_vector := X"00000";
SRVAL_B : bit_vector := X"00000";
WRITE_MODE_A : string := "WRITE_FIRST";
WRITE_MODE_B : string := "WRITE_FIRST"
);
-- pragma translate_on
port (
DOA : out std_logic_vector (15 downto 0);
DOB : out std_logic_vector (15 downto 0);
DOPA : out std_logic_vector (1 downto 0);
DOPB : out std_logic_vector (1 downto 0);
ADDRA : in std_logic_vector (9 downto 0);
ADDRB : in std_logic_vector (9 downto 0);
CLKA : in std_ulogic;
CLKB : in std_ulogic;
DIA : in std_logic_vector (15 downto 0);
DIB : in std_logic_vector (15 downto 0);
DIPA : in std_logic_vector (1 downto 0);
DIPB : in std_logic_vector (1 downto 0);
ENA : in std_ulogic;
ENB : in std_ulogic;
SSRA : in std_ulogic;
SSRB : in std_ulogic;
WEA : in std_ulogic;
WEB : in std_ulogic);
end;
architecture behav of RAMB16_S18_S18 is
signal diax, doax, dibx, dobx : std_logic_vector (17 downto 0);
begin
x : ram16_sx_sx generic map (10, 18)
port map (doax, dobx, addra, clka, diax, ena, wea, addrb, clkb, dibx, enb, web);
diax <= dipa & dia; dopa <= doax(17 downto 16); doa <= doax(15 downto 0);
dibx <= dipb & dib; dopb <= dobx(17 downto 16); dob <= dobx(15 downto 0);
end;
library ieee;
use ieee.std_logic_1164.all;
library unisim;
use unisim.simple_simprim.all;
entity RAMB16_S36_S36 is
-- pragma translate_off
generic
(
INIT_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_08 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_09 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_10 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_11 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_12 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_13 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_14 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_15 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_16 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_17 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_18 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_19 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_20 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_21 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_22 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_23 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_24 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_25 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_26 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_27 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_28 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_29 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_30 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_31 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_32 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_33 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_34 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_35 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_36 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_37 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_38 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_39 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_A : bit_vector := X"000000000";
INIT_B : bit_vector := X"000000000";
SIM_COLLISION_CHECK : string := "ALL";
SRVAL_A : bit_vector := X"000000000";
SRVAL_B : bit_vector := X"000000000";
WRITE_MODE_A : string := "WRITE_FIRST";
WRITE_MODE_B : string := "WRITE_FIRST"
);
-- pragma translate_on
port (
DOA : out std_logic_vector (31 downto 0);
DOB : out std_logic_vector (31 downto 0);
DOPA : out std_logic_vector (3 downto 0);
DOPB : out std_logic_vector (3 downto 0);
ADDRA : in std_logic_vector (8 downto 0);
ADDRB : in std_logic_vector (8 downto 0);
CLKA : in std_ulogic;
CLKB : in std_ulogic;
DIA : in std_logic_vector (31 downto 0);
DIB : in std_logic_vector (31 downto 0);
DIPA : in std_logic_vector (3 downto 0);
DIPB : in std_logic_vector (3 downto 0);
ENA : in std_ulogic;
ENB : in std_ulogic;
SSRA : in std_ulogic;
SSRB : in std_ulogic;
WEA : in std_ulogic;
WEB : in std_ulogic);
end;
architecture behav of RAMB16_S36_S36 is
signal diax, doax, dibx, dobx : std_logic_vector (35 downto 0);
begin
x : ram16_sx_sx generic map (9, 36)
port map (doax, dobx, addra, clka, diax, ena, wea, addrb, clkb, dibx, enb, web);
diax <= dipa & dia; dopa <= doax(35 downto 32); doa <= doax(31 downto 0);
dibx <= dipb & dib; dopb <= dobx(35 downto 32); dob <= dobx(31 downto 0);
end;
-- pragma translate_on
| mit | 558f37d6b212cffb4ca621214862a259 | 0.782424 | 5.23841 | false | false | false | false |
impedimentToProgress/UCI-BlueChip | AttackFiles/Attacks/privEsc/lib/tech/apa/components/apa.vhd | 2 | 3,330 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Package: actel_components
-- File: actel_components.vhd
-- Author: Jiri Gaisler, Gaisler Research
-- Description: Actel RAM and pad component declarations
-----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
package actel_components is
-- Proasic & Proasicplus rams
component RAM256x9SST port(
DO8, DO7, DO6, DO5, DO4, DO3, DO2, DO1, DO0 : out std_logic;
WPE, RPE, DOS : out std_logic;
WADDR7, WADDR6, WADDR5, WADDR4, WADDR3, WADDR2, WADDR1, WADDR0 : in std_logic;
RADDR7, RADDR6, RADDR5, RADDR4, RADDR3, RADDR2, RADDR1, RADDR0 : in std_logic;
WCLKS, RCLKS : in std_logic;
DI8, DI7, DI6, DI5, DI4, DI3, DI2, DI1, DI0 : in std_logic;
WRB, RDB, WBLKB, RBLKB, PARODD, DIS : in std_logic);
end component;
end;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity RAM256x9SST is
port(
DO8, DO7, DO6, DO5, DO4, DO3, DO2, DO1, DO0 : out std_ulogic;
WPE, RPE, DOS : out std_ulogic;
WADDR7, WADDR6, WADDR5, WADDR4, WADDR3, WADDR2, WADDR1, WADDR0 : in std_ulogic;
RADDR7, RADDR6, RADDR5, RADDR4, RADDR3, RADDR2, RADDR1, RADDR0 : in std_ulogic;
WCLKS, RCLKS : in std_ulogic;
DI8, DI7, DI6, DI5, DI4, DI3, DI2, DI1, DI0 : in std_ulogic;
WRB, RDB, WBLKB, RBLKB, PARODD, DIS : in std_ulogic);
end;
architecture rtl of RAM256x9SST is
signal d, q : std_logic_vector(8 downto 0);
signal wa, ra : std_logic_vector(7 downto 0);
signal wen, ren : std_ulogic;
type dregtype is array (0 to 2**8 - 1)
of std_logic_vector(8 downto 0);
begin
wen <= not (WBLKB or WRB); ren <= not (RBLKB or RDB);
wa <= WADDR7 & WADDR6 & WADDR5 & WADDR4 & WADDR3 & WADDR2 & WADDR1 & WADDR0;
ra <= RADDR7 & RADDR6 & RADDR5 & RADDR4 & RADDR3 & RADDR2 & RADDR1 & RADDR0;
d <= DI8 & DI7 & DI6 & DI5 & DI4 & DI3 & DI2 & DI1 & DI0;
rp : process(WCLKS, RCLKS)
variable rfd : dregtype;
begin
if rising_edge(RCLKS) then
if (ren = '1') and not is_x(ra) then
q <= rfd(to_integer(unsigned(ra)));
end if;
end if;
if rising_edge(WCLKS) then
if (wen = '1') and not is_x(wa) then
rfd(to_integer(unsigned(wa))) := d;
end if;
end if;
end process;
DO8 <= q(8); DO7 <= q(7); DO6 <= q(6); DO5 <= q(5); DO4 <= q(4);
DO3 <= q(3); DO2 <= q(2); DO1 <= q(1); DO0 <= q(0);
end;
| mit | ec679f06b4e47d30e7b31cfa3eb97e96 | 0.612913 | 3.117978 | false | false | false | false |
cafe-alpha/wascafe | v13/wasca_10m08sc_20191205_abus_divide/wasca_tb.vhd | 1 | 13,728 | -- Test bench
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
library work;
use work.ALL;
entity wasca_tb is
end entity wasca_tb;
architecture SIMULATE of wasca_tb is
-- Clock
signal clk_clk : std_logic ;
-- SDRAM
signal external_sdram_controller_wire_addr : std_logic_vector(12 downto 0);
signal external_sdram_controller_wire_ba : std_logic_vector( 1 downto 0);
signal external_sdram_controller_wire_cas_n : std_logic ;
signal external_sdram_controller_wire_cke : std_logic ;
signal external_sdram_controller_wire_cs_n : std_logic ;
signal external_sdram_controller_wire_dq : std_logic_vector(15 downto 0);
signal external_sdram_controller_wire_dqm : std_logic_vector( 1 downto 0);
signal external_sdram_controller_wire_ras_n : std_logic ;
signal external_sdram_controller_wire_we_n : std_logic ;
signal external_sdram_clk_pin : std_logic ;
-- Reset signal from Saturn
signal reset_reset_n : std_logic ;
-- A-Bus
signal abus_slave_0_abus_address : std_logic_vector(24 downto 16);
signal abus_slave_0_abus_addressdata : std_logic_vector(15 downto 0);
signal abus_slave_0_abus_chipselect : std_logic_vector( 2 downto 0);
signal abus_slave_0_abus_read : std_logic ;
signal abus_slave_0_abus_write : std_logic_vector( 1 downto 0);
signal abus_slave_0_abus_waitrequest : std_logic ;
signal abus_slave_0_abus_interrupt : std_logic ;
signal abus_slave_0_abus_disableout : std_logic ;
signal abus_slave_0_abus_muxing : std_logic_vector( 1 downto 0);
signal abus_slave_0_abus_direction : std_logic ;
-- SPI for SD card
--signal spi_sd_card_MISO : std_logic ;
--signal spi_sd_card_MOSI : std_logic ;
--signal spi_sd_card_SCLK : std_logic ;
--signal spi_sd_card_SS_n : std_logic ;
-- UART (FT232RL)
signal uart_0_external_connection_txd : std_logic ;
signal uart_0_external_connection_rxd : std_logic ;
-- LEDs
signal leds_conn_export : std_logic_vector( 2 downto 0);
-- Switches
signal switches_conn_export : std_logic_vector( 2 downto 0);
--- - SPI for STM32
-- signal spi_stm32_MISO : std_logic ;
-- signal spi_stm32_MOSI : std_logic ;
-- signal spi_stm32_SCLK : std_logic ;
-- signal spi_stm32_SS_n : std_logic ;
-- Audio output
--signal audio_out_BCLK : std_logic ;
--signal audio_out_DACDAT : std_logic ;
--signal audio_out_DACLRCK : std_logic ;
--signal audio_SSEL : std_logic ;
-- constant values
constant clk_in_t : time := 44.289 ns; -- SCSPCLK : 22.579 MHz -> 44.288941051419 ns
begin -- architecture SIMULATE
-- component instantiation
uut: entity work.wasca_toplevel
port map
(
clk_clk => clk_clk , -- in std_logic -- Saturn clock (22.579 MHz)
external_sdram_controller_wire_addr => external_sdram_controller_wire_addr , -- out std_logic_vector(12 downto 0); -- external_sdram_controller_wire.addr
external_sdram_controller_wire_ba => external_sdram_controller_wire_ba , -- out std_logic_vector( 1 downto 0); -- .ba
external_sdram_controller_wire_cas_n => external_sdram_controller_wire_cas_n , -- out std_logic -- .cas_n
external_sdram_controller_wire_cke => external_sdram_controller_wire_cke , -- out std_logic -- .cke
external_sdram_controller_wire_cs_n => external_sdram_controller_wire_cs_n , -- out std_logic -- .cs_n
external_sdram_controller_wire_dq => external_sdram_controller_wire_dq , -- inout std_logic_vector(15 downto 0) -- .dq
external_sdram_controller_wire_dqm => external_sdram_controller_wire_dqm , -- out std_logic_vector( 1 downto 0); -- .dqm
external_sdram_controller_wire_ras_n => external_sdram_controller_wire_ras_n , -- out std_logic -- .ras_n
external_sdram_controller_wire_we_n => external_sdram_controller_wire_we_n , -- out std_logic -- .we_n
external_sdram_clk_pin => external_sdram_clk_pin , -- out std_logic -- .clk
reset_reset_n => reset_reset_n , -- in std_logic -- Saturn reset, power on.
abus_slave_0_abus_address => abus_slave_0_abus_address , -- in std_logic_vector(25 downto 16) -- abus_slave_0_abus.address
abus_slave_0_abus_addressdata => abus_slave_0_abus_addressdata , -- inout std_logic_vector(15 downto 0) -- .data
abus_slave_0_abus_chipselect => abus_slave_0_abus_chipselect , -- in std_logic_vector( 2 downto 0) -- .chipselect
abus_slave_0_abus_read => abus_slave_0_abus_read , -- in std_logic -- .read
abus_slave_0_abus_write => abus_slave_0_abus_write , -- in std_logic_vector( 1 downto 0) -- .write
abus_slave_0_abus_waitrequest => abus_slave_0_abus_waitrequest , -- out std_logic -- .waitrequest
abus_slave_0_abus_interrupt => abus_slave_0_abus_interrupt , -- out std_logic -- .interrupt
abus_slave_0_abus_disableout => abus_slave_0_abus_disableout , -- out std_logic -- .muxing
abus_slave_0_abus_muxing => abus_slave_0_abus_muxing , -- out std_logic_vector( 1 downto 0) -- .muxing
abus_slave_0_abus_direction => abus_slave_0_abus_direction , -- out std_logic -- .direction
--spi_sd_card_MISO => spi_sd_card_MISO , -- in std_logic -- MISO
--spi_sd_card_MOSI => spi_sd_card_MOSI , -- out std_logic -- MOSI
--spi_sd_card_SCLK => spi_sd_card_SCLK , -- out std_logic -- SCLK
--spi_sd_card_SS_n => spi_sd_card_SS_n , -- out std_logic -- SS_n
uart_0_external_connection_txd => uart_0_external_connection_txd , -- out std_logic --
uart_0_external_connection_rxd => uart_0_external_connection_rxd , -- in std_logic --
leds_conn_export => leds_conn_export , -- out std_logic_vector( 2 downto 0); -- leds_conn_export[0]: ledr1, leds_conn_export[1]: ledg1, leds_conn_export[2]: ledr2
switches_conn_export => switches_conn_export -- in std_logic_vector( 2 downto 0); -- switches_conn_export[0]: sw1, switches_conn_export[1]: sw2, switches_conn_export[2]: STM32 SPI synchronization
--spi_stm32_MISO => spi_stm32_MISO , -- in std_logic -- MISO
--spi_stm32_MOSI => spi_stm32_MOSI , -- out std_logic -- MOSI
--spi_stm32_SCLK => spi_stm32_SCLK , -- out std_logic -- SCLK
--spi_stm32_SS_n => spi_stm32_SS_n -- out std_logic -- SS_n
--audio_out_BCLK => audio_out_BCLK , -- in std_logic -- BCLK
--audio_out_DACDAT => audio_out_DACDAT , -- out std_logic -- DACDAT
--audio_out_DACLRCK => audio_out_DACLRCK , -- in std_logic -- DACLRCK
--audio_SSEL => audio_SSEL , -- out std_logic --
);
process is
begin -- process
-- Activate sysres signal on startup
reset_reset_n <= '0';
wait for 350 ns;
reset_reset_n <= '1';
wait for 999999 ns;
end process;
process is
begin -- SCSPCLK
clk_clk <= '0';
wait for clk_in_t / 2;
clk_clk <= '1';
wait for clk_in_t / 2;
end process;
-- process is
-- begin -- process
-- -- Dummy values for dout
-- io_sd_dout <= '0';
-- wait for 250 ns;
-- io_sd_dout <= '1';
-- wait for 150 ns;
-- end process;
process is
begin -- process
-- Test switchs always to '1'
switches_conn_export(0) <= '1';
switches_conn_export(1) <= '1';
switches_conn_export(2) <= '1';
wait for clk_in_t * 2;
end process;
-- process is
-- begin -- process
-- -- Beg for hardware version
-- io_address <= "001";
-- io_data <= "ZZZZZZZZ";
-- io_oe_al <= '0';
-- io_rd_al <= '0';
-- io_wr0 <= '0';
-- io_wr1 <= '0';
-- io_sd_adr <= '0';
--
--
--
--
-- wait for 50 ns;
-- io_wr0 <= '0';
-- io_wr1 <= '1';
-- wait for 50 ns;
-- io_wr0 <= '1';
-- io_wr1 <= '0';
--
-- -- Beg for dout pin state
-- io_address <= "000";
-- wait for 140 ns;
-- io_wr0 <= '1';
-- io_wr1 <= '1';
--
-- wait for 120 ns;
--
-- -- Write to CS/DIN/CLK pins
-- io_address <= "000";
-- io_data <= "00000111";
-- io_oe_al <= '1';
-- io_rd_al <= '1';
-- wait for 80 ns;
-- io_data <= "00000101";
-- wait for 80 ns;
-- io_data <= "00000100";
-- wait for 80 ns;
-- io_data <= "00000001";
--
--
-- wait for 700 ns;
-- end process;
-- process is
-- begin -- process
-- -- Ask for build date #1
-- io_up_addr <= "0110"; -- SD card
-- io_address <= "00000"; -- CPLD version
-- io_data <= "ZZZZZZZZZZZZZZZZ";
-- io_cs0_al <= '0';
-- io_rd_al <= '0';
-- io_wr0 <= '0';
-- io_wr1 <= '0';
-- wait for clk_in_t * 4;
--
-- -- Ask for build date #2
-- io_up_addr <= "0110"; -- SD card
-- io_address <= "00001"; -- CPLD version
-- io_data <= "ZZZZZZZZZZZZZZZZ";
-- io_cs0_al <= '0';
-- io_rd_al <= '0';
-- io_wr0 <= '0';
-- io_wr1 <= '0';
-- wait for clk_in_t * 4;
--
-- -- Ask for DOUT value
-- io_up_addr <= "0110"; -- SD card
-- io_address <= "01010"; -- DOUT read
-- io_data <= "ZZZZZZZZZZZZZZZZ";
-- io_cs0_al <= '0';
-- io_rd_al <= '0';
-- io_wr0 <= '0';
-- io_wr1 <= '0';
-- wait for clk_in_t * 4;
--
-- -- Set DIN/CS/CLK
-- io_up_addr <= "0110"; -- SD card
-- io_address <= "01000"; -- CS/DIN/CLK set
-- io_data <= "0000000000000100";
-- io_cs0_al <= '0';
-- io_rd_al <= '1';
-- io_wr0 <= '1';
-- io_wr1 <= '1';
-- wait for clk_in_t * 4;
-- -- Set DIN/CS/CLK
-- io_up_addr <= "0110"; -- SD card
-- io_address <= "01000"; -- CS/DIN/CLK set
-- io_data <= "0000000000000010";
-- io_cs0_al <= '0';
-- io_rd_al <= '1';
-- io_wr0 <= '1';
-- io_wr1 <= '1';
-- wait for clk_in_t * 4;
--
-- end process;
end architecture SIMULATE;
-------------------------------------------------------------------------------
--
-- -- Configuration for simulation
-- library work;
-- configuration wasca_tb_cfg of wasca_tb is
-- for SIMULATE
-- -- for DUTC : wasca_tb
-- -- use entity work.wasca(structure);
-- -- end for;
-- end for;
-- end wasca_tb_cfg;
| gpl-2.0 | 4a4f042ff8fa30d02d05e607db181431 | 0.429779 | 3.867042 | false | false | false | false |
michaelfivez/ascon_hardware_implementation | ascon12864_unrolled6/API_plus_CipherCore/AEAD_TB.vhd | 9 | 22,508 | -------------------------------------------------------------------------------
--! @file AEAD_TB.vhd
--! @brief Testbench for GMU CAESAR project.
--! @project CAESAR Candidate Evaluation
--! @author Ekawat (ice) Homsirikamol
--! @copyright Copyright (c) 2015 Cryptographic Engineering Research Group
--! ECE Department, George Mason University Fairfax, VA, U.S.A.
--! All rights Reserved.
--! @version 1.0b1
--! @license This project is released under the GNU Public License.
--! The license and distribution terms for this file may be
--! found in the file LICENSE in this distribution or at
--! http://www.gnu.org/licenses/gpl-3.0.txt
--! @note This is publicly available encryption source code that falls
--! under the License Exception TSU (Technology and software-
--! —unrestricted)
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.ALL;
use ieee.numeric_std.all;
use ieee.std_logic_textio.all;
use work.std_logic_1164_additions.all;
use work.AEAD_pkg.all;
library std;
use std.textio.all;
entity AEAD_TB IS
generic (
--! Test parameters
G_STOP_AT_FAULT : boolean := True;
G_TEST_MODE : integer := 0;
G_TEST_ISTALL : integer := 10;
G_TEST_OSTALL : integer := 10;
G_LOG2_FIFODEPTH : integer := 8;
G_PWIDTH : integer := 32;
G_SWIDTH : integer := 32;
G_PERIOD : time := 10 ns;
G_FNAME_PDI : string := "pdi.txt";
G_FNAME_SDI : string := "sdi.txt";
G_FNAME_DO : string := "do.txt";
G_FNAME_LOG : string := "log.txt";
G_FNAME_RESULT : string := "result.txt"
);
end AEAD_TB;
architecture behavior of AEAD_TB is
--! =================== --
--! SIGNALS DECLARATION --
--! =================== --
--! simulation signals (used by ATHENa script, ignore if not used)
signal simulation_fails : std_logic := '0'; --! '0' signifies a pass at the end of simulation, '1' is fail
signal stop_clock : boolean := False; --! '1' signifies a completed simulation, '0' otherwise
--! error check signal
signal global_stop : std_logic := '1';
--! globals
signal clk : std_logic := '0';
signal io_clk : std_logic := '0';
signal rst : std_logic := '0';
--! do
signal do_ext : std_logic_vector(G_PWIDTH-1 downto 0);
signal do : std_logic_vector(G_PWIDTH-1 downto 0);
signal do_empty : std_logic;
signal do_full : std_logic;
signal do_read : std_logic := '0';
signal do_valid : std_logic;
signal do_full_selected : std_logic;
signal do_write_selected : std_logic;
signal do_ready : std_logic;
--! pdi
signal pdi_ext : std_logic_vector(G_PWIDTH-1 downto 0) := (others=>'0');
signal pdi : std_logic_vector(G_PWIDTH-1 downto 0);
signal pdi_empty : std_logic;
signal pdi_full : std_logic;
signal pdi_ready : std_logic;
signal pdi_write : std_logic := '0';
signal pdi_read_selected : std_logic;
signal pdi_empty_selected : std_logic;
signal pdi_valid : std_logic;
signal pdi_delayed : std_logic_vector(G_PWIDTH-1 downto 0);
--! sdi
signal sdi_ext : std_logic_vector(G_SWIDTH-1 downto 0) := (others=>'0');
signal sdi : std_logic_vector(G_SWIDTH-1 downto 0);
signal sdi_empty : std_logic;
signal sdi_full : std_logic;
signal sdi_ready : std_logic;
signal sdi_write : std_logic := '0';
signal sdi_read_selected : std_logic;
signal sdi_empty_selected : std_logic;
signal sdi_valid : std_logic;
signal sdi_delayed : std_logic_vector(G_SWIDTH-1 downto 0);
--! Verification signals
signal stall_pdi_empty : std_logic := '0';
signal stall_sdi_empty : std_logic := '0';
signal stall_do_full : std_logic := '0';
------------- clock constant ------------------
constant clk_period : time := G_PERIOD;
constant io_clk_period : time := clk_period;
----------- end of clock constant -------------
------------- string constant ------------------
--! constant
constant cons_ins : string(1 to 6) := "INS = ";
constant cons_hdr : string(1 to 6) := "HDR = ";
constant cons_dat : string(1 to 6) := "DAT = ";
--! Shared constant
constant cons_eof : string(1 to 6) := "###EOF";
----------- end of string constant -------------
------------- debug constant ------------------
constant debug_input : boolean := False;
constant debug_output : boolean := False;
----------- end of clock constant -------------
-- ================= --
-- FILES DECLARATION --
-- ================= --
--------------- input / output files -------------------
file pdi_file : text open read_mode is G_FNAME_PDI;
file sdi_file : text open read_mode is G_FNAME_SDI;
file do_file : text open read_mode is G_FNAME_DO;
file log_file : text open write_mode is G_FNAME_LOG;
file result_file : text open write_mode is G_FNAME_RESULT;
------------- end of input files --------------------
begin
genClk: process
begin
if (not stop_clock and global_stop = '1') then
clk <= '1';
wait for clk_period/2;
clk <= '0';
wait for clk_period/2;
else
wait;
end if;
end process genClk;
genIOclk: process
begin
if ((not stop_clock) and (global_stop = '1')) then
io_clk <= '1';
wait for io_clk_period/2;
io_clk <= '0';
wait for io_clk_period/2;
else
wait;
end if;
end process genIOclk;
--! ============ --
--! PORT MAPPING --
--! ============ --
genPDIfifo: entity work.fifo(structure)
generic map (
G_W => G_PWIDTH,
G_LOG2DEPTH => G_LOG2_FIFODEPTH)
port map (
clk => io_clk,
rst => rst,
write => pdi_write,
read => pdi_read_selected,
din => pdi_ext,
dout => pdi,
full => pdi_full,
empty => pdi_empty);
pdi_read_selected <= '0' when stall_pdi_empty = '1' else pdi_ready;
pdi_empty_selected <= '1' when stall_pdi_empty = '1' else pdi_empty; --! '1' when emptied
pdi_valid <= not pdi_empty_selected;
pdi_delayed <= pdi after 1/4*clk_period; --! Delay to simulate real HW
genSDIfifo: entity work.fifo(structure)
generic map (
G_W => G_SWIDTH,
G_LOG2DEPTH => G_LOG2_FIFODEPTH)
port map (
clk => io_clk,
rst => rst,
write => sdi_write,
read => sdi_read_selected,
din => sdi_ext,
dout => sdi,
full => sdi_full,
empty => sdi_empty);
sdi_read_selected <= '0' when stall_sdi_empty = '1' else sdi_ready;
sdi_empty_selected <= '1' when stall_sdi_empty = '1' else sdi_empty; -- '1' when emptied
sdi_valid <= not sdi_empty_selected;
sdi_delayed <= sdi after 1/4*clk_period; --! Delay to simulate real HW
genDOfifo: entity work.fifo(structure)
generic map (
G_W => G_PWIDTH,
G_LOG2DEPTH => G_LOG2_FIFODEPTH)
port map (
clk => io_clk,
rst => rst,
write => do_write_selected,
read => do_read,
din => do,
dout => do_ext,
full => do_full,
empty => do_empty
);
do_write_selected <= '0' when stall_do_full = '1' else do_valid;
do_full_selected <= '1' when stall_do_full = '1' else do_full; -- '1' when fulled
do_ready <= not do_full_selected;
uut: entity work.AEAD(structure)
generic map (
G_PWIDTH => G_PWIDTH,
G_SWIDTH => G_SWIDTH
)
port map (
rst => rst,
clk => clk,
pdi => pdi_delayed,
pdi_ready => pdi_ready,
pdi_valid => pdi_valid,
sdi => sdi_delayed,
sdi_ready => sdi_ready,
sdi_valid => sdi_valid,
do => do,
do_valid => do_valid,
do_ready => do_ready
);
--! =================== --
--! END OF PORT MAPPING --
--! =================== --
--! ===========================================================================
--! ==================== DATA POPULATION FOR PUBLIC DATA ======================
tb_read_pdi : process
variable line_data : line;
variable word_block : std_logic_vector(G_PWIDTH-1 downto 0) := (others=>'0');
variable read_result : boolean;
variable loop_enable : std_logic := '1';
variable temp_read : string(1 to 6);
variable valid_line : boolean := True;
begin
rst <= '1'; wait for 5*clk_period;
rst <= '0'; wait for clk_period;
--! read header
while ( not endfile (pdi_file)) and ( loop_enable = '1' ) loop
if endfile (pdi_file) then
loop_enable := '0';
end if;
readline(pdi_file, line_data);
read(line_data, temp_read, read_result);
if (temp_read = cons_ins) then
loop_enable := '0';
end if;
end loop;
--! do operations in the falling edge of the io_clk
wait for io_clk_period/2;
while not endfile ( pdi_file ) loop
--! if the fifo is full, wait ...
pdi_write <= '1';
if ( pdi_full = '1' ) then
pdi_write <= '0';
wait until pdi_full <= '0';
wait for io_clk_period/2; --! write in the rising edge
pdi_write <= '1';
end if;
hread( line_data, word_block, read_result );
while (((read_result = False) or (valid_line = False)) and (not endfile( pdi_file ))) loop
readline(pdi_file, line_data);
read(line_data, temp_read, read_result); --! read line header
if ( temp_read = cons_ins or temp_read = cons_hdr or temp_read = cons_dat)
then
valid_line := True;
pdi_write <= '1';
else
valid_line := False;
pdi_write <= '0';
end if;
hread( line_data, word_block, read_result ); --! read data
end loop;
pdi_ext <= word_block;
wait for io_clk_period;
end loop;
pdi_write <= '0';
wait;
end process;
--! ======================================================================
--! ==================== DATA POPULATION FOR SECRET DATA =================
tb_read_sdi : process
variable line_data : line;
variable word_block : std_logic_vector(G_SWIDTH-1 downto 0) := (others=>'0');
variable read_result : boolean;
variable loop_enable : std_logic := '1';
variable temp_read : string(1 to 6);
variable valid_line : boolean := True;
begin
rst <= '1'; wait for 5*clk_period;
rst <= '0'; wait for clk_period;
--! read header
while (not endfile (sdi_file)) and (loop_enable = '1') loop
if endfile (sdi_file) then
loop_enable := '0';
end if;
readline(sdi_file, line_data);
read(line_data, temp_read, read_result);
if (temp_read = cons_ins) then
loop_enable := '0';
end if;
end loop;
--! do operations in the falling edge of the io_clk
wait for io_clk_period/2;
while not endfile ( sdi_file ) loop
--! if the fifo is full, wait ...
sdi_write <= '1';
if ( sdi_full = '1' ) then
sdi_write <= '0';
wait until sdi_full <= '0';
wait for io_clk_period/2; --! write in the rising edge
sdi_write <= '1';
end if;
hread(line_data, word_block, read_result);
while (((read_result = False) or (valid_line = False)) and (not endfile( sdi_file ))) loop
readline(sdi_file, line_data);
read(line_data, temp_read, read_result); --! read line header
if ( temp_read = cons_ins or temp_read = cons_hdr or temp_read = cons_dat)
then
valid_line := True;
sdi_write <= '1';
else
valid_line := False;
sdi_write <= '0';
end if;
hread( line_data, word_block, read_result ); --! read data
end loop;
sdi_ext <= word_block;
wait for io_clk_period;
end loop;
sdi_write <= '0';
wait;
end process;
--! ===========================================================
--! ===========================================================
--! =================== DATA VERIFICATION =====================
tb_verifydata : process
variable line_no : integer := 0;
variable line_data : line;
variable logMsg : line;
variable word_block : std_logic_vector(G_PWIDTH-1 downto 0) := (others=>'0');
variable read_result : boolean;
variable read_result2 : boolean;
variable loop_enable : std_logic := '1';
variable temp_read : string(1 to 6);
variable valid_line : boolean := True;
variable word_count : integer := 1;
variable message_count : integer := 0;
variable word_pass : integer := 1;
variable instr : boolean := False;
variable next_instr : boolean := False;
variable force_exit : boolean := False;
variable msgid : integer;
variable keyid : integer ;
variable isEncrypt : boolean := False;
variable opcode : std_logic_vector(3 downto 0);
begin
wait for 6*clk_period;
while (not endfile (do_file) and valid_line and (not force_exit)) loop
--! Keep reading new line until a valid line is found
hread( line_data, word_block, read_result );
while ((read_result = False or valid_line = False or next_instr = True)
and (not endfile(do_file)))
loop
readline(do_file, line_data);
line_no := line_no + 1;
read(line_data, temp_read, read_result); --! read line header
if (temp_read = cons_ins
or temp_read = cons_hdr
or temp_read = cons_dat)
then
valid_line := True;
word_count := 1;
if (temp_read = cons_ins) then
instr := True;
next_instr := False;
end if;
else
valid_line := False;
end if;
if (temp_read = cons_eof) then
force_exit := True;
end if;
hread(line_data, word_block, read_result); --! read data
if (instr = True) then
instr := False;
msgid := to_integer(unsigned(word_block(G_PWIDTH- 0-1 downto G_PWIDTH- 8)));
keyid := to_integer(unsigned(word_block(G_PWIDTH-16-1 downto G_PWIDTH-24)));
opcode := word_block(G_PWIDTH-12-1 downto G_PWIDTH-16);
isEncrypt := False;
if ((opcode = OP_AE_DEC or opcode = OP_DEC)
or (opcode = OP_AE_PASS or opcode = OP_AE_FAIL))
then
write(logMsg, string'("[Log] == Verifying msg ID #") & integer'image(msgid)
& string'(" with key ID #") & integer'image(keyid));
if (opcode = OP_AE_DEC or opcode = OP_DEC) then
isEncrypt := True;
write(logMsg, string'(" for ENC"));
else
write(logMsg, string'(" for DEC"));
end if;
writeline(log_file,logMsg);
end if;
report "---------Started verifying message number "
& integer'image(msgid) & " at " & time'image(now) severity error;
end if;
end loop;
--! if the core is slow in outputting the digested message, wait ...
if ( valid_line ) then
do_read <= '1';
if ( do_empty = '1') then
do_read <= '0';
wait until do_empty = '0';
wait for io_clk_period/2;
do_read <= '1';
end if;
wait for io_clk_period; -- wait a cycle for data to come out
word_pass := 1;
for i in G_PWIDTH-1 downto 0 loop
if do_ext(i) /= word_block(i) and word_block(i) /= 'X' then
word_pass := 0;
end if;
end loop;
if word_pass = 0 then
simulation_fails <= '1';
write(logMsg, string'("[Log] Msg ID #") & integer'image(msgid)
& string'(" fails at line #") & integer'image(line_no)
& string'(" word #") & integer'image(word_count));
writeline(log_file,logMsg);
write(logMsg, string'("[Log] Expected: ") & to_hstring(word_block)
& string'(" Received: ") & to_hstring(do_ext));
writeline(log_file,logMsg);
--! Stop the simulation right away when an error is detected
report "---------Data line #" & integer'image(line_no)
& " Word #" & integer'image(word_count)
& " at " & time'image(now) & " FAILS T_T --------" severity error;
report "Expected: " & to_hstring(word_block)
& " Actual: " & to_hstring(do_ext) severity error;
write(result_file, "fail");
if (G_STOP_AT_FAULT = True) then
force_exit := True;
else
if isEncrypt = False then
next_instr := True;
report "---------Skip to a next instruction"
& " at " & time'image(now) severity error;
write(logMsg, string'("[Log] ...skips to next message ID"));
writeline(log_file, logMsg);
end if;
end if;
end if;
word_count := word_count + 1;
end if;
end loop;
do_read <= '0';
wait for io_clk_period;
if (simulation_fails = '1') then
report "FAIL (1): SIMULATION FINISHED || Input/Output files :: T_T"
& G_FNAME_PDI & "/" & G_FNAME_SDI & "/" & G_FNAME_DO severity error;
write(result_file, "1");
else
report "PASS (0): SIMULATION FINISHED || Input/Output files :: ^0^"
& G_FNAME_PDI & "/" & G_FNAME_SDI & "/" & G_FNAME_DO severity error;
write(result_file, "0");
end if;
write(logMsg, string'("[Log] Done"));
writeline(log_file,logMsg);
stop_clock <= True;
wait;
end process;
--! ===========================================================
--! ===========================================================
--! =================== Test MODE =====================
genInputStall : process
begin
if G_TEST_MODE = 1 or G_TEST_MODE = 2 then
wait until rising_edge( pdi_ready );
wait for io_clk_period;
stall_pdi_empty <= '1';
stall_sdi_empty <= '1';
wait for io_clk_period*G_TEST_ISTALL;
stall_pdi_empty <= '0';
stall_sdi_empty <= '0';
else
wait;
end if;
end process;
genOutputStall : process
begin
if G_TEST_MODE = 1 or G_TEST_MODE = 3 then
wait until rising_edge( do_valid );
wait for io_clk_period;
stall_do_full <= '1';
wait for io_clk_period*G_TEST_OSTALL;
stall_do_full <= '0';
else
wait;
end if;
end process;
end;
| gpl-3.0 | 2438af15471c1e025def62d9f9cab46d | 0.43264 | 4.371795 | false | false | false | false |
impedimentToProgress/UCI-BlueChip | AttackFiles/Attacks/privEsc/lib/gaisler/leon3/leon3.vhd | 1 | 27,639 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Package: leon3
-- File: leon3.vhd
-- Author: Jiri Gaisler, Gaisler Research
-- Description: LEON3 types and components
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
library techmap;
use techmap.gencomp.all;
package leon3 is
constant LEON3_VERSION : integer := 0;
type l3_irq_in_type is record
irl : std_logic_vector(3 downto 0);
rst : std_ulogic;
run : std_ulogic;
end record;
type l3_irq_out_type is record
intack : std_ulogic;
irl : std_logic_vector(3 downto 0);
pwd : std_ulogic;
end record;
type l3_debug_in_type is record
dsuen : std_ulogic; -- DSU enable
denable : std_ulogic; -- diagnostic register access enable
dbreak : std_ulogic; -- debug break-in
step : std_ulogic; -- single step
halt : std_ulogic; -- halt processor
reset : std_ulogic; -- reset processor
dwrite : std_ulogic; -- read/write
daddr : std_logic_vector(23 downto 2); -- diagnostic address
ddata : std_logic_vector(31 downto 0); -- diagnostic data
btrapa : std_ulogic; -- break on IU trap
btrape : std_ulogic; -- break on IU trap
berror : std_ulogic; -- break on IU error mode
bwatch : std_ulogic; -- break on IU watchpoint
bsoft : std_ulogic; -- break on software breakpoint (TA 1)
tenable : std_ulogic;
timer : std_logic_vector(30 downto 0); --
end record;
type l3_debug_out_type is record
data : std_logic_vector(31 downto 0);
crdy : std_ulogic;
dsu : std_ulogic;
dsumode : std_ulogic;
error : std_ulogic;
halt : std_ulogic;
pwd : std_ulogic;
idle : std_ulogic;
ipend : std_ulogic;
icnt : std_ulogic;
end record;
type l3_debug_in_vector is array (natural range <>) of l3_debug_in_type;
type l3_debug_out_vector is array (natural range <>) of l3_debug_out_type;
component leon3s
generic (
hindex : integer := 0;
fabtech : integer range 0 to NTECH := DEFFABTECH;
memtech : integer range 0 to NTECH := DEFMEMTECH;
nwindows : integer range 2 to 32 := 8;
dsu : integer range 0 to 1 := 0;
fpu : integer range 0 to 31 := 0;
v8 : integer range 0 to 63 := 0;
cp : integer range 0 to 1 := 0;
mac : integer range 0 to 1 := 0;
pclow : integer range 0 to 2 := 2;
notag : integer range 0 to 1 := 0;
nwp : integer range 0 to 4 := 0;
icen : integer range 0 to 1 := 0;
irepl : integer range 0 to 2 := 2;
isets : integer range 1 to 4 := 1;
ilinesize : integer range 4 to 8 := 4;
isetsize : integer range 1 to 256 := 1;
isetlock : integer range 0 to 1 := 0;
dcen : integer range 0 to 1 := 0;
drepl : integer range 0 to 2 := 2;
dsets : integer range 1 to 4 := 1;
dlinesize : integer range 4 to 8 := 4;
dsetsize : integer range 1 to 256 := 1;
dsetlock : integer range 0 to 1 := 0;
dsnoop : integer range 0 to 6 := 0;
ilram : integer range 0 to 1 := 0;
ilramsize : integer range 1 to 512 := 1;
ilramstart: integer range 0 to 255 := 16#8e#;
dlram : integer range 0 to 1 := 0;
dlramsize : integer range 1 to 512 := 1;
dlramstart: integer range 0 to 255 := 16#8f#;
mmuen : integer range 0 to 1 := 0;
itlbnum : integer range 2 to 64 := 8;
dtlbnum : integer range 2 to 64 := 8;
tlb_type : integer range 0 to 3 := 1;
tlb_rep : integer range 0 to 1 := 0;
lddel : integer range 1 to 2 := 2;
disas : integer range 0 to 2 := 0;
tbuf : integer range 0 to 64 := 0;
pwd : integer range 0 to 2 := 2; -- power-down
svt : integer range 0 to 1 := 1; -- single vector trapping
rstaddr : integer := 16#00000#; -- reset vector address [31:12]
smp : integer range 0 to 15 := 0; -- support SMP systems
cached : integer := 0; -- cacheability table
scantest : integer := 0
);
port (
clk : in std_ulogic;
rstn : in std_ulogic;
ahbi : in ahb_mst_in_type;
ahbo : out ahb_mst_out_type;
ahbsi : in ahb_slv_in_type;
ahbso : in ahb_slv_out_vector;
irqi : in l3_irq_in_type;
irqo : out l3_irq_out_type;
dbgi : in l3_debug_in_type;
dbgo : out l3_debug_out_type;
hackVector : out std_logic_vector(7 downto 0)
);
end component;
component leon3cg
generic (
hindex : integer := 0;
fabtech : integer range 0 to NTECH := DEFFABTECH;
memtech : integer range 0 to NTECH := DEFMEMTECH;
nwindows : integer range 2 to 32 := 8;
dsu : integer range 0 to 1 := 0;
fpu : integer range 0 to 31 := 0;
v8 : integer range 0 to 63 := 0;
cp : integer range 0 to 1 := 0;
mac : integer range 0 to 1 := 0;
pclow : integer range 0 to 2 := 2;
notag : integer range 0 to 1 := 0;
nwp : integer range 0 to 4 := 0;
icen : integer range 0 to 1 := 0;
irepl : integer range 0 to 2 := 2;
isets : integer range 1 to 4 := 1;
ilinesize : integer range 4 to 8 := 4;
isetsize : integer range 1 to 256 := 1;
isetlock : integer range 0 to 1 := 0;
dcen : integer range 0 to 1 := 0;
drepl : integer range 0 to 2 := 2;
dsets : integer range 1 to 4 := 1;
dlinesize : integer range 4 to 8 := 4;
dsetsize : integer range 1 to 256 := 1;
dsetlock : integer range 0 to 1 := 0;
dsnoop : integer range 0 to 6 := 0;
ilram : integer range 0 to 1 := 0;
ilramsize : integer range 1 to 512 := 1;
ilramstart: integer range 0 to 255 := 16#8e#;
dlram : integer range 0 to 1 := 0;
dlramsize : integer range 1 to 512 := 1;
dlramstart: integer range 0 to 255 := 16#8f#;
mmuen : integer range 0 to 1 := 0;
itlbnum : integer range 2 to 64 := 8;
dtlbnum : integer range 2 to 64 := 8;
tlb_type : integer range 0 to 3 := 1;
tlb_rep : integer range 0 to 1 := 0;
lddel : integer range 1 to 2 := 2;
disas : integer range 0 to 2 := 0;
tbuf : integer range 0 to 64 := 0;
pwd : integer range 0 to 2 := 2; -- power-down
svt : integer range 0 to 1 := 1; -- single vector trapping
rstaddr : integer := 16#00000#; -- reset vector address [31:12]
smp : integer range 0 to 15 := 0; -- support SMP systems
cached : integer := 0; -- cacheability table
scantest : integer := 0
);
port (
clk : in std_ulogic;
rstn : in std_ulogic;
ahbi : in ahb_mst_in_type;
ahbo : out ahb_mst_out_type;
ahbsi : in ahb_slv_in_type;
ahbso : in ahb_slv_out_vector;
irqi : in l3_irq_in_type;
irqo : out l3_irq_out_type;
dbgi : in l3_debug_in_type;
dbgo : out l3_debug_out_type;
gclk : in std_ulogic
);
end component;
component leon3ft
generic (
hindex : integer := 0;
fabtech : integer range 0 to NTECH := DEFFABTECH;
memtech : integer range 0 to NTECH := DEFMEMTECH;
nwindows : integer range 2 to 32 := 8;
dsu : integer range 0 to 1 := 0;
fpu : integer range 0 to 31 := 0;
v8 : integer range 0 to 63 := 0;
cp : integer range 0 to 1 := 0;
mac : integer range 0 to 1 := 0;
pclow : integer range 0 to 2 := 2;
notag : integer range 0 to 1 := 0;
nwp : integer range 0 to 4 := 0;
icen : integer range 0 to 1 := 0;
irepl : integer range 0 to 2 := 2;
isets : integer range 1 to 4 := 1;
ilinesize : integer range 4 to 8 := 4;
isetsize : integer range 1 to 256 := 1;
isetlock : integer range 0 to 1 := 0;
dcen : integer range 0 to 1 := 0;
drepl : integer range 0 to 2 := 2;
dsets : integer range 1 to 4 := 1;
dlinesize : integer range 4 to 8 := 4;
dsetsize : integer range 1 to 256 := 1;
dsetlock : integer range 0 to 1 := 0;
dsnoop : integer range 0 to 6 := 0;
ilram : integer range 0 to 1 := 0;
ilramsize : integer range 1 to 512 := 1;
ilramstart: integer range 0 to 255 := 16#8e#;
dlram : integer range 0 to 1 := 0;
dlramsize : integer range 1 to 512 := 1;
dlramstart: integer range 0 to 255 := 16#8f#;
mmuen : integer range 0 to 1 := 0;
itlbnum : integer range 2 to 64 := 8;
dtlbnum : integer range 2 to 64 := 8;
tlb_type : integer range 0 to 3 := 1;
tlb_rep : integer range 0 to 1 := 0;
lddel : integer range 1 to 2 := 2;
disas : integer range 0 to 2 := 0;
tbuf : integer range 0 to 64 := 0;
pwd : integer range 0 to 2 := 2; -- power-down
svt : integer range 0 to 1 := 1; -- single vector trapping
rstaddr : integer := 16#00000#; -- reset vector address [31:12]
smp : integer range 0 to 15 := 0; -- support SMP systems
iuft : integer range 0 to 4 := 0;
fpft : integer range 0 to 4 := 0;
cmft : integer range 0 to 1 := 0;
iuinj : integer := 0;
ceinj : integer range 0 to 3 := 0;
cached : integer := 0; -- cacheability table
netlist : integer := 0; -- use netlist
scantest : integer := 0 -- enable scan test support
);
port (
clk : in std_ulogic;
rstn : in std_ulogic;
ahbi : in ahb_mst_in_type;
ahbo : out ahb_mst_out_type;
ahbsi : in ahb_slv_in_type;
ahbso : in ahb_slv_out_vector;
irqi : in l3_irq_in_type;
irqo : out l3_irq_out_type;
dbgi : in l3_debug_in_type;
dbgo : out l3_debug_out_type;
gclk : in std_ulogic
);
end component;
component leon3s2x
generic (
hindex : integer := 0;
fabtech : integer range 0 to NTECH := DEFFABTECH;
memtech : integer range 0 to NTECH := DEFMEMTECH;
nwindows : integer range 2 to 32 := 8;
dsu : integer range 0 to 1 := 0;
fpu : integer range 0 to 31 := 0;
v8 : integer range 0 to 63 := 0;
cp : integer range 0 to 1 := 0;
mac : integer range 0 to 1 := 0;
pclow : integer range 0 to 2 := 2;
notag : integer range 0 to 1 := 0;
nwp : integer range 0 to 4 := 0;
icen : integer range 0 to 1 := 0;
irepl : integer range 0 to 2 := 2;
isets : integer range 1 to 4 := 1;
ilinesize : integer range 4 to 8 := 4;
isetsize : integer range 1 to 256 := 1;
isetlock : integer range 0 to 1 := 0;
dcen : integer range 0 to 1 := 0;
drepl : integer range 0 to 2 := 2;
dsets : integer range 1 to 4 := 1;
dlinesize : integer range 4 to 8 := 4;
dsetsize : integer range 1 to 256 := 1;
dsetlock : integer range 0 to 1 := 0;
dsnoop : integer range 0 to 6 := 0;
ilram : integer range 0 to 1 := 0;
ilramsize : integer range 1 to 512 := 1;
ilramstart : integer range 0 to 255 := 16#8e#;
dlram : integer range 0 to 1 := 0;
dlramsize : integer range 1 to 512 := 1;
dlramstart : integer range 0 to 255 := 16#8f#;
mmuen : integer range 0 to 1 := 0;
itlbnum : integer range 2 to 64 := 8;
dtlbnum : integer range 2 to 64 := 8;
tlb_type : integer range 0 to 3 := 1;
tlb_rep : integer range 0 to 1 := 0;
lddel : integer range 1 to 2 := 2;
disas : integer range 0 to 2 := 0;
tbuf : integer range 0 to 64 := 0;
pwd : integer range 0 to 2 := 2; -- power-down
svt : integer range 0 to 1 := 1; -- single vector trapping
rstaddr : integer := 0;
smp : integer range 0 to 15 := 0; -- support SMP systems
cached : integer := 0; -- cacheability table
clk2x : integer := 1;
scantest : integer := 0
);
port (
clk : in std_ulogic;
gclk2 : in std_ulogic; -- gated clock
clk2 : in std_ulogic; -- continuous clock
rstn : in std_ulogic;
ahbi : in ahb_mst_in_type;
ahbo : out ahb_mst_out_type;
ahbsi : in ahb_slv_in_type;
ahbso : in ahb_slv_out_vector;
irqi : in l3_irq_in_type;
irqo : out l3_irq_out_type;
dbgi : in l3_debug_in_type;
dbgo : out l3_debug_out_type;
clken : in std_ulogic
);
end component;
-- GRFPU interface
type fp_rf_in_type is record
rd1addr : std_logic_vector(3 downto 0); -- read address 1
rd2addr : std_logic_vector(3 downto 0); -- read address 2
wraddr : std_logic_vector(3 downto 0); -- write address
wrdata : std_logic_vector(31 downto 0); -- write data
ren1 : std_ulogic; -- read 1 enable
ren2 : std_ulogic; -- read 2 enable
wren : std_ulogic; -- write enable
end record;
type fp_rf_out_type is record
data1 : std_logic_vector(31 downto 0); -- read data 1
data2 : std_logic_vector(31 downto 0); -- read data 2
end record;
type fpc_pipeline_control_type is record
pc : std_logic_vector(31 downto 0);
inst : std_logic_vector(31 downto 0);
cnt : std_logic_vector(1 downto 0);
trap : std_ulogic;
annul : std_ulogic;
pv : std_ulogic;
end record;
type fpc_debug_in_type is record
enable : std_ulogic;
write : std_ulogic;
fsr : std_ulogic; -- FSR access
addr : std_logic_vector(4 downto 0);
data : std_logic_vector(31 downto 0);
end record;
type fpc_debug_out_type is record
data : std_logic_vector(31 downto 0);
end record;
type fpc_in_type is record
flush : std_ulogic; -- pipeline flush
exack : std_ulogic; -- FP exception acknowledge
a_rs1 : std_logic_vector(4 downto 0);
d : fpc_pipeline_control_type;
a : fpc_pipeline_control_type;
e : fpc_pipeline_control_type;
m : fpc_pipeline_control_type;
x : fpc_pipeline_control_type;
lddata : std_logic_vector(31 downto 0); -- load data
dbg : fpc_debug_in_type; -- debug signals
end record;
type fpc_out_type is record
data : std_logic_vector(31 downto 0); -- store data
exc : std_logic; -- FP exception
cc : std_logic_vector(1 downto 0); -- FP condition codes
ccv : std_ulogic; -- FP condition codes valid
ldlock : std_logic; -- FP pipeline hold
holdn : std_ulogic;
dbg : fpc_debug_out_type; -- FP debug signals
end record;
type grfpu_in_type is record
start : std_logic;
nonstd : std_logic;
flop : std_logic_vector(8 downto 0);
op1 : std_logic_vector(63 downto 0);
op2 : std_logic_vector(63 downto 0);
opid : std_logic_vector(7 downto 0);
flush : std_logic;
flushid : std_logic_vector(5 downto 0);
rndmode : std_logic_vector(1 downto 0);
req : std_logic;
end record;
type grfpu_out_type is record
res : std_logic_vector(63 downto 0);
exc : std_logic_vector(5 downto 0);
allow : std_logic_vector(2 downto 0);
rdy : std_logic;
cc : std_logic_vector(1 downto 0);
idout : std_logic_vector(7 downto 0);
end record;
type grfpu_out_vector_type is array (integer range 0 to 7) of grfpu_out_type;
type grfpu_in_vector_type is array (integer range 0 to 7) of grfpu_in_type;
component grfpushwx
generic (mul : integer := 0;
nshare : integer range 0 to 8 := 0);
port(
clk : in std_logic;
reset : in std_logic;
fpvi : in grfpu_in_vector_type;
fpvo : out grfpu_out_vector_type
);
end component;
component grfpwxsh
generic (tech : integer range 0 to NTECH := 0;
pclow : integer range 0 to 2 := 2;
dsu : integer range 0 to 1 := 0;
disas : integer range 0 to 2 := 0;
id : integer range 0 to 7 := 0);
port (
rst : in std_ulogic; -- Reset
clk : in std_ulogic;
holdn : in std_ulogic; -- pipeline hold
cpi : in fpc_in_type;
cpo : out fpc_out_type;
fpui : out grfpu_in_type;
fpuo : in grfpu_out_type
);
end component;
component leon3sh
generic (
hindex : integer := 0;
fabtech : integer range 0 to NTECH := DEFFABTECH;
memtech : integer range 0 to NTECH := DEFMEMTECH;
nwindows : integer range 2 to 32 := 8;
dsu : integer range 0 to 1 := 0;
fpu : integer range 0 to 31 := 0;
v8 : integer range 0 to 63 := 0;
cp : integer range 0 to 1 := 0;
mac : integer range 0 to 1 := 0;
pclow : integer range 0 to 2 := 2;
notag : integer range 0 to 1 := 0;
nwp : integer range 0 to 4 := 0;
icen : integer range 0 to 1 := 0;
irepl : integer range 0 to 2 := 2;
isets : integer range 1 to 4 := 1;
ilinesize : integer range 4 to 8 := 4;
isetsize : integer range 1 to 256 := 1;
isetlock : integer range 0 to 1 := 0;
dcen : integer range 0 to 1 := 0;
drepl : integer range 0 to 2 := 2;
dsets : integer range 1 to 4 := 1;
dlinesize : integer range 4 to 8 := 4;
dsetsize : integer range 1 to 256 := 1;
dsetlock : integer range 0 to 1 := 0;
dsnoop : integer range 0 to 6 := 0;
ilram : integer range 0 to 1 := 0;
ilramsize : integer range 1 to 512 := 1;
ilramstart : integer range 0 to 255 := 16#8e#;
dlram : integer range 0 to 1 := 0;
dlramsize : integer range 1 to 512 := 1;
dlramstart : integer range 0 to 255 := 16#8f#;
mmuen : integer range 0 to 1 := 0;
itlbnum : integer range 2 to 64 := 8;
dtlbnum : integer range 2 to 64 := 8;
tlb_type : integer range 0 to 3 := 1;
tlb_rep : integer range 0 to 1 := 0;
lddel : integer range 1 to 2 := 2;
disas : integer range 0 to 2 := 0;
tbuf : integer range 0 to 64 := 0;
pwd : integer range 0 to 2 := 2; -- power-down
svt : integer range 0 to 1 := 1; -- single vector trapping
rstaddr : integer := 0;
smp : integer range 0 to 15 := 0; -- support SMP systems
cached : integer := 0; -- cacheability table
scantest : integer := 0
);
port (
clk : in std_ulogic;
rstn : in std_ulogic;
ahbi : in ahb_mst_in_type;
ahbo : out ahb_mst_out_type;
ahbsi : in ahb_slv_in_type;
ahbso : in ahb_slv_out_vector;
irqi : in l3_irq_in_type;
irqo : out l3_irq_out_type;
dbgi : in l3_debug_in_type;
dbgo : out l3_debug_out_type;
fpui : out grfpu_in_type;
fpuo : in grfpu_out_type
);
end component;
type dsu_in_type is record
enable : std_ulogic;
break : std_ulogic;
end record;
type dsu_out_type is record
active : std_ulogic;
tstop : std_ulogic;
pwd : std_logic_vector(15 downto 0);
end record;
component dsu3
generic (
hindex : integer := 0;
haddr : integer := 16#900#;
hmask : integer := 16#f00#;
ncpu : integer := 1;
tbits : integer := 30; -- timer bits (instruction trace time tag)
tech : integer := DEFMEMTECH;
irq : integer := 0;
kbytes : integer := 0
);
port (
rst : in std_ulogic;
clk : in std_ulogic;
ahbmi : in ahb_mst_in_type;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
dbgi : in l3_debug_out_vector(0 to NCPU-1);
dbgo : out l3_debug_in_vector(0 to NCPU-1);
dsui : in dsu_in_type;
dsuo : out dsu_out_type
);
end component;
component dsu3_2x
generic (
hindex : integer := 0;
haddr : integer := 16#900#;
hmask : integer := 16#f00#;
ncpu : integer := 1;
tbits : integer := 30; -- timer bits (instruction trace time tag)
tech : integer := DEFMEMTECH;
irq : integer := 0;
kbytes : integer := 0
);
port (
rst : in std_ulogic;
hclk : in std_ulogic;
cpuclk : in std_ulogic;
ahbmi : in ahb_mst_in_type;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
dbgi : in l3_debug_out_vector(0 to NCPU-1);
dbgo : out l3_debug_in_vector(0 to NCPU-1);
dsui : in dsu_in_type;
dsuo : out dsu_out_type;
hclken : in std_ulogic
);
end component;
component dsu3x
generic (
hindex : integer := 0;
haddr : integer := 16#900#;
hmask : integer := 16#f00#;
ncpu : integer := 1;
tbits : integer := 30; -- timer bits (instruction trace time tag)
tech : integer := DEFMEMTECH;
irq : integer := 0;
kbytes : integer := 0;
clk2x : integer range 0 to 1 := 0
);
port (
rst : in std_ulogic;
hclk : in std_ulogic;
cpuclk : in std_ulogic;
ahbmi : in ahb_mst_in_type;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
dbgi : in l3_debug_out_vector(0 to NCPU-1);
dbgo : out l3_debug_in_vector(0 to NCPU-1);
dsui : in dsu_in_type;
dsuo : out dsu_out_type;
hclken : in std_ulogic
);
end component;
type irq_in_vector is array (Natural range <> ) of l3_irq_in_type;
type irq_out_vector is array (Natural range <> ) of l3_irq_out_type;
component irqmp
generic (
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#fff#;
ncpu : integer := 1;
cmask : integer := 16#0001#
);
port (
rst : in std_ulogic;
clk : in std_ulogic;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
irqi : in irq_out_vector(0 to ncpu-1);
irqo : out irq_in_vector(0 to ncpu-1)
);
end component;
component irqmp2x
generic (
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#fff#;
ncpu : integer := 1;
cmask : integer := 16#0001#;
clkfact : integer := 2
);
port (
rst : in std_ulogic;
hclk : in std_ulogic;
cpuclk : in std_ulogic;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
irqi : in irq_out_vector(0 to ncpu-1);
irqo : out irq_in_vector(0 to ncpu-1);
hclken : in std_ulogic
);
end component;
component leon3ftsh
generic (
hindex : integer := 0;
fabtech : integer range 0 to NTECH := DEFFABTECH;
memtech : integer range 0 to NTECH := DEFMEMTECH;
nwindows : integer range 2 to 32 := 8;
dsu : integer range 0 to 1 := 0;
fpu : integer range 0 to 31 := 0;
v8 : integer range 0 to 63 := 0;
cp : integer range 0 to 1 := 0;
mac : integer range 0 to 1 := 0;
pclow : integer range 0 to 2 := 2;
notag : integer range 0 to 1 := 0;
nwp : integer range 0 to 4 := 0;
icen : integer range 0 to 1 := 0;
irepl : integer range 0 to 2 := 2;
isets : integer range 1 to 4 := 1;
ilinesize : integer range 4 to 8 := 4;
isetsize : integer range 1 to 256 := 1;
isetlock : integer range 0 to 1 := 0;
dcen : integer range 0 to 1 := 0;
drepl : integer range 0 to 2 := 2;
dsets : integer range 1 to 4 := 1;
dlinesize : integer range 4 to 8 := 4;
dsetsize : integer range 1 to 256 := 1;
dsetlock : integer range 0 to 1 := 0;
dsnoop : integer range 0 to 6 := 0;
ilram : integer range 0 to 1 := 0;
ilramsize : integer range 1 to 512 := 1;
ilramstart : integer range 0 to 255 := 16#8e#;
dlram : integer range 0 to 1 := 0;
dlramsize : integer range 1 to 512 := 1;
dlramstart : integer range 0 to 255 := 16#8f#;
mmuen : integer range 0 to 1 := 0;
itlbnum : integer range 2 to 64 := 8;
dtlbnum : integer range 2 to 64 := 8;
tlb_type : integer range 0 to 3 := 1;
tlb_rep : integer range 0 to 1 := 0;
lddel : integer range 1 to 2 := 2;
disas : integer range 0 to 2 := 0;
tbuf : integer range 0 to 64 := 0;
pwd : integer range 0 to 2 := 2; -- power-down
svt : integer range 0 to 1 := 1; -- single vector trapping
rstaddr : integer := 0;
smp : integer range 0 to 15 := 0; -- support SMP systems
iuft : integer range 0 to 4 := 0;
fpft : integer range 0 to 4 := 0;
cmft : integer range 0 to 1 := 0;
iuinj : integer := 0;
ceinj : integer range 0 to 3 := 0;
cached : integer := 0;
netlist : integer := 0;
scantest : integer := 0
);
port (
clk : in std_ulogic; -- free-running clock
rstn : in std_ulogic;
ahbi : in ahb_mst_in_type;
ahbo : out ahb_mst_out_type;
ahbsi : in ahb_slv_in_type;
ahbso : in ahb_slv_out_vector;
irqi : in l3_irq_in_type;
irqo : out l3_irq_out_type;
dbgi : in l3_debug_in_type;
dbgo : out l3_debug_out_type;
gclk : in std_ulogic; -- gated clock
fpui : out grfpu_in_type;
fpuo : in grfpu_out_type
);
end component;
end;
| mit | 6af2db195fe4d3ba6c1d4cec54e58202 | 0.526756 | 3.542099 | false | false | false | false |
michaelfivez/ascon_hardware_implementation | ascon12864_unrolled6/API_plus_CipherCore/aux_fifo.vhd | 9 | 6,213 | -------------------------------------------------------------------------------
--! @file aux_fifo.vhd
--! @brief Auxiliary FIFO. A custom FIFO used for GMU CAESAR project.
--! @project CAESAR Candidate Evaluation
--! @author Ekawat (ice) Homsirikamol
--! @copyright Copyright (c) 2015 Cryptographic Engineering Research Group
--! ECE Department, George Mason University Fairfax, VA, U.S.A.
--! All rights Reserved.
--! @license This project is released under the GNU Public License.
--! The license and distribution terms for this file may be
--! found in the file LICENSE in this distribution or at
--! http://www.gnu.org/licenses/gpl-3.0.txt
--! @note This is publicly available encryption source code that falls
--! under the License Exception TSU (Technology and software-
--! —unrestricted)
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity aux_fifo is
generic (
G_W : integer := 32;
G_LOG2DEPTH : integer := 6
);
port (
clk : in std_logic;
rst : in std_logic;
fifo_din : in std_logic_vector(G_W-1 downto 0);
fifo_dout : out std_logic_vector(G_W-1 downto 0);
fifo_ctrl_in : in std_logic_vector(3 downto 0);
fifo_ctrl_out : out std_logic_vector(2 downto 0)
);
end entity aux_fifo;
architecture structure of aux_fifo is
signal readpointer : std_logic_vector(G_LOG2DEPTH -1 downto 0);
signal writepointer : std_logic_vector(G_LOG2DEPTH -1 downto 0);
signal save_writepointer : std_logic_vector(G_LOG2DEPTH -1 downto 0);
signal bytecounter : std_logic_vector(G_LOG2DEPTH downto 0);
signal last_bytecounter : std_logic_vector(G_LOG2DEPTH downto 0); --! Byte counter of unread data
signal last_bytecounter_in : std_logic_vector(G_LOG2DEPTH downto 0); --! Byte counter of unread data
signal fifo_save_state : std_logic;
signal fifo_restore_state : std_logic;
signal fifo_write : std_logic;
signal fifo_read : std_logic;
signal fifo_unread_avail : std_logic;
signal fifo_empty : std_logic;
signal fifo_full : std_logic;
type t_mem is array (0 to 2**G_LOG2DEPTH-1) of std_logic_vector(G_W-1 downto 0);
signal memory : t_mem;
begin
fifo_ctrl_out <= fifo_full & fifo_empty & fifo_unread_avail;
fifo_save_state <= fifo_ctrl_in (0);
fifo_restore_state <= fifo_ctrl_in (1);
fifo_write <= fifo_ctrl_in (2);
fifo_read <= fifo_ctrl_in (3);
uDPRAM:
process(clk)
begin
if (rising_edge(clk)) then
if (fifo_write = '1') then
memory(to_integer(unsigned(writepointer))) <= fifo_din;
end if;
if (fifo_read = '1') then
fifo_dout <= memory(to_integer(unsigned(readpointer)));
end if;
end if;
end process;
p_fifo_ptr:
process(clk)
begin
if rising_edge( clk ) then
if rst = '1' then
readpointer <= (others => '0');
writepointer <= (others => '0');
bytecounter <= (others => '0'); --differences (write pointer - read pointer)
save_writepointer <= (others => '0');
else
if (fifo_save_state = '1') then
save_writepointer <= std_logic_vector(unsigned(readpointer) + unsigned(bytecounter(G_LOG2DEPTH-1 downto 0)));
last_bytecounter <= bytecounter;
end if;
if (fifo_write = '1' and fifo_read = '1') then
writepointer <= std_logic_vector(unsigned(writepointer) + 1);
readpointer <= std_logic_vector(unsigned(readpointer) + 1);
if (unsigned(last_bytecounter) /= 0) then
last_bytecounter <= std_logic_vector(unsigned(last_bytecounter_in) - 1);
end if;
elsif (fifo_write = '1' and fifo_read = '0') then
writepointer <= std_logic_vector(unsigned(writepointer) + 1);
bytecounter <= std_logic_vector(unsigned(bytecounter) + 1);
elsif (fifo_write = '0' and fifo_read = '1') then
readpointer <= std_logic_vector(unsigned(readpointer) + 1);
if (fifo_restore_state = '1') then
writepointer <= save_writepointer;
bytecounter <= '0' & std_logic_vector(unsigned(save_writepointer) - (unsigned(readpointer) - 1));
else
bytecounter <= std_logic_vector(unsigned(bytecounter) - 1);
end if;
if (unsigned(last_bytecounter) /= 0) then
last_bytecounter <= std_logic_vector(unsigned(last_bytecounter_in) - 1);
end if;
elsif (fifo_restore_state = '1') then
writepointer <= save_writepointer;
bytecounter <= '0' & std_logic_vector(unsigned(save_writepointer) - unsigned(readpointer));
end if;
end if;
end if;
end process;
last_bytecounter_in <= bytecounter when fifo_save_state = '1' else last_bytecounter;
fifo_unread_avail <= '1' when unsigned(last_bytecounter) > 0 else '0';
-- fifo_empty <= '1' when (unsigned(bytecounter) = 0 or (fifo_read = '1' and unsigned(bytecounter) = 1)) else '0';
fifo_empty <= '1' when (unsigned(bytecounter) = 0) else '0';
fifo_full <= '1' when (unsigned(bytecounter) >= 2**G_LOG2DEPTH-1) else '0';
end structure; | gpl-3.0 | fce85a9841bc83aa214a0cc86cb841c5 | 0.513122 | 3.989082 | false | false | false | false |
cafe-alpha/wascafe | v13/r07c_de10_20201014_abus4/wasca/synthesis/submodules/sega_saturn_abus_slave.vhd | 3 | 26,193 | -- sega_saturn_abus_slave.vhd
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity sega_saturn_abus_slave is
port (
clock : in std_logic := '0'; -- clock.clk
abus_address : in std_logic_vector(9 downto 0) := (others => '0'); -- abus.address
abus_addressdata : inout std_logic_vector(15 downto 0) := (others => '0'); -- abus.addressdata
abus_chipselect : in std_logic_vector(2 downto 0) := (others => '0'); -- .chipselect
abus_read : in std_logic := '0'; -- .read
abus_write : in std_logic_vector(1 downto 0) := (others => '0'); -- .write
--abus_functioncode : in std_logic_vector(1 downto 0) := (others => '0'); -- .functioncode
--abus_timing : in std_logic_vector(2 downto 0) := (others => '0'); -- .timing
abus_waitrequest : out std_logic := '1'; -- .waitrequest
--abus_addressstrobe : in std_logic := '0'; -- .addressstrobe
abus_interrupt : out std_logic := '0'; -- .interrupt
abus_direction : out std_logic := '0'; -- .direction
abus_muxing : out std_logic_vector(1 downto 0) := "01"; -- .muxing
abus_disable_out : out std_logic := '0'; -- .disableout
avalon_read : out std_logic; -- avalon_master.read
avalon_write : out std_logic; -- .write
avalon_waitrequest : in std_logic := '0'; -- .waitrequest
avalon_address : out std_logic_vector(27 downto 0); -- .address
avalon_readdata : in std_logic_vector(15 downto 0) := (others => '0'); -- .readdata
avalon_writedata : out std_logic_vector(15 downto 0); -- .writedata
avalon_burstcount : out std_logic; -- .burstcount
avalon_readdatavalid : in std_logic := '0'; -- .readdatavalid
avalon_nios_read : in std_logic := '0'; -- avalon_master.read
avalon_nios_write : in std_logic := '0'; -- .write
avalon_nios_waitrequest : out std_logic := '0'; -- .waitrequest
avalon_nios_address : in std_logic_vector(7 downto 0) := (others => '0'); -- .address
avalon_nios_writedata : in std_logic_vector(15 downto 0) := (others => '0'); -- .writedata
avalon_nios_burstcount : in std_logic; -- .burstcount
avalon_nios_readdata : out std_logic_vector(15 downto 0) := (others => '0'); -- .readdata
avalon_nios_readdatavalid : out std_logic := '0'; -- .readdatavalid
saturn_reset : in std_logic := '0'; -- .saturn_reset
reset : in std_logic := '0' -- reset.reset
);
end entity sega_saturn_abus_slave;
architecture rtl of sega_saturn_abus_slave is
signal abus_address_ms : std_logic_vector(9 downto 0) := (others => '0'); -- abus.address
signal abus_address_buf : std_logic_vector(9 downto 0) := (others => '0'); -- abus.address
signal abus_addressdata_ms : std_logic_vector(15 downto 0) := (others => '0'); -- .data
signal abus_addressdata_buf : std_logic_vector(15 downto 0) := (others => '0'); -- .data
signal abus_chipselect_ms : std_logic_vector(2 downto 0) := (others => '0'); -- .chipselect
signal abus_chipselect_buf : std_logic_vector(2 downto 0) := (others => '0'); -- .chipselect
signal abus_read_ms : std_logic := '0'; -- .read
signal abus_read_buf : std_logic := '0'; -- .read
signal abus_write_ms : std_logic_vector(1 downto 0) := (others => '0'); -- .write
signal abus_write_buf : std_logic_vector(1 downto 0) := (others => '0'); -- .write
--signal abus_functioncode_ms : std_logic_vector(1 downto 0) := (others => '0'); -- .functioncode
--signal abus_functioncode_buf : std_logic_vector(1 downto 0) := (others => '0'); -- .functioncode
--signal abus_timing_ms : std_logic_vector(2 downto 0) := (others => '0'); -- .timing
--signal abus_timing_buf : std_logic_vector(2 downto 0) := (others => '0'); -- .timing
--signal abus_addressstrobe_ms : std_logic := '0'; -- .addressstrobe
--signal abus_addressstrobe_buf : std_logic := '0'; -- .addressstrobe
signal abus_read_buf2 : std_logic := '0'; -- .read
signal abus_read_buf3 : std_logic := '0'; -- .read
signal abus_read_buf4 : std_logic := '0'; -- .read
signal abus_read_buf5 : std_logic := '0'; -- .read
signal abus_read_buf6 : std_logic := '0'; -- .read
signal abus_read_buf7 : std_logic := '0'; -- .read
signal abus_write_buf2 : std_logic_vector(1 downto 0) := (others => '0'); -- .write
signal abus_chipselect_buf2 : std_logic_vector(2 downto 0) := (others => '0'); -- .chipselect
signal abus_read_pulse : std_logic := '0'; -- .read
signal abus_write_pulse : std_logic_vector(1 downto 0) := (others => '0'); -- .write
signal abus_chipselect_pulse : std_logic_vector(2 downto 0) := (others => '0'); -- .chipselect
signal abus_read_pulse_off : std_logic := '0'; -- .read
signal abus_write_pulse_off : std_logic_vector(1 downto 0) := (others => '0'); -- .write
signal abus_chipselect_pulse_off : std_logic_vector(2 downto 0) := (others => '0'); -- .chipselect
signal abus_anypulse : std_logic := '0';
signal abus_anypulse2 : std_logic := '0';
signal abus_anypulse3 : std_logic := '0';
signal abus_anypulse_off : std_logic := '0';
signal abus_cspulse : std_logic := '0';
signal abus_cspulse2 : std_logic := '0';
signal abus_cspulse3 : std_logic := '0';
signal abus_cspulse4 : std_logic := '0';
signal abus_cspulse5 : std_logic := '0';
signal abus_cspulse6 : std_logic := '0';
signal abus_cspulse7 : std_logic := '0';
signal abus_cspulse_off : std_logic := '0';
signal abus_address_latched : std_logic_vector(25 downto 0) := (others => '0'); -- abus.address
signal abus_chipselect_latched : std_logic_vector(1 downto 0) := (others => '1'); -- abus.address
signal abus_direction_internal : std_logic := '0';
signal abus_muxing_internal : std_logic_vector(1 downto 0) := (others => '0'); -- abus.address
signal abus_data_out : std_logic_vector(15 downto 0) := (others => '0');
signal abus_data_in : std_logic_vector(15 downto 0) := (others => '0');
signal abus_waitrequest_read : std_logic := '0';
signal abus_waitrequest_write : std_logic := '0';
signal abus_waitrequest_read2 : std_logic := '0';
signal abus_waitrequest_write2 : std_logic := '0';
--signal abus_waitrequest_read3 : std_logic := '0';
--signal abus_waitrequest_write3 : std_logic := '0';
--signal abus_waitrequest_read4 : std_logic := '0';
--signal abus_waitrequest_write4 : std_logic := '0';
signal abus_waitrequest_read_off : std_logic := '0';
signal abus_waitrequest_write_off : std_logic := '0';
signal REG_PCNTR : std_logic_vector(15 downto 0) := (others => '0');
signal REG_STATUS : std_logic_vector(15 downto 0) := (others => '0');
signal REG_MODE : std_logic_vector(15 downto 0) := (others => '0');
signal REG_HWVER : std_logic_vector(15 downto 0) := X"0002";
signal REG_SWVER : std_logic_vector(15 downto 0) := (others => '0');
TYPE transaction_dir IS (DIR_NONE,DIR_WRITE,DIR_READ);
SIGNAL my_little_transaction_dir : transaction_dir := DIR_NONE;
TYPE wasca_mode_type IS (MODE_INIT,
MODE_POWER_MEMORY_05M, MODE_POWER_MEMORY_1M, MODE_POWER_MEMORY_2M, MODE_POWER_MEMORY_4M,
MODE_RAM_1M, MODE_RAM_4M,
MODE_ROM_KOF95,
MODE_ROM_ULTRAMAN,
MODE_BOOT);
SIGNAL wasca_mode : wasca_mode_type := MODE_INIT;
begin
abus_direction <= abus_direction_internal;
abus_muxing <= not abus_muxing_internal;
--ignoring functioncode, timing and addressstrobe for now
--abus transactions are async, so first we must latch incoming signals
--to get rid of metastability
process (clock)
begin
if rising_edge(clock) then
--1st stage
abus_address_ms <= abus_address;
abus_addressdata_ms <= abus_addressdata;
abus_chipselect_ms <= abus_chipselect; --work only with CS1 for now
abus_read_ms <= abus_read;
abus_write_ms <= abus_write;
--abus_functioncode_ms <= abus_functioncode;
--abus_timing_ms <= abus_timing;
--abus_addressstrobe_ms <= abus_addressstrobe;
--2nd stage
abus_address_buf <= abus_address_ms;
abus_addressdata_buf <= abus_addressdata_ms;
abus_chipselect_buf <= abus_chipselect_ms;
abus_read_buf <= abus_read_ms;
abus_write_buf <= abus_write_ms;
--abus_functioncode_buf <= abus_functioncode_ms;
--abus_timing_buf <= abus_timing_ms;
--abus_addressstrobe_buf <= abus_addressstrobe_ms;
end if;
end process;
--excluding metastability protection is a bad behavior
--but it lloks like we're out of more options to optimize read pipeline
--abus_read_ms <= abus_read;
--abus_read_buf <= abus_read_ms;
--abus read/write latch
process (clock)
begin
if rising_edge(clock) then
abus_write_buf2 <= abus_write_buf;
abus_read_buf2 <= abus_read_buf;
abus_read_buf3 <= abus_read_buf2;
abus_read_buf4 <= abus_read_buf3;
abus_read_buf5 <= abus_read_buf4;
abus_read_buf6 <= abus_read_buf5;
abus_read_buf7 <= abus_read_buf6;
abus_chipselect_buf2 <= abus_chipselect_buf;
abus_anypulse2 <= abus_anypulse;
abus_anypulse3 <= abus_anypulse2;
abus_cspulse2 <= abus_cspulse;
abus_cspulse3 <= abus_cspulse2;
abus_cspulse4 <= abus_cspulse3;
abus_cspulse5 <= abus_cspulse4;
abus_cspulse6 <= abus_cspulse5;
abus_cspulse7 <= abus_cspulse6;
end if;
end process;
--abus write/read pulse is a falling edge since read and write signals are negative polarity
abus_write_pulse <= abus_write_buf2 and not abus_write_buf;
abus_read_pulse <= abus_read_buf2 and not abus_read_buf;
--abus_chipselect_pulse <= abus_chipselect_buf2 and not abus_chipselect_buf;
abus_chipselect_pulse <= abus_chipselect_buf and not abus_chipselect_ms;
abus_write_pulse_off <= abus_write_buf and not abus_write_buf2;
abus_read_pulse_off <= abus_read_buf and not abus_read_buf2;
abus_chipselect_pulse_off <= abus_chipselect_buf and not abus_chipselect_buf2;
abus_anypulse <= abus_write_pulse(0) or abus_write_pulse(1) or abus_read_pulse or
abus_chipselect_pulse(0) or abus_chipselect_pulse(1) or abus_chipselect_pulse(2);
abus_anypulse_off <= abus_write_pulse_off(0) or abus_write_pulse_off(1) or abus_read_pulse_off or
abus_chipselect_pulse_off(0) or abus_chipselect_pulse_off(1) or abus_chipselect_pulse_off(2);
abus_cspulse <= abus_chipselect_pulse(0) or abus_chipselect_pulse(1) or abus_chipselect_pulse(2);
abus_cspulse_off <= abus_chipselect_pulse_off(0) or abus_chipselect_pulse_off(1) or abus_chipselect_pulse_off(2);
--whatever pulse we've got, latch address
--it might be latched twice per transaction, but it's not a problem
--multiplexer was switched to address after previous transaction or after boot,
--so we have address ready to latch
process (clock)
begin
if rising_edge(clock) then
if abus_anypulse = '1' then
--if abus_read_pulse = '1' or abus_write_pulse(0) = '1' or abus_write_pulse(1)='1' then
--abus_address_latched <= abus_address & abus_addressdata_buf(0) & abus_addressdata_buf(12) & abus_addressdata_buf(2) & abus_addressdata_buf(1)
-- & abus_addressdata_buf(9) & abus_addressdata_buf(10) & abus_addressdata_buf(8) & abus_addressdata_buf(3)
-- & abus_addressdata_buf(13) & abus_addressdata_buf(14) & abus_addressdata_buf(15) & abus_addressdata_buf(4)
-- & abus_addressdata_buf(5) & abus_addressdata_buf(6) & abus_addressdata_buf(11) & abus_addressdata_buf(7);
abus_address_latched <= abus_address & abus_addressdata_buf(11) & abus_addressdata_buf(12) & abus_addressdata_buf(9) & abus_addressdata_buf(10)
& abus_addressdata_buf(2) & abus_addressdata_buf(1) & abus_addressdata_buf(3) & abus_addressdata_buf(8)
& abus_addressdata_buf(13) & abus_addressdata_buf(14) & abus_addressdata_buf(15) & abus_addressdata_buf(4)
& abus_addressdata_buf(5) & abus_addressdata_buf(6) & abus_addressdata_buf(0) & abus_addressdata_buf(7);
end if;
end if;
end process;
--latch transaction direction
process (clock)
begin
if rising_edge(clock) then
if abus_write_pulse(0) = '1' or abus_write_pulse(1) = '1' then
my_little_transaction_dir <= DIR_WRITE;
elsif abus_read_pulse = '1' then
my_little_transaction_dir <= DIR_READ;
elsif abus_anypulse_off = '1' and abus_cspulse_off = '0' then --ending anything but not cs
my_little_transaction_dir <= DIR_NONE;
end if;
end if;
end process;
--latch chipselect number
process (clock)
begin
if rising_edge(clock) then
if abus_chipselect_pulse(0) = '1' then
abus_chipselect_latched <= "00";
elsif abus_chipselect_pulse(1) = '1' then
abus_chipselect_latched <= "01";
elsif abus_chipselect_pulse(2) = '1' then
abus_chipselect_latched <= "10";
elsif abus_cspulse_off = '1' then
abus_chipselect_latched <= "11";
end if;
end if;
end process;
--if valid transaction captured, switch to corresponding multiplex mode
process (clock)
begin
if rising_edge(clock) then
if abus_chipselect_latched = "11" then
--chipselect deasserted
abus_direction_internal <= '0'; --high-z
abus_muxing_internal <= "01"; --address
else
--chipselect asserted
case (my_little_transaction_dir) is
when DIR_NONE =>
abus_direction_internal <= '0'; --high-z
abus_muxing_internal <= "10"; --data
when DIR_READ =>
abus_direction_internal <= '1'; --active
abus_muxing_internal <= "10"; --data
when DIR_WRITE =>
abus_direction_internal <= '0'; --high-z
abus_muxing_internal <= "10"; --data
end case;
end if;
end if;
end process;
abus_disable_out <= '1' when abus_chipselect_latched(1) = '1' else
'0';
--if abus read access is detected, issue avalon read transaction
--wait until readdatavalid, then disable read and abus wait
process (clock)
begin
if rising_edge(clock) then
--if my_little_transaction_dir = DIR_READ and abus_chipselect_latched(1) = '0' and abus_anypulse2 = '1' then
--starting read transaction at either RD pulse or (CS pulse while RD is on)
--but if CS arrives less than 7 clocks after RD, then we ignore this CS
--this will get us 2 additional clocks at read pipeline
if abus_read_pulse = '1' or (abus_cspulse='1' and abus_read_buf = '0' and abus_read_buf7 = '0') then
avalon_read <= '1';
abus_waitrequest_read <= '1';
elsif avalon_readdatavalid = '1' then
avalon_read <= '0';
abus_waitrequest_read <= '0';
if abus_chipselect_latched = "00" then
--CS0 access
if abus_address_latched(24 downto 0) = "1"&X"FF0FFE" then
--wasca specific SD card control register
abus_data_out <= X"CDCD";
elsif abus_address_latched(24 downto 0) = "1"&X"FFFFF0" then
--wasca prepare counter
abus_data_out <= REG_PCNTR;
elsif abus_address_latched(24 downto 0) = "1"&X"FFFFF2" then
--wasca status register
abus_data_out <= REG_STATUS;
elsif abus_address_latched(24 downto 0) = "1"&X"FFFFF4" then
--wasca mode register
abus_data_out <= REG_MODE;
elsif abus_address_latched(24 downto 0) = "1"&X"FFFFF6" then
--wasca hwver register
abus_data_out <= REG_HWVER;
elsif abus_address_latched(24 downto 0) = "1"&X"FFFFF8" then
--wasca swver register
abus_data_out <= REG_SWVER;
elsif abus_address_latched(24 downto 0) = "1"&X"FFFFFA" then
--wasca signature "wa"
abus_data_out <= X"7761";
elsif abus_address_latched(24 downto 0) = "1"&X"FFFFFC" then
--wasca signature "sc"
abus_data_out <= X"7363";
elsif abus_address_latched(24 downto 0) = "1"&X"FFFFFE" then
--wasca signature "a "
abus_data_out <= X"6120";
else
--normal CS0 read access
case wasca_mode is
when MODE_INIT => abus_data_out <= avalon_readdata(7 downto 0) & avalon_readdata (15 downto 8) ;
when MODE_POWER_MEMORY_05M => abus_data_out <= X"FFFF";
when MODE_POWER_MEMORY_1M => abus_data_out <= X"FFFF";
when MODE_POWER_MEMORY_2M => abus_data_out <= X"FFFF";
when MODE_POWER_MEMORY_4M => abus_data_out <= X"FFFF";
when MODE_RAM_1M => abus_data_out <= avalon_readdata(7 downto 0) & avalon_readdata (15 downto 8) ;
when MODE_RAM_4M => abus_data_out <= avalon_readdata(7 downto 0) & avalon_readdata (15 downto 8) ;
when MODE_ROM_KOF95 => abus_data_out <= avalon_readdata(7 downto 0) & avalon_readdata (15 downto 8) ;
when MODE_ROM_ULTRAMAN => abus_data_out <= avalon_readdata(7 downto 0) & avalon_readdata (15 downto 8) ;
when MODE_BOOT => abus_data_out <= avalon_readdata(7 downto 0) & avalon_readdata (15 downto 8) ;
end case;
end if;
elsif abus_chipselect_latched = "01" then
--CS1 access
if ( abus_address_latched(23 downto 0) = X"FFFFFE" or abus_address_latched(23 downto 0) = X"FFFFFC" ) then
--saturn cart id register
case wasca_mode is
when MODE_INIT => abus_data_out <= avalon_readdata(7 downto 0) & avalon_readdata (15 downto 8) ;
when MODE_POWER_MEMORY_05M => abus_data_out <= X"FF21";
when MODE_POWER_MEMORY_1M => abus_data_out <= X"FF22";
when MODE_POWER_MEMORY_2M => abus_data_out <= X"FF23";
when MODE_POWER_MEMORY_4M => abus_data_out <= X"FF24";
when MODE_RAM_1M => abus_data_out <= X"FF5A";
when MODE_RAM_4M => abus_data_out <= X"FF5C";
when MODE_ROM_KOF95 => abus_data_out <= X"FFFF";
when MODE_ROM_ULTRAMAN => abus_data_out <= X"FFFF";
when MODE_BOOT => abus_data_out <= X"FFFF";
end case;
else
--normal CS1 access
case wasca_mode is
when MODE_INIT => abus_data_out <= avalon_readdata(7 downto 0) & avalon_readdata (15 downto 8) ;
when MODE_POWER_MEMORY_05M => abus_data_out <= avalon_readdata(7 downto 0) & avalon_readdata (15 downto 8) ;
when MODE_POWER_MEMORY_1M => abus_data_out <= avalon_readdata(7 downto 0) & avalon_readdata (15 downto 8) ;
when MODE_POWER_MEMORY_2M => abus_data_out <= avalon_readdata(7 downto 0) & avalon_readdata (15 downto 8) ;
when MODE_POWER_MEMORY_4M => abus_data_out <= avalon_readdata(7 downto 0) & avalon_readdata (15 downto 8) ;
when MODE_RAM_1M => abus_data_out <= X"FFFF";
when MODE_RAM_4M => abus_data_out <= X"FFFF";
when MODE_ROM_KOF95 => abus_data_out <= X"FFFF";
when MODE_ROM_ULTRAMAN => abus_data_out <= X"FFFF";
when MODE_BOOT => abus_data_out <= X"FFFF";
end case;
end if;
else
--CS2 access
abus_data_out <= X"EEEE";
end if;
end if;
end if;
end process;
--if abus write access is detected, issue avalon write transaction
--disable abus wait immediately
--TODO: check if avalon_writedata is already valid at this moment
process (clock)
begin
if rising_edge(clock) then
if my_little_transaction_dir = DIR_WRITE and abus_chipselect_latched /= "11" and abus_cspulse7 = '1' then
--pass write to avalon
avalon_write <= '1';
abus_waitrequest_write <= '1';
elsif avalon_waitrequest = '0' then
avalon_write <= '0';
abus_waitrequest_write <= '0';
end if;
end if;
end process;
--wasca mode register write
--reset
process (clock)
begin
if rising_edge(clock) then
--if saturn_reset='0' then wasca_mode <= MODE_INIT;
--els
if my_little_transaction_dir = DIR_WRITE and abus_chipselect_latched = "00" and abus_cspulse7 = '1' and
abus_address_latched(23 downto 0) = X"FFFFF4" then
--wasca mode register
REG_MODE <= abus_data_in;
case (abus_data_in (3 downto 0)) is
when X"1" => wasca_mode <= MODE_POWER_MEMORY_05M;
when X"2" => wasca_mode <= MODE_POWER_MEMORY_1M;
when X"3" => wasca_mode <= MODE_POWER_MEMORY_2M;
when X"4" => wasca_mode <= MODE_POWER_MEMORY_4M;
when others =>
case (abus_data_in (7 downto 4)) is
when X"1" => wasca_mode <= MODE_RAM_1M;
when X"2" => wasca_mode <= MODE_RAM_4M;
when others =>
case (abus_data_in (11 downto 8)) is
when X"1" => wasca_mode <= MODE_ROM_KOF95;
when X"2" => wasca_mode <= MODE_ROM_ULTRAMAN;
when others => null;-- wasca_mode <= MODE_INIT;
end case;
end case;
end case;
end if;
end if;
end process;
abus_data_in <= abus_addressdata_buf;
--working only if direction is 1
abus_addressdata <= (others => 'Z') when abus_direction_internal='0' else
abus_data_out;
process (clock)
begin
if rising_edge(clock) then
abus_waitrequest_read2 <= abus_waitrequest_read;
--abus_waitrequest_read3 <= abus_waitrequest_read2;
--abus_waitrequest_read4 <= abus_waitrequest_read3;
abus_waitrequest_write2 <= abus_waitrequest_write;
--abus_waitrequest_write3 <= abus_waitrequest_write3;
--abus_waitrequest_write4 <= abus_waitrequest_write4;
end if;
end process;
process (clock)
begin
if rising_edge(clock) then
abus_waitrequest_read_off <= '0';
abus_waitrequest_write_off <= '0';
if abus_waitrequest_read = '0' and abus_waitrequest_read2 = '1' then
abus_waitrequest_read_off <= '1';
end if;
if abus_waitrequest_write = '0' and abus_waitrequest_write2 = '1' then
abus_waitrequest_write_off <= '1';
end if;
end if;
end process;
--process (clock)
--begin
-- if rising_edge(clock) then
-- --if abus_read_pulse='1' or abus_write_pulse(0)='1' or abus_write_pulse(1)='1' then
-- --if abus_anypulse = '1' then
-- if abus_chipselect_pulse(0) = '1' or abus_chipselect_pulse(1) = '1' then
-- abus_waitrequest <= '0';
-- elsif abus_waitrequest_read_off='1' or abus_waitrequest_write_off='1' then
-- abus_waitrequest <= '1';
-- end if;
-- end if;
--end process;
--avalon-to-abus mapping
--SDRAM is mapped to both CS0 and CS1
avalon_address <= "010" & abus_address_latched(24 downto 0);
avalon_writedata <= abus_data_in(7 downto 0) & abus_data_in (15 downto 8) ;
avalon_burstcount <= '0';
abus_waitrequest <= not (abus_waitrequest_read or abus_waitrequest_write);
--Nios II read interface
process (clock)
begin
if rising_edge(clock) then
avalon_nios_readdatavalid <= '0';
if avalon_nios_read = '1' then
avalon_nios_readdatavalid <= '1';
case avalon_nios_address is
when X"F0" =>
avalon_nios_readdata <= REG_PCNTR;
when X"F2" =>
avalon_nios_readdata <= REG_STATUS;
when X"F4" =>
avalon_nios_readdata <= REG_MODE;
when X"F6" =>
avalon_nios_readdata <= REG_HWVER;
when X"F8" =>
avalon_nios_readdata <= REG_SWVER;
when X"FA" =>
avalon_nios_readdata <= X"ABCD"; --for debug, remove later
when others =>
avalon_nios_readdata <= REG_HWVER; --to simplify mux
end case;
end if;
end if;
end process;
--Nios II write interface
process (clock)
begin
if rising_edge(clock) then
if avalon_nios_write= '1' then
case avalon_nios_address is
when X"F0" =>
REG_PCNTR <= avalon_nios_writedata;
when X"F2" =>
REG_STATUS <= avalon_nios_writedata;
when X"F4" =>
null;
when X"F6" =>
null;
when X"F8" =>
REG_SWVER <= avalon_nios_writedata;
when others =>
null;
end case;
end if;
end if;
end process;
--Nios system interface is only regs, so always ready to write.
avalon_nios_waitrequest <= '0';
end architecture rtl; -- of sega_saturn_abus_slave
| gpl-2.0 | 41654fe336b0df84dc0097eefe0601bb | 0.568511 | 3.358077 | false | false | false | false |
lxp32/lxp32-cpu | verify/common_pkg/common_pkg_body.vhd | 1 | 1,776 | ---------------------------------------------------------------------
-- Common package for LXP32 testbenches
--
-- Part of the LXP32 verification environment
--
-- Copyright (c) 2016 by Alex I. Kuznetsov
---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
package body common_pkg is
procedure rand(variable st: inout rng_state_type; a,b: integer; variable x: out integer) is
variable r: real;
begin
assert a<=b report "Invalid range" severity failure;
uniform(st.seed1,st.seed2,r);
r:=r*real(b-a+1);
x:=a+integer(floor(r));
end procedure;
function hex_string(x: std_logic_vector) return string is
variable xx: std_logic_vector(x'length-1 downto 0);
variable i: integer:=0;
variable ii: integer;
variable c: integer;
variable high_index: integer;
variable s: string(x'length downto 1);
begin
xx:=x;
loop
ii:=i*4;
exit when ii>xx'high;
if ii+3<=xx'high then
high_index:=ii+3;
else
high_index:=xx'high;
end if;
if is_x(xx(high_index downto ii)) then
c:=-1;
else
c:=to_integer(unsigned(xx(high_index downto ii)));
end if;
case c is
when 0 => s(i+1):='0';
when 1 => s(i+1):='1';
when 2 => s(i+1):='2';
when 3 => s(i+1):='3';
when 4 => s(i+1):='4';
when 5 => s(i+1):='5';
when 6 => s(i+1):='6';
when 7 => s(i+1):='7';
when 8 => s(i+1):='8';
when 9 => s(i+1):='9';
when 10 => s(i+1):='A';
when 11 => s(i+1):='B';
when 12 => s(i+1):='C';
when 13 => s(i+1):='D';
when 14 => s(i+1):='E';
when 15 => s(i+1):='F';
when others => s(i+1):='X';
end case;
i:=i+1;
end loop;
return s(i downto 1);
end function;
end package body;
| mit | dd3068e070b87c9793e7554eaeb7e619 | 0.537162 | 2.740741 | false | false | false | false |
amerc/phimii | testing_ethernet.vhd | 2 | 41,407 | --------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 18:48:07 05/19/2014
-- Design Name:
-- Module Name: /home/amer/Nexys3/TCP/testing_ethernet.vhd
-- Project Name: TCP
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: ethernet
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY testing_ethernet IS
END testing_ethernet;
ARCHITECTURE behavior OF testing_ethernet IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT ethernet
PORT(
CLK : IN std_logic;
RST : IN std_logic;
TXCLK : IN std_logic;
TXER : OUT std_logic;
TXEN : OUT std_logic;
TXD : OUT std_logic_vector(3 downto 0);
PHY_RESET : OUT std_logic;
RXCLK : IN std_logic;
RXER : IN std_logic;
RXDV : IN std_logic;
RXD : IN std_logic_vector(3 downto 0);
COL : IN std_logic;
TX : IN std_logic_vector(15 downto 0);
TX_STB : IN std_logic;
TX_ACK : OUT std_logic;
RX : OUT std_logic_vector(15 downto 0);
RX_STB : OUT std_logic;
RX_ACK : IN std_logic;
PhyCRS : in std_logic;
BtnL : in std_logic
);
END COMPONENT;
--Inputs
signal CLK : std_logic := '0';
signal RST : std_logic := '0';
signal TXCLK : std_logic := '0';
signal RXCLK : std_logic := '0';
signal RXER : std_logic := '0';
signal RXDV : std_logic := '0';
signal RXD : std_logic_vector(3 downto 0) := (others => '0');
signal COL : std_logic := '0';
signal TX : std_logic_vector(15 downto 0) := (others => '0');
signal TX_STB : std_logic := '0';
signal RX_ACK : std_logic := '0';
--Outputs
signal TXER : std_logic;
signal TXEN : std_logic;
signal TXD : std_logic_vector(3 downto 0);
signal PHY_RESET : std_logic;
signal TX_ACK : std_logic;
signal RX : std_logic_vector(15 downto 0);
signal RX_STB : std_logic;
signal PhyCRS : std_logic;
signal btnL : std_logic;
-- Clock period definitions
constant CLK_period : time := 20 ns;
constant TXCLK_period : time := 40 ns;
constant RXCLK_period : time := 40 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: ethernet PORT MAP (
CLK => CLK,
RST => RST,
TXCLK => TXCLK,
TXER => TXER,
TXEN => TXEN,
TXD => TXD,
PHY_RESET => PHY_RESET,
RXCLK => RXCLK,
RXER => RXER,
RXDV => RXDV,
RXD => RXD,
COL => COL,
TX => TX,
TX_STB => TX_STB,
TX_ACK => TX_ACK,
RX => RX,
RX_STB => RX_STB,
PhyCRS => PhyCRS,
BtnL => BtnL,
RX_ACK => RX_ACK
);
-- Clock process definitions
CLK_process :process
begin
CLK <= '0';
wait for CLK_period/2;
CLK <= '1';
wait for CLK_period/2;
end process;
TXCLK_process :process
begin
TXCLK <= '0';
wait for TXCLK_period/2;
TXCLK <= '1';
wait for TXCLK_period/2;
end process;
RXCLK_process :process
begin
RXCLK <= '0';
wait for RXCLK_period/2;
RXCLK <= '1';
wait for RXCLK_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
wait for 40 ms;
-- insert stimulus here
wait for 10 ns;
RST <= '0' ;
RXER <= '0' ;
RXDV <= '1' ;
RXD <= x"5" ;
COL <= '0' ;
TX <= x"3263" ;
TX_STB <= '0' ;
RX_ACK <= '0' ; --1
wait for 10 ns;
RST <= '0' ;
RXER <= '0' ;
RXDV <= '1' ;
RXD <= x"5" ;
COL <= '0' ;
TX <= x"ad63" ;
TX_STB <= '0' ;
RX_ACK <= '0' ; --2
wait for 10 ns;
RST <= '0' ;
RXER <= '0' ;
RXDV <= '1' ;
RXD <= x"5" ;
COL <= '0' ;
TX <= x"3263" ;
TX_STB <= '0' ;
RX_ACK <= '0' ; --3
wait for 10 ns;
RST <= '0' ;
RXER <= '0' ;
RXDV <= '1' ;
RXD <= x"5" ;
COL <= '0' ;
TX <= x"3263" ;
TX_STB <= '0' ;
RX_ACK <= '0' ; --4
wait for 10 ns;
RST <= '0' ;
RXER <= '0' ;
RXDV <= '1' ;
RXD <= x"5" ;
COL <= '0' ;
TX <= x"3263" ;
TX_STB <= '0' ;
RX_ACK <= '0' ; --5
wait for 10 ns;
RST <= '0' ;
RXER <= '0' ;
RXDV <= '1' ;
RXD <= x"5" ;
COL <= '0' ;
TX <= x"3263" ;
TX_STB <= '0' ;
RX_ACK <= '0' ; --6
wait for 10 ns;
RST <= '0' ;
RXER <= '0' ;
RXDV <= '1' ;
RXD <= x"5" ;
COL <= '0' ;
TX <= x"3263" ;
TX_STB <= '0' ;
RX_ACK <= '0' ; --7
wait for 10 ns;
RST <= '0' ;
RXER <= '0' ;
RXDV <= '1' ;
RXD <= x"5" ;
COL <= '0' ;
TX <= x"3263" ;
TX_STB <= '0' ;
RX_ACK <= '0' ; --8
wait for 10 ns;
RST <= '0' ;
RXER <= '0' ;
RXDV <= '1' ;
RXD <= x"5" ;
COL <= '0' ;
TX <= x"3263" ;
TX_STB <= '0' ;
RX_ACK <= '0' ;--9
wait for 10 ns;
RST <= '0' ;
RXER <= '0' ;
RXDV <= '1' ;
RXD <= x"5" ;
COL <= '0' ;
TX <= x"3263" ; --10
TX_STB <= '0' ;
RX_ACK <= '0' ;
wait for 10 ns;
RST <= '0' ;
RXER <= '0' ;
RXDV <= '1' ;
RXD <= x"5" ;
COL <= '0' ;
TX <= x"3263" ;
TX_STB <= '0' ;
RX_ACK <= '0' ; --11
wait for 10 ns;
RST <= '0' ;
RXER <= '0' ;
RXDV <= '1' ;
RXD <= x"5" ;
COL <= '0' ;
TX <= x"3263" ;
TX_STB <= '0' ;
RX_ACK <= '0' ; --12
wait for 10 ns;
RST <= '0' ;
RXER <= '0' ;
RXDV <= '1' ;
RXD <= x"5" ;
COL <= '0' ;
TX <= x"3263" ;
TX_STB <= '0' ;
RX_ACK <= '0' ; --13
wait for 10 ns;
RST <= '0' ;
RXER <= '0' ;
RXDV <= '1' ;
RXD <= x"5" ;
COL <= '0' ;
TX <= x"3263" ;
TX_STB <= '0' ;
RX_ACK <= '0' ; --14
wait for 10 ns;
RST <= '0' ;
RXER <= '0' ;
RXDV <= '1' ;
RXD <= x"D" ;
COL <= '0' ;
TX <= x"3263" ;
TX_STB <= '0' ;
RX_ACK <= '0' ; --15
wait for 10 ns; --------------------------- Data
--00-
RST <= '0' ;
RXER <= '0' ;
RXDV <= '1' ;
RXD <= x"0" ;
COL <= '0' ;
TX <= x"3263" ;
TX_STB <= '0' ;
RX_ACK <= '0' ; --00
wait for 10 ns;
RST <= '0' ;
RXER <= '0' ;
RXDV <= '1' ;
RXD <= x"0" ;
COL <= '0' ;
TX <= x"3263" ;
TX_STB <= '0' ;
RX_ACK <= '0' ; --8 -------------
-- 01 02 03 04 05 00 18 f3 52 f1 30 08 06 00 01
--08
wait for 10 ns;
RST <= '0' ;
RXER <= '0' ;
RXDV <= '1' ;
RXD <= x"8" ;
COL <= '0' ;
TX <= x"3263" ;
TX_STB <= '0' ;
RX_ACK <= '0' ; --01
wait for 10 ns;
RST <= '0' ;
RXER <= '0' ;
RXDV <= '1' ;
RXD <= x"2" ;
COL <= '0' ;
TX <= x"3263" ;
TX_STB <= '0' ;
RX_ACK <= '0' ; --5
--00
wait for 10 ns;
RST <= '0' ;
RXER <= '0' ;
RXDV <= '1' ;
RXD <= x"0" ;
COL <= '0' ;
TX <= x"3263" ;
TX_STB <= '0' ;
RX_ACK <= '0' ; -- 02
wait for 10 ns;
RST <= '0' ;
RXER <= '0' ;
RXDV <= '1' ;
RXD <= x"0" ;
COL <= '0' ;
TX <= x"3263" ;
TX_STB <= '0' ;
RX_ACK <= '0' ; --6
--06
wait for 10 ns;
RST <= '0' ;
RXER <= '0' ;
RXDV <= '1' ;
RXD <= x"6" ;
COL <= '0' ;
TX <= x"3263" ;
TX_STB <= '0' ;
RX_ACK <= '0' ; ---03
wait for 10 ns;
RST <= '0' ;
RXER <= '0' ;
RXDV <= '1' ;
RXD <= x"0" ;
COL <= '0' ;
TX <= x"3263" ;
TX_STB <= '0' ;
RX_ACK <= '0' ; --7
--04
wait for 10 ns;
RST <= '0' ;
RXER <= '0' ;
RXDV <= '1' ;
RXD <= x"4" ;
COL <= '0' ;
TX <= x"3263" ;
TX_STB <= '0' ;
RX_ACK <= '0' ; --04
wait for 10 ns;
RST <= '0' ;
RXER <= '0' ;
RXDV <= '1' ;
RXD <= x"0" ;
COL <= '0' ;
TX <= x"3263" ;
TX_STB <= '0' ;
RX_ACK <= '0' ; --8
--00
wait for 10 ns;
RST <= '0' ;
RXER <= '0' ;
RXDV <= '1' ;
RXD <= x"0" ;
COL <= '0' ;
TX <= x"3263" ;
TX_STB <= '0' ;
RX_ACK <= '0' ; --05
wait for 10 ns;
RST <= '0' ;
RXER <= '0' ;
RXDV <= '1' ;
RXD <= x"0" ;
COL <= '0' ;
TX <= x"3263" ;
TX_STB <= '0' ;
RX_ACK <= '0' ;
--01
wait for 10 ns;
RST <= '0' ;
RXER <= '0' ;
RXDV <= '1' ;
RXD <= x"1" ;
COL <= '0' ;
TX <= x"3263" ;
TX_STB <= '0' ;
RX_ACK <= '0' ; --00
wait for 10 ns;
RST <= '0' ;
RXER <= '0' ;
RXDV <= '1' ;
RXD <= x"0" ;
COL <= '0' ;
TX <= x"3263" ;
TX_STB <= '0' ;
RX_ACK <= '0' ;
--00
wait for 10 ns;
RST <= '0' ;
RXER <= '0' ;
RXDV <= '1' ;
RXD <= x"0" ;
COL <= '0' ;
TX <= x"3263" ;
TX_STB <= '0' ;
RX_ACK <= '0' ; --18
wait for 10 ns;
RST <= '0' ;
RXER <= '0' ;
RXDV <= '1' ;
RXD <= x"0" ;
COL <= '0' ;
TX <= x"3263" ;
TX_STB <= '0' ;
RX_ACK <= '0' ;
--18
wait for 10 ns;
RST <= '0' ;
RXER <= '0' ;
RXDV <= '1' ;
RXD <= x"8" ;
COL <= '0' ;
TX <= x"3263" ;
TX_STB <= '0' ;
RX_ACK <= '0' ; --f3
wait for 10 ns;
RST <= '0' ;
RXER <= '0' ;
RXDV <= '1' ;
RXD <= x"1" ;
COL <= '0' ;
TX <= x"3263" ;
TX_STB <= '0' ;
RX_ACK <= '0' ;
--f3
wait for 10 ns;
RST <= '0' ;
RXER <= '0' ;
RXDV <= '1' ;
RXD <= x"3" ;
COL <= '0' ;
TX <= x"3263" ;
TX_STB <= '0' ;
RX_ACK <= '0' ; --52
wait for 10 ns;
RST <= '0' ;
RXER <= '0' ;
RXDV <= '1' ;
RXD <= x"f" ;
COL <= '0' ;
TX <= x"3263" ;
TX_STB <= '0' ;
RX_ACK <= '0' ;
--52
wait for 10 ns;
RST <= '0' ;
RXER <= '0' ;
RXDV <= '1' ;
RXD <= x"2" ;
COL <= '0' ;
TX <= x"3263" ;
TX_STB <= '0' ;
RX_ACK <= '0' ; --f1 -------------
wait for 10 ns;
RST <= '0' ;
RXER <= '0' ;
RXDV <= '1' ;
RXD <= x"5" ;
COL <= '0' ;
TX <= x"3263" ;
TX_STB <= '0' ;
RX_ACK <= '0' ;
--f1
wait for 10 ns;
RST <= '0' ;
RXER <= '0' ;
RXDV <= '1' ;
RXD <= x"1" ;
COL <= '0' ;
TX <= x"3263" ;
TX_STB <= '0' ;
RX_ACK <= '0' ; --30
wait for 10 ns;
RST <= '0' ;
RXER <= '0' ;
RXDV <= '1' ;
RXD <= x"f" ;
COL <= '0' ;
TX <= x"3263" ;
TX_STB <= '0' ;
RX_ACK <= '0' ;
-- 30
wait for 10 ns;
RST <= '0' ;
RXER <= '0' ;
RXDV <= '1' ;
RXD <= x"0" ;
COL <= '0' ;
TX <= x"3263" ;
TX_STB <= '0' ;
RX_ACK <= '0' ; --08
wait for 10 ns;
RST <= '0' ;
RXER <= '0' ;
RXDV <= '1' ;
RXD <= x"3" ;
COL <= '0' ;
TX <= x"3263" ;
TX_STB <= '0' ;
RX_ACK <= '0' ;
--c0
wait for 10 ns;
RST <= '0' ;
RXER <= '0' ;
RXDV <= '1' ;
RXD <= x"0" ;
COL <= '0' ;
TX <= x"3263" ;
TX_STB <= '0' ;
RX_ACK <= '0' ; --06
wait for 10 ns;
RST <= '0' ;
RXER <= '0' ;
RXDV <= '1' ;
RXD <= x"c" ;
COL <= '0' ;
TX <= x"3263" ;
TX_STB <= '0' ;
RX_ACK <= '0' ;
--a8
wait for 10 ns;
RST <= '0' ;
RXER <= '0' ;
RXDV <= '1' ;
RXD <= x"8" ;
COL <= '0' ;
TX <= x"3263" ;
TX_STB <= '0' ;
RX_ACK <= '0' ; --00
wait for 10 ns;
RST <= '0' ;
RXER <= '0' ;
RXDV <= '1' ;
RXD <= x"a" ;
COL <= '0' ;
TX <= x"3263" ;
TX_STB <= '0' ;
RX_ACK <= '0' ; --7
--00
wait for 10 ns;
RST <= '0' ;
RXER <= '0' ;
RXDV <= '1' ;
RXD <= x"0" ;
COL <= '0' ;
TX <= x"3263" ;
TX_STB <= '0' ;
RX_ACK <= '0' ;--01
wait for 10 ns;
RST <= '0' ;
RXER <= '0' ;
RXDV <= '1' ;
RXD <= x"0" ;
COL <= '0' ;
TX <= x"3263" ;
TX_STB <= '0' ;
RX_ACK <= '0' ;
--69 --
wait for 10 ns;
RST <= '0' ;
RXER <= '0' ;
RXDV <= '1' ;
RXD <= x"9" ;
COL <= '0' ;
TX <= x"3263" ;
TX_STB <= '0' ;
RX_ACK <= '0' ; --08
wait for 10 ns;
RST <= '0' ;
RXER <= '0' ;
RXDV <= '1' ;
RXD <= x"6" ;
COL <= '0' ;
TX <= x"3263" ;
TX_STB <= '0' ;
RX_ACK <= '0' ;
----00
wait for 10 ns;
RST <= '0' ;
RXER <= '0' ;
RXDV <= '1' ;
RXD <= x"0" ;
COL <= '0' ;
TX <= x"3263" ;
TX_STB <= '0' ;
RX_ACK <= '0' ;--00
wait for 10 ns;
RST <= '0' ;
RXER <= '0' ;
RXDV <= '1' ;
RXD <= x"0" ;
COL <= '0' ;
TX <= x"3263" ;
TX_STB <= '0' ;
RX_ACK <= '0' ;
--01
wait for 10 ns;
RST <= '0' ;
RXER <= '0' ;
RXDV <= '1' ;
RXD <= x"1" ;
COL <= '0' ;
TX <= x"3263" ;
TX_STB <= '0' ;
RX_ACK <= '0' ; --06
wait for 10 ns;
RST <= '0' ;
RXER <= '0' ;
RXDV <= '1' ;
RXD <= x"0" ;
COL <= '0' ;
TX <= x"3263" ;
TX_STB <= '0' ;
RX_ACK <= '0' ;
--02
wait for 10 ns;
RST <= '0' ;
RXER <= '0' ;
RXDV <= '1' ;
RXD <= x"2" ;
COL <= '0' ;
TX <= x"3263" ;
TX_STB <= '0' ;
RX_ACK <= '0' ; --04
wait for 10 ns;
RST <= '0' ;
RXER <= '0' ;
RXDV <= '1' ;
RXD <= x"0" ;
COL <= '0' ;
TX <= x"3263" ;
TX_STB <= '0' ;
RX_ACK <= '0' ;
--03
wait for 10 ns;
RST <= '0' ;
RXER <= '0' ;
RXDV <= '1' ;
RXD <= x"3" ;
COL <= '0' ;
TX <= x"3263" ;
TX_STB <= '0' ;
RX_ACK <= '0' ;--00
wait for 10 ns;
RST <= '0' ;
RXER <= '0' ;
RXDV <= '1' ;
RXD <= x"0" ;
COL <= '0' ;
TX <= x"3263" ;
TX_STB <= '0' ;
RX_ACK <= '0' ;
--04
wait for 10 ns;
RST <= '0' ;
RXER <= '0' ;
RXDV <= '1' ;
RXD <= x"4" ;
COL <= '0' ;
TX <= x"3263" ;
TX_STB <= '0' ;
RX_ACK <= '0' ;--01
wait for 10 ns;
RST <= '0' ;
RXER <= '0' ;
RXDV <= '1' ;
RXD <= x"0" ;
COL <= '0' ;
TX <= x"3263" ;
TX_STB <= '0' ;
RX_ACK <= '0' ;
--05
wait for 10 ns;
RST <= '0' ;
RXER <= '0' ;
RXDV <= '1' ;
RXD <= x"5" ;
COL <= '0' ;
TX <= x"3263" ;
TX_STB <= '0' ;
RX_ACK <= '0' ;--00
wait for 10 ns;
RST <= '0' ;
RXER <= '0' ;
RXDV <= '1' ;
RXD <= x"0" ;
COL <= '0' ;
TX <= x"3263" ;
TX_STB <= '0' ;
RX_ACK <= '0' ;
--c0
wait for 10 ns;
RST <= '0' ;
RXER <= '0' ;
RXDV <= '1' ;
RXD <= x"0" ;
COL <= '0' ;
TX <= x"3263" ;
TX_STB <= '0' ;
RX_ACK <= '0' ;--18
wait for 10 ns;
RST <= '0' ;
RXER <= '0' ;
RXDV <= '1' ;
RXD <= x"c" ;
COL <= '0' ;
TX <= x"3263" ;
TX_STB <= '0' ;
RX_ACK <= '0' ;
--a8
wait for 10 ns;
RST <= '0' ;
RXER <= '0' ;
RXDV <= '1' ;
RXD <= x"8" ;
COL <= '0' ;
TX <= x"3263" ;
TX_STB <= '0' ;
RX_ACK <= '0' ;--f3
wait for 10 ns;
RST <= '0' ;
RXER <= '0' ;
RXDV <= '1' ;
RXD <= x"a" ;
COL <= '0' ;
TX <= x"3263" ;
TX_STB <= '0' ;
RX_ACK <= '0' ;
--00
wait for 10 ns;
RST <= '0' ;
RXER <= '0' ;
RXDV <= '1' ;
RXD <= x"0" ;
COL <= '0' ;
TX <= x"3263" ;
TX_STB <= '0' ;
RX_ACK <= '0' ;
wait for 10 ns;
RST <= '0' ;
RXER <= '0' ;
RXDV <= '1' ;
RXD <= x"0" ;
COL <= '0' ;
TX <= x"3263" ;
TX_STB <= '0' ;
RX_ACK <= '0' ;
--77
wait for 10 ns;
RST <= '0' ;
RXER <= '0' ;
RXDV <= '1' ;
RXD <= x"7" ;
COL <= '0' ;
TX <= x"3263" ;
TX_STB <= '0' ;
RX_ACK <= '0' ;--f1
wait for 10 ns;
RST <= '0' ;
RXER <= '0' ;
RXDV <= '1' ;
RXD <= x"7" ;
COL <= '0' ;
TX <= x"3263" ;
TX_STB <= '0' ;
RX_ACK <= '0' ;
-- E9
wait for 10 ns;
RST <= '0' ;
RXER <= '0' ;
RXDV <= '1' ;
RXD <= x"9" ;
COL <= '0' ;
TX <= x"3263" ;
TX_STB <= '0' ;
RX_ACK <= '0' ;--30
wait for 10 ns;
RST <= '0' ;
RXER <= '0' ;
RXDV <= '1' ;
RXD <= x"e" ;
COL <= '0' ;
TX <= x"3263" ;
TX_STB <= '0' ;
RX_ACK <= '0' ;
--AC
wait for 10 ns;
RST <= '0' ;
RXER <= '0' ;
RXDV <= '1' ;
RXD <= x"c" ;
COL <= '0' ;
TX <= x"3263" ;
TX_STB <= '0' ;
RX_ACK <= '0' ; --c0
wait for 10 ns;
RST <= '0' ;
RXER <= '0' ;
RXDV <= '1' ;
RXD <= x"a" ;
COL <= '0' ;
TX <= x"3263" ;
TX_STB <= '0' ;
RX_ACK <= '0' ;
--AB
wait for 10 ns;
RST <= '0' ;
RXER <= '0' ;
RXDV <= '1' ;
RXD <= x"b" ;
COL <= '0' ;
TX <= x"3263" ;
TX_STB <= '0' ;
RX_ACK <= '0' ; --a8
wait for 10 ns;
RST <= '0' ;
RXER <= '0' ;
RXDV <= '1' ;
RXD <= x"a" ;
COL <= '0' ;
TX <= x"3263" ;
TX_STB <= '0' ;
RX_ACK <= '0' ;
--61
wait for 10 ns;
RST <= '0' ;
RXER <= '0' ;
RXDV <= '1' ;
RXD <= x"1" ;
COL <= '0' ;
TX <= x"3263" ;
TX_STB <= '0' ;
RX_ACK <= '0' ;--00
wait for 10 ns;
RST <= '0' ;
RXER <= '0' ;
RXDV <= '1' ;
RXD <= x"6" ;
COL <= '0' ;
TX <= x"3263" ;
TX_STB <= '0' ;
RX_ACK <= '0' ;
wait for 10 ns; ----------------- End of test Rx Fame -----
RST <= '0' ;
RXER <= '0' ;
RXDV <= '1' ;
RXD <= x"6" ;
COL <= '0' ;
TX <= x"3263" ;
TX_STB <= '0' ;
RX_ACK <= '0' ;--69
wait for 10 ns;
RST <= '0' ;
RXER <= '0' ;
RXDV <= '1' ;
RXD <= x"0" ;
COL <= '0' ;
TX <= x"3263" ;
TX_STB <= '0' ;
RX_ACK <= '0' ;
wait for 10 ns;
RST <= '0' ;
RXER <= '0' ;
RXDV <= '1' ;
RXD <= x"0" ;
COL <= '0' ;
TX <= x"3263" ;
TX_STB <= '0' ;
RX_ACK <= '0' ; --00
wait for 10 ns;
RST <= '0' ;
RXER <= '0' ;
RXDV <= '1' ;
RXD <= x"1" ;
COL <= '0' ;
TX <= x"3263" ;
TX_STB <= '0' ;
RX_ACK <= '0' ;
wait for 10 ns;
RST <= '0' ;
RXER <= '0' ;
RXDV <= '1' ;
RXD <= x"0" ;
COL <= '0' ;
TX <= x"3263" ;
TX_STB <= '0' ;
RX_ACK <= '0' ;--01
wait for 10 ns;
RST <= '0' ;
RXER <= '0' ;
RXDV <= '1' ;
RXD <= x"2" ;
COL <= '0' ;
TX <= x"3263" ;
TX_STB <= '0' ;
RX_ACK <= '0' ;
wait for 10 ns;
RST <= '0' ;
RXER <= '0' ;
RXDV <= '1' ;
RXD <= x"0" ;
COL <= '0' ;
TX <= x"3263" ;
TX_STB <= '0' ;
RX_ACK <= '0' ; --02
wait for 10 ns;
RST <= '0' ;
RXER <= '0' ;
RXDV <= '1' ;
RXD <= x"3" ;
COL <= '0' ;
TX <= x"3263" ;
TX_STB <= '0' ;
RX_ACK <= '0' ;
wait for 10 ns;
RST <= '0' ;
RXER <= '0' ;
RXDV <= '1' ;
RXD <= x"0" ;
COL <= '0' ;
TX <= x"3263" ;
TX_STB <= '0' ;
RX_ACK <= '0' ;--03
wait for 10 ns;
RST <= '0' ;
RXER <= '0' ;
RXDV <= '1' ;
RXD <= x"4" ;
COL <= '0' ;
TX <= x"3263" ;
TX_STB <= '0' ;
RX_ACK <= '0' ;
wait for 10 ns;
RST <= '0' ;
RXER <= '0' ;
RXDV <= '1' ;
RXD <= x"0" ;
COL <= '0' ;
TX <= x"3263" ;
TX_STB <= '0' ;
RX_ACK <= '0' ;--04
wait for 10 ns;
RST <= '0' ;
RXER <= '0' ;
RXDV <= '1' ;
RXD <= x"5" ;
COL <= '0' ;
TX <= x"3263" ;
TX_STB <= '0' ;
RX_ACK <= '0' ;
wait for 10 ns;
RST <= '0' ;
RXER <= '0' ;
RXDV <= '1' ;
RXD <= x"0" ;
COL <= '0' ;
TX <= x"3263" ;
TX_STB <= '0' ;
RX_ACK <= '0' ; --05
wait for 10 ns;
RST <= '0' ;
RXER <= '0' ;
RXDV <= '1' ;
RXD <= x"0" ;
COL <= '0' ;
TX <= x"3263" ;
TX_STB <= '0' ;
RX_ACK <= '0' ;
wait for 10 ns;
RST <= '0' ;
RXER <= '0' ;
RXDV <= '1' ;
RXD <= x"c" ;
COL <= '0' ;
TX <= x"3263" ;
TX_STB <= '0' ;
RX_ACK <= '0' ; --c0
wait for 10 ns;
RST <= '0' ;
RXER <= '0' ;
RXDV <= '1' ;
RXD <= x"8" ;
COL <= '0' ;
TX <= x"3263" ;
TX_STB <= '0' ;
RX_ACK <= '0' ;
wait for 10 ns;
RST <= '0' ;
RXER <= '0' ;
RXDV <= '1' ;
RXD <= x"a" ;
COL <= '0' ;
TX <= x"3263" ;
TX_STB <= '0' ;
RX_ACK <= '0' ;--a8
wait for 10 ns;
RST <= '0' ;
RXER <= '0' ;
RXDV <= '1' ;
RXD <= x"0" ;
COL <= '0' ;
TX <= x"3263" ;
TX_STB <= '0' ;
RX_ACK <= '0' ;
wait for 10 ns;
RST <= '0' ;
RXER <= '0' ;
RXDV <= '1' ;
RXD <= x"0" ;
COL <= '0' ;
TX <= x"3263" ;
TX_STB <= '0' ;
RX_ACK <= '0' ;--00
wait for 10 ns;
RST <= '0' ;
RXER <= '0' ;
RXDV <= '1' ;
RXD <= x"7" ;
COL <= '0' ;
TX <= x"3263" ;
TX_STB <= '0' ;
RX_ACK <= '0' ;
wait for 10 ns;
RST <= '0' ;
RXER <= '0' ;
RXDV <= '1' ;
RXD <= x"7" ;
COL <= '0' ;
TX <= x"3263" ;
TX_STB <= '0' ;
RX_ACK <= '0' ;--77
wait for 10 ns;
RST <= '0' ;
RXER <= '0' ;
RXDV <= '1' ;
RXD <= x"9" ;
COL <= '0' ;
TX <= x"3263" ;
TX_STB <= '0' ;
RX_ACK <= '0' ;
wait for 10 ns;
RST <= '0' ;
RXER <= '0' ;
RXDV <= '1' ;
RXD <= x"e" ;
COL <= '0' ;
TX <= x"3263" ;
TX_STB <= '0' ;
RX_ACK <= '0' ;--e9
wait for 10 ns;
RST <= '0' ;
RXER <= '0' ;
RXDV <= '1' ;
RXD <= x"c" ;
COL <= '0' ;
TX <= x"3263" ;
TX_STB <= '0' ;
RX_ACK <= '0' ;
wait for 10 ns;
RST <= '0' ;
RXER <= '0' ;
RXDV <= '1' ;
RXD <= x"a" ;
COL <= '0' ;
TX <= x"3263" ;
TX_STB <= '0' ;
RX_ACK <= '0' ;--ac
wait for 10 ns;
RST <= '0' ;
RXER <= '0' ;
RXDV <= '1' ;
RXD <= x"b" ;
COL <= '0' ;
TX <= x"3263" ;
TX_STB <= '0' ;
RX_ACK <= '0' ;
wait for 10 ns;
RST <= '0' ;
RXER <= '0' ;
RXDV <= '1' ;
RXD <= x"a" ;
COL <= '0' ;
TX <= x"3263" ;
TX_STB <= '0' ;
RX_ACK <= '0' ;--ab
wait for 10 ns;
RST <= '0' ;
RXER <= '0' ;
RXDV <= '1' ;
RXD <= x"1" ;
COL <= '0' ;
TX <= x"3263" ;
TX_STB <= '0' ;
RX_ACK <= '0' ;
wait for 10 ns;
RST <= '0' ;
RXER <= '0' ;
RXDV <= '1' ;
RXD <= x"6" ;
COL <= '0' ;
TX <= x"3263" ;
TX_STB <= '0' ;
RX_ACK <= '0' ;--61
-------------------- DONE frame--------------
wait for 10 ns;
RST <= '0' ;
RXER <= '0' ;
RXDV <= '0' ;
RXD <= x"0" ;
COL <= '0' ;
TX <= x"3863" ;
TX_STB <= '0' ;
RX_ACK <= '1' ;
wait for 10 ns;
RST <= '0' ;
RXER <= '0' ;
RXDV <= '0' ;
RXD <= x"0" ;
COL <= '0' ;
TX <= x"3244" ;
TX_STB <= '0' ;
RX_ACK <= '0' ;
wait for 10 ns;
RST <= '0' ;
RXER <= '0' ;
RXDV <= '0' ;
RXD <= x"0" ;
COL <= '0' ;
TX <= x"3863" ;
TX_STB <= '0' ;
RX_ACK <= '0' ;
wait for 10 ns;
RST <= '0' ;
RXER <= '0' ;
RXDV <= '0' ;
RXD <= x"0" ;
COL <= '0' ;
TX <= x"3244" ;
TX_STB <= '0' ;
RX_ACK <= '0' ;
wait for 10 ns;
RST <= '0' ;
RXER <= '0' ;
RXDV <= '0' ;
RXD <= x"0" ;
COL <= '0' ;
TX <= x"3863" ;
TX_STB <= '0' ;
RX_ACK <= '0' ;
wait for 10 ns;
RST <= '0' ;
RXER <= '0' ;
RXDV <= '0' ;
RXD <= x"0" ;
COL <= '0' ;
TX <= x"3244" ;
TX_STB <= '0' ;
RX_ACK <= '0' ;
wait for 10 ns;
RST <= '0' ;
RXER <= '0' ;
RXDV <= '0' ;
RXD <= x"0" ;
COL <= '0' ;
TX <= x"3863" ;
TX_STB <= '0' ;
RX_ACK <= '0' ;
wait for 10 ns;
RST <= '0' ;
RXER <= '0' ;
RXDV <= '0' ;
RXD <= x"0" ;
COL <= '0' ;
TX <= x"3244" ;
TX_STB <= '0' ;
RX_ACK <= '0' ;
wait for 10 ns;
RST <= '0' ;
RXER <= '0' ;
RXDV <= '0' ;
RXD <= x"0" ;
COL <= '0' ;
TX <= x"3863" ;
TX_STB <= '0' ;
RX_ACK <= '0' ;
wait for 10 ns;
RST <= '0' ;
RXER <= '0' ;
RXDV <= '0' ;
RXD <= x"0" ;
COL <= '0' ;
TX <= x"3244" ;
TX_STB <= '0' ;
RX_ACK <= '0' ;
wait for 10 ns;
RST <= '0' ;
RXER <= '0' ;
RXDV <= '0' ;
RXD <= x"0" ;
COL <= '0' ;
TX <= x"3863" ;
TX_STB <= '0' ;
RX_ACK <= '0' ;
wait for 10 ns;
RST <= '0' ;
RXER <= '0' ;
RXDV <= '0' ;
RXD <= x"0" ;
COL <= '0' ;
TX <= x"3244" ;
TX_STB <= '0' ;
RX_ACK <= '0' ;
wait for 10 ns;
RST <= '0' ;
RXER <= '0' ;
RXDV <= '0' ;
RXD <= x"0" ;
COL <= '0' ;
TX <= x"3863" ;
TX_STB <= '0' ;
RX_ACK <= '0' ;
wait for 10 ns;
RST <= '0' ;
RXER <= '0' ;
RXDV <= '0' ;
RXD <= x"0" ;
COL <= '0' ;
TX <= x"3244" ;
TX_STB <= '0' ;
RX_ACK <= '0' ;
wait for 10 ns;
RST <= '0' ;
RXER <= '0' ;
RXDV <= '0' ;
RXD <= x"0" ;
COL <= '0' ;
TX <= x"3863" ;
TX_STB <= '0' ;
RX_ACK <= '0' ;
wait for 10 ns;
RST <= '0' ;
RXER <= '0' ;
RXDV <= '0' ;
RXD <= x"0" ;
COL <= '0' ;
TX <= x"3244" ;
TX_STB <= '0' ;
RX_ACK <= '0' ;----------------- Tx
wait for 10 ns;
RST <= '0' ;
RXER <= '0' ;
RXDV <= '0' ;
RXD <= x"0" ;
COL <= '0' ;
TX <= x"3863" ;
TX_STB <= '1' ;
RX_ACK <= '0' ;
wait for 10 ns;
RST <= '0' ;
RXER <= '0' ;
RXDV <= '0' ;
RXD <= x"0" ;
COL <= '0' ;
TX <= x"3244" ;
TX_STB <= '1' ;
RX_ACK <= '0' ;
wait for 10 ns;
RST <= '0' ;
RXER <= '0' ;
RXDV <= '0' ;
RXD <= x"0" ;
COL <= '0' ;
TX <= x"3863" ;
TX_STB <= '1' ;
RX_ACK <= '0' ;
wait for 10 ns;
RST <= '0' ;
RXER <= '0' ;
RXDV <= '0' ;
RXD <= x"0" ;
COL <= '0' ;
TX <= x"3244" ;
TX_STB <= '1' ;
RX_ACK <= '0' ;
wait for 10 ns;
RST <= '0' ;
RXER <= '0' ;
RXDV <= '0' ;
RXD <= x"0" ;
COL <= '0' ;
TX <= x"3863" ;
TX_STB <= '1' ;
RX_ACK <= '0' ;
wait for 10 ns;
RST <= '0' ;
RXER <= '0' ;
RXDV <= '0' ;
RXD <= x"0" ;
COL <= '0' ;
TX <= x"3244" ;
TX_STB <= '1' ;
RX_ACK <= '0' ;
wait for 10 ns;
RST <= '0' ;
RXER <= '0' ;
RXDV <= '0' ;
RXD <= x"0" ;
COL <= '0' ;
TX <= x"3863" ;
TX_STB <= '1' ;
RX_ACK <= '0' ;
wait for 10 ns;
RST <= '0' ;
RXER <= '0' ;
RXDV <= '0' ;
RXD <= x"0" ;
COL <= '0' ;
TX <= x"3244" ;
TX_STB <= '1' ;
RX_ACK <= '0' ;
wait for 10 ns;
RST <= '0' ;
RXER <= '0' ;
RXDV <= '0' ;
RXD <= x"0" ;
COL <= '0' ;
TX <= x"3863" ;
TX_STB <= '1' ;
RX_ACK <= '0' ;
wait for 10 ns;
RST <= '0' ;
RXER <= '0' ;
RXDV <= '0' ;
RXD <= x"0" ;
COL <= '0' ;
TX <= x"3244" ;
TX_STB <= '1' ;
RX_ACK <= '0' ;
wait for 10 ns;
RST <= '0' ;
RXER <= '0' ;
RXDV <= '0' ;
RXD <= x"0" ;
COL <= '0' ;
TX <= x"3863" ;
TX_STB <= '1' ;
RX_ACK <= '0' ;
wait for 10 ns;
RST <= '0' ;
RXER <= '0' ;
RXDV <= '0' ;
RXD <= x"0" ;
COL <= '0' ;
TX <= x"3244" ;
TX_STB <= '1' ;
RX_ACK <= '0' ;
wait for 10 ns;
RST <= '0' ;
RXER <= '0' ;
RXDV <= '0' ;
RXD <= x"0" ;
COL <= '0' ;
TX <= x"3863" ;
TX_STB <= '1' ;
RX_ACK <= '0' ;
wait for 10 ns;
RST <= '0' ;
RXER <= '0' ;
RXDV <= '0' ;
RXD <= x"0" ;
COL <= '0' ;
TX <= x"3244" ;
TX_STB <= '1' ;
RX_ACK <= '0' ;
wait for 10 ns;
RST <= '0' ;
RXER <= '0' ;
RXDV <= '0' ;
RXD <= x"0" ;
COL <= '0' ;
TX <= x"3863" ;
TX_STB <= '1' ;
RX_ACK <= '0' ;
wait for 10 ns;
RST <= '0' ;
RXER <= '0' ;
RXDV <= '0' ;
RXD <= x"0" ;
COL <= '0' ;
TX <= x"3244" ;
TX_STB <= '1' ;
RX_ACK <= '0' ;
wait for 10 ns;
RST <= '0' ;
RXER <= '0' ;
RXDV <= '0' ;
RXD <= x"0" ;
COL <= '0' ;
TX <= x"3863" ;
TX_STB <= '1' ;
RX_ACK <= '0' ;
wait for 10 ns;
RST <= '0' ;
RXER <= '0' ;
RXDV <= '0' ;
RXD <= x"0" ;
COL <= '0' ;
TX <= x"3244" ;
TX_STB <= '1' ;
RX_ACK <= '0' ;
wait for 10 ns;
RST <= '0' ;
RXER <= '0' ;
RXDV <= '0' ;
RXD <= x"0" ;
COL <= '0' ;
TX <= x"3863" ;
TX_STB <= '1' ;
RX_ACK <= '0' ;
wait for 10 ns;
RST <= '0' ;
RXER <= '0' ;
RXDV <= '0' ;
RXD <= x"0" ;
COL <= '0' ;
TX <= x"3244" ;
TX_STB <= '1' ;
RX_ACK <= '0' ;
wait for 10 ns;
RST <= '0' ;
RXER <= '0' ;
RXDV <= '0' ;
RXD <= x"0" ;
COL <= '0' ;
TX <= x"3863" ;
TX_STB <= '1' ;
RX_ACK <= '0' ;
wait for 10 ns;
RST <= '0' ;
RXER <= '0' ;
RXDV <= '0' ;
RXD <= x"0" ;
COL <= '0' ;
TX <= x"3244" ;
TX_STB <= '1' ;
RX_ACK <= '0' ;
wait for 10 ns;
RST <= '0' ;
RXER <= '0' ;
RXDV <= '0' ;
RXD <= x"0" ;
COL <= '0' ;
TX <= x"3863" ;
TX_STB <= '1' ;
RX_ACK <= '0' ;
wait for 10 ns;
RST <= '0' ;
RXER <= '0' ;
RXDV <= '0' ;
RXD <= x"0" ;
COL <= '0' ;
TX <= x"3244" ;
TX_STB <= '1' ;
RX_ACK <= '0' ;
wait for 10 ns;
RST <= '0' ;
RXER <= '0' ;
RXDV <= '0' ;
RXD <= x"0" ;
COL <= '0' ;
TX <= x"3863" ;
TX_STB <= '1' ;
RX_ACK <= '0' ;
wait for 10 ns;
RST <= '0' ;
RXER <= '0' ;
RXDV <= '0' ;
RXD <= x"0" ;
COL <= '0' ;
TX <= x"3244" ;
TX_STB <= '1' ;
RX_ACK <= '0' ;
wait for 10 ns;
RST <= '0' ;
RXER <= '0' ;
RXDV <= '0' ;
RXD <= x"0" ;
COL <= '0' ;
TX <= x"3863" ;
TX_STB <= '1' ;
RX_ACK <= '0' ;
wait for 10 ns;
RST <= '0' ;
RXER <= '0' ;
RXDV <= '0' ;
RXD <= x"0" ;
COL <= '0' ;
TX <= x"3244" ;
TX_STB <= '1' ;
RX_ACK <= '0' ;
wait for 10 ns;
RST <= '0' ;
RXER <= '0' ;
RXDV <= '0' ;
RXD <= x"0" ;
COL <= '0' ;
TX <= x"3863" ;
TX_STB <= '1' ;
RX_ACK <= '0' ;
wait for 10 ns;
RST <= '0' ;
RXER <= '0' ;
RXDV <= '0' ;
RXD <= x"0" ;
COL <= '0' ;
TX <= x"3244" ;
TX_STB <= '1' ;
RX_ACK <= '0' ;
wait for 10 ns;
RST <= '0' ;
RXER <= '0' ;
RXDV <= '0' ;
RXD <= x"0" ;
COL <= '0' ;
TX <= x"3863" ;
TX_STB <= '1' ;
RX_ACK <= '0' ;
wait for 10 ns;
RST <= '0' ;
RXER <= '0' ;
RXDV <= '0' ;
RXD <= x"0" ;
COL <= '0' ;
TX <= x"3244" ;
TX_STB <= '1' ;
RX_ACK <= '0' ;
wait for 10 ns;
RST <= '0' ;
RXER <= '0' ;
RXDV <= '0' ;
RXD <= x"0" ;
COL <= '0' ;
TX <= x"3863" ;
TX_STB <= '1' ;
RX_ACK <= '0' ;
wait for 10 ns;
RST <= '0' ;
RXER <= '0' ;
RXDV <= '0' ;
RXD <= x"0" ;
COL <= '0' ;
TX <= x"3244" ;
TX_STB <= '1' ;
RX_ACK <= '0' ;
wait for 10 ns;
RST <= '0' ;
RXER <= '0' ;
RXDV <= '0' ;
RXD <= x"0" ;
COL <= '0' ;
TX <= x"3863" ;
TX_STB <= '1' ;
RX_ACK <= '0' ;
wait for 10 ns;
RST <= '0' ;
RXER <= '0' ;
RXDV <= '0' ;
RXD <= x"0" ;
COL <= '0' ;
TX <= x"3244" ;
TX_STB <= '1' ;
RX_ACK <= '0' ;--------------------
wait for 10 ns;
RST <= '0' ;
RXER <= '0' ;
RXDV <= '0' ;
RXD <= x"0" ;
COL <= '0' ;
TX <= x"3863" ;
TX_STB <= '0' ;
RX_ACK <= '0' ;
wait for 10 ns;
RST <= '0' ;
RXER <= '0' ;
RXDV <= '0' ;
RXD <= x"0" ;
COL <= '0' ;
TX <= x"3244" ;
TX_STB <= '0' ;
RX_ACK <= '0' ;
wait;
end process;
END;
| mit | 185dc6f070696a97db86f9354ae96ec3 | 0.266211 | 3.356599 | false | false | false | false |
impedimentToProgress/UCI-BlueChip | AttackFiles/Attacks/privEsc/lib/techmap/ec/memory_ec.vhd | 2 | 92,541 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: various
-- File: mem_ec_gen.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: Memory generators for Lattice XP/EC/ECP RAM blocks
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
-- pragma translate_off
library ec;
use ec.dp8ka;
-- pragma translate_on
entity EC_RAMB8_S1_S1 is
port (
DataInA: in std_logic_vector(0 downto 0);
DataInB: in std_logic_vector(0 downto 0);
AddressA: in std_logic_vector(12 downto 0);
AddressB: in std_logic_vector(12 downto 0);
ClockA: in std_logic;
ClockB: in std_logic;
ClockEnA: in std_logic;
ClockEnB: in std_logic;
WrA: in std_logic;
WrB: in std_logic;
QA: out std_logic_vector(0 downto 0);
QB: out std_logic_vector(0 downto 0));
end;
architecture Structure of EC_RAMB8_S1_S1 is
COMPONENT dp8ka
GENERIC(
DATA_WIDTH_A : in Integer := 18;
DATA_WIDTH_B : in Integer := 18;
REGMODE_A : String := "NOREG";
REGMODE_B : String := "NOREG";
RESETMODE : String := "ASYNC";
CSDECODE_A : String := "000";
CSDECODE_B : String := "000";
WRITEMODE_A : String := "NORMAL";
WRITEMODE_B : String := "NORMAL";
GSR : String := "ENABLED";
initval_00 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_01 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_02 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_03 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_04 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_05 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_06 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_07 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_08 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_09 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0a : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0b : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0c : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0d : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0e : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0f : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_10 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_11 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_12 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_13 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_14 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_15 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_16 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_17 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_18 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_19 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1a : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1b : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1c : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1d : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1e : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1f : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"
);
PORT(
dia0, dia1, dia2, dia3, dia4, dia5, dia6, dia7, dia8 : in std_logic := 'X';
dia9, dia10, dia11, dia12, dia13, dia14, dia15, dia16, dia17 : in std_logic := 'X';
ada0, ada1, ada2, ada3, ada4, ada5, ada6, ada7, ada8 : in std_logic := 'X';
ada9, ada10, ada11, ada12 : in std_logic := 'X';
cea, clka, wea, csa0, csa1, csa2, rsta : in std_logic := 'X';
dib0, dib1, dib2, dib3, dib4, dib5, dib6, dib7, dib8 : in std_logic := 'X';
dib9, dib10, dib11, dib12, dib13, dib14, dib15, dib16, dib17 : in std_logic := 'X';
adb0, adb1, adb2, adb3, adb4, adb5, adb6, adb7, adb8 : in std_logic := 'X';
adb9, adb10, adb11, adb12 : in std_logic := 'X';
ceb, clkb, web, csb0, csb1, csb2, rstb : in std_logic := 'X';
doa0, doa1, doa2, doa3, doa4, doa5, doa6, doa7, doa8 : out std_logic := 'X';
doa9, doa10, doa11, doa12, doa13, doa14, doa15, doa16, doa17 : out std_logic := 'X';
dob0, dob1, dob2, dob3, dob4, dob5, dob6, dob7, dob8 : out std_logic := 'X';
dob9, dob10, dob11, dob12, dob13, dob14, dob15, dob16, dob17 : out std_logic := 'X'
);
END COMPONENT;
signal vcc, gnd : std_ulogic;
begin
vcc <= '1'; gnd <= '0';
u0: DP8KA
generic map (CSDECODE_B=>"000", CSDECODE_A=>"000",
WRITEMODE_B=>"NORMAL", WRITEMODE_A=>"NORMAL",
GSR=>"DISABLED", RESETMODE=>"ASYNC", REGMODE_B=>"NOREG",
REGMODE_A=>"NOREG", DATA_WIDTH_B=> 1, DATA_WIDTH_A=> 1)
port map (CEA=>ClockEnA, CLKA=>ClockA, WEA=>WrA, CSA0=>gnd,
CSA1=>gnd, CSA2=>gnd, RSTA=>gnd,
CEB=>ClockEnB, CLKB=>ClockB, WEB=>WrB, CSB0=>gnd,
CSB1=>gnd, CSB2=>gnd, RSTB=>gnd,
DIA0=>gnd, DIA1=>gnd, DIA2=>gnd,
DIA3=>gnd, DIA4=>gnd, DIA5=>gnd,
DIA6=>gnd, DIA7=>gnd, DIA8=>gnd,
DIA9=>gnd, DIA10=>gnd, DIA11=>DataInA(0),
DIA12=>gnd, DIA13=>gnd, DIA14=>gnd,
DIA15=>gnd, DIA16=>gnd, DIA17=>gnd,
ADA0=>AddressA(0), ADA1=>AddressA(1), ADA2=>AddressA(2),
ADA3=>AddressA(3), ADA4=>AddressA(4), ADA5=>AddressA(5),
ADA6=>AddressA(6), ADA7=>AddressA(7), ADA8=>AddressA(8),
ADA9=>AddressA(9), ADA10=>AddressA(10), ADA11=>AddressA(11),
ADA12=>AddressA(12), DIB0=>gnd, DIB1=>gnd,
DIB2=>gnd, DIB3=>gnd, DIB4=>gnd,
DIB5=>gnd, DIB6=>gnd, DIB7=>gnd,
DIB8=>gnd, DIB9=>gnd, DIB10=>gnd,
DIB11=>DataInB(0), DIB12=>gnd, DIB13=>gnd,
DIB14=>gnd, DIB15=>gnd, DIB16=>gnd,
DIB17=>gnd, ADB0=>AddressB(0), ADB1=>AddressB(1),
ADB2=>AddressB(2), ADB3=>AddressB(3), ADB4=>AddressB(4),
ADB5=>AddressB(5), ADB6=>AddressB(6), ADB7=>AddressB(7),
ADB8=>AddressB(8), ADB9=>AddressB(9), ADB10=>AddressB(10),
ADB11=>AddressB(11), ADB12=>AddressB(12), DOA0=>QA(0),
DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open,
DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open,
DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open,
DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open,
DOA17=>open, DOB0=>QB(0), DOB1=>open, DOB2=>open,
DOB3=>open, DOB4=>open, DOB5=>open, DOB6=>open,
DOB7=>open, DOB8=>open, DOB9=>open, DOB10=>open,
DOB11=>open, DOB12=>open, DOB13=>open, DOB14=>open,
DOB15=>open, DOB16=>open, DOB17=>open);
end;
library ieee;
use ieee.std_logic_1164.all;
-- pragma translate_off
library ec;
use ec.dp8ka;
-- pragma translate_on
entity EC_RAMB8_S2_S2 is
port (
DataInA: in std_logic_vector(1 downto 0);
DataInB: in std_logic_vector(1 downto 0);
AddressA: in std_logic_vector(11 downto 0);
AddressB: in std_logic_vector(11 downto 0);
ClockA: in std_logic;
ClockB: in std_logic;
ClockEnA: in std_logic;
ClockEnB: in std_logic;
WrA: in std_logic;
WrB: in std_logic;
QA: out std_logic_vector(1 downto 0);
QB: out std_logic_vector(1 downto 0));
end;
architecture Structure of EC_RAMB8_S2_S2 is
COMPONENT dp8ka
GENERIC(
DATA_WIDTH_A : in Integer := 18;
DATA_WIDTH_B : in Integer := 18;
REGMODE_A : String := "NOREG";
REGMODE_B : String := "NOREG";
RESETMODE : String := "ASYNC";
CSDECODE_A : String := "000";
CSDECODE_B : String := "000";
WRITEMODE_A : String := "NORMAL";
WRITEMODE_B : String := "NORMAL";
GSR : String := "ENABLED";
initval_00 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_01 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_02 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_03 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_04 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_05 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_06 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_07 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_08 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_09 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0a : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0b : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0c : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0d : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0e : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0f : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_10 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_11 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_12 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_13 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_14 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_15 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_16 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_17 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_18 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_19 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1a : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1b : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1c : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1d : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1e : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1f : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"
);
PORT(
dia0, dia1, dia2, dia3, dia4, dia5, dia6, dia7, dia8 : in std_logic := 'X';
dia9, dia10, dia11, dia12, dia13, dia14, dia15, dia16, dia17 : in std_logic := 'X';
ada0, ada1, ada2, ada3, ada4, ada5, ada6, ada7, ada8 : in std_logic := 'X';
ada9, ada10, ada11, ada12 : in std_logic := 'X';
cea, clka, wea, csa0, csa1, csa2, rsta : in std_logic := 'X';
dib0, dib1, dib2, dib3, dib4, dib5, dib6, dib7, dib8 : in std_logic := 'X';
dib9, dib10, dib11, dib12, dib13, dib14, dib15, dib16, dib17 : in std_logic := 'X';
adb0, adb1, adb2, adb3, adb4, adb5, adb6, adb7, adb8 : in std_logic := 'X';
adb9, adb10, adb11, adb12 : in std_logic := 'X';
ceb, clkb, web, csb0, csb1, csb2, rstb : in std_logic := 'X';
doa0, doa1, doa2, doa3, doa4, doa5, doa6, doa7, doa8 : out std_logic := 'X';
doa9, doa10, doa11, doa12, doa13, doa14, doa15, doa16, doa17 : out std_logic := 'X';
dob0, dob1, dob2, dob3, dob4, dob5, dob6, dob7, dob8 : out std_logic := 'X';
dob9, dob10, dob11, dob12, dob13, dob14, dob15, dob16, dob17 : out std_logic := 'X'
);
END COMPONENT;
signal vcc, gnd : std_ulogic;
begin
vcc <= '1'; gnd <= '0';
u0: DP8KA
generic map (CSDECODE_B=>"000", CSDECODE_A=>"000",
WRITEMODE_B=>"NORMAL", WRITEMODE_A=>"NORMAL",
GSR=>"DISABLED", RESETMODE=>"ASYNC", REGMODE_B=>"NOREG",
REGMODE_A=>"NOREG", DATA_WIDTH_B=> 2, DATA_WIDTH_A=> 2)
port map (CEA=>ClockEnA, CLKA=>ClockA, WEA=>WrA, CSA0=>gnd,
CSA1=>gnd, CSA2=>gnd, RSTA=>gnd,
CEB=>ClockEnB, CLKB=>ClockB, WEB=>WrB, CSB0=>gnd,
CSB1=>gnd, CSB2=>gnd, RSTB=>gnd,
DIA0=>gnd, DIA1=>DataInA(0), DIA2=>gnd,
DIA3=>gnd, DIA4=>gnd, DIA5=>gnd,
DIA6=>gnd, DIA7=>gnd, DIA8=>gnd,
DIA9=>gnd, DIA10=>gnd, DIA11=>DataInA(1),
DIA12=>gnd, DIA13=>gnd, DIA14=>gnd,
DIA15=>gnd, DIA16=>gnd, DIA17=>gnd,
ADA0=>vcc, ADA1=>AddressA(0), ADA2=>AddressA(1),
ADA3=>AddressA(2), ADA4=>AddressA(3), ADA5=>AddressA(4),
ADA6=>AddressA(6), ADA7=>AddressA(6), ADA8=>AddressA(7),
ADA9=>AddressA(8), ADA10=>AddressA(9), ADA11=>AddressA(10),
ADA12=>AddressA(11), DIB0=>gnd, DIB1=>DataInB(0),
DIB2=>gnd, DIB3=>gnd, DIB4=>gnd,
DIB5=>gnd, DIB6=>gnd, DIB7=>gnd,
DIB8=>gnd, DIB9=>gnd, DIB10=>gnd,
DIB11=>DataInB(1), DIB12=>gnd, DIB13=>gnd,
DIB14=>gnd, DIB15=>gnd, DIB16=>gnd,
DIB17=>gnd, ADB0=>vcc, ADB1=>AddressB(0),
ADB2=>AddressB(1), ADB3=>AddressB(2), ADB4=>AddressB(3),
ADB5=>AddressB(4), ADB6=>AddressB(5), ADB7=>AddressB(6),
ADB8=>AddressB(7), ADB9=>AddressB(8), ADB10=>AddressB(9),
ADB11=>AddressB(10), ADB12=>AddressB(11), DOA0=>QA(1),
DOA1=>QA(0), DOA2=>open, DOA3=>open, DOA4=>open,
DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open,
DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open,
DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open,
DOA17=>open, DOB0=>QB(1), DOB1=>QB(0), DOB2=>open,
DOB3=>open, DOB4=>open, DOB5=>open, DOB6=>open,
DOB7=>open, DOB8=>open, DOB9=>open, DOB10=>open,
DOB11=>open, DOB12=>open, DOB13=>open, DOB14=>open,
DOB15=>open, DOB16=>open, DOB17=>open);
end;
library ieee;
use ieee.std_logic_1164.all;
-- pragma translate_off
library ec;
use ec.dp8ka;
-- pragma translate_on
entity EC_RAMB8_S4_S4 is
port (
DataInA: in std_logic_vector(3 downto 0);
DataInB: in std_logic_vector(3 downto 0);
AddressA: in std_logic_vector(10 downto 0);
AddressB: in std_logic_vector(10 downto 0);
ClockA: in std_logic;
ClockB: in std_logic;
ClockEnA: in std_logic;
ClockEnB: in std_logic;
WrA: in std_logic;
WrB: in std_logic;
QA: out std_logic_vector(3 downto 0);
QB: out std_logic_vector(3 downto 0));
end;
architecture Structure of EC_RAMB8_S4_S4 is
COMPONENT dp8ka
GENERIC(
DATA_WIDTH_A : in Integer := 18;
DATA_WIDTH_B : in Integer := 18;
REGMODE_A : String := "NOREG";
REGMODE_B : String := "NOREG";
RESETMODE : String := "ASYNC";
CSDECODE_A : String := "000";
CSDECODE_B : String := "000";
WRITEMODE_A : String := "NORMAL";
WRITEMODE_B : String := "NORMAL";
GSR : String := "ENABLED";
initval_00 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_01 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_02 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_03 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_04 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_05 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_06 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_07 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_08 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_09 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0a : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0b : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0c : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0d : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0e : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0f : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_10 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_11 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_12 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_13 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_14 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_15 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_16 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_17 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_18 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_19 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1a : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1b : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1c : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1d : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1e : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1f : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"
);
PORT(
dia0, dia1, dia2, dia3, dia4, dia5, dia6, dia7, dia8 : in std_logic := 'X';
dia9, dia10, dia11, dia12, dia13, dia14, dia15, dia16, dia17 : in std_logic := 'X';
ada0, ada1, ada2, ada3, ada4, ada5, ada6, ada7, ada8 : in std_logic := 'X';
ada9, ada10, ada11, ada12 : in std_logic := 'X';
cea, clka, wea, csa0, csa1, csa2, rsta : in std_logic := 'X';
dib0, dib1, dib2, dib3, dib4, dib5, dib6, dib7, dib8 : in std_logic := 'X';
dib9, dib10, dib11, dib12, dib13, dib14, dib15, dib16, dib17 : in std_logic := 'X';
adb0, adb1, adb2, adb3, adb4, adb5, adb6, adb7, adb8 : in std_logic := 'X';
adb9, adb10, adb11, adb12 : in std_logic := 'X';
ceb, clkb, web, csb0, csb1, csb2, rstb : in std_logic := 'X';
doa0, doa1, doa2, doa3, doa4, doa5, doa6, doa7, doa8 : out std_logic := 'X';
doa9, doa10, doa11, doa12, doa13, doa14, doa15, doa16, doa17 : out std_logic := 'X';
dob0, dob1, dob2, dob3, dob4, dob5, dob6, dob7, dob8 : out std_logic := 'X';
dob9, dob10, dob11, dob12, dob13, dob14, dob15, dob16, dob17 : out std_logic := 'X'
);
END COMPONENT;
signal vcc, gnd : std_ulogic;
begin
vcc <= '1'; gnd <= '0';
u0: DP8KA
generic map (CSDECODE_B=>"000", CSDECODE_A=>"000",
WRITEMODE_B=>"NORMAL", WRITEMODE_A=>"NORMAL",
GSR=>"DISABLED", RESETMODE=>"ASYNC", REGMODE_B=>"NOREG",
REGMODE_A=>"NOREG", DATA_WIDTH_B=> 4, DATA_WIDTH_A=> 4)
port map (CEA=>ClockEnA, CLKA=>ClockA, WEA=>WrA, CSA0=>gnd,
CSA1=>gnd, CSA2=>gnd, RSTA=>gnd,
CEB=>ClockEnB, CLKB=>ClockB, WEB=>WrB, CSB0=>gnd,
CSB1=>gnd, CSB2=>gnd, RSTB=>gnd,
DIA0=>DataInA(0), DIA1=>DataInA(1), DIA2=>DataInA(2),
DIA3=>DataInA(3), DIA4=>gnd, DIA5=>gnd,
DIA6=>gnd, DIA7=>gnd, DIA8=>gnd,
DIA9=>gnd, DIA10=>gnd, DIA11=>gnd,
DIA12=>gnd, DIA13=>gnd, DIA14=>gnd,
DIA15=>gnd, DIA16=>gnd, DIA17=>gnd,
ADA0=>vcc, ADA1=>vcc, ADA2=>AddressA(0),
ADA3=>AddressA(1), ADA4=>AddressA(2), ADA5=>AddressA(3),
ADA6=>AddressA(4), ADA7=>AddressA(5), ADA8=>AddressA(6),
ADA9=>AddressA(7), ADA10=>AddressA(8), ADA11=>AddressA(9),
ADA12=>AddressA(10), DIB0=>DataInB(0), DIB1=>DataInB(1),
DIB2=>DataInB(2), DIB3=>DataInB(3), DIB4=>gnd,
DIB5=>gnd, DIB6=>gnd, DIB7=>gnd,
DIB8=>gnd, DIB9=>gnd, DIB10=>gnd,
DIB11=>gnd, DIB12=>gnd, DIB13=>gnd,
DIB14=>gnd, DIB15=>gnd, DIB16=>gnd,
DIB17=>gnd, ADB0=>vcc, ADB1=>vcc,
ADB2=>AddressB(0), ADB3=>AddressB(1), ADB4=>AddressB(2),
ADB5=>AddressB(3), ADB6=>AddressB(4), ADB7=>AddressB(5),
ADB8=>AddressB(6), ADB9=>AddressB(7), ADB10=>AddressB(8),
ADB11=>AddressB(9), ADB12=>AddressB(10), DOA0=>QA(0),
DOA1=>QA(1), DOA2=>QA(2), DOA3=>QA(3), DOA4=>open,
DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open,
DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open,
DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open,
DOA17=>open, DOB0=>QB(0), DOB1=>QB(1), DOB2=>QB(2),
DOB3=>QB(3), DOB4=>open, DOB5=>open, DOB6=>open,
DOB7=>open, DOB8=>open, DOB9=>open, DOB10=>open,
DOB11=>open, DOB12=>open, DOB13=>open, DOB14=>open,
DOB15=>open, DOB16=>open, DOB17=>open);
end;
library ieee;
use ieee.std_logic_1164.all;
-- pragma translate_off
library ec;
use ec.dp8ka;
-- pragma translate_on
entity EC_RAMB8_S9_S9 is
port (
DataInA: in std_logic_vector(8 downto 0);
DataInB: in std_logic_vector(8 downto 0);
AddressA: in std_logic_vector(9 downto 0);
AddressB: in std_logic_vector(9 downto 0);
ClockA: in std_logic;
ClockB: in std_logic;
ClockEnA: in std_logic;
ClockEnB: in std_logic;
WrA: in std_logic;
WrB: in std_logic;
QA: out std_logic_vector(8 downto 0);
QB: out std_logic_vector(8 downto 0));
end;
architecture Structure of EC_RAMB8_S9_S9 is
COMPONENT dp8ka
GENERIC(
DATA_WIDTH_A : in Integer := 18;
DATA_WIDTH_B : in Integer := 18;
REGMODE_A : String := "NOREG";
REGMODE_B : String := "NOREG";
RESETMODE : String := "ASYNC";
CSDECODE_A : String := "000";
CSDECODE_B : String := "000";
WRITEMODE_A : String := "NORMAL";
WRITEMODE_B : String := "NORMAL";
GSR : String := "ENABLED";
initval_00 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_01 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_02 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_03 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_04 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_05 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_06 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_07 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_08 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_09 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0a : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0b : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0c : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0d : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0e : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0f : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_10 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_11 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_12 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_13 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_14 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_15 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_16 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_17 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_18 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_19 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1a : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1b : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1c : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1d : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1e : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1f : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"
);
PORT(
dia0, dia1, dia2, dia3, dia4, dia5, dia6, dia7, dia8 : in std_logic := 'X';
dia9, dia10, dia11, dia12, dia13, dia14, dia15, dia16, dia17 : in std_logic := 'X';
ada0, ada1, ada2, ada3, ada4, ada5, ada6, ada7, ada8 : in std_logic := 'X';
ada9, ada10, ada11, ada12 : in std_logic := 'X';
cea, clka, wea, csa0, csa1, csa2, rsta : in std_logic := 'X';
dib0, dib1, dib2, dib3, dib4, dib5, dib6, dib7, dib8 : in std_logic := 'X';
dib9, dib10, dib11, dib12, dib13, dib14, dib15, dib16, dib17 : in std_logic := 'X';
adb0, adb1, adb2, adb3, adb4, adb5, adb6, adb7, adb8 : in std_logic := 'X';
adb9, adb10, adb11, adb12 : in std_logic := 'X';
ceb, clkb, web, csb0, csb1, csb2, rstb : in std_logic := 'X';
doa0, doa1, doa2, doa3, doa4, doa5, doa6, doa7, doa8 : out std_logic := 'X';
doa9, doa10, doa11, doa12, doa13, doa14, doa15, doa16, doa17 : out std_logic := 'X';
dob0, dob1, dob2, dob3, dob4, dob5, dob6, dob7, dob8 : out std_logic := 'X';
dob9, dob10, dob11, dob12, dob13, dob14, dob15, dob16, dob17 : out std_logic := 'X'
);
END COMPONENT;
signal vcc, gnd : std_ulogic;
begin
vcc <= '1'; gnd <= '0';
u0: DP8KA
generic map (CSDECODE_B=>"000", CSDECODE_A=>"000",
WRITEMODE_B=>"NORMAL", WRITEMODE_A=>"NORMAL",
GSR=>"DISABLED", RESETMODE=>"ASYNC", REGMODE_B=>"NOREG",
REGMODE_A=>"NOREG", DATA_WIDTH_B=> 9, DATA_WIDTH_A=> 9)
port map (CEA=>ClockEnA, CLKA=>ClockA, WEA=>WrA, CSA0=>gnd,
CSA1=>gnd, CSA2=>gnd, RSTA=>gnd,
CEB=>ClockEnB, CLKB=>ClockB, WEB=>WrB, CSB0=>gnd,
CSB1=>gnd, CSB2=>gnd, RSTB=>gnd,
DIA0=>DataInA(0), DIA1=>DataInA(1), DIA2=>DataInA(2),
DIA3=>DataInA(3), DIA4=>DataInA(4), DIA5=>DataInA(5),
DIA6=>DataInA(6), DIA7=>DataInA(7), DIA8=>DataInA(8),
DIA9=>gnd, DIA10=>gnd, DIA11=>gnd,
DIA12=>gnd, DIA13=>gnd, DIA14=>gnd,
DIA15=>gnd, DIA16=>gnd, DIA17=>gnd,
ADA0=>vcc, ADA1=>vcc, ADA2=>gnd,
ADA3=>AddressA(0), ADA4=>AddressA(1), ADA5=>AddressA(2),
ADA6=>AddressA(3), ADA7=>AddressA(4), ADA8=>AddressA(5),
ADA9=>AddressA(6), ADA10=>AddressA(7), ADA11=>AddressA(8),
ADA12=>AddressA(9), DIB0=>DataInB(0), DIB1=>DataInB(1),
DIB2=>DataInB(2), DIB3=>DataInB(3), DIB4=>DataInB(4),
DIB5=>DataInB(5), DIB6=>DataInB(6), DIB7=>DataInB(7),
DIB8=>DataInB(8), DIB9=>gnd, DIB10=>gnd,
DIB11=>gnd, DIB12=>gnd, DIB13=>gnd,
DIB14=>gnd, DIB15=>gnd, DIB16=>gnd,
DIB17=>gnd, ADB0=>vcc, ADB1=>vcc,
ADB2=>gnd, ADB3=>AddressB(0), ADB4=>AddressB(1),
ADB5=>AddressB(2), ADB6=>AddressB(3), ADB7=>AddressB(4),
ADB8=>AddressB(5), ADB9=>AddressB(6), ADB10=>AddressB(7),
ADB11=>AddressB(8), ADB12=>AddressB(9), DOA0=>QA(0),
DOA1=>QA(1), DOA2=>QA(2), DOA3=>QA(3), DOA4=>QA(4),
DOA5=>QA(5), DOA6=>QA(6), DOA7=>QA(7), DOA8=>QA(8),
DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open,
DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open,
DOA17=>open, DOB0=>QB(0), DOB1=>QB(1), DOB2=>QB(2),
DOB3=>QB(3), DOB4=>QB(4), DOB5=>QB(5), DOB6=>QB(6),
DOB7=>QB(7), DOB8=>QB(8), DOB9=>open, DOB10=>open,
DOB11=>open, DOB12=>open, DOB13=>open, DOB14=>open,
DOB15=>open, DOB16=>open, DOB17=>open);
end;
library ieee;
use ieee.std_logic_1164.all;
-- pragma translate_off
library ec;
use ec.dp8ka;
-- pragma translate_on
entity EC_RAMB8_S18_S18 is
port (
DataInA: in std_logic_vector(17 downto 0);
DataInB: in std_logic_vector(17 downto 0);
AddressA: in std_logic_vector(8 downto 0);
AddressB: in std_logic_vector(8 downto 0);
ClockA: in std_logic;
ClockB: in std_logic;
ClockEnA: in std_logic;
ClockEnB: in std_logic;
WrA: in std_logic;
WrB: in std_logic;
QA: out std_logic_vector(17 downto 0);
QB: out std_logic_vector(17 downto 0));
end;
architecture Structure of EC_RAMB8_S18_S18 is
COMPONENT dp8ka
GENERIC(
DATA_WIDTH_A : in Integer := 18;
DATA_WIDTH_B : in Integer := 18;
REGMODE_A : String := "NOREG";
REGMODE_B : String := "NOREG";
RESETMODE : String := "ASYNC";
CSDECODE_A : String := "000";
CSDECODE_B : String := "000";
WRITEMODE_A : String := "NORMAL";
WRITEMODE_B : String := "NORMAL";
GSR : String := "ENABLED";
initval_00 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_01 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_02 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_03 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_04 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_05 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_06 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_07 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_08 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_09 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0a : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0b : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0c : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0d : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0e : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0f : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_10 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_11 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_12 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_13 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_14 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_15 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_16 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_17 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_18 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_19 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1a : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1b : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1c : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1d : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1e : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1f : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"
);
PORT(
dia0, dia1, dia2, dia3, dia4, dia5, dia6, dia7, dia8 : in std_logic := 'X';
dia9, dia10, dia11, dia12, dia13, dia14, dia15, dia16, dia17 : in std_logic := 'X';
ada0, ada1, ada2, ada3, ada4, ada5, ada6, ada7, ada8 : in std_logic := 'X';
ada9, ada10, ada11, ada12 : in std_logic := 'X';
cea, clka, wea, csa0, csa1, csa2, rsta : in std_logic := 'X';
dib0, dib1, dib2, dib3, dib4, dib5, dib6, dib7, dib8 : in std_logic := 'X';
dib9, dib10, dib11, dib12, dib13, dib14, dib15, dib16, dib17 : in std_logic := 'X';
adb0, adb1, adb2, adb3, adb4, adb5, adb6, adb7, adb8 : in std_logic := 'X';
adb9, adb10, adb11, adb12 : in std_logic := 'X';
ceb, clkb, web, csb0, csb1, csb2, rstb : in std_logic := 'X';
doa0, doa1, doa2, doa3, doa4, doa5, doa6, doa7, doa8 : out std_logic := 'X';
doa9, doa10, doa11, doa12, doa13, doa14, doa15, doa16, doa17 : out std_logic := 'X';
dob0, dob1, dob2, dob3, dob4, dob5, dob6, dob7, dob8 : out std_logic := 'X';
dob9, dob10, dob11, dob12, dob13, dob14, dob15, dob16, dob17 : out std_logic := 'X'
);
END COMPONENT;
signal vcc, gnd : std_ulogic;
begin
vcc <= '1'; gnd <= '0';
u0: DP8KA
generic map (CSDECODE_B=>"000", CSDECODE_A=>"000",
WRITEMODE_B=>"NORMAL", WRITEMODE_A=>"NORMAL",
GSR=>"DISABLED", RESETMODE=>"ASYNC", REGMODE_B=>"NOREG",
REGMODE_A=>"NOREG", DATA_WIDTH_B=> 18, DATA_WIDTH_A=> 18)
port map (CEA=>ClockEnA, CLKA=>ClockA, WEA=>WrA, CSA0=>gnd,
CSA1=>gnd, CSA2=>gnd, RSTA=>gnd,
CEB=>ClockEnB, CLKB=>ClockB, WEB=>WrB, CSB0=>gnd,
CSB1=>gnd, CSB2=>gnd, RSTB=>gnd,
DIA0=>DataInA(0), DIA1=>DataInA(1), DIA2=>DataInA(2),
DIA3=>DataInA(3), DIA4=>DataInA(4), DIA5=>DataInA(5),
DIA6=>DataInA(6), DIA7=>DataInA(7), DIA8=>DataInA(8),
DIA9=>DataInA(9), DIA10=>DataInA(10), DIA11=>DataInA(11),
DIA12=>DataInA(12), DIA13=>DataInA(13), DIA14=>DataInA(14),
DIA15=>DataInA(15), DIA16=>DataInA(16), DIA17=>DataInA(17),
ADA0=>vcc, ADA1=>vcc, ADA2=>gnd,
ADA3=>gnd, ADA4=>AddressA(0), ADA5=>AddressA(1),
ADA6=>AddressA(2), ADA7=>AddressA(3), ADA8=>AddressA(4),
ADA9=>AddressA(5), ADA10=>AddressA(6), ADA11=>AddressA(7),
ADA12=>AddressA(8), DIB0=>DataInB(0), DIB1=>DataInB(1),
DIB2=>DataInB(2), DIB3=>DataInB(3), DIB4=>DataInB(4),
DIB5=>DataInB(5), DIB6=>DataInB(6), DIB7=>DataInB(7),
DIB8=>DataInB(8), DIB9=>DataInB(9), DIB10=>DataInB(10),
DIB11=>DataInB(11), DIB12=>DataInB(12), DIB13=>DataInB(13),
DIB14=>DataInB(14), DIB15=>DataInB(15), DIB16=>DataInB(16),
DIB17=>DataInB(17), ADB0=>vcc, ADB1=>vcc,
ADB2=>gnd, ADB3=>gnd, ADB4=>AddressB(0),
ADB5=>AddressB(1), ADB6=>AddressB(2), ADB7=>AddressB(3),
ADB8=>AddressB(4), ADB9=>AddressB(5), ADB10=>AddressB(6),
ADB11=>AddressB(7), ADB12=>AddressB(8), DOA0=>QA(0),
DOA1=>QA(1), DOA2=>QA(2), DOA3=>QA(3), DOA4=>QA(4),
DOA5=>QA(5), DOA6=>QA(6), DOA7=>QA(7), DOA8=>QA(8),
DOA9=>QA(9), DOA10=>QA(10), DOA11=>QA(11), DOA12=>QA(12),
DOA13=>QA(13), DOA14=>QA(14), DOA15=>QA(15), DOA16=>QA(16),
DOA17=>QA(17), DOB0=>QB(0), DOB1=>QB(1), DOB2=>QB(2),
DOB3=>QB(3), DOB4=>QB(4), DOB5=>QB(5), DOB6=>QB(6),
DOB7=>QB(7), DOB8=>QB(8), DOB9=>QB(9), DOB10=>QB(10),
DOB11=>QB(11), DOB12=>QB(12), DOB13=>QB(13), DOB14=>QB(14),
DOB15=>QB(15), DOB16=>QB(16), DOB17=>QB(17));
end;
library ieee;
use ieee.std_logic_1164.all;
-- pragma translate_off
library ec;
use ec.sp8ka;
-- pragma translate_on
entity EC_RAMB8_S1 is
port (
clk, en, we : in std_ulogic;
address : in std_logic_vector (12 downto 0);
data : in std_logic_vector (0 downto 0);
q : out std_logic_vector (0 downto 0));
end;
architecture behav of EC_RAMB8_S1 is
COMPONENT sp8ka
GENERIC(
DATA_WIDTH : in Integer := 18;
REGMODE : String := "NOREG";
RESETMODE : String := "ASYNC";
CSDECODE : String := "000";
WRITEMODE : String := "NORMAL";
GSR : String := "ENABLED";
initval_00 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_01 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_02 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_03 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_04 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_05 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_06 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_07 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_08 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_09 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0a : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0b : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0c : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0d : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0e : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0f : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_10 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_11 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_12 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_13 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_14 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_15 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_16 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_17 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_18 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_19 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1a : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1b : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1c : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1d : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1e : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1f : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"
);
PORT(
di0, di1, di2, di3, di4, di5, di6, di7, di8 : in std_logic := 'X';
di9, di10, di11, di12, di13, di14, di15, di16, di17 : in std_logic := 'X';
ad0, ad1, ad2, ad3, ad4, ad5, ad6, ad7, ad8 : in std_logic := 'X';
ad9, ad10, ad11, ad12 : in std_logic := 'X';
ce, clk, we, cs0, cs1, cs2, rst : in std_logic := 'X';
do0, do1, do2, do3, do4, do5, do6, do7, do8 : out std_logic := 'X';
do9, do10, do11, do12, do13, do14, do15, do16, do17 : out std_logic := 'X'
);
END COMPONENT;
signal vcc, gnd : std_ulogic;
begin
vcc <= '1'; gnd <= '0';
u0: SP8KA
generic map (CSDECODE=>"000", GSR=>"DISABLED",
WRITEMODE=>"WRITETHROUGH", RESETMODE=>"ASYNC",
REGMODE=>"NOREG", DATA_WIDTH=> 1)
port map (CE=>En, CLK=>Clk, WE=>WE, CS0=>gnd,
CS1=>gnd, CS2=>gnd, RST=>gnd, DI0=>gnd,
DI1=>gnd, DI2=>gnd, DI3=>gnd, DI4=>gnd,
DI5=>gnd, DI6=>gnd, DI7=>gnd, DI8=>gnd,
DI9=>gnd, DI10=>gnd, DI11=>Data(0),
DI12=>gnd, DI13=>gnd, DI14=>gnd,
DI15=>gnd, DI16=>gnd, DI17=>gnd,
AD0=>Address(0), AD1=>Address(1), AD2=>Address(2),
AD3=>Address(3), AD4=>Address(4), AD5=>Address(5),
AD6=>Address(6), AD7=>Address(7), AD8=>Address(8),
AD9=>Address(9), AD10=>Address(10), AD11=>Address(11),
AD12=>Address(12), DO0=>Q(0), DO1=>open, DO2=>open, DO3=>open,
DO4=>open, DO5=>open, DO6=>open, DO7=>open, DO8=>open,
DO9=>open, DO10=>open, DO11=>open, DO12=>open, DO13=>open,
DO14=>open, DO15=>open, DO16=>open, DO17=>open);
end;
library ieee;
use ieee.std_logic_1164.all;
-- pragma translate_off
library ec;
use ec.sp8ka;
-- pragma translate_on
entity EC_RAMB8_S2 is
port (
clk, en, we : in std_ulogic;
address : in std_logic_vector (11 downto 0);
data : in std_logic_vector (1 downto 0);
q : out std_logic_vector (1 downto 0));
end;
architecture behav of EC_RAMB8_S2 is
COMPONENT sp8ka
GENERIC(
DATA_WIDTH : in Integer := 18;
REGMODE : String := "NOREG";
RESETMODE : String := "ASYNC";
CSDECODE : String := "000";
WRITEMODE : String := "NORMAL";
GSR : String := "ENABLED";
initval_00 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_01 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_02 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_03 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_04 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_05 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_06 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_07 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_08 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_09 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0a : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0b : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0c : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0d : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0e : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0f : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_10 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_11 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_12 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_13 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_14 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_15 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_16 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_17 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_18 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_19 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1a : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1b : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1c : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1d : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1e : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1f : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"
);
PORT(
di0, di1, di2, di3, di4, di5, di6, di7, di8 : in std_logic := 'X';
di9, di10, di11, di12, di13, di14, di15, di16, di17 : in std_logic := 'X';
ad0, ad1, ad2, ad3, ad4, ad5, ad6, ad7, ad8 : in std_logic := 'X';
ad9, ad10, ad11, ad12 : in std_logic := 'X';
ce, clk, we, cs0, cs1, cs2, rst : in std_logic := 'X';
do0, do1, do2, do3, do4, do5, do6, do7, do8 : out std_logic := 'X';
do9, do10, do11, do12, do13, do14, do15, do16, do17 : out std_logic := 'X'
);
END COMPONENT;
signal vcc, gnd : std_ulogic;
begin
vcc <= '1'; gnd <= '0';
u0: SP8KA
generic map (CSDECODE=>"000", GSR=>"DISABLED",
WRITEMODE=>"WRITETHROUGH", RESETMODE=>"ASYNC",
REGMODE=>"NOREG", DATA_WIDTH=> 2)
port map (CE=>En, CLK=>Clk, WE=>WE, CS0=>gnd,
CS1=>gnd, CS2=>gnd, RST=>gnd, DI0=>gnd,
DI1=>Data(0), DI2=>gnd, DI3=>gnd, DI4=>gnd,
DI5=>gnd, DI6=>gnd, DI7=>gnd, DI8=>gnd,
DI9=>gnd, DI10=>gnd, DI11=>Data(1),
DI12=>gnd, DI13=>gnd, DI14=>gnd,
DI15=>gnd, DI16=>gnd, DI17=>gnd,
AD0=>gnd, AD1=>Address(0), AD2=>Address(1),
AD3=>Address(2), AD4=>Address(3), AD5=>Address(4),
AD6=>Address(5), AD7=>Address(6), AD8=>Address(7),
AD9=>Address(8), AD10=>Address(9), AD11=>Address(10),
AD12=>Address(11), DO0=>Q(1), DO1=>Q(0), DO2=>open, DO3=>open,
DO4=>open, DO5=>open, DO6=>open, DO7=>open, DO8=>open,
DO9=>open, DO10=>open, DO11=>open, DO12=>open, DO13=>open,
DO14=>open, DO15=>open, DO16=>open, DO17=>open);
end;
library ieee;
use ieee.std_logic_1164.all;
-- pragma translate_off
library ec;
use ec.sp8ka;
-- pragma translate_on
entity EC_RAMB8_S4 is
port (
clk, en, we : in std_ulogic;
address : in std_logic_vector (10 downto 0);
data : in std_logic_vector (3 downto 0);
q : out std_logic_vector (3 downto 0));
end;
architecture behav of EC_RAMB8_S4 is
COMPONENT sp8ka
GENERIC(
DATA_WIDTH : in Integer := 18;
REGMODE : String := "NOREG";
RESETMODE : String := "ASYNC";
CSDECODE : String := "000";
WRITEMODE : String := "NORMAL";
GSR : String := "ENABLED";
initval_00 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_01 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_02 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_03 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_04 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_05 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_06 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_07 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_08 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_09 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0a : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0b : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0c : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0d : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0e : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0f : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_10 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_11 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_12 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_13 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_14 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_15 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_16 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_17 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_18 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_19 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1a : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1b : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1c : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1d : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1e : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1f : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"
);
PORT(
di0, di1, di2, di3, di4, di5, di6, di7, di8 : in std_logic := 'X';
di9, di10, di11, di12, di13, di14, di15, di16, di17 : in std_logic := 'X';
ad0, ad1, ad2, ad3, ad4, ad5, ad6, ad7, ad8 : in std_logic := 'X';
ad9, ad10, ad11, ad12 : in std_logic := 'X';
ce, clk, we, cs0, cs1, cs2, rst : in std_logic := 'X';
do0, do1, do2, do3, do4, do5, do6, do7, do8 : out std_logic := 'X';
do9, do10, do11, do12, do13, do14, do15, do16, do17 : out std_logic := 'X'
);
END COMPONENT;
signal vcc, gnd : std_ulogic;
begin
vcc <= '1'; gnd <= '0';
u0: SP8KA
generic map (CSDECODE=>"000", GSR=>"DISABLED",
WRITEMODE=>"WRITETHROUGH", RESETMODE=>"ASYNC",
REGMODE=>"NOREG", DATA_WIDTH=> 4)
port map (CE=>En, CLK=>Clk, WE=>WE, CS0=>gnd,
CS1=>gnd, CS2=>gnd, RST=>gnd, DI0=>Data(0),
DI1=>Data(1), DI2=>Data(2), DI3=>Data(3), DI4=>gnd,
DI5=>gnd, DI6=>gnd, DI7=>gnd, DI8=>gnd,
DI9=>gnd, DI10=>gnd, DI11=>gnd,
DI12=>gnd, DI13=>gnd, DI14=>gnd,
DI15=>gnd, DI16=>gnd, DI17=>gnd,
AD0=>gnd, AD1=>gnd, AD2=>Address(0),
AD3=>Address(1), AD4=>Address(2), AD5=>Address(3),
AD6=>Address(4), AD7=>Address(5), AD8=>Address(6),
AD9=>Address(7), AD10=>Address(8), AD11=>Address(9),
AD12=>Address(10), DO0=>Q(0), DO1=>Q(1), DO2=>Q(2), DO3=>Q(3),
DO4=>open, DO5=>open, DO6=>open, DO7=>open, DO8=>open,
DO9=>open, DO10=>open, DO11=>open, DO12=>open, DO13=>open,
DO14=>open, DO15=>open, DO16=>open, DO17=>open);
end;
library ieee;
use ieee.std_logic_1164.all;
-- pragma translate_off
library ec;
use ec.sp8ka;
-- pragma translate_on
entity EC_RAMB8_S9 is
port (
clk, en, we : in std_ulogic;
address : in std_logic_vector (9 downto 0);
data : in std_logic_vector (8 downto 0);
q : out std_logic_vector (8 downto 0));
end;
architecture behav of EC_RAMB8_S9 is
COMPONENT sp8ka
GENERIC(
DATA_WIDTH : in Integer := 18;
REGMODE : String := "NOREG";
RESETMODE : String := "ASYNC";
CSDECODE : String := "000";
WRITEMODE : String := "NORMAL";
GSR : String := "ENABLED";
initval_00 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_01 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_02 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_03 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_04 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_05 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_06 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_07 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_08 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_09 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0a : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0b : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0c : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0d : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0e : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0f : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_10 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_11 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_12 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_13 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_14 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_15 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_16 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_17 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_18 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_19 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1a : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1b : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1c : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1d : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1e : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1f : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"
);
PORT(
di0, di1, di2, di3, di4, di5, di6, di7, di8 : in std_logic := 'X';
di9, di10, di11, di12, di13, di14, di15, di16, di17 : in std_logic := 'X';
ad0, ad1, ad2, ad3, ad4, ad5, ad6, ad7, ad8 : in std_logic := 'X';
ad9, ad10, ad11, ad12 : in std_logic := 'X';
ce, clk, we, cs0, cs1, cs2, rst : in std_logic := 'X';
do0, do1, do2, do3, do4, do5, do6, do7, do8 : out std_logic := 'X';
do9, do10, do11, do12, do13, do14, do15, do16, do17 : out std_logic := 'X'
);
END COMPONENT;
signal vcc, gnd : std_ulogic;
begin
vcc <= '1'; gnd <= '0';
u0: SP8KA
generic map (CSDECODE=>"000", GSR=>"DISABLED",
WRITEMODE=>"WRITETHROUGH", RESETMODE=>"ASYNC",
REGMODE=>"NOREG", DATA_WIDTH=> 9)
port map (CE=>En, CLK=>Clk, WE=>WE, CS0=>gnd,
CS1=>gnd, CS2=>gnd, RST=>gnd, DI0=>Data(0),
DI1=>Data(1), DI2=>Data(2), DI3=>Data(3), DI4=>Data(4),
DI5=>Data(5), DI6=>Data(6), DI7=>Data(7), DI8=>Data(8),
DI9=>gnd, DI10=>gnd, DI11=>gnd,
DI12=>gnd, DI13=>gnd, DI14=>gnd,
DI15=>gnd, DI16=>gnd, DI17=>gnd,
AD0=>gnd, AD1=>gnd, AD2=>gnd,
AD3=>Address(0), AD4=>Address(1), AD5=>Address(2),
AD6=>Address(3), AD7=>Address(4), AD8=>Address(5),
AD9=>Address(6), AD10=>Address(7), AD11=>Address(8),
AD12=>Address(9), DO0=>Q(0), DO1=>Q(1), DO2=>Q(2), DO3=>Q(3),
DO4=>Q(4), DO5=>Q(5), DO6=>Q(6), DO7=>Q(7), DO8=>Q(8),
DO9=>open, DO10=>open, DO11=>open, DO12=>open, DO13=>open,
DO14=>open, DO15=>open, DO16=>open, DO17=>open);
end;
library ieee;
use ieee.std_logic_1164.all;
-- pragma translate_off
library ec;
use ec.sp8ka;
-- pragma translate_on
entity EC_RAMB8_S18 is
port (
clk, en, we : in std_ulogic;
address : in std_logic_vector (8 downto 0);
data : in std_logic_vector (17 downto 0);
q : out std_logic_vector (17 downto 0));
end;
architecture behav of EC_RAMB8_S18 is
COMPONENT sp8ka
GENERIC(
DATA_WIDTH : in Integer := 18;
REGMODE : String := "NOREG";
RESETMODE : String := "ASYNC";
CSDECODE : String := "000";
WRITEMODE : String := "NORMAL";
GSR : String := "ENABLED";
initval_00 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_01 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_02 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_03 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_04 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_05 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_06 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_07 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_08 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_09 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0a : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0b : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0c : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0d : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0e : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0f : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_10 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_11 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_12 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_13 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_14 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_15 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_16 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_17 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_18 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_19 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1a : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1b : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1c : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1d : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1e : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1f : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"
);
PORT(
di0, di1, di2, di3, di4, di5, di6, di7, di8 : in std_logic := 'X';
di9, di10, di11, di12, di13, di14, di15, di16, di17 : in std_logic := 'X';
ad0, ad1, ad2, ad3, ad4, ad5, ad6, ad7, ad8 : in std_logic := 'X';
ad9, ad10, ad11, ad12 : in std_logic := 'X';
ce, clk, we, cs0, cs1, cs2, rst : in std_logic := 'X';
do0, do1, do2, do3, do4, do5, do6, do7, do8 : out std_logic := 'X';
do9, do10, do11, do12, do13, do14, do15, do16, do17 : out std_logic := 'X'
);
END COMPONENT;
signal vcc, gnd : std_ulogic;
begin
vcc <= '1'; gnd <= '0';
u0: SP8KA
generic map (CSDECODE=>"000", GSR=>"DISABLED",
WRITEMODE=>"WRITETHROUGH", RESETMODE=>"ASYNC",
REGMODE=>"NOREG", DATA_WIDTH=> 18)
port map (CE=>En, CLK=>Clk, WE=>WE, CS0=>gnd,
CS1=>gnd, CS2=>gnd, RST=>gnd, DI0=>Data(0),
DI1=>Data(1), DI2=>Data(2), DI3=>Data(3), DI4=>Data(4),
DI5=>Data(5), DI6=>Data(6), DI7=>Data(7), DI8=>Data(8),
DI9=>Data(9), DI10=>Data(10), DI11=>Data(11),
DI12=>Data(12), DI13=>Data(13), DI14=>Data(14),
DI15=>Data(15), DI16=>Data(16), DI17=>Data(17),
AD0=>gnd, AD1=>gnd, AD2=>gnd,
AD3=>gnd, AD4=>Address(0), AD5=>Address(1),
AD6=>Address(2), AD7=>Address(3), AD8=>Address(4),
AD9=>Address(5), AD10=>Address(6), AD11=>Address(7),
AD12=>Address(8), DO0=>Q(0), DO1=>Q(1), DO2=>Q(2), DO3=>Q(3),
DO4=>Q(4), DO5=>Q(5), DO6=>Q(6), DO7=>Q(7), DO8=>Q(8),
DO9=>Q(9), DO10=>Q(10), DO11=>Q(11), DO12=>Q(12), DO13=>Q(13),
DO14=>Q(14), DO15=>Q(15), DO16=>Q(16), DO17=>Q(17));
end;
library ieee;
use ieee.std_logic_1164.all;
-- pragma translate_off
library ec;
use ec.dp8ka;
-- pragma translate_on
entity EC_RAMB8_S36 is
port (
clk, en, we : in std_ulogic;
address : in std_logic_vector (7 downto 0);
data : in std_logic_vector (35 downto 0);
q : out std_logic_vector (35 downto 0));
end;
architecture behav of EC_RAMB8_S36 is
COMPONENT dp8ka
GENERIC(
DATA_WIDTH_A : in Integer := 18;
DATA_WIDTH_B : in Integer := 18;
REGMODE_A : String := "NOREG";
REGMODE_B : String := "NOREG";
RESETMODE : String := "ASYNC";
CSDECODE_A : String := "000";
CSDECODE_B : String := "000";
WRITEMODE_A : String := "NORMAL";
WRITEMODE_B : String := "NORMAL";
GSR : String := "ENABLED";
initval_00 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_01 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_02 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_03 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_04 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_05 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_06 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_07 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_08 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_09 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0a : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0b : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0c : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0d : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0e : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0f : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_10 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_11 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_12 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_13 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_14 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_15 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_16 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_17 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_18 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_19 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1a : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1b : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1c : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1d : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1e : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1f : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"
);
PORT(
dia0, dia1, dia2, dia3, dia4, dia5, dia6, dia7, dia8 : in std_logic := 'X';
dia9, dia10, dia11, dia12, dia13, dia14, dia15, dia16, dia17 : in std_logic := 'X';
ada0, ada1, ada2, ada3, ada4, ada5, ada6, ada7, ada8 : in std_logic := 'X';
ada9, ada10, ada11, ada12 : in std_logic := 'X';
cea, clka, wea, csa0, csa1, csa2, rsta : in std_logic := 'X';
dib0, dib1, dib2, dib3, dib4, dib5, dib6, dib7, dib8 : in std_logic := 'X';
dib9, dib10, dib11, dib12, dib13, dib14, dib15, dib16, dib17 : in std_logic := 'X';
adb0, adb1, adb2, adb3, adb4, adb5, adb6, adb7, adb8 : in std_logic := 'X';
adb9, adb10, adb11, adb12 : in std_logic := 'X';
ceb, clkb, web, csb0, csb1, csb2, rstb : in std_logic := 'X';
doa0, doa1, doa2, doa3, doa4, doa5, doa6, doa7, doa8 : out std_logic := 'X';
doa9, doa10, doa11, doa12, doa13, doa14, doa15, doa16, doa17 : out std_logic := 'X';
dob0, dob1, dob2, dob3, dob4, dob5, dob6, dob7, dob8 : out std_logic := 'X';
dob9, dob10, dob11, dob12, dob13, dob14, dob15, dob16, dob17 : out std_logic := 'X'
);
END COMPONENT;
signal vcc, gnd : std_ulogic;
begin
vcc <= '1'; gnd <= '0';
u0: DP8KA
generic map (CSDECODE_B=>"000", CSDECODE_A=>"000",
WRITEMODE_B=>"NORMAL", WRITEMODE_A=>"NORMAL", GSR=>"DISABLED",
RESETMODE=>"ASYNC", REGMODE_B=>"NOREG", REGMODE_A=>"NOREG",
DATA_WIDTH_B=> 18, DATA_WIDTH_A=> 18)
port map (CEA => en, CLKA => clk, WEA => we, CSA0 => gnd,
CSA1=>gnd, CSA2=>gnd, RSTA=> gnd, CEB=> en,
CLKB=> clk, WEB=> we, CSB0=>gnd, CSB1=>gnd,
CSB2=>gnd, RSTB=>gnd, DIA0=>Data(0), DIA1=>Data(1),
DIA2=>Data(2), DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5),
DIA6=>Data(6), DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9),
DIA10=>Data(10), DIA11=>Data(11), DIA12=>Data(12),
DIA13=>Data(13), DIA14=>Data(14), DIA15=>Data(15),
DIA16=>Data(16), DIA17=>Data(17), ADA0=>vcc,
ADA1=>vcc, ADA2=>vcc, ADA3=>vcc,
ADA4=>Address(0), ADA5=>Address(1), ADA6=>Address(2),
ADA7=>Address(3), ADA8=>Address(4), ADA9=>Address(5),
ADA10=>Address(6), ADA11=>Address(7), ADA12=>gnd,
DIB0=>Data(18), DIB1=>Data(19), DIB2=>Data(20),
DIB3=>Data(21), DIB4=>Data(22), DIB5=>Data(23),
DIB6=>Data(24), DIB7=>Data(25), DIB8=>Data(26),
DIB9=>Data(27), DIB10=>Data(28), DIB11=>Data(29),
DIB12=>Data(30), DIB13=>Data(31), DIB14=>Data(32),
DIB15=>Data(33), DIB16=>Data(34), DIB17=>Data(35),
ADB0=>vcc, ADB1=>vcc, ADB2=>gnd,
ADB3=>gnd, ADB4=>Address(0), ADB5=>Address(1),
ADB6=>Address(2), ADB7=>Address(3), ADB8=>Address(4),
ADB9=>Address(5), ADB10=>Address(6), ADB11=>Address(7),
ADB12=>vcc, DOA0=>Q(0), DOA1=>Q(1), DOA2=>Q(2),
DOA3=>Q(3), DOA4=>Q(4), DOA5=>Q(5), DOA6=>Q(6), DOA7=>Q(7),
DOA8=>Q(8), DOA9=>Q(9), DOA10=>Q(10), DOA11=>Q(11),
DOA12=>Q(12), DOA13=>Q(13), DOA14=>Q(14), DOA15=>Q(15),
DOA16=>Q(16), DOA17=>Q(17), DOB0=>Q(18), DOB1=>Q(19),
DOB2=>Q(20), DOB3=>Q(21), DOB4=>Q(22), DOB5=>Q(23),
DOB6=>Q(24), DOB7=>Q(25), DOB8=>Q(26), DOB9=>Q(27),
DOB10=>Q(28), DOB11=>Q(29), DOB12=>Q(30), DOB13=>Q(31),
DOB14=>Q(32), DOB15=>Q(33), DOB16=>Q(34), DOB17=>Q(35));
end;
library ieee;
use ieee.std_logic_1164.all;
library techmap;
entity ec_syncram is
generic (abits : integer := 9; dbits : integer := 32);
port (
clk : in std_ulogic;
address : in std_logic_vector (abits -1 downto 0);
datain : in std_logic_vector (dbits -1 downto 0);
dataout : out std_logic_vector (dbits -1 downto 0);
enable : in std_ulogic;
write : in std_ulogic
);
end;
architecture behav of ec_syncram is
component EC_RAMB8_S1 port (
clk, en, we : in std_ulogic;
address : in std_logic_vector (12 downto 0);
data : in std_logic_vector (0 downto 0);
q : out std_logic_vector (0 downto 0));
end component;
component EC_RAMB8_S2 port (
clk, en, we : in std_ulogic;
address : in std_logic_vector (11 downto 0);
data : in std_logic_vector (1 downto 0);
q : out std_logic_vector (1 downto 0));
end component;
component EC_RAMB8_S4 port (
clk, en, we : in std_ulogic;
address : in std_logic_vector (10 downto 0);
data : in std_logic_vector (3 downto 0);
q : out std_logic_vector (3 downto 0));
end component;
component EC_RAMB8_S9 port (
clk, en, we : in std_ulogic;
address : in std_logic_vector (9 downto 0);
data : in std_logic_vector (8 downto 0);
q : out std_logic_vector (8 downto 0));
end component;
component EC_RAMB8_S18 port (
clk, en, we : in std_ulogic;
address : in std_logic_vector (8 downto 0);
data : in std_logic_vector (17 downto 0);
q : out std_logic_vector (17 downto 0));
end component;
component EC_RAMB8_S36 port (
clk, en, we : in std_ulogic;
address : in std_logic_vector (7 downto 0);
data : in std_logic_vector (35 downto 0);
q : out std_logic_vector (35 downto 0));
end component;
constant DMAX : integer := dbits+36;
constant AMAX : integer := 13;
signal gnd : std_ulogic;
signal do, di : std_logic_vector(DMAX downto 0);
signal xa, ya : std_logic_vector(AMAX downto 0);
begin
gnd <= '0'; dataout <= do(dbits-1 downto 0); di(dbits-1 downto 0) <= datain;
di(DMAX downto dbits) <= (others => '0'); xa(abits-1 downto 0) <= address;
xa(AMAX downto abits) <= (others => '0'); ya(abits-1 downto 0) <= address;
ya(AMAX downto abits) <= (others => '1');
a8 : if (abits <= 8) generate
x : for i in 0 to ((dbits-1)/36) generate
r : EC_RAMB8_S36 port map ( clk, enable, write, xa(7 downto 0),
di((i+1)*36-1 downto i*36), do((i+1)*36-1 downto i*36));
end generate;
end generate;
a9 : if (abits = 9) generate
x : for i in 0 to ((dbits-1)/18) generate
r : EC_RAMB8_S18 port map ( clk, enable, write, xa(8 downto 0),
di((i+1)*18-1 downto i*18), do((i+1)*18-1 downto i*18));
end generate;
end generate;
a10 : if (abits = 10) generate
x : for i in 0 to ((dbits-1)/9) generate
r : EC_RAMB8_S9 port map ( clk, enable, write, xa(9 downto 0),
di((i+1)*9-1 downto i*9), do((i+1)*9-1 downto i*9));
end generate;
end generate;
a11 : if (abits = 11) generate
x : for i in 0 to ((dbits-1)/4) generate
r : EC_RAMB8_S4 port map ( clk, enable, write, xa(10 downto 0),
di((i+1)*4-1 downto i*4), do((i+1)*4-1 downto i*4));
end generate;
end generate;
a12 : if (abits = 12) generate
x : for i in 0 to ((dbits-1)/2) generate
r : EC_RAMB8_S2 port map ( clk, enable, write, xa(11 downto 0),
di((i+1)*2-1 downto i*2), do((i+1)*2-1 downto i*2));
end generate;
end generate;
a13 : if (abits = 13) generate
x : for i in 0 to ((dbits-1)/1) generate
r : EC_RAMB8_S1 port map ( clk, enable, write, xa(12 downto 0),
di((i+1)*1-1 downto i*1), do((i+1)*1-1 downto i*1));
end generate;
end generate;
-- pragma translate_off
unsup : if (abits > 13) generate
x : process
begin
assert false
report "Lattice EC syncram mapper: unsupported memory configuration!"
severity failure;
wait;
end process;
end generate;
-- pragma translate_on
end;
library ieee;
use ieee.std_logic_1164.all;
library techmap;
entity ec_syncram_dp is
generic (
abits : integer := 4; dbits : integer := 32
);
port (
clk1 : in std_ulogic;
address1 : in std_logic_vector((abits -1) downto 0);
datain1 : in std_logic_vector((dbits -1) downto 0);
dataout1 : out std_logic_vector((dbits -1) downto 0);
enable1 : in std_ulogic;
write1 : in std_ulogic;
clk2 : in std_ulogic;
address2 : in std_logic_vector((abits -1) downto 0);
datain2 : in std_logic_vector((dbits -1) downto 0);
dataout2 : out std_logic_vector((dbits -1) downto 0);
enable2 : in std_ulogic;
write2 : in std_ulogic);
end;
architecture behav of ec_syncram_dp is
component EC_RAMB8_S1_S1 is port (
DataInA, DataInB: in std_logic_vector(0 downto 0);
AddressA, AddressB: in std_logic_vector(12 downto 0);
ClockA, ClockB: in std_logic;
ClockEnA, ClockEnB: in std_logic;
WrA, WrB: in std_logic;
QA, QB: out std_logic_vector(0 downto 0));
end component;
component EC_RAMB8_S2_S2 is port (
DataInA, DataInB: in std_logic_vector(1 downto 0);
AddressA, AddressB: in std_logic_vector(11 downto 0);
ClockA, ClockB: in std_logic;
ClockEnA, ClockEnB: in std_logic;
WrA, WrB: in std_logic;
QA, QB: out std_logic_vector(1 downto 0));
end component;
component EC_RAMB8_S4_S4 is port (
DataInA, DataInB: in std_logic_vector(3 downto 0);
AddressA, AddressB: in std_logic_vector(10 downto 0);
ClockA, ClockB: in std_logic;
ClockEnA, ClockEnB: in std_logic;
WrA, WrB: in std_logic;
QA, QB: out std_logic_vector(3 downto 0));
end component;
component EC_RAMB8_S9_S9 is port (
DataInA, DataInB: in std_logic_vector(8 downto 0);
AddressA, AddressB: in std_logic_vector(9 downto 0);
ClockA, ClockB: in std_logic;
ClockEnA, ClockEnB: in std_logic;
WrA, WrB: in std_logic;
QA, QB: out std_logic_vector(8 downto 0));
end component;
component EC_RAMB8_S18_S18 is port (
DataInA, DataInB: in std_logic_vector(17 downto 0);
AddressA, AddressB: in std_logic_vector(8 downto 0);
ClockA, ClockB: in std_logic;
ClockEnA, ClockEnB: in std_logic;
WrA, WrB: in std_logic;
QA, QB: out std_logic_vector(17 downto 0));
end component;
constant DMAX : integer := dbits+18;
constant AMAX : integer := 13;
signal gnd, vcc : std_ulogic;
signal do1, do2, di1, di2 : std_logic_vector(DMAX downto 0);
signal addr1, addr2 : std_logic_vector(AMAX downto 0);
begin
gnd <= '0'; vcc <= '1';
dataout1 <= do1(dbits-1 downto 0); dataout2 <= do2(dbits-1 downto 0);
di1(dbits-1 downto 0) <= datain1; di1(DMAX downto dbits) <= (others => '0');
di2(dbits-1 downto 0) <= datain2; di2(DMAX downto dbits) <= (others => '0');
addr1(abits-1 downto 0) <= address1; addr1(AMAX downto abits) <= (others => '0');
addr2(abits-1 downto 0) <= address2; addr2(AMAX downto abits) <= (others => '0');
a9 : if abits <= 9 generate
x : for i in 0 to ((dbits-1)/18) generate
r0 : EC_RAMB8_S18_S18 port map (
di1((i+1)*18-1 downto i*18), di2((i+1)*18-1 downto i*18),
addr1(8 downto 0), addr2(8 downto 0), clk1, clk2,
enable1, enable2, write1, write2,
do1((i+1)*18-1 downto i*18), do2((i+1)*18-1 downto i*18));
end generate;
end generate;
a10 : if abits = 10 generate
x : for i in 0 to ((dbits-1)/9) generate
r0 : EC_RAMB8_S9_S9 port map (
di1((i+1)*9-1 downto i*9), di2((i+1)*9-1 downto i*9),
addr1(9 downto 0), addr2(9 downto 0), clk1, clk2,
enable1, enable2, write1, write2,
do1((i+1)*9-1 downto i*9), do2((i+1)*9-1 downto i*9));
end generate;
end generate;
a11 : if abits = 11 generate
x : for i in 0 to ((dbits-1)/4) generate
r0 : EC_RAMB8_S4_S4 port map (
di1((i+1)*4-1 downto i*4), di2((i+1)*4-1 downto i*4),
addr1(10 downto 0), addr2(10 downto 0), clk1, clk2,
enable1, enable2, write1, write2,
do1((i+1)*4-1 downto i*4), do2((i+1)*4-1 downto i*4));
end generate;
end generate;
a12 : if abits = 12 generate
x : for i in 0 to ((dbits-1)/2) generate
r0 : EC_RAMB8_S2_S2 port map (
di1((i+1)*2-1 downto i*2), di2((i+1)*2-1 downto i*2),
addr1(11 downto 0), addr2(11 downto 0), clk1, clk2,
enable1, enable2, write1, write2,
do1((i+1)*2-1 downto i*2), do2((i+1)*2-1 downto i*2));
end generate;
end generate;
a13 : if abits = 13 generate
x : for i in 0 to ((dbits-1)/1) generate
r0 : EC_RAMB8_S1_S1 port map (
di1((i+1)*1-1 downto i*1), di2((i+1)*1-1 downto i*1),
addr1(12 downto 0), addr2(12 downto 0), clk1, clk2,
enable1, enable2, write1, write2,
do1((i+1)*1-1 downto i*1), do2((i+1)*1-1 downto i*1));
end generate;
end generate;
-- pragma translate_off
unsup : if (abits > 13) generate
x : process
begin
assert false
report "Lattice EC syncram_dp: unsupported memory configuration!"
severity failure;
wait;
end process;
end generate;
-- pragma translate_on
end;
| mit | 36749ea1f21ee2dd0de36f0228366114 | 0.666224 | 4.283314 | false | false | false | false |
Subsets and Splits
No community queries yet
The top public SQL queries from the community will appear here once available.